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Use MODE_BASE_REG_CLASS in legitimize macros.
[official-gcc.git] / gcc / config / arm / arm.h
blob20044f2445a39e2b57049ae4bd849097cd50cd8f
1 /* Definitions of target machine for GNU compiler, for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com)
7 Minor hacks by Nick Clifton (nickc@cygnus.com)
8
9 This file is part of GNU CC.
10
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
14 any later version.
15
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
25
26 #ifndef GCC_ARM_H
27 #define GCC_ARM_H
28
29 #define TARGET_CPU_arm2 0x0000
30 #define TARGET_CPU_arm250 0x0000
31 #define TARGET_CPU_arm3 0x0000
32 #define TARGET_CPU_arm6 0x0001
33 #define TARGET_CPU_arm600 0x0001
34 #define TARGET_CPU_arm610 0x0002
35 #define TARGET_CPU_arm7 0x0001
36 #define TARGET_CPU_arm7m 0x0004
37 #define TARGET_CPU_arm7dm 0x0004
38 #define TARGET_CPU_arm7dmi 0x0004
39 #define TARGET_CPU_arm700 0x0001
40 #define TARGET_CPU_arm710 0x0002
41 #define TARGET_CPU_arm7100 0x0002
42 #define TARGET_CPU_arm7500 0x0002
43 #define TARGET_CPU_arm7500fe 0x1001
44 #define TARGET_CPU_arm7tdmi 0x0008
45 #define TARGET_CPU_arm8 0x0010
46 #define TARGET_CPU_arm810 0x0020
47 #define TARGET_CPU_strongarm 0x0040
48 #define TARGET_CPU_strongarm110 0x0040
49 #define TARGET_CPU_strongarm1100 0x0040
50 #define TARGET_CPU_arm9 0x0080
51 #define TARGET_CPU_arm9tdmi 0x0080
52 #define TARGET_CPU_xscale 0x0100
53 /* Configure didn't specify. */
54 #define TARGET_CPU_generic 0x8000
55
56 typedef enum arm_cond_code
57 {
58 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC,
59 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV
60 }
61 arm_cc;
62
63 extern arm_cc arm_current_cc;
64
65 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1))
66
67 extern int arm_target_label;
68 extern int arm_ccfsm_state;
69 extern struct rtx_def * arm_target_insn;
70 /* Run-time compilation parameters selecting different hardware subsets. */
71 extern int target_flags;
72 /* The floating point instruction architecture, can be 2 or 3 */
73 extern const char * target_fp_name;
74 /* Define the information needed to generate branch insns. This is
75 stored from the compare operation. Note that we can't use "rtx" here
76 since it hasn't been defined! */
77 extern struct rtx_def * arm_compare_op0;
78 extern struct rtx_def * arm_compare_op1;
79 /* The label of the current constant pool. */
80 extern struct rtx_def * pool_vector_label;
81 /* Set to 1 when a return insn is output, this means that the epilogue
82 is not needed. */
83 extern int return_used_this_function;
84 /* Nonzero if the prologue must setup `fp'. */
85 extern int current_function_anonymous_args;
86 \f
87 /* Just in case configure has failed to define anything. */
88 #ifndef TARGET_CPU_DEFAULT
89 #define TARGET_CPU_DEFAULT TARGET_CPU_generic
90 #endif
91
92 /* If the configuration file doesn't specify the cpu, the subtarget may
93 override it. If it doesn't, then default to an ARM6. */
94 #if TARGET_CPU_DEFAULT == TARGET_CPU_generic
95 #undef TARGET_CPU_DEFAULT
96
97 #ifdef SUBTARGET_CPU_DEFAULT
98 #define TARGET_CPU_DEFAULT SUBTARGET_CPU_DEFAULT
99 #else
100 #define TARGET_CPU_DEFAULT TARGET_CPU_arm6
101 #endif
102 #endif
103
104 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm2
105 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_2__"
106 #else
107 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm6 || TARGET_CPU_DEFAULT == TARGET_CPU_arm610 || TARGET_CPU_DEFAULT == TARGET_CPU_arm7500fe
108 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3__"
109 #else
110 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7m
111 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_3M__"
112 #else
113 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm7tdmi || TARGET_CPU_DEFAULT == TARGET_CPU_arm9 || TARGET_CPU_DEFAULT == TARGET_CPU_arm9tdmi
114 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__"
115 #else
116 #if TARGET_CPU_DEFAULT == TARGET_CPU_arm8 || TARGET_CPU_DEFAULT == TARGET_CPU_arm810 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm110 || TARGET_CPU_DEFAULT == TARGET_CPU_strongarm1100
117 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4__"
118 #else
119 #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale
120 #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__"
121 #else
122 Unrecognized value in TARGET_CPU_DEFAULT.
123 #endif
124 #endif
125 #endif
126 #endif
127 #endif
128 #endif
129
130 #undef CPP_SPEC
131 #define CPP_SPEC "\
132 %(cpp_cpu_arch) %(cpp_apcs_pc) %(cpp_float) \
133 %(cpp_endian) %(subtarget_cpp_spec) %(cpp_isa) %(cpp_interwork)"
134
135 #define CPP_ISA_SPEC "%{mthumb:-D__thumb__} %{!mthumb:-D__arm__}"
136
137 /* Set the architecture define -- if -march= is set, then it overrides
138 the -mcpu= setting. */
139 #define CPP_CPU_ARCH_SPEC "\
140 -Acpu=arm -Amachine=arm \
141 %{march=arm2:-D__ARM_ARCH_2__} \
142 %{march=arm250:-D__ARM_ARCH_2__} \
143 %{march=arm3:-D__ARM_ARCH_2__} \
144 %{march=arm6:-D__ARM_ARCH_3__} \
145 %{march=arm600:-D__ARM_ARCH_3__} \
146 %{march=arm610:-D__ARM_ARCH_3__} \
147 %{march=arm7:-D__ARM_ARCH_3__} \
148 %{march=arm700:-D__ARM_ARCH_3__} \
149 %{march=arm710:-D__ARM_ARCH_3__} \
150 %{march=arm720:-D__ARM_ARCH_3__} \
151 %{march=arm7100:-D__ARM_ARCH_3__} \
152 %{march=arm7500:-D__ARM_ARCH_3__} \
153 %{march=arm7500fe:-D__ARM_ARCH_3__} \
154 %{march=arm7m:-D__ARM_ARCH_3M__} \
155 %{march=arm7dm:-D__ARM_ARCH_3M__} \
156 %{march=arm7dmi:-D__ARM_ARCH_3M__} \
157 %{march=arm7tdmi:-D__ARM_ARCH_4T__} \
158 %{march=arm8:-D__ARM_ARCH_4__} \
159 %{march=arm810:-D__ARM_ARCH_4__} \
160 %{march=arm9:-D__ARM_ARCH_4T__} \
161 %{march=arm920:-D__ARM_ARCH_4__} \
162 %{march=arm920t:-D__ARM_ARCH_4T__} \
163 %{march=arm9tdmi:-D__ARM_ARCH_4T__} \
164 %{march=strongarm:-D__ARM_ARCH_4__} \
165 %{march=strongarm110:-D__ARM_ARCH_4__} \
166 %{march=strongarm1100:-D__ARM_ARCH_4__} \
167 %{march=xscale:-D__ARM_ARCH_5TE__} \
168 %{march=xscale:-D__XSCALE__} \
169 %{march=armv2:-D__ARM_ARCH_2__} \
170 %{march=armv2a:-D__ARM_ARCH_2__} \
171 %{march=armv3:-D__ARM_ARCH_3__} \
172 %{march=armv3m:-D__ARM_ARCH_3M__} \
173 %{march=armv4:-D__ARM_ARCH_4__} \
174 %{march=armv4t:-D__ARM_ARCH_4T__} \
175 %{march=armv5:-D__ARM_ARCH_5__} \
176 %{march=armv5t:-D__ARM_ARCH_5T__} \
177 %{march=armv5e:-D__ARM_ARCH_5E__} \
178 %{march=armv5te:-D__ARM_ARCH_5TE__} \
179 %{!march=*: \
180 %{mcpu=arm2:-D__ARM_ARCH_2__} \
181 %{mcpu=arm250:-D__ARM_ARCH_2__} \
182 %{mcpu=arm3:-D__ARM_ARCH_2__} \
183 %{mcpu=arm6:-D__ARM_ARCH_3__} \
184 %{mcpu=arm600:-D__ARM_ARCH_3__} \
185 %{mcpu=arm610:-D__ARM_ARCH_3__} \
186 %{mcpu=arm7:-D__ARM_ARCH_3__} \
187 %{mcpu=arm700:-D__ARM_ARCH_3__} \
188 %{mcpu=arm710:-D__ARM_ARCH_3__} \
189 %{mcpu=arm720:-D__ARM_ARCH_3__} \
190 %{mcpu=arm7100:-D__ARM_ARCH_3__} \
191 %{mcpu=arm7500:-D__ARM_ARCH_3__} \
192 %{mcpu=arm7500fe:-D__ARM_ARCH_3__} \
193 %{mcpu=arm7m:-D__ARM_ARCH_3M__} \
194 %{mcpu=arm7dm:-D__ARM_ARCH_3M__} \
195 %{mcpu=arm7dmi:-D__ARM_ARCH_3M__} \
196 %{mcpu=arm7tdmi:-D__ARM_ARCH_4T__} \
197 %{mcpu=arm8:-D__ARM_ARCH_4__} \
198 %{mcpu=arm810:-D__ARM_ARCH_4__} \
199 %{mcpu=arm9:-D__ARM_ARCH_4T__} \
200 %{mcpu=arm920:-D__ARM_ARCH_4__} \
201 %{mcpu=arm920t:-D__ARM_ARCH_4T__} \
202 %{mcpu=arm9tdmi:-D__ARM_ARCH_4T__} \
203 %{mcpu=strongarm:-D__ARM_ARCH_4__} \
204 %{mcpu=strongarm110:-D__ARM_ARCH_4__} \
205 %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \
206 %{mcpu=xscale:-D__ARM_ARCH_5TE__} \
207 %{mcpu=xscale:-D__XSCALE__} \
208 %{!mcpu*:%(cpp_cpu_arch_default)}} \
209 "
210
211 /* Define __APCS_26__ if the PC also contains the PSR */
212 #define CPP_APCS_PC_SPEC "\
213 %{mapcs-32:%{mapcs-26:%e-mapcs-26 and -mapcs-32 may not be used together} \
214 -D__APCS_32__} \
215 %{mapcs-26:-D__APCS_26__} \
216 %{!mapcs-32: %{!mapcs-26:%(cpp_apcs_pc_default)}} \
217 "
218
219 #ifndef CPP_APCS_PC_DEFAULT_SPEC
220 #define CPP_APCS_PC_DEFAULT_SPEC "-D__APCS_26__"
221 #endif
222
223 #define CPP_FLOAT_SPEC "\
224 %{msoft-float:\
225 %{mhard-float:%e-msoft-float and -mhard_float may not be used together} \
226 -D__SOFTFP__} \
227 %{!mhard-float:%{!msoft-float:%(cpp_float_default)}} \
228 "
229
230 /* Default is hard float, which doesn't define anything */
231 #define CPP_FLOAT_DEFAULT_SPEC ""
232
233 #define CPP_ENDIAN_SPEC "\
234 %{mbig-endian: \
235 %{mlittle-endian: \
236 %e-mbig-endian and -mlittle-endian may not be used together} \
237 -D__ARMEB__ %{mwords-little-endian:-D__ARMWEL__} %{mthumb:-D__THUMBEB__}}\
238 %{mlittle-endian:-D__ARMEL__ %{mthumb:-D__THUMBEL__}} \
239 %{!mlittle-endian:%{!mbig-endian:%(cpp_endian_default)}} \
240 "
241
242 /* Default is little endian. */
243 #define CPP_ENDIAN_DEFAULT_SPEC "-D__ARMEL__ %{mthumb:-D__THUMBEL__}"
244
245 /* Add a define for interworking. Needed when building libgcc.a.
246 This must define __THUMB_INTERWORK__ to the pre-processor if
247 interworking is enabled by default. */
248 #ifndef CPP_INTERWORK_DEFAULT_SPEC
249 #define CPP_INTERWORK_DEFAULT_SPEC ""
250 #endif
251
252 #define CPP_INTERWORK_SPEC " \
253 %{mthumb-interwork: \
254 %{mno-thumb-interwork: %eincompatible interworking options} \
255 -D__THUMB_INTERWORK__} \
256 %{!mthumb-interwork:%{!mno-thumb-interwork:%(cpp_interwork_default)}} \
257 "
258
259 #ifndef CPP_PREDEFINES
260 #define CPP_PREDEFINES ""
261 #endif
262
263 #ifndef CC1_SPEC
264 #define CC1_SPEC ""
265 #endif
266
267 /* This macro defines names of additional specifications to put in the specs
268 that can be used in various specifications like CC1_SPEC. Its definition
269 is an initializer with a subgrouping for each command option.
270
271 Each subgrouping contains a string constant, that defines the
272 specification name, and a string constant that used by the GNU CC driver
273 program.
274
275 Do not define this macro if it does not need to do anything. */
276 #define EXTRA_SPECS \
277 { "cpp_cpu_arch", CPP_CPU_ARCH_SPEC }, \
278 { "cpp_cpu_arch_default", CPP_ARCH_DEFAULT_SPEC }, \
279 { "cpp_apcs_pc", CPP_APCS_PC_SPEC }, \
280 { "cpp_apcs_pc_default", CPP_APCS_PC_DEFAULT_SPEC }, \
281 { "cpp_float", CPP_FLOAT_SPEC }, \
282 { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \
283 { "cpp_endian", CPP_ENDIAN_SPEC }, \
284 { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \
285 { "cpp_isa", CPP_ISA_SPEC }, \
286 { "cpp_interwork", CPP_INTERWORK_SPEC }, \
287 { "cpp_interwork_default", CPP_INTERWORK_DEFAULT_SPEC }, \
288 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
289 SUBTARGET_EXTRA_SPECS
290
291 #ifndef SUBTARGET_EXTRA_SPECS
292 #define SUBTARGET_EXTRA_SPECS
293 #endif
294
295 #ifndef SUBTARGET_CPP_SPEC
296 #define SUBTARGET_CPP_SPEC ""
297 #endif
298 \f
299 /* Run-time Target Specification. */
300 #ifndef TARGET_VERSION
301 #define TARGET_VERSION fputs (" (ARM/generic)", stderr);
302 #endif
303
304 /* Nonzero if the function prologue (and epilogue) should obey
305 the ARM Procedure Call Standard. */
306 #define ARM_FLAG_APCS_FRAME (1 << 0)
307
308 /* Nonzero if the function prologue should output the function name to enable
309 the post mortem debugger to print a backtrace (very useful on RISCOS,
310 unused on RISCiX). Specifying this flag also enables
311 -fno-omit-frame-pointer.
312 XXX Must still be implemented in the prologue. */
313 #define ARM_FLAG_POKE (1 << 1)
314
315 /* Nonzero if floating point instructions are emulated by the FPE, in which
316 case instruction scheduling becomes very uninteresting. */
317 #define ARM_FLAG_FPE (1 << 2)
318
319 /* Nonzero if destined for a processor in 32-bit program mode. Takes out bit
320 that assume restoration of the condition flags when returning from a
321 branch and link (ie a function). */
322 #define ARM_FLAG_APCS_32 (1 << 3)
323
324 /* FLAGS 0x0008 and 0x0010 are now spare (used to be arm3/6 selection). */
325
326 /* Nonzero if stack checking should be performed on entry to each function
327 which allocates temporary variables on the stack. */
328 #define ARM_FLAG_APCS_STACK (1 << 4)
329
330 /* Nonzero if floating point parameters should be passed to functions in
331 floating point registers. */
332 #define ARM_FLAG_APCS_FLOAT (1 << 5)
333
334 /* Nonzero if re-entrant, position independent code should be generated.
335 This is equivalent to -fpic. */
336 #define ARM_FLAG_APCS_REENT (1 << 6)
337
338 /* Nonzero if the MMU will trap unaligned word accesses, so shorts must
339 be loaded using either LDRH or LDRB instructions. */
340 #define ARM_FLAG_MMU_TRAPS (1 << 7)
341
342 /* Nonzero if all floating point instructions are missing (and there is no
343 emulator either). Generate function calls for all ops in this case. */
344 #define ARM_FLAG_SOFT_FLOAT (1 << 8)
345
346 /* Nonzero if we should compile with BYTES_BIG_ENDIAN set to 1. */
347 #define ARM_FLAG_BIG_END (1 << 9)
348
349 /* Nonzero if we should compile for Thumb interworking. */
350 #define ARM_FLAG_INTERWORK (1 << 10)
351
352 /* Nonzero if we should have little-endian words even when compiling for
353 big-endian (for backwards compatibility with older versions of GCC). */
354 #define ARM_FLAG_LITTLE_WORDS (1 << 11)
355
356 /* Nonzero if we need to protect the prolog from scheduling */
357 #define ARM_FLAG_NO_SCHED_PRO (1 << 12)
358
359 /* Nonzero if a call to abort should be generated if a noreturn
360 function tries to return. */
361 #define ARM_FLAG_ABORT_NORETURN (1 << 13)
362
363 /* Nonzero if function prologues should not load the PIC register. */
364 #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14)
365
366 /* Nonzero if all call instructions should be indirect. */
367 #define ARM_FLAG_LONG_CALLS (1 << 15)
368
369 /* Nonzero means that the target ISA is the THUMB, not the ARM. */
370 #define ARM_FLAG_THUMB (1 << 16)
371
372 /* Set if a TPCS style stack frame should be generated, for non-leaf
373 functions, even if they do not need one. */
374 #define THUMB_FLAG_BACKTRACE (1 << 17)
375
376 /* Set if a TPCS style stack frame should be generated, for leaf
377 functions, even if they do not need one. */
378 #define THUMB_FLAG_LEAF_BACKTRACE (1 << 18)
379
380 /* Set if externally visible functions should assume that they
381 might be called in ARM mode, from a non-thumb aware code. */
382 #define THUMB_FLAG_CALLEE_SUPER_INTERWORKING (1 << 19)
383
384 /* Set if calls via function pointers should assume that their
385 destination is non-Thumb aware. */
386 #define THUMB_FLAG_CALLER_SUPER_INTERWORKING (1 << 20)
387
388 #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME)
389 #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE)
390 #define TARGET_FPE (target_flags & ARM_FLAG_FPE)
391 #define TARGET_APCS_32 (target_flags & ARM_FLAG_APCS_32)
392 #define TARGET_APCS_STACK (target_flags & ARM_FLAG_APCS_STACK)
393 #define TARGET_APCS_FLOAT (target_flags & ARM_FLAG_APCS_FLOAT)
394 #define TARGET_APCS_REENT (target_flags & ARM_FLAG_APCS_REENT)
395 #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS)
396 #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT)
397 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
398 #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END)
399 #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK)
400 #define TARGET_LITTLE_WORDS (target_flags & ARM_FLAG_LITTLE_WORDS)
401 #define TARGET_NO_SCHED_PRO (target_flags & ARM_FLAG_NO_SCHED_PRO)
402 #define TARGET_ABORT_NORETURN (target_flags & ARM_FLAG_ABORT_NORETURN)
403 #define TARGET_SINGLE_PIC_BASE (target_flags & ARM_FLAG_SINGLE_PIC_BASE)
404 #define TARGET_LONG_CALLS (target_flags & ARM_FLAG_LONG_CALLS)
405 #define TARGET_THUMB (target_flags & ARM_FLAG_THUMB)
406 #define TARGET_ARM (! TARGET_THUMB)
407 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */
408 #define TARGET_CALLEE_INTERWORKING (target_flags & THUMB_FLAG_CALLEE_SUPER_INTERWORKING)
409 #define TARGET_CALLER_INTERWORKING (target_flags & THUMB_FLAG_CALLER_SUPER_INTERWORKING)
410 #define TARGET_BACKTRACE (leaf_function_p () \
411 ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \
412 : (target_flags & THUMB_FLAG_BACKTRACE))
413
414 /* SUBTARGET_SWITCHES is used to add flags on a per-config basis.
415 Bit 31 is reserved. See riscix.h. */
416 #ifndef SUBTARGET_SWITCHES
417 #define SUBTARGET_SWITCHES
418 #endif
419
420 #define TARGET_SWITCHES \
421 { \
422 {"apcs", ARM_FLAG_APCS_FRAME, "" }, \
423 {"apcs-frame", ARM_FLAG_APCS_FRAME, \
424 N_("Generate APCS conformant stack frames") }, \
425 {"no-apcs-frame", -ARM_FLAG_APCS_FRAME, "" }, \
426 {"poke-function-name", ARM_FLAG_POKE, \
427 N_("Store function names in object code") }, \
428 {"no-poke-function-name", -ARM_FLAG_POKE, "" }, \
429 {"fpe", ARM_FLAG_FPE, "" }, \
430 {"apcs-32", ARM_FLAG_APCS_32, \
431 N_("Use the 32-bit version of the APCS") }, \
432 {"apcs-26", -ARM_FLAG_APCS_32, \
433 N_("Use the 26-bit version of the APCS") }, \
434 {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \
435 {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \
436 {"apcs-float", ARM_FLAG_APCS_FLOAT, \
437 N_("Pass FP arguments in FP registers") }, \
438 {"no-apcs-float", -ARM_FLAG_APCS_FLOAT, "" }, \
439 {"apcs-reentrant", ARM_FLAG_APCS_REENT, \
440 N_("Generate re-entrant, PIC code") }, \
441 {"no-apcs-reentrant", -ARM_FLAG_APCS_REENT, "" }, \
442 {"alignment-traps", ARM_FLAG_MMU_TRAPS, \
443 N_("The MMU will trap on unaligned accesses") }, \
444 {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \
445 {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \
446 {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \
447 {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \
448 {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \
449 {"soft-float", ARM_FLAG_SOFT_FLOAT, \
450 N_("Use library calls to perform FP operations") }, \
451 {"hard-float", -ARM_FLAG_SOFT_FLOAT, \
452 N_("Use hardware floating point instructions") }, \
453 {"big-endian", ARM_FLAG_BIG_END, \
454 N_("Assume target CPU is configured as big endian") }, \
455 {"little-endian", -ARM_FLAG_BIG_END, \
456 N_("Assume target CPU is configured as little endian") }, \
457 {"words-little-endian", ARM_FLAG_LITTLE_WORDS, \
458 N_("Assume big endian bytes, little endian words") }, \
459 {"thumb-interwork", ARM_FLAG_INTERWORK, \
460 N_("Support calls between Thumb and ARM instruction sets") }, \
461 {"no-thumb-interwork", -ARM_FLAG_INTERWORK, "" }, \
462 {"abort-on-noreturn", ARM_FLAG_ABORT_NORETURN, \
463 N_("Generate a call to abort if a noreturn function returns")}, \
464 {"no-abort-on-noreturn", -ARM_FLAG_ABORT_NORETURN, "" }, \
465 {"no-sched-prolog", ARM_FLAG_NO_SCHED_PRO, \
466 N_("Do not move instructions into a function's prologue") }, \
467 {"sched-prolog", -ARM_FLAG_NO_SCHED_PRO, "" }, \
468 {"single-pic-base", ARM_FLAG_SINGLE_PIC_BASE, \
469 N_("Do not load the PIC register in function prologues") }, \
470 {"no-single-pic-base", -ARM_FLAG_SINGLE_PIC_BASE, "" }, \
471 {"long-calls", ARM_FLAG_LONG_CALLS, \
472 N_("Generate call insns as indirect calls, if necessary") }, \
473 {"no-long-calls", -ARM_FLAG_LONG_CALLS, "" }, \
474 {"thumb", ARM_FLAG_THUMB, \
475 N_("Compile for the Thumb not the ARM") }, \
476 {"no-thumb", -ARM_FLAG_THUMB, "" }, \
477 {"arm", -ARM_FLAG_THUMB, "" }, \
478 {"tpcs-frame", THUMB_FLAG_BACKTRACE, \
479 N_("Thumb: Generate (non-leaf) stack frames even if not needed") }, \
480 {"no-tpcs-frame", -THUMB_FLAG_BACKTRACE, "" }, \
481 {"tpcs-leaf-frame", THUMB_FLAG_LEAF_BACKTRACE, \
482 N_("Thumb: Generate (leaf) stack frames even if not needed") }, \
483 {"no-tpcs-leaf-frame", -THUMB_FLAG_LEAF_BACKTRACE, "" }, \
484 {"callee-super-interworking", THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
485 N_("Thumb: Assume non-static functions may be called from ARM code") }, \
486 {"no-callee-super-interworking", -THUMB_FLAG_CALLEE_SUPER_INTERWORKING, \
487 "" }, \
488 {"caller-super-interworking", THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
489 N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \
490 {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \
491 "" }, \
492 SUBTARGET_SWITCHES \
493 {"", TARGET_DEFAULT, "" } \
494 }
495
496 #define TARGET_OPTIONS \
497 { \
498 {"cpu=", & arm_select[0].string, \
499 N_("Specify the name of the target CPU") }, \
500 {"arch=", & arm_select[1].string, \
501 N_("Specify the name of the target architecture") }, \
502 {"tune=", & arm_select[2].string, "" }, \
503 {"fpe=", & target_fp_name, "" }, \
504 {"fp=", & target_fp_name, \
505 N_("Specify the version of the floating point emulator") }, \
506 {"structure-size-boundary=", & structure_size_string, \
507 N_("Specify the minimum bit alignment of structures") }, \
508 {"pic-register=", & arm_pic_register_string, \
509 N_("Specify the register to be used for PIC addressing") } \
510 }
511
512 struct arm_cpu_select
513 {
514 const char * string;
515 const char * name;
516 const struct processors * processors;
517 };
518
519 /* This is a magic array. If the user specifies a command line switch
520 which matches one of the entries in TARGET_OPTIONS then the corresponding
521 string pointer will be set to the value specified by the user. */
522 extern struct arm_cpu_select arm_select[];
523
524 enum prog_mode_type
525 {
526 prog_mode26,
527 prog_mode32
528 };
529
530 /* Recast the program mode class to be the prog_mode attribute */
531 #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode)
532
533 extern enum prog_mode_type arm_prgmode;
534
535 /* What sort of floating point unit do we have? Hardware or software.
536 If software, is it issue 2 or issue 3? */
537 enum floating_point_type
538 {
539 FP_HARD,
540 FP_SOFT2,
541 FP_SOFT3
542 };
543
544 /* Recast the floating point class to be the floating point attribute. */
545 #define arm_fpu_attr ((enum attr_fpu) arm_fpu)
546
547 /* What type of floating point to tune for */
548 extern enum floating_point_type arm_fpu;
549
550 /* What type of floating point instructions are available */
551 extern enum floating_point_type arm_fpu_arch;
552
553 /* Default floating point architecture. Override in sub-target if
554 necessary. */
555 #ifndef FP_DEFAULT
556 #define FP_DEFAULT FP_SOFT2
557 #endif
558
559 /* Nonzero if the processor has a fast multiply insn, and one that does
560 a 64-bit multiply of two 32-bit values. */
561 extern int arm_fast_multiply;
562
563 /* Nonzero if this chip supports the ARM Architecture 4 extensions */
564 extern int arm_arch4;
565
566 /* Nonzero if this chip supports the ARM Architecture 5 extensions */
567 extern int arm_arch5;
568
569 /* Nonzero if this chip supports the ARM Architecture 5E extensions */
570 extern int arm_arch5e;
571
572 /* Nonzero if this chip can benefit from load scheduling. */
573 extern int arm_ld_sched;
574
575 /* Nonzero if generating thumb code. */
576 extern int thumb_code;
577
578 /* Nonzero if this chip is a StrongARM. */
579 extern int arm_is_strong;
580
581 /* Nonzero if this chip is an XScale. */
582 extern int arm_is_xscale;
583
584 /* Nonzero if this chip is an ARM6 or an ARM7. */
585 extern int arm_is_6_or_7;
586
587 #ifndef TARGET_DEFAULT
588 #define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME)
589 #endif
590
591 /* The frame pointer register used in gcc has nothing to do with debugging;
592 that is controlled by the APCS-FRAME option. */
593 #define CAN_DEBUG_WITHOUT_FP
594
595 #undef TARGET_MEM_FUNCTIONS
596 #define TARGET_MEM_FUNCTIONS 1
597
598 #define OVERRIDE_OPTIONS arm_override_options ()
599
600 /* Nonzero if PIC code requires explicit qualifiers to generate
601 PLT and GOT relocs rather than the assembler doing so implicitly.
602 Subtargets can override these if required. */
603 #ifndef NEED_GOT_RELOC
604 #define NEED_GOT_RELOC 0
605 #endif
606 #ifndef NEED_PLT_RELOC
607 #define NEED_PLT_RELOC 0
608 #endif
609
610 /* Nonzero if we need to refer to the GOT with a PC-relative
611 offset. In other words, generate
612
613 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)]
614
615 rather than
616
617 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8)
618
619 The default is true, which matches NetBSD. Subtargets can
620 override this if required. */
621 #ifndef GOT_PCREL
622 #define GOT_PCREL 1
623 #endif
624 \f
625 /* Target machine storage Layout. */
626
627
628 /* Define this macro if it is advisable to hold scalars in registers
629 in a wider mode than that declared by the program. In such cases,
630 the value is constrained to be within the bounds of the declared
631 type, but kept valid in the wider mode. The signedness of the
632 extension may differ from that of the type. */
633
634 /* It is far faster to zero extend chars than to sign extend them */
635
636 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
637 if (GET_MODE_CLASS (MODE) == MODE_INT \
638 && GET_MODE_SIZE (MODE) < 4) \
639 { \
640 if (MODE == QImode) \
641 UNSIGNEDP = 1; \
642 else if (MODE == HImode) \
643 UNSIGNEDP = TARGET_MMU_TRAPS != 0; \
644 (MODE) = SImode; \
645 }
646
647 /* Define this macro if the promotion described by `PROMOTE_MODE'
648 should also be done for outgoing function arguments. */
649 /* This is required to ensure that push insns always push a word. */
650 #define PROMOTE_FUNCTION_ARGS
651
652 /* Define for XFmode extended real floating point support.
653 This will automatically cause REAL_ARITHMETIC to be defined. */
654 /* For the ARM:
655 I think I have added all the code to make this work. Unfortunately,
656 early releases of the floating point emulation code on RISCiX used a
657 different format for extended precision numbers. On my RISCiX box there
658 is a bug somewhere which causes the machine to lock up when running enquire
659 with long doubles. There is the additional aspect that Norcroft C
660 treats long doubles as doubles and we ought to remain compatible.
661 Perhaps someone with an FPA coprocessor and not running RISCiX would like
662 to try this someday. */
663 /* #define LONG_DOUBLE_TYPE_SIZE 96 */
664
665 /* Disable XFmode patterns in md file */
666 #define ENABLE_XF_PATTERNS 0
667
668 /* Define if you don't want extended real, but do want to use the
669 software floating point emulator for REAL_ARITHMETIC and
670 decimal <-> binary conversion. */
671 /* See comment above */
672 #define REAL_ARITHMETIC
673
674 /* Define this if most significant bit is lowest numbered
675 in instructions that operate on numbered bit-fields. */
676 #define BITS_BIG_ENDIAN 0
677
678 /* Define this if most significant byte of a word is the lowest numbered.
679 Most ARM processors are run in little endian mode, so that is the default.
680 If you want to have it run-time selectable, change the definition in a
681 cover file to be TARGET_BIG_ENDIAN. */
682 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0)
683
684 /* Define this if most significant word of a multiword number is the lowest
685 numbered.
686 This is always false, even when in big-endian mode. */
687 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS)
688
689 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based
690 on processor pre-defineds when compiling libgcc2.c. */
691 #if defined(__ARMEB__) && !defined(__ARMWEL__)
692 #define LIBGCC2_WORDS_BIG_ENDIAN 1
693 #else
694 #define LIBGCC2_WORDS_BIG_ENDIAN 0
695 #endif
696
697 /* Define this if most significant word of doubles is the lowest numbered.
698 This is always true, even when in little-endian mode. */
699 #define FLOAT_WORDS_BIG_ENDIAN 1
700
701 /* Number of bits in an addressable storage unit */
702 #define BITS_PER_UNIT 8
703
704 #define BITS_PER_WORD 32
705
706 #define UNITS_PER_WORD 4
707
708 #define POINTER_SIZE 32
709
710 #define PARM_BOUNDARY 32
711
712 #define STACK_BOUNDARY 32
713
714 #define FUNCTION_BOUNDARY 32
715
716 /* The lowest bit is used to indicate Thumb-mode functions, so the
717 vbit must go into the delta field of pointers to member
718 functions. */
719 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
720
721 #define EMPTY_FIELD_BOUNDARY 32
722
723 #define BIGGEST_ALIGNMENT 32
724
725 /* Make strings word-aligned so strcpy from constants will be faster. */
726 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_is_xscale ? 1 : 2)
727
728 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
729 ((TREE_CODE (EXP) == STRING_CST \
730 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \
731 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN))
732
733 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the
734 value set in previous versions of this toolchain was 8, which produces more
735 compact structures. The command line option -mstructure_size_boundary=<n>
736 can be used to change this value. For compatibility with the ARM SDK
737 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI
738 0020D) page 2-20 says "Structures are aligned on word boundaries". */
739 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary
740 extern int arm_structure_size_boundary;
741
742 /* This is the value used to initialise arm_structure_size_boundary. If a
743 particular arm target wants to change the default value it should change
744 the definition of this macro, not STRUCTRUE_SIZE_BOUNDARY. See netbsd.h
745 for an example of this. */
746 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY
747 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32
748 #endif
749
750 /* Used when parsing command line option -mstructure_size_boundary. */
751 extern const char * structure_size_string;
752
753 /* Non-zero if move instructions will actually fail to work
754 when given unaligned data. */
755 #define STRICT_ALIGNMENT 1
756
757 #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
758
759 \f
760 /* Standard register usage. */
761
762 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX):
763 (S - saved over call).
764
765 r0 * argument word/integer result
766 r1-r3 argument word
767
768 r4-r8 S register variable
769 r9 S (rfp) register variable (real frame pointer)
770
771 r10 F S (sl) stack limit (used by -mapcs-stack-check)
772 r11 F S (fp) argument pointer
773 r12 (ip) temp workspace
774 r13 F S (sp) lower end of current stack frame
775 r14 (lr) link address/workspace
776 r15 F (pc) program counter
777
778 f0 floating point result
779 f1-f3 floating point scratch
780
781 f4-f7 S floating point variable
782
783 cc This is NOT a real register, but is used internally
784 to represent things that use or set the condition
785 codes.
786 sfp This isn't either. It is used during rtl generation
787 since the offset between the frame pointer and the
788 auto's isn't known until after register allocation.
789 afp Nor this, we only need this because of non-local
790 goto. Without it fp appears to be used and the
791 elimination code won't get rid of sfp. It tracks
792 fp exactly at all times.
793
794 *: See CONDITIONAL_REGISTER_USAGE */
795
796 /* The stack backtrace structure is as follows:
797 fp points to here: | save code pointer | [fp]
798 | return link value | [fp, #-4]
799 | return sp value | [fp, #-8]
800 | return fp value | [fp, #-12]
801 [| saved r10 value |]
802 [| saved r9 value |]
803 [| saved r8 value |]
804 [| saved r7 value |]
805 [| saved r6 value |]
806 [| saved r5 value |]
807 [| saved r4 value |]
808 [| saved r3 value |]
809 [| saved r2 value |]
810 [| saved r1 value |]
811 [| saved r0 value |]
812 [| saved f7 value |] three words
813 [| saved f6 value |] three words
814 [| saved f5 value |] three words
815 [| saved f4 value |] three words
816 r0-r3 are not normally saved in a C function. */
817
818 /* 1 for registers that have pervasive standard uses
819 and are not available for the register allocator. */
820 #define FIXED_REGISTERS \
821 { \
822 0,0,0,0,0,0,0,0, \
823 0,0,0,0,0,1,0,1, \
824 0,0,0,0,0,0,0,0, \
825 1,1,1 \
826 }
827
828 /* 1 for registers not available across function calls.
829 These must include the FIXED_REGISTERS and also any
830 registers that can be used without being saved.
831 The latter must include the registers where values are returned
832 and the register where structure-value addresses are passed.
833 Aside from that, you can include as many other registers as you like.
834 The CC is not preserved over function calls on the ARM 6, so it is
835 easier to assume this for all. SFP is preserved, since FP is. */
836 #define CALL_USED_REGISTERS \
837 { \
838 1,1,1,1,0,0,0,0, \
839 0,0,0,0,1,1,1,1, \
840 1,1,1,1,0,0,0,0, \
841 1,1,1 \
842 }
843
844 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE
845 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE
846 #endif
847
848 #define CONDITIONAL_REGISTER_USAGE \
849 { \
850 if (TARGET_SOFT_FLOAT || TARGET_THUMB) \
851 { \
852 int regno; \
853 for (regno = FIRST_ARM_FP_REGNUM; \
854 regno <= LAST_ARM_FP_REGNUM; ++regno) \
855 fixed_regs[regno] = call_used_regs[regno] = 1; \
856 } \
857 if (flag_pic) \
858 { \
859 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
860 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
861 } \
862 else if (TARGET_APCS_STACK) \
863 { \
864 fixed_regs[10] = 1; \
865 call_used_regs[10] = 1; \
866 } \
867 if (TARGET_APCS_FRAME) \
868 { \
869 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
870 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \
871 } \
872 SUBTARGET_CONDITIONAL_REGISTER_USAGE \
873 }
874
875 /* These are a couple of extensions to the formats accecpted
876 by asm_fprintf:
877 %@ prints out ASM_COMMENT_START
878 %r prints out REGISTER_PREFIX reg_names[arg] */
879 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \
880 case '@': \
881 fputs (ASM_COMMENT_START, FILE); \
882 break; \
883 \
884 case 'r': \
885 fputs (REGISTER_PREFIX, FILE); \
886 fputs (reg_names [va_arg (ARGS, int)], FILE); \
887 break;
888
889 /* Round X up to the nearest word. */
890 #define ROUND_UP(X) (((X) + 3) & ~3)
891
892 /* Convert fron bytes to ints. */
893 #define NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
894
895 /* The number of (integer) registers required to hold a quantity of type MODE. */
896 #define NUM_REGS(MODE) \
897 NUM_INTS (GET_MODE_SIZE (MODE))
898
899 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */
900 #define NUM_REGS2(MODE, TYPE) \
901 NUM_INTS ((MODE) == BLKmode ? \
902 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE))
903
904 /* The number of (integer) argument register available. */
905 #define NUM_ARG_REGS 4
906
907 /* Return the regiser number of the N'th (integer) argument. */
908 #define ARG_REGISTER(N) (N - 1)
909
910 #if 0 /* FIXME: The ARM backend has special code to handle structure
911 returns, and will reserve its own hidden first argument. So
912 if this macro is enabled a *second* hidden argument will be
913 reserved, which will break binary compatibility with old
914 toolchains and also thunk handling. One day this should be
915 fixed. */
916 /* RTX for structure returns. NULL means use a hidden first argument. */
917 #define STRUCT_VALUE 0
918 #else
919 /* Register in which address to store a structure value
920 is passed to a function. */
921 #define STRUCT_VALUE_REGNUM ARG_REGISTER (1)
922 #endif
923
924 /* Specify the registers used for certain standard purposes.
925 The values of these macros are register numbers. */
926
927 /* The number of the last argument register. */
928 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS)
929
930 /* The number of the last "lo" register (thumb). */
931 #define LAST_LO_REGNUM 7
932
933 /* The register that holds the return address in exception handlers. */
934 #define EXCEPTION_LR_REGNUM 2
935
936 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain
937 as an invisible last argument (possible since varargs don't exist in
938 Pascal), so the following is not true. */
939 #define STATIC_CHAIN_REGNUM (TARGET_ARM ? 12 : 9)
940
941 /* Define this to be where the real frame pointer is if it is not possible to
942 work out the offset between the frame pointer and the automatic variables
943 until after register allocation has taken place. FRAME_POINTER_REGNUM
944 should point to a special register that we will make sure is eliminated.
945
946 For the Thumb we have another problem. The TPCS defines the frame pointer
947 as r11, and GCC belives that it is always possible to use the frame pointer
948 as base register for addressing purposes. (See comments in
949 find_reloads_address()). But - the Thumb does not allow high registers,
950 including r11, to be used as base address registers. Hence our problem.
951
952 The solution used here, and in the old thumb port is to use r7 instead of
953 r11 as the hard frame pointer and to have special code to generate
954 backtrace structures on the stack (if required to do so via a command line
955 option) using r11. This is the only 'user visable' use of r11 as a frame
956 pointer. */
957 #define ARM_HARD_FRAME_POINTER_REGNUM 11
958 #define THUMB_HARD_FRAME_POINTER_REGNUM 7
959
960 #define HARD_FRAME_POINTER_REGNUM \
961 (TARGET_ARM \
962 ? ARM_HARD_FRAME_POINTER_REGNUM \
963 : THUMB_HARD_FRAME_POINTER_REGNUM)
964
965 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM
966
967 /* Register to use for pushing function arguments. */
968 #define STACK_POINTER_REGNUM SP_REGNUM
969
970 /* ARM floating pointer registers. */
971 #define FIRST_ARM_FP_REGNUM 16
972 #define LAST_ARM_FP_REGNUM 23
973
974 /* Base register for access to local variables of the function. */
975 #define FRAME_POINTER_REGNUM 25
976
977 /* Base register for access to arguments of the function. */
978 #define ARG_POINTER_REGNUM 26
979
980 /* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */
981 #define FIRST_PSEUDO_REGISTER 27
982
983 /* Value should be nonzero if functions must have frame pointers.
984 Zero means the frame pointer need not be set up (and parms may be accessed
985 via the stack pointer) in functions that seem suitable.
986 If we have to have a frame pointer we might as well make use of it.
987 APCS says that the frame pointer does not need to be pushed in leaf
988 functions, or simple tail call functions. */
989 #define FRAME_POINTER_REQUIRED \
990 (current_function_has_nonlocal_label \
991 || (TARGET_ARM && TARGET_APCS_FRAME && ! leaf_function_p ()))
992
993 /* Return number of consecutive hard regs needed starting at reg REGNO
994 to hold something of mode MODE.
995 This is ordinarily the length in words of a value of mode MODE
996 but can be less for certain modes in special long registers.
997
998 On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP
999 mode. */
1000 #define HARD_REGNO_NREGS(REGNO, MODE) \
1001 ((TARGET_ARM \
1002 && REGNO >= FIRST_ARM_FP_REGNUM \
1003 && REGNO != FRAME_POINTER_REGNUM \
1004 && REGNO != ARG_POINTER_REGNUM) \
1005 ? 1 : NUM_REGS (MODE))
1006
1007 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
1008 This is TRUE for ARM regs since they can hold anything, and TRUE for FPU
1009 regs holding FP.
1010 For the Thumb we only allow values bigger than SImode in registers 0 - 6,
1011 so that there is always a second lo register available to hold the upper
1012 part of the value. Probably we ought to ensure that the register is the
1013 start of an even numbered register pair. */
1014 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1015 (TARGET_ARM ? \
1016 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
1017 ( REGNO <= LAST_ARM_REGNUM \
1018 || REGNO == FRAME_POINTER_REGNUM \
1019 || REGNO == ARG_POINTER_REGNUM \
1020 || GET_MODE_CLASS (MODE) == MODE_FLOAT)) \
1021 : \
1022 ((GET_MODE_CLASS (MODE) == MODE_CC) ? (REGNO == CC_REGNUM) : \
1023 (NUM_REGS (MODE) < 2 || REGNO < LAST_LO_REGNUM)))
1024
1025 /* Value is 1 if it is a good idea to tie two pseudo registers
1026 when one has mode MODE1 and one has mode MODE2.
1027 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1028 for any hard reg, then this must be 0 for correct output. */
1029 #define MODES_TIEABLE_P(MODE1, MODE2) \
1030 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
1031
1032 /* The order in which register should be allocated. It is good to use ip
1033 since no saving is required (though calls clobber it) and it never contains
1034 function parameters. It is quite good to use lr since other calls may
1035 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is
1036 least likely to contain a function parameter; in addition results are
1037 returned in r0. */
1038 #define REG_ALLOC_ORDER \
1039 { \
1040 3, 2, 1, 0, 12, 14, 4, 5, \
1041 6, 7, 8, 10, 9, 11, 13, 15, \
1042 16, 17, 18, 19, 20, 21, 22, 23, \
1043 24, 25, 26 \
1044 }
1045 \f
1046 /* Register and constant classes. */
1047
1048 /* Register classes: used to be simple, just all ARM regs or all FPU regs
1049 Now that the Thumb is involved it has become more complicated. */
1050 enum reg_class
1051 {
1052 NO_REGS,
1053 FPU_REGS,
1054 LO_REGS,
1055 STACK_REG,
1056 BASE_REGS,
1057 HI_REGS,
1058 CC_REG,
1059 GENERAL_REGS,
1060 ALL_REGS,
1061 LIM_REG_CLASSES
1062 };
1063
1064 #define N_REG_CLASSES (int) LIM_REG_CLASSES
1065
1066 /* Give names of register classes as strings for dump file. */
1067 #define REG_CLASS_NAMES \
1068 { \
1069 "NO_REGS", \
1070 "FPU_REGS", \
1071 "LO_REGS", \
1072 "STACK_REG", \
1073 "BASE_REGS", \
1074 "HI_REGS", \
1075 "CC_REG", \
1076 "GENERAL_REGS", \
1077 "ALL_REGS", \
1078 }
1079
1080 /* Define which registers fit in which classes.
1081 This is an initializer for a vector of HARD_REG_SET
1082 of length N_REG_CLASSES. */
1083 #define REG_CLASS_CONTENTS \
1084 { \
1085 { 0x0000000 }, /* NO_REGS */ \
1086 { 0x0FF0000 }, /* FPU_REGS */ \
1087 { 0x00000FF }, /* LO_REGS */ \
1088 { 0x0002000 }, /* STACK_REG */ \
1089 { 0x00020FF }, /* BASE_REGS */ \
1090 { 0x000FF00 }, /* HI_REGS */ \
1091 { 0x1000000 }, /* CC_REG */ \
1092 { 0x200FFFF }, /* GENERAL_REGS */ \
1093 { 0x2FFFFFF } /* ALL_REGS */ \
1094 }
1095
1096 /* The same information, inverted:
1097 Return the class number of the smallest class containing
1098 reg number REGNO. This could be a conditional expression
1099 or could index an array. */
1100 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO)
1101
1102 /* The class value for index registers, and the one for base regs. */
1103 #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS)
1104 #define BASE_REG_CLASS (TARGET_THUMB ? BASE_REGS : GENERAL_REGS)
1105
1106 /* For the Thumb the high registers cannot be used as base
1107 registers when addressing quanitities in QI or HI mode. */
1108 #define MODE_BASE_REG_CLASS(MODE) \
1109 (TARGET_ARM ? BASE_REGS : \
1110 (((MODE) == QImode || (MODE) == HImode || (MODE) == VOIDmode) \
1111 ? LO_REGS : BASE_REGS))
1112
1113 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
1114 registers explicitly used in the rtl to be used as spill registers
1115 but prevents the compiler from extending the lifetime of these
1116 registers. */
1117 #define SMALL_REGISTER_CLASSES TARGET_THUMB
1118
1119 /* Get reg_class from a letter such as appears in the machine description.
1120 We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS) for the
1121 ARM, but several more letters for the Thumb. */
1122 #define REG_CLASS_FROM_LETTER(C) \
1123 ( (C) == 'f' ? FPU_REGS \
1124 : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \
1125 : TARGET_ARM ? NO_REGS \
1126 : (C) == 'h' ? HI_REGS \
1127 : (C) == 'b' ? BASE_REGS \
1128 : (C) == 'k' ? STACK_REG \
1129 : (C) == 'c' ? CC_REG \
1130 : NO_REGS)
1131
1132 /* The letters I, J, K, L and M in a register constraint string
1133 can be used to stand for particular ranges of immediate operands.
1134 This macro defines what the ranges are.
1135 C is the letter, and VALUE is a constant value.
1136 Return 1 if VALUE is in the range specified by C.
1137 I: immediate arithmetic operand (i.e. 8 bits shifted as required).
1138 J: valid indexing constants.
1139 K: ~value ok in rhs argument of data operand.
1140 L: -value ok in rhs argument of data operand.
1141 M: 0..32, or a power of 2 (for shifts, or mult done by shift). */
1142 #define CONST_OK_FOR_ARM_LETTER(VALUE, C) \
1143 ((C) == 'I' ? const_ok_for_arm (VALUE) : \
1144 (C) == 'J' ? ((VALUE) < 4096 && (VALUE) > -4096) : \
1145 (C) == 'K' ? (const_ok_for_arm (~(VALUE))) : \
1146 (C) == 'L' ? (const_ok_for_arm (-(VALUE))) : \
1147 (C) == 'M' ? (((VALUE >= 0 && VALUE <= 32)) \
1148 || (((VALUE) & ((VALUE) - 1)) == 0)) \
1149 : 0)
1150
1151 #define CONST_OK_FOR_THUMB_LETTER(VAL, C) \
1152 ((C) == 'I' ? (unsigned HOST_WIDE_INT) (VAL) < 256 : \
1153 (C) == 'J' ? (VAL) > -256 && (VAL) < 0 : \
1154 (C) == 'K' ? thumb_shiftable_const (VAL) : \
1155 (C) == 'L' ? (VAL) > -8 && (VAL) < 8 : \
1156 (C) == 'M' ? ((unsigned HOST_WIDE_INT) (VAL) < 1024 \
1157 && ((VAL) & 3) == 0) : \
1158 (C) == 'N' ? ((unsigned HOST_WIDE_INT) (VAL) < 32) : \
1159 (C) == 'O' ? ((VAL) >= -508 && (VAL) <= 508) \
1160 : 0)
1161
1162 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1163 (TARGET_ARM ? \
1164 CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C))
1165
1166 /* Constant letter 'G' for the FPU immediate constants.
1167 'H' means the same constant negated. */
1168 #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \
1169 ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) : \
1170 (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0)
1171
1172 #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \
1173 (TARGET_ARM ? \
1174 CONST_DOUBLE_OK_FOR_ARM_LETTER (X, C) : 0)
1175
1176 /* For the ARM, `Q' means that this is a memory operand that is just
1177 an offset from a register.
1178 `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL
1179 address. This means that the symbol is in the text segment and can be
1180 accessed without using a load. */
1181
1182 #define EXTRA_CONSTRAINT_ARM(OP, C) \
1183 ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \
1184 (C) == 'R' ? (GET_CODE (OP) == MEM \
1185 && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \
1186 && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \
1187 (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \
1188 : 0)
1189
1190 #define EXTRA_CONSTRAINT_THUMB(X, C) \
1191 ((C) == 'Q' ? (GET_CODE (X) == MEM \
1192 && GET_CODE (XEXP (X, 0)) == LABEL_REF) : 0)
1193
1194 #define EXTRA_CONSTRAINT(X, C) \
1195 (TARGET_ARM ? \
1196 EXTRA_CONSTRAINT_ARM (X, C) : EXTRA_CONSTRAINT_THUMB (X, C))
1197
1198 /* Given an rtx X being reloaded into a reg required to be
1199 in class CLASS, return the class of reg to actually use.
1200 In general this is just CLASS, but for the Thumb we prefer
1201 a LO_REGS class or a subset. */
1202 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
1203 (TARGET_ARM ? (CLASS) : \
1204 ((CLASS) == BASE_REGS ? (CLASS) : LO_REGS))
1205
1206 /* Must leave BASE_REGS reloads alone */
1207 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1208 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \
1209 ? ((true_regnum (X) == -1 ? LO_REGS \
1210 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1211 : NO_REGS)) \
1212 : NO_REGS)
1213
1214 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1215 ((CLASS) != LO_REGS \
1216 ? ((true_regnum (X) == -1 ? LO_REGS \
1217 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \
1218 : NO_REGS)) \
1219 : NO_REGS)
1220
1221 /* Return the register class of a scratch register needed to copy IN into
1222 or out of a register in CLASS in MODE. If it can be done directly,
1223 NO_REGS is returned. */
1224 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
1225 (TARGET_ARM ? \
1226 (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \
1227 ? GENERAL_REGS : NO_REGS) \
1228 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X))
1229
1230 /* If we need to load shorts byte-at-a-time, then we need a scratch. */
1231 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
1232 (TARGET_ARM ? \
1233 (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \
1234 && (GET_CODE (X) == MEM \
1235 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
1236 && true_regnum (X) == -1))) \
1237 ? GENERAL_REGS : NO_REGS) \
1238 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))
1239
1240 /* Try a machine-dependent way of reloading an illegitimate address
1241 operand. If we find one, push the reload and jump to WIN. This
1242 macro is used in only one place: `find_reloads_address' in reload.c.
1243
1244 For the ARM, we wish to handle large displacements off a base
1245 register by splitting the addend across a MOV and the mem insn.
1246 This can cut the number of reloads needed. */
1247 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \
1248 do \
1249 { \
1250 if (GET_CODE (X) == PLUS \
1251 && GET_CODE (XEXP (X, 0)) == REG \
1252 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \
1253 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \
1254 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
1255 { \
1256 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
1257 HOST_WIDE_INT low, high; \
1258 \
1259 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
1260 low = ((val & 0xf) ^ 0x8) - 0x8; \
1261 else if (MODE == SImode \
1262 || (MODE == SFmode && TARGET_SOFT_FLOAT) \
1263 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \
1264 /* Need to be careful, -4096 is not a valid offset. */ \
1265 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \
1266 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \
1267 /* Need to be careful, -256 is not a valid offset. */ \
1268 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \
1269 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1270 && TARGET_HARD_FLOAT) \
1271 /* Need to be careful, -1024 is not a valid offset. */ \
1272 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \
1273 else \
1274 break; \
1275 \
1276 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \
1277 ^ (unsigned HOST_WIDE_INT) 0x80000000) \
1278 - (unsigned HOST_WIDE_INT) 0x80000000); \
1279 /* Check for overflow or zero */ \
1280 if (low == 0 || high == 0 || (high + low != val)) \
1281 break; \
1282 \
1283 /* Reload the high part into a base reg; leave the low part \
1284 in the mem. */ \
1285 X = gen_rtx_PLUS (GET_MODE (X), \
1286 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \
1287 GEN_INT (high)), \
1288 GEN_INT (low)); \
1289 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \
1290 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \
1291 VOIDmode, 0, 0, OPNUM, TYPE); \
1292 goto WIN; \
1293 } \
1294 } \
1295 while (0)
1296
1297 /* ??? If an HImode FP+large_offset address is converted to an HImode
1298 SP+large_offset address, then reload won't know how to fix it. It sees
1299 only that SP isn't valid for HImode, and so reloads the SP into an index
1300 register, but the resulting address is still invalid because the offset
1301 is too big. We fix it here instead by reloading the entire address. */
1302 /* We could probably achieve better results by defining PROMOTE_MODE to help
1303 cope with the variances between the Thumb's signed and unsigned byte and
1304 halfword load instructions. */
1305 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1306 { \
1307 if (GET_CODE (X) == PLUS \
1308 && GET_MODE_SIZE (MODE) < 4 \
1309 && GET_CODE (XEXP (X, 0)) == REG \
1310 && XEXP (X, 0) == stack_pointer_rtx \
1311 && GET_CODE (XEXP (X, 1)) == CONST_INT \
1312 && ! THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
1313 { \
1314 rtx orig_X = X; \
1315 X = copy_rtx (X); \
1316 push_reload (orig_X, NULL_RTX, &X, NULL, \
1317 MODE_BASE_REG_CLASS (MODE), \
1318 Pmode, VOIDmode, 0, 0, OPNUM, TYPE); \
1319 goto WIN; \
1320 } \
1321 }
1322
1323 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \
1324 if (TARGET_ARM) \
1325 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \
1326 else \
1327 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN)
1328
1329 /* Return the maximum number of consecutive registers
1330 needed to represent mode MODE in a register of class CLASS.
1331 ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */
1332 #define CLASS_MAX_NREGS(CLASS, MODE) \
1333 ((CLASS) == FPU_REGS ? 1 : NUM_REGS (MODE))
1334
1335 /* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */
1336 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
1337 (TARGET_ARM ? \
1338 ((FROM) == FPU_REGS && (TO) != FPU_REGS ? 20 : \
1339 (FROM) != FPU_REGS && (TO) == FPU_REGS ? 20 : 2) \
1340 : \
1341 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2)
1342 \f
1343 /* Stack layout; function entry, exit and calling. */
1344
1345 /* Define this if pushing a word on the stack
1346 makes the stack pointer a smaller address. */
1347 #define STACK_GROWS_DOWNWARD 1
1348
1349 /* Define this if the nominal address of the stack frame
1350 is at the high-address end of the local variables;
1351 that is, each additional local variable allocated
1352 goes at a more negative offset in the frame. */
1353 #define FRAME_GROWS_DOWNWARD 1
1354
1355 /* Offset within stack frame to start allocating local variables at.
1356 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1357 first local allocated. Otherwise, it is the offset to the BEGINNING
1358 of the first local allocated. */
1359 #define STARTING_FRAME_OFFSET 0
1360
1361 /* If we generate an insn to push BYTES bytes,
1362 this says how many the stack pointer really advances by. */
1363 /* The push insns do not do this rounding implicitly.
1364 So don't define this. */
1365 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP (NPUSHED) */
1366
1367 /* Define this if the maximum size of all the outgoing args is to be
1368 accumulated and pushed during the prologue. The amount can be
1369 found in the variable current_function_outgoing_args_size. */
1370 #define ACCUMULATE_OUTGOING_ARGS 1
1371
1372 /* Offset of first parameter from the argument pointer register value. */
1373 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0)
1374
1375 /* Value is the number of byte of arguments automatically
1376 popped when returning from a subroutine call.
1377 FUNDECL is the declaration node of the function (as a tree),
1378 FUNTYPE is the data type of the function (as a tree),
1379 or for a library call it is an identifier node for the subroutine name.
1380 SIZE is the number of bytes of arguments passed on the stack.
1381
1382 On the ARM, the caller does not pop any of its arguments that were passed
1383 on the stack. */
1384 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0
1385
1386 /* Define how to find the value returned by a library function
1387 assuming the value has mode MODE. */
1388 #define LIBCALL_VALUE(MODE) \
1389 (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \
1390 ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \
1391 : gen_rtx_REG (MODE, ARG_REGISTER (1)))
1392
1393 /* Define how to find the value returned by a function.
1394 VALTYPE is the data type of the value (as a tree).
1395 If the precise function being called is known, FUNC is its FUNCTION_DECL;
1396 otherwise, FUNC is 0. */
1397 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1398 LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1399
1400 /* 1 if N is a possible register number for a function value.
1401 On the ARM, only r0 and f0 can return results. */
1402 #define FUNCTION_VALUE_REGNO_P(REGNO) \
1403 ((REGNO) == ARG_REGISTER (1) \
1404 || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT))
1405
1406 /* How large values are returned */
1407 /* A C expression which can inhibit the returning of certain function values
1408 in registers, based on the type of value. */
1409 #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE)
1410
1411 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return
1412 values must be in memory. On the ARM, they need only do so if larger
1413 than a word, or if they contain elements offset from zero in the struct. */
1414 #define DEFAULT_PCC_STRUCT_RETURN 0
1415
1416 /* Flags for the call/call_value rtl operations set up by function_arg. */
1417 #define CALL_NORMAL 0x00000000 /* No special processing. */
1418 #define CALL_LONG 0x00000001 /* Always call indirect. */
1419 #define CALL_SHORT 0x00000002 /* Never call indirect. */
1420
1421 /* These bits describe the different types of function supported
1422 by the ARM backend. They are exclusive. ie a function cannot be both a
1423 normal function and an interworked function, for example. Knowing the
1424 type of a function is important for determining its prologue and
1425 epilogue sequences.
1426 Note value 7 is currently unassigned. Also note that the interrupt
1427 function types all have bit 2 set, so that they can be tested for easily.
1428 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the
1429 machine_function structure is initialised (to zero) func_type will
1430 default to unknown. This will force the first use of arm_current_func_type
1431 to call arm_compute_func_type. */
1432 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */
1433 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */
1434 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */
1435 #define ARM_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */
1436 #define ARM_FT_ISR 4 /* An interrupt service routine. */
1437 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */
1438 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */
1439
1440 #define ARM_FT_TYPE_MASK ((1 << 3) - 1)
1441
1442 /* In addition functions can have several type modifiers,
1443 outlined by these bit masks: */
1444 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */
1445 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */
1446 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */
1447 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */
1448
1449 /* Some macros to test these flags. */
1450 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK)
1451 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT)
1452 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE)
1453 #define IS_NAKED(t) (t & ARM_FT_NAKED)
1454 #define IS_NESTED(t) (t & ARM_FT_NESTED)
1455
1456 /* A C structure for machine-specific, per-function data.
1457 This is added to the cfun structure. */
1458 typedef struct machine_function
1459 {
1460 /* Additionsl stack adjustment in __builtin_eh_throw. */
1461 struct rtx_def *eh_epilogue_sp_ofs;
1462 /* Records if LR has to be saved for far jumps. */
1463 int far_jump_used;
1464 /* Records if ARG_POINTER was ever live. */
1465 int arg_pointer_live;
1466 /* Records if the save of LR has been eliminated. */
1467 int lr_save_eliminated;
1468 /* Records the type of the current function. */
1469 unsigned long func_type;
1470 }
1471 machine_function;
1472
1473 /* A C type for declaring a variable that is used as the first argument of
1474 `FUNCTION_ARG' and other related values. For some target machines, the
1475 type `int' suffices and can hold the number of bytes of argument so far. */
1476 typedef struct
1477 {
1478 /* This is the number of registers of arguments scanned so far. */
1479 int nregs;
1480 /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT . */
1481 int call_cookie;
1482 } CUMULATIVE_ARGS;
1483
1484 /* Define where to put the arguments to a function.
1485 Value is zero to push the argument on the stack,
1486 or a hard register in which to store the argument.
1487
1488 MODE is the argument's machine mode.
1489 TYPE is the data type of the argument (as a tree).
1490 This is null for libcalls where that information may
1491 not be available.
1492 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1493 the preceding args and about the function being called.
1494 NAMED is nonzero if this argument is a named parameter
1495 (otherwise it is an extra parameter matching an ellipsis).
1496
1497 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all
1498 other arguments are passed on the stack. If (NAMED == 0) (which happens
1499 only in assign_parms, since SETUP_INCOMING_VARARGS is defined), say it is
1500 passed in the stack (function_prologue will indeed make it pass in the
1501 stack if necessary). */
1502 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1503 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED))
1504
1505 /* For an arg passed partly in registers and partly in memory,
1506 this is the number of registers used.
1507 For args passed entirely in registers or entirely in memory, zero. */
1508 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1509 ( NUM_ARG_REGS > (CUM).nregs \
1510 && (NUM_ARG_REGS < ((CUM).nregs + NUM_REGS2 (MODE, TYPE))) \
1511 ? NUM_ARG_REGS - (CUM).nregs : 0)
1512
1513 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1514 for a call to a function whose data type is FNTYPE.
1515 For a library call, FNTYPE is 0.
1516 On the ARM, the offset starts at 0. */
1517 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \
1518 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT))
1519
1520 /* Update the data in CUM to advance over an argument
1521 of mode MODE and data type TYPE.
1522 (TYPE is null for libcalls where that information may not be available.) */
1523 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1524 (CUM).nregs += NUM_REGS2 (MODE, TYPE)
1525
1526 /* 1 if N is a possible register number for function argument passing.
1527 On the ARM, r0-r3 are used to pass args. */
1528 #define FUNCTION_ARG_REGNO_P(REGNO) (IN_RANGE ((REGNO), 0, 3))
1529
1530 \f
1531 /* Tail calling. */
1532
1533 /* A C expression that evaluates to true if it is ok to perform a sibling
1534 call to DECL. */
1535 #define FUNCTION_OK_FOR_SIBCALL(DECL) arm_function_ok_for_sibcall ((DECL))
1536
1537 /* Perform any actions needed for a function that is receiving a variable
1538 number of arguments. CUM is as above. MODE and TYPE are the mode and type
1539 of the current parameter. PRETEND_SIZE is a variable that should be set to
1540 the amount of stack that must be pushed by the prolog to pretend that our
1541 caller pushed it.
1542
1543 Normally, this macro will push all remaining incoming registers on the
1544 stack and set PRETEND_SIZE to the length of the registers pushed.
1545
1546 On the ARM, PRETEND_SIZE is set in order to have the prologue push the last
1547 named arg and all anonymous args onto the stack.
1548 XXX I know the prologue shouldn't be pushing registers, but it is faster
1549 that way. */
1550 #define SETUP_INCOMING_VARARGS(CUM, MODE, TYPE, PRETEND_SIZE, NO_RTL) \
1551 { \
1552 extern int current_function_anonymous_args; \
1553 current_function_anonymous_args = 1; \
1554 if ((CUM).nregs < NUM_ARG_REGS) \
1555 (PRETEND_SIZE) = (NUM_ARG_REGS - (CUM).nregs) * UNITS_PER_WORD; \
1556 }
1557
1558 /* If your target environment doesn't prefix user functions with an
1559 underscore, you may wish to re-define this to prevent any conflicts.
1560 e.g. AOF may prefix mcount with an underscore. */
1561 #ifndef ARM_MCOUNT_NAME
1562 #define ARM_MCOUNT_NAME "*mcount"
1563 #endif
1564
1565 /* Call the function profiler with a given profile label. The Acorn
1566 compiler puts this BEFORE the prolog but gcc puts it afterwards.
1567 On the ARM the full profile code will look like:
1568 .data
1569 LP1
1570 .word 0
1571 .text
1572 mov ip, lr
1573 bl mcount
1574 .word LP1
1575
1576 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER
1577 will output the .text section.
1578
1579 The ``mov ip,lr'' seems like a good idea to stick with cc convention.
1580 ``prof'' doesn't seem to mind about this! */
1581 #ifndef ARM_FUNCTION_PROFILER
1582 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \
1583 { \
1584 char temp[20]; \
1585 rtx sym; \
1586 \
1587 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \
1588 IP_REGNUM, LR_REGNUM); \
1589 assemble_name (STREAM, ARM_MCOUNT_NAME); \
1590 fputc ('\n', STREAM); \
1591 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \
1592 sym = gen_rtx (SYMBOL_REF, Pmode, temp); \
1593 assemble_aligned_integer (UNITS_PER_WORD, sym); \
1594 }
1595 #endif
1596
1597 #define THUMB_FUNCTION_PROFILER(STREAM, LABELNO) \
1598 { \
1599 fprintf (STREAM, "\tmov\tip, lr\n"); \
1600 fprintf (STREAM, "\tbl\tmcount\n"); \
1601 fprintf (STREAM, "\t.word\tLP%d\n", LABELNO); \
1602 }
1603
1604 #define FUNCTION_PROFILER(STREAM, LABELNO) \
1605 if (TARGET_ARM) \
1606 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \
1607 else \
1608 THUMB_FUNCTION_PROFILER (STREAM, LABELNO)
1609
1610 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1611 the stack pointer does not matter. The value is tested only in
1612 functions that have frame pointers.
1613 No definition is equivalent to always zero.
1614
1615 On the ARM, the function epilogue recovers the stack pointer from the
1616 frame. */
1617 #define EXIT_IGNORE_STACK 1
1618
1619 #define EPILOGUE_USES(REGNO) (reload_completed && (REGNO) == LR_REGNUM)
1620
1621 /* Determine if the epilogue should be output as RTL.
1622 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
1623 #define USE_RETURN_INSN(ISCOND) \
1624 (TARGET_ARM ? use_return_insn (ISCOND) : 0)
1625
1626 /* Definitions for register eliminations.
1627
1628 This is an array of structures. Each structure initializes one pair
1629 of eliminable registers. The "from" register number is given first,
1630 followed by "to". Eliminations of the same "from" register are listed
1631 in order of preference.
1632
1633 We have two registers that can be eliminated on the ARM. First, the
1634 arg pointer register can often be eliminated in favor of the stack
1635 pointer register. Secondly, the pseudo frame pointer register can always
1636 be eliminated; it is replaced with either the stack or the real frame
1637 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM
1638 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */
1639
1640 #define ELIMINABLE_REGS \
1641 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1642 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\
1643 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1644 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\
1645 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\
1646 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\
1647 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }}
1648
1649 /* Given FROM and TO register numbers, say whether this elimination is
1650 allowed. Frame pointer elimination is automatically handled.
1651
1652 All eliminations are permissible. Note that ARG_POINTER_REGNUM and
1653 HARD_FRAME_POINTER_REGNUM are in fact the same thing. If we need a frame
1654 pointer, we must eliminate FRAME_POINTER_REGNUM into
1655 HARD_FRAME_POINTER_REGNUM and not into STACK_POINTER_REGNUM or
1656 ARG_POINTER_REGNUM. */
1657 #define CAN_ELIMINATE(FROM, TO) \
1658 (((TO) == FRAME_POINTER_REGNUM && (FROM) == ARG_POINTER_REGNUM) ? 0 : \
1659 ((TO) == STACK_POINTER_REGNUM && frame_pointer_needed) ? 0 : \
1660 ((TO) == ARM_HARD_FRAME_POINTER_REGNUM && TARGET_THUMB) ? 0 : \
1661 ((TO) == THUMB_HARD_FRAME_POINTER_REGNUM && TARGET_ARM) ? 0 : \
1662 1)
1663
1664 /* Define the offset between two registers, one to be eliminated, and the
1665 other its replacement, at the start of a routine. */
1666 #define ARM_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1667 do \
1668 { \
1669 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \
1670 } \
1671 while (0)
1672
1673 /* Note: This macro must match the code in thumb_function_prologue(). */
1674 #define THUMB_INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1675 { \
1676 (OFFSET) = 0; \
1677 if ((FROM) == ARG_POINTER_REGNUM) \
1678 { \
1679 int count_regs = 0; \
1680 int regno; \
1681 for (regno = 8; regno < 13; regno ++) \
1682 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1683 count_regs ++; \
1684 if (count_regs) \
1685 (OFFSET) += 4 * count_regs; \
1686 count_regs = 0; \
1687 for (regno = 0; regno <= LAST_LO_REGNUM; regno ++) \
1688 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1689 count_regs ++; \
1690 if (count_regs || ! leaf_function_p () || thumb_far_jump_used_p (0))\
1691 (OFFSET) += 4 * (count_regs + 1); \
1692 if (TARGET_BACKTRACE) \
1693 { \
1694 if ((count_regs & 0xFF) == 0 && (regs_ever_live[3] != 0)) \
1695 (OFFSET) += 20; \
1696 else \
1697 (OFFSET) += 16; \
1698 } \
1699 } \
1700 if ((TO) == STACK_POINTER_REGNUM) \
1701 { \
1702 (OFFSET) += current_function_outgoing_args_size; \
1703 (OFFSET) += ROUND_UP (get_frame_size ()); \
1704 } \
1705 }
1706
1707 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1708 if (TARGET_ARM) \
1709 ARM_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET); \
1710 else \
1711 THUMB_INITIAL_ELIMINATION_OFFSET (FROM, TO, OFFSET)
1712
1713 /* Special case handling of the location of arguments passed on the stack. */
1714 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr)
1715
1716 /* Initialize data used by insn expanders. This is called from insn_emit,
1717 once for every function before code is generated. */
1718 #define INIT_EXPANDERS arm_init_expanders ()
1719
1720 /* Output assembler code for a block containing the constant parts
1721 of a trampoline, leaving space for the variable parts.
1722
1723 On the ARM, (if r8 is the static chain regnum, and remembering that
1724 referencing pc adds an offset of 8) the trampoline looks like:
1725 ldr r8, [pc, #0]
1726 ldr pc, [pc]
1727 .word static chain value
1728 .word function's address
1729 ??? FIXME: When the trampoline returns, r8 will be clobbered. */
1730 #define ARM_TRAMPOLINE_TEMPLATE(FILE) \
1731 { \
1732 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1733 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1734 asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \
1735 PC_REGNUM, PC_REGNUM); \
1736 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1737 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \
1738 }
1739
1740 /* On the Thumb we always switch into ARM mode to execute the trampoline.
1741 Why - because it is easier. This code will always be branched to via
1742 a BX instruction and since the compiler magically generates the address
1743 of the function the linker has no opportunity to ensure that the
1744 bottom bit is set. Thus the processor will be in ARM mode when it
1745 reaches this code. So we duplicate the ARM trampoline code and add
1746 a switch into Thumb mode as well. */
1747 #define THUMB_TRAMPOLINE_TEMPLATE(FILE) \
1748 { \
1749 fprintf (FILE, "\t.code 32\n"); \
1750 fprintf (FILE, ".Ltrampoline_start:\n"); \
1751 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1752 STATIC_CHAIN_REGNUM, PC_REGNUM); \
1753 asm_fprintf (FILE, "\tldr\t%r, [%r, #8]\n", \
1754 IP_REGNUM, PC_REGNUM); \
1755 asm_fprintf (FILE, "\torr\t%r, %r, #1\n", \
1756 IP_REGNUM, IP_REGNUM); \
1757 asm_fprintf (FILE, "\tbx\t%r\n", IP_REGNUM); \
1758 fprintf (FILE, "\t.word\t0\n"); \
1759 fprintf (FILE, "\t.word\t0\n"); \
1760 fprintf (FILE, "\t.code 16\n"); \
1761 }
1762
1763 #define TRAMPOLINE_TEMPLATE(FILE) \
1764 if (TARGET_ARM) \
1765 ARM_TRAMPOLINE_TEMPLATE (FILE) \
1766 else \
1767 THUMB_TRAMPOLINE_TEMPLATE (FILE)
1768
1769 /* Length in units of the trampoline for entering a nested function. */
1770 #define TRAMPOLINE_SIZE (TARGET_ARM ? 16 : 24)
1771
1772 /* Alignment required for a trampoline in units. */
1773 #define TRAMPOLINE_ALIGN 4
1774
1775 /* Emit RTL insns to initialize the variable parts of a trampoline.
1776 FNADDR is an RTX for the address of the function's pure code.
1777 CXT is an RTX for the static chain value for the function. */
1778 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1779 { \
1780 emit_move_insn \
1781 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 8 : 16)), CXT); \
1782 emit_move_insn \
1783 (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 12 : 20)), FNADDR); \
1784 }
1785
1786 \f
1787 /* Addressing modes, and classification of registers for them. */
1788 #define HAVE_POST_INCREMENT 1
1789 #define HAVE_PRE_INCREMENT TARGET_ARM
1790 #define HAVE_POST_DECREMENT TARGET_ARM
1791 #define HAVE_PRE_DECREMENT TARGET_ARM
1792
1793 /* Macros to check register numbers against specific register classes. */
1794
1795 /* These assume that REGNO is a hard or pseudo reg number.
1796 They give nonzero only if REGNO is a hard reg of the suitable class
1797 or a pseudo reg currently allocated to a suitable hard reg.
1798 Since they use reg_renumber, they are safe only once reg_renumber
1799 has been allocated, which happens in local-alloc.c. */
1800 #define TEST_REGNO(R, TEST, VALUE) \
1801 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
1802
1803 /* On the ARM, don't allow the pc to be used. */
1804 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \
1805 (TEST_REGNO (REGNO, <, PC_REGNUM) \
1806 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \
1807 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM))
1808
1809 #define THUMB_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1810 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \
1811 || (GET_MODE_SIZE (MODE) >= 4 \
1812 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)))
1813
1814 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \
1815 (TARGET_THUMB \
1816 ? THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \
1817 : ARM_REGNO_OK_FOR_BASE_P (REGNO))
1818
1819 /* For ARM code, we don't care about the mode, but for Thumb, the index
1820 must be suitable for use in a QImode load. */
1821 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1822 REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode)
1823
1824 /* Maximum number of registers that can appear in a valid memory address.
1825 Shifts in addresses can't be by a register. */
1826 #define MAX_REGS_PER_ADDRESS 2
1827
1828 /* Recognize any constant value that is a valid address. */
1829 /* XXX We can address any constant, eventually... */
1830
1831 #ifdef AOF_ASSEMBLER
1832
1833 #define CONSTANT_ADDRESS_P(X) \
1834 (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))
1835
1836 #else
1837
1838 #define CONSTANT_ADDRESS_P(X) \
1839 (GET_CODE (X) == SYMBOL_REF \
1840 && (CONSTANT_POOL_ADDRESS_P (X) \
1841 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
1842
1843 #endif /* AOF_ASSEMBLER */
1844
1845 /* Nonzero if the constant value X is a legitimate general operand.
1846 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1847
1848 On the ARM, allow any integer (invalid ones are removed later by insn
1849 patterns), nice doubles and symbol_refs which refer to the function's
1850 constant pool XXX.
1851
1852 When generating pic allow anything. */
1853 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X))
1854
1855 #define THUMB_LEGITIMATE_CONSTANT_P(X) \
1856 ( GET_CODE (X) == CONST_INT \
1857 || GET_CODE (X) == CONST_DOUBLE \
1858 || CONSTANT_ADDRESS_P (X))
1859
1860 #define LEGITIMATE_CONSTANT_P(X) \
1861 (TARGET_ARM ? ARM_LEGITIMATE_CONSTANT_P (X) : THUMB_LEGITIMATE_CONSTANT_P (X))
1862
1863 /* Special characters prefixed to function names
1864 in order to encode attribute like information.
1865 Note, '@' and '*' have already been taken. */
1866 #define SHORT_CALL_FLAG_CHAR '^'
1867 #define LONG_CALL_FLAG_CHAR '#'
1868
1869 #define ENCODED_SHORT_CALL_ATTR_P(SYMBOL_NAME) \
1870 (*(SYMBOL_NAME) == SHORT_CALL_FLAG_CHAR)
1871
1872 #define ENCODED_LONG_CALL_ATTR_P(SYMBOL_NAME) \
1873 (*(SYMBOL_NAME) == LONG_CALL_FLAG_CHAR)
1874
1875 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS
1876 #define SUBTARGET_NAME_ENCODING_LENGTHS
1877 #endif
1878
1879 /* This is a C fragement for the inside of a switch statement.
1880 Each case label should return the number of characters to
1881 be stripped from the start of a function's name, if that
1882 name starts with the indicated character. */
1883 #define ARM_NAME_ENCODING_LENGTHS \
1884 case SHORT_CALL_FLAG_CHAR: return 1; \
1885 case LONG_CALL_FLAG_CHAR: return 1; \
1886 case '*': return 1; \
1887 SUBTARGET_NAME_ENCODING_LENGTHS
1888
1889 /* This has to be handled by a function because more than part of the
1890 ARM backend uses function name prefixes to encode attributes. */
1891 #undef STRIP_NAME_ENCODING
1892 #define STRIP_NAME_ENCODING(VAR, SYMBOL_NAME) \
1893 (VAR) = arm_strip_name_encoding (SYMBOL_NAME)
1894
1895 /* This is how to output a reference to a user-level label named NAME.
1896 `assemble_name' uses this. */
1897 #undef ASM_OUTPUT_LABELREF
1898 #define ASM_OUTPUT_LABELREF(FILE, NAME) \
1899 asm_fprintf (FILE, "%U%s", arm_strip_name_encoding (NAME))
1900
1901 /* If we are referencing a function that is weak then encode a long call
1902 flag in the function name, otherwise if the function is static or
1903 or known to be defined in this file then encode a short call flag.
1904 This macro is used inside the ENCODE_SECTION macro. */
1905 #define ARM_ENCODE_CALL_TYPE(decl) \
1906 if (TREE_CODE (decl) == FUNCTION_DECL) \
1907 { \
1908 if (DECL_WEAK (decl)) \
1909 arm_encode_call_attribute (decl, LONG_CALL_FLAG_CHAR); \
1910 else if (! TREE_PUBLIC (decl)) \
1911 arm_encode_call_attribute (decl, SHORT_CALL_FLAG_CHAR); \
1912 } \
1913
1914 /* Symbols in the text segment can be accessed without indirecting via the
1915 constant pool; it may take an extra binary operation, but this is still
1916 faster than indirecting via memory. Don't do this when not optimizing,
1917 since we won't be calculating al of the offsets necessary to do this
1918 simplification. */
1919 /* This doesn't work with AOF syntax, since the string table may be in
1920 a different AREA. */
1921 #ifndef AOF_ASSEMBLER
1922 #define ENCODE_SECTION_INFO(decl) \
1923 { \
1924 if (optimize > 0 && TREE_CONSTANT (decl) \
1925 && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) \
1926 { \
1927 rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' \
1928 ? TREE_CST_RTL (decl) : DECL_RTL (decl)); \
1929 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; \
1930 } \
1931 ARM_ENCODE_CALL_TYPE (decl) \
1932 }
1933 #else
1934 #define ENCODE_SECTION_INFO(decl) \
1935 { \
1936 ARM_ENCODE_CALL_TYPE (decl) \
1937 }
1938 #endif
1939
1940 #define ARM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
1941 arm_encode_call_attribute (DECL, SHORT_CALL_FLAG_CHAR)
1942
1943 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1944 and check its validity for a certain class.
1945 We have two alternate definitions for each of them.
1946 The usual definition accepts all pseudo regs; the other rejects
1947 them unless they have been allocated suitable hard regs.
1948 The symbol REG_OK_STRICT causes the latter definition to be used. */
1949 #ifndef REG_OK_STRICT
1950
1951 #define ARM_REG_OK_FOR_BASE_P(X) \
1952 (REGNO (X) <= LAST_ARM_REGNUM \
1953 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1954 || REGNO (X) == FRAME_POINTER_REGNUM \
1955 || REGNO (X) == ARG_POINTER_REGNUM)
1956
1957 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1958 (REGNO (X) <= LAST_LO_REGNUM \
1959 || REGNO (X) >= FIRST_PSEUDO_REGISTER \
1960 || (GET_MODE_SIZE (MODE) >= 4 \
1961 && (REGNO (X) == STACK_POINTER_REGNUM \
1962 || (X) == hard_frame_pointer_rtx \
1963 || (X) == arg_pointer_rtx)))
1964
1965 #else /* REG_OK_STRICT */
1966
1967 #define ARM_REG_OK_FOR_BASE_P(X) \
1968 ARM_REGNO_OK_FOR_BASE_P (REGNO (X))
1969
1970 #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \
1971 THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE)
1972
1973 #endif /* REG_OK_STRICT */
1974
1975 /* Now define some helpers in terms of the above. */
1976
1977 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
1978 (TARGET_THUMB \
1979 ? THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE) \
1980 : ARM_REG_OK_FOR_BASE_P (X))
1981
1982 #define ARM_REG_OK_FOR_INDEX_P(X) ARM_REG_OK_FOR_BASE_P (X)
1983
1984 /* For Thumb, a valid index register is anything that can be used in
1985 a byte load instruction. */
1986 #define THUMB_REG_OK_FOR_INDEX_P(X) THUMB_REG_MODE_OK_FOR_BASE_P (X, QImode)
1987
1988 /* Nonzero if X is a hard reg that can be used as an index
1989 or if it is a pseudo reg. On the Thumb, the stack pointer
1990 is not suitable. */
1991 #define REG_OK_FOR_INDEX_P(X) \
1992 (TARGET_THUMB \
1993 ? THUMB_REG_OK_FOR_INDEX_P (X) \
1994 : ARM_REG_OK_FOR_INDEX_P (X))
1995
1996 \f
1997 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1998 that is a valid memory address for an instruction.
1999 The MODE argument is the machine mode for the MEM expression
2000 that wants to use this address.
2001
2002 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
2003
2004 /* --------------------------------arm version----------------------------- */
2005 #define ARM_BASE_REGISTER_RTX_P(X) \
2006 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
2007
2008 #define ARM_INDEX_REGISTER_RTX_P(X) \
2009 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
2010
2011 /* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs
2012 used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can
2013 only be small constants. */
2014 #define ARM_GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \
2015 do \
2016 { \
2017 HOST_WIDE_INT range; \
2018 enum rtx_code code = GET_CODE (INDEX); \
2019 \
2020 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
2021 { \
2022 if (code == CONST_INT && INTVAL (INDEX) < 1024 \
2023 && INTVAL (INDEX) > -1024 \
2024 && (INTVAL (INDEX) & 3) == 0) \
2025 goto LABEL; \
2026 } \
2027 else \
2028 { \
2029 if (ARM_INDEX_REGISTER_RTX_P (INDEX) \
2030 && GET_MODE_SIZE (MODE) <= 4) \
2031 goto LABEL; \
2032 if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \
2033 && (! arm_arch4 || (MODE) != HImode)) \
2034 { \
2035 rtx xiop0 = XEXP (INDEX, 0); \
2036 rtx xiop1 = XEXP (INDEX, 1); \
2037 if (ARM_INDEX_REGISTER_RTX_P (xiop0) \
2038 && power_of_two_operand (xiop1, SImode)) \
2039 goto LABEL; \
2040 if (ARM_INDEX_REGISTER_RTX_P (xiop1) \
2041 && power_of_two_operand (xiop0, SImode)) \
2042 goto LABEL; \
2043 } \
2044 if (GET_MODE_SIZE (MODE) <= 4 \
2045 && (code == LSHIFTRT || code == ASHIFTRT \
2046 || code == ASHIFT || code == ROTATERT) \
2047 && (! arm_arch4 || (MODE) != HImode)) \
2048 { \
2049 rtx op = XEXP (INDEX, 1); \
2050 if (ARM_INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \
2051 && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \
2052 && INTVAL (op) <= 31) \
2053 goto LABEL; \
2054 } \
2055 /* NASTY: Since this limits the addressing of unsigned \
2056 byte loads. */ \
2057 range = ((MODE) == HImode || (MODE) == QImode) \
2058 ? (arm_arch4 ? 256 : 4095) : 4096; \
2059 if (code == CONST_INT && INTVAL (INDEX) < range \
2060 && INTVAL (INDEX) > -range) \
2061 goto LABEL; \
2062 } \
2063 } \
2064 while (0)
2065
2066 /* Jump to LABEL if X is a valid address RTX. This must take
2067 REG_OK_STRICT into account when deciding about valid registers.
2068
2069 Allow REG, REG+REG, REG+INDEX, INDEX+REG, REG-INDEX, and non
2070 floating SYMBOL_REF to the constant pool. Allow REG-only and
2071 AUTINC-REG if handling TImode or HImode. Other symbol refs must be
2072 forced though a static cell to ensure addressability. */
2073 #define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
2074 { \
2075 if (ARM_BASE_REGISTER_RTX_P (X)) \
2076 goto LABEL; \
2077 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \
2078 && GET_CODE (XEXP (X, 0)) == REG \
2079 && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \
2080 goto LABEL; \
2081 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
2082 && (GET_CODE (X) == LABEL_REF \
2083 || (GET_CODE (X) == CONST \
2084 && GET_CODE (XEXP ((X), 0)) == PLUS \
2085 && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \
2086 && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\
2087 goto LABEL; \
2088 else if ((MODE) == TImode) \
2089 ; \
2090 else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \
2091 { \
2092 if (GET_CODE (X) == PLUS && ARM_BASE_REGISTER_RTX_P (XEXP (X, 0)) \
2093 && GET_CODE (XEXP (X, 1)) == CONST_INT) \
2094 { \
2095 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \
2096 if (val == 4 || val == -4 || val == -8) \
2097 goto LABEL; \
2098 } \
2099 } \
2100 else if (GET_CODE (X) == PLUS) \
2101 { \
2102 rtx xop0 = XEXP (X, 0); \
2103 rtx xop1 = XEXP (X, 1); \
2104 \
2105 if (ARM_BASE_REGISTER_RTX_P (xop0)) \
2106 ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \
2107 else if (ARM_BASE_REGISTER_RTX_P (xop1)) \
2108 ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \
2109 } \
2110 /* Reload currently can't handle MINUS, so disable this for now */ \
2111 /* else if (GET_CODE (X) == MINUS) \
2112 { \
2113 rtx xop0 = XEXP (X,0); \
2114 rtx xop1 = XEXP (X,1); \
2115 \
2116 if (ARM_BASE_REGISTER_RTX_P (xop0)) \
2117 ARM_GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \
2118 } */ \
2119 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
2120 && GET_CODE (X) == SYMBOL_REF \
2121 && CONSTANT_POOL_ADDRESS_P (X) \
2122 && ! (flag_pic \
2123 && symbol_mentioned_p (get_pool_constant (X)))) \
2124 goto LABEL; \
2125 else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \
2126 && (GET_MODE_SIZE (MODE) <= 4) \
2127 && GET_CODE (XEXP (X, 0)) == REG \
2128 && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \
2129 goto LABEL; \
2130 }
2131
2132 /* ---------------------thumb version----------------------------------*/
2133 #define THUMB_LEGITIMATE_OFFSET(MODE, VAL) \
2134 (GET_MODE_SIZE (MODE) == 1 ? ((unsigned HOST_WIDE_INT) (VAL) < 32) \
2135 : GET_MODE_SIZE (MODE) == 2 ? ((unsigned HOST_WIDE_INT) (VAL) < 64 \
2136 && ((VAL) & 1) == 0) \
2137 : ((VAL) >= 0 && ((VAL) + GET_MODE_SIZE (MODE)) <= 128 \
2138 && ((VAL) & 3) == 0))
2139
2140 /* The AP may be eliminated to either the SP or the FP, so we use the
2141 least common denominator, e.g. SImode, and offsets from 0 to 64. */
2142
2143 /* ??? Verify whether the above is the right approach. */
2144
2145 /* ??? Also, the FP may be eliminated to the SP, so perhaps that
2146 needs special handling also. */
2147
2148 /* ??? Look at how the mips16 port solves this problem. It probably uses
2149 better ways to solve some of these problems. */
2150
2151 /* Although it is not incorrect, we don't accept QImode and HImode
2152 addresses based on the frame pointer or arg pointer until the
2153 reload pass starts. This is so that eliminating such addresses
2154 into stack based ones won't produce impossible code. */
2155 #define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2156 { \
2157 /* ??? Not clear if this is right. Experiment. */ \
2158 if (GET_MODE_SIZE (MODE) < 4 \
2159 && ! (reload_in_progress || reload_completed) \
2160 && ( reg_mentioned_p (frame_pointer_rtx, X) \
2161 || reg_mentioned_p (arg_pointer_rtx, X) \
2162 || reg_mentioned_p (virtual_incoming_args_rtx, X) \
2163 || reg_mentioned_p (virtual_outgoing_args_rtx, X) \
2164 || reg_mentioned_p (virtual_stack_dynamic_rtx, X) \
2165 || reg_mentioned_p (virtual_stack_vars_rtx, X))) \
2166 ; \
2167 /* Accept any base register. SP only in SImode or larger. */ \
2168 else if (GET_CODE (X) == REG \
2169 && THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE)) \
2170 goto WIN; \
2171 /* This is PC relative data before MACHINE_DEPENDENT_REORG runs. */ \
2172 else if (GET_MODE_SIZE (MODE) >= 4 && CONSTANT_P (X) \
2173 && CONSTANT_POOL_ADDRESS_P (X) && ! flag_pic) \
2174 goto WIN; \
2175 /* This is PC relative data after MACHINE_DEPENDENT_REORG runs. */ \
2176 else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \
2177 && (GET_CODE (X) == LABEL_REF \
2178 || (GET_CODE (X) == CONST \
2179 && GET_CODE (XEXP (X, 0)) == PLUS \
2180 && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF \
2181 && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT))) \
2182 goto WIN; \
2183 /* Post-inc indexing only supported for SImode and larger. */ \
2184 else if (GET_CODE (X) == POST_INC && GET_MODE_SIZE (MODE) >= 4 \
2185 && GET_CODE (XEXP (X, 0)) == REG \
2186 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0))) \
2187 goto WIN; \
2188 else if (GET_CODE (X) == PLUS) \
2189 { \
2190 /* REG+REG address can be any two index registers. */ \
2191 /* We disallow FRAME+REG addressing since we know that FRAME \
2192 will be replaced with STACK, and SP relative addressing only \
2193 permits SP+OFFSET. */ \
2194 if (GET_MODE_SIZE (MODE) <= 4 \
2195 && GET_CODE (XEXP (X, 0)) == REG \
2196 && GET_CODE (XEXP (X, 1)) == REG \
2197 && XEXP (X, 0) != frame_pointer_rtx \
2198 && XEXP (X, 1) != frame_pointer_rtx \
2199 && XEXP (X, 0) != virtual_stack_vars_rtx \
2200 && XEXP (X, 1) != virtual_stack_vars_rtx \
2201 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
2202 && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 1))) \
2203 goto WIN; \
2204 /* REG+const has 5-7 bit offset for non-SP registers. */ \
2205 else if (GET_CODE (XEXP (X, 0)) == REG \
2206 && (THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \
2207 || XEXP (X, 0) == arg_pointer_rtx) \
2208 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2209 && THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \
2210 goto WIN; \
2211 /* REG+const has 10 bit offset for SP, but only SImode and \
2212 larger is supported. */ \
2213 /* ??? Should probably check for DI/DFmode overflow here \
2214 just like GO_IF_LEGITIMATE_OFFSET does. */ \
2215 else if (GET_CODE (XEXP (X, 0)) == REG \
2216 && REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \
2217 && GET_MODE_SIZE (MODE) >= 4 \
2218 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2219 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (X, 1)) \
2220 + GET_MODE_SIZE (MODE)) <= 1024 \
2221 && (INTVAL (XEXP (X, 1)) & 3) == 0) \
2222 goto WIN; \
2223 else if (GET_CODE (XEXP (X, 0)) == REG \
2224 && REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM \
2225 && GET_MODE_SIZE (MODE) >= 4 \
2226 && GET_CODE (XEXP (X, 1)) == CONST_INT \
2227 && (INTVAL (XEXP (X, 1)) & 3) == 0) \
2228 goto WIN; \
2229 } \
2230 else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \
2231 && GET_CODE (X) == SYMBOL_REF \
2232 && CONSTANT_POOL_ADDRESS_P (X) \
2233 && ! (flag_pic \
2234 && symbol_mentioned_p (get_pool_constant (X)))) \
2235 goto WIN; \
2236 }
2237
2238 /* ------------------------------------------------------------------- */
2239 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \
2240 if (TARGET_ARM) \
2241 ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \
2242 else /* if (TARGET_THUMB) */ \
2243 THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN)
2244 /* ------------------------------------------------------------------- */
2245 \f
2246 /* Try machine-dependent ways of modifying an illegitimate address
2247 to be legitimate. If we find one, return the new, valid address.
2248 This macro is used in only one place: `memory_address' in explow.c.
2249
2250 OLDX is the address as it was before break_out_memory_refs was called.
2251 In some cases it is useful to look at this to decide what needs to be done.
2252
2253 MODE and WIN are passed so that this macro can use
2254 GO_IF_LEGITIMATE_ADDRESS.
2255
2256 It is always safe for this macro to do nothing. It exists to recognize
2257 opportunities to optimize the output.
2258
2259 On the ARM, try to convert [REG, #BIGCONST]
2260 into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST],
2261 where VALIDCONST == 0 in case of TImode. */
2262 #define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2263 { \
2264 if (GET_CODE (X) == PLUS) \
2265 { \
2266 rtx xop0 = XEXP (X, 0); \
2267 rtx xop1 = XEXP (X, 1); \
2268 \
2269 if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \
2270 xop0 = force_reg (SImode, xop0); \
2271 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
2272 xop1 = force_reg (SImode, xop1); \
2273 if (ARM_BASE_REGISTER_RTX_P (xop0) \
2274 && GET_CODE (xop1) == CONST_INT) \
2275 { \
2276 HOST_WIDE_INT n, low_n; \
2277 rtx base_reg, val; \
2278 n = INTVAL (xop1); \
2279 \
2280 if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \
2281 { \
2282 low_n = n & 0x0f; \
2283 n &= ~0x0f; \
2284 if (low_n > 4) \
2285 { \
2286 n += 16; \
2287 low_n -= 16; \
2288 } \
2289 } \
2290 else \
2291 { \
2292 low_n = ((MODE) == TImode ? 0 \
2293 : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \
2294 n -= low_n; \
2295 } \
2296 base_reg = gen_reg_rtx (SImode); \
2297 val = force_operand (gen_rtx_PLUS (SImode, xop0, \
2298 GEN_INT (n)), NULL_RTX); \
2299 emit_move_insn (base_reg, val); \
2300 (X) = (low_n == 0 ? base_reg \
2301 : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \
2302 } \
2303 else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \
2304 (X) = gen_rtx_PLUS (SImode, xop0, xop1); \
2305 } \
2306 else if (GET_CODE (X) == MINUS) \
2307 { \
2308 rtx xop0 = XEXP (X, 0); \
2309 rtx xop1 = XEXP (X, 1); \
2310 \
2311 if (CONSTANT_P (xop0)) \
2312 xop0 = force_reg (SImode, xop0); \
2313 if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \
2314 xop1 = force_reg (SImode, xop1); \
2315 if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \
2316 (X) = gen_rtx_MINUS (SImode, xop0, xop1); \
2317 } \
2318 if (flag_pic) \
2319 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \
2320 if (memory_address_p (MODE, X)) \
2321 goto WIN; \
2322 }
2323
2324 #define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2325 if (flag_pic) \
2326 (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX);
2327
2328 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
2329 if (TARGET_ARM) \
2330 ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN) \
2331 else \
2332 THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN)
2333
2334 /* Go to LABEL if ADDR (a legitimate address expression)
2335 has an effect that depends on the machine mode it is used for. */
2336 #define ARM_GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2337 { \
2338 if ( GET_CODE (ADDR) == PRE_DEC || GET_CODE (ADDR) == POST_DEC \
2339 || GET_CODE (ADDR) == PRE_INC || GET_CODE (ADDR) == POST_INC) \
2340 goto LABEL; \
2341 }
2342
2343 /* Nothing helpful to do for the Thumb */
2344 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
2345 if (TARGET_ARM) \
2346 ARM_GO_IF_MODE_DEPENDENT_ADDRESS (ADDR, LABEL)
2347 \f
2348
2349 /* Specify the machine mode that this machine uses
2350 for the index in the tablejump instruction. */
2351 #define CASE_VECTOR_MODE Pmode
2352
2353 /* Define as C expression which evaluates to nonzero if the tablejump
2354 instruction expects the table to contain offsets from the address of the
2355 table.
2356 Do not define this if the table should contain absolute addresses. */
2357 /* #define CASE_VECTOR_PC_RELATIVE 1 */
2358
2359 /* signed 'char' is most compatible, but RISC OS wants it unsigned.
2360 unsigned is probably best, but may break some code. */
2361 #ifndef DEFAULT_SIGNED_CHAR
2362 #define DEFAULT_SIGNED_CHAR 0
2363 #endif
2364
2365 /* Don't cse the address of the function being compiled. */
2366 #define NO_RECURSIVE_FUNCTION_CSE 1
2367
2368 /* Max number of bytes we can move from memory to memory
2369 in one reasonably fast instruction. */
2370 #define MOVE_MAX 4
2371
2372 #undef MOVE_RATIO
2373 #define MOVE_RATIO (arm_is_xscale ? 4 : 2)
2374
2375 /* Define if operations between registers always perform the operation
2376 on the full register even if a narrower mode is specified. */
2377 #define WORD_REGISTER_OPERATIONS
2378
2379 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
2380 will either zero-extend or sign-extend. The value of this macro should
2381 be the code that says which one of the two operations is implicitly
2382 done, NIL if none. */
2383 #define LOAD_EXTEND_OP(MODE) \
2384 (TARGET_THUMB ? ZERO_EXTEND : \
2385 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \
2386 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : NIL)))
2387
2388 /* Define this if zero-extension is slow (more than one real instruction).
2389 On the ARM, it is more than one instruction only if not fetching from
2390 memory. */
2391 /* #define SLOW_ZERO_EXTEND */
2392
2393 /* Nonzero if access to memory by bytes is slow and undesirable. */
2394 #define SLOW_BYTE_ACCESS 0
2395
2396 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1
2397
2398 /* Immediate shift counts are truncated by the output routines (or was it
2399 the assembler?). Shift counts in a register are truncated by ARM. Note
2400 that the native compiler puts too large (> 32) immediate shift counts
2401 into a register and shifts by the register, letting the ARM decide what
2402 to do instead of doing that itself. */
2403 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that
2404 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y).
2405 On the arm, Y in a register is used modulo 256 for the shift. Only for
2406 rotates is modulo 32 used. */
2407 /* #define SHIFT_COUNT_TRUNCATED 1 */
2408
2409 /* All integers have the same format so truncation is easy. */
2410 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2411
2412 /* Calling from registers is a massive pain. */
2413 #define NO_FUNCTION_CSE 1
2414
2415 /* Chars and shorts should be passed as ints. */
2416 #define PROMOTE_PROTOTYPES 1
2417
2418 /* The machine modes of pointers and functions */
2419 #define Pmode SImode
2420 #define FUNCTION_MODE Pmode
2421
2422 #define ARM_FRAME_RTX(X) \
2423 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \
2424 || (X) == arg_pointer_rtx)
2425
2426 #define DEFAULT_RTX_COSTS(X, CODE, OUTER_CODE) \
2427 return arm_rtx_costs (X, CODE, OUTER_CODE);
2428
2429 /* Moves to and from memory are quite expensive */
2430 #define MEMORY_MOVE_COST(M, CLASS, IN) \
2431 (TARGET_ARM ? 10 : \
2432 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \
2433 * (CLASS == LO_REGS ? 1 : 2)))
2434
2435 /* All address computations that can be done are free, but rtx cost returns
2436 the same for practically all of them. So we weight the different types
2437 of address here in the order (most pref first):
2438 PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */
2439 #define ARM_ADDRESS_COST(X) \
2440 (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \
2441 || GET_CODE (X) == SYMBOL_REF) \
2442 ? 0 \
2443 : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \
2444 || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \
2445 ? 10 \
2446 : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \
2447 ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \
2448 : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \
2449 || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \
2450 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \
2451 || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \
2452 ? 1 : 0)) \
2453 : 4)))))
2454
2455 #define THUMB_ADDRESS_COST(X) \
2456 ((GET_CODE (X) == REG \
2457 || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \
2458 && GET_CODE (XEXP (X, 1)) == CONST_INT)) \
2459 ? 1 : 2)
2460
2461 #define ADDRESS_COST(X) \
2462 (TARGET_ARM ? ARM_ADDRESS_COST (X) : THUMB_ADDRESS_COST (X))
2463
2464 /* Try to generate sequences that don't involve branches, we can then use
2465 conditional instructions */
2466 #define BRANCH_COST \
2467 (TARGET_ARM ? 4 : (optimize > 1 ? 1 : 0))
2468 \f
2469 /* Position Independent Code. */
2470 /* We decide which register to use based on the compilation options and
2471 the assembler in use; this is more general than the APCS restriction of
2472 using sb (r9) all the time. */
2473 extern int arm_pic_register;
2474
2475 /* Used when parsing command line option -mpic-register=. */
2476 extern const char * arm_pic_register_string;
2477
2478 /* The register number of the register used to address a table of static
2479 data addresses in memory. */
2480 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register
2481
2482 #define FINALIZE_PIC arm_finalize_pic (1)
2483
2484 /* We can't directly access anything that contains a symbol,
2485 nor can we indirect via the constant pool. */
2486 #define LEGITIMATE_PIC_OPERAND_P(X) \
2487 ( ! symbol_mentioned_p (X) \
2488 && ! label_mentioned_p (X) \
2489 && (! CONSTANT_POOL_ADDRESS_P (X) \
2490 || ( ! symbol_mentioned_p (get_pool_constant (X)) \
2491 && ! label_mentioned_p (get_pool_constant (X)))))
2492
2493 /* We need to know when we are making a constant pool; this determines
2494 whether data needs to be in the GOT or can be referenced via a GOT
2495 offset. */
2496 extern int making_const_table;
2497 \f
2498 /* Handle pragmas for compatibility with Intel's compilers. */
2499 #define REGISTER_TARGET_PRAGMAS(PFILE) do { \
2500 cpp_register_pragma (PFILE, 0, "long_calls", arm_pr_long_calls); \
2501 cpp_register_pragma (PFILE, 0, "no_long_calls", arm_pr_no_long_calls); \
2502 cpp_register_pragma (PFILE, 0, "long_calls_off", arm_pr_long_calls_off); \
2503 } while (0)
2504
2505 /* Condition code information. */
2506 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2507 return the mode to be used for the comparison.
2508 CCFPEmode should be used with floating inequalities,
2509 CCFPmode should be used with floating equalities.
2510 CC_NOOVmode should be used with SImode integer equalities.
2511 CC_Zmode should be used if only the Z flag is set correctly
2512 CCmode should be used otherwise. */
2513
2514 #define EXTRA_CC_MODES \
2515 CC(CC_NOOVmode, "CC_NOOV") \
2516 CC(CC_Zmode, "CC_Z") \
2517 CC(CC_SWPmode, "CC_SWP") \
2518 CC(CCFPmode, "CCFP") \
2519 CC(CCFPEmode, "CCFPE") \
2520 CC(CC_DNEmode, "CC_DNE") \
2521 CC(CC_DEQmode, "CC_DEQ") \
2522 CC(CC_DLEmode, "CC_DLE") \
2523 CC(CC_DLTmode, "CC_DLT") \
2524 CC(CC_DGEmode, "CC_DGE") \
2525 CC(CC_DGTmode, "CC_DGT") \
2526 CC(CC_DLEUmode, "CC_DLEU") \
2527 CC(CC_DLTUmode, "CC_DLTU") \
2528 CC(CC_DGEUmode, "CC_DGEU") \
2529 CC(CC_DGTUmode, "CC_DGTU") \
2530 CC(CC_Cmode, "CC_C")
2531
2532 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y)
2533
2534 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode)
2535
2536 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
2537 do \
2538 { \
2539 if (GET_CODE (OP1) == CONST_INT \
2540 && ! (const_ok_for_arm (INTVAL (OP1)) \
2541 || (const_ok_for_arm (- INTVAL (OP1))))) \
2542 { \
2543 rtx const_op = OP1; \
2544 CODE = arm_canonicalize_comparison ((CODE), &const_op); \
2545 OP1 = const_op; \
2546 } \
2547 } \
2548 while (0)
2549
2550 #define STORE_FLAG_VALUE 1
2551
2552 \f
2553
2554 /* Gcc puts the pool in the wrong place for ARM, since we can only
2555 load addresses a limited distance around the pc. We do some
2556 special munging to move the constant pool values to the correct
2557 point in the code. */
2558 #define MACHINE_DEPENDENT_REORG(INSN) \
2559 arm_reorg (INSN); \
2560
2561 #undef ASM_APP_OFF
2562 #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "")
2563
2564 /* Output an internal label definition. */
2565 #ifndef ASM_OUTPUT_INTERNAL_LABEL
2566 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \
2567 do \
2568 { \
2569 char * s = (char *) alloca (40 + strlen (PREFIX)); \
2570 \
2571 if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \
2572 && !strcmp (PREFIX, "L")) \
2573 { \
2574 arm_ccfsm_state = 0; \
2575 arm_target_insn = NULL; \
2576 } \
2577 ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \
2578 ASM_OUTPUT_LABEL (STREAM, s); \
2579 } \
2580 while (0)
2581 #endif
2582
2583 /* Output a push or a pop instruction (only used when profiling). */
2584 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \
2585 if (TARGET_ARM) \
2586 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \
2587 STACK_POINTER_REGNUM, REGNO); \
2588 else \
2589 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO)
2590
2591
2592 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \
2593 if (TARGET_ARM) \
2594 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \
2595 STACK_POINTER_REGNUM, REGNO); \
2596 else \
2597 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO)
2598
2599 /* This is how to output a label which precedes a jumptable. Since
2600 Thumb instructions are 2 bytes, we may need explicit alignment here. */
2601 #undef ASM_OUTPUT_CASE_LABEL
2602 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \
2603 do \
2604 { \
2605 if (TARGET_THUMB) \
2606 ASM_OUTPUT_ALIGN (FILE, 2); \
2607 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
2608 } \
2609 while (0)
2610
2611 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \
2612 do \
2613 { \
2614 if (TARGET_THUMB) \
2615 { \
2616 if (is_called_in_ARM_mode (DECL)) \
2617 fprintf (STREAM, "\t.code 32\n") ; \
2618 else \
2619 fprintf (STREAM, "\t.thumb_func\n") ; \
2620 } \
2621 if (TARGET_POKE_FUNCTION_NAME) \
2622 arm_poke_function_name (STREAM, (char *) NAME); \
2623 } \
2624 while (0)
2625
2626 /* For aliases of functions we use .thumb_set instead. */
2627 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \
2628 do \
2629 { \
2630 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \
2631 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \
2632 \
2633 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \
2634 { \
2635 fprintf (FILE, "\t.thumb_set "); \
2636 assemble_name (FILE, LABEL1); \
2637 fprintf (FILE, ","); \
2638 assemble_name (FILE, LABEL2); \
2639 fprintf (FILE, "\n"); \
2640 } \
2641 else \
2642 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \
2643 } \
2644 while (0)
2645
2646 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
2647 /* To support -falign-* switches we need to use .p2align so
2648 that alignment directives in code sections will be padded
2649 with no-op instructions, rather than zeroes. */
2650 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \
2651 if ((LOG) != 0) \
2652 { \
2653 if ((MAX_SKIP) == 0) \
2654 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \
2655 else \
2656 fprintf ((FILE), "\t.p2align %d,,%d\n", \
2657 (LOG), (MAX_SKIP)); \
2658 }
2659 #endif
2660 \f
2661 /* Only perform branch elimination (by making instructions conditional) if
2662 we're optimising. Otherwise it's of no use anyway. */
2663 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2664 if (TARGET_ARM && optimize) \
2665 arm_final_prescan_insn (INSN); \
2666 else if (TARGET_THUMB) \
2667 thumb_final_prescan_insn (INSN)
2668
2669 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
2670 (CODE == '@' || CODE == '|' \
2671 || (TARGET_ARM && (CODE == '?')) \
2672 || (TARGET_THUMB && (CODE == '_')))
2673
2674 /* Output an operand of an instruction. */
2675 #define PRINT_OPERAND(STREAM, X, CODE) \
2676 arm_print_operand (STREAM, X, CODE)
2677
2678 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \
2679 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \
2680 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\
2681 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \
2682 ? ((~ (unsigned HOST_WIDE_INT) 0) \
2683 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \
2684 : 0))))
2685
2686 /* Output the address of an operand. */
2687 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \
2688 { \
2689 int is_minus = GET_CODE (X) == MINUS; \
2690 \
2691 if (GET_CODE (X) == REG) \
2692 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \
2693 else if (GET_CODE (X) == PLUS || is_minus) \
2694 { \
2695 rtx base = XEXP (X, 0); \
2696 rtx index = XEXP (X, 1); \
2697 HOST_WIDE_INT offset = 0; \
2698 if (GET_CODE (base) != REG) \
2699 { \
2700 /* Ensure that BASE is a register */ \
2701 /* (one of them must be). */ \
2702 rtx temp = base; \
2703 base = index; \
2704 index = temp; \
2705 } \
2706 switch (GET_CODE (index)) \
2707 { \
2708 case CONST_INT: \
2709 offset = INTVAL (index); \
2710 if (is_minus) \
2711 offset = -offset; \
2712 asm_fprintf (STREAM, "[%r, #%d]", \
2713 REGNO (base), offset); \
2714 break; \
2715 \
2716 case REG: \
2717 asm_fprintf (STREAM, "[%r, %s%r]", \
2718 REGNO (base), is_minus ? "-" : "", \
2719 REGNO (index)); \
2720 break; \
2721 \
2722 case MULT: \
2723 case ASHIFTRT: \
2724 case LSHIFTRT: \
2725 case ASHIFT: \
2726 case ROTATERT: \
2727 { \
2728 asm_fprintf (STREAM, "[%r, %s%r", \
2729 REGNO (base), is_minus ? "-" : "", \
2730 REGNO (XEXP (index, 0))); \
2731 arm_print_operand (STREAM, index, 'S'); \
2732 fputs ("]", STREAM); \
2733 break; \
2734 } \
2735 \
2736 default: \
2737 abort(); \
2738 } \
2739 } \
2740 else if ( GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC\
2741 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC)\
2742 { \
2743 extern int output_memory_reference_mode; \
2744 \
2745 if (GET_CODE (XEXP (X, 0)) != REG) \
2746 abort (); \
2747 \
2748 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \
2749 asm_fprintf (STREAM, "[%r, #%s%d]!", \
2750 REGNO (XEXP (X, 0)), \
2751 GET_CODE (X) == PRE_DEC ? "-" : "", \
2752 GET_MODE_SIZE (output_memory_reference_mode));\
2753 else \
2754 asm_fprintf (STREAM, "[%r], #%s%d", \
2755 REGNO (XEXP (X, 0)), \
2756 GET_CODE (X) == POST_DEC ? "-" : "", \
2757 GET_MODE_SIZE (output_memory_reference_mode));\
2758 } \
2759 else output_addr_const (STREAM, X); \
2760 }
2761
2762 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \
2763 { \
2764 if (GET_CODE (X) == REG) \
2765 asm_fprintf (STREAM, "[%r]", REGNO (X)); \
2766 else if (GET_CODE (X) == POST_INC) \
2767 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \
2768 else if (GET_CODE (X) == PLUS) \
2769 { \
2770 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2771 asm_fprintf (STREAM, "[%r, #%d]", \
2772 REGNO (XEXP (X, 0)), \
2773 (int) INTVAL (XEXP (X, 1))); \
2774 else \
2775 asm_fprintf (STREAM, "[%r, %r]", \
2776 REGNO (XEXP (X, 0)), \
2777 REGNO (XEXP (X, 1))); \
2778 } \
2779 else \
2780 output_addr_const (STREAM, X); \
2781 }
2782
2783 #define PRINT_OPERAND_ADDRESS(STREAM, X) \
2784 if (TARGET_ARM) \
2785 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \
2786 else \
2787 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X)
2788
2789 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
2790 Used for C++ multiple inheritance. */
2791 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
2792 do \
2793 { \
2794 int mi_delta = (DELTA); \
2795 const char *const mi_op = mi_delta < 0 ? "sub" : "add"; \
2796 int shift = 0; \
2797 int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))) \
2798 ? 1 : 0); \
2799 if (mi_delta < 0) \
2800 mi_delta = - mi_delta; \
2801 while (mi_delta != 0) \
2802 { \
2803 if ((mi_delta & (3 << shift)) == 0) \
2804 shift += 2; \
2805 else \
2806 { \
2807 asm_fprintf (FILE, "\t%s\t%r, %r, #%d\n", \
2808 mi_op, this_regno, this_regno, \
2809 mi_delta & (0xff << shift)); \
2810 mi_delta &= ~(0xff << shift); \
2811 shift += 8; \
2812 } \
2813 } \
2814 fputs ("\tb\t", FILE); \
2815 assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0)); \
2816 if (NEED_PLT_RELOC) \
2817 fputs ("(PLT)", FILE); \
2818 fputc ('\n', FILE); \
2819 } \
2820 while (0)
2821
2822 /* A C expression whose value is RTL representing the value of the return
2823 address for the frame COUNT steps up from the current frame. */
2824
2825 #define RETURN_ADDR_RTX(COUNT, FRAME) \
2826 arm_return_addr (COUNT, FRAME)
2827
2828 /* Mask of the bits in the PC that contain the real return address
2829 when running in 26-bit mode. */
2830 #define RETURN_ADDR_MASK26 (0x03fffffc)
2831
2832 /* Pick up the return address upon entry to a procedure. Used for
2833 dwarf2 unwind information. This also enables the table driven
2834 mechanism. */
2835 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
2836 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM)
2837
2838 /* Used to mask out junk bits from the return address, such as
2839 processor state, interrupt status, condition codes and the like. */
2840 #define MASK_RETURN_ADDR \
2841 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \
2842 in 26 bit mode, the condition codes must be masked out of the \
2843 return address. This does not apply to ARM6 and later processors \
2844 when running in 32 bit mode. */ \
2845 ((!TARGET_APCS_32) ? (GEN_INT (RETURN_ADDR_MASK26)) \
2846 : (GEN_INT ((unsigned long)0xffffffff)))
2847
2848 \f
2849 /* Define the codes that are matched by predicates in arm.c */
2850 #define PREDICATE_CODES \
2851 {"s_register_operand", {SUBREG, REG}}, \
2852 {"arm_hard_register_operand", {REG}}, \
2853 {"f_register_operand", {SUBREG, REG}}, \
2854 {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \
2855 {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2856 {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2857 {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \
2858 {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \
2859 {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \
2860 {"index_operand", {SUBREG, REG, CONST_INT}}, \
2861 {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \
2862 {"offsettable_memory_operand", {MEM}}, \
2863 {"bad_signed_byte_operand", {MEM}}, \
2864 {"alignable_memory_operand", {MEM}}, \
2865 {"shiftable_operator", {PLUS, MINUS, AND, IOR, XOR}}, \
2866 {"minmax_operator", {SMIN, SMAX, UMIN, UMAX}}, \
2867 {"shift_operator", {ASHIFT, ASHIFTRT, LSHIFTRT, ROTATERT, MULT}}, \
2868 {"di_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, MEM}}, \
2869 {"nonimmediate_di_operand", {SUBREG, REG, MEM}}, \
2870 {"soft_df_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \
2871 {"nonimmediate_soft_df_operand", {SUBREG, REG, MEM}}, \
2872 {"load_multiple_operation", {PARALLEL}}, \
2873 {"store_multiple_operation", {PARALLEL}}, \
2874 {"equality_operator", {EQ, NE}}, \
2875 {"arm_comparison_operator", {EQ, NE, LE, LT, GE, GT, GEU, GTU, LEU, \
2876 LTU, UNORDERED, ORDERED, UNLT, UNLE, \
2877 UNGE, UNGT}}, \
2878 {"arm_rhsm_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2879 {"const_shift_operand", {CONST_INT}}, \
2880 {"multi_register_push", {PARALLEL}}, \
2881 {"cc_register", {REG}}, \
2882 {"logical_binary_operator", {AND, IOR, XOR}}, \
2883 {"dominant_cc_register", {REG}},
2884
2885 /* Define this if you have special predicates that know special things
2886 about modes. Genrecog will warn about certain forms of
2887 match_operand without a mode; if the operand predicate is listed in
2888 SPECIAL_MODE_PREDICATES, the warning will be suppressed. */
2889 #define SPECIAL_MODE_PREDICATES \
2890 "cc_register", "dominant_cc_register",
2891
2892 enum arm_builtins
2893 {
2894 ARM_BUILTIN_CLZ,
2895 ARM_BUILTIN_MAX
2896 };
2897 #endif /* ! GCC_ARM_H */
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