gcc/config/we32k/we32k.c

   1 /* Subroutines for insn-output.c for AT&T we32000 Family.
   2    Copyright (C) 1991, 1992, 1997, 1998, 1999, 2000, 2001
   3    Free Software Foundation, Inc.
   4    Contributed by John Wehle (john@feith1.uucp)
   5
   6 This file is part of GNU CC.
   7
   8 GNU CC is free software; you can redistribute it and/or modify
   9 it under the terms of the GNU General Public License as published by
  10 the Free Software Foundation; either version 2, or (at your option)
  11 any later version.
  12
  13 GNU CC is distributed in the hope that it will be useful,
  14 but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 GNU General Public License for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GNU CC; see the file COPYING.  If not, write to
  20 the Free Software Foundation, 59 Temple Place - Suite 330,
  21 Boston, MA 02111-1307, USA.  */
  22
  23
  24 #include "config.h"
  25 #include "system.h"
  26 #include "insn-config.h"
  27 #include "rtl.h"
  28 #include "function.h"
  29 #include "real.h"
  30 #include "recog.h"
  31 #include "output.h"
  32 #include "regs.h"
  33 #include "tree.h"
  34 #include "expr.h"
  35 #include "tm_p.h"
  36 #include "target.h"
  37 #include "target-def.h"
  38
  39 static void we32k_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
  40 static void we32k_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
  41 \f
  42 /* Initialize the GCC target structure.  */
  43 #undef TARGET_ASM_ALIGNED_HI_OP
  44 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
  45 #undef TARGET_ASM_ALIGNED_SI_OP
  46 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
  47
  48 #undef TARGET_ASM_FUNCTION_PROLOGUE
  49 #define TARGET_ASM_FUNCTION_PROLOGUE we32k_output_function_prologue
  50 #undef TARGET_ASM_FUNCTION_EPILOGUE
  51 #define TARGET_ASM_FUNCTION_EPILOGUE we32k_output_function_epilogue
  52
  53 struct gcc_target targetm = TARGET_INITIALIZER;
  54 \f
  55 /* Generate the assembly code for function entry.  FILE is a stdio
  56    stream to output the code to.  SIZE is an int: how many units of
  57    temporary storage to allocate.
  58
  59    Refer to the array `regs_ever_live' to determine which registers to
  60    save; `regs_ever_live[I]' is nonzero if register number I is ever
  61    used in the function.  This function is responsible for knowing
  62    which registers should not be saved even if used.  */
  63
  64 static void
  65 we32k_output_function_prologue (file, size)
  66      FILE *file;
  67      HOST_WIDE_INT size;
  68 {
  69   register int nregs_to_save;
  70   register int regno;
  71   extern char call_used_regs[];
  72
  73   nregs_to_save = 0;
  74   for (regno = 8; regno > 2; regno--)
  75     if (regs_ever_live[regno] && ! call_used_regs[regno])
  76       nregs_to_save = (9 - regno);
  77
  78   fprintf (file, "\tsave &%d\n", nregs_to_save);
  79   if (size)
  80     fprintf (file, "\taddw2 &%d,%%sp\n", (size + 3) & ~3);
  81 }
  82
  83 /* This function generates the assembly code for function exit.
  84    Args are as for output_function_prologue ().
  85
  86    The function epilogue should not depend on the current stack
  87    pointer!  It should use the frame pointer only.  This is mandatory
  88    because of alloca; we also take advantage of it to omit stack
  89    adjustments before returning.  */
  90
  91 static void
  92 we32k_output_function_epilogue (file, size)
  93      FILE *file;
  94      HOST_WIDE_INT size ATTRIBUTE_UNUSED;
  95 {
  96   register int nregs_to_restore;
  97   register int regno;
  98   extern char call_used_regs[];
  99
 100   nregs_to_restore = 0;
 101   for (regno = 8; regno > 2; regno--)
 102     if (regs_ever_live[regno] && ! call_used_regs[regno])
 103       nregs_to_restore = (9 - regno);
 104
 105   fprintf (file, "\tret &%d\n", nregs_to_restore);
 106 }
 107
 108 void
 109 output_move_double (operands)
 110      rtx *operands;
 111 {
 112   rtx lsw_operands[2];
 113   rtx lsw_sreg = NULL;
 114   rtx msw_dreg = NULL;
 115
 116   if (GET_CODE (operands[0]) == REG)
 117     {
 118       lsw_operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
 119       msw_dreg = operands[0];
 120     }
 121   else if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
 122     lsw_operands[0] = adjust_address (operands[0], SImode, 4);
 123   else
 124     abort ();
 125
 126   if (GET_CODE (operands[1]) == REG)
 127     {
 128       lsw_operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
 129       lsw_sreg = lsw_operands[1];
 130     }
 131   else if (GET_CODE (operands[1]) == MEM && offsettable_memref_p (operands[1]))
 132     {
 133       lsw_operands[1] = adjust_address (operands[1], SImode, 4);
 134       lsw_sreg = operands[1];
 135       for ( ; ; )
 136         {
 137           if (REG_P (lsw_sreg))
 138             break;
 139           if (CONSTANT_ADDRESS_P (lsw_sreg))
 140             {
 141               lsw_sreg = NULL;
 142               break;
 143             }
 144           if (GET_CODE (lsw_sreg) == MEM)
 145             {
 146               lsw_sreg = XEXP (lsw_sreg, 0);
 147               continue;
 148             }
 149           if (GET_CODE (lsw_sreg) == PLUS)
 150             {
 151               if (CONSTANT_ADDRESS_P (XEXP (lsw_sreg, 1)))
 152                 {
 153                   lsw_sreg = XEXP (lsw_sreg, 0);
 154                   continue;
 155                 }
 156               else if (CONSTANT_ADDRESS_P (XEXP (lsw_sreg, 0)))
 157                 {
 158                   lsw_sreg = XEXP (lsw_sreg, 1);
 159                   continue;
 160                 }
 161             }
 162           abort ();
 163         }
 164     }
 165   else if (GET_CODE (operands[1]) == CONST_DOUBLE)
 166     {
 167       lsw_operands[1] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
 168       operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
 169     }
 170   else if (GET_CODE (operands[1]) == CONST_INT)
 171     {
 172       lsw_operands[1] = operands[1];
 173       operands[1] = const0_rtx;
 174     }
 175   else
 176     abort ();
 177
 178   if (!msw_dreg || !lsw_sreg || REGNO (msw_dreg) != REGNO (lsw_sreg))
 179     {
 180       output_asm_insn ("movw %1, %0", operands);
 181       output_asm_insn ("movw %1, %0", lsw_operands);
 182     }
 183   else
 184     {
 185       output_asm_insn ("movw %1, %0", lsw_operands);
 186       output_asm_insn ("movw %1, %0", operands);
 187     }
 188 }
 189
 190 void
 191 output_push_double (operands)
 192      rtx *operands;
 193 {
 194   rtx lsw_operands[1];
 195
 196   if (GET_CODE (operands[0]) == REG)
 197     lsw_operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
 198   else if (GET_CODE (operands[0]) == MEM && offsettable_memref_p (operands[0]))
 199     lsw_operands[0] = adjust_address (operands[0], SImode, 4);
 200   else if (GET_CODE (operands[0]) == CONST_DOUBLE)
 201     {
 202       lsw_operands[0] = GEN_INT (CONST_DOUBLE_HIGH (operands[0]));
 203       operands[0] = GEN_INT (CONST_DOUBLE_LOW (operands[0]));
 204     }
 205   else if (GET_CODE (operands[0]) == CONST_INT)
 206     {
 207       lsw_operands[0] = operands[0];
 208       operands[0] = const0_rtx;
 209     }
 210   else
 211     abort ();
 212
 213   output_asm_insn ("pushw %0", operands);
 214   output_asm_insn ("pushw %0", lsw_operands);
 215 }