1 /* Subroutines for insn-output.c for Matsushita MN10200 series
2 Copyright (C) 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
3 Contributed by Jeff Law (law@cygnus.com).
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
32 #include "insn-attr.h"
42 #include "target-def.h"
44 /* Global registers known to hold the value zero.
46 Normally we'd depend on CSE and combine to put zero into a
47 register and re-use it.
49 However, on the mn10x00 processors we implicitly use the constant
50 zero in tst instructions, so we might be able to do better by
51 loading the value into a register in the prologue, then re-useing
52 that register throughout the function.
54 We could perform similar optimizations for other constants, but with
55 gcse due soon, it doesn't seem worth the effort.
57 These variables hold a rtx for a register known to hold the value
58 zero throughout the entire function, or NULL if no register of
59 the appropriate class has such a value throughout the life of the
64 static void count_tst_insns
PARAMS ((int *));
66 /* Note whether or not we need an out of line epilogue. */
67 static int out_of_line_epilogue
;
69 /* Initialize the GCC target structure. */
70 #undef TARGET_ASM_ALIGNED_HI_OP
71 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
73 struct gcc_target targetm
= TARGET_INITIALIZER
;
75 /* Indicate this file was compiled by gcc and what optimization
81 fprintf (file
, "#\tGCC For the Matsushita MN10200\n");
83 fprintf (file
, "# -O%d\n", optimize
);
85 fprintf (file
, "\n\n");
86 output_file_directive (file
, main_input_filename
);
87 ggc_add_rtx_root (&zero_dreg
, 1);
88 ggc_add_rtx_root (&zero_areg
, 1);
91 /* Print operand X using operand code CODE to assembly language output file
95 print_operand (file
, x
, code
)
104 /* These are normal and reversed branches. */
105 switch (code
== 'b' ? GET_CODE (x
) : reverse_condition (GET_CODE (x
)))
108 fprintf (file
, "ne");
111 fprintf (file
, "eq");
114 fprintf (file
, "ge");
117 fprintf (file
, "gt");
120 fprintf (file
, "le");
123 fprintf (file
, "lt");
126 fprintf (file
, "cc");
129 fprintf (file
, "hi");
132 fprintf (file
, "ls");
135 fprintf (file
, "cs");
142 /* This is used for the operand to a call instruction;
143 if it's a REG, enclose it in parens, else output
144 the operand normally. */
145 if (GET_CODE (x
) == REG
)
148 print_operand (file
, x
, 0);
152 print_operand (file
, x
, 0);
155 /* These are the least significant word in a 32bit value.
156 'o' allows us to sign extend a constant if doing so
157 makes for more compact code. */
160 switch (GET_CODE (x
))
164 output_address (XEXP (x
, 0));
169 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
173 fprintf (file
, "%s", reg_names
[subreg_regno (x
)]);
182 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
183 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
184 print_operand_address (file
, GEN_INT (val
& 0xffff));
191 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
192 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
195 val
= (((val
) & 0xffff) ^ (~0x7fff)) + 0x8000;
196 print_operand_address (file
, GEN_INT (val
));
202 print_operand_address (file
, GEN_INT ((INTVAL (x
) & 0xffff)));
205 unsigned int val
= INTVAL (x
) & 0xffff;
206 val
= (((val
) & 0xffff) ^ (~0x7fff)) + 0x8000;
207 print_operand_address (file
, GEN_INT (val
));
215 /* Similarly, but for the most significant word. */
218 switch (GET_CODE (x
))
222 x
= adjust_address (x
, HImode
, 2);
223 output_address (XEXP (x
, 0));
228 fprintf (file
, "%s", reg_names
[REGNO (x
) + 1]);
232 fprintf (file
, "%s", reg_names
[subreg_regno (x
) + 1]);
241 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
242 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
244 print_operand_address (file
, GEN_INT ((val
>> 16) & 0xffff));
251 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
252 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
254 val
= (val
>> 16) & 0xffff;
255 val
= (((val
) & 0xffff) ^ (~0x7fff)) + 0x8000;
257 print_operand_address (file
, GEN_INT (val
));
263 print_operand_address (file
,
264 GEN_INT ((INTVAL (x
) >> 16) & 0xffff));
267 unsigned int val
= (INTVAL (x
) >> 16) & 0xffff;
268 val
= (((val
) & 0xffff) ^ (~0x7fff)) + 0x8000;
270 print_operand_address (file
, GEN_INT (val
));
278 /* Output ~CONST_INT. */
280 if (GET_CODE (x
) != CONST_INT
)
282 fprintf (file
, "%d", ~INTVAL (x
));
285 /* An address which can not be register indirect, if it is
286 register indirect, then turn it into reg + disp. */
288 if (GET_CODE (x
) != MEM
)
290 if (GET_CODE (XEXP (x
, 0)) == REG
)
291 x
= gen_rtx_PLUS (PSImode
, XEXP (x
, 0), GEN_INT (0));
300 print_operand (file
, XEXP (x
, 1), 0);
303 /* More cases where we can sign-extend a CONST_INT if it
304 results in more compact code. */
307 if (GET_CODE (x
) == CONST_INT
)
309 int val
= INTVAL (x
);
312 x
= GEN_INT (((val
& 0xffff) ^ (~0x7fff)) + 0x8000);
314 x
= GEN_INT (((val
& 0xff) ^ (~0x7f)) + 0x80);
318 switch (GET_CODE (x
))
322 output_address (XEXP (x
, 0));
327 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
331 fprintf (file
, "%s", reg_names
[subreg_regno (x
)]);
340 print_operand_address (file
, x
);
349 /* Output assembly language output for the address ADDR to FILE. */
352 print_operand_address (file
, addr
)
356 switch (GET_CODE (addr
))
359 print_operand (file
, addr
, 0);
364 /* The base and index could be in any order, so we have
365 to figure out which is the base and which is the index.
366 Uses the same code as GO_IF_LEGITIMATE_ADDRESS. */
367 if (REG_P (XEXP (addr
, 0))
368 && REG_OK_FOR_BASE_P (XEXP (addr
, 0)))
369 base
= XEXP (addr
, 0), index
= XEXP (addr
, 1);
370 else if (REG_P (XEXP (addr
, 1))
371 && REG_OK_FOR_BASE_P (XEXP (addr
, 1)))
372 base
= XEXP (addr
, 1), index
= XEXP (addr
, 0);
375 print_operand (file
, index
, 0);
377 print_operand (file
, base
, 0);;
381 output_addr_const (file
, addr
);
384 output_addr_const (file
, addr
);
389 /* Count the number of tst insns which compare an address register
392 count_tst_insns (areg_countp
)
397 /* Assume no tst insns exist. */
400 /* If not optimizing, then quit now. */
404 /* Walk through all the insns. */
405 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
409 /* Ignore anything that is not a normal INSN. */
410 if (GET_CODE (insn
) != INSN
)
413 /* Ignore anything that isn't a SET. */
414 pat
= PATTERN (insn
);
415 if (GET_CODE (pat
) != SET
)
418 /* Check for a tst insn. */
419 if (SET_DEST (pat
) == cc0_rtx
420 && GET_CODE (SET_SRC (pat
)) == REG
421 && REGNO_REG_CLASS (REGNO (SET_SRC (pat
))) == ADDRESS_REGS
)
426 /* Return the total size (in bytes) of the current function's frame.
427 This is the size of the register save area + the size of locals,
432 unsigned int size
= get_frame_size ();
433 unsigned int outgoing_args_size
= current_function_outgoing_args_size
;
436 /* First figure out if we're going to use an out of line
437 prologue, if so we have to make space for all the
438 registers, even if we don't use them. */
439 if (optimize
&& !current_function_needs_context
&& !frame_pointer_needed
)
441 int inline_count
, outline_count
;
443 /* Compute how many bytes an inline prologue would take.
445 Each address register store takes two bytes, each data register
446 store takes three bytes. */
448 if (regs_ever_live
[5])
450 if (regs_ever_live
[6])
452 if (regs_ever_live
[2])
454 if (regs_ever_live
[3])
457 /* If this function has any stack, then the stack adjustment
458 will take two (or more) bytes. */
459 if (size
|| outgoing_args_size
460 || regs_ever_live
[5] || regs_ever_live
[6]
461 || regs_ever_live
[2] || regs_ever_live
[3])
464 /* Multiply the current count by two and add one to account for the
466 inline_count
= inline_count
* 2 + 1;
468 /* Now compute how many bytes an out of line sequence would take. */
469 /* A relaxed jsr will be three bytes. */
472 /* If there are outgoing arguments, then we will need a stack
473 pointer adjustment after the call to the prologue, two
475 outline_count
+= (outgoing_args_size
== 0 ? 0 : 2);
477 /* If there is some local frame to allocate, it will need to be
478 done before the call to the prologue, two more bytes. */
479 if (get_frame_size () != 0)
482 /* Now account for the epilogue, multiply the base count by two,
483 then deal with optimizing away the rts instruction. */
484 outline_count
= outline_count
* 2 + 1;
486 if (get_frame_size () == 0 && outgoing_args_size
== 0)
489 /* If an out of line prologue is smaller, use it. */
490 if (inline_count
> outline_count
)
491 return size
+ outgoing_args_size
+ 16;
495 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
497 if ((regs_ever_live
[i
] && !call_used_regs
[i
] && ! fixed_regs
[i
])
498 || (i
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
))
502 return (size
+ outgoing_args_size
);
505 /* Expand the prologue into RTL. */
509 unsigned int size
= total_frame_size ();
510 unsigned int outgoing_args_size
= current_function_outgoing_args_size
;
513 zero_areg
= NULL_RTX
;
514 zero_dreg
= NULL_RTX
;
516 /* If optimizing, see if we should do an out of line prologue/epilogue
519 We don't support out of line prologues if the current function
520 needs a context or frame pointer. */
521 if (optimize
&& !current_function_needs_context
&& !frame_pointer_needed
)
523 int inline_count
, outline_count
, areg_count
;
525 /* We need to end the current sequence so that count_tst_insns can
526 look at all the insns in this function. Normally this would be
527 unsafe, but it's OK in the prologue/epilogue expanders. */
530 /* Get a count of the number of tst insns which use address
531 registers (it's not profitable to try and improve tst insns
532 which use data registers). */
533 count_tst_insns (&areg_count
);
535 /* Now start a new sequence. */
538 /* Compute how many bytes an inline prologue would take.
540 Each address register store takes two bytes, each data register
541 store takes three bytes. */
543 if (regs_ever_live
[5])
545 if (regs_ever_live
[6])
547 if (regs_ever_live
[2])
549 if (regs_ever_live
[3])
552 /* If this function has any stack, then the stack adjustment
553 will take two (or more) bytes. */
554 if (size
|| outgoing_args_size
555 || regs_ever_live
[5] || regs_ever_live
[6]
556 || regs_ever_live
[2] || regs_ever_live
[3])
559 /* Multiply the current count by two and add one to account for the
561 inline_count
= inline_count
* 2 + 1;
563 /* Now compute how many bytes an out of line sequence would take. */
564 /* A relaxed jsr will be three bytes. */
567 /* If there are outgoing arguments, then we will need a stack
568 pointer adjustment after the call to the prologue, two
570 outline_count
+= (outgoing_args_size
== 0 ? 0 : 2);
572 /* If there is some local frame to allocate, it will need to be
573 done before the call to the prologue, two more bytes. */
574 if (get_frame_size () != 0)
577 /* Now account for the epilogue, multiply the base count by two,
578 then deal with optimizing away the rts instruction. */
579 outline_count
= outline_count
* 2 + 1;
581 if (get_frame_size () == 0 && outgoing_args_size
== 0)
584 /* If an out of line prologue is smaller, use it. */
585 if (inline_count
> outline_count
)
587 if (get_frame_size () != 0)
588 emit_insn (gen_addpsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
589 GEN_INT (-size
+ outgoing_args_size
+ 16)));
590 emit_insn (gen_outline_prologue_call ());
592 if (outgoing_args_size
)
593 emit_insn (gen_addpsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
594 GEN_INT (-outgoing_args_size
)));
596 out_of_line_epilogue
= 1;
598 /* Determine if it is profitable to put the value zero into a register
599 for the entire function. If so, set ZERO_DREG and ZERO_AREG. */
601 /* First see if we could load the value into a data register
602 since that's the most efficient way. */
604 && (!regs_ever_live
[2] || !regs_ever_live
[3]))
606 if (!regs_ever_live
[2])
608 regs_ever_live
[2] = 1;
609 zero_dreg
= gen_rtx_REG (HImode
, 2);
611 if (!regs_ever_live
[3])
613 regs_ever_live
[3] = 1;
614 zero_dreg
= gen_rtx_REG (HImode
, 3);
618 /* Now see if we could load the value into a address register. */
619 if (zero_dreg
== NULL_RTX
621 && (!regs_ever_live
[5] || !regs_ever_live
[6]))
623 if (!regs_ever_live
[5])
625 regs_ever_live
[5] = 1;
626 zero_areg
= gen_rtx_REG (HImode
, 5);
628 if (!regs_ever_live
[6])
630 regs_ever_live
[6] = 1;
631 zero_areg
= gen_rtx_REG (HImode
, 6);
636 emit_move_insn (zero_dreg
, const0_rtx
);
639 emit_move_insn (zero_areg
, const0_rtx
);
645 out_of_line_epilogue
= 0;
647 /* Temporarily stuff the static chain onto the stack so we can
648 use a0 as a scratch register during the prologue. */
649 if (current_function_needs_context
)
651 emit_insn (gen_addpsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
653 emit_move_insn (gen_rtx_MEM (PSImode
, stack_pointer_rtx
),
654 gen_rtx_REG (PSImode
, STATIC_CHAIN_REGNUM
));
657 if (frame_pointer_needed
)
659 /* Store a2 into a0 temporarily. */
660 emit_move_insn (gen_rtx_REG (PSImode
, 4), frame_pointer_rtx
);
662 /* Set up the frame pointer. */
663 emit_move_insn (frame_pointer_rtx
, stack_pointer_rtx
);
666 /* Make any necessary space for the saved registers and local frame. */
668 emit_insn (gen_addpsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
671 /* Save the callee saved registers. They're saved into the top
672 of the frame, using the stack pointer. */
673 for (i
= 0, offset
= outgoing_args_size
;
674 i
< FIRST_PSEUDO_REGISTER
; i
++)
676 if ((regs_ever_live
[i
] && !call_used_regs
[i
] && ! fixed_regs
[i
])
677 || (i
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
))
681 /* If we're saving the frame pointer, then it will be found in
683 regno
= (i
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
) ? 4 : i
;
685 emit_move_insn (gen_rtx_MEM (PSImode
,
686 plus_constant (stack_pointer_rtx
,
688 gen_rtx_REG (PSImode
, regno
));
693 /* Now put the static chain back where the rest of the function
694 expects to find it. */
695 if (current_function_needs_context
)
697 emit_move_insn (gen_rtx_REG (PSImode
, STATIC_CHAIN_REGNUM
),
698 gen_rtx (MEM
, PSImode
,
699 gen_rtx_PLUS (PSImode
, stack_pointer_rtx
,
704 /* Expand the epilogue into RTL. */
709 unsigned int outgoing_args_size
= current_function_outgoing_args_size
;
710 int offset
, i
, temp_regno
;
713 size
= total_frame_size ();
715 if (DECL_RESULT (current_function_decl
)
716 && DECL_RTL (DECL_RESULT (current_function_decl
))
717 && REG_P (DECL_RTL (DECL_RESULT (current_function_decl
))))
718 temp_regno
= (REGNO (DECL_RTL (DECL_RESULT (current_function_decl
))) == 4
723 /* Emit an out of line epilogue sequence if it's profitable to do so. */
724 if (out_of_line_epilogue
)
726 /* If there were no outgoing arguments and no local frame, then
727 we will be able to omit the rts at the end of this function,
728 so just jump to the epilogue_noreturn routine. */
729 if (get_frame_size () == 0 && outgoing_args_size
== 0)
731 emit_jump_insn (gen_outline_epilogue_jump ());
735 if (outgoing_args_size
)
736 emit_insn (gen_addpsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
737 GEN_INT (outgoing_args_size
)));
740 emit_insn (gen_outline_epilogue_call_d0 ());
741 else if (temp_regno
== 4)
742 emit_insn (gen_outline_epilogue_call_a0 ());
744 if (get_frame_size () != 0)
745 emit_insn (gen_addpsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
746 GEN_INT (size
- outgoing_args_size
- 16)));
747 emit_jump_insn (gen_return_internal ());
751 /* Registers are restored from the frame pointer if we have one,
752 else they're restored from the stack pointer. Figure out
753 the appropriate offset to the register save area for both cases. */
754 if (frame_pointer_needed
)
756 basereg
= frame_pointer_rtx
;
757 offset
= -(size
- outgoing_args_size
);
761 basereg
= stack_pointer_rtx
;
762 offset
= outgoing_args_size
;
765 /* Restore each register. */
766 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
768 if ((regs_ever_live
[i
] && !call_used_regs
[i
] && ! fixed_regs
[i
])
769 || (i
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
))
773 /* Restore the frame pointer (if it exists) into a temporary
775 regno
= ((i
== FRAME_POINTER_REGNUM
&& frame_pointer_needed
)
778 emit_move_insn (gen_rtx_REG (PSImode
, regno
),
779 gen_rtx_MEM (PSImode
,
780 plus_constant (basereg
, offset
)));
785 if (frame_pointer_needed
)
787 /* Deallocate this frame's stack. */
788 emit_move_insn (stack_pointer_rtx
, frame_pointer_rtx
);
789 /* Restore the old frame pointer. */
790 emit_move_insn (frame_pointer_rtx
, gen_rtx_REG (PSImode
, temp_regno
));
794 /* Deallocate this function's stack. */
795 emit_insn (gen_addpsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
799 /* If we had to allocate a slot to save the context pointer,
800 then it must be deallocated here. */
801 if (current_function_needs_context
)
802 emit_insn (gen_addpsi3 (stack_pointer_rtx
, stack_pointer_rtx
, GEN_INT (4)));
804 /* Emit the return insn, if this function had no stack, then we
805 can use the standard return (which allows more optimizations),
806 else we have to use the special one which inhibits optimizations. */
807 if (size
== 0 && !current_function_needs_context
)
808 emit_jump_insn (gen_return ());
810 emit_jump_insn (gen_return_internal ());
813 /* Update the condition code from the insn. */
816 notice_update_cc (body
, insn
)
820 switch (get_attr_cc (insn
))
823 /* Insn does not affect CC at all. */
827 /* Insn does not change CC, but the 0'th operand has been changed. */
828 if (cc_status
.value1
!= 0
829 && reg_overlap_mentioned_p (recog_data
.operand
[0], cc_status
.value1
))
830 cc_status
.value1
= 0;
834 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
835 V,C is in an unusable state. */
837 cc_status
.flags
|= CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
;
838 cc_status
.value1
= recog_data
.operand
[0];
842 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
843 C is in an unusable state. */
845 cc_status
.flags
|= CC_NO_CARRY
;
846 cc_status
.value1
= recog_data
.operand
[0];
850 /* The insn is a compare instruction. */
852 cc_status
.value1
= SET_SRC (body
);
856 /* Insn doesn't leave CC in a usable state. */
866 /* Return true if OP is a valid call operand. Valid call operands
867 are SYMBOL_REFs and REGs. */
869 call_address_operand (op
, mode
)
871 enum machine_mode mode ATTRIBUTE_UNUSED
;
873 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == REG
);
876 /* Return true if OP is a memory operand with a constant address.
877 A special PSImode move pattern uses this predicate. */
879 constant_memory_operand (op
, mode
)
881 enum machine_mode mode ATTRIBUTE_UNUSED
;
883 return GET_CODE (op
) == MEM
&& CONSTANT_ADDRESS_P (XEXP (op
, 0));
886 /* Return true if OP is valid for a psi mode truncation operand.
887 It must either be a memory operand which is valid for a PSImode
888 address, or if it is not a memory operand at all. */
890 psimode_truncation_operand (op
, mode
)
892 enum machine_mode mode
;
894 return (general_operand (op
, mode
)
895 && (GET_CODE (op
) != MEM
896 || memory_address_p (PSImode
, XEXP (op
, 0))));
899 /* What (if any) secondary registers are needed to move IN with mode
900 MODE into a register from in register class CLASS.
902 We might be able to simplify this. */
904 secondary_reload_class (class, mode
, in
, input
)
905 enum reg_class
class;
906 enum machine_mode mode
;
910 /* Memory loads less than a full word wide can't have an
911 address or stack pointer destination. They must use
912 a data register as an intermediate register. */
914 && GET_CODE (in
) == MEM
916 && class == ADDRESS_REGS
)
919 /* Address register stores which are not PSImode need a scratch register. */
921 && GET_CODE (in
) == MEM
923 && class == ADDRESS_REGS
)
926 /* Otherwise assume no secondary reloads are needed. */
933 We devote a fair bit of code to getting efficient shifts since we can only
934 shift one bit at a time, and each single bit shift may take multiple
937 The basic shift methods:
939 * loop shifts -- emit a loop using one (or two on H8/S) bit shifts;
940 this is the default. SHIFT_LOOP
942 * inlined shifts -- emit straight line code for the shift; this is
943 used when a straight line shift is about the same size or smaller
944 than a loop. We allow the inline version to be slightly longer in
945 some cases as it saves a register. SHIFT_INLINE
947 * There other oddballs. Not worth explaining. SHIFT_SPECIAL
954 5-7 If ashift, then multiply, else loop.
956 8-14 - If ashift, then multiply, if lshiftrt, then divide, else loop.
957 15 - rotate the bit we want into the carry, clear the destination,
958 (use mov 0,dst, not sub as sub will clobber the carry), then
961 Don't Panic, it's not nearly as bad as the H8 shifting code!!! */
964 nshift_operator (x
, mode
)
966 enum machine_mode mode ATTRIBUTE_UNUSED
;
968 switch (GET_CODE (x
))
980 /* Called from the .md file to emit code to do shifts.
981 Returns a boolean indicating success
982 (currently this is always TRUE). */
985 expand_a_shift (mode
, code
, operands
)
986 enum machine_mode mode
;
990 emit_move_insn (operands
[0], operands
[1]);
992 /* need a loop to get all the bits we want - we generate the
993 code at emit time, but need to allocate a scratch reg now */
995 emit_insn (gen_rtx_PARALLEL
998 gen_rtx_SET (VOIDmode
, operands
[0],
1000 operands
[0], operands
[2])),
1001 gen_rtx_CLOBBER (VOIDmode
,
1002 gen_rtx_SCRATCH (HImode
)))));
1007 /* Shift algorithm determination.
1009 There are various ways of doing a shift:
1010 SHIFT_INLINE: If the amount is small enough, just generate as many one-bit
1012 SHIFT_SPECIAL: Hand crafted assembler.
1013 SHIFT_LOOP: If the above methods fail, just loop. */
1023 /* Symbols of the various shifts which can be used as indices. */
1027 SHIFT_ASHIFT
, SHIFT_LSHIFTRT
, SHIFT_ASHIFTRT
1030 /* Symbols of the various modes which can be used as indices. */
1037 /* For single bit shift insns, record assembler and what bits of the
1038 condition code are valid afterwards (represented as various CC_FOO
1039 bits, 0 means CC isn't left in a usable state). */
1043 const char *assembler
;
1047 /* Assembler instruction shift table.
1049 These tables are used to look up the basic shifts.
1050 They are indexed by cpu, shift_type, and mode.
1053 static const struct shift_insn shift_one
[3][3] =
1057 { "add\t%0,%0", CC_OVERFLOW_UNUSABLE
| CC_NO_CARRY
},
1059 /* SHIFT_LSHIFTRT */
1061 { "lsr\t%0", CC_NO_CARRY
},
1063 /* SHIFT_ASHIFTRT */
1065 { "asr\t%0", CC_NO_CARRY
},
1069 static enum shift_alg get_shift_alg
PARAMS ((enum shift_type
,
1070 enum machine_mode
, int,
1071 const char **, int *));
1073 /* Given CPU, MODE, SHIFT_TYPE, and shift count COUNT, determine the best
1074 algorithm for doing the shift. The assembler code is stored in ASSEMBLER.
1075 We don't achieve maximum efficiency in all cases, but the hooks are here
1078 For now we just use lots of switch statements. Since we don't even come
1079 close to supporting all the cases, this is simplest. If this function ever
1080 gets too big, perhaps resort to a more table based lookup. Of course,
1081 at this point you may just wish to do it all in rtl. */
1083 static enum shift_alg
1084 get_shift_alg (shift_type
, mode
, count
, assembler_p
, cc_valid_p
)
1085 enum shift_type shift_type
;
1086 enum machine_mode mode
;
1088 const char **assembler_p
;
1091 /* The default is to loop. */
1092 enum shift_alg alg
= SHIFT_LOOP
;
1093 enum shift_mode shift_mode
;
1095 /* We don't handle negative shifts or shifts greater than the word size,
1096 they should have been handled already. */
1098 if (count
< 0 || count
> GET_MODE_BITSIZE (mode
))
1104 shift_mode
= HIshift
;
1110 /* Assume either SHIFT_LOOP or SHIFT_INLINE.
1111 It is up to the caller to know that looping clobbers cc. */
1112 *assembler_p
= shift_one
[shift_type
][shift_mode
].assembler
;
1113 *cc_valid_p
= shift_one
[shift_type
][shift_mode
].cc_valid
;
1115 /* Now look for cases we want to optimize. */
1121 return SHIFT_INLINE
;
1122 else if (count
< 15 && shift_type
!= SHIFT_ASHIFTRT
)
1127 if (shift_type
== SHIFT_ASHIFT
)
1128 *assembler_p
= "mov 32,%4\n\tmul %4,%0";
1129 else if (shift_type
== SHIFT_LSHIFTRT
)
1131 = "sub %4,%4\n\tmov %4,mdr\n\tmov 32,%4\n\tdivu %4,%0";
1132 *cc_valid_p
= CC_NO_CARRY
;
1133 return SHIFT_SPECIAL
;
1135 if (shift_type
== SHIFT_ASHIFT
)
1136 *assembler_p
= "mov 64,%4\n\tmul %4,%0";
1137 else if (shift_type
== SHIFT_LSHIFTRT
)
1139 = "sub %4,%4\n\tmov %4,mdr\n\tmov 64,%4\n\tdivu %4,%0";
1140 *cc_valid_p
= CC_NO_CARRY
;
1141 return SHIFT_SPECIAL
;
1143 if (shift_type
== SHIFT_ASHIFT
)
1144 *assembler_p
= "mov 128,%4\n\tmul %4,%0";
1145 else if (shift_type
== SHIFT_LSHIFTRT
)
1147 = "sub %4,%4\n\tmov %4,mdr\n\tmov 128,%4\n\tdivu %4,%0";
1148 *cc_valid_p
= CC_NO_CARRY
;
1149 return SHIFT_SPECIAL
;
1151 if (shift_type
== SHIFT_ASHIFT
)
1152 *assembler_p
= "mov 256,%4\n\tmul %4,%0";
1153 else if (shift_type
== SHIFT_LSHIFTRT
)
1155 = "sub %4,%4\n\tmov %4,mdr\n\tmov 256,%4\n\tdivu %4,%0";
1156 *cc_valid_p
= CC_NO_CARRY
;
1157 return SHIFT_SPECIAL
;
1159 if (shift_type
== SHIFT_ASHIFT
)
1160 *assembler_p
= "mov 512,%4\n\tmul %4,%0";
1161 else if (shift_type
== SHIFT_LSHIFTRT
)
1163 = "sub %4,%4\n\tmov %4,mdr\n\tmov 512,%4\n\tdivu %4,%0";
1164 *cc_valid_p
= CC_NO_CARRY
;
1165 return SHIFT_SPECIAL
;
1167 if (shift_type
== SHIFT_ASHIFT
)
1168 *assembler_p
= "mov 1024,%4\n\tmul %4,%0";
1169 else if (shift_type
== SHIFT_LSHIFTRT
)
1171 = "sub %4,%4\n\tmov %4,mdr\n\tmov 1024,%4\n\tdivu %4,%0";
1172 *cc_valid_p
= CC_NO_CARRY
;
1173 return SHIFT_SPECIAL
;
1175 if (shift_type
== SHIFT_ASHIFT
)
1176 *assembler_p
= "mov 2048,%4\n\tmul %4,%0";
1177 else if (shift_type
== SHIFT_LSHIFTRT
)
1179 = "sub %4,%4\n\tmov %4,mdr\n\tmov 2048,%4\n\tdivu %4,%0";
1180 *cc_valid_p
= CC_NO_CARRY
;
1181 return SHIFT_SPECIAL
;
1183 if (shift_type
== SHIFT_ASHIFT
)
1184 *assembler_p
= "mov 4096,%4\n\tmul %4,%0";
1185 else if (shift_type
== SHIFT_LSHIFTRT
)
1187 = "sub %4,%4\n\tmov %4,mdr\n\tmov 4096,%4\n\tdivu %4,%0";
1188 *cc_valid_p
= CC_NO_CARRY
;
1189 return SHIFT_SPECIAL
;
1191 if (shift_type
== SHIFT_ASHIFT
)
1192 *assembler_p
= "mov 8192,%4\n\tmul %4,%0";
1193 else if (shift_type
== SHIFT_LSHIFTRT
)
1195 = "sub %4,%4\n\tmov %4,mdr\n\tmov 8192,%4\n\tdivu %4,%0";
1196 *cc_valid_p
= CC_NO_CARRY
;
1197 return SHIFT_SPECIAL
;
1199 if (shift_type
== SHIFT_ASHIFT
)
1200 *assembler_p
= "mov 16384,%4\n\tmul %4,%0";
1201 else if (shift_type
== SHIFT_LSHIFTRT
)
1203 = "sub %4,%4\n\tmov %4,mdr\n\tmov 16384,%4\n\tdivu %4,%0";
1204 *cc_valid_p
= CC_NO_CARRY
;
1205 return SHIFT_SPECIAL
;
1208 else if (count
== 15)
1210 if (shift_type
== SHIFT_ASHIFTRT
)
1212 *assembler_p
= "add\t%0,%0\n\tsubc\t%0,%0\n";
1213 *cc_valid_p
= CC_NO_CARRY
;
1214 return SHIFT_SPECIAL
;
1216 if (shift_type
== SHIFT_LSHIFTRT
)
1218 *assembler_p
= "add\t%0,%0\n\tmov 0,%0\n\trol %0\n";
1219 *cc_valid_p
= CC_NO_CARRY
;
1220 return SHIFT_SPECIAL
;
1222 if (shift_type
== SHIFT_ASHIFT
)
1224 *assembler_p
= "ror\t%0\n\tmov 0,%0\n\tror %0\n";
1225 *cc_valid_p
= CC_NO_CARRY
;
1226 return SHIFT_SPECIAL
;
1238 /* Emit the assembler code for doing shifts. */
1241 emit_a_shift (insn
, operands
)
1242 rtx insn ATTRIBUTE_UNUSED
;
1245 static int loopend_lab
;
1246 const char *assembler
;
1248 rtx shift
= operands
[3];
1249 enum machine_mode mode
= GET_MODE (shift
);
1250 enum rtx_code code
= GET_CODE (shift
);
1251 enum shift_type shift_type
;
1252 enum shift_mode shift_mode
;
1259 shift_mode
= HIshift
;
1268 shift_type
= SHIFT_ASHIFTRT
;
1271 shift_type
= SHIFT_LSHIFTRT
;
1274 shift_type
= SHIFT_ASHIFT
;
1280 if (GET_CODE (operands
[2]) != CONST_INT
)
1282 /* Indexing by reg, so have to loop and test at top */
1283 output_asm_insn ("mov %2,%4", operands
);
1284 output_asm_insn ("cmp 0,%4", operands
);
1285 fprintf (asm_out_file
, "\tble .Lle%d\n", loopend_lab
);
1287 /* Get the assembler code to do one shift. */
1288 get_shift_alg (shift_type
, mode
, 1, &assembler
, &cc_valid
);
1292 int n
= INTVAL (operands
[2]);
1295 /* If the count is negative, make it 0. */
1298 /* If the count is too big, truncate it.
1299 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to
1300 do the intuitive thing. */
1301 else if (n
> GET_MODE_BITSIZE (mode
))
1302 n
= GET_MODE_BITSIZE (mode
);
1304 alg
= get_shift_alg (shift_type
, mode
, n
, &assembler
, &cc_valid
);
1310 /* Emit one bit shifts. */
1313 output_asm_insn (assembler
, operands
);
1317 /* Keep track of CC. */
1320 cc_status
.value1
= operands
[0];
1321 cc_status
.flags
|= cc_valid
;
1326 output_asm_insn (assembler
, operands
);
1328 /* Keep track of CC. */
1331 cc_status
.value1
= operands
[0];
1332 cc_status
.flags
|= cc_valid
;
1338 fprintf (asm_out_file
, "\tmov %d,%s\n", n
,
1339 reg_names
[REGNO (operands
[4])]);
1340 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
1341 output_asm_insn (assembler
, operands
);
1342 output_asm_insn ("add -1,%4", operands
);
1343 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
1348 fprintf (asm_out_file
, ".Llt%d:\n", loopend_lab
);
1349 output_asm_insn (assembler
, operands
);
1350 output_asm_insn ("add -1,%4", operands
);
1351 fprintf (asm_out_file
, "\tbne .Llt%d\n", loopend_lab
);
1352 fprintf (asm_out_file
, ".Lle%d:\n", loopend_lab
);
1357 /* Return an RTX to represent where a value with mode MODE will be returned
1358 from a function. If the result is 0, the argument is pushed. */
1361 function_arg (cum
, mode
, type
, named
)
1362 CUMULATIVE_ARGS
*cum
;
1363 enum machine_mode mode
;
1370 /* We only support using 2 data registers as argument registers. */
1373 /* Only pass named arguments in registers. */
1377 /* Figure out the size of the object to be passed. We lie and claim
1378 PSImode values are only two bytes since they fit in a single
1380 if (mode
== BLKmode
)
1381 size
= int_size_in_bytes (type
);
1382 else if (mode
== PSImode
)
1385 size
= GET_MODE_SIZE (mode
);
1387 /* Figure out the alignment of the object to be passed. */
1390 cum
->nbytes
= (cum
->nbytes
+ 1) & ~1;
1392 /* Don't pass this arg via a register if all the argument registers
1394 if (cum
->nbytes
+ size
> nregs
* UNITS_PER_WORD
)
1397 switch (cum
->nbytes
/ UNITS_PER_WORD
)
1400 result
= gen_rtx_REG (mode
, 0);
1403 result
= gen_rtx_REG (mode
, 1);
1412 /* Return the number of registers to use for an argument passed partially
1413 in registers and partially in memory. */
1416 function_arg_partial_nregs (cum
, mode
, type
, named
)
1417 CUMULATIVE_ARGS
*cum
;
1418 enum machine_mode mode
;
1424 /* We only support using 2 data registers as argument registers. */
1428 /* Only pass named arguments in registers. */
1432 /* Figure out the size of the object to be passed. */
1433 if (mode
== BLKmode
)
1434 size
= int_size_in_bytes (type
);
1435 else if (mode
== PSImode
)
1438 size
= GET_MODE_SIZE (mode
);
1440 /* Figure out the alignment of the object to be passed. */
1443 cum
->nbytes
= (cum
->nbytes
+ 1) & ~1;
1445 /* Don't pass this arg via a register if all the argument registers
1447 if (cum
->nbytes
> nregs
* UNITS_PER_WORD
)
1450 if (cum
->nbytes
+ size
<= nregs
* UNITS_PER_WORD
)
1453 /* Don't pass this arg via a register if it would be split between
1454 registers and memory. */
1455 if (type
== NULL_TREE
1456 && cum
->nbytes
+ size
> nregs
* UNITS_PER_WORD
)
1459 return (nregs
* UNITS_PER_WORD
- cum
->nbytes
) / UNITS_PER_WORD
;
1463 mn10200_va_arg (valist
, type
)
1466 HOST_WIDE_INT align
, rsize
;
1469 /* Compute the rounded size of the type. */
1470 align
= PARM_BOUNDARY
/ BITS_PER_UNIT
;
1471 rsize
= (((int_size_in_bytes (type
) + align
- 1) / align
) * align
);
1473 t
= build (POSTINCREMENT_EXPR
, TREE_TYPE (valist
), valist
,
1474 build_int_2 ((rsize
> 8 ? 4 : rsize
), 0));
1475 TREE_SIDE_EFFECTS (t
) = 1;
1477 ptr
= build_pointer_type (type
);
1479 /* "Large" types are passed by reference. */
1482 pptr
= build_pointer_type (ptr
);
1483 t
= build1 (NOP_EXPR
, pptr
, t
);
1484 TREE_SIDE_EFFECTS (t
) = 1;
1486 t
= build1 (INDIRECT_REF
, ptr
, t
);
1487 TREE_SIDE_EFFECTS (t
) = 1;
1491 t
= build1 (NOP_EXPR
, ptr
, t
);
1492 TREE_SIDE_EFFECTS (t
) = 1;
1496 return force_reg (Pmode
, expand_expr (t
, NULL_RTX
, Pmode
, EXPAND_NORMAL
));
1500 output_tst (operand
, insn
)
1507 /* Only tst insns using address registers can be optimized. */
1508 if (REGNO_REG_CLASS (REGNO (operand
)) != ADDRESS_REGS
)
1511 /* If testing an address register against zero, we can do better if
1512 we know there's a register already holding the value zero. First
1513 see if a global register has been set to zero, else we do a search
1514 for a register holding zero, if both of those fail, then we use a
1515 compare against zero. */
1516 if (zero_dreg
|| zero_areg
)
1519 xoperands
[0] = operand
;
1520 xoperands
[1] = zero_dreg
? zero_dreg
: zero_areg
;
1522 output_asm_insn ("cmp %1,%0", xoperands
);
1526 /* We can save a byte if we can find a register which has the value
1528 temp
= PREV_INSN (insn
);
1533 /* We allow the search to go through call insns. We record
1534 the fact that we've past a CALL_INSN and reject matches which
1535 use call clobbered registers. */
1536 if (GET_CODE (temp
) == CODE_LABEL
1537 || GET_CODE (temp
) == JUMP_INSN
1538 || GET_CODE (temp
) == BARRIER
)
1541 if (GET_CODE (temp
) == CALL_INSN
)
1544 if (GET_CODE (temp
) == NOTE
)
1546 temp
= PREV_INSN (temp
);
1550 /* It must be an insn, see if it is a simple set. */
1551 set
= single_set (temp
);
1554 temp
= PREV_INSN (temp
);
1558 /* Are we setting a register to zero?
1560 If it's a call clobbered register, have we past a call? */
1561 if (REG_P (SET_DEST (set
))
1562 && SET_SRC (set
) == CONST0_RTX (GET_MODE (SET_DEST (set
)))
1563 && !reg_set_between_p (SET_DEST (set
), temp
, insn
)
1565 || !call_used_regs
[REGNO (SET_DEST (set
))]))
1568 xoperands
[0] = operand
;
1569 xoperands
[1] = SET_DEST (set
);
1571 output_asm_insn ("cmp %1,%0", xoperands
);
1574 temp
= PREV_INSN (temp
);
1579 /* Return nonzero if OP is a valid operand for a {zero,sign}_extendpsisi
1582 It accepts anything that is a general operand or the sum of the
1583 stack pointer and a general operand. */
1585 extendpsi_operand (op
, mode
)
1587 enum machine_mode mode
;
1589 return (general_operand (op
, mode
)
1590 || (GET_CODE (op
) == PLUS
1591 && XEXP (op
, 0) == stack_pointer_rtx
1592 && general_operand (XEXP (op
, 1), VOIDmode
)));