1 /* Subroutines used for code generation on intel 80960.
2 Copyright (C) 1992, 1995, 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Steven McGeady, Intel Corp.
5 Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
6 Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
48 #include "target-def.h"
50 static void i960_output_function_prologue
PARAMS ((FILE *, HOST_WIDE_INT
));
51 static void i960_output_function_epilogue
PARAMS ((FILE *, HOST_WIDE_INT
));
53 /* Save the operands last given to a compare for use when we
54 generate a scc or bcc insn. */
56 rtx i960_compare_op0
, i960_compare_op1
;
58 /* Used to implement #pragma align/noalign. Initialized by OVERRIDE_OPTIONS
61 int i960_maxbitalignment
;
62 int i960_last_maxbitalignment
;
64 /* Used to implement switching between MEM and ALU insn types, for better
65 C series performance. */
67 enum insn_types i960_last_insn_type
;
69 /* The leaf-procedure return register. Set only if this is a leaf routine. */
71 static int i960_leaf_ret_reg
;
73 /* True if replacing tail calls with jumps is OK. */
75 static int tail_call_ok
;
77 /* A string containing a list of insns to emit in the epilogue so as to
78 restore all registers saved by the prologue. Created by the prologue
79 code as it saves registers away. */
81 char epilogue_string
[1000];
83 /* A unique number (per function) for return labels. */
85 static int ret_label
= 0;
87 /* This is true if FNDECL is either a varargs or a stdarg function.
88 This is used to help identify functions that use an argument block. */
90 #define VARARGS_STDARG_FUNCTION(FNDECL) \
91 ((TYPE_ARG_TYPES (TREE_TYPE (FNDECL)) != 0 \
92 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (FNDECL)))) != void_type_node)) \
93 || current_function_varargs)
95 /* Initialize the GCC target structure. */
96 #undef TARGET_ASM_ALIGNED_SI_OP
97 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
99 #undef TARGET_ASM_FUNCTION_PROLOGUE
100 #define TARGET_ASM_FUNCTION_PROLOGUE i960_output_function_prologue
101 #undef TARGET_ASM_FUNCTION_EPILOGUE
102 #define TARGET_ASM_FUNCTION_EPILOGUE i960_output_function_epilogue
104 struct gcc_target targetm
= TARGET_INITIALIZER
;
106 /* Initialize variables before compiling any files. */
111 if (TARGET_IC_COMPAT2_0
)
113 i960_maxbitalignment
= 8;
114 i960_last_maxbitalignment
= 128;
118 i960_maxbitalignment
= 128;
119 i960_last_maxbitalignment
= 8;
123 /* Return true if OP can be used as the source of an fp move insn. */
126 fpmove_src_operand (op
, mode
)
128 enum machine_mode mode
;
130 return (GET_CODE (op
) == CONST_DOUBLE
|| general_operand (op
, mode
));
134 /* Return true if OP is a register or zero. */
137 reg_or_zero_operand (op
, mode
)
139 enum machine_mode mode
;
141 return register_operand (op
, mode
) || op
== const0_rtx
;
145 /* Return truth value of whether OP can be used as an operands in a three
146 address arithmetic insn (such as add %o1,7,%l2) of mode MODE. */
149 arith_operand (op
, mode
)
151 enum machine_mode mode
;
153 return (register_operand (op
, mode
) || literal (op
, mode
));
156 /* Return truth value of whether OP can be used as an operands in a three
157 address logic insn, possibly complementing OP, of mode MODE. */
160 logic_operand (op
, mode
)
162 enum machine_mode mode
;
164 return (register_operand (op
, mode
)
165 || (GET_CODE (op
) == CONST_INT
166 && INTVAL(op
) >= -32 && INTVAL(op
) < 32));
169 /* Return true if OP is a register or a valid floating point literal. */
172 fp_arith_operand (op
, mode
)
174 enum machine_mode mode
;
176 return (register_operand (op
, mode
) || fp_literal (op
, mode
));
179 /* Return true if OP is a register or a valid signed integer literal. */
182 signed_arith_operand (op
, mode
)
184 enum machine_mode mode
;
186 return (register_operand (op
, mode
) || signed_literal (op
, mode
));
189 /* Return truth value of whether OP is an integer which fits the
190 range constraining immediate operands in three-address insns. */
195 enum machine_mode mode ATTRIBUTE_UNUSED
;
197 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) >= 0 && INTVAL(op
) < 32);
200 /* Return true if OP is a float constant of 1. */
203 fp_literal_one (op
, mode
)
205 enum machine_mode mode
;
207 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST1_RTX (mode
));
210 /* Return true if OP is a float constant of 0. */
213 fp_literal_zero (op
, mode
)
215 enum machine_mode mode
;
217 return (TARGET_NUMERICS
&& mode
== GET_MODE (op
) && op
== CONST0_RTX (mode
));
220 /* Return true if OP is a valid floating point literal. */
225 enum machine_mode mode
;
227 return fp_literal_zero (op
, mode
) || fp_literal_one (op
, mode
);
230 /* Return true if OP is a valid signed immediate constant. */
233 signed_literal(op
, mode
)
235 enum machine_mode mode ATTRIBUTE_UNUSED
;
237 return ((GET_CODE (op
) == CONST_INT
) && INTVAL(op
) > -32 && INTVAL(op
) < 32);
240 /* Return truth value of statement that OP is a symbolic memory
241 operand of mode MODE. */
244 symbolic_memory_operand (op
, mode
)
246 enum machine_mode mode ATTRIBUTE_UNUSED
;
248 if (GET_CODE (op
) == SUBREG
)
249 op
= SUBREG_REG (op
);
250 if (GET_CODE (op
) != MEM
)
253 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
254 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
257 /* Return truth value of whether OP is EQ or NE. */
262 enum machine_mode mode ATTRIBUTE_UNUSED
;
264 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
267 /* OP is an integer register or a constant. */
270 arith32_operand (op
, mode
)
272 enum machine_mode mode
;
274 if (register_operand (op
, mode
))
276 return (CONSTANT_P (op
));
279 /* Return true if OP is an integer constant which is a power of 2. */
282 power2_operand (op
,mode
)
284 enum machine_mode mode ATTRIBUTE_UNUSED
;
286 if (GET_CODE (op
) != CONST_INT
)
289 return exact_log2 (INTVAL (op
)) >= 0;
292 /* Return true if OP is an integer constant which is the complement of a
296 cmplpower2_operand (op
, mode
)
298 enum machine_mode mode ATTRIBUTE_UNUSED
;
300 if (GET_CODE (op
) != CONST_INT
)
303 return exact_log2 (~ INTVAL (op
)) >= 0;
306 /* If VAL has only one bit set, return the index of that bit. Otherwise
315 for (i
= 0; val
!= 0; i
++, val
>>= 1)
327 /* Return non-zero if OP is a mask, i.e. all one bits are consecutive.
328 The return value indicates how many consecutive non-zero bits exist
329 if this is a mask. This is the same as the next function, except that
330 it does not indicate what the start and stop bit positions are. */
336 register int start
, end
= 0, i
;
339 for (i
= 0; val
!= 0; val
>>= 1, i
++)
349 /* Still looking for the first bit. */
353 /* We've seen the start of a bit sequence, and now a zero. There
354 must be more one bits, otherwise we would have exited the loop.
355 Therefore, it is not a mask. */
360 /* The bit string has ones from START to END bit positions only. */
361 return end
- start
+ 1;
364 /* If VAL is a mask, then return nonzero, with S set to the starting bit
365 position and E set to the ending bit position of the mask. The return
366 value indicates how many consecutive bits exist in the mask. This is
367 the same as the previous function, except that it also indicates the
368 start and end bit positions of the mask. */
375 register int start
, end
, i
;
379 for (i
= 0; val
!= 0; val
>>= 1, i
++)
390 /* Still looking for the first bit. */
394 /* We've seen the start of a bit sequence, and now a zero. There
395 must be more one bits, otherwise we would have exited the loop.
396 Therefor, it is not a mask. */
405 /* The bit string has ones from START to END bit positions only. */
408 return ((start
< 0) ? 0 : end
- start
+ 1);
411 /* Return the machine mode to use for a comparison. */
414 select_cc_mode (op
, x
)
416 rtx x ATTRIBUTE_UNUSED
;
418 if (op
== GTU
|| op
== LTU
|| op
== GEU
|| op
== LEU
)
423 /* X and Y are two things to compare using CODE. Emit the compare insn and
424 return the rtx for register 36 in the proper mode. */
427 gen_compare_reg (code
, x
, y
)
432 enum machine_mode ccmode
= SELECT_CC_MODE (code
, x
, y
);
433 enum machine_mode mode
434 = GET_MODE (x
) == VOIDmode
? GET_MODE (y
) : GET_MODE (x
);
438 if (! arith_operand (x
, mode
))
439 x
= force_reg (SImode
, x
);
440 if (! arith_operand (y
, mode
))
441 y
= force_reg (SImode
, y
);
444 cc_reg
= gen_rtx_REG (ccmode
, 36);
445 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
446 gen_rtx_COMPARE (ccmode
, x
, y
)));
451 /* For the i960, REG is cost 1, REG+immed CONST is cost 2, REG+REG is cost 2,
452 REG+nonimmed CONST is cost 4. REG+SYMBOL_REF, SYMBOL_REF, and similar
453 are 4. Indexed addresses are cost 6. */
455 /* ??? Try using just RTX_COST, i.e. not defining ADDRESS_COST. */
458 i960_address_cost (x
)
462 /* Handled before calling here. */
463 if (GET_CODE (x
) == REG
)
466 /* This is a MEMA operand -- it's free. */
467 if (GET_CODE (x
) == CONST_INT
469 && INTVAL (x
) < 4096)
472 if (GET_CODE (x
) == PLUS
)
474 rtx base
= XEXP (x
, 0);
475 rtx offset
= XEXP (x
, 1);
477 if (GET_CODE (base
) == SUBREG
)
478 base
= SUBREG_REG (base
);
479 if (GET_CODE (offset
) == SUBREG
)
480 offset
= SUBREG_REG (offset
);
482 if (GET_CODE (base
) == REG
)
484 if (GET_CODE (offset
) == REG
)
486 if (GET_CODE (offset
) == CONST_INT
)
488 if ((unsigned)INTVAL (offset
) < 2047)
492 if (CONSTANT_P (offset
))
495 if (GET_CODE (base
) == PLUS
|| GET_CODE (base
) == MULT
)
498 /* This is an invalid address. The return value doesn't matter, but
499 for convenience we make this more expensive than anything else. */
502 if (GET_CODE (x
) == MULT
)
505 /* Symbol_refs and other unrecognized addresses are cost 4. */
509 /* Emit insns to move operands[1] into operands[0].
511 Return 1 if we have written out everything that needs to be done to
512 do the move. Otherwise, return 0 and the caller will emit the move
516 emit_move_sequence (operands
, mode
)
518 enum machine_mode mode
;
520 /* We can only store registers to memory. */
522 if (GET_CODE (operands
[0]) == MEM
&& GET_CODE (operands
[1]) != REG
523 && (operands
[1] != const0_rtx
|| current_function_args_size
524 || current_function_varargs
|| current_function_stdarg
525 || rtx_equal_function_value_matters
))
526 /* Here we use the same test as movsi+1 pattern -- see i960.md. */
527 operands
[1] = force_reg (mode
, operands
[1]);
529 /* Storing multi-word values in unaligned hard registers to memory may
530 require a scratch since we have to store them a register at a time and
531 adding 4 to the memory address may not yield a valid insn. */
532 /* ??? We don't always need the scratch, but that would complicate things.
534 /* ??? We must also handle stores to pseudos here, because the pseudo may be
535 replaced with a MEM later. This would be cleaner if we didn't have
536 a separate pattern for unaligned DImode/TImode stores. */
537 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
538 && (GET_CODE (operands
[0]) == MEM
539 || (GET_CODE (operands
[0]) == REG
540 && REGNO (operands
[0]) >= FIRST_PSEUDO_REGISTER
))
541 && GET_CODE (operands
[1]) == REG
542 && REGNO (operands
[1]) < FIRST_PSEUDO_REGISTER
543 && ! HARD_REGNO_MODE_OK (REGNO (operands
[1]), mode
))
545 emit_insn (gen_rtx_PARALLEL
548 gen_rtx_SET (VOIDmode
, operands
[0], operands
[1]),
549 gen_rtx_CLOBBER (VOIDmode
,
550 gen_rtx_SCRATCH (Pmode
)))));
557 /* Output assembler to move a double word value. */
560 i960_output_move_double (dst
, src
)
565 if (GET_CODE (dst
) == REG
566 && GET_CODE (src
) == REG
)
568 if ((REGNO (src
) & 1)
569 || (REGNO (dst
) & 1))
571 /* We normally copy the low-numbered register first. However, if
572 the second source register is the same as the first destination
573 register, we must copy in the opposite order. */
574 if (REGNO (src
) + 1 == REGNO (dst
))
575 return "mov %D1,%D0\n\tmov %1,%0";
577 return "mov %1,%0\n\tmov %D1,%D0";
582 else if (GET_CODE (dst
) == REG
583 && GET_CODE (src
) == CONST_INT
584 && CONST_OK_FOR_LETTER_P (INTVAL (src
), 'I'))
587 return "mov %1,%0\n\tmov 0,%D0";
591 else if (GET_CODE (dst
) == REG
592 && GET_CODE (src
) == MEM
)
596 /* One can optimize a few cases here, but you have to be
597 careful of clobbering registers used in the address and
601 operands
[2] = gen_rtx_REG (Pmode
, REGNO (dst
) + 1);
602 operands
[3] = gen_rtx_MEM (word_mode
, operands
[2]);
603 operands
[4] = adjust_address (operands
[3], word_mode
,
606 ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0", operands
);
612 else if (GET_CODE (dst
) == MEM
613 && GET_CODE (src
) == REG
)
618 operands
[1] = adjust_address (dst
, word_mode
, UNITS_PER_WORD
);
619 if (! memory_address_p (word_mode
, XEXP (operands
[1], 0)))
622 output_asm_insn ("st %2,%0\n\tst %D2,%1", operands
);
631 /* Output assembler to move a double word zero. */
634 i960_output_move_double_zero (dst
)
641 operands
[1] = adjust_address (dst
, word_mode
, 4);
642 output_asm_insn ("st g14,%0\n\tst g14,%1", operands
);
647 /* Output assembler to move a quad word value. */
650 i960_output_move_quad (dst
, src
)
655 if (GET_CODE (dst
) == REG
656 && GET_CODE (src
) == REG
)
658 if ((REGNO (src
) & 3)
659 || (REGNO (dst
) & 3))
661 /* We normally copy starting with the low numbered register.
662 However, if there is an overlap such that the first dest reg
663 is <= the last source reg but not < the first source reg, we
664 must copy in the opposite order. */
665 if (REGNO (dst
) <= REGNO (src
) + 3
666 && REGNO (dst
) >= REGNO (src
))
667 return "mov %F1,%F0\n\tmov %E1,%E0\n\tmov %D1,%D0\n\tmov %1,%0";
669 return "mov %1,%0\n\tmov %D1,%D0\n\tmov %E1,%E0\n\tmov %F1,%F0";
674 else if (GET_CODE (dst
) == REG
675 && GET_CODE (src
) == CONST_INT
676 && CONST_OK_FOR_LETTER_P (INTVAL (src
), 'I'))
679 return "mov %1,%0\n\tmov 0,%D0\n\tmov 0,%E0\n\tmov 0,%F0";
683 else if (GET_CODE (dst
) == REG
684 && GET_CODE (src
) == MEM
)
688 /* One can optimize a few cases here, but you have to be
689 careful of clobbering registers used in the address and
693 operands
[2] = gen_rtx_REG (Pmode
, REGNO (dst
) + 3);
694 operands
[3] = gen_rtx_MEM (word_mode
, operands
[2]);
696 = adjust_address (operands
[3], word_mode
, UNITS_PER_WORD
);
698 = adjust_address (operands
[4], word_mode
, UNITS_PER_WORD
);
700 = adjust_address (operands
[5], word_mode
, UNITS_PER_WORD
);
701 output_asm_insn ("lda %1,%2\n\tld %3,%0\n\tld %4,%D0\n\tld %5,%E0\n\tld %6,%F0", operands
);
707 else if (GET_CODE (dst
) == MEM
708 && GET_CODE (src
) == REG
)
713 operands
[1] = adjust_address (dst
, word_mode
, UNITS_PER_WORD
);
714 operands
[2] = adjust_address (dst
, word_mode
, 2 * UNITS_PER_WORD
);
715 operands
[3] = adjust_address (dst
, word_mode
, 3 * UNITS_PER_WORD
);
716 if (! memory_address_p (word_mode
, XEXP (operands
[3], 0)))
719 output_asm_insn ("st %4,%0\n\tst %D4,%1\n\tst %E4,%2\n\tst %F4,%3", operands
);
728 /* Output assembler to move a quad word zero. */
731 i960_output_move_quad_zero (dst
)
738 operands
[1] = adjust_address (dst
, word_mode
, 4);
739 operands
[2] = adjust_address (dst
, word_mode
, 8);
740 operands
[3] = adjust_address (dst
, word_mode
, 12);
741 output_asm_insn ("st g14,%0\n\tst g14,%1\n\tst g14,%2\n\tst g14,%3", operands
);
747 /* Emit insns to load a constant to non-floating point registers.
748 Uses several strategies to try to use as few insns as possible. */
751 i960_output_ldconst (dst
, src
)
752 register rtx dst
, src
;
755 register unsigned rsrc2
;
756 enum machine_mode mode
= GET_MODE (dst
);
759 operands
[0] = operands
[2] = dst
;
760 operands
[1] = operands
[3] = src
;
762 /* Anything that isn't a compile time constant, such as a SYMBOL_REF,
763 must be a ldconst insn. */
765 if (GET_CODE (src
) != CONST_INT
&& GET_CODE (src
) != CONST_DOUBLE
)
767 output_asm_insn ("ldconst %1,%0", operands
);
770 else if (mode
== XFmode
)
776 if (fp_literal_zero (src
, XFmode
))
779 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
780 REAL_VALUE_TO_TARGET_LONG_DOUBLE (d
, value_long
);
782 output_asm_insn ("# ldconst %1,%0",operands
);
784 for (i
= 0; i
< 3; i
++)
786 operands
[0] = gen_rtx_REG (SImode
, REGNO (dst
) + i
);
787 operands
[1] = GEN_INT (value_long
[i
]);
788 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
794 else if (mode
== DFmode
)
798 if (fp_literal_zero (src
, DFmode
))
801 split_double (src
, &first
, &second
);
803 output_asm_insn ("# ldconst %1,%0",operands
);
805 operands
[0] = gen_rtx_REG (SImode
, REGNO (dst
));
807 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
809 operands
[0] = gen_rtx_REG (SImode
, REGNO (dst
) + 1);
810 operands
[1] = second
;
811 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
815 else if (mode
== SFmode
)
820 REAL_VALUE_FROM_CONST_DOUBLE (d
, src
);
821 REAL_VALUE_TO_TARGET_SINGLE (d
, value
);
823 output_asm_insn ("# ldconst %1,%0",operands
);
824 operands
[0] = gen_rtx_REG (SImode
, REGNO (dst
));
825 operands
[1] = GEN_INT (value
);
826 output_asm_insn (i960_output_ldconst (operands
[0], operands
[1]),
830 else if (mode
== TImode
)
832 /* ??? This is currently not handled at all. */
835 /* Note: lowest order word goes in lowest numbered reg. */
836 rsrc1
= INTVAL (src
);
837 if (rsrc1
>= 0 && rsrc1
< 32)
840 output_asm_insn ("movq\t0,%0\t# ldconstq %1,%0",operands
);
841 /* Go pick up the low-order word. */
843 else if (mode
== DImode
)
845 rtx upperhalf
, lowerhalf
, xoperands
[2];
847 if (GET_CODE (src
) == CONST_DOUBLE
|| GET_CODE (src
) == CONST_INT
)
848 split_double (src
, &lowerhalf
, &upperhalf
);
853 /* Note: lowest order word goes in lowest numbered reg. */
854 /* Numbers from 0 to 31 can be handled with a single insn. */
855 rsrc1
= INTVAL (lowerhalf
);
856 if (upperhalf
== const0_rtx
&& rsrc1
>= 0 && rsrc1
< 32)
859 /* Output the upper half with a recursive call. */
860 xoperands
[0] = gen_rtx_REG (SImode
, REGNO (dst
) + 1);
861 xoperands
[1] = upperhalf
;
862 output_asm_insn (i960_output_ldconst (xoperands
[0], xoperands
[1]),
864 /* The lower word is emitted as normally. */
868 rsrc1
= INTVAL (src
);
874 else if (mode
== HImode
)
883 /* ldconst 0..31,X -> mov 0..31,X */
886 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
891 /* ldconst 32..63,X -> add 31,nn,X */
894 if (i960_last_insn_type
== I_TYPE_REG
&& TARGET_C_SERIES
)
896 operands
[1] = GEN_INT (rsrc1
- 31);
897 output_asm_insn ("addo\t31,%1,%0\t# ldconst %3,%0", operands
);
903 /* ldconst -1..-31 -> sub 0,0..31,X */
906 /* return 'sub -(%1),0,%0' */
907 operands
[1] = GEN_INT (- rsrc1
);
908 output_asm_insn ("subo\t%1,0,%0\t# ldconst %3,%0", operands
);
912 /* ldconst -32 -> not 31,X */
915 operands
[1] = GEN_INT (~rsrc1
);
916 output_asm_insn ("not\t%1,%0 # ldconst %3,%0", operands
);
921 /* If const is a single bit. */
922 if (bitpos (rsrc1
) >= 0)
924 operands
[1] = GEN_INT (bitpos (rsrc1
));
925 output_asm_insn ("setbit\t%1,0,%0\t# ldconst %3,%0", operands
);
929 /* If const is a bit string of less than 6 bits (1..31 shifted). */
934 if (bitstr (rsrc1
, &s
, &e
) < 6)
936 rsrc2
= ((unsigned int) rsrc1
) >> s
;
937 operands
[1] = GEN_INT (rsrc2
);
938 operands
[2] = GEN_INT (s
);
939 output_asm_insn ("shlo\t%2,%1,%0\t# ldconst %3,%0", operands
);
944 /* Unimplemented cases:
945 const is in range 0..31 but rotated around end of word:
946 ror 31,3,g0 -> ldconst 0xe0000003,g0
948 and any 2 instruction cases that might be worthwhile */
950 output_asm_insn ("ldconst %1,%0", operands
);
954 /* Determine if there is an opportunity for a bypass optimization.
955 Bypass succeeds on the 960K* if the destination of the previous
956 instruction is the second operand of the current instruction.
957 Bypass always succeeds on the C*.
959 Return 1 if the pattern should interchange the operands.
961 CMPBR_FLAG is true if this is for a compare-and-branch insn.
962 OP1 and OP2 are the two source operands of a 3 operand insn. */
965 i960_bypass (insn
, op1
, op2
, cmpbr_flag
)
966 register rtx insn
, op1
, op2
;
969 register rtx prev_insn
, prev_dest
;
974 /* Can't do this if op1 isn't a register. */
978 /* Can't do this for a compare-and-branch if both ops aren't regs. */
979 if (cmpbr_flag
&& ! REG_P (op2
))
982 prev_insn
= prev_real_insn (insn
);
984 if (prev_insn
&& GET_CODE (prev_insn
) == INSN
985 && GET_CODE (PATTERN (prev_insn
)) == SET
)
987 prev_dest
= SET_DEST (PATTERN (prev_insn
));
988 if ((GET_CODE (prev_dest
) == REG
&& REGNO (prev_dest
) == REGNO (op1
))
989 || (GET_CODE (prev_dest
) == SUBREG
990 && GET_CODE (SUBREG_REG (prev_dest
)) == REG
991 && REGNO (SUBREG_REG (prev_dest
)) == REGNO (op1
)))
997 /* Output the code which declares the function name. This also handles
998 leaf routines, which have special requirements, and initializes some
1002 i960_function_name_declare (file
, name
, fndecl
)
1011 /* Increment global return label. */
1015 /* Compute whether tail calls and leaf routine optimizations can be performed
1016 for this function. */
1018 if (TARGET_TAILCALL
)
1023 if (TARGET_LEAFPROC
)
1028 /* Even if nobody uses extra parms, can't have leafproc or tail calls if
1029 argblock, because argblock uses g14 implicitly. */
1031 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
1037 /* See if caller passes in an address to return value. */
1039 if (aggregate_value_p (DECL_RESULT (fndecl
)))
1045 /* Can not use tail calls or make this a leaf routine if there is a non
1048 if (get_frame_size () != 0)
1051 /* I don't understand this condition, and do not think that it is correct.
1052 Apparently this is just checking whether the frame pointer is used, and
1053 we can't trust regs_ever_live[fp] since it is (almost?) always set. */
1056 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1057 if (GET_CODE (insn
) == INSN
1058 && reg_mentioned_p (frame_pointer_rtx
, insn
))
1064 /* Check for CALL insns. Can not be a leaf routine if there are any. */
1067 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1068 if (GET_CODE (insn
) == CALL_INSN
)
1074 /* Can not be a leaf routine if any non-call clobbered registers are
1075 used in this function. */
1078 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1079 if (regs_ever_live
[i
]
1080 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12)))
1082 /* Global registers. */
1083 if (i
< 16 && i
> 7 && i
!= 13)
1085 /* Local registers. */
1090 /* Now choose a leaf return register, if we can find one, and if it is
1091 OK for this to be a leaf routine. */
1093 i960_leaf_ret_reg
= -1;
1095 if (optimize
&& leaf_proc_ok
)
1097 for (i960_leaf_ret_reg
= -1, i
= 0; i
< 8; i
++)
1098 if (regs_ever_live
[i
] == 0)
1100 i960_leaf_ret_reg
= i
;
1101 regs_ever_live
[i
] = 1;
1106 /* Do this after choosing the leaf return register, so it will be listed
1107 if one was chosen. */
1109 fprintf (file
, "\t# Function '%s'\n", (name
[0] == '*' ? &name
[1] : name
));
1110 fprintf (file
, "\t# Registers used: ");
1112 for (i
= 0, j
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1114 if (regs_ever_live
[i
])
1116 fprintf (file
, "%s%s ", reg_names
[i
], call_used_regs
[i
] ? "" : "*");
1118 if (i
> 15 && j
== 0)
1120 fprintf (file
,"\n\t#\t\t ");
1126 fprintf (file
, "\n");
1128 if (i960_leaf_ret_reg
>= 0)
1130 /* Make it a leaf procedure. */
1132 if (TREE_PUBLIC (fndecl
))
1133 fprintf (file
,"\t.globl\t%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
1135 fprintf (file
, "\t.leafproc\t");
1136 assemble_name (file
, name
);
1137 fprintf (file
, ",%s.lf\n", (name
[0] == '*' ? &name
[1] : name
));
1138 ASM_OUTPUT_LABEL (file
, name
);
1139 fprintf (file
, "\tlda Li960R%d,g14\n", ret_label
);
1140 fprintf (file
, "%s.lf:\n", (name
[0] == '*' ? &name
[1] : name
));
1141 fprintf (file
, "\tmov g14,g%d\n", i960_leaf_ret_reg
);
1143 if (TARGET_C_SERIES
)
1145 fprintf (file
, "\tlda 0,g14\n");
1146 i960_last_insn_type
= I_TYPE_MEM
;
1150 fprintf (file
, "\tmov 0,g14\n");
1151 i960_last_insn_type
= I_TYPE_REG
;
1156 ASM_OUTPUT_LABEL (file
, name
);
1157 i960_last_insn_type
= I_TYPE_CTRL
;
1161 /* Compute and return the frame size. */
1164 compute_frame_size (size
)
1168 int outgoing_args_size
= current_function_outgoing_args_size
;
1170 /* The STARTING_FRAME_OFFSET is totally hidden to us as far
1171 as size is concerned. */
1172 actual_fsize
= (size
+ 15) & -16;
1173 actual_fsize
+= (outgoing_args_size
+ 15) & -16;
1175 return actual_fsize
;
1178 /* Here register group is range of registers which can be moved by
1179 one i960 instruction. */
1187 static int i960_form_reg_groups
PARAMS ((int, int, int *, int, struct reg_group
*));
1188 static int i960_reg_group_compare
PARAMS ((const void *, const void *));
1189 static int i960_split_reg_group
PARAMS ((struct reg_group
*, int, int));
1190 static void i960_arg_size_and_align
PARAMS ((enum machine_mode
, tree
, int *, int *));
1192 /* The following functions forms the biggest as possible register
1193 groups with registers in STATE. REGS contain states of the
1194 registers in range [start, finish_reg). The function returns the
1195 number of groups formed. */
1197 i960_form_reg_groups (start_reg
, finish_reg
, regs
, state
, reg_groups
)
1202 struct reg_group
*reg_groups
;
1207 for (i
= start_reg
; i
< finish_reg
; )
1209 if (regs
[i
] != state
)
1214 else if (i
% 2 != 0 || regs
[i
+ 1] != state
)
1215 reg_groups
[nw
].length
= 1;
1216 else if (i
% 4 != 0 || regs
[i
+ 2] != state
)
1217 reg_groups
[nw
].length
= 2;
1218 else if (regs
[i
+ 3] != state
)
1219 reg_groups
[nw
].length
= 3;
1221 reg_groups
[nw
].length
= 4;
1222 reg_groups
[nw
].start_reg
= i
;
1223 i
+= reg_groups
[nw
].length
;
1229 /* We sort register winodws in descending order by length. */
1231 i960_reg_group_compare (group1
, group2
)
1235 const struct reg_group
*w1
= group1
;
1236 const struct reg_group
*w2
= group2
;
1238 if (w1
->length
> w2
->length
)
1240 else if (w1
->length
< w2
->length
)
1246 /* Split the first register group in REG_GROUPS on subgroups one of
1247 which will contain SUBGROUP_LENGTH registers. The function
1248 returns new number of winodws. */
1250 i960_split_reg_group (reg_groups
, nw
, subgroup_length
)
1251 struct reg_group
*reg_groups
;
1253 int subgroup_length
;
1255 if (subgroup_length
< reg_groups
->length
- subgroup_length
)
1256 /* This guarantees correct alignments of the two subgroups for
1257 i960 (see spliting for the group length 2, 3, 4). More
1258 generalized algorithm would require splitting the group more
1260 subgroup_length
= reg_groups
->length
- subgroup_length
;
1261 /* More generalized algorithm would require to try merging
1262 subgroups here. But in case i960 it always results in failure
1263 because of register group alignment. */
1264 reg_groups
[nw
].length
= reg_groups
->length
- subgroup_length
;
1265 reg_groups
[nw
].start_reg
= reg_groups
->start_reg
+ subgroup_length
;
1267 reg_groups
->length
= subgroup_length
;
1268 qsort (reg_groups
, nw
, sizeof (struct reg_group
), i960_reg_group_compare
);
1272 /* Output code for the function prologue. */
1275 i960_output_function_prologue (file
, size
)
1279 register int i
, j
, nr
;
1280 int n_saved_regs
= 0;
1281 int n_remaining_saved_regs
;
1282 HOST_WIDE_INT lvar_size
;
1283 HOST_WIDE_INT actual_fsize
, offset
;
1285 struct reg_group
*g
, *l
;
1287 /* -1 if reg must be saved on proc entry, 0 if available, 1 if saved
1289 int regs
[FIRST_PSEUDO_REGISTER
];
1290 /* All global registers (which must be saved) divided by groups. */
1291 struct reg_group global_reg_groups
[16];
1292 /* All local registers (which are available) divided by groups. */
1293 struct reg_group local_reg_groups
[16];
1296 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1297 if (regs_ever_live
[i
]
1298 && ((! call_used_regs
[i
]) || (i
> 7 && i
< 12))
1299 /* No need to save the static chain pointer. */
1300 && ! (i
== STATIC_CHAIN_REGNUM
&& current_function_needs_context
))
1303 /* Count global registers that need saving. */
1310 n_remaining_saved_regs
= n_saved_regs
;
1312 epilogue_string
[0] = '\0';
1316 /* When profiling, we may use registers 20 to 27 to save arguments, so
1317 they can't be used here for saving globals. J is the number of
1318 argument registers the mcount call will save. */
1319 for (j
= 7; j
>= 0 && ! regs_ever_live
[j
]; j
--)
1322 for (i
= 20; i
<= j
+ 20; i
++)
1326 gnw
= i960_form_reg_groups (0, 16, regs
, -1, global_reg_groups
);
1327 lnw
= i960_form_reg_groups (19, 32, regs
, 0, local_reg_groups
);
1328 qsort (global_reg_groups
, gnw
, sizeof (struct reg_group
),
1329 i960_reg_group_compare
);
1330 qsort (local_reg_groups
, lnw
, sizeof (struct reg_group
),
1331 i960_reg_group_compare
);
1332 for (g
= global_reg_groups
, l
= local_reg_groups
; lnw
!= 0 && gnw
!= 0;)
1334 if (g
->length
== l
->length
)
1336 fprintf (file
, "\tmov%s %s,%s\n",
1337 ((g
->length
== 4) ? "q" :
1338 (g
->length
== 3) ? "t" :
1339 (g
->length
== 2) ? "l" : ""),
1340 reg_names
[(unsigned char) g
->start_reg
],
1341 reg_names
[(unsigned char) l
->start_reg
]);
1342 sprintf (tmpstr
, "\tmov%s %s,%s\n",
1343 ((g
->length
== 4) ? "q" :
1344 (g
->length
== 3) ? "t" :
1345 (g
->length
== 2) ? "l" : ""),
1346 reg_names
[(unsigned char) l
->start_reg
],
1347 reg_names
[(unsigned char) g
->start_reg
]);
1348 strcat (epilogue_string
, tmpstr
);
1349 n_remaining_saved_regs
-= g
->length
;
1350 for (i
= 0; i
< g
->length
; i
++)
1352 regs
[i
+ g
->start_reg
] = 1;
1353 regs
[i
+ l
->start_reg
] = -1;
1354 regs_ever_live
[i
+ l
->start_reg
] = 1;
1361 else if (g
->length
> l
->length
)
1362 gnw
= i960_split_reg_group (g
, gnw
, l
->length
);
1364 lnw
= i960_split_reg_group (l
, lnw
, g
->length
);
1367 actual_fsize
= compute_frame_size (size
) + 4 * n_remaining_saved_regs
;
1369 /* ??? The 1.2.1 compiler does this also. This is meant to round the frame
1370 size up to the nearest multiple of 16. I don't know whether this is
1371 necessary, or even desirable.
1373 The frame pointer must be aligned, but the call instruction takes care of
1374 that. If we leave the stack pointer unaligned, we may save a little on
1375 dynamic stack allocation. And we don't lose, at least according to the
1377 actual_fsize
= (actual_fsize
+ 15) & ~0xF;
1380 /* Check stack limit if necessary. */
1381 if (current_function_limit_stack
)
1383 rtx min_stack
= stack_limit_rtx
;
1384 if (actual_fsize
!= 0)
1385 min_stack
= plus_constant (stack_limit_rtx
, -actual_fsize
);
1387 /* Now, emulate a little bit of reload. We want to turn 'min_stack'
1388 into an arith_operand. Use register 20 as the temporary. */
1389 if (legitimate_address_p (Pmode
, min_stack
, 1)
1390 && !arith_operand (min_stack
, Pmode
))
1392 rtx tmp
= gen_rtx_MEM (Pmode
, min_stack
);
1393 fputs ("\tlda\t", file
);
1394 i960_print_operand (file
, tmp
, 0);
1395 fputs (",r4\n", file
);
1396 min_stack
= gen_rtx_REG (Pmode
, 20);
1398 if (arith_operand (min_stack
, Pmode
))
1400 fputs ("\tcmpo\tsp,", file
);
1401 i960_print_operand (file
, min_stack
, 0);
1402 fputs ("\n\tfaultge.f\n", file
);
1405 warning ("stack limit expression is not supported");
1408 /* Allocate space for register save and locals. */
1409 if (actual_fsize
> 0)
1411 if (actual_fsize
< 32)
1412 fprintf (file
, "\taddo %d,sp,sp\n", actual_fsize
);
1414 fprintf (file
, "\tlda\t%d(sp),sp\n", actual_fsize
);
1417 /* Take hardware register save area created by the call instruction
1418 into account, but store them before the argument block area. */
1419 lvar_size
= actual_fsize
- compute_frame_size (0) - n_remaining_saved_regs
* 4;
1420 offset
= STARTING_FRAME_OFFSET
+ lvar_size
;
1421 /* Save registers on stack if needed. */
1422 /* ??? Is it worth to use the same algorithm as one for saving
1423 global registers in local registers? */
1424 for (i
= 0, j
= n_remaining_saved_regs
; j
> 0 && i
< 16; i
++)
1431 if (i
<= 14 && i
% 2 == 0 && regs
[i
+1] == -1 && offset
% 2 == 0)
1434 if (nr
== 2 && i
<= 12 && i
% 4 == 0 && regs
[i
+2] == -1
1438 if (nr
== 3 && regs
[i
+3] == -1)
1441 fprintf (file
,"\tst%s %s,%d(fp)\n",
1444 (nr
== 2) ? "l" : ""),
1445 reg_names
[i
], offset
);
1446 sprintf (tmpstr
,"\tld%s %d(fp),%s\n",
1449 (nr
== 2) ? "l" : ""),
1450 offset
, reg_names
[i
]);
1451 strcat (epilogue_string
, tmpstr
);
1457 if (actual_fsize
== 0)
1460 fprintf (file
, "\t#Prologue stats:\n");
1461 fprintf (file
, "\t# Total Frame Size: %d bytes\n", actual_fsize
);
1464 fprintf (file
, "\t# Local Variable Size: %d bytes\n", lvar_size
);
1466 fprintf (file
, "\t# Register Save Size: %d regs, %d bytes\n",
1467 n_saved_regs
, n_saved_regs
* 4);
1468 fprintf (file
, "\t#End Prologue#\n");
1471 /* Output code for the function profiler. */
1474 output_function_profiler (file
, labelno
)
1478 /* The last used parameter register. */
1480 int i
, j
, increment
;
1481 int varargs_stdarg_function
1482 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1484 /* Figure out the last used parameter register. The proper thing to do
1485 is to walk incoming args of the function. A function might have live
1486 parameter registers even if it has no incoming args. Note that we
1487 don't have to save parameter registers g8 to g11 because they are
1490 /* See also output_function_prologue, which tries to use local registers
1491 for preserved call-saved global registers. */
1493 for (last_parm_reg
= 7;
1494 last_parm_reg
>= 0 && ! regs_ever_live
[last_parm_reg
];
1498 /* Save parameter registers in regs r4 (20) to r11 (27). */
1500 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1502 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1504 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1506 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1511 fprintf (file
, "\tmov%s g%d,r%d\n",
1512 (increment
== 4 ? "q" : increment
== 3 ? "t"
1513 : increment
== 2 ? "l": ""), i
, j
);
1516 /* If this function uses the arg pointer, then save it in r3 and then
1519 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1520 fprintf (file
, "\tmov g14,r3\n\tmov 0,g14\n");
1522 /* Load location address into g0 and call mcount. */
1524 fprintf (file
, "\tlda\tLP%d,g0\n\tcallx\tmcount\n", labelno
);
1526 /* If this function uses the arg pointer, restore it. */
1528 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1529 fprintf (file
, "\tmov r3,g14\n");
1531 /* Restore parameter registers. */
1533 for (i
= 0, j
= 4; i
<= last_parm_reg
; i
+= increment
, j
+= increment
)
1535 if (i
% 4 == 0 && (last_parm_reg
- i
) >= 3)
1537 else if (i
% 4 == 0 && (last_parm_reg
- i
) >= 2)
1539 else if (i
% 2 == 0 && (last_parm_reg
- i
) >= 1)
1544 fprintf (file
, "\tmov%s r%d,g%d\n",
1545 (increment
== 4 ? "q" : increment
== 3 ? "t"
1546 : increment
== 2 ? "l": ""), j
, i
);
1550 /* Output code for the function epilogue. */
1553 i960_output_function_epilogue (file
, size
)
1555 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
1557 if (i960_leaf_ret_reg
>= 0)
1559 fprintf (file
, "Li960R%d: ret\n", ret_label
);
1563 if (*epilogue_string
== 0)
1567 /* Emit a return insn, but only if control can fall through to here. */
1569 tmp
= get_last_insn ();
1572 if (GET_CODE (tmp
) == BARRIER
)
1574 if (GET_CODE (tmp
) == CODE_LABEL
)
1576 if (GET_CODE (tmp
) == JUMP_INSN
)
1578 if (GET_CODE (PATTERN (tmp
)) == RETURN
)
1582 if (GET_CODE (tmp
) == NOTE
)
1584 tmp
= PREV_INSN (tmp
);
1589 fprintf (file
, "Li960R%d: ret\n", ret_label
);
1593 fprintf (file
, "Li960R%d:\n", ret_label
);
1595 fprintf (file
, "\t#EPILOGUE#\n");
1597 /* Output the string created by the prologue which will restore all
1598 registers saved by the prologue. */
1600 if (epilogue_string
[0] != '\0')
1601 fprintf (file
, "%s", epilogue_string
);
1603 /* Must clear g14 on return if this function set it.
1604 Only varargs/stdarg functions modify g14. */
1606 if (VARARGS_STDARG_FUNCTION (current_function_decl
))
1607 fprintf (file
, "\tmov 0,g14\n");
1609 fprintf (file
, "\tret\n");
1610 fprintf (file
, "\t#End Epilogue#\n");
1613 /* Output code for a call insn. */
1616 i960_output_call_insn (target
, argsize_rtx
, arg_pointer
, insn
)
1617 register rtx target
, argsize_rtx
, arg_pointer
, insn
;
1619 int argsize
= INTVAL (argsize_rtx
);
1620 rtx nexti
= next_real_insn (insn
);
1622 int varargs_stdarg_function
1623 = VARARGS_STDARG_FUNCTION (current_function_decl
);
1625 operands
[0] = target
;
1626 operands
[1] = arg_pointer
;
1628 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1629 output_asm_insn ("mov g14,r3", operands
);
1632 output_asm_insn ("lda %a1,g14", operands
);
1633 else if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1634 output_asm_insn ("mov 0,g14", operands
);
1636 /* The code used to assume that calls to SYMBOL_REFs could not be more
1637 than 24 bits away (b vs bx, callj vs callx). This is not true. This
1638 feature is now implemented by relaxing in the GNU linker. It can convert
1639 bx to b if in range, and callx to calls/call/balx/bal as appropriate. */
1641 /* Nexti could be zero if the called routine is volatile. */
1642 if (optimize
&& (*epilogue_string
== 0) && argsize
== 0 && tail_call_ok
1643 && (nexti
== 0 || GET_CODE (PATTERN (nexti
)) == RETURN
))
1645 /* Delete following return insn. */
1646 if (nexti
&& no_labels_between_p (insn
, nexti
))
1647 delete_insn (nexti
);
1648 output_asm_insn ("bx %0", operands
);
1649 return "# notreached";
1652 output_asm_insn ("callx %0", operands
);
1654 /* If the caller sets g14 to the address of the argblock, then the caller
1655 must clear it after the return. */
1657 if (current_function_args_size
!= 0 || varargs_stdarg_function
)
1658 output_asm_insn ("mov r3,g14", operands
);
1659 else if (argsize
> 48)
1660 output_asm_insn ("mov 0,g14", operands
);
1665 /* Output code for a return insn. */
1668 i960_output_ret_insn (insn
)
1671 static char lbuf
[20];
1673 if (*epilogue_string
!= 0)
1675 if (! TARGET_CODE_ALIGN
&& next_real_insn (insn
) == 0)
1678 sprintf (lbuf
, "b Li960R%d", ret_label
);
1682 /* Must clear g14 on return if this function set it.
1683 Only varargs/stdarg functions modify g14. */
1685 if (VARARGS_STDARG_FUNCTION (current_function_decl
))
1686 output_asm_insn ("mov 0,g14", 0);
1688 if (i960_leaf_ret_reg
>= 0)
1690 sprintf (lbuf
, "bx (%s)", reg_names
[i960_leaf_ret_reg
]);
1696 /* Print the operand represented by rtx X formatted by code CODE. */
1699 i960_print_operand (file
, x
, code
)
1704 enum rtx_code rtxcode
= x
? GET_CODE (x
) : NIL
;
1711 /* Second reg of a double or quad. */
1712 fprintf (file
, "%s", reg_names
[REGNO (x
)+1]);
1716 /* Third reg of a quad. */
1717 fprintf (file
, "%s", reg_names
[REGNO (x
)+2]);
1721 /* Fourth reg of a quad. */
1722 fprintf (file
, "%s", reg_names
[REGNO (x
)+3]);
1726 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
1734 else if (rtxcode
== MEM
)
1736 output_address (XEXP (x
, 0));
1739 else if (rtxcode
== CONST_INT
)
1741 HOST_WIDE_INT val
= INTVAL (x
);
1744 if (val
> 9999 || val
< -999)
1745 fprintf (file
, "0x%x", val
);
1747 fprintf (file
, "%d", val
);
1750 else if (rtxcode
== CONST_DOUBLE
)
1755 if (x
== CONST0_RTX (GET_MODE (x
)))
1757 fprintf (file
, "0f0.0");
1760 else if (x
== CONST1_RTX (GET_MODE (x
)))
1762 fprintf (file
, "0f1.0");
1766 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
1767 REAL_VALUE_TO_DECIMAL (d
, "%#g", dstr
);
1768 fprintf (file
, "0f%s", dstr
);
1775 /* Branch or jump, depending on assembler. */
1776 if (TARGET_ASM_COMPAT
)
1783 /* Sign of condition. */
1784 if ((rtxcode
== EQ
) || (rtxcode
== NE
) || (rtxcode
== GTU
)
1785 || (rtxcode
== LTU
) || (rtxcode
== GEU
) || (rtxcode
== LEU
))
1787 else if ((rtxcode
== GT
) || (rtxcode
== LT
)
1788 || (rtxcode
== GE
) || (rtxcode
== LE
))
1795 /* Inverted condition. */
1796 rtxcode
= reverse_condition (rtxcode
);
1800 /* Inverted condition w/ reversed operands. */
1801 rtxcode
= reverse_condition (rtxcode
);
1805 /* Reversed operand condition. */
1806 rtxcode
= swap_condition (rtxcode
);
1810 /* Normal condition. */
1812 if (rtxcode
== EQ
) { fputs ("e", file
); return; }
1813 else if (rtxcode
== NE
) { fputs ("ne", file
); return; }
1814 else if (rtxcode
== GT
) { fputs ("g", file
); return; }
1815 else if (rtxcode
== GTU
) { fputs ("g", file
); return; }
1816 else if (rtxcode
== LT
) { fputs ("l", file
); return; }
1817 else if (rtxcode
== LTU
) { fputs ("l", file
); return; }
1818 else if (rtxcode
== GE
) { fputs ("ge", file
); return; }
1819 else if (rtxcode
== GEU
) { fputs ("ge", file
); return; }
1820 else if (rtxcode
== LE
) { fputs ("le", file
); return; }
1821 else if (rtxcode
== LEU
) { fputs ("le", file
); return; }
1826 /* For conditional branches, substitute ".t" or ".f". */
1827 if (TARGET_BRANCH_PREDICT
)
1829 x
= find_reg_note (current_output_insn
, REG_BR_PROB
, 0);
1832 int pred_val
= INTVAL (XEXP (x
, 0));
1833 fputs ((pred_val
< REG_BR_PROB_BASE
/ 2 ? ".f" : ".t"), file
);
1839 output_addr_const (file
, x
);
1849 /* Print a memory address as an operand to reference that memory location.
1851 This is exactly the same as legitimate_address_p, except that it the prints
1852 addresses instead of recognizing them. */
1855 i960_print_operand_addr (file
, addr
)
1867 if (GET_CODE (addr
) == REG
)
1869 else if (CONSTANT_P (addr
))
1871 else if (GET_CODE (addr
) == PLUS
)
1875 op0
= XEXP (addr
, 0);
1876 op1
= XEXP (addr
, 1);
1878 if (GET_CODE (op0
) == REG
)
1881 if (GET_CODE (op1
) == REG
)
1883 else if (CONSTANT_P (op1
))
1888 else if (GET_CODE (op0
) == PLUS
)
1890 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
1892 ireg
= XEXP (XEXP (op0
, 0), 0);
1893 scale
= XEXP (XEXP (op0
, 0), 1);
1894 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1896 breg
= XEXP (op0
, 1);
1902 else if (GET_CODE (XEXP (op0
, 0)) == REG
)
1904 breg
= XEXP (op0
, 0);
1905 if (GET_CODE (XEXP (op0
, 1)) == REG
)
1907 ireg
= XEXP (op0
, 1);
1916 else if (GET_CODE (op0
) == MULT
)
1918 ireg
= XEXP (op0
, 0);
1919 scale
= XEXP (op0
, 1);
1920 if (GET_CODE (op1
) == REG
)
1922 else if (CONSTANT_P (op1
))
1930 else if (GET_CODE (addr
) == MULT
)
1932 ireg
= XEXP (addr
, 0);
1933 scale
= XEXP (addr
, 1);
1939 output_addr_const (file
, offset
);
1941 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
1943 fprintf (file
, "[%s*%d]", reg_names
[REGNO (ireg
)], INTVAL (scale
));
1946 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1947 that is a valid memory address for an instruction.
1948 The MODE argument is the machine mode for the MEM expression
1949 that wants to use this address.
1951 On 80960, legitimate addresses are:
1953 disp (12 or 32 bit) ld foo,r0
1954 base + index ld (g0)[g1*1],r0
1955 base + displ ld 0xf00(g0),r0
1956 base + index*scale + displ ld 0xf00(g0)[g1*4],r0
1957 index*scale + base ld (g0)[g1*4],r0
1958 index*scale + displ ld 0xf00[g1*4],r0
1959 index*scale ld [g1*4],r0
1960 index + base + displ ld 0xf00(g0)[g1*1],r0
1962 In each case, scale can be 1, 2, 4, 8, or 16. */
1964 /* This is exactly the same as i960_print_operand_addr, except that
1965 it recognizes addresses instead of printing them.
1967 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
1968 convert common non-canonical forms to canonical form so that they will
1971 /* These two macros allow us to accept either a REG or a SUBREG anyplace
1972 where a register is valid. */
1974 #define RTX_OK_FOR_BASE_P(X, STRICT) \
1975 ((GET_CODE (X) == REG \
1976 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (X) : REG_OK_FOR_BASE_P (X))) \
1977 || (GET_CODE (X) == SUBREG \
1978 && GET_CODE (SUBREG_REG (X)) == REG \
1979 && (STRICT ? REG_OK_FOR_BASE_P_STRICT (SUBREG_REG (X)) \
1980 : REG_OK_FOR_BASE_P (SUBREG_REG (X)))))
1982 #define RTX_OK_FOR_INDEX_P(X, STRICT) \
1983 ((GET_CODE (X) == REG \
1984 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (X) : REG_OK_FOR_INDEX_P (X)))\
1985 || (GET_CODE (X) == SUBREG \
1986 && GET_CODE (SUBREG_REG (X)) == REG \
1987 && (STRICT ? REG_OK_FOR_INDEX_P_STRICT (SUBREG_REG (X)) \
1988 : REG_OK_FOR_INDEX_P (SUBREG_REG (X)))))
1991 legitimate_address_p (mode
, addr
, strict
)
1992 enum machine_mode mode ATTRIBUTE_UNUSED
;
1996 if (RTX_OK_FOR_BASE_P (addr
, strict
))
1998 else if (CONSTANT_P (addr
))
2000 else if (GET_CODE (addr
) == PLUS
)
2004 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
2007 op0
= XEXP (addr
, 0);
2008 op1
= XEXP (addr
, 1);
2010 if (RTX_OK_FOR_BASE_P (op0
, strict
))
2012 if (RTX_OK_FOR_INDEX_P (op1
, strict
))
2014 else if (CONSTANT_P (op1
))
2019 else if (GET_CODE (op0
) == PLUS
)
2021 if (GET_CODE (XEXP (op0
, 0)) == MULT
)
2023 if (! (RTX_OK_FOR_INDEX_P (XEXP (XEXP (op0
, 0), 0), strict
)
2024 && SCALE_TERM_P (XEXP (XEXP (op0
, 0), 1))))
2027 if (RTX_OK_FOR_BASE_P (XEXP (op0
, 1), strict
)
2028 && CONSTANT_P (op1
))
2033 else if (RTX_OK_FOR_BASE_P (XEXP (op0
, 0), strict
))
2035 if (RTX_OK_FOR_INDEX_P (XEXP (op0
, 1), strict
)
2036 && CONSTANT_P (op1
))
2044 else if (GET_CODE (op0
) == MULT
)
2046 if (! (RTX_OK_FOR_INDEX_P (XEXP (op0
, 0), strict
)
2047 && SCALE_TERM_P (XEXP (op0
, 1))))
2050 if (RTX_OK_FOR_BASE_P (op1
, strict
))
2052 else if (CONSTANT_P (op1
))
2060 else if (GET_CODE (addr
) == MULT
)
2062 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
2065 return (RTX_OK_FOR_INDEX_P (XEXP (addr
, 0), strict
)
2066 && SCALE_TERM_P (XEXP (addr
, 1)));
2072 /* Try machine-dependent ways of modifying an illegitimate address
2073 to be legitimate. If we find one, return the new, valid address.
2074 This macro is used in only one place: `memory_address' in explow.c.
2076 This converts some non-canonical addresses to canonical form so they
2077 can be recognized. */
2080 legitimize_address (x
, oldx
, mode
)
2082 register rtx oldx ATTRIBUTE_UNUSED
;
2083 enum machine_mode mode ATTRIBUTE_UNUSED
;
2085 if (GET_CODE (x
) == SYMBOL_REF
)
2088 x
= copy_to_reg (x
);
2091 if (! TARGET_COMPLEX_ADDR
&& ! reload_completed
)
2094 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
2095 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
2096 created by virtual register instantiation, register elimination, and
2097 similar optimizations. */
2098 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == MULT
2099 && GET_CODE (XEXP (x
, 1)) == PLUS
)
2100 x
= gen_rtx_PLUS (Pmode
,
2101 gen_rtx_PLUS (Pmode
, XEXP (x
, 0), XEXP (XEXP (x
, 1), 0)),
2102 XEXP (XEXP (x
, 1), 1));
2104 /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
2105 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
2106 else if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 0)) == PLUS
2107 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
2108 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == PLUS
2109 && CONSTANT_P (XEXP (x
, 1)))
2111 rtx constant
, other
;
2113 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2115 constant
= XEXP (x
, 1);
2116 other
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2118 else if (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 1), 1)) == CONST_INT
)
2120 constant
= XEXP (XEXP (XEXP (x
, 0), 1), 1);
2121 other
= XEXP (x
, 1);
2124 constant
= 0, other
= 0;
2127 x
= gen_rtx_PLUS (Pmode
,
2128 gen_rtx_PLUS (Pmode
, XEXP (XEXP (x
, 0), 0),
2129 XEXP (XEXP (XEXP (x
, 0), 1), 0)),
2130 plus_constant (other
, INTVAL (constant
)));
2137 /* Return the most stringent alignment that we are willing to consider
2138 objects of size SIZE and known alignment ALIGN as having. */
2141 i960_alignment (size
, align
)
2147 if (! TARGET_STRICT_ALIGN
)
2148 if (TARGET_IC_COMPAT2_0
|| align
>= 4)
2150 i
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
2161 hard_regno_mode_ok (regno
, mode
)
2163 enum machine_mode mode
;
2169 case CCmode
: case CC_UNSmode
: case CC_CHKmode
:
2172 case DImode
: case DFmode
:
2173 return (regno
& 1) == 0;
2175 case TImode
: case XFmode
:
2176 return (regno
& 3) == 0;
2182 else if (regno
>= 32 && regno
< 36)
2186 case SFmode
: case DFmode
: case XFmode
:
2187 case SCmode
: case DCmode
:
2194 else if (regno
== 36)
2198 case CCmode
: case CC_UNSmode
: case CC_CHKmode
:
2205 else if (regno
== 37)
2212 /* Return the minimum alignment of an expression rtx X in bytes. This takes
2213 advantage of machine specific facts, such as knowing that the frame pointer
2214 is always 16 byte aligned. */
2217 i960_expr_alignment (x
, size
)
2226 switch (GET_CODE(x
))
2231 if ((align
& 0xf) == 0)
2233 else if ((align
& 0x7) == 0)
2235 else if ((align
& 0x3) == 0)
2237 else if ((align
& 0x1) == 0)
2244 align
= MIN (i960_expr_alignment (XEXP (x
, 0), size
),
2245 i960_expr_alignment (XEXP (x
, 1), size
));
2249 /* If this is a valid program, objects are guaranteed to be
2250 correctly aligned for whatever size the reference actually is. */
2251 align
= i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
;
2255 if (REGNO (x
) == FRAME_POINTER_REGNUM
)
2260 align
= i960_expr_alignment (XEXP (x
, 0), size
);
2262 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2264 align
= align
<< INTVAL (XEXP (x
, 1));
2265 align
= MIN (align
, 16);
2270 align
= (i960_expr_alignment (XEXP (x
, 0), size
) *
2271 i960_expr_alignment (XEXP (x
, 1), size
));
2273 align
= MIN (align
, 16);
2282 /* Return true if it is possible to reference both BASE and OFFSET, which
2283 have alignment at least as great as 4 byte, as if they had alignment valid
2284 for an object of size SIZE. */
2287 i960_improve_align (base
, offset
, size
)
2294 /* We have at least a word reference to the object, so we know it has to
2295 be aligned at least to 4 bytes. */
2297 i
= MIN (i960_expr_alignment (base
, 4),
2298 i960_expr_alignment (offset
, 4));
2302 /* We know the size of the request. If strict align is not enabled, we
2303 can guess that the alignment is OK for the requested size. */
2305 if (! TARGET_STRICT_ALIGN
)
2306 if ((j
= (i960_object_bytes_bitalign (size
) / BITS_PER_UNIT
)) > i
)
2312 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2313 (SImode) alignment as if they had 16 byte (TImode) alignment. */
2316 i960_si_ti (base
, offset
)
2320 return i960_improve_align (base
, offset
, 16);
2323 /* Return true if it is possible to access BASE and OFFSET, which have 4 byte
2324 (SImode) alignment as if they had 8 byte (DImode) alignment. */
2327 i960_si_di (base
, offset
)
2331 return i960_improve_align (base
, offset
, 8);
2334 /* Return raw values of size and alignment (in words) for the data
2335 type being accessed. These values will be rounded by the caller. */
2338 i960_arg_size_and_align (mode
, type
, size_out
, align_out
)
2339 enum machine_mode mode
;
2346 /* Use formal alignment requirements of type being passed, except make
2347 it at least a word. If we don't have a type, this is a library call,
2348 and the parm has to be of scalar type. In this case, consider its
2349 formal alignment requirement to be its size in words. */
2351 if (mode
== BLKmode
)
2352 size
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2353 else if (mode
== VOIDmode
)
2355 /* End of parm list. */
2356 if (type
== 0 || TYPE_MODE (type
) != VOIDmode
)
2361 size
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
2365 /* ??? This is a hack to properly correct the alignment of XFmode
2366 values without affecting anything else. */
2372 else if (TYPE_ALIGN (type
) >= BITS_PER_WORD
)
2373 align
= TYPE_ALIGN (type
) / BITS_PER_WORD
;
2381 /* On the 80960 the first 12 args are in registers and the rest are pushed.
2382 Any arg that is bigger than 4 words is placed on the stack and all
2383 subsequent arguments are placed on the stack.
2385 Additionally, parameters with an alignment requirement stronger than
2386 a word must be aligned appropriately. Note that this means that a
2387 64 bit object with a 32 bit alignment is not 64 bit aligned and may be
2388 passed in an odd/even register pair. */
2390 /* Update CUM to advance past an argument described by MODE and TYPE. */
2393 i960_function_arg_advance (cum
, mode
, type
, named
)
2394 CUMULATIVE_ARGS
*cum
;
2395 enum machine_mode mode
;
2397 int named ATTRIBUTE_UNUSED
;
2401 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2403 if (size
> 4 || cum
->ca_nstackparms
!= 0
2404 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2405 || MUST_PASS_IN_STACK (mode
, type
))
2407 /* Indicate that all the registers are in use, even if all are not,
2408 so va_start will compute the right value. */
2409 cum
->ca_nregparms
= NPARM_REGS
;
2410 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
) + size
;
2413 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
) + size
;
2416 /* Return the register that the argument described by MODE and TYPE is
2417 passed in, or else return 0 if it is passed on the stack. */
2420 i960_function_arg (cum
, mode
, type
, named
)
2421 CUMULATIVE_ARGS
*cum
;
2422 enum machine_mode mode
;
2424 int named ATTRIBUTE_UNUSED
;
2429 if (mode
== VOIDmode
)
2432 i960_arg_size_and_align (mode
, type
, &size
, &align
);
2434 if (size
> 4 || cum
->ca_nstackparms
!= 0
2435 || (size
+ ROUND_PARM (cum
->ca_nregparms
, align
)) > NPARM_REGS
2436 || MUST_PASS_IN_STACK (mode
, type
))
2438 cum
->ca_nstackparms
= ROUND_PARM (cum
->ca_nstackparms
, align
);
2443 cum
->ca_nregparms
= ROUND_PARM (cum
->ca_nregparms
, align
);
2444 ret
= gen_rtx_REG (mode
, cum
->ca_nregparms
);
2450 /* Floating-point support. */
2453 i960_output_long_double (file
, value
)
2455 REAL_VALUE_TYPE value
;
2460 REAL_VALUE_TO_TARGET_LONG_DOUBLE (value
, value_long
);
2461 REAL_VALUE_TO_DECIMAL (value
, "%.20g", dstr
);
2464 "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n\t.word\t0x%08lx\n",
2465 value_long
[0], dstr
, value_long
[1], value_long
[2]);
2466 fprintf (file
, "\t.word\t0x0\n");
2470 i960_output_double (file
, value
)
2472 REAL_VALUE_TYPE value
;
2477 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
2478 REAL_VALUE_TO_DECIMAL (value
, "%.20g", dstr
);
2480 fprintf (file
, "\t.word\t0x%08lx\t\t# %s\n\t.word\t0x%08lx\n",
2481 value_long
[0], dstr
, value_long
[1]);
2485 i960_output_float (file
, value
)
2487 REAL_VALUE_TYPE value
;
2492 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
2493 REAL_VALUE_TO_DECIMAL (value
, "%.12g", dstr
);
2495 fprintf (file
, "\t.word\t0x%08lx\t\t# %s (float)\n", value_long
, dstr
);
2498 /* Return the number of bits that an object of size N bytes is aligned to. */
2501 i960_object_bytes_bitalign (n
)
2505 else if (n
> 4) n
= 64;
2506 else if (n
> 2) n
= 32;
2507 else if (n
> 1) n
= 16;
2513 /* Compute the alignment for an aggregate type TSIZE.
2514 Alignment is MAX (greatest member alignment,
2515 MIN (pragma align, structure size alignment)). */
2518 i960_round_align (align
, tsize
)
2524 if (! tsize
|| TREE_CODE (tsize
) != INTEGER_CST
)
2527 new_align
= i960_object_bytes_bitalign (TREE_INT_CST_LOW (tsize
)
2529 /* Handle #pragma align. */
2530 if (new_align
> i960_maxbitalignment
)
2531 new_align
= i960_maxbitalignment
;
2533 if (align
< new_align
)
2539 /* Do any needed setup for a varargs function. For the i960, we must
2540 create a register parameter block if one doesn't exist, and then copy
2541 all register parameters to memory. */
2544 i960_setup_incoming_varargs (cum
, mode
, type
, pretend_size
, no_rtl
)
2545 CUMULATIVE_ARGS
*cum
;
2546 enum machine_mode mode ATTRIBUTE_UNUSED
;
2547 tree type ATTRIBUTE_UNUSED
;
2548 int *pretend_size ATTRIBUTE_UNUSED
;
2551 /* Note: for a varargs fn with only a va_alist argument, this is 0. */
2552 int first_reg
= cum
->ca_nregparms
;
2554 /* Copy only unnamed register arguments to memory. If there are
2555 any stack parms, there are no unnamed arguments in registers, and
2556 an argument block was already allocated by the caller.
2557 Remember that any arg bigger than 4 words is passed on the stack as
2558 are all subsequent args.
2560 If there are no stack arguments but there are exactly NPARM_REGS
2561 registers, either there were no extra arguments or the caller
2562 allocated an argument block. */
2564 if (cum
->ca_nstackparms
== 0 && first_reg
< NPARM_REGS
&& !no_rtl
)
2566 rtx label
= gen_label_rtx ();
2569 /* If arg_pointer_rtx == 0, no arguments were passed on the stack
2570 and we need to allocate a chunk to save the registers (if any
2571 arguments were passed on the stack the caller would allocate the
2572 48 bytes as well). We must allocate all 48 bytes (12*4) because
2573 va_start assumes it. */
2574 emit_insn (gen_cmpsi (arg_pointer_rtx
, const0_rtx
));
2575 emit_jump_insn (gen_bne (label
));
2576 emit_insn (gen_rtx_SET (VOIDmode
, arg_pointer_rtx
,
2577 stack_pointer_rtx
));
2578 emit_insn (gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
2579 memory_address (SImode
,
2580 plus_constant (stack_pointer_rtx
,
2584 /* ??? Note that we unnecessarily store one extra register for stdarg
2585 fns. We could optimize this, but it's kept as for now. */
2586 regblock
= gen_rtx_MEM (BLKmode
,
2587 plus_constant (arg_pointer_rtx
, first_reg
* 4));
2588 set_mem_alias_set (regblock
, get_varargs_alias_set ());
2589 set_mem_align (regblock
, BITS_PER_WORD
);
2590 move_block_from_reg (first_reg
, regblock
,
2591 NPARM_REGS
- first_reg
,
2592 (NPARM_REGS
- first_reg
) * UNITS_PER_WORD
);
2596 /* Define the `__builtin_va_list' type for the ABI. */
2599 i960_build_va_list ()
2601 return build_array_type (unsigned_type_node
,
2602 build_index_type (size_one_node
));
2605 /* Implement `va_start' for varargs and stdarg. */
2608 i960_va_start (stdarg_p
, valist
, nextarg
)
2609 int stdarg_p ATTRIBUTE_UNUSED
;
2611 rtx nextarg ATTRIBUTE_UNUSED
;
2613 tree s
, t
, base
, num
;
2615 /* The array type always decays to a pointer before we get here, so we
2616 can't use ARRAY_REF. */
2617 base
= build1 (INDIRECT_REF
, unsigned_type_node
, valist
);
2618 num
= build1 (INDIRECT_REF
, unsigned_type_node
,
2619 build (PLUS_EXPR
, unsigned_type_node
, valist
,
2620 TYPE_SIZE_UNIT (TREE_TYPE (valist
))));
2622 s
= make_tree (unsigned_type_node
, arg_pointer_rtx
);
2623 t
= build (MODIFY_EXPR
, unsigned_type_node
, base
, s
);
2624 TREE_SIDE_EFFECTS (t
) = 1;
2625 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2627 s
= build_int_2 ((current_function_args_info
.ca_nregparms
2628 + current_function_args_info
.ca_nstackparms
) * 4, 0);
2629 t
= build (MODIFY_EXPR
, unsigned_type_node
, num
, s
);
2630 TREE_SIDE_EFFECTS (t
) = 1;
2631 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2634 /* Implement `va_arg'. */
2637 i960_va_arg (valist
, type
)
2640 HOST_WIDE_INT siz
, ali
;
2641 tree base
, num
, pad
, next
, this, t1
, t2
, int48
;
2644 /* The array type always decays to a pointer before we get here, so we
2645 can't use ARRAY_REF. */
2646 base
= build1 (INDIRECT_REF
, unsigned_type_node
, valist
);
2647 num
= build1 (INDIRECT_REF
, unsigned_type_node
,
2648 build (PLUS_EXPR
, unsigned_type_node
, valist
,
2649 TYPE_SIZE_UNIT (TREE_TYPE (valist
))));
2651 /* Round up sizeof(type) to a word. */
2652 siz
= (int_size_in_bytes (type
) + UNITS_PER_WORD
- 1) & -UNITS_PER_WORD
;
2654 /* Round up alignment to a word. */
2655 ali
= TYPE_ALIGN (type
);
2656 if (ali
< BITS_PER_WORD
)
2657 ali
= BITS_PER_WORD
;
2658 ali
/= BITS_PER_UNIT
;
2660 /* Align NUM appropriate for the argument. */
2661 pad
= fold (build (PLUS_EXPR
, unsigned_type_node
, num
,
2662 build_int_2 (ali
- 1, 0)));
2663 pad
= fold (build (BIT_AND_EXPR
, unsigned_type_node
, pad
,
2664 build_int_2 (-ali
, -1)));
2665 pad
= save_expr (pad
);
2667 /* Increment VPAD past this argument. */
2668 next
= fold (build (PLUS_EXPR
, unsigned_type_node
, pad
,
2669 build_int_2 (siz
, 0)));
2670 next
= save_expr (next
);
2672 /* Find the offset for the current argument. Mind peculiar overflow
2673 from registers to stack. */
2674 int48
= build_int_2 (48, 0);
2676 t2
= integer_one_node
;
2678 t2
= fold (build (GT_EXPR
, integer_type_node
, next
, int48
));
2679 t1
= fold (build (LE_EXPR
, integer_type_node
, num
, int48
));
2680 t1
= fold (build (TRUTH_AND_EXPR
, integer_type_node
, t1
, t2
));
2681 this = fold (build (COND_EXPR
, unsigned_type_node
, t1
, int48
, pad
));
2683 /* Find the address for the current argument. */
2684 t1
= fold (build (PLUS_EXPR
, unsigned_type_node
, base
, this));
2685 t1
= build1 (NOP_EXPR
, ptr_type_node
, t1
);
2686 addr_rtx
= expand_expr (t1
, NULL_RTX
, Pmode
, EXPAND_NORMAL
);
2688 /* Increment NUM. */
2689 t1
= build (MODIFY_EXPR
, unsigned_type_node
, num
, next
);
2690 TREE_SIDE_EFFECTS (t1
) = 1;
2691 expand_expr (t1
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2696 /* Calculate the final size of the reg parm stack space for the current
2697 function, based on how many bytes would be allocated on the stack. */
2700 i960_final_reg_parm_stack_space (const_size
, var_size
)
2704 if (var_size
|| const_size
> 48)
2710 /* Calculate the size of the reg parm stack space. This is a bit complicated
2714 i960_reg_parm_stack_space (fndecl
)
2717 /* In this case, we are called from emit_library_call, and we don't need
2718 to pretend we have more space for parameters than what's apparent. */
2722 /* In this case, we are called from locate_and_pad_parms when we're
2723 not IN_REGS, so we have an arg block. */
2724 if (fndecl
!= current_function_decl
)
2727 /* Otherwise, we have an arg block if the current function has more than
2728 48 bytes of parameters. */
2729 if (current_function_args_size
!= 0 || VARARGS_STDARG_FUNCTION (fndecl
))
2735 /* Return the register class of a scratch register needed to copy IN into
2736 or out of a register in CLASS in MODE. If it can be done directly,
2737 NO_REGS is returned. */
2740 secondary_reload_class (class, mode
, in
)
2741 enum reg_class
class;
2742 enum machine_mode mode
;
2747 if (GET_CODE (in
) == REG
|| GET_CODE (in
) == SUBREG
)
2748 regno
= true_regnum (in
);
2750 /* We can place anything into LOCAL_OR_GLOBAL_REGS and can put
2751 LOCAL_OR_GLOBAL_REGS into anything. */
2752 if (class == LOCAL_OR_GLOBAL_REGS
|| class == LOCAL_REGS
2753 || class == GLOBAL_REGS
|| (regno
>= 0 && regno
< 32))
2756 /* We can place any hard register, 0.0, and 1.0 into FP_REGS. */
2757 if (class == FP_REGS
2758 && ((regno
>= 0 && regno
< FIRST_PSEUDO_REGISTER
)
2759 || in
== CONST0_RTX (mode
) || in
== CONST1_RTX (mode
)))
2762 return LOCAL_OR_GLOBAL_REGS
;
2765 /* Look at the opcode P, and set i96_last_insn_type to indicate which
2766 function unit it executed on. */
2768 /* ??? This would make more sense as an attribute. */
2771 i960_scan_opcode (p
)
2783 /* Ret is not actually of type REG, but it won't matter, because no
2784 insn will ever follow it. */
2787 i960_last_insn_type
= I_TYPE_REG
;
2791 if (p
[1] == 'x' || p
[3] == 'x')
2792 i960_last_insn_type
= I_TYPE_MEM
;
2793 i960_last_insn_type
= I_TYPE_CTRL
;
2798 i960_last_insn_type
= I_TYPE_CTRL
;
2805 i960_last_insn_type
= I_TYPE_MEM
;
2807 i960_last_insn_type
= I_TYPE_CTRL
;
2809 else if (p
[1] == 'm')
2812 i960_last_insn_type
= I_TYPE_REG
;
2813 else if (p
[4] == 'b' || p
[4] == 'j')
2814 i960_last_insn_type
= I_TYPE_CTRL
;
2816 i960_last_insn_type
= I_TYPE_REG
;
2819 i960_last_insn_type
= I_TYPE_REG
;
2823 i960_last_insn_type
= I_TYPE_MEM
;
2828 i960_last_insn_type
= I_TYPE_MEM
;
2830 i960_last_insn_type
= I_TYPE_REG
;