PR sanitizer/59009
[official-gcc.git] / gcc / reload1.c
blob204685da31620ec8563128cfb7611269a5fc65cd
1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 #include "config.h"
21 #include "system.h"
22 #include "coretypes.h"
23 #include "tm.h"
25 #include "machmode.h"
26 #include "hard-reg-set.h"
27 #include "rtl-error.h"
28 #include "tm_p.h"
29 #include "obstack.h"
30 #include "insn-config.h"
31 #include "ggc.h"
32 #include "flags.h"
33 #include "function.h"
34 #include "expr.h"
35 #include "optabs.h"
36 #include "regs.h"
37 #include "addresses.h"
38 #include "basic-block.h"
39 #include "df.h"
40 #include "reload.h"
41 #include "recog.h"
42 #include "except.h"
43 #include "tree.h"
44 #include "ira.h"
45 #include "target.h"
46 #include "emit-rtl.h"
47 #include "dumpfile.h"
49 /* This file contains the reload pass of the compiler, which is
50 run after register allocation has been done. It checks that
51 each insn is valid (operands required to be in registers really
52 are in registers of the proper class) and fixes up invalid ones
53 by copying values temporarily into registers for the insns
54 that need them.
56 The results of register allocation are described by the vector
57 reg_renumber; the insns still contain pseudo regs, but reg_renumber
58 can be used to find which hard reg, if any, a pseudo reg is in.
60 The technique we always use is to free up a few hard regs that are
61 called ``reload regs'', and for each place where a pseudo reg
62 must be in a hard reg, copy it temporarily into one of the reload regs.
64 Reload regs are allocated locally for every instruction that needs
65 reloads. When there are pseudos which are allocated to a register that
66 has been chosen as a reload reg, such pseudos must be ``spilled''.
67 This means that they go to other hard regs, or to stack slots if no other
68 available hard regs can be found. Spilling can invalidate more
69 insns, requiring additional need for reloads, so we must keep checking
70 until the process stabilizes.
72 For machines with different classes of registers, we must keep track
73 of the register class needed for each reload, and make sure that
74 we allocate enough reload registers of each class.
76 The file reload.c contains the code that checks one insn for
77 validity and reports the reloads that it needs. This file
78 is in charge of scanning the entire rtl code, accumulating the
79 reload needs, spilling, assigning reload registers to use for
80 fixing up each insn, and generating the new insns to copy values
81 into the reload registers. */
83 struct target_reload default_target_reload;
84 #if SWITCHABLE_TARGET
85 struct target_reload *this_target_reload = &default_target_reload;
86 #endif
88 #define spill_indirect_levels \
89 (this_target_reload->x_spill_indirect_levels)
91 /* During reload_as_needed, element N contains a REG rtx for the hard reg
92 into which reg N has been reloaded (perhaps for a previous insn). */
93 static rtx *reg_last_reload_reg;
95 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
96 for an output reload that stores into reg N. */
97 static regset_head reg_has_output_reload;
99 /* Indicates which hard regs are reload-registers for an output reload
100 in the current insn. */
101 static HARD_REG_SET reg_is_output_reload;
103 /* Widest width in which each pseudo reg is referred to (via subreg). */
104 static unsigned int *reg_max_ref_width;
106 /* Vector to remember old contents of reg_renumber before spilling. */
107 static short *reg_old_renumber;
109 /* During reload_as_needed, element N contains the last pseudo regno reloaded
110 into hard register N. If that pseudo reg occupied more than one register,
111 reg_reloaded_contents points to that pseudo for each spill register in
112 use; all of these must remain set for an inheritance to occur. */
113 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
115 /* During reload_as_needed, element N contains the insn for which
116 hard register N was last used. Its contents are significant only
117 when reg_reloaded_valid is set for this register. */
118 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
120 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
121 static HARD_REG_SET reg_reloaded_valid;
122 /* Indicate if the register was dead at the end of the reload.
123 This is only valid if reg_reloaded_contents is set and valid. */
124 static HARD_REG_SET reg_reloaded_dead;
126 /* Indicate whether the register's current value is one that is not
127 safe to retain across a call, even for registers that are normally
128 call-saved. This is only meaningful for members of reg_reloaded_valid. */
129 static HARD_REG_SET reg_reloaded_call_part_clobbered;
131 /* Number of spill-regs so far; number of valid elements of spill_regs. */
132 static int n_spills;
134 /* In parallel with spill_regs, contains REG rtx's for those regs.
135 Holds the last rtx used for any given reg, or 0 if it has never
136 been used for spilling yet. This rtx is reused, provided it has
137 the proper mode. */
138 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
140 /* In parallel with spill_regs, contains nonzero for a spill reg
141 that was stored after the last time it was used.
142 The precise value is the insn generated to do the store. */
143 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
145 /* This is the register that was stored with spill_reg_store. This is a
146 copy of reload_out / reload_out_reg when the value was stored; if
147 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
148 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
150 /* This table is the inverse mapping of spill_regs:
151 indexed by hard reg number,
152 it contains the position of that reg in spill_regs,
153 or -1 for something that is not in spill_regs.
155 ?!? This is no longer accurate. */
156 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
158 /* This reg set indicates registers that can't be used as spill registers for
159 the currently processed insn. These are the hard registers which are live
160 during the insn, but not allocated to pseudos, as well as fixed
161 registers. */
162 static HARD_REG_SET bad_spill_regs;
164 /* These are the hard registers that can't be used as spill register for any
165 insn. This includes registers used for user variables and registers that
166 we can't eliminate. A register that appears in this set also can't be used
167 to retry register allocation. */
168 static HARD_REG_SET bad_spill_regs_global;
170 /* Describes order of use of registers for reloading
171 of spilled pseudo-registers. `n_spills' is the number of
172 elements that are actually valid; new ones are added at the end.
174 Both spill_regs and spill_reg_order are used on two occasions:
175 once during find_reload_regs, where they keep track of the spill registers
176 for a single insn, but also during reload_as_needed where they show all
177 the registers ever used by reload. For the latter case, the information
178 is calculated during finish_spills. */
179 static short spill_regs[FIRST_PSEUDO_REGISTER];
181 /* This vector of reg sets indicates, for each pseudo, which hard registers
182 may not be used for retrying global allocation because the register was
183 formerly spilled from one of them. If we allowed reallocating a pseudo to
184 a register that it was already allocated to, reload might not
185 terminate. */
186 static HARD_REG_SET *pseudo_previous_regs;
188 /* This vector of reg sets indicates, for each pseudo, which hard
189 registers may not be used for retrying global allocation because they
190 are used as spill registers during one of the insns in which the
191 pseudo is live. */
192 static HARD_REG_SET *pseudo_forbidden_regs;
194 /* All hard regs that have been used as spill registers for any insn are
195 marked in this set. */
196 static HARD_REG_SET used_spill_regs;
198 /* Index of last register assigned as a spill register. We allocate in
199 a round-robin fashion. */
200 static int last_spill_reg;
202 /* Record the stack slot for each spilled hard register. */
203 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
205 /* Width allocated so far for that stack slot. */
206 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
208 /* Record which pseudos needed to be spilled. */
209 static regset_head spilled_pseudos;
211 /* Record which pseudos changed their allocation in finish_spills. */
212 static regset_head changed_allocation_pseudos;
214 /* Used for communication between order_regs_for_reload and count_pseudo.
215 Used to avoid counting one pseudo twice. */
216 static regset_head pseudos_counted;
218 /* First uid used by insns created by reload in this function.
219 Used in find_equiv_reg. */
220 int reload_first_uid;
222 /* Flag set by local-alloc or global-alloc if anything is live in
223 a call-clobbered reg across calls. */
224 int caller_save_needed;
226 /* Set to 1 while reload_as_needed is operating.
227 Required by some machines to handle any generated moves differently. */
228 int reload_in_progress = 0;
230 /* This obstack is used for allocation of rtl during register elimination.
231 The allocated storage can be freed once find_reloads has processed the
232 insn. */
233 static struct obstack reload_obstack;
235 /* Points to the beginning of the reload_obstack. All insn_chain structures
236 are allocated first. */
237 static char *reload_startobj;
239 /* The point after all insn_chain structures. Used to quickly deallocate
240 memory allocated in copy_reloads during calculate_needs_all_insns. */
241 static char *reload_firstobj;
243 /* This points before all local rtl generated by register elimination.
244 Used to quickly free all memory after processing one insn. */
245 static char *reload_insn_firstobj;
247 /* List of insn_chain instructions, one for every insn that reload needs to
248 examine. */
249 struct insn_chain *reload_insn_chain;
251 /* TRUE if we potentially left dead insns in the insn stream and want to
252 run DCE immediately after reload, FALSE otherwise. */
253 static bool need_dce;
255 /* List of all insns needing reloads. */
256 static struct insn_chain *insns_need_reload;
258 /* This structure is used to record information about register eliminations.
259 Each array entry describes one possible way of eliminating a register
260 in favor of another. If there is more than one way of eliminating a
261 particular register, the most preferred should be specified first. */
263 struct elim_table
265 int from; /* Register number to be eliminated. */
266 int to; /* Register number used as replacement. */
267 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
268 int can_eliminate; /* Nonzero if this elimination can be done. */
269 int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE
270 target hook in previous scan over insns
271 made by reload. */
272 HOST_WIDE_INT offset; /* Current offset between the two regs. */
273 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
274 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
275 rtx from_rtx; /* REG rtx for the register to be eliminated.
276 We cannot simply compare the number since
277 we might then spuriously replace a hard
278 register corresponding to a pseudo
279 assigned to the reg to be eliminated. */
280 rtx to_rtx; /* REG rtx for the replacement. */
283 static struct elim_table *reg_eliminate = 0;
285 /* This is an intermediate structure to initialize the table. It has
286 exactly the members provided by ELIMINABLE_REGS. */
287 static const struct elim_table_1
289 const int from;
290 const int to;
291 } reg_eliminate_1[] =
293 /* If a set of eliminable registers was specified, define the table from it.
294 Otherwise, default to the normal case of the frame pointer being
295 replaced by the stack pointer. */
297 #ifdef ELIMINABLE_REGS
298 ELIMINABLE_REGS;
299 #else
300 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
301 #endif
303 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
305 /* Record the number of pending eliminations that have an offset not equal
306 to their initial offset. If nonzero, we use a new copy of each
307 replacement result in any insns encountered. */
308 int num_not_at_initial_offset;
310 /* Count the number of registers that we may be able to eliminate. */
311 static int num_eliminable;
312 /* And the number of registers that are equivalent to a constant that
313 can be eliminated to frame_pointer / arg_pointer + constant. */
314 static int num_eliminable_invariants;
316 /* For each label, we record the offset of each elimination. If we reach
317 a label by more than one path and an offset differs, we cannot do the
318 elimination. This information is indexed by the difference of the
319 number of the label and the first label number. We can't offset the
320 pointer itself as this can cause problems on machines with segmented
321 memory. The first table is an array of flags that records whether we
322 have yet encountered a label and the second table is an array of arrays,
323 one entry in the latter array for each elimination. */
325 static int first_label_num;
326 static char *offsets_known_at;
327 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
329 vec<reg_equivs_t, va_gc> *reg_equivs;
331 /* Stack of addresses where an rtx has been changed. We can undo the
332 changes by popping items off the stack and restoring the original
333 value at each location.
335 We use this simplistic undo capability rather than copy_rtx as copy_rtx
336 will not make a deep copy of a normally sharable rtx, such as
337 (const (plus (symbol_ref) (const_int))). If such an expression appears
338 as R1 in gen_reload_chain_without_interm_reg_p, then a shared
339 rtx expression would be changed. See PR 42431. */
341 typedef rtx *rtx_p;
342 static vec<rtx_p> substitute_stack;
344 /* Number of labels in the current function. */
346 static int num_labels;
348 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
349 static void maybe_fix_stack_asms (void);
350 static void copy_reloads (struct insn_chain *);
351 static void calculate_needs_all_insns (int);
352 static int find_reg (struct insn_chain *, int);
353 static void find_reload_regs (struct insn_chain *);
354 static void select_reload_regs (void);
355 static void delete_caller_save_insns (void);
357 static void spill_failure (rtx, enum reg_class);
358 static void count_spilled_pseudo (int, int, int);
359 static void delete_dead_insn (rtx);
360 static void alter_reg (int, int, bool);
361 static void set_label_offsets (rtx, rtx, int);
362 static void check_eliminable_occurrences (rtx);
363 static void elimination_effects (rtx, enum machine_mode);
364 static rtx eliminate_regs_1 (rtx, enum machine_mode, rtx, bool, bool);
365 static int eliminate_regs_in_insn (rtx, int);
366 static void update_eliminable_offsets (void);
367 static void mark_not_eliminable (rtx, const_rtx, void *);
368 static void set_initial_elim_offsets (void);
369 static bool verify_initial_elim_offsets (void);
370 static void set_initial_label_offsets (void);
371 static void set_offsets_for_label (rtx);
372 static void init_eliminable_invariants (rtx, bool);
373 static void init_elim_table (void);
374 static void free_reg_equiv (void);
375 static void update_eliminables (HARD_REG_SET *);
376 static bool update_eliminables_and_spill (void);
377 static void elimination_costs_in_insn (rtx);
378 static void spill_hard_reg (unsigned int, int);
379 static int finish_spills (int);
380 static void scan_paradoxical_subregs (rtx);
381 static void count_pseudo (int);
382 static void order_regs_for_reload (struct insn_chain *);
383 static void reload_as_needed (int);
384 static void forget_old_reloads_1 (rtx, const_rtx, void *);
385 static void forget_marked_reloads (regset);
386 static int reload_reg_class_lower (const void *, const void *);
387 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
388 enum machine_mode);
389 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
390 enum machine_mode);
391 static int reload_reg_free_p (unsigned int, int, enum reload_type);
392 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
393 rtx, rtx, int, int);
394 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
395 rtx, rtx, int, int);
396 static int allocate_reload_reg (struct insn_chain *, int, int);
397 static int conflicts_with_override (rtx);
398 static void failed_reload (rtx, int);
399 static int set_reload_reg (int, int);
400 static void choose_reload_regs_init (struct insn_chain *, rtx *);
401 static void choose_reload_regs (struct insn_chain *);
402 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
403 rtx, int);
404 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
405 int);
406 static void do_input_reload (struct insn_chain *, struct reload *, int);
407 static void do_output_reload (struct insn_chain *, struct reload *, int);
408 static void emit_reload_insns (struct insn_chain *);
409 static void delete_output_reload (rtx, int, int, rtx);
410 static void delete_address_reloads (rtx, rtx);
411 static void delete_address_reloads_1 (rtx, rtx, rtx);
412 static void inc_for_reload (rtx, rtx, rtx, int);
413 #ifdef AUTO_INC_DEC
414 static void add_auto_inc_notes (rtx, rtx);
415 #endif
416 static void substitute (rtx *, const_rtx, rtx);
417 static bool gen_reload_chain_without_interm_reg_p (int, int);
418 static int reloads_conflict (int, int);
419 static rtx gen_reload (rtx, rtx, int, enum reload_type);
420 static rtx emit_insn_if_valid_for_reload (rtx);
422 /* Initialize the reload pass. This is called at the beginning of compilation
423 and may be called again if the target is reinitialized. */
425 void
426 init_reload (void)
428 int i;
430 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
431 Set spill_indirect_levels to the number of levels such addressing is
432 permitted, zero if it is not permitted at all. */
434 rtx tem
435 = gen_rtx_MEM (Pmode,
436 gen_rtx_PLUS (Pmode,
437 gen_rtx_REG (Pmode,
438 LAST_VIRTUAL_REGISTER + 1),
439 gen_int_mode (4, Pmode)));
440 spill_indirect_levels = 0;
442 while (memory_address_p (QImode, tem))
444 spill_indirect_levels++;
445 tem = gen_rtx_MEM (Pmode, tem);
448 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
450 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
451 indirect_symref_ok = memory_address_p (QImode, tem);
453 /* See if reg+reg is a valid (and offsettable) address. */
455 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
457 tem = gen_rtx_PLUS (Pmode,
458 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
459 gen_rtx_REG (Pmode, i));
461 /* This way, we make sure that reg+reg is an offsettable address. */
462 tem = plus_constant (Pmode, tem, 4);
464 if (memory_address_p (QImode, tem))
466 double_reg_address_ok = 1;
467 break;
471 /* Initialize obstack for our rtl allocation. */
472 if (reload_startobj == NULL)
474 gcc_obstack_init (&reload_obstack);
475 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
478 INIT_REG_SET (&spilled_pseudos);
479 INIT_REG_SET (&changed_allocation_pseudos);
480 INIT_REG_SET (&pseudos_counted);
483 /* List of insn chains that are currently unused. */
484 static struct insn_chain *unused_insn_chains = 0;
486 /* Allocate an empty insn_chain structure. */
487 struct insn_chain *
488 new_insn_chain (void)
490 struct insn_chain *c;
492 if (unused_insn_chains == 0)
494 c = XOBNEW (&reload_obstack, struct insn_chain);
495 INIT_REG_SET (&c->live_throughout);
496 INIT_REG_SET (&c->dead_or_set);
498 else
500 c = unused_insn_chains;
501 unused_insn_chains = c->next;
503 c->is_caller_save_insn = 0;
504 c->need_operand_change = 0;
505 c->need_reload = 0;
506 c->need_elim = 0;
507 return c;
510 /* Small utility function to set all regs in hard reg set TO which are
511 allocated to pseudos in regset FROM. */
513 void
514 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
516 unsigned int regno;
517 reg_set_iterator rsi;
519 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
521 int r = reg_renumber[regno];
523 if (r < 0)
525 /* reload_combine uses the information from DF_LIVE_IN,
526 which might still contain registers that have not
527 actually been allocated since they have an
528 equivalence. */
529 gcc_assert (ira_conflicts_p || reload_completed);
531 else
532 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
536 /* Replace all pseudos found in LOC with their corresponding
537 equivalences. */
539 static void
540 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
542 rtx x = *loc;
543 enum rtx_code code;
544 const char *fmt;
545 int i, j;
547 if (! x)
548 return;
550 code = GET_CODE (x);
551 if (code == REG)
553 unsigned int regno = REGNO (x);
555 if (regno < FIRST_PSEUDO_REGISTER)
556 return;
558 x = eliminate_regs_1 (x, mem_mode, usage, true, false);
559 if (x != *loc)
561 *loc = x;
562 replace_pseudos_in (loc, mem_mode, usage);
563 return;
566 if (reg_equiv_constant (regno))
567 *loc = reg_equiv_constant (regno);
568 else if (reg_equiv_invariant (regno))
569 *loc = reg_equiv_invariant (regno);
570 else if (reg_equiv_mem (regno))
571 *loc = reg_equiv_mem (regno);
572 else if (reg_equiv_address (regno))
573 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address (regno));
574 else
576 gcc_assert (!REG_P (regno_reg_rtx[regno])
577 || REGNO (regno_reg_rtx[regno]) != regno);
578 *loc = regno_reg_rtx[regno];
581 return;
583 else if (code == MEM)
585 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
586 return;
589 /* Process each of our operands recursively. */
590 fmt = GET_RTX_FORMAT (code);
591 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
592 if (*fmt == 'e')
593 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
594 else if (*fmt == 'E')
595 for (j = 0; j < XVECLEN (x, i); j++)
596 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
599 /* Determine if the current function has an exception receiver block
600 that reaches the exit block via non-exceptional edges */
602 static bool
603 has_nonexceptional_receiver (void)
605 edge e;
606 edge_iterator ei;
607 basic_block *tos, *worklist, bb;
609 /* If we're not optimizing, then just err on the safe side. */
610 if (!optimize)
611 return true;
613 /* First determine which blocks can reach exit via normal paths. */
614 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
616 FOR_EACH_BB (bb)
617 bb->flags &= ~BB_REACHABLE;
619 /* Place the exit block on our worklist. */
620 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
621 *tos++ = EXIT_BLOCK_PTR;
623 /* Iterate: find everything reachable from what we've already seen. */
624 while (tos != worklist)
626 bb = *--tos;
628 FOR_EACH_EDGE (e, ei, bb->preds)
629 if (!(e->flags & EDGE_ABNORMAL))
631 basic_block src = e->src;
633 if (!(src->flags & BB_REACHABLE))
635 src->flags |= BB_REACHABLE;
636 *tos++ = src;
640 free (worklist);
642 /* Now see if there's a reachable block with an exceptional incoming
643 edge. */
644 FOR_EACH_BB (bb)
645 if (bb->flags & BB_REACHABLE && bb_has_abnormal_pred (bb))
646 return true;
648 /* No exceptional block reached exit unexceptionally. */
649 return false;
652 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be
653 zero elements) to MAX_REG_NUM elements.
655 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */
656 void
657 grow_reg_equivs (void)
659 int old_size = vec_safe_length (reg_equivs);
660 int max_regno = max_reg_num ();
661 int i;
662 reg_equivs_t ze;
664 memset (&ze, 0, sizeof (reg_equivs_t));
665 vec_safe_reserve (reg_equivs, max_regno);
666 for (i = old_size; i < max_regno; i++)
667 reg_equivs->quick_insert (i, ze);
671 /* Global variables used by reload and its subroutines. */
673 /* The current basic block while in calculate_elim_costs_all_insns. */
674 static basic_block elim_bb;
676 /* Set during calculate_needs if an insn needs register elimination. */
677 static int something_needs_elimination;
678 /* Set during calculate_needs if an insn needs an operand changed. */
679 static int something_needs_operands_changed;
680 /* Set by alter_regs if we spilled a register to the stack. */
681 static bool something_was_spilled;
683 /* Nonzero means we couldn't get enough spill regs. */
684 static int failure;
686 /* Temporary array of pseudo-register number. */
687 static int *temp_pseudo_reg_arr;
689 /* Main entry point for the reload pass.
691 FIRST is the first insn of the function being compiled.
693 GLOBAL nonzero means we were called from global_alloc
694 and should attempt to reallocate any pseudoregs that we
695 displace from hard regs we will use for reloads.
696 If GLOBAL is zero, we do not have enough information to do that,
697 so any pseudo reg that is spilled must go to the stack.
699 Return value is TRUE if reload likely left dead insns in the
700 stream and a DCE pass should be run to elimiante them. Else the
701 return value is FALSE. */
703 bool
704 reload (rtx first, int global)
706 int i, n;
707 rtx insn;
708 struct elim_table *ep;
709 basic_block bb;
710 bool inserted;
712 /* Make sure even insns with volatile mem refs are recognizable. */
713 init_recog ();
715 failure = 0;
717 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
719 /* Make sure that the last insn in the chain
720 is not something that needs reloading. */
721 emit_note (NOTE_INSN_DELETED);
723 /* Enable find_equiv_reg to distinguish insns made by reload. */
724 reload_first_uid = get_max_uid ();
726 #ifdef SECONDARY_MEMORY_NEEDED
727 /* Initialize the secondary memory table. */
728 clear_secondary_mem ();
729 #endif
731 /* We don't have a stack slot for any spill reg yet. */
732 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
733 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
735 /* Initialize the save area information for caller-save, in case some
736 are needed. */
737 init_save_areas ();
739 /* Compute which hard registers are now in use
740 as homes for pseudo registers.
741 This is done here rather than (eg) in global_alloc
742 because this point is reached even if not optimizing. */
743 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
744 mark_home_live (i);
746 /* A function that has a nonlocal label that can reach the exit
747 block via non-exceptional paths must save all call-saved
748 registers. */
749 if (cfun->has_nonlocal_label
750 && has_nonexceptional_receiver ())
751 crtl->saves_all_registers = 1;
753 if (crtl->saves_all_registers)
754 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
755 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
756 df_set_regs_ever_live (i, true);
758 /* Find all the pseudo registers that didn't get hard regs
759 but do have known equivalent constants or memory slots.
760 These include parameters (known equivalent to parameter slots)
761 and cse'd or loop-moved constant memory addresses.
763 Record constant equivalents in reg_equiv_constant
764 so they will be substituted by find_reloads.
765 Record memory equivalents in reg_mem_equiv so they can
766 be substituted eventually by altering the REG-rtx's. */
768 grow_reg_equivs ();
769 reg_old_renumber = XCNEWVEC (short, max_regno);
770 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
771 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
772 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
774 CLEAR_HARD_REG_SET (bad_spill_regs_global);
776 init_eliminable_invariants (first, true);
777 init_elim_table ();
779 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
780 stack slots to the pseudos that lack hard regs or equivalents.
781 Do not touch virtual registers. */
783 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
784 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
785 temp_pseudo_reg_arr[n++] = i;
787 if (ira_conflicts_p)
788 /* Ask IRA to order pseudo-registers for better stack slot
789 sharing. */
790 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
792 for (i = 0; i < n; i++)
793 alter_reg (temp_pseudo_reg_arr[i], -1, false);
795 /* If we have some registers we think can be eliminated, scan all insns to
796 see if there is an insn that sets one of these registers to something
797 other than itself plus a constant. If so, the register cannot be
798 eliminated. Doing this scan here eliminates an extra pass through the
799 main reload loop in the most common case where register elimination
800 cannot be done. */
801 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
802 if (INSN_P (insn))
803 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
805 maybe_fix_stack_asms ();
807 insns_need_reload = 0;
808 something_needs_elimination = 0;
810 /* Initialize to -1, which means take the first spill register. */
811 last_spill_reg = -1;
813 /* Spill any hard regs that we know we can't eliminate. */
814 CLEAR_HARD_REG_SET (used_spill_regs);
815 /* There can be multiple ways to eliminate a register;
816 they should be listed adjacently.
817 Elimination for any register fails only if all possible ways fail. */
818 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; )
820 int from = ep->from;
821 int can_eliminate = 0;
824 can_eliminate |= ep->can_eliminate;
825 ep++;
827 while (ep < &reg_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
828 if (! can_eliminate)
829 spill_hard_reg (from, 1);
832 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
833 if (frame_pointer_needed)
834 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
835 #endif
836 finish_spills (global);
838 /* From now on, we may need to generate moves differently. We may also
839 allow modifications of insns which cause them to not be recognized.
840 Any such modifications will be cleaned up during reload itself. */
841 reload_in_progress = 1;
843 /* This loop scans the entire function each go-round
844 and repeats until one repetition spills no additional hard regs. */
845 for (;;)
847 int something_changed;
848 int did_spill;
849 HOST_WIDE_INT starting_frame_size;
851 starting_frame_size = get_frame_size ();
852 something_was_spilled = false;
854 set_initial_elim_offsets ();
855 set_initial_label_offsets ();
857 /* For each pseudo register that has an equivalent location defined,
858 try to eliminate any eliminable registers (such as the frame pointer)
859 assuming initial offsets for the replacement register, which
860 is the normal case.
862 If the resulting location is directly addressable, substitute
863 the MEM we just got directly for the old REG.
865 If it is not addressable but is a constant or the sum of a hard reg
866 and constant, it is probably not addressable because the constant is
867 out of range, in that case record the address; we will generate
868 hairy code to compute the address in a register each time it is
869 needed. Similarly if it is a hard register, but one that is not
870 valid as an address register.
872 If the location is not addressable, but does not have one of the
873 above forms, assign a stack slot. We have to do this to avoid the
874 potential of producing lots of reloads if, e.g., a location involves
875 a pseudo that didn't get a hard register and has an equivalent memory
876 location that also involves a pseudo that didn't get a hard register.
878 Perhaps at some point we will improve reload_when_needed handling
879 so this problem goes away. But that's very hairy. */
881 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
882 if (reg_renumber[i] < 0 && reg_equiv_memory_loc (i))
884 rtx x = eliminate_regs (reg_equiv_memory_loc (i), VOIDmode,
885 NULL_RTX);
887 if (strict_memory_address_addr_space_p
888 (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0),
889 MEM_ADDR_SPACE (x)))
890 reg_equiv_mem (i) = x, reg_equiv_address (i) = 0;
891 else if (CONSTANT_P (XEXP (x, 0))
892 || (REG_P (XEXP (x, 0))
893 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
894 || (GET_CODE (XEXP (x, 0)) == PLUS
895 && REG_P (XEXP (XEXP (x, 0), 0))
896 && (REGNO (XEXP (XEXP (x, 0), 0))
897 < FIRST_PSEUDO_REGISTER)
898 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
899 reg_equiv_address (i) = XEXP (x, 0), reg_equiv_mem (i) = 0;
900 else
902 /* Make a new stack slot. Then indicate that something
903 changed so we go back and recompute offsets for
904 eliminable registers because the allocation of memory
905 below might change some offset. reg_equiv_{mem,address}
906 will be set up for this pseudo on the next pass around
907 the loop. */
908 reg_equiv_memory_loc (i) = 0;
909 reg_equiv_init (i) = 0;
910 alter_reg (i, -1, true);
914 if (caller_save_needed)
915 setup_save_areas ();
917 if (starting_frame_size && crtl->stack_alignment_needed)
919 /* If we have a stack frame, we must align it now. The
920 stack size may be a part of the offset computation for
921 register elimination. So if this changes the stack size,
922 then repeat the elimination bookkeeping. We don't
923 realign when there is no stack, as that will cause a
924 stack frame when none is needed should
925 STARTING_FRAME_OFFSET not be already aligned to
926 STACK_BOUNDARY. */
927 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
929 /* If we allocated another stack slot, redo elimination bookkeeping. */
930 if (something_was_spilled || starting_frame_size != get_frame_size ())
932 update_eliminables_and_spill ();
933 continue;
936 if (caller_save_needed)
938 save_call_clobbered_regs ();
939 /* That might have allocated new insn_chain structures. */
940 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
943 calculate_needs_all_insns (global);
945 if (! ira_conflicts_p)
946 /* Don't do it for IRA. We need this info because we don't
947 change live_throughout and dead_or_set for chains when IRA
948 is used. */
949 CLEAR_REG_SET (&spilled_pseudos);
951 did_spill = 0;
953 something_changed = 0;
955 /* If we allocated any new memory locations, make another pass
956 since it might have changed elimination offsets. */
957 if (something_was_spilled || starting_frame_size != get_frame_size ())
958 something_changed = 1;
960 /* Even if the frame size remained the same, we might still have
961 changed elimination offsets, e.g. if find_reloads called
962 force_const_mem requiring the back end to allocate a constant
963 pool base register that needs to be saved on the stack. */
964 else if (!verify_initial_elim_offsets ())
965 something_changed = 1;
967 if (update_eliminables_and_spill ())
969 did_spill = 1;
970 something_changed = 1;
973 select_reload_regs ();
974 if (failure)
975 goto failed;
977 if (insns_need_reload != 0 || did_spill)
978 something_changed |= finish_spills (global);
980 if (! something_changed)
981 break;
983 if (caller_save_needed)
984 delete_caller_save_insns ();
986 obstack_free (&reload_obstack, reload_firstobj);
989 /* If global-alloc was run, notify it of any register eliminations we have
990 done. */
991 if (global)
992 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
993 if (ep->can_eliminate)
994 mark_elimination (ep->from, ep->to);
996 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
997 If that insn didn't set the register (i.e., it copied the register to
998 memory), just delete that insn instead of the equivalencing insn plus
999 anything now dead. If we call delete_dead_insn on that insn, we may
1000 delete the insn that actually sets the register if the register dies
1001 there and that is incorrect. */
1003 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1005 if (reg_renumber[i] < 0 && reg_equiv_init (i) != 0)
1007 rtx list;
1008 for (list = reg_equiv_init (i); list; list = XEXP (list, 1))
1010 rtx equiv_insn = XEXP (list, 0);
1012 /* If we already deleted the insn or if it may trap, we can't
1013 delete it. The latter case shouldn't happen, but can
1014 if an insn has a variable address, gets a REG_EH_REGION
1015 note added to it, and then gets converted into a load
1016 from a constant address. */
1017 if (NOTE_P (equiv_insn)
1018 || can_throw_internal (equiv_insn))
1020 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1021 delete_dead_insn (equiv_insn);
1022 else
1023 SET_INSN_DELETED (equiv_insn);
1028 /* Use the reload registers where necessary
1029 by generating move instructions to move the must-be-register
1030 values into or out of the reload registers. */
1032 if (insns_need_reload != 0 || something_needs_elimination
1033 || something_needs_operands_changed)
1035 HOST_WIDE_INT old_frame_size = get_frame_size ();
1037 reload_as_needed (global);
1039 gcc_assert (old_frame_size == get_frame_size ());
1041 gcc_assert (verify_initial_elim_offsets ());
1044 /* If we were able to eliminate the frame pointer, show that it is no
1045 longer live at the start of any basic block. If it ls live by
1046 virtue of being in a pseudo, that pseudo will be marked live
1047 and hence the frame pointer will be known to be live via that
1048 pseudo. */
1050 if (! frame_pointer_needed)
1051 FOR_EACH_BB (bb)
1052 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1054 /* Come here (with failure set nonzero) if we can't get enough spill
1055 regs. */
1056 failed:
1058 CLEAR_REG_SET (&changed_allocation_pseudos);
1059 CLEAR_REG_SET (&spilled_pseudos);
1060 reload_in_progress = 0;
1062 /* Now eliminate all pseudo regs by modifying them into
1063 their equivalent memory references.
1064 The REG-rtx's for the pseudos are modified in place,
1065 so all insns that used to refer to them now refer to memory.
1067 For a reg that has a reg_equiv_address, all those insns
1068 were changed by reloading so that no insns refer to it any longer;
1069 but the DECL_RTL of a variable decl may refer to it,
1070 and if so this causes the debugging info to mention the variable. */
1072 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1074 rtx addr = 0;
1076 if (reg_equiv_mem (i))
1077 addr = XEXP (reg_equiv_mem (i), 0);
1079 if (reg_equiv_address (i))
1080 addr = reg_equiv_address (i);
1082 if (addr)
1084 if (reg_renumber[i] < 0)
1086 rtx reg = regno_reg_rtx[i];
1088 REG_USERVAR_P (reg) = 0;
1089 PUT_CODE (reg, MEM);
1090 XEXP (reg, 0) = addr;
1091 if (reg_equiv_memory_loc (i))
1092 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc (i));
1093 else
1094 MEM_ATTRS (reg) = 0;
1095 MEM_NOTRAP_P (reg) = 1;
1097 else if (reg_equiv_mem (i))
1098 XEXP (reg_equiv_mem (i), 0) = addr;
1101 /* We don't want complex addressing modes in debug insns
1102 if simpler ones will do, so delegitimize equivalences
1103 in debug insns. */
1104 if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
1106 rtx reg = regno_reg_rtx[i];
1107 rtx equiv = 0;
1108 df_ref use, next;
1110 if (reg_equiv_constant (i))
1111 equiv = reg_equiv_constant (i);
1112 else if (reg_equiv_invariant (i))
1113 equiv = reg_equiv_invariant (i);
1114 else if (reg && MEM_P (reg))
1115 equiv = targetm.delegitimize_address (reg);
1116 else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1117 equiv = reg;
1119 if (equiv == reg)
1120 continue;
1122 for (use = DF_REG_USE_CHAIN (i); use; use = next)
1124 insn = DF_REF_INSN (use);
1126 /* Make sure the next ref is for a different instruction,
1127 so that we're not affected by the rescan. */
1128 next = DF_REF_NEXT_REG (use);
1129 while (next && DF_REF_INSN (next) == insn)
1130 next = DF_REF_NEXT_REG (next);
1132 if (DEBUG_INSN_P (insn))
1134 if (!equiv)
1136 INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
1137 df_insn_rescan_debug_internal (insn);
1139 else
1140 INSN_VAR_LOCATION_LOC (insn)
1141 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn),
1142 reg, equiv);
1148 /* We must set reload_completed now since the cleanup_subreg_operands call
1149 below will re-recognize each insn and reload may have generated insns
1150 which are only valid during and after reload. */
1151 reload_completed = 1;
1153 /* Make a pass over all the insns and delete all USEs which we inserted
1154 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1155 notes. Delete all CLOBBER insns, except those that refer to the return
1156 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1157 from misarranging variable-array code, and simplify (subreg (reg))
1158 operands. Strip and regenerate REG_INC notes that may have been moved
1159 around. */
1161 for (insn = first; insn; insn = NEXT_INSN (insn))
1162 if (INSN_P (insn))
1164 rtx *pnote;
1166 if (CALL_P (insn))
1167 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1168 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1170 if ((GET_CODE (PATTERN (insn)) == USE
1171 /* We mark with QImode USEs introduced by reload itself. */
1172 && (GET_MODE (insn) == QImode
1173 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1174 || (GET_CODE (PATTERN (insn)) == CLOBBER
1175 && (!MEM_P (XEXP (PATTERN (insn), 0))
1176 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1177 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1178 && XEXP (XEXP (PATTERN (insn), 0), 0)
1179 != stack_pointer_rtx))
1180 && (!REG_P (XEXP (PATTERN (insn), 0))
1181 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1183 delete_insn (insn);
1184 continue;
1187 /* Some CLOBBERs may survive until here and still reference unassigned
1188 pseudos with const equivalent, which may in turn cause ICE in later
1189 passes if the reference remains in place. */
1190 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1191 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1192 VOIDmode, PATTERN (insn));
1194 /* Discard obvious no-ops, even without -O. This optimization
1195 is fast and doesn't interfere with debugging. */
1196 if (NONJUMP_INSN_P (insn)
1197 && GET_CODE (PATTERN (insn)) == SET
1198 && REG_P (SET_SRC (PATTERN (insn)))
1199 && REG_P (SET_DEST (PATTERN (insn)))
1200 && (REGNO (SET_SRC (PATTERN (insn)))
1201 == REGNO (SET_DEST (PATTERN (insn)))))
1203 delete_insn (insn);
1204 continue;
1207 pnote = &REG_NOTES (insn);
1208 while (*pnote != 0)
1210 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1211 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1212 || REG_NOTE_KIND (*pnote) == REG_INC)
1213 *pnote = XEXP (*pnote, 1);
1214 else
1215 pnote = &XEXP (*pnote, 1);
1218 #ifdef AUTO_INC_DEC
1219 add_auto_inc_notes (insn, PATTERN (insn));
1220 #endif
1222 /* Simplify (subreg (reg)) if it appears as an operand. */
1223 cleanup_subreg_operands (insn);
1225 /* Clean up invalid ASMs so that they don't confuse later passes.
1226 See PR 21299. */
1227 if (asm_noperands (PATTERN (insn)) >= 0)
1229 extract_insn (insn);
1230 if (!constrain_operands (1))
1232 error_for_asm (insn,
1233 "%<asm%> operand has impossible constraints");
1234 delete_insn (insn);
1235 continue;
1240 /* If we are doing generic stack checking, give a warning if this
1241 function's frame size is larger than we expect. */
1242 if (flag_stack_check == GENERIC_STACK_CHECK)
1244 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1245 static int verbose_warned = 0;
1247 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1248 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1249 size += UNITS_PER_WORD;
1251 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1253 warning (0, "frame size too large for reliable stack checking");
1254 if (! verbose_warned)
1256 warning (0, "try reducing the number of local variables");
1257 verbose_warned = 1;
1262 free (temp_pseudo_reg_arr);
1264 /* Indicate that we no longer have known memory locations or constants. */
1265 free_reg_equiv ();
1267 free (reg_max_ref_width);
1268 free (reg_old_renumber);
1269 free (pseudo_previous_regs);
1270 free (pseudo_forbidden_regs);
1272 CLEAR_HARD_REG_SET (used_spill_regs);
1273 for (i = 0; i < n_spills; i++)
1274 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1276 /* Free all the insn_chain structures at once. */
1277 obstack_free (&reload_obstack, reload_startobj);
1278 unused_insn_chains = 0;
1280 inserted = fixup_abnormal_edges ();
1282 /* We've possibly turned single trapping insn into multiple ones. */
1283 if (cfun->can_throw_non_call_exceptions)
1285 sbitmap blocks;
1286 blocks = sbitmap_alloc (last_basic_block);
1287 bitmap_ones (blocks);
1288 find_many_sub_basic_blocks (blocks);
1289 sbitmap_free (blocks);
1292 if (inserted)
1293 commit_edge_insertions ();
1295 /* Replacing pseudos with their memory equivalents might have
1296 created shared rtx. Subsequent passes would get confused
1297 by this, so unshare everything here. */
1298 unshare_all_rtl_again (first);
1300 #ifdef STACK_BOUNDARY
1301 /* init_emit has set the alignment of the hard frame pointer
1302 to STACK_BOUNDARY. It is very likely no longer valid if
1303 the hard frame pointer was used for register allocation. */
1304 if (!frame_pointer_needed)
1305 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1306 #endif
1308 substitute_stack.release ();
1310 gcc_assert (bitmap_empty_p (&spilled_pseudos));
1312 reload_completed = !failure;
1314 return need_dce;
1317 /* Yet another special case. Unfortunately, reg-stack forces people to
1318 write incorrect clobbers in asm statements. These clobbers must not
1319 cause the register to appear in bad_spill_regs, otherwise we'll call
1320 fatal_insn later. We clear the corresponding regnos in the live
1321 register sets to avoid this.
1322 The whole thing is rather sick, I'm afraid. */
1324 static void
1325 maybe_fix_stack_asms (void)
1327 #ifdef STACK_REGS
1328 const char *constraints[MAX_RECOG_OPERANDS];
1329 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1330 struct insn_chain *chain;
1332 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1334 int i, noperands;
1335 HARD_REG_SET clobbered, allowed;
1336 rtx pat;
1338 if (! INSN_P (chain->insn)
1339 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1340 continue;
1341 pat = PATTERN (chain->insn);
1342 if (GET_CODE (pat) != PARALLEL)
1343 continue;
1345 CLEAR_HARD_REG_SET (clobbered);
1346 CLEAR_HARD_REG_SET (allowed);
1348 /* First, make a mask of all stack regs that are clobbered. */
1349 for (i = 0; i < XVECLEN (pat, 0); i++)
1351 rtx t = XVECEXP (pat, 0, i);
1352 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1353 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1356 /* Get the operand values and constraints out of the insn. */
1357 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1358 constraints, operand_mode, NULL);
1360 /* For every operand, see what registers are allowed. */
1361 for (i = 0; i < noperands; i++)
1363 const char *p = constraints[i];
1364 /* For every alternative, we compute the class of registers allowed
1365 for reloading in CLS, and merge its contents into the reg set
1366 ALLOWED. */
1367 int cls = (int) NO_REGS;
1369 for (;;)
1371 char c = *p;
1373 if (c == '\0' || c == ',' || c == '#')
1375 /* End of one alternative - mark the regs in the current
1376 class, and reset the class. */
1377 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1378 cls = NO_REGS;
1379 p++;
1380 if (c == '#')
1381 do {
1382 c = *p++;
1383 } while (c != '\0' && c != ',');
1384 if (c == '\0')
1385 break;
1386 continue;
1389 switch (c)
1391 case '=': case '+': case '*': case '%': case '?': case '!':
1392 case '0': case '1': case '2': case '3': case '4': case '<':
1393 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1394 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1395 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1396 case TARGET_MEM_CONSTRAINT:
1397 break;
1399 case 'p':
1400 cls = (int) reg_class_subunion[cls]
1401 [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1402 ADDRESS, SCRATCH)];
1403 break;
1405 case 'g':
1406 case 'r':
1407 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1408 break;
1410 default:
1411 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1412 cls = (int) reg_class_subunion[cls]
1413 [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC,
1414 ADDRESS, SCRATCH)];
1415 else
1416 cls = (int) reg_class_subunion[cls]
1417 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1419 p += CONSTRAINT_LEN (c, p);
1422 /* Those of the registers which are clobbered, but allowed by the
1423 constraints, must be usable as reload registers. So clear them
1424 out of the life information. */
1425 AND_HARD_REG_SET (allowed, clobbered);
1426 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1427 if (TEST_HARD_REG_BIT (allowed, i))
1429 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1430 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1434 #endif
1437 /* Copy the global variables n_reloads and rld into the corresponding elts
1438 of CHAIN. */
1439 static void
1440 copy_reloads (struct insn_chain *chain)
1442 chain->n_reloads = n_reloads;
1443 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1444 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1445 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1448 /* Walk the chain of insns, and determine for each whether it needs reloads
1449 and/or eliminations. Build the corresponding insns_need_reload list, and
1450 set something_needs_elimination as appropriate. */
1451 static void
1452 calculate_needs_all_insns (int global)
1454 struct insn_chain **pprev_reload = &insns_need_reload;
1455 struct insn_chain *chain, *next = 0;
1457 something_needs_elimination = 0;
1459 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1460 for (chain = reload_insn_chain; chain != 0; chain = next)
1462 rtx insn = chain->insn;
1464 next = chain->next;
1466 /* Clear out the shortcuts. */
1467 chain->n_reloads = 0;
1468 chain->need_elim = 0;
1469 chain->need_reload = 0;
1470 chain->need_operand_change = 0;
1472 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1473 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1474 what effects this has on the known offsets at labels. */
1476 if (LABEL_P (insn) || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
1477 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1478 set_label_offsets (insn, insn, 0);
1480 if (INSN_P (insn))
1482 rtx old_body = PATTERN (insn);
1483 int old_code = INSN_CODE (insn);
1484 rtx old_notes = REG_NOTES (insn);
1485 int did_elimination = 0;
1486 int operands_changed = 0;
1487 rtx set = single_set (insn);
1489 /* Skip insns that only set an equivalence. */
1490 if (set && REG_P (SET_DEST (set))
1491 && reg_renumber[REGNO (SET_DEST (set))] < 0
1492 && (reg_equiv_constant (REGNO (SET_DEST (set)))
1493 || (reg_equiv_invariant (REGNO (SET_DEST (set)))))
1494 && reg_equiv_init (REGNO (SET_DEST (set))))
1495 continue;
1497 /* If needed, eliminate any eliminable registers. */
1498 if (num_eliminable || num_eliminable_invariants)
1499 did_elimination = eliminate_regs_in_insn (insn, 0);
1501 /* Analyze the instruction. */
1502 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1503 global, spill_reg_order);
1505 /* If a no-op set needs more than one reload, this is likely
1506 to be something that needs input address reloads. We
1507 can't get rid of this cleanly later, and it is of no use
1508 anyway, so discard it now.
1509 We only do this when expensive_optimizations is enabled,
1510 since this complements reload inheritance / output
1511 reload deletion, and it can make debugging harder. */
1512 if (flag_expensive_optimizations && n_reloads > 1)
1514 rtx set = single_set (insn);
1515 if (set
1517 ((SET_SRC (set) == SET_DEST (set)
1518 && REG_P (SET_SRC (set))
1519 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1520 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1521 && reg_renumber[REGNO (SET_SRC (set))] < 0
1522 && reg_renumber[REGNO (SET_DEST (set))] < 0
1523 && reg_equiv_memory_loc (REGNO (SET_SRC (set))) != NULL
1524 && reg_equiv_memory_loc (REGNO (SET_DEST (set))) != NULL
1525 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set))),
1526 reg_equiv_memory_loc (REGNO (SET_DEST (set)))))))
1528 if (ira_conflicts_p)
1529 /* Inform IRA about the insn deletion. */
1530 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1531 REGNO (SET_SRC (set)));
1532 delete_insn (insn);
1533 /* Delete it from the reload chain. */
1534 if (chain->prev)
1535 chain->prev->next = next;
1536 else
1537 reload_insn_chain = next;
1538 if (next)
1539 next->prev = chain->prev;
1540 chain->next = unused_insn_chains;
1541 unused_insn_chains = chain;
1542 continue;
1545 if (num_eliminable)
1546 update_eliminable_offsets ();
1548 /* Remember for later shortcuts which insns had any reloads or
1549 register eliminations. */
1550 chain->need_elim = did_elimination;
1551 chain->need_reload = n_reloads > 0;
1552 chain->need_operand_change = operands_changed;
1554 /* Discard any register replacements done. */
1555 if (did_elimination)
1557 obstack_free (&reload_obstack, reload_insn_firstobj);
1558 PATTERN (insn) = old_body;
1559 INSN_CODE (insn) = old_code;
1560 REG_NOTES (insn) = old_notes;
1561 something_needs_elimination = 1;
1564 something_needs_operands_changed |= operands_changed;
1566 if (n_reloads != 0)
1568 copy_reloads (chain);
1569 *pprev_reload = chain;
1570 pprev_reload = &chain->next_need_reload;
1574 *pprev_reload = 0;
1577 /* This function is called from the register allocator to set up estimates
1578 for the cost of eliminating pseudos which have REG_EQUIV equivalences to
1579 an invariant. The structure is similar to calculate_needs_all_insns. */
1581 void
1582 calculate_elim_costs_all_insns (void)
1584 int *reg_equiv_init_cost;
1585 basic_block bb;
1586 int i;
1588 reg_equiv_init_cost = XCNEWVEC (int, max_regno);
1589 init_elim_table ();
1590 init_eliminable_invariants (get_insns (), false);
1592 set_initial_elim_offsets ();
1593 set_initial_label_offsets ();
1595 FOR_EACH_BB (bb)
1597 rtx insn;
1598 elim_bb = bb;
1600 FOR_BB_INSNS (bb, insn)
1602 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1603 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1604 what effects this has on the known offsets at labels. */
1606 if (LABEL_P (insn) || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn)
1607 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1608 set_label_offsets (insn, insn, 0);
1610 if (INSN_P (insn))
1612 rtx set = single_set (insn);
1614 /* Skip insns that only set an equivalence. */
1615 if (set && REG_P (SET_DEST (set))
1616 && reg_renumber[REGNO (SET_DEST (set))] < 0
1617 && (reg_equiv_constant (REGNO (SET_DEST (set)))
1618 || reg_equiv_invariant (REGNO (SET_DEST (set)))))
1620 unsigned regno = REGNO (SET_DEST (set));
1621 rtx init = reg_equiv_init (regno);
1622 if (init)
1624 rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn,
1625 false, true);
1626 int cost = set_src_cost (t, optimize_bb_for_speed_p (bb));
1627 int freq = REG_FREQ_FROM_BB (bb);
1629 reg_equiv_init_cost[regno] = cost * freq;
1630 continue;
1633 /* If needed, eliminate any eliminable registers. */
1634 if (num_eliminable || num_eliminable_invariants)
1635 elimination_costs_in_insn (insn);
1637 if (num_eliminable)
1638 update_eliminable_offsets ();
1642 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1644 if (reg_equiv_invariant (i))
1646 if (reg_equiv_init (i))
1648 int cost = reg_equiv_init_cost[i];
1649 if (dump_file)
1650 fprintf (dump_file,
1651 "Reg %d has equivalence, initial gains %d\n", i, cost);
1652 if (cost != 0)
1653 ira_adjust_equiv_reg_cost (i, cost);
1655 else
1657 if (dump_file)
1658 fprintf (dump_file,
1659 "Reg %d had equivalence, but can't be eliminated\n",
1661 ira_adjust_equiv_reg_cost (i, 0);
1666 free (reg_equiv_init_cost);
1667 free (offsets_known_at);
1668 free (offsets_at);
1669 offsets_at = NULL;
1670 offsets_known_at = NULL;
1673 /* Comparison function for qsort to decide which of two reloads
1674 should be handled first. *P1 and *P2 are the reload numbers. */
1676 static int
1677 reload_reg_class_lower (const void *r1p, const void *r2p)
1679 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1680 int t;
1682 /* Consider required reloads before optional ones. */
1683 t = rld[r1].optional - rld[r2].optional;
1684 if (t != 0)
1685 return t;
1687 /* Count all solitary classes before non-solitary ones. */
1688 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1689 - (reg_class_size[(int) rld[r1].rclass] == 1));
1690 if (t != 0)
1691 return t;
1693 /* Aside from solitaires, consider all multi-reg groups first. */
1694 t = rld[r2].nregs - rld[r1].nregs;
1695 if (t != 0)
1696 return t;
1698 /* Consider reloads in order of increasing reg-class number. */
1699 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1700 if (t != 0)
1701 return t;
1703 /* If reloads are equally urgent, sort by reload number,
1704 so that the results of qsort leave nothing to chance. */
1705 return r1 - r2;
1708 /* The cost of spilling each hard reg. */
1709 static int spill_cost[FIRST_PSEUDO_REGISTER];
1711 /* When spilling multiple hard registers, we use SPILL_COST for the first
1712 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1713 only the first hard reg for a multi-reg pseudo. */
1714 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1716 /* Map of hard regno to pseudo regno currently occupying the hard
1717 reg. */
1718 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1720 /* Update the spill cost arrays, considering that pseudo REG is live. */
1722 static void
1723 count_pseudo (int reg)
1725 int freq = REG_FREQ (reg);
1726 int r = reg_renumber[reg];
1727 int nregs;
1729 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1730 if (ira_conflicts_p && r < 0)
1731 return;
1733 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1734 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1735 return;
1737 SET_REGNO_REG_SET (&pseudos_counted, reg);
1739 gcc_assert (r >= 0);
1741 spill_add_cost[r] += freq;
1742 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1743 while (nregs-- > 0)
1745 hard_regno_to_pseudo_regno[r + nregs] = reg;
1746 spill_cost[r + nregs] += freq;
1750 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1751 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1753 static void
1754 order_regs_for_reload (struct insn_chain *chain)
1756 unsigned i;
1757 HARD_REG_SET used_by_pseudos;
1758 HARD_REG_SET used_by_pseudos2;
1759 reg_set_iterator rsi;
1761 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1763 memset (spill_cost, 0, sizeof spill_cost);
1764 memset (spill_add_cost, 0, sizeof spill_add_cost);
1765 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1766 hard_regno_to_pseudo_regno[i] = -1;
1768 /* Count number of uses of each hard reg by pseudo regs allocated to it
1769 and then order them by decreasing use. First exclude hard registers
1770 that are live in or across this insn. */
1772 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1773 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1774 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1775 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1777 /* Now find out which pseudos are allocated to it, and update
1778 hard_reg_n_uses. */
1779 CLEAR_REG_SET (&pseudos_counted);
1781 EXECUTE_IF_SET_IN_REG_SET
1782 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1784 count_pseudo (i);
1786 EXECUTE_IF_SET_IN_REG_SET
1787 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1789 count_pseudo (i);
1791 CLEAR_REG_SET (&pseudos_counted);
1794 /* Vector of reload-numbers showing the order in which the reloads should
1795 be processed. */
1796 static short reload_order[MAX_RELOADS];
1798 /* This is used to keep track of the spill regs used in one insn. */
1799 static HARD_REG_SET used_spill_regs_local;
1801 /* We decided to spill hard register SPILLED, which has a size of
1802 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1803 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1804 update SPILL_COST/SPILL_ADD_COST. */
1806 static void
1807 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1809 int freq = REG_FREQ (reg);
1810 int r = reg_renumber[reg];
1811 int nregs;
1813 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */
1814 if (ira_conflicts_p && r < 0)
1815 return;
1817 gcc_assert (r >= 0);
1819 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1821 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1822 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1823 return;
1825 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1827 spill_add_cost[r] -= freq;
1828 while (nregs-- > 0)
1830 hard_regno_to_pseudo_regno[r + nregs] = -1;
1831 spill_cost[r + nregs] -= freq;
1835 /* Find reload register to use for reload number ORDER. */
1837 static int
1838 find_reg (struct insn_chain *chain, int order)
1840 int rnum = reload_order[order];
1841 struct reload *rl = rld + rnum;
1842 int best_cost = INT_MAX;
1843 int best_reg = -1;
1844 unsigned int i, j, n;
1845 int k;
1846 HARD_REG_SET not_usable;
1847 HARD_REG_SET used_by_other_reload;
1848 reg_set_iterator rsi;
1849 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1850 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1852 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1853 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1854 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1856 CLEAR_HARD_REG_SET (used_by_other_reload);
1857 for (k = 0; k < order; k++)
1859 int other = reload_order[k];
1861 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1862 for (j = 0; j < rld[other].nregs; j++)
1863 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1866 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1868 #ifdef REG_ALLOC_ORDER
1869 unsigned int regno = reg_alloc_order[i];
1870 #else
1871 unsigned int regno = i;
1872 #endif
1874 if (! TEST_HARD_REG_BIT (not_usable, regno)
1875 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1876 && HARD_REGNO_MODE_OK (regno, rl->mode))
1878 int this_cost = spill_cost[regno];
1879 int ok = 1;
1880 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1882 for (j = 1; j < this_nregs; j++)
1884 this_cost += spill_add_cost[regno + j];
1885 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1886 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1887 ok = 0;
1889 if (! ok)
1890 continue;
1892 if (ira_conflicts_p)
1894 /* Ask IRA to find a better pseudo-register for
1895 spilling. */
1896 for (n = j = 0; j < this_nregs; j++)
1898 int r = hard_regno_to_pseudo_regno[regno + j];
1900 if (r < 0)
1901 continue;
1902 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1903 regno_pseudo_regs[n++] = r;
1905 regno_pseudo_regs[n++] = -1;
1906 if (best_reg < 0
1907 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1908 best_regno_pseudo_regs,
1909 rl->in, rl->out,
1910 chain->insn))
1912 best_reg = regno;
1913 for (j = 0;; j++)
1915 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1916 if (regno_pseudo_regs[j] < 0)
1917 break;
1920 continue;
1923 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1924 this_cost--;
1925 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1926 this_cost--;
1927 if (this_cost < best_cost
1928 /* Among registers with equal cost, prefer caller-saved ones, or
1929 use REG_ALLOC_ORDER if it is defined. */
1930 || (this_cost == best_cost
1931 #ifdef REG_ALLOC_ORDER
1932 && (inv_reg_alloc_order[regno]
1933 < inv_reg_alloc_order[best_reg])
1934 #else
1935 && call_used_regs[regno]
1936 && ! call_used_regs[best_reg]
1937 #endif
1940 best_reg = regno;
1941 best_cost = this_cost;
1945 if (best_reg == -1)
1946 return 0;
1948 if (dump_file)
1949 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1951 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1952 rl->regno = best_reg;
1954 EXECUTE_IF_SET_IN_REG_SET
1955 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1957 count_spilled_pseudo (best_reg, rl->nregs, j);
1960 EXECUTE_IF_SET_IN_REG_SET
1961 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1963 count_spilled_pseudo (best_reg, rl->nregs, j);
1966 for (i = 0; i < rl->nregs; i++)
1968 gcc_assert (spill_cost[best_reg + i] == 0);
1969 gcc_assert (spill_add_cost[best_reg + i] == 0);
1970 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1971 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1973 return 1;
1976 /* Find more reload regs to satisfy the remaining need of an insn, which
1977 is given by CHAIN.
1978 Do it by ascending class number, since otherwise a reg
1979 might be spilled for a big class and might fail to count
1980 for a smaller class even though it belongs to that class. */
1982 static void
1983 find_reload_regs (struct insn_chain *chain)
1985 int i;
1987 /* In order to be certain of getting the registers we need,
1988 we must sort the reloads into order of increasing register class.
1989 Then our grabbing of reload registers will parallel the process
1990 that provided the reload registers. */
1991 for (i = 0; i < chain->n_reloads; i++)
1993 /* Show whether this reload already has a hard reg. */
1994 if (chain->rld[i].reg_rtx)
1996 int regno = REGNO (chain->rld[i].reg_rtx);
1997 chain->rld[i].regno = regno;
1998 chain->rld[i].nregs
1999 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
2001 else
2002 chain->rld[i].regno = -1;
2003 reload_order[i] = i;
2006 n_reloads = chain->n_reloads;
2007 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
2009 CLEAR_HARD_REG_SET (used_spill_regs_local);
2011 if (dump_file)
2012 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2014 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2016 /* Compute the order of preference for hard registers to spill. */
2018 order_regs_for_reload (chain);
2020 for (i = 0; i < n_reloads; i++)
2022 int r = reload_order[i];
2024 /* Ignore reloads that got marked inoperative. */
2025 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2026 && ! rld[r].optional
2027 && rld[r].regno == -1)
2028 if (! find_reg (chain, i))
2030 if (dump_file)
2031 fprintf (dump_file, "reload failure for reload %d\n", r);
2032 spill_failure (chain->insn, rld[r].rclass);
2033 failure = 1;
2034 return;
2038 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2039 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2041 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2044 static void
2045 select_reload_regs (void)
2047 struct insn_chain *chain;
2049 /* Try to satisfy the needs for each insn. */
2050 for (chain = insns_need_reload; chain != 0;
2051 chain = chain->next_need_reload)
2052 find_reload_regs (chain);
2055 /* Delete all insns that were inserted by emit_caller_save_insns during
2056 this iteration. */
2057 static void
2058 delete_caller_save_insns (void)
2060 struct insn_chain *c = reload_insn_chain;
2062 while (c != 0)
2064 while (c != 0 && c->is_caller_save_insn)
2066 struct insn_chain *next = c->next;
2067 rtx insn = c->insn;
2069 if (c == reload_insn_chain)
2070 reload_insn_chain = next;
2071 delete_insn (insn);
2073 if (next)
2074 next->prev = c->prev;
2075 if (c->prev)
2076 c->prev->next = next;
2077 c->next = unused_insn_chains;
2078 unused_insn_chains = c;
2079 c = next;
2081 if (c != 0)
2082 c = c->next;
2086 /* Handle the failure to find a register to spill.
2087 INSN should be one of the insns which needed this particular spill reg. */
2089 static void
2090 spill_failure (rtx insn, enum reg_class rclass)
2092 if (asm_noperands (PATTERN (insn)) >= 0)
2093 error_for_asm (insn, "can%'t find a register in class %qs while "
2094 "reloading %<asm%>",
2095 reg_class_names[rclass]);
2096 else
2098 error ("unable to find a register to spill in class %qs",
2099 reg_class_names[rclass]);
2101 if (dump_file)
2103 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2104 debug_reload_to_stream (dump_file);
2106 fatal_insn ("this is the insn:", insn);
2110 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2111 data that is dead in INSN. */
2113 static void
2114 delete_dead_insn (rtx insn)
2116 rtx prev = prev_active_insn (insn);
2117 rtx prev_dest;
2119 /* If the previous insn sets a register that dies in our insn make
2120 a note that we want to run DCE immediately after reload.
2122 We used to delete the previous insn & recurse, but that's wrong for
2123 block local equivalences. Instead of trying to figure out the exact
2124 circumstances where we can delete the potentially dead insns, just
2125 let DCE do the job. */
2126 if (prev && GET_CODE (PATTERN (prev)) == SET
2127 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2128 && reg_mentioned_p (prev_dest, PATTERN (insn))
2129 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2130 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2131 need_dce = 1;
2133 SET_INSN_DELETED (insn);
2136 /* Modify the home of pseudo-reg I.
2137 The new home is present in reg_renumber[I].
2139 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2140 or it may be -1, meaning there is none or it is not relevant.
2141 This is used so that all pseudos spilled from a given hard reg
2142 can share one stack slot. */
2144 static void
2145 alter_reg (int i, int from_reg, bool dont_share_p)
2147 /* When outputting an inline function, this can happen
2148 for a reg that isn't actually used. */
2149 if (regno_reg_rtx[i] == 0)
2150 return;
2152 /* If the reg got changed to a MEM at rtl-generation time,
2153 ignore it. */
2154 if (!REG_P (regno_reg_rtx[i]))
2155 return;
2157 /* Modify the reg-rtx to contain the new hard reg
2158 number or else to contain its pseudo reg number. */
2159 SET_REGNO (regno_reg_rtx[i],
2160 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2162 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2163 allocate a stack slot for it. */
2165 if (reg_renumber[i] < 0
2166 && REG_N_REFS (i) > 0
2167 && reg_equiv_constant (i) == 0
2168 && (reg_equiv_invariant (i) == 0
2169 || reg_equiv_init (i) == 0)
2170 && reg_equiv_memory_loc (i) == 0)
2172 rtx x = NULL_RTX;
2173 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2174 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2175 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2176 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2177 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2178 int adjust = 0;
2180 something_was_spilled = true;
2182 if (ira_conflicts_p)
2184 /* Mark the spill for IRA. */
2185 SET_REGNO_REG_SET (&spilled_pseudos, i);
2186 if (!dont_share_p)
2187 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2190 if (x)
2193 /* Each pseudo reg has an inherent size which comes from its own mode,
2194 and a total size which provides room for paradoxical subregs
2195 which refer to the pseudo reg in wider modes.
2197 We can use a slot already allocated if it provides both
2198 enough inherent space and enough total space.
2199 Otherwise, we allocate a new slot, making sure that it has no less
2200 inherent space, and no less total space, then the previous slot. */
2201 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2203 rtx stack_slot;
2205 /* No known place to spill from => no slot to reuse. */
2206 x = assign_stack_local (mode, total_size,
2207 min_align > inherent_align
2208 || total_size > inherent_size ? -1 : 0);
2210 stack_slot = x;
2212 /* Cancel the big-endian correction done in assign_stack_local.
2213 Get the address of the beginning of the slot. This is so we
2214 can do a big-endian correction unconditionally below. */
2215 if (BYTES_BIG_ENDIAN)
2217 adjust = inherent_size - total_size;
2218 if (adjust)
2219 stack_slot
2220 = adjust_address_nv (x, mode_for_size (total_size
2221 * BITS_PER_UNIT,
2222 MODE_INT, 1),
2223 adjust);
2226 if (! dont_share_p && ira_conflicts_p)
2227 /* Inform IRA about allocation a new stack slot. */
2228 ira_mark_new_stack_slot (stack_slot, i, total_size);
2231 /* Reuse a stack slot if possible. */
2232 else if (spill_stack_slot[from_reg] != 0
2233 && spill_stack_slot_width[from_reg] >= total_size
2234 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2235 >= inherent_size)
2236 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2237 x = spill_stack_slot[from_reg];
2239 /* Allocate a bigger slot. */
2240 else
2242 /* Compute maximum size needed, both for inherent size
2243 and for total size. */
2244 rtx stack_slot;
2246 if (spill_stack_slot[from_reg])
2248 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2249 > inherent_size)
2250 mode = GET_MODE (spill_stack_slot[from_reg]);
2251 if (spill_stack_slot_width[from_reg] > total_size)
2252 total_size = spill_stack_slot_width[from_reg];
2253 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2254 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2257 /* Make a slot with that size. */
2258 x = assign_stack_local (mode, total_size,
2259 min_align > inherent_align
2260 || total_size > inherent_size ? -1 : 0);
2261 stack_slot = x;
2263 /* Cancel the big-endian correction done in assign_stack_local.
2264 Get the address of the beginning of the slot. This is so we
2265 can do a big-endian correction unconditionally below. */
2266 if (BYTES_BIG_ENDIAN)
2268 adjust = GET_MODE_SIZE (mode) - total_size;
2269 if (adjust)
2270 stack_slot
2271 = adjust_address_nv (x, mode_for_size (total_size
2272 * BITS_PER_UNIT,
2273 MODE_INT, 1),
2274 adjust);
2277 spill_stack_slot[from_reg] = stack_slot;
2278 spill_stack_slot_width[from_reg] = total_size;
2281 /* On a big endian machine, the "address" of the slot
2282 is the address of the low part that fits its inherent mode. */
2283 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2284 adjust += (total_size - inherent_size);
2286 /* If we have any adjustment to make, or if the stack slot is the
2287 wrong mode, make a new stack slot. */
2288 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2290 /* Set all of the memory attributes as appropriate for a spill. */
2291 set_mem_attrs_for_spill (x);
2293 /* Save the stack slot for later. */
2294 reg_equiv_memory_loc (i) = x;
2298 /* Mark the slots in regs_ever_live for the hard regs used by
2299 pseudo-reg number REGNO, accessed in MODE. */
2301 static void
2302 mark_home_live_1 (int regno, enum machine_mode mode)
2304 int i, lim;
2306 i = reg_renumber[regno];
2307 if (i < 0)
2308 return;
2309 lim = end_hard_regno (mode, i);
2310 while (i < lim)
2311 df_set_regs_ever_live (i++, true);
2314 /* Mark the slots in regs_ever_live for the hard regs
2315 used by pseudo-reg number REGNO. */
2317 void
2318 mark_home_live (int regno)
2320 if (reg_renumber[regno] >= 0)
2321 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2324 /* This function handles the tracking of elimination offsets around branches.
2326 X is a piece of RTL being scanned.
2328 INSN is the insn that it came from, if any.
2330 INITIAL_P is nonzero if we are to set the offset to be the initial
2331 offset and zero if we are setting the offset of the label to be the
2332 current offset. */
2334 static void
2335 set_label_offsets (rtx x, rtx insn, int initial_p)
2337 enum rtx_code code = GET_CODE (x);
2338 rtx tem;
2339 unsigned int i;
2340 struct elim_table *p;
2342 switch (code)
2344 case LABEL_REF:
2345 if (LABEL_REF_NONLOCAL_P (x))
2346 return;
2348 x = XEXP (x, 0);
2350 /* ... fall through ... */
2352 case CODE_LABEL:
2353 /* If we know nothing about this label, set the desired offsets. Note
2354 that this sets the offset at a label to be the offset before a label
2355 if we don't know anything about the label. This is not correct for
2356 the label after a BARRIER, but is the best guess we can make. If
2357 we guessed wrong, we will suppress an elimination that might have
2358 been possible had we been able to guess correctly. */
2360 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2362 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2363 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2364 = (initial_p ? reg_eliminate[i].initial_offset
2365 : reg_eliminate[i].offset);
2366 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2369 /* Otherwise, if this is the definition of a label and it is
2370 preceded by a BARRIER, set our offsets to the known offset of
2371 that label. */
2373 else if (x == insn
2374 && (tem = prev_nonnote_insn (insn)) != 0
2375 && BARRIER_P (tem))
2376 set_offsets_for_label (insn);
2377 else
2378 /* If neither of the above cases is true, compare each offset
2379 with those previously recorded and suppress any eliminations
2380 where the offsets disagree. */
2382 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2383 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2384 != (initial_p ? reg_eliminate[i].initial_offset
2385 : reg_eliminate[i].offset))
2386 reg_eliminate[i].can_eliminate = 0;
2388 return;
2390 case JUMP_TABLE_DATA:
2391 set_label_offsets (PATTERN (insn), insn, initial_p);
2392 return;
2394 case JUMP_INSN:
2395 set_label_offsets (PATTERN (insn), insn, initial_p);
2397 /* ... fall through ... */
2399 case INSN:
2400 case CALL_INSN:
2401 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2402 to indirectly and hence must have all eliminations at their
2403 initial offsets. */
2404 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2405 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2406 set_label_offsets (XEXP (tem, 0), insn, 1);
2407 return;
2409 case PARALLEL:
2410 case ADDR_VEC:
2411 case ADDR_DIFF_VEC:
2412 /* Each of the labels in the parallel or address vector must be
2413 at their initial offsets. We want the first field for PARALLEL
2414 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2416 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2417 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2418 insn, initial_p);
2419 return;
2421 case SET:
2422 /* We only care about setting PC. If the source is not RETURN,
2423 IF_THEN_ELSE, or a label, disable any eliminations not at
2424 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2425 isn't one of those possibilities. For branches to a label,
2426 call ourselves recursively.
2428 Note that this can disable elimination unnecessarily when we have
2429 a non-local goto since it will look like a non-constant jump to
2430 someplace in the current function. This isn't a significant
2431 problem since such jumps will normally be when all elimination
2432 pairs are back to their initial offsets. */
2434 if (SET_DEST (x) != pc_rtx)
2435 return;
2437 switch (GET_CODE (SET_SRC (x)))
2439 case PC:
2440 case RETURN:
2441 return;
2443 case LABEL_REF:
2444 set_label_offsets (SET_SRC (x), insn, initial_p);
2445 return;
2447 case IF_THEN_ELSE:
2448 tem = XEXP (SET_SRC (x), 1);
2449 if (GET_CODE (tem) == LABEL_REF)
2450 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2451 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2452 break;
2454 tem = XEXP (SET_SRC (x), 2);
2455 if (GET_CODE (tem) == LABEL_REF)
2456 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2457 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2458 break;
2459 return;
2461 default:
2462 break;
2465 /* If we reach here, all eliminations must be at their initial
2466 offset because we are doing a jump to a variable address. */
2467 for (p = reg_eliminate; p < &reg_eliminate[NUM_ELIMINABLE_REGS]; p++)
2468 if (p->offset != p->initial_offset)
2469 p->can_eliminate = 0;
2470 break;
2472 default:
2473 break;
2477 /* Called through for_each_rtx, this function examines every reg that occurs
2478 in PX and adjusts the costs for its elimination which are gathered by IRA.
2479 DATA is the insn in which PX occurs. We do not recurse into MEM
2480 expressions. */
2482 static int
2483 note_reg_elim_costly (rtx *px, void *data)
2485 rtx insn = (rtx)data;
2486 rtx x = *px;
2488 if (MEM_P (x))
2489 return -1;
2491 if (REG_P (x)
2492 && REGNO (x) >= FIRST_PSEUDO_REGISTER
2493 && reg_equiv_init (REGNO (x))
2494 && reg_equiv_invariant (REGNO (x)))
2496 rtx t = reg_equiv_invariant (REGNO (x));
2497 rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true);
2498 int cost = set_src_cost (new_rtx, optimize_bb_for_speed_p (elim_bb));
2499 int freq = REG_FREQ_FROM_BB (elim_bb);
2501 if (cost != 0)
2502 ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq);
2504 return 0;
2507 /* Scan X and replace any eliminable registers (such as fp) with a
2508 replacement (such as sp), plus an offset.
2510 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2511 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2512 MEM, we are allowed to replace a sum of a register and the constant zero
2513 with the register, which we cannot do outside a MEM. In addition, we need
2514 to record the fact that a register is referenced outside a MEM.
2516 If INSN is an insn, it is the insn containing X. If we replace a REG
2517 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2518 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2519 the REG is being modified.
2521 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2522 That's used when we eliminate in expressions stored in notes.
2523 This means, do not set ref_outside_mem even if the reference
2524 is outside of MEMs.
2526 If FOR_COSTS is true, we are being called before reload in order to
2527 estimate the costs of keeping registers with an equivalence unallocated.
2529 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2530 replacements done assuming all offsets are at their initial values. If
2531 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2532 encounter, return the actual location so that find_reloads will do
2533 the proper thing. */
2535 static rtx
2536 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2537 bool may_use_invariant, bool for_costs)
2539 enum rtx_code code = GET_CODE (x);
2540 struct elim_table *ep;
2541 int regno;
2542 rtx new_rtx;
2543 int i, j;
2544 const char *fmt;
2545 int copied = 0;
2547 if (! current_function_decl)
2548 return x;
2550 switch (code)
2552 CASE_CONST_ANY:
2553 case CONST:
2554 case SYMBOL_REF:
2555 case CODE_LABEL:
2556 case PC:
2557 case CC0:
2558 case ASM_INPUT:
2559 case ADDR_VEC:
2560 case ADDR_DIFF_VEC:
2561 case RETURN:
2562 return x;
2564 case REG:
2565 regno = REGNO (x);
2567 /* First handle the case where we encounter a bare register that
2568 is eliminable. Replace it with a PLUS. */
2569 if (regno < FIRST_PSEUDO_REGISTER)
2571 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
2572 ep++)
2573 if (ep->from_rtx == x && ep->can_eliminate)
2574 return plus_constant (Pmode, ep->to_rtx, ep->previous_offset);
2577 else if (reg_renumber && reg_renumber[regno] < 0
2578 && reg_equivs
2579 && reg_equiv_invariant (regno))
2581 if (may_use_invariant || (insn && DEBUG_INSN_P (insn)))
2582 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno)),
2583 mem_mode, insn, true, for_costs);
2584 /* There exists at least one use of REGNO that cannot be
2585 eliminated. Prevent the defining insn from being deleted. */
2586 reg_equiv_init (regno) = NULL_RTX;
2587 if (!for_costs)
2588 alter_reg (regno, -1, true);
2590 return x;
2592 /* You might think handling MINUS in a manner similar to PLUS is a
2593 good idea. It is not. It has been tried multiple times and every
2594 time the change has had to have been reverted.
2596 Other parts of reload know a PLUS is special (gen_reload for example)
2597 and require special code to handle code a reloaded PLUS operand.
2599 Also consider backends where the flags register is clobbered by a
2600 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2601 lea instruction comes to mind). If we try to reload a MINUS, we
2602 may kill the flags register that was holding a useful value.
2604 So, please before trying to handle MINUS, consider reload as a
2605 whole instead of this little section as well as the backend issues. */
2606 case PLUS:
2607 /* If this is the sum of an eliminable register and a constant, rework
2608 the sum. */
2609 if (REG_P (XEXP (x, 0))
2610 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2611 && CONSTANT_P (XEXP (x, 1)))
2613 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
2614 ep++)
2615 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2617 /* The only time we want to replace a PLUS with a REG (this
2618 occurs when the constant operand of the PLUS is the negative
2619 of the offset) is when we are inside a MEM. We won't want
2620 to do so at other times because that would change the
2621 structure of the insn in a way that reload can't handle.
2622 We special-case the commonest situation in
2623 eliminate_regs_in_insn, so just replace a PLUS with a
2624 PLUS here, unless inside a MEM. */
2625 if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2626 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2627 return ep->to_rtx;
2628 else
2629 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2630 plus_constant (Pmode, XEXP (x, 1),
2631 ep->previous_offset));
2634 /* If the register is not eliminable, we are done since the other
2635 operand is a constant. */
2636 return x;
2639 /* If this is part of an address, we want to bring any constant to the
2640 outermost PLUS. We will do this by doing register replacement in
2641 our operands and seeing if a constant shows up in one of them.
2643 Note that there is no risk of modifying the structure of the insn,
2644 since we only get called for its operands, thus we are either
2645 modifying the address inside a MEM, or something like an address
2646 operand of a load-address insn. */
2649 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2650 for_costs);
2651 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2652 for_costs);
2654 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2656 /* If one side is a PLUS and the other side is a pseudo that
2657 didn't get a hard register but has a reg_equiv_constant,
2658 we must replace the constant here since it may no longer
2659 be in the position of any operand. */
2660 if (GET_CODE (new0) == PLUS && REG_P (new1)
2661 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2662 && reg_renumber[REGNO (new1)] < 0
2663 && reg_equivs
2664 && reg_equiv_constant (REGNO (new1)) != 0)
2665 new1 = reg_equiv_constant (REGNO (new1));
2666 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2667 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2668 && reg_renumber[REGNO (new0)] < 0
2669 && reg_equiv_constant (REGNO (new0)) != 0)
2670 new0 = reg_equiv_constant (REGNO (new0));
2672 new_rtx = form_sum (GET_MODE (x), new0, new1);
2674 /* As above, if we are not inside a MEM we do not want to
2675 turn a PLUS into something else. We might try to do so here
2676 for an addition of 0 if we aren't optimizing. */
2677 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2678 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2679 else
2680 return new_rtx;
2683 return x;
2685 case MULT:
2686 /* If this is the product of an eliminable register and a
2687 constant, apply the distribute law and move the constant out
2688 so that we have (plus (mult ..) ..). This is needed in order
2689 to keep load-address insns valid. This case is pathological.
2690 We ignore the possibility of overflow here. */
2691 if (REG_P (XEXP (x, 0))
2692 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2693 && CONST_INT_P (XEXP (x, 1)))
2694 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
2695 ep++)
2696 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2698 if (! mem_mode
2699 /* Refs inside notes or in DEBUG_INSNs don't count for
2700 this purpose. */
2701 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2702 || GET_CODE (insn) == INSN_LIST
2703 || DEBUG_INSN_P (insn))))
2704 ep->ref_outside_mem = 1;
2706 return
2707 plus_constant (Pmode,
2708 gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2709 ep->previous_offset * INTVAL (XEXP (x, 1)));
2712 /* ... fall through ... */
2714 case CALL:
2715 case COMPARE:
2716 /* See comments before PLUS about handling MINUS. */
2717 case MINUS:
2718 case DIV: case UDIV:
2719 case MOD: case UMOD:
2720 case AND: case IOR: case XOR:
2721 case ROTATERT: case ROTATE:
2722 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2723 case NE: case EQ:
2724 case GE: case GT: case GEU: case GTU:
2725 case LE: case LT: case LEU: case LTU:
2727 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2728 for_costs);
2729 rtx new1 = XEXP (x, 1)
2730 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false,
2731 for_costs) : 0;
2733 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2734 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2736 return x;
2738 case EXPR_LIST:
2739 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2740 if (XEXP (x, 0))
2742 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true,
2743 for_costs);
2744 if (new_rtx != XEXP (x, 0))
2746 /* If this is a REG_DEAD note, it is not valid anymore.
2747 Using the eliminated version could result in creating a
2748 REG_DEAD note for the stack or frame pointer. */
2749 if (REG_NOTE_KIND (x) == REG_DEAD)
2750 return (XEXP (x, 1)
2751 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2752 for_costs)
2753 : NULL_RTX);
2755 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2759 /* ... fall through ... */
2761 case INSN_LIST:
2762 case INT_LIST:
2763 /* Now do eliminations in the rest of the chain. If this was
2764 an EXPR_LIST, this might result in allocating more memory than is
2765 strictly needed, but it simplifies the code. */
2766 if (XEXP (x, 1))
2768 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true,
2769 for_costs);
2770 if (new_rtx != XEXP (x, 1))
2771 return
2772 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2774 return x;
2776 case PRE_INC:
2777 case POST_INC:
2778 case PRE_DEC:
2779 case POST_DEC:
2780 /* We do not support elimination of a register that is modified.
2781 elimination_effects has already make sure that this does not
2782 happen. */
2783 return x;
2785 case PRE_MODIFY:
2786 case POST_MODIFY:
2787 /* We do not support elimination of a register that is modified.
2788 elimination_effects has already make sure that this does not
2789 happen. The only remaining case we need to consider here is
2790 that the increment value may be an eliminable register. */
2791 if (GET_CODE (XEXP (x, 1)) == PLUS
2792 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2794 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2795 insn, true, for_costs);
2797 if (new_rtx != XEXP (XEXP (x, 1), 1))
2798 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2799 gen_rtx_PLUS (GET_MODE (x),
2800 XEXP (x, 0), new_rtx));
2802 return x;
2804 case STRICT_LOW_PART:
2805 case NEG: case NOT:
2806 case SIGN_EXTEND: case ZERO_EXTEND:
2807 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2808 case FLOAT: case FIX:
2809 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2810 case ABS:
2811 case SQRT:
2812 case FFS:
2813 case CLZ:
2814 case CTZ:
2815 case POPCOUNT:
2816 case PARITY:
2817 case BSWAP:
2818 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false,
2819 for_costs);
2820 if (new_rtx != XEXP (x, 0))
2821 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2822 return x;
2824 case SUBREG:
2825 /* Similar to above processing, but preserve SUBREG_BYTE.
2826 Convert (subreg (mem)) to (mem) if not paradoxical.
2827 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2828 pseudo didn't get a hard reg, we must replace this with the
2829 eliminated version of the memory location because push_reload
2830 may do the replacement in certain circumstances. */
2831 if (REG_P (SUBREG_REG (x))
2832 && !paradoxical_subreg_p (x)
2833 && reg_equivs
2834 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
2836 new_rtx = SUBREG_REG (x);
2838 else
2839 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false, for_costs);
2841 if (new_rtx != SUBREG_REG (x))
2843 int x_size = GET_MODE_SIZE (GET_MODE (x));
2844 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2846 if (MEM_P (new_rtx)
2847 && ((x_size < new_size
2848 #ifdef WORD_REGISTER_OPERATIONS
2849 /* On these machines, combine can create rtl of the form
2850 (set (subreg:m1 (reg:m2 R) 0) ...)
2851 where m1 < m2, and expects something interesting to
2852 happen to the entire word. Moreover, it will use the
2853 (reg:m2 R) later, expecting all bits to be preserved.
2854 So if the number of words is the same, preserve the
2855 subreg so that push_reload can see it. */
2856 && ! ((x_size - 1) / UNITS_PER_WORD
2857 == (new_size -1 ) / UNITS_PER_WORD)
2858 #endif
2860 || x_size == new_size)
2862 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2863 else
2864 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2867 return x;
2869 case MEM:
2870 /* Our only special processing is to pass the mode of the MEM to our
2871 recursive call and copy the flags. While we are here, handle this
2872 case more efficiently. */
2874 new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true,
2875 for_costs);
2876 if (for_costs
2877 && memory_address_p (GET_MODE (x), XEXP (x, 0))
2878 && !memory_address_p (GET_MODE (x), new_rtx))
2879 for_each_rtx (&XEXP (x, 0), note_reg_elim_costly, insn);
2881 return replace_equiv_address_nv (x, new_rtx);
2883 case USE:
2884 /* Handle insn_list USE that a call to a pure function may generate. */
2885 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false,
2886 for_costs);
2887 if (new_rtx != XEXP (x, 0))
2888 return gen_rtx_USE (GET_MODE (x), new_rtx);
2889 return x;
2891 case CLOBBER:
2892 case ASM_OPERANDS:
2893 gcc_assert (insn && DEBUG_INSN_P (insn));
2894 break;
2896 case SET:
2897 gcc_unreachable ();
2899 default:
2900 break;
2903 /* Process each of our operands recursively. If any have changed, make a
2904 copy of the rtx. */
2905 fmt = GET_RTX_FORMAT (code);
2906 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2908 if (*fmt == 'e')
2910 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false,
2911 for_costs);
2912 if (new_rtx != XEXP (x, i) && ! copied)
2914 x = shallow_copy_rtx (x);
2915 copied = 1;
2917 XEXP (x, i) = new_rtx;
2919 else if (*fmt == 'E')
2921 int copied_vec = 0;
2922 for (j = 0; j < XVECLEN (x, i); j++)
2924 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false,
2925 for_costs);
2926 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2928 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2929 XVEC (x, i)->elem);
2930 if (! copied)
2932 x = shallow_copy_rtx (x);
2933 copied = 1;
2935 XVEC (x, i) = new_v;
2936 copied_vec = 1;
2938 XVECEXP (x, i, j) = new_rtx;
2943 return x;
2947 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2949 return eliminate_regs_1 (x, mem_mode, insn, false, false);
2952 /* Scan rtx X for modifications of elimination target registers. Update
2953 the table of eliminables to reflect the changed state. MEM_MODE is
2954 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2956 static void
2957 elimination_effects (rtx x, enum machine_mode mem_mode)
2959 enum rtx_code code = GET_CODE (x);
2960 struct elim_table *ep;
2961 int regno;
2962 int i, j;
2963 const char *fmt;
2965 switch (code)
2967 CASE_CONST_ANY:
2968 case CONST:
2969 case SYMBOL_REF:
2970 case CODE_LABEL:
2971 case PC:
2972 case CC0:
2973 case ASM_INPUT:
2974 case ADDR_VEC:
2975 case ADDR_DIFF_VEC:
2976 case RETURN:
2977 return;
2979 case REG:
2980 regno = REGNO (x);
2982 /* First handle the case where we encounter a bare register that
2983 is eliminable. Replace it with a PLUS. */
2984 if (regno < FIRST_PSEUDO_REGISTER)
2986 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
2987 ep++)
2988 if (ep->from_rtx == x && ep->can_eliminate)
2990 if (! mem_mode)
2991 ep->ref_outside_mem = 1;
2992 return;
2996 else if (reg_renumber[regno] < 0
2997 && reg_equivs
2998 && reg_equiv_constant (regno)
2999 && ! function_invariant_p (reg_equiv_constant (regno)))
3000 elimination_effects (reg_equiv_constant (regno), mem_mode);
3001 return;
3003 case PRE_INC:
3004 case POST_INC:
3005 case PRE_DEC:
3006 case POST_DEC:
3007 case POST_MODIFY:
3008 case PRE_MODIFY:
3009 /* If we modify the source of an elimination rule, disable it. */
3010 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3011 if (ep->from_rtx == XEXP (x, 0))
3012 ep->can_eliminate = 0;
3014 /* If we modify the target of an elimination rule by adding a constant,
3015 update its offset. If we modify the target in any other way, we'll
3016 have to disable the rule as well. */
3017 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3018 if (ep->to_rtx == XEXP (x, 0))
3020 int size = GET_MODE_SIZE (mem_mode);
3022 /* If more bytes than MEM_MODE are pushed, account for them. */
3023 #ifdef PUSH_ROUNDING
3024 if (ep->to_rtx == stack_pointer_rtx)
3025 size = PUSH_ROUNDING (size);
3026 #endif
3027 if (code == PRE_DEC || code == POST_DEC)
3028 ep->offset += size;
3029 else if (code == PRE_INC || code == POST_INC)
3030 ep->offset -= size;
3031 else if (code == PRE_MODIFY || code == POST_MODIFY)
3033 if (GET_CODE (XEXP (x, 1)) == PLUS
3034 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3035 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3036 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3037 else
3038 ep->can_eliminate = 0;
3042 /* These two aren't unary operators. */
3043 if (code == POST_MODIFY || code == PRE_MODIFY)
3044 break;
3046 /* Fall through to generic unary operation case. */
3047 case STRICT_LOW_PART:
3048 case NEG: case NOT:
3049 case SIGN_EXTEND: case ZERO_EXTEND:
3050 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3051 case FLOAT: case FIX:
3052 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3053 case ABS:
3054 case SQRT:
3055 case FFS:
3056 case CLZ:
3057 case CTZ:
3058 case POPCOUNT:
3059 case PARITY:
3060 case BSWAP:
3061 elimination_effects (XEXP (x, 0), mem_mode);
3062 return;
3064 case SUBREG:
3065 if (REG_P (SUBREG_REG (x))
3066 && (GET_MODE_SIZE (GET_MODE (x))
3067 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3068 && reg_equivs
3069 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0)
3070 return;
3072 elimination_effects (SUBREG_REG (x), mem_mode);
3073 return;
3075 case USE:
3076 /* If using a register that is the source of an eliminate we still
3077 think can be performed, note it cannot be performed since we don't
3078 know how this register is used. */
3079 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3080 if (ep->from_rtx == XEXP (x, 0))
3081 ep->can_eliminate = 0;
3083 elimination_effects (XEXP (x, 0), mem_mode);
3084 return;
3086 case CLOBBER:
3087 /* If clobbering a register that is the replacement register for an
3088 elimination we still think can be performed, note that it cannot
3089 be performed. Otherwise, we need not be concerned about it. */
3090 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3091 if (ep->to_rtx == XEXP (x, 0))
3092 ep->can_eliminate = 0;
3094 elimination_effects (XEXP (x, 0), mem_mode);
3095 return;
3097 case SET:
3098 /* Check for setting a register that we know about. */
3099 if (REG_P (SET_DEST (x)))
3101 /* See if this is setting the replacement register for an
3102 elimination.
3104 If DEST is the hard frame pointer, we do nothing because we
3105 assume that all assignments to the frame pointer are for
3106 non-local gotos and are being done at a time when they are valid
3107 and do not disturb anything else. Some machines want to
3108 eliminate a fake argument pointer (or even a fake frame pointer)
3109 with either the real frame or the stack pointer. Assignments to
3110 the hard frame pointer must not prevent this elimination. */
3112 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
3113 ep++)
3114 if (ep->to_rtx == SET_DEST (x)
3115 && SET_DEST (x) != hard_frame_pointer_rtx)
3117 /* If it is being incremented, adjust the offset. Otherwise,
3118 this elimination can't be done. */
3119 rtx src = SET_SRC (x);
3121 if (GET_CODE (src) == PLUS
3122 && XEXP (src, 0) == SET_DEST (x)
3123 && CONST_INT_P (XEXP (src, 1)))
3124 ep->offset -= INTVAL (XEXP (src, 1));
3125 else
3126 ep->can_eliminate = 0;
3130 elimination_effects (SET_DEST (x), VOIDmode);
3131 elimination_effects (SET_SRC (x), VOIDmode);
3132 return;
3134 case MEM:
3135 /* Our only special processing is to pass the mode of the MEM to our
3136 recursive call. */
3137 elimination_effects (XEXP (x, 0), GET_MODE (x));
3138 return;
3140 default:
3141 break;
3144 fmt = GET_RTX_FORMAT (code);
3145 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3147 if (*fmt == 'e')
3148 elimination_effects (XEXP (x, i), mem_mode);
3149 else if (*fmt == 'E')
3150 for (j = 0; j < XVECLEN (x, i); j++)
3151 elimination_effects (XVECEXP (x, i, j), mem_mode);
3155 /* Descend through rtx X and verify that no references to eliminable registers
3156 remain. If any do remain, mark the involved register as not
3157 eliminable. */
3159 static void
3160 check_eliminable_occurrences (rtx x)
3162 const char *fmt;
3163 int i;
3164 enum rtx_code code;
3166 if (x == 0)
3167 return;
3169 code = GET_CODE (x);
3171 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3173 struct elim_table *ep;
3175 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3176 if (ep->from_rtx == x)
3177 ep->can_eliminate = 0;
3178 return;
3181 fmt = GET_RTX_FORMAT (code);
3182 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3184 if (*fmt == 'e')
3185 check_eliminable_occurrences (XEXP (x, i));
3186 else if (*fmt == 'E')
3188 int j;
3189 for (j = 0; j < XVECLEN (x, i); j++)
3190 check_eliminable_occurrences (XVECEXP (x, i, j));
3195 /* Scan INSN and eliminate all eliminable registers in it.
3197 If REPLACE is nonzero, do the replacement destructively. Also
3198 delete the insn as dead it if it is setting an eliminable register.
3200 If REPLACE is zero, do all our allocations in reload_obstack.
3202 If no eliminations were done and this insn doesn't require any elimination
3203 processing (these are not identical conditions: it might be updating sp,
3204 but not referencing fp; this needs to be seen during reload_as_needed so
3205 that the offset between fp and sp can be taken into consideration), zero
3206 is returned. Otherwise, 1 is returned. */
3208 static int
3209 eliminate_regs_in_insn (rtx insn, int replace)
3211 int icode = recog_memoized (insn);
3212 rtx old_body = PATTERN (insn);
3213 int insn_is_asm = asm_noperands (old_body) >= 0;
3214 rtx old_set = single_set (insn);
3215 rtx new_body;
3216 int val = 0;
3217 int i;
3218 rtx substed_operand[MAX_RECOG_OPERANDS];
3219 rtx orig_operand[MAX_RECOG_OPERANDS];
3220 struct elim_table *ep;
3221 rtx plus_src, plus_cst_src;
3223 if (! insn_is_asm && icode < 0)
3225 gcc_assert (DEBUG_INSN_P (insn)
3226 || GET_CODE (PATTERN (insn)) == USE
3227 || GET_CODE (PATTERN (insn)) == CLOBBER
3228 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3229 if (DEBUG_INSN_P (insn))
3230 INSN_VAR_LOCATION_LOC (insn)
3231 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn);
3232 return 0;
3235 if (old_set != 0 && REG_P (SET_DEST (old_set))
3236 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3238 /* Check for setting an eliminable register. */
3239 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3240 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3242 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
3243 /* If this is setting the frame pointer register to the
3244 hardware frame pointer register and this is an elimination
3245 that will be done (tested above), this insn is really
3246 adjusting the frame pointer downward to compensate for
3247 the adjustment done before a nonlocal goto. */
3248 if (ep->from == FRAME_POINTER_REGNUM
3249 && ep->to == HARD_FRAME_POINTER_REGNUM)
3251 rtx base = SET_SRC (old_set);
3252 rtx base_insn = insn;
3253 HOST_WIDE_INT offset = 0;
3255 while (base != ep->to_rtx)
3257 rtx prev_insn, prev_set;
3259 if (GET_CODE (base) == PLUS
3260 && CONST_INT_P (XEXP (base, 1)))
3262 offset += INTVAL (XEXP (base, 1));
3263 base = XEXP (base, 0);
3265 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3266 && (prev_set = single_set (prev_insn)) != 0
3267 && rtx_equal_p (SET_DEST (prev_set), base))
3269 base = SET_SRC (prev_set);
3270 base_insn = prev_insn;
3272 else
3273 break;
3276 if (base == ep->to_rtx)
3278 rtx src = plus_constant (Pmode, ep->to_rtx,
3279 offset - ep->offset);
3281 new_body = old_body;
3282 if (! replace)
3284 new_body = copy_insn (old_body);
3285 if (REG_NOTES (insn))
3286 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3288 PATTERN (insn) = new_body;
3289 old_set = single_set (insn);
3291 /* First see if this insn remains valid when we
3292 make the change. If not, keep the INSN_CODE
3293 the same and let reload fit it up. */
3294 validate_change (insn, &SET_SRC (old_set), src, 1);
3295 validate_change (insn, &SET_DEST (old_set),
3296 ep->to_rtx, 1);
3297 if (! apply_change_group ())
3299 SET_SRC (old_set) = src;
3300 SET_DEST (old_set) = ep->to_rtx;
3303 val = 1;
3304 goto done;
3307 #endif
3309 /* In this case this insn isn't serving a useful purpose. We
3310 will delete it in reload_as_needed once we know that this
3311 elimination is, in fact, being done.
3313 If REPLACE isn't set, we can't delete this insn, but needn't
3314 process it since it won't be used unless something changes. */
3315 if (replace)
3317 delete_dead_insn (insn);
3318 return 1;
3320 val = 1;
3321 goto done;
3325 /* We allow one special case which happens to work on all machines we
3326 currently support: a single set with the source or a REG_EQUAL
3327 note being a PLUS of an eliminable register and a constant. */
3328 plus_src = plus_cst_src = 0;
3329 if (old_set && REG_P (SET_DEST (old_set)))
3331 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3332 plus_src = SET_SRC (old_set);
3333 /* First see if the source is of the form (plus (...) CST). */
3334 if (plus_src
3335 && CONST_INT_P (XEXP (plus_src, 1)))
3336 plus_cst_src = plus_src;
3337 else if (REG_P (SET_SRC (old_set))
3338 || plus_src)
3340 /* Otherwise, see if we have a REG_EQUAL note of the form
3341 (plus (...) CST). */
3342 rtx links;
3343 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3345 if ((REG_NOTE_KIND (links) == REG_EQUAL
3346 || REG_NOTE_KIND (links) == REG_EQUIV)
3347 && GET_CODE (XEXP (links, 0)) == PLUS
3348 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3350 plus_cst_src = XEXP (links, 0);
3351 break;
3356 /* Check that the first operand of the PLUS is a hard reg or
3357 the lowpart subreg of one. */
3358 if (plus_cst_src)
3360 rtx reg = XEXP (plus_cst_src, 0);
3361 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3362 reg = SUBREG_REG (reg);
3364 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3365 plus_cst_src = 0;
3368 if (plus_cst_src)
3370 rtx reg = XEXP (plus_cst_src, 0);
3371 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3373 if (GET_CODE (reg) == SUBREG)
3374 reg = SUBREG_REG (reg);
3376 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3377 if (ep->from_rtx == reg && ep->can_eliminate)
3379 rtx to_rtx = ep->to_rtx;
3380 offset += ep->offset;
3381 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3383 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3384 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3385 to_rtx);
3386 /* If we have a nonzero offset, and the source is already
3387 a simple REG, the following transformation would
3388 increase the cost of the insn by replacing a simple REG
3389 with (plus (reg sp) CST). So try only when we already
3390 had a PLUS before. */
3391 if (offset == 0 || plus_src)
3393 rtx new_src = plus_constant (GET_MODE (to_rtx),
3394 to_rtx, offset);
3396 new_body = old_body;
3397 if (! replace)
3399 new_body = copy_insn (old_body);
3400 if (REG_NOTES (insn))
3401 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3403 PATTERN (insn) = new_body;
3404 old_set = single_set (insn);
3406 /* First see if this insn remains valid when we make the
3407 change. If not, try to replace the whole pattern with
3408 a simple set (this may help if the original insn was a
3409 PARALLEL that was only recognized as single_set due to
3410 REG_UNUSED notes). If this isn't valid either, keep
3411 the INSN_CODE the same and let reload fix it up. */
3412 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3414 rtx new_pat = gen_rtx_SET (VOIDmode,
3415 SET_DEST (old_set), new_src);
3417 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3418 SET_SRC (old_set) = new_src;
3421 else
3422 break;
3424 val = 1;
3425 /* This can't have an effect on elimination offsets, so skip right
3426 to the end. */
3427 goto done;
3431 /* Determine the effects of this insn on elimination offsets. */
3432 elimination_effects (old_body, VOIDmode);
3434 /* Eliminate all eliminable registers occurring in operands that
3435 can be handled by reload. */
3436 extract_insn (insn);
3437 for (i = 0; i < recog_data.n_operands; i++)
3439 orig_operand[i] = recog_data.operand[i];
3440 substed_operand[i] = recog_data.operand[i];
3442 /* For an asm statement, every operand is eliminable. */
3443 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3445 bool is_set_src, in_plus;
3447 /* Check for setting a register that we know about. */
3448 if (recog_data.operand_type[i] != OP_IN
3449 && REG_P (orig_operand[i]))
3451 /* If we are assigning to a register that can be eliminated, it
3452 must be as part of a PARALLEL, since the code above handles
3453 single SETs. We must indicate that we can no longer
3454 eliminate this reg. */
3455 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
3456 ep++)
3457 if (ep->from_rtx == orig_operand[i])
3458 ep->can_eliminate = 0;
3461 /* Companion to the above plus substitution, we can allow
3462 invariants as the source of a plain move. */
3463 is_set_src = false;
3464 if (old_set
3465 && recog_data.operand_loc[i] == &SET_SRC (old_set))
3466 is_set_src = true;
3467 in_plus = false;
3468 if (plus_src
3469 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3470 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3471 in_plus = true;
3473 substed_operand[i]
3474 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3475 replace ? insn : NULL_RTX,
3476 is_set_src || in_plus, false);
3477 if (substed_operand[i] != orig_operand[i])
3478 val = 1;
3479 /* Terminate the search in check_eliminable_occurrences at
3480 this point. */
3481 *recog_data.operand_loc[i] = 0;
3483 /* If an output operand changed from a REG to a MEM and INSN is an
3484 insn, write a CLOBBER insn. */
3485 if (recog_data.operand_type[i] != OP_IN
3486 && REG_P (orig_operand[i])
3487 && MEM_P (substed_operand[i])
3488 && replace)
3489 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3493 for (i = 0; i < recog_data.n_dups; i++)
3494 *recog_data.dup_loc[i]
3495 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3497 /* If any eliminable remain, they aren't eliminable anymore. */
3498 check_eliminable_occurrences (old_body);
3500 /* Substitute the operands; the new values are in the substed_operand
3501 array. */
3502 for (i = 0; i < recog_data.n_operands; i++)
3503 *recog_data.operand_loc[i] = substed_operand[i];
3504 for (i = 0; i < recog_data.n_dups; i++)
3505 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3507 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3508 re-recognize the insn. We do this in case we had a simple addition
3509 but now can do this as a load-address. This saves an insn in this
3510 common case.
3511 If re-recognition fails, the old insn code number will still be used,
3512 and some register operands may have changed into PLUS expressions.
3513 These will be handled by find_reloads by loading them into a register
3514 again. */
3516 if (val)
3518 /* If we aren't replacing things permanently and we changed something,
3519 make another copy to ensure that all the RTL is new. Otherwise
3520 things can go wrong if find_reload swaps commutative operands
3521 and one is inside RTL that has been copied while the other is not. */
3522 new_body = old_body;
3523 if (! replace)
3525 new_body = copy_insn (old_body);
3526 if (REG_NOTES (insn))
3527 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3529 PATTERN (insn) = new_body;
3531 /* If we had a move insn but now we don't, rerecognize it. This will
3532 cause spurious re-recognition if the old move had a PARALLEL since
3533 the new one still will, but we can't call single_set without
3534 having put NEW_BODY into the insn and the re-recognition won't
3535 hurt in this rare case. */
3536 /* ??? Why this huge if statement - why don't we just rerecognize the
3537 thing always? */
3538 if (! insn_is_asm
3539 && old_set != 0
3540 && ((REG_P (SET_SRC (old_set))
3541 && (GET_CODE (new_body) != SET
3542 || !REG_P (SET_SRC (new_body))))
3543 /* If this was a load from or store to memory, compare
3544 the MEM in recog_data.operand to the one in the insn.
3545 If they are not equal, then rerecognize the insn. */
3546 || (old_set != 0
3547 && ((MEM_P (SET_SRC (old_set))
3548 && SET_SRC (old_set) != recog_data.operand[1])
3549 || (MEM_P (SET_DEST (old_set))
3550 && SET_DEST (old_set) != recog_data.operand[0])))
3551 /* If this was an add insn before, rerecognize. */
3552 || GET_CODE (SET_SRC (old_set)) == PLUS))
3554 int new_icode = recog (PATTERN (insn), insn, 0);
3555 if (new_icode >= 0)
3556 INSN_CODE (insn) = new_icode;
3560 /* Restore the old body. If there were any changes to it, we made a copy
3561 of it while the changes were still in place, so we'll correctly return
3562 a modified insn below. */
3563 if (! replace)
3565 /* Restore the old body. */
3566 for (i = 0; i < recog_data.n_operands; i++)
3567 /* Restoring a top-level match_parallel would clobber the new_body
3568 we installed in the insn. */
3569 if (recog_data.operand_loc[i] != &PATTERN (insn))
3570 *recog_data.operand_loc[i] = orig_operand[i];
3571 for (i = 0; i < recog_data.n_dups; i++)
3572 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3575 /* Update all elimination pairs to reflect the status after the current
3576 insn. The changes we make were determined by the earlier call to
3577 elimination_effects.
3579 We also detect cases where register elimination cannot be done,
3580 namely, if a register would be both changed and referenced outside a MEM
3581 in the resulting insn since such an insn is often undefined and, even if
3582 not, we cannot know what meaning will be given to it. Note that it is
3583 valid to have a register used in an address in an insn that changes it
3584 (presumably with a pre- or post-increment or decrement).
3586 If anything changes, return nonzero. */
3588 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3590 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3591 ep->can_eliminate = 0;
3593 ep->ref_outside_mem = 0;
3595 if (ep->previous_offset != ep->offset)
3596 val = 1;
3599 done:
3600 /* If we changed something, perform elimination in REG_NOTES. This is
3601 needed even when REPLACE is zero because a REG_DEAD note might refer
3602 to a register that we eliminate and could cause a different number
3603 of spill registers to be needed in the final reload pass than in
3604 the pre-passes. */
3605 if (val && REG_NOTES (insn) != 0)
3606 REG_NOTES (insn)
3607 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true,
3608 false);
3610 return val;
3613 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the
3614 register allocator. INSN is the instruction we need to examine, we perform
3615 eliminations in its operands and record cases where eliminating a reg with
3616 an invariant equivalence would add extra cost. */
3618 static void
3619 elimination_costs_in_insn (rtx insn)
3621 int icode = recog_memoized (insn);
3622 rtx old_body = PATTERN (insn);
3623 int insn_is_asm = asm_noperands (old_body) >= 0;
3624 rtx old_set = single_set (insn);
3625 int i;
3626 rtx orig_operand[MAX_RECOG_OPERANDS];
3627 rtx orig_dup[MAX_RECOG_OPERANDS];
3628 struct elim_table *ep;
3629 rtx plus_src, plus_cst_src;
3630 bool sets_reg_p;
3632 if (! insn_is_asm && icode < 0)
3634 gcc_assert (DEBUG_INSN_P (insn)
3635 || GET_CODE (PATTERN (insn)) == USE
3636 || GET_CODE (PATTERN (insn)) == CLOBBER
3637 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3638 return;
3641 if (old_set != 0 && REG_P (SET_DEST (old_set))
3642 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3644 /* Check for setting an eliminable register. */
3645 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3646 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3647 return;
3650 /* We allow one special case which happens to work on all machines we
3651 currently support: a single set with the source or a REG_EQUAL
3652 note being a PLUS of an eliminable register and a constant. */
3653 plus_src = plus_cst_src = 0;
3654 sets_reg_p = false;
3655 if (old_set && REG_P (SET_DEST (old_set)))
3657 sets_reg_p = true;
3658 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3659 plus_src = SET_SRC (old_set);
3660 /* First see if the source is of the form (plus (...) CST). */
3661 if (plus_src
3662 && CONST_INT_P (XEXP (plus_src, 1)))
3663 plus_cst_src = plus_src;
3664 else if (REG_P (SET_SRC (old_set))
3665 || plus_src)
3667 /* Otherwise, see if we have a REG_EQUAL note of the form
3668 (plus (...) CST). */
3669 rtx links;
3670 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3672 if ((REG_NOTE_KIND (links) == REG_EQUAL
3673 || REG_NOTE_KIND (links) == REG_EQUIV)
3674 && GET_CODE (XEXP (links, 0)) == PLUS
3675 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3677 plus_cst_src = XEXP (links, 0);
3678 break;
3684 /* Determine the effects of this insn on elimination offsets. */
3685 elimination_effects (old_body, VOIDmode);
3687 /* Eliminate all eliminable registers occurring in operands that
3688 can be handled by reload. */
3689 extract_insn (insn);
3690 for (i = 0; i < recog_data.n_dups; i++)
3691 orig_dup[i] = *recog_data.dup_loc[i];
3693 for (i = 0; i < recog_data.n_operands; i++)
3695 orig_operand[i] = recog_data.operand[i];
3697 /* For an asm statement, every operand is eliminable. */
3698 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3700 bool is_set_src, in_plus;
3702 /* Check for setting a register that we know about. */
3703 if (recog_data.operand_type[i] != OP_IN
3704 && REG_P (orig_operand[i]))
3706 /* If we are assigning to a register that can be eliminated, it
3707 must be as part of a PARALLEL, since the code above handles
3708 single SETs. We must indicate that we can no longer
3709 eliminate this reg. */
3710 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS];
3711 ep++)
3712 if (ep->from_rtx == orig_operand[i])
3713 ep->can_eliminate = 0;
3716 /* Companion to the above plus substitution, we can allow
3717 invariants as the source of a plain move. */
3718 is_set_src = false;
3719 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3720 is_set_src = true;
3721 if (is_set_src && !sets_reg_p)
3722 note_reg_elim_costly (&SET_SRC (old_set), insn);
3723 in_plus = false;
3724 if (plus_src && sets_reg_p
3725 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3726 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3727 in_plus = true;
3729 eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3730 NULL_RTX,
3731 is_set_src || in_plus, true);
3732 /* Terminate the search in check_eliminable_occurrences at
3733 this point. */
3734 *recog_data.operand_loc[i] = 0;
3738 for (i = 0; i < recog_data.n_dups; i++)
3739 *recog_data.dup_loc[i]
3740 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3742 /* If any eliminable remain, they aren't eliminable anymore. */
3743 check_eliminable_occurrences (old_body);
3745 /* Restore the old body. */
3746 for (i = 0; i < recog_data.n_operands; i++)
3747 *recog_data.operand_loc[i] = orig_operand[i];
3748 for (i = 0; i < recog_data.n_dups; i++)
3749 *recog_data.dup_loc[i] = orig_dup[i];
3751 /* Update all elimination pairs to reflect the status after the current
3752 insn. The changes we make were determined by the earlier call to
3753 elimination_effects. */
3755 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3757 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3758 ep->can_eliminate = 0;
3760 ep->ref_outside_mem = 0;
3763 return;
3766 /* Loop through all elimination pairs.
3767 Recalculate the number not at initial offset.
3769 Compute the maximum offset (minimum offset if the stack does not
3770 grow downward) for each elimination pair. */
3772 static void
3773 update_eliminable_offsets (void)
3775 struct elim_table *ep;
3777 num_not_at_initial_offset = 0;
3778 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3780 ep->previous_offset = ep->offset;
3781 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3782 num_not_at_initial_offset++;
3786 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3787 replacement we currently believe is valid, mark it as not eliminable if X
3788 modifies DEST in any way other than by adding a constant integer to it.
3790 If DEST is the frame pointer, we do nothing because we assume that
3791 all assignments to the hard frame pointer are nonlocal gotos and are being
3792 done at a time when they are valid and do not disturb anything else.
3793 Some machines want to eliminate a fake argument pointer with either the
3794 frame or stack pointer. Assignments to the hard frame pointer must not
3795 prevent this elimination.
3797 Called via note_stores from reload before starting its passes to scan
3798 the insns of the function. */
3800 static void
3801 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3803 unsigned int i;
3805 /* A SUBREG of a hard register here is just changing its mode. We should
3806 not see a SUBREG of an eliminable hard register, but check just in
3807 case. */
3808 if (GET_CODE (dest) == SUBREG)
3809 dest = SUBREG_REG (dest);
3811 if (dest == hard_frame_pointer_rtx)
3812 return;
3814 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3815 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3816 && (GET_CODE (x) != SET
3817 || GET_CODE (SET_SRC (x)) != PLUS
3818 || XEXP (SET_SRC (x), 0) != dest
3819 || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3821 reg_eliminate[i].can_eliminate_previous
3822 = reg_eliminate[i].can_eliminate = 0;
3823 num_eliminable--;
3827 /* Verify that the initial elimination offsets did not change since the
3828 last call to set_initial_elim_offsets. This is used to catch cases
3829 where something illegal happened during reload_as_needed that could
3830 cause incorrect code to be generated if we did not check for it. */
3832 static bool
3833 verify_initial_elim_offsets (void)
3835 HOST_WIDE_INT t;
3837 if (!num_eliminable)
3838 return true;
3840 #ifdef ELIMINABLE_REGS
3842 struct elim_table *ep;
3844 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3846 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3847 if (t != ep->initial_offset)
3848 return false;
3851 #else
3852 INITIAL_FRAME_POINTER_OFFSET (t);
3853 if (t != reg_eliminate[0].initial_offset)
3854 return false;
3855 #endif
3857 return true;
3860 /* Reset all offsets on eliminable registers to their initial values. */
3862 static void
3863 set_initial_elim_offsets (void)
3865 struct elim_table *ep = reg_eliminate;
3867 #ifdef ELIMINABLE_REGS
3868 for (; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3870 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3871 ep->previous_offset = ep->offset = ep->initial_offset;
3873 #else
3874 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3875 ep->previous_offset = ep->offset = ep->initial_offset;
3876 #endif
3878 num_not_at_initial_offset = 0;
3881 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3883 static void
3884 set_initial_eh_label_offset (rtx label)
3886 set_label_offsets (label, NULL_RTX, 1);
3889 /* Initialize the known label offsets.
3890 Set a known offset for each forced label to be at the initial offset
3891 of each elimination. We do this because we assume that all
3892 computed jumps occur from a location where each elimination is
3893 at its initial offset.
3894 For all other labels, show that we don't know the offsets. */
3896 static void
3897 set_initial_label_offsets (void)
3899 rtx x;
3900 memset (offsets_known_at, 0, num_labels);
3902 for (x = forced_labels; x; x = XEXP (x, 1))
3903 if (XEXP (x, 0))
3904 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3906 for (x = nonlocal_goto_handler_labels; x; x = XEXP (x, 1))
3907 if (XEXP (x, 0))
3908 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3910 for_each_eh_label (set_initial_eh_label_offset);
3913 /* Set all elimination offsets to the known values for the code label given
3914 by INSN. */
3916 static void
3917 set_offsets_for_label (rtx insn)
3919 unsigned int i;
3920 int label_nr = CODE_LABEL_NUMBER (insn);
3921 struct elim_table *ep;
3923 num_not_at_initial_offset = 0;
3924 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3926 ep->offset = ep->previous_offset
3927 = offsets_at[label_nr - first_label_num][i];
3928 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3929 num_not_at_initial_offset++;
3933 /* See if anything that happened changes which eliminations are valid.
3934 For example, on the SPARC, whether or not the frame pointer can
3935 be eliminated can depend on what registers have been used. We need
3936 not check some conditions again (such as flag_omit_frame_pointer)
3937 since they can't have changed. */
3939 static void
3940 update_eliminables (HARD_REG_SET *pset)
3942 int previous_frame_pointer_needed = frame_pointer_needed;
3943 struct elim_table *ep;
3945 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3946 if ((ep->from == HARD_FRAME_POINTER_REGNUM
3947 && targetm.frame_pointer_required ())
3948 #ifdef ELIMINABLE_REGS
3949 || ! targetm.can_eliminate (ep->from, ep->to)
3950 #endif
3952 ep->can_eliminate = 0;
3954 /* Look for the case where we have discovered that we can't replace
3955 register A with register B and that means that we will now be
3956 trying to replace register A with register C. This means we can
3957 no longer replace register C with register B and we need to disable
3958 such an elimination, if it exists. This occurs often with A == ap,
3959 B == sp, and C == fp. */
3961 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3963 struct elim_table *op;
3964 int new_to = -1;
3966 if (! ep->can_eliminate && ep->can_eliminate_previous)
3968 /* Find the current elimination for ep->from, if there is a
3969 new one. */
3970 for (op = reg_eliminate;
3971 op < &reg_eliminate[NUM_ELIMINABLE_REGS]; op++)
3972 if (op->from == ep->from && op->can_eliminate)
3974 new_to = op->to;
3975 break;
3978 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3979 disable it. */
3980 for (op = reg_eliminate;
3981 op < &reg_eliminate[NUM_ELIMINABLE_REGS]; op++)
3982 if (op->from == new_to && op->to == ep->to)
3983 op->can_eliminate = 0;
3987 /* See if any registers that we thought we could eliminate the previous
3988 time are no longer eliminable. If so, something has changed and we
3989 must spill the register. Also, recompute the number of eliminable
3990 registers and see if the frame pointer is needed; it is if there is
3991 no elimination of the frame pointer that we can perform. */
3993 frame_pointer_needed = 1;
3994 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3996 if (ep->can_eliminate
3997 && ep->from == FRAME_POINTER_REGNUM
3998 && ep->to != HARD_FRAME_POINTER_REGNUM
3999 && (! SUPPORTS_STACK_ALIGNMENT
4000 || ! crtl->stack_realign_needed))
4001 frame_pointer_needed = 0;
4003 if (! ep->can_eliminate && ep->can_eliminate_previous)
4005 ep->can_eliminate_previous = 0;
4006 SET_HARD_REG_BIT (*pset, ep->from);
4007 num_eliminable--;
4011 /* If we didn't need a frame pointer last time, but we do now, spill
4012 the hard frame pointer. */
4013 if (frame_pointer_needed && ! previous_frame_pointer_needed)
4014 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
4017 /* Call update_eliminables an spill any registers we can't eliminate anymore.
4018 Return true iff a register was spilled. */
4020 static bool
4021 update_eliminables_and_spill (void)
4023 int i;
4024 bool did_spill = false;
4025 HARD_REG_SET to_spill;
4026 CLEAR_HARD_REG_SET (to_spill);
4027 update_eliminables (&to_spill);
4028 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
4030 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4031 if (TEST_HARD_REG_BIT (to_spill, i))
4033 spill_hard_reg (i, 1);
4034 did_spill = true;
4036 /* Regardless of the state of spills, if we previously had
4037 a register that we thought we could eliminate, but now can
4038 not eliminate, we must run another pass.
4040 Consider pseudos which have an entry in reg_equiv_* which
4041 reference an eliminable register. We must make another pass
4042 to update reg_equiv_* so that we do not substitute in the
4043 old value from when we thought the elimination could be
4044 performed. */
4046 return did_spill;
4049 /* Return true if X is used as the target register of an elimination. */
4051 bool
4052 elimination_target_reg_p (rtx x)
4054 struct elim_table *ep;
4056 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4057 if (ep->to_rtx == x && ep->can_eliminate)
4058 return true;
4060 return false;
4063 /* Initialize the table of registers to eliminate.
4064 Pre-condition: global flag frame_pointer_needed has been set before
4065 calling this function. */
4067 static void
4068 init_elim_table (void)
4070 struct elim_table *ep;
4071 #ifdef ELIMINABLE_REGS
4072 const struct elim_table_1 *ep1;
4073 #endif
4075 if (!reg_eliminate)
4076 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
4078 num_eliminable = 0;
4080 #ifdef ELIMINABLE_REGS
4081 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
4082 ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
4084 ep->from = ep1->from;
4085 ep->to = ep1->to;
4086 ep->can_eliminate = ep->can_eliminate_previous
4087 = (targetm.can_eliminate (ep->from, ep->to)
4088 && ! (ep->to == STACK_POINTER_REGNUM
4089 && frame_pointer_needed
4090 && (! SUPPORTS_STACK_ALIGNMENT
4091 || ! stack_realign_fp)));
4093 #else
4094 reg_eliminate[0].from = reg_eliminate_1[0].from;
4095 reg_eliminate[0].to = reg_eliminate_1[0].to;
4096 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
4097 = ! frame_pointer_needed;
4098 #endif
4100 /* Count the number of eliminable registers and build the FROM and TO
4101 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
4102 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
4103 We depend on this. */
4104 for (ep = reg_eliminate; ep < &reg_eliminate[NUM_ELIMINABLE_REGS]; ep++)
4106 num_eliminable += ep->can_eliminate;
4107 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
4108 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
4112 /* Find all the pseudo registers that didn't get hard regs
4113 but do have known equivalent constants or memory slots.
4114 These include parameters (known equivalent to parameter slots)
4115 and cse'd or loop-moved constant memory addresses.
4117 Record constant equivalents in reg_equiv_constant
4118 so they will be substituted by find_reloads.
4119 Record memory equivalents in reg_mem_equiv so they can
4120 be substituted eventually by altering the REG-rtx's. */
4122 static void
4123 init_eliminable_invariants (rtx first, bool do_subregs)
4125 int i;
4126 rtx insn;
4128 grow_reg_equivs ();
4129 if (do_subregs)
4130 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
4131 else
4132 reg_max_ref_width = NULL;
4134 num_eliminable_invariants = 0;
4136 first_label_num = get_first_label_num ();
4137 num_labels = max_label_num () - first_label_num;
4139 /* Allocate the tables used to store offset information at labels. */
4140 offsets_known_at = XNEWVEC (char, num_labels);
4141 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
4143 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
4144 to. If DO_SUBREGS is true, also find all paradoxical subregs and
4145 find largest such for each pseudo. FIRST is the head of the insn
4146 list. */
4148 for (insn = first; insn; insn = NEXT_INSN (insn))
4150 rtx set = single_set (insn);
4152 /* We may introduce USEs that we want to remove at the end, so
4153 we'll mark them with QImode. Make sure there are no
4154 previously-marked insns left by say regmove. */
4155 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
4156 && GET_MODE (insn) != VOIDmode)
4157 PUT_MODE (insn, VOIDmode);
4159 if (do_subregs && NONDEBUG_INSN_P (insn))
4160 scan_paradoxical_subregs (PATTERN (insn));
4162 if (set != 0 && REG_P (SET_DEST (set)))
4164 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
4165 rtx x;
4167 if (! note)
4168 continue;
4170 i = REGNO (SET_DEST (set));
4171 x = XEXP (note, 0);
4173 if (i <= LAST_VIRTUAL_REGISTER)
4174 continue;
4176 /* If flag_pic and we have constant, verify it's legitimate. */
4177 if (!CONSTANT_P (x)
4178 || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x))
4180 /* It can happen that a REG_EQUIV note contains a MEM
4181 that is not a legitimate memory operand. As later
4182 stages of reload assume that all addresses found
4183 in the reg_equiv_* arrays were originally legitimate,
4184 we ignore such REG_EQUIV notes. */
4185 if (memory_operand (x, VOIDmode))
4187 /* Always unshare the equivalence, so we can
4188 substitute into this insn without touching the
4189 equivalence. */
4190 reg_equiv_memory_loc (i) = copy_rtx (x);
4192 else if (function_invariant_p (x))
4194 enum machine_mode mode;
4196 mode = GET_MODE (SET_DEST (set));
4197 if (GET_CODE (x) == PLUS)
4199 /* This is PLUS of frame pointer and a constant,
4200 and might be shared. Unshare it. */
4201 reg_equiv_invariant (i) = copy_rtx (x);
4202 num_eliminable_invariants++;
4204 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4206 reg_equiv_invariant (i) = x;
4207 num_eliminable_invariants++;
4209 else if (targetm.legitimate_constant_p (mode, x))
4210 reg_equiv_constant (i) = x;
4211 else
4213 reg_equiv_memory_loc (i) = force_const_mem (mode, x);
4214 if (! reg_equiv_memory_loc (i))
4215 reg_equiv_init (i) = NULL_RTX;
4218 else
4220 reg_equiv_init (i) = NULL_RTX;
4221 continue;
4224 else
4225 reg_equiv_init (i) = NULL_RTX;
4229 if (dump_file)
4230 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4231 if (reg_equiv_init (i))
4233 fprintf (dump_file, "init_insns for %u: ", i);
4234 print_inline_rtx (dump_file, reg_equiv_init (i), 20);
4235 fprintf (dump_file, "\n");
4239 /* Indicate that we no longer have known memory locations or constants.
4240 Free all data involved in tracking these. */
4242 static void
4243 free_reg_equiv (void)
4245 int i;
4247 free (offsets_known_at);
4248 free (offsets_at);
4249 offsets_at = 0;
4250 offsets_known_at = 0;
4252 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4253 if (reg_equiv_alt_mem_list (i))
4254 free_EXPR_LIST_list (&reg_equiv_alt_mem_list (i));
4255 vec_free (reg_equivs);
4258 /* Kick all pseudos out of hard register REGNO.
4260 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
4261 because we found we can't eliminate some register. In the case, no pseudos
4262 are allowed to be in the register, even if they are only in a block that
4263 doesn't require spill registers, unlike the case when we are spilling this
4264 hard reg to produce another spill register.
4266 Return nonzero if any pseudos needed to be kicked out. */
4268 static void
4269 spill_hard_reg (unsigned int regno, int cant_eliminate)
4271 int i;
4273 if (cant_eliminate)
4275 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
4276 df_set_regs_ever_live (regno, true);
4279 /* Spill every pseudo reg that was allocated to this reg
4280 or to something that overlaps this reg. */
4282 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
4283 if (reg_renumber[i] >= 0
4284 && (unsigned int) reg_renumber[i] <= regno
4285 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
4286 SET_REGNO_REG_SET (&spilled_pseudos, i);
4289 /* After find_reload_regs has been run for all insn that need reloads,
4290 and/or spill_hard_regs was called, this function is used to actually
4291 spill pseudo registers and try to reallocate them. It also sets up the
4292 spill_regs array for use by choose_reload_regs. */
4294 static int
4295 finish_spills (int global)
4297 struct insn_chain *chain;
4298 int something_changed = 0;
4299 unsigned i;
4300 reg_set_iterator rsi;
4302 /* Build the spill_regs array for the function. */
4303 /* If there are some registers still to eliminate and one of the spill regs
4304 wasn't ever used before, additional stack space may have to be
4305 allocated to store this register. Thus, we may have changed the offset
4306 between the stack and frame pointers, so mark that something has changed.
4308 One might think that we need only set VAL to 1 if this is a call-used
4309 register. However, the set of registers that must be saved by the
4310 prologue is not identical to the call-used set. For example, the
4311 register used by the call insn for the return PC is a call-used register,
4312 but must be saved by the prologue. */
4314 n_spills = 0;
4315 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4316 if (TEST_HARD_REG_BIT (used_spill_regs, i))
4318 spill_reg_order[i] = n_spills;
4319 spill_regs[n_spills++] = i;
4320 if (num_eliminable && ! df_regs_ever_live_p (i))
4321 something_changed = 1;
4322 df_set_regs_ever_live (i, true);
4324 else
4325 spill_reg_order[i] = -1;
4327 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
4328 if (! ira_conflicts_p || reg_renumber[i] >= 0)
4330 /* Record the current hard register the pseudo is allocated to
4331 in pseudo_previous_regs so we avoid reallocating it to the
4332 same hard reg in a later pass. */
4333 gcc_assert (reg_renumber[i] >= 0);
4335 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
4336 /* Mark it as no longer having a hard register home. */
4337 reg_renumber[i] = -1;
4338 if (ira_conflicts_p)
4339 /* Inform IRA about the change. */
4340 ira_mark_allocation_change (i);
4341 /* We will need to scan everything again. */
4342 something_changed = 1;
4345 /* Retry global register allocation if possible. */
4346 if (global && ira_conflicts_p)
4348 unsigned int n;
4350 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
4351 /* For every insn that needs reloads, set the registers used as spill
4352 regs in pseudo_forbidden_regs for every pseudo live across the
4353 insn. */
4354 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
4356 EXECUTE_IF_SET_IN_REG_SET
4357 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
4359 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4360 chain->used_spill_regs);
4362 EXECUTE_IF_SET_IN_REG_SET
4363 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
4365 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
4366 chain->used_spill_regs);
4370 /* Retry allocating the pseudos spilled in IRA and the
4371 reload. For each reg, merge the various reg sets that
4372 indicate which hard regs can't be used, and call
4373 ira_reassign_pseudos. */
4374 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4375 if (reg_old_renumber[i] != reg_renumber[i])
4377 if (reg_renumber[i] < 0)
4378 temp_pseudo_reg_arr[n++] = i;
4379 else
4380 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4382 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4383 bad_spill_regs_global,
4384 pseudo_forbidden_regs, pseudo_previous_regs,
4385 &spilled_pseudos))
4386 something_changed = 1;
4388 /* Fix up the register information in the insn chain.
4389 This involves deleting those of the spilled pseudos which did not get
4390 a new hard register home from the live_{before,after} sets. */
4391 for (chain = reload_insn_chain; chain; chain = chain->next)
4393 HARD_REG_SET used_by_pseudos;
4394 HARD_REG_SET used_by_pseudos2;
4396 if (! ira_conflicts_p)
4398 /* Don't do it for IRA because IRA and the reload still can
4399 assign hard registers to the spilled pseudos on next
4400 reload iterations. */
4401 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4402 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4404 /* Mark any unallocated hard regs as available for spills. That
4405 makes inheritance work somewhat better. */
4406 if (chain->need_reload)
4408 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4409 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4410 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4412 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4413 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4414 /* Value of chain->used_spill_regs from previous iteration
4415 may be not included in the value calculated here because
4416 of possible removing caller-saves insns (see function
4417 delete_caller_save_insns. */
4418 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4419 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4423 CLEAR_REG_SET (&changed_allocation_pseudos);
4424 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4425 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4427 int regno = reg_renumber[i];
4428 if (reg_old_renumber[i] == regno)
4429 continue;
4431 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4433 alter_reg (i, reg_old_renumber[i], false);
4434 reg_old_renumber[i] = regno;
4435 if (dump_file)
4437 if (regno == -1)
4438 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4439 else
4440 fprintf (dump_file, " Register %d now in %d.\n\n",
4441 i, reg_renumber[i]);
4445 return something_changed;
4448 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4450 static void
4451 scan_paradoxical_subregs (rtx x)
4453 int i;
4454 const char *fmt;
4455 enum rtx_code code = GET_CODE (x);
4457 switch (code)
4459 case REG:
4460 case CONST:
4461 case SYMBOL_REF:
4462 case LABEL_REF:
4463 CASE_CONST_ANY:
4464 case CC0:
4465 case PC:
4466 case USE:
4467 case CLOBBER:
4468 return;
4470 case SUBREG:
4471 if (REG_P (SUBREG_REG (x))
4472 && (GET_MODE_SIZE (GET_MODE (x))
4473 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4475 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4476 = GET_MODE_SIZE (GET_MODE (x));
4477 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4479 return;
4481 default:
4482 break;
4485 fmt = GET_RTX_FORMAT (code);
4486 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4488 if (fmt[i] == 'e')
4489 scan_paradoxical_subregs (XEXP (x, i));
4490 else if (fmt[i] == 'E')
4492 int j;
4493 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4494 scan_paradoxical_subregs (XVECEXP (x, i, j));
4499 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload.
4500 If *OP_PTR is a paradoxical subreg, try to remove that subreg
4501 and apply the corresponding narrowing subreg to *OTHER_PTR.
4502 Return true if the operands were changed, false otherwise. */
4504 static bool
4505 strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
4507 rtx op, inner, other, tem;
4509 op = *op_ptr;
4510 if (!paradoxical_subreg_p (op))
4511 return false;
4512 inner = SUBREG_REG (op);
4514 other = *other_ptr;
4515 tem = gen_lowpart_common (GET_MODE (inner), other);
4516 if (!tem)
4517 return false;
4519 /* If the lowpart operation turned a hard register into a subreg,
4520 rather than simplifying it to another hard register, then the
4521 mode change cannot be properly represented. For example, OTHER
4522 might be valid in its current mode, but not in the new one. */
4523 if (GET_CODE (tem) == SUBREG
4524 && REG_P (other)
4525 && HARD_REGISTER_P (other))
4526 return false;
4528 *op_ptr = inner;
4529 *other_ptr = tem;
4530 return true;
4533 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4534 examine all of the reload insns between PREV and NEXT exclusive, and
4535 annotate all that may trap. */
4537 static void
4538 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4540 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4541 if (note == NULL)
4542 return;
4543 if (!insn_could_throw_p (insn))
4544 remove_note (insn, note);
4545 copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4548 /* Reload pseudo-registers into hard regs around each insn as needed.
4549 Additional register load insns are output before the insn that needs it
4550 and perhaps store insns after insns that modify the reloaded pseudo reg.
4552 reg_last_reload_reg and reg_reloaded_contents keep track of
4553 which registers are already available in reload registers.
4554 We update these for the reloads that we perform,
4555 as the insns are scanned. */
4557 static void
4558 reload_as_needed (int live_known)
4560 struct insn_chain *chain;
4561 #if defined (AUTO_INC_DEC)
4562 int i;
4563 #endif
4564 rtx x, marker;
4566 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4567 memset (spill_reg_store, 0, sizeof spill_reg_store);
4568 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4569 INIT_REG_SET (&reg_has_output_reload);
4570 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4571 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4573 set_initial_elim_offsets ();
4575 /* Generate a marker insn that we will move around. */
4576 marker = emit_note (NOTE_INSN_DELETED);
4577 unlink_insn_chain (marker, marker);
4579 for (chain = reload_insn_chain; chain; chain = chain->next)
4581 rtx prev = 0;
4582 rtx insn = chain->insn;
4583 rtx old_next = NEXT_INSN (insn);
4584 #ifdef AUTO_INC_DEC
4585 rtx old_prev = PREV_INSN (insn);
4586 #endif
4588 /* If we pass a label, copy the offsets from the label information
4589 into the current offsets of each elimination. */
4590 if (LABEL_P (insn))
4591 set_offsets_for_label (insn);
4593 else if (INSN_P (insn))
4595 regset_head regs_to_forget;
4596 INIT_REG_SET (&regs_to_forget);
4597 note_stores (PATTERN (insn), forget_old_reloads_1, &regs_to_forget);
4599 /* If this is a USE and CLOBBER of a MEM, ensure that any
4600 references to eliminable registers have been removed. */
4602 if ((GET_CODE (PATTERN (insn)) == USE
4603 || GET_CODE (PATTERN (insn)) == CLOBBER)
4604 && MEM_P (XEXP (PATTERN (insn), 0)))
4605 XEXP (XEXP (PATTERN (insn), 0), 0)
4606 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4607 GET_MODE (XEXP (PATTERN (insn), 0)),
4608 NULL_RTX);
4610 /* If we need to do register elimination processing, do so.
4611 This might delete the insn, in which case we are done. */
4612 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4614 eliminate_regs_in_insn (insn, 1);
4615 if (NOTE_P (insn))
4617 update_eliminable_offsets ();
4618 CLEAR_REG_SET (&regs_to_forget);
4619 continue;
4623 /* If need_elim is nonzero but need_reload is zero, one might think
4624 that we could simply set n_reloads to 0. However, find_reloads
4625 could have done some manipulation of the insn (such as swapping
4626 commutative operands), and these manipulations are lost during
4627 the first pass for every insn that needs register elimination.
4628 So the actions of find_reloads must be redone here. */
4630 if (! chain->need_elim && ! chain->need_reload
4631 && ! chain->need_operand_change)
4632 n_reloads = 0;
4633 /* First find the pseudo regs that must be reloaded for this insn.
4634 This info is returned in the tables reload_... (see reload.h).
4635 Also modify the body of INSN by substituting RELOAD
4636 rtx's for those pseudo regs. */
4637 else
4639 CLEAR_REG_SET (&reg_has_output_reload);
4640 CLEAR_HARD_REG_SET (reg_is_output_reload);
4642 find_reloads (insn, 1, spill_indirect_levels, live_known,
4643 spill_reg_order);
4646 if (n_reloads > 0)
4648 rtx next = NEXT_INSN (insn);
4649 rtx p;
4651 /* ??? PREV can get deleted by reload inheritance.
4652 Work around this by emitting a marker note. */
4653 prev = PREV_INSN (insn);
4654 reorder_insns_nobb (marker, marker, prev);
4656 /* Now compute which reload regs to reload them into. Perhaps
4657 reusing reload regs from previous insns, or else output
4658 load insns to reload them. Maybe output store insns too.
4659 Record the choices of reload reg in reload_reg_rtx. */
4660 choose_reload_regs (chain);
4662 /* Generate the insns to reload operands into or out of
4663 their reload regs. */
4664 emit_reload_insns (chain);
4666 /* Substitute the chosen reload regs from reload_reg_rtx
4667 into the insn's body (or perhaps into the bodies of other
4668 load and store insn that we just made for reloading
4669 and that we moved the structure into). */
4670 subst_reloads (insn);
4672 prev = PREV_INSN (marker);
4673 unlink_insn_chain (marker, marker);
4675 /* Adjust the exception region notes for loads and stores. */
4676 if (cfun->can_throw_non_call_exceptions && !CALL_P (insn))
4677 fixup_eh_region_note (insn, prev, next);
4679 /* Adjust the location of REG_ARGS_SIZE. */
4680 p = find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX);
4681 if (p)
4683 remove_note (insn, p);
4684 fixup_args_size_notes (prev, PREV_INSN (next),
4685 INTVAL (XEXP (p, 0)));
4688 /* If this was an ASM, make sure that all the reload insns
4689 we have generated are valid. If not, give an error
4690 and delete them. */
4691 if (asm_noperands (PATTERN (insn)) >= 0)
4692 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4693 if (p != insn && INSN_P (p)
4694 && GET_CODE (PATTERN (p)) != USE
4695 && (recog_memoized (p) < 0
4696 || (extract_insn (p), ! constrain_operands (1))))
4698 error_for_asm (insn,
4699 "%<asm%> operand requires "
4700 "impossible reload");
4701 delete_insn (p);
4705 if (num_eliminable && chain->need_elim)
4706 update_eliminable_offsets ();
4708 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4709 is no longer validly lying around to save a future reload.
4710 Note that this does not detect pseudos that were reloaded
4711 for this insn in order to be stored in
4712 (obeying register constraints). That is correct; such reload
4713 registers ARE still valid. */
4714 forget_marked_reloads (&regs_to_forget);
4715 CLEAR_REG_SET (&regs_to_forget);
4717 /* There may have been CLOBBER insns placed after INSN. So scan
4718 between INSN and NEXT and use them to forget old reloads. */
4719 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4720 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4721 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4723 #ifdef AUTO_INC_DEC
4724 /* Likewise for regs altered by auto-increment in this insn.
4725 REG_INC notes have been changed by reloading:
4726 find_reloads_address_1 records substitutions for them,
4727 which have been performed by subst_reloads above. */
4728 for (i = n_reloads - 1; i >= 0; i--)
4730 rtx in_reg = rld[i].in_reg;
4731 if (in_reg)
4733 enum rtx_code code = GET_CODE (in_reg);
4734 /* PRE_INC / PRE_DEC will have the reload register ending up
4735 with the same value as the stack slot, but that doesn't
4736 hold true for POST_INC / POST_DEC. Either we have to
4737 convert the memory access to a true POST_INC / POST_DEC,
4738 or we can't use the reload register for inheritance. */
4739 if ((code == POST_INC || code == POST_DEC)
4740 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4741 REGNO (rld[i].reg_rtx))
4742 /* Make sure it is the inc/dec pseudo, and not
4743 some other (e.g. output operand) pseudo. */
4744 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4745 == REGNO (XEXP (in_reg, 0))))
4748 rtx reload_reg = rld[i].reg_rtx;
4749 enum machine_mode mode = GET_MODE (reload_reg);
4750 int n = 0;
4751 rtx p;
4753 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4755 /* We really want to ignore REG_INC notes here, so
4756 use PATTERN (p) as argument to reg_set_p . */
4757 if (reg_set_p (reload_reg, PATTERN (p)))
4758 break;
4759 n = count_occurrences (PATTERN (p), reload_reg, 0);
4760 if (! n)
4761 continue;
4762 if (n == 1)
4764 rtx replace_reg
4765 = gen_rtx_fmt_e (code, mode, reload_reg);
4767 validate_replace_rtx_group (reload_reg,
4768 replace_reg, p);
4769 n = verify_changes (0);
4771 /* We must also verify that the constraints
4772 are met after the replacement. Make sure
4773 extract_insn is only called for an insn
4774 where the replacements were found to be
4775 valid so far. */
4776 if (n)
4778 extract_insn (p);
4779 n = constrain_operands (1);
4782 /* If the constraints were not met, then
4783 undo the replacement, else confirm it. */
4784 if (!n)
4785 cancel_changes (0);
4786 else
4787 confirm_change_group ();
4789 break;
4791 if (n == 1)
4793 add_reg_note (p, REG_INC, reload_reg);
4794 /* Mark this as having an output reload so that the
4795 REG_INC processing code below won't invalidate
4796 the reload for inheritance. */
4797 SET_HARD_REG_BIT (reg_is_output_reload,
4798 REGNO (reload_reg));
4799 SET_REGNO_REG_SET (&reg_has_output_reload,
4800 REGNO (XEXP (in_reg, 0)));
4802 else
4803 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4804 NULL);
4806 else if ((code == PRE_INC || code == PRE_DEC)
4807 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4808 REGNO (rld[i].reg_rtx))
4809 /* Make sure it is the inc/dec pseudo, and not
4810 some other (e.g. output operand) pseudo. */
4811 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4812 == REGNO (XEXP (in_reg, 0))))
4814 SET_HARD_REG_BIT (reg_is_output_reload,
4815 REGNO (rld[i].reg_rtx));
4816 SET_REGNO_REG_SET (&reg_has_output_reload,
4817 REGNO (XEXP (in_reg, 0)));
4819 else if (code == PRE_INC || code == PRE_DEC
4820 || code == POST_INC || code == POST_DEC)
4822 int in_regno = REGNO (XEXP (in_reg, 0));
4824 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4826 int in_hard_regno;
4827 bool forget_p = true;
4829 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4830 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4831 in_hard_regno))
4833 for (x = old_prev ? NEXT_INSN (old_prev) : insn;
4834 x != old_next;
4835 x = NEXT_INSN (x))
4836 if (x == reg_reloaded_insn[in_hard_regno])
4838 forget_p = false;
4839 break;
4842 /* If for some reasons, we didn't set up
4843 reg_last_reload_reg in this insn,
4844 invalidate inheritance from previous
4845 insns for the incremented/decremented
4846 register. Such registers will be not in
4847 reg_has_output_reload. Invalidate it
4848 also if the corresponding element in
4849 reg_reloaded_insn is also
4850 invalidated. */
4851 if (forget_p)
4852 forget_old_reloads_1 (XEXP (in_reg, 0),
4853 NULL_RTX, NULL);
4858 /* If a pseudo that got a hard register is auto-incremented,
4859 we must purge records of copying it into pseudos without
4860 hard registers. */
4861 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4862 if (REG_NOTE_KIND (x) == REG_INC)
4864 /* See if this pseudo reg was reloaded in this insn.
4865 If so, its last-reload info is still valid
4866 because it is based on this insn's reload. */
4867 for (i = 0; i < n_reloads; i++)
4868 if (rld[i].out == XEXP (x, 0))
4869 break;
4871 if (i == n_reloads)
4872 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4874 #endif
4876 /* A reload reg's contents are unknown after a label. */
4877 if (LABEL_P (insn))
4878 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4880 /* Don't assume a reload reg is still good after a call insn
4881 if it is a call-used reg, or if it contains a value that will
4882 be partially clobbered by the call. */
4883 else if (CALL_P (insn))
4885 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4886 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4888 /* If this is a call to a setjmp-type function, we must not
4889 reuse any reload reg contents across the call; that will
4890 just be clobbered by other uses of the register in later
4891 code, before the longjmp. */
4892 if (find_reg_note (insn, REG_SETJMP, NULL_RTX))
4893 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4897 /* Clean up. */
4898 free (reg_last_reload_reg);
4899 CLEAR_REG_SET (&reg_has_output_reload);
4902 /* Discard all record of any value reloaded from X,
4903 or reloaded in X from someplace else;
4904 unless X is an output reload reg of the current insn.
4906 X may be a hard reg (the reload reg)
4907 or it may be a pseudo reg that was reloaded from.
4909 When DATA is non-NULL just mark the registers in regset
4910 to be forgotten later. */
4912 static void
4913 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4914 void *data)
4916 unsigned int regno;
4917 unsigned int nr;
4918 regset regs = (regset) data;
4920 /* note_stores does give us subregs of hard regs,
4921 subreg_regno_offset requires a hard reg. */
4922 while (GET_CODE (x) == SUBREG)
4924 /* We ignore the subreg offset when calculating the regno,
4925 because we are using the entire underlying hard register
4926 below. */
4927 x = SUBREG_REG (x);
4930 if (!REG_P (x))
4931 return;
4933 regno = REGNO (x);
4935 if (regno >= FIRST_PSEUDO_REGISTER)
4936 nr = 1;
4937 else
4939 unsigned int i;
4941 nr = hard_regno_nregs[regno][GET_MODE (x)];
4942 /* Storing into a spilled-reg invalidates its contents.
4943 This can happen if a block-local pseudo is allocated to that reg
4944 and it wasn't spilled because this block's total need is 0.
4945 Then some insn might have an optional reload and use this reg. */
4946 if (!regs)
4947 for (i = 0; i < nr; i++)
4948 /* But don't do this if the reg actually serves as an output
4949 reload reg in the current instruction. */
4950 if (n_reloads == 0
4951 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4953 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4954 spill_reg_store[regno + i] = 0;
4958 if (regs)
4959 while (nr-- > 0)
4960 SET_REGNO_REG_SET (regs, regno + nr);
4961 else
4963 /* Since value of X has changed,
4964 forget any value previously copied from it. */
4966 while (nr-- > 0)
4967 /* But don't forget a copy if this is the output reload
4968 that establishes the copy's validity. */
4969 if (n_reloads == 0
4970 || !REGNO_REG_SET_P (&reg_has_output_reload, regno + nr))
4971 reg_last_reload_reg[regno + nr] = 0;
4975 /* Forget the reloads marked in regset by previous function. */
4976 static void
4977 forget_marked_reloads (regset regs)
4979 unsigned int reg;
4980 reg_set_iterator rsi;
4981 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4983 if (reg < FIRST_PSEUDO_REGISTER
4984 /* But don't do this if the reg actually serves as an output
4985 reload reg in the current instruction. */
4986 && (n_reloads == 0
4987 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4989 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4990 spill_reg_store[reg] = 0;
4992 if (n_reloads == 0
4993 || !REGNO_REG_SET_P (&reg_has_output_reload, reg))
4994 reg_last_reload_reg[reg] = 0;
4998 /* The following HARD_REG_SETs indicate when each hard register is
4999 used for a reload of various parts of the current insn. */
5001 /* If reg is unavailable for all reloads. */
5002 static HARD_REG_SET reload_reg_unavailable;
5003 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
5004 static HARD_REG_SET reload_reg_used;
5005 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
5006 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
5007 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
5008 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
5009 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
5010 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
5011 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
5012 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
5013 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
5014 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
5015 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
5016 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
5017 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
5018 static HARD_REG_SET reload_reg_used_in_op_addr;
5019 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
5020 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
5021 /* If reg is in use for a RELOAD_FOR_INSN reload. */
5022 static HARD_REG_SET reload_reg_used_in_insn;
5023 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
5024 static HARD_REG_SET reload_reg_used_in_other_addr;
5026 /* If reg is in use as a reload reg for any sort of reload. */
5027 static HARD_REG_SET reload_reg_used_at_all;
5029 /* If reg is use as an inherited reload. We just mark the first register
5030 in the group. */
5031 static HARD_REG_SET reload_reg_used_for_inherit;
5033 /* Records which hard regs are used in any way, either as explicit use or
5034 by being allocated to a pseudo during any point of the current insn. */
5035 static HARD_REG_SET reg_used_in_insn;
5037 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
5038 TYPE. MODE is used to indicate how many consecutive regs are
5039 actually used. */
5041 static void
5042 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
5043 enum machine_mode mode)
5045 switch (type)
5047 case RELOAD_OTHER:
5048 add_to_hard_reg_set (&reload_reg_used, mode, regno);
5049 break;
5051 case RELOAD_FOR_INPUT_ADDRESS:
5052 add_to_hard_reg_set (&reload_reg_used_in_input_addr[opnum], mode, regno);
5053 break;
5055 case RELOAD_FOR_INPADDR_ADDRESS:
5056 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr[opnum], mode, regno);
5057 break;
5059 case RELOAD_FOR_OUTPUT_ADDRESS:
5060 add_to_hard_reg_set (&reload_reg_used_in_output_addr[opnum], mode, regno);
5061 break;
5063 case RELOAD_FOR_OUTADDR_ADDRESS:
5064 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr[opnum], mode, regno);
5065 break;
5067 case RELOAD_FOR_OPERAND_ADDRESS:
5068 add_to_hard_reg_set (&reload_reg_used_in_op_addr, mode, regno);
5069 break;
5071 case RELOAD_FOR_OPADDR_ADDR:
5072 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload, mode, regno);
5073 break;
5075 case RELOAD_FOR_OTHER_ADDRESS:
5076 add_to_hard_reg_set (&reload_reg_used_in_other_addr, mode, regno);
5077 break;
5079 case RELOAD_FOR_INPUT:
5080 add_to_hard_reg_set (&reload_reg_used_in_input[opnum], mode, regno);
5081 break;
5083 case RELOAD_FOR_OUTPUT:
5084 add_to_hard_reg_set (&reload_reg_used_in_output[opnum], mode, regno);
5085 break;
5087 case RELOAD_FOR_INSN:
5088 add_to_hard_reg_set (&reload_reg_used_in_insn, mode, regno);
5089 break;
5092 add_to_hard_reg_set (&reload_reg_used_at_all, mode, regno);
5095 /* Similarly, but show REGNO is no longer in use for a reload. */
5097 static void
5098 clear_reload_reg_in_use (unsigned int regno, int opnum,
5099 enum reload_type type, enum machine_mode mode)
5101 unsigned int nregs = hard_regno_nregs[regno][mode];
5102 unsigned int start_regno, end_regno, r;
5103 int i;
5104 /* A complication is that for some reload types, inheritance might
5105 allow multiple reloads of the same types to share a reload register.
5106 We set check_opnum if we have to check only reloads with the same
5107 operand number, and check_any if we have to check all reloads. */
5108 int check_opnum = 0;
5109 int check_any = 0;
5110 HARD_REG_SET *used_in_set;
5112 switch (type)
5114 case RELOAD_OTHER:
5115 used_in_set = &reload_reg_used;
5116 break;
5118 case RELOAD_FOR_INPUT_ADDRESS:
5119 used_in_set = &reload_reg_used_in_input_addr[opnum];
5120 break;
5122 case RELOAD_FOR_INPADDR_ADDRESS:
5123 check_opnum = 1;
5124 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
5125 break;
5127 case RELOAD_FOR_OUTPUT_ADDRESS:
5128 used_in_set = &reload_reg_used_in_output_addr[opnum];
5129 break;
5131 case RELOAD_FOR_OUTADDR_ADDRESS:
5132 check_opnum = 1;
5133 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
5134 break;
5136 case RELOAD_FOR_OPERAND_ADDRESS:
5137 used_in_set = &reload_reg_used_in_op_addr;
5138 break;
5140 case RELOAD_FOR_OPADDR_ADDR:
5141 check_any = 1;
5142 used_in_set = &reload_reg_used_in_op_addr_reload;
5143 break;
5145 case RELOAD_FOR_OTHER_ADDRESS:
5146 used_in_set = &reload_reg_used_in_other_addr;
5147 check_any = 1;
5148 break;
5150 case RELOAD_FOR_INPUT:
5151 used_in_set = &reload_reg_used_in_input[opnum];
5152 break;
5154 case RELOAD_FOR_OUTPUT:
5155 used_in_set = &reload_reg_used_in_output[opnum];
5156 break;
5158 case RELOAD_FOR_INSN:
5159 used_in_set = &reload_reg_used_in_insn;
5160 break;
5161 default:
5162 gcc_unreachable ();
5164 /* We resolve conflicts with remaining reloads of the same type by
5165 excluding the intervals of reload registers by them from the
5166 interval of freed reload registers. Since we only keep track of
5167 one set of interval bounds, we might have to exclude somewhat
5168 more than what would be necessary if we used a HARD_REG_SET here.
5169 But this should only happen very infrequently, so there should
5170 be no reason to worry about it. */
5172 start_regno = regno;
5173 end_regno = regno + nregs;
5174 if (check_opnum || check_any)
5176 for (i = n_reloads - 1; i >= 0; i--)
5178 if (rld[i].when_needed == type
5179 && (check_any || rld[i].opnum == opnum)
5180 && rld[i].reg_rtx)
5182 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
5183 unsigned int conflict_end
5184 = end_hard_regno (rld[i].mode, conflict_start);
5186 /* If there is an overlap with the first to-be-freed register,
5187 adjust the interval start. */
5188 if (conflict_start <= start_regno && conflict_end > start_regno)
5189 start_regno = conflict_end;
5190 /* Otherwise, if there is a conflict with one of the other
5191 to-be-freed registers, adjust the interval end. */
5192 if (conflict_start > start_regno && conflict_start < end_regno)
5193 end_regno = conflict_start;
5198 for (r = start_regno; r < end_regno; r++)
5199 CLEAR_HARD_REG_BIT (*used_in_set, r);
5202 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
5203 specified by OPNUM and TYPE. */
5205 static int
5206 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
5208 int i;
5210 /* In use for a RELOAD_OTHER means it's not available for anything. */
5211 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
5212 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5213 return 0;
5215 switch (type)
5217 case RELOAD_OTHER:
5218 /* In use for anything means we can't use it for RELOAD_OTHER. */
5219 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
5220 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5221 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5222 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5223 return 0;
5225 for (i = 0; i < reload_n_operands; i++)
5226 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5227 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5228 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5229 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5230 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5231 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5232 return 0;
5234 return 1;
5236 case RELOAD_FOR_INPUT:
5237 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5238 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
5239 return 0;
5241 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5242 return 0;
5244 /* If it is used for some other input, can't use it. */
5245 for (i = 0; i < reload_n_operands; i++)
5246 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5247 return 0;
5249 /* If it is used in a later operand's address, can't use it. */
5250 for (i = opnum + 1; i < reload_n_operands; i++)
5251 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5252 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5253 return 0;
5255 return 1;
5257 case RELOAD_FOR_INPUT_ADDRESS:
5258 /* Can't use a register if it is used for an input address for this
5259 operand or used as an input in an earlier one. */
5260 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
5261 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5262 return 0;
5264 for (i = 0; i < opnum; i++)
5265 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5266 return 0;
5268 return 1;
5270 case RELOAD_FOR_INPADDR_ADDRESS:
5271 /* Can't use a register if it is used for an input address
5272 for this operand or used as an input in an earlier
5273 one. */
5274 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
5275 return 0;
5277 for (i = 0; i < opnum; i++)
5278 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5279 return 0;
5281 return 1;
5283 case RELOAD_FOR_OUTPUT_ADDRESS:
5284 /* Can't use a register if it is used for an output address for this
5285 operand or used as an output in this or a later operand. Note
5286 that multiple output operands are emitted in reverse order, so
5287 the conflicting ones are those with lower indices. */
5288 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
5289 return 0;
5291 for (i = 0; i <= opnum; i++)
5292 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5293 return 0;
5295 return 1;
5297 case RELOAD_FOR_OUTADDR_ADDRESS:
5298 /* Can't use a register if it is used for an output address
5299 for this operand or used as an output in this or a
5300 later operand. Note that multiple output operands are
5301 emitted in reverse order, so the conflicting ones are
5302 those with lower indices. */
5303 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5304 return 0;
5306 for (i = 0; i <= opnum; i++)
5307 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5308 return 0;
5310 return 1;
5312 case RELOAD_FOR_OPERAND_ADDRESS:
5313 for (i = 0; i < reload_n_operands; i++)
5314 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5315 return 0;
5317 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5318 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5320 case RELOAD_FOR_OPADDR_ADDR:
5321 for (i = 0; i < reload_n_operands; i++)
5322 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5323 return 0;
5325 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
5327 case RELOAD_FOR_OUTPUT:
5328 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
5329 outputs, or an operand address for this or an earlier output.
5330 Note that multiple output operands are emitted in reverse order,
5331 so the conflicting ones are those with higher indices. */
5332 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
5333 return 0;
5335 for (i = 0; i < reload_n_operands; i++)
5336 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5337 return 0;
5339 for (i = opnum; i < reload_n_operands; i++)
5340 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5341 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5342 return 0;
5344 return 1;
5346 case RELOAD_FOR_INSN:
5347 for (i = 0; i < reload_n_operands; i++)
5348 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
5349 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5350 return 0;
5352 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5353 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
5355 case RELOAD_FOR_OTHER_ADDRESS:
5356 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
5358 default:
5359 gcc_unreachable ();
5363 /* Return 1 if the value in reload reg REGNO, as used by the reload with
5364 the number RELOADNUM, is still available in REGNO at the end of the insn.
5366 We can assume that the reload reg was already tested for availability
5367 at the time it is needed, and we should not check this again,
5368 in case the reg has already been marked in use. */
5370 static int
5371 reload_reg_reaches_end_p (unsigned int regno, int reloadnum)
5373 int opnum = rld[reloadnum].opnum;
5374 enum reload_type type = rld[reloadnum].when_needed;
5375 int i;
5377 /* See if there is a reload with the same type for this operand, using
5378 the same register. This case is not handled by the code below. */
5379 for (i = reloadnum + 1; i < n_reloads; i++)
5381 rtx reg;
5382 int nregs;
5384 if (rld[i].opnum != opnum || rld[i].when_needed != type)
5385 continue;
5386 reg = rld[i].reg_rtx;
5387 if (reg == NULL_RTX)
5388 continue;
5389 nregs = hard_regno_nregs[REGNO (reg)][GET_MODE (reg)];
5390 if (regno >= REGNO (reg) && regno < REGNO (reg) + nregs)
5391 return 0;
5394 switch (type)
5396 case RELOAD_OTHER:
5397 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
5398 its value must reach the end. */
5399 return 1;
5401 /* If this use is for part of the insn,
5402 its value reaches if no subsequent part uses the same register.
5403 Just like the above function, don't try to do this with lots
5404 of fallthroughs. */
5406 case RELOAD_FOR_OTHER_ADDRESS:
5407 /* Here we check for everything else, since these don't conflict
5408 with anything else and everything comes later. */
5410 for (i = 0; i < reload_n_operands; i++)
5411 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5412 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5413 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
5414 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5415 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5416 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5417 return 0;
5419 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5420 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
5421 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5422 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
5424 case RELOAD_FOR_INPUT_ADDRESS:
5425 case RELOAD_FOR_INPADDR_ADDRESS:
5426 /* Similar, except that we check only for this and subsequent inputs
5427 and the address of only subsequent inputs and we do not need
5428 to check for RELOAD_OTHER objects since they are known not to
5429 conflict. */
5431 for (i = opnum; i < reload_n_operands; i++)
5432 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5433 return 0;
5435 /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS
5436 could be killed if the register is also used by reload with type
5437 RELOAD_FOR_INPUT_ADDRESS, so check it. */
5438 if (type == RELOAD_FOR_INPADDR_ADDRESS
5439 && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno))
5440 return 0;
5442 for (i = opnum + 1; i < reload_n_operands; i++)
5443 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5444 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5445 return 0;
5447 for (i = 0; i < reload_n_operands; i++)
5448 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5449 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5450 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5451 return 0;
5453 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5454 return 0;
5456 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5457 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5458 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5460 case RELOAD_FOR_INPUT:
5461 /* Similar to input address, except we start at the next operand for
5462 both input and input address and we do not check for
5463 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5464 would conflict. */
5466 for (i = opnum + 1; i < reload_n_operands; i++)
5467 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5468 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5469 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5470 return 0;
5472 /* ... fall through ... */
5474 case RELOAD_FOR_OPERAND_ADDRESS:
5475 /* Check outputs and their addresses. */
5477 for (i = 0; i < reload_n_operands; i++)
5478 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5479 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5480 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5481 return 0;
5483 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5485 case RELOAD_FOR_OPADDR_ADDR:
5486 for (i = 0; i < reload_n_operands; i++)
5487 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5488 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5489 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5490 return 0;
5492 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5493 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5494 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5496 case RELOAD_FOR_INSN:
5497 /* These conflict with other outputs with RELOAD_OTHER. So
5498 we need only check for output addresses. */
5500 opnum = reload_n_operands;
5502 /* ... fall through ... */
5504 case RELOAD_FOR_OUTPUT:
5505 case RELOAD_FOR_OUTPUT_ADDRESS:
5506 case RELOAD_FOR_OUTADDR_ADDRESS:
5507 /* We already know these can't conflict with a later output. So the
5508 only thing to check are later output addresses.
5509 Note that multiple output operands are emitted in reverse order,
5510 so the conflicting ones are those with lower indices. */
5511 for (i = 0; i < opnum; i++)
5512 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5513 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5514 return 0;
5516 /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS
5517 could be killed if the register is also used by reload with type
5518 RELOAD_FOR_OUTPUT_ADDRESS, so check it. */
5519 if (type == RELOAD_FOR_OUTADDR_ADDRESS
5520 && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
5521 return 0;
5523 return 1;
5525 default:
5526 gcc_unreachable ();
5530 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5531 every register in REG. */
5533 static bool
5534 reload_reg_rtx_reaches_end_p (rtx reg, int reloadnum)
5536 unsigned int i;
5538 for (i = REGNO (reg); i < END_REGNO (reg); i++)
5539 if (!reload_reg_reaches_end_p (i, reloadnum))
5540 return false;
5541 return true;
5545 /* Returns whether R1 and R2 are uniquely chained: the value of one
5546 is used by the other, and that value is not used by any other
5547 reload for this insn. This is used to partially undo the decision
5548 made in find_reloads when in the case of multiple
5549 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5550 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5551 reloads. This code tries to avoid the conflict created by that
5552 change. It might be cleaner to explicitly keep track of which
5553 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5554 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5555 this after the fact. */
5556 static bool
5557 reloads_unique_chain_p (int r1, int r2)
5559 int i;
5561 /* We only check input reloads. */
5562 if (! rld[r1].in || ! rld[r2].in)
5563 return false;
5565 /* Avoid anything with output reloads. */
5566 if (rld[r1].out || rld[r2].out)
5567 return false;
5569 /* "chained" means one reload is a component of the other reload,
5570 not the same as the other reload. */
5571 if (rld[r1].opnum != rld[r2].opnum
5572 || rtx_equal_p (rld[r1].in, rld[r2].in)
5573 || rld[r1].optional || rld[r2].optional
5574 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5575 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5576 return false;
5578 /* The following loop assumes that r1 is the reload that feeds r2. */
5579 if (r1 > r2)
5581 int tmp = r2;
5582 r2 = r1;
5583 r1 = tmp;
5586 for (i = 0; i < n_reloads; i ++)
5587 /* Look for input reloads that aren't our two */
5588 if (i != r1 && i != r2 && rld[i].in)
5590 /* If our reload is mentioned at all, it isn't a simple chain. */
5591 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5592 return false;
5594 return true;
5597 /* The recursive function change all occurrences of WHAT in *WHERE
5598 to REPL. */
5599 static void
5600 substitute (rtx *where, const_rtx what, rtx repl)
5602 const char *fmt;
5603 int i;
5604 enum rtx_code code;
5606 if (*where == 0)
5607 return;
5609 if (*where == what || rtx_equal_p (*where, what))
5611 /* Record the location of the changed rtx. */
5612 substitute_stack.safe_push (where);
5613 *where = repl;
5614 return;
5617 code = GET_CODE (*where);
5618 fmt = GET_RTX_FORMAT (code);
5619 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5621 if (fmt[i] == 'E')
5623 int j;
5625 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5626 substitute (&XVECEXP (*where, i, j), what, repl);
5628 else if (fmt[i] == 'e')
5629 substitute (&XEXP (*where, i), what, repl);
5633 /* The function returns TRUE if chain of reload R1 and R2 (in any
5634 order) can be evaluated without usage of intermediate register for
5635 the reload containing another reload. It is important to see
5636 gen_reload to understand what the function is trying to do. As an
5637 example, let us have reload chain
5639 r2: const
5640 r1: <something> + const
5642 and reload R2 got reload reg HR. The function returns true if
5643 there is a correct insn HR = HR + <something>. Otherwise,
5644 gen_reload will use intermediate register (and this is the reload
5645 reg for R1) to reload <something>.
5647 We need this function to find a conflict for chain reloads. In our
5648 example, if HR = HR + <something> is incorrect insn, then we cannot
5649 use HR as a reload register for R2. If we do use it then we get a
5650 wrong code:
5652 HR = const
5653 HR = <something>
5654 HR = HR + HR
5657 static bool
5658 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5660 /* Assume other cases in gen_reload are not possible for
5661 chain reloads or do need an intermediate hard registers. */
5662 bool result = true;
5663 int regno, n, code;
5664 rtx out, in, insn;
5665 rtx last = get_last_insn ();
5667 /* Make r2 a component of r1. */
5668 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5670 n = r1;
5671 r1 = r2;
5672 r2 = n;
5674 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5675 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5676 gcc_assert (regno >= 0);
5677 out = gen_rtx_REG (rld[r1].mode, regno);
5678 in = rld[r1].in;
5679 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5681 /* If IN is a paradoxical SUBREG, remove it and try to put the
5682 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5683 strip_paradoxical_subreg (&in, &out);
5685 if (GET_CODE (in) == PLUS
5686 && (REG_P (XEXP (in, 0))
5687 || GET_CODE (XEXP (in, 0)) == SUBREG
5688 || MEM_P (XEXP (in, 0)))
5689 && (REG_P (XEXP (in, 1))
5690 || GET_CODE (XEXP (in, 1)) == SUBREG
5691 || CONSTANT_P (XEXP (in, 1))
5692 || MEM_P (XEXP (in, 1))))
5694 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5695 code = recog_memoized (insn);
5696 result = false;
5698 if (code >= 0)
5700 extract_insn (insn);
5701 /* We want constrain operands to treat this insn strictly in
5702 its validity determination, i.e., the way it would after
5703 reload has completed. */
5704 result = constrain_operands (1);
5707 delete_insns_since (last);
5710 /* Restore the original value at each changed address within R1. */
5711 while (!substitute_stack.is_empty ())
5713 rtx *where = substitute_stack.pop ();
5714 *where = rld[r2].in;
5717 return result;
5720 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5721 Return 0 otherwise.
5723 This function uses the same algorithm as reload_reg_free_p above. */
5725 static int
5726 reloads_conflict (int r1, int r2)
5728 enum reload_type r1_type = rld[r1].when_needed;
5729 enum reload_type r2_type = rld[r2].when_needed;
5730 int r1_opnum = rld[r1].opnum;
5731 int r2_opnum = rld[r2].opnum;
5733 /* RELOAD_OTHER conflicts with everything. */
5734 if (r2_type == RELOAD_OTHER)
5735 return 1;
5737 /* Otherwise, check conflicts differently for each type. */
5739 switch (r1_type)
5741 case RELOAD_FOR_INPUT:
5742 return (r2_type == RELOAD_FOR_INSN
5743 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5744 || r2_type == RELOAD_FOR_OPADDR_ADDR
5745 || r2_type == RELOAD_FOR_INPUT
5746 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5747 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5748 && r2_opnum > r1_opnum));
5750 case RELOAD_FOR_INPUT_ADDRESS:
5751 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5752 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5754 case RELOAD_FOR_INPADDR_ADDRESS:
5755 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5756 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5758 case RELOAD_FOR_OUTPUT_ADDRESS:
5759 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5760 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5762 case RELOAD_FOR_OUTADDR_ADDRESS:
5763 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5764 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5766 case RELOAD_FOR_OPERAND_ADDRESS:
5767 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5768 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5769 && (!reloads_unique_chain_p (r1, r2)
5770 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5772 case RELOAD_FOR_OPADDR_ADDR:
5773 return (r2_type == RELOAD_FOR_INPUT
5774 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5776 case RELOAD_FOR_OUTPUT:
5777 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5778 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5779 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5780 && r2_opnum >= r1_opnum));
5782 case RELOAD_FOR_INSN:
5783 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5784 || r2_type == RELOAD_FOR_INSN
5785 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5787 case RELOAD_FOR_OTHER_ADDRESS:
5788 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5790 case RELOAD_OTHER:
5791 return 1;
5793 default:
5794 gcc_unreachable ();
5798 /* Indexed by reload number, 1 if incoming value
5799 inherited from previous insns. */
5800 static char reload_inherited[MAX_RELOADS];
5802 /* For an inherited reload, this is the insn the reload was inherited from,
5803 if we know it. Otherwise, this is 0. */
5804 static rtx reload_inheritance_insn[MAX_RELOADS];
5806 /* If nonzero, this is a place to get the value of the reload,
5807 rather than using reload_in. */
5808 static rtx reload_override_in[MAX_RELOADS];
5810 /* For each reload, the hard register number of the register used,
5811 or -1 if we did not need a register for this reload. */
5812 static int reload_spill_index[MAX_RELOADS];
5814 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5815 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5817 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5818 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5820 /* Subroutine of free_for_value_p, used to check a single register.
5821 START_REGNO is the starting regno of the full reload register
5822 (possibly comprising multiple hard registers) that we are considering. */
5824 static int
5825 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5826 enum reload_type type, rtx value, rtx out,
5827 int reloadnum, int ignore_address_reloads)
5829 int time1;
5830 /* Set if we see an input reload that must not share its reload register
5831 with any new earlyclobber, but might otherwise share the reload
5832 register with an output or input-output reload. */
5833 int check_earlyclobber = 0;
5834 int i;
5835 int copy = 0;
5837 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5838 return 0;
5840 if (out == const0_rtx)
5842 copy = 1;
5843 out = NULL_RTX;
5846 /* We use some pseudo 'time' value to check if the lifetimes of the
5847 new register use would overlap with the one of a previous reload
5848 that is not read-only or uses a different value.
5849 The 'time' used doesn't have to be linear in any shape or form, just
5850 monotonic.
5851 Some reload types use different 'buckets' for each operand.
5852 So there are MAX_RECOG_OPERANDS different time values for each
5853 such reload type.
5854 We compute TIME1 as the time when the register for the prospective
5855 new reload ceases to be live, and TIME2 for each existing
5856 reload as the time when that the reload register of that reload
5857 becomes live.
5858 Where there is little to be gained by exact lifetime calculations,
5859 we just make conservative assumptions, i.e. a longer lifetime;
5860 this is done in the 'default:' cases. */
5861 switch (type)
5863 case RELOAD_FOR_OTHER_ADDRESS:
5864 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5865 time1 = copy ? 0 : 1;
5866 break;
5867 case RELOAD_OTHER:
5868 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5869 break;
5870 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5871 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5872 respectively, to the time values for these, we get distinct time
5873 values. To get distinct time values for each operand, we have to
5874 multiply opnum by at least three. We round that up to four because
5875 multiply by four is often cheaper. */
5876 case RELOAD_FOR_INPADDR_ADDRESS:
5877 time1 = opnum * 4 + 2;
5878 break;
5879 case RELOAD_FOR_INPUT_ADDRESS:
5880 time1 = opnum * 4 + 3;
5881 break;
5882 case RELOAD_FOR_INPUT:
5883 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5884 executes (inclusive). */
5885 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5886 break;
5887 case RELOAD_FOR_OPADDR_ADDR:
5888 /* opnum * 4 + 4
5889 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5890 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5891 break;
5892 case RELOAD_FOR_OPERAND_ADDRESS:
5893 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5894 is executed. */
5895 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5896 break;
5897 case RELOAD_FOR_OUTADDR_ADDRESS:
5898 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5899 break;
5900 case RELOAD_FOR_OUTPUT_ADDRESS:
5901 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5902 break;
5903 default:
5904 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5907 for (i = 0; i < n_reloads; i++)
5909 rtx reg = rld[i].reg_rtx;
5910 if (reg && REG_P (reg)
5911 && ((unsigned) regno - true_regnum (reg)
5912 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5913 && i != reloadnum)
5915 rtx other_input = rld[i].in;
5917 /* If the other reload loads the same input value, that
5918 will not cause a conflict only if it's loading it into
5919 the same register. */
5920 if (true_regnum (reg) != start_regno)
5921 other_input = NULL_RTX;
5922 if (! other_input || ! rtx_equal_p (other_input, value)
5923 || rld[i].out || out)
5925 int time2;
5926 switch (rld[i].when_needed)
5928 case RELOAD_FOR_OTHER_ADDRESS:
5929 time2 = 0;
5930 break;
5931 case RELOAD_FOR_INPADDR_ADDRESS:
5932 /* find_reloads makes sure that a
5933 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5934 by at most one - the first -
5935 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5936 address reload is inherited, the address address reload
5937 goes away, so we can ignore this conflict. */
5938 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5939 && ignore_address_reloads
5940 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5941 Then the address address is still needed to store
5942 back the new address. */
5943 && ! rld[reloadnum].out)
5944 continue;
5945 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5946 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5947 reloads go away. */
5948 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5949 && ignore_address_reloads
5950 /* Unless we are reloading an auto_inc expression. */
5951 && ! rld[reloadnum].out)
5952 continue;
5953 time2 = rld[i].opnum * 4 + 2;
5954 break;
5955 case RELOAD_FOR_INPUT_ADDRESS:
5956 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5957 && ignore_address_reloads
5958 && ! rld[reloadnum].out)
5959 continue;
5960 time2 = rld[i].opnum * 4 + 3;
5961 break;
5962 case RELOAD_FOR_INPUT:
5963 time2 = rld[i].opnum * 4 + 4;
5964 check_earlyclobber = 1;
5965 break;
5966 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5967 == MAX_RECOG_OPERAND * 4 */
5968 case RELOAD_FOR_OPADDR_ADDR:
5969 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5970 && ignore_address_reloads
5971 && ! rld[reloadnum].out)
5972 continue;
5973 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5974 break;
5975 case RELOAD_FOR_OPERAND_ADDRESS:
5976 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5977 check_earlyclobber = 1;
5978 break;
5979 case RELOAD_FOR_INSN:
5980 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5981 break;
5982 case RELOAD_FOR_OUTPUT:
5983 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5984 instruction is executed. */
5985 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5986 break;
5987 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5988 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5989 value. */
5990 case RELOAD_FOR_OUTADDR_ADDRESS:
5991 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5992 && ignore_address_reloads
5993 && ! rld[reloadnum].out)
5994 continue;
5995 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5996 break;
5997 case RELOAD_FOR_OUTPUT_ADDRESS:
5998 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5999 break;
6000 case RELOAD_OTHER:
6001 /* If there is no conflict in the input part, handle this
6002 like an output reload. */
6003 if (! rld[i].in || rtx_equal_p (other_input, value))
6005 time2 = MAX_RECOG_OPERANDS * 4 + 4;
6006 /* Earlyclobbered outputs must conflict with inputs. */
6007 if (earlyclobber_operand_p (rld[i].out))
6008 time2 = MAX_RECOG_OPERANDS * 4 + 3;
6010 break;
6012 time2 = 1;
6013 /* RELOAD_OTHER might be live beyond instruction execution,
6014 but this is not obvious when we set time2 = 1. So check
6015 here if there might be a problem with the new reload
6016 clobbering the register used by the RELOAD_OTHER. */
6017 if (out)
6018 return 0;
6019 break;
6020 default:
6021 return 0;
6023 if ((time1 >= time2
6024 && (! rld[i].in || rld[i].out
6025 || ! rtx_equal_p (other_input, value)))
6026 || (out && rld[reloadnum].out_reg
6027 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
6028 return 0;
6033 /* Earlyclobbered outputs must conflict with inputs. */
6034 if (check_earlyclobber && out && earlyclobber_operand_p (out))
6035 return 0;
6037 return 1;
6040 /* Return 1 if the value in reload reg REGNO, as used by a reload
6041 needed for the part of the insn specified by OPNUM and TYPE,
6042 may be used to load VALUE into it.
6044 MODE is the mode in which the register is used, this is needed to
6045 determine how many hard regs to test.
6047 Other read-only reloads with the same value do not conflict
6048 unless OUT is nonzero and these other reloads have to live while
6049 output reloads live.
6050 If OUT is CONST0_RTX, this is a special case: it means that the
6051 test should not be for using register REGNO as reload register, but
6052 for copying from register REGNO into the reload register.
6054 RELOADNUM is the number of the reload we want to load this value for;
6055 a reload does not conflict with itself.
6057 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
6058 reloads that load an address for the very reload we are considering.
6060 The caller has to make sure that there is no conflict with the return
6061 register. */
6063 static int
6064 free_for_value_p (int regno, enum machine_mode mode, int opnum,
6065 enum reload_type type, rtx value, rtx out, int reloadnum,
6066 int ignore_address_reloads)
6068 int nregs = hard_regno_nregs[regno][mode];
6069 while (nregs-- > 0)
6070 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
6071 value, out, reloadnum,
6072 ignore_address_reloads))
6073 return 0;
6074 return 1;
6077 /* Return nonzero if the rtx X is invariant over the current function. */
6078 /* ??? Actually, the places where we use this expect exactly what is
6079 tested here, and not everything that is function invariant. In
6080 particular, the frame pointer and arg pointer are special cased;
6081 pic_offset_table_rtx is not, and we must not spill these things to
6082 memory. */
6085 function_invariant_p (const_rtx x)
6087 if (CONSTANT_P (x))
6088 return 1;
6089 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
6090 return 1;
6091 if (GET_CODE (x) == PLUS
6092 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
6093 && GET_CODE (XEXP (x, 1)) == CONST_INT)
6094 return 1;
6095 return 0;
6098 /* Determine whether the reload reg X overlaps any rtx'es used for
6099 overriding inheritance. Return nonzero if so. */
6101 static int
6102 conflicts_with_override (rtx x)
6104 int i;
6105 for (i = 0; i < n_reloads; i++)
6106 if (reload_override_in[i]
6107 && reg_overlap_mentioned_p (x, reload_override_in[i]))
6108 return 1;
6109 return 0;
6112 /* Give an error message saying we failed to find a reload for INSN,
6113 and clear out reload R. */
6114 static void
6115 failed_reload (rtx insn, int r)
6117 if (asm_noperands (PATTERN (insn)) < 0)
6118 /* It's the compiler's fault. */
6119 fatal_insn ("could not find a spill register", insn);
6121 /* It's the user's fault; the operand's mode and constraint
6122 don't match. Disable this reload so we don't crash in final. */
6123 error_for_asm (insn,
6124 "%<asm%> operand constraint incompatible with operand size");
6125 rld[r].in = 0;
6126 rld[r].out = 0;
6127 rld[r].reg_rtx = 0;
6128 rld[r].optional = 1;
6129 rld[r].secondary_p = 1;
6132 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
6133 for reload R. If it's valid, get an rtx for it. Return nonzero if
6134 successful. */
6135 static int
6136 set_reload_reg (int i, int r)
6138 /* regno is 'set but not used' if HARD_REGNO_MODE_OK doesn't use its first
6139 parameter. */
6140 int regno ATTRIBUTE_UNUSED;
6141 rtx reg = spill_reg_rtx[i];
6143 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
6144 spill_reg_rtx[i] = reg
6145 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
6147 regno = true_regnum (reg);
6149 /* Detect when the reload reg can't hold the reload mode.
6150 This used to be one `if', but Sequent compiler can't handle that. */
6151 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
6153 enum machine_mode test_mode = VOIDmode;
6154 if (rld[r].in)
6155 test_mode = GET_MODE (rld[r].in);
6156 /* If rld[r].in has VOIDmode, it means we will load it
6157 in whatever mode the reload reg has: to wit, rld[r].mode.
6158 We have already tested that for validity. */
6159 /* Aside from that, we need to test that the expressions
6160 to reload from or into have modes which are valid for this
6161 reload register. Otherwise the reload insns would be invalid. */
6162 if (! (rld[r].in != 0 && test_mode != VOIDmode
6163 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
6164 if (! (rld[r].out != 0
6165 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
6167 /* The reg is OK. */
6168 last_spill_reg = i;
6170 /* Mark as in use for this insn the reload regs we use
6171 for this. */
6172 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
6173 rld[r].when_needed, rld[r].mode);
6175 rld[r].reg_rtx = reg;
6176 reload_spill_index[r] = spill_regs[i];
6177 return 1;
6180 return 0;
6183 /* Find a spill register to use as a reload register for reload R.
6184 LAST_RELOAD is nonzero if this is the last reload for the insn being
6185 processed.
6187 Set rld[R].reg_rtx to the register allocated.
6189 We return 1 if successful, or 0 if we couldn't find a spill reg and
6190 we didn't change anything. */
6192 static int
6193 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
6194 int last_reload)
6196 int i, pass, count;
6198 /* If we put this reload ahead, thinking it is a group,
6199 then insist on finding a group. Otherwise we can grab a
6200 reg that some other reload needs.
6201 (That can happen when we have a 68000 DATA_OR_FP_REG
6202 which is a group of data regs or one fp reg.)
6203 We need not be so restrictive if there are no more reloads
6204 for this insn.
6206 ??? Really it would be nicer to have smarter handling
6207 for that kind of reg class, where a problem like this is normal.
6208 Perhaps those classes should be avoided for reloading
6209 by use of more alternatives. */
6211 int force_group = rld[r].nregs > 1 && ! last_reload;
6213 /* If we want a single register and haven't yet found one,
6214 take any reg in the right class and not in use.
6215 If we want a consecutive group, here is where we look for it.
6217 We use three passes so we can first look for reload regs to
6218 reuse, which are already in use for other reloads in this insn,
6219 and only then use additional registers which are not "bad", then
6220 finally any register.
6222 I think that maximizing reuse is needed to make sure we don't
6223 run out of reload regs. Suppose we have three reloads, and
6224 reloads A and B can share regs. These need two regs.
6225 Suppose A and B are given different regs.
6226 That leaves none for C. */
6227 for (pass = 0; pass < 3; pass++)
6229 /* I is the index in spill_regs.
6230 We advance it round-robin between insns to use all spill regs
6231 equally, so that inherited reloads have a chance
6232 of leapfrogging each other. */
6234 i = last_spill_reg;
6236 for (count = 0; count < n_spills; count++)
6238 int rclass = (int) rld[r].rclass;
6239 int regnum;
6241 i++;
6242 if (i >= n_spills)
6243 i -= n_spills;
6244 regnum = spill_regs[i];
6246 if ((reload_reg_free_p (regnum, rld[r].opnum,
6247 rld[r].when_needed)
6248 || (rld[r].in
6249 /* We check reload_reg_used to make sure we
6250 don't clobber the return register. */
6251 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
6252 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
6253 rld[r].when_needed, rld[r].in,
6254 rld[r].out, r, 1)))
6255 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
6256 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
6257 /* Look first for regs to share, then for unshared. But
6258 don't share regs used for inherited reloads; they are
6259 the ones we want to preserve. */
6260 && (pass
6261 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
6262 regnum)
6263 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
6264 regnum))))
6266 int nr = hard_regno_nregs[regnum][rld[r].mode];
6268 /* During the second pass we want to avoid reload registers
6269 which are "bad" for this reload. */
6270 if (pass == 1
6271 && ira_bad_reload_regno (regnum, rld[r].in, rld[r].out))
6272 continue;
6274 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
6275 (on 68000) got us two FP regs. If NR is 1,
6276 we would reject both of them. */
6277 if (force_group)
6278 nr = rld[r].nregs;
6279 /* If we need only one reg, we have already won. */
6280 if (nr == 1)
6282 /* But reject a single reg if we demand a group. */
6283 if (force_group)
6284 continue;
6285 break;
6287 /* Otherwise check that as many consecutive regs as we need
6288 are available here. */
6289 while (nr > 1)
6291 int regno = regnum + nr - 1;
6292 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
6293 && spill_reg_order[regno] >= 0
6294 && reload_reg_free_p (regno, rld[r].opnum,
6295 rld[r].when_needed)))
6296 break;
6297 nr--;
6299 if (nr == 1)
6300 break;
6304 /* If we found something on the current pass, omit later passes. */
6305 if (count < n_spills)
6306 break;
6309 /* We should have found a spill register by now. */
6310 if (count >= n_spills)
6311 return 0;
6313 /* I is the index in SPILL_REG_RTX of the reload register we are to
6314 allocate. Get an rtx for it and find its register number. */
6316 return set_reload_reg (i, r);
6319 /* Initialize all the tables needed to allocate reload registers.
6320 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
6321 is the array we use to restore the reg_rtx field for every reload. */
6323 static void
6324 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
6326 int i;
6328 for (i = 0; i < n_reloads; i++)
6329 rld[i].reg_rtx = save_reload_reg_rtx[i];
6331 memset (reload_inherited, 0, MAX_RELOADS);
6332 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
6333 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
6335 CLEAR_HARD_REG_SET (reload_reg_used);
6336 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
6337 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
6338 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
6339 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
6340 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
6342 CLEAR_HARD_REG_SET (reg_used_in_insn);
6344 HARD_REG_SET tmp;
6345 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
6346 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6347 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
6348 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
6349 compute_use_by_pseudos (&reg_used_in_insn, &chain->live_throughout);
6350 compute_use_by_pseudos (&reg_used_in_insn, &chain->dead_or_set);
6353 for (i = 0; i < reload_n_operands; i++)
6355 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
6356 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
6357 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
6358 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
6359 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
6360 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
6363 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
6365 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
6367 for (i = 0; i < n_reloads; i++)
6368 /* If we have already decided to use a certain register,
6369 don't use it in another way. */
6370 if (rld[i].reg_rtx)
6371 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
6372 rld[i].when_needed, rld[i].mode);
6375 #ifdef SECONDARY_MEMORY_NEEDED
6376 /* If X is not a subreg, return it unmodified. If it is a subreg,
6377 look up whether we made a replacement for the SUBREG_REG. Return
6378 either the replacement or the SUBREG_REG. */
6380 static rtx
6381 replaced_subreg (rtx x)
6383 if (GET_CODE (x) == SUBREG)
6384 return find_replacement (&SUBREG_REG (x));
6385 return x;
6387 #endif
6389 /* Compute the offset to pass to subreg_regno_offset, for a pseudo of
6390 mode OUTERMODE that is available in a hard reg of mode INNERMODE.
6391 SUBREG is non-NULL if the pseudo is a subreg whose reg is a pseudo,
6392 otherwise it is NULL. */
6394 static int
6395 compute_reload_subreg_offset (enum machine_mode outermode,
6396 rtx subreg,
6397 enum machine_mode innermode)
6399 int outer_offset;
6400 enum machine_mode middlemode;
6402 if (!subreg)
6403 return subreg_lowpart_offset (outermode, innermode);
6405 outer_offset = SUBREG_BYTE (subreg);
6406 middlemode = GET_MODE (SUBREG_REG (subreg));
6408 /* If SUBREG is paradoxical then return the normal lowpart offset
6409 for OUTERMODE and INNERMODE. Our caller has already checked
6410 that OUTERMODE fits in INNERMODE. */
6411 if (outer_offset == 0
6412 && GET_MODE_SIZE (outermode) > GET_MODE_SIZE (middlemode))
6413 return subreg_lowpart_offset (outermode, innermode);
6415 /* SUBREG is normal, but may not be lowpart; return OUTER_OFFSET
6416 plus the normal lowpart offset for MIDDLEMODE and INNERMODE. */
6417 return outer_offset + subreg_lowpart_offset (middlemode, innermode);
6420 /* Assign hard reg targets for the pseudo-registers we must reload
6421 into hard regs for this insn.
6422 Also output the instructions to copy them in and out of the hard regs.
6424 For machines with register classes, we are responsible for
6425 finding a reload reg in the proper class. */
6427 static void
6428 choose_reload_regs (struct insn_chain *chain)
6430 rtx insn = chain->insn;
6431 int i, j;
6432 unsigned int max_group_size = 1;
6433 enum reg_class group_class = NO_REGS;
6434 int pass, win, inheritance;
6436 rtx save_reload_reg_rtx[MAX_RELOADS];
6438 /* In order to be certain of getting the registers we need,
6439 we must sort the reloads into order of increasing register class.
6440 Then our grabbing of reload registers will parallel the process
6441 that provided the reload registers.
6443 Also note whether any of the reloads wants a consecutive group of regs.
6444 If so, record the maximum size of the group desired and what
6445 register class contains all the groups needed by this insn. */
6447 for (j = 0; j < n_reloads; j++)
6449 reload_order[j] = j;
6450 if (rld[j].reg_rtx != NULL_RTX)
6452 gcc_assert (REG_P (rld[j].reg_rtx)
6453 && HARD_REGISTER_P (rld[j].reg_rtx));
6454 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
6456 else
6457 reload_spill_index[j] = -1;
6459 if (rld[j].nregs > 1)
6461 max_group_size = MAX (rld[j].nregs, max_group_size);
6462 group_class
6463 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
6466 save_reload_reg_rtx[j] = rld[j].reg_rtx;
6469 if (n_reloads > 1)
6470 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
6472 /* If -O, try first with inheritance, then turning it off.
6473 If not -O, don't do inheritance.
6474 Using inheritance when not optimizing leads to paradoxes
6475 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
6476 because one side of the comparison might be inherited. */
6477 win = 0;
6478 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
6480 choose_reload_regs_init (chain, save_reload_reg_rtx);
6482 /* Process the reloads in order of preference just found.
6483 Beyond this point, subregs can be found in reload_reg_rtx.
6485 This used to look for an existing reloaded home for all of the
6486 reloads, and only then perform any new reloads. But that could lose
6487 if the reloads were done out of reg-class order because a later
6488 reload with a looser constraint might have an old home in a register
6489 needed by an earlier reload with a tighter constraint.
6491 To solve this, we make two passes over the reloads, in the order
6492 described above. In the first pass we try to inherit a reload
6493 from a previous insn. If there is a later reload that needs a
6494 class that is a proper subset of the class being processed, we must
6495 also allocate a spill register during the first pass.
6497 Then make a second pass over the reloads to allocate any reloads
6498 that haven't been given registers yet. */
6500 for (j = 0; j < n_reloads; j++)
6502 int r = reload_order[j];
6503 rtx search_equiv = NULL_RTX;
6505 /* Ignore reloads that got marked inoperative. */
6506 if (rld[r].out == 0 && rld[r].in == 0
6507 && ! rld[r].secondary_p)
6508 continue;
6510 /* If find_reloads chose to use reload_in or reload_out as a reload
6511 register, we don't need to chose one. Otherwise, try even if it
6512 found one since we might save an insn if we find the value lying
6513 around.
6514 Try also when reload_in is a pseudo without a hard reg. */
6515 if (rld[r].in != 0 && rld[r].reg_rtx != 0
6516 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
6517 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6518 && !MEM_P (rld[r].in)
6519 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6520 continue;
6522 #if 0 /* No longer needed for correct operation.
6523 It might give better code, or might not; worth an experiment? */
6524 /* If this is an optional reload, we can't inherit from earlier insns
6525 until we are sure that any non-optional reloads have been allocated.
6526 The following code takes advantage of the fact that optional reloads
6527 are at the end of reload_order. */
6528 if (rld[r].optional != 0)
6529 for (i = 0; i < j; i++)
6530 if ((rld[reload_order[i]].out != 0
6531 || rld[reload_order[i]].in != 0
6532 || rld[reload_order[i]].secondary_p)
6533 && ! rld[reload_order[i]].optional
6534 && rld[reload_order[i]].reg_rtx == 0)
6535 allocate_reload_reg (chain, reload_order[i], 0);
6536 #endif
6538 /* First see if this pseudo is already available as reloaded
6539 for a previous insn. We cannot try to inherit for reloads
6540 that are smaller than the maximum number of registers needed
6541 for groups unless the register we would allocate cannot be used
6542 for the groups.
6544 We could check here to see if this is a secondary reload for
6545 an object that is already in a register of the desired class.
6546 This would avoid the need for the secondary reload register.
6547 But this is complex because we can't easily determine what
6548 objects might want to be loaded via this reload. So let a
6549 register be allocated here. In `emit_reload_insns' we suppress
6550 one of the loads in the case described above. */
6552 if (inheritance)
6554 int byte = 0;
6555 int regno = -1;
6556 enum machine_mode mode = VOIDmode;
6557 rtx subreg = NULL_RTX;
6559 if (rld[r].in == 0)
6561 else if (REG_P (rld[r].in))
6563 regno = REGNO (rld[r].in);
6564 mode = GET_MODE (rld[r].in);
6566 else if (REG_P (rld[r].in_reg))
6568 regno = REGNO (rld[r].in_reg);
6569 mode = GET_MODE (rld[r].in_reg);
6571 else if (GET_CODE (rld[r].in_reg) == SUBREG
6572 && REG_P (SUBREG_REG (rld[r].in_reg)))
6574 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6575 if (regno < FIRST_PSEUDO_REGISTER)
6576 regno = subreg_regno (rld[r].in_reg);
6577 else
6579 subreg = rld[r].in_reg;
6580 byte = SUBREG_BYTE (subreg);
6582 mode = GET_MODE (rld[r].in_reg);
6584 #ifdef AUTO_INC_DEC
6585 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6586 && REG_P (XEXP (rld[r].in_reg, 0)))
6588 regno = REGNO (XEXP (rld[r].in_reg, 0));
6589 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6590 rld[r].out = rld[r].in;
6592 #endif
6593 #if 0
6594 /* This won't work, since REGNO can be a pseudo reg number.
6595 Also, it takes much more hair to keep track of all the things
6596 that can invalidate an inherited reload of part of a pseudoreg. */
6597 else if (GET_CODE (rld[r].in) == SUBREG
6598 && REG_P (SUBREG_REG (rld[r].in)))
6599 regno = subreg_regno (rld[r].in);
6600 #endif
6602 if (regno >= 0
6603 && reg_last_reload_reg[regno] != 0
6604 && (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno]))
6605 >= GET_MODE_SIZE (mode) + byte)
6606 #ifdef CANNOT_CHANGE_MODE_CLASS
6607 /* Verify that the register it's in can be used in
6608 mode MODE. */
6609 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6610 GET_MODE (reg_last_reload_reg[regno]),
6611 mode)
6612 #endif
6615 enum reg_class rclass = rld[r].rclass, last_class;
6616 rtx last_reg = reg_last_reload_reg[regno];
6618 i = REGNO (last_reg);
6619 byte = compute_reload_subreg_offset (mode,
6620 subreg,
6621 GET_MODE (last_reg));
6622 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6623 last_class = REGNO_REG_CLASS (i);
6625 if (reg_reloaded_contents[i] == regno
6626 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6627 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6628 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6629 /* Even if we can't use this register as a reload
6630 register, we might use it for reload_override_in,
6631 if copying it to the desired class is cheap
6632 enough. */
6633 || ((register_move_cost (mode, last_class, rclass)
6634 < memory_move_cost (mode, rclass, true))
6635 && (secondary_reload_class (1, rclass, mode,
6636 last_reg)
6637 == NO_REGS)
6638 #ifdef SECONDARY_MEMORY_NEEDED
6639 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6640 mode)
6641 #endif
6644 && (rld[r].nregs == max_group_size
6645 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6647 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6648 rld[r].when_needed, rld[r].in,
6649 const0_rtx, r, 1))
6651 /* If a group is needed, verify that all the subsequent
6652 registers still have their values intact. */
6653 int nr = hard_regno_nregs[i][rld[r].mode];
6654 int k;
6656 for (k = 1; k < nr; k++)
6657 if (reg_reloaded_contents[i + k] != regno
6658 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6659 break;
6661 if (k == nr)
6663 int i1;
6664 int bad_for_class;
6666 last_reg = (GET_MODE (last_reg) == mode
6667 ? last_reg : gen_rtx_REG (mode, i));
6669 bad_for_class = 0;
6670 for (k = 0; k < nr; k++)
6671 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6672 i+k);
6674 /* We found a register that contains the
6675 value we need. If this register is the
6676 same as an `earlyclobber' operand of the
6677 current insn, just mark it as a place to
6678 reload from since we can't use it as the
6679 reload register itself. */
6681 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6682 if (reg_overlap_mentioned_for_reload_p
6683 (reg_last_reload_reg[regno],
6684 reload_earlyclobbers[i1]))
6685 break;
6687 if (i1 != n_earlyclobbers
6688 || ! (free_for_value_p (i, rld[r].mode,
6689 rld[r].opnum,
6690 rld[r].when_needed, rld[r].in,
6691 rld[r].out, r, 1))
6692 /* Don't use it if we'd clobber a pseudo reg. */
6693 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6694 && rld[r].out
6695 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6696 /* Don't clobber the frame pointer. */
6697 || (i == HARD_FRAME_POINTER_REGNUM
6698 && frame_pointer_needed
6699 && rld[r].out)
6700 /* Don't really use the inherited spill reg
6701 if we need it wider than we've got it. */
6702 || (GET_MODE_SIZE (rld[r].mode)
6703 > GET_MODE_SIZE (mode))
6704 || bad_for_class
6706 /* If find_reloads chose reload_out as reload
6707 register, stay with it - that leaves the
6708 inherited register for subsequent reloads. */
6709 || (rld[r].out && rld[r].reg_rtx
6710 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6712 if (! rld[r].optional)
6714 reload_override_in[r] = last_reg;
6715 reload_inheritance_insn[r]
6716 = reg_reloaded_insn[i];
6719 else
6721 int k;
6722 /* We can use this as a reload reg. */
6723 /* Mark the register as in use for this part of
6724 the insn. */
6725 mark_reload_reg_in_use (i,
6726 rld[r].opnum,
6727 rld[r].when_needed,
6728 rld[r].mode);
6729 rld[r].reg_rtx = last_reg;
6730 reload_inherited[r] = 1;
6731 reload_inheritance_insn[r]
6732 = reg_reloaded_insn[i];
6733 reload_spill_index[r] = i;
6734 for (k = 0; k < nr; k++)
6735 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6736 i + k);
6743 /* Here's another way to see if the value is already lying around. */
6744 if (inheritance
6745 && rld[r].in != 0
6746 && ! reload_inherited[r]
6747 && rld[r].out == 0
6748 && (CONSTANT_P (rld[r].in)
6749 || GET_CODE (rld[r].in) == PLUS
6750 || REG_P (rld[r].in)
6751 || MEM_P (rld[r].in))
6752 && (rld[r].nregs == max_group_size
6753 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6754 search_equiv = rld[r].in;
6756 if (search_equiv)
6758 rtx equiv
6759 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6760 -1, NULL, 0, rld[r].mode);
6761 int regno = 0;
6763 if (equiv != 0)
6765 if (REG_P (equiv))
6766 regno = REGNO (equiv);
6767 else
6769 /* This must be a SUBREG of a hard register.
6770 Make a new REG since this might be used in an
6771 address and not all machines support SUBREGs
6772 there. */
6773 gcc_assert (GET_CODE (equiv) == SUBREG);
6774 regno = subreg_regno (equiv);
6775 equiv = gen_rtx_REG (rld[r].mode, regno);
6776 /* If we choose EQUIV as the reload register, but the
6777 loop below decides to cancel the inheritance, we'll
6778 end up reloading EQUIV in rld[r].mode, not the mode
6779 it had originally. That isn't safe when EQUIV isn't
6780 available as a spill register since its value might
6781 still be live at this point. */
6782 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6783 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6784 equiv = 0;
6788 /* If we found a spill reg, reject it unless it is free
6789 and of the desired class. */
6790 if (equiv != 0)
6792 int regs_used = 0;
6793 int bad_for_class = 0;
6794 int max_regno = regno + rld[r].nregs;
6796 for (i = regno; i < max_regno; i++)
6798 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6800 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6804 if ((regs_used
6805 && ! free_for_value_p (regno, rld[r].mode,
6806 rld[r].opnum, rld[r].when_needed,
6807 rld[r].in, rld[r].out, r, 1))
6808 || bad_for_class)
6809 equiv = 0;
6812 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6813 equiv = 0;
6815 /* We found a register that contains the value we need.
6816 If this register is the same as an `earlyclobber' operand
6817 of the current insn, just mark it as a place to reload from
6818 since we can't use it as the reload register itself. */
6820 if (equiv != 0)
6821 for (i = 0; i < n_earlyclobbers; i++)
6822 if (reg_overlap_mentioned_for_reload_p (equiv,
6823 reload_earlyclobbers[i]))
6825 if (! rld[r].optional)
6826 reload_override_in[r] = equiv;
6827 equiv = 0;
6828 break;
6831 /* If the equiv register we have found is explicitly clobbered
6832 in the current insn, it depends on the reload type if we
6833 can use it, use it for reload_override_in, or not at all.
6834 In particular, we then can't use EQUIV for a
6835 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6837 if (equiv != 0)
6839 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6840 switch (rld[r].when_needed)
6842 case RELOAD_FOR_OTHER_ADDRESS:
6843 case RELOAD_FOR_INPADDR_ADDRESS:
6844 case RELOAD_FOR_INPUT_ADDRESS:
6845 case RELOAD_FOR_OPADDR_ADDR:
6846 break;
6847 case RELOAD_OTHER:
6848 case RELOAD_FOR_INPUT:
6849 case RELOAD_FOR_OPERAND_ADDRESS:
6850 if (! rld[r].optional)
6851 reload_override_in[r] = equiv;
6852 /* Fall through. */
6853 default:
6854 equiv = 0;
6855 break;
6857 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6858 switch (rld[r].when_needed)
6860 case RELOAD_FOR_OTHER_ADDRESS:
6861 case RELOAD_FOR_INPADDR_ADDRESS:
6862 case RELOAD_FOR_INPUT_ADDRESS:
6863 case RELOAD_FOR_OPADDR_ADDR:
6864 case RELOAD_FOR_OPERAND_ADDRESS:
6865 case RELOAD_FOR_INPUT:
6866 break;
6867 case RELOAD_OTHER:
6868 if (! rld[r].optional)
6869 reload_override_in[r] = equiv;
6870 /* Fall through. */
6871 default:
6872 equiv = 0;
6873 break;
6877 /* If we found an equivalent reg, say no code need be generated
6878 to load it, and use it as our reload reg. */
6879 if (equiv != 0
6880 && (regno != HARD_FRAME_POINTER_REGNUM
6881 || !frame_pointer_needed))
6883 int nr = hard_regno_nregs[regno][rld[r].mode];
6884 int k;
6885 rld[r].reg_rtx = equiv;
6886 reload_spill_index[r] = regno;
6887 reload_inherited[r] = 1;
6889 /* If reg_reloaded_valid is not set for this register,
6890 there might be a stale spill_reg_store lying around.
6891 We must clear it, since otherwise emit_reload_insns
6892 might delete the store. */
6893 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6894 spill_reg_store[regno] = NULL_RTX;
6895 /* If any of the hard registers in EQUIV are spill
6896 registers, mark them as in use for this insn. */
6897 for (k = 0; k < nr; k++)
6899 i = spill_reg_order[regno + k];
6900 if (i >= 0)
6902 mark_reload_reg_in_use (regno, rld[r].opnum,
6903 rld[r].when_needed,
6904 rld[r].mode);
6905 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6906 regno + k);
6912 /* If we found a register to use already, or if this is an optional
6913 reload, we are done. */
6914 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6915 continue;
6917 #if 0
6918 /* No longer needed for correct operation. Might or might
6919 not give better code on the average. Want to experiment? */
6921 /* See if there is a later reload that has a class different from our
6922 class that intersects our class or that requires less register
6923 than our reload. If so, we must allocate a register to this
6924 reload now, since that reload might inherit a previous reload
6925 and take the only available register in our class. Don't do this
6926 for optional reloads since they will force all previous reloads
6927 to be allocated. Also don't do this for reloads that have been
6928 turned off. */
6930 for (i = j + 1; i < n_reloads; i++)
6932 int s = reload_order[i];
6934 if ((rld[s].in == 0 && rld[s].out == 0
6935 && ! rld[s].secondary_p)
6936 || rld[s].optional)
6937 continue;
6939 if ((rld[s].rclass != rld[r].rclass
6940 && reg_classes_intersect_p (rld[r].rclass,
6941 rld[s].rclass))
6942 || rld[s].nregs < rld[r].nregs)
6943 break;
6946 if (i == n_reloads)
6947 continue;
6949 allocate_reload_reg (chain, r, j == n_reloads - 1);
6950 #endif
6953 /* Now allocate reload registers for anything non-optional that
6954 didn't get one yet. */
6955 for (j = 0; j < n_reloads; j++)
6957 int r = reload_order[j];
6959 /* Ignore reloads that got marked inoperative. */
6960 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6961 continue;
6963 /* Skip reloads that already have a register allocated or are
6964 optional. */
6965 if (rld[r].reg_rtx != 0 || rld[r].optional)
6966 continue;
6968 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6969 break;
6972 /* If that loop got all the way, we have won. */
6973 if (j == n_reloads)
6975 win = 1;
6976 break;
6979 /* Loop around and try without any inheritance. */
6982 if (! win)
6984 /* First undo everything done by the failed attempt
6985 to allocate with inheritance. */
6986 choose_reload_regs_init (chain, save_reload_reg_rtx);
6988 /* Some sanity tests to verify that the reloads found in the first
6989 pass are identical to the ones we have now. */
6990 gcc_assert (chain->n_reloads == n_reloads);
6992 for (i = 0; i < n_reloads; i++)
6994 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6995 continue;
6996 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6997 for (j = 0; j < n_spills; j++)
6998 if (spill_regs[j] == chain->rld[i].regno)
6999 if (! set_reload_reg (j, i))
7000 failed_reload (chain->insn, i);
7004 /* If we thought we could inherit a reload, because it seemed that
7005 nothing else wanted the same reload register earlier in the insn,
7006 verify that assumption, now that all reloads have been assigned.
7007 Likewise for reloads where reload_override_in has been set. */
7009 /* If doing expensive optimizations, do one preliminary pass that doesn't
7010 cancel any inheritance, but removes reloads that have been needed only
7011 for reloads that we know can be inherited. */
7012 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
7014 for (j = 0; j < n_reloads; j++)
7016 int r = reload_order[j];
7017 rtx check_reg;
7018 #ifdef SECONDARY_MEMORY_NEEDED
7019 rtx tem;
7020 #endif
7021 if (reload_inherited[r] && rld[r].reg_rtx)
7022 check_reg = rld[r].reg_rtx;
7023 else if (reload_override_in[r]
7024 && (REG_P (reload_override_in[r])
7025 || GET_CODE (reload_override_in[r]) == SUBREG))
7026 check_reg = reload_override_in[r];
7027 else
7028 continue;
7029 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
7030 rld[r].opnum, rld[r].when_needed, rld[r].in,
7031 (reload_inherited[r]
7032 ? rld[r].out : const0_rtx),
7033 r, 1))
7035 if (pass)
7036 continue;
7037 reload_inherited[r] = 0;
7038 reload_override_in[r] = 0;
7040 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
7041 reload_override_in, then we do not need its related
7042 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
7043 likewise for other reload types.
7044 We handle this by removing a reload when its only replacement
7045 is mentioned in reload_in of the reload we are going to inherit.
7046 A special case are auto_inc expressions; even if the input is
7047 inherited, we still need the address for the output. We can
7048 recognize them because they have RELOAD_OUT set to RELOAD_IN.
7049 If we succeeded removing some reload and we are doing a preliminary
7050 pass just to remove such reloads, make another pass, since the
7051 removal of one reload might allow us to inherit another one. */
7052 else if (rld[r].in
7053 && rld[r].out != rld[r].in
7054 && remove_address_replacements (rld[r].in))
7056 if (pass)
7057 pass = 2;
7059 #ifdef SECONDARY_MEMORY_NEEDED
7060 /* If we needed a memory location for the reload, we also have to
7061 remove its related reloads. */
7062 else if (rld[r].in
7063 && rld[r].out != rld[r].in
7064 && (tem = replaced_subreg (rld[r].in), REG_P (tem))
7065 && REGNO (tem) < FIRST_PSEUDO_REGISTER
7066 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem)),
7067 rld[r].rclass, rld[r].inmode)
7068 && remove_address_replacements
7069 (get_secondary_mem (tem, rld[r].inmode, rld[r].opnum,
7070 rld[r].when_needed)))
7072 if (pass)
7073 pass = 2;
7075 #endif
7079 /* Now that reload_override_in is known valid,
7080 actually override reload_in. */
7081 for (j = 0; j < n_reloads; j++)
7082 if (reload_override_in[j])
7083 rld[j].in = reload_override_in[j];
7085 /* If this reload won't be done because it has been canceled or is
7086 optional and not inherited, clear reload_reg_rtx so other
7087 routines (such as subst_reloads) don't get confused. */
7088 for (j = 0; j < n_reloads; j++)
7089 if (rld[j].reg_rtx != 0
7090 && ((rld[j].optional && ! reload_inherited[j])
7091 || (rld[j].in == 0 && rld[j].out == 0
7092 && ! rld[j].secondary_p)))
7094 int regno = true_regnum (rld[j].reg_rtx);
7096 if (spill_reg_order[regno] >= 0)
7097 clear_reload_reg_in_use (regno, rld[j].opnum,
7098 rld[j].when_needed, rld[j].mode);
7099 rld[j].reg_rtx = 0;
7100 reload_spill_index[j] = -1;
7103 /* Record which pseudos and which spill regs have output reloads. */
7104 for (j = 0; j < n_reloads; j++)
7106 int r = reload_order[j];
7108 i = reload_spill_index[r];
7110 /* I is nonneg if this reload uses a register.
7111 If rld[r].reg_rtx is 0, this is an optional reload
7112 that we opted to ignore. */
7113 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
7114 && rld[r].reg_rtx != 0)
7116 int nregno = REGNO (rld[r].out_reg);
7117 int nr = 1;
7119 if (nregno < FIRST_PSEUDO_REGISTER)
7120 nr = hard_regno_nregs[nregno][rld[r].mode];
7122 while (--nr >= 0)
7123 SET_REGNO_REG_SET (&reg_has_output_reload,
7124 nregno + nr);
7126 if (i >= 0)
7127 add_to_hard_reg_set (&reg_is_output_reload, rld[r].mode, i);
7129 gcc_assert (rld[r].when_needed == RELOAD_OTHER
7130 || rld[r].when_needed == RELOAD_FOR_OUTPUT
7131 || rld[r].when_needed == RELOAD_FOR_INSN);
7136 /* Deallocate the reload register for reload R. This is called from
7137 remove_address_replacements. */
7139 void
7140 deallocate_reload_reg (int r)
7142 int regno;
7144 if (! rld[r].reg_rtx)
7145 return;
7146 regno = true_regnum (rld[r].reg_rtx);
7147 rld[r].reg_rtx = 0;
7148 if (spill_reg_order[regno] >= 0)
7149 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
7150 rld[r].mode);
7151 reload_spill_index[r] = -1;
7154 /* These arrays are filled by emit_reload_insns and its subroutines. */
7155 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
7156 static rtx other_input_address_reload_insns = 0;
7157 static rtx other_input_reload_insns = 0;
7158 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
7159 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7160 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
7161 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
7162 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
7163 static rtx operand_reload_insns = 0;
7164 static rtx other_operand_reload_insns = 0;
7165 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
7167 /* Values to be put in spill_reg_store are put here first. Instructions
7168 must only be placed here if the associated reload register reaches
7169 the end of the instruction's reload sequence. */
7170 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
7171 static HARD_REG_SET reg_reloaded_died;
7173 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
7174 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
7175 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
7176 adjusted register, and return true. Otherwise, return false. */
7177 static bool
7178 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
7179 enum reg_class new_class,
7180 enum machine_mode new_mode)
7183 rtx reg;
7185 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
7187 unsigned regno = REGNO (reg);
7189 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
7190 continue;
7191 if (GET_MODE (reg) != new_mode)
7193 if (!HARD_REGNO_MODE_OK (regno, new_mode))
7194 continue;
7195 if (hard_regno_nregs[regno][new_mode]
7196 > hard_regno_nregs[regno][GET_MODE (reg)])
7197 continue;
7198 reg = reload_adjust_reg_for_mode (reg, new_mode);
7200 *reload_reg = reg;
7201 return true;
7203 return false;
7206 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
7207 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
7208 nonzero, if that is suitable. On success, change *RELOAD_REG to the
7209 adjusted register, and return true. Otherwise, return false. */
7210 static bool
7211 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
7212 enum insn_code icode)
7215 enum reg_class new_class = scratch_reload_class (icode);
7216 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
7218 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
7219 new_class, new_mode);
7222 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
7223 has the number J. OLD contains the value to be used as input. */
7225 static void
7226 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
7227 rtx old, int j)
7229 rtx insn = chain->insn;
7230 rtx reloadreg;
7231 rtx oldequiv_reg = 0;
7232 rtx oldequiv = 0;
7233 int special = 0;
7234 enum machine_mode mode;
7235 rtx *where;
7237 /* delete_output_reload is only invoked properly if old contains
7238 the original pseudo register. Since this is replaced with a
7239 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
7240 find the pseudo in RELOAD_IN_REG. */
7241 if (reload_override_in[j]
7242 && REG_P (rl->in_reg))
7244 oldequiv = old;
7245 old = rl->in_reg;
7247 if (oldequiv == 0)
7248 oldequiv = old;
7249 else if (REG_P (oldequiv))
7250 oldequiv_reg = oldequiv;
7251 else if (GET_CODE (oldequiv) == SUBREG)
7252 oldequiv_reg = SUBREG_REG (oldequiv);
7254 reloadreg = reload_reg_rtx_for_input[j];
7255 mode = GET_MODE (reloadreg);
7257 /* If we are reloading from a register that was recently stored in
7258 with an output-reload, see if we can prove there was
7259 actually no need to store the old value in it. */
7261 if (optimize && REG_P (oldequiv)
7262 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
7263 && spill_reg_store[REGNO (oldequiv)]
7264 && REG_P (old)
7265 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
7266 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
7267 rl->out_reg)))
7268 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
7270 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
7271 OLDEQUIV. */
7273 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
7274 oldequiv = SUBREG_REG (oldequiv);
7275 if (GET_MODE (oldequiv) != VOIDmode
7276 && mode != GET_MODE (oldequiv))
7277 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
7279 /* Switch to the right place to emit the reload insns. */
7280 switch (rl->when_needed)
7282 case RELOAD_OTHER:
7283 where = &other_input_reload_insns;
7284 break;
7285 case RELOAD_FOR_INPUT:
7286 where = &input_reload_insns[rl->opnum];
7287 break;
7288 case RELOAD_FOR_INPUT_ADDRESS:
7289 where = &input_address_reload_insns[rl->opnum];
7290 break;
7291 case RELOAD_FOR_INPADDR_ADDRESS:
7292 where = &inpaddr_address_reload_insns[rl->opnum];
7293 break;
7294 case RELOAD_FOR_OUTPUT_ADDRESS:
7295 where = &output_address_reload_insns[rl->opnum];
7296 break;
7297 case RELOAD_FOR_OUTADDR_ADDRESS:
7298 where = &outaddr_address_reload_insns[rl->opnum];
7299 break;
7300 case RELOAD_FOR_OPERAND_ADDRESS:
7301 where = &operand_reload_insns;
7302 break;
7303 case RELOAD_FOR_OPADDR_ADDR:
7304 where = &other_operand_reload_insns;
7305 break;
7306 case RELOAD_FOR_OTHER_ADDRESS:
7307 where = &other_input_address_reload_insns;
7308 break;
7309 default:
7310 gcc_unreachable ();
7313 push_to_sequence (*where);
7315 /* Auto-increment addresses must be reloaded in a special way. */
7316 if (rl->out && ! rl->out_reg)
7318 /* We are not going to bother supporting the case where a
7319 incremented register can't be copied directly from
7320 OLDEQUIV since this seems highly unlikely. */
7321 gcc_assert (rl->secondary_in_reload < 0);
7323 if (reload_inherited[j])
7324 oldequiv = reloadreg;
7326 old = XEXP (rl->in_reg, 0);
7328 /* Prevent normal processing of this reload. */
7329 special = 1;
7330 /* Output a special code sequence for this case. */
7331 inc_for_reload (reloadreg, oldequiv, rl->out, rl->inc);
7334 /* If we are reloading a pseudo-register that was set by the previous
7335 insn, see if we can get rid of that pseudo-register entirely
7336 by redirecting the previous insn into our reload register. */
7338 else if (optimize && REG_P (old)
7339 && REGNO (old) >= FIRST_PSEUDO_REGISTER
7340 && dead_or_set_p (insn, old)
7341 /* This is unsafe if some other reload
7342 uses the same reg first. */
7343 && ! conflicts_with_override (reloadreg)
7344 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
7345 rl->when_needed, old, rl->out, j, 0))
7347 rtx temp = PREV_INSN (insn);
7348 while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
7349 temp = PREV_INSN (temp);
7350 if (temp
7351 && NONJUMP_INSN_P (temp)
7352 && GET_CODE (PATTERN (temp)) == SET
7353 && SET_DEST (PATTERN (temp)) == old
7354 /* Make sure we can access insn_operand_constraint. */
7355 && asm_noperands (PATTERN (temp)) < 0
7356 /* This is unsafe if operand occurs more than once in current
7357 insn. Perhaps some occurrences aren't reloaded. */
7358 && count_occurrences (PATTERN (insn), old, 0) == 1)
7360 rtx old = SET_DEST (PATTERN (temp));
7361 /* Store into the reload register instead of the pseudo. */
7362 SET_DEST (PATTERN (temp)) = reloadreg;
7364 /* Verify that resulting insn is valid. */
7365 extract_insn (temp);
7366 if (constrain_operands (1))
7368 /* If the previous insn is an output reload, the source is
7369 a reload register, and its spill_reg_store entry will
7370 contain the previous destination. This is now
7371 invalid. */
7372 if (REG_P (SET_SRC (PATTERN (temp)))
7373 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7375 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7376 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7379 /* If these are the only uses of the pseudo reg,
7380 pretend for GDB it lives in the reload reg we used. */
7381 if (REG_N_DEATHS (REGNO (old)) == 1
7382 && REG_N_SETS (REGNO (old)) == 1)
7384 reg_renumber[REGNO (old)] = REGNO (reloadreg);
7385 if (ira_conflicts_p)
7386 /* Inform IRA about the change. */
7387 ira_mark_allocation_change (REGNO (old));
7388 alter_reg (REGNO (old), -1, false);
7390 special = 1;
7392 /* Adjust any debug insns between temp and insn. */
7393 while ((temp = NEXT_INSN (temp)) != insn)
7394 if (DEBUG_INSN_P (temp))
7395 replace_rtx (PATTERN (temp), old, reloadreg);
7396 else
7397 gcc_assert (NOTE_P (temp));
7399 else
7401 SET_DEST (PATTERN (temp)) = old;
7406 /* We can't do that, so output an insn to load RELOADREG. */
7408 /* If we have a secondary reload, pick up the secondary register
7409 and icode, if any. If OLDEQUIV and OLD are different or
7410 if this is an in-out reload, recompute whether or not we
7411 still need a secondary register and what the icode should
7412 be. If we still need a secondary register and the class or
7413 icode is different, go back to reloading from OLD if using
7414 OLDEQUIV means that we got the wrong type of register. We
7415 cannot have different class or icode due to an in-out reload
7416 because we don't make such reloads when both the input and
7417 output need secondary reload registers. */
7419 if (! special && rl->secondary_in_reload >= 0)
7421 rtx second_reload_reg = 0;
7422 rtx third_reload_reg = 0;
7423 int secondary_reload = rl->secondary_in_reload;
7424 rtx real_oldequiv = oldequiv;
7425 rtx real_old = old;
7426 rtx tmp;
7427 enum insn_code icode;
7428 enum insn_code tertiary_icode = CODE_FOR_nothing;
7430 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7431 and similarly for OLD.
7432 See comments in get_secondary_reload in reload.c. */
7433 /* If it is a pseudo that cannot be replaced with its
7434 equivalent MEM, we must fall back to reload_in, which
7435 will have all the necessary substitutions registered.
7436 Likewise for a pseudo that can't be replaced with its
7437 equivalent constant.
7439 Take extra care for subregs of such pseudos. Note that
7440 we cannot use reg_equiv_mem in this case because it is
7441 not in the right mode. */
7443 tmp = oldequiv;
7444 if (GET_CODE (tmp) == SUBREG)
7445 tmp = SUBREG_REG (tmp);
7446 if (REG_P (tmp)
7447 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7448 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7449 || reg_equiv_constant (REGNO (tmp)) != 0))
7451 if (! reg_equiv_mem (REGNO (tmp))
7452 || num_not_at_initial_offset
7453 || GET_CODE (oldequiv) == SUBREG)
7454 real_oldequiv = rl->in;
7455 else
7456 real_oldequiv = reg_equiv_mem (REGNO (tmp));
7459 tmp = old;
7460 if (GET_CODE (tmp) == SUBREG)
7461 tmp = SUBREG_REG (tmp);
7462 if (REG_P (tmp)
7463 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7464 && (reg_equiv_memory_loc (REGNO (tmp)) != 0
7465 || reg_equiv_constant (REGNO (tmp)) != 0))
7467 if (! reg_equiv_mem (REGNO (tmp))
7468 || num_not_at_initial_offset
7469 || GET_CODE (old) == SUBREG)
7470 real_old = rl->in;
7471 else
7472 real_old = reg_equiv_mem (REGNO (tmp));
7475 second_reload_reg = rld[secondary_reload].reg_rtx;
7476 if (rld[secondary_reload].secondary_in_reload >= 0)
7478 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7480 third_reload_reg = rld[tertiary_reload].reg_rtx;
7481 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7482 /* We'd have to add more code for quartary reloads. */
7483 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7485 icode = rl->secondary_in_icode;
7487 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7488 || (rl->in != 0 && rl->out != 0))
7490 secondary_reload_info sri, sri2;
7491 enum reg_class new_class, new_t_class;
7493 sri.icode = CODE_FOR_nothing;
7494 sri.prev_sri = NULL;
7495 new_class
7496 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7497 rl->rclass, mode,
7498 &sri);
7500 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7501 second_reload_reg = 0;
7502 else if (new_class == NO_REGS)
7504 if (reload_adjust_reg_for_icode (&second_reload_reg,
7505 third_reload_reg,
7506 (enum insn_code) sri.icode))
7508 icode = (enum insn_code) sri.icode;
7509 third_reload_reg = 0;
7511 else
7513 oldequiv = old;
7514 real_oldequiv = real_old;
7517 else if (sri.icode != CODE_FOR_nothing)
7518 /* We currently lack a way to express this in reloads. */
7519 gcc_unreachable ();
7520 else
7522 sri2.icode = CODE_FOR_nothing;
7523 sri2.prev_sri = &sri;
7524 new_t_class
7525 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv,
7526 new_class, mode,
7527 &sri);
7528 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7530 if (reload_adjust_reg_for_temp (&second_reload_reg,
7531 third_reload_reg,
7532 new_class, mode))
7534 third_reload_reg = 0;
7535 tertiary_icode = (enum insn_code) sri2.icode;
7537 else
7539 oldequiv = old;
7540 real_oldequiv = real_old;
7543 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7545 rtx intermediate = second_reload_reg;
7547 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7548 new_class, mode)
7549 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7550 ((enum insn_code)
7551 sri2.icode)))
7553 second_reload_reg = intermediate;
7554 tertiary_icode = (enum insn_code) sri2.icode;
7556 else
7558 oldequiv = old;
7559 real_oldequiv = real_old;
7562 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7564 rtx intermediate = second_reload_reg;
7566 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7567 new_class, mode)
7568 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7569 new_t_class, mode))
7571 second_reload_reg = intermediate;
7572 tertiary_icode = (enum insn_code) sri2.icode;
7574 else
7576 oldequiv = old;
7577 real_oldequiv = real_old;
7580 else
7582 /* This could be handled more intelligently too. */
7583 oldequiv = old;
7584 real_oldequiv = real_old;
7589 /* If we still need a secondary reload register, check
7590 to see if it is being used as a scratch or intermediate
7591 register and generate code appropriately. If we need
7592 a scratch register, use REAL_OLDEQUIV since the form of
7593 the insn may depend on the actual address if it is
7594 a MEM. */
7596 if (second_reload_reg)
7598 if (icode != CODE_FOR_nothing)
7600 /* We'd have to add extra code to handle this case. */
7601 gcc_assert (!third_reload_reg);
7603 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7604 second_reload_reg));
7605 special = 1;
7607 else
7609 /* See if we need a scratch register to load the
7610 intermediate register (a tertiary reload). */
7611 if (tertiary_icode != CODE_FOR_nothing)
7613 emit_insn ((GEN_FCN (tertiary_icode)
7614 (second_reload_reg, real_oldequiv,
7615 third_reload_reg)));
7617 else if (third_reload_reg)
7619 gen_reload (third_reload_reg, real_oldequiv,
7620 rl->opnum,
7621 rl->when_needed);
7622 gen_reload (second_reload_reg, third_reload_reg,
7623 rl->opnum,
7624 rl->when_needed);
7626 else
7627 gen_reload (second_reload_reg, real_oldequiv,
7628 rl->opnum,
7629 rl->when_needed);
7631 oldequiv = second_reload_reg;
7636 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7638 rtx real_oldequiv = oldequiv;
7640 if ((REG_P (oldequiv)
7641 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7642 && (reg_equiv_memory_loc (REGNO (oldequiv)) != 0
7643 || reg_equiv_constant (REGNO (oldequiv)) != 0))
7644 || (GET_CODE (oldequiv) == SUBREG
7645 && REG_P (SUBREG_REG (oldequiv))
7646 && (REGNO (SUBREG_REG (oldequiv))
7647 >= FIRST_PSEUDO_REGISTER)
7648 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv))) != 0)
7649 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv))) != 0)))
7650 || (CONSTANT_P (oldequiv)
7651 && (targetm.preferred_reload_class (oldequiv,
7652 REGNO_REG_CLASS (REGNO (reloadreg)))
7653 == NO_REGS)))
7654 real_oldequiv = rl->in;
7655 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7656 rl->when_needed);
7659 if (cfun->can_throw_non_call_exceptions)
7660 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7662 /* End this sequence. */
7663 *where = get_insns ();
7664 end_sequence ();
7666 /* Update reload_override_in so that delete_address_reloads_1
7667 can see the actual register usage. */
7668 if (oldequiv_reg)
7669 reload_override_in[j] = oldequiv;
7672 /* Generate insns to for the output reload RL, which is for the insn described
7673 by CHAIN and has the number J. */
7674 static void
7675 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7676 int j)
7678 rtx reloadreg;
7679 rtx insn = chain->insn;
7680 int special = 0;
7681 rtx old = rl->out;
7682 enum machine_mode mode;
7683 rtx p;
7684 rtx rl_reg_rtx;
7686 if (rl->when_needed == RELOAD_OTHER)
7687 start_sequence ();
7688 else
7689 push_to_sequence (output_reload_insns[rl->opnum]);
7691 rl_reg_rtx = reload_reg_rtx_for_output[j];
7692 mode = GET_MODE (rl_reg_rtx);
7694 reloadreg = rl_reg_rtx;
7696 /* If we need two reload regs, set RELOADREG to the intermediate
7697 one, since it will be stored into OLD. We might need a secondary
7698 register only for an input reload, so check again here. */
7700 if (rl->secondary_out_reload >= 0)
7702 rtx real_old = old;
7703 int secondary_reload = rl->secondary_out_reload;
7704 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7706 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7707 && reg_equiv_mem (REGNO (old)) != 0)
7708 real_old = reg_equiv_mem (REGNO (old));
7710 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7712 rtx second_reloadreg = reloadreg;
7713 reloadreg = rld[secondary_reload].reg_rtx;
7715 /* See if RELOADREG is to be used as a scratch register
7716 or as an intermediate register. */
7717 if (rl->secondary_out_icode != CODE_FOR_nothing)
7719 /* We'd have to add extra code to handle this case. */
7720 gcc_assert (tertiary_reload < 0);
7722 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7723 (real_old, second_reloadreg, reloadreg)));
7724 special = 1;
7726 else
7728 /* See if we need both a scratch and intermediate reload
7729 register. */
7731 enum insn_code tertiary_icode
7732 = rld[secondary_reload].secondary_out_icode;
7734 /* We'd have to add more code for quartary reloads. */
7735 gcc_assert (tertiary_reload < 0
7736 || rld[tertiary_reload].secondary_out_reload < 0);
7738 if (GET_MODE (reloadreg) != mode)
7739 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7741 if (tertiary_icode != CODE_FOR_nothing)
7743 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7745 /* Copy primary reload reg to secondary reload reg.
7746 (Note that these have been swapped above, then
7747 secondary reload reg to OLD using our insn.) */
7749 /* If REAL_OLD is a paradoxical SUBREG, remove it
7750 and try to put the opposite SUBREG on
7751 RELOADREG. */
7752 strip_paradoxical_subreg (&real_old, &reloadreg);
7754 gen_reload (reloadreg, second_reloadreg,
7755 rl->opnum, rl->when_needed);
7756 emit_insn ((GEN_FCN (tertiary_icode)
7757 (real_old, reloadreg, third_reloadreg)));
7758 special = 1;
7761 else
7763 /* Copy between the reload regs here and then to
7764 OUT later. */
7766 gen_reload (reloadreg, second_reloadreg,
7767 rl->opnum, rl->when_needed);
7768 if (tertiary_reload >= 0)
7770 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7772 gen_reload (third_reloadreg, reloadreg,
7773 rl->opnum, rl->when_needed);
7774 reloadreg = third_reloadreg;
7781 /* Output the last reload insn. */
7782 if (! special)
7784 rtx set;
7786 /* Don't output the last reload if OLD is not the dest of
7787 INSN and is in the src and is clobbered by INSN. */
7788 if (! flag_expensive_optimizations
7789 || !REG_P (old)
7790 || !(set = single_set (insn))
7791 || rtx_equal_p (old, SET_DEST (set))
7792 || !reg_mentioned_p (old, SET_SRC (set))
7793 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7794 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7795 gen_reload (old, reloadreg, rl->opnum,
7796 rl->when_needed);
7799 /* Look at all insns we emitted, just to be safe. */
7800 for (p = get_insns (); p; p = NEXT_INSN (p))
7801 if (INSN_P (p))
7803 rtx pat = PATTERN (p);
7805 /* If this output reload doesn't come from a spill reg,
7806 clear any memory of reloaded copies of the pseudo reg.
7807 If this output reload comes from a spill reg,
7808 reg_has_output_reload will make this do nothing. */
7809 note_stores (pat, forget_old_reloads_1, NULL);
7811 if (reg_mentioned_p (rl_reg_rtx, pat))
7813 rtx set = single_set (insn);
7814 if (reload_spill_index[j] < 0
7815 && set
7816 && SET_SRC (set) == rl_reg_rtx)
7818 int src = REGNO (SET_SRC (set));
7820 reload_spill_index[j] = src;
7821 SET_HARD_REG_BIT (reg_is_output_reload, src);
7822 if (find_regno_note (insn, REG_DEAD, src))
7823 SET_HARD_REG_BIT (reg_reloaded_died, src);
7825 if (HARD_REGISTER_P (rl_reg_rtx))
7827 int s = rl->secondary_out_reload;
7828 set = single_set (p);
7829 /* If this reload copies only to the secondary reload
7830 register, the secondary reload does the actual
7831 store. */
7832 if (s >= 0 && set == NULL_RTX)
7833 /* We can't tell what function the secondary reload
7834 has and where the actual store to the pseudo is
7835 made; leave new_spill_reg_store alone. */
7837 else if (s >= 0
7838 && SET_SRC (set) == rl_reg_rtx
7839 && SET_DEST (set) == rld[s].reg_rtx)
7841 /* Usually the next instruction will be the
7842 secondary reload insn; if we can confirm
7843 that it is, setting new_spill_reg_store to
7844 that insn will allow an extra optimization. */
7845 rtx s_reg = rld[s].reg_rtx;
7846 rtx next = NEXT_INSN (p);
7847 rld[s].out = rl->out;
7848 rld[s].out_reg = rl->out_reg;
7849 set = single_set (next);
7850 if (set && SET_SRC (set) == s_reg
7851 && reload_reg_rtx_reaches_end_p (s_reg, s))
7853 SET_HARD_REG_BIT (reg_is_output_reload,
7854 REGNO (s_reg));
7855 new_spill_reg_store[REGNO (s_reg)] = next;
7858 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx, j))
7859 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7864 if (rl->when_needed == RELOAD_OTHER)
7866 emit_insn (other_output_reload_insns[rl->opnum]);
7867 other_output_reload_insns[rl->opnum] = get_insns ();
7869 else
7870 output_reload_insns[rl->opnum] = get_insns ();
7872 if (cfun->can_throw_non_call_exceptions)
7873 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7875 end_sequence ();
7878 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7879 and has the number J. */
7880 static void
7881 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7883 rtx insn = chain->insn;
7884 rtx old = (rl->in && MEM_P (rl->in)
7885 ? rl->in_reg : rl->in);
7886 rtx reg_rtx = rl->reg_rtx;
7888 if (old && reg_rtx)
7890 enum machine_mode mode;
7892 /* Determine the mode to reload in.
7893 This is very tricky because we have three to choose from.
7894 There is the mode the insn operand wants (rl->inmode).
7895 There is the mode of the reload register RELOADREG.
7896 There is the intrinsic mode of the operand, which we could find
7897 by stripping some SUBREGs.
7898 It turns out that RELOADREG's mode is irrelevant:
7899 we can change that arbitrarily.
7901 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7902 then the reload reg may not support QImode moves, so use SImode.
7903 If foo is in memory due to spilling a pseudo reg, this is safe,
7904 because the QImode value is in the least significant part of a
7905 slot big enough for a SImode. If foo is some other sort of
7906 memory reference, then it is impossible to reload this case,
7907 so previous passes had better make sure this never happens.
7909 Then consider a one-word union which has SImode and one of its
7910 members is a float, being fetched as (SUBREG:SF union:SI).
7911 We must fetch that as SFmode because we could be loading into
7912 a float-only register. In this case OLD's mode is correct.
7914 Consider an immediate integer: it has VOIDmode. Here we need
7915 to get a mode from something else.
7917 In some cases, there is a fourth mode, the operand's
7918 containing mode. If the insn specifies a containing mode for
7919 this operand, it overrides all others.
7921 I am not sure whether the algorithm here is always right,
7922 but it does the right things in those cases. */
7924 mode = GET_MODE (old);
7925 if (mode == VOIDmode)
7926 mode = rl->inmode;
7928 /* We cannot use gen_lowpart_common since it can do the wrong thing
7929 when REG_RTX has a multi-word mode. Note that REG_RTX must
7930 always be a REG here. */
7931 if (GET_MODE (reg_rtx) != mode)
7932 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7934 reload_reg_rtx_for_input[j] = reg_rtx;
7936 if (old != 0
7937 /* AUTO_INC reloads need to be handled even if inherited. We got an
7938 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7939 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7940 && ! rtx_equal_p (reg_rtx, old)
7941 && reg_rtx != 0)
7942 emit_input_reload_insns (chain, rld + j, old, j);
7944 /* When inheriting a wider reload, we have a MEM in rl->in,
7945 e.g. inheriting a SImode output reload for
7946 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7947 if (optimize && reload_inherited[j] && rl->in
7948 && MEM_P (rl->in)
7949 && MEM_P (rl->in_reg)
7950 && reload_spill_index[j] >= 0
7951 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7952 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7954 /* If we are reloading a register that was recently stored in with an
7955 output-reload, see if we can prove there was
7956 actually no need to store the old value in it. */
7958 if (optimize
7959 && (reload_inherited[j] || reload_override_in[j])
7960 && reg_rtx
7961 && REG_P (reg_rtx)
7962 && spill_reg_store[REGNO (reg_rtx)] != 0
7963 #if 0
7964 /* There doesn't seem to be any reason to restrict this to pseudos
7965 and doing so loses in the case where we are copying from a
7966 register of the wrong class. */
7967 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7968 #endif
7969 /* The insn might have already some references to stackslots
7970 replaced by MEMs, while reload_out_reg still names the
7971 original pseudo. */
7972 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7973 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7974 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7977 /* Do output reloading for reload RL, which is for the insn described by
7978 CHAIN and has the number J.
7979 ??? At some point we need to support handling output reloads of
7980 JUMP_INSNs or insns that set cc0. */
7981 static void
7982 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7984 rtx note, old;
7985 rtx insn = chain->insn;
7986 /* If this is an output reload that stores something that is
7987 not loaded in this same reload, see if we can eliminate a previous
7988 store. */
7989 rtx pseudo = rl->out_reg;
7990 rtx reg_rtx = rl->reg_rtx;
7992 if (rl->out && reg_rtx)
7994 enum machine_mode mode;
7996 /* Determine the mode to reload in.
7997 See comments above (for input reloading). */
7998 mode = GET_MODE (rl->out);
7999 if (mode == VOIDmode)
8001 /* VOIDmode should never happen for an output. */
8002 if (asm_noperands (PATTERN (insn)) < 0)
8003 /* It's the compiler's fault. */
8004 fatal_insn ("VOIDmode on an output", insn);
8005 error_for_asm (insn, "output operand is constant in %<asm%>");
8006 /* Prevent crash--use something we know is valid. */
8007 mode = word_mode;
8008 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
8010 if (GET_MODE (reg_rtx) != mode)
8011 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
8013 reload_reg_rtx_for_output[j] = reg_rtx;
8015 if (pseudo
8016 && optimize
8017 && REG_P (pseudo)
8018 && ! rtx_equal_p (rl->in_reg, pseudo)
8019 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
8020 && reg_last_reload_reg[REGNO (pseudo)])
8022 int pseudo_no = REGNO (pseudo);
8023 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
8025 /* We don't need to test full validity of last_regno for
8026 inherit here; we only want to know if the store actually
8027 matches the pseudo. */
8028 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
8029 && reg_reloaded_contents[last_regno] == pseudo_no
8030 && spill_reg_store[last_regno]
8031 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
8032 delete_output_reload (insn, j, last_regno, reg_rtx);
8035 old = rl->out_reg;
8036 if (old == 0
8037 || reg_rtx == 0
8038 || rtx_equal_p (old, reg_rtx))
8039 return;
8041 /* An output operand that dies right away does need a reload,
8042 but need not be copied from it. Show the new location in the
8043 REG_UNUSED note. */
8044 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
8045 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
8047 XEXP (note, 0) = reg_rtx;
8048 return;
8050 /* Likewise for a SUBREG of an operand that dies. */
8051 else if (GET_CODE (old) == SUBREG
8052 && REG_P (SUBREG_REG (old))
8053 && 0 != (note = find_reg_note (insn, REG_UNUSED,
8054 SUBREG_REG (old))))
8056 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
8057 return;
8059 else if (GET_CODE (old) == SCRATCH)
8060 /* If we aren't optimizing, there won't be a REG_UNUSED note,
8061 but we don't want to make an output reload. */
8062 return;
8064 /* If is a JUMP_INSN, we can't support output reloads yet. */
8065 gcc_assert (NONJUMP_INSN_P (insn));
8067 emit_output_reload_insns (chain, rld + j, j);
8070 /* A reload copies values of MODE from register SRC to register DEST.
8071 Return true if it can be treated for inheritance purposes like a
8072 group of reloads, each one reloading a single hard register. The
8073 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
8074 occupy the same number of hard registers. */
8076 static bool
8077 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
8078 int src ATTRIBUTE_UNUSED,
8079 enum machine_mode mode ATTRIBUTE_UNUSED)
8081 #ifdef CANNOT_CHANGE_MODE_CLASS
8082 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
8083 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
8084 #else
8085 return true;
8086 #endif
8089 /* Output insns to reload values in and out of the chosen reload regs. */
8091 static void
8092 emit_reload_insns (struct insn_chain *chain)
8094 rtx insn = chain->insn;
8096 int j;
8098 CLEAR_HARD_REG_SET (reg_reloaded_died);
8100 for (j = 0; j < reload_n_operands; j++)
8101 input_reload_insns[j] = input_address_reload_insns[j]
8102 = inpaddr_address_reload_insns[j]
8103 = output_reload_insns[j] = output_address_reload_insns[j]
8104 = outaddr_address_reload_insns[j]
8105 = other_output_reload_insns[j] = 0;
8106 other_input_address_reload_insns = 0;
8107 other_input_reload_insns = 0;
8108 operand_reload_insns = 0;
8109 other_operand_reload_insns = 0;
8111 /* Dump reloads into the dump file. */
8112 if (dump_file)
8114 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
8115 debug_reload_to_stream (dump_file);
8118 for (j = 0; j < n_reloads; j++)
8119 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
8121 unsigned int i;
8123 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
8124 new_spill_reg_store[i] = 0;
8127 /* Now output the instructions to copy the data into and out of the
8128 reload registers. Do these in the order that the reloads were reported,
8129 since reloads of base and index registers precede reloads of operands
8130 and the operands may need the base and index registers reloaded. */
8132 for (j = 0; j < n_reloads; j++)
8134 do_input_reload (chain, rld + j, j);
8135 do_output_reload (chain, rld + j, j);
8138 /* Now write all the insns we made for reloads in the order expected by
8139 the allocation functions. Prior to the insn being reloaded, we write
8140 the following reloads:
8142 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
8144 RELOAD_OTHER reloads.
8146 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
8147 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
8148 RELOAD_FOR_INPUT reload for the operand.
8150 RELOAD_FOR_OPADDR_ADDRS reloads.
8152 RELOAD_FOR_OPERAND_ADDRESS reloads.
8154 After the insn being reloaded, we write the following:
8156 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
8157 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
8158 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
8159 reloads for the operand. The RELOAD_OTHER output reloads are
8160 output in descending order by reload number. */
8162 emit_insn_before (other_input_address_reload_insns, insn);
8163 emit_insn_before (other_input_reload_insns, insn);
8165 for (j = 0; j < reload_n_operands; j++)
8167 emit_insn_before (inpaddr_address_reload_insns[j], insn);
8168 emit_insn_before (input_address_reload_insns[j], insn);
8169 emit_insn_before (input_reload_insns[j], insn);
8172 emit_insn_before (other_operand_reload_insns, insn);
8173 emit_insn_before (operand_reload_insns, insn);
8175 for (j = 0; j < reload_n_operands; j++)
8177 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
8178 x = emit_insn_after (output_address_reload_insns[j], x);
8179 x = emit_insn_after (output_reload_insns[j], x);
8180 emit_insn_after (other_output_reload_insns[j], x);
8183 /* For all the spill regs newly reloaded in this instruction,
8184 record what they were reloaded from, so subsequent instructions
8185 can inherit the reloads.
8187 Update spill_reg_store for the reloads of this insn.
8188 Copy the elements that were updated in the loop above. */
8190 for (j = 0; j < n_reloads; j++)
8192 int r = reload_order[j];
8193 int i = reload_spill_index[r];
8195 /* If this is a non-inherited input reload from a pseudo, we must
8196 clear any memory of a previous store to the same pseudo. Only do
8197 something if there will not be an output reload for the pseudo
8198 being reloaded. */
8199 if (rld[r].in_reg != 0
8200 && ! (reload_inherited[r] || reload_override_in[r]))
8202 rtx reg = rld[r].in_reg;
8204 if (GET_CODE (reg) == SUBREG)
8205 reg = SUBREG_REG (reg);
8207 if (REG_P (reg)
8208 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
8209 && !REGNO_REG_SET_P (&reg_has_output_reload, REGNO (reg)))
8211 int nregno = REGNO (reg);
8213 if (reg_last_reload_reg[nregno])
8215 int last_regno = REGNO (reg_last_reload_reg[nregno]);
8217 if (reg_reloaded_contents[last_regno] == nregno)
8218 spill_reg_store[last_regno] = 0;
8223 /* I is nonneg if this reload used a register.
8224 If rld[r].reg_rtx is 0, this is an optional reload
8225 that we opted to ignore. */
8227 if (i >= 0 && rld[r].reg_rtx != 0)
8229 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
8230 int k;
8232 /* For a multi register reload, we need to check if all or part
8233 of the value lives to the end. */
8234 for (k = 0; k < nr; k++)
8235 if (reload_reg_reaches_end_p (i + k, r))
8236 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
8238 /* Maybe the spill reg contains a copy of reload_out. */
8239 if (rld[r].out != 0
8240 && (REG_P (rld[r].out)
8241 || (rld[r].out_reg
8242 ? REG_P (rld[r].out_reg)
8243 /* The reload value is an auto-modification of
8244 some kind. For PRE_INC, POST_INC, PRE_DEC
8245 and POST_DEC, we record an equivalence
8246 between the reload register and the operand
8247 on the optimistic assumption that we can make
8248 the equivalence hold. reload_as_needed must
8249 then either make it hold or invalidate the
8250 equivalence.
8252 PRE_MODIFY and POST_MODIFY addresses are reloaded
8253 somewhat differently, and allowing them here leads
8254 to problems. */
8255 : (GET_CODE (rld[r].out) != POST_MODIFY
8256 && GET_CODE (rld[r].out) != PRE_MODIFY))))
8258 rtx reg;
8260 reg = reload_reg_rtx_for_output[r];
8261 if (reload_reg_rtx_reaches_end_p (reg, r))
8263 enum machine_mode mode = GET_MODE (reg);
8264 int regno = REGNO (reg);
8265 int nregs = hard_regno_nregs[regno][mode];
8266 rtx out = (REG_P (rld[r].out)
8267 ? rld[r].out
8268 : rld[r].out_reg
8269 ? rld[r].out_reg
8270 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
8271 int out_regno = REGNO (out);
8272 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
8273 : hard_regno_nregs[out_regno][mode]);
8274 bool piecemeal;
8276 spill_reg_store[regno] = new_spill_reg_store[regno];
8277 spill_reg_stored_to[regno] = out;
8278 reg_last_reload_reg[out_regno] = reg;
8280 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
8281 && nregs == out_nregs
8282 && inherit_piecemeal_p (out_regno, regno, mode));
8284 /* If OUT_REGNO is a hard register, it may occupy more than
8285 one register. If it does, say what is in the
8286 rest of the registers assuming that both registers
8287 agree on how many words the object takes. If not,
8288 invalidate the subsequent registers. */
8290 if (HARD_REGISTER_NUM_P (out_regno))
8291 for (k = 1; k < out_nregs; k++)
8292 reg_last_reload_reg[out_regno + k]
8293 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8295 /* Now do the inverse operation. */
8296 for (k = 0; k < nregs; k++)
8298 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8299 reg_reloaded_contents[regno + k]
8300 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
8301 ? out_regno
8302 : out_regno + k);
8303 reg_reloaded_insn[regno + k] = insn;
8304 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8305 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8306 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8307 regno + k);
8308 else
8309 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8310 regno + k);
8314 /* Maybe the spill reg contains a copy of reload_in. Only do
8315 something if there will not be an output reload for
8316 the register being reloaded. */
8317 else if (rld[r].out_reg == 0
8318 && rld[r].in != 0
8319 && ((REG_P (rld[r].in)
8320 && !HARD_REGISTER_P (rld[r].in)
8321 && !REGNO_REG_SET_P (&reg_has_output_reload,
8322 REGNO (rld[r].in)))
8323 || (REG_P (rld[r].in_reg)
8324 && !REGNO_REG_SET_P (&reg_has_output_reload,
8325 REGNO (rld[r].in_reg))))
8326 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
8328 rtx reg;
8330 reg = reload_reg_rtx_for_input[r];
8331 if (reload_reg_rtx_reaches_end_p (reg, r))
8333 enum machine_mode mode;
8334 int regno;
8335 int nregs;
8336 int in_regno;
8337 int in_nregs;
8338 rtx in;
8339 bool piecemeal;
8341 mode = GET_MODE (reg);
8342 regno = REGNO (reg);
8343 nregs = hard_regno_nregs[regno][mode];
8344 if (REG_P (rld[r].in)
8345 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
8346 in = rld[r].in;
8347 else if (REG_P (rld[r].in_reg))
8348 in = rld[r].in_reg;
8349 else
8350 in = XEXP (rld[r].in_reg, 0);
8351 in_regno = REGNO (in);
8353 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
8354 : hard_regno_nregs[in_regno][mode]);
8356 reg_last_reload_reg[in_regno] = reg;
8358 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
8359 && nregs == in_nregs
8360 && inherit_piecemeal_p (regno, in_regno, mode));
8362 if (HARD_REGISTER_NUM_P (in_regno))
8363 for (k = 1; k < in_nregs; k++)
8364 reg_last_reload_reg[in_regno + k]
8365 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
8367 /* Unless we inherited this reload, show we haven't
8368 recently done a store.
8369 Previous stores of inherited auto_inc expressions
8370 also have to be discarded. */
8371 if (! reload_inherited[r]
8372 || (rld[r].out && ! rld[r].out_reg))
8373 spill_reg_store[regno] = 0;
8375 for (k = 0; k < nregs; k++)
8377 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8378 reg_reloaded_contents[regno + k]
8379 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8380 ? in_regno
8381 : in_regno + k);
8382 reg_reloaded_insn[regno + k] = insn;
8383 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8384 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8385 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8386 regno + k);
8387 else
8388 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8389 regno + k);
8395 /* The following if-statement was #if 0'd in 1.34 (or before...).
8396 It's reenabled in 1.35 because supposedly nothing else
8397 deals with this problem. */
8399 /* If a register gets output-reloaded from a non-spill register,
8400 that invalidates any previous reloaded copy of it.
8401 But forget_old_reloads_1 won't get to see it, because
8402 it thinks only about the original insn. So invalidate it here.
8403 Also do the same thing for RELOAD_OTHER constraints where the
8404 output is discarded. */
8405 if (i < 0
8406 && ((rld[r].out != 0
8407 && (REG_P (rld[r].out)
8408 || (MEM_P (rld[r].out)
8409 && REG_P (rld[r].out_reg))))
8410 || (rld[r].out == 0 && rld[r].out_reg
8411 && REG_P (rld[r].out_reg))))
8413 rtx out = ((rld[r].out && REG_P (rld[r].out))
8414 ? rld[r].out : rld[r].out_reg);
8415 int out_regno = REGNO (out);
8416 enum machine_mode mode = GET_MODE (out);
8418 /* REG_RTX is now set or clobbered by the main instruction.
8419 As the comment above explains, forget_old_reloads_1 only
8420 sees the original instruction, and there is no guarantee
8421 that the original instruction also clobbered REG_RTX.
8422 For example, if find_reloads sees that the input side of
8423 a matched operand pair dies in this instruction, it may
8424 use the input register as the reload register.
8426 Calling forget_old_reloads_1 is a waste of effort if
8427 REG_RTX is also the output register.
8429 If we know that REG_RTX holds the value of a pseudo
8430 register, the code after the call will record that fact. */
8431 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8432 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8434 if (!HARD_REGISTER_NUM_P (out_regno))
8436 rtx src_reg, store_insn = NULL_RTX;
8438 reg_last_reload_reg[out_regno] = 0;
8440 /* If we can find a hard register that is stored, record
8441 the storing insn so that we may delete this insn with
8442 delete_output_reload. */
8443 src_reg = reload_reg_rtx_for_output[r];
8445 if (src_reg)
8447 if (reload_reg_rtx_reaches_end_p (src_reg, r))
8448 store_insn = new_spill_reg_store[REGNO (src_reg)];
8449 else
8450 src_reg = NULL_RTX;
8452 else
8454 /* If this is an optional reload, try to find the
8455 source reg from an input reload. */
8456 rtx set = single_set (insn);
8457 if (set && SET_DEST (set) == rld[r].out)
8459 int k;
8461 src_reg = SET_SRC (set);
8462 store_insn = insn;
8463 for (k = 0; k < n_reloads; k++)
8465 if (rld[k].in == src_reg)
8467 src_reg = reload_reg_rtx_for_input[k];
8468 break;
8473 if (src_reg && REG_P (src_reg)
8474 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8476 int src_regno, src_nregs, k;
8477 rtx note;
8479 gcc_assert (GET_MODE (src_reg) == mode);
8480 src_regno = REGNO (src_reg);
8481 src_nregs = hard_regno_nregs[src_regno][mode];
8482 /* The place where to find a death note varies with
8483 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8484 necessarily checked exactly in the code that moves
8485 notes, so just check both locations. */
8486 note = find_regno_note (insn, REG_DEAD, src_regno);
8487 if (! note && store_insn)
8488 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8489 for (k = 0; k < src_nregs; k++)
8491 spill_reg_store[src_regno + k] = store_insn;
8492 spill_reg_stored_to[src_regno + k] = out;
8493 reg_reloaded_contents[src_regno + k] = out_regno;
8494 reg_reloaded_insn[src_regno + k] = store_insn;
8495 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8496 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8497 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8498 mode))
8499 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8500 src_regno + k);
8501 else
8502 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8503 src_regno + k);
8504 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8505 if (note)
8506 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8507 else
8508 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8510 reg_last_reload_reg[out_regno] = src_reg;
8511 /* We have to set reg_has_output_reload here, or else
8512 forget_old_reloads_1 will clear reg_last_reload_reg
8513 right away. */
8514 SET_REGNO_REG_SET (&reg_has_output_reload,
8515 out_regno);
8518 else
8520 int k, out_nregs = hard_regno_nregs[out_regno][mode];
8522 for (k = 0; k < out_nregs; k++)
8523 reg_last_reload_reg[out_regno + k] = 0;
8527 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8530 /* Go through the motions to emit INSN and test if it is strictly valid.
8531 Return the emitted insn if valid, else return NULL. */
8533 static rtx
8534 emit_insn_if_valid_for_reload (rtx insn)
8536 rtx last = get_last_insn ();
8537 int code;
8539 insn = emit_insn (insn);
8540 code = recog_memoized (insn);
8542 if (code >= 0)
8544 extract_insn (insn);
8545 /* We want constrain operands to treat this insn strictly in its
8546 validity determination, i.e., the way it would after reload has
8547 completed. */
8548 if (constrain_operands (1))
8549 return insn;
8552 delete_insns_since (last);
8553 return NULL;
8556 /* Emit code to perform a reload from IN (which may be a reload register) to
8557 OUT (which may also be a reload register). IN or OUT is from operand
8558 OPNUM with reload type TYPE.
8560 Returns first insn emitted. */
8562 static rtx
8563 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8565 rtx last = get_last_insn ();
8566 rtx tem;
8567 #ifdef SECONDARY_MEMORY_NEEDED
8568 rtx tem1, tem2;
8569 #endif
8571 /* If IN is a paradoxical SUBREG, remove it and try to put the
8572 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8573 if (!strip_paradoxical_subreg (&in, &out))
8574 strip_paradoxical_subreg (&out, &in);
8576 /* How to do this reload can get quite tricky. Normally, we are being
8577 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8578 register that didn't get a hard register. In that case we can just
8579 call emit_move_insn.
8581 We can also be asked to reload a PLUS that adds a register or a MEM to
8582 another register, constant or MEM. This can occur during frame pointer
8583 elimination and while reloading addresses. This case is handled by
8584 trying to emit a single insn to perform the add. If it is not valid,
8585 we use a two insn sequence.
8587 Or we can be asked to reload an unary operand that was a fragment of
8588 an addressing mode, into a register. If it isn't recognized as-is,
8589 we try making the unop operand and the reload-register the same:
8590 (set reg:X (unop:X expr:Y))
8591 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8593 Finally, we could be called to handle an 'o' constraint by putting
8594 an address into a register. In that case, we first try to do this
8595 with a named pattern of "reload_load_address". If no such pattern
8596 exists, we just emit a SET insn and hope for the best (it will normally
8597 be valid on machines that use 'o').
8599 This entire process is made complex because reload will never
8600 process the insns we generate here and so we must ensure that
8601 they will fit their constraints and also by the fact that parts of
8602 IN might be being reloaded separately and replaced with spill registers.
8603 Because of this, we are, in some sense, just guessing the right approach
8604 here. The one listed above seems to work.
8606 ??? At some point, this whole thing needs to be rethought. */
8608 if (GET_CODE (in) == PLUS
8609 && (REG_P (XEXP (in, 0))
8610 || GET_CODE (XEXP (in, 0)) == SUBREG
8611 || MEM_P (XEXP (in, 0)))
8612 && (REG_P (XEXP (in, 1))
8613 || GET_CODE (XEXP (in, 1)) == SUBREG
8614 || CONSTANT_P (XEXP (in, 1))
8615 || MEM_P (XEXP (in, 1))))
8617 /* We need to compute the sum of a register or a MEM and another
8618 register, constant, or MEM, and put it into the reload
8619 register. The best possible way of doing this is if the machine
8620 has a three-operand ADD insn that accepts the required operands.
8622 The simplest approach is to try to generate such an insn and see if it
8623 is recognized and matches its constraints. If so, it can be used.
8625 It might be better not to actually emit the insn unless it is valid,
8626 but we need to pass the insn as an operand to `recog' and
8627 `extract_insn' and it is simpler to emit and then delete the insn if
8628 not valid than to dummy things up. */
8630 rtx op0, op1, tem, insn;
8631 enum insn_code code;
8633 op0 = find_replacement (&XEXP (in, 0));
8634 op1 = find_replacement (&XEXP (in, 1));
8636 /* Since constraint checking is strict, commutativity won't be
8637 checked, so we need to do that here to avoid spurious failure
8638 if the add instruction is two-address and the second operand
8639 of the add is the same as the reload reg, which is frequently
8640 the case. If the insn would be A = B + A, rearrange it so
8641 it will be A = A + B as constrain_operands expects. */
8643 if (REG_P (XEXP (in, 1))
8644 && REGNO (out) == REGNO (XEXP (in, 1)))
8645 tem = op0, op0 = op1, op1 = tem;
8647 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8648 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8650 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8651 if (insn)
8652 return insn;
8654 /* If that failed, we must use a conservative two-insn sequence.
8656 Use a move to copy one operand into the reload register. Prefer
8657 to reload a constant, MEM or pseudo since the move patterns can
8658 handle an arbitrary operand. If OP1 is not a constant, MEM or
8659 pseudo and OP1 is not a valid operand for an add instruction, then
8660 reload OP1.
8662 After reloading one of the operands into the reload register, add
8663 the reload register to the output register.
8665 If there is another way to do this for a specific machine, a
8666 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8667 we emit below. */
8669 code = optab_handler (add_optab, GET_MODE (out));
8671 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8672 || (REG_P (op1)
8673 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8674 || (code != CODE_FOR_nothing
8675 && !insn_operand_matches (code, 2, op1)))
8676 tem = op0, op0 = op1, op1 = tem;
8678 gen_reload (out, op0, opnum, type);
8680 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8681 This fixes a problem on the 32K where the stack pointer cannot
8682 be used as an operand of an add insn. */
8684 if (rtx_equal_p (op0, op1))
8685 op1 = out;
8687 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8688 if (insn)
8690 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8691 set_dst_reg_note (insn, REG_EQUIV, in, out);
8692 return insn;
8695 /* If that failed, copy the address register to the reload register.
8696 Then add the constant to the reload register. */
8698 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8699 gen_reload (out, op1, opnum, type);
8700 insn = emit_insn (gen_add2_insn (out, op0));
8701 set_dst_reg_note (insn, REG_EQUIV, in, out);
8704 #ifdef SECONDARY_MEMORY_NEEDED
8705 /* If we need a memory location to do the move, do it that way. */
8706 else if ((tem1 = replaced_subreg (in), tem2 = replaced_subreg (out),
8707 (REG_P (tem1) && REG_P (tem2)))
8708 && REGNO (tem1) < FIRST_PSEUDO_REGISTER
8709 && REGNO (tem2) < FIRST_PSEUDO_REGISTER
8710 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (tem1)),
8711 REGNO_REG_CLASS (REGNO (tem2)),
8712 GET_MODE (out)))
8714 /* Get the memory to use and rewrite both registers to its mode. */
8715 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8717 if (GET_MODE (loc) != GET_MODE (out))
8718 out = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (out));
8720 if (GET_MODE (loc) != GET_MODE (in))
8721 in = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (in));
8723 gen_reload (loc, in, opnum, type);
8724 gen_reload (out, loc, opnum, type);
8726 #endif
8727 else if (REG_P (out) && UNARY_P (in))
8729 rtx insn;
8730 rtx op1;
8731 rtx out_moded;
8732 rtx set;
8734 op1 = find_replacement (&XEXP (in, 0));
8735 if (op1 != XEXP (in, 0))
8736 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8738 /* First, try a plain SET. */
8739 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8740 if (set)
8741 return set;
8743 /* If that failed, move the inner operand to the reload
8744 register, and try the same unop with the inner expression
8745 replaced with the reload register. */
8747 if (GET_MODE (op1) != GET_MODE (out))
8748 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8749 else
8750 out_moded = out;
8752 gen_reload (out_moded, op1, opnum, type);
8754 insn
8755 = gen_rtx_SET (VOIDmode, out,
8756 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8757 out_moded));
8758 insn = emit_insn_if_valid_for_reload (insn);
8759 if (insn)
8761 set_unique_reg_note (insn, REG_EQUIV, in);
8762 return insn;
8765 fatal_insn ("failure trying to reload:", set);
8767 /* If IN is a simple operand, use gen_move_insn. */
8768 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8770 tem = emit_insn (gen_move_insn (out, in));
8771 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8772 mark_jump_label (in, tem, 0);
8775 #ifdef HAVE_reload_load_address
8776 else if (HAVE_reload_load_address)
8777 emit_insn (gen_reload_load_address (out, in));
8778 #endif
8780 /* Otherwise, just write (set OUT IN) and hope for the best. */
8781 else
8782 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8784 /* Return the first insn emitted.
8785 We can not just return get_last_insn, because there may have
8786 been multiple instructions emitted. Also note that gen_move_insn may
8787 emit more than one insn itself, so we can not assume that there is one
8788 insn emitted per emit_insn_before call. */
8790 return last ? NEXT_INSN (last) : get_insns ();
8793 /* Delete a previously made output-reload whose result we now believe
8794 is not needed. First we double-check.
8796 INSN is the insn now being processed.
8797 LAST_RELOAD_REG is the hard register number for which we want to delete
8798 the last output reload.
8799 J is the reload-number that originally used REG. The caller has made
8800 certain that reload J doesn't use REG any longer for input.
8801 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8803 static void
8804 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8806 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8807 rtx reg = spill_reg_stored_to[last_reload_reg];
8808 int k;
8809 int n_occurrences;
8810 int n_inherited = 0;
8811 rtx i1;
8812 rtx substed;
8813 unsigned regno;
8814 int nregs;
8816 /* It is possible that this reload has been only used to set another reload
8817 we eliminated earlier and thus deleted this instruction too. */
8818 if (INSN_DELETED_P (output_reload_insn))
8819 return;
8821 /* Get the raw pseudo-register referred to. */
8823 while (GET_CODE (reg) == SUBREG)
8824 reg = SUBREG_REG (reg);
8825 substed = reg_equiv_memory_loc (REGNO (reg));
8827 /* This is unsafe if the operand occurs more often in the current
8828 insn than it is inherited. */
8829 for (k = n_reloads - 1; k >= 0; k--)
8831 rtx reg2 = rld[k].in;
8832 if (! reg2)
8833 continue;
8834 if (MEM_P (reg2) || reload_override_in[k])
8835 reg2 = rld[k].in_reg;
8836 #ifdef AUTO_INC_DEC
8837 if (rld[k].out && ! rld[k].out_reg)
8838 reg2 = XEXP (rld[k].in_reg, 0);
8839 #endif
8840 while (GET_CODE (reg2) == SUBREG)
8841 reg2 = SUBREG_REG (reg2);
8842 if (rtx_equal_p (reg2, reg))
8844 if (reload_inherited[k] || reload_override_in[k] || k == j)
8845 n_inherited++;
8846 else
8847 return;
8850 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8851 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8852 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8853 reg, 0);
8854 if (substed)
8855 n_occurrences += count_occurrences (PATTERN (insn),
8856 eliminate_regs (substed, VOIDmode,
8857 NULL_RTX), 0);
8858 for (i1 = reg_equiv_alt_mem_list (REGNO (reg)); i1; i1 = XEXP (i1, 1))
8860 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8861 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8863 if (n_occurrences > n_inherited)
8864 return;
8866 regno = REGNO (reg);
8867 if (regno >= FIRST_PSEUDO_REGISTER)
8868 nregs = 1;
8869 else
8870 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
8872 /* If the pseudo-reg we are reloading is no longer referenced
8873 anywhere between the store into it and here,
8874 and we're within the same basic block, then the value can only
8875 pass through the reload reg and end up here.
8876 Otherwise, give up--return. */
8877 for (i1 = NEXT_INSN (output_reload_insn);
8878 i1 != insn; i1 = NEXT_INSN (i1))
8880 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8881 return;
8882 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8883 && refers_to_regno_p (regno, regno + nregs, PATTERN (i1), NULL))
8885 /* If this is USE in front of INSN, we only have to check that
8886 there are no more references than accounted for by inheritance. */
8887 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8889 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8890 i1 = NEXT_INSN (i1);
8892 if (n_occurrences <= n_inherited && i1 == insn)
8893 break;
8894 return;
8898 /* We will be deleting the insn. Remove the spill reg information. */
8899 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8901 spill_reg_store[last_reload_reg + k] = 0;
8902 spill_reg_stored_to[last_reload_reg + k] = 0;
8905 /* The caller has already checked that REG dies or is set in INSN.
8906 It has also checked that we are optimizing, and thus some
8907 inaccuracies in the debugging information are acceptable.
8908 So we could just delete output_reload_insn. But in some cases
8909 we can improve the debugging information without sacrificing
8910 optimization - maybe even improving the code: See if the pseudo
8911 reg has been completely replaced with reload regs. If so, delete
8912 the store insn and forget we had a stack slot for the pseudo. */
8913 if (rld[j].out != rld[j].in
8914 && REG_N_DEATHS (REGNO (reg)) == 1
8915 && REG_N_SETS (REGNO (reg)) == 1
8916 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8917 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8919 rtx i2;
8921 /* We know that it was used only between here and the beginning of
8922 the current basic block. (We also know that the last use before
8923 INSN was the output reload we are thinking of deleting, but never
8924 mind that.) Search that range; see if any ref remains. */
8925 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8927 rtx set = single_set (i2);
8929 /* Uses which just store in the pseudo don't count,
8930 since if they are the only uses, they are dead. */
8931 if (set != 0 && SET_DEST (set) == reg)
8932 continue;
8933 if (LABEL_P (i2) || JUMP_P (i2))
8934 break;
8935 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8936 && reg_mentioned_p (reg, PATTERN (i2)))
8938 /* Some other ref remains; just delete the output reload we
8939 know to be dead. */
8940 delete_address_reloads (output_reload_insn, insn);
8941 delete_insn (output_reload_insn);
8942 return;
8946 /* Delete the now-dead stores into this pseudo. Note that this
8947 loop also takes care of deleting output_reload_insn. */
8948 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8950 rtx set = single_set (i2);
8952 if (set != 0 && SET_DEST (set) == reg)
8954 delete_address_reloads (i2, insn);
8955 delete_insn (i2);
8957 if (LABEL_P (i2) || JUMP_P (i2))
8958 break;
8961 /* For the debugging info, say the pseudo lives in this reload reg. */
8962 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8963 if (ira_conflicts_p)
8964 /* Inform IRA about the change. */
8965 ira_mark_allocation_change (REGNO (reg));
8966 alter_reg (REGNO (reg), -1, false);
8968 else
8970 delete_address_reloads (output_reload_insn, insn);
8971 delete_insn (output_reload_insn);
8975 /* We are going to delete DEAD_INSN. Recursively delete loads of
8976 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8977 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8978 static void
8979 delete_address_reloads (rtx dead_insn, rtx current_insn)
8981 rtx set = single_set (dead_insn);
8982 rtx set2, dst, prev, next;
8983 if (set)
8985 rtx dst = SET_DEST (set);
8986 if (MEM_P (dst))
8987 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8989 /* If we deleted the store from a reloaded post_{in,de}c expression,
8990 we can delete the matching adds. */
8991 prev = PREV_INSN (dead_insn);
8992 next = NEXT_INSN (dead_insn);
8993 if (! prev || ! next)
8994 return;
8995 set = single_set (next);
8996 set2 = single_set (prev);
8997 if (! set || ! set2
8998 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8999 || !CONST_INT_P (XEXP (SET_SRC (set), 1))
9000 || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
9001 return;
9002 dst = SET_DEST (set);
9003 if (! rtx_equal_p (dst, SET_DEST (set2))
9004 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
9005 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
9006 || (INTVAL (XEXP (SET_SRC (set), 1))
9007 != -INTVAL (XEXP (SET_SRC (set2), 1))))
9008 return;
9009 delete_related_insns (prev);
9010 delete_related_insns (next);
9013 /* Subfunction of delete_address_reloads: process registers found in X. */
9014 static void
9015 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
9017 rtx prev, set, dst, i2;
9018 int i, j;
9019 enum rtx_code code = GET_CODE (x);
9021 if (code != REG)
9023 const char *fmt = GET_RTX_FORMAT (code);
9024 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9026 if (fmt[i] == 'e')
9027 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
9028 else if (fmt[i] == 'E')
9030 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9031 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
9032 current_insn);
9035 return;
9038 if (spill_reg_order[REGNO (x)] < 0)
9039 return;
9041 /* Scan backwards for the insn that sets x. This might be a way back due
9042 to inheritance. */
9043 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
9045 code = GET_CODE (prev);
9046 if (code == CODE_LABEL || code == JUMP_INSN)
9047 return;
9048 if (!INSN_P (prev))
9049 continue;
9050 if (reg_set_p (x, PATTERN (prev)))
9051 break;
9052 if (reg_referenced_p (x, PATTERN (prev)))
9053 return;
9055 if (! prev || INSN_UID (prev) < reload_first_uid)
9056 return;
9057 /* Check that PREV only sets the reload register. */
9058 set = single_set (prev);
9059 if (! set)
9060 return;
9061 dst = SET_DEST (set);
9062 if (!REG_P (dst)
9063 || ! rtx_equal_p (dst, x))
9064 return;
9065 if (! reg_set_p (dst, PATTERN (dead_insn)))
9067 /* Check if DST was used in a later insn -
9068 it might have been inherited. */
9069 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
9071 if (LABEL_P (i2))
9072 break;
9073 if (! INSN_P (i2))
9074 continue;
9075 if (reg_referenced_p (dst, PATTERN (i2)))
9077 /* If there is a reference to the register in the current insn,
9078 it might be loaded in a non-inherited reload. If no other
9079 reload uses it, that means the register is set before
9080 referenced. */
9081 if (i2 == current_insn)
9083 for (j = n_reloads - 1; j >= 0; j--)
9084 if ((rld[j].reg_rtx == dst && reload_inherited[j])
9085 || reload_override_in[j] == dst)
9086 return;
9087 for (j = n_reloads - 1; j >= 0; j--)
9088 if (rld[j].in && rld[j].reg_rtx == dst)
9089 break;
9090 if (j >= 0)
9091 break;
9093 return;
9095 if (JUMP_P (i2))
9096 break;
9097 /* If DST is still live at CURRENT_INSN, check if it is used for
9098 any reload. Note that even if CURRENT_INSN sets DST, we still
9099 have to check the reloads. */
9100 if (i2 == current_insn)
9102 for (j = n_reloads - 1; j >= 0; j--)
9103 if ((rld[j].reg_rtx == dst && reload_inherited[j])
9104 || reload_override_in[j] == dst)
9105 return;
9106 /* ??? We can't finish the loop here, because dst might be
9107 allocated to a pseudo in this block if no reload in this
9108 block needs any of the classes containing DST - see
9109 spill_hard_reg. There is no easy way to tell this, so we
9110 have to scan till the end of the basic block. */
9112 if (reg_set_p (dst, PATTERN (i2)))
9113 break;
9116 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
9117 reg_reloaded_contents[REGNO (dst)] = -1;
9118 delete_insn (prev);
9121 /* Output reload-insns to reload VALUE into RELOADREG.
9122 VALUE is an autoincrement or autodecrement RTX whose operand
9123 is a register or memory location;
9124 so reloading involves incrementing that location.
9125 IN is either identical to VALUE, or some cheaper place to reload from.
9127 INC_AMOUNT is the number to increment or decrement by (always positive).
9128 This cannot be deduced from VALUE. */
9130 static void
9131 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
9133 /* REG or MEM to be copied and incremented. */
9134 rtx incloc = find_replacement (&XEXP (value, 0));
9135 /* Nonzero if increment after copying. */
9136 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
9137 || GET_CODE (value) == POST_MODIFY);
9138 rtx last;
9139 rtx inc;
9140 rtx add_insn;
9141 int code;
9142 rtx real_in = in == value ? incloc : in;
9144 /* No hard register is equivalent to this register after
9145 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
9146 we could inc/dec that register as well (maybe even using it for
9147 the source), but I'm not sure it's worth worrying about. */
9148 if (REG_P (incloc))
9149 reg_last_reload_reg[REGNO (incloc)] = 0;
9151 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
9153 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
9154 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
9156 else
9158 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
9159 inc_amount = -inc_amount;
9161 inc = GEN_INT (inc_amount);
9164 /* If this is post-increment, first copy the location to the reload reg. */
9165 if (post && real_in != reloadreg)
9166 emit_insn (gen_move_insn (reloadreg, real_in));
9168 if (in == value)
9170 /* See if we can directly increment INCLOC. Use a method similar to
9171 that in gen_reload. */
9173 last = get_last_insn ();
9174 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
9175 gen_rtx_PLUS (GET_MODE (incloc),
9176 incloc, inc)));
9178 code = recog_memoized (add_insn);
9179 if (code >= 0)
9181 extract_insn (add_insn);
9182 if (constrain_operands (1))
9184 /* If this is a pre-increment and we have incremented the value
9185 where it lives, copy the incremented value to RELOADREG to
9186 be used as an address. */
9188 if (! post)
9189 emit_insn (gen_move_insn (reloadreg, incloc));
9190 return;
9193 delete_insns_since (last);
9196 /* If couldn't do the increment directly, must increment in RELOADREG.
9197 The way we do this depends on whether this is pre- or post-increment.
9198 For pre-increment, copy INCLOC to the reload register, increment it
9199 there, then save back. */
9201 if (! post)
9203 if (in != reloadreg)
9204 emit_insn (gen_move_insn (reloadreg, real_in));
9205 emit_insn (gen_add2_insn (reloadreg, inc));
9206 emit_insn (gen_move_insn (incloc, reloadreg));
9208 else
9210 /* Postincrement.
9211 Because this might be a jump insn or a compare, and because RELOADREG
9212 may not be available after the insn in an input reload, we must do
9213 the incrementation before the insn being reloaded for.
9215 We have already copied IN to RELOADREG. Increment the copy in
9216 RELOADREG, save that back, then decrement RELOADREG so it has
9217 the original value. */
9219 emit_insn (gen_add2_insn (reloadreg, inc));
9220 emit_insn (gen_move_insn (incloc, reloadreg));
9221 if (CONST_INT_P (inc))
9222 emit_insn (gen_add2_insn (reloadreg,
9223 gen_int_mode (-INTVAL (inc),
9224 GET_MODE (reloadreg))));
9225 else
9226 emit_insn (gen_sub2_insn (reloadreg, inc));
9230 #ifdef AUTO_INC_DEC
9231 static void
9232 add_auto_inc_notes (rtx insn, rtx x)
9234 enum rtx_code code = GET_CODE (x);
9235 const char *fmt;
9236 int i, j;
9238 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9240 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
9241 return;
9244 /* Scan all the operand sub-expressions. */
9245 fmt = GET_RTX_FORMAT (code);
9246 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9248 if (fmt[i] == 'e')
9249 add_auto_inc_notes (insn, XEXP (x, i));
9250 else if (fmt[i] == 'E')
9251 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9252 add_auto_inc_notes (insn, XVECEXP (x, i, j));
9255 #endif