| blob | 73eca193340544efb0a82b95862be2f06feb5d8e |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 ;; Free Software Foundation, Inc.
5 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it
10 ;; under the terms of the GNU General Public License as published
11 ;; by the Free Software Foundation; either version 3, or (at your
12 ;; option) any later version.
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
15 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 ;; License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING3. If not see
21 ;; <http://www.gnu.org/licenses/>.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;;
26 ;; REGNOS
27 ;;
29 (define_constants
30 [(MQ_REGNO 64)
31 (LR_REGNO 65)
32 (CTR_REGNO 66)
33 (CR0_REGNO 68)
34 (CR1_REGNO 69)
35 (CR2_REGNO 70)
36 (CR3_REGNO 71)
37 (CR4_REGNO 72)
38 (CR5_REGNO 73)
39 (CR6_REGNO 74)
40 (CR7_REGNO 75)
41 (MAX_CR_REGNO 75)
42 (XER_REGNO 76)
43 (FIRST_ALTIVEC_REGNO 77)
44 (LAST_ALTIVEC_REGNO 108)
45 (VRSAVE_REGNO 109)
46 (VSCR_REGNO 110)
47 (SPE_ACC_REGNO 111)
48 (SPEFSCR_REGNO 112)
49 (SFP_REGNO 113)
50 ])
52 ;;
53 ;; UNSPEC usage
54 ;;
56 (define_constants
57 [(UNSPEC_FRSP 0) ; frsp for POWER machines
58 (UNSPEC_PROBE_STACK 4) ; probe stack memory reference
59 (UNSPEC_TIE 5) ; tie stack contents and stack pointer
60 (UNSPEC_TOCPTR 6) ; address of a word pointing to the TOC
61 (UNSPEC_TOC 7) ; address of the TOC (more-or-less)
62 (UNSPEC_MOVSI_GOT 8)
63 (UNSPEC_MV_CR_OV 9) ; move_from_CR_ov_bit
64 (UNSPEC_FCTIWZ 10)
65 (UNSPEC_FRIM 11)
66 (UNSPEC_FRIN 12)
67 (UNSPEC_FRIP 13)
68 (UNSPEC_FRIZ 14)
69 (UNSPEC_LD_MPIC 15) ; load_macho_picbase
70 (UNSPEC_MPIC_CORRECT 16) ; macho_correct_pic
71 (UNSPEC_TLSGD 17)
72 (UNSPEC_TLSLD 18)
73 (UNSPEC_MOVESI_FROM_CR 19)
74 (UNSPEC_MOVESI_TO_CR 20)
75 (UNSPEC_TLSDTPREL 21)
76 (UNSPEC_TLSDTPRELHA 22)
77 (UNSPEC_TLSDTPRELLO 23)
78 (UNSPEC_TLSGOTDTPREL 24)
79 (UNSPEC_TLSTPREL 25)
80 (UNSPEC_TLSTPRELHA 26)
81 (UNSPEC_TLSTPRELLO 27)
82 (UNSPEC_TLSGOTTPREL 28)
83 (UNSPEC_TLSTLS 29)
84 (UNSPEC_FIX_TRUNC_TF 30) ; fadd, rounding towards zero
85 (UNSPEC_MV_CR_GT 31) ; move_from_CR_gt_bit
86 (UNSPEC_STFIWX 32)
87 (UNSPEC_POPCNTB 33)
88 (UNSPEC_FRES 34)
89 (UNSPEC_SP_SET 35)
90 (UNSPEC_SP_TEST 36)
91 (UNSPEC_SYNC 37)
92 (UNSPEC_LWSYNC 38)
93 (UNSPEC_ISYNC 39)
94 (UNSPEC_SYNC_OP 40)
95 (UNSPEC_ATOMIC 41)
96 (UNSPEC_CMPXCHG 42)
97 (UNSPEC_XCHG 43)
98 (UNSPEC_AND 44)
99 (UNSPEC_DLMZB 45)
100 (UNSPEC_DLMZB_CR 46)
101 (UNSPEC_DLMZB_STRLEN 47)
102 (UNSPEC_RSQRT 48)
103 (UNSPEC_TOCREL 49)
104 (UNSPEC_MACHOPIC_OFFSET 50)
105 (UNSPEC_BPERM 51)
106 ])
108 ;;
109 ;; UNSPEC_VOLATILE usage
110 ;;
112 (define_constants
113 [(UNSPECV_BLOCK 0)
114 (UNSPECV_LL 1) ; load-locked
115 (UNSPECV_SC 2) ; store-conditional
116 (UNSPECV_EH_RR 9) ; eh_reg_restore
117 ])
118 \f
119 ;; Define an insn type attribute. This is used in function unit delay
120 ;; computations.
121 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel"
122 (const_string "integer"))
124 ;; Define floating point instruction sub-types for use with Xfpu.md
125 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
127 ;; Length (in bytes).
128 ; '(pc)' in the following doesn't include the instruction itself; it is
129 ; calculated as if the instruction had zero size.
130 (define_attr "length" ""
131 (if_then_else (eq_attr "type" "branch")
132 (if_then_else (and (ge (minus (match_dup 0) (pc))
133 (const_int -32768))
134 (lt (minus (match_dup 0) (pc))
135 (const_int 32764)))
136 (const_int 4)
137 (const_int 8))
138 (const_int 4)))
140 ;; Processor type -- this attribute must exactly match the processor_type
141 ;; enumeration in rs6000.h.
143 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2"
144 (const (symbol_ref "rs6000_cpu_attr")))
147 ;; If this instruction is microcoded on the CELL processor
148 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
149 (define_attr "cell_micro" "not,conditional,always"
150 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
151 (const_string "always")
152 (const_string "not")))
154 (automata_option "ndfa")
156 (include "rios1.md")
157 (include "rios2.md")
158 (include "rs64.md")
159 (include "mpc.md")
160 (include "40x.md")
161 (include "440.md")
162 (include "476.md")
163 (include "603.md")
164 (include "6xx.md")
165 (include "7xx.md")
166 (include "7450.md")
167 (include "8540.md")
168 (include "e300c2c3.md")
169 (include "e500mc.md")
170 (include "e500mc64.md")
171 (include "power4.md")
172 (include "power5.md")
173 (include "power6.md")
174 (include "power7.md")
175 (include "cell.md")
176 (include "xfpu.md")
177 (include "a2.md")
179 (include "predicates.md")
180 (include "constraints.md")
182 (include "darwin.md")
184 \f
185 ;; Mode iterators
187 ; This mode iterator allows :GPR to be used to indicate the allowable size
188 ; of whole values in GPRs.
189 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
191 ; Any supported integer mode.
192 (define_mode_iterator INT [QI HI SI DI TI])
194 ; Any supported integer mode that fits in one register.
195 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
197 ; extend modes for DImode
198 (define_mode_iterator QHSI [QI HI SI])
200 ; SImode or DImode, even if DImode doesn't fit in GPRs.
201 (define_mode_iterator SDI [SI DI])
203 ; The size of a pointer. Also, the size of the value that a record-condition
204 ; (one with a '.') will compare.
205 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
207 ; Any hardware-supported floating-point mode
208 (define_mode_iterator FP [
209 (SF "TARGET_HARD_FLOAT
210 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
211 (DF "TARGET_HARD_FLOAT
212 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
213 (TF "!TARGET_IEEEQUAD
214 && TARGET_HARD_FLOAT
215 && (TARGET_FPRS || TARGET_E500_DOUBLE)
216 && TARGET_LONG_DOUBLE_128")
217 (DD "TARGET_DFP")
218 (TD "TARGET_DFP")])
220 ; These modes do not fit in integer registers in 32-bit mode.
221 (define_mode_iterator DIFD [DI DF DD])
223 ; Various instructions that come in SI and DI forms.
224 ; A generic w/d attribute, for things like cmpw/cmpd.
225 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
227 ; DImode bits
228 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
230 ;; ISEL/ISEL64 target selection
231 (define_mode_attr sel [(SI "") (DI "64")])
233 ;; Suffix for reload patterns
234 (define_mode_attr ptrsize [(SI "32bit")
235 (DI "64bit")])
237 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
238 (DI "TARGET_64BIT")])
240 (define_mode_attr mptrsize [(SI "si")
241 (DI "di")])
243 \f
244 ;; Start with fixed-point load and store insns. Here we put only the more
245 ;; complex forms. Basic data transfer is done later.
247 (define_expand "zero_extend<mode>di2"
248 [(set (match_operand:DI 0 "gpc_reg_operand" "")
249 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
250 "TARGET_POWERPC64"
251 "")
253 (define_insn "*zero_extend<mode>di2_internal1"
254 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
255 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
256 "TARGET_POWERPC64"
257 "@
258 l<wd>z%U1%X1 %0,%1
259 rldicl %0,%1,0,<dbits>"
260 [(set_attr "type" "load,*")])
262 (define_insn "*zero_extend<mode>di2_internal2"
263 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
264 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
265 (const_int 0)))
266 (clobber (match_scratch:DI 2 "=r,r"))]
267 "TARGET_64BIT"
268 "@
269 rldicl. %2,%1,0,<dbits>
270 #"
271 [(set_attr "type" "compare")
272 (set_attr "length" "4,8")])
274 (define_split
275 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
276 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
277 (const_int 0)))
278 (clobber (match_scratch:DI 2 ""))]
279 "TARGET_POWERPC64 && reload_completed"
280 [(set (match_dup 2)
281 (zero_extend:DI (match_dup 1)))
282 (set (match_dup 0)
283 (compare:CC (match_dup 2)
284 (const_int 0)))]
285 "")
287 (define_insn "*zero_extend<mode>di2_internal3"
288 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
289 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
290 (const_int 0)))
291 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
292 (zero_extend:DI (match_dup 1)))]
293 "TARGET_64BIT"
294 "@
295 rldicl. %0,%1,0,<dbits>
296 #"
297 [(set_attr "type" "compare")
298 (set_attr "length" "4,8")])
300 (define_split
301 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
302 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
303 (const_int 0)))
304 (set (match_operand:DI 0 "gpc_reg_operand" "")
305 (zero_extend:DI (match_dup 1)))]
306 "TARGET_POWERPC64 && reload_completed"
307 [(set (match_dup 0)
308 (zero_extend:DI (match_dup 1)))
309 (set (match_dup 2)
310 (compare:CC (match_dup 0)
311 (const_int 0)))]
312 "")
314 (define_insn "extendqidi2"
315 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
316 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
317 "TARGET_POWERPC64"
318 "extsb %0,%1"
319 [(set_attr "type" "exts")])
321 (define_insn ""
322 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
323 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
324 (const_int 0)))
325 (clobber (match_scratch:DI 2 "=r,r"))]
326 "TARGET_64BIT"
327 "@
328 extsb. %2,%1
329 #"
330 [(set_attr "type" "compare")
331 (set_attr "length" "4,8")])
333 (define_split
334 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
335 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
336 (const_int 0)))
337 (clobber (match_scratch:DI 2 ""))]
338 "TARGET_POWERPC64 && reload_completed"
339 [(set (match_dup 2)
340 (sign_extend:DI (match_dup 1)))
341 (set (match_dup 0)
342 (compare:CC (match_dup 2)
343 (const_int 0)))]
344 "")
346 (define_insn ""
347 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
348 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
349 (const_int 0)))
350 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
351 (sign_extend:DI (match_dup 1)))]
352 "TARGET_64BIT"
353 "@
354 extsb. %0,%1
355 #"
356 [(set_attr "type" "compare")
357 (set_attr "length" "4,8")])
359 (define_split
360 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
361 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
362 (const_int 0)))
363 (set (match_operand:DI 0 "gpc_reg_operand" "")
364 (sign_extend:DI (match_dup 1)))]
365 "TARGET_POWERPC64 && reload_completed"
366 [(set (match_dup 0)
367 (sign_extend:DI (match_dup 1)))
368 (set (match_dup 2)
369 (compare:CC (match_dup 0)
370 (const_int 0)))]
371 "")
373 (define_expand "extendhidi2"
374 [(set (match_operand:DI 0 "gpc_reg_operand" "")
375 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
376 "TARGET_POWERPC64"
377 "")
379 (define_insn ""
380 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
381 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
382 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
383 "@
384 lha%U1%X1 %0,%1
385 extsh %0,%1"
386 [(set_attr "type" "load_ext,exts")])
388 (define_insn ""
389 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
390 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
391 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
392 "extsh %0,%1"
393 [(set_attr "type" "exts")])
395 (define_insn ""
396 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
397 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
398 (const_int 0)))
399 (clobber (match_scratch:DI 2 "=r,r"))]
400 "TARGET_64BIT"
401 "@
402 extsh. %2,%1
403 #"
404 [(set_attr "type" "compare")
405 (set_attr "length" "4,8")])
407 (define_split
408 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
409 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
410 (const_int 0)))
411 (clobber (match_scratch:DI 2 ""))]
412 "TARGET_POWERPC64 && reload_completed"
413 [(set (match_dup 2)
414 (sign_extend:DI (match_dup 1)))
415 (set (match_dup 0)
416 (compare:CC (match_dup 2)
417 (const_int 0)))]
418 "")
420 (define_insn ""
421 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
422 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
423 (const_int 0)))
424 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
425 (sign_extend:DI (match_dup 1)))]
426 "TARGET_64BIT"
427 "@
428 extsh. %0,%1
429 #"
430 [(set_attr "type" "compare")
431 (set_attr "length" "4,8")])
433 (define_split
434 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
435 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
436 (const_int 0)))
437 (set (match_operand:DI 0 "gpc_reg_operand" "")
438 (sign_extend:DI (match_dup 1)))]
439 "TARGET_POWERPC64 && reload_completed"
440 [(set (match_dup 0)
441 (sign_extend:DI (match_dup 1)))
442 (set (match_dup 2)
443 (compare:CC (match_dup 0)
444 (const_int 0)))]
445 "")
447 (define_expand "extendsidi2"
448 [(set (match_operand:DI 0 "gpc_reg_operand" "")
449 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
450 "TARGET_POWERPC64"
451 "")
453 (define_insn ""
454 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
455 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
456 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
457 "@
458 lwa%U1%X1 %0,%1
459 extsw %0,%1"
460 [(set_attr "type" "load_ext,exts")])
462 (define_insn ""
463 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
464 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
465 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
466 "extsw %0,%1"
467 [(set_attr "type" "exts")])
469 (define_insn ""
470 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
471 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
472 (const_int 0)))
473 (clobber (match_scratch:DI 2 "=r,r"))]
474 "TARGET_64BIT"
475 "@
476 extsw. %2,%1
477 #"
478 [(set_attr "type" "compare")
479 (set_attr "length" "4,8")])
481 (define_split
482 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
483 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
484 (const_int 0)))
485 (clobber (match_scratch:DI 2 ""))]
486 "TARGET_POWERPC64 && reload_completed"
487 [(set (match_dup 2)
488 (sign_extend:DI (match_dup 1)))
489 (set (match_dup 0)
490 (compare:CC (match_dup 2)
491 (const_int 0)))]
492 "")
494 (define_insn ""
495 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
496 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
497 (const_int 0)))
498 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
499 (sign_extend:DI (match_dup 1)))]
500 "TARGET_64BIT"
501 "@
502 extsw. %0,%1
503 #"
504 [(set_attr "type" "compare")
505 (set_attr "length" "4,8")])
507 (define_split
508 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
509 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
510 (const_int 0)))
511 (set (match_operand:DI 0 "gpc_reg_operand" "")
512 (sign_extend:DI (match_dup 1)))]
513 "TARGET_POWERPC64 && reload_completed"
514 [(set (match_dup 0)
515 (sign_extend:DI (match_dup 1)))
516 (set (match_dup 2)
517 (compare:CC (match_dup 0)
518 (const_int 0)))]
519 "")
521 (define_expand "zero_extendqisi2"
522 [(set (match_operand:SI 0 "gpc_reg_operand" "")
523 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
524 ""
525 "")
527 (define_insn ""
528 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
529 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
530 ""
531 "@
532 lbz%U1%X1 %0,%1
533 {rlinm|rlwinm} %0,%1,0,0xff"
534 [(set_attr "type" "load,*")])
536 (define_insn ""
537 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
538 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
539 (const_int 0)))
540 (clobber (match_scratch:SI 2 "=r,r"))]
541 ""
542 "@
543 {andil.|andi.} %2,%1,0xff
544 #"
545 [(set_attr "type" "fast_compare,compare")
546 (set_attr "length" "4,8")])
548 (define_split
549 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
550 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
551 (const_int 0)))
552 (clobber (match_scratch:SI 2 ""))]
553 "reload_completed"
554 [(set (match_dup 2)
555 (zero_extend:SI (match_dup 1)))
556 (set (match_dup 0)
557 (compare:CC (match_dup 2)
558 (const_int 0)))]
559 "")
561 (define_insn ""
562 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
563 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
564 (const_int 0)))
565 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
566 (zero_extend:SI (match_dup 1)))]
567 ""
568 "@
569 {andil.|andi.} %0,%1,0xff
570 #"
571 [(set_attr "type" "fast_compare,compare")
572 (set_attr "length" "4,8")])
574 (define_split
575 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
576 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
577 (const_int 0)))
578 (set (match_operand:SI 0 "gpc_reg_operand" "")
579 (zero_extend:SI (match_dup 1)))]
580 "reload_completed"
581 [(set (match_dup 0)
582 (zero_extend:SI (match_dup 1)))
583 (set (match_dup 2)
584 (compare:CC (match_dup 0)
585 (const_int 0)))]
586 "")
588 (define_expand "extendqisi2"
589 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
590 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
591 ""
592 "
593 {
594 if (TARGET_POWERPC)
595 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
596 else if (TARGET_POWER)
597 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
598 else
599 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
600 DONE;
601 }")
603 (define_insn "extendqisi2_ppc"
604 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
605 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
606 "TARGET_POWERPC"
607 "extsb %0,%1"
608 [(set_attr "type" "exts")])
610 (define_insn ""
611 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
612 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
613 (const_int 0)))
614 (clobber (match_scratch:SI 2 "=r,r"))]
615 "TARGET_POWERPC"
616 "@
617 extsb. %2,%1
618 #"
619 [(set_attr "type" "compare")
620 (set_attr "length" "4,8")])
622 (define_split
623 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
624 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
625 (const_int 0)))
626 (clobber (match_scratch:SI 2 ""))]
627 "TARGET_POWERPC && reload_completed"
628 [(set (match_dup 2)
629 (sign_extend:SI (match_dup 1)))
630 (set (match_dup 0)
631 (compare:CC (match_dup 2)
632 (const_int 0)))]
633 "")
635 (define_insn ""
636 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
637 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
638 (const_int 0)))
639 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
640 (sign_extend:SI (match_dup 1)))]
641 "TARGET_POWERPC"
642 "@
643 extsb. %0,%1
644 #"
645 [(set_attr "type" "compare")
646 (set_attr "length" "4,8")])
648 (define_split
649 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
650 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
651 (const_int 0)))
652 (set (match_operand:SI 0 "gpc_reg_operand" "")
653 (sign_extend:SI (match_dup 1)))]
654 "TARGET_POWERPC && reload_completed"
655 [(set (match_dup 0)
656 (sign_extend:SI (match_dup 1)))
657 (set (match_dup 2)
658 (compare:CC (match_dup 0)
659 (const_int 0)))]
660 "")
662 (define_expand "extendqisi2_power"
663 [(parallel [(set (match_dup 2)
664 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
665 (const_int 24)))
666 (clobber (scratch:SI))])
667 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
668 (ashiftrt:SI (match_dup 2)
669 (const_int 24)))
670 (clobber (scratch:SI))])]
671 "TARGET_POWER"
672 "
673 { operands[1] = gen_lowpart (SImode, operands[1]);
674 operands[2] = gen_reg_rtx (SImode); }")
676 (define_expand "extendqisi2_no_power"
677 [(set (match_dup 2)
678 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
679 (const_int 24)))
680 (set (match_operand:SI 0 "gpc_reg_operand" "")
681 (ashiftrt:SI (match_dup 2)
682 (const_int 24)))]
683 "! TARGET_POWER && ! TARGET_POWERPC"
684 "
685 { operands[1] = gen_lowpart (SImode, operands[1]);
686 operands[2] = gen_reg_rtx (SImode); }")
688 (define_expand "zero_extendqihi2"
689 [(set (match_operand:HI 0 "gpc_reg_operand" "")
690 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
691 ""
692 "")
694 (define_insn ""
695 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
696 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
697 ""
698 "@
699 lbz%U1%X1 %0,%1
700 {rlinm|rlwinm} %0,%1,0,0xff"
701 [(set_attr "type" "load,*")])
703 (define_insn ""
704 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
705 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
706 (const_int 0)))
707 (clobber (match_scratch:HI 2 "=r,r"))]
708 ""
709 "@
710 {andil.|andi.} %2,%1,0xff
711 #"
712 [(set_attr "type" "fast_compare,compare")
713 (set_attr "length" "4,8")])
715 (define_split
716 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
717 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
718 (const_int 0)))
719 (clobber (match_scratch:HI 2 ""))]
720 "reload_completed"
721 [(set (match_dup 2)
722 (zero_extend:HI (match_dup 1)))
723 (set (match_dup 0)
724 (compare:CC (match_dup 2)
725 (const_int 0)))]
726 "")
728 (define_insn ""
729 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
730 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
731 (const_int 0)))
732 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
733 (zero_extend:HI (match_dup 1)))]
734 ""
735 "@
736 {andil.|andi.} %0,%1,0xff
737 #"
738 [(set_attr "type" "fast_compare,compare")
739 (set_attr "length" "4,8")])
741 (define_split
742 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
743 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
744 (const_int 0)))
745 (set (match_operand:HI 0 "gpc_reg_operand" "")
746 (zero_extend:HI (match_dup 1)))]
747 "reload_completed"
748 [(set (match_dup 0)
749 (zero_extend:HI (match_dup 1)))
750 (set (match_dup 2)
751 (compare:CC (match_dup 0)
752 (const_int 0)))]
753 "")
755 (define_expand "extendqihi2"
756 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
757 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
758 ""
759 "
760 {
761 if (TARGET_POWERPC)
762 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
763 else if (TARGET_POWER)
764 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
765 else
766 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
767 DONE;
768 }")
770 (define_insn "extendqihi2_ppc"
771 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
772 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
773 "TARGET_POWERPC"
774 "extsb %0,%1"
775 [(set_attr "type" "exts")])
777 (define_insn ""
778 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
779 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
780 (const_int 0)))
781 (clobber (match_scratch:HI 2 "=r,r"))]
782 "TARGET_POWERPC"
783 "@
784 extsb. %2,%1
785 #"
786 [(set_attr "type" "compare")
787 (set_attr "length" "4,8")])
789 (define_split
790 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
791 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
792 (const_int 0)))
793 (clobber (match_scratch:HI 2 ""))]
794 "TARGET_POWERPC && reload_completed"
795 [(set (match_dup 2)
796 (sign_extend:HI (match_dup 1)))
797 (set (match_dup 0)
798 (compare:CC (match_dup 2)
799 (const_int 0)))]
800 "")
802 (define_insn ""
803 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
804 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
805 (const_int 0)))
806 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
807 (sign_extend:HI (match_dup 1)))]
808 "TARGET_POWERPC"
809 "@
810 extsb. %0,%1
811 #"
812 [(set_attr "type" "compare")
813 (set_attr "length" "4,8")])
815 (define_split
816 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
817 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
818 (const_int 0)))
819 (set (match_operand:HI 0 "gpc_reg_operand" "")
820 (sign_extend:HI (match_dup 1)))]
821 "TARGET_POWERPC && reload_completed"
822 [(set (match_dup 0)
823 (sign_extend:HI (match_dup 1)))
824 (set (match_dup 2)
825 (compare:CC (match_dup 0)
826 (const_int 0)))]
827 "")
829 (define_expand "extendqihi2_power"
830 [(parallel [(set (match_dup 2)
831 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
832 (const_int 24)))
833 (clobber (scratch:SI))])
834 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
835 (ashiftrt:SI (match_dup 2)
836 (const_int 24)))
837 (clobber (scratch:SI))])]
838 "TARGET_POWER"
839 "
840 { operands[0] = gen_lowpart (SImode, operands[0]);
841 operands[1] = gen_lowpart (SImode, operands[1]);
842 operands[2] = gen_reg_rtx (SImode); }")
844 (define_expand "extendqihi2_no_power"
845 [(set (match_dup 2)
846 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
847 (const_int 24)))
848 (set (match_operand:HI 0 "gpc_reg_operand" "")
849 (ashiftrt:SI (match_dup 2)
850 (const_int 24)))]
851 "! TARGET_POWER && ! TARGET_POWERPC"
852 "
853 { operands[0] = gen_lowpart (SImode, operands[0]);
854 operands[1] = gen_lowpart (SImode, operands[1]);
855 operands[2] = gen_reg_rtx (SImode); }")
857 (define_expand "zero_extendhisi2"
858 [(set (match_operand:SI 0 "gpc_reg_operand" "")
859 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
860 ""
861 "")
863 (define_insn ""
864 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
865 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
866 ""
867 "@
868 lhz%U1%X1 %0,%1
869 {rlinm|rlwinm} %0,%1,0,0xffff"
870 [(set_attr "type" "load,*")])
872 (define_insn ""
873 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
874 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
875 (const_int 0)))
876 (clobber (match_scratch:SI 2 "=r,r"))]
877 ""
878 "@
879 {andil.|andi.} %2,%1,0xffff
880 #"
881 [(set_attr "type" "fast_compare,compare")
882 (set_attr "length" "4,8")])
884 (define_split
885 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
886 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
887 (const_int 0)))
888 (clobber (match_scratch:SI 2 ""))]
889 "reload_completed"
890 [(set (match_dup 2)
891 (zero_extend:SI (match_dup 1)))
892 (set (match_dup 0)
893 (compare:CC (match_dup 2)
894 (const_int 0)))]
895 "")
897 (define_insn ""
898 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
899 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
900 (const_int 0)))
901 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
902 (zero_extend:SI (match_dup 1)))]
903 ""
904 "@
905 {andil.|andi.} %0,%1,0xffff
906 #"
907 [(set_attr "type" "fast_compare,compare")
908 (set_attr "length" "4,8")])
910 (define_split
911 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
912 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
913 (const_int 0)))
914 (set (match_operand:SI 0 "gpc_reg_operand" "")
915 (zero_extend:SI (match_dup 1)))]
916 "reload_completed"
917 [(set (match_dup 0)
918 (zero_extend:SI (match_dup 1)))
919 (set (match_dup 2)
920 (compare:CC (match_dup 0)
921 (const_int 0)))]
922 "")
924 (define_expand "extendhisi2"
925 [(set (match_operand:SI 0 "gpc_reg_operand" "")
926 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
927 ""
928 "")
930 (define_insn ""
931 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
932 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
933 "rs6000_gen_cell_microcode"
934 "@
935 lha%U1%X1 %0,%1
936 {exts|extsh} %0,%1"
937 [(set_attr "type" "load_ext,exts")])
939 (define_insn ""
940 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
941 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
942 "!rs6000_gen_cell_microcode"
943 "{exts|extsh} %0,%1"
944 [(set_attr "type" "exts")])
946 (define_insn ""
947 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
948 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
949 (const_int 0)))
950 (clobber (match_scratch:SI 2 "=r,r"))]
951 ""
952 "@
953 {exts.|extsh.} %2,%1
954 #"
955 [(set_attr "type" "compare")
956 (set_attr "length" "4,8")])
958 (define_split
959 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
960 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
961 (const_int 0)))
962 (clobber (match_scratch:SI 2 ""))]
963 "reload_completed"
964 [(set (match_dup 2)
965 (sign_extend:SI (match_dup 1)))
966 (set (match_dup 0)
967 (compare:CC (match_dup 2)
968 (const_int 0)))]
969 "")
971 (define_insn ""
972 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
973 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
974 (const_int 0)))
975 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
976 (sign_extend:SI (match_dup 1)))]
977 ""
978 "@
979 {exts.|extsh.} %0,%1
980 #"
981 [(set_attr "type" "compare")
982 (set_attr "length" "4,8")])
983 \f
984 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
986 (define_insn "*macchwc"
987 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
988 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
989 (match_operand:SI 2 "gpc_reg_operand" "r")
990 (const_int 16))
991 (sign_extend:SI
992 (match_operand:HI 1 "gpc_reg_operand" "r")))
993 (match_operand:SI 4 "gpc_reg_operand" "0"))
994 (const_int 0)))
995 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
996 (plus:SI (mult:SI (ashiftrt:SI
997 (match_dup 2)
998 (const_int 16))
999 (sign_extend:SI
1000 (match_dup 1)))
1001 (match_dup 4)))]
1002 "TARGET_MULHW"
1003 "macchw. %0, %1, %2"
1004 [(set_attr "type" "imul3")])
1006 (define_insn "*macchw"
1007 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1008 (plus:SI (mult:SI (ashiftrt:SI
1009 (match_operand:SI 2 "gpc_reg_operand" "r")
1010 (const_int 16))
1011 (sign_extend:SI
1012 (match_operand:HI 1 "gpc_reg_operand" "r")))
1013 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1014 "TARGET_MULHW"
1015 "macchw %0, %1, %2"
1016 [(set_attr "type" "imul3")])
1018 (define_insn "*macchwuc"
1019 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1020 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1021 (match_operand:SI 2 "gpc_reg_operand" "r")
1022 (const_int 16))
1023 (zero_extend:SI
1024 (match_operand:HI 1 "gpc_reg_operand" "r")))
1025 (match_operand:SI 4 "gpc_reg_operand" "0"))
1026 (const_int 0)))
1027 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1028 (plus:SI (mult:SI (lshiftrt:SI
1029 (match_dup 2)
1030 (const_int 16))
1031 (zero_extend:SI
1032 (match_dup 1)))
1033 (match_dup 4)))]
1034 "TARGET_MULHW"
1035 "macchwu. %0, %1, %2"
1036 [(set_attr "type" "imul3")])
1038 (define_insn "*macchwu"
1039 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1040 (plus:SI (mult:SI (lshiftrt:SI
1041 (match_operand:SI 2 "gpc_reg_operand" "r")
1042 (const_int 16))
1043 (zero_extend:SI
1044 (match_operand:HI 1 "gpc_reg_operand" "r")))
1045 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1046 "TARGET_MULHW"
1047 "macchwu %0, %1, %2"
1048 [(set_attr "type" "imul3")])
1050 (define_insn "*machhwc"
1051 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1052 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1053 (match_operand:SI 1 "gpc_reg_operand" "%r")
1054 (const_int 16))
1055 (ashiftrt:SI
1056 (match_operand:SI 2 "gpc_reg_operand" "r")
1057 (const_int 16)))
1058 (match_operand:SI 4 "gpc_reg_operand" "0"))
1059 (const_int 0)))
1060 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1061 (plus:SI (mult:SI (ashiftrt:SI
1062 (match_dup 1)
1063 (const_int 16))
1064 (ashiftrt:SI
1065 (match_dup 2)
1066 (const_int 16)))
1067 (match_dup 4)))]
1068 "TARGET_MULHW"
1069 "machhw. %0, %1, %2"
1070 [(set_attr "type" "imul3")])
1072 (define_insn "*machhw"
1073 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1074 (plus:SI (mult:SI (ashiftrt:SI
1075 (match_operand:SI 1 "gpc_reg_operand" "%r")
1076 (const_int 16))
1077 (ashiftrt:SI
1078 (match_operand:SI 2 "gpc_reg_operand" "r")
1079 (const_int 16)))
1080 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1081 "TARGET_MULHW"
1082 "machhw %0, %1, %2"
1083 [(set_attr "type" "imul3")])
1085 (define_insn "*machhwuc"
1086 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1087 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1088 (match_operand:SI 1 "gpc_reg_operand" "%r")
1089 (const_int 16))
1090 (lshiftrt:SI
1091 (match_operand:SI 2 "gpc_reg_operand" "r")
1092 (const_int 16)))
1093 (match_operand:SI 4 "gpc_reg_operand" "0"))
1094 (const_int 0)))
1095 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1096 (plus:SI (mult:SI (lshiftrt:SI
1097 (match_dup 1)
1098 (const_int 16))
1099 (lshiftrt:SI
1100 (match_dup 2)
1101 (const_int 16)))
1102 (match_dup 4)))]
1103 "TARGET_MULHW"
1104 "machhwu. %0, %1, %2"
1105 [(set_attr "type" "imul3")])
1107 (define_insn "*machhwu"
1108 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1109 (plus:SI (mult:SI (lshiftrt:SI
1110 (match_operand:SI 1 "gpc_reg_operand" "%r")
1111 (const_int 16))
1112 (lshiftrt:SI
1113 (match_operand:SI 2 "gpc_reg_operand" "r")
1114 (const_int 16)))
1115 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1116 "TARGET_MULHW"
1117 "machhwu %0, %1, %2"
1118 [(set_attr "type" "imul3")])
1120 (define_insn "*maclhwc"
1121 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1122 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1123 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1124 (sign_extend:SI
1125 (match_operand:HI 2 "gpc_reg_operand" "r")))
1126 (match_operand:SI 4 "gpc_reg_operand" "0"))
1127 (const_int 0)))
1128 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1129 (plus:SI (mult:SI (sign_extend:SI
1130 (match_dup 1))
1131 (sign_extend:SI
1132 (match_dup 2)))
1133 (match_dup 4)))]
1134 "TARGET_MULHW"
1135 "maclhw. %0, %1, %2"
1136 [(set_attr "type" "imul3")])
1138 (define_insn "*maclhw"
1139 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1140 (plus:SI (mult:SI (sign_extend:SI
1141 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1142 (sign_extend:SI
1143 (match_operand:HI 2 "gpc_reg_operand" "r")))
1144 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1145 "TARGET_MULHW"
1146 "maclhw %0, %1, %2"
1147 [(set_attr "type" "imul3")])
1149 (define_insn "*maclhwuc"
1150 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1151 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1152 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1153 (zero_extend:SI
1154 (match_operand:HI 2 "gpc_reg_operand" "r")))
1155 (match_operand:SI 4 "gpc_reg_operand" "0"))
1156 (const_int 0)))
1157 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1158 (plus:SI (mult:SI (zero_extend:SI
1159 (match_dup 1))
1160 (zero_extend:SI
1161 (match_dup 2)))
1162 (match_dup 4)))]
1163 "TARGET_MULHW"
1164 "maclhwu. %0, %1, %2"
1165 [(set_attr "type" "imul3")])
1167 (define_insn "*maclhwu"
1168 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1169 (plus:SI (mult:SI (zero_extend:SI
1170 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1171 (zero_extend:SI
1172 (match_operand:HI 2 "gpc_reg_operand" "r")))
1173 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1174 "TARGET_MULHW"
1175 "maclhwu %0, %1, %2"
1176 [(set_attr "type" "imul3")])
1178 (define_insn "*nmacchwc"
1179 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1180 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1181 (mult:SI (ashiftrt:SI
1182 (match_operand:SI 2 "gpc_reg_operand" "r")
1183 (const_int 16))
1184 (sign_extend:SI
1185 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1186 (const_int 0)))
1187 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1188 (minus:SI (match_dup 4)
1189 (mult:SI (ashiftrt:SI
1190 (match_dup 2)
1191 (const_int 16))
1192 (sign_extend:SI
1193 (match_dup 1)))))]
1194 "TARGET_MULHW"
1195 "nmacchw. %0, %1, %2"
1196 [(set_attr "type" "imul3")])
1198 (define_insn "*nmacchw"
1199 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1200 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1201 (mult:SI (ashiftrt:SI
1202 (match_operand:SI 2 "gpc_reg_operand" "r")
1203 (const_int 16))
1204 (sign_extend:SI
1205 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1206 "TARGET_MULHW"
1207 "nmacchw %0, %1, %2"
1208 [(set_attr "type" "imul3")])
1210 (define_insn "*nmachhwc"
1211 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1212 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1213 (mult:SI (ashiftrt:SI
1214 (match_operand:SI 1 "gpc_reg_operand" "%r")
1215 (const_int 16))
1216 (ashiftrt:SI
1217 (match_operand:SI 2 "gpc_reg_operand" "r")
1218 (const_int 16))))
1219 (const_int 0)))
1220 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1221 (minus:SI (match_dup 4)
1222 (mult:SI (ashiftrt:SI
1223 (match_dup 1)
1224 (const_int 16))
1225 (ashiftrt:SI
1226 (match_dup 2)
1227 (const_int 16)))))]
1228 "TARGET_MULHW"
1229 "nmachhw. %0, %1, %2"
1230 [(set_attr "type" "imul3")])
1232 (define_insn "*nmachhw"
1233 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1234 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1235 (mult:SI (ashiftrt:SI
1236 (match_operand:SI 1 "gpc_reg_operand" "%r")
1237 (const_int 16))
1238 (ashiftrt:SI
1239 (match_operand:SI 2 "gpc_reg_operand" "r")
1240 (const_int 16)))))]
1241 "TARGET_MULHW"
1242 "nmachhw %0, %1, %2"
1243 [(set_attr "type" "imul3")])
1245 (define_insn "*nmaclhwc"
1246 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1247 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1248 (mult:SI (sign_extend:SI
1249 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1250 (sign_extend:SI
1251 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1252 (const_int 0)))
1253 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1254 (minus:SI (match_dup 4)
1255 (mult:SI (sign_extend:SI
1256 (match_dup 1))
1257 (sign_extend:SI
1258 (match_dup 2)))))]
1259 "TARGET_MULHW"
1260 "nmaclhw. %0, %1, %2"
1261 [(set_attr "type" "imul3")])
1263 (define_insn "*nmaclhw"
1264 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1265 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1266 (mult:SI (sign_extend:SI
1267 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1268 (sign_extend:SI
1269 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1270 "TARGET_MULHW"
1271 "nmaclhw %0, %1, %2"
1272 [(set_attr "type" "imul3")])
1274 (define_insn "*mulchwc"
1275 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1276 (compare:CC (mult:SI (ashiftrt:SI
1277 (match_operand:SI 2 "gpc_reg_operand" "r")
1278 (const_int 16))
1279 (sign_extend:SI
1280 (match_operand:HI 1 "gpc_reg_operand" "r")))
1281 (const_int 0)))
1282 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1283 (mult:SI (ashiftrt:SI
1284 (match_dup 2)
1285 (const_int 16))
1286 (sign_extend:SI
1287 (match_dup 1))))]
1288 "TARGET_MULHW"
1289 "mulchw. %0, %1, %2"
1290 [(set_attr "type" "imul3")])
1292 (define_insn "*mulchw"
1293 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1294 (mult:SI (ashiftrt:SI
1295 (match_operand:SI 2 "gpc_reg_operand" "r")
1296 (const_int 16))
1297 (sign_extend:SI
1298 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1299 "TARGET_MULHW"
1300 "mulchw %0, %1, %2"
1301 [(set_attr "type" "imul3")])
1303 (define_insn "*mulchwuc"
1304 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1305 (compare:CC (mult:SI (lshiftrt:SI
1306 (match_operand:SI 2 "gpc_reg_operand" "r")
1307 (const_int 16))
1308 (zero_extend:SI
1309 (match_operand:HI 1 "gpc_reg_operand" "r")))
1310 (const_int 0)))
1311 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1312 (mult:SI (lshiftrt:SI
1313 (match_dup 2)
1314 (const_int 16))
1315 (zero_extend:SI
1316 (match_dup 1))))]
1317 "TARGET_MULHW"
1318 "mulchwu. %0, %1, %2"
1319 [(set_attr "type" "imul3")])
1321 (define_insn "*mulchwu"
1322 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1323 (mult:SI (lshiftrt:SI
1324 (match_operand:SI 2 "gpc_reg_operand" "r")
1325 (const_int 16))
1326 (zero_extend:SI
1327 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1328 "TARGET_MULHW"
1329 "mulchwu %0, %1, %2"
1330 [(set_attr "type" "imul3")])
1332 (define_insn "*mulhhwc"
1333 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1334 (compare:CC (mult:SI (ashiftrt:SI
1335 (match_operand:SI 1 "gpc_reg_operand" "%r")
1336 (const_int 16))
1337 (ashiftrt:SI
1338 (match_operand:SI 2 "gpc_reg_operand" "r")
1339 (const_int 16)))
1340 (const_int 0)))
1341 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1342 (mult:SI (ashiftrt:SI
1343 (match_dup 1)
1344 (const_int 16))
1345 (ashiftrt:SI
1346 (match_dup 2)
1347 (const_int 16))))]
1348 "TARGET_MULHW"
1349 "mulhhw. %0, %1, %2"
1350 [(set_attr "type" "imul3")])
1352 (define_insn "*mulhhw"
1353 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1354 (mult:SI (ashiftrt:SI
1355 (match_operand:SI 1 "gpc_reg_operand" "%r")
1356 (const_int 16))
1357 (ashiftrt:SI
1358 (match_operand:SI 2 "gpc_reg_operand" "r")
1359 (const_int 16))))]
1360 "TARGET_MULHW"
1361 "mulhhw %0, %1, %2"
1362 [(set_attr "type" "imul3")])
1364 (define_insn "*mulhhwuc"
1365 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1366 (compare:CC (mult:SI (lshiftrt:SI
1367 (match_operand:SI 1 "gpc_reg_operand" "%r")
1368 (const_int 16))
1369 (lshiftrt:SI
1370 (match_operand:SI 2 "gpc_reg_operand" "r")
1371 (const_int 16)))
1372 (const_int 0)))
1373 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1374 (mult:SI (lshiftrt:SI
1375 (match_dup 1)
1376 (const_int 16))
1377 (lshiftrt:SI
1378 (match_dup 2)
1379 (const_int 16))))]
1380 "TARGET_MULHW"
1381 "mulhhwu. %0, %1, %2"
1382 [(set_attr "type" "imul3")])
1384 (define_insn "*mulhhwu"
1385 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1386 (mult:SI (lshiftrt:SI
1387 (match_operand:SI 1 "gpc_reg_operand" "%r")
1388 (const_int 16))
1389 (lshiftrt:SI
1390 (match_operand:SI 2 "gpc_reg_operand" "r")
1391 (const_int 16))))]
1392 "TARGET_MULHW"
1393 "mulhhwu %0, %1, %2"
1394 [(set_attr "type" "imul3")])
1396 (define_insn "*mullhwc"
1397 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1398 (compare:CC (mult:SI (sign_extend:SI
1399 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1400 (sign_extend:SI
1401 (match_operand:HI 2 "gpc_reg_operand" "r")))
1402 (const_int 0)))
1403 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1404 (mult:SI (sign_extend:SI
1405 (match_dup 1))
1406 (sign_extend:SI
1407 (match_dup 2))))]
1408 "TARGET_MULHW"
1409 "mullhw. %0, %1, %2"
1410 [(set_attr "type" "imul3")])
1412 (define_insn "*mullhw"
1413 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1414 (mult:SI (sign_extend:SI
1415 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1416 (sign_extend:SI
1417 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1418 "TARGET_MULHW"
1419 "mullhw %0, %1, %2"
1420 [(set_attr "type" "imul3")])
1422 (define_insn "*mullhwuc"
1423 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1424 (compare:CC (mult:SI (zero_extend:SI
1425 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1426 (zero_extend:SI
1427 (match_operand:HI 2 "gpc_reg_operand" "r")))
1428 (const_int 0)))
1429 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1430 (mult:SI (zero_extend:SI
1431 (match_dup 1))
1432 (zero_extend:SI
1433 (match_dup 2))))]
1434 "TARGET_MULHW"
1435 "mullhwu. %0, %1, %2"
1436 [(set_attr "type" "imul3")])
1438 (define_insn "*mullhwu"
1439 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1440 (mult:SI (zero_extend:SI
1441 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1442 (zero_extend:SI
1443 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1444 "TARGET_MULHW"
1445 "mullhwu %0, %1, %2"
1446 [(set_attr "type" "imul3")])
1447 \f
1448 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1449 (define_insn "dlmzb"
1450 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1451 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1452 (match_operand:SI 2 "gpc_reg_operand" "r")]
1453 UNSPEC_DLMZB_CR))
1454 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1455 (unspec:SI [(match_dup 1)
1456 (match_dup 2)]
1457 UNSPEC_DLMZB))]
1458 "TARGET_DLMZB"
1459 "dlmzb. %0, %1, %2")
1461 (define_expand "strlensi"
1462 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1463 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1464 (match_operand:QI 2 "const_int_operand" "")
1465 (match_operand 3 "const_int_operand" "")]
1466 UNSPEC_DLMZB_STRLEN))
1467 (clobber (match_scratch:CC 4 "=x"))]
1468 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1469 {
1470 rtx result = operands[0];
1471 rtx src = operands[1];
1472 rtx search_char = operands[2];
1473 rtx align = operands[3];
1474 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1475 rtx loop_label, end_label, mem, cr0, cond;
1476 if (search_char != const0_rtx
1477 || GET_CODE (align) != CONST_INT
1478 || INTVAL (align) < 8)
1479 FAIL;
1480 word1 = gen_reg_rtx (SImode);
1481 word2 = gen_reg_rtx (SImode);
1482 scratch_dlmzb = gen_reg_rtx (SImode);
1483 scratch_string = gen_reg_rtx (Pmode);
1484 loop_label = gen_label_rtx ();
1485 end_label = gen_label_rtx ();
1486 addr = force_reg (Pmode, XEXP (src, 0));
1487 emit_move_insn (scratch_string, addr);
1488 emit_label (loop_label);
1489 mem = change_address (src, SImode, scratch_string);
1490 emit_move_insn (word1, mem);
1491 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1492 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1493 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1494 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1495 emit_jump_insn (gen_rtx_SET (VOIDmode,
1496 pc_rtx,
1497 gen_rtx_IF_THEN_ELSE (VOIDmode,
1498 cond,
1499 gen_rtx_LABEL_REF
1500 (VOIDmode,
1501 end_label),
1502 pc_rtx)));
1503 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1504 emit_jump_insn (gen_rtx_SET (VOIDmode,
1505 pc_rtx,
1506 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1507 emit_barrier ();
1508 emit_label (end_label);
1509 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1510 emit_insn (gen_subsi3 (result, scratch_string, addr));
1511 emit_insn (gen_subsi3 (result, result, const1_rtx));
1512 DONE;
1513 })
1514 \f
1515 (define_split
1516 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1517 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1518 (const_int 0)))
1519 (set (match_operand:SI 0 "gpc_reg_operand" "")
1520 (sign_extend:SI (match_dup 1)))]
1521 "reload_completed"
1522 [(set (match_dup 0)
1523 (sign_extend:SI (match_dup 1)))
1524 (set (match_dup 2)
1525 (compare:CC (match_dup 0)
1526 (const_int 0)))]
1527 "")
1529 ;; Fixed-point arithmetic insns.
1531 (define_expand "add<mode>3"
1532 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1533 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1534 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1535 ""
1536 {
1537 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1538 {
1539 if (non_short_cint_operand (operands[2], DImode))
1540 FAIL;
1541 }
1542 else if (GET_CODE (operands[2]) == CONST_INT
1543 && ! add_operand (operands[2], <MODE>mode))
1544 {
1545 rtx tmp = ((!can_create_pseudo_p ()
1546 || rtx_equal_p (operands[0], operands[1]))
1547 ? operands[0] : gen_reg_rtx (<MODE>mode));
1549 HOST_WIDE_INT val = INTVAL (operands[2]);
1550 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1551 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1553 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1554 FAIL;
1556 /* The ordering here is important for the prolog expander.
1557 When space is allocated from the stack, adding 'low' first may
1558 produce a temporary deallocation (which would be bad). */
1559 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1560 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1561 DONE;
1562 }
1563 })
1565 ;; Discourage ai/addic because of carry but provide it in an alternative
1566 ;; allowing register zero as source.
1567 (define_insn "*add<mode>3_internal1"
1568 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1569 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1570 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1571 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1572 "@
1573 {cax|add} %0,%1,%2
1574 {cal %0,%2(%1)|addi %0,%1,%2}
1575 {ai|addic} %0,%1,%2
1576 {cau|addis} %0,%1,%v2"
1577 [(set_attr "length" "4,4,4,4")])
1579 (define_insn "addsi3_high"
1580 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1581 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1582 (high:SI (match_operand 2 "" ""))))]
1583 "TARGET_MACHO && !TARGET_64BIT"
1584 "{cau|addis} %0,%1,ha16(%2)"
1585 [(set_attr "length" "4")])
1587 (define_insn "*add<mode>3_internal2"
1588 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1589 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1590 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1591 (const_int 0)))
1592 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1593 ""
1594 "@
1595 {cax.|add.} %3,%1,%2
1596 {ai.|addic.} %3,%1,%2
1597 #
1598 #"
1599 [(set_attr "type" "fast_compare,compare,compare,compare")
1600 (set_attr "length" "4,4,8,8")])
1602 (define_split
1603 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1604 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1605 (match_operand:GPR 2 "reg_or_short_operand" ""))
1606 (const_int 0)))
1607 (clobber (match_scratch:GPR 3 ""))]
1608 "reload_completed"
1609 [(set (match_dup 3)
1610 (plus:GPR (match_dup 1)
1611 (match_dup 2)))
1612 (set (match_dup 0)
1613 (compare:CC (match_dup 3)
1614 (const_int 0)))]
1615 "")
1617 (define_insn "*add<mode>3_internal3"
1618 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1619 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1620 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1621 (const_int 0)))
1622 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1623 (plus:P (match_dup 1)
1624 (match_dup 2)))]
1625 ""
1626 "@
1627 {cax.|add.} %0,%1,%2
1628 {ai.|addic.} %0,%1,%2
1629 #
1630 #"
1631 [(set_attr "type" "fast_compare,compare,compare,compare")
1632 (set_attr "length" "4,4,8,8")])
1634 (define_split
1635 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1636 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1637 (match_operand:P 2 "reg_or_short_operand" ""))
1638 (const_int 0)))
1639 (set (match_operand:P 0 "gpc_reg_operand" "")
1640 (plus:P (match_dup 1) (match_dup 2)))]
1641 "reload_completed"
1642 [(set (match_dup 0)
1643 (plus:P (match_dup 1)
1644 (match_dup 2)))
1645 (set (match_dup 3)
1646 (compare:CC (match_dup 0)
1647 (const_int 0)))]
1648 "")
1650 ;; Split an add that we can't do in one insn into two insns, each of which
1651 ;; does one 16-bit part. This is used by combine. Note that the low-order
1652 ;; add should be last in case the result gets used in an address.
1654 (define_split
1655 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1656 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1657 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1658 ""
1659 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1660 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1661 {
1662 HOST_WIDE_INT val = INTVAL (operands[2]);
1663 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1664 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1666 operands[4] = GEN_INT (low);
1667 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1668 operands[3] = GEN_INT (rest);
1669 else if (can_create_pseudo_p ())
1670 {
1671 operands[3] = gen_reg_rtx (DImode);
1672 emit_move_insn (operands[3], operands[2]);
1673 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1674 DONE;
1675 }
1676 else
1677 FAIL;
1678 })
1680 (define_insn "one_cmpl<mode>2"
1681 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1682 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1683 ""
1684 "nor %0,%1,%1")
1686 (define_insn ""
1687 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1688 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1689 (const_int 0)))
1690 (clobber (match_scratch:P 2 "=r,r"))]
1691 ""
1692 "@
1693 nor. %2,%1,%1
1694 #"
1695 [(set_attr "type" "fast_compare,compare")
1696 (set_attr "length" "4,8")])
1698 (define_split
1699 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1700 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1701 (const_int 0)))
1702 (clobber (match_scratch:P 2 ""))]
1703 "reload_completed"
1704 [(set (match_dup 2)
1705 (not:P (match_dup 1)))
1706 (set (match_dup 0)
1707 (compare:CC (match_dup 2)
1708 (const_int 0)))]
1709 "")
1711 (define_insn ""
1712 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1713 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1714 (const_int 0)))
1715 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1716 (not:P (match_dup 1)))]
1717 ""
1718 "@
1719 nor. %0,%1,%1
1720 #"
1721 [(set_attr "type" "fast_compare,compare")
1722 (set_attr "length" "4,8")])
1724 (define_split
1725 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1726 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1727 (const_int 0)))
1728 (set (match_operand:P 0 "gpc_reg_operand" "")
1729 (not:P (match_dup 1)))]
1730 "reload_completed"
1731 [(set (match_dup 0)
1732 (not:P (match_dup 1)))
1733 (set (match_dup 2)
1734 (compare:CC (match_dup 0)
1735 (const_int 0)))]
1736 "")
1738 (define_insn ""
1739 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1740 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1741 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1742 "! TARGET_POWERPC"
1743 "{sf%I1|subf%I1c} %0,%2,%1")
1745 (define_insn ""
1746 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1747 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1748 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1749 "TARGET_POWERPC"
1750 "@
1751 subf %0,%2,%1
1752 subfic %0,%2,%1")
1754 (define_insn ""
1755 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1756 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1757 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1758 (const_int 0)))
1759 (clobber (match_scratch:SI 3 "=r,r"))]
1760 "! TARGET_POWERPC"
1761 "@
1762 {sf.|subfc.} %3,%2,%1
1763 #"
1764 [(set_attr "type" "compare")
1765 (set_attr "length" "4,8")])
1767 (define_insn ""
1768 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1769 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1770 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1771 (const_int 0)))
1772 (clobber (match_scratch:P 3 "=r,r"))]
1773 "TARGET_POWERPC"
1774 "@
1775 subf. %3,%2,%1
1776 #"
1777 [(set_attr "type" "fast_compare")
1778 (set_attr "length" "4,8")])
1780 (define_split
1781 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1782 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1783 (match_operand:P 2 "gpc_reg_operand" ""))
1784 (const_int 0)))
1785 (clobber (match_scratch:P 3 ""))]
1786 "reload_completed"
1787 [(set (match_dup 3)
1788 (minus:P (match_dup 1)
1789 (match_dup 2)))
1790 (set (match_dup 0)
1791 (compare:CC (match_dup 3)
1792 (const_int 0)))]
1793 "")
1795 (define_insn ""
1796 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1797 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1798 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1799 (const_int 0)))
1800 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1801 (minus:SI (match_dup 1) (match_dup 2)))]
1802 "! TARGET_POWERPC"
1803 "@
1804 {sf.|subfc.} %0,%2,%1
1805 #"
1806 [(set_attr "type" "compare")
1807 (set_attr "length" "4,8")])
1809 (define_insn ""
1810 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1811 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1812 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1813 (const_int 0)))
1814 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1815 (minus:P (match_dup 1)
1816 (match_dup 2)))]
1817 "TARGET_POWERPC"
1818 "@
1819 subf. %0,%2,%1
1820 #"
1821 [(set_attr "type" "fast_compare")
1822 (set_attr "length" "4,8")])
1824 (define_split
1825 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1826 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1827 (match_operand:P 2 "gpc_reg_operand" ""))
1828 (const_int 0)))
1829 (set (match_operand:P 0 "gpc_reg_operand" "")
1830 (minus:P (match_dup 1)
1831 (match_dup 2)))]
1832 "reload_completed"
1833 [(set (match_dup 0)
1834 (minus:P (match_dup 1)
1835 (match_dup 2)))
1836 (set (match_dup 3)
1837 (compare:CC (match_dup 0)
1838 (const_int 0)))]
1839 "")
1841 (define_expand "sub<mode>3"
1842 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1843 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1844 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1845 ""
1846 "
1847 {
1848 if (GET_CODE (operands[2]) == CONST_INT)
1849 {
1850 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1851 negate_rtx (<MODE>mode, operands[2])));
1852 DONE;
1853 }
1854 }")
1856 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
1857 ;; instruction and some auxiliary computations. Then we just have a single
1858 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
1859 ;; combine.
1861 (define_expand "sminsi3"
1862 [(set (match_dup 3)
1863 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1864 (match_operand:SI 2 "reg_or_short_operand" ""))
1865 (const_int 0)
1866 (minus:SI (match_dup 2) (match_dup 1))))
1867 (set (match_operand:SI 0 "gpc_reg_operand" "")
1868 (minus:SI (match_dup 2) (match_dup 3)))]
1869 "TARGET_POWER || TARGET_ISEL"
1870 "
1871 {
1872 if (TARGET_ISEL)
1873 {
1874 operands[2] = force_reg (SImode, operands[2]);
1875 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1876 DONE;
1877 }
1879 operands[3] = gen_reg_rtx (SImode);
1880 }")
1882 (define_split
1883 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1884 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
1885 (match_operand:SI 2 "reg_or_short_operand" "")))
1886 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1887 "TARGET_POWER"
1888 [(set (match_dup 3)
1889 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1890 (const_int 0)
1891 (minus:SI (match_dup 2) (match_dup 1))))
1892 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
1893 "")
1895 (define_expand "smaxsi3"
1896 [(set (match_dup 3)
1897 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1898 (match_operand:SI 2 "reg_or_short_operand" ""))
1899 (const_int 0)
1900 (minus:SI (match_dup 2) (match_dup 1))))
1901 (set (match_operand:SI 0 "gpc_reg_operand" "")
1902 (plus:SI (match_dup 3) (match_dup 1)))]
1903 "TARGET_POWER || TARGET_ISEL"
1904 "
1905 {
1906 if (TARGET_ISEL)
1907 {
1908 operands[2] = force_reg (SImode, operands[2]);
1909 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1910 DONE;
1911 }
1912 operands[3] = gen_reg_rtx (SImode);
1913 }")
1915 (define_split
1916 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1917 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
1918 (match_operand:SI 2 "reg_or_short_operand" "")))
1919 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
1920 "TARGET_POWER"
1921 [(set (match_dup 3)
1922 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
1923 (const_int 0)
1924 (minus:SI (match_dup 2) (match_dup 1))))
1925 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1926 "")
1928 (define_expand "uminsi3"
1929 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1930 (match_dup 5)))
1931 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1932 (match_dup 5)))
1933 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1934 (const_int 0)
1935 (minus:SI (match_dup 4) (match_dup 3))))
1936 (set (match_operand:SI 0 "gpc_reg_operand" "")
1937 (minus:SI (match_dup 2) (match_dup 3)))]
1938 "TARGET_POWER || TARGET_ISEL"
1939 "
1940 {
1941 if (TARGET_ISEL)
1942 {
1943 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1944 DONE;
1945 }
1946 operands[3] = gen_reg_rtx (SImode);
1947 operands[4] = gen_reg_rtx (SImode);
1948 operands[5] = GEN_INT (-2147483647 - 1);
1949 }")
1951 (define_expand "umaxsi3"
1952 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1953 (match_dup 5)))
1954 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1955 (match_dup 5)))
1956 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1957 (const_int 0)
1958 (minus:SI (match_dup 4) (match_dup 3))))
1959 (set (match_operand:SI 0 "gpc_reg_operand" "")
1960 (plus:SI (match_dup 3) (match_dup 1)))]
1961 "TARGET_POWER || TARGET_ISEL"
1962 "
1963 {
1964 if (TARGET_ISEL)
1965 {
1966 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1967 DONE;
1968 }
1969 operands[3] = gen_reg_rtx (SImode);
1970 operands[4] = gen_reg_rtx (SImode);
1971 operands[5] = GEN_INT (-2147483647 - 1);
1972 }")
1974 (define_insn ""
1975 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1976 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
1977 (match_operand:SI 2 "reg_or_short_operand" "rI"))
1978 (const_int 0)
1979 (minus:SI (match_dup 2) (match_dup 1))))]
1980 "TARGET_POWER"
1981 "doz%I2 %0,%1,%2")
1983 (define_insn ""
1984 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1985 (compare:CC
1986 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
1987 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
1988 (const_int 0)
1989 (minus:SI (match_dup 2) (match_dup 1)))
1990 (const_int 0)))
1991 (clobber (match_scratch:SI 3 "=r,r"))]
1992 "TARGET_POWER"
1993 "@
1994 doz%I2. %3,%1,%2
1995 #"
1996 [(set_attr "type" "delayed_compare")
1997 (set_attr "length" "4,8")])
1999 (define_split
2000 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2001 (compare:CC
2002 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2003 (match_operand:SI 2 "reg_or_short_operand" ""))
2004 (const_int 0)
2005 (minus:SI (match_dup 2) (match_dup 1)))
2006 (const_int 0)))
2007 (clobber (match_scratch:SI 3 ""))]
2008 "TARGET_POWER && reload_completed"
2009 [(set (match_dup 3)
2010 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2011 (const_int 0)
2012 (minus:SI (match_dup 2) (match_dup 1))))
2013 (set (match_dup 0)
2014 (compare:CC (match_dup 3)
2015 (const_int 0)))]
2016 "")
2018 (define_insn ""
2019 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2020 (compare:CC
2021 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2022 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2023 (const_int 0)
2024 (minus:SI (match_dup 2) (match_dup 1)))
2025 (const_int 0)))
2026 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2027 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2028 (const_int 0)
2029 (minus:SI (match_dup 2) (match_dup 1))))]
2030 "TARGET_POWER"
2031 "@
2032 doz%I2. %0,%1,%2
2033 #"
2034 [(set_attr "type" "delayed_compare")
2035 (set_attr "length" "4,8")])
2037 (define_split
2038 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2039 (compare:CC
2040 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2041 (match_operand:SI 2 "reg_or_short_operand" ""))
2042 (const_int 0)
2043 (minus:SI (match_dup 2) (match_dup 1)))
2044 (const_int 0)))
2045 (set (match_operand:SI 0 "gpc_reg_operand" "")
2046 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2047 (const_int 0)
2048 (minus:SI (match_dup 2) (match_dup 1))))]
2049 "TARGET_POWER && reload_completed"
2050 [(set (match_dup 0)
2051 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2052 (const_int 0)
2053 (minus:SI (match_dup 2) (match_dup 1))))
2054 (set (match_dup 3)
2055 (compare:CC (match_dup 0)
2056 (const_int 0)))]
2057 "")
2059 ;; We don't need abs with condition code because such comparisons should
2060 ;; never be done.
2061 (define_expand "abssi2"
2062 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2063 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2064 ""
2065 "
2066 {
2067 if (TARGET_ISEL)
2068 {
2069 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2070 DONE;
2071 }
2072 else if (! TARGET_POWER)
2073 {
2074 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2075 DONE;
2076 }
2077 }")
2079 (define_insn "*abssi2_power"
2080 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2081 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2082 "TARGET_POWER"
2083 "abs %0,%1")
2085 (define_insn_and_split "abs<mode>2_isel"
2086 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2087 (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b")))
2088 (clobber (match_scratch:GPR 2 "=&b"))
2089 (clobber (match_scratch:CC 3 "=y"))]
2090 "TARGET_ISEL"
2091 "#"
2092 "&& reload_completed"
2093 [(set (match_dup 2) (neg:GPR (match_dup 1)))
2094 (set (match_dup 3)
2095 (compare:CC (match_dup 1)
2096 (const_int 0)))
2097 (set (match_dup 0)
2098 (if_then_else:GPR (ge (match_dup 3)
2099 (const_int 0))
2100 (match_dup 1)
2101 (match_dup 2)))]
2102 "")
2104 (define_insn_and_split "nabs<mode>2_isel"
2105 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2106 (neg:GPR (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b"))))
2107 (clobber (match_scratch:GPR 2 "=&b"))
2108 (clobber (match_scratch:CC 3 "=y"))]
2109 "TARGET_ISEL"
2110 "#"
2111 "&& reload_completed"
2112 [(set (match_dup 2) (neg:GPR (match_dup 1)))
2113 (set (match_dup 3)
2114 (compare:CC (match_dup 1)
2115 (const_int 0)))
2116 (set (match_dup 0)
2117 (if_then_else:GPR (ge (match_dup 3)
2118 (const_int 0))
2119 (match_dup 2)
2120 (match_dup 1)))]
2121 "")
2123 (define_insn_and_split "abssi2_nopower"
2124 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2125 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2126 (clobber (match_scratch:SI 2 "=&r,&r"))]
2127 "! TARGET_POWER && ! TARGET_ISEL"
2128 "#"
2129 "&& reload_completed"
2130 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2131 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2132 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2133 "")
2135 (define_insn "*nabs_power"
2136 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2137 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2138 "TARGET_POWER"
2139 "nabs %0,%1")
2141 (define_insn_and_split "*nabs_nopower"
2142 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2143 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2144 (clobber (match_scratch:SI 2 "=&r,&r"))]
2145 "! TARGET_POWER"
2146 "#"
2147 "&& reload_completed"
2148 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2149 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2150 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2151 "")
2153 (define_expand "neg<mode>2"
2154 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2155 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2156 ""
2157 "")
2159 (define_insn "*neg<mode>2_internal"
2160 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2161 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2162 ""
2163 "neg %0,%1")
2165 (define_insn ""
2166 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2167 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2168 (const_int 0)))
2169 (clobber (match_scratch:P 2 "=r,r"))]
2170 ""
2171 "@
2172 neg. %2,%1
2173 #"
2174 [(set_attr "type" "fast_compare")
2175 (set_attr "length" "4,8")])
2177 (define_split
2178 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2179 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2180 (const_int 0)))
2181 (clobber (match_scratch:P 2 ""))]
2182 "reload_completed"
2183 [(set (match_dup 2)
2184 (neg:P (match_dup 1)))
2185 (set (match_dup 0)
2186 (compare:CC (match_dup 2)
2187 (const_int 0)))]
2188 "")
2190 (define_insn ""
2191 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2192 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2193 (const_int 0)))
2194 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2195 (neg:P (match_dup 1)))]
2196 ""
2197 "@
2198 neg. %0,%1
2199 #"
2200 [(set_attr "type" "fast_compare")
2201 (set_attr "length" "4,8")])
2203 (define_split
2204 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2205 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2206 (const_int 0)))
2207 (set (match_operand:P 0 "gpc_reg_operand" "")
2208 (neg:P (match_dup 1)))]
2209 "reload_completed"
2210 [(set (match_dup 0)
2211 (neg:P (match_dup 1)))
2212 (set (match_dup 2)
2213 (compare:CC (match_dup 0)
2214 (const_int 0)))]
2215 "")
2217 (define_insn "clz<mode>2"
2218 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2219 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2220 ""
2221 "{cntlz|cntlz<wd>} %0,%1"
2222 [(set_attr "type" "cntlz")])
2224 (define_expand "ctz<mode>2"
2225 [(set (match_dup 2)
2226 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2227 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2228 (match_dup 2)))
2229 (clobber (scratch:CC))])
2230 (set (match_dup 4) (clz:GPR (match_dup 3)))
2231 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2232 (minus:GPR (match_dup 5) (match_dup 4)))]
2233 ""
2234 {
2235 operands[2] = gen_reg_rtx (<MODE>mode);
2236 operands[3] = gen_reg_rtx (<MODE>mode);
2237 operands[4] = gen_reg_rtx (<MODE>mode);
2238 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2239 })
2241 (define_expand "ffs<mode>2"
2242 [(set (match_dup 2)
2243 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2244 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2245 (match_dup 2)))
2246 (clobber (scratch:CC))])
2247 (set (match_dup 4) (clz:GPR (match_dup 3)))
2248 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2249 (minus:GPR (match_dup 5) (match_dup 4)))]
2250 ""
2251 {
2252 operands[2] = gen_reg_rtx (<MODE>mode);
2253 operands[3] = gen_reg_rtx (<MODE>mode);
2254 operands[4] = gen_reg_rtx (<MODE>mode);
2255 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2256 })
2258 (define_insn "popcntb<mode>2"
2259 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2260 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2261 UNSPEC_POPCNTB))]
2262 "TARGET_POPCNTB"
2263 "popcntb %0,%1")
2265 (define_insn "popcntwsi2"
2266 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2267 (popcount:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2268 "TARGET_POPCNTD"
2269 "popcntw %0,%1")
2271 (define_insn "popcntddi2"
2272 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2273 (popcount:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
2274 "TARGET_POPCNTD && TARGET_POWERPC64"
2275 "popcntd %0,%1")
2277 (define_expand "popcount<mode>2"
2278 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2279 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2280 "TARGET_POPCNTB || TARGET_POPCNTD"
2281 {
2282 rs6000_emit_popcount (operands[0], operands[1]);
2283 DONE;
2284 })
2286 (define_expand "parity<mode>2"
2287 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2288 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2289 "TARGET_POPCNTB"
2290 {
2291 rs6000_emit_parity (operands[0], operands[1]);
2292 DONE;
2293 })
2295 ;; Since the hardware zeros the upper part of the register, save generating the
2296 ;; AND immediate if we are converting to unsigned
2297 (define_insn "*bswaphi2_extenddi"
2298 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2299 (zero_extend:DI
2300 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2301 "TARGET_POWERPC64"
2302 "lhbrx %0,%y1"
2303 [(set_attr "length" "4")
2304 (set_attr "type" "load")])
2306 (define_insn "*bswaphi2_extendsi"
2307 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2308 (zero_extend:SI
2309 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2310 "TARGET_POWERPC"
2311 "lhbrx %0,%y1"
2312 [(set_attr "length" "4")
2313 (set_attr "type" "load")])
2315 (define_expand "bswaphi2"
2316 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2317 (bswap:HI
2318 (match_operand:HI 1 "reg_or_mem_operand" "")))
2319 (clobber (match_scratch:SI 2 ""))])]
2320 ""
2321 {
2322 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2323 operands[1] = force_reg (HImode, operands[1]);
2324 })
2326 (define_insn "bswaphi2_internal"
2327 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2328 (bswap:HI
2329 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2330 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2331 "TARGET_POWERPC"
2332 "@
2333 lhbrx %0,%y1
2334 sthbrx %1,%y0
2335 #"
2336 [(set_attr "length" "4,4,12")
2337 (set_attr "type" "load,store,*")])
2339 (define_split
2340 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2341 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2342 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2343 "TARGET_POWERPC && reload_completed"
2344 [(set (match_dup 3)
2345 (zero_extract:SI (match_dup 4)
2346 (const_int 8)
2347 (const_int 16)))
2348 (set (match_dup 2)
2349 (and:SI (ashift:SI (match_dup 4)
2350 (const_int 8))
2351 (const_int 65280))) ;; 0xff00
2352 (set (match_dup 3)
2353 (ior:SI (match_dup 3)
2354 (match_dup 2)))]
2355 "
2356 {
2357 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2358 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2359 }")
2361 (define_insn "*bswapsi2_extenddi"
2362 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2363 (zero_extend:DI
2364 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2365 "TARGET_POWERPC64"
2366 "lwbrx %0,%y1"
2367 [(set_attr "length" "4")
2368 (set_attr "type" "load")])
2370 (define_expand "bswapsi2"
2371 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2372 (bswap:SI
2373 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2374 ""
2375 {
2376 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2377 operands[1] = force_reg (SImode, operands[1]);
2378 })
2380 (define_insn "*bswapsi2_internal"
2381 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2382 (bswap:SI
2383 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2384 ""
2385 "@
2386 {lbrx|lwbrx} %0,%y1
2387 {stbrx|stwbrx} %1,%y0
2388 #"
2389 [(set_attr "length" "4,4,12")
2390 (set_attr "type" "load,store,*")])
2392 (define_split
2393 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2394 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2395 "reload_completed"
2396 [(set (match_dup 0)
2397 (rotate:SI (match_dup 1) (const_int 8)))
2398 (set (zero_extract:SI (match_dup 0)
2399 (const_int 8)
2400 (const_int 0))
2401 (match_dup 1))
2402 (set (zero_extract:SI (match_dup 0)
2403 (const_int 8)
2404 (const_int 16))
2405 (rotate:SI (match_dup 1)
2406 (const_int 16)))]
2407 "")
2409 (define_expand "bswapdi2"
2410 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2411 (bswap:DI
2412 (match_operand:DI 1 "reg_or_mem_operand" "")))
2413 (clobber (match_scratch:DI 2 ""))
2414 (clobber (match_scratch:DI 3 ""))
2415 (clobber (match_scratch:DI 4 ""))])]
2416 ""
2417 {
2418 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2419 operands[1] = force_reg (DImode, operands[1]);
2421 if (!TARGET_POWERPC64)
2422 {
2423 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2424 that uses 64-bit registers needs the same scratch registers as 64-bit
2425 mode. */
2426 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2427 DONE;
2428 }
2429 })
2431 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2432 (define_insn "*bswapdi2_ldbrx"
2433 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2434 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2435 (clobber (match_scratch:DI 2 "=X,X,&r"))
2436 (clobber (match_scratch:DI 3 "=X,X,&r"))
2437 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2438 "TARGET_POWERPC64 && TARGET_LDBRX
2439 && (REG_P (operands[0]) || REG_P (operands[1]))"
2440 "@
2441 ldbrx %0,%y1
2442 stdbrx %1,%y0
2443 #"
2444 [(set_attr "length" "4,4,36")
2445 (set_attr "type" "load,store,*")])
2447 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2448 (define_insn "*bswapdi2_64bit"
2449 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2450 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2451 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2452 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2453 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2454 "TARGET_POWERPC64 && !TARGET_LDBRX
2455 && (REG_P (operands[0]) || REG_P (operands[1]))"
2456 "#"
2457 [(set_attr "length" "16,12,36")])
2459 (define_split
2460 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2461 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2462 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2463 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2464 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2465 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2466 [(const_int 0)]
2467 "
2468 {
2469 rtx dest = operands[0];
2470 rtx src = operands[1];
2471 rtx op2 = operands[2];
2472 rtx op3 = operands[3];
2473 rtx op4 = operands[4];
2474 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode, 4);
2475 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode, 4);
2476 rtx addr1;
2477 rtx addr2;
2478 rtx word_high;
2479 rtx word_low;
2481 addr1 = XEXP (src, 0);
2482 if (GET_CODE (addr1) == PLUS)
2483 {
2484 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2485 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2486 }
2487 else
2488 {
2489 emit_move_insn (op2, GEN_INT (4));
2490 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2491 }
2493 if (BYTES_BIG_ENDIAN)
2494 {
2495 word_high = change_address (src, SImode, addr1);
2496 word_low = change_address (src, SImode, addr2);
2497 }
2498 else
2499 {
2500 word_high = change_address (src, SImode, addr2);
2501 word_low = change_address (src, SImode, addr1);
2502 }
2504 emit_insn (gen_bswapsi2 (op3_32, word_low));
2505 emit_insn (gen_bswapsi2 (op4_32, word_high));
2506 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2507 emit_insn (gen_iordi3 (dest, dest, op4));
2508 }")
2510 (define_split
2511 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2512 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2513 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2514 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2515 (clobber (match_operand:DI 4 "" ""))]
2516 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2517 [(const_int 0)]
2518 "
2519 {
2520 rtx dest = operands[0];
2521 rtx src = operands[1];
2522 rtx op2 = operands[2];
2523 rtx op3 = operands[3];
2524 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2525 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2526 rtx addr1;
2527 rtx addr2;
2528 rtx word_high;
2529 rtx word_low;
2531 addr1 = XEXP (dest, 0);
2532 if (GET_CODE (addr1) == PLUS)
2533 {
2534 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2535 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2536 }
2537 else
2538 {
2539 emit_move_insn (op2, GEN_INT (4));
2540 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2541 }
2543 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2544 if (BYTES_BIG_ENDIAN)
2545 {
2546 word_high = change_address (dest, SImode, addr1);
2547 word_low = change_address (dest, SImode, addr2);
2548 emit_insn (gen_bswapsi2 (word_high, src_si));
2549 emit_insn (gen_bswapsi2 (word_low, op3_si));
2550 }
2551 else
2552 {
2553 word_high = change_address (dest, SImode, addr2);
2554 word_low = change_address (dest, SImode, addr1);
2555 emit_insn (gen_bswapsi2 (word_low, src_si));
2556 emit_insn (gen_bswapsi2 (word_high, op3_si));
2557 }
2558 }")
2560 (define_split
2561 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2562 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2563 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2564 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2565 (clobber (match_operand:DI 4 "" ""))]
2566 "TARGET_POWERPC64 && reload_completed"
2567 [(const_int 0)]
2568 "
2569 {
2570 rtx dest = operands[0];
2571 rtx src = operands[1];
2572 rtx op2 = operands[2];
2573 rtx op3 = operands[3];
2574 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, 4);
2575 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2576 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, 4);
2577 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2579 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2580 emit_insn (gen_bswapsi2 (dest_si, src_si));
2581 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2582 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2583 emit_insn (gen_iordi3 (dest, dest, op3));
2584 }")
2586 (define_insn "bswapdi2_32bit"
2587 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2588 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2589 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2590 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2591 "#"
2592 [(set_attr "length" "16,12,36")])
2594 (define_split
2595 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2596 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2597 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2598 "!TARGET_POWERPC64 && reload_completed"
2599 [(const_int 0)]
2600 "
2601 {
2602 rtx dest = operands[0];
2603 rtx src = operands[1];
2604 rtx op2 = operands[2];
2605 rtx dest_hi = simplify_gen_subreg (SImode, dest, DImode, 0);
2606 rtx dest_lo = simplify_gen_subreg (SImode, dest, DImode, 4);
2607 rtx addr1;
2608 rtx addr2;
2609 rtx word_high;
2610 rtx word_low;
2612 addr1 = XEXP (src, 0);
2613 if (GET_CODE (addr1) == PLUS)
2614 {
2615 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2616 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2617 }
2618 else
2619 {
2620 emit_move_insn (op2, GEN_INT (4));
2621 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2622 }
2624 if (BYTES_BIG_ENDIAN)
2625 {
2626 word_high = change_address (src, SImode, addr1);
2627 word_low = change_address (src, SImode, addr2);
2628 }
2629 else
2630 {
2631 word_high = change_address (src, SImode, addr2);
2632 word_low = change_address (src, SImode, addr1);
2633 }
2635 emit_insn (gen_bswapsi2 (dest_hi, word_low));
2636 emit_insn (gen_bswapsi2 (dest_lo, word_high));
2637 }")
2639 (define_split
2640 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2641 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2642 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2643 "!TARGET_POWERPC64 && reload_completed"
2644 [(const_int 0)]
2645 "
2646 {
2647 rtx dest = operands[0];
2648 rtx src = operands[1];
2649 rtx op2 = operands[2];
2650 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2651 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2652 rtx addr1;
2653 rtx addr2;
2654 rtx word_high;
2655 rtx word_low;
2657 addr1 = XEXP (dest, 0);
2658 if (GET_CODE (addr1) == PLUS)
2659 {
2660 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2661 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2662 }
2663 else
2664 {
2665 emit_move_insn (op2, GEN_INT (4));
2666 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2667 }
2669 if (BYTES_BIG_ENDIAN)
2670 {
2671 word_high = change_address (dest, SImode, addr1);
2672 word_low = change_address (dest, SImode, addr2);
2673 }
2674 else
2675 {
2676 word_high = change_address (dest, SImode, addr2);
2677 word_low = change_address (dest, SImode, addr1);
2678 }
2680 emit_insn (gen_bswapsi2 (word_high, src_low));
2681 emit_insn (gen_bswapsi2 (word_low, src_high));
2682 }")
2684 (define_split
2685 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2686 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2687 (clobber (match_operand:SI 2 "" ""))]
2688 "!TARGET_POWERPC64 && reload_completed"
2689 [(const_int 0)]
2690 "
2691 {
2692 rtx dest = operands[0];
2693 rtx src = operands[1];
2694 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2695 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2696 rtx dest_high = simplify_gen_subreg (SImode, dest, DImode, 0);
2697 rtx dest_low = simplify_gen_subreg (SImode, dest, DImode, 4);
2699 emit_insn (gen_bswapsi2 (dest_high, src_low));
2700 emit_insn (gen_bswapsi2 (dest_low, src_high));
2701 }")
2703 (define_expand "mulsi3"
2704 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2705 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2706 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2707 ""
2708 "
2709 {
2710 if (TARGET_POWER)
2711 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2712 else
2713 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2714 DONE;
2715 }")
2717 (define_insn "mulsi3_mq"
2718 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2719 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2720 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2721 (clobber (match_scratch:SI 3 "=q,q"))]
2722 "TARGET_POWER"
2723 "@
2724 {muls|mullw} %0,%1,%2
2725 {muli|mulli} %0,%1,%2"
2726 [(set (attr "type")
2727 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2728 (const_string "imul3")
2729 (match_operand:SI 2 "short_cint_operand" "")
2730 (const_string "imul2")]
2731 (const_string "imul")))])
2733 (define_insn "mulsi3_no_mq"
2734 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2735 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2736 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2737 "! TARGET_POWER"
2738 "@
2739 {muls|mullw} %0,%1,%2
2740 {muli|mulli} %0,%1,%2"
2741 [(set (attr "type")
2742 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2743 (const_string "imul3")
2744 (match_operand:SI 2 "short_cint_operand" "")
2745 (const_string "imul2")]
2746 (const_string "imul")))])
2748 (define_insn "*mulsi3_mq_internal1"
2749 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2750 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2751 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2752 (const_int 0)))
2753 (clobber (match_scratch:SI 3 "=r,r"))
2754 (clobber (match_scratch:SI 4 "=q,q"))]
2755 "TARGET_POWER"
2756 "@
2757 {muls.|mullw.} %3,%1,%2
2758 #"
2759 [(set_attr "type" "imul_compare")
2760 (set_attr "length" "4,8")])
2762 (define_split
2763 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2764 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2765 (match_operand:SI 2 "gpc_reg_operand" ""))
2766 (const_int 0)))
2767 (clobber (match_scratch:SI 3 ""))
2768 (clobber (match_scratch:SI 4 ""))]
2769 "TARGET_POWER && reload_completed"
2770 [(parallel [(set (match_dup 3)
2771 (mult:SI (match_dup 1) (match_dup 2)))
2772 (clobber (match_dup 4))])
2773 (set (match_dup 0)
2774 (compare:CC (match_dup 3)
2775 (const_int 0)))]
2776 "")
2778 (define_insn "*mulsi3_no_mq_internal1"
2779 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2780 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2781 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2782 (const_int 0)))
2783 (clobber (match_scratch:SI 3 "=r,r"))]
2784 "! TARGET_POWER"
2785 "@
2786 {muls.|mullw.} %3,%1,%2
2787 #"
2788 [(set_attr "type" "imul_compare")
2789 (set_attr "length" "4,8")])
2791 (define_split
2792 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2793 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2794 (match_operand:SI 2 "gpc_reg_operand" ""))
2795 (const_int 0)))
2796 (clobber (match_scratch:SI 3 ""))]
2797 "! TARGET_POWER && reload_completed"
2798 [(set (match_dup 3)
2799 (mult:SI (match_dup 1) (match_dup 2)))
2800 (set (match_dup 0)
2801 (compare:CC (match_dup 3)
2802 (const_int 0)))]
2803 "")
2805 (define_insn "*mulsi3_mq_internal2"
2806 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2807 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2808 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2809 (const_int 0)))
2810 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2811 (mult:SI (match_dup 1) (match_dup 2)))
2812 (clobber (match_scratch:SI 4 "=q,q"))]
2813 "TARGET_POWER"
2814 "@
2815 {muls.|mullw.} %0,%1,%2
2816 #"
2817 [(set_attr "type" "imul_compare")
2818 (set_attr "length" "4,8")])
2820 (define_split
2821 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2822 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2823 (match_operand:SI 2 "gpc_reg_operand" ""))
2824 (const_int 0)))
2825 (set (match_operand:SI 0 "gpc_reg_operand" "")
2826 (mult:SI (match_dup 1) (match_dup 2)))
2827 (clobber (match_scratch:SI 4 ""))]
2828 "TARGET_POWER && reload_completed"
2829 [(parallel [(set (match_dup 0)
2830 (mult:SI (match_dup 1) (match_dup 2)))
2831 (clobber (match_dup 4))])
2832 (set (match_dup 3)
2833 (compare:CC (match_dup 0)
2834 (const_int 0)))]
2835 "")
2837 (define_insn "*mulsi3_no_mq_internal2"
2838 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2839 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2840 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2841 (const_int 0)))
2842 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2843 (mult:SI (match_dup 1) (match_dup 2)))]
2844 "! TARGET_POWER"
2845 "@
2846 {muls.|mullw.} %0,%1,%2
2847 #"
2848 [(set_attr "type" "imul_compare")
2849 (set_attr "length" "4,8")])
2851 (define_split
2852 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2853 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2854 (match_operand:SI 2 "gpc_reg_operand" ""))
2855 (const_int 0)))
2856 (set (match_operand:SI 0 "gpc_reg_operand" "")
2857 (mult:SI (match_dup 1) (match_dup 2)))]
2858 "! TARGET_POWER && reload_completed"
2859 [(set (match_dup 0)
2860 (mult:SI (match_dup 1) (match_dup 2)))
2861 (set (match_dup 3)
2862 (compare:CC (match_dup 0)
2863 (const_int 0)))]
2864 "")
2866 ;; Operand 1 is divided by operand 2; quotient goes to operand
2867 ;; 0 and remainder to operand 3.
2868 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2870 (define_expand "divmodsi4"
2871 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2872 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2873 (match_operand:SI 2 "gpc_reg_operand" "")))
2874 (set (match_operand:SI 3 "register_operand" "")
2875 (mod:SI (match_dup 1) (match_dup 2)))])]
2876 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2877 "
2878 {
2879 if (! TARGET_POWER && ! TARGET_POWERPC)
2880 {
2881 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2882 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2883 emit_insn (gen_divss_call ());
2884 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2885 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2886 DONE;
2887 }
2888 }")
2890 (define_insn "*divmodsi4_internal"
2891 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2892 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2893 (match_operand:SI 2 "gpc_reg_operand" "r")))
2894 (set (match_operand:SI 3 "register_operand" "=q")
2895 (mod:SI (match_dup 1) (match_dup 2)))]
2896 "TARGET_POWER"
2897 "divs %0,%1,%2"
2898 [(set_attr "type" "idiv")])
2900 (define_expand "udiv<mode>3"
2901 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2902 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2903 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2904 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2905 "
2906 {
2907 if (! TARGET_POWER && ! TARGET_POWERPC)
2908 {
2909 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2910 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2911 emit_insn (gen_quous_call ());
2912 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2913 DONE;
2914 }
2915 else if (TARGET_POWER)
2916 {
2917 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2918 DONE;
2919 }
2920 }")
2922 (define_insn "udivsi3_mq"
2923 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2924 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2925 (match_operand:SI 2 "gpc_reg_operand" "r")))
2926 (clobber (match_scratch:SI 3 "=q"))]
2927 "TARGET_POWERPC && TARGET_POWER"
2928 "divwu %0,%1,%2"
2929 [(set_attr "type" "idiv")])
2931 (define_insn "*udivsi3_no_mq"
2932 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2933 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2934 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2935 "TARGET_POWERPC && ! TARGET_POWER"
2936 "div<wd>u %0,%1,%2"
2937 [(set (attr "type")
2938 (cond [(match_operand:SI 0 "" "")
2939 (const_string "idiv")]
2940 (const_string "ldiv")))])
2943 ;; For powers of two we can do srai/aze for divide and then adjust for
2944 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2945 ;; used; for PowerPC, force operands into register and do a normal divide;
2946 ;; for AIX common-mode, use quoss call on register operands.
2947 (define_expand "div<mode>3"
2948 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2949 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2950 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2951 ""
2952 "
2953 {
2954 if (GET_CODE (operands[2]) == CONST_INT
2955 && INTVAL (operands[2]) > 0
2956 && exact_log2 (INTVAL (operands[2])) >= 0)
2957 ;
2958 else if (TARGET_POWERPC)
2959 {
2960 operands[2] = force_reg (<MODE>mode, operands[2]);
2961 if (TARGET_POWER)
2962 {
2963 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2964 DONE;
2965 }
2966 }
2967 else if (TARGET_POWER)
2968 FAIL;
2969 else
2970 {
2971 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2972 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2973 emit_insn (gen_quoss_call ());
2974 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2975 DONE;
2976 }
2977 }")
2979 (define_insn "divsi3_mq"
2980 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2981 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2982 (match_operand:SI 2 "gpc_reg_operand" "r")))
2983 (clobber (match_scratch:SI 3 "=q"))]
2984 "TARGET_POWERPC && TARGET_POWER"
2985 "divw %0,%1,%2"
2986 [(set_attr "type" "idiv")])
2988 (define_insn "*div<mode>3_no_mq"
2989 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2990 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2991 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2992 "TARGET_POWERPC && ! TARGET_POWER"
2993 "div<wd> %0,%1,%2"
2994 [(set (attr "type")
2995 (cond [(match_operand:SI 0 "" "")
2996 (const_string "idiv")]
2997 (const_string "ldiv")))])
2999 (define_expand "mod<mode>3"
3000 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
3001 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
3002 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
3003 ""
3004 "
3005 {
3006 int i;
3007 rtx temp1;
3008 rtx temp2;
3010 if (GET_CODE (operands[2]) != CONST_INT
3011 || INTVAL (operands[2]) <= 0
3012 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
3013 FAIL;
3015 temp1 = gen_reg_rtx (<MODE>mode);
3016 temp2 = gen_reg_rtx (<MODE>mode);
3018 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
3019 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
3020 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
3021 DONE;
3022 }")
3024 (define_insn ""
3025 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
3026 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
3027 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
3028 ""
3029 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
3030 [(set_attr "type" "two")
3031 (set_attr "length" "8")])
3033 (define_insn ""
3034 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3035 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3036 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3037 (const_int 0)))
3038 (clobber (match_scratch:P 3 "=r,r"))]
3039 ""
3040 "@
3041 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
3042 #"
3043 [(set_attr "type" "compare")
3044 (set_attr "length" "8,12")
3045 (set_attr "cell_micro" "not")])
3047 (define_split
3048 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3049 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3050 (match_operand:GPR 2 "exact_log2_cint_operand"
3051 ""))
3052 (const_int 0)))
3053 (clobber (match_scratch:GPR 3 ""))]
3054 "reload_completed"
3055 [(set (match_dup 3)
3056 (div:<MODE> (match_dup 1) (match_dup 2)))
3057 (set (match_dup 0)
3058 (compare:CC (match_dup 3)
3059 (const_int 0)))]
3060 "")
3062 (define_insn ""
3063 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3064 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
3065 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
3066 (const_int 0)))
3067 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
3068 (div:P (match_dup 1) (match_dup 2)))]
3069 ""
3070 "@
3071 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
3072 #"
3073 [(set_attr "type" "compare")
3074 (set_attr "length" "8,12")
3075 (set_attr "cell_micro" "not")])
3077 (define_split
3078 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3079 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3080 (match_operand:GPR 2 "exact_log2_cint_operand"
3081 ""))
3082 (const_int 0)))
3083 (set (match_operand:GPR 0 "gpc_reg_operand" "")
3084 (div:GPR (match_dup 1) (match_dup 2)))]
3085 "reload_completed"
3086 [(set (match_dup 0)
3087 (div:<MODE> (match_dup 1) (match_dup 2)))
3088 (set (match_dup 3)
3089 (compare:CC (match_dup 0)
3090 (const_int 0)))]
3091 "")
3093 (define_insn ""
3094 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3095 (udiv:SI
3096 (plus:DI (ashift:DI
3097 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
3098 (const_int 32))
3099 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
3100 (match_operand:SI 3 "gpc_reg_operand" "r")))
3101 (set (match_operand:SI 2 "register_operand" "=*q")
3102 (umod:SI
3103 (plus:DI (ashift:DI
3104 (zero_extend:DI (match_dup 1)) (const_int 32))
3105 (zero_extend:DI (match_dup 4)))
3106 (match_dup 3)))]
3107 "TARGET_POWER"
3108 "div %0,%1,%3"
3109 [(set_attr "type" "idiv")])
3111 ;; To do unsigned divide we handle the cases of the divisor looking like a
3112 ;; negative number. If it is a constant that is less than 2**31, we don't
3113 ;; have to worry about the branches. So make a few subroutines here.
3114 ;;
3115 ;; First comes the normal case.
3116 (define_expand "udivmodsi4_normal"
3117 [(set (match_dup 4) (const_int 0))
3118 (parallel [(set (match_operand:SI 0 "" "")
3119 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3120 (const_int 32))
3121 (zero_extend:DI (match_operand:SI 1 "" "")))
3122 (match_operand:SI 2 "" "")))
3123 (set (match_operand:SI 3 "" "")
3124 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
3125 (const_int 32))
3126 (zero_extend:DI (match_dup 1)))
3127 (match_dup 2)))])]
3128 "TARGET_POWER"
3129 "
3130 { operands[4] = gen_reg_rtx (SImode); }")
3132 ;; This handles the branches.
3133 (define_expand "udivmodsi4_tests"
3134 [(set (match_operand:SI 0 "" "") (const_int 0))
3135 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
3136 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
3137 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
3138 (label_ref (match_operand:SI 4 "" "")) (pc)))
3139 (set (match_dup 0) (const_int 1))
3140 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
3141 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
3142 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
3143 (label_ref (match_dup 4)) (pc)))]
3144 "TARGET_POWER"
3145 "
3146 { operands[5] = gen_reg_rtx (CCUNSmode);
3147 operands[6] = gen_reg_rtx (CCmode);
3148 }")
3150 (define_expand "udivmodsi4"
3151 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
3152 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
3153 (match_operand:SI 2 "reg_or_cint_operand" "")))
3154 (set (match_operand:SI 3 "gpc_reg_operand" "")
3155 (umod:SI (match_dup 1) (match_dup 2)))])]
3156 ""
3157 "
3158 {
3159 rtx label = 0;
3161 if (! TARGET_POWER)
3162 {
3163 if (! TARGET_POWERPC)
3164 {
3165 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
3166 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
3167 emit_insn (gen_divus_call ());
3168 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
3169 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
3170 DONE;
3171 }
3172 else
3173 FAIL;
3174 }
3176 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
3177 {
3178 operands[2] = force_reg (SImode, operands[2]);
3179 label = gen_label_rtx ();
3180 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
3181 operands[3], label));
3182 }
3183 else
3184 operands[2] = force_reg (SImode, operands[2]);
3186 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
3187 operands[3]));
3188 if (label)
3189 emit_label (label);
3191 DONE;
3192 }")
3194 ;; AIX architecture-independent common-mode multiply (DImode),
3195 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
3196 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
3197 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
3198 ;; assumed unused if generating common-mode, so ignore.
3199 (define_insn "mulh_call"
3200 [(set (reg:SI 3)
3201 (truncate:SI
3202 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
3203 (sign_extend:DI (reg:SI 4)))
3204 (const_int 32))))
3205 (clobber (reg:SI LR_REGNO))]
3206 "! TARGET_POWER && ! TARGET_POWERPC"
3207 "bla __mulh"
3208 [(set_attr "type" "imul")])
3210 (define_insn "mull_call"
3211 [(set (reg:DI 3)
3212 (mult:DI (sign_extend:DI (reg:SI 3))
3213 (sign_extend:DI (reg:SI 4))))
3214 (clobber (reg:SI LR_REGNO))
3215 (clobber (reg:SI 0))]
3216 "! TARGET_POWER && ! TARGET_POWERPC"
3217 "bla __mull"
3218 [(set_attr "type" "imul")])
3220 (define_insn "divss_call"
3221 [(set (reg:SI 3)
3222 (div:SI (reg:SI 3) (reg:SI 4)))
3223 (set (reg:SI 4)
3224 (mod:SI (reg:SI 3) (reg:SI 4)))
3225 (clobber (reg:SI LR_REGNO))
3226 (clobber (reg:SI 0))]
3227 "! TARGET_POWER && ! TARGET_POWERPC"
3228 "bla __divss"
3229 [(set_attr "type" "idiv")])
3231 (define_insn "divus_call"
3232 [(set (reg:SI 3)
3233 (udiv:SI (reg:SI 3) (reg:SI 4)))
3234 (set (reg:SI 4)
3235 (umod:SI (reg:SI 3) (reg:SI 4)))
3236 (clobber (reg:SI LR_REGNO))
3237 (clobber (reg:SI 0))
3238 (clobber (match_scratch:CC 0 "=x"))
3239 (clobber (reg:CC CR1_REGNO))]
3240 "! TARGET_POWER && ! TARGET_POWERPC"
3241 "bla __divus"
3242 [(set_attr "type" "idiv")])
3244 (define_insn "quoss_call"
3245 [(set (reg:SI 3)
3246 (div:SI (reg:SI 3) (reg:SI 4)))
3247 (clobber (reg:SI LR_REGNO))]
3248 "! TARGET_POWER && ! TARGET_POWERPC"
3249 "bla __quoss"
3250 [(set_attr "type" "idiv")])
3252 (define_insn "quous_call"
3253 [(set (reg:SI 3)
3254 (udiv:SI (reg:SI 3) (reg:SI 4)))
3255 (clobber (reg:SI LR_REGNO))
3256 (clobber (reg:SI 0))
3257 (clobber (match_scratch:CC 0 "=x"))
3258 (clobber (reg:CC CR1_REGNO))]
3259 "! TARGET_POWER && ! TARGET_POWERPC"
3260 "bla __quous"
3261 [(set_attr "type" "idiv")])
3262 \f
3263 ;; Logical instructions
3264 ;; The logical instructions are mostly combined by using match_operator,
3265 ;; but the plain AND insns are somewhat different because there is no
3266 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
3267 ;; those rotate-and-mask operations. Thus, the AND insns come first.
3269 (define_expand "andsi3"
3270 [(parallel
3271 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3272 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3273 (match_operand:SI 2 "and_operand" "")))
3274 (clobber (match_scratch:CC 3 ""))])]
3275 ""
3276 "")
3278 (define_insn "andsi3_mc"
3279 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3280 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
3281 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
3282 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
3283 "rs6000_gen_cell_microcode"
3284 "@
3285 and %0,%1,%2
3286 {rlinm|rlwinm} %0,%1,0,%m2,%M2
3287 {andil.|andi.} %0,%1,%b2
3288 {andiu.|andis.} %0,%1,%u2"
3289 [(set_attr "type" "*,*,fast_compare,fast_compare")])
3291 (define_insn "andsi3_nomc"
3292 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3293 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3294 (match_operand:SI 2 "and_operand" "?r,T")))
3295 (clobber (match_scratch:CC 3 "=X,X"))]
3296 "!rs6000_gen_cell_microcode"
3297 "@
3298 and %0,%1,%2
3299 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3301 (define_insn "andsi3_internal0_nomc"
3302 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3303 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3304 (match_operand:SI 2 "and_operand" "?r,T")))]
3305 "!rs6000_gen_cell_microcode"
3306 "@
3307 and %0,%1,%2
3308 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3311 ;; Note to set cr's other than cr0 we do the and immediate and then
3312 ;; the test again -- this avoids a mfcr which on the higher end
3313 ;; machines causes an execution serialization
3315 (define_insn "*andsi3_internal2_mc"
3316 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3317 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3318 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3319 (const_int 0)))
3320 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3321 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3322 "TARGET_32BIT && rs6000_gen_cell_microcode"
3323 "@
3324 and. %3,%1,%2
3325 {andil.|andi.} %3,%1,%b2
3326 {andiu.|andis.} %3,%1,%u2
3327 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3328 #
3329 #
3330 #
3331 #"
3332 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3333 compare,compare,compare,compare")
3334 (set_attr "length" "4,4,4,4,8,8,8,8")])
3336 (define_insn "*andsi3_internal3_mc"
3337 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3338 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3339 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3340 (const_int 0)))
3341 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3342 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3343 "TARGET_64BIT && rs6000_gen_cell_microcode"
3344 "@
3345 #
3346 {andil.|andi.} %3,%1,%b2
3347 {andiu.|andis.} %3,%1,%u2
3348 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3349 #
3350 #
3351 #
3352 #"
3353 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3354 compare,compare,compare")
3355 (set_attr "length" "8,4,4,4,8,8,8,8")])
3357 (define_split
3358 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3359 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3360 (match_operand:GPR 2 "and_operand" ""))
3361 (const_int 0)))
3362 (clobber (match_scratch:GPR 3 ""))
3363 (clobber (match_scratch:CC 4 ""))]
3364 "reload_completed"
3365 [(parallel [(set (match_dup 3)
3366 (and:<MODE> (match_dup 1)
3367 (match_dup 2)))
3368 (clobber (match_dup 4))])
3369 (set (match_dup 0)
3370 (compare:CC (match_dup 3)
3371 (const_int 0)))]
3372 "")
3374 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
3375 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
3377 (define_split
3378 [(set (match_operand:CC 0 "cc_reg_operand" "")
3379 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3380 (match_operand:SI 2 "gpc_reg_operand" ""))
3381 (const_int 0)))
3382 (clobber (match_scratch:SI 3 ""))
3383 (clobber (match_scratch:CC 4 ""))]
3384 "TARGET_POWERPC64 && reload_completed"
3385 [(parallel [(set (match_dup 3)
3386 (and:SI (match_dup 1)
3387 (match_dup 2)))
3388 (clobber (match_dup 4))])
3389 (set (match_dup 0)
3390 (compare:CC (match_dup 3)
3391 (const_int 0)))]
3392 "")
3394 (define_insn "*andsi3_internal4"
3395 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3396 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3397 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3398 (const_int 0)))
3399 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3400 (and:SI (match_dup 1)
3401 (match_dup 2)))
3402 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3403 "TARGET_32BIT && rs6000_gen_cell_microcode"
3404 "@
3405 and. %0,%1,%2
3406 {andil.|andi.} %0,%1,%b2
3407 {andiu.|andis.} %0,%1,%u2
3408 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3409 #
3410 #
3411 #
3412 #"
3413 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3414 compare,compare,compare,compare")
3415 (set_attr "length" "4,4,4,4,8,8,8,8")])
3417 (define_insn "*andsi3_internal5_mc"
3418 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3419 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3420 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3421 (const_int 0)))
3422 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3423 (and:SI (match_dup 1)
3424 (match_dup 2)))
3425 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3426 "TARGET_64BIT && rs6000_gen_cell_microcode"
3427 "@
3428 #
3429 {andil.|andi.} %0,%1,%b2
3430 {andiu.|andis.} %0,%1,%u2
3431 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3432 #
3433 #
3434 #
3435 #"
3436 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3437 compare,compare,compare")
3438 (set_attr "length" "8,4,4,4,8,8,8,8")])
3440 (define_split
3441 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3442 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3443 (match_operand:SI 2 "and_operand" ""))
3444 (const_int 0)))
3445 (set (match_operand:SI 0 "gpc_reg_operand" "")
3446 (and:SI (match_dup 1)
3447 (match_dup 2)))
3448 (clobber (match_scratch:CC 4 ""))]
3449 "reload_completed"
3450 [(parallel [(set (match_dup 0)
3451 (and:SI (match_dup 1)
3452 (match_dup 2)))
3453 (clobber (match_dup 4))])
3454 (set (match_dup 3)
3455 (compare:CC (match_dup 0)
3456 (const_int 0)))]
3457 "")
3459 (define_split
3460 [(set (match_operand:CC 3 "cc_reg_operand" "")
3461 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3462 (match_operand:SI 2 "gpc_reg_operand" ""))
3463 (const_int 0)))
3464 (set (match_operand:SI 0 "gpc_reg_operand" "")
3465 (and:SI (match_dup 1)
3466 (match_dup 2)))
3467 (clobber (match_scratch:CC 4 ""))]
3468 "TARGET_POWERPC64 && reload_completed"
3469 [(parallel [(set (match_dup 0)
3470 (and:SI (match_dup 1)
3471 (match_dup 2)))
3472 (clobber (match_dup 4))])
3473 (set (match_dup 3)
3474 (compare:CC (match_dup 0)
3475 (const_int 0)))]
3476 "")
3478 ;; Handle the PowerPC64 rlwinm corner case
3480 (define_insn_and_split "*andsi3_internal6"
3481 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3482 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3483 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3484 "TARGET_POWERPC64"
3485 "#"
3486 "TARGET_POWERPC64"
3487 [(set (match_dup 0)
3488 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3489 (match_dup 4)))
3490 (set (match_dup 0)
3491 (rotate:SI (match_dup 0) (match_dup 5)))]
3492 "
3493 {
3494 int mb = extract_MB (operands[2]);
3495 int me = extract_ME (operands[2]);
3496 operands[3] = GEN_INT (me + 1);
3497 operands[5] = GEN_INT (32 - (me + 1));
3498 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3499 }"
3500 [(set_attr "length" "8")])
3502 (define_expand "iorsi3"
3503 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3504 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3505 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3506 ""
3507 "
3508 {
3509 if (GET_CODE (operands[2]) == CONST_INT
3510 && ! logical_operand (operands[2], SImode))
3511 {
3512 HOST_WIDE_INT value = INTVAL (operands[2]);
3513 rtx tmp = ((!can_create_pseudo_p ()
3514 || rtx_equal_p (operands[0], operands[1]))
3515 ? operands[0] : gen_reg_rtx (SImode));
3517 emit_insn (gen_iorsi3 (tmp, operands[1],
3518 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3519 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3520 DONE;
3521 }
3522 }")
3524 (define_expand "xorsi3"
3525 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3526 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3527 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3528 ""
3529 "
3530 {
3531 if (GET_CODE (operands[2]) == CONST_INT
3532 && ! logical_operand (operands[2], SImode))
3533 {
3534 HOST_WIDE_INT value = INTVAL (operands[2]);
3535 rtx tmp = ((!can_create_pseudo_p ()
3536 || rtx_equal_p (operands[0], operands[1]))
3537 ? operands[0] : gen_reg_rtx (SImode));
3539 emit_insn (gen_xorsi3 (tmp, operands[1],
3540 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3541 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3542 DONE;
3543 }
3544 }")
3546 (define_insn "*boolsi3_internal1"
3547 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3548 (match_operator:SI 3 "boolean_or_operator"
3549 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3550 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3551 ""
3552 "@
3553 %q3 %0,%1,%2
3554 {%q3il|%q3i} %0,%1,%b2
3555 {%q3iu|%q3is} %0,%1,%u2")
3557 (define_insn "*boolsi3_internal2"
3558 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3559 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3560 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3561 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3562 (const_int 0)))
3563 (clobber (match_scratch:SI 3 "=r,r"))]
3564 "TARGET_32BIT"
3565 "@
3566 %q4. %3,%1,%2
3567 #"
3568 [(set_attr "type" "fast_compare,compare")
3569 (set_attr "length" "4,8")])
3571 (define_split
3572 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3573 (compare:CC (match_operator:SI 4 "boolean_operator"
3574 [(match_operand:SI 1 "gpc_reg_operand" "")
3575 (match_operand:SI 2 "gpc_reg_operand" "")])
3576 (const_int 0)))
3577 (clobber (match_scratch:SI 3 ""))]
3578 "TARGET_32BIT && reload_completed"
3579 [(set (match_dup 3) (match_dup 4))
3580 (set (match_dup 0)
3581 (compare:CC (match_dup 3)
3582 (const_int 0)))]
3583 "")
3585 (define_insn "*boolsi3_internal3"
3586 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3587 (compare:CC (match_operator:SI 4 "boolean_operator"
3588 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3589 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3590 (const_int 0)))
3591 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3592 (match_dup 4))]
3593 "TARGET_32BIT"
3594 "@
3595 %q4. %0,%1,%2
3596 #"
3597 [(set_attr "type" "fast_compare,compare")
3598 (set_attr "length" "4,8")])
3600 (define_split
3601 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3602 (compare:CC (match_operator:SI 4 "boolean_operator"
3603 [(match_operand:SI 1 "gpc_reg_operand" "")
3604 (match_operand:SI 2 "gpc_reg_operand" "")])
3605 (const_int 0)))
3606 (set (match_operand:SI 0 "gpc_reg_operand" "")
3607 (match_dup 4))]
3608 "TARGET_32BIT && reload_completed"
3609 [(set (match_dup 0) (match_dup 4))
3610 (set (match_dup 3)
3611 (compare:CC (match_dup 0)
3612 (const_int 0)))]
3613 "")
3615 ;; Split a logical operation that we can't do in one insn into two insns,
3616 ;; each of which does one 16-bit part. This is used by combine.
3618 (define_split
3619 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3620 (match_operator:SI 3 "boolean_or_operator"
3621 [(match_operand:SI 1 "gpc_reg_operand" "")
3622 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3623 ""
3624 [(set (match_dup 0) (match_dup 4))
3625 (set (match_dup 0) (match_dup 5))]
3626 "
3627 {
3628 rtx i;
3629 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3630 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3631 operands[1], i);
3632 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3633 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3634 operands[0], i);
3635 }")
3637 (define_insn "*boolcsi3_internal1"
3638 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3639 (match_operator:SI 3 "boolean_operator"
3640 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3641 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3642 ""
3643 "%q3 %0,%2,%1")
3645 (define_insn "*boolcsi3_internal2"
3646 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3647 (compare:CC (match_operator:SI 4 "boolean_operator"
3648 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3649 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3650 (const_int 0)))
3651 (clobber (match_scratch:SI 3 "=r,r"))]
3652 "TARGET_32BIT"
3653 "@
3654 %q4. %3,%2,%1
3655 #"
3656 [(set_attr "type" "compare")
3657 (set_attr "length" "4,8")])
3659 (define_split
3660 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3661 (compare:CC (match_operator:SI 4 "boolean_operator"
3662 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3663 (match_operand:SI 2 "gpc_reg_operand" "")])
3664 (const_int 0)))
3665 (clobber (match_scratch:SI 3 ""))]
3666 "TARGET_32BIT && reload_completed"
3667 [(set (match_dup 3) (match_dup 4))
3668 (set (match_dup 0)
3669 (compare:CC (match_dup 3)
3670 (const_int 0)))]
3671 "")
3673 (define_insn "*boolcsi3_internal3"
3674 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3675 (compare:CC (match_operator:SI 4 "boolean_operator"
3676 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3677 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3678 (const_int 0)))
3679 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3680 (match_dup 4))]
3681 "TARGET_32BIT"
3682 "@
3683 %q4. %0,%2,%1
3684 #"
3685 [(set_attr "type" "compare")
3686 (set_attr "length" "4,8")])
3688 (define_split
3689 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3690 (compare:CC (match_operator:SI 4 "boolean_operator"
3691 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3692 (match_operand:SI 2 "gpc_reg_operand" "")])
3693 (const_int 0)))
3694 (set (match_operand:SI 0 "gpc_reg_operand" "")
3695 (match_dup 4))]
3696 "TARGET_32BIT && reload_completed"
3697 [(set (match_dup 0) (match_dup 4))
3698 (set (match_dup 3)
3699 (compare:CC (match_dup 0)
3700 (const_int 0)))]
3701 "")
3703 (define_insn "*boolccsi3_internal1"
3704 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3705 (match_operator:SI 3 "boolean_operator"
3706 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3707 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3708 ""
3709 "%q3 %0,%1,%2")
3711 (define_insn "*boolccsi3_internal2"
3712 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3713 (compare:CC (match_operator:SI 4 "boolean_operator"
3714 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3715 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3716 (const_int 0)))
3717 (clobber (match_scratch:SI 3 "=r,r"))]
3718 "TARGET_32BIT"
3719 "@
3720 %q4. %3,%1,%2
3721 #"
3722 [(set_attr "type" "fast_compare,compare")
3723 (set_attr "length" "4,8")])
3725 (define_split
3726 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3727 (compare:CC (match_operator:SI 4 "boolean_operator"
3728 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3729 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3730 (const_int 0)))
3731 (clobber (match_scratch:SI 3 ""))]
3732 "TARGET_32BIT && reload_completed"
3733 [(set (match_dup 3) (match_dup 4))
3734 (set (match_dup 0)
3735 (compare:CC (match_dup 3)
3736 (const_int 0)))]
3737 "")
3739 (define_insn "*boolccsi3_internal3"
3740 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3741 (compare:CC (match_operator:SI 4 "boolean_operator"
3742 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3743 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3744 (const_int 0)))
3745 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3746 (match_dup 4))]
3747 "TARGET_32BIT"
3748 "@
3749 %q4. %0,%1,%2
3750 #"
3751 [(set_attr "type" "fast_compare,compare")
3752 (set_attr "length" "4,8")])
3754 (define_split
3755 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3756 (compare:CC (match_operator:SI 4 "boolean_operator"
3757 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3758 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3759 (const_int 0)))
3760 (set (match_operand:SI 0 "gpc_reg_operand" "")
3761 (match_dup 4))]
3762 "TARGET_32BIT && reload_completed"
3763 [(set (match_dup 0) (match_dup 4))
3764 (set (match_dup 3)
3765 (compare:CC (match_dup 0)
3766 (const_int 0)))]
3767 "")
3769 ;; maskir insn. We need four forms because things might be in arbitrary
3770 ;; orders. Don't define forms that only set CR fields because these
3771 ;; would modify an input register.
3773 (define_insn "*maskir_internal1"
3774 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3775 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3776 (match_operand:SI 1 "gpc_reg_operand" "0"))
3777 (and:SI (match_dup 2)
3778 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3779 "TARGET_POWER"
3780 "maskir %0,%3,%2")
3782 (define_insn "*maskir_internal2"
3783 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3784 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3785 (match_operand:SI 1 "gpc_reg_operand" "0"))
3786 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3787 (match_dup 2))))]
3788 "TARGET_POWER"
3789 "maskir %0,%3,%2")
3791 (define_insn "*maskir_internal3"
3792 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3793 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3794 (match_operand:SI 3 "gpc_reg_operand" "r"))
3795 (and:SI (not:SI (match_dup 2))
3796 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3797 "TARGET_POWER"
3798 "maskir %0,%3,%2")
3800 (define_insn "*maskir_internal4"
3801 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3802 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3803 (match_operand:SI 2 "gpc_reg_operand" "r"))
3804 (and:SI (not:SI (match_dup 2))
3805 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3806 "TARGET_POWER"
3807 "maskir %0,%3,%2")
3809 (define_insn "*maskir_internal5"
3810 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3811 (compare:CC
3812 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3813 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3814 (and:SI (match_dup 2)
3815 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3816 (const_int 0)))
3817 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3818 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3819 (and:SI (match_dup 2) (match_dup 3))))]
3820 "TARGET_POWER"
3821 "@
3822 maskir. %0,%3,%2
3823 #"
3824 [(set_attr "type" "compare")
3825 (set_attr "length" "4,8")])
3827 (define_split
3828 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3829 (compare:CC
3830 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3831 (match_operand:SI 1 "gpc_reg_operand" ""))
3832 (and:SI (match_dup 2)
3833 (match_operand:SI 3 "gpc_reg_operand" "")))
3834 (const_int 0)))
3835 (set (match_operand:SI 0 "gpc_reg_operand" "")
3836 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3837 (and:SI (match_dup 2) (match_dup 3))))]
3838 "TARGET_POWER && reload_completed"
3839 [(set (match_dup 0)
3840 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3841 (and:SI (match_dup 2) (match_dup 3))))
3842 (set (match_dup 4)
3843 (compare:CC (match_dup 0)
3844 (const_int 0)))]
3845 "")
3847 (define_insn "*maskir_internal6"
3848 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3849 (compare:CC
3850 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3851 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3852 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3853 (match_dup 2)))
3854 (const_int 0)))
3855 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3856 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3857 (and:SI (match_dup 3) (match_dup 2))))]
3858 "TARGET_POWER"
3859 "@
3860 maskir. %0,%3,%2
3861 #"
3862 [(set_attr "type" "compare")
3863 (set_attr "length" "4,8")])
3865 (define_split
3866 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3867 (compare:CC
3868 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3869 (match_operand:SI 1 "gpc_reg_operand" ""))
3870 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3871 (match_dup 2)))
3872 (const_int 0)))
3873 (set (match_operand:SI 0 "gpc_reg_operand" "")
3874 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3875 (and:SI (match_dup 3) (match_dup 2))))]
3876 "TARGET_POWER && reload_completed"
3877 [(set (match_dup 0)
3878 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3879 (and:SI (match_dup 3) (match_dup 2))))
3880 (set (match_dup 4)
3881 (compare:CC (match_dup 0)
3882 (const_int 0)))]
3883 "")
3885 (define_insn "*maskir_internal7"
3886 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3887 (compare:CC
3888 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3889 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3890 (and:SI (not:SI (match_dup 2))
3891 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3892 (const_int 0)))
3893 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3894 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3895 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3896 "TARGET_POWER"
3897 "@
3898 maskir. %0,%3,%2
3899 #"
3900 [(set_attr "type" "compare")
3901 (set_attr "length" "4,8")])
3903 (define_split
3904 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3905 (compare:CC
3906 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3907 (match_operand:SI 3 "gpc_reg_operand" ""))
3908 (and:SI (not:SI (match_dup 2))
3909 (match_operand:SI 1 "gpc_reg_operand" "")))
3910 (const_int 0)))
3911 (set (match_operand:SI 0 "gpc_reg_operand" "")
3912 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3913 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3914 "TARGET_POWER && reload_completed"
3915 [(set (match_dup 0)
3916 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3917 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3918 (set (match_dup 4)
3919 (compare:CC (match_dup 0)
3920 (const_int 0)))]
3921 "")
3923 (define_insn "*maskir_internal8"
3924 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3925 (compare:CC
3926 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3927 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3928 (and:SI (not:SI (match_dup 2))
3929 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3930 (const_int 0)))
3931 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3932 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3933 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3934 "TARGET_POWER"
3935 "@
3936 maskir. %0,%3,%2
3937 #"
3938 [(set_attr "type" "compare")
3939 (set_attr "length" "4,8")])
3941 (define_split
3942 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3943 (compare:CC
3944 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3945 (match_operand:SI 2 "gpc_reg_operand" ""))
3946 (and:SI (not:SI (match_dup 2))
3947 (match_operand:SI 1 "gpc_reg_operand" "")))
3948 (const_int 0)))
3949 (set (match_operand:SI 0 "gpc_reg_operand" "")
3950 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3951 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3952 "TARGET_POWER && reload_completed"
3953 [(set (match_dup 0)
3954 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3955 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3956 (set (match_dup 4)
3957 (compare:CC (match_dup 0)
3958 (const_int 0)))]
3959 "")
3960 \f
3961 ;; Rotate and shift insns, in all their variants. These support shifts,
3962 ;; field inserts and extracts, and various combinations thereof.
3963 (define_expand "insv"
3964 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3965 (match_operand:SI 1 "const_int_operand" "")
3966 (match_operand:SI 2 "const_int_operand" ""))
3967 (match_operand 3 "gpc_reg_operand" ""))]
3968 ""
3969 "
3970 {
3971 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3972 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3973 compiler if the address of the structure is taken later. Likewise, do
3974 not handle invalid E500 subregs. */
3975 if (GET_CODE (operands[0]) == SUBREG
3976 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3977 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3978 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3979 FAIL;
3981 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3982 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3983 else
3984 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3985 DONE;
3986 }")
3988 (define_insn "insvsi"
3989 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3990 (match_operand:SI 1 "const_int_operand" "i")
3991 (match_operand:SI 2 "const_int_operand" "i"))
3992 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3993 ""
3994 "*
3995 {
3996 int start = INTVAL (operands[2]) & 31;
3997 int size = INTVAL (operands[1]) & 31;
3999 operands[4] = GEN_INT (32 - start - size);
4000 operands[1] = GEN_INT (start + size - 1);
4001 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4002 }"
4003 [(set_attr "type" "insert_word")])
4005 (define_insn "*insvsi_internal1"
4006 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4007 (match_operand:SI 1 "const_int_operand" "i")
4008 (match_operand:SI 2 "const_int_operand" "i"))
4009 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4010 (match_operand:SI 4 "const_int_operand" "i")))]
4011 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4012 "*
4013 {
4014 int shift = INTVAL (operands[4]) & 31;
4015 int start = INTVAL (operands[2]) & 31;
4016 int size = INTVAL (operands[1]) & 31;
4018 operands[4] = GEN_INT (shift - start - size);
4019 operands[1] = GEN_INT (start + size - 1);
4020 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4021 }"
4022 [(set_attr "type" "insert_word")])
4024 (define_insn "*insvsi_internal2"
4025 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4026 (match_operand:SI 1 "const_int_operand" "i")
4027 (match_operand:SI 2 "const_int_operand" "i"))
4028 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4029 (match_operand:SI 4 "const_int_operand" "i")))]
4030 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4031 "*
4032 {
4033 int shift = INTVAL (operands[4]) & 31;
4034 int start = INTVAL (operands[2]) & 31;
4035 int size = INTVAL (operands[1]) & 31;
4037 operands[4] = GEN_INT (32 - shift - start - size);
4038 operands[1] = GEN_INT (start + size - 1);
4039 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4040 }"
4041 [(set_attr "type" "insert_word")])
4043 (define_insn "*insvsi_internal3"
4044 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4045 (match_operand:SI 1 "const_int_operand" "i")
4046 (match_operand:SI 2 "const_int_operand" "i"))
4047 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4048 (match_operand:SI 4 "const_int_operand" "i")))]
4049 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
4050 "*
4051 {
4052 int shift = INTVAL (operands[4]) & 31;
4053 int start = INTVAL (operands[2]) & 31;
4054 int size = INTVAL (operands[1]) & 31;
4056 operands[4] = GEN_INT (32 - shift - start - size);
4057 operands[1] = GEN_INT (start + size - 1);
4058 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4059 }"
4060 [(set_attr "type" "insert_word")])
4062 (define_insn "*insvsi_internal4"
4063 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4064 (match_operand:SI 1 "const_int_operand" "i")
4065 (match_operand:SI 2 "const_int_operand" "i"))
4066 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4067 (match_operand:SI 4 "const_int_operand" "i")
4068 (match_operand:SI 5 "const_int_operand" "i")))]
4069 "INTVAL (operands[4]) >= INTVAL (operands[1])"
4070 "*
4071 {
4072 int extract_start = INTVAL (operands[5]) & 31;
4073 int extract_size = INTVAL (operands[4]) & 31;
4074 int insert_start = INTVAL (operands[2]) & 31;
4075 int insert_size = INTVAL (operands[1]) & 31;
4077 /* Align extract field with insert field */
4078 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
4079 operands[1] = GEN_INT (insert_start + insert_size - 1);
4080 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
4081 }"
4082 [(set_attr "type" "insert_word")])
4084 ;; combine patterns for rlwimi
4085 (define_insn "*insvsi_internal5"
4086 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4087 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4088 (match_operand:SI 1 "mask_operand" "i"))
4089 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4090 (match_operand:SI 2 "const_int_operand" "i"))
4091 (match_operand:SI 5 "mask_operand" "i"))))]
4092 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4093 "*
4094 {
4095 int me = extract_ME(operands[5]);
4096 int mb = extract_MB(operands[5]);
4097 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4098 operands[2] = GEN_INT(mb);
4099 operands[1] = GEN_INT(me);
4100 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4101 }"
4102 [(set_attr "type" "insert_word")])
4104 (define_insn "*insvsi_internal6"
4105 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4106 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
4107 (match_operand:SI 2 "const_int_operand" "i"))
4108 (match_operand:SI 5 "mask_operand" "i"))
4109 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
4110 (match_operand:SI 1 "mask_operand" "i"))))]
4111 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
4112 "*
4113 {
4114 int me = extract_ME(operands[5]);
4115 int mb = extract_MB(operands[5]);
4116 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
4117 operands[2] = GEN_INT(mb);
4118 operands[1] = GEN_INT(me);
4119 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
4120 }"
4121 [(set_attr "type" "insert_word")])
4123 (define_insn "insvdi"
4124 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4125 (match_operand:SI 1 "const_int_operand" "i")
4126 (match_operand:SI 2 "const_int_operand" "i"))
4127 (match_operand:DI 3 "gpc_reg_operand" "r"))]
4128 "TARGET_POWERPC64"
4129 "*
4130 {
4131 int start = INTVAL (operands[2]) & 63;
4132 int size = INTVAL (operands[1]) & 63;
4134 operands[1] = GEN_INT (64 - start - size);
4135 return \"rldimi %0,%3,%H1,%H2\";
4136 }"
4137 [(set_attr "type" "insert_dword")])
4139 (define_insn "*insvdi_internal2"
4140 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4141 (match_operand:SI 1 "const_int_operand" "i")
4142 (match_operand:SI 2 "const_int_operand" "i"))
4143 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4144 (match_operand:SI 4 "const_int_operand" "i")))]
4145 "TARGET_POWERPC64
4146 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4147 "*
4148 {
4149 int shift = INTVAL (operands[4]) & 63;
4150 int start = (INTVAL (operands[2]) & 63) - 32;
4151 int size = INTVAL (operands[1]) & 63;
4153 operands[4] = GEN_INT (64 - shift - start - size);
4154 operands[2] = GEN_INT (start);
4155 operands[1] = GEN_INT (start + size - 1);
4156 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4157 }")
4159 (define_insn "*insvdi_internal3"
4160 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
4161 (match_operand:SI 1 "const_int_operand" "i")
4162 (match_operand:SI 2 "const_int_operand" "i"))
4163 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
4164 (match_operand:SI 4 "const_int_operand" "i")))]
4165 "TARGET_POWERPC64
4166 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
4167 "*
4168 {
4169 int shift = INTVAL (operands[4]) & 63;
4170 int start = (INTVAL (operands[2]) & 63) - 32;
4171 int size = INTVAL (operands[1]) & 63;
4173 operands[4] = GEN_INT (64 - shift - start - size);
4174 operands[2] = GEN_INT (start);
4175 operands[1] = GEN_INT (start + size - 1);
4176 return \"rlwimi %0,%3,%h4,%h2,%h1\";
4177 }")
4179 (define_expand "extzv"
4180 [(set (match_operand 0 "gpc_reg_operand" "")
4181 (zero_extract (match_operand 1 "gpc_reg_operand" "")
4182 (match_operand:SI 2 "const_int_operand" "")
4183 (match_operand:SI 3 "const_int_operand" "")))]
4184 ""
4185 "
4186 {
4187 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
4188 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
4189 compiler if the address of the structure is taken later. */
4190 if (GET_CODE (operands[0]) == SUBREG
4191 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
4192 FAIL;
4194 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
4195 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
4196 else
4197 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
4198 DONE;
4199 }")
4201 (define_insn "extzvsi"
4202 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4203 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4204 (match_operand:SI 2 "const_int_operand" "i")
4205 (match_operand:SI 3 "const_int_operand" "i")))]
4206 ""
4207 "*
4208 {
4209 int start = INTVAL (operands[3]) & 31;
4210 int size = INTVAL (operands[2]) & 31;
4212 if (start + size >= 32)
4213 operands[3] = const0_rtx;
4214 else
4215 operands[3] = GEN_INT (start + size);
4216 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
4217 }")
4219 (define_insn "*extzvsi_internal1"
4220 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4221 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4222 (match_operand:SI 2 "const_int_operand" "i,i")
4223 (match_operand:SI 3 "const_int_operand" "i,i"))
4224 (const_int 0)))
4225 (clobber (match_scratch:SI 4 "=r,r"))]
4226 ""
4227 "*
4228 {
4229 int start = INTVAL (operands[3]) & 31;
4230 int size = INTVAL (operands[2]) & 31;
4232 /* Force split for non-cc0 compare. */
4233 if (which_alternative == 1)
4234 return \"#\";
4236 /* If the bit-field being tested fits in the upper or lower half of a
4237 word, it is possible to use andiu. or andil. to test it. This is
4238 useful because the condition register set-use delay is smaller for
4239 andi[ul]. than for rlinm. This doesn't work when the starting bit
4240 position is 0 because the LT and GT bits may be set wrong. */
4242 if ((start > 0 && start + size <= 16) || start >= 16)
4243 {
4244 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
4245 - (1 << (16 - (start & 15) - size))));
4246 if (start < 16)
4247 return \"{andiu.|andis.} %4,%1,%3\";
4248 else
4249 return \"{andil.|andi.} %4,%1,%3\";
4250 }
4252 if (start + size >= 32)
4253 operands[3] = const0_rtx;
4254 else
4255 operands[3] = GEN_INT (start + size);
4256 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
4257 }"
4258 [(set_attr "type" "delayed_compare")
4259 (set_attr "length" "4,8")])
4261 (define_split
4262 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4263 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4264 (match_operand:SI 2 "const_int_operand" "")
4265 (match_operand:SI 3 "const_int_operand" ""))
4266 (const_int 0)))
4267 (clobber (match_scratch:SI 4 ""))]
4268 "reload_completed"
4269 [(set (match_dup 4)
4270 (zero_extract:SI (match_dup 1) (match_dup 2)
4271 (match_dup 3)))
4272 (set (match_dup 0)
4273 (compare:CC (match_dup 4)
4274 (const_int 0)))]
4275 "")
4277 (define_insn "*extzvsi_internal2"
4278 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4279 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4280 (match_operand:SI 2 "const_int_operand" "i,i")
4281 (match_operand:SI 3 "const_int_operand" "i,i"))
4282 (const_int 0)))
4283 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4284 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4285 ""
4286 "*
4287 {
4288 int start = INTVAL (operands[3]) & 31;
4289 int size = INTVAL (operands[2]) & 31;
4291 /* Force split for non-cc0 compare. */
4292 if (which_alternative == 1)
4293 return \"#\";
4295 /* Since we are using the output value, we can't ignore any need for
4296 a shift. The bit-field must end at the LSB. */
4297 if (start >= 16 && start + size == 32)
4298 {
4299 operands[3] = GEN_INT ((1 << size) - 1);
4300 return \"{andil.|andi.} %0,%1,%3\";
4301 }
4303 if (start + size >= 32)
4304 operands[3] = const0_rtx;
4305 else
4306 operands[3] = GEN_INT (start + size);
4307 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
4308 }"
4309 [(set_attr "type" "delayed_compare")
4310 (set_attr "length" "4,8")])
4312 (define_split
4313 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4314 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
4315 (match_operand:SI 2 "const_int_operand" "")
4316 (match_operand:SI 3 "const_int_operand" ""))
4317 (const_int 0)))
4318 (set (match_operand:SI 0 "gpc_reg_operand" "")
4319 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
4320 "reload_completed"
4321 [(set (match_dup 0)
4322 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
4323 (set (match_dup 4)
4324 (compare:CC (match_dup 0)
4325 (const_int 0)))]
4326 "")
4328 (define_insn "extzvdi"
4329 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
4330 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4331 (match_operand:SI 2 "const_int_operand" "i")
4332 (match_operand:SI 3 "const_int_operand" "i")))]
4333 "TARGET_POWERPC64"
4334 "*
4335 {
4336 int start = INTVAL (operands[3]) & 63;
4337 int size = INTVAL (operands[2]) & 63;
4339 if (start + size >= 64)
4340 operands[3] = const0_rtx;
4341 else
4342 operands[3] = GEN_INT (start + size);
4343 operands[2] = GEN_INT (64 - size);
4344 return \"rldicl %0,%1,%3,%2\";
4345 }")
4347 (define_insn "*extzvdi_internal1"
4348 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
4349 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4350 (match_operand:SI 2 "const_int_operand" "i")
4351 (match_operand:SI 3 "const_int_operand" "i"))
4352 (const_int 0)))
4353 (clobber (match_scratch:DI 4 "=r"))]
4354 "TARGET_64BIT && rs6000_gen_cell_microcode"
4355 "*
4356 {
4357 int start = INTVAL (operands[3]) & 63;
4358 int size = INTVAL (operands[2]) & 63;
4360 if (start + size >= 64)
4361 operands[3] = const0_rtx;
4362 else
4363 operands[3] = GEN_INT (start + size);
4364 operands[2] = GEN_INT (64 - size);
4365 return \"rldicl. %4,%1,%3,%2\";
4366 }"
4367 [(set_attr "type" "compare")])
4369 (define_insn "*extzvdi_internal2"
4370 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
4371 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
4372 (match_operand:SI 2 "const_int_operand" "i")
4373 (match_operand:SI 3 "const_int_operand" "i"))
4374 (const_int 0)))
4375 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
4376 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
4377 "TARGET_64BIT && rs6000_gen_cell_microcode"
4378 "*
4379 {
4380 int start = INTVAL (operands[3]) & 63;
4381 int size = INTVAL (operands[2]) & 63;
4383 if (start + size >= 64)
4384 operands[3] = const0_rtx;
4385 else
4386 operands[3] = GEN_INT (start + size);
4387 operands[2] = GEN_INT (64 - size);
4388 return \"rldicl. %0,%1,%3,%2\";
4389 }"
4390 [(set_attr "type" "compare")])
4392 (define_insn "rotlsi3"
4393 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4394 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4395 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4396 ""
4397 "@
4398 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4399 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4400 [(set_attr "type" "var_shift_rotate,integer")])
4402 (define_insn "*rotlsi3_64"
4403 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4404 (zero_extend:DI
4405 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4406 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4407 "TARGET_64BIT"
4408 "@
4409 {rlnm|rlwnm} %0,%1,%2,0xffffffff
4410 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
4411 [(set_attr "type" "var_shift_rotate,integer")])
4413 (define_insn "*rotlsi3_internal2"
4414 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4415 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4416 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4417 (const_int 0)))
4418 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4419 ""
4420 "@
4421 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
4422 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
4423 #
4424 #"
4425 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4426 (set_attr "length" "4,4,8,8")])
4428 (define_split
4429 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4430 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4431 (match_operand:SI 2 "reg_or_cint_operand" ""))
4432 (const_int 0)))
4433 (clobber (match_scratch:SI 3 ""))]
4434 "reload_completed"
4435 [(set (match_dup 3)
4436 (rotate:SI (match_dup 1) (match_dup 2)))
4437 (set (match_dup 0)
4438 (compare:CC (match_dup 3)
4439 (const_int 0)))]
4440 "")
4442 (define_insn "*rotlsi3_internal3"
4443 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4444 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4445 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4446 (const_int 0)))
4447 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4448 (rotate:SI (match_dup 1) (match_dup 2)))]
4449 ""
4450 "@
4451 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
4452 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
4453 #
4454 #"
4455 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4456 (set_attr "length" "4,4,8,8")])
4458 (define_split
4459 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4460 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4461 (match_operand:SI 2 "reg_or_cint_operand" ""))
4462 (const_int 0)))
4463 (set (match_operand:SI 0 "gpc_reg_operand" "")
4464 (rotate:SI (match_dup 1) (match_dup 2)))]
4465 "reload_completed"
4466 [(set (match_dup 0)
4467 (rotate:SI (match_dup 1) (match_dup 2)))
4468 (set (match_dup 3)
4469 (compare:CC (match_dup 0)
4470 (const_int 0)))]
4471 "")
4473 (define_insn "*rotlsi3_internal4"
4474 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4475 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4476 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
4477 (match_operand:SI 3 "mask_operand" "n,n")))]
4478 ""
4479 "@
4480 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
4481 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
4482 [(set_attr "type" "var_shift_rotate,integer")])
4484 (define_insn "*rotlsi3_internal5"
4485 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4486 (compare:CC (and:SI
4487 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4488 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4489 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4490 (const_int 0)))
4491 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
4492 ""
4493 "@
4494 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
4495 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4496 #
4497 #"
4498 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4499 (set_attr "length" "4,4,8,8")])
4501 (define_split
4502 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4503 (compare:CC (and:SI
4504 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4505 (match_operand:SI 2 "reg_or_cint_operand" ""))
4506 (match_operand:SI 3 "mask_operand" ""))
4507 (const_int 0)))
4508 (clobber (match_scratch:SI 4 ""))]
4509 "reload_completed"
4510 [(set (match_dup 4)
4511 (and:SI (rotate:SI (match_dup 1)
4512 (match_dup 2))
4513 (match_dup 3)))
4514 (set (match_dup 0)
4515 (compare:CC (match_dup 4)
4516 (const_int 0)))]
4517 "")
4519 (define_insn "*rotlsi3_internal6"
4520 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
4521 (compare:CC (and:SI
4522 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4523 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4524 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4525 (const_int 0)))
4526 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4527 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4528 ""
4529 "@
4530 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4531 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4532 #
4533 #"
4534 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4535 (set_attr "length" "4,4,8,8")])
4537 (define_split
4538 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4539 (compare:CC (and:SI
4540 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4541 (match_operand:SI 2 "reg_or_cint_operand" ""))
4542 (match_operand:SI 3 "mask_operand" ""))
4543 (const_int 0)))
4544 (set (match_operand:SI 0 "gpc_reg_operand" "")
4545 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4546 "reload_completed"
4547 [(set (match_dup 0)
4548 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4549 (set (match_dup 4)
4550 (compare:CC (match_dup 0)
4551 (const_int 0)))]
4552 "")
4554 (define_insn "*rotlsi3_internal7"
4555 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4556 (zero_extend:SI
4557 (subreg:QI
4558 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4559 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4560 ""
4561 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff"
4562 [(set (attr "cell_micro")
4563 (if_then_else (match_operand:SI 2 "const_int_operand" "")
4564 (const_string "not")
4565 (const_string "always")))])
4567 (define_insn "*rotlsi3_internal8"
4568 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4569 (compare:CC (zero_extend:SI
4570 (subreg:QI
4571 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4572 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4573 (const_int 0)))
4574 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4575 ""
4576 "@
4577 {rlnm.|rlwnm.} %3,%1,%2,0xff
4578 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4579 #
4580 #"
4581 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4582 (set_attr "length" "4,4,8,8")])
4584 (define_split
4585 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4586 (compare:CC (zero_extend:SI
4587 (subreg:QI
4588 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4589 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4590 (const_int 0)))
4591 (clobber (match_scratch:SI 3 ""))]
4592 "reload_completed"
4593 [(set (match_dup 3)
4594 (zero_extend:SI (subreg:QI
4595 (rotate:SI (match_dup 1)
4596 (match_dup 2)) 0)))
4597 (set (match_dup 0)
4598 (compare:CC (match_dup 3)
4599 (const_int 0)))]
4600 "")
4602 (define_insn "*rotlsi3_internal9"
4603 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4604 (compare:CC (zero_extend:SI
4605 (subreg:QI
4606 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4607 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4608 (const_int 0)))
4609 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4610 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4611 ""
4612 "@
4613 {rlnm.|rlwnm.} %0,%1,%2,0xff
4614 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4615 #
4616 #"
4617 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4618 (set_attr "length" "4,4,8,8")])
4620 (define_split
4621 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4622 (compare:CC (zero_extend:SI
4623 (subreg:QI
4624 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4625 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4626 (const_int 0)))
4627 (set (match_operand:SI 0 "gpc_reg_operand" "")
4628 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4629 "reload_completed"
4630 [(set (match_dup 0)
4631 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4632 (set (match_dup 3)
4633 (compare:CC (match_dup 0)
4634 (const_int 0)))]
4635 "")
4637 (define_insn "*rotlsi3_internal10"
4638 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4639 (zero_extend:SI
4640 (subreg:HI
4641 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4642 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4643 ""
4644 "@
4645 {rlnm|rlwnm} %0,%1,%2,0xffff
4646 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4647 [(set_attr "type" "var_shift_rotate,integer")])
4650 (define_insn "*rotlsi3_internal11"
4651 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4652 (compare:CC (zero_extend:SI
4653 (subreg:HI
4654 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4655 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4656 (const_int 0)))
4657 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4658 ""
4659 "@
4660 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4661 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4662 #
4663 #"
4664 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4665 (set_attr "length" "4,4,8,8")])
4667 (define_split
4668 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4669 (compare:CC (zero_extend:SI
4670 (subreg:HI
4671 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4672 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4673 (const_int 0)))
4674 (clobber (match_scratch:SI 3 ""))]
4675 "reload_completed"
4676 [(set (match_dup 3)
4677 (zero_extend:SI (subreg:HI
4678 (rotate:SI (match_dup 1)
4679 (match_dup 2)) 0)))
4680 (set (match_dup 0)
4681 (compare:CC (match_dup 3)
4682 (const_int 0)))]
4683 "")
4685 (define_insn "*rotlsi3_internal12"
4686 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4687 (compare:CC (zero_extend:SI
4688 (subreg:HI
4689 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4690 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4691 (const_int 0)))
4692 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4693 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4694 ""
4695 "@
4696 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4697 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4698 #
4699 #"
4700 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4701 (set_attr "length" "4,4,8,8")])
4703 (define_split
4704 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4705 (compare:CC (zero_extend:SI
4706 (subreg:HI
4707 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4708 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4709 (const_int 0)))
4710 (set (match_operand:SI 0 "gpc_reg_operand" "")
4711 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4712 "reload_completed"
4713 [(set (match_dup 0)
4714 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4715 (set (match_dup 3)
4716 (compare:CC (match_dup 0)
4717 (const_int 0)))]
4718 "")
4720 ;; Note that we use "sle." instead of "sl." so that we can set
4721 ;; SHIFT_COUNT_TRUNCATED.
4723 (define_expand "ashlsi3"
4724 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4725 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4726 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4727 ""
4728 "
4729 {
4730 if (TARGET_POWER)
4731 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4732 else
4733 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4734 DONE;
4735 }")
4737 (define_insn "ashlsi3_power"
4738 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4739 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4740 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4741 (clobber (match_scratch:SI 3 "=q,X"))]
4742 "TARGET_POWER"
4743 "@
4744 sle %0,%1,%2
4745 {sli|slwi} %0,%1,%h2")
4747 (define_insn "ashlsi3_no_power"
4748 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4749 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4750 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4751 "! TARGET_POWER"
4752 "@
4753 {sl|slw} %0,%1,%2
4754 {sli|slwi} %0,%1,%h2"
4755 [(set_attr "type" "var_shift_rotate,shift")])
4757 (define_insn "*ashlsi3_64"
4758 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4759 (zero_extend:DI
4760 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4761 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4762 "TARGET_POWERPC64"
4763 "@
4764 {sl|slw} %0,%1,%2
4765 {sli|slwi} %0,%1,%h2"
4766 [(set_attr "type" "var_shift_rotate,shift")])
4768 (define_insn ""
4769 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4770 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4771 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4772 (const_int 0)))
4773 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4774 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4775 "TARGET_POWER"
4776 "@
4777 sle. %3,%1,%2
4778 {sli.|slwi.} %3,%1,%h2
4779 #
4780 #"
4781 [(set_attr "type" "delayed_compare")
4782 (set_attr "length" "4,4,8,8")])
4784 (define_split
4785 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4786 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4787 (match_operand:SI 2 "reg_or_cint_operand" ""))
4788 (const_int 0)))
4789 (clobber (match_scratch:SI 3 ""))
4790 (clobber (match_scratch:SI 4 ""))]
4791 "TARGET_POWER && reload_completed"
4792 [(parallel [(set (match_dup 3)
4793 (ashift:SI (match_dup 1) (match_dup 2)))
4794 (clobber (match_dup 4))])
4795 (set (match_dup 0)
4796 (compare:CC (match_dup 3)
4797 (const_int 0)))]
4798 "")
4800 (define_insn ""
4801 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4802 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4803 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4804 (const_int 0)))
4805 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4806 "! TARGET_POWER && TARGET_32BIT"
4807 "@
4808 {sl.|slw.} %3,%1,%2
4809 {sli.|slwi.} %3,%1,%h2
4810 #
4811 #"
4812 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4813 (set_attr "length" "4,4,8,8")])
4815 (define_split
4816 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4817 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4818 (match_operand:SI 2 "reg_or_cint_operand" ""))
4819 (const_int 0)))
4820 (clobber (match_scratch:SI 3 ""))]
4821 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4822 [(set (match_dup 3)
4823 (ashift:SI (match_dup 1) (match_dup 2)))
4824 (set (match_dup 0)
4825 (compare:CC (match_dup 3)
4826 (const_int 0)))]
4827 "")
4829 (define_insn ""
4830 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4831 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4832 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4833 (const_int 0)))
4834 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4835 (ashift:SI (match_dup 1) (match_dup 2)))
4836 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4837 "TARGET_POWER"
4838 "@
4839 sle. %0,%1,%2
4840 {sli.|slwi.} %0,%1,%h2
4841 #
4842 #"
4843 [(set_attr "type" "delayed_compare")
4844 (set_attr "length" "4,4,8,8")])
4846 (define_split
4847 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4848 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4849 (match_operand:SI 2 "reg_or_cint_operand" ""))
4850 (const_int 0)))
4851 (set (match_operand:SI 0 "gpc_reg_operand" "")
4852 (ashift:SI (match_dup 1) (match_dup 2)))
4853 (clobber (match_scratch:SI 4 ""))]
4854 "TARGET_POWER && reload_completed"
4855 [(parallel [(set (match_dup 0)
4856 (ashift:SI (match_dup 1) (match_dup 2)))
4857 (clobber (match_dup 4))])
4858 (set (match_dup 3)
4859 (compare:CC (match_dup 0)
4860 (const_int 0)))]
4861 "")
4863 (define_insn ""
4864 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4865 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4866 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4867 (const_int 0)))
4868 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4869 (ashift:SI (match_dup 1) (match_dup 2)))]
4870 "! TARGET_POWER && TARGET_32BIT"
4871 "@
4872 {sl.|slw.} %0,%1,%2
4873 {sli.|slwi.} %0,%1,%h2
4874 #
4875 #"
4876 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4877 (set_attr "length" "4,4,8,8")])
4879 (define_split
4880 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4881 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4882 (match_operand:SI 2 "reg_or_cint_operand" ""))
4883 (const_int 0)))
4884 (set (match_operand:SI 0 "gpc_reg_operand" "")
4885 (ashift:SI (match_dup 1) (match_dup 2)))]
4886 "! TARGET_POWER && TARGET_32BIT && reload_completed"
4887 [(set (match_dup 0)
4888 (ashift:SI (match_dup 1) (match_dup 2)))
4889 (set (match_dup 3)
4890 (compare:CC (match_dup 0)
4891 (const_int 0)))]
4892 "")
4894 (define_insn "rlwinm"
4895 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4896 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4897 (match_operand:SI 2 "const_int_operand" "i"))
4898 (match_operand:SI 3 "mask_operand" "n")))]
4899 "includes_lshift_p (operands[2], operands[3])"
4900 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4902 (define_insn ""
4903 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4904 (compare:CC
4905 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4906 (match_operand:SI 2 "const_int_operand" "i,i"))
4907 (match_operand:SI 3 "mask_operand" "n,n"))
4908 (const_int 0)))
4909 (clobber (match_scratch:SI 4 "=r,r"))]
4910 "includes_lshift_p (operands[2], operands[3])"
4911 "@
4912 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4913 #"
4914 [(set_attr "type" "delayed_compare")
4915 (set_attr "length" "4,8")])
4917 (define_split
4918 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4919 (compare:CC
4920 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4921 (match_operand:SI 2 "const_int_operand" ""))
4922 (match_operand:SI 3 "mask_operand" ""))
4923 (const_int 0)))
4924 (clobber (match_scratch:SI 4 ""))]
4925 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4926 [(set (match_dup 4)
4927 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4928 (match_dup 3)))
4929 (set (match_dup 0)
4930 (compare:CC (match_dup 4)
4931 (const_int 0)))]
4932 "")
4934 (define_insn ""
4935 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4936 (compare:CC
4937 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4938 (match_operand:SI 2 "const_int_operand" "i,i"))
4939 (match_operand:SI 3 "mask_operand" "n,n"))
4940 (const_int 0)))
4941 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4942 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4943 "includes_lshift_p (operands[2], operands[3])"
4944 "@
4945 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4946 #"
4947 [(set_attr "type" "delayed_compare")
4948 (set_attr "length" "4,8")])
4950 (define_split
4951 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4952 (compare:CC
4953 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4954 (match_operand:SI 2 "const_int_operand" ""))
4955 (match_operand:SI 3 "mask_operand" ""))
4956 (const_int 0)))
4957 (set (match_operand:SI 0 "gpc_reg_operand" "")
4958 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4959 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4960 [(set (match_dup 0)
4961 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4962 (set (match_dup 4)
4963 (compare:CC (match_dup 0)
4964 (const_int 0)))]
4965 "")
4967 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4968 ;; "sli x,x,0".
4969 (define_expand "lshrsi3"
4970 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4971 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4972 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4973 ""
4974 "
4975 {
4976 if (TARGET_POWER)
4977 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4978 else
4979 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4980 DONE;
4981 }")
4983 (define_insn "lshrsi3_power"
4984 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4985 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4986 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4987 (clobber (match_scratch:SI 3 "=q,X,X"))]
4988 "TARGET_POWER"
4989 "@
4990 sre %0,%1,%2
4991 mr %0,%1
4992 {s%A2i|s%A2wi} %0,%1,%h2")
4994 (define_insn "lshrsi3_no_power"
4995 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4996 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4997 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4998 "! TARGET_POWER"
4999 "@
5000 mr %0,%1
5001 {sr|srw} %0,%1,%2
5002 {sri|srwi} %0,%1,%h2"
5003 [(set_attr "type" "integer,var_shift_rotate,shift")])
5005 (define_insn "*lshrsi3_64"
5006 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5007 (zero_extend:DI
5008 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5009 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5010 "TARGET_POWERPC64"
5011 "@
5012 {sr|srw} %0,%1,%2
5013 {sri|srwi} %0,%1,%h2"
5014 [(set_attr "type" "var_shift_rotate,shift")])
5016 (define_insn ""
5017 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5018 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5019 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
5020 (const_int 0)))
5021 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
5022 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
5023 "TARGET_POWER"
5024 "@
5025 sre. %3,%1,%2
5026 mr. %1,%1
5027 {s%A2i.|s%A2wi.} %3,%1,%h2
5028 #
5029 #
5030 #"
5031 [(set_attr "type" "delayed_compare")
5032 (set_attr "length" "4,4,4,8,8,8")])
5034 (define_split
5035 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5036 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5037 (match_operand:SI 2 "reg_or_cint_operand" ""))
5038 (const_int 0)))
5039 (clobber (match_scratch:SI 3 ""))
5040 (clobber (match_scratch:SI 4 ""))]
5041 "TARGET_POWER && reload_completed"
5042 [(parallel [(set (match_dup 3)
5043 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5044 (clobber (match_dup 4))])
5045 (set (match_dup 0)
5046 (compare:CC (match_dup 3)
5047 (const_int 0)))]
5048 "")
5050 (define_insn ""
5051 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5052 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5053 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5054 (const_int 0)))
5055 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
5056 "! TARGET_POWER && TARGET_32BIT"
5057 "@
5058 mr. %1,%1
5059 {sr.|srw.} %3,%1,%2
5060 {sri.|srwi.} %3,%1,%h2
5061 #
5062 #
5063 #"
5064 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5065 (set_attr "length" "4,4,4,8,8,8")])
5067 (define_split
5068 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5069 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5070 (match_operand:SI 2 "reg_or_cint_operand" ""))
5071 (const_int 0)))
5072 (clobber (match_scratch:SI 3 ""))]
5073 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5074 [(set (match_dup 3)
5075 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5076 (set (match_dup 0)
5077 (compare:CC (match_dup 3)
5078 (const_int 0)))]
5079 "")
5081 (define_insn ""
5082 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5083 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5084 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
5085 (const_int 0)))
5086 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5087 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5088 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
5089 "TARGET_POWER"
5090 "@
5091 sre. %0,%1,%2
5092 mr. %0,%1
5093 {s%A2i.|s%A2wi.} %0,%1,%h2
5094 #
5095 #
5096 #"
5097 [(set_attr "type" "delayed_compare")
5098 (set_attr "length" "4,4,4,8,8,8")])
5100 (define_split
5101 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5102 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5103 (match_operand:SI 2 "reg_or_cint_operand" ""))
5104 (const_int 0)))
5105 (set (match_operand:SI 0 "gpc_reg_operand" "")
5106 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5107 (clobber (match_scratch:SI 4 ""))]
5108 "TARGET_POWER && reload_completed"
5109 [(parallel [(set (match_dup 0)
5110 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5111 (clobber (match_dup 4))])
5112 (set (match_dup 3)
5113 (compare:CC (match_dup 0)
5114 (const_int 0)))]
5115 "")
5117 (define_insn ""
5118 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
5119 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
5120 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
5121 (const_int 0)))
5122 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
5123 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5124 "! TARGET_POWER && TARGET_32BIT"
5125 "@
5126 mr. %0,%1
5127 {sr.|srw.} %0,%1,%2
5128 {sri.|srwi.} %0,%1,%h2
5129 #
5130 #
5131 #"
5132 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5133 (set_attr "length" "4,4,4,8,8,8")])
5135 (define_split
5136 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5137 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5138 (match_operand:SI 2 "reg_or_cint_operand" ""))
5139 (const_int 0)))
5140 (set (match_operand:SI 0 "gpc_reg_operand" "")
5141 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
5142 "! TARGET_POWER && TARGET_32BIT && reload_completed"
5143 [(set (match_dup 0)
5144 (lshiftrt:SI (match_dup 1) (match_dup 2)))
5145 (set (match_dup 3)
5146 (compare:CC (match_dup 0)
5147 (const_int 0)))]
5148 "")
5150 (define_insn ""
5151 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5152 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5153 (match_operand:SI 2 "const_int_operand" "i"))
5154 (match_operand:SI 3 "mask_operand" "n")))]
5155 "includes_rshift_p (operands[2], operands[3])"
5156 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
5158 (define_insn ""
5159 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5160 (compare:CC
5161 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5162 (match_operand:SI 2 "const_int_operand" "i,i"))
5163 (match_operand:SI 3 "mask_operand" "n,n"))
5164 (const_int 0)))
5165 (clobber (match_scratch:SI 4 "=r,r"))]
5166 "includes_rshift_p (operands[2], operands[3])"
5167 "@
5168 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
5169 #"
5170 [(set_attr "type" "delayed_compare")
5171 (set_attr "length" "4,8")])
5173 (define_split
5174 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5175 (compare:CC
5176 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5177 (match_operand:SI 2 "const_int_operand" ""))
5178 (match_operand:SI 3 "mask_operand" ""))
5179 (const_int 0)))
5180 (clobber (match_scratch:SI 4 ""))]
5181 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5182 [(set (match_dup 4)
5183 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
5184 (match_dup 3)))
5185 (set (match_dup 0)
5186 (compare:CC (match_dup 4)
5187 (const_int 0)))]
5188 "")
5190 (define_insn ""
5191 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
5192 (compare:CC
5193 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5194 (match_operand:SI 2 "const_int_operand" "i,i"))
5195 (match_operand:SI 3 "mask_operand" "n,n"))
5196 (const_int 0)))
5197 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5198 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5199 "includes_rshift_p (operands[2], operands[3])"
5200 "@
5201 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
5202 #"
5203 [(set_attr "type" "delayed_compare")
5204 (set_attr "length" "4,8")])
5206 (define_split
5207 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
5208 (compare:CC
5209 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5210 (match_operand:SI 2 "const_int_operand" ""))
5211 (match_operand:SI 3 "mask_operand" ""))
5212 (const_int 0)))
5213 (set (match_operand:SI 0 "gpc_reg_operand" "")
5214 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
5215 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
5216 [(set (match_dup 0)
5217 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
5218 (set (match_dup 4)
5219 (compare:CC (match_dup 0)
5220 (const_int 0)))]
5221 "")
5223 (define_insn ""
5224 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5225 (zero_extend:SI
5226 (subreg:QI
5227 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5228 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5229 "includes_rshift_p (operands[2], GEN_INT (255))"
5230 "{rlinm|rlwinm} %0,%1,%s2,0xff")
5232 (define_insn ""
5233 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5234 (compare:CC
5235 (zero_extend:SI
5236 (subreg:QI
5237 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5238 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5239 (const_int 0)))
5240 (clobber (match_scratch:SI 3 "=r,r"))]
5241 "includes_rshift_p (operands[2], GEN_INT (255))"
5242 "@
5243 {rlinm.|rlwinm.} %3,%1,%s2,0xff
5244 #"
5245 [(set_attr "type" "delayed_compare")
5246 (set_attr "length" "4,8")])
5248 (define_split
5249 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5250 (compare:CC
5251 (zero_extend:SI
5252 (subreg:QI
5253 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5254 (match_operand:SI 2 "const_int_operand" "")) 0))
5255 (const_int 0)))
5256 (clobber (match_scratch:SI 3 ""))]
5257 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5258 [(set (match_dup 3)
5259 (zero_extend:SI (subreg:QI
5260 (lshiftrt:SI (match_dup 1)
5261 (match_dup 2)) 0)))
5262 (set (match_dup 0)
5263 (compare:CC (match_dup 3)
5264 (const_int 0)))]
5265 "")
5267 (define_insn ""
5268 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5269 (compare:CC
5270 (zero_extend:SI
5271 (subreg:QI
5272 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5273 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5274 (const_int 0)))
5275 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5276 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5277 "includes_rshift_p (operands[2], GEN_INT (255))"
5278 "@
5279 {rlinm.|rlwinm.} %0,%1,%s2,0xff
5280 #"
5281 [(set_attr "type" "delayed_compare")
5282 (set_attr "length" "4,8")])
5284 (define_split
5285 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5286 (compare:CC
5287 (zero_extend:SI
5288 (subreg:QI
5289 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5290 (match_operand:SI 2 "const_int_operand" "")) 0))
5291 (const_int 0)))
5292 (set (match_operand:SI 0 "gpc_reg_operand" "")
5293 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5294 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
5295 [(set (match_dup 0)
5296 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5297 (set (match_dup 3)
5298 (compare:CC (match_dup 0)
5299 (const_int 0)))]
5300 "")
5302 (define_insn ""
5303 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5304 (zero_extend:SI
5305 (subreg:HI
5306 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
5307 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
5308 "includes_rshift_p (operands[2], GEN_INT (65535))"
5309 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
5311 (define_insn ""
5312 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5313 (compare:CC
5314 (zero_extend:SI
5315 (subreg:HI
5316 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5317 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5318 (const_int 0)))
5319 (clobber (match_scratch:SI 3 "=r,r"))]
5320 "includes_rshift_p (operands[2], GEN_INT (65535))"
5321 "@
5322 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
5323 #"
5324 [(set_attr "type" "delayed_compare")
5325 (set_attr "length" "4,8")])
5327 (define_split
5328 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5329 (compare:CC
5330 (zero_extend:SI
5331 (subreg:HI
5332 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5333 (match_operand:SI 2 "const_int_operand" "")) 0))
5334 (const_int 0)))
5335 (clobber (match_scratch:SI 3 ""))]
5336 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5337 [(set (match_dup 3)
5338 (zero_extend:SI (subreg:HI
5339 (lshiftrt:SI (match_dup 1)
5340 (match_dup 2)) 0)))
5341 (set (match_dup 0)
5342 (compare:CC (match_dup 3)
5343 (const_int 0)))]
5344 "")
5346 (define_insn ""
5347 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5348 (compare:CC
5349 (zero_extend:SI
5350 (subreg:HI
5351 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5352 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
5353 (const_int 0)))
5354 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5355 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5356 "includes_rshift_p (operands[2], GEN_INT (65535))"
5357 "@
5358 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
5359 #"
5360 [(set_attr "type" "delayed_compare")
5361 (set_attr "length" "4,8")])
5363 (define_split
5364 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5365 (compare:CC
5366 (zero_extend:SI
5367 (subreg:HI
5368 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5369 (match_operand:SI 2 "const_int_operand" "")) 0))
5370 (const_int 0)))
5371 (set (match_operand:SI 0 "gpc_reg_operand" "")
5372 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
5373 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
5374 [(set (match_dup 0)
5375 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
5376 (set (match_dup 3)
5377 (compare:CC (match_dup 0)
5378 (const_int 0)))]
5379 "")
5381 (define_insn ""
5382 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5383 (const_int 1)
5384 (match_operand:SI 1 "gpc_reg_operand" "r"))
5385 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5386 (const_int 31)))]
5387 "TARGET_POWER"
5388 "rrib %0,%1,%2")
5390 (define_insn ""
5391 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5392 (const_int 1)
5393 (match_operand:SI 1 "gpc_reg_operand" "r"))
5394 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5395 (const_int 31)))]
5396 "TARGET_POWER"
5397 "rrib %0,%1,%2")
5399 (define_insn ""
5400 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
5401 (const_int 1)
5402 (match_operand:SI 1 "gpc_reg_operand" "r"))
5403 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
5404 (const_int 1)
5405 (const_int 0)))]
5406 "TARGET_POWER"
5407 "rrib %0,%1,%2")
5409 (define_expand "ashrsi3"
5410 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5411 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5412 (match_operand:SI 2 "reg_or_cint_operand" "")))]
5413 ""
5414 "
5415 {
5416 if (TARGET_POWER)
5417 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
5418 else
5419 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
5420 DONE;
5421 }")
5423 (define_insn "ashrsi3_power"
5424 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5425 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5426 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
5427 (clobber (match_scratch:SI 3 "=q,X"))]
5428 "TARGET_POWER"
5429 "@
5430 srea %0,%1,%2
5431 {srai|srawi} %0,%1,%h2"
5432 [(set_attr "type" "shift")])
5434 (define_insn "ashrsi3_no_power"
5435 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5436 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5437 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
5438 "! TARGET_POWER"
5439 "@
5440 {sra|sraw} %0,%1,%2
5441 {srai|srawi} %0,%1,%h2"
5442 [(set_attr "type" "var_shift_rotate,shift")])
5444 (define_insn "*ashrsi3_64"
5445 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
5446 (sign_extend:DI
5447 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5448 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
5449 "TARGET_POWERPC64"
5450 "@
5451 {sra|sraw} %0,%1,%2
5452 {srai|srawi} %0,%1,%h2"
5453 [(set_attr "type" "var_shift_rotate,shift")])
5455 (define_insn ""
5456 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5457 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5458 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5459 (const_int 0)))
5460 (clobber (match_scratch:SI 3 "=r,r,r,r"))
5461 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5462 "TARGET_POWER"
5463 "@
5464 srea. %3,%1,%2
5465 {srai.|srawi.} %3,%1,%h2
5466 #
5467 #"
5468 [(set_attr "type" "delayed_compare")
5469 (set_attr "length" "4,4,8,8")])
5471 (define_split
5472 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5473 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5474 (match_operand:SI 2 "reg_or_cint_operand" ""))
5475 (const_int 0)))
5476 (clobber (match_scratch:SI 3 ""))
5477 (clobber (match_scratch:SI 4 ""))]
5478 "TARGET_POWER && reload_completed"
5479 [(parallel [(set (match_dup 3)
5480 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5481 (clobber (match_dup 4))])
5482 (set (match_dup 0)
5483 (compare:CC (match_dup 3)
5484 (const_int 0)))]
5485 "")
5487 (define_insn ""
5488 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
5489 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5490 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5491 (const_int 0)))
5492 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
5493 "! TARGET_POWER"
5494 "@
5495 {sra.|sraw.} %3,%1,%2
5496 {srai.|srawi.} %3,%1,%h2
5497 #
5498 #"
5499 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5500 (set_attr "length" "4,4,8,8")])
5502 (define_split
5503 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
5504 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5505 (match_operand:SI 2 "reg_or_cint_operand" ""))
5506 (const_int 0)))
5507 (clobber (match_scratch:SI 3 ""))]
5508 "! TARGET_POWER && reload_completed"
5509 [(set (match_dup 3)
5510 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5511 (set (match_dup 0)
5512 (compare:CC (match_dup 3)
5513 (const_int 0)))]
5514 "")
5516 (define_insn ""
5517 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5518 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5519 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5520 (const_int 0)))
5521 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5522 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5523 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5524 "TARGET_POWER"
5525 "@
5526 srea. %0,%1,%2
5527 {srai.|srawi.} %0,%1,%h2
5528 #
5529 #"
5530 [(set_attr "type" "delayed_compare")
5531 (set_attr "length" "4,4,8,8")])
5533 (define_split
5534 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5535 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5536 (match_operand:SI 2 "reg_or_cint_operand" ""))
5537 (const_int 0)))
5538 (set (match_operand:SI 0 "gpc_reg_operand" "")
5539 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5540 (clobber (match_scratch:SI 4 ""))]
5541 "TARGET_POWER && reload_completed"
5542 [(parallel [(set (match_dup 0)
5543 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5544 (clobber (match_dup 4))])
5545 (set (match_dup 3)
5546 (compare:CC (match_dup 0)
5547 (const_int 0)))]
5548 "")
5550 (define_insn ""
5551 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5552 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5553 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5554 (const_int 0)))
5555 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5556 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5557 "! TARGET_POWER"
5558 "@
5559 {sra.|sraw.} %0,%1,%2
5560 {srai.|srawi.} %0,%1,%h2
5561 #
5562 #"
5563 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
5564 (set_attr "length" "4,4,8,8")])
5565 \f
5566 (define_split
5567 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
5568 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5569 (match_operand:SI 2 "reg_or_cint_operand" ""))
5570 (const_int 0)))
5571 (set (match_operand:SI 0 "gpc_reg_operand" "")
5572 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5573 "! TARGET_POWER && reload_completed"
5574 [(set (match_dup 0)
5575 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5576 (set (match_dup 3)
5577 (compare:CC (match_dup 0)
5578 (const_int 0)))]
5579 "")
5581 ;; Floating-point insns, excluding normal data motion.
5582 ;;
5583 ;; PowerPC has a full set of single-precision floating point instructions.
5584 ;;
5585 ;; For the POWER architecture, we pretend that we have both SFmode and
5586 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5587 ;; The only conversions we will do will be when storing to memory. In that
5588 ;; case, we will use the "frsp" instruction before storing.
5589 ;;
5590 ;; Note that when we store into a single-precision memory location, we need to
5591 ;; use the frsp insn first. If the register being stored isn't dead, we
5592 ;; need a scratch register for the frsp. But this is difficult when the store
5593 ;; is done by reload. It is not incorrect to do the frsp on the register in
5594 ;; this case, we just lose precision that we would have otherwise gotten but
5595 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5597 (define_expand "extendsfdf2"
5598 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5599 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
5600 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5601 "")
5603 (define_insn_and_split "*extendsfdf2_fpr"
5604 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
5605 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
5606 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5607 "@
5608 #
5609 fmr %0,%1
5610 lfs%U1%X1 %0,%1"
5611 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
5612 [(const_int 0)]
5613 {
5614 emit_note (NOTE_INSN_DELETED);
5615 DONE;
5616 }
5617 [(set_attr "type" "fp,fp,fpload")])
5619 (define_expand "truncdfsf2"
5620 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5621 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
5622 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5623 "")
5625 (define_insn "*truncdfsf2_fpr"
5626 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5627 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5628 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5629 "frsp %0,%1"
5630 [(set_attr "type" "fp")])
5632 (define_insn "aux_truncdfsf2"
5633 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5634 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
5635 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5636 "frsp %0,%1"
5637 [(set_attr "type" "fp")])
5639 (define_expand "negsf2"
5640 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5641 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5642 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5643 "")
5645 (define_insn "*negsf2"
5646 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5647 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5648 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5649 "fneg %0,%1"
5650 [(set_attr "type" "fp")])
5652 (define_expand "abssf2"
5653 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5654 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5655 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5656 "")
5658 (define_insn "*abssf2"
5659 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5660 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5661 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5662 "fabs %0,%1"
5663 [(set_attr "type" "fp")])
5665 (define_insn ""
5666 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5667 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5668 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5669 "fnabs %0,%1"
5670 [(set_attr "type" "fp")])
5672 (define_expand "addsf3"
5673 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5674 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5675 (match_operand:SF 2 "gpc_reg_operand" "")))]
5676 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5677 "")
5679 (define_insn ""
5680 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5681 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5682 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5683 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5684 "fadds %0,%1,%2"
5685 [(set_attr "type" "fp")
5686 (set_attr "fp_type" "fp_addsub_s")])
5688 (define_insn ""
5689 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5690 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5691 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5692 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5693 "{fa|fadd} %0,%1,%2"
5694 [(set_attr "type" "fp")])
5696 (define_expand "subsf3"
5697 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5698 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5699 (match_operand:SF 2 "gpc_reg_operand" "")))]
5700 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5701 "")
5703 (define_insn ""
5704 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5705 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5706 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5707 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5708 "fsubs %0,%1,%2"
5709 [(set_attr "type" "fp")
5710 (set_attr "fp_type" "fp_addsub_s")])
5712 (define_insn ""
5713 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5714 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5715 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5716 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5717 "{fs|fsub} %0,%1,%2"
5718 [(set_attr "type" "fp")])
5720 (define_expand "mulsf3"
5721 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5722 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5723 (match_operand:SF 2 "gpc_reg_operand" "")))]
5724 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
5725 "")
5727 (define_insn ""
5728 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5729 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5730 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5731 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5732 "fmuls %0,%1,%2"
5733 [(set_attr "type" "fp")
5734 (set_attr "fp_type" "fp_mul_s")])
5736 (define_insn ""
5737 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5738 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5739 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5740 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5741 "{fm|fmul} %0,%1,%2"
5742 [(set_attr "type" "dmul")])
5744 (define_expand "divsf3"
5745 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5746 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5747 (match_operand:SF 2 "gpc_reg_operand" "")))]
5748 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5749 "")
5751 (define_insn ""
5752 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5753 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5754 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5755 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5756 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5757 "fdivs %0,%1,%2"
5758 [(set_attr "type" "sdiv")])
5760 (define_insn ""
5761 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5762 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5763 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5764 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5765 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5766 "{fd|fdiv} %0,%1,%2"
5767 [(set_attr "type" "ddiv")])
5769 (define_expand "recipsf3"
5770 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5771 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")
5772 (match_operand:SF 2 "gpc_reg_operand" "f")]
5773 UNSPEC_FRES))]
5774 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5775 && flag_finite_math_only && !flag_trapping_math"
5776 {
5777 rs6000_emit_swdivsf (operands[0], operands[1], operands[2]);
5778 DONE;
5779 })
5781 (define_insn "fres"
5782 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5783 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5784 "TARGET_PPC_GFXOPT && flag_finite_math_only"
5785 "fres %0,%1"
5786 [(set_attr "type" "fp")])
5788 (define_insn "*fmaddsf4_powerpc"
5789 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5790 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5791 (match_operand:SF 2 "gpc_reg_operand" "f"))
5792 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5793 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5794 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5795 "fmadds %0,%1,%2,%3"
5796 [(set_attr "type" "fp")
5797 (set_attr "fp_type" "fp_maddsub_s")])
5799 (define_insn "*fmaddsf4_power"
5800 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5801 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5802 (match_operand:SF 2 "gpc_reg_operand" "f"))
5803 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5804 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5805 "{fma|fmadd} %0,%1,%2,%3"
5806 [(set_attr "type" "dmul")])
5808 (define_insn "*fmsubsf4_powerpc"
5809 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5810 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5811 (match_operand:SF 2 "gpc_reg_operand" "f"))
5812 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5813 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5814 && TARGET_SINGLE_FLOAT && TARGET_FUSED_MADD"
5815 "fmsubs %0,%1,%2,%3"
5816 [(set_attr "type" "fp")
5817 (set_attr "fp_type" "fp_maddsub_s")])
5819 (define_insn "*fmsubsf4_power"
5820 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5821 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5822 (match_operand:SF 2 "gpc_reg_operand" "f"))
5823 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5824 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5825 "{fms|fmsub} %0,%1,%2,%3"
5826 [(set_attr "type" "dmul")])
5828 (define_insn "*fnmaddsf4_powerpc_1"
5829 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5830 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5831 (match_operand:SF 2 "gpc_reg_operand" "f"))
5832 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5833 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5834 && TARGET_SINGLE_FLOAT"
5835 "fnmadds %0,%1,%2,%3"
5836 [(set_attr "type" "fp")
5837 (set_attr "fp_type" "fp_maddsub_s")])
5839 (define_insn "*fnmaddsf4_powerpc_2"
5840 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5841 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5842 (match_operand:SF 2 "gpc_reg_operand" "f"))
5843 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5844 "TARGET_POWERPC && TARGET_SINGLE_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5845 && ! HONOR_SIGNED_ZEROS (SFmode)"
5846 "fnmadds %0,%1,%2,%3"
5847 [(set_attr "type" "fp")
5848 (set_attr "fp_type" "fp_maddsub_s")])
5850 (define_insn "*fnmaddsf4_power_1"
5851 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5852 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5853 (match_operand:SF 2 "gpc_reg_operand" "f"))
5854 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5855 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5856 "{fnma|fnmadd} %0,%1,%2,%3"
5857 [(set_attr "type" "dmul")])
5859 (define_insn "*fnmaddsf4_power_2"
5860 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5861 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5862 (match_operand:SF 2 "gpc_reg_operand" "f"))
5863 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5864 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5865 && ! HONOR_SIGNED_ZEROS (SFmode)"
5866 "{fnma|fnmadd} %0,%1,%2,%3"
5867 [(set_attr "type" "dmul")])
5869 (define_insn "*fnmsubsf4_powerpc_1"
5870 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5871 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5872 (match_operand:SF 2 "gpc_reg_operand" "f"))
5873 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5874 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5875 && TARGET_SINGLE_FLOAT"
5876 "fnmsubs %0,%1,%2,%3"
5877 [(set_attr "type" "fp")
5878 (set_attr "fp_type" "fp_maddsub_s")])
5880 (define_insn "*fnmsubsf4_powerpc_2"
5881 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5882 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5883 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5884 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5885 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5886 && TARGET_SINGLE_FLOAT && ! HONOR_SIGNED_ZEROS (SFmode)"
5887 "fnmsubs %0,%1,%2,%3"
5888 [(set_attr "type" "fp")
5889 (set_attr "fp_type" "fp_maddsub_s")])
5891 (define_insn "*fnmsubsf4_power_1"
5892 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5893 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5894 (match_operand:SF 2 "gpc_reg_operand" "f"))
5895 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5896 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5897 "{fnms|fnmsub} %0,%1,%2,%3"
5898 [(set_attr "type" "dmul")])
5900 (define_insn "*fnmsubsf4_power_2"
5901 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5902 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5903 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5904 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5905 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5906 && ! HONOR_SIGNED_ZEROS (SFmode)"
5907 "{fnms|fnmsub} %0,%1,%2,%3"
5908 [(set_attr "type" "dmul")])
5910 (define_expand "sqrtsf2"
5911 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5912 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5913 "(TARGET_PPC_GPOPT || TARGET_POWER2 || TARGET_XILINX_FPU)
5914 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5915 && !TARGET_SIMPLE_FPU"
5916 "")
5918 (define_insn ""
5919 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5920 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5921 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
5922 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5923 "fsqrts %0,%1"
5924 [(set_attr "type" "ssqrt")])
5926 (define_insn ""
5927 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5928 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5929 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS
5930 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5931 "fsqrt %0,%1"
5932 [(set_attr "type" "dsqrt")])
5934 (define_expand "rsqrtsf2"
5935 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5936 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5937 UNSPEC_RSQRT))]
5938 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT && !optimize_size
5939 && flag_finite_math_only && !flag_trapping_math"
5940 {
5941 rs6000_emit_swrsqrtsf (operands[0], operands[1]);
5942 DONE;
5943 })
5945 (define_insn "*rsqrt_internal1"
5946 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5947 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5948 UNSPEC_RSQRT))]
5949 "TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT"
5950 "frsqrte %0,%1"
5951 [(set_attr "type" "fp")])
5953 (define_expand "copysignsf3"
5954 [(set (match_dup 3)
5955 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))
5956 (set (match_dup 4)
5957 (neg:SF (abs:SF (match_dup 1))))
5958 (set (match_operand:SF 0 "gpc_reg_operand" "")
5959 (if_then_else:SF (ge (match_operand:SF 2 "gpc_reg_operand" "")
5960 (match_dup 5))
5961 (match_dup 3)
5962 (match_dup 4)))]
5963 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5964 && !HONOR_NANS (SFmode) && !HONOR_SIGNED_ZEROS (SFmode)"
5965 {
5966 operands[3] = gen_reg_rtx (SFmode);
5967 operands[4] = gen_reg_rtx (SFmode);
5968 operands[5] = CONST0_RTX (SFmode);
5969 })
5971 (define_expand "copysigndf3"
5972 [(set (match_dup 3)
5973 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))
5974 (set (match_dup 4)
5975 (neg:DF (abs:DF (match_dup 1))))
5976 (set (match_operand:DF 0 "gpc_reg_operand" "")
5977 (if_then_else:DF (ge (match_operand:DF 2 "gpc_reg_operand" "")
5978 (match_dup 5))
5979 (match_dup 3)
5980 (match_dup 4)))]
5981 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5982 && ((TARGET_PPC_GFXOPT
5983 && !HONOR_NANS (DFmode)
5984 && !HONOR_SIGNED_ZEROS (DFmode))
5985 || VECTOR_UNIT_VSX_P (DFmode))"
5986 {
5987 if (VECTOR_UNIT_VSX_P (DFmode))
5988 {
5989 emit_insn (gen_vsx_copysigndf3 (operands[0], operands[1],
5990 operands[2], CONST0_RTX (DFmode)));
5991 DONE;
5992 }
5993 operands[3] = gen_reg_rtx (DFmode);
5994 operands[4] = gen_reg_rtx (DFmode);
5995 operands[5] = CONST0_RTX (DFmode);
5996 })
5998 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5999 ;; fsel instruction and some auxiliary computations. Then we just have a
6000 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
6001 ;; combine.
6002 (define_expand "smaxsf3"
6003 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6004 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
6005 (match_operand:SF 2 "gpc_reg_operand" ""))
6006 (match_dup 1)
6007 (match_dup 2)))]
6008 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6009 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6010 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
6012 (define_expand "sminsf3"
6013 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6014 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
6015 (match_operand:SF 2 "gpc_reg_operand" ""))
6016 (match_dup 2)
6017 (match_dup 1)))]
6018 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6019 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6020 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
6022 (define_split
6023 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6024 (match_operator:SF 3 "min_max_operator"
6025 [(match_operand:SF 1 "gpc_reg_operand" "")
6026 (match_operand:SF 2 "gpc_reg_operand" "")]))]
6027 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
6028 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
6029 [(const_int 0)]
6030 "
6031 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6032 operands[1], operands[2]);
6033 DONE;
6034 }")
6036 (define_expand "mov<mode>cc"
6037 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
6038 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
6039 (match_operand:GPR 2 "gpc_reg_operand" "")
6040 (match_operand:GPR 3 "gpc_reg_operand" "")))]
6041 "TARGET_ISEL<sel>"
6042 "
6043 {
6044 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6045 DONE;
6046 else
6047 FAIL;
6048 }")
6050 ;; We use the BASE_REGS for the isel input operands because, if rA is
6051 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
6052 ;; because we may switch the operands and rB may end up being rA.
6053 ;;
6054 ;; We need 2 patterns: an unsigned and a signed pattern. We could
6055 ;; leave out the mode in operand 4 and use one pattern, but reload can
6056 ;; change the mode underneath our feet and then gets confused trying
6057 ;; to reload the value.
6058 (define_insn "isel_signed_<mode>"
6059 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
6060 (if_then_else:GPR
6061 (match_operator 1 "comparison_operator"
6062 [(match_operand:CC 4 "cc_reg_operand" "y")
6063 (const_int 0)])
6064 (match_operand:GPR 2 "gpc_reg_operand" "b")
6065 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
6066 "TARGET_ISEL<sel>"
6067 "*
6068 { return output_isel (operands); }"
6069 [(set_attr "type" "isel")
6070 (set_attr "length" "4")])
6072 (define_insn "isel_unsigned_<mode>"
6073 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
6074 (if_then_else:GPR
6075 (match_operator 1 "comparison_operator"
6076 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
6077 (const_int 0)])
6078 (match_operand:GPR 2 "gpc_reg_operand" "b")
6079 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
6080 "TARGET_ISEL<sel>"
6081 "*
6082 { return output_isel (operands); }"
6083 [(set_attr "type" "isel")
6084 (set_attr "length" "4")])
6086 (define_expand "movsfcc"
6087 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6088 (if_then_else:SF (match_operand 1 "comparison_operator" "")
6089 (match_operand:SF 2 "gpc_reg_operand" "")
6090 (match_operand:SF 3 "gpc_reg_operand" "")))]
6091 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6092 "
6093 {
6094 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6095 DONE;
6096 else
6097 FAIL;
6098 }")
6100 (define_insn "*fselsfsf4"
6101 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6102 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6103 (match_operand:SF 4 "zero_fp_constant" "F"))
6104 (match_operand:SF 2 "gpc_reg_operand" "f")
6105 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6106 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6107 "fsel %0,%1,%2,%3"
6108 [(set_attr "type" "fp")])
6110 (define_insn "*fseldfsf4"
6111 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6112 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6113 (match_operand:DF 4 "zero_fp_constant" "F"))
6114 (match_operand:SF 2 "gpc_reg_operand" "f")
6115 (match_operand:SF 3 "gpc_reg_operand" "f")))]
6116 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6117 "fsel %0,%1,%2,%3"
6118 [(set_attr "type" "fp")])
6120 (define_expand "negdf2"
6121 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6122 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6123 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6124 "")
6126 (define_insn "*negdf2_fpr"
6127 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6128 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6129 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6130 && !VECTOR_UNIT_VSX_P (DFmode)"
6131 "fneg %0,%1"
6132 [(set_attr "type" "fp")])
6134 (define_expand "absdf2"
6135 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6136 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6137 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6138 "")
6140 (define_insn "*absdf2_fpr"
6141 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6142 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6143 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6144 && !VECTOR_UNIT_VSX_P (DFmode)"
6145 "fabs %0,%1"
6146 [(set_attr "type" "fp")])
6148 (define_insn "*nabsdf2_fpr"
6149 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6150 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6151 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6152 && !VECTOR_UNIT_VSX_P (DFmode)"
6153 "fnabs %0,%1"
6154 [(set_attr "type" "fp")])
6156 (define_expand "adddf3"
6157 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6158 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6159 (match_operand:DF 2 "gpc_reg_operand" "")))]
6160 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6161 "")
6163 (define_insn "*adddf3_fpr"
6164 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6165 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6166 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6167 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6168 && !VECTOR_UNIT_VSX_P (DFmode)"
6169 "{fa|fadd} %0,%1,%2"
6170 [(set_attr "type" "fp")
6171 (set_attr "fp_type" "fp_addsub_d")])
6173 (define_expand "subdf3"
6174 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6175 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
6176 (match_operand:DF 2 "gpc_reg_operand" "")))]
6177 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6178 "")
6180 (define_insn "*subdf3_fpr"
6181 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6182 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6183 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6184 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6185 && !VECTOR_UNIT_VSX_P (DFmode)"
6186 "{fs|fsub} %0,%1,%2"
6187 [(set_attr "type" "fp")
6188 (set_attr "fp_type" "fp_addsub_d")])
6190 (define_expand "muldf3"
6191 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6192 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
6193 (match_operand:DF 2 "gpc_reg_operand" "")))]
6194 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6195 "")
6197 (define_insn "*muldf3_fpr"
6198 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6199 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6200 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6201 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6202 && !VECTOR_UNIT_VSX_P (DFmode)"
6203 "{fm|fmul} %0,%1,%2"
6204 [(set_attr "type" "dmul")
6205 (set_attr "fp_type" "fp_mul_d")])
6207 (define_expand "divdf3"
6208 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6209 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
6210 (match_operand:DF 2 "gpc_reg_operand" "")))]
6211 "TARGET_HARD_FLOAT
6212 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
6213 && !TARGET_SIMPLE_FPU"
6214 "")
6216 (define_insn "*divdf3_fpr"
6217 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6218 (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
6219 (match_operand:DF 2 "gpc_reg_operand" "d")))]
6220 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU
6221 && !VECTOR_UNIT_VSX_P (DFmode)"
6222 "{fd|fdiv} %0,%1,%2"
6223 [(set_attr "type" "ddiv")])
6225 (define_expand "recipdf3"
6226 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6227 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")
6228 (match_operand:DF 2 "gpc_reg_operand" "d")]
6229 UNSPEC_FRES))]
6230 "TARGET_RECIP && TARGET_HARD_FLOAT && TARGET_POPCNTB && !optimize_size
6231 && flag_finite_math_only && !flag_trapping_math"
6232 {
6233 rs6000_emit_swdivdf (operands[0], operands[1], operands[2]);
6234 DONE;
6235 })
6237 (define_expand "fred"
6238 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6239 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRES))]
6240 "(TARGET_POPCNTB || VECTOR_UNIT_VSX_P (DFmode)) && flag_finite_math_only"
6241 "")
6243 (define_insn "*fred_fpr"
6244 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6245 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
6246 "TARGET_POPCNTB && flag_finite_math_only && !VECTOR_UNIT_VSX_P (DFmode)"
6247 "fre %0,%1"
6248 [(set_attr "type" "fp")])
6250 (define_insn "*fmadddf4_fpr"
6251 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6252 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6253 (match_operand:DF 2 "gpc_reg_operand" "d"))
6254 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6255 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6256 && VECTOR_UNIT_NONE_P (DFmode)"
6257 "{fma|fmadd} %0,%1,%2,%3"
6258 [(set_attr "type" "dmul")
6259 (set_attr "fp_type" "fp_maddsub_d")])
6261 (define_insn "*fmsubdf4_fpr"
6262 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6263 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6264 (match_operand:DF 2 "gpc_reg_operand" "d"))
6265 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6266 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6267 && VECTOR_UNIT_NONE_P (DFmode)"
6268 "{fms|fmsub} %0,%1,%2,%3"
6269 [(set_attr "type" "dmul")
6270 (set_attr "fp_type" "fp_maddsub_d")])
6272 (define_insn "*fnmadddf4_fpr_1"
6273 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6274 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6275 (match_operand:DF 2 "gpc_reg_operand" "d"))
6276 (match_operand:DF 3 "gpc_reg_operand" "d"))))]
6277 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6278 && VECTOR_UNIT_NONE_P (DFmode)"
6279 "{fnma|fnmadd} %0,%1,%2,%3"
6280 [(set_attr "type" "dmul")
6281 (set_attr "fp_type" "fp_maddsub_d")])
6283 (define_insn "*fnmadddf4_fpr_2"
6284 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6285 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d"))
6286 (match_operand:DF 2 "gpc_reg_operand" "d"))
6287 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6288 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6289 && ! HONOR_SIGNED_ZEROS (DFmode) && VECTOR_UNIT_NONE_P (DFmode)"
6290 "{fnma|fnmadd} %0,%1,%2,%3"
6291 [(set_attr "type" "dmul")
6292 (set_attr "fp_type" "fp_maddsub_d")])
6294 (define_insn "*fnmsubdf4_fpr_1"
6295 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6296 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6297 (match_operand:DF 2 "gpc_reg_operand" "d"))
6298 (match_operand:DF 3 "gpc_reg_operand" "d"))))]
6299 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6300 && VECTOR_UNIT_NONE_P (DFmode)"
6301 "{fnms|fnmsub} %0,%1,%2,%3"
6302 [(set_attr "type" "dmul")
6303 (set_attr "fp_type" "fp_maddsub_d")])
6305 (define_insn "*fnmsubdf4_fpr_2"
6306 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6307 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "d")
6308 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
6309 (match_operand:DF 2 "gpc_reg_operand" "d"))))]
6310 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD && TARGET_DOUBLE_FLOAT
6311 && ! HONOR_SIGNED_ZEROS (DFmode) && VECTOR_UNIT_NONE_P (DFmode)"
6312 "{fnms|fnmsub} %0,%1,%2,%3"
6313 [(set_attr "type" "dmul")
6314 (set_attr "fp_type" "fp_maddsub_d")])
6316 (define_expand "sqrtdf2"
6317 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6318 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6319 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
6320 && TARGET_DOUBLE_FLOAT"
6321 "")
6323 (define_insn "*sqrtdf2_fpr"
6324 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6325 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
6326 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS
6327 && TARGET_DOUBLE_FLOAT
6328 && !VECTOR_UNIT_VSX_P (DFmode)"
6329 "fsqrt %0,%1"
6330 [(set_attr "type" "dsqrt")])
6332 ;; The conditional move instructions allow us to perform max and min
6333 ;; operations even when
6335 (define_expand "smaxdf3"
6336 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6337 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6338 (match_operand:DF 2 "gpc_reg_operand" ""))
6339 (match_dup 1)
6340 (match_dup 2)))]
6341 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6342 && !flag_trapping_math"
6343 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
6345 (define_expand "smindf3"
6346 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6347 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
6348 (match_operand:DF 2 "gpc_reg_operand" ""))
6349 (match_dup 2)
6350 (match_dup 1)))]
6351 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6352 && !flag_trapping_math"
6353 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
6355 (define_split
6356 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6357 (match_operator:DF 3 "min_max_operator"
6358 [(match_operand:DF 1 "gpc_reg_operand" "")
6359 (match_operand:DF 2 "gpc_reg_operand" "")]))]
6360 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6361 && !flag_trapping_math"
6362 [(const_int 0)]
6363 "
6364 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
6365 operands[1], operands[2]);
6366 DONE;
6367 }")
6369 (define_expand "movdfcc"
6370 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6371 (if_then_else:DF (match_operand 1 "comparison_operator" "")
6372 (match_operand:DF 2 "gpc_reg_operand" "")
6373 (match_operand:DF 3 "gpc_reg_operand" "")))]
6374 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6375 "
6376 {
6377 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
6378 DONE;
6379 else
6380 FAIL;
6381 }")
6383 (define_insn "*fseldfdf4"
6384 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6385 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
6386 (match_operand:DF 4 "zero_fp_constant" "F"))
6387 (match_operand:DF 2 "gpc_reg_operand" "d")
6388 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6389 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6390 "fsel %0,%1,%2,%3"
6391 [(set_attr "type" "fp")])
6393 (define_insn "*fselsfdf4"
6394 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6395 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
6396 (match_operand:SF 4 "zero_fp_constant" "F"))
6397 (match_operand:DF 2 "gpc_reg_operand" "d")
6398 (match_operand:DF 3 "gpc_reg_operand" "d")))]
6399 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
6400 "fsel %0,%1,%2,%3"
6401 [(set_attr "type" "fp")])
6402 \f
6403 ;; Conversions to and from floating-point.
6405 (define_expand "fixuns_truncsfsi2"
6406 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6407 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
6408 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
6409 "")
6411 (define_expand "fix_truncsfsi2"
6412 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6413 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
6414 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
6415 "")
6417 (define_expand "fixuns_truncdfsi2"
6418 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6419 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))]
6420 "TARGET_HARD_FLOAT && TARGET_E500_DOUBLE"
6421 "")
6423 (define_expand "fixuns_truncdfdi2"
6424 [(set (match_operand:DI 0 "register_operand" "")
6425 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
6426 "TARGET_HARD_FLOAT && TARGET_VSX"
6427 "")
6429 ; For each of these conversions, there is a define_expand, a define_insn
6430 ; with a '#' template, and a define_split (with C code). The idea is
6431 ; to allow constant folding with the template of the define_insn,
6432 ; then to have the insns split later (between sched1 and final).
6434 (define_expand "floatsidf2"
6435 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6436 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
6437 (use (match_dup 2))
6438 (use (match_dup 3))
6439 (clobber (match_dup 4))
6440 (clobber (match_dup 5))
6441 (clobber (match_dup 6))])]
6442 "TARGET_HARD_FLOAT
6443 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6444 "
6445 {
6446 if (TARGET_E500_DOUBLE)
6447 {
6448 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
6449 DONE;
6450 }
6451 if (TARGET_POWERPC64)
6452 {
6453 rtx x = convert_to_mode (DImode, operands[1], 0);
6454 emit_insn (gen_floatdidf2 (operands[0], x));
6455 DONE;
6456 }
6458 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6459 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
6460 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
6461 operands[5] = gen_reg_rtx (DFmode);
6462 operands[6] = gen_reg_rtx (SImode);
6463 }")
6465 (define_insn_and_split "*floatsidf2_internal"
6466 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6467 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6468 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6469 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6470 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6471 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
6472 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
6473 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6474 "#"
6475 ""
6476 [(pc)]
6477 "
6478 {
6479 rtx lowword, highword;
6480 gcc_assert (MEM_P (operands[4]));
6481 highword = adjust_address (operands[4], SImode, 0);
6482 lowword = adjust_address (operands[4], SImode, 4);
6483 if (! WORDS_BIG_ENDIAN)
6484 {
6485 rtx tmp;
6486 tmp = highword; highword = lowword; lowword = tmp;
6487 }
6489 emit_insn (gen_xorsi3 (operands[6], operands[1],
6490 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
6491 emit_move_insn (lowword, operands[6]);
6492 emit_move_insn (highword, operands[2]);
6493 emit_move_insn (operands[5], operands[4]);
6494 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6495 DONE;
6496 }"
6497 [(set_attr "length" "24")])
6499 (define_expand "floatunssisf2"
6500 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6501 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6502 "TARGET_HARD_FLOAT && !TARGET_FPRS && TARGET_SINGLE_FLOAT"
6503 "")
6505 (define_expand "floatunssidf2"
6506 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
6507 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
6508 (use (match_dup 2))
6509 (use (match_dup 3))
6510 (clobber (match_dup 4))
6511 (clobber (match_dup 5))])]
6512 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6513 "
6514 {
6515 if (TARGET_E500_DOUBLE)
6516 {
6517 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
6518 DONE;
6519 }
6520 if (TARGET_POWERPC64)
6521 {
6522 rtx x = convert_to_mode (DImode, operands[1], 1);
6523 emit_insn (gen_floatdidf2 (operands[0], x));
6524 DONE;
6525 }
6527 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
6528 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
6529 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
6530 operands[5] = gen_reg_rtx (DFmode);
6531 }")
6533 (define_insn_and_split "*floatunssidf2_internal"
6534 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
6535 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
6536 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
6537 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
6538 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
6539 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
6540 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6541 "#"
6542 ""
6543 [(pc)]
6544 "
6545 {
6546 rtx lowword, highword;
6547 gcc_assert (MEM_P (operands[4]));
6548 highword = adjust_address (operands[4], SImode, 0);
6549 lowword = adjust_address (operands[4], SImode, 4);
6550 if (! WORDS_BIG_ENDIAN)
6551 {
6552 rtx tmp;
6553 tmp = highword; highword = lowword; lowword = tmp;
6554 }
6556 emit_move_insn (lowword, operands[1]);
6557 emit_move_insn (highword, operands[2]);
6558 emit_move_insn (operands[5], operands[4]);
6559 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
6560 DONE;
6561 }"
6562 [(set_attr "length" "20")])
6564 (define_expand "fix_truncdfsi2"
6565 [(parallel [(set (match_operand:SI 0 "fix_trunc_dest_operand" "")
6566 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
6567 (clobber (match_dup 2))
6568 (clobber (match_dup 3))])]
6569 "(TARGET_POWER2 || TARGET_POWERPC)
6570 && TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
6571 "
6572 {
6573 if (TARGET_E500_DOUBLE)
6574 {
6575 emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
6576 DONE;
6577 }
6578 operands[2] = gen_reg_rtx (DImode);
6579 if (TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6580 && gpc_reg_operand(operands[0], GET_MODE (operands[0])))
6581 {
6582 operands[3] = gen_reg_rtx (DImode);
6583 emit_insn (gen_fix_truncdfsi2_mfpgpr (operands[0], operands[1],
6584 operands[2], operands[3]));
6585 DONE;
6586 }
6587 if (TARGET_PPC_GFXOPT)
6588 {
6589 rtx orig_dest = operands[0];
6590 if (! memory_operand (orig_dest, GET_MODE (orig_dest)))
6591 operands[0] = assign_stack_temp (SImode, GET_MODE_SIZE (SImode), 0);
6592 emit_insn (gen_fix_truncdfsi2_internal_gfxopt (operands[0], operands[1],
6593 operands[2]));
6594 if (operands[0] != orig_dest)
6595 emit_move_insn (orig_dest, operands[0]);
6596 DONE;
6597 }
6598 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
6599 }")
6601 (define_insn_and_split "*fix_truncdfsi2_internal"
6602 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6603 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6604 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
6605 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o"))]
6606 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6607 && TARGET_DOUBLE_FLOAT"
6608 "#"
6609 ""
6610 [(pc)]
6611 "
6612 {
6613 rtx lowword;
6614 gcc_assert (MEM_P (operands[3]));
6615 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
6617 emit_insn (gen_fctiwz (operands[2], operands[1]));
6618 emit_move_insn (operands[3], operands[2]);
6619 emit_move_insn (operands[0], lowword);
6620 DONE;
6621 }"
6622 [(set_attr "length" "16")])
6624 (define_insn_and_split "fix_truncdfsi2_internal_gfxopt"
6625 [(set (match_operand:SI 0 "memory_operand" "=Z")
6626 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6627 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))]
6628 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6629 && TARGET_DOUBLE_FLOAT
6630 && TARGET_PPC_GFXOPT"
6631 "#"
6632 "&& 1"
6633 [(pc)]
6634 "
6635 {
6636 emit_insn (gen_fctiwz (operands[2], operands[1]));
6637 emit_insn (gen_stfiwx (operands[0], operands[2]));
6638 DONE;
6639 }"
6640 [(set_attr "length" "16")])
6642 (define_insn_and_split "fix_truncdfsi2_mfpgpr"
6643 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6644 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "d")))
6645 (clobber (match_operand:DI 2 "gpc_reg_operand" "=d"))
6646 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))]
6647 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
6648 && TARGET_DOUBLE_FLOAT"
6649 "#"
6650 "&& 1"
6651 [(set (match_dup 2) (unspec:DI [(fix:SI (match_dup 1))] UNSPEC_FCTIWZ))
6652 (set (match_dup 3) (match_dup 2))
6653 (set (match_dup 0) (subreg:SI (match_dup 3) 4))]
6654 ""
6655 [(set_attr "length" "12")])
6657 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6658 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6659 ; because the first makes it clear that operand 0 is not live
6660 ; before the instruction.
6661 (define_insn "fctiwz"
6662 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6663 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "d"))]
6664 UNSPEC_FCTIWZ))]
6665 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS
6666 && TARGET_DOUBLE_FLOAT"
6667 "{fcirz|fctiwz} %0,%1"
6668 [(set_attr "type" "fp")])
6670 (define_expand "btruncdf2"
6671 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6672 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIZ))]
6673 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6674 "")
6676 (define_insn "*btruncdf2_fpr"
6677 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
6678 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6679 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6680 && !VECTOR_UNIT_VSX_P (DFmode)"
6681 "friz %0,%1"
6682 [(set_attr "type" "fp")])
6684 (define_insn "btruncsf2"
6685 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6686 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIZ))]
6687 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6688 "friz %0,%1"
6689 [(set_attr "type" "fp")])
6691 (define_expand "ceildf2"
6692 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6693 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "")] UNSPEC_FRIP))]
6694 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6695 "")
6697 (define_insn "*ceildf2_fpr"
6698 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6699 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIP))]
6700 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6701 && !VECTOR_UNIT_VSX_P (DFmode)"
6702 "frip %0,%1"
6703 [(set_attr "type" "fp")])
6705 (define_insn "ceilsf2"
6706 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6707 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIP))]
6708 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6709 "frip %0,%1"
6710 [(set_attr "type" "fp")])
6712 (define_expand "floordf2"
6713 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6714 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "")] UNSPEC_FRIM))]
6715 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6716 "")
6718 (define_insn "*floordf2_fpr"
6719 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6720 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIM))]
6721 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6722 && !VECTOR_UNIT_VSX_P (DFmode)"
6723 "frim %0,%1"
6724 [(set_attr "type" "fp")])
6726 (define_insn "floorsf2"
6727 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6728 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIM))]
6729 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6730 "frim %0,%1"
6731 [(set_attr "type" "fp")])
6733 ;; No VSX equivalent to frin
6734 (define_insn "rounddf2"
6735 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6736 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")] UNSPEC_FRIN))]
6737 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6738 "frin %0,%1"
6739 [(set_attr "type" "fp")])
6741 (define_insn "roundsf2"
6742 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6743 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRIN))]
6744 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6745 "frin %0,%1"
6746 [(set_attr "type" "fp")])
6748 (define_expand "ftruncdf2"
6749 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6750 (fix:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
6751 "VECTOR_UNIT_VSX_P (DFmode)"
6752 "")
6754 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6755 (define_insn "stfiwx"
6756 [(set (match_operand:SI 0 "memory_operand" "=Z")
6757 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6758 UNSPEC_STFIWX))]
6759 "TARGET_PPC_GFXOPT"
6760 "stfiwx %1,%y0"
6761 [(set_attr "type" "fpstore")])
6763 (define_expand "floatsisf2"
6764 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6765 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
6766 "TARGET_HARD_FLOAT && !TARGET_FPRS"
6767 "")
6769 (define_expand "floatdidf2"
6770 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6771 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6772 "(TARGET_POWERPC64 || TARGET_XILINX_FPU || VECTOR_UNIT_VSX_P (DFmode))
6773 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6774 "")
6776 (define_insn "*floatdidf2_fpr"
6777 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6778 (float:DF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))]
6779 "(TARGET_POWERPC64 || TARGET_XILINX_FPU)
6780 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6781 && !VECTOR_UNIT_VSX_P (DFmode)"
6782 "fcfid %0,%1"
6783 [(set_attr "type" "fp")])
6785 (define_expand "floatunsdidf2"
6786 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6787 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6788 "TARGET_VSX"
6789 "")
6791 (define_expand "fix_truncdfdi2"
6792 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6793 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "")))]
6794 "(TARGET_POWERPC64 || TARGET_XILINX_FPU || VECTOR_UNIT_VSX_P (DFmode))
6795 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6796 "")
6798 (define_insn "*fix_truncdfdi2_fpr"
6799 [(set (match_operand:DI 0 "gpc_reg_operand" "=!d#r")
6800 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d")))]
6801 "(TARGET_POWERPC64 || TARGET_XILINX_FPU)
6802 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6803 && !VECTOR_UNIT_VSX_P (DFmode)"
6804 "fctidz %0,%1"
6805 [(set_attr "type" "fp")])
6807 (define_expand "floatdisf2"
6808 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6809 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6810 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT "
6811 "
6812 {
6813 rtx val = operands[1];
6814 if (!flag_unsafe_math_optimizations)
6815 {
6816 rtx label = gen_label_rtx ();
6817 val = gen_reg_rtx (DImode);
6818 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6819 emit_label (label);
6820 }
6821 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6822 DONE;
6823 }")
6825 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6826 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6827 ;; from double rounding.
6828 (define_insn_and_split "floatdisf2_internal1"
6829 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6830 (float:SF (match_operand:DI 1 "gpc_reg_operand" "!d#r")))
6831 (clobber (match_scratch:DF 2 "=d"))]
6832 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6833 "#"
6834 "&& reload_completed"
6835 [(set (match_dup 2)
6836 (float:DF (match_dup 1)))
6837 (set (match_dup 0)
6838 (float_truncate:SF (match_dup 2)))]
6839 "")
6841 ;; Twiddles bits to avoid double rounding.
6842 ;; Bits that might be truncated when converting to DFmode are replaced
6843 ;; by a bit that won't be lost at that stage, but is below the SFmode
6844 ;; rounding position.
6845 (define_expand "floatdisf2_internal2"
6846 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6847 (const_int 53)))
6848 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6849 (const_int 2047)))
6850 (clobber (scratch:CC))])
6851 (set (match_dup 3) (plus:DI (match_dup 3)
6852 (const_int 1)))
6853 (set (match_dup 0) (plus:DI (match_dup 0)
6854 (const_int 2047)))
6855 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6856 (const_int 2)))
6857 (set (match_dup 0) (ior:DI (match_dup 0)
6858 (match_dup 1)))
6859 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6860 (const_int -2048)))
6861 (clobber (scratch:CC))])
6862 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6863 (label_ref (match_operand:DI 2 "" ""))
6864 (pc)))
6865 (set (match_dup 0) (match_dup 1))]
6866 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6867 "
6868 {
6869 operands[3] = gen_reg_rtx (DImode);
6870 operands[4] = gen_reg_rtx (CCUNSmode);
6871 }")
6872 \f
6873 ;; Define the DImode operations that can be done in a small number
6874 ;; of instructions. The & constraints are to prevent the register
6875 ;; allocator from allocating registers that overlap with the inputs
6876 ;; (for example, having an input in 7,8 and an output in 6,7). We
6877 ;; also allow for the output being the same as one of the inputs.
6879 (define_insn "*adddi3_noppc64"
6880 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6881 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6882 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6883 "! TARGET_POWERPC64"
6884 "*
6885 {
6886 if (WORDS_BIG_ENDIAN)
6887 return (GET_CODE (operands[2])) != CONST_INT
6888 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6889 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6890 else
6891 return (GET_CODE (operands[2])) != CONST_INT
6892 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6893 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6894 }"
6895 [(set_attr "type" "two")
6896 (set_attr "length" "8")])
6898 (define_insn "*subdi3_noppc64"
6899 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6900 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6901 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6902 "! TARGET_POWERPC64"
6903 "*
6904 {
6905 if (WORDS_BIG_ENDIAN)
6906 return (GET_CODE (operands[1]) != CONST_INT)
6907 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6908 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6909 else
6910 return (GET_CODE (operands[1]) != CONST_INT)
6911 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6912 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6913 }"
6914 [(set_attr "type" "two")
6915 (set_attr "length" "8")])
6917 (define_insn "*negdi2_noppc64"
6918 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6919 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6920 "! TARGET_POWERPC64"
6921 "*
6922 {
6923 return (WORDS_BIG_ENDIAN)
6924 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6925 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6926 }"
6927 [(set_attr "type" "two")
6928 (set_attr "length" "8")])
6930 (define_expand "mulsidi3"
6931 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6932 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6933 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6934 "! TARGET_POWERPC64"
6935 "
6936 {
6937 if (! TARGET_POWER && ! TARGET_POWERPC)
6938 {
6939 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6940 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6941 emit_insn (gen_mull_call ());
6942 if (WORDS_BIG_ENDIAN)
6943 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6944 else
6945 {
6946 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6947 gen_rtx_REG (SImode, 3));
6948 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6949 gen_rtx_REG (SImode, 4));
6950 }
6951 DONE;
6952 }
6953 else if (TARGET_POWER)
6954 {
6955 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6956 DONE;
6957 }
6958 }")
6960 (define_insn "mulsidi3_mq"
6961 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6962 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6963 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6964 (clobber (match_scratch:SI 3 "=q"))]
6965 "TARGET_POWER"
6966 "mul %0,%1,%2\;mfmq %L0"
6967 [(set_attr "type" "imul")
6968 (set_attr "length" "8")])
6970 (define_insn "*mulsidi3_no_mq"
6971 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6972 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6973 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6974 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6975 "*
6976 {
6977 return (WORDS_BIG_ENDIAN)
6978 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6979 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6980 }"
6981 [(set_attr "type" "imul")
6982 (set_attr "length" "8")])
6984 (define_split
6985 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6986 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6987 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6988 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6989 [(set (match_dup 3)
6990 (truncate:SI
6991 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6992 (sign_extend:DI (match_dup 2)))
6993 (const_int 32))))
6994 (set (match_dup 4)
6995 (mult:SI (match_dup 1)
6996 (match_dup 2)))]
6997 "
6998 {
6999 int endian = (WORDS_BIG_ENDIAN == 0);
7000 operands[3] = operand_subword (operands[0], endian, 0, DImode);
7001 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
7002 }")
7004 (define_expand "umulsidi3"
7005 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7006 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7007 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7008 "TARGET_POWERPC && ! TARGET_POWERPC64"
7009 "
7010 {
7011 if (TARGET_POWER)
7012 {
7013 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
7014 DONE;
7015 }
7016 }")
7018 (define_insn "umulsidi3_mq"
7019 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7020 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7021 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
7022 (clobber (match_scratch:SI 3 "=q"))]
7023 "TARGET_POWERPC && TARGET_POWER"
7024 "*
7025 {
7026 return (WORDS_BIG_ENDIAN)
7027 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
7028 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
7029 }"
7030 [(set_attr "type" "imul")
7031 (set_attr "length" "8")])
7033 (define_insn "*umulsidi3_no_mq"
7034 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
7035 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
7036 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
7037 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
7038 "*
7039 {
7040 return (WORDS_BIG_ENDIAN)
7041 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
7042 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
7043 }"
7044 [(set_attr "type" "imul")
7045 (set_attr "length" "8")])
7047 (define_split
7048 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7049 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
7050 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
7051 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
7052 [(set (match_dup 3)
7053 (truncate:SI
7054 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
7055 (zero_extend:DI (match_dup 2)))
7056 (const_int 32))))
7057 (set (match_dup 4)
7058 (mult:SI (match_dup 1)
7059 (match_dup 2)))]
7060 "
7061 {
7062 int endian = (WORDS_BIG_ENDIAN == 0);
7063 operands[3] = operand_subword (operands[0], endian, 0, DImode);
7064 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
7065 }")
7067 (define_expand "smulsi3_highpart"
7068 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7069 (truncate:SI
7070 (lshiftrt:DI (mult:DI (sign_extend:DI
7071 (match_operand:SI 1 "gpc_reg_operand" ""))
7072 (sign_extend:DI
7073 (match_operand:SI 2 "gpc_reg_operand" "")))
7074 (const_int 32))))]
7075 ""
7076 "
7077 {
7078 if (! TARGET_POWER && ! TARGET_POWERPC)
7079 {
7080 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
7081 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
7082 emit_insn (gen_mulh_call ());
7083 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
7084 DONE;
7085 }
7086 else if (TARGET_POWER)
7087 {
7088 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7089 DONE;
7090 }
7091 }")
7093 (define_insn "smulsi3_highpart_mq"
7094 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7095 (truncate:SI
7096 (lshiftrt:DI (mult:DI (sign_extend:DI
7097 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7098 (sign_extend:DI
7099 (match_operand:SI 2 "gpc_reg_operand" "r")))
7100 (const_int 32))))
7101 (clobber (match_scratch:SI 3 "=q"))]
7102 "TARGET_POWER"
7103 "mul %0,%1,%2"
7104 [(set_attr "type" "imul")])
7106 (define_insn "*smulsi3_highpart_no_mq"
7107 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7108 (truncate:SI
7109 (lshiftrt:DI (mult:DI (sign_extend:DI
7110 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7111 (sign_extend:DI
7112 (match_operand:SI 2 "gpc_reg_operand" "r")))
7113 (const_int 32))))]
7114 "TARGET_POWERPC && ! TARGET_POWER"
7115 "mulhw %0,%1,%2"
7116 [(set_attr "type" "imul")])
7118 (define_expand "umulsi3_highpart"
7119 [(set (match_operand:SI 0 "gpc_reg_operand" "")
7120 (truncate:SI
7121 (lshiftrt:DI (mult:DI (zero_extend:DI
7122 (match_operand:SI 1 "gpc_reg_operand" ""))
7123 (zero_extend:DI
7124 (match_operand:SI 2 "gpc_reg_operand" "")))
7125 (const_int 32))))]
7126 "TARGET_POWERPC"
7127 "
7128 {
7129 if (TARGET_POWER)
7130 {
7131 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
7132 DONE;
7133 }
7134 }")
7136 (define_insn "umulsi3_highpart_mq"
7137 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7138 (truncate:SI
7139 (lshiftrt:DI (mult:DI (zero_extend:DI
7140 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7141 (zero_extend:DI
7142 (match_operand:SI 2 "gpc_reg_operand" "r")))
7143 (const_int 32))))
7144 (clobber (match_scratch:SI 3 "=q"))]
7145 "TARGET_POWERPC && TARGET_POWER"
7146 "mulhwu %0,%1,%2"
7147 [(set_attr "type" "imul")])
7149 (define_insn "*umulsi3_highpart_no_mq"
7150 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7151 (truncate:SI
7152 (lshiftrt:DI (mult:DI (zero_extend:DI
7153 (match_operand:SI 1 "gpc_reg_operand" "%r"))
7154 (zero_extend:DI
7155 (match_operand:SI 2 "gpc_reg_operand" "r")))
7156 (const_int 32))))]
7157 "TARGET_POWERPC && ! TARGET_POWER"
7158 "mulhwu %0,%1,%2"
7159 [(set_attr "type" "imul")])
7161 ;; If operands 0 and 2 are in the same register, we have a problem. But
7162 ;; operands 0 and 1 (the usual case) can be in the same register. That's
7163 ;; why we have the strange constraints below.
7164 (define_insn "ashldi3_power"
7165 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7166 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7167 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7168 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7169 "TARGET_POWER"
7170 "@
7171 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
7172 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7173 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
7174 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
7175 [(set_attr "length" "8")])
7177 (define_insn "lshrdi3_power"
7178 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
7179 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
7180 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
7181 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
7182 "TARGET_POWER"
7183 "@
7184 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
7185 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7186 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
7187 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
7188 [(set_attr "length" "8")])
7190 ;; Shift by a variable amount is too complex to be worth open-coding. We
7191 ;; just handle shifts by constants.
7192 (define_insn "ashrdi3_power"
7193 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7194 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7195 (match_operand:SI 2 "const_int_operand" "M,i")))
7196 (clobber (match_scratch:SI 3 "=X,q"))]
7197 "TARGET_POWER"
7198 "@
7199 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7200 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
7201 [(set_attr "type" "shift")
7202 (set_attr "length" "8")])
7204 (define_insn "ashrdi3_no_power"
7205 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
7206 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7207 (match_operand:SI 2 "const_int_operand" "M,i")))]
7208 "TARGET_32BIT && !TARGET_POWERPC64 && !TARGET_POWER && WORDS_BIG_ENDIAN"
7209 "@
7210 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
7211 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
7212 [(set_attr "type" "two,three")
7213 (set_attr "length" "8,12")])
7215 (define_insn "*ashrdisi3_noppc64"
7216 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
7217 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7218 (const_int 32)) 4))]
7219 "TARGET_32BIT && !TARGET_POWERPC64"
7220 "*
7221 {
7222 if (REGNO (operands[0]) == REGNO (operands[1]))
7223 return \"\";
7224 else
7225 return \"mr %0,%1\";
7226 }"
7227 [(set_attr "length" "4")])
7229 \f
7230 ;; PowerPC64 DImode operations.
7232 (define_expand "absdi2"
7233 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7234 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
7235 "TARGET_POWERPC64"
7236 "
7237 {
7238 if (TARGET_ISEL)
7239 emit_insn (gen_absdi2_isel (operands[0], operands[1]));
7240 else
7241 emit_insn (gen_absdi2_internal (operands[0], operands[1]));
7242 DONE;
7243 }")
7245 (define_insn_and_split "absdi2_internal"
7246 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7247 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
7248 (clobber (match_scratch:DI 2 "=&r,&r"))]
7249 "TARGET_POWERPC64 && !TARGET_ISEL"
7250 "#"
7251 "&& reload_completed"
7252 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7253 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7254 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
7255 "")
7257 (define_insn_and_split "*nabsdi2"
7258 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
7259 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
7260 (clobber (match_scratch:DI 2 "=&r,&r"))]
7261 "TARGET_POWERPC64 && !TARGET_ISEL"
7262 "#"
7263 "&& reload_completed"
7264 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
7265 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
7266 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
7267 "")
7269 (define_insn "muldi3"
7270 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7271 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7272 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
7273 "TARGET_POWERPC64"
7274 "@
7275 mulld %0,%1,%2
7276 mulli %0,%1,%2"
7277 [(set (attr "type")
7278 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
7279 (const_string "imul3")
7280 (match_operand:SI 2 "short_cint_operand" "")
7281 (const_string "imul2")]
7282 (const_string "lmul")))])
7284 (define_insn "*muldi3_internal1"
7285 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7286 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7287 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7288 (const_int 0)))
7289 (clobber (match_scratch:DI 3 "=r,r"))]
7290 "TARGET_POWERPC64"
7291 "@
7292 mulld. %3,%1,%2
7293 #"
7294 [(set_attr "type" "lmul_compare")
7295 (set_attr "length" "4,8")])
7297 (define_split
7298 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7299 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7300 (match_operand:DI 2 "gpc_reg_operand" ""))
7301 (const_int 0)))
7302 (clobber (match_scratch:DI 3 ""))]
7303 "TARGET_POWERPC64 && reload_completed"
7304 [(set (match_dup 3)
7305 (mult:DI (match_dup 1) (match_dup 2)))
7306 (set (match_dup 0)
7307 (compare:CC (match_dup 3)
7308 (const_int 0)))]
7309 "")
7311 (define_insn "*muldi3_internal2"
7312 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7313 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
7314 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
7315 (const_int 0)))
7316 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7317 (mult:DI (match_dup 1) (match_dup 2)))]
7318 "TARGET_POWERPC64"
7319 "@
7320 mulld. %0,%1,%2
7321 #"
7322 [(set_attr "type" "lmul_compare")
7323 (set_attr "length" "4,8")])
7325 (define_split
7326 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7327 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
7328 (match_operand:DI 2 "gpc_reg_operand" ""))
7329 (const_int 0)))
7330 (set (match_operand:DI 0 "gpc_reg_operand" "")
7331 (mult:DI (match_dup 1) (match_dup 2)))]
7332 "TARGET_POWERPC64 && reload_completed"
7333 [(set (match_dup 0)
7334 (mult:DI (match_dup 1) (match_dup 2)))
7335 (set (match_dup 3)
7336 (compare:CC (match_dup 0)
7337 (const_int 0)))]
7338 "")
7340 (define_insn "smuldi3_highpart"
7341 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7342 (truncate:DI
7343 (lshiftrt:TI (mult:TI (sign_extend:TI
7344 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7345 (sign_extend:TI
7346 (match_operand:DI 2 "gpc_reg_operand" "r")))
7347 (const_int 64))))]
7348 "TARGET_POWERPC64"
7349 "mulhd %0,%1,%2"
7350 [(set_attr "type" "lmul")])
7352 (define_insn "umuldi3_highpart"
7353 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7354 (truncate:DI
7355 (lshiftrt:TI (mult:TI (zero_extend:TI
7356 (match_operand:DI 1 "gpc_reg_operand" "%r"))
7357 (zero_extend:TI
7358 (match_operand:DI 2 "gpc_reg_operand" "r")))
7359 (const_int 64))))]
7360 "TARGET_POWERPC64"
7361 "mulhdu %0,%1,%2"
7362 [(set_attr "type" "lmul")])
7364 (define_insn "rotldi3"
7365 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7366 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7367 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
7368 "TARGET_POWERPC64"
7369 "@
7370 rldcl %0,%1,%2,0
7371 rldicl %0,%1,%H2,0"
7372 [(set_attr "type" "var_shift_rotate,integer")])
7374 (define_insn "*rotldi3_internal2"
7375 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7376 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7377 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7378 (const_int 0)))
7379 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7380 "TARGET_64BIT"
7381 "@
7382 rldcl. %3,%1,%2,0
7383 rldicl. %3,%1,%H2,0
7384 #
7385 #"
7386 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7387 (set_attr "length" "4,4,8,8")])
7389 (define_split
7390 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7391 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7392 (match_operand:DI 2 "reg_or_cint_operand" ""))
7393 (const_int 0)))
7394 (clobber (match_scratch:DI 3 ""))]
7395 "TARGET_POWERPC64 && reload_completed"
7396 [(set (match_dup 3)
7397 (rotate:DI (match_dup 1) (match_dup 2)))
7398 (set (match_dup 0)
7399 (compare:CC (match_dup 3)
7400 (const_int 0)))]
7401 "")
7403 (define_insn "*rotldi3_internal3"
7404 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7405 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7406 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7407 (const_int 0)))
7408 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7409 (rotate:DI (match_dup 1) (match_dup 2)))]
7410 "TARGET_64BIT"
7411 "@
7412 rldcl. %0,%1,%2,0
7413 rldicl. %0,%1,%H2,0
7414 #
7415 #"
7416 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7417 (set_attr "length" "4,4,8,8")])
7419 (define_split
7420 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7421 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7422 (match_operand:DI 2 "reg_or_cint_operand" ""))
7423 (const_int 0)))
7424 (set (match_operand:DI 0 "gpc_reg_operand" "")
7425 (rotate:DI (match_dup 1) (match_dup 2)))]
7426 "TARGET_POWERPC64 && reload_completed"
7427 [(set (match_dup 0)
7428 (rotate:DI (match_dup 1) (match_dup 2)))
7429 (set (match_dup 3)
7430 (compare:CC (match_dup 0)
7431 (const_int 0)))]
7432 "")
7434 (define_insn "*rotldi3_internal4"
7435 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7436 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7437 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
7438 (match_operand:DI 3 "mask64_operand" "n,n")))]
7439 "TARGET_POWERPC64"
7440 "@
7441 rldc%B3 %0,%1,%2,%S3
7442 rldic%B3 %0,%1,%H2,%S3"
7443 [(set_attr "type" "var_shift_rotate,integer")])
7445 (define_insn "*rotldi3_internal5"
7446 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7447 (compare:CC (and:DI
7448 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7449 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7450 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7451 (const_int 0)))
7452 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
7453 "TARGET_64BIT"
7454 "@
7455 rldc%B3. %4,%1,%2,%S3
7456 rldic%B3. %4,%1,%H2,%S3
7457 #
7458 #"
7459 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7460 (set_attr "length" "4,4,8,8")])
7462 (define_split
7463 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7464 (compare:CC (and:DI
7465 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7466 (match_operand:DI 2 "reg_or_cint_operand" ""))
7467 (match_operand:DI 3 "mask64_operand" ""))
7468 (const_int 0)))
7469 (clobber (match_scratch:DI 4 ""))]
7470 "TARGET_POWERPC64 && reload_completed"
7471 [(set (match_dup 4)
7472 (and:DI (rotate:DI (match_dup 1)
7473 (match_dup 2))
7474 (match_dup 3)))
7475 (set (match_dup 0)
7476 (compare:CC (match_dup 4)
7477 (const_int 0)))]
7478 "")
7480 (define_insn "*rotldi3_internal6"
7481 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
7482 (compare:CC (and:DI
7483 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7484 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
7485 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
7486 (const_int 0)))
7487 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7488 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7489 "TARGET_64BIT"
7490 "@
7491 rldc%B3. %0,%1,%2,%S3
7492 rldic%B3. %0,%1,%H2,%S3
7493 #
7494 #"
7495 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7496 (set_attr "length" "4,4,8,8")])
7498 (define_split
7499 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7500 (compare:CC (and:DI
7501 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7502 (match_operand:DI 2 "reg_or_cint_operand" ""))
7503 (match_operand:DI 3 "mask64_operand" ""))
7504 (const_int 0)))
7505 (set (match_operand:DI 0 "gpc_reg_operand" "")
7506 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7507 "TARGET_POWERPC64 && reload_completed"
7508 [(set (match_dup 0)
7509 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
7510 (set (match_dup 4)
7511 (compare:CC (match_dup 0)
7512 (const_int 0)))]
7513 "")
7515 (define_insn "*rotldi3_internal7"
7516 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7517 (zero_extend:DI
7518 (subreg:QI
7519 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7520 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7521 "TARGET_POWERPC64"
7522 "@
7523 rldcl %0,%1,%2,56
7524 rldicl %0,%1,%H2,56"
7525 [(set_attr "type" "var_shift_rotate,integer")])
7527 (define_insn "*rotldi3_internal8"
7528 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7529 (compare:CC (zero_extend:DI
7530 (subreg:QI
7531 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7532 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7533 (const_int 0)))
7534 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7535 "TARGET_64BIT"
7536 "@
7537 rldcl. %3,%1,%2,56
7538 rldicl. %3,%1,%H2,56
7539 #
7540 #"
7541 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7542 (set_attr "length" "4,4,8,8")])
7544 (define_split
7545 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7546 (compare:CC (zero_extend:DI
7547 (subreg:QI
7548 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7549 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7550 (const_int 0)))
7551 (clobber (match_scratch:DI 3 ""))]
7552 "TARGET_POWERPC64 && reload_completed"
7553 [(set (match_dup 3)
7554 (zero_extend:DI (subreg:QI
7555 (rotate:DI (match_dup 1)
7556 (match_dup 2)) 0)))
7557 (set (match_dup 0)
7558 (compare:CC (match_dup 3)
7559 (const_int 0)))]
7560 "")
7562 (define_insn "*rotldi3_internal9"
7563 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7564 (compare:CC (zero_extend:DI
7565 (subreg:QI
7566 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7567 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7568 (const_int 0)))
7569 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7570 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7571 "TARGET_64BIT"
7572 "@
7573 rldcl. %0,%1,%2,56
7574 rldicl. %0,%1,%H2,56
7575 #
7576 #"
7577 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7578 (set_attr "length" "4,4,8,8")])
7580 (define_split
7581 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7582 (compare:CC (zero_extend:DI
7583 (subreg:QI
7584 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7585 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7586 (const_int 0)))
7587 (set (match_operand:DI 0 "gpc_reg_operand" "")
7588 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7589 "TARGET_POWERPC64 && reload_completed"
7590 [(set (match_dup 0)
7591 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7592 (set (match_dup 3)
7593 (compare:CC (match_dup 0)
7594 (const_int 0)))]
7595 "")
7597 (define_insn "*rotldi3_internal10"
7598 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7599 (zero_extend:DI
7600 (subreg:HI
7601 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7602 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7603 "TARGET_POWERPC64"
7604 "@
7605 rldcl %0,%1,%2,48
7606 rldicl %0,%1,%H2,48"
7607 [(set_attr "type" "var_shift_rotate,integer")])
7609 (define_insn "*rotldi3_internal11"
7610 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7611 (compare:CC (zero_extend:DI
7612 (subreg:HI
7613 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7614 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7615 (const_int 0)))
7616 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7617 "TARGET_64BIT"
7618 "@
7619 rldcl. %3,%1,%2,48
7620 rldicl. %3,%1,%H2,48
7621 #
7622 #"
7623 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7624 (set_attr "length" "4,4,8,8")])
7626 (define_split
7627 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7628 (compare:CC (zero_extend:DI
7629 (subreg:HI
7630 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7631 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7632 (const_int 0)))
7633 (clobber (match_scratch:DI 3 ""))]
7634 "TARGET_POWERPC64 && reload_completed"
7635 [(set (match_dup 3)
7636 (zero_extend:DI (subreg:HI
7637 (rotate:DI (match_dup 1)
7638 (match_dup 2)) 0)))
7639 (set (match_dup 0)
7640 (compare:CC (match_dup 3)
7641 (const_int 0)))]
7642 "")
7644 (define_insn "*rotldi3_internal12"
7645 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7646 (compare:CC (zero_extend:DI
7647 (subreg:HI
7648 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7649 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7650 (const_int 0)))
7651 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7652 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7653 "TARGET_64BIT"
7654 "@
7655 rldcl. %0,%1,%2,48
7656 rldicl. %0,%1,%H2,48
7657 #
7658 #"
7659 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7660 (set_attr "length" "4,4,8,8")])
7662 (define_split
7663 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7664 (compare:CC (zero_extend:DI
7665 (subreg:HI
7666 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7667 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7668 (const_int 0)))
7669 (set (match_operand:DI 0 "gpc_reg_operand" "")
7670 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7671 "TARGET_POWERPC64 && reload_completed"
7672 [(set (match_dup 0)
7673 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7674 (set (match_dup 3)
7675 (compare:CC (match_dup 0)
7676 (const_int 0)))]
7677 "")
7679 (define_insn "*rotldi3_internal13"
7680 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7681 (zero_extend:DI
7682 (subreg:SI
7683 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7684 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7685 "TARGET_POWERPC64"
7686 "@
7687 rldcl %0,%1,%2,32
7688 rldicl %0,%1,%H2,32"
7689 [(set_attr "type" "var_shift_rotate,integer")])
7691 (define_insn "*rotldi3_internal14"
7692 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7693 (compare:CC (zero_extend:DI
7694 (subreg:SI
7695 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7696 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7697 (const_int 0)))
7698 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7699 "TARGET_64BIT"
7700 "@
7701 rldcl. %3,%1,%2,32
7702 rldicl. %3,%1,%H2,32
7703 #
7704 #"
7705 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7706 (set_attr "length" "4,4,8,8")])
7708 (define_split
7709 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7710 (compare:CC (zero_extend:DI
7711 (subreg:SI
7712 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7713 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7714 (const_int 0)))
7715 (clobber (match_scratch:DI 3 ""))]
7716 "TARGET_POWERPC64 && reload_completed"
7717 [(set (match_dup 3)
7718 (zero_extend:DI (subreg:SI
7719 (rotate:DI (match_dup 1)
7720 (match_dup 2)) 0)))
7721 (set (match_dup 0)
7722 (compare:CC (match_dup 3)
7723 (const_int 0)))]
7724 "")
7726 (define_insn "*rotldi3_internal15"
7727 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7728 (compare:CC (zero_extend:DI
7729 (subreg:SI
7730 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7731 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7732 (const_int 0)))
7733 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7734 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7735 "TARGET_64BIT"
7736 "@
7737 rldcl. %0,%1,%2,32
7738 rldicl. %0,%1,%H2,32
7739 #
7740 #"
7741 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7742 (set_attr "length" "4,4,8,8")])
7744 (define_split
7745 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7746 (compare:CC (zero_extend:DI
7747 (subreg:SI
7748 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7749 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7750 (const_int 0)))
7751 (set (match_operand:DI 0 "gpc_reg_operand" "")
7752 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7753 "TARGET_POWERPC64 && reload_completed"
7754 [(set (match_dup 0)
7755 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7756 (set (match_dup 3)
7757 (compare:CC (match_dup 0)
7758 (const_int 0)))]
7759 "")
7761 (define_expand "ashldi3"
7762 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7763 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7764 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7765 "TARGET_POWERPC64 || TARGET_POWER"
7766 "
7767 {
7768 if (TARGET_POWERPC64)
7769 ;
7770 else if (TARGET_POWER)
7771 {
7772 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7773 DONE;
7774 }
7775 else
7776 FAIL;
7777 }")
7779 (define_insn "*ashldi3_internal1"
7780 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7781 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7782 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7783 "TARGET_POWERPC64"
7784 "@
7785 sld %0,%1,%2
7786 sldi %0,%1,%H2"
7787 [(set_attr "type" "var_shift_rotate,shift")])
7789 (define_insn "*ashldi3_internal2"
7790 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7791 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7792 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7793 (const_int 0)))
7794 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7795 "TARGET_64BIT"
7796 "@
7797 sld. %3,%1,%2
7798 sldi. %3,%1,%H2
7799 #
7800 #"
7801 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7802 (set_attr "length" "4,4,8,8")])
7804 (define_split
7805 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7806 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7807 (match_operand:SI 2 "reg_or_cint_operand" ""))
7808 (const_int 0)))
7809 (clobber (match_scratch:DI 3 ""))]
7810 "TARGET_POWERPC64 && reload_completed"
7811 [(set (match_dup 3)
7812 (ashift:DI (match_dup 1) (match_dup 2)))
7813 (set (match_dup 0)
7814 (compare:CC (match_dup 3)
7815 (const_int 0)))]
7816 "")
7818 (define_insn "*ashldi3_internal3"
7819 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7820 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7821 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7822 (const_int 0)))
7823 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7824 (ashift:DI (match_dup 1) (match_dup 2)))]
7825 "TARGET_64BIT"
7826 "@
7827 sld. %0,%1,%2
7828 sldi. %0,%1,%H2
7829 #
7830 #"
7831 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7832 (set_attr "length" "4,4,8,8")])
7834 (define_split
7835 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7836 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7837 (match_operand:SI 2 "reg_or_cint_operand" ""))
7838 (const_int 0)))
7839 (set (match_operand:DI 0 "gpc_reg_operand" "")
7840 (ashift:DI (match_dup 1) (match_dup 2)))]
7841 "TARGET_POWERPC64 && reload_completed"
7842 [(set (match_dup 0)
7843 (ashift:DI (match_dup 1) (match_dup 2)))
7844 (set (match_dup 3)
7845 (compare:CC (match_dup 0)
7846 (const_int 0)))]
7847 "")
7849 (define_insn "*ashldi3_internal4"
7850 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7851 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7852 (match_operand:SI 2 "const_int_operand" "i"))
7853 (match_operand:DI 3 "const_int_operand" "n")))]
7854 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7855 "rldic %0,%1,%H2,%W3")
7857 (define_insn "ashldi3_internal5"
7858 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7859 (compare:CC
7860 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7861 (match_operand:SI 2 "const_int_operand" "i,i"))
7862 (match_operand:DI 3 "const_int_operand" "n,n"))
7863 (const_int 0)))
7864 (clobber (match_scratch:DI 4 "=r,r"))]
7865 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7866 "@
7867 rldic. %4,%1,%H2,%W3
7868 #"
7869 [(set_attr "type" "compare")
7870 (set_attr "length" "4,8")])
7872 (define_split
7873 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7874 (compare:CC
7875 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7876 (match_operand:SI 2 "const_int_operand" ""))
7877 (match_operand:DI 3 "const_int_operand" ""))
7878 (const_int 0)))
7879 (clobber (match_scratch:DI 4 ""))]
7880 "TARGET_POWERPC64 && reload_completed
7881 && includes_rldic_lshift_p (operands[2], operands[3])"
7882 [(set (match_dup 4)
7883 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7884 (match_dup 3)))
7885 (set (match_dup 0)
7886 (compare:CC (match_dup 4)
7887 (const_int 0)))]
7888 "")
7890 (define_insn "*ashldi3_internal6"
7891 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7892 (compare:CC
7893 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7894 (match_operand:SI 2 "const_int_operand" "i,i"))
7895 (match_operand:DI 3 "const_int_operand" "n,n"))
7896 (const_int 0)))
7897 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7898 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7899 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7900 "@
7901 rldic. %0,%1,%H2,%W3
7902 #"
7903 [(set_attr "type" "compare")
7904 (set_attr "length" "4,8")])
7906 (define_split
7907 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7908 (compare:CC
7909 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7910 (match_operand:SI 2 "const_int_operand" ""))
7911 (match_operand:DI 3 "const_int_operand" ""))
7912 (const_int 0)))
7913 (set (match_operand:DI 0 "gpc_reg_operand" "")
7914 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7915 "TARGET_POWERPC64 && reload_completed
7916 && includes_rldic_lshift_p (operands[2], operands[3])"
7917 [(set (match_dup 0)
7918 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7919 (match_dup 3)))
7920 (set (match_dup 4)
7921 (compare:CC (match_dup 0)
7922 (const_int 0)))]
7923 "")
7925 (define_insn "*ashldi3_internal7"
7926 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7927 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7928 (match_operand:SI 2 "const_int_operand" "i"))
7929 (match_operand:DI 3 "mask64_operand" "n")))]
7930 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7931 "rldicr %0,%1,%H2,%S3")
7933 (define_insn "ashldi3_internal8"
7934 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7935 (compare:CC
7936 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7937 (match_operand:SI 2 "const_int_operand" "i,i"))
7938 (match_operand:DI 3 "mask64_operand" "n,n"))
7939 (const_int 0)))
7940 (clobber (match_scratch:DI 4 "=r,r"))]
7941 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7942 "@
7943 rldicr. %4,%1,%H2,%S3
7944 #"
7945 [(set_attr "type" "compare")
7946 (set_attr "length" "4,8")])
7948 (define_split
7949 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7950 (compare:CC
7951 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7952 (match_operand:SI 2 "const_int_operand" ""))
7953 (match_operand:DI 3 "mask64_operand" ""))
7954 (const_int 0)))
7955 (clobber (match_scratch:DI 4 ""))]
7956 "TARGET_POWERPC64 && reload_completed
7957 && includes_rldicr_lshift_p (operands[2], operands[3])"
7958 [(set (match_dup 4)
7959 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7960 (match_dup 3)))
7961 (set (match_dup 0)
7962 (compare:CC (match_dup 4)
7963 (const_int 0)))]
7964 "")
7966 (define_insn "*ashldi3_internal9"
7967 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7968 (compare:CC
7969 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7970 (match_operand:SI 2 "const_int_operand" "i,i"))
7971 (match_operand:DI 3 "mask64_operand" "n,n"))
7972 (const_int 0)))
7973 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7974 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7975 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7976 "@
7977 rldicr. %0,%1,%H2,%S3
7978 #"
7979 [(set_attr "type" "compare")
7980 (set_attr "length" "4,8")])
7982 (define_split
7983 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7984 (compare:CC
7985 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7986 (match_operand:SI 2 "const_int_operand" ""))
7987 (match_operand:DI 3 "mask64_operand" ""))
7988 (const_int 0)))
7989 (set (match_operand:DI 0 "gpc_reg_operand" "")
7990 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7991 "TARGET_POWERPC64 && reload_completed
7992 && includes_rldicr_lshift_p (operands[2], operands[3])"
7993 [(set (match_dup 0)
7994 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7995 (match_dup 3)))
7996 (set (match_dup 4)
7997 (compare:CC (match_dup 0)
7998 (const_int 0)))]
7999 "")
8001 (define_expand "lshrdi3"
8002 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8003 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8004 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8005 "TARGET_POWERPC64 || TARGET_POWER"
8006 "
8007 {
8008 if (TARGET_POWERPC64)
8009 ;
8010 else if (TARGET_POWER)
8011 {
8012 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
8013 DONE;
8014 }
8015 else
8016 FAIL;
8017 }")
8019 (define_insn "*lshrdi3_internal1"
8020 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8021 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8022 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8023 "TARGET_POWERPC64"
8024 "@
8025 srd %0,%1,%2
8026 srdi %0,%1,%H2"
8027 [(set_attr "type" "var_shift_rotate,shift")])
8029 (define_insn "*lshrdi3_internal2"
8030 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8031 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8032 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8033 (const_int 0)))
8034 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8035 "TARGET_64BIT "
8036 "@
8037 srd. %3,%1,%2
8038 srdi. %3,%1,%H2
8039 #
8040 #"
8041 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8042 (set_attr "length" "4,4,8,8")])
8044 (define_split
8045 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8046 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8047 (match_operand:SI 2 "reg_or_cint_operand" ""))
8048 (const_int 0)))
8049 (clobber (match_scratch:DI 3 ""))]
8050 "TARGET_POWERPC64 && reload_completed"
8051 [(set (match_dup 3)
8052 (lshiftrt:DI (match_dup 1) (match_dup 2)))
8053 (set (match_dup 0)
8054 (compare:CC (match_dup 3)
8055 (const_int 0)))]
8056 "")
8058 (define_insn "*lshrdi3_internal3"
8059 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8060 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8061 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8062 (const_int 0)))
8063 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8064 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8065 "TARGET_64BIT"
8066 "@
8067 srd. %0,%1,%2
8068 srdi. %0,%1,%H2
8069 #
8070 #"
8071 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8072 (set_attr "length" "4,4,8,8")])
8074 (define_split
8075 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8076 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8077 (match_operand:SI 2 "reg_or_cint_operand" ""))
8078 (const_int 0)))
8079 (set (match_operand:DI 0 "gpc_reg_operand" "")
8080 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
8081 "TARGET_POWERPC64 && reload_completed"
8082 [(set (match_dup 0)
8083 (lshiftrt:DI (match_dup 1) (match_dup 2)))
8084 (set (match_dup 3)
8085 (compare:CC (match_dup 0)
8086 (const_int 0)))]
8087 "")
8089 (define_expand "ashrdi3"
8090 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8091 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8092 (match_operand:SI 2 "reg_or_cint_operand" "")))]
8093 "WORDS_BIG_ENDIAN"
8094 "
8095 {
8096 if (TARGET_POWERPC64)
8097 ;
8098 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
8099 {
8100 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
8101 DONE;
8102 }
8103 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
8104 && WORDS_BIG_ENDIAN)
8105 {
8106 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
8107 DONE;
8108 }
8109 else
8110 FAIL;
8111 }")
8113 (define_insn "*ashrdi3_internal1"
8114 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8115 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
8116 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
8117 "TARGET_POWERPC64"
8118 "@
8119 srad %0,%1,%2
8120 sradi %0,%1,%H2"
8121 [(set_attr "type" "var_shift_rotate,shift")])
8123 (define_insn "*ashrdi3_internal2"
8124 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
8125 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8126 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8127 (const_int 0)))
8128 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
8129 "TARGET_64BIT"
8130 "@
8131 srad. %3,%1,%2
8132 sradi. %3,%1,%H2
8133 #
8134 #"
8135 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8136 (set_attr "length" "4,4,8,8")])
8138 (define_split
8139 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
8140 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8141 (match_operand:SI 2 "reg_or_cint_operand" ""))
8142 (const_int 0)))
8143 (clobber (match_scratch:DI 3 ""))]
8144 "TARGET_POWERPC64 && reload_completed"
8145 [(set (match_dup 3)
8146 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8147 (set (match_dup 0)
8148 (compare:CC (match_dup 3)
8149 (const_int 0)))]
8150 "")
8152 (define_insn "*ashrdi3_internal3"
8153 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
8154 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
8155 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
8156 (const_int 0)))
8157 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8158 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8159 "TARGET_64BIT"
8160 "@
8161 srad. %0,%1,%2
8162 sradi. %0,%1,%H2
8163 #
8164 #"
8165 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
8166 (set_attr "length" "4,4,8,8")])
8168 (define_split
8169 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
8170 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
8171 (match_operand:SI 2 "reg_or_cint_operand" ""))
8172 (const_int 0)))
8173 (set (match_operand:DI 0 "gpc_reg_operand" "")
8174 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
8175 "TARGET_POWERPC64 && reload_completed"
8176 [(set (match_dup 0)
8177 (ashiftrt:DI (match_dup 1) (match_dup 2)))
8178 (set (match_dup 3)
8179 (compare:CC (match_dup 0)
8180 (const_int 0)))]
8181 "")
8183 (define_expand "anddi3"
8184 [(parallel
8185 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8186 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8187 (match_operand:DI 2 "and64_2_operand" "")))
8188 (clobber (match_scratch:CC 3 ""))])]
8189 "TARGET_POWERPC64"
8190 "")
8192 (define_insn "anddi3_mc"
8193 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
8194 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
8195 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
8196 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
8197 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
8198 "@
8199 and %0,%1,%2
8200 rldic%B2 %0,%1,0,%S2
8201 rlwinm %0,%1,0,%m2,%M2
8202 andi. %0,%1,%b2
8203 andis. %0,%1,%u2
8204 #"
8205 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
8206 (set_attr "length" "4,4,4,4,4,8")])
8208 (define_insn "anddi3_nomc"
8209 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
8210 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
8211 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
8212 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
8213 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
8214 "@
8215 and %0,%1,%2
8216 rldic%B2 %0,%1,0,%S2
8217 rlwinm %0,%1,0,%m2,%M2
8218 #"
8219 [(set_attr "length" "4,4,4,8")])
8221 (define_split
8222 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8223 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8224 (match_operand:DI 2 "mask64_2_operand" "")))
8225 (clobber (match_scratch:CC 3 ""))]
8226 "TARGET_POWERPC64
8227 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8228 && !mask_operand (operands[2], DImode)
8229 && !mask64_operand (operands[2], DImode)"
8230 [(set (match_dup 0)
8231 (and:DI (rotate:DI (match_dup 1)
8232 (match_dup 4))
8233 (match_dup 5)))
8234 (set (match_dup 0)
8235 (and:DI (rotate:DI (match_dup 0)
8236 (match_dup 6))
8237 (match_dup 7)))]
8238 {
8239 build_mask64_2_operands (operands[2], &operands[4]);
8240 })
8242 (define_insn "*anddi3_internal2_mc"
8243 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8244 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8245 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8246 (const_int 0)))
8247 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
8248 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8249 "TARGET_64BIT && rs6000_gen_cell_microcode"
8250 "@
8251 and. %3,%1,%2
8252 rldic%B2. %3,%1,0,%S2
8253 rlwinm. %3,%1,0,%m2,%M2
8254 andi. %3,%1,%b2
8255 andis. %3,%1,%u2
8256 #
8257 #
8258 #
8259 #
8260 #
8261 #
8262 #"
8263 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8264 fast_compare,compare,compare,compare,compare,compare,\
8265 compare,compare")
8266 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8268 (define_split
8269 [(set (match_operand:CC 0 "cc_reg_operand" "")
8270 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8271 (match_operand:DI 2 "mask64_2_operand" ""))
8272 (const_int 0)))
8273 (clobber (match_scratch:DI 3 ""))
8274 (clobber (match_scratch:CC 4 ""))]
8275 "TARGET_64BIT && reload_completed
8276 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8277 && !mask_operand (operands[2], DImode)
8278 && !mask64_operand (operands[2], DImode)"
8279 [(set (match_dup 3)
8280 (and:DI (rotate:DI (match_dup 1)
8281 (match_dup 5))
8282 (match_dup 6)))
8283 (parallel [(set (match_dup 0)
8284 (compare:CC (and:DI (rotate:DI (match_dup 3)
8285 (match_dup 7))
8286 (match_dup 8))
8287 (const_int 0)))
8288 (clobber (match_dup 3))])]
8289 "
8290 {
8291 build_mask64_2_operands (operands[2], &operands[5]);
8292 }")
8294 (define_insn "*anddi3_internal3_mc"
8295 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
8296 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
8297 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
8298 (const_int 0)))
8299 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
8300 (and:DI (match_dup 1) (match_dup 2)))
8301 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
8302 "TARGET_64BIT && rs6000_gen_cell_microcode"
8303 "@
8304 and. %0,%1,%2
8305 rldic%B2. %0,%1,0,%S2
8306 rlwinm. %0,%1,0,%m2,%M2
8307 andi. %0,%1,%b2
8308 andis. %0,%1,%u2
8309 #
8310 #
8311 #
8312 #
8313 #
8314 #
8315 #"
8316 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
8317 fast_compare,compare,compare,compare,compare,compare,\
8318 compare,compare")
8319 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
8321 (define_split
8322 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8323 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8324 (match_operand:DI 2 "and64_2_operand" ""))
8325 (const_int 0)))
8326 (set (match_operand:DI 0 "gpc_reg_operand" "")
8327 (and:DI (match_dup 1) (match_dup 2)))
8328 (clobber (match_scratch:CC 4 ""))]
8329 "TARGET_64BIT && reload_completed"
8330 [(parallel [(set (match_dup 0)
8331 (and:DI (match_dup 1) (match_dup 2)))
8332 (clobber (match_dup 4))])
8333 (set (match_dup 3)
8334 (compare:CC (match_dup 0)
8335 (const_int 0)))]
8336 "")
8338 (define_split
8339 [(set (match_operand:CC 3 "cc_reg_operand" "")
8340 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
8341 (match_operand:DI 2 "mask64_2_operand" ""))
8342 (const_int 0)))
8343 (set (match_operand:DI 0 "gpc_reg_operand" "")
8344 (and:DI (match_dup 1) (match_dup 2)))
8345 (clobber (match_scratch:CC 4 ""))]
8346 "TARGET_64BIT && reload_completed
8347 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
8348 && !mask_operand (operands[2], DImode)
8349 && !mask64_operand (operands[2], DImode)"
8350 [(set (match_dup 0)
8351 (and:DI (rotate:DI (match_dup 1)
8352 (match_dup 5))
8353 (match_dup 6)))
8354 (parallel [(set (match_dup 3)
8355 (compare:CC (and:DI (rotate:DI (match_dup 0)
8356 (match_dup 7))
8357 (match_dup 8))
8358 (const_int 0)))
8359 (set (match_dup 0)
8360 (and:DI (rotate:DI (match_dup 0)
8361 (match_dup 7))
8362 (match_dup 8)))])]
8363 "
8364 {
8365 build_mask64_2_operands (operands[2], &operands[5]);
8366 }")
8368 (define_expand "iordi3"
8369 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8370 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
8371 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8372 "TARGET_POWERPC64"
8373 "
8374 {
8375 if (non_logical_cint_operand (operands[2], DImode))
8376 {
8377 HOST_WIDE_INT value;
8378 rtx tmp = ((!can_create_pseudo_p ()
8379 || rtx_equal_p (operands[0], operands[1]))
8380 ? operands[0] : gen_reg_rtx (DImode));
8382 if (GET_CODE (operands[2]) == CONST_INT)
8383 {
8384 value = INTVAL (operands[2]);
8385 emit_insn (gen_iordi3 (tmp, operands[1],
8386 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8387 }
8388 else
8389 {
8390 value = CONST_DOUBLE_LOW (operands[2]);
8391 emit_insn (gen_iordi3 (tmp, operands[1],
8392 immed_double_const (value
8393 & (~ (HOST_WIDE_INT) 0xffff),
8394 0, DImode)));
8395 }
8397 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8398 DONE;
8399 }
8400 }")
8402 (define_expand "xordi3"
8403 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8404 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
8405 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
8406 "TARGET_POWERPC64"
8407 "
8408 {
8409 if (non_logical_cint_operand (operands[2], DImode))
8410 {
8411 HOST_WIDE_INT value;
8412 rtx tmp = ((!can_create_pseudo_p ()
8413 || rtx_equal_p (operands[0], operands[1]))
8414 ? operands[0] : gen_reg_rtx (DImode));
8416 if (GET_CODE (operands[2]) == CONST_INT)
8417 {
8418 value = INTVAL (operands[2]);
8419 emit_insn (gen_xordi3 (tmp, operands[1],
8420 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
8421 }
8422 else
8423 {
8424 value = CONST_DOUBLE_LOW (operands[2]);
8425 emit_insn (gen_xordi3 (tmp, operands[1],
8426 immed_double_const (value
8427 & (~ (HOST_WIDE_INT) 0xffff),
8428 0, DImode)));
8429 }
8431 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
8432 DONE;
8433 }
8434 }")
8436 (define_insn "*booldi3_internal1"
8437 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
8438 (match_operator:DI 3 "boolean_or_operator"
8439 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
8440 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
8441 "TARGET_POWERPC64"
8442 "@
8443 %q3 %0,%1,%2
8444 %q3i %0,%1,%b2
8445 %q3is %0,%1,%u2")
8447 (define_insn "*booldi3_internal2"
8448 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8449 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8450 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8451 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8452 (const_int 0)))
8453 (clobber (match_scratch:DI 3 "=r,r"))]
8454 "TARGET_64BIT"
8455 "@
8456 %q4. %3,%1,%2
8457 #"
8458 [(set_attr "type" "fast_compare,compare")
8459 (set_attr "length" "4,8")])
8461 (define_split
8462 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8463 (compare:CC (match_operator:DI 4 "boolean_operator"
8464 [(match_operand:DI 1 "gpc_reg_operand" "")
8465 (match_operand:DI 2 "gpc_reg_operand" "")])
8466 (const_int 0)))
8467 (clobber (match_scratch:DI 3 ""))]
8468 "TARGET_POWERPC64 && reload_completed"
8469 [(set (match_dup 3) (match_dup 4))
8470 (set (match_dup 0)
8471 (compare:CC (match_dup 3)
8472 (const_int 0)))]
8473 "")
8475 (define_insn "*booldi3_internal3"
8476 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8477 (compare:CC (match_operator:DI 4 "boolean_or_operator"
8478 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
8479 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8480 (const_int 0)))
8481 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8482 (match_dup 4))]
8483 "TARGET_64BIT"
8484 "@
8485 %q4. %0,%1,%2
8486 #"
8487 [(set_attr "type" "fast_compare,compare")
8488 (set_attr "length" "4,8")])
8490 (define_split
8491 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8492 (compare:CC (match_operator:DI 4 "boolean_operator"
8493 [(match_operand:DI 1 "gpc_reg_operand" "")
8494 (match_operand:DI 2 "gpc_reg_operand" "")])
8495 (const_int 0)))
8496 (set (match_operand:DI 0 "gpc_reg_operand" "")
8497 (match_dup 4))]
8498 "TARGET_POWERPC64 && reload_completed"
8499 [(set (match_dup 0) (match_dup 4))
8500 (set (match_dup 3)
8501 (compare:CC (match_dup 0)
8502 (const_int 0)))]
8503 "")
8505 ;; Split a logical operation that we can't do in one insn into two insns,
8506 ;; each of which does one 16-bit part. This is used by combine.
8508 (define_split
8509 [(set (match_operand:DI 0 "gpc_reg_operand" "")
8510 (match_operator:DI 3 "boolean_or_operator"
8511 [(match_operand:DI 1 "gpc_reg_operand" "")
8512 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
8513 "TARGET_POWERPC64"
8514 [(set (match_dup 0) (match_dup 4))
8515 (set (match_dup 0) (match_dup 5))]
8516 "
8517 {
8518 rtx i3,i4;
8520 if (GET_CODE (operands[2]) == CONST_DOUBLE)
8521 {
8522 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
8523 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
8524 0, DImode);
8525 i4 = GEN_INT (value & 0xffff);
8526 }
8527 else
8528 {
8529 i3 = GEN_INT (INTVAL (operands[2])
8530 & (~ (HOST_WIDE_INT) 0xffff));
8531 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
8532 }
8533 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8534 operands[1], i3);
8535 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8536 operands[0], i4);
8537 }")
8539 (define_insn "*boolcdi3_internal1"
8540 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8541 (match_operator:DI 3 "boolean_operator"
8542 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8543 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
8544 "TARGET_POWERPC64"
8545 "%q3 %0,%2,%1")
8547 (define_insn "*boolcdi3_internal2"
8548 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8549 (compare:CC (match_operator:DI 4 "boolean_operator"
8550 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8551 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8552 (const_int 0)))
8553 (clobber (match_scratch:DI 3 "=r,r"))]
8554 "TARGET_64BIT"
8555 "@
8556 %q4. %3,%2,%1
8557 #"
8558 [(set_attr "type" "fast_compare,compare")
8559 (set_attr "length" "4,8")])
8561 (define_split
8562 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8563 (compare:CC (match_operator:DI 4 "boolean_operator"
8564 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8565 (match_operand:DI 2 "gpc_reg_operand" "")])
8566 (const_int 0)))
8567 (clobber (match_scratch:DI 3 ""))]
8568 "TARGET_POWERPC64 && reload_completed"
8569 [(set (match_dup 3) (match_dup 4))
8570 (set (match_dup 0)
8571 (compare:CC (match_dup 3)
8572 (const_int 0)))]
8573 "")
8575 (define_insn "*boolcdi3_internal3"
8576 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8577 (compare:CC (match_operator:DI 4 "boolean_operator"
8578 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8579 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8580 (const_int 0)))
8581 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8582 (match_dup 4))]
8583 "TARGET_64BIT"
8584 "@
8585 %q4. %0,%2,%1
8586 #"
8587 [(set_attr "type" "fast_compare,compare")
8588 (set_attr "length" "4,8")])
8590 (define_split
8591 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8592 (compare:CC (match_operator:DI 4 "boolean_operator"
8593 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8594 (match_operand:DI 2 "gpc_reg_operand" "")])
8595 (const_int 0)))
8596 (set (match_operand:DI 0 "gpc_reg_operand" "")
8597 (match_dup 4))]
8598 "TARGET_POWERPC64 && reload_completed"
8599 [(set (match_dup 0) (match_dup 4))
8600 (set (match_dup 3)
8601 (compare:CC (match_dup 0)
8602 (const_int 0)))]
8603 "")
8605 (define_insn "*boolccdi3_internal1"
8606 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8607 (match_operator:DI 3 "boolean_operator"
8608 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8609 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
8610 "TARGET_POWERPC64"
8611 "%q3 %0,%1,%2")
8613 (define_insn "*boolccdi3_internal2"
8614 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8615 (compare:CC (match_operator:DI 4 "boolean_operator"
8616 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8617 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8618 (const_int 0)))
8619 (clobber (match_scratch:DI 3 "=r,r"))]
8620 "TARGET_64BIT"
8621 "@
8622 %q4. %3,%1,%2
8623 #"
8624 [(set_attr "type" "fast_compare,compare")
8625 (set_attr "length" "4,8")])
8627 (define_split
8628 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8629 (compare:CC (match_operator:DI 4 "boolean_operator"
8630 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8631 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8632 (const_int 0)))
8633 (clobber (match_scratch:DI 3 ""))]
8634 "TARGET_POWERPC64 && reload_completed"
8635 [(set (match_dup 3) (match_dup 4))
8636 (set (match_dup 0)
8637 (compare:CC (match_dup 3)
8638 (const_int 0)))]
8639 "")
8641 (define_insn "*boolccdi3_internal3"
8642 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8643 (compare:CC (match_operator:DI 4 "boolean_operator"
8644 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8645 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8646 (const_int 0)))
8647 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8648 (match_dup 4))]
8649 "TARGET_64BIT"
8650 "@
8651 %q4. %0,%1,%2
8652 #"
8653 [(set_attr "type" "fast_compare,compare")
8654 (set_attr "length" "4,8")])
8656 (define_split
8657 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8658 (compare:CC (match_operator:DI 4 "boolean_operator"
8659 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8660 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8661 (const_int 0)))
8662 (set (match_operand:DI 0 "gpc_reg_operand" "")
8663 (match_dup 4))]
8664 "TARGET_POWERPC64 && reload_completed"
8665 [(set (match_dup 0) (match_dup 4))
8666 (set (match_dup 3)
8667 (compare:CC (match_dup 0)
8668 (const_int 0)))]
8669 "")
8671 (define_expand "smindi3"
8672 [(match_operand:DI 0 "gpc_reg_operand" "")
8673 (match_operand:DI 1 "gpc_reg_operand" "")
8674 (match_operand:DI 2 "gpc_reg_operand" "")]
8675 "TARGET_ISEL64"
8676 "
8677 {
8678 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
8679 DONE;
8680 }")
8682 (define_expand "smaxdi3"
8683 [(match_operand:DI 0 "gpc_reg_operand" "")
8684 (match_operand:DI 1 "gpc_reg_operand" "")
8685 (match_operand:DI 2 "gpc_reg_operand" "")]
8686 "TARGET_ISEL64"
8687 "
8688 {
8689 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
8690 DONE;
8691 }")
8693 (define_expand "umindi3"
8694 [(match_operand:DI 0 "gpc_reg_operand" "")
8695 (match_operand:DI 1 "gpc_reg_operand" "")
8696 (match_operand:DI 2 "gpc_reg_operand" "")]
8697 "TARGET_ISEL64"
8698 "
8699 {
8700 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
8701 DONE;
8702 }")
8704 (define_expand "umaxdi3"
8705 [(match_operand:DI 0 "gpc_reg_operand" "")
8706 (match_operand:DI 1 "gpc_reg_operand" "")
8707 (match_operand:DI 2 "gpc_reg_operand" "")]
8708 "TARGET_ISEL64"
8709 "
8710 {
8711 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
8712 DONE;
8713 }")
8715 \f
8716 ;; Now define ways of moving data around.
8718 ;; Set up a register with a value from the GOT table
8720 (define_expand "movsi_got"
8721 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8722 (unspec:SI [(match_operand:SI 1 "got_operand" "")
8723 (match_dup 2)] UNSPEC_MOVSI_GOT))]
8724 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8725 "
8726 {
8727 if (GET_CODE (operands[1]) == CONST)
8728 {
8729 rtx offset = const0_rtx;
8730 HOST_WIDE_INT value;
8732 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8733 value = INTVAL (offset);
8734 if (value != 0)
8735 {
8736 rtx tmp = (!can_create_pseudo_p ()
8737 ? operands[0]
8738 : gen_reg_rtx (Pmode));
8739 emit_insn (gen_movsi_got (tmp, operands[1]));
8740 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8741 DONE;
8742 }
8743 }
8745 operands[2] = rs6000_got_register (operands[1]);
8746 }")
8748 (define_insn "*movsi_got_internal"
8749 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8750 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8751 (match_operand:SI 2 "gpc_reg_operand" "b")]
8752 UNSPEC_MOVSI_GOT))]
8753 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8754 "{l|lwz} %0,%a1@got(%2)"
8755 [(set_attr "type" "load")])
8757 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8758 ;; didn't get allocated to a hard register.
8759 (define_split
8760 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8761 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8762 (match_operand:SI 2 "memory_operand" "")]
8763 UNSPEC_MOVSI_GOT))]
8764 "DEFAULT_ABI == ABI_V4
8765 && flag_pic == 1
8766 && (reload_in_progress || reload_completed)"
8767 [(set (match_dup 0) (match_dup 2))
8768 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8769 UNSPEC_MOVSI_GOT))]
8770 "")
8772 ;; For SI, we special-case integers that can't be loaded in one insn. We
8773 ;; do the load 16-bits at a time. We could do this by loading from memory,
8774 ;; and this is even supposed to be faster, but it is simpler not to get
8775 ;; integers in the TOC.
8776 (define_insn "movsi_low"
8777 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8778 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8779 (match_operand 2 "" ""))))]
8780 "TARGET_MACHO && ! TARGET_64BIT"
8781 "{l|lwz} %0,lo16(%2)(%1)"
8782 [(set_attr "type" "load")
8783 (set_attr "length" "4")])
8785 (define_insn "*movsi_internal1"
8786 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
8787 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
8788 "!TARGET_SINGLE_FPU &&
8789 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8790 "@
8791 mr %0,%1
8792 {cal|la} %0,%a1
8793 {l%U1%X1|lwz%U1%X1} %0,%1
8794 {st%U0%X0|stw%U0%X0} %1,%0
8795 {lil|li} %0,%1
8796 {liu|lis} %0,%v1
8797 #
8798 {cal|la} %0,%a1
8799 mf%1 %0
8800 mt%0 %1
8801 mt%0 %1
8802 mt%0 %1
8803 {cror 0,0,0|nop}"
8804 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*")
8805 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8807 (define_insn "*movsi_internal1_single"
8808 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h,m,*f")
8809 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0,f,m"))]
8810 "TARGET_SINGLE_FPU &&
8811 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8812 "@
8813 mr %0,%1
8814 {cal|la} %0,%a1
8815 {l%U1%X1|lwz%U1%X1} %0,%1
8816 {st%U0%X0|stw%U0%X0} %1,%0
8817 {lil|li} %0,%1
8818 {liu|lis} %0,%v1
8819 #
8820 {cal|la} %0,%a1
8821 mf%1 %0
8822 mt%0 %1
8823 mt%0 %1
8824 mt%0 %1
8825 {cror 0,0,0|nop}
8826 stfs%U0%X0 %1, %0
8827 lfs%U1%X1 %0, %1"
8828 [(set_attr "type" "*,*,load,store,*,*,*,*,mfjmpr,*,mtjmpr,*,*,*,*")
8829 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4,4,4")])
8831 ;; Split a load of a large constant into the appropriate two-insn
8832 ;; sequence.
8834 (define_split
8835 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8836 (match_operand:SI 1 "const_int_operand" ""))]
8837 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8838 && (INTVAL (operands[1]) & 0xffff) != 0"
8839 [(set (match_dup 0)
8840 (match_dup 2))
8841 (set (match_dup 0)
8842 (ior:SI (match_dup 0)
8843 (match_dup 3)))]
8844 "
8845 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8847 if (tem == operands[0])
8848 DONE;
8849 else
8850 FAIL;
8851 }")
8853 (define_insn "*mov<mode>_internal2"
8854 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8855 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8856 (const_int 0)))
8857 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8858 ""
8859 "@
8860 {cmpi|cmp<wd>i} %2,%0,0
8861 mr. %0,%1
8862 #"
8863 [(set_attr "type" "cmp,compare,cmp")
8864 (set_attr "length" "4,4,8")])
8866 (define_split
8867 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
8868 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8869 (const_int 0)))
8870 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8871 "reload_completed"
8872 [(set (match_dup 0) (match_dup 1))
8873 (set (match_dup 2)
8874 (compare:CC (match_dup 0)
8875 (const_int 0)))]
8876 "")
8877 \f
8878 (define_insn "*movhi_internal"
8879 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8880 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8881 "gpc_reg_operand (operands[0], HImode)
8882 || gpc_reg_operand (operands[1], HImode)"
8883 "@
8884 mr %0,%1
8885 lhz%U1%X1 %0,%1
8886 sth%U0%X0 %1,%0
8887 {lil|li} %0,%w1
8888 mf%1 %0
8889 mt%0 %1
8890 mt%0 %1
8891 {cror 0,0,0|nop}"
8892 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8894 (define_expand "mov<mode>"
8895 [(set (match_operand:INT 0 "general_operand" "")
8896 (match_operand:INT 1 "any_operand" ""))]
8897 ""
8898 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8900 (define_insn "*movqi_internal"
8901 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8902 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8903 "gpc_reg_operand (operands[0], QImode)
8904 || gpc_reg_operand (operands[1], QImode)"
8905 "@
8906 mr %0,%1
8907 lbz%U1%X1 %0,%1
8908 stb%U0%X0 %1,%0
8909 {lil|li} %0,%1
8910 mf%1 %0
8911 mt%0 %1
8912 mt%0 %1
8913 {cror 0,0,0|nop}"
8914 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8915 \f
8916 ;; Here is how to move condition codes around. When we store CC data in
8917 ;; an integer register or memory, we store just the high-order 4 bits.
8918 ;; This lets us not shift in the most common case of CR0.
8919 (define_expand "movcc"
8920 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8921 (match_operand:CC 1 "nonimmediate_operand" ""))]
8922 ""
8923 "")
8925 (define_insn "*movcc_internal1"
8926 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8927 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
8928 "register_operand (operands[0], CCmode)
8929 || register_operand (operands[1], CCmode)"
8930 "@
8931 mcrf %0,%1
8932 mtcrf 128,%1
8933 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
8934 crxor %0,%0,%0
8935 mfcr %0%Q1
8936 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
8937 mr %0,%1
8938 {lil|li} %0,%1
8939 mf%1 %0
8940 mt%0 %1
8941 mt%0 %1
8942 {l%U1%X1|lwz%U1%X1} %0,%1
8943 {st%U0%U1|stw%U0%U1} %1,%0"
8944 [(set (attr "type")
8945 (cond [(eq_attr "alternative" "0,3")
8946 (const_string "cr_logical")
8947 (eq_attr "alternative" "1,2")
8948 (const_string "mtcr")
8949 (eq_attr "alternative" "6,7,9")
8950 (const_string "integer")
8951 (eq_attr "alternative" "8")
8952 (const_string "mfjmpr")
8953 (eq_attr "alternative" "10")
8954 (const_string "mtjmpr")
8955 (eq_attr "alternative" "11")
8956 (const_string "load")
8957 (eq_attr "alternative" "12")
8958 (const_string "store")
8959 (ne (symbol_ref "TARGET_MFCRF") (const_int 0))
8960 (const_string "mfcrf")
8961 ]
8962 (const_string "mfcr")))
8963 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
8964 \f
8965 ;; For floating-point, we normally deal with the floating-point registers
8966 ;; unless -msoft-float is used. The sole exception is that parameter passing
8967 ;; can produce floating-point values in fixed-point registers. Unless the
8968 ;; value is a simple constant or already in memory, we deal with this by
8969 ;; allocating memory and copying the value explicitly via that memory location.
8970 (define_expand "movsf"
8971 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8972 (match_operand:SF 1 "any_operand" ""))]
8973 ""
8974 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
8976 (define_split
8977 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8978 (match_operand:SF 1 "const_double_operand" ""))]
8979 "reload_completed
8980 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8981 || (GET_CODE (operands[0]) == SUBREG
8982 && GET_CODE (SUBREG_REG (operands[0])) == REG
8983 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8984 [(set (match_dup 2) (match_dup 3))]
8985 "
8986 {
8987 long l;
8988 REAL_VALUE_TYPE rv;
8990 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8991 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
8993 if (! TARGET_POWERPC64)
8994 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8995 else
8996 operands[2] = gen_lowpart (SImode, operands[0]);
8998 operands[3] = gen_int_mode (l, SImode);
8999 }")
9001 (define_insn "*movsf_hardfloat"
9002 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
9003 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
9004 "(gpc_reg_operand (operands[0], SFmode)
9005 || gpc_reg_operand (operands[1], SFmode))
9006 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
9007 "@
9008 mr %0,%1
9009 {l%U1%X1|lwz%U1%X1} %0,%1
9010 {st%U0%X0|stw%U0%X0} %1,%0
9011 fmr %0,%1
9012 lfs%U1%X1 %0,%1
9013 stfs%U0%X0 %1,%0
9014 mt%0 %1
9015 mt%0 %1
9016 mf%1 %0
9017 {cror 0,0,0|nop}
9018 #
9019 #"
9020 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
9021 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
9023 (define_insn "*movsf_softfloat"
9024 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
9025 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn,0"))]
9026 "(gpc_reg_operand (operands[0], SFmode)
9027 || gpc_reg_operand (operands[1], SFmode))
9028 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
9029 "@
9030 mr %0,%1
9031 mt%0 %1
9032 mt%0 %1
9033 mf%1 %0
9034 {l%U1%X1|lwz%U1%X1} %0,%1
9035 {st%U0%X0|stw%U0%X0} %1,%0
9036 {lil|li} %0,%1
9037 {liu|lis} %0,%v1
9038 {cal|la} %0,%a1
9039 #
9040 #
9041 {cror 0,0,0|nop}"
9042 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
9043 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
9045 \f
9046 (define_expand "movdf"
9047 [(set (match_operand:DF 0 "nonimmediate_operand" "")
9048 (match_operand:DF 1 "any_operand" ""))]
9049 ""
9050 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
9052 (define_split
9053 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9054 (match_operand:DF 1 "const_int_operand" ""))]
9055 "! TARGET_POWERPC64 && reload_completed
9056 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9057 || (GET_CODE (operands[0]) == SUBREG
9058 && GET_CODE (SUBREG_REG (operands[0])) == REG
9059 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9060 [(set (match_dup 2) (match_dup 4))
9061 (set (match_dup 3) (match_dup 1))]
9062 "
9063 {
9064 int endian = (WORDS_BIG_ENDIAN == 0);
9065 HOST_WIDE_INT value = INTVAL (operands[1]);
9067 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9068 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9069 #if HOST_BITS_PER_WIDE_INT == 32
9070 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9071 #else
9072 operands[4] = GEN_INT (value >> 32);
9073 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9074 #endif
9075 }")
9077 (define_split
9078 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9079 (match_operand:DF 1 "const_double_operand" ""))]
9080 "! TARGET_POWERPC64 && reload_completed
9081 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9082 || (GET_CODE (operands[0]) == SUBREG
9083 && GET_CODE (SUBREG_REG (operands[0])) == REG
9084 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9085 [(set (match_dup 2) (match_dup 4))
9086 (set (match_dup 3) (match_dup 5))]
9087 "
9088 {
9089 int endian = (WORDS_BIG_ENDIAN == 0);
9090 long l[2];
9091 REAL_VALUE_TYPE rv;
9093 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9094 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9096 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
9097 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
9098 operands[4] = gen_int_mode (l[endian], SImode);
9099 operands[5] = gen_int_mode (l[1 - endian], SImode);
9100 }")
9102 (define_split
9103 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9104 (match_operand:DF 1 "const_double_operand" ""))]
9105 "TARGET_POWERPC64 && reload_completed
9106 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
9107 || (GET_CODE (operands[0]) == SUBREG
9108 && GET_CODE (SUBREG_REG (operands[0])) == REG
9109 && REGNO (SUBREG_REG (operands[0])) <= 31))"
9110 [(set (match_dup 2) (match_dup 3))]
9111 "
9112 {
9113 int endian = (WORDS_BIG_ENDIAN == 0);
9114 long l[2];
9115 REAL_VALUE_TYPE rv;
9116 #if HOST_BITS_PER_WIDE_INT >= 64
9117 HOST_WIDE_INT val;
9118 #endif
9120 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
9121 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
9123 operands[2] = gen_lowpart (DImode, operands[0]);
9124 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
9125 #if HOST_BITS_PER_WIDE_INT >= 64
9126 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
9127 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
9129 operands[3] = gen_int_mode (val, DImode);
9130 #else
9131 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
9132 #endif
9133 }")
9135 ;; Don't have reload use general registers to load a constant. First,
9136 ;; it might not work if the output operand is the equivalent of
9137 ;; a non-offsettable memref, but also it is less efficient than loading
9138 ;; the constant into an FP register, since it will probably be used there.
9139 ;; The "??" is a kludge until we can figure out a more reasonable way
9140 ;; of handling these non-offsettable values.
9141 (define_insn "*movdf_hardfloat32"
9142 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,!r,!r,!r")
9143 (match_operand:DF 1 "input_operand" "r,m,r,ws,wa,Z,Z,ws,wa,d,m,d,j,G,H,F"))]
9144 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9145 && (gpc_reg_operand (operands[0], DFmode)
9146 || gpc_reg_operand (operands[1], DFmode))"
9147 "*
9148 {
9149 switch (which_alternative)
9150 {
9151 default:
9152 gcc_unreachable ();
9153 case 0:
9154 case 1:
9155 case 2:
9156 return \"#\";
9157 case 3:
9158 case 4:
9159 return \"xxlor %x0,%x1,%x1\";
9160 case 5:
9161 case 6:
9162 return \"lxsd%U1x %x0,%y1\";
9163 case 7:
9164 case 8:
9165 return \"stxsd%U0x %x1,%y0\";
9166 case 9:
9167 return \"fmr %0,%1\";
9168 case 10:
9169 return \"lfd%U1%X1 %0,%1\";
9170 case 11:
9171 return \"stfd%U0%X0 %1,%0\";
9172 case 12:
9173 return \"xxlxor %x0,%x0,%x0\";
9174 case 13:
9175 case 14:
9176 case 15:
9177 return \"#\";
9178 }
9179 }"
9180 [(set_attr "type" "two,load,store,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,*,*,*")
9181 (set_attr "length" "8,16,16,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9183 (define_insn "*movdf_softfloat32"
9184 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
9185 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
9186 "! TARGET_POWERPC64
9187 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
9188 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
9189 && (gpc_reg_operand (operands[0], DFmode)
9190 || gpc_reg_operand (operands[1], DFmode))"
9191 "#"
9192 [(set_attr "type" "two,load,store,*,*,*")
9193 (set_attr "length" "8,8,8,8,12,16")])
9195 ; ld/std require word-aligned displacements -> 'Y' constraint.
9196 ; List Y->r and r->Y before r->r for reload.
9197 (define_insn "*movdf_hardfloat64_mfpgpr"
9198 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r,r,d")
9199 (match_operand:DF 1 "input_operand" "r,Y,r,ws,?wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F,d,r"))]
9200 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9201 && TARGET_DOUBLE_FLOAT
9202 && (gpc_reg_operand (operands[0], DFmode)
9203 || gpc_reg_operand (operands[1], DFmode))"
9204 "@
9205 std%U0%X0 %1,%0
9206 ld%U1%X1 %0,%1
9207 mr %0,%1
9208 xxlor %x0,%x1,%x1
9209 xxlor %x0,%x1,%x1
9210 lxsd%U1x %x0,%y1
9211 lxsd%U1x %x0,%y1
9212 stxsd%U0x %x1,%y0
9213 stxsd%U0x %x1,%y0
9214 fmr %0,%1
9215 lfd%U1%X1 %0,%1
9216 stfd%U0%X0 %1,%0
9217 xxlxor %x0,%x0,%x0
9218 mt%0 %1
9219 mf%1 %0
9220 {cror 0,0,0|nop}
9221 #
9222 #
9223 #
9224 mftgpr %0,%1
9225 mffgpr %0,%1"
9226 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
9227 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
9229 ; ld/std require word-aligned displacements -> 'Y' constraint.
9230 ; List Y->r and r->Y before r->r for reload.
9231 (define_insn "*movdf_hardfloat64"
9232 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,d,d,m,wa,*c*l,!r,*h,!r,!r,!r")
9233 (match_operand:DF 1 "input_operand" "r,Y,r,ws,wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F"))]
9234 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9235 && TARGET_DOUBLE_FLOAT
9236 && (gpc_reg_operand (operands[0], DFmode)
9237 || gpc_reg_operand (operands[1], DFmode))"
9238 "@
9239 std%U0%X0 %1,%0
9240 ld%U1%X1 %0,%1
9241 mr %0,%1
9242 xxlor %x0,%x1,%x1
9243 xxlor %x0,%x1,%x1
9244 lxsd%U1x %x0,%y1
9245 lxsd%U1x %x0,%y1
9246 stxsd%U0x %x1,%y0
9247 stxsd%U0x %x1,%y0
9248 fmr %0,%1
9249 lfd%U1%X1 %0,%1
9250 stfd%U0%X0 %1,%0
9251 xxlxor %x0,%x0,%x0
9252 mt%0 %1
9253 mf%1 %0
9254 {cror 0,0,0|nop}
9255 #
9256 #
9257 #"
9258 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fp,fpload,fpstore,vecsimple,mtjmpr,mfjmpr,*,*,*,*")
9259 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16")])
9261 (define_insn "*movdf_softfloat64"
9262 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
9263 (match_operand:DF 1 "input_operand" "Y,r,r,r,h,G,H,F,0"))]
9264 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
9265 && (gpc_reg_operand (operands[0], DFmode)
9266 || gpc_reg_operand (operands[1], DFmode))"
9267 "@
9268 ld%U1%X1 %0,%1
9269 std%U0%X0 %1,%0
9270 mr %0,%1
9271 mt%0 %1
9272 mf%1 %0
9273 #
9274 #
9275 #
9276 {cror 0,0,0|nop}"
9277 [(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
9278 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
9279 \f
9280 (define_expand "movtf"
9281 [(set (match_operand:TF 0 "general_operand" "")
9282 (match_operand:TF 1 "any_operand" ""))]
9283 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
9284 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
9286 ; It's important to list the o->f and f->o moves before f->f because
9287 ; otherwise reload, given m->f, will try to pick f->f and reload it,
9288 ; which doesn't make progress. Likewise r->Y must be before r->r.
9289 (define_insn_and_split "*movtf_internal"
9290 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,d,r,Y,r")
9291 (match_operand:TF 1 "input_operand" "d,o,d,YGHF,r,r"))]
9292 "!TARGET_IEEEQUAD
9293 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
9294 && (gpc_reg_operand (operands[0], TFmode)
9295 || gpc_reg_operand (operands[1], TFmode))"
9296 "#"
9297 "&& reload_completed"
9298 [(pc)]
9299 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9300 [(set_attr "length" "8,8,8,20,20,16")])
9302 (define_insn_and_split "*movtf_softfloat"
9303 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=r,Y,r")
9304 (match_operand:TF 1 "input_operand" "YGHF,r,r"))]
9305 "!TARGET_IEEEQUAD
9306 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
9307 && (gpc_reg_operand (operands[0], TFmode)
9308 || gpc_reg_operand (operands[1], TFmode))"
9309 "#"
9310 "&& reload_completed"
9311 [(pc)]
9312 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
9313 [(set_attr "length" "20,20,16")])
9315 (define_expand "extenddftf2"
9316 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9317 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
9318 "!TARGET_IEEEQUAD
9319 && TARGET_HARD_FLOAT
9320 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9321 && TARGET_LONG_DOUBLE_128"
9322 {
9323 if (TARGET_E500_DOUBLE)
9324 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
9325 else
9326 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
9327 DONE;
9328 })
9330 (define_expand "extenddftf2_fprs"
9331 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
9332 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
9333 (use (match_dup 2))])]
9334 "!TARGET_IEEEQUAD
9335 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9336 && TARGET_LONG_DOUBLE_128"
9337 {
9338 operands[2] = CONST0_RTX (DFmode);
9339 /* Generate GOT reference early for SVR4 PIC. */
9340 if (DEFAULT_ABI == ABI_V4 && flag_pic)
9341 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
9342 })
9344 (define_insn_and_split "*extenddftf2_internal"
9345 [(set (match_operand:TF 0 "nonimmediate_operand" "=o,d,&d,r")
9346 (float_extend:TF (match_operand:DF 1 "input_operand" "dr,md,md,rmGHF")))
9347 (use (match_operand:DF 2 "zero_reg_mem_operand" "rd,m,d,n"))]
9348 "!TARGET_IEEEQUAD
9349 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9350 && TARGET_LONG_DOUBLE_128"
9351 "#"
9352 "&& reload_completed"
9353 [(pc)]
9354 {
9355 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9356 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9357 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
9358 operands[1]);
9359 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
9360 operands[2]);
9361 DONE;
9362 })
9364 (define_expand "extendsftf2"
9365 [(set (match_operand:TF 0 "nonimmediate_operand" "")
9366 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
9367 "!TARGET_IEEEQUAD
9368 && TARGET_HARD_FLOAT
9369 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9370 && TARGET_LONG_DOUBLE_128"
9371 {
9372 rtx tmp = gen_reg_rtx (DFmode);
9373 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
9374 emit_insn (gen_extenddftf2 (operands[0], tmp));
9375 DONE;
9376 })
9378 (define_expand "trunctfdf2"
9379 [(set (match_operand:DF 0 "gpc_reg_operand" "")
9380 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
9381 "!TARGET_IEEEQUAD
9382 && TARGET_HARD_FLOAT
9383 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9384 && TARGET_LONG_DOUBLE_128"
9385 "")
9387 (define_insn_and_split "trunctfdf2_internal1"
9388 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
9389 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
9390 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
9391 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9392 "@
9393 #
9394 fmr %0,%1"
9395 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
9396 [(const_int 0)]
9397 {
9398 emit_note (NOTE_INSN_DELETED);
9399 DONE;
9400 }
9401 [(set_attr "type" "fp")])
9403 (define_insn "trunctfdf2_internal2"
9404 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9405 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9406 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
9407 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9408 && TARGET_LONG_DOUBLE_128"
9409 "fadd %0,%1,%L1"
9410 [(set_attr "type" "fp")
9411 (set_attr "fp_type" "fp_addsub_d")])
9413 (define_expand "trunctfsf2"
9414 [(set (match_operand:SF 0 "gpc_reg_operand" "")
9415 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
9416 "!TARGET_IEEEQUAD
9417 && TARGET_HARD_FLOAT
9418 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9419 && TARGET_LONG_DOUBLE_128"
9420 {
9421 if (TARGET_E500_DOUBLE)
9422 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
9423 else
9424 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
9425 DONE;
9426 })
9428 (define_insn_and_split "trunctfsf2_fprs"
9429 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
9430 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
9431 (clobber (match_scratch:DF 2 "=d"))]
9432 "!TARGET_IEEEQUAD
9433 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
9434 && TARGET_LONG_DOUBLE_128"
9435 "#"
9436 "&& reload_completed"
9437 [(set (match_dup 2)
9438 (float_truncate:DF (match_dup 1)))
9439 (set (match_dup 0)
9440 (float_truncate:SF (match_dup 2)))]
9441 "")
9443 (define_expand "floatsitf2"
9444 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9445 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
9446 "!TARGET_IEEEQUAD
9447 && TARGET_HARD_FLOAT
9448 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9449 && TARGET_LONG_DOUBLE_128"
9450 {
9451 rtx tmp = gen_reg_rtx (DFmode);
9452 expand_float (tmp, operands[1], false);
9453 emit_insn (gen_extenddftf2 (operands[0], tmp));
9454 DONE;
9455 })
9457 ; fadd, but rounding towards zero.
9458 ; This is probably not the optimal code sequence.
9459 (define_insn "fix_trunc_helper"
9460 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
9461 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
9462 UNSPEC_FIX_TRUNC_TF))
9463 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
9464 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
9465 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
9466 [(set_attr "type" "fp")
9467 (set_attr "length" "20")])
9469 (define_expand "fix_trunctfsi2"
9470 [(set (match_operand:SI 0 "gpc_reg_operand" "")
9471 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
9472 "!TARGET_IEEEQUAD
9473 && (TARGET_POWER2 || TARGET_POWERPC)
9474 && TARGET_HARD_FLOAT
9475 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9476 && TARGET_LONG_DOUBLE_128"
9477 {
9478 if (TARGET_E500_DOUBLE)
9479 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
9480 else
9481 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
9482 DONE;
9483 })
9485 (define_expand "fix_trunctfsi2_fprs"
9486 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
9487 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
9488 (clobber (match_dup 2))
9489 (clobber (match_dup 3))
9490 (clobber (match_dup 4))
9491 (clobber (match_dup 5))])]
9492 "!TARGET_IEEEQUAD
9493 && (TARGET_POWER2 || TARGET_POWERPC)
9494 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9495 {
9496 operands[2] = gen_reg_rtx (DFmode);
9497 operands[3] = gen_reg_rtx (DFmode);
9498 operands[4] = gen_reg_rtx (DImode);
9499 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
9500 })
9502 (define_insn_and_split "*fix_trunctfsi2_internal"
9503 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9504 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
9505 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
9506 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
9507 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
9508 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
9509 "!TARGET_IEEEQUAD
9510 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9511 "#"
9512 ""
9513 [(pc)]
9514 {
9515 rtx lowword;
9516 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
9518 gcc_assert (MEM_P (operands[5]));
9519 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
9521 emit_insn (gen_fctiwz (operands[4], operands[2]));
9522 emit_move_insn (operands[5], operands[4]);
9523 emit_move_insn (operands[0], lowword);
9524 DONE;
9525 })
9527 (define_expand "negtf2"
9528 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9529 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9530 "!TARGET_IEEEQUAD
9531 && TARGET_HARD_FLOAT
9532 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9533 && TARGET_LONG_DOUBLE_128"
9534 "")
9536 (define_insn "negtf2_internal"
9537 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
9538 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9539 "!TARGET_IEEEQUAD
9540 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9541 "*
9542 {
9543 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9544 return \"fneg %L0,%L1\;fneg %0,%1\";
9545 else
9546 return \"fneg %0,%1\;fneg %L0,%L1\";
9547 }"
9548 [(set_attr "type" "fp")
9549 (set_attr "length" "8")])
9551 (define_expand "abstf2"
9552 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9553 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9554 "!TARGET_IEEEQUAD
9555 && TARGET_HARD_FLOAT
9556 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9557 && TARGET_LONG_DOUBLE_128"
9558 "
9559 {
9560 rtx label = gen_label_rtx ();
9561 if (TARGET_E500_DOUBLE)
9562 {
9563 if (flag_finite_math_only && !flag_trapping_math)
9564 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
9565 else
9566 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
9567 }
9568 else
9569 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
9570 emit_label (label);
9571 DONE;
9572 }")
9574 (define_expand "abstf2_internal"
9575 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9576 (match_operand:TF 1 "gpc_reg_operand" ""))
9577 (set (match_dup 3) (match_dup 5))
9578 (set (match_dup 5) (abs:DF (match_dup 5)))
9579 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
9580 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
9581 (label_ref (match_operand 2 "" ""))
9582 (pc)))
9583 (set (match_dup 6) (neg:DF (match_dup 6)))]
9584 "!TARGET_IEEEQUAD
9585 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9586 && TARGET_LONG_DOUBLE_128"
9587 "
9588 {
9589 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9590 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9591 operands[3] = gen_reg_rtx (DFmode);
9592 operands[4] = gen_reg_rtx (CCFPmode);
9593 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
9594 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
9595 }")
9596 \f
9597 ;; Next come the multi-word integer load and store and the load and store
9598 ;; multiple insns.
9600 ; List r->r after r->"o<>", otherwise reload will try to reload a
9601 ; non-offsettable address by using r->r which won't make progress.
9602 (define_insn "*movdi_internal32"
9603 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=o<>,r,r,*d,*d,m,r")
9604 (match_operand:DI 1 "input_operand" "r,r,m,d,m,d,IJKnGHF"))]
9605 "! TARGET_POWERPC64
9606 && (gpc_reg_operand (operands[0], DImode)
9607 || gpc_reg_operand (operands[1], DImode))"
9608 "@
9609 #
9610 #
9611 #
9612 fmr %0,%1
9613 lfd%U1%X1 %0,%1
9614 stfd%U0%X0 %1,%0
9615 #"
9616 [(set_attr "type" "load,*,store,fp,fpload,fpstore,*")])
9618 (define_split
9619 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9620 (match_operand:DI 1 "const_int_operand" ""))]
9621 "! TARGET_POWERPC64 && reload_completed"
9622 [(set (match_dup 2) (match_dup 4))
9623 (set (match_dup 3) (match_dup 1))]
9624 "
9625 {
9626 HOST_WIDE_INT value = INTVAL (operands[1]);
9627 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9628 DImode);
9629 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9630 DImode);
9631 #if HOST_BITS_PER_WIDE_INT == 32
9632 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9633 #else
9634 operands[4] = GEN_INT (value >> 32);
9635 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9636 #endif
9637 }")
9639 (define_split
9640 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
9641 (match_operand:DIFD 1 "input_operand" ""))]
9642 "reload_completed && !TARGET_POWERPC64
9643 && gpr_or_gpr_p (operands[0], operands[1])"
9644 [(pc)]
9645 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9647 (define_insn "*movdi_mfpgpr"
9648 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h,r,*d")
9649 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0,*d,r"))]
9650 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9651 && (gpc_reg_operand (operands[0], DImode)
9652 || gpc_reg_operand (operands[1], DImode))"
9653 "@
9654 mr %0,%1
9655 ld%U1%X1 %0,%1
9656 std%U0%X0 %1,%0
9657 li %0,%1
9658 lis %0,%v1
9659 #
9660 {cal|la} %0,%a1
9661 fmr %0,%1
9662 lfd%U1%X1 %0,%1
9663 stfd%U0%X0 %1,%0
9664 mf%1 %0
9665 mt%0 %1
9666 {cror 0,0,0|nop}
9667 mftgpr %0,%1
9668 mffgpr %0,%1"
9669 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
9670 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4")])
9672 (define_insn "*movdi_internal64"
9673 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,*d,*d,m,r,*h,*h")
9674 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,d,m,d,*h,r,0"))]
9675 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
9676 && (gpc_reg_operand (operands[0], DImode)
9677 || gpc_reg_operand (operands[1], DImode))"
9678 "@
9679 mr %0,%1
9680 ld%U1%X1 %0,%1
9681 std%U0%X0 %1,%0
9682 li %0,%1
9683 lis %0,%v1
9684 #
9685 {cal|la} %0,%a1
9686 fmr %0,%1
9687 lfd%U1%X1 %0,%1
9688 stfd%U0%X0 %1,%0
9689 mf%1 %0
9690 mt%0 %1
9691 {cror 0,0,0|nop}"
9692 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
9693 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
9695 ;; immediate value valid for a single instruction hiding in a const_double
9696 (define_insn ""
9697 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9698 (match_operand:DI 1 "const_double_operand" "F"))]
9699 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9700 && GET_CODE (operands[1]) == CONST_DOUBLE
9701 && num_insns_constant (operands[1], DImode) == 1"
9702 "*
9703 {
9704 return ((unsigned HOST_WIDE_INT)
9705 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9706 ? \"li %0,%1\" : \"lis %0,%v1\";
9707 }")
9709 ;; Generate all one-bits and clear left or right.
9710 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9711 (define_split
9712 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9713 (match_operand:DI 1 "mask64_operand" ""))]
9714 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9715 [(set (match_dup 0) (const_int -1))
9716 (set (match_dup 0)
9717 (and:DI (rotate:DI (match_dup 0)
9718 (const_int 0))
9719 (match_dup 1)))]
9720 "")
9722 ;; Split a load of a large constant into the appropriate five-instruction
9723 ;; sequence. Handle anything in a constant number of insns.
9724 ;; When non-easy constants can go in the TOC, this should use
9725 ;; easy_fp_constant predicate.
9726 (define_split
9727 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9728 (match_operand:DI 1 "const_int_operand" ""))]
9729 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9730 [(set (match_dup 0) (match_dup 2))
9731 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9732 "
9733 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9735 if (tem == operands[0])
9736 DONE;
9737 else
9738 FAIL;
9739 }")
9741 (define_split
9742 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9743 (match_operand:DI 1 "const_double_operand" ""))]
9744 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9745 [(set (match_dup 0) (match_dup 2))
9746 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9747 "
9748 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9750 if (tem == operands[0])
9751 DONE;
9752 else
9753 FAIL;
9754 }")
9755 \f
9756 ;; TImode is similar, except that we usually want to compute the address into
9757 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
9758 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
9760 ;; We say that MQ is clobbered in the last alternative because the first
9761 ;; alternative would never get used otherwise since it would need a reload
9762 ;; while the 2nd alternative would not. We put memory cases first so they
9763 ;; are preferred. Otherwise, we'd try to reload the output instead of
9764 ;; giving the SCRATCH mq.
9766 (define_insn "*movti_power"
9767 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r,r")
9768 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))
9769 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X,X"))]
9770 "TARGET_POWER && ! TARGET_POWERPC64
9771 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9772 "*
9773 {
9774 switch (which_alternative)
9775 {
9776 default:
9777 gcc_unreachable ();
9779 case 0:
9780 if (TARGET_STRING)
9781 return \"{stsi|stswi} %1,%P0,16\";
9782 case 1:
9783 case 2:
9784 return \"#\";
9785 case 3:
9786 /* If the address is not used in the output, we can use lsi. Otherwise,
9787 fall through to generating four loads. */
9788 if (TARGET_STRING
9789 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9790 return \"{lsi|lswi} %0,%P1,16\";
9791 /* ... fall through ... */
9792 case 4:
9793 case 5:
9794 return \"#\";
9795 }
9796 }"
9797 [(set_attr "type" "store,store,*,load,load,*")])
9799 (define_insn "*movti_string"
9800 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,o<>,????r,????r,????r,r")
9801 (match_operand:TI 1 "input_operand" "r,r,r,Q,m,n"))]
9802 "! TARGET_POWER && ! TARGET_POWERPC64
9803 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9804 "*
9805 {
9806 switch (which_alternative)
9807 {
9808 default:
9809 gcc_unreachable ();
9810 case 0:
9811 if (TARGET_STRING)
9812 return \"{stsi|stswi} %1,%P0,16\";
9813 case 1:
9814 case 2:
9815 return \"#\";
9816 case 3:
9817 /* If the address is not used in the output, we can use lsi. Otherwise,
9818 fall through to generating four loads. */
9819 if (TARGET_STRING
9820 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9821 return \"{lsi|lswi} %0,%P1,16\";
9822 /* ... fall through ... */
9823 case 4:
9824 case 5:
9825 return \"#\";
9826 }
9827 }"
9828 [(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")
9829 (set (attr "cell_micro") (if_then_else (eq (symbol_ref "TARGET_STRING") (const_int 1))
9830 (const_string "always")
9831 (const_string "conditional")))])
9833 (define_insn "*movti_ppc64"
9834 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
9835 (match_operand:TI 1 "input_operand" "r,r,m"))]
9836 "(TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9837 || gpc_reg_operand (operands[1], TImode)))
9838 && VECTOR_MEM_NONE_P (TImode)"
9839 "#"
9840 [(set_attr "type" "*,store,load")])
9842 (define_split
9843 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9844 (match_operand:TI 1 "const_double_operand" ""))]
9845 "TARGET_POWERPC64 && VECTOR_MEM_NONE_P (TImode)"
9846 [(set (match_dup 2) (match_dup 4))
9847 (set (match_dup 3) (match_dup 5))]
9848 "
9849 {
9850 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9851 TImode);
9852 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9853 TImode);
9854 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9855 {
9856 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9857 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9858 }
9859 else if (GET_CODE (operands[1]) == CONST_INT)
9860 {
9861 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9862 operands[5] = operands[1];
9863 }
9864 else
9865 FAIL;
9866 }")
9868 (define_split
9869 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9870 (match_operand:TI 1 "input_operand" ""))]
9871 "reload_completed && VECTOR_MEM_NONE_P (TImode)
9872 && gpr_or_gpr_p (operands[0], operands[1])"
9873 [(pc)]
9874 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9875 \f
9876 (define_expand "load_multiple"
9877 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9878 (match_operand:SI 1 "" ""))
9879 (use (match_operand:SI 2 "" ""))])]
9880 "TARGET_STRING && !TARGET_POWERPC64"
9881 "
9882 {
9883 int regno;
9884 int count;
9885 rtx op1;
9886 int i;
9888 /* Support only loading a constant number of fixed-point registers from
9889 memory and only bother with this if more than two; the machine
9890 doesn't support more than eight. */
9891 if (GET_CODE (operands[2]) != CONST_INT
9892 || INTVAL (operands[2]) <= 2
9893 || INTVAL (operands[2]) > 8
9894 || GET_CODE (operands[1]) != MEM
9895 || GET_CODE (operands[0]) != REG
9896 || REGNO (operands[0]) >= 32)
9897 FAIL;
9899 count = INTVAL (operands[2]);
9900 regno = REGNO (operands[0]);
9902 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9903 op1 = replace_equiv_address (operands[1],
9904 force_reg (SImode, XEXP (operands[1], 0)));
9906 for (i = 0; i < count; i++)
9907 XVECEXP (operands[3], 0, i)
9908 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9909 adjust_address_nv (op1, SImode, i * 4));
9910 }")
9912 (define_insn "*ldmsi8"
9913 [(match_parallel 0 "load_multiple_operation"
9914 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9915 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9916 (set (match_operand:SI 3 "gpc_reg_operand" "")
9917 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9918 (set (match_operand:SI 4 "gpc_reg_operand" "")
9919 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9920 (set (match_operand:SI 5 "gpc_reg_operand" "")
9921 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9922 (set (match_operand:SI 6 "gpc_reg_operand" "")
9923 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9924 (set (match_operand:SI 7 "gpc_reg_operand" "")
9925 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9926 (set (match_operand:SI 8 "gpc_reg_operand" "")
9927 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9928 (set (match_operand:SI 9 "gpc_reg_operand" "")
9929 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9930 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9931 "*
9932 { return rs6000_output_load_multiple (operands); }"
9933 [(set_attr "type" "load_ux")
9934 (set_attr "length" "32")])
9936 (define_insn "*ldmsi7"
9937 [(match_parallel 0 "load_multiple_operation"
9938 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9939 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9940 (set (match_operand:SI 3 "gpc_reg_operand" "")
9941 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9942 (set (match_operand:SI 4 "gpc_reg_operand" "")
9943 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9944 (set (match_operand:SI 5 "gpc_reg_operand" "")
9945 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9946 (set (match_operand:SI 6 "gpc_reg_operand" "")
9947 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9948 (set (match_operand:SI 7 "gpc_reg_operand" "")
9949 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9950 (set (match_operand:SI 8 "gpc_reg_operand" "")
9951 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9952 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9953 "*
9954 { return rs6000_output_load_multiple (operands); }"
9955 [(set_attr "type" "load_ux")
9956 (set_attr "length" "32")])
9958 (define_insn "*ldmsi6"
9959 [(match_parallel 0 "load_multiple_operation"
9960 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9961 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9962 (set (match_operand:SI 3 "gpc_reg_operand" "")
9963 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9964 (set (match_operand:SI 4 "gpc_reg_operand" "")
9965 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9966 (set (match_operand:SI 5 "gpc_reg_operand" "")
9967 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9968 (set (match_operand:SI 6 "gpc_reg_operand" "")
9969 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9970 (set (match_operand:SI 7 "gpc_reg_operand" "")
9971 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9972 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9973 "*
9974 { return rs6000_output_load_multiple (operands); }"
9975 [(set_attr "type" "load_ux")
9976 (set_attr "length" "32")])
9978 (define_insn "*ldmsi5"
9979 [(match_parallel 0 "load_multiple_operation"
9980 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9981 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9982 (set (match_operand:SI 3 "gpc_reg_operand" "")
9983 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9984 (set (match_operand:SI 4 "gpc_reg_operand" "")
9985 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9986 (set (match_operand:SI 5 "gpc_reg_operand" "")
9987 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9988 (set (match_operand:SI 6 "gpc_reg_operand" "")
9989 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9990 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9991 "*
9992 { return rs6000_output_load_multiple (operands); }"
9993 [(set_attr "type" "load_ux")
9994 (set_attr "length" "32")])
9996 (define_insn "*ldmsi4"
9997 [(match_parallel 0 "load_multiple_operation"
9998 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9999 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10000 (set (match_operand:SI 3 "gpc_reg_operand" "")
10001 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10002 (set (match_operand:SI 4 "gpc_reg_operand" "")
10003 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
10004 (set (match_operand:SI 5 "gpc_reg_operand" "")
10005 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
10006 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
10007 "*
10008 { return rs6000_output_load_multiple (operands); }"
10009 [(set_attr "type" "load_ux")
10010 (set_attr "length" "32")])
10012 (define_insn "*ldmsi3"
10013 [(match_parallel 0 "load_multiple_operation"
10014 [(set (match_operand:SI 2 "gpc_reg_operand" "")
10015 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
10016 (set (match_operand:SI 3 "gpc_reg_operand" "")
10017 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
10018 (set (match_operand:SI 4 "gpc_reg_operand" "")
10019 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
10020 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
10021 "*
10022 { return rs6000_output_load_multiple (operands); }"
10023 [(set_attr "type" "load_ux")
10024 (set_attr "length" "32")])
10026 (define_expand "store_multiple"
10027 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
10028 (match_operand:SI 1 "" ""))
10029 (clobber (scratch:SI))
10030 (use (match_operand:SI 2 "" ""))])]
10031 "TARGET_STRING && !TARGET_POWERPC64"
10032 "
10033 {
10034 int regno;
10035 int count;
10036 rtx to;
10037 rtx op0;
10038 int i;
10040 /* Support only storing a constant number of fixed-point registers to
10041 memory and only bother with this if more than two; the machine
10042 doesn't support more than eight. */
10043 if (GET_CODE (operands[2]) != CONST_INT
10044 || INTVAL (operands[2]) <= 2
10045 || INTVAL (operands[2]) > 8
10046 || GET_CODE (operands[0]) != MEM
10047 || GET_CODE (operands[1]) != REG
10048 || REGNO (operands[1]) >= 32)
10049 FAIL;
10051 count = INTVAL (operands[2]);
10052 regno = REGNO (operands[1]);
10054 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
10055 to = force_reg (SImode, XEXP (operands[0], 0));
10056 op0 = replace_equiv_address (operands[0], to);
10058 XVECEXP (operands[3], 0, 0)
10059 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
10060 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
10061 gen_rtx_SCRATCH (SImode));
10063 for (i = 1; i < count; i++)
10064 XVECEXP (operands[3], 0, i + 1)
10065 = gen_rtx_SET (VOIDmode,
10066 adjust_address_nv (op0, SImode, i * 4),
10067 gen_rtx_REG (SImode, regno + i));
10068 }")
10070 (define_insn "*stmsi8"
10071 [(match_parallel 0 "store_multiple_operation"
10072 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10073 (match_operand:SI 2 "gpc_reg_operand" "r"))
10074 (clobber (match_scratch:SI 3 "=X"))
10075 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10076 (match_operand:SI 4 "gpc_reg_operand" "r"))
10077 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10078 (match_operand:SI 5 "gpc_reg_operand" "r"))
10079 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10080 (match_operand:SI 6 "gpc_reg_operand" "r"))
10081 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10082 (match_operand:SI 7 "gpc_reg_operand" "r"))
10083 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10084 (match_operand:SI 8 "gpc_reg_operand" "r"))
10085 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10086 (match_operand:SI 9 "gpc_reg_operand" "r"))
10087 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10088 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10089 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10090 "{stsi|stswi} %2,%1,%O0"
10091 [(set_attr "type" "store_ux")
10092 (set_attr "cell_micro" "always")])
10094 (define_insn "*stmsi7"
10095 [(match_parallel 0 "store_multiple_operation"
10096 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10097 (match_operand:SI 2 "gpc_reg_operand" "r"))
10098 (clobber (match_scratch:SI 3 "=X"))
10099 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10100 (match_operand:SI 4 "gpc_reg_operand" "r"))
10101 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10102 (match_operand:SI 5 "gpc_reg_operand" "r"))
10103 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10104 (match_operand:SI 6 "gpc_reg_operand" "r"))
10105 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10106 (match_operand:SI 7 "gpc_reg_operand" "r"))
10107 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10108 (match_operand:SI 8 "gpc_reg_operand" "r"))
10109 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10110 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10111 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10112 "{stsi|stswi} %2,%1,%O0"
10113 [(set_attr "type" "store_ux")
10114 (set_attr "cell_micro" "always")])
10116 (define_insn "*stmsi6"
10117 [(match_parallel 0 "store_multiple_operation"
10118 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10119 (match_operand:SI 2 "gpc_reg_operand" "r"))
10120 (clobber (match_scratch:SI 3 "=X"))
10121 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10122 (match_operand:SI 4 "gpc_reg_operand" "r"))
10123 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10124 (match_operand:SI 5 "gpc_reg_operand" "r"))
10125 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10126 (match_operand:SI 6 "gpc_reg_operand" "r"))
10127 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10128 (match_operand:SI 7 "gpc_reg_operand" "r"))
10129 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10130 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10131 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10132 "{stsi|stswi} %2,%1,%O0"
10133 [(set_attr "type" "store_ux")
10134 (set_attr "cell_micro" "always")])
10136 (define_insn "*stmsi5"
10137 [(match_parallel 0 "store_multiple_operation"
10138 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10139 (match_operand:SI 2 "gpc_reg_operand" "r"))
10140 (clobber (match_scratch:SI 3 "=X"))
10141 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10142 (match_operand:SI 4 "gpc_reg_operand" "r"))
10143 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10144 (match_operand:SI 5 "gpc_reg_operand" "r"))
10145 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10146 (match_operand:SI 6 "gpc_reg_operand" "r"))
10147 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10148 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10149 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10150 "{stsi|stswi} %2,%1,%O0"
10151 [(set_attr "type" "store_ux")
10152 (set_attr "cell_micro" "always")])
10154 (define_insn "*stmsi4"
10155 [(match_parallel 0 "store_multiple_operation"
10156 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10157 (match_operand:SI 2 "gpc_reg_operand" "r"))
10158 (clobber (match_scratch:SI 3 "=X"))
10159 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10160 (match_operand:SI 4 "gpc_reg_operand" "r"))
10161 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10162 (match_operand:SI 5 "gpc_reg_operand" "r"))
10163 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10164 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10165 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10166 "{stsi|stswi} %2,%1,%O0"
10167 [(set_attr "type" "store_ux")
10168 (set_attr "cell_micro" "always")])
10170 (define_insn "*stmsi3"
10171 [(match_parallel 0 "store_multiple_operation"
10172 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10173 (match_operand:SI 2 "gpc_reg_operand" "r"))
10174 (clobber (match_scratch:SI 3 "=X"))
10175 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10176 (match_operand:SI 4 "gpc_reg_operand" "r"))
10177 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10178 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10179 "TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10180 "{stsi|stswi} %2,%1,%O0"
10181 [(set_attr "type" "store_ux")
10182 (set_attr "cell_micro" "always")])
10184 (define_insn "*stmsi8_power"
10185 [(match_parallel 0 "store_multiple_operation"
10186 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10187 (match_operand:SI 2 "gpc_reg_operand" "r"))
10188 (clobber (match_scratch:SI 3 "=q"))
10189 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10190 (match_operand:SI 4 "gpc_reg_operand" "r"))
10191 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10192 (match_operand:SI 5 "gpc_reg_operand" "r"))
10193 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10194 (match_operand:SI 6 "gpc_reg_operand" "r"))
10195 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10196 (match_operand:SI 7 "gpc_reg_operand" "r"))
10197 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10198 (match_operand:SI 8 "gpc_reg_operand" "r"))
10199 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10200 (match_operand:SI 9 "gpc_reg_operand" "r"))
10201 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
10202 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
10203 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
10204 "{stsi|stswi} %2,%1,%O0"
10205 [(set_attr "type" "store_ux")
10206 (set_attr "cell_micro" "always")])
10208 (define_insn "*stmsi7_power"
10209 [(match_parallel 0 "store_multiple_operation"
10210 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10211 (match_operand:SI 2 "gpc_reg_operand" "r"))
10212 (clobber (match_scratch:SI 3 "=q"))
10213 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10214 (match_operand:SI 4 "gpc_reg_operand" "r"))
10215 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10216 (match_operand:SI 5 "gpc_reg_operand" "r"))
10217 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10218 (match_operand:SI 6 "gpc_reg_operand" "r"))
10219 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10220 (match_operand:SI 7 "gpc_reg_operand" "r"))
10221 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10222 (match_operand:SI 8 "gpc_reg_operand" "r"))
10223 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
10224 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
10225 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
10226 "{stsi|stswi} %2,%1,%O0"
10227 [(set_attr "type" "store_ux")
10228 (set_attr "cell_micro" "always")])
10230 (define_insn "*stmsi6_power"
10231 [(match_parallel 0 "store_multiple_operation"
10232 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10233 (match_operand:SI 2 "gpc_reg_operand" "r"))
10234 (clobber (match_scratch:SI 3 "=q"))
10235 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10236 (match_operand:SI 4 "gpc_reg_operand" "r"))
10237 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10238 (match_operand:SI 5 "gpc_reg_operand" "r"))
10239 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10240 (match_operand:SI 6 "gpc_reg_operand" "r"))
10241 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10242 (match_operand:SI 7 "gpc_reg_operand" "r"))
10243 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
10244 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
10245 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
10246 "{stsi|stswi} %2,%1,%O0"
10247 [(set_attr "type" "store_ux")
10248 (set_attr "cell_micro" "always")])
10250 (define_insn "*stmsi5_power"
10251 [(match_parallel 0 "store_multiple_operation"
10252 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10253 (match_operand:SI 2 "gpc_reg_operand" "r"))
10254 (clobber (match_scratch:SI 3 "=q"))
10255 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10256 (match_operand:SI 4 "gpc_reg_operand" "r"))
10257 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10258 (match_operand:SI 5 "gpc_reg_operand" "r"))
10259 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10260 (match_operand:SI 6 "gpc_reg_operand" "r"))
10261 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
10262 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
10263 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
10264 "{stsi|stswi} %2,%1,%O0"
10265 [(set_attr "type" "store_ux")
10266 (set_attr "cell_micro" "always")])
10268 (define_insn "*stmsi4_power"
10269 [(match_parallel 0 "store_multiple_operation"
10270 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10271 (match_operand:SI 2 "gpc_reg_operand" "r"))
10272 (clobber (match_scratch:SI 3 "=q"))
10273 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10274 (match_operand:SI 4 "gpc_reg_operand" "r"))
10275 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10276 (match_operand:SI 5 "gpc_reg_operand" "r"))
10277 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
10278 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
10279 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
10280 "{stsi|stswi} %2,%1,%O0"
10281 [(set_attr "type" "store_ux")
10282 (set_attr "cell_micro" "always")])
10284 (define_insn "*stmsi3_power"
10285 [(match_parallel 0 "store_multiple_operation"
10286 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
10287 (match_operand:SI 2 "gpc_reg_operand" "r"))
10288 (clobber (match_scratch:SI 3 "=q"))
10289 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
10290 (match_operand:SI 4 "gpc_reg_operand" "r"))
10291 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
10292 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
10293 "TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
10294 "{stsi|stswi} %2,%1,%O0"
10295 [(set_attr "type" "store_ux")
10296 (set_attr "cell_micro" "always")])
10297 \f
10298 (define_expand "setmemsi"
10299 [(parallel [(set (match_operand:BLK 0 "" "")
10300 (match_operand 2 "const_int_operand" ""))
10301 (use (match_operand:SI 1 "" ""))
10302 (use (match_operand:SI 3 "" ""))])]
10303 ""
10304 "
10305 {
10306 /* If value to set is not zero, use the library routine. */
10307 if (operands[2] != const0_rtx)
10308 FAIL;
10310 if (expand_block_clear (operands))
10311 DONE;
10312 else
10313 FAIL;
10314 }")
10316 ;; String/block move insn.
10317 ;; Argument 0 is the destination
10318 ;; Argument 1 is the source
10319 ;; Argument 2 is the length
10320 ;; Argument 3 is the alignment
10322 (define_expand "movmemsi"
10323 [(parallel [(set (match_operand:BLK 0 "" "")
10324 (match_operand:BLK 1 "" ""))
10325 (use (match_operand:SI 2 "" ""))
10326 (use (match_operand:SI 3 "" ""))])]
10327 ""
10328 "
10329 {
10330 if (expand_block_move (operands))
10331 DONE;
10332 else
10333 FAIL;
10334 }")
10336 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
10337 ;; register allocator doesn't have a clue about allocating 8 word registers.
10338 ;; rD/rS = r5 is preferred, efficient form.
10339 (define_expand "movmemsi_8reg"
10340 [(parallel [(set (match_operand 0 "" "")
10341 (match_operand 1 "" ""))
10342 (use (match_operand 2 "" ""))
10343 (use (match_operand 3 "" ""))
10344 (clobber (reg:SI 5))
10345 (clobber (reg:SI 6))
10346 (clobber (reg:SI 7))
10347 (clobber (reg:SI 8))
10348 (clobber (reg:SI 9))
10349 (clobber (reg:SI 10))
10350 (clobber (reg:SI 11))
10351 (clobber (reg:SI 12))
10352 (clobber (match_scratch:SI 4 ""))])]
10353 "TARGET_STRING"
10354 "")
10356 (define_insn ""
10357 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10358 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10359 (use (match_operand:SI 2 "immediate_operand" "i"))
10360 (use (match_operand:SI 3 "immediate_operand" "i"))
10361 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10362 (clobber (reg:SI 6))
10363 (clobber (reg:SI 7))
10364 (clobber (reg:SI 8))
10365 (clobber (reg:SI 9))
10366 (clobber (reg:SI 10))
10367 (clobber (reg:SI 11))
10368 (clobber (reg:SI 12))
10369 (clobber (match_scratch:SI 5 "=q"))]
10370 "TARGET_STRING && TARGET_POWER
10371 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10372 || INTVAL (operands[2]) == 0)
10373 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10374 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10375 && REGNO (operands[4]) == 5"
10376 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10377 [(set_attr "type" "store_ux")
10378 (set_attr "cell_micro" "always")
10379 (set_attr "length" "8")])
10381 (define_insn ""
10382 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10383 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10384 (use (match_operand:SI 2 "immediate_operand" "i"))
10385 (use (match_operand:SI 3 "immediate_operand" "i"))
10386 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10387 (clobber (reg:SI 6))
10388 (clobber (reg:SI 7))
10389 (clobber (reg:SI 8))
10390 (clobber (reg:SI 9))
10391 (clobber (reg:SI 10))
10392 (clobber (reg:SI 11))
10393 (clobber (reg:SI 12))
10394 (clobber (match_scratch:SI 5 "=X"))]
10395 "TARGET_STRING && ! TARGET_POWER
10396 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
10397 || INTVAL (operands[2]) == 0)
10398 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
10399 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
10400 && REGNO (operands[4]) == 5"
10401 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10402 [(set_attr "type" "store_ux")
10403 (set_attr "cell_micro" "always")
10404 (set_attr "length" "8")])
10406 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
10407 ;; register allocator doesn't have a clue about allocating 6 word registers.
10408 ;; rD/rS = r5 is preferred, efficient form.
10409 (define_expand "movmemsi_6reg"
10410 [(parallel [(set (match_operand 0 "" "")
10411 (match_operand 1 "" ""))
10412 (use (match_operand 2 "" ""))
10413 (use (match_operand 3 "" ""))
10414 (clobber (reg:SI 5))
10415 (clobber (reg:SI 6))
10416 (clobber (reg:SI 7))
10417 (clobber (reg:SI 8))
10418 (clobber (reg:SI 9))
10419 (clobber (reg:SI 10))
10420 (clobber (match_scratch:SI 4 ""))])]
10421 "TARGET_STRING"
10422 "")
10424 (define_insn ""
10425 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10426 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10427 (use (match_operand:SI 2 "immediate_operand" "i"))
10428 (use (match_operand:SI 3 "immediate_operand" "i"))
10429 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10430 (clobber (reg:SI 6))
10431 (clobber (reg:SI 7))
10432 (clobber (reg:SI 8))
10433 (clobber (reg:SI 9))
10434 (clobber (reg:SI 10))
10435 (clobber (match_scratch:SI 5 "=q"))]
10436 "TARGET_STRING && TARGET_POWER
10437 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
10438 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10439 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10440 && REGNO (operands[4]) == 5"
10441 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10442 [(set_attr "type" "store_ux")
10443 (set_attr "cell_micro" "always")
10444 (set_attr "length" "8")])
10446 (define_insn ""
10447 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10448 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10449 (use (match_operand:SI 2 "immediate_operand" "i"))
10450 (use (match_operand:SI 3 "immediate_operand" "i"))
10451 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10452 (clobber (reg:SI 6))
10453 (clobber (reg:SI 7))
10454 (clobber (reg:SI 8))
10455 (clobber (reg:SI 9))
10456 (clobber (reg:SI 10))
10457 (clobber (match_scratch:SI 5 "=X"))]
10458 "TARGET_STRING && ! TARGET_POWER
10459 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
10460 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
10461 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
10462 && REGNO (operands[4]) == 5"
10463 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10464 [(set_attr "type" "store_ux")
10465 (set_attr "cell_micro" "always")
10466 (set_attr "length" "8")])
10468 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
10469 ;; problems with TImode.
10470 ;; rD/rS = r5 is preferred, efficient form.
10471 (define_expand "movmemsi_4reg"
10472 [(parallel [(set (match_operand 0 "" "")
10473 (match_operand 1 "" ""))
10474 (use (match_operand 2 "" ""))
10475 (use (match_operand 3 "" ""))
10476 (clobber (reg:SI 5))
10477 (clobber (reg:SI 6))
10478 (clobber (reg:SI 7))
10479 (clobber (reg:SI 8))
10480 (clobber (match_scratch:SI 4 ""))])]
10481 "TARGET_STRING"
10482 "")
10484 (define_insn ""
10485 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10486 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10487 (use (match_operand:SI 2 "immediate_operand" "i"))
10488 (use (match_operand:SI 3 "immediate_operand" "i"))
10489 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10490 (clobber (reg:SI 6))
10491 (clobber (reg:SI 7))
10492 (clobber (reg:SI 8))
10493 (clobber (match_scratch:SI 5 "=q"))]
10494 "TARGET_STRING && TARGET_POWER
10495 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10496 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10497 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10498 && REGNO (operands[4]) == 5"
10499 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10500 [(set_attr "type" "store_ux")
10501 (set_attr "cell_micro" "always")
10502 (set_attr "length" "8")])
10504 (define_insn ""
10505 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10506 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10507 (use (match_operand:SI 2 "immediate_operand" "i"))
10508 (use (match_operand:SI 3 "immediate_operand" "i"))
10509 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
10510 (clobber (reg:SI 6))
10511 (clobber (reg:SI 7))
10512 (clobber (reg:SI 8))
10513 (clobber (match_scratch:SI 5 "=X"))]
10514 "TARGET_STRING && ! TARGET_POWER
10515 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
10516 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
10517 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
10518 && REGNO (operands[4]) == 5"
10519 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10520 [(set_attr "type" "store_ux")
10521 (set_attr "cell_micro" "always")
10522 (set_attr "length" "8")])
10524 ;; Move up to 8 bytes at a time.
10525 (define_expand "movmemsi_2reg"
10526 [(parallel [(set (match_operand 0 "" "")
10527 (match_operand 1 "" ""))
10528 (use (match_operand 2 "" ""))
10529 (use (match_operand 3 "" ""))
10530 (clobber (match_scratch:DI 4 ""))
10531 (clobber (match_scratch:SI 5 ""))])]
10532 "TARGET_STRING && ! TARGET_POWERPC64"
10533 "")
10535 (define_insn ""
10536 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10537 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10538 (use (match_operand:SI 2 "immediate_operand" "i"))
10539 (use (match_operand:SI 3 "immediate_operand" "i"))
10540 (clobber (match_scratch:DI 4 "=&r"))
10541 (clobber (match_scratch:SI 5 "=q"))]
10542 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
10543 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10544 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10545 [(set_attr "type" "store_ux")
10546 (set_attr "cell_micro" "always")
10547 (set_attr "length" "8")])
10549 (define_insn ""
10550 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10551 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10552 (use (match_operand:SI 2 "immediate_operand" "i"))
10553 (use (match_operand:SI 3 "immediate_operand" "i"))
10554 (clobber (match_scratch:DI 4 "=&r"))
10555 (clobber (match_scratch:SI 5 "=X"))]
10556 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
10557 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
10558 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10559 [(set_attr "type" "store_ux")
10560 (set_attr "cell_micro" "always")
10561 (set_attr "length" "8")])
10563 ;; Move up to 4 bytes at a time.
10564 (define_expand "movmemsi_1reg"
10565 [(parallel [(set (match_operand 0 "" "")
10566 (match_operand 1 "" ""))
10567 (use (match_operand 2 "" ""))
10568 (use (match_operand 3 "" ""))
10569 (clobber (match_scratch:SI 4 ""))
10570 (clobber (match_scratch:SI 5 ""))])]
10571 "TARGET_STRING"
10572 "")
10574 (define_insn ""
10575 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
10576 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
10577 (use (match_operand:SI 2 "immediate_operand" "i"))
10578 (use (match_operand:SI 3 "immediate_operand" "i"))
10579 (clobber (match_scratch:SI 4 "=&r"))
10580 (clobber (match_scratch:SI 5 "=q"))]
10581 "TARGET_STRING && TARGET_POWER
10582 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10583 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10584 [(set_attr "type" "store_ux")
10585 (set_attr "cell_micro" "always")
10586 (set_attr "length" "8")])
10588 (define_insn ""
10589 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
10590 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
10591 (use (match_operand:SI 2 "immediate_operand" "i"))
10592 (use (match_operand:SI 3 "immediate_operand" "i"))
10593 (clobber (match_scratch:SI 4 "=&r"))
10594 (clobber (match_scratch:SI 5 "=X"))]
10595 "TARGET_STRING && ! TARGET_POWER
10596 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
10597 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
10598 [(set_attr "type" "store_ux")
10599 (set_attr "cell_micro" "always")
10600 (set_attr "length" "8")])
10601 \f
10602 ;; Define insns that do load or store with update. Some of these we can
10603 ;; get by using pre-decrement or pre-increment, but the hardware can also
10604 ;; do cases where the increment is not the size of the object.
10605 ;;
10606 ;; In all these cases, we use operands 0 and 1 for the register being
10607 ;; incremented because those are the operands that local-alloc will
10608 ;; tie and these are the pair most likely to be tieable (and the ones
10609 ;; that will benefit the most).
10611 (define_insn "*movdi_update1"
10612 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
10613 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
10614 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
10615 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
10616 (plus:DI (match_dup 1) (match_dup 2)))]
10617 "TARGET_POWERPC64 && TARGET_UPDATE
10618 && (!avoiding_indexed_address_p (DImode)
10619 || !gpc_reg_operand (operands[2], DImode))"
10620 "@
10621 ldux %3,%0,%2
10622 ldu %3,%2(%0)"
10623 [(set_attr "type" "load_ux,load_u")])
10625 (define_insn "movdi_<mode>_update"
10626 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10627 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10628 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10629 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10630 (plus:P (match_dup 1) (match_dup 2)))]
10631 "TARGET_POWERPC64 && TARGET_UPDATE
10632 && (!avoiding_indexed_address_p (Pmode)
10633 || !gpc_reg_operand (operands[2], Pmode)
10634 || (REG_P (operands[0])
10635 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10636 "@
10637 stdux %3,%0,%2
10638 stdu %3,%2(%0)"
10639 [(set_attr "type" "store_ux,store_u")])
10641 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
10642 ;; needed for stack allocation, even if the user passes -mno-update.
10643 (define_insn "movdi_<mode>_update_stack"
10644 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
10645 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
10646 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10647 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
10648 (plus:P (match_dup 1) (match_dup 2)))]
10649 "TARGET_POWERPC64"
10650 "@
10651 stdux %3,%0,%2
10652 stdu %3,%2(%0)"
10653 [(set_attr "type" "store_ux,store_u")])
10655 (define_insn "*movsi_update1"
10656 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10657 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10658 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10659 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10660 (plus:SI (match_dup 1) (match_dup 2)))]
10661 "TARGET_UPDATE
10662 && (!avoiding_indexed_address_p (SImode)
10663 || !gpc_reg_operand (operands[2], SImode))"
10664 "@
10665 {lux|lwzux} %3,%0,%2
10666 {lu|lwzu} %3,%2(%0)"
10667 [(set_attr "type" "load_ux,load_u")])
10669 (define_insn "*movsi_update2"
10670 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
10671 (sign_extend:DI
10672 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
10673 (match_operand:DI 2 "gpc_reg_operand" "r")))))
10674 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
10675 (plus:DI (match_dup 1) (match_dup 2)))]
10676 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
10677 && !avoiding_indexed_address_p (DImode)"
10678 "lwaux %3,%0,%2"
10679 [(set_attr "type" "load_ext_ux")])
10681 (define_insn "movsi_update"
10682 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10683 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10684 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10685 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10686 (plus:SI (match_dup 1) (match_dup 2)))]
10687 "TARGET_UPDATE
10688 && (!avoiding_indexed_address_p (SImode)
10689 || !gpc_reg_operand (operands[2], SImode)
10690 || (REG_P (operands[0])
10691 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
10692 "@
10693 {stux|stwux} %3,%0,%2
10694 {stu|stwu} %3,%2(%0)"
10695 [(set_attr "type" "store_ux,store_u")])
10697 ;; This is an unconditional pattern; needed for stack allocation, even
10698 ;; if the user passes -mno-update.
10699 (define_insn "movsi_update_stack"
10700 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10701 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10702 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10703 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10704 (plus:SI (match_dup 1) (match_dup 2)))]
10705 ""
10706 "@
10707 {stux|stwux} %3,%0,%2
10708 {stu|stwu} %3,%2(%0)"
10709 [(set_attr "type" "store_ux,store_u")])
10711 (define_insn "*movhi_update1"
10712 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
10713 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10714 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10715 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10716 (plus:SI (match_dup 1) (match_dup 2)))]
10717 "TARGET_UPDATE
10718 && (!avoiding_indexed_address_p (SImode)
10719 || !gpc_reg_operand (operands[2], SImode))"
10720 "@
10721 lhzux %3,%0,%2
10722 lhzu %3,%2(%0)"
10723 [(set_attr "type" "load_ux,load_u")])
10725 (define_insn "*movhi_update2"
10726 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10727 (zero_extend:SI
10728 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10729 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10730 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10731 (plus:SI (match_dup 1) (match_dup 2)))]
10732 "TARGET_UPDATE
10733 && (!avoiding_indexed_address_p (SImode)
10734 || !gpc_reg_operand (operands[2], SImode))"
10735 "@
10736 lhzux %3,%0,%2
10737 lhzu %3,%2(%0)"
10738 [(set_attr "type" "load_ux,load_u")])
10740 (define_insn "*movhi_update3"
10741 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10742 (sign_extend:SI
10743 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10744 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10745 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10746 (plus:SI (match_dup 1) (match_dup 2)))]
10747 "TARGET_UPDATE && rs6000_gen_cell_microcode
10748 && (!avoiding_indexed_address_p (SImode)
10749 || !gpc_reg_operand (operands[2], SImode))"
10750 "@
10751 lhaux %3,%0,%2
10752 lhau %3,%2(%0)"
10753 [(set_attr "type" "load_ext_ux,load_ext_u")])
10755 (define_insn "*movhi_update4"
10756 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10757 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10758 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
10759 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10760 (plus:SI (match_dup 1) (match_dup 2)))]
10761 "TARGET_UPDATE
10762 && (!avoiding_indexed_address_p (SImode)
10763 || !gpc_reg_operand (operands[2], SImode))"
10764 "@
10765 sthux %3,%0,%2
10766 sthu %3,%2(%0)"
10767 [(set_attr "type" "store_ux,store_u")])
10769 (define_insn "*movqi_update1"
10770 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10771 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10772 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10773 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10774 (plus:SI (match_dup 1) (match_dup 2)))]
10775 "TARGET_UPDATE
10776 && (!avoiding_indexed_address_p (SImode)
10777 || !gpc_reg_operand (operands[2], SImode))"
10778 "@
10779 lbzux %3,%0,%2
10780 lbzu %3,%2(%0)"
10781 [(set_attr "type" "load_ux,load_u")])
10783 (define_insn "*movqi_update2"
10784 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10785 (zero_extend:SI
10786 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10787 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10788 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10789 (plus:SI (match_dup 1) (match_dup 2)))]
10790 "TARGET_UPDATE
10791 && (!avoiding_indexed_address_p (SImode)
10792 || !gpc_reg_operand (operands[2], SImode))"
10793 "@
10794 lbzux %3,%0,%2
10795 lbzu %3,%2(%0)"
10796 [(set_attr "type" "load_ux,load_u")])
10798 (define_insn "*movqi_update3"
10799 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10800 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10801 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10802 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10803 (plus:SI (match_dup 1) (match_dup 2)))]
10804 "TARGET_UPDATE
10805 && (!avoiding_indexed_address_p (SImode)
10806 || !gpc_reg_operand (operands[2], SImode))"
10807 "@
10808 stbux %3,%0,%2
10809 stbu %3,%2(%0)"
10810 [(set_attr "type" "store_ux,store_u")])
10812 (define_insn "*movsf_update1"
10813 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10814 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10815 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10816 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10817 (plus:SI (match_dup 1) (match_dup 2)))]
10818 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10819 && (!avoiding_indexed_address_p (SImode)
10820 || !gpc_reg_operand (operands[2], SImode))"
10821 "@
10822 lfsux %3,%0,%2
10823 lfsu %3,%2(%0)"
10824 [(set_attr "type" "fpload_ux,fpload_u")])
10826 (define_insn "*movsf_update2"
10827 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10828 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10829 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10830 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10831 (plus:SI (match_dup 1) (match_dup 2)))]
10832 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10833 && (!avoiding_indexed_address_p (SImode)
10834 || !gpc_reg_operand (operands[2], SImode))"
10835 "@
10836 stfsux %3,%0,%2
10837 stfsu %3,%2(%0)"
10838 [(set_attr "type" "fpstore_ux,fpstore_u")])
10840 (define_insn "*movsf_update3"
10841 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10842 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10843 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10844 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10845 (plus:SI (match_dup 1) (match_dup 2)))]
10846 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10847 && (!avoiding_indexed_address_p (SImode)
10848 || !gpc_reg_operand (operands[2], SImode))"
10849 "@
10850 {lux|lwzux} %3,%0,%2
10851 {lu|lwzu} %3,%2(%0)"
10852 [(set_attr "type" "load_ux,load_u")])
10854 (define_insn "*movsf_update4"
10855 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10856 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10857 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10858 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10859 (plus:SI (match_dup 1) (match_dup 2)))]
10860 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10861 && (!avoiding_indexed_address_p (SImode)
10862 || !gpc_reg_operand (operands[2], SImode))"
10863 "@
10864 {stux|stwux} %3,%0,%2
10865 {stu|stwu} %3,%2(%0)"
10866 [(set_attr "type" "store_ux,store_u")])
10868 (define_insn "*movdf_update1"
10869 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
10870 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10871 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10872 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10873 (plus:SI (match_dup 1) (match_dup 2)))]
10874 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10875 && (!avoiding_indexed_address_p (SImode)
10876 || !gpc_reg_operand (operands[2], SImode))"
10877 "@
10878 lfdux %3,%0,%2
10879 lfdu %3,%2(%0)"
10880 [(set_attr "type" "fpload_ux,fpload_u")])
10882 (define_insn "*movdf_update2"
10883 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10884 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10885 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
10886 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10887 (plus:SI (match_dup 1) (match_dup 2)))]
10888 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10889 && (!avoiding_indexed_address_p (SImode)
10890 || !gpc_reg_operand (operands[2], SImode))"
10891 "@
10892 stfdux %3,%0,%2
10893 stfdu %3,%2(%0)"
10894 [(set_attr "type" "fpstore_ux,fpstore_u")])
10896 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10898 (define_insn "*lfq_power2"
10899 [(set (match_operand:V2DF 0 "gpc_reg_operand" "=f")
10900 (match_operand:V2DF 1 "memory_operand" ""))]
10901 "TARGET_POWER2
10902 && TARGET_HARD_FLOAT && TARGET_FPRS"
10903 "lfq%U1%X1 %0,%1")
10905 (define_peephole2
10906 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10907 (match_operand:DF 1 "memory_operand" ""))
10908 (set (match_operand:DF 2 "gpc_reg_operand" "")
10909 (match_operand:DF 3 "memory_operand" ""))]
10910 "TARGET_POWER2
10911 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10912 && registers_ok_for_quad_peep (operands[0], operands[2])
10913 && mems_ok_for_quad_peep (operands[1], operands[3])"
10914 [(set (match_dup 0)
10915 (match_dup 1))]
10916 "operands[1] = widen_memory_access (operands[1], V2DFmode, 0);
10917 operands[0] = gen_rtx_REG (V2DFmode, REGNO (operands[0]));")
10919 (define_insn "*stfq_power2"
10920 [(set (match_operand:V2DF 0 "memory_operand" "")
10921 (match_operand:V2DF 1 "gpc_reg_operand" "f"))]
10922 "TARGET_POWER2
10923 && TARGET_HARD_FLOAT && TARGET_FPRS"
10924 "stfq%U0%X0 %1,%0")
10927 (define_peephole2
10928 [(set (match_operand:DF 0 "memory_operand" "")
10929 (match_operand:DF 1 "gpc_reg_operand" ""))
10930 (set (match_operand:DF 2 "memory_operand" "")
10931 (match_operand:DF 3 "gpc_reg_operand" ""))]
10932 "TARGET_POWER2
10933 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
10934 && registers_ok_for_quad_peep (operands[1], operands[3])
10935 && mems_ok_for_quad_peep (operands[0], operands[2])"
10936 [(set (match_dup 0)
10937 (match_dup 1))]
10938 "operands[0] = widen_memory_access (operands[0], V2DFmode, 0);
10939 operands[1] = gen_rtx_REG (V2DFmode, REGNO (operands[1]));")
10941 ;; After inserting conditional returns we can sometimes have
10942 ;; unnecessary register moves. Unfortunately we cannot have a
10943 ;; modeless peephole here, because some single SImode sets have early
10944 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10945 ;; sequences, using get_attr_length here will smash the operands
10946 ;; array. Neither is there an early_cobbler_p predicate.
10947 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10948 (define_peephole2
10949 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10950 (match_operand:DF 1 "any_operand" ""))
10951 (set (match_operand:DF 2 "gpc_reg_operand" "")
10952 (match_dup 0))]
10953 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10954 && peep2_reg_dead_p (2, operands[0])"
10955 [(set (match_dup 2) (match_dup 1))])
10957 (define_peephole2
10958 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10959 (match_operand:SF 1 "any_operand" ""))
10960 (set (match_operand:SF 2 "gpc_reg_operand" "")
10961 (match_dup 0))]
10962 "peep2_reg_dead_p (2, operands[0])"
10963 [(set (match_dup 2) (match_dup 1))])
10965 \f
10966 ;; TLS support.
10968 ;; Mode attributes for different ABIs.
10969 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
10970 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
10971 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
10972 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
10974 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
10975 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10976 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10977 (match_operand 4 "" "g")))
10978 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10979 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10980 UNSPEC_TLSGD)
10981 (clobber (reg:SI LR_REGNO))]
10982 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10983 "addi %0,%1,%2@got@tlsgd\;bl %z3\;%."
10984 "&& TARGET_TLS_MARKERS"
10985 [(set (match_dup 0)
10986 (unspec:TLSmode [(match_dup 1)
10987 (match_dup 2)]
10988 UNSPEC_TLSGD))
10989 (parallel [(set (match_dup 0)
10990 (call (mem:TLSmode (match_dup 3))
10991 (match_dup 4)))
10992 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10993 (clobber (reg:SI LR_REGNO))])]
10994 ""
10995 [(set_attr "type" "two")
10996 (set_attr "length" "12")])
10998 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
10999 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11000 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
11001 (match_operand 4 "" "g")))
11002 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11003 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11004 UNSPEC_TLSGD)
11005 (clobber (reg:SI LR_REGNO))]
11006 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11007 {
11008 if (flag_pic)
11009 {
11010 if (TARGET_SECURE_PLT && flag_pic == 2)
11011 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
11012 else
11013 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
11014 }
11015 else
11016 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
11017 }
11018 "&& TARGET_TLS_MARKERS"
11019 [(set (match_dup 0)
11020 (unspec:TLSmode [(match_dup 1)
11021 (match_dup 2)]
11022 UNSPEC_TLSGD))
11023 (parallel [(set (match_dup 0)
11024 (call (mem:TLSmode (match_dup 3))
11025 (match_dup 4)))
11026 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
11027 (clobber (reg:SI LR_REGNO))])]
11028 ""
11029 [(set_attr "type" "two")
11030 (set_attr "length" "8")])
11032 (define_insn "*tls_gd<TLSmode:tls_abi_suffix>"
11033 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11034 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11035 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11036 UNSPEC_TLSGD))]
11037 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11038 "addi %0,%1,%2@got@tlsgd"
11039 [(set_attr "length" "4")])
11041 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
11042 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11043 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11044 (match_operand 2 "" "g")))
11045 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11046 UNSPEC_TLSGD)
11047 (clobber (reg:SI LR_REGNO))]
11048 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11049 "bl %z1(%3@tlsgd)\;%."
11050 [(set_attr "type" "branch")
11051 (set_attr "length" "8")])
11053 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
11054 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11055 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11056 (match_operand 2 "" "g")))
11057 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
11058 UNSPEC_TLSGD)
11059 (clobber (reg:SI LR_REGNO))]
11060 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11061 {
11062 if (flag_pic)
11063 {
11064 if (TARGET_SECURE_PLT && flag_pic == 2)
11065 return "bl %z1+32768(%3@tlsgd)@plt";
11066 return "bl %z1(%3@tlsgd)@plt";
11067 }
11068 return "bl %z1(%3@tlsgd)";
11069 }
11070 [(set_attr "type" "branch")
11071 (set_attr "length" "4")])
11073 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
11074 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11075 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11076 (match_operand 3 "" "g")))
11077 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11078 UNSPEC_TLSLD)
11079 (clobber (reg:SI LR_REGNO))]
11080 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
11081 "addi %0,%1,%&@got@tlsld\;bl %z2\;%."
11082 "&& TARGET_TLS_MARKERS"
11083 [(set (match_dup 0)
11084 (unspec:TLSmode [(match_dup 1)]
11085 UNSPEC_TLSLD))
11086 (parallel [(set (match_dup 0)
11087 (call (mem:TLSmode (match_dup 2))
11088 (match_dup 3)))
11089 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11090 (clobber (reg:SI LR_REGNO))])]
11091 ""
11092 [(set_attr "length" "12")])
11094 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
11095 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11096 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
11097 (match_operand 3 "" "g")))
11098 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11099 UNSPEC_TLSLD)
11100 (clobber (reg:SI LR_REGNO))]
11101 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
11102 {
11103 if (flag_pic)
11104 {
11105 if (TARGET_SECURE_PLT && flag_pic == 2)
11106 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
11107 else
11108 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
11109 }
11110 else
11111 return "addi %0,%1,%&@got@tlsld\;bl %z2";
11112 }
11113 "&& TARGET_TLS_MARKERS"
11114 [(set (match_dup 0)
11115 (unspec:TLSmode [(match_dup 1)]
11116 UNSPEC_TLSLD))
11117 (parallel [(set (match_dup 0)
11118 (call (mem:TLSmode (match_dup 2))
11119 (match_dup 3)))
11120 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11121 (clobber (reg:SI LR_REGNO))])]
11122 ""
11123 [(set_attr "length" "8")])
11125 (define_insn "*tls_ld<TLSmode:tls_abi_suffix>"
11126 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11127 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
11128 UNSPEC_TLSLD))]
11129 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
11130 "addi %0,%1,%&@got@tlsld"
11131 [(set_attr "length" "4")])
11133 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
11134 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11135 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11136 (match_operand 2 "" "g")))
11137 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11138 (clobber (reg:SI LR_REGNO))]
11139 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
11140 "bl %z1(%&@tlsld)\;%."
11141 [(set_attr "type" "branch")
11142 (set_attr "length" "8")])
11144 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
11145 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11146 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
11147 (match_operand 2 "" "g")))
11148 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
11149 (clobber (reg:SI LR_REGNO))]
11150 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
11151 {
11152 if (flag_pic)
11153 {
11154 if (TARGET_SECURE_PLT && flag_pic == 2)
11155 return "bl %z1+32768(%&@tlsld)@plt";
11156 return "bl %z1(%&@tlsld)@plt";
11157 }
11158 return "bl %z1(%&@tlsld)";
11159 }
11160 [(set_attr "type" "branch")
11161 (set_attr "length" "4")])
11163 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
11164 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11165 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11166 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11167 UNSPEC_TLSDTPREL))]
11168 "HAVE_AS_TLS"
11169 "addi %0,%1,%2@dtprel")
11171 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
11172 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11173 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11174 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11175 UNSPEC_TLSDTPRELHA))]
11176 "HAVE_AS_TLS"
11177 "addis %0,%1,%2@dtprel@ha")
11179 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
11180 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11181 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11182 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11183 UNSPEC_TLSDTPRELLO))]
11184 "HAVE_AS_TLS"
11185 "addi %0,%1,%2@dtprel@l")
11187 (define_insn "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
11188 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11189 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11190 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11191 UNSPEC_TLSGOTDTPREL))]
11192 "HAVE_AS_TLS"
11193 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)")
11195 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
11196 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11197 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11198 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11199 UNSPEC_TLSTPREL))]
11200 "HAVE_AS_TLS"
11201 "addi %0,%1,%2@tprel")
11203 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
11204 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11205 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11206 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11207 UNSPEC_TLSTPRELHA))]
11208 "HAVE_AS_TLS"
11209 "addis %0,%1,%2@tprel@ha")
11211 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
11212 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11213 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11214 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11215 UNSPEC_TLSTPRELLO))]
11216 "HAVE_AS_TLS"
11217 "addi %0,%1,%2@tprel@l")
11219 ;; "b" output constraint here and on tls_tls input to support linker tls
11220 ;; optimization. The linker may edit the instructions emitted by a
11221 ;; tls_got_tprel/tls_tls pair to addis,addi.
11222 (define_insn "tls_got_tprel_<TLSmode:tls_abi_suffix>"
11223 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
11224 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11225 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11226 UNSPEC_TLSGOTTPREL))]
11227 "HAVE_AS_TLS"
11228 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)")
11230 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
11231 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
11232 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
11233 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
11234 UNSPEC_TLSTLS))]
11235 "HAVE_AS_TLS"
11236 "add %0,%1,%2@tls")
11238 \f
11239 ;; Next come insns related to the calling sequence.
11240 ;;
11241 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
11242 ;; We move the back-chain and decrement the stack pointer.
11244 (define_expand "allocate_stack"
11245 [(set (match_operand 0 "gpc_reg_operand" "")
11246 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
11247 (set (reg 1)
11248 (minus (reg 1) (match_dup 1)))]
11249 ""
11250 "
11251 { rtx chain = gen_reg_rtx (Pmode);
11252 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
11253 rtx neg_op0;
11254 rtx insn, par, set, mem;
11256 emit_move_insn (chain, stack_bot);
11258 /* Check stack bounds if necessary. */
11259 if (crtl->limit_stack)
11260 {
11261 rtx available;
11262 available = expand_binop (Pmode, sub_optab,
11263 stack_pointer_rtx, stack_limit_rtx,
11264 NULL_RTX, 1, OPTAB_WIDEN);
11265 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
11266 }
11268 if (GET_CODE (operands[1]) != CONST_INT
11269 || INTVAL (operands[1]) < -32767
11270 || INTVAL (operands[1]) > 32768)
11271 {
11272 neg_op0 = gen_reg_rtx (Pmode);
11273 if (TARGET_32BIT)
11274 emit_insn (gen_negsi2 (neg_op0, operands[1]));
11275 else
11276 emit_insn (gen_negdi2 (neg_op0, operands[1]));
11277 }
11278 else
11279 neg_op0 = GEN_INT (- INTVAL (operands[1]));
11281 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
11282 : gen_movdi_di_update_stack))
11283 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
11284 chain));
11285 /* Since we didn't use gen_frame_mem to generate the MEM, grab
11286 it now and set the alias set/attributes. The above gen_*_update
11287 calls will generate a PARALLEL with the MEM set being the first
11288 operation. */
11289 par = PATTERN (insn);
11290 gcc_assert (GET_CODE (par) == PARALLEL);
11291 set = XVECEXP (par, 0, 0);
11292 gcc_assert (GET_CODE (set) == SET);
11293 mem = SET_DEST (set);
11294 gcc_assert (MEM_P (mem));
11295 MEM_NOTRAP_P (mem) = 1;
11296 set_mem_alias_set (mem, get_frame_alias_set ());
11298 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
11299 DONE;
11300 }")
11302 ;; These patterns say how to save and restore the stack pointer. We need not
11303 ;; save the stack pointer at function level since we are careful to
11304 ;; preserve the backchain. At block level, we have to restore the backchain
11305 ;; when we restore the stack pointer.
11306 ;;
11307 ;; For nonlocal gotos, we must save both the stack pointer and its
11308 ;; backchain and restore both. Note that in the nonlocal case, the
11309 ;; save area is a memory location.
11311 (define_expand "save_stack_function"
11312 [(match_operand 0 "any_operand" "")
11313 (match_operand 1 "any_operand" "")]
11314 ""
11315 "DONE;")
11317 (define_expand "restore_stack_function"
11318 [(match_operand 0 "any_operand" "")
11319 (match_operand 1 "any_operand" "")]
11320 ""
11321 "DONE;")
11323 ;; Adjust stack pointer (op0) to a new value (op1).
11324 ;; First copy old stack backchain to new location, and ensure that the
11325 ;; scheduler won't reorder the sp assignment before the backchain write.
11326 (define_expand "restore_stack_block"
11327 [(set (match_dup 2) (match_dup 3))
11328 (set (match_dup 4) (match_dup 2))
11329 (set (match_dup 5) (unspec:BLK [(match_dup 5)] UNSPEC_TIE))
11330 (set (match_operand 0 "register_operand" "")
11331 (match_operand 1 "register_operand" ""))]
11332 ""
11333 "
11334 {
11335 operands[1] = force_reg (Pmode, operands[1]);
11336 operands[2] = gen_reg_rtx (Pmode);
11337 operands[3] = gen_frame_mem (Pmode, operands[0]);
11338 operands[4] = gen_frame_mem (Pmode, operands[1]);
11339 operands[5] = gen_frame_mem (BLKmode, operands[0]);
11340 }")
11342 (define_expand "save_stack_nonlocal"
11343 [(set (match_dup 3) (match_dup 4))
11344 (set (match_operand 0 "memory_operand" "") (match_dup 3))
11345 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
11346 ""
11347 "
11348 {
11349 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11351 /* Copy the backchain to the first word, sp to the second. */
11352 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
11353 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
11354 operands[3] = gen_reg_rtx (Pmode);
11355 operands[4] = gen_frame_mem (Pmode, operands[1]);
11356 }")
11358 (define_expand "restore_stack_nonlocal"
11359 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
11360 (set (match_dup 3) (match_dup 4))
11361 (set (match_dup 5) (match_dup 2))
11362 (set (match_dup 6) (unspec:BLK [(match_dup 6)] UNSPEC_TIE))
11363 (set (match_operand 0 "register_operand" "") (match_dup 3))]
11364 ""
11365 "
11366 {
11367 int units_per_word = (TARGET_32BIT) ? 4 : 8;
11369 /* Restore the backchain from the first word, sp from the second. */
11370 operands[2] = gen_reg_rtx (Pmode);
11371 operands[3] = gen_reg_rtx (Pmode);
11372 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
11373 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
11374 operands[5] = gen_frame_mem (Pmode, operands[3]);
11375 operands[6] = gen_frame_mem (BLKmode, operands[0]);
11376 }")
11377 \f
11378 ;; TOC register handling.
11380 ;; Code to initialize the TOC register...
11382 (define_insn "load_toc_aix_si"
11383 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11384 (unspec:SI [(const_int 0)] UNSPEC_TOC))
11385 (use (reg:SI 2))])]
11386 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
11387 "*
11388 {
11389 char buf[30];
11390 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11391 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11392 operands[2] = gen_rtx_REG (Pmode, 2);
11393 return \"{l|lwz} %0,%1(%2)\";
11394 }"
11395 [(set_attr "type" "load")])
11397 (define_insn "load_toc_aix_di"
11398 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11399 (unspec:DI [(const_int 0)] UNSPEC_TOC))
11400 (use (reg:DI 2))])]
11401 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
11402 "*
11403 {
11404 char buf[30];
11405 #ifdef TARGET_RELOCATABLE
11406 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
11407 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
11408 #else
11409 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
11410 #endif
11411 if (TARGET_ELF)
11412 strcat (buf, \"@toc\");
11413 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11414 operands[2] = gen_rtx_REG (Pmode, 2);
11415 return \"ld %0,%1(%2)\";
11416 }"
11417 [(set_attr "type" "load")])
11419 (define_insn "load_toc_v4_pic_si"
11420 [(set (reg:SI LR_REGNO)
11421 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
11422 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
11423 "bl _GLOBAL_OFFSET_TABLE_@local-4"
11424 [(set_attr "type" "branch")
11425 (set_attr "length" "4")])
11427 (define_insn "load_toc_v4_PIC_1"
11428 [(set (reg:SI LR_REGNO)
11429 (match_operand:SI 0 "immediate_operand" "s"))
11430 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
11431 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
11432 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
11433 "bcl 20,31,%0\\n%0:"
11434 [(set_attr "type" "branch")
11435 (set_attr "length" "4")])
11437 (define_insn "load_toc_v4_PIC_1b"
11438 [(set (reg:SI LR_REGNO)
11439 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")]
11440 UNSPEC_TOCPTR))]
11441 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11442 "bcl 20,31,$+8\\n\\t.long %0-$"
11443 [(set_attr "type" "branch")
11444 (set_attr "length" "8")])
11446 (define_insn "load_toc_v4_PIC_2"
11447 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11448 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11449 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
11450 (match_operand:SI 3 "immediate_operand" "s")))))]
11451 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
11452 "{l|lwz} %0,%2-%3(%1)"
11453 [(set_attr "type" "load")])
11455 (define_insn "load_toc_v4_PIC_3b"
11456 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
11457 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
11458 (high:SI
11459 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11460 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
11461 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
11462 "{cau|addis} %0,%1,%2-%3@ha")
11464 (define_insn "load_toc_v4_PIC_3c"
11465 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11466 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
11467 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
11468 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
11469 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
11470 "{cal %0,%2-%3@l(%1)|addi %0,%1,%2-%3@l}")
11472 ;; If the TOC is shared over a translation unit, as happens with all
11473 ;; the kinds of PIC that we support, we need to restore the TOC
11474 ;; pointer only when jumping over units of translation.
11475 ;; On Darwin, we need to reload the picbase.
11477 (define_expand "builtin_setjmp_receiver"
11478 [(use (label_ref (match_operand 0 "" "")))]
11479 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
11480 || (TARGET_TOC && TARGET_MINIMAL_TOC)
11481 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
11482 "
11483 {
11484 #if TARGET_MACHO
11485 if (DEFAULT_ABI == ABI_DARWIN)
11486 {
11487 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
11488 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11489 rtx tmplabrtx;
11490 char tmplab[20];
11492 crtl->uses_pic_offset_table = 1;
11493 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
11494 CODE_LABEL_NUMBER (operands[0]));
11495 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
11497 emit_insn (gen_load_macho_picbase (tmplabrtx));
11498 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
11499 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
11500 }
11501 else
11502 #endif
11503 rs6000_emit_load_toc_table (FALSE);
11504 DONE;
11505 }")
11507 ;; Elf specific ways of loading addresses for non-PIC code.
11508 ;; The output of this could be r0, but we make a very strong
11509 ;; preference for a base register because it will usually
11510 ;; be needed there.
11511 (define_insn "elf_high"
11512 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
11513 (high:SI (match_operand 1 "" "")))]
11514 "TARGET_ELF && ! TARGET_64BIT"
11515 "{liu|lis} %0,%1@ha")
11517 (define_insn "elf_low"
11518 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
11519 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
11520 (match_operand 2 "" "")))]
11521 "TARGET_ELF && ! TARGET_64BIT"
11522 "@
11523 {cal|la} %0,%2@l(%1)
11524 {ai|addic} %0,%1,%K2")
11525 \f
11526 ;; A function pointer under AIX is a pointer to a data area whose first word
11527 ;; contains the actual address of the function, whose second word contains a
11528 ;; pointer to its TOC, and whose third word contains a value to place in the
11529 ;; static chain register (r11). Note that if we load the static chain, our
11530 ;; "trampoline" need not have any executable code.
11532 (define_expand "call_indirect_aix32"
11533 [(set (match_dup 2)
11534 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
11535 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
11536 (reg:SI 2))
11537 (set (reg:SI 11)
11538 (mem:SI (plus:SI (match_dup 0)
11539 (const_int 8))))
11540 (parallel [(call (mem:SI (match_dup 2))
11541 (match_operand 1 "" ""))
11542 (use (mem:SI (plus:SI (match_dup 0) (const_int 4))))
11543 (use (reg:SI 11))
11544 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11545 (clobber (reg:SI LR_REGNO))])]
11546 "TARGET_32BIT"
11547 "
11548 { operands[2] = gen_reg_rtx (SImode); }")
11550 (define_expand "call_indirect_aix64"
11551 [(set (match_dup 2)
11552 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
11553 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
11554 (reg:DI 2))
11555 (set (reg:DI 11)
11556 (mem:DI (plus:DI (match_dup 0)
11557 (const_int 16))))
11558 (parallel [(call (mem:SI (match_dup 2))
11559 (match_operand 1 "" ""))
11560 (use (mem:DI (plus:DI (match_dup 0) (const_int 8))))
11561 (use (reg:DI 11))
11562 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11563 (clobber (reg:SI LR_REGNO))])]
11564 "TARGET_64BIT"
11565 "
11566 { operands[2] = gen_reg_rtx (DImode); }")
11568 (define_expand "call_value_indirect_aix32"
11569 [(set (match_dup 3)
11570 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
11571 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
11572 (reg:SI 2))
11573 (set (reg:SI 11)
11574 (mem:SI (plus:SI (match_dup 1)
11575 (const_int 8))))
11576 (parallel [(set (match_operand 0 "" "")
11577 (call (mem:SI (match_dup 3))
11578 (match_operand 2 "" "")))
11579 (use (mem:SI (plus:SI (match_dup 1) (const_int 4))))
11580 (use (reg:SI 11))
11581 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11582 (clobber (reg:SI LR_REGNO))])]
11583 "TARGET_32BIT"
11584 "
11585 { operands[3] = gen_reg_rtx (SImode); }")
11587 (define_expand "call_value_indirect_aix64"
11588 [(set (match_dup 3)
11589 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
11590 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
11591 (reg:DI 2))
11592 (set (reg:DI 11)
11593 (mem:DI (plus:DI (match_dup 1)
11594 (const_int 16))))
11595 (parallel [(set (match_operand 0 "" "")
11596 (call (mem:SI (match_dup 3))
11597 (match_operand 2 "" "")))
11598 (use (mem:DI (plus:DI (match_dup 1) (const_int 8))))
11599 (use (reg:DI 11))
11600 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11601 (clobber (reg:SI LR_REGNO))])]
11602 "TARGET_64BIT"
11603 "
11604 { operands[3] = gen_reg_rtx (DImode); }")
11606 ;; Now the definitions for the call and call_value insns
11607 (define_expand "call"
11608 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11609 (match_operand 1 "" ""))
11610 (use (match_operand 2 "" ""))
11611 (clobber (reg:SI LR_REGNO))])]
11612 ""
11613 "
11614 {
11615 #if TARGET_MACHO
11616 if (MACHOPIC_INDIRECT)
11617 operands[0] = machopic_indirect_call_target (operands[0]);
11618 #endif
11620 gcc_assert (GET_CODE (operands[0]) == MEM);
11621 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11623 operands[0] = XEXP (operands[0], 0);
11625 if (GET_CODE (operands[0]) != SYMBOL_REF
11626 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
11627 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
11628 {
11629 if (INTVAL (operands[2]) & CALL_LONG)
11630 operands[0] = rs6000_longcall_ref (operands[0]);
11632 switch (DEFAULT_ABI)
11633 {
11634 case ABI_V4:
11635 case ABI_DARWIN:
11636 operands[0] = force_reg (Pmode, operands[0]);
11637 break;
11639 case ABI_AIX:
11640 /* AIX function pointers are really pointers to a three word
11641 area. */
11642 emit_call_insn (TARGET_32BIT
11643 ? gen_call_indirect_aix32 (force_reg (SImode,
11644 operands[0]),
11645 operands[1])
11646 : gen_call_indirect_aix64 (force_reg (DImode,
11647 operands[0]),
11648 operands[1]));
11649 DONE;
11651 default:
11652 gcc_unreachable ();
11653 }
11654 }
11655 }")
11657 (define_expand "call_value"
11658 [(parallel [(set (match_operand 0 "" "")
11659 (call (mem:SI (match_operand 1 "address_operand" ""))
11660 (match_operand 2 "" "")))
11661 (use (match_operand 3 "" ""))
11662 (clobber (reg:SI LR_REGNO))])]
11663 ""
11664 "
11665 {
11666 #if TARGET_MACHO
11667 if (MACHOPIC_INDIRECT)
11668 operands[1] = machopic_indirect_call_target (operands[1]);
11669 #endif
11671 gcc_assert (GET_CODE (operands[1]) == MEM);
11672 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11674 operands[1] = XEXP (operands[1], 0);
11676 if (GET_CODE (operands[1]) != SYMBOL_REF
11677 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
11678 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
11679 {
11680 if (INTVAL (operands[3]) & CALL_LONG)
11681 operands[1] = rs6000_longcall_ref (operands[1]);
11683 switch (DEFAULT_ABI)
11684 {
11685 case ABI_V4:
11686 case ABI_DARWIN:
11687 operands[1] = force_reg (Pmode, operands[1]);
11688 break;
11690 case ABI_AIX:
11691 /* AIX function pointers are really pointers to a three word
11692 area. */
11693 emit_call_insn (TARGET_32BIT
11694 ? gen_call_value_indirect_aix32 (operands[0],
11695 force_reg (SImode,
11696 operands[1]),
11697 operands[2])
11698 : gen_call_value_indirect_aix64 (operands[0],
11699 force_reg (DImode,
11700 operands[1]),
11701 operands[2]));
11702 DONE;
11704 default:
11705 gcc_unreachable ();
11706 }
11707 }
11708 }")
11710 ;; Call to function in current module. No TOC pointer reload needed.
11711 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11712 ;; either the function was not prototyped, or it was prototyped as a
11713 ;; variable argument function. It is > 0 if FP registers were passed
11714 ;; and < 0 if they were not.
11716 (define_insn "*call_local32"
11717 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11718 (match_operand 1 "" "g,g"))
11719 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11720 (clobber (reg:SI LR_REGNO))]
11721 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11722 "*
11723 {
11724 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11725 output_asm_insn (\"crxor 6,6,6\", operands);
11727 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11728 output_asm_insn (\"creqv 6,6,6\", operands);
11730 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11731 }"
11732 [(set_attr "type" "branch")
11733 (set_attr "length" "4,8")])
11735 (define_insn "*call_local64"
11736 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11737 (match_operand 1 "" "g,g"))
11738 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11739 (clobber (reg:SI LR_REGNO))]
11740 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11741 "*
11742 {
11743 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11744 output_asm_insn (\"crxor 6,6,6\", operands);
11746 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11747 output_asm_insn (\"creqv 6,6,6\", operands);
11749 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11750 }"
11751 [(set_attr "type" "branch")
11752 (set_attr "length" "4,8")])
11754 (define_insn "*call_value_local32"
11755 [(set (match_operand 0 "" "")
11756 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11757 (match_operand 2 "" "g,g")))
11758 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11759 (clobber (reg:SI LR_REGNO))]
11760 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11761 "*
11762 {
11763 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11764 output_asm_insn (\"crxor 6,6,6\", operands);
11766 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11767 output_asm_insn (\"creqv 6,6,6\", operands);
11769 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11770 }"
11771 [(set_attr "type" "branch")
11772 (set_attr "length" "4,8")])
11775 (define_insn "*call_value_local64"
11776 [(set (match_operand 0 "" "")
11777 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11778 (match_operand 2 "" "g,g")))
11779 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11780 (clobber (reg:SI LR_REGNO))]
11781 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11782 "*
11783 {
11784 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11785 output_asm_insn (\"crxor 6,6,6\", operands);
11787 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11788 output_asm_insn (\"creqv 6,6,6\", operands);
11790 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11791 }"
11792 [(set_attr "type" "branch")
11793 (set_attr "length" "4,8")])
11795 ;; Call to function which may be in another module. Restore the TOC
11796 ;; pointer (r2) after the call unless this is System V.
11797 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11798 ;; either the function was not prototyped, or it was prototyped as a
11799 ;; variable argument function. It is > 0 if FP registers were passed
11800 ;; and < 0 if they were not.
11802 (define_insn_and_split "*call_indirect_nonlocal_aix32_internal"
11803 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
11804 (match_operand 1 "" "g,g"))
11805 (use (mem:SI (plus:SI (match_operand:SI 2 "register_operand" "b,b") (const_int 4))))
11806 (use (reg:SI 11))
11807 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11808 (clobber (reg:SI LR_REGNO))]
11809 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11810 "#"
11811 "&& reload_completed"
11812 [(set (reg:SI 2)
11813 (mem:SI (plus:SI (match_dup 2) (const_int 4))))
11814 (parallel [(call (mem:SI (match_dup 0))
11815 (match_dup 1))
11816 (use (reg:SI 2))
11817 (use (reg:SI 11))
11818 (set (reg:SI 2)
11819 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11820 (clobber (reg:SI LR_REGNO))])]
11821 ""
11822 [(set_attr "type" "jmpreg")
11823 (set_attr "length" "12")])
11825 (define_insn "*call_indirect_nonlocal_aix32"
11826 [(call (mem:SI (match_operand:SI 0 "register_operand" "c,*l"))
11827 (match_operand 1 "" "g,g"))
11828 (use (reg:SI 2))
11829 (use (reg:SI 11))
11830 (set (reg:SI 2)
11831 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11832 (clobber (reg:SI LR_REGNO))]
11833 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11834 "b%T0l\;{l|lwz} 2,20(1)"
11835 [(set_attr "type" "jmpreg")
11836 (set_attr "length" "8")])
11838 (define_insn "*call_nonlocal_aix32"
11839 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11840 (match_operand 1 "" "g"))
11841 (use (match_operand:SI 2 "immediate_operand" "O"))
11842 (clobber (reg:SI LR_REGNO))]
11843 "TARGET_32BIT
11844 && DEFAULT_ABI == ABI_AIX
11845 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11846 "bl %z0\;%."
11847 [(set_attr "type" "branch")
11848 (set_attr "length" "8")])
11850 (define_insn_and_split "*call_indirect_nonlocal_aix64_internal"
11851 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11852 (match_operand 1 "" "g,g"))
11853 (use (mem:DI (plus:DI (match_operand:DI 2 "register_operand" "b,b")
11854 (const_int 8))))
11855 (use (reg:DI 11))
11856 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11857 (clobber (reg:SI LR_REGNO))]
11858 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11859 "#"
11860 "&& reload_completed"
11861 [(set (reg:DI 2)
11862 (mem:DI (plus:DI (match_dup 2) (const_int 8))))
11863 (parallel [(call (mem:SI (match_dup 0))
11864 (match_dup 1))
11865 (use (reg:DI 2))
11866 (use (reg:DI 11))
11867 (set (reg:DI 2)
11868 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11869 (clobber (reg:SI LR_REGNO))])]
11870 ""
11871 [(set_attr "type" "jmpreg")
11872 (set_attr "length" "12")])
11874 (define_insn "*call_indirect_nonlocal_aix64"
11875 [(call (mem:SI (match_operand:DI 0 "register_operand" "c,*l"))
11876 (match_operand 1 "" "g,g"))
11877 (use (reg:DI 2))
11878 (use (reg:DI 11))
11879 (set (reg:DI 2)
11880 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11881 (clobber (reg:SI LR_REGNO))]
11882 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11883 "b%T0l\;ld 2,40(1)"
11884 [(set_attr "type" "jmpreg")
11885 (set_attr "length" "8")])
11887 (define_insn "*call_nonlocal_aix64"
11888 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11889 (match_operand 1 "" "g"))
11890 (use (match_operand:SI 2 "immediate_operand" "O"))
11891 (clobber (reg:SI LR_REGNO))]
11892 "TARGET_64BIT
11893 && DEFAULT_ABI == ABI_AIX
11894 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11895 "bl %z0\;%."
11896 [(set_attr "type" "branch")
11897 (set_attr "length" "8")])
11899 (define_insn_and_split "*call_value_indirect_nonlocal_aix32_internal"
11900 [(set (match_operand 0 "" "")
11901 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11902 (match_operand 2 "" "g,g")))
11903 (use (mem:SI (plus:SI (match_operand:SI 3 "register_operand" "b,b")
11904 (const_int 4))))
11905 (use (reg:SI 11))
11906 (use (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11907 (clobber (reg:SI LR_REGNO))]
11908 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
11909 "#"
11910 "&& reload_completed"
11911 [(set (reg:SI 2)
11912 (mem:SI (plus:SI (match_dup 3) (const_int 4))))
11913 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
11914 (match_dup 2)))
11915 (use (reg:SI 2))
11916 (use (reg:SI 11))
11917 (set (reg:SI 2)
11918 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11919 (clobber (reg:SI LR_REGNO))])]
11920 ""
11921 [(set_attr "type" "jmpreg")
11922 (set_attr "length" "12")])
11924 (define_insn "*call_value_indirect_nonlocal_aix32"
11925 [(set (match_operand 0 "" "")
11926 (call (mem:SI (match_operand:SI 1 "register_operand" "c,*l"))
11927 (match_operand 2 "" "g,g")))
11928 (use (reg:SI 2))
11929 (use (reg:SI 11))
11930 (set (reg:SI 2)
11931 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
11932 (clobber (reg:SI LR_REGNO))]
11933 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11934 "b%T1l\;{l|lwz} 2,20(1)"
11935 [(set_attr "type" "jmpreg")
11936 (set_attr "length" "8")])
11938 (define_insn "*call_value_nonlocal_aix32"
11939 [(set (match_operand 0 "" "")
11940 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11941 (match_operand 2 "" "g")))
11942 (use (match_operand:SI 3 "immediate_operand" "O"))
11943 (clobber (reg:SI LR_REGNO))]
11944 "TARGET_32BIT
11945 && DEFAULT_ABI == ABI_AIX
11946 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11947 "bl %z1\;%."
11948 [(set_attr "type" "branch")
11949 (set_attr "length" "8")])
11951 (define_insn_and_split "*call_value_indirect_nonlocal_aix64_internal"
11952 [(set (match_operand 0 "" "")
11953 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11954 (match_operand 2 "" "g,g")))
11955 (use (mem:DI (plus:DI (match_operand:DI 3 "register_operand" "b,b")
11956 (const_int 8))))
11957 (use (reg:DI 11))
11958 (use (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11959 (clobber (reg:SI LR_REGNO))]
11960 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
11961 "#"
11962 "&& reload_completed"
11963 [(set (reg:DI 2)
11964 (mem:DI (plus:DI (match_dup 3) (const_int 8))))
11965 (parallel [(set (match_dup 0) (call (mem:SI (match_dup 1))
11966 (match_dup 2)))
11967 (use (reg:DI 2))
11968 (use (reg:DI 11))
11969 (set (reg:DI 2)
11970 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11971 (clobber (reg:SI LR_REGNO))])]
11972 ""
11973 [(set_attr "type" "jmpreg")
11974 (set_attr "length" "12")])
11976 (define_insn "*call_value_indirect_nonlocal_aix64"
11977 [(set (match_operand 0 "" "")
11978 (call (mem:SI (match_operand:DI 1 "register_operand" "c,*l"))
11979 (match_operand 2 "" "g,g")))
11980 (use (reg:DI 2))
11981 (use (reg:DI 11))
11982 (set (reg:DI 2)
11983 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
11984 (clobber (reg:SI LR_REGNO))]
11985 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX && reload_completed"
11986 "b%T1l\;ld 2,40(1)"
11987 [(set_attr "type" "jmpreg")
11988 (set_attr "length" "8")])
11990 (define_insn "*call_value_nonlocal_aix64"
11991 [(set (match_operand 0 "" "")
11992 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11993 (match_operand 2 "" "g")))
11994 (use (match_operand:SI 3 "immediate_operand" "O"))
11995 (clobber (reg:SI LR_REGNO))]
11996 "TARGET_64BIT
11997 && DEFAULT_ABI == ABI_AIX
11998 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11999 "bl %z1\;%."
12000 [(set_attr "type" "branch")
12001 (set_attr "length" "8")])
12003 ;; A function pointer under System V is just a normal pointer
12004 ;; operands[0] is the function pointer
12005 ;; operands[1] is the stack size to clean up
12006 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
12007 ;; which indicates how to set cr1
12009 (define_insn "*call_indirect_nonlocal_sysv<mode>"
12010 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
12011 (match_operand 1 "" "g,g,g,g"))
12012 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
12013 (clobber (reg:SI LR_REGNO))]
12014 "DEFAULT_ABI == ABI_V4
12015 || DEFAULT_ABI == ABI_DARWIN"
12016 {
12017 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12018 output_asm_insn ("crxor 6,6,6", operands);
12020 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12021 output_asm_insn ("creqv 6,6,6", operands);
12023 return "b%T0l";
12024 }
12025 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12026 (set_attr "length" "4,4,8,8")])
12028 (define_insn_and_split "*call_nonlocal_sysv<mode>"
12029 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12030 (match_operand 1 "" "g,g"))
12031 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12032 (clobber (reg:SI LR_REGNO))]
12033 "(DEFAULT_ABI == ABI_DARWIN
12034 || (DEFAULT_ABI == ABI_V4
12035 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
12036 {
12037 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12038 output_asm_insn ("crxor 6,6,6", operands);
12040 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12041 output_asm_insn ("creqv 6,6,6", operands);
12043 #if TARGET_MACHO
12044 return output_call(insn, operands, 0, 2);
12045 #else
12046 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12047 {
12048 gcc_assert (!TARGET_SECURE_PLT);
12049 return "bl %z0@plt";
12050 }
12051 else
12052 return "bl %z0";
12053 #endif
12054 }
12055 "DEFAULT_ABI == ABI_V4
12056 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12057 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12058 [(parallel [(call (mem:SI (match_dup 0))
12059 (match_dup 1))
12060 (use (match_dup 2))
12061 (use (match_dup 3))
12062 (clobber (reg:SI LR_REGNO))])]
12063 {
12064 operands[3] = pic_offset_table_rtx;
12065 }
12066 [(set_attr "type" "branch,branch")
12067 (set_attr "length" "4,8")])
12069 (define_insn "*call_nonlocal_sysv_secure<mode>"
12070 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12071 (match_operand 1 "" "g,g"))
12072 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12073 (use (match_operand:SI 3 "register_operand" "r,r"))
12074 (clobber (reg:SI LR_REGNO))]
12075 "(DEFAULT_ABI == ABI_V4
12076 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
12077 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
12078 {
12079 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12080 output_asm_insn ("crxor 6,6,6", operands);
12082 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12083 output_asm_insn ("creqv 6,6,6", operands);
12085 if (flag_pic == 2)
12086 /* The magic 32768 offset here and in the other sysv call insns
12087 corresponds to the offset of r30 in .got2, as given by LCTOC1.
12088 See sysv4.h:toc_section. */
12089 return "bl %z0+32768@plt";
12090 else
12091 return "bl %z0@plt";
12092 }
12093 [(set_attr "type" "branch,branch")
12094 (set_attr "length" "4,8")])
12096 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
12097 [(set (match_operand 0 "" "")
12098 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
12099 (match_operand 2 "" "g,g,g,g")))
12100 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
12101 (clobber (reg:SI LR_REGNO))]
12102 "DEFAULT_ABI == ABI_V4
12103 || DEFAULT_ABI == ABI_DARWIN"
12104 {
12105 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12106 output_asm_insn ("crxor 6,6,6", operands);
12108 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12109 output_asm_insn ("creqv 6,6,6", operands);
12111 return "b%T1l";
12112 }
12113 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
12114 (set_attr "length" "4,4,8,8")])
12116 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
12117 [(set (match_operand 0 "" "")
12118 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12119 (match_operand 2 "" "g,g")))
12120 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12121 (clobber (reg:SI LR_REGNO))]
12122 "(DEFAULT_ABI == ABI_DARWIN
12123 || (DEFAULT_ABI == ABI_V4
12124 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
12125 {
12126 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12127 output_asm_insn ("crxor 6,6,6", operands);
12129 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12130 output_asm_insn ("creqv 6,6,6", operands);
12132 #if TARGET_MACHO
12133 return output_call(insn, operands, 1, 3);
12134 #else
12135 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12136 {
12137 gcc_assert (!TARGET_SECURE_PLT);
12138 return "bl %z1@plt";
12139 }
12140 else
12141 return "bl %z1";
12142 #endif
12143 }
12144 "DEFAULT_ABI == ABI_V4
12145 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12146 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12147 [(parallel [(set (match_dup 0)
12148 (call (mem:SI (match_dup 1))
12149 (match_dup 2)))
12150 (use (match_dup 3))
12151 (use (match_dup 4))
12152 (clobber (reg:SI LR_REGNO))])]
12153 {
12154 operands[4] = pic_offset_table_rtx;
12155 }
12156 [(set_attr "type" "branch,branch")
12157 (set_attr "length" "4,8")])
12159 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
12160 [(set (match_operand 0 "" "")
12161 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12162 (match_operand 2 "" "g,g")))
12163 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12164 (use (match_operand:SI 4 "register_operand" "r,r"))
12165 (clobber (reg:SI LR_REGNO))]
12166 "(DEFAULT_ABI == ABI_V4
12167 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
12168 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
12169 {
12170 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12171 output_asm_insn ("crxor 6,6,6", operands);
12173 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12174 output_asm_insn ("creqv 6,6,6", operands);
12176 if (flag_pic == 2)
12177 return "bl %z1+32768@plt";
12178 else
12179 return "bl %z1@plt";
12180 }
12181 [(set_attr "type" "branch,branch")
12182 (set_attr "length" "4,8")])
12184 ;; Call subroutine returning any type.
12185 (define_expand "untyped_call"
12186 [(parallel [(call (match_operand 0 "" "")
12187 (const_int 0))
12188 (match_operand 1 "" "")
12189 (match_operand 2 "" "")])]
12190 ""
12191 "
12192 {
12193 int i;
12195 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
12197 for (i = 0; i < XVECLEN (operands[2], 0); i++)
12198 {
12199 rtx set = XVECEXP (operands[2], 0, i);
12200 emit_move_insn (SET_DEST (set), SET_SRC (set));
12201 }
12203 /* The optimizer does not know that the call sets the function value
12204 registers we stored in the result block. We avoid problems by
12205 claiming that all hard registers are used and clobbered at this
12206 point. */
12207 emit_insn (gen_blockage ());
12209 DONE;
12210 }")
12212 ;; sibling call patterns
12213 (define_expand "sibcall"
12214 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
12215 (match_operand 1 "" ""))
12216 (use (match_operand 2 "" ""))
12217 (use (reg:SI LR_REGNO))
12218 (return)])]
12219 ""
12220 "
12221 {
12222 #if TARGET_MACHO
12223 if (MACHOPIC_INDIRECT)
12224 operands[0] = machopic_indirect_call_target (operands[0]);
12225 #endif
12227 gcc_assert (GET_CODE (operands[0]) == MEM);
12228 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
12230 operands[0] = XEXP (operands[0], 0);
12231 }")
12233 ;; this and similar patterns must be marked as using LR, otherwise
12234 ;; dataflow will try to delete the store into it. This is true
12235 ;; even when the actual reg to jump to is in CTR, when LR was
12236 ;; saved and restored around the PIC-setting BCL.
12237 (define_insn "*sibcall_local32"
12238 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
12239 (match_operand 1 "" "g,g"))
12240 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12241 (use (reg:SI LR_REGNO))
12242 (return)]
12243 "(INTVAL (operands[2]) & CALL_LONG) == 0"
12244 "*
12245 {
12246 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12247 output_asm_insn (\"crxor 6,6,6\", operands);
12249 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12250 output_asm_insn (\"creqv 6,6,6\", operands);
12252 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12253 }"
12254 [(set_attr "type" "branch")
12255 (set_attr "length" "4,8")])
12257 (define_insn "*sibcall_local64"
12258 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
12259 (match_operand 1 "" "g,g"))
12260 (use (match_operand:SI 2 "immediate_operand" "O,n"))
12261 (use (reg:SI LR_REGNO))
12262 (return)]
12263 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
12264 "*
12265 {
12266 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12267 output_asm_insn (\"crxor 6,6,6\", operands);
12269 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12270 output_asm_insn (\"creqv 6,6,6\", operands);
12272 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
12273 }"
12274 [(set_attr "type" "branch")
12275 (set_attr "length" "4,8")])
12277 (define_insn "*sibcall_value_local32"
12278 [(set (match_operand 0 "" "")
12279 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
12280 (match_operand 2 "" "g,g")))
12281 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12282 (use (reg:SI LR_REGNO))
12283 (return)]
12284 "(INTVAL (operands[3]) & CALL_LONG) == 0"
12285 "*
12286 {
12287 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12288 output_asm_insn (\"crxor 6,6,6\", operands);
12290 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12291 output_asm_insn (\"creqv 6,6,6\", operands);
12293 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12294 }"
12295 [(set_attr "type" "branch")
12296 (set_attr "length" "4,8")])
12299 (define_insn "*sibcall_value_local64"
12300 [(set (match_operand 0 "" "")
12301 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
12302 (match_operand 2 "" "g,g")))
12303 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12304 (use (reg:SI LR_REGNO))
12305 (return)]
12306 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
12307 "*
12308 {
12309 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
12310 output_asm_insn (\"crxor 6,6,6\", operands);
12312 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
12313 output_asm_insn (\"creqv 6,6,6\", operands);
12315 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
12316 }"
12317 [(set_attr "type" "branch")
12318 (set_attr "length" "4,8")])
12320 (define_insn "*sibcall_nonlocal_aix32"
12321 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
12322 (match_operand 1 "" "g"))
12323 (use (match_operand:SI 2 "immediate_operand" "O"))
12324 (use (reg:SI LR_REGNO))
12325 (return)]
12326 "TARGET_32BIT
12327 && DEFAULT_ABI == ABI_AIX
12328 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12329 "b %z0"
12330 [(set_attr "type" "branch")
12331 (set_attr "length" "4")])
12333 (define_insn "*sibcall_nonlocal_aix64"
12334 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
12335 (match_operand 1 "" "g"))
12336 (use (match_operand:SI 2 "immediate_operand" "O"))
12337 (use (reg:SI LR_REGNO))
12338 (return)]
12339 "TARGET_64BIT
12340 && DEFAULT_ABI == ABI_AIX
12341 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12342 "b %z0"
12343 [(set_attr "type" "branch")
12344 (set_attr "length" "4")])
12346 (define_insn "*sibcall_value_nonlocal_aix32"
12347 [(set (match_operand 0 "" "")
12348 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
12349 (match_operand 2 "" "g")))
12350 (use (match_operand:SI 3 "immediate_operand" "O"))
12351 (use (reg:SI LR_REGNO))
12352 (return)]
12353 "TARGET_32BIT
12354 && DEFAULT_ABI == ABI_AIX
12355 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12356 "b %z1"
12357 [(set_attr "type" "branch")
12358 (set_attr "length" "4")])
12360 (define_insn "*sibcall_value_nonlocal_aix64"
12361 [(set (match_operand 0 "" "")
12362 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
12363 (match_operand 2 "" "g")))
12364 (use (match_operand:SI 3 "immediate_operand" "O"))
12365 (use (reg:SI LR_REGNO))
12366 (return)]
12367 "TARGET_64BIT
12368 && DEFAULT_ABI == ABI_AIX
12369 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12370 "b %z1"
12371 [(set_attr "type" "branch")
12372 (set_attr "length" "4")])
12374 (define_insn "*sibcall_nonlocal_sysv<mode>"
12375 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
12376 (match_operand 1 "" ""))
12377 (use (match_operand 2 "immediate_operand" "O,n"))
12378 (use (reg:SI LR_REGNO))
12379 (return)]
12380 "(DEFAULT_ABI == ABI_DARWIN
12381 || DEFAULT_ABI == ABI_V4)
12382 && (INTVAL (operands[2]) & CALL_LONG) == 0"
12383 "*
12384 {
12385 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12386 output_asm_insn (\"crxor 6,6,6\", operands);
12388 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12389 output_asm_insn (\"creqv 6,6,6\", operands);
12391 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12392 {
12393 gcc_assert (!TARGET_SECURE_PLT);
12394 return \"b %z0@plt\";
12395 }
12396 else
12397 return \"b %z0\";
12398 }"
12399 [(set_attr "type" "branch,branch")
12400 (set_attr "length" "4,8")])
12402 (define_expand "sibcall_value"
12403 [(parallel [(set (match_operand 0 "register_operand" "")
12404 (call (mem:SI (match_operand 1 "address_operand" ""))
12405 (match_operand 2 "" "")))
12406 (use (match_operand 3 "" ""))
12407 (use (reg:SI LR_REGNO))
12408 (return)])]
12409 ""
12410 "
12411 {
12412 #if TARGET_MACHO
12413 if (MACHOPIC_INDIRECT)
12414 operands[1] = machopic_indirect_call_target (operands[1]);
12415 #endif
12417 gcc_assert (GET_CODE (operands[1]) == MEM);
12418 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
12420 operands[1] = XEXP (operands[1], 0);
12421 }")
12423 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
12424 [(set (match_operand 0 "" "")
12425 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
12426 (match_operand 2 "" "")))
12427 (use (match_operand:SI 3 "immediate_operand" "O,n"))
12428 (use (reg:SI LR_REGNO))
12429 (return)]
12430 "(DEFAULT_ABI == ABI_DARWIN
12431 || DEFAULT_ABI == ABI_V4)
12432 && (INTVAL (operands[3]) & CALL_LONG) == 0"
12433 "*
12434 {
12435 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
12436 output_asm_insn (\"crxor 6,6,6\", operands);
12438 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
12439 output_asm_insn (\"creqv 6,6,6\", operands);
12441 if (DEFAULT_ABI == ABI_V4 && flag_pic)
12442 {
12443 gcc_assert (!TARGET_SECURE_PLT);
12444 return \"b %z1@plt\";
12445 }
12446 else
12447 return \"b %z1\";
12448 }"
12449 [(set_attr "type" "branch,branch")
12450 (set_attr "length" "4,8")])
12452 (define_expand "sibcall_epilogue"
12453 [(use (const_int 0))]
12454 "TARGET_SCHED_PROLOG"
12455 "
12456 {
12457 rs6000_emit_epilogue (TRUE);
12458 DONE;
12459 }")
12461 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
12462 ;; all of memory. This blocks insns from being moved across this point.
12464 (define_insn "blockage"
12465 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
12466 ""
12467 "")
12469 (define_insn "probe_stack"
12470 [(set (match_operand 0 "memory_operand" "=m")
12471 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
12472 ""
12473 "{st%U0%X0|stw%U0%X0} 0,%0"
12474 [(set_attr "type" "store")
12475 (set_attr "length" "4")])
12476 \f
12477 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
12478 ;; signed & unsigned, and one type of branch.
12479 ;;
12480 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
12481 ;; insns, and branches.
12483 (define_expand "cbranch<mode>4"
12484 [(use (match_operator 0 "rs6000_cbranch_operator"
12485 [(match_operand:GPR 1 "gpc_reg_operand" "")
12486 (match_operand:GPR 2 "reg_or_short_operand" "")]))
12487 (use (match_operand 3 ""))]
12488 ""
12489 "
12490 {
12491 /* Take care of the possibility that operands[2] might be negative but
12492 this might be a logical operation. That insn doesn't exist. */
12493 if (GET_CODE (operands[2]) == CONST_INT
12494 && INTVAL (operands[2]) < 0)
12495 {
12496 operands[2] = force_reg (<MODE>mode, operands[2]);
12497 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
12498 GET_MODE (operands[0]),
12499 operands[1], operands[2]);
12500 }
12502 rs6000_emit_cbranch (<MODE>mode, operands);
12503 DONE;
12504 }")
12506 (define_expand "cbranch<mode>4"
12507 [(use (match_operator 0 "rs6000_cbranch_operator"
12508 [(match_operand:FP 1 "gpc_reg_operand" "")
12509 (match_operand:FP 2 "gpc_reg_operand" "")]))
12510 (use (match_operand 3 ""))]
12511 ""
12512 "
12513 {
12514 rs6000_emit_cbranch (<MODE>mode, operands);
12515 DONE;
12516 }")
12518 (define_expand "cstore<mode>4"
12519 [(use (match_operator 1 "rs6000_cbranch_operator"
12520 [(match_operand:GPR 2 "gpc_reg_operand" "")
12521 (match_operand:GPR 3 "reg_or_short_operand" "")]))
12522 (clobber (match_operand:SI 0 "register_operand"))]
12523 ""
12524 "
12525 {
12526 /* Take care of the possibility that operands[3] might be negative but
12527 this might be a logical operation. That insn doesn't exist. */
12528 if (GET_CODE (operands[3]) == CONST_INT
12529 && INTVAL (operands[3]) < 0)
12530 {
12531 operands[3] = force_reg (<MODE>mode, operands[3]);
12532 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
12533 GET_MODE (operands[1]),
12534 operands[2], operands[3]);
12535 }
12537 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
12538 For SEQ, likewise, except that comparisons with zero should be done
12539 with an scc insns. However, due to the order that combine see the
12540 resulting insns, we must, in fact, allow SEQ for integers. Fail in
12541 the cases we don't want to handle or are best handled by portable
12542 code. */
12543 if (GET_CODE (operands[1]) == NE)
12544 FAIL;
12545 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
12546 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
12547 && operands[3] == const0_rtx)
12548 FAIL;
12549 rs6000_emit_sCOND (<MODE>mode, operands);
12550 DONE;
12551 }")
12553 (define_expand "cstore<mode>4"
12554 [(use (match_operator 1 "rs6000_cbranch_operator"
12555 [(match_operand:FP 2 "gpc_reg_operand" "")
12556 (match_operand:FP 3 "gpc_reg_operand" "")]))
12557 (clobber (match_operand:SI 0 "register_operand"))]
12558 ""
12559 "
12560 {
12561 rs6000_emit_sCOND (<MODE>mode, operands);
12562 DONE;
12563 }")
12566 (define_expand "stack_protect_set"
12567 [(match_operand 0 "memory_operand" "")
12568 (match_operand 1 "memory_operand" "")]
12569 ""
12570 {
12571 #ifdef TARGET_THREAD_SSP_OFFSET
12572 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12573 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12574 operands[1] = gen_rtx_MEM (Pmode, addr);
12575 #endif
12576 if (TARGET_64BIT)
12577 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
12578 else
12579 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
12580 DONE;
12581 })
12583 (define_insn "stack_protect_setsi"
12584 [(set (match_operand:SI 0 "memory_operand" "=m")
12585 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12586 (set (match_scratch:SI 2 "=&r") (const_int 0))]
12587 "TARGET_32BIT"
12588 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
12589 [(set_attr "type" "three")
12590 (set_attr "length" "12")])
12592 (define_insn "stack_protect_setdi"
12593 [(set (match_operand:DI 0 "memory_operand" "=m")
12594 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")] UNSPEC_SP_SET))
12595 (set (match_scratch:DI 2 "=&r") (const_int 0))]
12596 "TARGET_64BIT"
12597 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
12598 [(set_attr "type" "three")
12599 (set_attr "length" "12")])
12601 (define_expand "stack_protect_test"
12602 [(match_operand 0 "memory_operand" "")
12603 (match_operand 1 "memory_operand" "")
12604 (match_operand 2 "" "")]
12605 ""
12606 {
12607 rtx test, op0, op1;
12608 #ifdef TARGET_THREAD_SSP_OFFSET
12609 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
12610 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
12611 operands[1] = gen_rtx_MEM (Pmode, addr);
12612 #endif
12613 op0 = operands[0];
12614 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
12615 test = gen_rtx_EQ (VOIDmode, op0, op1);
12616 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
12617 DONE;
12618 })
12620 (define_insn "stack_protect_testsi"
12621 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12622 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
12623 (match_operand:SI 2 "memory_operand" "m,m")]
12624 UNSPEC_SP_TEST))
12625 (set (match_scratch:SI 4 "=r,r") (const_int 0))
12626 (clobber (match_scratch:SI 3 "=&r,&r"))]
12627 "TARGET_32BIT"
12628 "@
12629 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12630 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12631 [(set_attr "length" "16,20")])
12633 (define_insn "stack_protect_testdi"
12634 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
12635 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "m,m")
12636 (match_operand:DI 2 "memory_operand" "m,m")]
12637 UNSPEC_SP_TEST))
12638 (set (match_scratch:DI 4 "=r,r") (const_int 0))
12639 (clobber (match_scratch:DI 3 "=&r,&r"))]
12640 "TARGET_64BIT"
12641 "@
12642 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
12643 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
12644 [(set_attr "length" "16,20")])
12646 \f
12647 ;; Here are the actual compare insns.
12648 (define_insn "*cmp<mode>_internal1"
12649 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
12650 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
12651 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
12652 ""
12653 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
12654 [(set_attr "type" "cmp")])
12656 ;; If we are comparing a register for equality with a large constant,
12657 ;; we can do this with an XOR followed by a compare. But this is profitable
12658 ;; only if the large constant is only used for the comparison (and in this
12659 ;; case we already have a register to reuse as scratch).
12660 ;;
12661 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
12662 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
12664 (define_peephole2
12665 [(set (match_operand:SI 0 "register_operand")
12666 (match_operand:SI 1 "logical_const_operand" ""))
12667 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
12668 [(match_dup 0)
12669 (match_operand:SI 2 "logical_const_operand" "")]))
12670 (set (match_operand:CC 4 "cc_reg_operand" "")
12671 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
12672 (match_dup 0)))
12673 (set (pc)
12674 (if_then_else (match_operator 6 "equality_operator"
12675 [(match_dup 4) (const_int 0)])
12676 (match_operand 7 "" "")
12677 (match_operand 8 "" "")))]
12678 "peep2_reg_dead_p (3, operands[0])
12679 && peep2_reg_dead_p (4, operands[4])"
12680 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
12681 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
12682 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
12684 {
12685 /* Get the constant we are comparing against, and see what it looks like
12686 when sign-extended from 16 to 32 bits. Then see what constant we could
12687 XOR with SEXTC to get the sign-extended value. */
12688 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
12689 SImode,
12690 operands[1], operands[2]);
12691 HOST_WIDE_INT c = INTVAL (cnst);
12692 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
12693 HOST_WIDE_INT xorv = c ^ sextc;
12695 operands[9] = GEN_INT (xorv);
12696 operands[10] = GEN_INT (sextc);
12697 })
12699 (define_insn "*cmpsi_internal2"
12700 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12701 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12702 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
12703 ""
12704 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
12705 [(set_attr "type" "cmp")])
12707 (define_insn "*cmpdi_internal2"
12708 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
12709 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
12710 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
12711 ""
12712 "cmpld%I2 %0,%1,%b2"
12713 [(set_attr "type" "cmp")])
12715 ;; The following two insns don't exist as single insns, but if we provide
12716 ;; them, we can swap an add and compare, which will enable us to overlap more
12717 ;; of the required delay between a compare and branch. We generate code for
12718 ;; them by splitting.
12720 (define_insn ""
12721 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12722 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
12723 (match_operand:SI 2 "short_cint_operand" "i")))
12724 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12725 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12726 ""
12727 "#"
12728 [(set_attr "length" "8")])
12730 (define_insn ""
12731 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
12732 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
12733 (match_operand:SI 2 "u_short_cint_operand" "i")))
12734 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
12735 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
12736 ""
12737 "#"
12738 [(set_attr "length" "8")])
12740 (define_split
12741 [(set (match_operand:CC 3 "cc_reg_operand" "")
12742 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
12743 (match_operand:SI 2 "short_cint_operand" "")))
12744 (set (match_operand:SI 0 "gpc_reg_operand" "")
12745 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12746 ""
12747 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
12748 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12750 (define_split
12751 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
12752 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
12753 (match_operand:SI 2 "u_short_cint_operand" "")))
12754 (set (match_operand:SI 0 "gpc_reg_operand" "")
12755 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12756 ""
12757 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
12758 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12760 (define_insn "*cmpsf_internal1"
12761 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12762 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
12763 (match_operand:SF 2 "gpc_reg_operand" "f")))]
12764 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
12765 "fcmpu %0,%1,%2"
12766 [(set_attr "type" "fpcompare")])
12768 (define_insn "*cmpdf_internal1"
12769 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12770 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
12771 (match_operand:DF 2 "gpc_reg_operand" "d")))]
12772 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
12773 && !VECTOR_UNIT_VSX_P (DFmode)"
12774 "fcmpu %0,%1,%2"
12775 [(set_attr "type" "fpcompare")])
12777 ;; Only need to compare second words if first words equal
12778 (define_insn "*cmptf_internal1"
12779 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12780 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12781 (match_operand:TF 2 "gpc_reg_operand" "d")))]
12782 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
12783 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12784 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
12785 [(set_attr "type" "fpcompare")
12786 (set_attr "length" "12")])
12788 (define_insn_and_split "*cmptf_internal2"
12789 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12790 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12791 (match_operand:TF 2 "gpc_reg_operand" "d")))
12792 (clobber (match_scratch:DF 3 "=d"))
12793 (clobber (match_scratch:DF 4 "=d"))
12794 (clobber (match_scratch:DF 5 "=d"))
12795 (clobber (match_scratch:DF 6 "=d"))
12796 (clobber (match_scratch:DF 7 "=d"))
12797 (clobber (match_scratch:DF 8 "=d"))
12798 (clobber (match_scratch:DF 9 "=d"))
12799 (clobber (match_scratch:DF 10 "=d"))]
12800 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
12801 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12802 "#"
12803 "&& reload_completed"
12804 [(set (match_dup 3) (match_dup 13))
12805 (set (match_dup 4) (match_dup 14))
12806 (set (match_dup 9) (abs:DF (match_dup 5)))
12807 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
12808 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
12809 (label_ref (match_dup 11))
12810 (pc)))
12811 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
12812 (set (pc) (label_ref (match_dup 12)))
12813 (match_dup 11)
12814 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
12815 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
12816 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
12817 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
12818 (match_dup 12)]
12819 {
12820 REAL_VALUE_TYPE rv;
12821 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
12822 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
12824 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
12825 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
12826 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12827 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12828 operands[11] = gen_label_rtx ();
12829 operands[12] = gen_label_rtx ();
12830 real_inf (&rv);
12831 operands[13] = force_const_mem (DFmode,
12832 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12833 operands[14] = force_const_mem (DFmode,
12834 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12835 DFmode));
12836 if (TARGET_TOC)
12837 {
12838 operands[13] = gen_const_mem (DFmode,
12839 create_TOC_reference (XEXP (operands[13], 0)));
12840 operands[14] = gen_const_mem (DFmode,
12841 create_TOC_reference (XEXP (operands[14], 0)));
12842 set_mem_alias_set (operands[13], get_TOC_alias_set ());
12843 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12844 }
12845 })
12846 \f
12847 ;; Now we have the scc insns. We can do some combinations because of the
12848 ;; way the machine works.
12849 ;;
12850 ;; Note that this is probably faster if we can put an insn between the
12851 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12852 ;; cases the insns below which don't use an intermediate CR field will
12853 ;; be used instead.
12854 (define_insn ""
12855 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12856 (match_operator:SI 1 "scc_comparison_operator"
12857 [(match_operand 2 "cc_reg_operand" "y")
12858 (const_int 0)]))]
12859 ""
12860 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12861 [(set (attr "type")
12862 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12863 (const_string "mfcrf")
12864 ]
12865 (const_string "mfcr")))
12866 (set_attr "length" "8")])
12868 ;; Same as above, but get the GT bit.
12869 (define_insn "move_from_CR_gt_bit"
12870 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12871 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12872 "TARGET_HARD_FLOAT && !TARGET_FPRS"
12873 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
12874 [(set_attr "type" "mfcr")
12875 (set_attr "length" "8")])
12877 ;; Same as above, but get the OV/ORDERED bit.
12878 (define_insn "move_from_CR_ov_bit"
12879 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12880 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
12881 "TARGET_ISEL"
12882 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
12883 [(set_attr "type" "mfcr")
12884 (set_attr "length" "8")])
12886 (define_insn ""
12887 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12888 (match_operator:DI 1 "scc_comparison_operator"
12889 [(match_operand 2 "cc_reg_operand" "y")
12890 (const_int 0)]))]
12891 "TARGET_POWERPC64"
12892 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12893 [(set (attr "type")
12894 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12895 (const_string "mfcrf")
12896 ]
12897 (const_string "mfcr")))
12898 (set_attr "length" "8")])
12900 (define_insn ""
12901 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12902 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12903 [(match_operand 2 "cc_reg_operand" "y,y")
12904 (const_int 0)])
12905 (const_int 0)))
12906 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12907 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12908 "TARGET_32BIT"
12909 "@
12910 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
12911 #"
12912 [(set_attr "type" "delayed_compare")
12913 (set_attr "length" "8,16")])
12915 (define_split
12916 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12917 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12918 [(match_operand 2 "cc_reg_operand" "")
12919 (const_int 0)])
12920 (const_int 0)))
12921 (set (match_operand:SI 3 "gpc_reg_operand" "")
12922 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12923 "TARGET_32BIT && reload_completed"
12924 [(set (match_dup 3)
12925 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12926 (set (match_dup 0)
12927 (compare:CC (match_dup 3)
12928 (const_int 0)))]
12929 "")
12931 (define_insn ""
12932 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12933 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12934 [(match_operand 2 "cc_reg_operand" "y")
12935 (const_int 0)])
12936 (match_operand:SI 3 "const_int_operand" "n")))]
12937 ""
12938 "*
12939 {
12940 int is_bit = ccr_bit (operands[1], 1);
12941 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12942 int count;
12944 if (is_bit >= put_bit)
12945 count = is_bit - put_bit;
12946 else
12947 count = 32 - (put_bit - is_bit);
12949 operands[4] = GEN_INT (count);
12950 operands[5] = GEN_INT (put_bit);
12952 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
12953 }"
12954 [(set (attr "type")
12955 (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))
12956 (const_string "mfcrf")
12957 ]
12958 (const_string "mfcr")))
12959 (set_attr "length" "8")])
12961 (define_insn ""
12962 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12963 (compare:CC
12964 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12965 [(match_operand 2 "cc_reg_operand" "y,y")
12966 (const_int 0)])
12967 (match_operand:SI 3 "const_int_operand" "n,n"))
12968 (const_int 0)))
12969 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
12970 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12971 (match_dup 3)))]
12972 ""
12973 "*
12974 {
12975 int is_bit = ccr_bit (operands[1], 1);
12976 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12977 int count;
12979 /* Force split for non-cc0 compare. */
12980 if (which_alternative == 1)
12981 return \"#\";
12983 if (is_bit >= put_bit)
12984 count = is_bit - put_bit;
12985 else
12986 count = 32 - (put_bit - is_bit);
12988 operands[5] = GEN_INT (count);
12989 operands[6] = GEN_INT (put_bit);
12991 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
12992 }"
12993 [(set_attr "type" "delayed_compare")
12994 (set_attr "length" "8,16")])
12996 (define_split
12997 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12998 (compare:CC
12999 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
13000 [(match_operand 2 "cc_reg_operand" "")
13001 (const_int 0)])
13002 (match_operand:SI 3 "const_int_operand" ""))
13003 (const_int 0)))
13004 (set (match_operand:SI 4 "gpc_reg_operand" "")
13005 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13006 (match_dup 3)))]
13007 "reload_completed"
13008 [(set (match_dup 4)
13009 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
13010 (match_dup 3)))
13011 (set (match_dup 0)
13012 (compare:CC (match_dup 4)
13013 (const_int 0)))]
13014 "")
13016 ;; There is a 3 cycle delay between consecutive mfcr instructions
13017 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
13019 (define_peephole
13020 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13021 (match_operator:SI 1 "scc_comparison_operator"
13022 [(match_operand 2 "cc_reg_operand" "y")
13023 (const_int 0)]))
13024 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
13025 (match_operator:SI 4 "scc_comparison_operator"
13026 [(match_operand 5 "cc_reg_operand" "y")
13027 (const_int 0)]))]
13028 "REGNO (operands[2]) != REGNO (operands[5])"
13029 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13030 [(set_attr "type" "mfcr")
13031 (set_attr "length" "12")])
13033 (define_peephole
13034 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13035 (match_operator:DI 1 "scc_comparison_operator"
13036 [(match_operand 2 "cc_reg_operand" "y")
13037 (const_int 0)]))
13038 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
13039 (match_operator:DI 4 "scc_comparison_operator"
13040 [(match_operand 5 "cc_reg_operand" "y")
13041 (const_int 0)]))]
13042 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
13043 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
13044 [(set_attr "type" "mfcr")
13045 (set_attr "length" "12")])
13047 ;; There are some scc insns that can be done directly, without a compare.
13048 ;; These are faster because they don't involve the communications between
13049 ;; the FXU and branch units. In fact, we will be replacing all of the
13050 ;; integer scc insns here or in the portable methods in emit_store_flag.
13051 ;;
13052 ;; Also support (neg (scc ..)) since that construct is used to replace
13053 ;; branches, (plus (scc ..) ..) since that construct is common and
13054 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
13055 ;; cases where it is no more expensive than (neg (scc ..)).
13057 ;; Have reload force a constant into a register for the simple insns that
13058 ;; otherwise won't accept constants. We do this because it is faster than
13059 ;; the cmp/mfcr sequence we would otherwise generate.
13061 (define_mode_attr scc_eq_op2 [(SI "rKLI")
13062 (DI "rKJI")])
13064 (define_insn_and_split "*eq<mode>"
13065 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
13066 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
13067 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
13068 "!TARGET_POWER"
13069 "#"
13070 "!TARGET_POWER"
13071 [(set (match_dup 0)
13072 (clz:GPR (match_dup 3)))
13073 (set (match_dup 0)
13074 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
13075 {
13076 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13077 {
13078 /* Use output operand as intermediate. */
13079 operands[3] = operands[0];
13081 if (logical_operand (operands[2], <MODE>mode))
13082 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13083 gen_rtx_XOR (<MODE>mode,
13084 operands[1], operands[2])));
13085 else
13086 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13087 gen_rtx_PLUS (<MODE>mode, operands[1],
13088 negate_rtx (<MODE>mode,
13089 operands[2]))));
13090 }
13091 else
13092 operands[3] = operands[1];
13094 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13095 })
13097 (define_insn_and_split "*eq<mode>_compare"
13098 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
13099 (compare:CC
13100 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
13101 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
13102 (const_int 0)))
13103 (set (match_operand:P 0 "gpc_reg_operand" "=r")
13104 (eq:P (match_dup 1) (match_dup 2)))]
13105 "!TARGET_POWER && optimize_size"
13106 "#"
13107 "!TARGET_POWER && optimize_size"
13108 [(set (match_dup 0)
13109 (clz:P (match_dup 4)))
13110 (parallel [(set (match_dup 3)
13111 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
13112 (const_int 0)))
13113 (set (match_dup 0)
13114 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
13115 {
13116 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13117 {
13118 /* Use output operand as intermediate. */
13119 operands[4] = operands[0];
13121 if (logical_operand (operands[2], <MODE>mode))
13122 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13123 gen_rtx_XOR (<MODE>mode,
13124 operands[1], operands[2])));
13125 else
13126 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
13127 gen_rtx_PLUS (<MODE>mode, operands[1],
13128 negate_rtx (<MODE>mode,
13129 operands[2]))));
13130 }
13131 else
13132 operands[4] = operands[1];
13134 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
13135 })
13137 (define_insn "*eqsi_power"
13138 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
13139 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13140 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
13141 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
13142 "TARGET_POWER"
13143 "@
13144 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13145 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
13146 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13147 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
13148 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
13149 [(set_attr "type" "three,two,three,three,three")
13150 (set_attr "length" "12,8,12,12,12")])
13152 ;; We have insns of the form shown by the first define_insn below. If
13153 ;; there is something inside the comparison operation, we must split it.
13154 (define_split
13155 [(set (match_operand:SI 0 "gpc_reg_operand" "")
13156 (plus:SI (match_operator 1 "comparison_operator"
13157 [(match_operand:SI 2 "" "")
13158 (match_operand:SI 3
13159 "reg_or_cint_operand" "")])
13160 (match_operand:SI 4 "gpc_reg_operand" "")))
13161 (clobber (match_operand:SI 5 "register_operand" ""))]
13162 "! gpc_reg_operand (operands[2], SImode)"
13163 [(set (match_dup 5) (match_dup 2))
13164 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
13165 (match_dup 4)))])
13167 (define_insn "*plus_eqsi"
13168 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
13169 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
13170 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
13171 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
13172 "TARGET_32BIT"
13173 "@
13174 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13175 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
13176 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13177 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13178 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
13179 [(set_attr "type" "three,two,three,three,three")
13180 (set_attr "length" "12,8,12,12,12")])
13182 (define_insn "*compare_plus_eqsi"
13183 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13184 (compare:CC
13185 (plus:SI
13186 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13187 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13188 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13189 (const_int 0)))
13190 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
13191 "TARGET_32BIT && optimize_size"
13192 "@
13193 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13194 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
13195 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13196 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13197 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13198 #
13199 #
13200 #
13201 #
13202 #"
13203 [(set_attr "type" "compare")
13204 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13206 (define_split
13207 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13208 (compare:CC
13209 (plus:SI
13210 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13211 (match_operand:SI 2 "scc_eq_operand" ""))
13212 (match_operand:SI 3 "gpc_reg_operand" ""))
13213 (const_int 0)))
13214 (clobber (match_scratch:SI 4 ""))]
13215 "TARGET_32BIT && optimize_size && reload_completed"
13216 [(set (match_dup 4)
13217 (plus:SI (eq:SI (match_dup 1)
13218 (match_dup 2))
13219 (match_dup 3)))
13220 (set (match_dup 0)
13221 (compare:CC (match_dup 4)
13222 (const_int 0)))]
13223 "")
13225 (define_insn "*plus_eqsi_compare"
13226 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
13227 (compare:CC
13228 (plus:SI
13229 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
13230 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
13231 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
13232 (const_int 0)))
13233 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
13234 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13235 "TARGET_32BIT && optimize_size"
13236 "@
13237 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13238 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
13239 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13240 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13241 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13242 #
13243 #
13244 #
13245 #
13246 #"
13247 [(set_attr "type" "compare")
13248 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
13250 (define_split
13251 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13252 (compare:CC
13253 (plus:SI
13254 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
13255 (match_operand:SI 2 "scc_eq_operand" ""))
13256 (match_operand:SI 3 "gpc_reg_operand" ""))
13257 (const_int 0)))
13258 (set (match_operand:SI 0 "gpc_reg_operand" "")
13259 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13260 "TARGET_32BIT && optimize_size && reload_completed"
13261 [(set (match_dup 0)
13262 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13263 (set (match_dup 4)
13264 (compare:CC (match_dup 0)
13265 (const_int 0)))]
13266 "")
13268 (define_insn "*neg_eq0<mode>"
13269 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13270 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
13271 (const_int 0))))]
13272 ""
13273 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
13274 [(set_attr "type" "two")
13275 (set_attr "length" "8")])
13277 (define_insn_and_split "*neg_eq<mode>"
13278 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13279 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
13280 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
13281 ""
13282 "#"
13283 ""
13284 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
13285 {
13286 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
13287 {
13288 /* Use output operand as intermediate. */
13289 operands[3] = operands[0];
13291 if (logical_operand (operands[2], <MODE>mode))
13292 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13293 gen_rtx_XOR (<MODE>mode,
13294 operands[1], operands[2])));
13295 else
13296 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
13297 gen_rtx_PLUS (<MODE>mode, operands[1],
13298 negate_rtx (<MODE>mode,
13299 operands[2]))));
13300 }
13301 else
13302 operands[3] = operands[1];
13303 })
13305 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
13306 ;; since it nabs/sr is just as fast.
13307 (define_insn "*ne0si"
13308 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13309 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13310 (const_int 31)))
13311 (clobber (match_scratch:SI 2 "=&r"))]
13312 "! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
13313 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
13314 [(set_attr "type" "two")
13315 (set_attr "length" "8")])
13317 (define_insn "*ne0di"
13318 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13319 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13320 (const_int 63)))
13321 (clobber (match_scratch:DI 2 "=&r"))]
13322 "TARGET_64BIT"
13323 "addic %2,%1,-1\;subfe %0,%2,%1"
13324 [(set_attr "type" "two")
13325 (set_attr "length" "8")])
13327 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
13328 (define_insn "*plus_ne0si"
13329 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13330 (plus:SI (lshiftrt:SI
13331 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
13332 (const_int 31))
13333 (match_operand:SI 2 "gpc_reg_operand" "r")))
13334 (clobber (match_scratch:SI 3 "=&r"))]
13335 "TARGET_32BIT"
13336 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
13337 [(set_attr "type" "two")
13338 (set_attr "length" "8")])
13340 (define_insn "*plus_ne0di"
13341 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13342 (plus:DI (lshiftrt:DI
13343 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
13344 (const_int 63))
13345 (match_operand:DI 2 "gpc_reg_operand" "r")))
13346 (clobber (match_scratch:DI 3 "=&r"))]
13347 "TARGET_64BIT"
13348 "addic %3,%1,-1\;addze %0,%2"
13349 [(set_attr "type" "two")
13350 (set_attr "length" "8")])
13352 (define_insn "*compare_plus_ne0si"
13353 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13354 (compare:CC
13355 (plus:SI (lshiftrt:SI
13356 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
13357 (const_int 31))
13358 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13359 (const_int 0)))
13360 (clobber (match_scratch:SI 3 "=&r,&r"))
13361 (clobber (match_scratch:SI 4 "=X,&r"))]
13362 "TARGET_32BIT"
13363 "@
13364 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
13365 #"
13366 [(set_attr "type" "compare")
13367 (set_attr "length" "8,12")])
13369 (define_split
13370 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13371 (compare:CC
13372 (plus:SI (lshiftrt:SI
13373 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
13374 (const_int 31))
13375 (match_operand:SI 2 "gpc_reg_operand" ""))
13376 (const_int 0)))
13377 (clobber (match_scratch:SI 3 ""))
13378 (clobber (match_scratch:SI 4 ""))]
13379 "TARGET_32BIT && reload_completed"
13380 [(parallel [(set (match_dup 3)
13381 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
13382 (const_int 31))
13383 (match_dup 2)))
13384 (clobber (match_dup 4))])
13385 (set (match_dup 0)
13386 (compare:CC (match_dup 3)
13387 (const_int 0)))]
13388 "")
13390 (define_insn "*compare_plus_ne0di"
13391 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13392 (compare:CC
13393 (plus:DI (lshiftrt:DI
13394 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
13395 (const_int 63))
13396 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13397 (const_int 0)))
13398 (clobber (match_scratch:DI 3 "=&r,&r"))]
13399 "TARGET_64BIT"
13400 "@
13401 addic %3,%1,-1\;addze. %3,%2
13402 #"
13403 [(set_attr "type" "compare")
13404 (set_attr "length" "8,12")])
13406 (define_split
13407 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13408 (compare:CC
13409 (plus:DI (lshiftrt:DI
13410 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
13411 (const_int 63))
13412 (match_operand:DI 2 "gpc_reg_operand" ""))
13413 (const_int 0)))
13414 (clobber (match_scratch:DI 3 ""))]
13415 "TARGET_64BIT && reload_completed"
13416 [(set (match_dup 3)
13417 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
13418 (const_int 63))
13419 (match_dup 2)))
13420 (set (match_dup 0)
13421 (compare:CC (match_dup 3)
13422 (const_int 0)))]
13423 "")
13425 (define_insn "*plus_ne0si_compare"
13426 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13427 (compare:CC
13428 (plus:SI (lshiftrt:SI
13429 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
13430 (const_int 31))
13431 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13432 (const_int 0)))
13433 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13434 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13435 (match_dup 2)))
13436 (clobber (match_scratch:SI 3 "=&r,&r"))]
13437 "TARGET_32BIT"
13438 "@
13439 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
13440 #"
13441 [(set_attr "type" "compare")
13442 (set_attr "length" "8,12")])
13444 (define_split
13445 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13446 (compare:CC
13447 (plus:SI (lshiftrt:SI
13448 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
13449 (const_int 31))
13450 (match_operand:SI 2 "gpc_reg_operand" ""))
13451 (const_int 0)))
13452 (set (match_operand:SI 0 "gpc_reg_operand" "")
13453 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13454 (match_dup 2)))
13455 (clobber (match_scratch:SI 3 ""))]
13456 "TARGET_32BIT && reload_completed"
13457 [(parallel [(set (match_dup 0)
13458 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
13459 (match_dup 2)))
13460 (clobber (match_dup 3))])
13461 (set (match_dup 4)
13462 (compare:CC (match_dup 0)
13463 (const_int 0)))]
13464 "")
13466 (define_insn "*plus_ne0di_compare"
13467 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13468 (compare:CC
13469 (plus:DI (lshiftrt:DI
13470 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
13471 (const_int 63))
13472 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13473 (const_int 0)))
13474 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13475 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13476 (match_dup 2)))
13477 (clobber (match_scratch:DI 3 "=&r,&r"))]
13478 "TARGET_64BIT"
13479 "@
13480 addic %3,%1,-1\;addze. %0,%2
13481 #"
13482 [(set_attr "type" "compare")
13483 (set_attr "length" "8,12")])
13485 (define_split
13486 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
13487 (compare:CC
13488 (plus:DI (lshiftrt:DI
13489 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
13490 (const_int 63))
13491 (match_operand:DI 2 "gpc_reg_operand" ""))
13492 (const_int 0)))
13493 (set (match_operand:DI 0 "gpc_reg_operand" "")
13494 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13495 (match_dup 2)))
13496 (clobber (match_scratch:DI 3 ""))]
13497 "TARGET_64BIT && reload_completed"
13498 [(parallel [(set (match_dup 0)
13499 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
13500 (match_dup 2)))
13501 (clobber (match_dup 3))])
13502 (set (match_dup 4)
13503 (compare:CC (match_dup 0)
13504 (const_int 0)))]
13505 "")
13507 (define_insn ""
13508 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13509 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13510 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
13511 (clobber (match_scratch:SI 3 "=r,X"))]
13512 "TARGET_POWER"
13513 "@
13514 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
13515 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
13516 [(set_attr "length" "12")])
13518 (define_insn ""
13519 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13520 (compare:CC
13521 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13522 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13523 (const_int 0)))
13524 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
13525 (le:SI (match_dup 1) (match_dup 2)))
13526 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
13527 "TARGET_POWER"
13528 "@
13529 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
13530 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
13531 #
13532 #"
13533 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
13534 (set_attr "length" "12,12,16,16")])
13536 (define_split
13537 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13538 (compare:CC
13539 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13540 (match_operand:SI 2 "reg_or_short_operand" ""))
13541 (const_int 0)))
13542 (set (match_operand:SI 0 "gpc_reg_operand" "")
13543 (le:SI (match_dup 1) (match_dup 2)))
13544 (clobber (match_scratch:SI 3 ""))]
13545 "TARGET_POWER && reload_completed"
13546 [(parallel [(set (match_dup 0)
13547 (le:SI (match_dup 1) (match_dup 2)))
13548 (clobber (match_dup 3))])
13549 (set (match_dup 4)
13550 (compare:CC (match_dup 0)
13551 (const_int 0)))]
13552 "")
13554 (define_insn ""
13555 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13556 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13557 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
13558 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
13559 "TARGET_POWER"
13560 "@
13561 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
13562 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
13563 [(set_attr "length" "12")])
13565 (define_insn ""
13566 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13567 (compare:CC
13568 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13569 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13570 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13571 (const_int 0)))
13572 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13573 "TARGET_POWER"
13574 "@
13575 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13576 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
13577 #
13578 #"
13579 [(set_attr "type" "compare")
13580 (set_attr "length" "12,12,16,16")])
13582 (define_split
13583 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13584 (compare:CC
13585 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13586 (match_operand:SI 2 "reg_or_short_operand" ""))
13587 (match_operand:SI 3 "gpc_reg_operand" ""))
13588 (const_int 0)))
13589 (clobber (match_scratch:SI 4 ""))]
13590 "TARGET_POWER && reload_completed"
13591 [(set (match_dup 4)
13592 (plus:SI (le:SI (match_dup 1) (match_dup 2))
13593 (match_dup 3)))
13594 (set (match_dup 0)
13595 (compare:CC (match_dup 4)
13596 (const_int 0)))]
13597 "")
13599 (define_insn ""
13600 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13601 (compare:CC
13602 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13603 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
13604 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13605 (const_int 0)))
13606 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13607 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13608 "TARGET_POWER"
13609 "@
13610 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13611 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
13612 #
13613 #"
13614 [(set_attr "type" "compare")
13615 (set_attr "length" "12,12,16,16")])
13617 (define_split
13618 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13619 (compare:CC
13620 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
13621 (match_operand:SI 2 "reg_or_short_operand" ""))
13622 (match_operand:SI 3 "gpc_reg_operand" ""))
13623 (const_int 0)))
13624 (set (match_operand:SI 0 "gpc_reg_operand" "")
13625 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13626 "TARGET_POWER && reload_completed"
13627 [(set (match_dup 0)
13628 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13629 (set (match_dup 4)
13630 (compare:CC (match_dup 0)
13631 (const_int 0)))]
13632 "")
13634 (define_insn ""
13635 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13636 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13637 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
13638 "TARGET_POWER"
13639 "@
13640 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
13641 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
13642 [(set_attr "length" "12")])
13644 (define_insn "*leu<mode>"
13645 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13646 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13647 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13648 ""
13649 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13650 [(set_attr "type" "three")
13651 (set_attr "length" "12")])
13653 (define_insn "*leu<mode>_compare"
13654 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13655 (compare:CC
13656 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13657 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13658 (const_int 0)))
13659 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13660 (leu:P (match_dup 1) (match_dup 2)))]
13661 ""
13662 "@
13663 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13664 #"
13665 [(set_attr "type" "compare")
13666 (set_attr "length" "12,16")])
13668 (define_split
13669 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13670 (compare:CC
13671 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
13672 (match_operand:P 2 "reg_or_short_operand" ""))
13673 (const_int 0)))
13674 (set (match_operand:P 0 "gpc_reg_operand" "")
13675 (leu:P (match_dup 1) (match_dup 2)))]
13676 "reload_completed"
13677 [(set (match_dup 0)
13678 (leu:P (match_dup 1) (match_dup 2)))
13679 (set (match_dup 3)
13680 (compare:CC (match_dup 0)
13681 (const_int 0)))]
13682 "")
13684 (define_insn "*plus_leu<mode>"
13685 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13686 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13687 (match_operand:P 2 "reg_or_short_operand" "rI"))
13688 (match_operand:P 3 "gpc_reg_operand" "r")))]
13689 ""
13690 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
13691 [(set_attr "type" "two")
13692 (set_attr "length" "8")])
13694 (define_insn ""
13695 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13696 (compare:CC
13697 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13698 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13699 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13700 (const_int 0)))
13701 (clobber (match_scratch:SI 4 "=&r,&r"))]
13702 "TARGET_32BIT"
13703 "@
13704 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
13705 #"
13706 [(set_attr "type" "compare")
13707 (set_attr "length" "8,12")])
13709 (define_split
13710 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13711 (compare:CC
13712 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13713 (match_operand:SI 2 "reg_or_short_operand" ""))
13714 (match_operand:SI 3 "gpc_reg_operand" ""))
13715 (const_int 0)))
13716 (clobber (match_scratch:SI 4 ""))]
13717 "TARGET_32BIT && reload_completed"
13718 [(set (match_dup 4)
13719 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
13720 (match_dup 3)))
13721 (set (match_dup 0)
13722 (compare:CC (match_dup 4)
13723 (const_int 0)))]
13724 "")
13726 (define_insn ""
13727 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13728 (compare:CC
13729 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13730 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13731 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13732 (const_int 0)))
13733 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13734 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13735 "TARGET_32BIT"
13736 "@
13737 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
13738 #"
13739 [(set_attr "type" "compare")
13740 (set_attr "length" "8,12")])
13742 (define_split
13743 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13744 (compare:CC
13745 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13746 (match_operand:SI 2 "reg_or_short_operand" ""))
13747 (match_operand:SI 3 "gpc_reg_operand" ""))
13748 (const_int 0)))
13749 (set (match_operand:SI 0 "gpc_reg_operand" "")
13750 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13751 "TARGET_32BIT && reload_completed"
13752 [(set (match_dup 0)
13753 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13754 (set (match_dup 4)
13755 (compare:CC (match_dup 0)
13756 (const_int 0)))]
13757 "")
13759 (define_insn "*neg_leu<mode>"
13760 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13761 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13762 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13763 ""
13764 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
13765 [(set_attr "type" "three")
13766 (set_attr "length" "12")])
13768 (define_insn "*and_neg_leu<mode>"
13769 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13770 (and:P (neg:P
13771 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
13772 (match_operand:P 2 "reg_or_short_operand" "rI")))
13773 (match_operand:P 3 "gpc_reg_operand" "r")))]
13774 ""
13775 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13776 [(set_attr "type" "three")
13777 (set_attr "length" "12")])
13779 (define_insn ""
13780 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13781 (compare:CC
13782 (and:SI (neg:SI
13783 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13784 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13785 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13786 (const_int 0)))
13787 (clobber (match_scratch:SI 4 "=&r,&r"))]
13788 "TARGET_32BIT"
13789 "@
13790 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13791 #"
13792 [(set_attr "type" "compare")
13793 (set_attr "length" "12,16")])
13795 (define_split
13796 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13797 (compare:CC
13798 (and:SI (neg:SI
13799 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13800 (match_operand:SI 2 "reg_or_short_operand" "")))
13801 (match_operand:SI 3 "gpc_reg_operand" ""))
13802 (const_int 0)))
13803 (clobber (match_scratch:SI 4 ""))]
13804 "TARGET_32BIT && reload_completed"
13805 [(set (match_dup 4)
13806 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13807 (match_dup 3)))
13808 (set (match_dup 0)
13809 (compare:CC (match_dup 4)
13810 (const_int 0)))]
13811 "")
13813 (define_insn ""
13814 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13815 (compare:CC
13816 (and:SI (neg:SI
13817 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13818 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
13819 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13820 (const_int 0)))
13821 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13822 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13823 "TARGET_32BIT"
13824 "@
13825 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13826 #"
13827 [(set_attr "type" "compare")
13828 (set_attr "length" "12,16")])
13830 (define_split
13831 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13832 (compare:CC
13833 (and:SI (neg:SI
13834 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13835 (match_operand:SI 2 "reg_or_short_operand" "")))
13836 (match_operand:SI 3 "gpc_reg_operand" ""))
13837 (const_int 0)))
13838 (set (match_operand:SI 0 "gpc_reg_operand" "")
13839 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13840 "TARGET_32BIT && reload_completed"
13841 [(set (match_dup 0)
13842 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
13843 (match_dup 3)))
13844 (set (match_dup 4)
13845 (compare:CC (match_dup 0)
13846 (const_int 0)))]
13847 "")
13849 (define_insn ""
13850 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13851 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13852 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13853 "TARGET_POWER"
13854 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13855 [(set_attr "length" "12")])
13857 (define_insn ""
13858 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13859 (compare:CC
13860 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13861 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13862 (const_int 0)))
13863 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13864 (lt:SI (match_dup 1) (match_dup 2)))]
13865 "TARGET_POWER"
13866 "@
13867 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13868 #"
13869 [(set_attr "type" "delayed_compare")
13870 (set_attr "length" "12,16")])
13872 (define_split
13873 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13874 (compare:CC
13875 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13876 (match_operand:SI 2 "reg_or_short_operand" ""))
13877 (const_int 0)))
13878 (set (match_operand:SI 0 "gpc_reg_operand" "")
13879 (lt:SI (match_dup 1) (match_dup 2)))]
13880 "TARGET_POWER && reload_completed"
13881 [(set (match_dup 0)
13882 (lt:SI (match_dup 1) (match_dup 2)))
13883 (set (match_dup 3)
13884 (compare:CC (match_dup 0)
13885 (const_int 0)))]
13886 "")
13888 (define_insn ""
13889 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13890 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13891 (match_operand:SI 2 "reg_or_short_operand" "rI"))
13892 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13893 "TARGET_POWER"
13894 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13895 [(set_attr "length" "12")])
13897 (define_insn ""
13898 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13899 (compare:CC
13900 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13901 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13902 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13903 (const_int 0)))
13904 (clobber (match_scratch:SI 4 "=&r,&r"))]
13905 "TARGET_POWER"
13906 "@
13907 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13908 #"
13909 [(set_attr "type" "compare")
13910 (set_attr "length" "12,16")])
13912 (define_split
13913 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13914 (compare:CC
13915 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13916 (match_operand:SI 2 "reg_or_short_operand" ""))
13917 (match_operand:SI 3 "gpc_reg_operand" ""))
13918 (const_int 0)))
13919 (clobber (match_scratch:SI 4 ""))]
13920 "TARGET_POWER && reload_completed"
13921 [(set (match_dup 4)
13922 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
13923 (match_dup 3)))
13924 (set (match_dup 0)
13925 (compare:CC (match_dup 4)
13926 (const_int 0)))]
13927 "")
13929 (define_insn ""
13930 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13931 (compare:CC
13932 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13933 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13934 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13935 (const_int 0)))
13936 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13937 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13938 "TARGET_POWER"
13939 "@
13940 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13941 #"
13942 [(set_attr "type" "compare")
13943 (set_attr "length" "12,16")])
13945 (define_split
13946 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13947 (compare:CC
13948 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13949 (match_operand:SI 2 "reg_or_short_operand" ""))
13950 (match_operand:SI 3 "gpc_reg_operand" ""))
13951 (const_int 0)))
13952 (set (match_operand:SI 0 "gpc_reg_operand" "")
13953 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13954 "TARGET_POWER && reload_completed"
13955 [(set (match_dup 0)
13956 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13957 (set (match_dup 4)
13958 (compare:CC (match_dup 0)
13959 (const_int 0)))]
13960 "")
13962 (define_insn ""
13963 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13964 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13965 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13966 "TARGET_POWER"
13967 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13968 [(set_attr "length" "12")])
13970 (define_insn_and_split "*ltu<mode>"
13971 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13972 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13973 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13974 ""
13975 "#"
13976 ""
13977 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13978 (set (match_dup 0) (neg:P (match_dup 0)))]
13979 "")
13981 (define_insn_and_split "*ltu<mode>_compare"
13982 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13983 (compare:CC
13984 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13985 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13986 (const_int 0)))
13987 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13988 (ltu:P (match_dup 1) (match_dup 2)))]
13989 ""
13990 "#"
13991 ""
13992 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13993 (parallel [(set (match_dup 3)
13994 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13995 (set (match_dup 0) (neg:P (match_dup 0)))])]
13996 "")
13998 (define_insn_and_split "*plus_ltu<mode>"
13999 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
14000 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14001 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14002 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
14003 ""
14004 "#"
14005 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14006 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14007 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14008 "")
14010 (define_insn_and_split "*plus_ltu<mode>_compare"
14011 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14012 (compare:CC
14013 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14014 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14015 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14016 (const_int 0)))
14017 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14018 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14019 ""
14020 "#"
14021 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14022 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
14023 (parallel [(set (match_dup 4)
14024 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14025 (const_int 0)))
14026 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14027 "")
14029 (define_insn "*neg_ltu<mode>"
14030 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14031 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14032 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
14033 ""
14034 "@
14035 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
14036 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
14037 [(set_attr "type" "two")
14038 (set_attr "length" "8")])
14040 (define_insn ""
14041 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14042 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14043 (match_operand:SI 2 "reg_or_short_operand" "rI")))
14044 (clobber (match_scratch:SI 3 "=r"))]
14045 "TARGET_POWER"
14046 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
14047 [(set_attr "length" "12")])
14049 (define_insn ""
14050 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14051 (compare:CC
14052 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14053 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14054 (const_int 0)))
14055 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14056 (ge:SI (match_dup 1) (match_dup 2)))
14057 (clobber (match_scratch:SI 3 "=r,r"))]
14058 "TARGET_POWER"
14059 "@
14060 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
14061 #"
14062 [(set_attr "type" "compare")
14063 (set_attr "length" "12,16")])
14065 (define_split
14066 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14067 (compare:CC
14068 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14069 (match_operand:SI 2 "reg_or_short_operand" ""))
14070 (const_int 0)))
14071 (set (match_operand:SI 0 "gpc_reg_operand" "")
14072 (ge:SI (match_dup 1) (match_dup 2)))
14073 (clobber (match_scratch:SI 3 ""))]
14074 "TARGET_POWER && reload_completed"
14075 [(parallel [(set (match_dup 0)
14076 (ge:SI (match_dup 1) (match_dup 2)))
14077 (clobber (match_dup 3))])
14078 (set (match_dup 4)
14079 (compare:CC (match_dup 0)
14080 (const_int 0)))]
14081 "")
14083 (define_insn ""
14084 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14085 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14086 (match_operand:SI 2 "reg_or_short_operand" "rI"))
14087 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14088 "TARGET_POWER"
14089 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
14090 [(set_attr "length" "12")])
14092 (define_insn ""
14093 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14094 (compare:CC
14095 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14096 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14097 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14098 (const_int 0)))
14099 (clobber (match_scratch:SI 4 "=&r,&r"))]
14100 "TARGET_POWER"
14101 "@
14102 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
14103 #"
14104 [(set_attr "type" "compare")
14105 (set_attr "length" "12,16")])
14107 (define_split
14108 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14109 (compare:CC
14110 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14111 (match_operand:SI 2 "reg_or_short_operand" ""))
14112 (match_operand:SI 3 "gpc_reg_operand" ""))
14113 (const_int 0)))
14114 (clobber (match_scratch:SI 4 ""))]
14115 "TARGET_POWER && reload_completed"
14116 [(set (match_dup 4)
14117 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
14118 (match_dup 3)))
14119 (set (match_dup 0)
14120 (compare:CC (match_dup 4)
14121 (const_int 0)))]
14122 "")
14124 (define_insn ""
14125 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14126 (compare:CC
14127 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14128 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
14129 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14130 (const_int 0)))
14131 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14132 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14133 "TARGET_POWER"
14134 "@
14135 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
14136 #"
14137 [(set_attr "type" "compare")
14138 (set_attr "length" "12,16")])
14140 (define_split
14141 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14142 (compare:CC
14143 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
14144 (match_operand:SI 2 "reg_or_short_operand" ""))
14145 (match_operand:SI 3 "gpc_reg_operand" ""))
14146 (const_int 0)))
14147 (set (match_operand:SI 0 "gpc_reg_operand" "")
14148 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14149 "TARGET_POWER && reload_completed"
14150 [(set (match_dup 0)
14151 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14152 (set (match_dup 4)
14153 (compare:CC (match_dup 0)
14154 (const_int 0)))]
14155 "")
14157 (define_insn ""
14158 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14159 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14160 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
14161 "TARGET_POWER"
14162 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
14163 [(set_attr "length" "12")])
14165 (define_insn "*geu<mode>"
14166 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14167 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14168 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
14169 ""
14170 "@
14171 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
14172 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
14173 [(set_attr "type" "three")
14174 (set_attr "length" "12")])
14176 (define_insn "*geu<mode>_compare"
14177 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
14178 (compare:CC
14179 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14180 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
14181 (const_int 0)))
14182 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
14183 (geu:P (match_dup 1) (match_dup 2)))]
14184 ""
14185 "@
14186 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14187 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
14188 #
14189 #"
14190 [(set_attr "type" "compare")
14191 (set_attr "length" "12,12,16,16")])
14193 (define_split
14194 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14195 (compare:CC
14196 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
14197 (match_operand:P 2 "reg_or_neg_short_operand" ""))
14198 (const_int 0)))
14199 (set (match_operand:P 0 "gpc_reg_operand" "")
14200 (geu:P (match_dup 1) (match_dup 2)))]
14201 "reload_completed"
14202 [(set (match_dup 0)
14203 (geu:P (match_dup 1) (match_dup 2)))
14204 (set (match_dup 3)
14205 (compare:CC (match_dup 0)
14206 (const_int 0)))]
14207 "")
14209 (define_insn "*plus_geu<mode>"
14210 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14211 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14212 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
14213 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14214 ""
14215 "@
14216 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
14217 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
14218 [(set_attr "type" "two")
14219 (set_attr "length" "8")])
14221 (define_insn ""
14222 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14223 (compare:CC
14224 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14225 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14226 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14227 (const_int 0)))
14228 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14229 "TARGET_32BIT"
14230 "@
14231 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
14232 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
14233 #
14234 #"
14235 [(set_attr "type" "compare")
14236 (set_attr "length" "8,8,12,12")])
14238 (define_split
14239 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14240 (compare:CC
14241 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14242 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14243 (match_operand:SI 3 "gpc_reg_operand" ""))
14244 (const_int 0)))
14245 (clobber (match_scratch:SI 4 ""))]
14246 "TARGET_32BIT && reload_completed"
14247 [(set (match_dup 4)
14248 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
14249 (match_dup 3)))
14250 (set (match_dup 0)
14251 (compare:CC (match_dup 4)
14252 (const_int 0)))]
14253 "")
14255 (define_insn ""
14256 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14257 (compare:CC
14258 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14259 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
14260 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14261 (const_int 0)))
14262 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14263 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14264 "TARGET_32BIT"
14265 "@
14266 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
14267 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
14268 #
14269 #"
14270 [(set_attr "type" "compare")
14271 (set_attr "length" "8,8,12,12")])
14273 (define_split
14274 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14275 (compare:CC
14276 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14277 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
14278 (match_operand:SI 3 "gpc_reg_operand" ""))
14279 (const_int 0)))
14280 (set (match_operand:SI 0 "gpc_reg_operand" "")
14281 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14282 "TARGET_32BIT && reload_completed"
14283 [(set (match_dup 0)
14284 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14285 (set (match_dup 4)
14286 (compare:CC (match_dup 0)
14287 (const_int 0)))]
14288 "")
14290 (define_insn "*neg_geu<mode>"
14291 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14292 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14293 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
14294 ""
14295 "@
14296 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
14297 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
14298 [(set_attr "type" "three")
14299 (set_attr "length" "12")])
14301 (define_insn "*and_neg_geu<mode>"
14302 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
14303 (and:P (neg:P
14304 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14305 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
14306 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
14307 ""
14308 "@
14309 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
14310 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
14311 [(set_attr "type" "three")
14312 (set_attr "length" "12")])
14314 (define_insn ""
14315 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
14316 (compare:CC
14317 (and:SI (neg:SI
14318 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14319 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14320 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14321 (const_int 0)))
14322 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
14323 "TARGET_32BIT"
14324 "@
14325 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14326 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
14327 #
14328 #"
14329 [(set_attr "type" "compare")
14330 (set_attr "length" "12,12,16,16")])
14332 (define_split
14333 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14334 (compare:CC
14335 (and:SI (neg:SI
14336 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14337 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14338 (match_operand:SI 3 "gpc_reg_operand" ""))
14339 (const_int 0)))
14340 (clobber (match_scratch:SI 4 ""))]
14341 "TARGET_32BIT && reload_completed"
14342 [(set (match_dup 4)
14343 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
14344 (match_dup 3)))
14345 (set (match_dup 0)
14346 (compare:CC (match_dup 4)
14347 (const_int 0)))]
14348 "")
14350 (define_insn ""
14351 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14352 (compare:CC
14353 (and:SI (neg:SI
14354 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
14355 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
14356 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
14357 (const_int 0)))
14358 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14359 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14360 "TARGET_32BIT"
14361 "@
14362 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14363 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
14364 #
14365 #"
14366 [(set_attr "type" "compare")
14367 (set_attr "length" "12,12,16,16")])
14369 (define_split
14370 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14371 (compare:CC
14372 (and:SI (neg:SI
14373 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
14374 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
14375 (match_operand:SI 3 "gpc_reg_operand" ""))
14376 (const_int 0)))
14377 (set (match_operand:SI 0 "gpc_reg_operand" "")
14378 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
14379 "TARGET_32BIT && reload_completed"
14380 [(set (match_dup 0)
14381 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
14382 (set (match_dup 4)
14383 (compare:CC (match_dup 0)
14384 (const_int 0)))]
14385 "")
14387 (define_insn ""
14388 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14389 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14390 (match_operand:SI 2 "reg_or_short_operand" "r")))]
14391 "TARGET_POWER"
14392 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
14393 [(set_attr "length" "12")])
14395 (define_insn ""
14396 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14397 (compare:CC
14398 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14399 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14400 (const_int 0)))
14401 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
14402 (gt:SI (match_dup 1) (match_dup 2)))]
14403 "TARGET_POWER"
14404 "@
14405 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
14406 #"
14407 [(set_attr "type" "delayed_compare")
14408 (set_attr "length" "12,16")])
14410 (define_split
14411 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14412 (compare:CC
14413 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14414 (match_operand:SI 2 "reg_or_short_operand" ""))
14415 (const_int 0)))
14416 (set (match_operand:SI 0 "gpc_reg_operand" "")
14417 (gt:SI (match_dup 1) (match_dup 2)))]
14418 "TARGET_POWER && reload_completed"
14419 [(set (match_dup 0)
14420 (gt:SI (match_dup 1) (match_dup 2)))
14421 (set (match_dup 3)
14422 (compare:CC (match_dup 0)
14423 (const_int 0)))]
14424 "")
14426 (define_insn "*plus_gt0<mode>"
14427 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14428 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
14429 (const_int 0))
14430 (match_operand:P 2 "gpc_reg_operand" "r")))]
14431 ""
14432 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
14433 [(set_attr "type" "three")
14434 (set_attr "length" "12")])
14436 (define_insn ""
14437 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14438 (compare:CC
14439 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14440 (const_int 0))
14441 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14442 (const_int 0)))
14443 (clobber (match_scratch:SI 3 "=&r,&r"))]
14444 "TARGET_32BIT"
14445 "@
14446 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
14447 #"
14448 [(set_attr "type" "compare")
14449 (set_attr "length" "12,16")])
14451 (define_split
14452 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14453 (compare:CC
14454 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14455 (const_int 0))
14456 (match_operand:SI 2 "gpc_reg_operand" ""))
14457 (const_int 0)))
14458 (clobber (match_scratch:SI 3 ""))]
14459 "TARGET_32BIT && reload_completed"
14460 [(set (match_dup 3)
14461 (plus:SI (gt:SI (match_dup 1) (const_int 0))
14462 (match_dup 2)))
14463 (set (match_dup 0)
14464 (compare:CC (match_dup 3)
14465 (const_int 0)))]
14466 "")
14468 (define_insn ""
14469 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14470 (compare:CC
14471 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14472 (const_int 0))
14473 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14474 (const_int 0)))
14475 (clobber (match_scratch:DI 3 "=&r,&r"))]
14476 "TARGET_64BIT"
14477 "@
14478 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
14479 #"
14480 [(set_attr "type" "compare")
14481 (set_attr "length" "12,16")])
14483 (define_split
14484 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
14485 (compare:CC
14486 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14487 (const_int 0))
14488 (match_operand:DI 2 "gpc_reg_operand" ""))
14489 (const_int 0)))
14490 (clobber (match_scratch:DI 3 ""))]
14491 "TARGET_64BIT && reload_completed"
14492 [(set (match_dup 3)
14493 (plus:DI (gt:DI (match_dup 1) (const_int 0))
14494 (match_dup 2)))
14495 (set (match_dup 0)
14496 (compare:CC (match_dup 3)
14497 (const_int 0)))]
14498 "")
14500 (define_insn ""
14501 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14502 (compare:CC
14503 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14504 (const_int 0))
14505 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
14506 (const_int 0)))
14507 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14508 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14509 "TARGET_32BIT"
14510 "@
14511 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
14512 #"
14513 [(set_attr "type" "compare")
14514 (set_attr "length" "12,16")])
14516 (define_split
14517 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
14518 (compare:CC
14519 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14520 (const_int 0))
14521 (match_operand:SI 2 "gpc_reg_operand" ""))
14522 (const_int 0)))
14523 (set (match_operand:SI 0 "gpc_reg_operand" "")
14524 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
14525 "TARGET_32BIT && reload_completed"
14526 [(set (match_dup 0)
14527 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
14528 (set (match_dup 3)
14529 (compare:CC (match_dup 0)
14530 (const_int 0)))]
14531 "")
14533 (define_insn ""
14534 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14535 (compare:CC
14536 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
14537 (const_int 0))
14538 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
14539 (const_int 0)))
14540 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
14541 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14542 "TARGET_64BIT"
14543 "@
14544 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
14545 #"
14546 [(set_attr "type" "compare")
14547 (set_attr "length" "12,16")])
14549 (define_split
14550 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
14551 (compare:CC
14552 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
14553 (const_int 0))
14554 (match_operand:DI 2 "gpc_reg_operand" ""))
14555 (const_int 0)))
14556 (set (match_operand:DI 0 "gpc_reg_operand" "")
14557 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
14558 "TARGET_64BIT && reload_completed"
14559 [(set (match_dup 0)
14560 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
14561 (set (match_dup 3)
14562 (compare:CC (match_dup 0)
14563 (const_int 0)))]
14564 "")
14566 (define_insn ""
14567 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
14568 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14569 (match_operand:SI 2 "reg_or_short_operand" "r"))
14570 (match_operand:SI 3 "gpc_reg_operand" "r")))]
14571 "TARGET_POWER"
14572 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
14573 [(set_attr "length" "12")])
14575 (define_insn ""
14576 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
14577 (compare:CC
14578 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14579 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14580 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14581 (const_int 0)))
14582 (clobber (match_scratch:SI 4 "=&r,&r"))]
14583 "TARGET_POWER"
14584 "@
14585 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
14586 #"
14587 [(set_attr "type" "compare")
14588 (set_attr "length" "12,16")])
14590 (define_split
14591 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
14592 (compare:CC
14593 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14594 (match_operand:SI 2 "reg_or_short_operand" ""))
14595 (match_operand:SI 3 "gpc_reg_operand" ""))
14596 (const_int 0)))
14597 (clobber (match_scratch:SI 4 ""))]
14598 "TARGET_POWER && reload_completed"
14599 [(set (match_dup 4)
14600 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14601 (set (match_dup 0)
14602 (compare:CC (match_dup 4)
14603 (const_int 0)))]
14604 "")
14606 (define_insn ""
14607 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
14608 (compare:CC
14609 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
14610 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
14611 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
14612 (const_int 0)))
14613 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
14614 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14615 "TARGET_POWER"
14616 "@
14617 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
14618 #"
14619 [(set_attr "type" "compare")
14620 (set_attr "length" "12,16")])
14622 (define_split
14623 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
14624 (compare:CC
14625 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
14626 (match_operand:SI 2 "reg_or_short_operand" ""))
14627 (match_operand:SI 3 "gpc_reg_operand" ""))
14628 (const_int 0)))
14629 (set (match_operand:SI 0 "gpc_reg_operand" "")
14630 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
14631 "TARGET_POWER && reload_completed"
14632 [(set (match_dup 0)
14633 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
14634 (set (match_dup 4)
14635 (compare:CC (match_dup 0)
14636 (const_int 0)))]
14637 "")
14639 (define_insn ""
14640 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14641 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
14642 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
14643 "TARGET_POWER"
14644 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
14645 [(set_attr "length" "12")])
14647 (define_insn_and_split "*gtu<mode>"
14648 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14649 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14650 (match_operand:P 2 "reg_or_short_operand" "rI")))]
14651 ""
14652 "#"
14653 ""
14654 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14655 (set (match_dup 0) (neg:P (match_dup 0)))]
14656 "")
14658 (define_insn_and_split "*gtu<mode>_compare"
14659 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
14660 (compare:CC
14661 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
14662 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
14663 (const_int 0)))
14664 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
14665 (gtu:P (match_dup 1) (match_dup 2)))]
14666 ""
14667 "#"
14668 ""
14669 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14670 (parallel [(set (match_dup 3)
14671 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
14672 (set (match_dup 0) (neg:P (match_dup 0)))])]
14673 "")
14675 (define_insn_and_split "*plus_gtu<mode>"
14676 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
14677 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14678 (match_operand:P 2 "reg_or_short_operand" "rI"))
14679 (match_operand:P 3 "reg_or_short_operand" "rI")))]
14680 ""
14681 "#"
14682 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14683 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14684 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
14685 "")
14687 (define_insn_and_split "*plus_gtu<mode>_compare"
14688 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
14689 (compare:CC
14690 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
14691 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
14692 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
14693 (const_int 0)))
14694 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
14695 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
14696 ""
14697 "#"
14698 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
14699 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
14700 (parallel [(set (match_dup 4)
14701 (compare:CC (minus:P (match_dup 3) (match_dup 0))
14702 (const_int 0)))
14703 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
14704 "")
14706 (define_insn "*neg_gtu<mode>"
14707 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14708 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
14709 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
14710 ""
14711 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
14712 [(set_attr "type" "two")
14713 (set_attr "length" "8")])
14715 \f
14716 ;; Define both directions of branch and return. If we need a reload
14717 ;; register, we'd rather use CR0 since it is much easier to copy a
14718 ;; register CC value to there.
14720 (define_insn ""
14721 [(set (pc)
14722 (if_then_else (match_operator 1 "branch_comparison_operator"
14723 [(match_operand 2
14724 "cc_reg_operand" "y")
14725 (const_int 0)])
14726 (label_ref (match_operand 0 "" ""))
14727 (pc)))]
14728 ""
14729 "*
14730 {
14731 return output_cbranch (operands[1], \"%l0\", 0, insn);
14732 }"
14733 [(set_attr "type" "branch")])
14735 (define_insn ""
14736 [(set (pc)
14737 (if_then_else (match_operator 0 "branch_comparison_operator"
14738 [(match_operand 1
14739 "cc_reg_operand" "y")
14740 (const_int 0)])
14741 (return)
14742 (pc)))]
14743 "direct_return ()"
14744 "*
14745 {
14746 return output_cbranch (operands[0], NULL, 0, insn);
14747 }"
14748 [(set_attr "type" "jmpreg")
14749 (set_attr "length" "4")])
14751 (define_insn ""
14752 [(set (pc)
14753 (if_then_else (match_operator 1 "branch_comparison_operator"
14754 [(match_operand 2
14755 "cc_reg_operand" "y")
14756 (const_int 0)])
14757 (pc)
14758 (label_ref (match_operand 0 "" ""))))]
14759 ""
14760 "*
14761 {
14762 return output_cbranch (operands[1], \"%l0\", 1, insn);
14763 }"
14764 [(set_attr "type" "branch")])
14766 (define_insn ""
14767 [(set (pc)
14768 (if_then_else (match_operator 0 "branch_comparison_operator"
14769 [(match_operand 1
14770 "cc_reg_operand" "y")
14771 (const_int 0)])
14772 (pc)
14773 (return)))]
14774 "direct_return ()"
14775 "*
14776 {
14777 return output_cbranch (operands[0], NULL, 1, insn);
14778 }"
14779 [(set_attr "type" "jmpreg")
14780 (set_attr "length" "4")])
14782 ;; Logic on condition register values.
14784 ; This pattern matches things like
14785 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
14786 ; (eq:SI (reg:CCFP 68) (const_int 0)))
14787 ; (const_int 1)))
14788 ; which are generated by the branch logic.
14789 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
14791 (define_insn "*cceq_ior_compare"
14792 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14793 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
14794 [(match_operator:SI 2
14795 "branch_positive_comparison_operator"
14796 [(match_operand 3
14797 "cc_reg_operand" "y,y")
14798 (const_int 0)])
14799 (match_operator:SI 4
14800 "branch_positive_comparison_operator"
14801 [(match_operand 5
14802 "cc_reg_operand" "0,y")
14803 (const_int 0)])])
14804 (const_int 1)))]
14805 ""
14806 "cr%q1 %E0,%j2,%j4"
14807 [(set_attr "type" "cr_logical,delayed_cr")])
14809 ; Why is the constant -1 here, but 1 in the previous pattern?
14810 ; Because ~1 has all but the low bit set.
14811 (define_insn ""
14812 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14813 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
14814 [(not:SI (match_operator:SI 2
14815 "branch_positive_comparison_operator"
14816 [(match_operand 3
14817 "cc_reg_operand" "y,y")
14818 (const_int 0)]))
14819 (match_operator:SI 4
14820 "branch_positive_comparison_operator"
14821 [(match_operand 5
14822 "cc_reg_operand" "0,y")
14823 (const_int 0)])])
14824 (const_int -1)))]
14825 ""
14826 "cr%q1 %E0,%j2,%j4"
14827 [(set_attr "type" "cr_logical,delayed_cr")])
14829 (define_insn "*cceq_rev_compare"
14830 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
14831 (compare:CCEQ (match_operator:SI 1
14832 "branch_positive_comparison_operator"
14833 [(match_operand 2
14834 "cc_reg_operand" "0,y")
14835 (const_int 0)])
14836 (const_int 0)))]
14837 ""
14838 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
14839 [(set_attr "type" "cr_logical,delayed_cr")])
14841 ;; If we are comparing the result of two comparisons, this can be done
14842 ;; using creqv or crxor.
14844 (define_insn_and_split ""
14845 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14846 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14847 [(match_operand 2 "cc_reg_operand" "y")
14848 (const_int 0)])
14849 (match_operator 3 "branch_comparison_operator"
14850 [(match_operand 4 "cc_reg_operand" "y")
14851 (const_int 0)])))]
14852 ""
14853 "#"
14854 ""
14855 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14856 (match_dup 5)))]
14857 "
14858 {
14859 int positive_1, positive_2;
14861 positive_1 = branch_positive_comparison_operator (operands[1],
14862 GET_MODE (operands[1]));
14863 positive_2 = branch_positive_comparison_operator (operands[3],
14864 GET_MODE (operands[3]));
14866 if (! positive_1)
14867 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
14868 GET_CODE (operands[1])),
14869 SImode,
14870 operands[2], const0_rtx);
14871 else if (GET_MODE (operands[1]) != SImode)
14872 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
14873 operands[2], const0_rtx);
14875 if (! positive_2)
14876 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
14877 GET_CODE (operands[3])),
14878 SImode,
14879 operands[4], const0_rtx);
14880 else if (GET_MODE (operands[3]) != SImode)
14881 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
14882 operands[4], const0_rtx);
14884 if (positive_1 == positive_2)
14885 {
14886 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14887 operands[5] = constm1_rtx;
14888 }
14889 else
14890 {
14891 operands[5] = const1_rtx;
14892 }
14893 }")
14895 ;; Unconditional branch and return.
14897 (define_insn "jump"
14898 [(set (pc)
14899 (label_ref (match_operand 0 "" "")))]
14900 ""
14901 "b %l0"
14902 [(set_attr "type" "branch")])
14904 (define_insn "return"
14905 [(return)]
14906 "direct_return ()"
14907 "{br|blr}"
14908 [(set_attr "type" "jmpreg")])
14910 (define_expand "indirect_jump"
14911 [(set (pc) (match_operand 0 "register_operand" ""))])
14913 (define_insn "*indirect_jump<mode>"
14914 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
14915 ""
14916 "@
14917 bctr
14918 {br|blr}"
14919 [(set_attr "type" "jmpreg")])
14921 ;; Table jump for switch statements:
14922 (define_expand "tablejump"
14923 [(use (match_operand 0 "" ""))
14924 (use (label_ref (match_operand 1 "" "")))]
14925 ""
14926 "
14927 {
14928 if (TARGET_32BIT)
14929 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14930 else
14931 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14932 DONE;
14933 }")
14935 (define_expand "tablejumpsi"
14936 [(set (match_dup 3)
14937 (plus:SI (match_operand:SI 0 "" "")
14938 (match_dup 2)))
14939 (parallel [(set (pc) (match_dup 3))
14940 (use (label_ref (match_operand 1 "" "")))])]
14941 "TARGET_32BIT"
14942 "
14943 { operands[0] = force_reg (SImode, operands[0]);
14944 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14945 operands[3] = gen_reg_rtx (SImode);
14946 }")
14948 (define_expand "tablejumpdi"
14949 [(set (match_dup 4)
14950 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
14951 (set (match_dup 3)
14952 (plus:DI (match_dup 4)
14953 (match_dup 2)))
14954 (parallel [(set (pc) (match_dup 3))
14955 (use (label_ref (match_operand 1 "" "")))])]
14956 "TARGET_64BIT"
14957 "
14958 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14959 operands[3] = gen_reg_rtx (DImode);
14960 operands[4] = gen_reg_rtx (DImode);
14961 }")
14963 (define_insn "*tablejump<mode>_internal1"
14964 [(set (pc)
14965 (match_operand:P 0 "register_operand" "c,*l"))
14966 (use (label_ref (match_operand 1 "" "")))]
14967 ""
14968 "@
14969 bctr
14970 {br|blr}"
14971 [(set_attr "type" "jmpreg")])
14973 (define_insn "nop"
14974 [(const_int 0)]
14975 ""
14976 "{cror 0,0,0|nop}")
14977 \f
14978 ;; Define the subtract-one-and-jump insns, starting with the template
14979 ;; so loop.c knows what to generate.
14981 (define_expand "doloop_end"
14982 [(use (match_operand 0 "" "")) ; loop pseudo
14983 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14984 (use (match_operand 2 "" "")) ; max iterations
14985 (use (match_operand 3 "" "")) ; loop level
14986 (use (match_operand 4 "" ""))] ; label
14987 ""
14988 "
14989 {
14990 /* Only use this on innermost loops. */
14991 if (INTVAL (operands[3]) > 1)
14992 FAIL;
14993 if (TARGET_64BIT)
14994 {
14995 if (GET_MODE (operands[0]) != DImode)
14996 FAIL;
14997 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14998 }
14999 else
15000 {
15001 if (GET_MODE (operands[0]) != SImode)
15002 FAIL;
15003 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
15004 }
15005 DONE;
15006 }")
15008 (define_expand "ctr<mode>"
15009 [(parallel [(set (pc)
15010 (if_then_else (ne (match_operand:P 0 "register_operand" "")
15011 (const_int 1))
15012 (label_ref (match_operand 1 "" ""))
15013 (pc)))
15014 (set (match_dup 0)
15015 (plus:P (match_dup 0)
15016 (const_int -1)))
15017 (clobber (match_scratch:CC 2 ""))
15018 (clobber (match_scratch:P 3 ""))])]
15019 ""
15020 "")
15022 ;; We need to be able to do this for any operand, including MEM, or we
15023 ;; will cause reload to blow up since we don't allow output reloads on
15024 ;; JUMP_INSNs.
15025 ;; For the length attribute to be calculated correctly, the
15026 ;; label MUST be operand 0.
15028 (define_insn "*ctr<mode>_internal1"
15029 [(set (pc)
15030 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15031 (const_int 1))
15032 (label_ref (match_operand 0 "" ""))
15033 (pc)))
15034 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15035 (plus:P (match_dup 1)
15036 (const_int -1)))
15037 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15038 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15039 ""
15040 "*
15041 {
15042 if (which_alternative != 0)
15043 return \"#\";
15044 else if (get_attr_length (insn) == 4)
15045 return \"{bdn|bdnz} %l0\";
15046 else
15047 return \"bdz $+8\;b %l0\";
15048 }"
15049 [(set_attr "type" "branch")
15050 (set_attr "length" "*,12,16,16")])
15052 (define_insn "*ctr<mode>_internal2"
15053 [(set (pc)
15054 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15055 (const_int 1))
15056 (pc)
15057 (label_ref (match_operand 0 "" ""))))
15058 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15059 (plus:P (match_dup 1)
15060 (const_int -1)))
15061 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15062 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15063 ""
15064 "*
15065 {
15066 if (which_alternative != 0)
15067 return \"#\";
15068 else if (get_attr_length (insn) == 4)
15069 return \"bdz %l0\";
15070 else
15071 return \"{bdn|bdnz} $+8\;b %l0\";
15072 }"
15073 [(set_attr "type" "branch")
15074 (set_attr "length" "*,12,16,16")])
15076 ;; Similar but use EQ
15078 (define_insn "*ctr<mode>_internal5"
15079 [(set (pc)
15080 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15081 (const_int 1))
15082 (label_ref (match_operand 0 "" ""))
15083 (pc)))
15084 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15085 (plus:P (match_dup 1)
15086 (const_int -1)))
15087 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15088 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15089 ""
15090 "*
15091 {
15092 if (which_alternative != 0)
15093 return \"#\";
15094 else if (get_attr_length (insn) == 4)
15095 return \"bdz %l0\";
15096 else
15097 return \"{bdn|bdnz} $+8\;b %l0\";
15098 }"
15099 [(set_attr "type" "branch")
15100 (set_attr "length" "*,12,16,16")])
15102 (define_insn "*ctr<mode>_internal6"
15103 [(set (pc)
15104 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
15105 (const_int 1))
15106 (pc)
15107 (label_ref (match_operand 0 "" ""))))
15108 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
15109 (plus:P (match_dup 1)
15110 (const_int -1)))
15111 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
15112 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
15113 ""
15114 "*
15115 {
15116 if (which_alternative != 0)
15117 return \"#\";
15118 else if (get_attr_length (insn) == 4)
15119 return \"{bdn|bdnz} %l0\";
15120 else
15121 return \"bdz $+8\;b %l0\";
15122 }"
15123 [(set_attr "type" "branch")
15124 (set_attr "length" "*,12,16,16")])
15126 ;; Now the splitters if we could not allocate the CTR register
15128 (define_split
15129 [(set (pc)
15130 (if_then_else (match_operator 2 "comparison_operator"
15131 [(match_operand:P 1 "gpc_reg_operand" "")
15132 (const_int 1)])
15133 (match_operand 5 "" "")
15134 (match_operand 6 "" "")))
15135 (set (match_operand:P 0 "gpc_reg_operand" "")
15136 (plus:P (match_dup 1) (const_int -1)))
15137 (clobber (match_scratch:CC 3 ""))
15138 (clobber (match_scratch:P 4 ""))]
15139 "reload_completed"
15140 [(parallel [(set (match_dup 3)
15141 (compare:CC (plus:P (match_dup 1)
15142 (const_int -1))
15143 (const_int 0)))
15144 (set (match_dup 0)
15145 (plus:P (match_dup 1)
15146 (const_int -1)))])
15147 (set (pc) (if_then_else (match_dup 7)
15148 (match_dup 5)
15149 (match_dup 6)))]
15150 "
15151 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15152 operands[3], const0_rtx); }")
15154 (define_split
15155 [(set (pc)
15156 (if_then_else (match_operator 2 "comparison_operator"
15157 [(match_operand:P 1 "gpc_reg_operand" "")
15158 (const_int 1)])
15159 (match_operand 5 "" "")
15160 (match_operand 6 "" "")))
15161 (set (match_operand:P 0 "nonimmediate_operand" "")
15162 (plus:P (match_dup 1) (const_int -1)))
15163 (clobber (match_scratch:CC 3 ""))
15164 (clobber (match_scratch:P 4 ""))]
15165 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
15166 [(parallel [(set (match_dup 3)
15167 (compare:CC (plus:P (match_dup 1)
15168 (const_int -1))
15169 (const_int 0)))
15170 (set (match_dup 4)
15171 (plus:P (match_dup 1)
15172 (const_int -1)))])
15173 (set (match_dup 0)
15174 (match_dup 4))
15175 (set (pc) (if_then_else (match_dup 7)
15176 (match_dup 5)
15177 (match_dup 6)))]
15178 "
15179 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
15180 operands[3], const0_rtx); }")
15181 \f
15182 (define_insn "trap"
15183 [(trap_if (const_int 1) (const_int 0))]
15184 ""
15185 "{t 31,0,0|trap}"
15186 [(set_attr "type" "trap")])
15188 (define_expand "ctrap<mode>4"
15189 [(trap_if (match_operator 0 "ordered_comparison_operator"
15190 [(match_operand:GPR 1 "register_operand")
15191 (match_operand:GPR 2 "reg_or_short_operand")])
15192 (match_operand 3 "zero_constant" ""))]
15193 ""
15194 "")
15196 (define_insn ""
15197 [(trap_if (match_operator 0 "ordered_comparison_operator"
15198 [(match_operand:GPR 1 "register_operand" "r")
15199 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
15200 (const_int 0))]
15201 ""
15202 "{t|t<wd>}%V0%I2 %1,%2"
15203 [(set_attr "type" "trap")])
15204 \f
15205 ;; Insns related to generating the function prologue and epilogue.
15207 (define_expand "prologue"
15208 [(use (const_int 0))]
15209 "TARGET_SCHED_PROLOG"
15210 "
15211 {
15212 rs6000_emit_prologue ();
15213 DONE;
15214 }")
15216 (define_insn "*movesi_from_cr_one"
15217 [(match_parallel 0 "mfcr_operation"
15218 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15219 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
15220 (match_operand 3 "immediate_operand" "n")]
15221 UNSPEC_MOVESI_FROM_CR))])]
15222 "TARGET_MFCRF"
15223 "*
15224 {
15225 int mask = 0;
15226 int i;
15227 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15228 {
15229 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15230 operands[4] = GEN_INT (mask);
15231 output_asm_insn (\"mfcr %1,%4\", operands);
15232 }
15233 return \"\";
15234 }"
15235 [(set_attr "type" "mfcrf")])
15237 (define_insn "movesi_from_cr"
15238 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
15239 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
15240 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
15241 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
15242 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
15243 UNSPEC_MOVESI_FROM_CR))]
15244 ""
15245 "mfcr %0"
15246 [(set_attr "type" "mfcr")])
15248 (define_insn "*stmw"
15249 [(match_parallel 0 "stmw_operation"
15250 [(set (match_operand:SI 1 "memory_operand" "=m")
15251 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
15252 "TARGET_MULTIPLE"
15253 "{stm|stmw} %2,%1"
15254 [(set_attr "type" "store_ux")])
15256 (define_insn "*save_gpregs_<mode>"
15257 [(match_parallel 0 "any_parallel_operand"
15258 [(clobber (reg:P 65))
15259 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15260 (use (match_operand:P 2 "gpc_reg_operand" "r"))
15261 (set (match_operand:P 3 "memory_operand" "=m")
15262 (match_operand:P 4 "gpc_reg_operand" "r"))])]
15263 ""
15264 "bl %1"
15265 [(set_attr "type" "branch")
15266 (set_attr "length" "4")])
15268 (define_insn "*save_fpregs_<mode>"
15269 [(match_parallel 0 "any_parallel_operand"
15270 [(clobber (reg:P 65))
15271 (use (match_operand:P 1 "symbol_ref_operand" "s"))
15272 (use (match_operand:P 2 "gpc_reg_operand" "r"))
15273 (set (match_operand:DF 3 "memory_operand" "=m")
15274 (match_operand:DF 4 "gpc_reg_operand" "d"))])]
15275 ""
15276 "bl %1"
15277 [(set_attr "type" "branch")
15278 (set_attr "length" "4")])
15280 ; These are to explain that changes to the stack pointer should
15281 ; not be moved over stores to stack memory.
15282 (define_insn "stack_tie"
15283 [(set (match_operand:BLK 0 "memory_operand" "+m")
15284 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))]
15285 ""
15286 ""
15287 [(set_attr "length" "0")])
15290 (define_expand "epilogue"
15291 [(use (const_int 0))]
15292 "TARGET_SCHED_PROLOG"
15293 "
15294 {
15295 rs6000_emit_epilogue (FALSE);
15296 DONE;
15297 }")
15299 ; On some processors, doing the mtcrf one CC register at a time is
15300 ; faster (like on the 604e). On others, doing them all at once is
15301 ; faster; for instance, on the 601 and 750.
15303 (define_expand "movsi_to_cr_one"
15304 [(set (match_operand:CC 0 "cc_reg_operand" "")
15305 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
15306 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
15307 ""
15308 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
15310 (define_insn "*movsi_to_cr"
15311 [(match_parallel 0 "mtcrf_operation"
15312 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
15313 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
15314 (match_operand 3 "immediate_operand" "n")]
15315 UNSPEC_MOVESI_TO_CR))])]
15316 ""
15317 "*
15318 {
15319 int mask = 0;
15320 int i;
15321 for (i = 0; i < XVECLEN (operands[0], 0); i++)
15322 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
15323 operands[4] = GEN_INT (mask);
15324 return \"mtcrf %4,%2\";
15325 }"
15326 [(set_attr "type" "mtcr")])
15328 (define_insn "*mtcrfsi"
15329 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
15330 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
15331 (match_operand 2 "immediate_operand" "n")]
15332 UNSPEC_MOVESI_TO_CR))]
15333 "GET_CODE (operands[0]) == REG
15334 && CR_REGNO_P (REGNO (operands[0]))
15335 && GET_CODE (operands[2]) == CONST_INT
15336 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
15337 "mtcrf %R0,%1"
15338 [(set_attr "type" "mtcr")])
15340 ; The load-multiple instructions have similar properties.
15341 ; Note that "load_multiple" is a name known to the machine-independent
15342 ; code that actually corresponds to the PowerPC load-string.
15344 (define_insn "*lmw"
15345 [(match_parallel 0 "lmw_operation"
15346 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
15347 (match_operand:SI 2 "memory_operand" "m"))])]
15348 "TARGET_MULTIPLE"
15349 "{lm|lmw} %1,%2"
15350 [(set_attr "type" "load_ux")
15351 (set_attr "cell_micro" "always")])
15353 (define_insn "*return_internal_<mode>"
15354 [(return)
15355 (use (match_operand:P 0 "register_operand" "lc"))]
15356 ""
15357 "b%T0"
15358 [(set_attr "type" "jmpreg")])
15360 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
15361 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
15363 (define_insn "*restore_gpregs_<mode>"
15364 [(match_parallel 0 "any_parallel_operand"
15365 [(clobber (match_operand:P 1 "register_operand" "=l"))
15366 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15367 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15368 (set (match_operand:P 4 "gpc_reg_operand" "=r")
15369 (match_operand:P 5 "memory_operand" "m"))])]
15370 ""
15371 "bl %2"
15372 [(set_attr "type" "branch")
15373 (set_attr "length" "4")])
15375 (define_insn "*return_and_restore_gpregs_<mode>"
15376 [(match_parallel 0 "any_parallel_operand"
15377 [(return)
15378 (clobber (match_operand:P 1 "register_operand" "=l"))
15379 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15380 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15381 (set (match_operand:P 4 "gpc_reg_operand" "=r")
15382 (match_operand:P 5 "memory_operand" "m"))])]
15383 ""
15384 "b %2"
15385 [(set_attr "type" "branch")
15386 (set_attr "length" "4")])
15388 (define_insn "*return_and_restore_fpregs_<mode>"
15389 [(match_parallel 0 "any_parallel_operand"
15390 [(return)
15391 (clobber (match_operand:P 1 "register_operand" "=l"))
15392 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15393 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15394 (set (match_operand:DF 4 "gpc_reg_operand" "=d")
15395 (match_operand:DF 5 "memory_operand" "m"))])]
15396 ""
15397 "b %2"
15398 [(set_attr "type" "branch")
15399 (set_attr "length" "4")])
15401 (define_insn "*return_and_restore_fpregs_aix_<mode>"
15402 [(match_parallel 0 "any_parallel_operand"
15403 [(return)
15404 (use (match_operand:P 1 "register_operand" "l"))
15405 (use (match_operand:P 2 "symbol_ref_operand" "s"))
15406 (use (match_operand:P 3 "gpc_reg_operand" "r"))
15407 (set (match_operand:DF 4 "gpc_reg_operand" "=d")
15408 (match_operand:DF 5 "memory_operand" "m"))])]
15409 ""
15410 "b %2"
15411 [(set_attr "type" "branch")
15412 (set_attr "length" "4")])
15414 ; This is used in compiling the unwind routines.
15415 (define_expand "eh_return"
15416 [(use (match_operand 0 "general_operand" ""))]
15417 ""
15418 "
15419 {
15420 if (TARGET_32BIT)
15421 emit_insn (gen_eh_set_lr_si (operands[0]));
15422 else
15423 emit_insn (gen_eh_set_lr_di (operands[0]));
15424 DONE;
15425 }")
15427 ; We can't expand this before we know where the link register is stored.
15428 (define_insn "eh_set_lr_<mode>"
15429 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
15430 UNSPECV_EH_RR)
15431 (clobber (match_scratch:P 1 "=&b"))]
15432 ""
15433 "#")
15435 (define_split
15436 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
15437 (clobber (match_scratch 1 ""))]
15438 "reload_completed"
15439 [(const_int 0)]
15440 "
15441 {
15442 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
15443 DONE;
15444 }")
15446 (define_insn "prefetch"
15447 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
15448 (match_operand:SI 1 "const_int_operand" "n")
15449 (match_operand:SI 2 "const_int_operand" "n"))]
15450 "TARGET_POWERPC"
15451 "*
15452 {
15453 if (GET_CODE (operands[0]) == REG)
15454 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
15455 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
15456 }"
15457 [(set_attr "type" "load")])
15458 \f
15459 (define_insn "bpermd_<mode>"
15460 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
15461 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
15462 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
15463 "TARGET_POPCNTD"
15464 "bpermd %0,%1,%2"
15465 [(set_attr "type" "integer")])
15467 \f
15469 (include "sync.md")
15470 (include "vector.md")
15471 (include "vsx.md")
15472 (include "altivec.md")
15473 (include "spe.md")
15474 (include "dfp.md")
15475 (include "paired.md")