[RS6000] PR79144, cmpstrnsi optimization breaks glibc
[official-gcc.git] / gcc / lra-spills.c
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1 /* Change pseudos by memory.
2 Copyright (C) 2010-2017 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* This file contains code for a pass to change spilled pseudos into
23 memory.
25 The pass creates necessary stack slots and assigns spilled pseudos
26 to the stack slots in following way:
28 for all spilled pseudos P most frequently used first do
29 for all stack slots S do
30 if P doesn't conflict with pseudos assigned to S then
31 assign S to P and goto to the next pseudo process
32 end
33 end
34 create new stack slot S and assign P to S
35 end
37 The actual algorithm is bit more complicated because of different
38 pseudo sizes.
40 After that the code changes spilled pseudos (except ones created
41 from scratches) by corresponding stack slot memory in RTL.
43 If at least one stack slot was created, we need to run more passes
44 because we have new addresses which should be checked and because
45 the old address displacements might change and address constraints
46 (or insn memory constraints) might not be satisfied any more.
48 For some targets, the pass can spill some pseudos into hard
49 registers of different class (usually into vector registers)
50 instead of spilling them into memory if it is possible and
51 profitable. Spilling GENERAL_REGS pseudo into SSE registers for
52 Intel Corei7 is an example of such optimization. And this is
53 actually recommended by Intel optimization guide.
55 The file also contains code for final change of pseudos on hard
56 regs correspondingly assigned to them. */
58 #include "config.h"
59 #include "system.h"
60 #include "coretypes.h"
61 #include "backend.h"
62 #include "target.h"
63 #include "rtl.h"
64 #include "df.h"
65 #include "insn-config.h"
66 #include "regs.h"
67 #include "memmodel.h"
68 #include "ira.h"
69 #include "recog.h"
70 #include "output.h"
71 #include "cfgrtl.h"
72 #include "lra.h"
73 #include "lra-int.h"
76 /* Max regno at the start of the pass. */
77 static int regs_num;
79 /* Map spilled regno -> hard regno used instead of memory for
80 spilling. */
81 static rtx *spill_hard_reg;
83 /* The structure describes stack slot of a spilled pseudo. */
84 struct pseudo_slot
86 /* Number (0, 1, ...) of the stack slot to which given pseudo
87 belongs. */
88 int slot_num;
89 /* First or next slot with the same slot number. */
90 struct pseudo_slot *next, *first;
91 /* Memory representing the spilled pseudo. */
92 rtx mem;
95 /* The stack slots for each spilled pseudo. Indexed by regnos. */
96 static struct pseudo_slot *pseudo_slots;
98 /* The structure describes a register or a stack slot which can be
99 used for several spilled pseudos. */
100 struct slot
102 /* First pseudo with given stack slot. */
103 int regno;
104 /* Hard reg into which the slot pseudos are spilled. The value is
105 negative for pseudos spilled into memory. */
106 int hard_regno;
107 /* Maximum alignment required by all users of the slot. */
108 unsigned int align;
109 /* Maximum size required by all users of the slot. */
110 HOST_WIDE_INT size;
111 /* Memory representing the all stack slot. It can be different from
112 memory representing a pseudo belonging to give stack slot because
113 pseudo can be placed in a part of the corresponding stack slot.
114 The value is NULL for pseudos spilled into a hard reg. */
115 rtx mem;
116 /* Combined live ranges of all pseudos belonging to given slot. It
117 is used to figure out that a new spilled pseudo can use given
118 stack slot. */
119 lra_live_range_t live_ranges;
122 /* Array containing info about the stack slots. The array element is
123 indexed by the stack slot number in the range [0..slots_num). */
124 static struct slot *slots;
125 /* The number of the stack slots currently existing. */
126 static int slots_num;
128 /* Set up memory of the spilled pseudo I. The function can allocate
129 the corresponding stack slot if it is not done yet. */
130 static void
131 assign_mem_slot (int i)
133 rtx x = NULL_RTX;
134 machine_mode mode = GET_MODE (regno_reg_rtx[i]);
135 HOST_WIDE_INT inherent_size = PSEUDO_REGNO_BYTES (i);
136 machine_mode wider_mode
137 = (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (lra_reg_info[i].biggest_mode)
138 ? mode : lra_reg_info[i].biggest_mode);
139 HOST_WIDE_INT total_size = GET_MODE_SIZE (wider_mode);
140 HOST_WIDE_INT adjust = 0;
142 lra_assert (regno_reg_rtx[i] != NULL_RTX && REG_P (regno_reg_rtx[i])
143 && lra_reg_info[i].nrefs != 0 && reg_renumber[i] < 0);
145 unsigned int slot_num = pseudo_slots[i].slot_num;
146 x = slots[slot_num].mem;
147 if (!x)
149 x = assign_stack_local (BLKmode, slots[slot_num].size,
150 slots[slot_num].align);
151 slots[slot_num].mem = x;
154 /* On a big endian machine, the "address" of the slot is the address
155 of the low part that fits its inherent mode. */
156 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
157 adjust += (total_size - inherent_size);
159 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
161 /* Set all of the memory attributes as appropriate for a spill. */
162 set_mem_attrs_for_spill (x);
163 pseudo_slots[i].mem = x;
166 /* Sort pseudos according their usage frequencies. */
167 static int
168 regno_freq_compare (const void *v1p, const void *v2p)
170 const int regno1 = *(const int *) v1p;
171 const int regno2 = *(const int *) v2p;
172 int diff;
174 if ((diff = lra_reg_info[regno2].freq - lra_reg_info[regno1].freq) != 0)
175 return diff;
176 return regno1 - regno2;
179 /* Sort pseudos according to their slots, putting the slots in the order
180 that they should be allocated. Slots with lower numbers have the highest
181 priority and should get the smallest displacement from the stack or
182 frame pointer (whichever is being used).
184 The first allocated slot is always closest to the frame pointer,
185 so prefer lower slot numbers when frame_pointer_needed. If the stack
186 and frame grow in the same direction, then the first allocated slot is
187 always closest to the initial stack pointer and furthest away from the
188 final stack pointer, so allocate higher numbers first when using the
189 stack pointer in that case. The reverse is true if the stack and
190 frame grow in opposite directions. */
191 static int
192 pseudo_reg_slot_compare (const void *v1p, const void *v2p)
194 const int regno1 = *(const int *) v1p;
195 const int regno2 = *(const int *) v2p;
196 int diff, slot_num1, slot_num2;
197 int total_size1, total_size2;
199 slot_num1 = pseudo_slots[regno1].slot_num;
200 slot_num2 = pseudo_slots[regno2].slot_num;
201 if ((diff = slot_num1 - slot_num2) != 0)
202 return (frame_pointer_needed
203 || (!FRAME_GROWS_DOWNWARD) == STACK_GROWS_DOWNWARD ? diff : -diff);
204 total_size1 = GET_MODE_SIZE (lra_reg_info[regno1].biggest_mode);
205 total_size2 = GET_MODE_SIZE (lra_reg_info[regno2].biggest_mode);
206 if ((diff = total_size2 - total_size1) != 0)
207 return diff;
208 return regno1 - regno2;
211 /* Assign spill hard registers to N pseudos in PSEUDO_REGNOS which is
212 sorted in order of highest frequency first. Put the pseudos which
213 did not get a spill hard register at the beginning of array
214 PSEUDO_REGNOS. Return the number of such pseudos. */
215 static int
216 assign_spill_hard_regs (int *pseudo_regnos, int n)
218 int i, k, p, regno, res, spill_class_size, hard_regno, nr;
219 enum reg_class rclass, spill_class;
220 machine_mode mode;
221 lra_live_range_t r;
222 rtx_insn *insn;
223 rtx set;
224 basic_block bb;
225 HARD_REG_SET conflict_hard_regs;
226 bitmap_head ok_insn_bitmap;
227 bitmap setjump_crosses = regstat_get_setjmp_crosses ();
228 /* Hard registers which can not be used for any purpose at given
229 program point because they are unallocatable or already allocated
230 for other pseudos. */
231 HARD_REG_SET *reserved_hard_regs;
233 if (! lra_reg_spill_p)
234 return n;
235 /* Set up reserved hard regs for every program point. */
236 reserved_hard_regs = XNEWVEC (HARD_REG_SET, lra_live_max_point);
237 for (p = 0; p < lra_live_max_point; p++)
238 COPY_HARD_REG_SET (reserved_hard_regs[p], lra_no_alloc_regs);
239 for (i = FIRST_PSEUDO_REGISTER; i < regs_num; i++)
240 if (lra_reg_info[i].nrefs != 0
241 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
242 for (r = lra_reg_info[i].live_ranges; r != NULL; r = r->next)
243 for (p = r->start; p <= r->finish; p++)
244 add_to_hard_reg_set (&reserved_hard_regs[p],
245 lra_reg_info[i].biggest_mode, hard_regno);
246 bitmap_initialize (&ok_insn_bitmap, &reg_obstack);
247 FOR_EACH_BB_FN (bb, cfun)
248 FOR_BB_INSNS (bb, insn)
249 if (DEBUG_INSN_P (insn)
250 || ((set = single_set (insn)) != NULL_RTX
251 && REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))))
252 bitmap_set_bit (&ok_insn_bitmap, INSN_UID (insn));
253 for (res = i = 0; i < n; i++)
255 regno = pseudo_regnos[i];
256 rclass = lra_get_allocno_class (regno);
257 if (bitmap_bit_p (setjump_crosses, regno)
258 || (spill_class
259 = ((enum reg_class)
260 targetm.spill_class ((reg_class_t) rclass,
261 PSEUDO_REGNO_MODE (regno)))) == NO_REGS
262 || bitmap_intersect_compl_p (&lra_reg_info[regno].insn_bitmap,
263 &ok_insn_bitmap))
265 pseudo_regnos[res++] = regno;
266 continue;
268 lra_assert (spill_class != NO_REGS);
269 COPY_HARD_REG_SET (conflict_hard_regs,
270 lra_reg_info[regno].conflict_hard_regs);
271 for (r = lra_reg_info[regno].live_ranges; r != NULL; r = r->next)
272 for (p = r->start; p <= r->finish; p++)
273 IOR_HARD_REG_SET (conflict_hard_regs, reserved_hard_regs[p]);
274 spill_class_size = ira_class_hard_regs_num[spill_class];
275 mode = lra_reg_info[regno].biggest_mode;
276 for (k = 0; k < spill_class_size; k++)
278 hard_regno = ira_class_hard_regs[spill_class][k];
279 if (! overlaps_hard_reg_set_p (conflict_hard_regs, mode, hard_regno))
280 break;
282 if (k >= spill_class_size)
284 /* There is no available regs -- assign memory later. */
285 pseudo_regnos[res++] = regno;
286 continue;
288 if (lra_dump_file != NULL)
289 fprintf (lra_dump_file, " Spill r%d into hr%d\n", regno, hard_regno);
290 /* Update reserved_hard_regs. */
291 for (r = lra_reg_info[regno].live_ranges; r != NULL; r = r->next)
292 for (p = r->start; p <= r->finish; p++)
293 add_to_hard_reg_set (&reserved_hard_regs[p],
294 lra_reg_info[regno].biggest_mode, hard_regno);
295 spill_hard_reg[regno]
296 = gen_raw_REG (PSEUDO_REGNO_MODE (regno), hard_regno);
297 for (nr = 0;
298 nr < hard_regno_nregs[hard_regno][lra_reg_info[regno].biggest_mode];
299 nr++)
300 /* Just loop. */
301 df_set_regs_ever_live (hard_regno + nr, true);
303 bitmap_clear (&ok_insn_bitmap);
304 free (reserved_hard_regs);
305 return res;
308 /* Add pseudo REGNO to slot SLOT_NUM. */
309 static void
310 add_pseudo_to_slot (int regno, int slot_num)
312 struct pseudo_slot *first;
314 /* Each pseudo has an inherent size which comes from its own mode,
315 and a total size which provides room for paradoxical subregs.
316 We need to make sure the size and alignment of the slot are
317 sufficient for both. */
318 machine_mode mode = (GET_MODE_SIZE (PSEUDO_REGNO_MODE (regno))
319 >= GET_MODE_SIZE (lra_reg_info[regno].biggest_mode)
320 ? PSEUDO_REGNO_MODE (regno)
321 : lra_reg_info[regno].biggest_mode);
322 unsigned int align = spill_slot_alignment (mode);
323 slots[slot_num].align = MAX (slots[slot_num].align, align);
324 slots[slot_num].size = MAX (slots[slot_num].size, GET_MODE_SIZE (mode));
326 if (slots[slot_num].regno < 0)
328 /* It is the first pseudo in the slot. */
329 slots[slot_num].regno = regno;
330 pseudo_slots[regno].first = &pseudo_slots[regno];
331 pseudo_slots[regno].next = NULL;
333 else
335 first = pseudo_slots[regno].first = &pseudo_slots[slots[slot_num].regno];
336 pseudo_slots[regno].next = first->next;
337 first->next = &pseudo_slots[regno];
339 pseudo_slots[regno].mem = NULL_RTX;
340 pseudo_slots[regno].slot_num = slot_num;
341 slots[slot_num].live_ranges
342 = lra_merge_live_ranges (slots[slot_num].live_ranges,
343 lra_copy_live_range_list
344 (lra_reg_info[regno].live_ranges));
347 /* Assign stack slot numbers to pseudos in array PSEUDO_REGNOS of
348 length N. Sort pseudos in PSEUDO_REGNOS for subsequent assigning
349 memory stack slots. */
350 static void
351 assign_stack_slot_num_and_sort_pseudos (int *pseudo_regnos, int n)
353 int i, j, regno;
355 slots_num = 0;
356 /* Assign stack slot numbers to spilled pseudos, use smaller numbers
357 for most frequently used pseudos. */
358 for (i = 0; i < n; i++)
360 regno = pseudo_regnos[i];
361 if (! flag_ira_share_spill_slots)
362 j = slots_num;
363 else
365 for (j = 0; j < slots_num; j++)
366 if (slots[j].hard_regno < 0
367 && ! (lra_intersected_live_ranges_p
368 (slots[j].live_ranges,
369 lra_reg_info[regno].live_ranges)))
370 break;
372 if (j >= slots_num)
374 /* New slot. */
375 slots[j].live_ranges = NULL;
376 slots[j].size = 0;
377 slots[j].align = BITS_PER_UNIT;
378 slots[j].regno = slots[j].hard_regno = -1;
379 slots[j].mem = NULL_RTX;
380 slots_num++;
382 add_pseudo_to_slot (regno, j);
384 /* Sort regnos according to their slot numbers. */
385 qsort (pseudo_regnos, n, sizeof (int), pseudo_reg_slot_compare);
388 /* Recursively process LOC in INSN and change spilled pseudos to the
389 corresponding memory or spilled hard reg. Ignore spilled pseudos
390 created from the scratches. Return true if the pseudo nrefs equal
391 to 0 (don't change the pseudo in this case). Otherwise return false. */
392 static bool
393 remove_pseudos (rtx *loc, rtx_insn *insn)
395 int i;
396 rtx hard_reg;
397 const char *fmt;
398 enum rtx_code code;
399 bool res = false;
401 if (*loc == NULL_RTX)
402 return res;
403 code = GET_CODE (*loc);
404 if (code == REG && (i = REGNO (*loc)) >= FIRST_PSEUDO_REGISTER
405 && lra_get_regno_hard_regno (i) < 0
406 /* We do not want to assign memory for former scratches because
407 it might result in an address reload for some targets. In
408 any case we transform such pseudos not getting hard registers
409 into scratches back. */
410 && ! lra_former_scratch_p (i))
412 if (lra_reg_info[i].nrefs == 0
413 && pseudo_slots[i].mem == NULL && spill_hard_reg[i] == NULL)
414 return true;
415 if ((hard_reg = spill_hard_reg[i]) != NULL_RTX)
416 *loc = copy_rtx (hard_reg);
417 else
419 rtx x = lra_eliminate_regs_1 (insn, pseudo_slots[i].mem,
420 GET_MODE (pseudo_slots[i].mem),
421 false, false, 0, true);
422 *loc = x != pseudo_slots[i].mem ? x : copy_rtx (x);
424 return res;
427 fmt = GET_RTX_FORMAT (code);
428 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
430 if (fmt[i] == 'e')
431 res = remove_pseudos (&XEXP (*loc, i), insn) || res;
432 else if (fmt[i] == 'E')
434 int j;
436 for (j = XVECLEN (*loc, i) - 1; j >= 0; j--)
437 res = remove_pseudos (&XVECEXP (*loc, i, j), insn) || res;
440 return res;
443 /* Convert spilled pseudos into their stack slots or spill hard regs,
444 put insns to process on the constraint stack (that is all insns in
445 which pseudos were changed to memory or spill hard regs). */
446 static void
447 spill_pseudos (void)
449 basic_block bb;
450 rtx_insn *insn, *curr;
451 int i;
452 bitmap_head spilled_pseudos, changed_insns;
454 bitmap_initialize (&spilled_pseudos, &reg_obstack);
455 bitmap_initialize (&changed_insns, &reg_obstack);
456 for (i = FIRST_PSEUDO_REGISTER; i < regs_num; i++)
458 if (lra_reg_info[i].nrefs != 0 && lra_get_regno_hard_regno (i) < 0
459 && ! lra_former_scratch_p (i))
461 bitmap_set_bit (&spilled_pseudos, i);
462 bitmap_ior_into (&changed_insns, &lra_reg_info[i].insn_bitmap);
465 FOR_EACH_BB_FN (bb, cfun)
467 FOR_BB_INSNS_SAFE (bb, insn, curr)
469 bool removed_pseudo_p = false;
471 if (bitmap_bit_p (&changed_insns, INSN_UID (insn)))
473 rtx *link_loc, link;
475 removed_pseudo_p = remove_pseudos (&PATTERN (insn), insn);
476 if (CALL_P (insn)
477 && remove_pseudos (&CALL_INSN_FUNCTION_USAGE (insn), insn))
478 removed_pseudo_p = true;
479 for (link_loc = &REG_NOTES (insn);
480 (link = *link_loc) != NULL_RTX;
481 link_loc = &XEXP (link, 1))
483 switch (REG_NOTE_KIND (link))
485 case REG_FRAME_RELATED_EXPR:
486 case REG_CFA_DEF_CFA:
487 case REG_CFA_ADJUST_CFA:
488 case REG_CFA_OFFSET:
489 case REG_CFA_REGISTER:
490 case REG_CFA_EXPRESSION:
491 case REG_CFA_RESTORE:
492 case REG_CFA_SET_VDRAP:
493 if (remove_pseudos (&XEXP (link, 0), insn))
494 removed_pseudo_p = true;
495 break;
496 default:
497 break;
500 if (lra_dump_file != NULL)
501 fprintf (lra_dump_file,
502 "Changing spilled pseudos to memory in insn #%u\n",
503 INSN_UID (insn));
504 lra_push_insn (insn);
505 if (lra_reg_spill_p || targetm.different_addr_displacement_p ())
506 lra_set_used_insn_alternative (insn, -1);
508 else if (CALL_P (insn)
509 /* Presence of any pseudo in CALL_INSN_FUNCTION_USAGE
510 does not affect value of insn_bitmap of the
511 corresponding lra_reg_info. That is because we
512 don't need to reload pseudos in
513 CALL_INSN_FUNCTION_USAGEs. So if we process only
514 insns in the insn_bitmap of given pseudo here, we
515 can miss the pseudo in some
516 CALL_INSN_FUNCTION_USAGEs. */
517 && remove_pseudos (&CALL_INSN_FUNCTION_USAGE (insn), insn))
518 removed_pseudo_p = true;
519 if (removed_pseudo_p)
521 lra_assert (DEBUG_INSN_P (insn));
522 lra_invalidate_insn_data (insn);
523 INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC ();
524 if (lra_dump_file != NULL)
525 fprintf (lra_dump_file,
526 "Debug insn #%u is reset because it referenced "
527 "removed pseudo\n", INSN_UID (insn));
529 bitmap_and_compl_into (df_get_live_in (bb), &spilled_pseudos);
530 bitmap_and_compl_into (df_get_live_out (bb), &spilled_pseudos);
533 bitmap_clear (&spilled_pseudos);
534 bitmap_clear (&changed_insns);
537 /* Return true if we need to change some pseudos into memory. */
538 bool
539 lra_need_for_spills_p (void)
541 int i; max_regno = max_reg_num ();
543 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
544 if (lra_reg_info[i].nrefs != 0 && lra_get_regno_hard_regno (i) < 0
545 && ! lra_former_scratch_p (i))
546 return true;
547 return false;
550 /* Change spilled pseudos into memory or spill hard regs. Put changed
551 insns on the constraint stack (these insns will be considered on
552 the next constraint pass). The changed insns are all insns in
553 which pseudos were changed. */
554 void
555 lra_spill (void)
557 int i, n, curr_regno;
558 int *pseudo_regnos;
560 regs_num = max_reg_num ();
561 spill_hard_reg = XNEWVEC (rtx, regs_num);
562 pseudo_regnos = XNEWVEC (int, regs_num);
563 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < regs_num; i++)
564 if (lra_reg_info[i].nrefs != 0 && lra_get_regno_hard_regno (i) < 0
565 /* We do not want to assign memory for former scratches. */
566 && ! lra_former_scratch_p (i))
567 pseudo_regnos[n++] = i;
568 lra_assert (n > 0);
569 pseudo_slots = XNEWVEC (struct pseudo_slot, regs_num);
570 for (i = FIRST_PSEUDO_REGISTER; i < regs_num; i++)
572 spill_hard_reg[i] = NULL_RTX;
573 pseudo_slots[i].mem = NULL_RTX;
575 slots = XNEWVEC (struct slot, regs_num);
576 /* Sort regnos according their usage frequencies. */
577 qsort (pseudo_regnos, n, sizeof (int), regno_freq_compare);
578 n = assign_spill_hard_regs (pseudo_regnos, n);
579 assign_stack_slot_num_and_sort_pseudos (pseudo_regnos, n);
580 for (i = 0; i < n; i++)
581 if (pseudo_slots[pseudo_regnos[i]].mem == NULL_RTX)
582 assign_mem_slot (pseudo_regnos[i]);
583 if (n > 0 && crtl->stack_alignment_needed)
584 /* If we have a stack frame, we must align it now. The stack size
585 may be a part of the offset computation for register
586 elimination. */
587 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
588 if (lra_dump_file != NULL)
590 for (i = 0; i < slots_num; i++)
592 fprintf (lra_dump_file, " Slot %d regnos (width = %d):", i,
593 GET_MODE_SIZE (GET_MODE (slots[i].mem)));
594 for (curr_regno = slots[i].regno;;
595 curr_regno = pseudo_slots[curr_regno].next - pseudo_slots)
597 fprintf (lra_dump_file, " %d", curr_regno);
598 if (pseudo_slots[curr_regno].next == NULL)
599 break;
601 fprintf (lra_dump_file, "\n");
604 spill_pseudos ();
605 free (slots);
606 free (pseudo_slots);
607 free (pseudo_regnos);
608 free (spill_hard_reg);
611 /* Apply alter_subreg for subregs of regs in *LOC. Use FINAL_P for
612 alter_subreg calls. Return true if any subreg of reg is
613 processed. */
614 static bool
615 alter_subregs (rtx *loc, bool final_p)
617 int i;
618 rtx x = *loc;
619 bool res;
620 const char *fmt;
621 enum rtx_code code;
623 if (x == NULL_RTX)
624 return false;
625 code = GET_CODE (x);
626 if (code == SUBREG && REG_P (SUBREG_REG (x)))
628 lra_assert (REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER);
629 alter_subreg (loc, final_p);
630 return true;
632 fmt = GET_RTX_FORMAT (code);
633 res = false;
634 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
636 if (fmt[i] == 'e')
638 if (alter_subregs (&XEXP (x, i), final_p))
639 res = true;
641 else if (fmt[i] == 'E')
643 int j;
645 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
646 if (alter_subregs (&XVECEXP (x, i, j), final_p))
647 res = true;
650 return res;
653 /* Return true if REGNO is used for return in the current
654 function. */
655 static bool
656 return_regno_p (unsigned int regno)
658 rtx outgoing = crtl->return_rtx;
660 if (! outgoing)
661 return false;
663 if (REG_P (outgoing))
664 return REGNO (outgoing) == regno;
665 else if (GET_CODE (outgoing) == PARALLEL)
667 int i;
669 for (i = 0; i < XVECLEN (outgoing, 0); i++)
671 rtx x = XEXP (XVECEXP (outgoing, 0, i), 0);
673 if (REG_P (x) && REGNO (x) == regno)
674 return true;
677 return false;
680 /* Return true if REGNO is in one of subsequent USE after INSN in the
681 same BB. */
682 static bool
683 regno_in_use_p (rtx_insn *insn, unsigned int regno)
685 static lra_insn_recog_data_t id;
686 static struct lra_static_insn_data *static_id;
687 struct lra_insn_reg *reg;
688 int i, arg_regno;
689 basic_block bb = BLOCK_FOR_INSN (insn);
691 while ((insn = next_nondebug_insn (insn)) != NULL_RTX)
693 if (BARRIER_P (insn) || bb != BLOCK_FOR_INSN (insn))
694 return false;
695 if (! INSN_P (insn))
696 continue;
697 if (GET_CODE (PATTERN (insn)) == USE
698 && REG_P (XEXP (PATTERN (insn), 0))
699 && regno == REGNO (XEXP (PATTERN (insn), 0)))
700 return true;
701 /* Check that the regno is not modified. */
702 id = lra_get_insn_recog_data (insn);
703 for (reg = id->regs; reg != NULL; reg = reg->next)
704 if (reg->type != OP_IN && reg->regno == (int) regno)
705 return false;
706 static_id = id->insn_static_data;
707 for (reg = static_id->hard_regs; reg != NULL; reg = reg->next)
708 if (reg->type != OP_IN && reg->regno == (int) regno)
709 return false;
710 if (id->arg_hard_regs != NULL)
711 for (i = 0; (arg_regno = id->arg_hard_regs[i]) >= 0; i++)
712 if ((int) regno == (arg_regno >= FIRST_PSEUDO_REGISTER
713 ? arg_regno : arg_regno - FIRST_PSEUDO_REGISTER))
714 return false;
716 return false;
719 /* Final change of pseudos got hard registers into the corresponding
720 hard registers and removing temporary clobbers. */
721 void
722 lra_final_code_change (void)
724 int i, hard_regno;
725 basic_block bb;
726 rtx_insn *insn, *curr;
727 int max_regno = max_reg_num ();
729 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
730 if (lra_reg_info[i].nrefs != 0
731 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0)
732 SET_REGNO (regno_reg_rtx[i], hard_regno);
733 FOR_EACH_BB_FN (bb, cfun)
734 FOR_BB_INSNS_SAFE (bb, insn, curr)
735 if (INSN_P (insn))
737 rtx pat = PATTERN (insn);
739 if (GET_CODE (pat) == CLOBBER && LRA_TEMP_CLOBBER_P (pat))
741 /* Remove clobbers temporarily created in LRA. We don't
742 need them anymore and don't want to waste compiler
743 time processing them in a few subsequent passes. */
744 lra_invalidate_insn_data (insn);
745 delete_insn (insn);
746 continue;
749 /* IRA can generate move insns involving pseudos. It is
750 better remove them earlier to speed up compiler a bit.
751 It is also better to do it here as they might not pass
752 final RTL check in LRA, (e.g. insn moving a control
753 register into itself). So remove an useless move insn
754 unless next insn is USE marking the return reg (we should
755 save this as some subsequent optimizations assume that
756 such original insns are saved). */
757 if (NONJUMP_INSN_P (insn) && GET_CODE (pat) == SET
758 && REG_P (SET_SRC (pat)) && REG_P (SET_DEST (pat))
759 && REGNO (SET_SRC (pat)) == REGNO (SET_DEST (pat))
760 && (! return_regno_p (REGNO (SET_SRC (pat)))
761 || ! regno_in_use_p (insn, REGNO (SET_SRC (pat)))))
763 lra_invalidate_insn_data (insn);
764 delete_insn (insn);
765 continue;
768 lra_insn_recog_data_t id = lra_get_insn_recog_data (insn);
769 struct lra_insn_reg *reg;
771 for (reg = id->regs; reg != NULL; reg = reg->next)
772 if (reg->regno >= FIRST_PSEUDO_REGISTER
773 && lra_reg_info [reg->regno].nrefs == 0)
774 break;
776 if (reg != NULL)
778 /* Pseudos still can be in debug insns in some very rare
779 and complicated cases, e.g. the pseudo was removed by
780 inheritance and the debug insn is not EBBs where the
781 inheritance happened. It is difficult and time
782 consuming to find what hard register corresponds the
783 pseudo -- so just remove the debug insn. Another
784 solution could be assigning hard reg/memory but it
785 would be a misleading info. It is better not to have
786 info than have it wrong. */
787 lra_assert (DEBUG_INSN_P (insn));
788 lra_invalidate_insn_data (insn);
789 delete_insn (insn);
790 continue;
793 struct lra_static_insn_data *static_id = id->insn_static_data;
794 bool insn_change_p = false;
796 for (i = id->insn_static_data->n_operands - 1; i >= 0; i--)
797 if ((DEBUG_INSN_P (insn) || ! static_id->operand[i].is_operator)
798 && alter_subregs (id->operand_loc[i], ! DEBUG_INSN_P (insn)))
800 lra_update_dup (id, i);
801 insn_change_p = true;
803 if (insn_change_p)
804 lra_update_operator_dups (id);