1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
80 #include "coretypes.h"
94 #include "stor-layout.h"
96 #include "cfgcleanup.h"
97 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
99 #include "insn-attr.h"
100 #include "rtlhooks-def.h"
102 #include "tree-pass.h"
103 #include "valtrack.h"
104 #include "rtl-iter.h"
105 #include "print-rtl.h"
107 #ifndef LOAD_EXTEND_OP
108 #define LOAD_EXTEND_OP(M) UNKNOWN
111 /* Number of attempts to combine instructions in this function. */
113 static int combine_attempts
;
115 /* Number of attempts that got as far as substitution in this function. */
117 static int combine_merges
;
119 /* Number of instructions combined with added SETs in this function. */
121 static int combine_extras
;
123 /* Number of instructions combined in this function. */
125 static int combine_successes
;
127 /* Totals over entire compilation. */
129 static int total_attempts
, total_merges
, total_extras
, total_successes
;
131 /* combine_instructions may try to replace the right hand side of the
132 second instruction with the value of an associated REG_EQUAL note
133 before throwing it at try_combine. That is problematic when there
134 is a REG_DEAD note for a register used in the old right hand side
135 and can cause distribute_notes to do wrong things. This is the
136 second instruction if it has been so modified, null otherwise. */
138 static rtx_insn
*i2mod
;
140 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
142 static rtx i2mod_old_rhs
;
144 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
146 static rtx i2mod_new_rhs
;
148 struct reg_stat_type
{
149 /* Record last point of death of (hard or pseudo) register n. */
150 rtx_insn
*last_death
;
152 /* Record last point of modification of (hard or pseudo) register n. */
155 /* The next group of fields allows the recording of the last value assigned
156 to (hard or pseudo) register n. We use this information to see if an
157 operation being processed is redundant given a prior operation performed
158 on the register. For example, an `and' with a constant is redundant if
159 all the zero bits are already known to be turned off.
161 We use an approach similar to that used by cse, but change it in the
164 (1) We do not want to reinitialize at each label.
165 (2) It is useful, but not critical, to know the actual value assigned
166 to a register. Often just its form is helpful.
168 Therefore, we maintain the following fields:
170 last_set_value the last value assigned
171 last_set_label records the value of label_tick when the
172 register was assigned
173 last_set_table_tick records the value of label_tick when a
174 value using the register is assigned
175 last_set_invalid set to nonzero when it is not valid
176 to use the value of this register in some
179 To understand the usage of these tables, it is important to understand
180 the distinction between the value in last_set_value being valid and
181 the register being validly contained in some other expression in the
184 (The next two parameters are out of date).
186 reg_stat[i].last_set_value is valid if it is nonzero, and either
187 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
189 Register I may validly appear in any expression returned for the value
190 of another register if reg_n_sets[i] is 1. It may also appear in the
191 value for register J if reg_stat[j].last_set_invalid is zero, or
192 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
194 If an expression is found in the table containing a register which may
195 not validly appear in an expression, the register is replaced by
196 something that won't match, (clobber (const_int 0)). */
198 /* Record last value assigned to (hard or pseudo) register n. */
202 /* Record the value of label_tick when an expression involving register n
203 is placed in last_set_value. */
205 int last_set_table_tick
;
207 /* Record the value of label_tick when the value for register n is placed in
212 /* These fields are maintained in parallel with last_set_value and are
213 used to store the mode in which the register was last set, the bits
214 that were known to be zero when it was last set, and the number of
215 sign bits copies it was known to have when it was last set. */
217 unsigned HOST_WIDE_INT last_set_nonzero_bits
;
218 char last_set_sign_bit_copies
;
219 ENUM_BITFIELD(machine_mode
) last_set_mode
: 8;
221 /* Set nonzero if references to register n in expressions should not be
222 used. last_set_invalid is set nonzero when this register is being
223 assigned to and last_set_table_tick == label_tick. */
225 char last_set_invalid
;
227 /* Some registers that are set more than once and used in more than one
228 basic block are nevertheless always set in similar ways. For example,
229 a QImode register may be loaded from memory in two places on a machine
230 where byte loads zero extend.
232 We record in the following fields if a register has some leading bits
233 that are always equal to the sign bit, and what we know about the
234 nonzero bits of a register, specifically which bits are known to be
237 If an entry is zero, it means that we don't know anything special. */
239 unsigned char sign_bit_copies
;
241 unsigned HOST_WIDE_INT nonzero_bits
;
243 /* Record the value of the label_tick when the last truncation
244 happened. The field truncated_to_mode is only valid if
245 truncation_label == label_tick. */
247 int truncation_label
;
249 /* Record the last truncation seen for this register. If truncation
250 is not a nop to this mode we might be able to save an explicit
251 truncation if we know that value already contains a truncated
254 ENUM_BITFIELD(machine_mode
) truncated_to_mode
: 8;
258 static vec
<reg_stat_type
> reg_stat
;
260 /* One plus the highest pseudo for which we track REG_N_SETS.
261 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
262 but during combine_split_insns new pseudos can be created. As we don't have
263 updated DF information in that case, it is hard to initialize the array
264 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
265 so instead of growing the arrays, just assume all newly created pseudos
266 during combine might be set multiple times. */
268 static unsigned int reg_n_sets_max
;
270 /* Record the luid of the last insn that invalidated memory
271 (anything that writes memory, and subroutine calls, but not pushes). */
273 static int mem_last_set
;
275 /* Record the luid of the last CALL_INSN
276 so we can tell whether a potential combination crosses any calls. */
278 static int last_call_luid
;
280 /* When `subst' is called, this is the insn that is being modified
281 (by combining in a previous insn). The PATTERN of this insn
282 is still the old pattern partially modified and it should not be
283 looked at, but this may be used to examine the successors of the insn
284 to judge whether a simplification is valid. */
286 static rtx_insn
*subst_insn
;
288 /* This is the lowest LUID that `subst' is currently dealing with.
289 get_last_value will not return a value if the register was set at or
290 after this LUID. If not for this mechanism, we could get confused if
291 I2 or I1 in try_combine were an insn that used the old value of a register
292 to obtain a new value. In that case, we might erroneously get the
293 new value of the register when we wanted the old one. */
295 static int subst_low_luid
;
297 /* This contains any hard registers that are used in newpat; reg_dead_at_p
298 must consider all these registers to be always live. */
300 static HARD_REG_SET newpat_used_regs
;
302 /* This is an insn to which a LOG_LINKS entry has been added. If this
303 insn is the earlier than I2 or I3, combine should rescan starting at
306 static rtx_insn
*added_links_insn
;
308 /* Basic block in which we are performing combines. */
309 static basic_block this_basic_block
;
310 static bool optimize_this_for_speed_p
;
313 /* Length of the currently allocated uid_insn_cost array. */
315 static int max_uid_known
;
317 /* The following array records the insn_rtx_cost for every insn
318 in the instruction stream. */
320 static int *uid_insn_cost
;
322 /* The following array records the LOG_LINKS for every insn in the
323 instruction stream as struct insn_link pointers. */
328 struct insn_link
*next
;
331 static struct insn_link
**uid_log_links
;
333 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
334 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
336 #define FOR_EACH_LOG_LINK(L, INSN) \
337 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
339 /* Links for LOG_LINKS are allocated from this obstack. */
341 static struct obstack insn_link_obstack
;
343 /* Allocate a link. */
345 static inline struct insn_link
*
346 alloc_insn_link (rtx_insn
*insn
, unsigned int regno
, struct insn_link
*next
)
349 = (struct insn_link
*) obstack_alloc (&insn_link_obstack
,
350 sizeof (struct insn_link
));
357 /* Incremented for each basic block. */
359 static int label_tick
;
361 /* Reset to label_tick for each extended basic block in scanning order. */
363 static int label_tick_ebb_start
;
365 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
366 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
368 static machine_mode nonzero_bits_mode
;
370 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
371 be safely used. It is zero while computing them and after combine has
372 completed. This former test prevents propagating values based on
373 previously set values, which can be incorrect if a variable is modified
376 static int nonzero_sign_valid
;
379 /* Record one modification to rtl structure
380 to be undone by storing old_contents into *where. */
382 enum undo_kind
{ UNDO_RTX
, UNDO_INT
, UNDO_MODE
, UNDO_LINKS
};
388 union { rtx r
; int i
; machine_mode m
; struct insn_link
*l
; } old_contents
;
389 union { rtx
*r
; int *i
; struct insn_link
**l
; } where
;
392 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
393 num_undo says how many are currently recorded.
395 other_insn is nonzero if we have modified some other insn in the process
396 of working on subst_insn. It must be verified too. */
402 rtx_insn
*other_insn
;
405 static struct undobuf undobuf
;
407 /* Number of times the pseudo being substituted for
408 was found and replaced. */
410 static int n_occurrences
;
412 static rtx
reg_nonzero_bits_for_combine (const_rtx
, machine_mode
, const_rtx
,
414 unsigned HOST_WIDE_INT
,
415 unsigned HOST_WIDE_INT
*);
416 static rtx
reg_num_sign_bit_copies_for_combine (const_rtx
, machine_mode
, const_rtx
,
418 unsigned int, unsigned int *);
419 static void do_SUBST (rtx
*, rtx
);
420 static void do_SUBST_INT (int *, int);
421 static void init_reg_last (void);
422 static void setup_incoming_promotions (rtx_insn
*);
423 static void set_nonzero_bits_and_sign_copies (rtx
, const_rtx
, void *);
424 static int cant_combine_insn_p (rtx_insn
*);
425 static int can_combine_p (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
426 rtx_insn
*, rtx_insn
*, rtx
*, rtx
*);
427 static int combinable_i3pat (rtx_insn
*, rtx
*, rtx
, rtx
, rtx
, int, int, rtx
*);
428 static int contains_muldiv (rtx
);
429 static rtx_insn
*try_combine (rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx_insn
*,
431 static void undo_all (void);
432 static void undo_commit (void);
433 static rtx
*find_split_point (rtx
*, rtx_insn
*, bool);
434 static rtx
subst (rtx
, rtx
, rtx
, int, int, int);
435 static rtx
combine_simplify_rtx (rtx
, machine_mode
, int, int);
436 static rtx
simplify_if_then_else (rtx
);
437 static rtx
simplify_set (rtx
);
438 static rtx
simplify_logical (rtx
);
439 static rtx
expand_compound_operation (rtx
);
440 static const_rtx
expand_field_assignment (const_rtx
);
441 static rtx
make_extraction (machine_mode
, rtx
, HOST_WIDE_INT
,
442 rtx
, unsigned HOST_WIDE_INT
, int, int, int);
443 static rtx
extract_left_shift (rtx
, int);
444 static int get_pos_from_mask (unsigned HOST_WIDE_INT
,
445 unsigned HOST_WIDE_INT
*);
446 static rtx
canon_reg_for_combine (rtx
, rtx
);
447 static rtx
force_to_mode (rtx
, machine_mode
,
448 unsigned HOST_WIDE_INT
, int);
449 static rtx
if_then_else_cond (rtx
, rtx
*, rtx
*);
450 static rtx
known_cond (rtx
, enum rtx_code
, rtx
, rtx
);
451 static int rtx_equal_for_field_assignment_p (rtx
, rtx
, bool = false);
452 static rtx
make_field_assignment (rtx
);
453 static rtx
apply_distributive_law (rtx
);
454 static rtx
distribute_and_simplify_rtx (rtx
, int);
455 static rtx
simplify_and_const_int_1 (machine_mode
, rtx
,
456 unsigned HOST_WIDE_INT
);
457 static rtx
simplify_and_const_int (rtx
, machine_mode
, rtx
,
458 unsigned HOST_WIDE_INT
);
459 static int merge_outer_ops (enum rtx_code
*, HOST_WIDE_INT
*, enum rtx_code
,
460 HOST_WIDE_INT
, machine_mode
, int *);
461 static rtx
simplify_shift_const_1 (enum rtx_code
, machine_mode
, rtx
, int);
462 static rtx
simplify_shift_const (rtx
, enum rtx_code
, machine_mode
, rtx
,
464 static int recog_for_combine (rtx
*, rtx_insn
*, rtx
*);
465 static rtx
gen_lowpart_for_combine (machine_mode
, rtx
);
466 static enum rtx_code
simplify_compare_const (enum rtx_code
, machine_mode
,
468 static enum rtx_code
simplify_comparison (enum rtx_code
, rtx
*, rtx
*);
469 static void update_table_tick (rtx
);
470 static void record_value_for_reg (rtx
, rtx_insn
*, rtx
);
471 static void check_promoted_subreg (rtx_insn
*, rtx
);
472 static void record_dead_and_set_regs_1 (rtx
, const_rtx
, void *);
473 static void record_dead_and_set_regs (rtx_insn
*);
474 static int get_last_value_validate (rtx
*, rtx_insn
*, int, int);
475 static rtx
get_last_value (const_rtx
);
476 static int use_crosses_set_p (const_rtx
, int);
477 static void reg_dead_at_p_1 (rtx
, const_rtx
, void *);
478 static int reg_dead_at_p (rtx
, rtx_insn
*);
479 static void move_deaths (rtx
, rtx
, int, rtx_insn
*, rtx
*);
480 static int reg_bitfield_target_p (rtx
, rtx
);
481 static void distribute_notes (rtx
, rtx_insn
*, rtx_insn
*, rtx_insn
*, rtx
, rtx
, rtx
);
482 static void distribute_links (struct insn_link
*);
483 static void mark_used_regs_combine (rtx
);
484 static void record_promoted_value (rtx_insn
*, rtx
);
485 static bool unmentioned_reg_p (rtx
, rtx
);
486 static void record_truncated_values (rtx
*, void *);
487 static bool reg_truncated_to_mode (machine_mode
, const_rtx
);
488 static rtx
gen_lowpart_or_truncate (machine_mode
, rtx
);
491 /* It is not safe to use ordinary gen_lowpart in combine.
492 See comments in gen_lowpart_for_combine. */
493 #undef RTL_HOOKS_GEN_LOWPART
494 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
496 /* Our implementation of gen_lowpart never emits a new pseudo. */
497 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
498 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
500 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
501 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
503 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
504 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
506 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
507 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
509 static const struct rtl_hooks combine_rtl_hooks
= RTL_HOOKS_INITIALIZER
;
512 /* Convenience wrapper for the canonicalize_comparison target hook.
513 Target hooks cannot use enum rtx_code. */
515 target_canonicalize_comparison (enum rtx_code
*code
, rtx
*op0
, rtx
*op1
,
516 bool op0_preserve_value
)
518 int code_int
= (int)*code
;
519 targetm
.canonicalize_comparison (&code_int
, op0
, op1
, op0_preserve_value
);
520 *code
= (enum rtx_code
)code_int
;
523 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
524 PATTERN can not be split. Otherwise, it returns an insn sequence.
525 This is a wrapper around split_insns which ensures that the
526 reg_stat vector is made larger if the splitter creates a new
530 combine_split_insns (rtx pattern
, rtx_insn
*insn
)
535 ret
= split_insns (pattern
, insn
);
536 nregs
= max_reg_num ();
537 if (nregs
> reg_stat
.length ())
538 reg_stat
.safe_grow_cleared (nregs
);
542 /* This is used by find_single_use to locate an rtx in LOC that
543 contains exactly one use of DEST, which is typically either a REG
544 or CC0. It returns a pointer to the innermost rtx expression
545 containing DEST. Appearances of DEST that are being used to
546 totally replace it are not counted. */
549 find_single_use_1 (rtx dest
, rtx
*loc
)
552 enum rtx_code code
= GET_CODE (x
);
568 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
569 of a REG that occupies all of the REG, the insn uses DEST if
570 it is mentioned in the destination or the source. Otherwise, we
571 need just check the source. */
572 if (GET_CODE (SET_DEST (x
)) != CC0
573 && GET_CODE (SET_DEST (x
)) != PC
574 && !REG_P (SET_DEST (x
))
575 && ! (GET_CODE (SET_DEST (x
)) == SUBREG
576 && REG_P (SUBREG_REG (SET_DEST (x
)))
577 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
578 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
579 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
580 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))))
583 return find_single_use_1 (dest
, &SET_SRC (x
));
587 return find_single_use_1 (dest
, &XEXP (x
, 0));
593 /* If it wasn't one of the common cases above, check each expression and
594 vector of this code. Look for a unique usage of DEST. */
596 fmt
= GET_RTX_FORMAT (code
);
597 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
601 if (dest
== XEXP (x
, i
)
602 || (REG_P (dest
) && REG_P (XEXP (x
, i
))
603 && REGNO (dest
) == REGNO (XEXP (x
, i
))))
606 this_result
= find_single_use_1 (dest
, &XEXP (x
, i
));
609 result
= this_result
;
610 else if (this_result
)
611 /* Duplicate usage. */
614 else if (fmt
[i
] == 'E')
618 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
620 if (XVECEXP (x
, i
, j
) == dest
622 && REG_P (XVECEXP (x
, i
, j
))
623 && REGNO (XVECEXP (x
, i
, j
)) == REGNO (dest
)))
626 this_result
= find_single_use_1 (dest
, &XVECEXP (x
, i
, j
));
629 result
= this_result
;
630 else if (this_result
)
640 /* See if DEST, produced in INSN, is used only a single time in the
641 sequel. If so, return a pointer to the innermost rtx expression in which
644 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
646 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
647 care about REG_DEAD notes or LOG_LINKS.
649 Otherwise, we find the single use by finding an insn that has a
650 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
651 only referenced once in that insn, we know that it must be the first
652 and last insn referencing DEST. */
655 find_single_use (rtx dest
, rtx_insn
*insn
, rtx_insn
**ploc
)
660 struct insn_link
*link
;
664 next
= NEXT_INSN (insn
);
666 || (!NONJUMP_INSN_P (next
) && !JUMP_P (next
)))
669 result
= find_single_use_1 (dest
, &PATTERN (next
));
678 bb
= BLOCK_FOR_INSN (insn
);
679 for (next
= NEXT_INSN (insn
);
680 next
&& BLOCK_FOR_INSN (next
) == bb
;
681 next
= NEXT_INSN (next
))
682 if (INSN_P (next
) && dead_or_set_p (next
, dest
))
684 FOR_EACH_LOG_LINK (link
, next
)
685 if (link
->insn
== insn
&& link
->regno
== REGNO (dest
))
690 result
= find_single_use_1 (dest
, &PATTERN (next
));
700 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
701 insn. The substitution can be undone by undo_all. If INTO is already
702 set to NEWVAL, do not record this change. Because computing NEWVAL might
703 also call SUBST, we have to compute it before we put anything into
707 do_SUBST (rtx
*into
, rtx newval
)
712 if (oldval
== newval
)
715 /* We'd like to catch as many invalid transformations here as
716 possible. Unfortunately, there are way too many mode changes
717 that are perfectly valid, so we'd waste too much effort for
718 little gain doing the checks here. Focus on catching invalid
719 transformations involving integer constants. */
720 if (GET_MODE_CLASS (GET_MODE (oldval
)) == MODE_INT
721 && CONST_INT_P (newval
))
723 /* Sanity check that we're replacing oldval with a CONST_INT
724 that is a valid sign-extension for the original mode. */
725 gcc_assert (INTVAL (newval
)
726 == trunc_int_for_mode (INTVAL (newval
), GET_MODE (oldval
)));
728 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
729 CONST_INT is not valid, because after the replacement, the
730 original mode would be gone. Unfortunately, we can't tell
731 when do_SUBST is called to replace the operand thereof, so we
732 perform this test on oldval instead, checking whether an
733 invalid replacement took place before we got here. */
734 gcc_assert (!(GET_CODE (oldval
) == SUBREG
735 && CONST_INT_P (SUBREG_REG (oldval
))));
736 gcc_assert (!(GET_CODE (oldval
) == ZERO_EXTEND
737 && CONST_INT_P (XEXP (oldval
, 0))));
741 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
743 buf
= XNEW (struct undo
);
745 buf
->kind
= UNDO_RTX
;
747 buf
->old_contents
.r
= oldval
;
750 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
753 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
755 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
756 for the value of a HOST_WIDE_INT value (including CONST_INT) is
760 do_SUBST_INT (int *into
, int newval
)
765 if (oldval
== newval
)
769 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
771 buf
= XNEW (struct undo
);
773 buf
->kind
= UNDO_INT
;
775 buf
->old_contents
.i
= oldval
;
778 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
781 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
783 /* Similar to SUBST, but just substitute the mode. This is used when
784 changing the mode of a pseudo-register, so that any other
785 references to the entry in the regno_reg_rtx array will change as
789 do_SUBST_MODE (rtx
*into
, machine_mode newval
)
792 machine_mode oldval
= GET_MODE (*into
);
794 if (oldval
== newval
)
798 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
800 buf
= XNEW (struct undo
);
802 buf
->kind
= UNDO_MODE
;
804 buf
->old_contents
.m
= oldval
;
805 adjust_reg_mode (*into
, newval
);
807 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
810 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
812 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
815 do_SUBST_LINK (struct insn_link
**into
, struct insn_link
*newval
)
818 struct insn_link
* oldval
= *into
;
820 if (oldval
== newval
)
824 buf
= undobuf
.frees
, undobuf
.frees
= buf
->next
;
826 buf
= XNEW (struct undo
);
828 buf
->kind
= UNDO_LINKS
;
830 buf
->old_contents
.l
= oldval
;
833 buf
->next
= undobuf
.undos
, undobuf
.undos
= buf
;
836 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
838 /* Subroutine of try_combine. Determine whether the replacement patterns
839 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
840 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
841 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
842 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
843 of all the instructions can be estimated and the replacements are more
844 expensive than the original sequence. */
847 combine_validate_cost (rtx_insn
*i0
, rtx_insn
*i1
, rtx_insn
*i2
, rtx_insn
*i3
,
848 rtx newpat
, rtx newi2pat
, rtx newotherpat
)
850 int i0_cost
, i1_cost
, i2_cost
, i3_cost
;
851 int new_i2_cost
, new_i3_cost
;
852 int old_cost
, new_cost
;
854 /* Lookup the original insn_rtx_costs. */
855 i2_cost
= INSN_COST (i2
);
856 i3_cost
= INSN_COST (i3
);
860 i1_cost
= INSN_COST (i1
);
863 i0_cost
= INSN_COST (i0
);
864 old_cost
= (i0_cost
> 0 && i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
865 ? i0_cost
+ i1_cost
+ i2_cost
+ i3_cost
: 0);
869 old_cost
= (i1_cost
> 0 && i2_cost
> 0 && i3_cost
> 0
870 ? i1_cost
+ i2_cost
+ i3_cost
: 0);
876 old_cost
= (i2_cost
> 0 && i3_cost
> 0) ? i2_cost
+ i3_cost
: 0;
877 i1_cost
= i0_cost
= 0;
880 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
882 if (old_cost
&& i1
&& INSN_UID (i1
) == INSN_UID (i2
))
886 /* Calculate the replacement insn_rtx_costs. */
887 new_i3_cost
= insn_rtx_cost (newpat
, optimize_this_for_speed_p
);
890 new_i2_cost
= insn_rtx_cost (newi2pat
, optimize_this_for_speed_p
);
891 new_cost
= (new_i2_cost
> 0 && new_i3_cost
> 0)
892 ? new_i2_cost
+ new_i3_cost
: 0;
896 new_cost
= new_i3_cost
;
900 if (undobuf
.other_insn
)
902 int old_other_cost
, new_other_cost
;
904 old_other_cost
= INSN_COST (undobuf
.other_insn
);
905 new_other_cost
= insn_rtx_cost (newotherpat
, optimize_this_for_speed_p
);
906 if (old_other_cost
> 0 && new_other_cost
> 0)
908 old_cost
+= old_other_cost
;
909 new_cost
+= new_other_cost
;
915 /* Disallow this combination if both new_cost and old_cost are greater than
916 zero, and new_cost is greater than old cost. */
917 int reject
= old_cost
> 0 && new_cost
> old_cost
;
921 fprintf (dump_file
, "%s combination of insns ",
922 reject
? "rejecting" : "allowing");
924 fprintf (dump_file
, "%d, ", INSN_UID (i0
));
925 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
926 fprintf (dump_file
, "%d, ", INSN_UID (i1
));
927 fprintf (dump_file
, "%d and %d\n", INSN_UID (i2
), INSN_UID (i3
));
929 fprintf (dump_file
, "original costs ");
931 fprintf (dump_file
, "%d + ", i0_cost
);
932 if (i1
&& INSN_UID (i1
) != INSN_UID (i2
))
933 fprintf (dump_file
, "%d + ", i1_cost
);
934 fprintf (dump_file
, "%d + %d = %d\n", i2_cost
, i3_cost
, old_cost
);
937 fprintf (dump_file
, "replacement costs %d + %d = %d\n",
938 new_i2_cost
, new_i3_cost
, new_cost
);
940 fprintf (dump_file
, "replacement cost %d\n", new_cost
);
946 /* Update the uid_insn_cost array with the replacement costs. */
947 INSN_COST (i2
) = new_i2_cost
;
948 INSN_COST (i3
) = new_i3_cost
;
960 /* Delete any insns that copy a register to itself. */
963 delete_noop_moves (void)
965 rtx_insn
*insn
, *next
;
968 FOR_EACH_BB_FN (bb
, cfun
)
970 for (insn
= BB_HEAD (bb
); insn
!= NEXT_INSN (BB_END (bb
)); insn
= next
)
972 next
= NEXT_INSN (insn
);
973 if (INSN_P (insn
) && noop_move_p (insn
))
976 fprintf (dump_file
, "deleting noop move %d\n", INSN_UID (insn
));
978 delete_insn_and_edges (insn
);
985 /* Return false if we do not want to (or cannot) combine DEF. */
987 can_combine_def_p (df_ref def
)
989 /* Do not consider if it is pre/post modification in MEM. */
990 if (DF_REF_FLAGS (def
) & DF_REF_PRE_POST_MODIFY
)
993 unsigned int regno
= DF_REF_REGNO (def
);
995 /* Do not combine frame pointer adjustments. */
996 if ((regno
== FRAME_POINTER_REGNUM
997 && (!reload_completed
|| frame_pointer_needed
))
998 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
999 && regno
== HARD_FRAME_POINTER_REGNUM
1000 && (!reload_completed
|| frame_pointer_needed
))
1001 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
1002 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
]))
1008 /* Return false if we do not want to (or cannot) combine USE. */
1010 can_combine_use_p (df_ref use
)
1012 /* Do not consider the usage of the stack pointer by function call. */
1013 if (DF_REF_FLAGS (use
) & DF_REF_CALL_STACK_USAGE
)
1019 /* Fill in log links field for all insns. */
1022 create_log_links (void)
1025 rtx_insn
**next_use
;
1029 next_use
= XCNEWVEC (rtx_insn
*, max_reg_num ());
1031 /* Pass through each block from the end, recording the uses of each
1032 register and establishing log links when def is encountered.
1033 Note that we do not clear next_use array in order to save time,
1034 so we have to test whether the use is in the same basic block as def.
1036 There are a few cases below when we do not consider the definition or
1037 usage -- these are taken from original flow.c did. Don't ask me why it is
1038 done this way; I don't know and if it works, I don't want to know. */
1040 FOR_EACH_BB_FN (bb
, cfun
)
1042 FOR_BB_INSNS_REVERSE (bb
, insn
)
1044 if (!NONDEBUG_INSN_P (insn
))
1047 /* Log links are created only once. */
1048 gcc_assert (!LOG_LINKS (insn
));
1050 FOR_EACH_INSN_DEF (def
, insn
)
1052 unsigned int regno
= DF_REF_REGNO (def
);
1055 if (!next_use
[regno
])
1058 if (!can_combine_def_p (def
))
1061 use_insn
= next_use
[regno
];
1062 next_use
[regno
] = NULL
;
1064 if (BLOCK_FOR_INSN (use_insn
) != bb
)
1069 We don't build a LOG_LINK for hard registers contained
1070 in ASM_OPERANDs. If these registers get replaced,
1071 we might wind up changing the semantics of the insn,
1072 even if reload can make what appear to be valid
1073 assignments later. */
1074 if (regno
< FIRST_PSEUDO_REGISTER
1075 && asm_noperands (PATTERN (use_insn
)) >= 0)
1078 /* Don't add duplicate links between instructions. */
1079 struct insn_link
*links
;
1080 FOR_EACH_LOG_LINK (links
, use_insn
)
1081 if (insn
== links
->insn
&& regno
== links
->regno
)
1085 LOG_LINKS (use_insn
)
1086 = alloc_insn_link (insn
, regno
, LOG_LINKS (use_insn
));
1089 FOR_EACH_INSN_USE (use
, insn
)
1090 if (can_combine_use_p (use
))
1091 next_use
[DF_REF_REGNO (use
)] = insn
;
1098 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1099 true if we found a LOG_LINK that proves that A feeds B. This only works
1100 if there are no instructions between A and B which could have a link
1101 depending on A, since in that case we would not record a link for B.
1102 We also check the implicit dependency created by a cc0 setter/user
1106 insn_a_feeds_b (rtx_insn
*a
, rtx_insn
*b
)
1108 struct insn_link
*links
;
1109 FOR_EACH_LOG_LINK (links
, b
)
1110 if (links
->insn
== a
)
1112 if (HAVE_cc0
&& sets_cc0_p (a
))
1117 /* Main entry point for combiner. F is the first insn of the function.
1118 NREGS is the first unused pseudo-reg number.
1120 Return nonzero if the combiner has turned an indirect jump
1121 instruction into a direct jump. */
1123 combine_instructions (rtx_insn
*f
, unsigned int nregs
)
1125 rtx_insn
*insn
, *next
;
1127 struct insn_link
*links
, *nextlinks
;
1129 basic_block last_bb
;
1131 int new_direct_jump_p
= 0;
1133 for (first
= f
; first
&& !INSN_P (first
); )
1134 first
= NEXT_INSN (first
);
1138 combine_attempts
= 0;
1141 combine_successes
= 0;
1143 rtl_hooks
= combine_rtl_hooks
;
1145 reg_stat
.safe_grow_cleared (nregs
);
1147 init_recog_no_volatile ();
1149 /* Allocate array for insn info. */
1150 max_uid_known
= get_max_uid ();
1151 uid_log_links
= XCNEWVEC (struct insn_link
*, max_uid_known
+ 1);
1152 uid_insn_cost
= XCNEWVEC (int, max_uid_known
+ 1);
1153 gcc_obstack_init (&insn_link_obstack
);
1155 nonzero_bits_mode
= mode_for_size (HOST_BITS_PER_WIDE_INT
, MODE_INT
, 0);
1157 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1158 problems when, for example, we have j <<= 1 in a loop. */
1160 nonzero_sign_valid
= 0;
1161 label_tick
= label_tick_ebb_start
= 1;
1163 /* Scan all SETs and see if we can deduce anything about what
1164 bits are known to be zero for some registers and how many copies
1165 of the sign bit are known to exist for those registers.
1167 Also set any known values so that we can use it while searching
1168 for what bits are known to be set. */
1170 setup_incoming_promotions (first
);
1171 /* Allow the entry block and the first block to fall into the same EBB.
1172 Conceptually the incoming promotions are assigned to the entry block. */
1173 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1175 create_log_links ();
1176 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1178 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1183 if (!single_pred_p (this_basic_block
)
1184 || single_pred (this_basic_block
) != last_bb
)
1185 label_tick_ebb_start
= label_tick
;
1186 last_bb
= this_basic_block
;
1188 FOR_BB_INSNS (this_basic_block
, insn
)
1189 if (INSN_P (insn
) && BLOCK_FOR_INSN (insn
))
1193 subst_low_luid
= DF_INSN_LUID (insn
);
1196 note_stores (PATTERN (insn
), set_nonzero_bits_and_sign_copies
,
1198 record_dead_and_set_regs (insn
);
1201 for (links
= REG_NOTES (insn
); links
; links
= XEXP (links
, 1))
1202 if (REG_NOTE_KIND (links
) == REG_INC
)
1203 set_nonzero_bits_and_sign_copies (XEXP (links
, 0), NULL_RTX
,
1206 /* Record the current insn_rtx_cost of this instruction. */
1207 if (NONJUMP_INSN_P (insn
))
1208 INSN_COST (insn
) = insn_rtx_cost (PATTERN (insn
),
1209 optimize_this_for_speed_p
);
1211 fprintf (dump_file
, "insn_cost %d: %d\n",
1212 INSN_UID (insn
), INSN_COST (insn
));
1216 nonzero_sign_valid
= 1;
1218 /* Now scan all the insns in forward order. */
1219 label_tick
= label_tick_ebb_start
= 1;
1221 setup_incoming_promotions (first
);
1222 last_bb
= ENTRY_BLOCK_PTR_FOR_FN (cfun
);
1223 int max_combine
= PARAM_VALUE (PARAM_MAX_COMBINE_INSNS
);
1225 FOR_EACH_BB_FN (this_basic_block
, cfun
)
1227 rtx_insn
*last_combined_insn
= NULL
;
1228 optimize_this_for_speed_p
= optimize_bb_for_speed_p (this_basic_block
);
1233 if (!single_pred_p (this_basic_block
)
1234 || single_pred (this_basic_block
) != last_bb
)
1235 label_tick_ebb_start
= label_tick
;
1236 last_bb
= this_basic_block
;
1238 rtl_profile_for_bb (this_basic_block
);
1239 for (insn
= BB_HEAD (this_basic_block
);
1240 insn
!= NEXT_INSN (BB_END (this_basic_block
));
1241 insn
= next
? next
: NEXT_INSN (insn
))
1244 if (!NONDEBUG_INSN_P (insn
))
1247 while (last_combined_insn
1248 && last_combined_insn
->deleted ())
1249 last_combined_insn
= PREV_INSN (last_combined_insn
);
1250 if (last_combined_insn
== NULL_RTX
1251 || BARRIER_P (last_combined_insn
)
1252 || BLOCK_FOR_INSN (last_combined_insn
) != this_basic_block
1253 || DF_INSN_LUID (last_combined_insn
) <= DF_INSN_LUID (insn
))
1254 last_combined_insn
= insn
;
1256 /* See if we know about function return values before this
1257 insn based upon SUBREG flags. */
1258 check_promoted_subreg (insn
, PATTERN (insn
));
1260 /* See if we can find hardregs and subreg of pseudos in
1261 narrower modes. This could help turning TRUNCATEs
1263 note_uses (&PATTERN (insn
), record_truncated_values
, NULL
);
1265 /* Try this insn with each insn it links back to. */
1267 FOR_EACH_LOG_LINK (links
, insn
)
1268 if ((next
= try_combine (insn
, links
->insn
, NULL
,
1269 NULL
, &new_direct_jump_p
,
1270 last_combined_insn
)) != 0)
1272 statistics_counter_event (cfun
, "two-insn combine", 1);
1276 /* Try each sequence of three linked insns ending with this one. */
1278 if (max_combine
>= 3)
1279 FOR_EACH_LOG_LINK (links
, insn
)
1281 rtx_insn
*link
= links
->insn
;
1283 /* If the linked insn has been replaced by a note, then there
1284 is no point in pursuing this chain any further. */
1288 FOR_EACH_LOG_LINK (nextlinks
, link
)
1289 if ((next
= try_combine (insn
, link
, nextlinks
->insn
,
1290 NULL
, &new_direct_jump_p
,
1291 last_combined_insn
)) != 0)
1293 statistics_counter_event (cfun
, "three-insn combine", 1);
1298 /* Try to combine a jump insn that uses CC0
1299 with a preceding insn that sets CC0, and maybe with its
1300 logical predecessor as well.
1301 This is how we make decrement-and-branch insns.
1302 We need this special code because data flow connections
1303 via CC0 do not get entered in LOG_LINKS. */
1307 && (prev
= prev_nonnote_insn (insn
)) != 0
1308 && NONJUMP_INSN_P (prev
)
1309 && sets_cc0_p (PATTERN (prev
)))
1311 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1313 last_combined_insn
)) != 0)
1316 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1317 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1318 NULL
, &new_direct_jump_p
,
1319 last_combined_insn
)) != 0)
1323 /* Do the same for an insn that explicitly references CC0. */
1324 if (HAVE_cc0
&& NONJUMP_INSN_P (insn
)
1325 && (prev
= prev_nonnote_insn (insn
)) != 0
1326 && NONJUMP_INSN_P (prev
)
1327 && sets_cc0_p (PATTERN (prev
))
1328 && GET_CODE (PATTERN (insn
)) == SET
1329 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (insn
))))
1331 if ((next
= try_combine (insn
, prev
, NULL
, NULL
,
1333 last_combined_insn
)) != 0)
1336 FOR_EACH_LOG_LINK (nextlinks
, prev
)
1337 if ((next
= try_combine (insn
, prev
, nextlinks
->insn
,
1338 NULL
, &new_direct_jump_p
,
1339 last_combined_insn
)) != 0)
1343 /* Finally, see if any of the insns that this insn links to
1344 explicitly references CC0. If so, try this insn, that insn,
1345 and its predecessor if it sets CC0. */
1348 FOR_EACH_LOG_LINK (links
, insn
)
1349 if (NONJUMP_INSN_P (links
->insn
)
1350 && GET_CODE (PATTERN (links
->insn
)) == SET
1351 && reg_mentioned_p (cc0_rtx
, SET_SRC (PATTERN (links
->insn
)))
1352 && (prev
= prev_nonnote_insn (links
->insn
)) != 0
1353 && NONJUMP_INSN_P (prev
)
1354 && sets_cc0_p (PATTERN (prev
))
1355 && (next
= try_combine (insn
, links
->insn
,
1356 prev
, NULL
, &new_direct_jump_p
,
1357 last_combined_insn
)) != 0)
1361 /* Try combining an insn with two different insns whose results it
1363 if (max_combine
>= 3)
1364 FOR_EACH_LOG_LINK (links
, insn
)
1365 for (nextlinks
= links
->next
; nextlinks
;
1366 nextlinks
= nextlinks
->next
)
1367 if ((next
= try_combine (insn
, links
->insn
,
1368 nextlinks
->insn
, NULL
,
1370 last_combined_insn
)) != 0)
1373 statistics_counter_event (cfun
, "three-insn combine", 1);
1377 /* Try four-instruction combinations. */
1378 if (max_combine
>= 4)
1379 FOR_EACH_LOG_LINK (links
, insn
)
1381 struct insn_link
*next1
;
1382 rtx_insn
*link
= links
->insn
;
1384 /* If the linked insn has been replaced by a note, then there
1385 is no point in pursuing this chain any further. */
1389 FOR_EACH_LOG_LINK (next1
, link
)
1391 rtx_insn
*link1
= next1
->insn
;
1394 /* I0 -> I1 -> I2 -> I3. */
1395 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1396 if ((next
= try_combine (insn
, link
, link1
,
1399 last_combined_insn
)) != 0)
1401 statistics_counter_event (cfun
, "four-insn combine", 1);
1404 /* I0, I1 -> I2, I2 -> I3. */
1405 for (nextlinks
= next1
->next
; nextlinks
;
1406 nextlinks
= nextlinks
->next
)
1407 if ((next
= try_combine (insn
, link
, link1
,
1410 last_combined_insn
)) != 0)
1412 statistics_counter_event (cfun
, "four-insn combine", 1);
1417 for (next1
= links
->next
; next1
; next1
= next1
->next
)
1419 rtx_insn
*link1
= next1
->insn
;
1422 /* I0 -> I2; I1, I2 -> I3. */
1423 FOR_EACH_LOG_LINK (nextlinks
, link
)
1424 if ((next
= try_combine (insn
, link
, link1
,
1427 last_combined_insn
)) != 0)
1429 statistics_counter_event (cfun
, "four-insn combine", 1);
1432 /* I0 -> I1; I1, I2 -> I3. */
1433 FOR_EACH_LOG_LINK (nextlinks
, link1
)
1434 if ((next
= try_combine (insn
, link
, link1
,
1437 last_combined_insn
)) != 0)
1439 statistics_counter_event (cfun
, "four-insn combine", 1);
1445 /* Try this insn with each REG_EQUAL note it links back to. */
1446 FOR_EACH_LOG_LINK (links
, insn
)
1449 rtx_insn
*temp
= links
->insn
;
1450 if ((set
= single_set (temp
)) != 0
1451 && (note
= find_reg_equal_equiv_note (temp
)) != 0
1452 && (note
= XEXP (note
, 0), GET_CODE (note
)) != EXPR_LIST
1453 /* Avoid using a register that may already been marked
1454 dead by an earlier instruction. */
1455 && ! unmentioned_reg_p (note
, SET_SRC (set
))
1456 && (GET_MODE (note
) == VOIDmode
1457 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set
)))
1458 : (GET_MODE (SET_DEST (set
)) == GET_MODE (note
)
1459 && (GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
1460 || (GET_MODE (XEXP (SET_DEST (set
), 0))
1461 == GET_MODE (note
))))))
1463 /* Temporarily replace the set's source with the
1464 contents of the REG_EQUAL note. The insn will
1465 be deleted or recognized by try_combine. */
1466 rtx orig_src
= SET_SRC (set
);
1467 rtx orig_dest
= SET_DEST (set
);
1468 if (GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
)
1469 SET_DEST (set
) = XEXP (SET_DEST (set
), 0);
1470 SET_SRC (set
) = note
;
1472 i2mod_old_rhs
= copy_rtx (orig_src
);
1473 i2mod_new_rhs
= copy_rtx (note
);
1474 next
= try_combine (insn
, i2mod
, NULL
, NULL
,
1476 last_combined_insn
);
1480 statistics_counter_event (cfun
, "insn-with-note combine", 1);
1483 SET_SRC (set
) = orig_src
;
1484 SET_DEST (set
) = orig_dest
;
1489 record_dead_and_set_regs (insn
);
1496 default_rtl_profile ();
1498 new_direct_jump_p
|= purge_all_dead_edges ();
1499 delete_noop_moves ();
1502 obstack_free (&insn_link_obstack
, NULL
);
1503 free (uid_log_links
);
1504 free (uid_insn_cost
);
1505 reg_stat
.release ();
1508 struct undo
*undo
, *next
;
1509 for (undo
= undobuf
.frees
; undo
; undo
= next
)
1517 total_attempts
+= combine_attempts
;
1518 total_merges
+= combine_merges
;
1519 total_extras
+= combine_extras
;
1520 total_successes
+= combine_successes
;
1522 nonzero_sign_valid
= 0;
1523 rtl_hooks
= general_rtl_hooks
;
1525 /* Make recognizer allow volatile MEMs again. */
1528 return new_direct_jump_p
;
1531 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1534 init_reg_last (void)
1539 FOR_EACH_VEC_ELT (reg_stat
, i
, p
)
1540 memset (p
, 0, offsetof (reg_stat_type
, sign_bit_copies
));
1543 /* Set up any promoted values for incoming argument registers. */
1546 setup_incoming_promotions (rtx_insn
*first
)
1549 bool strictly_local
= false;
1551 for (arg
= DECL_ARGUMENTS (current_function_decl
); arg
;
1552 arg
= DECL_CHAIN (arg
))
1554 rtx x
, reg
= DECL_INCOMING_RTL (arg
);
1556 machine_mode mode1
, mode2
, mode3
, mode4
;
1558 /* Only continue if the incoming argument is in a register. */
1562 /* Determine, if possible, whether all call sites of the current
1563 function lie within the current compilation unit. (This does
1564 take into account the exporting of a function via taking its
1565 address, and so forth.) */
1566 strictly_local
= cgraph_node::local_info (current_function_decl
)->local
;
1568 /* The mode and signedness of the argument before any promotions happen
1569 (equal to the mode of the pseudo holding it at that stage). */
1570 mode1
= TYPE_MODE (TREE_TYPE (arg
));
1571 uns1
= TYPE_UNSIGNED (TREE_TYPE (arg
));
1573 /* The mode and signedness of the argument after any source language and
1574 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1575 mode2
= TYPE_MODE (DECL_ARG_TYPE (arg
));
1576 uns3
= TYPE_UNSIGNED (DECL_ARG_TYPE (arg
));
1578 /* The mode and signedness of the argument as it is actually passed,
1579 see assign_parm_setup_reg in function.c. */
1580 mode3
= promote_function_mode (TREE_TYPE (arg
), mode1
, &uns3
,
1581 TREE_TYPE (cfun
->decl
), 0);
1583 /* The mode of the register in which the argument is being passed. */
1584 mode4
= GET_MODE (reg
);
1586 /* Eliminate sign extensions in the callee when:
1587 (a) A mode promotion has occurred; */
1590 /* (b) The mode of the register is the same as the mode of
1591 the argument as it is passed; */
1594 /* (c) There's no language level extension; */
1597 /* (c.1) All callers are from the current compilation unit. If that's
1598 the case we don't have to rely on an ABI, we only have to know
1599 what we're generating right now, and we know that we will do the
1600 mode1 to mode2 promotion with the given sign. */
1601 else if (!strictly_local
)
1603 /* (c.2) The combination of the two promotions is useful. This is
1604 true when the signs match, or if the first promotion is unsigned.
1605 In the later case, (sign_extend (zero_extend x)) is the same as
1606 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1612 /* Record that the value was promoted from mode1 to mode3,
1613 so that any sign extension at the head of the current
1614 function may be eliminated. */
1615 x
= gen_rtx_CLOBBER (mode1
, const0_rtx
);
1616 x
= gen_rtx_fmt_e ((uns3
? ZERO_EXTEND
: SIGN_EXTEND
), mode3
, x
);
1617 record_value_for_reg (reg
, first
, x
);
1621 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1622 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1623 because some machines (maybe most) will actually do the sign-extension and
1624 this is the conservative approach.
1626 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1630 sign_extend_short_imm (rtx src
, machine_mode mode
, unsigned int prec
)
1632 if (GET_MODE_PRECISION (mode
) < prec
1633 && CONST_INT_P (src
)
1635 && val_signbit_known_set_p (mode
, INTVAL (src
)))
1636 src
= GEN_INT (INTVAL (src
) | ~GET_MODE_MASK (mode
));
1641 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1645 update_rsp_from_reg_equal (reg_stat_type
*rsp
, rtx_insn
*insn
, const_rtx set
,
1648 rtx reg_equal_note
= insn
? find_reg_equal_equiv_note (insn
) : NULL_RTX
;
1649 unsigned HOST_WIDE_INT bits
= 0;
1650 rtx reg_equal
= NULL
, src
= SET_SRC (set
);
1651 unsigned int num
= 0;
1654 reg_equal
= XEXP (reg_equal_note
, 0);
1656 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
1658 src
= sign_extend_short_imm (src
, GET_MODE (x
), BITS_PER_WORD
);
1660 reg_equal
= sign_extend_short_imm (reg_equal
, GET_MODE (x
), BITS_PER_WORD
);
1663 /* Don't call nonzero_bits if it cannot change anything. */
1664 if (rsp
->nonzero_bits
!= HOST_WIDE_INT_M1U
)
1666 bits
= nonzero_bits (src
, nonzero_bits_mode
);
1667 if (reg_equal
&& bits
)
1668 bits
&= nonzero_bits (reg_equal
, nonzero_bits_mode
);
1669 rsp
->nonzero_bits
|= bits
;
1672 /* Don't call num_sign_bit_copies if it cannot change anything. */
1673 if (rsp
->sign_bit_copies
!= 1)
1675 num
= num_sign_bit_copies (SET_SRC (set
), GET_MODE (x
));
1676 if (reg_equal
&& num
!= GET_MODE_PRECISION (GET_MODE (x
)))
1678 unsigned int numeq
= num_sign_bit_copies (reg_equal
, GET_MODE (x
));
1679 if (num
== 0 || numeq
> num
)
1682 if (rsp
->sign_bit_copies
== 0 || num
< rsp
->sign_bit_copies
)
1683 rsp
->sign_bit_copies
= num
;
1687 /* Called via note_stores. If X is a pseudo that is narrower than
1688 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1690 If we are setting only a portion of X and we can't figure out what
1691 portion, assume all bits will be used since we don't know what will
1694 Similarly, set how many bits of X are known to be copies of the sign bit
1695 at all locations in the function. This is the smallest number implied
1699 set_nonzero_bits_and_sign_copies (rtx x
, const_rtx set
, void *data
)
1701 rtx_insn
*insn
= (rtx_insn
*) data
;
1704 && REGNO (x
) >= FIRST_PSEUDO_REGISTER
1705 /* If this register is undefined at the start of the file, we can't
1706 say what its contents were. */
1707 && ! REGNO_REG_SET_P
1708 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), REGNO (x
))
1709 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
1711 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
1713 if (set
== 0 || GET_CODE (set
) == CLOBBER
)
1715 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1716 rsp
->sign_bit_copies
= 1;
1720 /* If this register is being initialized using itself, and the
1721 register is uninitialized in this basic block, and there are
1722 no LOG_LINKS which set the register, then part of the
1723 register is uninitialized. In that case we can't assume
1724 anything about the number of nonzero bits.
1726 ??? We could do better if we checked this in
1727 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1728 could avoid making assumptions about the insn which initially
1729 sets the register, while still using the information in other
1730 insns. We would have to be careful to check every insn
1731 involved in the combination. */
1734 && reg_referenced_p (x
, PATTERN (insn
))
1735 && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn
)),
1738 struct insn_link
*link
;
1740 FOR_EACH_LOG_LINK (link
, insn
)
1741 if (dead_or_set_p (link
->insn
, x
))
1745 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1746 rsp
->sign_bit_copies
= 1;
1751 /* If this is a complex assignment, see if we can convert it into a
1752 simple assignment. */
1753 set
= expand_field_assignment (set
);
1755 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1756 set what we know about X. */
1758 if (SET_DEST (set
) == x
1759 || (paradoxical_subreg_p (SET_DEST (set
))
1760 && SUBREG_REG (SET_DEST (set
)) == x
))
1761 update_rsp_from_reg_equal (rsp
, insn
, set
, x
);
1764 rsp
->nonzero_bits
= GET_MODE_MASK (GET_MODE (x
));
1765 rsp
->sign_bit_copies
= 1;
1770 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1771 optionally insns that were previously combined into I3 or that will be
1772 combined into the merger of INSN and I3. The order is PRED, PRED2,
1773 INSN, SUCC, SUCC2, I3.
1775 Return 0 if the combination is not allowed for any reason.
1777 If the combination is allowed, *PDEST will be set to the single
1778 destination of INSN and *PSRC to the single source, and this function
1782 can_combine_p (rtx_insn
*insn
, rtx_insn
*i3
, rtx_insn
*pred ATTRIBUTE_UNUSED
,
1783 rtx_insn
*pred2 ATTRIBUTE_UNUSED
, rtx_insn
*succ
, rtx_insn
*succ2
,
1784 rtx
*pdest
, rtx
*psrc
)
1791 bool all_adjacent
= true;
1792 int (*is_volatile_p
) (const_rtx
);
1798 if (next_active_insn (succ2
) != i3
)
1799 all_adjacent
= false;
1800 if (next_active_insn (succ
) != succ2
)
1801 all_adjacent
= false;
1803 else if (next_active_insn (succ
) != i3
)
1804 all_adjacent
= false;
1805 if (next_active_insn (insn
) != succ
)
1806 all_adjacent
= false;
1808 else if (next_active_insn (insn
) != i3
)
1809 all_adjacent
= false;
1811 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1812 or a PARALLEL consisting of such a SET and CLOBBERs.
1814 If INSN has CLOBBER parallel parts, ignore them for our processing.
1815 By definition, these happen during the execution of the insn. When it
1816 is merged with another insn, all bets are off. If they are, in fact,
1817 needed and aren't also supplied in I3, they may be added by
1818 recog_for_combine. Otherwise, it won't match.
1820 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1823 Get the source and destination of INSN. If more than one, can't
1826 if (GET_CODE (PATTERN (insn
)) == SET
)
1827 set
= PATTERN (insn
);
1828 else if (GET_CODE (PATTERN (insn
)) == PARALLEL
1829 && GET_CODE (XVECEXP (PATTERN (insn
), 0, 0)) == SET
)
1831 for (i
= 0; i
< XVECLEN (PATTERN (insn
), 0); i
++)
1833 rtx elt
= XVECEXP (PATTERN (insn
), 0, i
);
1835 switch (GET_CODE (elt
))
1837 /* This is important to combine floating point insns
1838 for the SH4 port. */
1840 /* Combining an isolated USE doesn't make sense.
1841 We depend here on combinable_i3pat to reject them. */
1842 /* The code below this loop only verifies that the inputs of
1843 the SET in INSN do not change. We call reg_set_between_p
1844 to verify that the REG in the USE does not change between
1846 If the USE in INSN was for a pseudo register, the matching
1847 insn pattern will likely match any register; combining this
1848 with any other USE would only be safe if we knew that the
1849 used registers have identical values, or if there was
1850 something to tell them apart, e.g. different modes. For
1851 now, we forgo such complicated tests and simply disallow
1852 combining of USES of pseudo registers with any other USE. */
1853 if (REG_P (XEXP (elt
, 0))
1854 && GET_CODE (PATTERN (i3
)) == PARALLEL
)
1856 rtx i3pat
= PATTERN (i3
);
1857 int i
= XVECLEN (i3pat
, 0) - 1;
1858 unsigned int regno
= REGNO (XEXP (elt
, 0));
1862 rtx i3elt
= XVECEXP (i3pat
, 0, i
);
1864 if (GET_CODE (i3elt
) == USE
1865 && REG_P (XEXP (i3elt
, 0))
1866 && (REGNO (XEXP (i3elt
, 0)) == regno
1867 ? reg_set_between_p (XEXP (elt
, 0),
1868 PREV_INSN (insn
), i3
)
1869 : regno
>= FIRST_PSEUDO_REGISTER
))
1876 /* We can ignore CLOBBERs. */
1881 /* Ignore SETs whose result isn't used but not those that
1882 have side-effects. */
1883 if (find_reg_note (insn
, REG_UNUSED
, SET_DEST (elt
))
1884 && insn_nothrow_p (insn
)
1885 && !side_effects_p (elt
))
1888 /* If we have already found a SET, this is a second one and
1889 so we cannot combine with this insn. */
1897 /* Anything else means we can't combine. */
1903 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1904 so don't do anything with it. */
1905 || GET_CODE (SET_SRC (set
)) == ASM_OPERANDS
)
1914 /* The simplification in expand_field_assignment may call back to
1915 get_last_value, so set safe guard here. */
1916 subst_low_luid
= DF_INSN_LUID (insn
);
1918 set
= expand_field_assignment (set
);
1919 src
= SET_SRC (set
), dest
= SET_DEST (set
);
1921 /* Do not eliminate user-specified register if it is in an
1922 asm input because we may break the register asm usage defined
1923 in GCC manual if allow to do so.
1924 Be aware that this may cover more cases than we expect but this
1925 should be harmless. */
1926 if (REG_P (dest
) && REG_USERVAR_P (dest
) && HARD_REGISTER_P (dest
)
1927 && extract_asm_operands (PATTERN (i3
)))
1930 /* Don't eliminate a store in the stack pointer. */
1931 if (dest
== stack_pointer_rtx
1932 /* Don't combine with an insn that sets a register to itself if it has
1933 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1934 || (rtx_equal_p (src
, dest
) && find_reg_note (insn
, REG_EQUAL
, NULL_RTX
))
1935 /* Can't merge an ASM_OPERANDS. */
1936 || GET_CODE (src
) == ASM_OPERANDS
1937 /* Can't merge a function call. */
1938 || GET_CODE (src
) == CALL
1939 /* Don't eliminate a function call argument. */
1941 && (find_reg_fusage (i3
, USE
, dest
)
1943 && REGNO (dest
) < FIRST_PSEUDO_REGISTER
1944 && global_regs
[REGNO (dest
)])))
1945 /* Don't substitute into an incremented register. */
1946 || FIND_REG_INC_NOTE (i3
, dest
)
1947 || (succ
&& FIND_REG_INC_NOTE (succ
, dest
))
1948 || (succ2
&& FIND_REG_INC_NOTE (succ2
, dest
))
1949 /* Don't substitute into a non-local goto, this confuses CFG. */
1950 || (JUMP_P (i3
) && find_reg_note (i3
, REG_NON_LOCAL_GOTO
, NULL_RTX
))
1951 /* Make sure that DEST is not used after SUCC but before I3. */
1954 && (reg_used_between_p (dest
, succ2
, i3
)
1955 || reg_used_between_p (dest
, succ
, succ2
)))
1956 || (!succ2
&& succ
&& reg_used_between_p (dest
, succ
, i3
))))
1957 /* Make sure that the value that is to be substituted for the register
1958 does not use any registers whose values alter in between. However,
1959 If the insns are adjacent, a use can't cross a set even though we
1960 think it might (this can happen for a sequence of insns each setting
1961 the same destination; last_set of that register might point to
1962 a NOTE). If INSN has a REG_EQUIV note, the register is always
1963 equivalent to the memory so the substitution is valid even if there
1964 are intervening stores. Also, don't move a volatile asm or
1965 UNSPEC_VOLATILE across any other insns. */
1968 || ! find_reg_note (insn
, REG_EQUIV
, src
))
1969 && use_crosses_set_p (src
, DF_INSN_LUID (insn
)))
1970 || (GET_CODE (src
) == ASM_OPERANDS
&& MEM_VOLATILE_P (src
))
1971 || GET_CODE (src
) == UNSPEC_VOLATILE
))
1972 /* Don't combine across a CALL_INSN, because that would possibly
1973 change whether the life span of some REGs crosses calls or not,
1974 and it is a pain to update that information.
1975 Exception: if source is a constant, moving it later can't hurt.
1976 Accept that as a special case. */
1977 || (DF_INSN_LUID (insn
) < last_call_luid
&& ! CONSTANT_P (src
)))
1980 /* DEST must either be a REG or CC0. */
1983 /* If register alignment is being enforced for multi-word items in all
1984 cases except for parameters, it is possible to have a register copy
1985 insn referencing a hard register that is not allowed to contain the
1986 mode being copied and which would not be valid as an operand of most
1987 insns. Eliminate this problem by not combining with such an insn.
1989 Also, on some machines we don't want to extend the life of a hard
1993 && ((REGNO (dest
) < FIRST_PSEUDO_REGISTER
1994 && ! HARD_REGNO_MODE_OK (REGNO (dest
), GET_MODE (dest
)))
1995 /* Don't extend the life of a hard register unless it is
1996 user variable (if we have few registers) or it can't
1997 fit into the desired register (meaning something special
1999 Also avoid substituting a return register into I3, because
2000 reload can't handle a conflict with constraints of other
2002 || (REGNO (src
) < FIRST_PSEUDO_REGISTER
2003 && ! HARD_REGNO_MODE_OK (REGNO (src
), GET_MODE (src
)))))
2006 else if (GET_CODE (dest
) != CC0
)
2010 if (GET_CODE (PATTERN (i3
)) == PARALLEL
)
2011 for (i
= XVECLEN (PATTERN (i3
), 0) - 1; i
>= 0; i
--)
2012 if (GET_CODE (XVECEXP (PATTERN (i3
), 0, i
)) == CLOBBER
)
2014 rtx reg
= XEXP (XVECEXP (PATTERN (i3
), 0, i
), 0);
2016 /* If the clobber represents an earlyclobber operand, we must not
2017 substitute an expression containing the clobbered register.
2018 As we do not analyze the constraint strings here, we have to
2019 make the conservative assumption. However, if the register is
2020 a fixed hard reg, the clobber cannot represent any operand;
2021 we leave it up to the machine description to either accept or
2022 reject use-and-clobber patterns. */
2024 || REGNO (reg
) >= FIRST_PSEUDO_REGISTER
2025 || !fixed_regs
[REGNO (reg
)])
2026 if (reg_overlap_mentioned_p (reg
, src
))
2030 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2031 or not), reject, unless nothing volatile comes between it and I3 */
2033 if (GET_CODE (src
) == ASM_OPERANDS
|| volatile_refs_p (src
))
2035 /* Make sure neither succ nor succ2 contains a volatile reference. */
2036 if (succ2
!= 0 && volatile_refs_p (PATTERN (succ2
)))
2038 if (succ
!= 0 && volatile_refs_p (PATTERN (succ
)))
2040 /* We'll check insns between INSN and I3 below. */
2043 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2044 to be an explicit register variable, and was chosen for a reason. */
2046 if (GET_CODE (src
) == ASM_OPERANDS
2047 && REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
)
2050 /* If INSN contains volatile references (specifically volatile MEMs),
2051 we cannot combine across any other volatile references.
2052 Even if INSN doesn't contain volatile references, any intervening
2053 volatile insn might affect machine state. */
2055 is_volatile_p
= volatile_refs_p (PATTERN (insn
))
2059 for (p
= NEXT_INSN (insn
); p
!= i3
; p
= NEXT_INSN (p
))
2060 if (INSN_P (p
) && p
!= succ
&& p
!= succ2
&& is_volatile_p (PATTERN (p
)))
2063 /* If INSN contains an autoincrement or autodecrement, make sure that
2064 register is not used between there and I3, and not already used in
2065 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2066 Also insist that I3 not be a jump; if it were one
2067 and the incremented register were spilled, we would lose. */
2070 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
2071 if (REG_NOTE_KIND (link
) == REG_INC
2073 || reg_used_between_p (XEXP (link
, 0), insn
, i3
)
2074 || (pred
!= NULL_RTX
2075 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred
)))
2076 || (pred2
!= NULL_RTX
2077 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (pred2
)))
2078 || (succ
!= NULL_RTX
2079 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ
)))
2080 || (succ2
!= NULL_RTX
2081 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (succ2
)))
2082 || reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i3
))))
2085 /* Don't combine an insn that follows a CC0-setting insn.
2086 An insn that uses CC0 must not be separated from the one that sets it.
2087 We do, however, allow I2 to follow a CC0-setting insn if that insn
2088 is passed as I1; in that case it will be deleted also.
2089 We also allow combining in this case if all the insns are adjacent
2090 because that would leave the two CC0 insns adjacent as well.
2091 It would be more logical to test whether CC0 occurs inside I1 or I2,
2092 but that would be much slower, and this ought to be equivalent. */
2096 p
= prev_nonnote_insn (insn
);
2097 if (p
&& p
!= pred
&& NONJUMP_INSN_P (p
) && sets_cc0_p (PATTERN (p
))
2102 /* If we get here, we have passed all the tests and the combination is
2111 /* LOC is the location within I3 that contains its pattern or the component
2112 of a PARALLEL of the pattern. We validate that it is valid for combining.
2114 One problem is if I3 modifies its output, as opposed to replacing it
2115 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2116 doing so would produce an insn that is not equivalent to the original insns.
2120 (set (reg:DI 101) (reg:DI 100))
2121 (set (subreg:SI (reg:DI 101) 0) <foo>)
2123 This is NOT equivalent to:
2125 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2126 (set (reg:DI 101) (reg:DI 100))])
2128 Not only does this modify 100 (in which case it might still be valid
2129 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2131 We can also run into a problem if I2 sets a register that I1
2132 uses and I1 gets directly substituted into I3 (not via I2). In that
2133 case, we would be getting the wrong value of I2DEST into I3, so we
2134 must reject the combination. This case occurs when I2 and I1 both
2135 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2136 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2137 of a SET must prevent combination from occurring. The same situation
2138 can occur for I0, in which case I0_NOT_IN_SRC is set.
2140 Before doing the above check, we first try to expand a field assignment
2141 into a set of logical operations.
2143 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2144 we place a register that is both set and used within I3. If more than one
2145 such register is detected, we fail.
2147 Return 1 if the combination is valid, zero otherwise. */
2150 combinable_i3pat (rtx_insn
*i3
, rtx
*loc
, rtx i2dest
, rtx i1dest
, rtx i0dest
,
2151 int i1_not_in_src
, int i0_not_in_src
, rtx
*pi3dest_killed
)
2155 if (GET_CODE (x
) == SET
)
2158 rtx dest
= SET_DEST (set
);
2159 rtx src
= SET_SRC (set
);
2160 rtx inner_dest
= dest
;
2163 while (GET_CODE (inner_dest
) == STRICT_LOW_PART
2164 || GET_CODE (inner_dest
) == SUBREG
2165 || GET_CODE (inner_dest
) == ZERO_EXTRACT
)
2166 inner_dest
= XEXP (inner_dest
, 0);
2168 /* Check for the case where I3 modifies its output, as discussed
2169 above. We don't want to prevent pseudos from being combined
2170 into the address of a MEM, so only prevent the combination if
2171 i1 or i2 set the same MEM. */
2172 if ((inner_dest
!= dest
&&
2173 (!MEM_P (inner_dest
)
2174 || rtx_equal_p (i2dest
, inner_dest
)
2175 || (i1dest
&& rtx_equal_p (i1dest
, inner_dest
))
2176 || (i0dest
&& rtx_equal_p (i0dest
, inner_dest
)))
2177 && (reg_overlap_mentioned_p (i2dest
, inner_dest
)
2178 || (i1dest
&& reg_overlap_mentioned_p (i1dest
, inner_dest
))
2179 || (i0dest
&& reg_overlap_mentioned_p (i0dest
, inner_dest
))))
2181 /* This is the same test done in can_combine_p except we can't test
2182 all_adjacent; we don't have to, since this instruction will stay
2183 in place, thus we are not considering increasing the lifetime of
2186 Also, if this insn sets a function argument, combining it with
2187 something that might need a spill could clobber a previous
2188 function argument; the all_adjacent test in can_combine_p also
2189 checks this; here, we do a more specific test for this case. */
2191 || (REG_P (inner_dest
)
2192 && REGNO (inner_dest
) < FIRST_PSEUDO_REGISTER
2193 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest
),
2194 GET_MODE (inner_dest
))))
2195 || (i1_not_in_src
&& reg_overlap_mentioned_p (i1dest
, src
))
2196 || (i0_not_in_src
&& reg_overlap_mentioned_p (i0dest
, src
)))
2199 /* If DEST is used in I3, it is being killed in this insn, so
2200 record that for later. We have to consider paradoxical
2201 subregs here, since they kill the whole register, but we
2202 ignore partial subregs, STRICT_LOW_PART, etc.
2203 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2204 STACK_POINTER_REGNUM, since these are always considered to be
2205 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2207 if (GET_CODE (subdest
) == SUBREG
2208 && (GET_MODE_SIZE (GET_MODE (subdest
))
2209 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest
)))))
2210 subdest
= SUBREG_REG (subdest
);
2213 && reg_referenced_p (subdest
, PATTERN (i3
))
2214 && REGNO (subdest
) != FRAME_POINTER_REGNUM
2215 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2216 || REGNO (subdest
) != HARD_FRAME_POINTER_REGNUM
)
2217 && (FRAME_POINTER_REGNUM
== ARG_POINTER_REGNUM
2218 || (REGNO (subdest
) != ARG_POINTER_REGNUM
2219 || ! fixed_regs
[REGNO (subdest
)]))
2220 && REGNO (subdest
) != STACK_POINTER_REGNUM
)
2222 if (*pi3dest_killed
)
2225 *pi3dest_killed
= subdest
;
2229 else if (GET_CODE (x
) == PARALLEL
)
2233 for (i
= 0; i
< XVECLEN (x
, 0); i
++)
2234 if (! combinable_i3pat (i3
, &XVECEXP (x
, 0, i
), i2dest
, i1dest
, i0dest
,
2235 i1_not_in_src
, i0_not_in_src
, pi3dest_killed
))
2242 /* Return 1 if X is an arithmetic expression that contains a multiplication
2243 and division. We don't count multiplications by powers of two here. */
2246 contains_muldiv (rtx x
)
2248 switch (GET_CODE (x
))
2250 case MOD
: case DIV
: case UMOD
: case UDIV
:
2254 return ! (CONST_INT_P (XEXP (x
, 1))
2255 && pow2p_hwi (UINTVAL (XEXP (x
, 1))));
2258 return contains_muldiv (XEXP (x
, 0))
2259 || contains_muldiv (XEXP (x
, 1));
2262 return contains_muldiv (XEXP (x
, 0));
2268 /* Determine whether INSN can be used in a combination. Return nonzero if
2269 not. This is used in try_combine to detect early some cases where we
2270 can't perform combinations. */
2273 cant_combine_insn_p (rtx_insn
*insn
)
2278 /* If this isn't really an insn, we can't do anything.
2279 This can occur when flow deletes an insn that it has merged into an
2280 auto-increment address. */
2281 if (! INSN_P (insn
))
2284 /* Never combine loads and stores involving hard regs that are likely
2285 to be spilled. The register allocator can usually handle such
2286 reg-reg moves by tying. If we allow the combiner to make
2287 substitutions of likely-spilled regs, reload might die.
2288 As an exception, we allow combinations involving fixed regs; these are
2289 not available to the register allocator so there's no risk involved. */
2291 set
= single_set (insn
);
2294 src
= SET_SRC (set
);
2295 dest
= SET_DEST (set
);
2296 if (GET_CODE (src
) == SUBREG
)
2297 src
= SUBREG_REG (src
);
2298 if (GET_CODE (dest
) == SUBREG
)
2299 dest
= SUBREG_REG (dest
);
2300 if (REG_P (src
) && REG_P (dest
)
2301 && ((HARD_REGISTER_P (src
)
2302 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (src
))
2303 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src
))))
2304 || (HARD_REGISTER_P (dest
)
2305 && ! TEST_HARD_REG_BIT (fixed_reg_set
, REGNO (dest
))
2306 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest
))))))
2312 struct likely_spilled_retval_info
2314 unsigned regno
, nregs
;
2318 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2319 hard registers that are known to be written to / clobbered in full. */
2321 likely_spilled_retval_1 (rtx x
, const_rtx set
, void *data
)
2323 struct likely_spilled_retval_info
*const info
=
2324 (struct likely_spilled_retval_info
*) data
;
2325 unsigned regno
, nregs
;
2328 if (!REG_P (XEXP (set
, 0)))
2331 if (regno
>= info
->regno
+ info
->nregs
)
2333 nregs
= REG_NREGS (x
);
2334 if (regno
+ nregs
<= info
->regno
)
2336 new_mask
= (2U << (nregs
- 1)) - 1;
2337 if (regno
< info
->regno
)
2338 new_mask
>>= info
->regno
- regno
;
2340 new_mask
<<= regno
- info
->regno
;
2341 info
->mask
&= ~new_mask
;
2344 /* Return nonzero iff part of the return value is live during INSN, and
2345 it is likely spilled. This can happen when more than one insn is needed
2346 to copy the return value, e.g. when we consider to combine into the
2347 second copy insn for a complex value. */
2350 likely_spilled_retval_p (rtx_insn
*insn
)
2352 rtx_insn
*use
= BB_END (this_basic_block
);
2355 unsigned regno
, nregs
;
2356 /* We assume here that no machine mode needs more than
2357 32 hard registers when the value overlaps with a register
2358 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2360 struct likely_spilled_retval_info info
;
2362 if (!NONJUMP_INSN_P (use
) || GET_CODE (PATTERN (use
)) != USE
|| insn
== use
)
2364 reg
= XEXP (PATTERN (use
), 0);
2365 if (!REG_P (reg
) || !targetm
.calls
.function_value_regno_p (REGNO (reg
)))
2367 regno
= REGNO (reg
);
2368 nregs
= REG_NREGS (reg
);
2371 mask
= (2U << (nregs
- 1)) - 1;
2373 /* Disregard parts of the return value that are set later. */
2377 for (p
= PREV_INSN (use
); info
.mask
&& p
!= insn
; p
= PREV_INSN (p
))
2379 note_stores (PATTERN (p
), likely_spilled_retval_1
, &info
);
2382 /* Check if any of the (probably) live return value registers is
2387 if ((mask
& 1 << nregs
)
2388 && targetm
.class_likely_spilled_p (REGNO_REG_CLASS (regno
+ nregs
)))
2394 /* Adjust INSN after we made a change to its destination.
2396 Changing the destination can invalidate notes that say something about
2397 the results of the insn and a LOG_LINK pointing to the insn. */
2400 adjust_for_new_dest (rtx_insn
*insn
)
2402 /* For notes, be conservative and simply remove them. */
2403 remove_reg_equal_equiv_notes (insn
);
2405 /* The new insn will have a destination that was previously the destination
2406 of an insn just above it. Call distribute_links to make a LOG_LINK from
2407 the next use of that destination. */
2409 rtx set
= single_set (insn
);
2412 rtx reg
= SET_DEST (set
);
2414 while (GET_CODE (reg
) == ZERO_EXTRACT
2415 || GET_CODE (reg
) == STRICT_LOW_PART
2416 || GET_CODE (reg
) == SUBREG
)
2417 reg
= XEXP (reg
, 0);
2418 gcc_assert (REG_P (reg
));
2420 distribute_links (alloc_insn_link (insn
, REGNO (reg
), NULL
));
2422 df_insn_rescan (insn
);
2425 /* Return TRUE if combine can reuse reg X in mode MODE.
2426 ADDED_SETS is nonzero if the original set is still required. */
2428 can_change_dest_mode (rtx x
, int added_sets
, machine_mode mode
)
2436 /* Allow hard registers if the new mode is legal, and occupies no more
2437 registers than the old mode. */
2438 if (regno
< FIRST_PSEUDO_REGISTER
)
2439 return (HARD_REGNO_MODE_OK (regno
, mode
)
2440 && REG_NREGS (x
) >= hard_regno_nregs
[regno
][mode
]);
2442 /* Or a pseudo that is only used once. */
2443 return (regno
< reg_n_sets_max
2444 && REG_N_SETS (regno
) == 1
2446 && !REG_USERVAR_P (x
));
2450 /* Check whether X, the destination of a set, refers to part of
2451 the register specified by REG. */
2454 reg_subword_p (rtx x
, rtx reg
)
2456 /* Check that reg is an integer mode register. */
2457 if (!REG_P (reg
) || GET_MODE_CLASS (GET_MODE (reg
)) != MODE_INT
)
2460 if (GET_CODE (x
) == STRICT_LOW_PART
2461 || GET_CODE (x
) == ZERO_EXTRACT
)
2464 return GET_CODE (x
) == SUBREG
2465 && SUBREG_REG (x
) == reg
2466 && GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
;
2469 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2470 Note that the INSN should be deleted *after* removing dead edges, so
2471 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2472 but not for a (set (pc) (label_ref FOO)). */
2475 update_cfg_for_uncondjump (rtx_insn
*insn
)
2477 basic_block bb
= BLOCK_FOR_INSN (insn
);
2478 gcc_assert (BB_END (bb
) == insn
);
2480 purge_dead_edges (bb
);
2483 if (EDGE_COUNT (bb
->succs
) == 1)
2487 single_succ_edge (bb
)->flags
|= EDGE_FALLTHRU
;
2489 /* Remove barriers from the footer if there are any. */
2490 for (insn
= BB_FOOTER (bb
); insn
; insn
= NEXT_INSN (insn
))
2491 if (BARRIER_P (insn
))
2493 if (PREV_INSN (insn
))
2494 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
2496 BB_FOOTER (bb
) = NEXT_INSN (insn
);
2497 if (NEXT_INSN (insn
))
2498 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
2500 else if (LABEL_P (insn
))
2505 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2506 by an arbitrary number of CLOBBERs. */
2508 is_parallel_of_n_reg_sets (rtx pat
, int n
)
2510 if (GET_CODE (pat
) != PARALLEL
)
2513 int len
= XVECLEN (pat
, 0);
2518 for (i
= 0; i
< n
; i
++)
2519 if (GET_CODE (XVECEXP (pat
, 0, i
)) != SET
2520 || !REG_P (SET_DEST (XVECEXP (pat
, 0, i
))))
2522 for ( ; i
< len
; i
++)
2523 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
2524 || XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
2530 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2531 CLOBBERs), can be split into individual SETs in that order, without
2532 changing semantics. */
2534 can_split_parallel_of_n_reg_sets (rtx_insn
*insn
, int n
)
2536 if (!insn_nothrow_p (insn
))
2539 rtx pat
= PATTERN (insn
);
2542 for (i
= 0; i
< n
; i
++)
2544 if (side_effects_p (SET_SRC (XVECEXP (pat
, 0, i
))))
2547 rtx reg
= SET_DEST (XVECEXP (pat
, 0, i
));
2549 for (j
= i
+ 1; j
< n
; j
++)
2550 if (reg_referenced_p (reg
, XVECEXP (pat
, 0, j
)))
2557 /* Try to combine the insns I0, I1 and I2 into I3.
2558 Here I0, I1 and I2 appear earlier than I3.
2559 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2562 If we are combining more than two insns and the resulting insn is not
2563 recognized, try splitting it into two insns. If that happens, I2 and I3
2564 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2565 Otherwise, I0, I1 and I2 are pseudo-deleted.
2567 Return 0 if the combination does not work. Then nothing is changed.
2568 If we did the combination, return the insn at which combine should
2571 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2572 new direct jump instruction.
2574 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2575 been I3 passed to an earlier try_combine within the same basic
2579 try_combine (rtx_insn
*i3
, rtx_insn
*i2
, rtx_insn
*i1
, rtx_insn
*i0
,
2580 int *new_direct_jump_p
, rtx_insn
*last_combined_insn
)
2582 /* New patterns for I3 and I2, respectively. */
2583 rtx newpat
, newi2pat
= 0;
2584 rtvec newpat_vec_with_clobbers
= 0;
2585 int substed_i2
= 0, substed_i1
= 0, substed_i0
= 0;
2586 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2588 int added_sets_0
, added_sets_1
, added_sets_2
;
2589 /* Total number of SETs to put into I3. */
2591 /* Nonzero if I2's or I1's body now appears in I3. */
2592 int i2_is_used
= 0, i1_is_used
= 0;
2593 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2594 int insn_code_number
, i2_code_number
= 0, other_code_number
= 0;
2595 /* Contains I3 if the destination of I3 is used in its source, which means
2596 that the old life of I3 is being killed. If that usage is placed into
2597 I2 and not in I3, a REG_DEAD note must be made. */
2598 rtx i3dest_killed
= 0;
2599 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2600 rtx i2dest
= 0, i2src
= 0, i1dest
= 0, i1src
= 0, i0dest
= 0, i0src
= 0;
2601 /* Copy of SET_SRC of I1 and I0, if needed. */
2602 rtx i1src_copy
= 0, i0src_copy
= 0, i0src_copy2
= 0;
2603 /* Set if I2DEST was reused as a scratch register. */
2604 bool i2scratch
= false;
2605 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2606 rtx i0pat
= 0, i1pat
= 0, i2pat
= 0;
2607 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2608 int i2dest_in_i2src
= 0, i1dest_in_i1src
= 0, i2dest_in_i1src
= 0;
2609 int i0dest_in_i0src
= 0, i1dest_in_i0src
= 0, i2dest_in_i0src
= 0;
2610 int i2dest_killed
= 0, i1dest_killed
= 0, i0dest_killed
= 0;
2611 int i1_feeds_i2_n
= 0, i0_feeds_i2_n
= 0, i0_feeds_i1_n
= 0;
2612 /* Notes that must be added to REG_NOTES in I3 and I2. */
2613 rtx new_i3_notes
, new_i2_notes
;
2614 /* Notes that we substituted I3 into I2 instead of the normal case. */
2615 int i3_subst_into_i2
= 0;
2616 /* Notes that I1, I2 or I3 is a MULT operation. */
2619 int changed_i3_dest
= 0;
2622 rtx_insn
*temp_insn
;
2624 struct insn_link
*link
;
2626 rtx new_other_notes
;
2629 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2631 if (i1
== i2
|| i0
== i2
|| (i0
&& i0
== i1
))
2634 /* Only try four-insn combinations when there's high likelihood of
2635 success. Look for simple insns, such as loads of constants or
2636 binary operations involving a constant. */
2644 if (!flag_expensive_optimizations
)
2647 for (i
= 0; i
< 4; i
++)
2649 rtx_insn
*insn
= i
== 0 ? i0
: i
== 1 ? i1
: i
== 2 ? i2
: i3
;
2650 rtx set
= single_set (insn
);
2654 src
= SET_SRC (set
);
2655 if (CONSTANT_P (src
))
2660 else if (BINARY_P (src
) && CONSTANT_P (XEXP (src
, 1)))
2662 else if (GET_CODE (src
) == ASHIFT
|| GET_CODE (src
) == ASHIFTRT
2663 || GET_CODE (src
) == LSHIFTRT
)
2667 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2668 are likely manipulating its value. Ideally we'll be able to combine
2669 all four insns into a bitfield insertion of some kind.
2671 Note the source in I0 might be inside a sign/zero extension and the
2672 memory modes in I0 and I3 might be different. So extract the address
2673 from the destination of I3 and search for it in the source of I0.
2675 In the event that there's a match but the source/dest do not actually
2676 refer to the same memory, the worst that happens is we try some
2677 combinations that we wouldn't have otherwise. */
2678 if ((set0
= single_set (i0
))
2679 /* Ensure the source of SET0 is a MEM, possibly buried inside
2681 && (GET_CODE (SET_SRC (set0
)) == MEM
2682 || ((GET_CODE (SET_SRC (set0
)) == ZERO_EXTEND
2683 || GET_CODE (SET_SRC (set0
)) == SIGN_EXTEND
)
2684 && GET_CODE (XEXP (SET_SRC (set0
), 0)) == MEM
))
2685 && (set3
= single_set (i3
))
2686 /* Ensure the destination of SET3 is a MEM. */
2687 && GET_CODE (SET_DEST (set3
)) == MEM
2688 /* Would it be better to extract the base address for the MEM
2689 in SET3 and look for that? I don't have cases where it matters
2690 but I could envision such cases. */
2691 && rtx_referenced_p (XEXP (SET_DEST (set3
), 0), SET_SRC (set0
)))
2694 if (ngood
< 2 && nshift
< 2)
2698 /* Exit early if one of the insns involved can't be used for
2701 || (i1
&& CALL_P (i1
))
2702 || (i0
&& CALL_P (i0
))
2703 || cant_combine_insn_p (i3
)
2704 || cant_combine_insn_p (i2
)
2705 || (i1
&& cant_combine_insn_p (i1
))
2706 || (i0
&& cant_combine_insn_p (i0
))
2707 || likely_spilled_retval_p (i3
))
2711 undobuf
.other_insn
= 0;
2713 /* Reset the hard register usage information. */
2714 CLEAR_HARD_REG_SET (newpat_used_regs
);
2716 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
2719 fprintf (dump_file
, "\nTrying %d, %d, %d -> %d:\n",
2720 INSN_UID (i0
), INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2722 fprintf (dump_file
, "\nTrying %d, %d -> %d:\n",
2723 INSN_UID (i1
), INSN_UID (i2
), INSN_UID (i3
));
2725 fprintf (dump_file
, "\nTrying %d -> %d:\n",
2726 INSN_UID (i2
), INSN_UID (i3
));
2729 /* If multiple insns feed into one of I2 or I3, they can be in any
2730 order. To simplify the code below, reorder them in sequence. */
2731 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i2
))
2733 if (i0
&& DF_INSN_LUID (i0
) > DF_INSN_LUID (i1
))
2735 if (i1
&& DF_INSN_LUID (i1
) > DF_INSN_LUID (i2
))
2738 added_links_insn
= 0;
2740 /* First check for one important special case that the code below will
2741 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2742 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2743 we may be able to replace that destination with the destination of I3.
2744 This occurs in the common code where we compute both a quotient and
2745 remainder into a structure, in which case we want to do the computation
2746 directly into the structure to avoid register-register copies.
2748 Note that this case handles both multiple sets in I2 and also cases
2749 where I2 has a number of CLOBBERs inside the PARALLEL.
2751 We make very conservative checks below and only try to handle the
2752 most common cases of this. For example, we only handle the case
2753 where I2 and I3 are adjacent to avoid making difficult register
2756 if (i1
== 0 && NONJUMP_INSN_P (i3
) && GET_CODE (PATTERN (i3
)) == SET
2757 && REG_P (SET_SRC (PATTERN (i3
)))
2758 && REGNO (SET_SRC (PATTERN (i3
))) >= FIRST_PSEUDO_REGISTER
2759 && find_reg_note (i3
, REG_DEAD
, SET_SRC (PATTERN (i3
)))
2760 && GET_CODE (PATTERN (i2
)) == PARALLEL
2761 && ! side_effects_p (SET_DEST (PATTERN (i3
)))
2762 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2763 below would need to check what is inside (and reg_overlap_mentioned_p
2764 doesn't support those codes anyway). Don't allow those destinations;
2765 the resulting insn isn't likely to be recognized anyway. */
2766 && GET_CODE (SET_DEST (PATTERN (i3
))) != ZERO_EXTRACT
2767 && GET_CODE (SET_DEST (PATTERN (i3
))) != STRICT_LOW_PART
2768 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3
)),
2769 SET_DEST (PATTERN (i3
)))
2770 && next_active_insn (i2
) == i3
)
2772 rtx p2
= PATTERN (i2
);
2774 /* Make sure that the destination of I3,
2775 which we are going to substitute into one output of I2,
2776 is not used within another output of I2. We must avoid making this:
2777 (parallel [(set (mem (reg 69)) ...)
2778 (set (reg 69) ...)])
2779 which is not well-defined as to order of actions.
2780 (Besides, reload can't handle output reloads for this.)
2782 The problem can also happen if the dest of I3 is a memory ref,
2783 if another dest in I2 is an indirect memory ref. */
2784 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2785 if ((GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2786 || GET_CODE (XVECEXP (p2
, 0, i
)) == CLOBBER
)
2787 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3
)),
2788 SET_DEST (XVECEXP (p2
, 0, i
))))
2791 /* Make sure this PARALLEL is not an asm. We do not allow combining
2792 that usually (see can_combine_p), so do not here either. */
2793 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2794 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2795 && GET_CODE (SET_SRC (XVECEXP (p2
, 0, i
))) == ASM_OPERANDS
)
2798 if (i
== XVECLEN (p2
, 0))
2799 for (i
= 0; i
< XVECLEN (p2
, 0); i
++)
2800 if (GET_CODE (XVECEXP (p2
, 0, i
)) == SET
2801 && SET_DEST (XVECEXP (p2
, 0, i
)) == SET_SRC (PATTERN (i3
)))
2806 subst_low_luid
= DF_INSN_LUID (i2
);
2808 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2809 i2src
= SET_SRC (XVECEXP (p2
, 0, i
));
2810 i2dest
= SET_DEST (XVECEXP (p2
, 0, i
));
2811 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2813 /* Replace the dest in I2 with our dest and make the resulting
2814 insn the new pattern for I3. Then skip to where we validate
2815 the pattern. Everything was set up above. */
2816 SUBST (SET_DEST (XVECEXP (p2
, 0, i
)), SET_DEST (PATTERN (i3
)));
2818 i3_subst_into_i2
= 1;
2819 goto validate_replacement
;
2823 /* If I2 is setting a pseudo to a constant and I3 is setting some
2824 sub-part of it to another constant, merge them by making a new
2827 && (temp_expr
= single_set (i2
)) != 0
2828 && CONST_SCALAR_INT_P (SET_SRC (temp_expr
))
2829 && GET_CODE (PATTERN (i3
)) == SET
2830 && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3
)))
2831 && reg_subword_p (SET_DEST (PATTERN (i3
)), SET_DEST (temp_expr
)))
2833 rtx dest
= SET_DEST (PATTERN (i3
));
2837 if (GET_CODE (dest
) == ZERO_EXTRACT
)
2839 if (CONST_INT_P (XEXP (dest
, 1))
2840 && CONST_INT_P (XEXP (dest
, 2)))
2842 width
= INTVAL (XEXP (dest
, 1));
2843 offset
= INTVAL (XEXP (dest
, 2));
2844 dest
= XEXP (dest
, 0);
2845 if (BITS_BIG_ENDIAN
)
2846 offset
= GET_MODE_PRECISION (GET_MODE (dest
)) - width
- offset
;
2851 if (GET_CODE (dest
) == STRICT_LOW_PART
)
2852 dest
= XEXP (dest
, 0);
2853 width
= GET_MODE_PRECISION (GET_MODE (dest
));
2859 /* If this is the low part, we're done. */
2860 if (subreg_lowpart_p (dest
))
2862 /* Handle the case where inner is twice the size of outer. */
2863 else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp_expr
)))
2864 == 2 * GET_MODE_PRECISION (GET_MODE (dest
)))
2865 offset
+= GET_MODE_PRECISION (GET_MODE (dest
));
2866 /* Otherwise give up for now. */
2873 rtx inner
= SET_SRC (PATTERN (i3
));
2874 rtx outer
= SET_SRC (temp_expr
);
2877 = wi::insert (std::make_pair (outer
, GET_MODE (SET_DEST (temp_expr
))),
2878 std::make_pair (inner
, GET_MODE (dest
)),
2883 subst_low_luid
= DF_INSN_LUID (i2
);
2884 added_sets_2
= added_sets_1
= added_sets_0
= 0;
2885 i2dest
= SET_DEST (temp_expr
);
2886 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2888 /* Replace the source in I2 with the new constant and make the
2889 resulting insn the new pattern for I3. Then skip to where we
2890 validate the pattern. Everything was set up above. */
2891 SUBST (SET_SRC (temp_expr
),
2892 immed_wide_int_const (o
, GET_MODE (SET_DEST (temp_expr
))));
2894 newpat
= PATTERN (i2
);
2896 /* The dest of I3 has been replaced with the dest of I2. */
2897 changed_i3_dest
= 1;
2898 goto validate_replacement
;
2902 /* If we have no I1 and I2 looks like:
2903 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2905 make up a dummy I1 that is
2908 (set (reg:CC X) (compare:CC Y (const_int 0)))
2910 (We can ignore any trailing CLOBBERs.)
2912 This undoes a previous combination and allows us to match a branch-and-
2915 if (!HAVE_cc0
&& i1
== 0
2916 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2917 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0))))
2919 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0))) == COMPARE
2920 && XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 1) == const0_rtx
2921 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2
), 0, 0)), 0),
2922 SET_SRC (XVECEXP (PATTERN (i2
), 0, 1)))
2923 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2924 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2926 /* We make I1 with the same INSN_UID as I2. This gives it
2927 the same DF_INSN_LUID for value tracking. Our fake I1 will
2928 never appear in the insn stream so giving it the same INSN_UID
2929 as I2 will not cause a problem. */
2931 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2932 XVECEXP (PATTERN (i2
), 0, 1), INSN_LOCATION (i2
),
2934 INSN_UID (i1
) = INSN_UID (i2
);
2936 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 0));
2937 SUBST (XEXP (SET_SRC (PATTERN (i2
)), 0),
2938 SET_DEST (PATTERN (i1
)));
2939 unsigned int regno
= REGNO (SET_DEST (PATTERN (i1
)));
2940 SUBST_LINK (LOG_LINKS (i2
),
2941 alloc_insn_link (i1
, regno
, LOG_LINKS (i2
)));
2944 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2945 make those two SETs separate I1 and I2 insns, and make an I0 that is
2947 if (!HAVE_cc0
&& i0
== 0
2948 && is_parallel_of_n_reg_sets (PATTERN (i2
), 2)
2949 && can_split_parallel_of_n_reg_sets (i2
, 2)
2950 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 0)), i2
, i3
)
2951 && !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2
), 0, 1)), i2
, i3
))
2953 /* If there is no I1, there is no I0 either. */
2956 /* We make I1 with the same INSN_UID as I2. This gives it
2957 the same DF_INSN_LUID for value tracking. Our fake I1 will
2958 never appear in the insn stream so giving it the same INSN_UID
2959 as I2 will not cause a problem. */
2961 i1
= gen_rtx_INSN (VOIDmode
, NULL
, i2
, BLOCK_FOR_INSN (i2
),
2962 XVECEXP (PATTERN (i2
), 0, 0), INSN_LOCATION (i2
),
2964 INSN_UID (i1
) = INSN_UID (i2
);
2966 SUBST (PATTERN (i2
), XVECEXP (PATTERN (i2
), 0, 1));
2969 /* Verify that I2 and I1 are valid for combining. */
2970 if (! can_combine_p (i2
, i3
, i0
, i1
, NULL
, NULL
, &i2dest
, &i2src
)
2971 || (i1
&& ! can_combine_p (i1
, i3
, i0
, NULL
, i2
, NULL
,
2973 || (i0
&& ! can_combine_p (i0
, i3
, NULL
, NULL
, i1
, i2
,
2980 /* Record whether I2DEST is used in I2SRC and similarly for the other
2981 cases. Knowing this will help in register status updating below. */
2982 i2dest_in_i2src
= reg_overlap_mentioned_p (i2dest
, i2src
);
2983 i1dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i1dest
, i1src
);
2984 i2dest_in_i1src
= i1
&& reg_overlap_mentioned_p (i2dest
, i1src
);
2985 i0dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i0dest
, i0src
);
2986 i1dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i1dest
, i0src
);
2987 i2dest_in_i0src
= i0
&& reg_overlap_mentioned_p (i2dest
, i0src
);
2988 i2dest_killed
= dead_or_set_p (i2
, i2dest
);
2989 i1dest_killed
= i1
&& dead_or_set_p (i1
, i1dest
);
2990 i0dest_killed
= i0
&& dead_or_set_p (i0
, i0dest
);
2992 /* For the earlier insns, determine which of the subsequent ones they
2994 i1_feeds_i2_n
= i1
&& insn_a_feeds_b (i1
, i2
);
2995 i0_feeds_i1_n
= i0
&& insn_a_feeds_b (i0
, i1
);
2996 i0_feeds_i2_n
= (i0
&& (!i0_feeds_i1_n
? insn_a_feeds_b (i0
, i2
)
2997 : (!reg_overlap_mentioned_p (i1dest
, i0dest
)
2998 && reg_overlap_mentioned_p (i0dest
, i2src
))));
3000 /* Ensure that I3's pattern can be the destination of combines. */
3001 if (! combinable_i3pat (i3
, &PATTERN (i3
), i2dest
, i1dest
, i0dest
,
3002 i1
&& i2dest_in_i1src
&& !i1_feeds_i2_n
,
3003 i0
&& ((i2dest_in_i0src
&& !i0_feeds_i2_n
)
3004 || (i1dest_in_i0src
&& !i0_feeds_i1_n
)),
3011 /* See if any of the insns is a MULT operation. Unless one is, we will
3012 reject a combination that is, since it must be slower. Be conservative
3014 if (GET_CODE (i2src
) == MULT
3015 || (i1
!= 0 && GET_CODE (i1src
) == MULT
)
3016 || (i0
!= 0 && GET_CODE (i0src
) == MULT
)
3017 || (GET_CODE (PATTERN (i3
)) == SET
3018 && GET_CODE (SET_SRC (PATTERN (i3
))) == MULT
))
3021 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3022 We used to do this EXCEPT in one case: I3 has a post-inc in an
3023 output operand. However, that exception can give rise to insns like
3025 which is a famous insn on the PDP-11 where the value of r3 used as the
3026 source was model-dependent. Avoid this sort of thing. */
3029 if (!(GET_CODE (PATTERN (i3
)) == SET
3030 && REG_P (SET_SRC (PATTERN (i3
)))
3031 && MEM_P (SET_DEST (PATTERN (i3
)))
3032 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_INC
3033 || GET_CODE (XEXP (SET_DEST (PATTERN (i3
)), 0)) == POST_DEC
)))
3034 /* It's not the exception. */
3039 for (link
= REG_NOTES (i3
); link
; link
= XEXP (link
, 1))
3040 if (REG_NOTE_KIND (link
) == REG_INC
3041 && (reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i2
))
3043 && reg_overlap_mentioned_p (XEXP (link
, 0), PATTERN (i1
)))))
3050 /* See if the SETs in I1 or I2 need to be kept around in the merged
3051 instruction: whenever the value set there is still needed past I3.
3052 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3054 For the SET in I1, we have two cases: if I1 and I2 independently feed
3055 into I3, the set in I1 needs to be kept around unless I1DEST dies
3056 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3057 in I1 needs to be kept around unless I1DEST dies or is set in either
3058 I2 or I3. The same considerations apply to I0. */
3060 added_sets_2
= !dead_or_set_p (i3
, i2dest
);
3063 added_sets_1
= !(dead_or_set_p (i3
, i1dest
)
3064 || (i1_feeds_i2_n
&& dead_or_set_p (i2
, i1dest
)));
3069 added_sets_0
= !(dead_or_set_p (i3
, i0dest
)
3070 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
))
3071 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3072 && dead_or_set_p (i2
, i0dest
)));
3076 /* We are about to copy insns for the case where they need to be kept
3077 around. Check that they can be copied in the merged instruction. */
3079 if (targetm
.cannot_copy_insn_p
3080 && ((added_sets_2
&& targetm
.cannot_copy_insn_p (i2
))
3081 || (i1
&& added_sets_1
&& targetm
.cannot_copy_insn_p (i1
))
3082 || (i0
&& added_sets_0
&& targetm
.cannot_copy_insn_p (i0
))))
3088 /* If the set in I2 needs to be kept around, we must make a copy of
3089 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3090 PATTERN (I2), we are only substituting for the original I1DEST, not into
3091 an already-substituted copy. This also prevents making self-referential
3092 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3097 if (GET_CODE (PATTERN (i2
)) == PARALLEL
)
3098 i2pat
= gen_rtx_SET (i2dest
, copy_rtx (i2src
));
3100 i2pat
= copy_rtx (PATTERN (i2
));
3105 if (GET_CODE (PATTERN (i1
)) == PARALLEL
)
3106 i1pat
= gen_rtx_SET (i1dest
, copy_rtx (i1src
));
3108 i1pat
= copy_rtx (PATTERN (i1
));
3113 if (GET_CODE (PATTERN (i0
)) == PARALLEL
)
3114 i0pat
= gen_rtx_SET (i0dest
, copy_rtx (i0src
));
3116 i0pat
= copy_rtx (PATTERN (i0
));
3121 /* Substitute in the latest insn for the regs set by the earlier ones. */
3123 maxreg
= max_reg_num ();
3127 /* Many machines that don't use CC0 have insns that can both perform an
3128 arithmetic operation and set the condition code. These operations will
3129 be represented as a PARALLEL with the first element of the vector
3130 being a COMPARE of an arithmetic operation with the constant zero.
3131 The second element of the vector will set some pseudo to the result
3132 of the same arithmetic operation. If we simplify the COMPARE, we won't
3133 match such a pattern and so will generate an extra insn. Here we test
3134 for this case, where both the comparison and the operation result are
3135 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3136 I2SRC. Later we will make the PARALLEL that contains I2. */
3138 if (!HAVE_cc0
&& i1
== 0 && added_sets_2
&& GET_CODE (PATTERN (i3
)) == SET
3139 && GET_CODE (SET_SRC (PATTERN (i3
))) == COMPARE
3140 && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3
)), 1))
3141 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3
)), 0), i2dest
))
3144 rtx
*cc_use_loc
= NULL
;
3145 rtx_insn
*cc_use_insn
= NULL
;
3146 rtx op0
= i2src
, op1
= XEXP (SET_SRC (PATTERN (i3
)), 1);
3147 machine_mode compare_mode
, orig_compare_mode
;
3148 enum rtx_code compare_code
= UNKNOWN
, orig_compare_code
= UNKNOWN
;
3150 newpat
= PATTERN (i3
);
3151 newpat_dest
= SET_DEST (newpat
);
3152 compare_mode
= orig_compare_mode
= GET_MODE (newpat_dest
);
3154 if (undobuf
.other_insn
== 0
3155 && (cc_use_loc
= find_single_use (SET_DEST (newpat
), i3
,
3158 compare_code
= orig_compare_code
= GET_CODE (*cc_use_loc
);
3159 compare_code
= simplify_compare_const (compare_code
,
3160 GET_MODE (i2dest
), op0
, &op1
);
3161 target_canonicalize_comparison (&compare_code
, &op0
, &op1
, 1);
3164 /* Do the rest only if op1 is const0_rtx, which may be the
3165 result of simplification. */
3166 if (op1
== const0_rtx
)
3168 /* If a single use of the CC is found, prepare to modify it
3169 when SELECT_CC_MODE returns a new CC-class mode, or when
3170 the above simplify_compare_const() returned a new comparison
3171 operator. undobuf.other_insn is assigned the CC use insn
3172 when modifying it. */
3175 #ifdef SELECT_CC_MODE
3176 machine_mode new_mode
3177 = SELECT_CC_MODE (compare_code
, op0
, op1
);
3178 if (new_mode
!= orig_compare_mode
3179 && can_change_dest_mode (SET_DEST (newpat
),
3180 added_sets_2
, new_mode
))
3182 unsigned int regno
= REGNO (newpat_dest
);
3183 compare_mode
= new_mode
;
3184 if (regno
< FIRST_PSEUDO_REGISTER
)
3185 newpat_dest
= gen_rtx_REG (compare_mode
, regno
);
3188 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
3189 newpat_dest
= regno_reg_rtx
[regno
];
3193 /* Cases for modifying the CC-using comparison. */
3194 if (compare_code
!= orig_compare_code
3195 /* ??? Do we need to verify the zero rtx? */
3196 && XEXP (*cc_use_loc
, 1) == const0_rtx
)
3198 /* Replace cc_use_loc with entire new RTX. */
3200 gen_rtx_fmt_ee (compare_code
, compare_mode
,
3201 newpat_dest
, const0_rtx
));
3202 undobuf
.other_insn
= cc_use_insn
;
3204 else if (compare_mode
!= orig_compare_mode
)
3206 /* Just replace the CC reg with a new mode. */
3207 SUBST (XEXP (*cc_use_loc
, 0), newpat_dest
);
3208 undobuf
.other_insn
= cc_use_insn
;
3212 /* Now we modify the current newpat:
3213 First, SET_DEST(newpat) is updated if the CC mode has been
3214 altered. For targets without SELECT_CC_MODE, this should be
3216 if (compare_mode
!= orig_compare_mode
)
3217 SUBST (SET_DEST (newpat
), newpat_dest
);
3218 /* This is always done to propagate i2src into newpat. */
3219 SUBST (SET_SRC (newpat
),
3220 gen_rtx_COMPARE (compare_mode
, op0
, op1
));
3221 /* Create new version of i2pat if needed; the below PARALLEL
3222 creation needs this to work correctly. */
3223 if (! rtx_equal_p (i2src
, op0
))
3224 i2pat
= gen_rtx_SET (i2dest
, op0
);
3229 if (i2_is_used
== 0)
3231 /* It is possible that the source of I2 or I1 may be performing
3232 an unneeded operation, such as a ZERO_EXTEND of something
3233 that is known to have the high part zero. Handle that case
3234 by letting subst look at the inner insns.
3236 Another way to do this would be to have a function that tries
3237 to simplify a single insn instead of merging two or more
3238 insns. We don't do this because of the potential of infinite
3239 loops and because of the potential extra memory required.
3240 However, doing it the way we are is a bit of a kludge and
3241 doesn't catch all cases.
3243 But only do this if -fexpensive-optimizations since it slows
3244 things down and doesn't usually win.
3246 This is not done in the COMPARE case above because the
3247 unmodified I2PAT is used in the PARALLEL and so a pattern
3248 with a modified I2SRC would not match. */
3250 if (flag_expensive_optimizations
)
3252 /* Pass pc_rtx so no substitutions are done, just
3256 subst_low_luid
= DF_INSN_LUID (i1
);
3257 i1src
= subst (i1src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3260 subst_low_luid
= DF_INSN_LUID (i2
);
3261 i2src
= subst (i2src
, pc_rtx
, pc_rtx
, 0, 0, 0);
3264 n_occurrences
= 0; /* `subst' counts here */
3265 subst_low_luid
= DF_INSN_LUID (i2
);
3267 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3268 copy of I2SRC each time we substitute it, in order to avoid creating
3269 self-referential RTL when we will be substituting I1SRC for I1DEST
3270 later. Likewise if I0 feeds into I2, either directly or indirectly
3271 through I1, and I0DEST is in I0SRC. */
3272 newpat
= subst (PATTERN (i3
), i2dest
, i2src
, 0, 0,
3273 (i1_feeds_i2_n
&& i1dest_in_i1src
)
3274 || ((i0_feeds_i2_n
|| (i0_feeds_i1_n
&& i1_feeds_i2_n
))
3275 && i0dest_in_i0src
));
3278 /* Record whether I2's body now appears within I3's body. */
3279 i2_is_used
= n_occurrences
;
3282 /* If we already got a failure, don't try to do more. Otherwise, try to
3283 substitute I1 if we have it. */
3285 if (i1
&& GET_CODE (newpat
) != CLOBBER
)
3287 /* Check that an autoincrement side-effect on I1 has not been lost.
3288 This happens if I1DEST is mentioned in I2 and dies there, and
3289 has disappeared from the new pattern. */
3290 if ((FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3292 && dead_or_set_p (i2
, i1dest
)
3293 && !reg_overlap_mentioned_p (i1dest
, newpat
))
3294 /* Before we can do this substitution, we must redo the test done
3295 above (see detailed comments there) that ensures I1DEST isn't
3296 mentioned in any SETs in NEWPAT that are field assignments. */
3297 || !combinable_i3pat (NULL
, &newpat
, i1dest
, NULL_RTX
, NULL_RTX
,
3305 subst_low_luid
= DF_INSN_LUID (i1
);
3307 /* If the following substitution will modify I1SRC, make a copy of it
3308 for the case where it is substituted for I1DEST in I2PAT later. */
3309 if (added_sets_2
&& i1_feeds_i2_n
)
3310 i1src_copy
= copy_rtx (i1src
);
3312 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3313 copy of I1SRC each time we substitute it, in order to avoid creating
3314 self-referential RTL when we will be substituting I0SRC for I0DEST
3316 newpat
= subst (newpat
, i1dest
, i1src
, 0, 0,
3317 i0_feeds_i1_n
&& i0dest_in_i0src
);
3320 /* Record whether I1's body now appears within I3's body. */
3321 i1_is_used
= n_occurrences
;
3324 /* Likewise for I0 if we have it. */
3326 if (i0
&& GET_CODE (newpat
) != CLOBBER
)
3328 if ((FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3329 && ((i0_feeds_i2_n
&& dead_or_set_p (i2
, i0dest
))
3330 || (i0_feeds_i1_n
&& dead_or_set_p (i1
, i0dest
)))
3331 && !reg_overlap_mentioned_p (i0dest
, newpat
))
3332 || !combinable_i3pat (NULL
, &newpat
, i0dest
, NULL_RTX
, NULL_RTX
,
3339 /* If the following substitution will modify I0SRC, make a copy of it
3340 for the case where it is substituted for I0DEST in I1PAT later. */
3341 if (added_sets_1
&& i0_feeds_i1_n
)
3342 i0src_copy
= copy_rtx (i0src
);
3343 /* And a copy for I0DEST in I2PAT substitution. */
3344 if (added_sets_2
&& ((i0_feeds_i1_n
&& i1_feeds_i2_n
)
3345 || (i0_feeds_i2_n
)))
3346 i0src_copy2
= copy_rtx (i0src
);
3349 subst_low_luid
= DF_INSN_LUID (i0
);
3350 newpat
= subst (newpat
, i0dest
, i0src
, 0, 0, 0);
3354 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3355 to count all the ways that I2SRC and I1SRC can be used. */
3356 if ((FIND_REG_INC_NOTE (i2
, NULL_RTX
) != 0
3357 && i2_is_used
+ added_sets_2
> 1)
3358 || (i1
!= 0 && FIND_REG_INC_NOTE (i1
, NULL_RTX
) != 0
3359 && (i1_is_used
+ added_sets_1
+ (added_sets_2
&& i1_feeds_i2_n
)
3361 || (i0
!= 0 && FIND_REG_INC_NOTE (i0
, NULL_RTX
) != 0
3362 && (n_occurrences
+ added_sets_0
3363 + (added_sets_1
&& i0_feeds_i1_n
)
3364 + (added_sets_2
&& i0_feeds_i2_n
)
3366 /* Fail if we tried to make a new register. */
3367 || max_reg_num () != maxreg
3368 /* Fail if we couldn't do something and have a CLOBBER. */
3369 || GET_CODE (newpat
) == CLOBBER
3370 /* Fail if this new pattern is a MULT and we didn't have one before
3371 at the outer level. */
3372 || (GET_CODE (newpat
) == SET
&& GET_CODE (SET_SRC (newpat
)) == MULT
3379 /* If the actions of the earlier insns must be kept
3380 in addition to substituting them into the latest one,
3381 we must make a new PARALLEL for the latest insn
3382 to hold additional the SETs. */
3384 if (added_sets_0
|| added_sets_1
|| added_sets_2
)
3386 int extra_sets
= added_sets_0
+ added_sets_1
+ added_sets_2
;
3389 if (GET_CODE (newpat
) == PARALLEL
)
3391 rtvec old
= XVEC (newpat
, 0);
3392 total_sets
= XVECLEN (newpat
, 0) + extra_sets
;
3393 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3394 memcpy (XVEC (newpat
, 0)->elem
, &old
->elem
[0],
3395 sizeof (old
->elem
[0]) * old
->num_elem
);
3400 total_sets
= 1 + extra_sets
;
3401 newpat
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (total_sets
));
3402 XVECEXP (newpat
, 0, 0) = old
;
3406 XVECEXP (newpat
, 0, --total_sets
) = i0pat
;
3412 t
= subst (t
, i0dest
, i0src_copy
? i0src_copy
: i0src
, 0, 0, 0);
3414 XVECEXP (newpat
, 0, --total_sets
) = t
;
3420 t
= subst (t
, i1dest
, i1src_copy
? i1src_copy
: i1src
, 0, 0,
3421 i0_feeds_i1_n
&& i0dest_in_i0src
);
3422 if ((i0_feeds_i1_n
&& i1_feeds_i2_n
) || i0_feeds_i2_n
)
3423 t
= subst (t
, i0dest
, i0src_copy2
? i0src_copy2
: i0src
, 0, 0, 0);
3425 XVECEXP (newpat
, 0, --total_sets
) = t
;
3429 validate_replacement
:
3431 /* Note which hard regs this insn has as inputs. */
3432 mark_used_regs_combine (newpat
);
3434 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3435 consider splitting this pattern, we might need these clobbers. */
3436 if (i1
&& GET_CODE (newpat
) == PARALLEL
3437 && GET_CODE (XVECEXP (newpat
, 0, XVECLEN (newpat
, 0) - 1)) == CLOBBER
)
3439 int len
= XVECLEN (newpat
, 0);
3441 newpat_vec_with_clobbers
= rtvec_alloc (len
);
3442 for (i
= 0; i
< len
; i
++)
3443 RTVEC_ELT (newpat_vec_with_clobbers
, i
) = XVECEXP (newpat
, 0, i
);
3446 /* We have recognized nothing yet. */
3447 insn_code_number
= -1;
3449 /* See if this is a PARALLEL of two SETs where one SET's destination is
3450 a register that is unused and this isn't marked as an instruction that
3451 might trap in an EH region. In that case, we just need the other SET.
3452 We prefer this over the PARALLEL.
3454 This can occur when simplifying a divmod insn. We *must* test for this
3455 case here because the code below that splits two independent SETs doesn't
3456 handle this case correctly when it updates the register status.
3458 It's pointless doing this if we originally had two sets, one from
3459 i3, and one from i2. Combining then splitting the parallel results
3460 in the original i2 again plus an invalid insn (which we delete).
3461 The net effect is only to move instructions around, which makes
3462 debug info less accurate. */
3464 if (!(added_sets_2
&& i1
== 0)
3465 && is_parallel_of_n_reg_sets (newpat
, 2)
3466 && asm_noperands (newpat
) < 0)
3468 rtx set0
= XVECEXP (newpat
, 0, 0);
3469 rtx set1
= XVECEXP (newpat
, 0, 1);
3470 rtx oldpat
= newpat
;
3472 if (((REG_P (SET_DEST (set1
))
3473 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set1
)))
3474 || (GET_CODE (SET_DEST (set1
)) == SUBREG
3475 && find_reg_note (i3
, REG_UNUSED
, SUBREG_REG (SET_DEST (set1
)))))
3476 && insn_nothrow_p (i3
)
3477 && !side_effects_p (SET_SRC (set1
)))
3480 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3483 else if (((REG_P (SET_DEST (set0
))
3484 && find_reg_note (i3
, REG_UNUSED
, SET_DEST (set0
)))
3485 || (GET_CODE (SET_DEST (set0
)) == SUBREG
3486 && find_reg_note (i3
, REG_UNUSED
,
3487 SUBREG_REG (SET_DEST (set0
)))))
3488 && insn_nothrow_p (i3
)
3489 && !side_effects_p (SET_SRC (set0
)))
3492 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3494 if (insn_code_number
>= 0)
3495 changed_i3_dest
= 1;
3498 if (insn_code_number
< 0)
3502 /* Is the result of combination a valid instruction? */
3503 if (insn_code_number
< 0)
3504 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3506 /* If we were combining three insns and the result is a simple SET
3507 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3508 insns. There are two ways to do this. It can be split using a
3509 machine-specific method (like when you have an addition of a large
3510 constant) or by combine in the function find_split_point. */
3512 if (i1
&& insn_code_number
< 0 && GET_CODE (newpat
) == SET
3513 && asm_noperands (newpat
) < 0)
3515 rtx parallel
, *split
;
3516 rtx_insn
*m_split_insn
;
3518 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3519 use I2DEST as a scratch register will help. In the latter case,
3520 convert I2DEST to the mode of the source of NEWPAT if we can. */
3522 m_split_insn
= combine_split_insns (newpat
, i3
);
3524 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3525 inputs of NEWPAT. */
3527 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3528 possible to try that as a scratch reg. This would require adding
3529 more code to make it work though. */
3531 if (m_split_insn
== 0 && ! reg_overlap_mentioned_p (i2dest
, newpat
))
3533 machine_mode new_mode
= GET_MODE (SET_DEST (newpat
));
3535 /* First try to split using the original register as a
3536 scratch register. */
3537 parallel
= gen_rtx_PARALLEL (VOIDmode
,
3538 gen_rtvec (2, newpat
,
3539 gen_rtx_CLOBBER (VOIDmode
,
3541 m_split_insn
= combine_split_insns (parallel
, i3
);
3543 /* If that didn't work, try changing the mode of I2DEST if
3545 if (m_split_insn
== 0
3546 && new_mode
!= GET_MODE (i2dest
)
3547 && new_mode
!= VOIDmode
3548 && can_change_dest_mode (i2dest
, added_sets_2
, new_mode
))
3550 machine_mode old_mode
= GET_MODE (i2dest
);
3553 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3554 ni2dest
= gen_rtx_REG (new_mode
, REGNO (i2dest
));
3557 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], new_mode
);
3558 ni2dest
= regno_reg_rtx
[REGNO (i2dest
)];
3561 parallel
= (gen_rtx_PARALLEL
3563 gen_rtvec (2, newpat
,
3564 gen_rtx_CLOBBER (VOIDmode
,
3566 m_split_insn
= combine_split_insns (parallel
, i3
);
3568 if (m_split_insn
== 0
3569 && REGNO (i2dest
) >= FIRST_PSEUDO_REGISTER
)
3573 adjust_reg_mode (regno_reg_rtx
[REGNO (i2dest
)], old_mode
);
3574 buf
= undobuf
.undos
;
3575 undobuf
.undos
= buf
->next
;
3576 buf
->next
= undobuf
.frees
;
3577 undobuf
.frees
= buf
;
3581 i2scratch
= m_split_insn
!= 0;
3584 /* If recog_for_combine has discarded clobbers, try to use them
3585 again for the split. */
3586 if (m_split_insn
== 0 && newpat_vec_with_clobbers
)
3588 parallel
= gen_rtx_PARALLEL (VOIDmode
, newpat_vec_with_clobbers
);
3589 m_split_insn
= combine_split_insns (parallel
, i3
);
3592 if (m_split_insn
&& NEXT_INSN (m_split_insn
) == NULL_RTX
)
3594 rtx m_split_pat
= PATTERN (m_split_insn
);
3595 insn_code_number
= recog_for_combine (&m_split_pat
, i3
, &new_i3_notes
);
3596 if (insn_code_number
>= 0)
3597 newpat
= m_split_pat
;
3599 else if (m_split_insn
&& NEXT_INSN (NEXT_INSN (m_split_insn
)) == NULL_RTX
3600 && (next_nonnote_nondebug_insn (i2
) == i3
3601 || ! use_crosses_set_p (PATTERN (m_split_insn
), DF_INSN_LUID (i2
))))
3604 rtx newi3pat
= PATTERN (NEXT_INSN (m_split_insn
));
3605 newi2pat
= PATTERN (m_split_insn
);
3607 i3set
= single_set (NEXT_INSN (m_split_insn
));
3608 i2set
= single_set (m_split_insn
);
3610 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3612 /* If I2 or I3 has multiple SETs, we won't know how to track
3613 register status, so don't use these insns. If I2's destination
3614 is used between I2 and I3, we also can't use these insns. */
3616 if (i2_code_number
>= 0 && i2set
&& i3set
3617 && (next_nonnote_nondebug_insn (i2
) == i3
3618 || ! reg_used_between_p (SET_DEST (i2set
), i2
, i3
)))
3619 insn_code_number
= recog_for_combine (&newi3pat
, i3
,
3621 if (insn_code_number
>= 0)
3624 /* It is possible that both insns now set the destination of I3.
3625 If so, we must show an extra use of it. */
3627 if (insn_code_number
>= 0)
3629 rtx new_i3_dest
= SET_DEST (i3set
);
3630 rtx new_i2_dest
= SET_DEST (i2set
);
3632 while (GET_CODE (new_i3_dest
) == ZERO_EXTRACT
3633 || GET_CODE (new_i3_dest
) == STRICT_LOW_PART
3634 || GET_CODE (new_i3_dest
) == SUBREG
)
3635 new_i3_dest
= XEXP (new_i3_dest
, 0);
3637 while (GET_CODE (new_i2_dest
) == ZERO_EXTRACT
3638 || GET_CODE (new_i2_dest
) == STRICT_LOW_PART
3639 || GET_CODE (new_i2_dest
) == SUBREG
)
3640 new_i2_dest
= XEXP (new_i2_dest
, 0);
3642 if (REG_P (new_i3_dest
)
3643 && REG_P (new_i2_dest
)
3644 && REGNO (new_i3_dest
) == REGNO (new_i2_dest
)
3645 && REGNO (new_i2_dest
) < reg_n_sets_max
)
3646 INC_REG_N_SETS (REGNO (new_i2_dest
), 1);
3650 /* If we can split it and use I2DEST, go ahead and see if that
3651 helps things be recognized. Verify that none of the registers
3652 are set between I2 and I3. */
3653 if (insn_code_number
< 0
3654 && (split
= find_split_point (&newpat
, i3
, false)) != 0
3655 && (!HAVE_cc0
|| REG_P (i2dest
))
3656 /* We need I2DEST in the proper mode. If it is a hard register
3657 or the only use of a pseudo, we can change its mode.
3658 Make sure we don't change a hard register to have a mode that
3659 isn't valid for it, or change the number of registers. */
3660 && (GET_MODE (*split
) == GET_MODE (i2dest
)
3661 || GET_MODE (*split
) == VOIDmode
3662 || can_change_dest_mode (i2dest
, added_sets_2
,
3664 && (next_nonnote_nondebug_insn (i2
) == i3
3665 || ! use_crosses_set_p (*split
, DF_INSN_LUID (i2
)))
3666 /* We can't overwrite I2DEST if its value is still used by
3668 && ! reg_referenced_p (i2dest
, newpat
))
3670 rtx newdest
= i2dest
;
3671 enum rtx_code split_code
= GET_CODE (*split
);
3672 machine_mode split_mode
= GET_MODE (*split
);
3673 bool subst_done
= false;
3674 newi2pat
= NULL_RTX
;
3678 /* *SPLIT may be part of I2SRC, so make sure we have the
3679 original expression around for later debug processing.
3680 We should not need I2SRC any more in other cases. */
3681 if (MAY_HAVE_DEBUG_INSNS
)
3682 i2src
= copy_rtx (i2src
);
3686 /* Get NEWDEST as a register in the proper mode. We have already
3687 validated that we can do this. */
3688 if (GET_MODE (i2dest
) != split_mode
&& split_mode
!= VOIDmode
)
3690 if (REGNO (i2dest
) < FIRST_PSEUDO_REGISTER
)
3691 newdest
= gen_rtx_REG (split_mode
, REGNO (i2dest
));
3694 SUBST_MODE (regno_reg_rtx
[REGNO (i2dest
)], split_mode
);
3695 newdest
= regno_reg_rtx
[REGNO (i2dest
)];
3699 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3700 an ASHIFT. This can occur if it was inside a PLUS and hence
3701 appeared to be a memory address. This is a kludge. */
3702 if (split_code
== MULT
3703 && CONST_INT_P (XEXP (*split
, 1))
3704 && INTVAL (XEXP (*split
, 1)) > 0
3705 && (i
= exact_log2 (UINTVAL (XEXP (*split
, 1)))) >= 0)
3707 SUBST (*split
, gen_rtx_ASHIFT (split_mode
,
3708 XEXP (*split
, 0), GEN_INT (i
)));
3709 /* Update split_code because we may not have a multiply
3711 split_code
= GET_CODE (*split
);
3714 /* Similarly for (plus (mult FOO (const_int pow2))). */
3715 if (split_code
== PLUS
3716 && GET_CODE (XEXP (*split
, 0)) == MULT
3717 && CONST_INT_P (XEXP (XEXP (*split
, 0), 1))
3718 && INTVAL (XEXP (XEXP (*split
, 0), 1)) > 0
3719 && (i
= exact_log2 (UINTVAL (XEXP (XEXP (*split
, 0), 1)))) >= 0)
3721 rtx nsplit
= XEXP (*split
, 0);
3722 SUBST (XEXP (*split
, 0), gen_rtx_ASHIFT (GET_MODE (nsplit
),
3723 XEXP (nsplit
, 0), GEN_INT (i
)));
3724 /* Update split_code because we may not have a multiply
3726 split_code
= GET_CODE (*split
);
3729 #ifdef INSN_SCHEDULING
3730 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3731 be written as a ZERO_EXTEND. */
3732 if (split_code
== SUBREG
&& MEM_P (SUBREG_REG (*split
)))
3734 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3735 what it really is. */
3736 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split
)))
3738 SUBST (*split
, gen_rtx_SIGN_EXTEND (split_mode
,
3739 SUBREG_REG (*split
)));
3741 SUBST (*split
, gen_rtx_ZERO_EXTEND (split_mode
,
3742 SUBREG_REG (*split
)));
3746 /* Attempt to split binary operators using arithmetic identities. */
3747 if (BINARY_P (SET_SRC (newpat
))
3748 && split_mode
== GET_MODE (SET_SRC (newpat
))
3749 && ! side_effects_p (SET_SRC (newpat
)))
3751 rtx setsrc
= SET_SRC (newpat
);
3752 machine_mode mode
= GET_MODE (setsrc
);
3753 enum rtx_code code
= GET_CODE (setsrc
);
3754 rtx src_op0
= XEXP (setsrc
, 0);
3755 rtx src_op1
= XEXP (setsrc
, 1);
3757 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3758 if (rtx_equal_p (src_op0
, src_op1
))
3760 newi2pat
= gen_rtx_SET (newdest
, src_op0
);
3761 SUBST (XEXP (setsrc
, 0), newdest
);
3762 SUBST (XEXP (setsrc
, 1), newdest
);
3765 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3766 else if ((code
== PLUS
|| code
== MULT
)
3767 && GET_CODE (src_op0
) == code
3768 && GET_CODE (XEXP (src_op0
, 0)) == code
3769 && (INTEGRAL_MODE_P (mode
)
3770 || (FLOAT_MODE_P (mode
)
3771 && flag_unsafe_math_optimizations
)))
3773 rtx p
= XEXP (XEXP (src_op0
, 0), 0);
3774 rtx q
= XEXP (XEXP (src_op0
, 0), 1);
3775 rtx r
= XEXP (src_op0
, 1);
3778 /* Split both "((X op Y) op X) op Y" and
3779 "((X op Y) op Y) op X" as "T op T" where T is
3781 if ((rtx_equal_p (p
,r
) && rtx_equal_p (q
,s
))
3782 || (rtx_equal_p (p
,s
) && rtx_equal_p (q
,r
)))
3784 newi2pat
= gen_rtx_SET (newdest
, XEXP (src_op0
, 0));
3785 SUBST (XEXP (setsrc
, 0), newdest
);
3786 SUBST (XEXP (setsrc
, 1), newdest
);
3789 /* Split "((X op X) op Y) op Y)" as "T op T" where
3791 else if (rtx_equal_p (p
,q
) && rtx_equal_p (r
,s
))
3793 rtx tmp
= simplify_gen_binary (code
, mode
, p
, r
);
3794 newi2pat
= gen_rtx_SET (newdest
, tmp
);
3795 SUBST (XEXP (setsrc
, 0), newdest
);
3796 SUBST (XEXP (setsrc
, 1), newdest
);
3804 newi2pat
= gen_rtx_SET (newdest
, *split
);
3805 SUBST (*split
, newdest
);
3808 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3810 /* recog_for_combine might have added CLOBBERs to newi2pat.
3811 Make sure NEWPAT does not depend on the clobbered regs. */
3812 if (GET_CODE (newi2pat
) == PARALLEL
)
3813 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3814 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3816 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3817 if (reg_overlap_mentioned_p (reg
, newpat
))
3824 /* If the split point was a MULT and we didn't have one before,
3825 don't use one now. */
3826 if (i2_code_number
>= 0 && ! (split_code
== MULT
&& ! have_mult
))
3827 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3831 /* Check for a case where we loaded from memory in a narrow mode and
3832 then sign extended it, but we need both registers. In that case,
3833 we have a PARALLEL with both loads from the same memory location.
3834 We can split this into a load from memory followed by a register-register
3835 copy. This saves at least one insn, more if register allocation can
3838 We cannot do this if the destination of the first assignment is a
3839 condition code register or cc0. We eliminate this case by making sure
3840 the SET_DEST and SET_SRC have the same mode.
3842 We cannot do this if the destination of the second assignment is
3843 a register that we have already assumed is zero-extended. Similarly
3844 for a SUBREG of such a register. */
3846 else if (i1
&& insn_code_number
< 0 && asm_noperands (newpat
) < 0
3847 && GET_CODE (newpat
) == PARALLEL
3848 && XVECLEN (newpat
, 0) == 2
3849 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3850 && GET_CODE (SET_SRC (XVECEXP (newpat
, 0, 0))) == SIGN_EXTEND
3851 && (GET_MODE (SET_DEST (XVECEXP (newpat
, 0, 0)))
3852 == GET_MODE (SET_SRC (XVECEXP (newpat
, 0, 0))))
3853 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3854 && rtx_equal_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3855 XEXP (SET_SRC (XVECEXP (newpat
, 0, 0)), 0))
3856 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat
, 0, 1)),
3858 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3859 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3860 && ! (temp_expr
= SET_DEST (XVECEXP (newpat
, 0, 1)),
3862 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3863 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3864 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3865 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3866 != GET_MODE_MASK (word_mode
))))
3867 && ! (GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) == SUBREG
3868 && (temp_expr
= SUBREG_REG (SET_DEST (XVECEXP (newpat
, 0, 1))),
3870 && reg_stat
[REGNO (temp_expr
)].nonzero_bits
!= 0
3871 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < BITS_PER_WORD
3872 && GET_MODE_PRECISION (GET_MODE (temp_expr
)) < HOST_BITS_PER_INT
3873 && (reg_stat
[REGNO (temp_expr
)].nonzero_bits
3874 != GET_MODE_MASK (word_mode
)))))
3875 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3876 SET_SRC (XVECEXP (newpat
, 0, 1)))
3877 && ! find_reg_note (i3
, REG_UNUSED
,
3878 SET_DEST (XVECEXP (newpat
, 0, 0))))
3882 newi2pat
= XVECEXP (newpat
, 0, 0);
3883 ni2dest
= SET_DEST (XVECEXP (newpat
, 0, 0));
3884 newpat
= XVECEXP (newpat
, 0, 1);
3885 SUBST (SET_SRC (newpat
),
3886 gen_lowpart (GET_MODE (SET_SRC (newpat
)), ni2dest
));
3887 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3889 if (i2_code_number
>= 0)
3890 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3892 if (insn_code_number
>= 0)
3896 /* Similarly, check for a case where we have a PARALLEL of two independent
3897 SETs but we started with three insns. In this case, we can do the sets
3898 as two separate insns. This case occurs when some SET allows two
3899 other insns to combine, but the destination of that SET is still live.
3901 Also do this if we started with two insns and (at least) one of the
3902 resulting sets is a noop; this noop will be deleted later. */
3904 else if (insn_code_number
< 0 && asm_noperands (newpat
) < 0
3905 && GET_CODE (newpat
) == PARALLEL
3906 && XVECLEN (newpat
, 0) == 2
3907 && GET_CODE (XVECEXP (newpat
, 0, 0)) == SET
3908 && GET_CODE (XVECEXP (newpat
, 0, 1)) == SET
3909 && (i1
|| set_noop_p (XVECEXP (newpat
, 0, 0))
3910 || set_noop_p (XVECEXP (newpat
, 0, 1)))
3911 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != ZERO_EXTRACT
3912 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 0))) != STRICT_LOW_PART
3913 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != ZERO_EXTRACT
3914 && GET_CODE (SET_DEST (XVECEXP (newpat
, 0, 1))) != STRICT_LOW_PART
3915 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 1)),
3916 XVECEXP (newpat
, 0, 0))
3917 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat
, 0, 0)),
3918 XVECEXP (newpat
, 0, 1))
3919 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 0)))
3920 && contains_muldiv (SET_SRC (XVECEXP (newpat
, 0, 1)))))
3922 rtx set0
= XVECEXP (newpat
, 0, 0);
3923 rtx set1
= XVECEXP (newpat
, 0, 1);
3925 /* Normally, it doesn't matter which of the two is done first,
3926 but the one that references cc0 can't be the second, and
3927 one which uses any regs/memory set in between i2 and i3 can't
3928 be first. The PARALLEL might also have been pre-existing in i3,
3929 so we need to make sure that we won't wrongly hoist a SET to i2
3930 that would conflict with a death note present in there. */
3931 if (!use_crosses_set_p (SET_SRC (set1
), DF_INSN_LUID (i2
))
3932 && !(REG_P (SET_DEST (set1
))
3933 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set1
)))
3934 && !(GET_CODE (SET_DEST (set1
)) == SUBREG
3935 && find_reg_note (i2
, REG_DEAD
,
3936 SUBREG_REG (SET_DEST (set1
))))
3937 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set0
))
3938 /* If I3 is a jump, ensure that set0 is a jump so that
3939 we do not create invalid RTL. */
3940 && (!JUMP_P (i3
) || SET_DEST (set0
) == pc_rtx
)
3946 else if (!use_crosses_set_p (SET_SRC (set0
), DF_INSN_LUID (i2
))
3947 && !(REG_P (SET_DEST (set0
))
3948 && find_reg_note (i2
, REG_DEAD
, SET_DEST (set0
)))
3949 && !(GET_CODE (SET_DEST (set0
)) == SUBREG
3950 && find_reg_note (i2
, REG_DEAD
,
3951 SUBREG_REG (SET_DEST (set0
))))
3952 && (!HAVE_cc0
|| !reg_referenced_p (cc0_rtx
, set1
))
3953 /* If I3 is a jump, ensure that set1 is a jump so that
3954 we do not create invalid RTL. */
3955 && (!JUMP_P (i3
) || SET_DEST (set1
) == pc_rtx
)
3967 i2_code_number
= recog_for_combine (&newi2pat
, i2
, &new_i2_notes
);
3969 if (i2_code_number
>= 0)
3971 /* recog_for_combine might have added CLOBBERs to newi2pat.
3972 Make sure NEWPAT does not depend on the clobbered regs. */
3973 if (GET_CODE (newi2pat
) == PARALLEL
)
3975 for (i
= XVECLEN (newi2pat
, 0) - 1; i
>= 0; i
--)
3976 if (GET_CODE (XVECEXP (newi2pat
, 0, i
)) == CLOBBER
)
3978 rtx reg
= XEXP (XVECEXP (newi2pat
, 0, i
), 0);
3979 if (reg_overlap_mentioned_p (reg
, newpat
))
3987 insn_code_number
= recog_for_combine (&newpat
, i3
, &new_i3_notes
);
3991 /* If it still isn't recognized, fail and change things back the way they
3993 if ((insn_code_number
< 0
3994 /* Is the result a reasonable ASM_OPERANDS? */
3995 && (! check_asm_operands (newpat
) || added_sets_1
|| added_sets_2
)))
4001 /* If we had to change another insn, make sure it is valid also. */
4002 if (undobuf
.other_insn
)
4004 CLEAR_HARD_REG_SET (newpat_used_regs
);
4006 other_pat
= PATTERN (undobuf
.other_insn
);
4007 other_code_number
= recog_for_combine (&other_pat
, undobuf
.other_insn
,
4010 if (other_code_number
< 0 && ! check_asm_operands (other_pat
))
4017 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4018 they are adjacent to each other or not. */
4021 rtx_insn
*p
= prev_nonnote_insn (i3
);
4022 if (p
&& p
!= i2
&& NONJUMP_INSN_P (p
) && newi2pat
4023 && sets_cc0_p (newi2pat
))
4030 /* Only allow this combination if insn_rtx_costs reports that the
4031 replacement instructions are cheaper than the originals. */
4032 if (!combine_validate_cost (i0
, i1
, i2
, i3
, newpat
, newi2pat
, other_pat
))
4038 if (MAY_HAVE_DEBUG_INSNS
)
4042 for (undo
= undobuf
.undos
; undo
; undo
= undo
->next
)
4043 if (undo
->kind
== UNDO_MODE
)
4045 rtx reg
= *undo
->where
.r
;
4046 machine_mode new_mode
= GET_MODE (reg
);
4047 machine_mode old_mode
= undo
->old_contents
.m
;
4049 /* Temporarily revert mode back. */
4050 adjust_reg_mode (reg
, old_mode
);
4052 if (reg
== i2dest
&& i2scratch
)
4054 /* If we used i2dest as a scratch register with a
4055 different mode, substitute it for the original
4056 i2src while its original mode is temporarily
4057 restored, and then clear i2scratch so that we don't
4058 do it again later. */
4059 propagate_for_debug (i2
, last_combined_insn
, reg
, i2src
,
4062 /* Put back the new mode. */
4063 adjust_reg_mode (reg
, new_mode
);
4067 rtx tempreg
= gen_raw_REG (old_mode
, REGNO (reg
));
4068 rtx_insn
*first
, *last
;
4073 last
= last_combined_insn
;
4078 last
= undobuf
.other_insn
;
4080 if (DF_INSN_LUID (last
)
4081 < DF_INSN_LUID (last_combined_insn
))
4082 last
= last_combined_insn
;
4085 /* We're dealing with a reg that changed mode but not
4086 meaning, so we want to turn it into a subreg for
4087 the new mode. However, because of REG sharing and
4088 because its mode had already changed, we have to do
4089 it in two steps. First, replace any debug uses of
4090 reg, with its original mode temporarily restored,
4091 with this copy we have created; then, replace the
4092 copy with the SUBREG of the original shared reg,
4093 once again changed to the new mode. */
4094 propagate_for_debug (first
, last
, reg
, tempreg
,
4096 adjust_reg_mode (reg
, new_mode
);
4097 propagate_for_debug (first
, last
, tempreg
,
4098 lowpart_subreg (old_mode
, reg
, new_mode
),
4104 /* If we will be able to accept this, we have made a
4105 change to the destination of I3. This requires us to
4106 do a few adjustments. */
4108 if (changed_i3_dest
)
4110 PATTERN (i3
) = newpat
;
4111 adjust_for_new_dest (i3
);
4114 /* We now know that we can do this combination. Merge the insns and
4115 update the status of registers and LOG_LINKS. */
4117 if (undobuf
.other_insn
)
4121 PATTERN (undobuf
.other_insn
) = other_pat
;
4123 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4124 ensure that they are still valid. Then add any non-duplicate
4125 notes added by recog_for_combine. */
4126 for (note
= REG_NOTES (undobuf
.other_insn
); note
; note
= next
)
4128 next
= XEXP (note
, 1);
4130 if ((REG_NOTE_KIND (note
) == REG_DEAD
4131 && !reg_referenced_p (XEXP (note
, 0),
4132 PATTERN (undobuf
.other_insn
)))
4133 ||(REG_NOTE_KIND (note
) == REG_UNUSED
4134 && !reg_set_p (XEXP (note
, 0),
4135 PATTERN (undobuf
.other_insn
))))
4136 remove_note (undobuf
.other_insn
, note
);
4139 distribute_notes (new_other_notes
, undobuf
.other_insn
,
4140 undobuf
.other_insn
, NULL
, NULL_RTX
, NULL_RTX
,
4147 struct insn_link
*link
;
4150 /* I3 now uses what used to be its destination and which is now
4151 I2's destination. This requires us to do a few adjustments. */
4152 PATTERN (i3
) = newpat
;
4153 adjust_for_new_dest (i3
);
4155 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4158 However, some later insn might be using I2's dest and have
4159 a LOG_LINK pointing at I3. We must remove this link.
4160 The simplest way to remove the link is to point it at I1,
4161 which we know will be a NOTE. */
4163 /* newi2pat is usually a SET here; however, recog_for_combine might
4164 have added some clobbers. */
4165 if (GET_CODE (newi2pat
) == PARALLEL
)
4166 ni2dest
= SET_DEST (XVECEXP (newi2pat
, 0, 0));
4168 ni2dest
= SET_DEST (newi2pat
);
4170 for (insn
= NEXT_INSN (i3
);
4171 insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4172 || insn
!= BB_HEAD (this_basic_block
->next_bb
));
4173 insn
= NEXT_INSN (insn
))
4175 if (INSN_P (insn
) && reg_referenced_p (ni2dest
, PATTERN (insn
)))
4177 FOR_EACH_LOG_LINK (link
, insn
)
4178 if (link
->insn
== i3
)
4187 rtx i3notes
, i2notes
, i1notes
= 0, i0notes
= 0;
4188 struct insn_link
*i3links
, *i2links
, *i1links
= 0, *i0links
= 0;
4191 /* Compute which registers we expect to eliminate. newi2pat may be setting
4192 either i3dest or i2dest, so we must check it. */
4193 rtx elim_i2
= ((newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4194 || i2dest_in_i2src
|| i2dest_in_i1src
|| i2dest_in_i0src
4197 /* For i1, we need to compute both local elimination and global
4198 elimination information with respect to newi2pat because i1dest
4199 may be the same as i3dest, in which case newi2pat may be setting
4200 i1dest. Global information is used when distributing REG_DEAD
4201 note for i2 and i3, in which case it does matter if newi2pat sets
4204 Local information is used when distributing REG_DEAD note for i1,
4205 in which case it doesn't matter if newi2pat sets i1dest or not.
4206 See PR62151, if we have four insns combination:
4208 i1: r1 <- i1src (using r0)
4210 i2: r0 <- i2src (using r1)
4211 i3: r3 <- i3src (using r0)
4213 From i1's point of view, r0 is eliminated, no matter if it is set
4214 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4215 should be discarded.
4217 Note local information only affects cases in forms like "I1->I2->I3",
4218 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4219 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4221 rtx local_elim_i1
= (i1
== 0 || i1dest_in_i1src
|| i1dest_in_i0src
4224 rtx elim_i1
= (local_elim_i1
== 0
4225 || (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4227 /* Same case as i1. */
4228 rtx local_elim_i0
= (i0
== 0 || i0dest_in_i0src
|| !i0dest_killed
4230 rtx elim_i0
= (local_elim_i0
== 0
4231 || (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4234 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4236 i3notes
= REG_NOTES (i3
), i3links
= LOG_LINKS (i3
);
4237 i2notes
= REG_NOTES (i2
), i2links
= LOG_LINKS (i2
);
4239 i1notes
= REG_NOTES (i1
), i1links
= LOG_LINKS (i1
);
4241 i0notes
= REG_NOTES (i0
), i0links
= LOG_LINKS (i0
);
4243 /* Ensure that we do not have something that should not be shared but
4244 occurs multiple times in the new insns. Check this by first
4245 resetting all the `used' flags and then copying anything is shared. */
4247 reset_used_flags (i3notes
);
4248 reset_used_flags (i2notes
);
4249 reset_used_flags (i1notes
);
4250 reset_used_flags (i0notes
);
4251 reset_used_flags (newpat
);
4252 reset_used_flags (newi2pat
);
4253 if (undobuf
.other_insn
)
4254 reset_used_flags (PATTERN (undobuf
.other_insn
));
4256 i3notes
= copy_rtx_if_shared (i3notes
);
4257 i2notes
= copy_rtx_if_shared (i2notes
);
4258 i1notes
= copy_rtx_if_shared (i1notes
);
4259 i0notes
= copy_rtx_if_shared (i0notes
);
4260 newpat
= copy_rtx_if_shared (newpat
);
4261 newi2pat
= copy_rtx_if_shared (newi2pat
);
4262 if (undobuf
.other_insn
)
4263 reset_used_flags (PATTERN (undobuf
.other_insn
));
4265 INSN_CODE (i3
) = insn_code_number
;
4266 PATTERN (i3
) = newpat
;
4268 if (CALL_P (i3
) && CALL_INSN_FUNCTION_USAGE (i3
))
4270 rtx call_usage
= CALL_INSN_FUNCTION_USAGE (i3
);
4272 reset_used_flags (call_usage
);
4273 call_usage
= copy_rtx (call_usage
);
4277 /* I2SRC must still be meaningful at this point. Some splitting
4278 operations can invalidate I2SRC, but those operations do not
4281 replace_rtx (call_usage
, i2dest
, i2src
);
4285 replace_rtx (call_usage
, i1dest
, i1src
);
4287 replace_rtx (call_usage
, i0dest
, i0src
);
4289 CALL_INSN_FUNCTION_USAGE (i3
) = call_usage
;
4292 if (undobuf
.other_insn
)
4293 INSN_CODE (undobuf
.other_insn
) = other_code_number
;
4295 /* We had one special case above where I2 had more than one set and
4296 we replaced a destination of one of those sets with the destination
4297 of I3. In that case, we have to update LOG_LINKS of insns later
4298 in this basic block. Note that this (expensive) case is rare.
4300 Also, in this case, we must pretend that all REG_NOTEs for I2
4301 actually came from I3, so that REG_UNUSED notes from I2 will be
4302 properly handled. */
4304 if (i3_subst_into_i2
)
4306 for (i
= 0; i
< XVECLEN (PATTERN (i2
), 0); i
++)
4307 if ((GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == SET
4308 || GET_CODE (XVECEXP (PATTERN (i2
), 0, i
)) == CLOBBER
)
4309 && REG_P (SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)))
4310 && SET_DEST (XVECEXP (PATTERN (i2
), 0, i
)) != i2dest
4311 && ! find_reg_note (i2
, REG_UNUSED
,
4312 SET_DEST (XVECEXP (PATTERN (i2
), 0, i
))))
4313 for (temp_insn
= NEXT_INSN (i2
);
4315 && (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
4316 || BB_HEAD (this_basic_block
) != temp_insn
);
4317 temp_insn
= NEXT_INSN (temp_insn
))
4318 if (temp_insn
!= i3
&& INSN_P (temp_insn
))
4319 FOR_EACH_LOG_LINK (link
, temp_insn
)
4320 if (link
->insn
== i2
)
4326 while (XEXP (link
, 1))
4327 link
= XEXP (link
, 1);
4328 XEXP (link
, 1) = i2notes
;
4335 LOG_LINKS (i3
) = NULL
;
4337 LOG_LINKS (i2
) = NULL
;
4342 if (MAY_HAVE_DEBUG_INSNS
&& i2scratch
)
4343 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4345 INSN_CODE (i2
) = i2_code_number
;
4346 PATTERN (i2
) = newi2pat
;
4350 if (MAY_HAVE_DEBUG_INSNS
&& i2src
)
4351 propagate_for_debug (i2
, last_combined_insn
, i2dest
, i2src
,
4353 SET_INSN_DELETED (i2
);
4358 LOG_LINKS (i1
) = NULL
;
4360 if (MAY_HAVE_DEBUG_INSNS
)
4361 propagate_for_debug (i1
, last_combined_insn
, i1dest
, i1src
,
4363 SET_INSN_DELETED (i1
);
4368 LOG_LINKS (i0
) = NULL
;
4370 if (MAY_HAVE_DEBUG_INSNS
)
4371 propagate_for_debug (i0
, last_combined_insn
, i0dest
, i0src
,
4373 SET_INSN_DELETED (i0
);
4376 /* Get death notes for everything that is now used in either I3 or
4377 I2 and used to die in a previous insn. If we built two new
4378 patterns, move from I1 to I2 then I2 to I3 so that we get the
4379 proper movement on registers that I2 modifies. */
4382 from_luid
= DF_INSN_LUID (i0
);
4384 from_luid
= DF_INSN_LUID (i1
);
4386 from_luid
= DF_INSN_LUID (i2
);
4388 move_deaths (newi2pat
, NULL_RTX
, from_luid
, i2
, &midnotes
);
4389 move_deaths (newpat
, newi2pat
, from_luid
, i3
, &midnotes
);
4391 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4393 distribute_notes (i3notes
, i3
, i3
, newi2pat
? i2
: NULL
,
4394 elim_i2
, elim_i1
, elim_i0
);
4396 distribute_notes (i2notes
, i2
, i3
, newi2pat
? i2
: NULL
,
4397 elim_i2
, elim_i1
, elim_i0
);
4399 distribute_notes (i1notes
, i1
, i3
, newi2pat
? i2
: NULL
,
4400 elim_i2
, local_elim_i1
, local_elim_i0
);
4402 distribute_notes (i0notes
, i0
, i3
, newi2pat
? i2
: NULL
,
4403 elim_i2
, elim_i1
, local_elim_i0
);
4405 distribute_notes (midnotes
, NULL
, i3
, newi2pat
? i2
: NULL
,
4406 elim_i2
, elim_i1
, elim_i0
);
4408 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4409 know these are REG_UNUSED and want them to go to the desired insn,
4410 so we always pass it as i3. */
4412 if (newi2pat
&& new_i2_notes
)
4413 distribute_notes (new_i2_notes
, i2
, i2
, NULL
, NULL_RTX
, NULL_RTX
,
4417 distribute_notes (new_i3_notes
, i3
, i3
, NULL
, NULL_RTX
, NULL_RTX
,
4420 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4421 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4422 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4423 in that case, it might delete I2. Similarly for I2 and I1.
4424 Show an additional death due to the REG_DEAD note we make here. If
4425 we discard it in distribute_notes, we will decrement it again. */
4429 rtx new_note
= alloc_reg_note (REG_DEAD
, i3dest_killed
, NULL_RTX
);
4430 if (newi2pat
&& reg_set_p (i3dest_killed
, newi2pat
))
4431 distribute_notes (new_note
, NULL
, i2
, NULL
, elim_i2
,
4434 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4435 elim_i2
, elim_i1
, elim_i0
);
4438 if (i2dest_in_i2src
)
4440 rtx new_note
= alloc_reg_note (REG_DEAD
, i2dest
, NULL_RTX
);
4441 if (newi2pat
&& reg_set_p (i2dest
, newi2pat
))
4442 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4443 NULL_RTX
, NULL_RTX
);
4445 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4446 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4449 if (i1dest_in_i1src
)
4451 rtx new_note
= alloc_reg_note (REG_DEAD
, i1dest
, NULL_RTX
);
4452 if (newi2pat
&& reg_set_p (i1dest
, newi2pat
))
4453 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4454 NULL_RTX
, NULL_RTX
);
4456 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4457 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4460 if (i0dest_in_i0src
)
4462 rtx new_note
= alloc_reg_note (REG_DEAD
, i0dest
, NULL_RTX
);
4463 if (newi2pat
&& reg_set_p (i0dest
, newi2pat
))
4464 distribute_notes (new_note
, NULL
, i2
, NULL
, NULL_RTX
,
4465 NULL_RTX
, NULL_RTX
);
4467 distribute_notes (new_note
, NULL
, i3
, newi2pat
? i2
: NULL
,
4468 NULL_RTX
, NULL_RTX
, NULL_RTX
);
4471 distribute_links (i3links
);
4472 distribute_links (i2links
);
4473 distribute_links (i1links
);
4474 distribute_links (i0links
);
4478 struct insn_link
*link
;
4479 rtx_insn
*i2_insn
= 0;
4480 rtx i2_val
= 0, set
;
4482 /* The insn that used to set this register doesn't exist, and
4483 this life of the register may not exist either. See if one of
4484 I3's links points to an insn that sets I2DEST. If it does,
4485 that is now the last known value for I2DEST. If we don't update
4486 this and I2 set the register to a value that depended on its old
4487 contents, we will get confused. If this insn is used, thing
4488 will be set correctly in combine_instructions. */
4489 FOR_EACH_LOG_LINK (link
, i3
)
4490 if ((set
= single_set (link
->insn
)) != 0
4491 && rtx_equal_p (i2dest
, SET_DEST (set
)))
4492 i2_insn
= link
->insn
, i2_val
= SET_SRC (set
);
4494 record_value_for_reg (i2dest
, i2_insn
, i2_val
);
4496 /* If the reg formerly set in I2 died only once and that was in I3,
4497 zero its use count so it won't make `reload' do any work. */
4499 && (newi2pat
== 0 || ! reg_mentioned_p (i2dest
, newi2pat
))
4500 && ! i2dest_in_i2src
4501 && REGNO (i2dest
) < reg_n_sets_max
)
4502 INC_REG_N_SETS (REGNO (i2dest
), -1);
4505 if (i1
&& REG_P (i1dest
))
4507 struct insn_link
*link
;
4508 rtx_insn
*i1_insn
= 0;
4509 rtx i1_val
= 0, set
;
4511 FOR_EACH_LOG_LINK (link
, i3
)
4512 if ((set
= single_set (link
->insn
)) != 0
4513 && rtx_equal_p (i1dest
, SET_DEST (set
)))
4514 i1_insn
= link
->insn
, i1_val
= SET_SRC (set
);
4516 record_value_for_reg (i1dest
, i1_insn
, i1_val
);
4519 && ! i1dest_in_i1src
4520 && REGNO (i1dest
) < reg_n_sets_max
)
4521 INC_REG_N_SETS (REGNO (i1dest
), -1);
4524 if (i0
&& REG_P (i0dest
))
4526 struct insn_link
*link
;
4527 rtx_insn
*i0_insn
= 0;
4528 rtx i0_val
= 0, set
;
4530 FOR_EACH_LOG_LINK (link
, i3
)
4531 if ((set
= single_set (link
->insn
)) != 0
4532 && rtx_equal_p (i0dest
, SET_DEST (set
)))
4533 i0_insn
= link
->insn
, i0_val
= SET_SRC (set
);
4535 record_value_for_reg (i0dest
, i0_insn
, i0_val
);
4538 && ! i0dest_in_i0src
4539 && REGNO (i0dest
) < reg_n_sets_max
)
4540 INC_REG_N_SETS (REGNO (i0dest
), -1);
4543 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4544 been made to this insn. The order is important, because newi2pat
4545 can affect nonzero_bits of newpat. */
4547 note_stores (newi2pat
, set_nonzero_bits_and_sign_copies
, NULL
);
4548 note_stores (newpat
, set_nonzero_bits_and_sign_copies
, NULL
);
4551 if (undobuf
.other_insn
!= NULL_RTX
)
4555 fprintf (dump_file
, "modifying other_insn ");
4556 dump_insn_slim (dump_file
, undobuf
.other_insn
);
4558 df_insn_rescan (undobuf
.other_insn
);
4561 if (i0
&& !(NOTE_P (i0
) && (NOTE_KIND (i0
) == NOTE_INSN_DELETED
)))
4565 fprintf (dump_file
, "modifying insn i0 ");
4566 dump_insn_slim (dump_file
, i0
);
4568 df_insn_rescan (i0
);
4571 if (i1
&& !(NOTE_P (i1
) && (NOTE_KIND (i1
) == NOTE_INSN_DELETED
)))
4575 fprintf (dump_file
, "modifying insn i1 ");
4576 dump_insn_slim (dump_file
, i1
);
4578 df_insn_rescan (i1
);
4581 if (i2
&& !(NOTE_P (i2
) && (NOTE_KIND (i2
) == NOTE_INSN_DELETED
)))
4585 fprintf (dump_file
, "modifying insn i2 ");
4586 dump_insn_slim (dump_file
, i2
);
4588 df_insn_rescan (i2
);
4591 if (i3
&& !(NOTE_P (i3
) && (NOTE_KIND (i3
) == NOTE_INSN_DELETED
)))
4595 fprintf (dump_file
, "modifying insn i3 ");
4596 dump_insn_slim (dump_file
, i3
);
4598 df_insn_rescan (i3
);
4601 /* Set new_direct_jump_p if a new return or simple jump instruction
4602 has been created. Adjust the CFG accordingly. */
4603 if (returnjump_p (i3
) || any_uncondjump_p (i3
))
4605 *new_direct_jump_p
= 1;
4606 mark_jump_label (PATTERN (i3
), i3
, 0);
4607 update_cfg_for_uncondjump (i3
);
4610 if (undobuf
.other_insn
!= NULL_RTX
4611 && (returnjump_p (undobuf
.other_insn
)
4612 || any_uncondjump_p (undobuf
.other_insn
)))
4614 *new_direct_jump_p
= 1;
4615 update_cfg_for_uncondjump (undobuf
.other_insn
);
4618 /* A noop might also need cleaning up of CFG, if it comes from the
4619 simplification of a jump. */
4621 && GET_CODE (newpat
) == SET
4622 && SET_SRC (newpat
) == pc_rtx
4623 && SET_DEST (newpat
) == pc_rtx
)
4625 *new_direct_jump_p
= 1;
4626 update_cfg_for_uncondjump (i3
);
4629 if (undobuf
.other_insn
!= NULL_RTX
4630 && JUMP_P (undobuf
.other_insn
)
4631 && GET_CODE (PATTERN (undobuf
.other_insn
)) == SET
4632 && SET_SRC (PATTERN (undobuf
.other_insn
)) == pc_rtx
4633 && SET_DEST (PATTERN (undobuf
.other_insn
)) == pc_rtx
)
4635 *new_direct_jump_p
= 1;
4636 update_cfg_for_uncondjump (undobuf
.other_insn
);
4639 combine_successes
++;
4642 if (added_links_insn
4643 && (newi2pat
== 0 || DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i2
))
4644 && DF_INSN_LUID (added_links_insn
) < DF_INSN_LUID (i3
))
4645 return added_links_insn
;
4647 return newi2pat
? i2
: i3
;
4650 /* Get a marker for undoing to the current state. */
4653 get_undo_marker (void)
4655 return undobuf
.undos
;
4658 /* Undo the modifications up to the marker. */
4661 undo_to_marker (void *marker
)
4663 struct undo
*undo
, *next
;
4665 for (undo
= undobuf
.undos
; undo
!= marker
; undo
= next
)
4673 *undo
->where
.r
= undo
->old_contents
.r
;
4676 *undo
->where
.i
= undo
->old_contents
.i
;
4679 adjust_reg_mode (*undo
->where
.r
, undo
->old_contents
.m
);
4682 *undo
->where
.l
= undo
->old_contents
.l
;
4688 undo
->next
= undobuf
.frees
;
4689 undobuf
.frees
= undo
;
4692 undobuf
.undos
= (struct undo
*) marker
;
4695 /* Undo all the modifications recorded in undobuf. */
4703 /* We've committed to accepting the changes we made. Move all
4704 of the undos to the free list. */
4709 struct undo
*undo
, *next
;
4711 for (undo
= undobuf
.undos
; undo
; undo
= next
)
4714 undo
->next
= undobuf
.frees
;
4715 undobuf
.frees
= undo
;
4720 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4721 where we have an arithmetic expression and return that point. LOC will
4724 try_combine will call this function to see if an insn can be split into
4728 find_split_point (rtx
*loc
, rtx_insn
*insn
, bool set_src
)
4731 enum rtx_code code
= GET_CODE (x
);
4733 unsigned HOST_WIDE_INT len
= 0;
4734 HOST_WIDE_INT pos
= 0;
4736 rtx inner
= NULL_RTX
;
4738 /* First special-case some codes. */
4742 #ifdef INSN_SCHEDULING
4743 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4745 if (MEM_P (SUBREG_REG (x
)))
4748 return find_split_point (&SUBREG_REG (x
), insn
, false);
4751 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4752 using LO_SUM and HIGH. */
4753 if (HAVE_lo_sum
&& (GET_CODE (XEXP (x
, 0)) == CONST
4754 || GET_CODE (XEXP (x
, 0)) == SYMBOL_REF
))
4756 machine_mode address_mode
= get_address_mode (x
);
4759 gen_rtx_LO_SUM (address_mode
,
4760 gen_rtx_HIGH (address_mode
, XEXP (x
, 0)),
4762 return &XEXP (XEXP (x
, 0), 0);
4765 /* If we have a PLUS whose second operand is a constant and the
4766 address is not valid, perhaps will can split it up using
4767 the machine-specific way to split large constants. We use
4768 the first pseudo-reg (one of the virtual regs) as a placeholder;
4769 it will not remain in the result. */
4770 if (GET_CODE (XEXP (x
, 0)) == PLUS
4771 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
4772 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4773 MEM_ADDR_SPACE (x
)))
4775 rtx reg
= regno_reg_rtx
[FIRST_PSEUDO_REGISTER
];
4776 rtx_insn
*seq
= combine_split_insns (gen_rtx_SET (reg
, XEXP (x
, 0)),
4779 /* This should have produced two insns, each of which sets our
4780 placeholder. If the source of the second is a valid address,
4781 we can make put both sources together and make a split point
4785 && NEXT_INSN (seq
) != NULL_RTX
4786 && NEXT_INSN (NEXT_INSN (seq
)) == NULL_RTX
4787 && NONJUMP_INSN_P (seq
)
4788 && GET_CODE (PATTERN (seq
)) == SET
4789 && SET_DEST (PATTERN (seq
)) == reg
4790 && ! reg_mentioned_p (reg
,
4791 SET_SRC (PATTERN (seq
)))
4792 && NONJUMP_INSN_P (NEXT_INSN (seq
))
4793 && GET_CODE (PATTERN (NEXT_INSN (seq
))) == SET
4794 && SET_DEST (PATTERN (NEXT_INSN (seq
))) == reg
4795 && memory_address_addr_space_p
4796 (GET_MODE (x
), SET_SRC (PATTERN (NEXT_INSN (seq
))),
4797 MEM_ADDR_SPACE (x
)))
4799 rtx src1
= SET_SRC (PATTERN (seq
));
4800 rtx src2
= SET_SRC (PATTERN (NEXT_INSN (seq
)));
4802 /* Replace the placeholder in SRC2 with SRC1. If we can
4803 find where in SRC2 it was placed, that can become our
4804 split point and we can replace this address with SRC2.
4805 Just try two obvious places. */
4807 src2
= replace_rtx (src2
, reg
, src1
);
4809 if (XEXP (src2
, 0) == src1
)
4810 split
= &XEXP (src2
, 0);
4811 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2
, 0)))[0] == 'e'
4812 && XEXP (XEXP (src2
, 0), 0) == src1
)
4813 split
= &XEXP (XEXP (src2
, 0), 0);
4817 SUBST (XEXP (x
, 0), src2
);
4822 /* If that didn't work, perhaps the first operand is complex and
4823 needs to be computed separately, so make a split point there.
4824 This will occur on machines that just support REG + CONST
4825 and have a constant moved through some previous computation. */
4827 else if (!OBJECT_P (XEXP (XEXP (x
, 0), 0))
4828 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4829 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4830 return &XEXP (XEXP (x
, 0), 0);
4833 /* If we have a PLUS whose first operand is complex, try computing it
4834 separately by making a split there. */
4835 if (GET_CODE (XEXP (x
, 0)) == PLUS
4836 && ! memory_address_addr_space_p (GET_MODE (x
), XEXP (x
, 0),
4838 && ! OBJECT_P (XEXP (XEXP (x
, 0), 0))
4839 && ! (GET_CODE (XEXP (XEXP (x
, 0), 0)) == SUBREG
4840 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x
, 0), 0)))))
4841 return &XEXP (XEXP (x
, 0), 0);
4845 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4846 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4847 we need to put the operand into a register. So split at that
4850 if (SET_DEST (x
) == cc0_rtx
4851 && GET_CODE (SET_SRC (x
)) != COMPARE
4852 && GET_CODE (SET_SRC (x
)) != ZERO_EXTRACT
4853 && !OBJECT_P (SET_SRC (x
))
4854 && ! (GET_CODE (SET_SRC (x
)) == SUBREG
4855 && OBJECT_P (SUBREG_REG (SET_SRC (x
)))))
4856 return &SET_SRC (x
);
4858 /* See if we can split SET_SRC as it stands. */
4859 split
= find_split_point (&SET_SRC (x
), insn
, true);
4860 if (split
&& split
!= &SET_SRC (x
))
4863 /* See if we can split SET_DEST as it stands. */
4864 split
= find_split_point (&SET_DEST (x
), insn
, false);
4865 if (split
&& split
!= &SET_DEST (x
))
4868 /* See if this is a bitfield assignment with everything constant. If
4869 so, this is an IOR of an AND, so split it into that. */
4870 if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
4871 && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x
), 0)))
4872 && CONST_INT_P (XEXP (SET_DEST (x
), 1))
4873 && CONST_INT_P (XEXP (SET_DEST (x
), 2))
4874 && CONST_INT_P (SET_SRC (x
))
4875 && ((INTVAL (XEXP (SET_DEST (x
), 1))
4876 + INTVAL (XEXP (SET_DEST (x
), 2)))
4877 <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0))))
4878 && ! side_effects_p (XEXP (SET_DEST (x
), 0)))
4880 HOST_WIDE_INT pos
= INTVAL (XEXP (SET_DEST (x
), 2));
4881 unsigned HOST_WIDE_INT len
= INTVAL (XEXP (SET_DEST (x
), 1));
4882 unsigned HOST_WIDE_INT src
= INTVAL (SET_SRC (x
));
4883 rtx dest
= XEXP (SET_DEST (x
), 0);
4884 machine_mode mode
= GET_MODE (dest
);
4885 unsigned HOST_WIDE_INT mask
4886 = (HOST_WIDE_INT_1U
<< len
) - 1;
4889 if (BITS_BIG_ENDIAN
)
4890 pos
= GET_MODE_PRECISION (mode
) - len
- pos
;
4892 or_mask
= gen_int_mode (src
<< pos
, mode
);
4895 simplify_gen_binary (IOR
, mode
, dest
, or_mask
));
4898 rtx negmask
= gen_int_mode (~(mask
<< pos
), mode
);
4900 simplify_gen_binary (IOR
, mode
,
4901 simplify_gen_binary (AND
, mode
,
4906 SUBST (SET_DEST (x
), dest
);
4908 split
= find_split_point (&SET_SRC (x
), insn
, true);
4909 if (split
&& split
!= &SET_SRC (x
))
4913 /* Otherwise, see if this is an operation that we can split into two.
4914 If so, try to split that. */
4915 code
= GET_CODE (SET_SRC (x
));
4920 /* If we are AND'ing with a large constant that is only a single
4921 bit and the result is only being used in a context where we
4922 need to know if it is zero or nonzero, replace it with a bit
4923 extraction. This will avoid the large constant, which might
4924 have taken more than one insn to make. If the constant were
4925 not a valid argument to the AND but took only one insn to make,
4926 this is no worse, but if it took more than one insn, it will
4929 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4930 && REG_P (XEXP (SET_SRC (x
), 0))
4931 && (pos
= exact_log2 (UINTVAL (XEXP (SET_SRC (x
), 1)))) >= 7
4932 && REG_P (SET_DEST (x
))
4933 && (split
= find_single_use (SET_DEST (x
), insn
, NULL
)) != 0
4934 && (GET_CODE (*split
) == EQ
|| GET_CODE (*split
) == NE
)
4935 && XEXP (*split
, 0) == SET_DEST (x
)
4936 && XEXP (*split
, 1) == const0_rtx
)
4938 rtx extraction
= make_extraction (GET_MODE (SET_DEST (x
)),
4939 XEXP (SET_SRC (x
), 0),
4940 pos
, NULL_RTX
, 1, 1, 0, 0);
4941 if (extraction
!= 0)
4943 SUBST (SET_SRC (x
), extraction
);
4944 return find_split_point (loc
, insn
, false);
4950 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4951 is known to be on, this can be converted into a NEG of a shift. */
4952 if (STORE_FLAG_VALUE
== -1 && XEXP (SET_SRC (x
), 1) == const0_rtx
4953 && GET_MODE (SET_SRC (x
)) == GET_MODE (XEXP (SET_SRC (x
), 0))
4954 && 1 <= (pos
= exact_log2
4955 (nonzero_bits (XEXP (SET_SRC (x
), 0),
4956 GET_MODE (XEXP (SET_SRC (x
), 0))))))
4958 machine_mode mode
= GET_MODE (XEXP (SET_SRC (x
), 0));
4962 gen_rtx_LSHIFTRT (mode
,
4963 XEXP (SET_SRC (x
), 0),
4966 split
= find_split_point (&SET_SRC (x
), insn
, true);
4967 if (split
&& split
!= &SET_SRC (x
))
4973 inner
= XEXP (SET_SRC (x
), 0);
4975 /* We can't optimize if either mode is a partial integer
4976 mode as we don't know how many bits are significant
4978 if (GET_MODE_CLASS (GET_MODE (inner
)) == MODE_PARTIAL_INT
4979 || GET_MODE_CLASS (GET_MODE (SET_SRC (x
))) == MODE_PARTIAL_INT
)
4983 len
= GET_MODE_PRECISION (GET_MODE (inner
));
4989 if (CONST_INT_P (XEXP (SET_SRC (x
), 1))
4990 && CONST_INT_P (XEXP (SET_SRC (x
), 2)))
4992 inner
= XEXP (SET_SRC (x
), 0);
4993 len
= INTVAL (XEXP (SET_SRC (x
), 1));
4994 pos
= INTVAL (XEXP (SET_SRC (x
), 2));
4996 if (BITS_BIG_ENDIAN
)
4997 pos
= GET_MODE_PRECISION (GET_MODE (inner
)) - len
- pos
;
4998 unsignedp
= (code
== ZERO_EXTRACT
);
5007 && pos
+ len
<= GET_MODE_PRECISION (GET_MODE (inner
)))
5009 machine_mode mode
= GET_MODE (SET_SRC (x
));
5011 /* For unsigned, we have a choice of a shift followed by an
5012 AND or two shifts. Use two shifts for field sizes where the
5013 constant might be too large. We assume here that we can
5014 always at least get 8-bit constants in an AND insn, which is
5015 true for every current RISC. */
5017 if (unsignedp
&& len
<= 8)
5019 unsigned HOST_WIDE_INT mask
5020 = (HOST_WIDE_INT_1U
<< len
) - 1;
5024 (mode
, gen_lowpart (mode
, inner
),
5026 gen_int_mode (mask
, mode
)));
5028 split
= find_split_point (&SET_SRC (x
), insn
, true);
5029 if (split
&& split
!= &SET_SRC (x
))
5036 (unsignedp
? LSHIFTRT
: ASHIFTRT
, mode
,
5037 gen_rtx_ASHIFT (mode
,
5038 gen_lowpart (mode
, inner
),
5039 GEN_INT (GET_MODE_PRECISION (mode
)
5041 GEN_INT (GET_MODE_PRECISION (mode
) - len
)));
5043 split
= find_split_point (&SET_SRC (x
), insn
, true);
5044 if (split
&& split
!= &SET_SRC (x
))
5049 /* See if this is a simple operation with a constant as the second
5050 operand. It might be that this constant is out of range and hence
5051 could be used as a split point. */
5052 if (BINARY_P (SET_SRC (x
))
5053 && CONSTANT_P (XEXP (SET_SRC (x
), 1))
5054 && (OBJECT_P (XEXP (SET_SRC (x
), 0))
5055 || (GET_CODE (XEXP (SET_SRC (x
), 0)) == SUBREG
5056 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x
), 0))))))
5057 return &XEXP (SET_SRC (x
), 1);
5059 /* Finally, see if this is a simple operation with its first operand
5060 not in a register. The operation might require this operand in a
5061 register, so return it as a split point. We can always do this
5062 because if the first operand were another operation, we would have
5063 already found it as a split point. */
5064 if ((BINARY_P (SET_SRC (x
)) || UNARY_P (SET_SRC (x
)))
5065 && ! register_operand (XEXP (SET_SRC (x
), 0), VOIDmode
))
5066 return &XEXP (SET_SRC (x
), 0);
5072 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5073 it is better to write this as (not (ior A B)) so we can split it.
5074 Similarly for IOR. */
5075 if (GET_CODE (XEXP (x
, 0)) == NOT
&& GET_CODE (XEXP (x
, 1)) == NOT
)
5078 gen_rtx_NOT (GET_MODE (x
),
5079 gen_rtx_fmt_ee (code
== IOR
? AND
: IOR
,
5081 XEXP (XEXP (x
, 0), 0),
5082 XEXP (XEXP (x
, 1), 0))));
5083 return find_split_point (loc
, insn
, set_src
);
5086 /* Many RISC machines have a large set of logical insns. If the
5087 second operand is a NOT, put it first so we will try to split the
5088 other operand first. */
5089 if (GET_CODE (XEXP (x
, 1)) == NOT
)
5091 rtx tem
= XEXP (x
, 0);
5092 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5093 SUBST (XEXP (x
, 1), tem
);
5099 /* Canonicalization can produce (minus A (mult B C)), where C is a
5100 constant. It may be better to try splitting (plus (mult B -C) A)
5101 instead if this isn't a multiply by a power of two. */
5102 if (set_src
&& code
== MINUS
&& GET_CODE (XEXP (x
, 1)) == MULT
5103 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
5104 && !pow2p_hwi (INTVAL (XEXP (XEXP (x
, 1), 1))))
5106 machine_mode mode
= GET_MODE (x
);
5107 unsigned HOST_WIDE_INT this_int
= INTVAL (XEXP (XEXP (x
, 1), 1));
5108 HOST_WIDE_INT other_int
= trunc_int_for_mode (-this_int
, mode
);
5109 SUBST (*loc
, gen_rtx_PLUS (mode
,
5111 XEXP (XEXP (x
, 1), 0),
5112 gen_int_mode (other_int
,
5115 return find_split_point (loc
, insn
, set_src
);
5118 /* Split at a multiply-accumulate instruction. However if this is
5119 the SET_SRC, we likely do not have such an instruction and it's
5120 worthless to try this split. */
5122 && (GET_CODE (XEXP (x
, 0)) == MULT
5123 || (GET_CODE (XEXP (x
, 0)) == ASHIFT
5124 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
)))
5131 /* Otherwise, select our actions depending on our rtx class. */
5132 switch (GET_RTX_CLASS (code
))
5134 case RTX_BITFIELD_OPS
: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5136 split
= find_split_point (&XEXP (x
, 2), insn
, false);
5141 case RTX_COMM_ARITH
:
5143 case RTX_COMM_COMPARE
:
5144 split
= find_split_point (&XEXP (x
, 1), insn
, false);
5149 /* Some machines have (and (shift ...) ...) insns. If X is not
5150 an AND, but XEXP (X, 0) is, use it as our split point. */
5151 if (GET_CODE (x
) != AND
&& GET_CODE (XEXP (x
, 0)) == AND
)
5152 return &XEXP (x
, 0);
5154 split
= find_split_point (&XEXP (x
, 0), insn
, false);
5160 /* Otherwise, we don't have a split point. */
5165 /* Throughout X, replace FROM with TO, and return the result.
5166 The result is TO if X is FROM;
5167 otherwise the result is X, but its contents may have been modified.
5168 If they were modified, a record was made in undobuf so that
5169 undo_all will (among other things) return X to its original state.
5171 If the number of changes necessary is too much to record to undo,
5172 the excess changes are not made, so the result is invalid.
5173 The changes already made can still be undone.
5174 undobuf.num_undo is incremented for such changes, so by testing that
5175 the caller can tell whether the result is valid.
5177 `n_occurrences' is incremented each time FROM is replaced.
5179 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5181 IN_COND is nonzero if we are at the top level of a condition.
5183 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5184 by copying if `n_occurrences' is nonzero. */
5187 subst (rtx x
, rtx from
, rtx to
, int in_dest
, int in_cond
, int unique_copy
)
5189 enum rtx_code code
= GET_CODE (x
);
5190 machine_mode op0_mode
= VOIDmode
;
5195 /* Two expressions are equal if they are identical copies of a shared
5196 RTX or if they are both registers with the same register number
5199 #define COMBINE_RTX_EQUAL_P(X,Y) \
5201 || (REG_P (X) && REG_P (Y) \
5202 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5204 /* Do not substitute into clobbers of regs -- this will never result in
5206 if (GET_CODE (x
) == CLOBBER
&& REG_P (XEXP (x
, 0)))
5209 if (! in_dest
&& COMBINE_RTX_EQUAL_P (x
, from
))
5212 return (unique_copy
&& n_occurrences
> 1 ? copy_rtx (to
) : to
);
5215 /* If X and FROM are the same register but different modes, they
5216 will not have been seen as equal above. However, the log links code
5217 will make a LOG_LINKS entry for that case. If we do nothing, we
5218 will try to rerecognize our original insn and, when it succeeds,
5219 we will delete the feeding insn, which is incorrect.
5221 So force this insn not to match in this (rare) case. */
5222 if (! in_dest
&& code
== REG
&& REG_P (from
)
5223 && reg_overlap_mentioned_p (x
, from
))
5224 return gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
5226 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5227 of which may contain things that can be combined. */
5228 if (code
!= MEM
&& code
!= LO_SUM
&& OBJECT_P (x
))
5231 /* It is possible to have a subexpression appear twice in the insn.
5232 Suppose that FROM is a register that appears within TO.
5233 Then, after that subexpression has been scanned once by `subst',
5234 the second time it is scanned, TO may be found. If we were
5235 to scan TO here, we would find FROM within it and create a
5236 self-referent rtl structure which is completely wrong. */
5237 if (COMBINE_RTX_EQUAL_P (x
, to
))
5240 /* Parallel asm_operands need special attention because all of the
5241 inputs are shared across the arms. Furthermore, unsharing the
5242 rtl results in recognition failures. Failure to handle this case
5243 specially can result in circular rtl.
5245 Solve this by doing a normal pass across the first entry of the
5246 parallel, and only processing the SET_DESTs of the subsequent
5249 if (code
== PARALLEL
5250 && GET_CODE (XVECEXP (x
, 0, 0)) == SET
5251 && GET_CODE (SET_SRC (XVECEXP (x
, 0, 0))) == ASM_OPERANDS
)
5253 new_rtx
= subst (XVECEXP (x
, 0, 0), from
, to
, 0, 0, unique_copy
);
5255 /* If this substitution failed, this whole thing fails. */
5256 if (GET_CODE (new_rtx
) == CLOBBER
5257 && XEXP (new_rtx
, 0) == const0_rtx
)
5260 SUBST (XVECEXP (x
, 0, 0), new_rtx
);
5262 for (i
= XVECLEN (x
, 0) - 1; i
>= 1; i
--)
5264 rtx dest
= SET_DEST (XVECEXP (x
, 0, i
));
5267 && GET_CODE (dest
) != CC0
5268 && GET_CODE (dest
) != PC
)
5270 new_rtx
= subst (dest
, from
, to
, 0, 0, unique_copy
);
5272 /* If this substitution failed, this whole thing fails. */
5273 if (GET_CODE (new_rtx
) == CLOBBER
5274 && XEXP (new_rtx
, 0) == const0_rtx
)
5277 SUBST (SET_DEST (XVECEXP (x
, 0, i
)), new_rtx
);
5283 len
= GET_RTX_LENGTH (code
);
5284 fmt
= GET_RTX_FORMAT (code
);
5286 /* We don't need to process a SET_DEST that is a register, CC0,
5287 or PC, so set up to skip this common case. All other cases
5288 where we want to suppress replacing something inside a
5289 SET_SRC are handled via the IN_DEST operand. */
5291 && (REG_P (SET_DEST (x
))
5292 || GET_CODE (SET_DEST (x
)) == CC0
5293 || GET_CODE (SET_DEST (x
)) == PC
))
5296 /* Trying to simplify the operands of a widening MULT is not likely
5297 to create RTL matching a machine insn. */
5299 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
5300 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
5301 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
5302 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
5303 && REG_P (XEXP (XEXP (x
, 0), 0))
5304 && REG_P (XEXP (XEXP (x
, 1), 0))
5309 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5312 op0_mode
= GET_MODE (XEXP (x
, 0));
5314 for (i
= 0; i
< len
; i
++)
5319 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
5321 if (COMBINE_RTX_EQUAL_P (XVECEXP (x
, i
, j
), from
))
5323 new_rtx
= (unique_copy
&& n_occurrences
5324 ? copy_rtx (to
) : to
);
5329 new_rtx
= subst (XVECEXP (x
, i
, j
), from
, to
, 0, 0,
5332 /* If this substitution failed, this whole thing
5334 if (GET_CODE (new_rtx
) == CLOBBER
5335 && XEXP (new_rtx
, 0) == const0_rtx
)
5339 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
5342 else if (fmt
[i
] == 'e')
5344 /* If this is a register being set, ignore it. */
5345 new_rtx
= XEXP (x
, i
);
5348 && (((code
== SUBREG
|| code
== ZERO_EXTRACT
)
5350 || code
== STRICT_LOW_PART
))
5353 else if (COMBINE_RTX_EQUAL_P (XEXP (x
, i
), from
))
5355 /* In general, don't install a subreg involving two
5356 modes not tieable. It can worsen register
5357 allocation, and can even make invalid reload
5358 insns, since the reg inside may need to be copied
5359 from in the outside mode, and that may be invalid
5360 if it is an fp reg copied in integer mode.
5362 We allow two exceptions to this: It is valid if
5363 it is inside another SUBREG and the mode of that
5364 SUBREG and the mode of the inside of TO is
5365 tieable and it is valid if X is a SET that copies
5368 if (GET_CODE (to
) == SUBREG
5369 && ! MODES_TIEABLE_P (GET_MODE (to
),
5370 GET_MODE (SUBREG_REG (to
)))
5371 && ! (code
== SUBREG
5372 && MODES_TIEABLE_P (GET_MODE (x
),
5373 GET_MODE (SUBREG_REG (to
))))
5377 && XEXP (x
, 0) == cc0_rtx
))))
5378 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5382 && REGNO (to
) < FIRST_PSEUDO_REGISTER
5383 && simplify_subreg_regno (REGNO (to
), GET_MODE (to
),
5386 return gen_rtx_CLOBBER (VOIDmode
, const0_rtx
);
5388 new_rtx
= (unique_copy
&& n_occurrences
? copy_rtx (to
) : to
);
5392 /* If we are in a SET_DEST, suppress most cases unless we
5393 have gone inside a MEM, in which case we want to
5394 simplify the address. We assume here that things that
5395 are actually part of the destination have their inner
5396 parts in the first expression. This is true for SUBREG,
5397 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5398 things aside from REG and MEM that should appear in a
5400 new_rtx
= subst (XEXP (x
, i
), from
, to
,
5402 && (code
== SUBREG
|| code
== STRICT_LOW_PART
5403 || code
== ZERO_EXTRACT
))
5406 code
== IF_THEN_ELSE
&& i
== 0,
5409 /* If we found that we will have to reject this combination,
5410 indicate that by returning the CLOBBER ourselves, rather than
5411 an expression containing it. This will speed things up as
5412 well as prevent accidents where two CLOBBERs are considered
5413 to be equal, thus producing an incorrect simplification. */
5415 if (GET_CODE (new_rtx
) == CLOBBER
&& XEXP (new_rtx
, 0) == const0_rtx
)
5418 if (GET_CODE (x
) == SUBREG
&& CONST_SCALAR_INT_P (new_rtx
))
5420 machine_mode mode
= GET_MODE (x
);
5422 x
= simplify_subreg (GET_MODE (x
), new_rtx
,
5423 GET_MODE (SUBREG_REG (x
)),
5426 x
= gen_rtx_CLOBBER (mode
, const0_rtx
);
5428 else if (CONST_SCALAR_INT_P (new_rtx
)
5429 && GET_CODE (x
) == ZERO_EXTEND
)
5431 x
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
5432 new_rtx
, GET_MODE (XEXP (x
, 0)));
5436 SUBST (XEXP (x
, i
), new_rtx
);
5441 /* Check if we are loading something from the constant pool via float
5442 extension; in this case we would undo compress_float_constant
5443 optimization and degenerate constant load to an immediate value. */
5444 if (GET_CODE (x
) == FLOAT_EXTEND
5445 && MEM_P (XEXP (x
, 0))
5446 && MEM_READONLY_P (XEXP (x
, 0)))
5448 rtx tmp
= avoid_constant_pool_reference (x
);
5453 /* Try to simplify X. If the simplification changed the code, it is likely
5454 that further simplification will help, so loop, but limit the number
5455 of repetitions that will be performed. */
5457 for (i
= 0; i
< 4; i
++)
5459 /* If X is sufficiently simple, don't bother trying to do anything
5461 if (code
!= CONST_INT
&& code
!= REG
&& code
!= CLOBBER
)
5462 x
= combine_simplify_rtx (x
, op0_mode
, in_dest
, in_cond
);
5464 if (GET_CODE (x
) == code
)
5467 code
= GET_CODE (x
);
5469 /* We no longer know the original mode of operand 0 since we
5470 have changed the form of X) */
5471 op0_mode
= VOIDmode
;
5477 /* Simplify X, a piece of RTL. We just operate on the expression at the
5478 outer level; call `subst' to simplify recursively. Return the new
5481 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5482 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5486 combine_simplify_rtx (rtx x
, machine_mode op0_mode
, int in_dest
,
5489 enum rtx_code code
= GET_CODE (x
);
5490 machine_mode mode
= GET_MODE (x
);
5494 /* If this is a commutative operation, put a constant last and a complex
5495 expression first. We don't need to do this for comparisons here. */
5496 if (COMMUTATIVE_ARITH_P (x
)
5497 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
5500 SUBST (XEXP (x
, 0), XEXP (x
, 1));
5501 SUBST (XEXP (x
, 1), temp
);
5504 /* Try to fold this expression in case we have constants that weren't
5507 switch (GET_RTX_CLASS (code
))
5510 if (op0_mode
== VOIDmode
)
5511 op0_mode
= GET_MODE (XEXP (x
, 0));
5512 temp
= simplify_unary_operation (code
, mode
, XEXP (x
, 0), op0_mode
);
5515 case RTX_COMM_COMPARE
:
5517 machine_mode cmp_mode
= GET_MODE (XEXP (x
, 0));
5518 if (cmp_mode
== VOIDmode
)
5520 cmp_mode
= GET_MODE (XEXP (x
, 1));
5521 if (cmp_mode
== VOIDmode
)
5522 cmp_mode
= op0_mode
;
5524 temp
= simplify_relational_operation (code
, mode
, cmp_mode
,
5525 XEXP (x
, 0), XEXP (x
, 1));
5528 case RTX_COMM_ARITH
:
5530 temp
= simplify_binary_operation (code
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5532 case RTX_BITFIELD_OPS
:
5534 temp
= simplify_ternary_operation (code
, mode
, op0_mode
, XEXP (x
, 0),
5535 XEXP (x
, 1), XEXP (x
, 2));
5544 code
= GET_CODE (temp
);
5545 op0_mode
= VOIDmode
;
5546 mode
= GET_MODE (temp
);
5549 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5550 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5551 things. Check for cases where both arms are testing the same
5554 Don't do anything if all operands are very simple. */
5557 && ((!OBJECT_P (XEXP (x
, 0))
5558 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5559 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))
5560 || (!OBJECT_P (XEXP (x
, 1))
5561 && ! (GET_CODE (XEXP (x
, 1)) == SUBREG
5562 && OBJECT_P (SUBREG_REG (XEXP (x
, 1)))))))
5564 && (!OBJECT_P (XEXP (x
, 0))
5565 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5566 && OBJECT_P (SUBREG_REG (XEXP (x
, 0)))))))
5568 rtx cond
, true_rtx
, false_rtx
;
5570 cond
= if_then_else_cond (x
, &true_rtx
, &false_rtx
);
5572 /* If everything is a comparison, what we have is highly unlikely
5573 to be simpler, so don't use it. */
5574 && ! (COMPARISON_P (x
)
5575 && (COMPARISON_P (true_rtx
) || COMPARISON_P (false_rtx
))))
5577 rtx cop1
= const0_rtx
;
5578 enum rtx_code cond_code
= simplify_comparison (NE
, &cond
, &cop1
);
5580 if (cond_code
== NE
&& COMPARISON_P (cond
))
5583 /* Simplify the alternative arms; this may collapse the true and
5584 false arms to store-flag values. Be careful to use copy_rtx
5585 here since true_rtx or false_rtx might share RTL with x as a
5586 result of the if_then_else_cond call above. */
5587 true_rtx
= subst (copy_rtx (true_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5588 false_rtx
= subst (copy_rtx (false_rtx
), pc_rtx
, pc_rtx
, 0, 0, 0);
5590 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5591 is unlikely to be simpler. */
5592 if (general_operand (true_rtx
, VOIDmode
)
5593 && general_operand (false_rtx
, VOIDmode
))
5595 enum rtx_code reversed
;
5597 /* Restarting if we generate a store-flag expression will cause
5598 us to loop. Just drop through in this case. */
5600 /* If the result values are STORE_FLAG_VALUE and zero, we can
5601 just make the comparison operation. */
5602 if (true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
5603 x
= simplify_gen_relational (cond_code
, mode
, VOIDmode
,
5605 else if (true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
5606 && ((reversed
= reversed_comparison_code_parts
5607 (cond_code
, cond
, cop1
, NULL
))
5609 x
= simplify_gen_relational (reversed
, mode
, VOIDmode
,
5612 /* Likewise, we can make the negate of a comparison operation
5613 if the result values are - STORE_FLAG_VALUE and zero. */
5614 else if (CONST_INT_P (true_rtx
)
5615 && INTVAL (true_rtx
) == - STORE_FLAG_VALUE
5616 && false_rtx
== const0_rtx
)
5617 x
= simplify_gen_unary (NEG
, mode
,
5618 simplify_gen_relational (cond_code
,
5622 else if (CONST_INT_P (false_rtx
)
5623 && INTVAL (false_rtx
) == - STORE_FLAG_VALUE
5624 && true_rtx
== const0_rtx
5625 && ((reversed
= reversed_comparison_code_parts
5626 (cond_code
, cond
, cop1
, NULL
))
5628 x
= simplify_gen_unary (NEG
, mode
,
5629 simplify_gen_relational (reversed
,
5634 return gen_rtx_IF_THEN_ELSE (mode
,
5635 simplify_gen_relational (cond_code
,
5640 true_rtx
, false_rtx
);
5642 code
= GET_CODE (x
);
5643 op0_mode
= VOIDmode
;
5648 /* First see if we can apply the inverse distributive law. */
5649 if (code
== PLUS
|| code
== MINUS
5650 || code
== AND
|| code
== IOR
|| code
== XOR
)
5652 x
= apply_distributive_law (x
);
5653 code
= GET_CODE (x
);
5654 op0_mode
= VOIDmode
;
5657 /* If CODE is an associative operation not otherwise handled, see if we
5658 can associate some operands. This can win if they are constants or
5659 if they are logically related (i.e. (a & b) & a). */
5660 if ((code
== PLUS
|| code
== MINUS
|| code
== MULT
|| code
== DIV
5661 || code
== AND
|| code
== IOR
|| code
== XOR
5662 || code
== SMAX
|| code
== SMIN
|| code
== UMAX
|| code
== UMIN
)
5663 && ((INTEGRAL_MODE_P (mode
) && code
!= DIV
)
5664 || (flag_associative_math
&& FLOAT_MODE_P (mode
))))
5666 if (GET_CODE (XEXP (x
, 0)) == code
)
5668 rtx other
= XEXP (XEXP (x
, 0), 0);
5669 rtx inner_op0
= XEXP (XEXP (x
, 0), 1);
5670 rtx inner_op1
= XEXP (x
, 1);
5673 /* Make sure we pass the constant operand if any as the second
5674 one if this is a commutative operation. */
5675 if (CONSTANT_P (inner_op0
) && COMMUTATIVE_ARITH_P (x
))
5676 std::swap (inner_op0
, inner_op1
);
5677 inner
= simplify_binary_operation (code
== MINUS
? PLUS
5678 : code
== DIV
? MULT
5680 mode
, inner_op0
, inner_op1
);
5682 /* For commutative operations, try the other pair if that one
5684 if (inner
== 0 && COMMUTATIVE_ARITH_P (x
))
5686 other
= XEXP (XEXP (x
, 0), 1);
5687 inner
= simplify_binary_operation (code
, mode
,
5688 XEXP (XEXP (x
, 0), 0),
5693 return simplify_gen_binary (code
, mode
, other
, inner
);
5697 /* A little bit of algebraic simplification here. */
5701 /* Ensure that our address has any ASHIFTs converted to MULT in case
5702 address-recognizing predicates are called later. */
5703 temp
= make_compound_operation (XEXP (x
, 0), MEM
);
5704 SUBST (XEXP (x
, 0), temp
);
5708 if (op0_mode
== VOIDmode
)
5709 op0_mode
= GET_MODE (SUBREG_REG (x
));
5711 /* See if this can be moved to simplify_subreg. */
5712 if (CONSTANT_P (SUBREG_REG (x
))
5713 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5714 /* Don't call gen_lowpart if the inner mode
5715 is VOIDmode and we cannot simplify it, as SUBREG without
5716 inner mode is invalid. */
5717 && (GET_MODE (SUBREG_REG (x
)) != VOIDmode
5718 || gen_lowpart_common (mode
, SUBREG_REG (x
))))
5719 return gen_lowpart (mode
, SUBREG_REG (x
));
5721 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x
))) == MODE_CC
)
5725 temp
= simplify_subreg (mode
, SUBREG_REG (x
), op0_mode
,
5730 /* If op is known to have all lower bits zero, the result is zero. */
5732 && SCALAR_INT_MODE_P (mode
)
5733 && SCALAR_INT_MODE_P (op0_mode
)
5734 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (op0_mode
)
5735 && subreg_lowpart_offset (mode
, op0_mode
) == SUBREG_BYTE (x
)
5736 && HWI_COMPUTABLE_MODE_P (op0_mode
)
5737 && (nonzero_bits (SUBREG_REG (x
), op0_mode
)
5738 & GET_MODE_MASK (mode
)) == 0)
5739 return CONST0_RTX (mode
);
5742 /* Don't change the mode of the MEM if that would change the meaning
5744 if (MEM_P (SUBREG_REG (x
))
5745 && (MEM_VOLATILE_P (SUBREG_REG (x
))
5746 || mode_dependent_address_p (XEXP (SUBREG_REG (x
), 0),
5747 MEM_ADDR_SPACE (SUBREG_REG (x
)))))
5748 return gen_rtx_CLOBBER (mode
, const0_rtx
);
5750 /* Note that we cannot do any narrowing for non-constants since
5751 we might have been counting on using the fact that some bits were
5752 zero. We now do this in the SET. */
5757 temp
= expand_compound_operation (XEXP (x
, 0));
5759 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5760 replaced by (lshiftrt X C). This will convert
5761 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5763 if (GET_CODE (temp
) == ASHIFTRT
5764 && CONST_INT_P (XEXP (temp
, 1))
5765 && INTVAL (XEXP (temp
, 1)) == GET_MODE_PRECISION (mode
) - 1)
5766 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (temp
, 0),
5767 INTVAL (XEXP (temp
, 1)));
5769 /* If X has only a single bit that might be nonzero, say, bit I, convert
5770 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5771 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5772 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5773 or a SUBREG of one since we'd be making the expression more
5774 complex if it was just a register. */
5777 && ! (GET_CODE (temp
) == SUBREG
5778 && REG_P (SUBREG_REG (temp
)))
5779 && (i
= exact_log2 (nonzero_bits (temp
, mode
))) >= 0)
5781 rtx temp1
= simplify_shift_const
5782 (NULL_RTX
, ASHIFTRT
, mode
,
5783 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, temp
,
5784 GET_MODE_PRECISION (mode
) - 1 - i
),
5785 GET_MODE_PRECISION (mode
) - 1 - i
);
5787 /* If all we did was surround TEMP with the two shifts, we
5788 haven't improved anything, so don't use it. Otherwise,
5789 we are better off with TEMP1. */
5790 if (GET_CODE (temp1
) != ASHIFTRT
5791 || GET_CODE (XEXP (temp1
, 0)) != ASHIFT
5792 || XEXP (XEXP (temp1
, 0), 0) != temp
)
5798 /* We can't handle truncation to a partial integer mode here
5799 because we don't know the real bitsize of the partial
5801 if (GET_MODE_CLASS (mode
) == MODE_PARTIAL_INT
)
5804 if (HWI_COMPUTABLE_MODE_P (mode
))
5806 force_to_mode (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)),
5807 GET_MODE_MASK (mode
), 0));
5809 /* We can truncate a constant value and return it. */
5810 if (CONST_INT_P (XEXP (x
, 0)))
5811 return gen_int_mode (INTVAL (XEXP (x
, 0)), mode
);
5813 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5814 whose value is a comparison can be replaced with a subreg if
5815 STORE_FLAG_VALUE permits. */
5816 if (HWI_COMPUTABLE_MODE_P (mode
)
5817 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (mode
)) == 0
5818 && (temp
= get_last_value (XEXP (x
, 0)))
5819 && COMPARISON_P (temp
))
5820 return gen_lowpart (mode
, XEXP (x
, 0));
5824 /* (const (const X)) can become (const X). Do it this way rather than
5825 returning the inner CONST since CONST can be shared with a
5827 if (GET_CODE (XEXP (x
, 0)) == CONST
)
5828 SUBST (XEXP (x
, 0), XEXP (XEXP (x
, 0), 0));
5832 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5833 can add in an offset. find_split_point will split this address up
5834 again if it doesn't match. */
5835 if (HAVE_lo_sum
&& GET_CODE (XEXP (x
, 0)) == HIGH
5836 && rtx_equal_p (XEXP (XEXP (x
, 0), 0), XEXP (x
, 1)))
5841 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5842 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5843 bit-field and can be replaced by either a sign_extend or a
5844 sign_extract. The `and' may be a zero_extend and the two
5845 <c>, -<c> constants may be reversed. */
5846 if (GET_CODE (XEXP (x
, 0)) == XOR
5847 && CONST_INT_P (XEXP (x
, 1))
5848 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
5849 && INTVAL (XEXP (x
, 1)) == -INTVAL (XEXP (XEXP (x
, 0), 1))
5850 && ((i
= exact_log2 (UINTVAL (XEXP (XEXP (x
, 0), 1)))) >= 0
5851 || (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
5852 && HWI_COMPUTABLE_MODE_P (mode
)
5853 && ((GET_CODE (XEXP (XEXP (x
, 0), 0)) == AND
5854 && CONST_INT_P (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5855 && (UINTVAL (XEXP (XEXP (XEXP (x
, 0), 0), 1))
5856 == (HOST_WIDE_INT_1U
<< (i
+ 1)) - 1))
5857 || (GET_CODE (XEXP (XEXP (x
, 0), 0)) == ZERO_EXTEND
5858 && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)))
5859 == (unsigned int) i
+ 1))))
5860 return simplify_shift_const
5861 (NULL_RTX
, ASHIFTRT
, mode
,
5862 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5863 XEXP (XEXP (XEXP (x
, 0), 0), 0),
5864 GET_MODE_PRECISION (mode
) - (i
+ 1)),
5865 GET_MODE_PRECISION (mode
) - (i
+ 1));
5867 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5868 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5869 the bitsize of the mode - 1. This allows simplification of
5870 "a = (b & 8) == 0;" */
5871 if (XEXP (x
, 1) == constm1_rtx
5872 && !REG_P (XEXP (x
, 0))
5873 && ! (GET_CODE (XEXP (x
, 0)) == SUBREG
5874 && REG_P (SUBREG_REG (XEXP (x
, 0))))
5875 && nonzero_bits (XEXP (x
, 0), mode
) == 1)
5876 return simplify_shift_const (NULL_RTX
, ASHIFTRT
, mode
,
5877 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
5878 gen_rtx_XOR (mode
, XEXP (x
, 0), const1_rtx
),
5879 GET_MODE_PRECISION (mode
) - 1),
5880 GET_MODE_PRECISION (mode
) - 1);
5882 /* If we are adding two things that have no bits in common, convert
5883 the addition into an IOR. This will often be further simplified,
5884 for example in cases like ((a & 1) + (a & 2)), which can
5887 if (HWI_COMPUTABLE_MODE_P (mode
)
5888 && (nonzero_bits (XEXP (x
, 0), mode
)
5889 & nonzero_bits (XEXP (x
, 1), mode
)) == 0)
5891 /* Try to simplify the expression further. */
5892 rtx tor
= simplify_gen_binary (IOR
, mode
, XEXP (x
, 0), XEXP (x
, 1));
5893 temp
= combine_simplify_rtx (tor
, VOIDmode
, in_dest
, 0);
5895 /* If we could, great. If not, do not go ahead with the IOR
5896 replacement, since PLUS appears in many special purpose
5897 address arithmetic instructions. */
5898 if (GET_CODE (temp
) != CLOBBER
5899 && (GET_CODE (temp
) != IOR
5900 || ((XEXP (temp
, 0) != XEXP (x
, 0)
5901 || XEXP (temp
, 1) != XEXP (x
, 1))
5902 && (XEXP (temp
, 0) != XEXP (x
, 1)
5903 || XEXP (temp
, 1) != XEXP (x
, 0)))))
5907 /* Canonicalize x + x into x << 1. */
5908 if (GET_MODE_CLASS (mode
) == MODE_INT
5909 && rtx_equal_p (XEXP (x
, 0), XEXP (x
, 1))
5910 && !side_effects_p (XEXP (x
, 0)))
5911 return simplify_gen_binary (ASHIFT
, mode
, XEXP (x
, 0), const1_rtx
);
5916 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5917 (and <foo> (const_int pow2-1)) */
5918 if (GET_CODE (XEXP (x
, 1)) == AND
5919 && CONST_INT_P (XEXP (XEXP (x
, 1), 1))
5920 && pow2p_hwi (-UINTVAL (XEXP (XEXP (x
, 1), 1)))
5921 && rtx_equal_p (XEXP (XEXP (x
, 1), 0), XEXP (x
, 0)))
5922 return simplify_and_const_int (NULL_RTX
, mode
, XEXP (x
, 0),
5923 -INTVAL (XEXP (XEXP (x
, 1), 1)) - 1);
5927 /* If we have (mult (plus A B) C), apply the distributive law and then
5928 the inverse distributive law to see if things simplify. This
5929 occurs mostly in addresses, often when unrolling loops. */
5931 if (GET_CODE (XEXP (x
, 0)) == PLUS
)
5933 rtx result
= distribute_and_simplify_rtx (x
, 0);
5938 /* Try simplify a*(b/c) as (a*b)/c. */
5939 if (FLOAT_MODE_P (mode
) && flag_associative_math
5940 && GET_CODE (XEXP (x
, 0)) == DIV
)
5942 rtx tem
= simplify_binary_operation (MULT
, mode
,
5943 XEXP (XEXP (x
, 0), 0),
5946 return simplify_gen_binary (DIV
, mode
, tem
, XEXP (XEXP (x
, 0), 1));
5951 /* If this is a divide by a power of two, treat it as a shift if
5952 its first operand is a shift. */
5953 if (CONST_INT_P (XEXP (x
, 1))
5954 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0
5955 && (GET_CODE (XEXP (x
, 0)) == ASHIFT
5956 || GET_CODE (XEXP (x
, 0)) == LSHIFTRT
5957 || GET_CODE (XEXP (x
, 0)) == ASHIFTRT
5958 || GET_CODE (XEXP (x
, 0)) == ROTATE
5959 || GET_CODE (XEXP (x
, 0)) == ROTATERT
))
5960 return simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
, XEXP (x
, 0), i
);
5964 case GT
: case GTU
: case GE
: case GEU
:
5965 case LT
: case LTU
: case LE
: case LEU
:
5966 case UNEQ
: case LTGT
:
5967 case UNGT
: case UNGE
:
5968 case UNLT
: case UNLE
:
5969 case UNORDERED
: case ORDERED
:
5970 /* If the first operand is a condition code, we can't do anything
5972 if (GET_CODE (XEXP (x
, 0)) == COMPARE
5973 || (GET_MODE_CLASS (GET_MODE (XEXP (x
, 0))) != MODE_CC
5974 && ! CC0_P (XEXP (x
, 0))))
5976 rtx op0
= XEXP (x
, 0);
5977 rtx op1
= XEXP (x
, 1);
5978 enum rtx_code new_code
;
5980 if (GET_CODE (op0
) == COMPARE
)
5981 op1
= XEXP (op0
, 1), op0
= XEXP (op0
, 0);
5983 /* Simplify our comparison, if possible. */
5984 new_code
= simplify_comparison (code
, &op0
, &op1
);
5986 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5987 if only the low-order bit is possibly nonzero in X (such as when
5988 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5989 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5990 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5993 Remove any ZERO_EXTRACT we made when thinking this was a
5994 comparison. It may now be simpler to use, e.g., an AND. If a
5995 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5996 the call to make_compound_operation in the SET case.
5998 Don't apply these optimizations if the caller would
5999 prefer a comparison rather than a value.
6000 E.g., for the condition in an IF_THEN_ELSE most targets need
6001 an explicit comparison. */
6006 else if (STORE_FLAG_VALUE
== 1
6007 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6008 && op1
== const0_rtx
6009 && mode
== GET_MODE (op0
)
6010 && nonzero_bits (op0
, mode
) == 1)
6011 return gen_lowpart (mode
,
6012 expand_compound_operation (op0
));
6014 else if (STORE_FLAG_VALUE
== 1
6015 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6016 && op1
== const0_rtx
6017 && mode
== GET_MODE (op0
)
6018 && (num_sign_bit_copies (op0
, mode
)
6019 == GET_MODE_PRECISION (mode
)))
6021 op0
= expand_compound_operation (op0
);
6022 return simplify_gen_unary (NEG
, mode
,
6023 gen_lowpart (mode
, op0
),
6027 else if (STORE_FLAG_VALUE
== 1
6028 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6029 && op1
== const0_rtx
6030 && mode
== GET_MODE (op0
)
6031 && nonzero_bits (op0
, mode
) == 1)
6033 op0
= expand_compound_operation (op0
);
6034 return simplify_gen_binary (XOR
, mode
,
6035 gen_lowpart (mode
, op0
),
6039 else if (STORE_FLAG_VALUE
== 1
6040 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6041 && op1
== const0_rtx
6042 && mode
== GET_MODE (op0
)
6043 && (num_sign_bit_copies (op0
, mode
)
6044 == GET_MODE_PRECISION (mode
)))
6046 op0
= expand_compound_operation (op0
);
6047 return plus_constant (mode
, gen_lowpart (mode
, op0
), 1);
6050 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6055 else if (STORE_FLAG_VALUE
== -1
6056 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6057 && op1
== const0_rtx
6058 && mode
== GET_MODE (op0
)
6059 && (num_sign_bit_copies (op0
, mode
)
6060 == GET_MODE_PRECISION (mode
)))
6061 return gen_lowpart (mode
,
6062 expand_compound_operation (op0
));
6064 else if (STORE_FLAG_VALUE
== -1
6065 && new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6066 && op1
== const0_rtx
6067 && mode
== GET_MODE (op0
)
6068 && nonzero_bits (op0
, mode
) == 1)
6070 op0
= expand_compound_operation (op0
);
6071 return simplify_gen_unary (NEG
, mode
,
6072 gen_lowpart (mode
, op0
),
6076 else if (STORE_FLAG_VALUE
== -1
6077 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6078 && op1
== const0_rtx
6079 && mode
== GET_MODE (op0
)
6080 && (num_sign_bit_copies (op0
, mode
)
6081 == GET_MODE_PRECISION (mode
)))
6083 op0
= expand_compound_operation (op0
);
6084 return simplify_gen_unary (NOT
, mode
,
6085 gen_lowpart (mode
, op0
),
6089 /* If X is 0/1, (eq X 0) is X-1. */
6090 else if (STORE_FLAG_VALUE
== -1
6091 && new_code
== EQ
&& GET_MODE_CLASS (mode
) == MODE_INT
6092 && op1
== const0_rtx
6093 && mode
== GET_MODE (op0
)
6094 && nonzero_bits (op0
, mode
) == 1)
6096 op0
= expand_compound_operation (op0
);
6097 return plus_constant (mode
, gen_lowpart (mode
, op0
), -1);
6100 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6101 one bit that might be nonzero, we can convert (ne x 0) to
6102 (ashift x c) where C puts the bit in the sign bit. Remove any
6103 AND with STORE_FLAG_VALUE when we are done, since we are only
6104 going to test the sign bit. */
6105 if (new_code
== NE
&& GET_MODE_CLASS (mode
) == MODE_INT
6106 && HWI_COMPUTABLE_MODE_P (mode
)
6107 && val_signbit_p (mode
, STORE_FLAG_VALUE
)
6108 && op1
== const0_rtx
6109 && mode
== GET_MODE (op0
)
6110 && (i
= exact_log2 (nonzero_bits (op0
, mode
))) >= 0)
6112 x
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6113 expand_compound_operation (op0
),
6114 GET_MODE_PRECISION (mode
) - 1 - i
);
6115 if (GET_CODE (x
) == AND
&& XEXP (x
, 1) == const_true_rtx
)
6121 /* If the code changed, return a whole new comparison.
6122 We also need to avoid using SUBST in cases where
6123 simplify_comparison has widened a comparison with a CONST_INT,
6124 since in that case the wider CONST_INT may fail the sanity
6125 checks in do_SUBST. */
6126 if (new_code
!= code
6127 || (CONST_INT_P (op1
)
6128 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 0))
6129 && GET_MODE (op0
) != GET_MODE (XEXP (x
, 1))))
6130 return gen_rtx_fmt_ee (new_code
, mode
, op0
, op1
);
6132 /* Otherwise, keep this operation, but maybe change its operands.
6133 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6134 SUBST (XEXP (x
, 0), op0
);
6135 SUBST (XEXP (x
, 1), op1
);
6140 return simplify_if_then_else (x
);
6146 /* If we are processing SET_DEST, we are done. */
6150 return expand_compound_operation (x
);
6153 return simplify_set (x
);
6157 return simplify_logical (x
);
6164 /* If this is a shift by a constant amount, simplify it. */
6165 if (CONST_INT_P (XEXP (x
, 1)))
6166 return simplify_shift_const (x
, code
, mode
, XEXP (x
, 0),
6167 INTVAL (XEXP (x
, 1)));
6169 else if (SHIFT_COUNT_TRUNCATED
&& !REG_P (XEXP (x
, 1)))
6171 force_to_mode (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)),
6173 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x
))))
6185 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6188 simplify_if_then_else (rtx x
)
6190 machine_mode mode
= GET_MODE (x
);
6191 rtx cond
= XEXP (x
, 0);
6192 rtx true_rtx
= XEXP (x
, 1);
6193 rtx false_rtx
= XEXP (x
, 2);
6194 enum rtx_code true_code
= GET_CODE (cond
);
6195 int comparison_p
= COMPARISON_P (cond
);
6198 enum rtx_code false_code
;
6201 /* Simplify storing of the truth value. */
6202 if (comparison_p
&& true_rtx
== const_true_rtx
&& false_rtx
== const0_rtx
)
6203 return simplify_gen_relational (true_code
, mode
, VOIDmode
,
6204 XEXP (cond
, 0), XEXP (cond
, 1));
6206 /* Also when the truth value has to be reversed. */
6208 && true_rtx
== const0_rtx
&& false_rtx
== const_true_rtx
6209 && (reversed
= reversed_comparison (cond
, mode
)))
6212 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6213 in it is being compared against certain values. Get the true and false
6214 comparisons and see if that says anything about the value of each arm. */
6217 && ((false_code
= reversed_comparison_code (cond
, NULL
))
6219 && REG_P (XEXP (cond
, 0)))
6222 rtx from
= XEXP (cond
, 0);
6223 rtx true_val
= XEXP (cond
, 1);
6224 rtx false_val
= true_val
;
6227 /* If FALSE_CODE is EQ, swap the codes and arms. */
6229 if (false_code
== EQ
)
6231 swapped
= 1, true_code
= EQ
, false_code
= NE
;
6232 std::swap (true_rtx
, false_rtx
);
6235 /* If we are comparing against zero and the expression being tested has
6236 only a single bit that might be nonzero, that is its value when it is
6237 not equal to zero. Similarly if it is known to be -1 or 0. */
6239 if (true_code
== EQ
&& true_val
== const0_rtx
6240 && pow2p_hwi (nzb
= nonzero_bits (from
, GET_MODE (from
))))
6243 false_val
= gen_int_mode (nzb
, GET_MODE (from
));
6245 else if (true_code
== EQ
&& true_val
== const0_rtx
6246 && (num_sign_bit_copies (from
, GET_MODE (from
))
6247 == GET_MODE_PRECISION (GET_MODE (from
))))
6250 false_val
= constm1_rtx
;
6253 /* Now simplify an arm if we know the value of the register in the
6254 branch and it is used in the arm. Be careful due to the potential
6255 of locally-shared RTL. */
6257 if (reg_mentioned_p (from
, true_rtx
))
6258 true_rtx
= subst (known_cond (copy_rtx (true_rtx
), true_code
,
6260 pc_rtx
, pc_rtx
, 0, 0, 0);
6261 if (reg_mentioned_p (from
, false_rtx
))
6262 false_rtx
= subst (known_cond (copy_rtx (false_rtx
), false_code
,
6264 pc_rtx
, pc_rtx
, 0, 0, 0);
6266 SUBST (XEXP (x
, 1), swapped
? false_rtx
: true_rtx
);
6267 SUBST (XEXP (x
, 2), swapped
? true_rtx
: false_rtx
);
6269 true_rtx
= XEXP (x
, 1);
6270 false_rtx
= XEXP (x
, 2);
6271 true_code
= GET_CODE (cond
);
6274 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6275 reversed, do so to avoid needing two sets of patterns for
6276 subtract-and-branch insns. Similarly if we have a constant in the true
6277 arm, the false arm is the same as the first operand of the comparison, or
6278 the false arm is more complicated than the true arm. */
6281 && reversed_comparison_code (cond
, NULL
) != UNKNOWN
6282 && (true_rtx
== pc_rtx
6283 || (CONSTANT_P (true_rtx
)
6284 && !CONST_INT_P (false_rtx
) && false_rtx
!= pc_rtx
)
6285 || true_rtx
== const0_rtx
6286 || (OBJECT_P (true_rtx
) && !OBJECT_P (false_rtx
))
6287 || (GET_CODE (true_rtx
) == SUBREG
&& OBJECT_P (SUBREG_REG (true_rtx
))
6288 && !OBJECT_P (false_rtx
))
6289 || reg_mentioned_p (true_rtx
, false_rtx
)
6290 || rtx_equal_p (false_rtx
, XEXP (cond
, 0))))
6292 true_code
= reversed_comparison_code (cond
, NULL
);
6293 SUBST (XEXP (x
, 0), reversed_comparison (cond
, GET_MODE (cond
)));
6294 SUBST (XEXP (x
, 1), false_rtx
);
6295 SUBST (XEXP (x
, 2), true_rtx
);
6297 std::swap (true_rtx
, false_rtx
);
6300 /* It is possible that the conditional has been simplified out. */
6301 true_code
= GET_CODE (cond
);
6302 comparison_p
= COMPARISON_P (cond
);
6305 /* If the two arms are identical, we don't need the comparison. */
6307 if (rtx_equal_p (true_rtx
, false_rtx
) && ! side_effects_p (cond
))
6310 /* Convert a == b ? b : a to "a". */
6311 if (true_code
== EQ
&& ! side_effects_p (cond
)
6312 && !HONOR_NANS (mode
)
6313 && rtx_equal_p (XEXP (cond
, 0), false_rtx
)
6314 && rtx_equal_p (XEXP (cond
, 1), true_rtx
))
6316 else if (true_code
== NE
&& ! side_effects_p (cond
)
6317 && !HONOR_NANS (mode
)
6318 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6319 && rtx_equal_p (XEXP (cond
, 1), false_rtx
))
6322 /* Look for cases where we have (abs x) or (neg (abs X)). */
6324 if (GET_MODE_CLASS (mode
) == MODE_INT
6326 && XEXP (cond
, 1) == const0_rtx
6327 && GET_CODE (false_rtx
) == NEG
6328 && rtx_equal_p (true_rtx
, XEXP (false_rtx
, 0))
6329 && rtx_equal_p (true_rtx
, XEXP (cond
, 0))
6330 && ! side_effects_p (true_rtx
))
6335 return simplify_gen_unary (ABS
, mode
, true_rtx
, mode
);
6339 simplify_gen_unary (NEG
, mode
,
6340 simplify_gen_unary (ABS
, mode
, true_rtx
, mode
),
6346 /* Look for MIN or MAX. */
6348 if ((! FLOAT_MODE_P (mode
) || flag_unsafe_math_optimizations
)
6350 && rtx_equal_p (XEXP (cond
, 0), true_rtx
)
6351 && rtx_equal_p (XEXP (cond
, 1), false_rtx
)
6352 && ! side_effects_p (cond
))
6357 return simplify_gen_binary (SMAX
, mode
, true_rtx
, false_rtx
);
6360 return simplify_gen_binary (SMIN
, mode
, true_rtx
, false_rtx
);
6363 return simplify_gen_binary (UMAX
, mode
, true_rtx
, false_rtx
);
6366 return simplify_gen_binary (UMIN
, mode
, true_rtx
, false_rtx
);
6371 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6372 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6373 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6374 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6375 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6376 neither 1 or -1, but it isn't worth checking for. */
6378 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
6380 && GET_MODE_CLASS (mode
) == MODE_INT
6381 && ! side_effects_p (x
))
6383 rtx t
= make_compound_operation (true_rtx
, SET
);
6384 rtx f
= make_compound_operation (false_rtx
, SET
);
6385 rtx cond_op0
= XEXP (cond
, 0);
6386 rtx cond_op1
= XEXP (cond
, 1);
6387 enum rtx_code op
= UNKNOWN
, extend_op
= UNKNOWN
;
6388 machine_mode m
= mode
;
6389 rtx z
= 0, c1
= NULL_RTX
;
6391 if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == MINUS
6392 || GET_CODE (t
) == IOR
|| GET_CODE (t
) == XOR
6393 || GET_CODE (t
) == ASHIFT
6394 || GET_CODE (t
) == LSHIFTRT
|| GET_CODE (t
) == ASHIFTRT
)
6395 && rtx_equal_p (XEXP (t
, 0), f
))
6396 c1
= XEXP (t
, 1), op
= GET_CODE (t
), z
= f
;
6398 /* If an identity-zero op is commutative, check whether there
6399 would be a match if we swapped the operands. */
6400 else if ((GET_CODE (t
) == PLUS
|| GET_CODE (t
) == IOR
6401 || GET_CODE (t
) == XOR
)
6402 && rtx_equal_p (XEXP (t
, 1), f
))
6403 c1
= XEXP (t
, 0), op
= GET_CODE (t
), z
= f
;
6404 else if (GET_CODE (t
) == SIGN_EXTEND
6405 && (GET_CODE (XEXP (t
, 0)) == PLUS
6406 || GET_CODE (XEXP (t
, 0)) == MINUS
6407 || GET_CODE (XEXP (t
, 0)) == IOR
6408 || GET_CODE (XEXP (t
, 0)) == XOR
6409 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6410 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6411 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6412 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6413 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6414 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6415 && (num_sign_bit_copies (f
, GET_MODE (f
))
6417 (GET_MODE_PRECISION (mode
)
6418 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 0))))))
6420 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6421 extend_op
= SIGN_EXTEND
;
6422 m
= GET_MODE (XEXP (t
, 0));
6424 else if (GET_CODE (t
) == SIGN_EXTEND
6425 && (GET_CODE (XEXP (t
, 0)) == PLUS
6426 || GET_CODE (XEXP (t
, 0)) == IOR
6427 || GET_CODE (XEXP (t
, 0)) == XOR
)
6428 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6429 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6430 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6431 && (num_sign_bit_copies (f
, GET_MODE (f
))
6433 (GET_MODE_PRECISION (mode
)
6434 - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t
, 0), 1))))))
6436 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6437 extend_op
= SIGN_EXTEND
;
6438 m
= GET_MODE (XEXP (t
, 0));
6440 else if (GET_CODE (t
) == ZERO_EXTEND
6441 && (GET_CODE (XEXP (t
, 0)) == PLUS
6442 || GET_CODE (XEXP (t
, 0)) == MINUS
6443 || GET_CODE (XEXP (t
, 0)) == IOR
6444 || GET_CODE (XEXP (t
, 0)) == XOR
6445 || GET_CODE (XEXP (t
, 0)) == ASHIFT
6446 || GET_CODE (XEXP (t
, 0)) == LSHIFTRT
6447 || GET_CODE (XEXP (t
, 0)) == ASHIFTRT
)
6448 && GET_CODE (XEXP (XEXP (t
, 0), 0)) == SUBREG
6449 && HWI_COMPUTABLE_MODE_P (mode
)
6450 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 0))
6451 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 0)), f
)
6452 && ((nonzero_bits (f
, GET_MODE (f
))
6453 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 0))))
6456 c1
= XEXP (XEXP (t
, 0), 1); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6457 extend_op
= ZERO_EXTEND
;
6458 m
= GET_MODE (XEXP (t
, 0));
6460 else if (GET_CODE (t
) == ZERO_EXTEND
6461 && (GET_CODE (XEXP (t
, 0)) == PLUS
6462 || GET_CODE (XEXP (t
, 0)) == IOR
6463 || GET_CODE (XEXP (t
, 0)) == XOR
)
6464 && GET_CODE (XEXP (XEXP (t
, 0), 1)) == SUBREG
6465 && HWI_COMPUTABLE_MODE_P (mode
)
6466 && subreg_lowpart_p (XEXP (XEXP (t
, 0), 1))
6467 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t
, 0), 1)), f
)
6468 && ((nonzero_bits (f
, GET_MODE (f
))
6469 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t
, 0), 1))))
6472 c1
= XEXP (XEXP (t
, 0), 0); z
= f
; op
= GET_CODE (XEXP (t
, 0));
6473 extend_op
= ZERO_EXTEND
;
6474 m
= GET_MODE (XEXP (t
, 0));
6479 temp
= subst (simplify_gen_relational (true_code
, m
, VOIDmode
,
6480 cond_op0
, cond_op1
),
6481 pc_rtx
, pc_rtx
, 0, 0, 0);
6482 temp
= simplify_gen_binary (MULT
, m
, temp
,
6483 simplify_gen_binary (MULT
, m
, c1
,
6485 temp
= subst (temp
, pc_rtx
, pc_rtx
, 0, 0, 0);
6486 temp
= simplify_gen_binary (op
, m
, gen_lowpart (m
, z
), temp
);
6488 if (extend_op
!= UNKNOWN
)
6489 temp
= simplify_gen_unary (extend_op
, mode
, temp
, m
);
6495 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6496 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6497 negation of a single bit, we can convert this operation to a shift. We
6498 can actually do this more generally, but it doesn't seem worth it. */
6500 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6501 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6502 && ((1 == nonzero_bits (XEXP (cond
, 0), mode
)
6503 && (i
= exact_log2 (UINTVAL (true_rtx
))) >= 0)
6504 || ((num_sign_bit_copies (XEXP (cond
, 0), mode
)
6505 == GET_MODE_PRECISION (mode
))
6506 && (i
= exact_log2 (-UINTVAL (true_rtx
))) >= 0)))
6508 simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
6509 gen_lowpart (mode
, XEXP (cond
, 0)), i
);
6511 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6512 if (true_code
== NE
&& XEXP (cond
, 1) == const0_rtx
6513 && false_rtx
== const0_rtx
&& CONST_INT_P (true_rtx
)
6514 && GET_MODE (XEXP (cond
, 0)) == mode
6515 && (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))
6516 == nonzero_bits (XEXP (cond
, 0), mode
)
6517 && (i
= exact_log2 (UINTVAL (true_rtx
) & GET_MODE_MASK (mode
))) >= 0)
6518 return XEXP (cond
, 0);
6523 /* Simplify X, a SET expression. Return the new expression. */
6526 simplify_set (rtx x
)
6528 rtx src
= SET_SRC (x
);
6529 rtx dest
= SET_DEST (x
);
6531 = GET_MODE (src
) != VOIDmode
? GET_MODE (src
) : GET_MODE (dest
);
6532 rtx_insn
*other_insn
;
6535 /* (set (pc) (return)) gets written as (return). */
6536 if (GET_CODE (dest
) == PC
&& ANY_RETURN_P (src
))
6539 /* Now that we know for sure which bits of SRC we are using, see if we can
6540 simplify the expression for the object knowing that we only need the
6543 if (GET_MODE_CLASS (mode
) == MODE_INT
&& HWI_COMPUTABLE_MODE_P (mode
))
6545 src
= force_to_mode (src
, mode
, HOST_WIDE_INT_M1U
, 0);
6546 SUBST (SET_SRC (x
), src
);
6549 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6550 the comparison result and try to simplify it unless we already have used
6551 undobuf.other_insn. */
6552 if ((GET_MODE_CLASS (mode
) == MODE_CC
6553 || GET_CODE (src
) == COMPARE
6555 && (cc_use
= find_single_use (dest
, subst_insn
, &other_insn
)) != 0
6556 && (undobuf
.other_insn
== 0 || other_insn
== undobuf
.other_insn
)
6557 && COMPARISON_P (*cc_use
)
6558 && rtx_equal_p (XEXP (*cc_use
, 0), dest
))
6560 enum rtx_code old_code
= GET_CODE (*cc_use
);
6561 enum rtx_code new_code
;
6563 int other_changed
= 0;
6564 rtx inner_compare
= NULL_RTX
;
6565 machine_mode compare_mode
= GET_MODE (dest
);
6567 if (GET_CODE (src
) == COMPARE
)
6569 op0
= XEXP (src
, 0), op1
= XEXP (src
, 1);
6570 if (GET_CODE (op0
) == COMPARE
&& op1
== const0_rtx
)
6572 inner_compare
= op0
;
6573 op0
= XEXP (inner_compare
, 0), op1
= XEXP (inner_compare
, 1);
6577 op0
= src
, op1
= CONST0_RTX (GET_MODE (src
));
6579 tmp
= simplify_relational_operation (old_code
, compare_mode
, VOIDmode
,
6582 new_code
= old_code
;
6583 else if (!CONSTANT_P (tmp
))
6585 new_code
= GET_CODE (tmp
);
6586 op0
= XEXP (tmp
, 0);
6587 op1
= XEXP (tmp
, 1);
6591 rtx pat
= PATTERN (other_insn
);
6592 undobuf
.other_insn
= other_insn
;
6593 SUBST (*cc_use
, tmp
);
6595 /* Attempt to simplify CC user. */
6596 if (GET_CODE (pat
) == SET
)
6598 rtx new_rtx
= simplify_rtx (SET_SRC (pat
));
6599 if (new_rtx
!= NULL_RTX
)
6600 SUBST (SET_SRC (pat
), new_rtx
);
6603 /* Convert X into a no-op move. */
6604 SUBST (SET_DEST (x
), pc_rtx
);
6605 SUBST (SET_SRC (x
), pc_rtx
);
6609 /* Simplify our comparison, if possible. */
6610 new_code
= simplify_comparison (new_code
, &op0
, &op1
);
6612 #ifdef SELECT_CC_MODE
6613 /* If this machine has CC modes other than CCmode, check to see if we
6614 need to use a different CC mode here. */
6615 if (GET_MODE_CLASS (GET_MODE (op0
)) == MODE_CC
)
6616 compare_mode
= GET_MODE (op0
);
6617 else if (inner_compare
6618 && GET_MODE_CLASS (GET_MODE (inner_compare
)) == MODE_CC
6619 && new_code
== old_code
6620 && op0
== XEXP (inner_compare
, 0)
6621 && op1
== XEXP (inner_compare
, 1))
6622 compare_mode
= GET_MODE (inner_compare
);
6624 compare_mode
= SELECT_CC_MODE (new_code
, op0
, op1
);
6626 /* If the mode changed, we have to change SET_DEST, the mode in the
6627 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6628 a hard register, just build new versions with the proper mode. If it
6629 is a pseudo, we lose unless it is only time we set the pseudo, in
6630 which case we can safely change its mode. */
6631 if (!HAVE_cc0
&& compare_mode
!= GET_MODE (dest
))
6633 if (can_change_dest_mode (dest
, 0, compare_mode
))
6635 unsigned int regno
= REGNO (dest
);
6638 if (regno
< FIRST_PSEUDO_REGISTER
)
6639 new_dest
= gen_rtx_REG (compare_mode
, regno
);
6642 SUBST_MODE (regno_reg_rtx
[regno
], compare_mode
);
6643 new_dest
= regno_reg_rtx
[regno
];
6646 SUBST (SET_DEST (x
), new_dest
);
6647 SUBST (XEXP (*cc_use
, 0), new_dest
);
6653 #endif /* SELECT_CC_MODE */
6655 /* If the code changed, we have to build a new comparison in
6656 undobuf.other_insn. */
6657 if (new_code
!= old_code
)
6659 int other_changed_previously
= other_changed
;
6660 unsigned HOST_WIDE_INT mask
;
6661 rtx old_cc_use
= *cc_use
;
6663 SUBST (*cc_use
, gen_rtx_fmt_ee (new_code
, GET_MODE (*cc_use
),
6667 /* If the only change we made was to change an EQ into an NE or
6668 vice versa, OP0 has only one bit that might be nonzero, and OP1
6669 is zero, check if changing the user of the condition code will
6670 produce a valid insn. If it won't, we can keep the original code
6671 in that insn by surrounding our operation with an XOR. */
6673 if (((old_code
== NE
&& new_code
== EQ
)
6674 || (old_code
== EQ
&& new_code
== NE
))
6675 && ! other_changed_previously
&& op1
== const0_rtx
6676 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
6677 && pow2p_hwi (mask
= nonzero_bits (op0
, GET_MODE (op0
))))
6679 rtx pat
= PATTERN (other_insn
), note
= 0;
6681 if ((recog_for_combine (&pat
, other_insn
, ¬e
) < 0
6682 && ! check_asm_operands (pat
)))
6684 *cc_use
= old_cc_use
;
6687 op0
= simplify_gen_binary (XOR
, GET_MODE (op0
), op0
,
6695 undobuf
.other_insn
= other_insn
;
6697 /* Don't generate a compare of a CC with 0, just use that CC. */
6698 if (GET_MODE (op0
) == compare_mode
&& op1
== const0_rtx
)
6700 SUBST (SET_SRC (x
), op0
);
6703 /* Otherwise, if we didn't previously have the same COMPARE we
6704 want, create it from scratch. */
6705 else if (GET_CODE (src
) != COMPARE
|| GET_MODE (src
) != compare_mode
6706 || XEXP (src
, 0) != op0
|| XEXP (src
, 1) != op1
)
6708 SUBST (SET_SRC (x
), gen_rtx_COMPARE (compare_mode
, op0
, op1
));
6714 /* Get SET_SRC in a form where we have placed back any
6715 compound expressions. Then do the checks below. */
6716 src
= make_compound_operation (src
, SET
);
6717 SUBST (SET_SRC (x
), src
);
6720 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6721 and X being a REG or (subreg (reg)), we may be able to convert this to
6722 (set (subreg:m2 x) (op)).
6724 We can always do this if M1 is narrower than M2 because that means that
6725 we only care about the low bits of the result.
6727 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6728 perform a narrower operation than requested since the high-order bits will
6729 be undefined. On machine where it is defined, this transformation is safe
6730 as long as M1 and M2 have the same number of words. */
6732 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6733 && !OBJECT_P (SUBREG_REG (src
))
6734 && (((GET_MODE_SIZE (GET_MODE (src
)) + (UNITS_PER_WORD
- 1))
6736 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))
6737 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
))
6738 && (WORD_REGISTER_OPERATIONS
6739 || (GET_MODE_SIZE (GET_MODE (src
))
6740 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (src
)))))
6741 #ifdef CANNOT_CHANGE_MODE_CLASS
6742 && ! (REG_P (dest
) && REGNO (dest
) < FIRST_PSEUDO_REGISTER
6743 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest
),
6744 GET_MODE (SUBREG_REG (src
)),
6748 || (GET_CODE (dest
) == SUBREG
6749 && REG_P (SUBREG_REG (dest
)))))
6751 SUBST (SET_DEST (x
),
6752 gen_lowpart (GET_MODE (SUBREG_REG (src
)),
6754 SUBST (SET_SRC (x
), SUBREG_REG (src
));
6756 src
= SET_SRC (x
), dest
= SET_DEST (x
);
6759 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6762 && GET_CODE (src
) == SUBREG
6763 && subreg_lowpart_p (src
)
6764 && (GET_MODE_PRECISION (GET_MODE (src
))
6765 < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src
)))))
6767 rtx inner
= SUBREG_REG (src
);
6768 machine_mode inner_mode
= GET_MODE (inner
);
6770 /* Here we make sure that we don't have a sign bit on. */
6771 if (val_signbit_known_clear_p (GET_MODE (src
),
6772 nonzero_bits (inner
, inner_mode
)))
6774 SUBST (SET_SRC (x
), inner
);
6779 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6780 would require a paradoxical subreg. Replace the subreg with a
6781 zero_extend to avoid the reload that would otherwise be required. */
6783 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
)
6784 && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src
)))
6785 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))) != UNKNOWN
6786 && SUBREG_BYTE (src
) == 0
6787 && paradoxical_subreg_p (src
)
6788 && MEM_P (SUBREG_REG (src
)))
6791 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src
))),
6792 GET_MODE (src
), SUBREG_REG (src
)));
6797 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6798 are comparing an item known to be 0 or -1 against 0, use a logical
6799 operation instead. Check for one of the arms being an IOR of the other
6800 arm with some value. We compute three terms to be IOR'ed together. In
6801 practice, at most two will be nonzero. Then we do the IOR's. */
6803 if (GET_CODE (dest
) != PC
6804 && GET_CODE (src
) == IF_THEN_ELSE
6805 && GET_MODE_CLASS (GET_MODE (src
)) == MODE_INT
6806 && (GET_CODE (XEXP (src
, 0)) == EQ
|| GET_CODE (XEXP (src
, 0)) == NE
)
6807 && XEXP (XEXP (src
, 0), 1) == const0_rtx
6808 && GET_MODE (src
) == GET_MODE (XEXP (XEXP (src
, 0), 0))
6809 && (!HAVE_conditional_move
6810 || ! can_conditionally_move_p (GET_MODE (src
)))
6811 && (num_sign_bit_copies (XEXP (XEXP (src
, 0), 0),
6812 GET_MODE (XEXP (XEXP (src
, 0), 0)))
6813 == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src
, 0), 0))))
6814 && ! side_effects_p (src
))
6816 rtx true_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6817 ? XEXP (src
, 1) : XEXP (src
, 2));
6818 rtx false_rtx
= (GET_CODE (XEXP (src
, 0)) == NE
6819 ? XEXP (src
, 2) : XEXP (src
, 1));
6820 rtx term1
= const0_rtx
, term2
, term3
;
6822 if (GET_CODE (true_rtx
) == IOR
6823 && rtx_equal_p (XEXP (true_rtx
, 0), false_rtx
))
6824 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 1), false_rtx
= const0_rtx
;
6825 else if (GET_CODE (true_rtx
) == IOR
6826 && rtx_equal_p (XEXP (true_rtx
, 1), false_rtx
))
6827 term1
= false_rtx
, true_rtx
= XEXP (true_rtx
, 0), false_rtx
= const0_rtx
;
6828 else if (GET_CODE (false_rtx
) == IOR
6829 && rtx_equal_p (XEXP (false_rtx
, 0), true_rtx
))
6830 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 1), true_rtx
= const0_rtx
;
6831 else if (GET_CODE (false_rtx
) == IOR
6832 && rtx_equal_p (XEXP (false_rtx
, 1), true_rtx
))
6833 term1
= true_rtx
, false_rtx
= XEXP (false_rtx
, 0), true_rtx
= const0_rtx
;
6835 term2
= simplify_gen_binary (AND
, GET_MODE (src
),
6836 XEXP (XEXP (src
, 0), 0), true_rtx
);
6837 term3
= simplify_gen_binary (AND
, GET_MODE (src
),
6838 simplify_gen_unary (NOT
, GET_MODE (src
),
6839 XEXP (XEXP (src
, 0), 0),
6844 simplify_gen_binary (IOR
, GET_MODE (src
),
6845 simplify_gen_binary (IOR
, GET_MODE (src
),
6852 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6853 whole thing fail. */
6854 if (GET_CODE (src
) == CLOBBER
&& XEXP (src
, 0) == const0_rtx
)
6856 else if (GET_CODE (dest
) == CLOBBER
&& XEXP (dest
, 0) == const0_rtx
)
6859 /* Convert this into a field assignment operation, if possible. */
6860 return make_field_assignment (x
);
6863 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6867 simplify_logical (rtx x
)
6869 machine_mode mode
= GET_MODE (x
);
6870 rtx op0
= XEXP (x
, 0);
6871 rtx op1
= XEXP (x
, 1);
6873 switch (GET_CODE (x
))
6876 /* We can call simplify_and_const_int only if we don't lose
6877 any (sign) bits when converting INTVAL (op1) to
6878 "unsigned HOST_WIDE_INT". */
6879 if (CONST_INT_P (op1
)
6880 && (HWI_COMPUTABLE_MODE_P (mode
)
6881 || INTVAL (op1
) > 0))
6883 x
= simplify_and_const_int (x
, mode
, op0
, INTVAL (op1
));
6884 if (GET_CODE (x
) != AND
)
6891 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6892 apply the distributive law and then the inverse distributive
6893 law to see if things simplify. */
6894 if (GET_CODE (op0
) == IOR
|| GET_CODE (op0
) == XOR
)
6896 rtx result
= distribute_and_simplify_rtx (x
, 0);
6900 if (GET_CODE (op1
) == IOR
|| GET_CODE (op1
) == XOR
)
6902 rtx result
= distribute_and_simplify_rtx (x
, 1);
6909 /* If we have (ior (and A B) C), apply the distributive law and then
6910 the inverse distributive law to see if things simplify. */
6912 if (GET_CODE (op0
) == AND
)
6914 rtx result
= distribute_and_simplify_rtx (x
, 0);
6919 if (GET_CODE (op1
) == AND
)
6921 rtx result
= distribute_and_simplify_rtx (x
, 1);
6934 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6935 operations" because they can be replaced with two more basic operations.
6936 ZERO_EXTEND is also considered "compound" because it can be replaced with
6937 an AND operation, which is simpler, though only one operation.
6939 The function expand_compound_operation is called with an rtx expression
6940 and will convert it to the appropriate shifts and AND operations,
6941 simplifying at each stage.
6943 The function make_compound_operation is called to convert an expression
6944 consisting of shifts and ANDs into the equivalent compound expression.
6945 It is the inverse of this function, loosely speaking. */
6948 expand_compound_operation (rtx x
)
6950 unsigned HOST_WIDE_INT pos
= 0, len
;
6952 unsigned int modewidth
;
6955 switch (GET_CODE (x
))
6961 /* We can't necessarily use a const_int for a multiword mode;
6962 it depends on implicitly extending the value.
6963 Since we don't know the right way to extend it,
6964 we can't tell whether the implicit way is right.
6966 Even for a mode that is no wider than a const_int,
6967 we can't win, because we need to sign extend one of its bits through
6968 the rest of it, and we don't know which bit. */
6969 if (CONST_INT_P (XEXP (x
, 0)))
6972 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6973 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6974 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6975 reloaded. If not for that, MEM's would very rarely be safe.
6977 Reject MODEs bigger than a word, because we might not be able
6978 to reference a two-register group starting with an arbitrary register
6979 (and currently gen_lowpart might crash for a SUBREG). */
6981 if (GET_MODE_SIZE (GET_MODE (XEXP (x
, 0))) > UNITS_PER_WORD
)
6984 /* Reject MODEs that aren't scalar integers because turning vector
6985 or complex modes into shifts causes problems. */
6987 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
6990 len
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
6991 /* If the inner object has VOIDmode (the only way this can happen
6992 is if it is an ASM_OPERANDS), we can't do anything since we don't
6993 know how much masking to do. */
7005 /* If the operand is a CLOBBER, just return it. */
7006 if (GET_CODE (XEXP (x
, 0)) == CLOBBER
)
7009 if (!CONST_INT_P (XEXP (x
, 1))
7010 || !CONST_INT_P (XEXP (x
, 2))
7011 || GET_MODE (XEXP (x
, 0)) == VOIDmode
)
7014 /* Reject MODEs that aren't scalar integers because turning vector
7015 or complex modes into shifts causes problems. */
7017 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x
, 0))))
7020 len
= INTVAL (XEXP (x
, 1));
7021 pos
= INTVAL (XEXP (x
, 2));
7023 /* This should stay within the object being extracted, fail otherwise. */
7024 if (len
+ pos
> GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))))
7027 if (BITS_BIG_ENDIAN
)
7028 pos
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0))) - len
- pos
;
7035 /* Convert sign extension to zero extension, if we know that the high
7036 bit is not set, as this is easier to optimize. It will be converted
7037 back to cheaper alternative in make_extraction. */
7038 if (GET_CODE (x
) == SIGN_EXTEND
7039 && (HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7040 && ((nonzero_bits (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
7041 & ~(((unsigned HOST_WIDE_INT
)
7042 GET_MODE_MASK (GET_MODE (XEXP (x
, 0))))
7046 machine_mode mode
= GET_MODE (x
);
7047 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, XEXP (x
, 0));
7048 rtx temp2
= expand_compound_operation (temp
);
7050 /* Make sure this is a profitable operation. */
7051 if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7052 > set_src_cost (temp2
, mode
, optimize_this_for_speed_p
))
7054 else if (set_src_cost (x
, mode
, optimize_this_for_speed_p
)
7055 > set_src_cost (temp
, mode
, optimize_this_for_speed_p
))
7061 /* We can optimize some special cases of ZERO_EXTEND. */
7062 if (GET_CODE (x
) == ZERO_EXTEND
)
7064 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7065 know that the last value didn't have any inappropriate bits
7067 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7068 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7069 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7070 && (nonzero_bits (XEXP (XEXP (x
, 0), 0), GET_MODE (x
))
7071 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7072 return XEXP (XEXP (x
, 0), 0);
7074 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7075 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7076 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7077 && subreg_lowpart_p (XEXP (x
, 0))
7078 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
))
7079 && (nonzero_bits (SUBREG_REG (XEXP (x
, 0)), GET_MODE (x
))
7080 & ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7081 return SUBREG_REG (XEXP (x
, 0));
7083 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7084 is a comparison and STORE_FLAG_VALUE permits. This is like
7085 the first case, but it works even when GET_MODE (x) is larger
7086 than HOST_WIDE_INT. */
7087 if (GET_CODE (XEXP (x
, 0)) == TRUNCATE
7088 && GET_MODE (XEXP (XEXP (x
, 0), 0)) == GET_MODE (x
)
7089 && COMPARISON_P (XEXP (XEXP (x
, 0), 0))
7090 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7091 <= HOST_BITS_PER_WIDE_INT
)
7092 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7093 return XEXP (XEXP (x
, 0), 0);
7095 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7096 if (GET_CODE (XEXP (x
, 0)) == SUBREG
7097 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == GET_MODE (x
)
7098 && subreg_lowpart_p (XEXP (x
, 0))
7099 && COMPARISON_P (SUBREG_REG (XEXP (x
, 0)))
7100 && (GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)))
7101 <= HOST_BITS_PER_WIDE_INT
)
7102 && (STORE_FLAG_VALUE
& ~GET_MODE_MASK (GET_MODE (XEXP (x
, 0)))) == 0)
7103 return SUBREG_REG (XEXP (x
, 0));
7107 /* If we reach here, we want to return a pair of shifts. The inner
7108 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7109 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7110 logical depending on the value of UNSIGNEDP.
7112 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7113 converted into an AND of a shift.
7115 We must check for the case where the left shift would have a negative
7116 count. This can happen in a case like (x >> 31) & 255 on machines
7117 that can't shift by a constant. On those machines, we would first
7118 combine the shift with the AND to produce a variable-position
7119 extraction. Then the constant of 31 would be substituted in
7120 to produce such a position. */
7122 modewidth
= GET_MODE_PRECISION (GET_MODE (x
));
7123 if (modewidth
>= pos
+ len
)
7125 machine_mode mode
= GET_MODE (x
);
7126 tem
= gen_lowpart (mode
, XEXP (x
, 0));
7127 if (!tem
|| GET_CODE (tem
) == CLOBBER
)
7129 tem
= simplify_shift_const (NULL_RTX
, ASHIFT
, mode
,
7130 tem
, modewidth
- pos
- len
);
7131 tem
= simplify_shift_const (NULL_RTX
, unsignedp
? LSHIFTRT
: ASHIFTRT
,
7132 mode
, tem
, modewidth
- len
);
7134 else if (unsignedp
&& len
< HOST_BITS_PER_WIDE_INT
)
7135 tem
= simplify_and_const_int (NULL_RTX
, GET_MODE (x
),
7136 simplify_shift_const (NULL_RTX
, LSHIFTRT
,
7139 (HOST_WIDE_INT_1U
<< len
) - 1);
7141 /* Any other cases we can't handle. */
7144 /* If we couldn't do this for some reason, return the original
7146 if (GET_CODE (tem
) == CLOBBER
)
7152 /* X is a SET which contains an assignment of one object into
7153 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7154 or certain SUBREGS). If possible, convert it into a series of
7157 We half-heartedly support variable positions, but do not at all
7158 support variable lengths. */
7161 expand_field_assignment (const_rtx x
)
7164 rtx pos
; /* Always counts from low bit. */
7166 rtx mask
, cleared
, masked
;
7167 machine_mode compute_mode
;
7169 /* Loop until we find something we can't simplify. */
7172 if (GET_CODE (SET_DEST (x
)) == STRICT_LOW_PART
7173 && GET_CODE (XEXP (SET_DEST (x
), 0)) == SUBREG
)
7175 inner
= SUBREG_REG (XEXP (SET_DEST (x
), 0));
7176 len
= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x
), 0)));
7177 pos
= GEN_INT (subreg_lsb (XEXP (SET_DEST (x
), 0)));
7179 else if (GET_CODE (SET_DEST (x
)) == ZERO_EXTRACT
7180 && CONST_INT_P (XEXP (SET_DEST (x
), 1)))
7182 inner
= XEXP (SET_DEST (x
), 0);
7183 len
= INTVAL (XEXP (SET_DEST (x
), 1));
7184 pos
= XEXP (SET_DEST (x
), 2);
7186 /* A constant position should stay within the width of INNER. */
7187 if (CONST_INT_P (pos
)
7188 && INTVAL (pos
) + len
> GET_MODE_PRECISION (GET_MODE (inner
)))
7191 if (BITS_BIG_ENDIAN
)
7193 if (CONST_INT_P (pos
))
7194 pos
= GEN_INT (GET_MODE_PRECISION (GET_MODE (inner
)) - len
7196 else if (GET_CODE (pos
) == MINUS
7197 && CONST_INT_P (XEXP (pos
, 1))
7198 && (INTVAL (XEXP (pos
, 1))
7199 == GET_MODE_PRECISION (GET_MODE (inner
)) - len
))
7200 /* If position is ADJUST - X, new position is X. */
7201 pos
= XEXP (pos
, 0);
7204 HOST_WIDE_INT prec
= GET_MODE_PRECISION (GET_MODE (inner
));
7205 pos
= simplify_gen_binary (MINUS
, GET_MODE (pos
),
7206 gen_int_mode (prec
- len
,
7213 /* A SUBREG between two modes that occupy the same numbers of words
7214 can be done by moving the SUBREG to the source. */
7215 else if (GET_CODE (SET_DEST (x
)) == SUBREG
7216 /* We need SUBREGs to compute nonzero_bits properly. */
7217 && nonzero_sign_valid
7218 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x
)))
7219 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
7220 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x
))))
7221 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)))
7223 x
= gen_rtx_SET (SUBREG_REG (SET_DEST (x
)),
7225 (GET_MODE (SUBREG_REG (SET_DEST (x
))),
7232 while (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7233 inner
= SUBREG_REG (inner
);
7235 compute_mode
= GET_MODE (inner
);
7237 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7238 if (! SCALAR_INT_MODE_P (compute_mode
))
7242 /* Don't do anything for vector or complex integral types. */
7243 if (! FLOAT_MODE_P (compute_mode
))
7246 /* Try to find an integral mode to pun with. */
7247 imode
= mode_for_size (GET_MODE_BITSIZE (compute_mode
), MODE_INT
, 0);
7248 if (imode
== BLKmode
)
7251 compute_mode
= imode
;
7252 inner
= gen_lowpart (imode
, inner
);
7255 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7256 if (len
>= HOST_BITS_PER_WIDE_INT
)
7259 /* Don't try to compute in too wide unsupported modes. */
7260 if (!targetm
.scalar_mode_supported_p (compute_mode
))
7263 /* Now compute the equivalent expression. Make a copy of INNER
7264 for the SET_DEST in case it is a MEM into which we will substitute;
7265 we don't want shared RTL in that case. */
7266 mask
= gen_int_mode ((HOST_WIDE_INT_1U
<< len
) - 1,
7268 cleared
= simplify_gen_binary (AND
, compute_mode
,
7269 simplify_gen_unary (NOT
, compute_mode
,
7270 simplify_gen_binary (ASHIFT
,
7275 masked
= simplify_gen_binary (ASHIFT
, compute_mode
,
7276 simplify_gen_binary (
7278 gen_lowpart (compute_mode
, SET_SRC (x
)),
7282 x
= gen_rtx_SET (copy_rtx (inner
),
7283 simplify_gen_binary (IOR
, compute_mode
,
7290 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7291 it is an RTX that represents the (variable) starting position; otherwise,
7292 POS is the (constant) starting bit position. Both are counted from the LSB.
7294 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7296 IN_DEST is nonzero if this is a reference in the destination of a SET.
7297 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7298 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7301 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7302 ZERO_EXTRACT should be built even for bits starting at bit 0.
7304 MODE is the desired mode of the result (if IN_DEST == 0).
7306 The result is an RTX for the extraction or NULL_RTX if the target
7310 make_extraction (machine_mode mode
, rtx inner
, HOST_WIDE_INT pos
,
7311 rtx pos_rtx
, unsigned HOST_WIDE_INT len
, int unsignedp
,
7312 int in_dest
, int in_compare
)
7314 /* This mode describes the size of the storage area
7315 to fetch the overall value from. Within that, we
7316 ignore the POS lowest bits, etc. */
7317 machine_mode is_mode
= GET_MODE (inner
);
7318 machine_mode inner_mode
;
7319 machine_mode wanted_inner_mode
;
7320 machine_mode wanted_inner_reg_mode
= word_mode
;
7321 machine_mode pos_mode
= word_mode
;
7322 machine_mode extraction_mode
= word_mode
;
7323 machine_mode tmode
= mode_for_size (len
, MODE_INT
, 1);
7325 rtx orig_pos_rtx
= pos_rtx
;
7326 HOST_WIDE_INT orig_pos
;
7328 if (pos_rtx
&& CONST_INT_P (pos_rtx
))
7329 pos
= INTVAL (pos_rtx
), pos_rtx
= 0;
7331 if (GET_CODE (inner
) == SUBREG
&& subreg_lowpart_p (inner
))
7333 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7334 consider just the QI as the memory to extract from.
7335 The subreg adds or removes high bits; its mode is
7336 irrelevant to the meaning of this extraction,
7337 since POS and LEN count from the lsb. */
7338 if (MEM_P (SUBREG_REG (inner
)))
7339 is_mode
= GET_MODE (SUBREG_REG (inner
));
7340 inner
= SUBREG_REG (inner
);
7342 else if (GET_CODE (inner
) == ASHIFT
7343 && CONST_INT_P (XEXP (inner
, 1))
7344 && pos_rtx
== 0 && pos
== 0
7345 && len
> UINTVAL (XEXP (inner
, 1)))
7347 /* We're extracting the least significant bits of an rtx
7348 (ashift X (const_int C)), where LEN > C. Extract the
7349 least significant (LEN - C) bits of X, giving an rtx
7350 whose mode is MODE, then shift it left C times. */
7351 new_rtx
= make_extraction (mode
, XEXP (inner
, 0),
7352 0, 0, len
- INTVAL (XEXP (inner
, 1)),
7353 unsignedp
, in_dest
, in_compare
);
7355 return gen_rtx_ASHIFT (mode
, new_rtx
, XEXP (inner
, 1));
7357 else if (GET_CODE (inner
) == TRUNCATE
)
7358 inner
= XEXP (inner
, 0);
7360 inner_mode
= GET_MODE (inner
);
7362 /* See if this can be done without an extraction. We never can if the
7363 width of the field is not the same as that of some integer mode. For
7364 registers, we can only avoid the extraction if the position is at the
7365 low-order bit and this is either not in the destination or we have the
7366 appropriate STRICT_LOW_PART operation available.
7368 For MEM, we can avoid an extract if the field starts on an appropriate
7369 boundary and we can change the mode of the memory reference. */
7371 if (tmode
!= BLKmode
7372 && ((pos_rtx
== 0 && (pos
% BITS_PER_WORD
) == 0
7374 && (inner_mode
== tmode
7376 || TRULY_NOOP_TRUNCATION_MODES_P (tmode
, inner_mode
)
7377 || reg_truncated_to_mode (tmode
, inner
))
7380 && have_insn_for (STRICT_LOW_PART
, tmode
))))
7381 || (MEM_P (inner
) && pos_rtx
== 0
7383 % (STRICT_ALIGNMENT
? GET_MODE_ALIGNMENT (tmode
)
7384 : BITS_PER_UNIT
)) == 0
7385 /* We can't do this if we are widening INNER_MODE (it
7386 may not be aligned, for one thing). */
7387 && GET_MODE_PRECISION (inner_mode
) >= GET_MODE_PRECISION (tmode
)
7388 && (inner_mode
== tmode
7389 || (! mode_dependent_address_p (XEXP (inner
, 0),
7390 MEM_ADDR_SPACE (inner
))
7391 && ! MEM_VOLATILE_P (inner
))))))
7393 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7394 field. If the original and current mode are the same, we need not
7395 adjust the offset. Otherwise, we do if bytes big endian.
7397 If INNER is not a MEM, get a piece consisting of just the field
7398 of interest (in this case POS % BITS_PER_WORD must be 0). */
7402 HOST_WIDE_INT offset
;
7404 /* POS counts from lsb, but make OFFSET count in memory order. */
7405 if (BYTES_BIG_ENDIAN
)
7406 offset
= (GET_MODE_PRECISION (is_mode
) - len
- pos
) / BITS_PER_UNIT
;
7408 offset
= pos
/ BITS_PER_UNIT
;
7410 new_rtx
= adjust_address_nv (inner
, tmode
, offset
);
7412 else if (REG_P (inner
))
7414 if (tmode
!= inner_mode
)
7416 /* We can't call gen_lowpart in a DEST since we
7417 always want a SUBREG (see below) and it would sometimes
7418 return a new hard register. */
7421 HOST_WIDE_INT final_word
= pos
/ BITS_PER_WORD
;
7423 if (WORDS_BIG_ENDIAN
7424 && GET_MODE_SIZE (inner_mode
) > UNITS_PER_WORD
)
7425 final_word
= ((GET_MODE_SIZE (inner_mode
)
7426 - GET_MODE_SIZE (tmode
))
7427 / UNITS_PER_WORD
) - final_word
;
7429 final_word
*= UNITS_PER_WORD
;
7430 if (BYTES_BIG_ENDIAN
&&
7431 GET_MODE_SIZE (inner_mode
) > GET_MODE_SIZE (tmode
))
7432 final_word
+= (GET_MODE_SIZE (inner_mode
)
7433 - GET_MODE_SIZE (tmode
)) % UNITS_PER_WORD
;
7435 /* Avoid creating invalid subregs, for example when
7436 simplifying (x>>32)&255. */
7437 if (!validate_subreg (tmode
, inner_mode
, inner
, final_word
))
7440 new_rtx
= gen_rtx_SUBREG (tmode
, inner
, final_word
);
7443 new_rtx
= gen_lowpart (tmode
, inner
);
7449 new_rtx
= force_to_mode (inner
, tmode
,
7450 len
>= HOST_BITS_PER_WIDE_INT
7452 : (HOST_WIDE_INT_1U
<< len
) - 1,
7455 /* If this extraction is going into the destination of a SET,
7456 make a STRICT_LOW_PART unless we made a MEM. */
7459 return (MEM_P (new_rtx
) ? new_rtx
7460 : (GET_CODE (new_rtx
) != SUBREG
7461 ? gen_rtx_CLOBBER (tmode
, const0_rtx
)
7462 : gen_rtx_STRICT_LOW_PART (VOIDmode
, new_rtx
)));
7467 if (CONST_SCALAR_INT_P (new_rtx
))
7468 return simplify_unary_operation (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7469 mode
, new_rtx
, tmode
);
7471 /* If we know that no extraneous bits are set, and that the high
7472 bit is not set, convert the extraction to the cheaper of
7473 sign and zero extension, that are equivalent in these cases. */
7474 if (flag_expensive_optimizations
7475 && (HWI_COMPUTABLE_MODE_P (tmode
)
7476 && ((nonzero_bits (new_rtx
, tmode
)
7477 & ~(((unsigned HOST_WIDE_INT
)GET_MODE_MASK (tmode
)) >> 1))
7480 rtx temp
= gen_rtx_ZERO_EXTEND (mode
, new_rtx
);
7481 rtx temp1
= gen_rtx_SIGN_EXTEND (mode
, new_rtx
);
7483 /* Prefer ZERO_EXTENSION, since it gives more information to
7485 if (set_src_cost (temp
, mode
, optimize_this_for_speed_p
)
7486 <= set_src_cost (temp1
, mode
, optimize_this_for_speed_p
))
7491 /* Otherwise, sign- or zero-extend unless we already are in the
7494 return (gen_rtx_fmt_e (unsignedp
? ZERO_EXTEND
: SIGN_EXTEND
,
7498 /* Unless this is a COMPARE or we have a funny memory reference,
7499 don't do anything with zero-extending field extracts starting at
7500 the low-order bit since they are simple AND operations. */
7501 if (pos_rtx
== 0 && pos
== 0 && ! in_dest
7502 && ! in_compare
&& unsignedp
)
7505 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7506 if the position is not a constant and the length is not 1. In all
7507 other cases, we would only be going outside our object in cases when
7508 an original shift would have been undefined. */
7510 && ((pos_rtx
== 0 && pos
+ len
> GET_MODE_PRECISION (is_mode
))
7511 || (pos_rtx
!= 0 && len
!= 1)))
7514 enum extraction_pattern pattern
= (in_dest
? EP_insv
7515 : unsignedp
? EP_extzv
: EP_extv
);
7517 /* If INNER is not from memory, we want it to have the mode of a register
7518 extraction pattern's structure operand, or word_mode if there is no
7519 such pattern. The same applies to extraction_mode and pos_mode
7520 and their respective operands.
7522 For memory, assume that the desired extraction_mode and pos_mode
7523 are the same as for a register operation, since at present we don't
7524 have named patterns for aligned memory structures. */
7525 struct extraction_insn insn
;
7526 if (get_best_reg_extraction_insn (&insn
, pattern
,
7527 GET_MODE_BITSIZE (inner_mode
), mode
))
7529 wanted_inner_reg_mode
= insn
.struct_mode
;
7530 pos_mode
= insn
.pos_mode
;
7531 extraction_mode
= insn
.field_mode
;
7534 /* Never narrow an object, since that might not be safe. */
7536 if (mode
!= VOIDmode
7537 && GET_MODE_SIZE (extraction_mode
) < GET_MODE_SIZE (mode
))
7538 extraction_mode
= mode
;
7541 wanted_inner_mode
= wanted_inner_reg_mode
;
7544 /* Be careful not to go beyond the extracted object and maintain the
7545 natural alignment of the memory. */
7546 wanted_inner_mode
= smallest_mode_for_size (len
, MODE_INT
);
7547 while (pos
% GET_MODE_BITSIZE (wanted_inner_mode
) + len
7548 > GET_MODE_BITSIZE (wanted_inner_mode
))
7550 wanted_inner_mode
= GET_MODE_WIDER_MODE (wanted_inner_mode
);
7551 gcc_assert (wanted_inner_mode
!= VOIDmode
);
7557 if (BITS_BIG_ENDIAN
)
7559 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7560 BITS_BIG_ENDIAN style. If position is constant, compute new
7561 position. Otherwise, build subtraction.
7562 Note that POS is relative to the mode of the original argument.
7563 If it's a MEM we need to recompute POS relative to that.
7564 However, if we're extracting from (or inserting into) a register,
7565 we want to recompute POS relative to wanted_inner_mode. */
7566 int width
= (MEM_P (inner
)
7567 ? GET_MODE_BITSIZE (is_mode
)
7568 : GET_MODE_BITSIZE (wanted_inner_mode
));
7571 pos
= width
- len
- pos
;
7574 = gen_rtx_MINUS (GET_MODE (pos_rtx
),
7575 gen_int_mode (width
- len
, GET_MODE (pos_rtx
)),
7577 /* POS may be less than 0 now, but we check for that below.
7578 Note that it can only be less than 0 if !MEM_P (inner). */
7581 /* If INNER has a wider mode, and this is a constant extraction, try to
7582 make it smaller and adjust the byte to point to the byte containing
7584 if (wanted_inner_mode
!= VOIDmode
7585 && inner_mode
!= wanted_inner_mode
7587 && GET_MODE_SIZE (wanted_inner_mode
) < GET_MODE_SIZE (is_mode
)
7589 && ! mode_dependent_address_p (XEXP (inner
, 0), MEM_ADDR_SPACE (inner
))
7590 && ! MEM_VOLATILE_P (inner
))
7594 /* The computations below will be correct if the machine is big
7595 endian in both bits and bytes or little endian in bits and bytes.
7596 If it is mixed, we must adjust. */
7598 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7599 adjust OFFSET to compensate. */
7600 if (BYTES_BIG_ENDIAN
7601 && GET_MODE_SIZE (inner_mode
) < GET_MODE_SIZE (is_mode
))
7602 offset
-= GET_MODE_SIZE (is_mode
) - GET_MODE_SIZE (inner_mode
);
7604 /* We can now move to the desired byte. */
7605 offset
+= (pos
/ GET_MODE_BITSIZE (wanted_inner_mode
))
7606 * GET_MODE_SIZE (wanted_inner_mode
);
7607 pos
%= GET_MODE_BITSIZE (wanted_inner_mode
);
7609 if (BYTES_BIG_ENDIAN
!= BITS_BIG_ENDIAN
7610 && is_mode
!= wanted_inner_mode
)
7611 offset
= (GET_MODE_SIZE (is_mode
)
7612 - GET_MODE_SIZE (wanted_inner_mode
) - offset
);
7614 inner
= adjust_address_nv (inner
, wanted_inner_mode
, offset
);
7617 /* If INNER is not memory, get it into the proper mode. If we are changing
7618 its mode, POS must be a constant and smaller than the size of the new
7620 else if (!MEM_P (inner
))
7622 /* On the LHS, don't create paradoxical subregs implicitely truncating
7623 the register unless TRULY_NOOP_TRUNCATION. */
7625 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner
),
7629 if (GET_MODE (inner
) != wanted_inner_mode
7631 || orig_pos
+ len
> GET_MODE_BITSIZE (wanted_inner_mode
)))
7637 inner
= force_to_mode (inner
, wanted_inner_mode
,
7639 || len
+ orig_pos
>= HOST_BITS_PER_WIDE_INT
7641 : (((HOST_WIDE_INT_1U
<< len
) - 1)
7646 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7647 have to zero extend. Otherwise, we can just use a SUBREG. */
7649 && GET_MODE_SIZE (pos_mode
) > GET_MODE_SIZE (GET_MODE (pos_rtx
)))
7651 rtx temp
= simplify_gen_unary (ZERO_EXTEND
, pos_mode
, pos_rtx
,
7652 GET_MODE (pos_rtx
));
7654 /* If we know that no extraneous bits are set, and that the high
7655 bit is not set, convert extraction to cheaper one - either
7656 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7658 if (flag_expensive_optimizations
7659 && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx
))
7660 && ((nonzero_bits (pos_rtx
, GET_MODE (pos_rtx
))
7661 & ~(((unsigned HOST_WIDE_INT
)
7662 GET_MODE_MASK (GET_MODE (pos_rtx
)))
7666 rtx temp1
= simplify_gen_unary (SIGN_EXTEND
, pos_mode
, pos_rtx
,
7667 GET_MODE (pos_rtx
));
7669 /* Prefer ZERO_EXTENSION, since it gives more information to
7671 if (set_src_cost (temp1
, pos_mode
, optimize_this_for_speed_p
)
7672 < set_src_cost (temp
, pos_mode
, optimize_this_for_speed_p
))
7678 /* Make POS_RTX unless we already have it and it is correct. If we don't
7679 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7681 if (pos_rtx
== 0 && orig_pos_rtx
!= 0 && INTVAL (orig_pos_rtx
) == pos
)
7682 pos_rtx
= orig_pos_rtx
;
7684 else if (pos_rtx
== 0)
7685 pos_rtx
= GEN_INT (pos
);
7687 /* Make the required operation. See if we can use existing rtx. */
7688 new_rtx
= gen_rtx_fmt_eee (unsignedp
? ZERO_EXTRACT
: SIGN_EXTRACT
,
7689 extraction_mode
, inner
, GEN_INT (len
), pos_rtx
);
7691 new_rtx
= gen_lowpart (mode
, new_rtx
);
7696 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7697 with any other operations in X. Return X without that shift if so. */
7700 extract_left_shift (rtx x
, int count
)
7702 enum rtx_code code
= GET_CODE (x
);
7703 machine_mode mode
= GET_MODE (x
);
7709 /* This is the shift itself. If it is wide enough, we will return
7710 either the value being shifted if the shift count is equal to
7711 COUNT or a shift for the difference. */
7712 if (CONST_INT_P (XEXP (x
, 1))
7713 && INTVAL (XEXP (x
, 1)) >= count
)
7714 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (x
, 0),
7715 INTVAL (XEXP (x
, 1)) - count
);
7719 if ((tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7720 return simplify_gen_unary (code
, mode
, tem
, mode
);
7724 case PLUS
: case IOR
: case XOR
: case AND
:
7725 /* If we can safely shift this constant and we find the inner shift,
7726 make a new operation. */
7727 if (CONST_INT_P (XEXP (x
, 1))
7728 && (UINTVAL (XEXP (x
, 1))
7729 & (((HOST_WIDE_INT_1U
<< count
)) - 1)) == 0
7730 && (tem
= extract_left_shift (XEXP (x
, 0), count
)) != 0)
7732 HOST_WIDE_INT val
= INTVAL (XEXP (x
, 1)) >> count
;
7733 return simplify_gen_binary (code
, mode
, tem
,
7734 gen_int_mode (val
, mode
));
7745 /* Look at the expression rooted at X. Look for expressions
7746 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7747 Form these expressions.
7749 Return the new rtx, usually just X.
7751 Also, for machines like the VAX that don't have logical shift insns,
7752 try to convert logical to arithmetic shift operations in cases where
7753 they are equivalent. This undoes the canonicalizations to logical
7754 shifts done elsewhere.
7756 We try, as much as possible, to re-use rtl expressions to save memory.
7758 IN_CODE says what kind of expression we are processing. Normally, it is
7759 SET. In a memory address it is MEM. When processing the arguments of
7760 a comparison or a COMPARE against zero, it is COMPARE. */
7763 make_compound_operation (rtx x
, enum rtx_code in_code
)
7765 enum rtx_code code
= GET_CODE (x
);
7766 machine_mode mode
= GET_MODE (x
);
7767 int mode_width
= GET_MODE_PRECISION (mode
);
7769 enum rtx_code next_code
;
7775 /* PR rtl-optimization/70944. */
7776 if (VECTOR_MODE_P (mode
))
7779 /* Select the code to be used in recursive calls. Once we are inside an
7780 address, we stay there. If we have a comparison, set to COMPARE,
7781 but once inside, go back to our default of SET. */
7783 next_code
= (code
== MEM
? MEM
7784 : ((code
== COMPARE
|| COMPARISON_P (x
))
7785 && XEXP (x
, 1) == const0_rtx
) ? COMPARE
7786 : in_code
== COMPARE
? SET
: in_code
);
7788 /* Process depending on the code of this operation. If NEW is set
7789 nonzero, it will be returned. */
7794 /* Convert shifts by constants into multiplications if inside
7796 if (in_code
== MEM
&& CONST_INT_P (XEXP (x
, 1))
7797 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
7798 && INTVAL (XEXP (x
, 1)) >= 0
7799 && SCALAR_INT_MODE_P (mode
))
7801 HOST_WIDE_INT count
= INTVAL (XEXP (x
, 1));
7802 HOST_WIDE_INT multval
= HOST_WIDE_INT_1
<< count
;
7804 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7805 if (GET_CODE (new_rtx
) == NEG
)
7807 new_rtx
= XEXP (new_rtx
, 0);
7810 multval
= trunc_int_for_mode (multval
, mode
);
7811 new_rtx
= gen_rtx_MULT (mode
, new_rtx
, gen_int_mode (multval
, mode
));
7818 lhs
= make_compound_operation (lhs
, next_code
);
7819 rhs
= make_compound_operation (rhs
, next_code
);
7820 if (GET_CODE (lhs
) == MULT
&& GET_CODE (XEXP (lhs
, 0)) == NEG
7821 && SCALAR_INT_MODE_P (mode
))
7823 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (lhs
, 0), 0),
7825 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7827 else if (GET_CODE (lhs
) == MULT
7828 && (CONST_INT_P (XEXP (lhs
, 1)) && INTVAL (XEXP (lhs
, 1)) < 0))
7830 tem
= simplify_gen_binary (MULT
, mode
, XEXP (lhs
, 0),
7831 simplify_gen_unary (NEG
, mode
,
7834 new_rtx
= simplify_gen_binary (MINUS
, mode
, rhs
, tem
);
7838 SUBST (XEXP (x
, 0), lhs
);
7839 SUBST (XEXP (x
, 1), rhs
);
7842 x
= gen_lowpart (mode
, new_rtx
);
7848 lhs
= make_compound_operation (lhs
, next_code
);
7849 rhs
= make_compound_operation (rhs
, next_code
);
7850 if (GET_CODE (rhs
) == MULT
&& GET_CODE (XEXP (rhs
, 0)) == NEG
7851 && SCALAR_INT_MODE_P (mode
))
7853 tem
= simplify_gen_binary (MULT
, mode
, XEXP (XEXP (rhs
, 0), 0),
7855 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7857 else if (GET_CODE (rhs
) == MULT
7858 && (CONST_INT_P (XEXP (rhs
, 1)) && INTVAL (XEXP (rhs
, 1)) < 0))
7860 tem
= simplify_gen_binary (MULT
, mode
, XEXP (rhs
, 0),
7861 simplify_gen_unary (NEG
, mode
,
7864 new_rtx
= simplify_gen_binary (PLUS
, mode
, tem
, lhs
);
7868 SUBST (XEXP (x
, 0), lhs
);
7869 SUBST (XEXP (x
, 1), rhs
);
7872 return gen_lowpart (mode
, new_rtx
);
7875 /* If the second operand is not a constant, we can't do anything
7877 if (!CONST_INT_P (XEXP (x
, 1)))
7880 /* If the constant is a power of two minus one and the first operand
7881 is a logical right shift, make an extraction. */
7882 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7883 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7885 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7886 new_rtx
= make_extraction (mode
, new_rtx
, 0, XEXP (XEXP (x
, 0), 1), i
, 1,
7887 0, in_code
== COMPARE
);
7890 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7891 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
7892 && subreg_lowpart_p (XEXP (x
, 0))
7893 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == LSHIFTRT
7894 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7896 rtx inner_x0
= SUBREG_REG (XEXP (x
, 0));
7897 machine_mode inner_mode
= GET_MODE (inner_x0
);
7898 new_rtx
= make_compound_operation (XEXP (inner_x0
, 0), next_code
);
7899 new_rtx
= make_extraction (inner_mode
, new_rtx
, 0,
7901 i
, 1, 0, in_code
== COMPARE
);
7905 /* If we narrowed the mode when dropping the subreg, then
7906 we must zero-extend to keep the semantics of the AND. */
7907 if (GET_MODE_SIZE (inner_mode
) >= GET_MODE_SIZE (mode
))
7909 else if (SCALAR_INT_MODE_P (inner_mode
))
7910 new_rtx
= simplify_gen_unary (ZERO_EXTEND
, mode
,
7911 new_rtx
, inner_mode
);
7916 /* If that didn't give anything, see if the AND simplifies on
7918 if (!new_rtx
&& i
>= 0)
7920 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
7921 new_rtx
= make_extraction (mode
, new_rtx
, 0, NULL_RTX
, i
, 1,
7922 0, in_code
== COMPARE
);
7925 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7926 else if ((GET_CODE (XEXP (x
, 0)) == XOR
7927 || GET_CODE (XEXP (x
, 0)) == IOR
)
7928 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == LSHIFTRT
7929 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == LSHIFTRT
7930 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7932 /* Apply the distributive law, and then try to make extractions. */
7933 new_rtx
= gen_rtx_fmt_ee (GET_CODE (XEXP (x
, 0)), mode
,
7934 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 0),
7936 gen_rtx_AND (mode
, XEXP (XEXP (x
, 0), 1),
7938 new_rtx
= make_compound_operation (new_rtx
, in_code
);
7941 /* If we are have (and (rotate X C) M) and C is larger than the number
7942 of bits in M, this is an extraction. */
7944 else if (GET_CODE (XEXP (x
, 0)) == ROTATE
7945 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7946 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0
7947 && i
<= INTVAL (XEXP (XEXP (x
, 0), 1)))
7949 new_rtx
= make_compound_operation (XEXP (XEXP (x
, 0), 0), next_code
);
7950 new_rtx
= make_extraction (mode
, new_rtx
,
7951 (GET_MODE_PRECISION (mode
)
7952 - INTVAL (XEXP (XEXP (x
, 0), 1))),
7953 NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7956 /* On machines without logical shifts, if the operand of the AND is
7957 a logical shift and our mask turns off all the propagated sign
7958 bits, we can replace the logical shift with an arithmetic shift. */
7959 else if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
7960 && !have_insn_for (LSHIFTRT
, mode
)
7961 && have_insn_for (ASHIFTRT
, mode
)
7962 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
7963 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
7964 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
7965 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
7967 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
7969 mask
>>= INTVAL (XEXP (XEXP (x
, 0), 1));
7970 if ((INTVAL (XEXP (x
, 1)) & ~mask
) == 0)
7972 gen_rtx_ASHIFTRT (mode
,
7973 make_compound_operation
7974 (XEXP (XEXP (x
, 0), 0), next_code
),
7975 XEXP (XEXP (x
, 0), 1)));
7978 /* If the constant is one less than a power of two, this might be
7979 representable by an extraction even if no shift is present.
7980 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7981 we are in a COMPARE. */
7982 else if ((i
= exact_log2 (UINTVAL (XEXP (x
, 1)) + 1)) >= 0)
7983 new_rtx
= make_extraction (mode
,
7984 make_compound_operation (XEXP (x
, 0),
7986 0, NULL_RTX
, i
, 1, 0, in_code
== COMPARE
);
7988 /* If we are in a comparison and this is an AND with a power of two,
7989 convert this into the appropriate bit extract. */
7990 else if (in_code
== COMPARE
7991 && (i
= exact_log2 (UINTVAL (XEXP (x
, 1)))) >= 0)
7992 new_rtx
= make_extraction (mode
,
7993 make_compound_operation (XEXP (x
, 0),
7995 i
, NULL_RTX
, 1, 1, 0, 1);
7997 /* If the one operand is a paradoxical subreg of a register or memory and
7998 the constant (limited to the smaller mode) has only zero bits where
7999 the sub expression has known zero bits, this can be expressed as
8001 else if (GET_CODE (XEXP (x
, 0)) == SUBREG
)
8005 sub
= XEXP (XEXP (x
, 0), 0);
8006 machine_mode sub_mode
= GET_MODE (sub
);
8007 if ((REG_P (sub
) || MEM_P (sub
))
8008 && GET_MODE_PRECISION (sub_mode
) < mode_width
)
8010 unsigned HOST_WIDE_INT mode_mask
= GET_MODE_MASK (sub_mode
);
8011 unsigned HOST_WIDE_INT mask
;
8013 /* original AND constant with all the known zero bits set */
8014 mask
= UINTVAL (XEXP (x
, 1)) | (~nonzero_bits (sub
, sub_mode
));
8015 if ((mask
& mode_mask
) == mode_mask
)
8017 new_rtx
= make_compound_operation (sub
, next_code
);
8018 new_rtx
= make_extraction (mode
, new_rtx
, 0, 0,
8019 GET_MODE_PRECISION (sub_mode
),
8020 1, 0, in_code
== COMPARE
);
8028 /* If the sign bit is known to be zero, replace this with an
8029 arithmetic shift. */
8030 if (have_insn_for (ASHIFTRT
, mode
)
8031 && ! have_insn_for (LSHIFTRT
, mode
)
8032 && mode_width
<= HOST_BITS_PER_WIDE_INT
8033 && (nonzero_bits (XEXP (x
, 0), mode
) & (1 << (mode_width
- 1))) == 0)
8035 new_rtx
= gen_rtx_ASHIFTRT (mode
,
8036 make_compound_operation (XEXP (x
, 0),
8048 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8049 this is a SIGN_EXTRACT. */
8050 if (CONST_INT_P (rhs
)
8051 && GET_CODE (lhs
) == ASHIFT
8052 && CONST_INT_P (XEXP (lhs
, 1))
8053 && INTVAL (rhs
) >= INTVAL (XEXP (lhs
, 1))
8054 && INTVAL (XEXP (lhs
, 1)) >= 0
8055 && INTVAL (rhs
) < mode_width
)
8057 new_rtx
= make_compound_operation (XEXP (lhs
, 0), next_code
);
8058 new_rtx
= make_extraction (mode
, new_rtx
,
8059 INTVAL (rhs
) - INTVAL (XEXP (lhs
, 1)),
8060 NULL_RTX
, mode_width
- INTVAL (rhs
),
8061 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8065 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8066 If so, try to merge the shifts into a SIGN_EXTEND. We could
8067 also do this for some cases of SIGN_EXTRACT, but it doesn't
8068 seem worth the effort; the case checked for occurs on Alpha. */
8071 && ! (GET_CODE (lhs
) == SUBREG
8072 && (OBJECT_P (SUBREG_REG (lhs
))))
8073 && CONST_INT_P (rhs
)
8074 && INTVAL (rhs
) >= 0
8075 && INTVAL (rhs
) < HOST_BITS_PER_WIDE_INT
8076 && INTVAL (rhs
) < mode_width
8077 && (new_rtx
= extract_left_shift (lhs
, INTVAL (rhs
))) != 0)
8078 new_rtx
= make_extraction (mode
, make_compound_operation (new_rtx
, next_code
),
8079 0, NULL_RTX
, mode_width
- INTVAL (rhs
),
8080 code
== LSHIFTRT
, 0, in_code
== COMPARE
);
8085 /* Call ourselves recursively on the inner expression. If we are
8086 narrowing the object and it has a different RTL code from
8087 what it originally did, do this SUBREG as a force_to_mode. */
8089 rtx inner
= SUBREG_REG (x
), simplified
;
8090 enum rtx_code subreg_code
= in_code
;
8092 /* If in_code is COMPARE, it isn't always safe to pass it through
8093 to the recursive make_compound_operation call. */
8094 if (subreg_code
== COMPARE
8095 && (!subreg_lowpart_p (x
)
8096 || GET_CODE (inner
) == SUBREG
8097 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8098 is (const_int 0), rather than
8099 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
8100 || (GET_CODE (inner
) == AND
8101 && CONST_INT_P (XEXP (inner
, 1))
8102 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8103 && exact_log2 (UINTVAL (XEXP (inner
, 1)))
8104 >= GET_MODE_BITSIZE (mode
))))
8107 tem
= make_compound_operation (inner
, subreg_code
);
8110 = simplify_subreg (mode
, tem
, GET_MODE (inner
), SUBREG_BYTE (x
));
8114 if (GET_CODE (tem
) != GET_CODE (inner
)
8115 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (inner
))
8116 && subreg_lowpart_p (x
))
8119 = force_to_mode (tem
, mode
, HOST_WIDE_INT_M1U
, 0);
8121 /* If we have something other than a SUBREG, we might have
8122 done an expansion, so rerun ourselves. */
8123 if (GET_CODE (newer
) != SUBREG
)
8124 newer
= make_compound_operation (newer
, in_code
);
8126 /* force_to_mode can expand compounds. If it just re-expanded the
8127 compound, use gen_lowpart to convert to the desired mode. */
8128 if (rtx_equal_p (newer
, x
)
8129 /* Likewise if it re-expanded the compound only partially.
8130 This happens for SUBREG of ZERO_EXTRACT if they extract
8131 the same number of bits. */
8132 || (GET_CODE (newer
) == SUBREG
8133 && (GET_CODE (SUBREG_REG (newer
)) == LSHIFTRT
8134 || GET_CODE (SUBREG_REG (newer
)) == ASHIFTRT
)
8135 && GET_CODE (inner
) == AND
8136 && rtx_equal_p (SUBREG_REG (newer
), XEXP (inner
, 0))))
8137 return gen_lowpart (GET_MODE (x
), tem
);
8153 x
= gen_lowpart (mode
, new_rtx
);
8154 code
= GET_CODE (x
);
8157 /* Now recursively process each operand of this operation. We need to
8158 handle ZERO_EXTEND specially so that we don't lose track of the
8160 if (GET_CODE (x
) == ZERO_EXTEND
)
8162 new_rtx
= make_compound_operation (XEXP (x
, 0), next_code
);
8163 tem
= simplify_const_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
8164 new_rtx
, GET_MODE (XEXP (x
, 0)));
8167 SUBST (XEXP (x
, 0), new_rtx
);
8171 fmt
= GET_RTX_FORMAT (code
);
8172 for (i
= 0; i
< GET_RTX_LENGTH (code
); i
++)
8175 new_rtx
= make_compound_operation (XEXP (x
, i
), next_code
);
8176 SUBST (XEXP (x
, i
), new_rtx
);
8178 else if (fmt
[i
] == 'E')
8179 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8181 new_rtx
= make_compound_operation (XVECEXP (x
, i
, j
), next_code
);
8182 SUBST (XVECEXP (x
, i
, j
), new_rtx
);
8186 /* If this is a commutative operation, the changes to the operands
8187 may have made it noncanonical. */
8188 if (COMMUTATIVE_ARITH_P (x
)
8189 && swap_commutative_operands_p (XEXP (x
, 0), XEXP (x
, 1)))
8192 SUBST (XEXP (x
, 0), XEXP (x
, 1));
8193 SUBST (XEXP (x
, 1), tem
);
8199 /* Given M see if it is a value that would select a field of bits
8200 within an item, but not the entire word. Return -1 if not.
8201 Otherwise, return the starting position of the field, where 0 is the
8204 *PLEN is set to the length of the field. */
8207 get_pos_from_mask (unsigned HOST_WIDE_INT m
, unsigned HOST_WIDE_INT
*plen
)
8209 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8210 int pos
= m
? ctz_hwi (m
) : -1;
8214 /* Now shift off the low-order zero bits and see if we have a
8215 power of two minus 1. */
8216 len
= exact_log2 ((m
>> pos
) + 1);
8225 /* If X refers to a register that equals REG in value, replace these
8226 references with REG. */
8228 canon_reg_for_combine (rtx x
, rtx reg
)
8235 enum rtx_code code
= GET_CODE (x
);
8236 switch (GET_RTX_CLASS (code
))
8239 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8240 if (op0
!= XEXP (x
, 0))
8241 return simplify_gen_unary (GET_CODE (x
), GET_MODE (x
), op0
,
8246 case RTX_COMM_ARITH
:
8247 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8248 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8249 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8250 return simplify_gen_binary (GET_CODE (x
), GET_MODE (x
), op0
, op1
);
8254 case RTX_COMM_COMPARE
:
8255 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8256 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8257 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8258 return simplify_gen_relational (GET_CODE (x
), GET_MODE (x
),
8259 GET_MODE (op0
), op0
, op1
);
8263 case RTX_BITFIELD_OPS
:
8264 op0
= canon_reg_for_combine (XEXP (x
, 0), reg
);
8265 op1
= canon_reg_for_combine (XEXP (x
, 1), reg
);
8266 op2
= canon_reg_for_combine (XEXP (x
, 2), reg
);
8267 if (op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1) || op2
!= XEXP (x
, 2))
8268 return simplify_gen_ternary (GET_CODE (x
), GET_MODE (x
),
8269 GET_MODE (op0
), op0
, op1
, op2
);
8275 if (rtx_equal_p (get_last_value (reg
), x
)
8276 || rtx_equal_p (reg
, get_last_value (x
)))
8285 fmt
= GET_RTX_FORMAT (code
);
8287 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
8290 rtx op
= canon_reg_for_combine (XEXP (x
, i
), reg
);
8291 if (op
!= XEXP (x
, i
))
8301 else if (fmt
[i
] == 'E')
8304 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
8306 rtx op
= canon_reg_for_combine (XVECEXP (x
, i
, j
), reg
);
8307 if (op
!= XVECEXP (x
, i
, j
))
8314 XVECEXP (x
, i
, j
) = op
;
8325 /* Return X converted to MODE. If the value is already truncated to
8326 MODE we can just return a subreg even though in the general case we
8327 would need an explicit truncation. */
8330 gen_lowpart_or_truncate (machine_mode mode
, rtx x
)
8332 if (!CONST_INT_P (x
)
8333 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
))
8334 && !TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (x
))
8335 && !(REG_P (x
) && reg_truncated_to_mode (mode
, x
)))
8337 /* Bit-cast X into an integer mode. */
8338 if (!SCALAR_INT_MODE_P (GET_MODE (x
)))
8339 x
= gen_lowpart (int_mode_for_mode (GET_MODE (x
)), x
);
8340 x
= simplify_gen_unary (TRUNCATE
, int_mode_for_mode (mode
),
8344 return gen_lowpart (mode
, x
);
8347 /* See if X can be simplified knowing that we will only refer to it in
8348 MODE and will only refer to those bits that are nonzero in MASK.
8349 If other bits are being computed or if masking operations are done
8350 that select a superset of the bits in MASK, they can sometimes be
8353 Return a possibly simplified expression, but always convert X to
8354 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8356 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8357 are all off in X. This is used when X will be complemented, by either
8358 NOT, NEG, or XOR. */
8361 force_to_mode (rtx x
, machine_mode mode
, unsigned HOST_WIDE_INT mask
,
8364 enum rtx_code code
= GET_CODE (x
);
8365 int next_select
= just_select
|| code
== XOR
|| code
== NOT
|| code
== NEG
;
8366 machine_mode op_mode
;
8367 unsigned HOST_WIDE_INT fuller_mask
, nonzero
;
8370 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8371 code below will do the wrong thing since the mode of such an
8372 expression is VOIDmode.
8374 Also do nothing if X is a CLOBBER; this can happen if X was
8375 the return value from a call to gen_lowpart. */
8376 if (code
== CALL
|| code
== ASM_OPERANDS
|| code
== CLOBBER
)
8379 /* We want to perform the operation in its present mode unless we know
8380 that the operation is valid in MODE, in which case we do the operation
8382 op_mode
= ((GET_MODE_CLASS (mode
) == GET_MODE_CLASS (GET_MODE (x
))
8383 && have_insn_for (code
, mode
))
8384 ? mode
: GET_MODE (x
));
8386 /* It is not valid to do a right-shift in a narrower mode
8387 than the one it came in with. */
8388 if ((code
== LSHIFTRT
|| code
== ASHIFTRT
)
8389 && GET_MODE_PRECISION (mode
) < GET_MODE_PRECISION (GET_MODE (x
)))
8390 op_mode
= GET_MODE (x
);
8392 /* Truncate MASK to fit OP_MODE. */
8394 mask
&= GET_MODE_MASK (op_mode
);
8396 /* When we have an arithmetic operation, or a shift whose count we
8397 do not know, we need to assume that all bits up to the highest-order
8398 bit in MASK will be needed. This is how we form such a mask. */
8399 if (mask
& (HOST_WIDE_INT_1U
<< (HOST_BITS_PER_WIDE_INT
- 1)))
8400 fuller_mask
= HOST_WIDE_INT_M1U
;
8402 fuller_mask
= ((HOST_WIDE_INT_1U
<< (floor_log2 (mask
) + 1))
8405 /* Determine what bits of X are guaranteed to be (non)zero. */
8406 nonzero
= nonzero_bits (x
, mode
);
8408 /* If none of the bits in X are needed, return a zero. */
8409 if (!just_select
&& (nonzero
& mask
) == 0 && !side_effects_p (x
))
8412 /* If X is a CONST_INT, return a new one. Do this here since the
8413 test below will fail. */
8414 if (CONST_INT_P (x
))
8416 if (SCALAR_INT_MODE_P (mode
))
8417 return gen_int_mode (INTVAL (x
) & mask
, mode
);
8420 x
= GEN_INT (INTVAL (x
) & mask
);
8421 return gen_lowpart_common (mode
, x
);
8425 /* If X is narrower than MODE and we want all the bits in X's mode, just
8426 get X in the proper mode. */
8427 if (GET_MODE_SIZE (GET_MODE (x
)) < GET_MODE_SIZE (mode
)
8428 && (GET_MODE_MASK (GET_MODE (x
)) & ~mask
) == 0)
8429 return gen_lowpart (mode
, x
);
8431 /* We can ignore the effect of a SUBREG if it narrows the mode or
8432 if the constant masks to zero all the bits the mode doesn't have. */
8433 if (GET_CODE (x
) == SUBREG
8434 && subreg_lowpart_p (x
)
8435 && ((GET_MODE_SIZE (GET_MODE (x
))
8436 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x
))))
8438 & GET_MODE_MASK (GET_MODE (x
))
8439 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x
)))))))
8440 return force_to_mode (SUBREG_REG (x
), mode
, mask
, next_select
);
8442 /* The arithmetic simplifications here only work for scalar integer modes. */
8443 if (!SCALAR_INT_MODE_P (mode
) || !SCALAR_INT_MODE_P (GET_MODE (x
)))
8444 return gen_lowpart_or_truncate (mode
, x
);
8449 /* If X is a (clobber (const_int)), return it since we know we are
8450 generating something that won't match. */
8457 x
= expand_compound_operation (x
);
8458 if (GET_CODE (x
) != code
)
8459 return force_to_mode (x
, mode
, mask
, next_select
);
8463 /* Similarly for a truncate. */
8464 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8467 /* If this is an AND with a constant, convert it into an AND
8468 whose constant is the AND of that constant with MASK. If it
8469 remains an AND of MASK, delete it since it is redundant. */
8471 if (CONST_INT_P (XEXP (x
, 1)))
8473 x
= simplify_and_const_int (x
, op_mode
, XEXP (x
, 0),
8474 mask
& INTVAL (XEXP (x
, 1)));
8476 /* If X is still an AND, see if it is an AND with a mask that
8477 is just some low-order bits. If so, and it is MASK, we don't
8480 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8481 && ((INTVAL (XEXP (x
, 1)) & GET_MODE_MASK (GET_MODE (x
)))
8485 /* If it remains an AND, try making another AND with the bits
8486 in the mode mask that aren't in MASK turned on. If the
8487 constant in the AND is wide enough, this might make a
8488 cheaper constant. */
8490 if (GET_CODE (x
) == AND
&& CONST_INT_P (XEXP (x
, 1))
8491 && GET_MODE_MASK (GET_MODE (x
)) != mask
8492 && HWI_COMPUTABLE_MODE_P (GET_MODE (x
)))
8494 unsigned HOST_WIDE_INT cval
8495 = UINTVAL (XEXP (x
, 1))
8496 | (GET_MODE_MASK (GET_MODE (x
)) & ~mask
);
8499 y
= simplify_gen_binary (AND
, GET_MODE (x
), XEXP (x
, 0),
8500 gen_int_mode (cval
, GET_MODE (x
)));
8501 if (set_src_cost (y
, GET_MODE (x
), optimize_this_for_speed_p
)
8502 < set_src_cost (x
, GET_MODE (x
), optimize_this_for_speed_p
))
8512 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8513 low-order bits (as in an alignment operation) and FOO is already
8514 aligned to that boundary, mask C1 to that boundary as well.
8515 This may eliminate that PLUS and, later, the AND. */
8518 unsigned int width
= GET_MODE_PRECISION (mode
);
8519 unsigned HOST_WIDE_INT smask
= mask
;
8521 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8522 number, sign extend it. */
8524 if (width
< HOST_BITS_PER_WIDE_INT
8525 && (smask
& (HOST_WIDE_INT_1U
<< (width
- 1))) != 0)
8526 smask
|= HOST_WIDE_INT_M1U
<< width
;
8528 if (CONST_INT_P (XEXP (x
, 1))
8529 && pow2p_hwi (- smask
)
8530 && (nonzero_bits (XEXP (x
, 0), mode
) & ~smask
) == 0
8531 && (INTVAL (XEXP (x
, 1)) & ~smask
) != 0)
8532 return force_to_mode (plus_constant (GET_MODE (x
), XEXP (x
, 0),
8533 (INTVAL (XEXP (x
, 1)) & smask
)),
8534 mode
, smask
, next_select
);
8540 /* Substituting into the operands of a widening MULT is not likely to
8541 create RTL matching a machine insn. */
8543 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
8544 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
)
8545 && (GET_CODE (XEXP (x
, 1)) == ZERO_EXTEND
8546 || GET_CODE (XEXP (x
, 1)) == SIGN_EXTEND
)
8547 && REG_P (XEXP (XEXP (x
, 0), 0))
8548 && REG_P (XEXP (XEXP (x
, 1), 0)))
8549 return gen_lowpart_or_truncate (mode
, x
);
8551 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8552 most significant bit in MASK since carries from those bits will
8553 affect the bits we are interested in. */
8558 /* If X is (minus C Y) where C's least set bit is larger than any bit
8559 in the mask, then we may replace with (neg Y). */
8560 if (CONST_INT_P (XEXP (x
, 0))
8561 && least_bit_hwi (UINTVAL (XEXP (x
, 0))) > mask
)
8563 x
= simplify_gen_unary (NEG
, GET_MODE (x
), XEXP (x
, 1),
8565 return force_to_mode (x
, mode
, mask
, next_select
);
8568 /* Similarly, if C contains every bit in the fuller_mask, then we may
8569 replace with (not Y). */
8570 if (CONST_INT_P (XEXP (x
, 0))
8571 && ((UINTVAL (XEXP (x
, 0)) | fuller_mask
) == UINTVAL (XEXP (x
, 0))))
8573 x
= simplify_gen_unary (NOT
, GET_MODE (x
),
8574 XEXP (x
, 1), GET_MODE (x
));
8575 return force_to_mode (x
, mode
, mask
, next_select
);
8583 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8584 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8585 operation which may be a bitfield extraction. Ensure that the
8586 constant we form is not wider than the mode of X. */
8588 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8589 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8590 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8591 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
8592 && CONST_INT_P (XEXP (x
, 1))
8593 && ((INTVAL (XEXP (XEXP (x
, 0), 1))
8594 + floor_log2 (INTVAL (XEXP (x
, 1))))
8595 < GET_MODE_PRECISION (GET_MODE (x
)))
8596 && (UINTVAL (XEXP (x
, 1))
8597 & ~nonzero_bits (XEXP (x
, 0), GET_MODE (x
))) == 0)
8599 temp
= gen_int_mode ((INTVAL (XEXP (x
, 1)) & mask
)
8600 << INTVAL (XEXP (XEXP (x
, 0), 1)),
8602 temp
= simplify_gen_binary (GET_CODE (x
), GET_MODE (x
),
8603 XEXP (XEXP (x
, 0), 0), temp
);
8604 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), temp
,
8605 XEXP (XEXP (x
, 0), 1));
8606 return force_to_mode (x
, mode
, mask
, next_select
);
8610 /* For most binary operations, just propagate into the operation and
8611 change the mode if we have an operation of that mode. */
8613 op0
= force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8614 op1
= force_to_mode (XEXP (x
, 1), mode
, mask
, next_select
);
8616 /* If we ended up truncating both operands, truncate the result of the
8617 operation instead. */
8618 if (GET_CODE (op0
) == TRUNCATE
8619 && GET_CODE (op1
) == TRUNCATE
)
8621 op0
= XEXP (op0
, 0);
8622 op1
= XEXP (op1
, 0);
8625 op0
= gen_lowpart_or_truncate (op_mode
, op0
);
8626 op1
= gen_lowpart_or_truncate (op_mode
, op1
);
8628 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0) || op1
!= XEXP (x
, 1))
8629 x
= simplify_gen_binary (code
, op_mode
, op0
, op1
);
8633 /* For left shifts, do the same, but just for the first operand.
8634 However, we cannot do anything with shifts where we cannot
8635 guarantee that the counts are smaller than the size of the mode
8636 because such a count will have a different meaning in a
8639 if (! (CONST_INT_P (XEXP (x
, 1))
8640 && INTVAL (XEXP (x
, 1)) >= 0
8641 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (mode
))
8642 && ! (GET_MODE (XEXP (x
, 1)) != VOIDmode
8643 && (nonzero_bits (XEXP (x
, 1), GET_MODE (XEXP (x
, 1)))
8644 < (unsigned HOST_WIDE_INT
) GET_MODE_PRECISION (mode
))))
8647 /* If the shift count is a constant and we can do arithmetic in
8648 the mode of the shift, refine which bits we need. Otherwise, use the
8649 conservative form of the mask. */
8650 if (CONST_INT_P (XEXP (x
, 1))
8651 && INTVAL (XEXP (x
, 1)) >= 0
8652 && INTVAL (XEXP (x
, 1)) < GET_MODE_PRECISION (op_mode
)
8653 && HWI_COMPUTABLE_MODE_P (op_mode
))
8654 mask
>>= INTVAL (XEXP (x
, 1));
8658 op0
= gen_lowpart_or_truncate (op_mode
,
8659 force_to_mode (XEXP (x
, 0), op_mode
,
8660 mask
, next_select
));
8662 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8663 x
= simplify_gen_binary (code
, op_mode
, op0
, XEXP (x
, 1));
8667 /* Here we can only do something if the shift count is a constant,
8668 this shift constant is valid for the host, and we can do arithmetic
8671 if (CONST_INT_P (XEXP (x
, 1))
8672 && INTVAL (XEXP (x
, 1)) >= 0
8673 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
8674 && HWI_COMPUTABLE_MODE_P (op_mode
))
8676 rtx inner
= XEXP (x
, 0);
8677 unsigned HOST_WIDE_INT inner_mask
;
8679 /* Select the mask of the bits we need for the shift operand. */
8680 inner_mask
= mask
<< INTVAL (XEXP (x
, 1));
8682 /* We can only change the mode of the shift if we can do arithmetic
8683 in the mode of the shift and INNER_MASK is no wider than the
8684 width of X's mode. */
8685 if ((inner_mask
& ~GET_MODE_MASK (GET_MODE (x
))) != 0)
8686 op_mode
= GET_MODE (x
);
8688 inner
= force_to_mode (inner
, op_mode
, inner_mask
, next_select
);
8690 if (GET_MODE (x
) != op_mode
|| inner
!= XEXP (x
, 0))
8691 x
= simplify_gen_binary (LSHIFTRT
, op_mode
, inner
, XEXP (x
, 1));
8694 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8695 shift and AND produces only copies of the sign bit (C2 is one less
8696 than a power of two), we can do this with just a shift. */
8698 if (GET_CODE (x
) == LSHIFTRT
8699 && CONST_INT_P (XEXP (x
, 1))
8700 /* The shift puts one of the sign bit copies in the least significant
8702 && ((INTVAL (XEXP (x
, 1))
8703 + num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0))))
8704 >= GET_MODE_PRECISION (GET_MODE (x
)))
8705 && pow2p_hwi (mask
+ 1)
8706 /* Number of bits left after the shift must be more than the mask
8708 && ((INTVAL (XEXP (x
, 1)) + exact_log2 (mask
+ 1))
8709 <= GET_MODE_PRECISION (GET_MODE (x
)))
8710 /* Must be more sign bit copies than the mask needs. */
8711 && ((int) num_sign_bit_copies (XEXP (x
, 0), GET_MODE (XEXP (x
, 0)))
8712 >= exact_log2 (mask
+ 1)))
8713 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8714 GEN_INT (GET_MODE_PRECISION (GET_MODE (x
))
8715 - exact_log2 (mask
+ 1)));
8720 /* If we are just looking for the sign bit, we don't need this shift at
8721 all, even if it has a variable count. */
8722 if (val_signbit_p (GET_MODE (x
), mask
))
8723 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8725 /* If this is a shift by a constant, get a mask that contains those bits
8726 that are not copies of the sign bit. We then have two cases: If
8727 MASK only includes those bits, this can be a logical shift, which may
8728 allow simplifications. If MASK is a single-bit field not within
8729 those bits, we are requesting a copy of the sign bit and hence can
8730 shift the sign bit to the appropriate location. */
8732 if (CONST_INT_P (XEXP (x
, 1)) && INTVAL (XEXP (x
, 1)) >= 0
8733 && INTVAL (XEXP (x
, 1)) < HOST_BITS_PER_WIDE_INT
)
8737 /* If the considered data is wider than HOST_WIDE_INT, we can't
8738 represent a mask for all its bits in a single scalar.
8739 But we only care about the lower bits, so calculate these. */
8741 if (GET_MODE_PRECISION (GET_MODE (x
)) > HOST_BITS_PER_WIDE_INT
)
8743 nonzero
= HOST_WIDE_INT_M1U
;
8745 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8746 is the number of bits a full-width mask would have set.
8747 We need only shift if these are fewer than nonzero can
8748 hold. If not, we must keep all bits set in nonzero. */
8750 if (GET_MODE_PRECISION (GET_MODE (x
)) - INTVAL (XEXP (x
, 1))
8751 < HOST_BITS_PER_WIDE_INT
)
8752 nonzero
>>= INTVAL (XEXP (x
, 1))
8753 + HOST_BITS_PER_WIDE_INT
8754 - GET_MODE_PRECISION (GET_MODE (x
)) ;
8758 nonzero
= GET_MODE_MASK (GET_MODE (x
));
8759 nonzero
>>= INTVAL (XEXP (x
, 1));
8762 if ((mask
& ~nonzero
) == 0)
8764 x
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, GET_MODE (x
),
8765 XEXP (x
, 0), INTVAL (XEXP (x
, 1)));
8766 if (GET_CODE (x
) != ASHIFTRT
)
8767 return force_to_mode (x
, mode
, mask
, next_select
);
8770 else if ((i
= exact_log2 (mask
)) >= 0)
8772 x
= simplify_shift_const
8773 (NULL_RTX
, LSHIFTRT
, GET_MODE (x
), XEXP (x
, 0),
8774 GET_MODE_PRECISION (GET_MODE (x
)) - 1 - i
);
8776 if (GET_CODE (x
) != ASHIFTRT
)
8777 return force_to_mode (x
, mode
, mask
, next_select
);
8781 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8782 even if the shift count isn't a constant. */
8784 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8785 XEXP (x
, 0), XEXP (x
, 1));
8789 /* If this is a zero- or sign-extension operation that just affects bits
8790 we don't care about, remove it. Be sure the call above returned
8791 something that is still a shift. */
8793 if ((GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ASHIFTRT
)
8794 && CONST_INT_P (XEXP (x
, 1))
8795 && INTVAL (XEXP (x
, 1)) >= 0
8796 && (INTVAL (XEXP (x
, 1))
8797 <= GET_MODE_PRECISION (GET_MODE (x
)) - (floor_log2 (mask
) + 1))
8798 && GET_CODE (XEXP (x
, 0)) == ASHIFT
8799 && XEXP (XEXP (x
, 0), 1) == XEXP (x
, 1))
8800 return force_to_mode (XEXP (XEXP (x
, 0), 0), mode
, mask
,
8807 /* If the shift count is constant and we can do computations
8808 in the mode of X, compute where the bits we care about are.
8809 Otherwise, we can't do anything. Don't change the mode of
8810 the shift or propagate MODE into the shift, though. */
8811 if (CONST_INT_P (XEXP (x
, 1))
8812 && INTVAL (XEXP (x
, 1)) >= 0)
8814 temp
= simplify_binary_operation (code
== ROTATE
? ROTATERT
: ROTATE
,
8816 gen_int_mode (mask
, GET_MODE (x
)),
8818 if (temp
&& CONST_INT_P (temp
))
8819 x
= simplify_gen_binary (code
, GET_MODE (x
),
8820 force_to_mode (XEXP (x
, 0), GET_MODE (x
),
8821 INTVAL (temp
), next_select
),
8827 /* If we just want the low-order bit, the NEG isn't needed since it
8828 won't change the low-order bit. */
8830 return force_to_mode (XEXP (x
, 0), mode
, mask
, just_select
);
8832 /* We need any bits less significant than the most significant bit in
8833 MASK since carries from those bits will affect the bits we are
8839 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8840 same as the XOR case above. Ensure that the constant we form is not
8841 wider than the mode of X. */
8843 if (GET_CODE (XEXP (x
, 0)) == LSHIFTRT
8844 && CONST_INT_P (XEXP (XEXP (x
, 0), 1))
8845 && INTVAL (XEXP (XEXP (x
, 0), 1)) >= 0
8846 && (INTVAL (XEXP (XEXP (x
, 0), 1)) + floor_log2 (mask
)
8847 < GET_MODE_PRECISION (GET_MODE (x
)))
8848 && INTVAL (XEXP (XEXP (x
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
8850 temp
= gen_int_mode (mask
<< INTVAL (XEXP (XEXP (x
, 0), 1)),
8852 temp
= simplify_gen_binary (XOR
, GET_MODE (x
),
8853 XEXP (XEXP (x
, 0), 0), temp
);
8854 x
= simplify_gen_binary (LSHIFTRT
, GET_MODE (x
),
8855 temp
, XEXP (XEXP (x
, 0), 1));
8857 return force_to_mode (x
, mode
, mask
, next_select
);
8860 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8861 use the full mask inside the NOT. */
8865 op0
= gen_lowpart_or_truncate (op_mode
,
8866 force_to_mode (XEXP (x
, 0), mode
, mask
,
8868 if (op_mode
!= GET_MODE (x
) || op0
!= XEXP (x
, 0))
8869 x
= simplify_gen_unary (code
, op_mode
, op0
, op_mode
);
8873 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8874 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8875 which is equal to STORE_FLAG_VALUE. */
8876 if ((mask
& ~STORE_FLAG_VALUE
) == 0
8877 && XEXP (x
, 1) == const0_rtx
8878 && GET_MODE (XEXP (x
, 0)) == mode
8879 && pow2p_hwi (nonzero_bits (XEXP (x
, 0), mode
))
8880 && (nonzero_bits (XEXP (x
, 0), mode
)
8881 == (unsigned HOST_WIDE_INT
) STORE_FLAG_VALUE
))
8882 return force_to_mode (XEXP (x
, 0), mode
, mask
, next_select
);
8887 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8888 written in a narrower mode. We play it safe and do not do so. */
8890 op0
= gen_lowpart_or_truncate (GET_MODE (x
),
8891 force_to_mode (XEXP (x
, 1), mode
,
8892 mask
, next_select
));
8893 op1
= gen_lowpart_or_truncate (GET_MODE (x
),
8894 force_to_mode (XEXP (x
, 2), mode
,
8895 mask
, next_select
));
8896 if (op0
!= XEXP (x
, 1) || op1
!= XEXP (x
, 2))
8897 x
= simplify_gen_ternary (IF_THEN_ELSE
, GET_MODE (x
),
8898 GET_MODE (XEXP (x
, 0)), XEXP (x
, 0),
8906 /* Ensure we return a value of the proper mode. */
8907 return gen_lowpart_or_truncate (mode
, x
);
8910 /* Return nonzero if X is an expression that has one of two values depending on
8911 whether some other value is zero or nonzero. In that case, we return the
8912 value that is being tested, *PTRUE is set to the value if the rtx being
8913 returned has a nonzero value, and *PFALSE is set to the other alternative.
8915 If we return zero, we set *PTRUE and *PFALSE to X. */
8918 if_then_else_cond (rtx x
, rtx
*ptrue
, rtx
*pfalse
)
8920 machine_mode mode
= GET_MODE (x
);
8921 enum rtx_code code
= GET_CODE (x
);
8922 rtx cond0
, cond1
, true0
, true1
, false0
, false1
;
8923 unsigned HOST_WIDE_INT nz
;
8925 /* If we are comparing a value against zero, we are done. */
8926 if ((code
== NE
|| code
== EQ
)
8927 && XEXP (x
, 1) == const0_rtx
)
8929 *ptrue
= (code
== NE
) ? const_true_rtx
: const0_rtx
;
8930 *pfalse
= (code
== NE
) ? const0_rtx
: const_true_rtx
;
8934 /* If this is a unary operation whose operand has one of two values, apply
8935 our opcode to compute those values. */
8936 else if (UNARY_P (x
)
8937 && (cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
)) != 0)
8939 *ptrue
= simplify_gen_unary (code
, mode
, true0
, GET_MODE (XEXP (x
, 0)));
8940 *pfalse
= simplify_gen_unary (code
, mode
, false0
,
8941 GET_MODE (XEXP (x
, 0)));
8945 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8946 make can't possibly match and would suppress other optimizations. */
8947 else if (code
== COMPARE
)
8950 /* If this is a binary operation, see if either side has only one of two
8951 values. If either one does or if both do and they are conditional on
8952 the same value, compute the new true and false values. */
8953 else if (BINARY_P (x
))
8955 cond0
= if_then_else_cond (XEXP (x
, 0), &true0
, &false0
);
8956 cond1
= if_then_else_cond (XEXP (x
, 1), &true1
, &false1
);
8958 if ((cond0
!= 0 || cond1
!= 0)
8959 && ! (cond0
!= 0 && cond1
!= 0 && ! rtx_equal_p (cond0
, cond1
)))
8961 /* If if_then_else_cond returned zero, then true/false are the
8962 same rtl. We must copy one of them to prevent invalid rtl
8965 true0
= copy_rtx (true0
);
8966 else if (cond1
== 0)
8967 true1
= copy_rtx (true1
);
8969 if (COMPARISON_P (x
))
8971 *ptrue
= simplify_gen_relational (code
, mode
, VOIDmode
,
8973 *pfalse
= simplify_gen_relational (code
, mode
, VOIDmode
,
8978 *ptrue
= simplify_gen_binary (code
, mode
, true0
, true1
);
8979 *pfalse
= simplify_gen_binary (code
, mode
, false0
, false1
);
8982 return cond0
? cond0
: cond1
;
8985 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8986 operands is zero when the other is nonzero, and vice-versa,
8987 and STORE_FLAG_VALUE is 1 or -1. */
8989 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
8990 && (code
== PLUS
|| code
== IOR
|| code
== XOR
|| code
== MINUS
8992 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
8994 rtx op0
= XEXP (XEXP (x
, 0), 1);
8995 rtx op1
= XEXP (XEXP (x
, 1), 1);
8997 cond0
= XEXP (XEXP (x
, 0), 0);
8998 cond1
= XEXP (XEXP (x
, 1), 0);
9000 if (COMPARISON_P (cond0
)
9001 && COMPARISON_P (cond1
)
9002 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9003 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9004 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9005 || ((swap_condition (GET_CODE (cond0
))
9006 == reversed_comparison_code (cond1
, NULL
))
9007 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9008 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9009 && ! side_effects_p (x
))
9011 *ptrue
= simplify_gen_binary (MULT
, mode
, op0
, const_true_rtx
);
9012 *pfalse
= simplify_gen_binary (MULT
, mode
,
9014 ? simplify_gen_unary (NEG
, mode
,
9022 /* Similarly for MULT, AND and UMIN, except that for these the result
9024 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
9025 && (code
== MULT
|| code
== AND
|| code
== UMIN
)
9026 && GET_CODE (XEXP (x
, 0)) == MULT
&& GET_CODE (XEXP (x
, 1)) == MULT
)
9028 cond0
= XEXP (XEXP (x
, 0), 0);
9029 cond1
= XEXP (XEXP (x
, 1), 0);
9031 if (COMPARISON_P (cond0
)
9032 && COMPARISON_P (cond1
)
9033 && ((GET_CODE (cond0
) == reversed_comparison_code (cond1
, NULL
)
9034 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 0))
9035 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 1)))
9036 || ((swap_condition (GET_CODE (cond0
))
9037 == reversed_comparison_code (cond1
, NULL
))
9038 && rtx_equal_p (XEXP (cond0
, 0), XEXP (cond1
, 1))
9039 && rtx_equal_p (XEXP (cond0
, 1), XEXP (cond1
, 0))))
9040 && ! side_effects_p (x
))
9042 *ptrue
= *pfalse
= const0_rtx
;
9048 else if (code
== IF_THEN_ELSE
)
9050 /* If we have IF_THEN_ELSE already, extract the condition and
9051 canonicalize it if it is NE or EQ. */
9052 cond0
= XEXP (x
, 0);
9053 *ptrue
= XEXP (x
, 1), *pfalse
= XEXP (x
, 2);
9054 if (GET_CODE (cond0
) == NE
&& XEXP (cond0
, 1) == const0_rtx
)
9055 return XEXP (cond0
, 0);
9056 else if (GET_CODE (cond0
) == EQ
&& XEXP (cond0
, 1) == const0_rtx
)
9058 *ptrue
= XEXP (x
, 2), *pfalse
= XEXP (x
, 1);
9059 return XEXP (cond0
, 0);
9065 /* If X is a SUBREG, we can narrow both the true and false values
9066 if the inner expression, if there is a condition. */
9067 else if (code
== SUBREG
9068 && 0 != (cond0
= if_then_else_cond (SUBREG_REG (x
),
9071 true0
= simplify_gen_subreg (mode
, true0
,
9072 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9073 false0
= simplify_gen_subreg (mode
, false0
,
9074 GET_MODE (SUBREG_REG (x
)), SUBREG_BYTE (x
));
9075 if (true0
&& false0
)
9083 /* If X is a constant, this isn't special and will cause confusions
9084 if we treat it as such. Likewise if it is equivalent to a constant. */
9085 else if (CONSTANT_P (x
)
9086 || ((cond0
= get_last_value (x
)) != 0 && CONSTANT_P (cond0
)))
9089 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9090 will be least confusing to the rest of the compiler. */
9091 else if (mode
== BImode
)
9093 *ptrue
= GEN_INT (STORE_FLAG_VALUE
), *pfalse
= const0_rtx
;
9097 /* If X is known to be either 0 or -1, those are the true and
9098 false values when testing X. */
9099 else if (x
== constm1_rtx
|| x
== const0_rtx
9100 || (mode
!= VOIDmode
9101 && num_sign_bit_copies (x
, mode
) == GET_MODE_PRECISION (mode
)))
9103 *ptrue
= constm1_rtx
, *pfalse
= const0_rtx
;
9107 /* Likewise for 0 or a single bit. */
9108 else if (HWI_COMPUTABLE_MODE_P (mode
)
9109 && pow2p_hwi (nz
= nonzero_bits (x
, mode
)))
9111 *ptrue
= gen_int_mode (nz
, mode
), *pfalse
= const0_rtx
;
9115 /* Otherwise fail; show no condition with true and false values the same. */
9116 *ptrue
= *pfalse
= x
;
9120 /* Return the value of expression X given the fact that condition COND
9121 is known to be true when applied to REG as its first operand and VAL
9122 as its second. X is known to not be shared and so can be modified in
9125 We only handle the simplest cases, and specifically those cases that
9126 arise with IF_THEN_ELSE expressions. */
9129 known_cond (rtx x
, enum rtx_code cond
, rtx reg
, rtx val
)
9131 enum rtx_code code
= GET_CODE (x
);
9135 if (side_effects_p (x
))
9138 /* If either operand of the condition is a floating point value,
9139 then we have to avoid collapsing an EQ comparison. */
9141 && rtx_equal_p (x
, reg
)
9142 && ! FLOAT_MODE_P (GET_MODE (x
))
9143 && ! FLOAT_MODE_P (GET_MODE (val
)))
9146 if (cond
== UNEQ
&& rtx_equal_p (x
, reg
))
9149 /* If X is (abs REG) and we know something about REG's relationship
9150 with zero, we may be able to simplify this. */
9152 if (code
== ABS
&& rtx_equal_p (XEXP (x
, 0), reg
) && val
== const0_rtx
)
9155 case GE
: case GT
: case EQ
:
9158 return simplify_gen_unary (NEG
, GET_MODE (XEXP (x
, 0)),
9160 GET_MODE (XEXP (x
, 0)));
9165 /* The only other cases we handle are MIN, MAX, and comparisons if the
9166 operands are the same as REG and VAL. */
9168 else if (COMPARISON_P (x
) || COMMUTATIVE_ARITH_P (x
))
9170 if (rtx_equal_p (XEXP (x
, 0), val
))
9172 std::swap (val
, reg
);
9173 cond
= swap_condition (cond
);
9176 if (rtx_equal_p (XEXP (x
, 0), reg
) && rtx_equal_p (XEXP (x
, 1), val
))
9178 if (COMPARISON_P (x
))
9180 if (comparison_dominates_p (cond
, code
))
9181 return const_true_rtx
;
9183 code
= reversed_comparison_code (x
, NULL
);
9185 && comparison_dominates_p (cond
, code
))
9190 else if (code
== SMAX
|| code
== SMIN
9191 || code
== UMIN
|| code
== UMAX
)
9193 int unsignedp
= (code
== UMIN
|| code
== UMAX
);
9195 /* Do not reverse the condition when it is NE or EQ.
9196 This is because we cannot conclude anything about
9197 the value of 'SMAX (x, y)' when x is not equal to y,
9198 but we can when x equals y. */
9199 if ((code
== SMAX
|| code
== UMAX
)
9200 && ! (cond
== EQ
|| cond
== NE
))
9201 cond
= reverse_condition (cond
);
9206 return unsignedp
? x
: XEXP (x
, 1);
9208 return unsignedp
? x
: XEXP (x
, 0);
9210 return unsignedp
? XEXP (x
, 1) : x
;
9212 return unsignedp
? XEXP (x
, 0) : x
;
9219 else if (code
== SUBREG
)
9221 machine_mode inner_mode
= GET_MODE (SUBREG_REG (x
));
9222 rtx new_rtx
, r
= known_cond (SUBREG_REG (x
), cond
, reg
, val
);
9224 if (SUBREG_REG (x
) != r
)
9226 /* We must simplify subreg here, before we lose track of the
9227 original inner_mode. */
9228 new_rtx
= simplify_subreg (GET_MODE (x
), r
,
9229 inner_mode
, SUBREG_BYTE (x
));
9233 SUBST (SUBREG_REG (x
), r
);
9238 /* We don't have to handle SIGN_EXTEND here, because even in the
9239 case of replacing something with a modeless CONST_INT, a
9240 CONST_INT is already (supposed to be) a valid sign extension for
9241 its narrower mode, which implies it's already properly
9242 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9243 story is different. */
9244 else if (code
== ZERO_EXTEND
)
9246 machine_mode inner_mode
= GET_MODE (XEXP (x
, 0));
9247 rtx new_rtx
, r
= known_cond (XEXP (x
, 0), cond
, reg
, val
);
9249 if (XEXP (x
, 0) != r
)
9251 /* We must simplify the zero_extend here, before we lose
9252 track of the original inner_mode. */
9253 new_rtx
= simplify_unary_operation (ZERO_EXTEND
, GET_MODE (x
),
9258 SUBST (XEXP (x
, 0), r
);
9264 fmt
= GET_RTX_FORMAT (code
);
9265 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
9268 SUBST (XEXP (x
, i
), known_cond (XEXP (x
, i
), cond
, reg
, val
));
9269 else if (fmt
[i
] == 'E')
9270 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
9271 SUBST (XVECEXP (x
, i
, j
), known_cond (XVECEXP (x
, i
, j
),
9278 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9279 assignment as a field assignment. */
9282 rtx_equal_for_field_assignment_p (rtx x
, rtx y
, bool widen_x
)
9284 if (widen_x
&& GET_MODE (x
) != GET_MODE (y
))
9286 if (GET_MODE_SIZE (GET_MODE (x
)) > GET_MODE_SIZE (GET_MODE (y
)))
9288 if (BYTES_BIG_ENDIAN
!= WORDS_BIG_ENDIAN
)
9290 /* For big endian, adjust the memory offset. */
9291 if (BYTES_BIG_ENDIAN
)
9292 x
= adjust_address_nv (x
, GET_MODE (y
),
9293 -subreg_lowpart_offset (GET_MODE (x
),
9296 x
= adjust_address_nv (x
, GET_MODE (y
), 0);
9299 if (x
== y
|| rtx_equal_p (x
, y
))
9302 if (x
== 0 || y
== 0 || GET_MODE (x
) != GET_MODE (y
))
9305 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9306 Note that all SUBREGs of MEM are paradoxical; otherwise they
9307 would have been rewritten. */
9308 if (MEM_P (x
) && GET_CODE (y
) == SUBREG
9309 && MEM_P (SUBREG_REG (y
))
9310 && rtx_equal_p (SUBREG_REG (y
),
9311 gen_lowpart (GET_MODE (SUBREG_REG (y
)), x
)))
9314 if (MEM_P (y
) && GET_CODE (x
) == SUBREG
9315 && MEM_P (SUBREG_REG (x
))
9316 && rtx_equal_p (SUBREG_REG (x
),
9317 gen_lowpart (GET_MODE (SUBREG_REG (x
)), y
)))
9320 /* We used to see if get_last_value of X and Y were the same but that's
9321 not correct. In one direction, we'll cause the assignment to have
9322 the wrong destination and in the case, we'll import a register into this
9323 insn that might have already have been dead. So fail if none of the
9324 above cases are true. */
9328 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9329 Return that assignment if so.
9331 We only handle the most common cases. */
9334 make_field_assignment (rtx x
)
9336 rtx dest
= SET_DEST (x
);
9337 rtx src
= SET_SRC (x
);
9342 unsigned HOST_WIDE_INT len
;
9346 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9347 a clear of a one-bit field. We will have changed it to
9348 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9351 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == ROTATE
9352 && CONST_INT_P (XEXP (XEXP (src
, 0), 0))
9353 && INTVAL (XEXP (XEXP (src
, 0), 0)) == -2
9354 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9356 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9359 return gen_rtx_SET (assign
, const0_rtx
);
9363 if (GET_CODE (src
) == AND
&& GET_CODE (XEXP (src
, 0)) == SUBREG
9364 && subreg_lowpart_p (XEXP (src
, 0))
9365 && (GET_MODE_SIZE (GET_MODE (XEXP (src
, 0)))
9366 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src
, 0)))))
9367 && GET_CODE (SUBREG_REG (XEXP (src
, 0))) == ROTATE
9368 && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src
, 0)), 0))
9369 && INTVAL (XEXP (SUBREG_REG (XEXP (src
, 0)), 0)) == -2
9370 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9372 assign
= make_extraction (VOIDmode
, dest
, 0,
9373 XEXP (SUBREG_REG (XEXP (src
, 0)), 1),
9376 return gen_rtx_SET (assign
, const0_rtx
);
9380 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9382 if (GET_CODE (src
) == IOR
&& GET_CODE (XEXP (src
, 0)) == ASHIFT
9383 && XEXP (XEXP (src
, 0), 0) == const1_rtx
9384 && rtx_equal_for_field_assignment_p (dest
, XEXP (src
, 1)))
9386 assign
= make_extraction (VOIDmode
, dest
, 0, XEXP (XEXP (src
, 0), 1),
9389 return gen_rtx_SET (assign
, const1_rtx
);
9393 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9394 SRC is an AND with all bits of that field set, then we can discard
9396 if (GET_CODE (dest
) == ZERO_EXTRACT
9397 && CONST_INT_P (XEXP (dest
, 1))
9398 && GET_CODE (src
) == AND
9399 && CONST_INT_P (XEXP (src
, 1)))
9401 HOST_WIDE_INT width
= INTVAL (XEXP (dest
, 1));
9402 unsigned HOST_WIDE_INT and_mask
= INTVAL (XEXP (src
, 1));
9403 unsigned HOST_WIDE_INT ze_mask
;
9405 if (width
>= HOST_BITS_PER_WIDE_INT
)
9408 ze_mask
= ((unsigned HOST_WIDE_INT
)1 << width
) - 1;
9410 /* Complete overlap. We can remove the source AND. */
9411 if ((and_mask
& ze_mask
) == ze_mask
)
9412 return gen_rtx_SET (dest
, XEXP (src
, 0));
9414 /* Partial overlap. We can reduce the source AND. */
9415 if ((and_mask
& ze_mask
) != and_mask
)
9417 mode
= GET_MODE (src
);
9418 src
= gen_rtx_AND (mode
, XEXP (src
, 0),
9419 gen_int_mode (and_mask
& ze_mask
, mode
));
9420 return gen_rtx_SET (dest
, src
);
9424 /* The other case we handle is assignments into a constant-position
9425 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9426 a mask that has all one bits except for a group of zero bits and
9427 OTHER is known to have zeros where C1 has ones, this is such an
9428 assignment. Compute the position and length from C1. Shift OTHER
9429 to the appropriate position, force it to the required mode, and
9430 make the extraction. Check for the AND in both operands. */
9432 /* One or more SUBREGs might obscure the constant-position field
9433 assignment. The first one we are likely to encounter is an outer
9434 narrowing SUBREG, which we can just strip for the purposes of
9435 identifying the constant-field assignment. */
9436 if (GET_CODE (src
) == SUBREG
&& subreg_lowpart_p (src
))
9437 src
= SUBREG_REG (src
);
9439 if (GET_CODE (src
) != IOR
&& GET_CODE (src
) != XOR
)
9442 rhs
= expand_compound_operation (XEXP (src
, 0));
9443 lhs
= expand_compound_operation (XEXP (src
, 1));
9445 if (GET_CODE (rhs
) == AND
9446 && CONST_INT_P (XEXP (rhs
, 1))
9447 && rtx_equal_for_field_assignment_p (XEXP (rhs
, 0), dest
))
9448 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9449 /* The second SUBREG that might get in the way is a paradoxical
9450 SUBREG around the first operand of the AND. We want to
9451 pretend the operand is as wide as the destination here. We
9452 do this by adjusting the MEM to wider mode for the sole
9453 purpose of the call to rtx_equal_for_field_assignment_p. Also
9454 note this trick only works for MEMs. */
9455 else if (GET_CODE (rhs
) == AND
9456 && paradoxical_subreg_p (XEXP (rhs
, 0))
9457 && MEM_P (SUBREG_REG (XEXP (rhs
, 0)))
9458 && CONST_INT_P (XEXP (rhs
, 1))
9459 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs
, 0)),
9461 c1
= INTVAL (XEXP (rhs
, 1)), other
= lhs
;
9462 else if (GET_CODE (lhs
) == AND
9463 && CONST_INT_P (XEXP (lhs
, 1))
9464 && rtx_equal_for_field_assignment_p (XEXP (lhs
, 0), dest
))
9465 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9466 /* The second SUBREG that might get in the way is a paradoxical
9467 SUBREG around the first operand of the AND. We want to
9468 pretend the operand is as wide as the destination here. We
9469 do this by adjusting the MEM to wider mode for the sole
9470 purpose of the call to rtx_equal_for_field_assignment_p. Also
9471 note this trick only works for MEMs. */
9472 else if (GET_CODE (lhs
) == AND
9473 && paradoxical_subreg_p (XEXP (lhs
, 0))
9474 && MEM_P (SUBREG_REG (XEXP (lhs
, 0)))
9475 && CONST_INT_P (XEXP (lhs
, 1))
9476 && rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs
, 0)),
9478 c1
= INTVAL (XEXP (lhs
, 1)), other
= rhs
;
9482 pos
= get_pos_from_mask ((~c1
) & GET_MODE_MASK (GET_MODE (dest
)), &len
);
9483 if (pos
< 0 || pos
+ len
> GET_MODE_PRECISION (GET_MODE (dest
))
9484 || GET_MODE_PRECISION (GET_MODE (dest
)) > HOST_BITS_PER_WIDE_INT
9485 || (c1
& nonzero_bits (other
, GET_MODE (dest
))) != 0)
9488 assign
= make_extraction (VOIDmode
, dest
, pos
, NULL_RTX
, len
, 1, 1, 0);
9492 /* The mode to use for the source is the mode of the assignment, or of
9493 what is inside a possible STRICT_LOW_PART. */
9494 mode
= (GET_CODE (assign
) == STRICT_LOW_PART
9495 ? GET_MODE (XEXP (assign
, 0)) : GET_MODE (assign
));
9497 /* Shift OTHER right POS places and make it the source, restricting it
9498 to the proper length and mode. */
9500 src
= canon_reg_for_combine (simplify_shift_const (NULL_RTX
, LSHIFTRT
,
9504 src
= force_to_mode (src
, mode
,
9505 GET_MODE_PRECISION (mode
) >= HOST_BITS_PER_WIDE_INT
9507 : (HOST_WIDE_INT_1U
<< len
) - 1,
9510 /* If SRC is masked by an AND that does not make a difference in
9511 the value being stored, strip it. */
9512 if (GET_CODE (assign
) == ZERO_EXTRACT
9513 && CONST_INT_P (XEXP (assign
, 1))
9514 && INTVAL (XEXP (assign
, 1)) < HOST_BITS_PER_WIDE_INT
9515 && GET_CODE (src
) == AND
9516 && CONST_INT_P (XEXP (src
, 1))
9517 && UINTVAL (XEXP (src
, 1))
9518 == (HOST_WIDE_INT_1U
<< INTVAL (XEXP (assign
, 1))) - 1)
9519 src
= XEXP (src
, 0);
9521 return gen_rtx_SET (assign
, src
);
9524 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9528 apply_distributive_law (rtx x
)
9530 enum rtx_code code
= GET_CODE (x
);
9531 enum rtx_code inner_code
;
9532 rtx lhs
, rhs
, other
;
9535 /* Distributivity is not true for floating point as it can change the
9536 value. So we don't do it unless -funsafe-math-optimizations. */
9537 if (FLOAT_MODE_P (GET_MODE (x
))
9538 && ! flag_unsafe_math_optimizations
)
9541 /* The outer operation can only be one of the following: */
9542 if (code
!= IOR
&& code
!= AND
&& code
!= XOR
9543 && code
!= PLUS
&& code
!= MINUS
)
9549 /* If either operand is a primitive we can't do anything, so get out
9551 if (OBJECT_P (lhs
) || OBJECT_P (rhs
))
9554 lhs
= expand_compound_operation (lhs
);
9555 rhs
= expand_compound_operation (rhs
);
9556 inner_code
= GET_CODE (lhs
);
9557 if (inner_code
!= GET_CODE (rhs
))
9560 /* See if the inner and outer operations distribute. */
9567 /* These all distribute except over PLUS. */
9568 if (code
== PLUS
|| code
== MINUS
)
9573 if (code
!= PLUS
&& code
!= MINUS
)
9578 /* This is also a multiply, so it distributes over everything. */
9581 /* This used to handle SUBREG, but this turned out to be counter-
9582 productive, since (subreg (op ...)) usually is not handled by
9583 insn patterns, and this "optimization" therefore transformed
9584 recognizable patterns into unrecognizable ones. Therefore the
9585 SUBREG case was removed from here.
9587 It is possible that distributing SUBREG over arithmetic operations
9588 leads to an intermediate result than can then be optimized further,
9589 e.g. by moving the outer SUBREG to the other side of a SET as done
9590 in simplify_set. This seems to have been the original intent of
9591 handling SUBREGs here.
9593 However, with current GCC this does not appear to actually happen,
9594 at least on major platforms. If some case is found where removing
9595 the SUBREG case here prevents follow-on optimizations, distributing
9596 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9602 /* Set LHS and RHS to the inner operands (A and B in the example
9603 above) and set OTHER to the common operand (C in the example).
9604 There is only one way to do this unless the inner operation is
9606 if (COMMUTATIVE_ARITH_P (lhs
)
9607 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 0)))
9608 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 1);
9609 else if (COMMUTATIVE_ARITH_P (lhs
)
9610 && rtx_equal_p (XEXP (lhs
, 0), XEXP (rhs
, 1)))
9611 other
= XEXP (lhs
, 0), lhs
= XEXP (lhs
, 1), rhs
= XEXP (rhs
, 0);
9612 else if (COMMUTATIVE_ARITH_P (lhs
)
9613 && rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 0)))
9614 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 1);
9615 else if (rtx_equal_p (XEXP (lhs
, 1), XEXP (rhs
, 1)))
9616 other
= XEXP (lhs
, 1), lhs
= XEXP (lhs
, 0), rhs
= XEXP (rhs
, 0);
9620 /* Form the new inner operation, seeing if it simplifies first. */
9621 tem
= simplify_gen_binary (code
, GET_MODE (x
), lhs
, rhs
);
9623 /* There is one exception to the general way of distributing:
9624 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9625 if (code
== XOR
&& inner_code
== IOR
)
9628 other
= simplify_gen_unary (NOT
, GET_MODE (x
), other
, GET_MODE (x
));
9631 /* We may be able to continuing distributing the result, so call
9632 ourselves recursively on the inner operation before forming the
9633 outer operation, which we return. */
9634 return simplify_gen_binary (inner_code
, GET_MODE (x
),
9635 apply_distributive_law (tem
), other
);
9638 /* See if X is of the form (* (+ A B) C), and if so convert to
9639 (+ (* A C) (* B C)) and try to simplify.
9641 Most of the time, this results in no change. However, if some of
9642 the operands are the same or inverses of each other, simplifications
9645 For example, (and (ior A B) (not B)) can occur as the result of
9646 expanding a bit field assignment. When we apply the distributive
9647 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9648 which then simplifies to (and (A (not B))).
9650 Note that no checks happen on the validity of applying the inverse
9651 distributive law. This is pointless since we can do it in the
9652 few places where this routine is called.
9654 N is the index of the term that is decomposed (the arithmetic operation,
9655 i.e. (+ A B) in the first example above). !N is the index of the term that
9656 is distributed, i.e. of C in the first example above. */
9658 distribute_and_simplify_rtx (rtx x
, int n
)
9661 enum rtx_code outer_code
, inner_code
;
9662 rtx decomposed
, distributed
, inner_op0
, inner_op1
, new_op0
, new_op1
, tmp
;
9664 /* Distributivity is not true for floating point as it can change the
9665 value. So we don't do it unless -funsafe-math-optimizations. */
9666 if (FLOAT_MODE_P (GET_MODE (x
))
9667 && ! flag_unsafe_math_optimizations
)
9670 decomposed
= XEXP (x
, n
);
9671 if (!ARITHMETIC_P (decomposed
))
9674 mode
= GET_MODE (x
);
9675 outer_code
= GET_CODE (x
);
9676 distributed
= XEXP (x
, !n
);
9678 inner_code
= GET_CODE (decomposed
);
9679 inner_op0
= XEXP (decomposed
, 0);
9680 inner_op1
= XEXP (decomposed
, 1);
9682 /* Special case (and (xor B C) (not A)), which is equivalent to
9683 (xor (ior A B) (ior A C)) */
9684 if (outer_code
== AND
&& inner_code
== XOR
&& GET_CODE (distributed
) == NOT
)
9686 distributed
= XEXP (distributed
, 0);
9692 /* Distribute the second term. */
9693 new_op0
= simplify_gen_binary (outer_code
, mode
, inner_op0
, distributed
);
9694 new_op1
= simplify_gen_binary (outer_code
, mode
, inner_op1
, distributed
);
9698 /* Distribute the first term. */
9699 new_op0
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op0
);
9700 new_op1
= simplify_gen_binary (outer_code
, mode
, distributed
, inner_op1
);
9703 tmp
= apply_distributive_law (simplify_gen_binary (inner_code
, mode
,
9705 if (GET_CODE (tmp
) != outer_code
9706 && (set_src_cost (tmp
, mode
, optimize_this_for_speed_p
)
9707 < set_src_cost (x
, mode
, optimize_this_for_speed_p
)))
9713 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9714 in MODE. Return an equivalent form, if different from (and VAROP
9715 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9718 simplify_and_const_int_1 (machine_mode mode
, rtx varop
,
9719 unsigned HOST_WIDE_INT constop
)
9721 unsigned HOST_WIDE_INT nonzero
;
9722 unsigned HOST_WIDE_INT orig_constop
;
9727 orig_constop
= constop
;
9728 if (GET_CODE (varop
) == CLOBBER
)
9731 /* Simplify VAROP knowing that we will be only looking at some of the
9734 Note by passing in CONSTOP, we guarantee that the bits not set in
9735 CONSTOP are not significant and will never be examined. We must
9736 ensure that is the case by explicitly masking out those bits
9737 before returning. */
9738 varop
= force_to_mode (varop
, mode
, constop
, 0);
9740 /* If VAROP is a CLOBBER, we will fail so return it. */
9741 if (GET_CODE (varop
) == CLOBBER
)
9744 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9745 to VAROP and return the new constant. */
9746 if (CONST_INT_P (varop
))
9747 return gen_int_mode (INTVAL (varop
) & constop
, mode
);
9749 /* See what bits may be nonzero in VAROP. Unlike the general case of
9750 a call to nonzero_bits, here we don't care about bits outside
9753 nonzero
= nonzero_bits (varop
, mode
) & GET_MODE_MASK (mode
);
9755 /* Turn off all bits in the constant that are known to already be zero.
9756 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9757 which is tested below. */
9761 /* If we don't have any bits left, return zero. */
9765 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9766 a power of two, we can replace this with an ASHIFT. */
9767 if (GET_CODE (varop
) == NEG
&& nonzero_bits (XEXP (varop
, 0), mode
) == 1
9768 && (i
= exact_log2 (constop
)) >= 0)
9769 return simplify_shift_const (NULL_RTX
, ASHIFT
, mode
, XEXP (varop
, 0), i
);
9771 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9772 or XOR, then try to apply the distributive law. This may eliminate
9773 operations if either branch can be simplified because of the AND.
9774 It may also make some cases more complex, but those cases probably
9775 won't match a pattern either with or without this. */
9777 if (GET_CODE (varop
) == IOR
|| GET_CODE (varop
) == XOR
)
9781 apply_distributive_law
9782 (simplify_gen_binary (GET_CODE (varop
), GET_MODE (varop
),
9783 simplify_and_const_int (NULL_RTX
,
9787 simplify_and_const_int (NULL_RTX
,
9792 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9793 the AND and see if one of the operands simplifies to zero. If so, we
9794 may eliminate it. */
9796 if (GET_CODE (varop
) == PLUS
9797 && pow2p_hwi (constop
+ 1))
9801 o0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 0), constop
);
9802 o1
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (varop
, 1), constop
);
9803 if (o0
== const0_rtx
)
9805 if (o1
== const0_rtx
)
9809 /* Make a SUBREG if necessary. If we can't make it, fail. */
9810 varop
= gen_lowpart (mode
, varop
);
9811 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
9814 /* If we are only masking insignificant bits, return VAROP. */
9815 if (constop
== nonzero
)
9818 if (varop
== orig_varop
&& constop
== orig_constop
)
9821 /* Otherwise, return an AND. */
9822 return simplify_gen_binary (AND
, mode
, varop
, gen_int_mode (constop
, mode
));
9826 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9829 Return an equivalent form, if different from X. Otherwise, return X. If
9830 X is zero, we are to always construct the equivalent form. */
9833 simplify_and_const_int (rtx x
, machine_mode mode
, rtx varop
,
9834 unsigned HOST_WIDE_INT constop
)
9836 rtx tem
= simplify_and_const_int_1 (mode
, varop
, constop
);
9841 x
= simplify_gen_binary (AND
, GET_MODE (varop
), varop
,
9842 gen_int_mode (constop
, mode
));
9843 if (GET_MODE (x
) != mode
)
9844 x
= gen_lowpart (mode
, x
);
9848 /* Given a REG, X, compute which bits in X can be nonzero.
9849 We don't care about bits outside of those defined in MODE.
9851 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9852 a shift, AND, or zero_extract, we can do better. */
9855 reg_nonzero_bits_for_combine (const_rtx x
, machine_mode mode
,
9856 const_rtx known_x ATTRIBUTE_UNUSED
,
9857 machine_mode known_mode ATTRIBUTE_UNUSED
,
9858 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED
,
9859 unsigned HOST_WIDE_INT
*nonzero
)
9864 /* If X is a register whose nonzero bits value is current, use it.
9865 Otherwise, if X is a register whose value we can find, use that
9866 value. Otherwise, use the previously-computed global nonzero bits
9867 for this register. */
9869 rsp
= ®_stat
[REGNO (x
)];
9870 if (rsp
->last_set_value
!= 0
9871 && (rsp
->last_set_mode
== mode
9872 || (GET_MODE_CLASS (rsp
->last_set_mode
) == MODE_INT
9873 && GET_MODE_CLASS (mode
) == MODE_INT
))
9874 && ((rsp
->last_set_label
>= label_tick_ebb_start
9875 && rsp
->last_set_label
< label_tick
)
9876 || (rsp
->last_set_label
== label_tick
9877 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9878 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9879 && REGNO (x
) < reg_n_sets_max
9880 && REG_N_SETS (REGNO (x
)) == 1
9882 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9885 unsigned HOST_WIDE_INT mask
= rsp
->last_set_nonzero_bits
;
9887 if (GET_MODE_PRECISION (rsp
->last_set_mode
) < GET_MODE_PRECISION (mode
))
9888 /* We don't know anything about the upper bits. */
9889 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (rsp
->last_set_mode
);
9895 tem
= get_last_value (x
);
9899 if (SHORT_IMMEDIATES_SIGN_EXTEND
)
9900 tem
= sign_extend_short_imm (tem
, GET_MODE (x
),
9901 GET_MODE_PRECISION (mode
));
9905 else if (nonzero_sign_valid
&& rsp
->nonzero_bits
)
9907 unsigned HOST_WIDE_INT mask
= rsp
->nonzero_bits
;
9909 if (GET_MODE_PRECISION (GET_MODE (x
)) < GET_MODE_PRECISION (mode
))
9910 /* We don't know anything about the upper bits. */
9911 mask
|= GET_MODE_MASK (mode
) ^ GET_MODE_MASK (GET_MODE (x
));
9919 /* Return the number of bits at the high-order end of X that are known to
9920 be equal to the sign bit. X will be used in mode MODE; if MODE is
9921 VOIDmode, X will be used in its own mode. The returned value will always
9922 be between 1 and the number of bits in MODE. */
9925 reg_num_sign_bit_copies_for_combine (const_rtx x
, machine_mode mode
,
9926 const_rtx known_x ATTRIBUTE_UNUSED
,
9927 machine_mode known_mode
9929 unsigned int known_ret ATTRIBUTE_UNUSED
,
9930 unsigned int *result
)
9935 rsp
= ®_stat
[REGNO (x
)];
9936 if (rsp
->last_set_value
!= 0
9937 && rsp
->last_set_mode
== mode
9938 && ((rsp
->last_set_label
>= label_tick_ebb_start
9939 && rsp
->last_set_label
< label_tick
)
9940 || (rsp
->last_set_label
== label_tick
9941 && DF_INSN_LUID (rsp
->last_set
) < subst_low_luid
)
9942 || (REGNO (x
) >= FIRST_PSEUDO_REGISTER
9943 && REGNO (x
) < reg_n_sets_max
9944 && REG_N_SETS (REGNO (x
)) == 1
9946 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
9949 *result
= rsp
->last_set_sign_bit_copies
;
9953 tem
= get_last_value (x
);
9957 if (nonzero_sign_valid
&& rsp
->sign_bit_copies
!= 0
9958 && GET_MODE_PRECISION (GET_MODE (x
)) == GET_MODE_PRECISION (mode
))
9959 *result
= rsp
->sign_bit_copies
;
9964 /* Return the number of "extended" bits there are in X, when interpreted
9965 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9966 unsigned quantities, this is the number of high-order zero bits.
9967 For signed quantities, this is the number of copies of the sign bit
9968 minus 1. In both case, this function returns the number of "spare"
9969 bits. For example, if two quantities for which this function returns
9970 at least 1 are added, the addition is known not to overflow.
9972 This function will always return 0 unless called during combine, which
9973 implies that it must be called from a define_split. */
9976 extended_count (const_rtx x
, machine_mode mode
, int unsignedp
)
9978 if (nonzero_sign_valid
== 0)
9982 ? (HWI_COMPUTABLE_MODE_P (mode
)
9983 ? (unsigned int) (GET_MODE_PRECISION (mode
) - 1
9984 - floor_log2 (nonzero_bits (x
, mode
)))
9986 : num_sign_bit_copies (x
, mode
) - 1);
9989 /* This function is called from `simplify_shift_const' to merge two
9990 outer operations. Specifically, we have already found that we need
9991 to perform operation *POP0 with constant *PCONST0 at the outermost
9992 position. We would now like to also perform OP1 with constant CONST1
9993 (with *POP0 being done last).
9995 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9996 the resulting operation. *PCOMP_P is set to 1 if we would need to
9997 complement the innermost operand, otherwise it is unchanged.
9999 MODE is the mode in which the operation will be done. No bits outside
10000 the width of this mode matter. It is assumed that the width of this mode
10001 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10003 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10004 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10005 result is simply *PCONST0.
10007 If the resulting operation cannot be expressed as one operation, we
10008 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10011 merge_outer_ops (enum rtx_code
*pop0
, HOST_WIDE_INT
*pconst0
, enum rtx_code op1
, HOST_WIDE_INT const1
, machine_mode mode
, int *pcomp_p
)
10013 enum rtx_code op0
= *pop0
;
10014 HOST_WIDE_INT const0
= *pconst0
;
10016 const0
&= GET_MODE_MASK (mode
);
10017 const1
&= GET_MODE_MASK (mode
);
10019 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10023 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10026 if (op1
== UNKNOWN
|| op0
== SET
)
10029 else if (op0
== UNKNOWN
)
10030 op0
= op1
, const0
= const1
;
10032 else if (op0
== op1
)
10056 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10057 else if (op0
== PLUS
|| op1
== PLUS
|| op0
== NEG
|| op1
== NEG
)
10060 /* If the two constants aren't the same, we can't do anything. The
10061 remaining six cases can all be done. */
10062 else if (const0
!= const1
)
10070 /* (a & b) | b == b */
10072 else /* op1 == XOR */
10073 /* (a ^ b) | b == a | b */
10079 /* (a & b) ^ b == (~a) & b */
10080 op0
= AND
, *pcomp_p
= 1;
10081 else /* op1 == IOR */
10082 /* (a | b) ^ b == a & ~b */
10083 op0
= AND
, const0
= ~const0
;
10088 /* (a | b) & b == b */
10090 else /* op1 == XOR */
10091 /* (a ^ b) & b) == (~a) & b */
10098 /* Check for NO-OP cases. */
10099 const0
&= GET_MODE_MASK (mode
);
10101 && (op0
== IOR
|| op0
== XOR
|| op0
== PLUS
))
10103 else if (const0
== 0 && op0
== AND
)
10105 else if ((unsigned HOST_WIDE_INT
) const0
== GET_MODE_MASK (mode
)
10111 /* ??? Slightly redundant with the above mask, but not entirely.
10112 Moving this above means we'd have to sign-extend the mode mask
10113 for the final test. */
10114 if (op0
!= UNKNOWN
&& op0
!= NEG
)
10115 *pconst0
= trunc_int_for_mode (const0
, mode
);
10120 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10121 the shift in. The original shift operation CODE is performed on OP in
10122 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10123 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10124 result of the shift is subject to operation OUTER_CODE with operand
10127 static machine_mode
10128 try_widen_shift_mode (enum rtx_code code
, rtx op
, int count
,
10129 machine_mode orig_mode
, machine_mode mode
,
10130 enum rtx_code outer_code
, HOST_WIDE_INT outer_const
)
10132 if (orig_mode
== mode
)
10134 gcc_assert (GET_MODE_PRECISION (mode
) > GET_MODE_PRECISION (orig_mode
));
10136 /* In general we can't perform in wider mode for right shift and rotate. */
10140 /* We can still widen if the bits brought in from the left are identical
10141 to the sign bit of ORIG_MODE. */
10142 if (num_sign_bit_copies (op
, mode
)
10143 > (unsigned) (GET_MODE_PRECISION (mode
)
10144 - GET_MODE_PRECISION (orig_mode
)))
10149 /* Similarly here but with zero bits. */
10150 if (HWI_COMPUTABLE_MODE_P (mode
)
10151 && (nonzero_bits (op
, mode
) & ~GET_MODE_MASK (orig_mode
)) == 0)
10154 /* We can also widen if the bits brought in will be masked off. This
10155 operation is performed in ORIG_MODE. */
10156 if (outer_code
== AND
)
10158 int care_bits
= low_bitmask_len (orig_mode
, outer_const
);
10161 && GET_MODE_PRECISION (orig_mode
) - care_bits
>= count
)
10170 gcc_unreachable ();
10177 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10178 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10179 if we cannot simplify it. Otherwise, return a simplified value.
10181 The shift is normally computed in the widest mode we find in VAROP, as
10182 long as it isn't a different number of words than RESULT_MODE. Exceptions
10183 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10186 simplify_shift_const_1 (enum rtx_code code
, machine_mode result_mode
,
10187 rtx varop
, int orig_count
)
10189 enum rtx_code orig_code
= code
;
10190 rtx orig_varop
= varop
;
10192 machine_mode mode
= result_mode
;
10193 machine_mode shift_mode
, tmode
;
10194 unsigned int mode_words
10195 = (GET_MODE_SIZE (mode
) + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
;
10196 /* We form (outer_op (code varop count) (outer_const)). */
10197 enum rtx_code outer_op
= UNKNOWN
;
10198 HOST_WIDE_INT outer_const
= 0;
10199 int complement_p
= 0;
10202 /* Make sure and truncate the "natural" shift on the way in. We don't
10203 want to do this inside the loop as it makes it more difficult to
10205 if (SHIFT_COUNT_TRUNCATED
)
10206 orig_count
&= GET_MODE_BITSIZE (mode
) - 1;
10208 /* If we were given an invalid count, don't do anything except exactly
10209 what was requested. */
10211 if (orig_count
< 0 || orig_count
>= (int) GET_MODE_PRECISION (mode
))
10214 count
= orig_count
;
10216 /* Unless one of the branches of the `if' in this loop does a `continue',
10217 we will `break' the loop after the `if'. */
10221 /* If we have an operand of (clobber (const_int 0)), fail. */
10222 if (GET_CODE (varop
) == CLOBBER
)
10225 /* Convert ROTATERT to ROTATE. */
10226 if (code
== ROTATERT
)
10228 unsigned int bitsize
= GET_MODE_PRECISION (result_mode
);
10230 if (VECTOR_MODE_P (result_mode
))
10231 count
= bitsize
/ GET_MODE_NUNITS (result_mode
) - count
;
10233 count
= bitsize
- count
;
10236 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
,
10237 mode
, outer_op
, outer_const
);
10239 /* Handle cases where the count is greater than the size of the mode
10240 minus 1. For ASHIFT, use the size minus one as the count (this can
10241 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10242 take the count modulo the size. For other shifts, the result is
10245 Since these shifts are being produced by the compiler by combining
10246 multiple operations, each of which are defined, we know what the
10247 result is supposed to be. */
10249 if (count
> (GET_MODE_PRECISION (shift_mode
) - 1))
10251 if (code
== ASHIFTRT
)
10252 count
= GET_MODE_PRECISION (shift_mode
) - 1;
10253 else if (code
== ROTATE
|| code
== ROTATERT
)
10254 count
%= GET_MODE_PRECISION (shift_mode
);
10257 /* We can't simply return zero because there may be an
10259 varop
= const0_rtx
;
10265 /* If we discovered we had to complement VAROP, leave. Making a NOT
10266 here would cause an infinite loop. */
10270 /* An arithmetic right shift of a quantity known to be -1 or 0
10272 if (code
== ASHIFTRT
10273 && (num_sign_bit_copies (varop
, shift_mode
)
10274 == GET_MODE_PRECISION (shift_mode
)))
10280 /* If we are doing an arithmetic right shift and discarding all but
10281 the sign bit copies, this is equivalent to doing a shift by the
10282 bitsize minus one. Convert it into that shift because it will often
10283 allow other simplifications. */
10285 if (code
== ASHIFTRT
10286 && (count
+ num_sign_bit_copies (varop
, shift_mode
)
10287 >= GET_MODE_PRECISION (shift_mode
)))
10288 count
= GET_MODE_PRECISION (shift_mode
) - 1;
10290 /* We simplify the tests below and elsewhere by converting
10291 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10292 `make_compound_operation' will convert it to an ASHIFTRT for
10293 those machines (such as VAX) that don't have an LSHIFTRT. */
10294 if (code
== ASHIFTRT
10295 && val_signbit_known_clear_p (shift_mode
,
10296 nonzero_bits (varop
, shift_mode
)))
10299 if (((code
== LSHIFTRT
10300 && HWI_COMPUTABLE_MODE_P (shift_mode
)
10301 && !(nonzero_bits (varop
, shift_mode
) >> count
))
10303 && HWI_COMPUTABLE_MODE_P (shift_mode
)
10304 && !((nonzero_bits (varop
, shift_mode
) << count
)
10305 & GET_MODE_MASK (shift_mode
))))
10306 && !side_effects_p (varop
))
10307 varop
= const0_rtx
;
10309 switch (GET_CODE (varop
))
10315 new_rtx
= expand_compound_operation (varop
);
10316 if (new_rtx
!= varop
)
10324 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10325 minus the width of a smaller mode, we can do this with a
10326 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10327 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10328 && ! mode_dependent_address_p (XEXP (varop
, 0),
10329 MEM_ADDR_SPACE (varop
))
10330 && ! MEM_VOLATILE_P (varop
)
10331 && (tmode
= mode_for_size (GET_MODE_BITSIZE (mode
) - count
,
10332 MODE_INT
, 1)) != BLKmode
)
10334 new_rtx
= adjust_address_nv (varop
, tmode
,
10335 BYTES_BIG_ENDIAN
? 0
10336 : count
/ BITS_PER_UNIT
);
10338 varop
= gen_rtx_fmt_e (code
== ASHIFTRT
? SIGN_EXTEND
10339 : ZERO_EXTEND
, mode
, new_rtx
);
10346 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10347 the same number of words as what we've seen so far. Then store
10348 the widest mode in MODE. */
10349 if (subreg_lowpart_p (varop
)
10350 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10351 > GET_MODE_SIZE (GET_MODE (varop
)))
10352 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop
)))
10353 + (UNITS_PER_WORD
- 1)) / UNITS_PER_WORD
)
10355 && GET_MODE_CLASS (GET_MODE (varop
)) == MODE_INT
10356 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop
))) == MODE_INT
)
10358 varop
= SUBREG_REG (varop
);
10359 if (GET_MODE_SIZE (GET_MODE (varop
)) > GET_MODE_SIZE (mode
))
10360 mode
= GET_MODE (varop
);
10366 /* Some machines use MULT instead of ASHIFT because MULT
10367 is cheaper. But it is still better on those machines to
10368 merge two shifts into one. */
10369 if (CONST_INT_P (XEXP (varop
, 1))
10370 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10373 = simplify_gen_binary (ASHIFT
, GET_MODE (varop
),
10375 GEN_INT (exact_log2 (
10376 UINTVAL (XEXP (varop
, 1)))));
10382 /* Similar, for when divides are cheaper. */
10383 if (CONST_INT_P (XEXP (varop
, 1))
10384 && exact_log2 (UINTVAL (XEXP (varop
, 1))) >= 0)
10387 = simplify_gen_binary (LSHIFTRT
, GET_MODE (varop
),
10389 GEN_INT (exact_log2 (
10390 UINTVAL (XEXP (varop
, 1)))));
10396 /* If we are extracting just the sign bit of an arithmetic
10397 right shift, that shift is not needed. However, the sign
10398 bit of a wider mode may be different from what would be
10399 interpreted as the sign bit in a narrower mode, so, if
10400 the result is narrower, don't discard the shift. */
10401 if (code
== LSHIFTRT
10402 && count
== (GET_MODE_BITSIZE (result_mode
) - 1)
10403 && (GET_MODE_BITSIZE (result_mode
)
10404 >= GET_MODE_BITSIZE (GET_MODE (varop
))))
10406 varop
= XEXP (varop
, 0);
10415 /* Here we have two nested shifts. The result is usually the
10416 AND of a new shift with a mask. We compute the result below. */
10417 if (CONST_INT_P (XEXP (varop
, 1))
10418 && INTVAL (XEXP (varop
, 1)) >= 0
10419 && INTVAL (XEXP (varop
, 1)) < GET_MODE_PRECISION (GET_MODE (varop
))
10420 && HWI_COMPUTABLE_MODE_P (result_mode
)
10421 && HWI_COMPUTABLE_MODE_P (mode
)
10422 && !VECTOR_MODE_P (result_mode
))
10424 enum rtx_code first_code
= GET_CODE (varop
);
10425 unsigned int first_count
= INTVAL (XEXP (varop
, 1));
10426 unsigned HOST_WIDE_INT mask
;
10429 /* We have one common special case. We can't do any merging if
10430 the inner code is an ASHIFTRT of a smaller mode. However, if
10431 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10432 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10433 we can convert it to
10434 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10435 This simplifies certain SIGN_EXTEND operations. */
10436 if (code
== ASHIFT
&& first_code
== ASHIFTRT
10437 && count
== (GET_MODE_PRECISION (result_mode
)
10438 - GET_MODE_PRECISION (GET_MODE (varop
))))
10440 /* C3 has the low-order C1 bits zero. */
10442 mask
= GET_MODE_MASK (mode
)
10443 & ~((HOST_WIDE_INT_1U
<< first_count
) - 1);
10445 varop
= simplify_and_const_int (NULL_RTX
, result_mode
,
10446 XEXP (varop
, 0), mask
);
10447 varop
= simplify_shift_const (NULL_RTX
, ASHIFT
, result_mode
,
10449 count
= first_count
;
10454 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10455 than C1 high-order bits equal to the sign bit, we can convert
10456 this to either an ASHIFT or an ASHIFTRT depending on the
10459 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10461 if (code
== ASHIFTRT
&& first_code
== ASHIFT
10462 && GET_MODE (varop
) == shift_mode
10463 && (num_sign_bit_copies (XEXP (varop
, 0), shift_mode
)
10466 varop
= XEXP (varop
, 0);
10467 count
-= first_count
;
10477 /* There are some cases we can't do. If CODE is ASHIFTRT,
10478 we can only do this if FIRST_CODE is also ASHIFTRT.
10480 We can't do the case when CODE is ROTATE and FIRST_CODE is
10483 If the mode of this shift is not the mode of the outer shift,
10484 we can't do this if either shift is a right shift or ROTATE.
10486 Finally, we can't do any of these if the mode is too wide
10487 unless the codes are the same.
10489 Handle the case where the shift codes are the same
10492 if (code
== first_code
)
10494 if (GET_MODE (varop
) != result_mode
10495 && (code
== ASHIFTRT
|| code
== LSHIFTRT
10496 || code
== ROTATE
))
10499 count
+= first_count
;
10500 varop
= XEXP (varop
, 0);
10504 if (code
== ASHIFTRT
10505 || (code
== ROTATE
&& first_code
== ASHIFTRT
)
10506 || GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
10507 || (GET_MODE (varop
) != result_mode
10508 && (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
10509 || first_code
== ROTATE
10510 || code
== ROTATE
)))
10513 /* To compute the mask to apply after the shift, shift the
10514 nonzero bits of the inner shift the same way the
10515 outer shift will. */
10517 mask_rtx
= gen_int_mode (nonzero_bits (varop
, GET_MODE (varop
)),
10521 = simplify_const_binary_operation (code
, result_mode
, mask_rtx
,
10524 /* Give up if we can't compute an outer operation to use. */
10526 || !CONST_INT_P (mask_rtx
)
10527 || ! merge_outer_ops (&outer_op
, &outer_const
, AND
,
10529 result_mode
, &complement_p
))
10532 /* If the shifts are in the same direction, we add the
10533 counts. Otherwise, we subtract them. */
10534 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10535 == (first_code
== ASHIFTRT
|| first_code
== LSHIFTRT
))
10536 count
+= first_count
;
10538 count
-= first_count
;
10540 /* If COUNT is positive, the new shift is usually CODE,
10541 except for the two exceptions below, in which case it is
10542 FIRST_CODE. If the count is negative, FIRST_CODE should
10545 && ((first_code
== ROTATE
&& code
== ASHIFT
)
10546 || (first_code
== ASHIFTRT
&& code
== LSHIFTRT
)))
10548 else if (count
< 0)
10549 code
= first_code
, count
= -count
;
10551 varop
= XEXP (varop
, 0);
10555 /* If we have (A << B << C) for any shift, we can convert this to
10556 (A << C << B). This wins if A is a constant. Only try this if
10557 B is not a constant. */
10559 else if (GET_CODE (varop
) == code
10560 && CONST_INT_P (XEXP (varop
, 0))
10561 && !CONST_INT_P (XEXP (varop
, 1)))
10563 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10564 sure the result will be masked. See PR70222. */
10565 if (code
== LSHIFTRT
10566 && mode
!= result_mode
10567 && !merge_outer_ops (&outer_op
, &outer_const
, AND
,
10568 GET_MODE_MASK (result_mode
)
10569 >> orig_count
, result_mode
,
10572 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10573 up outer sign extension (often left and right shift) is
10574 hardly more efficient than the original. See PR70429. */
10575 if (code
== ASHIFTRT
&& mode
!= result_mode
)
10578 rtx new_rtx
= simplify_const_binary_operation (code
, mode
,
10581 varop
= gen_rtx_fmt_ee (code
, mode
, new_rtx
, XEXP (varop
, 1));
10588 if (VECTOR_MODE_P (mode
))
10591 /* Make this fit the case below. */
10592 varop
= gen_rtx_XOR (mode
, XEXP (varop
, 0), constm1_rtx
);
10598 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10599 with C the size of VAROP - 1 and the shift is logical if
10600 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10601 we have an (le X 0) operation. If we have an arithmetic shift
10602 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10603 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10605 if (GET_CODE (varop
) == IOR
&& GET_CODE (XEXP (varop
, 0)) == PLUS
10606 && XEXP (XEXP (varop
, 0), 1) == constm1_rtx
10607 && (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10608 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10609 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10610 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10613 varop
= gen_rtx_LE (GET_MODE (varop
), XEXP (varop
, 1),
10616 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10617 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10622 /* If we have (shift (logical)), move the logical to the outside
10623 to allow it to possibly combine with another logical and the
10624 shift to combine with another shift. This also canonicalizes to
10625 what a ZERO_EXTRACT looks like. Also, some machines have
10626 (and (shift)) insns. */
10628 if (CONST_INT_P (XEXP (varop
, 1))
10629 /* We can't do this if we have (ashiftrt (xor)) and the
10630 constant has its sign bit set in shift_mode with shift_mode
10631 wider than result_mode. */
10632 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10633 && result_mode
!= shift_mode
10634 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10636 && (new_rtx
= simplify_const_binary_operation
10637 (code
, result_mode
,
10638 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10639 GEN_INT (count
))) != 0
10640 && CONST_INT_P (new_rtx
)
10641 && merge_outer_ops (&outer_op
, &outer_const
, GET_CODE (varop
),
10642 INTVAL (new_rtx
), result_mode
, &complement_p
))
10644 varop
= XEXP (varop
, 0);
10648 /* If we can't do that, try to simplify the shift in each arm of the
10649 logical expression, make a new logical expression, and apply
10650 the inverse distributive law. This also can't be done for
10651 (ashiftrt (xor)) where we've widened the shift and the constant
10652 changes the sign bit. */
10653 if (CONST_INT_P (XEXP (varop
, 1))
10654 && !(code
== ASHIFTRT
&& GET_CODE (varop
) == XOR
10655 && result_mode
!= shift_mode
10656 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop
, 1)),
10659 rtx lhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10660 XEXP (varop
, 0), count
);
10661 rtx rhs
= simplify_shift_const (NULL_RTX
, code
, shift_mode
,
10662 XEXP (varop
, 1), count
);
10664 varop
= simplify_gen_binary (GET_CODE (varop
), shift_mode
,
10666 varop
= apply_distributive_law (varop
);
10674 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10675 says that the sign bit can be tested, FOO has mode MODE, C is
10676 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10677 that may be nonzero. */
10678 if (code
== LSHIFTRT
10679 && XEXP (varop
, 1) == const0_rtx
10680 && GET_MODE (XEXP (varop
, 0)) == result_mode
10681 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10682 && HWI_COMPUTABLE_MODE_P (result_mode
)
10683 && STORE_FLAG_VALUE
== -1
10684 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10685 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10688 varop
= XEXP (varop
, 0);
10695 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10696 than the number of bits in the mode is equivalent to A. */
10697 if (code
== LSHIFTRT
10698 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10699 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1)
10701 varop
= XEXP (varop
, 0);
10706 /* NEG commutes with ASHIFT since it is multiplication. Move the
10707 NEG outside to allow shifts to combine. */
10709 && merge_outer_ops (&outer_op
, &outer_const
, NEG
, 0, result_mode
,
10712 varop
= XEXP (varop
, 0);
10718 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10719 is one less than the number of bits in the mode is
10720 equivalent to (xor A 1). */
10721 if (code
== LSHIFTRT
10722 && count
== (GET_MODE_PRECISION (result_mode
) - 1)
10723 && XEXP (varop
, 1) == constm1_rtx
10724 && nonzero_bits (XEXP (varop
, 0), result_mode
) == 1
10725 && merge_outer_ops (&outer_op
, &outer_const
, XOR
, 1, result_mode
,
10729 varop
= XEXP (varop
, 0);
10733 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10734 that might be nonzero in BAR are those being shifted out and those
10735 bits are known zero in FOO, we can replace the PLUS with FOO.
10736 Similarly in the other operand order. This code occurs when
10737 we are computing the size of a variable-size array. */
10739 if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10740 && count
< HOST_BITS_PER_WIDE_INT
10741 && nonzero_bits (XEXP (varop
, 1), result_mode
) >> count
== 0
10742 && (nonzero_bits (XEXP (varop
, 1), result_mode
)
10743 & nonzero_bits (XEXP (varop
, 0), result_mode
)) == 0)
10745 varop
= XEXP (varop
, 0);
10748 else if ((code
== ASHIFTRT
|| code
== LSHIFTRT
)
10749 && count
< HOST_BITS_PER_WIDE_INT
10750 && HWI_COMPUTABLE_MODE_P (result_mode
)
10751 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10753 && 0 == (nonzero_bits (XEXP (varop
, 0), result_mode
)
10754 & nonzero_bits (XEXP (varop
, 1),
10757 varop
= XEXP (varop
, 1);
10761 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10763 && CONST_INT_P (XEXP (varop
, 1))
10764 && (new_rtx
= simplify_const_binary_operation
10765 (ASHIFT
, result_mode
,
10766 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10767 GEN_INT (count
))) != 0
10768 && CONST_INT_P (new_rtx
)
10769 && merge_outer_ops (&outer_op
, &outer_const
, PLUS
,
10770 INTVAL (new_rtx
), result_mode
, &complement_p
))
10772 varop
= XEXP (varop
, 0);
10776 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10777 signbit', and attempt to change the PLUS to an XOR and move it to
10778 the outer operation as is done above in the AND/IOR/XOR case
10779 leg for shift(logical). See details in logical handling above
10780 for reasoning in doing so. */
10781 if (code
== LSHIFTRT
10782 && CONST_INT_P (XEXP (varop
, 1))
10783 && mode_signbit_p (result_mode
, XEXP (varop
, 1))
10784 && (new_rtx
= simplify_const_binary_operation
10785 (code
, result_mode
,
10786 gen_int_mode (INTVAL (XEXP (varop
, 1)), result_mode
),
10787 GEN_INT (count
))) != 0
10788 && CONST_INT_P (new_rtx
)
10789 && merge_outer_ops (&outer_op
, &outer_const
, XOR
,
10790 INTVAL (new_rtx
), result_mode
, &complement_p
))
10792 varop
= XEXP (varop
, 0);
10799 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10800 with C the size of VAROP - 1 and the shift is logical if
10801 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10802 we have a (gt X 0) operation. If the shift is arithmetic with
10803 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10804 we have a (neg (gt X 0)) operation. */
10806 if ((STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
10807 && GET_CODE (XEXP (varop
, 0)) == ASHIFTRT
10808 && count
== (GET_MODE_PRECISION (GET_MODE (varop
)) - 1)
10809 && (code
== LSHIFTRT
|| code
== ASHIFTRT
)
10810 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10811 && INTVAL (XEXP (XEXP (varop
, 0), 1)) == count
10812 && rtx_equal_p (XEXP (XEXP (varop
, 0), 0), XEXP (varop
, 1)))
10815 varop
= gen_rtx_GT (GET_MODE (varop
), XEXP (varop
, 1),
10818 if (STORE_FLAG_VALUE
== 1 ? code
== ASHIFTRT
: code
== LSHIFTRT
)
10819 varop
= gen_rtx_NEG (GET_MODE (varop
), varop
);
10826 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10827 if the truncate does not affect the value. */
10828 if (code
== LSHIFTRT
10829 && GET_CODE (XEXP (varop
, 0)) == LSHIFTRT
10830 && CONST_INT_P (XEXP (XEXP (varop
, 0), 1))
10831 && (INTVAL (XEXP (XEXP (varop
, 0), 1))
10832 >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop
, 0)))
10833 - GET_MODE_PRECISION (GET_MODE (varop
)))))
10835 rtx varop_inner
= XEXP (varop
, 0);
10838 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner
),
10839 XEXP (varop_inner
, 0),
10841 (count
+ INTVAL (XEXP (varop_inner
, 1))));
10842 varop
= gen_rtx_TRUNCATE (GET_MODE (varop
), varop_inner
);
10855 shift_mode
= try_widen_shift_mode (code
, varop
, count
, result_mode
, mode
,
10856 outer_op
, outer_const
);
10858 /* We have now finished analyzing the shift. The result should be
10859 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10860 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10861 to the result of the shift. OUTER_CONST is the relevant constant,
10862 but we must turn off all bits turned off in the shift. */
10864 if (outer_op
== UNKNOWN
10865 && orig_code
== code
&& orig_count
== count
10866 && varop
== orig_varop
10867 && shift_mode
== GET_MODE (varop
))
10870 /* Make a SUBREG if necessary. If we can't make it, fail. */
10871 varop
= gen_lowpart (shift_mode
, varop
);
10872 if (varop
== NULL_RTX
|| GET_CODE (varop
) == CLOBBER
)
10875 /* If we have an outer operation and we just made a shift, it is
10876 possible that we could have simplified the shift were it not
10877 for the outer operation. So try to do the simplification
10880 if (outer_op
!= UNKNOWN
)
10881 x
= simplify_shift_const_1 (code
, shift_mode
, varop
, count
);
10886 x
= simplify_gen_binary (code
, shift_mode
, varop
, GEN_INT (count
));
10888 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10889 turn off all the bits that the shift would have turned off. */
10890 if (orig_code
== LSHIFTRT
&& result_mode
!= shift_mode
)
10891 x
= simplify_and_const_int (NULL_RTX
, shift_mode
, x
,
10892 GET_MODE_MASK (result_mode
) >> orig_count
);
10894 /* Do the remainder of the processing in RESULT_MODE. */
10895 x
= gen_lowpart_or_truncate (result_mode
, x
);
10897 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10900 x
= simplify_gen_unary (NOT
, result_mode
, x
, result_mode
);
10902 if (outer_op
!= UNKNOWN
)
10904 if (GET_RTX_CLASS (outer_op
) != RTX_UNARY
10905 && GET_MODE_PRECISION (result_mode
) < HOST_BITS_PER_WIDE_INT
)
10906 outer_const
= trunc_int_for_mode (outer_const
, result_mode
);
10908 if (outer_op
== AND
)
10909 x
= simplify_and_const_int (NULL_RTX
, result_mode
, x
, outer_const
);
10910 else if (outer_op
== SET
)
10912 /* This means that we have determined that the result is
10913 equivalent to a constant. This should be rare. */
10914 if (!side_effects_p (x
))
10915 x
= GEN_INT (outer_const
);
10917 else if (GET_RTX_CLASS (outer_op
) == RTX_UNARY
)
10918 x
= simplify_gen_unary (outer_op
, result_mode
, x
, result_mode
);
10920 x
= simplify_gen_binary (outer_op
, result_mode
, x
,
10921 GEN_INT (outer_const
));
10927 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10928 The result of the shift is RESULT_MODE. If we cannot simplify it,
10929 return X or, if it is NULL, synthesize the expression with
10930 simplify_gen_binary. Otherwise, return a simplified value.
10932 The shift is normally computed in the widest mode we find in VAROP, as
10933 long as it isn't a different number of words than RESULT_MODE. Exceptions
10934 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10937 simplify_shift_const (rtx x
, enum rtx_code code
, machine_mode result_mode
,
10938 rtx varop
, int count
)
10940 rtx tem
= simplify_shift_const_1 (code
, result_mode
, varop
, count
);
10945 x
= simplify_gen_binary (code
, GET_MODE (varop
), varop
, GEN_INT (count
));
10946 if (GET_MODE (x
) != result_mode
)
10947 x
= gen_lowpart (result_mode
, x
);
10952 /* A subroutine of recog_for_combine. See there for arguments and
10956 recog_for_combine_1 (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
10958 rtx pat
= *pnewpat
;
10959 rtx pat_without_clobbers
;
10960 int insn_code_number
;
10961 int num_clobbers_to_add
= 0;
10963 rtx notes
= NULL_RTX
;
10964 rtx old_notes
, old_pat
;
10967 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10968 we use to indicate that something didn't match. If we find such a
10969 thing, force rejection. */
10970 if (GET_CODE (pat
) == PARALLEL
)
10971 for (i
= XVECLEN (pat
, 0) - 1; i
>= 0; i
--)
10972 if (GET_CODE (XVECEXP (pat
, 0, i
)) == CLOBBER
10973 && XEXP (XVECEXP (pat
, 0, i
), 0) == const0_rtx
)
10976 old_pat
= PATTERN (insn
);
10977 old_notes
= REG_NOTES (insn
);
10978 PATTERN (insn
) = pat
;
10979 REG_NOTES (insn
) = NULL_RTX
;
10981 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
10982 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
10984 if (insn_code_number
< 0)
10985 fputs ("Failed to match this instruction:\n", dump_file
);
10987 fputs ("Successfully matched this instruction:\n", dump_file
);
10988 print_rtl_single (dump_file
, pat
);
10991 /* If it isn't, there is the possibility that we previously had an insn
10992 that clobbered some register as a side effect, but the combined
10993 insn doesn't need to do that. So try once more without the clobbers
10994 unless this represents an ASM insn. */
10996 if (insn_code_number
< 0 && ! check_asm_operands (pat
)
10997 && GET_CODE (pat
) == PARALLEL
)
11001 for (pos
= 0, i
= 0; i
< XVECLEN (pat
, 0); i
++)
11002 if (GET_CODE (XVECEXP (pat
, 0, i
)) != CLOBBER
)
11005 SUBST (XVECEXP (pat
, 0, pos
), XVECEXP (pat
, 0, i
));
11009 SUBST_INT (XVECLEN (pat
, 0), pos
);
11012 pat
= XVECEXP (pat
, 0, 0);
11014 PATTERN (insn
) = pat
;
11015 insn_code_number
= recog (pat
, insn
, &num_clobbers_to_add
);
11016 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11018 if (insn_code_number
< 0)
11019 fputs ("Failed to match this instruction:\n", dump_file
);
11021 fputs ("Successfully matched this instruction:\n", dump_file
);
11022 print_rtl_single (dump_file
, pat
);
11026 pat_without_clobbers
= pat
;
11028 PATTERN (insn
) = old_pat
;
11029 REG_NOTES (insn
) = old_notes
;
11031 /* Recognize all noop sets, these will be killed by followup pass. */
11032 if (insn_code_number
< 0 && GET_CODE (pat
) == SET
&& set_noop_p (pat
))
11033 insn_code_number
= NOOP_MOVE_INSN_CODE
, num_clobbers_to_add
= 0;
11035 /* If we had any clobbers to add, make a new pattern than contains
11036 them. Then check to make sure that all of them are dead. */
11037 if (num_clobbers_to_add
)
11039 rtx newpat
= gen_rtx_PARALLEL (VOIDmode
,
11040 rtvec_alloc (GET_CODE (pat
) == PARALLEL
11041 ? (XVECLEN (pat
, 0)
11042 + num_clobbers_to_add
)
11043 : num_clobbers_to_add
+ 1));
11045 if (GET_CODE (pat
) == PARALLEL
)
11046 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11047 XVECEXP (newpat
, 0, i
) = XVECEXP (pat
, 0, i
);
11049 XVECEXP (newpat
, 0, 0) = pat
;
11051 add_clobbers (newpat
, insn_code_number
);
11053 for (i
= XVECLEN (newpat
, 0) - num_clobbers_to_add
;
11054 i
< XVECLEN (newpat
, 0); i
++)
11056 if (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0))
11057 && ! reg_dead_at_p (XEXP (XVECEXP (newpat
, 0, i
), 0), insn
))
11059 if (GET_CODE (XEXP (XVECEXP (newpat
, 0, i
), 0)) != SCRATCH
)
11061 gcc_assert (REG_P (XEXP (XVECEXP (newpat
, 0, i
), 0)));
11062 notes
= alloc_reg_note (REG_UNUSED
,
11063 XEXP (XVECEXP (newpat
, 0, i
), 0), notes
);
11069 if (insn_code_number
>= 0
11070 && insn_code_number
!= NOOP_MOVE_INSN_CODE
)
11072 old_pat
= PATTERN (insn
);
11073 old_notes
= REG_NOTES (insn
);
11074 old_icode
= INSN_CODE (insn
);
11075 PATTERN (insn
) = pat
;
11076 REG_NOTES (insn
) = notes
;
11078 /* Allow targets to reject combined insn. */
11079 if (!targetm
.legitimate_combined_insn (insn
))
11081 if (dump_file
&& (dump_flags
& TDF_DETAILS
))
11082 fputs ("Instruction not appropriate for target.",
11085 /* Callers expect recog_for_combine to strip
11086 clobbers from the pattern on failure. */
11087 pat
= pat_without_clobbers
;
11090 insn_code_number
= -1;
11093 PATTERN (insn
) = old_pat
;
11094 REG_NOTES (insn
) = old_notes
;
11095 INSN_CODE (insn
) = old_icode
;
11101 return insn_code_number
;
11104 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11105 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11106 Return whether anything was so changed. */
11109 change_zero_ext (rtx
*src
)
11111 bool changed
= false;
11113 subrtx_ptr_iterator::array_type array
;
11114 FOR_EACH_SUBRTX_PTR (iter
, array
, src
, NONCONST
)
11117 machine_mode mode
= GET_MODE (x
);
11120 if (GET_CODE (x
) == ZERO_EXTRACT
11121 && CONST_INT_P (XEXP (x
, 1))
11122 && CONST_INT_P (XEXP (x
, 2))
11123 && GET_MODE (XEXP (x
, 0)) == mode
)
11125 size
= INTVAL (XEXP (x
, 1));
11127 int start
= INTVAL (XEXP (x
, 2));
11128 if (BITS_BIG_ENDIAN
)
11129 start
= GET_MODE_PRECISION (mode
) - size
- start
;
11131 x
= simplify_gen_binary (LSHIFTRT
, mode
,
11132 XEXP (x
, 0), GEN_INT (start
));
11134 else if (GET_CODE (x
) == ZERO_EXTEND
11135 && SCALAR_INT_MODE_P (mode
)
11136 && GET_CODE (XEXP (x
, 0)) == SUBREG
11137 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == mode
11138 && subreg_lowpart_p (XEXP (x
, 0)))
11140 size
= GET_MODE_PRECISION (GET_MODE (XEXP (x
, 0)));
11141 x
= SUBREG_REG (XEXP (x
, 0));
11146 wide_int mask
= wi::mask (size
, false, GET_MODE_PRECISION (mode
));
11147 x
= gen_rtx_AND (mode
, x
, immed_wide_int_const (mask
, mode
));
11156 /* Like recog, but we receive the address of a pointer to a new pattern.
11157 We try to match the rtx that the pointer points to.
11158 If that fails, we may try to modify or replace the pattern,
11159 storing the replacement into the same pointer object.
11161 Modifications include deletion or addition of CLOBBERs. If the
11162 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11163 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11164 (and undo if that fails).
11166 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11167 the CLOBBERs are placed.
11169 The value is the final insn code from the pattern ultimately matched,
11173 recog_for_combine (rtx
*pnewpat
, rtx_insn
*insn
, rtx
*pnotes
)
11175 rtx pat
= PATTERN (insn
);
11176 int insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11177 if (insn_code_number
>= 0 || check_asm_operands (pat
))
11178 return insn_code_number
;
11180 void *marker
= get_undo_marker ();
11181 bool changed
= false;
11183 if (GET_CODE (pat
) == SET
)
11184 changed
= change_zero_ext (&SET_SRC (pat
));
11185 else if (GET_CODE (pat
) == PARALLEL
)
11188 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
11190 rtx set
= XVECEXP (pat
, 0, i
);
11191 if (GET_CODE (set
) == SET
)
11192 changed
|= change_zero_ext (&SET_SRC (set
));
11198 insn_code_number
= recog_for_combine_1 (pnewpat
, insn
, pnotes
);
11200 if (insn_code_number
< 0)
11201 undo_to_marker (marker
);
11204 return insn_code_number
;
11207 /* Like gen_lowpart_general but for use by combine. In combine it
11208 is not possible to create any new pseudoregs. However, it is
11209 safe to create invalid memory addresses, because combine will
11210 try to recognize them and all they will do is make the combine
11213 If for some reason this cannot do its job, an rtx
11214 (clobber (const_int 0)) is returned.
11215 An insn containing that will not be recognized. */
11218 gen_lowpart_for_combine (machine_mode omode
, rtx x
)
11220 machine_mode imode
= GET_MODE (x
);
11221 unsigned int osize
= GET_MODE_SIZE (omode
);
11222 unsigned int isize
= GET_MODE_SIZE (imode
);
11225 if (omode
== imode
)
11228 /* We can only support MODE being wider than a word if X is a
11229 constant integer or has a mode the same size. */
11230 if (GET_MODE_SIZE (omode
) > UNITS_PER_WORD
11231 && ! (CONST_SCALAR_INT_P (x
) || isize
== osize
))
11234 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11235 won't know what to do. So we will strip off the SUBREG here and
11236 process normally. */
11237 if (GET_CODE (x
) == SUBREG
&& MEM_P (SUBREG_REG (x
)))
11239 x
= SUBREG_REG (x
);
11241 /* For use in case we fall down into the address adjustments
11242 further below, we need to adjust the known mode and size of
11243 x; imode and isize, since we just adjusted x. */
11244 imode
= GET_MODE (x
);
11246 if (imode
== omode
)
11249 isize
= GET_MODE_SIZE (imode
);
11252 result
= gen_lowpart_common (omode
, x
);
11261 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11263 if (MEM_VOLATILE_P (x
)
11264 || mode_dependent_address_p (XEXP (x
, 0), MEM_ADDR_SPACE (x
)))
11267 /* If we want to refer to something bigger than the original memref,
11268 generate a paradoxical subreg instead. That will force a reload
11269 of the original memref X. */
11271 return gen_rtx_SUBREG (omode
, x
, 0);
11273 if (WORDS_BIG_ENDIAN
)
11274 offset
= MAX (isize
, UNITS_PER_WORD
) - MAX (osize
, UNITS_PER_WORD
);
11276 /* Adjust the address so that the address-after-the-data is
11278 if (BYTES_BIG_ENDIAN
)
11279 offset
-= MIN (UNITS_PER_WORD
, osize
) - MIN (UNITS_PER_WORD
, isize
);
11281 return adjust_address_nv (x
, omode
, offset
);
11284 /* If X is a comparison operator, rewrite it in a new mode. This
11285 probably won't match, but may allow further simplifications. */
11286 else if (COMPARISON_P (x
))
11287 return gen_rtx_fmt_ee (GET_CODE (x
), omode
, XEXP (x
, 0), XEXP (x
, 1));
11289 /* If we couldn't simplify X any other way, just enclose it in a
11290 SUBREG. Normally, this SUBREG won't match, but some patterns may
11291 include an explicit SUBREG or we may simplify it further in combine. */
11296 if (imode
== VOIDmode
)
11298 imode
= int_mode_for_mode (omode
);
11299 x
= gen_lowpart_common (imode
, x
);
11303 res
= lowpart_subreg (omode
, x
, imode
);
11309 return gen_rtx_CLOBBER (omode
, const0_rtx
);
11312 /* Try to simplify a comparison between OP0 and a constant OP1,
11313 where CODE is the comparison code that will be tested, into a
11314 (CODE OP0 const0_rtx) form.
11316 The result is a possibly different comparison code to use.
11317 *POP1 may be updated. */
11319 static enum rtx_code
11320 simplify_compare_const (enum rtx_code code
, machine_mode mode
,
11321 rtx op0
, rtx
*pop1
)
11323 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11324 HOST_WIDE_INT const_op
= INTVAL (*pop1
);
11326 /* Get the constant we are comparing against and turn off all bits
11327 not on in our mode. */
11328 if (mode
!= VOIDmode
)
11329 const_op
= trunc_int_for_mode (const_op
, mode
);
11331 /* If we are comparing against a constant power of two and the value
11332 being compared can only have that single bit nonzero (e.g., it was
11333 `and'ed with that bit), we can replace this with a comparison
11336 && (code
== EQ
|| code
== NE
|| code
== GE
|| code
== GEU
11337 || code
== LT
|| code
== LTU
)
11338 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11339 && pow2p_hwi (const_op
& GET_MODE_MASK (mode
))
11340 && (nonzero_bits (op0
, mode
)
11341 == (unsigned HOST_WIDE_INT
) (const_op
& GET_MODE_MASK (mode
))))
11343 code
= (code
== EQ
|| code
== GE
|| code
== GEU
? NE
: EQ
);
11347 /* Similarly, if we are comparing a value known to be either -1 or
11348 0 with -1, change it to the opposite comparison against zero. */
11350 && (code
== EQ
|| code
== NE
|| code
== GT
|| code
== LE
11351 || code
== GEU
|| code
== LTU
)
11352 && num_sign_bit_copies (op0
, mode
) == mode_width
)
11354 code
= (code
== EQ
|| code
== LE
|| code
== GEU
? NE
: EQ
);
11358 /* Do some canonicalizations based on the comparison code. We prefer
11359 comparisons against zero and then prefer equality comparisons.
11360 If we can reduce the size of a constant, we will do that too. */
11364 /* < C is equivalent to <= (C - 1) */
11369 /* ... fall through to LE case below. */
11375 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11382 /* If we are doing a <= 0 comparison on a value known to have
11383 a zero sign bit, we can replace this with == 0. */
11384 else if (const_op
== 0
11385 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11386 && (nonzero_bits (op0
, mode
)
11387 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
11393 /* >= C is equivalent to > (C - 1). */
11398 /* ... fall through to GT below. */
11404 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11411 /* If we are doing a > 0 comparison on a value known to have
11412 a zero sign bit, we can replace this with != 0. */
11413 else if (const_op
== 0
11414 && mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11415 && (nonzero_bits (op0
, mode
)
11416 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
11422 /* < C is equivalent to <= (C - 1). */
11427 /* ... fall through ... */
11429 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11430 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11431 && (unsigned HOST_WIDE_INT
) const_op
11432 == HOST_WIDE_INT_1U
<< (mode_width
- 1))
11442 /* unsigned <= 0 is equivalent to == 0 */
11445 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11446 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11447 && (unsigned HOST_WIDE_INT
) const_op
11448 == (HOST_WIDE_INT_1U
<< (mode_width
- 1)) - 1)
11456 /* >= C is equivalent to > (C - 1). */
11461 /* ... fall through ... */
11464 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11465 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11466 && (unsigned HOST_WIDE_INT
) const_op
11467 == HOST_WIDE_INT_1U
<< (mode_width
- 1))
11477 /* unsigned > 0 is equivalent to != 0 */
11480 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11481 else if (mode_width
- 1 < HOST_BITS_PER_WIDE_INT
11482 && (unsigned HOST_WIDE_INT
) const_op
11483 == (HOST_WIDE_INT_1U
<< (mode_width
- 1)) - 1)
11494 *pop1
= GEN_INT (const_op
);
11498 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11499 comparison code that will be tested.
11501 The result is a possibly different comparison code to use. *POP0 and
11502 *POP1 may be updated.
11504 It is possible that we might detect that a comparison is either always
11505 true or always false. However, we do not perform general constant
11506 folding in combine, so this knowledge isn't useful. Such tautologies
11507 should have been detected earlier. Hence we ignore all such cases. */
11509 static enum rtx_code
11510 simplify_comparison (enum rtx_code code
, rtx
*pop0
, rtx
*pop1
)
11516 machine_mode mode
, tmode
;
11518 /* Try a few ways of applying the same transformation to both operands. */
11521 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11522 so check specially. */
11523 if (!WORD_REGISTER_OPERATIONS
11524 && code
!= GTU
&& code
!= GEU
&& code
!= LTU
&& code
!= LEU
11525 && GET_CODE (op0
) == ASHIFTRT
&& GET_CODE (op1
) == ASHIFTRT
11526 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
11527 && GET_CODE (XEXP (op1
, 0)) == ASHIFT
11528 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == SUBREG
11529 && GET_CODE (XEXP (XEXP (op1
, 0), 0)) == SUBREG
11530 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0)))
11531 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1
, 0), 0))))
11532 && CONST_INT_P (XEXP (op0
, 1))
11533 && XEXP (op0
, 1) == XEXP (op1
, 1)
11534 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
11535 && XEXP (op0
, 1) == XEXP (XEXP (op1
, 0), 1)
11536 && (INTVAL (XEXP (op0
, 1))
11537 == (GET_MODE_PRECISION (GET_MODE (op0
))
11538 - (GET_MODE_PRECISION
11539 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0
, 0), 0))))))))
11541 op0
= SUBREG_REG (XEXP (XEXP (op0
, 0), 0));
11542 op1
= SUBREG_REG (XEXP (XEXP (op1
, 0), 0));
11545 /* If both operands are the same constant shift, see if we can ignore the
11546 shift. We can if the shift is a rotate or if the bits shifted out of
11547 this shift are known to be zero for both inputs and if the type of
11548 comparison is compatible with the shift. */
11549 if (GET_CODE (op0
) == GET_CODE (op1
)
11550 && HWI_COMPUTABLE_MODE_P (GET_MODE (op0
))
11551 && ((GET_CODE (op0
) == ROTATE
&& (code
== NE
|| code
== EQ
))
11552 || ((GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFT
)
11553 && (code
!= GT
&& code
!= LT
&& code
!= GE
&& code
!= LE
))
11554 || (GET_CODE (op0
) == ASHIFTRT
11555 && (code
!= GTU
&& code
!= LTU
11556 && code
!= GEU
&& code
!= LEU
)))
11557 && CONST_INT_P (XEXP (op0
, 1))
11558 && INTVAL (XEXP (op0
, 1)) >= 0
11559 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
11560 && XEXP (op0
, 1) == XEXP (op1
, 1))
11562 machine_mode mode
= GET_MODE (op0
);
11563 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11564 int shift_count
= INTVAL (XEXP (op0
, 1));
11566 if (GET_CODE (op0
) == LSHIFTRT
|| GET_CODE (op0
) == ASHIFTRT
)
11567 mask
&= (mask
>> shift_count
) << shift_count
;
11568 else if (GET_CODE (op0
) == ASHIFT
)
11569 mask
= (mask
& (mask
<< shift_count
)) >> shift_count
;
11571 if ((nonzero_bits (XEXP (op0
, 0), mode
) & ~mask
) == 0
11572 && (nonzero_bits (XEXP (op1
, 0), mode
) & ~mask
) == 0)
11573 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0);
11578 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11579 SUBREGs are of the same mode, and, in both cases, the AND would
11580 be redundant if the comparison was done in the narrower mode,
11581 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11582 and the operand's possibly nonzero bits are 0xffffff01; in that case
11583 if we only care about QImode, we don't need the AND). This case
11584 occurs if the output mode of an scc insn is not SImode and
11585 STORE_FLAG_VALUE == 1 (e.g., the 386).
11587 Similarly, check for a case where the AND's are ZERO_EXTEND
11588 operations from some narrower mode even though a SUBREG is not
11591 else if (GET_CODE (op0
) == AND
&& GET_CODE (op1
) == AND
11592 && CONST_INT_P (XEXP (op0
, 1))
11593 && CONST_INT_P (XEXP (op1
, 1)))
11595 rtx inner_op0
= XEXP (op0
, 0);
11596 rtx inner_op1
= XEXP (op1
, 0);
11597 HOST_WIDE_INT c0
= INTVAL (XEXP (op0
, 1));
11598 HOST_WIDE_INT c1
= INTVAL (XEXP (op1
, 1));
11601 if (paradoxical_subreg_p (inner_op0
)
11602 && GET_CODE (inner_op1
) == SUBREG
11603 && (GET_MODE (SUBREG_REG (inner_op0
))
11604 == GET_MODE (SUBREG_REG (inner_op1
)))
11605 && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0
)))
11606 <= HOST_BITS_PER_WIDE_INT
)
11607 && (0 == ((~c0
) & nonzero_bits (SUBREG_REG (inner_op0
),
11608 GET_MODE (SUBREG_REG (inner_op0
)))))
11609 && (0 == ((~c1
) & nonzero_bits (SUBREG_REG (inner_op1
),
11610 GET_MODE (SUBREG_REG (inner_op1
))))))
11612 op0
= SUBREG_REG (inner_op0
);
11613 op1
= SUBREG_REG (inner_op1
);
11615 /* The resulting comparison is always unsigned since we masked
11616 off the original sign bit. */
11617 code
= unsigned_condition (code
);
11623 for (tmode
= GET_CLASS_NARROWEST_MODE
11624 (GET_MODE_CLASS (GET_MODE (op0
)));
11625 tmode
!= GET_MODE (op0
); tmode
= GET_MODE_WIDER_MODE (tmode
))
11626 if ((unsigned HOST_WIDE_INT
) c0
== GET_MODE_MASK (tmode
))
11628 op0
= gen_lowpart_or_truncate (tmode
, inner_op0
);
11629 op1
= gen_lowpart_or_truncate (tmode
, inner_op1
);
11630 code
= unsigned_condition (code
);
11639 /* If both operands are NOT, we can strip off the outer operation
11640 and adjust the comparison code for swapped operands; similarly for
11641 NEG, except that this must be an equality comparison. */
11642 else if ((GET_CODE (op0
) == NOT
&& GET_CODE (op1
) == NOT
)
11643 || (GET_CODE (op0
) == NEG
&& GET_CODE (op1
) == NEG
11644 && (code
== EQ
|| code
== NE
)))
11645 op0
= XEXP (op0
, 0), op1
= XEXP (op1
, 0), code
= swap_condition (code
);
11651 /* If the first operand is a constant, swap the operands and adjust the
11652 comparison code appropriately, but don't do this if the second operand
11653 is already a constant integer. */
11654 if (swap_commutative_operands_p (op0
, op1
))
11656 std::swap (op0
, op1
);
11657 code
= swap_condition (code
);
11660 /* We now enter a loop during which we will try to simplify the comparison.
11661 For the most part, we only are concerned with comparisons with zero,
11662 but some things may really be comparisons with zero but not start
11663 out looking that way. */
11665 while (CONST_INT_P (op1
))
11667 machine_mode mode
= GET_MODE (op0
);
11668 unsigned int mode_width
= GET_MODE_PRECISION (mode
);
11669 unsigned HOST_WIDE_INT mask
= GET_MODE_MASK (mode
);
11670 int equality_comparison_p
;
11671 int sign_bit_comparison_p
;
11672 int unsigned_comparison_p
;
11673 HOST_WIDE_INT const_op
;
11675 /* We only want to handle integral modes. This catches VOIDmode,
11676 CCmode, and the floating-point modes. An exception is that we
11677 can handle VOIDmode if OP0 is a COMPARE or a comparison
11680 if (GET_MODE_CLASS (mode
) != MODE_INT
11681 && ! (mode
== VOIDmode
11682 && (GET_CODE (op0
) == COMPARE
|| COMPARISON_P (op0
))))
11685 /* Try to simplify the compare to constant, possibly changing the
11686 comparison op, and/or changing op1 to zero. */
11687 code
= simplify_compare_const (code
, mode
, op0
, &op1
);
11688 const_op
= INTVAL (op1
);
11690 /* Compute some predicates to simplify code below. */
11692 equality_comparison_p
= (code
== EQ
|| code
== NE
);
11693 sign_bit_comparison_p
= ((code
== LT
|| code
== GE
) && const_op
== 0);
11694 unsigned_comparison_p
= (code
== LTU
|| code
== LEU
|| code
== GTU
11697 /* If this is a sign bit comparison and we can do arithmetic in
11698 MODE, say that we will only be needing the sign bit of OP0. */
11699 if (sign_bit_comparison_p
&& HWI_COMPUTABLE_MODE_P (mode
))
11700 op0
= force_to_mode (op0
, mode
,
11702 << (GET_MODE_PRECISION (mode
) - 1),
11705 /* Now try cases based on the opcode of OP0. If none of the cases
11706 does a "continue", we exit this loop immediately after the
11709 switch (GET_CODE (op0
))
11712 /* If we are extracting a single bit from a variable position in
11713 a constant that has only a single bit set and are comparing it
11714 with zero, we can convert this into an equality comparison
11715 between the position and the location of the single bit. */
11716 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11717 have already reduced the shift count modulo the word size. */
11718 if (!SHIFT_COUNT_TRUNCATED
11719 && CONST_INT_P (XEXP (op0
, 0))
11720 && XEXP (op0
, 1) == const1_rtx
11721 && equality_comparison_p
&& const_op
== 0
11722 && (i
= exact_log2 (UINTVAL (XEXP (op0
, 0)))) >= 0)
11724 if (BITS_BIG_ENDIAN
)
11725 i
= BITS_PER_WORD
- 1 - i
;
11727 op0
= XEXP (op0
, 2);
11731 /* Result is nonzero iff shift count is equal to I. */
11732 code
= reverse_condition (code
);
11739 tem
= expand_compound_operation (op0
);
11748 /* If testing for equality, we can take the NOT of the constant. */
11749 if (equality_comparison_p
11750 && (tem
= simplify_unary_operation (NOT
, mode
, op1
, mode
)) != 0)
11752 op0
= XEXP (op0
, 0);
11757 /* If just looking at the sign bit, reverse the sense of the
11759 if (sign_bit_comparison_p
)
11761 op0
= XEXP (op0
, 0);
11762 code
= (code
== GE
? LT
: GE
);
11768 /* If testing for equality, we can take the NEG of the constant. */
11769 if (equality_comparison_p
11770 && (tem
= simplify_unary_operation (NEG
, mode
, op1
, mode
)) != 0)
11772 op0
= XEXP (op0
, 0);
11777 /* The remaining cases only apply to comparisons with zero. */
11781 /* When X is ABS or is known positive,
11782 (neg X) is < 0 if and only if X != 0. */
11784 if (sign_bit_comparison_p
11785 && (GET_CODE (XEXP (op0
, 0)) == ABS
11786 || (mode_width
<= HOST_BITS_PER_WIDE_INT
11787 && (nonzero_bits (XEXP (op0
, 0), mode
)
11788 & (HOST_WIDE_INT_1U
<< (mode_width
- 1)))
11791 op0
= XEXP (op0
, 0);
11792 code
= (code
== LT
? NE
: EQ
);
11796 /* If we have NEG of something whose two high-order bits are the
11797 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11798 if (num_sign_bit_copies (op0
, mode
) >= 2)
11800 op0
= XEXP (op0
, 0);
11801 code
= swap_condition (code
);
11807 /* If we are testing equality and our count is a constant, we
11808 can perform the inverse operation on our RHS. */
11809 if (equality_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
11810 && (tem
= simplify_binary_operation (ROTATERT
, mode
,
11811 op1
, XEXP (op0
, 1))) != 0)
11813 op0
= XEXP (op0
, 0);
11818 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11819 a particular bit. Convert it to an AND of a constant of that
11820 bit. This will be converted into a ZERO_EXTRACT. */
11821 if (const_op
== 0 && sign_bit_comparison_p
11822 && CONST_INT_P (XEXP (op0
, 1))
11823 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
11825 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
11828 - INTVAL (XEXP (op0
, 1)))));
11829 code
= (code
== LT
? NE
: EQ
);
11833 /* Fall through. */
11836 /* ABS is ignorable inside an equality comparison with zero. */
11837 if (const_op
== 0 && equality_comparison_p
)
11839 op0
= XEXP (op0
, 0);
11845 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11846 (compare FOO CONST) if CONST fits in FOO's mode and we
11847 are either testing inequality or have an unsigned
11848 comparison with ZERO_EXTEND or a signed comparison with
11849 SIGN_EXTEND. But don't do it if we don't have a compare
11850 insn of the given mode, since we'd have to revert it
11851 later on, and then we wouldn't know whether to sign- or
11853 mode
= GET_MODE (XEXP (op0
, 0));
11854 if (GET_MODE_CLASS (mode
) == MODE_INT
11855 && ! unsigned_comparison_p
11856 && HWI_COMPUTABLE_MODE_P (mode
)
11857 && trunc_int_for_mode (const_op
, mode
) == const_op
11858 && have_insn_for (COMPARE
, mode
))
11860 op0
= XEXP (op0
, 0);
11866 /* Check for the case where we are comparing A - C1 with C2, that is
11868 (subreg:MODE (plus (A) (-C1))) op (C2)
11870 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11871 comparison in the wider mode. One of the following two conditions
11872 must be true in order for this to be valid:
11874 1. The mode extension results in the same bit pattern being added
11875 on both sides and the comparison is equality or unsigned. As
11876 C2 has been truncated to fit in MODE, the pattern can only be
11879 2. The mode extension results in the sign bit being copied on
11882 The difficulty here is that we have predicates for A but not for
11883 (A - C1) so we need to check that C1 is within proper bounds so
11884 as to perturbate A as little as possible. */
11886 if (mode_width
<= HOST_BITS_PER_WIDE_INT
11887 && subreg_lowpart_p (op0
)
11888 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) > mode_width
11889 && GET_CODE (SUBREG_REG (op0
)) == PLUS
11890 && CONST_INT_P (XEXP (SUBREG_REG (op0
), 1)))
11892 machine_mode inner_mode
= GET_MODE (SUBREG_REG (op0
));
11893 rtx a
= XEXP (SUBREG_REG (op0
), 0);
11894 HOST_WIDE_INT c1
= -INTVAL (XEXP (SUBREG_REG (op0
), 1));
11897 && (unsigned HOST_WIDE_INT
) c1
11898 < HOST_WIDE_INT_1U
<< (mode_width
- 1)
11899 && (equality_comparison_p
|| unsigned_comparison_p
)
11900 /* (A - C1) zero-extends if it is positive and sign-extends
11901 if it is negative, C2 both zero- and sign-extends. */
11902 && ((0 == (nonzero_bits (a
, inner_mode
)
11903 & ~GET_MODE_MASK (mode
))
11905 /* (A - C1) sign-extends if it is positive and 1-extends
11906 if it is negative, C2 both sign- and 1-extends. */
11907 || (num_sign_bit_copies (a
, inner_mode
)
11908 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11911 || ((unsigned HOST_WIDE_INT
) c1
11912 < HOST_WIDE_INT_1U
<< (mode_width
- 2)
11913 /* (A - C1) always sign-extends, like C2. */
11914 && num_sign_bit_copies (a
, inner_mode
)
11915 > (unsigned int) (GET_MODE_PRECISION (inner_mode
)
11916 - (mode_width
- 1))))
11918 op0
= SUBREG_REG (op0
);
11923 /* If the inner mode is narrower and we are extracting the low part,
11924 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11925 if (subreg_lowpart_p (op0
)
11926 && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
))) < mode_width
)
11934 mode
= GET_MODE (XEXP (op0
, 0));
11935 if (GET_MODE_CLASS (mode
) == MODE_INT
11936 && (unsigned_comparison_p
|| equality_comparison_p
)
11937 && HWI_COMPUTABLE_MODE_P (mode
)
11938 && (unsigned HOST_WIDE_INT
) const_op
<= GET_MODE_MASK (mode
)
11940 && have_insn_for (COMPARE
, mode
))
11942 op0
= XEXP (op0
, 0);
11948 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11949 this for equality comparisons due to pathological cases involving
11951 if (equality_comparison_p
11952 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11953 op1
, XEXP (op0
, 1))))
11955 op0
= XEXP (op0
, 0);
11960 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11961 if (const_op
== 0 && XEXP (op0
, 1) == constm1_rtx
11962 && GET_CODE (XEXP (op0
, 0)) == ABS
&& sign_bit_comparison_p
)
11964 op0
= XEXP (XEXP (op0
, 0), 0);
11965 code
= (code
== LT
? EQ
: NE
);
11971 /* We used to optimize signed comparisons against zero, but that
11972 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11973 arrive here as equality comparisons, or (GEU, LTU) are
11974 optimized away. No need to special-case them. */
11976 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11977 (eq B (minus A C)), whichever simplifies. We can only do
11978 this for equality comparisons due to pathological cases involving
11980 if (equality_comparison_p
11981 && 0 != (tem
= simplify_binary_operation (PLUS
, mode
,
11982 XEXP (op0
, 1), op1
)))
11984 op0
= XEXP (op0
, 0);
11989 if (equality_comparison_p
11990 && 0 != (tem
= simplify_binary_operation (MINUS
, mode
,
11991 XEXP (op0
, 0), op1
)))
11993 op0
= XEXP (op0
, 1);
11998 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11999 of bits in X minus 1, is one iff X > 0. */
12000 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == ASHIFTRT
12001 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12002 && UINTVAL (XEXP (XEXP (op0
, 0), 1)) == mode_width
- 1
12003 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12005 op0
= XEXP (op0
, 1);
12006 code
= (code
== GE
? LE
: GT
);
12012 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12013 if C is zero or B is a constant. */
12014 if (equality_comparison_p
12015 && 0 != (tem
= simplify_binary_operation (XOR
, mode
,
12016 XEXP (op0
, 1), op1
)))
12018 op0
= XEXP (op0
, 0);
12025 case UNEQ
: case LTGT
:
12026 case LT
: case LTU
: case UNLT
: case LE
: case LEU
: case UNLE
:
12027 case GT
: case GTU
: case UNGT
: case GE
: case GEU
: case UNGE
:
12028 case UNORDERED
: case ORDERED
:
12029 /* We can't do anything if OP0 is a condition code value, rather
12030 than an actual data value. */
12032 || CC0_P (XEXP (op0
, 0))
12033 || GET_MODE_CLASS (GET_MODE (XEXP (op0
, 0))) == MODE_CC
)
12036 /* Get the two operands being compared. */
12037 if (GET_CODE (XEXP (op0
, 0)) == COMPARE
)
12038 tem
= XEXP (XEXP (op0
, 0), 0), tem1
= XEXP (XEXP (op0
, 0), 1);
12040 tem
= XEXP (op0
, 0), tem1
= XEXP (op0
, 1);
12042 /* Check for the cases where we simply want the result of the
12043 earlier test or the opposite of that result. */
12044 if (code
== NE
|| code
== EQ
12045 || (val_signbit_known_set_p (GET_MODE (op0
), STORE_FLAG_VALUE
)
12046 && (code
== LT
|| code
== GE
)))
12048 enum rtx_code new_code
;
12049 if (code
== LT
|| code
== NE
)
12050 new_code
= GET_CODE (op0
);
12052 new_code
= reversed_comparison_code (op0
, NULL
);
12054 if (new_code
!= UNKNOWN
)
12065 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12067 if (sign_bit_comparison_p
&& GET_CODE (XEXP (op0
, 0)) == PLUS
12068 && XEXP (XEXP (op0
, 0), 1) == constm1_rtx
12069 && rtx_equal_p (XEXP (XEXP (op0
, 0), 0), XEXP (op0
, 1)))
12071 op0
= XEXP (op0
, 1);
12072 code
= (code
== GE
? GT
: LE
);
12078 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12079 will be converted to a ZERO_EXTRACT later. */
12080 if (const_op
== 0 && equality_comparison_p
12081 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12082 && XEXP (XEXP (op0
, 0), 0) == const1_rtx
)
12084 op0
= gen_rtx_LSHIFTRT (mode
, XEXP (op0
, 1),
12085 XEXP (XEXP (op0
, 0), 1));
12086 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12090 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12091 zero and X is a comparison and C1 and C2 describe only bits set
12092 in STORE_FLAG_VALUE, we can compare with X. */
12093 if (const_op
== 0 && equality_comparison_p
12094 && mode_width
<= HOST_BITS_PER_WIDE_INT
12095 && CONST_INT_P (XEXP (op0
, 1))
12096 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
12097 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12098 && INTVAL (XEXP (XEXP (op0
, 0), 1)) >= 0
12099 && INTVAL (XEXP (XEXP (op0
, 0), 1)) < HOST_BITS_PER_WIDE_INT
)
12101 mask
= ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12102 << INTVAL (XEXP (XEXP (op0
, 0), 1)));
12103 if ((~STORE_FLAG_VALUE
& mask
) == 0
12104 && (COMPARISON_P (XEXP (XEXP (op0
, 0), 0))
12105 || ((tem
= get_last_value (XEXP (XEXP (op0
, 0), 0))) != 0
12106 && COMPARISON_P (tem
))))
12108 op0
= XEXP (XEXP (op0
, 0), 0);
12113 /* If we are doing an equality comparison of an AND of a bit equal
12114 to the sign bit, replace this with a LT or GE comparison of
12115 the underlying value. */
12116 if (equality_comparison_p
12118 && CONST_INT_P (XEXP (op0
, 1))
12119 && mode_width
<= HOST_BITS_PER_WIDE_INT
12120 && ((INTVAL (XEXP (op0
, 1)) & GET_MODE_MASK (mode
))
12121 == HOST_WIDE_INT_1U
<< (mode_width
- 1)))
12123 op0
= XEXP (op0
, 0);
12124 code
= (code
== EQ
? GE
: LT
);
12128 /* If this AND operation is really a ZERO_EXTEND from a narrower
12129 mode, the constant fits within that mode, and this is either an
12130 equality or unsigned comparison, try to do this comparison in
12135 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12136 -> (ne:DI (reg:SI 4) (const_int 0))
12138 unless TRULY_NOOP_TRUNCATION allows it or the register is
12139 known to hold a value of the required mode the
12140 transformation is invalid. */
12141 if ((equality_comparison_p
|| unsigned_comparison_p
)
12142 && CONST_INT_P (XEXP (op0
, 1))
12143 && (i
= exact_log2 ((UINTVAL (XEXP (op0
, 1))
12144 & GET_MODE_MASK (mode
))
12146 && const_op
>> i
== 0
12147 && (tmode
= mode_for_size (i
, MODE_INT
, 1)) != BLKmode
)
12149 op0
= gen_lowpart_or_truncate (tmode
, XEXP (op0
, 0));
12153 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12154 fits in both M1 and M2 and the SUBREG is either paradoxical
12155 or represents the low part, permute the SUBREG and the AND
12157 if (GET_CODE (XEXP (op0
, 0)) == SUBREG
12158 && CONST_INT_P (XEXP (op0
, 1)))
12160 tmode
= GET_MODE (SUBREG_REG (XEXP (op0
, 0)));
12161 unsigned HOST_WIDE_INT c1
= INTVAL (XEXP (op0
, 1));
12162 /* Require an integral mode, to avoid creating something like
12164 if (SCALAR_INT_MODE_P (tmode
)
12165 /* It is unsafe to commute the AND into the SUBREG if the
12166 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12167 not defined. As originally written the upper bits
12168 have a defined value due to the AND operation.
12169 However, if we commute the AND inside the SUBREG then
12170 they no longer have defined values and the meaning of
12171 the code has been changed.
12172 Also C1 should not change value in the smaller mode,
12173 see PR67028 (a positive C1 can become negative in the
12174 smaller mode, so that the AND does no longer mask the
12176 && ((WORD_REGISTER_OPERATIONS
12177 && mode_width
> GET_MODE_PRECISION (tmode
)
12178 && mode_width
<= BITS_PER_WORD
12179 && trunc_int_for_mode (c1
, tmode
) == (HOST_WIDE_INT
) c1
)
12180 || (mode_width
<= GET_MODE_PRECISION (tmode
)
12181 && subreg_lowpart_p (XEXP (op0
, 0))))
12182 && mode_width
<= HOST_BITS_PER_WIDE_INT
12183 && HWI_COMPUTABLE_MODE_P (tmode
)
12184 && (c1
& ~mask
) == 0
12185 && (c1
& ~GET_MODE_MASK (tmode
)) == 0
12187 && c1
!= GET_MODE_MASK (tmode
))
12189 op0
= simplify_gen_binary (AND
, tmode
,
12190 SUBREG_REG (XEXP (op0
, 0)),
12191 gen_int_mode (c1
, tmode
));
12192 op0
= gen_lowpart (mode
, op0
);
12197 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12198 if (const_op
== 0 && equality_comparison_p
12199 && XEXP (op0
, 1) == const1_rtx
12200 && GET_CODE (XEXP (op0
, 0)) == NOT
)
12202 op0
= simplify_and_const_int (NULL_RTX
, mode
,
12203 XEXP (XEXP (op0
, 0), 0), 1);
12204 code
= (code
== NE
? EQ
: NE
);
12208 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12209 (eq (and (lshiftrt X) 1) 0).
12210 Also handle the case where (not X) is expressed using xor. */
12211 if (const_op
== 0 && equality_comparison_p
12212 && XEXP (op0
, 1) == const1_rtx
12213 && GET_CODE (XEXP (op0
, 0)) == LSHIFTRT
)
12215 rtx shift_op
= XEXP (XEXP (op0
, 0), 0);
12216 rtx shift_count
= XEXP (XEXP (op0
, 0), 1);
12218 if (GET_CODE (shift_op
) == NOT
12219 || (GET_CODE (shift_op
) == XOR
12220 && CONST_INT_P (XEXP (shift_op
, 1))
12221 && CONST_INT_P (shift_count
)
12222 && HWI_COMPUTABLE_MODE_P (mode
)
12223 && (UINTVAL (XEXP (shift_op
, 1))
12224 == HOST_WIDE_INT_1U
12225 << INTVAL (shift_count
))))
12228 = gen_rtx_LSHIFTRT (mode
, XEXP (shift_op
, 0), shift_count
);
12229 op0
= simplify_and_const_int (NULL_RTX
, mode
, op0
, 1);
12230 code
= (code
== NE
? EQ
: NE
);
12237 /* If we have (compare (ashift FOO N) (const_int C)) and
12238 the high order N bits of FOO (N+1 if an inequality comparison)
12239 are known to be zero, we can do this by comparing FOO with C
12240 shifted right N bits so long as the low-order N bits of C are
12242 if (CONST_INT_P (XEXP (op0
, 1))
12243 && INTVAL (XEXP (op0
, 1)) >= 0
12244 && ((INTVAL (XEXP (op0
, 1)) + ! equality_comparison_p
)
12245 < HOST_BITS_PER_WIDE_INT
)
12246 && (((unsigned HOST_WIDE_INT
) const_op
12247 & ((HOST_WIDE_INT_1U
<< INTVAL (XEXP (op0
, 1)))
12249 && mode_width
<= HOST_BITS_PER_WIDE_INT
12250 && (nonzero_bits (XEXP (op0
, 0), mode
)
12251 & ~(mask
>> (INTVAL (XEXP (op0
, 1))
12252 + ! equality_comparison_p
))) == 0)
12254 /* We must perform a logical shift, not an arithmetic one,
12255 as we want the top N bits of C to be zero. */
12256 unsigned HOST_WIDE_INT temp
= const_op
& GET_MODE_MASK (mode
);
12258 temp
>>= INTVAL (XEXP (op0
, 1));
12259 op1
= gen_int_mode (temp
, mode
);
12260 op0
= XEXP (op0
, 0);
12264 /* If we are doing a sign bit comparison, it means we are testing
12265 a particular bit. Convert it to the appropriate AND. */
12266 if (sign_bit_comparison_p
&& CONST_INT_P (XEXP (op0
, 1))
12267 && mode_width
<= HOST_BITS_PER_WIDE_INT
)
12269 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0),
12272 - INTVAL (XEXP (op0
, 1)))));
12273 code
= (code
== LT
? NE
: EQ
);
12277 /* If this an equality comparison with zero and we are shifting
12278 the low bit to the sign bit, we can convert this to an AND of the
12280 if (const_op
== 0 && equality_comparison_p
12281 && CONST_INT_P (XEXP (op0
, 1))
12282 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12284 op0
= simplify_and_const_int (NULL_RTX
, mode
, XEXP (op0
, 0), 1);
12290 /* If this is an equality comparison with zero, we can do this
12291 as a logical shift, which might be much simpler. */
12292 if (equality_comparison_p
&& const_op
== 0
12293 && CONST_INT_P (XEXP (op0
, 1)))
12295 op0
= simplify_shift_const (NULL_RTX
, LSHIFTRT
, mode
,
12297 INTVAL (XEXP (op0
, 1)));
12301 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12302 do the comparison in a narrower mode. */
12303 if (! unsigned_comparison_p
12304 && CONST_INT_P (XEXP (op0
, 1))
12305 && GET_CODE (XEXP (op0
, 0)) == ASHIFT
12306 && XEXP (op0
, 1) == XEXP (XEXP (op0
, 0), 1)
12307 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12308 MODE_INT
, 1)) != BLKmode
12309 && (((unsigned HOST_WIDE_INT
) const_op
12310 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12311 <= GET_MODE_MASK (tmode
)))
12313 op0
= gen_lowpart (tmode
, XEXP (XEXP (op0
, 0), 0));
12317 /* Likewise if OP0 is a PLUS of a sign extension with a
12318 constant, which is usually represented with the PLUS
12319 between the shifts. */
12320 if (! unsigned_comparison_p
12321 && CONST_INT_P (XEXP (op0
, 1))
12322 && GET_CODE (XEXP (op0
, 0)) == PLUS
12323 && CONST_INT_P (XEXP (XEXP (op0
, 0), 1))
12324 && GET_CODE (XEXP (XEXP (op0
, 0), 0)) == ASHIFT
12325 && XEXP (op0
, 1) == XEXP (XEXP (XEXP (op0
, 0), 0), 1)
12326 && (tmode
= mode_for_size (mode_width
- INTVAL (XEXP (op0
, 1)),
12327 MODE_INT
, 1)) != BLKmode
12328 && (((unsigned HOST_WIDE_INT
) const_op
12329 + (GET_MODE_MASK (tmode
) >> 1) + 1)
12330 <= GET_MODE_MASK (tmode
)))
12332 rtx inner
= XEXP (XEXP (XEXP (op0
, 0), 0), 0);
12333 rtx add_const
= XEXP (XEXP (op0
, 0), 1);
12334 rtx new_const
= simplify_gen_binary (ASHIFTRT
, GET_MODE (op0
),
12335 add_const
, XEXP (op0
, 1));
12337 op0
= simplify_gen_binary (PLUS
, tmode
,
12338 gen_lowpart (tmode
, inner
),
12345 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12346 the low order N bits of FOO are known to be zero, we can do this
12347 by comparing FOO with C shifted left N bits so long as no
12348 overflow occurs. Even if the low order N bits of FOO aren't known
12349 to be zero, if the comparison is >= or < we can use the same
12350 optimization and for > or <= by setting all the low
12351 order N bits in the comparison constant. */
12352 if (CONST_INT_P (XEXP (op0
, 1))
12353 && INTVAL (XEXP (op0
, 1)) > 0
12354 && INTVAL (XEXP (op0
, 1)) < HOST_BITS_PER_WIDE_INT
12355 && mode_width
<= HOST_BITS_PER_WIDE_INT
12356 && (((unsigned HOST_WIDE_INT
) const_op
12357 + (GET_CODE (op0
) != LSHIFTRT
12358 ? ((GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1)) >> 1)
12361 <= GET_MODE_MASK (mode
) >> INTVAL (XEXP (op0
, 1))))
12363 unsigned HOST_WIDE_INT low_bits
12364 = (nonzero_bits (XEXP (op0
, 0), mode
)
12365 & ((HOST_WIDE_INT_1U
12366 << INTVAL (XEXP (op0
, 1))) - 1));
12367 if (low_bits
== 0 || !equality_comparison_p
)
12369 /* If the shift was logical, then we must make the condition
12371 if (GET_CODE (op0
) == LSHIFTRT
)
12372 code
= unsigned_condition (code
);
12374 const_op
<<= INTVAL (XEXP (op0
, 1));
12376 && (code
== GT
|| code
== GTU
12377 || code
== LE
|| code
== LEU
))
12379 |= ((HOST_WIDE_INT_1
<< INTVAL (XEXP (op0
, 1))) - 1);
12380 op1
= GEN_INT (const_op
);
12381 op0
= XEXP (op0
, 0);
12386 /* If we are using this shift to extract just the sign bit, we
12387 can replace this with an LT or GE comparison. */
12389 && (equality_comparison_p
|| sign_bit_comparison_p
)
12390 && CONST_INT_P (XEXP (op0
, 1))
12391 && UINTVAL (XEXP (op0
, 1)) == mode_width
- 1)
12393 op0
= XEXP (op0
, 0);
12394 code
= (code
== NE
|| code
== GT
? LT
: GE
);
12406 /* Now make any compound operations involved in this comparison. Then,
12407 check for an outmost SUBREG on OP0 that is not doing anything or is
12408 paradoxical. The latter transformation must only be performed when
12409 it is known that the "extra" bits will be the same in op0 and op1 or
12410 that they don't matter. There are three cases to consider:
12412 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12413 care bits and we can assume they have any convenient value. So
12414 making the transformation is safe.
12416 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12417 In this case the upper bits of op0 are undefined. We should not make
12418 the simplification in that case as we do not know the contents of
12421 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12422 UNKNOWN. In that case we know those bits are zeros or ones. We must
12423 also be sure that they are the same as the upper bits of op1.
12425 We can never remove a SUBREG for a non-equality comparison because
12426 the sign bit is in a different place in the underlying object. */
12428 op0
= make_compound_operation (op0
, op1
== const0_rtx
? COMPARE
: SET
);
12429 op1
= make_compound_operation (op1
, SET
);
12431 if (GET_CODE (op0
) == SUBREG
&& subreg_lowpart_p (op0
)
12432 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
12433 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0
))) == MODE_INT
12434 && (code
== NE
|| code
== EQ
))
12436 if (paradoxical_subreg_p (op0
))
12438 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12440 if (REG_P (SUBREG_REG (op0
)))
12442 op0
= SUBREG_REG (op0
);
12443 op1
= gen_lowpart (GET_MODE (op0
), op1
);
12446 else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0
)))
12447 <= HOST_BITS_PER_WIDE_INT
)
12448 && (nonzero_bits (SUBREG_REG (op0
),
12449 GET_MODE (SUBREG_REG (op0
)))
12450 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12452 tem
= gen_lowpart (GET_MODE (SUBREG_REG (op0
)), op1
);
12454 if ((nonzero_bits (tem
, GET_MODE (SUBREG_REG (op0
)))
12455 & ~GET_MODE_MASK (GET_MODE (op0
))) == 0)
12456 op0
= SUBREG_REG (op0
), op1
= tem
;
12460 /* We now do the opposite procedure: Some machines don't have compare
12461 insns in all modes. If OP0's mode is an integer mode smaller than a
12462 word and we can't do a compare in that mode, see if there is a larger
12463 mode for which we can do the compare. There are a number of cases in
12464 which we can use the wider mode. */
12466 mode
= GET_MODE (op0
);
12467 if (mode
!= VOIDmode
&& GET_MODE_CLASS (mode
) == MODE_INT
12468 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
12469 && ! have_insn_for (COMPARE
, mode
))
12470 for (tmode
= GET_MODE_WIDER_MODE (mode
);
12471 (tmode
!= VOIDmode
&& HWI_COMPUTABLE_MODE_P (tmode
));
12472 tmode
= GET_MODE_WIDER_MODE (tmode
))
12473 if (have_insn_for (COMPARE
, tmode
))
12477 /* If this is a test for negative, we can make an explicit
12478 test of the sign bit. Test this first so we can use
12479 a paradoxical subreg to extend OP0. */
12481 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
12482 && HWI_COMPUTABLE_MODE_P (mode
))
12484 unsigned HOST_WIDE_INT sign
12485 = HOST_WIDE_INT_1U
<< (GET_MODE_BITSIZE (mode
) - 1);
12486 op0
= simplify_gen_binary (AND
, tmode
,
12487 gen_lowpart (tmode
, op0
),
12488 gen_int_mode (sign
, tmode
));
12489 code
= (code
== LT
) ? NE
: EQ
;
12493 /* If the only nonzero bits in OP0 and OP1 are those in the
12494 narrower mode and this is an equality or unsigned comparison,
12495 we can use the wider mode. Similarly for sign-extended
12496 values, in which case it is true for all comparisons. */
12497 zero_extended
= ((code
== EQ
|| code
== NE
12498 || code
== GEU
|| code
== GTU
12499 || code
== LEU
|| code
== LTU
)
12500 && (nonzero_bits (op0
, tmode
)
12501 & ~GET_MODE_MASK (mode
)) == 0
12502 && ((CONST_INT_P (op1
)
12503 || (nonzero_bits (op1
, tmode
)
12504 & ~GET_MODE_MASK (mode
)) == 0)));
12507 || ((num_sign_bit_copies (op0
, tmode
)
12508 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12509 - GET_MODE_PRECISION (mode
)))
12510 && (num_sign_bit_copies (op1
, tmode
)
12511 > (unsigned int) (GET_MODE_PRECISION (tmode
)
12512 - GET_MODE_PRECISION (mode
)))))
12514 /* If OP0 is an AND and we don't have an AND in MODE either,
12515 make a new AND in the proper mode. */
12516 if (GET_CODE (op0
) == AND
12517 && !have_insn_for (AND
, mode
))
12518 op0
= simplify_gen_binary (AND
, tmode
,
12519 gen_lowpart (tmode
,
12521 gen_lowpart (tmode
,
12527 op0
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op0
, mode
);
12528 op1
= simplify_gen_unary (ZERO_EXTEND
, tmode
, op1
, mode
);
12532 op0
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op0
, mode
);
12533 op1
= simplify_gen_unary (SIGN_EXTEND
, tmode
, op1
, mode
);
12540 /* We may have changed the comparison operands. Re-canonicalize. */
12541 if (swap_commutative_operands_p (op0
, op1
))
12543 std::swap (op0
, op1
);
12544 code
= swap_condition (code
);
12547 /* If this machine only supports a subset of valid comparisons, see if we
12548 can convert an unsupported one into a supported one. */
12549 target_canonicalize_comparison (&code
, &op0
, &op1
, 0);
12557 /* Utility function for record_value_for_reg. Count number of
12562 enum rtx_code code
= GET_CODE (x
);
12566 if (GET_RTX_CLASS (code
) == RTX_BIN_ARITH
12567 || GET_RTX_CLASS (code
) == RTX_COMM_ARITH
)
12569 rtx x0
= XEXP (x
, 0);
12570 rtx x1
= XEXP (x
, 1);
12573 return 1 + 2 * count_rtxs (x0
);
12575 if ((GET_RTX_CLASS (GET_CODE (x1
)) == RTX_BIN_ARITH
12576 || GET_RTX_CLASS (GET_CODE (x1
)) == RTX_COMM_ARITH
)
12577 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12578 return 2 + 2 * count_rtxs (x0
)
12579 + count_rtxs (x
== XEXP (x1
, 0)
12580 ? XEXP (x1
, 1) : XEXP (x1
, 0));
12582 if ((GET_RTX_CLASS (GET_CODE (x0
)) == RTX_BIN_ARITH
12583 || GET_RTX_CLASS (GET_CODE (x0
)) == RTX_COMM_ARITH
)
12584 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12585 return 2 + 2 * count_rtxs (x1
)
12586 + count_rtxs (x
== XEXP (x0
, 0)
12587 ? XEXP (x0
, 1) : XEXP (x0
, 0));
12590 fmt
= GET_RTX_FORMAT (code
);
12591 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12593 ret
+= count_rtxs (XEXP (x
, i
));
12594 else if (fmt
[i
] == 'E')
12595 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12596 ret
+= count_rtxs (XVECEXP (x
, i
, j
));
12601 /* Utility function for following routine. Called when X is part of a value
12602 being stored into last_set_value. Sets last_set_table_tick
12603 for each register mentioned. Similar to mention_regs in cse.c */
12606 update_table_tick (rtx x
)
12608 enum rtx_code code
= GET_CODE (x
);
12609 const char *fmt
= GET_RTX_FORMAT (code
);
12614 unsigned int regno
= REGNO (x
);
12615 unsigned int endregno
= END_REGNO (x
);
12618 for (r
= regno
; r
< endregno
; r
++)
12620 reg_stat_type
*rsp
= ®_stat
[r
];
12621 rsp
->last_set_table_tick
= label_tick
;
12627 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
12630 /* Check for identical subexpressions. If x contains
12631 identical subexpression we only have to traverse one of
12633 if (i
== 0 && ARITHMETIC_P (x
))
12635 /* Note that at this point x1 has already been
12637 rtx x0
= XEXP (x
, 0);
12638 rtx x1
= XEXP (x
, 1);
12640 /* If x0 and x1 are identical then there is no need to
12645 /* If x0 is identical to a subexpression of x1 then while
12646 processing x1, x0 has already been processed. Thus we
12647 are done with x. */
12648 if (ARITHMETIC_P (x1
)
12649 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
12652 /* If x1 is identical to a subexpression of x0 then we
12653 still have to process the rest of x0. */
12654 if (ARITHMETIC_P (x0
)
12655 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
12657 update_table_tick (XEXP (x0
, x1
== XEXP (x0
, 0) ? 1 : 0));
12662 update_table_tick (XEXP (x
, i
));
12664 else if (fmt
[i
] == 'E')
12665 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
12666 update_table_tick (XVECEXP (x
, i
, j
));
12669 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12670 are saying that the register is clobbered and we no longer know its
12671 value. If INSN is zero, don't update reg_stat[].last_set; this is
12672 only permitted with VALUE also zero and is used to invalidate the
12676 record_value_for_reg (rtx reg
, rtx_insn
*insn
, rtx value
)
12678 unsigned int regno
= REGNO (reg
);
12679 unsigned int endregno
= END_REGNO (reg
);
12681 reg_stat_type
*rsp
;
12683 /* If VALUE contains REG and we have a previous value for REG, substitute
12684 the previous value. */
12685 if (value
&& insn
&& reg_overlap_mentioned_p (reg
, value
))
12689 /* Set things up so get_last_value is allowed to see anything set up to
12691 subst_low_luid
= DF_INSN_LUID (insn
);
12692 tem
= get_last_value (reg
);
12694 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12695 it isn't going to be useful and will take a lot of time to process,
12696 so just use the CLOBBER. */
12700 if (ARITHMETIC_P (tem
)
12701 && GET_CODE (XEXP (tem
, 0)) == CLOBBER
12702 && GET_CODE (XEXP (tem
, 1)) == CLOBBER
)
12703 tem
= XEXP (tem
, 0);
12704 else if (count_occurrences (value
, reg
, 1) >= 2)
12706 /* If there are two or more occurrences of REG in VALUE,
12707 prevent the value from growing too much. */
12708 if (count_rtxs (tem
) > MAX_LAST_VALUE_RTL
)
12709 tem
= gen_rtx_CLOBBER (GET_MODE (tem
), const0_rtx
);
12712 value
= replace_rtx (copy_rtx (value
), reg
, tem
);
12716 /* For each register modified, show we don't know its value, that
12717 we don't know about its bitwise content, that its value has been
12718 updated, and that we don't know the location of the death of the
12720 for (i
= regno
; i
< endregno
; i
++)
12722 rsp
= ®_stat
[i
];
12725 rsp
->last_set
= insn
;
12727 rsp
->last_set_value
= 0;
12728 rsp
->last_set_mode
= VOIDmode
;
12729 rsp
->last_set_nonzero_bits
= 0;
12730 rsp
->last_set_sign_bit_copies
= 0;
12731 rsp
->last_death
= 0;
12732 rsp
->truncated_to_mode
= VOIDmode
;
12735 /* Mark registers that are being referenced in this value. */
12737 update_table_tick (value
);
12739 /* Now update the status of each register being set.
12740 If someone is using this register in this block, set this register
12741 to invalid since we will get confused between the two lives in this
12742 basic block. This makes using this register always invalid. In cse, we
12743 scan the table to invalidate all entries using this register, but this
12744 is too much work for us. */
12746 for (i
= regno
; i
< endregno
; i
++)
12748 rsp
= ®_stat
[i
];
12749 rsp
->last_set_label
= label_tick
;
12751 || (value
&& rsp
->last_set_table_tick
>= label_tick_ebb_start
))
12752 rsp
->last_set_invalid
= 1;
12754 rsp
->last_set_invalid
= 0;
12757 /* The value being assigned might refer to X (like in "x++;"). In that
12758 case, we must replace it with (clobber (const_int 0)) to prevent
12760 rsp
= ®_stat
[regno
];
12761 if (value
&& !get_last_value_validate (&value
, insn
, label_tick
, 0))
12763 value
= copy_rtx (value
);
12764 if (!get_last_value_validate (&value
, insn
, label_tick
, 1))
12768 /* For the main register being modified, update the value, the mode, the
12769 nonzero bits, and the number of sign bit copies. */
12771 rsp
->last_set_value
= value
;
12775 machine_mode mode
= GET_MODE (reg
);
12776 subst_low_luid
= DF_INSN_LUID (insn
);
12777 rsp
->last_set_mode
= mode
;
12778 if (GET_MODE_CLASS (mode
) == MODE_INT
12779 && HWI_COMPUTABLE_MODE_P (mode
))
12780 mode
= nonzero_bits_mode
;
12781 rsp
->last_set_nonzero_bits
= nonzero_bits (value
, mode
);
12782 rsp
->last_set_sign_bit_copies
12783 = num_sign_bit_copies (value
, GET_MODE (reg
));
12787 /* Called via note_stores from record_dead_and_set_regs to handle one
12788 SET or CLOBBER in an insn. DATA is the instruction in which the
12789 set is occurring. */
12792 record_dead_and_set_regs_1 (rtx dest
, const_rtx setter
, void *data
)
12794 rtx_insn
*record_dead_insn
= (rtx_insn
*) data
;
12796 if (GET_CODE (dest
) == SUBREG
)
12797 dest
= SUBREG_REG (dest
);
12799 if (!record_dead_insn
)
12802 record_value_for_reg (dest
, NULL
, NULL_RTX
);
12808 /* If we are setting the whole register, we know its value. Otherwise
12809 show that we don't know the value. We can handle SUBREG in
12811 if (GET_CODE (setter
) == SET
&& dest
== SET_DEST (setter
))
12812 record_value_for_reg (dest
, record_dead_insn
, SET_SRC (setter
));
12813 else if (GET_CODE (setter
) == SET
12814 && GET_CODE (SET_DEST (setter
)) == SUBREG
12815 && SUBREG_REG (SET_DEST (setter
)) == dest
12816 && GET_MODE_PRECISION (GET_MODE (dest
)) <= BITS_PER_WORD
12817 && subreg_lowpart_p (SET_DEST (setter
)))
12818 record_value_for_reg (dest
, record_dead_insn
,
12819 gen_lowpart (GET_MODE (dest
),
12820 SET_SRC (setter
)));
12822 record_value_for_reg (dest
, record_dead_insn
, NULL_RTX
);
12824 else if (MEM_P (dest
)
12825 /* Ignore pushes, they clobber nothing. */
12826 && ! push_operand (dest
, GET_MODE (dest
)))
12827 mem_last_set
= DF_INSN_LUID (record_dead_insn
);
12830 /* Update the records of when each REG was most recently set or killed
12831 for the things done by INSN. This is the last thing done in processing
12832 INSN in the combiner loop.
12834 We update reg_stat[], in particular fields last_set, last_set_value,
12835 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12836 last_death, and also the similar information mem_last_set (which insn
12837 most recently modified memory) and last_call_luid (which insn was the
12838 most recent subroutine call). */
12841 record_dead_and_set_regs (rtx_insn
*insn
)
12846 for (link
= REG_NOTES (insn
); link
; link
= XEXP (link
, 1))
12848 if (REG_NOTE_KIND (link
) == REG_DEAD
12849 && REG_P (XEXP (link
, 0)))
12851 unsigned int regno
= REGNO (XEXP (link
, 0));
12852 unsigned int endregno
= END_REGNO (XEXP (link
, 0));
12854 for (i
= regno
; i
< endregno
; i
++)
12856 reg_stat_type
*rsp
;
12858 rsp
= ®_stat
[i
];
12859 rsp
->last_death
= insn
;
12862 else if (REG_NOTE_KIND (link
) == REG_INC
)
12863 record_value_for_reg (XEXP (link
, 0), insn
, NULL_RTX
);
12868 hard_reg_set_iterator hrsi
;
12869 EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call
, 0, i
, hrsi
)
12871 reg_stat_type
*rsp
;
12873 rsp
= ®_stat
[i
];
12874 rsp
->last_set_invalid
= 1;
12875 rsp
->last_set
= insn
;
12876 rsp
->last_set_value
= 0;
12877 rsp
->last_set_mode
= VOIDmode
;
12878 rsp
->last_set_nonzero_bits
= 0;
12879 rsp
->last_set_sign_bit_copies
= 0;
12880 rsp
->last_death
= 0;
12881 rsp
->truncated_to_mode
= VOIDmode
;
12884 last_call_luid
= mem_last_set
= DF_INSN_LUID (insn
);
12886 /* We can't combine into a call pattern. Remember, though, that
12887 the return value register is set at this LUID. We could
12888 still replace a register with the return value from the
12889 wrong subroutine call! */
12890 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, NULL_RTX
);
12893 note_stores (PATTERN (insn
), record_dead_and_set_regs_1
, insn
);
12896 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12897 register present in the SUBREG, so for each such SUBREG go back and
12898 adjust nonzero and sign bit information of the registers that are
12899 known to have some zero/sign bits set.
12901 This is needed because when combine blows the SUBREGs away, the
12902 information on zero/sign bits is lost and further combines can be
12903 missed because of that. */
12906 record_promoted_value (rtx_insn
*insn
, rtx subreg
)
12908 struct insn_link
*links
;
12910 unsigned int regno
= REGNO (SUBREG_REG (subreg
));
12911 machine_mode mode
= GET_MODE (subreg
);
12913 if (GET_MODE_PRECISION (mode
) > HOST_BITS_PER_WIDE_INT
)
12916 for (links
= LOG_LINKS (insn
); links
;)
12918 reg_stat_type
*rsp
;
12920 insn
= links
->insn
;
12921 set
= single_set (insn
);
12923 if (! set
|| !REG_P (SET_DEST (set
))
12924 || REGNO (SET_DEST (set
)) != regno
12925 || GET_MODE (SET_DEST (set
)) != GET_MODE (SUBREG_REG (subreg
)))
12927 links
= links
->next
;
12931 rsp
= ®_stat
[regno
];
12932 if (rsp
->last_set
== insn
)
12934 if (SUBREG_PROMOTED_UNSIGNED_P (subreg
))
12935 rsp
->last_set_nonzero_bits
&= GET_MODE_MASK (mode
);
12938 if (REG_P (SET_SRC (set
)))
12940 regno
= REGNO (SET_SRC (set
));
12941 links
= LOG_LINKS (insn
);
12948 /* Check if X, a register, is known to contain a value already
12949 truncated to MODE. In this case we can use a subreg to refer to
12950 the truncated value even though in the generic case we would need
12951 an explicit truncation. */
12954 reg_truncated_to_mode (machine_mode mode
, const_rtx x
)
12956 reg_stat_type
*rsp
= ®_stat
[REGNO (x
)];
12957 machine_mode truncated
= rsp
->truncated_to_mode
;
12960 || rsp
->truncation_label
< label_tick_ebb_start
)
12962 if (GET_MODE_SIZE (truncated
) <= GET_MODE_SIZE (mode
))
12964 if (TRULY_NOOP_TRUNCATION_MODES_P (mode
, truncated
))
12969 /* If X is a hard reg or a subreg record the mode that the register is
12970 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12971 to turn a truncate into a subreg using this information. Return true
12972 if traversing X is complete. */
12975 record_truncated_value (rtx x
)
12977 machine_mode truncated_mode
;
12978 reg_stat_type
*rsp
;
12980 if (GET_CODE (x
) == SUBREG
&& REG_P (SUBREG_REG (x
)))
12982 machine_mode original_mode
= GET_MODE (SUBREG_REG (x
));
12983 truncated_mode
= GET_MODE (x
);
12985 if (GET_MODE_SIZE (original_mode
) <= GET_MODE_SIZE (truncated_mode
))
12988 if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode
, original_mode
))
12991 x
= SUBREG_REG (x
);
12993 /* ??? For hard-regs we now record everything. We might be able to
12994 optimize this using last_set_mode. */
12995 else if (REG_P (x
) && REGNO (x
) < FIRST_PSEUDO_REGISTER
)
12996 truncated_mode
= GET_MODE (x
);
13000 rsp
= ®_stat
[REGNO (x
)];
13001 if (rsp
->truncated_to_mode
== 0
13002 || rsp
->truncation_label
< label_tick_ebb_start
13003 || (GET_MODE_SIZE (truncated_mode
)
13004 < GET_MODE_SIZE (rsp
->truncated_to_mode
)))
13006 rsp
->truncated_to_mode
= truncated_mode
;
13007 rsp
->truncation_label
= label_tick
;
13013 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13014 the modes they are used in. This can help truning TRUNCATEs into
13018 record_truncated_values (rtx
*loc
, void *data ATTRIBUTE_UNUSED
)
13020 subrtx_var_iterator::array_type array
;
13021 FOR_EACH_SUBRTX_VAR (iter
, array
, *loc
, NONCONST
)
13022 if (record_truncated_value (*iter
))
13023 iter
.skip_subrtxes ();
13026 /* Scan X for promoted SUBREGs. For each one found,
13027 note what it implies to the registers used in it. */
13030 check_promoted_subreg (rtx_insn
*insn
, rtx x
)
13032 if (GET_CODE (x
) == SUBREG
13033 && SUBREG_PROMOTED_VAR_P (x
)
13034 && REG_P (SUBREG_REG (x
)))
13035 record_promoted_value (insn
, x
);
13038 const char *format
= GET_RTX_FORMAT (GET_CODE (x
));
13041 for (i
= 0; i
< GET_RTX_LENGTH (GET_CODE (x
)); i
++)
13045 check_promoted_subreg (insn
, XEXP (x
, i
));
13049 if (XVEC (x
, i
) != 0)
13050 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13051 check_promoted_subreg (insn
, XVECEXP (x
, i
, j
));
13057 /* Verify that all the registers and memory references mentioned in *LOC are
13058 still valid. *LOC was part of a value set in INSN when label_tick was
13059 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13060 the invalid references with (clobber (const_int 0)) and return 1. This
13061 replacement is useful because we often can get useful information about
13062 the form of a value (e.g., if it was produced by a shift that always
13063 produces -1 or 0) even though we don't know exactly what registers it
13064 was produced from. */
13067 get_last_value_validate (rtx
*loc
, rtx_insn
*insn
, int tick
, int replace
)
13070 const char *fmt
= GET_RTX_FORMAT (GET_CODE (x
));
13071 int len
= GET_RTX_LENGTH (GET_CODE (x
));
13076 unsigned int regno
= REGNO (x
);
13077 unsigned int endregno
= END_REGNO (x
);
13080 for (j
= regno
; j
< endregno
; j
++)
13082 reg_stat_type
*rsp
= ®_stat
[j
];
13083 if (rsp
->last_set_invalid
13084 /* If this is a pseudo-register that was only set once and not
13085 live at the beginning of the function, it is always valid. */
13086 || (! (regno
>= FIRST_PSEUDO_REGISTER
13087 && regno
< reg_n_sets_max
13088 && REG_N_SETS (regno
) == 1
13089 && (!REGNO_REG_SET_P
13090 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
),
13092 && rsp
->last_set_label
> tick
))
13095 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13102 /* If this is a memory reference, make sure that there were no stores after
13103 it that might have clobbered the value. We don't have alias info, so we
13104 assume any store invalidates it. Moreover, we only have local UIDs, so
13105 we also assume that there were stores in the intervening basic blocks. */
13106 else if (MEM_P (x
) && !MEM_READONLY_P (x
)
13107 && (tick
!= label_tick
|| DF_INSN_LUID (insn
) <= mem_last_set
))
13110 *loc
= gen_rtx_CLOBBER (GET_MODE (x
), const0_rtx
);
13114 for (i
= 0; i
< len
; i
++)
13118 /* Check for identical subexpressions. If x contains
13119 identical subexpression we only have to traverse one of
13121 if (i
== 1 && ARITHMETIC_P (x
))
13123 /* Note that at this point x0 has already been checked
13124 and found valid. */
13125 rtx x0
= XEXP (x
, 0);
13126 rtx x1
= XEXP (x
, 1);
13128 /* If x0 and x1 are identical then x is also valid. */
13132 /* If x1 is identical to a subexpression of x0 then
13133 while checking x0, x1 has already been checked. Thus
13134 it is valid and so as x. */
13135 if (ARITHMETIC_P (x0
)
13136 && (x1
== XEXP (x0
, 0) || x1
== XEXP (x0
, 1)))
13139 /* If x0 is identical to a subexpression of x1 then x is
13140 valid iff the rest of x1 is valid. */
13141 if (ARITHMETIC_P (x1
)
13142 && (x0
== XEXP (x1
, 0) || x0
== XEXP (x1
, 1)))
13144 get_last_value_validate (&XEXP (x1
,
13145 x0
== XEXP (x1
, 0) ? 1 : 0),
13146 insn
, tick
, replace
);
13149 if (get_last_value_validate (&XEXP (x
, i
), insn
, tick
,
13153 else if (fmt
[i
] == 'E')
13154 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13155 if (get_last_value_validate (&XVECEXP (x
, i
, j
),
13156 insn
, tick
, replace
) == 0)
13160 /* If we haven't found a reason for it to be invalid, it is valid. */
13164 /* Get the last value assigned to X, if known. Some registers
13165 in the value may be replaced with (clobber (const_int 0)) if their value
13166 is known longer known reliably. */
13169 get_last_value (const_rtx x
)
13171 unsigned int regno
;
13173 reg_stat_type
*rsp
;
13175 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13176 then convert it to the desired mode. If this is a paradoxical SUBREG,
13177 we cannot predict what values the "extra" bits might have. */
13178 if (GET_CODE (x
) == SUBREG
13179 && subreg_lowpart_p (x
)
13180 && !paradoxical_subreg_p (x
)
13181 && (value
= get_last_value (SUBREG_REG (x
))) != 0)
13182 return gen_lowpart (GET_MODE (x
), value
);
13188 rsp
= ®_stat
[regno
];
13189 value
= rsp
->last_set_value
;
13191 /* If we don't have a value, or if it isn't for this basic block and
13192 it's either a hard register, set more than once, or it's a live
13193 at the beginning of the function, return 0.
13195 Because if it's not live at the beginning of the function then the reg
13196 is always set before being used (is never used without being set).
13197 And, if it's set only once, and it's always set before use, then all
13198 uses must have the same last value, even if it's not from this basic
13202 || (rsp
->last_set_label
< label_tick_ebb_start
13203 && (regno
< FIRST_PSEUDO_REGISTER
13204 || regno
>= reg_n_sets_max
13205 || REG_N_SETS (regno
) != 1
13207 (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun
)->next_bb
), regno
))))
13210 /* If the value was set in a later insn than the ones we are processing,
13211 we can't use it even if the register was only set once. */
13212 if (rsp
->last_set_label
== label_tick
13213 && DF_INSN_LUID (rsp
->last_set
) >= subst_low_luid
)
13216 /* If fewer bits were set than what we are asked for now, we cannot use
13218 if (GET_MODE_PRECISION (rsp
->last_set_mode
)
13219 < GET_MODE_PRECISION (GET_MODE (x
)))
13222 /* If the value has all its registers valid, return it. */
13223 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 0))
13226 /* Otherwise, make a copy and replace any invalid register with
13227 (clobber (const_int 0)). If that fails for some reason, return 0. */
13229 value
= copy_rtx (value
);
13230 if (get_last_value_validate (&value
, rsp
->last_set
, rsp
->last_set_label
, 1))
13236 /* Return nonzero if expression X refers to a REG or to memory
13237 that is set in an instruction more recent than FROM_LUID. */
13240 use_crosses_set_p (const_rtx x
, int from_luid
)
13244 enum rtx_code code
= GET_CODE (x
);
13248 unsigned int regno
= REGNO (x
);
13249 unsigned endreg
= END_REGNO (x
);
13251 #ifdef PUSH_ROUNDING
13252 /* Don't allow uses of the stack pointer to be moved,
13253 because we don't know whether the move crosses a push insn. */
13254 if (regno
== STACK_POINTER_REGNUM
&& PUSH_ARGS
)
13257 for (; regno
< endreg
; regno
++)
13259 reg_stat_type
*rsp
= ®_stat
[regno
];
13261 && rsp
->last_set_label
== label_tick
13262 && DF_INSN_LUID (rsp
->last_set
) > from_luid
)
13268 if (code
== MEM
&& mem_last_set
> from_luid
)
13271 fmt
= GET_RTX_FORMAT (code
);
13273 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13278 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13279 if (use_crosses_set_p (XVECEXP (x
, i
, j
), from_luid
))
13282 else if (fmt
[i
] == 'e'
13283 && use_crosses_set_p (XEXP (x
, i
), from_luid
))
13289 /* Define three variables used for communication between the following
13292 static unsigned int reg_dead_regno
, reg_dead_endregno
;
13293 static int reg_dead_flag
;
13295 /* Function called via note_stores from reg_dead_at_p.
13297 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13298 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13301 reg_dead_at_p_1 (rtx dest
, const_rtx x
, void *data ATTRIBUTE_UNUSED
)
13303 unsigned int regno
, endregno
;
13308 regno
= REGNO (dest
);
13309 endregno
= END_REGNO (dest
);
13310 if (reg_dead_endregno
> regno
&& reg_dead_regno
< endregno
)
13311 reg_dead_flag
= (GET_CODE (x
) == CLOBBER
) ? 1 : -1;
13314 /* Return nonzero if REG is known to be dead at INSN.
13316 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13317 referencing REG, it is dead. If we hit a SET referencing REG, it is
13318 live. Otherwise, see if it is live or dead at the start of the basic
13319 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13320 must be assumed to be always live. */
13323 reg_dead_at_p (rtx reg
, rtx_insn
*insn
)
13328 /* Set variables for reg_dead_at_p_1. */
13329 reg_dead_regno
= REGNO (reg
);
13330 reg_dead_endregno
= END_REGNO (reg
);
13334 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13335 we allow the machine description to decide whether use-and-clobber
13336 patterns are OK. */
13337 if (reg_dead_regno
< FIRST_PSEUDO_REGISTER
)
13339 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13340 if (!fixed_regs
[i
] && TEST_HARD_REG_BIT (newpat_used_regs
, i
))
13344 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13345 beginning of basic block. */
13346 block
= BLOCK_FOR_INSN (insn
);
13351 if (find_regno_note (insn
, REG_UNUSED
, reg_dead_regno
))
13354 note_stores (PATTERN (insn
), reg_dead_at_p_1
, NULL
);
13356 return reg_dead_flag
== 1 ? 1 : 0;
13358 if (find_regno_note (insn
, REG_DEAD
, reg_dead_regno
))
13362 if (insn
== BB_HEAD (block
))
13365 insn
= PREV_INSN (insn
);
13368 /* Look at live-in sets for the basic block that we were in. */
13369 for (i
= reg_dead_regno
; i
< reg_dead_endregno
; i
++)
13370 if (REGNO_REG_SET_P (df_get_live_in (block
), i
))
13376 /* Note hard registers in X that are used. */
13379 mark_used_regs_combine (rtx x
)
13381 RTX_CODE code
= GET_CODE (x
);
13382 unsigned int regno
;
13393 case ADDR_DIFF_VEC
:
13395 /* CC0 must die in the insn after it is set, so we don't need to take
13396 special note of it here. */
13401 /* If we are clobbering a MEM, mark any hard registers inside the
13402 address as used. */
13403 if (MEM_P (XEXP (x
, 0)))
13404 mark_used_regs_combine (XEXP (XEXP (x
, 0), 0));
13409 /* A hard reg in a wide mode may really be multiple registers.
13410 If so, mark all of them just like the first. */
13411 if (regno
< FIRST_PSEUDO_REGISTER
)
13413 /* None of this applies to the stack, frame or arg pointers. */
13414 if (regno
== STACK_POINTER_REGNUM
13415 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13416 && regno
== HARD_FRAME_POINTER_REGNUM
)
13417 || (FRAME_POINTER_REGNUM
!= ARG_POINTER_REGNUM
13418 && regno
== ARG_POINTER_REGNUM
&& fixed_regs
[regno
])
13419 || regno
== FRAME_POINTER_REGNUM
)
13422 add_to_hard_reg_set (&newpat_used_regs
, GET_MODE (x
), regno
);
13428 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13430 rtx testreg
= SET_DEST (x
);
13432 while (GET_CODE (testreg
) == SUBREG
13433 || GET_CODE (testreg
) == ZERO_EXTRACT
13434 || GET_CODE (testreg
) == STRICT_LOW_PART
)
13435 testreg
= XEXP (testreg
, 0);
13437 if (MEM_P (testreg
))
13438 mark_used_regs_combine (XEXP (testreg
, 0));
13440 mark_used_regs_combine (SET_SRC (x
));
13448 /* Recursively scan the operands of this expression. */
13451 const char *fmt
= GET_RTX_FORMAT (code
);
13453 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
13456 mark_used_regs_combine (XEXP (x
, i
));
13457 else if (fmt
[i
] == 'E')
13461 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
13462 mark_used_regs_combine (XVECEXP (x
, i
, j
));
13468 /* Remove register number REGNO from the dead registers list of INSN.
13470 Return the note used to record the death, if there was one. */
13473 remove_death (unsigned int regno
, rtx_insn
*insn
)
13475 rtx note
= find_regno_note (insn
, REG_DEAD
, regno
);
13478 remove_note (insn
, note
);
13483 /* For each register (hardware or pseudo) used within expression X, if its
13484 death is in an instruction with luid between FROM_LUID (inclusive) and
13485 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13486 list headed by PNOTES.
13488 That said, don't move registers killed by maybe_kill_insn.
13490 This is done when X is being merged by combination into TO_INSN. These
13491 notes will then be distributed as needed. */
13494 move_deaths (rtx x
, rtx maybe_kill_insn
, int from_luid
, rtx_insn
*to_insn
,
13499 enum rtx_code code
= GET_CODE (x
);
13503 unsigned int regno
= REGNO (x
);
13504 rtx_insn
*where_dead
= reg_stat
[regno
].last_death
;
13506 /* Don't move the register if it gets killed in between from and to. */
13507 if (maybe_kill_insn
&& reg_set_p (x
, maybe_kill_insn
)
13508 && ! reg_referenced_p (x
, maybe_kill_insn
))
13512 && BLOCK_FOR_INSN (where_dead
) == BLOCK_FOR_INSN (to_insn
)
13513 && DF_INSN_LUID (where_dead
) >= from_luid
13514 && DF_INSN_LUID (where_dead
) < DF_INSN_LUID (to_insn
))
13516 rtx note
= remove_death (regno
, where_dead
);
13518 /* It is possible for the call above to return 0. This can occur
13519 when last_death points to I2 or I1 that we combined with.
13520 In that case make a new note.
13522 We must also check for the case where X is a hard register
13523 and NOTE is a death note for a range of hard registers
13524 including X. In that case, we must put REG_DEAD notes for
13525 the remaining registers in place of NOTE. */
13527 if (note
!= 0 && regno
< FIRST_PSEUDO_REGISTER
13528 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13529 > GET_MODE_SIZE (GET_MODE (x
))))
13531 unsigned int deadregno
= REGNO (XEXP (note
, 0));
13532 unsigned int deadend
= END_REGNO (XEXP (note
, 0));
13533 unsigned int ourend
= END_REGNO (x
);
13536 for (i
= deadregno
; i
< deadend
; i
++)
13537 if (i
< regno
|| i
>= ourend
)
13538 add_reg_note (where_dead
, REG_DEAD
, regno_reg_rtx
[i
]);
13541 /* If we didn't find any note, or if we found a REG_DEAD note that
13542 covers only part of the given reg, and we have a multi-reg hard
13543 register, then to be safe we must check for REG_DEAD notes
13544 for each register other than the first. They could have
13545 their own REG_DEAD notes lying around. */
13546 else if ((note
== 0
13548 && (GET_MODE_SIZE (GET_MODE (XEXP (note
, 0)))
13549 < GET_MODE_SIZE (GET_MODE (x
)))))
13550 && regno
< FIRST_PSEUDO_REGISTER
13551 && REG_NREGS (x
) > 1)
13553 unsigned int ourend
= END_REGNO (x
);
13554 unsigned int i
, offset
;
13558 offset
= hard_regno_nregs
[regno
][GET_MODE (XEXP (note
, 0))];
13562 for (i
= regno
+ offset
; i
< ourend
; i
++)
13563 move_deaths (regno_reg_rtx
[i
],
13564 maybe_kill_insn
, from_luid
, to_insn
, &oldnotes
);
13567 if (note
!= 0 && GET_MODE (XEXP (note
, 0)) == GET_MODE (x
))
13569 XEXP (note
, 1) = *pnotes
;
13573 *pnotes
= alloc_reg_note (REG_DEAD
, x
, *pnotes
);
13579 else if (GET_CODE (x
) == SET
)
13581 rtx dest
= SET_DEST (x
);
13583 move_deaths (SET_SRC (x
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13585 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13586 that accesses one word of a multi-word item, some
13587 piece of everything register in the expression is used by
13588 this insn, so remove any old death. */
13589 /* ??? So why do we test for equality of the sizes? */
13591 if (GET_CODE (dest
) == ZERO_EXTRACT
13592 || GET_CODE (dest
) == STRICT_LOW_PART
13593 || (GET_CODE (dest
) == SUBREG
13594 && (((GET_MODE_SIZE (GET_MODE (dest
))
13595 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
)
13596 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest
)))
13597 + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
))))
13599 move_deaths (dest
, maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13603 /* If this is some other SUBREG, we know it replaces the entire
13604 value, so use that as the destination. */
13605 if (GET_CODE (dest
) == SUBREG
)
13606 dest
= SUBREG_REG (dest
);
13608 /* If this is a MEM, adjust deaths of anything used in the address.
13609 For a REG (the only other possibility), the entire value is
13610 being replaced so the old value is not used in this insn. */
13613 move_deaths (XEXP (dest
, 0), maybe_kill_insn
, from_luid
,
13618 else if (GET_CODE (x
) == CLOBBER
)
13621 len
= GET_RTX_LENGTH (code
);
13622 fmt
= GET_RTX_FORMAT (code
);
13624 for (i
= 0; i
< len
; i
++)
13629 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
13630 move_deaths (XVECEXP (x
, i
, j
), maybe_kill_insn
, from_luid
,
13633 else if (fmt
[i
] == 'e')
13634 move_deaths (XEXP (x
, i
), maybe_kill_insn
, from_luid
, to_insn
, pnotes
);
13638 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13639 pattern of an insn. X must be a REG. */
13642 reg_bitfield_target_p (rtx x
, rtx body
)
13646 if (GET_CODE (body
) == SET
)
13648 rtx dest
= SET_DEST (body
);
13650 unsigned int regno
, tregno
, endregno
, endtregno
;
13652 if (GET_CODE (dest
) == ZERO_EXTRACT
)
13653 target
= XEXP (dest
, 0);
13654 else if (GET_CODE (dest
) == STRICT_LOW_PART
)
13655 target
= SUBREG_REG (XEXP (dest
, 0));
13659 if (GET_CODE (target
) == SUBREG
)
13660 target
= SUBREG_REG (target
);
13662 if (!REG_P (target
))
13665 tregno
= REGNO (target
), regno
= REGNO (x
);
13666 if (tregno
>= FIRST_PSEUDO_REGISTER
|| regno
>= FIRST_PSEUDO_REGISTER
)
13667 return target
== x
;
13669 endtregno
= end_hard_regno (GET_MODE (target
), tregno
);
13670 endregno
= end_hard_regno (GET_MODE (x
), regno
);
13672 return endregno
> tregno
&& regno
< endtregno
;
13675 else if (GET_CODE (body
) == PARALLEL
)
13676 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; i
--)
13677 if (reg_bitfield_target_p (x
, XVECEXP (body
, 0, i
)))
13683 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13684 as appropriate. I3 and I2 are the insns resulting from the combination
13685 insns including FROM (I2 may be zero).
13687 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13688 not need REG_DEAD notes because they are being substituted for. This
13689 saves searching in the most common cases.
13691 Each note in the list is either ignored or placed on some insns, depending
13692 on the type of note. */
13695 distribute_notes (rtx notes
, rtx_insn
*from_insn
, rtx_insn
*i3
, rtx_insn
*i2
,
13696 rtx elim_i2
, rtx elim_i1
, rtx elim_i0
)
13698 rtx note
, next_note
;
13700 rtx_insn
*tem_insn
;
13702 for (note
= notes
; note
; note
= next_note
)
13704 rtx_insn
*place
= 0, *place2
= 0;
13706 next_note
= XEXP (note
, 1);
13707 switch (REG_NOTE_KIND (note
))
13711 /* Doesn't matter much where we put this, as long as it's somewhere.
13712 It is preferable to keep these notes on branches, which is most
13713 likely to be i3. */
13717 case REG_NON_LOCAL_GOTO
:
13722 gcc_assert (i2
&& JUMP_P (i2
));
13727 case REG_EH_REGION
:
13728 /* These notes must remain with the call or trapping instruction. */
13731 else if (i2
&& CALL_P (i2
))
13735 gcc_assert (cfun
->can_throw_non_call_exceptions
);
13736 if (may_trap_p (i3
))
13738 else if (i2
&& may_trap_p (i2
))
13740 /* ??? Otherwise assume we've combined things such that we
13741 can now prove that the instructions can't trap. Drop the
13742 note in this case. */
13746 case REG_ARGS_SIZE
:
13747 /* ??? How to distribute between i3-i1. Assume i3 contains the
13748 entire adjustment. Assert i3 contains at least some adjust. */
13749 if (!noop_move_p (i3
))
13751 int old_size
, args_size
= INTVAL (XEXP (note
, 0));
13752 /* fixup_args_size_notes looks at REG_NORETURN note,
13753 so ensure the note is placed there first. */
13757 for (np
= &next_note
; *np
; np
= &XEXP (*np
, 1))
13758 if (REG_NOTE_KIND (*np
) == REG_NORETURN
)
13762 XEXP (n
, 1) = REG_NOTES (i3
);
13763 REG_NOTES (i3
) = n
;
13767 old_size
= fixup_args_size_notes (PREV_INSN (i3
), i3
, args_size
);
13768 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13769 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13770 gcc_assert (old_size
!= args_size
13772 && !ACCUMULATE_OUTGOING_ARGS
13773 && find_reg_note (i3
, REG_NORETURN
, NULL_RTX
)));
13780 case REG_CALL_DECL
:
13781 /* These notes must remain with the call. It should not be
13782 possible for both I2 and I3 to be a call. */
13787 gcc_assert (i2
&& CALL_P (i2
));
13793 /* Any clobbers for i3 may still exist, and so we must process
13794 REG_UNUSED notes from that insn.
13796 Any clobbers from i2 or i1 can only exist if they were added by
13797 recog_for_combine. In that case, recog_for_combine created the
13798 necessary REG_UNUSED notes. Trying to keep any original
13799 REG_UNUSED notes from these insns can cause incorrect output
13800 if it is for the same register as the original i3 dest.
13801 In that case, we will notice that the register is set in i3,
13802 and then add a REG_UNUSED note for the destination of i3, which
13803 is wrong. However, it is possible to have REG_UNUSED notes from
13804 i2 or i1 for register which were both used and clobbered, so
13805 we keep notes from i2 or i1 if they will turn into REG_DEAD
13808 /* If this register is set or clobbered in I3, put the note there
13809 unless there is one already. */
13810 if (reg_set_p (XEXP (note
, 0), PATTERN (i3
)))
13812 if (from_insn
!= i3
)
13815 if (! (REG_P (XEXP (note
, 0))
13816 ? find_regno_note (i3
, REG_UNUSED
, REGNO (XEXP (note
, 0)))
13817 : find_reg_note (i3
, REG_UNUSED
, XEXP (note
, 0))))
13820 /* Otherwise, if this register is used by I3, then this register
13821 now dies here, so we must put a REG_DEAD note here unless there
13823 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
))
13824 && ! (REG_P (XEXP (note
, 0))
13825 ? find_regno_note (i3
, REG_DEAD
,
13826 REGNO (XEXP (note
, 0)))
13827 : find_reg_note (i3
, REG_DEAD
, XEXP (note
, 0))))
13829 PUT_REG_NOTE_KIND (note
, REG_DEAD
);
13837 /* These notes say something about results of an insn. We can
13838 only support them if they used to be on I3 in which case they
13839 remain on I3. Otherwise they are ignored.
13841 If the note refers to an expression that is not a constant, we
13842 must also ignore the note since we cannot tell whether the
13843 equivalence is still true. It might be possible to do
13844 slightly better than this (we only have a problem if I2DEST
13845 or I1DEST is present in the expression), but it doesn't
13846 seem worth the trouble. */
13848 if (from_insn
== i3
13849 && (XEXP (note
, 0) == 0 || CONSTANT_P (XEXP (note
, 0))))
13854 /* These notes say something about how a register is used. They must
13855 be present on any use of the register in I2 or I3. */
13856 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
)))
13859 if (i2
&& reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
)))
13868 case REG_LABEL_TARGET
:
13869 case REG_LABEL_OPERAND
:
13870 /* This can show up in several ways -- either directly in the
13871 pattern, or hidden off in the constant pool with (or without?)
13872 a REG_EQUAL note. */
13873 /* ??? Ignore the without-reg_equal-note problem for now. */
13874 if (reg_mentioned_p (XEXP (note
, 0), PATTERN (i3
))
13875 || ((tem_note
= find_reg_note (i3
, REG_EQUAL
, NULL_RTX
))
13876 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
13877 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0)))
13881 && (reg_mentioned_p (XEXP (note
, 0), PATTERN (i2
))
13882 || ((tem_note
= find_reg_note (i2
, REG_EQUAL
, NULL_RTX
))
13883 && GET_CODE (XEXP (tem_note
, 0)) == LABEL_REF
13884 && label_ref_label (XEXP (tem_note
, 0)) == XEXP (note
, 0))))
13892 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13893 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13895 if (place
&& JUMP_P (place
)
13896 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13897 && (JUMP_LABEL (place
) == NULL
13898 || JUMP_LABEL (place
) == XEXP (note
, 0)))
13900 rtx label
= JUMP_LABEL (place
);
13903 JUMP_LABEL (place
) = XEXP (note
, 0);
13904 else if (LABEL_P (label
))
13905 LABEL_NUSES (label
)--;
13908 if (place2
&& JUMP_P (place2
)
13909 && REG_NOTE_KIND (note
) == REG_LABEL_TARGET
13910 && (JUMP_LABEL (place2
) == NULL
13911 || JUMP_LABEL (place2
) == XEXP (note
, 0)))
13913 rtx label
= JUMP_LABEL (place2
);
13916 JUMP_LABEL (place2
) = XEXP (note
, 0);
13917 else if (LABEL_P (label
))
13918 LABEL_NUSES (label
)--;
13924 /* This note says something about the value of a register prior
13925 to the execution of an insn. It is too much trouble to see
13926 if the note is still correct in all situations. It is better
13927 to simply delete it. */
13931 /* If we replaced the right hand side of FROM_INSN with a
13932 REG_EQUAL note, the original use of the dying register
13933 will not have been combined into I3 and I2. In such cases,
13934 FROM_INSN is guaranteed to be the first of the combined
13935 instructions, so we simply need to search back before
13936 FROM_INSN for the previous use or set of this register,
13937 then alter the notes there appropriately.
13939 If the register is used as an input in I3, it dies there.
13940 Similarly for I2, if it is nonzero and adjacent to I3.
13942 If the register is not used as an input in either I3 or I2
13943 and it is not one of the registers we were supposed to eliminate,
13944 there are two possibilities. We might have a non-adjacent I2
13945 or we might have somehow eliminated an additional register
13946 from a computation. For example, we might have had A & B where
13947 we discover that B will always be zero. In this case we will
13948 eliminate the reference to A.
13950 In both cases, we must search to see if we can find a previous
13951 use of A and put the death note there. */
13954 && from_insn
== i2mod
13955 && !reg_overlap_mentioned_p (XEXP (note
, 0), i2mod_new_rhs
))
13956 tem_insn
= from_insn
;
13960 && CALL_P (from_insn
)
13961 && find_reg_fusage (from_insn
, USE
, XEXP (note
, 0)))
13963 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (i3
)))
13965 else if (i2
!= 0 && next_nonnote_nondebug_insn (i2
) == i3
13966 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
13968 else if ((rtx_equal_p (XEXP (note
, 0), elim_i2
)
13970 && reg_overlap_mentioned_p (XEXP (note
, 0),
13972 || rtx_equal_p (XEXP (note
, 0), elim_i1
)
13973 || rtx_equal_p (XEXP (note
, 0), elim_i0
))
13976 /* If the new I2 sets the same register that is marked dead
13977 in the note, we do not know where to put the note.
13979 if (i2
!= 0 && reg_set_p (XEXP (note
, 0), PATTERN (i2
)))
13985 basic_block bb
= this_basic_block
;
13987 for (tem_insn
= PREV_INSN (tem_insn
); place
== 0; tem_insn
= PREV_INSN (tem_insn
))
13989 if (!NONDEBUG_INSN_P (tem_insn
))
13991 if (tem_insn
== BB_HEAD (bb
))
13996 /* If the register is being set at TEM_INSN, see if that is all
13997 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13998 into a REG_UNUSED note instead. Don't delete sets to
13999 global register vars. */
14000 if ((REGNO (XEXP (note
, 0)) >= FIRST_PSEUDO_REGISTER
14001 || !global_regs
[REGNO (XEXP (note
, 0))])
14002 && reg_set_p (XEXP (note
, 0), PATTERN (tem_insn
)))
14004 rtx set
= single_set (tem_insn
);
14005 rtx inner_dest
= 0;
14006 rtx_insn
*cc0_setter
= NULL
;
14009 for (inner_dest
= SET_DEST (set
);
14010 (GET_CODE (inner_dest
) == STRICT_LOW_PART
14011 || GET_CODE (inner_dest
) == SUBREG
14012 || GET_CODE (inner_dest
) == ZERO_EXTRACT
);
14013 inner_dest
= XEXP (inner_dest
, 0))
14016 /* Verify that it was the set, and not a clobber that
14017 modified the register.
14019 CC0 targets must be careful to maintain setter/user
14020 pairs. If we cannot delete the setter due to side
14021 effects, mark the user with an UNUSED note instead
14024 if (set
!= 0 && ! side_effects_p (SET_SRC (set
))
14025 && rtx_equal_p (XEXP (note
, 0), inner_dest
)
14027 || (! reg_mentioned_p (cc0_rtx
, SET_SRC (set
))
14028 || ((cc0_setter
= prev_cc0_setter (tem_insn
)) != NULL
14029 && sets_cc0_p (PATTERN (cc0_setter
)) > 0))))
14031 /* Move the notes and links of TEM_INSN elsewhere.
14032 This might delete other dead insns recursively.
14033 First set the pattern to something that won't use
14035 rtx old_notes
= REG_NOTES (tem_insn
);
14037 PATTERN (tem_insn
) = pc_rtx
;
14038 REG_NOTES (tem_insn
) = NULL
;
14040 distribute_notes (old_notes
, tem_insn
, tem_insn
, NULL
,
14041 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14042 distribute_links (LOG_LINKS (tem_insn
));
14044 SET_INSN_DELETED (tem_insn
);
14045 if (tem_insn
== i2
)
14048 /* Delete the setter too. */
14051 PATTERN (cc0_setter
) = pc_rtx
;
14052 old_notes
= REG_NOTES (cc0_setter
);
14053 REG_NOTES (cc0_setter
) = NULL
;
14055 distribute_notes (old_notes
, cc0_setter
,
14057 NULL_RTX
, NULL_RTX
, NULL_RTX
);
14058 distribute_links (LOG_LINKS (cc0_setter
));
14060 SET_INSN_DELETED (cc0_setter
);
14061 if (cc0_setter
== i2
)
14067 PUT_REG_NOTE_KIND (note
, REG_UNUSED
);
14069 /* If there isn't already a REG_UNUSED note, put one
14070 here. Do not place a REG_DEAD note, even if
14071 the register is also used here; that would not
14072 match the algorithm used in lifetime analysis
14073 and can cause the consistency check in the
14074 scheduler to fail. */
14075 if (! find_regno_note (tem_insn
, REG_UNUSED
,
14076 REGNO (XEXP (note
, 0))))
14081 else if (reg_referenced_p (XEXP (note
, 0), PATTERN (tem_insn
))
14082 || (CALL_P (tem_insn
)
14083 && find_reg_fusage (tem_insn
, USE
, XEXP (note
, 0))))
14087 /* If we are doing a 3->2 combination, and we have a
14088 register which formerly died in i3 and was not used
14089 by i2, which now no longer dies in i3 and is used in
14090 i2 but does not die in i2, and place is between i2
14091 and i3, then we may need to move a link from place to
14093 if (i2
&& DF_INSN_LUID (place
) > DF_INSN_LUID (i2
)
14095 && DF_INSN_LUID (from_insn
) > DF_INSN_LUID (i2
)
14096 && reg_referenced_p (XEXP (note
, 0), PATTERN (i2
)))
14098 struct insn_link
*links
= LOG_LINKS (place
);
14099 LOG_LINKS (place
) = NULL
;
14100 distribute_links (links
);
14105 if (tem_insn
== BB_HEAD (bb
))
14111 /* If the register is set or already dead at PLACE, we needn't do
14112 anything with this note if it is still a REG_DEAD note.
14113 We check here if it is set at all, not if is it totally replaced,
14114 which is what `dead_or_set_p' checks, so also check for it being
14117 if (place
&& REG_NOTE_KIND (note
) == REG_DEAD
)
14119 unsigned int regno
= REGNO (XEXP (note
, 0));
14120 reg_stat_type
*rsp
= ®_stat
[regno
];
14122 if (dead_or_set_p (place
, XEXP (note
, 0))
14123 || reg_bitfield_target_p (XEXP (note
, 0), PATTERN (place
)))
14125 /* Unless the register previously died in PLACE, clear
14126 last_death. [I no longer understand why this is
14128 if (rsp
->last_death
!= place
)
14129 rsp
->last_death
= 0;
14133 rsp
->last_death
= place
;
14135 /* If this is a death note for a hard reg that is occupying
14136 multiple registers, ensure that we are still using all
14137 parts of the object. If we find a piece of the object
14138 that is unused, we must arrange for an appropriate REG_DEAD
14139 note to be added for it. However, we can't just emit a USE
14140 and tag the note to it, since the register might actually
14141 be dead; so we recourse, and the recursive call then finds
14142 the previous insn that used this register. */
14144 if (place
&& REG_NREGS (XEXP (note
, 0)) > 1)
14146 unsigned int endregno
= END_REGNO (XEXP (note
, 0));
14147 bool all_used
= true;
14150 for (i
= regno
; i
< endregno
; i
++)
14151 if ((! refers_to_regno_p (i
, PATTERN (place
))
14152 && ! find_regno_fusage (place
, USE
, i
))
14153 || dead_or_set_regno_p (place
, i
))
14161 /* Put only REG_DEAD notes for pieces that are
14162 not already dead or set. */
14164 for (i
= regno
; i
< endregno
;
14165 i
+= hard_regno_nregs
[i
][reg_raw_mode
[i
]])
14167 rtx piece
= regno_reg_rtx
[i
];
14168 basic_block bb
= this_basic_block
;
14170 if (! dead_or_set_p (place
, piece
)
14171 && ! reg_bitfield_target_p (piece
,
14174 rtx new_note
= alloc_reg_note (REG_DEAD
, piece
,
14177 distribute_notes (new_note
, place
, place
,
14178 NULL
, NULL_RTX
, NULL_RTX
,
14181 else if (! refers_to_regno_p (i
, PATTERN (place
))
14182 && ! find_regno_fusage (place
, USE
, i
))
14183 for (tem_insn
= PREV_INSN (place
); ;
14184 tem_insn
= PREV_INSN (tem_insn
))
14186 if (!NONDEBUG_INSN_P (tem_insn
))
14188 if (tem_insn
== BB_HEAD (bb
))
14192 if (dead_or_set_p (tem_insn
, piece
)
14193 || reg_bitfield_target_p (piece
,
14194 PATTERN (tem_insn
)))
14196 add_reg_note (tem_insn
, REG_UNUSED
, piece
);
14209 /* Any other notes should not be present at this point in the
14211 gcc_unreachable ();
14216 XEXP (note
, 1) = REG_NOTES (place
);
14217 REG_NOTES (place
) = note
;
14221 add_shallow_copy_of_reg_note (place2
, note
);
14225 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14226 I3, I2, and I1 to new locations. This is also called to add a link
14227 pointing at I3 when I3's destination is changed. */
14230 distribute_links (struct insn_link
*links
)
14232 struct insn_link
*link
, *next_link
;
14234 for (link
= links
; link
; link
= next_link
)
14236 rtx_insn
*place
= 0;
14240 next_link
= link
->next
;
14242 /* If the insn that this link points to is a NOTE, ignore it. */
14243 if (NOTE_P (link
->insn
))
14247 rtx pat
= PATTERN (link
->insn
);
14248 if (GET_CODE (pat
) == SET
)
14250 else if (GET_CODE (pat
) == PARALLEL
)
14253 for (i
= 0; i
< XVECLEN (pat
, 0); i
++)
14255 set
= XVECEXP (pat
, 0, i
);
14256 if (GET_CODE (set
) != SET
)
14259 reg
= SET_DEST (set
);
14260 while (GET_CODE (reg
) == ZERO_EXTRACT
14261 || GET_CODE (reg
) == STRICT_LOW_PART
14262 || GET_CODE (reg
) == SUBREG
)
14263 reg
= XEXP (reg
, 0);
14268 if (REGNO (reg
) == link
->regno
)
14271 if (i
== XVECLEN (pat
, 0))
14277 reg
= SET_DEST (set
);
14279 while (GET_CODE (reg
) == ZERO_EXTRACT
14280 || GET_CODE (reg
) == STRICT_LOW_PART
14281 || GET_CODE (reg
) == SUBREG
)
14282 reg
= XEXP (reg
, 0);
14284 /* A LOG_LINK is defined as being placed on the first insn that uses
14285 a register and points to the insn that sets the register. Start
14286 searching at the next insn after the target of the link and stop
14287 when we reach a set of the register or the end of the basic block.
14289 Note that this correctly handles the link that used to point from
14290 I3 to I2. Also note that not much searching is typically done here
14291 since most links don't point very far away. */
14293 for (insn
= NEXT_INSN (link
->insn
);
14294 (insn
&& (this_basic_block
->next_bb
== EXIT_BLOCK_PTR_FOR_FN (cfun
)
14295 || BB_HEAD (this_basic_block
->next_bb
) != insn
));
14296 insn
= NEXT_INSN (insn
))
14297 if (DEBUG_INSN_P (insn
))
14299 else if (INSN_P (insn
) && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
14301 if (reg_referenced_p (reg
, PATTERN (insn
)))
14305 else if (CALL_P (insn
)
14306 && find_reg_fusage (insn
, USE
, reg
))
14311 else if (INSN_P (insn
) && reg_set_p (reg
, insn
))
14314 /* If we found a place to put the link, place it there unless there
14315 is already a link to the same insn as LINK at that point. */
14319 struct insn_link
*link2
;
14321 FOR_EACH_LOG_LINK (link2
, place
)
14322 if (link2
->insn
== link
->insn
&& link2
->regno
== link
->regno
)
14327 link
->next
= LOG_LINKS (place
);
14328 LOG_LINKS (place
) = link
;
14330 /* Set added_links_insn to the earliest insn we added a
14332 if (added_links_insn
== 0
14333 || DF_INSN_LUID (added_links_insn
) > DF_INSN_LUID (place
))
14334 added_links_insn
= place
;
14340 /* Check for any register or memory mentioned in EQUIV that is not
14341 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14342 of EXPR where some registers may have been replaced by constants. */
14345 unmentioned_reg_p (rtx equiv
, rtx expr
)
14347 subrtx_iterator::array_type array
;
14348 FOR_EACH_SUBRTX (iter
, array
, equiv
, NONCONST
)
14350 const_rtx x
= *iter
;
14351 if ((REG_P (x
) || MEM_P (x
))
14352 && !reg_mentioned_p (x
, expr
))
14358 DEBUG_FUNCTION
void
14359 dump_combine_stats (FILE *file
)
14363 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14364 combine_attempts
, combine_merges
, combine_extras
, combine_successes
);
14368 dump_combine_total_stats (FILE *file
)
14372 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14373 total_attempts
, total_merges
, total_extras
, total_successes
);
14376 /* Try combining insns through substitution. */
14377 static unsigned int
14378 rest_of_handle_combine (void)
14380 int rebuild_jump_labels_after_combine
;
14382 df_set_flags (DF_LR_RUN_DCE
+ DF_DEFER_INSN_RESCAN
);
14383 df_note_add_problem ();
14386 regstat_init_n_sets_and_refs ();
14387 reg_n_sets_max
= max_reg_num ();
14389 rebuild_jump_labels_after_combine
14390 = combine_instructions (get_insns (), max_reg_num ());
14392 /* Combining insns may have turned an indirect jump into a
14393 direct jump. Rebuild the JUMP_LABEL fields of jumping
14395 if (rebuild_jump_labels_after_combine
)
14397 if (dom_info_available_p (CDI_DOMINATORS
))
14398 free_dominance_info (CDI_DOMINATORS
);
14399 timevar_push (TV_JUMP
);
14400 rebuild_jump_labels (get_insns ());
14402 timevar_pop (TV_JUMP
);
14405 regstat_free_n_sets_and_refs ();
14411 const pass_data pass_data_combine
=
14413 RTL_PASS
, /* type */
14414 "combine", /* name */
14415 OPTGROUP_NONE
, /* optinfo_flags */
14416 TV_COMBINE
, /* tv_id */
14417 PROP_cfglayout
, /* properties_required */
14418 0, /* properties_provided */
14419 0, /* properties_destroyed */
14420 0, /* todo_flags_start */
14421 TODO_df_finish
, /* todo_flags_finish */
14424 class pass_combine
: public rtl_opt_pass
14427 pass_combine (gcc::context
*ctxt
)
14428 : rtl_opt_pass (pass_data_combine
, ctxt
)
14431 /* opt_pass methods: */
14432 virtual bool gate (function
*) { return (optimize
> 0); }
14433 virtual unsigned int execute (function
*)
14435 return rest_of_handle_combine ();
14438 }; // class pass_combine
14440 } // anon namespace
14443 make_pass_combine (gcc::context
*ctxt
)
14445 return new pass_combine (ctxt
);