| blob | 166ec60f8ff2fa829f162ca0521e8a324b5ccd6f |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990-2012 Free Software Foundation, Inc.
3 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 3, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23 ;;
24 ;; REGNOS
25 ;;
27 (define_constants
28 [(STACK_POINTER_REGNUM 1)
29 (TOC_REGNUM 2)
30 (STATIC_CHAIN_REGNUM 11)
31 (HARD_FRAME_POINTER_REGNUM 31)
32 (MQ_REGNO 64)
33 (LR_REGNO 65)
34 (CTR_REGNO 66)
35 (ARG_POINTER_REGNUM 67)
36 (CR0_REGNO 68)
37 (CR1_REGNO 69)
38 (CR2_REGNO 70)
39 (CR3_REGNO 71)
40 (CR4_REGNO 72)
41 (CR5_REGNO 73)
42 (CR6_REGNO 74)
43 (CR7_REGNO 75)
44 (MAX_CR_REGNO 75)
45 (CA_REGNO 76)
46 (FIRST_ALTIVEC_REGNO 77)
47 (LAST_ALTIVEC_REGNO 108)
48 (VRSAVE_REGNO 109)
49 (VSCR_REGNO 110)
50 (SPE_ACC_REGNO 111)
51 (SPEFSCR_REGNO 112)
52 (FRAME_POINTER_REGNUM 113)
54 ; ABI defined stack offsets for storing the TOC pointer with AIX calls.
55 (TOC_SAVE_OFFSET_32BIT 20)
56 (TOC_SAVE_OFFSET_64BIT 40)
58 ; Function TOC offset in the AIX function descriptor.
59 (AIX_FUNC_DESC_TOC_32BIT 4)
60 (AIX_FUNC_DESC_TOC_64BIT 8)
62 ; Static chain offset in the AIX function descriptor.
63 (AIX_FUNC_DESC_SC_32BIT 8)
64 (AIX_FUNC_DESC_SC_64BIT 16)
65 ])
67 ;;
68 ;; UNSPEC usage
69 ;;
71 (define_c_enum "unspec"
72 [UNSPEC_FRSP ; frsp for POWER machines
73 UNSPEC_PROBE_STACK ; probe stack memory reference
74 UNSPEC_TOCPTR ; address of a word pointing to the TOC
75 UNSPEC_TOC ; address of the TOC (more-or-less)
76 UNSPEC_MOVSI_GOT
77 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit
78 UNSPEC_FCTIWZ
79 UNSPEC_FRIM
80 UNSPEC_FRIN
81 UNSPEC_FRIP
82 UNSPEC_FRIZ
83 UNSPEC_LD_MPIC ; load_macho_picbase
84 UNSPEC_MPIC_CORRECT ; macho_correct_pic
85 UNSPEC_TLSGD
86 UNSPEC_TLSLD
87 UNSPEC_MOVESI_FROM_CR
88 UNSPEC_MOVESI_TO_CR
89 UNSPEC_TLSDTPREL
90 UNSPEC_TLSDTPRELHA
91 UNSPEC_TLSDTPRELLO
92 UNSPEC_TLSGOTDTPREL
93 UNSPEC_TLSTPREL
94 UNSPEC_TLSTPRELHA
95 UNSPEC_TLSTPRELLO
96 UNSPEC_TLSGOTTPREL
97 UNSPEC_TLSTLS
98 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero
99 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit
100 UNSPEC_STFIWX
101 UNSPEC_POPCNTB
102 UNSPEC_FRES
103 UNSPEC_SP_SET
104 UNSPEC_SP_TEST
105 UNSPEC_SYNC
106 UNSPEC_LWSYNC
107 UNSPEC_SYNC_OP
108 UNSPEC_ATOMIC
109 UNSPEC_CMPXCHG
110 UNSPEC_XCHG
111 UNSPEC_AND
112 UNSPEC_DLMZB
113 UNSPEC_DLMZB_CR
114 UNSPEC_DLMZB_STRLEN
115 UNSPEC_RSQRT
116 UNSPEC_TOCREL
117 UNSPEC_MACHOPIC_OFFSET
118 UNSPEC_BPERM
119 UNSPEC_COPYSIGN
120 UNSPEC_PARITY
121 UNSPEC_FCTIW
122 UNSPEC_FCTID
123 UNSPEC_LFIWAX
124 UNSPEC_LFIWZX
125 UNSPEC_FCTIWUZ
126 UNSPEC_GRP_END_NOP
127 ])
129 ;;
130 ;; UNSPEC_VOLATILE usage
131 ;;
133 (define_c_enum "unspecv"
134 [UNSPECV_BLOCK
135 UNSPECV_LL ; load-locked
136 UNSPECV_SC ; store-conditional
137 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses
138 UNSPECV_EH_RR ; eh_reg_restore
139 UNSPECV_ISYNC ; isync instruction
140 ])
142 \f
143 ;; Define an insn type attribute. This is used in function unit delay
144 ;; computations.
145 (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt"
146 (const_string "integer"))
148 ;; Define floating point instruction sub-types for use with Xfpu.md
149 (define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default"))
151 ;; Length (in bytes).
152 ; '(pc)' in the following doesn't include the instruction itself; it is
153 ; calculated as if the instruction had zero size.
154 (define_attr "length" ""
155 (if_then_else (eq_attr "type" "branch")
156 (if_then_else (and (ge (minus (match_dup 0) (pc))
157 (const_int -32768))
158 (lt (minus (match_dup 0) (pc))
159 (const_int 32764)))
160 (const_int 4)
161 (const_int 8))
162 (const_int 4)))
164 ;; Processor type -- this attribute must exactly match the processor_type
165 ;; enumeration in rs6000.h.
167 (define_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,power4,power5,power6,power7,cell,ppca2,titan"
168 (const (symbol_ref "rs6000_cpu_attr")))
171 ;; If this instruction is microcoded on the CELL processor
172 ; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
173 (define_attr "cell_micro" "not,conditional,always"
174 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare")
175 (const_string "always")
176 (const_string "not")))
178 (automata_option "ndfa")
180 (include "rs64.md")
181 (include "mpc.md")
182 (include "40x.md")
183 (include "440.md")
184 (include "476.md")
185 (include "601.md")
186 (include "603.md")
187 (include "6xx.md")
188 (include "7xx.md")
189 (include "7450.md")
190 (include "8540.md")
191 (include "e300c2c3.md")
192 (include "e500mc.md")
193 (include "e500mc64.md")
194 (include "e5500.md")
195 (include "e6500.md")
196 (include "power4.md")
197 (include "power5.md")
198 (include "power6.md")
199 (include "power7.md")
200 (include "cell.md")
201 (include "xfpu.md")
202 (include "a2.md")
203 (include "titan.md")
205 (include "predicates.md")
206 (include "constraints.md")
208 (include "darwin.md")
210 \f
211 ;; Mode iterators
213 ; This mode iterator allows :GPR to be used to indicate the allowable size
214 ; of whole values in GPRs.
215 (define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")])
217 ; Any supported integer mode.
218 (define_mode_iterator INT [QI HI SI DI TI])
220 ; Any supported integer mode that fits in one register.
221 (define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")])
223 ; extend modes for DImode
224 (define_mode_iterator QHSI [QI HI SI])
226 ; SImode or DImode, even if DImode doesn't fit in GPRs.
227 (define_mode_iterator SDI [SI DI])
229 ; The size of a pointer. Also, the size of the value that a record-condition
230 ; (one with a '.') will compare; and the size used for arithmetic carries.
231 (define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
233 ; Any hardware-supported floating-point mode
234 (define_mode_iterator FP [
235 (SF "TARGET_HARD_FLOAT
236 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)")
237 (DF "TARGET_HARD_FLOAT
238 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)")
239 (TF "!TARGET_IEEEQUAD
240 && TARGET_HARD_FLOAT
241 && (TARGET_FPRS || TARGET_E500_DOUBLE)
242 && TARGET_LONG_DOUBLE_128")
243 (DD "TARGET_DFP")
244 (TD "TARGET_DFP")])
246 ; Any fma capable floating-point mode.
247 (define_mode_iterator FMA_F [
248 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT")
249 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT)
250 || VECTOR_UNIT_VSX_P (DFmode)")
251 (V2SF "TARGET_PAIRED_FLOAT")
252 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)")
253 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)")
254 ])
256 ; These modes do not fit in integer registers in 32-bit mode.
257 ; but on e500v2, the gpr are 64 bit registers
258 (define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD])
260 ; Iterator for reciprocal estimate instructions
261 (define_mode_iterator RECIPF [SF DF V4SF V2DF])
263 ; Iterator for just SF/DF
264 (define_mode_iterator SFDF [SF DF])
266 ; Conditional returns.
267 (define_code_iterator any_return [return simple_return])
268 (define_code_attr return_pred [(return "direct_return ()")
269 (simple_return "")])
270 (define_code_attr return_str [(return "") (simple_return "simple_")])
272 ; Various instructions that come in SI and DI forms.
273 ; A generic w/d attribute, for things like cmpw/cmpd.
274 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
276 ; DImode bits
277 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
279 ;; ISEL/ISEL64 target selection
280 (define_mode_attr sel [(SI "") (DI "64")])
282 ;; Suffix for reload patterns
283 (define_mode_attr ptrsize [(SI "32bit")
284 (DI "64bit")])
286 (define_mode_attr tptrsize [(SI "TARGET_32BIT")
287 (DI "TARGET_64BIT")])
289 (define_mode_attr mptrsize [(SI "si")
290 (DI "di")])
292 (define_mode_attr ptrload [(SI "{l|lwz}")
293 (DI "ld")])
295 (define_mode_attr rreg [(SF "f")
296 (DF "ws")
297 (V4SF "wf")
298 (V2DF "wd")])
300 (define_mode_attr rreg2 [(SF "f")
301 (DF "d")])
303 (define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS")
304 (DF "TARGET_FCFID")])
306 (define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS")
307 (DF "TARGET_E500_DOUBLE")])
309 (define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT")
310 (DF "TARGET_DOUBLE_FLOAT")])
311 \f
312 ;; Start with fixed-point load and store insns. Here we put only the more
313 ;; complex forms. Basic data transfer is done later.
315 (define_expand "zero_extend<mode>di2"
316 [(set (match_operand:DI 0 "gpc_reg_operand" "")
317 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))]
318 "TARGET_POWERPC64"
319 "")
321 (define_insn "*zero_extend<mode>di2_internal1"
322 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
323 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))]
324 "TARGET_POWERPC64"
325 "@
326 l<wd>z%U1%X1 %0,%1
327 rldicl %0,%1,0,<dbits>"
328 [(set_attr "type" "load,*")])
330 (define_insn "*zero_extend<mode>di2_internal2"
331 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
332 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
333 (const_int 0)))
334 (clobber (match_scratch:DI 2 "=r,r"))]
335 "TARGET_64BIT"
336 "@
337 rldicl. %2,%1,0,<dbits>
338 #"
339 [(set_attr "type" "compare")
340 (set_attr "length" "4,8")])
342 (define_split
343 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
344 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
345 (const_int 0)))
346 (clobber (match_scratch:DI 2 ""))]
347 "TARGET_POWERPC64 && reload_completed"
348 [(set (match_dup 2)
349 (zero_extend:DI (match_dup 1)))
350 (set (match_dup 0)
351 (compare:CC (match_dup 2)
352 (const_int 0)))]
353 "")
355 (define_insn "*zero_extend<mode>di2_internal3"
356 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
357 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r"))
358 (const_int 0)))
359 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
360 (zero_extend:DI (match_dup 1)))]
361 "TARGET_64BIT"
362 "@
363 rldicl. %0,%1,0,<dbits>
364 #"
365 [(set_attr "type" "compare")
366 (set_attr "length" "4,8")])
368 (define_split
369 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
370 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" ""))
371 (const_int 0)))
372 (set (match_operand:DI 0 "gpc_reg_operand" "")
373 (zero_extend:DI (match_dup 1)))]
374 "TARGET_POWERPC64 && reload_completed"
375 [(set (match_dup 0)
376 (zero_extend:DI (match_dup 1)))
377 (set (match_dup 2)
378 (compare:CC (match_dup 0)
379 (const_int 0)))]
380 "")
382 (define_insn "extendqidi2"
383 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
384 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
385 "TARGET_POWERPC64"
386 "extsb %0,%1"
387 [(set_attr "type" "exts")])
389 (define_insn ""
390 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
391 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
392 (const_int 0)))
393 (clobber (match_scratch:DI 2 "=r,r"))]
394 "TARGET_64BIT"
395 "@
396 extsb. %2,%1
397 #"
398 [(set_attr "type" "compare")
399 (set_attr "length" "4,8")])
401 (define_split
402 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
403 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
404 (const_int 0)))
405 (clobber (match_scratch:DI 2 ""))]
406 "TARGET_POWERPC64 && reload_completed"
407 [(set (match_dup 2)
408 (sign_extend:DI (match_dup 1)))
409 (set (match_dup 0)
410 (compare:CC (match_dup 2)
411 (const_int 0)))]
412 "")
414 (define_insn ""
415 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
416 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
417 (const_int 0)))
418 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
419 (sign_extend:DI (match_dup 1)))]
420 "TARGET_64BIT"
421 "@
422 extsb. %0,%1
423 #"
424 [(set_attr "type" "compare")
425 (set_attr "length" "4,8")])
427 (define_split
428 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
429 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
430 (const_int 0)))
431 (set (match_operand:DI 0 "gpc_reg_operand" "")
432 (sign_extend:DI (match_dup 1)))]
433 "TARGET_POWERPC64 && reload_completed"
434 [(set (match_dup 0)
435 (sign_extend:DI (match_dup 1)))
436 (set (match_dup 2)
437 (compare:CC (match_dup 0)
438 (const_int 0)))]
439 "")
441 (define_expand "extendhidi2"
442 [(set (match_operand:DI 0 "gpc_reg_operand" "")
443 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
444 "TARGET_POWERPC64"
445 "")
447 (define_insn ""
448 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
449 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
450 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
451 "@
452 lha%U1%X1 %0,%1
453 extsh %0,%1"
454 [(set_attr "type" "load_ext,exts")])
456 (define_insn ""
457 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
458 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))]
459 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
460 "extsh %0,%1"
461 [(set_attr "type" "exts")])
463 (define_insn ""
464 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
465 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
466 (const_int 0)))
467 (clobber (match_scratch:DI 2 "=r,r"))]
468 "TARGET_64BIT"
469 "@
470 extsh. %2,%1
471 #"
472 [(set_attr "type" "compare")
473 (set_attr "length" "4,8")])
475 (define_split
476 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
477 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
478 (const_int 0)))
479 (clobber (match_scratch:DI 2 ""))]
480 "TARGET_POWERPC64 && reload_completed"
481 [(set (match_dup 2)
482 (sign_extend:DI (match_dup 1)))
483 (set (match_dup 0)
484 (compare:CC (match_dup 2)
485 (const_int 0)))]
486 "")
488 (define_insn ""
489 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
490 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
491 (const_int 0)))
492 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
493 (sign_extend:DI (match_dup 1)))]
494 "TARGET_64BIT"
495 "@
496 extsh. %0,%1
497 #"
498 [(set_attr "type" "compare")
499 (set_attr "length" "4,8")])
501 (define_split
502 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
503 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
504 (const_int 0)))
505 (set (match_operand:DI 0 "gpc_reg_operand" "")
506 (sign_extend:DI (match_dup 1)))]
507 "TARGET_POWERPC64 && reload_completed"
508 [(set (match_dup 0)
509 (sign_extend:DI (match_dup 1)))
510 (set (match_dup 2)
511 (compare:CC (match_dup 0)
512 (const_int 0)))]
513 "")
515 (define_expand "extendsidi2"
516 [(set (match_operand:DI 0 "gpc_reg_operand" "")
517 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
518 "TARGET_POWERPC64"
519 "")
521 (define_insn ""
522 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
523 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
524 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
525 "@
526 lwa%U1%X1 %0,%1
527 extsw %0,%1"
528 [(set_attr "type" "load_ext,exts")])
530 (define_insn ""
531 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
532 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))]
533 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
534 "extsw %0,%1"
535 [(set_attr "type" "exts")])
537 (define_insn ""
538 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
539 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
540 (const_int 0)))
541 (clobber (match_scratch:DI 2 "=r,r"))]
542 "TARGET_64BIT"
543 "@
544 extsw. %2,%1
545 #"
546 [(set_attr "type" "compare")
547 (set_attr "length" "4,8")])
549 (define_split
550 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
551 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
552 (const_int 0)))
553 (clobber (match_scratch:DI 2 ""))]
554 "TARGET_POWERPC64 && reload_completed"
555 [(set (match_dup 2)
556 (sign_extend:DI (match_dup 1)))
557 (set (match_dup 0)
558 (compare:CC (match_dup 2)
559 (const_int 0)))]
560 "")
562 (define_insn ""
563 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
564 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
565 (const_int 0)))
566 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
567 (sign_extend:DI (match_dup 1)))]
568 "TARGET_64BIT"
569 "@
570 extsw. %0,%1
571 #"
572 [(set_attr "type" "compare")
573 (set_attr "length" "4,8")])
575 (define_split
576 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
577 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
578 (const_int 0)))
579 (set (match_operand:DI 0 "gpc_reg_operand" "")
580 (sign_extend:DI (match_dup 1)))]
581 "TARGET_POWERPC64 && reload_completed"
582 [(set (match_dup 0)
583 (sign_extend:DI (match_dup 1)))
584 (set (match_dup 2)
585 (compare:CC (match_dup 0)
586 (const_int 0)))]
587 "")
589 (define_expand "zero_extendqisi2"
590 [(set (match_operand:SI 0 "gpc_reg_operand" "")
591 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
592 ""
593 "")
595 (define_insn ""
596 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
597 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
598 ""
599 "@
600 lbz%U1%X1 %0,%1
601 {rlinm|rlwinm} %0,%1,0,0xff"
602 [(set_attr "type" "load,*")])
604 (define_insn ""
605 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
606 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
607 (const_int 0)))
608 (clobber (match_scratch:SI 2 "=r,r"))]
609 ""
610 "@
611 {andil.|andi.} %2,%1,0xff
612 #"
613 [(set_attr "type" "fast_compare,compare")
614 (set_attr "length" "4,8")])
616 (define_split
617 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
618 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
619 (const_int 0)))
620 (clobber (match_scratch:SI 2 ""))]
621 "reload_completed"
622 [(set (match_dup 2)
623 (zero_extend:SI (match_dup 1)))
624 (set (match_dup 0)
625 (compare:CC (match_dup 2)
626 (const_int 0)))]
627 "")
629 (define_insn ""
630 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
631 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
632 (const_int 0)))
633 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
634 (zero_extend:SI (match_dup 1)))]
635 ""
636 "@
637 {andil.|andi.} %0,%1,0xff
638 #"
639 [(set_attr "type" "fast_compare,compare")
640 (set_attr "length" "4,8")])
642 (define_split
643 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
644 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
645 (const_int 0)))
646 (set (match_operand:SI 0 "gpc_reg_operand" "")
647 (zero_extend:SI (match_dup 1)))]
648 "reload_completed"
649 [(set (match_dup 0)
650 (zero_extend:SI (match_dup 1)))
651 (set (match_dup 2)
652 (compare:CC (match_dup 0)
653 (const_int 0)))]
654 "")
656 (define_expand "extendqisi2"
657 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
658 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
659 ""
660 "
661 {
662 if (TARGET_POWERPC)
663 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
664 else
665 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
666 DONE;
667 }")
669 (define_insn "extendqisi2_ppc"
670 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
671 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
672 "TARGET_POWERPC"
673 "extsb %0,%1"
674 [(set_attr "type" "exts")])
676 (define_insn ""
677 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
678 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
679 (const_int 0)))
680 (clobber (match_scratch:SI 2 "=r,r"))]
681 "TARGET_POWERPC"
682 "@
683 extsb. %2,%1
684 #"
685 [(set_attr "type" "compare")
686 (set_attr "length" "4,8")])
688 (define_split
689 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
690 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
691 (const_int 0)))
692 (clobber (match_scratch:SI 2 ""))]
693 "TARGET_POWERPC && reload_completed"
694 [(set (match_dup 2)
695 (sign_extend:SI (match_dup 1)))
696 (set (match_dup 0)
697 (compare:CC (match_dup 2)
698 (const_int 0)))]
699 "")
701 (define_insn ""
702 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
703 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
704 (const_int 0)))
705 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
706 (sign_extend:SI (match_dup 1)))]
707 "TARGET_POWERPC"
708 "@
709 extsb. %0,%1
710 #"
711 [(set_attr "type" "compare")
712 (set_attr "length" "4,8")])
714 (define_split
715 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
716 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
717 (const_int 0)))
718 (set (match_operand:SI 0 "gpc_reg_operand" "")
719 (sign_extend:SI (match_dup 1)))]
720 "TARGET_POWERPC && reload_completed"
721 [(set (match_dup 0)
722 (sign_extend:SI (match_dup 1)))
723 (set (match_dup 2)
724 (compare:CC (match_dup 0)
725 (const_int 0)))]
726 "")
728 (define_expand "extendqisi2_no_power"
729 [(set (match_dup 2)
730 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
731 (const_int 24)))
732 (set (match_operand:SI 0 "gpc_reg_operand" "")
733 (ashiftrt:SI (match_dup 2)
734 (const_int 24)))]
735 "! TARGET_POWERPC"
736 "
737 { operands[1] = gen_lowpart (SImode, operands[1]);
738 operands[2] = gen_reg_rtx (SImode); }")
740 (define_expand "zero_extendqihi2"
741 [(set (match_operand:HI 0 "gpc_reg_operand" "")
742 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
743 ""
744 "")
746 (define_insn ""
747 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
748 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
749 ""
750 "@
751 lbz%U1%X1 %0,%1
752 {rlinm|rlwinm} %0,%1,0,0xff"
753 [(set_attr "type" "load,*")])
755 (define_insn ""
756 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
757 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
758 (const_int 0)))
759 (clobber (match_scratch:HI 2 "=r,r"))]
760 ""
761 "@
762 {andil.|andi.} %2,%1,0xff
763 #"
764 [(set_attr "type" "fast_compare,compare")
765 (set_attr "length" "4,8")])
767 (define_split
768 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
769 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
770 (const_int 0)))
771 (clobber (match_scratch:HI 2 ""))]
772 "reload_completed"
773 [(set (match_dup 2)
774 (zero_extend:HI (match_dup 1)))
775 (set (match_dup 0)
776 (compare:CC (match_dup 2)
777 (const_int 0)))]
778 "")
780 (define_insn ""
781 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
782 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
783 (const_int 0)))
784 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
785 (zero_extend:HI (match_dup 1)))]
786 ""
787 "@
788 {andil.|andi.} %0,%1,0xff
789 #"
790 [(set_attr "type" "fast_compare,compare")
791 (set_attr "length" "4,8")])
793 (define_split
794 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
795 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
796 (const_int 0)))
797 (set (match_operand:HI 0 "gpc_reg_operand" "")
798 (zero_extend:HI (match_dup 1)))]
799 "reload_completed"
800 [(set (match_dup 0)
801 (zero_extend:HI (match_dup 1)))
802 (set (match_dup 2)
803 (compare:CC (match_dup 0)
804 (const_int 0)))]
805 "")
807 (define_expand "extendqihi2"
808 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
809 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
810 ""
811 "
812 {
813 if (TARGET_POWERPC)
814 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
815 else
816 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
817 DONE;
818 }")
820 (define_insn "extendqihi2_ppc"
821 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
822 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
823 "TARGET_POWERPC"
824 "extsb %0,%1"
825 [(set_attr "type" "exts")])
827 (define_insn ""
828 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
829 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
830 (const_int 0)))
831 (clobber (match_scratch:HI 2 "=r,r"))]
832 "TARGET_POWERPC"
833 "@
834 extsb. %2,%1
835 #"
836 [(set_attr "type" "compare")
837 (set_attr "length" "4,8")])
839 (define_split
840 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
841 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
842 (const_int 0)))
843 (clobber (match_scratch:HI 2 ""))]
844 "TARGET_POWERPC && reload_completed"
845 [(set (match_dup 2)
846 (sign_extend:HI (match_dup 1)))
847 (set (match_dup 0)
848 (compare:CC (match_dup 2)
849 (const_int 0)))]
850 "")
852 (define_insn ""
853 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
854 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
855 (const_int 0)))
856 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
857 (sign_extend:HI (match_dup 1)))]
858 "TARGET_POWERPC"
859 "@
860 extsb. %0,%1
861 #"
862 [(set_attr "type" "compare")
863 (set_attr "length" "4,8")])
865 (define_split
866 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
867 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
868 (const_int 0)))
869 (set (match_operand:HI 0 "gpc_reg_operand" "")
870 (sign_extend:HI (match_dup 1)))]
871 "TARGET_POWERPC && reload_completed"
872 [(set (match_dup 0)
873 (sign_extend:HI (match_dup 1)))
874 (set (match_dup 2)
875 (compare:CC (match_dup 0)
876 (const_int 0)))]
877 "")
879 (define_expand "extendqihi2_no_power"
880 [(set (match_dup 2)
881 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
882 (const_int 24)))
883 (set (match_operand:HI 0 "gpc_reg_operand" "")
884 (ashiftrt:SI (match_dup 2)
885 (const_int 24)))]
886 "! TARGET_POWERPC"
887 "
888 { operands[0] = gen_lowpart (SImode, operands[0]);
889 operands[1] = gen_lowpart (SImode, operands[1]);
890 operands[2] = gen_reg_rtx (SImode); }")
892 (define_expand "zero_extendhisi2"
893 [(set (match_operand:SI 0 "gpc_reg_operand" "")
894 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
895 ""
896 "")
898 (define_insn ""
899 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
900 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
901 ""
902 "@
903 lhz%U1%X1 %0,%1
904 {rlinm|rlwinm} %0,%1,0,0xffff"
905 [(set_attr "type" "load,*")])
907 (define_insn ""
908 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
909 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
910 (const_int 0)))
911 (clobber (match_scratch:SI 2 "=r,r"))]
912 ""
913 "@
914 {andil.|andi.} %2,%1,0xffff
915 #"
916 [(set_attr "type" "fast_compare,compare")
917 (set_attr "length" "4,8")])
919 (define_split
920 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
921 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
922 (const_int 0)))
923 (clobber (match_scratch:SI 2 ""))]
924 "reload_completed"
925 [(set (match_dup 2)
926 (zero_extend:SI (match_dup 1)))
927 (set (match_dup 0)
928 (compare:CC (match_dup 2)
929 (const_int 0)))]
930 "")
932 (define_insn ""
933 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
934 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
935 (const_int 0)))
936 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
937 (zero_extend:SI (match_dup 1)))]
938 ""
939 "@
940 {andil.|andi.} %0,%1,0xffff
941 #"
942 [(set_attr "type" "fast_compare,compare")
943 (set_attr "length" "4,8")])
945 (define_split
946 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
947 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
948 (const_int 0)))
949 (set (match_operand:SI 0 "gpc_reg_operand" "")
950 (zero_extend:SI (match_dup 1)))]
951 "reload_completed"
952 [(set (match_dup 0)
953 (zero_extend:SI (match_dup 1)))
954 (set (match_dup 2)
955 (compare:CC (match_dup 0)
956 (const_int 0)))]
957 "")
959 (define_expand "extendhisi2"
960 [(set (match_operand:SI 0 "gpc_reg_operand" "")
961 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
962 ""
963 "")
965 (define_insn ""
966 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
967 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
968 "rs6000_gen_cell_microcode"
969 "@
970 lha%U1%X1 %0,%1
971 {exts|extsh} %0,%1"
972 [(set_attr "type" "load_ext,exts")])
974 (define_insn ""
975 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
976 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))]
977 "!rs6000_gen_cell_microcode"
978 "{exts|extsh} %0,%1"
979 [(set_attr "type" "exts")])
981 (define_insn ""
982 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
983 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
984 (const_int 0)))
985 (clobber (match_scratch:SI 2 "=r,r"))]
986 ""
987 "@
988 {exts.|extsh.} %2,%1
989 #"
990 [(set_attr "type" "compare")
991 (set_attr "length" "4,8")])
993 (define_split
994 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
995 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
996 (const_int 0)))
997 (clobber (match_scratch:SI 2 ""))]
998 "reload_completed"
999 [(set (match_dup 2)
1000 (sign_extend:SI (match_dup 1)))
1001 (set (match_dup 0)
1002 (compare:CC (match_dup 2)
1003 (const_int 0)))]
1004 "")
1006 (define_insn ""
1007 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1008 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1009 (const_int 0)))
1010 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1011 (sign_extend:SI (match_dup 1)))]
1012 ""
1013 "@
1014 {exts.|extsh.} %0,%1
1015 #"
1016 [(set_attr "type" "compare")
1017 (set_attr "length" "4,8")])
1018 \f
1019 ;; IBM 405, 440, 464 and 476 half-word multiplication operations.
1021 (define_insn "*macchwc"
1022 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1023 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1024 (match_operand:SI 2 "gpc_reg_operand" "r")
1025 (const_int 16))
1026 (sign_extend:SI
1027 (match_operand:HI 1 "gpc_reg_operand" "r")))
1028 (match_operand:SI 4 "gpc_reg_operand" "0"))
1029 (const_int 0)))
1030 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1031 (plus:SI (mult:SI (ashiftrt:SI
1032 (match_dup 2)
1033 (const_int 16))
1034 (sign_extend:SI
1035 (match_dup 1)))
1036 (match_dup 4)))]
1037 "TARGET_MULHW"
1038 "macchw. %0, %1, %2"
1039 [(set_attr "type" "imul3")])
1041 (define_insn "*macchw"
1042 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1043 (plus:SI (mult:SI (ashiftrt:SI
1044 (match_operand:SI 2 "gpc_reg_operand" "r")
1045 (const_int 16))
1046 (sign_extend:SI
1047 (match_operand:HI 1 "gpc_reg_operand" "r")))
1048 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1049 "TARGET_MULHW"
1050 "macchw %0, %1, %2"
1051 [(set_attr "type" "imul3")])
1053 (define_insn "*macchwuc"
1054 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1055 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1056 (match_operand:SI 2 "gpc_reg_operand" "r")
1057 (const_int 16))
1058 (zero_extend:SI
1059 (match_operand:HI 1 "gpc_reg_operand" "r")))
1060 (match_operand:SI 4 "gpc_reg_operand" "0"))
1061 (const_int 0)))
1062 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1063 (plus:SI (mult:SI (lshiftrt:SI
1064 (match_dup 2)
1065 (const_int 16))
1066 (zero_extend:SI
1067 (match_dup 1)))
1068 (match_dup 4)))]
1069 "TARGET_MULHW"
1070 "macchwu. %0, %1, %2"
1071 [(set_attr "type" "imul3")])
1073 (define_insn "*macchwu"
1074 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1075 (plus:SI (mult:SI (lshiftrt:SI
1076 (match_operand:SI 2 "gpc_reg_operand" "r")
1077 (const_int 16))
1078 (zero_extend:SI
1079 (match_operand:HI 1 "gpc_reg_operand" "r")))
1080 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1081 "TARGET_MULHW"
1082 "macchwu %0, %1, %2"
1083 [(set_attr "type" "imul3")])
1085 (define_insn "*machhwc"
1086 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1087 (compare:CC (plus:SI (mult:SI (ashiftrt:SI
1088 (match_operand:SI 1 "gpc_reg_operand" "%r")
1089 (const_int 16))
1090 (ashiftrt:SI
1091 (match_operand:SI 2 "gpc_reg_operand" "r")
1092 (const_int 16)))
1093 (match_operand:SI 4 "gpc_reg_operand" "0"))
1094 (const_int 0)))
1095 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1096 (plus:SI (mult:SI (ashiftrt:SI
1097 (match_dup 1)
1098 (const_int 16))
1099 (ashiftrt:SI
1100 (match_dup 2)
1101 (const_int 16)))
1102 (match_dup 4)))]
1103 "TARGET_MULHW"
1104 "machhw. %0, %1, %2"
1105 [(set_attr "type" "imul3")])
1107 (define_insn "*machhw"
1108 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1109 (plus:SI (mult:SI (ashiftrt:SI
1110 (match_operand:SI 1 "gpc_reg_operand" "%r")
1111 (const_int 16))
1112 (ashiftrt:SI
1113 (match_operand:SI 2 "gpc_reg_operand" "r")
1114 (const_int 16)))
1115 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1116 "TARGET_MULHW"
1117 "machhw %0, %1, %2"
1118 [(set_attr "type" "imul3")])
1120 (define_insn "*machhwuc"
1121 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1122 (compare:CC (plus:SI (mult:SI (lshiftrt:SI
1123 (match_operand:SI 1 "gpc_reg_operand" "%r")
1124 (const_int 16))
1125 (lshiftrt:SI
1126 (match_operand:SI 2 "gpc_reg_operand" "r")
1127 (const_int 16)))
1128 (match_operand:SI 4 "gpc_reg_operand" "0"))
1129 (const_int 0)))
1130 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1131 (plus:SI (mult:SI (lshiftrt:SI
1132 (match_dup 1)
1133 (const_int 16))
1134 (lshiftrt:SI
1135 (match_dup 2)
1136 (const_int 16)))
1137 (match_dup 4)))]
1138 "TARGET_MULHW"
1139 "machhwu. %0, %1, %2"
1140 [(set_attr "type" "imul3")])
1142 (define_insn "*machhwu"
1143 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1144 (plus:SI (mult:SI (lshiftrt:SI
1145 (match_operand:SI 1 "gpc_reg_operand" "%r")
1146 (const_int 16))
1147 (lshiftrt:SI
1148 (match_operand:SI 2 "gpc_reg_operand" "r")
1149 (const_int 16)))
1150 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1151 "TARGET_MULHW"
1152 "machhwu %0, %1, %2"
1153 [(set_attr "type" "imul3")])
1155 (define_insn "*maclhwc"
1156 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1157 (compare:CC (plus:SI (mult:SI (sign_extend:SI
1158 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1159 (sign_extend:SI
1160 (match_operand:HI 2 "gpc_reg_operand" "r")))
1161 (match_operand:SI 4 "gpc_reg_operand" "0"))
1162 (const_int 0)))
1163 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1164 (plus:SI (mult:SI (sign_extend:SI
1165 (match_dup 1))
1166 (sign_extend:SI
1167 (match_dup 2)))
1168 (match_dup 4)))]
1169 "TARGET_MULHW"
1170 "maclhw. %0, %1, %2"
1171 [(set_attr "type" "imul3")])
1173 (define_insn "*maclhw"
1174 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1175 (plus:SI (mult:SI (sign_extend:SI
1176 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1177 (sign_extend:SI
1178 (match_operand:HI 2 "gpc_reg_operand" "r")))
1179 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1180 "TARGET_MULHW"
1181 "maclhw %0, %1, %2"
1182 [(set_attr "type" "imul3")])
1184 (define_insn "*maclhwuc"
1185 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1186 (compare:CC (plus:SI (mult:SI (zero_extend:SI
1187 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1188 (zero_extend:SI
1189 (match_operand:HI 2 "gpc_reg_operand" "r")))
1190 (match_operand:SI 4 "gpc_reg_operand" "0"))
1191 (const_int 0)))
1192 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1193 (plus:SI (mult:SI (zero_extend:SI
1194 (match_dup 1))
1195 (zero_extend:SI
1196 (match_dup 2)))
1197 (match_dup 4)))]
1198 "TARGET_MULHW"
1199 "maclhwu. %0, %1, %2"
1200 [(set_attr "type" "imul3")])
1202 (define_insn "*maclhwu"
1203 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1204 (plus:SI (mult:SI (zero_extend:SI
1205 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1206 (zero_extend:SI
1207 (match_operand:HI 2 "gpc_reg_operand" "r")))
1208 (match_operand:SI 3 "gpc_reg_operand" "0")))]
1209 "TARGET_MULHW"
1210 "maclhwu %0, %1, %2"
1211 [(set_attr "type" "imul3")])
1213 (define_insn "*nmacchwc"
1214 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1215 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1216 (mult:SI (ashiftrt:SI
1217 (match_operand:SI 2 "gpc_reg_operand" "r")
1218 (const_int 16))
1219 (sign_extend:SI
1220 (match_operand:HI 1 "gpc_reg_operand" "r"))))
1221 (const_int 0)))
1222 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1223 (minus:SI (match_dup 4)
1224 (mult:SI (ashiftrt:SI
1225 (match_dup 2)
1226 (const_int 16))
1227 (sign_extend:SI
1228 (match_dup 1)))))]
1229 "TARGET_MULHW"
1230 "nmacchw. %0, %1, %2"
1231 [(set_attr "type" "imul3")])
1233 (define_insn "*nmacchw"
1234 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1235 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1236 (mult:SI (ashiftrt:SI
1237 (match_operand:SI 2 "gpc_reg_operand" "r")
1238 (const_int 16))
1239 (sign_extend:SI
1240 (match_operand:HI 1 "gpc_reg_operand" "r")))))]
1241 "TARGET_MULHW"
1242 "nmacchw %0, %1, %2"
1243 [(set_attr "type" "imul3")])
1245 (define_insn "*nmachhwc"
1246 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1247 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1248 (mult:SI (ashiftrt:SI
1249 (match_operand:SI 1 "gpc_reg_operand" "%r")
1250 (const_int 16))
1251 (ashiftrt:SI
1252 (match_operand:SI 2 "gpc_reg_operand" "r")
1253 (const_int 16))))
1254 (const_int 0)))
1255 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1256 (minus:SI (match_dup 4)
1257 (mult:SI (ashiftrt:SI
1258 (match_dup 1)
1259 (const_int 16))
1260 (ashiftrt:SI
1261 (match_dup 2)
1262 (const_int 16)))))]
1263 "TARGET_MULHW"
1264 "nmachhw. %0, %1, %2"
1265 [(set_attr "type" "imul3")])
1267 (define_insn "*nmachhw"
1268 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1269 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1270 (mult:SI (ashiftrt:SI
1271 (match_operand:SI 1 "gpc_reg_operand" "%r")
1272 (const_int 16))
1273 (ashiftrt:SI
1274 (match_operand:SI 2 "gpc_reg_operand" "r")
1275 (const_int 16)))))]
1276 "TARGET_MULHW"
1277 "nmachhw %0, %1, %2"
1278 [(set_attr "type" "imul3")])
1280 (define_insn "*nmaclhwc"
1281 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1282 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0")
1283 (mult:SI (sign_extend:SI
1284 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1285 (sign_extend:SI
1286 (match_operand:HI 2 "gpc_reg_operand" "r"))))
1287 (const_int 0)))
1288 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1289 (minus:SI (match_dup 4)
1290 (mult:SI (sign_extend:SI
1291 (match_dup 1))
1292 (sign_extend:SI
1293 (match_dup 2)))))]
1294 "TARGET_MULHW"
1295 "nmaclhw. %0, %1, %2"
1296 [(set_attr "type" "imul3")])
1298 (define_insn "*nmaclhw"
1299 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1300 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0")
1301 (mult:SI (sign_extend:SI
1302 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1303 (sign_extend:SI
1304 (match_operand:HI 2 "gpc_reg_operand" "r")))))]
1305 "TARGET_MULHW"
1306 "nmaclhw %0, %1, %2"
1307 [(set_attr "type" "imul3")])
1309 (define_insn "*mulchwc"
1310 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1311 (compare:CC (mult:SI (ashiftrt:SI
1312 (match_operand:SI 2 "gpc_reg_operand" "r")
1313 (const_int 16))
1314 (sign_extend:SI
1315 (match_operand:HI 1 "gpc_reg_operand" "r")))
1316 (const_int 0)))
1317 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1318 (mult:SI (ashiftrt:SI
1319 (match_dup 2)
1320 (const_int 16))
1321 (sign_extend:SI
1322 (match_dup 1))))]
1323 "TARGET_MULHW"
1324 "mulchw. %0, %1, %2"
1325 [(set_attr "type" "imul3")])
1327 (define_insn "*mulchw"
1328 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1329 (mult:SI (ashiftrt:SI
1330 (match_operand:SI 2 "gpc_reg_operand" "r")
1331 (const_int 16))
1332 (sign_extend:SI
1333 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1334 "TARGET_MULHW"
1335 "mulchw %0, %1, %2"
1336 [(set_attr "type" "imul3")])
1338 (define_insn "*mulchwuc"
1339 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1340 (compare:CC (mult:SI (lshiftrt:SI
1341 (match_operand:SI 2 "gpc_reg_operand" "r")
1342 (const_int 16))
1343 (zero_extend:SI
1344 (match_operand:HI 1 "gpc_reg_operand" "r")))
1345 (const_int 0)))
1346 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1347 (mult:SI (lshiftrt:SI
1348 (match_dup 2)
1349 (const_int 16))
1350 (zero_extend:SI
1351 (match_dup 1))))]
1352 "TARGET_MULHW"
1353 "mulchwu. %0, %1, %2"
1354 [(set_attr "type" "imul3")])
1356 (define_insn "*mulchwu"
1357 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1358 (mult:SI (lshiftrt:SI
1359 (match_operand:SI 2 "gpc_reg_operand" "r")
1360 (const_int 16))
1361 (zero_extend:SI
1362 (match_operand:HI 1 "gpc_reg_operand" "r"))))]
1363 "TARGET_MULHW"
1364 "mulchwu %0, %1, %2"
1365 [(set_attr "type" "imul3")])
1367 (define_insn "*mulhhwc"
1368 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1369 (compare:CC (mult:SI (ashiftrt:SI
1370 (match_operand:SI 1 "gpc_reg_operand" "%r")
1371 (const_int 16))
1372 (ashiftrt:SI
1373 (match_operand:SI 2 "gpc_reg_operand" "r")
1374 (const_int 16)))
1375 (const_int 0)))
1376 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1377 (mult:SI (ashiftrt:SI
1378 (match_dup 1)
1379 (const_int 16))
1380 (ashiftrt:SI
1381 (match_dup 2)
1382 (const_int 16))))]
1383 "TARGET_MULHW"
1384 "mulhhw. %0, %1, %2"
1385 [(set_attr "type" "imul3")])
1387 (define_insn "*mulhhw"
1388 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1389 (mult:SI (ashiftrt:SI
1390 (match_operand:SI 1 "gpc_reg_operand" "%r")
1391 (const_int 16))
1392 (ashiftrt:SI
1393 (match_operand:SI 2 "gpc_reg_operand" "r")
1394 (const_int 16))))]
1395 "TARGET_MULHW"
1396 "mulhhw %0, %1, %2"
1397 [(set_attr "type" "imul3")])
1399 (define_insn "*mulhhwuc"
1400 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1401 (compare:CC (mult:SI (lshiftrt:SI
1402 (match_operand:SI 1 "gpc_reg_operand" "%r")
1403 (const_int 16))
1404 (lshiftrt:SI
1405 (match_operand:SI 2 "gpc_reg_operand" "r")
1406 (const_int 16)))
1407 (const_int 0)))
1408 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1409 (mult:SI (lshiftrt:SI
1410 (match_dup 1)
1411 (const_int 16))
1412 (lshiftrt:SI
1413 (match_dup 2)
1414 (const_int 16))))]
1415 "TARGET_MULHW"
1416 "mulhhwu. %0, %1, %2"
1417 [(set_attr "type" "imul3")])
1419 (define_insn "*mulhhwu"
1420 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1421 (mult:SI (lshiftrt:SI
1422 (match_operand:SI 1 "gpc_reg_operand" "%r")
1423 (const_int 16))
1424 (lshiftrt:SI
1425 (match_operand:SI 2 "gpc_reg_operand" "r")
1426 (const_int 16))))]
1427 "TARGET_MULHW"
1428 "mulhhwu %0, %1, %2"
1429 [(set_attr "type" "imul3")])
1431 (define_insn "*mullhwc"
1432 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1433 (compare:CC (mult:SI (sign_extend:SI
1434 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1435 (sign_extend:SI
1436 (match_operand:HI 2 "gpc_reg_operand" "r")))
1437 (const_int 0)))
1438 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1439 (mult:SI (sign_extend:SI
1440 (match_dup 1))
1441 (sign_extend:SI
1442 (match_dup 2))))]
1443 "TARGET_MULHW"
1444 "mullhw. %0, %1, %2"
1445 [(set_attr "type" "imul3")])
1447 (define_insn "*mullhw"
1448 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1449 (mult:SI (sign_extend:SI
1450 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1451 (sign_extend:SI
1452 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1453 "TARGET_MULHW"
1454 "mullhw %0, %1, %2"
1455 [(set_attr "type" "imul3")])
1457 (define_insn "*mullhwuc"
1458 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1459 (compare:CC (mult:SI (zero_extend:SI
1460 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1461 (zero_extend:SI
1462 (match_operand:HI 2 "gpc_reg_operand" "r")))
1463 (const_int 0)))
1464 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1465 (mult:SI (zero_extend:SI
1466 (match_dup 1))
1467 (zero_extend:SI
1468 (match_dup 2))))]
1469 "TARGET_MULHW"
1470 "mullhwu. %0, %1, %2"
1471 [(set_attr "type" "imul3")])
1473 (define_insn "*mullhwu"
1474 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1475 (mult:SI (zero_extend:SI
1476 (match_operand:HI 1 "gpc_reg_operand" "%r"))
1477 (zero_extend:SI
1478 (match_operand:HI 2 "gpc_reg_operand" "r"))))]
1479 "TARGET_MULHW"
1480 "mullhwu %0, %1, %2"
1481 [(set_attr "type" "imul3")])
1482 \f
1483 ;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support.
1484 (define_insn "dlmzb"
1485 [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1486 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
1487 (match_operand:SI 2 "gpc_reg_operand" "r")]
1488 UNSPEC_DLMZB_CR))
1489 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
1490 (unspec:SI [(match_dup 1)
1491 (match_dup 2)]
1492 UNSPEC_DLMZB))]
1493 "TARGET_DLMZB"
1494 "dlmzb. %0, %1, %2")
1496 (define_expand "strlensi"
1497 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1498 (unspec:SI [(match_operand:BLK 1 "general_operand" "")
1499 (match_operand:QI 2 "const_int_operand" "")
1500 (match_operand 3 "const_int_operand" "")]
1501 UNSPEC_DLMZB_STRLEN))
1502 (clobber (match_scratch:CC 4 "=x"))]
1503 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size"
1504 {
1505 rtx result = operands[0];
1506 rtx src = operands[1];
1507 rtx search_char = operands[2];
1508 rtx align = operands[3];
1509 rtx addr, scratch_string, word1, word2, scratch_dlmzb;
1510 rtx loop_label, end_label, mem, cr0, cond;
1511 if (search_char != const0_rtx
1512 || GET_CODE (align) != CONST_INT
1513 || INTVAL (align) < 8)
1514 FAIL;
1515 word1 = gen_reg_rtx (SImode);
1516 word2 = gen_reg_rtx (SImode);
1517 scratch_dlmzb = gen_reg_rtx (SImode);
1518 scratch_string = gen_reg_rtx (Pmode);
1519 loop_label = gen_label_rtx ();
1520 end_label = gen_label_rtx ();
1521 addr = force_reg (Pmode, XEXP (src, 0));
1522 emit_move_insn (scratch_string, addr);
1523 emit_label (loop_label);
1524 mem = change_address (src, SImode, scratch_string);
1525 emit_move_insn (word1, mem);
1526 emit_move_insn (word2, adjust_address (mem, SImode, 4));
1527 cr0 = gen_rtx_REG (CCmode, CR0_REGNO);
1528 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0));
1529 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx);
1530 emit_jump_insn (gen_rtx_SET (VOIDmode,
1531 pc_rtx,
1532 gen_rtx_IF_THEN_ELSE (VOIDmode,
1533 cond,
1534 gen_rtx_LABEL_REF
1535 (VOIDmode,
1536 end_label),
1537 pc_rtx)));
1538 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8)));
1539 emit_jump_insn (gen_rtx_SET (VOIDmode,
1540 pc_rtx,
1541 gen_rtx_LABEL_REF (VOIDmode, loop_label)));
1542 emit_barrier ();
1543 emit_label (end_label);
1544 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb));
1545 emit_insn (gen_subsi3 (result, scratch_string, addr));
1546 emit_insn (gen_subsi3 (result, result, const1_rtx));
1547 DONE;
1548 })
1549 \f
1550 (define_split
1551 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1552 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1553 (const_int 0)))
1554 (set (match_operand:SI 0 "gpc_reg_operand" "")
1555 (sign_extend:SI (match_dup 1)))]
1556 "reload_completed"
1557 [(set (match_dup 0)
1558 (sign_extend:SI (match_dup 1)))
1559 (set (match_dup 2)
1560 (compare:CC (match_dup 0)
1561 (const_int 0)))]
1562 "")
1564 ;; Fixed-point arithmetic insns.
1566 (define_expand "add<mode>3"
1567 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1568 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "")
1569 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))]
1570 ""
1571 {
1572 if (<MODE>mode == DImode && ! TARGET_POWERPC64)
1573 {
1574 if (non_short_cint_operand (operands[2], DImode))
1575 FAIL;
1576 }
1577 else if (GET_CODE (operands[2]) == CONST_INT
1578 && ! add_operand (operands[2], <MODE>mode))
1579 {
1580 rtx tmp = ((!can_create_pseudo_p ()
1581 || rtx_equal_p (operands[0], operands[1]))
1582 ? operands[0] : gen_reg_rtx (<MODE>mode));
1584 HOST_WIDE_INT val = INTVAL (operands[2]);
1585 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1586 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1588 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest)))
1589 FAIL;
1591 /* The ordering here is important for the prolog expander.
1592 When space is allocated from the stack, adding 'low' first may
1593 produce a temporary deallocation (which would be bad). */
1594 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest)));
1595 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low)));
1596 DONE;
1597 }
1598 })
1600 ;; Discourage ai/addic because of carry but provide it in an alternative
1601 ;; allowing register zero as source.
1602 (define_insn "*add<mode>3_internal1"
1603 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r")
1604 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b")
1605 (match_operand:GPR 2 "add_operand" "r,I,I,L")))]
1606 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))"
1607 "@
1608 {cax|add} %0,%1,%2
1609 {cal %0,%2(%1)|addi %0,%1,%2}
1610 {ai|addic} %0,%1,%2
1611 {cau|addis} %0,%1,%v2"
1612 [(set_attr "length" "4,4,4,4")])
1614 (define_insn "addsi3_high"
1615 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1616 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1617 (high:SI (match_operand 2 "" ""))))]
1618 "TARGET_MACHO && !TARGET_64BIT"
1619 "{cau|addis} %0,%1,ha16(%2)"
1620 [(set_attr "length" "4")])
1622 (define_insn "*add<mode>3_internal2"
1623 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1624 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1625 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1626 (const_int 0)))
1627 (clobber (match_scratch:P 3 "=r,r,r,r"))]
1628 ""
1629 "@
1630 {cax.|add.} %3,%1,%2
1631 {ai.|addic.} %3,%1,%2
1632 #
1633 #"
1634 [(set_attr "type" "fast_compare,compare,compare,compare")
1635 (set_attr "length" "4,4,8,8")])
1637 (define_split
1638 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1639 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1640 (match_operand:GPR 2 "reg_or_short_operand" ""))
1641 (const_int 0)))
1642 (clobber (match_scratch:GPR 3 ""))]
1643 "reload_completed"
1644 [(set (match_dup 3)
1645 (plus:GPR (match_dup 1)
1646 (match_dup 2)))
1647 (set (match_dup 0)
1648 (compare:CC (match_dup 3)
1649 (const_int 0)))]
1650 "")
1652 (define_insn "*add<mode>3_internal3"
1653 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1654 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r")
1655 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I"))
1656 (const_int 0)))
1657 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
1658 (plus:P (match_dup 1)
1659 (match_dup 2)))]
1660 ""
1661 "@
1662 {cax.|add.} %0,%1,%2
1663 {ai.|addic.} %0,%1,%2
1664 #
1665 #"
1666 [(set_attr "type" "fast_compare,compare,compare,compare")
1667 (set_attr "length" "4,4,8,8")])
1669 (define_split
1670 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1671 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "")
1672 (match_operand:P 2 "reg_or_short_operand" ""))
1673 (const_int 0)))
1674 (set (match_operand:P 0 "gpc_reg_operand" "")
1675 (plus:P (match_dup 1) (match_dup 2)))]
1676 "reload_completed"
1677 [(set (match_dup 0)
1678 (plus:P (match_dup 1)
1679 (match_dup 2)))
1680 (set (match_dup 3)
1681 (compare:CC (match_dup 0)
1682 (const_int 0)))]
1683 "")
1685 ;; Split an add that we can't do in one insn into two insns, each of which
1686 ;; does one 16-bit part. This is used by combine. Note that the low-order
1687 ;; add should be last in case the result gets used in an address.
1689 (define_split
1690 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
1691 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
1692 (match_operand:GPR 2 "non_add_cint_operand" "")))]
1693 ""
1694 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3)))
1695 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))]
1696 {
1697 HOST_WIDE_INT val = INTVAL (operands[2]);
1698 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1699 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode);
1701 operands[4] = GEN_INT (low);
1702 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest)))
1703 operands[3] = GEN_INT (rest);
1704 else if (can_create_pseudo_p ())
1705 {
1706 operands[3] = gen_reg_rtx (DImode);
1707 emit_move_insn (operands[3], operands[2]);
1708 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
1709 DONE;
1710 }
1711 else
1712 FAIL;
1713 })
1715 (define_insn "one_cmpl<mode>2"
1716 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1717 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
1718 ""
1719 "nor %0,%1,%1")
1721 (define_insn ""
1722 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1723 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1724 (const_int 0)))
1725 (clobber (match_scratch:P 2 "=r,r"))]
1726 ""
1727 "@
1728 nor. %2,%1,%1
1729 #"
1730 [(set_attr "type" "fast_compare,compare")
1731 (set_attr "length" "4,8")])
1733 (define_split
1734 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
1735 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1736 (const_int 0)))
1737 (clobber (match_scratch:P 2 ""))]
1738 "reload_completed"
1739 [(set (match_dup 2)
1740 (not:P (match_dup 1)))
1741 (set (match_dup 0)
1742 (compare:CC (match_dup 2)
1743 (const_int 0)))]
1744 "")
1746 (define_insn ""
1747 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1748 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
1749 (const_int 0)))
1750 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1751 (not:P (match_dup 1)))]
1752 ""
1753 "@
1754 nor. %0,%1,%1
1755 #"
1756 [(set_attr "type" "fast_compare,compare")
1757 (set_attr "length" "4,8")])
1759 (define_split
1760 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
1761 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" ""))
1762 (const_int 0)))
1763 (set (match_operand:P 0 "gpc_reg_operand" "")
1764 (not:P (match_dup 1)))]
1765 "reload_completed"
1766 [(set (match_dup 0)
1767 (not:P (match_dup 1)))
1768 (set (match_dup 2)
1769 (compare:CC (match_dup 0)
1770 (const_int 0)))]
1771 "")
1773 (define_insn ""
1774 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1775 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1776 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1777 "! TARGET_POWERPC"
1778 "{sf%I1|subf%I1c} %0,%2,%1")
1780 (define_insn ""
1781 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
1782 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I")
1783 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))]
1784 "TARGET_POWERPC"
1785 "@
1786 subf %0,%2,%1
1787 subfic %0,%2,%1")
1789 (define_insn ""
1790 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1791 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1792 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1793 (const_int 0)))
1794 (clobber (match_scratch:SI 3 "=r,r"))]
1795 "! TARGET_POWERPC"
1796 "@
1797 {sf.|subfc.} %3,%2,%1
1798 #"
1799 [(set_attr "type" "compare")
1800 (set_attr "length" "4,8")])
1802 (define_insn ""
1803 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1804 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1805 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1806 (const_int 0)))
1807 (clobber (match_scratch:P 3 "=r,r"))]
1808 "TARGET_POWERPC"
1809 "@
1810 subf. %3,%2,%1
1811 #"
1812 [(set_attr "type" "fast_compare")
1813 (set_attr "length" "4,8")])
1815 (define_split
1816 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1817 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1818 (match_operand:P 2 "gpc_reg_operand" ""))
1819 (const_int 0)))
1820 (clobber (match_scratch:P 3 ""))]
1821 "reload_completed"
1822 [(set (match_dup 3)
1823 (minus:P (match_dup 1)
1824 (match_dup 2)))
1825 (set (match_dup 0)
1826 (compare:CC (match_dup 3)
1827 (const_int 0)))]
1828 "")
1830 (define_insn ""
1831 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1832 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1833 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1834 (const_int 0)))
1835 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1836 (minus:SI (match_dup 1) (match_dup 2)))]
1837 "! TARGET_POWERPC"
1838 "@
1839 {sf.|subfc.} %0,%2,%1
1840 #"
1841 [(set_attr "type" "compare")
1842 (set_attr "length" "4,8")])
1844 (define_insn ""
1845 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1846 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r")
1847 (match_operand:P 2 "gpc_reg_operand" "r,r"))
1848 (const_int 0)))
1849 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
1850 (minus:P (match_dup 1)
1851 (match_dup 2)))]
1852 "TARGET_POWERPC"
1853 "@
1854 subf. %0,%2,%1
1855 #"
1856 [(set_attr "type" "fast_compare")
1857 (set_attr "length" "4,8")])
1859 (define_split
1860 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1861 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "")
1862 (match_operand:P 2 "gpc_reg_operand" ""))
1863 (const_int 0)))
1864 (set (match_operand:P 0 "gpc_reg_operand" "")
1865 (minus:P (match_dup 1)
1866 (match_dup 2)))]
1867 "reload_completed"
1868 [(set (match_dup 0)
1869 (minus:P (match_dup 1)
1870 (match_dup 2)))
1871 (set (match_dup 3)
1872 (compare:CC (match_dup 0)
1873 (const_int 0)))]
1874 "")
1876 (define_expand "sub<mode>3"
1877 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
1878 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "")
1879 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))]
1880 ""
1881 "
1882 {
1883 if (GET_CODE (operands[2]) == CONST_INT)
1884 {
1885 emit_insn (gen_add<mode>3 (operands[0], operands[1],
1886 negate_rtx (<MODE>mode, operands[2])));
1887 DONE;
1888 }
1889 }")
1891 (define_expand "sminsi3"
1892 [(set (match_dup 3)
1893 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1894 (match_operand:SI 2 "reg_or_short_operand" ""))
1895 (const_int 0)
1896 (minus:SI (match_dup 2) (match_dup 1))))
1897 (set (match_operand:SI 0 "gpc_reg_operand" "")
1898 (minus:SI (match_dup 2) (match_dup 3)))]
1899 "TARGET_ISEL"
1900 "
1901 {
1902 operands[2] = force_reg (SImode, operands[2]);
1903 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
1904 DONE;
1905 }")
1907 (define_expand "smaxsi3"
1908 [(set (match_dup 3)
1909 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
1910 (match_operand:SI 2 "reg_or_short_operand" ""))
1911 (const_int 0)
1912 (minus:SI (match_dup 2) (match_dup 1))))
1913 (set (match_operand:SI 0 "gpc_reg_operand" "")
1914 (plus:SI (match_dup 3) (match_dup 1)))]
1915 "TARGET_ISEL"
1916 "
1917 {
1918 operands[2] = force_reg (SImode, operands[2]);
1919 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
1920 DONE;
1921 }")
1923 (define_expand "uminsi3"
1924 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1925 (match_dup 5)))
1926 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1927 (match_dup 5)))
1928 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1929 (const_int 0)
1930 (minus:SI (match_dup 4) (match_dup 3))))
1931 (set (match_operand:SI 0 "gpc_reg_operand" "")
1932 (minus:SI (match_dup 2) (match_dup 3)))]
1933 "TARGET_ISEL"
1934 "
1935 {
1936 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
1937 DONE;
1938 }")
1940 (define_expand "umaxsi3"
1941 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
1942 (match_dup 5)))
1943 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
1944 (match_dup 5)))
1945 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
1946 (const_int 0)
1947 (minus:SI (match_dup 4) (match_dup 3))))
1948 (set (match_operand:SI 0 "gpc_reg_operand" "")
1949 (plus:SI (match_dup 3) (match_dup 1)))]
1950 "TARGET_ISEL"
1951 "
1952 {
1953 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
1954 DONE;
1955 }")
1957 ;; We don't need abs with condition code because such comparisons should
1958 ;; never be done.
1959 (define_expand "abssi2"
1960 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1961 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
1962 ""
1963 "
1964 {
1965 if (TARGET_ISEL)
1966 {
1967 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
1968 DONE;
1969 }
1970 else
1971 {
1972 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
1973 DONE;
1974 }
1975 }")
1977 (define_insn_and_split "abs<mode>2_isel"
1978 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1979 (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b")))
1980 (clobber (match_scratch:GPR 2 "=&b"))
1981 (clobber (match_scratch:CC 3 "=y"))]
1982 "TARGET_ISEL"
1983 "#"
1984 "&& reload_completed"
1985 [(set (match_dup 2) (neg:GPR (match_dup 1)))
1986 (set (match_dup 3)
1987 (compare:CC (match_dup 1)
1988 (const_int 0)))
1989 (set (match_dup 0)
1990 (if_then_else:GPR (lt (match_dup 3)
1991 (const_int 0))
1992 (match_dup 2)
1993 (match_dup 1)))]
1994 "")
1996 (define_insn_and_split "nabs<mode>2_isel"
1997 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
1998 (neg:GPR (abs:GPR (match_operand:GPR 1 "gpc_reg_operand" "b"))))
1999 (clobber (match_scratch:GPR 2 "=&b"))
2000 (clobber (match_scratch:CC 3 "=y"))]
2001 "TARGET_ISEL"
2002 "#"
2003 "&& reload_completed"
2004 [(set (match_dup 2) (neg:GPR (match_dup 1)))
2005 (set (match_dup 3)
2006 (compare:CC (match_dup 1)
2007 (const_int 0)))
2008 (set (match_dup 0)
2009 (if_then_else:GPR (lt (match_dup 3)
2010 (const_int 0))
2011 (match_dup 1)
2012 (match_dup 2)))]
2013 "")
2015 (define_insn_and_split "abssi2_nopower"
2016 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2017 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2018 (clobber (match_scratch:SI 2 "=&r,&r"))]
2019 "! TARGET_ISEL"
2020 "#"
2021 "&& reload_completed"
2022 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2023 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2024 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2025 "")
2027 (define_insn_and_split "*nabs_nopower"
2028 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2029 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2030 (clobber (match_scratch:SI 2 "=&r,&r"))]
2031 ""
2032 "#"
2033 "&& reload_completed"
2034 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2035 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2036 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2037 "")
2039 (define_expand "neg<mode>2"
2040 [(set (match_operand:SDI 0 "gpc_reg_operand" "")
2041 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))]
2042 ""
2043 "")
2045 (define_insn "*neg<mode>2_internal"
2046 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2047 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2048 ""
2049 "neg %0,%1")
2051 (define_insn ""
2052 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2053 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2054 (const_int 0)))
2055 (clobber (match_scratch:P 2 "=r,r"))]
2056 ""
2057 "@
2058 neg. %2,%1
2059 #"
2060 [(set_attr "type" "fast_compare")
2061 (set_attr "length" "4,8")])
2063 (define_split
2064 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2065 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2066 (const_int 0)))
2067 (clobber (match_scratch:P 2 ""))]
2068 "reload_completed"
2069 [(set (match_dup 2)
2070 (neg:P (match_dup 1)))
2071 (set (match_dup 0)
2072 (compare:CC (match_dup 2)
2073 (const_int 0)))]
2074 "")
2076 (define_insn ""
2077 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2078 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r"))
2079 (const_int 0)))
2080 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2081 (neg:P (match_dup 1)))]
2082 ""
2083 "@
2084 neg. %0,%1
2085 #"
2086 [(set_attr "type" "fast_compare")
2087 (set_attr "length" "4,8")])
2089 (define_split
2090 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2091 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" ""))
2092 (const_int 0)))
2093 (set (match_operand:P 0 "gpc_reg_operand" "")
2094 (neg:P (match_dup 1)))]
2095 "reload_completed"
2096 [(set (match_dup 0)
2097 (neg:P (match_dup 1)))
2098 (set (match_dup 2)
2099 (compare:CC (match_dup 0)
2100 (const_int 0)))]
2101 "")
2103 (define_insn "clz<mode>2"
2104 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2105 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2106 ""
2107 "{cntlz|cntlz<wd>} %0,%1"
2108 [(set_attr "type" "cntlz")])
2110 (define_expand "ctz<mode>2"
2111 [(set (match_dup 2)
2112 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2113 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2114 (match_dup 2)))
2115 (clobber (scratch:CC))])
2116 (set (match_dup 4) (clz:GPR (match_dup 3)))
2117 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2118 (minus:GPR (match_dup 5) (match_dup 4)))]
2119 ""
2120 {
2121 operands[2] = gen_reg_rtx (<MODE>mode);
2122 operands[3] = gen_reg_rtx (<MODE>mode);
2123 operands[4] = gen_reg_rtx (<MODE>mode);
2124 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1);
2125 })
2127 (define_expand "ffs<mode>2"
2128 [(set (match_dup 2)
2129 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))
2130 (parallel [(set (match_dup 3) (and:GPR (match_dup 1)
2131 (match_dup 2)))
2132 (clobber (scratch:CC))])
2133 (set (match_dup 4) (clz:GPR (match_dup 3)))
2134 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2135 (minus:GPR (match_dup 5) (match_dup 4)))]
2136 ""
2137 {
2138 operands[2] = gen_reg_rtx (<MODE>mode);
2139 operands[3] = gen_reg_rtx (<MODE>mode);
2140 operands[4] = gen_reg_rtx (<MODE>mode);
2141 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));
2142 })
2144 (define_insn "popcntb<mode>2"
2145 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2146 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")]
2147 UNSPEC_POPCNTB))]
2148 "TARGET_POPCNTB"
2149 "popcntb %0,%1"
2150 [(set_attr "length" "4")
2151 (set_attr "type" "popcnt")])
2153 (define_insn "popcntd<mode>2"
2154 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2155 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
2156 "TARGET_POPCNTD"
2157 "popcnt<wd> %0,%1"
2158 [(set_attr "length" "4")
2159 (set_attr "type" "popcnt")])
2161 (define_expand "popcount<mode>2"
2162 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2163 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2164 "TARGET_POPCNTB || TARGET_POPCNTD"
2165 {
2166 rs6000_emit_popcount (operands[0], operands[1]);
2167 DONE;
2168 })
2170 (define_insn "parity<mode>2_cmpb"
2171 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2172 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))]
2173 "TARGET_CMPB && TARGET_POPCNTB"
2174 "prty<wd> %0,%1")
2176 (define_expand "parity<mode>2"
2177 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2178 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))]
2179 "TARGET_POPCNTB"
2180 {
2181 rs6000_emit_parity (operands[0], operands[1]);
2182 DONE;
2183 })
2185 ;; Since the hardware zeros the upper part of the register, save generating the
2186 ;; AND immediate if we are converting to unsigned
2187 (define_insn "*bswaphi2_extenddi"
2188 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2189 (zero_extend:DI
2190 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2191 "TARGET_POWERPC64"
2192 "lhbrx %0,%y1"
2193 [(set_attr "length" "4")
2194 (set_attr "type" "load")])
2196 (define_insn "*bswaphi2_extendsi"
2197 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2198 (zero_extend:SI
2199 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))]
2200 "TARGET_POWERPC"
2201 "lhbrx %0,%y1"
2202 [(set_attr "length" "4")
2203 (set_attr "type" "load")])
2205 (define_expand "bswaphi2"
2206 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "")
2207 (bswap:HI
2208 (match_operand:HI 1 "reg_or_mem_operand" "")))
2209 (clobber (match_scratch:SI 2 ""))])]
2210 "TARGET_POWERPC"
2211 {
2212 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2213 operands[1] = force_reg (HImode, operands[1]);
2214 })
2216 (define_insn "bswaphi2_internal"
2217 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r")
2218 (bswap:HI
2219 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r")))
2220 (clobber (match_scratch:SI 2 "=X,X,&r"))]
2221 "TARGET_POWERPC"
2222 "@
2223 lhbrx %0,%y1
2224 sthbrx %1,%y0
2225 #"
2226 [(set_attr "length" "4,4,12")
2227 (set_attr "type" "load,store,*")])
2229 (define_split
2230 [(set (match_operand:HI 0 "gpc_reg_operand" "")
2231 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" "")))
2232 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2233 "TARGET_POWERPC && reload_completed"
2234 [(set (match_dup 3)
2235 (zero_extract:SI (match_dup 4)
2236 (const_int 8)
2237 (const_int 16)))
2238 (set (match_dup 2)
2239 (and:SI (ashift:SI (match_dup 4)
2240 (const_int 8))
2241 (const_int 65280))) ;; 0xff00
2242 (set (match_dup 3)
2243 (ior:SI (match_dup 3)
2244 (match_dup 2)))]
2245 "
2246 {
2247 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0);
2248 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0);
2249 }")
2251 (define_insn "*bswapsi2_extenddi"
2252 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
2253 (zero_extend:DI
2254 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))]
2255 "TARGET_POWERPC64"
2256 "lwbrx %0,%y1"
2257 [(set_attr "length" "4")
2258 (set_attr "type" "load")])
2260 (define_expand "bswapsi2"
2261 [(set (match_operand:SI 0 "reg_or_mem_operand" "")
2262 (bswap:SI
2263 (match_operand:SI 1 "reg_or_mem_operand" "")))]
2264 ""
2265 {
2266 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2267 operands[1] = force_reg (SImode, operands[1]);
2268 })
2270 (define_insn "*bswapsi2_internal"
2271 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r")
2272 (bswap:SI
2273 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))]
2274 ""
2275 "@
2276 {lbrx|lwbrx} %0,%y1
2277 {stbrx|stwbrx} %1,%y0
2278 #"
2279 [(set_attr "length" "4,4,12")
2280 (set_attr "type" "load,store,*")])
2282 (define_split
2283 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2284 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2285 "reload_completed"
2286 [(set (match_dup 0)
2287 (rotate:SI (match_dup 1) (const_int 8)))
2288 (set (zero_extract:SI (match_dup 0)
2289 (const_int 8)
2290 (const_int 0))
2291 (match_dup 1))
2292 (set (zero_extract:SI (match_dup 0)
2293 (const_int 8)
2294 (const_int 16))
2295 (rotate:SI (match_dup 1)
2296 (const_int 16)))]
2297 "")
2299 (define_expand "bswapdi2"
2300 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "")
2301 (bswap:DI
2302 (match_operand:DI 1 "reg_or_mem_operand" "")))
2303 (clobber (match_scratch:DI 2 ""))
2304 (clobber (match_scratch:DI 3 ""))
2305 (clobber (match_scratch:DI 4 ""))])]
2306 ""
2307 {
2308 if (!REG_P (operands[0]) && !REG_P (operands[1]))
2309 operands[1] = force_reg (DImode, operands[1]);
2311 if (!TARGET_POWERPC64)
2312 {
2313 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode
2314 that uses 64-bit registers needs the same scratch registers as 64-bit
2315 mode. */
2316 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1]));
2317 DONE;
2318 }
2319 })
2321 ;; Power7/cell has ldbrx/stdbrx, so use it directly
2322 (define_insn "*bswapdi2_ldbrx"
2323 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2324 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2325 (clobber (match_scratch:DI 2 "=X,X,&r"))
2326 (clobber (match_scratch:DI 3 "=X,X,&r"))
2327 (clobber (match_scratch:DI 4 "=X,X,&r"))]
2328 "TARGET_POWERPC64 && TARGET_LDBRX
2329 && (REG_P (operands[0]) || REG_P (operands[1]))"
2330 "@
2331 ldbrx %0,%y1
2332 stdbrx %1,%y0
2333 #"
2334 [(set_attr "length" "4,4,36")
2335 (set_attr "type" "load,store,*")])
2337 ;; Non-power7/cell, fall back to use lwbrx/stwbrx
2338 (define_insn "*bswapdi2_64bit"
2339 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2340 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2341 (clobber (match_scratch:DI 2 "=&b,&b,&r"))
2342 (clobber (match_scratch:DI 3 "=&r,&r,&r"))
2343 (clobber (match_scratch:DI 4 "=&r,X,&r"))]
2344 "TARGET_POWERPC64 && !TARGET_LDBRX
2345 && (REG_P (operands[0]) || REG_P (operands[1]))"
2346 "#"
2347 [(set_attr "length" "16,12,36")])
2349 (define_split
2350 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2351 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2352 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2353 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2354 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))]
2355 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2356 [(const_int 0)]
2357 "
2358 {
2359 rtx dest = operands[0];
2360 rtx src = operands[1];
2361 rtx op2 = operands[2];
2362 rtx op3 = operands[3];
2363 rtx op4 = operands[4];
2364 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode, 4);
2365 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode, 4);
2366 rtx addr1;
2367 rtx addr2;
2368 rtx word_high;
2369 rtx word_low;
2371 addr1 = XEXP (src, 0);
2372 if (GET_CODE (addr1) == PLUS)
2373 {
2374 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2375 if (TARGET_AVOID_XFORM)
2376 {
2377 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2378 addr2 = op2;
2379 }
2380 else
2381 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2382 }
2383 else if (TARGET_AVOID_XFORM)
2384 {
2385 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2386 addr2 = op2;
2387 }
2388 else
2389 {
2390 emit_move_insn (op2, GEN_INT (4));
2391 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2392 }
2394 if (BYTES_BIG_ENDIAN)
2395 {
2396 word_high = change_address (src, SImode, addr1);
2397 word_low = change_address (src, SImode, addr2);
2398 }
2399 else
2400 {
2401 word_high = change_address (src, SImode, addr2);
2402 word_low = change_address (src, SImode, addr1);
2403 }
2405 emit_insn (gen_bswapsi2 (op3_32, word_low));
2406 emit_insn (gen_bswapsi2 (op4_32, word_high));
2407 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32)));
2408 emit_insn (gen_iordi3 (dest, dest, op4));
2409 }")
2411 (define_split
2412 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2413 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2414 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2415 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2416 (clobber (match_operand:DI 4 "" ""))]
2417 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed"
2418 [(const_int 0)]
2419 "
2420 {
2421 rtx dest = operands[0];
2422 rtx src = operands[1];
2423 rtx op2 = operands[2];
2424 rtx op3 = operands[3];
2425 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2426 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2427 rtx addr1;
2428 rtx addr2;
2429 rtx word_high;
2430 rtx word_low;
2432 addr1 = XEXP (dest, 0);
2433 if (GET_CODE (addr1) == PLUS)
2434 {
2435 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2436 if (TARGET_AVOID_XFORM)
2437 {
2438 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2439 addr2 = op2;
2440 }
2441 else
2442 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1));
2443 }
2444 else if (TARGET_AVOID_XFORM)
2445 {
2446 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2447 addr2 = op2;
2448 }
2449 else
2450 {
2451 emit_move_insn (op2, GEN_INT (4));
2452 addr2 = gen_rtx_PLUS (Pmode, op2, addr1);
2453 }
2455 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32)));
2456 if (BYTES_BIG_ENDIAN)
2457 {
2458 word_high = change_address (dest, SImode, addr1);
2459 word_low = change_address (dest, SImode, addr2);
2460 emit_insn (gen_bswapsi2 (word_high, src_si));
2461 emit_insn (gen_bswapsi2 (word_low, op3_si));
2462 }
2463 else
2464 {
2465 word_high = change_address (dest, SImode, addr2);
2466 word_low = change_address (dest, SImode, addr1);
2467 emit_insn (gen_bswapsi2 (word_low, src_si));
2468 emit_insn (gen_bswapsi2 (word_high, op3_si));
2469 }
2470 }")
2472 (define_split
2473 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2474 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2475 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
2476 (clobber (match_operand:DI 3 "gpc_reg_operand" ""))
2477 (clobber (match_operand:DI 4 "" ""))]
2478 "TARGET_POWERPC64 && reload_completed"
2479 [(const_int 0)]
2480 "
2481 {
2482 rtx dest = operands[0];
2483 rtx src = operands[1];
2484 rtx op2 = operands[2];
2485 rtx op3 = operands[3];
2486 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, 4);
2487 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 4);
2488 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, 4);
2489 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 4);
2491 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32)));
2492 emit_insn (gen_bswapsi2 (dest_si, src_si));
2493 emit_insn (gen_bswapsi2 (op3_si, op2_si));
2494 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32)));
2495 emit_insn (gen_iordi3 (dest, dest, op3));
2496 }")
2498 (define_insn "bswapdi2_32bit"
2499 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r")
2500 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r")))
2501 (clobber (match_scratch:SI 2 "=&b,&b,X"))]
2502 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))"
2503 "#"
2504 [(set_attr "length" "16,12,36")])
2506 (define_split
2507 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2508 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" "")))
2509 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2510 "!TARGET_POWERPC64 && reload_completed"
2511 [(const_int 0)]
2512 "
2513 {
2514 rtx dest = operands[0];
2515 rtx src = operands[1];
2516 rtx op2 = operands[2];
2517 rtx dest_hi = simplify_gen_subreg (SImode, dest, DImode, 0);
2518 rtx dest_lo = simplify_gen_subreg (SImode, dest, DImode, 4);
2519 rtx addr1;
2520 rtx addr2;
2521 rtx word_high;
2522 rtx word_low;
2524 addr1 = XEXP (src, 0);
2525 if (GET_CODE (addr1) == PLUS)
2526 {
2527 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2528 if (TARGET_AVOID_XFORM)
2529 {
2530 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2531 addr2 = op2;
2532 }
2533 else
2534 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2535 }
2536 else if (TARGET_AVOID_XFORM)
2537 {
2538 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2539 addr2 = op2;
2540 }
2541 else
2542 {
2543 emit_move_insn (op2, GEN_INT (4));
2544 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2545 }
2547 if (BYTES_BIG_ENDIAN)
2548 {
2549 word_high = change_address (src, SImode, addr1);
2550 word_low = change_address (src, SImode, addr2);
2551 }
2552 else
2553 {
2554 word_high = change_address (src, SImode, addr2);
2555 word_low = change_address (src, SImode, addr1);
2556 }
2558 emit_insn (gen_bswapsi2 (dest_hi, word_low));
2559 emit_insn (gen_bswapsi2 (dest_lo, word_high));
2560 }")
2562 (define_split
2563 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "")
2564 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2565 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))]
2566 "!TARGET_POWERPC64 && reload_completed"
2567 [(const_int 0)]
2568 "
2569 {
2570 rtx dest = operands[0];
2571 rtx src = operands[1];
2572 rtx op2 = operands[2];
2573 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2574 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2575 rtx addr1;
2576 rtx addr2;
2577 rtx word_high;
2578 rtx word_low;
2580 addr1 = XEXP (dest, 0);
2581 if (GET_CODE (addr1) == PLUS)
2582 {
2583 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4)));
2584 if (TARGET_AVOID_XFORM)
2585 {
2586 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2));
2587 addr2 = op2;
2588 }
2589 else
2590 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1));
2591 }
2592 else if (TARGET_AVOID_XFORM)
2593 {
2594 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4)));
2595 addr2 = op2;
2596 }
2597 else
2598 {
2599 emit_move_insn (op2, GEN_INT (4));
2600 addr2 = gen_rtx_PLUS (SImode, op2, addr1);
2601 }
2603 if (BYTES_BIG_ENDIAN)
2604 {
2605 word_high = change_address (dest, SImode, addr1);
2606 word_low = change_address (dest, SImode, addr2);
2607 }
2608 else
2609 {
2610 word_high = change_address (dest, SImode, addr2);
2611 word_low = change_address (dest, SImode, addr1);
2612 }
2614 emit_insn (gen_bswapsi2 (word_high, src_low));
2615 emit_insn (gen_bswapsi2 (word_low, src_high));
2616 }")
2618 (define_split
2619 [(set (match_operand:DI 0 "gpc_reg_operand" "")
2620 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" "")))
2621 (clobber (match_operand:SI 2 "" ""))]
2622 "!TARGET_POWERPC64 && reload_completed"
2623 [(const_int 0)]
2624 "
2625 {
2626 rtx dest = operands[0];
2627 rtx src = operands[1];
2628 rtx src_high = simplify_gen_subreg (SImode, src, DImode, 0);
2629 rtx src_low = simplify_gen_subreg (SImode, src, DImode, 4);
2630 rtx dest_high = simplify_gen_subreg (SImode, dest, DImode, 0);
2631 rtx dest_low = simplify_gen_subreg (SImode, dest, DImode, 4);
2633 emit_insn (gen_bswapsi2 (dest_high, src_low));
2634 emit_insn (gen_bswapsi2 (dest_low, src_high));
2635 }")
2637 (define_insn "mulsi3"
2638 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2639 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2640 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2641 ""
2642 "@
2643 {muls|mullw} %0,%1,%2
2644 {muli|mulli} %0,%1,%2"
2645 [(set (attr "type")
2646 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2647 (const_string "imul3")
2648 (match_operand:SI 2 "short_cint_operand" "")
2649 (const_string "imul2")]
2650 (const_string "imul")))])
2652 (define_insn "*mulsi3_internal1"
2653 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2654 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2655 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2656 (const_int 0)))
2657 (clobber (match_scratch:SI 3 "=r,r"))]
2658 ""
2659 "@
2660 {muls.|mullw.} %3,%1,%2
2661 #"
2662 [(set_attr "type" "imul_compare")
2663 (set_attr "length" "4,8")])
2665 (define_split
2666 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
2667 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2668 (match_operand:SI 2 "gpc_reg_operand" ""))
2669 (const_int 0)))
2670 (clobber (match_scratch:SI 3 ""))]
2671 "reload_completed"
2672 [(set (match_dup 3)
2673 (mult:SI (match_dup 1) (match_dup 2)))
2674 (set (match_dup 0)
2675 (compare:CC (match_dup 3)
2676 (const_int 0)))]
2677 "")
2679 (define_insn "*mulsi3_internal2"
2680 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2681 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2682 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2683 (const_int 0)))
2684 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2685 (mult:SI (match_dup 1) (match_dup 2)))]
2686 ""
2687 "@
2688 {muls.|mullw.} %0,%1,%2
2689 #"
2690 [(set_attr "type" "imul_compare")
2691 (set_attr "length" "4,8")])
2693 (define_split
2694 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
2695 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2696 (match_operand:SI 2 "gpc_reg_operand" ""))
2697 (const_int 0)))
2698 (set (match_operand:SI 0 "gpc_reg_operand" "")
2699 (mult:SI (match_dup 1) (match_dup 2)))]
2700 "reload_completed"
2701 [(set (match_dup 0)
2702 (mult:SI (match_dup 1) (match_dup 2)))
2703 (set (match_dup 3)
2704 (compare:CC (match_dup 0)
2705 (const_int 0)))]
2706 "")
2708 ;; Operand 1 is divided by operand 2; quotient goes to operand
2709 ;; 0 and remainder to operand 3.
2710 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2712 (define_expand "divmodsi4"
2713 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2714 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2715 (match_operand:SI 2 "gpc_reg_operand" "")))
2716 (set (match_operand:SI 3 "register_operand" "")
2717 (mod:SI (match_dup 1) (match_dup 2)))])]
2718 "! TARGET_POWERPC"
2719 "
2720 {
2721 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2722 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2723 emit_insn (gen_divss_call ());
2724 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2725 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2726 DONE;
2727 }")
2729 (define_expand "udiv<mode>3"
2730 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2731 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2732 (match_operand:GPR 2 "gpc_reg_operand" "")))]
2733 ""
2734 "
2735 {
2736 if (! TARGET_POWERPC)
2737 {
2738 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2739 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2740 emit_insn (gen_quous_call ());
2741 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2742 DONE;
2743 }
2744 }")
2746 (define_insn "*udivsi3"
2747 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2748 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2749 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2750 "TARGET_POWERPC"
2751 "div<wd>u %0,%1,%2"
2752 [(set (attr "type")
2753 (cond [(match_operand:SI 0 "" "")
2754 (const_string "idiv")]
2755 (const_string "ldiv")))])
2758 ;; For powers of two we can do srai/aze for divide and then adjust for
2759 ;; modulus. If it isn't a power of two, force operands into register and do
2760 ;; a normal divide; for AIX common-mode, use quoss call on register operands.
2761 (define_expand "div<mode>3"
2762 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
2763 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2764 (match_operand:GPR 2 "reg_or_cint_operand" "")))]
2765 ""
2766 "
2767 {
2768 if (GET_CODE (operands[2]) == CONST_INT
2769 && INTVAL (operands[2]) > 0
2770 && exact_log2 (INTVAL (operands[2])) >= 0)
2771 ;
2772 else if (TARGET_POWERPC)
2773 {
2774 operands[2] = force_reg (<MODE>mode, operands[2]);
2775 }
2776 else
2777 {
2778 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2779 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2780 emit_insn (gen_quoss_call ());
2781 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2782 DONE;
2783 }
2784 }")
2786 (define_insn "*div<mode>3_no_mq"
2787 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2788 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2789 (match_operand:GPR 2 "gpc_reg_operand" "r")))]
2790 "TARGET_POWERPC"
2791 "div<wd> %0,%1,%2"
2792 [(set (attr "type")
2793 (cond [(match_operand:SI 0 "" "")
2794 (const_string "idiv")]
2795 (const_string "ldiv")))])
2797 (define_expand "mod<mode>3"
2798 [(use (match_operand:GPR 0 "gpc_reg_operand" ""))
2799 (use (match_operand:GPR 1 "gpc_reg_operand" ""))
2800 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))]
2801 ""
2802 "
2803 {
2804 int i;
2805 rtx temp1;
2806 rtx temp2;
2808 if (GET_CODE (operands[2]) != CONST_INT
2809 || INTVAL (operands[2]) <= 0
2810 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2811 FAIL;
2813 temp1 = gen_reg_rtx (<MODE>mode);
2814 temp2 = gen_reg_rtx (<MODE>mode);
2816 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2]));
2817 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i)));
2818 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2));
2819 DONE;
2820 }")
2822 (define_insn ""
2823 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
2824 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
2825 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))]
2826 ""
2827 "{srai|sra<wd>i} %0,%1,%p2\;{aze|addze} %0,%0"
2828 [(set_attr "type" "two")
2829 (set_attr "length" "8")])
2831 (define_insn ""
2832 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2833 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2834 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2835 (const_int 0)))
2836 (clobber (match_scratch:P 3 "=r,r"))]
2837 ""
2838 "@
2839 {srai|sra<wd>i} %3,%1,%p2\;{aze.|addze.} %3,%3
2840 #"
2841 [(set_attr "type" "compare")
2842 (set_attr "length" "8,12")
2843 (set_attr "cell_micro" "not")])
2845 (define_split
2846 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2847 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2848 (match_operand:GPR 2 "exact_log2_cint_operand"
2849 ""))
2850 (const_int 0)))
2851 (clobber (match_scratch:GPR 3 ""))]
2852 "reload_completed"
2853 [(set (match_dup 3)
2854 (div:<MODE> (match_dup 1) (match_dup 2)))
2855 (set (match_dup 0)
2856 (compare:CC (match_dup 3)
2857 (const_int 0)))]
2858 "")
2860 (define_insn ""
2861 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2862 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r")
2863 (match_operand:P 2 "exact_log2_cint_operand" "N,N"))
2864 (const_int 0)))
2865 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
2866 (div:P (match_dup 1) (match_dup 2)))]
2867 ""
2868 "@
2869 {srai|sra<wd>i} %0,%1,%p2\;{aze.|addze.} %0,%0
2870 #"
2871 [(set_attr "type" "compare")
2872 (set_attr "length" "8,12")
2873 (set_attr "cell_micro" "not")])
2875 (define_split
2876 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2877 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
2878 (match_operand:GPR 2 "exact_log2_cint_operand"
2879 ""))
2880 (const_int 0)))
2881 (set (match_operand:GPR 0 "gpc_reg_operand" "")
2882 (div:GPR (match_dup 1) (match_dup 2)))]
2883 "reload_completed"
2884 [(set (match_dup 0)
2885 (div:<MODE> (match_dup 1) (match_dup 2)))
2886 (set (match_dup 3)
2887 (compare:CC (match_dup 0)
2888 (const_int 0)))]
2889 "")
2891 (define_expand "udivmodsi4"
2892 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2893 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2894 (match_operand:SI 2 "reg_or_cint_operand" "")))
2895 (set (match_operand:SI 3 "gpc_reg_operand" "")
2896 (umod:SI (match_dup 1) (match_dup 2)))])]
2897 ""
2898 "
2899 {
2900 if (! TARGET_POWERPC)
2901 {
2902 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2903 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2904 emit_insn (gen_divus_call ());
2905 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2906 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2907 DONE;
2908 }
2909 else
2910 FAIL;
2911 }")
2913 ;; AIX architecture-independent common-mode multiply (DImode),
2914 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2915 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2916 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2917 ;; assumed unused if generating common-mode, so ignore.
2918 (define_insn "mulh_call"
2919 [(set (reg:SI 3)
2920 (truncate:SI
2921 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2922 (sign_extend:DI (reg:SI 4)))
2923 (const_int 32))))
2924 (clobber (reg:SI LR_REGNO))]
2925 "! TARGET_POWERPC"
2926 "bla __mulh"
2927 [(set_attr "type" "imul")])
2929 (define_insn "mull_call"
2930 [(set (reg:DI 3)
2931 (mult:DI (sign_extend:DI (reg:SI 3))
2932 (sign_extend:DI (reg:SI 4))))
2933 (clobber (reg:SI LR_REGNO))
2934 (clobber (reg:SI 0))]
2935 "! TARGET_POWERPC"
2936 "bla __mull"
2937 [(set_attr "type" "imul")])
2939 (define_insn "divss_call"
2940 [(set (reg:SI 3)
2941 (div:SI (reg:SI 3) (reg:SI 4)))
2942 (set (reg:SI 4)
2943 (mod:SI (reg:SI 3) (reg:SI 4)))
2944 (clobber (reg:SI LR_REGNO))
2945 (clobber (reg:SI 0))]
2946 "! TARGET_POWERPC"
2947 "bla __divss"
2948 [(set_attr "type" "idiv")])
2950 (define_insn "divus_call"
2951 [(set (reg:SI 3)
2952 (udiv:SI (reg:SI 3) (reg:SI 4)))
2953 (set (reg:SI 4)
2954 (umod:SI (reg:SI 3) (reg:SI 4)))
2955 (clobber (reg:SI LR_REGNO))
2956 (clobber (reg:SI 0))
2957 (clobber (match_scratch:CC 0 "=x"))
2958 (clobber (reg:CC CR1_REGNO))]
2959 "! TARGET_POWERPC"
2960 "bla __divus"
2961 [(set_attr "type" "idiv")])
2963 (define_insn "quoss_call"
2964 [(set (reg:SI 3)
2965 (div:SI (reg:SI 3) (reg:SI 4)))
2966 (clobber (reg:SI LR_REGNO))]
2967 "! TARGET_POWERPC"
2968 "bla __quoss"
2969 [(set_attr "type" "idiv")])
2971 (define_insn "quous_call"
2972 [(set (reg:SI 3)
2973 (udiv:SI (reg:SI 3) (reg:SI 4)))
2974 (clobber (reg:SI LR_REGNO))
2975 (clobber (reg:SI 0))
2976 (clobber (match_scratch:CC 0 "=x"))
2977 (clobber (reg:CC CR1_REGNO))]
2978 "! TARGET_POWERPC"
2979 "bla __quous"
2980 [(set_attr "type" "idiv")])
2981 \f
2982 ;; Logical instructions
2983 ;; The logical instructions are mostly combined by using match_operator,
2984 ;; but the plain AND insns are somewhat different because there is no
2985 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2986 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2988 (define_expand "andsi3"
2989 [(parallel
2990 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2991 (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
2992 (match_operand:SI 2 "and_operand" "")))
2993 (clobber (match_scratch:CC 3 ""))])]
2994 ""
2995 "")
2997 (define_insn "andsi3_mc"
2998 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2999 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
3000 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
3001 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
3002 "rs6000_gen_cell_microcode"
3003 "@
3004 and %0,%1,%2
3005 {rlinm|rlwinm} %0,%1,0,%m2,%M2
3006 {andil.|andi.} %0,%1,%b2
3007 {andiu.|andis.} %0,%1,%u2"
3008 [(set_attr "type" "*,*,fast_compare,fast_compare")])
3010 (define_insn "andsi3_nomc"
3011 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3012 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3013 (match_operand:SI 2 "and_operand" "?r,T")))
3014 (clobber (match_scratch:CC 3 "=X,X"))]
3015 "!rs6000_gen_cell_microcode"
3016 "@
3017 and %0,%1,%2
3018 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3020 (define_insn "andsi3_internal0_nomc"
3021 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3022 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
3023 (match_operand:SI 2 "and_operand" "?r,T")))]
3024 "!rs6000_gen_cell_microcode"
3025 "@
3026 and %0,%1,%2
3027 {rlinm|rlwinm} %0,%1,0,%m2,%M2")
3030 ;; Note to set cr's other than cr0 we do the and immediate and then
3031 ;; the test again -- this avoids a mfcr which on the higher end
3032 ;; machines causes an execution serialization
3034 (define_insn "*andsi3_internal2_mc"
3035 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3036 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3037 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3038 (const_int 0)))
3039 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3040 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3041 "TARGET_32BIT && rs6000_gen_cell_microcode"
3042 "@
3043 and. %3,%1,%2
3044 {andil.|andi.} %3,%1,%b2
3045 {andiu.|andis.} %3,%1,%u2
3046 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3047 #
3048 #
3049 #
3050 #"
3051 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3052 compare,compare,compare,compare")
3053 (set_attr "length" "4,4,4,4,8,8,8,8")])
3055 (define_insn "*andsi3_internal3_mc"
3056 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3057 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3058 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3059 (const_int 0)))
3060 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
3061 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3062 "TARGET_64BIT && rs6000_gen_cell_microcode"
3063 "@
3064 #
3065 {andil.|andi.} %3,%1,%b2
3066 {andiu.|andis.} %3,%1,%u2
3067 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
3068 #
3069 #
3070 #
3071 #"
3072 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3073 compare,compare,compare")
3074 (set_attr "length" "8,4,4,4,8,8,8,8")])
3076 (define_split
3077 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3078 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "")
3079 (match_operand:GPR 2 "and_operand" ""))
3080 (const_int 0)))
3081 (clobber (match_scratch:GPR 3 ""))
3082 (clobber (match_scratch:CC 4 ""))]
3083 "reload_completed"
3084 [(parallel [(set (match_dup 3)
3085 (and:<MODE> (match_dup 1)
3086 (match_dup 2)))
3087 (clobber (match_dup 4))])
3088 (set (match_dup 0)
3089 (compare:CC (match_dup 3)
3090 (const_int 0)))]
3091 "")
3093 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
3094 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
3096 (define_split
3097 [(set (match_operand:CC 0 "cc_reg_operand" "")
3098 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3099 (match_operand:SI 2 "gpc_reg_operand" ""))
3100 (const_int 0)))
3101 (clobber (match_scratch:SI 3 ""))
3102 (clobber (match_scratch:CC 4 ""))]
3103 "TARGET_POWERPC64 && reload_completed"
3104 [(parallel [(set (match_dup 3)
3105 (and:SI (match_dup 1)
3106 (match_dup 2)))
3107 (clobber (match_dup 4))])
3108 (set (match_dup 0)
3109 (compare:CC (match_dup 3)
3110 (const_int 0)))]
3111 "")
3113 (define_insn "*andsi3_internal4"
3114 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3115 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3116 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3117 (const_int 0)))
3118 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3119 (and:SI (match_dup 1)
3120 (match_dup 2)))
3121 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3122 "TARGET_32BIT && rs6000_gen_cell_microcode"
3123 "@
3124 and. %0,%1,%2
3125 {andil.|andi.} %0,%1,%b2
3126 {andiu.|andis.} %0,%1,%u2
3127 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3128 #
3129 #
3130 #
3131 #"
3132 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\
3133 compare,compare,compare,compare")
3134 (set_attr "length" "4,4,4,4,8,8,8,8")])
3136 (define_insn "*andsi3_internal5_mc"
3137 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3138 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3139 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3140 (const_int 0)))
3141 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3142 (and:SI (match_dup 1)
3143 (match_dup 2)))
3144 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3145 "TARGET_64BIT && rs6000_gen_cell_microcode"
3146 "@
3147 #
3148 {andil.|andi.} %0,%1,%b2
3149 {andiu.|andis.} %0,%1,%u2
3150 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3151 #
3152 #
3153 #
3154 #"
3155 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\
3156 compare,compare,compare")
3157 (set_attr "length" "8,4,4,4,8,8,8,8")])
3159 (define_split
3160 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3161 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3162 (match_operand:SI 2 "and_operand" ""))
3163 (const_int 0)))
3164 (set (match_operand:SI 0 "gpc_reg_operand" "")
3165 (and:SI (match_dup 1)
3166 (match_dup 2)))
3167 (clobber (match_scratch:CC 4 ""))]
3168 "reload_completed"
3169 [(parallel [(set (match_dup 0)
3170 (and:SI (match_dup 1)
3171 (match_dup 2)))
3172 (clobber (match_dup 4))])
3173 (set (match_dup 3)
3174 (compare:CC (match_dup 0)
3175 (const_int 0)))]
3176 "")
3178 (define_split
3179 [(set (match_operand:CC 3 "cc_reg_operand" "")
3180 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3181 (match_operand:SI 2 "gpc_reg_operand" ""))
3182 (const_int 0)))
3183 (set (match_operand:SI 0 "gpc_reg_operand" "")
3184 (and:SI (match_dup 1)
3185 (match_dup 2)))
3186 (clobber (match_scratch:CC 4 ""))]
3187 "TARGET_POWERPC64 && reload_completed"
3188 [(parallel [(set (match_dup 0)
3189 (and:SI (match_dup 1)
3190 (match_dup 2)))
3191 (clobber (match_dup 4))])
3192 (set (match_dup 3)
3193 (compare:CC (match_dup 0)
3194 (const_int 0)))]
3195 "")
3197 ;; Handle the PowerPC64 rlwinm corner case
3199 (define_insn_and_split "*andsi3_internal6"
3200 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3201 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3202 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3203 "TARGET_POWERPC64"
3204 "#"
3205 "TARGET_POWERPC64"
3206 [(set (match_dup 0)
3207 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3208 (match_dup 4)))
3209 (set (match_dup 0)
3210 (rotate:SI (match_dup 0) (match_dup 5)))]
3211 "
3212 {
3213 int mb = extract_MB (operands[2]);
3214 int me = extract_ME (operands[2]);
3215 operands[3] = GEN_INT (me + 1);
3216 operands[5] = GEN_INT (32 - (me + 1));
3217 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3218 }"
3219 [(set_attr "length" "8")])
3221 (define_expand "iorsi3"
3222 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3223 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3224 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3225 ""
3226 "
3227 {
3228 if (GET_CODE (operands[2]) == CONST_INT
3229 && ! logical_operand (operands[2], SImode))
3230 {
3231 HOST_WIDE_INT value = INTVAL (operands[2]);
3232 rtx tmp = ((!can_create_pseudo_p ()
3233 || rtx_equal_p (operands[0], operands[1]))
3234 ? operands[0] : gen_reg_rtx (SImode));
3236 emit_insn (gen_iorsi3 (tmp, operands[1],
3237 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3238 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3239 DONE;
3240 }
3241 }")
3243 (define_expand "xorsi3"
3244 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3245 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3246 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3247 ""
3248 "
3249 {
3250 if (GET_CODE (operands[2]) == CONST_INT
3251 && ! logical_operand (operands[2], SImode))
3252 {
3253 HOST_WIDE_INT value = INTVAL (operands[2]);
3254 rtx tmp = ((!can_create_pseudo_p ()
3255 || rtx_equal_p (operands[0], operands[1]))
3256 ? operands[0] : gen_reg_rtx (SImode));
3258 emit_insn (gen_xorsi3 (tmp, operands[1],
3259 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3260 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3261 DONE;
3262 }
3263 }")
3265 (define_insn "*boolsi3_internal1"
3266 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3267 (match_operator:SI 3 "boolean_or_operator"
3268 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3269 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3270 ""
3271 "@
3272 %q3 %0,%1,%2
3273 {%q3il|%q3i} %0,%1,%b2
3274 {%q3iu|%q3is} %0,%1,%u2")
3276 (define_insn "*boolsi3_internal2"
3277 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3278 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3279 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3280 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3281 (const_int 0)))
3282 (clobber (match_scratch:SI 3 "=r,r"))]
3283 "TARGET_32BIT"
3284 "@
3285 %q4. %3,%1,%2
3286 #"
3287 [(set_attr "type" "fast_compare,compare")
3288 (set_attr "length" "4,8")])
3290 (define_split
3291 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3292 (compare:CC (match_operator:SI 4 "boolean_operator"
3293 [(match_operand:SI 1 "gpc_reg_operand" "")
3294 (match_operand:SI 2 "gpc_reg_operand" "")])
3295 (const_int 0)))
3296 (clobber (match_scratch:SI 3 ""))]
3297 "TARGET_32BIT && reload_completed"
3298 [(set (match_dup 3) (match_dup 4))
3299 (set (match_dup 0)
3300 (compare:CC (match_dup 3)
3301 (const_int 0)))]
3302 "")
3304 (define_insn "*boolsi3_internal3"
3305 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3306 (compare:CC (match_operator:SI 4 "boolean_operator"
3307 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3308 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3309 (const_int 0)))
3310 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3311 (match_dup 4))]
3312 "TARGET_32BIT"
3313 "@
3314 %q4. %0,%1,%2
3315 #"
3316 [(set_attr "type" "fast_compare,compare")
3317 (set_attr "length" "4,8")])
3319 (define_split
3320 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3321 (compare:CC (match_operator:SI 4 "boolean_operator"
3322 [(match_operand:SI 1 "gpc_reg_operand" "")
3323 (match_operand:SI 2 "gpc_reg_operand" "")])
3324 (const_int 0)))
3325 (set (match_operand:SI 0 "gpc_reg_operand" "")
3326 (match_dup 4))]
3327 "TARGET_32BIT && reload_completed"
3328 [(set (match_dup 0) (match_dup 4))
3329 (set (match_dup 3)
3330 (compare:CC (match_dup 0)
3331 (const_int 0)))]
3332 "")
3334 ;; Split a logical operation that we can't do in one insn into two insns,
3335 ;; each of which does one 16-bit part. This is used by combine.
3337 (define_split
3338 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3339 (match_operator:SI 3 "boolean_or_operator"
3340 [(match_operand:SI 1 "gpc_reg_operand" "")
3341 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3342 ""
3343 [(set (match_dup 0) (match_dup 4))
3344 (set (match_dup 0) (match_dup 5))]
3345 "
3346 {
3347 rtx i;
3348 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3349 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3350 operands[1], i);
3351 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3352 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
3353 operands[0], i);
3354 }")
3356 (define_insn "*boolcsi3_internal1"
3357 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3358 (match_operator:SI 3 "boolean_operator"
3359 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3360 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3361 ""
3362 "%q3 %0,%2,%1")
3364 (define_insn "*boolcsi3_internal2"
3365 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3366 (compare:CC (match_operator:SI 4 "boolean_operator"
3367 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3368 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3369 (const_int 0)))
3370 (clobber (match_scratch:SI 3 "=r,r"))]
3371 "TARGET_32BIT"
3372 "@
3373 %q4. %3,%2,%1
3374 #"
3375 [(set_attr "type" "compare")
3376 (set_attr "length" "4,8")])
3378 (define_split
3379 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3380 (compare:CC (match_operator:SI 4 "boolean_operator"
3381 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3382 (match_operand:SI 2 "gpc_reg_operand" "")])
3383 (const_int 0)))
3384 (clobber (match_scratch:SI 3 ""))]
3385 "TARGET_32BIT && reload_completed"
3386 [(set (match_dup 3) (match_dup 4))
3387 (set (match_dup 0)
3388 (compare:CC (match_dup 3)
3389 (const_int 0)))]
3390 "")
3392 (define_insn "*boolcsi3_internal3"
3393 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3394 (compare:CC (match_operator:SI 4 "boolean_operator"
3395 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3396 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3397 (const_int 0)))
3398 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3399 (match_dup 4))]
3400 "TARGET_32BIT"
3401 "@
3402 %q4. %0,%2,%1
3403 #"
3404 [(set_attr "type" "compare")
3405 (set_attr "length" "4,8")])
3407 (define_split
3408 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3409 (compare:CC (match_operator:SI 4 "boolean_operator"
3410 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3411 (match_operand:SI 2 "gpc_reg_operand" "")])
3412 (const_int 0)))
3413 (set (match_operand:SI 0 "gpc_reg_operand" "")
3414 (match_dup 4))]
3415 "TARGET_32BIT && reload_completed"
3416 [(set (match_dup 0) (match_dup 4))
3417 (set (match_dup 3)
3418 (compare:CC (match_dup 0)
3419 (const_int 0)))]
3420 "")
3422 (define_insn "*boolccsi3_internal1"
3423 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3424 (match_operator:SI 3 "boolean_operator"
3425 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3426 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3427 ""
3428 "%q3 %0,%1,%2")
3430 (define_insn "*boolccsi3_internal2"
3431 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3432 (compare:CC (match_operator:SI 4 "boolean_operator"
3433 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3434 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3435 (const_int 0)))
3436 (clobber (match_scratch:SI 3 "=r,r"))]
3437 "TARGET_32BIT"
3438 "@
3439 %q4. %3,%1,%2
3440 #"
3441 [(set_attr "type" "fast_compare,compare")
3442 (set_attr "length" "4,8")])
3444 (define_split
3445 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3446 (compare:CC (match_operator:SI 4 "boolean_operator"
3447 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3448 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3449 (const_int 0)))
3450 (clobber (match_scratch:SI 3 ""))]
3451 "TARGET_32BIT && reload_completed"
3452 [(set (match_dup 3) (match_dup 4))
3453 (set (match_dup 0)
3454 (compare:CC (match_dup 3)
3455 (const_int 0)))]
3456 "")
3458 (define_insn "*boolccsi3_internal3"
3459 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3460 (compare:CC (match_operator:SI 4 "boolean_operator"
3461 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3462 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3463 (const_int 0)))
3464 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3465 (match_dup 4))]
3466 "TARGET_32BIT"
3467 "@
3468 %q4. %0,%1,%2
3469 #"
3470 [(set_attr "type" "fast_compare,compare")
3471 (set_attr "length" "4,8")])
3473 (define_split
3474 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3475 (compare:CC (match_operator:SI 4 "boolean_operator"
3476 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3477 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3478 (const_int 0)))
3479 (set (match_operand:SI 0 "gpc_reg_operand" "")
3480 (match_dup 4))]
3481 "TARGET_32BIT && reload_completed"
3482 [(set (match_dup 0) (match_dup 4))
3483 (set (match_dup 3)
3484 (compare:CC (match_dup 0)
3485 (const_int 0)))]
3486 "")
3487 \f
3488 ;; Rotate and shift insns, in all their variants. These support shifts,
3489 ;; field inserts and extracts, and various combinations thereof.
3490 (define_expand "insv"
3491 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3492 (match_operand:SI 1 "const_int_operand" "")
3493 (match_operand:SI 2 "const_int_operand" ""))
3494 (match_operand 3 "gpc_reg_operand" ""))]
3495 ""
3496 "
3497 {
3498 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3499 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3500 compiler if the address of the structure is taken later. Likewise, do
3501 not handle invalid E500 subregs. */
3502 if (GET_CODE (operands[0]) == SUBREG
3503 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD
3504 || ((TARGET_E500_DOUBLE || TARGET_SPE)
3505 && invalid_e500_subreg (operands[0], GET_MODE (operands[0])))))
3506 FAIL;
3508 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3509 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3510 else
3511 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3512 DONE;
3513 }")
3515 (define_insn "insvsi"
3516 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3517 (match_operand:SI 1 "const_int_operand" "i")
3518 (match_operand:SI 2 "const_int_operand" "i"))
3519 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3520 ""
3521 "*
3522 {
3523 int start = INTVAL (operands[2]) & 31;
3524 int size = INTVAL (operands[1]) & 31;
3526 operands[4] = GEN_INT (32 - start - size);
3527 operands[1] = GEN_INT (start + size - 1);
3528 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3529 }"
3530 [(set_attr "type" "insert_word")])
3532 (define_insn "*insvsi_internal1"
3533 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3534 (match_operand:SI 1 "const_int_operand" "i")
3535 (match_operand:SI 2 "const_int_operand" "i"))
3536 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3537 (match_operand:SI 4 "const_int_operand" "i")))]
3538 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3539 "*
3540 {
3541 int shift = INTVAL (operands[4]) & 31;
3542 int start = INTVAL (operands[2]) & 31;
3543 int size = INTVAL (operands[1]) & 31;
3545 operands[4] = GEN_INT (shift - start - size);
3546 operands[1] = GEN_INT (start + size - 1);
3547 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3548 }"
3549 [(set_attr "type" "insert_word")])
3551 (define_insn "*insvsi_internal2"
3552 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3553 (match_operand:SI 1 "const_int_operand" "i")
3554 (match_operand:SI 2 "const_int_operand" "i"))
3555 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3556 (match_operand:SI 4 "const_int_operand" "i")))]
3557 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3558 "*
3559 {
3560 int shift = INTVAL (operands[4]) & 31;
3561 int start = INTVAL (operands[2]) & 31;
3562 int size = INTVAL (operands[1]) & 31;
3564 operands[4] = GEN_INT (32 - shift - start - size);
3565 operands[1] = GEN_INT (start + size - 1);
3566 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3567 }"
3568 [(set_attr "type" "insert_word")])
3570 (define_insn "*insvsi_internal3"
3571 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3572 (match_operand:SI 1 "const_int_operand" "i")
3573 (match_operand:SI 2 "const_int_operand" "i"))
3574 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3575 (match_operand:SI 4 "const_int_operand" "i")))]
3576 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3577 "*
3578 {
3579 int shift = INTVAL (operands[4]) & 31;
3580 int start = INTVAL (operands[2]) & 31;
3581 int size = INTVAL (operands[1]) & 31;
3583 operands[4] = GEN_INT (32 - shift - start - size);
3584 operands[1] = GEN_INT (start + size - 1);
3585 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3586 }"
3587 [(set_attr "type" "insert_word")])
3589 (define_insn "*insvsi_internal4"
3590 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3591 (match_operand:SI 1 "const_int_operand" "i")
3592 (match_operand:SI 2 "const_int_operand" "i"))
3593 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3594 (match_operand:SI 4 "const_int_operand" "i")
3595 (match_operand:SI 5 "const_int_operand" "i")))]
3596 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3597 "*
3598 {
3599 int extract_start = INTVAL (operands[5]) & 31;
3600 int extract_size = INTVAL (operands[4]) & 31;
3601 int insert_start = INTVAL (operands[2]) & 31;
3602 int insert_size = INTVAL (operands[1]) & 31;
3604 /* Align extract field with insert field */
3605 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3606 operands[1] = GEN_INT (insert_start + insert_size - 1);
3607 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3608 }"
3609 [(set_attr "type" "insert_word")])
3611 ;; combine patterns for rlwimi
3612 (define_insn "*insvsi_internal5"
3613 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3614 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3615 (match_operand:SI 1 "mask_operand" "i"))
3616 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3617 (match_operand:SI 2 "const_int_operand" "i"))
3618 (match_operand:SI 5 "mask_operand" "i"))))]
3619 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3620 "*
3621 {
3622 int me = extract_ME(operands[5]);
3623 int mb = extract_MB(operands[5]);
3624 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3625 operands[2] = GEN_INT(mb);
3626 operands[1] = GEN_INT(me);
3627 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3628 }"
3629 [(set_attr "type" "insert_word")])
3631 (define_insn "*insvsi_internal6"
3632 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3633 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3634 (match_operand:SI 2 "const_int_operand" "i"))
3635 (match_operand:SI 5 "mask_operand" "i"))
3636 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0")
3637 (match_operand:SI 1 "mask_operand" "i"))))]
3638 "TARGET_POWERPC && INTVAL(operands[1]) == ~INTVAL(operands[5])"
3639 "*
3640 {
3641 int me = extract_ME(operands[5]);
3642 int mb = extract_MB(operands[5]);
3643 operands[4] = GEN_INT(32 - INTVAL(operands[2]));
3644 operands[2] = GEN_INT(mb);
3645 operands[1] = GEN_INT(me);
3646 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3647 }"
3648 [(set_attr "type" "insert_word")])
3650 (define_insn "insvdi"
3651 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3652 (match_operand:SI 1 "const_int_operand" "i")
3653 (match_operand:SI 2 "const_int_operand" "i"))
3654 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3655 "TARGET_POWERPC64"
3656 "*
3657 {
3658 int start = INTVAL (operands[2]) & 63;
3659 int size = INTVAL (operands[1]) & 63;
3661 operands[1] = GEN_INT (64 - start - size);
3662 return \"rldimi %0,%3,%H1,%H2\";
3663 }"
3664 [(set_attr "type" "insert_dword")])
3666 (define_insn "*insvdi_internal2"
3667 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3668 (match_operand:SI 1 "const_int_operand" "i")
3669 (match_operand:SI 2 "const_int_operand" "i"))
3670 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3671 (match_operand:SI 4 "const_int_operand" "i")))]
3672 "TARGET_POWERPC64
3673 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3674 "*
3675 {
3676 int shift = INTVAL (operands[4]) & 63;
3677 int start = (INTVAL (operands[2]) & 63) - 32;
3678 int size = INTVAL (operands[1]) & 63;
3680 operands[4] = GEN_INT (64 - shift - start - size);
3681 operands[2] = GEN_INT (start);
3682 operands[1] = GEN_INT (start + size - 1);
3683 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3684 }")
3686 (define_insn "*insvdi_internal3"
3687 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3688 (match_operand:SI 1 "const_int_operand" "i")
3689 (match_operand:SI 2 "const_int_operand" "i"))
3690 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r")
3691 (match_operand:SI 4 "const_int_operand" "i")))]
3692 "TARGET_POWERPC64
3693 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])"
3694 "*
3695 {
3696 int shift = INTVAL (operands[4]) & 63;
3697 int start = (INTVAL (operands[2]) & 63) - 32;
3698 int size = INTVAL (operands[1]) & 63;
3700 operands[4] = GEN_INT (64 - shift - start - size);
3701 operands[2] = GEN_INT (start);
3702 operands[1] = GEN_INT (start + size - 1);
3703 return \"rlwimi %0,%3,%h4,%h2,%h1\";
3704 }")
3706 (define_expand "extzv"
3707 [(set (match_operand 0 "gpc_reg_operand" "")
3708 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3709 (match_operand:SI 2 "const_int_operand" "")
3710 (match_operand:SI 3 "const_int_operand" "")))]
3711 ""
3712 "
3713 {
3714 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3715 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3716 compiler if the address of the structure is taken later. */
3717 if (GET_CODE (operands[0]) == SUBREG
3718 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3719 FAIL;
3721 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3722 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3723 else
3724 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3725 DONE;
3726 }")
3728 (define_insn "extzvsi"
3729 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3730 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3731 (match_operand:SI 2 "const_int_operand" "i")
3732 (match_operand:SI 3 "const_int_operand" "i")))]
3733 ""
3734 "*
3735 {
3736 int start = INTVAL (operands[3]) & 31;
3737 int size = INTVAL (operands[2]) & 31;
3739 if (start + size >= 32)
3740 operands[3] = const0_rtx;
3741 else
3742 operands[3] = GEN_INT (start + size);
3743 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3744 }")
3746 (define_insn "*extzvsi_internal1"
3747 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3748 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3749 (match_operand:SI 2 "const_int_operand" "i,i")
3750 (match_operand:SI 3 "const_int_operand" "i,i"))
3751 (const_int 0)))
3752 (clobber (match_scratch:SI 4 "=r,r"))]
3753 ""
3754 "*
3755 {
3756 int start = INTVAL (operands[3]) & 31;
3757 int size = INTVAL (operands[2]) & 31;
3759 /* Force split for non-cc0 compare. */
3760 if (which_alternative == 1)
3761 return \"#\";
3763 /* If the bit-field being tested fits in the upper or lower half of a
3764 word, it is possible to use andiu. or andil. to test it. This is
3765 useful because the condition register set-use delay is smaller for
3766 andi[ul]. than for rlinm. This doesn't work when the starting bit
3767 position is 0 because the LT and GT bits may be set wrong. */
3769 if ((start > 0 && start + size <= 16) || start >= 16)
3770 {
3771 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3772 - (1 << (16 - (start & 15) - size))));
3773 if (start < 16)
3774 return \"{andiu.|andis.} %4,%1,%3\";
3775 else
3776 return \"{andil.|andi.} %4,%1,%3\";
3777 }
3779 if (start + size >= 32)
3780 operands[3] = const0_rtx;
3781 else
3782 operands[3] = GEN_INT (start + size);
3783 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3784 }"
3785 [(set_attr "type" "delayed_compare")
3786 (set_attr "length" "4,8")])
3788 (define_split
3789 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3790 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3791 (match_operand:SI 2 "const_int_operand" "")
3792 (match_operand:SI 3 "const_int_operand" ""))
3793 (const_int 0)))
3794 (clobber (match_scratch:SI 4 ""))]
3795 "reload_completed"
3796 [(set (match_dup 4)
3797 (zero_extract:SI (match_dup 1) (match_dup 2)
3798 (match_dup 3)))
3799 (set (match_dup 0)
3800 (compare:CC (match_dup 4)
3801 (const_int 0)))]
3802 "")
3804 (define_insn "*extzvsi_internal2"
3805 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3806 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3807 (match_operand:SI 2 "const_int_operand" "i,i")
3808 (match_operand:SI 3 "const_int_operand" "i,i"))
3809 (const_int 0)))
3810 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3811 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3812 ""
3813 "*
3814 {
3815 int start = INTVAL (operands[3]) & 31;
3816 int size = INTVAL (operands[2]) & 31;
3818 /* Force split for non-cc0 compare. */
3819 if (which_alternative == 1)
3820 return \"#\";
3822 /* Since we are using the output value, we can't ignore any need for
3823 a shift. The bit-field must end at the LSB. */
3824 if (start >= 16 && start + size == 32)
3825 {
3826 operands[3] = GEN_INT ((1 << size) - 1);
3827 return \"{andil.|andi.} %0,%1,%3\";
3828 }
3830 if (start + size >= 32)
3831 operands[3] = const0_rtx;
3832 else
3833 operands[3] = GEN_INT (start + size);
3834 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3835 }"
3836 [(set_attr "type" "delayed_compare")
3837 (set_attr "length" "4,8")])
3839 (define_split
3840 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
3841 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3842 (match_operand:SI 2 "const_int_operand" "")
3843 (match_operand:SI 3 "const_int_operand" ""))
3844 (const_int 0)))
3845 (set (match_operand:SI 0 "gpc_reg_operand" "")
3846 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3847 "reload_completed"
3848 [(set (match_dup 0)
3849 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3850 (set (match_dup 4)
3851 (compare:CC (match_dup 0)
3852 (const_int 0)))]
3853 "")
3855 (define_insn "extzvdi"
3856 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3857 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3858 (match_operand:SI 2 "const_int_operand" "i")
3859 (match_operand:SI 3 "const_int_operand" "i")))]
3860 "TARGET_POWERPC64"
3861 "*
3862 {
3863 int start = INTVAL (operands[3]) & 63;
3864 int size = INTVAL (operands[2]) & 63;
3866 if (start + size >= 64)
3867 operands[3] = const0_rtx;
3868 else
3869 operands[3] = GEN_INT (start + size);
3870 operands[2] = GEN_INT (64 - size);
3871 return \"rldicl %0,%1,%3,%2\";
3872 }")
3874 (define_insn "*extzvdi_internal1"
3875 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3876 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3877 (match_operand:SI 2 "const_int_operand" "i")
3878 (match_operand:SI 3 "const_int_operand" "i"))
3879 (const_int 0)))
3880 (clobber (match_scratch:DI 4 "=r"))]
3881 "TARGET_64BIT && rs6000_gen_cell_microcode"
3882 "*
3883 {
3884 int start = INTVAL (operands[3]) & 63;
3885 int size = INTVAL (operands[2]) & 63;
3887 if (start + size >= 64)
3888 operands[3] = const0_rtx;
3889 else
3890 operands[3] = GEN_INT (start + size);
3891 operands[2] = GEN_INT (64 - size);
3892 return \"rldicl. %4,%1,%3,%2\";
3893 }"
3894 [(set_attr "type" "compare")])
3896 (define_insn "*extzvdi_internal2"
3897 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3898 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3899 (match_operand:SI 2 "const_int_operand" "i")
3900 (match_operand:SI 3 "const_int_operand" "i"))
3901 (const_int 0)))
3902 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3903 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3904 "TARGET_64BIT && rs6000_gen_cell_microcode"
3905 "*
3906 {
3907 int start = INTVAL (operands[3]) & 63;
3908 int size = INTVAL (operands[2]) & 63;
3910 if (start + size >= 64)
3911 operands[3] = const0_rtx;
3912 else
3913 operands[3] = GEN_INT (start + size);
3914 operands[2] = GEN_INT (64 - size);
3915 return \"rldicl. %0,%1,%3,%2\";
3916 }"
3917 [(set_attr "type" "compare")])
3919 (define_insn "rotlsi3"
3920 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3921 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3922 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
3923 ""
3924 "@
3925 {rlnm|rlwnm} %0,%1,%2,0xffffffff
3926 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
3927 [(set_attr "type" "var_shift_rotate,integer")])
3929 (define_insn "*rotlsi3_64"
3930 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
3931 (zero_extend:DI
3932 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3933 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
3934 "TARGET_64BIT"
3935 "@
3936 {rlnm|rlwnm} %0,%1,%2,0xffffffff
3937 {rlinm|rlwinm} %0,%1,%h2,0xffffffff"
3938 [(set_attr "type" "var_shift_rotate,integer")])
3940 (define_insn "*rotlsi3_internal2"
3941 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
3942 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3943 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3944 (const_int 0)))
3945 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
3946 ""
3947 "@
3948 {rlnm.|rlwnm.} %3,%1,%2,0xffffffff
3949 {rlinm.|rlwinm.} %3,%1,%h2,0xffffffff
3950 #
3951 #"
3952 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3953 (set_attr "length" "4,4,8,8")])
3955 (define_split
3956 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
3957 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3958 (match_operand:SI 2 "reg_or_cint_operand" ""))
3959 (const_int 0)))
3960 (clobber (match_scratch:SI 3 ""))]
3961 "reload_completed"
3962 [(set (match_dup 3)
3963 (rotate:SI (match_dup 1) (match_dup 2)))
3964 (set (match_dup 0)
3965 (compare:CC (match_dup 3)
3966 (const_int 0)))]
3967 "")
3969 (define_insn "*rotlsi3_internal3"
3970 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
3971 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
3972 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
3973 (const_int 0)))
3974 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
3975 (rotate:SI (match_dup 1) (match_dup 2)))]
3976 ""
3977 "@
3978 {rlnm.|rlwnm.} %0,%1,%2,0xffffffff
3979 {rlinm.|rlwinm.} %0,%1,%h2,0xffffffff
3980 #
3981 #"
3982 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
3983 (set_attr "length" "4,4,8,8")])
3985 (define_split
3986 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
3987 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
3988 (match_operand:SI 2 "reg_or_cint_operand" ""))
3989 (const_int 0)))
3990 (set (match_operand:SI 0 "gpc_reg_operand" "")
3991 (rotate:SI (match_dup 1) (match_dup 2)))]
3992 "reload_completed"
3993 [(set (match_dup 0)
3994 (rotate:SI (match_dup 1) (match_dup 2)))
3995 (set (match_dup 3)
3996 (compare:CC (match_dup 0)
3997 (const_int 0)))]
3998 "")
4000 (define_insn "*rotlsi3_internal4"
4001 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4002 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4003 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
4004 (match_operand:SI 3 "mask_operand" "n,n")))]
4005 ""
4006 "@
4007 {rlnm|rlwnm} %0,%1,%2,%m3,%M3
4008 {rlinm|rlwinm} %0,%1,%h2,%m3,%M3"
4009 [(set_attr "type" "var_shift_rotate,integer")])
4011 (define_insn "*rotlsi3_internal5"
4012 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4013 (compare:CC (and:SI
4014 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4015 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4016 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4017 (const_int 0)))
4018 (clobber (match_scratch:SI 4 "=r,r,r,r"))]
4019 ""
4020 "@
4021 {rlnm.|rlwnm.} %4,%1,%2,%m3,%M3
4022 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4023 #
4024 #"
4025 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4026 (set_attr "length" "4,4,8,8")])
4028 (define_split
4029 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4030 (compare:CC (and:SI
4031 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4032 (match_operand:SI 2 "reg_or_cint_operand" ""))
4033 (match_operand:SI 3 "mask_operand" ""))
4034 (const_int 0)))
4035 (clobber (match_scratch:SI 4 ""))]
4036 "reload_completed"
4037 [(set (match_dup 4)
4038 (and:SI (rotate:SI (match_dup 1)
4039 (match_dup 2))
4040 (match_dup 3)))
4041 (set (match_dup 0)
4042 (compare:CC (match_dup 4)
4043 (const_int 0)))]
4044 "")
4046 (define_insn "*rotlsi3_internal6"
4047 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
4048 (compare:CC (and:SI
4049 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4050 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4051 (match_operand:SI 3 "mask_operand" "n,n,n,n"))
4052 (const_int 0)))
4053 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4054 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4055 ""
4056 "@
4057 {rlnm.|rlwnm.} %0,%1,%2,%m3,%M3
4058 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4059 #
4060 #"
4061 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4062 (set_attr "length" "4,4,8,8")])
4064 (define_split
4065 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4066 (compare:CC (and:SI
4067 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4068 (match_operand:SI 2 "reg_or_cint_operand" ""))
4069 (match_operand:SI 3 "mask_operand" ""))
4070 (const_int 0)))
4071 (set (match_operand:SI 0 "gpc_reg_operand" "")
4072 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4073 "reload_completed"
4074 [(set (match_dup 0)
4075 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4076 (set (match_dup 4)
4077 (compare:CC (match_dup 0)
4078 (const_int 0)))]
4079 "")
4081 (define_insn "*rotlsi3_internal7"
4082 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4083 (zero_extend:SI
4084 (subreg:QI
4085 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4086 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4087 ""
4088 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff"
4089 [(set (attr "cell_micro")
4090 (if_then_else (match_operand:SI 2 "const_int_operand" "")
4091 (const_string "not")
4092 (const_string "always")))])
4094 (define_insn "*rotlsi3_internal8"
4095 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4096 (compare:CC (zero_extend:SI
4097 (subreg:QI
4098 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4099 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4100 (const_int 0)))
4101 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4102 ""
4103 "@
4104 {rlnm.|rlwnm.} %3,%1,%2,0xff
4105 {rlinm.|rlwinm.} %3,%1,%h2,0xff
4106 #
4107 #"
4108 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4109 (set_attr "length" "4,4,8,8")])
4111 (define_split
4112 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4113 (compare:CC (zero_extend:SI
4114 (subreg:QI
4115 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4116 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4117 (const_int 0)))
4118 (clobber (match_scratch:SI 3 ""))]
4119 "reload_completed"
4120 [(set (match_dup 3)
4121 (zero_extend:SI (subreg:QI
4122 (rotate:SI (match_dup 1)
4123 (match_dup 2)) 0)))
4124 (set (match_dup 0)
4125 (compare:CC (match_dup 3)
4126 (const_int 0)))]
4127 "")
4129 (define_insn "*rotlsi3_internal9"
4130 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4131 (compare:CC (zero_extend:SI
4132 (subreg:QI
4133 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4134 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4135 (const_int 0)))
4136 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4137 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4138 ""
4139 "@
4140 {rlnm.|rlwnm.} %0,%1,%2,0xff
4141 {rlinm.|rlwinm.} %0,%1,%h2,0xff
4142 #
4143 #"
4144 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4145 (set_attr "length" "4,4,8,8")])
4147 (define_split
4148 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4149 (compare:CC (zero_extend:SI
4150 (subreg:QI
4151 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4152 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4153 (const_int 0)))
4154 (set (match_operand:SI 0 "gpc_reg_operand" "")
4155 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4156 "reload_completed"
4157 [(set (match_dup 0)
4158 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4159 (set (match_dup 3)
4160 (compare:CC (match_dup 0)
4161 (const_int 0)))]
4162 "")
4164 (define_insn "*rotlsi3_internal10"
4165 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4166 (zero_extend:SI
4167 (subreg:HI
4168 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4169 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))]
4170 ""
4171 "@
4172 {rlnm|rlwnm} %0,%1,%2,0xffff
4173 {rlinm|rlwinm} %0,%1,%h2,0xffff"
4174 [(set_attr "type" "var_shift_rotate,integer")])
4177 (define_insn "*rotlsi3_internal11"
4178 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4179 (compare:CC (zero_extend:SI
4180 (subreg:HI
4181 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4182 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4183 (const_int 0)))
4184 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4185 ""
4186 "@
4187 {rlnm.|rlwnm.} %3,%1,%2,0xffff
4188 {rlinm.|rlwinm.} %3,%1,%h2,0xffff
4189 #
4190 #"
4191 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4192 (set_attr "length" "4,4,8,8")])
4194 (define_split
4195 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4196 (compare:CC (zero_extend:SI
4197 (subreg:HI
4198 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4199 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4200 (const_int 0)))
4201 (clobber (match_scratch:SI 3 ""))]
4202 "reload_completed"
4203 [(set (match_dup 3)
4204 (zero_extend:SI (subreg:HI
4205 (rotate:SI (match_dup 1)
4206 (match_dup 2)) 0)))
4207 (set (match_dup 0)
4208 (compare:CC (match_dup 3)
4209 (const_int 0)))]
4210 "")
4212 (define_insn "*rotlsi3_internal12"
4213 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4214 (compare:CC (zero_extend:SI
4215 (subreg:HI
4216 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4217 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
4218 (const_int 0)))
4219 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4220 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4221 ""
4222 "@
4223 {rlnm.|rlwnm.} %0,%1,%2,0xffff
4224 {rlinm.|rlwinm.} %0,%1,%h2,0xffff
4225 #
4226 #"
4227 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4228 (set_attr "length" "4,4,8,8")])
4230 (define_split
4231 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4232 (compare:CC (zero_extend:SI
4233 (subreg:HI
4234 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4235 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4236 (const_int 0)))
4237 (set (match_operand:SI 0 "gpc_reg_operand" "")
4238 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4239 "reload_completed"
4240 [(set (match_dup 0)
4241 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4242 (set (match_dup 3)
4243 (compare:CC (match_dup 0)
4244 (const_int 0)))]
4245 "")
4247 (define_insn "ashlsi3"
4248 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4249 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4250 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4251 ""
4252 "@
4253 {sl|slw} %0,%1,%2
4254 {sli|slwi} %0,%1,%h2"
4255 [(set_attr "type" "var_shift_rotate,shift")])
4257 (define_insn "*ashlsi3_64"
4258 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4259 (zero_extend:DI
4260 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4261 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4262 "TARGET_POWERPC64"
4263 "@
4264 {sl|slw} %0,%1,%2
4265 {sli|slwi} %0,%1,%h2"
4266 [(set_attr "type" "var_shift_rotate,shift")])
4268 (define_insn ""
4269 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4270 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4271 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4272 (const_int 0)))
4273 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4274 "TARGET_32BIT"
4275 "@
4276 {sl.|slw.} %3,%1,%2
4277 {sli.|slwi.} %3,%1,%h2
4278 #
4279 #"
4280 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4281 (set_attr "length" "4,4,8,8")])
4283 (define_split
4284 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4285 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4286 (match_operand:SI 2 "reg_or_cint_operand" ""))
4287 (const_int 0)))
4288 (clobber (match_scratch:SI 3 ""))]
4289 "TARGET_32BIT && reload_completed"
4290 [(set (match_dup 3)
4291 (ashift:SI (match_dup 1) (match_dup 2)))
4292 (set (match_dup 0)
4293 (compare:CC (match_dup 3)
4294 (const_int 0)))]
4295 "")
4297 (define_insn ""
4298 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4299 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4300 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4301 (const_int 0)))
4302 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4303 (ashift:SI (match_dup 1) (match_dup 2)))]
4304 "TARGET_32BIT"
4305 "@
4306 {sl.|slw.} %0,%1,%2
4307 {sli.|slwi.} %0,%1,%h2
4308 #
4309 #"
4310 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4311 (set_attr "length" "4,4,8,8")])
4313 (define_split
4314 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4315 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4316 (match_operand:SI 2 "reg_or_cint_operand" ""))
4317 (const_int 0)))
4318 (set (match_operand:SI 0 "gpc_reg_operand" "")
4319 (ashift:SI (match_dup 1) (match_dup 2)))]
4320 "TARGET_32BIT && reload_completed"
4321 [(set (match_dup 0)
4322 (ashift:SI (match_dup 1) (match_dup 2)))
4323 (set (match_dup 3)
4324 (compare:CC (match_dup 0)
4325 (const_int 0)))]
4326 "")
4328 (define_insn "rlwinm"
4329 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4330 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4331 (match_operand:SI 2 "const_int_operand" "i"))
4332 (match_operand:SI 3 "mask_operand" "n")))]
4333 "includes_lshift_p (operands[2], operands[3])"
4334 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4336 (define_insn ""
4337 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4338 (compare:CC
4339 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4340 (match_operand:SI 2 "const_int_operand" "i,i"))
4341 (match_operand:SI 3 "mask_operand" "n,n"))
4342 (const_int 0)))
4343 (clobber (match_scratch:SI 4 "=r,r"))]
4344 "includes_lshift_p (operands[2], operands[3])"
4345 "@
4346 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4347 #"
4348 [(set_attr "type" "delayed_compare")
4349 (set_attr "length" "4,8")])
4351 (define_split
4352 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4353 (compare:CC
4354 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4355 (match_operand:SI 2 "const_int_operand" ""))
4356 (match_operand:SI 3 "mask_operand" ""))
4357 (const_int 0)))
4358 (clobber (match_scratch:SI 4 ""))]
4359 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4360 [(set (match_dup 4)
4361 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4362 (match_dup 3)))
4363 (set (match_dup 0)
4364 (compare:CC (match_dup 4)
4365 (const_int 0)))]
4366 "")
4368 (define_insn ""
4369 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4370 (compare:CC
4371 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4372 (match_operand:SI 2 "const_int_operand" "i,i"))
4373 (match_operand:SI 3 "mask_operand" "n,n"))
4374 (const_int 0)))
4375 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4376 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4377 "includes_lshift_p (operands[2], operands[3])"
4378 "@
4379 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4380 #"
4381 [(set_attr "type" "delayed_compare")
4382 (set_attr "length" "4,8")])
4384 (define_split
4385 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4386 (compare:CC
4387 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4388 (match_operand:SI 2 "const_int_operand" ""))
4389 (match_operand:SI 3 "mask_operand" ""))
4390 (const_int 0)))
4391 (set (match_operand:SI 0 "gpc_reg_operand" "")
4392 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4393 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4394 [(set (match_dup 0)
4395 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4396 (set (match_dup 4)
4397 (compare:CC (match_dup 0)
4398 (const_int 0)))]
4399 "")
4401 (define_insn "lshrsi3"
4402 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4403 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4404 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
4405 ""
4406 "@
4407 mr %0,%1
4408 {sr|srw} %0,%1,%2
4409 {sri|srwi} %0,%1,%h2"
4410 [(set_attr "type" "integer,var_shift_rotate,shift")])
4412 (define_insn "*lshrsi3_64"
4413 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4414 (zero_extend:DI
4415 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4416 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4417 "TARGET_POWERPC64"
4418 "@
4419 {sr|srw} %0,%1,%2
4420 {sri|srwi} %0,%1,%h2"
4421 [(set_attr "type" "var_shift_rotate,shift")])
4423 (define_insn ""
4424 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4425 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4426 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4427 (const_int 0)))
4428 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
4429 "TARGET_32BIT"
4430 "@
4431 mr. %1,%1
4432 {sr.|srw.} %3,%1,%2
4433 {sri.|srwi.} %3,%1,%h2
4434 #
4435 #
4436 #"
4437 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4438 (set_attr "length" "4,4,4,8,8,8")])
4440 (define_split
4441 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4442 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4443 (match_operand:SI 2 "reg_or_cint_operand" ""))
4444 (const_int 0)))
4445 (clobber (match_scratch:SI 3 ""))]
4446 "TARGET_32BIT && reload_completed"
4447 [(set (match_dup 3)
4448 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4449 (set (match_dup 0)
4450 (compare:CC (match_dup 3)
4451 (const_int 0)))]
4452 "")
4454 (define_insn ""
4455 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4456 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4457 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
4458 (const_int 0)))
4459 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4460 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4461 "TARGET_32BIT"
4462 "@
4463 mr. %0,%1
4464 {sr.|srw.} %0,%1,%2
4465 {sri.|srwi.} %0,%1,%h2
4466 #
4467 #
4468 #"
4469 [(set_attr "type" "delayed_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4470 (set_attr "length" "4,4,4,8,8,8")])
4472 (define_split
4473 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4474 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4475 (match_operand:SI 2 "reg_or_cint_operand" ""))
4476 (const_int 0)))
4477 (set (match_operand:SI 0 "gpc_reg_operand" "")
4478 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4479 "TARGET_32BIT && reload_completed"
4480 [(set (match_dup 0)
4481 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4482 (set (match_dup 3)
4483 (compare:CC (match_dup 0)
4484 (const_int 0)))]
4485 "")
4487 (define_insn ""
4488 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4489 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4490 (match_operand:SI 2 "const_int_operand" "i"))
4491 (match_operand:SI 3 "mask_operand" "n")))]
4492 "includes_rshift_p (operands[2], operands[3])"
4493 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4495 (define_insn ""
4496 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4497 (compare:CC
4498 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4499 (match_operand:SI 2 "const_int_operand" "i,i"))
4500 (match_operand:SI 3 "mask_operand" "n,n"))
4501 (const_int 0)))
4502 (clobber (match_scratch:SI 4 "=r,r"))]
4503 "includes_rshift_p (operands[2], operands[3])"
4504 "@
4505 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4506 #"
4507 [(set_attr "type" "delayed_compare")
4508 (set_attr "length" "4,8")])
4510 (define_split
4511 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4512 (compare:CC
4513 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4514 (match_operand:SI 2 "const_int_operand" ""))
4515 (match_operand:SI 3 "mask_operand" ""))
4516 (const_int 0)))
4517 (clobber (match_scratch:SI 4 ""))]
4518 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4519 [(set (match_dup 4)
4520 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4521 (match_dup 3)))
4522 (set (match_dup 0)
4523 (compare:CC (match_dup 4)
4524 (const_int 0)))]
4525 "")
4527 (define_insn ""
4528 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4529 (compare:CC
4530 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4531 (match_operand:SI 2 "const_int_operand" "i,i"))
4532 (match_operand:SI 3 "mask_operand" "n,n"))
4533 (const_int 0)))
4534 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4535 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4536 "includes_rshift_p (operands[2], operands[3])"
4537 "@
4538 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4539 #"
4540 [(set_attr "type" "delayed_compare")
4541 (set_attr "length" "4,8")])
4543 (define_split
4544 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
4545 (compare:CC
4546 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4547 (match_operand:SI 2 "const_int_operand" ""))
4548 (match_operand:SI 3 "mask_operand" ""))
4549 (const_int 0)))
4550 (set (match_operand:SI 0 "gpc_reg_operand" "")
4551 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4552 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4553 [(set (match_dup 0)
4554 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4555 (set (match_dup 4)
4556 (compare:CC (match_dup 0)
4557 (const_int 0)))]
4558 "")
4560 (define_insn ""
4561 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4562 (zero_extend:SI
4563 (subreg:QI
4564 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4565 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4566 "includes_rshift_p (operands[2], GEN_INT (255))"
4567 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4569 (define_insn ""
4570 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4571 (compare:CC
4572 (zero_extend:SI
4573 (subreg:QI
4574 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4575 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4576 (const_int 0)))
4577 (clobber (match_scratch:SI 3 "=r,r"))]
4578 "includes_rshift_p (operands[2], GEN_INT (255))"
4579 "@
4580 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4581 #"
4582 [(set_attr "type" "delayed_compare")
4583 (set_attr "length" "4,8")])
4585 (define_split
4586 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4587 (compare:CC
4588 (zero_extend:SI
4589 (subreg:QI
4590 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4591 (match_operand:SI 2 "const_int_operand" "")) 0))
4592 (const_int 0)))
4593 (clobber (match_scratch:SI 3 ""))]
4594 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4595 [(set (match_dup 3)
4596 (zero_extend:SI (subreg:QI
4597 (lshiftrt:SI (match_dup 1)
4598 (match_dup 2)) 0)))
4599 (set (match_dup 0)
4600 (compare:CC (match_dup 3)
4601 (const_int 0)))]
4602 "")
4604 (define_insn ""
4605 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4606 (compare:CC
4607 (zero_extend:SI
4608 (subreg:QI
4609 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4610 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4611 (const_int 0)))
4612 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4613 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4614 "includes_rshift_p (operands[2], GEN_INT (255))"
4615 "@
4616 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4617 #"
4618 [(set_attr "type" "delayed_compare")
4619 (set_attr "length" "4,8")])
4621 (define_split
4622 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4623 (compare:CC
4624 (zero_extend:SI
4625 (subreg:QI
4626 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4627 (match_operand:SI 2 "const_int_operand" "")) 0))
4628 (const_int 0)))
4629 (set (match_operand:SI 0 "gpc_reg_operand" "")
4630 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4631 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4632 [(set (match_dup 0)
4633 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4634 (set (match_dup 3)
4635 (compare:CC (match_dup 0)
4636 (const_int 0)))]
4637 "")
4639 (define_insn ""
4640 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4641 (zero_extend:SI
4642 (subreg:HI
4643 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4644 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4645 "includes_rshift_p (operands[2], GEN_INT (65535))"
4646 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4648 (define_insn ""
4649 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4650 (compare:CC
4651 (zero_extend:SI
4652 (subreg:HI
4653 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4654 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4655 (const_int 0)))
4656 (clobber (match_scratch:SI 3 "=r,r"))]
4657 "includes_rshift_p (operands[2], GEN_INT (65535))"
4658 "@
4659 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4660 #"
4661 [(set_attr "type" "delayed_compare")
4662 (set_attr "length" "4,8")])
4664 (define_split
4665 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4666 (compare:CC
4667 (zero_extend:SI
4668 (subreg:HI
4669 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4670 (match_operand:SI 2 "const_int_operand" "")) 0))
4671 (const_int 0)))
4672 (clobber (match_scratch:SI 3 ""))]
4673 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4674 [(set (match_dup 3)
4675 (zero_extend:SI (subreg:HI
4676 (lshiftrt:SI (match_dup 1)
4677 (match_dup 2)) 0)))
4678 (set (match_dup 0)
4679 (compare:CC (match_dup 3)
4680 (const_int 0)))]
4681 "")
4683 (define_insn ""
4684 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4685 (compare:CC
4686 (zero_extend:SI
4687 (subreg:HI
4688 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4689 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4690 (const_int 0)))
4691 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4692 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4693 "includes_rshift_p (operands[2], GEN_INT (65535))"
4694 "@
4695 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4696 #"
4697 [(set_attr "type" "delayed_compare")
4698 (set_attr "length" "4,8")])
4700 (define_split
4701 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4702 (compare:CC
4703 (zero_extend:SI
4704 (subreg:HI
4705 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4706 (match_operand:SI 2 "const_int_operand" "")) 0))
4707 (const_int 0)))
4708 (set (match_operand:SI 0 "gpc_reg_operand" "")
4709 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4710 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4711 [(set (match_dup 0)
4712 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4713 (set (match_dup 3)
4714 (compare:CC (match_dup 0)
4715 (const_int 0)))]
4716 "")
4718 (define_insn "ashrsi3"
4719 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4720 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4721 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
4722 ""
4723 "@
4724 {sra|sraw} %0,%1,%2
4725 {srai|srawi} %0,%1,%h2"
4726 [(set_attr "type" "var_shift_rotate,shift")])
4728 (define_insn "*ashrsi3_64"
4729 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
4730 (sign_extend:DI
4731 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4732 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))]
4733 "TARGET_POWERPC64"
4734 "@
4735 {sra|sraw} %0,%1,%2
4736 {srai|srawi} %0,%1,%h2"
4737 [(set_attr "type" "var_shift_rotate,shift")])
4739 (define_insn ""
4740 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4741 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4742 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4743 (const_int 0)))
4744 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
4745 ""
4746 "@
4747 {sra.|sraw.} %3,%1,%2
4748 {srai.|srawi.} %3,%1,%h2
4749 #
4750 #"
4751 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4752 (set_attr "length" "4,4,8,8")])
4754 (define_split
4755 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
4756 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4757 (match_operand:SI 2 "reg_or_cint_operand" ""))
4758 (const_int 0)))
4759 (clobber (match_scratch:SI 3 ""))]
4760 "reload_completed"
4761 [(set (match_dup 3)
4762 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4763 (set (match_dup 0)
4764 (compare:CC (match_dup 3)
4765 (const_int 0)))]
4766 "")
4768 (define_insn ""
4769 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4770 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4771 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4772 (const_int 0)))
4773 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4774 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4775 ""
4776 "@
4777 {sra.|sraw.} %0,%1,%2
4778 {srai.|srawi.} %0,%1,%h2
4779 #
4780 #"
4781 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
4782 (set_attr "length" "4,4,8,8")])
4783 \f
4784 ;; Builtins to replace a division to generate FRE reciprocal estimate
4785 ;; instructions and the necessary fixup instructions
4786 (define_expand "recip<mode>3"
4787 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4788 (match_operand:RECIPF 1 "gpc_reg_operand" "")
4789 (match_operand:RECIPF 2 "gpc_reg_operand" "")]
4790 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)"
4791 {
4792 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false);
4793 DONE;
4794 })
4796 ;; Split to create division from FRE/FRES/etc. and fixup instead of the normal
4797 ;; hardware division. This is only done before register allocation and with
4798 ;; -ffast-math. This must appear before the divsf3/divdf3 insns.
4799 (define_split
4800 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "")
4801 (div:RECIPF (match_operand 1 "gpc_reg_operand" "")
4802 (match_operand 2 "gpc_reg_operand" "")))]
4803 "RS6000_RECIP_AUTO_RE_P (<MODE>mode)
4804 && can_create_pseudo_p () && optimize_insn_for_speed_p ()
4805 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math"
4806 [(const_int 0)]
4807 {
4808 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true);
4809 DONE;
4810 })
4812 ;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the
4813 ;; appropriate fixup.
4814 (define_expand "rsqrt<mode>2"
4815 [(match_operand:RECIPF 0 "gpc_reg_operand" "")
4816 (match_operand:RECIPF 1 "gpc_reg_operand" "")]
4817 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
4818 {
4819 rs6000_emit_swrsqrt (operands[0], operands[1]);
4820 DONE;
4821 })
4822 \f
4823 (define_split
4824 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
4825 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4826 (match_operand:SI 2 "reg_or_cint_operand" ""))
4827 (const_int 0)))
4828 (set (match_operand:SI 0 "gpc_reg_operand" "")
4829 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
4830 "reload_completed"
4831 [(set (match_dup 0)
4832 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4833 (set (match_dup 3)
4834 (compare:CC (match_dup 0)
4835 (const_int 0)))]
4836 "")
4838 ;; Floating-point insns, excluding normal data motion.
4839 ;;
4840 ;; PowerPC has a full set of single-precision floating point instructions.
4841 ;;
4842 ;; For the POWER architecture, we pretend that we have both SFmode and
4843 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
4844 ;; The only conversions we will do will be when storing to memory. In that
4845 ;; case, we will use the "frsp" instruction before storing.
4846 ;;
4847 ;; Note that when we store into a single-precision memory location, we need to
4848 ;; use the frsp insn first. If the register being stored isn't dead, we
4849 ;; need a scratch register for the frsp. But this is difficult when the store
4850 ;; is done by reload. It is not incorrect to do the frsp on the register in
4851 ;; this case, we just lose precision that we would have otherwise gotten but
4852 ;; is not guaranteed. Perhaps this should be tightened up at some point.
4854 (define_expand "extendsfdf2"
4855 [(set (match_operand:DF 0 "gpc_reg_operand" "")
4856 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))]
4857 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4858 "")
4860 (define_insn_and_split "*extendsfdf2_fpr"
4861 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d")
4862 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m")))]
4863 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4864 "@
4865 #
4866 fmr %0,%1
4867 lfs%U1%X1 %0,%1"
4868 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
4869 [(const_int 0)]
4870 {
4871 emit_note (NOTE_INSN_DELETED);
4872 DONE;
4873 }
4874 [(set_attr "type" "fp,fp,fpload")])
4876 (define_expand "truncdfsf2"
4877 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4878 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))]
4879 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
4880 "")
4882 (define_insn "*truncdfsf2_fpr"
4883 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4884 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
4885 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
4886 "frsp %0,%1"
4887 [(set_attr "type" "fp")])
4889 (define_insn "aux_truncdfsf2"
4890 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4891 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRSP))]
4892 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4893 "frsp %0,%1"
4894 [(set_attr "type" "fp")])
4896 (define_expand "negsf2"
4897 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4898 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4899 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4900 "")
4902 (define_insn "*negsf2"
4903 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4904 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4905 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4906 "fneg %0,%1"
4907 [(set_attr "type" "fp")])
4909 (define_expand "abssf2"
4910 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4911 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
4912 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4913 "")
4915 (define_insn "*abssf2"
4916 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4917 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
4918 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4919 "fabs %0,%1"
4920 [(set_attr "type" "fp")])
4922 (define_insn ""
4923 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4924 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
4925 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4926 "fnabs %0,%1"
4927 [(set_attr "type" "fp")])
4929 (define_expand "addsf3"
4930 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4931 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4932 (match_operand:SF 2 "gpc_reg_operand" "")))]
4933 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4934 "")
4936 (define_insn ""
4937 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4938 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4939 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4940 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4941 "fadds %0,%1,%2"
4942 [(set_attr "type" "fp")
4943 (set_attr "fp_type" "fp_addsub_s")])
4945 (define_insn ""
4946 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4947 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4948 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4949 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4950 "{fa|fadd} %0,%1,%2"
4951 [(set_attr "type" "fp")])
4953 (define_expand "subsf3"
4954 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4955 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
4956 (match_operand:SF 2 "gpc_reg_operand" "")))]
4957 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4958 "")
4960 (define_insn ""
4961 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4962 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4963 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4964 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4965 "fsubs %0,%1,%2"
4966 [(set_attr "type" "fp")
4967 (set_attr "fp_type" "fp_addsub_s")])
4969 (define_insn ""
4970 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4971 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
4972 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4973 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4974 "{fs|fsub} %0,%1,%2"
4975 [(set_attr "type" "fp")])
4977 (define_expand "mulsf3"
4978 [(set (match_operand:SF 0 "gpc_reg_operand" "")
4979 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
4980 (match_operand:SF 2 "gpc_reg_operand" "")))]
4981 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT"
4982 "")
4984 (define_insn ""
4985 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4986 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4987 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4988 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
4989 "fmuls %0,%1,%2"
4990 [(set_attr "type" "fp")
4991 (set_attr "fp_type" "fp_mul_s")])
4993 (define_insn ""
4994 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
4995 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
4996 (match_operand:SF 2 "gpc_reg_operand" "f")))]
4997 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
4998 "{fm|fmul} %0,%1,%2"
4999 [(set_attr "type" "dmul")])
5001 (define_expand "divsf3"
5002 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5003 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5004 (match_operand:SF 2 "gpc_reg_operand" "")))]
5005 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5006 "")
5008 (define_insn ""
5009 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5010 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5011 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5012 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5013 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5014 "fdivs %0,%1,%2"
5015 [(set_attr "type" "sdiv")])
5017 (define_insn ""
5018 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5019 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5020 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5021 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS
5022 && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5023 "{fd|fdiv} %0,%1,%2"
5024 [(set_attr "type" "ddiv")])
5026 (define_insn "fres"
5027 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5028 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5029 "TARGET_FRES"
5030 "fres %0,%1"
5031 [(set_attr "type" "fp")])
5033 ; builtin fmaf support
5034 (define_insn "*fmasf4_fpr"
5035 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5036 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5037 (match_operand:SF 2 "gpc_reg_operand" "f")
5038 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5039 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5040 {
5041 return (TARGET_POWERPC
5042 ? "fmadds %0,%1,%2,%3"
5043 : "{fma|fmadd} %0,%1,%2,%3");
5044 }
5045 [(set_attr "type" "fp")
5046 (set_attr "fp_type" "fp_maddsub_s")])
5048 (define_insn "*fmssf4_fpr"
5049 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5050 (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5051 (match_operand:SF 2 "gpc_reg_operand" "f")
5052 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5053 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5054 {
5055 return (TARGET_POWERPC
5056 ? "fmsubs %0,%1,%2,%3"
5057 : "{fms|fmsub} %0,%1,%2,%3");
5058 }
5059 [(set_attr "type" "fp")
5060 (set_attr "fp_type" "fp_maddsub_s")])
5062 (define_insn "*nfmasf4_fpr"
5063 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5064 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5065 (match_operand:SF 2 "gpc_reg_operand" "f")
5066 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5067 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5068 {
5069 return (TARGET_POWERPC
5070 ? "fnmadds %0,%1,%2,%3"
5071 : "{fnma|fnmadd} %0,%1,%2,%3");
5072 }
5073 [(set_attr "type" "fp")
5074 (set_attr "fp_type" "fp_maddsub_s")])
5076 (define_insn "*nfmssf4_fpr"
5077 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5078 (neg:SF (fma:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5079 (match_operand:SF 2 "gpc_reg_operand" "f")
5080 (neg:SF (match_operand:SF 3 "gpc_reg_operand" "f")))))]
5081 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5082 {
5083 return (TARGET_POWERPC
5084 ? "fnmsubs %0,%1,%2,%3"
5085 : "{fnms|fnmsub} %0,%1,%2,%3");
5086 }
5087 [(set_attr "type" "fp")
5088 (set_attr "fp_type" "fp_maddsub_s")])
5090 (define_expand "sqrtsf2"
5091 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5092 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5093 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU)
5094 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
5095 && !TARGET_SIMPLE_FPU"
5096 "")
5098 (define_insn ""
5099 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5100 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5101 "(TARGET_PPC_GPOPT || TARGET_XILINX_FPU) && TARGET_HARD_FLOAT
5102 && TARGET_FPRS && TARGET_SINGLE_FLOAT && !TARGET_SIMPLE_FPU"
5103 "fsqrts %0,%1"
5104 [(set_attr "type" "ssqrt")])
5106 (define_insn "*rsqrtsf_internal1"
5107 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5108 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")]
5109 UNSPEC_RSQRT))]
5110 "TARGET_FRSQRTES"
5111 "frsqrtes %0,%1"
5112 [(set_attr "type" "fp")])
5114 (define_expand "copysign<mode>3"
5115 [(set (match_dup 3)
5116 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))
5117 (set (match_dup 4)
5118 (neg:SFDF (abs:SFDF (match_dup 1))))
5119 (set (match_operand:SFDF 0 "gpc_reg_operand" "")
5120 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "")
5121 (match_dup 5))
5122 (match_dup 3)
5123 (match_dup 4)))]
5124 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
5125 && ((TARGET_PPC_GFXOPT
5126 && !HONOR_NANS (<MODE>mode)
5127 && !HONOR_SIGNED_ZEROS (<MODE>mode))
5128 || TARGET_CMPB
5129 || VECTOR_UNIT_VSX_P (<MODE>mode))"
5130 {
5131 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode))
5132 {
5133 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1],
5134 operands[2]));
5135 DONE;
5136 }
5138 operands[3] = gen_reg_rtx (<MODE>mode);
5139 operands[4] = gen_reg_rtx (<MODE>mode);
5140 operands[5] = CONST0_RTX (<MODE>mode);
5141 })
5143 ;; Use an unspec rather providing an if-then-else in RTL, to prevent the
5144 ;; compiler from optimizing -0.0
5145 (define_insn "copysign<mode>3_fcpsgn"
5146 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
5147 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")
5148 (match_operand:SFDF 2 "gpc_reg_operand" "<rreg2>")]
5149 UNSPEC_COPYSIGN))]
5150 "TARGET_CMPB && !VECTOR_UNIT_VSX_P (<MODE>mode)"
5151 "fcpsgn %0,%2,%1"
5152 [(set_attr "type" "fp")])
5154 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5155 ;; fsel instruction and some auxiliary computations. Then we just have a
5156 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5157 ;; combine.
5158 (define_expand "smaxsf3"
5159 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5160 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5161 (match_operand:SF 2 "gpc_reg_operand" ""))
5162 (match_dup 1)
5163 (match_dup 2)))]
5164 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5165 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5166 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5168 (define_expand "sminsf3"
5169 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5170 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5171 (match_operand:SF 2 "gpc_reg_operand" ""))
5172 (match_dup 2)
5173 (match_dup 1)))]
5174 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5175 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5176 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5178 (define_split
5179 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5180 (match_operator:SF 3 "min_max_operator"
5181 [(match_operand:SF 1 "gpc_reg_operand" "")
5182 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5183 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS
5184 && TARGET_SINGLE_FLOAT && !flag_trapping_math"
5185 [(const_int 0)]
5186 "
5187 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5188 operands[1], operands[2]);
5189 DONE;
5190 }")
5192 (define_expand "mov<mode>cc"
5193 [(set (match_operand:GPR 0 "gpc_reg_operand" "")
5194 (if_then_else:GPR (match_operand 1 "comparison_operator" "")
5195 (match_operand:GPR 2 "gpc_reg_operand" "")
5196 (match_operand:GPR 3 "gpc_reg_operand" "")))]
5197 "TARGET_ISEL<sel>"
5198 "
5199 {
5200 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5201 DONE;
5202 else
5203 FAIL;
5204 }")
5206 ;; We use the BASE_REGS for the isel input operands because, if rA is
5207 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5208 ;; because we may switch the operands and rB may end up being rA.
5209 ;;
5210 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5211 ;; leave out the mode in operand 4 and use one pattern, but reload can
5212 ;; change the mode underneath our feet and then gets confused trying
5213 ;; to reload the value.
5214 (define_insn "isel_signed_<mode>"
5215 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5216 (if_then_else:GPR
5217 (match_operator 1 "scc_comparison_operator"
5218 [(match_operand:CC 4 "cc_reg_operand" "y,y")
5219 (const_int 0)])
5220 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5221 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5222 "TARGET_ISEL<sel>"
5223 "*
5224 { return output_isel (operands); }"
5225 [(set_attr "type" "isel")
5226 (set_attr "length" "4")])
5228 (define_insn "isel_unsigned_<mode>"
5229 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
5230 (if_then_else:GPR
5231 (match_operator 1 "scc_comparison_operator"
5232 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y")
5233 (const_int 0)])
5234 (match_operand:GPR 2 "reg_or_cint_operand" "O,b")
5235 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))]
5236 "TARGET_ISEL<sel>"
5237 "*
5238 { return output_isel (operands); }"
5239 [(set_attr "type" "isel")
5240 (set_attr "length" "4")])
5242 ;; These patterns can be useful for combine; they let combine know that
5243 ;; isel can handle reversed comparisons so long as the operands are
5244 ;; registers.
5246 (define_insn "*isel_reversed_signed_<mode>"
5247 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5248 (if_then_else:GPR
5249 (match_operator 1 "scc_rev_comparison_operator"
5250 [(match_operand:CC 4 "cc_reg_operand" "y")
5251 (const_int 0)])
5252 (match_operand:GPR 2 "gpc_reg_operand" "b")
5253 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5254 "TARGET_ISEL<sel>"
5255 "*
5256 { return output_isel (operands); }"
5257 [(set_attr "type" "isel")
5258 (set_attr "length" "4")])
5260 (define_insn "*isel_reversed_unsigned_<mode>"
5261 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
5262 (if_then_else:GPR
5263 (match_operator 1 "scc_rev_comparison_operator"
5264 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5265 (const_int 0)])
5266 (match_operand:GPR 2 "gpc_reg_operand" "b")
5267 (match_operand:GPR 3 "gpc_reg_operand" "b")))]
5268 "TARGET_ISEL<sel>"
5269 "*
5270 { return output_isel (operands); }"
5271 [(set_attr "type" "isel")
5272 (set_attr "length" "4")])
5274 (define_expand "movsfcc"
5275 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5276 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5277 (match_operand:SF 2 "gpc_reg_operand" "")
5278 (match_operand:SF 3 "gpc_reg_operand" "")))]
5279 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5280 "
5281 {
5282 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5283 DONE;
5284 else
5285 FAIL;
5286 }")
5288 (define_insn "*fselsfsf4"
5289 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5290 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5291 (match_operand:SF 4 "zero_fp_constant" "F"))
5292 (match_operand:SF 2 "gpc_reg_operand" "f")
5293 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5294 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
5295 "fsel %0,%1,%2,%3"
5296 [(set_attr "type" "fp")])
5298 (define_insn "*fseldfsf4"
5299 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5300 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5301 (match_operand:DF 4 "zero_fp_constant" "F"))
5302 (match_operand:SF 2 "gpc_reg_operand" "f")
5303 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5304 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5305 "fsel %0,%1,%2,%3"
5306 [(set_attr "type" "fp")])
5308 (define_expand "negdf2"
5309 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5310 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5311 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5312 "")
5314 (define_insn "*negdf2_fpr"
5315 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5316 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5317 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5318 && !VECTOR_UNIT_VSX_P (DFmode)"
5319 "fneg %0,%1"
5320 [(set_attr "type" "fp")])
5322 (define_expand "absdf2"
5323 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5324 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5325 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5326 "")
5328 (define_insn "*absdf2_fpr"
5329 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5330 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5331 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5332 && !VECTOR_UNIT_VSX_P (DFmode)"
5333 "fabs %0,%1"
5334 [(set_attr "type" "fp")])
5336 (define_insn "*nabsdf2_fpr"
5337 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5338 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "d"))))]
5339 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5340 && !VECTOR_UNIT_VSX_P (DFmode)"
5341 "fnabs %0,%1"
5342 [(set_attr "type" "fp")])
5344 (define_expand "adddf3"
5345 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5346 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5347 (match_operand:DF 2 "gpc_reg_operand" "")))]
5348 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5349 "")
5351 (define_insn "*adddf3_fpr"
5352 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5353 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5354 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5355 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5356 && !VECTOR_UNIT_VSX_P (DFmode)"
5357 "{fa|fadd} %0,%1,%2"
5358 [(set_attr "type" "fp")
5359 (set_attr "fp_type" "fp_addsub_d")])
5361 (define_expand "subdf3"
5362 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5363 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "")
5364 (match_operand:DF 2 "gpc_reg_operand" "")))]
5365 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5366 "")
5368 (define_insn "*subdf3_fpr"
5369 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5370 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "d")
5371 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5372 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5373 && !VECTOR_UNIT_VSX_P (DFmode)"
5374 "{fs|fsub} %0,%1,%2"
5375 [(set_attr "type" "fp")
5376 (set_attr "fp_type" "fp_addsub_d")])
5378 (define_expand "muldf3"
5379 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5380 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "")
5381 (match_operand:DF 2 "gpc_reg_operand" "")))]
5382 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5383 "")
5385 (define_insn "*muldf3_fpr"
5386 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5387 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%d")
5388 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5389 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5390 && !VECTOR_UNIT_VSX_P (DFmode)"
5391 "{fm|fmul} %0,%1,%2"
5392 [(set_attr "type" "dmul")
5393 (set_attr "fp_type" "fp_mul_d")])
5395 (define_expand "divdf3"
5396 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5397 (div:DF (match_operand:DF 1 "gpc_reg_operand" "")
5398 (match_operand:DF 2 "gpc_reg_operand" "")))]
5399 "TARGET_HARD_FLOAT
5400 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)
5401 && !TARGET_SIMPLE_FPU"
5402 "")
5404 (define_insn "*divdf3_fpr"
5405 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5406 (div:DF (match_operand:DF 1 "gpc_reg_operand" "d")
5407 (match_operand:DF 2 "gpc_reg_operand" "d")))]
5408 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && !TARGET_SIMPLE_FPU
5409 && !VECTOR_UNIT_VSX_P (DFmode)"
5410 "{fd|fdiv} %0,%1,%2"
5411 [(set_attr "type" "ddiv")])
5413 (define_insn "*fred_fpr"
5414 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5415 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "f")] UNSPEC_FRES))]
5416 "TARGET_FRE && !VECTOR_UNIT_VSX_P (DFmode)"
5417 "fre %0,%1"
5418 [(set_attr "type" "fp")])
5420 (define_insn "*rsqrtdf_internal1"
5421 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5422 (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "d")]
5423 UNSPEC_RSQRT))]
5424 "TARGET_FRSQRTE && !VECTOR_UNIT_VSX_P (DFmode)"
5425 "frsqrte %0,%1"
5426 [(set_attr "type" "fp")])
5428 ; builtin fma support
5429 (define_insn "*fmadf4_fpr"
5430 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5431 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5432 (match_operand:DF 2 "gpc_reg_operand" "f")
5433 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5434 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5435 && VECTOR_UNIT_NONE_P (DFmode)"
5436 "{fma|fmadd} %0,%1,%2,%3"
5437 [(set_attr "type" "fp")
5438 (set_attr "fp_type" "fp_maddsub_d")])
5440 (define_insn "*fmsdf4_fpr"
5441 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5442 (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5443 (match_operand:DF 2 "gpc_reg_operand" "f")
5444 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5445 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5446 && VECTOR_UNIT_NONE_P (DFmode)"
5447 "{fms|fmsub} %0,%1,%2,%3"
5448 [(set_attr "type" "fp")
5449 (set_attr "fp_type" "fp_maddsub_d")])
5451 (define_insn "*nfmadf4_fpr"
5452 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5453 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5454 (match_operand:DF 2 "gpc_reg_operand" "f")
5455 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5456 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5457 && VECTOR_UNIT_NONE_P (DFmode)"
5458 "{fnma|fnmadd} %0,%1,%2,%3"
5459 [(set_attr "type" "fp")
5460 (set_attr "fp_type" "fp_maddsub_d")])
5462 (define_insn "*nfmsdf4_fpr"
5463 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5464 (neg:DF (fma:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5465 (match_operand:DF 2 "gpc_reg_operand" "f")
5466 (neg:DF (match_operand:DF 3 "gpc_reg_operand" "f")))))]
5467 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5468 && VECTOR_UNIT_NONE_P (DFmode)"
5469 "{fnms|fnmsub} %0,%1,%2,%3"
5470 [(set_attr "type" "fp")
5471 (set_attr "fp_type" "fp_maddsub_d")])
5473 (define_expand "sqrtdf2"
5474 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5475 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
5476 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5477 "")
5479 (define_insn "*sqrtdf2_fpr"
5480 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5481 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "d")))]
5482 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5483 && !VECTOR_UNIT_VSX_P (DFmode)"
5484 "fsqrt %0,%1"
5485 [(set_attr "type" "dsqrt")])
5487 ;; The conditional move instructions allow us to perform max and min
5488 ;; operations even when
5490 (define_expand "smaxdf3"
5491 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5492 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5493 (match_operand:DF 2 "gpc_reg_operand" ""))
5494 (match_dup 1)
5495 (match_dup 2)))]
5496 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5497 && !flag_trapping_math"
5498 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5500 (define_expand "smindf3"
5501 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5502 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5503 (match_operand:DF 2 "gpc_reg_operand" ""))
5504 (match_dup 2)
5505 (match_dup 1)))]
5506 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5507 && !flag_trapping_math"
5508 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5510 (define_split
5511 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5512 (match_operator:DF 3 "min_max_operator"
5513 [(match_operand:DF 1 "gpc_reg_operand" "")
5514 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5515 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5516 && !flag_trapping_math"
5517 [(const_int 0)]
5518 "
5519 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5520 operands[1], operands[2]);
5521 DONE;
5522 }")
5524 (define_expand "movdfcc"
5525 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5526 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5527 (match_operand:DF 2 "gpc_reg_operand" "")
5528 (match_operand:DF 3 "gpc_reg_operand" "")))]
5529 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5530 "
5531 {
5532 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5533 DONE;
5534 else
5535 FAIL;
5536 }")
5538 (define_insn "*fseldfdf4"
5539 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5540 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d")
5541 (match_operand:DF 4 "zero_fp_constant" "F"))
5542 (match_operand:DF 2 "gpc_reg_operand" "d")
5543 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5544 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5545 "fsel %0,%1,%2,%3"
5546 [(set_attr "type" "fp")])
5548 (define_insn "*fselsfdf4"
5549 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
5550 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5551 (match_operand:SF 4 "zero_fp_constant" "F"))
5552 (match_operand:DF 2 "gpc_reg_operand" "d")
5553 (match_operand:DF 3 "gpc_reg_operand" "d")))]
5554 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT"
5555 "fsel %0,%1,%2,%3"
5556 [(set_attr "type" "fp")])
5557 \f
5558 ;; Conversions to and from floating-point.
5560 ; We don't define lfiwax/lfiwzx with the normal definition, because we
5561 ; don't want to support putting SImode in FPR registers.
5562 (define_insn "lfiwax"
5563 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5564 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
5565 UNSPEC_LFIWAX))]
5566 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX"
5567 "lfiwax %0,%y1"
5568 [(set_attr "type" "fpload")])
5570 ; This split must be run before register allocation because it allocates the
5571 ; memory slot that is needed to move values to/from the FPR. We don't allocate
5572 ; it earlier to allow for the combiner to merge insns together where it might
5573 ; not be needed and also in case the insns are deleted as dead code.
5575 (define_insn_and_split "floatsi<mode>2_lfiwax"
5576 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5577 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5578 (clobber (match_scratch:DI 2 "=d"))]
5579 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5580 && <SI_CONVERT_FP> && can_create_pseudo_p ()"
5581 "#"
5582 ""
5583 [(pc)]
5584 "
5585 {
5586 rtx dest = operands[0];
5587 rtx src = operands[1];
5588 rtx tmp;
5590 if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
5591 tmp = convert_to_mode (DImode, src, false);
5592 else
5593 {
5594 tmp = operands[2];
5595 if (GET_CODE (tmp) == SCRATCH)
5596 tmp = gen_reg_rtx (DImode);
5597 if (MEM_P (src))
5598 {
5599 src = rs6000_address_for_fpconvert (src);
5600 emit_insn (gen_lfiwax (tmp, src));
5601 }
5602 else
5603 {
5604 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5605 emit_move_insn (stack, src);
5606 emit_insn (gen_lfiwax (tmp, stack));
5607 }
5608 }
5609 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5610 DONE;
5611 }"
5612 [(set_attr "length" "12")
5613 (set_attr "type" "fpload")])
5615 (define_insn_and_split "floatsi<mode>2_lfiwax_mem"
5616 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5617 (float:SFDF
5618 (sign_extend:DI
5619 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5620 (clobber (match_scratch:DI 2 "=0,d"))]
5621 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
5622 && <SI_CONVERT_FP>"
5623 "#"
5624 ""
5625 [(pc)]
5626 "
5627 {
5628 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5629 if (GET_CODE (operands[2]) == SCRATCH)
5630 operands[2] = gen_reg_rtx (DImode);
5631 emit_insn (gen_lfiwax (operands[2], operands[1]));
5632 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5633 DONE;
5634 }"
5635 [(set_attr "length" "8")
5636 (set_attr "type" "fpload")])
5638 (define_insn "lfiwzx"
5639 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
5640 (unspec:DI [(match_operand:SI 1 "indexed_or_indirect_operand" "Z")]
5641 UNSPEC_LFIWZX))]
5642 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX"
5643 "lfiwzx %0,%y1"
5644 [(set_attr "type" "fpload")])
5646 (define_insn_and_split "floatunssi<mode>2_lfiwzx"
5647 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
5648 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
5649 (clobber (match_scratch:DI 2 "=d"))]
5650 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5651 && <SI_CONVERT_FP>"
5652 "#"
5653 ""
5654 [(pc)]
5655 "
5656 {
5657 rtx dest = operands[0];
5658 rtx src = operands[1];
5659 rtx tmp;
5661 if (!MEM_P (src) && TARGET_MFPGPR && TARGET_POWERPC64)
5662 tmp = convert_to_mode (DImode, src, true);
5663 else
5664 {
5665 tmp = operands[2];
5666 if (GET_CODE (tmp) == SCRATCH)
5667 tmp = gen_reg_rtx (DImode);
5668 if (MEM_P (src))
5669 {
5670 src = rs6000_address_for_fpconvert (src);
5671 emit_insn (gen_lfiwzx (tmp, src));
5672 }
5673 else
5674 {
5675 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5676 emit_move_insn (stack, src);
5677 emit_insn (gen_lfiwzx (tmp, stack));
5678 }
5679 }
5680 emit_insn (gen_floatdi<mode>2 (dest, tmp));
5681 DONE;
5682 }"
5683 [(set_attr "length" "12")
5684 (set_attr "type" "fpload")])
5686 (define_insn_and_split "floatunssi<mode>2_lfiwzx_mem"
5687 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>")
5688 (unsigned_float:SFDF
5689 (zero_extend:DI
5690 (match_operand:SI 1 "memory_operand" "Z,Z"))))
5691 (clobber (match_scratch:DI 2 "=0,d"))]
5692 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
5693 && <SI_CONVERT_FP>"
5694 "#"
5695 ""
5696 [(pc)]
5697 "
5698 {
5699 operands[1] = rs6000_address_for_fpconvert (operands[1]);
5700 if (GET_CODE (operands[2]) == SCRATCH)
5701 operands[2] = gen_reg_rtx (DImode);
5702 emit_insn (gen_lfiwzx (operands[2], operands[1]));
5703 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2]));
5704 DONE;
5705 }"
5706 [(set_attr "length" "8")
5707 (set_attr "type" "fpload")])
5709 ; For each of these conversions, there is a define_expand, a define_insn
5710 ; with a '#' template, and a define_split (with C code). The idea is
5711 ; to allow constant folding with the template of the define_insn,
5712 ; then to have the insns split later (between sched1 and final).
5714 (define_expand "floatsidf2"
5715 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5716 (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5717 (use (match_dup 2))
5718 (use (match_dup 3))
5719 (clobber (match_dup 4))
5720 (clobber (match_dup 5))
5721 (clobber (match_dup 6))])]
5722 "TARGET_HARD_FLOAT
5723 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5724 "
5725 {
5726 if (TARGET_E500_DOUBLE)
5727 {
5728 if (!REG_P (operands[1]))
5729 operands[1] = force_reg (SImode, operands[1]);
5730 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
5731 DONE;
5732 }
5733 else if (TARGET_LFIWAX && TARGET_FCFID)
5734 {
5735 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1]));
5736 DONE;
5737 }
5738 else if (TARGET_FCFID)
5739 {
5740 rtx dreg = operands[1];
5741 if (!REG_P (dreg))
5742 dreg = force_reg (SImode, dreg);
5743 dreg = convert_to_mode (DImode, dreg, false);
5744 emit_insn (gen_floatdidf2 (operands[0], dreg));
5745 DONE;
5746 }
5748 if (!REG_P (operands[1]))
5749 operands[1] = force_reg (SImode, operands[1]);
5750 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5751 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5752 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5753 operands[5] = gen_reg_rtx (DFmode);
5754 operands[6] = gen_reg_rtx (SImode);
5755 }")
5757 (define_insn_and_split "*floatsidf2_internal"
5758 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5759 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5760 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5761 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5762 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5763 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))
5764 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))]
5765 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5766 "#"
5767 ""
5768 [(pc)]
5769 "
5770 {
5771 rtx lowword, highword;
5772 gcc_assert (MEM_P (operands[4]));
5773 highword = adjust_address (operands[4], SImode, 0);
5774 lowword = adjust_address (operands[4], SImode, 4);
5775 if (! WORDS_BIG_ENDIAN)
5776 {
5777 rtx tmp;
5778 tmp = highword; highword = lowword; lowword = tmp;
5779 }
5781 emit_insn (gen_xorsi3 (operands[6], operands[1],
5782 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5783 emit_move_insn (lowword, operands[6]);
5784 emit_move_insn (highword, operands[2]);
5785 emit_move_insn (operands[5], operands[4]);
5786 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5787 DONE;
5788 }"
5789 [(set_attr "length" "24")
5790 (set_attr "type" "fp")])
5792 ;; If we don't have a direct conversion to single precision, don't enable this
5793 ;; conversion for 32-bit without fast math, because we don't have the insn to
5794 ;; generate the fixup swizzle to avoid double rounding problems.
5795 (define_expand "floatunssisf2"
5796 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5797 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
5798 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
5799 && (!TARGET_FPRS
5800 || (TARGET_FPRS
5801 && ((TARGET_FCFIDUS && TARGET_LFIWZX)
5802 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
5803 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
5804 "
5805 {
5806 if (!TARGET_FPRS)
5807 {
5808 if (!REG_P (operands[1]))
5809 operands[1] = force_reg (SImode, operands[1]);
5810 }
5811 else if (TARGET_LFIWZX && TARGET_FCFIDUS)
5812 {
5813 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1]));
5814 DONE;
5815 }
5816 else
5817 {
5818 rtx dreg = operands[1];
5819 if (!REG_P (dreg))
5820 dreg = force_reg (SImode, dreg);
5821 dreg = convert_to_mode (DImode, dreg, true);
5822 emit_insn (gen_floatdisf2 (operands[0], dreg));
5823 DONE;
5824 }
5825 }")
5827 (define_expand "floatunssidf2"
5828 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5829 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" "")))
5830 (use (match_dup 2))
5831 (use (match_dup 3))
5832 (clobber (match_dup 4))
5833 (clobber (match_dup 5))])]
5834 "TARGET_HARD_FLOAT
5835 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)"
5836 "
5837 {
5838 if (TARGET_E500_DOUBLE)
5839 {
5840 if (!REG_P (operands[1]))
5841 operands[1] = force_reg (SImode, operands[1]);
5842 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
5843 DONE;
5844 }
5845 else if (TARGET_LFIWZX && TARGET_FCFID)
5846 {
5847 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1]));
5848 DONE;
5849 }
5850 else if (TARGET_FCFID)
5851 {
5852 rtx dreg = operands[1];
5853 if (!REG_P (dreg))
5854 dreg = force_reg (SImode, dreg);
5855 dreg = convert_to_mode (DImode, dreg, true);
5856 emit_insn (gen_floatdidf2 (operands[0], dreg));
5857 DONE;
5858 }
5860 if (!REG_P (operands[1]))
5861 operands[1] = force_reg (SImode, operands[1]);
5862 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5863 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5864 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false);
5865 operands[5] = gen_reg_rtx (DFmode);
5866 }")
5868 (define_insn_and_split "*floatunssidf2_internal"
5869 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d")
5870 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5871 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5872 (use (match_operand:DF 3 "gpc_reg_operand" "d"))
5873 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o"))
5874 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))]
5875 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5876 && !(TARGET_FCFID && TARGET_POWERPC64)"
5877 "#"
5878 ""
5879 [(pc)]
5880 "
5881 {
5882 rtx lowword, highword;
5883 gcc_assert (MEM_P (operands[4]));
5884 highword = adjust_address (operands[4], SImode, 0);
5885 lowword = adjust_address (operands[4], SImode, 4);
5886 if (! WORDS_BIG_ENDIAN)
5887 {
5888 rtx tmp;
5889 tmp = highword; highword = lowword; lowword = tmp;
5890 }
5892 emit_move_insn (lowword, operands[1]);
5893 emit_move_insn (highword, operands[2]);
5894 emit_move_insn (operands[5], operands[4]);
5895 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5896 DONE;
5897 }"
5898 [(set_attr "length" "20")
5899 (set_attr "type" "fp")])
5901 (define_expand "fix_trunc<mode>si2"
5902 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5903 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5904 "TARGET_POWERPC && TARGET_HARD_FLOAT
5905 && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)"
5906 "
5907 {
5908 if (!<E500_CONVERT>)
5909 {
5910 rtx tmp, stack;
5912 if (TARGET_STFIWX)
5913 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1]));
5914 else
5915 {
5916 tmp = gen_reg_rtx (DImode);
5917 stack = rs6000_allocate_stack_temp (DImode, true, false);
5918 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1],
5919 tmp, stack));
5920 }
5921 DONE;
5922 }
5923 }")
5925 ; Like the convert to float patterns, this insn must be split before
5926 ; register allocation so that it can allocate the memory slot if it
5927 ; needed
5928 (define_insn_and_split "fix_trunc<mode>si2_stfiwx"
5929 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
5930 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
5931 (clobber (match_scratch:DI 2 "=d"))]
5932 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
5933 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT)
5934 && TARGET_STFIWX && can_create_pseudo_p ()"
5935 "#"
5936 ""
5937 [(pc)]
5938 {
5939 rtx dest = operands[0];
5940 rtx src = operands[1];
5941 rtx tmp = operands[2];
5943 if (GET_CODE (tmp) == SCRATCH)
5944 tmp = gen_reg_rtx (DImode);
5946 emit_insn (gen_fctiwz_<mode> (tmp, src));
5947 if (MEM_P (dest))
5948 {
5949 dest = rs6000_address_for_fpconvert (dest);
5950 emit_insn (gen_stfiwx (dest, tmp));
5951 DONE;
5952 }
5953 else if (TARGET_MFPGPR && TARGET_POWERPC64)
5954 {
5955 dest = gen_lowpart (DImode, dest);
5956 emit_move_insn (dest, tmp);
5957 DONE;
5958 }
5959 else
5960 {
5961 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
5962 emit_insn (gen_stfiwx (stack, tmp));
5963 emit_move_insn (dest, stack);
5964 DONE;
5965 }
5966 }
5967 [(set_attr "length" "12")
5968 (set_attr "type" "fp")])
5970 (define_insn_and_split "fix_trunc<mode>si2_internal"
5971 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r")
5972 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>")))
5973 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d"))
5974 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))]
5975 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
5976 "#"
5977 ""
5978 [(pc)]
5979 "
5980 {
5981 rtx lowword;
5982 gcc_assert (MEM_P (operands[3]));
5983 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
5985 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1]));
5986 emit_move_insn (operands[3], operands[2]);
5987 emit_move_insn (operands[0], lowword);
5988 DONE;
5989 }"
5990 [(set_attr "length" "16")
5991 (set_attr "type" "fp")])
5993 (define_expand "fix_trunc<mode>di2"
5994 [(set (match_operand:DI 0 "gpc_reg_operand" "")
5995 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
5996 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
5997 && TARGET_FCFID"
5998 "")
6000 (define_insn "*fix_trunc<mode>di2_fctidz"
6001 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6002 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6003 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6004 && TARGET_FCFID && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6005 "fctidz %0,%1"
6006 [(set_attr "type" "fp")])
6008 (define_expand "fixuns_trunc<mode>si2"
6009 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6010 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))]
6011 "TARGET_HARD_FLOAT
6012 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX)
6013 || <E500_CONVERT>)"
6014 "
6015 {
6016 if (!<E500_CONVERT>)
6017 {
6018 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1]));
6019 DONE;
6020 }
6021 }")
6023 (define_insn_and_split "fixuns_trunc<mode>si2_stfiwx"
6024 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
6025 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))
6026 (clobber (match_scratch:DI 2 "=d"))]
6027 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ
6028 && TARGET_STFIWX && can_create_pseudo_p ()"
6029 "#"
6030 ""
6031 [(pc)]
6032 {
6033 rtx dest = operands[0];
6034 rtx src = operands[1];
6035 rtx tmp = operands[2];
6037 if (GET_CODE (tmp) == SCRATCH)
6038 tmp = gen_reg_rtx (DImode);
6040 emit_insn (gen_fctiwuz_<mode> (tmp, src));
6041 if (MEM_P (dest))
6042 {
6043 dest = rs6000_address_for_fpconvert (dest);
6044 emit_insn (gen_stfiwx (dest, tmp));
6045 DONE;
6046 }
6047 else if (TARGET_MFPGPR && TARGET_POWERPC64)
6048 {
6049 dest = gen_lowpart (DImode, dest);
6050 emit_move_insn (dest, tmp);
6051 DONE;
6052 }
6053 else
6054 {
6055 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6056 emit_insn (gen_stfiwx (stack, tmp));
6057 emit_move_insn (dest, stack);
6058 DONE;
6059 }
6060 }
6061 [(set_attr "length" "12")
6062 (set_attr "type" "fp")])
6064 (define_expand "fixuns_trunc<mode>di2"
6065 [(set (match_operand:DI 0 "register_operand" "")
6066 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))]
6067 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))"
6068 "")
6070 (define_insn "*fixuns_trunc<mode>di2_fctiduz"
6071 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6072 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))]
6073 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6074 && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6075 "fctiduz %0,%1"
6076 [(set_attr "type" "fp")])
6078 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ))
6079 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
6080 ; because the first makes it clear that operand 0 is not live
6081 ; before the instruction.
6082 (define_insn "fctiwz_<mode>"
6083 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6084 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))]
6085 UNSPEC_FCTIWZ))]
6086 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
6087 "{fcirz|fctiwz} %0,%1"
6088 [(set_attr "type" "fp")])
6090 (define_insn "fctiwuz_<mode>"
6091 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6092 (unspec:DI [(unsigned_fix:SI
6093 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>"))]
6094 UNSPEC_FCTIWUZ))]
6095 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
6096 "fctiwuz %0,%1"
6097 [(set_attr "type" "fp")])
6099 ;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since
6100 ;; since the friz instruction does not truncate the value if the floating
6101 ;; point value is < LONG_MIN or > LONG_MAX.
6102 (define_insn "*friz"
6103 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6104 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))]
6105 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND
6106 && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations
6107 && !flag_trapping_math && TARGET_FRIZ"
6108 "friz %0,%1"
6109 [(set_attr "type" "fp")])
6111 ;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a
6112 ;; load to properly sign extend the value, but at least doing a store, load
6113 ;; into a GPR to sign extend, a store from the GPR and a load back into the FPR
6114 ;; if we have 32-bit memory ops
6115 (define_insn_and_split "*round32<mode>2_fprs"
6116 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6117 (float:SFDF
6118 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6119 (clobber (match_scratch:DI 2 "=d"))
6120 (clobber (match_scratch:DI 3 "=d"))]
6121 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6122 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID
6123 && can_create_pseudo_p ()"
6124 "#"
6125 ""
6126 [(pc)]
6127 {
6128 rtx dest = operands[0];
6129 rtx src = operands[1];
6130 rtx tmp1 = operands[2];
6131 rtx tmp2 = operands[3];
6132 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6134 if (GET_CODE (tmp1) == SCRATCH)
6135 tmp1 = gen_reg_rtx (DImode);
6136 if (GET_CODE (tmp2) == SCRATCH)
6137 tmp2 = gen_reg_rtx (DImode);
6139 emit_insn (gen_fctiwz_<mode> (tmp1, src));
6140 emit_insn (gen_stfiwx (stack, tmp1));
6141 emit_insn (gen_lfiwax (tmp2, stack));
6142 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6143 DONE;
6144 }
6145 [(set_attr "type" "fpload")
6146 (set_attr "length" "16")])
6148 (define_insn_and_split "*roundu32<mode>2_fprs"
6149 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d")
6150 (unsigned_float:SFDF
6151 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))))
6152 (clobber (match_scratch:DI 2 "=d"))
6153 (clobber (match_scratch:DI 3 "=d"))]
6154 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
6155 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU
6156 && can_create_pseudo_p ()"
6157 "#"
6158 ""
6159 [(pc)]
6160 {
6161 rtx dest = operands[0];
6162 rtx src = operands[1];
6163 rtx tmp1 = operands[2];
6164 rtx tmp2 = operands[3];
6165 rtx stack = rs6000_allocate_stack_temp (SImode, false, true);
6167 if (GET_CODE (tmp1) == SCRATCH)
6168 tmp1 = gen_reg_rtx (DImode);
6169 if (GET_CODE (tmp2) == SCRATCH)
6170 tmp2 = gen_reg_rtx (DImode);
6172 emit_insn (gen_fctiwuz_<mode> (tmp1, src));
6173 emit_insn (gen_stfiwx (stack, tmp1));
6174 emit_insn (gen_lfiwzx (tmp2, stack));
6175 emit_insn (gen_floatdi<mode>2 (dest, tmp2));
6176 DONE;
6177 }
6178 [(set_attr "type" "fpload")
6179 (set_attr "length" "16")])
6181 ;; No VSX equivalent to fctid
6182 (define_insn "lrint<mode>di2"
6183 [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
6184 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6185 UNSPEC_FCTID))]
6186 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
6187 "fctid %0,%1"
6188 [(set_attr "type" "fp")])
6190 (define_expand "btrunc<mode>2"
6191 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
6192 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
6193 UNSPEC_FRIZ))]
6194 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
6195 "")
6197 (define_insn "*btrunc<mode>2_fpr"
6198 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6199 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6200 UNSPEC_FRIZ))]
6201 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
6202 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6203 "friz %0,%1"
6204 [(set_attr "type" "fp")])
6206 (define_expand "ceil<mode>2"
6207 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
6208 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
6209 UNSPEC_FRIP))]
6210 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
6211 "")
6213 (define_insn "*ceil<mode>2_fpr"
6214 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6215 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6216 UNSPEC_FRIP))]
6217 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
6218 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6219 "frip %0,%1"
6220 [(set_attr "type" "fp")])
6222 (define_expand "floor<mode>2"
6223 [(set (match_operand:SFDF 0 "gpc_reg_operand" "")
6224 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
6225 UNSPEC_FRIM))]
6226 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
6227 "")
6229 (define_insn "*floor<mode>2_fpr"
6230 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6231 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6232 UNSPEC_FRIM))]
6233 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>
6234 && !VECTOR_UNIT_VSX_P (<MODE>mode)"
6235 "frim %0,%1"
6236 [(set_attr "type" "fp")])
6238 ;; No VSX equivalent to frin
6239 (define_insn "round<mode>2"
6240 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>")
6241 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
6242 UNSPEC_FRIN))]
6243 "TARGET_FPRND && TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT>"
6244 "frin %0,%1"
6245 [(set_attr "type" "fp")])
6247 ; An UNSPEC is used so we don't have to support SImode in FP registers.
6248 (define_insn "stfiwx"
6249 [(set (match_operand:SI 0 "memory_operand" "=Z")
6250 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")]
6251 UNSPEC_STFIWX))]
6252 "TARGET_PPC_GFXOPT"
6253 "stfiwx %1,%y0"
6254 [(set_attr "type" "fpstore")])
6256 ;; If we don't have a direct conversion to single precision, don't enable this
6257 ;; conversion for 32-bit without fast math, because we don't have the insn to
6258 ;; generate the fixup swizzle to avoid double rounding problems.
6259 (define_expand "floatsisf2"
6260 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6261 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
6262 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT
6263 && (!TARGET_FPRS
6264 || (TARGET_FPRS
6265 && ((TARGET_FCFIDS && TARGET_LFIWAX)
6266 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID
6267 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))"
6268 "
6269 {
6270 if (!TARGET_FPRS)
6271 {
6272 if (!REG_P (operands[1]))
6273 operands[1] = force_reg (SImode, operands[1]);
6274 }
6275 else if (TARGET_FCFIDS && TARGET_LFIWAX)
6276 {
6277 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1]));
6278 DONE;
6279 }
6280 else if (TARGET_FCFID && TARGET_LFIWAX)
6281 {
6282 rtx dfreg = gen_reg_rtx (DFmode);
6283 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1]));
6284 emit_insn (gen_truncdfsf2 (operands[0], dfreg));
6285 DONE;
6286 }
6287 else
6288 {
6289 rtx dreg = operands[1];
6290 if (!REG_P (dreg))
6291 dreg = force_reg (SImode, dreg);
6292 dreg = convert_to_mode (DImode, dreg, false);
6293 emit_insn (gen_floatdisf2 (operands[0], dreg));
6294 DONE;
6295 }
6296 }")
6298 (define_expand "floatdidf2"
6299 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6300 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))]
6301 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS"
6302 "")
6304 (define_insn "*floatdidf2_fpr"
6305 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6306 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6307 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS
6308 && !VECTOR_UNIT_VSX_P (DFmode)"
6309 "fcfid %0,%1"
6310 [(set_attr "type" "fp")])
6312 ; Allow the combiner to merge source memory operands to the conversion so that
6313 ; the optimizer/register allocator doesn't try to load the value too early in a
6314 ; GPR and then use store/load to move it to a FPR and suffer from a store-load
6315 ; hit. We will split after reload to avoid the trip through the GPRs
6317 (define_insn_and_split "*floatdidf2_mem"
6318 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6319 (float:DF (match_operand:DI 1 "memory_operand" "m")))
6320 (clobber (match_scratch:DI 2 "=d"))]
6321 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID"
6322 "#"
6323 "&& reload_completed"
6324 [(set (match_dup 2) (match_dup 1))
6325 (set (match_dup 0) (float:DF (match_dup 2)))]
6326 ""
6327 [(set_attr "length" "8")
6328 (set_attr "type" "fpload")])
6330 (define_expand "floatunsdidf2"
6331 [(set (match_operand:DF 0 "gpc_reg_operand" "")
6332 (unsigned_float:DF
6333 (match_operand:DI 1 "gpc_reg_operand" "")))]
6334 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6335 "")
6337 (define_insn "*floatunsdidf2_fcfidu"
6338 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6339 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6340 "TARGET_HARD_FLOAT && TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)"
6341 "fcfidu %0,%1"
6342 [(set_attr "type" "fp")
6343 (set_attr "length" "4")])
6345 (define_insn_and_split "*floatunsdidf2_mem"
6346 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
6347 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m")))
6348 (clobber (match_scratch:DI 2 "=d"))]
6349 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
6350 "#"
6351 "&& reload_completed"
6352 [(set (match_dup 2) (match_dup 1))
6353 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))]
6354 ""
6355 [(set_attr "length" "8")
6356 (set_attr "type" "fpload")])
6358 (define_expand "floatdisf2"
6359 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6360 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6361 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6362 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)"
6363 "
6364 {
6365 if (!TARGET_FCFIDS)
6366 {
6367 rtx val = operands[1];
6368 if (!flag_unsafe_math_optimizations)
6369 {
6370 rtx label = gen_label_rtx ();
6371 val = gen_reg_rtx (DImode);
6372 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label));
6373 emit_label (label);
6374 }
6375 emit_insn (gen_floatdisf2_internal1 (operands[0], val));
6376 DONE;
6377 }
6378 }")
6380 (define_insn "floatdisf2_fcfids"
6381 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6382 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6383 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6384 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6385 "fcfids %0,%1"
6386 [(set_attr "type" "fp")])
6388 (define_insn_and_split "*floatdisf2_mem"
6389 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6390 (float:SF (match_operand:DI 1 "memory_operand" "m")))
6391 (clobber (match_scratch:DI 2 "=f"))]
6392 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6393 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS"
6394 "#"
6395 "&& reload_completed"
6396 [(pc)]
6397 "
6398 {
6399 emit_move_insn (operands[2], operands[1]);
6400 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2]));
6401 DONE;
6402 }"
6403 [(set_attr "length" "8")])
6405 ;; This is not IEEE compliant if rounding mode is "round to nearest".
6406 ;; If the DI->DF conversion is inexact, then it's possible to suffer
6407 ;; from double rounding.
6408 ;; Instead of creating a new cpu type for two FP operations, just use fp
6409 (define_insn_and_split "floatdisf2_internal1"
6410 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6411 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))
6412 (clobber (match_scratch:DF 2 "=d"))]
6413 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6414 "#"
6415 "&& reload_completed"
6416 [(set (match_dup 2)
6417 (float:DF (match_dup 1)))
6418 (set (match_dup 0)
6419 (float_truncate:SF (match_dup 2)))]
6420 ""
6421 [(set_attr "length" "8")
6422 (set_attr "type" "fp")])
6424 ;; Twiddles bits to avoid double rounding.
6425 ;; Bits that might be truncated when converting to DFmode are replaced
6426 ;; by a bit that won't be lost at that stage, but is below the SFmode
6427 ;; rounding position.
6428 (define_expand "floatdisf2_internal2"
6429 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "")
6430 (const_int 53)))
6431 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1)
6432 (const_int 2047)))
6433 (clobber (scratch:CC))])
6434 (set (match_dup 3) (plus:DI (match_dup 3)
6435 (const_int 1)))
6436 (set (match_dup 0) (plus:DI (match_dup 0)
6437 (const_int 2047)))
6438 (set (match_dup 4) (compare:CCUNS (match_dup 3)
6439 (const_int 2)))
6440 (set (match_dup 0) (ior:DI (match_dup 0)
6441 (match_dup 1)))
6442 (parallel [(set (match_dup 0) (and:DI (match_dup 0)
6443 (const_int -2048)))
6444 (clobber (scratch:CC))])
6445 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0))
6446 (label_ref (match_operand:DI 2 "" ""))
6447 (pc)))
6448 (set (match_dup 0) (match_dup 1))]
6449 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
6450 "
6451 {
6452 operands[3] = gen_reg_rtx (DImode);
6453 operands[4] = gen_reg_rtx (CCUNSmode);
6454 }")
6456 (define_expand "floatunsdisf2"
6457 [(set (match_operand:SF 0 "gpc_reg_operand" "")
6458 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
6459 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6460 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6461 "")
6463 (define_insn "floatunsdisf2_fcfidus"
6464 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6465 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))]
6466 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6467 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6468 "fcfidus %0,%1"
6469 [(set_attr "type" "fp")])
6471 (define_insn_and_split "*floatunsdisf2_mem"
6472 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
6473 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m")))
6474 (clobber (match_scratch:DI 2 "=f"))]
6475 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
6476 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS"
6477 "#"
6478 "&& reload_completed"
6479 [(pc)]
6480 "
6481 {
6482 emit_move_insn (operands[2], operands[1]);
6483 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2]));
6484 DONE;
6485 }"
6486 [(set_attr "length" "8")
6487 (set_attr "type" "fpload")])
6488 \f
6489 ;; Define the DImode operations that can be done in a small number
6490 ;; of instructions. The & constraints are to prevent the register
6491 ;; allocator from allocating registers that overlap with the inputs
6492 ;; (for example, having an input in 7,8 and an output in 6,7). We
6493 ;; also allow for the output being the same as one of the inputs.
6495 (define_insn "*adddi3_noppc64"
6496 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6497 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6498 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6499 "! TARGET_POWERPC64"
6500 "*
6501 {
6502 if (WORDS_BIG_ENDIAN)
6503 return (GET_CODE (operands[2])) != CONST_INT
6504 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6505 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6506 else
6507 return (GET_CODE (operands[2])) != CONST_INT
6508 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6509 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6510 }"
6511 [(set_attr "type" "two")
6512 (set_attr "length" "8")])
6514 (define_insn "*subdi3_noppc64"
6515 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6516 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6517 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6518 "! TARGET_POWERPC64"
6519 "*
6520 {
6521 if (WORDS_BIG_ENDIAN)
6522 return (GET_CODE (operands[1]) != CONST_INT)
6523 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6524 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6525 else
6526 return (GET_CODE (operands[1]) != CONST_INT)
6527 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6528 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6529 }"
6530 [(set_attr "type" "two")
6531 (set_attr "length" "8")])
6533 (define_insn "*negdi2_noppc64"
6534 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6535 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6536 "! TARGET_POWERPC64"
6537 "*
6538 {
6539 return (WORDS_BIG_ENDIAN)
6540 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6541 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6542 }"
6543 [(set_attr "type" "two")
6544 (set_attr "length" "8")])
6546 (define_expand "mulsidi3"
6547 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6548 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6549 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6550 "! TARGET_POWERPC64"
6551 "
6552 {
6553 if (! TARGET_POWERPC)
6554 {
6555 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6556 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6557 emit_insn (gen_mull_call ());
6558 if (WORDS_BIG_ENDIAN)
6559 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6560 else
6561 {
6562 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6563 gen_rtx_REG (SImode, 3));
6564 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6565 gen_rtx_REG (SImode, 4));
6566 }
6567 DONE;
6568 }
6569 }")
6571 (define_insn "*mulsidi3_no_mq"
6572 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6573 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6574 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6575 "TARGET_POWERPC && ! TARGET_POWERPC64"
6576 "*
6577 {
6578 return (WORDS_BIG_ENDIAN)
6579 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6580 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6581 }"
6582 [(set_attr "type" "imul")
6583 (set_attr "length" "8")])
6585 (define_split
6586 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6587 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6588 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6589 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6590 [(set (match_dup 3)
6591 (truncate:SI
6592 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6593 (sign_extend:DI (match_dup 2)))
6594 (const_int 32))))
6595 (set (match_dup 4)
6596 (mult:SI (match_dup 1)
6597 (match_dup 2)))]
6598 "
6599 {
6600 int endian = (WORDS_BIG_ENDIAN == 0);
6601 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6602 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6603 }")
6605 (define_insn "umulsidi3"
6606 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6607 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6608 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6609 "TARGET_POWERPC && ! TARGET_POWERPC64"
6610 "*
6611 {
6612 return (WORDS_BIG_ENDIAN)
6613 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6614 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6615 }"
6616 [(set_attr "type" "imul")
6617 (set_attr "length" "8")])
6619 (define_split
6620 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6621 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6622 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6623 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6624 [(set (match_dup 3)
6625 (truncate:SI
6626 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6627 (zero_extend:DI (match_dup 2)))
6628 (const_int 32))))
6629 (set (match_dup 4)
6630 (mult:SI (match_dup 1)
6631 (match_dup 2)))]
6632 "
6633 {
6634 int endian = (WORDS_BIG_ENDIAN == 0);
6635 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6636 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6637 }")
6639 (define_expand "smulsi3_highpart"
6640 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6641 (truncate:SI
6642 (lshiftrt:DI (mult:DI (sign_extend:DI
6643 (match_operand:SI 1 "gpc_reg_operand" ""))
6644 (sign_extend:DI
6645 (match_operand:SI 2 "gpc_reg_operand" "")))
6646 (const_int 32))))]
6647 ""
6648 "
6649 {
6650 if (! TARGET_POWERPC)
6651 {
6652 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6653 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6654 emit_insn (gen_mulh_call ());
6655 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
6656 DONE;
6657 }
6658 }")
6660 (define_insn "*smulsi3_highpart_no_mq"
6661 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6662 (truncate:SI
6663 (lshiftrt:DI (mult:DI (sign_extend:DI
6664 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6665 (sign_extend:DI
6666 (match_operand:SI 2 "gpc_reg_operand" "r")))
6667 (const_int 32))))]
6668 "TARGET_POWERPC"
6669 "mulhw %0,%1,%2"
6670 [(set_attr "type" "imul")])
6672 (define_expand "umulsi3_highpart"
6673 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6674 (truncate:SI
6675 (lshiftrt:DI (mult:DI (zero_extend:DI
6676 (match_operand:SI 1 "gpc_reg_operand" ""))
6677 (zero_extend:DI
6678 (match_operand:SI 2 "gpc_reg_operand" "")))
6679 (const_int 32))))]
6680 "TARGET_POWERPC"
6681 "")
6683 (define_insn "*umulsi3_highpart_no_mq"
6684 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6685 (truncate:SI
6686 (lshiftrt:DI (mult:DI (zero_extend:DI
6687 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6688 (zero_extend:DI
6689 (match_operand:SI 2 "gpc_reg_operand" "r")))
6690 (const_int 32))))]
6691 "TARGET_POWERPC"
6692 "mulhwu %0,%1,%2"
6693 [(set_attr "type" "imul")])
6695 ;; Shift by a variable amount is too complex to be worth open-coding. We
6696 ;; just handle shifts by constants.
6697 (define_insn "ashrdi3_no_power"
6698 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6699 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6700 (match_operand:SI 2 "const_int_operand" "M,i")))]
6701 "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN"
6702 "@
6703 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6704 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
6705 [(set_attr "type" "two,three")
6706 (set_attr "length" "8,12")])
6708 (define_insn "*ashrdisi3_noppc64"
6709 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6710 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6711 (const_int 32)) 4))]
6712 "TARGET_32BIT && !TARGET_POWERPC64"
6713 "*
6714 {
6715 if (REGNO (operands[0]) == REGNO (operands[1]))
6716 return \"\";
6717 else
6718 return \"mr %0,%1\";
6719 }"
6720 [(set_attr "length" "4")])
6722 \f
6723 ;; PowerPC64 DImode operations.
6725 (define_expand "absdi2"
6726 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6727 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
6728 "TARGET_POWERPC64"
6729 "
6730 {
6731 if (TARGET_ISEL)
6732 emit_insn (gen_absdi2_isel (operands[0], operands[1]));
6733 else
6734 emit_insn (gen_absdi2_internal (operands[0], operands[1]));
6735 DONE;
6736 }")
6738 (define_insn_and_split "absdi2_internal"
6739 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6740 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6741 (clobber (match_scratch:DI 2 "=&r,&r"))]
6742 "TARGET_POWERPC64 && !TARGET_ISEL"
6743 "#"
6744 "&& reload_completed"
6745 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6746 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6747 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6748 "")
6750 (define_insn_and_split "*nabsdi2"
6751 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6752 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6753 (clobber (match_scratch:DI 2 "=&r,&r"))]
6754 "TARGET_POWERPC64 && !TARGET_ISEL"
6755 "#"
6756 "&& reload_completed"
6757 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6758 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6759 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6760 "")
6762 (define_insn "muldi3"
6763 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6764 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6765 (match_operand:DI 2 "reg_or_short_operand" "r,I")))]
6766 "TARGET_POWERPC64"
6767 "@
6768 mulld %0,%1,%2
6769 mulli %0,%1,%2"
6770 [(set (attr "type")
6771 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
6772 (const_string "imul3")
6773 (match_operand:SI 2 "short_cint_operand" "")
6774 (const_string "imul2")]
6775 (const_string "lmul")))])
6777 (define_insn "*muldi3_internal1"
6778 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6779 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6780 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6781 (const_int 0)))
6782 (clobber (match_scratch:DI 3 "=r,r"))]
6783 "TARGET_POWERPC64"
6784 "@
6785 mulld. %3,%1,%2
6786 #"
6787 [(set_attr "type" "lmul_compare")
6788 (set_attr "length" "4,8")])
6790 (define_split
6791 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6792 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6793 (match_operand:DI 2 "gpc_reg_operand" ""))
6794 (const_int 0)))
6795 (clobber (match_scratch:DI 3 ""))]
6796 "TARGET_POWERPC64 && reload_completed"
6797 [(set (match_dup 3)
6798 (mult:DI (match_dup 1) (match_dup 2)))
6799 (set (match_dup 0)
6800 (compare:CC (match_dup 3)
6801 (const_int 0)))]
6802 "")
6804 (define_insn "*muldi3_internal2"
6805 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6806 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")
6807 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6808 (const_int 0)))
6809 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6810 (mult:DI (match_dup 1) (match_dup 2)))]
6811 "TARGET_POWERPC64"
6812 "@
6813 mulld. %0,%1,%2
6814 #"
6815 [(set_attr "type" "lmul_compare")
6816 (set_attr "length" "4,8")])
6818 (define_split
6819 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6820 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "")
6821 (match_operand:DI 2 "gpc_reg_operand" ""))
6822 (const_int 0)))
6823 (set (match_operand:DI 0 "gpc_reg_operand" "")
6824 (mult:DI (match_dup 1) (match_dup 2)))]
6825 "TARGET_POWERPC64 && reload_completed"
6826 [(set (match_dup 0)
6827 (mult:DI (match_dup 1) (match_dup 2)))
6828 (set (match_dup 3)
6829 (compare:CC (match_dup 0)
6830 (const_int 0)))]
6831 "")
6833 (define_insn "smuldi3_highpart"
6834 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6835 (truncate:DI
6836 (lshiftrt:TI (mult:TI (sign_extend:TI
6837 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6838 (sign_extend:TI
6839 (match_operand:DI 2 "gpc_reg_operand" "r")))
6840 (const_int 64))))]
6841 "TARGET_POWERPC64"
6842 "mulhd %0,%1,%2"
6843 [(set_attr "type" "lmul")])
6845 (define_insn "umuldi3_highpart"
6846 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6847 (truncate:DI
6848 (lshiftrt:TI (mult:TI (zero_extend:TI
6849 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6850 (zero_extend:TI
6851 (match_operand:DI 2 "gpc_reg_operand" "r")))
6852 (const_int 64))))]
6853 "TARGET_POWERPC64"
6854 "mulhdu %0,%1,%2"
6855 [(set_attr "type" "lmul")])
6857 (define_insn "rotldi3"
6858 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6859 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6860 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))]
6861 "TARGET_POWERPC64"
6862 "@
6863 rldcl %0,%1,%2,0
6864 rldicl %0,%1,%H2,0"
6865 [(set_attr "type" "var_shift_rotate,integer")])
6867 (define_insn "*rotldi3_internal2"
6868 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6869 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6870 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6871 (const_int 0)))
6872 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6873 "TARGET_64BIT"
6874 "@
6875 rldcl. %3,%1,%2,0
6876 rldicl. %3,%1,%H2,0
6877 #
6878 #"
6879 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6880 (set_attr "length" "4,4,8,8")])
6882 (define_split
6883 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6884 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6885 (match_operand:DI 2 "reg_or_cint_operand" ""))
6886 (const_int 0)))
6887 (clobber (match_scratch:DI 3 ""))]
6888 "TARGET_POWERPC64 && reload_completed"
6889 [(set (match_dup 3)
6890 (rotate:DI (match_dup 1) (match_dup 2)))
6891 (set (match_dup 0)
6892 (compare:CC (match_dup 3)
6893 (const_int 0)))]
6894 "")
6896 (define_insn "*rotldi3_internal3"
6897 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6898 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6899 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6900 (const_int 0)))
6901 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6902 (rotate:DI (match_dup 1) (match_dup 2)))]
6903 "TARGET_64BIT"
6904 "@
6905 rldcl. %0,%1,%2,0
6906 rldicl. %0,%1,%H2,0
6907 #
6908 #"
6909 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6910 (set_attr "length" "4,4,8,8")])
6912 (define_split
6913 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
6914 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6915 (match_operand:DI 2 "reg_or_cint_operand" ""))
6916 (const_int 0)))
6917 (set (match_operand:DI 0 "gpc_reg_operand" "")
6918 (rotate:DI (match_dup 1) (match_dup 2)))]
6919 "TARGET_POWERPC64 && reload_completed"
6920 [(set (match_dup 0)
6921 (rotate:DI (match_dup 1) (match_dup 2)))
6922 (set (match_dup 3)
6923 (compare:CC (match_dup 0)
6924 (const_int 0)))]
6925 "")
6927 (define_insn "*rotldi3_internal4"
6928 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6929 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6930 (match_operand:DI 2 "reg_or_cint_operand" "r,i"))
6931 (match_operand:DI 3 "mask64_operand" "n,n")))]
6932 "TARGET_POWERPC64"
6933 "@
6934 rldc%B3 %0,%1,%2,%S3
6935 rldic%B3 %0,%1,%H2,%S3"
6936 [(set_attr "type" "var_shift_rotate,integer")])
6938 (define_insn "*rotldi3_internal5"
6939 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6940 (compare:CC (and:DI
6941 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6942 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6943 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6944 (const_int 0)))
6945 (clobber (match_scratch:DI 4 "=r,r,r,r"))]
6946 "TARGET_64BIT"
6947 "@
6948 rldc%B3. %4,%1,%2,%S3
6949 rldic%B3. %4,%1,%H2,%S3
6950 #
6951 #"
6952 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6953 (set_attr "length" "4,4,8,8")])
6955 (define_split
6956 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
6957 (compare:CC (and:DI
6958 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6959 (match_operand:DI 2 "reg_or_cint_operand" ""))
6960 (match_operand:DI 3 "mask64_operand" ""))
6961 (const_int 0)))
6962 (clobber (match_scratch:DI 4 ""))]
6963 "TARGET_POWERPC64 && reload_completed"
6964 [(set (match_dup 4)
6965 (and:DI (rotate:DI (match_dup 1)
6966 (match_dup 2))
6967 (match_dup 3)))
6968 (set (match_dup 0)
6969 (compare:CC (match_dup 4)
6970 (const_int 0)))]
6971 "")
6973 (define_insn "*rotldi3_internal6"
6974 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
6975 (compare:CC (and:DI
6976 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
6977 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i"))
6978 (match_operand:DI 3 "mask64_operand" "n,n,n,n"))
6979 (const_int 0)))
6980 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6981 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
6982 "TARGET_64BIT"
6983 "@
6984 rldc%B3. %0,%1,%2,%S3
6985 rldic%B3. %0,%1,%H2,%S3
6986 #
6987 #"
6988 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
6989 (set_attr "length" "4,4,8,8")])
6991 (define_split
6992 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
6993 (compare:CC (and:DI
6994 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6995 (match_operand:DI 2 "reg_or_cint_operand" ""))
6996 (match_operand:DI 3 "mask64_operand" ""))
6997 (const_int 0)))
6998 (set (match_operand:DI 0 "gpc_reg_operand" "")
6999 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7000 "TARGET_POWERPC64 && reload_completed"
7001 [(set (match_dup 0)
7002 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
7003 (set (match_dup 4)
7004 (compare:CC (match_dup 0)
7005 (const_int 0)))]
7006 "")
7008 (define_insn "*rotldi3_internal7"
7009 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7010 (zero_extend:DI
7011 (subreg:QI
7012 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7013 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7014 "TARGET_POWERPC64"
7015 "@
7016 rldcl %0,%1,%2,56
7017 rldicl %0,%1,%H2,56"
7018 [(set_attr "type" "var_shift_rotate,integer")])
7020 (define_insn "*rotldi3_internal8"
7021 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7022 (compare:CC (zero_extend:DI
7023 (subreg:QI
7024 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7025 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7026 (const_int 0)))
7027 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7028 "TARGET_64BIT"
7029 "@
7030 rldcl. %3,%1,%2,56
7031 rldicl. %3,%1,%H2,56
7032 #
7033 #"
7034 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7035 (set_attr "length" "4,4,8,8")])
7037 (define_split
7038 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7039 (compare:CC (zero_extend:DI
7040 (subreg:QI
7041 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7042 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7043 (const_int 0)))
7044 (clobber (match_scratch:DI 3 ""))]
7045 "TARGET_POWERPC64 && reload_completed"
7046 [(set (match_dup 3)
7047 (zero_extend:DI (subreg:QI
7048 (rotate:DI (match_dup 1)
7049 (match_dup 2)) 0)))
7050 (set (match_dup 0)
7051 (compare:CC (match_dup 3)
7052 (const_int 0)))]
7053 "")
7055 (define_insn "*rotldi3_internal9"
7056 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7057 (compare:CC (zero_extend:DI
7058 (subreg:QI
7059 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7060 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7061 (const_int 0)))
7062 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7063 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7064 "TARGET_64BIT"
7065 "@
7066 rldcl. %0,%1,%2,56
7067 rldicl. %0,%1,%H2,56
7068 #
7069 #"
7070 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7071 (set_attr "length" "4,4,8,8")])
7073 (define_split
7074 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7075 (compare:CC (zero_extend:DI
7076 (subreg:QI
7077 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7078 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7079 (const_int 0)))
7080 (set (match_operand:DI 0 "gpc_reg_operand" "")
7081 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7082 "TARGET_POWERPC64 && reload_completed"
7083 [(set (match_dup 0)
7084 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7085 (set (match_dup 3)
7086 (compare:CC (match_dup 0)
7087 (const_int 0)))]
7088 "")
7090 (define_insn "*rotldi3_internal10"
7091 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7092 (zero_extend:DI
7093 (subreg:HI
7094 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7095 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7096 "TARGET_POWERPC64"
7097 "@
7098 rldcl %0,%1,%2,48
7099 rldicl %0,%1,%H2,48"
7100 [(set_attr "type" "var_shift_rotate,integer")])
7102 (define_insn "*rotldi3_internal11"
7103 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7104 (compare:CC (zero_extend:DI
7105 (subreg:HI
7106 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7107 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7108 (const_int 0)))
7109 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7110 "TARGET_64BIT"
7111 "@
7112 rldcl. %3,%1,%2,48
7113 rldicl. %3,%1,%H2,48
7114 #
7115 #"
7116 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7117 (set_attr "length" "4,4,8,8")])
7119 (define_split
7120 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7121 (compare:CC (zero_extend:DI
7122 (subreg:HI
7123 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7124 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7125 (const_int 0)))
7126 (clobber (match_scratch:DI 3 ""))]
7127 "TARGET_POWERPC64 && reload_completed"
7128 [(set (match_dup 3)
7129 (zero_extend:DI (subreg:HI
7130 (rotate:DI (match_dup 1)
7131 (match_dup 2)) 0)))
7132 (set (match_dup 0)
7133 (compare:CC (match_dup 3)
7134 (const_int 0)))]
7135 "")
7137 (define_insn "*rotldi3_internal12"
7138 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7139 (compare:CC (zero_extend:DI
7140 (subreg:HI
7141 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7142 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7143 (const_int 0)))
7144 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7145 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7146 "TARGET_64BIT"
7147 "@
7148 rldcl. %0,%1,%2,48
7149 rldicl. %0,%1,%H2,48
7150 #
7151 #"
7152 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7153 (set_attr "length" "4,4,8,8")])
7155 (define_split
7156 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7157 (compare:CC (zero_extend:DI
7158 (subreg:HI
7159 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7160 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7161 (const_int 0)))
7162 (set (match_operand:DI 0 "gpc_reg_operand" "")
7163 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7164 "TARGET_POWERPC64 && reload_completed"
7165 [(set (match_dup 0)
7166 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7167 (set (match_dup 3)
7168 (compare:CC (match_dup 0)
7169 (const_int 0)))]
7170 "")
7172 (define_insn "*rotldi3_internal13"
7173 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7174 (zero_extend:DI
7175 (subreg:SI
7176 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7177 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))]
7178 "TARGET_POWERPC64"
7179 "@
7180 rldcl %0,%1,%2,32
7181 rldicl %0,%1,%H2,32"
7182 [(set_attr "type" "var_shift_rotate,integer")])
7184 (define_insn "*rotldi3_internal14"
7185 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7186 (compare:CC (zero_extend:DI
7187 (subreg:SI
7188 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7189 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7190 (const_int 0)))
7191 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7192 "TARGET_64BIT"
7193 "@
7194 rldcl. %3,%1,%2,32
7195 rldicl. %3,%1,%H2,32
7196 #
7197 #"
7198 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7199 (set_attr "length" "4,4,8,8")])
7201 (define_split
7202 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7203 (compare:CC (zero_extend:DI
7204 (subreg:SI
7205 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7206 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7207 (const_int 0)))
7208 (clobber (match_scratch:DI 3 ""))]
7209 "TARGET_POWERPC64 && reload_completed"
7210 [(set (match_dup 3)
7211 (zero_extend:DI (subreg:SI
7212 (rotate:DI (match_dup 1)
7213 (match_dup 2)) 0)))
7214 (set (match_dup 0)
7215 (compare:CC (match_dup 3)
7216 (const_int 0)))]
7217 "")
7219 (define_insn "*rotldi3_internal15"
7220 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7221 (compare:CC (zero_extend:DI
7222 (subreg:SI
7223 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7224 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0))
7225 (const_int 0)))
7226 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7227 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7228 "TARGET_64BIT"
7229 "@
7230 rldcl. %0,%1,%2,32
7231 rldicl. %0,%1,%H2,32
7232 #
7233 #"
7234 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7235 (set_attr "length" "4,4,8,8")])
7237 (define_split
7238 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7239 (compare:CC (zero_extend:DI
7240 (subreg:SI
7241 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7242 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7243 (const_int 0)))
7244 (set (match_operand:DI 0 "gpc_reg_operand" "")
7245 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7246 "TARGET_POWERPC64 && reload_completed"
7247 [(set (match_dup 0)
7248 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7249 (set (match_dup 3)
7250 (compare:CC (match_dup 0)
7251 (const_int 0)))]
7252 "")
7254 (define_expand "ashldi3"
7255 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7256 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7257 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7258 "TARGET_POWERPC64"
7259 "")
7261 (define_insn "*ashldi3_internal1"
7262 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7263 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7264 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7265 "TARGET_POWERPC64"
7266 "@
7267 sld %0,%1,%2
7268 sldi %0,%1,%H2"
7269 [(set_attr "type" "var_shift_rotate,shift")])
7271 (define_insn "*ashldi3_internal2"
7272 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7273 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7274 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7275 (const_int 0)))
7276 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7277 "TARGET_64BIT"
7278 "@
7279 sld. %3,%1,%2
7280 sldi. %3,%1,%H2
7281 #
7282 #"
7283 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7284 (set_attr "length" "4,4,8,8")])
7286 (define_split
7287 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7288 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7289 (match_operand:SI 2 "reg_or_cint_operand" ""))
7290 (const_int 0)))
7291 (clobber (match_scratch:DI 3 ""))]
7292 "TARGET_POWERPC64 && reload_completed"
7293 [(set (match_dup 3)
7294 (ashift:DI (match_dup 1) (match_dup 2)))
7295 (set (match_dup 0)
7296 (compare:CC (match_dup 3)
7297 (const_int 0)))]
7298 "")
7300 (define_insn "*ashldi3_internal3"
7301 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7302 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7303 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7304 (const_int 0)))
7305 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7306 (ashift:DI (match_dup 1) (match_dup 2)))]
7307 "TARGET_64BIT"
7308 "@
7309 sld. %0,%1,%2
7310 sldi. %0,%1,%H2
7311 #
7312 #"
7313 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7314 (set_attr "length" "4,4,8,8")])
7316 (define_split
7317 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7318 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7319 (match_operand:SI 2 "reg_or_cint_operand" ""))
7320 (const_int 0)))
7321 (set (match_operand:DI 0 "gpc_reg_operand" "")
7322 (ashift:DI (match_dup 1) (match_dup 2)))]
7323 "TARGET_POWERPC64 && reload_completed"
7324 [(set (match_dup 0)
7325 (ashift:DI (match_dup 1) (match_dup 2)))
7326 (set (match_dup 3)
7327 (compare:CC (match_dup 0)
7328 (const_int 0)))]
7329 "")
7331 (define_insn "*ashldi3_internal4"
7332 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7333 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7334 (match_operand:SI 2 "const_int_operand" "i"))
7335 (match_operand:DI 3 "const_int_operand" "n")))]
7336 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7337 "rldic %0,%1,%H2,%W3")
7339 (define_insn "ashldi3_internal5"
7340 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7341 (compare:CC
7342 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7343 (match_operand:SI 2 "const_int_operand" "i,i"))
7344 (match_operand:DI 3 "const_int_operand" "n,n"))
7345 (const_int 0)))
7346 (clobber (match_scratch:DI 4 "=r,r"))]
7347 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7348 "@
7349 rldic. %4,%1,%H2,%W3
7350 #"
7351 [(set_attr "type" "compare")
7352 (set_attr "length" "4,8")])
7354 (define_split
7355 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7356 (compare:CC
7357 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7358 (match_operand:SI 2 "const_int_operand" ""))
7359 (match_operand:DI 3 "const_int_operand" ""))
7360 (const_int 0)))
7361 (clobber (match_scratch:DI 4 ""))]
7362 "TARGET_POWERPC64 && reload_completed
7363 && includes_rldic_lshift_p (operands[2], operands[3])"
7364 [(set (match_dup 4)
7365 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7366 (match_dup 3)))
7367 (set (match_dup 0)
7368 (compare:CC (match_dup 4)
7369 (const_int 0)))]
7370 "")
7372 (define_insn "*ashldi3_internal6"
7373 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7374 (compare:CC
7375 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7376 (match_operand:SI 2 "const_int_operand" "i,i"))
7377 (match_operand:DI 3 "const_int_operand" "n,n"))
7378 (const_int 0)))
7379 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7380 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7381 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])"
7382 "@
7383 rldic. %0,%1,%H2,%W3
7384 #"
7385 [(set_attr "type" "compare")
7386 (set_attr "length" "4,8")])
7388 (define_split
7389 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7390 (compare:CC
7391 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7392 (match_operand:SI 2 "const_int_operand" ""))
7393 (match_operand:DI 3 "const_int_operand" ""))
7394 (const_int 0)))
7395 (set (match_operand:DI 0 "gpc_reg_operand" "")
7396 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7397 "TARGET_POWERPC64 && reload_completed
7398 && includes_rldic_lshift_p (operands[2], operands[3])"
7399 [(set (match_dup 0)
7400 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7401 (match_dup 3)))
7402 (set (match_dup 4)
7403 (compare:CC (match_dup 0)
7404 (const_int 0)))]
7405 "")
7407 (define_insn "*ashldi3_internal7"
7408 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7409 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7410 (match_operand:SI 2 "const_int_operand" "i"))
7411 (match_operand:DI 3 "mask64_operand" "n")))]
7412 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7413 "rldicr %0,%1,%H2,%S3")
7415 (define_insn "ashldi3_internal8"
7416 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7417 (compare:CC
7418 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7419 (match_operand:SI 2 "const_int_operand" "i,i"))
7420 (match_operand:DI 3 "mask64_operand" "n,n"))
7421 (const_int 0)))
7422 (clobber (match_scratch:DI 4 "=r,r"))]
7423 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7424 "@
7425 rldicr. %4,%1,%H2,%S3
7426 #"
7427 [(set_attr "type" "compare")
7428 (set_attr "length" "4,8")])
7430 (define_split
7431 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7432 (compare:CC
7433 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7434 (match_operand:SI 2 "const_int_operand" ""))
7435 (match_operand:DI 3 "mask64_operand" ""))
7436 (const_int 0)))
7437 (clobber (match_scratch:DI 4 ""))]
7438 "TARGET_POWERPC64 && reload_completed
7439 && includes_rldicr_lshift_p (operands[2], operands[3])"
7440 [(set (match_dup 4)
7441 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7442 (match_dup 3)))
7443 (set (match_dup 0)
7444 (compare:CC (match_dup 4)
7445 (const_int 0)))]
7446 "")
7448 (define_insn "*ashldi3_internal9"
7449 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7450 (compare:CC
7451 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7452 (match_operand:SI 2 "const_int_operand" "i,i"))
7453 (match_operand:DI 3 "mask64_operand" "n,n"))
7454 (const_int 0)))
7455 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7456 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7457 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])"
7458 "@
7459 rldicr. %0,%1,%H2,%S3
7460 #"
7461 [(set_attr "type" "compare")
7462 (set_attr "length" "4,8")])
7464 (define_split
7465 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
7466 (compare:CC
7467 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7468 (match_operand:SI 2 "const_int_operand" ""))
7469 (match_operand:DI 3 "mask64_operand" ""))
7470 (const_int 0)))
7471 (set (match_operand:DI 0 "gpc_reg_operand" "")
7472 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7473 "TARGET_POWERPC64 && reload_completed
7474 && includes_rldicr_lshift_p (operands[2], operands[3])"
7475 [(set (match_dup 0)
7476 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7477 (match_dup 3)))
7478 (set (match_dup 4)
7479 (compare:CC (match_dup 0)
7480 (const_int 0)))]
7481 "")
7483 (define_expand "lshrdi3"
7484 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7485 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7486 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7487 "TARGET_POWERPC64"
7488 "")
7490 (define_insn "*lshrdi3_internal1"
7491 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7492 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7493 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7494 "TARGET_POWERPC64"
7495 "@
7496 srd %0,%1,%2
7497 srdi %0,%1,%H2"
7498 [(set_attr "type" "var_shift_rotate,shift")])
7500 (define_insn "*lshrdi3_internal2"
7501 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7502 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7503 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7504 (const_int 0)))
7505 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7506 "TARGET_64BIT "
7507 "@
7508 srd. %3,%1,%2
7509 srdi. %3,%1,%H2
7510 #
7511 #"
7512 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7513 (set_attr "length" "4,4,8,8")])
7515 (define_split
7516 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7517 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7518 (match_operand:SI 2 "reg_or_cint_operand" ""))
7519 (const_int 0)))
7520 (clobber (match_scratch:DI 3 ""))]
7521 "TARGET_POWERPC64 && reload_completed"
7522 [(set (match_dup 3)
7523 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7524 (set (match_dup 0)
7525 (compare:CC (match_dup 3)
7526 (const_int 0)))]
7527 "")
7529 (define_insn "*lshrdi3_internal3"
7530 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7531 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7532 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7533 (const_int 0)))
7534 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7535 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7536 "TARGET_64BIT"
7537 "@
7538 srd. %0,%1,%2
7539 srdi. %0,%1,%H2
7540 #
7541 #"
7542 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7543 (set_attr "length" "4,4,8,8")])
7545 (define_split
7546 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7547 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7548 (match_operand:SI 2 "reg_or_cint_operand" ""))
7549 (const_int 0)))
7550 (set (match_operand:DI 0 "gpc_reg_operand" "")
7551 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7552 "TARGET_POWERPC64 && reload_completed"
7553 [(set (match_dup 0)
7554 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7555 (set (match_dup 3)
7556 (compare:CC (match_dup 0)
7557 (const_int 0)))]
7558 "")
7560 (define_expand "ashrdi3"
7561 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7562 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7563 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7564 "WORDS_BIG_ENDIAN"
7565 "
7566 {
7567 if (TARGET_POWERPC64)
7568 ;
7569 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT
7570 && WORDS_BIG_ENDIAN)
7571 {
7572 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7573 DONE;
7574 }
7575 else
7576 FAIL;
7577 }")
7579 (define_insn "*ashrdi3_internal1"
7580 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7581 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7582 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
7583 "TARGET_POWERPC64"
7584 "@
7585 srad %0,%1,%2
7586 sradi %0,%1,%H2"
7587 [(set_attr "type" "var_shift_rotate,shift")])
7589 (define_insn "*ashrdi3_internal2"
7590 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
7591 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7592 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7593 (const_int 0)))
7594 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
7595 "TARGET_64BIT"
7596 "@
7597 srad. %3,%1,%2
7598 sradi. %3,%1,%H2
7599 #
7600 #"
7601 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7602 (set_attr "length" "4,4,8,8")])
7604 (define_split
7605 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7606 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7607 (match_operand:SI 2 "reg_or_cint_operand" ""))
7608 (const_int 0)))
7609 (clobber (match_scratch:DI 3 ""))]
7610 "TARGET_POWERPC64 && reload_completed"
7611 [(set (match_dup 3)
7612 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7613 (set (match_dup 0)
7614 (compare:CC (match_dup 3)
7615 (const_int 0)))]
7616 "")
7618 (define_insn "*ashrdi3_internal3"
7619 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
7620 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
7621 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
7622 (const_int 0)))
7623 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7624 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7625 "TARGET_64BIT"
7626 "@
7627 srad. %0,%1,%2
7628 sradi. %0,%1,%H2
7629 #
7630 #"
7631 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare")
7632 (set_attr "length" "4,4,8,8")])
7634 (define_split
7635 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7636 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7637 (match_operand:SI 2 "reg_or_cint_operand" ""))
7638 (const_int 0)))
7639 (set (match_operand:DI 0 "gpc_reg_operand" "")
7640 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7641 "TARGET_POWERPC64 && reload_completed"
7642 [(set (match_dup 0)
7643 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7644 (set (match_dup 3)
7645 (compare:CC (match_dup 0)
7646 (const_int 0)))]
7647 "")
7649 (define_expand "anddi3"
7650 [(parallel
7651 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7652 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7653 (match_operand:DI 2 "and64_2_operand" "")))
7654 (clobber (match_scratch:CC 3 ""))])]
7655 "TARGET_POWERPC64"
7656 "")
7658 (define_insn "anddi3_mc"
7659 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
7660 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r")
7661 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t")))
7662 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))]
7663 "TARGET_POWERPC64 && rs6000_gen_cell_microcode"
7664 "@
7665 and %0,%1,%2
7666 rldic%B2 %0,%1,0,%S2
7667 rlwinm %0,%1,0,%m2,%M2
7668 andi. %0,%1,%b2
7669 andis. %0,%1,%u2
7670 #"
7671 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*")
7672 (set_attr "length" "4,4,4,4,4,8")])
7674 (define_insn "anddi3_nomc"
7675 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
7676 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
7677 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t")))
7678 (clobber (match_scratch:CC 3 "=X,X,X,X"))]
7679 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode"
7680 "@
7681 and %0,%1,%2
7682 rldic%B2 %0,%1,0,%S2
7683 rlwinm %0,%1,0,%m2,%M2
7684 #"
7685 [(set_attr "length" "4,4,4,8")])
7687 (define_split
7688 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7689 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7690 (match_operand:DI 2 "mask64_2_operand" "")))
7691 (clobber (match_scratch:CC 3 ""))]
7692 "TARGET_POWERPC64
7693 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7694 && !mask_operand (operands[2], DImode)
7695 && !mask64_operand (operands[2], DImode)"
7696 [(set (match_dup 0)
7697 (and:DI (rotate:DI (match_dup 1)
7698 (match_dup 4))
7699 (match_dup 5)))
7700 (set (match_dup 0)
7701 (and:DI (rotate:DI (match_dup 0)
7702 (match_dup 6))
7703 (match_dup 7)))]
7704 {
7705 build_mask64_2_operands (operands[2], &operands[4]);
7706 })
7708 (define_insn "*anddi3_internal2_mc"
7709 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7710 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7711 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7712 (const_int 0)))
7713 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r"))
7714 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7715 "TARGET_64BIT && rs6000_gen_cell_microcode"
7716 "@
7717 and. %3,%1,%2
7718 rldic%B2. %3,%1,0,%S2
7719 rlwinm. %3,%1,0,%m2,%M2
7720 andi. %3,%1,%b2
7721 andis. %3,%1,%u2
7722 #
7723 #
7724 #
7725 #
7726 #
7727 #
7728 #"
7729 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
7730 fast_compare,compare,compare,compare,compare,compare,\
7731 compare,compare")
7732 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7734 (define_split
7735 [(set (match_operand:CC 0 "cc_reg_operand" "")
7736 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7737 (match_operand:DI 2 "mask64_2_operand" ""))
7738 (const_int 0)))
7739 (clobber (match_scratch:DI 3 ""))
7740 (clobber (match_scratch:CC 4 ""))]
7741 "TARGET_64BIT && reload_completed
7742 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7743 && !mask_operand (operands[2], DImode)
7744 && !mask64_operand (operands[2], DImode)"
7745 [(set (match_dup 3)
7746 (and:DI (rotate:DI (match_dup 1)
7747 (match_dup 5))
7748 (match_dup 6)))
7749 (parallel [(set (match_dup 0)
7750 (compare:CC (and:DI (rotate:DI (match_dup 3)
7751 (match_dup 7))
7752 (match_dup 8))
7753 (const_int 0)))
7754 (clobber (match_dup 3))])]
7755 "
7756 {
7757 build_mask64_2_operands (operands[2], &operands[5]);
7758 }")
7760 (define_insn "*anddi3_internal3_mc"
7761 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y")
7762 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r")
7763 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t"))
7764 (const_int 0)))
7765 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r")
7766 (and:DI (match_dup 1) (match_dup 2)))
7767 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))]
7768 "TARGET_64BIT && rs6000_gen_cell_microcode"
7769 "@
7770 and. %0,%1,%2
7771 rldic%B2. %0,%1,0,%S2
7772 rlwinm. %0,%1,0,%m2,%M2
7773 andi. %0,%1,%b2
7774 andis. %0,%1,%u2
7775 #
7776 #
7777 #
7778 #
7779 #
7780 #
7781 #"
7782 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\
7783 fast_compare,compare,compare,compare,compare,compare,\
7784 compare,compare")
7785 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
7787 (define_split
7788 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7789 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7790 (match_operand:DI 2 "and64_2_operand" ""))
7791 (const_int 0)))
7792 (set (match_operand:DI 0 "gpc_reg_operand" "")
7793 (and:DI (match_dup 1) (match_dup 2)))
7794 (clobber (match_scratch:CC 4 ""))]
7795 "TARGET_64BIT && reload_completed"
7796 [(parallel [(set (match_dup 0)
7797 (and:DI (match_dup 1) (match_dup 2)))
7798 (clobber (match_dup 4))])
7799 (set (match_dup 3)
7800 (compare:CC (match_dup 0)
7801 (const_int 0)))]
7802 "")
7804 (define_split
7805 [(set (match_operand:CC 3 "cc_reg_operand" "")
7806 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7807 (match_operand:DI 2 "mask64_2_operand" ""))
7808 (const_int 0)))
7809 (set (match_operand:DI 0 "gpc_reg_operand" "")
7810 (and:DI (match_dup 1) (match_dup 2)))
7811 (clobber (match_scratch:CC 4 ""))]
7812 "TARGET_64BIT && reload_completed
7813 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7814 && !mask_operand (operands[2], DImode)
7815 && !mask64_operand (operands[2], DImode)"
7816 [(set (match_dup 0)
7817 (and:DI (rotate:DI (match_dup 1)
7818 (match_dup 5))
7819 (match_dup 6)))
7820 (parallel [(set (match_dup 3)
7821 (compare:CC (and:DI (rotate:DI (match_dup 0)
7822 (match_dup 7))
7823 (match_dup 8))
7824 (const_int 0)))
7825 (set (match_dup 0)
7826 (and:DI (rotate:DI (match_dup 0)
7827 (match_dup 7))
7828 (match_dup 8)))])]
7829 "
7830 {
7831 build_mask64_2_operands (operands[2], &operands[5]);
7832 }")
7834 (define_expand "iordi3"
7835 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7836 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7837 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7838 "TARGET_POWERPC64"
7839 "
7840 {
7841 if (non_logical_cint_operand (operands[2], DImode))
7842 {
7843 HOST_WIDE_INT value;
7844 rtx tmp = ((!can_create_pseudo_p ()
7845 || rtx_equal_p (operands[0], operands[1]))
7846 ? operands[0] : gen_reg_rtx (DImode));
7848 if (GET_CODE (operands[2]) == CONST_INT)
7849 {
7850 value = INTVAL (operands[2]);
7851 emit_insn (gen_iordi3 (tmp, operands[1],
7852 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7853 }
7854 else
7855 {
7856 value = CONST_DOUBLE_LOW (operands[2]);
7857 emit_insn (gen_iordi3 (tmp, operands[1],
7858 immed_double_const (value
7859 & (~ (HOST_WIDE_INT) 0xffff),
7860 0, DImode)));
7861 }
7863 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7864 DONE;
7865 }
7866 }")
7868 (define_expand "xordi3"
7869 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7870 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7871 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7872 "TARGET_POWERPC64"
7873 "
7874 {
7875 if (non_logical_cint_operand (operands[2], DImode))
7876 {
7877 HOST_WIDE_INT value;
7878 rtx tmp = ((!can_create_pseudo_p ()
7879 || rtx_equal_p (operands[0], operands[1]))
7880 ? operands[0] : gen_reg_rtx (DImode));
7882 if (GET_CODE (operands[2]) == CONST_INT)
7883 {
7884 value = INTVAL (operands[2]);
7885 emit_insn (gen_xordi3 (tmp, operands[1],
7886 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7887 }
7888 else
7889 {
7890 value = CONST_DOUBLE_LOW (operands[2]);
7891 emit_insn (gen_xordi3 (tmp, operands[1],
7892 immed_double_const (value
7893 & (~ (HOST_WIDE_INT) 0xffff),
7894 0, DImode)));
7895 }
7897 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7898 DONE;
7899 }
7900 }")
7902 (define_insn "*booldi3_internal1"
7903 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7904 (match_operator:DI 3 "boolean_or_operator"
7905 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7906 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7907 "TARGET_POWERPC64"
7908 "@
7909 %q3 %0,%1,%2
7910 %q3i %0,%1,%b2
7911 %q3is %0,%1,%u2")
7913 (define_insn "*booldi3_internal2"
7914 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7915 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7916 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7917 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7918 (const_int 0)))
7919 (clobber (match_scratch:DI 3 "=r,r"))]
7920 "TARGET_64BIT"
7921 "@
7922 %q4. %3,%1,%2
7923 #"
7924 [(set_attr "type" "fast_compare,compare")
7925 (set_attr "length" "4,8")])
7927 (define_split
7928 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
7929 (compare:CC (match_operator:DI 4 "boolean_operator"
7930 [(match_operand:DI 1 "gpc_reg_operand" "")
7931 (match_operand:DI 2 "gpc_reg_operand" "")])
7932 (const_int 0)))
7933 (clobber (match_scratch:DI 3 ""))]
7934 "TARGET_POWERPC64 && reload_completed"
7935 [(set (match_dup 3) (match_dup 4))
7936 (set (match_dup 0)
7937 (compare:CC (match_dup 3)
7938 (const_int 0)))]
7939 "")
7941 (define_insn "*booldi3_internal3"
7942 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7943 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7944 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7945 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7946 (const_int 0)))
7947 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7948 (match_dup 4))]
7949 "TARGET_64BIT"
7950 "@
7951 %q4. %0,%1,%2
7952 #"
7953 [(set_attr "type" "fast_compare,compare")
7954 (set_attr "length" "4,8")])
7956 (define_split
7957 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
7958 (compare:CC (match_operator:DI 4 "boolean_operator"
7959 [(match_operand:DI 1 "gpc_reg_operand" "")
7960 (match_operand:DI 2 "gpc_reg_operand" "")])
7961 (const_int 0)))
7962 (set (match_operand:DI 0 "gpc_reg_operand" "")
7963 (match_dup 4))]
7964 "TARGET_POWERPC64 && reload_completed"
7965 [(set (match_dup 0) (match_dup 4))
7966 (set (match_dup 3)
7967 (compare:CC (match_dup 0)
7968 (const_int 0)))]
7969 "")
7971 ;; Split a logical operation that we can't do in one insn into two insns,
7972 ;; each of which does one 16-bit part. This is used by combine.
7974 (define_split
7975 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7976 (match_operator:DI 3 "boolean_or_operator"
7977 [(match_operand:DI 1 "gpc_reg_operand" "")
7978 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7979 "TARGET_POWERPC64"
7980 [(set (match_dup 0) (match_dup 4))
7981 (set (match_dup 0) (match_dup 5))]
7982 "
7983 {
7984 rtx i3,i4;
7986 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7987 {
7988 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
7989 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
7990 0, DImode);
7991 i4 = GEN_INT (value & 0xffff);
7992 }
7993 else
7994 {
7995 i3 = GEN_INT (INTVAL (operands[2])
7996 & (~ (HOST_WIDE_INT) 0xffff));
7997 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
7998 }
7999 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8000 operands[1], i3);
8001 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode,
8002 operands[0], i4);
8003 }")
8005 (define_insn "*boolcdi3_internal1"
8006 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8007 (match_operator:DI 3 "boolean_operator"
8008 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8009 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
8010 "TARGET_POWERPC64"
8011 "%q3 %0,%2,%1")
8013 (define_insn "*boolcdi3_internal2"
8014 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8015 (compare:CC (match_operator:DI 4 "boolean_operator"
8016 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8017 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8018 (const_int 0)))
8019 (clobber (match_scratch:DI 3 "=r,r"))]
8020 "TARGET_64BIT"
8021 "@
8022 %q4. %3,%2,%1
8023 #"
8024 [(set_attr "type" "fast_compare,compare")
8025 (set_attr "length" "4,8")])
8027 (define_split
8028 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8029 (compare:CC (match_operator:DI 4 "boolean_operator"
8030 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8031 (match_operand:DI 2 "gpc_reg_operand" "")])
8032 (const_int 0)))
8033 (clobber (match_scratch:DI 3 ""))]
8034 "TARGET_POWERPC64 && reload_completed"
8035 [(set (match_dup 3) (match_dup 4))
8036 (set (match_dup 0)
8037 (compare:CC (match_dup 3)
8038 (const_int 0)))]
8039 "")
8041 (define_insn "*boolcdi3_internal3"
8042 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8043 (compare:CC (match_operator:DI 4 "boolean_operator"
8044 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8045 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8046 (const_int 0)))
8047 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8048 (match_dup 4))]
8049 "TARGET_64BIT"
8050 "@
8051 %q4. %0,%2,%1
8052 #"
8053 [(set_attr "type" "fast_compare,compare")
8054 (set_attr "length" "4,8")])
8056 (define_split
8057 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8058 (compare:CC (match_operator:DI 4 "boolean_operator"
8059 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8060 (match_operand:DI 2 "gpc_reg_operand" "")])
8061 (const_int 0)))
8062 (set (match_operand:DI 0 "gpc_reg_operand" "")
8063 (match_dup 4))]
8064 "TARGET_POWERPC64 && reload_completed"
8065 [(set (match_dup 0) (match_dup 4))
8066 (set (match_dup 3)
8067 (compare:CC (match_dup 0)
8068 (const_int 0)))]
8069 "")
8071 (define_insn "*boolccdi3_internal1"
8072 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8073 (match_operator:DI 3 "boolean_operator"
8074 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8075 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
8076 "TARGET_POWERPC64"
8077 "%q3 %0,%1,%2")
8079 (define_insn "*boolccdi3_internal2"
8080 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8081 (compare:CC (match_operator:DI 4 "boolean_operator"
8082 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8083 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8084 (const_int 0)))
8085 (clobber (match_scratch:DI 3 "=r,r"))]
8086 "TARGET_64BIT"
8087 "@
8088 %q4. %3,%1,%2
8089 #"
8090 [(set_attr "type" "fast_compare,compare")
8091 (set_attr "length" "4,8")])
8093 (define_split
8094 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
8095 (compare:CC (match_operator:DI 4 "boolean_operator"
8096 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8097 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8098 (const_int 0)))
8099 (clobber (match_scratch:DI 3 ""))]
8100 "TARGET_POWERPC64 && reload_completed"
8101 [(set (match_dup 3) (match_dup 4))
8102 (set (match_dup 0)
8103 (compare:CC (match_dup 3)
8104 (const_int 0)))]
8105 "")
8107 (define_insn "*boolccdi3_internal3"
8108 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8109 (compare:CC (match_operator:DI 4 "boolean_operator"
8110 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8111 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8112 (const_int 0)))
8113 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8114 (match_dup 4))]
8115 "TARGET_64BIT"
8116 "@
8117 %q4. %0,%1,%2
8118 #"
8119 [(set_attr "type" "fast_compare,compare")
8120 (set_attr "length" "4,8")])
8122 (define_split
8123 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
8124 (compare:CC (match_operator:DI 4 "boolean_operator"
8125 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8126 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8127 (const_int 0)))
8128 (set (match_operand:DI 0 "gpc_reg_operand" "")
8129 (match_dup 4))]
8130 "TARGET_POWERPC64 && reload_completed"
8131 [(set (match_dup 0) (match_dup 4))
8132 (set (match_dup 3)
8133 (compare:CC (match_dup 0)
8134 (const_int 0)))]
8135 "")
8137 (define_expand "smindi3"
8138 [(match_operand:DI 0 "gpc_reg_operand" "")
8139 (match_operand:DI 1 "gpc_reg_operand" "")
8140 (match_operand:DI 2 "gpc_reg_operand" "")]
8141 "TARGET_ISEL64"
8142 "
8143 {
8144 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
8145 DONE;
8146 }")
8148 (define_expand "smaxdi3"
8149 [(match_operand:DI 0 "gpc_reg_operand" "")
8150 (match_operand:DI 1 "gpc_reg_operand" "")
8151 (match_operand:DI 2 "gpc_reg_operand" "")]
8152 "TARGET_ISEL64"
8153 "
8154 {
8155 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
8156 DONE;
8157 }")
8159 (define_expand "umindi3"
8160 [(match_operand:DI 0 "gpc_reg_operand" "")
8161 (match_operand:DI 1 "gpc_reg_operand" "")
8162 (match_operand:DI 2 "gpc_reg_operand" "")]
8163 "TARGET_ISEL64"
8164 "
8165 {
8166 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
8167 DONE;
8168 }")
8170 (define_expand "umaxdi3"
8171 [(match_operand:DI 0 "gpc_reg_operand" "")
8172 (match_operand:DI 1 "gpc_reg_operand" "")
8173 (match_operand:DI 2 "gpc_reg_operand" "")]
8174 "TARGET_ISEL64"
8175 "
8176 {
8177 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
8178 DONE;
8179 }")
8181 \f
8182 ;; Now define ways of moving data around.
8184 ;; Set up a register with a value from the GOT table
8186 (define_expand "movsi_got"
8187 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8188 (unspec:SI [(match_operand:SI 1 "got_operand" "")
8189 (match_dup 2)] UNSPEC_MOVSI_GOT))]
8190 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8191 "
8192 {
8193 if (GET_CODE (operands[1]) == CONST)
8194 {
8195 rtx offset = const0_rtx;
8196 HOST_WIDE_INT value;
8198 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8199 value = INTVAL (offset);
8200 if (value != 0)
8201 {
8202 rtx tmp = (!can_create_pseudo_p ()
8203 ? operands[0]
8204 : gen_reg_rtx (Pmode));
8205 emit_insn (gen_movsi_got (tmp, operands[1]));
8206 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8207 DONE;
8208 }
8209 }
8211 operands[2] = rs6000_got_register (operands[1]);
8212 }")
8214 (define_insn "*movsi_got_internal"
8215 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8216 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8217 (match_operand:SI 2 "gpc_reg_operand" "b")]
8218 UNSPEC_MOVSI_GOT))]
8219 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8220 "{l|lwz} %0,%a1@got(%2)"
8221 [(set_attr "type" "load")])
8223 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8224 ;; didn't get allocated to a hard register.
8225 (define_split
8226 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8227 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8228 (match_operand:SI 2 "memory_operand" "")]
8229 UNSPEC_MOVSI_GOT))]
8230 "DEFAULT_ABI == ABI_V4
8231 && flag_pic == 1
8232 && (reload_in_progress || reload_completed)"
8233 [(set (match_dup 0) (match_dup 2))
8234 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)]
8235 UNSPEC_MOVSI_GOT))]
8236 "")
8238 ;; For SI, we special-case integers that can't be loaded in one insn. We
8239 ;; do the load 16-bits at a time. We could do this by loading from memory,
8240 ;; and this is even supposed to be faster, but it is simpler not to get
8241 ;; integers in the TOC.
8242 (define_insn "movsi_low"
8243 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8244 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8245 (match_operand 2 "" ""))))]
8246 "TARGET_MACHO && ! TARGET_64BIT"
8247 "{l|lwz} %0,lo16(%2)(%1)"
8248 [(set_attr "type" "load")
8249 (set_attr "length" "4")])
8251 (define_insn "*movsi_internal1"
8252 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*q,*c*l,*h,*h")
8253 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,r,0"))]
8254 "!TARGET_SINGLE_FPU &&
8255 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8256 "@
8257 mr %0,%1
8258 {cal|la} %0,%a1
8259 {l%U1%X1|lwz%U1%X1} %0,%1
8260 {st%U0%X0|stw%U0%X0} %1,%0
8261 {lil|li} %0,%1
8262 {liu|lis} %0,%v1
8263 #
8264 mf%1 %0
8265 mt%0 %1
8266 mt%0 %1
8267 mt%0 %1
8268 {cror 0,0,0|nop}"
8269 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,*,mtjmpr,*,*")
8270 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4")])
8272 (define_insn "*movsi_internal1_single"
8273 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*q,*c*l,*h,*h,m,*f")
8274 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,r,0,f,m"))]
8275 "TARGET_SINGLE_FPU &&
8276 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))"
8277 "@
8278 mr %0,%1
8279 {cal|la} %0,%a1
8280 {l%U1%X1|lwz%U1%X1} %0,%1
8281 {st%U0%X0|stw%U0%X0} %1,%0
8282 {lil|li} %0,%1
8283 {liu|lis} %0,%v1
8284 #
8285 mf%1 %0
8286 mt%0 %1
8287 mt%0 %1
8288 mt%0 %1
8289 {cror 0,0,0|nop}
8290 stfs%U0%X0 %1, %0
8291 lfs%U1%X1 %0, %1"
8292 [(set_attr "type" "*,*,load,store,*,*,*,mfjmpr,*,mtjmpr,*,*,*,*")
8293 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4,4")])
8295 ;; Split a load of a large constant into the appropriate two-insn
8296 ;; sequence.
8298 (define_split
8299 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8300 (match_operand:SI 1 "const_int_operand" ""))]
8301 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8302 && (INTVAL (operands[1]) & 0xffff) != 0"
8303 [(set (match_dup 0)
8304 (match_dup 2))
8305 (set (match_dup 0)
8306 (ior:SI (match_dup 0)
8307 (match_dup 3)))]
8308 "
8309 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8311 if (tem == operands[0])
8312 DONE;
8313 else
8314 FAIL;
8315 }")
8317 (define_insn "*mov<mode>_internal2"
8318 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y")
8319 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r")
8320 (const_int 0)))
8321 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))]
8322 ""
8323 "@
8324 {cmpi|cmp<wd>i} %2,%0,0
8325 mr. %0,%1
8326 #"
8327 [(set_attr "type" "cmp,compare,cmp")
8328 (set_attr "length" "4,4,8")])
8330 (define_split
8331 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "")
8332 (compare:CC (match_operand:P 1 "gpc_reg_operand" "")
8333 (const_int 0)))
8334 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))]
8335 "reload_completed"
8336 [(set (match_dup 0) (match_dup 1))
8337 (set (match_dup 2)
8338 (compare:CC (match_dup 0)
8339 (const_int 0)))]
8340 "")
8341 \f
8342 (define_insn "*movhi_internal"
8343 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8344 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8345 "gpc_reg_operand (operands[0], HImode)
8346 || gpc_reg_operand (operands[1], HImode)"
8347 "@
8348 mr %0,%1
8349 lhz%U1%X1 %0,%1
8350 sth%U0%X0 %1,%0
8351 {lil|li} %0,%w1
8352 mf%1 %0
8353 mt%0 %1
8354 mt%0 %1
8355 {cror 0,0,0|nop}"
8356 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8358 (define_expand "mov<mode>"
8359 [(set (match_operand:INT 0 "general_operand" "")
8360 (match_operand:INT 1 "any_operand" ""))]
8361 ""
8362 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }")
8364 (define_insn "*movqi_internal"
8365 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8366 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8367 "gpc_reg_operand (operands[0], QImode)
8368 || gpc_reg_operand (operands[1], QImode)"
8369 "@
8370 mr %0,%1
8371 lbz%U1%X1 %0,%1
8372 stb%U0%X0 %1,%0
8373 {lil|li} %0,%1
8374 mf%1 %0
8375 mt%0 %1
8376 mt%0 %1
8377 {cror 0,0,0|nop}"
8378 [(set_attr "type" "*,load,store,*,mfjmpr,*,mtjmpr,*")])
8379 \f
8380 ;; Here is how to move condition codes around. When we store CC data in
8381 ;; an integer register or memory, we store just the high-order 4 bits.
8382 ;; This lets us not shift in the most common case of CR0.
8383 (define_expand "movcc"
8384 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8385 (match_operand:CC 1 "nonimmediate_operand" ""))]
8386 ""
8387 "")
8389 (define_insn "*movcc_internal1"
8390 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,q,cl,r,m")
8391 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,r,m,r"))]
8392 "register_operand (operands[0], CCmode)
8393 || register_operand (operands[1], CCmode)"
8394 "@
8395 mcrf %0,%1
8396 mtcrf 128,%1
8397 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
8398 crxor %0,%0,%0
8399 mfcr %0%Q1
8400 mfcr %0%Q1\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
8401 mr %0,%1
8402 {lil|li} %0,%1
8403 mf%1 %0
8404 mt%0 %1
8405 mt%0 %1
8406 {l%U1%X1|lwz%U1%X1} %0,%1
8407 {st%U0%U1|stw%U0%U1} %1,%0"
8408 [(set (attr "type")
8409 (cond [(eq_attr "alternative" "0,3")
8410 (const_string "cr_logical")
8411 (eq_attr "alternative" "1,2")
8412 (const_string "mtcr")
8413 (eq_attr "alternative" "6,7,9")
8414 (const_string "integer")
8415 (eq_attr "alternative" "8")
8416 (const_string "mfjmpr")
8417 (eq_attr "alternative" "10")
8418 (const_string "mtjmpr")
8419 (eq_attr "alternative" "11")
8420 (const_string "load")
8421 (eq_attr "alternative" "12")
8422 (const_string "store")
8423 (match_test "TARGET_MFCRF")
8424 (const_string "mfcrf")
8425 ]
8426 (const_string "mfcr")))
8427 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4,4")])
8428 \f
8429 ;; For floating-point, we normally deal with the floating-point registers
8430 ;; unless -msoft-float is used. The sole exception is that parameter passing
8431 ;; can produce floating-point values in fixed-point registers. Unless the
8432 ;; value is a simple constant or already in memory, we deal with this by
8433 ;; allocating memory and copying the value explicitly via that memory location.
8434 (define_expand "movsf"
8435 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8436 (match_operand:SF 1 "any_operand" ""))]
8437 ""
8438 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
8440 (define_split
8441 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8442 (match_operand:SF 1 "const_double_operand" ""))]
8443 "reload_completed
8444 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8445 || (GET_CODE (operands[0]) == SUBREG
8446 && GET_CODE (SUBREG_REG (operands[0])) == REG
8447 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8448 [(set (match_dup 2) (match_dup 3))]
8449 "
8450 {
8451 long l;
8452 REAL_VALUE_TYPE rv;
8454 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8455 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
8457 if (! TARGET_POWERPC64)
8458 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8459 else
8460 operands[2] = gen_lowpart (SImode, operands[0]);
8462 operands[3] = gen_int_mode (l, SImode);
8463 }")
8465 (define_insn "*movsf_hardfloat"
8466 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,*c*l,*q,!r,*h,!r,!r")
8467 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
8468 "(gpc_reg_operand (operands[0], SFmode)
8469 || gpc_reg_operand (operands[1], SFmode))
8470 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)"
8471 "@
8472 mr %0,%1
8473 {l%U1%X1|lwz%U1%X1} %0,%1
8474 {st%U0%X0|stw%U0%X0} %1,%0
8475 fmr %0,%1
8476 lfs%U1%X1 %0,%1
8477 stfs%U0%X0 %1,%0
8478 mt%0 %1
8479 mt%0 %1
8480 mf%1 %0
8481 {cror 0,0,0|nop}
8482 #
8483 #"
8484 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
8485 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
8487 (define_insn "*movsf_softfloat"
8488 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,*h")
8489 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,G,Fn,0"))]
8490 "(gpc_reg_operand (operands[0], SFmode)
8491 || gpc_reg_operand (operands[1], SFmode))
8492 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8493 "@
8494 mr %0,%1
8495 mt%0 %1
8496 mt%0 %1
8497 mf%1 %0
8498 {l%U1%X1|lwz%U1%X1} %0,%1
8499 {st%U0%X0|stw%U0%X0} %1,%0
8500 {lil|li} %0,%1
8501 {liu|lis} %0,%v1
8502 #
8503 #
8504 {cror 0,0,0|nop}"
8505 [(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*")
8506 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,4")])
8508 \f
8509 (define_expand "movdf"
8510 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8511 (match_operand:DF 1 "any_operand" ""))]
8512 ""
8513 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
8515 (define_split
8516 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8517 (match_operand:DF 1 "const_int_operand" ""))]
8518 "! TARGET_POWERPC64 && reload_completed
8519 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8520 || (GET_CODE (operands[0]) == SUBREG
8521 && GET_CODE (SUBREG_REG (operands[0])) == REG
8522 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8523 [(set (match_dup 2) (match_dup 4))
8524 (set (match_dup 3) (match_dup 1))]
8525 "
8526 {
8527 int endian = (WORDS_BIG_ENDIAN == 0);
8528 HOST_WIDE_INT value = INTVAL (operands[1]);
8530 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8531 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8532 #if HOST_BITS_PER_WIDE_INT == 32
8533 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8534 #else
8535 operands[4] = GEN_INT (value >> 32);
8536 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8537 #endif
8538 }")
8540 (define_split
8541 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8542 (match_operand:DF 1 "const_double_operand" ""))]
8543 "! TARGET_POWERPC64 && reload_completed
8544 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8545 || (GET_CODE (operands[0]) == SUBREG
8546 && GET_CODE (SUBREG_REG (operands[0])) == REG
8547 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8548 [(set (match_dup 2) (match_dup 4))
8549 (set (match_dup 3) (match_dup 5))]
8550 "
8551 {
8552 int endian = (WORDS_BIG_ENDIAN == 0);
8553 long l[2];
8554 REAL_VALUE_TYPE rv;
8556 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8557 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8559 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8560 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8561 operands[4] = gen_int_mode (l[endian], SImode);
8562 operands[5] = gen_int_mode (l[1 - endian], SImode);
8563 }")
8565 (define_split
8566 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8567 (match_operand:DF 1 "const_double_operand" ""))]
8568 "TARGET_POWERPC64 && reload_completed
8569 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8570 || (GET_CODE (operands[0]) == SUBREG
8571 && GET_CODE (SUBREG_REG (operands[0])) == REG
8572 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8573 [(set (match_dup 2) (match_dup 3))]
8574 "
8575 {
8576 int endian = (WORDS_BIG_ENDIAN == 0);
8577 long l[2];
8578 REAL_VALUE_TYPE rv;
8579 #if HOST_BITS_PER_WIDE_INT >= 64
8580 HOST_WIDE_INT val;
8581 #endif
8583 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8584 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8586 operands[2] = gen_lowpart (DImode, operands[0]);
8587 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8588 #if HOST_BITS_PER_WIDE_INT >= 64
8589 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8590 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8592 operands[3] = gen_int_mode (val, DImode);
8593 #else
8594 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8595 #endif
8596 }")
8598 ;; Don't have reload use general registers to load a constant. It is
8599 ;; less efficient than loading the constant into an FP register, since
8600 ;; it will probably be used there.
8601 (define_insn "*movdf_hardfloat32"
8602 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,m,d,d,wa,!r,!r,!r")
8603 (match_operand:DF 1 "input_operand" "r,Y,r,ws,wa,Z,Z,ws,wa,d,m,d,j,G,H,F"))]
8604 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8605 && (gpc_reg_operand (operands[0], DFmode)
8606 || gpc_reg_operand (operands[1], DFmode))"
8607 "*
8608 {
8609 switch (which_alternative)
8610 {
8611 default:
8612 gcc_unreachable ();
8613 case 0:
8614 case 1:
8615 case 2:
8616 return \"#\";
8617 case 3:
8618 case 4:
8619 return \"xxlor %x0,%x1,%x1\";
8620 case 5:
8621 case 6:
8622 return \"lxsd%U1x %x0,%y1\";
8623 case 7:
8624 case 8:
8625 return \"stxsd%U0x %x1,%y0\";
8626 case 9:
8627 return \"stfd%U0%X0 %1,%0\";
8628 case 10:
8629 return \"lfd%U1%X1 %0,%1\";
8630 case 11:
8631 return \"fmr %0,%1\";
8632 case 12:
8633 return \"xxlxor %x0,%x0,%x0\";
8634 case 13:
8635 case 14:
8636 case 15:
8637 return \"#\";
8638 }
8639 }"
8640 [(set_attr "type" "store,load,two,fp,fp,fpload,fpload,fpstore,fpstore,fpstore,fpload,fp,vecsimple,*,*,*")
8641 (set_attr "length" "8,8,8,4,4,4,4,4,4,4,4,4,4,8,12,16")])
8643 (define_insn "*movdf_softfloat32"
8644 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
8645 (match_operand:DF 1 "input_operand" "r,Y,r,G,H,F"))]
8646 "! TARGET_POWERPC64
8647 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT)
8648 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
8649 && (gpc_reg_operand (operands[0], DFmode)
8650 || gpc_reg_operand (operands[1], DFmode))"
8651 "#"
8652 [(set_attr "type" "store,load,two,*,*,*")
8653 (set_attr "length" "8,8,8,8,12,16")])
8655 ;; Reload patterns to support gpr load/store with misaligned mem.
8656 ;; and multiple gpr load/store at offset >= 0xfffc
8657 (define_expand "reload_<mode>_store"
8658 [(parallel [(match_operand 0 "memory_operand" "=m")
8659 (match_operand 1 "gpc_reg_operand" "r")
8660 (match_operand:GPR 2 "register_operand" "=&b")])]
8661 ""
8662 {
8663 rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true);
8664 DONE;
8665 })
8667 (define_expand "reload_<mode>_load"
8668 [(parallel [(match_operand 0 "gpc_reg_operand" "=r")
8669 (match_operand 1 "memory_operand" "m")
8670 (match_operand:GPR 2 "register_operand" "=b")])]
8671 ""
8672 {
8673 rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false);
8674 DONE;
8675 })
8677 ; ld/std require word-aligned displacements -> 'Y' constraint.
8678 ; List Y->r and r->Y before r->r for reload.
8679 (define_insn "*movdf_hardfloat64_mfpgpr"
8680 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,m,d,d,wa,*c*l,!r,*h,!r,!r,!r,r,d")
8681 (match_operand:DF 1 "input_operand" "r,Y,r,ws,?wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F,d,r"))]
8682 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8683 && TARGET_DOUBLE_FLOAT
8684 && (gpc_reg_operand (operands[0], DFmode)
8685 || gpc_reg_operand (operands[1], DFmode))"
8686 "@
8687 std%U0%X0 %1,%0
8688 ld%U1%X1 %0,%1
8689 mr %0,%1
8690 xxlor %x0,%x1,%x1
8691 xxlor %x0,%x1,%x1
8692 lxsd%U1x %x0,%y1
8693 lxsd%U1x %x0,%y1
8694 stxsd%U0x %x1,%y0
8695 stxsd%U0x %x1,%y0
8696 stfd%U0%X0 %1,%0
8697 lfd%U1%X1 %0,%1
8698 fmr %0,%1
8699 xxlxor %x0,%x0,%x0
8700 mt%0 %1
8701 mf%1 %0
8702 {cror 0,0,0|nop}
8703 #
8704 #
8705 #
8706 mftgpr %0,%1
8707 mffgpr %0,%1"
8708 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fpstore,fpload,fp,vecsimple,mtjmpr,mfjmpr,*,*,*,*,mftgpr,mffgpr")
8709 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4")])
8711 ; ld/std require word-aligned displacements -> 'Y' constraint.
8712 ; List Y->r and r->Y before r->r for reload.
8713 (define_insn "*movdf_hardfloat64"
8714 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,ws,?wa,ws,?wa,Z,?Z,m,d,d,wa,*c*l,!r,*h,!r,!r,!r")
8715 (match_operand:DF 1 "input_operand" "r,Y,r,ws,wa,Z,Z,ws,wa,d,m,d,j,r,h,0,G,H,F"))]
8716 "TARGET_POWERPC64 && !TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
8717 && TARGET_DOUBLE_FLOAT
8718 && (gpc_reg_operand (operands[0], DFmode)
8719 || gpc_reg_operand (operands[1], DFmode))"
8720 "@
8721 std%U0%X0 %1,%0
8722 ld%U1%X1 %0,%1
8723 mr %0,%1
8724 xxlor %x0,%x1,%x1
8725 xxlor %x0,%x1,%x1
8726 lxsd%U1x %x0,%y1
8727 lxsd%U1x %x0,%y1
8728 stxsd%U0x %x1,%y0
8729 stxsd%U0x %x1,%y0
8730 stfd%U0%X0 %1,%0
8731 lfd%U1%X1 %0,%1
8732 fmr %0,%1
8733 xxlxor %x0,%x0,%x0
8734 mt%0 %1
8735 mf%1 %0
8736 {cror 0,0,0|nop}
8737 #
8738 #
8739 #"
8740 [(set_attr "type" "store,load,*,fp,fp,fpload,fpload,fpstore,fpstore,fpstore,fpload,fp,vecsimple,mtjmpr,mfjmpr,*,*,*,*")
8741 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16")])
8743 (define_insn "*movdf_softfloat64"
8744 [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
8745 (match_operand:DF 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
8746 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8747 && (gpc_reg_operand (operands[0], DFmode)
8748 || gpc_reg_operand (operands[1], DFmode))"
8749 "@
8750 std%U0%X0 %1,%0
8751 ld%U1%X1 %0,%1
8752 mr %0,%1
8753 mt%0 %1
8754 mf%1 %0
8755 #
8756 #
8757 #
8758 {cror 0,0,0|nop}"
8759 [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*")
8760 (set_attr "length" "4,4,4,4,4,8,12,16,4")])
8761 \f
8762 (define_expand "movtf"
8763 [(set (match_operand:TF 0 "general_operand" "")
8764 (match_operand:TF 1 "any_operand" ""))]
8765 "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128"
8766 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8768 ;; It's important to list Y->r and r->Y before r->r because otherwise
8769 ;; reload, given m->r, will try to pick r->r and reload it, which
8770 ;; doesn't make progress.
8771 (define_insn_and_split "*movtf_internal"
8772 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
8773 (match_operand:TF 1 "input_operand" "d,m,d,r,YGHF,r"))]
8774 "!TARGET_IEEEQUAD
8775 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
8776 && (gpc_reg_operand (operands[0], TFmode)
8777 || gpc_reg_operand (operands[1], TFmode))"
8778 "#"
8779 "&& reload_completed"
8780 [(pc)]
8781 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8782 [(set_attr "length" "8,8,8,20,20,16")])
8784 (define_insn_and_split "*movtf_softfloat"
8785 [(set (match_operand:TF 0 "rs6000_nonimmediate_operand" "=Y,r,r")
8786 (match_operand:TF 1 "input_operand" "r,YGHF,r"))]
8787 "!TARGET_IEEEQUAD
8788 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_LONG_DOUBLE_128
8789 && (gpc_reg_operand (operands[0], TFmode)
8790 || gpc_reg_operand (operands[1], TFmode))"
8791 "#"
8792 "&& reload_completed"
8793 [(pc)]
8794 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; }
8795 [(set_attr "length" "20,20,16")])
8797 (define_expand "extenddftf2"
8798 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8799 (float_extend:TF (match_operand:DF 1 "input_operand" "")))]
8800 "!TARGET_IEEEQUAD
8801 && TARGET_HARD_FLOAT
8802 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8803 && TARGET_LONG_DOUBLE_128"
8804 {
8805 if (TARGET_E500_DOUBLE)
8806 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1]));
8807 else
8808 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1]));
8809 DONE;
8810 })
8812 (define_expand "extenddftf2_fprs"
8813 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "")
8814 (float_extend:TF (match_operand:DF 1 "input_operand" "")))
8815 (use (match_dup 2))])]
8816 "!TARGET_IEEEQUAD
8817 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8818 && TARGET_LONG_DOUBLE_128"
8819 {
8820 operands[2] = CONST0_RTX (DFmode);
8821 /* Generate GOT reference early for SVR4 PIC. */
8822 if (DEFAULT_ABI == ABI_V4 && flag_pic)
8823 operands[2] = validize_mem (force_const_mem (DFmode, operands[2]));
8824 })
8826 (define_insn_and_split "*extenddftf2_internal"
8827 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r")
8828 (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF")))
8829 (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))]
8830 "!TARGET_IEEEQUAD
8831 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8832 && TARGET_LONG_DOUBLE_128"
8833 "#"
8834 "&& reload_completed"
8835 [(pc)]
8836 {
8837 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
8838 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
8839 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word),
8840 operands[1]);
8841 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word),
8842 operands[2]);
8843 DONE;
8844 })
8846 (define_expand "extendsftf2"
8847 [(set (match_operand:TF 0 "nonimmediate_operand" "")
8848 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))]
8849 "!TARGET_IEEEQUAD
8850 && TARGET_HARD_FLOAT
8851 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8852 && TARGET_LONG_DOUBLE_128"
8853 {
8854 rtx tmp = gen_reg_rtx (DFmode);
8855 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
8856 emit_insn (gen_extenddftf2 (operands[0], tmp));
8857 DONE;
8858 })
8860 (define_expand "trunctfdf2"
8861 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8862 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))]
8863 "!TARGET_IEEEQUAD
8864 && TARGET_HARD_FLOAT
8865 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8866 && TARGET_LONG_DOUBLE_128"
8867 "")
8869 (define_insn_and_split "trunctfdf2_internal1"
8870 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d")
8871 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))]
8872 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
8873 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8874 "@
8875 #
8876 fmr %0,%1"
8877 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])"
8878 [(const_int 0)]
8879 {
8880 emit_note (NOTE_INSN_DELETED);
8881 DONE;
8882 }
8883 [(set_attr "type" "fp")])
8885 (define_insn "trunctfdf2_internal2"
8886 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8887 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))]
8888 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
8889 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
8890 && TARGET_LONG_DOUBLE_128"
8891 "fadd %0,%1,%L1"
8892 [(set_attr "type" "fp")
8893 (set_attr "fp_type" "fp_addsub_d")])
8895 (define_expand "trunctfsf2"
8896 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8897 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))]
8898 "!TARGET_IEEEQUAD
8899 && TARGET_HARD_FLOAT
8900 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8901 && TARGET_LONG_DOUBLE_128"
8902 {
8903 if (TARGET_E500_DOUBLE)
8904 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1]));
8905 else
8906 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1]));
8907 DONE;
8908 })
8910 (define_insn_and_split "trunctfsf2_fprs"
8911 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8912 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d")))
8913 (clobber (match_scratch:DF 2 "=d"))]
8914 "!TARGET_IEEEQUAD
8915 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT
8916 && TARGET_LONG_DOUBLE_128"
8917 "#"
8918 "&& reload_completed"
8919 [(set (match_dup 2)
8920 (float_truncate:DF (match_dup 1)))
8921 (set (match_dup 0)
8922 (float_truncate:SF (match_dup 2)))]
8923 "")
8925 (define_expand "floatsitf2"
8926 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8927 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))]
8928 "!TARGET_IEEEQUAD
8929 && TARGET_HARD_FLOAT
8930 && (TARGET_FPRS || TARGET_E500_DOUBLE)
8931 && TARGET_LONG_DOUBLE_128"
8932 {
8933 rtx tmp = gen_reg_rtx (DFmode);
8934 expand_float (tmp, operands[1], false);
8935 emit_insn (gen_extenddftf2 (operands[0], tmp));
8936 DONE;
8937 })
8939 ; fadd, but rounding towards zero.
8940 ; This is probably not the optimal code sequence.
8941 (define_insn "fix_trunc_helper"
8942 [(set (match_operand:DF 0 "gpc_reg_operand" "=d")
8943 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")]
8944 UNSPEC_FIX_TRUNC_TF))
8945 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))]
8946 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
8947 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2"
8948 [(set_attr "type" "fp")
8949 (set_attr "length" "20")])
8951 (define_expand "fix_trunctfsi2"
8952 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8953 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))]
8954 "!TARGET_IEEEQUAD && TARGET_POWERPC && TARGET_HARD_FLOAT
8955 && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128"
8956 {
8957 if (TARGET_E500_DOUBLE)
8958 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1]));
8959 else
8960 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1]));
8961 DONE;
8962 })
8964 (define_expand "fix_trunctfsi2_fprs"
8965 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
8966 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))
8967 (clobber (match_dup 2))
8968 (clobber (match_dup 3))
8969 (clobber (match_dup 4))
8970 (clobber (match_dup 5))])]
8971 "!TARGET_IEEEQUAD && TARGET_POWERPC
8972 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8973 {
8974 operands[2] = gen_reg_rtx (DFmode);
8975 operands[3] = gen_reg_rtx (DFmode);
8976 operands[4] = gen_reg_rtx (DImode);
8977 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode));
8978 })
8980 (define_insn_and_split "*fix_trunctfsi2_internal"
8981 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8982 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d")))
8983 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d"))
8984 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d"))
8985 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d"))
8986 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))]
8987 "!TARGET_IEEEQUAD
8988 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8989 "#"
8990 ""
8991 [(pc)]
8992 {
8993 rtx lowword;
8994 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3]));
8996 gcc_assert (MEM_P (operands[5]));
8997 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0);
8999 emit_insn (gen_fctiwz_df (operands[4], operands[2]));
9000 emit_move_insn (operands[5], operands[4]);
9001 emit_move_insn (operands[0], lowword);
9002 DONE;
9003 })
9005 (define_expand "negtf2"
9006 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9007 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9008 "!TARGET_IEEEQUAD
9009 && TARGET_HARD_FLOAT
9010 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9011 && TARGET_LONG_DOUBLE_128"
9012 "")
9014 (define_insn "negtf2_internal"
9015 [(set (match_operand:TF 0 "gpc_reg_operand" "=d")
9016 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))]
9017 "!TARGET_IEEEQUAD
9018 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9019 "*
9020 {
9021 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9022 return \"fneg %L0,%L1\;fneg %0,%1\";
9023 else
9024 return \"fneg %0,%1\;fneg %L0,%L1\";
9025 }"
9026 [(set_attr "type" "fp")
9027 (set_attr "length" "8")])
9029 (define_expand "abstf2"
9030 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9031 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))]
9032 "!TARGET_IEEEQUAD
9033 && TARGET_HARD_FLOAT
9034 && (TARGET_FPRS || TARGET_E500_DOUBLE)
9035 && TARGET_LONG_DOUBLE_128"
9036 "
9037 {
9038 rtx label = gen_label_rtx ();
9039 if (TARGET_E500_DOUBLE)
9040 {
9041 if (flag_finite_math_only && !flag_trapping_math)
9042 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label));
9043 else
9044 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label));
9045 }
9046 else
9047 emit_insn (gen_abstf2_internal (operands[0], operands[1], label));
9048 emit_label (label);
9049 DONE;
9050 }")
9052 (define_expand "abstf2_internal"
9053 [(set (match_operand:TF 0 "gpc_reg_operand" "")
9054 (match_operand:TF 1 "gpc_reg_operand" ""))
9055 (set (match_dup 3) (match_dup 5))
9056 (set (match_dup 5) (abs:DF (match_dup 5)))
9057 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5)))
9058 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
9059 (label_ref (match_operand 2 "" ""))
9060 (pc)))
9061 (set (match_dup 6) (neg:DF (match_dup 6)))]
9062 "!TARGET_IEEEQUAD
9063 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
9064 && TARGET_LONG_DOUBLE_128"
9065 "
9066 {
9067 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
9068 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
9069 operands[3] = gen_reg_rtx (DFmode);
9070 operands[4] = gen_reg_rtx (CCFPmode);
9071 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word);
9072 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word);
9073 }")
9074 \f
9075 ;; Next come the multi-word integer load and store and the load and store
9076 ;; multiple insns.
9078 ;; List r->r after r->Y, otherwise reload will try to reload a
9079 ;; non-offsettable address by using r->r which won't make progress.
9080 ;; Use of fprs is disparaged slightly otherwise reload prefers to reload
9081 ;; a gpr into a fpr instead of reloading an invalid 'Y' address
9082 (define_insn "*movdi_internal32"
9083 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r,?wa")
9084 (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF,O"))]
9085 "! TARGET_POWERPC64
9086 && (gpc_reg_operand (operands[0], DImode)
9087 || gpc_reg_operand (operands[1], DImode))"
9088 "@
9089 #
9090 #
9091 #
9092 stfd%U0%X0 %1,%0
9093 lfd%U1%X1 %0,%1
9094 fmr %0,%1
9095 #
9096 xxlxor %x0,%x0,%x0"
9097 [(set_attr "type" "store,load,*,fpstore,fpload,fp,*,vecsimple")])
9099 (define_split
9100 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9101 (match_operand:DI 1 "const_int_operand" ""))]
9102 "! TARGET_POWERPC64 && reload_completed
9103 && gpr_or_gpr_p (operands[0], operands[1])"
9104 [(set (match_dup 2) (match_dup 4))
9105 (set (match_dup 3) (match_dup 1))]
9106 "
9107 {
9108 HOST_WIDE_INT value = INTVAL (operands[1]);
9109 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9110 DImode);
9111 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9112 DImode);
9113 #if HOST_BITS_PER_WIDE_INT == 32
9114 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9115 #else
9116 operands[4] = GEN_INT (value >> 32);
9117 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9118 #endif
9119 }")
9121 (define_split
9122 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "")
9123 (match_operand:DIFD 1 "input_operand" ""))]
9124 "reload_completed && !TARGET_POWERPC64
9125 && gpr_or_gpr_p (operands[0], operands[1])"
9126 [(pc)]
9127 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9129 (define_insn "*movdi_mfpgpr"
9130 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*d")
9131 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*d,r"))]
9132 "TARGET_POWERPC64 && TARGET_MFPGPR && TARGET_HARD_FLOAT && TARGET_FPRS
9133 && (gpc_reg_operand (operands[0], DImode)
9134 || gpc_reg_operand (operands[1], DImode))"
9135 "@
9136 std%U0%X0 %1,%0
9137 ld%U1%X1 %0,%1
9138 mr %0,%1
9139 li %0,%1
9140 lis %0,%v1
9141 #
9142 stfd%U0%X0 %1,%0
9143 lfd%U1%X1 %0,%1
9144 fmr %0,%1
9145 mf%1 %0
9146 mt%0 %1
9147 {cror 0,0,0|nop}
9148 mftgpr %0,%1
9149 mffgpr %0,%1"
9150 [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,mftgpr,mffgpr")
9151 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4")])
9153 (define_insn "*movdi_internal64"
9154 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,?wa")
9155 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,O"))]
9156 "TARGET_POWERPC64 && (!TARGET_MFPGPR || !TARGET_HARD_FLOAT || !TARGET_FPRS)
9157 && (gpc_reg_operand (operands[0], DImode)
9158 || gpc_reg_operand (operands[1], DImode))"
9159 "@
9160 std%U0%X0 %1,%0
9161 ld%U1%X1 %0,%1
9162 mr %0,%1
9163 li %0,%1
9164 lis %0,%v1
9165 #
9166 stfd%U0%X0 %1,%0
9167 lfd%U1%X1 %0,%1
9168 fmr %0,%1
9169 mf%1 %0
9170 mt%0 %1
9171 {cror 0,0,0|nop}
9172 xxlxor %x0,%x0,%x0"
9173 [(set_attr "type" "store,load,*,*,*,*,fpstore,fpload,fp,mfjmpr,mtjmpr,*,vecsimple")
9174 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
9176 ;; immediate value valid for a single instruction hiding in a const_double
9177 (define_insn ""
9178 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9179 (match_operand:DI 1 "const_double_operand" "F"))]
9180 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9181 && GET_CODE (operands[1]) == CONST_DOUBLE
9182 && num_insns_constant (operands[1], DImode) == 1"
9183 "*
9184 {
9185 return ((unsigned HOST_WIDE_INT)
9186 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9187 ? \"li %0,%1\" : \"lis %0,%v1\";
9188 }")
9190 ;; Generate all one-bits and clear left or right.
9191 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9192 (define_split
9193 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9194 (match_operand:DI 1 "mask64_operand" ""))]
9195 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9196 [(set (match_dup 0) (const_int -1))
9197 (set (match_dup 0)
9198 (and:DI (rotate:DI (match_dup 0)
9199 (const_int 0))
9200 (match_dup 1)))]
9201 "")
9203 ;; Split a load of a large constant into the appropriate five-instruction
9204 ;; sequence. Handle anything in a constant number of insns.
9205 ;; When non-easy constants can go in the TOC, this should use
9206 ;; easy_fp_constant predicate.
9207 (define_split
9208 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9209 (match_operand:DI 1 "const_int_operand" ""))]
9210 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9211 [(set (match_dup 0) (match_dup 2))
9212 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9213 "
9214 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9216 if (tem == operands[0])
9217 DONE;
9218 else
9219 FAIL;
9220 }")
9222 (define_split
9223 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9224 (match_operand:DI 1 "const_double_operand" ""))]
9225 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9226 [(set (match_dup 0) (match_dup 2))
9227 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9228 "
9229 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9231 if (tem == operands[0])
9232 DONE;
9233 else
9234 FAIL;
9235 }")
9236 \f
9237 ;; TImode is similar, except that we usually want to compute the address into
9238 ;; a register and use lsi/stsi (the exception is during reload).
9240 (define_insn "*movti_string"
9241 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r")
9242 (match_operand:TI 1 "input_operand" "r,r,Q,Y,r,n"))]
9243 "! TARGET_POWERPC64
9244 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9245 "*
9246 {
9247 switch (which_alternative)
9248 {
9249 default:
9250 gcc_unreachable ();
9251 case 0:
9252 if (TARGET_STRING)
9253 return \"{stsi|stswi} %1,%P0,16\";
9254 case 1:
9255 return \"#\";
9256 case 2:
9257 /* If the address is not used in the output, we can use lsi. Otherwise,
9258 fall through to generating four loads. */
9259 if (TARGET_STRING
9260 && ! reg_overlap_mentioned_p (operands[0], operands[1]))
9261 return \"{lsi|lswi} %0,%P1,16\";
9262 /* ... fall through ... */
9263 case 3:
9264 case 4:
9265 case 5:
9266 return \"#\";
9267 }
9268 }"
9269 [(set_attr "type" "store_ux,store_ux,load_ux,load_ux,*,*")
9270 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING")
9271 (const_string "always")
9272 (const_string "conditional")))])
9274 (define_insn "*movti_ppc64"
9275 [(set (match_operand:TI 0 "nonimmediate_operand" "=Y,r,r")
9276 (match_operand:TI 1 "input_operand" "r,Y,r"))]
9277 "(TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9278 || gpc_reg_operand (operands[1], TImode)))
9279 && VECTOR_MEM_NONE_P (TImode)"
9280 "#"
9281 [(set_attr "type" "store,load,*")])
9283 (define_split
9284 [(set (match_operand:TI 0 "gpc_reg_operand" "")
9285 (match_operand:TI 1 "const_double_operand" ""))]
9286 "TARGET_POWERPC64 && VECTOR_MEM_NONE_P (TImode)"
9287 [(set (match_dup 2) (match_dup 4))
9288 (set (match_dup 3) (match_dup 5))]
9289 "
9290 {
9291 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9292 TImode);
9293 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9294 TImode);
9295 if (GET_CODE (operands[1]) == CONST_DOUBLE)
9296 {
9297 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9298 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9299 }
9300 else if (GET_CODE (operands[1]) == CONST_INT)
9301 {
9302 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0));
9303 operands[5] = operands[1];
9304 }
9305 else
9306 FAIL;
9307 }")
9309 (define_split
9310 [(set (match_operand:TI 0 "nonimmediate_operand" "")
9311 (match_operand:TI 1 "input_operand" ""))]
9312 "reload_completed && VECTOR_MEM_NONE_P (TImode)
9313 && gpr_or_gpr_p (operands[0], operands[1])"
9314 [(pc)]
9315 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
9316 \f
9317 (define_expand "load_multiple"
9318 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9319 (match_operand:SI 1 "" ""))
9320 (use (match_operand:SI 2 "" ""))])]
9321 "TARGET_STRING && !TARGET_POWERPC64"
9322 "
9323 {
9324 int regno;
9325 int count;
9326 rtx op1;
9327 int i;
9329 /* Support only loading a constant number of fixed-point registers from
9330 memory and only bother with this if more than two; the machine
9331 doesn't support more than eight. */
9332 if (GET_CODE (operands[2]) != CONST_INT
9333 || INTVAL (operands[2]) <= 2
9334 || INTVAL (operands[2]) > 8
9335 || GET_CODE (operands[1]) != MEM
9336 || GET_CODE (operands[0]) != REG
9337 || REGNO (operands[0]) >= 32)
9338 FAIL;
9340 count = INTVAL (operands[2]);
9341 regno = REGNO (operands[0]);
9343 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9344 op1 = replace_equiv_address (operands[1],
9345 force_reg (SImode, XEXP (operands[1], 0)));
9347 for (i = 0; i < count; i++)
9348 XVECEXP (operands[3], 0, i)
9349 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9350 adjust_address_nv (op1, SImode, i * 4));
9351 }")
9353 (define_insn "*ldmsi8"
9354 [(match_parallel 0 "load_multiple_operation"
9355 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9356 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9357 (set (match_operand:SI 3 "gpc_reg_operand" "")
9358 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9359 (set (match_operand:SI 4 "gpc_reg_operand" "")
9360 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9361 (set (match_operand:SI 5 "gpc_reg_operand" "")
9362 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9363 (set (match_operand:SI 6 "gpc_reg_operand" "")
9364 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9365 (set (match_operand:SI 7 "gpc_reg_operand" "")
9366 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9367 (set (match_operand:SI 8 "gpc_reg_operand" "")
9368 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9369 (set (match_operand:SI 9 "gpc_reg_operand" "")
9370 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9371 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9372 "*
9373 { return rs6000_output_load_multiple (operands); }"
9374 [(set_attr "type" "load_ux")
9375 (set_attr "length" "32")])
9377 (define_insn "*ldmsi7"
9378 [(match_parallel 0 "load_multiple_operation"
9379 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9380 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9381 (set (match_operand:SI 3 "gpc_reg_operand" "")
9382 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9383 (set (match_operand:SI 4 "gpc_reg_operand" "")
9384 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9385 (set (match_operand:SI 5 "gpc_reg_operand" "")
9386 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9387 (set (match_operand:SI 6 "gpc_reg_operand" "")
9388 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9389 (set (match_operand:SI 7 "gpc_reg_operand" "")
9390 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9391 (set (match_operand:SI 8 "gpc_reg_operand" "")
9392 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9393 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9394 "*
9395 { return rs6000_output_load_multiple (operands); }"
9396 [(set_attr "type" "load_ux")
9397 (set_attr "length" "32")])
9399 (define_insn "*ldmsi6"
9400 [(match_parallel 0 "load_multiple_operation"
9401 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9402 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9403 (set (match_operand:SI 3 "gpc_reg_operand" "")
9404 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9405 (set (match_operand:SI 4 "gpc_reg_operand" "")
9406 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9407 (set (match_operand:SI 5 "gpc_reg_operand" "")
9408 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9409 (set (match_operand:SI 6 "gpc_reg_operand" "")
9410 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9411 (set (match_operand:SI 7 "gpc_reg_operand" "")
9412 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9413 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9414 "*
9415 { return rs6000_output_load_multiple (operands); }"
9416 [(set_attr "type" "load_ux")
9417 (set_attr "length" "32")])
9419 (define_insn "*ldmsi5"
9420 [(match_parallel 0 "load_multiple_operation"
9421 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9422 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9423 (set (match_operand:SI 3 "gpc_reg_operand" "")
9424 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9425 (set (match_operand:SI 4 "gpc_reg_operand" "")
9426 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9427 (set (match_operand:SI 5 "gpc_reg_operand" "")
9428 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9429 (set (match_operand:SI 6 "gpc_reg_operand" "")
9430 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9431 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9432 "*
9433 { return rs6000_output_load_multiple (operands); }"
9434 [(set_attr "type" "load_ux")
9435 (set_attr "length" "32")])
9437 (define_insn "*ldmsi4"
9438 [(match_parallel 0 "load_multiple_operation"
9439 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9440 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9441 (set (match_operand:SI 3 "gpc_reg_operand" "")
9442 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9443 (set (match_operand:SI 4 "gpc_reg_operand" "")
9444 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9445 (set (match_operand:SI 5 "gpc_reg_operand" "")
9446 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9447 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9448 "*
9449 { return rs6000_output_load_multiple (operands); }"
9450 [(set_attr "type" "load_ux")
9451 (set_attr "length" "32")])
9453 (define_insn "*ldmsi3"
9454 [(match_parallel 0 "load_multiple_operation"
9455 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9456 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9457 (set (match_operand:SI 3 "gpc_reg_operand" "")
9458 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9459 (set (match_operand:SI 4 "gpc_reg_operand" "")
9460 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9461 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9462 "*
9463 { return rs6000_output_load_multiple (operands); }"
9464 [(set_attr "type" "load_ux")
9465 (set_attr "length" "32")])
9467 (define_expand "store_multiple"
9468 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9469 (match_operand:SI 1 "" ""))
9470 (clobber (scratch:SI))
9471 (use (match_operand:SI 2 "" ""))])]
9472 "TARGET_STRING && !TARGET_POWERPC64"
9473 "
9474 {
9475 int regno;
9476 int count;
9477 rtx to;
9478 rtx op0;
9479 int i;
9481 /* Support only storing a constant number of fixed-point registers to
9482 memory and only bother with this if more than two; the machine
9483 doesn't support more than eight. */
9484 if (GET_CODE (operands[2]) != CONST_INT
9485 || INTVAL (operands[2]) <= 2
9486 || INTVAL (operands[2]) > 8
9487 || GET_CODE (operands[0]) != MEM
9488 || GET_CODE (operands[1]) != REG
9489 || REGNO (operands[1]) >= 32)
9490 FAIL;
9492 count = INTVAL (operands[2]);
9493 regno = REGNO (operands[1]);
9495 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9496 to = force_reg (SImode, XEXP (operands[0], 0));
9497 op0 = replace_equiv_address (operands[0], to);
9499 XVECEXP (operands[3], 0, 0)
9500 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9501 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9502 gen_rtx_SCRATCH (SImode));
9504 for (i = 1; i < count; i++)
9505 XVECEXP (operands[3], 0, i + 1)
9506 = gen_rtx_SET (VOIDmode,
9507 adjust_address_nv (op0, SImode, i * 4),
9508 gen_rtx_REG (SImode, regno + i));
9509 }")
9511 (define_insn "*stmsi8"
9512 [(match_parallel 0 "store_multiple_operation"
9513 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9514 (match_operand:SI 2 "gpc_reg_operand" "r"))
9515 (clobber (match_scratch:SI 3 "=X"))
9516 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9517 (match_operand:SI 4 "gpc_reg_operand" "r"))
9518 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9519 (match_operand:SI 5 "gpc_reg_operand" "r"))
9520 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9521 (match_operand:SI 6 "gpc_reg_operand" "r"))
9522 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9523 (match_operand:SI 7 "gpc_reg_operand" "r"))
9524 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9525 (match_operand:SI 8 "gpc_reg_operand" "r"))
9526 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9527 (match_operand:SI 9 "gpc_reg_operand" "r"))
9528 (set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
9529 (match_operand:SI 10 "gpc_reg_operand" "r"))])]
9530 "TARGET_STRING && XVECLEN (operands[0], 0) == 9"
9531 "{stsi|stswi} %2,%1,%O0"
9532 [(set_attr "type" "store_ux")
9533 (set_attr "cell_micro" "always")])
9535 (define_insn "*stmsi7"
9536 [(match_parallel 0 "store_multiple_operation"
9537 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9538 (match_operand:SI 2 "gpc_reg_operand" "r"))
9539 (clobber (match_scratch:SI 3 "=X"))
9540 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9541 (match_operand:SI 4 "gpc_reg_operand" "r"))
9542 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9543 (match_operand:SI 5 "gpc_reg_operand" "r"))
9544 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9545 (match_operand:SI 6 "gpc_reg_operand" "r"))
9546 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9547 (match_operand:SI 7 "gpc_reg_operand" "r"))
9548 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9549 (match_operand:SI 8 "gpc_reg_operand" "r"))
9550 (set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
9551 (match_operand:SI 9 "gpc_reg_operand" "r"))])]
9552 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9553 "{stsi|stswi} %2,%1,%O0"
9554 [(set_attr "type" "store_ux")
9555 (set_attr "cell_micro" "always")])
9557 (define_insn "*stmsi6"
9558 [(match_parallel 0 "store_multiple_operation"
9559 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9560 (match_operand:SI 2 "gpc_reg_operand" "r"))
9561 (clobber (match_scratch:SI 3 "=X"))
9562 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9563 (match_operand:SI 4 "gpc_reg_operand" "r"))
9564 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9565 (match_operand:SI 5 "gpc_reg_operand" "r"))
9566 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9567 (match_operand:SI 6 "gpc_reg_operand" "r"))
9568 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9569 (match_operand:SI 7 "gpc_reg_operand" "r"))
9570 (set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
9571 (match_operand:SI 8 "gpc_reg_operand" "r"))])]
9572 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9573 "{stsi|stswi} %2,%1,%O0"
9574 [(set_attr "type" "store_ux")
9575 (set_attr "cell_micro" "always")])
9577 (define_insn "*stmsi5"
9578 [(match_parallel 0 "store_multiple_operation"
9579 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9580 (match_operand:SI 2 "gpc_reg_operand" "r"))
9581 (clobber (match_scratch:SI 3 "=X"))
9582 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9583 (match_operand:SI 4 "gpc_reg_operand" "r"))
9584 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9585 (match_operand:SI 5 "gpc_reg_operand" "r"))
9586 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9587 (match_operand:SI 6 "gpc_reg_operand" "r"))
9588 (set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
9589 (match_operand:SI 7 "gpc_reg_operand" "r"))])]
9590 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9591 "{stsi|stswi} %2,%1,%O0"
9592 [(set_attr "type" "store_ux")
9593 (set_attr "cell_micro" "always")])
9595 (define_insn "*stmsi4"
9596 [(match_parallel 0 "store_multiple_operation"
9597 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9598 (match_operand:SI 2 "gpc_reg_operand" "r"))
9599 (clobber (match_scratch:SI 3 "=X"))
9600 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9601 (match_operand:SI 4 "gpc_reg_operand" "r"))
9602 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9603 (match_operand:SI 5 "gpc_reg_operand" "r"))
9604 (set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
9605 (match_operand:SI 6 "gpc_reg_operand" "r"))])]
9606 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9607 "{stsi|stswi} %2,%1,%O0"
9608 [(set_attr "type" "store_ux")
9609 (set_attr "cell_micro" "always")])
9611 (define_insn "*stmsi3"
9612 [(match_parallel 0 "store_multiple_operation"
9613 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9614 (match_operand:SI 2 "gpc_reg_operand" "r"))
9615 (clobber (match_scratch:SI 3 "=X"))
9616 (set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
9617 (match_operand:SI 4 "gpc_reg_operand" "r"))
9618 (set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
9619 (match_operand:SI 5 "gpc_reg_operand" "r"))])]
9620 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9621 "{stsi|stswi} %2,%1,%O0"
9622 [(set_attr "type" "store_ux")
9623 (set_attr "cell_micro" "always")])
9624 \f
9625 (define_expand "setmemsi"
9626 [(parallel [(set (match_operand:BLK 0 "" "")
9627 (match_operand 2 "const_int_operand" ""))
9628 (use (match_operand:SI 1 "" ""))
9629 (use (match_operand:SI 3 "" ""))])]
9630 ""
9631 "
9632 {
9633 /* If value to set is not zero, use the library routine. */
9634 if (operands[2] != const0_rtx)
9635 FAIL;
9637 if (expand_block_clear (operands))
9638 DONE;
9639 else
9640 FAIL;
9641 }")
9643 ;; String/block move insn.
9644 ;; Argument 0 is the destination
9645 ;; Argument 1 is the source
9646 ;; Argument 2 is the length
9647 ;; Argument 3 is the alignment
9649 (define_expand "movmemsi"
9650 [(parallel [(set (match_operand:BLK 0 "" "")
9651 (match_operand:BLK 1 "" ""))
9652 (use (match_operand:SI 2 "" ""))
9653 (use (match_operand:SI 3 "" ""))])]
9654 ""
9655 "
9656 {
9657 if (expand_block_move (operands))
9658 DONE;
9659 else
9660 FAIL;
9661 }")
9663 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9664 ;; register allocator doesn't have a clue about allocating 8 word registers.
9665 ;; rD/rS = r5 is preferred, efficient form.
9666 (define_expand "movmemsi_8reg"
9667 [(parallel [(set (match_operand 0 "" "")
9668 (match_operand 1 "" ""))
9669 (use (match_operand 2 "" ""))
9670 (use (match_operand 3 "" ""))
9671 (clobber (reg:SI 5))
9672 (clobber (reg:SI 6))
9673 (clobber (reg:SI 7))
9674 (clobber (reg:SI 8))
9675 (clobber (reg:SI 9))
9676 (clobber (reg:SI 10))
9677 (clobber (reg:SI 11))
9678 (clobber (reg:SI 12))
9679 (clobber (match_scratch:SI 4 ""))])]
9680 "TARGET_STRING"
9681 "")
9683 (define_insn ""
9684 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9685 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9686 (use (match_operand:SI 2 "immediate_operand" "i"))
9687 (use (match_operand:SI 3 "immediate_operand" "i"))
9688 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9689 (clobber (reg:SI 6))
9690 (clobber (reg:SI 7))
9691 (clobber (reg:SI 8))
9692 (clobber (reg:SI 9))
9693 (clobber (reg:SI 10))
9694 (clobber (reg:SI 11))
9695 (clobber (reg:SI 12))
9696 (clobber (match_scratch:SI 5 "=X"))]
9697 "TARGET_STRING
9698 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9699 || INTVAL (operands[2]) == 0)
9700 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9701 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9702 && REGNO (operands[4]) == 5"
9703 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9704 [(set_attr "type" "store_ux")
9705 (set_attr "cell_micro" "always")
9706 (set_attr "length" "8")])
9708 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9709 ;; register allocator doesn't have a clue about allocating 6 word registers.
9710 ;; rD/rS = r5 is preferred, efficient form.
9711 (define_expand "movmemsi_6reg"
9712 [(parallel [(set (match_operand 0 "" "")
9713 (match_operand 1 "" ""))
9714 (use (match_operand 2 "" ""))
9715 (use (match_operand 3 "" ""))
9716 (clobber (reg:SI 5))
9717 (clobber (reg:SI 6))
9718 (clobber (reg:SI 7))
9719 (clobber (reg:SI 8))
9720 (clobber (reg:SI 9))
9721 (clobber (reg:SI 10))
9722 (clobber (match_scratch:SI 4 ""))])]
9723 "TARGET_STRING"
9724 "")
9726 (define_insn ""
9727 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9728 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9729 (use (match_operand:SI 2 "immediate_operand" "i"))
9730 (use (match_operand:SI 3 "immediate_operand" "i"))
9731 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9732 (clobber (reg:SI 6))
9733 (clobber (reg:SI 7))
9734 (clobber (reg:SI 8))
9735 (clobber (reg:SI 9))
9736 (clobber (reg:SI 10))
9737 (clobber (match_scratch:SI 5 "=X"))]
9738 "TARGET_STRING
9739 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9740 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9741 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9742 && REGNO (operands[4]) == 5"
9743 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9744 [(set_attr "type" "store_ux")
9745 (set_attr "cell_micro" "always")
9746 (set_attr "length" "8")])
9748 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9749 ;; problems with TImode.
9750 ;; rD/rS = r5 is preferred, efficient form.
9751 (define_expand "movmemsi_4reg"
9752 [(parallel [(set (match_operand 0 "" "")
9753 (match_operand 1 "" ""))
9754 (use (match_operand 2 "" ""))
9755 (use (match_operand 3 "" ""))
9756 (clobber (reg:SI 5))
9757 (clobber (reg:SI 6))
9758 (clobber (reg:SI 7))
9759 (clobber (reg:SI 8))
9760 (clobber (match_scratch:SI 4 ""))])]
9761 "TARGET_STRING"
9762 "")
9764 (define_insn ""
9765 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9766 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9767 (use (match_operand:SI 2 "immediate_operand" "i"))
9768 (use (match_operand:SI 3 "immediate_operand" "i"))
9769 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r"))
9770 (clobber (reg:SI 6))
9771 (clobber (reg:SI 7))
9772 (clobber (reg:SI 8))
9773 (clobber (match_scratch:SI 5 "=X"))]
9774 "TARGET_STRING
9775 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9776 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9777 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9778 && REGNO (operands[4]) == 5"
9779 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9780 [(set_attr "type" "store_ux")
9781 (set_attr "cell_micro" "always")
9782 (set_attr "length" "8")])
9784 ;; Move up to 8 bytes at a time.
9785 (define_expand "movmemsi_2reg"
9786 [(parallel [(set (match_operand 0 "" "")
9787 (match_operand 1 "" ""))
9788 (use (match_operand 2 "" ""))
9789 (use (match_operand 3 "" ""))
9790 (clobber (match_scratch:DI 4 ""))
9791 (clobber (match_scratch:SI 5 ""))])]
9792 "TARGET_STRING && ! TARGET_POWERPC64"
9793 "")
9795 (define_insn ""
9796 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9797 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9798 (use (match_operand:SI 2 "immediate_operand" "i"))
9799 (use (match_operand:SI 3 "immediate_operand" "i"))
9800 (clobber (match_scratch:DI 4 "=&r"))
9801 (clobber (match_scratch:SI 5 "=X"))]
9802 "TARGET_STRING && ! TARGET_POWERPC64
9803 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9804 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9805 [(set_attr "type" "store_ux")
9806 (set_attr "cell_micro" "always")
9807 (set_attr "length" "8")])
9809 ;; Move up to 4 bytes at a time.
9810 (define_expand "movmemsi_1reg"
9811 [(parallel [(set (match_operand 0 "" "")
9812 (match_operand 1 "" ""))
9813 (use (match_operand 2 "" ""))
9814 (use (match_operand 3 "" ""))
9815 (clobber (match_scratch:SI 4 ""))
9816 (clobber (match_scratch:SI 5 ""))])]
9817 "TARGET_STRING"
9818 "")
9820 (define_insn ""
9821 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b"))
9822 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b")))
9823 (use (match_operand:SI 2 "immediate_operand" "i"))
9824 (use (match_operand:SI 3 "immediate_operand" "i"))
9825 (clobber (match_scratch:SI 4 "=&r"))
9826 (clobber (match_scratch:SI 5 "=X"))]
9827 "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9828 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9829 [(set_attr "type" "store_ux")
9830 (set_attr "cell_micro" "always")
9831 (set_attr "length" "8")])
9832 \f
9833 ;; Define insns that do load or store with update. Some of these we can
9834 ;; get by using pre-decrement or pre-increment, but the hardware can also
9835 ;; do cases where the increment is not the size of the object.
9836 ;;
9837 ;; In all these cases, we use operands 0 and 1 for the register being
9838 ;; incremented because those are the operands that local-alloc will
9839 ;; tie and these are the pair most likely to be tieable (and the ones
9840 ;; that will benefit the most).
9842 (define_insn "*movdi_update1"
9843 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
9844 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
9845 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
9846 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
9847 (plus:DI (match_dup 1) (match_dup 2)))]
9848 "TARGET_POWERPC64 && TARGET_UPDATE
9849 && (!avoiding_indexed_address_p (DImode)
9850 || !gpc_reg_operand (operands[2], DImode))"
9851 "@
9852 ldux %3,%0,%2
9853 ldu %3,%2(%0)"
9854 [(set_attr "type" "load_ux,load_u")])
9856 (define_insn "movdi_<mode>_update"
9857 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9858 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9859 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9860 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9861 (plus:P (match_dup 1) (match_dup 2)))]
9862 "TARGET_POWERPC64 && TARGET_UPDATE
9863 && (!avoiding_indexed_address_p (Pmode)
9864 || !gpc_reg_operand (operands[2], Pmode)
9865 || (REG_P (operands[0])
9866 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9867 "@
9868 stdux %3,%0,%2
9869 stdu %3,%2(%0)"
9870 [(set_attr "type" "store_ux,store_u")])
9872 ;; This pattern is only conditional on TARGET_POWERPC64, as it is
9873 ;; needed for stack allocation, even if the user passes -mno-update.
9874 (define_insn "movdi_<mode>_update_stack"
9875 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0")
9876 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I")))
9877 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
9878 (set (match_operand:P 0 "gpc_reg_operand" "=b,b")
9879 (plus:P (match_dup 1) (match_dup 2)))]
9880 "TARGET_POWERPC64"
9881 "@
9882 stdux %3,%0,%2
9883 stdu %3,%2(%0)"
9884 [(set_attr "type" "store_ux,store_u")])
9886 (define_insn "*movsi_update1"
9887 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9888 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9889 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9890 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9891 (plus:SI (match_dup 1) (match_dup 2)))]
9892 "TARGET_UPDATE
9893 && (!avoiding_indexed_address_p (SImode)
9894 || !gpc_reg_operand (operands[2], SImode))"
9895 "@
9896 {lux|lwzux} %3,%0,%2
9897 {lu|lwzu} %3,%2(%0)"
9898 [(set_attr "type" "load_ux,load_u")])
9900 (define_insn "*movsi_update2"
9901 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
9902 (sign_extend:DI
9903 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
9904 (match_operand:DI 2 "gpc_reg_operand" "r")))))
9905 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
9906 (plus:DI (match_dup 1) (match_dup 2)))]
9907 "TARGET_POWERPC64 && rs6000_gen_cell_microcode
9908 && !avoiding_indexed_address_p (DImode)"
9909 "lwaux %3,%0,%2"
9910 [(set_attr "type" "load_ext_ux")])
9912 (define_insn "movsi_update"
9913 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9914 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9915 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9916 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9917 (plus:SI (match_dup 1) (match_dup 2)))]
9918 "TARGET_UPDATE
9919 && (!avoiding_indexed_address_p (SImode)
9920 || !gpc_reg_operand (operands[2], SImode)
9921 || (REG_P (operands[0])
9922 && REGNO (operands[0]) == STACK_POINTER_REGNUM))"
9923 "@
9924 {stux|stwux} %3,%0,%2
9925 {stu|stwu} %3,%2(%0)"
9926 [(set_attr "type" "store_ux,store_u")])
9928 ;; This is an unconditional pattern; needed for stack allocation, even
9929 ;; if the user passes -mno-update.
9930 (define_insn "movsi_update_stack"
9931 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9932 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9933 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
9934 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9935 (plus:SI (match_dup 1) (match_dup 2)))]
9936 ""
9937 "@
9938 {stux|stwux} %3,%0,%2
9939 {stu|stwu} %3,%2(%0)"
9940 [(set_attr "type" "store_ux,store_u")])
9942 (define_insn "*movhi_update1"
9943 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
9944 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9945 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
9946 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9947 (plus:SI (match_dup 1) (match_dup 2)))]
9948 "TARGET_UPDATE
9949 && (!avoiding_indexed_address_p (SImode)
9950 || !gpc_reg_operand (operands[2], SImode))"
9951 "@
9952 lhzux %3,%0,%2
9953 lhzu %3,%2(%0)"
9954 [(set_attr "type" "load_ux,load_u")])
9956 (define_insn "*movhi_update2"
9957 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9958 (zero_extend:SI
9959 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9960 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9961 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9962 (plus:SI (match_dup 1) (match_dup 2)))]
9963 "TARGET_UPDATE
9964 && (!avoiding_indexed_address_p (SImode)
9965 || !gpc_reg_operand (operands[2], SImode))"
9966 "@
9967 lhzux %3,%0,%2
9968 lhzu %3,%2(%0)"
9969 [(set_attr "type" "load_ux,load_u")])
9971 (define_insn "*movhi_update3"
9972 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
9973 (sign_extend:SI
9974 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9975 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
9976 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9977 (plus:SI (match_dup 1) (match_dup 2)))]
9978 "TARGET_UPDATE && rs6000_gen_cell_microcode
9979 && (!avoiding_indexed_address_p (SImode)
9980 || !gpc_reg_operand (operands[2], SImode))"
9981 "@
9982 lhaux %3,%0,%2
9983 lhau %3,%2(%0)"
9984 [(set_attr "type" "load_ext_ux,load_ext_u")])
9986 (define_insn "*movhi_update4"
9987 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
9988 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
9989 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
9990 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
9991 (plus:SI (match_dup 1) (match_dup 2)))]
9992 "TARGET_UPDATE
9993 && (!avoiding_indexed_address_p (SImode)
9994 || !gpc_reg_operand (operands[2], SImode))"
9995 "@
9996 sthux %3,%0,%2
9997 sthu %3,%2(%0)"
9998 [(set_attr "type" "store_ux,store_u")])
10000 (define_insn "*movqi_update1"
10001 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10002 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10003 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10004 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10005 (plus:SI (match_dup 1) (match_dup 2)))]
10006 "TARGET_UPDATE
10007 && (!avoiding_indexed_address_p (SImode)
10008 || !gpc_reg_operand (operands[2], SImode))"
10009 "@
10010 lbzux %3,%0,%2
10011 lbzu %3,%2(%0)"
10012 [(set_attr "type" "load_ux,load_u")])
10014 (define_insn "*movqi_update2"
10015 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10016 (zero_extend:SI
10017 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10018 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10019 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10020 (plus:SI (match_dup 1) (match_dup 2)))]
10021 "TARGET_UPDATE
10022 && (!avoiding_indexed_address_p (SImode)
10023 || !gpc_reg_operand (operands[2], SImode))"
10024 "@
10025 lbzux %3,%0,%2
10026 lbzu %3,%2(%0)"
10027 [(set_attr "type" "load_ux,load_u")])
10029 (define_insn "*movqi_update3"
10030 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10031 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10032 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10033 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10034 (plus:SI (match_dup 1) (match_dup 2)))]
10035 "TARGET_UPDATE
10036 && (!avoiding_indexed_address_p (SImode)
10037 || !gpc_reg_operand (operands[2], SImode))"
10038 "@
10039 stbux %3,%0,%2
10040 stbu %3,%2(%0)"
10041 [(set_attr "type" "store_ux,store_u")])
10043 (define_insn "*movsf_update1"
10044 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10045 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10046 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10047 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10048 (plus:SI (match_dup 1) (match_dup 2)))]
10049 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10050 && (!avoiding_indexed_address_p (SImode)
10051 || !gpc_reg_operand (operands[2], SImode))"
10052 "@
10053 lfsux %3,%0,%2
10054 lfsu %3,%2(%0)"
10055 [(set_attr "type" "fpload_ux,fpload_u")])
10057 (define_insn "*movsf_update2"
10058 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10059 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10060 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10061 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10062 (plus:SI (match_dup 1) (match_dup 2)))]
10063 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE
10064 && (!avoiding_indexed_address_p (SImode)
10065 || !gpc_reg_operand (operands[2], SImode))"
10066 "@
10067 stfsux %3,%0,%2
10068 stfsu %3,%2(%0)"
10069 [(set_attr "type" "fpstore_ux,fpstore_u")])
10071 (define_insn "*movsf_update3"
10072 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10073 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10074 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10075 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10076 (plus:SI (match_dup 1) (match_dup 2)))]
10077 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10078 && (!avoiding_indexed_address_p (SImode)
10079 || !gpc_reg_operand (operands[2], SImode))"
10080 "@
10081 {lux|lwzux} %3,%0,%2
10082 {lu|lwzu} %3,%2(%0)"
10083 [(set_attr "type" "load_ux,load_u")])
10085 (define_insn "*movsf_update4"
10086 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10087 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10088 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10089 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10090 (plus:SI (match_dup 1) (match_dup 2)))]
10091 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE
10092 && (!avoiding_indexed_address_p (SImode)
10093 || !gpc_reg_operand (operands[2], SImode))"
10094 "@
10095 {stux|stwux} %3,%0,%2
10096 {stu|stwu} %3,%2(%0)"
10097 [(set_attr "type" "store_ux,store_u")])
10099 (define_insn "*movdf_update1"
10100 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d")
10101 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10102 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10103 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10104 (plus:SI (match_dup 1) (match_dup 2)))]
10105 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10106 && (!avoiding_indexed_address_p (SImode)
10107 || !gpc_reg_operand (operands[2], SImode))"
10108 "@
10109 lfdux %3,%0,%2
10110 lfdu %3,%2(%0)"
10111 [(set_attr "type" "fpload_ux,fpload_u")])
10113 (define_insn "*movdf_update2"
10114 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10115 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10116 (match_operand:DF 3 "gpc_reg_operand" "d,d"))
10117 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10118 (plus:SI (match_dup 1) (match_dup 2)))]
10119 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE
10120 && (!avoiding_indexed_address_p (SImode)
10121 || !gpc_reg_operand (operands[2], SImode))"
10122 "@
10123 stfdux %3,%0,%2
10124 stfdu %3,%2(%0)"
10125 [(set_attr "type" "fpstore_ux,fpstore_u")])
10128 ;; After inserting conditional returns we can sometimes have
10129 ;; unnecessary register moves. Unfortunately we cannot have a
10130 ;; modeless peephole here, because some single SImode sets have early
10131 ;; clobber outputs. Although those sets expand to multi-ppc-insn
10132 ;; sequences, using get_attr_length here will smash the operands
10133 ;; array. Neither is there an early_cobbler_p predicate.
10134 ;; Disallow subregs for E500 so we don't munge frob_di_df_2.
10135 (define_peephole2
10136 [(set (match_operand:DF 0 "gpc_reg_operand" "")
10137 (match_operand:DF 1 "any_operand" ""))
10138 (set (match_operand:DF 2 "gpc_reg_operand" "")
10139 (match_dup 0))]
10140 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG)
10141 && peep2_reg_dead_p (2, operands[0])"
10142 [(set (match_dup 2) (match_dup 1))])
10144 (define_peephole2
10145 [(set (match_operand:SF 0 "gpc_reg_operand" "")
10146 (match_operand:SF 1 "any_operand" ""))
10147 (set (match_operand:SF 2 "gpc_reg_operand" "")
10148 (match_dup 0))]
10149 "peep2_reg_dead_p (2, operands[0])"
10150 [(set (match_dup 2) (match_dup 1))])
10152 \f
10153 ;; TLS support.
10155 ;; Mode attributes for different ABIs.
10156 (define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")])
10157 (define_mode_attr tls_abi_suffix [(SI "32") (DI "64")])
10158 (define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")])
10159 (define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")])
10161 (define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>"
10162 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10163 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10164 (match_operand 4 "" "g")))
10165 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10166 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10167 UNSPEC_TLSGD)
10168 (clobber (reg:SI LR_REGNO))]
10169 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10170 {
10171 if (TARGET_CMODEL != CMODEL_SMALL)
10172 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;bl %z3\;%.";
10173 else
10174 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;%.";
10175 }
10176 "&& TARGET_TLS_MARKERS"
10177 [(set (match_dup 0)
10178 (unspec:TLSmode [(match_dup 1)
10179 (match_dup 2)]
10180 UNSPEC_TLSGD))
10181 (parallel [(set (match_dup 0)
10182 (call (mem:TLSmode (match_dup 3))
10183 (match_dup 4)))
10184 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10185 (clobber (reg:SI LR_REGNO))])]
10186 ""
10187 [(set_attr "type" "two")
10188 (set (attr "length")
10189 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10190 (const_int 16)
10191 (const_int 12)))])
10193 (define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>"
10194 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10195 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s"))
10196 (match_operand 4 "" "g")))
10197 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10198 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10199 UNSPEC_TLSGD)
10200 (clobber (reg:SI LR_REGNO))]
10201 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10202 {
10203 if (flag_pic)
10204 {
10205 if (TARGET_SECURE_PLT && flag_pic == 2)
10206 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt";
10207 else
10208 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt";
10209 }
10210 else
10211 return "addi %0,%1,%2@got@tlsgd\;bl %z3";
10212 }
10213 "&& TARGET_TLS_MARKERS"
10214 [(set (match_dup 0)
10215 (unspec:TLSmode [(match_dup 1)
10216 (match_dup 2)]
10217 UNSPEC_TLSGD))
10218 (parallel [(set (match_dup 0)
10219 (call (mem:TLSmode (match_dup 3))
10220 (match_dup 4)))
10221 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)
10222 (clobber (reg:SI LR_REGNO))])]
10223 ""
10224 [(set_attr "type" "two")
10225 (set_attr "length" "8")])
10227 (define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>"
10228 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10229 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10230 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10231 UNSPEC_TLSGD))]
10232 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10233 "addi %0,%1,%2@got@tlsgd"
10234 "&& TARGET_CMODEL != CMODEL_SMALL"
10235 [(set (match_dup 3)
10236 (high:TLSmode
10237 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))
10238 (set (match_dup 0)
10239 (lo_sum:TLSmode (match_dup 3)
10240 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD)))]
10241 "
10242 {
10243 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10244 }"
10245 [(set (attr "length")
10246 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10247 (const_int 8)
10248 (const_int 4)))])
10250 (define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>"
10251 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10252 (high:TLSmode
10253 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10254 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10255 UNSPEC_TLSGD)))]
10256 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10257 "addis %0,%1,%2@got@tlsgd@ha"
10258 [(set_attr "length" "4")])
10260 (define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>"
10261 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10262 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10263 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10264 UNSPEC_TLSGD)))]
10265 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10266 "addi %0,%1,%2@got@tlsgd@l"
10267 [(set_attr "length" "4")])
10269 (define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>"
10270 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10271 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10272 (match_operand 2 "" "g")))
10273 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
10274 UNSPEC_TLSGD)
10275 (clobber (reg:SI LR_REGNO))]
10276 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
10277 "bl %z1(%3@tlsgd)\;%."
10278 [(set_attr "type" "branch")
10279 (set_attr "length" "8")])
10281 (define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>"
10282 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10283 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10284 (match_operand 2 "" "g")))
10285 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")]
10286 UNSPEC_TLSGD)
10287 (clobber (reg:SI LR_REGNO))]
10288 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10289 {
10290 if (flag_pic)
10291 {
10292 if (TARGET_SECURE_PLT && flag_pic == 2)
10293 return "bl %z1+32768(%3@tlsgd)@plt";
10294 return "bl %z1(%3@tlsgd)@plt";
10295 }
10296 return "bl %z1(%3@tlsgd)";
10297 }
10298 [(set_attr "type" "branch")
10299 (set_attr "length" "4")])
10301 (define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>"
10302 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10303 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10304 (match_operand 3 "" "g")))
10305 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10306 UNSPEC_TLSLD)
10307 (clobber (reg:SI LR_REGNO))]
10308 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX"
10309 {
10310 if (TARGET_CMODEL != CMODEL_SMALL)
10311 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;bl %z2\;%.";
10312 else
10313 return "addi %0,%1,%&@got@tlsld\;bl %z2\;%.";
10314 }
10315 "&& TARGET_TLS_MARKERS"
10316 [(set (match_dup 0)
10317 (unspec:TLSmode [(match_dup 1)]
10318 UNSPEC_TLSLD))
10319 (parallel [(set (match_dup 0)
10320 (call (mem:TLSmode (match_dup 2))
10321 (match_dup 3)))
10322 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10323 (clobber (reg:SI LR_REGNO))])]
10324 ""
10325 [(set_attr "type" "two")
10326 (set (attr "length")
10327 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10328 (const_int 16)
10329 (const_int 12)))])
10331 (define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>"
10332 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10333 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s"))
10334 (match_operand 3 "" "g")))
10335 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10336 UNSPEC_TLSLD)
10337 (clobber (reg:SI LR_REGNO))]
10338 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4"
10339 {
10340 if (flag_pic)
10341 {
10342 if (TARGET_SECURE_PLT && flag_pic == 2)
10343 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt";
10344 else
10345 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt";
10346 }
10347 else
10348 return "addi %0,%1,%&@got@tlsld\;bl %z2";
10349 }
10350 "&& TARGET_TLS_MARKERS"
10351 [(set (match_dup 0)
10352 (unspec:TLSmode [(match_dup 1)]
10353 UNSPEC_TLSLD))
10354 (parallel [(set (match_dup 0)
10355 (call (mem:TLSmode (match_dup 2))
10356 (match_dup 3)))
10357 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10358 (clobber (reg:SI LR_REGNO))])]
10359 ""
10360 [(set_attr "length" "8")])
10362 (define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>"
10363 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10364 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10365 UNSPEC_TLSLD))]
10366 "HAVE_AS_TLS && TARGET_TLS_MARKERS"
10367 "addi %0,%1,%&@got@tlsld"
10368 "&& TARGET_CMODEL != CMODEL_SMALL"
10369 [(set (match_dup 2)
10370 (high:TLSmode
10371 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))
10372 (set (match_dup 0)
10373 (lo_sum:TLSmode (match_dup 2)
10374 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
10375 "
10376 {
10377 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10378 }"
10379 [(set (attr "length")
10380 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10381 (const_int 8)
10382 (const_int 4)))])
10384 (define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>"
10385 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10386 (high:TLSmode
10387 (unspec:TLSmode [(const_int 0)
10388 (match_operand:TLSmode 1 "gpc_reg_operand" "b")]
10389 UNSPEC_TLSLD)))]
10390 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10391 "addis %0,%1,%&@got@tlsld@ha"
10392 [(set_attr "length" "4")])
10394 (define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>"
10395 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10396 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10397 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)))]
10398 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL"
10399 "addi %0,%1,%&@got@tlsld@l"
10400 [(set_attr "length" "4")])
10402 (define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>"
10403 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10404 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10405 (match_operand 2 "" "g")))
10406 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10407 (clobber (reg:SI LR_REGNO))]
10408 "HAVE_AS_TLS && DEFAULT_ABI == ABI_AIX && TARGET_TLS_MARKERS"
10409 "bl %z1(%&@tlsld)\;%."
10410 [(set_attr "type" "branch")
10411 (set_attr "length" "8")])
10413 (define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>"
10414 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10415 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s"))
10416 (match_operand 2 "" "g")))
10417 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD)
10418 (clobber (reg:SI LR_REGNO))]
10419 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS"
10420 {
10421 if (flag_pic)
10422 {
10423 if (TARGET_SECURE_PLT && flag_pic == 2)
10424 return "bl %z1+32768(%&@tlsld)@plt";
10425 return "bl %z1(%&@tlsld)@plt";
10426 }
10427 return "bl %z1(%&@tlsld)";
10428 }
10429 [(set_attr "type" "branch")
10430 (set_attr "length" "4")])
10432 (define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>"
10433 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10434 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10435 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10436 UNSPEC_TLSDTPREL))]
10437 "HAVE_AS_TLS"
10438 "addi %0,%1,%2@dtprel")
10440 (define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>"
10441 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10442 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10443 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10444 UNSPEC_TLSDTPRELHA))]
10445 "HAVE_AS_TLS"
10446 "addis %0,%1,%2@dtprel@ha")
10448 (define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>"
10449 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10450 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10451 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10452 UNSPEC_TLSDTPRELLO))]
10453 "HAVE_AS_TLS"
10454 "addi %0,%1,%2@dtprel@l")
10456 (define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>"
10457 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10458 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10459 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10460 UNSPEC_TLSGOTDTPREL))]
10461 "HAVE_AS_TLS"
10462 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)"
10463 "&& TARGET_CMODEL != CMODEL_SMALL"
10464 [(set (match_dup 3)
10465 (high:TLSmode
10466 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))
10467 (set (match_dup 0)
10468 (lo_sum:TLSmode (match_dup 3)
10469 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTDTPREL)))]
10470 "
10471 {
10472 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10473 }"
10474 [(set (attr "length")
10475 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10476 (const_int 8)
10477 (const_int 4)))])
10479 (define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>"
10480 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10481 (high:TLSmode
10482 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10483 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10484 UNSPEC_TLSGOTDTPREL)))]
10485 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10486 "addis %0,%1,%2@got@dtprel@ha"
10487 [(set_attr "length" "4")])
10489 (define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>"
10490 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10491 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10492 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10493 UNSPEC_TLSGOTDTPREL)))]
10494 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10495 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)"
10496 [(set_attr "length" "4")])
10498 (define_insn "tls_tprel_<TLSmode:tls_abi_suffix>"
10499 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10500 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10501 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10502 UNSPEC_TLSTPREL))]
10503 "HAVE_AS_TLS"
10504 "addi %0,%1,%2@tprel")
10506 (define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>"
10507 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10508 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10509 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10510 UNSPEC_TLSTPRELHA))]
10511 "HAVE_AS_TLS"
10512 "addis %0,%1,%2@tprel@ha")
10514 (define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>"
10515 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10516 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10517 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10518 UNSPEC_TLSTPRELLO))]
10519 "HAVE_AS_TLS"
10520 "addi %0,%1,%2@tprel@l")
10522 ;; "b" output constraint here and on tls_tls input to support linker tls
10523 ;; optimization. The linker may edit the instructions emitted by a
10524 ;; tls_got_tprel/tls_tls pair to addis,addi.
10525 (define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>"
10526 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10527 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10528 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10529 UNSPEC_TLSGOTTPREL))]
10530 "HAVE_AS_TLS"
10531 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)"
10532 "&& TARGET_CMODEL != CMODEL_SMALL"
10533 [(set (match_dup 3)
10534 (high:TLSmode
10535 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))
10536 (set (match_dup 0)
10537 (lo_sum:TLSmode (match_dup 3)
10538 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGOTTPREL)))]
10539 "
10540 {
10541 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode);
10542 }"
10543 [(set (attr "length")
10544 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL"))
10545 (const_int 8)
10546 (const_int 4)))])
10548 (define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>"
10549 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b")
10550 (high:TLSmode
10551 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10552 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10553 UNSPEC_TLSGOTTPREL)))]
10554 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10555 "addis %0,%1,%2@got@tprel@ha"
10556 [(set_attr "length" "4")])
10558 (define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>"
10559 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10560 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b")
10561 (unspec:TLSmode [(match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10562 UNSPEC_TLSGOTTPREL)))]
10563 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL"
10564 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)"
10565 [(set_attr "length" "4")])
10567 (define_insn "tls_tls_<TLSmode:tls_abi_suffix>"
10568 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r")
10569 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")
10570 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")]
10571 UNSPEC_TLSTLS))]
10572 "HAVE_AS_TLS"
10573 "add %0,%1,%2@tls")
10574 \f
10575 ;; Next come insns related to the calling sequence.
10576 ;;
10577 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10578 ;; We move the back-chain and decrement the stack pointer.
10580 (define_expand "allocate_stack"
10581 [(set (match_operand 0 "gpc_reg_operand" "")
10582 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10583 (set (reg 1)
10584 (minus (reg 1) (match_dup 1)))]
10585 ""
10586 "
10587 { rtx chain = gen_reg_rtx (Pmode);
10588 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10589 rtx neg_op0;
10590 rtx insn, par, set, mem;
10592 emit_move_insn (chain, stack_bot);
10594 /* Check stack bounds if necessary. */
10595 if (crtl->limit_stack)
10596 {
10597 rtx available;
10598 available = expand_binop (Pmode, sub_optab,
10599 stack_pointer_rtx, stack_limit_rtx,
10600 NULL_RTX, 1, OPTAB_WIDEN);
10601 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10602 }
10604 if (GET_CODE (operands[1]) != CONST_INT
10605 || INTVAL (operands[1]) < -32767
10606 || INTVAL (operands[1]) > 32768)
10607 {
10608 neg_op0 = gen_reg_rtx (Pmode);
10609 if (TARGET_32BIT)
10610 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10611 else
10612 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10613 }
10614 else
10615 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10617 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack
10618 : gen_movdi_di_update_stack))
10619 (stack_pointer_rtx, stack_pointer_rtx, neg_op0,
10620 chain));
10621 /* Since we didn't use gen_frame_mem to generate the MEM, grab
10622 it now and set the alias set/attributes. The above gen_*_update
10623 calls will generate a PARALLEL with the MEM set being the first
10624 operation. */
10625 par = PATTERN (insn);
10626 gcc_assert (GET_CODE (par) == PARALLEL);
10627 set = XVECEXP (par, 0, 0);
10628 gcc_assert (GET_CODE (set) == SET);
10629 mem = SET_DEST (set);
10630 gcc_assert (MEM_P (mem));
10631 MEM_NOTRAP_P (mem) = 1;
10632 set_mem_alias_set (mem, get_frame_alias_set ());
10634 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10635 DONE;
10636 }")
10638 ;; These patterns say how to save and restore the stack pointer. We need not
10639 ;; save the stack pointer at function level since we are careful to
10640 ;; preserve the backchain. At block level, we have to restore the backchain
10641 ;; when we restore the stack pointer.
10642 ;;
10643 ;; For nonlocal gotos, we must save both the stack pointer and its
10644 ;; backchain and restore both. Note that in the nonlocal case, the
10645 ;; save area is a memory location.
10647 (define_expand "save_stack_function"
10648 [(match_operand 0 "any_operand" "")
10649 (match_operand 1 "any_operand" "")]
10650 ""
10651 "DONE;")
10653 (define_expand "restore_stack_function"
10654 [(match_operand 0 "any_operand" "")
10655 (match_operand 1 "any_operand" "")]
10656 ""
10657 "DONE;")
10659 ;; Adjust stack pointer (op0) to a new value (op1).
10660 ;; First copy old stack backchain to new location, and ensure that the
10661 ;; scheduler won't reorder the sp assignment before the backchain write.
10662 (define_expand "restore_stack_block"
10663 [(set (match_dup 2) (match_dup 3))
10664 (set (match_dup 4) (match_dup 2))
10665 (match_dup 5)
10666 (set (match_operand 0 "register_operand" "")
10667 (match_operand 1 "register_operand" ""))]
10668 ""
10669 "
10670 {
10671 rtvec p;
10673 operands[1] = force_reg (Pmode, operands[1]);
10674 operands[2] = gen_reg_rtx (Pmode);
10675 operands[3] = gen_frame_mem (Pmode, operands[0]);
10676 operands[4] = gen_frame_mem (Pmode, operands[1]);
10677 p = rtvec_alloc (1);
10678 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10679 gen_frame_mem (BLKmode, operands[0]),
10680 const0_rtx);
10681 operands[5] = gen_rtx_PARALLEL (VOIDmode, p);
10682 }")
10684 (define_expand "save_stack_nonlocal"
10685 [(set (match_dup 3) (match_dup 4))
10686 (set (match_operand 0 "memory_operand" "") (match_dup 3))
10687 (set (match_dup 2) (match_operand 1 "register_operand" ""))]
10688 ""
10689 "
10690 {
10691 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10693 /* Copy the backchain to the first word, sp to the second. */
10694 operands[0] = adjust_address_nv (operands[0], Pmode, 0);
10695 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word);
10696 operands[3] = gen_reg_rtx (Pmode);
10697 operands[4] = gen_frame_mem (Pmode, operands[1]);
10698 }")
10700 (define_expand "restore_stack_nonlocal"
10701 [(set (match_dup 2) (match_operand 1 "memory_operand" ""))
10702 (set (match_dup 3) (match_dup 4))
10703 (set (match_dup 5) (match_dup 2))
10704 (match_dup 6)
10705 (set (match_operand 0 "register_operand" "") (match_dup 3))]
10706 ""
10707 "
10708 {
10709 int units_per_word = (TARGET_32BIT) ? 4 : 8;
10710 rtvec p;
10712 /* Restore the backchain from the first word, sp from the second. */
10713 operands[2] = gen_reg_rtx (Pmode);
10714 operands[3] = gen_reg_rtx (Pmode);
10715 operands[1] = adjust_address_nv (operands[1], Pmode, 0);
10716 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word);
10717 operands[5] = gen_frame_mem (Pmode, operands[3]);
10718 p = rtvec_alloc (1);
10719 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode,
10720 gen_frame_mem (BLKmode, operands[0]),
10721 const0_rtx);
10722 operands[6] = gen_rtx_PARALLEL (VOIDmode, p);
10723 }")
10724 \f
10725 ;; TOC register handling.
10727 ;; Code to initialize the TOC register...
10729 (define_insn "load_toc_aix_si"
10730 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10731 (unspec:SI [(const_int 0)] UNSPEC_TOC))
10732 (use (reg:SI 2))])]
10733 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10734 "*
10735 {
10736 char buf[30];
10737 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10738 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10739 operands[2] = gen_rtx_REG (Pmode, 2);
10740 return \"{l|lwz} %0,%1(%2)\";
10741 }"
10742 [(set_attr "type" "load")])
10744 (define_insn "load_toc_aix_di"
10745 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10746 (unspec:DI [(const_int 0)] UNSPEC_TOC))
10747 (use (reg:DI 2))])]
10748 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10749 "*
10750 {
10751 char buf[30];
10752 #ifdef TARGET_RELOCATABLE
10753 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10754 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10755 #else
10756 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10757 #endif
10758 if (TARGET_ELF)
10759 strcat (buf, \"@toc\");
10760 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10761 operands[2] = gen_rtx_REG (Pmode, 2);
10762 return \"ld %0,%1(%2)\";
10763 }"
10764 [(set_attr "type" "load")])
10766 (define_insn "load_toc_v4_pic_si"
10767 [(set (reg:SI LR_REGNO)
10768 (unspec:SI [(const_int 0)] UNSPEC_TOC))]
10769 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10770 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10771 [(set_attr "type" "branch")
10772 (set_attr "length" "4")])
10774 (define_expand "load_toc_v4_PIC_1"
10775 [(parallel [(set (reg:SI LR_REGNO)
10776 (match_operand:SI 0 "immediate_operand" "s"))
10777 (use (unspec [(match_dup 0)] UNSPEC_TOC))])]
10778 "TARGET_ELF && DEFAULT_ABI != ABI_AIX
10779 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10780 "")
10782 (define_insn "load_toc_v4_PIC_1_normal"
10783 [(set (reg:SI LR_REGNO)
10784 (match_operand:SI 0 "immediate_operand" "s"))
10785 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10786 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX
10787 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10788 "bcl 20,31,%0\\n%0:"
10789 [(set_attr "type" "branch")
10790 (set_attr "length" "4")])
10792 (define_insn "load_toc_v4_PIC_1_476"
10793 [(set (reg:SI LR_REGNO)
10794 (match_operand:SI 0 "immediate_operand" "s"))
10795 (use (unspec [(match_dup 0)] UNSPEC_TOC))]
10796 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX
10797 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))"
10798 "*
10799 {
10800 char name[32];
10801 static char templ[32];
10803 get_ppc476_thunk_name (name);
10804 sprintf (templ, \"bl %s\\n%%0:\", name);
10805 return templ;
10806 }"
10807 [(set_attr "type" "branch")
10808 (set_attr "length" "4")])
10810 (define_expand "load_toc_v4_PIC_1b"
10811 [(parallel [(set (reg:SI LR_REGNO)
10812 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10813 (label_ref (match_operand 1 "" ""))]
10814 UNSPEC_TOCPTR))
10815 (match_dup 1)])]
10816 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10817 "")
10819 (define_insn "load_toc_v4_PIC_1b_normal"
10820 [(set (reg:SI LR_REGNO)
10821 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10822 (label_ref (match_operand 1 "" ""))]
10823 UNSPEC_TOCPTR))
10824 (match_dup 1)]
10825 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10826 "bcl 20,31,$+8\;.long %0-$"
10827 [(set_attr "type" "branch")
10828 (set_attr "length" "8")])
10830 (define_insn "load_toc_v4_PIC_1b_476"
10831 [(set (reg:SI LR_REGNO)
10832 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s")
10833 (label_ref (match_operand 1 "" ""))]
10834 UNSPEC_TOCPTR))
10835 (match_dup 1)]
10836 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10837 "*
10838 {
10839 char name[32];
10840 static char templ[32];
10842 get_ppc476_thunk_name (name);
10843 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name);
10844 return templ;
10845 }"
10846 [(set_attr "type" "branch")
10847 (set_attr "length" "16")])
10849 (define_insn "load_toc_v4_PIC_2"
10850 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10851 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10852 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10853 (match_operand:SI 3 "immediate_operand" "s")))))]
10854 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10855 "{l|lwz} %0,%2-%3(%1)"
10856 [(set_attr "type" "load")])
10858 (define_insn "load_toc_v4_PIC_3b"
10859 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10860 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10861 (high:SI
10862 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10863 (match_operand:SI 3 "symbol_ref_operand" "s")))))]
10864 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10865 "{cau|addis} %0,%1,%2-%3@ha")
10867 (define_insn "load_toc_v4_PIC_3c"
10868 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10869 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10870 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s")
10871 (match_operand:SI 3 "symbol_ref_operand" "s"))))]
10872 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic"
10873 "{cal %0,%2-%3@l(%1)|addi %0,%1,%2-%3@l}")
10875 ;; If the TOC is shared over a translation unit, as happens with all
10876 ;; the kinds of PIC that we support, we need to restore the TOC
10877 ;; pointer only when jumping over units of translation.
10878 ;; On Darwin, we need to reload the picbase.
10880 (define_expand "builtin_setjmp_receiver"
10881 [(use (label_ref (match_operand 0 "" "")))]
10882 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10883 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10884 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10885 "
10886 {
10887 #if TARGET_MACHO
10888 if (DEFAULT_ABI == ABI_DARWIN)
10889 {
10890 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME);
10891 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10892 rtx tmplabrtx;
10893 char tmplab[20];
10895 crtl->uses_pic_offset_table = 1;
10896 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10897 CODE_LABEL_NUMBER (operands[0]));
10898 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab));
10900 emit_insn (gen_load_macho_picbase (tmplabrtx));
10901 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO));
10902 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10903 }
10904 else
10905 #endif
10906 rs6000_emit_load_toc_table (FALSE);
10907 DONE;
10908 }")
10910 ;; Largetoc support
10911 (define_insn "*largetoc_high"
10912 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10913 (high:DI
10914 (unspec [(match_operand:DI 1 "" "")
10915 (match_operand:DI 2 "gpc_reg_operand" "b")]
10916 UNSPEC_TOCREL)))]
10917 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10918 "{cau|addis} %0,%2,%1@toc@ha")
10920 (define_insn "*largetoc_high_plus"
10921 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r")
10922 (high:DI
10923 (plus:DI
10924 (unspec [(match_operand:DI 1 "" "")
10925 (match_operand:DI 2 "gpc_reg_operand" "b")]
10926 UNSPEC_TOCREL)
10927 (match_operand 3 "const_int_operand" "n"))))]
10928 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10929 "{cau|addis} %0,%2,%1+%3@toc@ha")
10931 (define_insn "*largetoc_low"
10932 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
10933 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r")
10934 (match_operand:DI 2 "" "")))]
10935 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL"
10936 "@
10937 {cal %0,%2@l(%1)|addi %0,%1,%2@l}
10938 {ai|addic} %0,%1,%2@l")
10940 (define_insn_and_split "*tocref<mode>"
10941 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r")
10942 (match_operand:P 1 "small_toc_ref" "R"))]
10943 "TARGET_TOC"
10944 "{cal|la} %0,%a1"
10945 "&& TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL && reload_completed"
10946 [(set (match_dup 0) (high:P (match_dup 1)))
10947 (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))])
10949 ;; Elf specific ways of loading addresses for non-PIC code.
10950 ;; The output of this could be r0, but we make a very strong
10951 ;; preference for a base register because it will usually
10952 ;; be needed there.
10953 (define_insn "elf_high"
10954 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
10955 (high:SI (match_operand 1 "" "")))]
10956 "TARGET_ELF && ! TARGET_64BIT"
10957 "{liu|lis} %0,%1@ha")
10959 (define_insn "elf_low"
10960 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
10961 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
10962 (match_operand 2 "" "")))]
10963 "TARGET_ELF && ! TARGET_64BIT"
10964 "@
10965 {cal|la} %0,%2@l(%1)
10966 {ai|addic} %0,%1,%K2")
10967 \f
10968 ;; Call and call_value insns
10969 (define_expand "call"
10970 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10971 (match_operand 1 "" ""))
10972 (use (match_operand 2 "" ""))
10973 (clobber (reg:SI LR_REGNO))])]
10974 ""
10975 "
10976 {
10977 #if TARGET_MACHO
10978 if (MACHOPIC_INDIRECT)
10979 operands[0] = machopic_indirect_call_target (operands[0]);
10980 #endif
10982 gcc_assert (GET_CODE (operands[0]) == MEM);
10983 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
10985 operands[0] = XEXP (operands[0], 0);
10987 if (GET_CODE (operands[0]) != SYMBOL_REF
10988 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[0]))
10989 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0))
10990 {
10991 if (INTVAL (operands[2]) & CALL_LONG)
10992 operands[0] = rs6000_longcall_ref (operands[0]);
10994 switch (DEFAULT_ABI)
10995 {
10996 case ABI_V4:
10997 case ABI_DARWIN:
10998 operands[0] = force_reg (Pmode, operands[0]);
10999 break;
11001 case ABI_AIX:
11002 /* AIX function pointers are really pointers to a three word
11003 area. */
11004 rs6000_call_indirect_aix (NULL_RTX, operands[0], operands[1]);
11005 DONE;
11007 default:
11008 gcc_unreachable ();
11009 }
11010 }
11011 }")
11013 (define_expand "call_value"
11014 [(parallel [(set (match_operand 0 "" "")
11015 (call (mem:SI (match_operand 1 "address_operand" ""))
11016 (match_operand 2 "" "")))
11017 (use (match_operand 3 "" ""))
11018 (clobber (reg:SI LR_REGNO))])]
11019 ""
11020 "
11021 {
11022 #if TARGET_MACHO
11023 if (MACHOPIC_INDIRECT)
11024 operands[1] = machopic_indirect_call_target (operands[1]);
11025 #endif
11027 gcc_assert (GET_CODE (operands[1]) == MEM);
11028 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11030 operands[1] = XEXP (operands[1], 0);
11032 if (GET_CODE (operands[1]) != SYMBOL_REF
11033 || (DEFAULT_ABI == ABI_AIX && !SYMBOL_REF_FUNCTION_P (operands[1]))
11034 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0))
11035 {
11036 if (INTVAL (operands[3]) & CALL_LONG)
11037 operands[1] = rs6000_longcall_ref (operands[1]);
11039 switch (DEFAULT_ABI)
11040 {
11041 case ABI_V4:
11042 case ABI_DARWIN:
11043 operands[1] = force_reg (Pmode, operands[1]);
11044 break;
11046 case ABI_AIX:
11047 /* AIX function pointers are really pointers to a three word
11048 area. */
11049 rs6000_call_indirect_aix (operands[0], operands[1], operands[2]);
11050 DONE;
11052 default:
11053 gcc_unreachable ();
11054 }
11055 }
11056 }")
11058 ;; Call to function in current module. No TOC pointer reload needed.
11059 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11060 ;; either the function was not prototyped, or it was prototyped as a
11061 ;; variable argument function. It is > 0 if FP registers were passed
11062 ;; and < 0 if they were not.
11064 (define_insn "*call_local32"
11065 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11066 (match_operand 1 "" "g,g"))
11067 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11068 (clobber (reg:SI LR_REGNO))]
11069 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11070 "*
11071 {
11072 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11073 output_asm_insn (\"crxor 6,6,6\", operands);
11075 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11076 output_asm_insn (\"creqv 6,6,6\", operands);
11078 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11079 }"
11080 [(set_attr "type" "branch")
11081 (set_attr "length" "4,8")])
11083 (define_insn "*call_local64"
11084 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11085 (match_operand 1 "" "g,g"))
11086 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11087 (clobber (reg:SI LR_REGNO))]
11088 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11089 "*
11090 {
11091 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11092 output_asm_insn (\"crxor 6,6,6\", operands);
11094 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11095 output_asm_insn (\"creqv 6,6,6\", operands);
11097 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
11098 }"
11099 [(set_attr "type" "branch")
11100 (set_attr "length" "4,8")])
11102 (define_insn "*call_value_local32"
11103 [(set (match_operand 0 "" "")
11104 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11105 (match_operand 2 "" "g,g")))
11106 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11107 (clobber (reg:SI LR_REGNO))]
11108 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11109 "*
11110 {
11111 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11112 output_asm_insn (\"crxor 6,6,6\", operands);
11114 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11115 output_asm_insn (\"creqv 6,6,6\", operands);
11117 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11118 }"
11119 [(set_attr "type" "branch")
11120 (set_attr "length" "4,8")])
11123 (define_insn "*call_value_local64"
11124 [(set (match_operand 0 "" "")
11125 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11126 (match_operand 2 "" "g,g")))
11127 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11128 (clobber (reg:SI LR_REGNO))]
11129 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11130 "*
11131 {
11132 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11133 output_asm_insn (\"crxor 6,6,6\", operands);
11135 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11136 output_asm_insn (\"creqv 6,6,6\", operands);
11138 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
11139 }"
11140 [(set_attr "type" "branch")
11141 (set_attr "length" "4,8")])
11143 ;; Call to indirect functions with the AIX abi using a 3 word descriptor.
11144 ;; Operand0 is the addresss of the function to call
11145 ;; Operand1 is the flag for System V.4 for unprototyped or FP registers
11146 ;; Operand2 is the location in the function descriptor to load r2 from
11147 ;; Operand3 is the stack location to hold the current TOC pointer
11149 (define_insn "call_indirect_aix<ptrsize>"
11150 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11151 (match_operand 1 "" "g,g"))
11152 (use (match_operand:P 2 "memory_operand" "m,m"))
11153 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "m,m"))
11154 (use (reg:P STATIC_CHAIN_REGNUM))
11155 (clobber (reg:P LR_REGNO))]
11156 "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
11157 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
11158 [(set_attr "type" "jmpreg")
11159 (set_attr "length" "12")])
11161 ;; Like call_indirect_aix<ptrsize>, but no use of the static chain
11162 ;; Operand0 is the addresss of the function to call
11163 ;; Operand1 is the flag for System V.4 for unprototyped or FP registers
11164 ;; Operand2 is the location in the function descriptor to load r2 from
11165 ;; Operand3 is the stack location to hold the current TOC pointer
11167 (define_insn "call_indirect_aix<ptrsize>_nor11"
11168 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l"))
11169 (match_operand 1 "" "g,g"))
11170 (use (match_operand:P 2 "memory_operand" "m,m"))
11171 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "m,m"))
11172 (clobber (reg:P LR_REGNO))]
11173 "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
11174 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3"
11175 [(set_attr "type" "jmpreg")
11176 (set_attr "length" "12")])
11178 ;; Operand0 is the return result of the function
11179 ;; Operand1 is the addresss of the function to call
11180 ;; Operand2 is the flag for System V.4 for unprototyped or FP registers
11181 ;; Operand3 is the location in the function descriptor to load r2 from
11182 ;; Operand4 is the stack location to hold the current TOC pointer
11184 (define_insn "call_value_indirect_aix<ptrsize>"
11185 [(set (match_operand 0 "" "")
11186 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11187 (match_operand 2 "" "g,g")))
11188 (use (match_operand:P 3 "memory_operand" "m,m"))
11189 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "m,m"))
11190 (use (reg:P STATIC_CHAIN_REGNUM))
11191 (clobber (reg:P LR_REGNO))]
11192 "DEFAULT_ABI == ABI_AIX && TARGET_POINTERS_TO_NESTED_FUNCTIONS"
11193 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
11194 [(set_attr "type" "jmpreg")
11195 (set_attr "length" "12")])
11197 ;; Like call_value_indirect_aix<ptrsize>, but no use of the static chain
11198 ;; Operand0 is the return result of the function
11199 ;; Operand1 is the addresss of the function to call
11200 ;; Operand2 is the flag for System V.4 for unprototyped or FP registers
11201 ;; Operand3 is the location in the function descriptor to load r2 from
11202 ;; Operand4 is the stack location to hold the current TOC pointer
11204 (define_insn "call_value_indirect_aix<ptrsize>_nor11"
11205 [(set (match_operand 0 "" "")
11206 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l"))
11207 (match_operand 2 "" "g,g")))
11208 (use (match_operand:P 3 "memory_operand" "m,m"))
11209 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "m,m"))
11210 (clobber (reg:P LR_REGNO))]
11211 "DEFAULT_ABI == ABI_AIX && !TARGET_POINTERS_TO_NESTED_FUNCTIONS"
11212 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4"
11213 [(set_attr "type" "jmpreg")
11214 (set_attr "length" "12")])
11216 ;; Call to function which may be in another module. Restore the TOC
11217 ;; pointer (r2) after the call unless this is System V.
11218 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
11219 ;; either the function was not prototyped, or it was prototyped as a
11220 ;; variable argument function. It is > 0 if FP registers were passed
11221 ;; and < 0 if they were not.
11223 (define_insn "*call_nonlocal_aix32"
11224 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11225 (match_operand 1 "" "g"))
11226 (use (match_operand:SI 2 "immediate_operand" "O"))
11227 (clobber (reg:SI LR_REGNO))]
11228 "TARGET_32BIT
11229 && DEFAULT_ABI == ABI_AIX
11230 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11231 "bl %z0\;%."
11232 [(set_attr "type" "branch")
11233 (set_attr "length" "8")])
11235 (define_insn "*call_nonlocal_aix64"
11236 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11237 (match_operand 1 "" "g"))
11238 (use (match_operand:SI 2 "immediate_operand" "O"))
11239 (clobber (reg:SI LR_REGNO))]
11240 "TARGET_64BIT
11241 && DEFAULT_ABI == ABI_AIX
11242 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11243 "bl %z0\;%."
11244 [(set_attr "type" "branch")
11245 (set_attr "length" "8")])
11247 (define_insn "*call_value_nonlocal_aix32"
11248 [(set (match_operand 0 "" "")
11249 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11250 (match_operand 2 "" "g")))
11251 (use (match_operand:SI 3 "immediate_operand" "O"))
11252 (clobber (reg:SI LR_REGNO))]
11253 "TARGET_32BIT
11254 && DEFAULT_ABI == ABI_AIX
11255 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11256 "bl %z1\;%."
11257 [(set_attr "type" "branch")
11258 (set_attr "length" "8")])
11260 (define_insn "*call_value_nonlocal_aix64"
11261 [(set (match_operand 0 "" "")
11262 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11263 (match_operand 2 "" "g")))
11264 (use (match_operand:SI 3 "immediate_operand" "O"))
11265 (clobber (reg:SI LR_REGNO))]
11266 "TARGET_64BIT
11267 && DEFAULT_ABI == ABI_AIX
11268 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11269 "bl %z1\;%."
11270 [(set_attr "type" "branch")
11271 (set_attr "length" "8")])
11273 ;; A function pointer under System V is just a normal pointer
11274 ;; operands[0] is the function pointer
11275 ;; operands[1] is the stack size to clean up
11276 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
11277 ;; which indicates how to set cr1
11279 (define_insn "*call_indirect_nonlocal_sysv<mode>"
11280 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l"))
11281 (match_operand 1 "" "g,g,g,g"))
11282 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n"))
11283 (clobber (reg:SI LR_REGNO))]
11284 "DEFAULT_ABI == ABI_V4
11285 || DEFAULT_ABI == ABI_DARWIN"
11286 {
11287 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11288 output_asm_insn ("crxor 6,6,6", operands);
11290 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11291 output_asm_insn ("creqv 6,6,6", operands);
11293 return "b%T0l";
11294 }
11295 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11296 (set_attr "length" "4,4,8,8")])
11298 (define_insn_and_split "*call_nonlocal_sysv<mode>"
11299 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11300 (match_operand 1 "" "g,g"))
11301 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11302 (clobber (reg:SI LR_REGNO))]
11303 "(DEFAULT_ABI == ABI_DARWIN
11304 || (DEFAULT_ABI == ABI_V4
11305 && (INTVAL (operands[2]) & CALL_LONG) == 0))"
11306 {
11307 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11308 output_asm_insn ("crxor 6,6,6", operands);
11310 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11311 output_asm_insn ("creqv 6,6,6", operands);
11313 #if TARGET_MACHO
11314 return output_call(insn, operands, 0, 2);
11315 #else
11316 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11317 {
11318 gcc_assert (!TARGET_SECURE_PLT);
11319 return "bl %z0@plt";
11320 }
11321 else
11322 return "bl %z0";
11323 #endif
11324 }
11325 "DEFAULT_ABI == ABI_V4
11326 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11327 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11328 [(parallel [(call (mem:SI (match_dup 0))
11329 (match_dup 1))
11330 (use (match_dup 2))
11331 (use (match_dup 3))
11332 (clobber (reg:SI LR_REGNO))])]
11333 {
11334 operands[3] = pic_offset_table_rtx;
11335 }
11336 [(set_attr "type" "branch,branch")
11337 (set_attr "length" "4,8")])
11339 (define_insn "*call_nonlocal_sysv_secure<mode>"
11340 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s"))
11341 (match_operand 1 "" "g,g"))
11342 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11343 (use (match_operand:SI 3 "register_operand" "r,r"))
11344 (clobber (reg:SI LR_REGNO))]
11345 "(DEFAULT_ABI == ABI_V4
11346 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0])
11347 && (INTVAL (operands[2]) & CALL_LONG) == 0)"
11348 {
11349 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11350 output_asm_insn ("crxor 6,6,6", operands);
11352 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11353 output_asm_insn ("creqv 6,6,6", operands);
11355 if (flag_pic == 2)
11356 /* The magic 32768 offset here and in the other sysv call insns
11357 corresponds to the offset of r30 in .got2, as given by LCTOC1.
11358 See sysv4.h:toc_section. */
11359 return "bl %z0+32768@plt";
11360 else
11361 return "bl %z0@plt";
11362 }
11363 [(set_attr "type" "branch,branch")
11364 (set_attr "length" "4,8")])
11366 (define_insn "*call_value_indirect_nonlocal_sysv<mode>"
11367 [(set (match_operand 0 "" "")
11368 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l"))
11369 (match_operand 2 "" "g,g,g,g")))
11370 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n"))
11371 (clobber (reg:SI LR_REGNO))]
11372 "DEFAULT_ABI == ABI_V4
11373 || DEFAULT_ABI == ABI_DARWIN"
11374 {
11375 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11376 output_asm_insn ("crxor 6,6,6", operands);
11378 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11379 output_asm_insn ("creqv 6,6,6", operands);
11381 return "b%T1l";
11382 }
11383 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg")
11384 (set_attr "length" "4,4,8,8")])
11386 (define_insn_and_split "*call_value_nonlocal_sysv<mode>"
11387 [(set (match_operand 0 "" "")
11388 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11389 (match_operand 2 "" "g,g")))
11390 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11391 (clobber (reg:SI LR_REGNO))]
11392 "(DEFAULT_ABI == ABI_DARWIN
11393 || (DEFAULT_ABI == ABI_V4
11394 && (INTVAL (operands[3]) & CALL_LONG) == 0))"
11395 {
11396 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11397 output_asm_insn ("crxor 6,6,6", operands);
11399 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11400 output_asm_insn ("creqv 6,6,6", operands);
11402 #if TARGET_MACHO
11403 return output_call(insn, operands, 1, 3);
11404 #else
11405 if (DEFAULT_ABI == ABI_V4 && flag_pic)
11406 {
11407 gcc_assert (!TARGET_SECURE_PLT);
11408 return "bl %z1@plt";
11409 }
11410 else
11411 return "bl %z1";
11412 #endif
11413 }
11414 "DEFAULT_ABI == ABI_V4
11415 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11416 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11417 [(parallel [(set (match_dup 0)
11418 (call (mem:SI (match_dup 1))
11419 (match_dup 2)))
11420 (use (match_dup 3))
11421 (use (match_dup 4))
11422 (clobber (reg:SI LR_REGNO))])]
11423 {
11424 operands[4] = pic_offset_table_rtx;
11425 }
11426 [(set_attr "type" "branch,branch")
11427 (set_attr "length" "4,8")])
11429 (define_insn "*call_value_nonlocal_sysv_secure<mode>"
11430 [(set (match_operand 0 "" "")
11431 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s"))
11432 (match_operand 2 "" "g,g")))
11433 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11434 (use (match_operand:SI 4 "register_operand" "r,r"))
11435 (clobber (reg:SI LR_REGNO))]
11436 "(DEFAULT_ABI == ABI_V4
11437 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1])
11438 && (INTVAL (operands[3]) & CALL_LONG) == 0)"
11439 {
11440 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11441 output_asm_insn ("crxor 6,6,6", operands);
11443 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11444 output_asm_insn ("creqv 6,6,6", operands);
11446 if (flag_pic == 2)
11447 return "bl %z1+32768@plt";
11448 else
11449 return "bl %z1@plt";
11450 }
11451 [(set_attr "type" "branch,branch")
11452 (set_attr "length" "4,8")])
11454 ;; Call subroutine returning any type.
11455 (define_expand "untyped_call"
11456 [(parallel [(call (match_operand 0 "" "")
11457 (const_int 0))
11458 (match_operand 1 "" "")
11459 (match_operand 2 "" "")])]
11460 ""
11461 "
11462 {
11463 int i;
11465 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11467 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11468 {
11469 rtx set = XVECEXP (operands[2], 0, i);
11470 emit_move_insn (SET_DEST (set), SET_SRC (set));
11471 }
11473 /* The optimizer does not know that the call sets the function value
11474 registers we stored in the result block. We avoid problems by
11475 claiming that all hard registers are used and clobbered at this
11476 point. */
11477 emit_insn (gen_blockage ());
11479 DONE;
11480 }")
11482 ;; sibling call patterns
11483 (define_expand "sibcall"
11484 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11485 (match_operand 1 "" ""))
11486 (use (match_operand 2 "" ""))
11487 (use (reg:SI LR_REGNO))
11488 (simple_return)])]
11489 ""
11490 "
11491 {
11492 #if TARGET_MACHO
11493 if (MACHOPIC_INDIRECT)
11494 operands[0] = machopic_indirect_call_target (operands[0]);
11495 #endif
11497 gcc_assert (GET_CODE (operands[0]) == MEM);
11498 gcc_assert (GET_CODE (operands[1]) == CONST_INT);
11500 operands[0] = XEXP (operands[0], 0);
11501 }")
11503 ;; this and similar patterns must be marked as using LR, otherwise
11504 ;; dataflow will try to delete the store into it. This is true
11505 ;; even when the actual reg to jump to is in CTR, when LR was
11506 ;; saved and restored around the PIC-setting BCL.
11507 (define_insn "*sibcall_local32"
11508 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11509 (match_operand 1 "" "g,g"))
11510 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11511 (use (reg:SI LR_REGNO))
11512 (simple_return)]
11513 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11514 "*
11515 {
11516 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11517 output_asm_insn (\"crxor 6,6,6\", operands);
11519 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11520 output_asm_insn (\"creqv 6,6,6\", operands);
11522 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11523 }"
11524 [(set_attr "type" "branch")
11525 (set_attr "length" "4,8")])
11527 (define_insn "*sibcall_local64"
11528 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11529 (match_operand 1 "" "g,g"))
11530 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11531 (use (reg:SI LR_REGNO))
11532 (simple_return)]
11533 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11534 "*
11535 {
11536 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11537 output_asm_insn (\"crxor 6,6,6\", operands);
11539 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11540 output_asm_insn (\"creqv 6,6,6\", operands);
11542 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11543 }"
11544 [(set_attr "type" "branch")
11545 (set_attr "length" "4,8")])
11547 (define_insn "*sibcall_value_local32"
11548 [(set (match_operand 0 "" "")
11549 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11550 (match_operand 2 "" "g,g")))
11551 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11552 (use (reg:SI LR_REGNO))
11553 (simple_return)]
11554 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11555 "*
11556 {
11557 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11558 output_asm_insn (\"crxor 6,6,6\", operands);
11560 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11561 output_asm_insn (\"creqv 6,6,6\", operands);
11563 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11564 }"
11565 [(set_attr "type" "branch")
11566 (set_attr "length" "4,8")])
11569 (define_insn "*sibcall_value_local64"
11570 [(set (match_operand 0 "" "")
11571 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11572 (match_operand 2 "" "g,g")))
11573 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11574 (use (reg:SI LR_REGNO))
11575 (simple_return)]
11576 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11577 "*
11578 {
11579 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11580 output_asm_insn (\"crxor 6,6,6\", operands);
11582 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11583 output_asm_insn (\"creqv 6,6,6\", operands);
11585 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11586 }"
11587 [(set_attr "type" "branch")
11588 (set_attr "length" "4,8")])
11590 (define_insn "*sibcall_nonlocal_aix<mode>"
11591 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c"))
11592 (match_operand 1 "" "g,g"))
11593 (use (match_operand:SI 2 "immediate_operand" "O,O"))
11594 (use (reg:SI LR_REGNO))
11595 (simple_return)]
11596 "DEFAULT_ABI == ABI_AIX
11597 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11598 "@
11599 b %z0
11600 b%T0"
11601 [(set_attr "type" "branch")
11602 (set_attr "length" "4")])
11604 (define_insn "*sibcall_value_nonlocal_aix<mode>"
11605 [(set (match_operand 0 "" "")
11606 (call (mem:SI (match_operand:P 1 "call_operand" "s,c"))
11607 (match_operand 2 "" "g,g")))
11608 (use (match_operand:SI 3 "immediate_operand" "O,O"))
11609 (use (reg:SI LR_REGNO))
11610 (simple_return)]
11611 "DEFAULT_ABI == ABI_AIX
11612 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11613 "@
11614 b %z1
11615 b%T1"
11616 [(set_attr "type" "branch")
11617 (set_attr "length" "4")])
11619 (define_insn "*sibcall_nonlocal_sysv<mode>"
11620 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c"))
11621 (match_operand 1 "" ""))
11622 (use (match_operand 2 "immediate_operand" "O,n,O,n"))
11623 (use (reg:SI LR_REGNO))
11624 (simple_return)]
11625 "(DEFAULT_ABI == ABI_DARWIN
11626 || DEFAULT_ABI == ABI_V4)
11627 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11628 "*
11629 {
11630 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11631 output_asm_insn (\"crxor 6,6,6\", operands);
11633 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11634 output_asm_insn (\"creqv 6,6,6\", operands);
11636 if (which_alternative >= 2)
11637 return \"b%T0\";
11638 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11639 {
11640 gcc_assert (!TARGET_SECURE_PLT);
11641 return \"b %z0@plt\";
11642 }
11643 else
11644 return \"b %z0\";
11645 }"
11646 [(set_attr "type" "branch")
11647 (set_attr "length" "4,8,4,8")])
11649 (define_expand "sibcall_value"
11650 [(parallel [(set (match_operand 0 "register_operand" "")
11651 (call (mem:SI (match_operand 1 "address_operand" ""))
11652 (match_operand 2 "" "")))
11653 (use (match_operand 3 "" ""))
11654 (use (reg:SI LR_REGNO))
11655 (simple_return)])]
11656 ""
11657 "
11658 {
11659 #if TARGET_MACHO
11660 if (MACHOPIC_INDIRECT)
11661 operands[1] = machopic_indirect_call_target (operands[1]);
11662 #endif
11664 gcc_assert (GET_CODE (operands[1]) == MEM);
11665 gcc_assert (GET_CODE (operands[2]) == CONST_INT);
11667 operands[1] = XEXP (operands[1], 0);
11668 }")
11670 (define_insn "*sibcall_value_nonlocal_sysv<mode>"
11671 [(set (match_operand 0 "" "")
11672 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c"))
11673 (match_operand 2 "" "")))
11674 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n"))
11675 (use (reg:SI LR_REGNO))
11676 (simple_return)]
11677 "(DEFAULT_ABI == ABI_DARWIN
11678 || DEFAULT_ABI == ABI_V4)
11679 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11680 "*
11681 {
11682 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11683 output_asm_insn (\"crxor 6,6,6\", operands);
11685 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11686 output_asm_insn (\"creqv 6,6,6\", operands);
11688 if (which_alternative >= 2)
11689 return \"b%T1\";
11690 else if (DEFAULT_ABI == ABI_V4 && flag_pic)
11691 {
11692 gcc_assert (!TARGET_SECURE_PLT);
11693 return \"b %z1@plt\";
11694 }
11695 else
11696 return \"b %z1\";
11697 }"
11698 [(set_attr "type" "branch")
11699 (set_attr "length" "4,8,4,8")])
11701 (define_expand "sibcall_epilogue"
11702 [(use (const_int 0))]
11703 ""
11704 {
11705 if (!TARGET_SCHED_PROLOG)
11706 emit_insn (gen_blockage ());
11707 rs6000_emit_epilogue (TRUE);
11708 DONE;
11709 })
11711 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11712 ;; all of memory. This blocks insns from being moved across this point.
11714 (define_insn "blockage"
11715 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)]
11716 ""
11717 "")
11719 (define_insn "probe_stack"
11720 [(set (match_operand 0 "memory_operand" "=m")
11721 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))]
11722 ""
11723 "*
11724 {
11725 operands[1] = gen_rtx_REG (Pmode, 0);
11726 return \"{st%U0%X0|stw%U0%X0} %1,%0\";
11727 }"
11728 [(set_attr "type" "store")
11729 (set_attr "length" "4")])
11731 (define_insn "probe_stack_range<P:mode>"
11732 [(set (match_operand:P 0 "register_operand" "=r")
11733 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
11734 (match_operand:P 2 "register_operand" "r")]
11735 UNSPECV_PROBE_STACK_RANGE))]
11736 ""
11737 "* return output_probe_stack_range (operands[0], operands[2]);"
11738 [(set_attr "type" "three")])
11739 \f
11740 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11741 ;; signed & unsigned, and one type of branch.
11742 ;;
11743 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11744 ;; insns, and branches.
11746 (define_expand "cbranch<mode>4"
11747 [(use (match_operator 0 "rs6000_cbranch_operator"
11748 [(match_operand:GPR 1 "gpc_reg_operand" "")
11749 (match_operand:GPR 2 "reg_or_short_operand" "")]))
11750 (use (match_operand 3 ""))]
11751 ""
11752 "
11753 {
11754 /* Take care of the possibility that operands[2] might be negative but
11755 this might be a logical operation. That insn doesn't exist. */
11756 if (GET_CODE (operands[2]) == CONST_INT
11757 && INTVAL (operands[2]) < 0)
11758 {
11759 operands[2] = force_reg (<MODE>mode, operands[2]);
11760 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]),
11761 GET_MODE (operands[0]),
11762 operands[1], operands[2]);
11763 }
11765 rs6000_emit_cbranch (<MODE>mode, operands);
11766 DONE;
11767 }")
11769 (define_expand "cbranch<mode>4"
11770 [(use (match_operator 0 "rs6000_cbranch_operator"
11771 [(match_operand:FP 1 "gpc_reg_operand" "")
11772 (match_operand:FP 2 "gpc_reg_operand" "")]))
11773 (use (match_operand 3 ""))]
11774 ""
11775 "
11776 {
11777 rs6000_emit_cbranch (<MODE>mode, operands);
11778 DONE;
11779 }")
11781 (define_expand "cstore<mode>4"
11782 [(use (match_operator 1 "rs6000_cbranch_operator"
11783 [(match_operand:GPR 2 "gpc_reg_operand" "")
11784 (match_operand:GPR 3 "reg_or_short_operand" "")]))
11785 (clobber (match_operand:SI 0 "register_operand"))]
11786 ""
11787 "
11788 {
11789 /* Take care of the possibility that operands[3] might be negative but
11790 this might be a logical operation. That insn doesn't exist. */
11791 if (GET_CODE (operands[3]) == CONST_INT
11792 && INTVAL (operands[3]) < 0)
11793 {
11794 operands[3] = force_reg (<MODE>mode, operands[3]);
11795 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]),
11796 GET_MODE (operands[1]),
11797 operands[2], operands[3]);
11798 }
11800 /* For SNE, we would prefer that the xor/abs sequence be used for integers.
11801 For SEQ, likewise, except that comparisons with zero should be done
11802 with an scc insns. However, due to the order that combine see the
11803 resulting insns, we must, in fact, allow SEQ for integers. Fail in
11804 the cases we don't want to handle or are best handled by portable
11805 code. */
11806 if (GET_CODE (operands[1]) == NE)
11807 FAIL;
11808 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE
11809 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE)
11810 && operands[3] == const0_rtx)
11811 FAIL;
11812 rs6000_emit_sCOND (<MODE>mode, operands);
11813 DONE;
11814 }")
11816 (define_expand "cstore<mode>4"
11817 [(use (match_operator 1 "rs6000_cbranch_operator"
11818 [(match_operand:FP 2 "gpc_reg_operand" "")
11819 (match_operand:FP 3 "gpc_reg_operand" "")]))
11820 (clobber (match_operand:SI 0 "register_operand"))]
11821 ""
11822 "
11823 {
11824 rs6000_emit_sCOND (<MODE>mode, operands);
11825 DONE;
11826 }")
11829 (define_expand "stack_protect_set"
11830 [(match_operand 0 "memory_operand" "")
11831 (match_operand 1 "memory_operand" "")]
11832 ""
11833 {
11834 #ifdef TARGET_THREAD_SSP_OFFSET
11835 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11836 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11837 operands[1] = gen_rtx_MEM (Pmode, addr);
11838 #endif
11839 if (TARGET_64BIT)
11840 emit_insn (gen_stack_protect_setdi (operands[0], operands[1]));
11841 else
11842 emit_insn (gen_stack_protect_setsi (operands[0], operands[1]));
11843 DONE;
11844 })
11846 (define_insn "stack_protect_setsi"
11847 [(set (match_operand:SI 0 "memory_operand" "=m")
11848 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
11849 (set (match_scratch:SI 2 "=&r") (const_int 0))]
11850 "TARGET_32BIT"
11851 "{l%U1%X1|lwz%U1%X1} %2,%1\;{st%U0%X0|stw%U0%X0} %2,%0\;{lil|li} %2,0"
11852 [(set_attr "type" "three")
11853 (set_attr "length" "12")])
11855 (define_insn "stack_protect_setdi"
11856 [(set (match_operand:DI 0 "memory_operand" "=Y")
11857 (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET))
11858 (set (match_scratch:DI 2 "=&r") (const_int 0))]
11859 "TARGET_64BIT"
11860 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;{lil|li} %2,0"
11861 [(set_attr "type" "three")
11862 (set_attr "length" "12")])
11864 (define_expand "stack_protect_test"
11865 [(match_operand 0 "memory_operand" "")
11866 (match_operand 1 "memory_operand" "")
11867 (match_operand 2 "" "")]
11868 ""
11869 {
11870 rtx test, op0, op1;
11871 #ifdef TARGET_THREAD_SSP_OFFSET
11872 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2);
11873 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET));
11874 operands[1] = gen_rtx_MEM (Pmode, addr);
11875 #endif
11876 op0 = operands[0];
11877 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST);
11878 test = gen_rtx_EQ (VOIDmode, op0, op1);
11879 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2]));
11880 DONE;
11881 })
11883 (define_insn "stack_protect_testsi"
11884 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11885 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
11886 (match_operand:SI 2 "memory_operand" "m,m")]
11887 UNSPEC_SP_TEST))
11888 (set (match_scratch:SI 4 "=r,r") (const_int 0))
11889 (clobber (match_scratch:SI 3 "=&r,&r"))]
11890 "TARGET_32BIT"
11891 "@
11892 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11893 {l%U1%X1|lwz%U1%X1} %3,%1\;{l%U2%X2|lwz%U2%X2} %4,%2\;{cmpl|cmplw} %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11894 [(set_attr "length" "16,20")])
11896 (define_insn "stack_protect_testdi"
11897 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
11898 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y")
11899 (match_operand:DI 2 "memory_operand" "Y,Y")]
11900 UNSPEC_SP_TEST))
11901 (set (match_scratch:DI 4 "=r,r") (const_int 0))
11902 (clobber (match_scratch:DI 3 "=&r,&r"))]
11903 "TARGET_64BIT"
11904 "@
11905 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;{lil|li} %4,0
11906 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;{lil|li} %3,0\;{lil|li} %4,0"
11907 [(set_attr "length" "16,20")])
11909 \f
11910 ;; Here are the actual compare insns.
11911 (define_insn "*cmp<mode>_internal1"
11912 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11913 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r")
11914 (match_operand:GPR 2 "reg_or_short_operand" "rI")))]
11915 ""
11916 "{cmp%I2|cmp<wd>%I2} %0,%1,%2"
11917 [(set_attr "type" "cmp")])
11919 ;; If we are comparing a register for equality with a large constant,
11920 ;; we can do this with an XOR followed by a compare. But this is profitable
11921 ;; only if the large constant is only used for the comparison (and in this
11922 ;; case we already have a register to reuse as scratch).
11923 ;;
11924 ;; For 64-bit registers, we could only do so if the constant's bit 15 is clear:
11925 ;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available.
11927 (define_peephole2
11928 [(set (match_operand:SI 0 "register_operand")
11929 (match_operand:SI 1 "logical_const_operand" ""))
11930 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator"
11931 [(match_dup 0)
11932 (match_operand:SI 2 "logical_const_operand" "")]))
11933 (set (match_operand:CC 4 "cc_reg_operand" "")
11934 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "")
11935 (match_dup 0)))
11936 (set (pc)
11937 (if_then_else (match_operator 6 "equality_operator"
11938 [(match_dup 4) (const_int 0)])
11939 (match_operand 7 "" "")
11940 (match_operand 8 "" "")))]
11941 "peep2_reg_dead_p (3, operands[0])
11942 && peep2_reg_dead_p (4, operands[4])"
11943 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9)))
11944 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10)))
11945 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))]
11947 {
11948 /* Get the constant we are comparing against, and see what it looks like
11949 when sign-extended from 16 to 32 bits. Then see what constant we could
11950 XOR with SEXTC to get the sign-extended value. */
11951 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]),
11952 SImode,
11953 operands[1], operands[2]);
11954 HOST_WIDE_INT c = INTVAL (cnst);
11955 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11956 HOST_WIDE_INT xorv = c ^ sextc;
11958 operands[9] = GEN_INT (xorv);
11959 operands[10] = GEN_INT (sextc);
11960 })
11962 (define_insn "*cmpsi_internal2"
11963 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11964 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11965 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11966 ""
11967 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11968 [(set_attr "type" "cmp")])
11970 (define_insn "*cmpdi_internal2"
11971 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11972 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11973 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11974 ""
11975 "cmpld%I2 %0,%1,%b2"
11976 [(set_attr "type" "cmp")])
11978 ;; The following two insns don't exist as single insns, but if we provide
11979 ;; them, we can swap an add and compare, which will enable us to overlap more
11980 ;; of the required delay between a compare and branch. We generate code for
11981 ;; them by splitting.
11983 (define_insn ""
11984 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11985 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11986 (match_operand:SI 2 "short_cint_operand" "i")))
11987 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11988 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11989 ""
11990 "#"
11991 [(set_attr "length" "8")])
11993 (define_insn ""
11994 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11995 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11996 (match_operand:SI 2 "u_short_cint_operand" "i")))
11997 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11998 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11999 ""
12000 "#"
12001 [(set_attr "length" "8")])
12003 (define_split
12004 [(set (match_operand:CC 3 "cc_reg_operand" "")
12005 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
12006 (match_operand:SI 2 "short_cint_operand" "")))
12007 (set (match_operand:SI 0 "gpc_reg_operand" "")
12008 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12009 ""
12010 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
12011 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12013 (define_split
12014 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
12015 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
12016 (match_operand:SI 2 "u_short_cint_operand" "")))
12017 (set (match_operand:SI 0 "gpc_reg_operand" "")
12018 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
12019 ""
12020 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
12021 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
12023 (define_insn "*cmpsf_internal1"
12024 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12025 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
12026 (match_operand:SF 2 "gpc_reg_operand" "f")))]
12027 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT"
12028 "fcmpu %0,%1,%2"
12029 [(set_attr "type" "fpcompare")])
12031 (define_insn "*cmpdf_internal1"
12032 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12033 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "d")
12034 (match_operand:DF 2 "gpc_reg_operand" "d")))]
12035 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT
12036 && !VECTOR_UNIT_VSX_P (DFmode)"
12037 "fcmpu %0,%1,%2"
12038 [(set_attr "type" "fpcompare")])
12040 ;; Only need to compare second words if first words equal
12041 (define_insn "*cmptf_internal1"
12042 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12043 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12044 (match_operand:TF 2 "gpc_reg_operand" "d")))]
12045 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT
12046 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12047 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2"
12048 [(set_attr "type" "fpcompare")
12049 (set_attr "length" "12")])
12051 (define_insn_and_split "*cmptf_internal2"
12052 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
12053 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d")
12054 (match_operand:TF 2 "gpc_reg_operand" "d")))
12055 (clobber (match_scratch:DF 3 "=d"))
12056 (clobber (match_scratch:DF 4 "=d"))
12057 (clobber (match_scratch:DF 5 "=d"))
12058 (clobber (match_scratch:DF 6 "=d"))
12059 (clobber (match_scratch:DF 7 "=d"))
12060 (clobber (match_scratch:DF 8 "=d"))
12061 (clobber (match_scratch:DF 9 "=d"))
12062 (clobber (match_scratch:DF 10 "=d"))
12063 (clobber (match_scratch:GPR 11 "=b"))]
12064 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT
12065 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128"
12066 "#"
12067 "&& reload_completed"
12068 [(set (match_dup 3) (match_dup 14))
12069 (set (match_dup 4) (match_dup 15))
12070 (set (match_dup 9) (abs:DF (match_dup 5)))
12071 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3)))
12072 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0))
12073 (label_ref (match_dup 12))
12074 (pc)))
12075 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7)))
12076 (set (pc) (label_ref (match_dup 13)))
12077 (match_dup 12)
12078 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7)))
12079 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8)))
12080 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9)))
12081 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4)))
12082 (match_dup 13)]
12083 {
12084 REAL_VALUE_TYPE rv;
12085 const int lo_word = FLOAT_WORDS_BIG_ENDIAN ? GET_MODE_SIZE (DFmode) : 0;
12086 const int hi_word = FLOAT_WORDS_BIG_ENDIAN ? 0 : GET_MODE_SIZE (DFmode);
12088 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word);
12089 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word);
12090 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word);
12091 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word);
12092 operands[12] = gen_label_rtx ();
12093 operands[13] = gen_label_rtx ();
12094 real_inf (&rv);
12095 operands[14] = force_const_mem (DFmode,
12096 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode));
12097 operands[15] = force_const_mem (DFmode,
12098 CONST_DOUBLE_FROM_REAL_VALUE (dconst0,
12099 DFmode));
12100 if (TARGET_TOC)
12101 {
12102 rtx tocref;
12103 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]);
12104 operands[14] = gen_const_mem (DFmode, tocref);
12105 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]);
12106 operands[15] = gen_const_mem (DFmode, tocref);
12107 set_mem_alias_set (operands[14], get_TOC_alias_set ());
12108 set_mem_alias_set (operands[15], get_TOC_alias_set ());
12109 }
12110 })
12111 \f
12112 ;; Now we have the scc insns. We can do some combinations because of the
12113 ;; way the machine works.
12114 ;;
12115 ;; Note that this is probably faster if we can put an insn between the
12116 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
12117 ;; cases the insns below which don't use an intermediate CR field will
12118 ;; be used instead.
12119 (define_insn ""
12120 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12121 (match_operator:SI 1 "scc_comparison_operator"
12122 [(match_operand 2 "cc_reg_operand" "y")
12123 (const_int 0)]))]
12124 ""
12125 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12126 [(set (attr "type")
12127 (cond [(match_test "TARGET_MFCRF")
12128 (const_string "mfcrf")
12129 ]
12130 (const_string "mfcr")))
12131 (set_attr "length" "8")])
12133 ;; Same as above, but get the GT bit.
12134 (define_insn "move_from_CR_gt_bit"
12135 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12136 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))]
12137 "TARGET_HARD_FLOAT && !TARGET_FPRS"
12138 "mfcr %0\;{rlinm|rlwinm} %0,%0,%D1,31,31"
12139 [(set_attr "type" "mfcr")
12140 (set_attr "length" "8")])
12142 ;; Same as above, but get the OV/ORDERED bit.
12143 (define_insn "move_from_CR_ov_bit"
12144 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12145 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_OV))]
12146 "TARGET_ISEL"
12147 "mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
12148 [(set_attr "type" "mfcr")
12149 (set_attr "length" "8")])
12151 (define_insn ""
12152 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12153 (match_operator:DI 1 "scc_comparison_operator"
12154 [(match_operand 2 "cc_reg_operand" "y")
12155 (const_int 0)]))]
12156 "TARGET_POWERPC64"
12157 "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
12158 [(set (attr "type")
12159 (cond [(match_test "TARGET_MFCRF")
12160 (const_string "mfcrf")
12161 ]
12162 (const_string "mfcr")))
12163 (set_attr "length" "8")])
12165 (define_insn ""
12166 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12167 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12168 [(match_operand 2 "cc_reg_operand" "y,y")
12169 (const_int 0)])
12170 (const_int 0)))
12171 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
12172 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12173 "TARGET_32BIT"
12174 "@
12175 mfcr %3%Q2\;{rlinm.|rlwinm.} %3,%3,%J1,1
12176 #"
12177 [(set_attr "type" "delayed_compare")
12178 (set_attr "length" "8,16")])
12180 (define_split
12181 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12182 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
12183 [(match_operand 2 "cc_reg_operand" "")
12184 (const_int 0)])
12185 (const_int 0)))
12186 (set (match_operand:SI 3 "gpc_reg_operand" "")
12187 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
12188 "TARGET_32BIT && reload_completed"
12189 [(set (match_dup 3)
12190 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
12191 (set (match_dup 0)
12192 (compare:CC (match_dup 3)
12193 (const_int 0)))]
12194 "")
12196 (define_insn ""
12197 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12198 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12199 [(match_operand 2 "cc_reg_operand" "y")
12200 (const_int 0)])
12201 (match_operand:SI 3 "const_int_operand" "n")))]
12202 ""
12203 "*
12204 {
12205 int is_bit = ccr_bit (operands[1], 1);
12206 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12207 int count;
12209 if (is_bit >= put_bit)
12210 count = is_bit - put_bit;
12211 else
12212 count = 32 - (put_bit - is_bit);
12214 operands[4] = GEN_INT (count);
12215 operands[5] = GEN_INT (put_bit);
12217 return \"mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
12218 }"
12219 [(set (attr "type")
12220 (cond [(match_test "TARGET_MFCRF")
12221 (const_string "mfcrf")
12222 ]
12223 (const_string "mfcr")))
12224 (set_attr "length" "8")])
12226 (define_insn ""
12227 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12228 (compare:CC
12229 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12230 [(match_operand 2 "cc_reg_operand" "y,y")
12231 (const_int 0)])
12232 (match_operand:SI 3 "const_int_operand" "n,n"))
12233 (const_int 0)))
12234 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
12235 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12236 (match_dup 3)))]
12237 ""
12238 "*
12239 {
12240 int is_bit = ccr_bit (operands[1], 1);
12241 int put_bit = 31 - (INTVAL (operands[3]) & 31);
12242 int count;
12244 /* Force split for non-cc0 compare. */
12245 if (which_alternative == 1)
12246 return \"#\";
12248 if (is_bit >= put_bit)
12249 count = is_bit - put_bit;
12250 else
12251 count = 32 - (put_bit - is_bit);
12253 operands[5] = GEN_INT (count);
12254 operands[6] = GEN_INT (put_bit);
12256 return \"mfcr %4%Q2\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
12257 }"
12258 [(set_attr "type" "delayed_compare")
12259 (set_attr "length" "8,16")])
12261 (define_split
12262 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12263 (compare:CC
12264 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
12265 [(match_operand 2 "cc_reg_operand" "")
12266 (const_int 0)])
12267 (match_operand:SI 3 "const_int_operand" ""))
12268 (const_int 0)))
12269 (set (match_operand:SI 4 "gpc_reg_operand" "")
12270 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12271 (match_dup 3)))]
12272 "reload_completed"
12273 [(set (match_dup 4)
12274 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
12275 (match_dup 3)))
12276 (set (match_dup 0)
12277 (compare:CC (match_dup 4)
12278 (const_int 0)))]
12279 "")
12281 ;; There is a 3 cycle delay between consecutive mfcr instructions
12282 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
12284 (define_peephole
12285 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12286 (match_operator:SI 1 "scc_comparison_operator"
12287 [(match_operand 2 "cc_reg_operand" "y")
12288 (const_int 0)]))
12289 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
12290 (match_operator:SI 4 "scc_comparison_operator"
12291 [(match_operand 5 "cc_reg_operand" "y")
12292 (const_int 0)]))]
12293 "REGNO (operands[2]) != REGNO (operands[5])"
12294 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12295 [(set_attr "type" "mfcr")
12296 (set_attr "length" "12")])
12298 (define_peephole
12299 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12300 (match_operator:DI 1 "scc_comparison_operator"
12301 [(match_operand 2 "cc_reg_operand" "y")
12302 (const_int 0)]))
12303 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
12304 (match_operator:DI 4 "scc_comparison_operator"
12305 [(match_operand 5 "cc_reg_operand" "y")
12306 (const_int 0)]))]
12307 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
12308 "mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
12309 [(set_attr "type" "mfcr")
12310 (set_attr "length" "12")])
12312 ;; There are some scc insns that can be done directly, without a compare.
12313 ;; These are faster because they don't involve the communications between
12314 ;; the FXU and branch units. In fact, we will be replacing all of the
12315 ;; integer scc insns here or in the portable methods in emit_store_flag.
12316 ;;
12317 ;; Also support (neg (scc ..)) since that construct is used to replace
12318 ;; branches, (plus (scc ..) ..) since that construct is common and
12319 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
12320 ;; cases where it is no more expensive than (neg (scc ..)).
12322 ;; Have reload force a constant into a register for the simple insns that
12323 ;; otherwise won't accept constants. We do this because it is faster than
12324 ;; the cmp/mfcr sequence we would otherwise generate.
12326 (define_mode_attr scc_eq_op2 [(SI "rKLI")
12327 (DI "rKJI")])
12329 (define_insn_and_split "*eq<mode>"
12330 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
12331 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
12332 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))]
12333 ""
12334 "#"
12335 ""
12336 [(set (match_dup 0)
12337 (clz:GPR (match_dup 3)))
12338 (set (match_dup 0)
12339 (lshiftrt:GPR (match_dup 0) (match_dup 4)))]
12340 {
12341 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12342 {
12343 /* Use output operand as intermediate. */
12344 operands[3] = operands[0];
12346 if (logical_operand (operands[2], <MODE>mode))
12347 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12348 gen_rtx_XOR (<MODE>mode,
12349 operands[1], operands[2])));
12350 else
12351 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12352 gen_rtx_PLUS (<MODE>mode, operands[1],
12353 negate_rtx (<MODE>mode,
12354 operands[2]))));
12355 }
12356 else
12357 operands[3] = operands[1];
12359 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12360 })
12362 (define_insn_and_split "*eq<mode>_compare"
12363 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
12364 (compare:CC
12365 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r")
12366 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))
12367 (const_int 0)))
12368 (set (match_operand:P 0 "gpc_reg_operand" "=r")
12369 (eq:P (match_dup 1) (match_dup 2)))]
12370 "optimize_size"
12371 "#"
12372 "optimize_size"
12373 [(set (match_dup 0)
12374 (clz:P (match_dup 4)))
12375 (parallel [(set (match_dup 3)
12376 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5))
12377 (const_int 0)))
12378 (set (match_dup 0)
12379 (lshiftrt:P (match_dup 0) (match_dup 5)))])]
12380 {
12381 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12382 {
12383 /* Use output operand as intermediate. */
12384 operands[4] = operands[0];
12386 if (logical_operand (operands[2], <MODE>mode))
12387 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12388 gen_rtx_XOR (<MODE>mode,
12389 operands[1], operands[2])));
12390 else
12391 emit_insn (gen_rtx_SET (VOIDmode, operands[4],
12392 gen_rtx_PLUS (<MODE>mode, operands[1],
12393 negate_rtx (<MODE>mode,
12394 operands[2]))));
12395 }
12396 else
12397 operands[4] = operands[1];
12399 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode)));
12400 })
12402 ;; We have insns of the form shown by the first define_insn below. If
12403 ;; there is something inside the comparison operation, we must split it.
12404 (define_split
12405 [(set (match_operand:SI 0 "gpc_reg_operand" "")
12406 (plus:SI (match_operator 1 "comparison_operator"
12407 [(match_operand:SI 2 "" "")
12408 (match_operand:SI 3
12409 "reg_or_cint_operand" "")])
12410 (match_operand:SI 4 "gpc_reg_operand" "")))
12411 (clobber (match_operand:SI 5 "register_operand" ""))]
12412 "! gpc_reg_operand (operands[2], SImode)"
12413 [(set (match_dup 5) (match_dup 2))
12414 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
12415 (match_dup 4)))])
12417 (define_insn "*plus_eqsi"
12418 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
12419 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12420 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
12421 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
12422 "TARGET_32BIT"
12423 "@
12424 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12425 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
12426 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12427 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12428 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12429 [(set_attr "type" "three,two,three,three,three")
12430 (set_attr "length" "12,8,12,12,12")])
12432 (define_insn "*compare_plus_eqsi"
12433 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12434 (compare:CC
12435 (plus:SI
12436 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12437 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12438 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12439 (const_int 0)))
12440 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12441 "TARGET_32BIT && optimize_size"
12442 "@
12443 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12444 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
12445 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12446 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12447 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12448 #
12449 #
12450 #
12451 #
12452 #"
12453 [(set_attr "type" "compare")
12454 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12456 (define_split
12457 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12458 (compare:CC
12459 (plus:SI
12460 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12461 (match_operand:SI 2 "scc_eq_operand" ""))
12462 (match_operand:SI 3 "gpc_reg_operand" ""))
12463 (const_int 0)))
12464 (clobber (match_scratch:SI 4 ""))]
12465 "TARGET_32BIT && optimize_size && reload_completed"
12466 [(set (match_dup 4)
12467 (plus:SI (eq:SI (match_dup 1)
12468 (match_dup 2))
12469 (match_dup 3)))
12470 (set (match_dup 0)
12471 (compare:CC (match_dup 4)
12472 (const_int 0)))]
12473 "")
12475 (define_insn "*plus_eqsi_compare"
12476 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12477 (compare:CC
12478 (plus:SI
12479 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12480 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
12481 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12482 (const_int 0)))
12483 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12484 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12485 "TARGET_32BIT && optimize_size"
12486 "@
12487 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12488 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12489 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12490 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12491 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12492 #
12493 #
12494 #
12495 #
12496 #"
12497 [(set_attr "type" "compare")
12498 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12500 (define_split
12501 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12502 (compare:CC
12503 (plus:SI
12504 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12505 (match_operand:SI 2 "scc_eq_operand" ""))
12506 (match_operand:SI 3 "gpc_reg_operand" ""))
12507 (const_int 0)))
12508 (set (match_operand:SI 0 "gpc_reg_operand" "")
12509 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12510 "TARGET_32BIT && optimize_size && reload_completed"
12511 [(set (match_dup 0)
12512 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12513 (set (match_dup 4)
12514 (compare:CC (match_dup 0)
12515 (const_int 0)))]
12516 "")
12518 (define_insn "*neg_eq0<mode>"
12519 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12520 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r")
12521 (const_int 0))))]
12522 ""
12523 "{ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0"
12524 [(set_attr "type" "two")
12525 (set_attr "length" "8")])
12527 (define_insn_and_split "*neg_eq<mode>"
12528 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12529 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r")
12530 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))]
12531 ""
12532 "#"
12533 ""
12534 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))]
12535 {
12536 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)
12537 {
12538 /* Use output operand as intermediate. */
12539 operands[3] = operands[0];
12541 if (logical_operand (operands[2], <MODE>mode))
12542 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12543 gen_rtx_XOR (<MODE>mode,
12544 operands[1], operands[2])));
12545 else
12546 emit_insn (gen_rtx_SET (VOIDmode, operands[3],
12547 gen_rtx_PLUS (<MODE>mode, operands[1],
12548 negate_rtx (<MODE>mode,
12549 operands[2]))));
12550 }
12551 else
12552 operands[3] = operands[1];
12553 })
12555 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12556 ;; since it nabs/sr is just as fast.
12557 (define_insn "*ne0si"
12558 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12559 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12560 (const_int 31)))
12561 (clobber (match_scratch:SI 2 "=&r"))]
12562 "TARGET_32BIT && !TARGET_ISEL"
12563 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
12564 [(set_attr "type" "two")
12565 (set_attr "length" "8")])
12567 (define_insn "*ne0di"
12568 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12569 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12570 (const_int 63)))
12571 (clobber (match_scratch:DI 2 "=&r"))]
12572 "TARGET_64BIT"
12573 "addic %2,%1,-1\;subfe %0,%2,%1"
12574 [(set_attr "type" "two")
12575 (set_attr "length" "8")])
12577 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
12578 (define_insn "*plus_ne0si"
12579 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12580 (plus:SI (lshiftrt:SI
12581 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12582 (const_int 31))
12583 (match_operand:SI 2 "gpc_reg_operand" "r")))
12584 (clobber (match_scratch:SI 3 "=&r"))]
12585 "TARGET_32BIT"
12586 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
12587 [(set_attr "type" "two")
12588 (set_attr "length" "8")])
12590 (define_insn "*plus_ne0di"
12591 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12592 (plus:DI (lshiftrt:DI
12593 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12594 (const_int 63))
12595 (match_operand:DI 2 "gpc_reg_operand" "r")))
12596 (clobber (match_scratch:DI 3 "=&r"))]
12597 "TARGET_64BIT"
12598 "addic %3,%1,-1\;addze %0,%2"
12599 [(set_attr "type" "two")
12600 (set_attr "length" "8")])
12602 (define_insn "*compare_plus_ne0si"
12603 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12604 (compare:CC
12605 (plus:SI (lshiftrt:SI
12606 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12607 (const_int 31))
12608 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12609 (const_int 0)))
12610 (clobber (match_scratch:SI 3 "=&r,&r"))
12611 (clobber (match_scratch:SI 4 "=X,&r"))]
12612 "TARGET_32BIT"
12613 "@
12614 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12615 #"
12616 [(set_attr "type" "compare")
12617 (set_attr "length" "8,12")])
12619 (define_split
12620 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12621 (compare:CC
12622 (plus:SI (lshiftrt:SI
12623 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12624 (const_int 31))
12625 (match_operand:SI 2 "gpc_reg_operand" ""))
12626 (const_int 0)))
12627 (clobber (match_scratch:SI 3 ""))
12628 (clobber (match_scratch:SI 4 ""))]
12629 "TARGET_32BIT && reload_completed"
12630 [(parallel [(set (match_dup 3)
12631 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12632 (const_int 31))
12633 (match_dup 2)))
12634 (clobber (match_dup 4))])
12635 (set (match_dup 0)
12636 (compare:CC (match_dup 3)
12637 (const_int 0)))]
12638 "")
12640 (define_insn "*compare_plus_ne0di"
12641 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12642 (compare:CC
12643 (plus:DI (lshiftrt:DI
12644 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12645 (const_int 63))
12646 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12647 (const_int 0)))
12648 (clobber (match_scratch:DI 3 "=&r,&r"))]
12649 "TARGET_64BIT"
12650 "@
12651 addic %3,%1,-1\;addze. %3,%2
12652 #"
12653 [(set_attr "type" "compare")
12654 (set_attr "length" "8,12")])
12656 (define_split
12657 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
12658 (compare:CC
12659 (plus:DI (lshiftrt:DI
12660 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12661 (const_int 63))
12662 (match_operand:DI 2 "gpc_reg_operand" ""))
12663 (const_int 0)))
12664 (clobber (match_scratch:DI 3 ""))]
12665 "TARGET_64BIT && reload_completed"
12666 [(set (match_dup 3)
12667 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12668 (const_int 63))
12669 (match_dup 2)))
12670 (set (match_dup 0)
12671 (compare:CC (match_dup 3)
12672 (const_int 0)))]
12673 "")
12675 (define_insn "*plus_ne0si_compare"
12676 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12677 (compare:CC
12678 (plus:SI (lshiftrt:SI
12679 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12680 (const_int 31))
12681 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12682 (const_int 0)))
12683 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12684 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12685 (match_dup 2)))
12686 (clobber (match_scratch:SI 3 "=&r,&r"))]
12687 "TARGET_32BIT"
12688 "@
12689 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12690 #"
12691 [(set_attr "type" "compare")
12692 (set_attr "length" "8,12")])
12694 (define_split
12695 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12696 (compare:CC
12697 (plus:SI (lshiftrt:SI
12698 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12699 (const_int 31))
12700 (match_operand:SI 2 "gpc_reg_operand" ""))
12701 (const_int 0)))
12702 (set (match_operand:SI 0 "gpc_reg_operand" "")
12703 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12704 (match_dup 2)))
12705 (clobber (match_scratch:SI 3 ""))]
12706 "TARGET_32BIT && reload_completed"
12707 [(parallel [(set (match_dup 0)
12708 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12709 (match_dup 2)))
12710 (clobber (match_dup 3))])
12711 (set (match_dup 4)
12712 (compare:CC (match_dup 0)
12713 (const_int 0)))]
12714 "")
12716 (define_insn "*plus_ne0di_compare"
12717 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12718 (compare:CC
12719 (plus:DI (lshiftrt:DI
12720 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12721 (const_int 63))
12722 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12723 (const_int 0)))
12724 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12725 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12726 (match_dup 2)))
12727 (clobber (match_scratch:DI 3 "=&r,&r"))]
12728 "TARGET_64BIT"
12729 "@
12730 addic %3,%1,-1\;addze. %0,%2
12731 #"
12732 [(set_attr "type" "compare")
12733 (set_attr "length" "8,12")])
12735 (define_split
12736 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "")
12737 (compare:CC
12738 (plus:DI (lshiftrt:DI
12739 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12740 (const_int 63))
12741 (match_operand:DI 2 "gpc_reg_operand" ""))
12742 (const_int 0)))
12743 (set (match_operand:DI 0 "gpc_reg_operand" "")
12744 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12745 (match_dup 2)))
12746 (clobber (match_scratch:DI 3 ""))]
12747 "TARGET_64BIT && reload_completed"
12748 [(parallel [(set (match_dup 0)
12749 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12750 (match_dup 2)))
12751 (clobber (match_dup 3))])
12752 (set (match_dup 4)
12753 (compare:CC (match_dup 0)
12754 (const_int 0)))]
12755 "")
12757 (define_insn "*leu<mode>"
12758 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12759 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12760 (match_operand:P 2 "reg_or_short_operand" "rI")))]
12761 ""
12762 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12763 [(set_attr "type" "three")
12764 (set_attr "length" "12")])
12766 (define_insn "*leu<mode>_compare"
12767 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12768 (compare:CC
12769 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12770 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
12771 (const_int 0)))
12772 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12773 (leu:P (match_dup 1) (match_dup 2)))]
12774 ""
12775 "@
12776 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12777 #"
12778 [(set_attr "type" "compare")
12779 (set_attr "length" "12,16")])
12781 (define_split
12782 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12783 (compare:CC
12784 (leu:P (match_operand:P 1 "gpc_reg_operand" "")
12785 (match_operand:P 2 "reg_or_short_operand" ""))
12786 (const_int 0)))
12787 (set (match_operand:P 0 "gpc_reg_operand" "")
12788 (leu:P (match_dup 1) (match_dup 2)))]
12789 "reload_completed"
12790 [(set (match_dup 0)
12791 (leu:P (match_dup 1) (match_dup 2)))
12792 (set (match_dup 3)
12793 (compare:CC (match_dup 0)
12794 (const_int 0)))]
12795 "")
12797 (define_insn "*plus_leu<mode>"
12798 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12799 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12800 (match_operand:P 2 "reg_or_short_operand" "rI"))
12801 (match_operand:P 3 "gpc_reg_operand" "r")))]
12802 ""
12803 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12804 [(set_attr "type" "two")
12805 (set_attr "length" "8")])
12807 (define_insn ""
12808 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12809 (compare:CC
12810 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12811 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12812 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12813 (const_int 0)))
12814 (clobber (match_scratch:SI 4 "=&r,&r"))]
12815 "TARGET_32BIT"
12816 "@
12817 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12818 #"
12819 [(set_attr "type" "compare")
12820 (set_attr "length" "8,12")])
12822 (define_split
12823 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12824 (compare:CC
12825 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12826 (match_operand:SI 2 "reg_or_short_operand" ""))
12827 (match_operand:SI 3 "gpc_reg_operand" ""))
12828 (const_int 0)))
12829 (clobber (match_scratch:SI 4 ""))]
12830 "TARGET_32BIT && reload_completed"
12831 [(set (match_dup 4)
12832 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12833 (match_dup 3)))
12834 (set (match_dup 0)
12835 (compare:CC (match_dup 4)
12836 (const_int 0)))]
12837 "")
12839 (define_insn ""
12840 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12841 (compare:CC
12842 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12843 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12844 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12845 (const_int 0)))
12846 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12847 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12848 "TARGET_32BIT"
12849 "@
12850 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12851 #"
12852 [(set_attr "type" "compare")
12853 (set_attr "length" "8,12")])
12855 (define_split
12856 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12857 (compare:CC
12858 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12859 (match_operand:SI 2 "reg_or_short_operand" ""))
12860 (match_operand:SI 3 "gpc_reg_operand" ""))
12861 (const_int 0)))
12862 (set (match_operand:SI 0 "gpc_reg_operand" "")
12863 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12864 "TARGET_32BIT && reload_completed"
12865 [(set (match_dup 0)
12866 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12867 (set (match_dup 4)
12868 (compare:CC (match_dup 0)
12869 (const_int 0)))]
12870 "")
12872 (define_insn "*neg_leu<mode>"
12873 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
12874 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12875 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
12876 ""
12877 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12878 [(set_attr "type" "three")
12879 (set_attr "length" "12")])
12881 (define_insn "*and_neg_leu<mode>"
12882 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
12883 (and:P (neg:P
12884 (leu:P (match_operand:P 1 "gpc_reg_operand" "r")
12885 (match_operand:P 2 "reg_or_short_operand" "rI")))
12886 (match_operand:P 3 "gpc_reg_operand" "r")))]
12887 ""
12888 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12889 [(set_attr "type" "three")
12890 (set_attr "length" "12")])
12892 (define_insn ""
12893 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12894 (compare:CC
12895 (and:SI (neg:SI
12896 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12897 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12898 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12899 (const_int 0)))
12900 (clobber (match_scratch:SI 4 "=&r,&r"))]
12901 "TARGET_32BIT"
12902 "@
12903 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12904 #"
12905 [(set_attr "type" "compare")
12906 (set_attr "length" "12,16")])
12908 (define_split
12909 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12910 (compare:CC
12911 (and:SI (neg:SI
12912 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12913 (match_operand:SI 2 "reg_or_short_operand" "")))
12914 (match_operand:SI 3 "gpc_reg_operand" ""))
12915 (const_int 0)))
12916 (clobber (match_scratch:SI 4 ""))]
12917 "TARGET_32BIT && reload_completed"
12918 [(set (match_dup 4)
12919 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12920 (match_dup 3)))
12921 (set (match_dup 0)
12922 (compare:CC (match_dup 4)
12923 (const_int 0)))]
12924 "")
12926 (define_insn ""
12927 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12928 (compare:CC
12929 (and:SI (neg:SI
12930 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12931 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12932 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12933 (const_int 0)))
12934 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12935 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12936 "TARGET_32BIT"
12937 "@
12938 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12939 #"
12940 [(set_attr "type" "compare")
12941 (set_attr "length" "12,16")])
12943 (define_split
12944 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12945 (compare:CC
12946 (and:SI (neg:SI
12947 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12948 (match_operand:SI 2 "reg_or_short_operand" "")))
12949 (match_operand:SI 3 "gpc_reg_operand" ""))
12950 (const_int 0)))
12951 (set (match_operand:SI 0 "gpc_reg_operand" "")
12952 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12953 "TARGET_32BIT && reload_completed"
12954 [(set (match_dup 0)
12955 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12956 (match_dup 3)))
12957 (set (match_dup 4)
12958 (compare:CC (match_dup 0)
12959 (const_int 0)))]
12960 "")
12962 (define_insn_and_split "*ltu<mode>"
12963 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
12964 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12965 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
12966 ""
12967 "#"
12968 ""
12969 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12970 (set (match_dup 0) (neg:P (match_dup 0)))]
12971 "")
12973 (define_insn_and_split "*ltu<mode>_compare"
12974 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12975 (compare:CC
12976 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
12977 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
12978 (const_int 0)))
12979 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
12980 (ltu:P (match_dup 1) (match_dup 2)))]
12981 ""
12982 "#"
12983 ""
12984 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12985 (parallel [(set (match_dup 3)
12986 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
12987 (set (match_dup 0) (neg:P (match_dup 0)))])]
12988 "")
12990 (define_insn_and_split "*plus_ltu<mode>"
12991 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r")
12992 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
12993 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
12994 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))]
12995 ""
12996 "#"
12997 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
12998 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
12999 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13000 "")
13002 (define_insn_and_split "*plus_ltu<mode>_compare"
13003 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13004 (compare:CC
13005 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13006 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13007 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13008 (const_int 0)))
13009 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13010 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13011 ""
13012 "#"
13013 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13014 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2))))
13015 (parallel [(set (match_dup 4)
13016 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13017 (const_int 0)))
13018 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13019 "")
13021 (define_insn "*neg_ltu<mode>"
13022 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13023 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13024 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))]
13025 ""
13026 "@
13027 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
13028 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
13029 [(set_attr "type" "two")
13030 (set_attr "length" "8")])
13032 (define_insn "*geu<mode>"
13033 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13034 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13035 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))]
13036 ""
13037 "@
13038 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
13039 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13040 [(set_attr "type" "three")
13041 (set_attr "length" "12")])
13043 (define_insn "*geu<mode>_compare"
13044 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13045 (compare:CC
13046 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13047 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P"))
13048 (const_int 0)))
13049 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r")
13050 (geu:P (match_dup 1) (match_dup 2)))]
13051 ""
13052 "@
13053 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13054 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13055 #
13056 #"
13057 [(set_attr "type" "compare")
13058 (set_attr "length" "12,12,16,16")])
13060 (define_split
13061 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
13062 (compare:CC
13063 (geu:P (match_operand:P 1 "gpc_reg_operand" "")
13064 (match_operand:P 2 "reg_or_neg_short_operand" ""))
13065 (const_int 0)))
13066 (set (match_operand:P 0 "gpc_reg_operand" "")
13067 (geu:P (match_dup 1) (match_dup 2)))]
13068 "reload_completed"
13069 [(set (match_dup 0)
13070 (geu:P (match_dup 1) (match_dup 2)))
13071 (set (match_dup 3)
13072 (compare:CC (match_dup 0)
13073 (const_int 0)))]
13074 "")
13076 (define_insn "*plus_geu<mode>"
13077 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13078 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13079 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))
13080 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13081 ""
13082 "@
13083 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13084 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
13085 [(set_attr "type" "two")
13086 (set_attr "length" "8")])
13088 (define_insn ""
13089 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13090 (compare:CC
13091 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13092 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13093 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13094 (const_int 0)))
13095 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13096 "TARGET_32BIT"
13097 "@
13098 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
13099 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13100 #
13101 #"
13102 [(set_attr "type" "compare")
13103 (set_attr "length" "8,8,12,12")])
13105 (define_split
13106 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13107 (compare:CC
13108 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13109 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13110 (match_operand:SI 3 "gpc_reg_operand" ""))
13111 (const_int 0)))
13112 (clobber (match_scratch:SI 4 ""))]
13113 "TARGET_32BIT && reload_completed"
13114 [(set (match_dup 4)
13115 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13116 (match_dup 3)))
13117 (set (match_dup 0)
13118 (compare:CC (match_dup 4)
13119 (const_int 0)))]
13120 "")
13122 (define_insn ""
13123 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13124 (compare:CC
13125 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13126 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13127 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13128 (const_int 0)))
13129 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13130 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13131 "TARGET_32BIT"
13132 "@
13133 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13134 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
13135 #
13136 #"
13137 [(set_attr "type" "compare")
13138 (set_attr "length" "8,8,12,12")])
13140 (define_split
13141 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13142 (compare:CC
13143 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13144 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13145 (match_operand:SI 3 "gpc_reg_operand" ""))
13146 (const_int 0)))
13147 (set (match_operand:SI 0 "gpc_reg_operand" "")
13148 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13149 "TARGET_32BIT && reload_completed"
13150 [(set (match_dup 0)
13151 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13152 (set (match_dup 4)
13153 (compare:CC (match_dup 0)
13154 (const_int 0)))]
13155 "")
13157 (define_insn "*neg_geu<mode>"
13158 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13159 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13160 (match_operand:P 2 "reg_or_short_operand" "r,I"))))]
13161 ""
13162 "@
13163 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
13164 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
13165 [(set_attr "type" "three")
13166 (set_attr "length" "12")])
13168 (define_insn "*and_neg_geu<mode>"
13169 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r")
13170 (and:P (neg:P
13171 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13172 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))
13173 (match_operand:P 3 "gpc_reg_operand" "r,r")))]
13174 ""
13175 "@
13176 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13177 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13178 [(set_attr "type" "three")
13179 (set_attr "length" "12")])
13181 (define_insn ""
13182 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13183 (compare:CC
13184 (and:SI (neg:SI
13185 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13186 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13187 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13188 (const_int 0)))
13189 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13190 "TARGET_32BIT"
13191 "@
13192 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13193 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13194 #
13195 #"
13196 [(set_attr "type" "compare")
13197 (set_attr "length" "12,12,16,16")])
13199 (define_split
13200 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13201 (compare:CC
13202 (and:SI (neg:SI
13203 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13204 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13205 (match_operand:SI 3 "gpc_reg_operand" ""))
13206 (const_int 0)))
13207 (clobber (match_scratch:SI 4 ""))]
13208 "TARGET_32BIT && reload_completed"
13209 [(set (match_dup 4)
13210 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13211 (match_dup 3)))
13212 (set (match_dup 0)
13213 (compare:CC (match_dup 4)
13214 (const_int 0)))]
13215 "")
13217 (define_insn ""
13218 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13219 (compare:CC
13220 (and:SI (neg:SI
13221 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13222 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13223 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13224 (const_int 0)))
13225 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13226 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13227 "TARGET_32BIT"
13228 "@
13229 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13230 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13231 #
13232 #"
13233 [(set_attr "type" "compare")
13234 (set_attr "length" "12,12,16,16")])
13236 (define_split
13237 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13238 (compare:CC
13239 (and:SI (neg:SI
13240 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13241 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13242 (match_operand:SI 3 "gpc_reg_operand" ""))
13243 (const_int 0)))
13244 (set (match_operand:SI 0 "gpc_reg_operand" "")
13245 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13246 "TARGET_32BIT && reload_completed"
13247 [(set (match_dup 0)
13248 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13249 (set (match_dup 4)
13250 (compare:CC (match_dup 0)
13251 (const_int 0)))]
13252 "")
13254 (define_insn "*plus_gt0<mode>"
13255 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13256 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r")
13257 (const_int 0))
13258 (match_operand:P 2 "gpc_reg_operand" "r")))]
13259 ""
13260 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13261 [(set_attr "type" "three")
13262 (set_attr "length" "12")])
13264 (define_insn ""
13265 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13266 (compare:CC
13267 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13268 (const_int 0))
13269 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13270 (const_int 0)))
13271 (clobber (match_scratch:SI 3 "=&r,&r"))]
13272 "TARGET_32BIT"
13273 "@
13274 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13275 #"
13276 [(set_attr "type" "compare")
13277 (set_attr "length" "12,16")])
13279 (define_split
13280 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13281 (compare:CC
13282 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13283 (const_int 0))
13284 (match_operand:SI 2 "gpc_reg_operand" ""))
13285 (const_int 0)))
13286 (clobber (match_scratch:SI 3 ""))]
13287 "TARGET_32BIT && reload_completed"
13288 [(set (match_dup 3)
13289 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13290 (match_dup 2)))
13291 (set (match_dup 0)
13292 (compare:CC (match_dup 3)
13293 (const_int 0)))]
13294 "")
13296 (define_insn ""
13297 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13298 (compare:CC
13299 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13300 (const_int 0))
13301 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13302 (const_int 0)))
13303 (clobber (match_scratch:DI 3 "=&r,&r"))]
13304 "TARGET_64BIT"
13305 "@
13306 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13307 #"
13308 [(set_attr "type" "compare")
13309 (set_attr "length" "12,16")])
13311 (define_split
13312 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "")
13313 (compare:CC
13314 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13315 (const_int 0))
13316 (match_operand:DI 2 "gpc_reg_operand" ""))
13317 (const_int 0)))
13318 (clobber (match_scratch:DI 3 ""))]
13319 "TARGET_64BIT && reload_completed"
13320 [(set (match_dup 3)
13321 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13322 (match_dup 2)))
13323 (set (match_dup 0)
13324 (compare:CC (match_dup 3)
13325 (const_int 0)))]
13326 "")
13328 (define_insn ""
13329 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13330 (compare:CC
13331 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13332 (const_int 0))
13333 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13334 (const_int 0)))
13335 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13336 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13337 "TARGET_32BIT"
13338 "@
13339 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13340 #"
13341 [(set_attr "type" "compare")
13342 (set_attr "length" "12,16")])
13344 (define_split
13345 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13346 (compare:CC
13347 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13348 (const_int 0))
13349 (match_operand:SI 2 "gpc_reg_operand" ""))
13350 (const_int 0)))
13351 (set (match_operand:SI 0 "gpc_reg_operand" "")
13352 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13353 "TARGET_32BIT && reload_completed"
13354 [(set (match_dup 0)
13355 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13356 (set (match_dup 3)
13357 (compare:CC (match_dup 0)
13358 (const_int 0)))]
13359 "")
13361 (define_insn ""
13362 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13363 (compare:CC
13364 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13365 (const_int 0))
13366 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13367 (const_int 0)))
13368 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13369 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13370 "TARGET_64BIT"
13371 "@
13372 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13373 #"
13374 [(set_attr "type" "compare")
13375 (set_attr "length" "12,16")])
13377 (define_split
13378 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "")
13379 (compare:CC
13380 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13381 (const_int 0))
13382 (match_operand:DI 2 "gpc_reg_operand" ""))
13383 (const_int 0)))
13384 (set (match_operand:DI 0 "gpc_reg_operand" "")
13385 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13386 "TARGET_64BIT && reload_completed"
13387 [(set (match_dup 0)
13388 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13389 (set (match_dup 3)
13390 (compare:CC (match_dup 0)
13391 (const_int 0)))]
13392 "")
13394 (define_insn_and_split "*gtu<mode>"
13395 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13396 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13397 (match_operand:P 2 "reg_or_short_operand" "rI")))]
13398 ""
13399 "#"
13400 ""
13401 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13402 (set (match_dup 0) (neg:P (match_dup 0)))]
13403 "")
13405 (define_insn_and_split "*gtu<mode>_compare"
13406 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13407 (compare:CC
13408 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r")
13409 (match_operand:P 2 "reg_or_short_operand" "rI,rI"))
13410 (const_int 0)))
13411 (set (match_operand:P 0 "gpc_reg_operand" "=r,r")
13412 (gtu:P (match_dup 1) (match_dup 2)))]
13413 ""
13414 "#"
13415 ""
13416 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13417 (parallel [(set (match_dup 3)
13418 (compare:CC (neg:P (match_dup 0)) (const_int 0)))
13419 (set (match_dup 0) (neg:P (match_dup 0)))])]
13420 "")
13422 (define_insn_and_split "*plus_gtu<mode>"
13423 [(set (match_operand:P 0 "gpc_reg_operand" "=&r")
13424 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13425 (match_operand:P 2 "reg_or_short_operand" "rI"))
13426 (match_operand:P 3 "reg_or_short_operand" "rI")))]
13427 ""
13428 "#"
13429 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13430 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13431 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))]
13432 "")
13434 (define_insn_and_split "*plus_gtu<mode>_compare"
13435 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13436 (compare:CC
13437 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r")
13438 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r"))
13439 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r"))
13440 (const_int 0)))
13441 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13442 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))]
13443 ""
13444 "#"
13445 "&& !reg_overlap_mentioned_p (operands[0], operands[3])"
13446 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2))))
13447 (parallel [(set (match_dup 4)
13448 (compare:CC (minus:P (match_dup 3) (match_dup 0))
13449 (const_int 0)))
13450 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])]
13451 "")
13453 (define_insn "*neg_gtu<mode>"
13454 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
13455 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r")
13456 (match_operand:P 2 "reg_or_short_operand" "rI"))))]
13457 ""
13458 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13459 [(set_attr "type" "two")
13460 (set_attr "length" "8")])
13462 \f
13463 ;; Define both directions of branch and return. If we need a reload
13464 ;; register, we'd rather use CR0 since it is much easier to copy a
13465 ;; register CC value to there.
13467 (define_insn ""
13468 [(set (pc)
13469 (if_then_else (match_operator 1 "branch_comparison_operator"
13470 [(match_operand 2
13471 "cc_reg_operand" "y")
13472 (const_int 0)])
13473 (label_ref (match_operand 0 "" ""))
13474 (pc)))]
13475 ""
13476 "*
13477 {
13478 return output_cbranch (operands[1], \"%l0\", 0, insn);
13479 }"
13480 [(set_attr "type" "branch")])
13482 (define_insn ""
13483 [(set (pc)
13484 (if_then_else (match_operator 0 "branch_comparison_operator"
13485 [(match_operand 1
13486 "cc_reg_operand" "y")
13487 (const_int 0)])
13488 (any_return)
13489 (pc)))]
13490 "<return_pred>"
13491 "*
13492 {
13493 return output_cbranch (operands[0], NULL, 0, insn);
13494 }"
13495 [(set_attr "type" "jmpreg")
13496 (set_attr "length" "4")])
13498 (define_insn ""
13499 [(set (pc)
13500 (if_then_else (match_operator 1 "branch_comparison_operator"
13501 [(match_operand 2
13502 "cc_reg_operand" "y")
13503 (const_int 0)])
13504 (pc)
13505 (label_ref (match_operand 0 "" ""))))]
13506 ""
13507 "*
13508 {
13509 return output_cbranch (operands[1], \"%l0\", 1, insn);
13510 }"
13511 [(set_attr "type" "branch")])
13513 (define_insn ""
13514 [(set (pc)
13515 (if_then_else (match_operator 0 "branch_comparison_operator"
13516 [(match_operand 1
13517 "cc_reg_operand" "y")
13518 (const_int 0)])
13519 (pc)
13520 (any_return)))]
13521 "<return_pred>"
13522 "*
13523 {
13524 return output_cbranch (operands[0], NULL, 1, insn);
13525 }"
13526 [(set_attr "type" "jmpreg")
13527 (set_attr "length" "4")])
13529 ;; Logic on condition register values.
13531 ; This pattern matches things like
13532 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
13533 ; (eq:SI (reg:CCFP 68) (const_int 0)))
13534 ; (const_int 1)))
13535 ; which are generated by the branch logic.
13536 ; Prefer destructive operations where BT = BB (for crXX BT,BA,BB)
13538 (define_insn "*cceq_ior_compare"
13539 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13540 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
13541 [(match_operator:SI 2
13542 "branch_positive_comparison_operator"
13543 [(match_operand 3
13544 "cc_reg_operand" "y,y")
13545 (const_int 0)])
13546 (match_operator:SI 4
13547 "branch_positive_comparison_operator"
13548 [(match_operand 5
13549 "cc_reg_operand" "0,y")
13550 (const_int 0)])])
13551 (const_int 1)))]
13552 ""
13553 "cr%q1 %E0,%j2,%j4"
13554 [(set_attr "type" "cr_logical,delayed_cr")])
13556 ; Why is the constant -1 here, but 1 in the previous pattern?
13557 ; Because ~1 has all but the low bit set.
13558 (define_insn ""
13559 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13560 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
13561 [(not:SI (match_operator:SI 2
13562 "branch_positive_comparison_operator"
13563 [(match_operand 3
13564 "cc_reg_operand" "y,y")
13565 (const_int 0)]))
13566 (match_operator:SI 4
13567 "branch_positive_comparison_operator"
13568 [(match_operand 5
13569 "cc_reg_operand" "0,y")
13570 (const_int 0)])])
13571 (const_int -1)))]
13572 ""
13573 "cr%q1 %E0,%j2,%j4"
13574 [(set_attr "type" "cr_logical,delayed_cr")])
13576 (define_insn "*cceq_rev_compare"
13577 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y")
13578 (compare:CCEQ (match_operator:SI 1
13579 "branch_positive_comparison_operator"
13580 [(match_operand 2
13581 "cc_reg_operand" "0,y")
13582 (const_int 0)])
13583 (const_int 0)))]
13584 ""
13585 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
13586 [(set_attr "type" "cr_logical,delayed_cr")])
13588 ;; If we are comparing the result of two comparisons, this can be done
13589 ;; using creqv or crxor.
13591 (define_insn_and_split ""
13592 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
13593 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
13594 [(match_operand 2 "cc_reg_operand" "y")
13595 (const_int 0)])
13596 (match_operator 3 "branch_comparison_operator"
13597 [(match_operand 4 "cc_reg_operand" "y")
13598 (const_int 0)])))]
13599 ""
13600 "#"
13601 ""
13602 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
13603 (match_dup 5)))]
13604 "
13605 {
13606 int positive_1, positive_2;
13608 positive_1 = branch_positive_comparison_operator (operands[1],
13609 GET_MODE (operands[1]));
13610 positive_2 = branch_positive_comparison_operator (operands[3],
13611 GET_MODE (operands[3]));
13613 if (! positive_1)
13614 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]),
13615 GET_CODE (operands[1])),
13616 SImode,
13617 operands[2], const0_rtx);
13618 else if (GET_MODE (operands[1]) != SImode)
13619 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode,
13620 operands[2], const0_rtx);
13622 if (! positive_2)
13623 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]),
13624 GET_CODE (operands[3])),
13625 SImode,
13626 operands[4], const0_rtx);
13627 else if (GET_MODE (operands[3]) != SImode)
13628 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode,
13629 operands[4], const0_rtx);
13631 if (positive_1 == positive_2)
13632 {
13633 operands[1] = gen_rtx_NOT (SImode, operands[1]);
13634 operands[5] = constm1_rtx;
13635 }
13636 else
13637 {
13638 operands[5] = const1_rtx;
13639 }
13640 }")
13642 ;; Unconditional branch and return.
13644 (define_insn "jump"
13645 [(set (pc)
13646 (label_ref (match_operand 0 "" "")))]
13647 ""
13648 "b %l0"
13649 [(set_attr "type" "branch")])
13651 (define_insn "<return_str>return"
13652 [(any_return)]
13653 "<return_pred>"
13654 "{br|blr}"
13655 [(set_attr "type" "jmpreg")])
13657 (define_expand "indirect_jump"
13658 [(set (pc) (match_operand 0 "register_operand" ""))])
13660 (define_insn "*indirect_jump<mode>"
13661 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))]
13662 ""
13663 "@
13664 bctr
13665 {br|blr}"
13666 [(set_attr "type" "jmpreg")])
13668 ;; Table jump for switch statements:
13669 (define_expand "tablejump"
13670 [(use (match_operand 0 "" ""))
13671 (use (label_ref (match_operand 1 "" "")))]
13672 ""
13673 "
13674 {
13675 if (TARGET_32BIT)
13676 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
13677 else
13678 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
13679 DONE;
13680 }")
13682 (define_expand "tablejumpsi"
13683 [(set (match_dup 3)
13684 (plus:SI (match_operand:SI 0 "" "")
13685 (match_dup 2)))
13686 (parallel [(set (pc) (match_dup 3))
13687 (use (label_ref (match_operand 1 "" "")))])]
13688 "TARGET_32BIT"
13689 "
13690 { operands[0] = force_reg (SImode, operands[0]);
13691 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
13692 operands[3] = gen_reg_rtx (SImode);
13693 }")
13695 (define_expand "tablejumpdi"
13696 [(set (match_dup 4)
13697 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "")))
13698 (set (match_dup 3)
13699 (plus:DI (match_dup 4)
13700 (match_dup 2)))
13701 (parallel [(set (pc) (match_dup 3))
13702 (use (label_ref (match_operand 1 "" "")))])]
13703 "TARGET_64BIT"
13704 "
13705 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
13706 operands[3] = gen_reg_rtx (DImode);
13707 operands[4] = gen_reg_rtx (DImode);
13708 }")
13710 (define_insn "*tablejump<mode>_internal1"
13711 [(set (pc)
13712 (match_operand:P 0 "register_operand" "c,*l"))
13713 (use (label_ref (match_operand 1 "" "")))]
13714 ""
13715 "@
13716 bctr
13717 {br|blr}"
13718 [(set_attr "type" "jmpreg")])
13720 (define_insn "nop"
13721 [(const_int 0)]
13722 ""
13723 "{cror 0,0,0|nop}")
13725 (define_insn "group_ending_nop"
13726 [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)]
13727 ""
13728 "*
13729 {
13730 if (rs6000_cpu_attr == CPU_POWER6)
13731 return \"ori 1,1,0\";
13732 return \"ori 2,2,0\";
13733 }")
13734 \f
13735 ;; Define the subtract-one-and-jump insns, starting with the template
13736 ;; so loop.c knows what to generate.
13738 (define_expand "doloop_end"
13739 [(use (match_operand 0 "" "")) ; loop pseudo
13740 (use (match_operand 1 "" "")) ; iterations; zero if unknown
13741 (use (match_operand 2 "" "")) ; max iterations
13742 (use (match_operand 3 "" "")) ; loop level
13743 (use (match_operand 4 "" ""))] ; label
13744 ""
13745 "
13746 {
13747 /* Only use this on innermost loops. */
13748 if (INTVAL (operands[3]) > 1)
13749 FAIL;
13750 if (TARGET_64BIT)
13751 {
13752 if (GET_MODE (operands[0]) != DImode)
13753 FAIL;
13754 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
13755 }
13756 else
13757 {
13758 if (GET_MODE (operands[0]) != SImode)
13759 FAIL;
13760 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
13761 }
13762 DONE;
13763 }")
13765 (define_expand "ctr<mode>"
13766 [(parallel [(set (pc)
13767 (if_then_else (ne (match_operand:P 0 "register_operand" "")
13768 (const_int 1))
13769 (label_ref (match_operand 1 "" ""))
13770 (pc)))
13771 (set (match_dup 0)
13772 (plus:P (match_dup 0)
13773 (const_int -1)))
13774 (clobber (match_scratch:CC 2 ""))
13775 (clobber (match_scratch:P 3 ""))])]
13776 ""
13777 "")
13779 ;; We need to be able to do this for any operand, including MEM, or we
13780 ;; will cause reload to blow up since we don't allow output reloads on
13781 ;; JUMP_INSNs.
13782 ;; For the length attribute to be calculated correctly, the
13783 ;; label MUST be operand 0.
13785 (define_insn "*ctr<mode>_internal1"
13786 [(set (pc)
13787 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13788 (const_int 1))
13789 (label_ref (match_operand 0 "" ""))
13790 (pc)))
13791 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13792 (plus:P (match_dup 1)
13793 (const_int -1)))
13794 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13795 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13796 ""
13797 "*
13798 {
13799 if (which_alternative != 0)
13800 return \"#\";
13801 else if (get_attr_length (insn) == 4)
13802 return \"{bdn|bdnz} %l0\";
13803 else
13804 return \"bdz $+8\;b %l0\";
13805 }"
13806 [(set_attr "type" "branch")
13807 (set_attr "length" "*,12,16,16")])
13809 (define_insn "*ctr<mode>_internal2"
13810 [(set (pc)
13811 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13812 (const_int 1))
13813 (pc)
13814 (label_ref (match_operand 0 "" ""))))
13815 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13816 (plus:P (match_dup 1)
13817 (const_int -1)))
13818 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13819 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13820 ""
13821 "*
13822 {
13823 if (which_alternative != 0)
13824 return \"#\";
13825 else if (get_attr_length (insn) == 4)
13826 return \"bdz %l0\";
13827 else
13828 return \"{bdn|bdnz} $+8\;b %l0\";
13829 }"
13830 [(set_attr "type" "branch")
13831 (set_attr "length" "*,12,16,16")])
13833 ;; Similar but use EQ
13835 (define_insn "*ctr<mode>_internal5"
13836 [(set (pc)
13837 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13838 (const_int 1))
13839 (label_ref (match_operand 0 "" ""))
13840 (pc)))
13841 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13842 (plus:P (match_dup 1)
13843 (const_int -1)))
13844 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13845 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13846 ""
13847 "*
13848 {
13849 if (which_alternative != 0)
13850 return \"#\";
13851 else if (get_attr_length (insn) == 4)
13852 return \"bdz %l0\";
13853 else
13854 return \"{bdn|bdnz} $+8\;b %l0\";
13855 }"
13856 [(set_attr "type" "branch")
13857 (set_attr "length" "*,12,16,16")])
13859 (define_insn "*ctr<mode>_internal6"
13860 [(set (pc)
13861 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r")
13862 (const_int 1))
13863 (pc)
13864 (label_ref (match_operand 0 "" ""))))
13865 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*q*c*l")
13866 (plus:P (match_dup 1)
13867 (const_int -1)))
13868 (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
13869 (clobber (match_scratch:P 4 "=X,X,&r,r"))]
13870 ""
13871 "*
13872 {
13873 if (which_alternative != 0)
13874 return \"#\";
13875 else if (get_attr_length (insn) == 4)
13876 return \"{bdn|bdnz} %l0\";
13877 else
13878 return \"bdz $+8\;b %l0\";
13879 }"
13880 [(set_attr "type" "branch")
13881 (set_attr "length" "*,12,16,16")])
13883 ;; Now the splitters if we could not allocate the CTR register
13885 (define_split
13886 [(set (pc)
13887 (if_then_else (match_operator 2 "comparison_operator"
13888 [(match_operand:P 1 "gpc_reg_operand" "")
13889 (const_int 1)])
13890 (match_operand 5 "" "")
13891 (match_operand 6 "" "")))
13892 (set (match_operand:P 0 "gpc_reg_operand" "")
13893 (plus:P (match_dup 1) (const_int -1)))
13894 (clobber (match_scratch:CC 3 ""))
13895 (clobber (match_scratch:P 4 ""))]
13896 "reload_completed"
13897 [(parallel [(set (match_dup 3)
13898 (compare:CC (plus:P (match_dup 1)
13899 (const_int -1))
13900 (const_int 0)))
13901 (set (match_dup 0)
13902 (plus:P (match_dup 1)
13903 (const_int -1)))])
13904 (set (pc) (if_then_else (match_dup 7)
13905 (match_dup 5)
13906 (match_dup 6)))]
13907 "
13908 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13909 operands[3], const0_rtx); }")
13911 (define_split
13912 [(set (pc)
13913 (if_then_else (match_operator 2 "comparison_operator"
13914 [(match_operand:P 1 "gpc_reg_operand" "")
13915 (const_int 1)])
13916 (match_operand 5 "" "")
13917 (match_operand 6 "" "")))
13918 (set (match_operand:P 0 "nonimmediate_operand" "")
13919 (plus:P (match_dup 1) (const_int -1)))
13920 (clobber (match_scratch:CC 3 ""))
13921 (clobber (match_scratch:P 4 ""))]
13922 "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
13923 [(parallel [(set (match_dup 3)
13924 (compare:CC (plus:P (match_dup 1)
13925 (const_int -1))
13926 (const_int 0)))
13927 (set (match_dup 4)
13928 (plus:P (match_dup 1)
13929 (const_int -1)))])
13930 (set (match_dup 0)
13931 (match_dup 4))
13932 (set (pc) (if_then_else (match_dup 7)
13933 (match_dup 5)
13934 (match_dup 6)))]
13935 "
13936 { operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode,
13937 operands[3], const0_rtx); }")
13938 \f
13939 (define_insn "trap"
13940 [(trap_if (const_int 1) (const_int 0))]
13941 ""
13942 "{t 31,0,0|trap}"
13943 [(set_attr "type" "trap")])
13945 (define_expand "ctrap<mode>4"
13946 [(trap_if (match_operator 0 "ordered_comparison_operator"
13947 [(match_operand:GPR 1 "register_operand")
13948 (match_operand:GPR 2 "reg_or_short_operand")])
13949 (match_operand 3 "zero_constant" ""))]
13950 ""
13951 "")
13953 (define_insn ""
13954 [(trap_if (match_operator 0 "ordered_comparison_operator"
13955 [(match_operand:GPR 1 "register_operand" "r")
13956 (match_operand:GPR 2 "reg_or_short_operand" "rI")])
13957 (const_int 0))]
13958 ""
13959 "{t|t<wd>}%V0%I2 %1,%2"
13960 [(set_attr "type" "trap")])
13961 \f
13962 ;; Insns related to generating the function prologue and epilogue.
13964 (define_expand "prologue"
13965 [(use (const_int 0))]
13966 ""
13967 {
13968 rs6000_emit_prologue ();
13969 if (!TARGET_SCHED_PROLOG)
13970 emit_insn (gen_blockage ());
13971 DONE;
13972 })
13974 (define_insn "*movesi_from_cr_one"
13975 [(match_parallel 0 "mfcr_operation"
13976 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
13977 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y")
13978 (match_operand 3 "immediate_operand" "n")]
13979 UNSPEC_MOVESI_FROM_CR))])]
13980 "TARGET_MFCRF"
13981 "*
13982 {
13983 int mask = 0;
13984 int i;
13985 for (i = 0; i < XVECLEN (operands[0], 0); i++)
13986 {
13987 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
13988 operands[4] = GEN_INT (mask);
13989 output_asm_insn (\"mfcr %1,%4\", operands);
13990 }
13991 return \"\";
13992 }"
13993 [(set_attr "type" "mfcrf")])
13995 (define_insn "movesi_from_cr"
13996 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13997 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO)
13998 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO)
13999 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO)
14000 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)]
14001 UNSPEC_MOVESI_FROM_CR))]
14002 ""
14003 "mfcr %0"
14004 [(set_attr "type" "mfcr")])
14006 (define_insn "*stmw"
14007 [(match_parallel 0 "stmw_operation"
14008 [(set (match_operand:SI 1 "memory_operand" "=m")
14009 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14010 "TARGET_MULTIPLE"
14011 "{stm|stmw} %2,%1"
14012 [(set_attr "type" "store_ux")])
14014 ; The following comment applies to:
14015 ; save_gpregs_*
14016 ; save_fpregs_*
14017 ; restore_gpregs*
14018 ; return_and_restore_gpregs*
14019 ; return_and_restore_fpregs*
14020 ; return_and_restore_fpregs_aix*
14021 ;
14022 ; The out-of-line save / restore functions expects one input argument.
14023 ; Since those are not standard call_insn's, we must avoid using
14024 ; MATCH_OPERAND for that argument. That way the register rename
14025 ; optimization will not try to rename this register.
14026 ; Each pattern is repeated for each possible register number used in
14027 ; various ABIs (r11, r1, and for some functions r12)
14029 (define_insn "*save_gpregs_<mode>_r11"
14030 [(match_parallel 0 "any_parallel_operand"
14031 [(clobber (reg:P 65))
14032 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14033 (use (reg:P 11))
14034 (set (match_operand:P 2 "memory_operand" "=m")
14035 (match_operand:P 3 "gpc_reg_operand" "r"))])]
14036 ""
14037 "bl %1"
14038 [(set_attr "type" "branch")
14039 (set_attr "length" "4")])
14041 (define_insn "*save_gpregs_<mode>_r12"
14042 [(match_parallel 0 "any_parallel_operand"
14043 [(clobber (reg:P 65))
14044 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14045 (use (reg:P 12))
14046 (set (match_operand:P 2 "memory_operand" "=m")
14047 (match_operand:P 3 "gpc_reg_operand" "r"))])]
14048 ""
14049 "bl %1"
14050 [(set_attr "type" "branch")
14051 (set_attr "length" "4")])
14053 (define_insn "*save_gpregs_<mode>_r1"
14054 [(match_parallel 0 "any_parallel_operand"
14055 [(clobber (reg:P 65))
14056 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14057 (use (reg:P 1))
14058 (set (match_operand:P 2 "memory_operand" "=m")
14059 (match_operand:P 3 "gpc_reg_operand" "r"))])]
14060 ""
14061 "bl %1"
14062 [(set_attr "type" "branch")
14063 (set_attr "length" "4")])
14065 (define_insn "*save_fpregs_<mode>_r11"
14066 [(match_parallel 0 "any_parallel_operand"
14067 [(clobber (reg:P 65))
14068 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14069 (use (reg:P 11))
14070 (set (match_operand:DF 2 "memory_operand" "=m")
14071 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
14072 ""
14073 "bl %1"
14074 [(set_attr "type" "branch")
14075 (set_attr "length" "4")])
14077 (define_insn "*save_fpregs_<mode>_r12"
14078 [(match_parallel 0 "any_parallel_operand"
14079 [(clobber (reg:P 65))
14080 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14081 (use (reg:P 12))
14082 (set (match_operand:DF 2 "memory_operand" "=m")
14083 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
14084 ""
14085 "bl %1"
14086 [(set_attr "type" "branch")
14087 (set_attr "length" "4")])
14089 (define_insn "*save_fpregs_<mode>_r1"
14090 [(match_parallel 0 "any_parallel_operand"
14091 [(clobber (reg:P 65))
14092 (use (match_operand:P 1 "symbol_ref_operand" "s"))
14093 (use (reg:P 1))
14094 (set (match_operand:DF 2 "memory_operand" "=m")
14095 (match_operand:DF 3 "gpc_reg_operand" "d"))])]
14096 ""
14097 "bl %1"
14098 [(set_attr "type" "branch")
14099 (set_attr "length" "4")])
14101 ; This is to explain that changes to the stack pointer should
14102 ; not be moved over loads from or stores to stack memory.
14103 (define_insn "stack_tie"
14104 [(match_parallel 0 "tie_operand"
14105 [(set (mem:BLK (reg 1)) (const_int 0))])]
14106 ""
14107 ""
14108 [(set_attr "length" "0")])
14110 (define_expand "epilogue"
14111 [(use (const_int 0))]
14112 ""
14113 {
14114 if (!TARGET_SCHED_PROLOG)
14115 emit_insn (gen_blockage ());
14116 rs6000_emit_epilogue (FALSE);
14117 DONE;
14118 })
14120 ; On some processors, doing the mtcrf one CC register at a time is
14121 ; faster (like on the 604e). On others, doing them all at once is
14122 ; faster; for instance, on the 601 and 750.
14124 (define_expand "movsi_to_cr_one"
14125 [(set (match_operand:CC 0 "cc_reg_operand" "")
14126 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "")
14127 (match_dup 2)] UNSPEC_MOVESI_TO_CR))]
14128 ""
14129 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14131 (define_insn "*movsi_to_cr"
14132 [(match_parallel 0 "mtcrf_operation"
14133 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14134 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14135 (match_operand 3 "immediate_operand" "n")]
14136 UNSPEC_MOVESI_TO_CR))])]
14137 ""
14138 "*
14139 {
14140 int mask = 0;
14141 int i;
14142 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14143 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14144 operands[4] = GEN_INT (mask);
14145 return \"mtcrf %4,%2\";
14146 }"
14147 [(set_attr "type" "mtcr")])
14149 (define_insn "*mtcrfsi"
14150 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14151 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14152 (match_operand 2 "immediate_operand" "n")]
14153 UNSPEC_MOVESI_TO_CR))]
14154 "GET_CODE (operands[0]) == REG
14155 && CR_REGNO_P (REGNO (operands[0]))
14156 && GET_CODE (operands[2]) == CONST_INT
14157 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14158 "mtcrf %R0,%1"
14159 [(set_attr "type" "mtcr")])
14161 ; The load-multiple instructions have similar properties.
14162 ; Note that "load_multiple" is a name known to the machine-independent
14163 ; code that actually corresponds to the PowerPC load-string.
14165 (define_insn "*lmw"
14166 [(match_parallel 0 "lmw_operation"
14167 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14168 (match_operand:SI 2 "memory_operand" "m"))])]
14169 "TARGET_MULTIPLE"
14170 "{lm|lmw} %1,%2"
14171 [(set_attr "type" "load_ux")
14172 (set_attr "cell_micro" "always")])
14174 (define_insn "*return_internal_<mode>"
14175 [(simple_return)
14176 (use (match_operand:P 0 "register_operand" "lc"))]
14177 ""
14178 "b%T0"
14179 [(set_attr "type" "jmpreg")])
14181 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14182 ; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible...
14184 ; The following comment applies to:
14185 ; save_gpregs_*
14186 ; save_fpregs_*
14187 ; restore_gpregs*
14188 ; return_and_restore_gpregs*
14189 ; return_and_restore_fpregs*
14190 ; return_and_restore_fpregs_aix*
14191 ;
14192 ; The out-of-line save / restore functions expects one input argument.
14193 ; Since those are not standard call_insn's, we must avoid using
14194 ; MATCH_OPERAND for that argument. That way the register rename
14195 ; optimization will not try to rename this register.
14196 ; Each pattern is repeated for each possible register number used in
14197 ; various ABIs (r11, r1, and for some functions r12)
14199 (define_insn "*restore_gpregs_<mode>_r11"
14200 [(match_parallel 0 "any_parallel_operand"
14201 [(clobber (match_operand:P 1 "register_operand" "=l"))
14202 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14203 (use (reg:P 11))
14204 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14205 (match_operand:P 4 "memory_operand" "m"))])]
14206 ""
14207 "bl %2"
14208 [(set_attr "type" "branch")
14209 (set_attr "length" "4")])
14211 (define_insn "*restore_gpregs_<mode>_r12"
14212 [(match_parallel 0 "any_parallel_operand"
14213 [(clobber (match_operand:P 1 "register_operand" "=l"))
14214 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14215 (use (reg:P 12))
14216 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14217 (match_operand:P 4 "memory_operand" "m"))])]
14218 ""
14219 "bl %2"
14220 [(set_attr "type" "branch")
14221 (set_attr "length" "4")])
14223 (define_insn "*restore_gpregs_<mode>_r1"
14224 [(match_parallel 0 "any_parallel_operand"
14225 [(clobber (match_operand:P 1 "register_operand" "=l"))
14226 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14227 (use (reg:P 1))
14228 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14229 (match_operand:P 4 "memory_operand" "m"))])]
14230 ""
14231 "bl %2"
14232 [(set_attr "type" "branch")
14233 (set_attr "length" "4")])
14235 (define_insn "*return_and_restore_gpregs_<mode>_r11"
14236 [(match_parallel 0 "any_parallel_operand"
14237 [(return)
14238 (clobber (match_operand:P 1 "register_operand" "=l"))
14239 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14240 (use (reg:P 11))
14241 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14242 (match_operand:P 4 "memory_operand" "m"))])]
14243 ""
14244 "b %2"
14245 [(set_attr "type" "branch")
14246 (set_attr "length" "4")])
14248 (define_insn "*return_and_restore_gpregs_<mode>_r12"
14249 [(match_parallel 0 "any_parallel_operand"
14250 [(return)
14251 (clobber (match_operand:P 1 "register_operand" "=l"))
14252 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14253 (use (reg:P 12))
14254 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14255 (match_operand:P 4 "memory_operand" "m"))])]
14256 ""
14257 "b %2"
14258 [(set_attr "type" "branch")
14259 (set_attr "length" "4")])
14261 (define_insn "*return_and_restore_gpregs_<mode>_r1"
14262 [(match_parallel 0 "any_parallel_operand"
14263 [(return)
14264 (clobber (match_operand:P 1 "register_operand" "=l"))
14265 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14266 (use (reg:P 1))
14267 (set (match_operand:P 3 "gpc_reg_operand" "=r")
14268 (match_operand:P 4 "memory_operand" "m"))])]
14269 ""
14270 "b %2"
14271 [(set_attr "type" "branch")
14272 (set_attr "length" "4")])
14274 (define_insn "*return_and_restore_fpregs_<mode>_r11"
14275 [(match_parallel 0 "any_parallel_operand"
14276 [(return)
14277 (clobber (match_operand:P 1 "register_operand" "=l"))
14278 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14279 (use (reg:P 11))
14280 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14281 (match_operand:DF 4 "memory_operand" "m"))])]
14282 ""
14283 "b %2"
14284 [(set_attr "type" "branch")
14285 (set_attr "length" "4")])
14287 (define_insn "*return_and_restore_fpregs_<mode>_r12"
14288 [(match_parallel 0 "any_parallel_operand"
14289 [(return)
14290 (clobber (match_operand:P 1 "register_operand" "=l"))
14291 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14292 (use (reg:P 12))
14293 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14294 (match_operand:DF 4 "memory_operand" "m"))])]
14295 ""
14296 "b %2"
14297 [(set_attr "type" "branch")
14298 (set_attr "length" "4")])
14300 (define_insn "*return_and_restore_fpregs_<mode>_r1"
14301 [(match_parallel 0 "any_parallel_operand"
14302 [(return)
14303 (clobber (match_operand:P 1 "register_operand" "=l"))
14304 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14305 (use (reg:P 1))
14306 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14307 (match_operand:DF 4 "memory_operand" "m"))])]
14308 ""
14309 "b %2"
14310 [(set_attr "type" "branch")
14311 (set_attr "length" "4")])
14313 (define_insn "*return_and_restore_fpregs_aix_<mode>_r11"
14314 [(match_parallel 0 "any_parallel_operand"
14315 [(return)
14316 (use (match_operand:P 1 "register_operand" "l"))
14317 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14318 (use (reg:P 11))
14319 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14320 (match_operand:DF 4 "memory_operand" "m"))])]
14321 ""
14322 "b %2"
14323 [(set_attr "type" "branch")
14324 (set_attr "length" "4")])
14326 (define_insn "*return_and_restore_fpregs_aix_<mode>_r1"
14327 [(match_parallel 0 "any_parallel_operand"
14328 [(return)
14329 (use (match_operand:P 1 "register_operand" "l"))
14330 (use (match_operand:P 2 "symbol_ref_operand" "s"))
14331 (use (reg:P 1))
14332 (set (match_operand:DF 3 "gpc_reg_operand" "=d")
14333 (match_operand:DF 4 "memory_operand" "m"))])]
14334 ""
14335 "b %2"
14336 [(set_attr "type" "branch")
14337 (set_attr "length" "4")])
14339 ; This is used in compiling the unwind routines.
14340 (define_expand "eh_return"
14341 [(use (match_operand 0 "general_operand" ""))]
14342 ""
14343 "
14344 {
14345 if (TARGET_32BIT)
14346 emit_insn (gen_eh_set_lr_si (operands[0]));
14347 else
14348 emit_insn (gen_eh_set_lr_di (operands[0]));
14349 DONE;
14350 }")
14352 ; We can't expand this before we know where the link register is stored.
14353 (define_insn "eh_set_lr_<mode>"
14354 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
14355 UNSPECV_EH_RR)
14356 (clobber (match_scratch:P 1 "=&b"))]
14357 ""
14358 "#")
14360 (define_split
14361 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR)
14362 (clobber (match_scratch 1 ""))]
14363 "reload_completed"
14364 [(const_int 0)]
14365 "
14366 {
14367 rs6000_emit_eh_reg_restore (operands[0], operands[1]);
14368 DONE;
14369 }")
14371 (define_insn "prefetch"
14372 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a")
14373 (match_operand:SI 1 "const_int_operand" "n")
14374 (match_operand:SI 2 "const_int_operand" "n"))]
14375 "TARGET_POWERPC"
14376 "*
14377 {
14378 if (GET_CODE (operands[0]) == REG)
14379 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14380 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14381 }"
14382 [(set_attr "type" "load")])
14383 \f
14384 (define_insn "bpermd_<mode>"
14385 [(set (match_operand:P 0 "gpc_reg_operand" "=r")
14386 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r")
14387 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))]
14388 "TARGET_POPCNTD"
14389 "bpermd %0,%1,%2"
14390 [(set_attr "type" "integer")])
14392 \f
14393 ;; Builtin fma support. Handle
14394 ;; Note that the conditions for expansion are in the FMA_F iterator.
14396 (define_expand "fma<mode>4"
14397 [(set (match_operand:FMA_F 0 "register_operand" "")
14398 (fma:FMA_F
14399 (match_operand:FMA_F 1 "register_operand" "")
14400 (match_operand:FMA_F 2 "register_operand" "")
14401 (match_operand:FMA_F 3 "register_operand" "")))]
14402 ""
14403 "")
14405 ; Altivec only has fma and nfms.
14406 (define_expand "fms<mode>4"
14407 [(set (match_operand:FMA_F 0 "register_operand" "")
14408 (fma:FMA_F
14409 (match_operand:FMA_F 1 "register_operand" "")
14410 (match_operand:FMA_F 2 "register_operand" "")
14411 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))]
14412 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14413 "")
14415 ;; If signed zeros are ignored, -(a * b - c) = -a * b + c.
14416 (define_expand "fnma<mode>4"
14417 [(set (match_operand:FMA_F 0 "register_operand" "")
14418 (neg:FMA_F
14419 (fma:FMA_F
14420 (match_operand:FMA_F 1 "register_operand" "")
14421 (match_operand:FMA_F 2 "register_operand" "")
14422 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
14423 "!HONOR_SIGNED_ZEROS (<MODE>mode)"
14424 "")
14426 ;; If signed zeros are ignored, -(a * b + c) = -a * b - c.
14427 (define_expand "fnms<mode>4"
14428 [(set (match_operand:FMA_F 0 "register_operand" "")
14429 (neg:FMA_F
14430 (fma:FMA_F
14431 (match_operand:FMA_F 1 "register_operand" "")
14432 (match_operand:FMA_F 2 "register_operand" "")
14433 (match_operand:FMA_F 3 "register_operand" ""))))]
14434 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14435 "")
14437 ; Not an official optab name, but used from builtins.
14438 (define_expand "nfma<mode>4"
14439 [(set (match_operand:FMA_F 0 "register_operand" "")
14440 (neg:FMA_F
14441 (fma:FMA_F
14442 (match_operand:FMA_F 1 "register_operand" "")
14443 (match_operand:FMA_F 2 "register_operand" "")
14444 (match_operand:FMA_F 3 "register_operand" ""))))]
14445 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)"
14446 "")
14448 ; Not an official optab name, but used from builtins.
14449 (define_expand "nfms<mode>4"
14450 [(set (match_operand:FMA_F 0 "register_operand" "")
14451 (neg:FMA_F
14452 (fma:FMA_F
14453 (match_operand:FMA_F 1 "register_operand" "")
14454 (match_operand:FMA_F 2 "register_operand" "")
14455 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))]
14456 ""
14457 "")
14459 \f
14461 (include "sync.md")
14462 (include "vector.md")
14463 (include "vsx.md")
14464 (include "altivec.md")
14465 (include "spe.md")
14466 (include "dfp.md")
14467 (include "paired.md")