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33 File: gcc.info, Node: Output Template, Next: Output Statement, Prev: RTL Template, Up: Machine Desc
35 Output Templates and Operand Substitution
36 =========================================
38 The "output template" is a string which specifies how to output the
39 assembler code for an instruction pattern. Most of the template is a
40 fixed string which is output literally. The character `%' is used to
41 specify where to substitute an operand; it can also be used to identify
42 places where different variants of the assembler require different
45 In the simplest case, a `%' followed by a digit N says to output
46 operand N at that point in the string.
48 `%' followed by a letter and a digit says to output an operand in an
49 alternate fashion. Four letters have standard, built-in meanings
50 described below. The machine description macro `PRINT_OPERAND' can
51 define additional letters with nonstandard meanings.
53 `%cDIGIT' can be used to substitute an operand that is a constant
54 value without the syntax that normally indicates an immediate operand.
56 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is
57 negated before printing.
59 `%aDIGIT' can be used to substitute an operand as if it were a
60 memory reference, with the actual operand treated as the address. This
61 may be useful when outputting a "load address" instruction, because
62 often the assembler syntax for such an instruction requires you to
63 write the operand as if it were a memory reference.
65 `%lDIGIT' is used to substitute a `label_ref' into a jump
68 `%=' outputs a number which is unique to each instruction in the
69 entire compilation. This is useful for making local labels to be
70 referred to more than once in a single template that generates multiple
71 assembler instructions.
73 `%' followed by a punctuation character specifies a substitution that
74 does not use an operand. Only one case is standard: `%%' outputs a `%'
75 into the assembler code. Other nonstandard cases can be defined in the
76 `PRINT_OPERAND' macro. You must also define which punctuation
77 characters are valid with the `PRINT_OPERAND_PUNCT_VALID_P' macro.
79 The template may generate multiple assembler instructions. Write
80 the text for the instructions, with `\;' between them.
82 When the RTL contains two operands which are required by constraint
83 to match each other, the output template must refer only to the
84 lower-numbered operand. Matching operands are not always identical,
85 and the rest of the compiler arranges to put the proper RTL expression
86 for printing into the lower-numbered operand.
88 One use of nonstandard letters or punctuation following `%' is to
89 distinguish between different assembler languages for the same machine;
90 for example, Motorola syntax versus MIT syntax for the 68000. Motorola
91 syntax requires periods in most opcode names, while MIT syntax does
92 not. For example, the opcode `movel' in MIT syntax is `move.l' in
93 Motorola syntax. The same file of patterns is used for both kinds of
94 output syntax, but the character sequence `%.' is used in each place
95 where Motorola syntax wants a period. The `PRINT_OPERAND' macro for
96 Motorola syntax defines the sequence to output a period; the macro for
97 MIT syntax defines it to do nothing.
99 As a special case, a template consisting of the single character `#'
100 instructs the compiler to first split the insn, and then output the
101 resulting instructions separately. This helps eliminate redundancy in
102 the output templates. If you have a `define_insn' that needs to emit
103 multiple assembler instructions, and there is an matching `define_split'
104 already defined, then you can simply use `#' as the output template
105 instead of writing an output template that emits the multiple assembler
108 If the macro `ASSEMBLER_DIALECT' is defined, you can use construct
109 of the form `{option0|option1|option2}' in the templates. These
110 describe multiple variants of assembler language syntax. *Note
111 Instruction Output::.
114 File: gcc.info, Node: Output Statement, Next: Constraints, Prev: Output Template, Up: Machine Desc
116 C Statements for Assembler Output
117 =================================
119 Often a single fixed template string cannot produce correct and
120 efficient assembler code for all the cases that are recognized by a
121 single instruction pattern. For example, the opcodes may depend on the
122 kinds of operands; or some unfortunate combinations of operands may
123 require extra machine instructions.
125 If the output control string starts with a `@', then it is actually
126 a series of templates, each on a separate line. (Blank lines and
127 leading spaces and tabs are ignored.) The templates correspond to the
128 pattern's constraint alternatives (*note Multi-Alternative::.). For
129 example, if a target machine has a two-address add instruction `addr'
130 to add into a register and another `addm' to add a register to memory,
131 you might write this pattern:
133 (define_insn "addsi3"
134 [(set (match_operand:SI 0 "general_operand" "=r,m")
135 (plus:SI (match_operand:SI 1 "general_operand" "0,0")
136 (match_operand:SI 2 "general_operand" "g,r")))]
142 If the output control string starts with a `*', then it is not an
143 output template but rather a piece of C program that should compute a
144 template. It should execute a `return' statement to return the
145 template-string you want. Most such templates use C string literals,
146 which require doublequote characters to delimit them. To include these
147 doublequote characters in the string, prefix each one with `\'.
149 The operands may be found in the array `operands', whose C data type
152 It is very common to select different ways of generating assembler
153 code based on whether an immediate operand is within a certain range.
154 Be careful when doing this, because the result of `INTVAL' is an
155 integer on the host machine. If the host machine has more bits in an
156 `int' than the target machine has in the mode in which the constant
157 will be used, then some of the bits you get from `INTVAL' will be
158 superfluous. For proper results, you must carefully disregard the
159 values of those bits.
161 It is possible to output an assembler instruction and then go on to
162 output or compute more of them, using the subroutine `output_asm_insn'.
163 This receives two arguments: a template-string and a vector of
164 operands. The vector may be `operands', or it may be another array of
165 `rtx' that you declare locally and initialize yourself.
167 When an insn pattern has multiple alternatives in its constraints,
168 often the appearance of the assembler code is determined mostly by
169 which alternative was matched. When this is so, the C code can test
170 the variable `which_alternative', which is the ordinal number of the
171 alternative that was actually satisfied (0 for the first, 1 for the
172 second alternative, etc.).
174 For example, suppose there are two opcodes for storing zero, `clrreg'
175 for registers and `clrmem' for memory locations. Here is how a pattern
176 could use `which_alternative' to choose between them:
179 [(set (match_operand:SI 0 "general_operand" "=r,m")
183 return (which_alternative == 0
184 ? \"clrreg %0\" : \"clrmem %0\");
187 The example above, where the assembler code to generate was *solely*
188 determined by the alternative, could also have been specified as
189 follows, having the output control string start with a `@':
192 [(set (match_operand:SI 0 "general_operand" "=r,m")
200 File: gcc.info, Node: Constraints, Next: Standard Names, Prev: Output Statement, Up: Machine Desc
205 Each `match_operand' in an instruction pattern can specify a
206 constraint for the type of operands allowed. Constraints can say
207 whether an operand may be in a register, and which kinds of register;
208 whether the operand can be a memory reference, and which kinds of
209 address; whether the operand may be an immediate constant, and which
210 possible values it may have. Constraints can also require two operands
215 * Simple Constraints:: Basic use of constraints.
216 * Multi-Alternative:: When an insn has two alternative constraint-patterns.
217 * Class Preferences:: Constraints guide which hard register to put things in.
218 * Modifiers:: More precise control over effects of constraints.
219 * Machine Constraints:: Existing constraints for some particular machines.
220 * No Constraints:: Describing a clean machine without constraints.
223 File: gcc.info, Node: Simple Constraints, Next: Multi-Alternative, Up: Constraints
228 The simplest kind of constraint is a string full of letters, each of
229 which describes one kind of operand that is permitted. Here are the
230 letters that are allowed:
233 A memory operand is allowed, with any kind of address that the
234 machine supports in general.
237 A memory operand is allowed, but only if the address is
238 "offsettable". This means that adding a small integer (actually,
239 the width in bytes of the operand, as determined by its machine
240 mode) may be added to the address and the result is also a valid
243 For example, an address which is constant is offsettable; so is an
244 address that is the sum of a register and a constant (as long as a
245 slightly larger constant is also within the range of
246 address-offsets supported by the machine); but an autoincrement or
247 autodecrement address is not offsettable. More complicated
248 indirect/indexed addresses may or may not be offsettable depending
249 on the other addressing modes that the machine supports.
251 Note that in an output operand which can be matched by another
252 operand, the constraint letter `o' is valid only when accompanied
253 by both `<' (if the target machine has predecrement addressing)
254 and `>' (if the target machine has preincrement addressing).
257 A memory operand that is not offsettable. In other words,
258 anything that would fit the `m' constraint but not the `o'
262 A memory operand with autodecrement addressing (either
263 predecrement or postdecrement) is allowed.
266 A memory operand with autoincrement addressing (either
267 preincrement or postincrement) is allowed.
270 A register operand is allowed provided that it is in a general
274 Other letters can be defined in machine-dependent fashion to stand
275 for particular classes of registers. `d', `a' and `f' are defined
276 on the 68000/68020 to stand for data, address and floating point
280 An immediate integer operand (one with constant value) is allowed.
281 This includes symbolic constants whose values will be known only at
285 An immediate integer operand with a known numeric value is allowed.
286 Many systems cannot support assembly-time constants for operands
287 less than a word wide. Constraints for these operands should use
290 `I', `J', `K', ... `P'
291 Other letters in the range `I' through `P' may be defined in a
292 machine-dependent fashion to permit immediate integer operands with
293 explicit integer values in specified ranges. For example, on the
294 68000, `I' is defined to stand for the range of values 1 to 8.
295 This is the range permitted as a shift count in the shift
299 An immediate floating operand (expression code `const_double') is
300 allowed, but only if the target floating point format is the same
301 as that of the host machine (on which the compiler is running).
304 An immediate floating operand (expression code `const_double') is
308 `G' and `H' may be defined in a machine-dependent fashion to
309 permit immediate floating operands in particular ranges of values.
312 An immediate integer operand whose value is not an explicit
315 This might appear strange; if an insn allows a constant operand
316 with a value not known at compile time, it certainly must allow
317 any known value. So why use `s' instead of `i'? Sometimes it
318 allows better code to be generated.
320 For example, on the 68000 in a fullword instruction it is possible
321 to use an immediate operand; but if the immediate value is between
322 -128 and 127, better code results from loading the value into a
323 register and using the register. This is because the load into
324 the register can be done with a `moveq' instruction. We arrange
325 for this to happen by defining the letter `K' to mean "any integer
326 outside the range -128 to 127", and then specifying `Ks' in the
330 Any register, memory or immediate integer operand is allowed,
331 except for registers that are not general registers.
334 Any operand whatsoever is allowed, even if it does not satisfy
335 `general_operand'. This is normally used in the constraint of a
336 `match_scratch' when certain alternatives will not actually
337 require a scratch register.
339 `0', `1', `2', ... `9'
340 An operand that matches the specified operand number is allowed.
341 If a digit is used together with letters within the same
342 alternative, the digit should come last.
344 This is called a "matching constraint" and what it really means is
345 that the assembler has only a single operand that fills two roles
346 considered separate in the RTL insn. For example, an add insn has
347 two input operands and one output operand in the RTL, but on most
348 CISC machines an add instruction really has only two operands, one
349 of them an input-output operand:
353 Matching constraints are used in these circumstances. More
354 precisely, the two operands that match must include one input-only
355 operand and one output-only operand. Moreover, the digit must be a
356 smaller number than the number of the operand that uses it in the
359 For operands to match in a particular case usually means that they
360 are identical-looking RTL expressions. But in a few special cases
361 specific kinds of dissimilarity are allowed. For example, `*x' as
362 an input operand will match `*x++' as an output operand. For
363 proper results in such cases, the output template should always
364 use the output-operand's number when printing the operand.
367 An operand that is a valid memory address is allowed. This is for
368 "load address" and "push address" instructions.
370 `p' in the constraint must be accompanied by `address_operand' as
371 the predicate in the `match_operand'. This predicate interprets
372 the mode specified in the `match_operand' as the mode of the memory
373 reference for which the address would be valid.
375 `Q', `R', `S', ... `U'
376 Letters in the range `Q' through `U' may be defined in a
377 machine-dependent fashion to stand for arbitrary operand types.
378 The machine description macro `EXTRA_CONSTRAINT' is passed the
379 operand as its first argument and the constraint letter as its
382 A typical use for this would be to distinguish certain types of
383 memory references that affect other insn operands.
385 Do not define these constraint letters to accept register
386 references (`reg'); the reload pass does not expect this and would
387 not handle it properly.
389 In order to have valid assembler code, each operand must satisfy its
390 constraint. But a failure to do so does not prevent the pattern from
391 applying to an insn. Instead, it directs the compiler to modify the
392 code so that the constraint will be satisfied. Usually this is done by
393 copying an operand into a register.
395 Contrast, therefore, the two instruction patterns that follow:
398 [(set (match_operand:SI 0 "general_operand" "=r")
399 (plus:SI (match_dup 0)
400 (match_operand:SI 1 "general_operand" "r")))]
404 which has two operands, one of which must appear in two places, and
407 [(set (match_operand:SI 0 "general_operand" "=r")
408 (plus:SI (match_operand:SI 1 "general_operand" "0")
409 (match_operand:SI 2 "general_operand" "r")))]
413 which has three operands, two of which are required by a constraint to
414 be identical. If we are considering an insn of the form
418 (plus:SI (reg:SI 6) (reg:SI 109)))
421 the first pattern would not apply at all, because this insn does not
422 contain two identical subexpressions in the right place. The pattern
423 would say, "That does not look like an add instruction; try other
424 patterns." The second pattern would say, "Yes, that's an add
425 instruction, but there is something wrong with it." It would direct
426 the reload pass of the compiler to generate additional insns to make
427 the constraint true. The results might look like this:
430 (set (reg:SI 3) (reg:SI 6))
435 (plus:SI (reg:SI 3) (reg:SI 109)))
438 It is up to you to make sure that each operand, in each pattern, has
439 constraints that can handle any RTL expression that could be present for
440 that operand. (When multiple alternatives are in use, each pattern
441 must, for each possible combination of operand expressions, have at
442 least one alternative which can handle that combination of operands.)
443 The constraints don't need to *allow* any possible operand--when this is
444 the case, they do not constrain--but they must at least point the way to
445 reloading any possible operand so that it will fit.
447 * If the constraint accepts whatever operands the predicate permits,
448 there is no problem: reloading is never necessary for this operand.
450 For example, an operand whose constraints permit everything except
451 registers is safe provided its predicate rejects registers.
453 An operand whose predicate accepts only constant values is safe
454 provided its constraints include the letter `i'. If any possible
455 constant value is accepted, then nothing less than `i' will do; if
456 the predicate is more selective, then the constraints may also be
459 * Any operand expression can be reloaded by copying it into a
460 register. So if an operand's constraints allow some kind of
461 register, it is certain to be safe. It need not permit all
462 classes of registers; the compiler knows how to copy a register
463 into another register of the proper class in order to make an
466 * A nonoffsettable memory reference can be reloaded by copying the
467 address into a register. So if the constraint uses the letter
468 `o', all memory references are taken care of.
470 * A constant operand can be reloaded by allocating space in memory to
471 hold it as preinitialized data. Then the memory reference can be
472 used in place of the constant. So if the constraint uses the
473 letters `o' or `m', constant operands are not a problem.
475 * If the constraint permits a constant and a pseudo register used in
476 an insn was not allocated to a hard register and is equivalent to
477 a constant, the register will be replaced with the constant. If
478 the predicate does not permit a constant and the insn is
479 re-recognized for some reason, the compiler will crash. Thus the
480 predicate must always recognize any objects allowed by the
483 If the operand's predicate can recognize registers, but the
484 constraint does not permit them, it can make the compiler crash. When
485 this operand happens to be a register, the reload pass will be stymied,
486 because it does not know how to copy a register temporarily into memory.
488 If the predicate accepts a unary operator, the constraint applies to
489 the operand. For example, the MIPS processor at ISA level 3 supports an
490 instruction which adds two registers in `SImode' to produce a `DImode'
491 result, but only if the registers are correctly sign extended. This
492 predicate for the input operands accepts a `sign_extend' of an `SImode'
493 register. Write the constraint to indicate the type of register that
494 is required for the operand of the `sign_extend'.
497 File: gcc.info, Node: Multi-Alternative, Next: Class Preferences, Prev: Simple Constraints, Up: Constraints
499 Multiple Alternative Constraints
500 --------------------------------
502 Sometimes a single instruction has multiple alternative sets of
503 possible operands. For example, on the 68000, a logical-or instruction
504 can combine register or an immediate value into memory, or it can
505 combine any kind of operand into a register; but it cannot combine one
506 memory location into another.
508 These constraints are represented as multiple alternatives. An
509 alternative can be described by a series of letters for each operand.
510 The overall constraint for an operand is made from the letters for this
511 operand from the first alternative, a comma, the letters for this
512 operand from the second alternative, a comma, and so on until the last
513 alternative. Here is how it is done for fullword logical-or on the
516 (define_insn "iorsi3"
517 [(set (match_operand:SI 0 "general_operand" "=m,d")
518 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
519 (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
522 The first alternative has `m' (memory) for operand 0, `0' for
523 operand 1 (meaning it must match operand 0), and `dKs' for operand 2.
524 The second alternative has `d' (data register) for operand 0, `0' for
525 operand 1, and `dmKs' for operand 2. The `=' and `%' in the
526 constraints apply to all the alternatives; their meaning is explained
527 in the next section (*note Class Preferences::.).
529 If all the operands fit any one alternative, the instruction is
530 valid. Otherwise, for each alternative, the compiler counts how many
531 instructions must be added to copy the operands so that that
532 alternative applies. The alternative requiring the least copying is
533 chosen. If two alternatives need the same amount of copying, the one
534 that comes first is chosen. These choices can be altered with the `?'
538 Disparage slightly the alternative that the `?' appears in, as a
539 choice when no alternative applies exactly. The compiler regards
540 this alternative as one unit more costly for each `?' that appears
544 Disparage severely the alternative that the `!' appears in. This
545 alternative can still be used if it fits without reloading, but if
546 reloading is needed, some other alternative will be used.
548 When an insn pattern has multiple alternatives in its constraints,
549 often the appearance of the assembler code is determined mostly by which
550 alternative was matched. When this is so, the C code for writing the
551 assembler code can use the variable `which_alternative', which is the
552 ordinal number of the alternative that was actually satisfied (0 for
553 the first, 1 for the second alternative, etc.). *Note Output
557 File: gcc.info, Node: Class Preferences, Next: Modifiers, Prev: Multi-Alternative, Up: Constraints
559 Register Class Preferences
560 --------------------------
562 The operand constraints have another function: they enable the
563 compiler to decide which kind of hardware register a pseudo register is
564 best allocated to. The compiler examines the constraints that apply to
565 the insns that use the pseudo register, looking for the
566 machine-dependent letters such as `d' and `a' that specify classes of
567 registers. The pseudo register is put in whichever class gets the most
568 "votes". The constraint letters `g' and `r' also vote: they vote in
569 favor of a general register. The machine description says which
570 registers are considered general.
572 Of course, on some machines all registers are equivalent, and no
573 register classes are defined. Then none of this complexity is relevant.
576 File: gcc.info, Node: Modifiers, Next: Machine Constraints, Prev: Class Preferences, Up: Constraints
578 Constraint Modifier Characters
579 ------------------------------
581 Here are constraint modifier characters.
584 Means that this operand is write-only for this instruction: the
585 previous value is discarded and replaced by output data.
588 Means that this operand is both read and written by the
591 When the compiler fixes up the operands to satisfy the constraints,
592 it needs to know which operands are inputs to the instruction and
593 which are outputs from it. `=' identifies an output; `+'
594 identifies an operand that is both input and output; all other
595 operands are assumed to be input only.
598 Means (in a particular alternative) that this operand is an
599 "earlyclobber" operand, which is modified before the instruction is
600 finished using the input operands. Therefore, this operand may
601 not lie in a register that is used as an input operand or as part
602 of any memory address.
604 `&' applies only to the alternative in which it is written. In
605 constraints with multiple alternatives, sometimes one alternative
606 requires `&' while others do not. See, for example, the `movdf'
609 An input operand can be tied to an earlyclobber operand if its only
610 use as an input occurs before the early result is written. Adding
611 alternatives of this form often allows GCC to produce better code
612 when only some of the inputs can be affected by the earlyclobber.
613 See, for example, the `mulsi3' insn of the ARM.
615 `&' does not obviate the need to write `='.
618 Declares the instruction to be commutative for this operand and the
619 following operand. This means that the compiler may interchange
620 the two operands if that is the cheapest way to make all operands
621 fit the constraints. This is often used in patterns for addition
622 instructions that really have only two operands: the result must
623 go in one of the arguments. Here for example, is how the 68000
624 halfword-add instruction is defined:
626 (define_insn "addhi3"
627 [(set (match_operand:HI 0 "general_operand" "=m,r")
628 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
629 (match_operand:HI 2 "general_operand" "di,g")))]
633 Says that all following characters, up to the next comma, are to be
634 ignored as a constraint. They are significant only for choosing
635 register preferences.
638 Says that the following character should be ignored when choosing
639 register preferences. `*' has no effect on the meaning of the
640 constraint as a constraint, and no effect on reloading.
642 Here is an example: the 68000 has an instruction to sign-extend a
643 halfword in a data register, and can also sign-extend a value by
644 copying it into an address register. While either kind of
645 register is acceptable, the constraints on an address-register
646 destination are less strict, so it is best if register allocation
647 makes an address register its goal. Therefore, `*' is used so
648 that the `d' constraint letter (for data register) is ignored when
649 computing register preferences.
651 (define_insn "extendhisi2"
652 [(set (match_operand:SI 0 "general_operand" "=*d,a")
654 (match_operand:HI 1 "general_operand" "0,g")))]
658 File: gcc.info, Node: Machine Constraints, Next: No Constraints, Prev: Modifiers, Up: Constraints
660 Constraints for Particular Machines
661 -----------------------------------
663 Whenever possible, you should use the general-purpose constraint
664 letters in `asm' arguments, since they will convey meaning more readily
665 to people reading your code. Failing that, use the constraint letters
666 that usually have very similar meanings across architectures. The most
667 commonly used constraints are `m' and `r' (for memory and
668 general-purpose registers respectively; *note Simple Constraints::.),
669 and `I', usually the letter indicating the most common
670 immediate-constant format.
672 For each machine architecture, the `config/MACHINE.h' file defines
673 additional constraints. These constraints are used by the compiler
674 itself for instruction generation, as well as for `asm' statements;
675 therefore, some of the constraints are not particularly interesting for
676 `asm'. The constraints are defined through these macros:
678 `REG_CLASS_FROM_LETTER'
679 Register class constraints (usually lower case).
681 `CONST_OK_FOR_LETTER_P'
682 Immediate constant constraints, for non-floating point constants of
683 word size or smaller precision (usually upper case).
685 `CONST_DOUBLE_OK_FOR_LETTER_P'
686 Immediate constant constraints, for all floating point constants
687 and for constants of greater than word size precision (usually
691 Special cases of registers or memory. This macro is not required,
692 and is only defined for some machines.
694 Inspecting these macro definitions in the compiler source for your
695 machine is the best way to be certain you have the right constraints.
696 However, here is a summary of the machine-dependent constraints
697 available on some particular machines.
699 *ARM family--`arm.h'*
702 Floating-point register
705 One of the floating-point constants 0.0, 0.5, 1.0, 2.0, 3.0,
709 Floating-point constant that would satisfy the constraint `F'
713 Integer that is valid as an immediate operand in a data
714 processing instruction. That is, an integer in the range 0
715 to 255 rotated by a multiple of 2
718 Integer in the range -4095 to 4095
721 Integer that satisfies constraint `I' when inverted (ones
725 Integer that satisfies constraint `I' when negated (twos
729 Integer in the range 0 to 32
732 A memory reference where the exact address is in a single
733 register (``m'' is preferable for `asm' statements)
736 An item in the constant pool
739 A symbol in the text segment of the current file
741 *AMD 29000 family--`a29k.h'*
747 Byte Pointer (`BP') register
753 Special purpose register
756 First accumulator register
759 Other accumulator register
762 Floating point register
765 Constant greater than 0, less than 0x100
768 Constant greater than 0, less than 0x10000
771 Constant whose high 24 bits are on (1)
774 16 bit constant whose high 8 bits are on (1)
777 32 bit constant whose high 16 bits are on (1)
780 32 bit negative constant that fits in 8 bits
783 The constant 0x80000000 or, on the 29050, any 32 bit constant
784 whose low 16 bits are 0.
787 16 bit negative constant that fits in 8 bits
791 A floating point constant (in `asm' statements, use the
792 machine independent `E' or `F' instead)
794 *IBM RS6000--`rs6000.h'*
797 Address base register
800 Floating point register
803 `MQ', `CTR', or `LINK' register
815 `CR' register (condition register) number 0
818 `CR' register (condition register)
821 Signed 16 bit constant
824 Constant whose low 16 bits are 0
827 Constant whose high 16 bits are 0
830 Constant suitable as a mask operand
833 Constant larger than 31
842 Constant whose negation is a signed 16 bit constant
845 Floating point constant that can be loaded into a register
846 with one instruction per word
849 Memory operand that is an offset from a register (`m' is
850 preferable for `asm' statements)
856 Windows NT SYMBOL_REF
862 System V Release 4 small data area reference
864 *Intel 386--`i386.h'*
867 `a', `b', `c', or `d' register
870 `a', or `d' register (for 64-bit ints)
873 Floating point register
876 First (top of stack) floating point register
879 Second floating point register
900 Constant in range 0 to 31 (for 32 bit shifts)
903 Constant in range 0 to 63 (for 64 bit shifts)
912 0, 1, 2, or 3 (shifts for `lea' instruction)
915 Constant in range 0 to 255 (for `out' instruction)
918 Standard 80387 floating point constant
920 *Intel 960--`i960.h'*
923 Floating point register (`fp0' to `fp3')
926 Local register (`r0' to `r15')
929 Global register (`g0' to `g15')
932 Any local or global register
935 Integers from 0 to 31
941 Integers from -31 to 0
952 General-purpose integer register
955 Floating-point register (if available)
964 `Hi' or `Lo' register
967 General-purpose integer register
970 Floating-point status register
973 Signed 16 bit constant (for arithmetic instructions)
979 Zero-extended 16-bit constant (for logic instructions)
982 Constant with low 16 bits zero (can be loaded with `lui')
985 32 bit constant which requires two instructions to load (a
986 constant which is not `I', `K', or `L')
989 Negative 16 bit constant
995 Positive 16 bit constant
1001 Memory reference that can be loaded with more than one
1002 instruction (`m' is preferable for `asm' statements)
1005 Memory reference that can be loaded with one instruction (`m'
1006 is preferable for `asm' statements)
1009 Memory reference in external OSF/rose PIC format (`m' is
1010 preferable for `asm' statements)
1012 *Motorola 680x0--`m68k.h'*
1021 68881 floating-point register, if available
1024 Sun FPA (floating-point) register, if available
1027 First 16 Sun FPA registers, if available
1030 Integer in the range 1 to 8
1033 16 bit signed number
1036 Signed number whose magnitude is greater than 0x80
1039 Integer in the range -8 to -1
1042 Signed number whose magnitude is greater than 0x100
1045 Floating point constant that is not a 68881 constant
1048 Floating point constant that can be used by Sun FPA
1053 Floating-point register that can hold 32 or 64 bit values.
1056 Floating-point register that can hold 64 or 128 bit values.
1059 Signed 13 bit constant
1065 32 bit constant with the low 12 bits clear (a constant that
1066 can be loaded with the `sethi' instruction)
1072 Signed 13 bit constant, sign-extended to 32 or 64 bits
1075 Memory reference that can be loaded with one instruction
1076 (`m' is more appropriate for `asm' statements)
1079 Constant, or memory address
1082 Memory address aligned to an 8-byte boundary
1088 File: gcc.info, Node: No Constraints, Prev: Machine Constraints, Up: Constraints
1090 Not Using Constraints
1091 ---------------------
1093 Some machines are so clean that operand constraints are not
1094 required. For example, on the Vax, an operand valid in one context is
1095 valid in any other context. On such a machine, every operand
1096 constraint would be `g', excepting only operands of "load address"
1097 instructions which are written as if they referred to a memory
1098 location's contents but actual refer to its address. They would have
1101 For such machines, instead of writing `g' and `p' for all the
1102 constraints, you can choose to write a description with empty
1103 constraints. Then you write `""' for the constraint in every
1104 `match_operand'. Address operands are identified by writing an
1105 `address' expression around the `match_operand', not by their
1108 When the machine description has just empty constraints, certain
1109 parts of compilation are skipped, making the compiler faster. However,
1110 few machines actually do not need constraints; all machine descriptions
1111 now in existence use constraints.