1 /* Subroutines for insn-output.c for Sun SPARC.
2 Copyright (C) 1987, 88, 89, 92-97, 1998 Free Software Foundation, Inc.
3 Contributed by Michael Tiemann (tiemann@cygnus.com)
4 64 bit SPARC V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-flags.h"
35 #include "insn-attr.h"
40 /* 1 if the caller has placed an "unimp" insn immediately after the call.
41 This is used in v8 code when calling a function that returns a structure.
42 v9 doesn't have this. Be careful to have this test be the same as that
45 #define SKIP_CALLERS_UNIMP_P \
46 (!TARGET_ARCH64 && current_function_returns_struct \
47 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
48 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
51 /* Global variables for machine-dependent things. */
53 /* Size of frame. Need to know this to emit return insns from leaf procedures.
54 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
55 reload pass. This is important as the value is later used in insn
56 scheduling (to see what can go in a delay slot).
57 APPARENT_FSIZE is the size of the stack less the register save area and less
58 the outgoing argument area. It is used when saving call preserved regs. */
59 static int apparent_fsize
;
60 static int actual_fsize
;
62 /* Save the operands last given to a compare for use when we
63 generate a scc or bcc insn. */
65 rtx sparc_compare_op0
, sparc_compare_op1
;
67 /* We may need an epilogue if we spill too many registers.
68 If this is non-zero, then we branch here for the epilogue. */
69 static rtx leaf_label
;
73 /* Vector to say how input registers are mapped to output
74 registers. FRAME_POINTER_REGNUM cannot be remapped by
75 this function to eliminate it. You must use -fomit-frame-pointer
77 char leaf_reg_remap
[] =
78 { 0, 1, 2, 3, 4, 5, 6, 7,
79 -1, -1, -1, -1, -1, -1, 14, -1,
80 -1, -1, -1, -1, -1, -1, -1, -1,
81 8, 9, 10, 11, 12, 13, -1, 15,
83 32, 33, 34, 35, 36, 37, 38, 39,
84 40, 41, 42, 43, 44, 45, 46, 47,
85 48, 49, 50, 51, 52, 53, 54, 55,
86 56, 57, 58, 59, 60, 61, 62, 63,
87 64, 65, 66, 67, 68, 69, 70, 71,
88 72, 73, 74, 75, 76, 77, 78, 79,
89 80, 81, 82, 83, 84, 85, 86, 87,
90 88, 89, 90, 91, 92, 93, 94, 95,
95 /* Name of where we pretend to think the frame pointer points.
96 Normally, this is "%fp", but if we are in a leaf procedure,
97 this is "%sp+something". We record "something" separately as it may be
98 too big for reg+constant addressing. */
100 static char *frame_base_name
;
101 static int frame_base_offset
;
103 static rtx pic_setup_code
PROTO((void));
104 static rtx find_addr_reg
PROTO((rtx
));
105 static void sparc_init_modes
PROTO((void));
106 static int save_regs
PROTO((FILE *, int, int, char *,
108 static int restore_regs
PROTO((FILE *, int, int, char *, int, int));
109 static void build_big_number
PROTO((FILE *, int, char *));
110 static function_arg_slotno
PROTO((const CUMULATIVE_ARGS
*,
111 enum machine_mode
, tree
, int, int,
114 #ifdef DWARF2_DEBUGGING_INFO
115 extern char *dwarf2out_cfi_label ();
118 /* Option handling. */
120 /* Code model option as passed by user. */
121 char *sparc_cmodel_string
;
123 enum cmodel sparc_cmodel
;
125 /* Record alignment options as passed by user. */
126 char *sparc_align_loops_string
;
127 char *sparc_align_jumps_string
;
128 char *sparc_align_funcs_string
;
130 /* Parsed values, as a power of two. */
131 int sparc_align_loops
;
132 int sparc_align_jumps
;
133 int sparc_align_funcs
;
135 struct sparc_cpu_select sparc_select
[] =
137 /* switch name, tune arch */
138 { (char *)0, "default", 1, 1 },
139 { (char *)0, "-mcpu=", 1, 1 },
140 { (char *)0, "-mtune=", 1, 0 },
144 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
145 enum processor_type sparc_cpu
;
147 /* Validate and override various options, and do some machine dependent
151 sparc_override_options ()
153 static struct code_model
{
158 { "medlow", CM_MEDLOW
},
159 { "medmid", CM_MEDMID
},
160 { "medany", CM_MEDANY
},
161 { "embmedany", CM_EMBMEDANY
},
164 struct code_model
*cmodel
;
165 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
166 static struct cpu_default
{
170 /* There must be one entry here for each TARGET_CPU value. */
171 { TARGET_CPU_sparc
, "cypress" },
172 { TARGET_CPU_sparclet
, "tsc701" },
173 { TARGET_CPU_sparclite
, "f930" },
174 { TARGET_CPU_v8
, "v8" },
175 { TARGET_CPU_supersparc
, "supersparc" },
176 { TARGET_CPU_v9
, "v9" },
177 { TARGET_CPU_ultrasparc
, "ultrasparc" },
180 struct cpu_default
*def
;
181 /* Table of values for -m{cpu,tune}=. */
182 static struct cpu_table
{
184 enum processor_type processor
;
188 { "v7", PROCESSOR_V7
, MASK_ISA
, 0 },
189 { "cypress", PROCESSOR_CYPRESS
, MASK_ISA
, 0 },
190 { "v8", PROCESSOR_V8
, MASK_ISA
, MASK_V8
},
191 /* TI TMS390Z55 supersparc */
192 { "supersparc", PROCESSOR_SUPERSPARC
, MASK_ISA
, MASK_V8
},
193 { "sparclite", PROCESSOR_SPARCLITE
, MASK_ISA
, MASK_SPARCLITE
},
194 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
195 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
196 { "f930", PROCESSOR_F930
, MASK_ISA
|MASK_FPU
, MASK_SPARCLITE
},
197 { "f934", PROCESSOR_F934
, MASK_ISA
, MASK_SPARCLITE
|MASK_FPU
},
198 { "sparclet", PROCESSOR_SPARCLET
, MASK_ISA
, MASK_SPARCLET
},
200 { "tsc701", PROCESSOR_TSC701
, MASK_ISA
, MASK_SPARCLET
},
201 /* "v8plus" is what Sun calls Solaris2.5 running on UltraSPARC's. */
202 { "v8plus", PROCESSOR_V8PLUS
, MASK_ISA
, MASK_V9
},
203 { "v9", PROCESSOR_V9
, MASK_ISA
, MASK_V9
},
205 { "ultrasparc", PROCESSOR_ULTRASPARC
, MASK_ISA
, MASK_V9
},
208 struct cpu_table
*cpu
;
209 struct sparc_cpu_select
*sel
;
212 #ifndef SPARC_BI_ARCH
213 /* Check for unsupported architecture size. */
214 if (! TARGET_64BIT
!= DEFAULT_ARCH32_P
)
216 error ("%s is not supported by this configuration",
217 DEFAULT_ARCH32_P
? "-m64" : "-m32");
221 /* Code model selection. */
222 sparc_cmodel
= SPARC_DEFAULT_CMODEL
;
223 if (sparc_cmodel_string
!= NULL
)
227 for (cmodel
= &cmodels
[0]; cmodel
->name
; cmodel
++)
228 if (strcmp (sparc_cmodel_string
, cmodel
->name
) == 0)
230 if (cmodel
->name
== NULL
)
231 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string
);
233 sparc_cmodel
= cmodel
->value
;
236 error ("-mcmodel= is not supported on 32 bit systems");
239 fpu
= TARGET_FPU
; /* save current -mfpu status */
241 /* Set the default CPU. */
242 for (def
= &cpu_default
[0]; def
->name
; ++def
)
243 if (def
->cpu
== TARGET_CPU_DEFAULT
)
247 sparc_select
[0].string
= def
->name
;
249 for (sel
= &sparc_select
[0]; sel
->name
; ++sel
)
253 for (cpu
= &cpu_table
[0]; cpu
->name
; ++cpu
)
254 if (! strcmp (sel
->string
, cpu
->name
))
257 sparc_cpu
= cpu
->processor
;
261 target_flags
&= ~cpu
->disable
;
262 target_flags
|= cpu
->enable
;
268 error ("bad value (%s) for %s switch", sel
->string
, sel
->name
);
272 /* If -mfpu or -mno-fpu was explicitly used, don't override with
273 the processor default. */
275 target_flags
= (target_flags
& ~MASK_FPU
) | fpu
;
277 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
278 if (TARGET_V9
&& TARGET_ARCH32
)
279 target_flags
|= MASK_DEPRECATED_V8_INSNS
;
281 /* Validate -malign-loops= value, or provide default. */
282 if (sparc_align_loops_string
)
284 sparc_align_loops
= exact_log2 (atoi (sparc_align_loops_string
));
285 if (sparc_align_loops
< 2 || sparc_align_loops
> 7)
286 fatal ("-malign-loops=%s is not between 4 and 128 or is not a power of two",
287 sparc_align_loops_string
);
291 /* ??? This relies on ASM_OUTPUT_ALIGN to not emit the alignment if
292 its 0. This sounds a bit kludgey. */
293 sparc_align_loops
= 0;
296 /* Validate -malign-jumps= value, or provide default. */
297 if (sparc_align_jumps_string
)
299 sparc_align_jumps
= exact_log2 (atoi (sparc_align_jumps_string
));
300 if (sparc_align_jumps
< 2 || sparc_align_loops
> 7)
301 fatal ("-malign-jumps=%s is not between 4 and 128 or is not a power of two",
302 sparc_align_jumps_string
);
306 /* ??? This relies on ASM_OUTPUT_ALIGN to not emit the alignment if
307 its 0. This sounds a bit kludgey. */
308 sparc_align_jumps
= 0;
311 /* Validate -malign-functions= value, or provide default. */
312 if (sparc_align_funcs_string
)
314 sparc_align_funcs
= exact_log2 (atoi (sparc_align_funcs_string
));
315 if (sparc_align_funcs
< 2 || sparc_align_loops
> 7)
316 fatal ("-malign-functions=%s is not between 4 and 128 or is not a power of two",
317 sparc_align_funcs_string
);
320 sparc_align_funcs
= DEFAULT_SPARC_ALIGN_FUNCS
;
322 /* Do various machine dependent initializations. */
326 /* Float conversions (v9 only).
328 The floating point registers cannot hold DImode values because SUBREG's
329 on them get the wrong register. "(subreg:SI (reg:DI M int-reg) 0)" is the
330 same as "(subreg:SI (reg:DI N float-reg) 1)", but gcc doesn't know how to
331 turn the "0" to a "1". Therefore, we must explicitly do the conversions
332 to/from int/fp regs. `sparc64_fpconv_stack_slot' is the address of an
333 8 byte stack slot used during the transfer.
334 ??? I could have used [%fp-16] but I didn't want to add yet another
335 dependence on this. */
336 /* ??? Can we use assign_stack_temp here? */
338 static rtx fpconv_stack_temp
;
340 /* Called once for each function. */
343 sparc_init_expanders ()
345 fpconv_stack_temp
= NULL_RTX
;
348 /* Assign a stack temp for fp/int DImode conversions. */
351 sparc64_fpconv_stack_temp ()
353 if (fpconv_stack_temp
== NULL_RTX
)
355 assign_stack_local (DImode
, GET_MODE_SIZE (DImode
), 0);
357 return fpconv_stack_temp
;
360 /* Miscellaneous utilities. */
362 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
363 or branch on register contents instructions. */
369 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
370 || code
== LE
|| code
== GT
);
373 /* Operand constraints. */
375 /* Return non-zero only if OP is a register of mode MODE,
376 or const0_rtx. Don't allow const0_rtx if TARGET_LIVE_G0 because
377 %g0 may contain anything. */
380 reg_or_0_operand (op
, mode
)
382 enum machine_mode mode
;
384 if (register_operand (op
, mode
))
388 if (op
== const0_rtx
)
390 if (GET_MODE (op
) == VOIDmode
&& GET_CODE (op
) == CONST_DOUBLE
391 && CONST_DOUBLE_HIGH (op
) == 0
392 && CONST_DOUBLE_LOW (op
) == 0)
394 if (GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
395 && GET_CODE (op
) == CONST_DOUBLE
396 && fp_zero_operand (op
))
401 /* Nonzero if OP is a floating point value with value 0.0. */
409 REAL_VALUE_FROM_CONST_DOUBLE (r
, op
);
410 return (REAL_VALUES_EQUAL (r
, dconst0
) && ! REAL_VALUE_MINUS_ZERO (r
));
413 /* Nonzero if OP is an integer register. */
416 intreg_operand (op
, mode
)
418 enum machine_mode mode
;
420 return (register_operand (op
, SImode
)
421 || (TARGET_ARCH64
&& register_operand (op
, DImode
)));
424 /* Nonzero if OP is a floating point condition code register. */
427 fcc_reg_operand (op
, mode
)
429 enum machine_mode mode
;
431 /* This can happen when recog is called from combine. Op may be a MEM.
432 Fail instead of calling abort in this case. */
433 if (GET_CODE (op
) != REG
)
436 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
439 && (GET_MODE (op
) != CCFPmode
&& GET_MODE (op
) != CCFPEmode
))
442 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
443 if (reg_renumber
== 0)
444 return REGNO (op
) >= FIRST_PSEUDO_REGISTER
;
445 return REGNO_OK_FOR_CCFP_P (REGNO (op
));
447 return (unsigned) REGNO (op
) - SPARC_FIRST_V9_FCC_REG
< 4;
451 /* Nonzero if OP is an integer or floating point condition code register. */
454 icc_or_fcc_reg_operand (op
, mode
)
456 enum machine_mode mode
;
458 if (GET_CODE (op
) == REG
&& REGNO (op
) == SPARC_ICC_REG
)
460 if (mode
!= VOIDmode
&& mode
!= GET_MODE (op
))
463 && GET_MODE (op
) != CCmode
&& GET_MODE (op
) != CCXmode
)
468 return fcc_reg_operand (op
, mode
);
471 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
473 restore_operand (op
, mode
)
475 enum machine_mode mode
;
477 return (GET_CODE (op
) == REG
&& GET_MODE (op
) == mode
478 && (REGNO (op
) < 8 || (REGNO (op
) >= 24 && REGNO (op
) < 32)));
481 /* Call insn on SPARC can take a PC-relative constant address, or any regular
485 call_operand (op
, mode
)
487 enum machine_mode mode
;
489 if (GET_CODE (op
) != MEM
)
492 return (symbolic_operand (op
, mode
) || memory_address_p (Pmode
, op
));
496 call_operand_address (op
, mode
)
498 enum machine_mode mode
;
500 return (symbolic_operand (op
, mode
) || memory_address_p (Pmode
, op
));
503 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
504 reference and a constant. */
507 symbolic_operand (op
, mode
)
509 enum machine_mode mode
;
511 switch (GET_CODE (op
))
519 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
520 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
521 && GET_CODE (XEXP (op
, 1)) == CONST_INT
);
523 /* ??? This clause seems to be irrelevant. */
525 return GET_MODE (op
) == mode
;
532 /* Return truth value of statement that OP is a symbolic memory
533 operand of mode MODE. */
536 symbolic_memory_operand (op
, mode
)
538 enum machine_mode mode
;
540 if (GET_CODE (op
) == SUBREG
)
541 op
= SUBREG_REG (op
);
542 if (GET_CODE (op
) != MEM
)
545 return (GET_CODE (op
) == SYMBOL_REF
|| GET_CODE (op
) == CONST
546 || GET_CODE (op
) == HIGH
|| GET_CODE (op
) == LABEL_REF
);
549 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
552 label_ref_operand (op
, mode
)
554 enum machine_mode mode
;
556 if (GET_CODE (op
) != LABEL_REF
)
558 if (GET_MODE (op
) != mode
)
563 /* Return 1 if the operand is an argument used in generating pic references
564 in either the medium/low or medium/anywhere code models of sparc64. */
567 sp64_medium_pic_operand (op
, mode
)
569 enum machine_mode mode
;
571 /* Check for (const (minus (symbol_ref:GOT)
572 (const (minus (label) (pc))))). */
573 if (GET_CODE (op
) != CONST
)
576 if (GET_CODE (op
) != MINUS
)
578 if (GET_CODE (XEXP (op
, 0)) != SYMBOL_REF
)
580 /* ??? Ensure symbol is GOT. */
581 if (GET_CODE (XEXP (op
, 1)) != CONST
)
583 if (GET_CODE (XEXP (XEXP (op
, 1), 0)) != MINUS
)
588 /* Return 1 if the operand is a data segment reference. This includes
589 the readonly data segment, or in other words anything but the text segment.
590 This is needed in the medium/anywhere code model on v9. These values
591 are accessed with EMBMEDANY_BASE_REG. */
594 data_segment_operand (op
, mode
)
596 enum machine_mode mode
;
598 switch (GET_CODE (op
))
601 return ! SYMBOL_REF_FLAG (op
);
603 /* Assume canonical format of symbol + constant.
606 return data_segment_operand (XEXP (op
, 0));
612 /* Return 1 if the operand is a text segment reference.
613 This is needed in the medium/anywhere code model on v9. */
616 text_segment_operand (op
, mode
)
618 enum machine_mode mode
;
620 switch (GET_CODE (op
))
625 return SYMBOL_REF_FLAG (op
);
627 /* Assume canonical format of symbol + constant.
630 return text_segment_operand (XEXP (op
, 0));
636 /* Return 1 if the operand is either a register or a memory operand that is
640 reg_or_nonsymb_mem_operand (op
, mode
)
642 enum machine_mode mode
;
644 if (register_operand (op
, mode
))
647 if (memory_operand (op
, mode
) && ! symbolic_memory_operand (op
, mode
))
654 sparc_operand (op
, mode
)
656 enum machine_mode mode
;
658 if (register_operand (op
, mode
))
660 if (GET_CODE (op
) == CONST_INT
)
661 return SMALL_INT (op
);
662 if (GET_MODE (op
) != mode
)
664 if (GET_CODE (op
) == SUBREG
)
665 op
= SUBREG_REG (op
);
666 if (GET_CODE (op
) != MEM
)
670 if (GET_CODE (op
) == LO_SUM
)
671 return (GET_CODE (XEXP (op
, 0)) == REG
672 && symbolic_operand (XEXP (op
, 1), Pmode
));
673 return memory_address_p (mode
, op
);
677 move_operand (op
, mode
)
679 enum machine_mode mode
;
681 if (mode
== DImode
&& arith_double_operand (op
, mode
))
683 if (register_operand (op
, mode
))
685 if (GET_CODE (op
) == CONST_INT
)
686 return SMALL_INT (op
) || SPARC_SETHI_P (INTVAL (op
));
688 if (GET_MODE (op
) != mode
)
690 if (GET_CODE (op
) == SUBREG
)
691 op
= SUBREG_REG (op
);
692 if (GET_CODE (op
) != MEM
)
695 if (GET_CODE (op
) == LO_SUM
)
696 return (register_operand (XEXP (op
, 0), Pmode
)
697 && CONSTANT_P (XEXP (op
, 1)));
698 return memory_address_p (mode
, op
);
702 splittable_symbolic_memory_operand (op
, mode
)
704 enum machine_mode mode
;
706 if (GET_CODE (op
) != MEM
)
708 if (! symbolic_operand (XEXP (op
, 0), Pmode
))
714 splittable_immediate_memory_operand (op
, mode
)
716 enum machine_mode mode
;
718 if (GET_CODE (op
) != MEM
)
720 if (! immediate_operand (XEXP (op
, 0), Pmode
))
725 /* Return truth value of whether OP is EQ or NE. */
730 enum machine_mode mode
;
732 return (GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
);
735 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
736 or LTU for non-floating-point. We handle those specially. */
739 normal_comp_operator (op
, mode
)
741 enum machine_mode mode
;
743 enum rtx_code code
= GET_CODE (op
);
745 if (GET_RTX_CLASS (code
) != '<')
748 if (GET_MODE (XEXP (op
, 0)) == CCFPmode
749 || GET_MODE (XEXP (op
, 0)) == CCFPEmode
)
752 return (code
!= NE
&& code
!= EQ
&& code
!= GEU
&& code
!= LTU
);
755 /* Return 1 if this is a comparison operator. This allows the use of
756 MATCH_OPERATOR to recognize all the branch insns. */
759 noov_compare_op (op
, mode
)
761 enum machine_mode mode
;
763 enum rtx_code code
= GET_CODE (op
);
765 if (GET_RTX_CLASS (code
) != '<')
768 if (GET_MODE (XEXP (op
, 0)) == CC_NOOVmode
)
769 /* These are the only branches which work with CC_NOOVmode. */
770 return (code
== EQ
|| code
== NE
|| code
== GE
|| code
== LT
);
774 /* Nonzero if OP is a comparison operator suitable for use in v9
775 conditional move or branch on register contents instructions. */
778 v9_regcmp_op (op
, mode
)
780 enum machine_mode mode
;
782 enum rtx_code code
= GET_CODE (op
);
784 if (GET_RTX_CLASS (code
) != '<')
787 return v9_regcmp_p (code
);
790 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
795 enum machine_mode mode
;
797 return GET_CODE (op
) == SIGN_EXTEND
|| GET_CODE (op
) == ZERO_EXTEND
;
800 /* Return nonzero if OP is an operator of mode MODE which can set
801 the condition codes explicitly. We do not include PLUS and MINUS
802 because these require CC_NOOVmode, which we handle explicitly. */
805 cc_arithop (op
, mode
)
807 enum machine_mode mode
;
809 if (GET_CODE (op
) == AND
810 || GET_CODE (op
) == IOR
811 || GET_CODE (op
) == XOR
)
817 /* Return nonzero if OP is an operator of mode MODE which can bitwise
818 complement its second operand and set the condition codes explicitly. */
821 cc_arithopn (op
, mode
)
823 enum machine_mode mode
;
825 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
826 and (xor ... (not ...)) to (not (xor ...)). */
827 return (GET_CODE (op
) == AND
828 || GET_CODE (op
) == IOR
);
831 /* Return true if OP is a register, or is a CONST_INT that can fit in a
832 signed 13 bit immediate field. This is an acceptable SImode operand for
833 most 3 address instructions. */
836 arith_operand (op
, mode
)
838 enum machine_mode mode
;
840 return (register_operand (op
, mode
)
841 || (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
)));
844 /* Return true if OP is a register, or is a CONST_INT that can fit in a
845 signed 11 bit immediate field. This is an acceptable SImode operand for
846 the movcc instructions. */
849 arith11_operand (op
, mode
)
851 enum machine_mode mode
;
853 return (register_operand (op
, mode
)
854 || (GET_CODE (op
) == CONST_INT
&& SPARC_SIMM11_P (INTVAL (op
))));
857 /* Return true if OP is a register, or is a CONST_INT that can fit in a
858 signed 10 bit immediate field. This is an acceptable SImode operand for
859 the movrcc instructions. */
862 arith10_operand (op
, mode
)
864 enum machine_mode mode
;
866 return (register_operand (op
, mode
)
867 || (GET_CODE (op
) == CONST_INT
&& SPARC_SIMM10_P (INTVAL (op
))));
870 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
871 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
873 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
874 can fit in a 13 bit immediate field. This is an acceptable DImode operand
875 for most 3 address instructions. */
878 arith_double_operand (op
, mode
)
880 enum machine_mode mode
;
882 return (register_operand (op
, mode
)
883 || (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
885 && GET_CODE (op
) == CONST_DOUBLE
886 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x1000) < 0x2000
887 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_HIGH (op
) + 0x1000) < 0x2000)
889 && GET_CODE (op
) == CONST_DOUBLE
890 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x1000) < 0x2000
891 && ((CONST_DOUBLE_HIGH (op
) == -1
892 && (CONST_DOUBLE_LOW (op
) & 0x1000) == 0x1000)
893 || (CONST_DOUBLE_HIGH (op
) == 0
894 && (CONST_DOUBLE_LOW (op
) & 0x1000) == 0))));
897 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
898 can fit in an 11 bit immediate field. This is an acceptable DImode
899 operand for the movcc instructions. */
900 /* ??? Replace with arith11_operand? */
903 arith11_double_operand (op
, mode
)
905 enum machine_mode mode
;
907 return (register_operand (op
, mode
)
908 || (GET_CODE (op
) == CONST_DOUBLE
909 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
910 && (unsigned HOST_WIDE_INT
) (CONST_DOUBLE_LOW (op
) + 0x400) < 0x800
911 && ((CONST_DOUBLE_HIGH (op
) == -1
912 && (CONST_DOUBLE_LOW (op
) & 0x400) == 0x400)
913 || (CONST_DOUBLE_HIGH (op
) == 0
914 && (CONST_DOUBLE_LOW (op
) & 0x400) == 0)))
915 || (GET_CODE (op
) == CONST_INT
916 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
917 && (unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x400) < 0x800));
920 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
921 can fit in an 10 bit immediate field. This is an acceptable DImode
922 operand for the movrcc instructions. */
923 /* ??? Replace with arith10_operand? */
926 arith10_double_operand (op
, mode
)
928 enum machine_mode mode
;
930 return (register_operand (op
, mode
)
931 || (GET_CODE (op
) == CONST_DOUBLE
932 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
933 && (unsigned) (CONST_DOUBLE_LOW (op
) + 0x200) < 0x400
934 && ((CONST_DOUBLE_HIGH (op
) == -1
935 && (CONST_DOUBLE_LOW (op
) & 0x200) == 0x200)
936 || (CONST_DOUBLE_HIGH (op
) == 0
937 && (CONST_DOUBLE_LOW (op
) & 0x200) == 0)))
938 || (GET_CODE (op
) == CONST_INT
939 && (GET_MODE (op
) == mode
|| GET_MODE (op
) == VOIDmode
)
940 && (unsigned HOST_WIDE_INT
) (INTVAL (op
) + 0x200) < 0x400));
943 /* Return truth value of whether OP is a integer which fits the
944 range constraining immediate operands in most three-address insns,
945 which have a 13 bit immediate field. */
950 enum machine_mode mode
;
952 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
955 /* Recognize operand values for the umul instruction. That instruction sign
956 extends immediate values just like all other sparc instructions, but
957 interprets the extended result as an unsigned number. */
960 uns_small_int (op
, mode
)
962 enum machine_mode mode
;
964 #if HOST_BITS_PER_WIDE_INT > 32
965 /* All allowed constants will fit a CONST_INT. */
966 return (GET_CODE (op
) == CONST_INT
967 && ((INTVAL (op
) >= 0 && INTVAL (op
) < 0x1000)
968 || (INTVAL (op
) >= 0xFFFFF000 && INTVAL (op
) < 0x100000000L
)));
970 return ((GET_CODE (op
) == CONST_INT
&& (unsigned) INTVAL (op
) < 0x1000)
971 || (GET_CODE (op
) == CONST_DOUBLE
972 && CONST_DOUBLE_HIGH (op
) == 0
973 && (unsigned) CONST_DOUBLE_LOW (op
) - 0xFFFFF000 < 0x1000));
978 uns_arith_operand (op
, mode
)
980 enum machine_mode mode
;
982 return register_operand (op
, mode
) || uns_small_int (op
, mode
);
985 /* Return truth value of statement that OP is a call-clobbered register. */
987 clobbered_register (op
, mode
)
989 enum machine_mode mode
;
991 return (GET_CODE (op
) == REG
&& call_used_regs
[REGNO (op
)]);
994 /* X and Y are two things to compare using CODE. Emit the compare insn and
995 return the rtx for the cc reg in the proper mode. */
998 gen_compare_reg (code
, x
, y
)
1002 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
1005 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
1006 fcc regs (cse can't tell they're really call clobbered regs and will
1007 remove a duplicate comparison even if there is an intervening function
1008 call - it will then try to reload the cc reg via an int reg which is why
1009 we need the movcc patterns). It is possible to provide the movcc
1010 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
1011 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
1012 to tell cse that CCFPE mode registers (even pseudos) are call
1015 /* ??? This is an experiment. Rather than making changes to cse which may
1016 or may not be easy/clean, we do our own cse. This is possible because
1017 we will generate hard registers. Cse knows they're call clobbered (it
1018 doesn't know the same thing about pseudos). If we guess wrong, no big
1019 deal, but if we win, great! */
1021 if (TARGET_V9
&& GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
1022 #if 1 /* experiment */
1025 /* We cycle through the registers to ensure they're all exercised. */
1026 static int next_fcc_reg
= 0;
1027 /* Previous x,y for each fcc reg. */
1028 static rtx prev_args
[4][2];
1030 /* Scan prev_args for x,y. */
1031 for (reg
= 0; reg
< 4; reg
++)
1032 if (prev_args
[reg
][0] == x
&& prev_args
[reg
][1] == y
)
1037 prev_args
[reg
][0] = x
;
1038 prev_args
[reg
][1] = y
;
1039 next_fcc_reg
= (next_fcc_reg
+ 1) & 3;
1041 cc_reg
= gen_rtx_REG (mode
, reg
+ SPARC_FIRST_V9_FCC_REG
);
1044 cc_reg
= gen_reg_rtx (mode
);
1045 #endif /* ! experiment */
1046 else if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
1047 cc_reg
= gen_rtx_REG (mode
, SPARC_FCC_REG
);
1049 cc_reg
= gen_rtx_REG (mode
, SPARC_ICC_REG
);
1051 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
1052 gen_rtx_COMPARE (mode
, x
, y
)));
1057 /* This function is used for v9 only.
1058 CODE is the code for an Scc's comparison.
1059 OPERANDS[0] is the target of the Scc insn.
1060 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
1061 been generated yet).
1063 This function is needed to turn
1066 (gt (reg:CCX 100 %icc)
1070 (gt:DI (reg:CCX 100 %icc)
1073 IE: The instruction recognizer needs to see the mode of the comparison to
1074 find the right instruction. We could use "gt:DI" right in the
1075 define_expand, but leaving it out allows us to handle DI, SI, etc.
1077 We refer to the global sparc compare operands sparc_compare_op0 and
1078 sparc_compare_op1. */
1081 gen_v9_scc (compare_code
, operands
)
1082 enum rtx_code compare_code
;
1083 register rtx
*operands
;
1088 && (GET_MODE (sparc_compare_op0
) == DImode
1089 || GET_MODE (operands
[0]) == DImode
))
1092 /* Handle the case where operands[0] == sparc_compare_op0.
1093 We "early clobber" the result. */
1094 if (REGNO (operands
[0]) == REGNO (sparc_compare_op0
))
1096 op0
= gen_reg_rtx (GET_MODE (sparc_compare_op0
));
1097 emit_move_insn (op0
, sparc_compare_op0
);
1100 op0
= sparc_compare_op0
;
1101 /* For consistency in the following. */
1102 op1
= sparc_compare_op1
;
1104 /* Try to use the movrCC insns. */
1106 && GET_MODE_CLASS (GET_MODE (op0
)) == MODE_INT
1107 && op1
== const0_rtx
1108 && v9_regcmp_p (compare_code
))
1110 /* Special case for op0 != 0. This can be done with one instruction if
1111 operands[0] == sparc_compare_op0. We don't assume they are equal
1114 if (compare_code
== NE
1115 && GET_MODE (operands
[0]) == DImode
1116 && GET_MODE (op0
) == DImode
)
1118 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], op0
));
1119 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
1120 gen_rtx_IF_THEN_ELSE
1121 (DImode
, gen_rtx (compare_code
, DImode
,
1123 const1_rtx
, operands
[0])));
1127 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], const0_rtx
));
1128 if (GET_MODE (op0
) != DImode
)
1130 temp
= gen_reg_rtx (DImode
);
1131 convert_move (temp
, op0
, 0);
1135 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
1136 gen_rtx_IF_THEN_ELSE
1137 (GET_MODE (operands
[0]),
1138 gen_rtx (compare_code
, DImode
,
1140 const1_rtx
, operands
[0])));
1145 operands
[1] = gen_compare_reg (compare_code
, op0
, op1
);
1147 switch (GET_MODE (operands
[1]))
1157 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0], const0_rtx
));
1158 emit_insn (gen_rtx_SET (VOIDmode
, operands
[0],
1159 gen_rtx_IF_THEN_ELSE
1160 (GET_MODE (operands
[0]),
1161 gen_rtx (compare_code
, GET_MODE (operands
[1]),
1162 operands
[1], const0_rtx
),
1163 const1_rtx
, operands
[0])));
1168 /* Emit a conditional jump insn for the v9 architecture using comparison code
1169 CODE and jump target LABEL.
1170 This function exists to take advantage of the v9 brxx insns. */
1173 emit_v9_brxx_insn (code
, op0
, label
)
1177 emit_jump_insn (gen_rtx_SET (VOIDmode
,
1179 gen_rtx_IF_THEN_ELSE
1181 gen_rtx (code
, GET_MODE (op0
),
1183 gen_rtx_LABEL_REF (VOIDmode
, label
), pc_rtx
)));
1186 /* Return nonzero if a return peephole merging return with
1187 setting of output register is ok. */
1189 leaf_return_peephole_ok ()
1191 return (actual_fsize
== 0);
1194 /* Return nonzero if TRIAL can go into the function epilogue's
1195 delay slot. SLOT is the slot we are trying to fill. */
1198 eligible_for_epilogue_delay (trial
, slot
)
1207 if (GET_CODE (trial
) != INSN
|| GET_CODE (PATTERN (trial
)) != SET
)
1210 if (get_attr_length (trial
) != 1)
1213 /* If %g0 is live, there are lots of things we can't handle.
1214 Rather than trying to find them all now, let's punt and only
1215 optimize things as necessary. */
1219 /* In the case of a true leaf function, anything can go into the delay slot.
1220 A delay slot only exists however if the frame size is zero, otherwise
1221 we will put an insn to adjust the stack after the return. */
1224 if (leaf_return_peephole_ok ())
1225 return ((get_attr_in_uncond_branch_delay (trial
)
1226 == IN_BRANCH_DELAY_TRUE
));
1230 /* If only trivial `restore' insns work, nothing can go in the
1232 else if (TARGET_BROKEN_SAVERESTORE
)
1235 pat
= PATTERN (trial
);
1237 /* Otherwise, only operations which can be done in tandem with
1238 a `restore' insn can go into the delay slot. */
1239 if (GET_CODE (SET_DEST (pat
)) != REG
1240 || REGNO (SET_DEST (pat
)) >= 32
1241 || REGNO (SET_DEST (pat
)) < 24)
1244 /* The set of insns matched here must agree precisely with the set of
1245 patterns paired with a RETURN in sparc.md. */
1247 src
= SET_SRC (pat
);
1249 /* This matches "*return_[qhs]". */
1250 if (arith_operand (src
, GET_MODE (src
)))
1251 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (SImode
);
1253 /* This matches "*return_di". */
1254 else if (arith_double_operand (src
, GET_MODE (src
)))
1255 return GET_MODE_SIZE (GET_MODE (src
)) <= GET_MODE_SIZE (DImode
);
1257 /* This matches "*return_sf_no_fpu". */
1258 else if (! TARGET_FPU
&& restore_operand (SET_DEST (pat
), SFmode
)
1259 && register_operand (src
, SFmode
))
1262 /* This matches "*return_addsi". */
1263 else if (GET_CODE (src
) == PLUS
1264 && arith_operand (XEXP (src
, 0), SImode
)
1265 && arith_operand (XEXP (src
, 1), SImode
)
1266 && (register_operand (XEXP (src
, 0), SImode
)
1267 || register_operand (XEXP (src
, 1), SImode
)))
1270 /* This matches "*return_adddi". */
1271 else if (GET_CODE (src
) == PLUS
1272 && arith_double_operand (XEXP (src
, 0), DImode
)
1273 && arith_double_operand (XEXP (src
, 1), DImode
)
1274 && (register_operand (XEXP (src
, 0), DImode
)
1275 || register_operand (XEXP (src
, 1), DImode
)))
1278 /* This matches "*return_subsi". */
1279 else if (GET_CODE (src
) == MINUS
1280 && register_operand (XEXP (src
, 0), SImode
)
1281 && small_int (XEXP (src
, 1), VOIDmode
)
1282 && INTVAL (XEXP (src
, 1)) != -4096)
1289 short_branch (uid1
, uid2
)
1292 unsigned int delta
= insn_addresses
[uid1
] - insn_addresses
[uid2
];
1293 if (delta
+ 1024 < 2048)
1295 /* warning ("long branch, distance %d", delta); */
1299 /* Return non-zero if REG is not used after INSN.
1300 We assume REG is a reload reg, and therefore does
1301 not live past labels or calls or jumps. */
1303 reg_unused_after (reg
, insn
)
1307 enum rtx_code code
, prev_code
= UNKNOWN
;
1309 while (insn
= NEXT_INSN (insn
))
1311 if (prev_code
== CALL_INSN
&& call_used_regs
[REGNO (reg
)])
1314 code
= GET_CODE (insn
);
1315 if (GET_CODE (insn
) == CODE_LABEL
)
1318 if (GET_RTX_CLASS (code
) == 'i')
1320 rtx set
= single_set (insn
);
1321 int in_src
= set
&& reg_overlap_mentioned_p (reg
, SET_SRC (set
));
1324 if (set
&& reg_overlap_mentioned_p (reg
, SET_DEST (set
)))
1326 if (set
== 0 && reg_overlap_mentioned_p (reg
, PATTERN (insn
)))
1334 /* The table we use to reference PIC data. */
1335 static rtx global_offset_table
;
1337 /* Ensure that we are not using patterns that are not OK with PIC. */
1346 if (GET_CODE (recog_operand
[i
]) == SYMBOL_REF
1347 || (GET_CODE (recog_operand
[i
]) == CONST
1348 && ! (GET_CODE (XEXP (recog_operand
[i
], 0)) == MINUS
1349 && (XEXP (XEXP (recog_operand
[i
], 0), 0)
1350 == global_offset_table
)
1351 && (GET_CODE (XEXP (XEXP (recog_operand
[i
], 0), 1))
1360 /* Return true if X is an address which needs a temporary register when
1361 reloaded while generating PIC code. */
1364 pic_address_needs_scratch (x
)
1367 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
1368 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
1369 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
1370 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1371 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
1377 /* Legitimize PIC addresses. If the address is already position-independent,
1378 we return ORIG. Newly generated position-independent addresses go into a
1379 reg. This is REG if non zero, otherwise we allocate register(s) as
1383 legitimize_pic_address (orig
, mode
, reg
)
1385 enum machine_mode mode
;
1388 if (GET_CODE (orig
) == SYMBOL_REF
)
1390 rtx pic_ref
, address
;
1395 if (reload_in_progress
|| reload_completed
)
1398 reg
= gen_reg_rtx (Pmode
);
1403 /* If not during reload, allocate another temp reg here for loading
1404 in the address, so that these instructions can be optimized
1406 rtx temp_reg
= ((reload_in_progress
|| reload_completed
)
1407 ? reg
: gen_reg_rtx (Pmode
));
1409 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
1410 won't get confused into thinking that these two instructions
1411 are loading in the true address of the symbol. If in the
1412 future a PIC rtx exists, that should be used instead. */
1413 emit_insn (gen_pic_sethi_si (temp_reg
, orig
));
1414 emit_insn (gen_pic_lo_sum_si (temp_reg
, temp_reg
, orig
));
1421 pic_ref
= gen_rtx_MEM (Pmode
,
1422 gen_rtx_PLUS (Pmode
,
1423 pic_offset_table_rtx
, address
));
1425 current_function_uses_pic_offset_table
= 1;
1426 RTX_UNCHANGING_P (pic_ref
) = 1;
1427 insn
= emit_move_insn (reg
, pic_ref
);
1428 /* Put a REG_EQUAL note on this insn, so that it can be optimized
1430 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
1434 else if (GET_CODE (orig
) == CONST
)
1438 if (GET_CODE (XEXP (orig
, 0)) == PLUS
1439 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
1444 if (reload_in_progress
|| reload_completed
)
1447 reg
= gen_reg_rtx (Pmode
);
1450 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
1452 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
1453 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
1454 base
== reg
? 0 : reg
);
1459 if (GET_CODE (offset
) == CONST_INT
)
1461 if (SMALL_INT (offset
))
1462 return plus_constant_for_output (base
, INTVAL (offset
));
1463 else if (! reload_in_progress
&& ! reload_completed
)
1464 offset
= force_reg (Pmode
, offset
);
1466 /* If we reach here, then something is seriously wrong. */
1469 return gen_rtx_PLUS (Pmode
, base
, offset
);
1471 else if (GET_CODE (orig
) == LABEL_REF
)
1472 /* ??? Why do we do this? */
1473 current_function_uses_pic_offset_table
= 1;
1478 /* Set up PIC-specific rtl. This should not cause any insns
1486 /* Return the RTX for insns to set the PIC register. */
1497 /* If -O0, show the PIC register remains live before this. */
1499 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
1501 l1
= gen_label_rtx ();
1504 = gen_rtx_CONST (Pmode
,
1506 (Pmode
, global_offset_table
,
1507 gen_rtx_CONST (Pmode
,
1509 (Pmode
, gen_rtx_LABEL_REF (VOIDmode
, l1
),
1512 /* sparc64: the RDPC instruction doesn't pair, and puts 4 bubbles in the
1513 pipe to boot. So don't use it here, especially when we're
1514 doing a save anyway because of %l7. */
1516 l2
= gen_label_rtx ();
1519 /* Iff we are doing delay branch optimization, slot the sethi up
1520 here so that it will fill the delay slot of the call. */
1521 if (flag_delayed_branch
)
1522 emit_insn (gen_rtx_SET (VOIDmode
, pic_offset_table_rtx
,
1523 gen_rtx_HIGH (Pmode
, pic_pc_rtx
)));
1525 /* Note that we pun calls and jumps here! */
1526 emit_jump_insn (gen_get_pc_via_call (l2
, l1
));
1530 if (!flag_delayed_branch
)
1531 emit_insn (gen_rtx_SET (VOIDmode
, pic_offset_table_rtx
,
1532 gen_rtx_HIGH (Pmode
, pic_pc_rtx
)));
1534 emit_insn (gen_rtx_SET (VOIDmode
,
1535 pic_offset_table_rtx
,
1536 gen_rtx_LO_SUM (Pmode
,
1537 pic_offset_table_rtx
, pic_pc_rtx
)));
1538 emit_insn (gen_rtx_SET (VOIDmode
,
1539 pic_offset_table_rtx
,
1540 gen_rtx_PLUS (Pmode
,
1541 pic_offset_table_rtx
,
1542 gen_rtx_REG (Pmode
, 15))));
1544 /* emit_insn (gen_rtx_ASM_INPUT (VOIDmode, "!#PROLOGUE# 1")); */
1545 LABEL_PRESERVE_P (l1
) = 1;
1546 LABEL_PRESERVE_P (l2
) = 1;
1548 seq
= gen_sequence ();
1554 /* Emit special PIC prologues and epilogues. */
1559 /* Labels to get the PC in the prologue of this function. */
1560 int orig_flag_pic
= flag_pic
;
1563 if (current_function_uses_pic_offset_table
== 0)
1569 /* Initialize every time through, since we can't easily
1570 know this to be permanent. */
1571 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
1574 emit_insn_after (pic_setup_code (), get_insns ());
1576 /* Insert the code in each nonlocal goto receiver. */
1577 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
1578 if (GET_CODE (insn
) == INSN
&& GET_CODE (PATTERN (insn
)) == UNSPEC_VOLATILE
1579 && XINT (PATTERN (insn
), 1) == 4)
1580 emit_insn_after (pic_setup_code (), insn
);
1582 flag_pic
= orig_flag_pic
;
1584 /* Need to emit this whether or not we obey regdecls,
1585 since setjmp/longjmp can cause life info to screw up.
1586 ??? In the case where we don't obey regdecls, this is not sufficient
1587 since we may not fall out the bottom. */
1588 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
1591 /* Emit insns to move operands[1] into operands[0].
1593 Return 1 if we have written out everything that needs to be done to
1594 do the move. Otherwise, return 0 and the caller will emit the move
1598 emit_move_sequence (operands
, mode
)
1600 enum machine_mode mode
;
1602 register rtx operand0
= operands
[0];
1603 register rtx operand1
= operands
[1];
1605 if (CONSTANT_P (operand1
) && flag_pic
1606 && pic_address_needs_scratch (operand1
))
1607 operands
[1] = operand1
= legitimize_pic_address (operand1
, mode
, 0);
1609 /* Handle most common case first: storing into a register. */
1610 if (register_operand (operand0
, mode
))
1612 if (register_operand (operand1
, mode
)
1613 || (GET_CODE (operand1
) == CONST_INT
&& SMALL_INT (operand1
))
1614 || (GET_CODE (operand1
) == CONST_DOUBLE
1615 && arith_double_operand (operand1
, DImode
))
1616 || (GET_CODE (operand1
) == HIGH
&& GET_MODE (operand1
) != DImode
)
1617 /* Only `general_operands' can come here, so MEM is ok. */
1618 || GET_CODE (operand1
) == MEM
)
1620 /* Run this case quickly. */
1621 emit_insn (gen_rtx_SET (VOIDmode
, operand0
, operand1
));
1625 else if (GET_CODE (operand0
) == MEM
)
1627 if (register_operand (operand1
, mode
)
1628 || (operand1
== const0_rtx
&& ! TARGET_LIVE_G0
))
1630 /* Run this case quickly. */
1631 emit_insn (gen_rtx_SET (VOIDmode
, operand0
, operand1
));
1634 if (! reload_in_progress
)
1636 operands
[0] = validize_mem (operand0
);
1637 operands
[1] = operand1
= force_reg (mode
, operand1
);
1641 if (GET_CODE (operand1
) == LABEL_REF
1642 && mode
== SImode
&& flag_pic
)
1646 emit_insn (gen_move_pic_label_si (operand0
, operand1
));
1649 /* Non-pic LABEL_REF's in sparc64 are expensive to do the normal way,
1650 so always use special code. */
1651 else if (GET_CODE (operand1
) == LABEL_REF
1654 if (! TARGET_ARCH64
)
1656 emit_insn (gen_move_label_di (operand0
, operand1
));
1659 /* DImode HIGH values in sparc64 need a clobber added. */
1660 else if (TARGET_ARCH64
1661 && GET_CODE (operand1
) == HIGH
&& GET_MODE (operand1
) == DImode
)
1663 emit_insn (gen_sethi_di_sp64 (operand0
, XEXP (operand1
, 0)));
1666 /* Simplify the source if we need to. */
1667 else if (GET_CODE (operand1
) != HIGH
&& immediate_operand (operand1
, mode
))
1669 if (flag_pic
&& symbolic_operand (operand1
, mode
))
1671 rtx temp_reg
= reload_in_progress
? operand0
: 0;
1673 operands
[1] = legitimize_pic_address (operand1
, mode
, temp_reg
);
1675 else if (GET_CODE (operand1
) == CONST_INT
1676 ? (! SMALL_INT (operand1
)
1677 && ! SPARC_SETHI_P (INTVAL (operand1
)))
1678 : GET_CODE (operand1
) == CONST_DOUBLE
1679 ? ! arith_double_operand (operand1
, DImode
)
1682 /* For DImode values, temp must be operand0 because of the way
1683 HI and LO_SUM work. The LO_SUM operator only copies half of
1684 the LSW from the dest of the HI operator. If the LO_SUM dest is
1685 not the same as the HI dest, then the MSW of the LO_SUM dest will
1688 ??? The real problem here is that the ...(HI:DImode pattern emits
1689 multiple instructions, and the ...(LO_SUM:DImode pattern emits
1690 one instruction. This fails, because the compiler assumes that
1691 LO_SUM copies all bits of the first operand to its dest. Better
1692 would be to have the HI pattern emit one instruction and the
1693 LO_SUM pattern multiple instructions. Even better would be
1694 to use four rtl insns. */
1695 rtx temp
= ((reload_in_progress
|| mode
== DImode
)
1696 ? operand0
: gen_reg_rtx (mode
));
1698 if (TARGET_ARCH64
&& mode
== DImode
)
1699 emit_insn (gen_sethi_di_sp64 (temp
, operand1
));
1701 emit_insn (gen_rtx_SET (VOIDmode
, temp
,
1702 gen_rtx_HIGH (mode
, operand1
)));
1704 if (GET_CODE (operand1
) == CONST_INT
)
1705 operand1
= GEN_INT (INTVAL (operand1
) & 0xffffffff);
1706 else if (GET_CODE (operand1
) == CONST_DOUBLE
)
1707 operand1
= GEN_INT (CONST_DOUBLE_LOW (operand1
) & 0xffffffff);
1708 operands
[1] = gen_rtx_LO_SUM (mode
, temp
, operand1
);
1712 /* Now have insn-emit do whatever it normally does. */
1716 /* Return the best assembler insn template
1717 for moving operands[1] into operands[0] as a 4 byte quantity.
1719 This isn't intended to be very smart. It is up to the caller to
1720 choose the best way to do things.
1722 Note that OPERANDS may be modified to suit the returned string. */
1725 singlemove_string (operands
)
1728 if (GET_CODE (operands
[0]) == MEM
)
1730 if (GET_CODE (operands
[1]) != MEM
)
1735 else if (GET_CODE (operands
[1]) == MEM
)
1737 else if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1742 /* Must be SFmode, otherwise this doesn't make sense. */
1743 if (GET_MODE (operands
[1]) != SFmode
)
1746 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
1747 REAL_VALUE_TO_TARGET_SINGLE (r
, i
);
1748 operands
[1] = GEN_INT (i
);
1750 if (CONST_OK_FOR_LETTER_P (i
, 'I'))
1752 else if ((i
& 0x000003FF) != 0)
1753 return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0";
1755 return "sethi %%hi(%a1),%0";
1757 else if (GET_CODE (operands
[1]) == CONST_INT
1758 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands
[1]), 'I'))
1760 HOST_WIDE_INT i
= INTVAL (operands
[1]);
1762 /* If all low order 10 bits are clear, then we only need a single
1763 sethi insn to load the constant. */
1764 /* FIXME: Use SETHI_P. */
1765 if ((i
& 0x000003FF) != 0)
1766 return "sethi %%hi(%a1),%0\n\tor %0,%%lo(%a1),%0";
1768 return "sethi %%hi(%a1),%0";
1770 /* Operand 1 must be a register, or a 'I' type CONST_INT. */
1774 /* Return the best assembler insn template
1775 for moving operands[1] into operands[0] as an 8 byte quantity.
1777 This isn't intended to be very smart. It is up to the caller to
1778 choose the best way to do things.
1780 Note that OPERANDS may be modified to suit the returned string. */
1783 doublemove_string (operands
)
1786 rtx op0
= operands
[0], op1
= operands
[1];
1788 if (GET_CODE (op0
) == MEM
)
1790 if (GET_CODE (op1
) == REG
)
1794 return TARGET_ARCH64
? "stx %1,%0" : "std %1,%0";
1797 && (op1
== const0_rtx
1798 || (GET_MODE (op1
) != VOIDmode
1799 && op1
== CONST0_RTX (GET_MODE (op1
)))))
1800 return "stx %r1,%0";
1803 else if (GET_CODE (op1
) == MEM
)
1805 if (GET_CODE (op0
) != REG
)
1809 return TARGET_ARCH64
? "ldx %1,%0" : "ldd %1,%0";
1811 else if (GET_CODE (operands
[1]) == CONST_DOUBLE
)
1813 /* ??? Unfinished, and maybe not needed. */
1816 else if (GET_CODE (operands
[1]) == CONST_INT
1817 && ! CONST_OK_FOR_LETTER_P (INTVAL (operands
[1]), 'I'))
1819 /* ??? Unfinished, and maybe not needed. */
1822 /* Operand 1 must be a register, or a 'I' type CONST_INT. */
1826 /* Return non-zero if it is OK to assume that the given memory operand is
1827 aligned at least to a 8-byte boundary. This should only be called
1828 for memory accesses whose size is 8 bytes or larger. */
1836 register rtx offset
;
1838 if (GET_CODE (mem
) != MEM
)
1839 return 0; /* It's gotta be a MEM! */
1841 addr
= XEXP (mem
, 0);
1843 /* Now that all misaligned double parms are copied on function entry,
1844 we can assume any 64-bit object is 64-bit aligned except those which
1845 are at unaligned offsets from the stack or frame pointer. If the
1846 TARGET_UNALIGNED_DOUBLES switch is given, we do not make this
1849 /* See what register we use in the address. */
1851 if (GET_CODE (addr
) == PLUS
)
1853 if (GET_CODE (XEXP (addr
, 0)) == REG
1854 && GET_CODE (XEXP (addr
, 1)) == CONST_INT
)
1856 base
= XEXP (addr
, 0);
1857 offset
= XEXP (addr
, 1);
1860 else if (GET_CODE (addr
) == REG
)
1863 offset
= const0_rtx
;
1866 /* If it's the stack or frame pointer, check offset alignment.
1867 We can have improper alignment in the function entry code. */
1869 && (REGNO (base
) == FRAME_POINTER_REGNUM
1870 || REGNO (base
) == STACK_POINTER_REGNUM
))
1872 if (((INTVAL (offset
) - SPARC_STACK_BIAS
) & 0x7) == 0)
1875 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
1876 is true, in which case we can only assume that an access is aligned if
1877 it is to a constant address, or the address involves a LO_SUM.
1879 We used to assume an address was aligned if MEM_IN_STRUCT_P was true.
1880 That assumption was deleted so that gcc generated code can be used with
1881 memory allocators that only guarantee 4 byte alignment. */
1882 else if (! TARGET_UNALIGNED_DOUBLES
|| CONSTANT_P (addr
)
1883 || GET_CODE (addr
) == LO_SUM
)
1886 /* An obviously unaligned address. */
1890 enum optype
{ REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
};
1892 /* Output assembler code to perform a doubleword move insn
1893 with operands OPERANDS. This is very similar to the following
1894 output_move_quad function. */
1897 output_move_double (operands
)
1900 register rtx op0
= operands
[0];
1901 register rtx op1
= operands
[1];
1902 register enum optype optype0
;
1903 register enum optype optype1
;
1907 int highest_first
= 0;
1908 int no_addreg1_decrement
= 0;
1910 /* First classify both operands. */
1914 else if (offsettable_memref_p (op0
))
1916 else if (GET_CODE (op0
) == MEM
)
1923 else if (CONSTANT_P (op1
))
1925 else if (offsettable_memref_p (op1
))
1927 else if (GET_CODE (op1
) == MEM
)
1932 /* Check for the cases that the operand constraints are not
1933 supposed to allow to happen. Abort if we get one,
1934 because generating code for these cases is painful. */
1936 if (optype0
== RNDOP
|| optype1
== RNDOP
1937 || (optype0
== MEM
&& optype1
== MEM
))
1940 /* If an operand is an unoffsettable memory ref, find a register
1941 we can increment temporarily to make it refer to the second word. */
1943 if (optype0
== MEMOP
)
1944 addreg0
= find_addr_reg (XEXP (op0
, 0));
1946 if (optype1
== MEMOP
)
1947 addreg1
= find_addr_reg (XEXP (op1
, 0));
1949 /* Ok, we can do one word at a time.
1950 Set up in LATEHALF the operands to use for the
1951 high-numbered (least significant) word and in some cases alter the
1952 operands in OPERANDS to be suitable for the low-numbered word. */
1954 if (optype0
== REGOP
)
1955 latehalf
[0] = gen_rtx_REG (SImode
, REGNO (op0
) + 1);
1956 else if (optype0
== OFFSOP
)
1957 latehalf
[0] = adj_offsettable_operand (op0
, 4);
1961 if (optype1
== REGOP
)
1962 latehalf
[1] = gen_rtx_REG (SImode
, REGNO (op1
) + 1);
1963 else if (optype1
== OFFSOP
)
1964 latehalf
[1] = adj_offsettable_operand (op1
, 4);
1965 else if (optype1
== CNSTOP
)
1969 if (arith_double_operand (op1
, DImode
))
1971 operands
[1] = GEN_INT (CONST_DOUBLE_LOW (op1
));
1976 /* The only way to handle CONST_DOUBLEs or other 64 bit
1977 constants here is to use a temporary, such as is done
1978 for the V9 DImode sethi insn pattern. This is not
1979 a practical solution, so abort if we reach here.
1980 The md file should always force such constants to
1986 split_double (op1
, &operands
[1], &latehalf
[1]);
1991 /* Easy case: try moving both words at once. Check for moving between
1992 an even/odd register pair and a memory location. */
1993 if ((optype0
== REGOP
&& optype1
!= REGOP
&& optype1
!= CNSTOP
1994 && (TARGET_ARCH64
|| (REGNO (op0
) & 1) == 0))
1995 || (optype0
!= REGOP
&& optype0
!= CNSTOP
&& optype1
== REGOP
1996 && (TARGET_ARCH64
|| (REGNO (op1
) & 1) == 0)))
1998 register rtx mem
,reg
;
2000 if (optype0
== REGOP
)
2001 mem
= op1
, reg
= op0
;
2003 mem
= op0
, reg
= op1
;
2005 /* In v9, ldd can be used for word aligned addresses, so technically
2006 some of this logic is unneeded. We still avoid ldd if the address
2007 is obviously unaligned though. */
2009 if (mem_aligned_8 (mem
)
2010 /* If this is a floating point register higher than %f31,
2011 then we *must* use an aligned load, since `ld' will not accept
2012 the register number. */
2013 || (TARGET_V9
&& REGNO (reg
) >= 64))
2015 if (FP_REG_P (reg
) || ! TARGET_ARCH64
)
2016 return (mem
== op1
? "ldd %1,%0" : "std %1,%0");
2018 return (mem
== op1
? "ldx %1,%0" : "stx %1,%0");
2024 if (optype0
== REGOP
&& optype1
== REGOP
)
2027 return "fmovd %1,%0";
2033 /* If the first move would clobber the source of the second one,
2034 do them in the other order. */
2036 /* Overlapping registers. */
2037 if (optype0
== REGOP
&& optype1
== REGOP
2038 && REGNO (op0
) == REGNO (latehalf
[1]))
2041 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2042 /* Do low-numbered word. */
2043 return singlemove_string (operands
);
2045 /* Loading into a register which overlaps a register used in the address. */
2046 else if (optype0
== REGOP
&& optype1
!= REGOP
2047 && reg_overlap_mentioned_p (op0
, op1
))
2049 /* If both halves of dest are used in the src memory address,
2050 add the two regs and put them in the low reg (op0).
2051 Then it works to load latehalf first. */
2052 if (reg_mentioned_p (op0
, XEXP (op1
, 0))
2053 && reg_mentioned_p (latehalf
[0], XEXP (op1
, 0)))
2056 xops
[0] = latehalf
[0];
2058 output_asm_insn ("add %1,%0,%1", xops
);
2059 operands
[1] = gen_rtx_MEM (DImode
, op0
);
2060 latehalf
[1] = adj_offsettable_operand (operands
[1], 4);
2064 /* Only one register in the dest is used in the src memory address,
2065 and this is the first register of the dest, so we want to do
2066 the late half first here also. */
2067 else if (! reg_mentioned_p (latehalf
[0], XEXP (op1
, 0)))
2069 /* Only one register in the dest is used in the src memory address,
2070 and this is the second register of the dest, so we want to do
2071 the late half last. If addreg1 is set, and addreg1 is the same
2072 register as latehalf, then we must suppress the trailing decrement,
2073 because it would clobber the value just loaded. */
2074 else if (addreg1
&& reg_mentioned_p (addreg1
, latehalf
[0]))
2075 no_addreg1_decrement
= 1;
2078 /* Normal case: do the two words, low-numbered first.
2079 Overlap case (highest_first set): do high-numbered word first. */
2081 if (! highest_first
)
2082 output_asm_insn (singlemove_string (operands
), operands
);
2084 /* Make any unoffsettable addresses point at high-numbered word. */
2086 output_asm_insn ("add %0,0x4,%0", &addreg0
);
2088 output_asm_insn ("add %0,0x4,%0", &addreg1
);
2091 output_asm_insn (singlemove_string (latehalf
), latehalf
);
2093 /* Undo the adds we just did. */
2095 output_asm_insn ("add %0,-0x4,%0", &addreg0
);
2096 if (addreg1
&& ! no_addreg1_decrement
)
2097 output_asm_insn ("add %0,-0x4,%0", &addreg1
);
2100 output_asm_insn (singlemove_string (operands
), operands
);
2105 /* Output assembler code to perform a quadword move insn
2106 with operands OPERANDS. This is very similar to the preceding
2107 output_move_double function. */
2110 output_move_quad (operands
)
2113 register rtx op0
= operands
[0];
2114 register rtx op1
= operands
[1];
2115 register enum optype optype0
;
2116 register enum optype optype1
;
2121 /* First classify both operands. */
2125 else if (offsettable_memref_p (op0
))
2127 else if (GET_CODE (op0
) == MEM
)
2134 else if (CONSTANT_P (op1
))
2136 else if (offsettable_memref_p (op1
))
2138 else if (GET_CODE (op1
) == MEM
)
2143 /* Check for the cases that the operand constraints are not
2144 supposed to allow to happen. Abort if we get one,
2145 because generating code for these cases is painful. */
2147 if (optype0
== RNDOP
|| optype1
== RNDOP
2148 || (optype0
== MEM
&& optype1
== MEM
))
2151 /* If an operand is an unoffsettable memory ref, find a register
2152 we can increment temporarily to make it refer to the later words. */
2154 if (optype0
== MEMOP
)
2155 addreg0
= find_addr_reg (XEXP (op0
, 0));
2157 if (optype1
== MEMOP
)
2158 addreg1
= find_addr_reg (XEXP (op1
, 0));
2160 /* Ok, we can do one word at a time.
2161 Set up in wordpart the operands to use for each word of the arguments. */
2163 if (optype0
== REGOP
)
2165 wordpart
[0][0] = gen_rtx_REG (word_mode
, REGNO (op0
) + 0);
2166 wordpart
[1][0] = gen_rtx_REG (word_mode
, REGNO (op0
) + 1);
2169 wordpart
[2][0] = gen_rtx_REG (word_mode
, REGNO (op0
) + 2);
2170 wordpart
[3][0] = gen_rtx_REG (word_mode
, REGNO (op0
) + 3);
2173 else if (optype0
== OFFSOP
)
2175 wordpart
[0][0] = adj_offsettable_operand (op0
, 0);
2178 wordpart
[1][0] = adj_offsettable_operand (op0
, 4);
2179 wordpart
[2][0] = adj_offsettable_operand (op0
, 8);
2180 wordpart
[3][0] = adj_offsettable_operand (op0
, 12);
2183 wordpart
[1][0] = adj_offsettable_operand (op0
, 8);
2187 wordpart
[0][0] = op0
;
2188 wordpart
[1][0] = op0
;
2189 wordpart
[2][0] = op0
;
2190 wordpart
[3][0] = op0
;
2193 if (optype1
== REGOP
)
2195 wordpart
[0][1] = gen_rtx_REG (word_mode
, REGNO (op1
) + 0);
2196 wordpart
[1][1] = gen_rtx_REG (word_mode
, REGNO (op1
) + 1);
2199 wordpart
[2][1] = gen_rtx_REG (word_mode
, REGNO (op1
) + 2);
2200 wordpart
[3][1] = gen_rtx_REG (word_mode
, REGNO (op1
) + 3);
2203 else if (optype1
== OFFSOP
)
2205 wordpart
[0][1] = adj_offsettable_operand (op1
, 0);
2208 wordpart
[1][1] = adj_offsettable_operand (op1
, 4);
2209 wordpart
[2][1] = adj_offsettable_operand (op1
, 8);
2210 wordpart
[3][1] = adj_offsettable_operand (op1
, 12);
2213 wordpart
[1][1] = adj_offsettable_operand (op1
, 8);
2215 else if (optype1
== CNSTOP
)
2220 /* This only works for TFmode floating point constants. */
2221 if (GET_CODE (op1
) != CONST_DOUBLE
|| GET_MODE (op1
) != TFmode
)
2224 REAL_VALUE_FROM_CONST_DOUBLE (r
, op1
);
2225 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r
, l
);
2227 wordpart
[0][1] = GEN_INT (l
[0]);
2228 wordpart
[1][1] = GEN_INT (l
[1]);
2229 wordpart
[2][1] = GEN_INT (l
[2]);
2230 wordpart
[3][1] = GEN_INT (l
[3]);
2234 wordpart
[0][1] = op1
;
2235 wordpart
[1][1] = op1
;
2236 wordpart
[2][1] = op1
;
2237 wordpart
[3][1] = op1
;
2240 /* Easy case: try moving the quad as two pairs. Check for moving between
2241 an even/odd register pair and a memory location.
2242 Also handle new v9 fp regs here. */
2243 /* ??? Should also handle the case of non-offsettable addresses here.
2244 We can at least do the first pair as a ldd/std, and then do the third
2245 and fourth words individually. */
2246 if ((optype0
== REGOP
&& optype1
== OFFSOP
&& (REGNO (op0
) & 1) == 0)
2247 || (optype0
== OFFSOP
&& optype1
== REGOP
&& (REGNO (op1
) & 1) == 0))
2251 if (optype0
== REGOP
)
2252 mem
= op1
, reg
= op0
;
2254 mem
= op0
, reg
= op1
;
2256 if (mem_aligned_8 (mem
)
2257 /* If this is a floating point register higher than %f31,
2258 then we *must* use an aligned load, since `ld' will not accept
2259 the register number. */
2260 || (TARGET_V9
&& REGNO (reg
) >= SPARC_FIRST_V9_FP_REG
))
2262 if (TARGET_V9
&& FP_REG_P (reg
) && TARGET_HARD_QUAD
)
2264 if ((REGNO (reg
) & 3) != 0)
2266 /* ??? Can `mem' have an inappropriate alignment here? */
2267 return (mem
== op1
? "ldq %1,%0" : "stq %1,%0");
2269 operands
[2] = adj_offsettable_operand (mem
, 8);
2270 /* ??? In arch64 case, shouldn't we use ldd/std for fp regs. */
2272 return TARGET_ARCH64
? "ldx %1,%0;ldx %2,%R0" : "ldd %1,%0;ldd %2,%S0";
2274 return TARGET_ARCH64
? "stx %1,%0;stx %R1,%2" : "std %1,%0;std %S1,%2";
2278 /* If the first move would clobber the source of the second one,
2279 do them in the other order. */
2281 /* Overlapping registers? */
2284 if (optype0
== REGOP
&& optype1
== REGOP
2285 && (REGNO (op0
) == REGNO (wordpart
[1][3])
2286 || REGNO (op0
) == REGNO (wordpart
[1][2])
2287 || REGNO (op0
) == REGNO (wordpart
[1][1])))
2289 /* Do fourth word. */
2290 output_asm_insn (singlemove_string (wordpart
[3]), wordpart
[3]);
2291 /* Do the third word. */
2292 output_asm_insn (singlemove_string (wordpart
[2]), wordpart
[2]);
2293 /* Do the second word. */
2294 output_asm_insn (singlemove_string (wordpart
[1]), wordpart
[1]);
2295 /* Do lowest-numbered word. */
2296 output_asm_insn (singlemove_string (wordpart
[0]), wordpart
[0]);
2300 else /* TARGET_ARCH64 */
2302 if (optype0
== REGOP
&& optype1
== REGOP
2303 && REGNO (op0
) == REGNO (wordpart
[1][1]))
2305 output_asm_insn ("mov %1,%0", wordpart
[1]);
2306 output_asm_insn ("mov %1,%0", wordpart
[0]);
2311 /* Loading into a register which overlaps a register used in the address. */
2312 if (optype0
== REGOP
&& optype1
!= REGOP
2313 && reg_overlap_mentioned_p (op0
, op1
))
2315 /* ??? Not implemented yet. This is a bit complicated, because we
2316 must load which ever part overlaps the address last. If the address
2317 is a double-reg address, then there are two parts which need to
2318 be done last, which is impossible. We would need a scratch register
2323 /* Normal case: move the words in lowest to highest address order. */
2327 output_asm_insn (singlemove_string (wordpart
[0]), wordpart
[0]);
2329 /* Make any unoffsettable addresses point at the second word. */
2331 output_asm_insn ("add %0,0x4,%0", &addreg0
);
2333 output_asm_insn ("add %0,0x4,%0", &addreg1
);
2335 /* Do the second word. */
2336 output_asm_insn (singlemove_string (wordpart
[1]), wordpart
[1]);
2338 /* Make any unoffsettable addresses point at the third word. */
2340 output_asm_insn ("add %0,0x4,%0", &addreg0
);
2342 output_asm_insn ("add %0,0x4,%0", &addreg1
);
2344 /* Do the third word. */
2345 output_asm_insn (singlemove_string (wordpart
[2]), wordpart
[2]);
2347 /* Make any unoffsettable addresses point at the fourth word. */
2349 output_asm_insn ("add %0,0x4,%0", &addreg0
);
2351 output_asm_insn ("add %0,0x4,%0", &addreg1
);
2353 /* Do the fourth word. */
2354 output_asm_insn (singlemove_string (wordpart
[3]), wordpart
[3]);
2356 /* Undo the adds we just did. */
2358 output_asm_insn ("add %0,-0xc,%0", &addreg0
);
2360 output_asm_insn ("add %0,-0xc,%0", &addreg1
);
2362 else /* TARGET_ARCH64 */
2364 output_asm_insn (doublemove_string (wordpart
[0]), wordpart
[0]);
2366 /* Make any unoffsettable addresses point at the second word. */
2368 output_asm_insn ("add %0,0x8,%0", &addreg0
);
2370 output_asm_insn ("add %0,0x8,%0", &addreg1
);
2372 /* Do the second word. */
2373 output_asm_insn (doublemove_string (wordpart
[1]), wordpart
[1]);
2375 /* Undo the adds we just did. */
2377 output_asm_insn ("add %0,-0x8,%0", &addreg0
);
2379 output_asm_insn ("add %0,-0x8,%0", &addreg1
);
2385 /* Output assembler code to perform a doubleword move insn with operands
2386 OPERANDS, one of which must be a floating point register. */
2389 output_fp_move_double (operands
)
2392 if (FP_REG_P (operands
[0]))
2394 if (FP_REG_P (operands
[1]))
2397 return "fmovd %1,%0";
2399 return "fmovs %1,%0\n\tfmovs %R1,%R0";
2401 else if (GET_CODE (operands
[1]) == REG
)
2404 return output_move_double (operands
);
2406 else if (FP_REG_P (operands
[1]))
2408 if (GET_CODE (operands
[0]) == REG
)
2411 return output_move_double (operands
);
2416 /* Output assembler code to perform a quadword move insn with operands
2417 OPERANDS, one of which must be a floating point register. */
2420 output_fp_move_quad (operands
)
2423 register rtx op0
= operands
[0];
2424 register rtx op1
= operands
[1];
2430 if (TARGET_V9
&& TARGET_HARD_QUAD
)
2431 return "fmovq %1,%0";
2433 return "fmovd %1,%0\n\tfmovd %S1,%S0";
2435 return "fmovs %1,%0\n\tfmovs %R1,%R0\n\tfmovs %S1,%S0\n\tfmovs %T1,%T0";
2437 else if (GET_CODE (op1
) == REG
)
2440 return output_move_quad (operands
);
2442 else if (FP_REG_P (op1
))
2444 if (GET_CODE (op0
) == REG
)
2447 return output_move_quad (operands
);
2453 /* Return a REG that occurs in ADDR with coefficient 1.
2454 ADDR can be effectively incremented by incrementing REG. */
2457 find_addr_reg (addr
)
2460 while (GET_CODE (addr
) == PLUS
)
2462 /* We absolutely can not fudge the frame pointer here, because the
2463 frame pointer must always be 8 byte aligned. It also confuses
2465 if (GET_CODE (XEXP (addr
, 0)) == REG
2466 && REGNO (XEXP (addr
, 0)) != FRAME_POINTER_REGNUM
)
2467 addr
= XEXP (addr
, 0);
2468 else if (GET_CODE (XEXP (addr
, 1)) == REG
2469 && REGNO (XEXP (addr
, 1)) != FRAME_POINTER_REGNUM
)
2470 addr
= XEXP (addr
, 1);
2471 else if (CONSTANT_P (XEXP (addr
, 0)))
2472 addr
= XEXP (addr
, 1);
2473 else if (CONSTANT_P (XEXP (addr
, 1)))
2474 addr
= XEXP (addr
, 0);
2478 if (GET_CODE (addr
) == REG
)
2483 #if 0 /* not currently used */
2486 output_sized_memop (opname
, mode
, signedp
)
2488 enum machine_mode mode
;
2491 static char *ld_size_suffix_u
[] = { "ub", "uh", "", "?", "d" };
2492 static char *ld_size_suffix_s
[] = { "sb", "sh", "", "?", "d" };
2493 static char *st_size_suffix
[] = { "b", "h", "", "?", "d" };
2494 char **opnametab
, *modename
;
2496 if (opname
[0] == 'l')
2498 opnametab
= ld_size_suffix_s
;
2500 opnametab
= ld_size_suffix_u
;
2502 opnametab
= st_size_suffix
;
2503 modename
= opnametab
[GET_MODE_SIZE (mode
) >> 1];
2505 fprintf (asm_out_file
, "\t%s%s", opname
, modename
);
2509 output_move_with_extension (operands
)
2512 if (GET_MODE (operands
[2]) == HImode
)
2513 output_asm_insn ("sll %2,0x10,%0", operands
);
2514 else if (GET_MODE (operands
[2]) == QImode
)
2515 output_asm_insn ("sll %2,0x18,%0", operands
);
2519 #endif /* not currently used */
2522 /* ??? These are only used by the movstrsi pattern, but we get better code
2523 in general without that, because emit_block_move can do just as good a
2524 job as this function does when alignment and size are known. When they
2525 aren't known, a call to strcpy may be faster anyways, because it is
2526 likely to be carefully crafted assembly language code, and below we just
2527 do a byte-wise copy.
2529 Also, emit_block_move expands into multiple read/write RTL insns, which
2530 can then be optimized, whereas our movstrsi pattern can not be optimized
2533 /* Load the address specified by OPERANDS[3] into the register
2534 specified by OPERANDS[0].
2536 OPERANDS[3] may be the result of a sum, hence it could either be:
2541 (3) REG + REG + CONST_INT
2542 (4) REG + REG (special case of 3).
2544 Note that (3) is not a legitimate address.
2545 All cases are handled here. */
2548 output_load_address (operands
)
2553 if (CONSTANT_P (operands
[3]))
2555 output_asm_insn ("set %3,%0", operands
);
2559 if (REG_P (operands
[3]))
2561 if (REGNO (operands
[0]) != REGNO (operands
[3]))
2562 output_asm_insn ("mov %3,%0", operands
);
2566 if (GET_CODE (operands
[3]) != PLUS
)
2569 base
= XEXP (operands
[3], 0);
2570 offset
= XEXP (operands
[3], 1);
2572 if (GET_CODE (base
) == CONST_INT
)
2579 if (GET_CODE (offset
) != CONST_INT
)
2581 /* Operand is (PLUS (REG) (REG)). */
2583 offset
= const0_rtx
;
2589 operands
[7] = offset
;
2590 if (SMALL_INT (offset
))
2591 output_asm_insn ("add %6,%7,%0", operands
);
2593 output_asm_insn ("set %7,%0\n\tadd %0,%6,%0", operands
);
2595 else if (GET_CODE (base
) == PLUS
)
2597 operands
[6] = XEXP (base
, 0);
2598 operands
[7] = XEXP (base
, 1);
2599 operands
[8] = offset
;
2601 if (SMALL_INT (offset
))
2602 output_asm_insn ("add %6,%7,%0\n\tadd %0,%8,%0", operands
);
2604 output_asm_insn ("set %8,%0\n\tadd %0,%6,%0\n\tadd %0,%7,%0", operands
);
2610 /* Output code to place a size count SIZE in register REG.
2611 ALIGN is the size of the unit of transfer.
2613 Because block moves are pipelined, we don't include the
2614 first element in the transfer of SIZE to REG. */
2617 output_size_for_block_move (size
, reg
, align
)
2624 xoperands
[1] = size
;
2625 xoperands
[2] = align
;
2626 if (GET_CODE (size
) == REG
)
2627 output_asm_insn ("sub %1,%2,%0", xoperands
);
2630 xoperands
[1] = GEN_INT (INTVAL (size
) - INTVAL (align
));
2631 output_asm_insn ("set %1,%0", xoperands
);
2635 /* Emit code to perform a block move.
2637 OPERANDS[0] is the destination.
2638 OPERANDS[1] is the source.
2639 OPERANDS[2] is the size.
2640 OPERANDS[3] is the alignment safe to use.
2641 OPERANDS[4] is a register we can safely clobber as a temp. */
2644 output_block_move (operands
)
2647 /* A vector for our computed operands. Note that load_output_address
2648 makes use of (and can clobber) up to the 8th element of this vector. */
2651 static int movstrsi_label
= 0;
2653 rtx temp1
= operands
[4];
2654 rtx sizertx
= operands
[2];
2655 rtx alignrtx
= operands
[3];
2656 int align
= INTVAL (alignrtx
);
2657 char label3
[30], label5
[30];
2659 xoperands
[0] = operands
[0];
2660 xoperands
[1] = operands
[1];
2661 xoperands
[2] = temp1
;
2663 /* We can't move more than this many bytes at a time because we have only
2664 one register, %g1, to move them through. */
2665 if (align
> UNITS_PER_WORD
)
2667 align
= UNITS_PER_WORD
;
2668 alignrtx
= GEN_INT (UNITS_PER_WORD
);
2671 /* We consider 8 ld/st pairs, for a total of 16 inline insns to be
2672 reasonable here. (Actually will emit a maximum of 18 inline insns for
2673 the case of size == 31 and align == 4). */
2675 if (GET_CODE (sizertx
) == CONST_INT
&& (INTVAL (sizertx
) / align
) <= 8
2676 && memory_address_p (QImode
, plus_constant_for_output (xoperands
[0],
2678 && memory_address_p (QImode
, plus_constant_for_output (xoperands
[1],
2681 int size
= INTVAL (sizertx
);
2684 /* We will store different integers into this particular RTX. */
2685 xoperands
[2] = rtx_alloc (CONST_INT
);
2686 PUT_MODE (xoperands
[2], VOIDmode
);
2688 /* This case is currently not handled. Abort instead of generating
2690 if (align
> UNITS_PER_WORD
)
2693 if (TARGET_ARCH64
&& align
>= 8)
2695 for (i
= (size
>> 3) - 1; i
>= 0; i
--)
2697 INTVAL (xoperands
[2]) = (i
<< 3) + offset
;
2698 output_asm_insn ("ldx [%a1+%2],%%g1\n\tstx %%g1,[%a0+%2]",
2701 offset
+= (size
& ~0x7);
2709 for (i
= (size
>> 2) - 1; i
>= 0; i
--)
2711 INTVAL (xoperands
[2]) = (i
<< 2) + offset
;
2712 output_asm_insn ("ld [%a1+%2],%%g1\n\tst %%g1,[%a0+%2]",
2715 offset
+= (size
& ~0x3);
2723 for (i
= (size
>> 1) - 1; i
>= 0; i
--)
2725 INTVAL (xoperands
[2]) = (i
<< 1) + offset
;
2726 output_asm_insn ("lduh [%a1+%2],%%g1\n\tsth %%g1,[%a0+%2]",
2729 offset
+= (size
& ~0x1);
2737 for (i
= size
- 1; i
>= 0; i
--)
2739 INTVAL (xoperands
[2]) = i
+ offset
;
2740 output_asm_insn ("ldub [%a1+%2],%%g1\n\tstb %%g1,[%a0+%2]",
2746 /* We should never reach here. */
2750 /* If the size isn't known to be a multiple of the alignment,
2751 we have to do it in smaller pieces. If we could determine that
2752 the size was a multiple of 2 (or whatever), we could be smarter
2754 if (GET_CODE (sizertx
) != CONST_INT
)
2758 int size
= INTVAL (sizertx
);
2759 while (size
% align
)
2763 if (align
!= INTVAL (alignrtx
))
2764 alignrtx
= GEN_INT (align
);
2766 xoperands
[3] = GEN_INT (movstrsi_label
++);
2767 xoperands
[4] = GEN_INT (align
);
2768 xoperands
[5] = GEN_INT (movstrsi_label
++);
2770 ASM_GENERATE_INTERNAL_LABEL (label3
, "Lm", INTVAL (xoperands
[3]));
2771 ASM_GENERATE_INTERNAL_LABEL (label5
, "Lm", INTVAL (xoperands
[5]));
2773 /* This is the size of the transfer. Emit code to decrement the size
2774 value by ALIGN, and store the result in the temp1 register. */
2775 output_size_for_block_move (sizertx
, temp1
, alignrtx
);
2777 /* Must handle the case when the size is zero or negative, so the first thing
2778 we do is compare the size against zero, and only copy bytes if it is
2779 zero or greater. Note that we have already subtracted off the alignment
2780 once, so we must copy 1 alignment worth of bytes if the size is zero
2783 The SUN assembler complains about labels in branch delay slots, so we
2784 do this before outputting the load address, so that there will always
2785 be a harmless insn between the branch here and the next label emitted
2791 sprintf (pattern
, "cmp %%2,0\n\tbl %s", &label5
[1]);
2792 output_asm_insn (pattern
, xoperands
);
2795 zoperands
[0] = operands
[0];
2796 zoperands
[3] = plus_constant_for_output (operands
[0], align
);
2797 output_load_address (zoperands
);
2799 /* ??? This might be much faster if the loops below were preconditioned
2802 That is, at run time, copy enough bytes one at a time to ensure that the
2803 target and source addresses are aligned to the the largest possible
2804 alignment. Then use a preconditioned unrolled loop to copy say 16
2805 bytes at a time. Then copy bytes one at a time until finish the rest. */
2807 /* Output the first label separately, so that it is spaced properly. */
2809 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file
, "Lm", INTVAL (xoperands
[3]));
2813 register char *ld_suffix
= ((align
== 1) ? "ub" : (align
== 2) ? "uh"
2814 : (align
== 8 && TARGET_ARCH64
) ? "x" : "");
2815 register char *st_suffix
= ((align
== 1) ? "b" : (align
== 2) ? "h"
2816 : (align
== 8 && TARGET_ARCH64
) ? "x" : "");
2818 sprintf (pattern
, "ld%s [%%1+%%2],%%%%g1\n\tsubcc %%2,%%4,%%2\n\tbge %s\n\tst%s %%%%g1,[%%0+%%2]\n%s:", ld_suffix
, &label3
[1], st_suffix
, &label5
[1]);
2819 output_asm_insn (pattern
, xoperands
);
2826 /* Output reasonable peephole for set-on-condition-code insns.
2827 Note that these insns assume a particular way of defining
2828 labels. Therefore, *both* sparc.h and this function must
2829 be changed if a new syntax is needed. */
2832 output_scc_insn (operands
, insn
)
2836 static char string
[100];
2837 rtx label
= 0, next
= insn
;
2840 /* Try doing a jump optimization which jump.c can't do for us
2841 because we did not expose that setcc works by using branches.
2843 If this scc insn is followed by an unconditional branch, then have
2844 the jump insn emitted here jump to that location, instead of to
2845 the end of the scc sequence as usual. */
2849 if (GET_CODE (next
) == CODE_LABEL
)
2851 next
= NEXT_INSN (next
);
2855 while (GET_CODE (next
) == NOTE
|| GET_CODE (next
) == CODE_LABEL
);
2857 /* If we are in a sequence, and the following insn is a sequence also,
2858 then just following the current insn's next field will take us to the
2859 first insn of the next sequence, which is the wrong place. We don't
2860 want to optimize with a branch that has had its delay slot filled.
2861 Avoid this by verifying that NEXT_INSN (PREV_INSN (next)) == next
2862 which fails only if NEXT is such a branch. */
2864 if (next
&& GET_CODE (next
) == JUMP_INSN
&& simplejump_p (next
)
2865 && (! final_sequence
|| NEXT_INSN (PREV_INSN (next
)) == next
))
2866 label
= JUMP_LABEL (next
);
2867 /* If not optimizing, jump label fields are not set. To be safe, always
2868 check here to whether label is still zero. */
2871 label
= gen_label_rtx ();
2875 LABEL_NUSES (label
) += 1;
2877 /* operands[3] is an unused slot. */
2878 operands
[3] = label
;
2880 /* If we are in a delay slot, assume it is the delay slot of an fpcc
2881 insn since our type isn't allowed anywhere else. */
2883 /* ??? Fpcc instructions no longer have delay slots, so this code is
2884 probably obsolete. */
2886 /* The fastest way to emit code for this is an annulled branch followed
2887 by two move insns. This will take two cycles if the branch is taken,
2888 and three cycles if the branch is not taken.
2890 However, if we are in the delay slot of another branch, this won't work,
2891 because we can't put a branch in the delay slot of another branch.
2892 The above sequence would effectively take 3 or 4 cycles respectively
2893 since a no op would have be inserted between the two branches.
2894 In this case, we want to emit a move, annulled branch, and then the
2895 second move. This sequence always takes 3 cycles, and hence is faster
2896 when we are in a branch delay slot. */
2900 strcpy (string
, "mov 0,%0\n\t");
2901 strcat (string
, output_cbranch (operands
[2], 3, 0, 1, 0));
2902 strcat (string
, "\n\tmov 1,%0");
2906 strcpy (string
, output_cbranch (operands
[2], 3, 0, 1, 0));
2907 strcat (string
, "\n\tmov 1,%0\n\tmov 0,%0");
2911 strcat (string
, "\n%l3:");
2916 /* Vectors to keep interesting information about registers where it can easily
2917 be got. We use to use the actual mode value as the bit number, but there
2918 are more than 32 modes now. Instead we use two tables: one indexed by
2919 hard register number, and one indexed by mode. */
2921 /* The purpose of sparc_mode_class is to shrink the range of modes so that
2922 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
2923 mapped into one sparc_mode_class mode. */
2925 enum sparc_mode_class
{
2926 S_MODE
, D_MODE
, T_MODE
, O_MODE
,
2927 SF_MODE
, DF_MODE
, TF_MODE
, OF_MODE
,
2931 /* Modes for single-word and smaller quantities. */
2932 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
2934 /* Modes for double-word and smaller quantities. */
2935 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
2937 /* Modes for quad-word and smaller quantities. */
2938 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
2940 /* Modes for single-float quantities. We must allow any single word or
2941 smaller quantity. This is because the fix/float conversion instructions
2942 take integer inputs/outputs from the float registers. */
2943 #define SF_MODES (S_MODES)
2945 /* Modes for double-float and smaller quantities. */
2946 #define DF_MODES (S_MODES | D_MODES)
2948 /* ??? Sparc64 fp regs cannot hold DImode values. */
2949 #define DF_MODES64 (SF_MODES | DF_MODE /* | D_MODE*/)
2951 /* Modes for double-float only quantities. */
2952 /* ??? Sparc64 fp regs cannot hold DImode values.
2953 See fix_truncsfdi2. */
2954 #define DF_ONLY_MODES ((1 << (int) DF_MODE) /*| (1 << (int) D_MODE)*/)
2956 /* Modes for double-float and larger quantities. */
2957 #define DF_UP_MODES (DF_ONLY_MODES | TF_ONLY_MODES)
2959 /* Modes for quad-float only quantities. */
2960 #define TF_ONLY_MODES (1 << (int) TF_MODE)
2962 /* Modes for quad-float and smaller quantities. */
2963 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
2965 /* ??? Sparc64 fp regs cannot hold DImode values.
2966 See fix_truncsfdi2. */
2967 #define TF_MODES64 (DF_MODES64 | TF_ONLY_MODES)
2969 /* Modes for condition codes. */
2970 #define CC_MODES (1 << (int) CC_MODE)
2971 #define CCFP_MODES (1 << (int) CCFP_MODE)
2973 /* Value is 1 if register/mode pair is acceptable on sparc.
2974 The funny mixture of D and T modes is because integer operations
2975 do not specially operate on tetra quantities, so non-quad-aligned
2976 registers can hold quadword quantities (except %o4 and %i4 because
2977 they cross fixed registers). */
2979 /* This points to either the 32 bit or the 64 bit version. */
2980 int *hard_regno_mode_classes
;
2982 static int hard_32bit_mode_classes
[] = {
2983 S_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2984 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
2985 T_MODES
, S_MODES
, T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
,
2986 T_MODES
, S_MODES
, T_MODES
, S_MODES
, D_MODES
, S_MODES
, D_MODES
, S_MODES
,
2988 TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
2989 TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
2990 TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
2991 TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
, TF_MODES
, SF_MODES
, DF_MODES
, SF_MODES
,
2993 /* FP regs f32 to f63. Only the even numbered registers actually exist,
2994 and none can hold SFmode/SImode values. */
2995 DF_UP_MODES
, 0, DF_ONLY_MODES
, 0, DF_UP_MODES
, 0, DF_ONLY_MODES
, 0,
2996 DF_UP_MODES
, 0, DF_ONLY_MODES
, 0, DF_UP_MODES
, 0, DF_ONLY_MODES
, 0,
2997 DF_UP_MODES
, 0, DF_ONLY_MODES
, 0, DF_UP_MODES
, 0, DF_ONLY_MODES
, 0,
2998 DF_UP_MODES
, 0, DF_ONLY_MODES
, 0, DF_UP_MODES
, 0, DF_ONLY_MODES
, 0,
3001 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
3007 static int hard_64bit_mode_classes
[] = {
3008 D_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3009 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3010 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3011 T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
, T_MODES
, D_MODES
,
3013 TF_MODES64
, SF_MODES
, DF_MODES64
, SF_MODES
, TF_MODES64
, SF_MODES
, DF_MODES64
, SF_MODES
,
3014 TF_MODES64
, SF_MODES
, DF_MODES64
, SF_MODES
, TF_MODES64
, SF_MODES
, DF_MODES64
, SF_MODES
,
3015 TF_MODES64
, SF_MODES
, DF_MODES64
, SF_MODES
, TF_MODES64
, SF_MODES
, DF_MODES64
, SF_MODES
,
3016 TF_MODES64
, SF_MODES
, DF_MODES64
, SF_MODES
, TF_MODES64
, SF_MODES
, DF_MODES64
, SF_MODES
,
3018 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3019 and none can hold SFmode/SImode values. */
3020 DF_UP_MODES
, 0, DF_ONLY_MODES
, 0, DF_UP_MODES
, 0, DF_ONLY_MODES
, 0,
3021 DF_UP_MODES
, 0, DF_ONLY_MODES
, 0, DF_UP_MODES
, 0, DF_ONLY_MODES
, 0,
3022 DF_UP_MODES
, 0, DF_ONLY_MODES
, 0, DF_UP_MODES
, 0, DF_ONLY_MODES
, 0,
3023 DF_UP_MODES
, 0, DF_ONLY_MODES
, 0, DF_UP_MODES
, 0, DF_ONLY_MODES
, 0,
3026 CCFP_MODES
, CCFP_MODES
, CCFP_MODES
, CCFP_MODES
,
3032 int sparc_mode_class
[NUM_MACHINE_MODES
];
3034 enum reg_class sparc_regno_reg_class
[FIRST_PSEUDO_REGISTER
];
3041 for (i
= 0; i
< NUM_MACHINE_MODES
; i
++)
3043 switch (GET_MODE_CLASS (i
))
3046 case MODE_PARTIAL_INT
:
3047 case MODE_COMPLEX_INT
:
3048 if (GET_MODE_SIZE (i
) <= 4)
3049 sparc_mode_class
[i
] = 1 << (int) S_MODE
;
3050 else if (GET_MODE_SIZE (i
) == 8)
3051 sparc_mode_class
[i
] = 1 << (int) D_MODE
;
3052 else if (GET_MODE_SIZE (i
) == 16)
3053 sparc_mode_class
[i
] = 1 << (int) T_MODE
;
3054 else if (GET_MODE_SIZE (i
) == 32)
3055 sparc_mode_class
[i
] = 1 << (int) O_MODE
;
3057 sparc_mode_class
[i
] = 0;
3060 case MODE_COMPLEX_FLOAT
:
3061 if (GET_MODE_SIZE (i
) <= 4)
3062 sparc_mode_class
[i
] = 1 << (int) SF_MODE
;
3063 else if (GET_MODE_SIZE (i
) == 8)
3064 sparc_mode_class
[i
] = 1 << (int) DF_MODE
;
3065 else if (GET_MODE_SIZE (i
) == 16)
3066 sparc_mode_class
[i
] = 1 << (int) TF_MODE
;
3067 else if (GET_MODE_SIZE (i
) == 32)
3068 sparc_mode_class
[i
] = 1 << (int) OF_MODE
;
3070 sparc_mode_class
[i
] = 0;
3074 /* mode_class hasn't been initialized yet for EXTRA_CC_MODES, so
3075 we must explicitly check for them here. */
3076 if (i
== (int) CCFPmode
|| i
== (int) CCFPEmode
)
3077 sparc_mode_class
[i
] = 1 << (int) CCFP_MODE
;
3078 else if (i
== (int) CCmode
|| i
== (int) CC_NOOVmode
3079 || i
== (int) CCXmode
|| i
== (int) CCX_NOOVmode
)
3080 sparc_mode_class
[i
] = 1 << (int) CC_MODE
;
3082 sparc_mode_class
[i
] = 0;
3088 hard_regno_mode_classes
= hard_64bit_mode_classes
;
3090 hard_regno_mode_classes
= hard_32bit_mode_classes
;
3092 /* Initialize the array used by REGNO_REG_CLASS. */
3093 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3096 sparc_regno_reg_class
[i
] = GENERAL_REGS
;
3098 sparc_regno_reg_class
[i
] = FP_REGS
;
3100 sparc_regno_reg_class
[i
] = EXTRA_FP_REGS
;
3102 sparc_regno_reg_class
[i
] = FPCC_REGS
;
3104 sparc_regno_reg_class
[i
] = NO_REGS
;
3108 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
3109 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3110 v9 int regs as it simplifies the code. */
3113 save_regs (file
, low
, high
, base
, offset
, n_regs
, real_offset
)
3123 if (TARGET_ARCH64
&& high
<= 32)
3125 for (i
= low
; i
< high
; i
++)
3127 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3129 fprintf (file
, "\tstx %s,[%s+%d]\n",
3130 reg_names
[i
], base
, offset
+ 4 * n_regs
);
3131 if (dwarf2out_do_frame ())
3132 dwarf2out_reg_save ("", i
, real_offset
+ 4 * n_regs
);
3139 for (i
= low
; i
< high
; i
+= 2)
3141 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3142 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3144 fprintf (file
, "\tstd %s,[%s+%d]\n",
3145 reg_names
[i
], base
, offset
+ 4 * n_regs
);
3146 if (dwarf2out_do_frame ())
3148 char *l
= dwarf2out_cfi_label ();
3149 dwarf2out_reg_save (l
, i
, real_offset
+ 4 * n_regs
);
3150 dwarf2out_reg_save (l
, i
+1, real_offset
+ 4 * n_regs
+ 4);
3156 fprintf (file
, "\tst %s,[%s+%d]\n",
3157 reg_names
[i
], base
, offset
+ 4 * n_regs
);
3158 if (dwarf2out_do_frame ())
3159 dwarf2out_reg_save ("", i
, real_offset
+ 4 * n_regs
);
3162 else if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3164 fprintf (file
, "\tst %s,[%s+%d]\n",
3165 reg_names
[i
+1], base
, offset
+ 4 * n_regs
+ 4);
3166 if (dwarf2out_do_frame ())
3167 dwarf2out_reg_save ("", i
+ 1, real_offset
+ 4 * n_regs
+ 4);
3175 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
3177 N_REGS is the number of 4-byte regs saved thus far. This applies even to
3178 v9 int regs as it simplifies the code. */
3181 restore_regs (file
, low
, high
, base
, offset
, n_regs
)
3190 if (TARGET_ARCH64
&& high
<= 32)
3192 for (i
= low
; i
< high
; i
++)
3194 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3195 fprintf (file
, "\tldx [%s+%d], %s\n",
3196 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
3202 for (i
= low
; i
< high
; i
+= 2)
3204 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3205 if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3206 fprintf (file
, "\tldd [%s+%d], %s\n",
3207 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
3210 fprintf (file
, "\tld [%s+%d],%s\n",
3211 base
, offset
+ 4 * n_regs
, reg_names
[i
]),
3213 else if (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1])
3214 fprintf (file
, "\tld [%s+%d],%s\n",
3215 base
, offset
+ 4 * n_regs
+ 4, reg_names
[i
+1]),
3222 /* Static variables we want to share between prologue and epilogue. */
3224 /* Number of live general or floating point registers needed to be saved
3225 (as 4-byte quantities). This is only done if TARGET_EPILOGUE. */
3226 static int num_gfregs
;
3228 /* Compute the frame size required by the function. This function is called
3229 during the reload pass and also by output_function_prologue(). */
3232 compute_frame_size (size
, leaf_function
)
3237 int outgoing_args_size
= (current_function_outgoing_args_size
3238 + REG_PARM_STACK_SPACE (current_function_decl
));
3240 if (TARGET_EPILOGUE
)
3242 /* N_REGS is the number of 4-byte regs saved thus far. This applies
3243 even to v9 int regs to be consistent with save_regs/restore_regs. */
3247 for (i
= 0; i
< 8; i
++)
3248 if (regs_ever_live
[i
] && ! call_used_regs
[i
])
3253 for (i
= 0; i
< 8; i
+= 2)
3254 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
3255 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
3259 for (i
= 32; i
< (TARGET_V9
? 96 : 64); i
+= 2)
3260 if ((regs_ever_live
[i
] && ! call_used_regs
[i
])
3261 || (regs_ever_live
[i
+1] && ! call_used_regs
[i
+1]))
3265 /* Set up values for use in `function_epilogue'. */
3266 num_gfregs
= n_regs
;
3268 if (leaf_function
&& n_regs
== 0
3269 && size
== 0 && current_function_outgoing_args_size
== 0)
3271 actual_fsize
= apparent_fsize
= 0;
3275 /* We subtract STARTING_FRAME_OFFSET, remember it's negative.
3276 The stack bias (if any) is taken out to undo its effects. */
3277 apparent_fsize
= (size
- STARTING_FRAME_OFFSET
+ SPARC_STACK_BIAS
+ 7) & -8;
3278 apparent_fsize
+= n_regs
* 4;
3279 actual_fsize
= apparent_fsize
+ ((outgoing_args_size
+ 7) & -8);
3282 /* Make sure nothing can clobber our register windows.
3283 If a SAVE must be done, or there is a stack-local variable,
3284 the register window area must be allocated.
3285 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
3286 if (leaf_function
== 0 || size
> 0)
3287 actual_fsize
+= (16 * UNITS_PER_WORD
) + (TARGET_ARCH64
? 0 : 8);
3289 return SPARC_STACK_ALIGN (actual_fsize
);
3292 /* Build a (32 bit) big number in a register. */
3293 /* ??? We may be able to use the set macro here too. */
3296 build_big_number (file
, num
, reg
)
3301 if (num
>= 0 || ! TARGET_ARCH64
)
3303 fprintf (file
, "\tsethi %%hi(%d),%s\n", num
, reg
);
3304 if ((num
& 0x3ff) != 0)
3305 fprintf (file
, "\tor %s,%%lo(%d),%s\n", reg
, num
, reg
);
3307 else /* num < 0 && TARGET_ARCH64 */
3309 /* Sethi does not sign extend, so we must use a little trickery
3310 to use it for negative numbers. Invert the constant before
3311 loading it in, then use xor immediate to invert the loaded bits
3312 (along with the upper 32 bits) to the desired constant. This
3313 works because the sethi and immediate fields overlap. */
3316 int low
= -0x400 + (asize
& 0x3FF);
3318 fprintf (file
, "\tsethi %%hi(%d),%s\n\txor %s,%d,%s\n",
3319 inv
, reg
, reg
, low
, reg
);
3323 /* Output code for the function prologue. */
3326 output_function_prologue (file
, size
, leaf_function
)
3331 /* Need to use actual_fsize, since we are also allocating
3332 space for our callee (and our own register save area). */
3333 actual_fsize
= compute_frame_size (size
, leaf_function
);
3337 frame_base_name
= "%sp";
3338 frame_base_offset
= actual_fsize
+ SPARC_STACK_BIAS
;
3342 frame_base_name
= "%fp";
3343 frame_base_offset
= SPARC_STACK_BIAS
;
3346 /* This is only for the human reader. */
3347 fprintf (file
, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START
);
3349 if (actual_fsize
== 0)
3351 else if (! leaf_function
&& ! TARGET_BROKEN_SAVERESTORE
)
3353 if (actual_fsize
<= 4096)
3354 fprintf (file
, "\tsave %%sp,-%d,%%sp\n", actual_fsize
);
3355 else if (actual_fsize
<= 8192)
3357 fprintf (file
, "\tsave %%sp,-4096,%%sp\n");
3358 fprintf (file
, "\tadd %%sp,-%d,%%sp\n", actual_fsize
- 4096);
3362 build_big_number (file
, -actual_fsize
, "%g1");
3363 fprintf (file
, "\tsave %%sp,%%g1,%%sp\n");
3366 else if (! leaf_function
&& TARGET_BROKEN_SAVERESTORE
)
3368 /* We assume the environment will properly handle or otherwise avoid
3369 trouble associated with an interrupt occurring after the `save' or
3370 trap occurring during it. */
3371 fprintf (file
, "\tsave\n");
3373 if (actual_fsize
<= 4096)
3374 fprintf (file
, "\tadd %%fp,-%d,%%sp\n", actual_fsize
);
3375 else if (actual_fsize
<= 8192)
3377 fprintf (file
, "\tadd %%fp,-4096,%%sp\n");
3378 fprintf (file
, "\tadd %%fp,-%d,%%sp\n", actual_fsize
- 4096);
3382 build_big_number (file
, -actual_fsize
, "%g1");
3383 fprintf (file
, "\tadd %%fp,%%g1,%%sp\n");
3386 else /* leaf function */
3388 if (actual_fsize
<= 4096)
3389 fprintf (file
, "\tadd %%sp,-%d,%%sp\n", actual_fsize
);
3390 else if (actual_fsize
<= 8192)
3392 fprintf (file
, "\tadd %%sp,-4096,%%sp\n");
3393 fprintf (file
, "\tadd %%sp,-%d,%%sp\n", actual_fsize
- 4096);
3397 build_big_number (file
, -actual_fsize
, "%g1");
3398 fprintf (file
, "\tadd %%sp,%%g1,%%sp\n");
3402 if (dwarf2out_do_frame () && actual_fsize
)
3404 char *label
= dwarf2out_cfi_label ();
3406 /* The canonical frame address refers to the top of the frame. */
3407 dwarf2out_def_cfa (label
, (leaf_function
? STACK_POINTER_REGNUM
3408 : FRAME_POINTER_REGNUM
),
3411 if (! leaf_function
)
3413 /* Note the register window save. This tells the unwinder that
3414 it needs to restore the window registers from the previous
3415 frame's window save area at 0(cfa). */
3416 dwarf2out_window_save (label
);
3418 /* The return address (-8) is now in %i7. */
3419 dwarf2out_return_reg (label
, 31);
3423 /* If doing anything with PIC, do it now. */
3425 fprintf (file
, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START
);
3427 /* Call saved registers are saved just above the outgoing argument area. */
3430 int offset
, real_offset
, n_regs
;
3433 real_offset
= -apparent_fsize
;
3434 offset
= -apparent_fsize
+ frame_base_offset
;
3435 if (offset
< -4096 || offset
+ num_gfregs
* 4 > 4096)
3437 /* ??? This might be optimized a little as %g1 might already have a
3438 value close enough that a single add insn will do. */
3439 /* ??? Although, all of this is probably only a temporary fix
3440 because if %g1 can hold a function result, then
3441 output_function_epilogue will lose (the result will get
3443 build_big_number (file
, offset
, "%g1");
3444 fprintf (file
, "\tadd %s,%%g1,%%g1\n", frame_base_name
);
3450 base
= frame_base_name
;
3453 if (TARGET_EPILOGUE
&& ! leaf_function
)
3454 /* ??? Originally saved regs 0-15 here. */
3455 n_regs
= save_regs (file
, 0, 8, base
, offset
, 0, real_offset
);
3456 else if (leaf_function
)
3457 /* ??? Originally saved regs 0-31 here. */
3458 n_regs
= save_regs (file
, 0, 8, base
, offset
, 0, real_offset
);
3459 if (TARGET_EPILOGUE
)
3460 save_regs (file
, 32, TARGET_V9
? 96 : 64, base
, offset
, n_regs
,
3465 if (leaf_function
&& actual_fsize
!= 0)
3467 /* warning ("leaf procedure with frame size %d", actual_fsize); */
3468 if (! TARGET_EPILOGUE
)
3469 leaf_label
= gen_label_rtx ();
3473 /* Output code for the function epilogue. */
3476 output_function_epilogue (file
, size
, leaf_function
)
3485 emit_label_after (leaf_label
, get_last_insn ());
3486 final_scan_insn (get_last_insn (), file
, 0, 0, 1);
3489 #ifdef FUNCTION_BLOCK_PROFILER_EXIT
3490 else if (profile_block_flag
== 2)
3492 FUNCTION_BLOCK_PROFILER_EXIT(file
);
3496 /* Restore any call saved registers. */
3502 offset
= -apparent_fsize
+ frame_base_offset
;
3503 if (offset
< -4096 || offset
+ num_gfregs
* 4 > 4096 - 8 /*double*/)
3505 build_big_number (file
, offset
, "%g1");
3506 fprintf (file
, "\tadd %s,%%g1,%%g1\n", frame_base_name
);
3512 base
= frame_base_name
;
3515 if (TARGET_EPILOGUE
&& ! leaf_function
)
3516 /* ??? Originally saved regs 0-15 here. */
3517 n_regs
= restore_regs (file
, 0, 8, base
, offset
, 0);
3518 else if (leaf_function
)
3519 /* ??? Originally saved regs 0-31 here. */
3520 n_regs
= restore_regs (file
, 0, 8, base
, offset
, 0);
3521 if (TARGET_EPILOGUE
)
3522 restore_regs (file
, 32, TARGET_V9
? 96 : 64, base
, offset
, n_regs
);
3525 /* Work out how to skip the caller's unimp instruction if required. */
3527 ret
= (SKIP_CALLERS_UNIMP_P
? "jmp %o7+12" : "retl");
3529 ret
= (SKIP_CALLERS_UNIMP_P
? "jmp %i7+12" : "ret");
3531 if (TARGET_EPILOGUE
|| leaf_label
)
3533 int old_target_epilogue
= TARGET_EPILOGUE
;
3534 target_flags
&= ~old_target_epilogue
;
3536 if (! leaf_function
)
3538 /* If we wound up with things in our delay slot, flush them here. */
3539 if (current_function_epilogue_delay_list
)
3541 rtx insn
= emit_jump_insn_after (gen_rtx_RETURN (VOIDmode
),
3548 (XEXP (current_function_epilogue_delay_list
, 0)),
3551 final_scan_insn (insn
, file
, 1, 0, 1);
3554 fprintf (file
, "\t%s\n\trestore\n", ret
);
3556 /* All of the following cases are for leaf functions. */
3557 else if (current_function_epilogue_delay_list
)
3559 /* eligible_for_epilogue_delay_slot ensures that if this is a
3560 leaf function, then we will only have insn in the delay slot
3561 if the frame size is zero, thus no adjust for the stack is
3563 if (actual_fsize
!= 0)
3565 fprintf (file
, "\t%s\n", ret
);
3566 final_scan_insn (XEXP (current_function_epilogue_delay_list
, 0),
3569 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
3570 avoid generating confusing assembly language output. */
3571 else if (actual_fsize
== 0)
3572 fprintf (file
, "\t%s\n\tnop\n", ret
);
3573 else if (actual_fsize
<= 4096)
3574 fprintf (file
, "\t%s\n\tsub %%sp,-%d,%%sp\n", ret
, actual_fsize
);
3575 else if (actual_fsize
<= 8192)
3576 fprintf (file
, "\tsub %%sp,-4096,%%sp\n\t%s\n\tsub %%sp,-%d,%%sp\n",
3577 ret
, actual_fsize
- 4096);
3578 else if ((actual_fsize
& 0x3ff) == 0)
3579 fprintf (file
, "\tsethi %%hi(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n",
3582 fprintf (file
, "\tsethi %%hi(%d),%%g1\n\tor %%g1,%%lo(%d),%%g1\n\t%s\n\tadd %%sp,%%g1,%%sp\n",
3583 actual_fsize
, actual_fsize
, ret
);
3584 target_flags
|= old_target_epilogue
;
3588 /* Functions for handling argument passing.
3590 For v8 the first six args are normally in registers and the rest are
3591 pushed. Any arg that starts within the first 6 words is at least
3592 partially passed in a register unless its data type forbids.
3594 For v9, the argument registers are laid out as an array of 16 elements
3595 and arguments are added sequentially. The first 6 int args and up to the
3596 first 16 fp args (depending on size) are passed in regs.
3598 Slot Stack Integral Float Float in structure Double Long Double
3599 ---- ----- -------- ----- ------------------ ------ -----------
3600 15 [SP+248] %f31 %f30,%f31 %d30
3601 14 [SP+240] %f29 %f28,%f29 %d28 %q28
3602 13 [SP+232] %f27 %f26,%f27 %d26
3603 12 [SP+224] %f25 %f24,%f25 %d24 %q24
3604 11 [SP+216] %f23 %f22,%f23 %d22
3605 10 [SP+208] %f21 %f20,%f21 %d20 %q20
3606 9 [SP+200] %f19 %f18,%f19 %d18
3607 8 [SP+192] %f17 %f16,%f17 %d16 %q16
3608 7 [SP+184] %f15 %f14,%f15 %d14
3609 6 [SP+176] %f13 %f12,%f13 %d12 %q12
3610 5 [SP+168] %o5 %f11 %f10,%f11 %d10
3611 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
3612 3 [SP+152] %o3 %f7 %f6,%f7 %d6
3613 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
3614 1 [SP+136] %o1 %f3 %f2,%f3 %d2
3615 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
3617 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
3619 Integral arguments are always passed as 64 bit quantities appropriately
3622 Passing of floating point values is handled as follows.
3623 If a prototype is in scope:
3624 If the value is in a named argument (i.e. not a stdarg function or a
3625 value not part of the `...') then the value is passed in the appropriate
3627 If the value is part of the `...' and is passed in one of the first 6
3628 slots then the value is passed in the appropriate int reg.
3629 If the value is part of the `...' and is not passed in one of the first 6
3630 slots then the value is passed in memory.
3631 If a prototype is not in scope:
3632 If the value is one of the first 6 arguments the value is passed in the
3633 appropriate integer reg and the appropriate fp reg.
3634 If the value is not one of the first 6 arguments the value is passed in
3635 the appropriate fp reg and in memory.
3638 /* Maximum number of int regs for args. */
3639 #define SPARC_INT_ARG_MAX 6
3640 /* Maximum number of fp regs for args. */
3641 #define SPARC_FP_ARG_MAX 16
3643 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
3645 /* Handle the INIT_CUMULATIVE_ARGS macro.
3646 Initialize a variable CUM of type CUMULATIVE_ARGS
3647 for a call to a function whose data type is FNTYPE.
3648 For a library call, FNTYPE is 0. */
3651 init_cumulative_args (cum
, fntype
, libname
, indirect
)
3652 CUMULATIVE_ARGS
*cum
;
3653 tree fntype
, libname
;
3657 cum
->prototype_p
= fntype
&& TYPE_ARG_TYPES (fntype
);
3658 cum
->libcall_p
= fntype
== 0;
3661 /* Compute the slot number to pass an argument in.
3662 Returns the slot number or -1 if passing on the stack.
3664 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3665 the preceding args and about the function being called.
3666 MODE is the argument's machine mode.
3667 TYPE is the data type of the argument (as a tree).
3668 This is null for libcalls where that information may
3670 NAMED is nonzero if this argument is a named parameter
3671 (otherwise it is an extra parameter matching an ellipsis).
3672 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
3673 *PREGNO records the register number to use if scalar type.
3674 *PPADDING records the amount of padding needed in words. */
3677 function_arg_slotno (cum
, mode
, type
, named
, incoming_p
, pregno
, ppadding
)
3678 const CUMULATIVE_ARGS
*cum
;
3679 enum machine_mode mode
;
3686 int regbase
= (incoming_p
3687 ? SPARC_INCOMING_INT_ARG_FIRST
3688 : SPARC_OUTGOING_INT_ARG_FIRST
);
3689 int slotno
= cum
->words
;
3694 if (type
!= 0 && TREE_ADDRESSABLE (type
))
3697 && type
!= 0 && mode
== BLKmode
3698 && TYPE_ALIGN (type
) % PARM_BOUNDARY
!= 0)
3704 /* MODE is VOIDmode when generating the actual call.
3708 case QImode
: case CQImode
:
3709 case HImode
: case CHImode
:
3710 case SImode
: case CSImode
:
3711 case DImode
: case CDImode
:
3712 if (slotno
>= SPARC_INT_ARG_MAX
)
3714 regno
= regbase
+ slotno
;
3717 case SFmode
: case SCmode
:
3718 case DFmode
: case DCmode
:
3719 case TFmode
: case TCmode
:
3722 if (slotno
>= SPARC_INT_ARG_MAX
)
3724 regno
= regbase
+ slotno
;
3728 if ((mode
== TFmode
|| mode
== TCmode
)
3729 && (slotno
& 1) != 0)
3730 slotno
++, *ppadding
= 1;
3731 if (TARGET_FPU
&& named
)
3733 if (slotno
>= SPARC_FP_ARG_MAX
)
3735 regno
= SPARC_FP_ARG_FIRST
+ slotno
* 2;
3741 if (slotno
>= SPARC_INT_ARG_MAX
)
3743 regno
= regbase
+ slotno
;
3749 /* For sparc64, objects requiring 16 byte alignment get it. */
3752 if (type
&& TYPE_ALIGN (type
) == 128 && (slotno
& 1) != 0)
3753 slotno
++, *ppadding
= 1;
3757 || type
&& TREE_CODE (type
) == UNION_TYPE
)
3759 if (slotno
>= SPARC_INT_ARG_MAX
)
3761 regno
= regbase
+ slotno
;
3766 int intregs_p
= 0, fpregs_p
= 0;
3767 /* The ABI obviously doesn't specify how packed
3768 structures are passed. These are defined to be passed
3769 in int regs if possible, otherwise memory. */
3772 /* First see what kinds of registers we need. */
3773 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3775 if (TREE_CODE (field
) == FIELD_DECL
)
3777 if (TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3782 if (DECL_PACKED (field
))
3786 if (packed_p
|| !named
)
3787 fpregs_p
= 0, intregs_p
= 1;
3789 /* If all arg slots are filled, then must pass on stack. */
3790 if (fpregs_p
&& slotno
>= SPARC_FP_ARG_MAX
)
3792 /* If there are only int args and all int arg slots are filled,
3793 then must pass on stack. */
3794 if (!fpregs_p
&& intregs_p
&& slotno
>= SPARC_INT_ARG_MAX
)
3796 /* Note that even if all int arg slots are filled, fp members may
3797 still be passed in regs if such regs are available.
3798 *PREGNO isn't set because there may be more than one, it's up
3799 to the caller to compute them. */
3812 /* Handle the FUNCTION_ARG macro.
3813 Determine where to put an argument to a function.
3814 Value is zero to push the argument on the stack,
3815 or a hard register in which to store the argument.
3817 CUM is a variable of type CUMULATIVE_ARGS which gives info about
3818 the preceding args and about the function being called.
3819 MODE is the argument's machine mode.
3820 TYPE is the data type of the argument (as a tree).
3821 This is null for libcalls where that information may
3823 NAMED is nonzero if this argument is a named parameter
3824 (otherwise it is an extra parameter matching an ellipsis).
3825 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
3828 function_arg (cum
, mode
, type
, named
, incoming_p
)
3829 const CUMULATIVE_ARGS
*cum
;
3830 enum machine_mode mode
;
3835 int regbase
= (incoming_p
3836 ? SPARC_INCOMING_INT_ARG_FIRST
3837 : SPARC_OUTGOING_INT_ARG_FIRST
);
3838 int slotno
, regno
, padding
;
3841 slotno
= function_arg_slotno (cum
, mode
, type
, named
, incoming_p
,
3849 reg
= gen_rtx_REG (mode
, regno
);
3853 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
3854 but also have the slot allocated for them.
3855 If no prototype is in scope fp values in register slots get passed
3856 in two places, either fp regs and int regs or fp regs and memory. */
3857 if ((GET_MODE_CLASS (mode
) == MODE_FLOAT
3858 || GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
3859 && SPARC_FP_REG_P (regno
))
3861 reg
= gen_rtx_REG (mode
, regno
);
3862 if (cum
->prototype_p
|| cum
->libcall_p
)
3864 /* "* 2" because fp reg numbers are recorded in 4 byte
3866 /* ??? This will cause the value to be passed in the fp reg and
3867 in the stack. When a prototype exists we want to pass the
3868 value in the reg but reserve space on the stack. That's an
3869 optimization, and is deferred [for a bit]. */
3870 if ((regno
- SPARC_FP_ARG_FIRST
) >= SPARC_INT_ARG_MAX
* 2)
3871 return gen_rtx_PARALLEL
3874 gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
),
3875 gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
)));
3881 if ((regno
- SPARC_FP_ARG_FIRST
) < SPARC_INT_ARG_MAX
* 2)
3883 int regbase
= (incoming_p
3884 ? SPARC_INCOMING_INT_ARG_FIRST
3885 : SPARC_OUTGOING_INT_ARG_FIRST
);
3886 int intreg
= regbase
+ (regno
- SPARC_FP_ARG_FIRST
) / 2;
3888 return gen_rtx_PARALLEL
3891 gen_rtx_EXPR_LIST (VOIDmode
,
3892 gen_rtx_REG (mode
, intreg
),
3894 gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
)));
3897 return gen_rtx_PARALLEL
3900 gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
),
3901 gen_rtx_EXPR_LIST (VOIDmode
, reg
, const0_rtx
)));
3904 else if (type
&& TREE_CODE (type
) == RECORD_TYPE
)
3906 /* Structures up to 16 bytes in size are passed in arg slots on the
3907 stack and are promoted to registers where possible. */
3912 /* Starting bit position of a sequence of integer fields, counted from
3913 msb of left most byte, -1 if last field wasn't an int. */
3914 /* ??? This isn't entirely necessary, some simplification
3916 int start_int_bitpos
;
3917 /* Current bitpos in struct, counted from msb of left most byte. */
3918 int bitpos
, this_slotno
;
3919 /* The ABI obviously doesn't specify how packed
3920 structures are passed. These are defined to be passed
3921 in int regs if possible, otherwise memory. */
3924 if (int_size_in_bytes (type
) > 16)
3925 abort (); /* shouldn't get here */
3927 /* We need to compute how many registers are needed so we can allocate
3928 the PARALLEL but before we can do that we need to know whether there
3929 are any packed fields. If there are, int regs are used regardless of
3930 whether there are fp values present. */
3931 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3933 if (TREE_CODE (field
) == FIELD_DECL
3934 && DECL_PACKED (field
))
3941 /* Compute how many registers we need. */
3943 start_int_bitpos
= -1;
3944 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3946 bitpos
= TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
));
3947 this_slotno
= slotno
+ bitpos
/ BITS_PER_WORD
;
3948 if (TREE_CODE (field
) == FIELD_DECL
)
3950 if (TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3955 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
3956 If it wasn't true we wouldn't be here. */
3958 start_int_bitpos
= -1;
3960 else if (this_slotno
< SPARC_INT_ARG_MAX
)
3962 if (start_int_bitpos
== -1)
3965 start_int_bitpos
= bitpos
;
3969 if (bitpos
% BITS_PER_WORD
== 0)
3978 ret
= gen_rtx_PARALLEL (BLKmode
, rtvec_alloc (nregs
+ 1));
3980 /* ??? This causes the entire struct to be passed in memory.
3981 This isn't necessary, but is left for later. */
3982 XVECEXP (ret
, 0, 0) = gen_rtx_EXPR_LIST (VOIDmode
, NULL_RTX
, const0_rtx
);
3984 /* Fill in the entries. */
3985 start_int_bitpos
= -1;
3986 for (i
= 1, field
= TYPE_FIELDS (type
);
3988 field
= TREE_CHAIN (field
))
3990 bitpos
= TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
));
3991 this_slotno
= slotno
+ bitpos
/ BITS_PER_WORD
;
3992 if (TREE_CODE (field
) == FIELD_DECL
)
3994 if (TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3999 reg
= gen_rtx_REG (DECL_MODE (field
),
4000 (SPARC_FP_ARG_FIRST
+ this_slotno
* 2
4001 + (DECL_MODE (field
) == SFmode
4002 && (bitpos
& 32) != 0)));
4004 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
4005 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4007 start_int_bitpos
= -1;
4011 if (this_slotno
< SPARC_INT_ARG_MAX
4012 && (start_int_bitpos
== -1
4013 || bitpos
% BITS_PER_WORD
== 0))
4015 enum machine_mode mode
;
4017 /* If this is the trailing part of a word, only load
4018 that much into the register. Otherwise load the
4019 whole register. Note that in the latter case we may
4020 pick up unwanted bits. It's not a problem at the
4021 moment but may wish to revisit. */
4022 if (bitpos
% BITS_PER_WORD
!= 0)
4023 mode
= mode_for_size (BITS_PER_WORD
- bitpos
% BITS_PER_WORD
,
4028 regno
= regbase
+ this_slotno
;
4029 reg
= gen_rtx_REG (mode
, regno
);
4031 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
4032 GEN_INT (bitpos
/ BITS_PER_UNIT
));
4034 if (start_int_bitpos
== -1)
4035 start_int_bitpos
= bitpos
;
4045 else if (type
&& TREE_CODE (type
) == UNION_TYPE
)
4047 enum machine_mode mode
;
4048 int bytes
= int_size_in_bytes (type
);
4053 mode
= mode_for_size (bytes
* BITS_PER_UNIT
, MODE_INT
, 0);
4054 reg
= gen_rtx_REG (mode
, regno
);
4058 /* Scalar or complex int. */
4059 reg
= gen_rtx_REG (mode
, regno
);
4065 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
4066 For an arg passed partly in registers and partly in memory,
4067 this is the number of registers used.
4068 For args passed entirely in registers or entirely in memory, zero.
4070 Any arg that starts in the first 6 regs but won't entirely fit in them
4071 needs partial registers on v8. On v9, structures with integer
4072 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
4073 values that begin in the last fp reg [where "last fp reg" varies with the
4074 mode] will be split between that reg and memory. */
4077 function_arg_partial_nregs (cum
, mode
, type
, named
)
4078 const CUMULATIVE_ARGS
*cum
;
4079 enum machine_mode mode
;
4083 int slotno
, regno
, padding
;
4085 /* We pass 0 for incoming_p here, it doesn't matter. */
4086 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
4093 if ((slotno
+ (mode
== BLKmode
4094 ? ROUND_ADVANCE (int_size_in_bytes (type
))
4095 : ROUND_ADVANCE (GET_MODE_SIZE (mode
))))
4096 > NPARM_REGS (SImode
))
4097 return NPARM_REGS (SImode
) - slotno
;
4102 if (type
&& AGGREGATE_TYPE_P (type
))
4104 int size
= int_size_in_bytes (type
);
4105 int align
= TYPE_ALIGN (type
);
4108 slotno
+= slotno
& 1;
4109 if (size
> 8 && size
<= 16
4110 && slotno
== SPARC_INT_ARG_MAX
- 1)
4113 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
4114 || (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
4117 if (GET_MODE_ALIGNMENT (mode
) == 128)
4119 slotno
+= slotno
& 1;
4120 if (slotno
== SPARC_INT_ARG_MAX
- 2)
4125 if (slotno
== SPARC_INT_ARG_MAX
- 1)
4129 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4131 if (GET_MODE_ALIGNMENT (mode
) == 128)
4132 slotno
+= slotno
& 1;
4133 if ((slotno
+ GET_MODE_SIZE (mode
) / UNITS_PER_WORD
)
4141 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
4142 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
4143 quad-precision floats by invisible reference.
4144 v9: aggregates greater than 16 bytes are passed by reference.
4145 For Pascal, also pass arrays by reference. */
4148 function_arg_pass_by_reference (cum
, mode
, type
, named
)
4149 const CUMULATIVE_ARGS
*cum
;
4150 enum machine_mode mode
;
4156 return (type
&& AGGREGATE_TYPE_P (type
)
4157 || mode
== TFmode
|| mode
== TCmode
);
4161 return ((type
&& TREE_CODE (type
) == ARRAY_TYPE
)
4162 || (type
&& AGGREGATE_TYPE_P (type
)
4163 && int_size_in_bytes (type
) > 16));
4167 /* Handle the FUNCTION_ARG_ADVANCE macro.
4168 Update the data in CUM to advance over an argument
4169 of mode MODE and data type TYPE.
4170 TYPE is null for libcalls where that information may not be available. */
4173 function_arg_advance (cum
, mode
, type
, named
)
4174 CUMULATIVE_ARGS
*cum
;
4175 enum machine_mode mode
;
4179 int slotno
, regno
, padding
;
4181 /* We pass 0 for incoming_p here, it doesn't matter. */
4182 slotno
= function_arg_slotno (cum
, mode
, type
, named
, 0, ®no
, &padding
);
4184 /* If register required leading padding, add it. */
4186 cum
->words
+= padding
;
4190 cum
->words
+= (mode
!= BLKmode
4191 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
4192 : ROUND_ADVANCE (int_size_in_bytes (type
)));
4196 if (type
&& AGGREGATE_TYPE_P (type
))
4198 int size
= int_size_in_bytes (type
);
4202 else if (size
<= 16)
4204 else /* passed by reference */
4207 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_INT
)
4211 else if (GET_MODE_CLASS (mode
) == MODE_COMPLEX_FLOAT
)
4213 cum
->words
+= GET_MODE_SIZE (mode
) / UNITS_PER_WORD
;
4217 cum
->words
+= (mode
!= BLKmode
4218 ? ROUND_ADVANCE (GET_MODE_SIZE (mode
))
4219 : ROUND_ADVANCE (int_size_in_bytes (type
)));
4224 /* Handle the FUNCTION_ARG_PADDING macro.
4225 For the 64 bit ABI structs are always stored left shifted in their
4229 function_arg_padding (mode
, type
)
4230 enum machine_mode mode
;
4233 if (TARGET_ARCH64
&& type
&& TREE_CODE (type
) == RECORD_TYPE
)
4238 /* This is the default definition. */
4239 return (! BYTES_BIG_ENDIAN
4242 ? (type
&& TREE_CODE (TYPE_SIZE (type
)) == INTEGER_CST
4243 && int_size_in_bytes (type
) < (PARM_BOUNDARY
/ BITS_PER_UNIT
))
4244 : GET_MODE_BITSIZE (mode
) < PARM_BOUNDARY
)
4245 ? downward
: upward
));
4248 /* Do what is necessary for `va_start'. The argument is ignored.
4250 We look at the current function to determine if stdarg or varargs
4251 is used and return the address of the first unnamed parameter. */
4254 sparc_builtin_saveregs (arglist
)
4257 tree fntype
= TREE_TYPE (current_function_decl
);
4258 int stdarg
= (TYPE_ARG_TYPES (fntype
) != 0
4259 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
4260 != void_type_node
));
4261 int first_reg
= current_function_args_info
.words
;
4265 for (regno
= first_reg
; regno
< NPARM_REGS (word_mode
); regno
++)
4266 emit_move_insn (gen_rtx_MEM (word_mode
,
4267 plus_constant (frame_pointer_rtx
,
4268 (STACK_POINTER_OFFSET
4269 + UNITS_PER_WORD
* regno
))),
4270 gen_rtx_REG (word_mode
,
4271 BASE_INCOMING_ARG_REG (word_mode
) + regno
));
4273 address
= plus_constant (frame_pointer_rtx
,
4274 STACK_POINTER_OFFSET
+ UNITS_PER_WORD
* first_reg
);
4276 if (current_function_check_memory_usage
4277 && first_reg
< NPARM_REGS (word_mode
))
4278 emit_library_call (chkr_set_right_libfunc
, 1, VOIDmode
, 3,
4280 GEN_INT (UNITS_PER_WORD
4281 * (NPARM_REGS (word_mode
) - first_reg
)),
4282 TYPE_MODE (sizetype
), GEN_INT (MEMORY_USE_RW
),
4283 TYPE_MODE (integer_type_node
));
4288 /* Return the string to output a conditional branch to LABEL, which is
4289 the operand number of the label. OP is the conditional expression.
4290 XEXP (OP, 0) is assumed to be a condition code register (integer or
4291 floating point) and its mode specifies what kind of comparison we made.
4293 REVERSED is non-zero if we should reverse the sense of the comparison.
4295 ANNUL is non-zero if we should generate an annulling branch.
4297 NOOP is non-zero if we have to follow this branch by a noop. */
4300 output_cbranch (op
, label
, reversed
, annul
, noop
)
4303 int reversed
, annul
, noop
;
4305 static char string
[20];
4306 enum rtx_code code
= GET_CODE (op
);
4307 rtx cc_reg
= XEXP (op
, 0);
4308 enum machine_mode mode
= GET_MODE (cc_reg
);
4309 static char v8_labelno
[] = " %lX";
4310 static char v9_icc_labelno
[] = " %%icc,%lX";
4311 static char v9_xcc_labelno
[] = " %%xcc,%lX";
4312 static char v9_fcc_labelno
[] = " %%fccX,%lY";
4316 /* ??? !v9: FP branches cannot be preceded by another floating point insn.
4317 Because there is currently no concept of pre-delay slots, we can fix
4318 this only by always emitting a nop before a floating point branch. */
4320 if ((mode
== CCFPmode
|| mode
== CCFPEmode
) && ! TARGET_V9
)
4321 strcpy (string
, "nop\n\t");
4325 /* If not floating-point or if EQ or NE, we can just reverse the code. */
4327 && ((mode
!= CCFPmode
&& mode
!= CCFPEmode
) || code
== EQ
|| code
== NE
))
4328 code
= reverse_condition (code
), reversed
= 0;
4330 /* Start by writing the branch condition. */
4334 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
4335 strcat (string
, "fbne");
4337 strcpy (string
, "bne");
4341 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
4342 strcat (string
, "fbe");
4344 strcpy (string
, "be");
4348 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
4351 strcat (string
, "fbul");
4353 strcat (string
, "fbge");
4355 else if (mode
== CC_NOOVmode
)
4356 strcpy (string
, "bpos");
4358 strcpy (string
, "bge");
4362 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
4365 strcat (string
, "fbule");
4367 strcat (string
, "fbg");
4370 strcpy (string
, "bg");
4374 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
4377 strcat (string
, "fbug");
4379 strcat (string
, "fble");
4382 strcpy (string
, "ble");
4386 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
4389 strcat (string
, "fbuge");
4391 strcat (string
, "fbl");
4393 else if (mode
== CC_NOOVmode
)
4394 strcpy (string
, "bneg");
4396 strcpy (string
, "bl");
4400 strcpy (string
, "bgeu");
4404 strcpy (string
, "bgu");
4408 strcpy (string
, "bleu");
4412 strcpy (string
, "blu");
4416 /* Now add the annulling, the label, and a possible noop. */
4418 strcat (string
, ",a");
4420 /* ??? If v9, optional prediction bit ",pt" or ",pf" goes here. */
4425 labelno
= v8_labelno
;
4430 if (mode
== CCFPmode
|| mode
== CCFPEmode
)
4433 labelno
= v9_fcc_labelno
;
4434 /* Set the char indicating the number of the fcc reg to use. */
4435 labelno
[6] = REGNO (cc_reg
) - SPARC_FIRST_V9_FCC_REG
+ '0';
4437 else if (mode
== CCXmode
|| mode
== CCX_NOOVmode
)
4438 labelno
= v9_xcc_labelno
;
4440 labelno
= v9_icc_labelno
;
4442 /* Set the char indicating the number of the operand containing the
4444 labelno
[labeloff
] = label
+ '0';
4445 strcat (string
, labelno
);
4448 strcat (string
, "\n\tnop");
4453 /* Return the string to output a conditional branch to LABEL, testing
4454 register REG. LABEL is the operand number of the label; REG is the
4455 operand number of the reg. OP is the conditional expression. The mode
4456 of REG says what kind of comparison we made.
4458 REVERSED is non-zero if we should reverse the sense of the comparison.
4460 ANNUL is non-zero if we should generate an annulling branch.
4462 NOOP is non-zero if we have to follow this branch by a noop. */
4465 output_v9branch (op
, reg
, label
, reversed
, annul
, noop
)
4468 int reversed
, annul
, noop
;
4470 static char string
[20];
4471 enum rtx_code code
= GET_CODE (op
);
4472 enum machine_mode mode
= GET_MODE (XEXP (op
, 0));
4473 static char labelno
[] = " %X,%lX";
4475 /* If not floating-point or if EQ or NE, we can just reverse the code. */
4477 code
= reverse_condition (code
), reversed
= 0;
4479 /* Only 64 bit versions of these instructions exist. */
4483 /* Start by writing the branch condition. */
4488 strcpy (string
, "brnz");
4492 strcpy (string
, "brz");
4496 strcpy (string
, "brgez");
4500 strcpy (string
, "brlz");
4504 strcpy (string
, "brlez");
4508 strcpy (string
, "brgz");
4515 /* Now add the annulling, reg, label, and nop. */
4517 strcat (string
, ",a");
4519 /* ??? Optional prediction bit ",pt" or ",pf" goes here. */
4521 labelno
[2] = reg
+ '0';
4522 labelno
[6] = label
+ '0';
4523 strcat (string
, labelno
);
4526 strcat (string
, "\n\tnop");
4531 /* Output assembler code to return from a function. */
4533 /* ??? v9: Update to use the new `return' instruction. Also, add patterns to
4534 md file for the `return' instruction. */
4537 output_return (operands
)
4542 operands
[0] = leaf_label
;
4545 else if (leaf_function
)
4547 /* If we didn't allocate a frame pointer for the current function,
4548 the stack pointer might have been adjusted. Output code to
4551 operands
[0] = GEN_INT (actual_fsize
);
4553 /* Use sub of negated value in first two cases instead of add to
4554 allow actual_fsize == 4096. */
4556 if (actual_fsize
<= 4096)
4558 if (SKIP_CALLERS_UNIMP_P
)
4559 return "jmp %%o7+12\n\tsub %%sp,-%0,%%sp";
4561 return "retl\n\tsub %%sp,-%0,%%sp";
4563 else if (actual_fsize
<= 8192)
4565 operands
[0] = GEN_INT (actual_fsize
- 4096);
4566 if (SKIP_CALLERS_UNIMP_P
)
4567 return "sub %%sp,-4096,%%sp\n\tjmp %%o7+12\n\tsub %%sp,-%0,%%sp";
4569 return "sub %%sp,-4096,%%sp\n\tretl\n\tsub %%sp,-%0,%%sp";
4571 else if (SKIP_CALLERS_UNIMP_P
)
4573 if ((actual_fsize
& 0x3ff) != 0)
4574 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp";
4576 return "sethi %%hi(%a0),%%g1\n\tjmp %%o7+12\n\tadd %%sp,%%g1,%%sp";
4580 if ((actual_fsize
& 0x3ff) != 0)
4581 return "sethi %%hi(%a0),%%g1\n\tor %%g1,%%lo(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
4583 return "sethi %%hi(%a0),%%g1\n\tretl\n\tadd %%sp,%%g1,%%sp";
4588 if (SKIP_CALLERS_UNIMP_P
)
4589 return "jmp %%i7+12\n\trestore";
4591 return "ret\n\trestore";
4595 /* Leaf functions and non-leaf functions have different needs. */
4598 reg_leaf_alloc_order
[] = REG_LEAF_ALLOC_ORDER
;
4601 reg_nonleaf_alloc_order
[] = REG_ALLOC_ORDER
;
4603 static int *reg_alloc_orders
[] = {
4604 reg_leaf_alloc_order
,
4605 reg_nonleaf_alloc_order
};
4608 order_regs_for_local_alloc ()
4610 static int last_order_nonleaf
= 1;
4612 if (regs_ever_live
[15] != last_order_nonleaf
)
4614 last_order_nonleaf
= !last_order_nonleaf
;
4615 bcopy ((char *) reg_alloc_orders
[last_order_nonleaf
],
4616 (char *) reg_alloc_order
, FIRST_PSEUDO_REGISTER
* sizeof (int));
4620 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
4621 This makes them candidates for using ldd and std insns.
4623 Note reg1 and reg2 *must* be hard registers. To be sure we will
4624 abort if we are passed pseudo registers. */
4627 registers_ok_for_ldd_peep (reg1
, reg2
)
4630 /* We might have been passed a SUBREG. */
4631 if (GET_CODE (reg1
) != REG
|| GET_CODE (reg2
) != REG
)
4634 if (REGNO (reg1
) % 2 != 0)
4637 return (REGNO (reg1
) == REGNO (reg2
) - 1);
4640 /* Return 1 if addr1 and addr2 are suitable for use in an ldd or
4643 This can only happen when addr1 and addr2 are consecutive memory
4644 locations (addr1 + 4 == addr2). addr1 must also be aligned on a
4645 64 bit boundary (addr1 % 8 == 0).
4647 We know %sp and %fp are kept aligned on a 64 bit boundary. Other
4648 registers are assumed to *never* be properly aligned and are
4651 Knowing %sp and %fp are kept aligned on a 64 bit boundary, we
4652 need only check that the offset for addr1 % 8 == 0. */
4655 addrs_ok_for_ldd_peep (addr1
, addr2
)
4660 /* Extract a register number and offset (if used) from the first addr. */
4661 if (GET_CODE (addr1
) == PLUS
)
4663 /* If not a REG, return zero. */
4664 if (GET_CODE (XEXP (addr1
, 0)) != REG
)
4668 reg1
= REGNO (XEXP (addr1
, 0));
4669 /* The offset must be constant! */
4670 if (GET_CODE (XEXP (addr1
, 1)) != CONST_INT
)
4672 offset1
= INTVAL (XEXP (addr1
, 1));
4675 else if (GET_CODE (addr1
) != REG
)
4679 reg1
= REGNO (addr1
);
4680 /* This was a simple (mem (reg)) expression. Offset is 0. */
4684 /* Make sure the second address is a (mem (plus (reg) (const_int). */
4685 if (GET_CODE (addr2
) != PLUS
)
4688 if (GET_CODE (XEXP (addr2
, 0)) != REG
4689 || GET_CODE (XEXP (addr2
, 1)) != CONST_INT
)
4692 /* Only %fp and %sp are allowed. Additionally both addresses must
4693 use the same register. */
4694 if (reg1
!= FRAME_POINTER_REGNUM
&& reg1
!= STACK_POINTER_REGNUM
)
4697 if (reg1
!= REGNO (XEXP (addr2
, 0)))
4700 /* The first offset must be evenly divisible by 8 to ensure the
4701 address is 64 bit aligned. */
4702 if (offset1
% 8 != 0)
4705 /* The offset for the second addr must be 4 more than the first addr. */
4706 if (INTVAL (XEXP (addr2
, 1)) != offset1
+ 4)
4709 /* All the tests passed. addr1 and addr2 are valid for ldd and std
4714 /* Return 1 if reg is a pseudo, or is the first register in
4715 a hard register pair. This makes it a candidate for use in
4716 ldd and std insns. */
4719 register_ok_for_ldd (reg
)
4722 /* We might have been passed a SUBREG. */
4723 if (GET_CODE (reg
) != REG
)
4726 if (REGNO (reg
) < FIRST_PSEUDO_REGISTER
)
4727 return (REGNO (reg
) % 2 == 0);
4732 /* Print operand X (an rtx) in assembler syntax to file FILE.
4733 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4734 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4737 print_operand (file
, x
, code
)
4745 /* Output a 'nop' if there's nothing for the delay slot. */
4746 if (dbr_sequence_length () == 0)
4747 fputs ("\n\tnop", file
);
4750 /* Output an annul flag if there's nothing for the delay slot and we
4751 are optimizing. This is always used with '(' below. */
4752 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
4753 this is a dbx bug. So, we only do this when optimizing. */
4754 if (dbr_sequence_length () == 0 && optimize
)
4758 /* Output a 'nop' if there's nothing for the delay slot and we are
4759 not optimizing. This is always used with '*' above. */
4760 if (dbr_sequence_length () == 0 && ! optimize
)
4761 fputs ("\n\tnop", file
);
4764 /* Output the Embedded Medium/Anywhere code model base register. */
4765 fputs (EMBMEDANY_BASE_REG
, file
);
4768 /* Print out what we are using as the frame pointer. This might
4769 be %fp, or might be %sp+offset. */
4770 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
4771 fprintf (file
, "%s+%d", frame_base_name
, frame_base_offset
);
4774 /* Adjust the operand to take into account a RESTORE operation. */
4775 if (GET_CODE (x
) != REG
)
4776 output_operand_lossage ("Invalid %%Y operand");
4777 else if (REGNO (x
) < 8)
4778 fputs (reg_names
[REGNO (x
)], file
);
4779 else if (REGNO (x
) >= 24 && REGNO (x
) < 32)
4780 fputs (reg_names
[REGNO (x
)-16], file
);
4782 output_operand_lossage ("Invalid %%Y operand");
4785 /* Print out the low order register name of a register pair. */
4786 if (WORDS_BIG_ENDIAN
)
4787 fputs (reg_names
[REGNO (x
)+1], file
);
4789 fputs (reg_names
[REGNO (x
)], file
);
4792 /* Print out the high order register name of a register pair. */
4793 if (WORDS_BIG_ENDIAN
)
4794 fputs (reg_names
[REGNO (x
)], file
);
4796 fputs (reg_names
[REGNO (x
)+1], file
);
4799 /* Print out the second register name of a register pair or quad.
4800 I.e., R (%o0) => %o1. */
4801 fputs (reg_names
[REGNO (x
)+1], file
);
4804 /* Print out the third register name of a register quad.
4805 I.e., S (%o0) => %o2. */
4806 fputs (reg_names
[REGNO (x
)+2], file
);
4809 /* Print out the fourth register name of a register quad.
4810 I.e., T (%o0) => %o3. */
4811 fputs (reg_names
[REGNO (x
)+3], file
);
4814 /* Print a condition code register. */
4815 if (REGNO (x
) == SPARC_ICC_REG
)
4817 /* We don't handle CC[X]_NOOVmode because they're not supposed
4819 if (GET_MODE (x
) == CCmode
)
4820 fputs ("%icc", file
);
4821 else if (GET_MODE (x
) == CCXmode
)
4822 fputs ("%xcc", file
);
4827 /* %fccN register */
4828 fputs (reg_names
[REGNO (x
)], file
);
4831 /* Print the operand's address only. */
4832 output_address (XEXP (x
, 0));
4835 /* In this case we need a register. Use %g0 if the
4836 operand is const0_rtx. */
4838 || (GET_MODE (x
) != VOIDmode
&& x
== CONST0_RTX (GET_MODE (x
))))
4840 fputs ("%g0", file
);
4847 switch (GET_CODE (x
))
4849 case IOR
: fputs ("or", file
); break;
4850 case AND
: fputs ("and", file
); break;
4851 case XOR
: fputs ("xor", file
); break;
4852 default: output_operand_lossage ("Invalid %%A operand");
4857 switch (GET_CODE (x
))
4859 case IOR
: fputs ("orn", file
); break;
4860 case AND
: fputs ("andn", file
); break;
4861 case XOR
: fputs ("xnor", file
); break;
4862 default: output_operand_lossage ("Invalid %%B operand");
4866 /* These are used by the conditional move instructions. */
4870 enum rtx_code rc
= (code
== 'c'
4871 ? reverse_condition (GET_CODE (x
))
4875 case NE
: fputs ("ne", file
); break;
4876 case EQ
: fputs ("e", file
); break;
4877 case GE
: fputs ("ge", file
); break;
4878 case GT
: fputs ("g", file
); break;
4879 case LE
: fputs ("le", file
); break;
4880 case LT
: fputs ("l", file
); break;
4881 case GEU
: fputs ("geu", file
); break;
4882 case GTU
: fputs ("gu", file
); break;
4883 case LEU
: fputs ("leu", file
); break;
4884 case LTU
: fputs ("lu", file
); break;
4885 default: output_operand_lossage (code
== 'c'
4886 ? "Invalid %%c operand"
4887 : "Invalid %%C operand");
4892 /* These are used by the movr instruction pattern. */
4896 enum rtx_code rc
= (code
== 'd'
4897 ? reverse_condition (GET_CODE (x
))
4901 case NE
: fputs ("ne", file
); break;
4902 case EQ
: fputs ("e", file
); break;
4903 case GE
: fputs ("gez", file
); break;
4904 case LT
: fputs ("lz", file
); break;
4905 case LE
: fputs ("lez", file
); break;
4906 case GT
: fputs ("gz", file
); break;
4907 default: output_operand_lossage (code
== 'd'
4908 ? "Invalid %%d operand"
4909 : "Invalid %%D operand");
4916 /* Print a sign-extended character. */
4917 int i
= INTVAL (x
) & 0xff;
4920 fprintf (file
, "%d", i
);
4925 /* Operand must be a MEM; write its address. */
4926 if (GET_CODE (x
) != MEM
)
4927 output_operand_lossage ("Invalid %%f operand");
4928 output_address (XEXP (x
, 0));
4932 /* Do nothing special. */
4936 /* Undocumented flag. */
4937 output_operand_lossage ("invalid operand output code");
4940 if (GET_CODE (x
) == REG
)
4941 fputs (reg_names
[REGNO (x
)], file
);
4942 else if (GET_CODE (x
) == MEM
)
4945 /* Poor Sun assembler doesn't understand absolute addressing. */
4946 if (CONSTANT_P (XEXP (x
, 0))
4947 && ! TARGET_LIVE_G0
)
4948 fputs ("%g0+", file
);
4949 output_address (XEXP (x
, 0));
4952 else if (GET_CODE (x
) == HIGH
)
4954 fputs ("%hi(", file
);
4955 output_addr_const (file
, XEXP (x
, 0));
4958 else if (GET_CODE (x
) == LO_SUM
)
4960 print_operand (file
, XEXP (x
, 0), 0);
4961 fputs ("+%lo(", file
);
4962 output_addr_const (file
, XEXP (x
, 1));
4965 else if (GET_CODE (x
) == CONST_DOUBLE
4966 && (GET_MODE (x
) == VOIDmode
4967 || GET_MODE_CLASS (GET_MODE (x
)) == MODE_INT
))
4969 if (CONST_DOUBLE_HIGH (x
) == 0)
4970 fprintf (file
, "%u", CONST_DOUBLE_LOW (x
));
4971 else if (CONST_DOUBLE_HIGH (x
) == -1
4972 && CONST_DOUBLE_LOW (x
) < 0)
4973 fprintf (file
, "%d", CONST_DOUBLE_LOW (x
));
4975 output_operand_lossage ("long long constant not a valid immediate operand");
4977 else if (GET_CODE (x
) == CONST_DOUBLE
)
4978 output_operand_lossage ("floating point constant not a valid immediate operand");
4979 else { output_addr_const (file
, x
); }
4982 /* This function outputs assembler code for VALUE to FILE, where VALUE is
4983 a 64 bit (DImode) value. */
4985 /* ??? If there is a 64 bit counterpart to .word that the assembler
4986 understands, then using that would simply this code greatly. */
4987 /* ??? We only output .xword's for symbols and only then in environments
4988 where the assembler can handle them. */
4991 output_double_int (file
, value
)
4995 if (GET_CODE (value
) == CONST_INT
)
4997 /* ??? This has endianness issues. */
4998 #if HOST_BITS_PER_WIDE_INT == 64
4999 HOST_WIDE_INT xword
= INTVAL (value
);
5000 HOST_WIDE_INT high
, low
;
5002 high
= (xword
>> 32) & 0xffffffff;
5003 low
= xword
& 0xffffffff;
5004 ASM_OUTPUT_INT (file
, GEN_INT (high
));
5005 ASM_OUTPUT_INT (file
, GEN_INT (low
));
5007 if (INTVAL (value
) < 0)
5008 ASM_OUTPUT_INT (file
, constm1_rtx
);
5010 ASM_OUTPUT_INT (file
, const0_rtx
);
5011 ASM_OUTPUT_INT (file
, value
);
5014 else if (GET_CODE (value
) == CONST_DOUBLE
)
5016 ASM_OUTPUT_INT (file
, GEN_INT (CONST_DOUBLE_HIGH (value
)));
5017 ASM_OUTPUT_INT (file
, GEN_INT (CONST_DOUBLE_LOW (value
)));
5019 else if (GET_CODE (value
) == SYMBOL_REF
5020 || GET_CODE (value
) == CONST
5021 || GET_CODE (value
) == PLUS
5022 || (TARGET_ARCH64
&&
5023 (GET_CODE (value
) == LABEL_REF
5024 || GET_CODE (value
) == CODE_LABEL
5025 || GET_CODE (value
) == MINUS
)))
5027 if (!TARGET_V9
|| TARGET_CM_MEDLOW
)
5029 ASM_OUTPUT_INT (file
, const0_rtx
);
5030 ASM_OUTPUT_INT (file
, value
);
5034 fprintf (file
, "\t%s\t", ASM_LONGLONG
);
5035 output_addr_const (file
, value
);
5036 fprintf (file
, "\n");
5043 /* Return the value of a code used in the .proc pseudo-op that says
5044 what kind of result this function returns. For non-C types, we pick
5045 the closest C type. */
5047 #ifndef CHAR_TYPE_SIZE
5048 #define CHAR_TYPE_SIZE BITS_PER_UNIT
5051 #ifndef SHORT_TYPE_SIZE
5052 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
5055 #ifndef INT_TYPE_SIZE
5056 #define INT_TYPE_SIZE BITS_PER_WORD
5059 #ifndef LONG_TYPE_SIZE
5060 #define LONG_TYPE_SIZE BITS_PER_WORD
5063 #ifndef LONG_LONG_TYPE_SIZE
5064 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
5067 #ifndef FLOAT_TYPE_SIZE
5068 #define FLOAT_TYPE_SIZE BITS_PER_WORD
5071 #ifndef DOUBLE_TYPE_SIZE
5072 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5075 #ifndef LONG_DOUBLE_TYPE_SIZE
5076 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
5080 sparc_type_code (type
)
5083 register unsigned long qualifiers
= 0;
5084 register unsigned shift
;
5086 /* Only the first 30 bits of the qualifier are valid. We must refrain from
5087 setting more, since some assemblers will give an error for this. Also,
5088 we must be careful to avoid shifts of 32 bits or more to avoid getting
5089 unpredictable results. */
5091 for (shift
= 6; shift
< 30; shift
+= 2, type
= TREE_TYPE (type
))
5093 switch (TREE_CODE (type
))
5099 qualifiers
|= (3 << shift
);
5104 qualifiers
|= (2 << shift
);
5108 case REFERENCE_TYPE
:
5110 qualifiers
|= (1 << shift
);
5114 return (qualifiers
| 8);
5117 case QUAL_UNION_TYPE
:
5118 return (qualifiers
| 9);
5121 return (qualifiers
| 10);
5124 return (qualifiers
| 16);
5127 /* If this is a range type, consider it to be the underlying
5129 if (TREE_TYPE (type
) != 0)
5132 /* Carefully distinguish all the standard types of C,
5133 without messing up if the language is not C. We do this by
5134 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
5135 look at both the names and the above fields, but that's redundant.
5136 Any type whose size is between two C types will be considered
5137 to be the wider of the two types. Also, we do not have a
5138 special code to use for "long long", so anything wider than
5139 long is treated the same. Note that we can't distinguish
5140 between "int" and "long" in this code if they are the same
5141 size, but that's fine, since neither can the assembler. */
5143 if (TYPE_PRECISION (type
) <= CHAR_TYPE_SIZE
)
5144 return (qualifiers
| (TREE_UNSIGNED (type
) ? 12 : 2));
5146 else if (TYPE_PRECISION (type
) <= SHORT_TYPE_SIZE
)
5147 return (qualifiers
| (TREE_UNSIGNED (type
) ? 13 : 3));
5149 else if (TYPE_PRECISION (type
) <= INT_TYPE_SIZE
)
5150 return (qualifiers
| (TREE_UNSIGNED (type
) ? 14 : 4));
5153 return (qualifiers
| (TREE_UNSIGNED (type
) ? 15 : 5));
5156 /* If this is a range type, consider it to be the underlying
5158 if (TREE_TYPE (type
) != 0)
5161 /* Carefully distinguish all the standard types of C,
5162 without messing up if the language is not C. */
5164 if (TYPE_PRECISION (type
) == FLOAT_TYPE_SIZE
)
5165 return (qualifiers
| 6);
5168 return (qualifiers
| 7);
5170 case COMPLEX_TYPE
: /* GNU Fortran COMPLEX type. */
5171 /* ??? We need to distinguish between double and float complex types,
5172 but I don't know how yet because I can't reach this code from
5173 existing front-ends. */
5174 return (qualifiers
| 7); /* Who knows? */
5176 case CHAR_TYPE
: /* GNU Pascal CHAR type. Not used in C. */
5177 case BOOLEAN_TYPE
: /* GNU Fortran BOOLEAN type. */
5178 case FILE_TYPE
: /* GNU Pascal FILE type. */
5179 case SET_TYPE
: /* GNU Pascal SET type. */
5180 case LANG_TYPE
: /* ? */
5184 abort (); /* Not a type! */
5191 /* Nested function support. */
5193 /* Emit RTL insns to initialize the variable parts of a trampoline.
5194 FNADDR is an RTX for the address of the function's pure code.
5195 CXT is an RTX for the static chain value for the function.
5197 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
5198 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
5199 (to store insns). This is a bit excessive. Perhaps a different
5200 mechanism would be better here.
5202 Emit enough FLUSH insns to synchronize the data and instruction caches. */
5205 sparc_initialize_trampoline (tramp
, fnaddr
, cxt
)
5206 rtx tramp
, fnaddr
, cxt
;
5208 rtx high_cxt
= expand_shift (RSHIFT_EXPR
, SImode
, cxt
,
5209 size_int (10), 0, 1);
5210 rtx high_fn
= expand_shift (RSHIFT_EXPR
, SImode
, fnaddr
,
5211 size_int (10), 0, 1);
5212 rtx low_cxt
= expand_and (cxt
, GEN_INT (0x3ff), 0);
5213 rtx low_fn
= expand_and (fnaddr
, GEN_INT (0x3ff), 0);
5214 rtx g1_sethi
= gen_rtx_HIGH (SImode
, GEN_INT (0x03000000));
5215 rtx g2_sethi
= gen_rtx_HIGH (SImode
, GEN_INT (0x05000000));
5216 rtx g1_ori
= gen_rtx_HIGH (SImode
, GEN_INT (0x82106000));
5217 rtx g2_ori
= gen_rtx_HIGH (SImode
, GEN_INT (0x8410A000));
5218 rtx tem
= gen_reg_rtx (SImode
);
5219 emit_move_insn (tem
, g1_sethi
);
5220 emit_insn (gen_iorsi3 (high_fn
, high_fn
, tem
));
5221 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 0)), high_fn
);
5222 emit_move_insn (tem
, g1_ori
);
5223 emit_insn (gen_iorsi3 (low_fn
, low_fn
, tem
));
5224 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 4)), low_fn
);
5225 emit_move_insn (tem
, g2_sethi
);
5226 emit_insn (gen_iorsi3 (high_cxt
, high_cxt
, tem
));
5227 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)), high_cxt
);
5228 emit_move_insn (tem
, g2_ori
);
5229 emit_insn (gen_iorsi3 (low_cxt
, low_cxt
, tem
));
5230 emit_move_insn (gen_rtx_MEM (SImode
, plus_constant (tramp
, 16)), low_cxt
);
5231 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode
, tramp
))));
5232 emit_insn (gen_flush (validize_mem
5233 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 8)))));
5234 emit_insn (gen_flush (validize_mem
5235 (gen_rtx_MEM (SImode
, plus_constant (tramp
, 16)))));
5238 /* The 64 bit version is simpler because it makes more sense to load the
5239 values as "immediate" data out of the trampoline. It's also easier since
5240 we can read the PC without clobbering a register. */
5243 sparc64_initialize_trampoline (tramp
, fnaddr
, cxt
)
5244 rtx tramp
, fnaddr
, cxt
;
5246 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 24)), cxt
);
5247 emit_move_insn (gen_rtx_MEM (DImode
, plus_constant (tramp
, 32)), fnaddr
);
5248 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (DImode
, tramp
))));
5249 emit_insn (gen_flush (validize_mem
5250 (gen_rtx_MEM (DImode
, plus_constant (tramp
, 8)))));
5251 emit_insn (gen_flush (validize_mem
5252 (gen_rtx_MEM (DImode
, plus_constant (tramp
, 16)))));
5253 emit_insn (gen_flush (validize_mem
5254 (gen_rtx_MEM (DImode
, plus_constant (tramp
, 24)))));
5255 emit_insn (gen_flush (validize_mem
5256 (gen_rtx_MEM (DImode
, plus_constant (tramp
, 32)))));
5259 /* Subroutines to support a flat (single) register window calling
5262 /* Single-register window sparc stack frames look like:
5264 Before call After call
5265 +-----------------------+ +-----------------------+
5267 mem | caller's temps. | | caller's temps. |
5269 +-----------------------+ +-----------------------+
5271 | arguments on stack. | | arguments on stack. |
5273 +-----------------------+FP+92->+-----------------------+
5274 | 6 words to save | | 6 words to save |
5275 | arguments passed | | arguments passed |
5276 | in registers, even | | in registers, even |
5277 | if not passed. | | if not passed. |
5278 SP+68->+-----------------------+FP+68->+-----------------------+
5279 | 1 word struct addr | | 1 word struct addr |
5280 +-----------------------+FP+64->+-----------------------+
5282 | 16 word reg save area | | 16 word reg save area |
5284 SP->+-----------------------+ FP->+-----------------------+
5286 | fp/alu reg moves |
5287 FP-16->+-----------------------+
5291 +-----------------------+
5293 | fp register save |
5295 +-----------------------+
5297 | gp register save |
5299 +-----------------------+
5301 | alloca allocations |
5303 +-----------------------+
5305 | arguments on stack |
5307 SP+92->+-----------------------+
5309 | arguments passed |
5310 | in registers, even |
5311 low | if not passed. |
5312 memory SP+68->+-----------------------+
5313 | 1 word struct addr |
5314 SP+64->+-----------------------+
5316 I 16 word reg save area |
5318 SP->+-----------------------+ */
5320 /* Structure to be filled in by sparc_flat_compute_frame_size with register
5321 save masks, and offsets for the current function. */
5323 struct sparc_frame_info
5325 unsigned long total_size
; /* # bytes that the entire frame takes up. */
5326 unsigned long var_size
; /* # bytes that variables take up. */
5327 unsigned long args_size
; /* # bytes that outgoing arguments take up. */
5328 unsigned long extra_size
; /* # bytes of extra gunk. */
5329 unsigned int gp_reg_size
; /* # bytes needed to store gp regs. */
5330 unsigned int fp_reg_size
; /* # bytes needed to store fp regs. */
5331 unsigned long gmask
; /* Mask of saved gp registers. */
5332 unsigned long fmask
; /* Mask of saved fp registers. */
5333 unsigned long reg_offset
; /* Offset from new sp to store regs. */
5334 int initialized
; /* Nonzero if frame size already calculated. */
5337 /* Current frame information calculated by sparc_flat_compute_frame_size. */
5338 struct sparc_frame_info current_frame_info
;
5340 /* Zero structure to initialize current_frame_info. */
5341 struct sparc_frame_info zero_frame_info
;
5343 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
5345 #define RETURN_ADDR_REGNUM 15
5346 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM))
5347 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
5349 #define MUST_SAVE_REGISTER(regno) \
5350 ((regs_ever_live[regno] && !call_used_regs[regno]) \
5351 || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
5352 || (regno == RETURN_ADDR_REGNUM && regs_ever_live[RETURN_ADDR_REGNUM]))
5354 /* Return the bytes needed to compute the frame pointer from the current
5358 sparc_flat_compute_frame_size (size
)
5359 int size
; /* # of var. bytes allocated. */
5362 unsigned long total_size
; /* # bytes that the entire frame takes up. */
5363 unsigned long var_size
; /* # bytes that variables take up. */
5364 unsigned long args_size
; /* # bytes that outgoing arguments take up. */
5365 unsigned long extra_size
; /* # extra bytes. */
5366 unsigned int gp_reg_size
; /* # bytes needed to store gp regs. */
5367 unsigned int fp_reg_size
; /* # bytes needed to store fp regs. */
5368 unsigned long gmask
; /* Mask of saved gp registers. */
5369 unsigned long fmask
; /* Mask of saved fp registers. */
5370 unsigned long reg_offset
; /* Offset to register save area. */
5371 int need_aligned_p
; /* 1 if need the save area 8 byte aligned. */
5373 /* This is the size of the 16 word reg save area, 1 word struct addr
5374 area, and 4 word fp/alu register copy area. */
5375 extra_size
= -STARTING_FRAME_OFFSET
+ FIRST_PARM_OFFSET(0);
5377 /* Also include the size needed for the 6 parameter registers. */
5378 args_size
= current_function_outgoing_args_size
+ 24;
5379 total_size
= var_size
+ args_size
+ extra_size
;
5387 /* Calculate space needed for gp registers. */
5388 for (regno
= 1; regno
<= 31; regno
++)
5390 if (MUST_SAVE_REGISTER (regno
))
5392 /* If we need to save two regs in a row, ensure there's room to bump
5393 up the address to align it to a doubleword boundary. */
5394 if ((regno
& 0x1) == 0 && MUST_SAVE_REGISTER (regno
+1))
5396 if (gp_reg_size
% 8 != 0)
5398 gp_reg_size
+= 2 * UNITS_PER_WORD
;
5399 gmask
|= 3 << regno
;
5405 gp_reg_size
+= UNITS_PER_WORD
;
5406 gmask
|= 1 << regno
;
5411 /* Calculate space needed for fp registers. */
5412 for (regno
= 32; regno
<= 63; regno
++)
5414 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
5416 fp_reg_size
+= UNITS_PER_WORD
;
5417 fmask
|= 1 << (regno
- 32);
5424 reg_offset
= FIRST_PARM_OFFSET(0) + args_size
;
5425 /* Ensure save area is 8 byte aligned if we need it. */
5427 if (need_aligned_p
&& n
!= 0)
5429 total_size
+= 8 - n
;
5430 reg_offset
+= 8 - n
;
5432 total_size
+= gp_reg_size
+ fp_reg_size
;
5435 /* ??? This looks a little suspicious. Clarify. */
5436 if (total_size
== extra_size
)
5437 total_size
= extra_size
= 0;
5439 total_size
= SPARC_STACK_ALIGN (total_size
);
5441 /* Save other computed information. */
5442 current_frame_info
.total_size
= total_size
;
5443 current_frame_info
.var_size
= var_size
;
5444 current_frame_info
.args_size
= args_size
;
5445 current_frame_info
.extra_size
= extra_size
;
5446 current_frame_info
.gp_reg_size
= gp_reg_size
;
5447 current_frame_info
.fp_reg_size
= fp_reg_size
;
5448 current_frame_info
.gmask
= gmask
;
5449 current_frame_info
.fmask
= fmask
;
5450 current_frame_info
.reg_offset
= reg_offset
;
5451 current_frame_info
.initialized
= reload_completed
;
5453 /* Ok, we're done. */
5457 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
5460 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
5461 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
5462 [BASE_REG+OFFSET] will always be a valid address.
5464 WORD_OP is either "st" for save, "ld" for restore.
5465 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
5468 sparc_flat_save_restore (file
, base_reg
, offset
, gmask
, fmask
, word_op
,
5469 doubleword_op
, base_offset
)
5472 unsigned int offset
;
5473 unsigned long gmask
;
5474 unsigned long fmask
;
5476 char *doubleword_op
;
5477 unsigned long base_offset
;
5481 if (gmask
== 0 && fmask
== 0)
5484 /* Save registers starting from high to low. We've already saved the
5485 previous frame pointer and previous return address for the debugger's
5486 sake. The debugger allows us to not need a nop in the epilog if at least
5487 one register is reloaded in addition to return address. */
5491 for (regno
= 1; regno
<= 31; regno
++)
5493 if ((gmask
& (1L << regno
)) != 0)
5495 if ((regno
& 0x1) == 0 && ((gmask
& (1L << (regno
+1))) != 0))
5497 /* We can save two registers in a row. If we're not at a
5498 double word boundary, move to one.
5499 sparc_flat_compute_frame_size ensures there's room to do
5501 if (offset
% 8 != 0)
5502 offset
+= UNITS_PER_WORD
;
5504 if (word_op
[0] == 's')
5506 fprintf (file
, "\t%s %s,[%s+%d]\n",
5507 doubleword_op
, reg_names
[regno
],
5509 if (dwarf2out_do_frame ())
5511 char *l
= dwarf2out_cfi_label ();
5512 dwarf2out_reg_save (l
, regno
, offset
+ base_offset
);
5514 (l
, regno
+1, offset
+base_offset
+ UNITS_PER_WORD
);
5518 fprintf (file
, "\t%s [%s+%d],%s\n",
5519 doubleword_op
, base_reg
, offset
,
5522 offset
+= 2 * UNITS_PER_WORD
;
5527 if (word_op
[0] == 's')
5529 fprintf (file
, "\t%s %s,[%s+%d]\n",
5530 word_op
, reg_names
[regno
],
5532 if (dwarf2out_do_frame ())
5533 dwarf2out_reg_save ("", regno
, offset
+ base_offset
);
5536 fprintf (file
, "\t%s [%s+%d],%s\n",
5537 word_op
, base_reg
, offset
, reg_names
[regno
]);
5539 offset
+= UNITS_PER_WORD
;
5547 for (regno
= 32; regno
<= 63; regno
++)
5549 if ((fmask
& (1L << (regno
- 32))) != 0)
5551 if (word_op
[0] == 's')
5553 fprintf (file
, "\t%s %s,[%s+%d]\n",
5554 word_op
, reg_names
[regno
],
5556 if (dwarf2out_do_frame ())
5557 dwarf2out_reg_save ("", regno
, offset
+ base_offset
);
5560 fprintf (file
, "\t%s [%s+%d],%s\n",
5561 word_op
, base_reg
, offset
, reg_names
[regno
]);
5563 offset
+= UNITS_PER_WORD
;
5569 /* Set up the stack and frame (if desired) for the function. */
5572 sparc_flat_output_function_prologue (file
, size
)
5576 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
5577 unsigned long gmask
= current_frame_info
.gmask
;
5579 /* This is only for the human reader. */
5580 fprintf (file
, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START
);
5581 fprintf (file
, "\t%s# vars= %d, regs= %d/%d, args= %d, extra= %d\n",
5583 current_frame_info
.var_size
,
5584 current_frame_info
.gp_reg_size
/ 4,
5585 current_frame_info
.fp_reg_size
/ 4,
5586 current_function_outgoing_args_size
,
5587 current_frame_info
.extra_size
);
5589 size
= SPARC_STACK_ALIGN (size
);
5590 size
= (! current_frame_info
.initialized
5591 ? sparc_flat_compute_frame_size (size
)
5592 : current_frame_info
.total_size
);
5594 /* These cases shouldn't happen. Catch them now. */
5595 if (size
== 0 && (gmask
|| current_frame_info
.fmask
))
5598 /* Allocate our stack frame by decrementing %sp.
5599 At present, the only algorithm gdb can use to determine if this is a
5600 flat frame is if we always set %i7 if we set %sp. This can be optimized
5601 in the future by putting in some sort of debugging information that says
5602 this is a `flat' function. However, there is still the case of debugging
5603 code without such debugging information (including cases where most fns
5604 have such info, but there is one that doesn't). So, always do this now
5605 so we don't get a lot of code out there that gdb can't handle.
5606 If the frame pointer isn't needn't then that's ok - gdb won't be able to
5607 distinguish us from a non-flat function but there won't (and shouldn't)
5608 be any differences anyway. The return pc is saved (if necessary) right
5609 after %i7 so gdb won't have to look too far to find it. */
5612 unsigned int reg_offset
= current_frame_info
.reg_offset
;
5613 char *fp_str
= reg_names
[FRAME_POINTER_REGNUM
];
5614 char *t1_str
= "%g1";
5616 /* Things get a little tricky if local variables take up more than ~4096
5617 bytes and outgoing arguments take up more than ~4096 bytes. When that
5618 happens, the register save area can't be accessed from either end of
5619 the frame. Handle this by decrementing %sp to the start of the gp
5620 register save area, save the regs, update %i7, and then set %sp to its
5621 final value. Given that we only have one scratch register to play
5622 with it is the cheapest solution, and it helps gdb out as it won't
5623 slow down recognition of flat functions.
5624 Don't change the order of insns emitted here without checking with
5625 the gdb folk first. */
5627 /* Is the entire register save area offsettable from %sp? */
5628 if (reg_offset
< 4096 - 64 * UNITS_PER_WORD
)
5632 fprintf (file
, "\tadd %s,%d,%s\n",
5633 sp_str
, -size
, sp_str
);
5634 if (gmask
& FRAME_POINTER_MASK
)
5636 fprintf (file
, "\tst %s,[%s+%d]\n",
5637 fp_str
, sp_str
, reg_offset
);
5638 fprintf (file
, "\tsub %s,%d,%s\t%s# set up frame pointer\n",
5639 sp_str
, -size
, fp_str
, ASM_COMMENT_START
);
5645 fprintf (file
, "\tset %d,%s\n\tsub %s,%s,%s\n",
5646 size
, t1_str
, sp_str
, t1_str
, sp_str
);
5647 if (gmask
& FRAME_POINTER_MASK
)
5649 fprintf (file
, "\tst %s,[%s+%d]\n",
5650 fp_str
, sp_str
, reg_offset
);
5651 fprintf (file
, "\tadd %s,%s,%s\t%s# set up frame pointer\n",
5652 sp_str
, t1_str
, fp_str
, ASM_COMMENT_START
);
5656 if (dwarf2out_do_frame ())
5658 char *l
= dwarf2out_cfi_label ();
5659 if (gmask
& FRAME_POINTER_MASK
)
5661 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
,
5662 reg_offset
- 4 - size
);
5663 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, 0);
5666 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, size
);
5668 if (gmask
& RETURN_ADDR_MASK
)
5670 fprintf (file
, "\tst %s,[%s+%d]\n",
5671 reg_names
[RETURN_ADDR_REGNUM
], sp_str
, reg_offset
);
5672 if (dwarf2out_do_frame ())
5673 dwarf2out_return_save ("", reg_offset
- size
);
5676 sparc_flat_save_restore (file
, sp_str
, reg_offset
,
5677 gmask
& ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
5678 current_frame_info
.fmask
,
5679 "st", "std", -size
);
5683 /* Subtract %sp in two steps, but make sure there is always a
5684 64 byte register save area, and %sp is properly aligned. */
5685 /* Amount to decrement %sp by, the first time. */
5686 unsigned int size1
= ((size
- reg_offset
+ 64) + 15) & -16;
5687 /* Offset to register save area from %sp. */
5688 unsigned int offset
= size1
- (size
- reg_offset
);
5692 fprintf (file
, "\tadd %s,%d,%s\n",
5693 sp_str
, -size1
, sp_str
);
5694 if (gmask
& FRAME_POINTER_MASK
)
5696 fprintf (file
, "\tst %s,[%s+%d]\n\tsub %s,%d,%s\t%s# set up frame pointer\n",
5697 fp_str
, sp_str
, offset
, sp_str
, -size1
, fp_str
,
5704 fprintf (file
, "\tset %d,%s\n\tsub %s,%s,%s\n",
5705 size1
, t1_str
, sp_str
, t1_str
, sp_str
);
5706 if (gmask
& FRAME_POINTER_MASK
)
5708 fprintf (file
, "\tst %s,[%s+%d]\n\tadd %s,%s,%s\t%s# set up frame pointer\n",
5709 fp_str
, sp_str
, offset
, sp_str
, t1_str
, fp_str
,
5714 if (dwarf2out_do_frame ())
5716 char *l
= dwarf2out_cfi_label ();
5717 if (gmask
& FRAME_POINTER_MASK
)
5719 dwarf2out_reg_save (l
, FRAME_POINTER_REGNUM
,
5720 offset
- 4 - size1
);
5721 dwarf2out_def_cfa (l
, FRAME_POINTER_REGNUM
, 0);
5724 dwarf2out_def_cfa (l
, STACK_POINTER_REGNUM
, size1
);
5726 if (gmask
& RETURN_ADDR_MASK
)
5728 fprintf (file
, "\tst %s,[%s+%d]\n",
5729 reg_names
[RETURN_ADDR_REGNUM
], sp_str
, offset
);
5730 if (dwarf2out_do_frame ())
5731 /* offset - size1 == reg_offset - size
5732 if reg_offset were updated above like offset. */
5733 dwarf2out_return_save ("", offset
- size1
);
5736 sparc_flat_save_restore (file
, sp_str
, offset
,
5737 gmask
& ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
5738 current_frame_info
.fmask
,
5739 "st", "std", -size1
);
5740 fprintf (file
, "\tset %d,%s\n\tsub %s,%s,%s\n",
5741 size
- size1
, t1_str
, sp_str
, t1_str
, sp_str
);
5742 if (dwarf2out_do_frame ())
5743 if (! (gmask
& FRAME_POINTER_MASK
))
5744 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, size
);
5748 fprintf (file
, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START
);
5751 /* Do any necessary cleanup after a function to restore stack, frame,
5755 sparc_flat_output_function_epilogue (file
, size
)
5759 rtx epilogue_delay
= current_function_epilogue_delay_list
;
5760 int noepilogue
= FALSE
;
5762 /* This is only for the human reader. */
5763 fprintf (file
, "\t%s#EPILOGUE#\n", ASM_COMMENT_START
);
5765 /* The epilogue does not depend on any registers, but the stack
5766 registers, so we assume that if we have 1 pending nop, it can be
5767 ignored, and 2 it must be filled (2 nops occur for integer
5768 multiply and divide). */
5770 size
= SPARC_STACK_ALIGN (size
);
5771 size
= (!current_frame_info
.initialized
5772 ? sparc_flat_compute_frame_size (size
)
5773 : current_frame_info
.total_size
);
5775 if (size
== 0 && epilogue_delay
== 0)
5777 rtx insn
= get_last_insn ();
5779 /* If the last insn was a BARRIER, we don't have to write any code
5780 because a jump (aka return) was put there. */
5781 if (GET_CODE (insn
) == NOTE
)
5782 insn
= prev_nonnote_insn (insn
);
5783 if (insn
&& GET_CODE (insn
) == BARRIER
)
5789 unsigned int reg_offset
= current_frame_info
.reg_offset
;
5791 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
5792 char *fp_str
= reg_names
[FRAME_POINTER_REGNUM
];
5793 char *t1_str
= "%g1";
5795 /* In the reload sequence, we don't need to fill the load delay
5796 slots for most of the loads, also see if we can fill the final
5797 delay slot if not otherwise filled by the reload sequence. */
5800 fprintf (file
, "\tset %d,%s\n", size
, t1_str
);
5802 if (frame_pointer_needed
)
5805 fprintf (file
,"\tsub %s,%s,%s\t\t%s# sp not trusted here\n",
5806 fp_str
, t1_str
, sp_str
, ASM_COMMENT_START
);
5808 fprintf (file
,"\tsub %s,%d,%s\t\t%s# sp not trusted here\n",
5809 fp_str
, size
, sp_str
, ASM_COMMENT_START
);
5812 /* Is the entire register save area offsettable from %sp? */
5813 if (reg_offset
< 4096 - 64 * UNITS_PER_WORD
)
5819 /* Restore %sp in two steps, but make sure there is always a
5820 64 byte register save area, and %sp is properly aligned. */
5821 /* Amount to increment %sp by, the first time. */
5822 size1
= ((reg_offset
- 64 - 16) + 15) & -16;
5823 /* Offset to register save area from %sp. */
5824 reg_offset
= size1
- reg_offset
;
5826 fprintf (file
, "\tset %d,%s\n\tadd %s,%s,%s\n",
5827 size1
, t1_str
, sp_str
, t1_str
, sp_str
);
5830 /* We must restore the frame pointer and return address reg first
5831 because they are treated specially by the prologue output code. */
5832 if (current_frame_info
.gmask
& FRAME_POINTER_MASK
)
5834 fprintf (file
, "\tld [%s+%d],%s\n",
5835 sp_str
, reg_offset
, fp_str
);
5838 if (current_frame_info
.gmask
& RETURN_ADDR_MASK
)
5840 fprintf (file
, "\tld [%s+%d],%s\n",
5841 sp_str
, reg_offset
, reg_names
[RETURN_ADDR_REGNUM
]);
5845 /* Restore any remaining saved registers. */
5846 sparc_flat_save_restore (file
, sp_str
, reg_offset
,
5847 current_frame_info
.gmask
& ~(FRAME_POINTER_MASK
| RETURN_ADDR_MASK
),
5848 current_frame_info
.fmask
,
5851 /* If we had to increment %sp in two steps, record it so the second
5852 restoration in the epilogue finishes up. */
5857 fprintf (file
, "\tset %d,%s\n",
5861 if (current_function_returns_struct
)
5862 fprintf (file
, "\tjmp %%o7+12\n");
5864 fprintf (file
, "\tretl\n");
5866 /* If the only register saved is the return address, we need a
5867 nop, unless we have an instruction to put into it. Otherwise
5868 we don't since reloading multiple registers doesn't reference
5869 the register being loaded. */
5875 final_scan_insn (XEXP (epilogue_delay
, 0), file
, 1, -2, 1);
5878 else if (size
> 4095)
5879 fprintf (file
, "\tadd %s,%s,%s\n", sp_str
, t1_str
, sp_str
);
5882 fprintf (file
, "\tadd %s,%d,%s\n", sp_str
, size
, sp_str
);
5885 fprintf (file
, "\tnop\n");
5888 /* Reset state info for each function. */
5889 current_frame_info
= zero_frame_info
;
5892 /* Define the number of delay slots needed for the function epilogue.
5894 On the sparc, we need a slot if either no stack has been allocated,
5895 or the only register saved is the return register. */
5898 sparc_flat_epilogue_delay_slots ()
5900 if (!current_frame_info
.initialized
)
5901 (void) sparc_flat_compute_frame_size (get_frame_size ());
5903 if (current_frame_info
.total_size
== 0)
5909 /* Return true is TRIAL is a valid insn for the epilogue delay slot.
5910 Any single length instruction which doesn't reference the stack or frame
5914 sparc_flat_eligible_for_epilogue_delay (trial
, slot
)
5918 rtx pat
= PATTERN (trial
);
5920 if (get_attr_length (trial
) != 1)
5923 /* If %g0 is live, there are lots of things we can't handle.
5924 Rather than trying to find them all now, let's punt and only
5925 optimize things as necessary. */
5929 if (! reg_mentioned_p (stack_pointer_rtx
, pat
)
5930 && ! reg_mentioned_p (frame_pointer_rtx
, pat
))
5936 /* Adjust the cost of a scheduling dependency. Return the new cost of
5937 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
5940 supersparc_adjust_cost (insn
, link
, dep_insn
, cost
)
5946 enum attr_type insn_type
;
5948 if (! recog_memoized (insn
))
5951 insn_type
= get_attr_type (insn
);
5953 if (REG_NOTE_KIND (link
) == 0)
5955 /* Data dependency; DEP_INSN writes a register that INSN reads some
5958 /* if a load, then the dependence must be on the memory address;
5959 add an extra 'cycle'. Note that the cost could be two cycles
5960 if the reg was written late in an instruction group; we can't tell
5962 if (insn_type
== TYPE_LOAD
|| insn_type
== TYPE_FPLOAD
)
5965 /* Get the delay only if the address of the store is the dependence. */
5966 if (insn_type
== TYPE_STORE
|| insn_type
== TYPE_FPSTORE
)
5968 rtx pat
= PATTERN(insn
);
5969 rtx dep_pat
= PATTERN (dep_insn
);
5971 if (GET_CODE (pat
) != SET
|| GET_CODE (dep_pat
) != SET
)
5972 return cost
; /* This shouldn't happen! */
5974 /* The dependency between the two instructions was on the data that
5975 is being stored. Assume that this implies that the address of the
5976 store is not dependent. */
5977 if (rtx_equal_p (SET_DEST (dep_pat
), SET_SRC (pat
)))
5980 return cost
+ 3; /* An approximation. */
5983 /* A shift instruction cannot receive its data from an instruction
5984 in the same cycle; add a one cycle penalty. */
5985 if (insn_type
== TYPE_SHIFT
)
5986 return cost
+ 3; /* Split before cascade into shift. */
5990 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
5991 INSN writes some cycles later. */
5993 /* These are only significant for the fpu unit; writing a fp reg before
5994 the fpu has finished with it stalls the processor. */
5996 /* Reusing an integer register causes no problems. */
5997 if (insn_type
== TYPE_IALU
|| insn_type
== TYPE_SHIFT
)