1 ;;- Machine description for GNU compiler, ns32000 Version
2 ;; Copyright (C) 1988, 1994, 1996, 1998 Free Software Foundation, Inc.
3 ;; Contributed by Michael Tiemann (tiemann@cygnus.com)
5 ;; This file is part of GNU CC.
7 ;; GNU CC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 2, or (at your option)
12 ;; GNU CC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GNU CC; see the file COPYING. If not, write to
19 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
20 ;; Boston, MA 02111-1307, USA.
24 ;; Insert no-op between an insn with memory read-write operands
25 ;; following by a scale-indexing operation.
26 ;; The Sequent assembler does not allow addresses to be used
27 ;; except in insns which explicitly compute an effective address.
28 ;; I.e., one cannot say "cmpd _p,@_x"
29 ;; Implement unsigned multiplication??
31 ;;- Instruction patterns. When multiple patterns apply,
32 ;;- the first one in the file is chosen.
34 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
36 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
37 ;;- updates for most instructions.
39 ;; We don't want to allow a constant operand for test insns because
40 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
41 ;; be folded while optimizing anyway.
45 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
48 { cc_status.flags |= CC_REVERSED;
49 operands[1] = const0_rtx;
50 return \"cmpqd %1,%0\"; }")
54 (match_operand:HI 0 "nonimmediate_operand" "g"))]
57 { cc_status.flags |= CC_REVERSED;
58 operands[1] = const0_rtx;
59 return \"cmpqw %1,%0\"; }")
63 (match_operand:QI 0 "nonimmediate_operand" "g"))]
66 { cc_status.flags |= CC_REVERSED;
67 operands[1] = const0_rtx;
68 return \"cmpqb %1,%0\"; }")
72 (match_operand:DF 0 "general_operand" "fmF"))]
75 { cc_status.flags |= CC_REVERSED;
76 operands[1] = CONST0_RTX (DFmode);
77 return \"cmpl %1,%0\"; }")
81 (match_operand:SF 0 "general_operand" "fmF"))]
84 { cc_status.flags |= CC_REVERSED;
85 operands[1] = CONST0_RTX (SFmode);
86 return \"cmpf %1,%0\"; }")
90 (compare (match_operand:SI 0 "nonimmediate_operand" "rmn")
91 (match_operand:SI 1 "general_operand" "rmn")))]
95 if (GET_CODE (operands[1]) == CONST_INT)
97 int i = INTVAL (operands[1]);
98 if (i <= 7 && i >= -8)
100 cc_status.flags |= CC_REVERSED;
101 return \"cmpqd %1,%0\";
104 cc_status.flags &= ~CC_REVERSED;
105 if (GET_CODE (operands[0]) == CONST_INT)
107 int i = INTVAL (operands[0]);
108 if (i <= 7 && i >= -8)
109 return \"cmpqd %0,%1\";
111 return \"cmpd %0,%1\";
116 (compare (match_operand:HI 0 "nonimmediate_operand" "g")
117 (match_operand:HI 1 "general_operand" "g")))]
121 if (GET_CODE (operands[1]) == CONST_INT)
123 short i = INTVAL (operands[1]);
124 if (i <= 7 && i >= -8)
126 cc_status.flags |= CC_REVERSED;
127 if (INTVAL (operands[1]) > 7)
128 operands[1] = GEN_INT (i);
129 return \"cmpqw %1,%0\";
132 cc_status.flags &= ~CC_REVERSED;
133 if (GET_CODE (operands[0]) == CONST_INT)
135 short i = INTVAL (operands[0]);
136 if (i <= 7 && i >= -8)
138 if (INTVAL (operands[0]) > 7)
139 operands[0] = GEN_INT (i);
140 return \"cmpqw %0,%1\";
143 return \"cmpw %0,%1\";
148 (compare (match_operand:QI 0 "nonimmediate_operand" "g")
149 (match_operand:QI 1 "general_operand" "g")))]
153 if (GET_CODE (operands[1]) == CONST_INT)
155 char i = INTVAL (operands[1]);
156 if (i <= 7 && i >= -8)
158 cc_status.flags |= CC_REVERSED;
159 if (INTVAL (operands[1]) > 7)
160 operands[1] = GEN_INT (i);
161 return \"cmpqb %1,%0\";
164 cc_status.flags &= ~CC_REVERSED;
165 if (GET_CODE (operands[0]) == CONST_INT)
167 char i = INTVAL (operands[0]);
168 if (i <= 7 && i >= -8)
170 if (INTVAL (operands[0]) > 7)
171 operands[0] = GEN_INT (i);
172 return \"cmpqb %0,%1\";
175 return \"cmpb %0,%1\";
180 (compare (match_operand:DF 0 "general_operand" "fmF")
181 (match_operand:DF 1 "general_operand" "fmF")))]
187 (compare (match_operand:SF 0 "general_operand" "fmF")
188 (match_operand:SF 1 "general_operand" "fmF")))]
193 [(set (match_operand:DF 0 "general_operand" "=fg<")
194 (match_operand:DF 1 "general_operand" "fFg"))]
198 if (FP_REG_P (operands[0]))
200 if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
201 return \"movl %1,%0\";
202 if (REG_P (operands[1]))
205 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
206 output_asm_insn (\"movd %1,tos\", xoperands);
207 output_asm_insn (\"movd %1,tos\", operands);
208 return \"movl tos,%0\";
210 return \"movl %1,%0\";
212 else if (FP_REG_P (operands[1]))
214 if (REG_P (operands[0]))
216 output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
217 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
218 return \"movd tos,%0\";
221 return \"movl %1,%0\";
223 return output_move_double (operands);
227 [(set (match_operand:SF 0 "general_operand" "=fg<")
228 (match_operand:SF 1 "general_operand" "fFg"))]
232 if (FP_REG_P (operands[0]))
234 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
235 return \"movd %1,tos\;movf tos,%0\";
237 return \"movf %1,%0\";
239 else if (FP_REG_P (operands[1]))
241 if (REG_P (operands[0]))
242 return \"movf %1,tos\;movd tos,%0\";
243 return \"movf %1,%0\";
245 #if 0 /* Someone suggested this for the Sequent. Is it needed? */
246 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
247 return \"movf %1,%0\";
249 /* There was a #if 0 around this, but that was erroneous
250 for many machines -- rms. */
251 #ifndef MOVD_FLOAT_OK
252 /* GAS understands floating constants in ordinary movd instructions
253 but other assemblers might object. */
254 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
256 union {int i[2]; float f; double d;} convrt;
257 convrt.i[0] = CONST_DOUBLE_LOW (operands[1]);
258 convrt.i[1] = CONST_DOUBLE_HIGH (operands[1]);
261 /* Is there a better machine-independent way to to this? */
262 operands[1] = GEN_INT (convrt.i[0]);
263 return \"movd %1,%0\";
266 else return \"movd %1,%0\";
270 [(set (match_operand:TI 0 "memory_operand" "=m")
271 (match_operand:TI 1 "memory_operand" "m"))]
276 [(set (match_operand:DI 0 "general_operand" "=g<,*f,g")
277 (match_operand:DI 1 "general_operand" "gF,g,*f"))]
281 if (FP_REG_P (operands[0]))
283 if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
284 return \"movl %1,%0\";
285 if (REG_P (operands[1]))
288 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
289 output_asm_insn (\"movd %1,tos\", xoperands);
290 output_asm_insn (\"movd %1,tos\", operands);
291 return \"movl tos,%0\";
293 return \"movl %1,%0\";
295 else if (FP_REG_P (operands[1]))
297 if (REG_P (operands[0]))
299 output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
300 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
301 return \"movd tos,%0\";
304 return \"movl %1,%0\";
306 return output_move_double (operands);
309 ;; This special case must precede movsi.
312 (match_operand:SI 0 "general_operand" "rmn"))]
317 [(set (match_operand:SI 0 "general_operand" "=g<,g<,*f,g,x")
318 (match_operand:SI 1 "general_operand" "g,?xy,g,*f,rmn"))]
322 extern int flag_pic; \
324 if (FP_REG_P (operands[0]))
326 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
327 return \"movd %1,tos\;movf tos,%0\";
329 return \"movf %1,%0\";
331 else if (FP_REG_P (operands[1]))
333 if (REG_P (operands[0]))
334 return \"movf %1,tos\;movd tos,%0\";
335 return \"movf %1,%0\";
337 if (GET_CODE (operands[0]) == REG
338 && REGNO (operands[0]) == FRAME_POINTER_REGNUM)
339 return \"lprd fp,%1\";
340 if (GET_CODE (operands[1]) == CONST_DOUBLE)
341 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
342 if (GET_CODE (operands[1]) == CONST_INT)
344 int i = INTVAL (operands[1]);
347 if (i <= 7 && i >= -8)
348 return \"movqd %1,%0\";
349 if (i <= 0x1fffffff && i >= -0x20000000)
350 #if defined (GNX_V3) || defined (UTEK_ASM)
351 return \"addr %c1,%0\";
353 return \"addr @%c1,%0\";
355 return \"movd %$%1,%0\";
358 return output_move_dconst(i, \"%$%1,%0\");
360 else if (GET_CODE (operands[1]) == CONST && ! flag_pic)
362 /* Must contain symbols so we don`t know how big it is. In
363 * that case addr might lead to overflow. For PIC symbolic
364 * address loads always have to be done with addr.
366 return \"movd %$%1,%0\";
368 else if (GET_CODE (operands[1]) == REG)
370 if (REGNO (operands[1]) < 16)
371 return \"movd %1,%0\";
372 else if (REGNO (operands[1]) == FRAME_POINTER_REGNUM)
374 if (GET_CODE(operands[0]) == REG)
375 return \"sprd fp,%0\";
377 return \"addr 0(fp),%0\" ;
379 else if (REGNO (operands[1]) == STACK_POINTER_REGNUM)
381 if (GET_CODE(operands[0]) == REG)
382 return \"sprd sp,%0\";
384 return \"addr 0(sp),%0\" ;
388 else if (GET_CODE (operands[1]) == MEM)
389 return \"movd %1,%0\";
391 /* Check if this effective address can be
392 calculated faster by pulling it apart. */
393 if (REG_P (operands[0])
394 && GET_CODE (operands[1]) == MULT
395 && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
396 && (INTVAL (XEXP (operands[1], 1)) == 2
397 || INTVAL (XEXP (operands[1], 1)) == 4))
400 xoperands[0] = operands[0];
401 xoperands[1] = XEXP (operands[1], 0);
402 xoperands[2] = GEN_INT (INTVAL (XEXP (operands[1], 1)) >> 1);
403 return output_shift_insn (xoperands);
405 return \"addr %a1,%0\";
409 [(set (match_operand:HI 0 "general_operand" "=g<,*f,g")
410 (match_operand:HI 1 "general_operand" "g,g,*f"))]
414 if (GET_CODE (operands[1]) == CONST_INT)
416 short i = INTVAL (operands[1]);
417 if (i <= 7 && i >= -8)
419 if (INTVAL (operands[1]) > 7)
420 operands[1] = GEN_INT (i);
421 return \"movqw %1,%0\";
423 return \"movw %1,%0\";
425 else if (FP_REG_P (operands[0]))
427 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
428 return \"movwf %1,tos\;movf tos,%0\";
430 return \"movwf %1,%0\";
432 else if (FP_REG_P (operands[1]))
434 if (REG_P (operands[0]))
435 return \"movf %1,tos\;movd tos,%0\";
436 return \"movf %1,%0\";
439 return \"movw %1,%0\";
442 (define_insn "movstricthi"
443 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+r"))
444 (match_operand:HI 1 "general_operand" "g"))]
448 if (GET_CODE (operands[1]) == CONST_INT
449 && INTVAL(operands[1]) <= 7 && INTVAL(operands[1]) >= -8)
450 return \"movqw %1,%0\";
451 return \"movw %1,%0\";
455 [(set (match_operand:QI 0 "general_operand" "=g<,*f,g")
456 (match_operand:QI 1 "general_operand" "g,g,*f"))]
459 { if (GET_CODE (operands[1]) == CONST_INT)
461 char char_val = (char)INTVAL (operands[1]);
462 if (char_val <= 7 && char_val >= -8)
464 if (INTVAL (operands[1]) > 7)
465 operands[1] = GEN_INT (char_val);
466 return \"movqb %1,%0\";
468 return \"movb %1,%0\";
470 else if (FP_REG_P (operands[0]))
472 if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
473 return \"movbf %1,tos\;movf tos,%0\";
475 return \"movbf %1,%0\";
477 else if (FP_REG_P (operands[1]))
479 if (REG_P (operands[0]))
480 return \"movf %1,tos\;movd tos,%0\";
481 return \"movf %1,%0\";
484 return \"movb %1,%0\";
487 (define_insn "movstrictqi"
488 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+r"))
489 (match_operand:QI 1 "general_operand" "g"))]
493 if (GET_CODE (operands[1]) == CONST_INT
494 && INTVAL(operands[1]) < 8 && INTVAL(operands[1]) > -9)
495 return \"movqb %1,%0\";
496 return \"movb %1,%0\";
499 ;; This is here to accept 4 arguments and pass the first 3 along
500 ;; to the movstrsi1 pattern that really does the work.
501 (define_expand "movstrsi"
502 [(set (match_operand:BLK 0 "general_operand" "=g")
503 (match_operand:BLK 1 "general_operand" "g"))
504 (use (match_operand:SI 2 "general_operand" "rmn"))
505 (match_operand 3 "" "")]
508 emit_insn (gen_movstrsi1 (operands[0], operands[1], operands[2]));
512 ;; The definition of this insn does not really explain what it does,
513 ;; but it should suffice
514 ;; that anything generated as this insn will be recognized as one
515 ;; and that it won't successfully combine with anything.
516 (define_insn "movstrsi1"
517 [(set (match_operand:BLK 0 "general_operand" "=g")
518 (match_operand:BLK 1 "general_operand" "g"))
519 (use (match_operand:SI 2 "general_operand" "rmn"))
522 (clobber (reg:SI 2))]
526 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
528 operands[0] = XEXP (operands[0], 0);
529 operands[1] = XEXP (operands[1], 0);
530 if (GET_CODE (operands[0]) == MEM)
531 if (GET_CODE (operands[1]) == MEM)
532 output_asm_insn (\"movd %0,r2\;movd %1,r1\", operands);
534 output_asm_insn (\"movd %0,r2\;addr %a1,r1\", operands);
535 else if (GET_CODE (operands[1]) == MEM)
536 output_asm_insn (\"addr %a0,r2\;movd %1,r1\", operands);
538 output_asm_insn (\"addr %a0,r2\;addr %a1,r1\", operands);
541 if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0)
543 operands[2] = GEN_INT (INTVAL (operands[2]) >> 2);
544 if ((unsigned) INTVAL (operands[2]) <= 7)
545 return \"movqd %2,r0\;movsd $0\";
547 return \"movd %2,r0\;movsd $0\";
551 return \"movd %2,r0\;movsb $0\";
554 if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0)
556 operands[2] = GEN_INT (INTVAL (operands[2]) >> 2);
557 if ((unsigned) INTVAL (operands[2]) <= 7)
558 return \"movqd %2,r0\;movsd\";
560 return \"movd %2,r0\;movsd\";
564 return \"movd %2,r0\;movsb\";
569 ;; Extension and truncation insns.
570 ;; Those for integer source operand
571 ;; are ordered widest source type first.
573 (define_insn "truncsiqi2"
574 [(set (match_operand:QI 0 "general_operand" "=g<")
575 (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "rmn")))]
579 (define_insn "truncsihi2"
580 [(set (match_operand:HI 0 "general_operand" "=g<")
581 (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "rmn")))]
585 (define_insn "trunchiqi2"
586 [(set (match_operand:QI 0 "general_operand" "=g<")
587 (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
591 (define_insn "extendhisi2"
592 [(set (match_operand:SI 0 "general_operand" "=g<")
593 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
597 (define_insn "extendqihi2"
598 [(set (match_operand:HI 0 "general_operand" "=g<")
599 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
603 (define_insn "extendqisi2"
604 [(set (match_operand:SI 0 "general_operand" "=g<")
605 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
609 (define_insn "extendsfdf2"
610 [(set (match_operand:DF 0 "general_operand" "=fm<")
611 (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))]
615 (define_insn "truncdfsf2"
616 [(set (match_operand:SF 0 "general_operand" "=fm<")
617 (float_truncate:SF (match_operand:DF 1 "general_operand" "fmF")))]
621 (define_insn "zero_extendhisi2"
622 [(set (match_operand:SI 0 "general_operand" "=g<")
623 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
627 (define_insn "zero_extendqihi2"
628 [(set (match_operand:HI 0 "general_operand" "=g<")
629 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
633 (define_insn "zero_extendqisi2"
634 [(set (match_operand:SI 0 "general_operand" "=g<")
635 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
639 ;; Fix-to-float conversion insns.
640 ;; Note that the ones that start with SImode come first.
641 ;; That is so that an operand that is a CONST_INT
642 ;; (and therefore lacks a specific machine mode).
643 ;; will be recognized as SImode (which is always valid)
644 ;; rather than as QImode or HImode.
646 ;; Rumor has it that the National part does not correctly convert
647 ;; constant ints to floats. This conversion is therefore disabled.
648 ;; A register must be used to perform the conversion.
650 (define_insn "floatsisf2"
651 [(set (match_operand:SF 0 "general_operand" "=fm<")
652 (float:SF (match_operand:SI 1 "general_operand" "rm")))]
656 (define_insn "floatsidf2"
657 [(set (match_operand:DF 0 "general_operand" "=fm<")
658 (float:DF (match_operand:SI 1 "general_operand" "rm")))]
662 (define_insn "floathisf2"
663 [(set (match_operand:SF 0 "general_operand" "=fm<")
664 (float:SF (match_operand:HI 1 "general_operand" "rm")))]
668 (define_insn "floathidf2"
669 [(set (match_operand:DF 0 "general_operand" "=fm<")
670 (float:DF (match_operand:HI 1 "general_operand" "rm")))]
674 (define_insn "floatqisf2"
675 [(set (match_operand:SF 0 "general_operand" "=fm<")
676 (float:SF (match_operand:QI 1 "general_operand" "rm")))]
680 ; Some assemblers warn that this insn doesn't work.
681 ; Maybe they know something we don't.
682 ;(define_insn "floatqidf2"
683 ; [(set (match_operand:DF 0 "general_operand" "=fm<")
684 ; (float:DF (match_operand:QI 1 "general_operand" "rm")))]
688 ;; Float-to-fix conversion insns.
689 ;; The sequent compiler always generates "trunc" insns.
691 (define_insn "fixsfqi2"
692 [(set (match_operand:QI 0 "general_operand" "=g<")
693 (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
697 (define_insn "fixsfhi2"
698 [(set (match_operand:HI 0 "general_operand" "=g<")
699 (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
703 (define_insn "fixsfsi2"
704 [(set (match_operand:SI 0 "general_operand" "=g<")
705 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
709 (define_insn "fixdfqi2"
710 [(set (match_operand:QI 0 "general_operand" "=g<")
711 (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
715 (define_insn "fixdfhi2"
716 [(set (match_operand:HI 0 "general_operand" "=g<")
717 (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
721 (define_insn "fixdfsi2"
722 [(set (match_operand:SI 0 "general_operand" "=g<")
723 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
729 (define_insn "fixunssfqi2"
730 [(set (match_operand:QI 0 "general_operand" "=g<")
731 (unsigned_fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
735 (define_insn "fixunssfhi2"
736 [(set (match_operand:HI 0 "general_operand" "=g<")
737 (unsigned_fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
741 (define_insn "fixunssfsi2"
742 [(set (match_operand:SI 0 "general_operand" "=g<")
743 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
747 (define_insn "fixunsdfqi2"
748 [(set (match_operand:QI 0 "general_operand" "=g<")
749 (unsigned_fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
753 (define_insn "fixunsdfhi2"
754 [(set (match_operand:HI 0 "general_operand" "=g<")
755 (unsigned_fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
759 (define_insn "fixunsdfsi2"
760 [(set (match_operand:SI 0 "general_operand" "=g<")
761 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
765 ;;; These are not yet used by GCC
766 (define_insn "fix_truncsfqi2"
767 [(set (match_operand:QI 0 "general_operand" "=g<")
768 (fix:QI (match_operand:SF 1 "general_operand" "fm")))]
772 (define_insn "fix_truncsfhi2"
773 [(set (match_operand:HI 0 "general_operand" "=g<")
774 (fix:HI (match_operand:SF 1 "general_operand" "fm")))]
778 (define_insn "fix_truncsfsi2"
779 [(set (match_operand:SI 0 "general_operand" "=g<")
780 (fix:SI (match_operand:SF 1 "general_operand" "fm")))]
784 (define_insn "fix_truncdfqi2"
785 [(set (match_operand:QI 0 "general_operand" "=g<")
786 (fix:QI (match_operand:DF 1 "general_operand" "fm")))]
790 (define_insn "fix_truncdfhi2"
791 [(set (match_operand:HI 0 "general_operand" "=g<")
792 (fix:HI (match_operand:DF 1 "general_operand" "fm")))]
796 (define_insn "fix_truncdfsi2"
797 [(set (match_operand:SI 0 "general_operand" "=g<")
798 (fix:SI (match_operand:DF 1 "general_operand" "fm")))]
802 ;;- All kinds of add instructions.
804 (define_insn "adddf3"
805 [(set (match_operand:DF 0 "general_operand" "=fm")
806 (plus:DF (match_operand:DF 1 "general_operand" "%0")
807 (match_operand:DF 2 "general_operand" "fmF")))]
812 (define_insn "addsf3"
813 [(set (match_operand:SF 0 "general_operand" "=fm")
814 (plus:SF (match_operand:SF 1 "general_operand" "%0")
815 (match_operand:SF 2 "general_operand" "fmF")))]
822 (match_operand:SI 0 "immediate_operand" "i")))]
823 "GET_CODE (operands[0]) == CONST_INT"
826 #ifndef SEQUENT_ADJUST_STACK
828 if (INTVAL (operands[0]) == 8)
829 return \"cmpd tos,tos\";
830 if (TARGET_32532 || TARGET_32332)
831 if (INTVAL (operands[0]) == 4)
832 return \"cmpqd %$0,tos\";
836 if (INTVAL (operands[0]) < 64 && INTVAL (operands[0]) > -64)
837 return \"adjspb %$%n0\";
838 else if (INTVAL (operands[0]) < 8192 && INTVAL (operands[0]) >= -8192)
839 return \"adjspw %$%n0\";
841 return \"adjspd %$%n0\";
845 [(set (match_operand:SI 0 "general_operand" "=g<")
847 (match_operand:SI 1 "immediate_operand" "i")))]
848 "GET_CODE (operands[1]) == CONST_INT"
852 [(set (match_operand:SI 0 "general_operand" "=g<")
854 (match_operand:SI 1 "immediate_operand" "i")))]
855 "GET_CODE (operands[1]) == CONST_INT"
858 (define_insn "adddi3"
859 [(set (match_operand:DI 0 "general_operand" "=ro")
860 (plus:DI (match_operand:DI 1 "general_operand" "%0")
861 (match_operand:DI 2 "general_operand" "ron")))]
865 rtx low[3], high[3], xops[4];
866 split_di (operands, 3, low, high);
872 if (GET_CODE (xops[2]) == CONST_INT)
874 int i = INTVAL (xops[2]);
876 if (i <= 7 && i >= -8)
880 i = INTVAL (xops[3]);
881 if (i <= 7 && i >= -8)
882 output_asm_insn (\"addqd %$%3,%1\", xops);
884 output_asm_insn (\"addd %$%3,%1\", xops);
888 output_asm_insn (\"addqd %$%2,%0\", xops);
889 output_asm_insn (\"addcd %$%3,%1\", xops);
894 output_asm_insn (\"addd %2,%0\", xops);
895 output_asm_insn (\"addcd %3,%1\", xops);
899 (define_insn "addsi3"
900 [(set (match_operand:SI 0 "general_operand" "=g,=g&<")
901 (plus:SI (match_operand:SI 1 "general_operand" "%0,r")
902 (match_operand:SI 2 "general_operand" "rmn,n")))]
906 if (which_alternative == 1)
908 int i = INTVAL (operands[2]);
909 if (NS32K_DISPLACEMENT_P (i))
910 return \"addr %c2(%1),%0\";
912 return \"movd %1,%0\;addd %2,%0\";
914 if (GET_CODE (operands[2]) == CONST_INT)
916 int i = INTVAL (operands[2]);
918 if (i <= 7 && i >= -8)
919 return \"addqd %2,%0\";
920 else if (! TARGET_32532 && GET_CODE (operands[0]) == REG
921 && i <= 0x1fffffff && i >= -0x20000000)
922 return \"addr %c2(%0),%0\";
924 return \"addd %2,%0\";
927 (define_insn "addhi3"
928 [(set (match_operand:HI 0 "general_operand" "=g")
929 (plus:HI (match_operand:HI 1 "general_operand" "%0")
930 (match_operand:HI 2 "general_operand" "g")))]
933 { if (GET_CODE (operands[2]) == CONST_INT)
935 int i = INTVAL (operands[2]);
936 if (i <= 7 && i >= -8)
937 return \"addqw %2,%0\";
939 return \"addw %2,%0\";
943 [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
944 (plus:HI (match_operand:HI 1 "general_operand" "0")
945 (match_operand:HI 2 "general_operand" "g")))]
949 if (GET_CODE (operands[1]) == CONST_INT
950 && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
951 return \"addqw %2,%0\";
952 return \"addw %2,%0\";
955 (define_insn "addqi3"
956 [(set (match_operand:QI 0 "general_operand" "=g")
957 (plus:QI (match_operand:QI 1 "general_operand" "%0")
958 (match_operand:QI 2 "general_operand" "g")))]
961 { if (GET_CODE (operands[2]) == CONST_INT)
963 int i = INTVAL (operands[2]);
964 if (i <= 7 && i >= -8)
965 return \"addqb %2,%0\";
967 return \"addb %2,%0\";
971 [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
972 (plus:QI (match_operand:QI 1 "general_operand" "0")
973 (match_operand:QI 2 "general_operand" "g")))]
977 if (GET_CODE (operands[1]) == CONST_INT
978 && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
979 return \"addqb %2,%0\";
980 return \"addb %2,%0\";
983 ;;- All kinds of subtract instructions.
985 (define_insn "subdf3"
986 [(set (match_operand:DF 0 "general_operand" "=fm")
987 (minus:DF (match_operand:DF 1 "general_operand" "0")
988 (match_operand:DF 2 "general_operand" "fmF")))]
992 (define_insn "subsf3"
993 [(set (match_operand:SF 0 "general_operand" "=fm")
994 (minus:SF (match_operand:SF 1 "general_operand" "0")
995 (match_operand:SF 2 "general_operand" "fmF")))]
1001 (minus:SI (reg:SI 17)
1002 (match_operand:SI 0 "immediate_operand" "i")))]
1003 "GET_CODE (operands[0]) == CONST_INT"
1006 if (! TARGET_32532 && GET_CODE(operands[0]) == CONST_INT
1007 && INTVAL(operands[0]) < 64 && INTVAL(operands[0]) > -64)
1008 return \"adjspb %$%0\";
1009 return \"adjspd %$%0\";
1012 (define_insn "subdi3"
1013 [(set (match_operand:DI 0 "general_operand" "=ro")
1014 (minus:DI (match_operand:DI 1 "general_operand" "0")
1015 (match_operand:DI 2 "general_operand" "ron")))]
1019 rtx low[3], high[3], xops[4];
1020 split_di (operands, 3, low, high);
1026 if (GET_CODE (xops[2]) == CONST_INT)
1028 int i = INTVAL (xops[2]);
1030 if (i <= 8 && i >= -7)
1034 i = INTVAL (xops[3]);
1035 if (i <= 8 && i >= -7)
1036 output_asm_insn (\"addqd %$%n3,%1\", xops);
1038 output_asm_insn (\"subd %$%3,%1\", xops);
1042 output_asm_insn (\"addqd %$%n2,%0\", xops);
1043 output_asm_insn (\"subcd %$%3,%1\", xops);
1048 output_asm_insn (\"subd %2,%0\", xops);
1049 output_asm_insn (\"subcd %3,%1\", xops);
1053 (define_insn "subsi3"
1054 [(set (match_operand:SI 0 "general_operand" "=g")
1055 (minus:SI (match_operand:SI 1 "general_operand" "0")
1056 (match_operand:SI 2 "general_operand" "rmn")))]
1059 { if (GET_CODE (operands[2]) == CONST_INT)
1061 int i = INTVAL (operands[2]);
1063 if (i <= 8 && i >= -7)
1064 return \"addqd %$%n2,%0\";
1066 return \"subd %2,%0\";
1069 (define_insn "subhi3"
1070 [(set (match_operand:HI 0 "general_operand" "=g")
1071 (minus:HI (match_operand:HI 1 "general_operand" "0")
1072 (match_operand:HI 2 "general_operand" "g")))]
1075 { if (GET_CODE (operands[2]) == CONST_INT)
1077 int i = INTVAL (operands[2]);
1079 if (i <= 8 && i >= -7)
1080 return \"addqw %$%n2,%0\";
1082 return \"subw %2,%0\";
1086 [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
1087 (minus:HI (match_operand:HI 1 "general_operand" "0")
1088 (match_operand:HI 2 "general_operand" "g")))]
1092 if (GET_CODE (operands[1]) == CONST_INT
1093 && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
1094 return \"addqw %$%n2,%0\";
1095 return \"subw %2,%0\";
1098 (define_insn "subqi3"
1099 [(set (match_operand:QI 0 "general_operand" "=g")
1100 (minus:QI (match_operand:QI 1 "general_operand" "0")
1101 (match_operand:QI 2 "general_operand" "g")))]
1104 { if (GET_CODE (operands[2]) == CONST_INT)
1106 int i = INTVAL (operands[2]);
1108 if (i <= 8 && i >= -7)
1109 return \"addqb %$%n2,%0\";
1111 return \"subb %2,%0\";
1115 [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
1116 (minus:QI (match_operand:QI 1 "general_operand" "0")
1117 (match_operand:QI 2 "general_operand" "g")))]
1121 if (GET_CODE (operands[1]) == CONST_INT
1122 && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
1123 return \"addqb %$%n2,%0\";
1124 return \"subb %2,%0\";
1127 ;;- Multiply instructions.
1129 (define_insn "muldf3"
1130 [(set (match_operand:DF 0 "general_operand" "=fm")
1131 (mult:DF (match_operand:DF 1 "general_operand" "%0")
1132 (match_operand:DF 2 "general_operand" "fmF")))]
1136 (define_insn "mulsf3"
1137 [(set (match_operand:SF 0 "general_operand" "=fm")
1138 (mult:SF (match_operand:SF 1 "general_operand" "%0")
1139 (match_operand:SF 2 "general_operand" "fmF")))]
1143 (define_insn "mulsi3"
1144 [(set (match_operand:SI 0 "general_operand" "=g")
1145 (mult:SI (match_operand:SI 1 "general_operand" "%0")
1146 (match_operand:SI 2 "general_operand" "rmn")))]
1150 (define_insn "mulhi3"
1151 [(set (match_operand:HI 0 "general_operand" "=g")
1152 (mult:HI (match_operand:HI 1 "general_operand" "%0")
1153 (match_operand:HI 2 "general_operand" "g")))]
1157 (define_insn "mulqi3"
1158 [(set (match_operand:QI 0 "general_operand" "=g")
1159 (mult:QI (match_operand:QI 1 "general_operand" "%0")
1160 (match_operand:QI 2 "general_operand" "g")))]
1164 (define_insn "umulsidi3"
1165 [(set (match_operand:DI 0 "general_operand" "=g")
1166 (mult:DI (zero_extend:DI
1167 (match_operand:SI 1 "nonimmediate_operand" "0"))
1169 (match_operand:SI 2 "nonimmediate_operand" "rmn"))))]
1173 ;;- Divide instructions.
1175 (define_insn "divdf3"
1176 [(set (match_operand:DF 0 "general_operand" "=fm")
1177 (div:DF (match_operand:DF 1 "general_operand" "0")
1178 (match_operand:DF 2 "general_operand" "fmF")))]
1182 (define_insn "divsf3"
1183 [(set (match_operand:SF 0 "general_operand" "=fm")
1184 (div:SF (match_operand:SF 1 "general_operand" "0")
1185 (match_operand:SF 2 "general_operand" "fmF")))]
1189 (define_insn "divsi3"
1190 [(set (match_operand:SI 0 "general_operand" "=g")
1191 (div:SI (match_operand:SI 1 "general_operand" "0")
1192 (match_operand:SI 2 "general_operand" "rmn")))]
1196 (define_insn "divhi3"
1197 [(set (match_operand:HI 0 "general_operand" "=g")
1198 (div:HI (match_operand:HI 1 "general_operand" "0")
1199 (match_operand:HI 2 "general_operand" "g")))]
1203 (define_insn "divqi3"
1204 [(set (match_operand:QI 0 "general_operand" "=g")
1205 (div:QI (match_operand:QI 1 "general_operand" "0")
1206 (match_operand:QI 2 "general_operand" "g")))]
1210 (define_insn "udivsi3"
1211 [(set (match_operand:SI 0 "register_operand" "=r")
1212 (udiv:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1213 (match_operand:SI 2 "general_operand" "rmn")))]
1217 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1218 return \"deid %2,%0\;movd %1,%0\";
1221 (define_insn "udivhi3"
1222 [(set (match_operand:HI 0 "register_operand" "=r")
1223 (udiv:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1224 (match_operand:HI 2 "general_operand" "g")))]
1228 operands[1] = gen_rtx_REG (HImode, REGNO (operands[0]) + 1);
1229 return \"deiw %2,%0\;movw %1,%0\";
1232 (define_insn "udivqi3"
1233 [(set (match_operand:QI 0 "register_operand" "=r")
1234 (udiv:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1235 (match_operand:QI 2 "general_operand" "g")))]
1239 operands[1] = gen_rtx_REG (QImode, REGNO (operands[0]) + 1);
1240 return \"deib %2,%0\;movb %1,%0\";
1243 ;; Remainder instructions.
1245 (define_insn "modsi3"
1246 [(set (match_operand:SI 0 "general_operand" "=g")
1247 (mod:SI (match_operand:SI 1 "general_operand" "0")
1248 (match_operand:SI 2 "general_operand" "rmn")))]
1252 (define_insn "modhi3"
1253 [(set (match_operand:HI 0 "general_operand" "=g")
1254 (mod:HI (match_operand:HI 1 "general_operand" "0")
1255 (match_operand:HI 2 "general_operand" "g")))]
1259 (define_insn "modqi3"
1260 [(set (match_operand:QI 0 "general_operand" "=g")
1261 (mod:QI (match_operand:QI 1 "general_operand" "0")
1262 (match_operand:QI 2 "general_operand" "g")))]
1266 (define_insn "umodsi3"
1267 [(set (match_operand:SI 0 "register_operand" "=r")
1268 (umod:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1269 (match_operand:SI 2 "general_operand" "rmn")))]
1273 (define_insn "umodhi3"
1274 [(set (match_operand:HI 0 "register_operand" "=r")
1275 (umod:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1276 (match_operand:HI 2 "general_operand" "g")))]
1280 (define_insn "umodqi3"
1281 [(set (match_operand:QI 0 "register_operand" "=r")
1282 (umod:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1283 (match_operand:QI 2 "general_operand" "g")))]
1287 ; This isn't be usable in its current form.
1288 ;(define_insn "udivmoddisi4"
1289 ; [(set (subreg:SI (match_operand:DI 0 "general_operand" "=r") 1)
1290 ; (udiv:SI (match_operand:DI 1 "general_operand" "0")
1291 ; (match_operand:SI 2 "general_operand" "rmn")))
1292 ; (set (subreg:SI (match_dup 0) 0)
1293 ; (umod:SI (match_dup 1) (match_dup 2)))]
1297 ;;- Logical Instructions: AND
1299 (define_insn "andsi3"
1300 [(set (match_operand:SI 0 "general_operand" "=g")
1301 (and:SI (match_operand:SI 1 "general_operand" "%0")
1302 (match_operand:SI 2 "general_operand" "rmn")))]
1306 if (GET_CODE (operands[2]) == CONST_INT)
1308 if ((INTVAL (operands[2]) | 0xff) == 0xffffffff)
1310 if (INTVAL (operands[2]) == 0xffffff00)
1311 return \"movqb %$0,%0\";
1314 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
1315 return \"andb %2,%0\";
1318 if ((INTVAL (operands[2]) | 0xffff) == 0xffffffff)
1320 if (INTVAL (operands[2]) == 0xffff0000)
1321 return \"movqw %$0,%0\";
1324 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
1325 return \"andw %2,%0\";
1329 return \"andd %2,%0\";
1332 (define_insn "andhi3"
1333 [(set (match_operand:HI 0 "general_operand" "=g")
1334 (and:HI (match_operand:HI 1 "general_operand" "%0")
1335 (match_operand:HI 2 "general_operand" "g")))]
1339 if (GET_CODE (operands[2]) == CONST_INT
1340 && (INTVAL (operands[2]) | 0xff) == 0xffffffff)
1342 if (INTVAL (operands[2]) == 0xffffff00)
1343 return \"movqb %$0,%0\";
1346 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff);
1347 return \"andb %2,%0\";
1350 return \"andw %2,%0\";
1353 (define_insn "andqi3"
1354 [(set (match_operand:QI 0 "general_operand" "=g")
1355 (and:QI (match_operand:QI 1 "general_operand" "%0")
1356 (match_operand:QI 2 "general_operand" "g")))]
1361 [(set (match_operand:SI 0 "general_operand" "=g")
1362 (and:SI (not:SI (match_operand:SI 1 "general_operand" "rmn"))
1363 (match_operand:SI 2 "general_operand" "0")))]
1368 [(set (match_operand:HI 0 "general_operand" "=g")
1369 (and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
1370 (match_operand:HI 2 "general_operand" "0")))]
1375 [(set (match_operand:QI 0 "general_operand" "=g")
1376 (and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
1377 (match_operand:QI 2 "general_operand" "0")))]
1381 ;;- Bit set instructions.
1383 (define_insn "iorsi3"
1384 [(set (match_operand:SI 0 "general_operand" "=g")
1385 (ior:SI (match_operand:SI 1 "general_operand" "%0")
1386 (match_operand:SI 2 "general_operand" "rmn")))]
1390 if (GET_CODE (operands[2]) == CONST_INT) {
1391 if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1392 return \"orb %2,%0\";
1393 if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1394 return \"orw %2,%0\";
1396 return \"ord %2,%0\";
1399 (define_insn "iorhi3"
1400 [(set (match_operand:HI 0 "general_operand" "=g")
1401 (ior:HI (match_operand:HI 1 "general_operand" "%0")
1402 (match_operand:HI 2 "general_operand" "g")))]
1406 if (GET_CODE(operands[2]) == CONST_INT &&
1407 (INTVAL(operands[2]) & 0xffffff00) == 0)
1408 return \"orb %2,%0\";
1409 return \"orw %2,%0\";
1412 (define_insn "iorqi3"
1413 [(set (match_operand:QI 0 "general_operand" "=g")
1414 (ior:QI (match_operand:QI 1 "general_operand" "%0")
1415 (match_operand:QI 2 "general_operand" "g")))]
1419 ;;- xor instructions.
1421 (define_insn "xorsi3"
1422 [(set (match_operand:SI 0 "general_operand" "=g")
1423 (xor:SI (match_operand:SI 1 "general_operand" "%0")
1424 (match_operand:SI 2 "general_operand" "rmn")))]
1428 if (GET_CODE (operands[2]) == CONST_INT) {
1429 if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1430 return \"xorb %2,%0\";
1431 if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1432 return \"xorw %2,%0\";
1434 return \"xord %2,%0\";
1437 (define_insn "xorhi3"
1438 [(set (match_operand:HI 0 "general_operand" "=g")
1439 (xor:HI (match_operand:HI 1 "general_operand" "%0")
1440 (match_operand:HI 2 "general_operand" "g")))]
1444 if (GET_CODE(operands[2]) == CONST_INT &&
1445 (INTVAL(operands[2]) & 0xffffff00) == 0)
1446 return \"xorb %2,%0\";
1447 return \"xorw %2,%0\";
1450 (define_insn "xorqi3"
1451 [(set (match_operand:QI 0 "general_operand" "=g")
1452 (xor:QI (match_operand:QI 1 "general_operand" "%0")
1453 (match_operand:QI 2 "general_operand" "g")))]
1457 (define_insn "negdf2"
1458 [(set (match_operand:DF 0 "general_operand" "=fm<")
1459 (neg:DF (match_operand:DF 1 "general_operand" "fmF")))]
1463 (define_insn "negsf2"
1464 [(set (match_operand:SF 0 "general_operand" "=fm<")
1465 (neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
1469 (define_insn "negdi2"
1470 [(set (match_operand:DI 0 "general_operand" "=ro")
1471 (neg:DI (match_operand:DI 1 "general_operand" "ro")))]
1475 rtx low[2], high[2], xops[4];
1476 split_di (operands, 2, low, high);
1482 if (rtx_equal_p (operands[0], operands[1]))
1484 output_asm_insn (\"negd %3,%1\", xops);
1485 output_asm_insn (\"negd %2,%0\", xops);
1486 output_asm_insn (\"subcd %$0,%1\", xops);
1490 output_asm_insn (\"negd %2,%0\", xops);
1491 output_asm_insn (\"movqd %$0,%1\", xops);
1492 output_asm_insn (\"subcd %3,%1\", xops);
1497 (define_insn "negsi2"
1498 [(set (match_operand:SI 0 "general_operand" "=g<")
1499 (neg:SI (match_operand:SI 1 "general_operand" "rmn")))]
1503 (define_insn "neghi2"
1504 [(set (match_operand:HI 0 "general_operand" "=g<")
1505 (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1509 (define_insn "negqi2"
1510 [(set (match_operand:QI 0 "general_operand" "=g<")
1511 (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1515 (define_insn "one_cmplsi2"
1516 [(set (match_operand:SI 0 "general_operand" "=g<")
1517 (not:SI (match_operand:SI 1 "general_operand" "rmn")))]
1521 (define_insn "one_cmplhi2"
1522 [(set (match_operand:HI 0 "general_operand" "=g<")
1523 (not:HI (match_operand:HI 1 "general_operand" "g")))]
1527 (define_insn "one_cmplqi2"
1528 [(set (match_operand:QI 0 "general_operand" "=g<")
1529 (not:QI (match_operand:QI 1 "general_operand" "g")))]
1533 ;; arithmetic left and right shift operations
1534 ;; on the 32532 we will always use lshd for arithmetic left shifts,
1535 ;; because it is three times faster. Broken programs which
1536 ;; use negative shift counts are probably broken differently
1539 ;; alternative 0 never matches on the 32532
1540 (define_insn "ashlsi3"
1541 [(set (match_operand:SI 0 "general_operand" "=g,g")
1542 (ashift:SI (match_operand:SI 1 "general_operand" "r,0")
1543 (match_operand:SI 2 "general_operand" "I,rmn")))]
1547 return \"lshd %2,%0\";
1549 return output_shift_insn (operands);
1552 (define_insn "ashlhi3"
1553 [(set (match_operand:HI 0 "general_operand" "=g")
1554 (ashift:HI (match_operand:HI 1 "general_operand" "0")
1555 (match_operand:SI 2 "general_operand" "rmn")))]
1558 { if (GET_CODE (operands[2]) == CONST_INT)
1560 if (INTVAL (operands[2]) == 1)
1561 return \"addw %0,%0\";
1562 else if (! TARGET_32532 && INTVAL (operands[2]) == 2)
1563 return \"addw %0,%0\;addw %0,%0\";
1566 return \"lshw %2,%0\";
1568 return \"ashw %2,%0\";
1571 (define_insn "ashlqi3"
1572 [(set (match_operand:QI 0 "general_operand" "=g")
1573 (ashift:QI (match_operand:QI 1 "general_operand" "0")
1574 (match_operand:SI 2 "general_operand" "rmn")))]
1577 { if (GET_CODE (operands[2]) == CONST_INT)
1579 if (INTVAL (operands[2]) == 1)
1580 return \"addb %0,%0\";
1581 else if (! TARGET_32532 && INTVAL (operands[2]) == 2)
1582 return \"addb %0,%0\;addb %0,%0\";
1585 return \"lshb %2,%0\";
1587 return \"ashb %2,%0\";
1590 ;; Arithmetic right shift on the 32k works by negating the shift count.
1591 (define_expand "ashrsi3"
1592 [(set (match_operand:SI 0 "general_operand" "=g")
1593 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1594 (match_operand:SI 2 "general_operand" "g")))]
1598 if (GET_CODE (operands[2]) != CONST_INT)
1599 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1603 [(set (match_operand:SI 0 "general_operand" "=g")
1604 (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
1605 (match_operand:SI 2 "immediate_operand" "i")))]
1610 [(set (match_operand:SI 0 "general_operand" "=g")
1611 (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
1612 (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1616 (define_expand "ashrhi3"
1617 [(set (match_operand:HI 0 "general_operand" "=g")
1618 (ashiftrt:HI (match_operand:HI 1 "general_operand" "g")
1619 (match_operand:SI 2 "general_operand" "g")))]
1623 if (GET_CODE (operands[2]) != CONST_INT)
1624 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1628 [(set (match_operand:HI 0 "general_operand" "=g")
1629 (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
1630 (match_operand:SI 2 "immediate_operand" "i")))]
1635 [(set (match_operand:HI 0 "general_operand" "=g")
1636 (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
1637 (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1641 (define_expand "ashrqi3"
1642 [(set (match_operand:QI 0 "general_operand" "=g")
1643 (ashiftrt:QI (match_operand:QI 1 "general_operand" "g")
1644 (match_operand:SI 2 "general_operand" "g")))]
1648 if (GET_CODE (operands[2]) != CONST_INT)
1649 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1653 [(set (match_operand:QI 0 "general_operand" "=g")
1654 (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
1655 (match_operand:SI 2 "immediate_operand" "i")))]
1660 [(set (match_operand:QI 0 "general_operand" "=g")
1661 (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
1662 (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1666 ;; logical shift instructions
1668 ;; Logical right shift on the 32k works by negating the shift count.
1669 (define_expand "lshrsi3"
1670 [(set (match_operand:SI 0 "general_operand" "=g")
1671 (lshiftrt:SI (match_operand:SI 1 "general_operand" "g")
1672 (match_operand:SI 2 "general_operand" "g")))]
1676 if (GET_CODE (operands[2]) != CONST_INT)
1677 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1681 [(set (match_operand:SI 0 "general_operand" "=g")
1682 (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
1683 (match_operand:SI 2 "immediate_operand" "i")))]
1688 [(set (match_operand:SI 0 "general_operand" "=g")
1689 (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
1690 (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1694 (define_expand "lshrhi3"
1695 [(set (match_operand:HI 0 "general_operand" "=g")
1696 (lshiftrt:HI (match_operand:HI 1 "general_operand" "g")
1697 (match_operand:SI 2 "general_operand" "g")))]
1701 if (GET_CODE (operands[2]) != CONST_INT)
1702 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1706 [(set (match_operand:HI 0 "general_operand" "=g")
1707 (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
1708 (match_operand:SI 2 "immediate_operand" "i")))]
1713 [(set (match_operand:HI 0 "general_operand" "=g")
1714 (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
1715 (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1719 (define_expand "lshrqi3"
1720 [(set (match_operand:QI 0 "general_operand" "=g")
1721 (lshiftrt:QI (match_operand:QI 1 "general_operand" "g")
1722 (match_operand:SI 2 "general_operand" "g")))]
1726 if (GET_CODE (operands[2]) != CONST_INT)
1727 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1731 [(set (match_operand:QI 0 "general_operand" "=g")
1732 (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
1733 (match_operand:SI 2 "immediate_operand" "i")))]
1738 [(set (match_operand:QI 0 "general_operand" "=g")
1739 (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
1740 (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1744 ;; Rotate instructions
1746 (define_insn "rotlsi3"
1747 [(set (match_operand:SI 0 "general_operand" "=g")
1748 (rotate:SI (match_operand:SI 1 "general_operand" "0")
1749 (match_operand:SI 2 "general_operand" "rmn")))]
1753 (define_insn "rotlhi3"
1754 [(set (match_operand:HI 0 "general_operand" "=g")
1755 (rotate:HI (match_operand:HI 1 "general_operand" "0")
1756 (match_operand:SI 2 "general_operand" "rmn")))]
1760 (define_insn "rotlqi3"
1761 [(set (match_operand:QI 0 "general_operand" "=g")
1762 (rotate:QI (match_operand:QI 1 "general_operand" "0")
1763 (match_operand:SI 2 "general_operand" "rmn")))]
1767 ;; Right rotate on the 32k works by negating the shift count.
1768 (define_expand "rotrsi3"
1769 [(set (match_operand:SI 0 "general_operand" "=g")
1770 (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1771 (match_operand:SI 2 "general_operand" "g")))]
1775 if (GET_CODE (operands[2]) != CONST_INT)
1776 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1780 [(set (match_operand:SI 0 "general_operand" "=g")
1781 (rotatert:SI (match_operand:SI 1 "general_operand" "0")
1782 (match_operand:SI 2 "immediate_operand" "i")))]
1787 [(set (match_operand:SI 0 "general_operand" "=g")
1788 (rotatert:SI (match_operand:SI 1 "general_operand" "0")
1789 (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1793 (define_expand "rotrhi3"
1794 [(set (match_operand:HI 0 "general_operand" "=g")
1795 (rotatert:HI (match_operand:HI 1 "general_operand" "g")
1796 (match_operand:SI 2 "general_operand" "g")))]
1800 if (GET_CODE (operands[2]) != CONST_INT)
1801 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1805 [(set (match_operand:HI 0 "general_operand" "=g")
1806 (rotatert:HI (match_operand:HI 1 "general_operand" "0")
1807 (match_operand:SI 2 "immediate_operand" "i")))]
1812 [(set (match_operand:HI 0 "general_operand" "=g")
1813 (rotatert:HI (match_operand:HI 1 "general_operand" "0")
1814 (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1818 (define_expand "rotrqi3"
1819 [(set (match_operand:QI 0 "general_operand" "=g")
1820 (rotatert:QI (match_operand:QI 1 "general_operand" "g")
1821 (match_operand:SI 2 "general_operand" "g")))]
1825 if (GET_CODE (operands[2]) != CONST_INT)
1826 operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
1830 [(set (match_operand:QI 0 "general_operand" "=g")
1831 (rotatert:QI (match_operand:QI 1 "general_operand" "0")
1832 (match_operand:SI 2 "immediate_operand" "i")))]
1837 [(set (match_operand:QI 0 "general_operand" "=g")
1838 (rotatert:QI (match_operand:QI 1 "general_operand" "0")
1839 (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1843 ;;- load or push effective address
1844 ;; These come after the move, add, and multiply patterns
1845 ;; because we don't want pushl $1 turned into pushad 1.
1848 [(set (match_operand:SI 0 "general_operand" "=g<")
1849 (match_operand:QI 1 "address_operand" "p"))]
1853 if (REG_P (operands[0])
1854 && GET_CODE (operands[1]) == MULT
1855 && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
1856 && (INTVAL (XEXP (operands[1], 1)) == 2
1857 || INTVAL (XEXP (operands[1], 1)) == 4))
1860 xoperands[0] = operands[0];
1861 xoperands[1] = XEXP (operands[1], 0);
1862 xoperands[2] = GEN_INT (INTVAL (XEXP (operands[1], 1)) >> 1);
1863 return output_shift_insn (xoperands);
1865 return \"addr %a1,%0\";
1868 ;;; Index insns. These are about the same speed as multiply-add counterparts.
1869 ;;; but slower then using power-of-2 shifts if we can use them
1872 ; [(set (match_operand:SI 0 "register_operand" "=r")
1873 ; (plus:SI (match_operand:SI 1 "general_operand" "rmn")
1874 ; (mult:SI (match_operand:SI 2 "register_operand" "0")
1875 ; (plus:SI (match_operand:SI 3 "general_operand" "rmn") (const_int 1)))))]
1876 ; "GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 8"
1877 ; "indexd %0,%3,%1")
1880 ; [(set (match_operand:SI 0 "register_operand" "=r")
1881 ; (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
1882 ; (plus:SI (match_operand:SI 2 "general_operand" "rmn") (const_int 1)))
1883 ; (match_operand:SI 3 "general_operand" "rmn")))]
1884 ; "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 8"
1885 ; "indexd %0,%2,%3")
1887 ;; Set, Clear, and Invert bit
1890 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g")
1892 (match_operand:SI 1 "general_operand" "rmn"))
1898 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g")
1900 (match_operand:SI 1 "general_operand" "rmn"))
1906 [(set (match_operand:SI 0 "general_operand" "+g")
1907 (xor:SI (ashift:SI (const_int 1)
1908 (match_operand:SI 1 "general_operand" "rmn"))
1914 [(set (match_operand:QI 0 "general_operand" "=g")
1916 (ashift:SI (const_int 1)
1917 (match_operand:QI 1 "general_operand" "rmn")) 0)
1922 ;; Recognize jbs and jbc instructions.
1926 (zero_extract (match_operand:SI 0 "general_operand" "rm")
1928 (match_operand:SI 1 "general_operand" "g")))]
1931 { cc_status.flags = CC_Z_IN_F;
1932 return \"tbitd %1,%0\";
1935 ;; extract(base, width, offset)
1936 ;; Signed bitfield extraction is not supported in hardware on the
1937 ;; NS 32032. It is therefore better to let GCC figure out a
1938 ;; good strategy for generating the proper instruction sequence
1939 ;; and represent it as rtl.
1941 ;; Optimize the case of extracting a byte or word from a register.
1942 ;; Otherwise we must load a register with the offset of the
1943 ;; chunk we want, and perform an extract insn (each of which
1944 ;; is very expensive). Since we use the stack to do our bit-twiddling
1945 ;; we cannot use it for a destination. Perhaps things are fast
1946 ;; enough on the 32532 that such hacks are not needed.
1949 [(set (match_operand:SI 0 "general_operand" "=ro")
1950 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
1951 (match_operand:SI 2 "const_int_operand" "i")
1952 (match_operand:SI 3 "const_int_operand" "i")))]
1953 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1954 && (INTVAL (operands[3]) == 8 || INTVAL (operands[3]) == 16 || INTVAL (operands[3]) == 24)"
1957 output_asm_insn (\"movd %1,tos\", operands);
1958 if (INTVAL (operands[2]) == 16)
1960 if (INTVAL (operands[3]) == 8)
1961 output_asm_insn (\"movzwd 1(sp),%0\", operands);
1963 output_asm_insn (\"movzwd 2(sp),%0\", operands);
1967 if (INTVAL (operands[3]) == 8)
1968 output_asm_insn (\"movzbd 1(sp),%0\", operands);
1969 else if (INTVAL (operands[3]) == 16)
1970 output_asm_insn (\"movzbd 2(sp),%0\", operands);
1972 output_asm_insn (\"movzbd 3(sp),%0\", operands);
1974 if (TARGET_32532 || TARGET_32332)
1975 return \"cmpqd %$0,tos\";
1977 return \"adjspb %$-4\";
1980 ;; The exts/ext instructions have the problem that they always access
1981 ;; 32 bits even if the bitfield is smaller. For example the instruction
1982 ;; extsd 7(r1),r0,2,5
1983 ;; would read not only at address 7(r1) but also at 8(r1) to 10(r1).
1984 ;; If these addresses are in a different (unmapped) page a memory fault
1987 ;; Timing considerations:
1988 ;; movd 0(r1),r0 3 bytes
1991 ;; takes about 13 cycles on the 532 while
1992 ;; extsd 7(r1),r0,2,5 5 bytes
1993 ;; takes about 21 cycles.
1995 ;; The inss/ins instructions suffer from the same problem.
1997 ;; A machine specific option (-mbitfield/-mnobitfield) is used
1998 ;; to allow/disallow the use of these instructions.
2001 [(set (match_operand:SI 0 "general_operand" "=g<")
2002 (zero_extract:SI (match_operand:SI 1 "register_operand" "g")
2003 (match_operand:SI 2 "const_int_operand" "i")
2004 (match_operand:SI 3 "general_operand" "rK")))]
2007 { if (GET_CODE (operands[3]) == CONST_INT)
2008 return \"extsd %1,%0,%3,%2\";
2009 else return \"extd %3,%1,%0,%2\";
2012 (define_insn "extzv"
2013 [(set (match_operand:SI 0 "general_operand" "=g<")
2014 (zero_extract:SI (match_operand:QI 1 "general_operand" "g")
2015 (match_operand:SI 2 "const_int_operand" "i")
2016 (match_operand:SI 3 "general_operand" "rK")))]
2019 { if (GET_CODE (operands[3]) == CONST_INT)
2020 return \"extsd %1,%0,%3,%2\";
2021 else return \"extd %3,%1,%0,%2\";
2025 [(set (zero_extract:SI (match_operand:SI 0 "memory_operand" "+o")
2026 (match_operand:SI 1 "const_int_operand" "i")
2027 (match_operand:SI 2 "general_operand" "rn"))
2028 (match_operand:SI 3 "general_operand" "rm"))]
2031 { if (GET_CODE (operands[2]) == CONST_INT)
2033 if (INTVAL (operands[2]) >= 8)
2035 operands[0] = adj_offsettable_operand (operands[0],
2036 INTVAL (operands[2]) / 8);
2037 operands[2] = GEN_INT (INTVAL (operands[2]) % 8);
2039 if (INTVAL (operands[1]) <= 8)
2040 return \"inssb %3,%0,%2,%1\";
2041 else if (INTVAL (operands[1]) <= 16)
2042 return \"inssw %3,%0,%2,%1\";
2044 return \"inssd %3,%0,%2,%1\";
2046 return \"insd %2,%3,%0,%1\";
2050 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
2051 (match_operand:SI 1 "const_int_operand" "i")
2052 (match_operand:SI 2 "general_operand" "rK"))
2053 (match_operand:SI 3 "general_operand" "rm"))]
2056 { if (GET_CODE (operands[2]) == CONST_INT)
2057 if (INTVAL (operands[1]) <= 8)
2058 return \"inssb %3,%0,%2,%1\";
2059 else if (INTVAL (operands[1]) <= 16)
2060 return \"inssw %3,%0,%2,%1\";
2062 return \"inssd %3,%0,%2,%1\";
2063 return \"insd %2,%3,%0,%1\";
2067 [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+g")
2068 (match_operand:SI 1 "const_int_operand" "i")
2069 (match_operand:SI 2 "general_operand" "rK"))
2070 (match_operand:SI 3 "general_operand" "rm"))]
2073 { if (GET_CODE (operands[2]) == CONST_INT)
2074 if (INTVAL (operands[1]) <= 8)
2075 return \"inssb %3,%0,%2,%1\";
2076 else if (INTVAL (operands[1]) <= 16)
2077 return \"inssw %3,%0,%2,%1\";
2079 return \"inssd %3,%0,%2,%1\";
2080 return \"insd %2,%3,%0,%1\";
2086 (label_ref (match_operand 0 "" "")))]
2092 (if_then_else (eq (cc0)
2094 (label_ref (match_operand 0 "" ""))
2098 { if (cc_prev_status.flags & CC_Z_IN_F)
2100 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2102 else return \"beq %l0\";
2107 (if_then_else (ne (cc0)
2109 (label_ref (match_operand 0 "" ""))
2113 { if (cc_prev_status.flags & CC_Z_IN_F)
2115 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2117 else return \"bne %l0\";
2122 (if_then_else (gt (cc0)
2124 (label_ref (match_operand 0 "" ""))
2131 (if_then_else (gtu (cc0)
2133 (label_ref (match_operand 0 "" ""))
2140 (if_then_else (lt (cc0)
2142 (label_ref (match_operand 0 "" ""))
2149 (if_then_else (ltu (cc0)
2151 (label_ref (match_operand 0 "" ""))
2158 (if_then_else (ge (cc0)
2160 (label_ref (match_operand 0 "" ""))
2167 (if_then_else (geu (cc0)
2169 (label_ref (match_operand 0 "" ""))
2176 (if_then_else (le (cc0)
2178 (label_ref (match_operand 0 "" ""))
2185 (if_then_else (leu (cc0)
2187 (label_ref (match_operand 0 "" ""))
2194 (if_then_else (eq (cc0)
2197 (label_ref (match_operand 0 "" ""))))]
2200 { if (cc_prev_status.flags & CC_Z_IN_F)
2202 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2204 else return \"bne %l0\";
2209 (if_then_else (ne (cc0)
2212 (label_ref (match_operand 0 "" ""))))]
2215 { if (cc_prev_status.flags & CC_Z_IN_F)
2217 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2219 else return \"beq %l0\";
2224 (if_then_else (gt (cc0)
2227 (label_ref (match_operand 0 "" ""))))]
2233 (if_then_else (gtu (cc0)
2236 (label_ref (match_operand 0 "" ""))))]
2242 (if_then_else (lt (cc0)
2245 (label_ref (match_operand 0 "" ""))))]
2251 (if_then_else (ltu (cc0)
2254 (label_ref (match_operand 0 "" ""))))]
2260 (if_then_else (ge (cc0)
2263 (label_ref (match_operand 0 "" ""))))]
2269 (if_then_else (geu (cc0)
2272 (label_ref (match_operand 0 "" ""))))]
2278 (if_then_else (le (cc0)
2281 (label_ref (match_operand 0 "" ""))))]
2287 (if_then_else (leu (cc0)
2290 (label_ref (match_operand 0 "" ""))))]
2294 ;; Subtract-and-jump and Add-and-jump insns.
2295 ;; These can actually be used for adding numbers in the range -8 to 7
2300 (ne (match_operand:SI 0 "general_operand" "+g")
2301 (match_operand:SI 1 "const_int_operand" "i"))
2302 (label_ref (match_operand 2 "" ""))
2305 (minus:SI (match_dup 0)
2307 "INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2308 "acbd %$%n1,%0,%l2")
2313 (ne (match_operand:SI 0 "general_operand" "+g")
2314 (match_operand:SI 1 "const_int_operand" "i"))
2315 (label_ref (match_operand 2 "" ""))
2318 (plus:SI (match_dup 0)
2319 (match_operand:SI 3 "const_int_operand" "i")))]
2320 "INTVAL (operands[1]) == - INTVAL (operands[3])
2321 && INTVAL (operands[3]) >= -8 && INTVAL (operands[3]) < 8"
2325 [(call (match_operand:QI 0 "memory_operand" "m")
2326 (match_operand:QI 1 "general_operand" "g"))]
2331 if (GET_CODE (operands[0]) == MEM)
2333 rtx temp = XEXP (operands[0], 0);
2334 if (CONSTANT_ADDRESS_P (temp))
2337 return \"bsr %?%0\";
2339 #ifdef CALL_MEMREF_IMPLICIT
2346 return \"bsr %?%a0\";
2351 if (GET_CODE (XEXP (operands[0], 0)) == REG)
2352 #if defined (GNX_V3) || defined (CALL_MEMREF_IMPLICIT)
2358 #endif /* not JSR_ALWAYS */
2362 (define_insn "call_value"
2363 [(set (match_operand 0 "" "=rf")
2364 (call (match_operand:QI 1 "memory_operand" "m")
2365 (match_operand:QI 2 "general_operand" "g")))]
2370 if (GET_CODE (operands[1]) == MEM)
2372 rtx temp = XEXP (operands[1], 0);
2373 if (CONSTANT_ADDRESS_P (temp))
2376 return \"bsr %?%1\";
2378 #ifdef CALL_MEMREF_IMPLICIT
2385 return \"bsr %?%a1\";
2390 if (GET_CODE (XEXP (operands[1], 0)) == REG)
2391 #if defined (GNX_V3) || defined (CALL_MEMREF_IMPLICIT)
2397 #endif /* not JSR_ALWAYS */
2401 ;; Call subroutine returning any type.
2403 (define_expand "untyped_call"
2404 [(parallel [(call (match_operand 0 "" "")
2406 (match_operand 1 "" "")
2407 (match_operand 2 "" "")])]
2413 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
2415 for (i = 0; i < XVECLEN (operands[2], 0); i++)
2417 rtx set = XVECEXP (operands[2], 0, i);
2418 emit_move_insn (SET_DEST (set), SET_SRC (set));
2421 /* The optimizer does not know that the call sets the function value
2422 registers we stored in the result block. We avoid problems by
2423 claiming that all hard registers are used and clobbered at this
2425 emit_insn (gen_blockage ());
2430 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
2431 ;; all of memory. This blocks insns from being moved across this point.
2433 (define_insn "blockage"
2434 [(unspec_volatile [(const_int 0)] 0)]
2438 (define_insn "return"
2443 (define_insn "abssf2"
2444 [(set (match_operand:SF 0 "general_operand" "=fm<")
2445 (abs:SF (match_operand:SF 1 "general_operand" "fmF")))]
2449 (define_insn "absdf2"
2450 [(set (match_operand:DF 0 "general_operand" "=fm<")
2451 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
2455 (define_insn "abssi2"
2456 [(set (match_operand:SI 0 "general_operand" "=g<")
2457 (abs:SI (match_operand:SI 1 "general_operand" "rmn")))]
2461 (define_insn "abshi2"
2462 [(set (match_operand:HI 0 "general_operand" "=g<")
2463 (abs:HI (match_operand:HI 1 "general_operand" "g")))]
2467 (define_insn "absqi2"
2468 [(set (match_operand:QI 0 "general_operand" "=g<")
2469 (abs:QI (match_operand:QI 1 "general_operand" "g")))]
2478 (define_insn "indirect_jump"
2479 [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
2483 (define_insn "tablejump"
2485 (plus:SI (pc) (match_operand:SI 0 "general_operand" "g")))
2486 (use (label_ref (match_operand 1 "" "")))]
2490 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
2491 CODE_LABEL_NUMBER (operands[1]));
2492 return \"cased %0\";
2495 ;; Scondi instructions
2497 [(set (match_operand:SI 0 "general_operand" "=g<")
2498 (eq:SI (cc0) (const_int 0)))]
2501 { if (cc_prev_status.flags & CC_Z_IN_F)
2503 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2505 else return \"seqd %0\";
2509 [(set (match_operand:HI 0 "general_operand" "=g<")
2510 (eq:HI (cc0) (const_int 0)))]
2513 { if (cc_prev_status.flags & CC_Z_IN_F)
2515 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2517 else return \"seqw %0\";
2521 [(set (match_operand:QI 0 "general_operand" "=g<")
2522 (eq:QI (cc0) (const_int 0)))]
2525 { if (cc_prev_status.flags & CC_Z_IN_F)
2527 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2529 else return \"seqb %0\";
2533 [(set (match_operand:SI 0 "general_operand" "=g<")
2534 (ne:SI (cc0) (const_int 0)))]
2537 { if (cc_prev_status.flags & CC_Z_IN_F)
2539 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2541 else return \"sned %0\";
2545 [(set (match_operand:HI 0 "general_operand" "=g<")
2546 (ne:HI (cc0) (const_int 0)))]
2549 { if (cc_prev_status.flags & CC_Z_IN_F)
2551 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2553 else return \"snew %0\";
2557 [(set (match_operand:QI 0 "general_operand" "=g<")
2558 (ne:QI (cc0) (const_int 0)))]
2561 { if (cc_prev_status.flags & CC_Z_IN_F)
2563 else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2565 else return \"sneb %0\";
2569 [(set (match_operand:SI 0 "general_operand" "=g<")
2570 (gt:SI (cc0) (const_int 0)))]
2575 [(set (match_operand:HI 0 "general_operand" "=g<")
2576 (gt:HI (cc0) (const_int 0)))]
2581 [(set (match_operand:QI 0 "general_operand" "=g<")
2582 (gt:QI (cc0) (const_int 0)))]
2587 [(set (match_operand:SI 0 "general_operand" "=g<")
2588 (gtu:SI (cc0) (const_int 0)))]
2593 [(set (match_operand:HI 0 "general_operand" "=g<")
2594 (gtu:HI (cc0) (const_int 0)))]
2599 [(set (match_operand:QI 0 "general_operand" "=g<")
2600 (gtu:QI (cc0) (const_int 0)))]
2605 [(set (match_operand:SI 0 "general_operand" "=g<")
2606 (lt:SI (cc0) (const_int 0)))]
2611 [(set (match_operand:HI 0 "general_operand" "=g<")
2612 (lt:HI (cc0) (const_int 0)))]
2617 [(set (match_operand:QI 0 "general_operand" "=g<")
2618 (lt:QI (cc0) (const_int 0)))]
2623 [(set (match_operand:SI 0 "general_operand" "=g<")
2624 (ltu:SI (cc0) (const_int 0)))]
2629 [(set (match_operand:HI 0 "general_operand" "=g<")
2630 (ltu:HI (cc0) (const_int 0)))]
2635 [(set (match_operand:QI 0 "general_operand" "=g<")
2636 (ltu:QI (cc0) (const_int 0)))]
2641 [(set (match_operand:SI 0 "general_operand" "=g<")
2642 (ge:SI (cc0) (const_int 0)))]
2647 [(set (match_operand:HI 0 "general_operand" "=g<")
2648 (ge:HI (cc0) (const_int 0)))]
2653 [(set (match_operand:QI 0 "general_operand" "=g<")
2654 (ge:QI (cc0) (const_int 0)))]
2659 [(set (match_operand:SI 0 "general_operand" "=g<")
2660 (geu:SI (cc0) (const_int 0)))]
2665 [(set (match_operand:HI 0 "general_operand" "=g<")
2666 (geu:HI (cc0) (const_int 0)))]
2671 [(set (match_operand:QI 0 "general_operand" "=g<")
2672 (geu:QI (cc0) (const_int 0)))]
2677 [(set (match_operand:SI 0 "general_operand" "=g<")
2678 (le:SI (cc0) (const_int 0)))]
2683 [(set (match_operand:HI 0 "general_operand" "=g<")
2684 (le:HI (cc0) (const_int 0)))]
2689 [(set (match_operand:QI 0 "general_operand" "=g<")
2690 (le:QI (cc0) (const_int 0)))]
2695 [(set (match_operand:SI 0 "general_operand" "=g<")
2696 (leu:SI (cc0) (const_int 0)))]
2701 [(set (match_operand:HI 0 "general_operand" "=g<")
2702 (leu:HI (cc0) (const_int 0)))]
2707 [(set (match_operand:QI 0 "general_operand" "=g<")
2708 (leu:QI (cc0) (const_int 0)))]
2715 [(set (match_operand:SI 0 "general_operand" "ro")
2717 (plus:SI (ffs:SI (zero_extract:SI
2718 (match_operand:SI 1 "general_operand" "g")
2719 (minus:SI (const_int 32) (match_dup 0))
2724 "ffsd %1,%0; bfc 1f; addqd %$-1,%0; 1:")
2726 (define_expand "ffssi2"
2727 [(set (match_operand:SI 0 "general_operand" "=g") (const_int 0))
2730 (plus:SI (ffs:SI (zero_extract:SI
2731 (match_operand:SI 1 "general_operand" "g")
2732 (minus:SI (const_int 32) (match_dup 0))
2737 (plus:SI (match_dup 0)
2740 "operands[1] = make_safe_from(operands[1], operands[0]);")
2742 ;; Speed up stack adjust followed by a HI fixedpoint push.
2745 [(set (reg:SI 17) (plus:SI (reg:SI 17) (const_int -2)))
2746 (set (match_operand:HI 0 "push_operand" "=m")
2747 (match_operand:HI 1 "general_operand" "g"))]
2748 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
2751 if (GET_CODE (operands[1]) == CONST_INT)
2752 output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%$%1,tos\"),
2755 output_asm_insn (\"movzwd %1,tos\", operands);
2759 ;; Speed up stack adjust followed by a zero_extend:HI(QI) fixedpoint push.
2762 [(set (reg:SI 17) (plus:SI (reg:SI 17) (const_int -2)))
2763 (set (match_operand:HI 0 "push_operand" "=m")
2764 (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))]
2765 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
2768 if (GET_CODE (operands[1]) == CONST_INT)
2769 output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%$%1,tos\"),
2772 output_asm_insn (\"movzbd %1,tos\", operands);
2776 ;; Speed up stack adjust followed by a sign_extend:HI(QI) fixedpoint push.
2779 [(set (reg:SI 17) (plus:SI (reg:SI 17) (const_int -2)))
2780 (set (match_operand:HI 0 "push_operand" "=m")
2781 (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))]
2782 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
2785 if (GET_CODE (operands[1]) == CONST_INT)
2786 output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%$%1,tos\"),
2789 output_asm_insn (\"movxbd %1,tos\", operands);
2793 ;; Speed up stack adjust followed by a QI fixedpoint push.
2796 [(set (reg:SI 17) (plus:SI (reg:SI 17) (const_int -3)))
2797 (set (match_operand:QI 0 "push_operand" "=m")
2798 (match_operand:QI 1 "general_operand" "g"))]
2799 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
2802 if (GET_CODE (operands[1]) == CONST_INT)
2803 output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%$%1,tos\"),
2806 output_asm_insn (\"movzbd %1,tos\", operands);
2810 ;; Speed up stack adjust followed by a SI fixedpoint push.
2813 [(set (reg:SI 17) (plus:SI (reg:SI 17) (const_int 4)))
2814 (set (match_operand:SI 0 "push_operand" "=m")
2815 (match_operand:SI 1 "general_operand" "g"))]
2816 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
2819 if (GET_CODE (operands[1]) == CONST_INT)
2820 output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%$%1,0(sp)\"),
2822 else if (GET_CODE (operands[1]) != REG
2823 && GET_CODE (operands[1]) != MEM
2824 && address_operand (operands[1], SImode))
2825 output_asm_insn (\"addr %a1,0(sp)\", operands);
2827 output_asm_insn (\"movd %1,0(sp)\", operands);
2831 ;; Speed up stack adjust followed by two fullword fixedpoint pushes.
2834 [(set (reg:SI 17) (plus:SI (reg:SI 17) (const_int 8)))
2835 (set (match_operand:SI 0 "push_operand" "=m")
2836 (match_operand:SI 1 "general_operand" "g"))
2837 (set (match_operand:SI 2 "push_operand" "=m")
2838 (match_operand:SI 3 "general_operand" "g"))]
2839 "! reg_mentioned_p (stack_pointer_rtx, operands[1])
2840 && ! reg_mentioned_p (stack_pointer_rtx, operands[3])"
2843 if (GET_CODE (operands[1]) == CONST_INT)
2844 output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%$%1,4(sp)\"),
2846 else if (GET_CODE (operands[1]) != REG
2847 && GET_CODE (operands[1]) != MEM
2848 && address_operand (operands[1], SImode))
2849 output_asm_insn (\"addr %a1,4(sp)\", operands);
2851 output_asm_insn (\"movd %1,4(sp)\", operands);
2853 if (GET_CODE (operands[3]) == CONST_INT)
2854 output_asm_insn (output_move_dconst (INTVAL (operands[3]), \"%$%3,0(sp)\"),
2856 else if (GET_CODE (operands[3]) != REG
2857 && GET_CODE (operands[3]) != MEM
2858 && address_operand (operands[3], SImode))
2859 output_asm_insn (\"addr %a3,0(sp)\", operands);
2861 output_asm_insn (\"movd %3,0(sp)\", operands);