1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 90, 91, 93-97, 1998 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
26 calling convention in 64 bit mode. It doesn't work though, and should
27 be replaced with something better designed. */
33 #include "hard-reg-set.h"
35 #include "insn-config.h"
36 #include "conditions.h"
37 #include "insn-flags.h"
38 #include "insn-attr.h"
39 #include "insn-codes.h"
43 #undef MAX /* sys/param.h may also define these */
51 #if defined(USG) || defined(NO_STAB_H)
52 #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
54 #include <stab.h> /* On BSD, use the system's stab.h. */
58 #define STAB_CODE_TYPE enum __stab_debug_code
60 #define STAB_CODE_TYPE int
63 extern char *mktemp ();
65 extern rtx
adj_offsettable_operand ();
66 extern rtx
copy_to_reg ();
69 extern tree
lookup_name ();
70 extern void pfatal_with_name ();
71 extern void warning ();
73 extern FILE *asm_out_file
;
75 /* Enumeration for all of the relational tests, so that we can build
76 arrays indexed by the test type, and not worry about the order
93 /* Global variables for machine-dependent things. */
95 /* Threshold for data being put into the small data/bss area, instead
96 of the normal data area (references to the small data/bss area take
97 1 instruction, and use the global pointer, references to the normal
98 data area takes 2 instructions). */
99 int mips_section_threshold
= -1;
101 /* Count the number of .file directives, so that .loc is up to date. */
102 int num_source_filenames
= 0;
104 /* Count the number of sdb related labels are generated (to find block
105 start and end boundaries). */
106 int sdb_label_count
= 0;
108 /* Next label # for each statement for Silicon Graphics IRIS systems. */
111 /* Non-zero if inside of a function, because the stupid MIPS asm can't
112 handle .files inside of functions. */
113 int inside_function
= 0;
115 /* Files to separate the text and the data output, so that all of the data
116 can be emitted before the text, which will mean that the assembler will
117 generate smaller code, based on the global pointer. */
118 FILE *asm_out_data_file
;
119 FILE *asm_out_text_file
;
121 /* Linked list of all externals that are to be emitted when optimizing
122 for the global pointer if they haven't been declared by the end of
123 the program with an appropriate .comm or initialization. */
127 struct extern_list
*next
; /* next external */
128 char *name
; /* name of the external */
129 int size
; /* size in bytes */
132 /* Name of the file containing the current function. */
133 char *current_function_file
= "";
135 /* Warning given that Mips ECOFF can't support changing files
136 within a function. */
137 int file_in_function_warning
= FALSE
;
139 /* Whether to suppress issuing .loc's because the user attempted
140 to change the filename within a function. */
141 int ignore_line_number
= FALSE
;
143 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
149 /* The next branch instruction is a branch likely, not branch normal. */
150 int mips_branch_likely
;
152 /* Count of delay slots and how many are filled. */
153 int dslots_load_total
;
154 int dslots_load_filled
;
155 int dslots_jump_total
;
156 int dslots_jump_filled
;
158 /* # of nops needed by previous insn */
159 int dslots_number_nops
;
161 /* Number of 1/2/3 word references to data items (ie, not jal's). */
164 /* registers to check for load delay */
165 rtx mips_load_reg
, mips_load_reg2
, mips_load_reg3
, mips_load_reg4
;
167 /* Cached operands, and operator to compare for use in set/branch on
171 /* what type of branch to use */
172 enum cmp_type branch_type
;
174 /* Number of previously seen half-pic pointers and references. */
175 static int prev_half_pic_ptrs
= 0;
176 static int prev_half_pic_refs
= 0;
178 /* which cpu are we scheduling for */
179 enum processor_type mips_cpu
;
181 /* which instruction set architecture to use. */
184 #ifdef MIPS_ABI_DEFAULT
185 /* Which ABI to use. This is defined to a constant in mips.h if the target
186 doesn't support multiple ABIs. */
190 /* Strings to hold which cpu and instruction set architecture to use. */
191 char *mips_cpu_string
; /* for -mcpu=<xxx> */
192 char *mips_isa_string
; /* for -mips{1,2,3,4} */
193 char *mips_abi_string
; /* for -mabi={o32,32,n32,n64,64,eabi} */
195 /* If TRUE, we split addresses into their high and low parts in the RTL. */
196 int mips_split_addresses
;
198 /* Generating calls to position independent functions? */
199 enum mips_abicalls_type mips_abicalls
;
201 /* High and low marks for floating point values which we will accept
202 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
203 initialized in override_options. */
204 REAL_VALUE_TYPE dfhigh
, dflow
, sfhigh
, sflow
;
206 /* Array giving truth value on whether or not a given hard register
207 can support a given mode. */
208 char mips_hard_regno_mode_ok
[(int)MAX_MACHINE_MODE
][FIRST_PSEUDO_REGISTER
];
210 /* Current frame information calculated by compute_frame_size. */
211 struct mips_frame_info current_frame_info
;
213 /* Zero structure to initialize current_frame_info. */
214 struct mips_frame_info zero_frame_info
;
216 /* Temporary filename used to buffer .text until end of program
218 static char *temp_filename
;
220 /* Pseudo-reg holding the address of the current function when
221 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
222 by mips_finalize_pic if it was created. */
223 rtx embedded_pic_fnaddr_rtx
;
225 /* List of all MIPS punctuation characters used by print_operand. */
226 char mips_print_operand_punct
[256];
228 /* Map GCC register number to debugger register number. */
229 int mips_dbx_regno
[FIRST_PSEUDO_REGISTER
];
231 /* Buffer to use to enclose a load/store operation with %{ %} to
232 turn on .set volatile. */
233 static char volatile_buffer
[60];
235 /* Hardware names for the registers. If -mrnames is used, this
236 will be overwritten with mips_sw_reg_names. */
238 char mips_reg_names
[][8] =
240 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
241 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
242 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
243 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
244 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
245 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
246 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
247 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
248 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
249 "$fcc5","$fcc6","$fcc7","$rap"
252 /* Mips software names for the registers, used to overwrite the
253 mips_reg_names array. */
255 char mips_sw_reg_names
[][8] =
257 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
258 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
259 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
260 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
261 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
262 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
263 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
264 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
265 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
266 "$fcc5","$fcc6","$fcc7","$rap"
269 /* Map hard register number to register class */
270 enum reg_class mips_regno_to_class
[] =
272 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
273 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
274 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
275 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
276 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
277 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
278 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
279 GR_REGS
, GR_REGS
, GR_REGS
, GR_REGS
,
280 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
281 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
282 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
283 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
284 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
285 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
286 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
287 FP_REGS
, FP_REGS
, FP_REGS
, FP_REGS
,
288 HI_REG
, LO_REG
, HILO_REG
, ST_REGS
,
289 ST_REGS
, ST_REGS
, ST_REGS
, ST_REGS
,
290 ST_REGS
, ST_REGS
, ST_REGS
, GR_REGS
293 /* Map register constraint character to register class. */
294 enum reg_class mips_char_to_class
[256] =
296 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
297 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
298 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
299 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
300 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
301 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
302 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
303 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
304 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
305 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
306 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
307 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
308 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
309 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
310 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
311 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
312 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
313 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
314 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
315 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
316 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
317 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
318 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
319 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
320 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
321 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
322 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
323 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
324 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
325 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
326 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
327 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
328 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
329 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
330 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
331 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
332 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
333 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
334 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
335 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
336 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
337 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
338 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
339 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
340 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
341 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
342 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
343 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
344 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
345 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
346 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
347 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
348 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
349 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
350 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
351 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
352 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
353 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
354 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
355 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
356 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
357 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
358 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
359 NO_REGS
, NO_REGS
, NO_REGS
, NO_REGS
,
363 /* Return truth value of whether OP can be used as an operands
364 where a register or 16 bit unsigned integer is needed. */
367 uns_arith_operand (op
, mode
)
369 enum machine_mode mode
;
371 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT_UNSIGNED (op
))
374 return register_operand (op
, mode
);
377 /* Return truth value of whether OP can be used as an operands
378 where a 16 bit integer is needed */
381 arith_operand (op
, mode
)
383 enum machine_mode mode
;
385 if (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
))
388 return register_operand (op
, mode
);
391 /* Return truth value of whether OP can be used as an operand in a two
392 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
395 arith32_operand (op
, mode
)
397 enum machine_mode mode
;
399 if (GET_CODE (op
) == CONST_INT
)
402 return register_operand (op
, mode
);
405 /* Return truth value of whether OP is a integer which fits in 16 bits */
410 enum machine_mode mode
;
412 return (GET_CODE (op
) == CONST_INT
&& SMALL_INT (op
));
415 /* Return truth value of whether OP is a 32 bit integer which is too big to
416 be loaded with one instruction. */
421 enum machine_mode mode
;
425 if (GET_CODE (op
) != CONST_INT
)
430 /* ior reg,$r0,value */
431 if ((value
& ~ ((HOST_WIDE_INT
) 0x0000ffff)) == 0)
434 /* subu reg,$r0,value */
435 if (((unsigned HOST_WIDE_INT
) (value
+ 32768)) <= 32767)
438 /* lui reg,value>>16 */
439 if ((value
& 0x0000ffff) == 0)
445 /* Return truth value of whether OP is a register or the constant 0. */
448 reg_or_0_operand (op
, mode
)
450 enum machine_mode mode
;
452 switch (GET_CODE (op
))
455 return INTVAL (op
) == 0;
458 return op
== CONST0_RTX (mode
);
462 return register_operand (op
, mode
);
471 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
474 mips_const_double_ok (op
, mode
)
476 enum machine_mode mode
;
480 if (GET_CODE (op
) != CONST_DOUBLE
)
483 if (mode
== VOIDmode
)
486 if (mode
!= SFmode
&& mode
!= DFmode
)
489 if (op
== CONST0_RTX (mode
))
492 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
493 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_EABI
)
496 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
498 if (REAL_VALUE_ISNAN (d
))
501 if (REAL_VALUE_NEGATIVE (d
))
502 d
= REAL_VALUE_NEGATE (d
);
506 if (REAL_VALUES_LESS (d
, dfhigh
)
507 && REAL_VALUES_LESS (dflow
, d
))
512 if (REAL_VALUES_LESS (d
, sfhigh
)
513 && REAL_VALUES_LESS (sflow
, d
))
520 /* Accept the floating point constant 1 in the appropriate mode. */
523 const_float_1_operand (op
, mode
)
525 enum machine_mode mode
;
528 static REAL_VALUE_TYPE onedf
;
529 static REAL_VALUE_TYPE onesf
;
530 static int one_initialized
;
532 if (GET_CODE (op
) != CONST_DOUBLE
533 || mode
!= GET_MODE (op
)
534 || (mode
!= DFmode
&& mode
!= SFmode
))
537 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
539 /* We only initialize these values if we need them, since we will
540 never get called unless mips_isa >= 4. */
541 if (! one_initialized
)
543 onedf
= REAL_VALUE_ATOF ("1.0", DFmode
);
544 onesf
= REAL_VALUE_ATOF ("1.0", SFmode
);
549 return REAL_VALUES_EQUAL (d
, onedf
);
551 return REAL_VALUES_EQUAL (d
, onesf
);
554 /* Return truth value if a memory operand fits in a single instruction
555 (ie, register + small offset). */
558 simple_memory_operand (op
, mode
)
560 enum machine_mode mode
;
562 rtx addr
, plus0
, plus1
;
564 /* Eliminate non-memory operations */
565 if (GET_CODE (op
) != MEM
)
568 /* dword operations really put out 2 instructions, so eliminate them. */
569 /* ??? This isn't strictly correct. It is OK to accept multiword modes
570 here, since the length attributes are being set correctly, but only
571 if the address is offsettable. LO_SUM is not offsettable. */
572 if (GET_MODE_SIZE (GET_MODE (op
)) > UNITS_PER_WORD
)
575 /* Decode the address now. */
577 switch (GET_CODE (addr
))
584 return SMALL_INT (op
);
587 plus0
= XEXP (addr
, 0);
588 plus1
= XEXP (addr
, 1);
589 return ((GET_CODE (plus0
) == REG
590 && GET_CODE (plus1
) == CONST_INT
&& SMALL_INT (plus1
))
591 || (GET_CODE (plus1
) == REG
592 && GET_CODE (plus0
) == CONST_INT
&& SMALL_INT (plus0
)));
595 /* We used to allow small symbol refs here (ie, stuff in .sdata
596 or .sbss), but this causes some bugs in G++. Also, it won't
597 interfere if the MIPS linker rewrites the store instruction
598 because the function is PIC. */
600 case LABEL_REF
: /* never gp relative */
604 /* If -G 0, we can never have a GP relative memory operation.
605 Also, save some time if not optimizing. */
610 rtx offset
= const0_rtx
;
611 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
612 if (GET_CODE (op
) != SYMBOL_REF
)
615 /* let's be paranoid.... */
616 if (! SMALL_INT (offset
))
623 return SYMBOL_REF_FLAG (addr
);
633 /* Return nonzero if the code of this rtx pattern is EQ or NE. */
636 equality_op (op
, mode
)
638 enum machine_mode mode
;
640 if (mode
!= GET_MODE (op
))
643 return GET_CODE (op
) == EQ
|| GET_CODE (op
) == NE
;
646 /* Return nonzero if the code is a relational operations (EQ, LE, etc.) */
651 enum machine_mode mode
;
653 if (mode
!= GET_MODE (op
))
656 return GET_RTX_CLASS (GET_CODE (op
)) == '<';
659 /* Return nonzero if the operand is either the PC or a label_ref. */
662 pc_or_label_operand (op
, mode
)
664 enum machine_mode mode
;
669 if (GET_CODE (op
) == LABEL_REF
)
675 /* Test for a valid operand for a call instruction.
676 Don't allow the arg pointer register or virtual regs
677 since they may change into reg + const, which the patterns
681 call_insn_operand (op
, mode
)
683 enum machine_mode mode
;
685 return (CONSTANT_ADDRESS_P (op
)
686 || (GET_CODE (op
) == REG
&& op
!= arg_pointer_rtx
687 && ! (REGNO (op
) >= FIRST_PSEUDO_REGISTER
688 && REGNO (op
) <= LAST_VIRTUAL_REGISTER
)));
691 /* Return nonzero if OPERAND is valid as a source operand for a move
695 move_operand (op
, mode
)
697 enum machine_mode mode
;
699 /* Accept any general operand after reload has started; doing so
700 avoids losing if reload does an in-place replacement of a register
701 with a SYMBOL_REF or CONST. */
702 return (general_operand (op
, mode
)
703 && (! (mips_split_addresses
&& mips_check_split (op
, mode
))
704 || reload_in_progress
|| reload_completed
));
707 /* Return nonzero if OPERAND is valid as a source operand for movdi.
708 This accepts not only general_operand, but also sign extended
709 constants and registers. We need to accept sign extended constants
710 in case a sign extended register which is used in an expression,
711 and is equivalent to a constant, is spilled. */
714 movdi_operand (op
, mode
)
716 enum machine_mode mode
;
720 && GET_CODE (op
) == SIGN_EXTEND
721 && GET_MODE (op
) == DImode
722 && (GET_MODE (XEXP (op
, 0)) == SImode
723 || (GET_CODE (XEXP (op
, 0)) == CONST_INT
724 && GET_MODE (XEXP (op
, 0)) == VOIDmode
))
725 && (register_operand (XEXP (op
, 0), SImode
)
726 || immediate_operand (XEXP (op
, 0), SImode
)))
729 return general_operand (op
, mode
);
732 /* Like register_operand, but when in 64 bit mode also accept a sign
733 extend of a 32 bit register, since the value is known to be already
737 se_register_operand (op
, mode
)
739 enum machine_mode mode
;
743 && GET_CODE (op
) == SIGN_EXTEND
744 && GET_MODE (op
) == DImode
745 && GET_MODE (XEXP (op
, 0)) == SImode
746 && register_operand (XEXP (op
, 0), SImode
))
749 return register_operand (op
, mode
);
752 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
753 extend of a 32 bit register, since the value is known to be already
757 se_reg_or_0_operand (op
, mode
)
759 enum machine_mode mode
;
763 && GET_CODE (op
) == SIGN_EXTEND
764 && GET_MODE (op
) == DImode
765 && GET_MODE (XEXP (op
, 0)) == SImode
766 && register_operand (XEXP (op
, 0), SImode
))
769 return reg_or_0_operand (op
, mode
);
772 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
773 extend of a 32 bit register, since the value is known to be already
777 se_uns_arith_operand (op
, mode
)
779 enum machine_mode mode
;
783 && GET_CODE (op
) == SIGN_EXTEND
784 && GET_MODE (op
) == DImode
785 && GET_MODE (XEXP (op
, 0)) == SImode
786 && register_operand (XEXP (op
, 0), SImode
))
789 return uns_arith_operand (op
, mode
);
792 /* Like arith_operand, but when in 64 bit mode also accept a sign
793 extend of a 32 bit register, since the value is known to be already
797 se_arith_operand (op
, mode
)
799 enum machine_mode mode
;
803 && GET_CODE (op
) == SIGN_EXTEND
804 && GET_MODE (op
) == DImode
805 && GET_MODE (XEXP (op
, 0)) == SImode
806 && register_operand (XEXP (op
, 0), SImode
))
809 return arith_operand (op
, mode
);
812 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
813 extend of a 32 bit register, since the value is known to be already
817 se_nonmemory_operand (op
, mode
)
819 enum machine_mode mode
;
823 && GET_CODE (op
) == SIGN_EXTEND
824 && GET_MODE (op
) == DImode
825 && GET_MODE (XEXP (op
, 0)) == SImode
826 && register_operand (XEXP (op
, 0), SImode
))
829 return nonmemory_operand (op
, mode
);
832 /* Like nonimmediate_operand, but when in 64 bit mode also accept a
833 sign extend of a 32 bit register, since the value is known to be
834 already sign extended. */
837 se_nonimmediate_operand (op
, mode
)
839 enum machine_mode mode
;
843 && GET_CODE (op
) == SIGN_EXTEND
844 && GET_MODE (op
) == DImode
845 && GET_MODE (XEXP (op
, 0)) == SImode
846 && register_operand (XEXP (op
, 0), SImode
))
849 return nonimmediate_operand (op
, mode
);
852 /* Return nonzero if we split the address into high and low parts. */
854 /* ??? We should also handle reg+array somewhere. We get four
855 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
856 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
857 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
858 out of the address, then we have 4 instructions to combine. Perhaps
859 add a 3->2 define_split for combine. */
861 /* ??? We could also split a CONST_INT here if it is a large_int().
862 However, it doesn't seem to be very useful to have %hi(constant).
863 We would be better off by doing the masking ourselves and then putting
864 the explicit high part of the constant in the RTL. This will give better
865 optimization. Also, %hi(constant) needs assembler changes to work.
866 There is already a define_split that does this. */
869 mips_check_split (address
, mode
)
871 enum machine_mode mode
;
873 /* ??? This is the same check used in simple_memory_operand.
874 We use it here because LO_SUM is not offsettable. */
875 if (GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
878 if ((GET_CODE (address
) == SYMBOL_REF
&& ! SYMBOL_REF_FLAG (address
))
879 || (GET_CODE (address
) == CONST
880 && GET_CODE (XEXP (XEXP (address
, 0), 0)) == SYMBOL_REF
881 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address
, 0), 0)))
882 || GET_CODE (address
) == LABEL_REF
)
888 /* Returns an operand string for the given instruction's delay slot,
889 after updating filled delay slot statistics.
891 We assume that operands[0] is the target register that is set.
893 In order to check the next insn, most of this functionality is moved
894 to FINAL_PRESCAN_INSN, and we just set the global variables that
897 /* ??? This function no longer does anything useful, because final_prescan_insn
898 now will never emit a nop. */
901 mips_fill_delay_slot (ret
, type
, operands
, cur_insn
)
902 char *ret
; /* normal string to return */
903 enum delay_type type
; /* type of delay */
904 rtx operands
[]; /* operands to use */
905 rtx cur_insn
; /* current insn */
907 register rtx set_reg
;
908 register enum machine_mode mode
;
909 register rtx next_insn
= cur_insn
? NEXT_INSN (cur_insn
) : NULL_RTX
;
910 register int num_nops
;
912 if (type
== DELAY_LOAD
|| type
== DELAY_FCMP
)
915 else if (type
== DELAY_HILO
)
921 /* Make sure that we don't put nop's after labels. */
922 next_insn
= NEXT_INSN (cur_insn
);
923 while (next_insn
!= 0 && GET_CODE (next_insn
) == NOTE
)
924 next_insn
= NEXT_INSN (next_insn
);
926 dslots_load_total
+= num_nops
;
927 if (TARGET_DEBUG_F_MODE
929 || type
== DELAY_NONE
933 || GET_CODE (next_insn
) == CODE_LABEL
934 || (set_reg
= operands
[0]) == 0)
936 dslots_number_nops
= 0;
944 set_reg
= operands
[0];
948 while (GET_CODE (set_reg
) == SUBREG
)
949 set_reg
= SUBREG_REG (set_reg
);
951 mode
= GET_MODE (set_reg
);
952 dslots_number_nops
= num_nops
;
953 mips_load_reg
= set_reg
;
954 if (GET_MODE_SIZE (mode
)
955 > (FP_REG_P (REGNO (set_reg
)) ? UNITS_PER_FPREG
: UNITS_PER_WORD
))
956 mips_load_reg2
= gen_rtx_REG (SImode
, REGNO (set_reg
) + 1);
960 if (type
== DELAY_HILO
)
962 mips_load_reg3
= gen_rtx_REG (SImode
, MD_REG_FIRST
);
963 mips_load_reg4
= gen_rtx_REG (SImode
, MD_REG_FIRST
+1);
975 /* Determine whether a memory reference takes one (based off of the GP
976 pointer), two (normal), or three (label + reg) instructions, and bump the
977 appropriate counter for -mstats. */
980 mips_count_memory_refs (op
, num
)
986 rtx addr
, plus0
, plus1
;
987 enum rtx_code code0
, code1
;
990 if (TARGET_DEBUG_B_MODE
)
992 fprintf (stderr
, "\n========== mips_count_memory_refs:\n");
996 /* Skip MEM if passed, otherwise handle movsi of address. */
997 addr
= (GET_CODE (op
) != MEM
) ? op
: XEXP (op
, 0);
999 /* Loop, going through the address RTL. */
1003 switch (GET_CODE (addr
))
1011 plus0
= XEXP (addr
, 0);
1012 plus1
= XEXP (addr
, 1);
1013 code0
= GET_CODE (plus0
);
1014 code1
= GET_CODE (plus1
);
1024 if (code0
== CONST_INT
)
1039 if (code1
== CONST_INT
)
1046 if (code0
== SYMBOL_REF
|| code0
== LABEL_REF
|| code0
== CONST
)
1053 if (code1
== SYMBOL_REF
|| code1
== LABEL_REF
|| code1
== CONST
)
1063 n_words
= 2; /* always 2 words */
1067 addr
= XEXP (addr
, 0);
1072 n_words
= SYMBOL_REF_FLAG (addr
) ? 1 : 2;
1084 n_words
+= additional
;
1088 num_refs
[n_words
-1] += num
;
1092 /* Return RTL for the offset from the current function to the argument.
1094 ??? Which argument is this? */
1097 embedded_pic_offset (x
)
1100 if (embedded_pic_fnaddr_rtx
== NULL
)
1104 embedded_pic_fnaddr_rtx
= gen_reg_rtx (Pmode
);
1106 /* Output code at function start to initialize the pseudo-reg. */
1107 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
1108 inline functions, because it is called after RTL for the function
1109 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
1110 does not get copied, and ends up not matching the rest of the RTL.
1111 This solution works, but means that we get unnecessary code to
1112 initialize this value every time a function is inlined into another
1115 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx
,
1116 XEXP (DECL_RTL (current_function_decl
), 0)));
1117 seq
= gen_sequence ();
1119 push_topmost_sequence ();
1120 emit_insn_after (seq
, get_insns ());
1121 pop_topmost_sequence ();
1125 gen_rtx_CONST (Pmode
,
1126 gen_rtx_MINUS (Pmode
, x
,
1127 XEXP (DECL_RTL (current_function_decl
), 0)));
1130 /* Return the appropriate instructions to move one operand to another. */
1133 mips_move_1word (operands
, insn
, unsignedp
)
1139 rtx op0
= operands
[0];
1140 rtx op1
= operands
[1];
1141 enum rtx_code code0
= GET_CODE (op0
);
1142 enum rtx_code code1
= GET_CODE (op1
);
1143 enum machine_mode mode
= GET_MODE (op0
);
1144 int subreg_word0
= 0;
1145 int subreg_word1
= 0;
1146 enum delay_type delay
= DELAY_NONE
;
1148 while (code0
== SUBREG
)
1150 subreg_word0
+= SUBREG_WORD (op0
);
1151 op0
= SUBREG_REG (op0
);
1152 code0
= GET_CODE (op0
);
1155 while (code1
== SUBREG
)
1157 subreg_word1
+= SUBREG_WORD (op1
);
1158 op1
= SUBREG_REG (op1
);
1159 code1
= GET_CODE (op1
);
1162 /* For our purposes, a condition code mode is the same as SImode. */
1168 int regno0
= REGNO (op0
) + subreg_word0
;
1172 int regno1
= REGNO (op1
) + subreg_word1
;
1174 /* Just in case, don't do anything for assigning a register
1175 to itself, unless we are filling a delay slot. */
1176 if (regno0
== regno1
&& set_nomacro
== 0)
1179 else if (GP_REG_P (regno0
))
1181 if (GP_REG_P (regno1
))
1182 ret
= "move\t%0,%1";
1184 else if (MD_REG_P (regno1
))
1187 if (regno1
!= HILO_REGNUM
)
1193 else if (ST_REG_P (regno1
) && mips_isa
>= 4)
1194 ret
= "li\t%0,1\n\tmovf\t%0,%.,%1";
1199 if (FP_REG_P (regno1
))
1200 ret
= "mfc1\t%0,%1";
1202 else if (regno1
== FPSW_REGNUM
&& mips_isa
< 4)
1203 ret
= "cfc1\t%0,$31";
1207 else if (FP_REG_P (regno0
))
1209 if (GP_REG_P (regno1
))
1212 ret
= "mtc1\t%1,%0";
1215 if (FP_REG_P (regno1
))
1216 ret
= "mov.s\t%0,%1";
1219 else if (MD_REG_P (regno0
))
1221 if (GP_REG_P (regno1
))
1224 if (regno0
!= HILO_REGNUM
)
1229 else if (regno0
== FPSW_REGNUM
&& mips_isa
< 4)
1231 if (GP_REG_P (regno1
))
1234 ret
= "ctc1\t%0,$31";
1239 else if (code1
== MEM
)
1244 mips_count_memory_refs (op1
, 1);
1246 if (GP_REG_P (regno0
))
1248 /* For loads, use the mode of the memory item, instead of the
1249 target, so zero/sign extend can use this code as well. */
1250 switch (GET_MODE (op1
))
1259 ret
= ((unsignedp
&& TARGET_64BIT
)
1264 ret
= (unsignedp
) ? "lhu\t%0,%1" : "lh\t%0,%1";
1267 ret
= (unsignedp
) ? "lbu\t%0,%1" : "lb\t%0,%1";
1272 else if (FP_REG_P (regno0
) && (mode
== SImode
|| mode
== SFmode
))
1275 if (ret
!= (char *)0 && MEM_VOLATILE_P (op1
))
1277 int i
= strlen (ret
);
1278 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1281 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1282 ret
= volatile_buffer
;
1286 else if (code1
== CONST_INT
1287 || (code1
== CONST_DOUBLE
1288 && GET_MODE (op1
) == VOIDmode
))
1290 if (code1
== CONST_DOUBLE
)
1292 /* This can happen when storing constants into long long
1293 bitfields. Just store the least significant word of
1295 operands
[1] = op1
= GEN_INT (CONST_DOUBLE_LOW (op1
));
1298 if (INTVAL (op1
) == 0)
1300 if (GP_REG_P (regno0
))
1301 ret
= "move\t%0,%z1";
1303 else if (FP_REG_P (regno0
))
1306 ret
= "mtc1\t%z1,%0";
1309 else if (MD_REG_P (regno0
))
1316 else if (GP_REG_P (regno0
))
1317 /* Don't use X format, because that will give out of range
1318 numbers for 64 bit host and 32 bit target. */
1319 ret
= "li\t%0,%1\t\t\t# %X1";
1322 else if (code1
== CONST_DOUBLE
&& mode
== SFmode
)
1324 if (op1
== CONST0_RTX (SFmode
))
1326 if (GP_REG_P (regno0
))
1327 ret
= "move\t%0,%.";
1329 else if (FP_REG_P (regno0
))
1332 ret
= "mtc1\t%.,%0";
1339 ret
= "li.s\t%0,%1";
1343 else if (code1
== LABEL_REF
)
1346 mips_count_memory_refs (op1
, 1);
1351 else if (code1
== SYMBOL_REF
|| code1
== CONST
)
1353 if (HALF_PIC_P () && CONSTANT_P (op1
) && HALF_PIC_ADDRESS_P (op1
))
1355 rtx offset
= const0_rtx
;
1357 if (GET_CODE (op1
) == CONST
)
1358 op1
= eliminate_constant_term (XEXP (op1
, 0), &offset
);
1360 if (GET_CODE (op1
) == SYMBOL_REF
)
1362 operands
[2] = HALF_PIC_PTR (op1
);
1365 mips_count_memory_refs (operands
[2], 1);
1367 if (INTVAL (offset
) == 0)
1370 ret
= (unsignedp
&& TARGET_64BIT
1376 dslots_load_total
++;
1377 operands
[3] = offset
;
1378 if (unsignedp
&& TARGET_64BIT
)
1379 ret
= (SMALL_INT (offset
)
1380 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
1381 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
1383 ret
= (SMALL_INT (offset
)
1384 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
1385 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]");
1392 mips_count_memory_refs (op1
, 1);
1398 else if (code1
== PLUS
)
1400 rtx add_op0
= XEXP (op1
, 0);
1401 rtx add_op1
= XEXP (op1
, 1);
1403 if (GET_CODE (XEXP (op1
, 1)) == REG
1404 && GET_CODE (XEXP (op1
, 0)) == CONST_INT
)
1405 add_op0
= XEXP (op1
, 1), add_op1
= XEXP (op1
, 0);
1407 operands
[2] = add_op0
;
1408 operands
[3] = add_op1
;
1409 ret
= "add%:\t%0,%2,%3";
1412 else if (code1
== HIGH
)
1414 operands
[1] = XEXP (op1
, 0);
1415 ret
= "lui\t%0,%%hi(%1)";
1419 else if (code0
== MEM
)
1422 mips_count_memory_refs (op0
, 1);
1426 int regno1
= REGNO (op1
) + subreg_word1
;
1428 if (GP_REG_P (regno1
))
1432 case SFmode
: ret
= "sw\t%1,%0"; break;
1433 case SImode
: ret
= "sw\t%1,%0"; break;
1434 case HImode
: ret
= "sh\t%1,%0"; break;
1435 case QImode
: ret
= "sb\t%1,%0"; break;
1440 else if (FP_REG_P (regno1
) && (mode
== SImode
|| mode
== SFmode
))
1444 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
1448 case SFmode
: ret
= "sw\t%z1,%0"; break;
1449 case SImode
: ret
= "sw\t%z1,%0"; break;
1450 case HImode
: ret
= "sh\t%z1,%0"; break;
1451 case QImode
: ret
= "sb\t%z1,%0"; break;
1456 else if (code1
== CONST_DOUBLE
&& op1
== CONST0_RTX (mode
))
1460 case SFmode
: ret
= "sw\t%.,%0"; break;
1461 case SImode
: ret
= "sw\t%.,%0"; break;
1462 case HImode
: ret
= "sh\t%.,%0"; break;
1463 case QImode
: ret
= "sb\t%.,%0"; break;
1468 if (ret
!= 0 && MEM_VOLATILE_P (op0
))
1470 int i
= strlen (ret
);
1472 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1475 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1476 ret
= volatile_buffer
;
1482 abort_with_insn (insn
, "Bad move");
1486 if (delay
!= DELAY_NONE
)
1487 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
1493 /* Return the appropriate instructions to move 2 words */
1496 mips_move_2words (operands
, insn
)
1501 rtx op0
= operands
[0];
1502 rtx op1
= operands
[1];
1503 enum rtx_code code0
= GET_CODE (operands
[0]);
1504 enum rtx_code code1
= GET_CODE (operands
[1]);
1505 int subreg_word0
= 0;
1506 int subreg_word1
= 0;
1507 enum delay_type delay
= DELAY_NONE
;
1509 while (code0
== SUBREG
)
1511 subreg_word0
+= SUBREG_WORD (op0
);
1512 op0
= SUBREG_REG (op0
);
1513 code0
= GET_CODE (op0
);
1516 if (code1
== SIGN_EXTEND
)
1518 op1
= XEXP (op1
, 0);
1519 code1
= GET_CODE (op1
);
1522 while (code1
== SUBREG
)
1524 subreg_word1
+= SUBREG_WORD (op1
);
1525 op1
= SUBREG_REG (op1
);
1526 code1
= GET_CODE (op1
);
1530 if (GET_CODE (operands
[1]) == SIGN_EXTEND
1532 && code1
!= CONST_INT
1533 /* The following three can happen as the result of a questionable
1535 && code1
!= LABEL_REF
1536 && code1
!= SYMBOL_REF
1542 int regno0
= REGNO (op0
) + subreg_word0
;
1546 int regno1
= REGNO (op1
) + subreg_word1
;
1548 /* Just in case, don't do anything for assigning a register
1549 to itself, unless we are filling a delay slot. */
1550 if (regno0
== regno1
&& set_nomacro
== 0)
1553 else if (FP_REG_P (regno0
))
1555 if (FP_REG_P (regno1
))
1556 ret
= "mov.d\t%0,%1";
1564 abort_with_insn (insn
, "Bad move");
1566 #ifdef TARGET_FP_CALL_32
1567 if (FP_CALL_GP_REG_P (regno1
))
1568 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
1571 ret
= "dmtc1\t%1,%0";
1574 ret
= "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
1578 else if (FP_REG_P (regno1
))
1584 abort_with_insn (insn
, "Bad move");
1586 #ifdef TARGET_FP_CALL_32
1587 if (FP_CALL_GP_REG_P (regno0
))
1588 ret
= "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
1591 ret
= "dmfc1\t%0,%1";
1594 ret
= "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
1597 else if (MD_REG_P (regno0
) && GP_REG_P (regno1
))
1602 if (regno0
!= HILO_REGNUM
)
1604 else if (regno1
== 0)
1605 ret
= "mtlo\t%.\n\tmthi\t%.";
1608 ret
= "mthi\t%M1\n\tmtlo\t%L1";
1611 else if (GP_REG_P (regno0
) && MD_REG_P (regno1
))
1616 if (regno1
!= HILO_REGNUM
)
1620 ret
= "mfhi\t%M0\n\tmflo\t%L0";
1623 else if (TARGET_64BIT
)
1624 ret
= "move\t%0,%1";
1626 else if (regno0
!= (regno1
+1))
1627 ret
= "move\t%0,%1\n\tmove\t%D0,%D1";
1630 ret
= "move\t%D0,%D1\n\tmove\t%0,%1";
1633 else if (code1
== CONST_DOUBLE
)
1635 /* Move zero from $0 unless !TARGET_64BIT and recipient
1636 is 64-bit fp reg, in which case generate a constant. */
1637 if (op1
!= CONST0_RTX (GET_MODE (op1
))
1638 || (TARGET_FLOAT64
&& !TARGET_64BIT
&& FP_REG_P (regno0
)))
1640 if (GET_MODE (op1
) == DFmode
)
1644 #ifdef TARGET_FP_CALL_32
1645 if (FP_CALL_GP_REG_P (regno0
))
1647 if (TARGET_FLOAT64
&& !TARGET_64BIT
)
1649 split_double (op1
, operands
+ 2, operands
+ 3);
1650 ret
= "li\t%0,%2\n\tli\t%D0,%3";
1653 ret
= "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
1657 ret
= "li.d\t%0,%1";
1660 else if (TARGET_64BIT
)
1665 split_double (op1
, operands
+ 2, operands
+ 3);
1666 ret
= "li\t%0,%2\n\tli\t%D0,%3";
1672 if (GP_REG_P (regno0
))
1674 #ifdef TARGET_FP_CALL_32
1675 && ! FP_CALL_GP_REG_P (regno0
)
1678 : "move\t%0,%.\n\tmove\t%D0,%.");
1680 else if (FP_REG_P (regno0
))
1685 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
1690 else if (code1
== CONST_INT
&& INTVAL (op1
) == 0)
1692 if (GP_REG_P (regno0
))
1695 : "move\t%0,%.\n\tmove\t%D0,%.");
1697 else if (FP_REG_P (regno0
))
1704 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0"));
1706 else if (MD_REG_P (regno0
))
1709 ret
= (regno0
== HILO_REGNUM
1710 ? "mtlo\t%.\n\tmthi\t%."
1715 else if (code1
== CONST_INT
&& GET_MODE (op0
) == DImode
1716 && GP_REG_P (regno0
))
1720 if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
1721 ret
= "li\t%0,%1\t\t# %X1";
1722 else if (HOST_BITS_PER_WIDE_INT
< 64)
1723 /* We can't use 'X' for negative numbers, because then we won't
1724 get the right value for the upper 32 bits. */
1725 ret
= (INTVAL (op1
) < 0
1726 ? "dli\t%0,%1\t\t\t# %X1"
1727 : "dli\t%0,%X1\t\t# %1");
1729 /* We must use 'X', because otherwise LONG_MIN will print as
1730 a number that the assembler won't accept. */
1731 ret
= "dli\t%0,%X1\t\t# %1";
1733 else if (HOST_BITS_PER_WIDE_INT
< 64)
1735 operands
[2] = GEN_INT (INTVAL (operands
[1]) >= 0 ? 0 : -1);
1736 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
1740 /* We use multiple shifts here, to avoid warnings about out
1741 of range shifts on 32 bit hosts. */
1742 operands
[2] = GEN_INT (INTVAL (operands
[1]) >> 16 >> 16);
1744 = GEN_INT (INTVAL (operands
[1]) << 16 << 16 >> 16 >> 16);
1745 ret
= "li\t%M0,%2\n\tli\t%L0,%1";
1749 else if (code1
== MEM
)
1754 mips_count_memory_refs (op1
, 2);
1756 if (FP_REG_P (regno0
))
1759 else if (TARGET_64BIT
)
1762 #ifdef TARGET_FP_CALL_32
1763 if (FP_CALL_GP_REG_P (regno0
))
1764 ret
= (offsettable_address_p (FALSE
, SImode
, op1
)
1765 ? "lwu\t%0,%1\n\tlwu\t%D0,4+%1"
1766 : "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32")
1772 else if (offsettable_address_p (1, DFmode
, XEXP (op1
, 0)))
1774 operands
[2] = adj_offsettable_operand (op1
, 4);
1775 ret
= (reg_mentioned_p (op0
, op1
)
1776 ? "lw\t%D0,%2\n\tlw\t%0,%1"
1777 : "lw\t%0,%1\n\tlw\t%D0,%2");
1780 if (ret
!= 0 && MEM_VOLATILE_P (op1
))
1782 int i
= strlen (ret
);
1784 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1787 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1788 ret
= volatile_buffer
;
1792 else if (code1
== LABEL_REF
|| code1
== SYMBOL_REF
|| code1
== CONST
)
1795 mips_count_memory_refs (op1
, 2);
1797 if (GET_CODE (operands
[1]) == SIGN_EXTEND
)
1798 /* We deliberately remove the 'a' from '%1', so that we don't
1799 have to add SIGN_EXTEND support to print_operand_address.
1800 print_operand will just call print_operand_address in this
1801 case, so there is no problem. */
1804 ret
= "dla\t%0,%a1";
1808 else if (code0
== MEM
)
1812 int regno1
= REGNO (op1
) + subreg_word1
;
1814 if (FP_REG_P (regno1
))
1817 else if (TARGET_64BIT
)
1820 #ifdef TARGET_FP_CALL_32
1821 if (FP_CALL_GP_REG_P (regno1
))
1822 ret
= "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
1828 else if (offsettable_address_p (1, DFmode
, XEXP (op0
, 0)))
1830 operands
[2] = adj_offsettable_operand (op0
, 4);
1831 ret
= "sw\t%1,%0\n\tsw\t%D1,%2";
1835 else if (((code1
== CONST_INT
&& INTVAL (op1
) == 0)
1836 || (code1
== CONST_DOUBLE
1837 && op1
== CONST0_RTX (GET_MODE (op1
))))
1839 || offsettable_address_p (1, DFmode
, XEXP (op0
, 0))))
1845 operands
[2] = adj_offsettable_operand (op0
, 4);
1846 ret
= "sw\t%.,%0\n\tsw\t%.,%2";
1851 mips_count_memory_refs (op0
, 2);
1853 if (ret
!= 0 && MEM_VOLATILE_P (op0
))
1855 int i
= strlen (ret
);
1857 if (i
> sizeof (volatile_buffer
) - sizeof ("%{%}"))
1860 sprintf (volatile_buffer
, "%%{%s%%}", ret
);
1861 ret
= volatile_buffer
;
1867 abort_with_insn (insn
, "Bad move");
1871 if (delay
!= DELAY_NONE
)
1872 return mips_fill_delay_slot (ret
, delay
, operands
, insn
);
1877 /* Provide the costs of an addressing mode that contains ADDR.
1878 If ADDR is not a valid address, its cost is irrelevant. */
1881 mips_address_cost (addr
)
1884 switch (GET_CODE (addr
))
1894 rtx offset
= const0_rtx
;
1895 addr
= eliminate_constant_term (XEXP (addr
, 0), &offset
);
1896 if (GET_CODE (addr
) == LABEL_REF
)
1899 if (GET_CODE (addr
) != SYMBOL_REF
)
1902 if (! SMALL_INT (offset
))
1906 /* ... fall through ... */
1909 return SYMBOL_REF_FLAG (addr
) ? 1 : 2;
1913 register rtx plus0
= XEXP (addr
, 0);
1914 register rtx plus1
= XEXP (addr
, 1);
1916 if (GET_CODE (plus0
) != REG
&& GET_CODE (plus1
) == REG
)
1917 plus0
= XEXP (addr
, 1), plus1
= XEXP (addr
, 0);
1919 if (GET_CODE (plus0
) != REG
)
1922 switch (GET_CODE (plus1
))
1925 return SMALL_INT (plus1
) ? 1 : 2;
1932 return mips_address_cost (plus1
) + 1;
1946 /* Return nonzero if X is an address which needs a temporary register when
1947 reloaded while generating PIC code. */
1950 pic_address_needs_scratch (x
)
1953 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
1954 if (GET_CODE (x
) == CONST
&& GET_CODE (XEXP (x
, 0)) == PLUS
1955 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
1956 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
1957 && ! SMALL_INT (XEXP (XEXP (x
, 0), 1)))
1963 /* Make normal rtx_code into something we can index from an array */
1965 static enum internal_test
1966 map_test_to_internal_test (test_code
)
1967 enum rtx_code test_code
;
1969 enum internal_test test
= ITEST_MAX
;
1973 case EQ
: test
= ITEST_EQ
; break;
1974 case NE
: test
= ITEST_NE
; break;
1975 case GT
: test
= ITEST_GT
; break;
1976 case GE
: test
= ITEST_GE
; break;
1977 case LT
: test
= ITEST_LT
; break;
1978 case LE
: test
= ITEST_LE
; break;
1979 case GTU
: test
= ITEST_GTU
; break;
1980 case GEU
: test
= ITEST_GEU
; break;
1981 case LTU
: test
= ITEST_LTU
; break;
1982 case LEU
: test
= ITEST_LEU
; break;
1990 /* Generate the code to compare two integer values. The return value is:
1991 (reg:SI xx) The pseudo register the comparison is in
1992 0 No register, generate a simple branch.
1994 ??? This is called with result nonzero by the Scond patterns in
1995 mips.md. These patterns are called with a target in the mode of
1996 the Scond instruction pattern. Since this must be a constant, we
1997 must use SImode. This means that if RESULT is non-zero, it will
1998 always be an SImode register, even if TARGET_64BIT is true. We
1999 cope with this by calling convert_move rather than emit_move_insn.
2000 This will sometimes lead to an unnecessary extension of the result;
2012 gen_int_relational (test_code
, result
, cmp0
, cmp1
, p_invert
)
2013 enum rtx_code test_code
; /* relational test (EQ, etc) */
2014 rtx result
; /* result to store comp. or 0 if branch */
2015 rtx cmp0
; /* first operand to compare */
2016 rtx cmp1
; /* second operand to compare */
2017 int *p_invert
; /* NULL or ptr to hold whether branch needs */
2018 /* to reverse its test */
2022 enum rtx_code test_code
; /* code to use in instruction (LT vs. LTU) */
2023 int const_low
; /* low bound of constant we can accept */
2024 int const_high
; /* high bound of constant we can accept */
2025 int const_add
; /* constant to add (convert LE -> LT) */
2026 int reverse_regs
; /* reverse registers in test */
2027 int invert_const
; /* != 0 if invert value if cmp1 is constant */
2028 int invert_reg
; /* != 0 if invert value if cmp1 is register */
2029 int unsignedp
; /* != 0 for unsigned comparisons. */
2032 static struct cmp_info info
[ (int)ITEST_MAX
] = {
2034 { XOR
, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2035 { XOR
, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2036 { LT
, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2037 { LT
, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2038 { LT
, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2039 { LT
, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2040 { LTU
, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2041 { LTU
, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2042 { LTU
, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2043 { LTU
, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
2046 enum internal_test test
;
2047 enum machine_mode mode
;
2048 struct cmp_info
*p_info
;
2055 test
= map_test_to_internal_test (test_code
);
2056 if (test
== ITEST_MAX
)
2059 p_info
= &info
[(int) test
];
2060 eqne_p
= (p_info
->test_code
== XOR
);
2062 mode
= GET_MODE (cmp0
);
2063 if (mode
== VOIDmode
)
2064 mode
= GET_MODE (cmp1
);
2066 /* Eliminate simple branches */
2067 branch_p
= (result
== 0);
2070 if (GET_CODE (cmp0
) == REG
|| GET_CODE (cmp0
) == SUBREG
)
2072 /* Comparisons against zero are simple branches */
2073 if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
2076 /* Test for beq/bne. */
2081 /* allocate a pseudo to calculate the value in. */
2082 result
= gen_reg_rtx (mode
);
2085 /* Make sure we can handle any constants given to us. */
2086 if (GET_CODE (cmp0
) == CONST_INT
)
2087 cmp0
= force_reg (mode
, cmp0
);
2089 if (GET_CODE (cmp1
) == CONST_INT
)
2091 HOST_WIDE_INT value
= INTVAL (cmp1
);
2093 if (value
< p_info
->const_low
2094 || value
> p_info
->const_high
2095 /* ??? Why? And why wasn't the similar code below modified too? */
2097 && HOST_BITS_PER_WIDE_INT
< 64
2098 && p_info
->const_add
!= 0
2099 && ((p_info
->unsignedp
2100 ? ((unsigned HOST_WIDE_INT
) (value
+ p_info
->const_add
)
2102 : (value
+ p_info
->const_add
) > INTVAL (cmp1
))
2103 != (p_info
->const_add
> 0))))
2104 cmp1
= force_reg (mode
, cmp1
);
2107 /* See if we need to invert the result. */
2108 invert
= (GET_CODE (cmp1
) == CONST_INT
2109 ? p_info
->invert_const
: p_info
->invert_reg
);
2111 if (p_invert
!= (int *)0)
2117 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2118 Comparison between two registers, may involve switching operands. */
2119 if (GET_CODE (cmp1
) == CONST_INT
)
2121 if (p_info
->const_add
!= 0)
2123 HOST_WIDE_INT
new = INTVAL (cmp1
) + p_info
->const_add
;
2125 /* If modification of cmp1 caused overflow,
2126 we would get the wrong answer if we follow the usual path;
2127 thus, x > 0xffffffffU would turn into x > 0U. */
2128 if ((p_info
->unsignedp
2129 ? (unsigned HOST_WIDE_INT
) new > INTVAL (cmp1
)
2130 : new > INTVAL (cmp1
))
2131 != (p_info
->const_add
> 0))
2133 /* This test is always true, but if INVERT is true then
2134 the result of the test needs to be inverted so 0 should
2135 be returned instead. */
2136 emit_move_insn (result
, invert
? const0_rtx
: const_true_rtx
);
2140 cmp1
= GEN_INT (new);
2144 else if (p_info
->reverse_regs
)
2151 if (test
== ITEST_NE
&& GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) == 0)
2155 reg
= (invert
|| eqne_p
) ? gen_reg_rtx (mode
) : result
;
2156 convert_move (reg
, gen_rtx (p_info
->test_code
, mode
, cmp0
, cmp1
), 0);
2159 if (test
== ITEST_NE
)
2161 convert_move (result
, gen_rtx_GTU (mode
, reg
, const0_rtx
), 0);
2165 else if (test
== ITEST_EQ
)
2167 reg2
= invert
? gen_reg_rtx (mode
) : result
;
2168 convert_move (reg2
, gen_rtx_LTU (mode
, reg
, const1_rtx
), 0);
2173 convert_move (result
, gen_rtx_XOR (mode
, reg
, const1_rtx
), 0);
2178 /* Emit the common code for doing conditional branches.
2179 operand[0] is the label to jump to.
2180 The comparison operands are saved away by cmp{si,di,sf,df}. */
2183 gen_conditional_branch (operands
, test_code
)
2185 enum rtx_code test_code
;
2187 enum cmp_type type
= branch_type
;
2188 rtx cmp0
= branch_cmp
[0];
2189 rtx cmp1
= branch_cmp
[1];
2190 enum machine_mode mode
;
2199 mode
= type
== CMP_SI
? SImode
: DImode
;
2201 reg
= gen_int_relational (test_code
, NULL_RTX
, cmp0
, cmp1
, &invert
);
2209 else if (GET_CODE (cmp1
) == CONST_INT
&& INTVAL (cmp1
) != 0)
2210 /* We don't want to build a comparison against a non-zero
2212 cmp1
= force_reg (mode
, cmp1
);
2219 reg
= gen_rtx_REG (CCmode
, FPSW_REGNUM
);
2221 reg
= gen_reg_rtx (CCmode
);
2223 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
2224 0 in the instruction built below. The MIPS FPU handles
2225 inequality testing by testing for equality and looking for a
2227 emit_insn (gen_rtx_SET (VOIDmode
, reg
,
2228 gen_rtx (test_code
== NE
? EQ
: test_code
,
2229 CCmode
, cmp0
, cmp1
)));
2231 test_code
= test_code
== NE
? EQ
: NE
;
2239 abort_with_insn (gen_rtx (test_code
, VOIDmode
, cmp0
, cmp1
), "bad test");
2242 /* Generate the branch. */
2244 label1
= gen_rtx_LABEL_REF (VOIDmode
, operands
[0]);
2253 emit_jump_insn (gen_rtx_SET (VOIDmode
, pc_rtx
,
2254 gen_rtx_IF_THEN_ELSE (VOIDmode
,
2255 gen_rtx (test_code
, mode
,
2260 /* Emit the common code for conditional moves. OPERANDS is the array
2261 of operands passed to the conditional move defined_expand. */
2264 gen_conditional_move (operands
)
2267 rtx op0
= branch_cmp
[0];
2268 rtx op1
= branch_cmp
[1];
2269 enum machine_mode mode
= GET_MODE (branch_cmp
[0]);
2270 enum rtx_code cmp_code
= GET_CODE (operands
[1]);
2271 enum rtx_code move_code
= NE
;
2272 enum machine_mode op_mode
= GET_MODE (operands
[0]);
2273 enum machine_mode cmp_mode
;
2276 if (GET_MODE_CLASS (mode
) != MODE_FLOAT
)
2295 op0
= force_reg (mode
, branch_cmp
[1]);
2296 op1
= branch_cmp
[0];
2300 op0
= force_reg (mode
, branch_cmp
[1]);
2301 op1
= branch_cmp
[0];
2312 op0
= force_reg (mode
, branch_cmp
[1]);
2313 op1
= branch_cmp
[0];
2317 op0
= force_reg (mode
, branch_cmp
[1]);
2318 op1
= branch_cmp
[0];
2325 else if (cmp_code
== NE
)
2326 cmp_code
= EQ
, move_code
= EQ
;
2328 if (mode
== SImode
|| mode
== DImode
)
2330 else if (mode
== SFmode
|| mode
== DFmode
)
2335 cmp_reg
= gen_reg_rtx (cmp_mode
);
2336 emit_insn (gen_rtx_SET (cmp_mode
, cmp_reg
,
2337 gen_rtx (cmp_code
, cmp_mode
, op0
, op1
)));
2339 emit_insn (gen_rtx_SET (op_mode
, operands
[0],
2340 gen_rtx_IF_THEN_ELSE (op_mode
,
2341 gen_rtx (move_code
, VOIDmode
,
2343 CONST0_RTX (SImode
)),
2344 operands
[2], operands
[3])));
2347 /* Write a loop to move a constant number of bytes.
2348 Generate load/stores as follows:
2354 temp<last> = src[MAX_MOVE_REGS-1];
2358 dest[MAX_MOVE_REGS-1] = temp<last>;
2359 src += MAX_MOVE_REGS;
2360 dest += MAX_MOVE_REGS;
2361 } while (src != final);
2363 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
2364 registers are needed.
2366 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
2367 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
2368 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
2370 #define MAX_MOVE_REGS 4
2371 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
2374 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_dest
, orig_src
)
2375 rtx dest_reg
; /* register holding destination address */
2376 rtx src_reg
; /* register holding source address */
2377 int bytes
; /* # bytes to move */
2378 int align
; /* alignment */
2379 rtx orig_dest
; /* original dest for change_address */
2380 rtx orig_src
; /* original source for making a reg note */
2382 rtx dest_mem
= change_address (orig_dest
, BLKmode
, dest_reg
);
2383 rtx src_mem
= change_address (orig_src
, BLKmode
, src_reg
);
2384 rtx align_rtx
= GEN_INT (align
);
2390 if (bytes
< 2 * MAX_MOVE_BYTES
)
2393 leftover
= bytes
% MAX_MOVE_BYTES
;
2396 label
= gen_label_rtx ();
2397 final_src
= gen_reg_rtx (Pmode
);
2398 bytes_rtx
= GEN_INT (bytes
);
2404 emit_insn (gen_movdi (final_src
, bytes_rtx
));
2405 emit_insn (gen_adddi3 (final_src
, final_src
, src_reg
));
2409 emit_insn (gen_movsi (final_src
, bytes_rtx
));
2410 emit_insn (gen_addsi3 (final_src
, final_src
, src_reg
));
2416 emit_insn (gen_adddi3 (final_src
, src_reg
, bytes_rtx
));
2418 emit_insn (gen_addsi3 (final_src
, src_reg
, bytes_rtx
));
2423 bytes_rtx
= GEN_INT (MAX_MOVE_BYTES
);
2424 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
, bytes_rtx
, align_rtx
));
2428 emit_insn (gen_adddi3 (src_reg
, src_reg
, bytes_rtx
));
2429 emit_insn (gen_adddi3 (dest_reg
, dest_reg
, bytes_rtx
));
2430 emit_insn (gen_cmpdi (src_reg
, final_src
));
2434 emit_insn (gen_addsi3 (src_reg
, src_reg
, bytes_rtx
));
2435 emit_insn (gen_addsi3 (dest_reg
, dest_reg
, bytes_rtx
));
2436 emit_insn (gen_cmpsi (src_reg
, final_src
));
2439 emit_jump_insn (gen_bne (label
));
2442 emit_insn (gen_movstrsi_internal (dest_mem
, src_mem
, GEN_INT (leftover
),
2446 /* Use a library function to move some bytes. */
2449 block_move_call (dest_reg
, src_reg
, bytes_rtx
)
2454 /* We want to pass the size as Pmode, which will normally be SImode
2455 but will be DImode if we are using 64 bit longs and pointers. */
2456 if (GET_MODE (bytes_rtx
) != VOIDmode
2457 && GET_MODE (bytes_rtx
) != Pmode
)
2458 bytes_rtx
= convert_to_mode (Pmode
, bytes_rtx
, 1);
2460 #ifdef TARGET_MEM_FUNCTIONS
2461 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "memcpy"), 0,
2462 VOIDmode
, 3, dest_reg
, Pmode
, src_reg
, Pmode
,
2463 convert_to_mode (TYPE_MODE (sizetype
), bytes_rtx
,
2464 TREE_UNSIGNED (sizetype
)),
2465 TYPE_MODE (sizetype
));
2467 emit_library_call (gen_rtx_SYMBOL_REF (Pmode
, "bcopy"), 0,
2468 VOIDmode
, 3, src_reg
, Pmode
, dest_reg
, Pmode
,
2469 convert_to_mode (TYPE_MODE (integer_type_node
), bytes_rtx
,
2470 TREE_UNSIGNED (integer_type_node
)),
2471 TYPE_MODE (integer_type_node
));
2475 /* Expand string/block move operations.
2477 operands[0] is the pointer to the destination.
2478 operands[1] is the pointer to the source.
2479 operands[2] is the number of bytes to move.
2480 operands[3] is the alignment. */
2483 expand_block_move (operands
)
2486 rtx bytes_rtx
= operands
[2];
2487 rtx align_rtx
= operands
[3];
2488 int constp
= GET_CODE (bytes_rtx
) == CONST_INT
;
2489 HOST_WIDE_INT bytes
= constp
? INTVAL (bytes_rtx
) : 0;
2490 int align
= INTVAL (align_rtx
);
2491 rtx orig_src
= operands
[1];
2492 rtx orig_dest
= operands
[0];
2496 if (constp
&& bytes
<= 0)
2499 if (align
> UNITS_PER_WORD
)
2500 align
= UNITS_PER_WORD
;
2502 /* Move the address into scratch registers. */
2503 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2504 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2507 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
2509 else if (constp
&& bytes
<= 2 * MAX_MOVE_BYTES
)
2510 emit_insn (gen_movstrsi_internal (change_address (orig_dest
, BLKmode
,
2512 change_address (orig_src
, BLKmode
,
2514 bytes_rtx
, align_rtx
));
2516 else if (constp
&& align
>= UNITS_PER_WORD
&& optimize
)
2517 block_move_loop (dest_reg
, src_reg
, bytes
, align
, orig_dest
, orig_src
);
2519 else if (constp
&& optimize
)
2521 /* If the alignment is not word aligned, generate a test at
2522 runtime, to see whether things wound up aligned, and we
2523 can use the faster lw/sw instead ulw/usw. */
2525 rtx temp
= gen_reg_rtx (Pmode
);
2526 rtx aligned_label
= gen_label_rtx ();
2527 rtx join_label
= gen_label_rtx ();
2528 int leftover
= bytes
% MAX_MOVE_BYTES
;
2534 emit_insn (gen_iordi3 (temp
, src_reg
, dest_reg
));
2535 emit_insn (gen_anddi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
- 1)));
2536 emit_insn (gen_cmpdi (temp
, const0_rtx
));
2540 emit_insn (gen_iorsi3 (temp
, src_reg
, dest_reg
));
2541 emit_insn (gen_andsi3 (temp
, temp
, GEN_INT (UNITS_PER_WORD
- 1)));
2542 emit_insn (gen_cmpsi (temp
, const0_rtx
));
2545 emit_jump_insn (gen_beq (aligned_label
));
2547 /* Unaligned loop. */
2548 block_move_loop (dest_reg
, src_reg
, bytes
, 1, orig_dest
, orig_src
);
2549 emit_jump_insn (gen_jump (join_label
));
2553 emit_label (aligned_label
);
2554 block_move_loop (dest_reg
, src_reg
, bytes
, UNITS_PER_WORD
, orig_dest
,
2556 emit_label (join_label
);
2558 /* Bytes at the end of the loop. */
2560 emit_insn (gen_movstrsi_internal (change_address (orig_dest
, BLKmode
,
2562 change_address (orig_src
, BLKmode
,
2569 block_move_call (dest_reg
, src_reg
, bytes_rtx
);
2572 /* Emit load/stores for a small constant block_move.
2574 operands[0] is the memory address of the destination.
2575 operands[1] is the memory address of the source.
2576 operands[2] is the number of bytes to move.
2577 operands[3] is the alignment.
2578 operands[4] is a temp register.
2579 operands[5] is a temp register.
2581 operands[3+num_regs] is the last temp register.
2583 The block move type can be one of the following:
2584 BLOCK_MOVE_NORMAL Do all of the block move.
2585 BLOCK_MOVE_NOT_LAST Do all but the last store.
2586 BLOCK_MOVE_LAST Do just the last store. */
2589 output_block_move (insn
, operands
, num_regs
, move_type
)
2593 enum block_move_type move_type
;
2595 rtx dest_reg
= XEXP (operands
[0], 0);
2596 rtx src_reg
= XEXP (operands
[1], 0);
2597 HOST_WIDE_INT bytes
= INTVAL (operands
[2]);
2598 int align
= INTVAL (operands
[3]);
2601 int use_lwl_lwr
= 0;
2602 int last_operand
= num_regs
+ 4;
2608 char *load
; /* load insn without nop */
2609 char *load_nop
; /* load insn with trailing nop */
2610 char *store
; /* store insn */
2611 char *final
; /* if last_store used: NULL or swr */
2612 char *last_store
; /* last store instruction */
2613 int offset
; /* current offset */
2614 enum machine_mode mode
; /* mode to use on (MEM) */
2617 /* ??? Detect a bug in GCC, where it can give us a register
2618 the same as one of the addressing registers and reduce
2619 the number of registers available. */
2622 && safe_regs
< (sizeof(xoperands
) / sizeof(xoperands
[0]));
2624 if (! reg_mentioned_p (operands
[i
], operands
[0])
2625 && ! reg_mentioned_p (operands
[i
], operands
[1]))
2626 xoperands
[safe_regs
++] = operands
[i
];
2628 if (safe_regs
< last_operand
)
2630 xoperands
[0] = operands
[0];
2631 xoperands
[1] = operands
[1];
2632 xoperands
[2] = operands
[2];
2633 xoperands
[3] = operands
[3];
2634 return output_block_move (insn
, xoperands
, safe_regs
- 4, move_type
);
2637 /* If we are given global or static addresses, and we would be
2638 emitting a few instructions, try to save time by using a
2639 temporary register for the pointer. */
2640 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
2641 an ldl/ldr instruction pair. We play it safe, and always move
2642 constant addresses into registers when generating N32/N64 code, just
2643 in case we might emit an unaligned load instruction. */
2644 if (num_regs
> 2 && (bytes
> 2 * align
|| move_type
!= BLOCK_MOVE_NORMAL
2645 || mips_abi
== ABI_N32
|| mips_abi
== ABI_64
))
2647 if (CONSTANT_P (src_reg
))
2650 mips_count_memory_refs (operands
[1], 1);
2652 src_reg
= operands
[3 + num_regs
--];
2653 if (move_type
!= BLOCK_MOVE_LAST
)
2655 xoperands
[1] = operands
[1];
2656 xoperands
[0] = src_reg
;
2657 if (Pmode
== DImode
)
2658 output_asm_insn ("dla\t%0,%1", xoperands
);
2660 output_asm_insn ("la\t%0,%1", xoperands
);
2664 if (CONSTANT_P (dest_reg
))
2667 mips_count_memory_refs (operands
[0], 1);
2669 dest_reg
= operands
[3 + num_regs
--];
2670 if (move_type
!= BLOCK_MOVE_LAST
)
2672 xoperands
[1] = operands
[0];
2673 xoperands
[0] = dest_reg
;
2674 if (Pmode
== DImode
)
2675 output_asm_insn ("dla\t%0,%1", xoperands
);
2677 output_asm_insn ("la\t%0,%1", xoperands
);
2682 /* ??? We really shouldn't get any LO_SUM addresses here, because they
2683 are not offsettable, however, offsettable_address_p says they are
2684 offsettable. I think this is a bug in offsettable_address_p.
2685 For expediency, we fix this by just loading the address into a register
2686 if we happen to get one. */
2688 if (GET_CODE (src_reg
) == LO_SUM
)
2690 src_reg
= operands
[3 + num_regs
--];
2691 if (move_type
!= BLOCK_MOVE_LAST
)
2693 xoperands
[2] = XEXP (XEXP (operands
[1], 0), 1);
2694 xoperands
[1] = XEXP (XEXP (operands
[1], 0), 0);
2695 xoperands
[0] = src_reg
;
2696 if (Pmode
== DImode
)
2697 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
2699 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
2703 if (GET_CODE (dest_reg
) == LO_SUM
)
2705 dest_reg
= operands
[3 + num_regs
--];
2706 if (move_type
!= BLOCK_MOVE_LAST
)
2708 xoperands
[2] = XEXP (XEXP (operands
[0], 0), 1);
2709 xoperands
[1] = XEXP (XEXP (operands
[0], 0), 0);
2710 xoperands
[0] = dest_reg
;
2711 if (Pmode
== DImode
)
2712 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands
);
2714 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands
);
2718 if (num_regs
> sizeof (load_store
) / sizeof (load_store
[0]))
2719 num_regs
= sizeof (load_store
) / sizeof (load_store
[0]);
2721 else if (num_regs
< 1)
2722 abort_with_insn (insn
,
2723 "Cannot do block move, not enough scratch registers");
2727 load_store
[num
].offset
= offset
;
2729 if (TARGET_64BIT
&& bytes
>= 8 && align
>= 8)
2731 load_store
[num
].load
= "ld\t%0,%1";
2732 load_store
[num
].load_nop
= "ld\t%0,%1%#";
2733 load_store
[num
].store
= "sd\t%0,%1";
2734 load_store
[num
].last_store
= "sd\t%0,%1";
2735 load_store
[num
].final
= 0;
2736 load_store
[num
].mode
= DImode
;
2741 else if (TARGET_64BIT
&& bytes
>= 8)
2743 if (BYTES_BIG_ENDIAN
)
2745 load_store
[num
].load
= "ldl\t%0,%1\n\tldr\t%0,%2";
2746 load_store
[num
].load_nop
= "ldl\t%0,%1\n\tldr\t%0,%2%#";
2747 load_store
[num
].store
= "sdl\t%0,%1\n\tsdr\t%0,%2";
2748 load_store
[num
].last_store
= "sdr\t%0,%2";
2749 load_store
[num
].final
= "sdl\t%0,%1";
2753 load_store
[num
].load
= "ldl\t%0,%2\n\tldr\t%0,%1";
2754 load_store
[num
].load_nop
= "ldl\t%0,%2\n\tldr\t%0,%1%#";
2755 load_store
[num
].store
= "sdl\t%0,%2\n\tsdr\t%0,%1";
2756 load_store
[num
].last_store
= "sdr\t%0,%1";
2757 load_store
[num
].final
= "sdl\t%0,%2";
2760 load_store
[num
].mode
= DImode
;
2766 else if (bytes
>= 4 && align
>= 4)
2768 load_store
[num
].load
= "lw\t%0,%1";
2769 load_store
[num
].load_nop
= "lw\t%0,%1%#";
2770 load_store
[num
].store
= "sw\t%0,%1";
2771 load_store
[num
].last_store
= "sw\t%0,%1";
2772 load_store
[num
].final
= 0;
2773 load_store
[num
].mode
= SImode
;
2778 else if (bytes
>= 4)
2780 if (BYTES_BIG_ENDIAN
)
2782 load_store
[num
].load
= "lwl\t%0,%1\n\tlwr\t%0,%2";
2783 load_store
[num
].load_nop
= "lwl\t%0,%1\n\tlwr\t%0,%2%#";
2784 load_store
[num
].store
= "swl\t%0,%1\n\tswr\t%0,%2";
2785 load_store
[num
].last_store
= "swr\t%0,%2";
2786 load_store
[num
].final
= "swl\t%0,%1";
2790 load_store
[num
].load
= "lwl\t%0,%2\n\tlwr\t%0,%1";
2791 load_store
[num
].load_nop
= "lwl\t%0,%2\n\tlwr\t%0,%1%#";
2792 load_store
[num
].store
= "swl\t%0,%2\n\tswr\t%0,%1";
2793 load_store
[num
].last_store
= "swr\t%0,%1";
2794 load_store
[num
].final
= "swl\t%0,%2";
2797 load_store
[num
].mode
= SImode
;
2803 else if (bytes
>= 2 && align
>= 2)
2805 load_store
[num
].load
= "lh\t%0,%1";
2806 load_store
[num
].load_nop
= "lh\t%0,%1%#";
2807 load_store
[num
].store
= "sh\t%0,%1";
2808 load_store
[num
].last_store
= "sh\t%0,%1";
2809 load_store
[num
].final
= 0;
2810 load_store
[num
].mode
= HImode
;
2816 load_store
[num
].load
= "lb\t%0,%1";
2817 load_store
[num
].load_nop
= "lb\t%0,%1%#";
2818 load_store
[num
].store
= "sb\t%0,%1";
2819 load_store
[num
].last_store
= "sb\t%0,%1";
2820 load_store
[num
].final
= 0;
2821 load_store
[num
].mode
= QImode
;
2826 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
2828 dslots_load_total
++;
2829 dslots_load_filled
++;
2831 if (CONSTANT_P (src_reg
))
2832 mips_count_memory_refs (src_reg
, 1);
2834 if (CONSTANT_P (dest_reg
))
2835 mips_count_memory_refs (dest_reg
, 1);
2838 /* Emit load/stores now if we have run out of registers or are
2839 at the end of the move. */
2841 if (++num
== num_regs
|| bytes
== 0)
2843 /* If only load/store, we need a NOP after the load. */
2846 load_store
[0].load
= load_store
[0].load_nop
;
2847 if (TARGET_STATS
&& move_type
!= BLOCK_MOVE_LAST
)
2848 dslots_load_filled
--;
2851 if (move_type
!= BLOCK_MOVE_LAST
)
2853 for (i
= 0; i
< num
; i
++)
2857 if (!operands
[i
+ 4])
2860 if (GET_MODE (operands
[i
+ 4]) != load_store
[i
].mode
)
2861 operands
[i
+ 4] = gen_rtx_REG (load_store
[i
].mode
,
2862 REGNO (operands
[i
+ 4]));
2864 offset
= load_store
[i
].offset
;
2865 xoperands
[0] = operands
[i
+ 4];
2866 xoperands
[1] = gen_rtx_MEM (load_store
[i
].mode
,
2867 plus_constant (src_reg
, offset
));
2872 = GET_MODE_SIZE (load_store
[i
].mode
) - 1;
2874 xoperands
[2] = gen_rtx_MEM (load_store
[i
].mode
,
2875 plus_constant (src_reg
,
2880 output_asm_insn (load_store
[i
].load
, xoperands
);
2884 for (i
= 0; i
< num
; i
++)
2886 int last_p
= (i
== num
-1 && bytes
== 0);
2887 int offset
= load_store
[i
].offset
;
2889 xoperands
[0] = operands
[i
+ 4];
2890 xoperands
[1] = gen_rtx_MEM (load_store
[i
].mode
,
2891 plus_constant (dest_reg
, offset
));
2896 int extra_offset
= GET_MODE_SIZE (load_store
[i
].mode
) - 1;
2897 xoperands
[2] = gen_rtx_MEM (load_store
[i
].mode
,
2898 plus_constant (dest_reg
,
2903 if (move_type
== BLOCK_MOVE_NORMAL
)
2904 output_asm_insn (load_store
[i
].store
, xoperands
);
2906 else if (move_type
== BLOCK_MOVE_NOT_LAST
)
2909 output_asm_insn (load_store
[i
].store
, xoperands
);
2911 else if (load_store
[i
].final
!= 0)
2912 output_asm_insn (load_store
[i
].final
, xoperands
);
2916 output_asm_insn (load_store
[i
].last_store
, xoperands
);
2919 num
= 0; /* reset load_store */
2927 /* Argument support functions. */
2929 /* Initialize CUMULATIVE_ARGS for a function. */
2932 init_cumulative_args (cum
, fntype
, libname
)
2933 CUMULATIVE_ARGS
*cum
; /* argument info to initialize */
2934 tree fntype
; /* tree ptr for function decl */
2935 rtx libname
; /* SYMBOL_REF of library name or 0 */
2937 static CUMULATIVE_ARGS zero_cum
;
2938 tree param
, next_param
;
2940 if (TARGET_DEBUG_E_MODE
)
2943 "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype
);
2946 fputc ('\n', stderr
);
2950 tree ret_type
= TREE_TYPE (fntype
);
2951 fprintf (stderr
, ", fntype code = %s, ret code = %s\n",
2952 tree_code_name
[(int)TREE_CODE (fntype
)],
2953 tree_code_name
[(int)TREE_CODE (ret_type
)]);
2959 /* Determine if this function has variable arguments. This is
2960 indicated by the last argument being 'void_type_mode' if there
2961 are no variable arguments. The standard MIPS calling sequence
2962 passes all arguments in the general purpose registers in this case. */
2964 for (param
= fntype
? TYPE_ARG_TYPES (fntype
) : 0;
2965 param
!= 0; param
= next_param
)
2967 next_param
= TREE_CHAIN (param
);
2968 if (next_param
== 0 && TREE_VALUE (param
) != void_type_node
)
2969 cum
->gp_reg_found
= 1;
2973 /* Advance the argument to the next argument position. */
2976 function_arg_advance (cum
, mode
, type
, named
)
2977 CUMULATIVE_ARGS
*cum
; /* current arg information */
2978 enum machine_mode mode
; /* current arg mode */
2979 tree type
; /* type of the argument or 0 if lib support */
2980 int named
; /* whether or not the argument was named */
2982 if (TARGET_DEBUG_E_MODE
)
2984 "function_adv({gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d )\n\n",
2985 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
,
2986 GET_MODE_NAME (mode
), type
, named
);
2995 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
2996 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
2999 cum
->gp_reg_found
= 1;
3000 cum
->arg_words
+= ((GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1)
3005 cum
->gp_reg_found
= 1;
3006 cum
->arg_words
+= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
3011 if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
)
3012 cum
->fp_arg_words
++;
3018 if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
&& ! TARGET_SINGLE_FLOAT
)
3019 cum
->fp_arg_words
+= (TARGET_64BIT
? 1 : 2);
3021 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
3025 cum
->gp_reg_found
= 1;
3026 cum
->arg_words
+= (TARGET_64BIT
? 1 : 2);
3032 cum
->gp_reg_found
= 1;
3038 /* Return an RTL expression containing the register for the given mode,
3039 or 0 if the argument is to be passed on the stack. */
3042 function_arg (cum
, mode
, type
, named
)
3043 CUMULATIVE_ARGS
*cum
; /* current arg information */
3044 enum machine_mode mode
; /* current arg mode */
3045 tree type
; /* type of the argument or 0 if lib support */
3046 int named
; /* != 0 for normal args, == 0 for ... args */
3051 int *arg_words
= &cum
->arg_words
;
3052 int struct_p
= (type
!= 0
3053 && (TREE_CODE (type
) == RECORD_TYPE
3054 || TREE_CODE (type
) == UNION_TYPE
3055 || TREE_CODE (type
) == QUAL_UNION_TYPE
));
3057 if (TARGET_DEBUG_E_MODE
)
3059 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d ) = ",
3060 cum
->gp_reg_found
, cum
->arg_number
, cum
->arg_words
,
3061 GET_MODE_NAME (mode
), type
, named
);
3063 cum
->last_arg_fp
= 0;
3067 if (mips_abi
== ABI_32
)
3069 if (cum
->gp_reg_found
|| cum
->arg_number
>= 2 || TARGET_SOFT_FLOAT
)
3070 regbase
= GP_ARG_FIRST
;
3073 regbase
= FP_ARG_FIRST
;
3075 /* If the first arg was a float in a floating point register,
3076 then set bias to align this float arg properly. */
3077 if (cum
->arg_words
== 1)
3081 else if (mips_abi
== ABI_EABI
&& ! TARGET_SOFT_FLOAT
)
3084 cum
->fp_arg_words
+= cum
->fp_arg_words
& 1;
3085 cum
->last_arg_fp
= 1;
3086 arg_words
= &cum
->fp_arg_words
;
3087 regbase
= FP_ARG_FIRST
;
3090 regbase
= (TARGET_SOFT_FLOAT
|| ! named
? GP_ARG_FIRST
: FP_ARG_FIRST
);
3096 if (mips_abi
== ABI_EABI
3097 && ! TARGET_SOFT_FLOAT
&& ! TARGET_SINGLE_FLOAT
)
3098 cum
->fp_arg_words
+= cum
->fp_arg_words
& 1;
3100 cum
->arg_words
+= cum
->arg_words
& 1;
3103 if (mips_abi
== ABI_32
)
3104 regbase
= ((cum
->gp_reg_found
3105 || TARGET_SOFT_FLOAT
|| TARGET_SINGLE_FLOAT
3106 || cum
->arg_number
>= 2)
3107 ? GP_ARG_FIRST
: FP_ARG_FIRST
);
3108 else if (mips_abi
== ABI_EABI
3109 && ! TARGET_SOFT_FLOAT
&& ! TARGET_SINGLE_FLOAT
)
3111 cum
->last_arg_fp
= 1;
3112 arg_words
= &cum
->fp_arg_words
;
3113 regbase
= FP_ARG_FIRST
;
3116 regbase
= (TARGET_SOFT_FLOAT
|| TARGET_SINGLE_FLOAT
|| ! named
3117 ? GP_ARG_FIRST
: FP_ARG_FIRST
);
3121 if (GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3122 && GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3125 /* Drops through. */
3127 if (type
!= (tree
)0 && TYPE_ALIGN (type
) > BITS_PER_WORD
3128 && ! TARGET_64BIT
&& mips_abi
!= ABI_EABI
)
3129 cum
->arg_words
+= (cum
->arg_words
& 1);
3130 regbase
= GP_ARG_FIRST
;
3137 regbase
= GP_ARG_FIRST
;
3142 cum
->arg_words
+= (cum
->arg_words
& 1);
3143 regbase
= GP_ARG_FIRST
;
3146 if (*arg_words
>= MAX_ARGS_IN_REGISTERS
)
3148 if (TARGET_DEBUG_E_MODE
)
3149 fprintf (stderr
, "<stack>%s\n", struct_p
? ", [struct]" : "");
3158 if (! type
|| TREE_CODE (type
) != RECORD_TYPE
|| mips_abi
== ABI_32
3159 || mips_abi
== ABI_EABI
|| ! named
)
3160 ret
= gen_rtx_REG (mode
, regbase
+ *arg_words
+ bias
);
3163 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3164 structure contains a double in its entirety, then that 64 bit
3165 chunk is passed in a floating point register. */
3168 /* First check to see if there is any such field. */
3169 for (field
= TYPE_FIELDS (type
); field
; field
= TREE_CHAIN (field
))
3170 if (TREE_CODE (field
) == FIELD_DECL
3171 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3172 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
3173 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
))
3174 % BITS_PER_WORD
== 0))
3177 /* If the whole struct fits a DFmode register,
3178 we don't need the PARALLEL. */
3179 if (! field
|| mode
== DFmode
)
3180 ret
= gen_rtx_REG (mode
, regbase
+ *arg_words
+ bias
);
3183 /* Now handle the special case by returning a PARALLEL
3184 indicating where each 64 bit chunk goes. */
3190 /* ??? If this is a packed structure, then the last hunk won't
3193 chunks
= TREE_INT_CST_LOW (TYPE_SIZE (type
)) / BITS_PER_WORD
;
3194 if (chunks
+ *arg_words
+ bias
> MAX_ARGS_IN_REGISTERS
)
3195 chunks
= MAX_ARGS_IN_REGISTERS
- *arg_words
- bias
;
3197 /* assign_parms checks the mode of ENTRY_PARM, so we must
3198 use the actual mode here. */
3199 ret
= gen_rtx_PARALLEL (mode
, rtvec_alloc (chunks
));
3202 regno
= regbase
+ *arg_words
+ bias
;
3203 field
= TYPE_FIELDS (type
);
3204 for (i
= 0; i
< chunks
; i
++)
3208 for (; field
; field
= TREE_CHAIN (field
))
3209 if (TREE_CODE (field
) == FIELD_DECL
3210 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
))
3215 && TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field
)) == bitpos
3216 && TREE_CODE (TREE_TYPE (field
)) == REAL_TYPE
3217 && TYPE_PRECISION (TREE_TYPE (field
)) == BITS_PER_WORD
)
3218 reg
= gen_rtx_REG (DFmode
,
3219 regno
+ FP_ARG_FIRST
- GP_ARG_FIRST
);
3221 reg
= gen_rtx_REG (word_mode
, regno
);
3224 = gen_rtx_EXPR_LIST (VOIDmode
, reg
,
3225 GEN_INT (bitpos
/ BITS_PER_UNIT
));
3233 if (TARGET_DEBUG_E_MODE
)
3234 fprintf (stderr
, "%s%s\n", reg_names
[regbase
+ *arg_words
+ bias
],
3235 struct_p
? ", [struct]" : "");
3237 /* The following is a hack in order to pass 1 byte structures
3238 the same way that the MIPS compiler does (namely by passing
3239 the structure in the high byte or half word of the register).
3240 This also makes varargs work. If we have such a structure,
3241 we save the adjustment RTL, and the call define expands will
3242 emit them. For the VOIDmode argument (argument after the
3243 last real argument), pass back a parallel vector holding each
3244 of the adjustments. */
3246 /* ??? function_arg can be called more than once for each argument.
3247 As a result, we compute more adjustments than we need here.
3248 See the CUMULATIVE_ARGS definition in mips.h. */
3250 /* ??? This scheme requires everything smaller than the word size to
3251 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
3252 that would mean every int needs to be shifted left, which is very
3253 inefficient. Let's not carry this compatibility to the 64 bit
3254 calling convention for now. */
3256 if (struct_p
&& int_size_in_bytes (type
) < UNITS_PER_WORD
3257 && ! TARGET_64BIT
&& mips_abi
!= ABI_EABI
)
3259 rtx amount
= GEN_INT (BITS_PER_WORD
3260 - int_size_in_bytes (type
) * BITS_PER_UNIT
);
3261 rtx reg
= gen_rtx_REG (word_mode
, regbase
+ *arg_words
+ bias
);
3264 cum
->adjust
[cum
->num_adjusts
++] = gen_ashldi3 (reg
, reg
, amount
);
3266 cum
->adjust
[cum
->num_adjusts
++] = gen_ashlsi3 (reg
, reg
, amount
);
3270 if (mode
== VOIDmode
&& cum
->num_adjusts
> 0)
3271 ret
= gen_rtx_PARALLEL (VOIDmode
,
3272 gen_rtvec_v (cum
->num_adjusts
, cum
->adjust
));
3278 function_arg_partial_nregs (cum
, mode
, type
, named
)
3279 CUMULATIVE_ARGS
*cum
; /* current arg information */
3280 enum machine_mode mode
; /* current arg mode */
3281 tree type
; /* type of the argument or 0 if lib support */
3282 int named
; /* != 0 for normal args, == 0 for ... args */
3284 if ((mode
== BLKmode
3285 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_INT
3286 || GET_MODE_CLASS (mode
) != MODE_COMPLEX_FLOAT
)
3287 && cum
->arg_words
< MAX_ARGS_IN_REGISTERS
3288 && mips_abi
!= ABI_EABI
)
3291 if (mode
== BLKmode
)
3292 words
= ((int_size_in_bytes (type
) + UNITS_PER_WORD
- 1)
3295 words
= (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3297 if (words
+ cum
->arg_words
<= MAX_ARGS_IN_REGISTERS
)
3298 return 0; /* structure fits in registers */
3300 if (TARGET_DEBUG_E_MODE
)
3301 fprintf (stderr
, "function_arg_partial_nregs = %d\n",
3302 MAX_ARGS_IN_REGISTERS
- cum
->arg_words
);
3304 return MAX_ARGS_IN_REGISTERS
- cum
->arg_words
;
3307 else if (mode
== DImode
&& cum
->arg_words
== MAX_ARGS_IN_REGISTERS
-1
3308 && ! TARGET_64BIT
&& mips_abi
!= ABI_EABI
)
3310 if (TARGET_DEBUG_E_MODE
)
3311 fprintf (stderr
, "function_arg_partial_nregs = 1\n");
3319 /* Abort after printing out a specific insn. */
3322 abort_with_insn (insn
, reason
)
3331 /* Write a message to stderr (for use in macros expanded in files that do not
3332 include stdio.h). */
3338 fprintf (stderr
, s
, s1
, s2
);
3341 /* Set up the threshold for data to go into the small data area, instead
3342 of the normal data area, and detect any conflicts in the switches. */
3347 register int i
, start
;
3349 register enum machine_mode mode
;
3351 mips_section_threshold
= g_switch_set
? g_switch_value
: MIPS_DEFAULT_GVALUE
;
3353 if (mips_section_threshold
<= 0)
3354 target_flags
&= ~MASK_GPOPT
;
3356 target_flags
|= MASK_GPOPT
;
3358 /* Get the architectural level. */
3359 if (mips_isa_string
== 0)
3361 #ifdef MIPS_ISA_DEFAULT
3362 mips_isa
= MIPS_ISA_DEFAULT
;
3368 else if (isdigit (*mips_isa_string
))
3370 mips_isa
= atoi (mips_isa_string
);
3371 if (mips_isa
< 1 || mips_isa
> 4)
3373 error ("-mips%d not supported", mips_isa
);
3380 error ("bad value (%s) for -mips switch", mips_isa_string
);
3384 #ifdef MIPS_ABI_DEFAULT
3385 /* Get the ABI to use. Currently this code is only used for Irix 6. */
3386 if (mips_abi_string
== (char *) 0)
3387 mips_abi
= MIPS_ABI_DEFAULT
;
3388 else if (! strcmp (mips_abi_string
, "32")
3389 || ! strcmp (mips_abi_string
, "o32"))
3391 else if (! strcmp (mips_abi_string
, "n32"))
3393 else if (! strcmp (mips_abi_string
, "64")
3394 || ! strcmp (mips_abi_string
, "n64"))
3396 else if (! strcmp (mips_abi_string
, "eabi"))
3397 mips_abi
= ABI_EABI
;
3399 error ("bad value (%s) for -mabi= switch", mips_abi_string
);
3401 /* A specified ISA defaults the ABI if it was not specified. */
3402 if (mips_abi_string
== 0 && mips_isa_string
&& mips_abi
!= ABI_EABI
)
3410 /* A specified ABI defaults the ISA if it was not specified. */
3411 else if (mips_isa_string
== 0 && mips_abi_string
&& mips_abi
!= ABI_EABI
)
3413 if (mips_abi
== ABI_32
)
3415 else if (mips_abi
== ABI_N32
)
3421 /* If both ABI and ISA were specified, check for conflicts. */
3422 else if (mips_isa_string
&& mips_abi_string
)
3424 if ((mips_isa
<= 2 && (mips_abi
== ABI_N32
|| mips_abi
== ABI_64
))
3425 || (mips_isa
>= 3 && mips_abi
== ABI_32
))
3426 error ("-mabi=%s does not support -mips%d", mips_abi_string
, mips_isa
);
3429 /* Override TARGET_DEFAULT if necessary. */
3430 if (mips_abi
== ABI_32
)
3431 target_flags
&= ~ (MASK_FLOAT64
|MASK_64BIT
);
3433 /* In the EABI in 64 bit mode, longs and pointers are 64 bits. Likewise
3434 for the SGI Irix6 N64 ABI. */
3435 if ((mips_abi
== ABI_EABI
&& TARGET_64BIT
)
3436 || mips_abi
== ABI_64
)
3437 target_flags
|= MASK_LONG64
;
3439 /* ??? This doesn't work yet, so don't let people try to use it. */
3440 if (mips_abi
== ABI_32
)
3441 error ("The -mabi=32 support does not work yet.");
3444 if (mips_abi_string
)
3445 error ("This target does not support the -mabi switch.");
3448 #ifdef MIPS_CPU_STRING_DEFAULT
3449 /* ??? There is a minor inconsistency here. If the user specifies an ISA
3450 greater than that supported by the default processor, then the user gets
3451 an error. Normally, the compiler will just default to the base level cpu
3452 for the indicated isa. */
3453 if (mips_cpu_string
== 0)
3454 mips_cpu_string
= MIPS_CPU_STRING_DEFAULT
;
3457 /* Identify the processor type */
3458 if (mips_cpu_string
== 0
3459 || !strcmp (mips_cpu_string
, "default")
3460 || !strcmp (mips_cpu_string
, "DEFAULT"))
3465 mips_cpu_string
= "3000";
3466 mips_cpu
= PROCESSOR_R3000
;
3469 mips_cpu_string
= "6000";
3470 mips_cpu
= PROCESSOR_R6000
;
3473 mips_cpu_string
= "4000";
3474 mips_cpu
= PROCESSOR_R4000
;
3477 mips_cpu_string
= "8000";
3478 mips_cpu
= PROCESSOR_R8000
;
3485 char *p
= mips_cpu_string
;
3488 /* We need to cope with the various "vr" prefixes for the NEC 4300
3489 and 4100 processors. */
3490 if (*p
== 'v' || *p
== 'V')
3493 if (*p
== 'r' || *p
== 'R')
3496 /* Since there is no difference between a R2000 and R3000 in
3497 terms of the scheduler, we collapse them into just an R3000. */
3499 mips_cpu
= PROCESSOR_DEFAULT
;
3503 if (!strcmp (p
, "2000") || !strcmp (p
, "2k") || !strcmp (p
, "2K"))
3504 mips_cpu
= PROCESSOR_R3000
;
3508 if (!strcmp (p
, "3000") || !strcmp (p
, "3k") || !strcmp (p
, "3K"))
3509 mips_cpu
= PROCESSOR_R3000
;
3510 else if (!strcmp (p
, "3900"))
3511 mips_cpu
= PROCESSOR_R3900
;
3515 if (!strcmp (p
, "4000") || !strcmp (p
, "4k") || !strcmp (p
, "4K"))
3516 mips_cpu
= PROCESSOR_R4000
;
3517 /* The vr4100 is a non-FP ISA III processor with some extra
3519 else if (!strcmp (p
, "4100"))
3521 mips_cpu
= PROCESSOR_R4100
;
3522 target_flags
|= MASK_SOFT_FLOAT
;
3524 /* The vr4300 is a standard ISA III processor, but with a different
3526 else if (!strcmp (p
, "4300"))
3527 mips_cpu
= PROCESSOR_R4300
;
3528 /* The r4400 is exactly the same as the r4000 from the compiler's
3530 else if (!strcmp (p
, "4400"))
3531 mips_cpu
= PROCESSOR_R4000
;
3532 else if (!strcmp (p
, "4600"))
3533 mips_cpu
= PROCESSOR_R4600
;
3534 else if (!strcmp (p
, "4650"))
3535 mips_cpu
= PROCESSOR_R4650
;
3539 if (!strcmp (p
, "5000") || !strcmp (p
, "5k") || !strcmp (p
, "5K"))
3540 mips_cpu
= PROCESSOR_R5000
;
3544 if (!strcmp (p
, "6000") || !strcmp (p
, "6k") || !strcmp (p
, "6K"))
3545 mips_cpu
= PROCESSOR_R6000
;
3549 if (!strcmp (p
, "8000"))
3550 mips_cpu
= PROCESSOR_R8000
;
3554 if (!strcmp (p
, "orion"))
3555 mips_cpu
= PROCESSOR_R4600
;
3560 && mips_cpu
!= PROCESSOR_R4300
3561 && mips_cpu
!= PROCESSOR_R4100
3562 && mips_cpu
!= PROCESSOR_R5000
)
3563 mips_cpu
= PROCESSOR_DEFAULT
;
3565 if (mips_cpu
== PROCESSOR_DEFAULT
)
3567 error ("bad value (%s) for -mcpu= switch", mips_cpu_string
);
3568 mips_cpu_string
= "default";
3572 if ((mips_cpu
== PROCESSOR_R3000
&& mips_isa
> 1)
3573 || (mips_cpu
== PROCESSOR_R6000
&& mips_isa
> 2)
3574 || ((mips_cpu
== PROCESSOR_R4000
3575 || mips_cpu
== PROCESSOR_R4100
3576 || mips_cpu
== PROCESSOR_R4300
3577 || mips_cpu
== PROCESSOR_R4600
3578 || mips_cpu
== PROCESSOR_R4650
)
3580 error ("-mcpu=%s does not support -mips%d", mips_cpu_string
, mips_isa
);
3582 /* make sure sizes of ints/longs/etc. are ok */
3586 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit ints");
3588 else if (TARGET_LONG64
)
3589 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit longs");
3591 else if (TARGET_FLOAT64
)
3592 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
3594 else if (TARGET_64BIT
)
3595 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers");
3598 if (mips_abi
!= ABI_32
)
3599 flag_pcc_struct_return
= 0;
3601 /* Tell halfpic.c that we have half-pic code if we do. */
3602 if (TARGET_HALF_PIC
)
3605 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
3606 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
3607 /* ??? -non_shared turns off pic code generation, but this is not
3609 if (TARGET_ABICALLS
)
3611 mips_abicalls
= MIPS_ABICALLS_YES
;
3613 if (mips_section_threshold
> 0)
3614 warning ("-G is incompatible with PIC code which is the default");
3617 mips_abicalls
= MIPS_ABICALLS_NO
;
3619 /* -membedded-pic is a form of PIC code suitable for embedded
3620 systems. All calls are made using PC relative addressing, and
3621 all data is addressed using the $gp register. This requires gas,
3622 which does most of the work, and GNU ld, which automatically
3623 expands PC relative calls which are out of range into a longer
3624 instruction sequence. All gcc really does differently is
3625 generate a different sequence for a switch. */
3626 if (TARGET_EMBEDDED_PIC
)
3629 if (TARGET_ABICALLS
)
3630 warning ("-membedded-pic and -mabicalls are incompatible");
3633 warning ("-G and -membedded-pic are incompatible");
3635 /* Setting mips_section_threshold is not required, because gas
3636 will force everything to be GP addressable anyhow, but
3637 setting it will cause gcc to make better estimates of the
3638 number of instructions required to access a particular data
3640 mips_section_threshold
= 0x7fffffff;
3643 /* This optimization requires a linker that can support a R_MIPS_LO16
3644 relocation which is not immediately preceded by a R_MIPS_HI16 relocation.
3645 GNU ld has this support, but not all other MIPS linkers do, so we enable
3646 this optimization only if the user requests it, or if GNU ld is the
3647 standard linker for this configuration. */
3648 /* ??? This does not work when target addresses are DImode.
3649 This is because we are missing DImode high/lo_sum patterns. */
3650 if (TARGET_GAS
&& TARGET_SPLIT_ADDRESSES
&& optimize
&& ! flag_pic
3652 mips_split_addresses
= 1;
3654 mips_split_addresses
= 0;
3656 /* -mrnames says to use the MIPS software convention for register
3657 names instead of the hardware names (ie, $a0 instead of $4).
3658 We do this by switching the names in mips_reg_names, which the
3659 reg_names points into via the REGISTER_NAMES macro. */
3661 if (TARGET_NAME_REGS
)
3662 bcopy ((char *) mips_sw_reg_names
, (char *) mips_reg_names
,
3663 sizeof (mips_reg_names
));
3665 /* Initialize the high and low values for legitimate floating point
3666 constants. Rather than trying to get the accuracy down to the
3667 last bit, just use approximate ranges. */
3668 dfhigh
= REAL_VALUE_ATOF ("1.0e300", DFmode
);
3669 dflow
= REAL_VALUE_ATOF ("1.0e-300", DFmode
);
3670 sfhigh
= REAL_VALUE_ATOF ("1.0e38", SFmode
);
3671 sflow
= REAL_VALUE_ATOF ("1.0e-38", SFmode
);
3673 mips_print_operand_punct
['?'] = 1;
3674 mips_print_operand_punct
['#'] = 1;
3675 mips_print_operand_punct
['&'] = 1;
3676 mips_print_operand_punct
['!'] = 1;
3677 mips_print_operand_punct
['*'] = 1;
3678 mips_print_operand_punct
['@'] = 1;
3679 mips_print_operand_punct
['.'] = 1;
3680 mips_print_operand_punct
['('] = 1;
3681 mips_print_operand_punct
[')'] = 1;
3682 mips_print_operand_punct
['['] = 1;
3683 mips_print_operand_punct
[']'] = 1;
3684 mips_print_operand_punct
['<'] = 1;
3685 mips_print_operand_punct
['>'] = 1;
3686 mips_print_operand_punct
['{'] = 1;
3687 mips_print_operand_punct
['}'] = 1;
3688 mips_print_operand_punct
['^'] = 1;
3690 mips_char_to_class
['d'] = GR_REGS
;
3691 mips_char_to_class
['f'] = TARGET_HARD_FLOAT
? FP_REGS
: NO_REGS
;
3692 mips_char_to_class
['h'] = HI_REG
;
3693 mips_char_to_class
['l'] = LO_REG
;
3694 mips_char_to_class
['a'] = HILO_REG
;
3695 mips_char_to_class
['x'] = MD_REGS
;
3696 mips_char_to_class
['b'] = ALL_REGS
;
3697 mips_char_to_class
['y'] = GR_REGS
;
3698 mips_char_to_class
['z'] = ST_REGS
;
3700 /* Set up array to map GCC register number to debug register number.
3701 Ignore the special purpose register numbers. */
3703 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
3704 mips_dbx_regno
[i
] = -1;
3706 start
= GP_DBX_FIRST
- GP_REG_FIRST
;
3707 for (i
= GP_REG_FIRST
; i
<= GP_REG_LAST
; i
++)
3708 mips_dbx_regno
[i
] = i
+ start
;
3710 start
= FP_DBX_FIRST
- FP_REG_FIRST
;
3711 for (i
= FP_REG_FIRST
; i
<= FP_REG_LAST
; i
++)
3712 mips_dbx_regno
[i
] = i
+ start
;
3714 /* Set up array giving whether a given register can hold a given mode.
3715 At present, restrict ints from being in FP registers, because reload
3716 is a little enthusiastic about storing extra values in FP registers,
3717 and this is not good for things like OS kernels. Also, due to the
3718 mandatory delay, it is as fast to load from cached memory as to move
3719 from the FP register. */
3721 for (mode
= VOIDmode
;
3722 mode
!= MAX_MACHINE_MODE
;
3723 mode
= (enum machine_mode
) ((int)mode
+ 1))
3725 register int size
= GET_MODE_SIZE (mode
);
3726 register enum mode_class
class = GET_MODE_CLASS (mode
);
3728 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
3735 temp
= (regno
== FPSW_REGNUM
);
3737 temp
= (ST_REG_P (regno
) || GP_REG_P (regno
)
3738 || FP_REG_P (regno
));
3741 else if (GP_REG_P (regno
))
3742 temp
= ((regno
& 1) == 0 || size
<= UNITS_PER_WORD
);
3744 else if (FP_REG_P (regno
))
3745 temp
= ((TARGET_FLOAT64
|| ((regno
& 1) == 0))
3746 && (class == MODE_FLOAT
3747 || class == MODE_COMPLEX_FLOAT
3748 || (TARGET_DEBUG_H_MODE
&& class == MODE_INT
))
3749 && (! TARGET_SINGLE_FLOAT
|| size
<= 4));
3751 else if (MD_REG_P (regno
))
3752 temp
= (class == MODE_INT
3753 && (size
<= UNITS_PER_WORD
3754 || (regno
== MD_REG_FIRST
3755 && size
== 2 * UNITS_PER_WORD
)));
3760 mips_hard_regno_mode_ok
[(int)mode
][regno
] = temp
;
3765 /* The MIPS debug format wants all automatic variables and arguments
3766 to be in terms of the virtual frame pointer (stack pointer before
3767 any adjustment in the function), while the MIPS 3.0 linker wants
3768 the frame pointer to be the stack pointer after the initial
3769 adjustment. So, we do the adjustment here. The arg pointer (which
3770 is eliminated) points to the virtual frame pointer, while the frame
3771 pointer (which may be eliminated) points to the stack pointer after
3772 the initial adjustments. */
3775 mips_debugger_offset (addr
, offset
)
3777 HOST_WIDE_INT offset
;
3779 rtx offset2
= const0_rtx
;
3780 rtx reg
= eliminate_constant_term (addr
, &offset2
);
3783 offset
= INTVAL (offset2
);
3785 if (reg
== stack_pointer_rtx
|| reg
== frame_pointer_rtx
)
3787 HOST_WIDE_INT frame_size
= (!current_frame_info
.initialized
3788 ? compute_frame_size (get_frame_size ())
3789 : current_frame_info
.total_size
);
3791 offset
= offset
- frame_size
;
3794 /* sdbout_parms does not want this to crash for unrecognized cases. */
3796 else if (reg
!= arg_pointer_rtx
)
3797 abort_with_insn (addr
, "mips_debugger_offset called with non stack/frame/arg pointer.");
3803 /* A C compound statement to output to stdio stream STREAM the
3804 assembler syntax for an instruction operand X. X is an RTL
3807 CODE is a value that can be used to specify one of several ways
3808 of printing the operand. It is used when identical operands
3809 must be printed differently depending on the context. CODE
3810 comes from the `%' specification that was used to request
3811 printing of the operand. If the specification was just `%DIGIT'
3812 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
3813 is the ASCII code for LTR.
3815 If X is a register, this macro should print the register's name.
3816 The names can be found in an array `reg_names' whose type is
3817 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
3819 When the machine description has a specification `%PUNCT' (a `%'
3820 followed by a punctuation character), this macro is called with
3821 a null pointer for X and the punctuation character for CODE.
3823 The MIPS specific codes are:
3825 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
3826 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
3827 'd' output integer constant in decimal,
3828 'z' if the operand is 0, use $0 instead of normal operand.
3829 'D' print second register of double-word register operand.
3830 'L' print low-order register of double-word register operand.
3831 'M' print high-order register of double-word register operand.
3832 'C' print part of opcode for a branch condition.
3833 'N' print part of opcode for a branch condition, inverted.
3834 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
3835 'B' print 'z' for EQ, 'n' for NE
3836 'b' print 'n' for EQ, 'z' for NE
3837 'T' print 'f' for EQ, 't' for NE
3838 't' print 't' for EQ, 'f' for NE
3839 'Z' print register and a comma, but print nothing for $fcc0
3840 '(' Turn on .set noreorder
3841 ')' Turn on .set reorder
3842 '[' Turn on .set noat
3844 '<' Turn on .set nomacro
3845 '>' Turn on .set macro
3846 '{' Turn on .set volatile (not GAS)
3847 '}' Turn on .set novolatile (not GAS)
3848 '&' Turn on .set noreorder if filling delay slots
3849 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
3850 '!' Turn on .set nomacro if filling delay slots
3851 '#' Print nop if in a .set noreorder section.
3852 '?' Print 'l' if we are to use a branch likely instead of normal branch.
3853 '@' Print the name of the assembler temporary register (at or $1).
3854 '.' Print the name of the register with a hard-wired zero (zero or $0).
3855 '^' Print the name of the pic call-through register (t9 or $25). */
3858 print_operand (file
, op
, letter
)
3859 FILE *file
; /* file to write to */
3860 rtx op
; /* operand to print */
3861 int letter
; /* %<letter> or 0 */
3863 register enum rtx_code code
;
3865 if (PRINT_OPERAND_PUNCT_VALID_P (letter
))
3870 if (mips_branch_likely
)
3875 fputs (reg_names
[GP_REG_FIRST
+ 1], file
);
3879 fputs (reg_names
[PIC_FUNCTION_ADDR_REGNUM
], file
);
3883 fputs (reg_names
[GP_REG_FIRST
+ 0], file
);
3887 if (final_sequence
!= 0 && set_noreorder
++ == 0)
3888 fputs (".set\tnoreorder\n\t", file
);
3892 if (final_sequence
!= 0)
3894 if (set_noreorder
++ == 0)
3895 fputs (".set\tnoreorder\n\t", file
);
3897 if (set_nomacro
++ == 0)
3898 fputs (".set\tnomacro\n\t", file
);
3903 if (final_sequence
!= 0 && set_nomacro
++ == 0)
3904 fputs ("\n\t.set\tnomacro", file
);
3908 if (set_noreorder
!= 0)
3909 fputs ("\n\tnop", file
);
3910 else if (TARGET_STATS
)
3911 fputs ("\n\t#nop", file
);
3916 if (set_noreorder
++ == 0)
3917 fputs (".set\tnoreorder\n\t", file
);
3921 if (set_noreorder
== 0)
3922 error ("internal error: %%) found without a %%( in assembler pattern");
3924 else if (--set_noreorder
== 0)
3925 fputs ("\n\t.set\treorder", file
);
3930 if (set_noat
++ == 0)
3931 fputs (".set\tnoat\n\t", file
);
3936 error ("internal error: %%] found without a %%[ in assembler pattern");
3937 else if (--set_noat
== 0)
3938 fputs ("\n\t.set\tat", file
);
3943 if (set_nomacro
++ == 0)
3944 fputs (".set\tnomacro\n\t", file
);
3948 if (set_nomacro
== 0)
3949 error ("internal error: %%> found without a %%< in assembler pattern");
3950 else if (--set_nomacro
== 0)
3951 fputs ("\n\t.set\tmacro", file
);
3956 if (set_volatile
++ == 0)
3957 fprintf (file
, "%s.set\tvolatile\n\t", TARGET_MIPS_AS
? "" : "#");
3961 if (set_volatile
== 0)
3962 error ("internal error: %%} found without a %%{ in assembler pattern");
3963 else if (--set_volatile
== 0)
3964 fprintf (file
, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS
) ? "" : "#");
3969 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter
);
3976 code
= GET_CODE (op
);
3978 if (code
== SIGN_EXTEND
)
3979 op
= XEXP (op
, 0), code
= GET_CODE (op
);
3984 case EQ
: fputs ("eq", file
); break;
3985 case NE
: fputs ("ne", file
); break;
3986 case GT
: fputs ("gt", file
); break;
3987 case GE
: fputs ("ge", file
); break;
3988 case LT
: fputs ("lt", file
); break;
3989 case LE
: fputs ("le", file
); break;
3990 case GTU
: fputs ("gtu", file
); break;
3991 case GEU
: fputs ("geu", file
); break;
3992 case LTU
: fputs ("ltu", file
); break;
3993 case LEU
: fputs ("leu", file
); break;
3995 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%C");
3998 else if (letter
== 'N')
4001 case EQ
: fputs ("ne", file
); break;
4002 case NE
: fputs ("eq", file
); break;
4003 case GT
: fputs ("le", file
); break;
4004 case GE
: fputs ("lt", file
); break;
4005 case LT
: fputs ("ge", file
); break;
4006 case LE
: fputs ("gt", file
); break;
4007 case GTU
: fputs ("leu", file
); break;
4008 case GEU
: fputs ("ltu", file
); break;
4009 case LTU
: fputs ("geu", file
); break;
4010 case LEU
: fputs ("gtu", file
); break;
4012 abort_with_insn (op
, "PRINT_OPERAND, invalid insn for %%N");
4015 else if (letter
== 'S')
4019 ASM_GENERATE_INTERNAL_LABEL (buffer
, "LS", CODE_LABEL_NUMBER (op
));
4020 assemble_name (file
, buffer
);
4023 else if (letter
== 'Z')
4025 register int regnum
;
4030 regnum
= REGNO (op
);
4031 if (! ST_REG_P (regnum
))
4034 if (regnum
!= ST_REG_FIRST
)
4035 fprintf (file
, "%s,", reg_names
[regnum
]);
4038 else if (code
== REG
|| code
== SUBREG
)
4040 register int regnum
;
4043 regnum
= REGNO (op
);
4045 regnum
= true_regnum (op
);
4047 if ((letter
== 'M' && ! WORDS_BIG_ENDIAN
)
4048 || (letter
== 'L' && WORDS_BIG_ENDIAN
)
4052 fprintf (file
, "%s", reg_names
[regnum
]);
4055 else if (code
== MEM
)
4056 output_address (XEXP (op
, 0));
4058 else if (code
== CONST_DOUBLE
4059 && GET_MODE_CLASS (GET_MODE (op
)) == MODE_FLOAT
)
4064 REAL_VALUE_FROM_CONST_DOUBLE (d
, op
);
4065 REAL_VALUE_TO_DECIMAL (d
, "%.20e", s
);
4069 else if (letter
== 'x' && GET_CODE (op
) == CONST_INT
)
4070 fprintf (file
, "0x%04x", 0xffff & INTVAL(op
));
4072 else if (letter
== 'X' && GET_CODE(op
) == CONST_INT
)
4073 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (op
));
4075 else if (letter
== 'd' && GET_CODE(op
) == CONST_INT
)
4076 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
, (INTVAL(op
)));
4078 else if (letter
== 'z' && GET_CODE (op
) == CONST_INT
&& INTVAL (op
) == 0)
4079 fputs (reg_names
[GP_REG_FIRST
], file
);
4081 else if (letter
== 'd' || letter
== 'x' || letter
== 'X')
4082 fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT",
4085 else if (letter
== 'B')
4086 fputs (code
== EQ
? "z" : "n", file
);
4087 else if (letter
== 'b')
4088 fputs (code
== EQ
? "n" : "z", file
);
4089 else if (letter
== 'T')
4090 fputs (code
== EQ
? "f" : "t", file
);
4091 else if (letter
== 't')
4092 fputs (code
== EQ
? "t" : "f", file
);
4095 output_addr_const (file
, op
);
4098 /* A C compound statement to output to stdio stream STREAM the
4099 assembler syntax for an instruction operand that is a memory
4100 reference whose address is ADDR. ADDR is an RTL expression.
4102 On some machines, the syntax for a symbolic address depends on
4103 the section that the address refers to. On these machines,
4104 define the macro `ENCODE_SECTION_INFO' to store the information
4105 into the `symbol_ref', and then check for it here. */
4108 print_operand_address (file
, addr
)
4112 switch (GET_CODE (addr
))
4115 if (REGNO (addr
) == ARG_POINTER_REGNUM
)
4116 abort_with_insn (addr
, "Arg pointer not eliminated.");
4118 fprintf (file
, "0(%s)", reg_names
[REGNO (addr
)]);
4123 register rtx arg0
= XEXP (addr
, 0);
4124 register rtx arg1
= XEXP (addr
, 1);
4126 if (! mips_split_addresses
)
4127 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
4129 if (GET_CODE (arg0
) != REG
)
4130 abort_with_insn (addr
,
4131 "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
4133 fprintf (file
, "%%lo(");
4134 print_operand_address (file
, arg1
);
4135 fprintf (file
, ")(%s)", reg_names
[REGNO (arg0
)]);
4141 register rtx reg
= 0;
4142 register rtx offset
= 0;
4143 register rtx arg0
= XEXP (addr
, 0);
4144 register rtx arg1
= XEXP (addr
, 1);
4146 if (GET_CODE (arg0
) == REG
)
4150 if (GET_CODE (offset
) == REG
)
4151 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, 2 regs");
4154 else if (GET_CODE (arg1
) == REG
)
4155 reg
= arg1
, offset
= arg0
;
4156 else if (CONSTANT_P (arg0
) && CONSTANT_P (arg1
))
4158 output_addr_const (file
, addr
);
4162 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, no regs");
4164 if (! CONSTANT_P (offset
))
4165 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #2");
4167 if (REGNO (reg
) == ARG_POINTER_REGNUM
)
4168 abort_with_insn (addr
, "Arg pointer not eliminated.");
4170 output_addr_const (file
, offset
);
4171 fprintf (file
, "(%s)", reg_names
[REGNO (reg
)]);
4179 output_addr_const (file
, addr
);
4183 abort_with_insn (addr
, "PRINT_OPERAND_ADDRESS, invalid insn #1");
4188 /* If optimizing for the global pointer, keep track of all of the externs, so
4189 that at the end of the file, we can emit the appropriate .extern
4190 declaration for them, before writing out the text section. We assume all
4191 names passed to us are in the permanent obstack, so they will be valid at
4192 the end of the compilation.
4194 If we have -G 0, or the extern size is unknown, or the object is in a user
4195 specified section that is not .sbss/.sdata, don't bother emitting the
4196 .externs. In the case of user specified sections this behaviour is
4197 required as otherwise GAS will think the object lives in .sbss/.sdata. */
4200 mips_output_external (file
, decl
, name
)
4205 register struct extern_list
*p
;
4210 && TREE_CODE (decl
) != FUNCTION_DECL
4211 && (len
= int_size_in_bytes (TREE_TYPE (decl
))) > 0
4212 && ((section_name
= DECL_SECTION_NAME (decl
)) == NULL
4213 || strcmp (TREE_STRING_POINTER (section_name
), ".sbss") == 0
4214 || strcmp (TREE_STRING_POINTER (section_name
), ".sdata") == 0))
4216 p
= (struct extern_list
*) permalloc (sizeof (struct extern_list
));
4217 p
->next
= extern_head
;
4223 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4224 if (TREE_CODE (decl
) == FUNCTION_DECL
4225 /* ??? Don't include alloca, since gcc will always expand it
4226 inline. If we don't do this, the C++ library fails to build. */
4227 && strcmp (name
, "alloca")
4228 /* ??? Don't include __builtin_next_arg, because then gcc will not
4229 bootstrap under Irix 5.1. */
4230 && strcmp (name
, "__builtin_next_arg"))
4232 p
= (struct extern_list
*) permalloc (sizeof (struct extern_list
));
4233 p
->next
= extern_head
;
4243 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4245 mips_output_external_libcall (file
, name
)
4249 register struct extern_list
*p
;
4251 p
= (struct extern_list
*) permalloc (sizeof (struct extern_list
));
4252 p
->next
= extern_head
;
4261 /* Compute a string to use as a temporary file name. */
4263 /* On MSDOS, write temp files in current dir
4264 because there's no place else we can expect to use. */
4267 #define P_tmpdir "./"
4275 char *base
= getenv ("TMPDIR");
4281 if (access (P_tmpdir
, R_OK
| W_OK
) == 0)
4285 if (access ("/usr/tmp", R_OK
| W_OK
) == 0)
4291 len
= strlen (base
);
4292 /* temp_filename is global, so we must use malloc, not alloca. */
4293 temp_filename
= (char *) xmalloc (len
+ sizeof("/ctXXXXXX"));
4294 strcpy (temp_filename
, base
);
4295 if (len
> 0 && temp_filename
[len
-1] != '/')
4296 temp_filename
[len
++] = '/';
4298 strcpy (temp_filename
+ len
, "ctXXXXXX");
4299 mktemp (temp_filename
);
4301 stream
= fopen (temp_filename
, "w+");
4303 pfatal_with_name (temp_filename
);
4306 /* In MSDOS, we cannot unlink the temporary file until we are finished using
4307 it. Otherwise, we delete it now, so that it will be gone even if the
4308 compiler happens to crash. */
4309 unlink (temp_filename
);
4314 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
4315 for .file's that start within a function. If we are smuggling stabs, try to
4316 put out a MIPS ECOFF file and a stab. */
4319 mips_output_filename (stream
, name
)
4323 static int first_time
= 1;
4324 char ltext_label_name
[100];
4330 current_function_file
= name
;
4331 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
4332 /* This tells mips-tfile that stabs will follow. */
4333 if (!TARGET_GAS
&& write_symbols
== DBX_DEBUG
)
4334 fprintf (stream
, "\t#@stabs\n");
4337 else if (write_symbols
== DBX_DEBUG
)
4339 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name
, "Ltext", 0);
4340 fprintf (stream
, "%s ", ASM_STABS_OP
);
4341 output_quoted_string (stream
, name
);
4342 fprintf (stream
, ",%d,0,0,%s\n", N_SOL
, <ext_label_name
[1]);
4345 else if (name
!= current_function_file
4346 && strcmp (name
, current_function_file
) != 0)
4348 if (inside_function
&& !TARGET_GAS
)
4350 if (!file_in_function_warning
)
4352 file_in_function_warning
= 1;
4353 ignore_line_number
= 1;
4354 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
4360 current_function_file
= name
;
4361 ASM_OUTPUT_FILENAME (stream
, num_source_filenames
, name
);
4366 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
4367 as well as a .loc, since it is possible that MIPS ECOFF might not be
4368 able to represent the location for inlines that come from a different
4372 mips_output_lineno (stream
, line
)
4376 if (write_symbols
== DBX_DEBUG
)
4379 fprintf (stream
, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n",
4380 LOCAL_LABEL_PREFIX
, sym_lineno
, ASM_STABN_OP
, N_SLINE
, line
,
4381 LOCAL_LABEL_PREFIX
, sym_lineno
);
4386 fprintf (stream
, "\n\t%s.loc\t%d %d\n",
4387 (ignore_line_number
) ? "#" : "",
4388 num_source_filenames
, line
);
4390 LABEL_AFTER_LOC (stream
);
4394 /* If defined, a C statement to be executed just prior to the output of
4395 assembler code for INSN, to modify the extracted operands so they will be
4398 Here the argument OPVEC is the vector containing the operands extracted
4399 from INSN, and NOPERANDS is the number of elements of the vector which
4400 contain meaningful data for this insn. The contents of this vector are
4401 what will be used to convert the insn template into assembler code, so you
4402 can change the assembler output by changing the contents of the vector.
4404 We use it to check if the current insn needs a nop in front of it because
4405 of load delays, and also to update the delay slot statistics. */
4407 /* ??? There is no real need for this function, because it never actually
4408 emits a NOP anymore. */
4411 final_prescan_insn (insn
, opvec
, noperands
)
4416 if (dslots_number_nops
> 0)
4418 rtx pattern
= PATTERN (insn
);
4419 int length
= get_attr_length (insn
);
4421 /* Do we need to emit a NOP? */
4423 || (mips_load_reg
!= 0 && reg_mentioned_p (mips_load_reg
, pattern
))
4424 || (mips_load_reg2
!= 0 && reg_mentioned_p (mips_load_reg2
, pattern
))
4425 || (mips_load_reg3
!= 0 && reg_mentioned_p (mips_load_reg3
, pattern
))
4426 || (mips_load_reg4
!= 0
4427 && reg_mentioned_p (mips_load_reg4
, pattern
)))
4428 fputs ("\t#nop\n", asm_out_file
);
4431 dslots_load_filled
++;
4433 while (--dslots_number_nops
> 0)
4434 fputs ("\t#nop\n", asm_out_file
);
4443 && (GET_CODE (insn
) == JUMP_INSN
|| GET_CODE (insn
) == CALL_INSN
))
4444 dslots_jump_total
++;
4447 /* Output at beginning of assembler file.
4449 If we are optimizing to use the global pointer, create a temporary file to
4450 hold all of the text stuff, and write it out to the end. This is needed
4451 because the MIPS assembler is evidently one pass, and if it hasn't seen the
4452 relevant .comm/.lcomm/.extern/.sdata declaration when the code is
4453 processed, it generates a two instruction sequence. */
4456 mips_asm_file_start (stream
)
4459 ASM_OUTPUT_SOURCE_FILENAME (stream
, main_input_filename
);
4461 /* Versions of the MIPS assembler before 2.20 generate errors if a branch
4462 inside of a .set noreorder section jumps to a label outside of the .set
4463 noreorder section. Revision 2.20 just set nobopt silently rather than
4466 if (TARGET_MIPS_AS
&& optimize
&& flag_delayed_branch
)
4467 fprintf (stream
, "\t.set\tnobopt\n");
4469 /* Generate the pseudo ops that System V.4 wants. */
4470 #ifndef ABICALLS_ASM_OP
4471 #define ABICALLS_ASM_OP ".abicalls"
4473 if (TARGET_ABICALLS
)
4474 /* ??? but do not want this (or want pic0) if -non-shared? */
4475 fprintf (stream
, "\t%s\n", ABICALLS_ASM_OP
);
4477 /* Start a section, so that the first .popsection directive is guaranteed
4478 to have a previously defined section to pop back to. */
4479 if (mips_abi
!= ABI_32
&& mips_abi
!= ABI_EABI
)
4480 fprintf (stream
, "\t.section\t.text\n");
4482 /* This code exists so that we can put all externs before all symbol
4483 references. This is necessary for the MIPS assembler's global pointer
4484 optimizations to work. */
4485 if (TARGET_FILE_SWITCHING
)
4487 asm_out_data_file
= stream
;
4488 asm_out_text_file
= make_temp_file ();
4492 asm_out_data_file
= asm_out_text_file
= stream
;
4494 if (flag_verbose_asm
)
4495 fprintf (stream
, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
4497 mips_section_threshold
, mips_cpu_string
, mips_isa
);
4500 /* If we are optimizing the global pointer, emit the text section now and any
4501 small externs which did not have .comm, etc that are needed. Also, give a
4502 warning if the data area is more than 32K and -pic because 3 instructions
4503 are needed to reference the data pointers. */
4506 mips_asm_file_end (file
)
4511 struct extern_list
*p
;
4515 HALF_PIC_FINISH (file
);
4521 for (p
= extern_head
; p
!= 0; p
= p
->next
)
4523 name_tree
= get_identifier (p
->name
);
4525 /* Positively ensure only one .extern for any given symbol. */
4526 if (! TREE_ASM_WRITTEN (name_tree
))
4528 TREE_ASM_WRITTEN (name_tree
) = 1;
4529 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
4531 ASM_OUTPUT_UNDEF_FUNCTION (file
, p
->name
);
4535 fputs ("\t.extern\t", file
);
4536 assemble_name (file
, p
->name
);
4537 fprintf (file
, ", %d\n", p
->size
);
4543 if (TARGET_FILE_SWITCHING
)
4545 fprintf (file
, "\n\t.text\n");
4546 rewind (asm_out_text_file
);
4547 if (ferror (asm_out_text_file
))
4548 fatal_io_error (temp_filename
);
4550 while ((len
= fread (buffer
, 1, sizeof (buffer
), asm_out_text_file
)) > 0)
4551 if (fwrite (buffer
, 1, len
, file
) != len
)
4552 pfatal_with_name (asm_file_name
);
4555 pfatal_with_name (temp_filename
);
4557 if (fclose (asm_out_text_file
) != 0)
4558 pfatal_with_name (temp_filename
);
4561 unlink (temp_filename
);
4566 /* Emit either a label, .comm, or .lcomm directive, and mark that the symbol
4567 is used, so that we don't emit an .extern for it in mips_asm_file_end. */
4570 mips_declare_object (stream
, name
, init_string
, final_string
, size
)
4577 fputs (init_string
, stream
); /* "", "\t.comm\t", or "\t.lcomm\t" */
4578 assemble_name (stream
, name
);
4579 fprintf (stream
, final_string
, size
); /* ":\n", ",%u\n", ",%u\n" */
4583 tree name_tree
= get_identifier (name
);
4584 TREE_ASM_WRITTEN (name_tree
) = 1;
4588 /* Output a double precision value to the assembler. If both the
4589 host and target are IEEE, emit the values in hex. */
4592 mips_output_double (stream
, value
)
4594 REAL_VALUE_TYPE value
;
4596 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
4598 REAL_VALUE_TO_TARGET_DOUBLE (value
, value_long
);
4600 fprintf (stream
, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
4601 value_long
[0], value
, value_long
[1]);
4603 fprintf (stream
, "\t.double\t%.20g\n", value
);
4607 /* Output a single precision value to the assembler. If both the
4608 host and target are IEEE, emit the values in hex. */
4611 mips_output_float (stream
, value
)
4613 REAL_VALUE_TYPE value
;
4615 #ifdef REAL_VALUE_TO_TARGET_SINGLE
4617 REAL_VALUE_TO_TARGET_SINGLE (value
, value_long
);
4619 fprintf (stream
, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long
, value
);
4621 fprintf (stream
, "\t.float\t%.12g\n", value
);
4625 /* Return the bytes needed to compute the frame pointer from the current
4628 Mips stack frames look like:
4630 Before call After call
4631 +-----------------------+ +-----------------------+
4634 | caller's temps. | | caller's temps. |
4636 +-----------------------+ +-----------------------+
4638 | arguments on stack. | | arguments on stack. |
4640 +-----------------------+ +-----------------------+
4641 | 4 words to save | | 4 words to save |
4642 | arguments passed | | arguments passed |
4643 | in registers, even | | in registers, even |
4644 SP->| if not passed. | VFP->| if not passed. |
4645 +-----------------------+ +-----------------------+
4647 | fp register save |
4649 +-----------------------+
4651 | gp register save |
4653 +-----------------------+
4657 +-----------------------+
4659 | alloca allocations |
4661 +-----------------------+
4663 | GP save for V.4 abi |
4665 +-----------------------+
4667 | arguments on stack |
4669 +-----------------------+
4671 | arguments passed |
4672 | in registers, even |
4673 low SP->| if not passed. |
4674 memory +-----------------------+
4679 compute_frame_size (size
)
4680 HOST_WIDE_INT size
; /* # of var. bytes allocated */
4683 HOST_WIDE_INT total_size
; /* # bytes that the entire frame takes up */
4684 HOST_WIDE_INT var_size
; /* # bytes that variables take up */
4685 HOST_WIDE_INT args_size
; /* # bytes that outgoing arguments take up */
4686 HOST_WIDE_INT extra_size
; /* # extra bytes */
4687 HOST_WIDE_INT gp_reg_rounded
; /* # bytes needed to store gp after rounding */
4688 HOST_WIDE_INT gp_reg_size
; /* # bytes needed to store gp regs */
4689 HOST_WIDE_INT fp_reg_size
; /* # bytes needed to store fp regs */
4690 long mask
; /* mask of saved gp registers */
4691 long fmask
; /* mask of saved fp registers */
4692 int fp_inc
; /* 1 or 2 depending on the size of fp regs */
4693 long fp_bits
; /* bitmask to use for each fp register */
4699 extra_size
= MIPS_STACK_ALIGN (((TARGET_ABICALLS
) ? UNITS_PER_WORD
: 0));
4700 var_size
= MIPS_STACK_ALIGN (size
);
4701 args_size
= MIPS_STACK_ALIGN (current_function_outgoing_args_size
);
4703 /* The MIPS 3.0 linker does not like functions that dynamically allocate the
4704 stack and have 0 for STACK_DYNAMIC_OFFSET, since it looks like we are
4705 trying to create a second frame pointer to the function, so allocate
4706 some stack space to make it happy. */
4708 if (args_size
== 0 && current_function_calls_alloca
)
4709 args_size
= 4 * UNITS_PER_WORD
;
4711 total_size
= var_size
+ args_size
+ extra_size
;
4713 /* Calculate space needed for gp registers. */
4714 for (regno
= GP_REG_FIRST
; regno
<= GP_REG_LAST
; regno
++)
4715 if (MUST_SAVE_REGISTER (regno
))
4717 gp_reg_size
+= UNITS_PER_WORD
;
4718 mask
|= 1L << (regno
- GP_REG_FIRST
);
4721 /* Calculate space needed for fp registers. */
4722 if (TARGET_FLOAT64
|| TARGET_SINGLE_FLOAT
)
4723 fp_inc
= 1, fp_bits
= 1;
4725 fp_inc
= 2, fp_bits
= 3;
4727 for (regno
= FP_REG_FIRST
; regno
<= FP_REG_LAST
; regno
+= fp_inc
)
4728 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
4730 fp_reg_size
+= fp_inc
* UNITS_PER_FPREG
;
4731 fmask
|= fp_bits
<< (regno
- FP_REG_FIRST
);
4734 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
4735 total_size
+= gp_reg_rounded
+ MIPS_STACK_ALIGN (fp_reg_size
);
4737 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
4738 for leaf routines (total_size == extra_size) to save the gp reg.
4739 The gp reg is callee saved in the 64 bit ABI, so all routines must
4740 save the gp reg. This is not a leaf routine if -p, because of the
4742 if (total_size
== extra_size
&& (mips_abi
== ABI_32
|| mips_abi
== ABI_EABI
)
4744 total_size
= extra_size
= 0;
4745 else if (TARGET_ABICALLS
)
4747 /* Add the context-pointer to the saved registers. */
4748 gp_reg_size
+= UNITS_PER_WORD
;
4749 mask
|= 1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
);
4750 total_size
-= gp_reg_rounded
;
4751 gp_reg_rounded
= MIPS_STACK_ALIGN (gp_reg_size
);
4752 total_size
+= gp_reg_rounded
;
4755 /* Add in space reserved on the stack by the callee for storing arguments
4756 passed in registers. */
4757 if (mips_abi
!= ABI_32
)
4758 total_size
+= MIPS_STACK_ALIGN (current_function_pretend_args_size
);
4760 /* Save other computed information. */
4761 current_frame_info
.total_size
= total_size
;
4762 current_frame_info
.var_size
= var_size
;
4763 current_frame_info
.args_size
= args_size
;
4764 current_frame_info
.extra_size
= extra_size
;
4765 current_frame_info
.gp_reg_size
= gp_reg_size
;
4766 current_frame_info
.fp_reg_size
= fp_reg_size
;
4767 current_frame_info
.mask
= mask
;
4768 current_frame_info
.fmask
= fmask
;
4769 current_frame_info
.initialized
= reload_completed
;
4770 current_frame_info
.num_gp
= gp_reg_size
/ UNITS_PER_WORD
;
4771 current_frame_info
.num_fp
= fp_reg_size
/ (fp_inc
* UNITS_PER_FPREG
);
4775 unsigned long offset
= (args_size
+ extra_size
+ var_size
4776 + gp_reg_size
- UNITS_PER_WORD
);
4777 current_frame_info
.gp_sp_offset
= offset
;
4778 current_frame_info
.gp_save_offset
= offset
- total_size
;
4782 current_frame_info
.gp_sp_offset
= 0;
4783 current_frame_info
.gp_save_offset
= 0;
4788 unsigned long offset
= (args_size
+ extra_size
+ var_size
4789 + gp_reg_rounded
+ fp_reg_size
4790 - fp_inc
* UNITS_PER_FPREG
);
4791 current_frame_info
.fp_sp_offset
= offset
;
4792 current_frame_info
.fp_save_offset
= offset
- total_size
;
4796 current_frame_info
.fp_sp_offset
= 0;
4797 current_frame_info
.fp_save_offset
= 0;
4800 /* Ok, we're done. */
4804 /* Common code to emit the insns (or to write the instructions to a file)
4805 to save/restore registers.
4807 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
4808 is not modified within save_restore_insns. */
4810 #define BITSET_P(VALUE,BIT) (((VALUE) & (1L << (BIT))) != 0)
4813 save_restore_insns (store_p
, large_reg
, large_offset
, file
)
4814 int store_p
; /* true if this is prologue */
4815 rtx large_reg
; /* register holding large offset constant or NULL */
4816 long large_offset
; /* large constant offset value */
4817 FILE *file
; /* file to write instructions instead of making RTL */
4819 long mask
= current_frame_info
.mask
;
4820 long fmask
= current_frame_info
.fmask
;
4823 HOST_WIDE_INT base_offset
;
4824 HOST_WIDE_INT gp_offset
;
4825 HOST_WIDE_INT fp_offset
;
4826 HOST_WIDE_INT end_offset
;
4829 if (frame_pointer_needed
4830 && ! BITSET_P (mask
, FRAME_POINTER_REGNUM
- GP_REG_FIRST
))
4833 if (mask
== 0 && fmask
== 0)
4836 /* Save registers starting from high to low. The debuggers prefer at least
4837 the return register be stored at func+4, and also it allows us not to
4838 need a nop in the epilog if at least one register is reloaded in
4839 addition to return address. */
4841 /* Save GP registers if needed. */
4844 /* Pick which pointer to use as a base register. For small frames, just
4845 use the stack pointer. Otherwise, use a temporary register. Save 2
4846 cycles if the save area is near the end of a large frame, by reusing
4847 the constant created in the prologue/epilogue to adjust the stack
4850 gp_offset
= current_frame_info
.gp_sp_offset
;
4852 = gp_offset
- (current_frame_info
.gp_reg_size
- UNITS_PER_WORD
);
4854 if (gp_offset
< 0 || end_offset
< 0)
4855 fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
4856 gp_offset
, end_offset
);
4858 else if (gp_offset
< 32768)
4859 base_reg_rtx
= stack_pointer_rtx
, base_offset
= 0;
4861 else if (large_reg
!= 0
4862 && (unsigned HOST_WIDE_INT
) (large_offset
- gp_offset
) < 32768
4863 && (unsigned HOST_WIDE_INT
) (large_offset
- end_offset
) < 32768)
4865 base_reg_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP2_REGNUM
);
4866 base_offset
= large_offset
;
4870 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
,
4871 stack_pointer_rtx
));
4873 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
,
4874 stack_pointer_rtx
));
4876 RTX_FRAME_RELATED_P (insn
) = 1;
4879 fprintf (file
, "\t%s\t%s,%s,%s\n",
4880 TARGET_LONG64
? "daddu" : "addu",
4881 reg_names
[MIPS_TEMP2_REGNUM
],
4882 reg_names
[REGNO (large_reg
)],
4883 reg_names
[STACK_POINTER_REGNUM
]);
4888 base_reg_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP2_REGNUM
);
4889 base_offset
= gp_offset
;
4892 rtx gp_offset_rtx
= GEN_INT (gp_offset
);
4894 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
4895 bit, so make sure that we don't emit anything that can be
4897 /* ??? There is no DImode ori immediate pattern, so we can only
4898 do this for 32 bit code. */
4899 if (large_int (gp_offset_rtx
)
4900 && GET_MODE (base_reg_rtx
) == SImode
)
4902 insn
= emit_move_insn (base_reg_rtx
,
4903 GEN_INT (gp_offset
& 0xffff0000));
4905 RTX_FRAME_RELATED_P (insn
) = 1;
4907 = emit_insn (gen_iorsi3 (base_reg_rtx
, base_reg_rtx
,
4908 GEN_INT (gp_offset
& 0x0000ffff)));
4910 RTX_FRAME_RELATED_P (insn
) = 1;
4914 insn
= emit_move_insn (base_reg_rtx
, gp_offset_rtx
);
4916 RTX_FRAME_RELATED_P (insn
) = 1;
4920 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, base_reg_rtx
,
4921 stack_pointer_rtx
));
4923 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
,
4924 stack_pointer_rtx
));
4926 RTX_FRAME_RELATED_P (insn
) = 1;
4929 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
4930 reg_names
[MIPS_TEMP2_REGNUM
],
4931 base_offset
, base_offset
,
4932 TARGET_LONG64
? "daddu" : "addu",
4933 reg_names
[MIPS_TEMP2_REGNUM
],
4934 reg_names
[MIPS_TEMP2_REGNUM
],
4935 reg_names
[STACK_POINTER_REGNUM
]);
4938 for (regno
= GP_REG_LAST
; regno
>= GP_REG_FIRST
; regno
--)
4939 if (BITSET_P (mask
, regno
- GP_REG_FIRST
))
4943 rtx reg_rtx
= gen_rtx_REG (word_mode
, regno
);
4945 = gen_rtx_MEM (word_mode
,
4946 plus_constant (base_reg_rtx
,
4947 gp_offset
- base_offset
));
4951 insn
= emit_move_insn (mem_rtx
, reg_rtx
);
4952 RTX_FRAME_RELATED_P (insn
) = 1;
4955 else if (!TARGET_ABICALLS
|| mips_abi
!= ABI_32
4956 || regno
!= (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))
4957 emit_move_insn (reg_rtx
, mem_rtx
);
4961 if (store_p
|| !TARGET_ABICALLS
|| mips_abi
!= ABI_32
4962 || regno
!= (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))
4963 fprintf (file
, "\t%s\t%s,%ld(%s)\n",
4965 ? (store_p
? "sd" : "ld")
4966 : (store_p
? "sw" : "lw")),
4967 reg_names
[regno
], gp_offset
- base_offset
,
4968 reg_names
[REGNO(base_reg_rtx
)]);
4971 gp_offset
-= UNITS_PER_WORD
;
4976 base_reg_rtx
= 0, base_offset
= 0;
4978 /* Save floating point registers if needed. */
4981 int fp_inc
= (TARGET_FLOAT64
|| TARGET_SINGLE_FLOAT
) ? 1 : 2;
4982 int fp_size
= fp_inc
* UNITS_PER_FPREG
;
4984 /* Pick which pointer to use as a base register. */
4985 fp_offset
= current_frame_info
.fp_sp_offset
;
4986 end_offset
= fp_offset
- (current_frame_info
.fp_reg_size
- fp_size
);
4988 if (fp_offset
< 0 || end_offset
< 0)
4989 fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
4990 fp_offset
, end_offset
);
4992 else if (fp_offset
< 32768)
4993 base_reg_rtx
= stack_pointer_rtx
, base_offset
= 0;
4995 else if (base_reg_rtx
!= 0
4996 && (unsigned HOST_WIDE_INT
) (base_offset
- fp_offset
) < 32768
4997 && (unsigned HOST_WIDE_INT
) (base_offset
- end_offset
) < 32768)
4998 ; /* already set up for gp registers above */
5000 else if (large_reg
!= 0
5001 && (unsigned HOST_WIDE_INT
) (large_offset
- fp_offset
) < 32768
5002 && (unsigned HOST_WIDE_INT
) (large_offset
- end_offset
) < 32768)
5004 base_reg_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP2_REGNUM
);
5005 base_offset
= large_offset
;
5009 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, large_reg
,
5010 stack_pointer_rtx
));
5012 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, large_reg
,
5013 stack_pointer_rtx
));
5015 RTX_FRAME_RELATED_P (insn
) = 1;
5019 fprintf (file
, "\t%s\t%s,%s,%s\n",
5020 TARGET_LONG64
? "daddu" : "addu",
5021 reg_names
[MIPS_TEMP2_REGNUM
],
5022 reg_names
[REGNO (large_reg
)],
5023 reg_names
[STACK_POINTER_REGNUM
]);
5028 base_reg_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP2_REGNUM
);
5029 base_offset
= fp_offset
;
5032 rtx fp_offset_rtx
= GEN_INT (fp_offset
);
5034 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
5035 bit, so make sure that we don't emit anything that can be
5037 /* ??? There is no DImode ori immediate pattern, so we can only
5038 do this for 32 bit code. */
5039 if (large_int (fp_offset_rtx
)
5040 && GET_MODE (base_reg_rtx
) == SImode
)
5042 insn
= emit_move_insn (base_reg_rtx
,
5043 GEN_INT (fp_offset
& 0xffff0000));
5045 RTX_FRAME_RELATED_P (insn
) = 1;
5046 insn
= emit_insn (gen_iorsi3 (base_reg_rtx
, base_reg_rtx
,
5047 GEN_INT (fp_offset
& 0x0000ffff)));
5049 RTX_FRAME_RELATED_P (insn
) = 1;
5053 insn
= emit_move_insn (base_reg_rtx
, fp_offset_rtx
);
5055 RTX_FRAME_RELATED_P (insn
) = 1;
5059 RTX_FRAME_RELATED_P (insn
) = 1;
5061 insn
= emit_insn (gen_adddi3 (base_reg_rtx
, base_reg_rtx
,
5062 stack_pointer_rtx
));
5064 insn
= emit_insn (gen_addsi3 (base_reg_rtx
, base_reg_rtx
,
5065 stack_pointer_rtx
));
5067 RTX_FRAME_RELATED_P (insn
) = 1;
5070 fprintf (file
, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
5071 reg_names
[MIPS_TEMP2_REGNUM
],
5072 base_offset
, base_offset
,
5073 TARGET_LONG64
? "daddu" : "addu",
5074 reg_names
[MIPS_TEMP2_REGNUM
],
5075 reg_names
[MIPS_TEMP2_REGNUM
],
5076 reg_names
[STACK_POINTER_REGNUM
]);
5079 for (regno
= FP_REG_LAST
-1; regno
>= FP_REG_FIRST
; regno
-= fp_inc
)
5080 if (BITSET_P (fmask
, regno
- FP_REG_FIRST
))
5084 enum machine_mode sz
5085 = TARGET_SINGLE_FLOAT
? SFmode
: DFmode
;
5086 rtx reg_rtx
= gen_rtx_REG (sz
, regno
);
5087 rtx mem_rtx
= gen_rtx_MEM (sz
,
5088 plus_constant (base_reg_rtx
,
5094 insn
= emit_move_insn (mem_rtx
, reg_rtx
);
5095 RTX_FRAME_RELATED_P (insn
) = 1;
5098 emit_move_insn (reg_rtx
, mem_rtx
);
5101 fprintf (file
, "\t%s\t%s,%ld(%s)\n",
5102 (TARGET_SINGLE_FLOAT
5103 ? (store_p
? "s.s" : "l.s")
5104 : (store_p
? "s.d" : "l.d")),
5106 fp_offset
- base_offset
,
5107 reg_names
[REGNO(base_reg_rtx
)]);
5109 fp_offset
-= fp_size
;
5114 /* Set up the stack and frame (if desired) for the function. */
5117 function_prologue (file
, size
)
5122 long tsize
= current_frame_info
.total_size
;
5124 ASM_OUTPUT_SOURCE_FILENAME (file
, DECL_SOURCE_FILE (current_function_decl
));
5126 #ifdef SDB_DEBUGGING_INFO
5127 if (debug_info_level
!= DINFO_LEVEL_TERSE
&& write_symbols
== SDB_DEBUG
)
5128 ASM_OUTPUT_SOURCE_LINE (file
, DECL_SOURCE_LINE (current_function_decl
));
5131 inside_function
= 1;
5133 #ifndef FUNCTION_NAME_ALREADY_DECLARED
5134 /* Get the function name the same way that toplev.c does before calling
5135 assemble_start_function. This is needed so that the name used here
5136 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
5137 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
5139 if (!flag_inhibit_size_directive
)
5141 fputs ("\t.ent\t", file
);
5142 assemble_name (file
, fnname
);
5146 assemble_name (file
, fnname
);
5147 fputs (":\n", file
);
5150 if (!flag_inhibit_size_directive
)
5153 "\t.frame\t%s,%d,%s\t\t# vars= %d, regs= %d/%d, args= %d, extra= %d\n",
5154 (reg_names
[(frame_pointer_needed
)
5155 ? FRAME_POINTER_REGNUM
: STACK_POINTER_REGNUM
]),
5156 tsize
, reg_names
[31 + GP_REG_FIRST
],
5157 current_frame_info
.var_size
,
5158 current_frame_info
.num_gp
,
5159 current_frame_info
.num_fp
,
5160 current_function_outgoing_args_size
,
5161 current_frame_info
.extra_size
);
5163 fprintf (file
, "\t.mask\t0x%08lx,%d\n\t.fmask\t0x%08lx,%d\n",
5164 current_frame_info
.mask
,
5165 current_frame_info
.gp_save_offset
,
5166 current_frame_info
.fmask
,
5167 current_frame_info
.fp_save_offset
);
5170 if (TARGET_ABICALLS
&& mips_abi
== ABI_32
)
5172 char *sp_str
= reg_names
[STACK_POINTER_REGNUM
];
5174 fprintf (file
, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
5175 reg_names
[PIC_FUNCTION_ADDR_REGNUM
]);
5178 fprintf (file
, "\t%s\t%s,%s,%d\n",
5179 (TARGET_LONG64
? "dsubu" : "subu"),
5180 sp_str
, sp_str
, tsize
);
5181 fprintf (file
, "\t.cprestore %d\n", current_frame_info
.args_size
);
5184 if (dwarf2out_do_frame ())
5185 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM
, tsize
);
5189 /* Expand the prologue into a bunch of separate insns. */
5192 mips_expand_prologue ()
5195 HOST_WIDE_INT tsize
;
5198 tree fndecl
= current_function_decl
;
5199 tree fntype
= TREE_TYPE (fndecl
);
5200 tree fnargs
= DECL_ARGUMENTS (fndecl
);
5205 CUMULATIVE_ARGS args_so_far
;
5207 /* If struct value address is treated as the first argument, make it so. */
5208 if (aggregate_value_p (DECL_RESULT (fndecl
))
5209 && ! current_function_returns_pcc_struct
5210 && struct_value_incoming_rtx
== 0)
5212 tree type
= build_pointer_type (fntype
);
5213 tree function_result_decl
= build_decl (PARM_DECL
, NULL_TREE
, type
);
5215 DECL_ARG_TYPE (function_result_decl
) = type
;
5216 TREE_CHAIN (function_result_decl
) = fnargs
;
5217 fnargs
= function_result_decl
;
5220 /* Determine the last argument, and get its name. */
5222 INIT_CUMULATIVE_ARGS (args_so_far
, fntype
, NULL_RTX
, 0);
5223 regno
= GP_ARG_FIRST
;
5225 for (cur_arg
= fnargs
; cur_arg
!= 0; cur_arg
= next_arg
)
5227 tree passed_type
= DECL_ARG_TYPE (cur_arg
);
5228 enum machine_mode passed_mode
= TYPE_MODE (passed_type
);
5231 if (TREE_ADDRESSABLE (passed_type
))
5233 passed_type
= build_pointer_type (passed_type
);
5234 passed_mode
= Pmode
;
5237 entry_parm
= FUNCTION_ARG (args_so_far
, passed_mode
, passed_type
, 1);
5243 /* passed in a register, so will get homed automatically */
5244 if (GET_MODE (entry_parm
) == BLKmode
)
5245 words
= (int_size_in_bytes (passed_type
) + 3) / 4;
5247 words
= (GET_MODE_SIZE (GET_MODE (entry_parm
)) + 3) / 4;
5249 regno
= REGNO (entry_parm
) + words
- 1;
5253 regno
= GP_ARG_LAST
+1;
5257 FUNCTION_ARG_ADVANCE (args_so_far
, passed_mode
, passed_type
, 1);
5259 next_arg
= TREE_CHAIN (cur_arg
);
5262 if (DECL_NAME (cur_arg
))
5263 arg_name
= IDENTIFIER_POINTER (DECL_NAME (cur_arg
));
5269 /* In order to pass small structures by value in registers compatibly with
5270 the MIPS compiler, we need to shift the value into the high part of the
5271 register. Function_arg has encoded a PARALLEL rtx, holding a vector of
5272 adjustments to be made as the next_arg_reg variable, so we split up the
5273 insns, and emit them separately. */
5275 next_arg_reg
= FUNCTION_ARG (args_so_far
, VOIDmode
, void_type_node
, 1);
5276 if (next_arg_reg
!= 0 && GET_CODE (next_arg_reg
) == PARALLEL
)
5278 rtvec adjust
= XVEC (next_arg_reg
, 0);
5279 int num
= GET_NUM_ELEM (adjust
);
5281 for (i
= 0; i
< num
; i
++)
5283 rtx pattern
= RTVEC_ELT (adjust
, i
);
5284 if (GET_CODE (pattern
) != SET
5285 || GET_CODE (SET_SRC (pattern
)) != ASHIFT
)
5286 abort_with_insn (pattern
, "Insn is not a shift");
5288 PUT_CODE (SET_SRC (pattern
), ASHIFTRT
);
5289 emit_insn (pattern
);
5293 tsize
= compute_frame_size (get_frame_size ());
5295 /* If this function is a varargs function, store any registers that
5296 would normally hold arguments ($4 - $7) on the stack. */
5297 if (mips_abi
== ABI_32
5298 && ((TYPE_ARG_TYPES (fntype
) != 0
5299 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype
)))
5302 && ((arg_name
[0] == '_'
5303 && strcmp (arg_name
, "__builtin_va_alist") == 0)
5304 || (arg_name
[0] == 'v'
5305 && strcmp (arg_name
, "va_alist") == 0)))))
5307 int offset
= (regno
- GP_ARG_FIRST
) * UNITS_PER_WORD
;
5308 rtx ptr
= stack_pointer_rtx
;
5310 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
5311 if (TARGET_ABICALLS
)
5314 for (; regno
<= GP_ARG_LAST
; regno
++)
5317 ptr
= plus_constant (stack_pointer_rtx
, offset
);
5319 emit_move_insn (gen_rtx_MEM (word_mode
, ptr
),
5320 gen_rtx_REG (word_mode
, regno
));
5321 offset
+= UNITS_PER_WORD
;
5327 rtx tsize_rtx
= GEN_INT (tsize
);
5329 /* If we are doing svr4-abi, sp move is done by function_prologue. */
5330 if (!TARGET_ABICALLS
|| mips_abi
!= ABI_32
)
5336 tmp_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP1_REGNUM
);
5338 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
5339 bit, so make sure that we don't emit anything that can be
5341 /* ??? There is no DImode ori immediate pattern, so we can only
5342 do this for 32 bit code. */
5343 if (large_int (tsize_rtx
) && GET_MODE (tmp_rtx
) == SImode
)
5345 insn
= emit_move_insn (tmp_rtx
,
5346 GEN_INT (tsize
& 0xffff0000));
5347 RTX_FRAME_RELATED_P (insn
) = 1;
5348 insn
= emit_insn (gen_iorsi3 (tmp_rtx
, tmp_rtx
,
5349 GEN_INT (tsize
& 0x0000ffff)));
5350 RTX_FRAME_RELATED_P (insn
) = 1;
5354 insn
= emit_move_insn (tmp_rtx
, tsize_rtx
);
5355 RTX_FRAME_RELATED_P (insn
) = 1;
5358 tsize_rtx
= tmp_rtx
;
5362 insn
= emit_insn (gen_subdi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5365 insn
= emit_insn (gen_subsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5368 RTX_FRAME_RELATED_P (insn
) = 1;
5371 save_restore_insns (TRUE
, tmp_rtx
, tsize
, (FILE *)0);
5373 if (frame_pointer_needed
)
5378 insn
= emit_insn (gen_movdi (frame_pointer_rtx
,
5379 stack_pointer_rtx
));
5381 insn
= emit_insn (gen_movsi (frame_pointer_rtx
,
5382 stack_pointer_rtx
));
5384 RTX_FRAME_RELATED_P (insn
) = 1;
5387 if (TARGET_ABICALLS
&& mips_abi
!= ABI_32
)
5388 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl
), 0),
5389 gen_rtx_REG (DImode
, 25)));
5392 /* If we are profiling, make sure no instructions are scheduled before
5393 the call to mcount. */
5395 if (profile_flag
|| profile_block_flag
)
5396 emit_insn (gen_blockage ());
5399 /* Do any necessary cleanup after a function to restore stack, frame,
5402 #define RA_MASK ((long) 0x80000000) /* 1 << 31 */
5403 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
5406 function_epilogue (file
, size
)
5412 #ifndef FUNCTION_NAME_ALREADY_DECLARED
5413 /* Get the function name the same way that toplev.c does before calling
5414 assemble_start_function. This is needed so that the name used here
5415 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
5416 fnname
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
5418 if (!flag_inhibit_size_directive
)
5420 fputs ("\t.end\t", file
);
5421 assemble_name (file
, fnname
);
5428 int num_gp_regs
= current_frame_info
.gp_reg_size
/ 4;
5429 int num_fp_regs
= current_frame_info
.fp_reg_size
/ 8;
5430 int num_regs
= num_gp_regs
+ num_fp_regs
;
5431 char *name
= fnname
;
5436 dslots_load_total
+= num_regs
;
5439 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3ld reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
5440 name
, frame_pointer_needed
? 'y' : 'n',
5441 (current_frame_info
.mask
& RA_MASK
) != 0 ? 'n' : 'y',
5442 current_function_calls_alloca
? 'y' : 'n',
5443 current_function_calls_setjmp
? 'y' : 'n',
5444 current_frame_info
.total_size
,
5445 current_function_outgoing_args_size
, num_gp_regs
, num_fp_regs
,
5446 dslots_load_total
, dslots_load_filled
,
5447 dslots_jump_total
, dslots_jump_filled
,
5448 num_refs
[0], num_refs
[1], num_refs
[2]);
5450 if (HALF_PIC_NUMBER_PTRS
> prev_half_pic_ptrs
)
5453 " half-pic=%3d", HALF_PIC_NUMBER_PTRS
- prev_half_pic_ptrs
);
5454 prev_half_pic_ptrs
= HALF_PIC_NUMBER_PTRS
;
5457 if (HALF_PIC_NUMBER_REFS
> prev_half_pic_refs
)
5460 " pic-ref=%3d", HALF_PIC_NUMBER_REFS
- prev_half_pic_refs
);
5461 prev_half_pic_refs
= HALF_PIC_NUMBER_REFS
;
5464 fputc ('\n', stderr
);
5467 /* Reset state info for each function. */
5468 inside_function
= 0;
5469 ignore_line_number
= 0;
5470 dslots_load_total
= 0;
5471 dslots_jump_total
= 0;
5472 dslots_load_filled
= 0;
5473 dslots_jump_filled
= 0;
5479 current_frame_info
= zero_frame_info
;
5481 /* Restore the output file if optimizing the GP (optimizing the GP causes
5482 the text to be diverted to a tempfile, so that data decls come before
5483 references to the data). */
5486 asm_out_file
= asm_out_data_file
;
5489 /* Expand the epilogue into a bunch of separate insns. */
5492 mips_expand_epilogue ()
5494 HOST_WIDE_INT tsize
= current_frame_info
.total_size
;
5495 rtx tsize_rtx
= GEN_INT (tsize
);
5496 rtx tmp_rtx
= (rtx
)0;
5498 if (mips_can_use_return_insn ())
5500 emit_insn (gen_return ());
5506 tmp_rtx
= gen_rtx_REG (Pmode
, MIPS_TEMP1_REGNUM
);
5507 emit_move_insn (tmp_rtx
, tsize_rtx
);
5508 tsize_rtx
= tmp_rtx
;
5513 if (frame_pointer_needed
)
5515 emit_insn (gen_blockage ());
5517 emit_insn (gen_movdi (stack_pointer_rtx
, frame_pointer_rtx
));
5519 emit_insn (gen_movsi (stack_pointer_rtx
, frame_pointer_rtx
));
5522 /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
5523 are going to restore it, then we must emit a blockage insn to
5524 prevent the scheduler from moving the restore out of the epilogue. */
5525 else if (TARGET_ABICALLS
&& mips_abi
!= ABI_32
5526 && (current_frame_info
.mask
5527 & (1L << (PIC_OFFSET_TABLE_REGNUM
- GP_REG_FIRST
))))
5528 emit_insn (gen_blockage ());
5530 save_restore_insns (FALSE
, tmp_rtx
, tsize
, (FILE *)0);
5532 emit_insn (gen_blockage ());
5534 emit_insn (gen_adddi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5537 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
5541 emit_jump_insn (gen_return_internal ());
5544 /* Return nonzero if this function is known to have a null epilogue.
5545 This allows the optimizer to omit jumps to jumps if no stack
5549 mips_can_use_return_insn ()
5551 if (! reload_completed
)
5554 if (regs_ever_live
[31] || profile_flag
)
5557 if (current_frame_info
.initialized
)
5558 return current_frame_info
.total_size
== 0;
5560 return compute_frame_size (get_frame_size ()) == 0;
5563 /* Choose the section to use for the constant rtx expression X that has
5566 mips_select_rtx_section (mode
, x
)
5567 enum machine_mode mode
;
5570 if (TARGET_EMBEDDED_DATA
)
5572 /* For embedded applications, always put constants in read-only data,
5573 in order to reduce RAM usage. */
5574 READONLY_DATA_SECTION ();
5578 /* For hosted applications, always put constants in small data if
5579 possible, as this gives the best performance. */
5581 if (GET_MODE_SIZE (mode
) <= mips_section_threshold
5582 && mips_section_threshold
> 0)
5583 SMALL_DATA_SECTION ();
5585 READONLY_DATA_SECTION ();
5589 /* Choose the section to use for DECL. RELOC is true if its value contains
5590 any relocatable expression. */
5592 mips_select_section (decl
, reloc
)
5596 int size
= int_size_in_bytes (TREE_TYPE (decl
));
5598 if (TARGET_EMBEDDED_PIC
5599 && TREE_CODE (decl
) == STRING_CST
5600 && !flag_writable_strings
)
5601 /* For embedded position independent code, put constant strings in the
5602 text section, because the data section is limited to 64K in size. */
5605 else if (TARGET_EMBEDDED_DATA
)
5607 /* For embedded applications, always put an object in read-only data
5608 if possible, in order to reduce RAM usage. */
5610 if (((TREE_CODE (decl
) == VAR_DECL
5611 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
5612 && DECL_INITIAL (decl
)
5613 && (DECL_INITIAL (decl
) == error_mark_node
5614 || TREE_CONSTANT (DECL_INITIAL (decl
))))
5615 /* Deal with calls from output_constant_def_contents. */
5616 || (TREE_CODE (decl
) != VAR_DECL
5617 && (TREE_CODE (decl
) != STRING_CST
5618 || !flag_writable_strings
)))
5619 && ! (flag_pic
&& reloc
))
5620 READONLY_DATA_SECTION ();
5621 else if (size
> 0 && size
<= mips_section_threshold
)
5622 SMALL_DATA_SECTION ();
5628 /* For hosted applications, always put an object in small data if
5629 possible, as this gives the best performance. */
5631 if (size
> 0 && size
<= mips_section_threshold
)
5632 SMALL_DATA_SECTION ();
5633 else if (((TREE_CODE (decl
) == VAR_DECL
5634 && TREE_READONLY (decl
) && !TREE_SIDE_EFFECTS (decl
)
5635 && DECL_INITIAL (decl
)
5636 && (DECL_INITIAL (decl
) == error_mark_node
5637 || TREE_CONSTANT (DECL_INITIAL (decl
))))
5638 /* Deal with calls from output_constant_def_contents. */
5639 || (TREE_CODE (decl
) != VAR_DECL
5640 && (TREE_CODE (decl
) != STRING_CST
5641 || !flag_writable_strings
)))
5642 && ! (flag_pic
&& reloc
))
5643 READONLY_DATA_SECTION ();
5649 #ifdef MIPS_ABI_DEFAULT
5651 /* Support functions for the 64 bit ABI. */
5653 /* Return register to use for a function return value with VALTYPE for function
5657 mips_function_value (valtype
, func
)
5661 int reg
= GP_RETURN
;
5662 enum machine_mode mode
= TYPE_MODE (valtype
);
5663 enum mode_class mclass
= GET_MODE_CLASS (mode
);
5665 /* ??? How should we return complex float? */
5666 if (mclass
== MODE_FLOAT
|| mclass
== MODE_COMPLEX_FLOAT
)
5668 if (TARGET_SINGLE_FLOAT
5669 && (mclass
== MODE_FLOAT
5670 ? GET_MODE_SIZE (mode
) > 4 : GET_MODE_SIZE (mode
) / 2 > 4))
5676 else if (TREE_CODE (valtype
) == RECORD_TYPE
5677 && mips_abi
!= ABI_32
&& mips_abi
!= ABI_EABI
)
5679 /* A struct with only one or two floating point fields is returned in
5680 the floating point registers. */
5681 tree field
, fields
[2];
5684 for (i
= 0, field
= TYPE_FIELDS (valtype
); field
;
5685 field
= TREE_CHAIN (field
))
5687 if (TREE_CODE (field
) != FIELD_DECL
)
5690 if (TREE_CODE (TREE_TYPE (field
)) != REAL_TYPE
|| i
>= 2)
5693 fields
[i
++] = field
;
5696 /* Must check i, so that we reject structures with no elements. */
5701 /* The structure has DImode, but we don't allow DImode values
5702 in FP registers, so we use a PARALLEL even though it isn't
5703 strictly necessary. */
5704 enum machine_mode field_mode
= TYPE_MODE (TREE_TYPE (fields
[0]));
5706 return gen_rtx_PARALLEL
5709 gen_rtx_EXPR_LIST (VOIDmode
,
5710 gen_rtx_REG (field_mode
,
5717 enum machine_mode first_mode
5718 = TYPE_MODE (TREE_TYPE (fields
[0]));
5719 enum machine_mode second_mode
5720 = TYPE_MODE (TREE_TYPE (fields
[1]));
5722 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields
[0]));
5724 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields
[1]));
5726 return gen_rtx_PARALLEL
5729 gen_rtx_EXPR_LIST (VOIDmode
,
5730 gen_rtx_REG (first_mode
,
5732 GEN_INT (first_offset
5734 gen_rtx_EXPR_LIST (VOIDmode
,
5735 gen_rtx_REG (second_mode
,
5737 GEN_INT (second_offset
5738 / BITS_PER_UNIT
))));
5743 return gen_rtx_REG (mode
, reg
);
5746 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
5747 nonzero when an argument must be passed by reference. */
5750 function_arg_pass_by_reference (cum
, mode
, type
, named
)
5751 CUMULATIVE_ARGS
*cum
;
5752 enum machine_mode mode
;
5758 /* We must pass by reference if we would be both passing in registers
5759 and the stack. This is because any subsequent partial arg would be
5760 handled incorrectly in this case.
5762 ??? This is really a kludge. We should either fix GCC so that such
5763 a situation causes an abort and then do something in the MIPS port
5764 to prevent it, or add code to function.c to properly handle the case. */
5765 if (FUNCTION_ARG (*cum
, mode
, type
, named
) != 0
5766 && MUST_PASS_IN_STACK (mode
, type
))
5769 /* Otherwise, we only do this if EABI is selected. */
5770 if (mips_abi
!= ABI_EABI
)
5773 /* ??? How should SCmode be handled? */
5774 if (type
== NULL_TREE
|| mode
== DImode
|| mode
== DFmode
)
5777 size
= int_size_in_bytes (type
);
5778 return size
== -1 || size
> UNITS_PER_WORD
;
5782 /* This function returns the register class required for a secondary
5783 register when copying between one of the registers in CLASS, and X,
5784 using MODE. If IN_P is nonzero, the copy is going from X to the
5785 register, otherwise the register is the source. A return value of
5786 NO_REGS means that no secondary register is required. */
5789 mips_secondary_reload_class (class, mode
, x
, in_p
)
5790 enum reg_class
class;
5791 enum machine_mode mode
;
5797 if (GET_CODE (x
) == SIGN_EXTEND
)
5803 /* We may be called with reg_renumber NULL from regclass.
5804 ??? This is probably a bug. */
5806 regno
= true_regnum (x
);
5809 while (GET_CODE (x
) == SUBREG
)
5811 off
+= SUBREG_WORD (x
);
5815 if (GET_CODE (x
) == REG
)
5816 regno
= REGNO (x
) + off
;
5820 else if (GET_CODE (x
) == REG
|| GET_CODE (x
) == SUBREG
)
5821 regno
= true_regnum (x
);
5823 /* We always require a general register when copying anything to
5824 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
5825 to a general register, or when copying from register 0. */
5826 if (class == HILO_REG
&& regno
!= GP_REG_FIRST
+ 0)
5829 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
5830 ? NO_REGS
: GR_REGS
);
5832 else if (regno
== HILO_REGNUM
)
5835 && GET_MODE_SIZE (mode
) <= GET_MODE_SIZE (SImode
))
5836 ? NO_REGS
: GR_REGS
);
5838 /* Copying from HI or LO to anywhere other than a general register
5839 requires a general register. */
5840 else if (class == HI_REG
|| class == LO_REG
|| class == MD_REGS
)
5841 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
5843 else if (MD_REG_P (regno
))
5844 return class == GR_REGS
? NO_REGS
: GR_REGS
;
5846 /* We can only copy a value to a condition code register from a floating
5847 point register, and even then we require a scratch floating point
5848 register. We can only copy a value out of a condition code register
5849 into a general register. */
5850 else if (class == ST_REGS
)
5855 return GP_REG_P (regno
) ? NO_REGS
: GR_REGS
;
5858 else if (ST_REG_P (regno
))
5863 return class == GR_REGS
? NO_REGS
: GR_REGS
;