1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C) 2005-2019 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return 1 for anything except PARALLEL.
21 (define_predicate "any_operand"
22 (match_code "const_int,const_double,const_wide_int,const,symbol_ref,label_ref,subreg,reg,mem"))
24 ;; Return 1 for any PARALLEL.
25 (define_predicate "any_parallel_operand"
26 (match_code "parallel"))
28 ;; Return 1 if op is COUNT register.
29 (define_predicate "count_register_operand"
30 (and (match_code "reg")
31 (match_test "REGNO (op) == CTR_REGNO
32 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
34 ;; Return 1 if op is a SUBREG that is used to look at a SFmode value as
35 ;; and integer or vice versa.
37 ;; In the normal case where SFmode is in a floating point/vector register, it
38 ;; is stored as a DFmode and has a different format. If we don't transform the
39 ;; value, things that use logical operations on the values will get the wrong
42 ;; If we don't have 64-bit and direct move, this conversion will be done by
43 ;; store and load, instead of by fiddling with the bits within the register.
44 (define_predicate "sf_subreg_operand"
47 rtx inner_reg = SUBREG_REG (op);
48 machine_mode inner_mode = GET_MODE (inner_reg);
50 if (TARGET_ALLOW_SF_SUBREG || !REG_P (inner_reg))
53 if ((mode == SFmode && GET_MODE_CLASS (inner_mode) == MODE_INT)
54 || (GET_MODE_CLASS (mode) == MODE_INT && inner_mode == SFmode))
56 if (INT_REGNO_P (REGNO (inner_reg)))
64 ;; Return 1 if op is an Altivec register.
65 (define_predicate "altivec_register_operand"
66 (match_operand 0 "register_operand")
70 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
79 if (!HARD_REGISTER_P (op))
82 return ALTIVEC_REGNO_P (REGNO (op));
85 ;; Return 1 if op is a VSX register.
86 (define_predicate "vsx_register_operand"
87 (match_operand 0 "register_operand")
91 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
100 if (!HARD_REGISTER_P (op))
103 return VSX_REGNO_P (REGNO (op));
106 ;; Like vsx_register_operand, but allow SF SUBREGS
107 (define_predicate "vsx_reg_sfsubreg_ok"
108 (match_operand 0 "register_operand")
111 op = SUBREG_REG (op);
116 if (!HARD_REGISTER_P (op))
119 return VSX_REGNO_P (REGNO (op));
122 ;; Return 1 if op is a vector register that operates on floating point vectors
123 ;; (either altivec or VSX).
124 (define_predicate "vfloat_operand"
125 (match_operand 0 "register_operand")
129 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
132 op = SUBREG_REG (op);
138 if (!HARD_REGISTER_P (op))
141 return VFLOAT_REGNO_P (REGNO (op));
144 ;; Return 1 if op is a vector register that operates on integer vectors
145 ;; (only altivec, VSX doesn't support integer vectors)
146 (define_predicate "vint_operand"
147 (match_operand 0 "register_operand")
151 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
154 op = SUBREG_REG (op);
160 if (!HARD_REGISTER_P (op))
163 return VINT_REGNO_P (REGNO (op));
166 ;; Return 1 if op is a vector register to do logical operations on (and, or,
168 (define_predicate "vlogical_operand"
169 (match_operand 0 "register_operand")
173 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
176 op = SUBREG_REG (op);
183 if (!HARD_REGISTER_P (op))
186 return VLOGICAL_REGNO_P (REGNO (op));
189 ;; Return 1 if op is the carry register.
190 (define_predicate "ca_operand"
191 (match_operand 0 "register_operand")
194 op = SUBREG_REG (op);
199 return CA_REGNO_P (REGNO (op));
202 ;; Return 1 if operand is constant zero (scalars and vectors).
203 (define_predicate "zero_constant"
204 (and (match_code "const_int,const_double,const_wide_int,const_vector")
205 (match_test "op == CONST0_RTX (mode)")))
207 ;; Return 1 if operand is constant -1 (scalars and vectors).
208 (define_predicate "all_ones_constant"
209 (and (match_code "const_int,const_double,const_wide_int,const_vector")
210 (match_test "op == CONSTM1_RTX (mode) && !FLOAT_MODE_P (mode)")))
212 ;; Return 1 if op is a signed 5-bit constant integer.
213 (define_predicate "s5bit_cint_operand"
214 (and (match_code "const_int")
215 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))
217 ;; Return 1 if op is a unsigned 3-bit constant integer.
218 (define_predicate "u3bit_cint_operand"
219 (and (match_code "const_int")
220 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 7")))
222 ;; Return 1 if op is a unsigned 5-bit constant integer.
223 (define_predicate "u5bit_cint_operand"
224 (and (match_code "const_int")
225 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31")))
227 ;; Return 1 if op is a unsigned 6-bit constant integer.
228 (define_predicate "u6bit_cint_operand"
229 (and (match_code "const_int")
230 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 63")))
232 ;; Return 1 if op is an unsigned 7-bit constant integer.
233 (define_predicate "u7bit_cint_operand"
234 (and (match_code "const_int")
235 (match_test "IN_RANGE (INTVAL (op), 0, 127)")))
237 ;; Return 1 if op is a signed 8-bit constant integer.
238 ;; Integer multiplication complete more quickly
239 (define_predicate "s8bit_cint_operand"
240 (and (match_code "const_int")
241 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))
243 ;; Return 1 if op is a unsigned 10-bit constant integer.
244 (define_predicate "u10bit_cint_operand"
245 (and (match_code "const_int")
246 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 1023")))
248 ;; Return 1 if op is a constant integer that can fit in a D field.
249 (define_predicate "short_cint_operand"
250 (and (match_code "const_int")
251 (match_test "satisfies_constraint_I (op)")))
253 ;; Return 1 if op is a constant integer that can fit in an unsigned D field.
254 (define_predicate "u_short_cint_operand"
255 (and (match_code "const_int")
256 (match_test "satisfies_constraint_K (op)")))
258 ;; Return 1 if op is a constant integer that is a signed 16-bit constant
259 ;; shifted left 16 bits
260 (define_predicate "upper16_cint_operand"
261 (and (match_code "const_int")
262 (match_test "satisfies_constraint_L (op)")))
264 ;; Return 1 if op is a constant integer that cannot fit in a signed D field.
265 (define_predicate "non_short_cint_operand"
266 (and (match_code "const_int")
267 (match_test "(unsigned HOST_WIDE_INT)
268 (INTVAL (op) + 0x8000) >= 0x10000")))
270 ;; Return 1 if op is a positive constant integer that is an exact power of 2.
271 (define_predicate "exact_log2_cint_operand"
272 (and (match_code "const_int")
273 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0")))
275 ;; Match op = 0 or op = 1.
276 (define_predicate "const_0_to_1_operand"
277 (and (match_code "const_int")
278 (match_test "IN_RANGE (INTVAL (op), 0, 1)")))
281 (define_predicate "const_0_to_3_operand"
282 (and (match_code "const_int")
283 (match_test "IN_RANGE (INTVAL (op), 0, 3)")))
285 ;; Match op = 2 or op = 3.
286 (define_predicate "const_2_to_3_operand"
287 (and (match_code "const_int")
288 (match_test "IN_RANGE (INTVAL (op), 2, 3)")))
291 (define_predicate "const_0_to_7_operand"
292 (and (match_code "const_int")
293 (match_test "IN_RANGE (INTVAL (op), 0, 7)")))
296 (define_predicate "const_0_to_12_operand"
297 (and (match_code "const_int")
298 (match_test "IN_RANGE (INTVAL (op), 0, 12)")))
301 (define_predicate "const_0_to_15_operand"
302 (and (match_code "const_int")
303 (match_test "IN_RANGE (INTVAL (op), 0, 15)")))
305 ;; Return 1 if op is a 34-bit constant integer.
306 (define_predicate "cint34_operand"
307 (match_code "const_int")
309 if (!TARGET_PREFIXED_ADDR)
312 return SIGNED_34BIT_OFFSET_P (INTVAL (op));
315 ;; Return 1 if op is a register that is not special.
316 ;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where
317 ;; you need to be careful in moving a SFmode to SImode and vice versa due to
318 ;; the fact that SFmode is represented as DFmode in the VSX registers.
319 (define_predicate "gpc_reg_operand"
320 (match_operand 0 "register_operand")
324 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
327 op = SUBREG_REG (op);
333 if (!HARD_REGISTER_P (op))
336 if (TARGET_ALTIVEC && ALTIVEC_REGNO_P (REGNO (op)))
339 if (TARGET_VSX && VSX_REGNO_P (REGNO (op)))
342 return INT_REGNO_P (REGNO (op)) || FP_REGNO_P (REGNO (op));
345 ;; Return 1 if op is a general purpose register. Unlike gpc_reg_operand, don't
346 ;; allow floating point or vector registers. Since vector registers are not
347 ;; allowed, we don't have to reject SFmode/SImode subregs.
348 (define_predicate "int_reg_operand"
349 (match_operand 0 "register_operand")
353 if (TARGET_NO_SF_SUBREG && sf_subreg_operand (op, mode))
356 op = SUBREG_REG (op);
362 if (!HARD_REGISTER_P (op))
365 return INT_REGNO_P (REGNO (op));
368 ;; Like int_reg_operand, but don't return true for pseudo registers
369 ;; We don't have to check for SF SUBREGS because pseudo registers
370 ;; are not allowed, and SF SUBREGs are ok within GPR registers.
371 (define_predicate "int_reg_operand_not_pseudo"
372 (match_operand 0 "register_operand")
375 op = SUBREG_REG (op);
380 if (!HARD_REGISTER_P (op))
383 return INT_REGNO_P (REGNO (op));
386 ;; Like int_reg_operand, but only return true for base registers
387 (define_predicate "base_reg_operand"
388 (match_operand 0 "int_reg_operand")
391 op = SUBREG_REG (op);
396 return (REGNO (op) != FIRST_GPR_REGNO);
400 ;; Return true if this is a traditional floating point register
401 (define_predicate "fpr_reg_operand"
402 (match_code "reg,subreg")
407 op = SUBREG_REG (op);
413 if (!HARD_REGISTER_NUM_P (r))
416 return FP_REGNO_P (r);
419 ;; Return 1 if op is a general purpose register that is an even register
420 ;; which suitable for a load/store quad operation
421 ;; Subregs are not allowed here because when they are combine can
422 ;; create (subreg:PTI (reg:TI pseudo)) which will cause reload to
423 ;; think the innermost reg needs reloading, in TImode instead of
424 ;; PTImode. So reload will choose a reg in TImode which has no
425 ;; requirement that the reg be even.
426 (define_predicate "quad_int_reg_operand"
431 if (!TARGET_QUAD_MEMORY && !TARGET_QUAD_MEMORY_ATOMIC)
435 if (!HARD_REGISTER_NUM_P (r))
438 return (INT_REGNO_P (r) && ((r & 1) == 0));
441 ;; Return 1 if op is a register that is a condition register field.
442 (define_predicate "cc_reg_operand"
443 (match_operand 0 "register_operand")
446 op = SUBREG_REG (op);
451 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
454 return CR_REGNO_P (REGNO (op));
457 ;; Return 1 if op is a register that is a condition register field not cr0.
458 (define_predicate "cc_reg_not_cr0_operand"
459 (match_operand 0 "register_operand")
462 op = SUBREG_REG (op);
467 if (REGNO (op) > LAST_VIRTUAL_REGISTER)
470 return CR_REGNO_NOT_CR0_P (REGNO (op));
473 ;; Return 1 if op is a constant integer valid for D field
474 ;; or non-special register register.
475 (define_predicate "reg_or_short_operand"
476 (if_then_else (match_code "const_int")
477 (match_operand 0 "short_cint_operand")
478 (match_operand 0 "gpc_reg_operand")))
480 ;; Return 1 if op is a constant integer valid for DS field
481 ;; or non-special register.
482 (define_predicate "reg_or_aligned_short_operand"
483 (if_then_else (match_code "const_int")
484 (and (match_operand 0 "short_cint_operand")
485 (match_test "!(INTVAL (op) & 3)"))
486 (match_operand 0 "gpc_reg_operand")))
488 ;; Return 1 if op is a constant integer whose high-order 16 bits are zero
489 ;; or non-special register.
490 (define_predicate "reg_or_u_short_operand"
491 (if_then_else (match_code "const_int")
492 (match_operand 0 "u_short_cint_operand")
493 (match_operand 0 "gpc_reg_operand")))
495 ;; Return 1 if op is any constant integer or a non-special register.
496 (define_predicate "reg_or_cint_operand"
497 (ior (match_code "const_int")
498 (match_operand 0 "gpc_reg_operand")))
500 ;; Return 1 if op is constant zero or a non-special register.
501 (define_predicate "reg_or_zero_operand"
502 (ior (match_operand 0 "zero_constant")
503 (match_operand 0 "gpc_reg_operand")))
505 ;; Return 1 if op is a constant integer valid for addition with addis, addi.
506 (define_predicate "add_cint_operand"
507 (and (match_code "const_int")
508 (match_test "((unsigned HOST_WIDE_INT) INTVAL (op)
509 + (mode == SImode ? 0x80000000 : 0x80008000))
510 < (unsigned HOST_WIDE_INT) 0x100000000ll")))
512 ;; Return 1 if op is a constant integer valid for addition
513 ;; or non-special register.
514 (define_predicate "reg_or_add_cint_operand"
515 (if_then_else (match_code "const_int")
516 (match_operand 0 "add_cint_operand")
517 (match_operand 0 "gpc_reg_operand")))
519 ;; Return 1 if op is a constant integer valid for subtraction
520 ;; or non-special register.
521 (define_predicate "reg_or_sub_cint_operand"
522 (if_then_else (match_code "const_int")
523 (match_test "(unsigned HOST_WIDE_INT)
524 (- UINTVAL (op) + (mode == SImode ? 0x80000000 : 0x80008000))
525 < (unsigned HOST_WIDE_INT) 0x100000000ll")
526 (match_operand 0 "gpc_reg_operand")))
528 ;; Return 1 if op is any 32-bit unsigned constant integer
529 ;; or non-special register.
530 (define_predicate "reg_or_logical_cint_operand"
531 (if_then_else (match_code "const_int")
532 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
534 || ((INTVAL (op) & GET_MODE_MASK (mode)
535 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)")
536 (match_operand 0 "gpc_reg_operand")))
538 ;; Like reg_or_logical_cint_operand, but allow vsx registers
539 (define_predicate "vsx_reg_or_cint_operand"
540 (ior (match_operand 0 "vsx_register_operand")
541 (match_operand 0 "reg_or_logical_cint_operand")))
543 ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register
544 ;; with no more than one instruction per word.
545 (define_predicate "easy_fp_constant"
546 (match_code "const_double")
548 gcc_assert (GET_MODE (op) == mode && SCALAR_FLOAT_MODE_P (mode));
550 /* Consider all constants with -msoft-float to be easy when regs are
551 32-bit and thus can be loaded with a maximum of 2 insns. For
552 64-bit avoid long dependent insn sequences. */
553 if (TARGET_SOFT_FLOAT)
555 if (!TARGET_POWERPC64)
558 int size = GET_MODE_SIZE (mode);
562 int load_from_mem_insns = 2;
564 load_from_mem_insns++;
565 if (TARGET_CMODEL != CMODEL_SMALL)
566 load_from_mem_insns++;
567 if (num_insns_constant (op, mode) <= load_from_mem_insns)
571 /* 0.0D is not all zero bits. */
572 if (DECIMAL_FLOAT_MODE_P (mode))
575 /* The constant 0.0 is easy under VSX. */
576 if (TARGET_VSX && op == CONST0_RTX (mode))
579 /* Otherwise consider floating point constants hard, so that the
580 constant gets pushed to memory during the early RTL phases. This
581 has the advantage that double precision constants that can be
582 represented in single precision without a loss of precision will
583 use single precision loads. */
587 ;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB
588 ;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
590 (define_predicate "xxspltib_constant_split"
591 (match_code "const_vector,vec_duplicate,const_int")
596 if (!xxspltib_constant_p (op, mode, &num_insns, &value))
599 return num_insns > 1;
603 ;; Return 1 if the operand is constant that can loaded directly with a XXSPLTIB
606 (define_predicate "xxspltib_constant_nosplit"
607 (match_code "const_vector,vec_duplicate,const_int")
612 if (!xxspltib_constant_p (op, mode, &num_insns, &value))
615 return num_insns == 1;
618 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
619 ;; vector register without using memory.
620 (define_predicate "easy_vector_constant"
621 (match_code "const_vector")
623 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
628 if (zero_constant (op, mode) || all_ones_constant (op, mode))
632 && xxspltib_constant_p (op, mode, &num_insns, &value))
635 return easy_altivec_constant (op, mode);
641 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
642 (define_predicate "easy_vector_constant_add_self"
643 (and (match_code "const_vector")
644 (and (match_test "TARGET_ALTIVEC")
645 (match_test "easy_altivec_constant (op, mode)")))
649 if (mode == V2DImode || mode == V2DFmode)
651 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0;
652 val = const_vector_elt_as_int (op, elt);
653 val = ((val & 0xff) ^ 0x80) - 0x80;
654 return EASY_VECTOR_15_ADD_SELF (val);
657 ;; Same as easy_vector_constant but only for EASY_VECTOR_MSB.
658 (define_predicate "easy_vector_constant_msb"
659 (and (match_code "const_vector")
660 (and (match_test "TARGET_ALTIVEC")
661 (match_test "easy_altivec_constant (op, mode)")))
665 if (mode == V2DImode || mode == V2DFmode)
667 elt = BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 : 0;
668 val = const_vector_elt_as_int (op, elt);
669 return EASY_VECTOR_MSB (val, GET_MODE_INNER (mode));
672 ;; Return true if this is an easy altivec constant that we form
674 (define_predicate "easy_vector_constant_vsldoi"
675 (and (match_code "const_vector")
676 (and (match_test "TARGET_ALTIVEC")
677 (and (match_test "easy_altivec_constant (op, mode)")
678 (match_test "vspltis_shifted (op) != 0")))))
680 ;; Return 1 if operand is a vector int register or is either a vector constant
681 ;; of all 0 bits of a vector constant of all 1 bits.
682 (define_predicate "vector_int_reg_or_same_bit"
683 (match_code "reg,subreg,const_vector")
685 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
688 else if (REG_P (op) || SUBREG_P (op))
689 return vint_operand (op, mode);
692 return op == CONST0_RTX (mode) || op == CONSTM1_RTX (mode);
695 ;; Return 1 if operand is 0.0.
696 (define_predicate "zero_fp_constant"
697 (and (match_code "const_double")
698 (match_test "SCALAR_FLOAT_MODE_P (mode)
699 && op == CONST0_RTX (mode)")))
701 ;; Return 1 if the operand is in volatile memory. Note that during the
702 ;; RTL generation phase, memory_operand does not return TRUE for volatile
703 ;; memory references. So this function allows us to recognize volatile
704 ;; references where it's safe.
705 (define_predicate "volatile_mem_operand"
706 (and (match_code "mem")
707 (match_test "MEM_VOLATILE_P (op)")
708 (if_then_else (match_test "reload_completed")
709 (match_operand 0 "memory_operand")
710 (match_test "memory_address_p (mode, XEXP (op, 0))"))))
712 ;; Return 1 if the operand is a volatile or non-volatile memory operand.
713 (define_predicate "any_memory_operand"
714 (ior (match_operand 0 "memory_operand")
715 (match_operand 0 "volatile_mem_operand")))
717 ;; Return 1 if the operand is an offsettable memory operand.
718 (define_predicate "offsettable_mem_operand"
719 (and (match_operand 0 "any_memory_operand")
720 (match_test "offsettable_nonstrict_memref_p (op)")))
722 ;; Return 1 if the operand is a simple offsettable memory operand
723 ;; that does not include pre-increment, post-increment, etc.
724 (define_predicate "simple_offsettable_mem_operand"
725 (match_operand 0 "offsettable_mem_operand")
727 rtx addr = XEXP (op, 0);
729 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
732 if (!CONSTANT_P (XEXP (addr, 1)))
735 return base_reg_operand (XEXP (addr, 0), Pmode);
738 ;; Return 1 if the operand is suitable for load/store quad memory.
739 ;; This predicate only checks for non-atomic loads/stores (not lqarx/stqcx).
740 (define_predicate "quad_memory_operand"
743 if (!TARGET_QUAD_MEMORY && !TARGET_SYNC_TI)
746 if (GET_MODE_SIZE (mode) != 16 || !MEM_P (op) || MEM_ALIGN (op) < 128)
749 return quad_address_p (XEXP (op, 0), mode, false);
752 ;; Return 1 if the operand is suitable for load/store to vector registers with
753 ;; d-form addressing (register+offset), which was added in ISA 3.0.
754 ;; Unlike quad_memory_operand, we do not have to check for alignment.
755 (define_predicate "vsx_quad_dform_memory_operand"
758 if (!TARGET_P9_VECTOR || !MEM_P (op) || GET_MODE_SIZE (mode) != 16)
761 return quad_address_p (XEXP (op, 0), mode, false);
764 ;; Return 1 if the operand is an indexed or indirect memory operand.
765 (define_predicate "indexed_or_indirect_operand"
769 if (VECTOR_MEM_ALTIVEC_P (mode)
770 && GET_CODE (op) == AND
771 && CONST_INT_P (XEXP (op, 1))
772 && INTVAL (XEXP (op, 1)) == -16)
775 return indexed_or_indirect_address (op, mode);
778 ;; Like indexed_or_indirect_operand, but also allow a GPR register if direct
779 ;; moves are supported.
780 (define_predicate "reg_or_indexed_operand"
781 (match_code "mem,reg,subreg")
784 return indexed_or_indirect_operand (op, mode);
785 else if (TARGET_DIRECT_MOVE)
786 return register_operand (op, mode);
791 ;; Return 1 if the operand is an indexed or indirect memory operand with an
792 ;; AND -16 in it, used to recognize when we need to switch to Altivec loads
793 ;; to realign loops instead of VSX (altivec silently ignores the bottom bits,
794 ;; while VSX uses the full address and traps)
795 (define_predicate "altivec_indexed_or_indirect_operand"
799 if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
800 && GET_CODE (op) == AND
801 && CONST_INT_P (XEXP (op, 1))
802 && INTVAL (XEXP (op, 1)) == -16)
803 return indexed_or_indirect_address (XEXP (op, 0), mode);
808 ;; Return 1 if the operand is an indexed or indirect address.
809 (define_special_predicate "indexed_or_indirect_address"
810 (and (match_test "REG_P (op)
811 || (GET_CODE (op) == PLUS
812 /* Omit testing REG_P (XEXP (op, 0)). */
813 && REG_P (XEXP (op, 1)))")
814 (match_operand 0 "address_operand")))
816 ;; Return 1 if the operand is an index-form address.
817 (define_special_predicate "indexed_address"
818 (match_test "(GET_CODE (op) == PLUS
819 && REG_P (XEXP (op, 0))
820 && REG_P (XEXP (op, 1)))"))
822 ;; Return 1 if the operand is a MEM with an update-form address. This may
823 ;; also include update-indexed form.
824 (define_special_predicate "update_address_mem"
825 (match_test "(MEM_P (op)
826 && (GET_CODE (XEXP (op, 0)) == PRE_INC
827 || GET_CODE (XEXP (op, 0)) == PRE_DEC
828 || GET_CODE (XEXP (op, 0)) == PRE_MODIFY))"))
830 ;; Return 1 if the operand is a MEM with an indexed-form address.
831 (define_special_predicate "indexed_address_mem"
832 (match_test "(MEM_P (op)
833 && (indexed_address (XEXP (op, 0), mode)
834 || (GET_CODE (XEXP (op, 0)) == PRE_MODIFY
835 && indexed_address (XEXP (XEXP (op, 0), 1), mode))))"))
837 ;; Return 1 if the operand is either a non-special register or can be used
838 ;; as the operand of a `mode' add insn.
839 (define_predicate "add_operand"
840 (if_then_else (match_code "const_int")
841 (match_test "satisfies_constraint_I (op)
842 || satisfies_constraint_L (op)
843 || satisfies_constraint_eI (op)")
844 (match_operand 0 "gpc_reg_operand")))
846 ;; Return 1 if the operand is either a non-special register, or 0, or -1.
847 (define_predicate "adde_operand"
848 (if_then_else (match_code "const_int")
849 (match_test "INTVAL (op) == 0 || INTVAL (op) == -1")
850 (match_operand 0 "gpc_reg_operand")))
852 ;; Return 1 if OP is a constant but not a valid add_operand.
853 (define_predicate "non_add_cint_operand"
854 (and (match_code "const_int")
855 (not (match_operand 0 "add_operand"))))
857 ;; Return 1 if the operand is a constant that can be used as the operand
858 ;; of an AND, OR or XOR.
859 (define_predicate "logical_const_operand"
860 (match_code "const_int")
864 opl = INTVAL (op) & GET_MODE_MASK (mode);
866 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
867 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
870 ;; Return 1 if the operand is a non-special register or a constant that
871 ;; can be used as the operand of an AND, OR or XOR.
872 (define_predicate "logical_operand"
873 (ior (match_operand 0 "gpc_reg_operand")
874 (match_operand 0 "logical_const_operand")))
876 ;; Return 1 if op is a constant that is not a logical operand, but could
877 ;; be split into one.
878 (define_predicate "non_logical_cint_operand"
879 (and (match_code "const_int,const_wide_int")
880 (and (not (match_operand 0 "logical_operand"))
881 (match_operand 0 "reg_or_logical_cint_operand"))))
883 ;; Return 1 if the operand is either a non-special register or a
884 ;; constant that can be used as the operand of a logical AND.
885 (define_predicate "and_operand"
886 (ior (and (match_code "const_int")
887 (match_test "rs6000_is_valid_and_mask (op, mode)"))
888 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
889 (match_operand 0 "gpc_reg_operand")
890 (match_operand 0 "logical_operand"))))
892 ;; Return 1 if the operand is either a logical operand or a short cint operand.
893 (define_predicate "scc_eq_operand"
894 (ior (match_operand 0 "logical_operand")
895 (match_operand 0 "short_cint_operand")))
897 ;; Return 1 if the operand is a general non-special register or memory operand.
898 (define_predicate "reg_or_mem_operand"
899 (ior (match_operand 0 "gpc_reg_operand")
900 (match_operand 0 "any_memory_operand")
901 (and (match_code "mem")
902 (match_test "macho_lo_sum_memory_operand (op, mode)"))))
904 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
905 (define_predicate "zero_reg_mem_operand"
906 (ior (and (match_test "TARGET_VSX")
907 (match_operand 0 "zero_fp_constant"))
908 (match_operand 0 "reg_or_mem_operand")))
910 ;; Return 1 if the operand is a CONST_INT and it is the element for 64-bit
911 ;; data types inside of a vector that scalar instructions operate on
912 (define_predicate "vsx_scalar_64bit"
913 (match_code "const_int")
915 return (INTVAL (op) == VECTOR_ELEMENT_SCALAR_64BIT);
918 ;; Return 1 if the operand is a general register or memory operand without
919 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
921 (define_predicate "lwa_operand"
922 (match_code "reg,subreg,mem")
924 rtx inner, addr, offset;
927 if (reload_completed && SUBREG_P (inner))
928 inner = SUBREG_REG (inner);
930 if (gpc_reg_operand (inner, mode))
932 if (!any_memory_operand (inner, mode))
935 addr = XEXP (inner, 0);
937 /* The LWA instruction uses the DS-form instruction format which requires
938 that the bottom two bits of the offset must be 0. The prefixed PLWA does
939 not have this restriction. While the actual load from memory is 32-bits,
940 we pass in DImode here to test for using a DS instruction. */
941 if (address_is_prefixed (addr, DImode, NON_PREFIXED_DS))
944 if (GET_CODE (addr) == PRE_INC
945 || GET_CODE (addr) == PRE_DEC
946 || (GET_CODE (addr) == PRE_MODIFY
947 && !legitimate_indexed_address_p (XEXP (addr, 1), 0)))
949 if (GET_CODE (addr) == LO_SUM
950 && REG_P (XEXP (addr, 0))
951 && GET_CODE (XEXP (addr, 1)) == CONST)
952 addr = XEXP (XEXP (addr, 1), 0);
953 if (GET_CODE (addr) != PLUS)
955 offset = XEXP (addr, 1);
956 if (!CONST_INT_P (offset))
958 return INTVAL (offset) % 4 == 0;
961 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
962 (define_predicate "symbol_ref_operand"
963 (and (match_code "symbol_ref")
964 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
965 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
967 ;; Return 1 if op is an operand that can be loaded via the GOT.
968 ;; or non-special register register field no cr0
969 (define_predicate "got_operand"
970 (match_code "symbol_ref,const,label_ref"))
972 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
973 ;; excluding labels involving addition.
974 (define_predicate "got_no_const_operand"
975 (match_code "symbol_ref,label_ref"))
977 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
978 (define_predicate "rs6000_tls_symbol_ref"
979 (and (match_code "symbol_ref")
980 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
982 ;; Return 1 for the CONST_INT or UNSPEC second CALL operand.
983 ;; Prevents unwanted substitution of the unspec got_reg arg.
984 (define_predicate "unspec_tls"
985 (match_code "const_int,unspec")
987 if (CONST_INT_P (op))
989 if (XINT (op, 1) == UNSPEC_TLSGD)
990 return REG_P (XVECEXP (op, 0, 1)) || XVECEXP (op, 0, 1) == const0_rtx;
991 if (XINT (op, 1) == UNSPEC_TLSLD)
992 return REG_P (XVECEXP (op, 0, 0)) || XVECEXP (op, 0, 0) == const0_rtx;
996 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
997 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
998 (define_predicate "call_operand"
999 (if_then_else (match_code "reg")
1000 (match_test "REGNO (op) == LR_REGNO
1001 || REGNO (op) == CTR_REGNO
1002 || !HARD_REGISTER_P (op)")
1003 (match_code "symbol_ref")))
1005 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
1006 ;; to an indirect CALL. This is LR, CTR, or a PLTSEQ unspec using CTR.
1007 (define_predicate "indirect_call_operand"
1008 (match_code "reg,unspec")
1011 return (REGNO (op) == LR_REGNO
1012 || REGNO (op) == CTR_REGNO);
1013 if (GET_CODE (op) == UNSPEC)
1015 if (XINT (op, 1) != UNSPEC_PLTSEQ)
1017 op = XVECEXP (op, 0, 0);
1018 return REG_P (op) && REGNO (op) == CTR_REGNO;
1023 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
1025 (define_predicate "current_file_function_operand"
1026 (and (match_code "symbol_ref")
1027 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
1028 && (SYMBOL_REF_LOCAL_P (op)
1029 || (op == XEXP (DECL_RTL (current_function_decl), 0)
1030 && !decl_replaceable_p (current_function_decl)))
1031 && !((DEFAULT_ABI == ABI_AIX
1032 || DEFAULT_ABI == ABI_ELFv2)
1033 && (SYMBOL_REF_EXTERNAL_P (op)
1034 || SYMBOL_REF_WEAK (op)))")))
1036 ;; Return 1 if this operand is a valid input for a move insn.
1037 (define_predicate "input_operand"
1038 (match_code "symbol_ref,const,reg,subreg,mem,
1039 const_double,const_wide_int,const_vector,const_int")
1041 /* Memory is always valid. */
1042 if (any_memory_operand (op, mode))
1045 /* For floating-point, easy constants are valid. */
1046 if (SCALAR_FLOAT_MODE_P (mode)
1047 && easy_fp_constant (op, mode))
1050 /* Allow any integer constant. */
1051 if (SCALAR_INT_MODE_P (mode) && CONST_SCALAR_INT_P (op))
1054 /* Allow easy vector constants. */
1055 if (GET_CODE (op) == CONST_VECTOR
1056 && easy_vector_constant (op, mode))
1059 /* For floating-point or multi-word mode, the only remaining valid type
1061 if (SCALAR_FLOAT_MODE_P (mode)
1062 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1063 return register_operand (op, mode);
1065 /* We don't allow moving the carry bit around. */
1066 if (ca_operand (op, mode))
1069 /* The only cases left are integral modes one word or smaller (we
1070 do not get called for MODE_CC values). These can be in any
1072 if (register_operand (op, mode))
1075 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
1077 if (DEFAULT_ABI == ABI_V4
1078 && (SYMBOL_REF_P (op) || GET_CODE (op) == CONST)
1079 && small_data_operand (op, Pmode))
1085 ;; Return 1 if this operand is a valid input for a vsx_splat insn.
1086 (define_predicate "splat_input_operand"
1087 (match_code "reg,subreg,mem")
1093 else if (mode == DImode)
1095 else if (mode == SImode && TARGET_P9_VECTOR)
1097 else if (mode == SFmode && TARGET_P9_VECTOR)
1104 rtx addr = XEXP (op, 0);
1106 if (! volatile_ok && MEM_VOLATILE_P (op))
1109 if (lra_in_progress || reload_completed)
1110 return indexed_or_indirect_address (addr, vmode);
1112 return memory_address_addr_space_p (vmode, addr, MEM_ADDR_SPACE (op));
1114 return gpc_reg_operand (op, mode);
1117 ;; Return true if operand is an operator used in rotate-and-mask instructions.
1118 (define_predicate "rotate_mask_operator"
1119 (match_code "rotate,ashift,lshiftrt"))
1121 ;; Return true if operand is boolean operator.
1122 (define_predicate "boolean_operator"
1123 (match_code "and,ior,xor"))
1125 ;; Return true if operand is OR-form of boolean operator.
1126 (define_predicate "boolean_or_operator"
1127 (match_code "ior,xor"))
1129 ;; Return true if operand is an equality operator.
1130 (define_special_predicate "equality_operator"
1131 (match_code "eq,ne"))
1133 ;; Return 1 if OP is a comparison operation that is valid for a branch
1134 ;; instruction. We check the opcode against the mode of the CC value.
1135 ;; validate_condition_mode is an assertion.
1136 (define_predicate "branch_comparison_operator"
1137 (and (match_operand 0 "comparison_operator")
1138 (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
1139 (if_then_else (match_test "GET_MODE (XEXP (op, 0)) == CCFPmode
1140 && !flag_finite_math_only")
1141 (match_code "lt,gt,eq,unordered,unge,unle,ne,ordered")
1142 (match_code "lt,ltu,le,leu,gt,gtu,ge,geu,eq,ne"))
1143 (match_test "validate_condition_mode (GET_CODE (op),
1144 GET_MODE (XEXP (op, 0))),
1147 ;; Return 1 if OP is a comparison that needs an extra instruction to do (a
1148 ;; crlogical or an extra branch).
1149 (define_predicate "extra_insn_branch_comparison_operator"
1150 (and (match_operand 0 "comparison_operator")
1151 (match_test "GET_MODE (XEXP (op, 0)) == CCFPmode")
1152 (match_code "ltgt,le,ge,unlt,ungt,uneq")
1153 (match_test "validate_condition_mode (GET_CODE (op),
1154 GET_MODE (XEXP (op, 0))),
1157 ;; Return 1 if OP is an unsigned comparison operator.
1158 (define_predicate "unsigned_comparison_operator"
1159 (match_code "ltu,gtu,leu,geu"))
1161 ;; Return 1 if OP is a signed comparison operator.
1162 (define_predicate "signed_comparison_operator"
1163 (match_code "lt,gt,le,ge"))
1165 ;; Return 1 if OP is a signed comparison or an equality operator.
1166 (define_predicate "signed_or_equality_comparison_operator"
1167 (ior (match_operand 0 "equality_operator")
1168 (match_operand 0 "signed_comparison_operator")))
1170 ;; Return 1 if OP is an unsigned comparison or an equality operator.
1171 (define_predicate "unsigned_or_equality_comparison_operator"
1172 (ior (match_operand 0 "equality_operator")
1173 (match_operand 0 "unsigned_comparison_operator")))
1175 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
1176 ;; it must be a positive comparison.
1177 (define_predicate "scc_comparison_operator"
1178 (and (match_operand 0 "branch_comparison_operator")
1179 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1181 ;; Return 1 if OP is a comparison operation whose inverse would be valid for
1183 (define_predicate "scc_rev_comparison_operator"
1184 (and (match_operand 0 "branch_comparison_operator")
1185 (match_code "ne,le,ge,leu,geu,ordered")))
1187 ;; Return 1 if OP is a comparison operator suitable for floating point
1188 ;; vector/scalar comparisons that generate a -1/0 mask.
1189 (define_predicate "fpmask_comparison_operator"
1190 (match_code "eq,gt,ge"))
1192 ;; Return 1 if OP is a comparison operator suitable for vector/scalar
1193 ;; comparisons that generate a 0/-1 mask (i.e. the inverse of
1194 ;; fpmask_comparison_operator).
1195 (define_predicate "invert_fpmask_comparison_operator"
1196 (match_code "ne,unlt,unle"))
1198 ;; Return 1 if OP is a comparison operation suitable for integer vector/scalar
1199 ;; comparisons that generate a -1/0 mask.
1200 (define_predicate "vecint_comparison_operator"
1201 (match_code "eq,gt,gtu"))
1203 ;; Return 1 if OP is a comparison operation that is valid for a branch
1204 ;; insn, which is true if the corresponding bit in the CC register is set.
1205 (define_predicate "branch_positive_comparison_operator"
1206 (and (match_operand 0 "branch_comparison_operator")
1207 (match_code "eq,lt,gt,ltu,gtu,unordered")))
1209 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
1211 (define_predicate "save_world_operation"
1212 (match_code "parallel")
1217 int count = XVECLEN (op, 0);
1223 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1224 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1227 for (i=1; i <= 18; i++)
1229 elt = XVECEXP (op, 0, index++);
1230 if (GET_CODE (elt) != SET
1231 || !MEM_P (SET_DEST (elt))
1232 || !memory_operand (SET_DEST (elt), DFmode)
1233 || !REG_P (SET_SRC (elt))
1234 || GET_MODE (SET_SRC (elt)) != DFmode)
1238 for (i=1; i <= 12; i++)
1240 elt = XVECEXP (op, 0, index++);
1241 if (GET_CODE (elt) != SET
1242 || !MEM_P (SET_DEST (elt))
1243 || !REG_P (SET_SRC (elt))
1244 || GET_MODE (SET_SRC (elt)) != V4SImode)
1248 for (i=1; i <= 19; i++)
1250 elt = XVECEXP (op, 0, index++);
1251 if (GET_CODE (elt) != SET
1252 || !MEM_P (SET_DEST (elt))
1253 || !memory_operand (SET_DEST (elt), Pmode)
1254 || !REG_P (SET_SRC (elt))
1255 || GET_MODE (SET_SRC (elt)) != Pmode)
1259 elt = XVECEXP (op, 0, index++);
1260 if (GET_CODE (elt) != SET
1261 || !MEM_P (SET_DEST (elt))
1262 || !memory_operand (SET_DEST (elt), Pmode)
1263 || !REG_P (SET_SRC (elt))
1264 || REGNO (SET_SRC (elt)) != CR2_REGNO
1265 || GET_MODE (SET_SRC (elt)) != Pmode)
1268 if (GET_CODE (XVECEXP (op, 0, index++)) != SET
1269 || GET_CODE (XVECEXP (op, 0, index++)) != SET)
1274 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
1276 (define_predicate "restore_world_operation"
1277 (match_code "parallel")
1282 int count = XVECLEN (op, 0);
1288 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
1289 || GET_CODE (XVECEXP (op, 0, index++)) != USE
1290 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
1293 elt = XVECEXP (op, 0, index++);
1294 if (GET_CODE (elt) != SET
1295 || !MEM_P (SET_SRC (elt))
1296 || !memory_operand (SET_SRC (elt), Pmode)
1297 || !REG_P (SET_DEST (elt))
1298 || REGNO (SET_DEST (elt)) != CR2_REGNO
1299 || GET_MODE (SET_DEST (elt)) != Pmode)
1302 for (i=1; i <= 19; i++)
1304 elt = XVECEXP (op, 0, index++);
1305 if (GET_CODE (elt) != SET
1306 || !MEM_P (SET_SRC (elt))
1307 || !memory_operand (SET_SRC (elt), Pmode)
1308 || !REG_P (SET_DEST (elt))
1309 || GET_MODE (SET_DEST (elt)) != Pmode)
1313 for (i=1; i <= 12; i++)
1315 elt = XVECEXP (op, 0, index++);
1316 if (GET_CODE (elt) != SET
1317 || !MEM_P (SET_SRC (elt))
1318 || !REG_P (SET_DEST (elt))
1319 || GET_MODE (SET_DEST (elt)) != V4SImode)
1323 for (i=1; i <= 18; i++)
1325 elt = XVECEXP (op, 0, index++);
1326 if (GET_CODE (elt) != SET
1327 || !MEM_P (SET_SRC (elt))
1328 || !memory_operand (SET_SRC (elt), DFmode)
1329 || !REG_P (SET_DEST (elt))
1330 || GET_MODE (SET_DEST (elt)) != DFmode)
1334 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1335 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1336 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1337 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1338 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1343 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1344 (define_predicate "vrsave_operation"
1345 (match_code "parallel")
1347 int count = XVECLEN (op, 0);
1348 unsigned int dest_regno, src_regno;
1352 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1353 || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
1354 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1355 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1358 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1359 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1361 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1364 for (i = 1; i < count; i++)
1366 rtx elt = XVECEXP (op, 0, i);
1368 if (GET_CODE (elt) != CLOBBER
1369 && GET_CODE (elt) != SET)
1376 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1377 (define_predicate "mfcr_operation"
1378 (match_code "parallel")
1380 int count = XVECLEN (op, 0);
1383 /* Perform a quick check so we don't blow up below. */
1385 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1386 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1387 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1390 for (i = 0; i < count; i++)
1392 rtx exp = XVECEXP (op, 0, i);
1397 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1399 if (!REG_P (src_reg)
1400 || GET_MODE (src_reg) != CCmode
1401 || ! CR_REGNO_P (REGNO (src_reg)))
1404 if (GET_CODE (exp) != SET
1405 || !REG_P (SET_DEST (exp))
1406 || GET_MODE (SET_DEST (exp)) != SImode
1407 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1409 unspec = SET_SRC (exp);
1410 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1412 if (GET_CODE (unspec) != UNSPEC
1413 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1414 || XVECLEN (unspec, 0) != 2
1415 || XVECEXP (unspec, 0, 0) != src_reg
1416 || !CONST_INT_P (XVECEXP (unspec, 0, 1))
1417 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1423 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1424 (define_predicate "mtcrf_operation"
1425 (match_code "parallel")
1427 int count = XVECLEN (op, 0);
1431 /* Perform a quick check so we don't blow up below. */
1433 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1434 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1435 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1437 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1439 if (!REG_P (src_reg)
1440 || GET_MODE (src_reg) != SImode
1441 || ! INT_REGNO_P (REGNO (src_reg)))
1444 for (i = 0; i < count; i++)
1446 rtx exp = XVECEXP (op, 0, i);
1450 if (GET_CODE (exp) != SET
1451 || !REG_P (SET_DEST (exp))
1452 || GET_MODE (SET_DEST (exp)) != CCmode
1453 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1455 unspec = SET_SRC (exp);
1456 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1458 if (GET_CODE (unspec) != UNSPEC
1459 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1460 || XVECLEN (unspec, 0) != 2
1461 || XVECEXP (unspec, 0, 0) != src_reg
1462 || !CONST_INT_P (XVECEXP (unspec, 0, 1))
1463 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1469 ;; Return 1 if OP is valid for crsave insn, known to be a PARALLEL.
1470 (define_predicate "crsave_operation"
1471 (match_code "parallel")
1473 int count = XVECLEN (op, 0);
1476 for (i = 1; i < count; i++)
1478 rtx exp = XVECEXP (op, 0, i);
1480 if (GET_CODE (exp) != USE
1481 || !REG_P (XEXP (exp, 0))
1482 || GET_MODE (XEXP (exp, 0)) != CCmode
1483 || ! CR_REGNO_P (REGNO (XEXP (exp, 0))))
1489 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1490 (define_predicate "lmw_operation"
1491 (match_code "parallel")
1493 int count = XVECLEN (op, 0);
1494 unsigned int dest_regno;
1496 unsigned int base_regno;
1497 HOST_WIDE_INT offset;
1500 /* Perform a quick check so we don't blow up below. */
1502 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1503 || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
1504 || !MEM_P (SET_SRC (XVECEXP (op, 0, 0))))
1507 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1508 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1511 || count != 32 - (int) dest_regno)
1514 if (legitimate_indirect_address_p (src_addr, 0))
1517 base_regno = REGNO (src_addr);
1518 if (base_regno == 0)
1521 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, false, false))
1523 offset = INTVAL (XEXP (src_addr, 1));
1524 base_regno = REGNO (XEXP (src_addr, 0));
1529 for (i = 0; i < count; i++)
1531 rtx elt = XVECEXP (op, 0, i);
1534 HOST_WIDE_INT newoffset;
1536 if (GET_CODE (elt) != SET
1537 || !REG_P (SET_DEST (elt))
1538 || GET_MODE (SET_DEST (elt)) != SImode
1539 || REGNO (SET_DEST (elt)) != dest_regno + i
1540 || !MEM_P (SET_SRC (elt))
1541 || GET_MODE (SET_SRC (elt)) != SImode)
1543 newaddr = XEXP (SET_SRC (elt), 0);
1544 if (legitimate_indirect_address_p (newaddr, 0))
1549 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1551 addr_reg = XEXP (newaddr, 0);
1552 newoffset = INTVAL (XEXP (newaddr, 1));
1556 if (REGNO (addr_reg) != base_regno
1557 || newoffset != offset + 4 * i)
1564 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1565 (define_predicate "stmw_operation"
1566 (match_code "parallel")
1568 int count = XVECLEN (op, 0);
1569 unsigned int src_regno;
1571 unsigned int base_regno;
1572 HOST_WIDE_INT offset;
1575 /* Perform a quick check so we don't blow up below. */
1577 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1578 || !MEM_P (SET_DEST (XVECEXP (op, 0, 0)))
1579 || !REG_P (SET_SRC (XVECEXP (op, 0, 0))))
1582 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1583 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1586 || count != 32 - (int) src_regno)
1589 if (legitimate_indirect_address_p (dest_addr, 0))
1592 base_regno = REGNO (dest_addr);
1593 if (base_regno == 0)
1596 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, false, false))
1598 offset = INTVAL (XEXP (dest_addr, 1));
1599 base_regno = REGNO (XEXP (dest_addr, 0));
1604 for (i = 0; i < count; i++)
1606 rtx elt = XVECEXP (op, 0, i);
1609 HOST_WIDE_INT newoffset;
1611 if (GET_CODE (elt) != SET
1612 || !REG_P (SET_SRC (elt))
1613 || GET_MODE (SET_SRC (elt)) != SImode
1614 || REGNO (SET_SRC (elt)) != src_regno + i
1615 || !MEM_P (SET_DEST (elt))
1616 || GET_MODE (SET_DEST (elt)) != SImode)
1618 newaddr = XEXP (SET_DEST (elt), 0);
1619 if (legitimate_indirect_address_p (newaddr, 0))
1624 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, false, false))
1626 addr_reg = XEXP (newaddr, 0);
1627 newoffset = INTVAL (XEXP (newaddr, 1));
1631 if (REGNO (addr_reg) != base_regno
1632 || newoffset != offset + 4 * i)
1639 ;; Return 1 if OP is a stack tie operand.
1640 (define_predicate "tie_operand"
1641 (match_code "parallel")
1643 return (GET_CODE (XVECEXP (op, 0, 0)) == SET
1644 && MEM_P (XEXP (XVECEXP (op, 0, 0), 0))
1645 && GET_MODE (XEXP (XVECEXP (op, 0, 0), 0)) == BLKmode
1646 && XEXP (XVECEXP (op, 0, 0), 1) == const0_rtx);
1649 ;; Match a small code model toc reference (or medium and large
1650 ;; model toc references before reload).
1651 (define_predicate "small_toc_ref"
1652 (match_code "unspec,plus")
1654 if (GET_CODE (op) == PLUS && add_cint_operand (XEXP (op, 1), mode))
1657 return GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_TOCREL;
1661 ;; Match the first insn (addis) in fusing the combination of addis and loads to
1662 ;; GPR registers on power8.
1663 (define_predicate "fusion_gpr_addis"
1664 (match_code "const_int,high,plus")
1666 HOST_WIDE_INT value;
1669 if (GET_CODE (op) == HIGH)
1672 if (CONST_INT_P (op))
1675 else if (GET_CODE (op) == PLUS
1676 && base_reg_operand (XEXP (op, 0), Pmode)
1677 && CONST_INT_P (XEXP (op, 1)))
1678 int_const = XEXP (op, 1);
1683 value = INTVAL (int_const);
1684 if ((value & (HOST_WIDE_INT)0xffff) != 0)
1687 if ((value & (HOST_WIDE_INT)0xffff0000) == 0)
1690 /* Power8 only does the fusion if the top 12 bits of the addis value are all
1692 return (IN_RANGE (value >> 16, -16, 15));
1695 ;; Match the second insn (lbz, lhz, lwz, ld) in fusing the combination of addis
1696 ;; and loads to GPR registers on power8.
1697 (define_predicate "fusion_gpr_mem_load"
1698 (match_code "mem,sign_extend,zero_extend")
1700 rtx addr, base, offset;
1702 /* Handle sign/zero extend. */
1703 if (GET_CODE (op) == ZERO_EXTEND
1704 || (TARGET_P8_FUSION_SIGN && GET_CODE (op) == SIGN_EXTEND))
1707 mode = GET_MODE (op);
1721 if (!TARGET_POWERPC64)
1725 /* Do not allow SF/DFmode in GPR fusion. While the loads do occur, they
1731 addr = XEXP (op, 0);
1732 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1735 base = XEXP (addr, 0);
1736 if (!base_reg_operand (base, GET_MODE (base)))
1739 offset = XEXP (addr, 1);
1741 if (GET_CODE (addr) == PLUS)
1742 return satisfies_constraint_I (offset);
1744 else if (GET_CODE (addr) == LO_SUM)
1746 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1747 return small_toc_ref (offset, GET_MODE (offset));
1749 else if (TARGET_ELF && !TARGET_POWERPC64)
1750 return CONSTANT_P (offset);
1756 ;; Match a GPR load (lbz, lhz, lwz, ld) that uses a combined address in the
1757 ;; memory field with both the addis and the memory offset. Sign extension
1758 ;; is not handled here, since lha and lwa are not fused.
1759 (define_predicate "fusion_addis_mem_combo_load"
1760 (match_code "mem,zero_extend")
1762 rtx addr, base, offset;
1764 /* Handle zero extend. */
1765 if (GET_CODE (op) == ZERO_EXTEND)
1768 mode = GET_MODE (op);
1781 /* Do not fuse 64-bit DImode in 32-bit since it splits into two
1782 separate instructions. */
1784 if (!TARGET_POWERPC64)
1788 /* Do not allow SF/DFmode in GPR fusion. While the loads do occur, they
1794 addr = XEXP (op, 0);
1795 if (GET_CODE (addr) != PLUS && GET_CODE (addr) != LO_SUM)
1798 base = XEXP (addr, 0);
1799 if (!fusion_gpr_addis (base, GET_MODE (base)))
1802 offset = XEXP (addr, 1);
1803 if (GET_CODE (addr) == PLUS)
1804 return satisfies_constraint_I (offset);
1806 else if (GET_CODE (addr) == LO_SUM)
1808 if (TARGET_XCOFF || (TARGET_ELF && TARGET_POWERPC64))
1809 return small_toc_ref (offset, GET_MODE (offset));
1811 else if (TARGET_ELF && !TARGET_POWERPC64)
1812 return CONSTANT_P (offset);
1819 ;; Return true if the operand is a PC-relative address of a local symbol or a
1820 ;; label that can be used directly in a memory operation.
1821 (define_predicate "pcrel_local_address"
1822 (match_code "label_ref,symbol_ref,const")
1824 enum insn_form iform = address_to_insn_form (op, mode, NON_PREFIXED_DEFAULT);
1825 return iform == INSN_FORM_PCREL_LOCAL;
1828 ;; Return true if the operand is a PC-relative external symbol whose address
1829 ;; can be loaded into a register.
1830 (define_predicate "pcrel_external_address"
1831 (match_code "symbol_ref,const")
1833 enum insn_form iform = address_to_insn_form (op, mode, NON_PREFIXED_DEFAULT);
1834 return iform == INSN_FORM_PCREL_EXTERNAL;
1837 ;; Return true if the address is PC-relative and the symbol is either local or
1839 (define_predicate "pcrel_local_or_external_address"
1840 (ior (match_operand 0 "pcrel_local_address")
1841 (match_operand 0 "pcrel_external_address")))
1843 ;; Return true if the operand is a memory address that uses a prefixed address.
1844 (define_predicate "prefixed_memory"
1847 return address_is_prefixed (XEXP (op, 0), mode, NON_PREFIXED_DEFAULT);