| blob | acd5c4764ee9a27519b5c9c03fa6914ae03cd4cd |
1 ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2 ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 ;; This file is part of GNU CC.
8 ;; GNU CC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; any later version.
13 ;; GNU CC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GNU CC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
21 ;; Boston, MA 02111-1307, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; `unspec' values used in rs6000.md:
26 ;; Number Use
27 ;; 0 frsp for POWER machines
28 ;; 0/v blockage
29 ;; 5 used to tie the stack contents and the stack pointer
30 ;; 6 address of a word pointing to the TOC
31 ;; 7 address of the TOC (more-or-less)
32 ;; 8 movsi_got
33 ;; 9/v eh_reg_restore
34 ;; 10 fctiwz
35 ;; 15 load_macho_picbase
36 ;; 16 macho_correct_pic
37 ;; 19 movesi_from_cr
38 ;; 20 movesi_to_cr
39 ;; 21 cntlz{w,d}2 count lead zero word/double word
40 \f
41 ;; Define an insn type attribute. This is used in function unit delay
42 ;; computations.
43 (define_attr "type" "integer,load,store,fpload,fpstore,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,branch,compare,cr_logical,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,vecsimple,veccomplex,veccmp,vecperm,vecfloat"
44 (const_string "integer"))
46 ;; Length (in bytes).
47 ; '(pc)' in the following doesn't include the instruction itself; it is
48 ; calculated as if the instruction had zero size.
49 (define_attr "length" ""
50 (if_then_else (eq_attr "type" "branch")
51 (if_then_else (and (ge (minus (match_dup 0) (pc))
52 (const_int -32768))
53 (lt (minus (match_dup 0) (pc))
54 (const_int 32764)))
55 (const_int 4)
56 (const_int 8))
57 (const_int 4)))
59 ;; Processor type -- this attribute must exactly match the processor_type
60 ;; enumeration in rs6000.h.
62 (define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4"
63 (const (symbol_ref "rs6000_cpu_attr")))
65 ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
66 ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
68 ; Load/Store Unit -- pure PowerPC only
69 ; (POWER and 601 use Integer Unit)
70 (define_function_unit "lsu" 1 0
71 (and (eq_attr "type" "load")
72 (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400"))
73 2 1)
75 (define_function_unit "lsu" 1 0
76 (and (eq_attr "type" "load,vecload")
77 (eq_attr "cpu" "ppc7450"))
78 3 1)
80 (define_function_unit "lsu" 1 0
81 (and (eq_attr "type" "store,fpstore")
82 (eq_attr "cpu" "rs64a,mpccore,ppc603,ppc604,ppc604e,ppc620,ppc630"))
83 1 1)
85 (define_function_unit "lsu" 1 0
86 (and (eq_attr "type" "store,fpstore")
87 (eq_attr "cpu" "ppc750,ppc7400"))
88 2 1)
90 (define_function_unit "lsu" 1 0
91 (and (eq_attr "type" "store,vecstore")
92 (eq_attr "cpu" "ppc7450"))
93 3 1)
95 (define_function_unit "lsu" 1 0
96 (and (eq_attr "type" "fpstore")
97 (eq_attr "cpu" "ppc7450"))
98 3 3)
100 (define_function_unit "lsu" 1 0
101 (and (eq_attr "type" "fpload")
102 (eq_attr "cpu" "mpccore,ppc603,ppc750,ppc7400"))
103 2 1)
105 (define_function_unit "lsu" 1 0
106 (and (eq_attr "type" "fpload")
107 (eq_attr "cpu" "ppc7450"))
108 4 1)
110 (define_function_unit "lsu" 1 0
111 (and (eq_attr "type" "fpload")
112 (eq_attr "cpu" "rs64a,ppc604,ppc604e,ppc620,ppc630"))
113 3 1)
115 (define_function_unit "iu" 1 0
116 (and (eq_attr "type" "load")
117 (eq_attr "cpu" "rios1,ppc403,ppc405,ppc601"))
118 2 1)
120 (define_function_unit "iu" 1 0
121 (and (eq_attr "type" "store,fpstore")
122 (eq_attr "cpu" "rios1,ppc403,ppc405,ppc601"))
123 1 1)
125 (define_function_unit "fpu" 1 0
126 (and (eq_attr "type" "fpstore")
127 (eq_attr "cpu" "rios1,ppc601"))
128 0 1)
130 (define_function_unit "iu" 1 0
131 (and (eq_attr "type" "fpload")
132 (eq_attr "cpu" "rios1"))
133 2 1)
135 (define_function_unit "iu" 1 0
136 (and (eq_attr "type" "fpload")
137 (eq_attr "cpu" "ppc601"))
138 3 1)
140 (define_function_unit "iu2" 2 0
141 (and (eq_attr "type" "load,fpload")
142 (eq_attr "cpu" "rios2"))
143 2 1)
145 (define_function_unit "iu2" 2 0
146 (and (eq_attr "type" "store,fpstore")
147 (eq_attr "cpu" "rios2"))
148 1 1)
150 ; Integer Unit (RIOS1, PPC601, PPC603, RS64a)
151 (define_function_unit "iu" 1 0
152 (and (eq_attr "type" "integer")
153 (eq_attr "cpu" "rios1,rs64a,mpccore,ppc403,ppc405,ppc601,ppc603"))
154 1 1)
156 (define_function_unit "iu" 1 0
157 (and (eq_attr "type" "cr_logical")
158 (eq_attr "cpu" "mpccore,ppc403,ppc405,ppc601"))
159 1 1)
161 (define_function_unit "iu" 1 0
162 (and (eq_attr "type" "imul,imul2,imul3")
163 (eq_attr "cpu" "ppc403"))
164 4 4)
166 (define_function_unit "iu" 1 0
167 (and (eq_attr "type" "imul")
168 (eq_attr "cpu" "ppc405"))
169 4 3)
171 (define_function_unit "iu" 1 0
172 (and (eq_attr "type" "imul2,imul3")
173 (eq_attr "cpu" "ppc405"))
174 3 2)
176 (define_function_unit "iu" 1 0
177 (and (eq_attr "type" "imul")
178 (eq_attr "cpu" "rios1"))
179 5 5)
181 (define_function_unit "iu" 1 0
182 (and (eq_attr "type" "imul2")
183 (eq_attr "cpu" "rios1"))
184 4 4)
186 (define_function_unit "iu" 1 0
187 (and (eq_attr "type" "imul3")
188 (eq_attr "cpu" "rios1"))
189 3 3)
191 (define_function_unit "iu" 1 0
192 (and (eq_attr "type" "imul,imul2,imul3")
193 (eq_attr "cpu" "ppc601,ppc603"))
194 5 5)
196 (define_function_unit "iu" 1 0
197 (and (eq_attr "type" "imul")
198 (eq_attr "cpu" "rs64a"))
199 20 20)
201 (define_function_unit "iu" 1 0
202 (and (eq_attr "type" "imul2")
203 (eq_attr "cpu" "rs64a"))
204 12 12)
206 (define_function_unit "iu" 1 0
207 (and (eq_attr "type" "imul3")
208 (eq_attr "cpu" "rs64a"))
209 8 8)
211 (define_function_unit "iu" 1 0
212 (and (eq_attr "type" "lmul")
213 (eq_attr "cpu" "rs64a"))
214 34 34)
216 (define_function_unit "iu" 1 0
217 (and (eq_attr "type" "idiv")
218 (eq_attr "cpu" "rios1"))
219 19 19)
221 (define_function_unit "iu" 1 0
222 (and (eq_attr "type" "idiv")
223 (eq_attr "cpu" "rs64a"))
224 66 66)
226 (define_function_unit "iu" 1 0
227 (and (eq_attr "type" "ldiv")
228 (eq_attr "cpu" "rs64a"))
229 66 66)
231 (define_function_unit "iu" 1 0
232 (and (eq_attr "type" "idiv")
233 (eq_attr "cpu" "ppc403"))
234 33 33)
236 (define_function_unit "iu" 1 0
237 (and (eq_attr "type" "idiv")
238 (eq_attr "cpu" "ppc405"))
239 35 35)
241 (define_function_unit "iu" 1 0
242 (and (eq_attr "type" "idiv")
243 (eq_attr "cpu" "ppc601"))
244 36 36)
246 (define_function_unit "iu" 1 0
247 (and (eq_attr "type" "idiv")
248 (eq_attr "cpu" "ppc603"))
249 37 36)
251 ; RIOS2 has two integer units: a primary one which can perform all
252 ; operations and a secondary one which is fed in lock step with the first
253 ; and can perform "simple" integer operations.
254 ; To catch this we define a 'dummy' imuldiv-unit that is also needed
255 ; for the complex insns.
256 (define_function_unit "iu2" 2 0
257 (and (eq_attr "type" "integer")
258 (eq_attr "cpu" "rios2"))
259 1 1)
261 (define_function_unit "iu2" 2 0
262 (and (eq_attr "type" "imul,imul2,imul3")
263 (eq_attr "cpu" "rios2"))
264 2 2)
266 (define_function_unit "iu2" 2 0
267 (and (eq_attr "type" "idiv")
268 (eq_attr "cpu" "rios2"))
269 13 13)
271 (define_function_unit "imuldiv" 1 0
272 (and (eq_attr "type" "imul,imul2,imul3")
273 (eq_attr "cpu" "rios2"))
274 2 2)
276 (define_function_unit "imuldiv" 1 0
277 (and (eq_attr "type" "idiv")
278 (eq_attr "cpu" "rios2"))
279 13 13)
281 ; MPCCORE has separate IMUL/IDIV unit for multicycle instructions
282 ; Divide latency varies greatly from 2-11, use 6 as average
283 (define_function_unit "imuldiv" 1 0
284 (and (eq_attr "type" "imul,imul2,imul3")
285 (eq_attr "cpu" "mpccore"))
286 2 1)
288 (define_function_unit "imuldiv" 1 0
289 (and (eq_attr "type" "idiv")
290 (eq_attr "cpu" "mpccore"))
291 6 6)
293 ; PPC604{,e} has two units that perform integer operations
294 ; and one unit for divide/multiply operations (and move
295 ; from/to spr).
296 (define_function_unit "iu2" 2 0
297 (and (eq_attr "type" "integer")
298 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
299 1 1)
301 (define_function_unit "imuldiv" 1 0
302 (and (eq_attr "type" "imul,imul2,imul3")
303 (eq_attr "cpu" "ppc604"))
304 4 2)
306 (define_function_unit "imuldiv" 1 0
307 (and (eq_attr "type" "imul,imul2,imul3")
308 (eq_attr "cpu" "ppc604e"))
309 2 1)
311 (define_function_unit "imuldiv" 1 0
312 (and (eq_attr "type" "imul")
313 (eq_attr "cpu" "ppc620,ppc630"))
314 5 3)
316 (define_function_unit "imuldiv" 1 0
317 (and (eq_attr "type" "imul2")
318 (eq_attr "cpu" "ppc620,ppc630"))
319 4 3)
321 (define_function_unit "imuldiv" 1 0
322 (and (eq_attr "type" "imul3")
323 (eq_attr "cpu" "ppc620,ppc630"))
324 3 3)
326 (define_function_unit "imuldiv" 1 0
327 (and (eq_attr "type" "lmul")
328 (eq_attr "cpu" "ppc620,ppc630"))
329 7 5)
331 (define_function_unit "imuldiv" 1 0
332 (and (eq_attr "type" "idiv")
333 (eq_attr "cpu" "ppc604,ppc604e"))
334 20 19)
336 (define_function_unit "imuldiv" 1 0
337 (and (eq_attr "type" "idiv")
338 (eq_attr "cpu" "ppc620"))
339 37 36)
341 (define_function_unit "imuldiv" 1 0
342 (and (eq_attr "type" "idiv")
343 (eq_attr "cpu" "ppc630"))
344 21 20)
346 (define_function_unit "imuldiv" 1 0
347 (and (eq_attr "type" "ldiv")
348 (eq_attr "cpu" "ppc620,ppc630"))
349 37 36)
351 ; PPC7450 has 3 integer units (for most integer insns) and one mul/div
352 ; unit, which also does CR-logical insns and move to/from SPR.
353 ; It also has 4 vector units, one for each type of vector instruction.
354 ; However, we can only dispatch 2 instructions per cycle.
355 ; We model this as saying that dispatching two of the same type of instruction
356 ; in a row incurs a single cycle delay.
357 (define_function_unit "iu3" 3 0
358 (and (eq_attr "type" "integer")
359 (eq_attr "cpu" "ppc7450"))
360 1 1)
362 (define_function_unit "imuldiv" 1 0
363 (and (eq_attr "type" "imul")
364 (eq_attr "cpu" "ppc7450"))
365 4 2)
367 (define_function_unit "imuldiv" 1 0
368 (and (eq_attr "type" "imul2,imul3")
369 (eq_attr "cpu" "ppc7450"))
370 3 1)
372 (define_function_unit "imuldiv" 1 0
373 (and (eq_attr "type" "idiv")
374 (eq_attr "cpu" "ppc7450"))
375 23 23)
377 (define_function_unit "imuldiv" 1 0
378 (and (eq_attr "type" "cr_logical")
379 (eq_attr "cpu" "ppc7450"))
380 1 1)
382 (define_function_unit "vec_alu2" 2 0
383 (and (eq_attr "type" "vecsimple")
384 (eq_attr "cpu" "ppc7450"))
385 1 2 [(eq_attr "type" "vecsimple")])
387 (define_function_unit "vec_alu2" 2 0
388 (and (eq_attr "type" "vecsimple")
389 (eq_attr "cpu" "ppc7450"))
390 1 1 [(eq_attr "type" "!vecsimple")])
392 (define_function_unit "vec_alu2" 2 0
393 (and (eq_attr "type" "veccomplex")
394 (eq_attr "cpu" "ppc7450"))
395 4 2 [(eq_attr "type" "veccomplex")])
397 (define_function_unit "vec_alu2" 2 0
398 (and (eq_attr "type" "veccomplex")
399 (eq_attr "cpu" "ppc7450"))
400 4 1 [(eq_attr "type" "!veccomplex")])
402 (define_function_unit "vec_alu2" 2 0
403 (and (eq_attr "type" "veccmp")
404 (eq_attr "cpu" "ppc7450"))
405 2 2 [(eq_attr "type" "veccmp")])
407 (define_function_unit "vec_alu2" 2 0
408 (and (eq_attr "type" "veccmp")
409 (eq_attr "cpu" "ppc7450"))
410 2 1 [(eq_attr "type" "!veccmp")])
412 (define_function_unit "vec_alu2" 2 0
413 (and (eq_attr "type" "vecfloat")
414 (eq_attr "cpu" "ppc7450"))
415 4 2 [(eq_attr "type" "vecfloat")])
417 (define_function_unit "vec_alu2" 2 0
418 (and (eq_attr "type" "vecfloat")
419 (eq_attr "cpu" "ppc7450"))
420 4 1 [(eq_attr "type" "!vecfloat")])
422 (define_function_unit "vec_alu2" 2 0
423 (and (eq_attr "type" "vecperm")
424 (eq_attr "cpu" "ppc7450"))
425 2 2 [(eq_attr "type" "vecperm")])
427 (define_function_unit "vec_alu2" 2 0
428 (and (eq_attr "type" "vecperm")
429 (eq_attr "cpu" "ppc7450"))
430 2 1 [(eq_attr "type" "!vecperm")])
432 ; PPC750 has two integer units: a primary one which can perform all
433 ; operations and a secondary one which is fed in lock step with the first
434 ; and can perform "simple" integer operations.
435 ; To catch this we define a 'dummy' imuldiv-unit that is also needed
436 ; for the complex insns.
437 (define_function_unit "iu2" 2 0
438 (and (eq_attr "type" "integer")
439 (eq_attr "cpu" "ppc750,ppc7400"))
440 1 1)
442 (define_function_unit "iu2" 2 0
443 (and (eq_attr "type" "imul")
444 (eq_attr "cpu" "ppc750,ppc7400"))
445 4 4)
447 (define_function_unit "iu2" 2 0
448 (and (eq_attr "type" "imul2")
449 (eq_attr "cpu" "ppc750,ppc7400"))
450 3 2)
452 (define_function_unit "iu2" 2 0
453 (and (eq_attr "type" "imul3")
454 (eq_attr "cpu" "ppc750,ppc7400"))
455 2 1)
457 (define_function_unit "iu2" 2 0
458 (and (eq_attr "type" "idiv")
459 (eq_attr "cpu" "ppc750,ppc7400"))
460 19 19)
462 (define_function_unit "imuldiv" 1 0
463 (and (eq_attr "type" "imul")
464 (eq_attr "cpu" "ppc750,ppc7400"))
465 4 4)
467 (define_function_unit "imuldiv" 1 0
468 (and (eq_attr "type" "imul2")
469 (eq_attr "cpu" "ppc750,ppc7400"))
470 3 2)
472 (define_function_unit "imuldiv" 1 0
473 (and (eq_attr "type" "imul3")
474 (eq_attr "cpu" "ppc750,ppc7400"))
475 2 1)
477 (define_function_unit "imuldiv" 1 0
478 (and (eq_attr "type" "idiv")
479 (eq_attr "cpu" "ppc750,ppc7400"))
480 19 19)
482 ; CR-logical operations are execute-serialized, that is they don't
483 ; start (and block the function unit) until all preceding operations
484 ; have finished. They don't block dispatch of other insns, though.
485 ; I've imitated this by giving them longer latency.
486 (define_function_unit "sru" 1 0
487 (and (eq_attr "type" "cr_logical")
488 (eq_attr "cpu" "ppc603,ppc750,ppc7400"))
489 3 2)
491 ; compare is done on integer unit, but feeds insns which
492 ; execute on the branch unit.
493 (define_function_unit "iu" 1 0
494 (and (eq_attr "type" "compare")
495 (eq_attr "cpu" "rios1"))
496 4 1)
498 (define_function_unit "iu" 1 0
499 (and (eq_attr "type" "delayed_compare")
500 (eq_attr "cpu" "rios1"))
501 5 1)
503 (define_function_unit "iu" 1 0
504 (and (eq_attr "type" "compare,delayed_compare")
505 (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc601,ppc603"))
506 3 1)
508 ; some extra cycles added by TARGET_SCHED_ADJUST_COST between compare
509 ; and a following branch, to reduce mispredicts
510 (define_function_unit "iu3" 3 0
511 (and (eq_attr "type" "compare,delayed_compare")
512 (eq_attr "cpu" "ppc7450"))
513 1 1)
515 (define_function_unit "iu2" 2 0
516 (and (eq_attr "type" "compare,delayed_compare")
517 (eq_attr "cpu" "rios2"))
518 3 1)
520 (define_function_unit "iu2" 2 0
521 (and (eq_attr "type" "compare,delayed_compare")
522 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400"))
523 1 1)
525 ; fp compare uses fp unit
526 (define_function_unit "fpu" 1 0
527 (and (eq_attr "type" "fpcompare")
528 (eq_attr "cpu" "rios1"))
529 9 1)
531 ; rios1 and rios2 have different fpcompare delays
532 (define_function_unit "fpu2" 2 0
533 (and (eq_attr "type" "fpcompare")
534 (eq_attr "cpu" "rios2,ppc630"))
535 5 1)
537 ; on ppc601 and ppc603, fpcompare takes also 2 cycles from
538 ; the integer unit
539 ; here we do not define delays, just occupy the unit. The dependencies
540 ; will be assigned by the fpcompare definition in the fpu.
541 (define_function_unit "iu" 1 0
542 (and (eq_attr "type" "fpcompare")
543 (eq_attr "cpu" "ppc601,ppc603"))
544 0 2)
546 ; fp compare uses fp unit
547 (define_function_unit "fpu" 1 0
548 (and (eq_attr "type" "fpcompare")
549 (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620"))
550 5 1)
552 (define_function_unit "fpu" 1 0
553 (and (eq_attr "type" "fpcompare")
554 (eq_attr "cpu" "ppc750,ppc7400,ppc7450"))
555 3 1)
557 (define_function_unit "fpu" 1 0
558 (and (eq_attr "type" "fpcompare")
559 (eq_attr "cpu" "mpccore"))
560 1 1)
562 (define_function_unit "bpu" 1 0
563 (and (eq_attr "type" "mtjmpr")
564 (eq_attr "cpu" "rios1,rios2,rs64a"))
565 5 1)
567 (define_function_unit "bpu" 1 0
568 (and (eq_attr "type" "mtjmpr")
569 (eq_attr "cpu" "mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630"))
570 4 1)
572 (define_function_unit "sru" 1 0
573 (and (eq_attr "type" "mtjmpr")
574 (eq_attr "cpu" "ppc750,ppc7400"))
575 2 2)
577 (define_function_unit "imuldiv" 1 0
578 (and (eq_attr "type" "mtjmpr")
579 (eq_attr "cpu" "ppc7450"))
580 2 2)
582 (define_function_unit "bpu" 1 0
583 (and (eq_attr "type" "cr_logical")
584 (eq_attr "cpu" "rios1,rios2,ppc604"))
585 4 1)
587 (define_function_unit "cru" 1 0
588 (and (eq_attr "type" "cr_logical")
589 (eq_attr "cpu" "ppc604e,ppc620,ppc630,rs64a"))
590 1 1)
592 ; all jumps/branches are executing on the bpu, in 1 cycle, for all machines.
593 (define_function_unit "bpu" 1 0
594 (eq_attr "type" "jmpreg")
595 1 1)
597 (define_function_unit "bpu" 1 0
598 (eq_attr "type" "branch")
599 1 1)
601 ; Floating Point Unit
602 (define_function_unit "fpu" 1 0
603 (and (eq_attr "type" "fp,dmul")
604 (eq_attr "cpu" "rios1"))
605 2 1)
607 (define_function_unit "fpu" 1 0
608 (and (eq_attr "type" "fp")
609 (eq_attr "cpu" "rs64a,mpccore"))
610 4 2)
612 (define_function_unit "fpu" 1 0
613 (and (eq_attr "type" "fp")
614 (eq_attr "cpu" "ppc601"))
615 4 1)
617 (define_function_unit "fpu" 1 0
618 (and (eq_attr "type" "fp")
619 (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620,ppc750,ppc7400"))
620 3 1)
622 (define_function_unit "fpu" 1 0
623 (and (eq_attr "type" "fp,dmul")
624 (eq_attr "cpu" "ppc7450"))
625 5 1)
627 (define_function_unit "fpu" 1 0
628 (and (eq_attr "type" "dmul")
629 (eq_attr "cpu" "rs64a"))
630 7 2)
632 (define_function_unit "fpu" 1 0
633 (and (eq_attr "type" "dmul")
634 (eq_attr "cpu" "mpccore"))
635 5 5)
637 (define_function_unit "fpu" 1 0
638 (and (eq_attr "type" "dmul")
639 (eq_attr "cpu" "ppc601"))
640 5 2)
642 ; is this true?
643 (define_function_unit "fpu" 1 0
644 (and (eq_attr "type" "dmul")
645 (eq_attr "cpu" "ppc603,ppc750"))
646 4 2)
648 (define_function_unit "fpu" 1 0
649 (and (eq_attr "type" "dmul")
650 (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc7400"))
651 3 1)
653 (define_function_unit "fpu" 1 0
654 (and (eq_attr "type" "sdiv,ddiv")
655 (eq_attr "cpu" "rios1"))
656 19 19)
658 (define_function_unit "fpu" 1 0
659 (and (eq_attr "type" "sdiv")
660 (eq_attr "cpu" "rs64a"))
661 31 31)
663 (define_function_unit "fpu" 1 0
664 (and (eq_attr "type" "sdiv")
665 (eq_attr "cpu" "ppc601,ppc750,ppc7400"))
666 17 17)
668 (define_function_unit "fpu" 1 0
669 (and (eq_attr "type" "sdiv")
670 (eq_attr "cpu" "ppc7450"))
671 21 21)
673 (define_function_unit "fpu" 1 0
674 (and (eq_attr "type" "sdiv")
675 (eq_attr "cpu" "mpccore"))
676 10 10)
678 (define_function_unit "fpu" 1 0
679 (and (eq_attr "type" "sdiv")
680 (eq_attr "cpu" "ppc603,ppc604,ppc604e,ppc620"))
681 18 18)
683 (define_function_unit "fpu" 1 0
684 (and (eq_attr "type" "ddiv")
685 (eq_attr "cpu" "mpccore"))
686 17 17)
688 (define_function_unit "fpu" 1 0
689 (and (eq_attr "type" "ddiv")
690 (eq_attr "cpu" "rs64a,ppc601,ppc750,ppc604,ppc604e,ppc620,ppc7400"))
691 31 31)
693 (define_function_unit "fpu" 1 0
694 (and (eq_attr "type" "ddiv")
695 (eq_attr "cpu" "ppc7450"))
696 35 35)
698 (define_function_unit "fpu" 1 0
699 (and (eq_attr "type" "ddiv")
700 (eq_attr "cpu" "ppc603"))
701 33 33)
703 (define_function_unit "fpu" 1 0
704 (and (eq_attr "type" "ssqrt")
705 (eq_attr "cpu" "ppc620"))
706 31 31)
708 (define_function_unit "fpu" 1 0
709 (and (eq_attr "type" "dsqrt")
710 (eq_attr "cpu" "ppc620"))
711 31 31)
713 ; RIOS2 has two symmetric FPUs.
714 (define_function_unit "fpu2" 2 0
715 (and (eq_attr "type" "fp,dmul")
716 (eq_attr "cpu" "rios2"))
717 2 1)
719 (define_function_unit "fpu2" 2 0
720 (and (eq_attr "type" "fp,dmul")
721 (eq_attr "cpu" "ppc630"))
722 3 1)
724 (define_function_unit "fpu2" 2 0
725 (and (eq_attr "type" "sdiv,ddiv")
726 (eq_attr "cpu" "rios2"))
727 17 17)
729 (define_function_unit "fpu2" 2 0
730 (and (eq_attr "type" "sdiv")
731 (eq_attr "cpu" "ppc630"))
732 17 17)
734 (define_function_unit "fpu2" 2 0
735 (and (eq_attr "type" "ddiv")
736 (eq_attr "cpu" "ppc630"))
737 21 21)
739 (define_function_unit "fpu2" 2 0
740 (and (eq_attr "type" "ssqrt,dsqrt")
741 (eq_attr "cpu" "rios2"))
742 26 26)
744 (define_function_unit "fpu2" 2 0
745 (and (eq_attr "type" "ssqrt")
746 (eq_attr "cpu" "ppc630"))
747 18 18)
749 (define_function_unit "fpu2" 2 0
750 (and (eq_attr "type" "dsqrt")
751 (eq_attr "cpu" "ppc630"))
752 26 26)
754 ;; Power4
755 (define_function_unit "lsu2" 2 0
756 (and (eq_attr "type" "load")
757 (eq_attr "cpu" "power4"))
758 3 1)
760 (define_function_unit "lsu2" 2 0
761 (and (eq_attr "type" "fpload")
762 (eq_attr "cpu" "power4"))
763 5 1)
765 (define_function_unit "lsu2" 2 0
766 (and (eq_attr "type" "store,fpstore")
767 (eq_attr "cpu" "power4"))
768 1 1)
770 (define_function_unit "iu2" 2 0
771 (and (eq_attr "type" "integer")
772 (eq_attr "cpu" "power4"))
773 2 1)
775 (define_function_unit "iu2" 2 0
776 (and (eq_attr "type" "imul,lmul")
777 (eq_attr "cpu" "power4"))
778 7 6)
780 (define_function_unit "iu2" 2 0
781 (and (eq_attr "type" "imul2")
782 (eq_attr "cpu" "power4"))
783 5 4)
785 (define_function_unit "iu2" 2 0
786 (and (eq_attr "type" "imul3")
787 (eq_attr "cpu" "power4"))
788 4 3)
790 (define_function_unit "iu2" 2 0
791 (and (eq_attr "type" "idiv")
792 (eq_attr "cpu" "power4"))
793 36 35)
795 (define_function_unit "iu2" 2 0
796 (and (eq_attr "type" "ldiv")
797 (eq_attr "cpu" "power4"))
798 68 67)
800 (define_function_unit "imuldiv" 1 0
801 (and (eq_attr "type" "idiv")
802 (eq_attr "cpu" "power4"))
803 36 35)
805 (define_function_unit "imuldiv" 1 0
806 (and (eq_attr "type" "ldiv")
807 (eq_attr "cpu" "power4"))
808 68 67)
810 (define_function_unit "iu2" 2 0
811 (and (eq_attr "type" "compare")
812 (eq_attr "cpu" "power4"))
813 3 1)
815 (define_function_unit "iu2" 2 0
816 (and (eq_attr "type" "delayed_compare")
817 (eq_attr "cpu" "power4"))
818 4 1)
820 (define_function_unit "bpu" 1 0
821 (and (eq_attr "type" "mtjmpr")
822 (eq_attr "cpu" "power4"))
823 3 1)
825 (define_function_unit "bpu" 1 0
826 (and (eq_attr "type" "jmpreg,branch")
827 (eq_attr "cpu" "power4"))
828 2 1)
830 (define_function_unit "cru" 1 0
831 (and (eq_attr "type" "cr_logical")
832 (eq_attr "cpu" "power4"))
833 4 1)
835 (define_function_unit "fpu2" 2 0
836 (and (eq_attr "type" "fp,dmul")
837 (eq_attr "cpu" "power4"))
838 6 1)
840 ; adjust_cost increases the cost of dependent branches,
841 ; so shave a few cycles off for fpcompare.
842 (define_function_unit "fpu2" 2 0
843 (and (eq_attr "type" "fpcompare")
844 (eq_attr "cpu" "power4"))
845 5 1)
847 (define_function_unit "fpu2" 2 0
848 (and (eq_attr "type" "sdiv,ddiv")
849 (eq_attr "cpu" "power4"))
850 33 28)
852 (define_function_unit "fpu2" 2 0
853 (and (eq_attr "type" "ssqrt,dsqrt")
854 (eq_attr "cpu" "power4"))
855 40 35)
857 \f
858 ;; Start with fixed-point load and store insns. Here we put only the more
859 ;; complex forms. Basic data transfer is done later.
861 (define_expand "zero_extendqidi2"
862 [(set (match_operand:DI 0 "gpc_reg_operand" "")
863 (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")))]
864 "TARGET_POWERPC64"
865 "")
867 (define_insn ""
868 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
869 (zero_extend:DI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
870 "TARGET_POWERPC64"
871 "@
872 lbz%U1%X1 %0,%1
873 rldicl %0,%1,0,56"
874 [(set_attr "type" "load,*")])
876 (define_insn ""
877 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
878 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
879 (const_int 0)))
880 (clobber (match_scratch:DI 2 "=r,r"))]
881 "TARGET_POWERPC64"
882 "@
883 rldicl. %2,%1,0,56
884 #"
885 [(set_attr "type" "compare")
886 (set_attr "length" "4,8")])
888 (define_split
889 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
890 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
891 (const_int 0)))
892 (clobber (match_scratch:DI 2 ""))]
893 "TARGET_POWERPC64 && reload_completed"
894 [(set (match_dup 2)
895 (zero_extend:DI (match_dup 1)))
896 (set (match_dup 0)
897 (compare:CC (match_dup 2)
898 (const_int 0)))]
899 "")
901 (define_insn ""
902 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
903 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
904 (const_int 0)))
905 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
906 (zero_extend:DI (match_dup 1)))]
907 "TARGET_POWERPC64"
908 "@
909 rldicl. %0,%1,0,56
910 #"
911 [(set_attr "type" "compare")
912 (set_attr "length" "4,8")])
914 (define_split
915 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
916 (compare:CC (zero_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
917 (const_int 0)))
918 (set (match_operand:DI 0 "gpc_reg_operand" "")
919 (zero_extend:DI (match_dup 1)))]
920 "TARGET_POWERPC64 && reload_completed"
921 [(set (match_dup 0)
922 (zero_extend:DI (match_dup 1)))
923 (set (match_dup 2)
924 (compare:CC (match_dup 0)
925 (const_int 0)))]
926 "")
928 (define_insn "extendqidi2"
929 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
930 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))]
931 "TARGET_POWERPC64"
932 "extsb %0,%1")
934 (define_insn ""
935 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
936 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
937 (const_int 0)))
938 (clobber (match_scratch:DI 2 "=r,r"))]
939 "TARGET_POWERPC64"
940 "@
941 extsb. %2,%1
942 #"
943 [(set_attr "type" "compare")
944 (set_attr "length" "4,8")])
946 (define_split
947 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
948 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
949 (const_int 0)))
950 (clobber (match_scratch:DI 2 ""))]
951 "TARGET_POWERPC64 && reload_completed"
952 [(set (match_dup 2)
953 (sign_extend:DI (match_dup 1)))
954 (set (match_dup 0)
955 (compare:CC (match_dup 2)
956 (const_int 0)))]
957 "")
959 (define_insn ""
960 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
961 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
962 (const_int 0)))
963 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
964 (sign_extend:DI (match_dup 1)))]
965 "TARGET_POWERPC64"
966 "@
967 extsb. %0,%1
968 #"
969 [(set_attr "type" "compare")
970 (set_attr "length" "4,8")])
972 (define_split
973 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
974 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" ""))
975 (const_int 0)))
976 (set (match_operand:DI 0 "gpc_reg_operand" "")
977 (sign_extend:DI (match_dup 1)))]
978 "TARGET_POWERPC64 && reload_completed"
979 [(set (match_dup 0)
980 (sign_extend:DI (match_dup 1)))
981 (set (match_dup 2)
982 (compare:CC (match_dup 0)
983 (const_int 0)))]
984 "")
986 (define_expand "zero_extendhidi2"
987 [(set (match_operand:DI 0 "gpc_reg_operand" "")
988 (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
989 "TARGET_POWERPC64"
990 "")
992 (define_insn ""
993 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
994 (zero_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
995 "TARGET_POWERPC64"
996 "@
997 lhz%U1%X1 %0,%1
998 rldicl %0,%1,0,48"
999 [(set_attr "type" "load,*")])
1001 (define_insn ""
1002 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1003 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1004 (const_int 0)))
1005 (clobber (match_scratch:DI 2 "=r,r"))]
1006 "TARGET_POWERPC64"
1007 "@
1008 rldicl. %2,%1,0,48
1009 #"
1010 [(set_attr "type" "compare")
1011 (set_attr "length" "4,8")])
1013 (define_split
1014 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1015 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
1016 (const_int 0)))
1017 (clobber (match_scratch:DI 2 ""))]
1018 "TARGET_POWERPC64 && reload_completed"
1019 [(set (match_dup 2)
1020 (zero_extend:DI (match_dup 1)))
1021 (set (match_dup 0)
1022 (compare:CC (match_dup 2)
1023 (const_int 0)))]
1024 "")
1026 (define_insn ""
1027 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1028 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1029 (const_int 0)))
1030 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
1031 (zero_extend:DI (match_dup 1)))]
1032 "TARGET_POWERPC64"
1033 "@
1034 rldicl. %0,%1,0,48
1035 #"
1036 [(set_attr "type" "compare")
1037 (set_attr "length" "4,8")])
1039 (define_split
1040 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1041 (compare:CC (zero_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
1042 (const_int 0)))
1043 (set (match_operand:DI 0 "gpc_reg_operand" "")
1044 (zero_extend:DI (match_dup 1)))]
1045 "TARGET_POWERPC64 && reload_completed"
1046 [(set (match_dup 0)
1047 (zero_extend:DI (match_dup 1)))
1048 (set (match_dup 2)
1049 (compare:CC (match_dup 0)
1050 (const_int 0)))]
1051 "")
1053 (define_expand "extendhidi2"
1054 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1055 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))]
1056 "TARGET_POWERPC64"
1057 "")
1059 (define_insn ""
1060 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
1061 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1062 "TARGET_POWERPC64"
1063 "@
1064 lha%U1%X1 %0,%1
1065 extsh %0,%1"
1066 [(set_attr "type" "load,*")])
1068 (define_insn ""
1069 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1070 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1071 (const_int 0)))
1072 (clobber (match_scratch:DI 2 "=r,r"))]
1073 "TARGET_POWERPC64"
1074 "@
1075 extsh. %2,%1
1076 #"
1077 [(set_attr "type" "compare")
1078 (set_attr "length" "4,8")])
1080 (define_split
1081 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1082 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
1083 (const_int 0)))
1084 (clobber (match_scratch:DI 2 ""))]
1085 "TARGET_POWERPC64 && reload_completed"
1086 [(set (match_dup 2)
1087 (sign_extend:DI (match_dup 1)))
1088 (set (match_dup 0)
1089 (compare:CC (match_dup 2)
1090 (const_int 0)))]
1091 "")
1093 (define_insn ""
1094 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1095 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1096 (const_int 0)))
1097 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
1098 (sign_extend:DI (match_dup 1)))]
1099 "TARGET_POWERPC64"
1100 "@
1101 extsh. %0,%1
1102 #"
1103 [(set_attr "type" "compare")
1104 (set_attr "length" "4,8")])
1106 (define_split
1107 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1108 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" ""))
1109 (const_int 0)))
1110 (set (match_operand:DI 0 "gpc_reg_operand" "")
1111 (sign_extend:DI (match_dup 1)))]
1112 "TARGET_POWERPC64 && reload_completed"
1113 [(set (match_dup 0)
1114 (sign_extend:DI (match_dup 1)))
1115 (set (match_dup 2)
1116 (compare:CC (match_dup 0)
1117 (const_int 0)))]
1118 "")
1120 (define_expand "zero_extendsidi2"
1121 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1122 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
1123 "TARGET_POWERPC64"
1124 "")
1126 (define_insn ""
1127 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
1128 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r")))]
1129 "TARGET_POWERPC64"
1130 "@
1131 lwz%U1%X1 %0,%1
1132 rldicl %0,%1,0,32"
1133 [(set_attr "type" "load,*")])
1135 (define_insn ""
1136 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1137 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1138 (const_int 0)))
1139 (clobber (match_scratch:DI 2 "=r,r"))]
1140 "TARGET_POWERPC64"
1141 "@
1142 rldicl. %2,%1,0,32
1143 #"
1144 [(set_attr "type" "compare")
1145 (set_attr "length" "4,8")])
1147 (define_split
1148 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1149 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
1150 (const_int 0)))
1151 (clobber (match_scratch:DI 2 ""))]
1152 "TARGET_POWERPC64 && reload_completed"
1153 [(set (match_dup 2)
1154 (zero_extend:DI (match_dup 1)))
1155 (set (match_dup 0)
1156 (compare:CC (match_dup 2)
1157 (const_int 0)))]
1158 "")
1160 (define_insn ""
1161 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1162 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1163 (const_int 0)))
1164 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
1165 (zero_extend:DI (match_dup 1)))]
1166 "TARGET_POWERPC64"
1167 "@
1168 rldicl. %0,%1,0,32
1169 #"
1170 [(set_attr "type" "compare")
1171 (set_attr "length" "4,8")])
1173 (define_split
1174 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1175 (compare:CC (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
1176 (const_int 0)))
1177 (set (match_operand:DI 0 "gpc_reg_operand" "")
1178 (zero_extend:DI (match_dup 1)))]
1179 "TARGET_POWERPC64 && reload_completed"
1180 [(set (match_dup 0)
1181 (zero_extend:DI (match_dup 1)))
1182 (set (match_dup 2)
1183 (compare:CC (match_dup 0)
1184 (const_int 0)))]
1185 "")
1187 (define_expand "extendsidi2"
1188 [(set (match_operand:DI 0 "gpc_reg_operand" "")
1189 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
1190 "TARGET_POWERPC64"
1191 "")
1193 (define_insn ""
1194 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
1195 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "m,r")))]
1196 "TARGET_POWERPC64"
1197 "@
1198 lwa%U1%X1 %0,%1
1199 extsw %0,%1"
1200 [(set_attr "type" "load,*")])
1202 (define_insn ""
1203 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1204 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1205 (const_int 0)))
1206 (clobber (match_scratch:DI 2 "=r,r"))]
1207 "TARGET_POWERPC64"
1208 "@
1209 extsw. %2,%1
1210 #"
1211 [(set_attr "type" "compare")
1212 (set_attr "length" "4,8")])
1214 (define_split
1215 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1216 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
1217 (const_int 0)))
1218 (clobber (match_scratch:DI 2 ""))]
1219 "TARGET_POWERPC64 && reload_completed"
1220 [(set (match_dup 2)
1221 (sign_extend:DI (match_dup 1)))
1222 (set (match_dup 0)
1223 (compare:CC (match_dup 2)
1224 (const_int 0)))]
1225 "")
1227 (define_insn ""
1228 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1229 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1230 (const_int 0)))
1231 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
1232 (sign_extend:DI (match_dup 1)))]
1233 "TARGET_POWERPC64"
1234 "@
1235 extsw. %0,%1
1236 #"
1237 [(set_attr "type" "compare")
1238 (set_attr "length" "4,8")])
1240 (define_split
1241 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1242 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
1243 (const_int 0)))
1244 (set (match_operand:DI 0 "gpc_reg_operand" "")
1245 (sign_extend:DI (match_dup 1)))]
1246 "TARGET_POWERPC64 && reload_completed"
1247 [(set (match_dup 0)
1248 (sign_extend:DI (match_dup 1)))
1249 (set (match_dup 2)
1250 (compare:CC (match_dup 0)
1251 (const_int 0)))]
1252 "")
1254 (define_expand "zero_extendqisi2"
1255 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1256 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
1257 ""
1258 "")
1260 (define_insn ""
1261 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1262 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
1263 ""
1264 "@
1265 lbz%U1%X1 %0,%1
1266 {rlinm|rlwinm} %0,%1,0,0xff"
1267 [(set_attr "type" "load,*")])
1269 (define_insn ""
1270 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1271 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1272 (const_int 0)))
1273 (clobber (match_scratch:SI 2 "=r,r"))]
1274 ""
1275 "@
1276 {andil.|andi.} %2,%1,0xff
1277 #"
1278 [(set_attr "type" "compare")
1279 (set_attr "length" "4,8")])
1281 (define_split
1282 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1283 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
1284 (const_int 0)))
1285 (clobber (match_scratch:SI 2 ""))]
1286 "reload_completed"
1287 [(set (match_dup 2)
1288 (zero_extend:SI (match_dup 1)))
1289 (set (match_dup 0)
1290 (compare:CC (match_dup 2)
1291 (const_int 0)))]
1292 "")
1294 (define_insn ""
1295 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1296 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1297 (const_int 0)))
1298 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1299 (zero_extend:SI (match_dup 1)))]
1300 ""
1301 "@
1302 {andil.|andi.} %0,%1,0xff
1303 #"
1304 [(set_attr "type" "compare")
1305 (set_attr "length" "4,8")])
1307 (define_split
1308 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1309 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
1310 (const_int 0)))
1311 (set (match_operand:SI 0 "gpc_reg_operand" "")
1312 (zero_extend:SI (match_dup 1)))]
1313 "reload_completed"
1314 [(set (match_dup 0)
1315 (zero_extend:SI (match_dup 1)))
1316 (set (match_dup 2)
1317 (compare:CC (match_dup 0)
1318 (const_int 0)))]
1319 "")
1321 (define_expand "extendqisi2"
1322 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
1323 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
1324 ""
1325 "
1326 {
1327 if (TARGET_POWERPC)
1328 emit_insn (gen_extendqisi2_ppc (operands[0], operands[1]));
1329 else if (TARGET_POWER)
1330 emit_insn (gen_extendqisi2_power (operands[0], operands[1]));
1331 else
1332 emit_insn (gen_extendqisi2_no_power (operands[0], operands[1]));
1333 DONE;
1334 }")
1336 (define_insn "extendqisi2_ppc"
1337 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1338 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))]
1339 "TARGET_POWERPC"
1340 "extsb %0,%1")
1342 (define_insn ""
1343 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1344 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1345 (const_int 0)))
1346 (clobber (match_scratch:SI 2 "=r,r"))]
1347 "TARGET_POWERPC"
1348 "@
1349 extsb. %2,%1
1350 #"
1351 [(set_attr "type" "compare")
1352 (set_attr "length" "4,8")])
1354 (define_split
1355 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1356 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
1357 (const_int 0)))
1358 (clobber (match_scratch:SI 2 ""))]
1359 "TARGET_POWERPC && reload_completed"
1360 [(set (match_dup 2)
1361 (sign_extend:SI (match_dup 1)))
1362 (set (match_dup 0)
1363 (compare:CC (match_dup 2)
1364 (const_int 0)))]
1365 "")
1367 (define_insn ""
1368 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1369 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1370 (const_int 0)))
1371 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1372 (sign_extend:SI (match_dup 1)))]
1373 "TARGET_POWERPC"
1374 "@
1375 extsb. %0,%1
1376 #"
1377 [(set_attr "type" "compare")
1378 (set_attr "length" "4,8")])
1380 (define_split
1381 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1382 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" ""))
1383 (const_int 0)))
1384 (set (match_operand:SI 0 "gpc_reg_operand" "")
1385 (sign_extend:SI (match_dup 1)))]
1386 "TARGET_POWERPC && reload_completed"
1387 [(set (match_dup 0)
1388 (sign_extend:SI (match_dup 1)))
1389 (set (match_dup 2)
1390 (compare:CC (match_dup 0)
1391 (const_int 0)))]
1392 "")
1394 (define_expand "extendqisi2_power"
1395 [(parallel [(set (match_dup 2)
1396 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1397 (const_int 24)))
1398 (clobber (scratch:SI))])
1399 (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
1400 (ashiftrt:SI (match_dup 2)
1401 (const_int 24)))
1402 (clobber (scratch:SI))])]
1403 "TARGET_POWER"
1404 "
1405 { operands[1] = gen_lowpart (SImode, operands[1]);
1406 operands[2] = gen_reg_rtx (SImode); }")
1408 (define_expand "extendqisi2_no_power"
1409 [(set (match_dup 2)
1410 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1411 (const_int 24)))
1412 (set (match_operand:SI 0 "gpc_reg_operand" "")
1413 (ashiftrt:SI (match_dup 2)
1414 (const_int 24)))]
1415 "! TARGET_POWER && ! TARGET_POWERPC"
1416 "
1417 { operands[1] = gen_lowpart (SImode, operands[1]);
1418 operands[2] = gen_reg_rtx (SImode); }")
1420 (define_expand "zero_extendqihi2"
1421 [(set (match_operand:HI 0 "gpc_reg_operand" "")
1422 (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
1423 ""
1424 "")
1426 (define_insn ""
1427 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1428 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
1429 ""
1430 "@
1431 lbz%U1%X1 %0,%1
1432 {rlinm|rlwinm} %0,%1,0,0xff"
1433 [(set_attr "type" "load,*")])
1435 (define_insn ""
1436 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1437 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1438 (const_int 0)))
1439 (clobber (match_scratch:HI 2 "=r,r"))]
1440 ""
1441 "@
1442 {andil.|andi.} %2,%1,0xff
1443 #"
1444 [(set_attr "type" "compare")
1445 (set_attr "length" "4,8")])
1447 (define_split
1448 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1449 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1450 (const_int 0)))
1451 (clobber (match_scratch:HI 2 ""))]
1452 "reload_completed"
1453 [(set (match_dup 2)
1454 (zero_extend:HI (match_dup 1)))
1455 (set (match_dup 0)
1456 (compare:CC (match_dup 2)
1457 (const_int 0)))]
1458 "")
1460 (define_insn ""
1461 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1462 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1463 (const_int 0)))
1464 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1465 (zero_extend:HI (match_dup 1)))]
1466 ""
1467 "@
1468 {andil.|andi.} %0,%1,0xff
1469 #"
1470 [(set_attr "type" "compare")
1471 (set_attr "length" "4,8")])
1473 (define_split
1474 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1475 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1476 (const_int 0)))
1477 (set (match_operand:HI 0 "gpc_reg_operand" "")
1478 (zero_extend:HI (match_dup 1)))]
1479 "reload_completed"
1480 [(set (match_dup 0)
1481 (zero_extend:HI (match_dup 1)))
1482 (set (match_dup 2)
1483 (compare:CC (match_dup 0)
1484 (const_int 0)))]
1485 "")
1487 (define_expand "extendqihi2"
1488 [(use (match_operand:HI 0 "gpc_reg_operand" ""))
1489 (use (match_operand:QI 1 "gpc_reg_operand" ""))]
1490 ""
1491 "
1492 {
1493 if (TARGET_POWERPC)
1494 emit_insn (gen_extendqihi2_ppc (operands[0], operands[1]));
1495 else if (TARGET_POWER)
1496 emit_insn (gen_extendqihi2_power (operands[0], operands[1]));
1497 else
1498 emit_insn (gen_extendqihi2_no_power (operands[0], operands[1]));
1499 DONE;
1500 }")
1502 (define_insn "extendqihi2_ppc"
1503 [(set (match_operand:HI 0 "gpc_reg_operand" "=r")
1504 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))]
1505 "TARGET_POWERPC"
1506 "extsb %0,%1")
1508 (define_insn ""
1509 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1510 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1511 (const_int 0)))
1512 (clobber (match_scratch:HI 2 "=r,r"))]
1513 "TARGET_POWERPC"
1514 "@
1515 extsb. %2,%1
1516 #"
1517 [(set_attr "type" "compare")
1518 (set_attr "length" "4,8")])
1520 (define_split
1521 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1522 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1523 (const_int 0)))
1524 (clobber (match_scratch:HI 2 ""))]
1525 "TARGET_POWERPC && reload_completed"
1526 [(set (match_dup 2)
1527 (sign_extend:HI (match_dup 1)))
1528 (set (match_dup 0)
1529 (compare:CC (match_dup 2)
1530 (const_int 0)))]
1531 "")
1533 (define_insn ""
1534 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1535 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r"))
1536 (const_int 0)))
1537 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
1538 (sign_extend:HI (match_dup 1)))]
1539 "TARGET_POWERPC"
1540 "@
1541 extsb. %0,%1
1542 #"
1543 [(set_attr "type" "compare")
1544 (set_attr "length" "4,8")])
1546 (define_split
1547 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1548 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" ""))
1549 (const_int 0)))
1550 (set (match_operand:HI 0 "gpc_reg_operand" "")
1551 (sign_extend:HI (match_dup 1)))]
1552 "TARGET_POWERPC && reload_completed"
1553 [(set (match_dup 0)
1554 (sign_extend:HI (match_dup 1)))
1555 (set (match_dup 2)
1556 (compare:CC (match_dup 0)
1557 (const_int 0)))]
1558 "")
1560 (define_expand "extendqihi2_power"
1561 [(parallel [(set (match_dup 2)
1562 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1563 (const_int 24)))
1564 (clobber (scratch:SI))])
1565 (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
1566 (ashiftrt:SI (match_dup 2)
1567 (const_int 24)))
1568 (clobber (scratch:SI))])]
1569 "TARGET_POWER"
1570 "
1571 { operands[0] = gen_lowpart (SImode, operands[0]);
1572 operands[1] = gen_lowpart (SImode, operands[1]);
1573 operands[2] = gen_reg_rtx (SImode); }")
1575 (define_expand "extendqihi2_no_power"
1576 [(set (match_dup 2)
1577 (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
1578 (const_int 24)))
1579 (set (match_operand:HI 0 "gpc_reg_operand" "")
1580 (ashiftrt:SI (match_dup 2)
1581 (const_int 24)))]
1582 "! TARGET_POWER && ! TARGET_POWERPC"
1583 "
1584 { operands[0] = gen_lowpart (SImode, operands[0]);
1585 operands[1] = gen_lowpart (SImode, operands[1]);
1586 operands[2] = gen_reg_rtx (SImode); }")
1588 (define_expand "zero_extendhisi2"
1589 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1590 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1591 ""
1592 "")
1594 (define_insn ""
1595 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1596 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1597 ""
1598 "@
1599 lhz%U1%X1 %0,%1
1600 {rlinm|rlwinm} %0,%1,0,0xffff"
1601 [(set_attr "type" "load,*")])
1603 (define_insn ""
1604 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1605 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1606 (const_int 0)))
1607 (clobber (match_scratch:SI 2 "=r,r"))]
1608 ""
1609 "@
1610 {andil.|andi.} %2,%1,0xffff
1611 #"
1612 [(set_attr "type" "compare")
1613 (set_attr "length" "4,8")])
1615 (define_split
1616 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1617 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1618 (const_int 0)))
1619 (clobber (match_scratch:SI 2 ""))]
1620 "reload_completed"
1621 [(set (match_dup 2)
1622 (zero_extend:SI (match_dup 1)))
1623 (set (match_dup 0)
1624 (compare:CC (match_dup 2)
1625 (const_int 0)))]
1626 "")
1628 (define_insn ""
1629 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1630 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1631 (const_int 0)))
1632 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1633 (zero_extend:SI (match_dup 1)))]
1634 ""
1635 "@
1636 {andil.|andi.} %0,%1,0xffff
1637 #"
1638 [(set_attr "type" "compare")
1639 (set_attr "length" "4,8")])
1641 (define_split
1642 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1643 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1644 (const_int 0)))
1645 (set (match_operand:SI 0 "gpc_reg_operand" "")
1646 (zero_extend:SI (match_dup 1)))]
1647 "reload_completed"
1648 [(set (match_dup 0)
1649 (zero_extend:SI (match_dup 1)))
1650 (set (match_dup 2)
1651 (compare:CC (match_dup 0)
1652 (const_int 0)))]
1653 "")
1655 (define_expand "extendhisi2"
1656 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1657 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
1658 ""
1659 "")
1661 (define_insn ""
1662 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1663 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
1664 ""
1665 "@
1666 lha%U1%X1 %0,%1
1667 {exts|extsh} %0,%1"
1668 [(set_attr "type" "load,*")])
1670 (define_insn ""
1671 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1672 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1673 (const_int 0)))
1674 (clobber (match_scratch:SI 2 "=r,r"))]
1675 ""
1676 "@
1677 {exts.|extsh.} %2,%1
1678 #"
1679 [(set_attr "type" "compare")
1680 (set_attr "length" "4,8")])
1682 (define_split
1683 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1684 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1685 (const_int 0)))
1686 (clobber (match_scratch:SI 2 ""))]
1687 "reload_completed"
1688 [(set (match_dup 2)
1689 (sign_extend:SI (match_dup 1)))
1690 (set (match_dup 0)
1691 (compare:CC (match_dup 2)
1692 (const_int 0)))]
1693 "")
1695 (define_insn ""
1696 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1697 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r"))
1698 (const_int 0)))
1699 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1700 (sign_extend:SI (match_dup 1)))]
1701 ""
1702 "@
1703 {exts.|extsh.} %0,%1
1704 #"
1705 [(set_attr "type" "compare")
1706 (set_attr "length" "4,8")])
1707 \f
1708 (define_split
1709 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1710 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" ""))
1711 (const_int 0)))
1712 (set (match_operand:SI 0 "gpc_reg_operand" "")
1713 (sign_extend:SI (match_dup 1)))]
1714 "reload_completed"
1715 [(set (match_dup 0)
1716 (sign_extend:SI (match_dup 1)))
1717 (set (match_dup 2)
1718 (compare:CC (match_dup 0)
1719 (const_int 0)))]
1720 "")
1722 ;; Fixed-point arithmetic insns.
1724 ;; Discourage ai/addic because of carry but provide it in an alternative
1725 ;; allowing register zero as source.
1726 (define_expand "addsi3"
1727 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1728 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1729 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
1730 ""
1731 "
1732 {
1733 if (GET_CODE (operands[2]) == CONST_INT
1734 && ! add_operand (operands[2], SImode))
1735 {
1736 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
1737 ? operands[0] : gen_reg_rtx (SImode));
1739 HOST_WIDE_INT val = INTVAL (operands[2]);
1740 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1741 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
1743 /* The ordering here is important for the prolog expander.
1744 When space is allocated from the stack, adding 'low' first may
1745 produce a temporary deallocation (which would be bad). */
1746 emit_insn (gen_addsi3 (tmp, operands[1], GEN_INT (rest)));
1747 emit_insn (gen_addsi3 (operands[0], tmp, GEN_INT (low)));
1748 DONE;
1749 }
1750 }")
1752 (define_insn "*addsi3_internal1"
1753 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,?r,r")
1754 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b,r,b")
1755 (match_operand:SI 2 "add_operand" "r,I,I,L")))]
1756 ""
1757 "@
1758 {cax|add} %0,%1,%2
1759 {cal %0,%2(%1)|addi %0,%1,%2}
1760 {ai|addic} %0,%1,%2
1761 {cau|addis} %0,%1,%v2"
1762 [(set_attr "length" "4,4,4,4")])
1764 (define_insn "addsi3_high"
1765 [(set (match_operand:SI 0 "gpc_reg_operand" "=b")
1766 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
1767 (high:SI (match_operand 2 "" ""))))]
1768 "TARGET_MACHO && !TARGET_64BIT"
1769 "{cau|addis} %0,%1,ha16(%2)"
1770 [(set_attr "length" "4")])
1772 (define_insn "*addsi3_internal2"
1773 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
1774 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1775 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1776 (const_int 0)))
1777 (clobber (match_scratch:SI 3 "=r,r,r,r"))]
1778 "! TARGET_POWERPC64"
1779 "@
1780 {cax.|add.} %3,%1,%2
1781 {ai.|addic.} %3,%1,%2
1782 #
1783 #"
1784 [(set_attr "type" "compare")
1785 (set_attr "length" "4,4,8,8")])
1787 (define_split
1788 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1789 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1790 (match_operand:SI 2 "reg_or_short_operand" ""))
1791 (const_int 0)))
1792 (clobber (match_scratch:SI 3 ""))]
1793 "! TARGET_POWERPC64 && reload_completed"
1794 [(set (match_dup 3)
1795 (plus:SI (match_dup 1)
1796 (match_dup 2)))
1797 (set (match_dup 0)
1798 (compare:CC (match_dup 3)
1799 (const_int 0)))]
1800 "")
1802 (define_insn "*addsi3_internal3"
1803 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
1804 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
1805 (match_operand:SI 2 "reg_or_short_operand" "r,I,r,I"))
1806 (const_int 0)))
1807 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
1808 (plus:SI (match_dup 1)
1809 (match_dup 2)))]
1810 "! TARGET_POWERPC64"
1811 "@
1812 {cax.|add.} %0,%1,%2
1813 {ai.|addic.} %0,%1,%2
1814 #
1815 #"
1816 [(set_attr "type" "compare")
1817 (set_attr "length" "4,4,8,8")])
1819 (define_split
1820 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
1821 (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1822 (match_operand:SI 2 "reg_or_short_operand" ""))
1823 (const_int 0)))
1824 (set (match_operand:SI 0 "gpc_reg_operand" "")
1825 (plus:SI (match_dup 1) (match_dup 2)))]
1826 "! TARGET_POWERPC64 && reload_completed"
1827 [(set (match_dup 0)
1828 (plus:SI (match_dup 1)
1829 (match_dup 2)))
1830 (set (match_dup 3)
1831 (compare:CC (match_dup 0)
1832 (const_int 0)))]
1833 "")
1835 ;; Split an add that we can't do in one insn into two insns, each of which
1836 ;; does one 16-bit part. This is used by combine. Note that the low-order
1837 ;; add should be last in case the result gets used in an address.
1839 (define_split
1840 [(set (match_operand:SI 0 "gpc_reg_operand" "")
1841 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1842 (match_operand:SI 2 "non_add_cint_operand" "")))]
1843 ""
1844 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
1845 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
1846 "
1847 {
1848 HOST_WIDE_INT val = INTVAL (operands[2]);
1849 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
1850 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode);
1852 operands[3] = GEN_INT (rest);
1853 operands[4] = GEN_INT (low);
1854 }")
1856 (define_insn "one_cmplsi2"
1857 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1858 (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
1859 ""
1860 "nor %0,%1,%1")
1862 (define_insn ""
1863 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1864 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1865 (const_int 0)))
1866 (clobber (match_scratch:SI 2 "=r,r"))]
1867 "! TARGET_POWERPC64"
1868 "@
1869 nor. %2,%1,%1
1870 #"
1871 [(set_attr "type" "compare")
1872 (set_attr "length" "4,8")])
1874 (define_split
1875 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1876 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1877 (const_int 0)))
1878 (clobber (match_scratch:SI 2 ""))]
1879 "! TARGET_POWERPC64 && reload_completed"
1880 [(set (match_dup 2)
1881 (not:SI (match_dup 1)))
1882 (set (match_dup 0)
1883 (compare:CC (match_dup 2)
1884 (const_int 0)))]
1885 "")
1887 (define_insn ""
1888 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
1889 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
1890 (const_int 0)))
1891 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1892 (not:SI (match_dup 1)))]
1893 "! TARGET_POWERPC64"
1894 "@
1895 nor. %0,%1,%1
1896 #"
1897 [(set_attr "type" "compare")
1898 (set_attr "length" "4,8")])
1900 (define_split
1901 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
1902 (compare:CC (not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
1903 (const_int 0)))
1904 (set (match_operand:SI 0 "gpc_reg_operand" "")
1905 (not:SI (match_dup 1)))]
1906 "! TARGET_POWERPC64 && reload_completed"
1907 [(set (match_dup 0)
1908 (not:SI (match_dup 1)))
1909 (set (match_dup 2)
1910 (compare:CC (match_dup 0)
1911 (const_int 0)))]
1912 "")
1914 (define_insn ""
1915 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
1916 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "rI")
1917 (match_operand:SI 2 "gpc_reg_operand" "r")))]
1918 "! TARGET_POWERPC"
1919 "{sf%I1|subf%I1c} %0,%2,%1")
1921 (define_insn ""
1922 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1923 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
1924 (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
1925 "TARGET_POWERPC"
1926 "@
1927 subf %0,%2,%1
1928 subfic %0,%2,%1")
1930 (define_insn ""
1931 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1932 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1933 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1934 (const_int 0)))
1935 (clobber (match_scratch:SI 3 "=r,r"))]
1936 "! TARGET_POWERPC"
1937 "@
1938 {sf.|subfc.} %3,%2,%1
1939 #"
1940 [(set_attr "type" "compare")
1941 (set_attr "length" "4,8")])
1943 (define_insn ""
1944 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
1945 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1946 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1947 (const_int 0)))
1948 (clobber (match_scratch:SI 3 "=r,r"))]
1949 "TARGET_POWERPC && ! TARGET_POWERPC64"
1950 "@
1951 subf. %3,%2,%1
1952 #"
1953 [(set_attr "type" "compare")
1954 (set_attr "length" "4,8")])
1956 (define_split
1957 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
1958 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
1959 (match_operand:SI 2 "gpc_reg_operand" ""))
1960 (const_int 0)))
1961 (clobber (match_scratch:SI 3 ""))]
1962 "! TARGET_POWERPC64 && reload_completed"
1963 [(set (match_dup 3)
1964 (minus:SI (match_dup 1)
1965 (match_dup 2)))
1966 (set (match_dup 0)
1967 (compare:CC (match_dup 3)
1968 (const_int 0)))]
1969 "")
1971 (define_insn ""
1972 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1973 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1974 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1975 (const_int 0)))
1976 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1977 (minus:SI (match_dup 1) (match_dup 2)))]
1978 "! TARGET_POWERPC"
1979 "@
1980 {sf.|subfc.} %0,%2,%1
1981 #"
1982 [(set_attr "type" "compare")
1983 (set_attr "length" "4,8")])
1985 (define_insn ""
1986 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
1987 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
1988 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
1989 (const_int 0)))
1990 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
1991 (minus:SI (match_dup 1)
1992 (match_dup 2)))]
1993 "TARGET_POWERPC && ! TARGET_POWERPC64"
1994 "@
1995 subf. %0,%2,%1
1996 #"
1997 [(set_attr "type" "compare")
1998 (set_attr "length" "4,8")])
2000 (define_split
2001 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2002 (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "")
2003 (match_operand:SI 2 "gpc_reg_operand" ""))
2004 (const_int 0)))
2005 (set (match_operand:SI 0 "gpc_reg_operand" "")
2006 (minus:SI (match_dup 1)
2007 (match_dup 2)))]
2008 "! TARGET_POWERPC64 && reload_completed"
2009 [(set (match_dup 0)
2010 (minus:SI (match_dup 1)
2011 (match_dup 2)))
2012 (set (match_dup 3)
2013 (compare:CC (match_dup 0)
2014 (const_int 0)))]
2015 "")
2017 (define_expand "subsi3"
2018 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2019 (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
2020 (match_operand:SI 2 "reg_or_arith_cint_operand" "")))]
2021 ""
2022 "
2023 {
2024 if (GET_CODE (operands[2]) == CONST_INT)
2025 {
2026 emit_insn (gen_addsi3 (operands[0], operands[1],
2027 negate_rtx (SImode, operands[2])));
2028 DONE;
2029 }
2030 }")
2032 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
2033 ;; instruction and some auxiliary computations. Then we just have a single
2034 ;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
2035 ;; combine.
2037 (define_expand "sminsi3"
2038 [(set (match_dup 3)
2039 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
2040 (match_operand:SI 2 "reg_or_short_operand" ""))
2041 (const_int 0)
2042 (minus:SI (match_dup 2) (match_dup 1))))
2043 (set (match_operand:SI 0 "gpc_reg_operand" "")
2044 (minus:SI (match_dup 2) (match_dup 3)))]
2045 "TARGET_POWER || TARGET_ISEL"
2046 "
2047 {
2048 if (TARGET_ISEL)
2049 {
2050 operands[2] = force_reg (SImode, operands[2]);
2051 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]);
2052 DONE;
2053 }
2055 operands[3] = gen_reg_rtx (SImode);
2056 }")
2058 (define_split
2059 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2060 (smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
2061 (match_operand:SI 2 "reg_or_short_operand" "")))
2062 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
2063 "TARGET_POWER"
2064 [(set (match_dup 3)
2065 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
2066 (const_int 0)
2067 (minus:SI (match_dup 2) (match_dup 1))))
2068 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
2069 "")
2071 (define_expand "smaxsi3"
2072 [(set (match_dup 3)
2073 (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
2074 (match_operand:SI 2 "reg_or_short_operand" ""))
2075 (const_int 0)
2076 (minus:SI (match_dup 2) (match_dup 1))))
2077 (set (match_operand:SI 0 "gpc_reg_operand" "")
2078 (plus:SI (match_dup 3) (match_dup 1)))]
2079 "TARGET_POWER || TARGET_ISEL"
2080 "
2081 {
2082 if (TARGET_ISEL)
2083 {
2084 operands[2] = force_reg (SImode, operands[2]);
2085 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]);
2086 DONE;
2087 }
2088 operands[3] = gen_reg_rtx (SImode);
2089 }")
2091 (define_split
2092 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2093 (smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
2094 (match_operand:SI 2 "reg_or_short_operand" "")))
2095 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
2096 "TARGET_POWER"
2097 [(set (match_dup 3)
2098 (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
2099 (const_int 0)
2100 (minus:SI (match_dup 2) (match_dup 1))))
2101 (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
2102 "")
2104 (define_expand "uminsi3"
2105 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2106 (match_dup 5)))
2107 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
2108 (match_dup 5)))
2109 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
2110 (const_int 0)
2111 (minus:SI (match_dup 4) (match_dup 3))))
2112 (set (match_operand:SI 0 "gpc_reg_operand" "")
2113 (minus:SI (match_dup 2) (match_dup 3)))]
2114 "TARGET_POWER || TARGET_ISEL"
2115 "
2116 {
2117 if (TARGET_ISEL)
2118 {
2119 rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]);
2120 DONE;
2121 }
2122 operands[3] = gen_reg_rtx (SImode);
2123 operands[4] = gen_reg_rtx (SImode);
2124 operands[5] = GEN_INT (-2147483647 - 1);
2125 }")
2127 (define_expand "umaxsi3"
2128 [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
2129 (match_dup 5)))
2130 (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
2131 (match_dup 5)))
2132 (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
2133 (const_int 0)
2134 (minus:SI (match_dup 4) (match_dup 3))))
2135 (set (match_operand:SI 0 "gpc_reg_operand" "")
2136 (plus:SI (match_dup 3) (match_dup 1)))]
2137 "TARGET_POWER || TARGET_ISEL"
2138 "
2139 {
2140 if (TARGET_ISEL)
2141 {
2142 rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]);
2143 DONE;
2144 }
2145 operands[3] = gen_reg_rtx (SImode);
2146 operands[4] = gen_reg_rtx (SImode);
2147 operands[5] = GEN_INT (-2147483647 - 1);
2148 }")
2150 (define_insn ""
2151 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2152 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
2153 (match_operand:SI 2 "reg_or_short_operand" "rI"))
2154 (const_int 0)
2155 (minus:SI (match_dup 2) (match_dup 1))))]
2156 "TARGET_POWER"
2157 "doz%I2 %0,%1,%2")
2159 (define_insn ""
2160 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2161 (compare:CC
2162 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2163 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2164 (const_int 0)
2165 (minus:SI (match_dup 2) (match_dup 1)))
2166 (const_int 0)))
2167 (clobber (match_scratch:SI 3 "=r,r"))]
2168 "TARGET_POWER"
2169 "@
2170 doz%I2. %3,%1,%2
2171 #"
2172 [(set_attr "type" "delayed_compare")
2173 (set_attr "length" "4,8")])
2175 (define_split
2176 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2177 (compare:CC
2178 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2179 (match_operand:SI 2 "reg_or_short_operand" ""))
2180 (const_int 0)
2181 (minus:SI (match_dup 2) (match_dup 1)))
2182 (const_int 0)))
2183 (clobber (match_scratch:SI 3 ""))]
2184 "TARGET_POWER && reload_completed"
2185 [(set (match_dup 3)
2186 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2187 (const_int 0)
2188 (minus:SI (match_dup 2) (match_dup 1))))
2189 (set (match_dup 0)
2190 (compare:CC (match_dup 3)
2191 (const_int 0)))]
2192 "")
2194 (define_insn ""
2195 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2196 (compare:CC
2197 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r,r")
2198 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
2199 (const_int 0)
2200 (minus:SI (match_dup 2) (match_dup 1)))
2201 (const_int 0)))
2202 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2203 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2204 (const_int 0)
2205 (minus:SI (match_dup 2) (match_dup 1))))]
2206 "TARGET_POWER"
2207 "@
2208 doz%I2. %0,%1,%2
2209 #"
2210 [(set_attr "type" "delayed_compare")
2211 (set_attr "length" "4,8")])
2213 (define_split
2214 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2215 (compare:CC
2216 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "")
2217 (match_operand:SI 2 "reg_or_short_operand" ""))
2218 (const_int 0)
2219 (minus:SI (match_dup 2) (match_dup 1)))
2220 (const_int 0)))
2221 (set (match_operand:SI 0 "gpc_reg_operand" "")
2222 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2223 (const_int 0)
2224 (minus:SI (match_dup 2) (match_dup 1))))]
2225 "TARGET_POWER && reload_completed"
2226 [(set (match_dup 0)
2227 (if_then_else:SI (gt (match_dup 1) (match_dup 2))
2228 (const_int 0)
2229 (minus:SI (match_dup 2) (match_dup 1))))
2230 (set (match_dup 3)
2231 (compare:CC (match_dup 0)
2232 (const_int 0)))]
2233 "")
2235 ;; We don't need abs with condition code because such comparisons should
2236 ;; never be done.
2237 (define_expand "abssi2"
2238 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2239 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))]
2240 ""
2241 "
2242 {
2243 if (TARGET_ISEL)
2244 {
2245 emit_insn (gen_abssi2_isel (operands[0], operands[1]));
2246 DONE;
2247 }
2248 else if (! TARGET_POWER)
2249 {
2250 emit_insn (gen_abssi2_nopower (operands[0], operands[1]));
2251 DONE;
2252 }
2253 }")
2255 (define_insn "*abssi2_power"
2256 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2257 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2258 "TARGET_POWER"
2259 "abs %0,%1")
2261 (define_insn_and_split "abssi2_isel"
2262 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2263 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
2264 (clobber (match_scratch:SI 2 "=b"))
2265 (clobber (match_scratch:CC 3 "=y"))]
2266 "TARGET_ISEL"
2267 "#"
2268 "&& reload_completed"
2269 [(set (match_dup 2) (neg:SI (match_dup 1)))
2270 (set (match_dup 3)
2271 (compare:CC (match_dup 1)
2272 (const_int 0)))
2273 (set (match_dup 0)
2274 (if_then_else:SI (ge (match_dup 3)
2275 (const_int 0))
2276 (match_dup 1)
2277 (match_dup 2)))]
2278 "")
2280 (define_insn_and_split "abssi2_nopower"
2281 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2282 (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))
2283 (clobber (match_scratch:SI 2 "=&r,&r"))]
2284 "! TARGET_POWER && ! TARGET_ISEL"
2285 "#"
2286 "&& reload_completed"
2287 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2288 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2289 (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))]
2290 "")
2292 (define_insn "*nabs_power"
2293 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2294 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
2295 "TARGET_POWER"
2296 "nabs %0,%1")
2298 (define_insn_and_split "*nabs_nopower"
2299 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r")
2300 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))))
2301 (clobber (match_scratch:SI 2 "=&r,&r"))]
2302 "! TARGET_POWER"
2303 "#"
2304 "&& reload_completed"
2305 [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31)))
2306 (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1)))
2307 (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))]
2308 "")
2310 (define_insn "negsi2"
2311 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2312 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
2313 ""
2314 "neg %0,%1")
2316 (define_insn ""
2317 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2318 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2319 (const_int 0)))
2320 (clobber (match_scratch:SI 2 "=r,r"))]
2321 "! TARGET_POWERPC64"
2322 "@
2323 neg. %2,%1
2324 #"
2325 [(set_attr "type" "compare")
2326 (set_attr "length" "4,8")])
2328 (define_split
2329 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2330 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2331 (const_int 0)))
2332 (clobber (match_scratch:SI 2 ""))]
2333 "! TARGET_POWERPC64 && reload_completed"
2334 [(set (match_dup 2)
2335 (neg:SI (match_dup 1)))
2336 (set (match_dup 0)
2337 (compare:CC (match_dup 2)
2338 (const_int 0)))]
2339 "")
2341 (define_insn ""
2342 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
2343 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
2344 (const_int 0)))
2345 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2346 (neg:SI (match_dup 1)))]
2347 "! TARGET_POWERPC64"
2348 "@
2349 neg. %0,%1
2350 #"
2351 [(set_attr "type" "compare")
2352 (set_attr "length" "4,8")])
2354 (define_split
2355 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
2356 (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" ""))
2357 (const_int 0)))
2358 (set (match_operand:SI 0 "gpc_reg_operand" "")
2359 (neg:SI (match_dup 1)))]
2360 "! TARGET_POWERPC64 && reload_completed"
2361 [(set (match_dup 0)
2362 (neg:SI (match_dup 1)))
2363 (set (match_dup 2)
2364 (compare:CC (match_dup 0)
2365 (const_int 0)))]
2366 "")
2368 (define_expand "ffssi2"
2369 [(set (match_dup 2)
2370 (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
2371 (parallel [(set (match_dup 3) (and:SI (match_dup 1)
2372 (match_dup 2)))
2373 (clobber (scratch:CC))])
2374 (set (match_dup 4) (unspec:SI [(match_dup 3)] 21))
2375 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
2376 (minus:SI (const_int 32) (match_dup 4)))]
2377 ""
2378 {
2379 operands[2] = gen_reg_rtx (SImode);
2380 operands[3] = gen_reg_rtx (SImode);
2381 operands[4] = gen_reg_rtx (SImode);
2382 })
2384 (define_insn "cntlzw2"
2385 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2386 (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "r")] 21))]
2387 ""
2388 "{cntlz|cntlzw} %0,%1")
2390 (define_expand "mulsi3"
2391 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2392 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2393 (use (match_operand:SI 2 "reg_or_short_operand" ""))]
2394 ""
2395 "
2396 {
2397 if (TARGET_POWER)
2398 emit_insn (gen_mulsi3_mq (operands[0], operands[1], operands[2]));
2399 else
2400 emit_insn (gen_mulsi3_no_mq (operands[0], operands[1], operands[2]));
2401 DONE;
2402 }")
2404 (define_insn "mulsi3_mq"
2405 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2406 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2407 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2408 (clobber (match_scratch:SI 3 "=q,q"))]
2409 "TARGET_POWER"
2410 "@
2411 {muls|mullw} %0,%1,%2
2412 {muli|mulli} %0,%1,%2"
2413 [(set (attr "type")
2414 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2415 (const_string "imul3")
2416 (match_operand:SI 2 "short_cint_operand" "")
2417 (const_string "imul2")]
2418 (const_string "imul")))])
2420 (define_insn "mulsi3_no_mq"
2421 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2422 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2423 (match_operand:SI 2 "reg_or_short_operand" "r,I")))]
2424 "! TARGET_POWER"
2425 "@
2426 {muls|mullw} %0,%1,%2
2427 {muli|mulli} %0,%1,%2"
2428 [(set (attr "type")
2429 (cond [(match_operand:SI 2 "s8bit_cint_operand" "")
2430 (const_string "imul3")
2431 (match_operand:SI 2 "short_cint_operand" "")
2432 (const_string "imul2")]
2433 (const_string "imul")))])
2435 (define_insn ""
2436 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2437 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2438 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2439 (const_int 0)))
2440 (clobber (match_scratch:SI 3 "=r,r"))
2441 (clobber (match_scratch:SI 4 "=q,q"))]
2442 "TARGET_POWER"
2443 "@
2444 {muls.|mullw.} %3,%1,%2
2445 #"
2446 [(set_attr "type" "delayed_compare")
2447 (set_attr "length" "4,8")])
2449 (define_split
2450 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2451 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2452 (match_operand:SI 2 "gpc_reg_operand" ""))
2453 (const_int 0)))
2454 (clobber (match_scratch:SI 3 ""))
2455 (clobber (match_scratch:SI 4 ""))]
2456 "TARGET_POWER && reload_completed"
2457 [(parallel [(set (match_dup 3)
2458 (mult:SI (match_dup 1) (match_dup 2)))
2459 (clobber (match_dup 4))])
2460 (set (match_dup 0)
2461 (compare:CC (match_dup 3)
2462 (const_int 0)))]
2463 "")
2465 (define_insn ""
2466 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2467 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2468 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2469 (const_int 0)))
2470 (clobber (match_scratch:SI 3 "=r,r"))]
2471 "! TARGET_POWER"
2472 "@
2473 {muls.|mullw.} %3,%1,%2
2474 #"
2475 [(set_attr "type" "delayed_compare")
2476 (set_attr "length" "4,8")])
2478 (define_split
2479 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2480 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2481 (match_operand:SI 2 "gpc_reg_operand" ""))
2482 (const_int 0)))
2483 (clobber (match_scratch:SI 3 ""))]
2484 "! TARGET_POWER && reload_completed"
2485 [(set (match_dup 3)
2486 (mult:SI (match_dup 1) (match_dup 2)))
2487 (set (match_dup 0)
2488 (compare:CC (match_dup 3)
2489 (const_int 0)))]
2490 "")
2492 (define_insn ""
2493 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2494 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2495 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2496 (const_int 0)))
2497 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2498 (mult:SI (match_dup 1) (match_dup 2)))
2499 (clobber (match_scratch:SI 4 "=q,q"))]
2500 "TARGET_POWER"
2501 "@
2502 {muls.|mullw.} %0,%1,%2
2503 #"
2504 [(set_attr "type" "delayed_compare")
2505 (set_attr "length" "4,8")])
2507 (define_split
2508 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2509 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2510 (match_operand:SI 2 "gpc_reg_operand" ""))
2511 (const_int 0)))
2512 (set (match_operand:SI 0 "gpc_reg_operand" "")
2513 (mult:SI (match_dup 1) (match_dup 2)))
2514 (clobber (match_scratch:SI 4 ""))]
2515 "TARGET_POWER && reload_completed"
2516 [(parallel [(set (match_dup 0)
2517 (mult:SI (match_dup 1) (match_dup 2)))
2518 (clobber (match_dup 4))])
2519 (set (match_dup 3)
2520 (compare:CC (match_dup 0)
2521 (const_int 0)))]
2522 "")
2524 (define_insn ""
2525 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2526 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
2527 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
2528 (const_int 0)))
2529 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2530 (mult:SI (match_dup 1) (match_dup 2)))]
2531 "! TARGET_POWER"
2532 "@
2533 {muls.|mullw.} %0,%1,%2
2534 #"
2535 [(set_attr "type" "delayed_compare")
2536 (set_attr "length" "4,8")])
2538 (define_split
2539 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2540 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "")
2541 (match_operand:SI 2 "gpc_reg_operand" ""))
2542 (const_int 0)))
2543 (set (match_operand:SI 0 "gpc_reg_operand" "")
2544 (mult:SI (match_dup 1) (match_dup 2)))]
2545 "! TARGET_POWER && reload_completed"
2546 [(set (match_dup 0)
2547 (mult:SI (match_dup 1) (match_dup 2)))
2548 (set (match_dup 3)
2549 (compare:CC (match_dup 0)
2550 (const_int 0)))]
2551 "")
2553 ;; Operand 1 is divided by operand 2; quotient goes to operand
2554 ;; 0 and remainder to operand 3.
2555 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
2557 (define_expand "divmodsi4"
2558 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2559 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2560 (match_operand:SI 2 "gpc_reg_operand" "")))
2561 (set (match_operand:SI 3 "gpc_reg_operand" "")
2562 (mod:SI (match_dup 1) (match_dup 2)))])]
2563 "TARGET_POWER || (! TARGET_POWER && ! TARGET_POWERPC)"
2564 "
2565 {
2566 if (! TARGET_POWER && ! TARGET_POWERPC)
2567 {
2568 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2569 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2570 emit_insn (gen_divss_call ());
2571 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2572 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2573 DONE;
2574 }
2575 }")
2577 (define_insn ""
2578 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2579 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2580 (match_operand:SI 2 "gpc_reg_operand" "r")))
2581 (set (match_operand:SI 3 "gpc_reg_operand" "=q")
2582 (mod:SI (match_dup 1) (match_dup 2)))]
2583 "TARGET_POWER"
2584 "divs %0,%1,%2"
2585 [(set_attr "type" "idiv")])
2587 (define_expand "udivsi3"
2588 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2589 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2590 (match_operand:SI 2 "gpc_reg_operand" "")))]
2591 "TARGET_POWERPC || (! TARGET_POWER && ! TARGET_POWERPC)"
2592 "
2593 {
2594 if (! TARGET_POWER && ! TARGET_POWERPC)
2595 {
2596 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2597 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2598 emit_insn (gen_quous_call ());
2599 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2600 DONE;
2601 }
2602 else if (TARGET_POWER)
2603 {
2604 emit_insn (gen_udivsi3_mq (operands[0], operands[1], operands[2]));
2605 DONE;
2606 }
2607 }")
2609 (define_insn "udivsi3_mq"
2610 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2611 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2612 (match_operand:SI 2 "gpc_reg_operand" "r")))
2613 (clobber (match_scratch:SI 3 "=q"))]
2614 "TARGET_POWERPC && TARGET_POWER"
2615 "divwu %0,%1,%2"
2616 [(set_attr "type" "idiv")])
2618 (define_insn "*udivsi3_no_mq"
2619 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2620 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2621 (match_operand:SI 2 "gpc_reg_operand" "r")))]
2622 "TARGET_POWERPC && ! TARGET_POWER"
2623 "divwu %0,%1,%2"
2624 [(set_attr "type" "idiv")])
2626 ;; For powers of two we can do srai/aze for divide and then adjust for
2627 ;; modulus. If it isn't a power of two, FAIL on POWER so divmodsi4 will be
2628 ;; used; for PowerPC, force operands into register and do a normal divide;
2629 ;; for AIX common-mode, use quoss call on register operands.
2630 (define_expand "divsi3"
2631 [(set (match_operand:SI 0 "gpc_reg_operand" "")
2632 (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2633 (match_operand:SI 2 "reg_or_cint_operand" "")))]
2634 ""
2635 "
2636 {
2637 if (GET_CODE (operands[2]) == CONST_INT
2638 && INTVAL (operands[2]) > 0
2639 && exact_log2 (INTVAL (operands[2])) >= 0)
2640 ;
2641 else if (TARGET_POWERPC)
2642 {
2643 operands[2] = force_reg (SImode, operands[2]);
2644 if (TARGET_POWER)
2645 {
2646 emit_insn (gen_divsi3_mq (operands[0], operands[1], operands[2]));
2647 DONE;
2648 }
2649 }
2650 else if (TARGET_POWER)
2651 FAIL;
2652 else
2653 {
2654 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2655 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2656 emit_insn (gen_quoss_call ());
2657 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2658 DONE;
2659 }
2660 }")
2662 (define_insn "divsi3_mq"
2663 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2664 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2665 (match_operand:SI 2 "gpc_reg_operand" "r")))
2666 (clobber (match_scratch:SI 3 "=q"))]
2667 "TARGET_POWERPC && TARGET_POWER"
2668 "divw %0,%1,%2"
2669 [(set_attr "type" "idiv")])
2671 (define_insn "*divsi3_no_mq"
2672 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2673 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2674 (match_operand:SI 2 "gpc_reg_operand" "r")))]
2675 "TARGET_POWERPC && ! TARGET_POWER"
2676 "divw %0,%1,%2"
2677 [(set_attr "type" "idiv")])
2679 (define_expand "modsi3"
2680 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
2681 (use (match_operand:SI 1 "gpc_reg_operand" ""))
2682 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
2683 ""
2684 "
2685 {
2686 int i;
2687 rtx temp1;
2688 rtx temp2;
2690 if (GET_CODE (operands[2]) != CONST_INT
2691 || INTVAL (operands[2]) <= 0
2692 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
2693 FAIL;
2695 temp1 = gen_reg_rtx (SImode);
2696 temp2 = gen_reg_rtx (SImode);
2698 emit_insn (gen_divsi3 (temp1, operands[1], operands[2]));
2699 emit_insn (gen_ashlsi3 (temp2, temp1, GEN_INT (i)));
2700 emit_insn (gen_subsi3 (operands[0], operands[1], temp2));
2701 DONE;
2702 }")
2704 (define_insn ""
2705 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2706 (div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
2707 (match_operand:SI 2 "exact_log2_cint_operand" "N")))]
2708 ""
2709 "{srai|srawi} %0,%1,%p2\;{aze|addze} %0,%0"
2710 [(set_attr "length" "8")])
2712 (define_insn ""
2713 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
2714 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2715 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2716 (const_int 0)))
2717 (clobber (match_scratch:SI 3 "=r,r"))]
2718 ""
2719 "@
2720 {srai|srawi} %3,%1,%p2\;{aze.|addze.} %3,%3
2721 #"
2722 [(set_attr "type" "compare")
2723 (set_attr "length" "8,12")])
2725 (define_split
2726 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
2727 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2728 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2729 (const_int 0)))
2730 (clobber (match_scratch:SI 3 ""))]
2731 "reload_completed"
2732 [(set (match_dup 3)
2733 (div:SI (match_dup 1) (match_dup 2)))
2734 (set (match_dup 0)
2735 (compare:CC (match_dup 3)
2736 (const_int 0)))]
2737 "")
2739 (define_insn ""
2740 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
2741 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
2742 (match_operand:SI 2 "exact_log2_cint_operand" "N,N"))
2743 (const_int 0)))
2744 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
2745 (div:SI (match_dup 1) (match_dup 2)))]
2746 ""
2747 "@
2748 {srai|srawi} %0,%1,%p2\;{aze.|addze.} %0,%0
2749 #"
2750 [(set_attr "type" "compare")
2751 (set_attr "length" "8,12")])
2753 (define_split
2754 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
2755 (compare:CC (div:SI (match_operand:SI 1 "gpc_reg_operand" "")
2756 (match_operand:SI 2 "exact_log2_cint_operand" ""))
2757 (const_int 0)))
2758 (set (match_operand:SI 0 "gpc_reg_operand" "")
2759 (div:SI (match_dup 1) (match_dup 2)))]
2760 "reload_completed"
2761 [(set (match_dup 0)
2762 (div:SI (match_dup 1) (match_dup 2)))
2763 (set (match_dup 3)
2764 (compare:CC (match_dup 0)
2765 (const_int 0)))]
2766 "")
2768 (define_insn ""
2769 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
2770 (udiv:SI
2771 (plus:DI (ashift:DI
2772 (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
2773 (const_int 32))
2774 (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
2775 (match_operand:SI 3 "gpc_reg_operand" "r")))
2776 (set (match_operand:SI 2 "register_operand" "=*q")
2777 (umod:SI
2778 (plus:DI (ashift:DI
2779 (zero_extend:DI (match_dup 1)) (const_int 32))
2780 (zero_extend:DI (match_dup 4)))
2781 (match_dup 3)))]
2782 "TARGET_POWER"
2783 "div %0,%1,%3"
2784 [(set_attr "type" "idiv")])
2786 ;; To do unsigned divide we handle the cases of the divisor looking like a
2787 ;; negative number. If it is a constant that is less than 2**31, we don't
2788 ;; have to worry about the branches. So make a few subroutines here.
2789 ;;
2790 ;; First comes the normal case.
2791 (define_expand "udivmodsi4_normal"
2792 [(set (match_dup 4) (const_int 0))
2793 (parallel [(set (match_operand:SI 0 "" "")
2794 (udiv:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2795 (const_int 32))
2796 (zero_extend:DI (match_operand:SI 1 "" "")))
2797 (match_operand:SI 2 "" "")))
2798 (set (match_operand:SI 3 "" "")
2799 (umod:SI (plus:DI (ashift:DI (zero_extend:DI (match_dup 4))
2800 (const_int 32))
2801 (zero_extend:DI (match_dup 1)))
2802 (match_dup 2)))])]
2803 "TARGET_POWER"
2804 "
2805 { operands[4] = gen_reg_rtx (SImode); }")
2807 ;; This handles the branches.
2808 (define_expand "udivmodsi4_tests"
2809 [(set (match_operand:SI 0 "" "") (const_int 0))
2810 (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
2811 (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
2812 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
2813 (label_ref (match_operand:SI 4 "" "")) (pc)))
2814 (set (match_dup 0) (const_int 1))
2815 (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
2816 (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
2817 (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
2818 (label_ref (match_dup 4)) (pc)))]
2819 "TARGET_POWER"
2820 "
2821 { operands[5] = gen_reg_rtx (CCUNSmode);
2822 operands[6] = gen_reg_rtx (CCmode);
2823 }")
2825 (define_expand "udivmodsi4"
2826 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
2827 (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
2828 (match_operand:SI 2 "reg_or_cint_operand" "")))
2829 (set (match_operand:SI 3 "gpc_reg_operand" "")
2830 (umod:SI (match_dup 1) (match_dup 2)))])]
2831 ""
2832 "
2833 {
2834 rtx label = 0;
2836 if (! TARGET_POWER)
2837 {
2838 if (! TARGET_POWERPC)
2839 {
2840 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
2841 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
2842 emit_insn (gen_divus_call ());
2843 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
2844 emit_move_insn (operands[3], gen_rtx_REG (SImode, 4));
2845 DONE;
2846 }
2847 else
2848 FAIL;
2849 }
2851 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
2852 {
2853 operands[2] = force_reg (SImode, operands[2]);
2854 label = gen_label_rtx ();
2855 emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
2856 operands[3], label));
2857 }
2858 else
2859 operands[2] = force_reg (SImode, operands[2]);
2861 emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
2862 operands[3]));
2863 if (label)
2864 emit_label (label);
2866 DONE;
2867 }")
2869 ;; AIX architecture-independent common-mode multiply (DImode),
2870 ;; divide/modulus, and quotient subroutine calls. Input operands in R3 and
2871 ;; R4; results in R3 and sometimes R4; link register always clobbered by bla
2872 ;; instruction; R0 sometimes clobbered; also, MQ sometimes clobbered but
2873 ;; assumed unused if generating common-mode, so ignore.
2874 (define_insn "mulh_call"
2875 [(set (reg:SI 3)
2876 (truncate:SI
2877 (lshiftrt:DI (mult:DI (sign_extend:DI (reg:SI 3))
2878 (sign_extend:DI (reg:SI 4)))
2879 (const_int 32))))
2880 (clobber (match_scratch:SI 0 "=l"))]
2881 "! TARGET_POWER && ! TARGET_POWERPC"
2882 "bla __mulh"
2883 [(set_attr "type" "imul")])
2885 (define_insn "mull_call"
2886 [(set (reg:DI 3)
2887 (mult:DI (sign_extend:DI (reg:SI 3))
2888 (sign_extend:DI (reg:SI 4))))
2889 (clobber (match_scratch:SI 0 "=l"))
2890 (clobber (reg:SI 0))]
2891 "! TARGET_POWER && ! TARGET_POWERPC"
2892 "bla __mull"
2893 [(set_attr "type" "imul")])
2895 (define_insn "divss_call"
2896 [(set (reg:SI 3)
2897 (div:SI (reg:SI 3) (reg:SI 4)))
2898 (set (reg:SI 4)
2899 (mod:SI (reg:SI 3) (reg:SI 4)))
2900 (clobber (match_scratch:SI 0 "=l"))
2901 (clobber (reg:SI 0))]
2902 "! TARGET_POWER && ! TARGET_POWERPC"
2903 "bla __divss"
2904 [(set_attr "type" "idiv")])
2906 (define_insn "divus_call"
2907 [(set (reg:SI 3)
2908 (udiv:SI (reg:SI 3) (reg:SI 4)))
2909 (set (reg:SI 4)
2910 (umod:SI (reg:SI 3) (reg:SI 4)))
2911 (clobber (match_scratch:SI 0 "=l"))
2912 (clobber (reg:SI 0))
2913 (clobber (match_scratch:CC 1 "=x"))
2914 (clobber (reg:CC 69))]
2915 "! TARGET_POWER && ! TARGET_POWERPC"
2916 "bla __divus"
2917 [(set_attr "type" "idiv")])
2919 (define_insn "quoss_call"
2920 [(set (reg:SI 3)
2921 (div:SI (reg:SI 3) (reg:SI 4)))
2922 (clobber (match_scratch:SI 0 "=l"))]
2923 "! TARGET_POWER && ! TARGET_POWERPC"
2924 "bla __quoss"
2925 [(set_attr "type" "idiv")])
2927 (define_insn "quous_call"
2928 [(set (reg:SI 3)
2929 (udiv:SI (reg:SI 3) (reg:SI 4)))
2930 (clobber (match_scratch:SI 0 "=l"))
2931 (clobber (reg:SI 0))
2932 (clobber (match_scratch:CC 1 "=x"))
2933 (clobber (reg:CC 69))]
2934 "! TARGET_POWER && ! TARGET_POWERPC"
2935 "bla __quous"
2936 [(set_attr "type" "idiv")])
2937 \f
2938 ;; Logical instructions
2939 ;; The logical instructions are mostly combined by using match_operator,
2940 ;; but the plain AND insns are somewhat different because there is no
2941 ;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all
2942 ;; those rotate-and-mask operations. Thus, the AND insns come first.
2944 (define_insn "andsi3"
2945 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
2946 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
2947 (match_operand:SI 2 "and_operand" "?r,T,K,L")))
2948 (clobber (match_scratch:CC 3 "=X,X,x,x"))]
2949 ""
2950 "@
2951 and %0,%1,%2
2952 {rlinm|rlwinm} %0,%1,0,%m2,%M2
2953 {andil.|andi.} %0,%1,%b2
2954 {andiu.|andis.} %0,%1,%u2")
2956 ;; Note to set cr's other than cr0 we do the and immediate and then
2957 ;; the test again -- this avoids a mfcr which on the higher end
2958 ;; machines causes an execution serialization
2960 (define_insn "*andsi3_internal2"
2961 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2962 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2963 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2964 (const_int 0)))
2965 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2966 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2967 "! TARGET_POWERPC64"
2968 "@
2969 and. %3,%1,%2
2970 {andil.|andi.} %3,%1,%b2
2971 {andiu.|andis.} %3,%1,%u2
2972 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2973 #
2974 #
2975 #
2976 #"
2977 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2978 (set_attr "length" "4,4,4,4,8,8,8,8")])
2980 (define_insn "*andsi3_internal3"
2981 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
2982 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
2983 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
2984 (const_int 0)))
2985 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r"))
2986 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
2987 "TARGET_POWERPC64"
2988 "@
2989 #
2990 {andil.|andi.} %3,%1,%b2
2991 {andiu.|andis.} %3,%1,%u2
2992 {rlinm.|rlwinm.} %3,%1,0,%m2,%M2
2993 #
2994 #
2995 #
2996 #"
2997 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
2998 (set_attr "length" "8,4,4,4,8,8,8,8")])
3000 (define_split
3001 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3002 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3003 (match_operand:SI 2 "and_operand" ""))
3004 (const_int 0)))
3005 (clobber (match_scratch:SI 3 ""))
3006 (clobber (match_scratch:CC 4 ""))]
3007 "reload_completed"
3008 [(parallel [(set (match_dup 3)
3009 (and:SI (match_dup 1)
3010 (match_dup 2)))
3011 (clobber (match_dup 4))])
3012 (set (match_dup 0)
3013 (compare:CC (match_dup 3)
3014 (const_int 0)))]
3015 "")
3017 ;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the
3018 ;; whole 64 bit reg, and we don't know what is in the high 32 bits.
3020 (define_split
3021 [(set (match_operand:CC 0 "cc_reg_operand" "")
3022 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3023 (match_operand:SI 2 "gpc_reg_operand" ""))
3024 (const_int 0)))
3025 (clobber (match_scratch:SI 3 ""))
3026 (clobber (match_scratch:CC 4 ""))]
3027 "TARGET_POWERPC64 && reload_completed"
3028 [(parallel [(set (match_dup 3)
3029 (and:SI (match_dup 1)
3030 (match_dup 2)))
3031 (clobber (match_dup 4))])
3032 (set (match_dup 0)
3033 (compare:CC (match_dup 3)
3034 (const_int 0)))]
3035 "")
3037 (define_insn "*andsi3_internal4"
3038 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3039 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3040 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3041 (const_int 0)))
3042 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3043 (and:SI (match_dup 1)
3044 (match_dup 2)))
3045 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3046 "! TARGET_POWERPC64"
3047 "@
3048 and. %0,%1,%2
3049 {andil.|andi.} %0,%1,%b2
3050 {andiu.|andis.} %0,%1,%u2
3051 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3052 #
3053 #
3054 #
3055 #"
3056 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
3057 (set_attr "length" "4,4,4,4,8,8,8,8")])
3059 (define_insn "*andsi3_internal5"
3060 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y")
3061 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r")
3062 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T"))
3063 (const_int 0)))
3064 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r")
3065 (and:SI (match_dup 1)
3066 (match_dup 2)))
3067 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))]
3068 "TARGET_POWERPC64"
3069 "@
3070 #
3071 {andil.|andi.} %0,%1,%b2
3072 {andiu.|andis.} %0,%1,%u2
3073 {rlinm.|rlwinm.} %0,%1,0,%m2,%M2
3074 #
3075 #
3076 #
3077 #"
3078 [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare")
3079 (set_attr "length" "8,4,4,4,8,8,8,8")])
3081 (define_split
3082 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3083 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3084 (match_operand:SI 2 "and_operand" ""))
3085 (const_int 0)))
3086 (set (match_operand:SI 0 "gpc_reg_operand" "")
3087 (and:SI (match_dup 1)
3088 (match_dup 2)))
3089 (clobber (match_scratch:CC 4 ""))]
3090 "reload_completed"
3091 [(parallel [(set (match_dup 0)
3092 (and:SI (match_dup 1)
3093 (match_dup 2)))
3094 (clobber (match_dup 4))])
3095 (set (match_dup 3)
3096 (compare:CC (match_dup 0)
3097 (const_int 0)))]
3098 "")
3100 (define_split
3101 [(set (match_operand:CC 3 "cc_reg_operand" "")
3102 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "")
3103 (match_operand:SI 2 "gpc_reg_operand" ""))
3104 (const_int 0)))
3105 (set (match_operand:SI 0 "gpc_reg_operand" "")
3106 (and:SI (match_dup 1)
3107 (match_dup 2)))
3108 (clobber (match_scratch:CC 4 ""))]
3109 "TARGET_POWERPC64 && reload_completed"
3110 [(parallel [(set (match_dup 0)
3111 (and:SI (match_dup 1)
3112 (match_dup 2)))
3113 (clobber (match_dup 4))])
3114 (set (match_dup 3)
3115 (compare:CC (match_dup 0)
3116 (const_int 0)))]
3117 "")
3119 ;; Handle the PowerPC64 rlwinm corner case
3121 (define_insn_and_split "*andsi3_internal6"
3122 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3123 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3124 (match_operand:SI 2 "mask_operand_wrap" "i")))]
3125 "TARGET_POWERPC64"
3126 "#"
3127 "TARGET_POWERPC64"
3128 [(set (match_dup 0)
3129 (and:SI (rotate:SI (match_dup 1) (match_dup 3))
3130 (match_dup 4)))
3131 (set (match_dup 0)
3132 (rotate:SI (match_dup 0) (match_dup 5)))]
3133 "
3134 {
3135 int mb = extract_MB (operands[2]);
3136 int me = extract_ME (operands[2]);
3137 operands[3] = GEN_INT (me + 1);
3138 operands[5] = GEN_INT (32 - (me + 1));
3139 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3140 }"
3141 [(set_attr "length" "8")])
3143 (define_insn_and_split "*andsi3_internal7"
3144 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
3145 (compare:CC (and:SI (match_operand:SI 0 "gpc_reg_operand" "r,r")
3146 (match_operand:SI 1 "mask_operand_wrap" "i,i"))
3147 (const_int 0)))
3148 (clobber (match_scratch:SI 3 "=r,r"))]
3149 "TARGET_POWERPC64"
3150 "#"
3151 "TARGET_POWERPC64"
3152 [(parallel [(set (match_dup 2)
3153 (compare:CC (and:SI (rotate:SI (match_dup 0) (match_dup 4))
3154 (match_dup 5))
3155 (const_int 0)))
3156 (clobber (match_dup 3))])]
3157 "
3158 {
3159 int mb = extract_MB (operands[1]);
3160 int me = extract_ME (operands[1]);
3161 operands[4] = GEN_INT (me + 1);
3162 operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3163 }"
3164 [(set_attr "type" "delayed_compare,compare")
3165 (set_attr "length" "4,8")])
3167 (define_insn_and_split "*andsi3_internal8"
3168 [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
3169 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3170 (match_operand:SI 2 "mask_operand_wrap" "i,i"))
3171 (const_int 0)))
3172 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3173 (and:SI (match_dup 1)
3174 (match_dup 2)))]
3175 "TARGET_POWERPC64"
3176 "#"
3177 "TARGET_POWERPC64"
3178 [(parallel [(set (match_dup 3)
3179 (compare:CC (and:SI (rotate:SI (match_dup 1) (match_dup 4))
3180 (match_dup 5))
3181 (const_int 0)))
3182 (set (match_dup 0)
3183 (and:SI (rotate:SI (match_dup 1) (match_dup 4))
3184 (match_dup 5)))])
3185 (set (match_dup 0)
3186 (rotate:SI (match_dup 0) (match_dup 6)))]
3187 "
3188 {
3189 int mb = extract_MB (operands[2]);
3190 int me = extract_ME (operands[2]);
3191 operands[4] = GEN_INT (me + 1);
3192 operands[6] = GEN_INT (32 - (me + 1));
3193 operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb)));
3194 }"
3195 [(set_attr "type" "delayed_compare,compare")
3196 (set_attr "length" "8,12")])
3198 (define_expand "iorsi3"
3199 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3200 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
3201 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3202 ""
3203 "
3204 {
3205 if (GET_CODE (operands[2]) == CONST_INT
3206 && ! logical_operand (operands[2], SImode))
3207 {
3208 HOST_WIDE_INT value = INTVAL (operands[2]);
3209 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
3210 ? operands[0] : gen_reg_rtx (SImode));
3212 emit_insn (gen_iorsi3 (tmp, operands[1],
3213 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3214 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3215 DONE;
3216 }
3217 }")
3219 (define_expand "xorsi3"
3220 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3221 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
3222 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))]
3223 ""
3224 "
3225 {
3226 if (GET_CODE (operands[2]) == CONST_INT
3227 && ! logical_operand (operands[2], SImode))
3228 {
3229 HOST_WIDE_INT value = INTVAL (operands[2]);
3230 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
3231 ? operands[0] : gen_reg_rtx (SImode));
3233 emit_insn (gen_xorsi3 (tmp, operands[1],
3234 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
3235 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
3236 DONE;
3237 }
3238 }")
3240 (define_insn "*boolsi3_internal1"
3241 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
3242 (match_operator:SI 3 "boolean_or_operator"
3243 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
3244 (match_operand:SI 2 "logical_operand" "r,K,L")]))]
3245 ""
3246 "@
3247 %q3 %0,%1,%2
3248 {%q3il|%q3i} %0,%1,%b2
3249 {%q3iu|%q3is} %0,%1,%u2")
3251 (define_insn "*boolsi3_internal2"
3252 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3253 (compare:CC (match_operator:SI 4 "boolean_or_operator"
3254 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3255 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3256 (const_int 0)))
3257 (clobber (match_scratch:SI 3 "=r,r"))]
3258 "! TARGET_POWERPC64"
3259 "@
3260 %q4. %3,%1,%2
3261 #"
3262 [(set_attr "type" "compare")
3263 (set_attr "length" "4,8")])
3265 (define_split
3266 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3267 (compare:CC (match_operator:SI 4 "boolean_operator"
3268 [(match_operand:SI 1 "gpc_reg_operand" "")
3269 (match_operand:SI 2 "gpc_reg_operand" "")])
3270 (const_int 0)))
3271 (clobber (match_scratch:SI 3 ""))]
3272 "! TARGET_POWERPC64 && reload_completed"
3273 [(set (match_dup 3) (match_dup 4))
3274 (set (match_dup 0)
3275 (compare:CC (match_dup 3)
3276 (const_int 0)))]
3277 "")
3279 (define_insn "*boolsi3_internal3"
3280 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3281 (compare:CC (match_operator:SI 4 "boolean_operator"
3282 [(match_operand:SI 1 "gpc_reg_operand" "%r,r")
3283 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3284 (const_int 0)))
3285 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3286 (match_dup 4))]
3287 "! TARGET_POWERPC64"
3288 "@
3289 %q4. %0,%1,%2
3290 #"
3291 [(set_attr "type" "compare")
3292 (set_attr "length" "4,8")])
3294 (define_split
3295 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3296 (compare:CC (match_operator:SI 4 "boolean_operator"
3297 [(match_operand:SI 1 "gpc_reg_operand" "")
3298 (match_operand:SI 2 "gpc_reg_operand" "")])
3299 (const_int 0)))
3300 (set (match_operand:SI 0 "gpc_reg_operand" "")
3301 (match_dup 4))]
3302 "! TARGET_POWERPC64 && reload_completed"
3303 [(set (match_dup 0) (match_dup 4))
3304 (set (match_dup 3)
3305 (compare:CC (match_dup 0)
3306 (const_int 0)))]
3307 "")
3309 ;; Split an logical operation that we can't do in one insn into two insns,
3310 ;; each of which does one 16-bit part. This is used by combine.
3312 (define_split
3313 [(set (match_operand:SI 0 "gpc_reg_operand" "")
3314 (match_operator:SI 3 "boolean_or_operator"
3315 [(match_operand:SI 1 "gpc_reg_operand" "")
3316 (match_operand:SI 2 "non_logical_cint_operand" "")]))]
3317 ""
3318 [(set (match_dup 0) (match_dup 4))
3319 (set (match_dup 0) (match_dup 5))]
3320 "
3321 {
3322 rtx i;
3323 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff));
3324 operands[4] = gen_rtx (GET_CODE (operands[3]), SImode,
3325 operands[1], i);
3326 i = GEN_INT (INTVAL (operands[2]) & 0xffff);
3327 operands[5] = gen_rtx (GET_CODE (operands[3]), SImode,
3328 operands[0], i);
3329 }")
3331 (define_insn "*boolcsi3_internal1"
3332 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3333 (match_operator:SI 3 "boolean_operator"
3334 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3335 (match_operand:SI 2 "gpc_reg_operand" "r")]))]
3336 ""
3337 "%q3 %0,%2,%1")
3339 (define_insn "*boolcsi3_internal2"
3340 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3341 (compare:CC (match_operator:SI 4 "boolean_operator"
3342 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3343 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3344 (const_int 0)))
3345 (clobber (match_scratch:SI 3 "=r,r"))]
3346 "! TARGET_POWERPC64"
3347 "@
3348 %q4. %3,%2,%1
3349 #"
3350 [(set_attr "type" "compare")
3351 (set_attr "length" "4,8")])
3353 (define_split
3354 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3355 (compare:CC (match_operator:SI 4 "boolean_operator"
3356 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3357 (match_operand:SI 2 "gpc_reg_operand" "")])
3358 (const_int 0)))
3359 (clobber (match_scratch:SI 3 ""))]
3360 "! TARGET_POWERPC64 && reload_completed"
3361 [(set (match_dup 3) (match_dup 4))
3362 (set (match_dup 0)
3363 (compare:CC (match_dup 3)
3364 (const_int 0)))]
3365 "")
3367 (define_insn "*boolcsi3_internal3"
3368 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3369 (compare:CC (match_operator:SI 4 "boolean_operator"
3370 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3371 (match_operand:SI 2 "gpc_reg_operand" "r,r")])
3372 (const_int 0)))
3373 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3374 (match_dup 4))]
3375 "! TARGET_POWERPC64"
3376 "@
3377 %q4. %0,%2,%1
3378 #"
3379 [(set_attr "type" "compare")
3380 (set_attr "length" "4,8")])
3382 (define_split
3383 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3384 (compare:CC (match_operator:SI 4 "boolean_operator"
3385 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3386 (match_operand:SI 2 "gpc_reg_operand" "")])
3387 (const_int 0)))
3388 (set (match_operand:SI 0 "gpc_reg_operand" "")
3389 (match_dup 4))]
3390 "! TARGET_POWERPC64 && reload_completed"
3391 [(set (match_dup 0) (match_dup 4))
3392 (set (match_dup 3)
3393 (compare:CC (match_dup 0)
3394 (const_int 0)))]
3395 "")
3397 (define_insn "*boolccsi3_internal1"
3398 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3399 (match_operator:SI 3 "boolean_operator"
3400 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
3401 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))]
3402 ""
3403 "%q3 %0,%1,%2")
3405 (define_insn "*boolccsi3_internal2"
3406 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3407 (compare:CC (match_operator:SI 4 "boolean_operator"
3408 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r"))
3409 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3410 (const_int 0)))
3411 (clobber (match_scratch:SI 3 "=r,r"))]
3412 "! TARGET_POWERPC64"
3413 "@
3414 %q4. %3,%1,%2
3415 #"
3416 [(set_attr "type" "compare")
3417 (set_attr "length" "4,8")])
3419 (define_split
3420 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3421 (compare:CC (match_operator:SI 4 "boolean_operator"
3422 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3423 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3424 (const_int 0)))
3425 (clobber (match_scratch:SI 3 ""))]
3426 "! TARGET_POWERPC64 && reload_completed"
3427 [(set (match_dup 3) (match_dup 4))
3428 (set (match_dup 0)
3429 (compare:CC (match_dup 3)
3430 (const_int 0)))]
3431 "")
3433 (define_insn "*boolccsi3_internal3"
3434 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
3435 (compare:CC (match_operator:SI 4 "boolean_operator"
3436 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r"))
3437 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))])
3438 (const_int 0)))
3439 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3440 (match_dup 4))]
3441 "! TARGET_POWERPC64"
3442 "@
3443 %q4. %0,%1,%2
3444 #"
3445 [(set_attr "type" "compare")
3446 (set_attr "length" "4,8")])
3448 (define_split
3449 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
3450 (compare:CC (match_operator:SI 4 "boolean_operator"
3451 [(not:SI (match_operand:SI 1 "gpc_reg_operand" ""))
3452 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))])
3453 (const_int 0)))
3454 (set (match_operand:SI 0 "gpc_reg_operand" "")
3455 (match_dup 4))]
3456 "! TARGET_POWERPC64 && reload_completed"
3457 [(set (match_dup 0) (match_dup 4))
3458 (set (match_dup 3)
3459 (compare:CC (match_dup 0)
3460 (const_int 0)))]
3461 "")
3463 ;; maskir insn. We need four forms because things might be in arbitrary
3464 ;; orders. Don't define forms that only set CR fields because these
3465 ;; would modify an input register.
3467 (define_insn "*maskir_internal1"
3468 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3469 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3470 (match_operand:SI 1 "gpc_reg_operand" "0"))
3471 (and:SI (match_dup 2)
3472 (match_operand:SI 3 "gpc_reg_operand" "r"))))]
3473 "TARGET_POWER"
3474 "maskir %0,%3,%2")
3476 (define_insn "*maskir_internal2"
3477 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3478 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
3479 (match_operand:SI 1 "gpc_reg_operand" "0"))
3480 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3481 (match_dup 2))))]
3482 "TARGET_POWER"
3483 "maskir %0,%3,%2")
3485 (define_insn "*maskir_internal3"
3486 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3487 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
3488 (match_operand:SI 3 "gpc_reg_operand" "r"))
3489 (and:SI (not:SI (match_dup 2))
3490 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3491 "TARGET_POWER"
3492 "maskir %0,%3,%2")
3494 (define_insn "*maskir_internal4"
3495 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3496 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3497 (match_operand:SI 2 "gpc_reg_operand" "r"))
3498 (and:SI (not:SI (match_dup 2))
3499 (match_operand:SI 1 "gpc_reg_operand" "0"))))]
3500 "TARGET_POWER"
3501 "maskir %0,%3,%2")
3503 (define_insn "*maskir_internal5"
3504 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3505 (compare:CC
3506 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3507 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3508 (and:SI (match_dup 2)
3509 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
3510 (const_int 0)))
3511 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3512 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3513 (and:SI (match_dup 2) (match_dup 3))))]
3514 "TARGET_POWER"
3515 "@
3516 maskir. %0,%3,%2
3517 #"
3518 [(set_attr "type" "compare")
3519 (set_attr "length" "4,8")])
3521 (define_split
3522 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3523 (compare:CC
3524 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3525 (match_operand:SI 1 "gpc_reg_operand" ""))
3526 (and:SI (match_dup 2)
3527 (match_operand:SI 3 "gpc_reg_operand" "")))
3528 (const_int 0)))
3529 (set (match_operand:SI 0 "gpc_reg_operand" "")
3530 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3531 (and:SI (match_dup 2) (match_dup 3))))]
3532 "TARGET_POWER && reload_completed"
3533 [(set (match_dup 0)
3534 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3535 (and:SI (match_dup 2) (match_dup 3))))
3536 (set (match_dup 4)
3537 (compare:CC (match_dup 0)
3538 (const_int 0)))]
3539 "")
3541 (define_insn "*maskir_internal6"
3542 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3543 (compare:CC
3544 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3545 (match_operand:SI 1 "gpc_reg_operand" "0,0"))
3546 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3547 (match_dup 2)))
3548 (const_int 0)))
3549 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3550 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3551 (and:SI (match_dup 3) (match_dup 2))))]
3552 "TARGET_POWER"
3553 "@
3554 maskir. %0,%3,%2
3555 #"
3556 [(set_attr "type" "compare")
3557 (set_attr "length" "4,8")])
3559 (define_split
3560 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3561 (compare:CC
3562 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))
3563 (match_operand:SI 1 "gpc_reg_operand" ""))
3564 (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3565 (match_dup 2)))
3566 (const_int 0)))
3567 (set (match_operand:SI 0 "gpc_reg_operand" "")
3568 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3569 (and:SI (match_dup 3) (match_dup 2))))]
3570 "TARGET_POWER && reload_completed"
3571 [(set (match_dup 0)
3572 (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
3573 (and:SI (match_dup 3) (match_dup 2))))
3574 (set (match_dup 4)
3575 (compare:CC (match_dup 0)
3576 (const_int 0)))]
3577 "")
3579 (define_insn "*maskir_internal7"
3580 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3581 (compare:CC
3582 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r,r")
3583 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
3584 (and:SI (not:SI (match_dup 2))
3585 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3586 (const_int 0)))
3587 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3588 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3589 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3590 "TARGET_POWER"
3591 "@
3592 maskir. %0,%3,%2
3593 #"
3594 [(set_attr "type" "compare")
3595 (set_attr "length" "4,8")])
3597 (define_split
3598 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3599 (compare:CC
3600 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "")
3601 (match_operand:SI 3 "gpc_reg_operand" ""))
3602 (and:SI (not:SI (match_dup 2))
3603 (match_operand:SI 1 "gpc_reg_operand" "")))
3604 (const_int 0)))
3605 (set (match_operand:SI 0 "gpc_reg_operand" "")
3606 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3607 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3608 "TARGET_POWER && reload_completed"
3609 [(set (match_dup 0)
3610 (ior:SI (and:SI (match_dup 2) (match_dup 3))
3611 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3612 (set (match_dup 4)
3613 (compare:CC (match_dup 0)
3614 (const_int 0)))]
3615 "")
3617 (define_insn "*maskir_internal8"
3618 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3619 (compare:CC
3620 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r,r")
3621 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
3622 (and:SI (not:SI (match_dup 2))
3623 (match_operand:SI 1 "gpc_reg_operand" "0,0")))
3624 (const_int 0)))
3625 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3626 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3627 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3628 "TARGET_POWER"
3629 "@
3630 maskir. %0,%3,%2
3631 #"
3632 [(set_attr "type" "compare")
3633 (set_attr "length" "4,8")])
3635 (define_split
3636 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3637 (compare:CC
3638 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "")
3639 (match_operand:SI 2 "gpc_reg_operand" ""))
3640 (and:SI (not:SI (match_dup 2))
3641 (match_operand:SI 1 "gpc_reg_operand" "")))
3642 (const_int 0)))
3643 (set (match_operand:SI 0 "gpc_reg_operand" "")
3644 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3645 (and:SI (not:SI (match_dup 2)) (match_dup 1))))]
3646 "TARGET_POWER && reload_completed"
3647 [(set (match_dup 0)
3648 (ior:SI (and:SI (match_dup 3) (match_dup 2))
3649 (and:SI (not:SI (match_dup 2)) (match_dup 1))))
3650 (set (match_dup 4)
3651 (compare:CC (match_dup 0)
3652 (const_int 0)))]
3653 "")
3654 \f
3655 ;; Rotate and shift insns, in all their variants. These support shifts,
3656 ;; field inserts and extracts, and various combinations thereof.
3657 (define_expand "insv"
3658 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "")
3659 (match_operand:SI 1 "const_int_operand" "")
3660 (match_operand:SI 2 "const_int_operand" ""))
3661 (match_operand 3 "gpc_reg_operand" ""))]
3662 ""
3663 "
3664 {
3665 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3666 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3667 compiler if the address of the structure is taken later. */
3668 if (GET_CODE (operands[0]) == SUBREG
3669 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3670 FAIL;
3672 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode)
3673 emit_insn (gen_insvdi (operands[0], operands[1], operands[2], operands[3]));
3674 else
3675 emit_insn (gen_insvsi (operands[0], operands[1], operands[2], operands[3]));
3676 DONE;
3677 }")
3679 (define_insn "insvsi"
3680 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3681 (match_operand:SI 1 "const_int_operand" "i")
3682 (match_operand:SI 2 "const_int_operand" "i"))
3683 (match_operand:SI 3 "gpc_reg_operand" "r"))]
3684 ""
3685 "*
3686 {
3687 int start = INTVAL (operands[2]) & 31;
3688 int size = INTVAL (operands[1]) & 31;
3690 operands[4] = GEN_INT (32 - start - size);
3691 operands[1] = GEN_INT (start + size - 1);
3692 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3693 }")
3695 (define_insn "*insvsi_internal1"
3696 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3697 (match_operand:SI 1 "const_int_operand" "i")
3698 (match_operand:SI 2 "const_int_operand" "i"))
3699 (ashift:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3700 (match_operand:SI 4 "const_int_operand" "i")))]
3701 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3702 "*
3703 {
3704 int shift = INTVAL (operands[4]) & 31;
3705 int start = INTVAL (operands[2]) & 31;
3706 int size = INTVAL (operands[1]) & 31;
3708 operands[4] = GEN_INT (shift - start - size);
3709 operands[1] = GEN_INT (start + size - 1);
3710 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3711 }")
3713 (define_insn "*insvsi_internal2"
3714 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3715 (match_operand:SI 1 "const_int_operand" "i")
3716 (match_operand:SI 2 "const_int_operand" "i"))
3717 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3718 (match_operand:SI 4 "const_int_operand" "i")))]
3719 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3720 "*
3721 {
3722 int shift = INTVAL (operands[4]) & 31;
3723 int start = INTVAL (operands[2]) & 31;
3724 int size = INTVAL (operands[1]) & 31;
3726 operands[4] = GEN_INT (32 - shift - start - size);
3727 operands[1] = GEN_INT (start + size - 1);
3728 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3729 }")
3731 (define_insn "*insvsi_internal3"
3732 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3733 (match_operand:SI 1 "const_int_operand" "i")
3734 (match_operand:SI 2 "const_int_operand" "i"))
3735 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3736 (match_operand:SI 4 "const_int_operand" "i")))]
3737 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])"
3738 "*
3739 {
3740 int shift = INTVAL (operands[4]) & 31;
3741 int start = INTVAL (operands[2]) & 31;
3742 int size = INTVAL (operands[1]) & 31;
3744 operands[4] = GEN_INT (32 - shift - start - size);
3745 operands[1] = GEN_INT (start + size - 1);
3746 return \"{rlimi|rlwimi} %0,%3,%h4,%h2,%h1\";
3747 }")
3749 (define_insn "*insvsi_internal4"
3750 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
3751 (match_operand:SI 1 "const_int_operand" "i")
3752 (match_operand:SI 2 "const_int_operand" "i"))
3753 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r")
3754 (match_operand:SI 4 "const_int_operand" "i")
3755 (match_operand:SI 5 "const_int_operand" "i")))]
3756 "INTVAL (operands[4]) >= INTVAL (operands[1])"
3757 "*
3758 {
3759 int extract_start = INTVAL (operands[5]) & 31;
3760 int extract_size = INTVAL (operands[4]) & 31;
3761 int insert_start = INTVAL (operands[2]) & 31;
3762 int insert_size = INTVAL (operands[1]) & 31;
3764 /* Align extract field with insert field */
3765 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size);
3766 operands[1] = GEN_INT (insert_start + insert_size - 1);
3767 return \"{rlimi|rlwimi} %0,%3,%h5,%h2,%h1\";
3768 }")
3770 (define_insn "insvdi"
3771 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r")
3772 (match_operand:SI 1 "const_int_operand" "i")
3773 (match_operand:SI 2 "const_int_operand" "i"))
3774 (match_operand:DI 3 "gpc_reg_operand" "r"))]
3775 "TARGET_POWERPC64"
3776 "*
3777 {
3778 int start = INTVAL (operands[2]) & 63;
3779 int size = INTVAL (operands[1]) & 63;
3781 operands[1] = GEN_INT (64 - start - size);
3782 return \"rldimi %0,%3,%H1,%H2\";
3783 }")
3785 (define_expand "extzv"
3786 [(set (match_operand 0 "gpc_reg_operand" "")
3787 (zero_extract (match_operand 1 "gpc_reg_operand" "")
3788 (match_operand:SI 2 "const_int_operand" "")
3789 (match_operand:SI 3 "const_int_operand" "")))]
3790 ""
3791 "
3792 {
3793 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since
3794 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the
3795 compiler if the address of the structure is taken later. */
3796 if (GET_CODE (operands[0]) == SUBREG
3797 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD))
3798 FAIL;
3800 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode)
3801 emit_insn (gen_extzvdi (operands[0], operands[1], operands[2], operands[3]));
3802 else
3803 emit_insn (gen_extzvsi (operands[0], operands[1], operands[2], operands[3]));
3804 DONE;
3805 }")
3807 (define_insn "extzvsi"
3808 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3809 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3810 (match_operand:SI 2 "const_int_operand" "i")
3811 (match_operand:SI 3 "const_int_operand" "i")))]
3812 ""
3813 "*
3814 {
3815 int start = INTVAL (operands[3]) & 31;
3816 int size = INTVAL (operands[2]) & 31;
3818 if (start + size >= 32)
3819 operands[3] = const0_rtx;
3820 else
3821 operands[3] = GEN_INT (start + size);
3822 return \"{rlinm|rlwinm} %0,%1,%3,%s2,31\";
3823 }")
3825 (define_insn "*extzvsi_internal1"
3826 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
3827 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3828 (match_operand:SI 2 "const_int_operand" "i,i")
3829 (match_operand:SI 3 "const_int_operand" "i,i"))
3830 (const_int 0)))
3831 (clobber (match_scratch:SI 4 "=r,r"))]
3832 ""
3833 "*
3834 {
3835 int start = INTVAL (operands[3]) & 31;
3836 int size = INTVAL (operands[2]) & 31;
3838 /* Force split for non-cc0 compare. */
3839 if (which_alternative == 1)
3840 return \"#\";
3842 /* If the bit-field being tested fits in the upper or lower half of a
3843 word, it is possible to use andiu. or andil. to test it. This is
3844 useful because the condition register set-use delay is smaller for
3845 andi[ul]. than for rlinm. This doesn't work when the starting bit
3846 position is 0 because the LT and GT bits may be set wrong. */
3848 if ((start > 0 && start + size <= 16) || start >= 16)
3849 {
3850 operands[3] = GEN_INT (((1 << (16 - (start & 15)))
3851 - (1 << (16 - (start & 15) - size))));
3852 if (start < 16)
3853 return \"{andiu.|andis.} %4,%1,%3\";
3854 else
3855 return \"{andil.|andi.} %4,%1,%3\";
3856 }
3858 if (start + size >= 32)
3859 operands[3] = const0_rtx;
3860 else
3861 operands[3] = GEN_INT (start + size);
3862 return \"{rlinm.|rlwinm.} %4,%1,%3,%s2,31\";
3863 }"
3864 [(set_attr "type" "compare")
3865 (set_attr "length" "4,8")])
3867 (define_split
3868 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
3869 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3870 (match_operand:SI 2 "const_int_operand" "")
3871 (match_operand:SI 3 "const_int_operand" ""))
3872 (const_int 0)))
3873 (clobber (match_scratch:SI 4 ""))]
3874 "reload_completed"
3875 [(set (match_dup 4)
3876 (zero_extract:SI (match_dup 1) (match_dup 2)
3877 (match_dup 3)))
3878 (set (match_dup 0)
3879 (compare:CC (match_dup 4)
3880 (const_int 0)))]
3881 "")
3883 (define_insn "*extzvsi_internal2"
3884 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
3885 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
3886 (match_operand:SI 2 "const_int_operand" "i,i")
3887 (match_operand:SI 3 "const_int_operand" "i,i"))
3888 (const_int 0)))
3889 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
3890 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3891 ""
3892 "*
3893 {
3894 int start = INTVAL (operands[3]) & 31;
3895 int size = INTVAL (operands[2]) & 31;
3897 /* Force split for non-cc0 compare. */
3898 if (which_alternative == 1)
3899 return \"#\";
3901 /* Since we are using the output value, we can't ignore any need for
3902 a shift. The bit-field must end at the LSB. */
3903 if (start >= 16 && start + size == 32)
3904 {
3905 operands[3] = GEN_INT ((1 << size) - 1);
3906 return \"{andil.|andi.} %0,%1,%3\";
3907 }
3909 if (start + size >= 32)
3910 operands[3] = const0_rtx;
3911 else
3912 operands[3] = GEN_INT (start + size);
3913 return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\";
3914 }"
3915 [(set_attr "type" "compare")
3916 (set_attr "length" "4,8")])
3918 (define_split
3919 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
3920 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "")
3921 (match_operand:SI 2 "const_int_operand" "")
3922 (match_operand:SI 3 "const_int_operand" ""))
3923 (const_int 0)))
3924 (set (match_operand:SI 0 "gpc_reg_operand" "")
3925 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
3926 "reload_completed"
3927 [(set (match_dup 0)
3928 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))
3929 (set (match_dup 4)
3930 (compare:CC (match_dup 0)
3931 (const_int 0)))]
3932 "")
3934 (define_insn "extzvdi"
3935 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
3936 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3937 (match_operand:SI 2 "const_int_operand" "i")
3938 (match_operand:SI 3 "const_int_operand" "i")))]
3939 "TARGET_POWERPC64"
3940 "*
3941 {
3942 int start = INTVAL (operands[3]) & 63;
3943 int size = INTVAL (operands[2]) & 63;
3945 if (start + size >= 64)
3946 operands[3] = const0_rtx;
3947 else
3948 operands[3] = GEN_INT (start + size);
3949 operands[2] = GEN_INT (64 - size);
3950 return \"rldicl %0,%1,%3,%2\";
3951 }")
3953 (define_insn "*extzvdi_internal1"
3954 [(set (match_operand:CC 0 "gpc_reg_operand" "=x")
3955 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3956 (match_operand:SI 2 "const_int_operand" "i")
3957 (match_operand:SI 3 "const_int_operand" "i"))
3958 (const_int 0)))
3959 (clobber (match_scratch:DI 4 "=r"))]
3960 "TARGET_POWERPC64"
3961 "*
3962 {
3963 int start = INTVAL (operands[3]) & 63;
3964 int size = INTVAL (operands[2]) & 63;
3966 if (start + size >= 64)
3967 operands[3] = const0_rtx;
3968 else
3969 operands[3] = GEN_INT (start + size);
3970 operands[2] = GEN_INT (64 - size);
3971 return \"rldicl. %4,%1,%3,%2\";
3972 }")
3974 (define_insn "*extzvdi_internal2"
3975 [(set (match_operand:CC 4 "gpc_reg_operand" "=x")
3976 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r")
3977 (match_operand:SI 2 "const_int_operand" "i")
3978 (match_operand:SI 3 "const_int_operand" "i"))
3979 (const_int 0)))
3980 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
3981 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))]
3982 "TARGET_POWERPC64"
3983 "*
3984 {
3985 int start = INTVAL (operands[3]) & 63;
3986 int size = INTVAL (operands[2]) & 63;
3988 if (start + size >= 64)
3989 operands[3] = const0_rtx;
3990 else
3991 operands[3] = GEN_INT (start + size);
3992 operands[2] = GEN_INT (64 - size);
3993 return \"rldicl. %0,%1,%3,%2\";
3994 }")
3996 (define_insn "rotlsi3"
3997 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
3998 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
3999 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4000 ""
4001 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffffffff")
4003 (define_insn "*rotlsi3_internal2"
4004 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4005 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4006 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4007 (const_int 0)))
4008 (clobber (match_scratch:SI 3 "=r,r"))]
4009 ""
4010 "@
4011 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff
4012 #"
4013 [(set_attr "type" "delayed_compare")
4014 (set_attr "length" "4,8")])
4016 (define_split
4017 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4018 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4019 (match_operand:SI 2 "reg_or_cint_operand" ""))
4020 (const_int 0)))
4021 (clobber (match_scratch:SI 3 ""))]
4022 "reload_completed"
4023 [(set (match_dup 3)
4024 (rotate:SI (match_dup 1) (match_dup 2)))
4025 (set (match_dup 0)
4026 (compare:CC (match_dup 3)
4027 (const_int 0)))]
4028 "")
4030 (define_insn "*rotlsi3_internal3"
4031 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4032 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4033 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4034 (const_int 0)))
4035 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4036 (rotate:SI (match_dup 1) (match_dup 2)))]
4037 ""
4038 "@
4039 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff
4040 #"
4041 [(set_attr "type" "delayed_compare")
4042 (set_attr "length" "4,8")])
4044 (define_split
4045 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4046 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4047 (match_operand:SI 2 "reg_or_cint_operand" ""))
4048 (const_int 0)))
4049 (set (match_operand:SI 0 "gpc_reg_operand" "")
4050 (rotate:SI (match_dup 1) (match_dup 2)))]
4051 "reload_completed"
4052 [(set (match_dup 0)
4053 (rotate:SI (match_dup 1) (match_dup 2)))
4054 (set (match_dup 3)
4055 (compare:CC (match_dup 0)
4056 (const_int 0)))]
4057 "")
4059 (define_insn "*rotlsi3_internal4"
4060 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4061 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4062 (match_operand:SI 2 "reg_or_cint_operand" "ri"))
4063 (match_operand:SI 3 "mask_operand" "n")))]
4064 ""
4065 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3")
4067 (define_insn "*rotlsi3_internal5"
4068 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4069 (compare:CC (and:SI
4070 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4071 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4072 (match_operand:SI 3 "mask_operand" "n,n"))
4073 (const_int 0)))
4074 (clobber (match_scratch:SI 4 "=r,r"))]
4075 ""
4076 "@
4077 {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3
4078 #"
4079 [(set_attr "type" "delayed_compare")
4080 (set_attr "length" "4,8")])
4082 (define_split
4083 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4084 (compare:CC (and:SI
4085 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4086 (match_operand:SI 2 "reg_or_cint_operand" ""))
4087 (match_operand:SI 3 "mask_operand" ""))
4088 (const_int 0)))
4089 (clobber (match_scratch:SI 4 ""))]
4090 "reload_completed"
4091 [(set (match_dup 4)
4092 (and:SI (rotate:SI (match_dup 1)
4093 (match_dup 2))
4094 (match_dup 3)))
4095 (set (match_dup 0)
4096 (compare:CC (match_dup 4)
4097 (const_int 0)))]
4098 "")
4100 (define_insn "*rotlsi3_internal6"
4101 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4102 (compare:CC (and:SI
4103 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4104 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4105 (match_operand:SI 3 "mask_operand" "n,n"))
4106 (const_int 0)))
4107 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4108 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4109 ""
4110 "@
4111 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3
4112 #"
4113 [(set_attr "type" "delayed_compare")
4114 (set_attr "length" "4,8")])
4116 (define_split
4117 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4118 (compare:CC (and:SI
4119 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4120 (match_operand:SI 2 "reg_or_cint_operand" ""))
4121 (match_operand:SI 3 "mask_operand" ""))
4122 (const_int 0)))
4123 (set (match_operand:SI 0 "gpc_reg_operand" "")
4124 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4125 "reload_completed"
4126 [(set (match_dup 0)
4127 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4128 (set (match_dup 4)
4129 (compare:CC (match_dup 0)
4130 (const_int 0)))]
4131 "")
4133 (define_insn "*rotlsi3_internal7"
4134 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4135 (zero_extend:SI
4136 (subreg:QI
4137 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4138 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4139 ""
4140 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xff")
4142 (define_insn "*rotlsi3_internal8"
4143 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4144 (compare:CC (zero_extend:SI
4145 (subreg:QI
4146 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4147 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
4148 (const_int 0)))
4149 (clobber (match_scratch:SI 3 "=r,r"))]
4150 ""
4151 "@
4152 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xff
4153 #"
4154 [(set_attr "type" "delayed_compare")
4155 (set_attr "length" "4,8")])
4157 (define_split
4158 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4159 (compare:CC (zero_extend:SI
4160 (subreg:QI
4161 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4162 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4163 (const_int 0)))
4164 (clobber (match_scratch:SI 3 ""))]
4165 "reload_completed"
4166 [(set (match_dup 3)
4167 (zero_extend:SI (subreg:QI
4168 (rotate:SI (match_dup 1)
4169 (match_dup 2)) 0)))
4170 (set (match_dup 0)
4171 (compare:CC (match_dup 3)
4172 (const_int 0)))]
4173 "")
4175 (define_insn "*rotlsi3_internal9"
4176 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4177 (compare:CC (zero_extend:SI
4178 (subreg:QI
4179 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4180 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
4181 (const_int 0)))
4182 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4183 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4184 ""
4185 "@
4186 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xff
4187 #"
4188 [(set_attr "type" "delayed_compare")
4189 (set_attr "length" "4,8")])
4191 (define_split
4192 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4193 (compare:CC (zero_extend:SI
4194 (subreg:QI
4195 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4196 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4197 (const_int 0)))
4198 (set (match_operand:SI 0 "gpc_reg_operand" "")
4199 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4200 "reload_completed"
4201 [(set (match_dup 0)
4202 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4203 (set (match_dup 3)
4204 (compare:CC (match_dup 0)
4205 (const_int 0)))]
4206 "")
4208 (define_insn "*rotlsi3_internal10"
4209 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4210 (zero_extend:SI
4211 (subreg:HI
4212 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4213 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
4214 ""
4215 "{rl%I2nm|rlw%I2nm} %0,%1,%h2,0xffff")
4217 (define_insn "*rotlsi3_internal11"
4218 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4219 (compare:CC (zero_extend:SI
4220 (subreg:HI
4221 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4222 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
4223 (const_int 0)))
4224 (clobber (match_scratch:SI 3 "=r,r"))]
4225 ""
4226 "@
4227 {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffff
4228 #"
4229 [(set_attr "type" "delayed_compare")
4230 (set_attr "length" "4,8")])
4232 (define_split
4233 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4234 (compare:CC (zero_extend:SI
4235 (subreg:HI
4236 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4237 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4238 (const_int 0)))
4239 (clobber (match_scratch:SI 3 ""))]
4240 "reload_completed"
4241 [(set (match_dup 3)
4242 (zero_extend:SI (subreg:HI
4243 (rotate:SI (match_dup 1)
4244 (match_dup 2)) 0)))
4245 (set (match_dup 0)
4246 (compare:CC (match_dup 3)
4247 (const_int 0)))]
4248 "")
4250 (define_insn "*rotlsi3_internal12"
4251 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4252 (compare:CC (zero_extend:SI
4253 (subreg:HI
4254 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4255 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) 0))
4256 (const_int 0)))
4257 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4258 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4259 ""
4260 "@
4261 {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffff
4262 #"
4263 [(set_attr "type" "delayed_compare")
4264 (set_attr "length" "4,8")])
4266 (define_split
4267 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4268 (compare:CC (zero_extend:SI
4269 (subreg:HI
4270 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "")
4271 (match_operand:SI 2 "reg_or_cint_operand" "")) 0))
4272 (const_int 0)))
4273 (set (match_operand:SI 0 "gpc_reg_operand" "")
4274 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
4275 "reload_completed"
4276 [(set (match_dup 0)
4277 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))
4278 (set (match_dup 3)
4279 (compare:CC (match_dup 0)
4280 (const_int 0)))]
4281 "")
4283 ;; Note that we use "sle." instead of "sl." so that we can set
4284 ;; SHIFT_COUNT_TRUNCATED.
4286 (define_expand "ashlsi3"
4287 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4288 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4289 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4290 ""
4291 "
4292 {
4293 if (TARGET_POWER)
4294 emit_insn (gen_ashlsi3_power (operands[0], operands[1], operands[2]));
4295 else
4296 emit_insn (gen_ashlsi3_no_power (operands[0], operands[1], operands[2]));
4297 DONE;
4298 }")
4300 (define_insn "ashlsi3_power"
4301 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4302 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4303 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4304 (clobber (match_scratch:SI 3 "=q,X"))]
4305 "TARGET_POWER"
4306 "@
4307 sle %0,%1,%2
4308 {sli|slwi} %0,%1,%h2")
4310 (define_insn "ashlsi3_no_power"
4311 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4312 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4313 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4314 "! TARGET_POWER"
4315 "{sl|slw}%I2 %0,%1,%h2")
4317 (define_insn ""
4318 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4319 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4320 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4321 (const_int 0)))
4322 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4323 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4324 "TARGET_POWER"
4325 "@
4326 sle. %3,%1,%2
4327 {sli.|slwi.} %3,%1,%h2
4328 #
4329 #"
4330 [(set_attr "type" "delayed_compare")
4331 (set_attr "length" "4,4,8,8")])
4333 (define_split
4334 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4335 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4336 (match_operand:SI 2 "reg_or_cint_operand" ""))
4337 (const_int 0)))
4338 (clobber (match_scratch:SI 3 ""))
4339 (clobber (match_scratch:SI 4 ""))]
4340 "TARGET_POWER && reload_completed"
4341 [(parallel [(set (match_dup 3)
4342 (ashift:SI (match_dup 1) (match_dup 2)))
4343 (clobber (match_dup 4))])
4344 (set (match_dup 0)
4345 (compare:CC (match_dup 3)
4346 (const_int 0)))]
4347 "")
4349 (define_insn ""
4350 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4351 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4352 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4353 (const_int 0)))
4354 (clobber (match_scratch:SI 3 "=r,r"))]
4355 "! TARGET_POWER && ! TARGET_POWERPC64"
4356 "@
4357 {sl|slw}%I2. %3,%1,%h2
4358 #"
4359 [(set_attr "type" "delayed_compare")
4360 (set_attr "length" "4,8")])
4362 (define_split
4363 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4364 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4365 (match_operand:SI 2 "reg_or_cint_operand" ""))
4366 (const_int 0)))
4367 (clobber (match_scratch:SI 3 ""))]
4368 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
4369 [(set (match_dup 3)
4370 (ashift:SI (match_dup 1) (match_dup 2)))
4371 (set (match_dup 0)
4372 (compare:CC (match_dup 3)
4373 (const_int 0)))]
4374 "")
4376 (define_insn ""
4377 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4378 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4379 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4380 (const_int 0)))
4381 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4382 (ashift:SI (match_dup 1) (match_dup 2)))
4383 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4384 "TARGET_POWER"
4385 "@
4386 sle. %0,%1,%2
4387 {sli.|slwi.} %0,%1,%h2
4388 #
4389 #"
4390 [(set_attr "type" "delayed_compare")
4391 (set_attr "length" "4,4,8,8")])
4393 (define_split
4394 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4395 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4396 (match_operand:SI 2 "reg_or_cint_operand" ""))
4397 (const_int 0)))
4398 (set (match_operand:SI 0 "gpc_reg_operand" "")
4399 (ashift:SI (match_dup 1) (match_dup 2)))
4400 (clobber (match_scratch:SI 4 ""))]
4401 "TARGET_POWER && reload_completed"
4402 [(parallel [(set (match_dup 0)
4403 (ashift:SI (match_dup 1) (match_dup 2)))
4404 (clobber (match_dup 4))])
4405 (set (match_dup 3)
4406 (compare:CC (match_dup 0)
4407 (const_int 0)))]
4408 "")
4410 (define_insn ""
4411 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4412 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4413 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
4414 (const_int 0)))
4415 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4416 (ashift:SI (match_dup 1) (match_dup 2)))]
4417 "! TARGET_POWER && ! TARGET_POWERPC64"
4418 "@
4419 {sl|slw}%I2. %0,%1,%h2
4420 #"
4421 [(set_attr "type" "delayed_compare")
4422 (set_attr "length" "4,8")])
4424 (define_split
4425 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4426 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4427 (match_operand:SI 2 "reg_or_cint_operand" ""))
4428 (const_int 0)))
4429 (set (match_operand:SI 0 "gpc_reg_operand" "")
4430 (ashift:SI (match_dup 1) (match_dup 2)))]
4431 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
4432 [(set (match_dup 0)
4433 (ashift:SI (match_dup 1) (match_dup 2)))
4434 (set (match_dup 3)
4435 (compare:CC (match_dup 0)
4436 (const_int 0)))]
4437 "")
4439 (define_insn ""
4440 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4441 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4442 (match_operand:SI 2 "const_int_operand" "i"))
4443 (match_operand:SI 3 "mask_operand" "n")))]
4444 "includes_lshift_p (operands[2], operands[3])"
4445 "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3")
4447 (define_insn ""
4448 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4449 (compare:CC
4450 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4451 (match_operand:SI 2 "const_int_operand" "i,i"))
4452 (match_operand:SI 3 "mask_operand" "n,n"))
4453 (const_int 0)))
4454 (clobber (match_scratch:SI 4 "=r,r"))]
4455 "includes_lshift_p (operands[2], operands[3])"
4456 "@
4457 {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3
4458 #"
4459 [(set_attr "type" "delayed_compare")
4460 (set_attr "length" "4,8")])
4462 (define_split
4463 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4464 (compare:CC
4465 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4466 (match_operand:SI 2 "const_int_operand" ""))
4467 (match_operand:SI 3 "mask_operand" ""))
4468 (const_int 0)))
4469 (clobber (match_scratch:SI 4 ""))]
4470 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4471 [(set (match_dup 4)
4472 (and:SI (ashift:SI (match_dup 1) (match_dup 2))
4473 (match_dup 3)))
4474 (set (match_dup 0)
4475 (compare:CC (match_dup 4)
4476 (const_int 0)))]
4477 "")
4479 (define_insn ""
4480 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4481 (compare:CC
4482 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4483 (match_operand:SI 2 "const_int_operand" "i,i"))
4484 (match_operand:SI 3 "mask_operand" "n,n"))
4485 (const_int 0)))
4486 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4487 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4488 "includes_lshift_p (operands[2], operands[3])"
4489 "@
4490 {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3
4491 #"
4492 [(set_attr "type" "delayed_compare")
4493 (set_attr "length" "4,8")])
4495 (define_split
4496 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4497 (compare:CC
4498 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "")
4499 (match_operand:SI 2 "const_int_operand" ""))
4500 (match_operand:SI 3 "mask_operand" ""))
4501 (const_int 0)))
4502 (set (match_operand:SI 0 "gpc_reg_operand" "")
4503 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4504 "includes_lshift_p (operands[2], operands[3]) && reload_completed"
4505 [(set (match_dup 0)
4506 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4507 (set (match_dup 4)
4508 (compare:CC (match_dup 0)
4509 (const_int 0)))]
4510 "")
4512 ;; The AIX assembler mis-handles "sri x,x,0", so write that case as
4513 ;; "sli x,x,0".
4514 (define_expand "lshrsi3"
4515 [(use (match_operand:SI 0 "gpc_reg_operand" ""))
4516 (use (match_operand:SI 1 "gpc_reg_operand" ""))
4517 (use (match_operand:SI 2 "reg_or_cint_operand" ""))]
4518 ""
4519 "
4520 {
4521 if (TARGET_POWER)
4522 emit_insn (gen_lshrsi3_power (operands[0], operands[1], operands[2]));
4523 else
4524 emit_insn (gen_lshrsi3_no_power (operands[0], operands[1], operands[2]));
4525 DONE;
4526 }")
4528 (define_insn "lshrsi3_power"
4529 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
4530 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
4531 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i")))
4532 (clobber (match_scratch:SI 3 "=q,X,X"))]
4533 "TARGET_POWER"
4534 "@
4535 sre %0,%1,%2
4536 mr %0,%1
4537 {s%A2i|s%A2wi} %0,%1,%h2")
4539 (define_insn "lshrsi3_no_power"
4540 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4541 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4542 (match_operand:SI 2 "reg_or_cint_operand" "O,ri")))]
4543 "! TARGET_POWER"
4544 "@
4545 mr %0,%1
4546 {sr|srw}%I2 %0,%1,%h2")
4548 (define_insn ""
4549 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4550 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4551 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4552 (const_int 0)))
4553 (clobber (match_scratch:SI 3 "=r,X,r,r,X,r"))
4554 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4555 "TARGET_POWER"
4556 "@
4557 sre. %3,%1,%2
4558 mr. %1,%1
4559 {s%A2i.|s%A2wi.} %3,%1,%h2
4560 #
4561 #
4562 #"
4563 [(set_attr "type" "delayed_compare")
4564 (set_attr "length" "4,4,4,8,8,8")])
4566 (define_split
4567 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4568 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4569 (match_operand:SI 2 "reg_or_cint_operand" ""))
4570 (const_int 0)))
4571 (clobber (match_scratch:SI 3 ""))
4572 (clobber (match_scratch:SI 4 ""))]
4573 "TARGET_POWER && reload_completed"
4574 [(parallel [(set (match_dup 3)
4575 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4576 (clobber (match_dup 4))])
4577 (set (match_dup 0)
4578 (compare:CC (match_dup 3)
4579 (const_int 0)))]
4580 "")
4582 (define_insn ""
4583 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4584 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4585 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4586 (const_int 0)))
4587 (clobber (match_scratch:SI 3 "=X,r,X,r"))]
4588 "! TARGET_POWER && ! TARGET_POWERPC64"
4589 "@
4590 mr. %1,%1
4591 {sr|srw}%I2. %3,%1,%h2
4592 #
4593 #"
4594 [(set_attr "type" "delayed_compare")
4595 (set_attr "length" "4,4,8,8")])
4597 (define_split
4598 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4599 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4600 (match_operand:SI 2 "reg_or_cint_operand" ""))
4601 (const_int 0)))
4602 (clobber (match_scratch:SI 3 ""))]
4603 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
4604 [(set (match_dup 3)
4605 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4606 (set (match_dup 0)
4607 (compare:CC (match_dup 3)
4608 (const_int 0)))]
4609 "")
4611 (define_insn ""
4612 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
4613 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
4614 (match_operand:SI 2 "reg_or_cint_operand" "r,O,i,r,O,i"))
4615 (const_int 0)))
4616 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
4617 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4618 (clobber (match_scratch:SI 4 "=q,X,X,q,X,X"))]
4619 "TARGET_POWER"
4620 "@
4621 sre. %0,%1,%2
4622 mr. %0,%1
4623 {s%A2i.|s%A2wi.} %0,%1,%h2
4624 #
4625 #
4626 #"
4627 [(set_attr "type" "delayed_compare")
4628 (set_attr "length" "4,4,4,8,8,8")])
4630 (define_split
4631 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4632 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4633 (match_operand:SI 2 "reg_or_cint_operand" ""))
4634 (const_int 0)))
4635 (set (match_operand:SI 0 "gpc_reg_operand" "")
4636 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4637 (clobber (match_scratch:SI 4 ""))]
4638 "TARGET_POWER && reload_completed"
4639 [(parallel [(set (match_dup 0)
4640 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4641 (clobber (match_dup 4))])
4642 (set (match_dup 3)
4643 (compare:CC (match_dup 0)
4644 (const_int 0)))]
4645 "")
4647 (define_insn ""
4648 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
4649 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4650 (match_operand:SI 2 "reg_or_cint_operand" "O,ri,O,ri"))
4651 (const_int 0)))
4652 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
4653 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4654 "! TARGET_POWER && ! TARGET_POWERPC64"
4655 "@
4656 mr. %0,%1
4657 {sr|srw}%I2. %0,%1,%h2
4658 #
4659 #"
4660 [(set_attr "type" "delayed_compare")
4661 (set_attr "length" "4,4,8,8")])
4663 (define_split
4664 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4665 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4666 (match_operand:SI 2 "reg_or_cint_operand" ""))
4667 (const_int 0)))
4668 (set (match_operand:SI 0 "gpc_reg_operand" "")
4669 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
4670 "! TARGET_POWER && ! TARGET_POWERPC64 && reload_completed"
4671 [(set (match_dup 0)
4672 (lshiftrt:SI (match_dup 1) (match_dup 2)))
4673 (set (match_dup 3)
4674 (compare:CC (match_dup 0)
4675 (const_int 0)))]
4676 "")
4678 (define_insn ""
4679 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4680 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4681 (match_operand:SI 2 "const_int_operand" "i"))
4682 (match_operand:SI 3 "mask_operand" "n")))]
4683 "includes_rshift_p (operands[2], operands[3])"
4684 "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3")
4686 (define_insn ""
4687 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4688 (compare:CC
4689 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4690 (match_operand:SI 2 "const_int_operand" "i,i"))
4691 (match_operand:SI 3 "mask_operand" "n,n"))
4692 (const_int 0)))
4693 (clobber (match_scratch:SI 4 "=r,r"))]
4694 "includes_rshift_p (operands[2], operands[3])"
4695 "@
4696 {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3
4697 #"
4698 [(set_attr "type" "delayed_compare")
4699 (set_attr "length" "4,8")])
4701 (define_split
4702 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4703 (compare:CC
4704 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4705 (match_operand:SI 2 "const_int_operand" ""))
4706 (match_operand:SI 3 "mask_operand" ""))
4707 (const_int 0)))
4708 (clobber (match_scratch:SI 4 ""))]
4709 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4710 [(set (match_dup 4)
4711 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2))
4712 (match_dup 3)))
4713 (set (match_dup 0)
4714 (compare:CC (match_dup 4)
4715 (const_int 0)))]
4716 "")
4718 (define_insn ""
4719 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
4720 (compare:CC
4721 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4722 (match_operand:SI 2 "const_int_operand" "i,i"))
4723 (match_operand:SI 3 "mask_operand" "n,n"))
4724 (const_int 0)))
4725 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4726 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4727 "includes_rshift_p (operands[2], operands[3])"
4728 "@
4729 {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3
4730 #"
4731 [(set_attr "type" "delayed_compare")
4732 (set_attr "length" "4,8")])
4734 (define_split
4735 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
4736 (compare:CC
4737 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4738 (match_operand:SI 2 "const_int_operand" ""))
4739 (match_operand:SI 3 "mask_operand" ""))
4740 (const_int 0)))
4741 (set (match_operand:SI 0 "gpc_reg_operand" "")
4742 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4743 "includes_rshift_p (operands[2], operands[3]) && reload_completed"
4744 [(set (match_dup 0)
4745 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4746 (set (match_dup 4)
4747 (compare:CC (match_dup 0)
4748 (const_int 0)))]
4749 "")
4751 (define_insn ""
4752 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4753 (zero_extend:SI
4754 (subreg:QI
4755 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4756 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4757 "includes_rshift_p (operands[2], GEN_INT (255))"
4758 "{rlinm|rlwinm} %0,%1,%s2,0xff")
4760 (define_insn ""
4761 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4762 (compare:CC
4763 (zero_extend:SI
4764 (subreg:QI
4765 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4766 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4767 (const_int 0)))
4768 (clobber (match_scratch:SI 3 "=r,r"))]
4769 "includes_rshift_p (operands[2], GEN_INT (255))"
4770 "@
4771 {rlinm.|rlwinm.} %3,%1,%s2,0xff
4772 #"
4773 [(set_attr "type" "delayed_compare")
4774 (set_attr "length" "4,8")])
4776 (define_split
4777 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4778 (compare:CC
4779 (zero_extend:SI
4780 (subreg:QI
4781 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4782 (match_operand:SI 2 "const_int_operand" "")) 0))
4783 (const_int 0)))
4784 (clobber (match_scratch:SI 3 ""))]
4785 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4786 [(set (match_dup 3)
4787 (zero_extend:SI (subreg:QI
4788 (lshiftrt:SI (match_dup 1)
4789 (match_dup 2)) 0)))
4790 (set (match_dup 0)
4791 (compare:CC (match_dup 3)
4792 (const_int 0)))]
4793 "")
4795 (define_insn ""
4796 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4797 (compare:CC
4798 (zero_extend:SI
4799 (subreg:QI
4800 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4801 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4802 (const_int 0)))
4803 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4804 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4805 "includes_rshift_p (operands[2], GEN_INT (255))"
4806 "@
4807 {rlinm.|rlwinm.} %0,%1,%s2,0xff
4808 #"
4809 [(set_attr "type" "delayed_compare")
4810 (set_attr "length" "4,8")])
4812 (define_split
4813 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4814 (compare:CC
4815 (zero_extend:SI
4816 (subreg:QI
4817 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4818 (match_operand:SI 2 "const_int_operand" "")) 0))
4819 (const_int 0)))
4820 (set (match_operand:SI 0 "gpc_reg_operand" "")
4821 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4822 "includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed"
4823 [(set (match_dup 0)
4824 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4825 (set (match_dup 3)
4826 (compare:CC (match_dup 0)
4827 (const_int 0)))]
4828 "")
4830 (define_insn ""
4831 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4832 (zero_extend:SI
4833 (subreg:HI
4834 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4835 (match_operand:SI 2 "const_int_operand" "i")) 0)))]
4836 "includes_rshift_p (operands[2], GEN_INT (65535))"
4837 "{rlinm|rlwinm} %0,%1,%s2,0xffff")
4839 (define_insn ""
4840 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
4841 (compare:CC
4842 (zero_extend:SI
4843 (subreg:HI
4844 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4845 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4846 (const_int 0)))
4847 (clobber (match_scratch:SI 3 "=r,r"))]
4848 "includes_rshift_p (operands[2], GEN_INT (65535))"
4849 "@
4850 {rlinm.|rlwinm.} %3,%1,%s2,0xffff
4851 #"
4852 [(set_attr "type" "delayed_compare")
4853 (set_attr "length" "4,8")])
4855 (define_split
4856 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4857 (compare:CC
4858 (zero_extend:SI
4859 (subreg:HI
4860 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4861 (match_operand:SI 2 "const_int_operand" "")) 0))
4862 (const_int 0)))
4863 (clobber (match_scratch:SI 3 ""))]
4864 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4865 [(set (match_dup 3)
4866 (zero_extend:SI (subreg:HI
4867 (lshiftrt:SI (match_dup 1)
4868 (match_dup 2)) 0)))
4869 (set (match_dup 0)
4870 (compare:CC (match_dup 3)
4871 (const_int 0)))]
4872 "")
4874 (define_insn ""
4875 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
4876 (compare:CC
4877 (zero_extend:SI
4878 (subreg:HI
4879 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4880 (match_operand:SI 2 "const_int_operand" "i,i")) 0))
4881 (const_int 0)))
4882 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4883 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4884 "includes_rshift_p (operands[2], GEN_INT (65535))"
4885 "@
4886 {rlinm.|rlwinm.} %0,%1,%s2,0xffff
4887 #"
4888 [(set_attr "type" "delayed_compare")
4889 (set_attr "length" "4,8")])
4891 (define_split
4892 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
4893 (compare:CC
4894 (zero_extend:SI
4895 (subreg:HI
4896 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4897 (match_operand:SI 2 "const_int_operand" "")) 0))
4898 (const_int 0)))
4899 (set (match_operand:SI 0 "gpc_reg_operand" "")
4900 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
4901 "includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed"
4902 [(set (match_dup 0)
4903 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))
4904 (set (match_dup 3)
4905 (compare:CC (match_dup 0)
4906 (const_int 0)))]
4907 "")
4909 (define_insn ""
4910 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4911 (const_int 1)
4912 (match_operand:SI 1 "gpc_reg_operand" "r"))
4913 (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4914 (const_int 31)))]
4915 "TARGET_POWER"
4916 "rrib %0,%1,%2")
4918 (define_insn ""
4919 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4920 (const_int 1)
4921 (match_operand:SI 1 "gpc_reg_operand" "r"))
4922 (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4923 (const_int 31)))]
4924 "TARGET_POWER"
4925 "rrib %0,%1,%2")
4927 (define_insn ""
4928 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
4929 (const_int 1)
4930 (match_operand:SI 1 "gpc_reg_operand" "r"))
4931 (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
4932 (const_int 1)
4933 (const_int 0)))]
4934 "TARGET_POWER"
4935 "rrib %0,%1,%2")
4937 (define_expand "ashrsi3"
4938 [(set (match_operand:SI 0 "gpc_reg_operand" "")
4939 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4940 (match_operand:SI 2 "reg_or_cint_operand" "")))]
4941 ""
4942 "
4943 {
4944 if (TARGET_POWER)
4945 emit_insn (gen_ashrsi3_power (operands[0], operands[1], operands[2]));
4946 else
4947 emit_insn (gen_ashrsi3_no_power (operands[0], operands[1], operands[2]));
4948 DONE;
4949 }")
4951 (define_insn "ashrsi3_power"
4952 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
4953 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
4954 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
4955 (clobber (match_scratch:SI 3 "=q,X"))]
4956 "TARGET_POWER"
4957 "@
4958 srea %0,%1,%2
4959 {srai|srawi} %0,%1,%h2")
4961 (define_insn "ashrsi3_no_power"
4962 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
4963 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
4964 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
4965 "! TARGET_POWER"
4966 "{sra|sraw}%I2 %0,%1,%h2")
4968 (define_insn ""
4969 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
4970 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
4971 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
4972 (const_int 0)))
4973 (clobber (match_scratch:SI 3 "=r,r,r,r"))
4974 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
4975 "TARGET_POWER"
4976 "@
4977 srea. %3,%1,%2
4978 {srai.|srawi.} %3,%1,%h2
4979 #
4980 #"
4981 [(set_attr "type" "delayed_compare")
4982 (set_attr "length" "4,4,8,8")])
4984 (define_split
4985 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
4986 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
4987 (match_operand:SI 2 "reg_or_cint_operand" ""))
4988 (const_int 0)))
4989 (clobber (match_scratch:SI 3 ""))
4990 (clobber (match_scratch:SI 4 ""))]
4991 "TARGET_POWER && reload_completed"
4992 [(parallel [(set (match_dup 3)
4993 (ashiftrt:SI (match_dup 1) (match_dup 2)))
4994 (clobber (match_dup 4))])
4995 (set (match_dup 0)
4996 (compare:CC (match_dup 3)
4997 (const_int 0)))]
4998 "")
5000 (define_insn ""
5001 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
5002 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5003 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
5004 (const_int 0)))
5005 (clobber (match_scratch:SI 3 "=r,r"))]
5006 "! TARGET_POWER"
5007 "@
5008 {sra|sraw}%I2. %3,%1,%h2
5009 #"
5010 [(set_attr "type" "delayed_compare")
5011 (set_attr "length" "4,8")])
5013 (define_split
5014 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
5015 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5016 (match_operand:SI 2 "reg_or_cint_operand" ""))
5017 (const_int 0)))
5018 (clobber (match_scratch:SI 3 ""))]
5019 "! TARGET_POWER && reload_completed"
5020 [(set (match_dup 3)
5021 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5022 (set (match_dup 0)
5023 (compare:CC (match_dup 3)
5024 (const_int 0)))]
5025 "")
5027 (define_insn ""
5028 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
5029 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
5030 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
5031 (const_int 0)))
5032 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
5033 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5034 (clobber (match_scratch:SI 4 "=q,X,q,X"))]
5035 "TARGET_POWER"
5036 "@
5037 srea. %0,%1,%2
5038 {srai.|srawi.} %0,%1,%h2
5039 #
5040 #"
5041 [(set_attr "type" "delayed_compare")
5042 (set_attr "length" "4,4,8,8")])
5044 (define_split
5045 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5046 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5047 (match_operand:SI 2 "reg_or_cint_operand" ""))
5048 (const_int 0)))
5049 (set (match_operand:SI 0 "gpc_reg_operand" "")
5050 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5051 (clobber (match_scratch:SI 4 ""))]
5052 "TARGET_POWER && reload_completed"
5053 [(parallel [(set (match_dup 0)
5054 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5055 (clobber (match_dup 4))])
5056 (set (match_dup 3)
5057 (compare:CC (match_dup 0)
5058 (const_int 0)))]
5059 "")
5061 (define_insn ""
5062 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
5063 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
5064 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
5065 (const_int 0)))
5066 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
5067 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5068 "! TARGET_POWER"
5069 "@
5070 {sra|sraw}%I2. %0,%1,%h2
5071 #"
5072 [(set_attr "type" "delayed_compare")
5073 (set_attr "length" "4,8")])
5074 \f
5075 (define_split
5076 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
5077 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "")
5078 (match_operand:SI 2 "reg_or_cint_operand" ""))
5079 (const_int 0)))
5080 (set (match_operand:SI 0 "gpc_reg_operand" "")
5081 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
5082 "! TARGET_POWER && reload_completed"
5083 [(set (match_dup 0)
5084 (ashiftrt:SI (match_dup 1) (match_dup 2)))
5085 (set (match_dup 3)
5086 (compare:CC (match_dup 0)
5087 (const_int 0)))]
5088 "")
5090 ;; Floating-point insns, excluding normal data motion.
5091 ;;
5092 ;; PowerPC has a full set of single-precision floating point instructions.
5093 ;;
5094 ;; For the POWER architecture, we pretend that we have both SFmode and
5095 ;; DFmode insns, while, in fact, all fp insns are actually done in double.
5096 ;; The only conversions we will do will be when storing to memory. In that
5097 ;; case, we will use the "frsp" instruction before storing.
5098 ;;
5099 ;; Note that when we store into a single-precision memory location, we need to
5100 ;; use the frsp insn first. If the register being stored isn't dead, we
5101 ;; need a scratch register for the frsp. But this is difficult when the store
5102 ;; is done by reload. It is not incorrect to do the frsp on the register in
5103 ;; this case, we just lose precision that we would have otherwise gotten but
5104 ;; is not guaranteed. Perhaps this should be tightened up at some point.
5106 (define_insn "extendsfdf2"
5107 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5108 (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5109 "TARGET_HARD_FLOAT && TARGET_FPRS"
5110 "*
5111 {
5112 if (REGNO (operands[0]) == REGNO (operands[1]))
5113 return \"\";
5114 else
5115 return \"fmr %0,%1\";
5116 }"
5117 [(set_attr "type" "fp")])
5119 (define_insn "truncdfsf2"
5120 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5121 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5122 "TARGET_HARD_FLOAT && TARGET_FPRS"
5123 "frsp %0,%1"
5124 [(set_attr "type" "fp")])
5126 (define_insn "aux_truncdfsf2"
5127 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5128 (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))]
5129 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5130 "frsp %0,%1"
5131 [(set_attr "type" "fp")])
5133 (define_expand "negsf2"
5134 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5135 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5136 "TARGET_HARD_FLOAT"
5137 "")
5139 (define_insn "*negsf2"
5140 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5141 (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5142 "TARGET_HARD_FLOAT && TARGET_FPRS"
5143 "fneg %0,%1"
5144 [(set_attr "type" "fp")])
5146 (define_expand "abssf2"
5147 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5148 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5149 "TARGET_HARD_FLOAT"
5150 "")
5152 (define_insn "*abssf2"
5153 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5154 (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5155 "TARGET_HARD_FLOAT && TARGET_FPRS"
5156 "fabs %0,%1"
5157 [(set_attr "type" "fp")])
5159 (define_insn ""
5160 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5161 (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
5162 "TARGET_HARD_FLOAT && TARGET_FPRS"
5163 "fnabs %0,%1"
5164 [(set_attr "type" "fp")])
5166 (define_expand "addsf3"
5167 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5168 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5169 (match_operand:SF 2 "gpc_reg_operand" "")))]
5170 "TARGET_HARD_FLOAT"
5171 "")
5173 (define_insn ""
5174 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5175 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5176 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5177 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5178 "fadds %0,%1,%2"
5179 [(set_attr "type" "fp")])
5181 (define_insn ""
5182 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5183 (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5184 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5185 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5186 "{fa|fadd} %0,%1,%2"
5187 [(set_attr "type" "fp")])
5189 (define_expand "subsf3"
5190 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5191 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "")
5192 (match_operand:SF 2 "gpc_reg_operand" "")))]
5193 "TARGET_HARD_FLOAT"
5194 "")
5196 (define_insn ""
5197 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5198 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5199 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5200 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5201 "fsubs %0,%1,%2"
5202 [(set_attr "type" "fp")])
5204 (define_insn ""
5205 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5206 (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5207 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5208 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5209 "{fs|fsub} %0,%1,%2"
5210 [(set_attr "type" "fp")])
5212 (define_expand "mulsf3"
5213 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5214 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "")
5215 (match_operand:SF 2 "gpc_reg_operand" "")))]
5216 "TARGET_HARD_FLOAT"
5217 "")
5219 (define_insn ""
5220 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5221 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5222 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5223 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5224 "fmuls %0,%1,%2"
5225 [(set_attr "type" "fp")])
5227 (define_insn ""
5228 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5229 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5230 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5231 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5232 "{fm|fmul} %0,%1,%2"
5233 [(set_attr "type" "dmul")])
5235 (define_expand "divsf3"
5236 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5237 (div:SF (match_operand:SF 1 "gpc_reg_operand" "")
5238 (match_operand:SF 2 "gpc_reg_operand" "")))]
5239 "TARGET_HARD_FLOAT"
5240 "")
5242 (define_insn ""
5243 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5244 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5245 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5246 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5247 "fdivs %0,%1,%2"
5248 [(set_attr "type" "sdiv")])
5250 (define_insn ""
5251 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5252 (div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
5253 (match_operand:SF 2 "gpc_reg_operand" "f")))]
5254 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
5255 "{fd|fdiv} %0,%1,%2"
5256 [(set_attr "type" "ddiv")])
5258 (define_insn ""
5259 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5260 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5261 (match_operand:SF 2 "gpc_reg_operand" "f"))
5262 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5263 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5264 "fmadds %0,%1,%2,%3"
5265 [(set_attr "type" "fp")])
5267 (define_insn ""
5268 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5269 (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5270 (match_operand:SF 2 "gpc_reg_operand" "f"))
5271 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5272 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5273 "{fma|fmadd} %0,%1,%2,%3"
5274 [(set_attr "type" "dmul")])
5276 (define_insn ""
5277 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5278 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5279 (match_operand:SF 2 "gpc_reg_operand" "f"))
5280 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5281 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5282 "fmsubs %0,%1,%2,%3"
5283 [(set_attr "type" "fp")])
5285 (define_insn ""
5286 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5287 (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5288 (match_operand:SF 2 "gpc_reg_operand" "f"))
5289 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5290 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5291 "{fms|fmsub} %0,%1,%2,%3"
5292 [(set_attr "type" "dmul")])
5294 (define_insn ""
5295 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5296 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5297 (match_operand:SF 2 "gpc_reg_operand" "f"))
5298 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5299 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5300 && HONOR_SIGNED_ZEROS (SFmode)"
5301 "fnmadds %0,%1,%2,%3"
5302 [(set_attr "type" "fp")])
5304 (define_insn ""
5305 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5306 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5307 (match_operand:SF 2 "gpc_reg_operand" "f"))
5308 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5309 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5310 && ! HONOR_SIGNED_ZEROS (SFmode)"
5311 "fnmadds %0,%1,%2,%3"
5312 [(set_attr "type" "fp")])
5314 (define_insn ""
5315 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5316 (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5317 (match_operand:SF 2 "gpc_reg_operand" "f"))
5318 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5319 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5320 "{fnma|fnmadd} %0,%1,%2,%3"
5321 [(set_attr "type" "dmul")])
5323 (define_insn ""
5324 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5325 (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f"))
5326 (match_operand:SF 2 "gpc_reg_operand" "f"))
5327 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5328 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5329 && ! HONOR_SIGNED_ZEROS (SFmode)"
5330 "{fnma|fnmadd} %0,%1,%2,%3"
5331 [(set_attr "type" "dmul")])
5333 (define_insn ""
5334 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5335 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5336 (match_operand:SF 2 "gpc_reg_operand" "f"))
5337 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5338 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5339 && HONOR_SIGNED_ZEROS (SFmode)"
5340 "fnmsubs %0,%1,%2,%3"
5341 [(set_attr "type" "fp")])
5343 (define_insn ""
5344 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5345 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5346 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5347 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5348 "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5349 && ! HONOR_SIGNED_ZEROS (SFmode)"
5350 "fnmsubs %0,%1,%2,%3"
5351 [(set_attr "type" "fp")])
5353 (define_insn ""
5354 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5355 (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5356 (match_operand:SF 2 "gpc_reg_operand" "f"))
5357 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
5358 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5359 "{fnms|fnmsub} %0,%1,%2,%3"
5360 [(set_attr "type" "dmul")])
5362 (define_insn ""
5363 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5364 (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f")
5365 (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
5366 (match_operand:SF 2 "gpc_reg_operand" "f"))))]
5367 "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5368 && ! HONOR_SIGNED_ZEROS (SFmode)"
5369 "{fnms|fnmsub} %0,%1,%2,%3"
5370 [(set_attr "type" "fp")])
5372 (define_expand "sqrtsf2"
5373 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5374 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))]
5375 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5376 "")
5378 (define_insn ""
5379 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5380 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5381 "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5382 "fsqrts %0,%1"
5383 [(set_attr "type" "ssqrt")])
5385 (define_insn ""
5386 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5387 (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
5388 "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS"
5389 "fsqrt %0,%1"
5390 [(set_attr "type" "dsqrt")])
5392 ;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a
5393 ;; fsel instruction and some auxiliary computations. Then we just have a
5394 ;; single DEFINE_INSN for fsel and the define_splits to make them if made by
5395 ;; combine.
5396 (define_expand "maxsf3"
5397 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5398 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5399 (match_operand:SF 2 "gpc_reg_operand" ""))
5400 (match_dup 1)
5401 (match_dup 2)))]
5402 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5403 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5405 (define_expand "minsf3"
5406 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5407 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "")
5408 (match_operand:SF 2 "gpc_reg_operand" ""))
5409 (match_dup 2)
5410 (match_dup 1)))]
5411 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5412 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5414 (define_split
5415 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5416 (match_operator:SF 3 "min_max_operator"
5417 [(match_operand:SF 1 "gpc_reg_operand" "")
5418 (match_operand:SF 2 "gpc_reg_operand" "")]))]
5419 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5420 [(const_int 0)]
5421 "
5422 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5423 operands[1], operands[2]);
5424 DONE;
5425 }")
5427 (define_expand "movsicc"
5428 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5429 (if_then_else:SI (match_operand 1 "comparison_operator" "")
5430 (match_operand:SI 2 "gpc_reg_operand" "")
5431 (match_operand:SI 3 "gpc_reg_operand" "")))]
5432 "TARGET_ISEL"
5433 "
5434 {
5435 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5436 DONE;
5437 else
5438 FAIL;
5439 }")
5441 ;; We use the BASE_REGS for the isel input operands because, if rA is
5442 ;; 0, the value of 0 is placed in rD upon truth. Similarly for rB
5443 ;; because we may switch the operands and rB may end up being rA.
5444 ;;
5445 ;; We need 2 patterns: an unsigned and a signed pattern. We could
5446 ;; leave out the mode in operand 4 and use one pattern, but reload can
5447 ;; change the mode underneath our feet and then gets confused trying
5448 ;; to reload the value.
5449 (define_insn "isel_signed"
5450 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5451 (if_then_else:SI
5452 (match_operator 1 "comparison_operator"
5453 [(match_operand:CC 4 "cc_reg_operand" "y")
5454 (const_int 0)])
5455 (match_operand:SI 2 "gpc_reg_operand" "b")
5456 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5457 "TARGET_ISEL"
5458 "*
5459 { return output_isel (operands); }"
5460 [(set_attr "length" "4")])
5462 (define_insn "isel_unsigned"
5463 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5464 (if_then_else:SI
5465 (match_operator 1 "comparison_operator"
5466 [(match_operand:CCUNS 4 "cc_reg_operand" "y")
5467 (const_int 0)])
5468 (match_operand:SI 2 "gpc_reg_operand" "b")
5469 (match_operand:SI 3 "gpc_reg_operand" "b")))]
5470 "TARGET_ISEL"
5471 "*
5472 { return output_isel (operands); }"
5473 [(set_attr "length" "4")])
5475 (define_expand "movsfcc"
5476 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5477 (if_then_else:SF (match_operand 1 "comparison_operator" "")
5478 (match_operand:SF 2 "gpc_reg_operand" "")
5479 (match_operand:SF 3 "gpc_reg_operand" "")))]
5480 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5481 "
5482 {
5483 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5484 DONE;
5485 else
5486 FAIL;
5487 }")
5489 (define_insn "*fselsfsf4"
5490 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5491 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5492 (match_operand:SF 4 "zero_fp_constant" "F"))
5493 (match_operand:SF 2 "gpc_reg_operand" "f")
5494 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5495 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5496 "fsel %0,%1,%2,%3"
5497 [(set_attr "type" "fp")])
5499 (define_insn "*fseldfsf4"
5500 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5501 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5502 (match_operand:DF 4 "zero_fp_constant" "F"))
5503 (match_operand:SF 2 "gpc_reg_operand" "f")
5504 (match_operand:SF 3 "gpc_reg_operand" "f")))]
5505 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5506 "fsel %0,%1,%2,%3"
5507 [(set_attr "type" "fp")])
5509 (define_insn "negdf2"
5510 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5511 (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5512 "TARGET_HARD_FLOAT && TARGET_FPRS"
5513 "fneg %0,%1"
5514 [(set_attr "type" "fp")])
5516 (define_insn "absdf2"
5517 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5518 (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5519 "TARGET_HARD_FLOAT && TARGET_FPRS"
5520 "fabs %0,%1"
5521 [(set_attr "type" "fp")])
5523 (define_insn ""
5524 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5525 (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
5526 "TARGET_HARD_FLOAT && TARGET_FPRS"
5527 "fnabs %0,%1"
5528 [(set_attr "type" "fp")])
5530 (define_insn "adddf3"
5531 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5532 (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5533 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5534 "TARGET_HARD_FLOAT && TARGET_FPRS"
5535 "{fa|fadd} %0,%1,%2"
5536 [(set_attr "type" "fp")])
5538 (define_insn "subdf3"
5539 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5540 (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5541 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5542 "TARGET_HARD_FLOAT && TARGET_FPRS"
5543 "{fs|fsub} %0,%1,%2"
5544 [(set_attr "type" "fp")])
5546 (define_insn "muldf3"
5547 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5548 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5549 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5550 "TARGET_HARD_FLOAT && TARGET_FPRS"
5551 "{fm|fmul} %0,%1,%2"
5552 [(set_attr "type" "dmul")])
5554 (define_insn "divdf3"
5555 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5556 (div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
5557 (match_operand:DF 2 "gpc_reg_operand" "f")))]
5558 "TARGET_HARD_FLOAT && TARGET_FPRS"
5559 "{fd|fdiv} %0,%1,%2"
5560 [(set_attr "type" "ddiv")])
5562 (define_insn ""
5563 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5564 (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5565 (match_operand:DF 2 "gpc_reg_operand" "f"))
5566 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5567 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5568 "{fma|fmadd} %0,%1,%2,%3"
5569 [(set_attr "type" "dmul")])
5571 (define_insn ""
5572 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5573 (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5574 (match_operand:DF 2 "gpc_reg_operand" "f"))
5575 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5576 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
5577 "{fms|fmsub} %0,%1,%2,%3"
5578 [(set_attr "type" "dmul")])
5580 (define_insn ""
5581 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5582 (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5583 (match_operand:DF 2 "gpc_reg_operand" "f"))
5584 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5585 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5586 && HONOR_SIGNED_ZEROS (DFmode)"
5587 "{fnma|fnmadd} %0,%1,%2,%3"
5588 [(set_attr "type" "dmul")])
5590 (define_insn ""
5591 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5592 (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f"))
5593 (match_operand:DF 2 "gpc_reg_operand" "f"))
5594 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5595 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5596 && ! HONOR_SIGNED_ZEROS (DFmode)"
5597 "{fnma|fnmadd} %0,%1,%2,%3"
5598 [(set_attr "type" "dmul")])
5600 (define_insn ""
5601 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5602 (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5603 (match_operand:DF 2 "gpc_reg_operand" "f"))
5604 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
5605 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5606 && HONOR_SIGNED_ZEROS (DFmode)"
5607 "{fnms|fnmsub} %0,%1,%2,%3"
5608 [(set_attr "type" "dmul")])
5610 (define_insn ""
5611 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5612 (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f")
5613 (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
5614 (match_operand:DF 2 "gpc_reg_operand" "f"))))]
5615 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
5616 && ! HONOR_SIGNED_ZEROS (DFmode)"
5617 "{fnms|fnmsub} %0,%1,%2,%3"
5618 [(set_attr "type" "dmul")])
5620 (define_insn "sqrtdf2"
5621 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5622 (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
5623 "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS"
5624 "fsqrt %0,%1"
5625 [(set_attr "type" "dsqrt")])
5627 ;; The conditional move instructions allow us to perform max and min
5628 ;; operations even when
5630 (define_expand "maxdf3"
5631 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5632 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5633 (match_operand:DF 2 "gpc_reg_operand" ""))
5634 (match_dup 1)
5635 (match_dup 2)))]
5636 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5637 "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}")
5639 (define_expand "mindf3"
5640 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5641 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "")
5642 (match_operand:DF 2 "gpc_reg_operand" ""))
5643 (match_dup 2)
5644 (match_dup 1)))]
5645 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5646 "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}")
5648 (define_split
5649 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5650 (match_operator:DF 3 "min_max_operator"
5651 [(match_operand:DF 1 "gpc_reg_operand" "")
5652 (match_operand:DF 2 "gpc_reg_operand" "")]))]
5653 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5654 [(const_int 0)]
5655 "
5656 { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]),
5657 operands[1], operands[2]);
5658 DONE;
5659 }")
5661 (define_expand "movdfcc"
5662 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5663 (if_then_else:DF (match_operand 1 "comparison_operator" "")
5664 (match_operand:DF 2 "gpc_reg_operand" "")
5665 (match_operand:DF 3 "gpc_reg_operand" "")))]
5666 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5667 "
5668 {
5669 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3]))
5670 DONE;
5671 else
5672 FAIL;
5673 }")
5675 (define_insn "*fseldfdf4"
5676 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5677 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "f")
5678 (match_operand:DF 4 "zero_fp_constant" "F"))
5679 (match_operand:DF 2 "gpc_reg_operand" "f")
5680 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5681 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS"
5682 "fsel %0,%1,%2,%3"
5683 [(set_attr "type" "fp")])
5685 (define_insn "*fselsfdf4"
5686 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5687 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f")
5688 (match_operand:SF 4 "zero_fp_constant" "F"))
5689 (match_operand:DF 2 "gpc_reg_operand" "f")
5690 (match_operand:DF 3 "gpc_reg_operand" "f")))]
5691 "TARGET_PPC_GFXOPT"
5692 "fsel %0,%1,%2,%3"
5693 [(set_attr "type" "fp")])
5694 \f
5695 ;; Conversions to and from floating-point.
5697 (define_expand "fixunssfsi2"
5698 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5699 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "gpc_reg_operand" ""))))]
5700 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5701 "")
5703 (define_expand "fix_truncsfsi2"
5704 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5705 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))]
5706 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5707 "")
5709 ; For each of these conversions, there is a define_expand, a define_insn
5710 ; with a '#' template, and a define_split (with C code). The idea is
5711 ; to allow constant folding with the template of the define_insn,
5712 ; then to have the insns split later (between sched1 and final).
5714 (define_expand "floatsidf2"
5715 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5716 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5717 (use (match_dup 2))
5718 (use (match_dup 3))
5719 (clobber (match_dup 4))
5720 (clobber (match_dup 5))
5721 (clobber (match_dup 6))])]
5722 "TARGET_HARD_FLOAT && TARGET_FPRS"
5723 "
5724 {
5725 if (TARGET_POWERPC64)
5726 {
5727 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5728 rtx t1 = gen_reg_rtx (DImode);
5729 rtx t2 = gen_reg_rtx (DImode);
5730 emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
5731 DONE;
5732 }
5734 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5735 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode));
5736 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5737 operands[5] = gen_reg_rtx (DFmode);
5738 operands[6] = gen_reg_rtx (SImode);
5739 }")
5741 (define_insn "*floatsidf2_internal"
5742 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5743 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5744 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5745 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5746 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5747 (clobber (match_operand:DF 5 "gpc_reg_operand" "=f"))
5748 (clobber (match_operand:SI 6 "gpc_reg_operand" "=r"))]
5749 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5750 "#"
5751 [(set_attr "length" "24")])
5753 (define_split
5754 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5755 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5756 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5757 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5758 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5759 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5760 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5761 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5762 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5763 (float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5764 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5765 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5766 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5767 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))
5768 (clobber (match_operand:SI 6 "gpc_reg_operand" ""))]
5769 "
5770 {
5771 rtx lowword, highword;
5772 if (GET_CODE (operands[4]) != MEM)
5773 abort();
5774 highword = XEXP (operands[4], 0);
5775 lowword = plus_constant (highword, 4);
5776 if (! WORDS_BIG_ENDIAN)
5777 {
5778 rtx tmp;
5779 tmp = highword; highword = lowword; lowword = tmp;
5780 }
5782 emit_insn (gen_xorsi3 (operands[6], operands[1],
5783 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff)));
5784 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[6]);
5785 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5786 emit_move_insn (operands[5], operands[4]);
5787 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5788 DONE;
5789 }")
5791 (define_expand "floatunssisf2"
5792 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5793 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5794 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5795 "")
5797 (define_expand "floatunssidf2"
5798 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "")
5799 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5800 (use (match_dup 2))
5801 (use (match_dup 3))
5802 (clobber (match_dup 4))
5803 (clobber (match_dup 5))])]
5804 "TARGET_HARD_FLOAT && TARGET_FPRS"
5805 "
5806 {
5807 if (TARGET_POWERPC64)
5808 {
5809 rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5810 rtx t1 = gen_reg_rtx (DImode);
5811 rtx t2 = gen_reg_rtx (DImode);
5812 emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
5813 t1, t2));
5814 DONE;
5815 }
5817 operands[2] = force_reg (SImode, GEN_INT (0x43300000));
5818 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode));
5819 operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
5820 operands[5] = gen_reg_rtx (DFmode);
5821 }")
5823 (define_insn "*floatunssidf2_internal"
5824 [(set (match_operand:DF 0 "gpc_reg_operand" "=&f")
5825 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5826 (use (match_operand:SI 2 "gpc_reg_operand" "r"))
5827 (use (match_operand:DF 3 "gpc_reg_operand" "f"))
5828 (clobber (match_operand:DF 4 "memory_operand" "=o"))
5829 (clobber (match_operand:DF 5 "gpc_reg_operand" "=f"))]
5830 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5831 "#"
5832 [(set_attr "length" "20")])
5834 (define_split
5835 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5836 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5837 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5838 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5839 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5840 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5841 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5842 [(set (match_operand:DF 0 "gpc_reg_operand" "")
5843 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "")))
5844 (use (match_operand:SI 2 "gpc_reg_operand" ""))
5845 (use (match_operand:DF 3 "gpc_reg_operand" ""))
5846 (clobber (match_operand:DF 4 "offsettable_mem_operand" ""))
5847 (clobber (match_operand:DF 5 "gpc_reg_operand" ""))]
5848 "
5849 {
5850 rtx lowword, highword;
5851 if (GET_CODE (operands[4]) != MEM)
5852 abort();
5853 highword = XEXP (operands[4], 0);
5854 lowword = plus_constant (highword, 4);
5855 if (! WORDS_BIG_ENDIAN)
5856 {
5857 rtx tmp;
5858 tmp = highword; highword = lowword; lowword = tmp;
5859 }
5861 emit_move_insn (gen_rtx_MEM (SImode, lowword), operands[1]);
5862 emit_move_insn (gen_rtx_MEM (SImode, highword), operands[2]);
5863 emit_move_insn (operands[5], operands[4]);
5864 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3]));
5865 DONE;
5866 }")
5868 (define_expand "fix_truncdfsi2"
5869 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
5870 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5871 (clobber (match_dup 2))
5872 (clobber (match_dup 3))])]
5873 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5874 "
5875 {
5876 operands[2] = gen_reg_rtx (DImode);
5877 operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
5878 }")
5880 (define_insn "*fix_truncdfsi2_internal"
5881 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
5882 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
5883 (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
5884 (clobber (match_operand:DI 3 "memory_operand" "=o"))]
5885 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5886 "#"
5887 [(set_attr "length" "16")])
5889 (define_split
5890 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5891 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5892 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5893 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5894 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5895 [(set (match_operand:SI 0 "gpc_reg_operand" "")
5896 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
5897 (clobber (match_operand:DI 2 "gpc_reg_operand" ""))
5898 (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))]
5899 "
5900 {
5901 rtx lowword;
5902 if (GET_CODE (operands[3]) != MEM)
5903 abort();
5904 lowword = XEXP (operands[3], 0);
5905 if (WORDS_BIG_ENDIAN)
5906 lowword = plus_constant (lowword, 4);
5908 emit_insn (gen_fctiwz (operands[2], operands[1]));
5909 emit_move_insn (operands[3], operands[2]);
5910 emit_move_insn (operands[0], gen_rtx_MEM (SImode, lowword));
5911 DONE;
5912 }")
5914 ; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] 10))
5915 ; rather than (set (subreg:SI (reg)) (fix:SI ...))
5916 ; because the first makes it clear that operand 0 is not live
5917 ; before the instruction.
5918 (define_insn "fctiwz"
5919 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5920 (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 10))]
5921 "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
5922 "{fcirz|fctiwz} %0,%1"
5923 [(set_attr "type" "fp")])
5925 (define_expand "floatsisf2"
5926 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5927 (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))]
5928 "TARGET_HARD_FLOAT && !TARGET_FPRS"
5929 "")
5931 (define_insn "floatdidf2"
5932 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5933 (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
5934 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5935 "fcfid %0,%1"
5936 [(set_attr "type" "fp")])
5938 (define_insn_and_split "floatsidf_ppc64"
5939 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5940 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5941 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5942 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5943 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5944 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5945 "#"
5946 ""
5947 [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
5948 (set (match_dup 2) (match_dup 3))
5949 (set (match_dup 4) (match_dup 2))
5950 (set (match_dup 0) (float:DF (match_dup 4)))]
5951 "")
5953 (define_insn_and_split "floatunssidf_ppc64"
5954 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
5955 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
5956 (clobber (match_operand:DI 2 "memory_operand" "=o"))
5957 (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
5958 (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
5959 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5960 "#"
5961 ""
5962 [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
5963 (set (match_dup 2) (match_dup 3))
5964 (set (match_dup 4) (match_dup 2))
5965 (set (match_dup 0) (float:DF (match_dup 4)))]
5966 "")
5968 (define_insn "fix_truncdfdi2"
5969 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
5970 (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
5971 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5972 "fctidz %0,%1"
5973 [(set_attr "type" "fp")])
5975 (define_expand "floatdisf2"
5976 [(set (match_operand:SF 0 "gpc_reg_operand" "")
5977 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))]
5978 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5979 "
5980 {
5981 if (!flag_unsafe_math_optimizations)
5982 {
5983 rtx label = gen_label_rtx ();
5984 emit_insn (gen_floatdisf2_internal2 (operands[1], label));
5985 emit_label (label);
5986 }
5987 emit_insn (gen_floatdisf2_internal1 (operands[0], operands[1]));
5988 DONE;
5989 }")
5991 ;; This is not IEEE compliant if rounding mode is "round to nearest".
5992 ;; If the DI->DF conversion is inexact, then it's possible to suffer
5993 ;; from double rounding.
5994 (define_insn_and_split "floatdisf2_internal1"
5995 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
5996 (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f")))
5997 (clobber (match_scratch:DF 2 "=f"))]
5998 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
5999 "#"
6000 "&& reload_completed"
6001 [(set (match_dup 2)
6002 (float:DF (match_dup 1)))
6003 (set (match_dup 0)
6004 (float_truncate:SF (match_dup 2)))]
6005 "")
6007 ;; Twiddles bits to avoid double rounding.
6008 ;; Bits that might be trucated when converting to DFmode are replaced
6009 ;; by a bit that won't be lost at that stage, but is below the SFmode
6010 ;; rounding position.
6011 (define_expand "floatdisf2_internal2"
6012 [(parallel [(set (match_dup 4)
6013 (compare:CC (and:DI (match_operand:DI 0 "" "")
6014 (const_int 2047))
6015 (const_int 0)))
6016 (set (match_dup 2) (and:DI (match_dup 0) (const_int 2047)))
6017 (clobber (match_scratch:CC 7 ""))])
6018 (set (match_dup 3) (ashiftrt:DI (match_dup 0) (const_int 53)))
6019 (set (match_dup 3) (plus:DI (match_dup 3) (const_int 1)))
6020 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0))
6021 (label_ref (match_operand:DI 1 "" ""))
6022 (pc)))
6023 (set (match_dup 5) (compare:CCUNS (match_dup 3) (const_int 2)))
6024 (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
6025 (label_ref (match_dup 1))
6026 (pc)))
6027 (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 2)))
6028 (set (match_dup 0) (ior:DI (match_dup 0) (const_int 2048)))]
6029 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS"
6030 "
6031 {
6032 operands[2] = gen_reg_rtx (DImode);
6033 operands[3] = gen_reg_rtx (DImode);
6034 operands[4] = gen_reg_rtx (CCmode);
6035 operands[5] = gen_reg_rtx (CCUNSmode);
6036 }")
6037 \f
6038 ;; Define the DImode operations that can be done in a small number
6039 ;; of instructions. The & constraints are to prevent the register
6040 ;; allocator from allocating registers that overlap with the inputs
6041 ;; (for example, having an input in 7,8 and an output in 6,7). We
6042 ;; also allow for the output being the same as one of the inputs.
6044 (define_insn "*adddi3_noppc64"
6045 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r")
6046 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0")
6047 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))]
6048 "! TARGET_POWERPC64"
6049 "*
6050 {
6051 if (WORDS_BIG_ENDIAN)
6052 return (GET_CODE (operands[2])) != CONST_INT
6053 ? \"{a|addc} %L0,%L1,%L2\;{ae|adde} %0,%1,%2\"
6054 : \"{ai|addic} %L0,%L1,%2\;{a%G2e|add%G2e} %0,%1\";
6055 else
6056 return (GET_CODE (operands[2])) != CONST_INT
6057 ? \"{a|addc} %0,%1,%2\;{ae|adde} %L0,%L1,%L2\"
6058 : \"{ai|addic} %0,%1,%2\;{a%G2e|add%G2e} %L0,%L1\";
6059 }"
6060 [(set_attr "length" "8")])
6062 (define_insn "*subdi3_noppc64"
6063 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r")
6064 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I")
6065 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))]
6066 "! TARGET_POWERPC64"
6067 "*
6068 {
6069 if (WORDS_BIG_ENDIAN)
6070 return (GET_CODE (operands[1]) != CONST_INT)
6071 ? \"{sf|subfc} %L0,%L2,%L1\;{sfe|subfe} %0,%2,%1\"
6072 : \"{sfi|subfic} %L0,%L2,%1\;{sf%G1e|subf%G1e} %0,%2\";
6073 else
6074 return (GET_CODE (operands[1]) != CONST_INT)
6075 ? \"{sf|subfc} %0,%2,%1\;{sfe|subfe} %L0,%L2,%L1\"
6076 : \"{sfi|subfic} %0,%2,%1\;{sf%G1e|subf%G1e} %L0,%L2\";
6077 }"
6078 [(set_attr "length" "8")])
6080 (define_insn "*negdi2_noppc64"
6081 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6082 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))]
6083 "! TARGET_POWERPC64"
6084 "*
6085 {
6086 return (WORDS_BIG_ENDIAN)
6087 ? \"{sfi|subfic} %L0,%L1,0\;{sfze|subfze} %0,%1\"
6088 : \"{sfi|subfic} %0,%1,0\;{sfze|subfze} %L0,%L1\";
6089 }"
6090 [(set_attr "length" "8")])
6092 (define_expand "mulsidi3"
6093 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6094 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6095 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6096 "! TARGET_POWERPC64"
6097 "
6098 {
6099 if (! TARGET_POWER && ! TARGET_POWERPC)
6100 {
6101 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6102 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6103 emit_insn (gen_mull_call ());
6104 if (WORDS_BIG_ENDIAN)
6105 emit_move_insn (operands[0], gen_rtx_REG (DImode, 3));
6106 else
6107 {
6108 emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
6109 gen_rtx_REG (SImode, 3));
6110 emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
6111 gen_rtx_REG (SImode, 4));
6112 }
6113 DONE;
6114 }
6115 else if (TARGET_POWER)
6116 {
6117 emit_insn (gen_mulsidi3_mq (operands[0], operands[1], operands[2]));
6118 DONE;
6119 }
6120 }")
6122 (define_insn "mulsidi3_mq"
6123 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6124 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6125 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6126 (clobber (match_scratch:SI 3 "=q"))]
6127 "TARGET_POWER"
6128 "mul %0,%1,%2\;mfmq %L0"
6129 [(set_attr "type" "imul")
6130 (set_attr "length" "8")])
6132 (define_insn "*mulsidi3_no_mq"
6133 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6134 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6135 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6136 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6137 "*
6138 {
6139 return (WORDS_BIG_ENDIAN)
6140 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
6141 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
6142 }"
6143 [(set_attr "type" "imul")
6144 (set_attr "length" "8")])
6146 (define_split
6147 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6148 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6149 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6150 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6151 [(set (match_dup 3)
6152 (truncate:SI
6153 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
6154 (sign_extend:DI (match_dup 2)))
6155 (const_int 32))))
6156 (set (match_dup 4)
6157 (mult:SI (match_dup 1)
6158 (match_dup 2)))]
6159 "
6160 {
6161 int endian = (WORDS_BIG_ENDIAN == 0);
6162 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6163 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6164 }")
6166 (define_expand "umulsidi3"
6167 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6168 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6169 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6170 "TARGET_POWERPC && ! TARGET_POWERPC64"
6171 "
6172 {
6173 if (TARGET_POWER)
6174 {
6175 emit_insn (gen_umulsidi3_mq (operands[0], operands[1], operands[2]));
6176 DONE;
6177 }
6178 }")
6180 (define_insn "umulsidi3_mq"
6181 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6182 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6183 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
6184 (clobber (match_scratch:SI 3 "=q"))]
6185 "TARGET_POWERPC && TARGET_POWER"
6186 "*
6187 {
6188 return (WORDS_BIG_ENDIAN)
6189 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6190 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6191 }"
6192 [(set_attr "type" "imul")
6193 (set_attr "length" "8")])
6195 (define_insn "*umulsidi3_no_mq"
6196 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
6197 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r"))
6198 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
6199 "TARGET_POWERPC && ! TARGET_POWER && ! TARGET_POWERPC64"
6200 "*
6201 {
6202 return (WORDS_BIG_ENDIAN)
6203 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
6204 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
6205 }"
6206 [(set_attr "type" "imul")
6207 (set_attr "length" "8")])
6209 (define_split
6210 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6211 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
6212 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))]
6213 "TARGET_POWERPC && ! TARGET_POWERPC64 && reload_completed"
6214 [(set (match_dup 3)
6215 (truncate:SI
6216 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
6217 (zero_extend:DI (match_dup 2)))
6218 (const_int 32))))
6219 (set (match_dup 4)
6220 (mult:SI (match_dup 1)
6221 (match_dup 2)))]
6222 "
6223 {
6224 int endian = (WORDS_BIG_ENDIAN == 0);
6225 operands[3] = operand_subword (operands[0], endian, 0, DImode);
6226 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode);
6227 }")
6229 (define_expand "smulsi3_highpart"
6230 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6231 (truncate:SI
6232 (lshiftrt:DI (mult:DI (sign_extend:DI
6233 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6234 (sign_extend:DI
6235 (match_operand:SI 2 "gpc_reg_operand" "r")))
6236 (const_int 32))))]
6237 ""
6238 "
6239 {
6240 if (! TARGET_POWER && ! TARGET_POWERPC)
6241 {
6242 emit_move_insn (gen_rtx_REG (SImode, 3), operands[1]);
6243 emit_move_insn (gen_rtx_REG (SImode, 4), operands[2]);
6244 emit_insn (gen_mulh_call ());
6245 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3));
6246 DONE;
6247 }
6248 else if (TARGET_POWER)
6249 {
6250 emit_insn (gen_smulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6251 DONE;
6252 }
6253 }")
6255 (define_insn "smulsi3_highpart_mq"
6256 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6257 (truncate:SI
6258 (lshiftrt:DI (mult:DI (sign_extend:DI
6259 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6260 (sign_extend:DI
6261 (match_operand:SI 2 "gpc_reg_operand" "r")))
6262 (const_int 32))))
6263 (clobber (match_scratch:SI 3 "=q"))]
6264 "TARGET_POWER"
6265 "mul %0,%1,%2"
6266 [(set_attr "type" "imul")])
6268 (define_insn "*smulsi3_highpart_no_mq"
6269 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6270 (truncate:SI
6271 (lshiftrt:DI (mult:DI (sign_extend:DI
6272 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6273 (sign_extend:DI
6274 (match_operand:SI 2 "gpc_reg_operand" "r")))
6275 (const_int 32))))]
6276 "TARGET_POWERPC && ! TARGET_POWER"
6277 "mulhw %0,%1,%2"
6278 [(set_attr "type" "imul")])
6280 (define_expand "umulsi3_highpart"
6281 [(set (match_operand:SI 0 "gpc_reg_operand" "")
6282 (truncate:SI
6283 (lshiftrt:DI (mult:DI (zero_extend:DI
6284 (match_operand:SI 1 "gpc_reg_operand" ""))
6285 (zero_extend:DI
6286 (match_operand:SI 2 "gpc_reg_operand" "")))
6287 (const_int 32))))]
6288 "TARGET_POWERPC"
6289 "
6290 {
6291 if (TARGET_POWER)
6292 {
6293 emit_insn (gen_umulsi3_highpart_mq (operands[0], operands[1], operands[2]));
6294 DONE;
6295 }
6296 }")
6298 (define_insn "umulsi3_highpart_mq"
6299 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6300 (truncate:SI
6301 (lshiftrt:DI (mult:DI (zero_extend:DI
6302 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6303 (zero_extend:DI
6304 (match_operand:SI 2 "gpc_reg_operand" "r")))
6305 (const_int 32))))
6306 (clobber (match_scratch:SI 3 "=q"))]
6307 "TARGET_POWERPC && TARGET_POWER"
6308 "mulhwu %0,%1,%2"
6309 [(set_attr "type" "imul")])
6311 (define_insn "*umulsi3_highpart_no_mq"
6312 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
6313 (truncate:SI
6314 (lshiftrt:DI (mult:DI (zero_extend:DI
6315 (match_operand:SI 1 "gpc_reg_operand" "%r"))
6316 (zero_extend:DI
6317 (match_operand:SI 2 "gpc_reg_operand" "r")))
6318 (const_int 32))))]
6319 "TARGET_POWERPC && ! TARGET_POWER"
6320 "mulhwu %0,%1,%2"
6321 [(set_attr "type" "imul")])
6323 ;; If operands 0 and 2 are in the same register, we have a problem. But
6324 ;; operands 0 and 1 (the usual case) can be in the same register. That's
6325 ;; why we have the strange constraints below.
6326 (define_insn "ashldi3_power"
6327 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6328 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6329 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6330 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6331 "TARGET_POWER"
6332 "@
6333 {sli|slwi} %0,%L1,%h2\;{cal %L0,0(0)|li %L0,0}
6334 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6335 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
6336 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2"
6337 [(set_attr "length" "8")])
6339 (define_insn "lshrdi3_power"
6340 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
6341 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
6342 (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
6343 (clobber (match_scratch:SI 3 "=X,q,q,q"))]
6344 "TARGET_POWER"
6345 "@
6346 {s%A2i|s%A2wi} %L0,%1,%h2\;{cal %0,0(0)|li %0,0}
6347 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6348 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
6349 sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2"
6350 [(set_attr "length" "8")])
6352 ;; Shift by a variable amount is too complex to be worth open-coding. We
6353 ;; just handle shifts by constants.
6354 (define_insn "ashrdi3_power"
6355 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6356 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6357 (match_operand:SI 2 "const_int_operand" "M,i")))
6358 (clobber (match_scratch:SI 3 "=X,q"))]
6359 "TARGET_POWER"
6360 "@
6361 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6362 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2"
6363 [(set_attr "length" "8")])
6365 (define_insn "ashrdi3_no_power"
6366 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
6367 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6368 (match_operand:SI 2 "const_int_operand" "M,i")))]
6369 "TARGET_32BIT && !TARGET_POWER"
6370 "@
6371 {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2
6372 {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2"
6373 [(set_attr "length" "8,12")])
6374 \f
6375 ;; PowerPC64 DImode operations.
6377 (define_expand "adddi3"
6378 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6379 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
6380 (match_operand:DI 2 "reg_or_add_cint64_operand" "")))]
6381 ""
6382 "
6383 {
6384 if (! TARGET_POWERPC64)
6385 {
6386 if (non_short_cint_operand (operands[2], DImode))
6387 FAIL;
6388 }
6389 else
6390 if (GET_CODE (operands[2]) == CONST_INT
6391 && ! add_operand (operands[2], DImode))
6392 {
6393 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
6394 ? operands[0] : gen_reg_rtx (DImode));
6396 HOST_WIDE_INT val = INTVAL (operands[2]);
6397 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
6398 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
6400 if (!CONST_OK_FOR_LETTER_P (rest, 'L'))
6401 FAIL;
6403 /* The ordering here is important for the prolog expander.
6404 When space is allocated from the stack, adding 'low' first may
6405 produce a temporary deallocation (which would be bad). */
6406 emit_insn (gen_adddi3 (tmp, operands[1], GEN_INT (rest)));
6407 emit_insn (gen_adddi3 (operands[0], tmp, GEN_INT (low)));
6408 DONE;
6409 }
6410 }")
6412 ;; Discourage ai/addic because of carry but provide it in an alternative
6413 ;; allowing register zero as source.
6415 (define_insn "*adddi3_internal1"
6416 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,?r,r")
6417 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,b,r,b")
6418 (match_operand:DI 2 "add_operand" "r,I,I,L")))]
6419 "TARGET_POWERPC64"
6420 "@
6421 add %0,%1,%2
6422 addi %0,%1,%2
6423 addic %0,%1,%2
6424 addis %0,%1,%v2")
6426 (define_insn "*adddi3_internal2"
6427 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
6428 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
6429 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
6430 (const_int 0)))
6431 (clobber (match_scratch:DI 3 "=r,r,r,r"))]
6432 "TARGET_POWERPC64"
6433 "@
6434 add. %3,%1,%2
6435 addic. %3,%1,%2
6436 #
6437 #"
6438 [(set_attr "type" "compare")
6439 (set_attr "length" "4,4,8,8")])
6441 (define_split
6442 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6443 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
6444 (match_operand:DI 2 "reg_or_short_operand" ""))
6445 (const_int 0)))
6446 (clobber (match_scratch:DI 3 ""))]
6447 "TARGET_POWERPC64 && reload_completed"
6448 [(set (match_dup 3)
6449 (plus:DI (match_dup 1) (match_dup 2)))
6450 (set (match_dup 0)
6451 (compare:CC (match_dup 3)
6452 (const_int 0)))]
6453 "")
6455 (define_insn "*adddi3_internal3"
6456 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
6457 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r")
6458 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I"))
6459 (const_int 0)))
6460 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
6461 (plus:DI (match_dup 1) (match_dup 2)))]
6462 "TARGET_POWERPC64"
6463 "@
6464 add. %0,%1,%2
6465 addic. %0,%1,%2
6466 #
6467 #"
6468 [(set_attr "type" "compare")
6469 (set_attr "length" "4,4,8,8")])
6471 (define_split
6472 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6473 (compare:CC (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
6474 (match_operand:DI 2 "reg_or_short_operand" ""))
6475 (const_int 0)))
6476 (set (match_operand:DI 0 "gpc_reg_operand" "")
6477 (plus:DI (match_dup 1) (match_dup 2)))]
6478 "TARGET_POWERPC64 && reload_completed"
6479 [(set (match_dup 0)
6480 (plus:DI (match_dup 1) (match_dup 2)))
6481 (set (match_dup 3)
6482 (compare:CC (match_dup 0)
6483 (const_int 0)))]
6484 "")
6486 ;; Split an add that we can't do in one insn into two insns, each of which
6487 ;; does one 16-bit part. This is used by combine. Note that the low-order
6488 ;; add should be last in case the result gets used in an address.
6490 (define_split
6491 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6492 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
6493 (match_operand:DI 2 "non_add_cint_operand" "")))]
6494 "TARGET_POWERPC64"
6495 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
6496 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
6497 "
6498 {
6499 HOST_WIDE_INT val = INTVAL (operands[2]);
6500 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
6501 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode);
6503 operands[4] = GEN_INT (low);
6504 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
6505 operands[3] = GEN_INT (rest);
6506 else if (! no_new_pseudos)
6507 {
6508 operands[3] = gen_reg_rtx (DImode);
6509 emit_move_insn (operands[3], operands[2]);
6510 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
6511 DONE;
6512 }
6513 else
6514 FAIL;
6515 }")
6517 (define_insn "one_cmpldi2"
6518 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6519 (not:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6520 "TARGET_POWERPC64"
6521 "nor %0,%1,%1")
6523 (define_insn ""
6524 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6525 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6526 (const_int 0)))
6527 (clobber (match_scratch:DI 2 "=r,r"))]
6528 "TARGET_POWERPC64"
6529 "@
6530 nor. %2,%1,%1
6531 #"
6532 [(set_attr "type" "compare")
6533 (set_attr "length" "4,8")])
6535 (define_split
6536 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6537 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6538 (const_int 0)))
6539 (clobber (match_scratch:DI 2 ""))]
6540 "TARGET_POWERPC64 && reload_completed"
6541 [(set (match_dup 2)
6542 (not:DI (match_dup 1)))
6543 (set (match_dup 0)
6544 (compare:CC (match_dup 2)
6545 (const_int 0)))]
6546 "")
6548 (define_insn ""
6549 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
6550 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6551 (const_int 0)))
6552 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6553 (not:DI (match_dup 1)))]
6554 "TARGET_POWERPC64"
6555 "@
6556 nor. %0,%1,%1
6557 #"
6558 [(set_attr "type" "compare")
6559 (set_attr "length" "4,8")])
6561 (define_split
6562 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
6563 (compare:CC (not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6564 (const_int 0)))
6565 (set (match_operand:DI 0 "gpc_reg_operand" "")
6566 (not:DI (match_dup 1)))]
6567 "TARGET_POWERPC64 && reload_completed"
6568 [(set (match_dup 0)
6569 (not:DI (match_dup 1)))
6570 (set (match_dup 2)
6571 (compare:CC (match_dup 0)
6572 (const_int 0)))]
6573 "")
6575 (define_insn ""
6576 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6577 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I")
6578 (match_operand:DI 2 "gpc_reg_operand" "r,r")))]
6579 "TARGET_POWERPC64"
6580 "@
6581 subf %0,%2,%1
6582 subfic %0,%2,%1")
6584 (define_insn ""
6585 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6586 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6587 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6588 (const_int 0)))
6589 (clobber (match_scratch:DI 3 "=r,r"))]
6590 "TARGET_POWERPC64"
6591 "@
6592 subf. %3,%2,%1
6593 #"
6594 [(set_attr "type" "compare")
6595 (set_attr "length" "4,8")])
6597 (define_split
6598 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6599 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
6600 (match_operand:DI 2 "gpc_reg_operand" ""))
6601 (const_int 0)))
6602 (clobber (match_scratch:DI 3 ""))]
6603 "TARGET_POWERPC64 && reload_completed"
6604 [(set (match_dup 3)
6605 (minus:DI (match_dup 1) (match_dup 2)))
6606 (set (match_dup 0)
6607 (compare:CC (match_dup 3)
6608 (const_int 0)))]
6609 "")
6611 (define_insn ""
6612 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6613 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6614 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
6615 (const_int 0)))
6616 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6617 (minus:DI (match_dup 1) (match_dup 2)))]
6618 "TARGET_POWERPC64"
6619 "@
6620 subf. %0,%2,%1
6621 #"
6622 [(set_attr "type" "compare")
6623 (set_attr "length" "4,8")])
6625 (define_split
6626 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6627 (compare:CC (minus:DI (match_operand:DI 1 "gpc_reg_operand" "")
6628 (match_operand:DI 2 "gpc_reg_operand" ""))
6629 (const_int 0)))
6630 (set (match_operand:DI 0 "gpc_reg_operand" "")
6631 (minus:DI (match_dup 1) (match_dup 2)))]
6632 "TARGET_POWERPC64 && reload_completed"
6633 [(set (match_dup 0)
6634 (minus:DI (match_dup 1) (match_dup 2)))
6635 (set (match_dup 3)
6636 (compare:CC (match_dup 0)
6637 (const_int 0)))]
6638 "")
6640 (define_expand "subdi3"
6641 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6642 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "")
6643 (match_operand:DI 2 "reg_or_sub_cint64_operand" "")))]
6644 ""
6645 "
6646 {
6647 if (GET_CODE (operands[2]) == CONST_INT)
6648 {
6649 emit_insn (gen_adddi3 (operands[0], operands[1],
6650 negate_rtx (DImode, operands[2])));
6651 DONE;
6652 }
6653 }")
6655 (define_insn_and_split "absdi2"
6656 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6657 (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))
6658 (clobber (match_scratch:DI 2 "=&r,&r"))]
6659 "TARGET_POWERPC64"
6660 "#"
6661 "&& reload_completed"
6662 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6663 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6664 (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))]
6665 "")
6667 (define_insn_and_split "*nabsdi2"
6668 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r")
6669 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))))
6670 (clobber (match_scratch:DI 2 "=&r,&r"))]
6671 "TARGET_POWERPC64"
6672 "#"
6673 "&& reload_completed"
6674 [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63)))
6675 (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1)))
6676 (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))]
6677 "")
6679 (define_expand "negdi2"
6680 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6681 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "")))]
6682 ""
6683 "")
6685 (define_insn ""
6686 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6687 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
6688 "TARGET_POWERPC64"
6689 "neg %0,%1")
6691 (define_insn ""
6692 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6693 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6694 (const_int 0)))
6695 (clobber (match_scratch:DI 2 "=r,r"))]
6696 "TARGET_POWERPC64"
6697 "@
6698 neg. %2,%1
6699 #"
6700 [(set_attr "type" "compare")
6701 (set_attr "length" "4,8")])
6703 (define_split
6704 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6705 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6706 (const_int 0)))
6707 (clobber (match_scratch:DI 2 ""))]
6708 "TARGET_POWERPC64 && reload_completed"
6709 [(set (match_dup 2)
6710 (neg:DI (match_dup 1)))
6711 (set (match_dup 0)
6712 (compare:CC (match_dup 2)
6713 (const_int 0)))]
6714 "")
6716 (define_insn ""
6717 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
6718 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
6719 (const_int 0)))
6720 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6721 (neg:DI (match_dup 1)))]
6722 "TARGET_POWERPC64"
6723 "@
6724 neg. %0,%1
6725 #"
6726 [(set_attr "type" "compare")
6727 (set_attr "length" "4,8")])
6729 (define_split
6730 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
6731 (compare:CC (neg:DI (match_operand:DI 1 "gpc_reg_operand" ""))
6732 (const_int 0)))
6733 (set (match_operand:DI 0 "gpc_reg_operand" "")
6734 (neg:DI (match_dup 1)))]
6735 "TARGET_POWERPC64 && reload_completed"
6736 [(set (match_dup 0)
6737 (neg:DI (match_dup 1)))
6738 (set (match_dup 2)
6739 (compare:CC (match_dup 0)
6740 (const_int 0)))]
6741 "")
6743 (define_expand "ffsdi2"
6744 [(set (match_dup 2)
6745 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
6746 (parallel [(set (match_dup 3) (and:DI (match_dup 1)
6747 (match_dup 2)))
6748 (clobber (scratch:CC))])
6749 (set (match_dup 4) (unspec:DI [(match_dup 3)] 21))
6750 (set (match_operand:DI 0 "gpc_reg_operand" "=r")
6751 (minus:DI (const_int 64) (match_dup 4)))]
6752 "TARGET_POWERPC64"
6753 {
6754 operands[2] = gen_reg_rtx (DImode);
6755 operands[3] = gen_reg_rtx (DImode);
6756 operands[4] = gen_reg_rtx (DImode);
6757 })
6759 (define_insn "cntlzd2"
6760 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6761 (unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "r")] 21))]
6762 "TARGET_POWERPC64"
6763 "cntlzd %0,%1")
6765 (define_insn "muldi3"
6766 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6767 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
6768 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6769 "TARGET_POWERPC64"
6770 "mulld %0,%1,%2"
6771 [(set_attr "type" "lmul")])
6773 (define_insn "smuldi3_highpart"
6774 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6775 (truncate:DI
6776 (lshiftrt:TI (mult:TI (sign_extend:TI
6777 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6778 (sign_extend:TI
6779 (match_operand:DI 2 "gpc_reg_operand" "r")))
6780 (const_int 64))))]
6781 "TARGET_POWERPC64"
6782 "mulhd %0,%1,%2"
6783 [(set_attr "type" "lmul")])
6785 (define_insn "umuldi3_highpart"
6786 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6787 (truncate:DI
6788 (lshiftrt:TI (mult:TI (zero_extend:TI
6789 (match_operand:DI 1 "gpc_reg_operand" "%r"))
6790 (zero_extend:TI
6791 (match_operand:DI 2 "gpc_reg_operand" "r")))
6792 (const_int 64))))]
6793 "TARGET_POWERPC64"
6794 "mulhdu %0,%1,%2"
6795 [(set_attr "type" "lmul")])
6797 (define_expand "divdi3"
6798 [(set (match_operand:DI 0 "gpc_reg_operand" "")
6799 (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6800 (match_operand:DI 2 "reg_or_cint_operand" "")))]
6801 "TARGET_POWERPC64"
6802 "
6803 {
6804 if (GET_CODE (operands[2]) == CONST_INT
6805 && INTVAL (operands[2]) > 0
6806 && exact_log2 (INTVAL (operands[2])) >= 0)
6807 ;
6808 else
6809 operands[2] = force_reg (DImode, operands[2]);
6810 }")
6812 (define_expand "moddi3"
6813 [(use (match_operand:DI 0 "gpc_reg_operand" ""))
6814 (use (match_operand:DI 1 "gpc_reg_operand" ""))
6815 (use (match_operand:DI 2 "reg_or_cint_operand" ""))]
6816 "TARGET_POWERPC64"
6817 "
6818 {
6819 int i;
6820 rtx temp1;
6821 rtx temp2;
6823 if (GET_CODE (operands[2]) != CONST_INT
6824 || INTVAL (operands[2]) <= 0
6825 || (i = exact_log2 (INTVAL (operands[2]))) < 0)
6826 FAIL;
6828 temp1 = gen_reg_rtx (DImode);
6829 temp2 = gen_reg_rtx (DImode);
6831 emit_insn (gen_divdi3 (temp1, operands[1], operands[2]));
6832 emit_insn (gen_ashldi3 (temp2, temp1, GEN_INT (i)));
6833 emit_insn (gen_subdi3 (operands[0], operands[1], temp2));
6834 DONE;
6835 }")
6837 (define_insn ""
6838 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6839 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6840 (match_operand:DI 2 "exact_log2_cint_operand" "N")))]
6841 "TARGET_POWERPC64"
6842 "sradi %0,%1,%p2\;addze %0,%0"
6843 [(set_attr "length" "8")])
6845 (define_insn ""
6846 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6847 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6848 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6849 (const_int 0)))
6850 (clobber (match_scratch:DI 3 "=r,r"))]
6851 "TARGET_POWERPC64"
6852 "@
6853 sradi %3,%1,%p2\;addze. %3,%3
6854 #"
6855 [(set_attr "type" "compare")
6856 (set_attr "length" "8,12")])
6858 (define_split
6859 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6860 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6861 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6862 (const_int 0)))
6863 (clobber (match_scratch:DI 3 ""))]
6864 "TARGET_POWERPC64 && reload_completed"
6865 [(set (match_dup 3)
6866 (div:DI (match_dup 1) (match_dup 2)))
6867 (set (match_dup 0)
6868 (compare:CC (match_dup 3)
6869 (const_int 0)))]
6870 "")
6872 (define_insn ""
6873 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6874 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6875 (match_operand:DI 2 "exact_log2_cint_operand" "N,N"))
6876 (const_int 0)))
6877 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6878 (div:DI (match_dup 1) (match_dup 2)))]
6879 "TARGET_POWERPC64"
6880 "@
6881 sradi %0,%1,%p2\;addze. %0,%0
6882 #"
6883 [(set_attr "type" "compare")
6884 (set_attr "length" "8,12")])
6886 (define_split
6887 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6888 (compare:CC (div:DI (match_operand:DI 1 "gpc_reg_operand" "")
6889 (match_operand:DI 2 "exact_log2_cint_operand" ""))
6890 (const_int 0)))
6891 (set (match_operand:DI 0 "gpc_reg_operand" "")
6892 (div:DI (match_dup 1) (match_dup 2)))]
6893 "TARGET_POWERPC64 && reload_completed"
6894 [(set (match_dup 0)
6895 (div:DI (match_dup 1) (match_dup 2)))
6896 (set (match_dup 3)
6897 (compare:CC (match_dup 0)
6898 (const_int 0)))]
6899 "")
6901 (define_insn ""
6902 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6903 (div:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6904 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6905 "TARGET_POWERPC64"
6906 "divd %0,%1,%2"
6907 [(set_attr "type" "ldiv")])
6909 (define_insn "udivdi3"
6910 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6911 (udiv:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6912 (match_operand:DI 2 "gpc_reg_operand" "r")))]
6913 "TARGET_POWERPC64"
6914 "divdu %0,%1,%2"
6915 [(set_attr "type" "ldiv")])
6917 (define_insn "rotldi3"
6918 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6919 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6920 (match_operand:DI 2 "reg_or_cint_operand" "ri")))]
6921 "TARGET_POWERPC64"
6922 "rld%I2cl %0,%1,%H2,0")
6924 (define_insn "*rotldi3_internal2"
6925 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6926 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6927 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6928 (const_int 0)))
6929 (clobber (match_scratch:DI 3 "=r,r"))]
6930 "TARGET_POWERPC64"
6931 "@
6932 rld%I2cl. %3,%1,%H2,0
6933 #"
6934 [(set_attr "type" "delayed_compare")
6935 (set_attr "length" "4,8")])
6937 (define_split
6938 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
6939 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6940 (match_operand:DI 2 "reg_or_cint_operand" ""))
6941 (const_int 0)))
6942 (clobber (match_scratch:DI 3 ""))]
6943 "TARGET_POWERPC64 && reload_completed"
6944 [(set (match_dup 3)
6945 (rotate:DI (match_dup 1) (match_dup 2)))
6946 (set (match_dup 0)
6947 (compare:CC (match_dup 3)
6948 (const_int 0)))]
6949 "")
6951 (define_insn "*rotldi3_internal3"
6952 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
6953 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6954 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6955 (const_int 0)))
6956 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
6957 (rotate:DI (match_dup 1) (match_dup 2)))]
6958 "TARGET_POWERPC64"
6959 "@
6960 rld%I2cl. %0,%1,%H2,0
6961 #"
6962 [(set_attr "type" "delayed_compare")
6963 (set_attr "length" "4,8")])
6965 (define_split
6966 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
6967 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
6968 (match_operand:DI 2 "reg_or_cint_operand" ""))
6969 (const_int 0)))
6970 (set (match_operand:DI 0 "gpc_reg_operand" "")
6971 (rotate:DI (match_dup 1) (match_dup 2)))]
6972 "TARGET_POWERPC64 && reload_completed"
6973 [(set (match_dup 0)
6974 (rotate:DI (match_dup 1) (match_dup 2)))
6975 (set (match_dup 3)
6976 (compare:CC (match_dup 0)
6977 (const_int 0)))]
6978 "")
6980 (define_insn "*rotldi3_internal4"
6981 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
6982 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
6983 (match_operand:DI 2 "reg_or_cint_operand" "ri"))
6984 (match_operand:DI 3 "mask64_operand" "n")))]
6985 "TARGET_POWERPC64"
6986 "rld%I2c%B3 %0,%1,%H2,%S3")
6988 (define_insn "*rotldi3_internal5"
6989 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
6990 (compare:CC (and:DI
6991 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
6992 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
6993 (match_operand:DI 3 "mask64_operand" "n,n"))
6994 (const_int 0)))
6995 (clobber (match_scratch:DI 4 "=r,r"))]
6996 "TARGET_POWERPC64"
6997 "@
6998 rld%I2c%B3. %4,%1,%H2,%S3
6999 #"
7000 [(set_attr "type" "delayed_compare")
7001 (set_attr "length" "4,8")])
7003 (define_split
7004 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7005 (compare:CC (and:DI
7006 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7007 (match_operand:DI 2 "reg_or_cint_operand" ""))
7008 (match_operand:DI 3 "mask64_operand" ""))
7009 (const_int 0)))
7010 (clobber (match_scratch:DI 4 ""))]
7011 "TARGET_POWERPC64 && reload_completed"
7012 [(set (match_dup 4)
7013 (and:DI (rotate:DI (match_dup 1)
7014 (match_dup 2))
7015 (match_dup 3)))
7016 (set (match_dup 0)
7017 (compare:CC (match_dup 4)
7018 (const_int 0)))]
7019 "")
7021 (define_insn "*rotldi3_internal6"
7022 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7023 (compare:CC (and:DI
7024 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7025 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri"))
7026 (match_operand:DI 3 "mask64_operand" "n,n"))
7027 (const_int 0)))
7028 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7029 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7030 "TARGET_POWERPC64"
7031 "@
7032 rld%I2c%B3. %0,%1,%H2,%S3
7033 #"
7034 [(set_attr "type" "delayed_compare")
7035 (set_attr "length" "4,8")])
7037 (define_split
7038 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7039 (compare:CC (and:DI
7040 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7041 (match_operand:DI 2 "reg_or_cint_operand" ""))
7042 (match_operand:DI 3 "mask64_operand" ""))
7043 (const_int 0)))
7044 (set (match_operand:DI 0 "gpc_reg_operand" "")
7045 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7046 "TARGET_POWERPC64 && reload_completed"
7047 [(set (match_dup 0)
7048 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
7049 (set (match_dup 4)
7050 (compare:CC (match_dup 0)
7051 (const_int 0)))]
7052 "")
7054 (define_insn "*rotldi3_internal7"
7055 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7056 (zero_extend:DI
7057 (subreg:QI
7058 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7059 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
7060 "TARGET_POWERPC64"
7061 "rld%I2cl %0,%1,%H2,56")
7063 (define_insn "*rotldi3_internal8"
7064 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7065 (compare:CC (zero_extend:DI
7066 (subreg:QI
7067 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7068 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
7069 (const_int 0)))
7070 (clobber (match_scratch:DI 3 "=r,r"))]
7071 "TARGET_POWERPC64"
7072 "@
7073 rld%I2cl. %3,%1,%H2,56
7074 #"
7075 [(set_attr "type" "delayed_compare")
7076 (set_attr "length" "4,8")])
7078 (define_split
7079 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7080 (compare:CC (zero_extend:DI
7081 (subreg:QI
7082 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7083 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7084 (const_int 0)))
7085 (clobber (match_scratch:DI 3 ""))]
7086 "TARGET_POWERPC64 && reload_completed"
7087 [(set (match_dup 3)
7088 (zero_extend:DI (subreg:QI
7089 (rotate:DI (match_dup 1)
7090 (match_dup 2)) 0)))
7091 (set (match_dup 0)
7092 (compare:CC (match_dup 3)
7093 (const_int 0)))]
7094 "")
7096 (define_insn "*rotldi3_internal9"
7097 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7098 (compare:CC (zero_extend:DI
7099 (subreg:QI
7100 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7101 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
7102 (const_int 0)))
7103 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7104 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7105 "TARGET_POWERPC64"
7106 "@
7107 rld%I2cl. %0,%1,%H2,56
7108 #"
7109 [(set_attr "type" "delayed_compare")
7110 (set_attr "length" "4,8")])
7112 (define_split
7113 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7114 (compare:CC (zero_extend:DI
7115 (subreg:QI
7116 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7117 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7118 (const_int 0)))
7119 (set (match_operand:DI 0 "gpc_reg_operand" "")
7120 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7121 "TARGET_POWERPC64 && reload_completed"
7122 [(set (match_dup 0)
7123 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7124 (set (match_dup 3)
7125 (compare:CC (match_dup 0)
7126 (const_int 0)))]
7127 "")
7129 (define_insn "*rotldi3_internal10"
7130 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7131 (zero_extend:DI
7132 (subreg:HI
7133 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7134 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
7135 "TARGET_POWERPC64"
7136 "rld%I2cl %0,%1,%H2,48")
7138 (define_insn "*rotldi3_internal11"
7139 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7140 (compare:CC (zero_extend:DI
7141 (subreg:HI
7142 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7143 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
7144 (const_int 0)))
7145 (clobber (match_scratch:DI 3 "=r,r"))]
7146 "TARGET_POWERPC64"
7147 "@
7148 rld%I2cl. %3,%1,%H2,48
7149 #"
7150 [(set_attr "type" "delayed_compare")
7151 (set_attr "length" "4,8")])
7153 (define_split
7154 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7155 (compare:CC (zero_extend:DI
7156 (subreg:HI
7157 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7158 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7159 (const_int 0)))
7160 (clobber (match_scratch:DI 3 ""))]
7161 "TARGET_POWERPC64 && reload_completed"
7162 [(set (match_dup 3)
7163 (zero_extend:DI (subreg:HI
7164 (rotate:DI (match_dup 1)
7165 (match_dup 2)) 0)))
7166 (set (match_dup 0)
7167 (compare:CC (match_dup 3)
7168 (const_int 0)))]
7169 "")
7171 (define_insn "*rotldi3_internal12"
7172 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7173 (compare:CC (zero_extend:DI
7174 (subreg:HI
7175 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7176 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
7177 (const_int 0)))
7178 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7179 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7180 "TARGET_POWERPC64"
7181 "@
7182 rld%I2cl. %0,%1,%H2,48
7183 #"
7184 [(set_attr "type" "delayed_compare")
7185 (set_attr "length" "4,8")])
7187 (define_split
7188 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7189 (compare:CC (zero_extend:DI
7190 (subreg:HI
7191 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7192 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7193 (const_int 0)))
7194 (set (match_operand:DI 0 "gpc_reg_operand" "")
7195 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7196 "TARGET_POWERPC64 && reload_completed"
7197 [(set (match_dup 0)
7198 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7199 (set (match_dup 3)
7200 (compare:CC (match_dup 0)
7201 (const_int 0)))]
7202 "")
7204 (define_insn "*rotldi3_internal13"
7205 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7206 (zero_extend:DI
7207 (subreg:SI
7208 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7209 (match_operand:DI 2 "reg_or_cint_operand" "ri")) 0)))]
7210 "TARGET_POWERPC64"
7211 "rld%I2cl %0,%1,%H2,32")
7213 (define_insn "*rotldi3_internal14"
7214 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7215 (compare:CC (zero_extend:DI
7216 (subreg:SI
7217 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7218 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
7219 (const_int 0)))
7220 (clobber (match_scratch:DI 3 "=r,r"))]
7221 "TARGET_POWERPC64"
7222 "@
7223 rld%I2cl. %3,%1,%H2,32
7224 #"
7225 [(set_attr "type" "delayed_compare")
7226 (set_attr "length" "4,8")])
7228 (define_split
7229 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7230 (compare:CC (zero_extend:DI
7231 (subreg:SI
7232 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7233 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7234 (const_int 0)))
7235 (clobber (match_scratch:DI 3 ""))]
7236 "TARGET_POWERPC64 && reload_completed"
7237 [(set (match_dup 3)
7238 (zero_extend:DI (subreg:SI
7239 (rotate:DI (match_dup 1)
7240 (match_dup 2)) 0)))
7241 (set (match_dup 0)
7242 (compare:CC (match_dup 3)
7243 (const_int 0)))]
7244 "")
7246 (define_insn "*rotldi3_internal15"
7247 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7248 (compare:CC (zero_extend:DI
7249 (subreg:SI
7250 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7251 (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) 0))
7252 (const_int 0)))
7253 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7254 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7255 "TARGET_POWERPC64"
7256 "@
7257 rld%I2cl. %0,%1,%H2,32
7258 #"
7259 [(set_attr "type" "delayed_compare")
7260 (set_attr "length" "4,8")])
7262 (define_split
7263 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7264 (compare:CC (zero_extend:DI
7265 (subreg:SI
7266 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "")
7267 (match_operand:DI 2 "reg_or_cint_operand" "")) 0))
7268 (const_int 0)))
7269 (set (match_operand:DI 0 "gpc_reg_operand" "")
7270 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))]
7271 "TARGET_POWERPC64 && reload_completed"
7272 [(set (match_dup 0)
7273 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))
7274 (set (match_dup 3)
7275 (compare:CC (match_dup 0)
7276 (const_int 0)))]
7277 "")
7279 (define_expand "ashldi3"
7280 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7281 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7282 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7283 "TARGET_POWERPC64 || TARGET_POWER"
7284 "
7285 {
7286 if (TARGET_POWERPC64)
7287 ;
7288 else if (TARGET_POWER)
7289 {
7290 emit_insn (gen_ashldi3_power (operands[0], operands[1], operands[2]));
7291 DONE;
7292 }
7293 else
7294 FAIL;
7295 }")
7297 (define_insn "*ashldi3_internal1"
7298 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7299 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7300 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7301 "TARGET_POWERPC64"
7302 "sld%I2 %0,%1,%H2"
7303 [(set_attr "length" "8")])
7305 (define_insn "*ashldi3_internal2"
7306 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7307 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7308 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7309 (const_int 0)))
7310 (clobber (match_scratch:DI 3 "=r,r"))]
7311 "TARGET_POWERPC64"
7312 "@
7313 sld%I2. %3,%1,%H2
7314 #"
7315 [(set_attr "type" "delayed_compare")
7316 (set_attr "length" "4,8")])
7318 (define_split
7319 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7320 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7321 (match_operand:SI 2 "reg_or_cint_operand" ""))
7322 (const_int 0)))
7323 (clobber (match_scratch:DI 3 ""))]
7324 "TARGET_POWERPC64 && reload_completed"
7325 [(set (match_dup 3)
7326 (ashift:DI (match_dup 1) (match_dup 2)))
7327 (set (match_dup 0)
7328 (compare:CC (match_dup 3)
7329 (const_int 0)))]
7330 "")
7332 (define_insn "*ashldi3_internal3"
7333 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7334 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7335 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7336 (const_int 0)))
7337 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7338 (ashift:DI (match_dup 1) (match_dup 2)))]
7339 "TARGET_POWERPC64"
7340 "@
7341 sld%I2. %0,%1,%H2
7342 #"
7343 [(set_attr "type" "delayed_compare")
7344 (set_attr "length" "4,8")])
7346 (define_split
7347 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7348 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7349 (match_operand:SI 2 "reg_or_cint_operand" ""))
7350 (const_int 0)))
7351 (set (match_operand:DI 0 "gpc_reg_operand" "")
7352 (ashift:DI (match_dup 1) (match_dup 2)))]
7353 "TARGET_POWERPC64 && reload_completed"
7354 [(set (match_dup 0)
7355 (ashift:DI (match_dup 1) (match_dup 2)))
7356 (set (match_dup 3)
7357 (compare:CC (match_dup 0)
7358 (const_int 0)))]
7359 "")
7361 (define_insn "*ashldi3_internal4"
7362 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7363 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7364 (match_operand:SI 2 "const_int_operand" "i"))
7365 (match_operand:DI 3 "const_int_operand" "n")))]
7366 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7367 "rldic %0,%1,%H2,%W3")
7369 (define_insn "ashldi3_internal5"
7370 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7371 (compare:CC
7372 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7373 (match_operand:SI 2 "const_int_operand" "i,i"))
7374 (match_operand:DI 3 "const_int_operand" "n,n"))
7375 (const_int 0)))
7376 (clobber (match_scratch:DI 4 "=r,r"))]
7377 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7378 "@
7379 rldic. %4,%1,%H2,%W3
7380 #"
7381 [(set_attr "type" "delayed_compare")
7382 (set_attr "length" "4,8")])
7384 (define_split
7385 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7386 (compare:CC
7387 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7388 (match_operand:SI 2 "const_int_operand" ""))
7389 (match_operand:DI 3 "const_int_operand" ""))
7390 (const_int 0)))
7391 (clobber (match_scratch:DI 4 ""))]
7392 "TARGET_POWERPC64 && reload_completed
7393 && includes_rldic_lshift_p (operands[2], operands[3])"
7394 [(set (match_dup 4)
7395 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7396 (match_dup 3)))
7397 (set (match_dup 0)
7398 (compare:CC (match_dup 4)
7399 (const_int 0)))]
7400 "")
7402 (define_insn "*ashldi3_internal6"
7403 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7404 (compare:CC
7405 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7406 (match_operand:SI 2 "const_int_operand" "i,i"))
7407 (match_operand:DI 3 "const_int_operand" "n,n"))
7408 (const_int 0)))
7409 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7410 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7411 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])"
7412 "@
7413 rldic. %0,%1,%H2,%W3
7414 #"
7415 [(set_attr "type" "delayed_compare")
7416 (set_attr "length" "4,8")])
7418 (define_split
7419 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7420 (compare:CC
7421 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7422 (match_operand:SI 2 "const_int_operand" ""))
7423 (match_operand:DI 3 "const_int_operand" ""))
7424 (const_int 0)))
7425 (set (match_operand:DI 0 "gpc_reg_operand" "")
7426 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7427 "TARGET_POWERPC64 && reload_completed
7428 && includes_rldic_lshift_p (operands[2], operands[3])"
7429 [(set (match_dup 0)
7430 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7431 (match_dup 3)))
7432 (set (match_dup 4)
7433 (compare:CC (match_dup 0)
7434 (const_int 0)))]
7435 "")
7437 (define_insn "*ashldi3_internal7"
7438 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7439 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7440 (match_operand:SI 2 "const_int_operand" "i"))
7441 (match_operand:DI 3 "mask64_operand" "n")))]
7442 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7443 "rldicr %0,%1,%H2,%S3")
7445 (define_insn "ashldi3_internal8"
7446 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7447 (compare:CC
7448 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7449 (match_operand:SI 2 "const_int_operand" "i,i"))
7450 (match_operand:DI 3 "mask64_operand" "n,n"))
7451 (const_int 0)))
7452 (clobber (match_scratch:DI 4 "=r,r"))]
7453 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7454 "@
7455 rldicr. %4,%1,%H2,%S3
7456 #"
7457 [(set_attr "type" "delayed_compare")
7458 (set_attr "length" "4,8")])
7460 (define_split
7461 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7462 (compare:CC
7463 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7464 (match_operand:SI 2 "const_int_operand" ""))
7465 (match_operand:DI 3 "mask64_operand" ""))
7466 (const_int 0)))
7467 (clobber (match_scratch:DI 4 ""))]
7468 "TARGET_POWERPC64 && reload_completed
7469 && includes_rldicr_lshift_p (operands[2], operands[3])"
7470 [(set (match_dup 4)
7471 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7472 (match_dup 3)))
7473 (set (match_dup 0)
7474 (compare:CC (match_dup 4)
7475 (const_int 0)))]
7476 "")
7478 (define_insn "*ashldi3_internal9"
7479 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
7480 (compare:CC
7481 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7482 (match_operand:SI 2 "const_int_operand" "i,i"))
7483 (match_operand:DI 3 "mask64_operand" "n,n"))
7484 (const_int 0)))
7485 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7486 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7487 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])"
7488 "@
7489 rldicr. %0,%1,%H2,%S3
7490 #"
7491 [(set_attr "type" "delayed_compare")
7492 (set_attr "length" "4,8")])
7494 (define_split
7495 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
7496 (compare:CC
7497 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "")
7498 (match_operand:SI 2 "const_int_operand" ""))
7499 (match_operand:DI 3 "mask64_operand" ""))
7500 (const_int 0)))
7501 (set (match_operand:DI 0 "gpc_reg_operand" "")
7502 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
7503 "TARGET_POWERPC64 && reload_completed
7504 && includes_rldicr_lshift_p (operands[2], operands[3])"
7505 [(set (match_dup 0)
7506 (and:DI (ashift:DI (match_dup 1) (match_dup 2))
7507 (match_dup 3)))
7508 (set (match_dup 4)
7509 (compare:CC (match_dup 0)
7510 (const_int 0)))]
7511 "")
7513 (define_expand "lshrdi3"
7514 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7515 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7516 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7517 "TARGET_POWERPC64 || TARGET_POWER"
7518 "
7519 {
7520 if (TARGET_POWERPC64)
7521 ;
7522 else if (TARGET_POWER)
7523 {
7524 emit_insn (gen_lshrdi3_power (operands[0], operands[1], operands[2]));
7525 DONE;
7526 }
7527 else
7528 FAIL;
7529 }")
7531 (define_insn "*lshrdi3_internal1"
7532 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7533 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7534 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7535 "TARGET_POWERPC64"
7536 "srd%I2 %0,%1,%H2")
7538 (define_insn "*lshrdi3_internal2"
7539 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7540 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7541 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7542 (const_int 0)))
7543 (clobber (match_scratch:DI 3 "=r,r"))]
7544 "TARGET_POWERPC64"
7545 "@
7546 srd%I2. %3,%1,%H2
7547 #"
7548 [(set_attr "type" "delayed_compare")
7549 (set_attr "length" "4,8")])
7551 (define_split
7552 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7553 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7554 (match_operand:SI 2 "reg_or_cint_operand" ""))
7555 (const_int 0)))
7556 (clobber (match_scratch:DI 3 ""))]
7557 "TARGET_POWERPC64 && reload_completed"
7558 [(set (match_dup 3)
7559 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7560 (set (match_dup 0)
7561 (compare:CC (match_dup 3)
7562 (const_int 0)))]
7563 "")
7565 (define_insn "*lshrdi3_internal3"
7566 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7567 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7568 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7569 (const_int 0)))
7570 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7571 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7572 "TARGET_POWERPC64"
7573 "@
7574 srd%I2. %0,%1,%H2
7575 #"
7576 [(set_attr "type" "delayed_compare")
7577 (set_attr "length" "4,8")])
7579 (define_split
7580 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7581 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7582 (match_operand:SI 2 "reg_or_cint_operand" ""))
7583 (const_int 0)))
7584 (set (match_operand:DI 0 "gpc_reg_operand" "")
7585 (lshiftrt:DI (match_dup 1) (match_dup 2)))]
7586 "TARGET_POWERPC64 && reload_completed"
7587 [(set (match_dup 0)
7588 (lshiftrt:DI (match_dup 1) (match_dup 2)))
7589 (set (match_dup 3)
7590 (compare:CC (match_dup 0)
7591 (const_int 0)))]
7592 "")
7594 (define_expand "ashrdi3"
7595 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7596 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7597 (match_operand:SI 2 "reg_or_cint_operand" "")))]
7598 ""
7599 "
7600 {
7601 if (TARGET_POWERPC64)
7602 ;
7603 else if (TARGET_POWER && GET_CODE (operands[2]) == CONST_INT)
7604 {
7605 emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2]));
7606 DONE;
7607 }
7608 else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT)
7609 {
7610 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2]));
7611 DONE;
7612 }
7613 else
7614 FAIL;
7615 }")
7617 (define_insn "*ashrdi3_internal1"
7618 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
7619 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
7620 (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
7621 "TARGET_POWERPC64"
7622 "srad%I2 %0,%1,%H2")
7624 (define_insn "*ashrdi3_internal2"
7625 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7626 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7627 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7628 (const_int 0)))
7629 (clobber (match_scratch:DI 3 "=r,r"))]
7630 "TARGET_POWERPC64"
7631 "@
7632 srad%I2. %3,%1,%H2
7633 #"
7634 [(set_attr "type" "delayed_compare")
7635 (set_attr "length" "4,8")])
7637 (define_split
7638 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7639 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7640 (match_operand:SI 2 "reg_or_cint_operand" ""))
7641 (const_int 0)))
7642 (clobber (match_scratch:DI 3 ""))]
7643 "TARGET_POWERPC64 && reload_completed"
7644 [(set (match_dup 3)
7645 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7646 (set (match_dup 0)
7647 (compare:CC (match_dup 3)
7648 (const_int 0)))]
7649 "")
7651 (define_insn "*ashrdi3_internal3"
7652 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7653 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
7654 (match_operand:SI 2 "reg_or_cint_operand" "ri,ri"))
7655 (const_int 0)))
7656 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7657 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7658 "TARGET_POWERPC64"
7659 "@
7660 srad%I2. %0,%1,%H2
7661 #"
7662 [(set_attr "type" "delayed_compare")
7663 (set_attr "length" "4,8")])
7665 (define_split
7666 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7667 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
7668 (match_operand:SI 2 "reg_or_cint_operand" ""))
7669 (const_int 0)))
7670 (set (match_operand:DI 0 "gpc_reg_operand" "")
7671 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
7672 "TARGET_POWERPC64 && reload_completed"
7673 [(set (match_dup 0)
7674 (ashiftrt:DI (match_dup 1) (match_dup 2)))
7675 (set (match_dup 3)
7676 (compare:CC (match_dup 0)
7677 (const_int 0)))]
7678 "")
7680 (define_insn "anddi3"
7681 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
7682 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
7683 (match_operand:DI 2 "and64_2_operand" "?r,S,K,J,t")))
7684 (clobber (match_scratch:CC 3 "=X,X,x,x,X"))]
7685 "TARGET_POWERPC64"
7686 "@
7687 and %0,%1,%2
7688 rldic%B2 %0,%1,0,%S2
7689 andi. %0,%1,%b2
7690 andis. %0,%1,%u2
7691 #"
7692 [(set_attr "length" "4,4,4,4,8")])
7694 (define_split
7695 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7696 (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7697 (match_operand:DI 2 "mask64_2_operand" "")))
7698 (clobber (match_scratch:CC 3 ""))]
7699 "TARGET_POWERPC64
7700 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7701 && !mask64_operand (operands[2], DImode)"
7702 [(set (match_dup 0)
7703 (and:DI (rotate:DI (match_dup 1)
7704 (match_dup 4))
7705 (match_dup 5)))
7706 (set (match_dup 0)
7707 (and:DI (rotate:DI (match_dup 0)
7708 (match_dup 6))
7709 (match_dup 7)))]
7710 "
7711 {
7712 build_mask64_2_operands (operands[2], &operands[4]);
7713 }")
7715 (define_insn "*anddi3_internal2"
7716 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7717 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7718 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7719 (const_int 0)))
7720 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r"))
7721 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7722 "TARGET_POWERPC64"
7723 "@
7724 and. %3,%1,%2
7725 rldic%B2. %3,%1,0,%S2
7726 andi. %3,%1,%b2
7727 andis. %3,%1,%u2
7728 #
7729 #
7730 #
7731 #
7732 #
7733 #"
7734 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7735 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7737 (define_split
7738 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7739 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7740 (match_operand:DI 2 "and64_operand" ""))
7741 (const_int 0)))
7742 (clobber (match_scratch:DI 3 ""))
7743 (clobber (match_scratch:CC 4 ""))]
7744 "TARGET_POWERPC64 && reload_completed"
7745 [(parallel [(set (match_dup 3)
7746 (and:DI (match_dup 1)
7747 (match_dup 2)))
7748 (clobber (match_dup 4))])
7749 (set (match_dup 0)
7750 (compare:CC (match_dup 3)
7751 (const_int 0)))]
7752 "")
7754 (define_split
7755 [(set (match_operand:CC 0 "cc_reg_operand" "")
7756 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7757 (match_operand:DI 2 "mask64_2_operand" ""))
7758 (const_int 0)))
7759 (clobber (match_scratch:DI 3 ""))
7760 (clobber (match_scratch:CC 4 ""))]
7761 "TARGET_POWERPC64 && reload_completed
7762 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7763 && !mask64_operand (operands[2], DImode)"
7764 [(set (match_dup 3)
7765 (and:DI (rotate:DI (match_dup 1)
7766 (match_dup 5))
7767 (match_dup 6)))
7768 (parallel [(set (match_dup 0)
7769 (compare:CC (and:DI (rotate:DI (match_dup 3)
7770 (match_dup 7))
7771 (match_dup 8))
7772 (const_int 0)))
7773 (clobber (match_dup 3))])]
7774 "
7775 {
7776 build_mask64_2_operands (operands[2], &operands[5]);
7777 }")
7779 (define_insn "*anddi3_internal3"
7780 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y")
7781 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
7782 (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t"))
7783 (const_int 0)))
7784 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
7785 (and:DI (match_dup 1) (match_dup 2)))
7786 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))]
7787 "TARGET_POWERPC64"
7788 "@
7789 and. %0,%1,%2
7790 rldic%B2. %0,%1,0,%S2
7791 andi. %0,%1,%b2
7792 andis. %0,%1,%u2
7793 #
7794 #
7795 #
7796 #
7797 #
7798 #"
7799 [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare")
7800 (set_attr "length" "4,4,4,4,8,8,8,8,8,12")])
7802 (define_split
7803 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7804 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7805 (match_operand:DI 2 "and64_operand" ""))
7806 (const_int 0)))
7807 (set (match_operand:DI 0 "gpc_reg_operand" "")
7808 (and:DI (match_dup 1) (match_dup 2)))
7809 (clobber (match_scratch:CC 4 ""))]
7810 "TARGET_POWERPC64 && reload_completed"
7811 [(parallel [(set (match_dup 0)
7812 (and:DI (match_dup 1) (match_dup 2)))
7813 (clobber (match_dup 4))])
7814 (set (match_dup 3)
7815 (compare:CC (match_dup 0)
7816 (const_int 0)))]
7817 "")
7819 (define_split
7820 [(set (match_operand:CC 3 "cc_reg_operand" "")
7821 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "")
7822 (match_operand:DI 2 "mask64_2_operand" ""))
7823 (const_int 0)))
7824 (set (match_operand:DI 0 "gpc_reg_operand" "")
7825 (and:DI (match_dup 1) (match_dup 2)))
7826 (clobber (match_scratch:CC 4 ""))]
7827 "TARGET_POWERPC64 && reload_completed
7828 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode))
7829 && !mask64_operand (operands[2], DImode)"
7830 [(set (match_dup 0)
7831 (and:DI (rotate:DI (match_dup 1)
7832 (match_dup 5))
7833 (match_dup 6)))
7834 (parallel [(set (match_dup 3)
7835 (compare:CC (and:DI (rotate:DI (match_dup 0)
7836 (match_dup 7))
7837 (match_dup 8))
7838 (const_int 0)))
7839 (set (match_dup 0)
7840 (and:DI (rotate:DI (match_dup 0)
7841 (match_dup 7))
7842 (match_dup 8)))])]
7843 "
7844 {
7845 build_mask64_2_operands (operands[2], &operands[5]);
7846 }")
7848 (define_expand "iordi3"
7849 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7850 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "")
7851 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7852 "TARGET_POWERPC64"
7853 "
7854 {
7855 if (non_logical_cint_operand (operands[2], DImode))
7856 {
7857 HOST_WIDE_INT value;
7858 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7859 ? operands[0] : gen_reg_rtx (DImode));
7861 if (GET_CODE (operands[2]) == CONST_INT)
7862 {
7863 value = INTVAL (operands[2]);
7864 emit_insn (gen_iordi3 (tmp, operands[1],
7865 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7866 }
7867 else
7868 {
7869 value = CONST_DOUBLE_LOW (operands[2]);
7870 emit_insn (gen_iordi3 (tmp, operands[1],
7871 immed_double_const (value
7872 & (~ (HOST_WIDE_INT) 0xffff),
7873 0, DImode)));
7874 }
7876 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7877 DONE;
7878 }
7879 }")
7881 (define_expand "xordi3"
7882 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7883 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "")
7884 (match_operand:DI 2 "reg_or_logical_cint_operand" "")))]
7885 "TARGET_POWERPC64"
7886 "
7887 {
7888 if (non_logical_cint_operand (operands[2], DImode))
7889 {
7890 HOST_WIDE_INT value;
7891 rtx tmp = ((no_new_pseudos || rtx_equal_p (operands[0], operands[1]))
7892 ? operands[0] : gen_reg_rtx (DImode));
7894 if (GET_CODE (operands[2]) == CONST_INT)
7895 {
7896 value = INTVAL (operands[2]);
7897 emit_insn (gen_xordi3 (tmp, operands[1],
7898 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff))));
7899 }
7900 else
7901 {
7902 value = CONST_DOUBLE_LOW (operands[2]);
7903 emit_insn (gen_xordi3 (tmp, operands[1],
7904 immed_double_const (value
7905 & (~ (HOST_WIDE_INT) 0xffff),
7906 0, DImode)));
7907 }
7909 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff)));
7910 DONE;
7911 }
7912 }")
7914 (define_insn "*booldi3_internal1"
7915 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r")
7916 (match_operator:DI 3 "boolean_or_operator"
7917 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r")
7918 (match_operand:DI 2 "logical_operand" "r,K,JF")]))]
7919 "TARGET_POWERPC64"
7920 "@
7921 %q3 %0,%1,%2
7922 %q3i %0,%1,%b2
7923 %q3is %0,%1,%u2")
7925 (define_insn "*booldi3_internal2"
7926 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
7927 (compare:CC (match_operator:DI 4 "boolean_or_operator"
7928 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7929 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7930 (const_int 0)))
7931 (clobber (match_scratch:DI 3 "=r,r"))]
7932 "TARGET_POWERPC64"
7933 "@
7934 %q4. %3,%1,%2
7935 #"
7936 [(set_attr "type" "compare")
7937 (set_attr "length" "4,8")])
7939 (define_split
7940 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
7941 (compare:CC (match_operator:DI 4 "boolean_operator"
7942 [(match_operand:DI 1 "gpc_reg_operand" "")
7943 (match_operand:DI 2 "gpc_reg_operand" "")])
7944 (const_int 0)))
7945 (clobber (match_scratch:DI 3 ""))]
7946 "TARGET_POWERPC64 && reload_completed"
7947 [(set (match_dup 3) (match_dup 4))
7948 (set (match_dup 0)
7949 (compare:CC (match_dup 3)
7950 (const_int 0)))]
7951 "")
7953 (define_insn "*booldi3_internal3"
7954 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
7955 (compare:CC (match_operator:DI 4 "boolean_operator"
7956 [(match_operand:DI 1 "gpc_reg_operand" "%r,r")
7957 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
7958 (const_int 0)))
7959 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
7960 (match_dup 4))]
7961 "TARGET_POWERPC64"
7962 "@
7963 %q4. %0,%1,%2
7964 #"
7965 [(set_attr "type" "compare")
7966 (set_attr "length" "4,8")])
7968 (define_split
7969 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
7970 (compare:CC (match_operator:DI 4 "boolean_operator"
7971 [(match_operand:DI 1 "gpc_reg_operand" "")
7972 (match_operand:DI 2 "gpc_reg_operand" "")])
7973 (const_int 0)))
7974 (set (match_operand:DI 0 "gpc_reg_operand" "")
7975 (match_dup 4))]
7976 "TARGET_POWERPC64 && reload_completed"
7977 [(set (match_dup 0) (match_dup 4))
7978 (set (match_dup 3)
7979 (compare:CC (match_dup 0)
7980 (const_int 0)))]
7981 "")
7983 ;; Split an logical operation that we can't do in one insn into two insns,
7984 ;; each of which does one 16-bit part. This is used by combine.
7986 (define_split
7987 [(set (match_operand:DI 0 "gpc_reg_operand" "")
7988 (match_operator:DI 3 "boolean_or_operator"
7989 [(match_operand:DI 1 "gpc_reg_operand" "")
7990 (match_operand:DI 2 "non_logical_cint_operand" "")]))]
7991 "TARGET_POWERPC64"
7992 [(set (match_dup 0) (match_dup 4))
7993 (set (match_dup 0) (match_dup 5))]
7994 "
7995 {
7996 rtx i3,i4;
7998 if (GET_CODE (operands[2]) == CONST_DOUBLE)
7999 {
8000 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]);
8001 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff),
8002 0, DImode);
8003 i4 = GEN_INT (value & 0xffff);
8004 }
8005 else
8006 {
8007 i3 = GEN_INT (INTVAL (operands[2])
8008 & (~ (HOST_WIDE_INT) 0xffff));
8009 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff);
8010 }
8011 operands[4] = gen_rtx (GET_CODE (operands[3]), DImode,
8012 operands[1], i3);
8013 operands[5] = gen_rtx (GET_CODE (operands[3]), DImode,
8014 operands[0], i4);
8015 }")
8017 (define_insn "*boolcdi3_internal1"
8018 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8019 (match_operator:DI 3 "boolean_operator"
8020 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8021 (match_operand:DI 2 "gpc_reg_operand" "r")]))]
8022 "TARGET_POWERPC64"
8023 "%q3 %0,%2,%1")
8025 (define_insn "*boolcdi3_internal2"
8026 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8027 (compare:CC (match_operator:DI 4 "boolean_operator"
8028 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8029 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8030 (const_int 0)))
8031 (clobber (match_scratch:DI 3 "=r,r"))]
8032 "TARGET_POWERPC64"
8033 "@
8034 %q4. %3,%2,%1
8035 #"
8036 [(set_attr "type" "compare")
8037 (set_attr "length" "4,8")])
8039 (define_split
8040 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
8041 (compare:CC (match_operator:DI 4 "boolean_operator"
8042 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8043 (match_operand:DI 2 "gpc_reg_operand" "")])
8044 (const_int 0)))
8045 (clobber (match_scratch:DI 3 ""))]
8046 "TARGET_POWERPC64 && reload_completed"
8047 [(set (match_dup 3) (match_dup 4))
8048 (set (match_dup 0)
8049 (compare:CC (match_dup 3)
8050 (const_int 0)))]
8051 "")
8053 (define_insn "*boolcdi3_internal3"
8054 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8055 (compare:CC (match_operator:DI 4 "boolean_operator"
8056 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8057 (match_operand:DI 2 "gpc_reg_operand" "r,r")])
8058 (const_int 0)))
8059 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8060 (match_dup 4))]
8061 "TARGET_POWERPC64"
8062 "@
8063 %q4. %0,%2,%1
8064 #"
8065 [(set_attr "type" "compare")
8066 (set_attr "length" "4,8")])
8068 (define_split
8069 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
8070 (compare:CC (match_operator:DI 4 "boolean_operator"
8071 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8072 (match_operand:DI 2 "gpc_reg_operand" "")])
8073 (const_int 0)))
8074 (set (match_operand:DI 0 "gpc_reg_operand" "")
8075 (match_dup 4))]
8076 "TARGET_POWERPC64 && reload_completed"
8077 [(set (match_dup 0) (match_dup 4))
8078 (set (match_dup 3)
8079 (compare:CC (match_dup 0)
8080 (const_int 0)))]
8081 "")
8083 (define_insn "*boolccdi3_internal1"
8084 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
8085 (match_operator:DI 3 "boolean_operator"
8086 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r"))
8087 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))]
8088 "TARGET_POWERPC64"
8089 "%q3 %0,%1,%2")
8091 (define_insn "*boolccdi3_internal2"
8092 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
8093 (compare:CC (match_operator:DI 4 "boolean_operator"
8094 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r"))
8095 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8096 (const_int 0)))
8097 (clobber (match_scratch:DI 3 "=r,r"))]
8098 "TARGET_POWERPC64"
8099 "@
8100 %q4. %3,%1,%2
8101 #"
8102 [(set_attr "type" "compare")
8103 (set_attr "length" "4,8")])
8105 (define_split
8106 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
8107 (compare:CC (match_operator:DI 4 "boolean_operator"
8108 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8109 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8110 (const_int 0)))
8111 (clobber (match_scratch:DI 3 ""))]
8112 "TARGET_POWERPC64 && reload_completed"
8113 [(set (match_dup 3) (match_dup 4))
8114 (set (match_dup 0)
8115 (compare:CC (match_dup 3)
8116 (const_int 0)))]
8117 "")
8119 (define_insn "*boolccdi3_internal3"
8120 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
8121 (compare:CC (match_operator:DI 4 "boolean_operator"
8122 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r"))
8123 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))])
8124 (const_int 0)))
8125 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
8126 (match_dup 4))]
8127 "TARGET_POWERPC64"
8128 "@
8129 %q4. %0,%1,%2
8130 #"
8131 [(set_attr "type" "compare")
8132 (set_attr "length" "4,8")])
8134 (define_split
8135 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
8136 (compare:CC (match_operator:DI 4 "boolean_operator"
8137 [(not:DI (match_operand:DI 1 "gpc_reg_operand" ""))
8138 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))])
8139 (const_int 0)))
8140 (set (match_operand:DI 0 "gpc_reg_operand" "")
8141 (match_dup 4))]
8142 "TARGET_POWERPC64 && reload_completed"
8143 [(set (match_dup 0) (match_dup 4))
8144 (set (match_dup 3)
8145 (compare:CC (match_dup 0)
8146 (const_int 0)))]
8147 "")
8148 \f
8149 ;; Now define ways of moving data around.
8151 ;; Elf specific ways of loading addresses for non-PIC code.
8152 ;; The output of this could be r0, but we make a very strong
8153 ;; preference for a base register because it will usually
8154 ;; be needed there.
8155 (define_insn "elf_high"
8156 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
8157 (high:SI (match_operand 1 "" "")))]
8158 "TARGET_ELF && ! TARGET_64BIT"
8159 "{liu|lis} %0,%1@ha")
8161 (define_insn "elf_low"
8162 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8163 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
8164 (match_operand 2 "" "")))]
8165 "TARGET_ELF && ! TARGET_64BIT"
8166 "@
8167 {cal|la} %0,%2@l(%1)
8168 {ai|addic} %0,%1,%K2")
8170 ;; Mach-O PIC trickery.
8171 (define_insn "macho_high"
8172 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
8173 (high:SI (match_operand 1 "" "")))]
8174 "TARGET_MACHO && ! TARGET_64BIT"
8175 "{liu|lis} %0,ha16(%1)")
8177 (define_insn "macho_low"
8178 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
8179 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
8180 (match_operand 2 "" "")))]
8181 "TARGET_MACHO && ! TARGET_64BIT"
8182 "@
8183 {cal %0,%a2@l(%1)|la %0,lo16(%2)(%1)}
8184 {cal %0,%a2@l(%1)|addic %0,%1,lo16(%2)}")
8186 ;; Set up a register with a value from the GOT table
8188 (define_expand "movsi_got"
8189 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8190 (unspec:SI [(match_operand:SI 1 "got_operand" "")
8191 (match_dup 2)] 8))]
8192 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8193 "
8194 {
8195 if (GET_CODE (operands[1]) == CONST)
8196 {
8197 rtx offset = const0_rtx;
8198 HOST_WIDE_INT value;
8200 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset);
8201 value = INTVAL (offset);
8202 if (value != 0)
8203 {
8204 rtx tmp = (no_new_pseudos ? operands[0] : gen_reg_rtx (Pmode));
8205 emit_insn (gen_movsi_got (tmp, operands[1]));
8206 emit_insn (gen_addsi3 (operands[0], tmp, offset));
8207 DONE;
8208 }
8209 }
8211 operands[2] = rs6000_got_register (operands[1]);
8212 }")
8214 (define_insn "*movsi_got_internal"
8215 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8216 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8217 (match_operand:SI 2 "gpc_reg_operand" "b")] 8))]
8218 "DEFAULT_ABI == ABI_V4 && flag_pic == 1"
8219 "{l|lwz} %0,%a1@got(%2)"
8220 [(set_attr "type" "load")])
8222 ;; Used by sched, shorten_branches and final when the GOT pseudo reg
8223 ;; didn't get allocated to a hard register.
8224 (define_split
8225 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8226 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "")
8227 (match_operand:SI 2 "memory_operand" "")] 8))]
8228 "DEFAULT_ABI == ABI_V4
8229 && flag_pic == 1
8230 && (reload_in_progress || reload_completed)"
8231 [(set (match_dup 0) (match_dup 2))
8232 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] 8))]
8233 "")
8235 ;; For SI, we special-case integers that can't be loaded in one insn. We
8236 ;; do the load 16-bits at a time. We could do this by loading from memory,
8237 ;; and this is even supposed to be faster, but it is simpler not to get
8238 ;; integers in the TOC.
8239 (define_expand "movsi"
8240 [(set (match_operand:SI 0 "general_operand" "")
8241 (match_operand:SI 1 "any_operand" ""))]
8242 ""
8243 "{ rs6000_emit_move (operands[0], operands[1], SImode); DONE; }")
8245 (define_insn "movsi_low"
8246 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
8247 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8248 (match_operand 2 "" ""))))]
8249 "TARGET_MACHO && ! TARGET_64BIT"
8250 "{l|lwz} %0,lo16(%2)(%1)"
8251 [(set_attr "type" "load")
8252 (set_attr "length" "4")])
8254 (define_insn "movsi_low_st"
8255 [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8256 (match_operand 2 "" "")))
8257 (match_operand:SI 0 "gpc_reg_operand" "r"))]
8258 "TARGET_MACHO && ! TARGET_64BIT"
8259 "{st|stw} %0,lo16(%2)(%1)"
8260 [(set_attr "type" "store")
8261 (set_attr "length" "4")])
8263 (define_insn "movdf_low"
8264 [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r")
8265 (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
8266 (match_operand 2 "" ""))))]
8267 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
8268 "*
8269 {
8270 switch (which_alternative)
8271 {
8272 case 0:
8273 return \"lfd %0,lo16(%2)(%1)\";
8274 case 1:
8275 {
8276 rtx operands2[4];
8277 operands2[0] = operands[0];
8278 operands2[1] = operands[1];
8279 operands2[2] = operands[2];
8280 operands2[3] = gen_rtx_REG (SImode, RS6000_PIC_OFFSET_TABLE_REGNUM);
8281 output_asm_insn (\"{l|lwz} %0,lo16(%2)(%1)\", operands);
8282 /* We cannot rely on ha16(low half)==ha16(high half), alas,
8283 although in practice it almost always is. */
8284 output_asm_insn (\"{cau|addis} %L0,%3,ha16(%2+4)\", operands2);
8285 return (\"{l|lwz} %L0,lo16(%2+4)(%L0)\");
8286 }
8287 default:
8288 abort();
8289 }
8290 }"
8291 [(set_attr "type" "load")
8292 (set_attr "length" "4,12")])
8294 (define_insn "movdf_low_st"
8295 [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
8296 (match_operand 2 "" "")))
8297 (match_operand:DF 0 "gpc_reg_operand" "f"))]
8298 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
8299 "stfd %0,lo16(%2)(%1)"
8300 [(set_attr "type" "store")
8301 (set_attr "length" "4")])
8303 (define_insn "movsf_low"
8304 [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r")
8305 (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
8306 (match_operand 2 "" ""))))]
8307 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
8308 "@
8309 lfs %0,lo16(%2)(%1)
8310 {l|lwz} %0,lo16(%2)(%1)"
8311 [(set_attr "type" "load")
8312 (set_attr "length" "4")])
8314 (define_insn "movsf_low_st"
8315 [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
8316 (match_operand 2 "" "")))
8317 (match_operand:SF 0 "gpc_reg_operand" "f,!r"))]
8318 "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT"
8319 "@
8320 stfs %0,lo16(%2)(%1)
8321 {st|stw} %0,lo16(%2)(%1)"
8322 [(set_attr "type" "store")
8323 (set_attr "length" "4")])
8325 (define_insn "*movsi_internal1"
8326 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,m,r,r,r,r,r,*q,*c*l,*h,*h")
8327 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,R,*h,r,r,r,0"))]
8328 "gpc_reg_operand (operands[0], SImode)
8329 || gpc_reg_operand (operands[1], SImode)"
8330 "@
8331 mr %0,%1
8332 {cal|la} %0,%a1
8333 {l%U1%X1|lwz%U1%X1} %0,%1
8334 {st%U0%X0|stw%U0%X0} %1,%0
8335 {lil|li} %0,%1
8336 {liu|lis} %0,%v1
8337 #
8338 {cal|la} %0,%a1
8339 mf%1 %0
8340 mt%0 %1
8341 mt%0 %1
8342 mt%0 %1
8343 {cror 0,0,0|nop}"
8344 [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*,*")
8345 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")])
8347 ;; Split a load of a large constant into the appropriate two-insn
8348 ;; sequence.
8350 (define_split
8351 [(set (match_operand:SI 0 "gpc_reg_operand" "")
8352 (match_operand:SI 1 "const_int_operand" ""))]
8353 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000
8354 && (INTVAL (operands[1]) & 0xffff) != 0"
8355 [(set (match_dup 0)
8356 (match_dup 2))
8357 (set (match_dup 0)
8358 (ior:SI (match_dup 0)
8359 (match_dup 3)))]
8360 "
8361 { rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2);
8363 if (tem == operands[0])
8364 DONE;
8365 else
8366 FAIL;
8367 }")
8369 (define_insn "*movsi_internal2"
8370 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
8371 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r,r")
8372 (const_int 0)))
8373 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
8374 "! TARGET_POWERPC64"
8375 "@
8376 mr. %0,%1
8377 #"
8378 [(set_attr "type" "compare")
8379 (set_attr "length" "4,8")])
8380 \f
8381 (define_split
8382 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
8383 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
8384 (const_int 0)))
8385 (set (match_operand:SI 0 "gpc_reg_operand" "") (match_dup 1))]
8386 "! TARGET_POWERPC64 && reload_completed"
8387 [(set (match_dup 0) (match_dup 1))
8388 (set (match_dup 2)
8389 (compare:CC (match_dup 0)
8390 (const_int 0)))]
8391 "")
8393 (define_expand "movhi"
8394 [(set (match_operand:HI 0 "general_operand" "")
8395 (match_operand:HI 1 "any_operand" ""))]
8396 ""
8397 "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }")
8399 (define_insn "*movhi_internal"
8400 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8401 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8402 "gpc_reg_operand (operands[0], HImode)
8403 || gpc_reg_operand (operands[1], HImode)"
8404 "@
8405 mr %0,%1
8406 lhz%U1%X1 %0,%1
8407 sth%U0%X0 %1,%0
8408 {lil|li} %0,%w1
8409 mf%1 %0
8410 mt%0 %1
8411 mt%0 %1
8412 {cror 0,0,0|nop}"
8413 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
8415 (define_expand "movqi"
8416 [(set (match_operand:QI 0 "general_operand" "")
8417 (match_operand:QI 1 "any_operand" ""))]
8418 ""
8419 "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }")
8421 (define_insn "*movqi_internal"
8422 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h")
8423 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))]
8424 "gpc_reg_operand (operands[0], QImode)
8425 || gpc_reg_operand (operands[1], QImode)"
8426 "@
8427 mr %0,%1
8428 lbz%U1%X1 %0,%1
8429 stb%U0%X0 %1,%0
8430 {lil|li} %0,%1
8431 mf%1 %0
8432 mt%0 %1
8433 mt%0 %1
8434 {cror 0,0,0|nop}"
8435 [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")])
8436 \f
8437 ;; Here is how to move condition codes around. When we store CC data in
8438 ;; an integer register or memory, we store just the high-order 4 bits.
8439 ;; This lets us not shift in the most common case of CR0.
8440 (define_expand "movcc"
8441 [(set (match_operand:CC 0 "nonimmediate_operand" "")
8442 (match_operand:CC 1 "nonimmediate_operand" ""))]
8443 ""
8444 "")
8446 (define_insn "*movcc_internal1"
8447 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,cl,q,r,r,m")
8448 (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,r,r,h,m,r"))]
8449 "register_operand (operands[0], CCmode)
8450 || register_operand (operands[1], CCmode)"
8451 "@
8452 mcrf %0,%1
8453 mtcrf 128,%1
8454 {rlinm|rlwinm} %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;{rlinm|rlwinm} %1,%1,%f0,0xffffffff
8455 mfcr %0
8456 mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000
8457 mr %0,%1
8458 mt%0 %1
8459 mt%0 %1
8460 mf%1 %0
8461 {l%U1%X1|lwz%U1%X1} %0,%1
8462 {st%U0%U1|stw%U0%U1} %1,%0"
8463 [(set_attr "type" "cr_logical,cr_logical,cr_logical,cr_logical,cr_logical,*,*,mtjmpr,*,load,store")
8464 (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")])
8465 \f
8466 ;; For floating-point, we normally deal with the floating-point registers
8467 ;; unless -msoft-float is used. The sole exception is that parameter passing
8468 ;; can produce floating-point values in fixed-point registers. Unless the
8469 ;; value is a simple constant or already in memory, we deal with this by
8470 ;; allocating memory and copying the value explicitly via that memory location.
8471 (define_expand "movsf"
8472 [(set (match_operand:SF 0 "nonimmediate_operand" "")
8473 (match_operand:SF 1 "any_operand" ""))]
8474 ""
8475 "{ rs6000_emit_move (operands[0], operands[1], SFmode); DONE; }")
8477 (define_split
8478 [(set (match_operand:SF 0 "gpc_reg_operand" "")
8479 (match_operand:SF 1 "const_double_operand" ""))]
8480 "reload_completed
8481 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8482 || (GET_CODE (operands[0]) == SUBREG
8483 && GET_CODE (SUBREG_REG (operands[0])) == REG
8484 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8485 [(set (match_dup 2) (match_dup 3))]
8486 "
8487 {
8488 long l;
8489 REAL_VALUE_TYPE rv;
8491 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8492 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
8494 if (! TARGET_POWERPC64)
8495 operands[2] = operand_subword (operands[0], 0, 0, SFmode);
8496 else
8497 operands[2] = gen_lowpart (SImode, operands[0]);
8499 operands[3] = gen_int_mode (l, SImode);
8500 }")
8502 (define_insn "*movsf_hardfloat"
8503 [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!r,!r")
8504 (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,G,Fn"))]
8505 "(gpc_reg_operand (operands[0], SFmode)
8506 || gpc_reg_operand (operands[1], SFmode))
8507 && (TARGET_HARD_FLOAT && TARGET_FPRS)"
8508 "@
8509 mr %0,%1
8510 {l%U1%X1|lwz%U1%X1} %0,%1
8511 {st%U0%X0|stw%U0%X0} %1,%0
8512 fmr %0,%1
8513 lfs%U1%X1 %0,%1
8514 stfs%U0%X0 %1,%0
8515 mt%0 %1
8516 mt%0 %1
8517 mf%1 %0
8518 #
8519 #"
8520 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*")
8521 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")])
8523 (define_insn "*movsf_softfloat"
8524 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r")
8525 (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn"))]
8526 "(gpc_reg_operand (operands[0], SFmode)
8527 || gpc_reg_operand (operands[1], SFmode))
8528 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)"
8529 "@
8530 mr %0,%1
8531 mt%0 %1
8532 mt%0 %1
8533 mf%1 %0
8534 {l%U1%X1|lwz%U1%X1} %0,%1
8535 {st%U0%X0|stw%U0%X0} %1,%0
8536 {lil|li} %0,%1
8537 {liu|lis} %0,%v1
8538 {cal|la} %0,%a1
8539 #
8540 #"
8541 [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*")
8542 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")])
8544 \f
8545 (define_expand "movdf"
8546 [(set (match_operand:DF 0 "nonimmediate_operand" "")
8547 (match_operand:DF 1 "any_operand" ""))]
8548 ""
8549 "{ rs6000_emit_move (operands[0], operands[1], DFmode); DONE; }")
8551 (define_split
8552 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8553 (match_operand:DF 1 "const_int_operand" ""))]
8554 "! TARGET_POWERPC64 && reload_completed
8555 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8556 || (GET_CODE (operands[0]) == SUBREG
8557 && GET_CODE (SUBREG_REG (operands[0])) == REG
8558 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8559 [(set (match_dup 2) (match_dup 4))
8560 (set (match_dup 3) (match_dup 1))]
8561 "
8562 {
8563 int endian = (WORDS_BIG_ENDIAN == 0);
8564 HOST_WIDE_INT value = INTVAL (operands[1]);
8566 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8567 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8568 #if HOST_BITS_PER_WIDE_INT == 32
8569 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
8570 #else
8571 operands[4] = GEN_INT (value >> 32);
8572 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
8573 #endif
8574 }")
8576 (define_split
8577 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8578 (match_operand:DF 1 "const_double_operand" ""))]
8579 "! TARGET_POWERPC64 && reload_completed
8580 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8581 || (GET_CODE (operands[0]) == SUBREG
8582 && GET_CODE (SUBREG_REG (operands[0])) == REG
8583 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8584 [(set (match_dup 2) (match_dup 4))
8585 (set (match_dup 3) (match_dup 5))]
8586 "
8587 {
8588 int endian = (WORDS_BIG_ENDIAN == 0);
8589 long l[2];
8590 REAL_VALUE_TYPE rv;
8592 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8593 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8595 operands[2] = operand_subword (operands[0], endian, 0, DFmode);
8596 operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode);
8597 operands[4] = gen_int_mode (l[endian], SImode);
8598 operands[5] = gen_int_mode (l[1 - endian], SImode);
8599 }")
8601 (define_split
8602 [(set (match_operand:DF 0 "gpc_reg_operand" "")
8603 (match_operand:DF 1 "easy_fp_constant" ""))]
8604 "TARGET_POWERPC64 && reload_completed
8605 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8606 || (GET_CODE (operands[0]) == SUBREG
8607 && GET_CODE (SUBREG_REG (operands[0])) == REG
8608 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8609 [(set (match_dup 2) (match_dup 3))]
8610 "
8611 {
8612 int endian = (WORDS_BIG_ENDIAN == 0);
8613 long l[2];
8614 REAL_VALUE_TYPE rv;
8615 #if HOST_BITS_PER_WIDE_INT >= 64
8616 HOST_WIDE_INT val;
8617 #endif
8619 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8620 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
8622 operands[2] = gen_lowpart (DImode, operands[0]);
8623 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */
8624 #if HOST_BITS_PER_WIDE_INT >= 64
8625 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32
8626 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian]));
8628 operands[3] = gen_int_mode (val, DImode);
8629 #else
8630 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode);
8631 #endif
8632 }")
8634 ;; Don't have reload use general registers to load a constant. First,
8635 ;; it might not work if the output operand is the equivalent of
8636 ;; a non-offsettable memref, but also it is less efficient than loading
8637 ;; the constant into an FP register, since it will probably be used there.
8638 ;; The "??" is a kludge until we can figure out a more reasonable way
8639 ;; of handling these non-offsettable values.
8640 (define_insn "*movdf_hardfloat32"
8641 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r")
8642 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))]
8643 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8644 && (gpc_reg_operand (operands[0], DFmode)
8645 || gpc_reg_operand (operands[1], DFmode))"
8646 "*
8647 {
8648 switch (which_alternative)
8649 {
8650 default:
8651 abort ();
8652 case 0:
8653 /* We normally copy the low-numbered register first. However, if
8654 the first register operand 0 is the same as the second register
8655 of operand 1, we must copy in the opposite order. */
8656 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8657 return \"mr %L0,%L1\;mr %0,%1\";
8658 else
8659 return \"mr %0,%1\;mr %L0,%L1\";
8660 case 1:
8661 if (offsettable_memref_p (operands[1])
8662 || (GET_CODE (operands[1]) == MEM
8663 && (GET_CODE (XEXP (operands[1], 0)) == LO_SUM
8664 || GET_CODE (XEXP (operands[1], 0)) == PRE_INC
8665 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)))
8666 {
8667 /* If the low-address word is used in the address, we must load
8668 it last. Otherwise, load it first. Note that we cannot have
8669 auto-increment in that case since the address register is
8670 known to be dead. */
8671 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8672 operands[1], 0))
8673 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8674 else
8675 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8676 }
8677 else
8678 {
8679 rtx addreg;
8681 addreg = find_addr_reg (XEXP (operands[1], 0));
8682 if (refers_to_regno_p (REGNO (operands[0]),
8683 REGNO (operands[0]) + 1,
8684 operands[1], 0))
8685 {
8686 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8687 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8688 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8689 return \"{lx|lwzx} %0,%1\";
8690 }
8691 else
8692 {
8693 output_asm_insn (\"{lx|lwzx} %0,%1\", operands);
8694 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8695 output_asm_insn (\"{lx|lwzx} %L0,%1\", operands);
8696 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8697 return \"\";
8698 }
8699 }
8700 case 2:
8701 if (offsettable_memref_p (operands[0])
8702 || (GET_CODE (operands[0]) == MEM
8703 && (GET_CODE (XEXP (operands[0], 0)) == LO_SUM
8704 || GET_CODE (XEXP (operands[0], 0)) == PRE_INC
8705 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)))
8706 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8707 else
8708 {
8709 rtx addreg;
8711 addreg = find_addr_reg (XEXP (operands[0], 0));
8712 output_asm_insn (\"{stx|stwx} %1,%0\", operands);
8713 output_asm_insn (\"{cal|la} %0,4(%0)\", &addreg);
8714 output_asm_insn (\"{stx|stwx} %L1,%0\", operands);
8715 output_asm_insn (\"{cal|la} %0,-4(%0)\", &addreg);
8716 return \"\";
8717 }
8718 case 3:
8719 return \"fmr %0,%1\";
8720 case 4:
8721 return \"lfd%U1%X1 %0,%1\";
8722 case 5:
8723 return \"stfd%U0%X0 %1,%0\";
8724 case 6:
8725 case 7:
8726 case 8:
8727 return \"#\";
8728 }
8729 }"
8730 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*")
8731 (set_attr "length" "8,16,16,4,4,4,8,12,16")])
8733 (define_insn "*movdf_softfloat32"
8734 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r")
8735 (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))]
8736 "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8737 && (gpc_reg_operand (operands[0], DFmode)
8738 || gpc_reg_operand (operands[1], DFmode))"
8739 "*
8740 {
8741 switch (which_alternative)
8742 {
8743 default:
8744 abort ();
8745 case 0:
8746 /* We normally copy the low-numbered register first. However, if
8747 the first register operand 0 is the same as the second register of
8748 operand 1, we must copy in the opposite order. */
8749 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8750 return \"mr %L0,%L1\;mr %0,%1\";
8751 else
8752 return \"mr %0,%1\;mr %L0,%L1\";
8753 case 1:
8754 /* If the low-address word is used in the address, we must load
8755 it last. Otherwise, load it first. Note that we cannot have
8756 auto-increment in that case since the address register is
8757 known to be dead. */
8758 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
8759 operands[1], 0))
8760 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
8761 else
8762 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
8763 case 2:
8764 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
8765 case 3:
8766 case 4:
8767 case 5:
8768 return \"#\";
8769 }
8770 }"
8771 [(set_attr "type" "*,load,store,*,*,*")
8772 (set_attr "length" "8,8,8,8,12,16")])
8774 (define_insn "*movdf_hardfloat64"
8775 [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!cl,!r,!r,!r,!r")
8776 (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,r,h,G,H,F"))]
8777 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
8778 && (gpc_reg_operand (operands[0], DFmode)
8779 || gpc_reg_operand (operands[1], DFmode))"
8780 "@
8781 mr %0,%1
8782 ld%U1%X1 %0,%1
8783 std%U0%X0 %1,%0
8784 fmr %0,%1
8785 lfd%U1%X1 %0,%1
8786 stfd%U0%X0 %1,%0
8787 mt%0 %1
8788 mf%1 %0
8789 #
8790 #
8791 #"
8792 [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*")
8793 (set_attr "length" "4,4,4,4,4,4,4,4,8,12,16")])
8795 (define_insn "*movdf_softfloat64"
8796 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r")
8797 (match_operand:DF 1 "input_operand" "r,r,h,m,r,G,H,F"))]
8798 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)
8799 && (gpc_reg_operand (operands[0], DFmode)
8800 || gpc_reg_operand (operands[1], DFmode))"
8801 "@
8802 mr %0,%1
8803 mt%0 %1
8804 mf%1 %0
8805 ld%U1%X1 %0,%1
8806 std%U0%X0 %1,%0
8807 #
8808 #
8809 #"
8810 [(set_attr "type" "*,*,*,load,store,*,*,*")
8811 (set_attr "length" "4,4,4,4,4,8,12,16")])
8812 \f
8813 (define_expand "movtf"
8814 [(set (match_operand:TF 0 "general_operand" "")
8815 (match_operand:TF 1 "any_operand" ""))]
8816 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8817 && TARGET_LONG_DOUBLE_128"
8818 "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }")
8820 (define_insn "*movtf_internal"
8821 [(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,m,!r,!r,!r")
8822 (match_operand:TF 1 "input_operand" "f,m,f,G,H,F"))]
8823 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8824 && TARGET_LONG_DOUBLE_128
8825 && (gpc_reg_operand (operands[0], TFmode)
8826 || gpc_reg_operand (operands[1], TFmode))"
8827 "*
8828 {
8829 switch (which_alternative)
8830 {
8831 default:
8832 abort ();
8833 case 0:
8834 /* We normally copy the low-numbered register first. However, if
8835 the first register operand 0 is the same as the second register of
8836 operand 1, we must copy in the opposite order. */
8837 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
8838 return \"fmr %L0,%L1\;fmr %0,%1\";
8839 else
8840 return \"fmr %0,%1\;fmr %L0,%L1\";
8841 case 1:
8842 return \"lfd %0,%1\;lfd %L0,%Y1\";
8843 case 2:
8844 return \"stfd %1,%0\;stfd %L1,%Y0\";
8845 case 3:
8846 case 4:
8847 case 5:
8848 return \"#\";
8849 }
8850 }"
8851 [(set_attr "type" "fp,fpload,fpstore,*,*,*")
8852 (set_attr "length" "8,8,8,12,16,20")])
8854 (define_split
8855 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8856 (match_operand:TF 1 "easy_fp_constant" ""))]
8857 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8858 && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_POWERPC64
8859 && TARGET_LONG_DOUBLE_128 && reload_completed
8860 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8861 || (GET_CODE (operands[0]) == SUBREG
8862 && GET_CODE (SUBREG_REG (operands[0])) == REG
8863 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8864 [(set (match_dup 2) (match_dup 6))
8865 (set (match_dup 3) (match_dup 7))
8866 (set (match_dup 4) (match_dup 8))
8867 (set (match_dup 5) (match_dup 9))]
8868 "
8869 {
8870 long l[4];
8871 REAL_VALUE_TYPE rv;
8873 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8874 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, l);
8876 operands[2] = operand_subword (operands[0], 0, 0, TFmode);
8877 operands[3] = operand_subword (operands[0], 1, 0, TFmode);
8878 operands[4] = operand_subword (operands[0], 2, 0, TFmode);
8879 operands[5] = operand_subword (operands[0], 3, 0, TFmode);
8880 operands[6] = gen_int_mode (l[0], SImode);
8881 operands[7] = gen_int_mode (l[1], SImode);
8882 operands[8] = gen_int_mode (l[2], SImode);
8883 operands[9] = gen_int_mode (l[3], SImode);
8884 }")
8886 (define_split
8887 [(set (match_operand:TF 0 "gpc_reg_operand" "")
8888 (match_operand:TF 1 "easy_fp_constant" ""))]
8889 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
8890 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64
8891 && TARGET_LONG_DOUBLE_128 && reload_completed
8892 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31)
8893 || (GET_CODE (operands[0]) == SUBREG
8894 && GET_CODE (SUBREG_REG (operands[0])) == REG
8895 && REGNO (SUBREG_REG (operands[0])) <= 31))"
8896 [(set (match_dup 2) (match_dup 4))
8897 (set (match_dup 3) (match_dup 5))]
8898 "
8899 {
8900 long l[4];
8901 REAL_VALUE_TYPE rv;
8902 HOST_WIDE_INT val;
8904 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
8905 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, l);
8907 operands[2] = gen_lowpart (DImode, operands[0]);
8908 operands[3] = gen_highpart (DImode, operands[0]);
8909 #if HOST_BITS_PER_WIDE_INT >= 64
8910 val = ((HOST_WIDE_INT)(unsigned long)l[0] << 32
8911 | ((HOST_WIDE_INT)(unsigned long)l[1]));
8912 operands[4] = gen_int_mode (val, DImode);
8914 val = ((HOST_WIDE_INT)(unsigned long)l[2] << 32
8915 | ((HOST_WIDE_INT)(unsigned long)l[3]));
8916 operands[5] = gen_int_mode (val, DImode);
8917 #else
8918 operands[4] = immed_double_const (l[1], l[0], DImode);
8919 operands[5] = immed_double_const (l[3], l[2], DImode);
8920 #endif
8921 }")
8923 (define_insn "extenddftf2"
8924 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8925 (float_extend:TF (match_operand:DF 1 "gpc_reg_operand" "f")))]
8926 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8927 && TARGET_LONG_DOUBLE_128"
8928 "*
8929 {
8930 if (REGNO (operands[0]) == REGNO (operands[1]))
8931 return \"fsub %L0,%L0,%L0\";
8932 else
8933 return \"fmr %0,%1\;fsub %L0,%L0,%L0\";
8934 }"
8935 [(set_attr "type" "fp")])
8937 (define_insn "extendsftf2"
8938 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8939 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "f")))]
8940 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8941 && TARGET_LONG_DOUBLE_128"
8942 "*
8943 {
8944 if (REGNO (operands[0]) == REGNO (operands[1]))
8945 return \"fsub %L0,%L0,%L0\";
8946 else
8947 return \"fmr %0,%1\;fsub %L0,%L0,%L0\";
8948 }"
8949 [(set_attr "type" "fp")])
8951 (define_insn "trunctfdf2"
8952 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
8953 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))]
8954 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8955 && TARGET_LONG_DOUBLE_128"
8956 "fadd %0,%1,%L1"
8957 [(set_attr "type" "fp")
8958 (set_attr "length" "8")])
8960 (define_insn_and_split "trunctfsf2"
8961 [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
8962 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))
8963 (clobber (match_scratch:DF 2 "=f"))]
8964 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT
8965 && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8966 "#"
8967 "&& reload_completed"
8968 [(set (match_dup 2)
8969 (float_truncate:DF (match_dup 1)))
8970 (set (match_dup 0)
8971 (float_truncate:SF (match_dup 2)))]
8972 "")
8974 (define_insn_and_split "floatditf2"
8975 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8976 (float:TF (match_operand:DI 1 "gpc_reg_operand" "*f")))
8977 (clobber (match_scratch:DF 2 "=f"))]
8978 "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
8979 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
8980 "#"
8981 "&& reload_completed"
8982 [(set (match_dup 2)
8983 (float:DF (match_dup 1)))
8984 (set (match_dup 0)
8985 (float_extend:TF (match_dup 2)))]
8986 "")
8988 (define_insn_and_split "floatsitf2"
8989 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
8990 (float:TF (match_operand:SI 1 "gpc_reg_operand" "r")))
8991 (clobber (match_scratch:DF 2 "=f"))]
8992 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
8993 && TARGET_LONG_DOUBLE_128"
8994 "#"
8995 "&& reload_completed"
8996 [(set (match_dup 2)
8997 (float:DF (match_dup 1)))
8998 (set (match_dup 0)
8999 (float_extend:TF (match_dup 2)))]
9000 "")
9002 (define_insn_and_split "fix_trunctfdi2"
9003 [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
9004 (fix:DI (match_operand:TF 1 "gpc_reg_operand" "f")))
9005 (clobber (match_scratch:DF 2 "=f"))]
9006 "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64
9007 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
9008 "#"
9009 "&& reload_completed"
9010 [(set (match_dup 2)
9011 (float_truncate:DF (match_dup 1)))
9012 (set (match_dup 0)
9013 (fix:DI (match_dup 2)))]
9014 "")
9016 (define_insn_and_split "fix_trunctfsi2"
9017 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
9018 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f")))
9019 (clobber (match_scratch:DF 2 "=f"))]
9020 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
9021 && TARGET_LONG_DOUBLE_128"
9022 "#"
9023 "&& reload_completed"
9024 [(set (match_dup 2)
9025 (float_truncate:DF (match_dup 1)))
9026 (set (match_dup 0)
9027 (fix:SI (match_dup 2)))]
9028 "")
9030 (define_insn "negtf2"
9031 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
9032 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
9033 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
9034 && TARGET_LONG_DOUBLE_128"
9035 "*
9036 {
9037 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9038 return \"fneg %L0,%L1\;fneg %0,%1\";
9039 else
9040 return \"fneg %0,%1\;fneg %L0,%L1\";
9041 }"
9042 [(set_attr "type" "fp")
9043 (set_attr "length" "8")])
9045 (define_insn "abstf2"
9046 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
9047 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))]
9048 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
9049 && TARGET_LONG_DOUBLE_128"
9050 "*
9051 {
9052 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9053 return \"fabs %L0,%L1\;fabs %0,%1\";
9054 else
9055 return \"fabs %0,%1\;fabs %L0,%L1\";
9056 }"
9057 [(set_attr "type" "fp")
9058 (set_attr "length" "8")])
9060 (define_insn ""
9061 [(set (match_operand:TF 0 "gpc_reg_operand" "=f")
9062 (neg:TF (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f"))))]
9063 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
9064 && TARGET_LONG_DOUBLE_128"
9065 "*
9066 {
9067 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9068 return \"fnabs %L0,%L1\;fnabs %0,%1\";
9069 else
9070 return \"fnabs %0,%1\;fnabs %L0,%L1\";
9071 }"
9072 [(set_attr "type" "fp")
9073 (set_attr "length" "8")])
9074 \f
9075 ;; Next come the multi-word integer load and store and the load and store
9076 ;; multiple insns.
9077 (define_expand "movdi"
9078 [(set (match_operand:DI 0 "general_operand" "")
9079 (match_operand:DI 1 "any_operand" ""))]
9080 ""
9081 "{ rs6000_emit_move (operands[0], operands[1], DImode); DONE; }")
9083 (define_insn "*movdi_internal32"
9084 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,f,f,m,r,r,r,r,r")
9085 (match_operand:DI 1 "input_operand" "r,m,r,f,m,f,IJK,n,G,H,F"))]
9086 "! TARGET_POWERPC64
9087 && (gpc_reg_operand (operands[0], DImode)
9088 || gpc_reg_operand (operands[1], DImode))"
9089 "*
9090 {
9091 switch (which_alternative)
9092 {
9093 default:
9094 abort ();
9095 case 0:
9096 /* We normally copy the low-numbered register first. However, if
9097 the first register operand 0 is the same as the second register of
9098 operand 1, we must copy in the opposite order. */
9099 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9100 return \"mr %L0,%L1\;mr %0,%1\";
9101 else
9102 return \"mr %0,%1\;mr %L0,%L1\";
9103 case 1:
9104 /* If the low-address word is used in the address, we must load it
9105 last. Otherwise, load it first. Note that we cannot have
9106 auto-increment in that case since the address register is known to be
9107 dead. */
9108 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
9109 operands[1], 0))
9110 return \"{l|lwz} %L0,%L1\;{l|lwz} %0,%1\";
9111 else
9112 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\";
9113 case 2:
9114 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\";
9115 case 3:
9116 return \"fmr %0,%1\";
9117 case 4:
9118 return \"lfd%U1%X1 %0,%1\";
9119 case 5:
9120 return \"stfd%U0%X0 %1,%0\";
9121 case 6:
9122 case 7:
9123 case 8:
9124 case 9:
9125 case 10:
9126 return \"#\";
9127 }
9128 }"
9129 [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*")
9130 (set_attr "length" "8,8,8,4,4,4,8,12,8,12,16")])
9132 (define_split
9133 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9134 (match_operand:DI 1 "const_int_operand" ""))]
9135 "! TARGET_POWERPC64 && reload_completed"
9136 [(set (match_dup 2) (match_dup 4))
9137 (set (match_dup 3) (match_dup 1))]
9138 "
9139 {
9140 HOST_WIDE_INT value = INTVAL (operands[1]);
9141 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9142 DImode);
9143 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9144 DImode);
9145 #if HOST_BITS_PER_WIDE_INT == 32
9146 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx;
9147 #else
9148 operands[4] = GEN_INT (value >> 32);
9149 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
9150 #endif
9151 }")
9153 (define_split
9154 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9155 (match_operand:DI 1 "const_double_operand" ""))]
9156 "HOST_BITS_PER_WIDE_INT == 32 && ! TARGET_POWERPC64 && reload_completed"
9157 [(set (match_dup 2) (match_dup 4))
9158 (set (match_dup 3) (match_dup 5))]
9159 "
9160 {
9161 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0,
9162 DImode);
9163 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0,
9164 DImode);
9165 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1]));
9166 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1]));
9167 }")
9169 (define_insn "*movdi_internal64"
9170 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,?f,f,m,r,*h,*h")
9171 (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
9172 "TARGET_POWERPC64
9173 && (gpc_reg_operand (operands[0], DImode)
9174 || gpc_reg_operand (operands[1], DImode))"
9175 "@
9176 mr %0,%1
9177 ld%U1%X1 %0,%1
9178 std%U0%X0 %1,%0
9179 li %0,%1
9180 lis %0,%v1
9181 #
9182 {cal|la} %0,%a1
9183 fmr %0,%1
9184 lfd%U1%X1 %0,%1
9185 stfd%U0%X0 %1,%0
9186 mf%1 %0
9187 mt%0 %1
9188 {cror 0,0,0|nop}"
9189 [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*")
9190 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
9192 ;; immediate value valid for a single instruction hiding in a const_double
9193 (define_insn ""
9194 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
9195 (match_operand:DI 1 "const_double_operand" "F"))]
9196 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64
9197 && GET_CODE (operands[1]) == CONST_DOUBLE
9198 && num_insns_constant (operands[1], DImode) == 1"
9199 "*
9200 {
9201 return ((unsigned HOST_WIDE_INT)
9202 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000)
9203 ? \"li %0,%1\" : \"lis %0,%v1\";
9204 }")
9206 ;; Generate all one-bits and clear left or right.
9207 ;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber.
9208 (define_split
9209 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9210 (match_operand:DI 1 "mask64_operand" ""))]
9211 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9212 [(set (match_dup 0) (const_int -1))
9213 (set (match_dup 0)
9214 (and:DI (rotate:DI (match_dup 0)
9215 (const_int 0))
9216 (match_dup 1)))]
9217 "")
9219 ;; Split a load of a large constant into the appropriate five-instruction
9220 ;; sequence. Handle anything in a constant number of insns.
9221 ;; When non-easy constants can go in the TOC, this should use
9222 ;; easy_fp_constant predicate.
9223 (define_split
9224 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9225 (match_operand:DI 1 "const_int_operand" ""))]
9226 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9227 [(set (match_dup 0) (match_dup 2))
9228 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9229 "
9230 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9232 if (tem == operands[0])
9233 DONE;
9234 else
9235 FAIL;
9236 }")
9238 (define_split
9239 [(set (match_operand:DI 0 "gpc_reg_operand" "")
9240 (match_operand:DI 1 "const_double_operand" ""))]
9241 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1"
9242 [(set (match_dup 0) (match_dup 2))
9243 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
9244 "
9245 { rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5);
9247 if (tem == operands[0])
9248 DONE;
9249 else
9250 FAIL;
9251 }")
9253 ;; Split a load of a large constant into the appropriate five-instruction
9254 (define_insn "*movdi_internal2"
9255 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
9256 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r,r")
9257 (const_int 0)))
9258 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (match_dup 1))]
9259 "TARGET_POWERPC64"
9260 "@
9261 mr. %0,%1
9262 #"
9263 [(set_attr "type" "compare")
9264 (set_attr "length" "4,8")])
9266 (define_split
9267 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
9268 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "")
9269 (const_int 0)))
9270 (set (match_operand:DI 0 "gpc_reg_operand" "") (match_dup 1))]
9271 "TARGET_POWERPC64 && reload_completed"
9272 [(set (match_dup 0) (match_dup 1))
9273 (set (match_dup 2)
9274 (compare:CC (match_dup 0)
9275 (const_int 0)))]
9276 "")
9277 \f
9278 ;; TImode is similar, except that we usually want to compute the address into
9279 ;; a register and use lsi/stsi (the exception is during reload). MQ is also
9280 ;; clobbered in stsi for POWER, so we need a SCRATCH for it.
9281 (define_expand "movti"
9282 [(parallel [(set (match_operand:TI 0 "general_operand" "")
9283 (match_operand:TI 1 "general_operand" ""))
9284 (clobber (scratch:SI))])]
9285 "TARGET_STRING || TARGET_POWERPC64"
9286 "{ rs6000_emit_move (operands[0], operands[1], TImode); DONE; }")
9288 ;; We say that MQ is clobbered in the last alternative because the first
9289 ;; alternative would never get used otherwise since it would need a reload
9290 ;; while the 2nd alternative would not. We put memory cases first so they
9291 ;; are preferred. Otherwise, we'd try to reload the output instead of
9292 ;; giving the SCRATCH mq.
9293 (define_insn "*movti_power"
9294 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
9295 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
9296 (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
9297 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9298 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9299 "*
9300 {
9301 switch (which_alternative)
9302 {
9303 default:
9304 abort ();
9306 case 0:
9307 return \"{stsi|stswi} %1,%P0,16\";
9309 case 1:
9310 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
9312 case 2:
9313 /* Normally copy registers with lowest numbered register copied first.
9314 But copy in the other order if the first register of the output
9315 is the second, third, or fourth register in the input. */
9316 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
9317 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
9318 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
9319 else
9320 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
9321 case 3:
9322 /* If the address is not used in the output, we can use lsi. Otherwise,
9323 fall through to generating four loads. */
9324 if (! reg_overlap_mentioned_p (operands[0], operands[1]))
9325 return \"{lsi|lswi} %0,%P1,16\";
9326 /* ... fall through ... */
9327 case 4:
9328 /* If the address register is the same as the register for the lowest-
9329 addressed word, load it last. Similarly for the next two words.
9330 Otherwise load lowest address to highest. */
9331 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
9332 operands[1], 0))
9333 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
9334 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
9335 REGNO (operands[0]) + 2, operands[1], 0))
9336 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
9337 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
9338 REGNO (operands[0]) + 3, operands[1], 0))
9339 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
9340 else
9341 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
9342 }
9343 }"
9344 [(set_attr "type" "store,store,*,load,load")
9345 (set_attr "length" "4,16,16,4,16")])
9347 (define_insn "*movti_string"
9348 [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r")
9349 (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
9350 (clobber (match_scratch:SI 2 "X,X,X,X,X"))]
9351 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9352 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))"
9353 "*
9354 {
9355 switch (which_alternative)
9356 {
9357 default:
9358 abort ();
9360 case 0:
9361 return \"{stsi|stswi} %1,%P0,16\";
9362 case 1:
9363 return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\";
9364 case 2:
9365 /* Normally copy registers with lowest numbered register copied first.
9366 But copy in the other order if the first register of the output
9367 is the second, third, or fourth register in the input. */
9368 if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
9369 && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
9370 return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\";
9371 else
9372 return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\";
9373 case 3:
9374 /* If the address is not used in the output, we can use lsi. Otherwise,
9375 fall through to generating four loads. */
9376 if (! reg_overlap_mentioned_p (operands[0], operands[1]))
9377 return \"{lsi|lswi} %0,%P1,16\";
9378 /* ... fall through ... */
9379 case 4:
9380 /* If the address register is the same as the register for the lowest-
9381 addressed word, load it last. Similarly for the next two words.
9382 Otherwise load lowest address to highest. */
9383 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
9384 operands[1], 0))
9385 return \"{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %0,%1\";
9386 else if (refers_to_regno_p (REGNO (operands[0]) + 1,
9387 REGNO (operands[0]) + 2, operands[1], 0))
9388 return \"{l|lwz} %0,%1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\;{l|lwz} %L0,%L1\";
9389 else if (refers_to_regno_p (REGNO (operands[0]) + 2,
9390 REGNO (operands[0]) + 3, operands[1], 0))
9391 return \"{l|lwz} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Z0,%Z1\;{l|lwz} %Y0,%Y1\";
9392 else
9393 return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\";
9394 }
9395 }"
9396 [(set_attr "type" "store,store,*,load,load")
9397 (set_attr "length" "4,16,16,4,16")])
9399 (define_insn "*movti_ppc64"
9400 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m")
9401 (match_operand:TI 1 "input_operand" "r,m,r"))]
9402 "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode)
9403 || gpc_reg_operand (operands[1], TImode))"
9404 "*
9405 {
9406 switch (which_alternative)
9407 {
9408 default:
9409 abort ();
9410 case 0:
9411 /* We normally copy the low-numbered register first. However, if
9412 the first register operand 0 is the same as the second register of
9413 operand 1, we must copy in the opposite order. */
9414 if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
9415 return \"mr %L0,%L1\;mr %0,%1\";
9416 else
9417 return \"mr %0,%1\;mr %L0,%L1\";
9418 case 1:
9419 /* If the low-address word is used in the address, we must load it
9420 last. Otherwise, load it first. Note that we cannot have
9421 auto-increment in that case since the address register is known to be
9422 dead. */
9423 if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
9424 operands[1], 0))
9425 return \"ld %L0,%L1\;ld %0,%1\";
9426 else
9427 return \"ld%U1 %0,%1\;ld %L0,%L1\";
9428 case 2:
9429 return \"std%U0 %1,%0\;std %L1,%L0\";
9430 }
9431 }"
9432 [(set_attr "type" "*,load,store")
9433 (set_attr "length" "8,8,8")])
9434 \f
9435 (define_expand "load_multiple"
9436 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9437 (match_operand:SI 1 "" ""))
9438 (use (match_operand:SI 2 "" ""))])]
9439 "TARGET_STRING && !TARGET_POWERPC64"
9440 "
9441 {
9442 int regno;
9443 int count;
9444 rtx op1;
9445 int i;
9447 /* Support only loading a constant number of fixed-point registers from
9448 memory and only bother with this if more than two; the machine
9449 doesn't support more than eight. */
9450 if (GET_CODE (operands[2]) != CONST_INT
9451 || INTVAL (operands[2]) <= 2
9452 || INTVAL (operands[2]) > 8
9453 || GET_CODE (operands[1]) != MEM
9454 || GET_CODE (operands[0]) != REG
9455 || REGNO (operands[0]) >= 32)
9456 FAIL;
9458 count = INTVAL (operands[2]);
9459 regno = REGNO (operands[0]);
9461 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
9462 op1 = replace_equiv_address (operands[1],
9463 force_reg (SImode, XEXP (operands[1], 0)));
9465 for (i = 0; i < count; i++)
9466 XVECEXP (operands[3], 0, i)
9467 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i),
9468 adjust_address_nv (op1, SImode, i * 4));
9469 }")
9471 (define_insn "*ldmsi8"
9472 [(match_parallel 0 "load_multiple_operation"
9473 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9474 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9475 (set (match_operand:SI 3 "gpc_reg_operand" "")
9476 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9477 (set (match_operand:SI 4 "gpc_reg_operand" "")
9478 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9479 (set (match_operand:SI 5 "gpc_reg_operand" "")
9480 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9481 (set (match_operand:SI 6 "gpc_reg_operand" "")
9482 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9483 (set (match_operand:SI 7 "gpc_reg_operand" "")
9484 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9485 (set (match_operand:SI 8 "gpc_reg_operand" "")
9486 (mem:SI (plus:SI (match_dup 1) (const_int 24))))
9487 (set (match_operand:SI 9 "gpc_reg_operand" "")
9488 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])]
9489 "TARGET_STRING && XVECLEN (operands[0], 0) == 8"
9490 "*
9491 { return rs6000_output_load_multiple (operands); }"
9492 [(set_attr "type" "load")
9493 (set_attr "length" "32")])
9495 (define_insn "*ldmsi7"
9496 [(match_parallel 0 "load_multiple_operation"
9497 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9498 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9499 (set (match_operand:SI 3 "gpc_reg_operand" "")
9500 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9501 (set (match_operand:SI 4 "gpc_reg_operand" "")
9502 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9503 (set (match_operand:SI 5 "gpc_reg_operand" "")
9504 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9505 (set (match_operand:SI 6 "gpc_reg_operand" "")
9506 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9507 (set (match_operand:SI 7 "gpc_reg_operand" "")
9508 (mem:SI (plus:SI (match_dup 1) (const_int 20))))
9509 (set (match_operand:SI 8 "gpc_reg_operand" "")
9510 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])]
9511 "TARGET_STRING && XVECLEN (operands[0], 0) == 7"
9512 "*
9513 { return rs6000_output_load_multiple (operands); }"
9514 [(set_attr "type" "load")
9515 (set_attr "length" "32")])
9517 (define_insn "*ldmsi6"
9518 [(match_parallel 0 "load_multiple_operation"
9519 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9520 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9521 (set (match_operand:SI 3 "gpc_reg_operand" "")
9522 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9523 (set (match_operand:SI 4 "gpc_reg_operand" "")
9524 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9525 (set (match_operand:SI 5 "gpc_reg_operand" "")
9526 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9527 (set (match_operand:SI 6 "gpc_reg_operand" "")
9528 (mem:SI (plus:SI (match_dup 1) (const_int 16))))
9529 (set (match_operand:SI 7 "gpc_reg_operand" "")
9530 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])]
9531 "TARGET_STRING && XVECLEN (operands[0], 0) == 6"
9532 "*
9533 { return rs6000_output_load_multiple (operands); }"
9534 [(set_attr "type" "load")
9535 (set_attr "length" "32")])
9537 (define_insn "*ldmsi5"
9538 [(match_parallel 0 "load_multiple_operation"
9539 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9540 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9541 (set (match_operand:SI 3 "gpc_reg_operand" "")
9542 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9543 (set (match_operand:SI 4 "gpc_reg_operand" "")
9544 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9545 (set (match_operand:SI 5 "gpc_reg_operand" "")
9546 (mem:SI (plus:SI (match_dup 1) (const_int 12))))
9547 (set (match_operand:SI 6 "gpc_reg_operand" "")
9548 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])]
9549 "TARGET_STRING && XVECLEN (operands[0], 0) == 5"
9550 "*
9551 { return rs6000_output_load_multiple (operands); }"
9552 [(set_attr "type" "load")
9553 (set_attr "length" "32")])
9555 (define_insn "*ldmsi4"
9556 [(match_parallel 0 "load_multiple_operation"
9557 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9558 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9559 (set (match_operand:SI 3 "gpc_reg_operand" "")
9560 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9561 (set (match_operand:SI 4 "gpc_reg_operand" "")
9562 (mem:SI (plus:SI (match_dup 1) (const_int 8))))
9563 (set (match_operand:SI 5 "gpc_reg_operand" "")
9564 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])]
9565 "TARGET_STRING && XVECLEN (operands[0], 0) == 4"
9566 "*
9567 { return rs6000_output_load_multiple (operands); }"
9568 [(set_attr "type" "load")
9569 (set_attr "length" "32")])
9571 (define_insn "*ldmsi3"
9572 [(match_parallel 0 "load_multiple_operation"
9573 [(set (match_operand:SI 2 "gpc_reg_operand" "")
9574 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")))
9575 (set (match_operand:SI 3 "gpc_reg_operand" "")
9576 (mem:SI (plus:SI (match_dup 1) (const_int 4))))
9577 (set (match_operand:SI 4 "gpc_reg_operand" "")
9578 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])]
9579 "TARGET_STRING && XVECLEN (operands[0], 0) == 3"
9580 "*
9581 { return rs6000_output_load_multiple (operands); }"
9582 [(set_attr "type" "load")
9583 (set_attr "length" "32")])
9585 (define_expand "store_multiple"
9586 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
9587 (match_operand:SI 1 "" ""))
9588 (clobber (scratch:SI))
9589 (use (match_operand:SI 2 "" ""))])]
9590 "TARGET_STRING && !TARGET_POWERPC64"
9591 "
9592 {
9593 int regno;
9594 int count;
9595 rtx to;
9596 rtx op0;
9597 int i;
9599 /* Support only storing a constant number of fixed-point registers to
9600 memory and only bother with this if more than two; the machine
9601 doesn't support more than eight. */
9602 if (GET_CODE (operands[2]) != CONST_INT
9603 || INTVAL (operands[2]) <= 2
9604 || INTVAL (operands[2]) > 8
9605 || GET_CODE (operands[0]) != MEM
9606 || GET_CODE (operands[1]) != REG
9607 || REGNO (operands[1]) >= 32)
9608 FAIL;
9610 count = INTVAL (operands[2]);
9611 regno = REGNO (operands[1]);
9613 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
9614 to = force_reg (SImode, XEXP (operands[0], 0));
9615 op0 = replace_equiv_address (operands[0], to);
9617 XVECEXP (operands[3], 0, 0)
9618 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]);
9619 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode,
9620 gen_rtx_SCRATCH (SImode));
9622 for (i = 1; i < count; i++)
9623 XVECEXP (operands[3], 0, i + 1)
9624 = gen_rtx_SET (VOIDmode,
9625 adjust_address_nv (op0, SImode, i * 4),
9626 gen_rtx_REG (SImode, regno + i));
9627 }")
9629 (define_insn "*store_multiple_power"
9630 [(match_parallel 0 "store_multiple_operation"
9631 [(set (match_operand:SI 1 "indirect_operand" "=Q")
9632 (match_operand:SI 2 "gpc_reg_operand" "r"))
9633 (clobber (match_scratch:SI 3 "=q"))])]
9634 "TARGET_STRING && TARGET_POWER"
9635 "{stsi|stswi} %2,%P1,%O0"
9636 [(set_attr "type" "store")])
9638 (define_insn "*store_multiple_string"
9639 [(match_parallel 0 "store_multiple_operation"
9640 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
9641 (match_operand:SI 2 "gpc_reg_operand" "r"))
9642 (clobber (match_scratch:SI 3 "X"))])]
9643 "TARGET_STRING && ! TARGET_POWER"
9644 "{stsi|stswi} %2,%1,%O0"
9645 [(set_attr "type" "store")])
9647 \f
9648 ;; String/block move insn.
9649 ;; Argument 0 is the destination
9650 ;; Argument 1 is the source
9651 ;; Argument 2 is the length
9652 ;; Argument 3 is the alignment
9654 (define_expand "movstrsi"
9655 [(parallel [(set (match_operand:BLK 0 "" "")
9656 (match_operand:BLK 1 "" ""))
9657 (use (match_operand:SI 2 "" ""))
9658 (use (match_operand:SI 3 "" ""))])]
9659 ""
9660 "
9661 {
9662 if (expand_block_move (operands))
9663 DONE;
9664 else
9665 FAIL;
9666 }")
9668 ;; Move up to 32 bytes at a time. The fixed registers are needed because the
9669 ;; register allocator doesn't have a clue about allocating 8 word registers.
9670 ;; rD/rS = r5 is preferred, efficient form.
9671 (define_expand "movstrsi_8reg"
9672 [(parallel [(set (match_operand 0 "" "")
9673 (match_operand 1 "" ""))
9674 (use (match_operand 2 "" ""))
9675 (use (match_operand 3 "" ""))
9676 (clobber (reg:SI 5))
9677 (clobber (reg:SI 6))
9678 (clobber (reg:SI 7))
9679 (clobber (reg:SI 8))
9680 (clobber (reg:SI 9))
9681 (clobber (reg:SI 10))
9682 (clobber (reg:SI 11))
9683 (clobber (reg:SI 12))
9684 (clobber (match_scratch:SI 4 ""))])]
9685 "TARGET_STRING"
9686 "")
9688 (define_insn ""
9689 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9690 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9691 (use (match_operand:SI 2 "immediate_operand" "i"))
9692 (use (match_operand:SI 3 "immediate_operand" "i"))
9693 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9694 (clobber (reg:SI 6))
9695 (clobber (reg:SI 7))
9696 (clobber (reg:SI 8))
9697 (clobber (reg:SI 9))
9698 (clobber (reg:SI 10))
9699 (clobber (reg:SI 11))
9700 (clobber (reg:SI 12))
9701 (clobber (match_scratch:SI 5 "=q"))]
9702 "TARGET_STRING && TARGET_POWER
9703 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9704 || INTVAL (operands[2]) == 0)
9705 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9706 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9707 && REGNO (operands[4]) == 5"
9708 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9709 [(set_attr "type" "load")
9710 (set_attr "length" "8")])
9712 (define_insn ""
9713 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9714 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9715 (use (match_operand:SI 2 "immediate_operand" "i"))
9716 (use (match_operand:SI 3 "immediate_operand" "i"))
9717 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9718 (clobber (reg:SI 6))
9719 (clobber (reg:SI 7))
9720 (clobber (reg:SI 8))
9721 (clobber (reg:SI 9))
9722 (clobber (reg:SI 10))
9723 (clobber (reg:SI 11))
9724 (clobber (reg:SI 12))
9725 (clobber (match_scratch:SI 5 "X"))]
9726 "TARGET_STRING && ! TARGET_POWER
9727 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9728 || INTVAL (operands[2]) == 0)
9729 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9730 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9731 && REGNO (operands[4]) == 5"
9732 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9733 [(set_attr "type" "load")
9734 (set_attr "length" "8")])
9736 (define_insn ""
9737 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9738 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9739 (use (match_operand:SI 2 "immediate_operand" "i"))
9740 (use (match_operand:SI 3 "immediate_operand" "i"))
9741 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9742 (clobber (reg:SI 6))
9743 (clobber (reg:SI 7))
9744 (clobber (reg:SI 8))
9745 (clobber (reg:SI 9))
9746 (clobber (reg:SI 10))
9747 (clobber (reg:SI 11))
9748 (clobber (reg:SI 12))
9749 (clobber (match_scratch:SI 5 "X"))]
9750 "TARGET_STRING && TARGET_POWERPC64
9751 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32)
9752 || INTVAL (operands[2]) == 0)
9753 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12)
9754 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
9755 && REGNO (operands[4]) == 5"
9756 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9757 [(set_attr "type" "load")
9758 (set_attr "length" "8")])
9760 ;; Move up to 24 bytes at a time. The fixed registers are needed because the
9761 ;; register allocator doesn't have a clue about allocating 6 word registers.
9762 ;; rD/rS = r5 is preferred, efficient form.
9763 (define_expand "movstrsi_6reg"
9764 [(parallel [(set (match_operand 0 "" "")
9765 (match_operand 1 "" ""))
9766 (use (match_operand 2 "" ""))
9767 (use (match_operand 3 "" ""))
9768 (clobber (reg:SI 5))
9769 (clobber (reg:SI 6))
9770 (clobber (reg:SI 7))
9771 (clobber (reg:SI 8))
9772 (clobber (reg:SI 9))
9773 (clobber (reg:SI 10))
9774 (clobber (match_scratch:SI 4 ""))])]
9775 "TARGET_STRING"
9776 "")
9778 (define_insn ""
9779 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9780 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9781 (use (match_operand:SI 2 "immediate_operand" "i"))
9782 (use (match_operand:SI 3 "immediate_operand" "i"))
9783 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9784 (clobber (reg:SI 6))
9785 (clobber (reg:SI 7))
9786 (clobber (reg:SI 8))
9787 (clobber (reg:SI 9))
9788 (clobber (reg:SI 10))
9789 (clobber (match_scratch:SI 5 "=q"))]
9790 "TARGET_STRING && TARGET_POWER
9791 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24
9792 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9793 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9794 && REGNO (operands[4]) == 5"
9795 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9796 [(set_attr "type" "load")
9797 (set_attr "length" "8")])
9799 (define_insn ""
9800 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9801 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9802 (use (match_operand:SI 2 "immediate_operand" "i"))
9803 (use (match_operand:SI 3 "immediate_operand" "i"))
9804 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9805 (clobber (reg:SI 6))
9806 (clobber (reg:SI 7))
9807 (clobber (reg:SI 8))
9808 (clobber (reg:SI 9))
9809 (clobber (reg:SI 10))
9810 (clobber (match_scratch:SI 5 "X"))]
9811 "TARGET_STRING && ! TARGET_POWER
9812 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9813 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9814 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9815 && REGNO (operands[4]) == 5"
9816 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9817 [(set_attr "type" "load")
9818 (set_attr "length" "8")])
9820 (define_insn ""
9821 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9822 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9823 (use (match_operand:SI 2 "immediate_operand" "i"))
9824 (use (match_operand:SI 3 "immediate_operand" "i"))
9825 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9826 (clobber (reg:SI 6))
9827 (clobber (reg:SI 7))
9828 (clobber (reg:SI 8))
9829 (clobber (reg:SI 9))
9830 (clobber (reg:SI 10))
9831 (clobber (match_scratch:SI 5 "X"))]
9832 "TARGET_STRING && TARGET_POWERPC64
9833 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32
9834 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10)
9835 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
9836 && REGNO (operands[4]) == 5"
9837 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9838 [(set_attr "type" "load")
9839 (set_attr "length" "8")])
9841 ;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
9842 ;; problems with TImode.
9843 ;; rD/rS = r5 is preferred, efficient form.
9844 (define_expand "movstrsi_4reg"
9845 [(parallel [(set (match_operand 0 "" "")
9846 (match_operand 1 "" ""))
9847 (use (match_operand 2 "" ""))
9848 (use (match_operand 3 "" ""))
9849 (clobber (reg:SI 5))
9850 (clobber (reg:SI 6))
9851 (clobber (reg:SI 7))
9852 (clobber (reg:SI 8))
9853 (clobber (match_scratch:SI 4 ""))])]
9854 "TARGET_STRING"
9855 "")
9857 (define_insn ""
9858 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9859 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9860 (use (match_operand:SI 2 "immediate_operand" "i"))
9861 (use (match_operand:SI 3 "immediate_operand" "i"))
9862 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9863 (clobber (reg:SI 6))
9864 (clobber (reg:SI 7))
9865 (clobber (reg:SI 8))
9866 (clobber (match_scratch:SI 5 "=q"))]
9867 "TARGET_STRING && TARGET_POWER
9868 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9869 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9870 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9871 && REGNO (operands[4]) == 5"
9872 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9873 [(set_attr "type" "load")
9874 (set_attr "length" "8")])
9876 (define_insn ""
9877 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9878 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9879 (use (match_operand:SI 2 "immediate_operand" "i"))
9880 (use (match_operand:SI 3 "immediate_operand" "i"))
9881 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9882 (clobber (reg:SI 6))
9883 (clobber (reg:SI 7))
9884 (clobber (reg:SI 8))
9885 (clobber (match_scratch:SI 5 "X"))]
9886 "TARGET_STRING && ! TARGET_POWER
9887 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9888 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9889 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9890 && REGNO (operands[4]) == 5"
9891 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9892 [(set_attr "type" "load")
9893 (set_attr "length" "8")])
9895 (define_insn ""
9896 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9897 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9898 (use (match_operand:SI 2 "immediate_operand" "i"))
9899 (use (match_operand:SI 3 "immediate_operand" "i"))
9900 (clobber (match_operand:SI 4 "gpc_reg_operand" "=r"))
9901 (clobber (reg:SI 6))
9902 (clobber (reg:SI 7))
9903 (clobber (reg:SI 8))
9904 (clobber (match_scratch:SI 5 "X"))]
9905 "TARGET_STRING && TARGET_POWERPC64
9906 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16
9907 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8)
9908 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
9909 && REGNO (operands[4]) == 5"
9910 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9911 [(set_attr "type" "load")
9912 (set_attr "length" "8")])
9914 ;; Move up to 8 bytes at a time.
9915 (define_expand "movstrsi_2reg"
9916 [(parallel [(set (match_operand 0 "" "")
9917 (match_operand 1 "" ""))
9918 (use (match_operand 2 "" ""))
9919 (use (match_operand 3 "" ""))
9920 (clobber (match_scratch:DI 4 ""))
9921 (clobber (match_scratch:SI 5 ""))])]
9922 "TARGET_STRING && ! TARGET_POWERPC64"
9923 "")
9925 (define_insn ""
9926 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9927 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9928 (use (match_operand:SI 2 "immediate_operand" "i"))
9929 (use (match_operand:SI 3 "immediate_operand" "i"))
9930 (clobber (match_scratch:DI 4 "=&r"))
9931 (clobber (match_scratch:SI 5 "=q"))]
9932 "TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
9933 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9934 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9935 [(set_attr "type" "load")
9936 (set_attr "length" "8")])
9938 (define_insn ""
9939 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9940 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9941 (use (match_operand:SI 2 "immediate_operand" "i"))
9942 (use (match_operand:SI 3 "immediate_operand" "i"))
9943 (clobber (match_scratch:DI 4 "=&r"))
9944 (clobber (match_scratch:SI 5 "X"))]
9945 "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
9946 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
9947 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9948 [(set_attr "type" "load")
9949 (set_attr "length" "8")])
9951 ;; Move up to 4 bytes at a time.
9952 (define_expand "movstrsi_1reg"
9953 [(parallel [(set (match_operand 0 "" "")
9954 (match_operand 1 "" ""))
9955 (use (match_operand 2 "" ""))
9956 (use (match_operand 3 "" ""))
9957 (clobber (match_scratch:SI 4 ""))
9958 (clobber (match_scratch:SI 5 ""))])]
9959 "TARGET_STRING"
9960 "")
9962 (define_insn ""
9963 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9964 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9965 (use (match_operand:SI 2 "immediate_operand" "i"))
9966 (use (match_operand:SI 3 "immediate_operand" "i"))
9967 (clobber (match_scratch:SI 4 "=&r"))
9968 (clobber (match_scratch:SI 5 "=q"))]
9969 "TARGET_STRING && TARGET_POWER
9970 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9971 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9972 [(set_attr "type" "load")
9973 (set_attr "length" "8")])
9975 (define_insn ""
9976 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b"))
9977 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b")))
9978 (use (match_operand:SI 2 "immediate_operand" "i"))
9979 (use (match_operand:SI 3 "immediate_operand" "i"))
9980 (clobber (match_scratch:SI 4 "=&r"))
9981 (clobber (match_scratch:SI 5 "X"))]
9982 "TARGET_STRING && ! TARGET_POWER
9983 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9984 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9985 [(set_attr "type" "load")
9986 (set_attr "length" "8")])
9988 (define_insn ""
9989 [(set (mem:BLK (match_operand:DI 0 "gpc_reg_operand" "b"))
9990 (mem:BLK (match_operand:DI 1 "gpc_reg_operand" "b")))
9991 (use (match_operand:SI 2 "immediate_operand" "i"))
9992 (use (match_operand:SI 3 "immediate_operand" "i"))
9993 (clobber (match_scratch:SI 4 "=&r"))
9994 (clobber (match_scratch:SI 5 "X"))]
9995 "TARGET_STRING && TARGET_POWERPC64
9996 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
9997 "{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
9998 [(set_attr "type" "load")
9999 (set_attr "length" "8")])
10001 \f
10002 ;; Define insns that do load or store with update. Some of these we can
10003 ;; get by using pre-decrement or pre-increment, but the hardware can also
10004 ;; do cases where the increment is not the size of the object.
10005 ;;
10006 ;; In all these cases, we use operands 0 and 1 for the register being
10007 ;; incremented because those are the operands that local-alloc will
10008 ;; tie and these are the pair most likely to be tieable (and the ones
10009 ;; that will benefit the most).
10011 (define_insn "*movdi_update1"
10012 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r")
10013 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
10014 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I"))))
10015 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
10016 (plus:DI (match_dup 1) (match_dup 2)))]
10017 "TARGET_POWERPC64 && TARGET_UPDATE"
10018 "@
10019 ldux %3,%0,%2
10020 ldu %3,%2(%0)"
10021 [(set_attr "type" "load")])
10023 (define_insn "*movdi_update2"
10024 [(set (match_operand:DI 3 "gpc_reg_operand" "=r")
10025 (sign_extend:DI
10026 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0")
10027 (match_operand:DI 2 "gpc_reg_operand" "r")))))
10028 (set (match_operand:DI 0 "gpc_reg_operand" "=b")
10029 (plus:DI (match_dup 1) (match_dup 2)))]
10030 "TARGET_POWERPC64"
10031 "lwaux %3,%0,%2"
10032 [(set_attr "type" "load")])
10034 (define_insn "movdi_update"
10035 [(set (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0")
10036 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))
10037 (match_operand:DI 3 "gpc_reg_operand" "r,r"))
10038 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b")
10039 (plus:DI (match_dup 1) (match_dup 2)))]
10040 "TARGET_POWERPC64 && TARGET_UPDATE"
10041 "@
10042 stdux %3,%0,%2
10043 stdu %3,%2(%0)"
10044 [(set_attr "type" "store")])
10046 (define_insn "*movsi_update1"
10047 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10048 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10049 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10050 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10051 (plus:SI (match_dup 1) (match_dup 2)))]
10052 ""
10053 "@
10054 {lux|lwzux} %3,%0,%2
10055 {lu|lwzu} %3,%2(%0)"
10056 [(set_attr "type" "load")])
10058 (define_insn "movsi_update"
10059 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10060 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10061 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
10062 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10063 (plus:SI (match_dup 1) (match_dup 2)))]
10064 "TARGET_UPDATE"
10065 "@
10066 {stux|stwux} %3,%0,%2
10067 {stu|stwu} %3,%2(%0)"
10068 [(set_attr "type" "store")])
10070 (define_insn "*movhi_update"
10071 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
10072 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10073 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10074 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10075 (plus:SI (match_dup 1) (match_dup 2)))]
10076 "TARGET_UPDATE"
10077 "@
10078 lhzux %3,%0,%2
10079 lhzu %3,%2(%0)"
10080 [(set_attr "type" "load")])
10082 (define_insn "*movhi_update2"
10083 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10084 (zero_extend:SI
10085 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10086 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10087 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10088 (plus:SI (match_dup 1) (match_dup 2)))]
10089 "TARGET_UPDATE"
10090 "@
10091 lhzux %3,%0,%2
10092 lhzu %3,%2(%0)"
10093 [(set_attr "type" "load")])
10095 (define_insn "*movhi_update3"
10096 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10097 (sign_extend:SI
10098 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10099 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10100 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10101 (plus:SI (match_dup 1) (match_dup 2)))]
10102 "TARGET_UPDATE"
10103 "@
10104 lhaux %3,%0,%2
10105 lhau %3,%2(%0)"
10106 [(set_attr "type" "load")])
10108 (define_insn "*movhi_update4"
10109 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10110 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10111 (match_operand:HI 3 "gpc_reg_operand" "r,r"))
10112 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10113 (plus:SI (match_dup 1) (match_dup 2)))]
10114 "TARGET_UPDATE"
10115 "@
10116 sthux %3,%0,%2
10117 sthu %3,%2(%0)"
10118 [(set_attr "type" "store")])
10120 (define_insn "*movqi_update1"
10121 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
10122 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10123 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10124 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10125 (plus:SI (match_dup 1) (match_dup 2)))]
10126 "TARGET_UPDATE"
10127 "@
10128 lbzux %3,%0,%2
10129 lbzu %3,%2(%0)"
10130 [(set_attr "type" "load")])
10132 (define_insn "*movqi_update2"
10133 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
10134 (zero_extend:SI
10135 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10136 (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
10137 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10138 (plus:SI (match_dup 1) (match_dup 2)))]
10139 "TARGET_UPDATE"
10140 "@
10141 lbzux %3,%0,%2
10142 lbzu %3,%2(%0)"
10143 [(set_attr "type" "load")])
10145 (define_insn "*movqi_update3"
10146 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10147 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10148 (match_operand:QI 3 "gpc_reg_operand" "r,r"))
10149 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10150 (plus:SI (match_dup 1) (match_dup 2)))]
10151 "TARGET_UPDATE"
10152 "@
10153 stbux %3,%0,%2
10154 stbu %3,%2(%0)"
10155 [(set_attr "type" "store")])
10157 (define_insn "*movsf_update1"
10158 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
10159 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10160 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10161 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10162 (plus:SI (match_dup 1) (match_dup 2)))]
10163 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
10164 "@
10165 lfsux %3,%0,%2
10166 lfsu %3,%2(%0)"
10167 [(set_attr "type" "fpload")])
10169 (define_insn "*movsf_update2"
10170 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10171 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10172 (match_operand:SF 3 "gpc_reg_operand" "f,f"))
10173 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10174 (plus:SI (match_dup 1) (match_dup 2)))]
10175 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
10176 "@
10177 stfsux %3,%0,%2
10178 stfsu %3,%2(%0)"
10179 [(set_attr "type" "fpstore")])
10181 (define_insn "*movsf_update3"
10182 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r")
10183 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10184 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10185 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10186 (plus:SI (match_dup 1) (match_dup 2)))]
10187 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
10188 "@
10189 {lux|lwzux} %3,%0,%2
10190 {lu|lwzu} %3,%2(%0)"
10191 [(set_attr "type" "load")])
10193 (define_insn "*movsf_update4"
10194 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10195 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10196 (match_operand:SF 3 "gpc_reg_operand" "r,r"))
10197 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10198 (plus:SI (match_dup 1) (match_dup 2)))]
10199 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE"
10200 "@
10201 {stux|stwux} %3,%0,%2
10202 {stu|stwu} %3,%2(%0)"
10203 [(set_attr "type" "store")])
10205 (define_insn "*movdf_update1"
10206 [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
10207 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10208 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
10209 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10210 (plus:SI (match_dup 1) (match_dup 2)))]
10211 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
10212 "@
10213 lfdux %3,%0,%2
10214 lfdu %3,%2(%0)"
10215 [(set_attr "type" "fpload")])
10217 (define_insn "*movdf_update2"
10218 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
10219 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
10220 (match_operand:DF 3 "gpc_reg_operand" "f,f"))
10221 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
10222 (plus:SI (match_dup 1) (match_dup 2)))]
10223 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE"
10224 "@
10225 stfdux %3,%0,%2
10226 stfdu %3,%2(%0)"
10227 [(set_attr "type" "fpstore")])
10229 ;; Peephole to convert two consecutive FP loads or stores into lfq/stfq.
10231 (define_peephole
10232 [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
10233 (match_operand:DF 1 "memory_operand" ""))
10234 (set (match_operand:DF 2 "gpc_reg_operand" "=f")
10235 (match_operand:DF 3 "memory_operand" ""))]
10236 "TARGET_POWER2
10237 && TARGET_HARD_FLOAT && TARGET_FPRS
10238 && registers_ok_for_quad_peep (operands[0], operands[2])
10239 && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3])
10240 && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))"
10241 "lfq%U1%X1 %0,%1")
10243 (define_peephole
10244 [(set (match_operand:DF 0 "memory_operand" "")
10245 (match_operand:DF 1 "gpc_reg_operand" "f"))
10246 (set (match_operand:DF 2 "memory_operand" "")
10247 (match_operand:DF 3 "gpc_reg_operand" "f"))]
10248 "TARGET_POWER2
10249 && TARGET_HARD_FLOAT && TARGET_FPRS
10250 && registers_ok_for_quad_peep (operands[1], operands[3])
10251 && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2])
10252 && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))"
10253 "stfq%U0%X0 %1,%0")
10254 \f
10255 ;; Next come insns related to the calling sequence.
10256 ;;
10257 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
10258 ;; We move the back-chain and decrement the stack pointer.
10260 (define_expand "allocate_stack"
10261 [(set (match_operand 0 "gpc_reg_operand" "=r")
10262 (minus (reg 1) (match_operand 1 "reg_or_short_operand" "")))
10263 (set (reg 1)
10264 (minus (reg 1) (match_dup 1)))]
10265 ""
10266 "
10267 { rtx chain = gen_reg_rtx (Pmode);
10268 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx);
10269 rtx neg_op0;
10271 emit_move_insn (chain, stack_bot);
10273 /* Check stack bounds if necessary. */
10274 if (current_function_limit_stack)
10275 {
10276 rtx available;
10277 available = expand_binop (Pmode, sub_optab,
10278 stack_pointer_rtx, stack_limit_rtx,
10279 NULL_RTX, 1, OPTAB_WIDEN);
10280 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx));
10281 }
10283 if (GET_CODE (operands[1]) != CONST_INT
10284 || INTVAL (operands[1]) < -32767
10285 || INTVAL (operands[1]) > 32768)
10286 {
10287 neg_op0 = gen_reg_rtx (Pmode);
10288 if (TARGET_32BIT)
10289 emit_insn (gen_negsi2 (neg_op0, operands[1]));
10290 else
10291 emit_insn (gen_negdi2 (neg_op0, operands[1]));
10292 }
10293 else
10294 neg_op0 = GEN_INT (- INTVAL (operands[1]));
10296 if (TARGET_UPDATE)
10297 emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update : gen_movdi_update))
10298 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, chain));
10300 else
10301 {
10302 emit_insn ((* ((TARGET_32BIT) ? gen_addsi3 : gen_adddi3))
10303 (stack_pointer_rtx, stack_pointer_rtx, neg_op0));
10304 emit_move_insn (gen_rtx_MEM (Pmode, stack_pointer_rtx), chain);
10305 }
10307 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
10308 DONE;
10309 }")
10311 ;; These patterns say how to save and restore the stack pointer. We need not
10312 ;; save the stack pointer at function level since we are careful to
10313 ;; preserve the backchain. At block level, we have to restore the backchain
10314 ;; when we restore the stack pointer.
10315 ;;
10316 ;; For nonlocal gotos, we must save both the stack pointer and its
10317 ;; backchain and restore both. Note that in the nonlocal case, the
10318 ;; save area is a memory location.
10320 (define_expand "save_stack_function"
10321 [(match_operand 0 "any_operand" "")
10322 (match_operand 1 "any_operand" "")]
10323 ""
10324 "DONE;")
10326 (define_expand "restore_stack_function"
10327 [(match_operand 0 "any_operand" "")
10328 (match_operand 1 "any_operand" "")]
10329 ""
10330 "DONE;")
10332 (define_expand "restore_stack_block"
10333 [(use (match_operand 0 "register_operand" ""))
10334 (set (match_dup 2) (match_dup 3))
10335 (set (match_dup 0) (match_operand 1 "register_operand" ""))
10336 (set (match_dup 3) (match_dup 2))]
10337 ""
10338 "
10339 {
10340 operands[2] = gen_reg_rtx (Pmode);
10341 operands[3] = gen_rtx_MEM (Pmode, operands[0]);
10342 }")
10344 (define_expand "save_stack_nonlocal"
10345 [(match_operand 0 "memory_operand" "")
10346 (match_operand 1 "register_operand" "")]
10347 ""
10348 "
10349 {
10350 rtx temp = gen_reg_rtx (Pmode);
10352 /* Copy the backchain to the first word, sp to the second. */
10353 emit_move_insn (temp, gen_rtx_MEM (Pmode, operands[1]));
10354 emit_move_insn (operand_subword (operands[0], 0, 0,
10355 (TARGET_32BIT ? DImode : TImode)),
10356 temp);
10357 emit_move_insn (operand_subword (operands[0], 1, 0, (TARGET_32BIT ? DImode : TImode)),
10358 operands[1]);
10359 DONE;
10360 }")
10362 (define_expand "restore_stack_nonlocal"
10363 [(match_operand 0 "register_operand" "")
10364 (match_operand 1 "memory_operand" "")]
10365 ""
10366 "
10367 {
10368 rtx temp = gen_reg_rtx (Pmode);
10370 /* Restore the backchain from the first word, sp from the second. */
10371 emit_move_insn (temp,
10372 operand_subword (operands[1], 0, 0, (TARGET_32BIT ? DImode : TImode)));
10373 emit_move_insn (operands[0],
10374 operand_subword (operands[1], 1, 0,
10375 (TARGET_32BIT ? DImode : TImode)));
10376 emit_move_insn (gen_rtx_MEM (Pmode, operands[0]), temp);
10377 DONE;
10378 }")
10379 \f
10380 ;; TOC register handling.
10382 ;; Code to initialize the TOC register...
10384 (define_insn "load_toc_aix_si"
10385 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10386 (unspec:SI [(const_int 0)] 7))
10387 (use (reg:SI 2))])]
10388 "DEFAULT_ABI == ABI_AIX && TARGET_32BIT"
10389 "*
10390 {
10391 char buf[30];
10392 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10393 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10394 operands[2] = gen_rtx_REG (Pmode, 2);
10395 return \"{l|lwz} %0,%1(%2)\";
10396 }"
10397 [(set_attr "type" "load")])
10399 (define_insn "load_toc_aix_di"
10400 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
10401 (unspec:DI [(const_int 0)] 7))
10402 (use (reg:DI 2))])]
10403 "DEFAULT_ABI == ABI_AIX && TARGET_64BIT"
10404 "*
10405 {
10406 char buf[30];
10407 #ifdef TARGET_RELOCATABLE
10408 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\",
10409 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE);
10410 #else
10411 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1);
10412 #endif
10413 if (TARGET_ELF)
10414 strcat (buf, \"@toc\");
10415 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
10416 operands[2] = gen_rtx_REG (Pmode, 2);
10417 return \"ld %0,%1(%2)\";
10418 }"
10419 [(set_attr "type" "load")])
10421 (define_insn "load_toc_v4_pic_si"
10422 [(set (match_operand:SI 0 "register_operand" "=l")
10423 (unspec:SI [(const_int 0)] 7))]
10424 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT"
10425 "bl _GLOBAL_OFFSET_TABLE_@local-4"
10426 [(set_attr "type" "branch")
10427 (set_attr "length" "4")])
10429 (define_insn "load_toc_v4_PIC_1"
10430 [(set (match_operand:SI 0 "register_operand" "=l")
10431 (match_operand:SI 1 "immediate_operand" "s"))
10432 (unspec [(match_dup 1)] 7)]
10433 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10434 "bcl 20,31,%1\\n%1:"
10435 [(set_attr "type" "branch")
10436 (set_attr "length" "4")])
10438 (define_insn "load_toc_v4_PIC_1b"
10439 [(set (match_operand:SI 0 "register_operand" "=l")
10440 (match_operand:SI 1 "immediate_operand" "s"))
10441 (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] 6)]
10442 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10443 "bcl 20,31,%1\\n\\t.long %2-%1+4\\n%1:"
10444 [(set_attr "type" "branch")
10445 (set_attr "length" "8")])
10447 (define_insn "load_toc_v4_PIC_2"
10448 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10449 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b")
10450 (minus:SI (match_operand:SI 2 "immediate_operand" "s")
10451 (match_operand:SI 3 "immediate_operand" "s")))))]
10452 "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2"
10453 "{l|lwz} %0,%2-%3(%1)"
10454 [(set_attr "type" "load")])
10456 (define_insn "load_macho_picbase"
10457 [(set (match_operand:SI 0 "register_operand" "=l")
10458 (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")] 15))]
10459 "(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
10460 "bcl 20,31,%1\\n%1:"
10461 [(set_attr "type" "branch")
10462 (set_attr "length" "4")])
10464 (define_insn "macho_correct_pic"
10465 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
10466 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "=r")
10467 (unspec:SI [(match_operand:SI 2 "immediate_operand" "s")
10468 (match_operand:SI 3 "immediate_operand" "s")]
10469 16)))]
10470 "DEFAULT_ABI == ABI_DARWIN"
10471 "addis %0,%1,ha16(%2-%3)\n\taddi %1,%1,lo16(%2-%3)"
10472 [(set_attr "length" "8")])
10474 ;; If the TOC is shared over a translation unit, as happens with all
10475 ;; the kinds of PIC that we support, we need to restore the TOC
10476 ;; pointer only when jumping over units of translation.
10477 ;; On Darwin, we need to reload the picbase.
10479 (define_expand "builtin_setjmp_receiver"
10480 [(use (label_ref (match_operand 0 "" "")))]
10481 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1)
10482 || (TARGET_TOC && TARGET_MINIMAL_TOC)
10483 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)"
10484 "
10485 {
10486 #if TARGET_MACHO
10487 if (DEFAULT_ABI == ABI_DARWIN)
10488 {
10489 char *picbase = machopic_function_base_name ();
10490 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1));
10491 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
10492 rtx tmplabrtx;
10493 char tmplab[20];
10495 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\",
10496 CODE_LABEL_NUMBER (operands[0]));
10497 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (tmplab, -1));
10499 emit_insn (gen_load_macho_picbase (picreg, tmplabrtx));
10500 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx));
10501 }
10502 else
10503 #endif
10504 rs6000_emit_load_toc_table (FALSE);
10505 DONE;
10506 }")
10507 \f
10508 ;; A function pointer under AIX is a pointer to a data area whose first word
10509 ;; contains the actual address of the function, whose second word contains a
10510 ;; pointer to its TOC, and whose third word contains a value to place in the
10511 ;; static chain register (r11). Note that if we load the static chain, our
10512 ;; "trampoline" need not have any executable code.
10514 (define_expand "call_indirect_aix32"
10515 [(set (match_dup 2)
10516 (mem:SI (match_operand:SI 0 "gpc_reg_operand" "")))
10517 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10518 (reg:SI 2))
10519 (set (reg:SI 2)
10520 (mem:SI (plus:SI (match_dup 0)
10521 (const_int 4))))
10522 (set (reg:SI 11)
10523 (mem:SI (plus:SI (match_dup 0)
10524 (const_int 8))))
10525 (parallel [(call (mem:SI (match_dup 2))
10526 (match_operand 1 "" ""))
10527 (use (reg:SI 2))
10528 (use (reg:SI 11))
10529 (set (reg:SI 2)
10530 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10531 (clobber (scratch:SI))])]
10532 "TARGET_32BIT"
10533 "
10534 { operands[2] = gen_reg_rtx (SImode); }")
10536 (define_expand "call_indirect_aix64"
10537 [(set (match_dup 2)
10538 (mem:DI (match_operand:DI 0 "gpc_reg_operand" "")))
10539 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10540 (reg:DI 2))
10541 (set (reg:DI 2)
10542 (mem:DI (plus:DI (match_dup 0)
10543 (const_int 8))))
10544 (set (reg:DI 11)
10545 (mem:DI (plus:DI (match_dup 0)
10546 (const_int 16))))
10547 (parallel [(call (mem:SI (match_dup 2))
10548 (match_operand 1 "" ""))
10549 (use (reg:DI 2))
10550 (use (reg:DI 11))
10551 (set (reg:DI 2)
10552 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10553 (clobber (scratch:SI))])]
10554 "TARGET_64BIT"
10555 "
10556 { operands[2] = gen_reg_rtx (DImode); }")
10558 (define_expand "call_value_indirect_aix32"
10559 [(set (match_dup 3)
10560 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
10561 (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
10562 (reg:SI 2))
10563 (set (reg:SI 2)
10564 (mem:SI (plus:SI (match_dup 1)
10565 (const_int 4))))
10566 (set (reg:SI 11)
10567 (mem:SI (plus:SI (match_dup 1)
10568 (const_int 8))))
10569 (parallel [(set (match_operand 0 "" "")
10570 (call (mem:SI (match_dup 3))
10571 (match_operand 2 "" "")))
10572 (use (reg:SI 2))
10573 (use (reg:SI 11))
10574 (set (reg:SI 2)
10575 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10576 (clobber (scratch:SI))])]
10577 "TARGET_32BIT"
10578 "
10579 { operands[3] = gen_reg_rtx (SImode); }")
10581 (define_expand "call_value_indirect_aix64"
10582 [(set (match_dup 3)
10583 (mem:DI (match_operand:DI 1 "gpc_reg_operand" "")))
10584 (set (mem:DI (plus:DI (reg:DI 1) (const_int 40)))
10585 (reg:DI 2))
10586 (set (reg:DI 2)
10587 (mem:DI (plus:DI (match_dup 1)
10588 (const_int 8))))
10589 (set (reg:DI 11)
10590 (mem:DI (plus:DI (match_dup 1)
10591 (const_int 16))))
10592 (parallel [(set (match_operand 0 "" "")
10593 (call (mem:SI (match_dup 3))
10594 (match_operand 2 "" "")))
10595 (use (reg:DI 2))
10596 (use (reg:DI 11))
10597 (set (reg:DI 2)
10598 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10599 (clobber (scratch:SI))])]
10600 "TARGET_64BIT"
10601 "
10602 { operands[3] = gen_reg_rtx (DImode); }")
10604 ;; Now the definitions for the call and call_value insns
10605 (define_expand "call"
10606 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
10607 (match_operand 1 "" ""))
10608 (use (match_operand 2 "" ""))
10609 (clobber (scratch:SI))])]
10610 ""
10611 "
10612 {
10613 #if TARGET_MACHO
10614 if (flag_pic)
10615 operands[0] = machopic_indirect_call_target (operands[0]);
10616 #endif
10618 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
10619 abort ();
10621 operands[0] = XEXP (operands[0], 0);
10623 if (GET_CODE (operands[0]) != SYMBOL_REF
10624 || (INTVAL (operands[2]) & CALL_LONG) != 0)
10625 {
10626 if (INTVAL (operands[2]) & CALL_LONG)
10627 operands[0] = rs6000_longcall_ref (operands[0]);
10629 if (DEFAULT_ABI == ABI_V4
10630 || DEFAULT_ABI == ABI_AIX_NODESC
10631 || DEFAULT_ABI == ABI_DARWIN)
10632 operands[0] = force_reg (Pmode, operands[0]);
10634 else if (DEFAULT_ABI == ABI_AIX)
10635 {
10636 /* AIX function pointers are really pointers to a three word
10637 area. */
10638 emit_call_insn (TARGET_32BIT
10639 ? gen_call_indirect_aix32 (force_reg (SImode,
10640 operands[0]),
10641 operands[1])
10642 : gen_call_indirect_aix64 (force_reg (DImode,
10643 operands[0]),
10644 operands[1]));
10645 DONE;
10646 }
10647 else
10648 abort ();
10649 }
10650 }")
10652 (define_expand "call_value"
10653 [(parallel [(set (match_operand 0 "" "")
10654 (call (mem:SI (match_operand 1 "address_operand" ""))
10655 (match_operand 2 "" "")))
10656 (use (match_operand 3 "" ""))
10657 (clobber (scratch:SI))])]
10658 ""
10659 "
10660 {
10661 #if TARGET_MACHO
10662 if (flag_pic)
10663 operands[1] = machopic_indirect_call_target (operands[1]);
10664 #endif
10666 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
10667 abort ();
10669 operands[1] = XEXP (operands[1], 0);
10671 if (GET_CODE (operands[1]) != SYMBOL_REF
10672 || (INTVAL (operands[3]) & CALL_LONG) != 0)
10673 {
10674 if (INTVAL (operands[3]) & CALL_LONG)
10675 operands[1] = rs6000_longcall_ref (operands[1]);
10677 if (DEFAULT_ABI == ABI_V4
10678 || DEFAULT_ABI == ABI_AIX_NODESC
10679 || DEFAULT_ABI == ABI_DARWIN)
10680 operands[0] = force_reg (Pmode, operands[0]);
10682 else if (DEFAULT_ABI == ABI_AIX)
10683 {
10684 /* AIX function pointers are really pointers to a three word
10685 area. */
10686 emit_call_insn (TARGET_32BIT
10687 ? gen_call_value_indirect_aix32 (operands[0],
10688 force_reg (SImode,
10689 operands[1]),
10690 operands[2])
10691 : gen_call_value_indirect_aix64 (operands[0],
10692 force_reg (DImode,
10693 operands[1]),
10694 operands[2]));
10695 DONE;
10696 }
10697 else
10698 abort ();
10699 }
10700 }")
10702 ;; Call to function in current module. No TOC pointer reload needed.
10703 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10704 ;; either the function was not prototyped, or it was prototyped as a
10705 ;; variable argument function. It is > 0 if FP registers were passed
10706 ;; and < 0 if they were not.
10708 (define_insn "*call_local32"
10709 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
10710 (match_operand 1 "" "g,g"))
10711 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10712 (clobber (match_scratch:SI 3 "=l,l"))]
10713 "(INTVAL (operands[2]) & CALL_LONG) == 0"
10714 "*
10715 {
10716 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10717 output_asm_insn (\"crxor 6,6,6\", operands);
10719 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10720 output_asm_insn (\"creqv 6,6,6\", operands);
10722 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10723 }"
10724 [(set_attr "type" "branch")
10725 (set_attr "length" "4,8")])
10727 (define_insn "*call_local64"
10728 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
10729 (match_operand 1 "" "g,g"))
10730 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10731 (clobber (match_scratch:SI 3 "=l,l"))]
10732 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
10733 "*
10734 {
10735 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10736 output_asm_insn (\"crxor 6,6,6\", operands);
10738 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10739 output_asm_insn (\"creqv 6,6,6\", operands);
10741 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\";
10742 }"
10743 [(set_attr "type" "branch")
10744 (set_attr "length" "4,8")])
10746 (define_insn "*call_value_local32"
10747 [(set (match_operand 0 "" "")
10748 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
10749 (match_operand 2 "" "g,g")))
10750 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10751 (clobber (match_scratch:SI 4 "=l,l"))]
10752 "(INTVAL (operands[3]) & CALL_LONG) == 0"
10753 "*
10754 {
10755 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10756 output_asm_insn (\"crxor 6,6,6\", operands);
10758 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10759 output_asm_insn (\"creqv 6,6,6\", operands);
10761 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10762 }"
10763 [(set_attr "type" "branch")
10764 (set_attr "length" "4,8")])
10767 (define_insn "*call_value_local64"
10768 [(set (match_operand 0 "" "")
10769 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
10770 (match_operand 2 "" "g,g")))
10771 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10772 (clobber (match_scratch:SI 4 "=l,l"))]
10773 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
10774 "*
10775 {
10776 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10777 output_asm_insn (\"crxor 6,6,6\", operands);
10779 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10780 output_asm_insn (\"creqv 6,6,6\", operands);
10782 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\";
10783 }"
10784 [(set_attr "type" "branch")
10785 (set_attr "length" "4,8")])
10787 ;; Call to function which may be in another module. Restore the TOC
10788 ;; pointer (r2) after the call unless this is System V.
10789 ;; Operand2 is nonzero if we are using the V.4 calling sequence and
10790 ;; either the function was not prototyped, or it was prototyped as a
10791 ;; variable argument function. It is > 0 if FP registers were passed
10792 ;; and < 0 if they were not.
10794 (define_insn "*call_indirect_nonlocal_aix32"
10795 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl"))
10796 (match_operand 1 "" "g"))
10797 (use (reg:SI 2))
10798 (use (reg:SI 11))
10799 (set (reg:SI 2)
10800 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10801 (clobber (match_scratch:SI 2 "=l"))]
10802 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10803 "b%T0l\;{l|lwz} 2,20(1)"
10804 [(set_attr "type" "jmpreg")
10805 (set_attr "length" "8")])
10807 (define_insn "*call_nonlocal_aix32"
10808 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
10809 (match_operand 1 "" "g"))
10810 (use (match_operand:SI 2 "immediate_operand" "O"))
10811 (clobber (match_scratch:SI 3 "=l"))]
10812 "TARGET_32BIT
10813 && DEFAULT_ABI == ABI_AIX
10814 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10815 "bl %z0\;%."
10816 [(set_attr "type" "branch")
10817 (set_attr "length" "8")])
10819 (define_insn "*call_indirect_nonlocal_aix64"
10820 [(call (mem:SI (match_operand:DI 0 "register_operand" "cl"))
10821 (match_operand 1 "" "g"))
10822 (use (reg:DI 2))
10823 (use (reg:DI 11))
10824 (set (reg:DI 2)
10825 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10826 (clobber (match_scratch:SI 2 "=l"))]
10827 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10828 "b%T0l\;ld 2,40(1)"
10829 [(set_attr "type" "jmpreg")
10830 (set_attr "length" "8")])
10832 (define_insn "*call_nonlocal_aix64"
10833 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
10834 (match_operand 1 "" "g"))
10835 (use (match_operand:SI 2 "immediate_operand" "O"))
10836 (clobber (match_scratch:SI 3 "=l"))]
10837 "TARGET_64BIT
10838 && DEFAULT_ABI == ABI_AIX
10839 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10840 "bl %z0\;%."
10841 [(set_attr "type" "branch")
10842 (set_attr "length" "8")])
10844 (define_insn "*call_value_indirect_nonlocal_aix32"
10845 [(set (match_operand 0 "" "")
10846 (call (mem:SI (match_operand:SI 1 "register_operand" "cl"))
10847 (match_operand 2 "" "g")))
10848 (use (reg:SI 2))
10849 (use (reg:SI 11))
10850 (set (reg:SI 2)
10851 (mem:SI (plus:SI (reg:SI 1) (const_int 20))))
10852 (clobber (match_scratch:SI 3 "=l"))]
10853 "TARGET_32BIT && DEFAULT_ABI == ABI_AIX"
10854 "b%T1l\;{l|lwz} 2,20(1)"
10855 [(set_attr "type" "jmpreg")
10856 (set_attr "length" "8")])
10858 (define_insn "*call_value_nonlocal_aix32"
10859 [(set (match_operand 0 "" "")
10860 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
10861 (match_operand 2 "" "g")))
10862 (use (match_operand:SI 3 "immediate_operand" "O"))
10863 (clobber (match_scratch:SI 4 "=l"))]
10864 "TARGET_32BIT
10865 && DEFAULT_ABI == ABI_AIX
10866 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10867 "bl %z1\;%."
10868 [(set_attr "type" "branch")
10869 (set_attr "length" "8")])
10871 (define_insn "*call_value_indirect_nonlocal_aix64"
10872 [(set (match_operand 0 "" "")
10873 (call (mem:SI (match_operand:DI 1 "register_operand" "cl"))
10874 (match_operand 2 "" "g")))
10875 (use (reg:DI 2))
10876 (use (reg:DI 11))
10877 (set (reg:DI 2)
10878 (mem:DI (plus:DI (reg:DI 1) (const_int 40))))
10879 (clobber (match_scratch:SI 3 "=l"))]
10880 "TARGET_64BIT && DEFAULT_ABI == ABI_AIX"
10881 "b%T1l\;ld 2,40(1)"
10882 [(set_attr "type" "jmpreg")
10883 (set_attr "length" "8")])
10885 (define_insn "*call_value_nonlocal_aix64"
10886 [(set (match_operand 0 "" "")
10887 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
10888 (match_operand 2 "" "g")))
10889 (use (match_operand:SI 3 "immediate_operand" "O"))
10890 (clobber (match_scratch:SI 4 "=l"))]
10891 "TARGET_64BIT
10892 && DEFAULT_ABI == ABI_AIX
10893 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10894 "bl %z1\;%."
10895 [(set_attr "type" "branch")
10896 (set_attr "length" "8")])
10898 ;; A function pointer under System V is just a normal pointer
10899 ;; operands[0] is the function pointer
10900 ;; operands[1] is the stack size to clean up
10901 ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument
10902 ;; which indicates how to set cr1
10904 (define_insn "*call_indirect_nonlocal_sysv"
10905 [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl"))
10906 (match_operand 1 "" "g,g"))
10907 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10908 (clobber (match_scratch:SI 3 "=l,l"))]
10909 "DEFAULT_ABI == ABI_AIX_NODESC
10910 || DEFAULT_ABI == ABI_V4
10911 || DEFAULT_ABI == ABI_DARWIN"
10912 {
10913 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10914 output_asm_insn ("crxor 6,6,6", operands);
10916 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10917 output_asm_insn ("creqv 6,6,6", operands);
10919 return "b%T0l";
10920 }
10921 [(set_attr "type" "jmpreg,jmpreg")
10922 (set_attr "length" "4,8")])
10924 (define_insn "*call_nonlocal_sysv"
10925 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
10926 (match_operand 1 "" "g,g"))
10927 (use (match_operand:SI 2 "immediate_operand" "O,n"))
10928 (clobber (match_scratch:SI 3 "=l,l"))]
10929 "(DEFAULT_ABI == ABI_AIX_NODESC
10930 || DEFAULT_ABI == ABI_V4
10931 || DEFAULT_ABI == ABI_DARWIN)
10932 && (INTVAL (operands[2]) & CALL_LONG) == 0"
10933 {
10934 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
10935 output_asm_insn ("crxor 6,6,6", operands);
10937 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
10938 output_asm_insn ("creqv 6,6,6", operands);
10940 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0";
10941 }
10942 [(set_attr "type" "branch,branch")
10943 (set_attr "length" "4,8")])
10945 (define_insn "*call_value_indirect_nonlocal_sysv"
10946 [(set (match_operand 0 "" "")
10947 (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl"))
10948 (match_operand 2 "" "g,g")))
10949 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10950 (clobber (match_scratch:SI 4 "=l,l"))]
10951 "DEFAULT_ABI == ABI_AIX_NODESC
10952 || DEFAULT_ABI == ABI_V4
10953 || DEFAULT_ABI == ABI_DARWIN"
10954 {
10955 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10956 output_asm_insn ("crxor 6,6,6", operands);
10958 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10959 output_asm_insn ("creqv 6,6,6", operands);
10961 return "b%T1l";
10962 }
10963 [(set_attr "type" "jmpreg,jmpreg")
10964 (set_attr "length" "4,8")])
10966 (define_insn "*call_value_nonlocal_sysv"
10967 [(set (match_operand 0 "" "")
10968 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
10969 (match_operand 2 "" "g,g")))
10970 (use (match_operand:SI 3 "immediate_operand" "O,n"))
10971 (clobber (match_scratch:SI 4 "=l,l"))]
10972 "(DEFAULT_ABI == ABI_AIX_NODESC
10973 || DEFAULT_ABI == ABI_V4
10974 || DEFAULT_ABI == ABI_DARWIN)
10975 && (INTVAL (operands[3]) & CALL_LONG) == 0"
10976 {
10977 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
10978 output_asm_insn ("crxor 6,6,6", operands);
10980 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
10981 output_asm_insn ("creqv 6,6,6", operands);
10983 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1";
10984 }
10985 [(set_attr "type" "branch,branch")
10986 (set_attr "length" "4,8")])
10988 ;; Call subroutine returning any type.
10989 (define_expand "untyped_call"
10990 [(parallel [(call (match_operand 0 "" "")
10991 (const_int 0))
10992 (match_operand 1 "" "")
10993 (match_operand 2 "" "")])]
10994 ""
10995 "
10996 {
10997 int i;
10999 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx));
11001 for (i = 0; i < XVECLEN (operands[2], 0); i++)
11002 {
11003 rtx set = XVECEXP (operands[2], 0, i);
11004 emit_move_insn (SET_DEST (set), SET_SRC (set));
11005 }
11007 /* The optimizer does not know that the call sets the function value
11008 registers we stored in the result block. We avoid problems by
11009 claiming that all hard registers are used and clobbered at this
11010 point. */
11011 emit_insn (gen_blockage ());
11013 DONE;
11014 }")
11016 ;; sibling call patterns
11017 (define_expand "sibcall"
11018 [(parallel [(call (mem:SI (match_operand 0 "address_operand" ""))
11019 (match_operand 1 "" ""))
11020 (use (match_operand 2 "" ""))
11021 (use (scratch:SI))
11022 (return)])]
11023 ""
11024 "
11025 {
11026 #if TARGET_MACHO
11027 if (flag_pic)
11028 operands[0] = machopic_indirect_call_target (operands[0]);
11029 #endif
11031 if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
11032 abort ();
11034 operands[0] = XEXP (operands[0], 0);
11036 }")
11038 ;; this and similar patterns must be marked as using LR, otherwise
11039 ;; dataflow will try to delete the store into it. This is true
11040 ;; even when the actual reg to jump to is in CTR, when LR was
11041 ;; saved and restored around the PIC-setting BCL.
11042 (define_insn "*sibcall_local32"
11043 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s"))
11044 (match_operand 1 "" "g,g"))
11045 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11046 (use (match_scratch:SI 3 "=l,l"))
11047 (return)]
11048 "(INTVAL (operands[2]) & CALL_LONG) == 0"
11049 "*
11050 {
11051 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11052 output_asm_insn (\"crxor 6,6,6\", operands);
11054 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11055 output_asm_insn (\"creqv 6,6,6\", operands);
11057 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11058 }"
11059 [(set_attr "type" "branch")
11060 (set_attr "length" "4,8")])
11062 (define_insn "*sibcall_local64"
11063 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s"))
11064 (match_operand 1 "" "g,g"))
11065 (use (match_operand:SI 2 "immediate_operand" "O,n"))
11066 (use (match_scratch:SI 3 "=l,l"))
11067 (return)]
11068 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0"
11069 "*
11070 {
11071 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11072 output_asm_insn (\"crxor 6,6,6\", operands);
11074 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11075 output_asm_insn (\"creqv 6,6,6\", operands);
11077 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\";
11078 }"
11079 [(set_attr "type" "branch")
11080 (set_attr "length" "4,8")])
11082 (define_insn "*sibcall_value_local32"
11083 [(set (match_operand 0 "" "")
11084 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s"))
11085 (match_operand 2 "" "g,g")))
11086 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11087 (use (match_scratch:SI 4 "=l,l"))
11088 (return)]
11089 "(INTVAL (operands[3]) & CALL_LONG) == 0"
11090 "*
11091 {
11092 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11093 output_asm_insn (\"crxor 6,6,6\", operands);
11095 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11096 output_asm_insn (\"creqv 6,6,6\", operands);
11098 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11099 }"
11100 [(set_attr "type" "branch")
11101 (set_attr "length" "4,8")])
11104 (define_insn "*sibcall_value_local64"
11105 [(set (match_operand 0 "" "")
11106 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s"))
11107 (match_operand 2 "" "g,g")))
11108 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11109 (use (match_scratch:SI 4 "=l,l"))
11110 (return)]
11111 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0"
11112 "*
11113 {
11114 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS)
11115 output_asm_insn (\"crxor 6,6,6\", operands);
11117 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS)
11118 output_asm_insn (\"creqv 6,6,6\", operands);
11120 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\";
11121 }"
11122 [(set_attr "type" "branch")
11123 (set_attr "length" "4,8")])
11125 (define_insn "*sibcall_nonlocal_aix32"
11126 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s"))
11127 (match_operand 1 "" "g"))
11128 (use (match_operand:SI 2 "immediate_operand" "O"))
11129 (use (match_scratch:SI 3 "=l"))
11130 (return)]
11131 "TARGET_32BIT
11132 && DEFAULT_ABI == ABI_AIX
11133 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11134 "b %z0"
11135 [(set_attr "type" "branch")
11136 (set_attr "length" "4")])
11138 (define_insn "*sibcall_nonlocal_aix64"
11139 [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s"))
11140 (match_operand 1 "" "g"))
11141 (use (match_operand:SI 2 "immediate_operand" "O"))
11142 (use (match_scratch:SI 3 "=l"))
11143 (return)]
11144 "TARGET_64BIT
11145 && DEFAULT_ABI == ABI_AIX
11146 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11147 "b %z0"
11148 [(set_attr "type" "branch")
11149 (set_attr "length" "4")])
11151 (define_insn "*sibcall_value_nonlocal_aix32"
11152 [(set (match_operand 0 "" "")
11153 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s"))
11154 (match_operand 2 "" "g")))
11155 (use (match_operand:SI 3 "immediate_operand" "O"))
11156 (use (match_scratch:SI 4 "=l"))
11157 (return)]
11158 "TARGET_32BIT
11159 && DEFAULT_ABI == ABI_AIX
11160 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11161 "b %z1"
11162 [(set_attr "type" "branch")
11163 (set_attr "length" "4")])
11165 (define_insn "*sibcall_value_nonlocal_aix64"
11166 [(set (match_operand 0 "" "")
11167 (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s"))
11168 (match_operand 2 "" "g")))
11169 (use (match_operand:SI 3 "immediate_operand" "O"))
11170 (use (match_scratch:SI 4 "=l"))
11171 (return)]
11172 "TARGET_64BIT
11173 && DEFAULT_ABI == ABI_AIX
11174 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11175 "b %z1"
11176 [(set_attr "type" "branch")
11177 (set_attr "length" "4")])
11179 (define_insn "*sibcall_nonlocal_sysv"
11180 [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s"))
11181 (match_operand 1 "" ""))
11182 (use (match_operand 2 "immediate_operand" "O,n"))
11183 (use (match_scratch:SI 3 "=l,l"))
11184 (return)]
11185 "(DEFAULT_ABI == ABI_DARWIN
11186 || DEFAULT_ABI == ABI_V4
11187 || DEFAULT_ABI == ABI_AIX_NODESC)
11188 && (INTVAL (operands[2]) & CALL_LONG) == 0"
11189 "*
11190 {
11191 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11192 output_asm_insn (\"crxor 6,6,6\", operands);
11194 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11195 output_asm_insn (\"creqv 6,6,6\", operands);
11197 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\";
11198 }"
11199 [(set_attr "type" "branch,branch")
11200 (set_attr "length" "4,8")])
11202 (define_expand "sibcall_value"
11203 [(parallel [(set (match_operand 0 "register_operand" "")
11204 (call (mem:SI (match_operand 1 "address_operand" ""))
11205 (match_operand 2 "" "")))
11206 (use (match_operand 3 "" ""))
11207 (use (scratch:SI))
11208 (return)])]
11209 ""
11210 "
11211 {
11212 #if TARGET_MACHO
11213 if (flag_pic)
11214 operands[1] = machopic_indirect_call_target (operands[1]);
11215 #endif
11217 if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
11218 abort ();
11220 operands[1] = XEXP (operands[1], 0);
11222 }")
11224 (define_insn "*sibcall_value_nonlocal_sysv"
11225 [(set (match_operand 0 "" "")
11226 (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s"))
11227 (match_operand 2 "" "")))
11228 (use (match_operand:SI 3 "immediate_operand" "O,n"))
11229 (use (match_scratch:SI 4 "=l,l"))
11230 (return)]
11231 "(DEFAULT_ABI == ABI_DARWIN
11232 || DEFAULT_ABI == ABI_V4
11233 || DEFAULT_ABI == ABI_AIX_NODESC)
11234 && (INTVAL (operands[3]) & CALL_LONG) == 0"
11235 "*
11236 {
11237 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS)
11238 output_asm_insn (\"crxor 6,6,6\", operands);
11240 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS)
11241 output_asm_insn (\"creqv 6,6,6\", operands);
11243 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\";
11244 }"
11245 [(set_attr "type" "branch,branch")
11246 (set_attr "length" "4,8")])
11248 (define_expand "sibcall_epilogue"
11249 [(use (const_int 0))]
11250 "TARGET_SCHED_PROLOG"
11251 "
11252 {
11253 rs6000_emit_epilogue (TRUE);
11254 DONE;
11255 }")
11257 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
11258 ;; all of memory. This blocks insns from being moved across this point.
11260 (define_insn "blockage"
11261 [(unspec_volatile [(const_int 0)] 0)]
11262 ""
11263 "")
11264 \f
11265 ;; Compare insns are next. Note that the RS/6000 has two types of compares,
11266 ;; signed & unsigned, and one type of branch.
11267 ;;
11268 ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
11269 ;; insns, and branches. We store the operands of compares until we see
11270 ;; how it is used.
11271 (define_expand "cmpsi"
11272 [(set (cc0)
11273 (compare (match_operand:SI 0 "gpc_reg_operand" "")
11274 (match_operand:SI 1 "reg_or_short_operand" "")))]
11275 ""
11276 "
11277 {
11278 /* Take care of the possibility that operands[1] might be negative but
11279 this might be a logical operation. That insn doesn't exist. */
11280 if (GET_CODE (operands[1]) == CONST_INT
11281 && INTVAL (operands[1]) < 0)
11282 operands[1] = force_reg (SImode, operands[1]);
11284 rs6000_compare_op0 = operands[0];
11285 rs6000_compare_op1 = operands[1];
11286 rs6000_compare_fp_p = 0;
11287 DONE;
11288 }")
11290 (define_expand "cmpdi"
11291 [(set (cc0)
11292 (compare (match_operand:DI 0 "gpc_reg_operand" "")
11293 (match_operand:DI 1 "reg_or_short_operand" "")))]
11294 "TARGET_POWERPC64"
11295 "
11296 {
11297 /* Take care of the possibility that operands[1] might be negative but
11298 this might be a logical operation. That insn doesn't exist. */
11299 if (GET_CODE (operands[1]) == CONST_INT
11300 && INTVAL (operands[1]) < 0)
11301 operands[1] = force_reg (DImode, operands[1]);
11303 rs6000_compare_op0 = operands[0];
11304 rs6000_compare_op1 = operands[1];
11305 rs6000_compare_fp_p = 0;
11306 DONE;
11307 }")
11309 (define_expand "cmpsf"
11310 [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
11311 (match_operand:SF 1 "gpc_reg_operand" "")))]
11312 "TARGET_HARD_FLOAT"
11313 "
11314 {
11315 rs6000_compare_op0 = operands[0];
11316 rs6000_compare_op1 = operands[1];
11317 rs6000_compare_fp_p = 1;
11318 DONE;
11319 }")
11321 (define_expand "cmpdf"
11322 [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
11323 (match_operand:DF 1 "gpc_reg_operand" "")))]
11324 "TARGET_HARD_FLOAT && TARGET_FPRS"
11325 "
11326 {
11327 rs6000_compare_op0 = operands[0];
11328 rs6000_compare_op1 = operands[1];
11329 rs6000_compare_fp_p = 1;
11330 DONE;
11331 }")
11333 (define_expand "cmptf"
11334 [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "")
11335 (match_operand:TF 1 "gpc_reg_operand" "")))]
11336 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT
11337 && TARGET_FPRS && TARGET_LONG_DOUBLE_128"
11338 "
11339 {
11340 rs6000_compare_op0 = operands[0];
11341 rs6000_compare_op1 = operands[1];
11342 rs6000_compare_fp_p = 1;
11343 DONE;
11344 }")
11346 (define_expand "beq"
11347 [(use (match_operand 0 "" ""))]
11348 ""
11349 "{ rs6000_emit_cbranch (EQ, operands[0]); DONE; }")
11351 (define_expand "bne"
11352 [(use (match_operand 0 "" ""))]
11353 ""
11354 "{ rs6000_emit_cbranch (NE, operands[0]); DONE; }")
11356 (define_expand "bge"
11357 [(use (match_operand 0 "" ""))]
11358 ""
11359 "{ rs6000_emit_cbranch (GE, operands[0]); DONE; }")
11361 (define_expand "bgt"
11362 [(use (match_operand 0 "" ""))]
11363 ""
11364 "{ rs6000_emit_cbranch (GT, operands[0]); DONE; }")
11366 (define_expand "ble"
11367 [(use (match_operand 0 "" ""))]
11368 ""
11369 "{ rs6000_emit_cbranch (LE, operands[0]); DONE; }")
11371 (define_expand "blt"
11372 [(use (match_operand 0 "" ""))]
11373 ""
11374 "{ rs6000_emit_cbranch (LT, operands[0]); DONE; }")
11376 (define_expand "bgeu"
11377 [(use (match_operand 0 "" ""))]
11378 ""
11379 "{ rs6000_emit_cbranch (GEU, operands[0]); DONE; }")
11381 (define_expand "bgtu"
11382 [(use (match_operand 0 "" ""))]
11383 ""
11384 "{ rs6000_emit_cbranch (GTU, operands[0]); DONE; }")
11386 (define_expand "bleu"
11387 [(use (match_operand 0 "" ""))]
11388 ""
11389 "{ rs6000_emit_cbranch (LEU, operands[0]); DONE; }")
11391 (define_expand "bltu"
11392 [(use (match_operand 0 "" ""))]
11393 ""
11394 "{ rs6000_emit_cbranch (LTU, operands[0]); DONE; }")
11396 (define_expand "bunordered"
11397 [(use (match_operand 0 "" ""))]
11398 ""
11399 "{ rs6000_emit_cbranch (UNORDERED, operands[0]); DONE; }")
11401 (define_expand "bordered"
11402 [(use (match_operand 0 "" ""))]
11403 ""
11404 "{ rs6000_emit_cbranch (ORDERED, operands[0]); DONE; }")
11406 (define_expand "buneq"
11407 [(use (match_operand 0 "" ""))]
11408 ""
11409 "{ rs6000_emit_cbranch (UNEQ, operands[0]); DONE; }")
11411 (define_expand "bunge"
11412 [(use (match_operand 0 "" ""))]
11413 ""
11414 "{ rs6000_emit_cbranch (UNGE, operands[0]); DONE; }")
11416 (define_expand "bungt"
11417 [(use (match_operand 0 "" ""))]
11418 ""
11419 "{ rs6000_emit_cbranch (UNGT, operands[0]); DONE; }")
11421 (define_expand "bunle"
11422 [(use (match_operand 0 "" ""))]
11423 ""
11424 "{ rs6000_emit_cbranch (UNLE, operands[0]); DONE; }")
11426 (define_expand "bunlt"
11427 [(use (match_operand 0 "" ""))]
11428 ""
11429 "{ rs6000_emit_cbranch (UNLT, operands[0]); DONE; }")
11431 (define_expand "bltgt"
11432 [(use (match_operand 0 "" ""))]
11433 ""
11434 "{ rs6000_emit_cbranch (LTGT, operands[0]); DONE; }")
11436 ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
11437 ;; For SEQ, likewise, except that comparisons with zero should be done
11438 ;; with an scc insns. However, due to the order that combine see the
11439 ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
11440 ;; the cases we don't want to handle.
11441 (define_expand "seq"
11442 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11443 ""
11444 "{ rs6000_emit_sCOND (EQ, operands[0]); DONE; }")
11446 (define_expand "sne"
11447 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11448 ""
11449 "
11450 {
11451 if (! rs6000_compare_fp_p)
11452 FAIL;
11454 rs6000_emit_sCOND (NE, operands[0]);
11455 DONE;
11456 }")
11458 ;; A > 0 is best done using the portable sequence, so fail in that case.
11459 (define_expand "sgt"
11460 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11461 ""
11462 "
11463 {
11464 if (! rs6000_compare_fp_p
11465 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11466 FAIL;
11468 rs6000_emit_sCOND (GT, operands[0]);
11469 DONE;
11470 }")
11472 ;; A < 0 is best done in the portable way for A an integer.
11473 (define_expand "slt"
11474 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11475 ""
11476 "
11477 {
11478 if (! rs6000_compare_fp_p
11479 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11480 FAIL;
11482 rs6000_emit_sCOND (LT, operands[0]);
11483 DONE;
11484 }")
11486 ;; A >= 0 is best done the portable way for A an integer.
11487 (define_expand "sge"
11488 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11489 ""
11490 "
11491 {
11492 if (! rs6000_compare_fp_p
11493 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11494 FAIL;
11496 rs6000_emit_sCOND (GE, operands[0]);
11497 DONE;
11498 }")
11500 ;; A <= 0 is best done the portable way for A an integer.
11501 (define_expand "sle"
11502 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11503 ""
11504 "
11505 {
11506 if (! rs6000_compare_fp_p
11507 && (! TARGET_POWER || rs6000_compare_op1 == const0_rtx))
11508 FAIL;
11510 rs6000_emit_sCOND (LE, operands[0]);
11511 DONE;
11512 }")
11514 (define_expand "sgtu"
11515 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11516 ""
11517 "{ rs6000_emit_sCOND (GTU, operands[0]); DONE; }")
11519 (define_expand "sltu"
11520 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11521 ""
11522 "{ rs6000_emit_sCOND (LTU, operands[0]); DONE; }")
11524 (define_expand "sgeu"
11525 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11526 ""
11527 "{ rs6000_emit_sCOND (GEU, operands[0]); DONE; }")
11529 (define_expand "sleu"
11530 [(clobber (match_operand:SI 0 "gpc_reg_operand" ""))]
11531 ""
11532 "{ rs6000_emit_sCOND (LEU, operands[0]); DONE; }")
11533 \f
11534 ;; Here are the actual compare insns.
11535 (define_insn "*cmpsi_internal1"
11536 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11537 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11538 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
11539 ""
11540 "{cmp%I2|cmpw%I2} %0,%1,%2"
11541 [(set_attr "type" "compare")])
11543 (define_insn "*cmpdi_internal1"
11544 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
11545 (compare:CC (match_operand:DI 1 "gpc_reg_operand" "r")
11546 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
11547 "TARGET_POWERPC64"
11548 "cmpd%I2 %0,%1,%2"
11549 [(set_attr "type" "compare")])
11551 ;; If we are comparing a register for equality with a large constant,
11552 ;; we can do this with an XOR followed by a compare. But we need a scratch
11553 ;; register for the result of the XOR.
11555 (define_split
11556 [(set (match_operand:CC 0 "cc_reg_operand" "")
11557 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11558 (match_operand:SI 2 "non_short_cint_operand" "")))
11559 (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
11560 "find_single_use (operands[0], insn, 0)
11561 && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
11562 || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
11563 [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
11564 (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
11565 "
11566 {
11567 /* Get the constant we are comparing against, C, and see what it looks like
11568 sign-extended to 16 bits. Then see what constant could be XOR'ed
11569 with C to get the sign-extended value. */
11571 HOST_WIDE_INT c = INTVAL (operands[2]);
11572 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000;
11573 HOST_WIDE_INT xorv = c ^ sextc;
11575 operands[4] = GEN_INT (xorv);
11576 operands[5] = GEN_INT (sextc);
11577 }")
11579 (define_insn "*cmpsi_internal2"
11580 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11581 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11582 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))]
11583 ""
11584 "{cmpl%I2|cmplw%I2} %0,%1,%b2"
11585 [(set_attr "type" "compare")])
11587 (define_insn "*cmpdi_internal2"
11588 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
11589 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r")
11590 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))]
11591 ""
11592 "cmpld%I2 %0,%1,%b2"
11593 [(set_attr "type" "compare")])
11595 ;; The following two insns don't exist as single insns, but if we provide
11596 ;; them, we can swap an add and compare, which will enable us to overlap more
11597 ;; of the required delay between a compare and branch. We generate code for
11598 ;; them by splitting.
11600 (define_insn ""
11601 [(set (match_operand:CC 3 "cc_reg_operand" "=y")
11602 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
11603 (match_operand:SI 2 "short_cint_operand" "i")))
11604 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11605 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11606 ""
11607 "#"
11608 [(set_attr "length" "8")])
11610 (define_insn ""
11611 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
11612 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
11613 (match_operand:SI 2 "u_short_cint_operand" "i")))
11614 (set (match_operand:SI 0 "gpc_reg_operand" "=r")
11615 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
11616 ""
11617 "#"
11618 [(set_attr "length" "8")])
11620 (define_split
11621 [(set (match_operand:CC 3 "cc_reg_operand" "")
11622 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
11623 (match_operand:SI 2 "short_cint_operand" "")))
11624 (set (match_operand:SI 0 "gpc_reg_operand" "")
11625 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11626 ""
11627 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
11628 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11630 (define_split
11631 [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
11632 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
11633 (match_operand:SI 2 "u_short_cint_operand" "")))
11634 (set (match_operand:SI 0 "gpc_reg_operand" "")
11635 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
11636 ""
11637 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
11638 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
11640 (define_insn "*cmpsf_internal1"
11641 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11642 (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
11643 (match_operand:SF 2 "gpc_reg_operand" "f")))]
11644 "TARGET_HARD_FLOAT && TARGET_FPRS"
11645 "fcmpu %0,%1,%2"
11646 [(set_attr "type" "fpcompare")])
11648 (define_insn "*cmpdf_internal1"
11649 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11650 (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
11651 (match_operand:DF 2 "gpc_reg_operand" "f")))]
11652 "TARGET_HARD_FLOAT && TARGET_FPRS"
11653 "fcmpu %0,%1,%2"
11654 [(set_attr "type" "fpcompare")])
11656 ;; Only need to compare second words if first words equal
11657 (define_insn "*cmptf_internal1"
11658 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
11659 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f")
11660 (match_operand:TF 2 "gpc_reg_operand" "f")))]
11661 "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS
11662 && TARGET_LONG_DOUBLE_128"
11663 "fcmpu %0,%1,%2\;bne %0,$+4\;fcmpu %0,%L1,%L2"
11664 [(set_attr "type" "fpcompare")
11665 (set_attr "length" "12")])
11666 \f
11667 ;; Now we have the scc insns. We can do some combinations because of the
11668 ;; way the machine works.
11669 ;;
11670 ;; Note that this is probably faster if we can put an insn between the
11671 ;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most
11672 ;; cases the insns below which don't use an intermediate CR field will
11673 ;; be used instead.
11674 (define_insn ""
11675 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11676 (match_operator:SI 1 "scc_comparison_operator"
11677 [(match_operand 2 "cc_reg_operand" "y")
11678 (const_int 0)]))]
11679 ""
11680 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
11681 [(set_attr "type" "cr_logical")
11682 (set_attr "length" "12")])
11684 ;; Same as above, but get the OV/ORDERED bit.
11685 (define_insn "move_from_CR_ov_bit"
11686 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11687 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] 724))]
11688 "TARGET_ISEL"
11689 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1"
11690 [(set_attr "length" "12")])
11692 (define_insn ""
11693 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11694 (match_operator:DI 1 "scc_comparison_operator"
11695 [(match_operand 2 "cc_reg_operand" "y")
11696 (const_int 0)]))]
11697 "TARGET_POWERPC64"
11698 "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1"
11699 [(set_attr "type" "cr_logical")
11700 (set_attr "length" "12")])
11702 (define_insn ""
11703 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11704 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11705 [(match_operand 2 "cc_reg_operand" "y,y")
11706 (const_int 0)])
11707 (const_int 0)))
11708 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
11709 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11710 "! TARGET_POWERPC64"
11711 "@
11712 %D1mfcr %3\;{rlinm.|rlwinm.} %3,%3,%J1,1
11713 #"
11714 [(set_attr "type" "delayed_compare")
11715 (set_attr "length" "12,16")])
11717 (define_split
11718 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11719 (compare:CC (match_operator:SI 1 "scc_comparison_operator"
11720 [(match_operand 2 "cc_reg_operand" "")
11721 (const_int 0)])
11722 (const_int 0)))
11723 (set (match_operand:SI 3 "gpc_reg_operand" "")
11724 (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
11725 "! TARGET_POWERPC64 && reload_completed"
11726 [(set (match_dup 3)
11727 (match_op_dup 1 [(match_dup 2) (const_int 0)]))
11728 (set (match_dup 0)
11729 (compare:CC (match_dup 3)
11730 (const_int 0)))]
11731 "")
11733 (define_insn ""
11734 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11735 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11736 [(match_operand 2 "cc_reg_operand" "y")
11737 (const_int 0)])
11738 (match_operand:SI 3 "const_int_operand" "n")))]
11739 ""
11740 "*
11741 {
11742 int is_bit = ccr_bit (operands[1], 1);
11743 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11744 int count;
11746 if (is_bit >= put_bit)
11747 count = is_bit - put_bit;
11748 else
11749 count = 32 - (put_bit - is_bit);
11751 operands[4] = GEN_INT (count);
11752 operands[5] = GEN_INT (put_bit);
11754 return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\";
11755 }"
11756 [(set_attr "type" "cr_logical")
11757 (set_attr "length" "12")])
11759 (define_insn ""
11760 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
11761 (compare:CC
11762 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11763 [(match_operand 2 "cc_reg_operand" "y,y")
11764 (const_int 0)])
11765 (match_operand:SI 3 "const_int_operand" "n,n"))
11766 (const_int 0)))
11767 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r")
11768 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11769 (match_dup 3)))]
11770 ""
11771 "*
11772 {
11773 int is_bit = ccr_bit (operands[1], 1);
11774 int put_bit = 31 - (INTVAL (operands[3]) & 31);
11775 int count;
11777 /* Force split for non-cc0 compare. */
11778 if (which_alternative == 1)
11779 return \"#\";
11781 if (is_bit >= put_bit)
11782 count = is_bit - put_bit;
11783 else
11784 count = 32 - (put_bit - is_bit);
11786 operands[5] = GEN_INT (count);
11787 operands[6] = GEN_INT (put_bit);
11789 return \"%D1mfcr %4\;{rlinm.|rlwinm.} %4,%4,%5,%6,%6\";
11790 }"
11791 [(set_attr "type" "delayed_compare")
11792 (set_attr "length" "12,16")])
11794 (define_split
11795 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
11796 (compare:CC
11797 (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
11798 [(match_operand 2 "cc_reg_operand" "")
11799 (const_int 0)])
11800 (match_operand:SI 3 "const_int_operand" ""))
11801 (const_int 0)))
11802 (set (match_operand:SI 4 "gpc_reg_operand" "")
11803 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11804 (match_dup 3)))]
11805 "reload_completed"
11806 [(set (match_dup 4)
11807 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
11808 (match_dup 3)))
11809 (set (match_dup 0)
11810 (compare:CC (match_dup 4)
11811 (const_int 0)))]
11812 "")
11814 ;; There is a 3 cycle delay between consecutive mfcr instructions
11815 ;; so it is useful to combine 2 scc instructions to use only one mfcr.
11817 (define_peephole
11818 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
11819 (match_operator:SI 1 "scc_comparison_operator"
11820 [(match_operand 2 "cc_reg_operand" "y")
11821 (const_int 0)]))
11822 (set (match_operand:SI 3 "gpc_reg_operand" "=r")
11823 (match_operator:SI 4 "scc_comparison_operator"
11824 [(match_operand 5 "cc_reg_operand" "y")
11825 (const_int 0)]))]
11826 "REGNO (operands[2]) != REGNO (operands[5])"
11827 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11828 [(set_attr "type" "cr_logical")
11829 (set_attr "length" "20")])
11831 (define_peephole
11832 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
11833 (match_operator:DI 1 "scc_comparison_operator"
11834 [(match_operand 2 "cc_reg_operand" "y")
11835 (const_int 0)]))
11836 (set (match_operand:DI 3 "gpc_reg_operand" "=r")
11837 (match_operator:DI 4 "scc_comparison_operator"
11838 [(match_operand 5 "cc_reg_operand" "y")
11839 (const_int 0)]))]
11840 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])"
11841 "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1"
11842 [(set_attr "type" "cr_logical")
11843 (set_attr "length" "20")])
11845 ;; There are some scc insns that can be done directly, without a compare.
11846 ;; These are faster because they don't involve the communications between
11847 ;; the FXU and branch units. In fact, we will be replacing all of the
11848 ;; integer scc insns here or in the portable methods in emit_store_flag.
11849 ;;
11850 ;; Also support (neg (scc ..)) since that construct is used to replace
11851 ;; branches, (plus (scc ..) ..) since that construct is common and
11852 ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
11853 ;; cases where it is no more expensive than (neg (scc ..)).
11855 ;; Have reload force a constant into a register for the simple insns that
11856 ;; otherwise won't accept constants. We do this because it is faster than
11857 ;; the cmp/mfcr sequence we would otherwise generate.
11859 (define_insn ""
11860 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
11861 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11862 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I")))
11863 (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
11864 "! TARGET_POWERPC64"
11865 "@
11866 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11867 {sfi|subfic} %3,%1,0\;{ae|adde} %0,%3,%1
11868 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11869 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
11870 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
11871 [(set_attr "length" "12,8,12,12,12")])
11873 (define_insn ""
11874 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
11875 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r")
11876 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I")))
11877 (clobber (match_scratch:DI 3 "=r,&r,r,r,r"))]
11878 "TARGET_POWERPC64"
11879 "@
11880 xor %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0
11881 subfic %3,%1,0\;adde %0,%3,%1
11882 xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
11883 xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
11884 subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
11885 [(set_attr "length" "12,8,12,12,12")])
11887 (define_insn ""
11888 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11889 (compare:CC
11890 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11891 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
11892 (const_int 0)))
11893 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11894 (eq:SI (match_dup 1) (match_dup 2)))
11895 (clobber (match_scratch:SI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11896 "! TARGET_POWERPC64"
11897 "@
11898 xor %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11899 {sfi|subfic} %3,%1,0\;{ae.|adde.} %0,%3,%1
11900 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11901 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11902 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae.|adde.} %0,%3,%0
11903 #
11904 #
11905 #
11906 #
11907 #"
11908 [(set_attr "type" "compare")
11909 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11911 (define_split
11912 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11913 (compare:CC
11914 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
11915 (match_operand:SI 2 "reg_or_cint_operand" ""))
11916 (const_int 0)))
11917 (set (match_operand:SI 0 "gpc_reg_operand" "")
11918 (eq:SI (match_dup 1) (match_dup 2)))
11919 (clobber (match_scratch:SI 3 ""))]
11920 "! TARGET_POWERPC64 && reload_completed"
11921 [(parallel [(set (match_dup 0)
11922 (eq:SI (match_dup 1) (match_dup 2)))
11923 (clobber (match_dup 3))])
11924 (set (match_dup 4)
11925 (compare:CC (match_dup 0)
11926 (const_int 0)))]
11927 "")
11929 (define_insn ""
11930 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
11931 (compare:CC
11932 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
11933 (match_operand:DI 2 "reg_or_cint_operand" "r,O,K,J,I,r,O,K,J,I"))
11934 (const_int 0)))
11935 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r")
11936 (eq:DI (match_dup 1) (match_dup 2)))
11937 (clobber (match_scratch:DI 3 "=r,&r,r,r,r,r,&r,r,r,r"))]
11938 "TARGET_POWERPC64"
11939 "@
11940 xor %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11941 subfic %3,%1,0\;adde. %0,%3,%1
11942 xori %0,%1,%b2\;subfic %3,%0,0\;adde. %0,%3,%0
11943 xoris %0,%1,%u2\;subfic %3,%0,0\;adde. %0,%3,%0
11944 subfic %0,%1,%2\;subfic %3,%0,0\;adde. %0,%3,%0
11945 #
11946 #
11947 #
11948 #
11949 #"
11950 [(set_attr "type" "compare")
11951 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
11953 (define_split
11954 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
11955 (compare:CC
11956 (eq:DI (match_operand:DI 1 "gpc_reg_operand" "")
11957 (match_operand:DI 2 "reg_or_cint_operand" ""))
11958 (const_int 0)))
11959 (set (match_operand:DI 0 "gpc_reg_operand" "")
11960 (eq:DI (match_dup 1) (match_dup 2)))
11961 (clobber (match_scratch:DI 3 ""))]
11962 "TARGET_POWERPC64 && reload_completed"
11963 [(parallel [(set (match_dup 0)
11964 (eq:DI (match_dup 1) (match_dup 2)))
11965 (clobber (match_dup 3))])
11966 (set (match_dup 4)
11967 (compare:CC (match_dup 0)
11968 (const_int 0)))]
11969 "")
11971 ;; We have insns of the form shown by the first define_insn below. If
11972 ;; there is something inside the comparison operation, we must split it.
11973 (define_split
11974 [(set (match_operand:SI 0 "gpc_reg_operand" "")
11975 (plus:SI (match_operator 1 "comparison_operator"
11976 [(match_operand:SI 2 "" "")
11977 (match_operand:SI 3
11978 "reg_or_cint_operand" "")])
11979 (match_operand:SI 4 "gpc_reg_operand" "")))
11980 (clobber (match_operand:SI 5 "register_operand" ""))]
11981 "! gpc_reg_operand (operands[2], SImode)"
11982 [(set (match_dup 5) (match_dup 2))
11983 (set (match_dup 2) (plus:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)])
11984 (match_dup 4)))])
11986 (define_insn ""
11987 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
11988 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
11989 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))
11990 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
11991 "! TARGET_POWERPC64"
11992 "@
11993 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11994 {sfi|subfic} %0,%1,0\;{aze|addze} %0,%3
11995 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11996 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
11997 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
11998 [(set_attr "length" "12,8,12,12,12")])
12000 (define_insn ""
12001 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12002 (compare:CC
12003 (plus:SI
12004 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12005 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
12006 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12007 (const_int 0)))
12008 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
12009 "! TARGET_POWERPC64"
12010 "@
12011 xor %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12012 {sfi|subfic} %4,%1,0\;{aze.|addze.} %4,%3
12013 {xoril|xori} %4,%1,%b2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12014 {xoriu|xoris} %4,%1,%u2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12015 {sfi|subfic} %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12016 #
12017 #
12018 #
12019 #
12020 #"
12021 [(set_attr "type" "compare")
12022 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12024 (define_split
12025 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12026 (compare:CC
12027 (plus:SI
12028 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12029 (match_operand:SI 2 "reg_or_cint_operand" ""))
12030 (match_operand:SI 3 "gpc_reg_operand" ""))
12031 (const_int 0)))
12032 (clobber (match_scratch:SI 4 ""))]
12033 "! TARGET_POWERPC64 && reload_completed"
12034 [(set (match_dup 4)
12035 (plus:SI (eq:SI (match_dup 1)
12036 (match_dup 2))
12037 (match_dup 3)))
12038 (set (match_dup 0)
12039 (compare:CC (match_dup 4)
12040 (const_int 0)))]
12041 "")
12043 (define_insn ""
12044 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
12045 (compare:CC
12046 (plus:SI
12047 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
12048 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I,r,O,K,L,I"))
12049 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
12050 (const_int 0)))
12051 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
12052 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12053 "! TARGET_POWERPC64"
12054 "@
12055 xor %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12056 {sfi|subfic} %0,%1,0\;{aze.|addze.} %0,%3
12057 {xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12058 {xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12059 {sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12060 #
12061 #
12062 #
12063 #
12064 #"
12065 [(set_attr "type" "compare")
12066 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")])
12068 (define_split
12069 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12070 (compare:CC
12071 (plus:SI
12072 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
12073 (match_operand:SI 2 "reg_or_cint_operand" ""))
12074 (match_operand:SI 3 "gpc_reg_operand" ""))
12075 (const_int 0)))
12076 (set (match_operand:SI 0 "gpc_reg_operand" "")
12077 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12078 "! TARGET_POWERPC64 && reload_completed"
12079 [(set (match_dup 0)
12080 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12081 (set (match_dup 4)
12082 (compare:CC (match_dup 0)
12083 (const_int 0)))]
12084 "")
12086 (define_insn ""
12087 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
12088 (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
12089 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,L,I"))))]
12090 "! TARGET_POWERPC64"
12091 "@
12092 xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12093 {ai|addic} %0,%1,-1\;{sfe|subfe} %0,%0,%0
12094 {xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12095 {xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12096 {sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
12097 [(set_attr "length" "12,8,12,12,12")])
12099 ;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
12100 ;; since it nabs/sr is just as fast.
12101 (define_insn "*ne0"
12102 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12103 (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12104 (const_int 31)))
12105 (clobber (match_scratch:SI 2 "=&r"))]
12106 "! TARGET_POWER && ! TARGET_POWERPC64 && !TARGET_ISEL"
12107 "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
12108 [(set_attr "length" "8")])
12110 (define_insn ""
12111 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12112 (lshiftrt:DI (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12113 (const_int 63)))
12114 (clobber (match_scratch:DI 2 "=&r"))]
12115 "TARGET_POWERPC64"
12116 "addic %2,%1,-1\;subfe %0,%2,%1"
12117 [(set_attr "length" "8")])
12119 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
12120 (define_insn ""
12121 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12122 (plus:SI (lshiftrt:SI
12123 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
12124 (const_int 31))
12125 (match_operand:SI 2 "gpc_reg_operand" "r")))
12126 (clobber (match_scratch:SI 3 "=&r"))]
12127 "! TARGET_POWERPC64"
12128 "{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
12129 [(set_attr "length" "8")])
12131 (define_insn ""
12132 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12133 (plus:DI (lshiftrt:DI
12134 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r")))
12135 (const_int 63))
12136 (match_operand:DI 2 "gpc_reg_operand" "r")))
12137 (clobber (match_scratch:DI 3 "=&r"))]
12138 "TARGET_POWERPC64"
12139 "addic %3,%1,-1\;addze %0,%2"
12140 [(set_attr "length" "8")])
12142 (define_insn ""
12143 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12144 (compare:CC
12145 (plus:SI (lshiftrt:SI
12146 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12147 (const_int 31))
12148 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12149 (const_int 0)))
12150 (clobber (match_scratch:SI 3 "=&r,&r"))
12151 (clobber (match_scratch:SI 4 "=X,&r"))]
12152 "! TARGET_POWERPC64"
12153 "@
12154 {ai|addic} %3,%1,-1\;{aze.|addze.} %3,%2
12155 #"
12156 [(set_attr "type" "compare")
12157 (set_attr "length" "8,12")])
12159 (define_split
12160 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12161 (compare:CC
12162 (plus:SI (lshiftrt:SI
12163 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12164 (const_int 31))
12165 (match_operand:SI 2 "gpc_reg_operand" ""))
12166 (const_int 0)))
12167 (clobber (match_scratch:SI 3 ""))
12168 (clobber (match_scratch:SI 4 ""))]
12169 "! TARGET_POWERPC64 && reload_completed"
12170 [(parallel [(set (match_dup 3)
12171 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1)))
12172 (const_int 31))
12173 (match_dup 2)))
12174 (clobber (match_dup 4))])
12175 (set (match_dup 0)
12176 (compare:CC (match_dup 3)
12177 (const_int 0)))]
12178 "")
12180 (define_insn ""
12181 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12182 (compare:CC
12183 (plus:DI (lshiftrt:DI
12184 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12185 (const_int 63))
12186 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12187 (const_int 0)))
12188 (clobber (match_scratch:DI 3 "=&r,&r"))]
12189 "TARGET_POWERPC64"
12190 "@
12191 addic %3,%1,-1\;addze. %3,%2
12192 #"
12193 [(set_attr "type" "compare")
12194 (set_attr "length" "8,12")])
12196 (define_split
12197 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12198 (compare:CC
12199 (plus:DI (lshiftrt:DI
12200 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12201 (const_int 63))
12202 (match_operand:DI 2 "gpc_reg_operand" ""))
12203 (const_int 0)))
12204 (clobber (match_scratch:DI 3 ""))]
12205 "TARGET_POWERPC64 && reload_completed"
12206 [(set (match_dup 3)
12207 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1)))
12208 (const_int 63))
12209 (match_dup 2)))
12210 (set (match_dup 0)
12211 (compare:CC (match_dup 3)
12212 (const_int 0)))]
12213 "")
12215 (define_insn ""
12216 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12217 (compare:CC
12218 (plus:SI (lshiftrt:SI
12219 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")))
12220 (const_int 31))
12221 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
12222 (const_int 0)))
12223 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12224 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12225 (match_dup 2)))
12226 (clobber (match_scratch:SI 3 "=&r,&r"))]
12227 "! TARGET_POWERPC64"
12228 "@
12229 {ai|addic} %3,%1,-1\;{aze.|addze.} %0,%2
12230 #"
12231 [(set_attr "type" "compare")
12232 (set_attr "length" "8,12")])
12234 (define_split
12235 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12236 (compare:CC
12237 (plus:SI (lshiftrt:SI
12238 (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))
12239 (const_int 31))
12240 (match_operand:SI 2 "gpc_reg_operand" ""))
12241 (const_int 0)))
12242 (set (match_operand:SI 0 "gpc_reg_operand" "")
12243 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12244 (match_dup 2)))
12245 (clobber (match_scratch:SI 3 ""))]
12246 "! TARGET_POWERPC64 && reload_completed"
12247 [(parallel [(set (match_dup 0)
12248 (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
12249 (match_dup 2)))
12250 (clobber (match_dup 3))])
12251 (set (match_dup 4)
12252 (compare:CC (match_dup 0)
12253 (const_int 0)))]
12254 "")
12256 (define_insn ""
12257 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12258 (compare:CC
12259 (plus:DI (lshiftrt:DI
12260 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")))
12261 (const_int 63))
12262 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
12263 (const_int 0)))
12264 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12265 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12266 (match_dup 2)))
12267 (clobber (match_scratch:DI 3 "=&r,&r"))]
12268 "TARGET_POWERPC64"
12269 "@
12270 addic %3,%1,-1\;addze. %0,%2
12271 #"
12272 [(set_attr "type" "compare")
12273 (set_attr "length" "8,12")])
12275 (define_split
12276 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12277 (compare:CC
12278 (plus:DI (lshiftrt:DI
12279 (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))
12280 (const_int 63))
12281 (match_operand:DI 2 "gpc_reg_operand" ""))
12282 (const_int 0)))
12283 (set (match_operand:DI 0 "gpc_reg_operand" "")
12284 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12285 (match_dup 2)))
12286 (clobber (match_scratch:DI 3 ""))]
12287 "TARGET_POWERPC64 && reload_completed"
12288 [(parallel [(set (match_dup 0)
12289 (plus:DI (lshiftrt:DI (neg:DI (abs:DI (match_dup 1))) (const_int 63))
12290 (match_dup 2)))
12291 (clobber (match_dup 3))])
12292 (set (match_dup 4)
12293 (compare:CC (match_dup 0)
12294 (const_int 0)))]
12295 "")
12297 (define_insn ""
12298 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12299 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12300 (match_operand:SI 2 "reg_or_short_operand" "r,O")))
12301 (clobber (match_scratch:SI 3 "=r,X"))]
12302 "TARGET_POWER"
12303 "@
12304 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3
12305 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri|srwi} %0,%0,31"
12306 [(set_attr "length" "12")])
12308 (define_insn ""
12309 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12310 (compare:CC
12311 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12312 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12313 (const_int 0)))
12314 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12315 (le:SI (match_dup 1) (match_dup 2)))
12316 (clobber (match_scratch:SI 3 "=r,X,r,X"))]
12317 "TARGET_POWER"
12318 "@
12319 doz %3,%2,%1\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12320 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{sri.|srwi.} %0,%0,31
12321 #
12322 #"
12323 [(set_attr "type" "compare,delayed_compare,compare,delayed_compare")
12324 (set_attr "length" "12,12,16,16")])
12326 (define_split
12327 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12328 (compare:CC
12329 (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12330 (match_operand:SI 2 "reg_or_short_operand" ""))
12331 (const_int 0)))
12332 (set (match_operand:SI 0 "gpc_reg_operand" "")
12333 (le:SI (match_dup 1) (match_dup 2)))
12334 (clobber (match_scratch:SI 3 ""))]
12335 "TARGET_POWER && reload_completed"
12336 [(parallel [(set (match_dup 0)
12337 (le:SI (match_dup 1) (match_dup 2)))
12338 (clobber (match_dup 3))])
12339 (set (match_dup 4)
12340 (compare:CC (match_dup 0)
12341 (const_int 0)))]
12342 "")
12344 (define_insn ""
12345 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12346 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12347 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
12348 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
12349 "TARGET_POWER"
12350 "@
12351 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
12352 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze|addze} %0,%3"
12353 [(set_attr "length" "12")])
12355 (define_insn ""
12356 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12357 (compare:CC
12358 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12359 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12360 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12361 (const_int 0)))
12362 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12363 "TARGET_POWER"
12364 "@
12365 doz %4,%2,%1\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
12366 {srai|srawi} %4,%1,31\;{sf|subfc} %4,%1,%4\;{aze.|addze.} %4,%3
12367 #
12368 #"
12369 [(set_attr "type" "compare")
12370 (set_attr "length" "12,12,16,16")])
12372 (define_split
12373 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12374 (compare:CC
12375 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12376 (match_operand:SI 2 "reg_or_short_operand" ""))
12377 (match_operand:SI 3 "gpc_reg_operand" ""))
12378 (const_int 0)))
12379 (clobber (match_scratch:SI 4 ""))]
12380 "TARGET_POWER && reload_completed"
12381 [(set (match_dup 4)
12382 (plus:SI (le:SI (match_dup 1) (match_dup 2))
12383 (match_dup 3)))
12384 (set (match_dup 0)
12385 (compare:CC (match_dup 4)
12386 (const_int 0)))]
12387 "")
12389 (define_insn ""
12390 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12391 (compare:CC
12392 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12393 (match_operand:SI 2 "reg_or_short_operand" "r,O,r,O"))
12394 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12395 (const_int 0)))
12396 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12397 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12398 "TARGET_POWER"
12399 "@
12400 doz %0,%2,%1\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
12401 {srai|srawi} %0,%1,31\;{sf|subfc} %0,%1,%0\;{aze.|addze.} %0,%3
12402 #
12403 #"
12404 [(set_attr "type" "compare")
12405 (set_attr "length" "12,12,16,16")])
12407 (define_split
12408 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12409 (compare:CC
12410 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "")
12411 (match_operand:SI 2 "reg_or_short_operand" ""))
12412 (match_operand:SI 3 "gpc_reg_operand" ""))
12413 (const_int 0)))
12414 (set (match_operand:SI 0 "gpc_reg_operand" "")
12415 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12416 "TARGET_POWER && reload_completed"
12417 [(set (match_dup 0)
12418 (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12419 (set (match_dup 4)
12420 (compare:CC (match_dup 0)
12421 (const_int 0)))]
12422 "")
12424 (define_insn ""
12425 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12426 (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12427 (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
12428 "TARGET_POWER"
12429 "@
12430 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
12431 {ai|addic} %0,%1,-1\;{aze|addze} %0,%0\;{srai|srawi} %0,%0,31"
12432 [(set_attr "length" "12")])
12434 (define_insn ""
12435 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12436 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12437 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12438 "! TARGET_POWERPC64"
12439 "{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
12440 [(set_attr "length" "12")])
12442 (define_insn ""
12443 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
12444 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
12445 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
12446 "TARGET_POWERPC64"
12447 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
12448 [(set_attr "length" "12")])
12450 (define_insn ""
12451 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12452 (compare:CC
12453 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12454 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
12455 (const_int 0)))
12456 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12457 (leu:DI (match_dup 1) (match_dup 2)))]
12458 "TARGET_POWERPC64"
12459 "@
12460 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12461 #"
12462 [(set_attr "type" "compare")
12463 (set_attr "length" "12,16")])
12465 (define_split
12466 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12467 (compare:CC
12468 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "")
12469 (match_operand:DI 2 "reg_or_short_operand" ""))
12470 (const_int 0)))
12471 (set (match_operand:DI 0 "gpc_reg_operand" "")
12472 (leu:DI (match_dup 1) (match_dup 2)))]
12473 "TARGET_POWERPC64 && reload_completed"
12474 [(set (match_dup 0)
12475 (leu:DI (match_dup 1) (match_dup 2)))
12476 (set (match_dup 3)
12477 (compare:CC (match_dup 0)
12478 (const_int 0)))]
12479 "")
12481 (define_insn ""
12482 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12483 (compare:CC
12484 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12485 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12486 (const_int 0)))
12487 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12488 (leu:SI (match_dup 1) (match_dup 2)))]
12489 "! TARGET_POWERPC64"
12490 "@
12491 {sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
12492 #"
12493 [(set_attr "type" "compare")
12494 (set_attr "length" "12,16")])
12496 (define_split
12497 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12498 (compare:CC
12499 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12500 (match_operand:SI 2 "reg_or_short_operand" ""))
12501 (const_int 0)))
12502 (set (match_operand:SI 0 "gpc_reg_operand" "")
12503 (leu:SI (match_dup 1) (match_dup 2)))]
12504 "! TARGET_POWERPC64 && reload_completed"
12505 [(set (match_dup 0)
12506 (leu:SI (match_dup 1) (match_dup 2)))
12507 (set (match_dup 3)
12508 (compare:CC (match_dup 0)
12509 (const_int 0)))]
12510 "")
12512 (define_insn ""
12513 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12514 (compare:CC
12515 (leu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
12516 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
12517 (const_int 0)))
12518 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
12519 (leu:DI (match_dup 1) (match_dup 2)))]
12520 "TARGET_POWERPC64"
12521 "@
12522 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0
12523 #"
12524 [(set_attr "type" "compare")
12525 (set_attr "length" "12,16")])
12527 (define_insn ""
12528 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12529 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12530 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12531 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12532 "! TARGET_POWERPC64"
12533 "{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
12534 [(set_attr "length" "8")])
12536 (define_insn ""
12537 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12538 (compare:CC
12539 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12540 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12541 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12542 (const_int 0)))
12543 (clobber (match_scratch:SI 4 "=&r,&r"))]
12544 "! TARGET_POWERPC64"
12545 "@
12546 {sf%I2|subf%I2c} %4,%1,%2\;{aze.|addze.} %4,%3
12547 #"
12548 [(set_attr "type" "compare")
12549 (set_attr "length" "8,12")])
12551 (define_split
12552 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12553 (compare:CC
12554 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12555 (match_operand:SI 2 "reg_or_short_operand" ""))
12556 (match_operand:SI 3 "gpc_reg_operand" ""))
12557 (const_int 0)))
12558 (clobber (match_scratch:SI 4 ""))]
12559 "! TARGET_POWERPC64 && reload_completed"
12560 [(set (match_dup 4)
12561 (plus:SI (leu:SI (match_dup 1) (match_dup 2))
12562 (match_dup 3)))
12563 (set (match_dup 0)
12564 (compare:CC (match_dup 4)
12565 (const_int 0)))]
12566 "")
12568 (define_insn ""
12569 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12570 (compare:CC
12571 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12572 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12573 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12574 (const_int 0)))
12575 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12576 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12577 "! TARGET_POWERPC64"
12578 "@
12579 {sf%I2|subf%I2c} %0,%1,%2\;{aze.|addze.} %0,%3
12580 #"
12581 [(set_attr "type" "compare")
12582 (set_attr "length" "8,12")])
12584 (define_split
12585 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12586 (compare:CC
12587 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12588 (match_operand:SI 2 "reg_or_short_operand" ""))
12589 (match_operand:SI 3 "gpc_reg_operand" ""))
12590 (const_int 0)))
12591 (set (match_operand:SI 0 "gpc_reg_operand" "")
12592 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12593 "! TARGET_POWERPC64 && reload_completed"
12594 [(set (match_dup 0)
12595 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12596 (set (match_dup 4)
12597 (compare:CC (match_dup 0)
12598 (const_int 0)))]
12599 "")
12601 (define_insn ""
12602 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12603 (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12604 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12605 "! TARGET_POWERPC64"
12606 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
12607 [(set_attr "length" "12")])
12609 (define_insn ""
12610 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12611 (and:SI (neg:SI
12612 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12613 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12614 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12615 "! TARGET_POWERPC64"
12616 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
12617 [(set_attr "length" "12")])
12619 (define_insn ""
12620 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12621 (compare:CC
12622 (and:SI (neg:SI
12623 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12624 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12625 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12626 (const_int 0)))
12627 (clobber (match_scratch:SI 4 "=&r,&r"))]
12628 "! TARGET_POWERPC64"
12629 "@
12630 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
12631 #"
12632 [(set_attr "type" "compare")
12633 (set_attr "length" "12,16")])
12635 (define_split
12636 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12637 (compare:CC
12638 (and:SI (neg:SI
12639 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12640 (match_operand:SI 2 "reg_or_short_operand" "")))
12641 (match_operand:SI 3 "gpc_reg_operand" ""))
12642 (const_int 0)))
12643 (clobber (match_scratch:SI 4 ""))]
12644 "! TARGET_POWERPC64 && reload_completed"
12645 [(set (match_dup 4)
12646 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12647 (match_dup 3)))
12648 (set (match_dup 0)
12649 (compare:CC (match_dup 4)
12650 (const_int 0)))]
12651 "")
12653 (define_insn ""
12654 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12655 (compare:CC
12656 (and:SI (neg:SI
12657 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12658 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")))
12659 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12660 (const_int 0)))
12661 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12662 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12663 "! TARGET_POWERPC64"
12664 "@
12665 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
12666 #"
12667 [(set_attr "type" "compare")
12668 (set_attr "length" "12,16")])
12670 (define_split
12671 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12672 (compare:CC
12673 (and:SI (neg:SI
12674 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12675 (match_operand:SI 2 "reg_or_short_operand" "")))
12676 (match_operand:SI 3 "gpc_reg_operand" ""))
12677 (const_int 0)))
12678 (set (match_operand:SI 0 "gpc_reg_operand" "")
12679 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
12680 "! TARGET_POWERPC64 && reload_completed"
12681 [(set (match_dup 0)
12682 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2)))
12683 (match_dup 3)))
12684 (set (match_dup 4)
12685 (compare:CC (match_dup 0)
12686 (const_int 0)))]
12687 "")
12689 (define_insn ""
12690 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12691 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12692 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
12693 "TARGET_POWER"
12694 "doz%I2 %0,%1,%2\;nabs %0,%0\;{sri|srwi} %0,%0,31"
12695 [(set_attr "length" "12")])
12697 (define_insn ""
12698 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
12699 (compare:CC
12700 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12701 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12702 (const_int 0)))
12703 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12704 (lt:SI (match_dup 1) (match_dup 2)))]
12705 "TARGET_POWER"
12706 "@
12707 doz%I2 %0,%1,%2\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
12708 #"
12709 [(set_attr "type" "delayed_compare")
12710 (set_attr "length" "12,16")])
12712 (define_split
12713 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12714 (compare:CC
12715 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12716 (match_operand:SI 2 "reg_or_short_operand" ""))
12717 (const_int 0)))
12718 (set (match_operand:SI 0 "gpc_reg_operand" "")
12719 (lt:SI (match_dup 1) (match_dup 2)))]
12720 "TARGET_POWER && reload_completed"
12721 [(set (match_dup 0)
12722 (lt:SI (match_dup 1) (match_dup 2)))
12723 (set (match_dup 3)
12724 (compare:CC (match_dup 0)
12725 (const_int 0)))]
12726 "")
12728 (define_insn ""
12729 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12730 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12731 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12732 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12733 "TARGET_POWER"
12734 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
12735 [(set_attr "length" "12")])
12737 (define_insn ""
12738 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12739 (compare:CC
12740 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12741 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12742 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12743 (const_int 0)))
12744 (clobber (match_scratch:SI 4 "=&r,&r"))]
12745 "TARGET_POWER"
12746 "@
12747 doz%I2 %4,%1,%2\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
12748 #"
12749 [(set_attr "type" "compare")
12750 (set_attr "length" "12,16")])
12752 (define_split
12753 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12754 (compare:CC
12755 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12756 (match_operand:SI 2 "reg_or_short_operand" ""))
12757 (match_operand:SI 3 "gpc_reg_operand" ""))
12758 (const_int 0)))
12759 (clobber (match_scratch:SI 4 ""))]
12760 "TARGET_POWER && reload_completed"
12761 [(set (match_dup 4)
12762 (plus:SI (lt:SI (match_dup 1) (match_dup 2))
12763 (match_dup 3)))
12764 (set (match_dup 0)
12765 (compare:CC (match_dup 4)
12766 (const_int 0)))]
12767 "")
12769 (define_insn ""
12770 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12771 (compare:CC
12772 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12773 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12774 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
12775 (const_int 0)))
12776 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12777 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12778 "TARGET_POWER"
12779 "@
12780 doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
12781 #"
12782 [(set_attr "type" "compare")
12783 (set_attr "length" "12,16")])
12785 (define_split
12786 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12787 (compare:CC
12788 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "")
12789 (match_operand:SI 2 "reg_or_short_operand" ""))
12790 (match_operand:SI 3 "gpc_reg_operand" ""))
12791 (const_int 0)))
12792 (set (match_operand:SI 0 "gpc_reg_operand" "")
12793 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12794 "TARGET_POWER && reload_completed"
12795 [(set (match_dup 0)
12796 (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12797 (set (match_dup 4)
12798 (compare:CC (match_dup 0)
12799 (const_int 0)))]
12800 "")
12802 (define_insn ""
12803 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12804 (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12805 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
12806 "TARGET_POWER"
12807 "doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
12808 [(set_attr "length" "12")])
12810 (define_insn ""
12811 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12812 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12813 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
12814 "! TARGET_POWERPC64"
12815 "@
12816 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
12817 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
12818 [(set_attr "length" "12")])
12820 (define_insn ""
12821 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
12822 (compare:CC
12823 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12824 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12825 (const_int 0)))
12826 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
12827 (ltu:SI (match_dup 1) (match_dup 2)))]
12828 "! TARGET_POWERPC64"
12829 "@
12830 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12831 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
12832 #
12833 #"
12834 [(set_attr "type" "compare")
12835 (set_attr "length" "12,12,16,16")])
12837 (define_split
12838 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
12839 (compare:CC
12840 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12841 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12842 (const_int 0)))
12843 (set (match_operand:SI 0 "gpc_reg_operand" "")
12844 (ltu:SI (match_dup 1) (match_dup 2)))]
12845 "! TARGET_POWERPC64 && reload_completed"
12846 [(set (match_dup 0)
12847 (ltu:SI (match_dup 1) (match_dup 2)))
12848 (set (match_dup 3)
12849 (compare:CC (match_dup 0)
12850 (const_int 0)))]
12851 "")
12853 (define_insn ""
12854 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
12855 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12856 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
12857 (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
12858 "! TARGET_POWERPC64"
12859 "@
12860 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3
12861 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
12862 [(set_attr "length" "12")])
12864 (define_insn ""
12865 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
12866 (compare:CC
12867 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12868 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12869 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12870 (const_int 0)))
12871 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
12872 "! TARGET_POWERPC64"
12873 "@
12874 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12875 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
12876 #
12877 #"
12878 [(set_attr "type" "compare")
12879 (set_attr "length" "12,12,16,16")])
12881 (define_split
12882 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
12883 (compare:CC
12884 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12885 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12886 (match_operand:SI 3 "gpc_reg_operand" ""))
12887 (const_int 0)))
12888 (clobber (match_scratch:SI 4 ""))]
12889 "! TARGET_POWERPC64 && reload_completed"
12890 [(set (match_dup 4)
12891 (plus:SI (ltu:SI (match_dup 1) (match_dup 2))
12892 (match_dup 3)))
12893 (set (match_dup 0)
12894 (compare:CC (match_dup 4)
12895 (const_int 0)))]
12896 "")
12898 (define_insn ""
12899 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
12900 (compare:CC
12901 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
12902 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
12903 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
12904 (const_int 0)))
12905 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
12906 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12907 "! TARGET_POWERPC64"
12908 "@
12909 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
12910 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
12911 #
12912 #"
12913 [(set_attr "type" "compare")
12914 (set_attr "length" "12,12,16,16")])
12916 (define_split
12917 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12918 (compare:CC
12919 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "")
12920 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
12921 (match_operand:SI 3 "gpc_reg_operand" ""))
12922 (const_int 0)))
12923 (set (match_operand:SI 0 "gpc_reg_operand" "")
12924 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
12925 "! TARGET_POWERPC64 && reload_completed"
12926 [(set (match_dup 0)
12927 (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
12928 (set (match_dup 4)
12929 (compare:CC (match_dup 0)
12930 (const_int 0)))]
12931 "")
12933 (define_insn ""
12934 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12935 (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12936 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
12937 "! TARGET_POWERPC64"
12938 "@
12939 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
12940 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
12941 [(set_attr "length" "8")])
12943 (define_insn ""
12944 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
12945 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12946 (match_operand:SI 2 "reg_or_short_operand" "rI")))
12947 (clobber (match_scratch:SI 3 "=r"))]
12948 "TARGET_POWER"
12949 "doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae|adde} %0,%0,%3"
12950 [(set_attr "length" "12")])
12952 (define_insn ""
12953 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
12954 (compare:CC
12955 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12956 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
12957 (const_int 0)))
12958 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
12959 (ge:SI (match_dup 1) (match_dup 2)))
12960 (clobber (match_scratch:SI 3 "=r,r"))]
12961 "TARGET_POWER"
12962 "@
12963 doz%I2 %3,%1,%2\;{sfi|subfic} %0,%3,0\;{ae.|adde.} %0,%0,%3
12964 #"
12965 [(set_attr "type" "compare")
12966 (set_attr "length" "12,16")])
12968 (define_split
12969 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
12970 (compare:CC
12971 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
12972 (match_operand:SI 2 "reg_or_short_operand" ""))
12973 (const_int 0)))
12974 (set (match_operand:SI 0 "gpc_reg_operand" "")
12975 (ge:SI (match_dup 1) (match_dup 2)))
12976 (clobber (match_scratch:SI 3 ""))]
12977 "TARGET_POWER && reload_completed"
12978 [(parallel [(set (match_dup 0)
12979 (ge:SI (match_dup 1) (match_dup 2)))
12980 (clobber (match_dup 3))])
12981 (set (match_dup 4)
12982 (compare:CC (match_dup 0)
12983 (const_int 0)))]
12984 "")
12986 (define_insn ""
12987 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
12988 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
12989 (match_operand:SI 2 "reg_or_short_operand" "rI"))
12990 (match_operand:SI 3 "gpc_reg_operand" "r")))]
12991 "TARGET_POWER"
12992 "doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
12993 [(set_attr "length" "12")])
12995 (define_insn ""
12996 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
12997 (compare:CC
12998 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
12999 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13000 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13001 (const_int 0)))
13002 (clobber (match_scratch:SI 4 "=&r,&r"))]
13003 "TARGET_POWER"
13004 "@
13005 doz%I2 %4,%1,%2\;{sfi|subfic} %4,%4,0\;{aze.|addze.} %4,%3
13006 #"
13007 [(set_attr "type" "compare")
13008 (set_attr "length" "12,16")])
13010 (define_split
13011 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13012 (compare:CC
13013 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13014 (match_operand:SI 2 "reg_or_short_operand" ""))
13015 (match_operand:SI 3 "gpc_reg_operand" ""))
13016 (const_int 0)))
13017 (clobber (match_scratch:SI 4 ""))]
13018 "TARGET_POWER && reload_completed"
13019 [(set (match_dup 4)
13020 (plus:SI (ge:SI (match_dup 1) (match_dup 2))
13021 (match_dup 3)))
13022 (set (match_dup 0)
13023 (compare:CC (match_dup 4)
13024 (const_int 0)))]
13025 "")
13027 (define_insn ""
13028 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13029 (compare:CC
13030 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13031 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13032 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13033 (const_int 0)))
13034 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13035 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13036 "TARGET_POWER"
13037 "@
13038 doz%I2 %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze.|addze.} %0,%3
13039 #"
13040 [(set_attr "type" "compare")
13041 (set_attr "length" "12,16")])
13043 (define_split
13044 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13045 (compare:CC
13046 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "")
13047 (match_operand:SI 2 "reg_or_short_operand" ""))
13048 (match_operand:SI 3 "gpc_reg_operand" ""))
13049 (const_int 0)))
13050 (set (match_operand:SI 0 "gpc_reg_operand" "")
13051 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13052 "TARGET_POWER && reload_completed"
13053 [(set (match_dup 0)
13054 (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13055 (set (match_dup 4)
13056 (compare:CC (match_dup 0)
13057 (const_int 0)))]
13058 "")
13060 (define_insn ""
13061 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13062 (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13063 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13064 "TARGET_POWER"
13065 "doz%I2 %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
13066 [(set_attr "length" "12")])
13068 (define_insn ""
13069 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13070 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13071 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
13072 "! TARGET_POWERPC64"
13073 "@
13074 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
13075 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
13076 [(set_attr "length" "12")])
13078 (define_insn ""
13079 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13080 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13081 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
13082 "TARGET_POWERPC64"
13083 "@
13084 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
13085 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
13086 [(set_attr "length" "12")])
13088 (define_insn ""
13089 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13090 (compare:CC
13091 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13092 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13093 (const_int 0)))
13094 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
13095 (geu:SI (match_dup 1) (match_dup 2)))]
13096 "! TARGET_POWERPC64"
13097 "@
13098 {sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13099 {ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae.|adde.} %0,%0,%0
13100 #
13101 #"
13102 [(set_attr "type" "compare")
13103 (set_attr "length" "12,12,16,16")])
13105 (define_split
13106 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13107 (compare:CC
13108 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13109 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13110 (const_int 0)))
13111 (set (match_operand:SI 0 "gpc_reg_operand" "")
13112 (geu:SI (match_dup 1) (match_dup 2)))]
13113 "! TARGET_POWERPC64 && reload_completed"
13114 [(set (match_dup 0)
13115 (geu:SI (match_dup 1) (match_dup 2)))
13116 (set (match_dup 3)
13117 (compare:CC (match_dup 0)
13118 (const_int 0)))]
13119 "")
13121 (define_insn ""
13122 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
13123 (compare:CC
13124 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13125 (match_operand:DI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13126 (const_int 0)))
13127 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r")
13128 (geu:DI (match_dup 1) (match_dup 2)))]
13129 "TARGET_POWERPC64"
13130 "@
13131 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0
13132 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0
13133 #
13134 #"
13135 [(set_attr "type" "compare")
13136 (set_attr "length" "12,12,16,16")])
13138 (define_split
13139 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13140 (compare:CC
13141 (geu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13142 (match_operand:DI 2 "reg_or_neg_short_operand" ""))
13143 (const_int 0)))
13144 (set (match_operand:DI 0 "gpc_reg_operand" "")
13145 (geu:DI (match_dup 1) (match_dup 2)))]
13146 "TARGET_POWERPC64 && reload_completed"
13147 [(set (match_dup 0)
13148 (geu:DI (match_dup 1) (match_dup 2)))
13149 (set (match_dup 3)
13150 (compare:CC (match_dup 0)
13151 (const_int 0)))]
13152 "")
13154 (define_insn ""
13155 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13156 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13157 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
13158 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
13159 "! TARGET_POWERPC64"
13160 "@
13161 {sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
13162 {ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
13163 [(set_attr "length" "8")])
13165 (define_insn ""
13166 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13167 (compare:CC
13168 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13169 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13170 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13171 (const_int 0)))
13172 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13173 "! TARGET_POWERPC64"
13174 "@
13175 {sf|subfc} %4,%2,%1\;{aze.|addze.} %4,%3
13176 {ai|addic} %4,%1,%n2\;{aze.|addze.} %4,%3
13177 #
13178 #"
13179 [(set_attr "type" "compare")
13180 (set_attr "length" "8,8,12,12")])
13182 (define_split
13183 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13184 (compare:CC
13185 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13186 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13187 (match_operand:SI 3 "gpc_reg_operand" ""))
13188 (const_int 0)))
13189 (clobber (match_scratch:SI 4 ""))]
13190 "! TARGET_POWERPC64 && reload_completed"
13191 [(set (match_dup 4)
13192 (plus:SI (geu:SI (match_dup 1) (match_dup 2))
13193 (match_dup 3)))
13194 (set (match_dup 0)
13195 (compare:CC (match_dup 4)
13196 (const_int 0)))]
13197 "")
13199 (define_insn ""
13200 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13201 (compare:CC
13202 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13203 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))
13204 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13205 (const_int 0)))
13206 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13207 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13208 "! TARGET_POWERPC64"
13209 "@
13210 {sf|subfc} %0,%2,%1\;{aze.|addze.} %0,%3
13211 {ai|addic} %0,%1,%n2\;{aze.|addze.} %0,%3
13212 #
13213 #"
13214 [(set_attr "type" "compare")
13215 (set_attr "length" "8,8,12,12")])
13217 (define_split
13218 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13219 (compare:CC
13220 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13221 (match_operand:SI 2 "reg_or_neg_short_operand" ""))
13222 (match_operand:SI 3 "gpc_reg_operand" ""))
13223 (const_int 0)))
13224 (set (match_operand:SI 0 "gpc_reg_operand" "")
13225 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13226 "! TARGET_POWERPC64 && reload_completed"
13227 [(set (match_dup 0)
13228 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13229 (set (match_dup 4)
13230 (compare:CC (match_dup 0)
13231 (const_int 0)))]
13232 "")
13234 (define_insn ""
13235 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13236 (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13237 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
13238 "! TARGET_POWERPC64"
13239 "@
13240 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
13241 {sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
13242 [(set_attr "length" "12")])
13244 (define_insn ""
13245 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13246 (and:SI (neg:SI
13247 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13248 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
13249 (match_operand:SI 3 "gpc_reg_operand" "r,r")))]
13250 "! TARGET_POWERPC64"
13251 "@
13252 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
13253 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
13254 [(set_attr "length" "12")])
13256 (define_insn ""
13257 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13258 (compare:CC
13259 (and:SI (neg:SI
13260 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13261 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13262 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13263 (const_int 0)))
13264 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13265 "! TARGET_POWERPC64"
13266 "@
13267 {sf|subfc} %4,%2,%1\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13268 {ai|addic} %4,%1,%n2\;{sfe|subfe} %4,%4,%4\;andc. %4,%3,%4
13269 #
13270 #"
13271 [(set_attr "type" "compare")
13272 (set_attr "length" "12,12,16,16")])
13274 (define_split
13275 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13276 (compare:CC
13277 (and:SI (neg:SI
13278 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13279 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13280 (match_operand:SI 3 "gpc_reg_operand" ""))
13281 (const_int 0)))
13282 (clobber (match_scratch:SI 4 ""))]
13283 "! TARGET_POWERPC64 && reload_completed"
13284 [(set (match_dup 4)
13285 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2)))
13286 (match_dup 3)))
13287 (set (match_dup 0)
13288 (compare:CC (match_dup 4)
13289 (const_int 0)))]
13290 "")
13292 (define_insn ""
13293 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13294 (compare:CC
13295 (and:SI (neg:SI
13296 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13297 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")))
13298 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13299 (const_int 0)))
13300 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13301 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13302 "! TARGET_POWERPC64"
13303 "@
13304 {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13305 {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc. %0,%3,%0
13306 #
13307 #"
13308 [(set_attr "type" "compare")
13309 (set_attr "length" "12,12,16,16")])
13311 (define_split
13312 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13313 (compare:CC
13314 (and:SI (neg:SI
13315 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13316 (match_operand:SI 2 "reg_or_neg_short_operand" "")))
13317 (match_operand:SI 3 "gpc_reg_operand" ""))
13318 (const_int 0)))
13319 (set (match_operand:SI 0 "gpc_reg_operand" "")
13320 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))]
13321 "! TARGET_POWERPC64 && reload_completed"
13322 [(set (match_dup 0)
13323 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
13324 (set (match_dup 4)
13325 (compare:CC (match_dup 0)
13326 (const_int 0)))]
13327 "")
13329 (define_insn ""
13330 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13331 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13332 (const_int 0)))]
13333 "! TARGET_POWERPC64"
13334 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
13335 [(set_attr "length" "12")])
13337 (define_insn ""
13338 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13339 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13340 (const_int 0)))]
13341 "TARGET_POWERPC64"
13342 "subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
13343 [(set_attr "length" "12")])
13345 (define_insn ""
13346 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
13347 (compare:CC
13348 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13349 (const_int 0))
13350 (const_int 0)))
13351 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13352 (gt:SI (match_dup 1) (const_int 0)))]
13353 "! TARGET_POWERPC64"
13354 "@
13355 {sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri.|srwi.} %0,%0,31
13356 #"
13357 [(set_attr "type" "delayed_compare")
13358 (set_attr "length" "12,16")])
13360 (define_split
13361 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
13362 (compare:CC
13363 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13364 (const_int 0))
13365 (const_int 0)))
13366 (set (match_operand:SI 0 "gpc_reg_operand" "")
13367 (gt:SI (match_dup 1) (const_int 0)))]
13368 "! TARGET_POWERPC64 && reload_completed"
13369 [(set (match_dup 0)
13370 (gt:SI (match_dup 1) (const_int 0)))
13371 (set (match_dup 2)
13372 (compare:CC (match_dup 0)
13373 (const_int 0)))]
13374 "")
13376 (define_insn ""
13377 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
13378 (compare:CC
13379 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13380 (const_int 0))
13381 (const_int 0)))
13382 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13383 (gt:DI (match_dup 1) (const_int 0)))]
13384 "TARGET_POWERPC64"
13385 "@
13386 subfic %0,%1,0\;addme %0,%0\;srdi. %0,%0,63
13387 #"
13388 [(set_attr "type" "delayed_compare")
13389 (set_attr "length" "12,16")])
13391 (define_split
13392 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "")
13393 (compare:CC
13394 (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13395 (const_int 0))
13396 (const_int 0)))
13397 (set (match_operand:DI 0 "gpc_reg_operand" "")
13398 (gt:DI (match_dup 1) (const_int 0)))]
13399 "TARGET_POWERPC64 && reload_completed"
13400 [(set (match_dup 0)
13401 (gt:DI (match_dup 1) (const_int 0)))
13402 (set (match_dup 2)
13403 (compare:CC (match_dup 0)
13404 (const_int 0)))]
13405 "")
13407 (define_insn ""
13408 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13409 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13410 (match_operand:SI 2 "reg_or_short_operand" "r")))]
13411 "TARGET_POWER"
13412 "doz %0,%2,%1\;nabs %0,%0\;{sri|srwi} %0,%0,31"
13413 [(set_attr "length" "12")])
13415 (define_insn ""
13416 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13417 (compare:CC
13418 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13419 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13420 (const_int 0)))
13421 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13422 (gt:SI (match_dup 1) (match_dup 2)))]
13423 "TARGET_POWER"
13424 "@
13425 doz %0,%2,%1\;nabs %0,%0\;{sri.|srwi.} %0,%0,31
13426 #"
13427 [(set_attr "type" "delayed_compare")
13428 (set_attr "length" "12,16")])
13430 (define_split
13431 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13432 (compare:CC
13433 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13434 (match_operand:SI 2 "reg_or_short_operand" ""))
13435 (const_int 0)))
13436 (set (match_operand:SI 0 "gpc_reg_operand" "")
13437 (gt:SI (match_dup 1) (match_dup 2)))]
13438 "TARGET_POWER && reload_completed"
13439 [(set (match_dup 0)
13440 (gt:SI (match_dup 1) (match_dup 2)))
13441 (set (match_dup 3)
13442 (compare:CC (match_dup 0)
13443 (const_int 0)))]
13444 "")
13446 (define_insn ""
13447 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13448 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13449 (const_int 0))
13450 (match_operand:SI 2 "gpc_reg_operand" "r")))]
13451 "! TARGET_POWERPC64"
13452 "{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
13453 [(set_attr "length" "12")])
13455 (define_insn ""
13456 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
13457 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13458 (const_int 0))
13459 (match_operand:DI 2 "gpc_reg_operand" "r")))]
13460 "TARGET_POWERPC64"
13461 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
13462 [(set_attr "length" "12")])
13464 (define_insn ""
13465 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13466 (compare:CC
13467 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13468 (const_int 0))
13469 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13470 (const_int 0)))
13471 (clobber (match_scratch:SI 3 "=&r,&r"))]
13472 "! TARGET_POWERPC64"
13473 "@
13474 {a|addc} %3,%1,%1\;{sfe|subfe} %3,%1,%3\;{aze.|addze.} %3,%2
13475 #"
13476 [(set_attr "type" "compare")
13477 (set_attr "length" "12,16")])
13479 (define_split
13480 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13481 (compare:CC
13482 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13483 (const_int 0))
13484 (match_operand:SI 2 "gpc_reg_operand" ""))
13485 (const_int 0)))
13486 (clobber (match_scratch:SI 3 ""))]
13487 "! TARGET_POWERPC64 && reload_completed"
13488 [(set (match_dup 3)
13489 (plus:SI (gt:SI (match_dup 1) (const_int 0))
13490 (match_dup 2)))
13491 (set (match_dup 0)
13492 (compare:CC (match_dup 3)
13493 (const_int 0)))]
13494 "")
13496 (define_insn ""
13497 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13498 (compare:CC
13499 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13500 (const_int 0))
13501 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13502 (const_int 0)))
13503 (clobber (match_scratch:DI 3 "=&r,&r"))]
13504 "TARGET_POWERPC64"
13505 "@
13506 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2
13507 #"
13508 [(set_attr "type" "compare")
13509 (set_attr "length" "12,16")])
13511 (define_split
13512 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13513 (compare:CC
13514 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13515 (const_int 0))
13516 (match_operand:DI 2 "gpc_reg_operand" ""))
13517 (const_int 0)))
13518 (clobber (match_scratch:DI 3 ""))]
13519 "TARGET_POWERPC64 && reload_completed"
13520 [(set (match_dup 3)
13521 (plus:DI (gt:DI (match_dup 1) (const_int 0))
13522 (match_dup 2)))
13523 (set (match_dup 0)
13524 (compare:CC (match_dup 3)
13525 (const_int 0)))]
13526 "")
13528 (define_insn ""
13529 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13530 (compare:CC
13531 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13532 (const_int 0))
13533 (match_operand:SI 2 "gpc_reg_operand" "r,r"))
13534 (const_int 0)))
13535 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13536 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13537 "! TARGET_POWERPC64"
13538 "@
13539 {a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze.|addze.} %0,%2
13540 #"
13541 [(set_attr "type" "compare")
13542 (set_attr "length" "12,16")])
13544 (define_split
13545 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13546 (compare:CC
13547 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13548 (const_int 0))
13549 (match_operand:SI 2 "gpc_reg_operand" ""))
13550 (const_int 0)))
13551 (set (match_operand:SI 0 "gpc_reg_operand" "")
13552 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))]
13553 "! TARGET_POWERPC64 && reload_completed"
13554 [(set (match_dup 0)
13555 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
13556 (set (match_dup 3)
13557 (compare:CC (match_dup 0)
13558 (const_int 0)))]
13559 "")
13561 (define_insn ""
13562 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13563 (compare:CC
13564 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13565 (const_int 0))
13566 (match_operand:DI 2 "gpc_reg_operand" "r,r"))
13567 (const_int 0)))
13568 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13569 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13570 "TARGET_POWERPC64"
13571 "@
13572 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2
13573 #"
13574 [(set_attr "type" "compare")
13575 (set_attr "length" "12,16")])
13577 (define_split
13578 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13579 (compare:CC
13580 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "")
13581 (const_int 0))
13582 (match_operand:DI 2 "gpc_reg_operand" ""))
13583 (const_int 0)))
13584 (set (match_operand:DI 0 "gpc_reg_operand" "")
13585 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))]
13586 "TARGET_POWERPC64 && reload_completed"
13587 [(set (match_dup 0)
13588 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))
13589 (set (match_dup 3)
13590 (compare:CC (match_dup 0)
13591 (const_int 0)))]
13592 "")
13594 (define_insn ""
13595 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
13596 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13597 (match_operand:SI 2 "reg_or_short_operand" "r"))
13598 (match_operand:SI 3 "gpc_reg_operand" "r")))]
13599 "TARGET_POWER"
13600 "doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze|addze} %0,%3"
13601 [(set_attr "length" "12")])
13603 (define_insn ""
13604 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
13605 (compare:CC
13606 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13607 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13608 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13609 (const_int 0)))
13610 (clobber (match_scratch:SI 4 "=&r,&r"))]
13611 "TARGET_POWER"
13612 "@
13613 doz %4,%2,%1\;{ai|addic} %4,%4,-1\;{aze.|addze.} %4,%3
13614 #"
13615 [(set_attr "type" "compare")
13616 (set_attr "length" "12,16")])
13618 (define_split
13619 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13620 (compare:CC
13621 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13622 (match_operand:SI 2 "reg_or_short_operand" ""))
13623 (match_operand:SI 3 "gpc_reg_operand" ""))
13624 (const_int 0)))
13625 (clobber (match_scratch:SI 4 ""))]
13626 "TARGET_POWER && reload_completed"
13627 [(set (match_dup 4)
13628 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13629 (set (match_dup 0)
13630 (compare:CC (match_dup 4)
13631 (const_int 0)))]
13632 "")
13634 (define_insn ""
13635 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y")
13636 (compare:CC
13637 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13638 (match_operand:SI 2 "reg_or_short_operand" "r,r"))
13639 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
13640 (const_int 0)))
13641 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13642 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13643 "TARGET_POWER"
13644 "@
13645 doz %0,%2,%1\;{ai|addic} %0,%0,-1\;{aze.|addze.} %0,%3
13646 #"
13647 [(set_attr "type" "compare")
13648 (set_attr "length" "12,16")])
13650 (define_split
13651 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13652 (compare:CC
13653 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
13654 (match_operand:SI 2 "reg_or_short_operand" ""))
13655 (match_operand:SI 3 "gpc_reg_operand" ""))
13656 (const_int 0)))
13657 (set (match_operand:SI 0 "gpc_reg_operand" "")
13658 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13659 "TARGET_POWER && reload_completed"
13660 [(set (match_dup 0)
13661 (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13662 (set (match_dup 4)
13663 (compare:CC (match_dup 0)
13664 (const_int 0)))]
13665 "")
13667 (define_insn ""
13668 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13669 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13670 (const_int 0))))]
13671 "! TARGET_POWERPC64"
13672 "{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
13673 [(set_attr "length" "12")])
13675 (define_insn ""
13676 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13677 (neg:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13678 (const_int 0))))]
13679 "TARGET_POWERPC64"
13680 "subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
13681 [(set_attr "length" "12")])
13683 (define_insn ""
13684 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13685 (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13686 (match_operand:SI 2 "reg_or_short_operand" "r"))))]
13687 "TARGET_POWER"
13688 "doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
13689 [(set_attr "length" "12")])
13691 (define_insn ""
13692 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13693 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13694 (match_operand:SI 2 "reg_or_short_operand" "rI")))]
13695 "! TARGET_POWERPC64"
13696 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
13697 [(set_attr "length" "12")])
13699 (define_insn ""
13700 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13701 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13702 (match_operand:DI 2 "reg_or_short_operand" "rI")))]
13703 "TARGET_POWERPC64"
13704 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0"
13705 [(set_attr "length" "12")])
13707 (define_insn ""
13708 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13709 (compare:CC
13710 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13711 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
13712 (const_int 0)))
13713 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
13714 (gtu:SI (match_dup 1) (match_dup 2)))]
13715 "! TARGET_POWERPC64"
13716 "@
13717 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg. %0,%0
13718 #"
13719 [(set_attr "type" "compare")
13720 (set_attr "length" "12,16")])
13722 (define_split
13723 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13724 (compare:CC
13725 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13726 (match_operand:SI 2 "reg_or_short_operand" ""))
13727 (const_int 0)))
13728 (set (match_operand:SI 0 "gpc_reg_operand" "")
13729 (gtu:SI (match_dup 1) (match_dup 2)))]
13730 "! TARGET_POWERPC64 && reload_completed"
13731 [(set (match_dup 0)
13732 (gtu:SI (match_dup 1) (match_dup 2)))
13733 (set (match_dup 3)
13734 (compare:CC (match_dup 0)
13735 (const_int 0)))]
13736 "")
13738 (define_insn ""
13739 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
13740 (compare:CC
13741 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13742 (match_operand:DI 2 "reg_or_short_operand" "rI,rI"))
13743 (const_int 0)))
13744 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
13745 (gtu:DI (match_dup 1) (match_dup 2)))]
13746 "TARGET_POWERPC64"
13747 "@
13748 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg. %0,%0
13749 #"
13750 [(set_attr "type" "compare")
13751 (set_attr "length" "12,16")])
13753 (define_split
13754 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")
13755 (compare:CC
13756 (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13757 (match_operand:DI 2 "reg_or_short_operand" ""))
13758 (const_int 0)))
13759 (set (match_operand:DI 0 "gpc_reg_operand" "")
13760 (gtu:DI (match_dup 1) (match_dup 2)))]
13761 "TARGET_POWERPC64 && reload_completed"
13762 [(set (match_dup 0)
13763 (gtu:DI (match_dup 1) (match_dup 2)))
13764 (set (match_dup 3)
13765 (compare:CC (match_dup 0)
13766 (const_int 0)))]
13767 "")
13769 (define_insn ""
13770 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
13771 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
13772 (match_operand:SI 2 "reg_or_short_operand" "I,rI"))
13773 (match_operand:SI 3 "reg_or_short_operand" "r,rI")))]
13774 "! TARGET_POWERPC64"
13775 "@
13776 {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3
13777 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf%I3|subf%I3c} %0,%0,%3"
13778 [(set_attr "length" "8,12")])
13780 (define_insn ""
13781 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r")
13782 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
13783 (match_operand:DI 2 "reg_or_short_operand" "I,rI"))
13784 (match_operand:DI 3 "reg_or_short_operand" "r,rI")))]
13785 "TARGET_POWERPC64"
13786 "@
13787 addic %0,%1,%k2\;addze %0,%3
13788 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf%I3c %0,%0,%3"
13789 [(set_attr "length" "8,12")])
13791 (define_insn ""
13792 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13793 (compare:CC
13794 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13795 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13796 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13797 (const_int 0)))
13798 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))]
13799 "! TARGET_POWERPC64"
13800 "@
13801 {ai|addic} %4,%1,%k2\;{aze.|addze.} %4,%3
13802 {sf%I2|subf%I2c} %4,%1,%2\;{sfe|subfe} %4,%4,%4\;{sf.|subfc.} %4,%4,%3
13803 #
13804 #"
13805 [(set_attr "type" "compare")
13806 (set_attr "length" "8,12,12,16")])
13808 (define_split
13809 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13810 (compare:CC
13811 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13812 (match_operand:SI 2 "reg_or_short_operand" ""))
13813 (match_operand:SI 3 "gpc_reg_operand" ""))
13814 (const_int 0)))
13815 (clobber (match_scratch:SI 4 ""))]
13816 "! TARGET_POWERPC64 && reload_completed"
13817 [(set (match_dup 4)
13818 (plus:SI (gtu:SI (match_dup 1) (match_dup 2))
13819 (match_dup 3)))
13820 (set (match_dup 0)
13821 (compare:CC (match_dup 4)
13822 (const_int 0)))]
13823 "")
13825 (define_insn ""
13826 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
13827 (compare:CC
13828 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13829 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13830 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13831 (const_int 0)))
13832 (clobber (match_scratch:DI 4 "=&r,&r,&r,&r"))]
13833 "TARGET_POWERPC64"
13834 "@
13835 addic %4,%1,%k2\;addze. %4,%3
13836 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;subfc. %4,%4,%3
13837 #
13838 #"
13839 [(set_attr "type" "compare")
13840 (set_attr "length" "8,12,12,16")])
13842 (define_split
13843 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
13844 (compare:CC
13845 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13846 (match_operand:DI 2 "reg_or_short_operand" ""))
13847 (match_operand:DI 3 "gpc_reg_operand" ""))
13848 (const_int 0)))
13849 (clobber (match_scratch:DI 4 ""))]
13850 "TARGET_POWERPC64 && reload_completed"
13851 [(set (match_dup 4)
13852 (plus:DI (gtu:DI (match_dup 1) (match_dup 2))
13853 (match_dup 3)))
13854 (set (match_dup 0)
13855 (compare:CC (match_dup 4)
13856 (const_int 0)))]
13857 "")
13859 (define_insn ""
13860 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13861 (compare:CC
13862 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
13863 (match_operand:SI 2 "reg_or_short_operand" "I,r,I,r"))
13864 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r"))
13865 (const_int 0)))
13866 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13867 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13868 "! TARGET_POWERPC64"
13869 "@
13870 {ai|addic} %0,%1,%k2\;{aze.|addze.} %0,%3
13871 {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf.|subfc.} %0,%0,%3
13872 #
13873 #"
13874 [(set_attr "type" "compare")
13875 (set_attr "length" "8,12,12,16")])
13877 (define_split
13878 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13879 (compare:CC
13880 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "")
13881 (match_operand:SI 2 "reg_or_short_operand" ""))
13882 (match_operand:SI 3 "gpc_reg_operand" ""))
13883 (const_int 0)))
13884 (set (match_operand:SI 0 "gpc_reg_operand" "")
13885 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13886 "! TARGET_POWERPC64 && reload_completed"
13887 [(set (match_dup 0)
13888 (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
13889 (set (match_dup 4)
13890 (compare:CC (match_dup 0)
13891 (const_int 0)))]
13892 "")
13894 (define_insn ""
13895 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y")
13896 (compare:CC
13897 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r")
13898 (match_operand:DI 2 "reg_or_short_operand" "I,r,I,r"))
13899 (match_operand:DI 3 "gpc_reg_operand" "r,r,r,r"))
13900 (const_int 0)))
13901 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
13902 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13903 "TARGET_POWERPC64"
13904 "@
13905 addic %0,%1,%k2\;addze. %0,%3
13906 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfc. %0,%0,%3
13907 #
13908 #"
13909 [(set_attr "type" "compare")
13910 (set_attr "length" "8,12,12,16")])
13912 (define_split
13913 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "")
13914 (compare:CC
13915 (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "")
13916 (match_operand:DI 2 "reg_or_short_operand" ""))
13917 (match_operand:DI 3 "gpc_reg_operand" ""))
13918 (const_int 0)))
13919 (set (match_operand:DI 0 "gpc_reg_operand" "")
13920 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
13921 "TARGET_POWERPC64 && reload_completed"
13922 [(set (match_dup 0)
13923 (plus:DI (gtu:DI (match_dup 1) (match_dup 2)) (match_dup 3)))
13924 (set (match_dup 4)
13925 (compare:CC (match_dup 0)
13926 (const_int 0)))]
13927 "")
13929 (define_insn ""
13930 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
13931 (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
13932 (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
13933 "! TARGET_POWERPC64"
13934 "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
13935 [(set_attr "length" "8")])
13937 (define_insn ""
13938 [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
13939 (neg:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
13940 (match_operand:DI 2 "reg_or_short_operand" "rI"))))]
13941 "TARGET_POWERPC64"
13942 "subf%I2c %0,%1,%2\;subfe %0,%0,%0"
13943 [(set_attr "length" "8")])
13944 \f
13945 ;; Define both directions of branch and return. If we need a reload
13946 ;; register, we'd rather use CR0 since it is much easier to copy a
13947 ;; register CC value to there.
13949 (define_insn ""
13950 [(set (pc)
13951 (if_then_else (match_operator 1 "branch_comparison_operator"
13952 [(match_operand 2
13953 "cc_reg_operand" "x,?y")
13954 (const_int 0)])
13955 (label_ref (match_operand 0 "" ""))
13956 (pc)))]
13957 ""
13958 "*
13959 {
13960 return output_cbranch (operands[1], \"%l0\", 0, insn);
13961 }"
13962 [(set_attr "type" "branch")])
13964 (define_insn ""
13965 [(set (pc)
13966 (if_then_else (match_operator 0 "branch_comparison_operator"
13967 [(match_operand 1
13968 "cc_reg_operand" "x,?y")
13969 (const_int 0)])
13970 (return)
13971 (pc)))]
13972 "direct_return ()"
13973 "*
13974 {
13975 return output_cbranch (operands[0], NULL, 0, insn);
13976 }"
13977 [(set_attr "type" "branch")
13978 (set_attr "length" "4")])
13980 (define_insn ""
13981 [(set (pc)
13982 (if_then_else (match_operator 1 "branch_comparison_operator"
13983 [(match_operand 2
13984 "cc_reg_operand" "x,?y")
13985 (const_int 0)])
13986 (pc)
13987 (label_ref (match_operand 0 "" ""))))]
13988 ""
13989 "*
13990 {
13991 return output_cbranch (operands[1], \"%l0\", 1, insn);
13992 }"
13993 [(set_attr "type" "branch")])
13995 (define_insn ""
13996 [(set (pc)
13997 (if_then_else (match_operator 0 "branch_comparison_operator"
13998 [(match_operand 1
13999 "cc_reg_operand" "x,?y")
14000 (const_int 0)])
14001 (pc)
14002 (return)))]
14003 "direct_return ()"
14004 "*
14005 {
14006 return output_cbranch (operands[0], NULL, 1, insn);
14007 }"
14008 [(set_attr "type" "branch")
14009 (set_attr "length" "4")])
14011 ;; Logic on condition register values.
14013 ; This pattern matches things like
14014 ; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0))
14015 ; (eq:SI (reg:CCFP 68) (const_int 0)))
14016 ; (const_int 1)))
14017 ; which are generated by the branch logic.
14019 (define_insn ""
14020 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14021 (compare:CCEQ (match_operator:SI 1 "boolean_operator"
14022 [(match_operator:SI 2
14023 "branch_positive_comparison_operator"
14024 [(match_operand 3
14025 "cc_reg_operand" "y")
14026 (const_int 0)])
14027 (match_operator:SI 4
14028 "branch_positive_comparison_operator"
14029 [(match_operand 5
14030 "cc_reg_operand" "y")
14031 (const_int 0)])])
14032 (const_int 1)))]
14033 ""
14034 "cr%q1 %E0,%j2,%j4"
14035 [(set_attr "type" "cr_logical")])
14037 ; Why is the constant -1 here, but 1 in the previous pattern?
14038 ; Because ~1 has all but the low bit set.
14039 (define_insn ""
14040 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14041 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator"
14042 [(not:SI (match_operator:SI 2
14043 "branch_positive_comparison_operator"
14044 [(match_operand 3
14045 "cc_reg_operand" "y")
14046 (const_int 0)]))
14047 (match_operator:SI 4
14048 "branch_positive_comparison_operator"
14049 [(match_operand 5
14050 "cc_reg_operand" "y")
14051 (const_int 0)])])
14052 (const_int -1)))]
14053 ""
14054 "cr%q1 %E0,%j2,%j4"
14055 [(set_attr "type" "cr_logical")])
14057 (define_insn ""
14058 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14059 (compare:CCEQ (match_operator:SI 1
14060 "branch_positive_comparison_operator"
14061 [(match_operand 2
14062 "cc_reg_operand" "y")
14063 (const_int 0)])
14064 (const_int 0)))]
14065 "!TARGET_SPE"
14066 "{crnor %E0,%j1,%j1|crnot %E0,%j1}"
14067 [(set_attr "type" "cr_logical")])
14069 ;; If we are comparing the result of two comparisons, this can be done
14070 ;; using creqv or crxor.
14072 (define_insn_and_split ""
14073 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
14074 (compare:CCEQ (match_operator 1 "branch_comparison_operator"
14075 [(match_operand 2 "cc_reg_operand" "y")
14076 (const_int 0)])
14077 (match_operator 3 "branch_comparison_operator"
14078 [(match_operand 4 "cc_reg_operand" "y")
14079 (const_int 0)])))]
14080 ""
14081 "#"
14082 ""
14083 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3))
14084 (match_dup 5)))]
14085 "
14086 {
14087 int positive_1, positive_2;
14089 positive_1 = branch_positive_comparison_operator (operands[1], CCEQmode);
14090 positive_2 = branch_positive_comparison_operator (operands[3], CCEQmode);
14092 if (! positive_1)
14093 operands[1] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[2]),
14094 GET_CODE (operands[1])),
14095 SImode,
14096 operands[2], const0_rtx);
14097 else if (GET_MODE (operands[1]) != SImode)
14098 operands[1] = gen_rtx (GET_CODE (operands[1]),
14099 SImode,
14100 operands[2], const0_rtx);
14102 if (! positive_2)
14103 operands[3] = gen_rtx (rs6000_reverse_condition (GET_MODE (operands[4]),
14104 GET_CODE (operands[3])),
14105 SImode,
14106 operands[4], const0_rtx);
14107 else if (GET_MODE (operands[3]) != SImode)
14108 operands[3] = gen_rtx (GET_CODE (operands[3]),
14109 SImode,
14110 operands[4], const0_rtx);
14112 if (positive_1 == positive_2)
14113 {
14114 operands[1] = gen_rtx_NOT (SImode, operands[1]);
14115 operands[5] = constm1_rtx;
14116 }
14117 else
14118 {
14119 operands[5] = const1_rtx;
14120 }
14121 }")
14123 ;; Unconditional branch and return.
14125 (define_insn "jump"
14126 [(set (pc)
14127 (label_ref (match_operand 0 "" "")))]
14128 ""
14129 "b %l0"
14130 [(set_attr "type" "branch")])
14132 (define_insn "return"
14133 [(return)]
14134 "direct_return ()"
14135 "{br|blr}"
14136 [(set_attr "type" "jmpreg")])
14138 (define_expand "indirect_jump"
14139 [(set (pc) (match_operand 0 "register_operand" ""))]
14140 ""
14141 "
14142 {
14143 if (TARGET_32BIT)
14144 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
14145 else
14146 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
14147 DONE;
14148 }")
14150 (define_insn "indirect_jumpsi"
14151 [(set (pc) (match_operand:SI 0 "register_operand" "c,*l"))]
14152 "TARGET_32BIT"
14153 "@
14154 bctr
14155 {br|blr}"
14156 [(set_attr "type" "jmpreg")])
14158 (define_insn "indirect_jumpdi"
14159 [(set (pc) (match_operand:DI 0 "register_operand" "c,*l"))]
14160 "TARGET_64BIT"
14161 "@
14162 bctr
14163 blr"
14164 [(set_attr "type" "jmpreg")])
14166 ;; Table jump for switch statements:
14167 (define_expand "tablejump"
14168 [(use (match_operand 0 "" ""))
14169 (use (label_ref (match_operand 1 "" "")))]
14170 ""
14171 "
14172 {
14173 if (TARGET_32BIT)
14174 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
14175 else
14176 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
14177 DONE;
14178 }")
14180 (define_expand "tablejumpsi"
14181 [(set (match_dup 3)
14182 (plus:SI (match_operand:SI 0 "" "")
14183 (match_dup 2)))
14184 (parallel [(set (pc) (match_dup 3))
14185 (use (label_ref (match_operand 1 "" "")))])]
14186 "TARGET_32BIT"
14187 "
14188 { operands[0] = force_reg (SImode, operands[0]);
14189 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1]));
14190 operands[3] = gen_reg_rtx (SImode);
14191 }")
14193 (define_expand "tablejumpdi"
14194 [(set (match_dup 4)
14195 (sign_extend:DI (match_operand:SI 0 "lwa_operand" "rm")))
14196 (set (match_dup 3)
14197 (plus:DI (match_dup 4)
14198 (match_dup 2)))
14199 (parallel [(set (pc) (match_dup 3))
14200 (use (label_ref (match_operand 1 "" "")))])]
14201 "TARGET_64BIT"
14202 "
14203 { operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1]));
14204 operands[3] = gen_reg_rtx (DImode);
14205 operands[4] = gen_reg_rtx (DImode);
14206 }")
14208 (define_insn ""
14209 [(set (pc)
14210 (match_operand:SI 0 "register_operand" "c,*l"))
14211 (use (label_ref (match_operand 1 "" "")))]
14212 "TARGET_32BIT"
14213 "@
14214 bctr
14215 {br|blr}"
14216 [(set_attr "type" "jmpreg")])
14218 (define_insn ""
14219 [(set (pc)
14220 (match_operand:DI 0 "register_operand" "c,*l"))
14221 (use (label_ref (match_operand 1 "" "")))]
14222 "TARGET_64BIT"
14223 "@
14224 bctr
14225 blr"
14226 [(set_attr "type" "jmpreg")])
14228 (define_insn "nop"
14229 [(const_int 0)]
14230 ""
14231 "{cror 0,0,0|nop}")
14232 \f
14233 ;; Define the subtract-one-and-jump insns, starting with the template
14234 ;; so loop.c knows what to generate.
14236 (define_expand "doloop_end"
14237 [(use (match_operand 0 "" "")) ; loop pseudo
14238 (use (match_operand 1 "" "")) ; iterations; zero if unknown
14239 (use (match_operand 2 "" "")) ; max iterations
14240 (use (match_operand 3 "" "")) ; loop level
14241 (use (match_operand 4 "" ""))] ; label
14242 ""
14243 "
14244 {
14245 /* Only use this on innermost loops. */
14246 if (INTVAL (operands[3]) > 1)
14247 FAIL;
14248 if (TARGET_POWERPC64)
14249 {
14250 if (GET_MODE (operands[0]) != DImode)
14251 FAIL;
14252 emit_jump_insn (gen_ctrdi (operands[0], operands[4]));
14253 }
14254 else
14255 {
14256 if (GET_MODE (operands[0]) != SImode)
14257 FAIL;
14258 emit_jump_insn (gen_ctrsi (operands[0], operands[4]));
14259 }
14260 DONE;
14261 }")
14263 (define_expand "ctrsi"
14264 [(parallel [(set (pc)
14265 (if_then_else (ne (match_operand:SI 0 "register_operand" "")
14266 (const_int 1))
14267 (label_ref (match_operand 1 "" ""))
14268 (pc)))
14269 (set (match_dup 0)
14270 (plus:SI (match_dup 0)
14271 (const_int -1)))
14272 (clobber (match_scratch:CC 2 ""))
14273 (clobber (match_scratch:SI 3 ""))])]
14274 "! TARGET_POWERPC64"
14275 "")
14277 (define_expand "ctrdi"
14278 [(parallel [(set (pc)
14279 (if_then_else (ne (match_operand:DI 0 "register_operand" "")
14280 (const_int 1))
14281 (label_ref (match_operand 1 "" ""))
14282 (pc)))
14283 (set (match_dup 0)
14284 (plus:DI (match_dup 0)
14285 (const_int -1)))
14286 (clobber (match_scratch:CC 2 ""))
14287 (clobber (match_scratch:DI 3 ""))])]
14288 "TARGET_POWERPC64"
14289 "")
14291 ;; We need to be able to do this for any operand, including MEM, or we
14292 ;; will cause reload to blow up since we don't allow output reloads on
14293 ;; JUMP_INSNs.
14294 ;; For the length attribute to be calculated correctly, the
14295 ;; label MUST be operand 0.
14297 (define_insn "*ctrsi_internal1"
14298 [(set (pc)
14299 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
14300 (const_int 1))
14301 (label_ref (match_operand 0 "" ""))
14302 (pc)))
14303 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
14304 (plus:SI (match_dup 1)
14305 (const_int -1)))
14306 (clobber (match_scratch:CC 3 "=X,&x,&x"))
14307 (clobber (match_scratch:SI 4 "=X,X,r"))]
14308 "! TARGET_POWERPC64"
14309 "*
14310 {
14311 if (which_alternative != 0)
14312 return \"#\";
14313 else if (get_attr_length (insn) == 4)
14314 return \"{bdn|bdnz} %l0\";
14315 else
14316 return \"bdz $+8\;b %l0\";
14317 }"
14318 [(set_attr "type" "branch")
14319 (set_attr "length" "4,12,16")])
14321 (define_insn "*ctrsi_internal2"
14322 [(set (pc)
14323 (if_then_else (ne (match_operand:SI 1 "register_operand" "c,*r,*r")
14324 (const_int 1))
14325 (pc)
14326 (label_ref (match_operand 0 "" ""))))
14327 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
14328 (plus:SI (match_dup 1)
14329 (const_int -1)))
14330 (clobber (match_scratch:CC 3 "=X,&x,&x"))
14331 (clobber (match_scratch:SI 4 "=X,X,r"))]
14332 "! TARGET_POWERPC64"
14333 "*
14334 {
14335 if (which_alternative != 0)
14336 return \"#\";
14337 else if (get_attr_length (insn) == 4)
14338 return \"bdz %l0\";
14339 else
14340 return \"{bdn|bdnz} $+8\;b %l0\";
14341 }"
14342 [(set_attr "type" "branch")
14343 (set_attr "length" "4,12,16")])
14345 (define_insn "*ctrdi_internal1"
14346 [(set (pc)
14347 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
14348 (const_int 1))
14349 (label_ref (match_operand 0 "" ""))
14350 (pc)))
14351 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
14352 (plus:DI (match_dup 1)
14353 (const_int -1)))
14354 (clobber (match_scratch:CC 3 "=X,&x,&x"))
14355 (clobber (match_scratch:DI 4 "=X,X,r"))]
14356 "TARGET_POWERPC64"
14357 "*
14358 {
14359 if (which_alternative != 0)
14360 return \"#\";
14361 else if (get_attr_length (insn) == 4)
14362 return \"{bdn|bdnz} %l0\";
14363 else
14364 return \"bdz $+8\;b %l0\";
14365 }"
14366 [(set_attr "type" "branch")
14367 (set_attr "length" "4,12,16")])
14369 (define_insn "*ctrdi_internal2"
14370 [(set (pc)
14371 (if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
14372 (const_int 1))
14373 (pc)
14374 (label_ref (match_operand 0 "" ""))))
14375 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
14376 (plus:DI (match_dup 1)
14377 (const_int -1)))
14378 (clobber (match_scratch:CC 3 "=X,&x,&x"))
14379 (clobber (match_scratch:DI 4 "=X,X,r"))]
14380 "TARGET_POWERPC64"
14381 "*
14382 {
14383 if (which_alternative != 0)
14384 return \"#\";
14385 else if (get_attr_length (insn) == 4)
14386 return \"bdz %l0\";
14387 else
14388 return \"{bdn|bdnz} $+8\;b %l0\";
14389 }"
14390 [(set_attr "type" "branch")
14391 (set_attr "length" "4,12,16")])
14393 ;; Similar, but we can use GE since we have a REG_NONNEG.
14395 (define_insn "*ctrsi_internal3"
14396 [(set (pc)
14397 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
14398 (const_int 0))
14399 (label_ref (match_operand 0 "" ""))
14400 (pc)))
14401 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
14402 (plus:SI (match_dup 1)
14403 (const_int -1)))
14404 (clobber (match_scratch:CC 3 "=X,&x,&X"))
14405 (clobber (match_scratch:SI 4 "=X,X,r"))]
14406 "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
14407 "*
14408 {
14409 if (which_alternative != 0)
14410 return \"#\";
14411 else if (get_attr_length (insn) == 4)
14412 return \"{bdn|bdnz} %l0\";
14413 else
14414 return \"bdz $+8\;b %l0\";
14415 }"
14416 [(set_attr "type" "branch")
14417 (set_attr "length" "4,12,16")])
14419 (define_insn "*ctrsi_internal4"
14420 [(set (pc)
14421 (if_then_else (ge (match_operand:SI 1 "register_operand" "c,*r,*r")
14422 (const_int 0))
14423 (pc)
14424 (label_ref (match_operand 0 "" ""))))
14425 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
14426 (plus:SI (match_dup 1)
14427 (const_int -1)))
14428 (clobber (match_scratch:CC 3 "=X,&x,&X"))
14429 (clobber (match_scratch:SI 4 "=X,X,r"))]
14430 "! TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
14431 "*
14432 {
14433 if (which_alternative != 0)
14434 return \"#\";
14435 else if (get_attr_length (insn) == 4)
14436 return \"bdz %l0\";
14437 else
14438 return \"{bdn|bdnz} $+8\;b %l0\";
14439 }"
14440 [(set_attr "type" "branch")
14441 (set_attr "length" "4,12,16")])
14443 (define_insn "*ctrdi_internal3"
14444 [(set (pc)
14445 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
14446 (const_int 0))
14447 (label_ref (match_operand 0 "" ""))
14448 (pc)))
14449 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
14450 (plus:DI (match_dup 1)
14451 (const_int -1)))
14452 (clobber (match_scratch:CC 3 "=X,&x,&x"))
14453 (clobber (match_scratch:DI 4 "=X,X,r"))]
14454 "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
14455 "*
14456 {
14457 if (which_alternative != 0)
14458 return \"#\";
14459 else if (get_attr_length (insn) == 4)
14460 return \"{bdn|bdnz} %l0\";
14461 else
14462 return \"bdz $+8\;b %l0\";
14463 }"
14464 [(set_attr "type" "branch")
14465 (set_attr "length" "4,12,16")])
14467 (define_insn "*ctrdi_internal4"
14468 [(set (pc)
14469 (if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
14470 (const_int 0))
14471 (pc)
14472 (label_ref (match_operand 0 "" ""))))
14473 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
14474 (plus:DI (match_dup 1)
14475 (const_int -1)))
14476 (clobber (match_scratch:CC 3 "=X,&x,&x"))
14477 (clobber (match_scratch:DI 4 "=X,X,r"))]
14478 "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
14479 "*
14480 {
14481 if (which_alternative != 0)
14482 return \"#\";
14483 else if (get_attr_length (insn) == 4)
14484 return \"bdz %l0\";
14485 else
14486 return \"{bdn|bdnz} $+8\;b %l0\";
14487 }"
14488 [(set_attr "type" "branch")
14489 (set_attr "length" "4,12,16")])
14491 ;; Similar but use EQ
14493 (define_insn "*ctrsi_internal5"
14494 [(set (pc)
14495 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
14496 (const_int 1))
14497 (label_ref (match_operand 0 "" ""))
14498 (pc)))
14499 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
14500 (plus:SI (match_dup 1)
14501 (const_int -1)))
14502 (clobber (match_scratch:CC 3 "=X,&x,&x"))
14503 (clobber (match_scratch:SI 4 "=X,X,r"))]
14504 "! TARGET_POWERPC64"
14505 "*
14506 {
14507 if (which_alternative != 0)
14508 return \"#\";
14509 else if (get_attr_length (insn) == 4)
14510 return \"bdz %l0\";
14511 else
14512 return \"{bdn|bdnz} $+8\;b %l0\";
14513 }"
14514 [(set_attr "type" "branch")
14515 (set_attr "length" "4,12,16")])
14517 (define_insn "*ctrsi_internal6"
14518 [(set (pc)
14519 (if_then_else (eq (match_operand:SI 1 "register_operand" "c,*r,*r")
14520 (const_int 1))
14521 (pc)
14522 (label_ref (match_operand 0 "" ""))))
14523 (set (match_operand:SI 2 "register_operand" "=1,*r,m*q*c*l")
14524 (plus:SI (match_dup 1)
14525 (const_int -1)))
14526 (clobber (match_scratch:CC 3 "=X,&x,&x"))
14527 (clobber (match_scratch:SI 4 "=X,X,r"))]
14528 "! TARGET_POWERPC64"
14529 "*
14530 {
14531 if (which_alternative != 0)
14532 return \"#\";
14533 else if (get_attr_length (insn) == 4)
14534 return \"{bdn|bdnz} %l0\";
14535 else
14536 return \"bdz $+8\;b %l0\";
14537 }"
14538 [(set_attr "type" "branch")
14539 (set_attr "length" "4,12,16")])
14541 (define_insn "*ctrdi_internal5"
14542 [(set (pc)
14543 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
14544 (const_int 1))
14545 (label_ref (match_operand 0 "" ""))
14546 (pc)))
14547 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
14548 (plus:DI (match_dup 1)
14549 (const_int -1)))
14550 (clobber (match_scratch:CC 3 "=X,&x,&x"))
14551 (clobber (match_scratch:DI 4 "=X,X,r"))]
14552 "TARGET_POWERPC64"
14553 "*
14554 {
14555 if (which_alternative != 0)
14556 return \"#\";
14557 else if (get_attr_length (insn) == 4)
14558 return \"bdz %l0\";
14559 else
14560 return \"{bdn|bdnz} $+8\;b %l0\";
14561 }"
14562 [(set_attr "type" "branch")
14563 (set_attr "length" "4,12,16")])
14565 (define_insn "*ctrdi_internal6"
14566 [(set (pc)
14567 (if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
14568 (const_int 1))
14569 (pc)
14570 (label_ref (match_operand 0 "" ""))))
14571 (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
14572 (plus:DI (match_dup 1)
14573 (const_int -1)))
14574 (clobber (match_scratch:CC 3 "=X,&x,&x"))
14575 (clobber (match_scratch:DI 4 "=X,X,r"))]
14576 "TARGET_POWERPC64"
14577 "*
14578 {
14579 if (which_alternative != 0)
14580 return \"#\";
14581 else if (get_attr_length (insn) == 4)
14582 return \"{bdn|bdnz} %l0\";
14583 else
14584 return \"bdz $+8\;b %l0\";
14585 }"
14586 [(set_attr "type" "branch")
14587 (set_attr "length" "4,12,16")])
14589 ;; Now the splitters if we could not allocate the CTR register
14591 (define_split
14592 [(set (pc)
14593 (if_then_else (match_operator 2 "comparison_operator"
14594 [(match_operand:SI 1 "gpc_reg_operand" "")
14595 (const_int 1)])
14596 (match_operand 5 "" "")
14597 (match_operand 6 "" "")))
14598 (set (match_operand:SI 0 "gpc_reg_operand" "")
14599 (plus:SI (match_dup 1)
14600 (const_int -1)))
14601 (clobber (match_scratch:CC 3 ""))
14602 (clobber (match_scratch:SI 4 ""))]
14603 "! TARGET_POWERPC64 && reload_completed"
14604 [(parallel [(set (match_dup 3)
14605 (compare:CC (plus:SI (match_dup 1)
14606 (const_int -1))
14607 (const_int 0)))
14608 (set (match_dup 0)
14609 (plus:SI (match_dup 1)
14610 (const_int -1)))])
14611 (set (pc) (if_then_else (match_dup 7)
14612 (match_dup 5)
14613 (match_dup 6)))]
14614 "
14615 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14616 const0_rtx); }")
14618 (define_split
14619 [(set (pc)
14620 (if_then_else (match_operator 2 "comparison_operator"
14621 [(match_operand:SI 1 "gpc_reg_operand" "")
14622 (const_int 1)])
14623 (match_operand 5 "" "")
14624 (match_operand 6 "" "")))
14625 (set (match_operand:SI 0 "nonimmediate_operand" "")
14626 (plus:SI (match_dup 1) (const_int -1)))
14627 (clobber (match_scratch:CC 3 ""))
14628 (clobber (match_scratch:SI 4 ""))]
14629 "! TARGET_POWERPC64 && reload_completed
14630 && ! gpc_reg_operand (operands[0], SImode)"
14631 [(parallel [(set (match_dup 3)
14632 (compare:CC (plus:SI (match_dup 1)
14633 (const_int -1))
14634 (const_int 0)))
14635 (set (match_dup 4)
14636 (plus:SI (match_dup 1)
14637 (const_int -1)))])
14638 (set (match_dup 0)
14639 (match_dup 4))
14640 (set (pc) (if_then_else (match_dup 7)
14641 (match_dup 5)
14642 (match_dup 6)))]
14643 "
14644 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14645 const0_rtx); }")
14646 (define_split
14647 [(set (pc)
14648 (if_then_else (match_operator 2 "comparison_operator"
14649 [(match_operand:DI 1 "gpc_reg_operand" "")
14650 (const_int 1)])
14651 (match_operand 5 "" "")
14652 (match_operand 6 "" "")))
14653 (set (match_operand:DI 0 "gpc_reg_operand" "")
14654 (plus:DI (match_dup 1)
14655 (const_int -1)))
14656 (clobber (match_scratch:CC 3 ""))
14657 (clobber (match_scratch:DI 4 ""))]
14658 "TARGET_POWERPC64 && reload_completed"
14659 [(parallel [(set (match_dup 3)
14660 (compare:CC (plus:DI (match_dup 1)
14661 (const_int -1))
14662 (const_int 0)))
14663 (set (match_dup 0)
14664 (plus:DI (match_dup 1)
14665 (const_int -1)))])
14666 (set (pc) (if_then_else (match_dup 7)
14667 (match_dup 5)
14668 (match_dup 6)))]
14669 "
14670 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14671 const0_rtx); }")
14673 (define_split
14674 [(set (pc)
14675 (if_then_else (match_operator 2 "comparison_operator"
14676 [(match_operand:DI 1 "gpc_reg_operand" "")
14677 (const_int 1)])
14678 (match_operand 5 "" "")
14679 (match_operand 6 "" "")))
14680 (set (match_operand:DI 0 "nonimmediate_operand" "")
14681 (plus:DI (match_dup 1) (const_int -1)))
14682 (clobber (match_scratch:CC 3 ""))
14683 (clobber (match_scratch:DI 4 ""))]
14684 "TARGET_POWERPC64 && reload_completed
14685 && ! gpc_reg_operand (operands[0], DImode)"
14686 [(parallel [(set (match_dup 3)
14687 (compare:CC (plus:DI (match_dup 1)
14688 (const_int -1))
14689 (const_int 0)))
14690 (set (match_dup 4)
14691 (plus:DI (match_dup 1)
14692 (const_int -1)))])
14693 (set (match_dup 0)
14694 (match_dup 4))
14695 (set (pc) (if_then_else (match_dup 7)
14696 (match_dup 5)
14697 (match_dup 6)))]
14698 "
14699 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
14700 const0_rtx); }")
14702 \f
14703 (define_insn "trap"
14704 [(trap_if (const_int 1) (const_int 0))]
14705 ""
14706 "{t 31,0,0|trap}")
14708 (define_expand "conditional_trap"
14709 [(trap_if (match_operator 0 "trap_comparison_operator"
14710 [(match_dup 2) (match_dup 3)])
14711 (match_operand 1 "const_int_operand" ""))]
14712 ""
14713 "if (rs6000_compare_fp_p || operands[1] != const0_rtx) FAIL;
14714 operands[2] = rs6000_compare_op0;
14715 operands[3] = rs6000_compare_op1;")
14717 (define_insn ""
14718 [(trap_if (match_operator 0 "trap_comparison_operator"
14719 [(match_operand:SI 1 "register_operand" "r")
14720 (match_operand:SI 2 "reg_or_short_operand" "rI")])
14721 (const_int 0))]
14722 ""
14723 "{t|tw}%V0%I2 %1,%2")
14725 (define_insn ""
14726 [(trap_if (match_operator 0 "trap_comparison_operator"
14727 [(match_operand:DI 1 "register_operand" "r")
14728 (match_operand:DI 2 "reg_or_short_operand" "rI")])
14729 (const_int 0))]
14730 "TARGET_POWERPC64"
14731 "td%V0%I2 %1,%2")
14732 \f
14733 ;; Insns related to generating the function prologue and epilogue.
14735 (define_expand "prologue"
14736 [(use (const_int 0))]
14737 "TARGET_SCHED_PROLOG"
14738 "
14739 {
14740 rs6000_emit_prologue ();
14741 DONE;
14742 }")
14744 (define_insn "movesi_from_cr"
14745 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
14746 (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71)
14747 (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] 19))]
14748 ""
14749 "mfcr %0"
14750 [(set_attr "type" "cr_logical")])
14752 (define_insn "*stmw"
14753 [(match_parallel 0 "stmw_operation"
14754 [(set (match_operand:SI 1 "memory_operand" "=m")
14755 (match_operand:SI 2 "gpc_reg_operand" "r"))])]
14756 "TARGET_MULTIPLE"
14757 "{stm|stmw} %2,%1")
14759 (define_insn "*save_fpregs_si"
14760 [(match_parallel 0 "any_operand"
14761 [(clobber (match_operand:SI 1 "register_operand" "=l"))
14762 (use (match_operand:SI 2 "call_operand" "s"))
14763 (set (match_operand:DF 3 "memory_operand" "=m")
14764 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14765 "TARGET_32BIT"
14766 "bl %z2")
14768 (define_insn "*save_fpregs_di"
14769 [(match_parallel 0 "any_operand"
14770 [(clobber (match_operand:DI 1 "register_operand" "=l"))
14771 (use (match_operand:DI 2 "call_operand" "s"))
14772 (set (match_operand:DF 3 "memory_operand" "=m")
14773 (match_operand:DF 4 "gpc_reg_operand" "f"))])]
14774 "TARGET_64BIT"
14775 "bl %z2")
14777 ; These are to explain that changes to the stack pointer should
14778 ; not be moved over stores to stack memory.
14779 (define_insn "stack_tie"
14780 [(set (match_operand:BLK 0 "memory_operand" "+m")
14781 (unspec:BLK [(match_dup 0)] 5))]
14782 ""
14783 ""
14784 [(set_attr "length" "0")])
14787 (define_expand "epilogue"
14788 [(use (const_int 0))]
14789 "TARGET_SCHED_PROLOG"
14790 "
14791 {
14792 rs6000_emit_epilogue (FALSE);
14793 DONE;
14794 }")
14796 ; On some processors, doing the mtcrf one CC register at a time is
14797 ; faster (like on the 604e). On others, doing them all at once is
14798 ; faster; for instance, on the 601 and 750.
14800 (define_expand "movsi_to_cr_one"
14801 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14802 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14803 (match_dup 2)] 20))]
14804 ""
14805 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));")
14807 (define_insn "*movsi_to_cr"
14808 [(match_parallel 0 "mtcrf_operation"
14809 [(set (match_operand:CC 1 "cc_reg_operand" "=y")
14810 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r")
14811 (match_operand 3 "immediate_operand" "n")]
14812 20))])]
14813 ""
14814 "*
14815 {
14816 int mask = 0;
14817 int i;
14818 for (i = 0; i < XVECLEN (operands[0], 0); i++)
14819 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1));
14820 operands[4] = GEN_INT (mask);
14821 return \"mtcrf %4,%2\";
14822 }"
14823 [(set_attr "type" "cr_logical")])
14825 (define_insn ""
14826 [(set (match_operand:CC 0 "cc_reg_operand" "=y")
14827 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r")
14828 (match_operand 2 "immediate_operand" "n")] 20))]
14829 "GET_CODE (operands[0]) == REG
14830 && CR_REGNO_P (REGNO (operands[0]))
14831 && GET_CODE (operands[2]) == CONST_INT
14832 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))"
14833 "mtcrf %R0,%1"
14834 [(set_attr "type" "cr_logical")])
14836 ; The load-multiple instructions have similar properties.
14837 ; Note that "load_multiple" is a name known to the machine-independent
14838 ; code that actually corresponds to the powerpc load-string.
14840 (define_insn "*lmw"
14841 [(match_parallel 0 "lmw_operation"
14842 [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
14843 (match_operand:SI 2 "memory_operand" "m"))])]
14844 "TARGET_MULTIPLE"
14845 "{lm|lmw} %1,%2")
14847 (define_insn "*return_internal_si"
14848 [(return)
14849 (use (match_operand:SI 0 "register_operand" "lc"))]
14850 "TARGET_32BIT"
14851 "b%T0"
14852 [(set_attr "type" "jmpreg")])
14854 (define_insn "*return_internal_di"
14855 [(return)
14856 (use (match_operand:DI 0 "register_operand" "lc"))]
14857 "TARGET_64BIT"
14858 "b%T0"
14859 [(set_attr "type" "jmpreg")])
14861 ; FIXME: This would probably be somewhat simpler if the Cygnus sibcall
14862 ; stuff was in GCC. Oh, and "any_operand" is a bit flexible...
14864 (define_insn "*return_and_restore_fpregs_si"
14865 [(match_parallel 0 "any_operand"
14866 [(return)
14867 (use (match_operand:SI 1 "register_operand" "l"))
14868 (use (match_operand:SI 2 "call_operand" "s"))
14869 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14870 (match_operand:DF 4 "memory_operand" "m"))])]
14871 "TARGET_32BIT"
14872 "b %z2")
14874 (define_insn "*return_and_restore_fpregs_di"
14875 [(match_parallel 0 "any_operand"
14876 [(return)
14877 (use (match_operand:DI 1 "register_operand" "l"))
14878 (use (match_operand:DI 2 "call_operand" "s"))
14879 (set (match_operand:DF 3 "gpc_reg_operand" "=f")
14880 (match_operand:DF 4 "memory_operand" "m"))])]
14881 "TARGET_64BIT"
14882 "b %z2")
14884 ; This is used in compiling the unwind routines.
14885 (define_expand "eh_return"
14886 [(use (match_operand 0 "general_operand" ""))
14887 (use (match_operand 1 "general_operand" ""))]
14888 ""
14889 "
14890 {
14891 #if TARGET_AIX
14892 rs6000_emit_eh_toc_restore (operands[0]);
14893 #endif
14894 if (TARGET_32BIT)
14895 emit_insn (gen_eh_set_lr_si (operands[1]));
14896 else
14897 emit_insn (gen_eh_set_lr_di (operands[1]));
14898 emit_move_insn (EH_RETURN_STACKADJ_RTX, operands[0]);
14899 DONE;
14900 }")
14902 ; We can't expand this before we know where the link register is stored.
14903 (define_insn "eh_set_lr_si"
14904 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] 9)
14905 (clobber (match_scratch:SI 1 "=&b"))]
14906 "TARGET_32BIT"
14907 "#")
14909 (define_insn "eh_set_lr_di"
14910 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")] 9)
14911 (clobber (match_scratch:DI 1 "=&b"))]
14912 "TARGET_64BIT"
14913 "#")
14915 (define_split
14916 [(unspec_volatile [(match_operand 0 "register_operand" "")] 9)
14917 (clobber (match_scratch 1 ""))]
14918 "reload_completed"
14919 [(const_int 0)]
14920 "
14921 {
14922 rs6000_stack_t *info = rs6000_stack_info ();
14924 if (info->lr_save_p)
14925 {
14926 rtx frame_rtx = stack_pointer_rtx;
14927 int sp_offset = 0;
14928 rtx tmp;
14930 if (frame_pointer_needed
14931 || current_function_calls_alloca
14932 || info->total_size > 32767)
14933 {
14934 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
14935 frame_rtx = operands[1];
14936 }
14937 else if (info->push_p)
14938 sp_offset = info->total_size;
14940 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
14941 tmp = gen_rtx_MEM (Pmode, tmp);
14942 emit_move_insn (tmp, operands[0]);
14943 }
14944 else
14945 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
14946 DONE;
14947 }")
14949 (define_insn "prefetch"
14950 [(prefetch (match_operand:V4SI 0 "address_operand" "p")
14951 (match_operand:SI 1 "const_int_operand" "n")
14952 (match_operand:SI 2 "const_int_operand" "n"))]
14953 "TARGET_POWERPC"
14954 "*
14955 {
14956 if (GET_CODE (operands[0]) == REG)
14957 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\";
14958 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\";
14959 }"
14960 [(set_attr "type" "load")])
14962 (include "altivec.md")
14963 (include "spe.md")