gcc/config/i386/driver-i386.c

   1 /* Subroutines for the gcc driver.
   2    Copyright (C) 2006-2019 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 3, or (at your option)
   9 any later version.
  10
  11 GCC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 #define IN_TARGET_CODE 1
  21
  22 #include "config.h"
  23 #include "system.h"
  24 #include "coretypes.h"
  25 #include "tm.h"
  26
  27 const char *host_detect_local_cpu (int argc, const char **argv);
  28
  29 #if defined(__GNUC__) && (__GNUC__ >= 5 || !defined(__PIC__))
  30 #include "cpuid.h"
  31
  32 struct cache_desc
  33 {
  34   unsigned sizekb;
  35   unsigned assoc;
  36   unsigned line;
  37 };
  38
  39 /* Returns command line parameters that describe size and
  40    cache line size of the processor caches.  */
  41
  42 static char *
  43 describe_cache (struct cache_desc level1, struct cache_desc level2)
  44 {
  45   char size[100], line[100], size2[100];
  46
  47   /* At the moment, gcc does not use the information
  48      about the associativity of the cache.  */
  49
  50   snprintf (size, sizeof (size),
  51             "--param l1-cache-size=%u ", level1.sizekb);
  52   snprintf (line, sizeof (line),
  53             "--param l1-cache-line-size=%u ", level1.line);
  54
  55   snprintf (size2, sizeof (size2),
  56             "--param l2-cache-size=%u ", level2.sizekb);
  57
  58   return concat (size, line, size2, NULL);
  59 }
  60
  61 /* Detect L2 cache parameters using CPUID extended function 0x80000006.  */
  62
  63 static void
  64 detect_l2_cache (struct cache_desc *level2)
  65 {
  66   unsigned eax, ebx, ecx, edx;
  67   unsigned assoc;
  68
  69   __cpuid (0x80000006, eax, ebx, ecx, edx);
  70
  71   level2->sizekb = (ecx >> 16) & 0xffff;
  72   level2->line = ecx & 0xff;
  73
  74   assoc = (ecx >> 12) & 0xf;
  75   if (assoc == 6)
  76     assoc = 8;
  77   else if (assoc == 8)
  78     assoc = 16;
  79   else if (assoc >= 0xa && assoc <= 0xc)
  80     assoc = 32 + (assoc - 0xa) * 16;
  81   else if (assoc >= 0xd && assoc <= 0xe)
  82     assoc = 96 + (assoc - 0xd) * 32;
  83
  84   level2->assoc = assoc;
  85 }
  86
  87 /* Returns the description of caches for an AMD processor.  */
  88
  89 static const char *
  90 detect_caches_amd (unsigned max_ext_level)
  91 {
  92   unsigned eax, ebx, ecx, edx;
  93
  94   struct cache_desc level1, level2 = {0, 0, 0};
  95
  96   if (max_ext_level < 0x80000005)
  97     return "";
  98
  99   __cpuid (0x80000005, eax, ebx, ecx, edx);
 100
 101   level1.sizekb = (ecx >> 24) & 0xff;
 102   level1.assoc = (ecx >> 16) & 0xff;
 103   level1.line = ecx & 0xff;
 104
 105   if (max_ext_level >= 0x80000006)
 106     detect_l2_cache (&level2);
 107
 108   return describe_cache (level1, level2);
 109 }
 110
 111 /* Decodes the size, the associativity and the cache line size of
 112    L1/L2 caches of an Intel processor.  Values are based on
 113    "Intel Processor Identification and the CPUID Instruction"
 114    [Application Note 485], revision -032, December 2007.  */
 115
 116 static void
 117 decode_caches_intel (unsigned reg, bool xeon_mp,
 118                      struct cache_desc *level1, struct cache_desc *level2)
 119 {
 120   int i;
 121
 122   for (i = 24; i >= 0; i -= 8)
 123     switch ((reg >> i) & 0xff)
 124       {
 125       case 0x0a:
 126         level1->sizekb = 8; level1->assoc = 2; level1->line = 32;
 127         break;
 128       case 0x0c:
 129         level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
 130         break;
 131       case 0x0d:
 132         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 133         break;
 134       case 0x0e:
 135         level1->sizekb = 24; level1->assoc = 6; level1->line = 64;
 136         break;
 137       case 0x21:
 138         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 139         break;
 140       case 0x24:
 141         level2->sizekb = 1024; level2->assoc = 16; level2->line = 64;
 142         break;
 143       case 0x2c:
 144         level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
 145         break;
 146       case 0x39:
 147         level2->sizekb = 128; level2->assoc = 4; level2->line = 64;
 148         break;
 149       case 0x3a:
 150         level2->sizekb = 192; level2->assoc = 6; level2->line = 64;
 151         break;
 152       case 0x3b:
 153         level2->sizekb = 128; level2->assoc = 2; level2->line = 64;
 154         break;
 155       case 0x3c:
 156         level2->sizekb = 256; level2->assoc = 4; level2->line = 64;
 157         break;
 158       case 0x3d:
 159         level2->sizekb = 384; level2->assoc = 6; level2->line = 64;
 160         break;
 161       case 0x3e:
 162         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 163         break;
 164       case 0x41:
 165         level2->sizekb = 128; level2->assoc = 4; level2->line = 32;
 166         break;
 167       case 0x42:
 168         level2->sizekb = 256; level2->assoc = 4; level2->line = 32;
 169         break;
 170       case 0x43:
 171         level2->sizekb = 512; level2->assoc = 4; level2->line = 32;
 172         break;
 173       case 0x44:
 174         level2->sizekb = 1024; level2->assoc = 4; level2->line = 32;
 175         break;
 176       case 0x45:
 177         level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
 178         break;
 179       case 0x48:
 180         level2->sizekb = 3072; level2->assoc = 12; level2->line = 64;
 181         break;
 182       case 0x49:
 183         if (xeon_mp)
 184           break;
 185         level2->sizekb = 4096; level2->assoc = 16; level2->line = 64;
 186         break;
 187       case 0x4e:
 188         level2->sizekb = 6144; level2->assoc = 24; level2->line = 64;
 189         break;
 190       case 0x60:
 191         level1->sizekb = 16; level1->assoc = 8; level1->line = 64;
 192         break;
 193       case 0x66:
 194         level1->sizekb = 8; level1->assoc = 4; level1->line = 64;
 195         break;
 196       case 0x67:
 197         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 198         break;
 199       case 0x68:
 200         level1->sizekb = 32; level1->assoc = 4; level1->line = 64;
 201         break;
 202       case 0x78:
 203         level2->sizekb = 1024; level2->assoc = 4; level2->line = 64;
 204         break;
 205       case 0x79:
 206         level2->sizekb = 128; level2->assoc = 8; level2->line = 64;
 207         break;
 208       case 0x7a:
 209         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 210         break;
 211       case 0x7b:
 212         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 213         break;
 214       case 0x7c:
 215         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 216         break;
 217       case 0x7d:
 218         level2->sizekb = 2048; level2->assoc = 8; level2->line = 64;
 219         break;
 220       case 0x7f:
 221         level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
 222         break;
 223       case 0x80:
 224         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 225         break;
 226       case 0x82:
 227         level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
 228         break;
 229       case 0x83:
 230         level2->sizekb = 512; level2->assoc = 8; level2->line = 32;
 231         break;
 232       case 0x84:
 233         level2->sizekb = 1024; level2->assoc = 8; level2->line = 32;
 234         break;
 235       case 0x85:
 236         level2->sizekb = 2048; level2->assoc = 8; level2->line = 32;
 237         break;
 238       case 0x86:
 239         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 240         break;
 241       case 0x87:
 242         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 243
 244       default:
 245         break;
 246       }
 247 }
 248
 249 /* Detect cache parameters using CPUID function 2.  */
 250
 251 static void
 252 detect_caches_cpuid2 (bool xeon_mp,
 253                       struct cache_desc *level1, struct cache_desc *level2)
 254 {
 255   unsigned regs[4];
 256   int nreps, i;
 257
 258   __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 259
 260   nreps = regs[0] & 0x0f;
 261   regs[0] &= ~0x0f;
 262
 263   while (--nreps >= 0)
 264     {
 265       for (i = 0; i < 4; i++)
 266         if (regs[i] && !((regs[i] >> 31) & 1))
 267           decode_caches_intel (regs[i], xeon_mp, level1, level2);
 268
 269       if (nreps)
 270         __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 271     }
 272 }
 273
 274 /* Detect cache parameters using CPUID function 4. This
 275    method doesn't require hardcoded tables.  */
 276
 277 enum cache_type
 278 {
 279   CACHE_END = 0,
 280   CACHE_DATA = 1,
 281   CACHE_INST = 2,
 282   CACHE_UNIFIED = 3
 283 };
 284
 285 static void
 286 detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2,
 287                       struct cache_desc *level3)
 288 {
 289   struct cache_desc *cache;
 290
 291   unsigned eax, ebx, ecx, edx;
 292   int count;
 293
 294   for (count = 0;; count++)
 295     {
 296       __cpuid_count(4, count, eax, ebx, ecx, edx);
 297       switch (eax & 0x1f)
 298         {
 299         case CACHE_END:
 300           return;
 301         case CACHE_DATA:
 302         case CACHE_UNIFIED:
 303           {
 304             switch ((eax >> 5) & 0x07)
 305               {
 306               case 1:
 307                 cache = level1;
 308                 break;
 309               case 2:
 310                 cache = level2;
 311                 break;
 312               case 3:
 313                 cache = level3;
 314                 break;
 315               default:
 316                 cache = NULL;
 317               }
 318
 319             if (cache)
 320               {
 321                 unsigned sets = ecx + 1;
 322                 unsigned part = ((ebx >> 12) & 0x03ff) + 1;
 323
 324                 cache->assoc = ((ebx >> 22) & 0x03ff) + 1;
 325                 cache->line = (ebx & 0x0fff) + 1;
 326
 327                 cache->sizekb = (cache->assoc * part
 328                                  * cache->line * sets) / 1024;
 329               }
 330           }
 331         default:
 332           break;
 333         }
 334     }
 335 }
 336
 337 /* Returns the description of caches for an Intel processor.  */
 338
 339 static const char *
 340 detect_caches_intel (bool xeon_mp, unsigned max_level,
 341                      unsigned max_ext_level, unsigned *l2sizekb)
 342 {
 343   struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0};
 344
 345   if (max_level >= 4)
 346     detect_caches_cpuid4 (&level1, &level2, &level3);
 347   else if (max_level >= 2)
 348     detect_caches_cpuid2 (xeon_mp, &level1, &level2);
 349   else
 350     return "";
 351
 352   if (level1.sizekb == 0)
 353     return "";
 354
 355   /* Let the L3 replace the L2. This assumes inclusive caches
 356      and single threaded program for now. */
 357   if (level3.sizekb)
 358     level2 = level3;
 359
 360   /* Intel CPUs are equipped with AMD style L2 cache info.  Try this
 361      method if other methods fail to provide L2 cache parameters.  */
 362   if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
 363     detect_l2_cache (&level2);
 364
 365   *l2sizekb = level2.sizekb;
 366
 367   return describe_cache (level1, level2);
 368 }
 369
 370 /* This will be called by the spec parser in gcc.c when it sees
 371    a %:local_cpu_detect(args) construct.  Currently it will be called
 372    with either "arch" or "tune" as argument depending on if -march=native
 373    or -mtune=native is to be substituted.
 374
 375    It returns a string containing new command line parameters to be
 376    put at the place of the above two options, depending on what CPU
 377    this is executed.  E.g. "-march=k8" on an AMD64 machine
 378    for -march=native.
 379
 380    ARGC and ARGV are set depending on the actual arguments given
 381    in the spec.  */
 382
 383 const char *host_detect_local_cpu (int argc, const char **argv)
 384 {
 385   enum processor_type processor = PROCESSOR_I386;
 386   const char *cpu = "i386";
 387
 388   const char *cache = "";
 389   const char *options = "";
 390
 391   unsigned int eax, ebx, ecx, edx;
 392
 393   unsigned int max_level, ext_level;
 394
 395   unsigned int vendor;
 396   unsigned int model, family;
 397
 398   unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
 399   unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;
 400
 401   /* Extended features */
 402   unsigned int has_lahf_lm = 0, has_sse4a = 0;
 403   unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
 404   unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
 405   unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0, has_avx2 = 0;
 406   unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
 407   unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0;
 408   unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
 409   unsigned int has_hle = 0, has_rtm = 0, has_sgx = 0;
 410   unsigned int has_pconfig = 0, has_wbnoinvd = 0;
 411   unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
 412   unsigned int has_rdseed = 0, has_prfchw = 0, has_adx = 0;
 413   unsigned int has_osxsave = 0, has_fxsr = 0, has_xsave = 0, has_xsaveopt = 0;
 414   unsigned int has_avx512er = 0, has_avx512pf = 0, has_avx512cd = 0;
 415   unsigned int has_avx512f = 0, has_sha = 0, has_prefetchwt1 = 0;
 416   unsigned int has_clflushopt = 0, has_xsavec = 0, has_xsaves = 0;
 417   unsigned int has_avx512dq = 0, has_avx512bw = 0, has_avx512vl = 0;
 418   unsigned int has_avx512vbmi = 0, has_avx512ifma = 0, has_clwb = 0;
 419   unsigned int has_mwaitx = 0, has_clzero = 0, has_pku = 0, has_rdpid = 0;
 420   unsigned int has_avx5124fmaps = 0, has_avx5124vnniw = 0;
 421   unsigned int has_gfni = 0, has_avx512vbmi2 = 0;
 422   unsigned int has_avx512bitalg = 0;
 423   unsigned int has_shstk = 0;
 424   unsigned int has_avx512vnni = 0, has_vaes = 0;
 425   unsigned int has_vpclmulqdq = 0;
 426   unsigned int has_movdiri = 0, has_movdir64b = 0;
 427   unsigned int has_enqcmd = 0;
 428   unsigned int has_waitpkg = 0;
 429   unsigned int has_cldemote = 0;
 430   unsigned int has_avx512bf16 = 0;
 431
 432   unsigned int has_ptwrite = 0;
 433
 434   bool arch;
 435
 436   unsigned int l2sizekb = 0;
 437
 438   if (argc < 1)
 439     return NULL;
 440
 441   arch = !strcmp (argv[0], "arch");
 442
 443   if (!arch && strcmp (argv[0], "tune"))
 444     return NULL;
 445
 446   max_level = __get_cpuid_max (0, &vendor);
 447   if (max_level < 1)
 448     goto done;
 449
 450   __cpuid (1, eax, ebx, ecx, edx);
 451
 452   model = (eax >> 4) & 0x0f;
 453   family = (eax >> 8) & 0x0f;
 454   if (vendor == signature_INTEL_ebx
 455       || vendor == signature_AMD_ebx)
 456     {
 457       unsigned int extended_model, extended_family;
 458
 459       extended_model = (eax >> 12) & 0xf0;
 460       extended_family = (eax >> 20) & 0xff;
 461       if (family == 0x0f)
 462         {
 463           family += extended_family;
 464           model += extended_model;
 465         }
 466       else if (family == 0x06)
 467         model += extended_model;
 468     }
 469
 470   has_sse3 = ecx & bit_SSE3;
 471   has_ssse3 = ecx & bit_SSSE3;
 472   has_sse4_1 = ecx & bit_SSE4_1;
 473   has_sse4_2 = ecx & bit_SSE4_2;
 474   has_avx = ecx & bit_AVX;
 475   has_osxsave = ecx & bit_OSXSAVE;
 476   has_cmpxchg16b = ecx & bit_CMPXCHG16B;
 477   has_movbe = ecx & bit_MOVBE;
 478   has_popcnt = ecx & bit_POPCNT;
 479   has_aes = ecx & bit_AES;
 480   has_pclmul = ecx & bit_PCLMUL;
 481   has_fma = ecx & bit_FMA;
 482   has_f16c = ecx & bit_F16C;
 483   has_rdrnd = ecx & bit_RDRND;
 484   has_xsave = ecx & bit_XSAVE;
 485
 486   has_cmpxchg8b = edx & bit_CMPXCHG8B;
 487   has_cmov = edx & bit_CMOV;
 488   has_mmx = edx & bit_MMX;
 489   has_fxsr = edx & bit_FXSAVE;
 490   has_sse = edx & bit_SSE;
 491   has_sse2 = edx & bit_SSE2;
 492
 493   if (max_level >= 7)
 494     {
 495       __cpuid_count (7, 0, eax, ebx, ecx, edx);
 496
 497       has_bmi = ebx & bit_BMI;
 498       has_sgx = ebx & bit_SGX;
 499       has_hle = ebx & bit_HLE;
 500       has_rtm = ebx & bit_RTM;
 501       has_avx2 = ebx & bit_AVX2;
 502       has_bmi2 = ebx & bit_BMI2;
 503       has_fsgsbase = ebx & bit_FSGSBASE;
 504       has_rdseed = ebx & bit_RDSEED;
 505       has_adx = ebx & bit_ADX;
 506       has_avx512f = ebx & bit_AVX512F;
 507       has_avx512er = ebx & bit_AVX512ER;
 508       has_avx512pf = ebx & bit_AVX512PF;
 509       has_avx512cd = ebx & bit_AVX512CD;
 510       has_sha = ebx & bit_SHA;
 511       has_clflushopt = ebx & bit_CLFLUSHOPT;
 512       has_clwb = ebx & bit_CLWB;
 513       has_avx512dq = ebx & bit_AVX512DQ;
 514       has_avx512bw = ebx & bit_AVX512BW;
 515       has_avx512vl = ebx & bit_AVX512VL;
 516       has_avx512ifma = ebx & bit_AVX512IFMA;
 517
 518       has_prefetchwt1 = ecx & bit_PREFETCHWT1;
 519       has_avx512vbmi = ecx & bit_AVX512VBMI;
 520       has_pku = ecx & bit_OSPKE;
 521       has_avx512vbmi2 = ecx & bit_AVX512VBMI2;
 522       has_avx512vnni = ecx & bit_AVX512VNNI;
 523       has_rdpid = ecx & bit_RDPID;
 524       has_gfni = ecx & bit_GFNI;
 525       has_vaes = ecx & bit_VAES;
 526       has_vpclmulqdq = ecx & bit_VPCLMULQDQ;
 527       has_avx512bitalg = ecx & bit_AVX512BITALG;
 528       has_movdiri = ecx & bit_MOVDIRI;
 529       has_movdir64b = ecx & bit_MOVDIR64B;
 530       has_enqcmd = ecx & bit_ENQCMD;
 531       has_cldemote = ecx & bit_CLDEMOTE;
 532
 533       has_avx5124vnniw = edx & bit_AVX5124VNNIW;
 534       has_avx5124fmaps = edx & bit_AVX5124FMAPS;
 535
 536       has_shstk = ecx & bit_SHSTK;
 537       has_pconfig = edx & bit_PCONFIG;
 538       has_waitpkg = ecx & bit_WAITPKG;
 539
 540       __cpuid_count (7, 1, eax, ebx, ecx, edx);
 541       has_avx512bf16 = eax & bit_AVX512BF16;
 542     }
 543
 544   if (max_level >= 13)
 545     {
 546       __cpuid_count (13, 1, eax, ebx, ecx, edx);
 547
 548       has_xsaveopt = eax & bit_XSAVEOPT;
 549       has_xsavec = eax & bit_XSAVEC;
 550       has_xsaves = eax & bit_XSAVES;
 551     }
 552
 553   if (max_level >= 0x14)
 554     {
 555       __cpuid_count (0x14, 0, eax, ebx, ecx, edx);
 556
 557       has_ptwrite = ebx & bit_PTWRITE;
 558     }
 559
 560   /* Check cpuid level of extended features.  */
 561   __cpuid (0x80000000, ext_level, ebx, ecx, edx);
 562
 563   if (ext_level >= 0x80000001)
 564     {
 565       __cpuid (0x80000001, eax, ebx, ecx, edx);
 566
 567       has_lahf_lm = ecx & bit_LAHF_LM;
 568       has_sse4a = ecx & bit_SSE4a;
 569       has_abm = ecx & bit_ABM;
 570       has_lwp = ecx & bit_LWP;
 571       has_fma4 = ecx & bit_FMA4;
 572       has_xop = ecx & bit_XOP;
 573       has_tbm = ecx & bit_TBM;
 574       has_lzcnt = ecx & bit_LZCNT;
 575       has_prfchw = ecx & bit_PRFCHW;
 576
 577       has_longmode = edx & bit_LM;
 578       has_3dnowp = edx & bit_3DNOWP;
 579       has_3dnow = edx & bit_3DNOW;
 580       has_mwaitx = ecx & bit_MWAITX;
 581     }
 582
 583   if (ext_level >= 0x80000008)
 584     {
 585       __cpuid (0x80000008, eax, ebx, ecx, edx);
 586       has_clzero = ebx & bit_CLZERO;
 587       has_wbnoinvd = ebx & bit_WBNOINVD;
 588     }
 589
 590   /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv.  */
 591 #define XCR_XFEATURE_ENABLED_MASK       0x0
 592 #define XSTATE_FP                       0x1
 593 #define XSTATE_SSE                      0x2
 594 #define XSTATE_YMM                      0x4
 595 #define XSTATE_OPMASK                   0x20
 596 #define XSTATE_ZMM                      0x40
 597 #define XSTATE_HI_ZMM                   0x80
 598
 599 #define XCR_AVX_ENABLED_MASK \
 600   (XSTATE_SSE | XSTATE_YMM)
 601 #define XCR_AVX512F_ENABLED_MASK \
 602   (XSTATE_SSE | XSTATE_YMM | XSTATE_OPMASK | XSTATE_ZMM | XSTATE_HI_ZMM)
 603
 604   if (has_osxsave)
 605     asm (".byte 0x0f; .byte 0x01; .byte 0xd0"
 606          : "=a" (eax), "=d" (edx)
 607          : "c" (XCR_XFEATURE_ENABLED_MASK));
 608   else
 609     eax = 0;
 610
 611   /* Check if AVX registers are supported.  */
 612   if ((eax & XCR_AVX_ENABLED_MASK) != XCR_AVX_ENABLED_MASK)
 613     {
 614       has_avx = 0;
 615       has_avx2 = 0;
 616       has_fma = 0;
 617       has_fma4 = 0;
 618       has_f16c = 0;
 619       has_xop = 0;
 620       has_xsave = 0;
 621       has_xsaveopt = 0;
 622       has_xsaves = 0;
 623       has_xsavec = 0;
 624     }
 625
 626   /* Check if AVX512F registers are supported.  */
 627   if ((eax & XCR_AVX512F_ENABLED_MASK) != XCR_AVX512F_ENABLED_MASK)
 628     {
 629       has_avx512f = 0;
 630       has_avx512er = 0;
 631       has_avx512pf = 0;
 632       has_avx512cd = 0;
 633       has_avx512dq = 0;
 634       has_avx512bw = 0;
 635       has_avx512vl = 0;
 636     }
 637
 638   if (!arch)
 639     {
 640       if (vendor == signature_AMD_ebx
 641           || vendor == signature_CENTAUR_ebx
 642           || vendor == signature_CYRIX_ebx
 643           || vendor == signature_NSC_ebx)
 644         cache = detect_caches_amd (ext_level);
 645       else if (vendor == signature_INTEL_ebx)
 646         {
 647           bool xeon_mp = (family == 15 && model == 6);
 648           cache = detect_caches_intel (xeon_mp, max_level,
 649                                        ext_level, &l2sizekb);
 650         }
 651     }
 652
 653   if (vendor == signature_AMD_ebx)
 654     {
 655       unsigned int name;
 656
 657       /* Detect geode processor by its processor signature.  */
 658       if (ext_level >= 0x80000002)
 659         __cpuid (0x80000002, name, ebx, ecx, edx);
 660       else
 661         name = 0;
 662
 663       if (name == signature_NSC_ebx)
 664         processor = PROCESSOR_GEODE;
 665       else if (has_movbe && family == 22)
 666         processor = PROCESSOR_BTVER2;
 667       else if (has_clwb)
 668         processor = PROCESSOR_ZNVER2;
 669       else if (has_clzero)
 670         processor = PROCESSOR_ZNVER1;
 671       else if (has_avx2)
 672         processor = PROCESSOR_BDVER4;
 673       else if (has_xsaveopt)
 674         processor = PROCESSOR_BDVER3;
 675       else if (has_bmi)
 676         processor = PROCESSOR_BDVER2;
 677       else if (has_xop)
 678         processor = PROCESSOR_BDVER1;
 679       else if (has_sse4a && has_ssse3)
 680         processor = PROCESSOR_BTVER1;
 681       else if (has_sse4a)
 682         processor = PROCESSOR_AMDFAM10;
 683       else if (has_sse2 || has_longmode)
 684         processor = PROCESSOR_K8;
 685       else if (has_3dnowp && family == 6)
 686         processor = PROCESSOR_ATHLON;
 687       else if (has_mmx)
 688         processor = PROCESSOR_K6;
 689       else
 690         processor = PROCESSOR_PENTIUM;
 691     }
 692   else if (vendor == signature_CENTAUR_ebx)
 693     {
 694       processor = PROCESSOR_GENERIC;
 695
 696       switch (family)
 697         {
 698         default:
 699           /* We have no idea.  */
 700           break;
 701
 702         case 5:
 703           if (has_3dnow || has_mmx)
 704             processor = PROCESSOR_I486;
 705           break;
 706
 707         case 6:
 708           if (has_longmode)
 709             processor = PROCESSOR_K8;
 710           else if (model >= 9)
 711             processor = PROCESSOR_PENTIUMPRO;
 712           else if (model >= 6)
 713             processor = PROCESSOR_I486;
 714         }
 715     }
 716   else
 717     {
 718       switch (family)
 719         {
 720         case 4:
 721           processor = PROCESSOR_I486;
 722           break;
 723         case 5:
 724           processor = PROCESSOR_PENTIUM;
 725           break;
 726         case 6:
 727           processor = PROCESSOR_PENTIUMPRO;
 728           break;
 729         case 15:
 730           processor = PROCESSOR_PENTIUM4;
 731           break;
 732         default:
 733           /* We have no idea.  */
 734           processor = PROCESSOR_GENERIC;
 735         }
 736     }
 737
 738   switch (processor)
 739     {
 740     case PROCESSOR_I386:
 741       /* Default.  */
 742       break;
 743     case PROCESSOR_I486:
 744       if (arch && vendor == signature_CENTAUR_ebx)
 745         {
 746           if (model >= 6)
 747             cpu = "c3";
 748           else if (has_3dnow)
 749             cpu = "winchip2";
 750           else
 751             /* Assume WinChip C6.  */
 752             cpu = "winchip-c6";
 753         }
 754       else
 755         cpu = "i486";
 756       break;
 757     case PROCESSOR_PENTIUM:
 758       if (arch && has_mmx)
 759         cpu = "pentium-mmx";
 760       else
 761         cpu = "pentium";
 762       break;
 763     case PROCESSOR_PENTIUMPRO:
 764       switch (model)
 765         {
 766         case 0x1c:
 767         case 0x26:
 768           /* Bonnell.  */
 769           cpu = "bonnell";
 770           break;
 771         case 0x37:
 772         case 0x4a:
 773         case 0x4d:
 774         case 0x5a:
 775         case 0x5d:
 776           /* Silvermont.  */
 777           cpu = "silvermont";
 778           break;
 779         case 0x5c:
 780         case 0x5f:
 781           /* Goldmont.  */
 782           cpu = "goldmont";
 783           break;
 784         case 0x7a:
 785           /* Goldmont Plus.  */
 786           cpu = "goldmont-plus";
 787           break;
 788         case 0x0f:
 789           /* Merom.  */
 790         case 0x17:
 791         case 0x1d:
 792           /* Penryn.  */
 793           cpu = "core2";
 794           break;
 795         case 0x1a:
 796         case 0x1e:
 797         case 0x1f:
 798         case 0x2e:
 799           /* Nehalem.  */
 800           cpu = "nehalem";
 801           break;
 802         case 0x25:
 803         case 0x2c:
 804         case 0x2f:
 805           /* Westmere.  */
 806           cpu = "westmere";
 807           break;
 808         case 0x2a:
 809         case 0x2d:
 810           /* Sandy Bridge.  */
 811           cpu = "sandybridge";
 812           break;
 813         case 0x3a:
 814         case 0x3e:
 815           /* Ivy Bridge.  */
 816           cpu = "ivybridge";
 817           break;
 818         case 0x3c:
 819         case 0x3f:
 820         case 0x45:
 821         case 0x46:
 822           /* Haswell.  */
 823           cpu = "haswell";
 824           break;
 825         case 0x3d:
 826         case 0x47:
 827         case 0x4f:
 828         case 0x56:
 829           /* Broadwell.  */
 830           cpu = "broadwell";
 831           break;
 832         case 0x4e:
 833         case 0x5e:
 834           /* Skylake.  */
 835         case 0x8e:
 836         case 0x9e:
 837           /* Kaby Lake.  */
 838           cpu = "skylake";
 839           break;
 840         case 0x55:
 841           if (has_avx512vnni)
 842             /* Cascade Lake.  */
 843             cpu = "cascadelake";
 844           else
 845             /* Skylake with AVX-512.  */
 846             cpu = "skylake-avx512";
 847           break;
 848         case 0x57:
 849           /* Knights Landing.  */
 850           cpu = "knl";
 851           break;
 852         case 0x66:
 853           /* Cannon Lake.  */
 854           cpu = "cannonlake";
 855           break;
 856         case 0x85:
 857           /* Knights Mill.  */
 858           cpu = "knm";
 859           break;
 860         default:
 861           if (arch)
 862             {
 863               /* This is unknown family 0x6 CPU.  */
 864               /* Assume Ice Lake Server.  */
 865               if (has_wbnoinvd)
 866                 cpu = "icelake-server";
 867               /* Assume Ice Lake.  */
 868               else if (has_gfni)
 869                 cpu = "icelake-client";
 870               /* Assume Cannon Lake.  */
 871               else if (has_avx512vbmi)
 872                 cpu = "cannonlake";
 873               /* Assume Knights Mill.  */
 874               else if (has_avx5124vnniw)
 875                 cpu = "knm";
 876               /* Assume Knights Landing.  */
 877               else if (has_avx512er)
 878                 cpu = "knl";
 879               /* Assume Skylake with AVX-512.  */
 880               else if (has_avx512f)
 881                 cpu = "skylake-avx512";
 882               /* Assume Skylake.  */
 883               else if (has_clflushopt)
 884                 cpu = "skylake";
 885               /* Assume Broadwell.  */
 886               else if (has_adx)
 887                 cpu = "broadwell";
 888               else if (has_avx2)
 889                 /* Assume Haswell.  */
 890                 cpu = "haswell";
 891               else if (has_avx)
 892                 /* Assume Sandy Bridge.  */
 893                 cpu = "sandybridge";
 894               else if (has_sse4_2)
 895                 {
 896                   if (has_gfni)
 897                     /* Assume Tremont.  */
 898                     cpu = "tremont";
 899                   else if (has_sgx)
 900                     /* Assume Goldmont Plus.  */
 901                     cpu = "goldmont-plus";
 902                   else if (has_xsave)
 903                     /* Assume Goldmont.  */
 904                     cpu = "goldmont";
 905                   else if (has_movbe)
 906                     /* Assume Silvermont.  */
 907                     cpu = "silvermont";
 908                   else
 909                     /* Assume Nehalem.  */
 910                     cpu = "nehalem";
 911                 }
 912               else if (has_ssse3)
 913                 {
 914                   if (has_movbe)
 915                     /* Assume Bonnell.  */
 916                     cpu = "bonnell";
 917                   else
 918                     /* Assume Core 2.  */
 919                     cpu = "core2";
 920                 }
 921               else if (has_longmode)
 922                 /* Perhaps some emulator?  Assume x86-64, otherwise gcc
 923                    -march=native would be unusable for 64-bit compilations,
 924                    as all the CPUs below are 32-bit only.  */
 925                 cpu = "x86-64";
 926               else if (has_sse3)
 927                 {
 928                   if (vendor == signature_CENTAUR_ebx)
 929                     /* C7 / Eden "Esther" */
 930                     cpu = "c7";
 931                   else
 932                     /* It is Core Duo.  */
 933                     cpu = "pentium-m";
 934                 }
 935               else if (has_sse2)
 936                 /* It is Pentium M.  */
 937                 cpu = "pentium-m";
 938               else if (has_sse)
 939                 {
 940                   if (vendor == signature_CENTAUR_ebx)
 941                     {
 942                       if (model >= 9)
 943                         /* Eden "Nehemiah" */
 944                         cpu = "nehemiah";
 945                       else
 946                         cpu = "c3-2";
 947                     }
 948                   else
 949                     /* It is Pentium III.  */
 950                     cpu = "pentium3";
 951                 }
 952               else if (has_mmx)
 953                 /* It is Pentium II.  */
 954                 cpu = "pentium2";
 955               else
 956                 /* Default to Pentium Pro.  */
 957                 cpu = "pentiumpro";
 958             }
 959           else
 960             /* For -mtune, we default to -mtune=generic.  */
 961             cpu = "generic";
 962           break;
 963         }
 964       break;
 965     case PROCESSOR_PENTIUM4:
 966       if (has_sse3)
 967         {
 968           if (has_longmode)
 969             cpu = "nocona";
 970           else
 971             cpu = "prescott";
 972         }
 973       else
 974         cpu = "pentium4";
 975       break;
 976     case PROCESSOR_GEODE:
 977       cpu = "geode";
 978       break;
 979     case PROCESSOR_K6:
 980       if (arch && has_3dnow)
 981         cpu = "k6-3";
 982       else
 983         cpu = "k6";
 984       break;
 985     case PROCESSOR_ATHLON:
 986       if (arch && has_sse)
 987         cpu = "athlon-4";
 988       else
 989         cpu = "athlon";
 990       break;
 991     case PROCESSOR_K8:
 992       if (arch)
 993         {
 994           if (vendor == signature_CENTAUR_ebx)
 995             {
 996               if (has_sse4_1)
 997                 /* Nano 3000 | Nano dual / quad core | Eden X4 */
 998                 cpu = "nano-3000";
 999               else if (has_ssse3)
1000                 /* Nano 1000 | Nano 2000 */
1001                 cpu = "nano";
1002               else if (has_sse3)
1003                 /* Eden X2 */
1004                 cpu = "eden-x2";
1005               else
1006                 /* Default to k8 */
1007                 cpu = "k8";
1008             }
1009           else if (has_sse3)
1010             cpu = "k8-sse3";
1011           else
1012             cpu = "k8";
1013         }
1014       else
1015         /* For -mtune, we default to -mtune=k8 */
1016         cpu = "k8";
1017       break;
1018     case PROCESSOR_AMDFAM10:
1019       cpu = "amdfam10";
1020       break;
1021     case PROCESSOR_BDVER1:
1022       cpu = "bdver1";
1023       break;
1024     case PROCESSOR_BDVER2:
1025       cpu = "bdver2";
1026       break;
1027     case PROCESSOR_BDVER3:
1028       cpu = "bdver3";
1029       break;
1030     case PROCESSOR_BDVER4:
1031       cpu = "bdver4";
1032       break;
1033     case PROCESSOR_ZNVER1:
1034       cpu = "znver1";
1035       break;
1036     case PROCESSOR_ZNVER2:
1037       cpu = "znver2";
1038       break;
1039     case PROCESSOR_BTVER1:
1040       cpu = "btver1";
1041       break;
1042     case PROCESSOR_BTVER2:
1043       cpu = "btver2";
1044       break;
1045
1046     default:
1047       /* Use something reasonable.  */
1048       if (arch)
1049         {
1050           if (has_ssse3)
1051             cpu = "core2";
1052           else if (has_sse3)
1053             {
1054               if (has_longmode)
1055                 cpu = "nocona";
1056               else
1057                 cpu = "prescott";
1058             }
1059           else if (has_longmode)
1060             /* Perhaps some emulator?  Assume x86-64, otherwise gcc
1061                -march=native would be unusable for 64-bit compilations,
1062                as all the CPUs below are 32-bit only.  */
1063             cpu = "x86-64";
1064           else if (has_sse2)
1065             cpu = "pentium4";
1066           else if (has_cmov)
1067             cpu = "pentiumpro";
1068           else if (has_mmx)
1069             cpu = "pentium-mmx";
1070           else if (has_cmpxchg8b)
1071             cpu = "pentium";
1072         }
1073       else
1074         cpu = "generic";
1075     }
1076
1077   if (arch)
1078     {
1079       const char *mmx = has_mmx ? " -mmmx" : " -mno-mmx";
1080       const char *mmx3dnow = has_3dnow ? " -m3dnow" : " -mno-3dnow";
1081       const char *sse = has_sse ? " -msse" : " -mno-sse";
1082       const char *sse2 = has_sse2 ? " -msse2" : " -mno-sse2";
1083       const char *sse3 = has_sse3 ? " -msse3" : " -mno-sse3";
1084       const char *ssse3 = has_ssse3 ? " -mssse3" : " -mno-ssse3";
1085       const char *sse4a = has_sse4a ? " -msse4a" : " -mno-sse4a";
1086       const char *cx16 = has_cmpxchg16b ? " -mcx16" : " -mno-cx16";
1087       const char *sahf = has_lahf_lm ? " -msahf" : " -mno-sahf";
1088       const char *movbe = has_movbe ? " -mmovbe" : " -mno-movbe";
1089       const char *aes = has_aes ? " -maes" : " -mno-aes";
1090       const char *sha = has_sha ? " -msha" : " -mno-sha";
1091       const char *pclmul = has_pclmul ? " -mpclmul" : " -mno-pclmul";
1092       const char *popcnt = has_popcnt ? " -mpopcnt" : " -mno-popcnt";
1093       const char *abm = has_abm ? " -mabm" : " -mno-abm";
1094       const char *lwp = has_lwp ? " -mlwp" : " -mno-lwp";
1095       const char *fma = has_fma ? " -mfma" : " -mno-fma";
1096       const char *fma4 = has_fma4 ? " -mfma4" : " -mno-fma4";
1097       const char *xop = has_xop ? " -mxop" : " -mno-xop";
1098       const char *bmi = has_bmi ? " -mbmi" : " -mno-bmi";
1099       const char *pconfig = has_pconfig ? " -mpconfig" : " -mno-pconfig";
1100       const char *wbnoinvd = has_wbnoinvd ? " -mwbnoinvd" : " -mno-wbnoinvd";
1101       const char *sgx = has_sgx ? " -msgx" : " -mno-sgx";
1102       const char *bmi2 = has_bmi2 ? " -mbmi2" : " -mno-bmi2";
1103       const char *tbm = has_tbm ? " -mtbm" : " -mno-tbm";
1104       const char *avx = has_avx ? " -mavx" : " -mno-avx";
1105       const char *avx2 = has_avx2 ? " -mavx2" : " -mno-avx2";
1106       const char *sse4_2 = has_sse4_2 ? " -msse4.2" : " -mno-sse4.2";
1107       const char *sse4_1 = has_sse4_1 ? " -msse4.1" : " -mno-sse4.1";
1108       const char *lzcnt = has_lzcnt ? " -mlzcnt" : " -mno-lzcnt";
1109       const char *hle = has_hle ? " -mhle" : " -mno-hle";
1110       const char *rtm = has_rtm ? " -mrtm" : " -mno-rtm";
1111       const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd";
1112       const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c";
1113       const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase";
1114       const char *rdseed = has_rdseed ? " -mrdseed" : " -mno-rdseed";
1115       const char *prfchw = has_prfchw ? " -mprfchw" : " -mno-prfchw";
1116       const char *adx = has_adx ? " -madx" : " -mno-adx";
1117       const char *fxsr = has_fxsr ? " -mfxsr" : " -mno-fxsr";
1118       const char *xsave = has_xsave ? " -mxsave" : " -mno-xsave";
1119       const char *xsaveopt = has_xsaveopt ? " -mxsaveopt" : " -mno-xsaveopt";
1120       const char *avx512f = has_avx512f ? " -mavx512f" : " -mno-avx512f";
1121       const char *avx512er = has_avx512er ? " -mavx512er" : " -mno-avx512er";
1122       const char *avx512cd = has_avx512cd ? " -mavx512cd" : " -mno-avx512cd";
1123       const char *avx512pf = has_avx512pf ? " -mavx512pf" : " -mno-avx512pf";
1124       const char *prefetchwt1 = has_prefetchwt1 ? " -mprefetchwt1" : " -mno-prefetchwt1";
1125       const char *clflushopt = has_clflushopt ? " -mclflushopt" : " -mno-clflushopt";
1126       const char *xsavec = has_xsavec ? " -mxsavec" : " -mno-xsavec";
1127       const char *xsaves = has_xsaves ? " -mxsaves" : " -mno-xsaves";
1128       const char *avx512dq = has_avx512dq ? " -mavx512dq" : " -mno-avx512dq";
1129       const char *avx512bw = has_avx512bw ? " -mavx512bw" : " -mno-avx512bw";
1130       const char *avx512vl = has_avx512vl ? " -mavx512vl" : " -mno-avx512vl";
1131       const char *avx512ifma = has_avx512ifma ? " -mavx512ifma" : " -mno-avx512ifma";
1132       const char *avx512vbmi = has_avx512vbmi ? " -mavx512vbmi" : " -mno-avx512vbmi";
1133       const char *avx5124vnniw = has_avx5124vnniw ? " -mavx5124vnniw" : " -mno-avx5124vnniw";
1134       const char *avx512vbmi2 = has_avx512vbmi2 ? " -mavx512vbmi2" : " -mno-avx512vbmi2";
1135       const char *avx512vnni = has_avx512vnni ? " -mavx512vnni" : " -mno-avx512vnni";
1136       const char *avx5124fmaps = has_avx5124fmaps ? " -mavx5124fmaps" : " -mno-avx5124fmaps";
1137       const char *clwb = has_clwb ? " -mclwb" : " -mno-clwb";
1138       const char *mwaitx  = has_mwaitx  ? " -mmwaitx"  : " -mno-mwaitx";
1139       const char *clzero  = has_clzero  ? " -mclzero"  : " -mno-clzero";
1140       const char *pku = has_pku ? " -mpku" : " -mno-pku";
1141       const char *rdpid = has_rdpid ? " -mrdpid" : " -mno-rdpid";
1142       const char *gfni = has_gfni ? " -mgfni" : " -mno-gfni";
1143       const char *shstk = has_shstk ? " -mshstk" : " -mno-shstk";
1144       const char *vaes = has_vaes ? " -mvaes" : " -mno-vaes";
1145       const char *vpclmulqdq = has_vpclmulqdq ? " -mvpclmulqdq" : " -mno-vpclmulqdq";
1146       const char *avx512bitalg = has_avx512bitalg ? " -mavx512bitalg" : " -mno-avx512bitalg";
1147       const char *movdiri = has_movdiri ? " -mmovdiri" : " -mno-movdiri";
1148       const char *movdir64b = has_movdir64b ? " -mmovdir64b" : " -mno-movdir64b";
1149       const char *enqcmd = has_enqcmd ? " -menqcmd" : " -mno-enqcmd";
1150       const char *waitpkg = has_waitpkg ? " -mwaitpkg" : " -mno-waitpkg";
1151       const char *cldemote = has_cldemote ? " -mcldemote" : " -mno-cldemote";
1152       const char *ptwrite = has_ptwrite ? " -mptwrite" : " -mno-ptwrite";
1153       const char *avx512bf16 = has_avx512bf16 ? " -mavx512bf16" : " -mno-avx512bf16";
1154
1155       options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3,
1156                         sse4a, cx16, sahf, movbe, aes, sha, pclmul,
1157                         popcnt, abm, lwp, fma, fma4, xop, bmi, sgx, bmi2,
1158                         pconfig, wbnoinvd,
1159                         tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm,
1160                         hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx,
1161                         fxsr, xsave, xsaveopt, avx512f, avx512er,
1162                         avx512cd, avx512pf, prefetchwt1, clflushopt,
1163                         xsavec, xsaves, avx512dq, avx512bw, avx512vl,
1164                         avx512ifma, avx512vbmi, avx5124fmaps, avx5124vnniw,
1165                         clwb, mwaitx, clzero, pku, rdpid, gfni, shstk,
1166                         avx512vbmi2, avx512vnni, vaes, vpclmulqdq,
1167                         avx512bitalg, movdiri, movdir64b, waitpkg, cldemote,
1168                         ptwrite, avx512bf16, enqcmd,
1169                         NULL);
1170     }
1171
1172 done:
1173   return concat (cache, "-m", argv[0], "=", cpu, options, NULL);
1174 }
1175 #else
1176
1177 /* If we are compiling with GCC where %EBX register is fixed, then the
1178    driver will just ignore -march and -mtune "native" target and will leave
1179    to the newly built compiler to generate code for its default target.  */
1180
1181 const char *host_detect_local_cpu (int, const char **)
1182 {
1183   return NULL;
1184 }
1185 #endif /* __GNUC__ */