2 Copyright (C) 1988-2019 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
23 #include "diagnostic-core.h"
27 #include "common/common-target.h"
28 #include "common/common-target-def.h"
32 /* Define a set of ISAs which are available when a given ISA is
33 enabled. MMX and SSE ISAs are handled separately. */
35 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
36 #define OPTION_MASK_ISA_3DNOW_SET \
37 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
38 #define OPTION_MASK_ISA_3DNOW_A_SET \
39 (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET)
41 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
42 #define OPTION_MASK_ISA_SSE2_SET \
43 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
44 #define OPTION_MASK_ISA_SSE3_SET \
45 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
46 #define OPTION_MASK_ISA_SSSE3_SET \
47 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
48 #define OPTION_MASK_ISA_SSE4_1_SET \
49 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
50 #define OPTION_MASK_ISA_SSE4_2_SET \
51 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
52 #define OPTION_MASK_ISA_AVX_SET \
53 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \
54 | OPTION_MASK_ISA_XSAVE_SET)
55 #define OPTION_MASK_ISA_FMA_SET \
56 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
57 #define OPTION_MASK_ISA_AVX2_SET \
58 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
59 #define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR
60 #define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE
61 #define OPTION_MASK_ISA_XSAVEOPT_SET \
62 (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE_SET)
63 #define OPTION_MASK_ISA_AVX512F_SET \
64 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET)
65 #define OPTION_MASK_ISA_AVX512CD_SET \
66 (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET)
67 #define OPTION_MASK_ISA_AVX512PF_SET \
68 (OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET)
69 #define OPTION_MASK_ISA_AVX512ER_SET \
70 (OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET)
71 #define OPTION_MASK_ISA_AVX512DQ_SET \
72 (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET)
73 #define OPTION_MASK_ISA_AVX512BW_SET \
74 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET)
75 #define OPTION_MASK_ISA_AVX512VL_SET \
76 (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET)
77 #define OPTION_MASK_ISA_AVX512IFMA_SET \
78 (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET)
79 #define OPTION_MASK_ISA_AVX512VBMI_SET \
80 (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
81 #define OPTION_MASK_ISA_AVX5124FMAPS_SET OPTION_MASK_ISA_AVX5124FMAPS
82 #define OPTION_MASK_ISA_AVX5124VNNIW_SET OPTION_MASK_ISA_AVX5124VNNIW
83 #define OPTION_MASK_ISA_AVX512VBMI2_SET \
84 (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512F_SET)
85 #define OPTION_MASK_ISA_AVX512VNNI_SET \
86 (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET)
87 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
88 (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET)
89 #define OPTION_MASK_ISA_AVX512BITALG_SET \
90 (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512F_SET)
91 #define OPTION_MASK_ISA_AVX512BF16_SET OPTION_MASK_ISA_AVX512BF16
92 #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
93 #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
94 #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
95 #define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX
96 #define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1
97 #define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT
98 #define OPTION_MASK_ISA_XSAVES_SET \
99 (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET)
100 #define OPTION_MASK_ISA_XSAVEC_SET \
101 (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET)
102 #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
104 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
106 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
108 #define OPTION_MASK_ISA_SSE4A_SET \
109 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
110 #define OPTION_MASK_ISA_FMA4_SET \
111 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
112 | OPTION_MASK_ISA_AVX_SET)
113 #define OPTION_MASK_ISA_XOP_SET \
114 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
115 #define OPTION_MASK_ISA_LWP_SET \
118 /* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */
119 #define OPTION_MASK_ISA_AES_SET \
120 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
121 #define OPTION_MASK_ISA_SHA_SET \
122 (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET)
123 #define OPTION_MASK_ISA_PCLMUL_SET \
124 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
126 #define OPTION_MASK_ISA_ABM_SET \
127 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
129 #define OPTION_MASK_ISA_PCONFIG_SET OPTION_MASK_ISA_PCONFIG
130 #define OPTION_MASK_ISA_WBNOINVD_SET OPTION_MASK_ISA_WBNOINVD
131 #define OPTION_MASK_ISA_SGX_SET OPTION_MASK_ISA_SGX
132 #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
133 #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2
134 #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT
135 #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
136 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
137 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
138 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
139 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
140 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
142 #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
143 #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
144 #define OPTION_MASK_ISA_PTWRITE_SET OPTION_MASK_ISA_PTWRITE
145 #define OPTION_MASK_ISA_F16C_SET \
146 (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
147 #define OPTION_MASK_ISA_MWAITX_SET OPTION_MASK_ISA_MWAITX
148 #define OPTION_MASK_ISA_CLZERO_SET OPTION_MASK_ISA_CLZERO
149 #define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU
150 #define OPTION_MASK_ISA_RDPID_SET OPTION_MASK_ISA_RDPID
151 #define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI
152 #define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK
153 #define OPTION_MASK_ISA_VAES_SET OPTION_MASK_ISA_VAES
154 #define OPTION_MASK_ISA_VPCLMULQDQ_SET OPTION_MASK_ISA_VPCLMULQDQ
155 #define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI
156 #define OPTION_MASK_ISA_MOVDIR64B_SET OPTION_MASK_ISA_MOVDIR64B
157 #define OPTION_MASK_ISA_WAITPKG_SET OPTION_MASK_ISA_WAITPKG
158 #define OPTION_MASK_ISA_CLDEMOTE_SET OPTION_MASK_ISA_CLDEMOTE
159 #define OPTION_MASK_ISA_ENQCMD_SET OPTION_MASK_ISA_ENQCMD
161 /* Define a set of ISAs which aren't available when a given ISA is
162 disabled. MMX and SSE ISAs are handled separately. */
164 #define OPTION_MASK_ISA_MMX_UNSET \
165 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
166 #define OPTION_MASK_ISA_3DNOW_UNSET \
167 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
168 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
170 #define OPTION_MASK_ISA_SSE_UNSET \
171 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
172 #define OPTION_MASK_ISA_SSE2_UNSET \
173 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
174 #define OPTION_MASK_ISA_SSE3_UNSET \
175 (OPTION_MASK_ISA_SSE3 \
176 | OPTION_MASK_ISA_SSSE3_UNSET \
177 | OPTION_MASK_ISA_SSE4A_UNSET )
178 #define OPTION_MASK_ISA_SSSE3_UNSET \
179 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
180 #define OPTION_MASK_ISA_SSE4_1_UNSET \
181 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
182 #define OPTION_MASK_ISA_SSE4_2_UNSET \
183 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
184 #define OPTION_MASK_ISA_AVX_UNSET \
185 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
186 | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \
187 | OPTION_MASK_ISA_AVX2_UNSET | OPTION_MASK_ISA_XSAVE_UNSET)
188 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
189 #define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR
190 #define OPTION_MASK_ISA_XSAVE_UNSET \
191 (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \
192 | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET)
193 #define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT
194 #define OPTION_MASK_ISA_AVX2_UNSET \
195 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)
196 #define OPTION_MASK_ISA_AVX512F_UNSET \
197 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
198 | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \
199 | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
200 | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512IFMA_UNSET \
201 | OPTION_MASK_ISA_AVX512VBMI2_UNSET \
202 | OPTION_MASK_ISA_AVX512VNNI_UNSET \
203 | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET \
204 | OPTION_MASK_ISA_AVX512BITALG_UNSET)
205 #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
206 #define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF
207 #define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER
208 #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
209 #define OPTION_MASK_ISA_AVX512BW_UNSET \
210 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET)
211 #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL
212 #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA
213 #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI
214 #define OPTION_MASK_ISA_AVX5124FMAPS_UNSET OPTION_MASK_ISA_AVX5124FMAPS
215 #define OPTION_MASK_ISA_AVX5124VNNIW_UNSET OPTION_MASK_ISA_AVX5124VNNIW
216 #define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2
217 #define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI
218 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ
219 #define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG
220 #define OPTION_MASK_ISA_AVX512BF16_UNSET OPTION_MASK_ISA_AVX512BF16
221 #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
222 #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
223 #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
224 #define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX
225 #define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1
226 #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
227 #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
228 #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
229 #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
230 #define OPTION_MASK_ISA_MWAITX_UNSET OPTION_MASK_ISA_MWAITX
231 #define OPTION_MASK_ISA_CLZERO_UNSET OPTION_MASK_ISA_CLZERO
232 #define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU
233 #define OPTION_MASK_ISA_RDPID_UNSET OPTION_MASK_ISA_RDPID
234 #define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI
235 #define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK
236 #define OPTION_MASK_ISA_VAES_UNSET OPTION_MASK_ISA_VAES
237 #define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ
238 #define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI
239 #define OPTION_MASK_ISA_MOVDIR64B_UNSET OPTION_MASK_ISA_MOVDIR64B
240 #define OPTION_MASK_ISA_WAITPKG_UNSET OPTION_MASK_ISA_WAITPKG
241 #define OPTION_MASK_ISA_CLDEMOTE_UNSET OPTION_MASK_ISA_CLDEMOTE
242 #define OPTION_MASK_ISA_ENQCMD_UNSET OPTION_MASK_ISA_ENQCMD
244 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
246 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
248 #define OPTION_MASK_ISA_SSE4A_UNSET \
249 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
251 #define OPTION_MASK_ISA_FMA4_UNSET \
252 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
253 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
254 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
256 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
257 #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA
258 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
259 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
260 #define OPTION_MASK_ISA_PCONFIG_UNSET OPTION_MASK_ISA_PCONFIG
261 #define OPTION_MASK_ISA_WBNOINVD_UNSET OPTION_MASK_ISA_WBNOINVD
262 #define OPTION_MASK_ISA_SGX_UNSET OPTION_MASK_ISA_SGX
263 #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
264 #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2
265 #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT
266 #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
267 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
268 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
269 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
270 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
271 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
273 #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
274 #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
275 #define OPTION_MASK_ISA_PTWRITE_UNSET OPTION_MASK_ISA_PTWRITE
276 #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
278 #define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \
279 (OPTION_MASK_ISA_MMX_UNSET \
280 | OPTION_MASK_ISA_SSE_UNSET)
282 #define OPTION_MASK_ISA2_AVX512F_UNSET \
283 (OPTION_MASK_ISA_AVX512BF16_UNSET \
284 | OPTION_MASK_ISA_AVX5124FMAPS_UNSET \
285 | OPTION_MASK_ISA_AVX5124VNNIW_UNSET)
286 #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
287 (OPTION_MASK_ISA2_AVX512F_UNSET)
289 #define OPTION_MASK_ISA2_AVX512BW_UNSET OPTION_MASK_ISA_AVX512BF16_UNSET
291 /* Set 1 << value as value of -malign-FLAG option. */
294 set_malign_value (const char **flag
, unsigned value
)
296 char *r
= XNEWVEC (char, 6);
297 sprintf (r
, "%d", 1 << value
);
301 /* Implement TARGET_HANDLE_OPTION. */
304 ix86_handle_option (struct gcc_options
*opts
,
305 struct gcc_options
*opts_set ATTRIBUTE_UNUSED
,
306 const struct cl_decoded_option
*decoded
,
309 size_t code
= decoded
->opt_index
;
310 int value
= decoded
->value
;
314 case OPT_mgeneral_regs_only
:
317 /* Disable MMX, SSE and x87 instructions if only
318 general registers are allowed. */
319 opts
->x_ix86_isa_flags
320 &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET
;
321 opts
->x_ix86_isa_flags2
322 &= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET
;
323 opts
->x_ix86_isa_flags_explicit
324 |= OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET
;
325 opts
->x_ix86_isa_flags2_explicit
326 |= OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET
;
328 opts
->x_target_flags
&= ~MASK_80387
;
337 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_MMX_SET
;
338 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_MMX_SET
;
342 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_MMX_UNSET
;
343 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_MMX_UNSET
;
350 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_3DNOW_SET
;
351 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_3DNOW_SET
;
355 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_3DNOW_UNSET
;
356 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_3DNOW_UNSET
;
363 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_3DNOW_A_SET
;
364 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_3DNOW_A_SET
;
368 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_3DNOW_A_UNSET
;
369 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_3DNOW_A_UNSET
;
376 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_SSE_SET
;
377 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE_SET
;
381 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_SSE_UNSET
;
382 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE_UNSET
;
383 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AVX512F_UNSET
;
384 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX512F_UNSET
;
391 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_SSE2_SET
;
392 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE2_SET
;
396 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_SSE2_UNSET
;
397 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE2_UNSET
;
398 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AVX512F_UNSET
;
399 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX512F_UNSET
;
406 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_SSE3_SET
;
407 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE3_SET
;
411 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_SSE3_UNSET
;
412 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE3_UNSET
;
413 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AVX512F_UNSET
;
414 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX512F_UNSET
;
421 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_SSSE3_SET
;
422 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSSE3_SET
;
426 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_SSSE3_UNSET
;
427 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSSE3_UNSET
;
428 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AVX512F_UNSET
;
429 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX512F_UNSET
;
436 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_SSE4_1_SET
;
437 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE4_1_SET
;
441 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_SSE4_1_UNSET
;
442 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE4_1_UNSET
;
443 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AVX512F_UNSET
;
444 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX512F_UNSET
;
451 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_SSE4_2_SET
;
452 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE4_2_SET
;
456 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_SSE4_2_UNSET
;
457 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE4_2_UNSET
;
458 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AVX512F_UNSET
;
459 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX512F_UNSET
;
466 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX_SET
;
467 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX_SET
;
471 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX_UNSET
;
472 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX_UNSET
;
473 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AVX512F_UNSET
;
474 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX512F_UNSET
;
481 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX2_SET
;
482 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX2_SET
;
486 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX2_UNSET
;
487 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX2_UNSET
;
488 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AVX512F_UNSET
;
489 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX512F_UNSET
;
496 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512F_SET
;
497 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512F_SET
;
501 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512F_UNSET
;
502 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512F_UNSET
;
503 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AVX512F_UNSET
;
504 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX512F_UNSET
;
511 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512CD_SET
;
512 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512CD_SET
;
516 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512CD_UNSET
;
517 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512CD_UNSET
;
524 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512PF_SET
;
525 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512PF_SET
;
529 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512PF_UNSET
;
530 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512PF_UNSET
;
537 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512ER_SET
;
538 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512ER_SET
;
542 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512ER_UNSET
;
543 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512ER_UNSET
;
550 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA_RDPID_SET
;
551 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_RDPID_SET
;
555 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA_RDPID_UNSET
;
556 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_RDPID_UNSET
;
563 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_GFNI_SET
;
564 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_GFNI_SET
;
568 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_GFNI_UNSET
;
569 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_GFNI_UNSET
;
576 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_SHSTK_SET
;
577 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SHSTK_SET
;
581 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_SHSTK_UNSET
;
582 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SHSTK_UNSET
;
589 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA_VAES_SET
;
590 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_VAES_SET
;
594 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA_VAES_UNSET
;
595 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_VAES_UNSET
;
599 case OPT_mvpclmulqdq
:
602 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_VPCLMULQDQ_SET
;
603 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_VPCLMULQDQ_SET
;
607 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_VPCLMULQDQ_UNSET
;
608 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_VPCLMULQDQ_UNSET
;
615 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_MOVDIRI_SET
;
616 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_MOVDIRI_SET
;
620 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_MOVDIRI_UNSET
;
621 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_MOVDIRI_UNSET
;
628 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA_MOVDIR64B_SET
;
629 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_MOVDIR64B_SET
;
633 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA_MOVDIR64B_UNSET
;
634 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_MOVDIR64B_UNSET
;
641 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA_CLDEMOTE_SET
;
642 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_CLDEMOTE_SET
;
646 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA_CLDEMOTE_UNSET
;
647 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_CLDEMOTE_UNSET
;
654 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA_WAITPKG_SET
;
655 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_WAITPKG_SET
;
659 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA_WAITPKG_UNSET
;
660 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_WAITPKG_UNSET
;
667 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA_ENQCMD_SET
;
668 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_ENQCMD_SET
;
672 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA_ENQCMD_UNSET
;
673 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_ENQCMD_UNSET
;
677 case OPT_mavx5124fmaps
:
680 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA_AVX5124FMAPS_SET
;
681 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_AVX5124FMAPS_SET
;
682 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512F_SET
;
683 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512F_SET
;
687 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA_AVX5124FMAPS_UNSET
;
688 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_AVX5124FMAPS_UNSET
;
692 case OPT_mavx5124vnniw
:
695 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA_AVX5124VNNIW_SET
;
696 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_AVX5124VNNIW_SET
;
697 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512F_SET
;
698 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512F_SET
;
702 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA_AVX5124VNNIW_UNSET
;
703 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_AVX5124VNNIW_UNSET
;
707 case OPT_mavx512vbmi2
:
710 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512VBMI2_SET
;
711 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512VBMI2_SET
;
715 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET
;
716 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512VBMI2_UNSET
;
720 case OPT_mavx512vnni
:
723 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512VNNI_SET
;
724 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512VNNI_SET
;
728 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512VNNI_UNSET
;
729 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512VNNI_UNSET
;
733 case OPT_mavx512vpopcntdq
:
736 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET
;
737 opts
->x_ix86_isa_flags_explicit
738 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET
;
742 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET
;
743 opts
->x_ix86_isa_flags_explicit
744 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET
;
748 case OPT_mavx512bitalg
:
751 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512BITALG_SET
;
752 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512BITALG_SET
;
756 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512BITALG_UNSET
;
757 opts
->x_ix86_isa_flags_explicit
758 |= OPTION_MASK_ISA_AVX512BITALG_UNSET
;
762 case OPT_mavx512bf16
:
765 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA_AVX512BF16_SET
;
766 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_AVX512BF16_SET
;
767 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512BW_SET
;
768 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512BW_SET
;
772 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA_AVX512BF16_UNSET
;
773 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_AVX512BF16_UNSET
;
780 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA_SGX_SET
;
781 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_SGX_SET
;
785 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA_SGX_UNSET
;
786 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_SGX_UNSET
;
793 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA_PCONFIG_SET
;
794 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_PCONFIG_SET
;
798 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA_PCONFIG_UNSET
;
799 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_PCONFIG_UNSET
;
806 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA_WBNOINVD_SET
;
807 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_WBNOINVD_SET
;
811 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA_WBNOINVD_UNSET
;
812 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_WBNOINVD_UNSET
;
819 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512DQ_SET
;
820 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512DQ_SET
;
824 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512DQ_UNSET
;
825 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512DQ_UNSET
;
832 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512BW_SET
;
833 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512BW_SET
;
837 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512BW_UNSET
;
838 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512BW_UNSET
;
839 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AVX512BW_UNSET
;
840 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX512BW_UNSET
;
847 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512VL_SET
;
848 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512VL_SET
;
852 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512VL_UNSET
;
853 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512VL_UNSET
;
857 case OPT_mavx512ifma
:
860 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512IFMA_SET
;
861 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512IFMA_SET
;
865 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512IFMA_UNSET
;
866 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512IFMA_UNSET
;
870 case OPT_mavx512vbmi
:
873 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AVX512VBMI_SET
;
874 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512VBMI_SET
;
878 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AVX512VBMI_UNSET
;
879 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AVX512VBMI_UNSET
;
886 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_FMA_SET
;
887 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_FMA_SET
;
891 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_FMA_UNSET
;
892 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_FMA_UNSET
;
899 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_RTM_SET
;
900 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_RTM_SET
;
904 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_RTM_UNSET
;
905 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_RTM_UNSET
;
910 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_SSE4_SET
;
911 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE4_SET
;
915 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_SSE4_UNSET
;
916 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE4_UNSET
;
917 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA2_AVX512F_UNSET
;
918 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA2_AVX512F_UNSET
;
924 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_SSE4A_SET
;
925 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE4A_SET
;
929 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_SSE4A_UNSET
;
930 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SSE4A_UNSET
;
937 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_FMA4_SET
;
938 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_FMA4_SET
;
942 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_FMA4_UNSET
;
943 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_FMA4_UNSET
;
950 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_XOP_SET
;
951 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_XOP_SET
;
955 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_XOP_UNSET
;
956 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_XOP_UNSET
;
963 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_LWP_SET
;
964 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_LWP_SET
;
968 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_LWP_UNSET
;
969 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_LWP_UNSET
;
976 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_ABM_SET
;
977 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_ABM_SET
;
981 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_ABM_UNSET
;
982 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_ABM_UNSET
;
989 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_BMI_SET
;
990 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_BMI_SET
;
994 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_BMI_UNSET
;
995 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_BMI_UNSET
;
1002 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_BMI2_SET
;
1003 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_BMI2_SET
;
1007 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_BMI2_UNSET
;
1008 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_BMI2_UNSET
;
1015 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_LZCNT_SET
;
1016 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_LZCNT_SET
;
1020 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_LZCNT_UNSET
;
1021 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_LZCNT_UNSET
;
1028 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_TBM_SET
;
1029 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_TBM_SET
;
1033 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_TBM_UNSET
;
1034 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_TBM_UNSET
;
1041 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_POPCNT_SET
;
1042 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_POPCNT_SET
;
1046 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_POPCNT_UNSET
;
1047 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_POPCNT_UNSET
;
1054 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_SAHF_SET
;
1055 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SAHF_SET
;
1059 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_SAHF_UNSET
;
1060 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SAHF_UNSET
;
1067 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA_CX16_SET
;
1068 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_CX16_SET
;
1072 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA_CX16_UNSET
;
1073 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_CX16_UNSET
;
1080 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA_MOVBE_SET
;
1081 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_MOVBE_SET
;
1085 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA_MOVBE_UNSET
;
1086 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_MOVBE_UNSET
;
1093 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_CRC32_SET
;
1094 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_CRC32_SET
;
1098 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_CRC32_UNSET
;
1099 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_CRC32_UNSET
;
1106 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_AES_SET
;
1107 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AES_SET
;
1111 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_AES_UNSET
;
1112 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_AES_UNSET
;
1119 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_SHA_SET
;
1120 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SHA_SET
;
1124 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_SHA_UNSET
;
1125 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_SHA_UNSET
;
1132 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_PCLMUL_SET
;
1133 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_PCLMUL_SET
;
1137 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_PCLMUL_UNSET
;
1138 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_PCLMUL_UNSET
;
1145 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_FSGSBASE_SET
;
1146 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_FSGSBASE_SET
;
1150 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_FSGSBASE_UNSET
;
1151 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_FSGSBASE_UNSET
;
1158 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_RDRND_SET
;
1159 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_RDRND_SET
;
1163 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_RDRND_UNSET
;
1164 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_RDRND_UNSET
;
1171 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA_PTWRITE_SET
;
1172 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_PTWRITE_SET
;
1176 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA_PTWRITE_UNSET
;
1177 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_PTWRITE_UNSET
;
1184 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_F16C_SET
;
1185 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_F16C_SET
;
1189 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_F16C_UNSET
;
1190 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_F16C_UNSET
;
1197 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_FXSR_SET
;
1198 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_FXSR_SET
;
1202 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_FXSR_UNSET
;
1203 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_FXSR_UNSET
;
1210 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_XSAVE_SET
;
1211 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_XSAVE_SET
;
1215 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_XSAVE_UNSET
;
1216 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_XSAVE_UNSET
;
1223 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_XSAVEOPT_SET
;
1224 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_XSAVEOPT_SET
;
1228 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_XSAVEOPT_UNSET
;
1229 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_XSAVEOPT_UNSET
;
1236 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_XSAVEC_SET
;
1237 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_XSAVEC_SET
;
1241 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_XSAVEC_UNSET
;
1242 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_XSAVEC_UNSET
;
1249 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_XSAVES_SET
;
1250 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_XSAVES_SET
;
1254 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_XSAVES_UNSET
;
1255 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_XSAVES_UNSET
;
1262 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_RDSEED_SET
;
1263 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_RDSEED_SET
;
1267 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_RDSEED_UNSET
;
1268 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_RDSEED_UNSET
;
1275 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_PRFCHW_SET
;
1276 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_PRFCHW_SET
;
1280 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_PRFCHW_UNSET
;
1281 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_PRFCHW_UNSET
;
1288 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_ADX_SET
;
1289 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_ADX_SET
;
1293 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_ADX_UNSET
;
1294 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_ADX_UNSET
;
1298 case OPT_mprefetchwt1
:
1301 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_PREFETCHWT1_SET
;
1302 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_PREFETCHWT1_SET
;
1306 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_PREFETCHWT1_UNSET
;
1307 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_PREFETCHWT1_UNSET
;
1311 case OPT_mclflushopt
:
1314 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_CLFLUSHOPT_SET
;
1315 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_CLFLUSHOPT_SET
;
1319 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_CLFLUSHOPT_UNSET
;
1320 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_CLFLUSHOPT_UNSET
;
1327 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_CLWB_SET
;
1328 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_CLWB_SET
;
1332 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_CLWB_UNSET
;
1333 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_CLWB_UNSET
;
1340 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA_MWAITX_SET
;
1341 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_MWAITX_SET
;
1345 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA_MWAITX_UNSET
;
1346 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_MWAITX_UNSET
;
1353 opts
->x_ix86_isa_flags2
|= OPTION_MASK_ISA_CLZERO_SET
;
1354 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_CLZERO_SET
;
1358 opts
->x_ix86_isa_flags2
&= ~OPTION_MASK_ISA_CLZERO_UNSET
;
1359 opts
->x_ix86_isa_flags2_explicit
|= OPTION_MASK_ISA_CLZERO_UNSET
;
1366 opts
->x_ix86_isa_flags
|= OPTION_MASK_ISA_PKU_SET
;
1367 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_PKU_SET
;
1371 opts
->x_ix86_isa_flags
&= ~OPTION_MASK_ISA_PKU_UNSET
;
1372 opts
->x_ix86_isa_flags_explicit
|= OPTION_MASK_ISA_PKU_UNSET
;
1377 case OPT_malign_loops_
:
1378 warning_at (loc
, 0, "%<-malign-loops%> is obsolete, "
1379 "use %<-falign-loops%>");
1380 if (value
> MAX_CODE_ALIGN
)
1381 error_at (loc
, "%<-malign-loops=%d%> is not between 0 and %d",
1382 value
, MAX_CODE_ALIGN
);
1384 set_malign_value (&opts
->x_str_align_loops
, value
);
1387 case OPT_malign_jumps_
:
1388 warning_at (loc
, 0, "%<-malign-jumps%> is obsolete, "
1389 "use %<-falign-jumps%>");
1390 if (value
> MAX_CODE_ALIGN
)
1391 error_at (loc
, "%<-malign-jumps=%d%> is not between 0 and %d",
1392 value
, MAX_CODE_ALIGN
);
1394 set_malign_value (&opts
->x_str_align_jumps
, value
);
1397 case OPT_malign_functions_
:
1399 "%<-malign-functions%> is obsolete, "
1400 "use %<-falign-functions%>");
1401 if (value
> MAX_CODE_ALIGN
)
1402 error_at (loc
, "%<-malign-functions=%d%> is not between 0 and %d",
1403 value
, MAX_CODE_ALIGN
);
1405 set_malign_value (&opts
->x_str_align_functions
, value
);
1408 case OPT_mbranch_cost_
:
1411 error_at (loc
, "%<-mbranch-cost=%d%> is not between 0 and 5", value
);
1412 opts
->x_ix86_branch_cost
= 5;
1421 static const struct default_options ix86_option_optimization_table
[] =
1423 /* Enable redundant extension instructions removal at -O2 and higher. */
1424 { OPT_LEVELS_2_PLUS
, OPT_free
, NULL
, 1 },
1425 /* Enable function splitting at -O2 and higher. */
1426 { OPT_LEVELS_2_PLUS
, OPT_freorder_blocks_and_partition
, NULL
, 1 },
1427 /* The STC algorithm produces the smallest code at -Os, for x86. */
1428 { OPT_LEVELS_2_PLUS
, OPT_freorder_blocks_algorithm_
, NULL
,
1429 REORDER_BLOCKS_ALGORITHM_STC
},
1430 /* Turn off -fschedule-insns by default. It tends to make the
1431 problem with not enough registers even worse. */
1432 { OPT_LEVELS_ALL
, OPT_fschedule_insns
, NULL
, 0 },
1434 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
1435 SUBTARGET_OPTIMIZATION_OPTIONS
,
1437 { OPT_LEVELS_NONE
, 0, NULL
, 0 }
1440 /* Implement TARGET_OPTION_INIT_STRUCT. */
1443 ix86_option_init_struct (struct gcc_options
*opts
)
1446 /* The Darwin libraries never set errno, so we might as well
1447 avoid calling them when that's the only reason we would. */
1448 opts
->x_flag_errno_math
= 0;
1450 opts
->x_flag_pcc_struct_return
= 2;
1451 opts
->x_flag_asynchronous_unwind_tables
= 2;
1454 /* On the x86 -fsplit-stack and -fstack-protector both use the same
1455 field in the TCB, so they cannot be used together. */
1458 ix86_supports_split_stack (bool report ATTRIBUTE_UNUSED
,
1459 struct gcc_options
*opts ATTRIBUTE_UNUSED
)
1463 #ifndef TARGET_THREAD_SPLIT_STACK_OFFSET
1465 error ("%<-fsplit-stack%> currently only supported on GNU/Linux");
1468 if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE
)
1471 error ("%<-fsplit-stack%> requires "
1472 "assembler support for CFI directives");
1480 /* Implement TARGET_EXCEPT_UNWIND_INFO. */
1482 static enum unwind_info_type
1483 i386_except_unwind_info (struct gcc_options
*opts
)
1485 /* Honor the --enable-sjlj-exceptions configure switch. */
1486 #ifdef CONFIG_SJLJ_EXCEPTIONS
1487 if (CONFIG_SJLJ_EXCEPTIONS
)
1491 /* On windows 64, prefer SEH exceptions over anything else. */
1492 if (TARGET_64BIT
&& DEFAULT_ABI
== MS_ABI
&& opts
->x_flag_unwind_tables
)
1495 if (DWARF2_UNWIND_INFO
)
1501 #undef TARGET_EXCEPT_UNWIND_INFO
1502 #define TARGET_EXCEPT_UNWIND_INFO i386_except_unwind_info
1504 #undef TARGET_DEFAULT_TARGET_FLAGS
1505 #define TARGET_DEFAULT_TARGET_FLAGS \
1507 | TARGET_SUBTARGET_DEFAULT \
1508 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
1510 #undef TARGET_HANDLE_OPTION
1511 #define TARGET_HANDLE_OPTION ix86_handle_option
1513 #undef TARGET_OPTION_OPTIMIZATION_TABLE
1514 #define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table
1515 #undef TARGET_OPTION_INIT_STRUCT
1516 #define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct
1518 #undef TARGET_SUPPORTS_SPLIT_STACK
1519 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
1521 /* This table must be in sync with enum processor_type in i386.h. */
1522 const char *const processor_names
[] =
1565 /* Guarantee that the array is aligned with enum processor_type. */
1566 STATIC_ASSERT (ARRAY_SIZE (processor_names
) == PROCESSOR_max
);
1568 const pta processor_alias_table
[] =
1570 {"i386", PROCESSOR_I386
, CPU_NONE
, 0},
1571 {"i486", PROCESSOR_I486
, CPU_NONE
, 0},
1572 {"i586", PROCESSOR_PENTIUM
, CPU_PENTIUM
, 0},
1573 {"pentium", PROCESSOR_PENTIUM
, CPU_PENTIUM
, 0},
1574 {"lakemont", PROCESSOR_LAKEMONT
, CPU_PENTIUM
, PTA_NO_80387
},
1575 {"pentium-mmx", PROCESSOR_PENTIUM
, CPU_PENTIUM
, PTA_MMX
},
1576 {"winchip-c6", PROCESSOR_I486
, CPU_NONE
, PTA_MMX
},
1577 {"winchip2", PROCESSOR_I486
, CPU_NONE
, PTA_MMX
| PTA_3DNOW
},
1578 {"c3", PROCESSOR_I486
, CPU_NONE
, PTA_MMX
| PTA_3DNOW
},
1579 {"samuel-2", PROCESSOR_I486
, CPU_NONE
, PTA_MMX
| PTA_3DNOW
},
1580 {"c3-2", PROCESSOR_PENTIUMPRO
, CPU_PENTIUMPRO
,
1581 PTA_MMX
| PTA_SSE
| PTA_FXSR
},
1582 {"nehemiah", PROCESSOR_PENTIUMPRO
, CPU_PENTIUMPRO
,
1583 PTA_MMX
| PTA_SSE
| PTA_FXSR
},
1584 {"c7", PROCESSOR_PENTIUMPRO
, CPU_PENTIUMPRO
,
1585 PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
| PTA_FXSR
},
1586 {"esther", PROCESSOR_PENTIUMPRO
, CPU_PENTIUMPRO
,
1587 PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
| PTA_FXSR
},
1588 {"i686", PROCESSOR_PENTIUMPRO
, CPU_PENTIUMPRO
, 0},
1589 {"pentiumpro", PROCESSOR_PENTIUMPRO
, CPU_PENTIUMPRO
, 0},
1590 {"pentium2", PROCESSOR_PENTIUMPRO
, CPU_PENTIUMPRO
, PTA_MMX
| PTA_FXSR
},
1591 {"pentium3", PROCESSOR_PENTIUMPRO
, CPU_PENTIUMPRO
,
1592 PTA_MMX
| PTA_SSE
| PTA_FXSR
},
1593 {"pentium3m", PROCESSOR_PENTIUMPRO
, CPU_PENTIUMPRO
,
1594 PTA_MMX
| PTA_SSE
| PTA_FXSR
},
1595 {"pentium-m", PROCESSOR_PENTIUMPRO
, CPU_PENTIUMPRO
,
1596 PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_FXSR
},
1597 {"pentium4", PROCESSOR_PENTIUM4
, CPU_NONE
,
1598 PTA_MMX
|PTA_SSE
| PTA_SSE2
| PTA_FXSR
},
1599 {"pentium4m", PROCESSOR_PENTIUM4
, CPU_NONE
,
1600 PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_FXSR
},
1601 {"prescott", PROCESSOR_NOCONA
, CPU_NONE
,
1602 PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
| PTA_FXSR
},
1603 {"nocona", PROCESSOR_NOCONA
, CPU_NONE
,
1604 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
1605 | PTA_CX16
| PTA_NO_SAHF
| PTA_FXSR
},
1606 {"core2", PROCESSOR_CORE2
, CPU_CORE2
, PTA_CORE2
},
1607 {"nehalem", PROCESSOR_NEHALEM
, CPU_NEHALEM
, PTA_NEHALEM
},
1608 {"corei7", PROCESSOR_NEHALEM
, CPU_NEHALEM
, PTA_NEHALEM
},
1609 {"westmere", PROCESSOR_NEHALEM
, CPU_NEHALEM
, PTA_WESTMERE
},
1610 {"sandybridge", PROCESSOR_SANDYBRIDGE
, CPU_NEHALEM
,
1612 {"corei7-avx", PROCESSOR_SANDYBRIDGE
, CPU_NEHALEM
,
1614 {"ivybridge", PROCESSOR_SANDYBRIDGE
, CPU_NEHALEM
,
1616 {"core-avx-i", PROCESSOR_SANDYBRIDGE
, CPU_NEHALEM
,
1618 {"haswell", PROCESSOR_HASWELL
, CPU_HASWELL
, PTA_HASWELL
},
1619 {"core-avx2", PROCESSOR_HASWELL
, CPU_HASWELL
, PTA_HASWELL
},
1620 {"broadwell", PROCESSOR_HASWELL
, CPU_HASWELL
, PTA_BROADWELL
},
1621 {"skylake", PROCESSOR_SKYLAKE
, CPU_HASWELL
, PTA_SKYLAKE
},
1622 {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512
, CPU_HASWELL
,
1623 PTA_SKYLAKE_AVX512
},
1624 {"cannonlake", PROCESSOR_CANNONLAKE
, CPU_HASWELL
, PTA_CANNONLAKE
},
1625 {"icelake-client", PROCESSOR_ICELAKE_CLIENT
, CPU_HASWELL
,
1626 PTA_ICELAKE_CLIENT
},
1627 {"icelake-server", PROCESSOR_ICELAKE_SERVER
, CPU_HASWELL
,
1628 PTA_ICELAKE_SERVER
},
1629 {"cascadelake", PROCESSOR_CASCADELAKE
, CPU_HASWELL
,
1631 {"bonnell", PROCESSOR_BONNELL
, CPU_ATOM
, PTA_BONNELL
},
1632 {"atom", PROCESSOR_BONNELL
, CPU_ATOM
, PTA_BONNELL
},
1633 {"silvermont", PROCESSOR_SILVERMONT
, CPU_SLM
, PTA_SILVERMONT
},
1634 {"slm", PROCESSOR_SILVERMONT
, CPU_SLM
, PTA_SILVERMONT
},
1635 {"goldmont", PROCESSOR_GOLDMONT
, CPU_GLM
, PTA_GOLDMONT
},
1636 {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS
, CPU_GLM
, PTA_GOLDMONT_PLUS
},
1637 {"tremont", PROCESSOR_TREMONT
, CPU_GLM
, PTA_TREMONT
},
1638 {"knl", PROCESSOR_KNL
, CPU_SLM
, PTA_KNL
},
1639 {"knm", PROCESSOR_KNM
, CPU_SLM
, PTA_KNM
},
1640 {"intel", PROCESSOR_INTEL
, CPU_SLM
, PTA_NEHALEM
},
1641 {"geode", PROCESSOR_GEODE
, CPU_GEODE
,
1642 PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_PREFETCH_SSE
},
1643 {"k6", PROCESSOR_K6
, CPU_K6
, PTA_MMX
},
1644 {"k6-2", PROCESSOR_K6
, CPU_K6
, PTA_MMX
| PTA_3DNOW
},
1645 {"k6-3", PROCESSOR_K6
, CPU_K6
, PTA_MMX
| PTA_3DNOW
},
1646 {"athlon", PROCESSOR_ATHLON
, CPU_ATHLON
,
1647 PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_PREFETCH_SSE
},
1648 {"athlon-tbird", PROCESSOR_ATHLON
, CPU_ATHLON
,
1649 PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_PREFETCH_SSE
},
1650 {"athlon-4", PROCESSOR_ATHLON
, CPU_ATHLON
,
1651 PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_SSE
| PTA_FXSR
},
1652 {"athlon-xp", PROCESSOR_ATHLON
, CPU_ATHLON
,
1653 PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_SSE
| PTA_FXSR
},
1654 {"athlon-mp", PROCESSOR_ATHLON
, CPU_ATHLON
,
1655 PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_SSE
| PTA_FXSR
},
1656 {"x86-64", PROCESSOR_K8
, CPU_K8
,
1657 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_NO_SAHF
| PTA_FXSR
},
1658 {"eden-x2", PROCESSOR_K8
, CPU_K8
,
1659 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
| PTA_FXSR
},
1660 {"nano", PROCESSOR_K8
, CPU_K8
,
1661 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
1662 | PTA_SSSE3
| PTA_FXSR
},
1663 {"nano-1000", PROCESSOR_K8
, CPU_K8
,
1664 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
1665 | PTA_SSSE3
| PTA_FXSR
},
1666 {"nano-2000", PROCESSOR_K8
, CPU_K8
,
1667 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
1668 | PTA_SSSE3
| PTA_FXSR
},
1669 {"nano-3000", PROCESSOR_K8
, CPU_K8
,
1670 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
1671 | PTA_SSSE3
| PTA_SSE4_1
| PTA_FXSR
},
1672 {"nano-x2", PROCESSOR_K8
, CPU_K8
,
1673 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
1674 | PTA_SSSE3
| PTA_SSE4_1
| PTA_FXSR
},
1675 {"eden-x4", PROCESSOR_K8
, CPU_K8
,
1676 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
1677 | PTA_SSSE3
| PTA_SSE4_1
| PTA_FXSR
},
1678 {"nano-x4", PROCESSOR_K8
, CPU_K8
,
1679 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
1680 | PTA_SSSE3
| PTA_SSE4_1
| PTA_FXSR
},
1681 {"k8", PROCESSOR_K8
, CPU_K8
,
1682 PTA_64BIT
| PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_SSE
1683 | PTA_SSE2
| PTA_NO_SAHF
| PTA_FXSR
},
1684 {"k8-sse3", PROCESSOR_K8
, CPU_K8
,
1685 PTA_64BIT
| PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_SSE
1686 | PTA_SSE2
| PTA_SSE3
| PTA_NO_SAHF
| PTA_FXSR
},
1687 {"opteron", PROCESSOR_K8
, CPU_K8
,
1688 PTA_64BIT
| PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_SSE
1689 | PTA_SSE2
| PTA_NO_SAHF
| PTA_FXSR
},
1690 {"opteron-sse3", PROCESSOR_K8
, CPU_K8
,
1691 PTA_64BIT
| PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_SSE
1692 | PTA_SSE2
| PTA_SSE3
| PTA_NO_SAHF
| PTA_FXSR
},
1693 {"athlon64", PROCESSOR_K8
, CPU_K8
,
1694 PTA_64BIT
| PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_SSE
1695 | PTA_SSE2
| PTA_NO_SAHF
| PTA_FXSR
},
1696 {"athlon64-sse3", PROCESSOR_K8
, CPU_K8
,
1697 PTA_64BIT
| PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_SSE
1698 | PTA_SSE2
| PTA_SSE3
| PTA_NO_SAHF
| PTA_FXSR
},
1699 {"athlon-fx", PROCESSOR_K8
, CPU_K8
,
1700 PTA_64BIT
| PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_SSE
1701 | PTA_SSE2
| PTA_NO_SAHF
| PTA_FXSR
},
1702 {"amdfam10", PROCESSOR_AMDFAM10
, CPU_AMDFAM10
,
1703 PTA_64BIT
| PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_SSE
| PTA_SSE2
1704 | PTA_SSE3
| PTA_SSE4A
| PTA_CX16
| PTA_ABM
| PTA_PRFCHW
| PTA_FXSR
},
1705 {"barcelona", PROCESSOR_AMDFAM10
, CPU_AMDFAM10
,
1706 PTA_64BIT
| PTA_MMX
| PTA_3DNOW
| PTA_3DNOW_A
| PTA_SSE
| PTA_SSE2
1707 | PTA_SSE3
| PTA_SSE4A
| PTA_CX16
| PTA_ABM
| PTA_PRFCHW
| PTA_FXSR
},
1708 {"bdver1", PROCESSOR_BDVER1
, CPU_BDVER1
,
1709 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
1710 | PTA_SSE4A
| PTA_CX16
| PTA_ABM
| PTA_SSSE3
| PTA_SSE4_1
1711 | PTA_SSE4_2
| PTA_AES
| PTA_PCLMUL
| PTA_AVX
| PTA_FMA4
1712 | PTA_XOP
| PTA_LWP
| PTA_PRFCHW
| PTA_FXSR
| PTA_XSAVE
},
1713 {"bdver2", PROCESSOR_BDVER2
, CPU_BDVER2
,
1714 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
1715 | PTA_SSE4A
| PTA_CX16
| PTA_ABM
| PTA_SSSE3
| PTA_SSE4_1
1716 | PTA_SSE4_2
| PTA_AES
| PTA_PCLMUL
| PTA_AVX
| PTA_FMA4
1717 | PTA_XOP
| PTA_LWP
| PTA_BMI
| PTA_TBM
| PTA_F16C
1718 | PTA_FMA
| PTA_PRFCHW
| PTA_FXSR
| PTA_XSAVE
},
1719 {"bdver3", PROCESSOR_BDVER3
, CPU_BDVER3
,
1720 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
1721 | PTA_SSE4A
| PTA_CX16
| PTA_ABM
| PTA_SSSE3
| PTA_SSE4_1
1722 | PTA_SSE4_2
| PTA_AES
| PTA_PCLMUL
| PTA_AVX
| PTA_FMA4
1723 | PTA_XOP
| PTA_LWP
| PTA_BMI
| PTA_TBM
| PTA_F16C
1724 | PTA_FMA
| PTA_PRFCHW
| PTA_FXSR
| PTA_XSAVE
1725 | PTA_XSAVEOPT
| PTA_FSGSBASE
},
1726 {"bdver4", PROCESSOR_BDVER4
, CPU_BDVER4
,
1727 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
1728 | PTA_SSE4A
| PTA_CX16
| PTA_ABM
| PTA_SSSE3
| PTA_SSE4_1
1729 | PTA_SSE4_2
| PTA_AES
| PTA_PCLMUL
| PTA_AVX
| PTA_AVX2
1730 | PTA_FMA4
| PTA_XOP
| PTA_LWP
| PTA_BMI
| PTA_BMI2
1731 | PTA_TBM
| PTA_F16C
| PTA_FMA
| PTA_PRFCHW
| PTA_FXSR
1732 | PTA_XSAVE
| PTA_XSAVEOPT
| PTA_FSGSBASE
| PTA_RDRND
1733 | PTA_MOVBE
| PTA_MWAITX
},
1734 {"znver1", PROCESSOR_ZNVER1
, CPU_ZNVER1
,
1735 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
1736 | PTA_SSE4A
| PTA_CX16
| PTA_ABM
| PTA_SSSE3
| PTA_SSE4_1
1737 | PTA_SSE4_2
| PTA_AES
| PTA_PCLMUL
| PTA_AVX
| PTA_AVX2
1738 | PTA_BMI
| PTA_BMI2
| PTA_F16C
| PTA_FMA
| PTA_PRFCHW
1739 | PTA_FXSR
| PTA_XSAVE
| PTA_XSAVEOPT
| PTA_FSGSBASE
1740 | PTA_RDRND
| PTA_MOVBE
| PTA_MWAITX
| PTA_ADX
| PTA_RDSEED
1741 | PTA_CLZERO
| PTA_CLFLUSHOPT
| PTA_XSAVEC
| PTA_XSAVES
1742 | PTA_SHA
| PTA_LZCNT
| PTA_POPCNT
},
1743 {"znver2", PROCESSOR_ZNVER2
, CPU_ZNVER1
,
1744 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
1745 | PTA_SSE4A
| PTA_CX16
| PTA_ABM
| PTA_SSSE3
| PTA_SSE4_1
1746 | PTA_SSE4_2
| PTA_AES
| PTA_PCLMUL
| PTA_AVX
| PTA_AVX2
1747 | PTA_BMI
| PTA_BMI2
| PTA_F16C
| PTA_FMA
| PTA_PRFCHW
1748 | PTA_FXSR
| PTA_XSAVE
| PTA_XSAVEOPT
| PTA_FSGSBASE
1749 | PTA_RDRND
| PTA_MOVBE
| PTA_MWAITX
| PTA_ADX
| PTA_RDSEED
1750 | PTA_CLZERO
| PTA_CLFLUSHOPT
| PTA_XSAVEC
| PTA_XSAVES
1751 | PTA_SHA
| PTA_LZCNT
| PTA_POPCNT
| PTA_CLWB
| PTA_RDPID
1753 {"btver1", PROCESSOR_BTVER1
, CPU_GENERIC
,
1754 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
1755 | PTA_SSSE3
| PTA_SSE4A
|PTA_ABM
| PTA_CX16
| PTA_PRFCHW
1756 | PTA_FXSR
| PTA_XSAVE
},
1757 {"btver2", PROCESSOR_BTVER2
, CPU_BTVER2
,
1758 PTA_64BIT
| PTA_MMX
| PTA_SSE
| PTA_SSE2
| PTA_SSE3
1759 | PTA_SSSE3
| PTA_SSE4A
|PTA_ABM
| PTA_CX16
| PTA_SSE4_1
1760 | PTA_SSE4_2
| PTA_AES
| PTA_PCLMUL
| PTA_AVX
1761 | PTA_BMI
| PTA_F16C
| PTA_MOVBE
| PTA_PRFCHW
1762 | PTA_FXSR
| PTA_XSAVE
| PTA_XSAVEOPT
},
1764 {"generic", PROCESSOR_GENERIC
, CPU_GENERIC
,
1766 | PTA_HLE
/* flags are only used for -march switch. */ },
1769 int const pta_size
= ARRAY_SIZE (processor_alias_table
);
1771 /* Provide valid option values for -march and -mtune options. */
1774 ix86_get_valid_option_values (int option_code
,
1775 const char *prefix ATTRIBUTE_UNUSED
)
1777 vec
<const char *> v
;
1779 opt_code opt
= (opt_code
) option_code
;
1784 for (unsigned i
= 0; i
< pta_size
; i
++)
1786 const char *name
= processor_alias_table
[i
].name
;
1787 gcc_checking_assert (name
!= NULL
);
1790 #ifdef HAVE_LOCAL_CPU_DETECT
1791 /* Add also "native" as possible value. */
1792 v
.safe_push ("native");
1797 for (unsigned i
= 0; i
< PROCESSOR_max
; i
++)
1799 const char *name
= processor_names
[i
];
1800 gcc_checking_assert (name
!= NULL
);
1811 #undef TARGET_GET_VALID_OPTION_VALUES
1812 #define TARGET_GET_VALID_OPTION_VALUES ix86_get_valid_option_values
1814 struct gcc_targetm_common targetm_common
= TARGETM_COMMON_INITIALIZER
;