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Add GCC support to ENQCMD.
[official-gcc.git] / gcc / common / config / i386 / i386-common.c
blob096aa3d47637e5a08ca176dafe4f9c150ac7d5fe
1 /* IA-32 common hooks.
2 Copyright (C) 1988-2019 Free Software Foundation, Inc.
3
4 This file is part of GCC.
5
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
10
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
19
20 #include "config.h"
21 #include "system.h"
22 #include "coretypes.h"
23 #include "diagnostic-core.h"
24 #include "tm.h"
25 #include "memmodel.h"
26 #include "tm_p.h"
27 #include "common/common-target.h"
28 #include "common/common-target-def.h"
29 #include "opts.h"
30 #include "flags.h"
31
32 /* Define a set of ISAs which are available when a given ISA is
33 enabled. MMX and SSE ISAs are handled separately. */
34
35 #define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
36 #define OPTION_MASK_ISA_3DNOW_SET \
37 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
38 #define OPTION_MASK_ISA_3DNOW_A_SET \
39 (OPTION_MASK_ISA_3DNOW_A | OPTION_MASK_ISA_3DNOW_SET)
40
41 #define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
42 #define OPTION_MASK_ISA_SSE2_SET \
43 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
44 #define OPTION_MASK_ISA_SSE3_SET \
45 (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
46 #define OPTION_MASK_ISA_SSSE3_SET \
47 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
48 #define OPTION_MASK_ISA_SSE4_1_SET \
49 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
50 #define OPTION_MASK_ISA_SSE4_2_SET \
51 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
52 #define OPTION_MASK_ISA_AVX_SET \
53 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_SSE4_2_SET \
54 | OPTION_MASK_ISA_XSAVE_SET)
55 #define OPTION_MASK_ISA_FMA_SET \
56 (OPTION_MASK_ISA_FMA | OPTION_MASK_ISA_AVX_SET)
57 #define OPTION_MASK_ISA_AVX2_SET \
58 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX_SET)
59 #define OPTION_MASK_ISA_FXSR_SET OPTION_MASK_ISA_FXSR
60 #define OPTION_MASK_ISA_XSAVE_SET OPTION_MASK_ISA_XSAVE
61 #define OPTION_MASK_ISA_XSAVEOPT_SET \
62 (OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_XSAVE_SET)
63 #define OPTION_MASK_ISA_AVX512F_SET \
64 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX2_SET)
65 #define OPTION_MASK_ISA_AVX512CD_SET \
66 (OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512F_SET)
67 #define OPTION_MASK_ISA_AVX512PF_SET \
68 (OPTION_MASK_ISA_AVX512PF | OPTION_MASK_ISA_AVX512F_SET)
69 #define OPTION_MASK_ISA_AVX512ER_SET \
70 (OPTION_MASK_ISA_AVX512ER | OPTION_MASK_ISA_AVX512F_SET)
71 #define OPTION_MASK_ISA_AVX512DQ_SET \
72 (OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512F_SET)
73 #define OPTION_MASK_ISA_AVX512BW_SET \
74 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512F_SET)
75 #define OPTION_MASK_ISA_AVX512VL_SET \
76 (OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512F_SET)
77 #define OPTION_MASK_ISA_AVX512IFMA_SET \
78 (OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512F_SET)
79 #define OPTION_MASK_ISA_AVX512VBMI_SET \
80 (OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512BW_SET)
81 #define OPTION_MASK_ISA_AVX5124FMAPS_SET OPTION_MASK_ISA_AVX5124FMAPS
82 #define OPTION_MASK_ISA_AVX5124VNNIW_SET OPTION_MASK_ISA_AVX5124VNNIW
83 #define OPTION_MASK_ISA_AVX512VBMI2_SET \
84 (OPTION_MASK_ISA_AVX512VBMI2 | OPTION_MASK_ISA_AVX512F_SET)
85 #define OPTION_MASK_ISA_AVX512VNNI_SET \
86 (OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512F_SET)
87 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET \
88 (OPTION_MASK_ISA_AVX512VPOPCNTDQ | OPTION_MASK_ISA_AVX512F_SET)
89 #define OPTION_MASK_ISA_AVX512BITALG_SET \
90 (OPTION_MASK_ISA_AVX512BITALG | OPTION_MASK_ISA_AVX512F_SET)
91 #define OPTION_MASK_ISA_AVX512BF16_SET OPTION_MASK_ISA_AVX512BF16
92 #define OPTION_MASK_ISA_RTM_SET OPTION_MASK_ISA_RTM
93 #define OPTION_MASK_ISA_PRFCHW_SET OPTION_MASK_ISA_PRFCHW
94 #define OPTION_MASK_ISA_RDSEED_SET OPTION_MASK_ISA_RDSEED
95 #define OPTION_MASK_ISA_ADX_SET OPTION_MASK_ISA_ADX
96 #define OPTION_MASK_ISA_PREFETCHWT1_SET OPTION_MASK_ISA_PREFETCHWT1
97 #define OPTION_MASK_ISA_CLFLUSHOPT_SET OPTION_MASK_ISA_CLFLUSHOPT
98 #define OPTION_MASK_ISA_XSAVES_SET \
99 (OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_XSAVE_SET)
100 #define OPTION_MASK_ISA_XSAVEC_SET \
101 (OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_XSAVE_SET)
102 #define OPTION_MASK_ISA_CLWB_SET OPTION_MASK_ISA_CLWB
103
104 /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
105 as -msse4.2. */
106 #define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
107
108 #define OPTION_MASK_ISA_SSE4A_SET \
109 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
110 #define OPTION_MASK_ISA_FMA4_SET \
111 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_SSE4A_SET \
112 | OPTION_MASK_ISA_AVX_SET)
113 #define OPTION_MASK_ISA_XOP_SET \
114 (OPTION_MASK_ISA_XOP | OPTION_MASK_ISA_FMA4_SET)
115 #define OPTION_MASK_ISA_LWP_SET \
116 OPTION_MASK_ISA_LWP
117
118 /* AES, SHA and PCLMUL need SSE2 because they use xmm registers. */
119 #define OPTION_MASK_ISA_AES_SET \
120 (OPTION_MASK_ISA_AES | OPTION_MASK_ISA_SSE2_SET)
121 #define OPTION_MASK_ISA_SHA_SET \
122 (OPTION_MASK_ISA_SHA | OPTION_MASK_ISA_SSE2_SET)
123 #define OPTION_MASK_ISA_PCLMUL_SET \
124 (OPTION_MASK_ISA_PCLMUL | OPTION_MASK_ISA_SSE2_SET)
125
126 #define OPTION_MASK_ISA_ABM_SET \
127 (OPTION_MASK_ISA_ABM | OPTION_MASK_ISA_POPCNT)
128
129 #define OPTION_MASK_ISA_PCONFIG_SET OPTION_MASK_ISA_PCONFIG
130 #define OPTION_MASK_ISA_WBNOINVD_SET OPTION_MASK_ISA_WBNOINVD
131 #define OPTION_MASK_ISA_SGX_SET OPTION_MASK_ISA_SGX
132 #define OPTION_MASK_ISA_BMI_SET OPTION_MASK_ISA_BMI
133 #define OPTION_MASK_ISA_BMI2_SET OPTION_MASK_ISA_BMI2
134 #define OPTION_MASK_ISA_LZCNT_SET OPTION_MASK_ISA_LZCNT
135 #define OPTION_MASK_ISA_TBM_SET OPTION_MASK_ISA_TBM
136 #define OPTION_MASK_ISA_POPCNT_SET OPTION_MASK_ISA_POPCNT
137 #define OPTION_MASK_ISA_CX16_SET OPTION_MASK_ISA_CX16
138 #define OPTION_MASK_ISA_SAHF_SET OPTION_MASK_ISA_SAHF
139 #define OPTION_MASK_ISA_MOVBE_SET OPTION_MASK_ISA_MOVBE
140 #define OPTION_MASK_ISA_CRC32_SET OPTION_MASK_ISA_CRC32
141
142 #define OPTION_MASK_ISA_FSGSBASE_SET OPTION_MASK_ISA_FSGSBASE
143 #define OPTION_MASK_ISA_RDRND_SET OPTION_MASK_ISA_RDRND
144 #define OPTION_MASK_ISA_PTWRITE_SET OPTION_MASK_ISA_PTWRITE
145 #define OPTION_MASK_ISA_F16C_SET \
146 (OPTION_MASK_ISA_F16C | OPTION_MASK_ISA_AVX_SET)
147 #define OPTION_MASK_ISA_MWAITX_SET OPTION_MASK_ISA_MWAITX
148 #define OPTION_MASK_ISA_CLZERO_SET OPTION_MASK_ISA_CLZERO
149 #define OPTION_MASK_ISA_PKU_SET OPTION_MASK_ISA_PKU
150 #define OPTION_MASK_ISA_RDPID_SET OPTION_MASK_ISA_RDPID
151 #define OPTION_MASK_ISA_GFNI_SET OPTION_MASK_ISA_GFNI
152 #define OPTION_MASK_ISA_SHSTK_SET OPTION_MASK_ISA_SHSTK
153 #define OPTION_MASK_ISA_VAES_SET OPTION_MASK_ISA_VAES
154 #define OPTION_MASK_ISA_VPCLMULQDQ_SET OPTION_MASK_ISA_VPCLMULQDQ
155 #define OPTION_MASK_ISA_MOVDIRI_SET OPTION_MASK_ISA_MOVDIRI
156 #define OPTION_MASK_ISA_MOVDIR64B_SET OPTION_MASK_ISA_MOVDIR64B
157 #define OPTION_MASK_ISA_WAITPKG_SET OPTION_MASK_ISA_WAITPKG
158 #define OPTION_MASK_ISA_CLDEMOTE_SET OPTION_MASK_ISA_CLDEMOTE
159 #define OPTION_MASK_ISA_ENQCMD_SET OPTION_MASK_ISA_ENQCMD
160
161 /* Define a set of ISAs which aren't available when a given ISA is
162 disabled. MMX and SSE ISAs are handled separately. */
163
164 #define OPTION_MASK_ISA_MMX_UNSET \
165 (OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_3DNOW_UNSET)
166 #define OPTION_MASK_ISA_3DNOW_UNSET \
167 (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_A_UNSET)
168 #define OPTION_MASK_ISA_3DNOW_A_UNSET OPTION_MASK_ISA_3DNOW_A
169
170 #define OPTION_MASK_ISA_SSE_UNSET \
171 (OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_SSE2_UNSET)
172 #define OPTION_MASK_ISA_SSE2_UNSET \
173 (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE3_UNSET)
174 #define OPTION_MASK_ISA_SSE3_UNSET \
175 (OPTION_MASK_ISA_SSE3 \
176 | OPTION_MASK_ISA_SSSE3_UNSET \
177 | OPTION_MASK_ISA_SSE4A_UNSET )
178 #define OPTION_MASK_ISA_SSSE3_UNSET \
179 (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE4_1_UNSET)
180 #define OPTION_MASK_ISA_SSE4_1_UNSET \
181 (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2_UNSET)
182 #define OPTION_MASK_ISA_SSE4_2_UNSET \
183 (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_AVX_UNSET )
184 #define OPTION_MASK_ISA_AVX_UNSET \
185 (OPTION_MASK_ISA_AVX | OPTION_MASK_ISA_FMA_UNSET \
186 | OPTION_MASK_ISA_FMA4_UNSET | OPTION_MASK_ISA_F16C_UNSET \
187 | OPTION_MASK_ISA_AVX2_UNSET | OPTION_MASK_ISA_XSAVE_UNSET)
188 #define OPTION_MASK_ISA_FMA_UNSET OPTION_MASK_ISA_FMA
189 #define OPTION_MASK_ISA_FXSR_UNSET OPTION_MASK_ISA_FXSR
190 #define OPTION_MASK_ISA_XSAVE_UNSET \
191 (OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_XSAVEOPT_UNSET \
192 | OPTION_MASK_ISA_XSAVES_UNSET | OPTION_MASK_ISA_XSAVEC_UNSET)
193 #define OPTION_MASK_ISA_XSAVEOPT_UNSET OPTION_MASK_ISA_XSAVEOPT
194 #define OPTION_MASK_ISA_AVX2_UNSET \
195 (OPTION_MASK_ISA_AVX2 | OPTION_MASK_ISA_AVX512F_UNSET)
196 #define OPTION_MASK_ISA_AVX512F_UNSET \
197 (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \
198 | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \
199 | OPTION_MASK_ISA_AVX512DQ_UNSET | OPTION_MASK_ISA_AVX512BW_UNSET \
200 | OPTION_MASK_ISA_AVX512VL_UNSET | OPTION_MASK_ISA_AVX512IFMA_UNSET \
201 | OPTION_MASK_ISA_AVX512VBMI2_UNSET \
202 | OPTION_MASK_ISA_AVX512VNNI_UNSET \
203 | OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET \
204 | OPTION_MASK_ISA_AVX512BITALG_UNSET)
205 #define OPTION_MASK_ISA_AVX512CD_UNSET OPTION_MASK_ISA_AVX512CD
206 #define OPTION_MASK_ISA_AVX512PF_UNSET OPTION_MASK_ISA_AVX512PF
207 #define OPTION_MASK_ISA_AVX512ER_UNSET OPTION_MASK_ISA_AVX512ER
208 #define OPTION_MASK_ISA_AVX512DQ_UNSET OPTION_MASK_ISA_AVX512DQ
209 #define OPTION_MASK_ISA_AVX512BW_UNSET \
210 (OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VBMI_UNSET)
211 #define OPTION_MASK_ISA_AVX512VL_UNSET OPTION_MASK_ISA_AVX512VL
212 #define OPTION_MASK_ISA_AVX512IFMA_UNSET OPTION_MASK_ISA_AVX512IFMA
213 #define OPTION_MASK_ISA_AVX512VBMI_UNSET OPTION_MASK_ISA_AVX512VBMI
214 #define OPTION_MASK_ISA_AVX5124FMAPS_UNSET OPTION_MASK_ISA_AVX5124FMAPS
215 #define OPTION_MASK_ISA_AVX5124VNNIW_UNSET OPTION_MASK_ISA_AVX5124VNNIW
216 #define OPTION_MASK_ISA_AVX512VBMI2_UNSET OPTION_MASK_ISA_AVX512VBMI2
217 #define OPTION_MASK_ISA_AVX512VNNI_UNSET OPTION_MASK_ISA_AVX512VNNI
218 #define OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET OPTION_MASK_ISA_AVX512VPOPCNTDQ
219 #define OPTION_MASK_ISA_AVX512BITALG_UNSET OPTION_MASK_ISA_AVX512BITALG
220 #define OPTION_MASK_ISA_AVX512BF16_UNSET OPTION_MASK_ISA_AVX512BF16
221 #define OPTION_MASK_ISA_RTM_UNSET OPTION_MASK_ISA_RTM
222 #define OPTION_MASK_ISA_PRFCHW_UNSET OPTION_MASK_ISA_PRFCHW
223 #define OPTION_MASK_ISA_RDSEED_UNSET OPTION_MASK_ISA_RDSEED
224 #define OPTION_MASK_ISA_ADX_UNSET OPTION_MASK_ISA_ADX
225 #define OPTION_MASK_ISA_PREFETCHWT1_UNSET OPTION_MASK_ISA_PREFETCHWT1
226 #define OPTION_MASK_ISA_CLFLUSHOPT_UNSET OPTION_MASK_ISA_CLFLUSHOPT
227 #define OPTION_MASK_ISA_XSAVEC_UNSET OPTION_MASK_ISA_XSAVEC
228 #define OPTION_MASK_ISA_XSAVES_UNSET OPTION_MASK_ISA_XSAVES
229 #define OPTION_MASK_ISA_CLWB_UNSET OPTION_MASK_ISA_CLWB
230 #define OPTION_MASK_ISA_MWAITX_UNSET OPTION_MASK_ISA_MWAITX
231 #define OPTION_MASK_ISA_CLZERO_UNSET OPTION_MASK_ISA_CLZERO
232 #define OPTION_MASK_ISA_PKU_UNSET OPTION_MASK_ISA_PKU
233 #define OPTION_MASK_ISA_RDPID_UNSET OPTION_MASK_ISA_RDPID
234 #define OPTION_MASK_ISA_GFNI_UNSET OPTION_MASK_ISA_GFNI
235 #define OPTION_MASK_ISA_SHSTK_UNSET OPTION_MASK_ISA_SHSTK
236 #define OPTION_MASK_ISA_VAES_UNSET OPTION_MASK_ISA_VAES
237 #define OPTION_MASK_ISA_VPCLMULQDQ_UNSET OPTION_MASK_ISA_VPCLMULQDQ
238 #define OPTION_MASK_ISA_MOVDIRI_UNSET OPTION_MASK_ISA_MOVDIRI
239 #define OPTION_MASK_ISA_MOVDIR64B_UNSET OPTION_MASK_ISA_MOVDIR64B
240 #define OPTION_MASK_ISA_WAITPKG_UNSET OPTION_MASK_ISA_WAITPKG
241 #define OPTION_MASK_ISA_CLDEMOTE_UNSET OPTION_MASK_ISA_CLDEMOTE
242 #define OPTION_MASK_ISA_ENQCMD_UNSET OPTION_MASK_ISA_ENQCMD
243
244 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same
245 as -mno-sse4.1. */
246 #define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
247
248 #define OPTION_MASK_ISA_SSE4A_UNSET \
249 (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_FMA4_UNSET)
250
251 #define OPTION_MASK_ISA_FMA4_UNSET \
252 (OPTION_MASK_ISA_FMA4 | OPTION_MASK_ISA_XOP_UNSET)
253 #define OPTION_MASK_ISA_XOP_UNSET OPTION_MASK_ISA_XOP
254 #define OPTION_MASK_ISA_LWP_UNSET OPTION_MASK_ISA_LWP
255
256 #define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
257 #define OPTION_MASK_ISA_SHA_UNSET OPTION_MASK_ISA_SHA
258 #define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
259 #define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
260 #define OPTION_MASK_ISA_PCONFIG_UNSET OPTION_MASK_ISA_PCONFIG
261 #define OPTION_MASK_ISA_WBNOINVD_UNSET OPTION_MASK_ISA_WBNOINVD
262 #define OPTION_MASK_ISA_SGX_UNSET OPTION_MASK_ISA_SGX
263 #define OPTION_MASK_ISA_BMI_UNSET OPTION_MASK_ISA_BMI
264 #define OPTION_MASK_ISA_BMI2_UNSET OPTION_MASK_ISA_BMI2
265 #define OPTION_MASK_ISA_LZCNT_UNSET OPTION_MASK_ISA_LZCNT
266 #define OPTION_MASK_ISA_TBM_UNSET OPTION_MASK_ISA_TBM
267 #define OPTION_MASK_ISA_POPCNT_UNSET OPTION_MASK_ISA_POPCNT
268 #define OPTION_MASK_ISA_CX16_UNSET OPTION_MASK_ISA_CX16
269 #define OPTION_MASK_ISA_SAHF_UNSET OPTION_MASK_ISA_SAHF
270 #define OPTION_MASK_ISA_MOVBE_UNSET OPTION_MASK_ISA_MOVBE
271 #define OPTION_MASK_ISA_CRC32_UNSET OPTION_MASK_ISA_CRC32
272
273 #define OPTION_MASK_ISA_FSGSBASE_UNSET OPTION_MASK_ISA_FSGSBASE
274 #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
275 #define OPTION_MASK_ISA_PTWRITE_UNSET OPTION_MASK_ISA_PTWRITE
276 #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
277
278 #define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \
279 (OPTION_MASK_ISA_MMX_UNSET \
280 | OPTION_MASK_ISA_SSE_UNSET)
281
282 #define OPTION_MASK_ISA2_AVX512F_UNSET \
283 (OPTION_MASK_ISA_AVX512BF16_UNSET \
284 | OPTION_MASK_ISA_AVX5124FMAPS_UNSET \
285 | OPTION_MASK_ISA_AVX5124VNNIW_UNSET)
286 #define OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET \
287 (OPTION_MASK_ISA2_AVX512F_UNSET)
288
289 #define OPTION_MASK_ISA2_AVX512BW_UNSET OPTION_MASK_ISA_AVX512BF16_UNSET
290
291 /* Set 1 << value as value of -malign-FLAG option. */
292
293 static void
294 set_malign_value (const char **flag, unsigned value)
295 {
296 char *r = XNEWVEC (char, 6);
297 sprintf (r, "%d", 1 << value);
298 *flag = r;
299 }
300
301 /* Implement TARGET_HANDLE_OPTION. */
302
303 bool
304 ix86_handle_option (struct gcc_options *opts,
305 struct gcc_options *opts_set ATTRIBUTE_UNUSED,
306 const struct cl_decoded_option *decoded,
307 location_t loc)
308 {
309 size_t code = decoded->opt_index;
310 int value = decoded->value;
311
312 switch (code)
313 {
314 case OPT_mgeneral_regs_only:
315 if (value)
316 {
317 /* Disable MMX, SSE and x87 instructions if only
318 general registers are allowed. */
319 opts->x_ix86_isa_flags
320 &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
321 opts->x_ix86_isa_flags2
322 &= ~OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET;
323 opts->x_ix86_isa_flags_explicit
324 |= OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
325 opts->x_ix86_isa_flags2_explicit
326 |= OPTION_MASK_ISA2_GENERAL_REGS_ONLY_UNSET;
327
328 opts->x_target_flags &= ~MASK_80387;
329 }
330 else
331 gcc_unreachable ();
332 return true;
333
334 case OPT_mmmx:
335 if (value)
336 {
337 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
338 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_SET;
339 }
340 else
341 {
342 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
343 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
344 }
345 return true;
346
347 case OPT_m3dnow:
348 if (value)
349 {
350 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
351 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_SET;
352 }
353 else
354 {
355 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
356 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
357 }
358 return true;
359
360 case OPT_m3dnowa:
361 if (value)
362 {
363 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A_SET;
364 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_SET;
365 }
366 else
367 {
368 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_A_UNSET;
369 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_A_UNSET;
370 }
371 return true;
372
373 case OPT_msse:
374 if (value)
375 {
376 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
377 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_SET;
378 }
379 else
380 {
381 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
382 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
383 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
384 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
385 }
386 return true;
387
388 case OPT_msse2:
389 if (value)
390 {
391 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
392 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_SET;
393 }
394 else
395 {
396 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
397 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
398 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
399 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
400 }
401 return true;
402
403 case OPT_msse3:
404 if (value)
405 {
406 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
407 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_SET;
408 }
409 else
410 {
411 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
412 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
413 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
414 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
415 }
416 return true;
417
418 case OPT_mssse3:
419 if (value)
420 {
421 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
422 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_SET;
423 }
424 else
425 {
426 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
427 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
428 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
429 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
430 }
431 return true;
432
433 case OPT_msse4_1:
434 if (value)
435 {
436 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
437 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_SET;
438 }
439 else
440 {
441 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
442 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
443 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
444 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
445 }
446 return true;
447
448 case OPT_msse4_2:
449 if (value)
450 {
451 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
452 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_SET;
453 }
454 else
455 {
456 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
457 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
458 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
459 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
460 }
461 return true;
462
463 case OPT_mavx:
464 if (value)
465 {
466 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX_SET;
467 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_SET;
468 }
469 else
470 {
471 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX_UNSET;
472 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX_UNSET;
473 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
474 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
475 }
476 return true;
477
478 case OPT_mavx2:
479 if (value)
480 {
481 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET;
482 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET;
483 }
484 else
485 {
486 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX2_UNSET;
487 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_UNSET;
488 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
489 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
490 }
491 return true;
492
493 case OPT_mavx512f:
494 if (value)
495 {
496 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
497 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
498 }
499 else
500 {
501 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512F_UNSET;
502 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET;
503 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
504 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
505 }
506 return true;
507
508 case OPT_mavx512cd:
509 if (value)
510 {
511 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD_SET;
512 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_SET;
513 }
514 else
515 {
516 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET;
517 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET;
518 }
519 return true;
520
521 case OPT_mavx512pf:
522 if (value)
523 {
524 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512PF_SET;
525 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_SET;
526 }
527 else
528 {
529 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512PF_UNSET;
530 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512PF_UNSET;
531 }
532 return true;
533
534 case OPT_mavx512er:
535 if (value)
536 {
537 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512ER_SET;
538 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_SET;
539 }
540 else
541 {
542 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512ER_UNSET;
543 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512ER_UNSET;
544 }
545 return true;
546
547 case OPT_mrdpid:
548 if (value)
549 {
550 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID_SET;
551 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_RDPID_SET;
552 }
553 else
554 {
555 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_RDPID_UNSET;
556 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_RDPID_UNSET;
557 }
558 return true;
559
560 case OPT_mgfni:
561 if (value)
562 {
563 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI_SET;
564 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_SET;
565 }
566 else
567 {
568 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_GFNI_UNSET;
569 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_GFNI_UNSET;
570 }
571 return true;
572
573 case OPT_mshstk:
574 if (value)
575 {
576 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHSTK_SET;
577 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_SET;
578 }
579 else
580 {
581 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHSTK_UNSET;
582 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHSTK_UNSET;
583 }
584 return true;
585
586 case OPT_mvaes:
587 if (value)
588 {
589 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_VAES_SET;
590 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_VAES_SET;
591 }
592 else
593 {
594 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_VAES_UNSET;
595 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_VAES_UNSET;
596 }
597 return true;
598
599 case OPT_mvpclmulqdq:
600 if (value)
601 {
602 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
603 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_SET;
604 }
605 else
606 {
607 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
608 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_VPCLMULQDQ_UNSET;
609 }
610 return true;
611
612 case OPT_mmovdiri:
613 if (value)
614 {
615 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVDIRI_SET;
616 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_SET;
617 }
618 else
619 {
620 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_MOVDIRI_UNSET;
621 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_MOVDIRI_UNSET;
622 }
623 return true;
624
625 case OPT_mmovdir64b:
626 if (value)
627 {
628 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVDIR64B_SET;
629 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVDIR64B_SET;
630 }
631 else
632 {
633 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MOVDIR64B_UNSET;
634 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVDIR64B_UNSET;
635 }
636 return true;
637
638 case OPT_mcldemote:
639 if (value)
640 {
641 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CLDEMOTE_SET;
642 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLDEMOTE_SET;
643 }
644 else
645 {
646 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CLDEMOTE_UNSET;
647 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLDEMOTE_UNSET;
648 }
649 return true;
650
651 case OPT_mwaitpkg:
652 if (value)
653 {
654 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_WAITPKG_SET;
655 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WAITPKG_SET;
656 }
657 else
658 {
659 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_WAITPKG_UNSET;
660 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WAITPKG_UNSET;
661 }
662 return true;
663
664 case OPT_menqcmd:
665 if (value)
666 {
667 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_ENQCMD_SET;
668 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_ENQCMD_SET;
669 }
670 else
671 {
672 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_ENQCMD_UNSET;
673 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_ENQCMD_UNSET;
674 }
675 return true;
676
677 case OPT_mavx5124fmaps:
678 if (value)
679 {
680 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124FMAPS_SET;
681 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124FMAPS_SET;
682 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
683 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
684 }
685 else
686 {
687 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX5124FMAPS_UNSET;
688 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124FMAPS_UNSET;
689 }
690 return true;
691
692 case OPT_mavx5124vnniw:
693 if (value)
694 {
695 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124VNNIW_SET;
696 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124VNNIW_SET;
697 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F_SET;
698 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_SET;
699 }
700 else
701 {
702 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX5124VNNIW_UNSET;
703 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX5124VNNIW_UNSET;
704 }
705 return true;
706
707 case OPT_mavx512vbmi2:
708 if (value)
709 {
710 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI2_SET;
711 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_SET;
712 }
713 else
714 {
715 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET;
716 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET;
717 }
718 return true;
719
720 case OPT_mavx512vnni:
721 if (value)
722 {
723 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VNNI_SET;
724 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_SET;
725 }
726 else
727 {
728 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET;
729 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET;
730 }
731 return true;
732
733 case OPT_mavx512vpopcntdq:
734 if (value)
735 {
736 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
737 opts->x_ix86_isa_flags_explicit
738 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_SET;
739 }
740 else
741 {
742 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
743 opts->x_ix86_isa_flags_explicit
744 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET;
745 }
746 return true;
747
748 case OPT_mavx512bitalg:
749 if (value)
750 {
751 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BITALG_SET;
752 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BITALG_SET;
753 }
754 else
755 {
756 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET;
757 opts->x_ix86_isa_flags_explicit
758 |= OPTION_MASK_ISA_AVX512BITALG_UNSET;
759 }
760 return true;
761
762 case OPT_mavx512bf16:
763 if (value)
764 {
765 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX512BF16_SET;
766 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX512BF16_SET;
767 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
768 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
769 }
770 else
771 {
772 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_AVX512BF16_UNSET;
773 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_AVX512BF16_UNSET;
774 }
775 return true;
776
777 case OPT_msgx:
778 if (value)
779 {
780 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX_SET;
781 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_SET;
782 }
783 else
784 {
785 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_SGX_UNSET;
786 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_SGX_UNSET;
787 }
788 return true;
789
790 case OPT_mpconfig:
791 if (value)
792 {
793 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_PCONFIG_SET;
794 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PCONFIG_SET;
795 }
796 else
797 {
798 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_PCONFIG_UNSET;
799 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PCONFIG_UNSET;
800 }
801 return true;
802
803 case OPT_mwbnoinvd:
804 if (value)
805 {
806 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_WBNOINVD_SET;
807 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WBNOINVD_SET;
808 }
809 else
810 {
811 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_WBNOINVD_UNSET;
812 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_WBNOINVD_UNSET;
813 }
814 return true;
815
816 case OPT_mavx512dq:
817 if (value)
818 {
819 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ_SET;
820 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_SET;
821 }
822 else
823 {
824 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET;
825 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET;
826 }
827 return true;
828
829 case OPT_mavx512bw:
830 if (value)
831 {
832 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW_SET;
833 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_SET;
834 }
835 else
836 {
837 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BW_UNSET;
838 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET;
839 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BW_UNSET;
840 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BW_UNSET;
841 }
842 return true;
843
844 case OPT_mavx512vl:
845 if (value)
846 {
847 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL_SET;
848 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_SET;
849 }
850 else
851 {
852 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET;
853 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET;
854 }
855 return true;
856
857 case OPT_mavx512ifma:
858 if (value)
859 {
860 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA_SET;
861 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_SET;
862 }
863 else
864 {
865 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET;
866 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET;
867 }
868 return true;
869
870 case OPT_mavx512vbmi:
871 if (value)
872 {
873 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI_SET;
874 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_SET;
875 }
876 else
877 {
878 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET;
879 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET;
880 }
881 return true;
882
883 case OPT_mfma:
884 if (value)
885 {
886 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA_SET;
887 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_SET;
888 }
889 else
890 {
891 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA_UNSET;
892 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA_UNSET;
893 }
894 return true;
895
896 case OPT_mrtm:
897 if (value)
898 {
899 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM_SET;
900 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_SET;
901 }
902 else
903 {
904 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RTM_UNSET;
905 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RTM_UNSET;
906 }
907 return true;
908
909 case OPT_msse4:
910 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
911 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
912 return true;
913
914 case OPT_mno_sse4:
915 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_UNSET;
916 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_UNSET;
917 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET;
918 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET;
919 return true;
920
921 case OPT_msse4a:
922 if (value)
923 {
924 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
925 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_SET;
926 }
927 else
928 {
929 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
930 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
931 }
932 return true;
933
934 case OPT_mfma4:
935 if (value)
936 {
937 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4_SET;
938 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_SET;
939 }
940 else
941 {
942 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FMA4_UNSET;
943 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FMA4_UNSET;
944 }
945 return true;
946
947 case OPT_mxop:
948 if (value)
949 {
950 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP_SET;
951 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_SET;
952 }
953 else
954 {
955 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XOP_UNSET;
956 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XOP_UNSET;
957 }
958 return true;
959
960 case OPT_mlwp:
961 if (value)
962 {
963 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP_SET;
964 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_SET;
965 }
966 else
967 {
968 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LWP_UNSET;
969 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LWP_UNSET;
970 }
971 return true;
972
973 case OPT_mabm:
974 if (value)
975 {
976 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM_SET;
977 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_SET;
978 }
979 else
980 {
981 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ABM_UNSET;
982 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ABM_UNSET;
983 }
984 return true;
985
986 case OPT_mbmi:
987 if (value)
988 {
989 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI_SET;
990 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_SET;
991 }
992 else
993 {
994 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI_UNSET;
995 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI_UNSET;
996 }
997 return true;
998
999 case OPT_mbmi2:
1000 if (value)
1001 {
1002 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2_SET;
1003 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_SET;
1004 }
1005 else
1006 {
1007 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_BMI2_UNSET;
1008 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_BMI2_UNSET;
1009 }
1010 return true;
1011
1012 case OPT_mlzcnt:
1013 if (value)
1014 {
1015 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT_SET;
1016 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_SET;
1017 }
1018 else
1019 {
1020 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_LZCNT_UNSET;
1021 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_LZCNT_UNSET;
1022 }
1023 return true;
1024
1025 case OPT_mtbm:
1026 if (value)
1027 {
1028 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM_SET;
1029 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_SET;
1030 }
1031 else
1032 {
1033 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_TBM_UNSET;
1034 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_TBM_UNSET;
1035 }
1036 return true;
1037
1038 case OPT_mpopcnt:
1039 if (value)
1040 {
1041 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT_SET;
1042 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_SET;
1043 }
1044 else
1045 {
1046 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_POPCNT_UNSET;
1047 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_POPCNT_UNSET;
1048 }
1049 return true;
1050
1051 case OPT_msahf:
1052 if (value)
1053 {
1054 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF_SET;
1055 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_SET;
1056 }
1057 else
1058 {
1059 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SAHF_UNSET;
1060 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SAHF_UNSET;
1061 }
1062 return true;
1063
1064 case OPT_mcx16:
1065 if (value)
1066 {
1067 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CX16_SET;
1068 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CX16_SET;
1069 }
1070 else
1071 {
1072 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CX16_UNSET;
1073 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CX16_UNSET;
1074 }
1075 return true;
1076
1077 case OPT_mmovbe:
1078 if (value)
1079 {
1080 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVBE_SET;
1081 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVBE_SET;
1082 }
1083 else
1084 {
1085 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MOVBE_UNSET;
1086 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MOVBE_UNSET;
1087 }
1088 return true;
1089
1090 case OPT_mcrc32:
1091 if (value)
1092 {
1093 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CRC32_SET;
1094 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_SET;
1095 }
1096 else
1097 {
1098 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CRC32_UNSET;
1099 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CRC32_UNSET;
1100 }
1101 return true;
1102
1103 case OPT_maes:
1104 if (value)
1105 {
1106 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AES_SET;
1107 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_SET;
1108 }
1109 else
1110 {
1111 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AES_UNSET;
1112 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AES_UNSET;
1113 }
1114 return true;
1115
1116 case OPT_msha:
1117 if (value)
1118 {
1119 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SHA_SET;
1120 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_SET;
1121 }
1122 else
1123 {
1124 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_SHA_UNSET;
1125 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_SHA_UNSET;
1126 }
1127 return true;
1128
1129 case OPT_mpclmul:
1130 if (value)
1131 {
1132 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL_SET;
1133 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_SET;
1134 }
1135 else
1136 {
1137 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PCLMUL_UNSET;
1138 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PCLMUL_UNSET;
1139 }
1140 return true;
1141
1142 case OPT_mfsgsbase:
1143 if (value)
1144 {
1145 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE_SET;
1146 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_SET;
1147 }
1148 else
1149 {
1150 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FSGSBASE_UNSET;
1151 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FSGSBASE_UNSET;
1152 }
1153 return true;
1154
1155 case OPT_mrdrnd:
1156 if (value)
1157 {
1158 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND_SET;
1159 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_SET;
1160 }
1161 else
1162 {
1163 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDRND_UNSET;
1164 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDRND_UNSET;
1165 }
1166 return true;
1167
1168 case OPT_mptwrite:
1169 if (value)
1170 {
1171 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_PTWRITE_SET;
1172 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PTWRITE_SET;
1173 }
1174 else
1175 {
1176 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_PTWRITE_UNSET;
1177 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_PTWRITE_UNSET;
1178 }
1179 return true;
1180
1181 case OPT_mf16c:
1182 if (value)
1183 {
1184 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C_SET;
1185 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_SET;
1186 }
1187 else
1188 {
1189 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_F16C_UNSET;
1190 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_F16C_UNSET;
1191 }
1192 return true;
1193
1194 case OPT_mfxsr:
1195 if (value)
1196 {
1197 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR_SET;
1198 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_SET;
1199 }
1200 else
1201 {
1202 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_FXSR_UNSET;
1203 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_FXSR_UNSET;
1204 }
1205 return true;
1206
1207 case OPT_mxsave:
1208 if (value)
1209 {
1210 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE_SET;
1211 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_SET;
1212 }
1213 else
1214 {
1215 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVE_UNSET;
1216 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVE_UNSET;
1217 }
1218 return true;
1219
1220 case OPT_mxsaveopt:
1221 if (value)
1222 {
1223 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT_SET;
1224 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_SET;
1225 }
1226 else
1227 {
1228 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEOPT_UNSET;
1229 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEOPT_UNSET;
1230 }
1231 return true;
1232
1233 case OPT_mxsavec:
1234 if (value)
1235 {
1236 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC_SET;
1237 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_SET;
1238 }
1239 else
1240 {
1241 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVEC_UNSET;
1242 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVEC_UNSET;
1243 }
1244 return true;
1245
1246 case OPT_mxsaves:
1247 if (value)
1248 {
1249 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES_SET;
1250 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_SET;
1251 }
1252 else
1253 {
1254 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_XSAVES_UNSET;
1255 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_XSAVES_UNSET;
1256 }
1257 return true;
1258
1259 case OPT_mrdseed:
1260 if (value)
1261 {
1262 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED_SET;
1263 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_SET;
1264 }
1265 else
1266 {
1267 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_RDSEED_UNSET;
1268 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_RDSEED_UNSET;
1269 }
1270 return true;
1271
1272 case OPT_mprfchw:
1273 if (value)
1274 {
1275 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW_SET;
1276 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_SET;
1277 }
1278 else
1279 {
1280 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PRFCHW_UNSET;
1281 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PRFCHW_UNSET;
1282 }
1283 return true;
1284
1285 case OPT_madx:
1286 if (value)
1287 {
1288 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX_SET;
1289 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_SET;
1290 }
1291 else
1292 {
1293 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_ADX_UNSET;
1294 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_ADX_UNSET;
1295 }
1296 return true;
1297
1298 case OPT_mprefetchwt1:
1299 if (value)
1300 {
1301 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1_SET;
1302 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_SET;
1303 }
1304 else
1305 {
1306 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PREFETCHWT1_UNSET;
1307 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PREFETCHWT1_UNSET;
1308 }
1309 return true;
1310
1311 case OPT_mclflushopt:
1312 if (value)
1313 {
1314 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1315 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_SET;
1316 }
1317 else
1318 {
1319 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1320 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLFLUSHOPT_UNSET;
1321 }
1322 return true;
1323
1324 case OPT_mclwb:
1325 if (value)
1326 {
1327 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB_SET;
1328 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_SET;
1329 }
1330 else
1331 {
1332 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_CLWB_UNSET;
1333 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_CLWB_UNSET;
1334 }
1335 return true;
1336
1337 case OPT_mmwaitx:
1338 if (value)
1339 {
1340 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MWAITX_SET;
1341 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MWAITX_SET;
1342 }
1343 else
1344 {
1345 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_MWAITX_UNSET;
1346 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_MWAITX_UNSET;
1347 }
1348 return true;
1349
1350 case OPT_mclzero:
1351 if (value)
1352 {
1353 opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CLZERO_SET;
1354 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLZERO_SET;
1355 }
1356 else
1357 {
1358 opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA_CLZERO_UNSET;
1359 opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA_CLZERO_UNSET;
1360 }
1361 return true;
1362
1363 case OPT_mpku:
1364 if (value)
1365 {
1366 opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU_SET;
1367 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_SET;
1368 }
1369 else
1370 {
1371 opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_PKU_UNSET;
1372 opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_PKU_UNSET;
1373 }
1374 return true;
1375
1376
1377 case OPT_malign_loops_:
1378 warning_at (loc, 0, "%<-malign-loops%> is obsolete, "
1379 "use %<-falign-loops%>");
1380 if (value > MAX_CODE_ALIGN)
1381 error_at (loc, "%<-malign-loops=%d%> is not between 0 and %d",
1382 value, MAX_CODE_ALIGN);
1383 else
1384 set_malign_value (&opts->x_str_align_loops, value);
1385 return true;
1386
1387 case OPT_malign_jumps_:
1388 warning_at (loc, 0, "%<-malign-jumps%> is obsolete, "
1389 "use %<-falign-jumps%>");
1390 if (value > MAX_CODE_ALIGN)
1391 error_at (loc, "%<-malign-jumps=%d%> is not between 0 and %d",
1392 value, MAX_CODE_ALIGN);
1393 else
1394 set_malign_value (&opts->x_str_align_jumps, value);
1395 return true;
1396
1397 case OPT_malign_functions_:
1398 warning_at (loc, 0,
1399 "%<-malign-functions%> is obsolete, "
1400 "use %<-falign-functions%>");
1401 if (value > MAX_CODE_ALIGN)
1402 error_at (loc, "%<-malign-functions=%d%> is not between 0 and %d",
1403 value, MAX_CODE_ALIGN);
1404 else
1405 set_malign_value (&opts->x_str_align_functions, value);
1406 return true;
1407
1408 case OPT_mbranch_cost_:
1409 if (value > 5)
1410 {
1411 error_at (loc, "%<-mbranch-cost=%d%> is not between 0 and 5", value);
1412 opts->x_ix86_branch_cost = 5;
1413 }
1414 return true;
1415
1416 default:
1417 return true;
1418 }
1419 }
1420
1421 static const struct default_options ix86_option_optimization_table[] =
1422 {
1423 /* Enable redundant extension instructions removal at -O2 and higher. */
1424 { OPT_LEVELS_2_PLUS, OPT_free, NULL, 1 },
1425 /* Enable function splitting at -O2 and higher. */
1426 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_and_partition, NULL, 1 },
1427 /* The STC algorithm produces the smallest code at -Os, for x86. */
1428 { OPT_LEVELS_2_PLUS, OPT_freorder_blocks_algorithm_, NULL,
1429 REORDER_BLOCKS_ALGORITHM_STC },
1430 /* Turn off -fschedule-insns by default. It tends to make the
1431 problem with not enough registers even worse. */
1432 { OPT_LEVELS_ALL, OPT_fschedule_insns, NULL, 0 },
1433
1434 #ifdef SUBTARGET_OPTIMIZATION_OPTIONS
1435 SUBTARGET_OPTIMIZATION_OPTIONS,
1436 #endif
1437 { OPT_LEVELS_NONE, 0, NULL, 0 }
1438 };
1439
1440 /* Implement TARGET_OPTION_INIT_STRUCT. */
1441
1442 static void
1443 ix86_option_init_struct (struct gcc_options *opts)
1444 {
1445 if (TARGET_MACHO)
1446 /* The Darwin libraries never set errno, so we might as well
1447 avoid calling them when that's the only reason we would. */
1448 opts->x_flag_errno_math = 0;
1449
1450 opts->x_flag_pcc_struct_return = 2;
1451 opts->x_flag_asynchronous_unwind_tables = 2;
1452 }
1453
1454 /* On the x86 -fsplit-stack and -fstack-protector both use the same
1455 field in the TCB, so they cannot be used together. */
1456
1457 static bool
1458 ix86_supports_split_stack (bool report ATTRIBUTE_UNUSED,
1459 struct gcc_options *opts ATTRIBUTE_UNUSED)
1460 {
1461 bool ret = true;
1462
1463 #ifndef TARGET_THREAD_SPLIT_STACK_OFFSET
1464 if (report)
1465 error ("%<-fsplit-stack%> currently only supported on GNU/Linux");
1466 ret = false;
1467 #else
1468 if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE)
1469 {
1470 if (report)
1471 error ("%<-fsplit-stack%> requires "
1472 "assembler support for CFI directives");
1473 ret = false;
1474 }
1475 #endif
1476
1477 return ret;
1478 }
1479
1480 /* Implement TARGET_EXCEPT_UNWIND_INFO. */
1481
1482 static enum unwind_info_type
1483 i386_except_unwind_info (struct gcc_options *opts)
1484 {
1485 /* Honor the --enable-sjlj-exceptions configure switch. */
1486 #ifdef CONFIG_SJLJ_EXCEPTIONS
1487 if (CONFIG_SJLJ_EXCEPTIONS)
1488 return UI_SJLJ;
1489 #endif
1490
1491 /* On windows 64, prefer SEH exceptions over anything else. */
1492 if (TARGET_64BIT && DEFAULT_ABI == MS_ABI && opts->x_flag_unwind_tables)
1493 return UI_SEH;
1494
1495 if (DWARF2_UNWIND_INFO)
1496 return UI_DWARF2;
1497
1498 return UI_SJLJ;
1499 }
1500
1501 #undef TARGET_EXCEPT_UNWIND_INFO
1502 #define TARGET_EXCEPT_UNWIND_INFO i386_except_unwind_info
1503
1504 #undef TARGET_DEFAULT_TARGET_FLAGS
1505 #define TARGET_DEFAULT_TARGET_FLAGS \
1506 (TARGET_DEFAULT \
1507 | TARGET_SUBTARGET_DEFAULT \
1508 | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
1509
1510 #undef TARGET_HANDLE_OPTION
1511 #define TARGET_HANDLE_OPTION ix86_handle_option
1512
1513 #undef TARGET_OPTION_OPTIMIZATION_TABLE
1514 #define TARGET_OPTION_OPTIMIZATION_TABLE ix86_option_optimization_table
1515 #undef TARGET_OPTION_INIT_STRUCT
1516 #define TARGET_OPTION_INIT_STRUCT ix86_option_init_struct
1517
1518 #undef TARGET_SUPPORTS_SPLIT_STACK
1519 #define TARGET_SUPPORTS_SPLIT_STACK ix86_supports_split_stack
1520
1521 /* This table must be in sync with enum processor_type in i386.h. */
1522 const char *const processor_names[] =
1523 {
1524 "generic",
1525 "i386",
1526 "i486",
1527 "pentium",
1528 "lakemont",
1529 "pentiumpro",
1530 "pentium4",
1531 "nocona",
1532 "core2",
1533 "nehalem",
1534 "sandybridge",
1535 "haswell",
1536 "bonnell",
1537 "silvermont",
1538 "goldmont",
1539 "goldmont-plus",
1540 "tremont",
1541 "knl",
1542 "knm",
1543 "skylake",
1544 "skylake-avx512",
1545 "cannonlake",
1546 "icelake-client",
1547 "icelake-server",
1548 "cascadelake",
1549 "intel",
1550 "geode",
1551 "k6",
1552 "athlon",
1553 "k8",
1554 "amdfam10",
1555 "bdver1",
1556 "bdver2",
1557 "bdver3",
1558 "bdver4",
1559 "btver1",
1560 "btver2",
1561 "znver1",
1562 "znver2"
1563 };
1564
1565 /* Guarantee that the array is aligned with enum processor_type. */
1566 STATIC_ASSERT (ARRAY_SIZE (processor_names) == PROCESSOR_max);
1567
1568 const pta processor_alias_table[] =
1569 {
1570 {"i386", PROCESSOR_I386, CPU_NONE, 0},
1571 {"i486", PROCESSOR_I486, CPU_NONE, 0},
1572 {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
1573 {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
1574 {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
1575 {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
1576 {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
1577 {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
1578 {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
1579 {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
1580 {"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1581 PTA_MMX | PTA_SSE | PTA_FXSR},
1582 {"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1583 PTA_MMX | PTA_SSE | PTA_FXSR},
1584 {"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1585 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
1586 {"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1587 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
1588 {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
1589 {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
1590 {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
1591 {"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1592 PTA_MMX | PTA_SSE | PTA_FXSR},
1593 {"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1594 PTA_MMX | PTA_SSE | PTA_FXSR},
1595 {"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
1596 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
1597 {"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
1598 PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
1599 {"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
1600 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
1601 {"prescott", PROCESSOR_NOCONA, CPU_NONE,
1602 PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
1603 {"nocona", PROCESSOR_NOCONA, CPU_NONE,
1604 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1605 | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
1606 {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
1607 {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
1608 {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
1609 {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
1610 {"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
1611 PTA_SANDYBRIDGE},
1612 {"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
1613 PTA_SANDYBRIDGE},
1614 {"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
1615 PTA_IVYBRIDGE},
1616 {"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
1617 PTA_IVYBRIDGE},
1618 {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
1619 {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
1620 {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
1621 {"skylake", PROCESSOR_SKYLAKE, CPU_HASWELL, PTA_SKYLAKE},
1622 {"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
1623 PTA_SKYLAKE_AVX512},
1624 {"cannonlake", PROCESSOR_CANNONLAKE, CPU_HASWELL, PTA_CANNONLAKE},
1625 {"icelake-client", PROCESSOR_ICELAKE_CLIENT, CPU_HASWELL,
1626 PTA_ICELAKE_CLIENT},
1627 {"icelake-server", PROCESSOR_ICELAKE_SERVER, CPU_HASWELL,
1628 PTA_ICELAKE_SERVER},
1629 {"cascadelake", PROCESSOR_CASCADELAKE, CPU_HASWELL,
1630 PTA_CASCADELAKE},
1631 {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
1632 {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
1633 {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
1634 {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
1635 {"goldmont", PROCESSOR_GOLDMONT, CPU_GLM, PTA_GOLDMONT},
1636 {"goldmont-plus", PROCESSOR_GOLDMONT_PLUS, CPU_GLM, PTA_GOLDMONT_PLUS},
1637 {"tremont", PROCESSOR_TREMONT, CPU_GLM, PTA_TREMONT},
1638 {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
1639 {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
1640 {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
1641 {"geode", PROCESSOR_GEODE, CPU_GEODE,
1642 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
1643 {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
1644 {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
1645 {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
1646 {"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
1647 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
1648 {"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
1649 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
1650 {"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
1651 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
1652 {"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
1653 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
1654 {"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
1655 PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
1656 {"x86-64", PROCESSOR_K8, CPU_K8,
1657 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
1658 {"eden-x2", PROCESSOR_K8, CPU_K8,
1659 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
1660 {"nano", PROCESSOR_K8, CPU_K8,
1661 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1662 | PTA_SSSE3 | PTA_FXSR},
1663 {"nano-1000", PROCESSOR_K8, CPU_K8,
1664 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1665 | PTA_SSSE3 | PTA_FXSR},
1666 {"nano-2000", PROCESSOR_K8, CPU_K8,
1667 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1668 | PTA_SSSE3 | PTA_FXSR},
1669 {"nano-3000", PROCESSOR_K8, CPU_K8,
1670 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1671 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
1672 {"nano-x2", PROCESSOR_K8, CPU_K8,
1673 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1674 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
1675 {"eden-x4", PROCESSOR_K8, CPU_K8,
1676 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1677 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
1678 {"nano-x4", PROCESSOR_K8, CPU_K8,
1679 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1680 | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
1681 {"k8", PROCESSOR_K8, CPU_K8,
1682 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1683 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
1684 {"k8-sse3", PROCESSOR_K8, CPU_K8,
1685 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1686 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
1687 {"opteron", PROCESSOR_K8, CPU_K8,
1688 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1689 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
1690 {"opteron-sse3", PROCESSOR_K8, CPU_K8,
1691 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1692 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
1693 {"athlon64", PROCESSOR_K8, CPU_K8,
1694 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1695 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
1696 {"athlon64-sse3", PROCESSOR_K8, CPU_K8,
1697 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1698 | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
1699 {"athlon-fx", PROCESSOR_K8, CPU_K8,
1700 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
1701 | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
1702 {"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
1703 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
1704 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
1705 {"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
1706 PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
1707 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
1708 {"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
1709 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1710 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
1711 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
1712 | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
1713 {"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
1714 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1715 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
1716 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
1717 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
1718 | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
1719 {"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
1720 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1721 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
1722 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
1723 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
1724 | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
1725 | PTA_XSAVEOPT | PTA_FSGSBASE},
1726 {"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
1727 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1728 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
1729 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
1730 | PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2
1731 | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR
1732 | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
1733 | PTA_MOVBE | PTA_MWAITX},
1734 {"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
1735 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1736 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
1737 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
1738 | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
1739 | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
1740 | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
1741 | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
1742 | PTA_SHA | PTA_LZCNT | PTA_POPCNT},
1743 {"znver2", PROCESSOR_ZNVER2, CPU_ZNVER1,
1744 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1745 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
1746 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
1747 | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
1748 | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
1749 | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
1750 | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
1751 | PTA_SHA | PTA_LZCNT | PTA_POPCNT | PTA_CLWB | PTA_RDPID
1752 | PTA_WBNOINVD},
1753 {"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
1754 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1755 | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
1756 | PTA_FXSR | PTA_XSAVE},
1757 {"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
1758 PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
1759 | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
1760 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
1761 | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
1762 | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
1763
1764 {"generic", PROCESSOR_GENERIC, CPU_GENERIC,
1765 PTA_64BIT
1766 | PTA_HLE /* flags are only used for -march switch. */ },
1767 };
1768
1769 int const pta_size = ARRAY_SIZE (processor_alias_table);
1770
1771 /* Provide valid option values for -march and -mtune options. */
1772
1773 vec<const char *>
1774 ix86_get_valid_option_values (int option_code,
1775 const char *prefix ATTRIBUTE_UNUSED)
1776 {
1777 vec<const char *> v;
1778 v.create (0);
1779 opt_code opt = (opt_code) option_code;
1780
1781 switch (opt)
1782 {
1783 case OPT_march_:
1784 for (unsigned i = 0; i < pta_size; i++)
1785 {
1786 const char *name = processor_alias_table[i].name;
1787 gcc_checking_assert (name != NULL);
1788 v.safe_push (name);
1789 }
1790 #ifdef HAVE_LOCAL_CPU_DETECT
1791 /* Add also "native" as possible value. */
1792 v.safe_push ("native");
1793 #endif
1794
1795 break;
1796 case OPT_mtune_:
1797 for (unsigned i = 0; i < PROCESSOR_max; i++)
1798 {
1799 const char *name = processor_names[i];
1800 gcc_checking_assert (name != NULL);
1801 v.safe_push (name);
1802 }
1803 break;
1804 default:
1805 break;
1806 }
1807
1808 return v;
1809 }
1810
1811 #undef TARGET_GET_VALID_OPTION_VALUES
1812 #define TARGET_GET_VALID_OPTION_VALUES ix86_get_valid_option_values
1813
1814 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
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