| blob | 4a987d50337cfe65b15a19afd770682440b0702d |
1 /* Perform various loop optimizations, including strength reduction.
2 Copyright (C) 1987, 1988, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
10 version.
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
20 02111-1307, USA. */
22 /* This is the loop optimization pass of the compiler.
23 It finds invariant computations within loops and moves them
24 to the beginning of the loop. Then it identifies basic and
25 general induction variables. Strength reduction is applied to the general
26 induction variables, and induction variable elimination is applied to
27 the basic induction variables.
29 It also finds cases where
30 a register is set within the loop by zero-extending a narrower value
31 and changes these to zero the entire register once before the loop
32 and merely copy the low part within the loop.
34 Most of the complexity is in heuristics to decide when it is worth
35 while to do these things. */
61 /* Not really meaningful values, but at least something. */
62 #ifndef SIMULTANEOUS_PREFETCHES
63 #define SIMULTANEOUS_PREFETCHES 3
64 #endif
65 #ifndef PREFETCH_BLOCK
66 #define PREFETCH_BLOCK 32
67 #endif
68 #ifndef HAVE_prefetch
69 #define HAVE_prefetch 0
70 #define CODE_FOR_prefetch 0
71 #define gen_prefetch(a,b,c) (abort(), NULL_RTX)
72 #endif
74 /* Give up the prefetch optimizations once we exceed a given threshold.
75 It is unlikely that we would be able to optimize something in a loop
76 with so many detected prefetches. */
77 #define MAX_PREFETCHES 100
78 /* The number of prefetch blocks that are beneficial to fetch at once before
79 a loop with a known (and low) iteration count. */
80 #define PREFETCH_BLOCKS_BEFORE_LOOP_MAX 6
81 /* For very tiny loops it is not worthwhile to prefetch even before the loop,
82 since it is likely that the data are already in the cache. */
83 #define PREFETCH_BLOCKS_BEFORE_LOOP_MIN 2
85 /* Parameterize some prefetch heuristics so they can be turned on and off
86 easily for performance testing on new architectures. These can be
87 defined in target-dependent files. */
89 /* Prefetch is worthwhile only when loads/stores are dense. */
90 #ifndef PREFETCH_ONLY_DENSE_MEM
91 #define PREFETCH_ONLY_DENSE_MEM 1
92 #endif
94 /* Define what we mean by "dense" loads and stores; This value divided by 256
95 is the minimum percentage of memory references that worth prefetching. */
96 #ifndef PREFETCH_DENSE_MEM
97 #define PREFETCH_DENSE_MEM 220
98 #endif
100 /* Do not prefetch for a loop whose iteration count is known to be low. */
101 #ifndef PREFETCH_NO_LOW_LOOPCNT
102 #define PREFETCH_NO_LOW_LOOPCNT 1
103 #endif
105 /* Define what we mean by a "low" iteration count. */
106 #ifndef PREFETCH_LOW_LOOPCNT
107 #define PREFETCH_LOW_LOOPCNT 32
108 #endif
110 /* Do not prefetch for a loop that contains a function call; such a loop is
111 probably not an internal loop. */
112 #ifndef PREFETCH_NO_CALL
113 #define PREFETCH_NO_CALL 1
114 #endif
116 /* Do not prefetch accesses with an extreme stride. */
117 #ifndef PREFETCH_NO_EXTREME_STRIDE
118 #define PREFETCH_NO_EXTREME_STRIDE 1
119 #endif
121 /* Define what we mean by an "extreme" stride. */
122 #ifndef PREFETCH_EXTREME_STRIDE
123 #define PREFETCH_EXTREME_STRIDE 4096
124 #endif
126 /* Define a limit to how far apart indices can be and still be merged
127 into a single prefetch. */
128 #ifndef PREFETCH_EXTREME_DIFFERENCE
129 #define PREFETCH_EXTREME_DIFFERENCE 4096
130 #endif
132 /* Issue prefetch instructions before the loop to fetch data to be used
133 in the first few loop iterations. */
134 #ifndef PREFETCH_BEFORE_LOOP
135 #define PREFETCH_BEFORE_LOOP 1
136 #endif
138 /* Do not handle reversed order prefetches (negative stride). */
139 #ifndef PREFETCH_NO_REVERSE_ORDER
140 #define PREFETCH_NO_REVERSE_ORDER 1
141 #endif
143 /* Prefetch even if the GIV is in conditional code. */
144 #ifndef PREFETCH_CONDITIONAL
145 #define PREFETCH_CONDITIONAL 1
146 #endif
148 #define LOOP_REG_LIFETIME(LOOP, REGNO) \
149 ((REGNO_LAST_LUID (REGNO) - REGNO_FIRST_LUID (REGNO)))
151 #define LOOP_REG_GLOBAL_P(LOOP, REGNO) \
152 ((REGNO_LAST_LUID (REGNO) > INSN_LUID ((LOOP)->end) \
153 || REGNO_FIRST_LUID (REGNO) < INSN_LUID ((LOOP)->start)))
155 #define LOOP_REGNO_NREGS(REGNO, SET_DEST) \
156 ((REGNO) < FIRST_PSEUDO_REGISTER \
157 ? (int) HARD_REGNO_NREGS ((REGNO), GET_MODE (SET_DEST)) : 1)
160 /* Vector mapping INSN_UIDs to luids.
161 The luids are like uids but increase monotonically always.
162 We use them to see whether a jump comes from outside a given loop. */
166 /* Indexed by INSN_UID, contains the ordinal giving the (innermost) loop
167 number the insn is contained in. */
171 /* 1 + largest uid of any insn. */
175 /* Number of loops detected in current function. Used as index to the
176 next few tables. */
180 /* Bound on pseudo register number before loop optimization.
181 A pseudo has valid regscan info if its number is < max_reg_before_loop. */
184 /* The value to pass to the next call of reg_scan_update. */
186 \f
187 /* During the analysis of a loop, a chain of `struct movable's
188 is made to record all the movable insns found.
189 Then the entire chain can be scanned to decide which to move. */
191 struct movable
192 {
197 of any registers used within the LIBCALL. */
199 that must be moved with this one. */
202 may be adjusted when matching movables
203 that load the same value are found. */
205 including other movables that force this
206 or match this one. */
208 a low part that we should avoid changing when
209 clearing the rest of the reg. */
213 /* If PARTIAL is 1, GLOBAL means something different:
214 that the reg is live outside the range from where it is set
215 to the following label. */
219 In particular, moving it does not make it
220 invariant. */
222 load SRC, rather than copying INSN. */
224 first insn of a consecutive sets group. */
227 the original insn with a copy from that
228 pseudo, rather than deleting it. */
232 };
237 /* Forward declarations. */
251 #if 0
253 #endif
294 rtx *);
355 {
356 rtx match;
357 rtx replacement;
358 rtx insn;
361 /* Nonzero iff INSN is between START and END, inclusive. */
362 #define INSN_IN_RANGE_P(INSN, START, END) \
363 (INSN_UID (INSN) < max_uid_for_loop \
364 && INSN_LUID (INSN) >= INSN_LUID (START) \
365 && INSN_LUID (INSN) <= INSN_LUID (END))
367 /* Indirect_jump_in_function is computed once per function. */
375 \f
376 /* Benefit penalty, if a giv is not replaceable, i.e. must emit an insn to
377 copy the value of the strength reduced giv to its original register. */
380 /* Cost of using a register, to normalize the benefits of a giv. */
383 void
385 {
391 }
392 \f
393 /* Compute the mapping from uids to luids.
394 LUIDs are numbers assigned to insns, like uids,
395 except that luids increase monotonically through the code.
396 Start at insn START and stop just before END. Assign LUIDs
397 starting with PREV_LUID + 1. Return the last assigned LUID + 1. */
398 static int
400 {
402 rtx insn;
405 {
408 /* Don't assign luids to line-number NOTEs, so that the distance in
409 luids between two insns is not affected by -g. */
413 else
414 /* Give a line number note the same luid as preceding insn. */
416 }
418 }
419 \f
420 /* Entry point of this file. Perform loop optimization
421 on the current function. F is the first insn of the function
422 and DUMPFILE is a stream for output of a trace of actions taken
423 (or 0 if none should be output). */
425 void
427 {
428 rtx insn;
443 /* Count the number of loops. */
447 {
450 max_loop_num++;
451 }
453 /* Don't waste time if no loops. */
459 /* Get size to use for tables indexed by uids.
460 Leave some space for labels allocated by find_and_verify_loops. */
466 /* Allocate storage for array of loops. */
469 /* Find and process each loop.
470 First, find them, and record them in order of their beginnings. */
473 /* Allocate and initialize auxiliary loop information. */
478 /* Now find all register lifetimes. This must be done after
479 find_and_verify_loops, because it might reorder the insns in the
480 function. */
483 /* This must occur after reg_scan so that registers created by gcse
484 will have entries in the register tables.
486 We could have added a call to reg_scan after gcse_main in toplev.c,
487 but moving this call to init_alias_analysis is more efficient. */
490 /* See if we went too far. Note that get_max_uid already returns
491 one more that the maximum uid of all insn. */
494 /* Now reset it to the actual size we need. See above. */
497 /* find_and_verify_loops has already called compute_luids, but it
498 might have rearranged code afterwards, so we need to recompute
499 the luids now. */
502 /* Don't leave gaps in uid_luid for insns that have been
503 deleted. It is possible that the first or last insn
504 using some register has been deleted by cross-jumping.
505 Make sure that uid_luid for that former insn's uid
506 points to the general area where that insn used to be. */
508 {
512 }
517 /* Determine if the function has indirect jump. On some systems
518 this prevents low overhead loop instructions from being used. */
521 /* Now scan the loops, last ones first, since this means inner ones are done
522 before outer ones. */
524 {
529 }
533 /* Clean up. */
538 }
539 \f
540 /* Returns the next insn, in execution order, after INSN. START and
541 END are the NOTE_INSN_LOOP_BEG and NOTE_INSN_LOOP_END for the loop,
542 respectively. LOOP->TOP, if non-NULL, is the top of the loop in the
543 insn-stream; it is used with loops that are entered near the
544 bottom. */
546 static rtx
548 {
552 {
554 /* Go to the top of the loop, and continue there. */
556 else
557 /* We're done. */
559 }
562 /* We're done. */
566 }
568 /* Optimize one loop described by LOOP. */
570 /* ??? Could also move memory writes out of loops if the destination address
571 is invariant, the source is invariant, the memory write is not volatile,
572 and if we can prove that no read inside the loop can read this address
573 before the write occurs. If there is a read of this address after the
574 write, then we can also mark the memory read as invariant. */
576 static void
578 {
584 rtx p;
585 /* 1 if we are scanning insns that could be executed zero times. */
587 /* 1 if we are scanning insns that might never be executed
588 due to a subroutine call which might exit before they are reached. */
590 /* Number of insns in the loop. */
594 /* The SET from an insn, if it is the only SET in the insn. */
596 /* Chain describing insns movable in current loop. */
598 /* Ratio of extra register life span we can justify
599 for saving an instruction. More if loop doesn't call subroutines
600 since in that case saving an insn makes more difference
601 and more registers are available. */
603 /* Nonzero if we are scanning instructions in a sub-loop. */
612 /* Determine whether this loop starts with a jump down to a test at
613 the end. This will occur for a small number of loops with a test
614 that is too complex to duplicate in front of the loop.
616 We search for the first insn or label in the loop, skipping NOTEs.
617 However, we must be careful not to skip past a NOTE_INSN_LOOP_BEG
618 (because we might have a loop executed only once that contains a
619 loop which starts with a jump to its exit test) or a NOTE_INSN_LOOP_END
620 (in case we have a degenerate loop).
622 Note that if we mistakenly think that a loop is entered at the top
623 when, in fact, it is entered at the exit test, the only effect will be
624 slightly poorer optimization. Making the opposite error can generate
625 incorrect code. Since very few loops now start with a jump to the
626 exit test, the code here to detect that case is very conservative. */
629 p != loop_end
635 ;
639 /* If loop end is the end of the current function, then emit a
640 NOTE_INSN_DELETED after loop_end and set loop->sink to the dummy
641 note insn. This is the position we use when sinking insns out of
642 the loop. */
645 else
648 /* Set up variables describing this loop. */
652 /* If loop has a jump before the first label,
653 the true entry is the target of that jump.
654 Start scan from there.
655 But record in LOOP->TOP the place where the end-test jumps
656 back to so we can scan that after the end of the loop. */
658 /* Loop entry must be unconditional jump (and not a RETURN) */
661 /* Check to see whether the jump actually
662 jumps out of the loop (meaning it's no loop).
663 This case can happen for things like
664 do {..} while (0). If this label was generated previously
665 by loop, we can't tell anything about it and have to reject
666 the loop. */
668 {
671 }
673 /* If LOOP->SCAN_START was an insn created by loop, we don't know its luid
674 as required by loop_reg_used_before_p. So skip such loops. (This
675 test may never be true, but it's best to play it safe.)
677 Also, skip loops where we do not start scanning at a label. This
678 test also rejects loops starting with a JUMP_INSN that failed the
679 test above. */
683 {
688 }
690 /* Allocate extra space for REGs that might be created by load_mems.
691 We allocate a little extra slop as well, in the hopes that we
692 won't have to reallocate the regs array. */
697 {
703 }
705 /* Scan through the loop finding insns that are safe to move.
706 Set REGS->ARRAY[I].SET_IN_LOOP negative for the reg I being set, so that
707 this reg will be considered invariant for subsequent insns.
708 We consider whether subsequent insns use the reg
709 in deciding whether it is worth actually moving.
711 MAYBE_NEVER is nonzero if we have passed a conditional jump insn
712 and therefore it is possible that the insns we are scanning
713 would never be executed. At such times, we must make sure
714 that it is safe to execute the insn once instead of zero times.
715 When MAYBE_NEVER is 0, all insns will be executed at least once
716 so that is not a problem. */
721 {
723 in_libcall--;
725 {
728 in_libcall++;
732 #ifdef PIC_OFFSET_TABLE_REG_CALL_CLOBBERED
734 #endif
736 {
744 /* Figure out what to use as a source of this insn. If a
745 REG_EQUIV note is given or if a REG_EQUAL note with a
746 constant operand is specified, use it as the source and
747 mark that we should move this insn by calling
748 emit_move_insn rather that duplicating the insn.
750 Otherwise, only use the REG_EQUAL contents if a REG_RETVAL
751 note is present. */
755 else
756 {
761 {
763 /* A libcall block can use regs that don't appear in
764 the equivalent expression. To move the libcall,
765 we must move those regs too. */
767 }
768 }
770 /* For parallels, add any possible uses to the dependencies, as
771 we can't move the insn without resolving them first. */
773 {
775 {
778 dependencies
780 dependencies);
781 }
782 }
785 than the one where it is set (meaning that
786 something after this point in the loop might
787 depend on its value before the set). */
789 /* And the set is not guaranteed to be executed once
790 the loop starts, or the value before the set is
791 needed before the set occurs...
793 ??? Note we have quadratic behavior here, mitigated
794 by the fact that the previous test will often fail for
795 large loops. Rather than re-scanning the entire loop
796 each time for register usage, we should build tables
797 of the register usage and use them here instead. */
798 && (maybe_never
800 /* It is unsafe to move the set. However, it may be OK to
801 move the source into a new pseudo, and substitute a
802 reg-to-reg copy for the original insn.
804 This code used to consider it OK to move a set of a variable
805 which was not created by the user and not used in an exit
806 test.
807 That behavior is incorrect and was removed. */
810 /* Don't try to optimize a MODE_CC set with a constant
811 source. It probably will be combined with a conditional
812 jump. */
815 ;
816 /* Don't try to optimize a register that was made
817 by loop-optimization for an inner loop.
818 We don't know its life-span, so we can't compute
819 the benefit. */
821 ;
822 /* Don't move the source and add a reg-to-reg copy:
823 - with -Os (this certainly increases size),
824 - if the mode doesn't support copy operations (obviously),
825 - if the source is already a reg (the motion will gain nothing),
826 - if the source is a legitimate constant (likewise). */
828 && (optimize_size
833 ;
836 || (tem2
839 || (tem1
840 = consec_sets_invariant_p
843 p)))
844 /* If the insn can cause a trap (such as divide by zero),
845 can't move it unless it's guaranteed to be executed
846 once loop is entered. Even a function call might
847 prevent the trap insn from being reached
848 (since it might exit!) */
851 {
855 /* A potential lossage is where we have a case where two insns
856 can be combined as long as they are both in the loop, but
857 we move one of them outside the loop. For large loops,
858 this can lose. The most common case of this is the address
859 of a function being called.
861 Therefore, if this register is marked as being used
862 exactly once if we are in a loop with calls
863 (a "large loop"), see if we can replace the usage of
864 this register with the source of this SET. If we can,
865 delete this insn.
867 Don't do this if P has a REG_RETVAL note or if we have
868 SMALL_REGISTER_CLASSES and SET_SRC is a hard register. */
880 && (! SMALL_REGISTER_CLASSES
884 /* This test is not redundant; SET_SRC (set) might be
885 a call-clobbered register and the life of REGNO
886 might span a call. */
893 {
894 /* Replace any usage in a REG_EQUAL note. Must copy
895 the new source, so that we don't get rtx sharing
896 between the SET_SOURCE and REG_NOTES of insn p. */
898 = (replace_rtx
904 i++)
907 }
916 m->consec
927 /* Set M->cond if either loop_invariant_p
928 or consec_sets_invariant_p returned 2
929 (only conditionally invariant). */
939 /* Add M to the end of the chain MOVABLES. */
943 {
944 /* It is possible for the first instruction to have a
945 REG_EQUAL note but a non-invariant SET_SRC, so we must
946 remember the status of the first instruction in case
947 the last instruction doesn't have a REG_EQUAL note. */
950 /* Skip this insn, not checking REG_LIBCALL notes. */
952 /* Skip the consecutive insns, if there are any. */
954 /* Back up to the last insn of the consecutive group. */
957 /* We must now reset m->move_insn, m->is_equiv, and
958 possibly m->set_src to correspond to the effects of
959 all the insns. */
963 else
964 {
968 else
971 }
972 m->is_equiv
974 }
975 }
976 /* If this register is always set within a STRICT_LOW_PART
977 or set to zero, then its high bytes are constant.
978 So clear them outside the loop and within the loop
979 just load the low bytes.
980 We must check that the machine has an instruction to do so.
981 Also, if the value loaded into the register
982 depends on the same register, this cannot be done. */
992 {
995 {
1010 /* If the insn may not be executed on some cycles,
1011 we can't clear the whole reg; clear just high part.
1012 Not even if the reg is used only within this loop.
1013 Consider this:
1014 while (1)
1015 while (s != t) {
1016 if (foo ()) x = *s;
1017 use (x);
1018 }
1019 Clearing x before the inner loop could clobber a value
1020 being saved from the last time around the outer loop.
1021 However, if the reg is not used outside this loop
1022 and all uses of the register are in the same
1023 basic block as the store, there is no problem.
1025 If this insn was made by loop, we don't know its
1026 INSN_LUID and hence must make a conservative
1027 assumption. */
1030 || (labels_in_range_p
1034 else
1043 i++)
1045 /* Add M to the end of the chain MOVABLES. */
1047 }
1048 }
1049 }
1050 }
1051 /* Past a call insn, we get to insns which might not be executed
1052 because the call might exit. This matters for insns that trap.
1053 Constant and pure call insns always return, so they don't count. */
1056 /* Past a label or a jump, we get to insns for which we
1057 can't count on whether or how many times they will be
1058 executed during each iteration. Therefore, we can
1059 only move out sets of trivial variables
1060 (those not used after the loop). */
1061 /* Similar code appears twice in strength_reduce. */
1063 /* If we enter the loop in the middle, and scan around to the
1064 beginning, don't set maybe_never for that. This must be an
1065 unconditional jump, otherwise the code at the top of the
1066 loop might never be executed. Unconditional jumps are
1067 followed by a barrier then the loop_end. */
1073 {
1074 /* At the virtual top of a converted loop, insns are again known to
1075 be executed: logically, the loop begins here even though the exit
1076 code has been duplicated. */
1080 loop_depth++;
1082 loop_depth--;
1083 }
1084 }
1086 /* If one movable subsumes another, ignore that other. */
1090 /* For each movable insn, see if the reg that it loads
1091 leads when it dies right into another conditionally movable insn.
1092 If so, record that the second insn "forces" the first one,
1093 since the second can be moved only if the first is. */
1097 /* See if there are multiple movable insns that load the same value.
1098 If there are, make all but the first point at the first one
1099 through the `match' field, and add the priorities of them
1100 all together as the priority of the first. */
1104 /* Now consider each movable insn to decide whether it is worth moving.
1105 Store 0 in regs->array[I].set_in_loop for each reg I that is moved.
1107 For machines with few registers this increases code size, so do not
1108 move moveables when optimizing for code size on such machines.
1109 (The 18 below is the value for i386.) */
1113 {
1116 /* Recalculate regs->array if move_movables has created new
1117 registers. */
1119 {
1125 ;
1130 }
1131 }
1133 /* Now candidates that still are negative are those not moved.
1134 Change regs->array[I].set_in_loop to indicate that those are not actually
1135 invariant. */
1140 /* Now that we've moved some things out of the loop, we might be able to
1141 hoist even more memory references. */
1144 /* Recalculate regs->array if load_mems has created new registers. */
1152 ;
1159 {
1161 /* Ensure our label doesn't go away. */
1172 }
1175 /* The movable information is required for strength reduction. */
1181 }
1182 \f
1183 /* Add elements to *OUTPUT to record all the pseudo-regs
1184 mentioned in IN_THIS but not mentioned in NOT_IN_THIS. */
1186 void
1188 {
1196 {
1214 }
1218 {
1222 {
1231 }
1232 }
1233 }
1234 \f
1235 /* Check what regs are referred to in the libcall block ending with INSN,
1236 aside from those mentioned in the equivalent value.
1237 If there are none, return 0.
1238 If there are one or more, return an EXPR_LIST containing all of them. */
1240 rtx
1242 {
1247 /* First, find all the regs used in the libcall block
1248 that are not mentioned as inputs to the result. */
1251 {
1256 }
1259 }
1260 \f
1261 /* Return 1 if all uses of REG
1262 are between INSN and the end of the basic block. */
1264 static int
1266 {
1268 rtx p;
1273 /* Search this basic block for the already recorded last use of the reg. */
1275 {
1277 {
1283 /* Ordinary insn: if this is the last use, we win. */
1289 /* Jump insn: if this is the last use, we win. */
1292 /* Otherwise, it's the end of the basic block, so we lose. */
1297 /* It's the end of the basic block, so we lose. */
1302 }
1303 }
1305 /* The "last use" that was recorded can't be found after the first
1306 use. This can happen when the last use was deleted while
1307 processing an inner loop, this inner loop was then completely
1308 unrolled, and the outer loop is always exited after the inner loop,
1309 so that everything after the first use becomes a single basic block. */
1311 }
1312 \f
1313 /* Compute the benefit of eliminating the insns in the block whose
1314 last insn is LAST. This may be a group of insns used to compute a
1315 value directly or can contain a library call. */
1317 static int
1319 {
1320 rtx insn;
1325 {
1328 routine. */
1332 benefit++;
1333 }
1336 }
1337 \f
1338 /* Skip COUNT insns from INSN, counting library calls as 1 insn. */
1340 static rtx
1342 {
1344 {
1345 rtx temp;
1347 /* If first insn of libcall sequence, skip to end. */
1348 /* Do this at start of loop, since INSN is guaranteed to
1349 be an insn here. */
1354 do
1357 }
1360 }
1362 /* Ignore any movable whose insn falls within a libcall
1363 which is part of another movable.
1364 We make use of the fact that the movable for the libcall value
1365 was made later and so appears later on the chain. */
1367 static void
1369 {
1373 {
1374 /* Is this a movable for the value of a libcall? */
1377 {
1378 rtx insn;
1379 /* Check for earlier movables inside that range,
1380 and mark them invalid. We cannot use LUIDs here because
1381 insns created by loop.c for prior loops don't have LUIDs.
1382 Rather than reject all such insns from movables, we just
1383 explicitly check each insn in the libcall (since invariant
1384 libcalls aren't that common). */
1389 }
1390 }
1391 }
1393 /* For each movable insn, see if the reg that it loads
1394 leads when it dies right into another conditionally movable insn.
1395 If so, record that the second insn "forces" the first one,
1396 since the second can be moved only if the first is. */
1398 static void
1400 {
1404 /* Omit this if moving just the (SET (REG) 0) of a zero-extend. */
1406 {
1409 /* ??? Could this be a bug? What if CSE caused the
1410 register of M1 to be used after this insn?
1411 Since CSE does not update regno_last_uid,
1412 this insn M->insn might not be where it dies.
1413 But very likely this doesn't matter; what matters is
1414 that M's reg is computed from M1's reg. */
1419 /* If m->consec, m->set_src isn't valid. */
1423 /* Increase the priority of the moving the first insn
1424 since it permits the second to be moved as well. */
1426 {
1430 }
1431 }
1432 }
1433 \f
1434 /* Find invariant expressions that are equal and can be combined into
1435 one register. */
1437 static void
1439 {
1444 /* Regs that are set more than once are not allowed to match
1445 or be matched. I'm no longer sure why not. */
1446 /* Only pseudo registers are allowed to match or be matched,
1447 since move_movables does not validate the change. */
1448 /* Perhaps testing m->consec_sets would be more appropriate here? */
1455 {
1462 /* We want later insns to match the first one. Don't make the first
1463 one match any later ones. So start this loop at m->next. */
1469 /* A reg used outside the loop mustn't be eliminated. */
1471 /* A reg used for zero-extending mustn't be eliminated. */
1474 ||
1475 (
1476 /* Can combine regs with different modes loaded from the
1477 same constant only if the modes are the same or
1478 if both are integer modes with M wider or the same
1479 width as M1. The check for integer is redundant, but
1480 safe, since the only case of differing destination
1481 modes with equal sources is when both sources are
1482 VOIDmode, i.e., CONST_INT. */
1488 /* See if the source of M1 says it matches M. */
1495 {
1501 }
1502 }
1504 /* Now combine the regs used for zero-extension.
1505 This can be done for those not marked `global'
1506 provided their lives don't overlap. */
1510 {
1513 /* Combine all the registers for extension from mode MODE.
1514 Don't combine any that are used outside this loop. */
1518 {
1525 {
1526 /* First one: don't check for overlap, just record it. */
1529 }
1531 /* Make sure they extend to the same mode.
1532 (Almost always true.) */
1536 /* We already have one: check for overlap with those
1537 already combined together. */
1544 /* No overlap: we can combine this with the others. */
1550 overlap:
1551 ;
1552 }
1553 }
1555 /* Clean up. */
1557 }
1559 /* Returns the number of movable instructions in LOOP that were not
1560 moved outside the loop. */
1562 static int
1564 {
1573 }
1575 \f
1576 /* Return 1 if regs X and Y will become the same if moved. */
1578 static int
1580 {
1597 }
1599 /* Return 1 if X and Y are identical-looking rtx's.
1600 This is the Lisp function EQUAL for rtx arguments.
1602 If two registers are matching movables or a movable register and an
1603 equivalent constant, consider them equal. */
1605 static int
1608 {
1622 /* If we have a register and a constant, they may sometimes be
1623 equal. */
1626 {
1631 }
1634 {
1639 }
1641 /* Otherwise, rtx's of different codes cannot be equal. */
1645 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent.
1646 (REG:SI x) and (REG:HI x) are NOT equivalent. */
1651 /* These three types of rtx's can be compared nonrecursively. */
1660 /* Compare the elements. If any pair of corresponding elements
1661 fail to match, return 0 for the whole things. */
1665 {
1667 {
1679 /* Two vectors must have the same length. */
1683 /* And the corresponding elements must match. */
1702 /* These are just backpointers, so they don't matter. */
1708 /* It is believed that rtx's at this level will never
1709 contain anything but integers and other rtx's,
1710 except for within LABEL_REFs and SYMBOL_REFs. */
1713 }
1714 }
1716 }
1717 \f
1718 /* If X contains any LABEL_REF's, add REG_LABEL notes for them to all
1719 insns in INSNS which use the reference. LABEL_NUSES for CODE_LABEL
1720 references is incremented once for each added note. */
1722 static void
1724 {
1728 rtx insn;
1731 {
1732 /* This code used to ignore labels that referred to dispatch tables to
1733 avoid flow generating (slightly) worse code.
1735 We no longer ignore such label references (see LABEL_REF handling in
1736 mark_jump_label for additional information). */
1739 {
1744 }
1745 }
1749 {
1755 }
1756 }
1757 \f
1758 /* Scan MOVABLES, and move the insns that deserve to be moved.
1759 If two matching movables are combined, replace one reg with the
1760 other throughout. */
1762 static void
1765 {
1770 rtx p;
1773 /* Map of pseudo-register replacements to handle combining
1774 when we move several insns that load the same value
1775 into different pseudo-registers. */
1780 {
1781 /* Describe this movable insn. */
1784 {
1805 }
1807 /* Ignore the insn if it's already done (it matched something else).
1808 Otherwise, see if it is now safe to move. */
1820 {
1822 rtx p;
1825 /* We have an insn that is safe to move.
1826 Compute its desirability. */
1837 /* An insn MUST be moved if we already moved something else
1838 which is safe only if this one is moved too: that is,
1839 if already_moved[REGNO] is nonzero. */
1841 /* An insn is desirable to move if the new lifetime of the
1842 register is no more than THRESHOLD times the old lifetime.
1843 If it's not desirable, it means the loop is so big
1844 that moving won't speed things up much,
1845 and it is liable to make register usage worse. */
1847 /* It is also desirable to move if it can be moved at no
1848 extra cost because something else was already moved. */
1851 || flag_move_all_movables
1856 {
1865 /* Now move the insns that set the reg. */
1868 {
1871 /* Find the end of this chain of matching regs.
1872 Thus, we load each reg in the chain from that one reg.
1873 And that reg is loaded with 0 directly,
1874 since it has ->match == 0. */
1880 /* Mark the moved, invariant reg as being allowed to
1881 share a hard reg with the other matching invariant. */
1885 regs_may_share
1888 regs_may_share));
1896 }
1897 /* If we are to re-generate the item being moved with a
1898 new move insn, first delete what we have and then emit
1899 the move insn before the loop. */
1901 {
1905 {
1906 /* If this is the first insn of a library call sequence,
1907 something is very wrong. */
1912 /* If this is the last insn of a libcall sequence, then
1913 delete every insn in the sequence except the last.
1914 The last insn is handled in the normal manner. */
1917 {
1921 }
1926 /* simplify_giv_expr expects that it can walk the insns
1927 at m->insn forwards and see this old sequence we are
1928 tossing here. delete_insn does preserve the next
1929 pointers, but when we skip over a NOTE we must fix
1930 it up. Otherwise that code walks into the non-deleted
1931 insn stream. */
1936 {
1937 /* Replace the original insn with a move from
1938 our newly created temp. */
1944 }
1945 }
1964 /* The more regs we move, the less we like moving them. */
1966 }
1967 else
1968 {
1970 {
1973 /* If first insn of libcall sequence, skip to end. */
1974 /* Do this at start of loop, since p is guaranteed to
1975 be an insn here. */
1980 /* If last insn of libcall sequence, move all
1981 insns except the last before the loop. The last
1982 insn is handled in the normal manner. */
1985 {
1993 {
1994 rtx body;
1995 rtx n;
1996 rtx next;
2003 /* Find the next insn after TEMP,
2004 not counting USE or NOTE insns. */
2012 /* If that is the call, this may be the insn
2013 that loads the function address.
2015 Extract the function address from the insn
2016 that loads it into a register.
2017 If this insn was cse'd, we get incorrect code.
2019 So emit a new move insn that copies the
2020 function address into the register that the
2021 call insn will use. flow.c will delete any
2022 redundant stores that we have created. */
2027 NULL_RTX)))
2028 {
2034 }
2035 /* We have the call insn.
2036 If it uses the register we suspect it might,
2037 load it with the correct address directly. */
2042 gen_move_insn
2046 {
2048 /* Because the USAGE information potentially
2049 contains objects other than hard registers
2050 we need to copy it. */
2054 }
2055 else
2064 }
2067 }
2069 {
2070 /* P sets REG to zero; but we should clear only
2071 the bits that are not covered by the mode
2072 m->savemode. */
2074 rtx sequence;
2075 rtx tem;
2078 tem = expand_simple_binop
2091 }
2093 {
2095 /* Because the USAGE information potentially
2096 contains objects other than hard registers
2097 we need to copy it. */
2101 }
2103 {
2104 rtx seq;
2105 /* The SET_SRC might not be invariant, so we must
2106 use the REG_EQUAL note. */
2118 }
2120 {
2128 }
2129 else
2133 {
2137 /* If there is a REG_EQUAL note present whose value
2138 is not loop invariant, then delete it, since it
2139 may cause problems with later optimization passes.
2140 It is possible for cse to create such notes
2141 like this as a result of record_jump_cond. */
2146 }
2155 /* If library call, now fix the REG_NOTES that contain
2156 insn pointers, namely REG_LIBCALL on FIRST
2157 and REG_RETVAL on I1. */
2159 {
2163 }
2169 /* simplify_giv_expr expects that it can walk the insns
2170 at m->insn forwards and see this old sequence we are
2171 tossing here. delete_insn does preserve the next
2172 pointers, but when we skip over a NOTE we must fix
2173 it up. Otherwise that code walks into the non-deleted
2174 insn stream. */
2179 {
2180 rtx seq;
2181 /* Replace the original insn with a move from
2182 our newly created temp. */
2188 }
2189 }
2191 /* The more regs we move, the less we like moving them. */
2193 }
2198 {
2199 /* Any other movable that loads the same register
2200 MUST be moved. */
2203 /* This reg has been moved out of one loop. */
2206 /* The reg set here is now invariant. */
2208 {
2212 }
2214 /* Change the length-of-life info for the register
2215 to say it lives at least the full length of this loop.
2216 This will help guide optimizations in outer loops. */
2219 /* This is the old insn before all the moved insns.
2220 We can't use the moved insn because it is out of range
2221 in uid_luid. Only the old insns have luids. */
2225 }
2227 /* Combine with this moved insn any other matching movables. */
2232 {
2233 rtx temp;
2235 /* Schedule the reg loaded by M1
2236 for replacement so that shares the reg of M.
2237 If the modes differ (only possible in restricted
2238 circumstances, make a SUBREG.
2240 Note this assumes that the target dependent files
2241 treat REG and SUBREG equally, including within
2242 GO_IF_LEGITIMATE_ADDRESS and in all the
2243 predicates since we never verify that replacing the
2244 original register with a SUBREG results in a
2245 recognizable insn. */
2248 else
2253 /* Get rid of the matching insn
2254 and prevent further processing of it. */
2257 /* If library call, delete all insns. */
2259 NULL_RTX)))
2261 else
2264 /* Any other movable that loads the same register
2265 MUST be moved. */
2268 /* The reg merged here is now invariant,
2269 if the reg it matches is invariant. */
2271 {
2275 i++)
2277 }
2278 }
2279 }
2282 }
2288 }
2293 /* Go through all the instructions in the loop, making
2294 all the register substitutions scheduled in REG_MAP. */
2298 {
2302 }
2304 /* Clean up. */
2307 }
2310 static void
2312 {
2315 else
2318 }
2321 static void
2323 {
2328 {
2331 }
2332 }
2333 \f
2334 #if 0
2335 /* Scan X and replace the address of any MEM in it with ADDR.
2336 REG is the address that MEM should have before the replacement. */
2338 static void
2340 {
2349 {
2361 /* Short cut for very common case. */
2366 /* Short cut for very common case. */
2371 /* If this MEM uses a reg other than the one we expected,
2372 something is wrong. */
2380 }
2384 {
2388 {
2392 }
2393 }
2394 }
2395 #endif
2396 \f
2397 /* Return the number of memory refs to addresses that vary
2398 in the rtx X. */
2400 static int
2402 {
2413 {
2430 }
2435 {
2439 {
2443 }
2444 }
2446 }
2447 \f
2448 /* Scan a loop setting the elements `cont', `vtop', `loops_enclosed',
2449 `has_call', `has_nonconst_call', `has_volatile', `has_tablejump',
2450 `unknown_address_altered', `unknown_constant_address_altered', and
2451 `num_mem_sets' in LOOP. Also, fill in the array `mems' and the
2452 list `store_mems' in LOOP. */
2454 static void
2456 {
2458 rtx insn;
2462 /* The label after END. Jumping here is just like falling off the
2463 end of the loop. We use next_nonnote_insn instead of next_label
2464 as a hedge against the (pathological) case where some actual insn
2465 might end up between the two. */
2484 /* If loop opts run twice, this was set on 1st pass for 2nd. */
2489 {
2491 {
2494 }
2495 }
2499 {
2501 {
2504 {
2506 /* Count number of loops contained in this one. */
2508 }
2515 {
2518 }
2525 /* Calls initializing constant objects have CLOBBER of MEM /u in the
2526 attached FUNCTION_USAGE expression list, not accounted for by the
2527 code above. We should note these to avoid missing dependencies in
2528 later references. */
2529 {
2530 rtx fusage_entry;
2534 {
2540 {
2545 }
2546 }
2547 }
2552 {
2556 {
2561 {
2564 }
2565 else
2566 {
2569 }
2571 do
2572 {
2574 {
2576 {
2577 /* Something tricky. */
2580 }
2583 {
2584 /* A jump outside the current loop. */
2587 }
2588 }
2592 }
2594 }
2595 else
2596 {
2597 /* A return, or something tricky. */
2599 }
2600 }
2601 /* FALLTHRU */
2622 }
2623 }
2625 /* Now, rescan the loop, setting up the LOOP_MEMS array. */
2627 anywhere. */
2629 /* We don't want loads for MEMs moved to a location before the
2630 one at which their stack memory becomes allocated. (Note
2631 that this is not a problem for malloc, etc., since those
2632 require actual function calls. */
2633 && ! current_function_calls_alloca
2634 /* There are ways to leave the loop other than falling off the
2635 end. */
2641 /* BLKmode MEMs are added to LOOP_STORE_MEM as necessary so
2642 that loop_invariant_p and load_mems can use true_dependence
2643 to determine what is really clobbered. */
2645 {
2648 loop_info->store_mems
2650 }
2652 {
2656 loop_info->store_mems
2658 }
2659 }
2660 \f
2661 /* Invalidate all loops containing LABEL. */
2663 static void
2665 {
2669 }
2671 /* Scan the function looking for loops. Record the start and end of each loop.
2672 Also mark as invalid loops any loops that contain a setjmp or are branched
2673 to from outside the loop. */
2675 static void
2677 {
2678 rtx insn;
2679 rtx label;
2689 /* If there are jumps to undefined labels,
2690 treat them as jumps out of any/all loops.
2691 This also avoids writing past end of tables when there are no loops. */
2694 /* Find boundaries of loops, mark which loops are contained within
2695 loops, and invalidate loops that have setjmp. */
2700 {
2703 {
2707 num_loops++;
2731 }
2735 {
2736 /* In this case, we must invalidate our current loop and any
2737 enclosing loop. */
2739 {
2745 }
2746 }
2748 /* Note that this will mark the NOTE_INSN_LOOP_END note as being in the
2749 enclosing loop, but this doesn't matter. */
2751 }
2753 /* Any loop containing a label used in an initializer must be invalidated,
2754 because it can be jumped into from anywhere. */
2758 /* Any loop containing a label used for an exception handler must be
2759 invalidated, because it can be jumped into from anywhere. */
2762 /* Now scan all insn's in the function. If any JUMP_INSN branches into a
2763 loop that it is not contained within, that loop is marked invalid.
2764 If any INSN or CALL_INSN uses a label's address, then the loop containing
2765 that label is marked invalid, because it could be jumped into from
2766 anywhere.
2768 Also look for blocks of code ending in an unconditional branch that
2769 exits the loop. If such a block is surrounded by a conditional
2770 branch around the block, move the block elsewhere (see below) and
2771 invert the jump to point to the code block. This may eliminate a
2772 label in our loop and will simplify processing by both us and a
2773 possible second cse pass. */
2777 {
2781 {
2785 }
2792 /* See if this is an unconditional branch outside the loop. */
2800 {
2801 rtx p;
2807 /* Go backwards until we reach the start of the loop, a label,
2808 or a JUMP_INSN. */
2815 ;
2817 /* Check for the case where we have a jump to an inner nested
2818 loop, and do not perform the optimization in that case. */
2821 {
2824 {
2829 }
2830 }
2832 /* Make sure that the target of P is within the current loop. */
2838 /* If we stopped on a JUMP_INSN to the next insn after INSN,
2839 we have a block of code to try to move.
2841 We look backward and then forward from the target of INSN
2842 to find a BARRIER at the same loop depth as the target.
2843 If we find such a BARRIER, we make a new label for the start
2844 of the block, invert the jump in P and point it to that label,
2845 and move the block of code to the spot we found. */
2850 /* Just ignore jumps to labels that were never emitted.
2851 These always indicate compilation errors. */
2855 /* If it's not safe to move the sequence, then we
2856 mustn't try. */
2859 {
2860 rtx target
2864 rtx tmp;
2866 /* Search for possible garbage past the conditional jumps
2867 and look for the last barrier. */
2875 /* Don't move things inside a tablejump. */
2888 /* Don't move things inside a tablejump. */
2899 {
2903 /* Ensure our label doesn't go away. */
2906 /* Verify that uid_loop is large enough and that
2907 we can invert P. */
2909 {
2912 /* If no suitable BARRIER was found, create a suitable
2913 one before TARGET. Since TARGET is a fall through
2914 path, we'll need to insert a jump around our block
2915 and add a BARRIER before TARGET.
2917 This creates an extra unconditional jump outside
2918 the loop. However, the benefits of removing rarely
2919 executed instructions from inside the loop usually
2920 outweighs the cost of the extra unconditional jump
2921 outside the loop. */
2923 {
2924 rtx temp;
2931 }
2933 /* Include the BARRIER after INSN and copy the
2934 block after LOC. */
2939 /* All those insns are now in TARGET_LOOP. */
2945 /* The label jumped to by INSN is no longer a loop
2946 exit. Unless INSN does not have a label (e.g.,
2947 it is a RETURN insn), search loop->exit_labels
2948 to find its label_ref, and remove it. Also turn
2949 off LABEL_OUTSIDE_LOOP_P bit. */
2951 {
2953 r;
2956 {
2960 else
2963 }
2969 /* If we didn't find it, then something is
2970 wrong. */
2973 }
2975 /* P is now a jump outside the loop, so it must be put
2976 in loop->exit_labels, and marked as such.
2977 The easiest way to do this is to just call
2978 mark_loop_jump again for P. */
2981 /* If INSN now jumps to the insn after it,
2982 delete INSN. */
2987 }
2989 /* Continue the loop after where the conditional
2990 branch used to jump, since the only branch insn
2991 in the block (if it still remains) is an inter-loop
2992 branch and hence needs no processing. */
2998 /* This loop will be continued with NEXT_INSN (insn). */
3000 }
3001 }
3002 }
3003 }
3004 }
3006 /* If any label in X jumps to a loop different from LOOP_NUM and any of the
3007 loops it is contained in, mark the target loop invalid.
3009 For speed, we assume that X is part of a pattern of a JUMP_INSN. */
3011 static void
3013 {
3019 {
3031 /* There could be a label reference in here. */
3043 /* This may refer to a LABEL_REF or SYMBOL_REF. */
3055 /* Link together all labels that branch outside the loop. This
3056 is used by final_[bg]iv_value and the loop unrolling code. Also
3057 mark this LABEL_REF so we know that this branch should predict
3058 false. */
3060 /* A check to make sure the label is not in an inner nested loop,
3061 since this does not count as a loop exit. */
3063 {
3068 }
3069 else
3073 {
3082 }
3084 /* If this is inside a loop, but not in the current loop or one enclosed
3085 by it, it invalidates at least one loop. */
3090 /* We must invalidate every nested loop containing the target of this
3091 label, except those that also contain the jump insn. */
3094 {
3095 /* Stop when we reach a loop that also contains the jump insn. */
3100 /* If we get here, we know we need to invalidate a loop. */
3107 }
3111 /* If this is not setting pc, ignore. */
3133 /* Strictly speaking this is not a jump into the loop, only a possible
3134 jump out of the loop. However, we have no way to link the destination
3135 of this jump onto the list of exit labels. To be safe we mark this
3136 loop and any containing loops as invalid. */
3138 {
3140 {
3146 }
3147 }
3149 }
3150 }
3151 \f
3152 /* Return nonzero if there is a label in the range from
3153 insn INSN to and including the insn whose luid is END
3154 INSN must have an assigned luid (i.e., it must not have
3155 been previously created by loop.c). */
3157 static int
3159 {
3161 {
3165 }
3168 }
3170 /* Record that a memory reference X is being set. */
3172 static void
3175 {
3181 /* Count number of memory writes.
3182 This affects heuristics in strength_reduce. */
3185 /* BLKmode MEM means all memory is clobbered. */
3187 {
3190 else
3194 }
3198 }
3200 /* X is a value modified by an INSN that references a biv inside a loop
3201 exit test (ie, X is somehow related to the value of the biv). If X
3202 is a pseudo that is used more than once, then the biv is (effectively)
3203 used more than once. DATA is a pointer to a loop_regs structure. */
3205 static void
3207 {
3222 /* If we do not have usage information, or if we know the register
3223 is used more than once, note that fact for check_dbra_loop. */
3228 }
3229 \f
3230 /* Return nonzero if the rtx X is invariant over the current loop.
3232 The value is 2 if we refer to something only conditionally invariant.
3234 A memory ref is invariant if it is not volatile and does not conflict
3235 with anything stored in `loop_info->store_mems'. */
3237 int
3239 {
3246 rtx mem_list_entry;
3252 {
3260 /* A LABEL_REF is normally invariant, however, if we are unrolling
3261 loops, and this label is inside the loop, then it isn't invariant.
3262 This is because each unrolled copy of the loop body will have
3263 a copy of this label. If this was invariant, then an insn loading
3264 the address of this label into a register might get moved outside
3265 the loop, and then each loop body would end up using the same label.
3267 We don't know the loop bounds here though, so just fail for all
3268 labels. */
3271 else
3280 /* We used to check RTX_UNCHANGING_P (x) here, but that is invalid
3281 since the reg might be set by initialization within the loop. */
3292 /* Out-of-range regs can occur when we are called from unrolling.
3293 These have always been created by the unroller and are set in
3294 the loop, hence are never invariant. */
3305 /* Volatile memory references must be rejected. Do this before
3306 checking for read-only items, so that volatile read-only items
3307 will be rejected also. */
3311 /* See if there is any dependence between a store and this load. */
3314 {
3320 }
3322 /* It's not invalidated by a store in memory
3323 but we must still verify the address is invariant. */
3327 /* Don't mess with insns declared volatile. */
3334 }
3338 {
3340 {
3346 }
3348 {
3351 {
3357 }
3359 }
3360 }
3363 }
3364 \f
3365 /* Return nonzero if all the insns in the loop that set REG
3366 are INSN and the immediately following insns,
3367 and if each of those insns sets REG in an invariant way
3368 (not counting uses of REG in them).
3370 The value is 2 if some of these insns are only conditionally invariant.
3372 We assume that INSN itself is the first set of REG
3373 and that its source is invariant. */
3375 static int
3377 rtx insn)
3378 {
3382 rtx temp;
3383 /* Number of sets we have to insist on finding after INSN. */
3389 /* If N_SETS hit the limit, we can't rely on its value. */
3396 {
3398 rtx set;
3403 /* If library call, skip to end of it. */
3412 {
3417 {
3418 /* If this is a libcall, then any invariant REG_EQUAL note is OK.
3419 If this is an ordinary insn, then only CONSTANT_P REG_EQUAL
3420 notes are OK. */
3426 }
3427 }
3429 count--;
3431 {
3434 }
3435 }
3438 /* If loop_invariant_p ever returned 2, we return 2. */
3440 }
3442 #if 0
3443 /* I don't think this condition is sufficient to allow INSN
3444 to be moved, so we no longer test it. */
3446 /* Return 1 if all insns in the basic block of INSN and following INSN
3447 that set REG are invariant according to TABLE. */
3449 static int
3451 {
3456 {
3465 {
3468 }
3469 }
3470 }
3472 \f
3473 /* Look at all uses (not sets) of registers in X. For each, if it is
3474 the single use, set USAGE[REGNO] to INSN; if there was a previous use in
3475 a different insn, set USAGE[REGNO] to const0_rtx. */
3477 static void
3479 {
3491 {
3492 /* Don't count SET_DEST if it is a REG; otherwise count things
3493 in SET_DEST because if a register is partially modified, it won't
3494 show up as a potential movable so we don't care how USAGE is set
3495 for it. */
3499 }
3500 else
3502 {
3508 }
3509 }
3510 \f
3511 /* Count and record any set in X which is contained in INSN. Update
3512 REGS->array[I].MAY_NOT_OPTIMIZE and LAST_SET for any register I set
3513 in X. */
3515 static void
3517 {
3519 /* Don't move a reg that has an explicit clobber.
3520 It's not worth the pain to try to do it correctly. */
3524 {
3532 {
3536 {
3537 /* If this is the first setting of this reg
3538 in current basic block, and it was set before,
3539 it must be set in two basic blocks, so it cannot
3540 be moved out of the loop. */
3544 /* If this is not first setting in current basic block,
3545 see if reg was used in between previous one and this.
3546 If so, neither one can be moved. */
3553 }
3554 }
3555 }
3556 }
3557 \f
3558 /* Given a loop that is bounded by LOOP->START and LOOP->END and that
3559 is entered at LOOP->SCAN_START, return 1 if the register set in SET
3560 contained in insn INSN is used by any insn that precedes INSN in
3561 cyclic order starting from the loop entry point.
3563 We don't want to use INSN_LUID here because if we restrict INSN to those
3564 that have a valid INSN_LUID, it means we cannot move an invariant out
3565 from an inner loop past two loops. */
3567 static int
3569 {
3571 rtx p;
3573 /* Scan forward checking for register usage. If we hit INSN, we
3574 are done. Otherwise, if we hit LOOP->END, wrap around to LOOP->START. */
3576 {
3582 }
3585 }
3586 \f
3588 /* Information we collect about arrays that we might want to prefetch. */
3589 struct prefetch_info
3590 {
3594 index. */
3595 HOST_WIDE_INT index;
3597 iteration. */
3599 prefetch area in one iteration. */
3601 This is set only for loops with known
3602 iteration counts and is 0xffffffff
3603 otherwise. */
3607 };
3609 /* Data used by check_store function. */
3610 struct check_store_data
3611 {
3612 rtx mem_address;
3614 };
3620 /* Set mem_write when mem_address is found. Used as callback to
3621 note_stores. */
3622 static void
3624 {
3629 }
3630 \f
3631 /* Like rtx_equal_p, but attempts to swap commutative operands. This is
3632 important to get some addresses combined. Later more sophisticated
3633 transformations can be added when necessary.
3635 ??? Same trick with swapping operand is done at several other places.
3636 It can be nice to develop some common way to handle this. */
3638 static int
3640 {
3654 {
3659 }
3660 /* Compare the elements. If any pair of corresponding elements fails to
3661 match, return 0 for the whole thing. */
3665 {
3667 {
3679 /* Two vectors must have the same length. */
3683 /* And the corresponding elements must match. */
3701 /* These are just backpointers, so they don't matter. */
3707 /* It is believed that rtx's at this level will never
3708 contain anything but integers and other rtx's,
3709 except for within LABEL_REFs and SYMBOL_REFs. */
3712 }
3713 }
3715 }
3716 \f
3717 /* Remove constant addition value from the expression X (when present)
3718 and return it. */
3720 static HOST_WIDE_INT
3722 {
3726 /* Avoid clobbering a shared CONST expression. */
3728 {
3732 {
3735 }
3737 }
3740 {
3743 }
3745 /* For plus expression recurse on ourself. */
3747 {
3751 /* In case our parameter was constant, remove extra zero from the
3752 expression. */
3757 }
3760 }
3762 /* Attempt to identify accesses to arrays that are most likely to cause cache
3763 misses, and emit prefetch instructions a few prefetch blocks forward.
3765 To detect the arrays we use the GIV information that was collected by the
3766 strength reduction pass.
3768 The prefetch instructions are generated after the GIV information is done
3769 and before the strength reduction process. The new GIVs are injected into
3770 the strength reduction tables, so the prefetch addresses are optimized as
3771 well.
3773 GIVs are split into base address, stride, and constant addition values.
3774 GIVs with the same address, stride and close addition values are combined
3775 into a single prefetch. Also writes to GIVs are detected, so that prefetch
3776 for write instructions can be used for the block we write to, on machines
3777 that support write prefetches.
3779 Several heuristics are used to determine when to prefetch. They are
3780 controlled by defined symbols that can be overridden for each target. */
3782 static void
3784 {
3800 /* Consider only loops w/o calls. When a call is done, the loop is probably
3801 slow enough to read the memory. */
3803 {
3808 }
3810 /* Don't prefetch in loops known to have few iterations. */
3814 {
3819 }
3821 /* Search all induction variables and pick those interesting for the prefetch
3822 machinery. */
3824 {
3830 /* Expect all BIVs to be executed in each iteration. This makes our
3831 analysis more conservative. */
3833 {
3834 /* Discard non-constant additions that we can't handle well yet, and
3835 BIVs that are executed multiple times; such BIVs ought to be
3836 handled in the nested loop. We accept not_every_iteration BIVs,
3837 since these only result in larger strides and make our
3838 heuristics more conservative. */
3840 {
3842 {
3848 }
3850 }
3853 {
3855 {
3861 }
3863 }
3867 }
3873 {
3874 rtx address;
3875 rtx temp;
3884 /* See whether an induction variable is interesting to us and if
3885 not, report the reason. */
3889 /* We are interested only in constant stride memory references
3890 in order to be able to compute density easily. */
3894 else
3895 {
3898 {
3901 }
3903 /* On some targets, reversed order prefetches are not
3904 worthwhile. */
3908 /* Prefetch of accesses with an extreme stride might not be
3909 worthwhile, either. */
3914 /* Ignore GIVs with varying add values; we can't predict the
3915 value for the next iteration. */
3919 /* Ignore GIVs in the nested loops; they ought to have been
3920 handled already. */
3923 }
3926 {
3932 }
3934 /* Determine the pointer to the basic array we are examining. It is
3935 the sum of the BIV's initial value and the GIV's add_val. */
3945 /* When the GIV is not always executed, we might be better off by
3946 not dirtying the cache pages. */
3949 else
3950 {
3955 }
3957 /* Attempt to find another prefetch to the same array and see if we
3958 can merge this one. */
3962 {
3963 /* In case both access same array (same location
3964 just with small difference in constant indexes), merge
3965 the prefetches. Just do the later and the earlier will
3966 get prefetched from previous iteration.
3967 The artificial threshold should not be too small,
3968 but also not bigger than small portion of memory usually
3969 traversed by single loop. */
3972 {
3981 }
3985 {
3990 }
3991 }
3993 /* Merging failed. */
3995 {
4003 num_prefetches++;
4005 {
4010 }
4011 }
4012 }
4013 }
4016 {
4019 /* Attempt to calculate the total number of bytes fetched by all
4020 iterations of the loop. Avoid overflow. */
4025 else
4030 /* Prefetch might be worthwhile only when the loads/stores are dense. */
4035 {
4040 }
4041 else
4042 {
4048 }
4049 else
4052 /* Find how many prefetch instructions we'll use within the loop. */
4054 {
4060 }
4061 }
4063 /* Determine how many iterations ahead to prefetch within the loop, based
4064 on how many prefetches we currently expect to do within the loop. */
4066 {
4068 {
4074 }
4075 }
4076 /* We'll also use AHEAD to determine how many prefetch instructions to
4077 emit before a loop, so don't leave it zero. */
4082 {
4083 /* Update if we've decided not to prefetch anything within the loop. */
4087 /* Find how many prefetch instructions we'll use before the loop. */
4089 {
4097 }
4100 {
4120 }
4121 }
4124 {
4125 /* Record that this loop uses prefetch instructions. */
4129 {
4134 }
4135 }
4138 {
4142 {
4144 rtx insn;
4148 rtx seq;
4150 /* We can save some effort by offsetting the address on
4151 architectures with offsettable memory references. */
4154 else
4155 {
4161 }
4164 /* Make sure the address operand is valid for prefetch. */
4174 /* Check all insns emitted and record the new GIV
4175 information. */
4178 {
4183 }
4184 }
4187 {
4188 /* Emit insns before the loop to fetch the first cache lines or,
4189 if we're not prefetching within the loop, everything we expect
4190 to need. */
4192 {
4200 /* Functions called by LOOP_IV_ADD_EMIT_BEFORE expect a
4201 non-constant INIT_VAL to have the same mode as REG, which
4202 in this case we know to be Pmode. */
4204 {
4205 rtx seq;
4212 }
4218 loop_start);
4219 }
4220 }
4221 }
4224 }
4225 \f
4226 /* A "basic induction variable" or biv is a pseudo reg that is set
4227 (within this loop) only by incrementing or decrementing it. */
4228 /* A "general induction variable" or giv is a pseudo reg whose
4229 value is a linear function of a biv. */
4231 /* Bivs are recognized by `basic_induction_var';
4232 Givs by `general_induction_var'. */
4234 /* Communication with routines called via `note_stores'. */
4238 /* Dummy register to have nonzero DEST_REG for DEST_ADDR type givs. */
4242 /* ??? Unfinished optimizations, and possible future optimizations,
4243 for the strength reduction code. */
4245 /* ??? The interaction of biv elimination, and recognition of 'constant'
4246 bivs, may cause problems. */
4248 /* ??? Add heuristics so that DEST_ADDR strength reduction does not cause
4249 performance problems.
4251 Perhaps don't eliminate things that can be combined with an addressing
4252 mode. Find all givs that have the same biv, mult_val, and add_val;
4253 then for each giv, check to see if its only use dies in a following
4254 memory address. If so, generate a new memory address and check to see
4255 if it is valid. If it is valid, then store the modified memory address,
4256 otherwise, mark the giv as not done so that it will get its own iv. */
4258 /* ??? Could try to optimize branches when it is known that a biv is always
4259 positive. */
4261 /* ??? When replace a biv in a compare insn, we should replace with closest
4262 giv so that an optimized branch can still be recognized by the combiner,
4263 e.g. the VAX acb insn. */
4265 /* ??? Many of the checks involving uid_luid could be simplified if regscan
4266 was rerun in loop_optimize whenever a register was added or moved.
4267 Also, some of the optimizations could be a little less conservative. */
4268 \f
4269 /* Scan the loop body and call FNCALL for each insn. In the addition to the
4270 LOOP and INSN parameters pass MAYBE_MULTIPLE and NOT_EVERY_ITERATION to the
4271 callback.
4273 NOT_EVERY_ITERATION is 1 if current insn is not known to be executed at
4274 least once for every loop iteration except for the last one.
4276 MAYBE_MULTIPLE is 1 if current insn may be executed more than once for every
4277 loop iteration.
4278 */
4279 void
4281 {
4286 rtx p;
4288 /* If loop_scan_start points to the loop exit test, we have to be wary of
4289 subversive use of gotos inside expression statements. */
4293 /* Scan through loop and update NOT_EVERY_ITERATION and MAYBE_MULTIPLE. */
4297 {
4300 /* Past CODE_LABEL, we get to insns that may be executed multiple
4301 times. The only way we can be sure that they can't is if every
4302 jump insn between here and the end of the loop either
4303 returns, exits the loop, is a jump to a location that is still
4304 behind the label, or is a jump to the loop start. */
4307 {
4313 {
4318 {
4321 else
4325 }
4333 {
4336 }
4337 }
4338 }
4340 /* Past a jump, we get to insns for which we can't count
4341 on whether they will be executed during each iteration. */
4342 /* This code appears twice in strength_reduce. There is also similar
4343 code in scan_loop. */
4345 /* If we enter the loop in the middle, and scan around to the
4346 beginning, don't set not_every_iteration for that.
4347 This can be any kind of jump, since we want to know if insns
4348 will be executed if the loop is executed. */
4353 {
4356 /* If this is a jump outside the loop, then it also doesn't
4357 matter. Check to see if the target of this branch is on the
4358 loop->exits_labels list. */
4366 }
4369 {
4370 /* At the virtual top of a converted loop, insns are again known to
4371 be executed each iteration: logically, the loop begins here
4372 even though the exit code has been duplicated.
4374 Insns are also again known to be executed each iteration at
4375 the LOOP_CONT note. */
4381 loop_depth++;
4383 loop_depth--;
4384 }
4386 /* Note if we pass a loop latch. If we do, then we can not clear
4387 NOT_EVERY_ITERATION below when we pass the last CODE_LABEL in
4388 a loop since a jump before the last CODE_LABEL may have started
4389 a new loop iteration.
4391 Note that LOOP_TOP is only set for rotated loops and we need
4392 this check for all loops, so compare against the CODE_LABEL
4393 which immediately follows LOOP_START. */
4398 /* Unlike in the code motion pass where MAYBE_NEVER indicates that
4399 an insn may never be executed, NOT_EVERY_ITERATION indicates whether
4400 or not an insn is known to be executed each iteration of the
4401 loop, whether or not any iterations are known to occur.
4403 Therefore, if we have just passed a label and have no more labels
4404 between here and the test insn of the loop, and we have not passed
4405 a jump to the top of the loop, then we know these insns will be
4406 executed each iteration. */
4409 && !past_loop_latch
4414 }
4415 }
4416 \f
4417 static void
4419 {
4422 /* Temporary list pointers for traversing ivs->list. */
4429 /* Scan ivs->list to remove all regs that proved not to be bivs.
4430 Make a sanity check against regs->n_times_set. */
4432 {
4434 /* Above happens if register modified by subreg, etc. */
4435 /* Make sure it is not recognized as a basic induction var: */
4437 /* If never incremented, it is invariant that we decided not to
4438 move. So leave it alone. */
4440 {
4451 }
4452 else
4453 {
4458 }
4459 }
4460 }
4463 /* Determine how BIVS are initialized by looking through pre-header
4464 extended basic block. */
4465 static void
4467 {
4469 /* Temporary list pointers for traversing ivs->list. */
4472 rtx p;
4474 /* Find initial value for each biv by searching backwards from loop_start,
4475 halting at first label. Also record any test condition. */
4479 {
4480 rtx test;
4490 /* Record any test of a biv that branches around the loop if no store
4491 between it and the start of loop. We only care about tests with
4492 constants and registers and only certain of those. */
4502 {
4503 /* If an NE test, we have an initial value! */
4505 {
4509 }
4510 else
4512 }
4513 }
4514 }
4517 /* Look at the each biv and see if we can say anything better about its
4518 initial value from any initializing insns set up above. (This is done
4519 in two passes to avoid missing SETs in a PARALLEL.) */
4520 static void
4522 {
4524 /* Temporary list pointers for traversing ivs->list. */
4529 {
4530 rtx src;
4531 rtx note;
4536 /* IF INIT_INSN has a REG_EQUAL or REG_EQUIV note and the value
4537 is a constant, use the value of that. */
4543 else
4556 {
4560 {
4563 }
4564 }
4565 /* If we can't make it a giv,
4566 let biv keep initial value of "itself". */
4569 }
4570 }
4573 /* Search the loop for general induction variables. */
4575 static void
4577 {
4579 }
4582 /* For each giv for which we still don't know whether or not it is
4583 replaceable, check to see if it is replaceable because its final value
4584 can be calculated. */
4586 static void
4588 {
4593 {
4599 }
4600 }
4603 /* Return nonzero if it is possible to eliminate the biv BL provided
4604 all givs are reduced. This is possible if either the reg is not
4605 used outside the loop, or we can compute what its final value will
4606 be. */
4608 static int
4611 {
4612 /* For architectures with a decrement_and_branch_until_zero insn,
4613 don't do this if we put a REG_NONNEG note on the endtest for this
4614 biv. */
4616 #ifdef HAVE_decrement_and_branch_until_zero
4618 {
4623 }
4624 #endif
4626 /* Check that biv is used outside loop or if it has a final value.
4627 Compare against bl->init_insn rather than loop->start. We aren't
4628 concerned with any uses of the biv between init_insn and
4629 loop->start since these won't be affected by the value of the biv
4630 elsewhere in the function, so long as init_insn doesn't use the
4631 biv itself. */
4642 {
4650 }
4652 }
4655 /* Reduce each giv of BL that we have decided to reduce. */
4657 static void
4659 {
4663 {
4666 {
4669 /* If the code for derived givs immediately below has already
4670 allocated a new_reg, we must keep it. */
4674 #ifdef AUTO_INC_DEC
4675 /* If the target has auto-increment addressing modes, and
4676 this is an address giv, then try to put the increment
4677 immediately after its use, so that flow can create an
4678 auto-increment addressing mode. */
4681 /* We don't handle reversed biv's because bl->biv->insn
4682 does not have a valid INSN_LUID. */
4686 {
4687 /* If other giv's have been combined with this one, then
4688 this will work only if all uses of the other giv's occur
4689 before this giv's insn. This is difficult to check.
4691 We simplify this by looking for the common case where
4692 there is one DEST_REG giv, and this giv's insn is the
4693 last use of the dest_reg of that DEST_REG giv. If the
4694 increment occurs after the address giv, then we can
4695 perform the optimization. (Otherwise, the increment
4696 would have to go before other_giv, and we would not be
4697 able to combine it with the address giv to get an
4698 auto-inc address.) */
4700 {
4705 {
4708 else
4710 }
4717 }
4718 /* Check for case where increment is before the address
4719 giv. Do this test in "loop order". */
4728 else
4731 #ifdef HAVE_cc0
4732 {
4733 rtx prev;
4735 /* We can't put an insn immediately after one setting
4736 cc0, or immediately before one using cc0. */
4743 }
4744 #endif
4748 }
4749 #endif
4751 /* For each place where the biv is incremented, add an insn
4752 to increment the new, reduced reg for the giv. */
4754 {
4755 rtx insert_before;
4757 /* Skip if location is the same as a previous one. */
4764 else
4772 /* A multiply is acceptable here
4773 since this is presumed to be seldom executed. */
4777 }
4779 /* Add code at loop start to initialize giv's reduced reg. */
4784 }
4785 }
4786 }
4789 /* Check for givs whose first use is their definition and whose
4790 last use is the definition of another giv. If so, it is likely
4791 dead and should not be used to derive another giv nor to
4792 eliminate a biv. */
4794 static void
4796 {
4800 {
4807 {
4813 }
4814 }
4815 }
4818 static void
4820 {
4824 {
4831 /* Update expression if this was combined, in case other giv was
4832 replaced. */
4837 /* See if this register is known to be a pointer to something. If
4838 so, see if we can find the alignment. First see if there is a
4839 destination register that is a pointer. If so, this shares the
4840 alignment too. Next see if we can deduce anything from the
4841 computational information. If not, and this is a DEST_ADDR
4842 giv, at least we know that it's a pointer, though we don't know
4843 the alignment. */
4851 {
4860 }
4864 {
4872 }
4877 /* Store reduced reg as the address in the memref where we found
4878 this giv. */
4881 {
4883 }
4884 else
4885 {
4887 rtx note;
4889 /* Not replaceable; emit an insn to set the original giv reg from
4890 the reduced giv, same as above. */
4895 /* The original insn may have a REG_EQUAL note. This note is
4896 now incorrect and may result in invalid substitutions later.
4897 The original insn is dead, but may be part of a libcall
4898 sequence, which doesn't seem worth the bother of handling. */
4902 }
4904 /* When a loop is reversed, givs which depend on the reversed
4905 biv, and which are live outside the loop, must be set to their
4906 correct final value. This insn is only needed if the giv is
4907 not replaceable. The correct final value is the same as the
4908 value that the giv starts the reversed loop with. */
4919 {
4924 }
4925 }
4926 }
4929 static int
4932 rtx test_reg)
4933 {
4942 /* Reduce benefit if not replaceable, since we will insert a
4943 move-insn to replace the insn that calculates this giv. Don't do
4944 this unless the giv is a user variable, since it will often be
4945 marked non-replaceable because of the duplication of the exit
4946 code outside the loop. In such a case, the copies we insert are
4947 dead and will be deleted. So they don't have a cost. Similar
4948 situations exist. */
4949 /* ??? The new final_[bg]iv_value code does a much better job of
4950 finding replaceable giv's, and hence this code may no longer be
4951 necessary. */
4956 /* Decrease the benefit to count the add-insns that we will insert
4957 to increment the reduced reg for the giv. ??? This can
4958 overestimate the run-time cost of the additional insns, e.g. if
4959 there are multiple basic blocks that increment the biv, but only
4960 one of these blocks is executed during each iteration. There is
4961 no good way to detect cases like this with the current structure
4962 of the loop optimizer. This code is more accurate for
4963 determining code size than run-time benefits. */
4966 /* Decide whether to strength-reduce this giv or to leave the code
4967 unchanged (recompute it from the biv each time it is used). This
4968 decision can be made independently for each giv. */
4970 #ifdef AUTO_INC_DEC
4971 /* Attempt to guess whether autoincrement will handle some of the
4972 new add insns; if so, increase BENEFIT (undo the subtraction of
4973 add_cost that was done above). */
4975 /* Increasing the benefit is risky, since this is only a guess.
4976 Avoid increasing register pressure in cases where there would
4977 be no other benefit from reducing this giv. */
4980 {
4995 }
4996 #endif
4999 }
5002 /* Free IV structures for LOOP. */
5004 static void
5006 {
5013 {
5019 {
5022 }
5024 {
5027 }
5031 }
5032 }
5035 /* Perform strength reduction and induction variable elimination.
5037 Pseudo registers created during this function will be beyond the
5038 last valid index in several tables including
5039 REGS->ARRAY[I].N_TIMES_SET and REGNO_LAST_UID. This does not cause a
5040 problem here, because the added registers cannot be givs outside of
5041 their loop, and hence will never be reconsidered. But scan_loop
5042 must check regnos to make sure they are in bounds. */
5044 static void
5046 {
5050 rtx p;
5051 /* Temporary list pointer for traversing ivs->list. */
5053 /* Ratio of extra register life span we can justify
5054 for saving an instruction. More if loop doesn't call subroutines
5055 since in that case saving an insn makes more difference
5056 and more registers are available. */
5057 /* ??? could set this to last value of threshold in move_movables */
5059 /* Map of pseudo-register replacements. */
5071 /* Find all BIVs in loop. */
5074 /* Exit if there are no bivs. */
5076 {
5077 /* Can still unroll the loop anyways, but indicate that there is no
5078 strength reduction info available. */
5084 }
5086 /* Determine how BIVS are initialized by looking through pre-header
5087 extended basic block. */
5090 /* Look at the each biv and see if we can say anything better about its
5091 initial value from any initializing insns set up above. */
5094 /* Search the loop for general induction variables. */
5097 /* Try to calculate and save the number of loop iterations. This is
5098 set to zero if the actual number can not be calculated. This must
5099 be called after all giv's have been identified, since otherwise it may
5100 fail if the iteration variable is a giv. */
5103 #ifdef HAVE_prefetch
5106 #endif
5108 /* Now for each giv for which we still don't know whether or not it is
5109 replaceable, check to see if it is replaceable because its final value
5110 can be calculated. This must be done after loop_iterations is called,
5111 so that final_giv_value will work correctly. */
5114 /* Try to prove that the loop counter variable (if any) is always
5115 nonnegative; if so, record that fact with a REG_NONNEG note
5116 so that "decrement and branch until zero" insn can be used. */
5119 /* Create reg_map to hold substitutions for replaceable giv regs.
5120 Some givs might have been made from biv increments, so look at
5121 ivs->reg_iv_type for a suitable size. */
5125 /* Examine each iv class for feasibility of strength reduction/induction
5126 variable elimination. */
5129 {
5133 /* Test whether it will be possible to eliminate this biv
5134 provided all givs are reduced. */
5137 /* This will be true at the end, if all givs which depend on this
5138 biv have been strength reduced.
5139 We can't (currently) eliminate the biv unless this is so. */
5142 /* Check each extension dependent giv in this class to see if its
5143 root biv is safe from wrapping in the interior mode. */
5146 /* Combine all giv's for this iv_class. */
5150 {
5158 /* If an insn is not to be strength reduced, then set its ignore
5159 flag, and clear bl->all_reduced. */
5161 /* A giv that depends on a reversed biv must be reduced if it is
5162 used after the loop exit, otherwise, it would have the wrong
5163 value after the loop exit. To make it simple, just reduce all
5164 of such giv's whether or not we know they are used after the loop
5165 exit. */
5170 {
5178 }
5179 else
5180 {
5181 /* Check that we can increment the reduced giv without a
5182 multiply insn. If not, reject it. */
5187 {
5195 }
5196 }
5197 }
5199 /* Check for givs whose first use is their definition and whose
5200 last use is the definition of another giv. If so, it is likely
5201 dead and should not be used to derive another giv nor to
5202 eliminate a biv. */
5205 /* Reduce each giv that we decided to reduce. */
5208 /* Rescan all givs. If a giv is the same as a giv not reduced, mark it
5209 as not reduced.
5211 For each giv register that can be reduced now: if replaceable,
5212 substitute reduced reg wherever the old giv occurs;
5213 else add new move insn "giv_reg = reduced_reg". */
5216 /* All the givs based on the biv bl have been reduced if they
5217 merit it. */
5219 /* For each giv not marked as maybe dead that has been combined with a
5220 second giv, clear any "maybe dead" mark on that second giv.
5221 v->new_reg will either be or refer to the register of the giv it
5222 combined with.
5224 Doing this clearing avoids problems in biv elimination where
5225 a giv's new_reg is a complex value that can't be put in the
5226 insn but the giv combined with (with a reg as new_reg) is
5227 marked maybe_dead. Since the register will be used in either
5228 case, we'd prefer it be used from the simpler giv. */
5234 /* Try to eliminate the biv, if it is a candidate.
5235 This won't work if ! bl->all_reduced,
5236 since the givs we planned to use might not have been reduced.
5238 We have to be careful that we didn't initially think we could
5239 eliminate this biv because of a giv that we now think may be
5240 dead and shouldn't be used as a biv replacement.
5242 Also, there is the possibility that we may have a giv that looks
5243 like it can be used to eliminate a biv, but the resulting insn
5244 isn't valid. This can happen, for example, on the 88k, where a
5245 JUMP_INSN can compare a register only with zero. Attempts to
5246 replace it with a compare with a constant will fail.
5248 Note that in cases where this call fails, we may have replaced some
5249 of the occurrences of the biv with a giv, but no harm was done in
5250 doing so in the rare cases where it can occur. */
5254 {
5255 /* ?? If we created a new test to bypass the loop entirely,
5256 or otherwise drop straight in, based on this test, then
5257 we might want to rewrite it also. This way some later
5258 pass has more hope of removing the initialization of this
5259 biv entirely. */
5261 /* If final_value != 0, then the biv may be used after loop end
5262 and we must emit an insn to set it just in case.
5264 Reversed bivs already have an insn after the loop setting their
5265 value, so we don't need another one. We can't calculate the
5266 proper final value for such a biv here anyways. */
5275 }
5276 /* See above note wrt final_value. But since we couldn't eliminate
5277 the biv, we must set the value after the loop instead of before. */
5281 }
5283 /* Go through all the instructions in the loop, making all the
5284 register substitutions scheduled in REG_MAP. */
5289 {
5293 }
5296 {
5297 /* When we completely unroll a loop we will likely not need the increment
5298 of the loop BIV and we will not need the conditional branch at the
5299 end of the loop. */
5302 #ifdef HAVE_cc0
5303 /* When we completely unroll a loop on a HAVE_cc0 machine we will not
5304 need the comparison before the conditional branch at the end of the
5305 loop. */
5307 #endif
5309 /* We'll need one copy for each loop iteration. */
5312 /* A little slop to account for the ability to remove initialization
5313 code, better CSE, and other secondary benefits of completely
5314 unrolling some loops. */
5317 /* Clamp the value. */
5320 }
5322 /* Unroll loops from within strength reduction so that we can use the
5323 induction variable information that strength_reduce has already
5324 collected. Always unroll loops that would be as small or smaller
5325 unrolled than when rolled. */
5332 #ifdef HAVE_doloop_end
5337 /* In case number of iterations is known, drop branch prediction note
5338 in the branch. Do that only in second loop pass, as loop unrolling
5339 may change the number of iterations performed. */
5341 {
5342 unsigned HOST_WIDE_INT n
5347 }
5355 }
5356 \f
5357 /*Record all basic induction variables calculated in the insn. */
5358 static rtx
5361 {
5363 rtx set;
5364 rtx dest_reg;
5365 rtx inc_val;
5366 rtx mult_val;
5372 {
5377 {
5382 {
5383 /* It is a possible basic induction variable.
5384 Create and initialize an induction structure for it. */
5391 }
5394 }
5395 }
5397 }
5398 \f
5399 /* Record all givs calculated in the insn.
5400 A register is a giv if: it is only set once, it is a function of a
5401 biv and a constant (or invariant), and it is not a biv. */
5402 static rtx
5405 {
5408 rtx set;
5409 /* Look for a general induction variable in a register. */
5414 {
5415 rtx src_reg;
5416 rtx dest_reg;
5417 rtx add_val;
5418 rtx mult_val;
5419 rtx ext_val;
5422 rtx last_consec_insn;
5431 /* Equivalent expression is a giv. */
5436 /* Don't try to handle any regs made by loop optimization.
5437 We have nothing on them in regno_first_uid, etc. */
5439 /* Don't recognize a BASIC_INDUCT_VAR here. */
5441 /* This must be the only place where the register is set. */
5443 /* or all sets must be consecutive and make a giv. */
5448 {
5451 /* If this is a library call, increase benefit. */
5455 /* Skip the consecutive insns, if there are any. */
5463 }
5464 }
5466 /* Look for givs which are memory addresses. */
5469 maybe_multiple);
5471 /* Update the status of whether giv can derive other givs. This can
5472 change when we pass a label or an insn that updates a biv. */
5477 }
5478 \f
5479 /* Return 1 if X is a valid source for an initial value (or as value being
5480 compared against in an initial test).
5482 X must be either a register or constant and must not be clobbered between
5483 the current insn and the start of the loop.
5485 INSN is the insn containing X. */
5487 static int
5489 {
5493 /* Only consider pseudos we know about initialized in insns whose luids
5494 we know. */
5499 /* Don't use call-clobbered registers across a call which clobbers it. On
5500 some machines, don't use any hard registers at all. */
5502 && (SMALL_REGISTER_CLASSES
5506 /* Don't use registers that have been clobbered before the start of the
5507 loop. */
5512 }
5513 \f
5514 /* Scan X for memory refs and check each memory address
5515 as a possible giv. INSN is the insn whose pattern X comes from.
5516 NOT_EVERY_ITERATION is 1 if the insn might not be executed during
5517 every loop iteration. MAYBE_MULTIPLE is 1 if the insn might be executed
5518 more than once in each loop iteration. */
5520 static void
5523 {
5533 {
5549 {
5550 rtx src_reg;
5551 rtx add_val;
5552 rtx mult_val;
5553 rtx ext_val;
5556 /* This code used to disable creating GIVs with mult_val == 1 and
5557 add_val == 0. However, this leads to lost optimizations when
5558 it comes time to combine a set of related DEST_ADDR GIVs, since
5559 this one would not be seen. */
5564 {
5565 /* Found one; record it. */
5573 }
5574 }
5579 }
5581 /* Recursively scan the subexpressions for other mem refs. */
5587 maybe_multiple);
5591 maybe_multiple);
5592 }
5593 \f
5594 /* Fill in the data about one biv update.
5595 V is the `struct induction' in which we record the biv. (It is
5596 allocated by the caller, with alloca.)
5597 INSN is the insn that sets it.
5598 DEST_REG is the biv's reg.
5600 MULT_VAL is const1_rtx if the biv is being incremented here, in which case
5601 INC_VAL is the increment. Otherwise, MULT_VAL is const0_rtx and the biv is
5602 being set to INC_VAL.
5604 NOT_EVERY_ITERATION is nonzero if this biv update is not know to be
5605 executed every iteration; MAYBE_MULTIPLE is nonzero if this biv update
5606 can be executed more than once per iteration. If MAYBE_MULTIPLE
5607 and NOT_EVERY_ITERATION are both zero, we know that the biv update is
5608 executed exactly once per iteration. */
5610 static void
5614 {
5631 /* Add this to the reg's iv_class, creating a class
5632 if this is the first incrementation of the reg. */
5636 {
5637 /* Create and initialize new iv_class. */
5647 /* Set initial value to the reg itself. */
5650 /* We haven't seen the initializing insn yet */
5660 /* Add this class to ivs->list. */
5664 /* Put it in the array of biv register classes. */
5666 }
5667 else
5668 {
5669 /* Check if location is the same as a previous one. */
5673 {
5676 }
5677 }
5679 /* Update IV_CLASS entry for this biv. */
5688 }
5689 \f
5690 /* Fill in the data about one giv.
5691 V is the `struct induction' in which we record the giv. (It is
5692 allocated by the caller, with alloca.)
5693 INSN is the insn that sets it.
5694 BENEFIT estimates the savings from deleting this insn.
5695 TYPE is DEST_REG or DEST_ADDR; it says whether the giv is computed
5696 into a register or is used as a memory address.
5698 SRC_REG is the biv reg which the giv is computed from.
5699 DEST_REG is the giv's reg (if the giv is stored in a reg).
5700 MULT_VAL and ADD_VAL are the coefficients used to compute the giv.
5701 LOCATION points to the place where this giv's value appears in INSN. */
5703 static void
5708 {
5713 rtx temp;
5715 /* Attempt to prove constantness of the values. Don't let simplify_rtx
5716 undo the MULT canonicalization that we performed earlier. */
5746 /* The v->always_computable field is used in update_giv_derive, to
5747 determine whether a giv can be used to derive another giv. For a
5748 DEST_REG giv, INSN computes a new value for the giv, so its value
5749 isn't computable if INSN insn't executed every iteration.
5750 However, for a DEST_ADDR giv, INSN merely uses the value of the giv;
5751 it does not compute a new value. Hence the value is always computable
5752 regardless of whether INSN is executed each iteration. */
5756 else
5762 {
5765 }
5767 {
5772 /* If the lifetime is zero, it means that this register is
5773 really a dead store. So mark this as a giv that can be
5774 ignored. This will not prevent the biv from being eliminated. */
5780 }
5782 /* Add the giv to the class of givs computed from one biv. */
5786 {
5789 /* Don't count DEST_ADDR. This is supposed to count the number of
5790 insns that calculate givs. */
5794 }
5795 else
5796 /* Fatal error, biv missing for this giv? */
5800 {
5803 }
5804 else
5805 {
5806 /* The giv can be replaced outright by the reduced register only if all
5807 of the following conditions are true:
5808 - the insn that sets the giv is always executed on any iteration
5809 on which the giv is used at all
5810 (there are two ways to deduce this:
5811 either the insn is executed on every iteration,
5812 or all uses follow that insn in the same basic block),
5813 - the giv is not used outside the loop
5814 - no assignments to the biv occur during the giv's lifetime. */
5817 /* Previous line always fails if INSN was moved by loop opt. */
5820 && (! not_every_iteration
5822 {
5823 /* Now check that there are no assignments to the biv within the
5824 giv's lifetime. This requires two separate checks. */
5826 /* Check each biv update, and fail if any are between the first
5827 and last use of the giv.
5829 If this loop contains an inner loop that was unrolled, then
5830 the insn modifying the biv may have been emitted by the loop
5831 unrolling code, and hence does not have a valid luid. Just
5832 mark the biv as not replaceable in this case. It is not very
5833 useful as a biv, because it is used in two different loops.
5834 It is very unlikely that we would be able to optimize the giv
5835 using this biv anyways. */
5840 {
5846 {
5850 }
5851 }
5853 /* If there are any backwards branches that go from after the
5854 biv update to before it, then this giv is not replaceable. */
5858 {
5862 }
5863 }
5864 else
5865 {
5866 /* May still be replaceable, we don't have enough info here to
5867 decide. */
5870 }
5871 }
5873 /* Record whether the add_val contains a const_int, for later use by
5874 combine_givs. */
5875 {
5880 ;
5884 {
5886 {
5891 else
5893 }
5896 }
5897 }
5901 }
5903 /* All this does is determine whether a giv can be made replaceable because
5904 its final value can be calculated. This code can not be part of record_giv
5905 above, because final_giv_value requires that the number of loop iterations
5906 be known, and that can not be accurately calculated until after all givs
5907 have been identified. */
5909 static void
5911 {
5914 /* DEST_ADDR givs will never reach here, because they are always marked
5915 replaceable above in record_giv. */
5917 /* The giv can be replaced outright by the reduced register only if all
5918 of the following conditions are true:
5919 - the insn that sets the giv is always executed on any iteration
5920 on which the giv is used at all
5921 (there are two ways to deduce this:
5922 either the insn is executed on every iteration,
5923 or all uses follow that insn in the same basic block),
5924 - its final value can be calculated (this condition is different
5925 than the one above in record_giv)
5926 - it's not used before the it's set
5927 - no assignments to the biv occur during the giv's lifetime. */
5929 #if 0
5930 /* This is only called now when replaceable is known to be false. */
5931 /* Clear replaceable, so that it won't confuse final_giv_value. */
5933 #endif
5938 {
5941 rtx last_giv_use;
5946 /* When trying to determine whether or not a biv increment occurs
5947 during the lifetime of the giv, we can ignore uses of the variable
5948 outside the loop because final_value is true. Hence we can not
5949 use regno_last_uid and regno_first_uid as above in record_giv. */
5951 /* Search the loop to determine whether any assignments to the
5952 biv occur during the giv's lifetime. Start with the insn
5953 that sets the giv, and search around the loop until we come
5954 back to that insn again.
5956 Also fail if there is a jump within the giv's lifetime that jumps
5957 to somewhere outside the lifetime but still within the loop. This
5958 catches spaghetti code where the execution order is not linear, and
5959 hence the above test fails. Here we assume that the giv lifetime
5960 does not extend from one iteration of the loop to the next, so as
5961 to make the test easier. Since the lifetime isn't known yet,
5962 this requires two loops. See also record_giv above. */
5967 {
5970 {
5973 }
5979 {
5980 /* It is possible for the BIV increment to use the GIV if we
5981 have a cycle. Thus we must be sure to check each insn for
5982 both BIV and GIV uses, and we must check for BIV uses
5983 first. */
5990 {
5992 {
5996 }
5998 }
5999 }
6000 }
6002 /* Now that the lifetime of the giv is known, check for branches
6003 from within the lifetime to outside the lifetime if it is still
6004 replaceable. */
6007 {
6010 {
6023 {
6032 }
6033 }
6034 }
6036 /* If it is replaceable, then save the final value. */
6039 }
6044 }
6045 \f
6046 /* Update the status of whether a giv can derive other givs.
6048 We need to do something special if there is or may be an update to the biv
6049 between the time the giv is defined and the time it is used to derive
6050 another giv.
6052 In addition, a giv that is only conditionally set is not allowed to
6053 derive another giv once a label has been passed.
6055 The cases we look at are when a label or an update to a biv is passed. */
6057 static void
6059 {
6063 rtx tem;
6066 /* Search all IV classes, then all bivs, and finally all givs.
6068 There are three cases we are concerned with. First we have the situation
6069 of a giv that is only updated conditionally. In that case, it may not
6070 derive any givs after a label is passed.
6072 The second case is when a biv update occurs, or may occur, after the
6073 definition of a giv. For certain biv updates (see below) that are
6074 known to occur between the giv definition and use, we can adjust the
6075 giv definition. For others, or when the biv update is conditional,
6076 we must prevent the giv from deriving any other givs. There are two
6077 sub-cases within this case.
6079 If this is a label, we are concerned with any biv update that is done
6080 conditionally, since it may be done after the giv is defined followed by
6081 a branch here (actually, we need to pass both a jump and a label, but
6082 this extra tracking doesn't seem worth it).
6084 If this is a jump, we are concerned about any biv update that may be
6085 executed multiple times. We are actually only concerned about
6086 backward jumps, but it is probably not worth performing the test
6087 on the jump again here.
6089 If this is a biv update, we must adjust the giv status to show that a
6090 subsequent biv update was performed. If this adjustment cannot be done,
6091 the giv cannot derive further givs. */
6097 {
6099 {
6100 /* If cant_derive is already true, there is no point in
6101 checking all of these conditions again. */
6105 /* If this giv is conditionally set and we have passed a label,
6106 it cannot derive anything. */
6110 /* Skip givs that have mult_val == 0, since
6111 they are really invariants. Also skip those that are
6112 replaceable, since we know their lifetime doesn't contain
6113 any biv update. */
6117 /* The only way we can allow this giv to derive another
6118 is if this is a biv increment and we can form the product
6119 of biv->add_val and giv->mult_val. In this case, we will
6120 be able to compute a compensation. */
6122 {
6123 rtx ext_val_dummy;
6134 tem = simplify_giv_expr
6141 else
6143 }
6147 }
6148 }
6149 }
6150 \f
6151 /* Check whether an insn is an increment legitimate for a basic induction var.
6152 X is the source of insn P, or a part of it.
6153 MODE is the mode in which X should be interpreted.
6155 DEST_REG is the putative biv, also the destination of the insn.
6156 We accept patterns of these forms:
6157 REG = REG + INVARIANT (includes REG = REG - CONSTANT)
6158 REG = INVARIANT + REG
6160 If X is suitable, we return 1, set *MULT_VAL to CONST1_RTX,
6161 store the additive term into *INC_VAL, and store the place where
6162 we found the additive term into *LOCATION.
6164 If X is an assignment of an invariant into DEST_REG, we set
6165 *MULT_VAL to CONST0_RTX, and store the invariant into *INC_VAL.
6167 We also want to detect a BIV when it corresponds to a variable
6168 whose mode was promoted via PROMOTED_MODE. In that case, an increment
6169 of the variable may be a PLUS that adds a SUBREG of that variable to
6170 an invariant and then sign- or zero-extends the result of the PLUS
6171 into the variable.
6173 Most GIVs in such cases will be in the promoted mode, since that is the
6174 probably the natural computation mode (and almost certainly the mode
6175 used for addresses) on the machine. So we view the pseudo-reg containing
6176 the variable as the BIV, as if it were simply incremented.
6178 Note that treating the entire pseudo as a BIV will result in making
6179 simple increments to any GIVs based on it. However, if the variable
6180 overflows in its declared mode but not its promoted mode, the result will
6181 be incorrect. This is acceptable if the variable is signed, since
6182 overflows in such cases are undefined, but not if it is unsigned, since
6183 those overflows are defined. So we only check for SIGN_EXTEND and
6184 not ZERO_EXTEND.
6186 If we cannot find a biv, we return 0. */
6188 static int
6192 {
6200 {
6206 {
6208 }
6213 {
6215 }
6216 else
6223 /* convert_modes can emit new instructions, e.g. when arg is a loop
6224 invariant MEM and dest_reg has a different mode.
6225 These instructions would be emitted after the end of the function
6226 and then *inc_val would be an unitialized pseudo.
6227 Detect this and bail in this case.
6228 Other alternatives to solve this can be introducing a convert_modes
6229 variant which is allowed to fail but not allowed to emit new
6230 instructions, emit these instructions before loop start and let
6231 it be garbage collected if *inc_val is never used or saving the
6232 *inc_val initialization sequence generated here and when *inc_val
6233 is going to be actually used, emit it at some suitable place. */
6237 {
6240 }
6248 /* If what's inside the SUBREG is a BIV, then the SUBREG. This will
6249 handle addition of promoted variables.
6250 ??? The comment at the start of this function is wrong: promoted
6251 variable increments don't look like it says they do. */
6257 /* If this register is assigned in a previous insn, look at its
6258 source, but don't go outside the loop or past a label. */
6260 /* If this sets a register to itself, we would repeat any previous
6261 biv increment if we applied this strategy blindly. */
6267 {
6268 rtx dest;
6269 do
6270 {
6272 }
6301 }
6302 /* Fall through. */
6304 /* Can accept constant setting of biv only when inside inner most loop.
6305 Otherwise, a biv of an inner loop may be incorrectly recognized
6306 as a biv of the outer loop,
6307 causing code to be moved INTO the inner loop. */
6314 /* convert_modes aborts if we try to convert to or from CCmode, so just
6315 exclude that case. It is very unlikely that a condition code value
6316 would be a useful iterator anyways. convert_modes aborts if we try to
6317 convert a float mode to non-float or vice versa too. */
6321 {
6322 /* Possible bug here? Perhaps we don't know the mode of X. */
6326 {
6329 }
6334 }
6335 else
6339 /* Ignore this BIV if signed arithmetic overflow is defined. */
6346 /* Similar, since this can be a sign extension. */
6351 ;
6365 location);
6370 }
6371 }
6372 \f
6373 /* A general induction variable (giv) is any quantity that is a linear
6374 function of a basic induction variable,
6375 i.e. giv = biv * mult_val + add_val.
6376 The coefficients can be any loop invariant quantity.
6377 A giv need not be computed directly from the biv;
6378 it can be computed by way of other givs. */
6380 /* Determine whether X computes a giv.
6381 If it does, return a nonzero value
6382 which is the benefit from eliminating the computation of X;
6383 set *SRC_REG to the register of the biv that it is computed from;
6384 set *ADD_VAL and *MULT_VAL to the coefficients,
6385 such that the value of X is biv * mult + add; */
6387 static int
6392 {
6396 /* If this is an invariant, forget it, it isn't a giv. */
6407 {
6410 /* Since this is now an invariant and wasn't before, it must be a giv
6411 with MULT_VAL == 0. It doesn't matter which BIV we associate this
6412 with. */
6419 /* This is equivalent to a BIV. */
6426 /* Either (plus (biv) (invar)) or
6427 (plus (mult (biv) (invar_1)) (invar_2)). */
6429 {
6432 }
6433 else
6434 {
6437 }
6442 /* ADD_VAL is zero. */
6450 }
6452 /* Remove any enclosing USE from ADD_VAL and MULT_VAL (there will be
6453 unless they are CONST_INT). */
6461 else
6464 /* Always return true if this is a giv so it will be detected as such,
6465 even if the benefit is zero or negative. This allows elimination
6466 of bivs that might otherwise not be eliminated. */
6468 }
6469 \f
6470 /* Given an expression, X, try to form it as a linear function of a biv.
6471 We will canonicalize it to be of the form
6472 (plus (mult (BIV) (invar_1))
6473 (invar_2))
6474 with possible degeneracies.
6476 The invariant expressions must each be of a form that can be used as a
6477 machine operand. We surround then with a USE rtx (a hack, but localized
6478 and certainly unambiguous!) if not a CONST_INT for simplicity in this
6479 routine; it is the caller's responsibility to strip them.
6481 If no such canonicalization is possible (i.e., two biv's are used or an
6482 expression that is neither invariant nor a biv or giv), this routine
6483 returns 0.
6485 For a nonzero return, the result will have a code of CONST_INT, USE,
6486 REG (for a BIV), PLUS, or MULT. No other codes will occur.
6488 *BENEFIT will be incremented by the benefit of any sub-giv encountered. */
6493 static rtx
6495 {
6500 rtx tem;
6502 /* If this is not an integer mode, or if we cannot do arithmetic in this
6503 mode, this can't be a giv. */
6510 {
6517 /* Put constant last, CONST_INT last if both constant. */
6525 /* Handle addition of zero, then addition of an invariant. */
6530 {
6533 /* Adding two invariants must result in an invariant, so enclose
6534 addition operation inside a USE and return it. */
6544 else
6553 /* biv + invar or mult + invar. Return sum. */
6557 /* (a + invar_1) + invar_2. Associate. */
6558 return
6564 arg1)),
6569 }
6571 /* Each argument must be either REG, PLUS, or MULT. Convert REG to
6572 MULT to reduce cases. */
6578 /* Now have PLUS + PLUS, PLUS + MULT, MULT + PLUS, or MULT + MULT.
6579 Put a MULT first, leaving PLUS + PLUS, MULT + PLUS, or MULT + MULT.
6580 Recurse to associate the second PLUS. */
6585 return
6593 /* Now must have MULT + MULT. Distribute if same biv, else not giv. */
6609 /* Handle "a - b" as "a + b * (-1)". */
6615 constm1_rtx)),
6624 /* Put constant last, CONST_INT last if both constant. */
6629 /* If second argument is not now constant, not giv. */
6633 /* Handle multiply by 0 or 1. */
6641 {
6643 /* biv * invar. Done. */
6647 /* Product of two constants. */
6651 /* invar * invar is a giv, but attempt to simplify it somehow. */
6657 {
6658 /* (invar_0 * invar_1) * invar_2. Associate. */
6665 arg1)),
6667 }
6668 /* Propagate the MULT expressions to the intermost nodes. */
6670 {
6671 /* (invar_0 + invar_1) * invar_2. Distribute. */
6677 arg1),
6681 arg1)),
6683 }
6687 /* (a * invar_1) * invar_2. Associate. */
6693 arg1)),
6697 /* (a + invar_1) * invar_2. Distribute. */
6702 arg1),
6705 arg1)),
6710 }
6713 /* Shift by constant is multiply by power of two. */
6717 return
6726 /* "-a" is "a * (-1)" */
6732 /* "~a" is "-a - 1". Silly, but easy. */
6736 const1_rtx),
6740 /* Already in proper form for invariant. */
6746 /* Conditionally recognize extensions of simple IVs. After we've
6747 computed loop traversal counts and verified the range of the
6748 source IV, we'll reevaluate this as a GIV. */
6750 {
6753 {
6756 }
6757 }
6761 /* If this is a new register, we can't deal with it. */
6765 /* Check for biv or giv. */
6767 {
6771 {
6774 /* Form expression from giv and add benefit. Ensure this giv
6775 can derive another and subtract any needed adjustment if so. */
6777 /* Increasing the benefit here is risky. The only case in which it
6778 is arguably correct is if this is the only use of V. In other
6779 cases, this will artificially inflate the benefit of the current
6780 giv, and lead to suboptimal code. Thus, it is disabled, since
6781 potentially not reducing an only marginally beneficial giv is
6782 less harmful than reducing many givs that are not really
6783 beneficial. */
6784 {
6788 }
6801 {
6804 }
6805 else
6806 {
6809 }
6811 }
6814 do_default:
6815 /* If it isn't an induction variable, and it is invariant, we
6816 may be able to simplify things further by looking through
6817 the bits we just moved outside the loop. */
6819 {
6825 {
6826 /* Ok, we found a match. Substitute and simplify. */
6828 /* If we match another movable, we must use that, as
6829 this one is going away. */
6834 /* If consec is nonzero, this is a member of a group of
6835 instructions that were moved together. We handle this
6836 case only to the point of seeking to the last insn and
6837 looking for a REG_EQUAL. Fail if we don't find one. */
6839 {
6842 do
6843 {
6845 }
6851 }
6852 else
6853 {
6857 }
6860 {
6861 /* What we are most interested in is pointer
6862 arithmetic on invariants -- only take
6863 patterns we may be able to do something with. */
6869 {
6871 benefit);
6874 }
6879 {
6884 }
6885 }
6887 }
6888 }
6890 }
6892 /* Fall through to general case. */
6894 /* If invariant, return as USE (unless CONST_INT).
6895 Otherwise, not giv. */
6900 {
6909 }
6910 else
6912 }
6913 }
6915 /* This routine folds invariants such that there is only ever one
6916 CONST_INT in the summation. It is only used by simplify_giv_expr. */
6918 static rtx
6920 {
6926 {
6929 }
6932 {
6935 }
6936 else
6937 {
6940 }
6941 }
6943 static rtx
6945 {
6947 {
6951 else
6954 }
6957 else
6960 }
6961 \f
6962 /* Help detect a giv that is calculated by several consecutive insns;
6963 for example,
6964 giv = biv * M
6965 giv = giv + A
6966 The caller has already identified the first insn P as having a giv as dest;
6967 we check that all other insns that set the same register follow
6968 immediately after P, that they alter nothing else,
6969 and that the result of the last is still a giv.
6971 The value is 0 if the reg set in P is not really a giv.
6972 Otherwise, the value is the amount gained by eliminating
6973 all the consecutive insns that compute the value.
6975 FIRST_BENEFIT is the amount gained by eliminating the first insn, P.
6976 SRC_REG is the reg of the biv; DEST_REG is the reg of the giv.
6978 The coefficients of the ultimate giv value are stored in
6979 *MULT_VAL and *ADD_VAL. */
6981 static int
6985 {
6991 rtx temp;
6992 rtx set;
6994 /* Indicate that this is a giv so that we can update the value produced in
6995 each insn of the multi-insn sequence.
6997 This induction structure will be used only by the call to
6998 general_induction_var below, so we can allocate it on our stack.
6999 If this is a giv, our caller will replace the induct var entry with
7000 a new induction structure. */
7021 {
7025 /* If libcall, skip to end of call sequence. */
7036 /* Giv created by equivalent expression. */
7042 {
7046 count--;
7050 }
7052 {
7053 /* Allow insns that set something other than this giv to a
7054 constant. Such insns are needed on machines which cannot
7055 include long constants and should not disqualify a giv. */
7064 }
7065 }
7070 }
7071 \f
7072 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7073 represented by G1. If no such expression can be found, or it is clear that
7074 it cannot possibly be a valid address, 0 is returned.
7076 To perform the computation, we note that
7077 G1 = x * v + a and
7078 G2 = y * v + b
7079 where `v' is the biv.
7081 So G2 = (y/b) * G1 + (b - a*y/x).
7083 Note that MULT = y/x.
7085 Update: A and B are now allowed to be additive expressions such that
7086 B contains all variables in A. That is, computing B-A will not require
7087 subtracting variables. */
7089 static rtx
7091 {
7092 /* If MULT is zero, then A*MULT is zero, and our expression is B. */
7097 /* If MULT is not 1, we cannot handle A with non-constants, since we
7098 would then be required to subtract multiples of the registers in A.
7099 This is theoretically possible, and may even apply to some Fortran
7100 constructs, but it is a lot of work and we do not attempt it here. */
7105 /* In general these structures are sorted top to bottom (down the PLUS
7106 chain), but not left to right across the PLUS. If B is a higher
7107 order giv than A, we can strip one level and recurse. If A is higher
7108 order, we'll eventually bail out, but won't know that until the end.
7109 If they are the same, we'll strip one level around this loop. */
7112 {
7124 /* We matched: remove one reg completely. */
7127 /* An alternate match. */
7130 /* An alternate match. */
7132 else
7133 {
7134 /* Indicates an extra register in B. Strip one level from B and
7135 recurse, hoping B was the higher order expression. */
7140 }
7141 }
7143 /* Here we are at the last level of A, go through the cases hoping to
7144 get rid of everything but a constant. */
7147 {
7160 }
7162 {
7164 }
7166 {
7171 }
7173 {
7178 else
7180 }
7185 }
7187 rtx
7189 {
7192 /* The value that G1 will be multiplied by must be a constant integer. Also,
7193 the only chance we have of getting a valid address is if b*c/a (see above
7194 for notation) is also an integer. */
7197 {
7202 }
7205 else
7206 {
7207 /* ??? Find out if the one is a multiple of the other? */
7209 }
7213 {
7214 /* Failed. If we've got a multiplication factor between G1 and G2,
7215 scale G1's addend and try again. */
7217 {
7221 {
7222 HOST_WIDE_INT m;
7226 }
7227 else
7228 {
7230 mult);
7231 }
7234 }
7235 }
7239 /* Form simplified final result. */
7244 else
7249 else
7250 {
7253 {
7257 }
7260 }
7261 }
7262 \f
7263 /* Return an rtx, if any, that expresses giv G2 as a function of the register
7264 represented by G1. This indicates that G2 should be combined with G1 and
7265 that G2 can use (either directly or via an address expression) a register
7266 used to represent G1. */
7268 static rtx
7270 {
7273 /* With the introduction of ext dependent givs, we must care for modes.
7274 G2 must not use a wider mode than G1. */
7284 /* If these givs are identical, they can be combined. We use the results
7285 of express_from because the addends are not in a canonical form, so
7286 rtx_equal_p is a weaker test. */
7287 /* But don't combine a DEST_REG giv with a DEST_ADDR giv; we want the
7288 combination to be the other way round. */
7291 {
7293 }
7295 /* If G2 can be expressed as a function of G1 and that function is valid
7296 as an address and no more expensive than using a register for G2,
7297 the expression of G2 in terms of G1 can be used. */
7304 }
7305 \f
7306 /* Check each extension dependent giv in this class to see if its
7307 root biv is safe from wrapping in the interior mode, which would
7308 make the giv illegal. */
7310 static void
7312 {
7316 HOST_WIDE_INT start_val;
7322 /* Make sure the iteration data is available. We must have
7323 constants in order to be certain of no overflow. */
7329 /* Make sure the host can represent the arithmetic. */
7331 {
7333 HOST_WIDE_INT s_end_val;
7345 /* Check for host arithmetic overflow. */
7347 {
7349 HOST_WIDE_INT s_max;
7356 /* Check zero extension of biv ok. */
7358 /* Check for host arithmetic overflow. */
7359 && (neg_incr
7362 /* Check for target arithmetic overflow. */
7363 && (neg_incr
7366 {
7368 }
7370 /* Check sign extension of biv ok. */
7371 /* ??? While it is true that overflow with signed and pointer
7372 arithmetic is undefined, I fear too many programmers don't
7373 keep this fact in mind -- myself included on occasion.
7374 So leave alone with the signed overflow optimizations. */
7376 /* Check for host arithmetic overflow. */
7377 && (neg_incr
7380 /* Check for target arithmetic overflow. */
7381 && (neg_incr
7384 {
7386 }
7387 }
7388 }
7390 /* If we know the BIV is compared at run-time against an
7391 invariant value, and the increment is +/- 1, we may also
7392 be able to prove that the BIV cannot overflow. */
7398 {
7399 /* If the increment is +1, and the exit test is a <,
7400 the BIV cannot overflow. (For <=, we have the
7401 problematic case that the comparison value might
7402 be the maximum value of the range.) */
7404 {
7409 }
7411 /* Likewise for increment -1 and exit test >. */
7413 {
7418 }
7419 }
7421 /* Invalidate givs that fail the tests. */
7424 {
7429 {
7438 /* We don't know whether this value is being used as either
7439 signed or unsigned, so to safely truncate we must satisfy
7440 both. The initial check here verifies the BIV itself;
7441 once that is successful we may check its range wrt the
7442 derived GIV. This works only if we were able to determine
7443 constant start and end values above. */
7445 {
7449 /* We know from the above that both endpoints are nonnegative,
7450 and that there is no wrapping. Verify that both endpoints
7451 are within the (signed) range of the outer mode. */
7454 }
7459 }
7462 {
7464 {
7468 }
7469 }
7470 else
7471 {
7473 {
7478 else
7479 {
7484 else
7486 }
7491 }
7494 }
7495 }
7496 }
7498 /* Generate a version of VALUE in a mode appropriate for initializing V. */
7500 rtx
7502 {
7508 /* Recall that check_ext_dependent_givs verified that the known bounds
7509 of a biv did not overflow or wrap with respect to the extension for
7510 the giv. Therefore, constants need no additional adjustment. */
7514 /* Otherwise, we must adjust the value to compensate for the
7515 differing modes of the biv and the giv. */
7517 }
7518 \f
7519 struct combine_givs_stats
7520 {
7523 };
7525 static int
7527 {
7534 /* Stabilize the sort. */
7538 }
7540 /* Check all pairs of givs for iv_class BL and see if any can be combined with
7541 any other. If so, point SAME to the giv combined with and set NEW_REG to
7542 be an expression (in terms of the other giv's DEST_REG) equivalent to the
7543 giv. Also, update BENEFIT and related fields for cost/benefit analysis. */
7545 static void
7547 {
7548 /* Additional benefit to add for being combined multiple times. */
7556 /* Count givs, because bl->giv_count is incorrect here. */
7560 giv_count++;
7572 {
7574 rtx single_use;
7579 /* If a DEST_REG GIV is used only once, do not allow it to combine
7580 with anything, for in doing so we will gain nothing that cannot
7581 be had by simply letting the GIV with which we would have combined
7582 to be reduced on its own. The losage shows up in particular with
7583 DEST_ADDR targets on hosts with reg+reg addressing, though it can
7584 be seen elsewhere as well. */
7591 /* Add an additional weight for zero addends. */
7596 {
7597 rtx this_combine;
7602 {
7605 }
7606 }
7608 }
7610 /* Iterate, combining until we can't. */
7611 restart:
7615 {
7618 {
7624 }
7626 }
7629 {
7635 /* If it has already been combined, skip. */
7640 {
7643 /* If it has already been combined, skip. */
7645 {
7650 /* For destination, we now may replace by mem expression instead
7651 of register. This changes the costs considerably, so add the
7652 compensation. */
7662 /* ??? The new final_[bg]iv_value code does a much better job
7663 of finding replaceable giv's, and hence this code may no
7664 longer be necessary. */
7668 /* To help optimize the next set of combinations, remove
7669 this giv from the benefits of other potential mates. */
7671 {
7675 }
7682 }
7683 }
7685 /* To help optimize the next set of combinations, remove
7686 this giv from the benefits of other potential mates. */
7688 {
7690 {
7694 }
7698 /* We've finished with this giv, and everything it touched.
7699 Restart the combination so that proper weights for the
7700 rest of the givs are properly taken into account. */
7701 /* ??? Ideally we would compact the arrays at this point, so
7702 as to not cover old ground. But sanely compacting
7703 can_combine is tricky. */
7705 }
7706 }
7708 /* Clean up. */
7711 }
7712 \f
7713 /* Generate sequence for REG = B * M + A. B is the initial value of
7714 the basic induction variable, M a multiplicative constant, A an
7715 additive constant and REG the destination register. */
7717 static rtx
7719 {
7720 rtx seq;
7721 rtx result;
7724 /* Use unsigned arithmetic. */
7732 }
7735 /* Update registers created in insn sequence SEQ. */
7737 static void
7739 {
7740 rtx insn;
7742 /* Update register info for alias analysis. */
7748 {
7751 {
7758 }
7759 }
7763 }
7766 /* EMIT code before BEFORE_BB/BEFORE_INSN to set REG = B * M + A. B
7767 is the initial value of the basic induction variable, M a
7768 multiplicative constant, A an additive constant and REG the
7769 destination register. */
7771 void
7774 {
7775 rtx seq;
7778 {
7781 }
7783 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7786 /* Increase the lifetime of any invariants moved further in code. */
7791 /* It is possible that the expansion created lots of new registers.
7792 Iterate over the sequence we just created and record them all. We
7793 must do this before inserting the sequence. */
7797 }
7800 /* Emit insns in loop pre-header to set REG = B * M + A. B is the
7801 initial value of the basic induction variable, M a multiplicative
7802 constant, A an additive constant and REG the destination
7803 register. */
7805 void
7807 {
7808 rtx seq;
7810 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7813 /* Increase the lifetime of any invariants moved further in code.
7814 ???? Is this really necessary? */
7819 /* It is possible that the expansion created lots of new registers.
7820 Iterate over the sequence we just created and record them all. We
7821 must do this before inserting the sequence. */
7825 }
7828 /* Emit insns after loop to set REG = B * M + A. B is the initial
7829 value of the basic induction variable, M a multiplicative constant,
7830 A an additive constant and REG the destination register. */
7832 void
7834 {
7835 rtx seq;
7837 /* Use copy_rtx to prevent unexpected sharing of these rtx. */
7840 /* It is possible that the expansion created lots of new registers.
7841 Iterate over the sequence we just created and record them all. We
7842 must do this before inserting the sequence. */
7846 }
7850 /* Similar to gen_add_mult, but compute cost rather than generating
7851 sequence. */
7853 static int
7855 {
7865 {
7870 }
7873 }
7874 \f
7875 /* Test whether A * B can be computed without
7876 an actual multiply insn. Value is 1 if so.
7878 ??? This function stinks because it generates a ton of wasted RTL
7879 ??? and as a result fragments GC memory to no end. There are other
7880 ??? places in the compiler which are invoked a lot and do the same
7881 ??? thing, generate wasted RTL just to see if something is possible. */
7883 static int
7885 {
7886 rtx tmp;
7889 /* If only one is constant, make it B. */
7893 /* If first constant, both constant, so don't need multiply. */
7897 /* If second not constant, neither is constant, so would need multiply. */
7901 /* One operand is constant, so might not need multiply insn. Generate the
7902 code for the multiply and see if a call or multiply, or long sequence
7903 of insns is generated. */
7912 {
7915 {
7925 {
7928 }
7931 }
7932 }
7942 }
7943 \f
7944 /* Check to see if loop can be terminated by a "decrement and branch until
7945 zero" instruction. If so, add a REG_NONNEG note to the branch insn if so.
7946 Also try reversing an increment loop to a decrement loop
7947 to see if the optimization can be performed.
7948 Value is nonzero if optimization was performed. */
7950 /* This is useful even if the architecture doesn't have such an insn,
7951 because it might change a loops which increments from 0 to n to a loop
7952 which decrements from n to 0. A loop that decrements to zero is usually
7953 faster than one that increments from zero. */
7955 /* ??? This could be rewritten to use some of the loop unrolling procedures,
7956 such as approx_final_value, biv_total_increment, loop_iterations, and
7957 final_[bg]iv_value. */
7959 static int
7961 {
7966 rtx reg;
7967 rtx jump_label;
7968 rtx final_value;
7969 rtx start_value;
7970 rtx new_add_val;
7971 rtx comparison;
7972 rtx before_comparison;
7973 rtx p;
7974 rtx jump;
7975 rtx first_compare;
7980 /* If last insn is a conditional branch, and the insn before tests a
7981 register value, try to optimize it. Otherwise, we can't do anything. */
7990 /* Try to compute whether the compare/branch at the loop end is one or
7991 two instructions. */
7997 else
8000 {
8001 /* If more than one condition is present to control the loop, then
8002 do not proceed, as this function does not know how to rewrite
8003 loop tests with more than one condition.
8005 Look backwards from the first insn in the last comparison
8006 sequence and see if we've got another comparison sequence. */
8008 rtx jump1;
8012 }
8014 /* Check all of the bivs to see if the compare uses one of them.
8015 Skip biv's set more than once because we can't guarantee that
8016 it will be zero on the last iteration. Also skip if the biv is
8017 used between its update and the test insn. */
8020 {
8025 first_compare))
8027 }
8032 /* Look for the case where the basic induction variable is always
8033 nonnegative, and equals zero on the last iteration.
8034 In this case, add a reg_note REG_NONNEG, which allows the
8035 m68k DBRA instruction to be used. */
8041 {
8042 /* Initial value must be greater than 0,
8043 init_val % -dec_value == 0 to ensure that it equals zero on
8044 the last iteration */
8050 {
8051 /* register always nonnegative, add REG_NOTE to branch */
8059 }
8061 /* If the decrement is 1 and the value was tested as >= 0 before
8062 the loop, then we can safely optimize. */
8064 {
8078 {
8086 }
8087 }
8088 }
8091 {
8092 /* Try to change inc to dec, so can apply above optimization. */
8093 /* Can do this if:
8094 all registers modified are induction variables or invariant,
8095 all memory references have non-overlapping addresses
8096 (obviously true if only one write)
8097 allow 2 insns for the compare/jump at the end of the loop. */
8098 /* Also, we must avoid any instructions which use both the reversed
8099 biv and another biv. Such instructions will fail if the loop is
8100 reversed. We meet this condition by requiring that either
8101 no_use_except_counting is true, or else that there is only
8102 one biv. */
8104 /* 1 if the iteration var is used only to count iterations. */
8106 /* 1 if the loop has no memory store, or it has a single memory store
8107 which is reversible. */
8113 {
8117 /* If there are no givs for this biv, and the only exit is the
8118 fall through at the end of the loop, then
8119 see if perhaps there are no uses except to count. */
8123 {
8128 /* An insn that sets the biv is okay. */
8129 ;
8131 /* An insn that doesn't mention the biv is okay. */
8132 ;
8135 {
8136 /* If either of these insns uses the biv and sets a pseudo
8137 that has more than one usage, then the biv has uses
8138 other than counting since it's used to derive a value
8139 that is used more than one time. */
8141 regs);
8143 {
8146 }
8147 }
8148 else
8149 {
8152 }
8153 }
8155 /* A biv has uses besides counting if it is used to set
8156 another biv. */
8160 {
8163 }
8164 }
8167 /* No need to worry about MEMs. */
8168 ;
8170 {
8175 /* If the loop has a single store, and the destination address is
8176 invariant, then we can't reverse the loop, because this address
8177 might then have the wrong value at loop exit.
8178 This would work if the source was invariant also, however, in that
8179 case, the insn should have been moved out of the loop. */
8182 {
8185 /* If we could prove that each of the memory locations
8186 written to was different, then we could reverse the
8187 store -- but we don't presently have any way of
8188 knowing that. */
8191 /* If the store depends on a register that is set after the
8192 store, it depends on the initial value, and is thus not
8193 reversible. */
8195 {
8202 }
8203 }
8204 }
8205 else
8208 /* This code only acts for innermost loops. Also it simplifies
8209 the memory address check by only reversing loops with
8210 zero or one memory access.
8211 Two memory accesses could involve parts of the same array,
8212 and that can't be reversed.
8213 If the biv is used only for counting, than we don't need to worry
8214 about all these things. */
8220 && reversible_mem_store
8225 {
8226 rtx tem;
8228 /* Loop can be reversed. */
8232 /* Now check other conditions:
8234 The increment must be a constant, as must the initial value,
8235 and the comparison code must be LT.
8237 This test can probably be improved since +/- 1 in the constant
8238 can be obtained by changing LT to LE and vice versa; this is
8239 confusing. */
8242 /* for constants, LE gets turned into LT */
8247 {
8258 comparison_const_width
8260 else
8261 comparison_const_width
8265 comparison_sign_mask
8268 /* If the comparison value is not a loop invariant, then we
8269 can not reverse this loop.
8271 ??? If the insns which initialize the comparison value as
8272 a whole compute an invariant result, then we could move
8273 them out of the loop and proceed with loop reversal. */
8281 /* Normalize the initial value if it is an integer and
8282 has no other use except as a counter. This will allow
8283 a few more loops to be reversed. */
8287 {
8289 /* The code below requires comparison_val to be a multiple
8290 of add_val in order to do the loop reversal, so
8291 round up comparison_val to a multiple of add_val.
8292 Since comparison_value is constant, we know that the
8293 current comparison code is LT. */
8295 comparison_val
8297 /* We postpone overflow checks for COMPARISON_VAL here;
8298 even if there is an overflow, we might still be able to
8299 reverse the loop, if converting the loop exit test to
8300 NE is possible. */
8302 }
8304 /* First check if we can do a vanilla loop reversal. */
8306 /* If we have a decrement_and_branch_on_count,
8307 prefer the NE test, since this will allow that
8308 instruction to be generated. Note that we must
8309 use a vanilla loop reversal if the biv is used to
8310 calculate a giv or has a non-counting use. */
8311 #if ! defined (HAVE_decrement_and_branch_until_zero) \
8312 && defined (HAVE_decrement_and_branch_on_count)
8316 #endif
8318 /* Now do postponed overflow checks on COMPARISON_VAL. */
8321 {
8322 /* Register will always be nonnegative, with value
8323 0 on last iteration */
8327 }
8331 {
8334 }
8335 else
8341 /* If the initial value is not zero, or if the comparison
8342 value is not an exact multiple of the increment, then we
8343 can not reverse this loop. */
8346 {
8349 }
8350 else
8351 {
8354 }
8358 /* Reset these in case we normalized the initial value
8359 and comparison value above. */
8362 {
8364 final_value
8366 }
8369 /* Save some info needed to produce the new insns. */
8374 /* Set start_value; if this is not a CONST_INT, we need
8375 to generate a SUB.
8376 Initialize biv to start_value before loop start.
8377 The old initializing insn will be deleted as a
8378 dead store by flow.c. */
8381 {
8384 }
8386 {
8394 start_value
8400 }
8402 {
8405 initial_value);
8409 start_value
8412 }
8413 else
8414 /* We could handle the other cases too, but it'll be
8415 better to have a testcase first. */
8418 /* We may not have a single insn which can increment a reg, so
8419 create a sequence to hold all the insns from expand_inc. */
8428 /* Update biv info to reflect its new status. */
8433 /* Update loop info. */
8442 /* Inc LABEL_NUSES so that delete_insn will
8443 not delete the label. */
8446 /* Emit an insn after the end of the loop to set the biv's
8447 proper exit value if it is used anywhere outside the loop. */
8453 /* Delete compare/branch at end of loop. */
8458 /* Add new compare/branch insn at end of loop. */
8470 ;
8476 {
8478 {
8479 /* Increment of LABEL_NUSES done above. */
8480 /* Register is now always nonnegative,
8481 so add REG_NONNEG note to the branch. */
8484 }
8486 }
8488 /* No insn may reference both the reversed and another biv or it
8489 will fail (see comment near the top of the loop reversal
8490 code).
8491 Earlier on, we have verified that the biv has no use except
8492 counting, or it is the only biv in this function.
8493 However, the code that computes no_use_except_counting does
8494 not verify reg notes. It's possible to have an insn that
8495 references another biv, and has a REG_EQUAL note with an
8496 expression based on the reversed biv. To avoid this case,
8497 remove all REG_EQUAL notes based on the reversed biv
8498 here. */
8501 {
8504 /* If this is a set of a GIV based on the reversed biv, any
8505 REG_EQUAL notes should still be correct. */
8512 {
8517 else
8519 }
8520 }
8522 /* Mark that this biv has been reversed. Each giv which depends
8523 on this biv, and which is also live past the end of the loop
8524 will have to be fixed up. */
8529 {
8533 else
8535 }
8538 }
8539 }
8540 }
8543 }
8544 \f
8545 /* Verify whether the biv BL appears to be eliminable,
8546 based on the insns in the loop that refer to it.
8548 If ELIMINATE_P is nonzero, actually do the elimination.
8550 THRESHOLD and INSN_COUNT are from loop_optimize and are used to
8551 determine whether invariant insns should be placed inside or at the
8552 start of the loop. */
8554 static int
8557 {
8560 rtx p;
8562 /* Scan all insns in the loop, stopping if we find one that uses the
8563 biv in a way that we cannot eliminate. */
8566 {
8570 rtx note;
8572 /* If this is a libcall that sets a giv, skip ahead to its end. */
8574 {
8578 {
8583 {
8590 }
8591 }
8592 }
8594 /* Closely examine the insn if the biv is mentioned. */
8599 {
8605 }
8607 /* If we are eliminating, kill REG_EQUAL notes mentioning the biv. */
8612 }
8615 {
8620 }
8623 }
8624 \f
8625 /* INSN and REFERENCE are instructions in the same insn chain.
8626 Return nonzero if INSN is first. */
8628 int
8630 {
8634 {
8635 /* Start with test for not first so that INSN == REFERENCE yields not
8636 first. */
8642 /* Either of P or Q might be a NOTE. Notes have the same LUID as the
8643 previous insn, hence the <= comparison below does not work if
8644 P is a note. */
8655 }
8656 }
8658 /* We are trying to eliminate BIV in INSN using GIV. Return nonzero if
8659 the offset that we have to take into account due to auto-increment /
8660 div derivation is zero. */
8661 static int
8664 {
8665 /* If the giv V had the auto-inc address optimization applied
8666 to it, and INSN occurs between the giv insn and the biv
8667 insn, then we'd have to adjust the value used here.
8668 This is rare, so we don't bother to make this possible. */
8677 }
8679 /* If BL appears in X (part of the pattern of INSN), see if we can
8680 eliminate its use. If so, return 1. If not, return 0.
8682 If BIV does not appear in X, return 1.
8684 If ELIMINATE_P is nonzero, actually do the elimination.
8685 WHERE_INSN/WHERE_BB indicate where extra insns should be added.
8686 Depending on how many items have been moved out of the loop, it
8687 will either be before INSN (when WHERE_INSN is nonzero) or at the
8688 start of the loop (when WHERE_INSN is zero). */
8690 static int
8694 {
8700 #ifdef HAVE_cc0
8702 #endif
8708 {
8710 /* If we haven't already been able to do something with this BIV,
8711 we can't eliminate it. */
8717 /* If this sets the BIV, it is not a problem. */
8721 /* If this is an insn that defines a giv, it is also ok because
8722 it will go away when the giv is reduced. */
8727 #ifdef HAVE_cc0
8729 {
8730 /* Can replace with any giv that was reduced and
8731 that has (MULT_VAL != 0) and (ADD_VAL == 0).
8732 Require a constant for MULT_VAL, so we know it's nonzero.
8733 ??? We disable this optimization to avoid potential
8734 overflows. */
8742 {
8749 /* If the giv has the opposite direction of change,
8750 then reverse the comparison. */
8754 else
8757 /* We can probably test that giv's reduced reg. */
8760 }
8762 /* Look for a giv with (MULT_VAL != 0) and (ADD_VAL != 0);
8763 replace test insn with a compare insn (cmp REDUCED_GIV ADD_VAL).
8764 Require a constant for MULT_VAL, so we know it's nonzero.
8765 ??? Do this only if ADD_VAL is a pointer to avoid a potential
8766 overflow problem. */
8778 {
8785 /* If the giv has the opposite direction of change,
8786 then reverse the comparison. */
8790 else
8794 /* Replace biv with the giv's reduced register. */
8799 /* Insn doesn't support that constant or invariant. Copy it
8800 into a register (it will be a loop invariant.) */
8807 /* Substitute the new register for its invariant value in
8808 the compare expression. */
8812 }
8813 }
8814 #endif
8821 /* See if either argument is the biv. */
8826 else
8830 {
8831 /* First try to replace with any giv that has constant positive
8832 mult_val and constant add_val. We might be able to support
8833 negative mult_val, but it seems complex to do it in general. */
8845 {
8849 /* Don't eliminate if the linear combination that makes up
8850 the giv overflows when it is applied to ARG. */
8852 {
8853 rtx add_val;
8857 else
8863 }
8868 /* Replace biv with the giv's reduced reg. */
8871 /* If all constants are actually constant integers and
8872 the derived constant can be directly placed in the COMPARE,
8873 do so. */
8876 {
8879 }
8880 else
8881 {
8882 /* Otherwise, load it into a register. */
8887 }
8893 }
8895 /* Look for giv with positive constant mult_val and nonconst add_val.
8896 Insert insns to calculate new compare value.
8897 ??? Turn this off due to possible overflow. */
8905 {
8906 rtx tem;
8916 /* Replace biv with giv's reduced register. */
8920 /* Compute value to compare against. */
8924 /* Use it in this insn. */
8928 }
8929 }
8931 {
8933 {
8934 /* Look for giv with constant positive mult_val and nonconst
8935 add_val. Insert insns to compute new compare value.
8936 ??? Turn this off due to possible overflow. */
8943 {
8944 rtx tem;
8954 /* Replace biv with giv's reduced register. */
8958 /* Compute value to compare against. */
8965 }
8966 }
8968 /* This code has problems. Basically, you can't know when
8969 seeing if we will eliminate BL, whether a particular giv
8970 of ARG will be reduced. If it isn't going to be reduced,
8971 we can't eliminate BL. We can try forcing it to be reduced,
8972 but that can generate poor code.
8974 The problem is that the benefit of reducing TV, below should
8975 be increased if BL can actually be eliminated, but this means
8976 we might have to do a topological sort of the order in which
8977 we try to process biv. It doesn't seem worthwhile to do
8978 this sort of thing now. */
8980 #if 0
8981 /* Otherwise the reg compared with had better be a biv. */
8986 /* Look for a pair of givs, one for each biv,
8987 with identical coefficients. */
8989 {
9001 {
9008 /* Replace biv with its giv's reduced reg. */
9010 /* Replace other operand with the other giv's
9011 reduced reg. */
9014 }
9015 }
9016 #endif
9017 }
9019 /* If we get here, the biv can't be eliminated. */
9023 /* If this address is a DEST_ADDR giv, it doesn't matter if the
9024 biv is used in it, since it will be replaced. */
9032 }
9034 /* See if any subexpression fails elimination. */
9037 {
9039 {
9052 }
9053 }
9056 }
9057 \f
9058 /* Return nonzero if the last use of REG
9059 is in an insn following INSN in the same basic block. */
9061 static int
9063 {
9064 rtx n;
9068 {
9071 }
9073 }
9074 \f
9075 /* Called via `note_stores' to record the initial value of a biv. Here we
9076 just record the location of the set and process it later. */
9078 static void
9080 {
9091 /* If this is the first set found, record it. */
9093 {
9096 }
9097 }
9098 \f
9099 /* If any of the registers in X are "old" and currently have a last use earlier
9100 than INSN, update them to have a last use of INSN. Their actual last use
9101 will be the previous insn but it will not have a valid uid_luid so we can't
9102 use it. X must be a source expression only. */
9104 static void
9106 {
9107 /* Check for the case where INSN does not have a valid luid. In this case,
9108 there is no need to modify the regno_last_uid, as this can only happen
9109 when code is inserted after the loop_end to set a pseudo's final value,
9110 and hence this insn will never be the last use of x.
9111 ???? This comment is not correct. See for example loop_givs_reduce.
9112 This may insert an insn before another new insn. */
9116 {
9118 }
9119 else
9120 {
9124 {
9130 }
9131 }
9132 }
9133 \f
9134 /* Given an insn INSN and condition COND, return the condition in a
9135 canonical form to simplify testing by callers. Specifically:
9137 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
9138 (2) Both operands will be machine operands; (cc0) will have been replaced.
9139 (3) If an operand is a constant, it will be the second operand.
9140 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
9141 for GE, GEU, and LEU.
9143 If the condition cannot be understood, or is an inequality floating-point
9144 comparison which needs to be reversed, 0 will be returned.
9146 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
9148 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9149 insn used in locating the condition was found. If a replacement test
9150 of the condition is desired, it should be placed in front of that
9151 insn and we will be sure that the inputs are still valid.
9153 If WANT_REG is nonzero, we wish the condition to be relative to that
9154 register, if possible. Therefore, do not canonicalize the condition
9155 further. */
9157 rtx
9159 rtx want_reg)
9160 {
9163 rtx set;
9164 rtx tem;
9182 /* If we are comparing a register with zero, see if the register is set
9183 in the previous insn to a COMPARE or a comparison operation. Perform
9184 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
9185 in cse.c */
9190 {
9191 /* Set nonzero when we find something of interest. */
9194 #ifdef HAVE_cc0
9195 /* If comparison with cc0, import actual comparison from compare
9196 insn. */
9198 {
9209 }
9210 #endif
9212 /* If this is a COMPARE, pick up the two things being compared. */
9214 {
9218 }
9222 /* Go back to the previous insn. Stop if it is not an INSN. We also
9223 stop if it isn't a single set or if it has a REG_INC note because
9224 we don't want to bother dealing with it. */
9238 /* If this is setting OP0, get what it sets it to if it looks
9239 relevant. */
9241 {
9243 #ifdef FLOAT_STORE_FLAG_VALUE
9244 REAL_VALUE_TYPE fsfv;
9245 #endif
9247 /* ??? We may not combine comparisons done in a CCmode with
9248 comparisons not done in a CCmode. This is to aid targets
9249 like Alpha that have an IEEE compliant EQ instruction, and
9250 a non-IEEE compliant BEQ instruction. The use of CCmode is
9251 actually artificial, simply to prevent the combination, but
9252 should not affect other platforms.
9254 However, we must allow VOIDmode comparisons to match either
9255 CCmode or non-CCmode comparison, because some ports have
9256 modeless comparisons inside branch patterns.
9258 ??? This mode check should perhaps look more like the mode check
9259 in simplify_comparison in combine. */
9267 && (STORE_FLAG_VALUE
9270 #ifdef FLOAT_STORE_FLAG_VALUE
9275 #endif
9276 ))
9287 && (STORE_FLAG_VALUE
9290 #ifdef FLOAT_STORE_FLAG_VALUE
9295 #endif
9296 ))
9302 {
9305 }
9306 else
9308 }
9311 /* If this sets OP0, but not directly, we have to give up. */
9315 {
9319 {
9324 }
9329 }
9330 }
9332 /* If constant is first, put it last. */
9336 /* If OP0 is the result of a comparison, we weren't able to find what
9337 was really being compared, so fail. */
9341 /* Canonicalize any ordered comparison with integers involving equality
9342 if we can do computations in the relevant mode and we do not
9343 overflow. */
9348 {
9351 unsigned HOST_WIDE_INT max_val
9355 {
9361 /* When cross-compiling, const_val might be sign-extended from
9362 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
9382 }
9383 }
9385 /* Never return CC0; return zero instead. */
9390 }
9392 /* Given a jump insn JUMP, return the condition that will cause it to branch
9393 to its JUMP_LABEL. If the condition cannot be understood, or is an
9394 inequality floating-point comparison which needs to be reversed, 0 will
9395 be returned.
9397 If EARLIEST is nonzero, it is a pointer to a place where the earliest
9398 insn used in locating the condition was found. If a replacement test
9399 of the condition is desired, it should be placed in front of that
9400 insn and we will be sure that the inputs are still valid. */
9402 rtx
9404 {
9405 rtx cond;
9407 rtx set;
9409 /* If this is not a standard conditional jump, we can't parse it. */
9417 /* If this branches to JUMP_LABEL when the condition is false, reverse
9418 the condition. */
9419 reverse
9424 }
9426 /* Similar to above routine, except that we also put an invariant last
9427 unless both operands are invariants. */
9429 rtx
9431 {
9441 }
9443 /* Scan the function and determine whether it has indirect (computed) jumps.
9445 This is taken mostly from flow.c; similar code exists elsewhere
9446 in the compiler. It may be useful to put this into rtlanal.c. */
9447 static int
9449 {
9450 rtx insn;
9457 }
9459 /* Add MEM to the LOOP_MEMS array, if appropriate. See the
9460 documentation for LOOP_MEMS for the definition of `appropriate'.
9461 This function is called from prescan_loop via for_each_rtx. */
9463 static int
9465 {
9474 {
9479 /* We're not interested in MEMs that are only clobbered. */
9483 /* We're not interested in the MEM associated with a
9484 CONST_DOUBLE, so there's no need to traverse into this. */
9488 /* We're not interested in any MEMs that only appear in notes. */
9492 /* This is not a MEM. */
9494 }
9496 /* See if we've already seen this MEM. */
9499 {
9501 /* The modes of the two memory accesses are different. If
9502 this happens, something tricky is going on, and we just
9503 don't optimize accesses to this MEM. */
9507 }
9509 /* Resize the array, if necessary. */
9511 {
9514 else
9519 }
9521 /* Actually insert the MEM. */
9523 /* We can't hoist this MEM out of the loop if it's a BLKmode MEM
9524 because we can't put it in a register. We still store it in the
9525 table, though, so that if we see the same address later, but in a
9526 non-BLK mode, we'll not think we can optimize it at that point. */
9532 }
9535 /* Allocate REGS->ARRAY or reallocate it if it is too small.
9537 Increment REGS->ARRAY[I].SET_IN_LOOP at the index I of each
9538 register that is modified by an insn between FROM and TO. If the
9539 value of an element of REGS->array[I].SET_IN_LOOP becomes 127 or
9540 more, stop incrementing it, to avoid overflow.
9542 Store in REGS->ARRAY[I].SINGLE_USAGE the single insn in which
9543 register I is used, if it is only used once. Otherwise, it is set
9544 to 0 (for no uses) or const0_rtx for more than one use. This
9545 parameter may be zero, in which case this processing is not done.
9547 Set REGS->ARRAY[I].MAY_NOT_OPTIMIZE nonzero if we should not
9548 optimize register I. */
9550 static void
9552 {
9555 /* last_set[n] is nonzero iff reg n has been set in the current
9556 basic block. In that case, it is the insn that last set reg n. */
9558 rtx insn;
9564 /* Grow the regs array if not allocated or too small. */
9566 {
9571 /* Zero the new elements. */
9574 }
9576 /* Clear previously scanned fields but do not clear n_times_set. */
9578 {
9582 }
9586 /* Scan the loop, recording register usage. */
9589 {
9591 {
9592 /* Record registers that have exactly one use. */
9595 /* Include uses in REG_EQUAL notes. */
9603 {
9607 last_set);
9608 }
9609 }
9614 /* Invalidate all registers used for function argument passing.
9615 We check rtx_varies_p for the same reason as below, to allow
9616 optimizing PIC calculations. */
9618 {
9619 rtx link;
9621 link;
9623 {
9630 }
9631 }
9632 }
9634 /* Invalidate all hard registers clobbered by calls. With one exception:
9635 a call-clobbered PIC register is still function-invariant for our
9636 purposes, since we can hoist any PIC calculations out of the loop.
9637 Thus the call to rtx_varies_p. */
9642 {
9645 }
9647 #ifdef AVOID_CCMODE_COPIES
9648 /* Don't try to move insns which set CC registers if we should not
9649 create CCmode register copies. */
9653 #endif
9655 /* Set regs->array[I].n_times_set for the new registers. */
9660 }
9662 /* Returns the number of real INSNs in the LOOP. */
9664 static int
9666 {
9668 rtx insn;
9676 }
9678 /* Move MEMs into registers for the duration of the loop. */
9680 static void
9682 {
9689 rtx end_label;
9690 /* Nonzero if the next instruction may never be executed. */
9697 /* We cannot use next_label here because it skips over normal insns. */
9702 /* Check to see if it's possible that some instructions in the loop are
9703 never executed. Also check if there is a goto out of the loop other
9704 than right after the end of the loop. */
9708 {
9712 /* If we enter the loop in the middle, and scan
9713 around to the beginning, don't set maybe_never
9714 for that. This must be an unconditional jump,
9715 otherwise the code at the top of the loop might
9716 never be executed. Unconditional jumps are
9717 followed a by barrier then loop end. */
9722 {
9723 /* If this is a jump outside of the loop but not right
9724 after the end of the loop, we would have to emit new fixup
9725 sequences for each such label. */
9727 JUMP_INSN is executed, we must be conservative. */
9736 /* Something complicated. */
9738 else
9739 /* If there are any more instructions in the loop, they
9740 might not be reached. */
9742 }
9745 }
9747 /* Find start of the extended basic block that enters the loop. */
9751 ;
9756 /* Build table of mems that get set to constant values before the
9757 loop. */
9761 /* Actually move the MEMs. */
9763 {
9764 regset_head load_copies;
9765 regset_head store_copies;
9767 rtx reg;
9769 rtx mem_list_entry;
9773 /* There's no telling whether or not MEM is modified. */
9776 /* Go through the MEMs written to in the loop to see if this
9777 one is aliased by one of them. */
9780 {
9785 {
9786 /* MEM is indeed aliased by this store. */
9789 }
9791 }
9797 /* If this MEM is written to, we must be sure that there
9798 are no reads from another MEM that aliases this one. */
9800 {
9804 {
9808 VOIDmode,
9810 rtx_varies_p))
9811 {
9812 /* It's not safe to hoist loop_info->mems[i] out of
9813 the loop because writes to it might not be
9814 seen by reads from loop_info->mems[j]. */
9817 }
9818 }
9819 }
9822 /* We can't access the MEM outside the loop; it might
9823 cause a trap that wouldn't have happened otherwise. */
9827 /* We thought we were going to lift this MEM out of the
9828 loop, but later discovered that we could not. */
9834 /* Allocate a pseudo for this MEM. We set REG_USERVAR_P in
9835 order to keep scan_loop from moving stores to this MEM
9836 out of the loop just because this REG is neither a
9837 user-variable nor used in the loop test. */
9842 /* Now, replace all references to the MEM with the
9843 corresponding pseudos. */
9848 {
9850 {
9851 rtx set;
9855 /* See if this copies the mem into a register that isn't
9856 modified afterwards. We'll try to do copy propagation
9857 a little further on. */
9859 /* @@@ This test is _way_ too conservative. */
9860 && ! maybe_never
9868 /* See if this copies the mem from a register that isn't
9869 modified afterwards. We'll try to remove the
9870 redundant copy later on by doing a little register
9871 renaming and copy propagation. This will help
9872 to untangle things for the BIV detection code. */
9874 && ! maybe_never
9882 /* If this is a call which uses / clobbers this memory
9883 location, we must not change the interface here. */
9887 {
9891 }
9892 else
9893 /* Replace the memory reference with the shadow register. */
9896 }
9901 }
9906 /* We couldn't replace all occurrences of the MEM. */
9908 else
9909 {
9910 /* Load the memory immediately before LOOP->START, which is
9911 the NOTE_LOOP_BEG. */
9913 rtx set;
9919 {
9923 {
9927 /* Extending hard register lifetimes causes crash
9928 on SRC targets. Doing so on non-SRC is
9929 probably also not good idea, since we most
9930 probably have pseudoregister equivalence as
9931 well. */
9934 }
9935 /* Use the constant equivalence if that is cheap enough. */
9941 {
9944 }
9946 /* If best_equiv is nonzero, we know that MEM is set to a
9947 constant or register before the loop. We will use this
9948 knowledge to initialize the shadow register with that
9949 constant or reg rather than by loading from MEM. */
9952 }
9957 {
9960 {
9963 }
9964 }
9970 {
9972 {
9975 }
9977 /* Store the memory immediately after END, which is
9978 the NOTE_LOOP_END. */
9981 }
9984 {
9989 }
9991 /* Attempt a bit of copy propagation. This helps untangle the
9992 data flow, and enables {basic,general}_induction_var to find
9993 more bivs/givs. */
9994 EXECUTE_IF_SET_IN_REG_SET
9996 {
9998 });
10001 EXECUTE_IF_SET_IN_REG_SET
10003 {
10005 });
10007 }
10008 }
10011 {
10012 /* Now, we need to replace all references to the previous exit
10013 label with the new one. */
10014 replace_label_data rr;
10020 {
10022 }
10023 }
10026 }
10028 /* For communication between note_reg_stored and its caller. */
10029 struct note_reg_stored_arg
10030 {
10032 rtx reg;
10033 };
10035 /* Called via note_stores, record in SET_SEEN whether X, which is written,
10036 is equal to ARG. */
10037 static void
10039 {
10043 }
10045 /* Try to replace every occurrence of pseudo REGNO with REPLACEMENT.
10046 There must be exactly one insn that sets this pseudo; it will be
10047 deleted if all replacements succeed and we can prove that the register
10048 is not used after the loop. */
10050 static void
10052 {
10053 /* This is the reg that we are copying from. */
10056 rtx insn;
10057 /* These help keep track of whether we replaced all uses of the reg. */
10064 {
10065 rtx set;
10067 /* Only substitute within one extended basic block from the initializing
10068 insn. */
10075 /* Is this the initializing insn? */
10080 {
10087 }
10089 /* Only substitute after seeing the initializing insn. */
10091 {
10098 /* Stop replacing when REPLACEMENT is modified. */
10103 {
10106 /* It is possible that we've turned previously valid REG_EQUAL to
10107 invalid, as we change the REGNO to REPLACEMENT and unlike REGNO,
10108 REPLACEMENT is modified, we get different meaning. */
10112 }
10113 }
10114 }
10118 {
10122 {
10123 rtx first;
10124 rtx retval_note;
10126 /* Assume we're just deleting INIT_INSN. */
10128 /* Look for REG_RETVAL note. If we're deleting the end of
10129 the libcall sequence, the whole sequence can go. */
10131 /* If we found a REG_RETVAL note, find the first instruction
10132 in the sequence. */
10136 /* Delete the instructions. */
10138 }
10141 }
10142 }
10144 /* Replace all the instructions from FIRST up to and including LAST
10145 with NOTE_INSN_DELETED notes. */
10147 static void
10149 {
10151 {
10157 /* If this was the LAST instructions we're supposed to delete,
10158 we're done. */
10163 }
10164 }
10166 /* Try to replace occurrences of pseudo REGNO with REPLACEMENT within
10167 loop LOOP if the order of the sets of these registers can be
10168 swapped. There must be exactly one insn within the loop that sets
10169 this pseudo followed immediately by a move insn that sets
10170 REPLACEMENT with REGNO. */
10171 static void
10174 {
10175 rtx insn;
10184 {
10185 /* Search for the insn that copies REGNO to NEW_REGNO? */
10193 }
10196 {
10197 rtx prev_insn;
10198 rtx prev_set;
10200 /* Some DEF-USE info would come in handy here to make this
10201 function more general. For now, just check the previous insn
10202 which is the most likely candidate for setting REGNO. */
10210 {
10211 /* We have:
10212 (set (reg regno) (expr))
10213 (set (reg new_regno) (reg regno))
10215 so try converting this to:
10216 (set (reg new_regno) (expr))
10217 (set (reg regno) (reg new_regno))
10219 The former construct is often generated when a global
10220 variable used for an induction variable is shadowed by a
10221 register (NEW_REGNO). The latter construct improves the
10222 chances of GIV replacement and BIV elimination. */
10232 {
10239 /* Update first use of REGNO. */
10243 /* Now perform copy propagation to hopefully
10244 remove all uses of REGNO within the loop. */
10246 }
10247 }
10248 }
10249 }
10251 /* Worker function for find_mem_in_note, called via for_each_rtx. */
10253 static int
10255 {
10257 {
10261 }
10263 }
10265 /* Returns the first MEM found in NOTE by depth-first search. */
10267 static rtx
10269 {
10273 }
10275 /* Replace MEM with its associated pseudo register. This function is
10276 called from load_mems via for_each_rtx. DATA is actually a pointer
10277 to a structure describing the instruction currently being scanned
10278 and the MEM we are currently replacing. */
10280 static int
10282 {
10290 {
10295 /* We're not interested in the MEM associated with a
10296 CONST_DOUBLE, so there's no need to traverse into one. */
10300 /* This is not a MEM. */
10302 }
10305 /* This is not the MEM we are currently replacing. */
10308 /* Actually replace the MEM. */
10312 }
10314 static void
10316 {
10317 loop_replace_args args;
10325 /* If we hoist a mem write out of the loop, then REG_EQUAL
10326 notes referring to the mem are no longer valid. */
10328 {
10333 {
10337 {
10338 /* Remove the note. */
10341 }
10342 }
10343 }
10344 }
10346 /* Replace one register with another. Called through for_each_rtx; PX points
10347 to the rtx being scanned. DATA is actually a pointer to
10348 a structure of arguments. */
10350 static int
10352 {
10363 }
10365 static void
10367 {
10368 loop_replace_args args;
10375 }
10376 \f
10377 /* Emit insn for PATTERN after WHERE_INSN in basic block WHERE_BB
10378 (ignored in the interim). */
10380 static rtx
10383 rtx pattern)
10384 {
10386 }
10389 /* If WHERE_INSN is nonzero emit insn for PATTERN before WHERE_INSN
10390 in basic block WHERE_BB (ignored in the interim) within the loop
10391 otherwise hoist PATTERN into the loop pre-header. */
10393 rtx
10395 basic_block where_bb ATTRIBUTE_UNUSED,
10397 {
10401 }
10404 /* Emit call insn for PATTERN before WHERE_INSN in basic block
10405 WHERE_BB (ignored in the interim) within the loop. */
10407 static rtx
10409 basic_block where_bb ATTRIBUTE_UNUSED,
10411 {
10413 }
10416 /* Hoist insn for PATTERN into the loop pre-header. */
10418 rtx
10420 {
10422 }
10425 /* Hoist call insn for PATTERN into the loop pre-header. */
10427 static rtx
10429 {
10431 }
10434 /* Sink insn for PATTERN after the loop end. */
10436 rtx
10438 {
10440 }
10442 /* bl->final_value can be either general_operand or PLUS of general_operand
10443 and constant. Emit sequence of instructions to load it into REG. */
10444 static rtx
10446 {
10447 rtx seq;
10455 }
10457 /* If the loop has multiple exits, emit insn for PATTERN before the
10458 loop to ensure that it will always be executed no matter how the
10459 loop exits. Otherwise, emit the insn for PATTERN after the loop,
10460 since this is slightly more efficient. */
10462 static rtx
10464 {
10467 else
10469 }
10470 \f
10471 static void
10473 {
10481 iv_num++;
10486 {
10489 }
10490 }
10493 static void
10496 {
10498 rtx incr;
10509 {
10512 }
10514 {
10517 }
10521 {
10525 }
10528 {
10532 }
10534 /* List the increments. */
10536 {
10540 }
10542 /* List the givs. */
10544 {
10549 else
10552 }
10553 }
10556 static void
10558 {
10569 {
10573 }
10576 }
10579 static void
10581 {
10588 else
10604 {
10606 {
10618 }
10619 }
10630 {
10634 }
10637 }
10640 void
10642 {
10644 }
10647 void
10649 {
10651 }
10654 void
10656 {
10658 }
10661 void
10663 {
10665 }
10668 #define LOOP_BLOCK_NUM_1(INSN) \
10669 ((INSN) ? (BLOCK_FOR_INSN (INSN) ? BLOCK_NUM (INSN) : - 1) : -1)
10671 /* The notes do not have an assigned block, so look at the next insn. */
10672 #define LOOP_BLOCK_NUM(INSN) \
10673 ((INSN) ? (GET_CODE (INSN) == NOTE \
10674 ? LOOP_BLOCK_NUM_1 (next_nonnote_insn (INSN)) \
10675 : LOOP_BLOCK_NUM_1 (INSN)) \
10676 : -1)
10678 #define LOOP_INSN_UID(INSN) ((INSN) ? INSN_UID (INSN) : -1)
10680 static void
10683 {
10684 rtx label;
10689 /* Print diagnostics to compare our concept of a loop with
10690 what the loop notes say. */
10705 {
10725 {
10728 {
10731 }
10732 }
10735 /* This can happen when a marked loop appears as two nested loops,
10736 say from while (a || b) {}. The inner loop won't match
10737 the loop markers but the outer one will. */
10740 }
10741 }
10743 /* Call this function from the debugger to dump LOOP. */
10745 void
10747 {
10749 }
10751 /* Call this function from the debugger to dump LOOPS. */
10753 void
10755 {
10757 }