1 /* Subroutines for insn-output.c for Matsushita MN10300 series
2 Copyright (C) 1996-2014 Free Software Foundation, Inc.
3 Contributed by Jeff Law (law@cygnus.com).
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "stor-layout.h"
31 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
40 #include "insn-codes.h"
49 #include "diagnostic-core.h"
51 #include "tm-constrs.h"
53 #include "target-def.h"
54 #include "dominance.h"
60 #include "cfgcleanup.h"
62 #include "basic-block.h"
69 /* This is used in the am33_2.0-linux-gnu port, in which global symbol
70 names are not prefixed by underscores, to tell whether to prefix a
71 label with a plus sign or not, so that the assembler can tell
72 symbol names from register names. */
73 int mn10300_protect_label
;
75 /* Selected processor type for tuning. */
76 enum processor_type mn10300_tune_cpu
= PROCESSOR_DEFAULT
;
83 static int cc_flags_for_mode(machine_mode
);
84 static int cc_flags_for_code(enum rtx_code
);
86 /* Implement TARGET_OPTION_OVERRIDE. */
88 mn10300_option_override (void)
91 target_flags
&= ~MASK_MULT_BUG
;
94 /* Disable scheduling for the MN10300 as we do
95 not have timing information available for it. */
96 flag_schedule_insns
= 0;
97 flag_schedule_insns_after_reload
= 0;
99 /* Force enable splitting of wide types, as otherwise it is trivial
100 to run out of registers. Indeed, this works so well that register
101 allocation problems are now more common *without* optimization,
102 when this flag is not enabled by default. */
103 flag_split_wide_types
= 1;
106 if (mn10300_tune_string
)
108 if (strcasecmp (mn10300_tune_string
, "mn10300") == 0)
109 mn10300_tune_cpu
= PROCESSOR_MN10300
;
110 else if (strcasecmp (mn10300_tune_string
, "am33") == 0)
111 mn10300_tune_cpu
= PROCESSOR_AM33
;
112 else if (strcasecmp (mn10300_tune_string
, "am33-2") == 0)
113 mn10300_tune_cpu
= PROCESSOR_AM33_2
;
114 else if (strcasecmp (mn10300_tune_string
, "am34") == 0)
115 mn10300_tune_cpu
= PROCESSOR_AM34
;
117 error ("-mtune= expects mn10300, am33, am33-2, or am34");
122 mn10300_file_start (void)
124 default_file_start ();
127 fprintf (asm_out_file
, "\t.am33_2\n");
128 else if (TARGET_AM33
)
129 fprintf (asm_out_file
, "\t.am33\n");
132 /* Note: This list must match the liw_op attribute in mn10300.md. */
134 static const char *liw_op_names
[] =
136 "add", "cmp", "sub", "mov",
142 /* Print operand X using operand code CODE to assembly language output file
146 mn10300_print_operand (FILE *file
, rtx x
, int code
)
152 unsigned int liw_op
= UINTVAL (x
);
154 gcc_assert (TARGET_ALLOW_LIW
);
155 gcc_assert (liw_op
< LIW_OP_MAX
);
156 fputs (liw_op_names
[liw_op
], file
);
163 enum rtx_code cmp
= GET_CODE (x
);
164 machine_mode mode
= GET_MODE (XEXP (x
, 0));
169 cmp
= reverse_condition (cmp
);
170 have_flags
= cc_flags_for_mode (mode
);
181 /* bge is smaller than bnc. */
182 str
= (have_flags
& CC_FLAG_V
? "ge" : "nc");
185 str
= (have_flags
& CC_FLAG_V
? "lt" : "ns");
233 gcc_checking_assert ((cc_flags_for_code (cmp
) & ~have_flags
) == 0);
239 /* This is used for the operand to a call instruction;
240 if it's a REG, enclose it in parens, else output
241 the operand normally. */
245 mn10300_print_operand (file
, x
, 0);
249 mn10300_print_operand (file
, x
, 0);
253 switch (GET_CODE (x
))
257 output_address (XEXP (x
, 0));
262 fprintf (file
, "fd%d", REGNO (x
) - 18);
270 /* These are the least significant word in a 64bit value. */
272 switch (GET_CODE (x
))
276 output_address (XEXP (x
, 0));
281 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
285 fprintf (file
, "%s", reg_names
[subreg_regno (x
)]);
293 switch (GET_MODE (x
))
296 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
297 REAL_VALUE_TO_TARGET_DOUBLE (rv
, val
);
298 fprintf (file
, "0x%lx", val
[0]);
301 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
302 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
[0]);
303 fprintf (file
, "0x%lx", val
[0]);
307 mn10300_print_operand_address (file
,
308 GEN_INT (CONST_DOUBLE_LOW (x
)));
319 split_double (x
, &low
, &high
);
320 fprintf (file
, "%ld", (long)INTVAL (low
));
329 /* Similarly, but for the most significant word. */
331 switch (GET_CODE (x
))
335 x
= adjust_address (x
, SImode
, 4);
336 output_address (XEXP (x
, 0));
341 fprintf (file
, "%s", reg_names
[REGNO (x
) + 1]);
345 fprintf (file
, "%s", reg_names
[subreg_regno (x
) + 1]);
353 switch (GET_MODE (x
))
356 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
357 REAL_VALUE_TO_TARGET_DOUBLE (rv
, val
);
358 fprintf (file
, "0x%lx", val
[1]);
364 mn10300_print_operand_address (file
,
365 GEN_INT (CONST_DOUBLE_HIGH (x
)));
376 split_double (x
, &low
, &high
);
377 fprintf (file
, "%ld", (long)INTVAL (high
));
388 if (REG_P (XEXP (x
, 0)))
389 output_address (gen_rtx_PLUS (SImode
, XEXP (x
, 0), const0_rtx
));
391 output_address (XEXP (x
, 0));
396 gcc_assert (INTVAL (x
) >= -128 && INTVAL (x
) <= 255);
397 fprintf (file
, "%d", (int)((~INTVAL (x
)) & 0xff));
401 gcc_assert (INTVAL (x
) >= -128 && INTVAL (x
) <= 255);
402 fprintf (file
, "%d", (int)(INTVAL (x
) & 0xff));
405 /* For shift counts. The hardware ignores the upper bits of
406 any immediate, but the assembler will flag an out of range
407 shift count as an error. So we mask off the high bits
408 of the immediate here. */
412 fprintf (file
, "%d", (int)(INTVAL (x
) & 0x1f));
418 switch (GET_CODE (x
))
422 output_address (XEXP (x
, 0));
431 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
435 fprintf (file
, "%s", reg_names
[subreg_regno (x
)]);
438 /* This will only be single precision.... */
444 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
445 REAL_VALUE_TO_TARGET_SINGLE (rv
, val
);
446 fprintf (file
, "0x%lx", val
);
456 mn10300_print_operand_address (file
, x
);
465 /* Output assembly language output for the address ADDR to FILE. */
468 mn10300_print_operand_address (FILE *file
, rtx addr
)
470 switch (GET_CODE (addr
))
473 mn10300_print_operand (file
, XEXP (addr
, 0), 0);
478 mn10300_print_operand (file
, XEXP (addr
, 0), 0);
481 mn10300_print_operand (file
, XEXP (addr
, 1), 0);
485 mn10300_print_operand (file
, addr
, 0);
489 rtx base
= XEXP (addr
, 0);
490 rtx index
= XEXP (addr
, 1);
492 if (REG_P (index
) && !REG_OK_FOR_INDEX_P (index
))
498 gcc_assert (REG_P (index
) && REG_OK_FOR_INDEX_P (index
));
500 gcc_assert (REG_OK_FOR_BASE_P (base
));
502 mn10300_print_operand (file
, index
, 0);
504 mn10300_print_operand (file
, base
, 0);
508 output_addr_const (file
, addr
);
511 output_addr_const (file
, addr
);
516 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA.
518 Used for PIC-specific UNSPECs. */
521 mn10300_asm_output_addr_const_extra (FILE *file
, rtx x
)
523 if (GET_CODE (x
) == UNSPEC
)
528 /* GLOBAL_OFFSET_TABLE or local symbols, no suffix. */
529 output_addr_const (file
, XVECEXP (x
, 0, 0));
532 output_addr_const (file
, XVECEXP (x
, 0, 0));
533 fputs ("@GOT", file
);
536 output_addr_const (file
, XVECEXP (x
, 0, 0));
537 fputs ("@GOTOFF", file
);
540 output_addr_const (file
, XVECEXP (x
, 0, 0));
541 fputs ("@PLT", file
);
543 case UNSPEC_GOTSYM_OFF
:
544 assemble_name (file
, GOT_SYMBOL_NAME
);
546 output_addr_const (file
, XVECEXP (x
, 0, 0));
558 /* Count the number of FP registers that have to be saved. */
560 fp_regs_to_save (void)
567 for (i
= FIRST_FP_REGNUM
; i
<= LAST_FP_REGNUM
; ++i
)
568 if (df_regs_ever_live_p (i
) && ! call_really_used_regs
[i
])
574 /* Print a set of registers in the format required by "movm" and "ret".
575 Register K is saved if bit K of MASK is set. The data and address
576 registers can be stored individually, but the extended registers cannot.
577 We assume that the mask already takes that into account. For instance,
578 bits 14 to 17 must have the same value. */
581 mn10300_print_reg_list (FILE *file
, int mask
)
589 for (i
= 0; i
< FIRST_EXTENDED_REGNUM
; i
++)
590 if ((mask
& (1 << i
)) != 0)
594 fputs (reg_names
[i
], file
);
598 if ((mask
& 0x3c000) != 0)
600 gcc_assert ((mask
& 0x3c000) == 0x3c000);
603 fputs ("exreg1", file
);
610 /* If the MDR register is never clobbered, we can use the RETF instruction
611 which takes the address from the MDR register. This is 3 cycles faster
612 than having to load the address from the stack. */
615 mn10300_can_use_retf_insn (void)
617 /* Don't bother if we're not optimizing. In this case we won't
618 have proper access to df_regs_ever_live_p. */
622 /* EH returns alter the saved return address; MDR is not current. */
623 if (crtl
->calls_eh_return
)
626 /* Obviously not if MDR is ever clobbered. */
627 if (df_regs_ever_live_p (MDR_REG
))
630 /* ??? Careful not to use this during expand_epilogue etc. */
631 gcc_assert (!in_sequence_p ());
632 return leaf_function_p ();
636 mn10300_can_use_rets_insn (void)
638 return !mn10300_initial_offset (ARG_POINTER_REGNUM
, STACK_POINTER_REGNUM
);
641 /* Returns the set of live, callee-saved registers as a bitmask. The
642 callee-saved extended registers cannot be stored individually, so
643 all of them will be included in the mask if any one of them is used.
644 Also returns the number of bytes in the registers in the mask if
645 BYTES_SAVED is not NULL. */
648 mn10300_get_live_callee_saved_regs (unsigned int * bytes_saved
)
655 for (i
= 0; i
<= LAST_EXTENDED_REGNUM
; i
++)
656 if (df_regs_ever_live_p (i
) && ! call_really_used_regs
[i
])
662 if ((mask
& 0x3c000) != 0)
664 for (i
= 0x04000; i
< 0x40000; i
<<= 1)
672 * bytes_saved
= count
* UNITS_PER_WORD
;
680 RTX_FRAME_RELATED_P (r
) = 1;
684 /* Generate an instruction that pushes several registers onto the stack.
685 Register K will be saved if bit K in MASK is set. The function does
686 nothing if MASK is zero.
688 To be compatible with the "movm" instruction, the lowest-numbered
689 register must be stored in the lowest slot. If MASK is the set
690 { R1,...,RN }, where R1...RN are ordered least first, the generated
691 instruction will have the form:
694 (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4)))
695 (set (mem:SI (plus:SI (reg:SI 9)
699 (set (mem:SI (plus:SI (reg:SI 9)
704 mn10300_gen_multiple_store (unsigned int mask
)
706 /* The order in which registers are stored, from SP-4 through SP-N*4. */
707 static const unsigned int store_order
[8] = {
708 /* e2, e3: never saved */
709 FIRST_EXTENDED_REGNUM
+ 4,
710 FIRST_EXTENDED_REGNUM
+ 5,
711 FIRST_EXTENDED_REGNUM
+ 6,
712 FIRST_EXTENDED_REGNUM
+ 7,
713 /* e0, e1, mdrq, mcrh, mcrl, mcvf: never saved. */
714 FIRST_DATA_REGNUM
+ 2,
715 FIRST_DATA_REGNUM
+ 3,
716 FIRST_ADDRESS_REGNUM
+ 2,
717 FIRST_ADDRESS_REGNUM
+ 3,
718 /* d0, d1, a0, a1, mdr, lir, lar: never saved. */
728 for (i
= count
= 0; i
< ARRAY_SIZE(store_order
); ++i
)
730 unsigned regno
= store_order
[i
];
732 if (((mask
>> regno
) & 1) == 0)
736 x
= plus_constant (Pmode
, stack_pointer_rtx
, count
* -4);
737 x
= gen_frame_mem (SImode
, x
);
738 x
= gen_rtx_SET (VOIDmode
, x
, gen_rtx_REG (SImode
, regno
));
741 /* Remove the register from the mask so that... */
742 mask
&= ~(1u << regno
);
745 /* ... we can make sure that we didn't try to use a register
746 not listed in the store order. */
747 gcc_assert (mask
== 0);
749 /* Create the instruction that updates the stack pointer. */
750 x
= plus_constant (Pmode
, stack_pointer_rtx
, count
* -4);
751 x
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
, x
);
754 /* We need one PARALLEL element to update the stack pointer and
755 an additional element for each register that is stored. */
756 x
= gen_rtx_PARALLEL (VOIDmode
, gen_rtvec_v (count
+ 1, elts
));
760 static inline unsigned int
761 popcount (unsigned int mask
)
763 unsigned int count
= 0;
768 mask
&= ~ (mask
& - mask
);
774 mn10300_expand_prologue (void)
776 HOST_WIDE_INT size
= mn10300_frame_size ();
779 mask
= mn10300_get_live_callee_saved_regs (NULL
);
780 /* If we use any of the callee-saved registers, save them now. */
781 mn10300_gen_multiple_store (mask
);
783 if (flag_stack_usage_info
)
784 current_function_static_stack_size
= size
+ popcount (mask
) * 4;
786 if (TARGET_AM33_2
&& fp_regs_to_save ())
788 int num_regs_to_save
= fp_regs_to_save (), i
;
794 save_sp_partial_merge
,
798 unsigned int strategy_size
= (unsigned)-1, this_strategy_size
;
801 if (flag_stack_usage_info
)
802 current_function_static_stack_size
+= num_regs_to_save
* 4;
804 /* We have several different strategies to save FP registers.
805 We can store them using SP offsets, which is beneficial if
806 there are just a few registers to save, or we can use `a0' in
807 post-increment mode (`a0' is the only call-clobbered address
808 register that is never used to pass information to a
809 function). Furthermore, if we don't need a frame pointer, we
810 can merge the two SP adds into a single one, but this isn't
811 always beneficial; sometimes we can just split the two adds
812 so that we don't exceed a 16-bit constant size. The code
813 below will select which strategy to use, so as to generate
814 smallest code. Ties are broken in favor or shorter sequences
815 (in terms of number of instructions). */
817 #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
818 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2)
819 #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
820 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3)
822 /* We add 0 * (S) in two places to promote to the type of S,
823 so that all arms of the conditional have the same type. */
824 #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \
825 (((S) >= (L)) ? 0 * (S) + (SIZE1) * (N) \
826 : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \
827 + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \
829 #define SIZE_FMOV_SP_(S,N) \
830 (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \
831 SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \
832 (S) ? 4 * (N) : 3 + 4 * ((N) - 1))))
833 #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N)))
835 /* Consider alternative save_sp_merge only if we don't need the
836 frame pointer and size is nonzero. */
837 if (! frame_pointer_needed
&& size
)
839 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
840 this_strategy_size
= SIZE_ADD_SP (-(size
+ 4 * num_regs_to_save
));
841 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
842 this_strategy_size
+= SIZE_FMOV_SP (size
, num_regs_to_save
);
844 if (this_strategy_size
< strategy_size
)
846 strategy
= save_sp_merge
;
847 strategy_size
= this_strategy_size
;
851 /* Consider alternative save_sp_no_merge unconditionally. */
852 /* Insn: add -4 * num_regs_to_save, sp. */
853 this_strategy_size
= SIZE_ADD_SP (-4 * num_regs_to_save
);
854 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
855 this_strategy_size
+= SIZE_FMOV_SP (0, num_regs_to_save
);
858 /* Insn: add -size, sp. */
859 this_strategy_size
+= SIZE_ADD_SP (-size
);
862 if (this_strategy_size
< strategy_size
)
864 strategy
= save_sp_no_merge
;
865 strategy_size
= this_strategy_size
;
868 /* Consider alternative save_sp_partial_merge only if we don't
869 need a frame pointer and size is reasonably large. */
870 if (! frame_pointer_needed
&& size
+ 4 * num_regs_to_save
> 128)
872 /* Insn: add -128, sp. */
873 this_strategy_size
= SIZE_ADD_SP (-128);
874 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
875 this_strategy_size
+= SIZE_FMOV_SP (128 - 4 * num_regs_to_save
,
879 /* Insn: add 128-size, sp. */
880 this_strategy_size
+= SIZE_ADD_SP (128 - size
);
883 if (this_strategy_size
< strategy_size
)
885 strategy
= save_sp_partial_merge
;
886 strategy_size
= this_strategy_size
;
890 /* Consider alternative save_a0_merge only if we don't need a
891 frame pointer, size is nonzero and the user hasn't
892 changed the calling conventions of a0. */
893 if (! frame_pointer_needed
&& size
894 && call_really_used_regs
[FIRST_ADDRESS_REGNUM
]
895 && ! fixed_regs
[FIRST_ADDRESS_REGNUM
])
897 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
898 this_strategy_size
= SIZE_ADD_SP (-(size
+ 4 * num_regs_to_save
));
899 /* Insn: mov sp, a0. */
900 this_strategy_size
++;
903 /* Insn: add size, a0. */
904 this_strategy_size
+= SIZE_ADD_AX (size
);
906 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
907 this_strategy_size
+= 3 * num_regs_to_save
;
909 if (this_strategy_size
< strategy_size
)
911 strategy
= save_a0_merge
;
912 strategy_size
= this_strategy_size
;
916 /* Consider alternative save_a0_no_merge if the user hasn't
917 changed the calling conventions of a0. */
918 if (call_really_used_regs
[FIRST_ADDRESS_REGNUM
]
919 && ! fixed_regs
[FIRST_ADDRESS_REGNUM
])
921 /* Insn: add -4 * num_regs_to_save, sp. */
922 this_strategy_size
= SIZE_ADD_SP (-4 * num_regs_to_save
);
923 /* Insn: mov sp, a0. */
924 this_strategy_size
++;
925 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
926 this_strategy_size
+= 3 * num_regs_to_save
;
929 /* Insn: add -size, sp. */
930 this_strategy_size
+= SIZE_ADD_SP (-size
);
933 if (this_strategy_size
< strategy_size
)
935 strategy
= save_a0_no_merge
;
936 strategy_size
= this_strategy_size
;
940 /* Emit the initial SP add, common to all strategies. */
943 case save_sp_no_merge
:
944 case save_a0_no_merge
:
945 F (emit_insn (gen_addsi3 (stack_pointer_rtx
,
947 GEN_INT (-4 * num_regs_to_save
))));
951 case save_sp_partial_merge
:
952 F (emit_insn (gen_addsi3 (stack_pointer_rtx
,
955 xsize
= 128 - 4 * num_regs_to_save
;
961 F (emit_insn (gen_addsi3 (stack_pointer_rtx
,
963 GEN_INT (-(size
+ 4 * num_regs_to_save
)))));
964 /* We'll have to adjust FP register saves according to the
967 /* Since we've already created the stack frame, don't do it
968 again at the end of the function. */
976 /* Now prepare register a0, if we have decided to use it. */
980 case save_sp_no_merge
:
981 case save_sp_partial_merge
:
986 case save_a0_no_merge
:
987 reg
= gen_rtx_REG (SImode
, FIRST_ADDRESS_REGNUM
);
988 F (emit_insn (gen_movsi (reg
, stack_pointer_rtx
)));
990 F (emit_insn (gen_addsi3 (reg
, reg
, GEN_INT (xsize
))));
991 reg
= gen_rtx_POST_INC (SImode
, reg
);
998 /* Now actually save the FP registers. */
999 for (i
= FIRST_FP_REGNUM
; i
<= LAST_FP_REGNUM
; ++i
)
1000 if (df_regs_ever_live_p (i
) && ! call_really_used_regs
[i
])
1008 /* If we aren't using `a0', use an SP offset. */
1011 addr
= gen_rtx_PLUS (SImode
,
1016 addr
= stack_pointer_rtx
;
1021 F (emit_insn (gen_movsf (gen_rtx_MEM (SFmode
, addr
),
1022 gen_rtx_REG (SFmode
, i
))));
1026 /* Now put the frame pointer into the frame pointer register. */
1027 if (frame_pointer_needed
)
1028 F (emit_move_insn (frame_pointer_rtx
, stack_pointer_rtx
));
1030 /* Allocate stack for this frame. */
1032 F (emit_insn (gen_addsi3 (stack_pointer_rtx
,
1036 if (flag_pic
&& df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM
))
1037 emit_insn (gen_load_pic ());
1041 mn10300_expand_epilogue (void)
1043 HOST_WIDE_INT size
= mn10300_frame_size ();
1044 unsigned int reg_save_bytes
;
1046 mn10300_get_live_callee_saved_regs (& reg_save_bytes
);
1048 if (TARGET_AM33_2
&& fp_regs_to_save ())
1050 int num_regs_to_save
= fp_regs_to_save (), i
;
1053 /* We have several options to restore FP registers. We could
1054 load them from SP offsets, but, if there are enough FP
1055 registers to restore, we win if we use a post-increment
1058 /* If we have a frame pointer, it's the best option, because we
1059 already know it has the value we want. */
1060 if (frame_pointer_needed
)
1061 reg
= gen_rtx_REG (SImode
, FRAME_POINTER_REGNUM
);
1062 /* Otherwise, we may use `a1', since it's call-clobbered and
1063 it's never used for return values. But only do so if it's
1064 smaller than using SP offsets. */
1067 enum { restore_sp_post_adjust
,
1068 restore_sp_pre_adjust
,
1069 restore_sp_partial_adjust
,
1070 restore_a1
} strategy
;
1071 unsigned int this_strategy_size
, strategy_size
= (unsigned)-1;
1073 /* Consider using sp offsets before adjusting sp. */
1074 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
1075 this_strategy_size
= SIZE_FMOV_SP (size
, num_regs_to_save
);
1076 /* If size is too large, we'll have to adjust SP with an
1078 if (size
+ 4 * num_regs_to_save
+ reg_save_bytes
> 255)
1080 /* Insn: add size + 4 * num_regs_to_save, sp. */
1081 this_strategy_size
+= SIZE_ADD_SP (size
+ 4 * num_regs_to_save
);
1083 /* If we don't have to restore any non-FP registers,
1084 we'll be able to save one byte by using rets. */
1085 if (! reg_save_bytes
)
1086 this_strategy_size
--;
1088 if (this_strategy_size
< strategy_size
)
1090 strategy
= restore_sp_post_adjust
;
1091 strategy_size
= this_strategy_size
;
1094 /* Consider using sp offsets after adjusting sp. */
1095 /* Insn: add size, sp. */
1096 this_strategy_size
= SIZE_ADD_SP (size
);
1097 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
1098 this_strategy_size
+= SIZE_FMOV_SP (0, num_regs_to_save
);
1099 /* We're going to use ret to release the FP registers
1100 save area, so, no savings. */
1102 if (this_strategy_size
< strategy_size
)
1104 strategy
= restore_sp_pre_adjust
;
1105 strategy_size
= this_strategy_size
;
1108 /* Consider using sp offsets after partially adjusting sp.
1109 When size is close to 32Kb, we may be able to adjust SP
1110 with an imm16 add instruction while still using fmov
1112 if (size
+ 4 * num_regs_to_save
+ reg_save_bytes
> 255)
1114 /* Insn: add size + 4 * num_regs_to_save
1115 + reg_save_bytes - 252,sp. */
1116 this_strategy_size
= SIZE_ADD_SP (size
+ 4 * num_regs_to_save
1117 + (int) reg_save_bytes
- 252);
1118 /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */
1119 this_strategy_size
+= SIZE_FMOV_SP (252 - reg_save_bytes
1120 - 4 * num_regs_to_save
,
1122 /* We're going to use ret to release the FP registers
1123 save area, so, no savings. */
1125 if (this_strategy_size
< strategy_size
)
1127 strategy
= restore_sp_partial_adjust
;
1128 strategy_size
= this_strategy_size
;
1132 /* Consider using a1 in post-increment mode, as long as the
1133 user hasn't changed the calling conventions of a1. */
1134 if (call_really_used_regs
[FIRST_ADDRESS_REGNUM
+ 1]
1135 && ! fixed_regs
[FIRST_ADDRESS_REGNUM
+1])
1137 /* Insn: mov sp,a1. */
1138 this_strategy_size
= 1;
1141 /* Insn: add size,a1. */
1142 this_strategy_size
+= SIZE_ADD_AX (size
);
1144 /* Insn: fmov (a1+),fs#, for each fs# to be restored. */
1145 this_strategy_size
+= 3 * num_regs_to_save
;
1146 /* If size is large enough, we may be able to save a
1148 if (size
+ 4 * num_regs_to_save
+ reg_save_bytes
> 255)
1150 /* Insn: mov a1,sp. */
1151 this_strategy_size
+= 2;
1153 /* If we don't have to restore any non-FP registers,
1154 we'll be able to save one byte by using rets. */
1155 if (! reg_save_bytes
)
1156 this_strategy_size
--;
1158 if (this_strategy_size
< strategy_size
)
1160 strategy
= restore_a1
;
1161 strategy_size
= this_strategy_size
;
1167 case restore_sp_post_adjust
:
1170 case restore_sp_pre_adjust
:
1171 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1177 case restore_sp_partial_adjust
:
1178 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1180 GEN_INT (size
+ 4 * num_regs_to_save
1181 + reg_save_bytes
- 252)));
1182 size
= 252 - reg_save_bytes
- 4 * num_regs_to_save
;
1186 reg
= gen_rtx_REG (SImode
, FIRST_ADDRESS_REGNUM
+ 1);
1187 emit_insn (gen_movsi (reg
, stack_pointer_rtx
));
1189 emit_insn (gen_addsi3 (reg
, reg
, GEN_INT (size
)));
1197 /* Adjust the selected register, if any, for post-increment. */
1199 reg
= gen_rtx_POST_INC (SImode
, reg
);
1201 for (i
= FIRST_FP_REGNUM
; i
<= LAST_FP_REGNUM
; ++i
)
1202 if (df_regs_ever_live_p (i
) && ! call_really_used_regs
[i
])
1210 /* If we aren't using a post-increment register, use an
1212 addr
= gen_rtx_PLUS (SImode
,
1217 addr
= stack_pointer_rtx
;
1221 emit_insn (gen_movsf (gen_rtx_REG (SFmode
, i
),
1222 gen_rtx_MEM (SFmode
, addr
)));
1225 /* If we were using the restore_a1 strategy and the number of
1226 bytes to be released won't fit in the `ret' byte, copy `a1'
1227 to `sp', to avoid having to use `add' to adjust it. */
1228 if (! frame_pointer_needed
&& reg
&& size
+ reg_save_bytes
> 255)
1230 emit_move_insn (stack_pointer_rtx
, XEXP (reg
, 0));
1235 /* Maybe cut back the stack, except for the register save area.
1237 If the frame pointer exists, then use the frame pointer to
1240 If the stack size + register save area is more than 255 bytes,
1241 then the stack must be cut back here since the size + register
1242 save size is too big for a ret/retf instruction.
1244 Else leave it alone, it will be cut back as part of the
1245 ret/retf instruction, or there wasn't any stack to begin with.
1247 Under no circumstances should the register save area be
1248 deallocated here, that would leave a window where an interrupt
1249 could occur and trash the register save area. */
1250 if (frame_pointer_needed
)
1252 emit_move_insn (stack_pointer_rtx
, frame_pointer_rtx
);
1255 else if (size
+ reg_save_bytes
> 255)
1257 emit_insn (gen_addsi3 (stack_pointer_rtx
,
1263 /* Adjust the stack and restore callee-saved registers, if any. */
1264 if (mn10300_can_use_rets_insn ())
1265 emit_jump_insn (ret_rtx
);
1267 emit_jump_insn (gen_return_ret (GEN_INT (size
+ reg_save_bytes
)));
1270 /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store().
1271 This function is for MATCH_PARALLEL and so assumes OP is known to be
1272 parallel. If OP is a multiple store, return a mask indicating which
1273 registers it saves. Return 0 otherwise. */
1276 mn10300_store_multiple_regs (rtx op
)
1284 count
= XVECLEN (op
, 0);
1288 /* Check that first instruction has the form (set (sp) (plus A B)) */
1289 elt
= XVECEXP (op
, 0, 0);
1290 if (GET_CODE (elt
) != SET
1291 || (! REG_P (SET_DEST (elt
)))
1292 || REGNO (SET_DEST (elt
)) != STACK_POINTER_REGNUM
1293 || GET_CODE (SET_SRC (elt
)) != PLUS
)
1296 /* Check that A is the stack pointer and B is the expected stack size.
1297 For OP to match, each subsequent instruction should push a word onto
1298 the stack. We therefore expect the first instruction to create
1299 COUNT-1 stack slots. */
1300 elt
= SET_SRC (elt
);
1301 if ((! REG_P (XEXP (elt
, 0)))
1302 || REGNO (XEXP (elt
, 0)) != STACK_POINTER_REGNUM
1303 || (! CONST_INT_P (XEXP (elt
, 1)))
1304 || INTVAL (XEXP (elt
, 1)) != -(count
- 1) * 4)
1308 for (i
= 1; i
< count
; i
++)
1310 /* Check that element i is a (set (mem M) R). */
1311 /* ??? Validate the register order a-la mn10300_gen_multiple_store.
1312 Remember: the ordering is *not* monotonic. */
1313 elt
= XVECEXP (op
, 0, i
);
1314 if (GET_CODE (elt
) != SET
1315 || (! MEM_P (SET_DEST (elt
)))
1316 || (! REG_P (SET_SRC (elt
))))
1319 /* Remember which registers are to be saved. */
1320 last
= REGNO (SET_SRC (elt
));
1321 mask
|= (1 << last
);
1323 /* Check that M has the form (plus (sp) (const_int -I*4)) */
1324 elt
= XEXP (SET_DEST (elt
), 0);
1325 if (GET_CODE (elt
) != PLUS
1326 || (! REG_P (XEXP (elt
, 0)))
1327 || REGNO (XEXP (elt
, 0)) != STACK_POINTER_REGNUM
1328 || (! CONST_INT_P (XEXP (elt
, 1)))
1329 || INTVAL (XEXP (elt
, 1)) != -i
* 4)
1333 /* All or none of the callee-saved extended registers must be in the set. */
1334 if ((mask
& 0x3c000) != 0
1335 && (mask
& 0x3c000) != 0x3c000)
1341 /* Implement TARGET_PREFERRED_RELOAD_CLASS. */
1344 mn10300_preferred_reload_class (rtx x
, reg_class_t rclass
)
1346 if (x
== stack_pointer_rtx
&& rclass
!= SP_REGS
)
1347 return (TARGET_AM33
? GENERAL_REGS
: ADDRESS_REGS
);
1350 && !HARD_REGISTER_P (x
))
1351 || (GET_CODE (x
) == SUBREG
1352 && REG_P (SUBREG_REG (x
))
1353 && !HARD_REGISTER_P (SUBREG_REG (x
))))
1354 return LIMIT_RELOAD_CLASS (GET_MODE (x
), rclass
);
1359 /* Implement TARGET_PREFERRED_OUTPUT_RELOAD_CLASS. */
1362 mn10300_preferred_output_reload_class (rtx x
, reg_class_t rclass
)
1364 if (x
== stack_pointer_rtx
&& rclass
!= SP_REGS
)
1365 return (TARGET_AM33
? GENERAL_REGS
: ADDRESS_REGS
);
1369 /* Implement TARGET_SECONDARY_RELOAD. */
1372 mn10300_secondary_reload (bool in_p
, rtx x
, reg_class_t rclass_i
,
1373 machine_mode mode
, secondary_reload_info
*sri
)
1375 enum reg_class rclass
= (enum reg_class
) rclass_i
;
1376 enum reg_class xclass
= NO_REGS
;
1377 unsigned int xregno
= INVALID_REGNUM
;
1382 if (xregno
>= FIRST_PSEUDO_REGISTER
)
1383 xregno
= true_regnum (x
);
1384 if (xregno
!= INVALID_REGNUM
)
1385 xclass
= REGNO_REG_CLASS (xregno
);
1390 /* Memory load/stores less than a full word wide can't have an
1391 address or stack pointer destination. They must use a data
1392 register as an intermediate register. */
1393 if (rclass
!= DATA_REGS
1394 && (mode
== QImode
|| mode
== HImode
)
1395 && xclass
== NO_REGS
)
1398 /* We can only move SP to/from an address register. */
1400 && rclass
== SP_REGS
1401 && xclass
!= ADDRESS_REGS
)
1402 return ADDRESS_REGS
;
1404 && xclass
== SP_REGS
1405 && rclass
!= ADDRESS_REGS
1406 && rclass
!= SP_OR_ADDRESS_REGS
)
1407 return ADDRESS_REGS
;
1410 /* We can't directly load sp + const_int into a register;
1411 we must use an address register as an scratch. */
1413 && rclass
!= SP_REGS
1414 && rclass
!= SP_OR_ADDRESS_REGS
1415 && rclass
!= SP_OR_GENERAL_REGS
1416 && GET_CODE (x
) == PLUS
1417 && (XEXP (x
, 0) == stack_pointer_rtx
1418 || XEXP (x
, 1) == stack_pointer_rtx
))
1420 sri
->icode
= CODE_FOR_reload_plus_sp_const
;
1424 /* We can only move MDR to/from a data register. */
1425 if (rclass
== MDR_REGS
&& xclass
!= DATA_REGS
)
1427 if (xclass
== MDR_REGS
&& rclass
!= DATA_REGS
)
1430 /* We can't load/store an FP register from a constant address. */
1432 && (rclass
== FP_REGS
|| xclass
== FP_REGS
)
1433 && (xclass
== NO_REGS
|| rclass
== NO_REGS
))
1437 if (xregno
>= FIRST_PSEUDO_REGISTER
&& xregno
!= INVALID_REGNUM
)
1439 addr
= reg_equiv_mem (xregno
);
1441 addr
= XEXP (addr
, 0);
1446 if (addr
&& CONSTANT_ADDRESS_P (addr
))
1447 return GENERAL_REGS
;
1449 /* Otherwise assume no secondary reloads are needed. */
1454 mn10300_frame_size (void)
1456 /* size includes the fixed stack space needed for function calls. */
1457 int size
= get_frame_size () + crtl
->outgoing_args_size
;
1459 /* And space for the return pointer. */
1460 size
+= crtl
->outgoing_args_size
? 4 : 0;
1466 mn10300_initial_offset (int from
, int to
)
1470 gcc_assert (from
== ARG_POINTER_REGNUM
|| from
== FRAME_POINTER_REGNUM
);
1471 gcc_assert (to
== FRAME_POINTER_REGNUM
|| to
== STACK_POINTER_REGNUM
);
1473 if (to
== STACK_POINTER_REGNUM
)
1474 diff
= mn10300_frame_size ();
1476 /* The difference between the argument pointer and the frame pointer
1477 is the size of the callee register save area. */
1478 if (from
== ARG_POINTER_REGNUM
)
1480 unsigned int reg_save_bytes
;
1482 mn10300_get_live_callee_saved_regs (& reg_save_bytes
);
1483 diff
+= reg_save_bytes
;
1484 diff
+= 4 * fp_regs_to_save ();
1490 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1493 mn10300_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
1495 /* Return values > 8 bytes in length in memory. */
1496 return (int_size_in_bytes (type
) > 8
1497 || int_size_in_bytes (type
) == 0
1498 || TYPE_MODE (type
) == BLKmode
);
1501 /* Flush the argument registers to the stack for a stdarg function;
1502 return the new argument pointer. */
1504 mn10300_builtin_saveregs (void)
1507 tree fntype
= TREE_TYPE (current_function_decl
);
1508 int argadj
= ((!stdarg_p (fntype
))
1509 ? UNITS_PER_WORD
: 0);
1510 alias_set_type set
= get_varargs_alias_set ();
1513 offset
= plus_constant (Pmode
, crtl
->args
.arg_offset_rtx
, argadj
);
1515 offset
= crtl
->args
.arg_offset_rtx
;
1517 mem
= gen_rtx_MEM (SImode
, crtl
->args
.internal_arg_pointer
);
1518 set_mem_alias_set (mem
, set
);
1519 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
1521 mem
= gen_rtx_MEM (SImode
,
1522 plus_constant (Pmode
,
1523 crtl
->args
.internal_arg_pointer
, 4));
1524 set_mem_alias_set (mem
, set
);
1525 emit_move_insn (mem
, gen_rtx_REG (SImode
, 1));
1527 return copy_to_reg (expand_binop (Pmode
, add_optab
,
1528 crtl
->args
.internal_arg_pointer
,
1529 offset
, 0, 0, OPTAB_LIB_WIDEN
));
1533 mn10300_va_start (tree valist
, rtx nextarg
)
1535 nextarg
= expand_builtin_saveregs ();
1536 std_expand_builtin_va_start (valist
, nextarg
);
1539 /* Return true when a parameter should be passed by reference. */
1542 mn10300_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED
,
1543 machine_mode mode
, const_tree type
,
1544 bool named ATTRIBUTE_UNUSED
)
1546 unsigned HOST_WIDE_INT size
;
1549 size
= int_size_in_bytes (type
);
1551 size
= GET_MODE_SIZE (mode
);
1553 return (size
> 8 || size
== 0);
1556 /* Return an RTX to represent where a value with mode MODE will be returned
1557 from a function. If the result is NULL_RTX, the argument is pushed. */
1560 mn10300_function_arg (cumulative_args_t cum_v
, machine_mode mode
,
1561 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1563 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1564 rtx result
= NULL_RTX
;
1567 /* We only support using 2 data registers as argument registers. */
1570 /* Figure out the size of the object to be passed. */
1571 if (mode
== BLKmode
)
1572 size
= int_size_in_bytes (type
);
1574 size
= GET_MODE_SIZE (mode
);
1576 cum
->nbytes
= (cum
->nbytes
+ 3) & ~3;
1578 /* Don't pass this arg via a register if all the argument registers
1580 if (cum
->nbytes
> nregs
* UNITS_PER_WORD
)
1583 /* Don't pass this arg via a register if it would be split between
1584 registers and memory. */
1585 if (type
== NULL_TREE
1586 && cum
->nbytes
+ size
> nregs
* UNITS_PER_WORD
)
1589 switch (cum
->nbytes
/ UNITS_PER_WORD
)
1592 result
= gen_rtx_REG (mode
, FIRST_ARGUMENT_REGNUM
);
1595 result
= gen_rtx_REG (mode
, FIRST_ARGUMENT_REGNUM
+ 1);
1604 /* Update the data in CUM to advance over an argument
1605 of mode MODE and data type TYPE.
1606 (TYPE is null for libcalls where that information may not be available.) */
1609 mn10300_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
1610 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1612 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1614 cum
->nbytes
+= (mode
!= BLKmode
1615 ? (GET_MODE_SIZE (mode
) + 3) & ~3
1616 : (int_size_in_bytes (type
) + 3) & ~3);
1619 /* Return the number of bytes of registers to use for an argument passed
1620 partially in registers and partially in memory. */
1623 mn10300_arg_partial_bytes (cumulative_args_t cum_v
, machine_mode mode
,
1624 tree type
, bool named ATTRIBUTE_UNUSED
)
1626 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1629 /* We only support using 2 data registers as argument registers. */
1632 /* Figure out the size of the object to be passed. */
1633 if (mode
== BLKmode
)
1634 size
= int_size_in_bytes (type
);
1636 size
= GET_MODE_SIZE (mode
);
1638 cum
->nbytes
= (cum
->nbytes
+ 3) & ~3;
1640 /* Don't pass this arg via a register if all the argument registers
1642 if (cum
->nbytes
> nregs
* UNITS_PER_WORD
)
1645 if (cum
->nbytes
+ size
<= nregs
* UNITS_PER_WORD
)
1648 /* Don't pass this arg via a register if it would be split between
1649 registers and memory. */
1650 if (type
== NULL_TREE
1651 && cum
->nbytes
+ size
> nregs
* UNITS_PER_WORD
)
1654 return nregs
* UNITS_PER_WORD
- cum
->nbytes
;
1657 /* Return the location of the function's value. This will be either
1658 $d0 for integer functions, $a0 for pointers, or a PARALLEL of both
1659 $d0 and $a0 if the -mreturn-pointer-on-do flag is set. Note that
1660 we only return the PARALLEL for outgoing values; we do not want
1661 callers relying on this extra copy. */
1664 mn10300_function_value (const_tree valtype
,
1665 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
1669 machine_mode mode
= TYPE_MODE (valtype
);
1671 if (! POINTER_TYPE_P (valtype
))
1672 return gen_rtx_REG (mode
, FIRST_DATA_REGNUM
);
1673 else if (! TARGET_PTR_A0D0
|| ! outgoing
1674 || cfun
->returns_struct
)
1675 return gen_rtx_REG (mode
, FIRST_ADDRESS_REGNUM
);
1677 rv
= gen_rtx_PARALLEL (mode
, rtvec_alloc (2));
1679 = gen_rtx_EXPR_LIST (VOIDmode
,
1680 gen_rtx_REG (mode
, FIRST_ADDRESS_REGNUM
),
1684 = gen_rtx_EXPR_LIST (VOIDmode
,
1685 gen_rtx_REG (mode
, FIRST_DATA_REGNUM
),
1690 /* Implements TARGET_LIBCALL_VALUE. */
1693 mn10300_libcall_value (machine_mode mode
,
1694 const_rtx fun ATTRIBUTE_UNUSED
)
1696 return gen_rtx_REG (mode
, FIRST_DATA_REGNUM
);
1699 /* Implements FUNCTION_VALUE_REGNO_P. */
1702 mn10300_function_value_regno_p (const unsigned int regno
)
1704 return (regno
== FIRST_DATA_REGNUM
|| regno
== FIRST_ADDRESS_REGNUM
);
1707 /* Output an addition operation. */
1710 mn10300_output_add (rtx operands
[3], bool need_flags
)
1712 rtx dest
, src1
, src2
;
1713 unsigned int dest_regnum
, src1_regnum
, src2_regnum
;
1714 enum reg_class src1_class
, src2_class
, dest_class
;
1720 dest_regnum
= true_regnum (dest
);
1721 src1_regnum
= true_regnum (src1
);
1723 dest_class
= REGNO_REG_CLASS (dest_regnum
);
1724 src1_class
= REGNO_REG_CLASS (src1_regnum
);
1726 if (CONST_INT_P (src2
))
1728 gcc_assert (dest_regnum
== src1_regnum
);
1730 if (src2
== const1_rtx
&& !need_flags
)
1732 if (INTVAL (src2
) == 4 && !need_flags
&& dest_class
!= DATA_REGS
)
1735 gcc_assert (!need_flags
|| dest_class
!= SP_REGS
);
1738 else if (CONSTANT_P (src2
))
1741 src2_regnum
= true_regnum (src2
);
1742 src2_class
= REGNO_REG_CLASS (src2_regnum
);
1744 if (dest_regnum
== src1_regnum
)
1746 if (dest_regnum
== src2_regnum
)
1749 /* The rest of the cases are reg = reg+reg. For AM33, we can implement
1750 this directly, as below, but when optimizing for space we can sometimes
1751 do better by using a mov+add. For MN103, we claimed that we could
1752 implement a three-operand add because the various move and add insns
1753 change sizes across register classes, and we can often do better than
1754 reload in choosing which operand to move. */
1755 if (TARGET_AM33
&& optimize_insn_for_speed_p ())
1756 return "add %2,%1,%0";
1758 /* Catch cases where no extended register was used. */
1759 if (src1_class
!= EXTENDED_REGS
1760 && src2_class
!= EXTENDED_REGS
1761 && dest_class
!= EXTENDED_REGS
)
1763 /* We have to copy one of the sources into the destination, then
1764 add the other source to the destination.
1766 Carefully select which source to copy to the destination; a
1767 naive implementation will waste a byte when the source classes
1768 are different and the destination is an address register.
1769 Selecting the lowest cost register copy will optimize this
1771 if (src1_class
== dest_class
)
1772 return "mov %1,%0\n\tadd %2,%0";
1774 return "mov %2,%0\n\tadd %1,%0";
1777 /* At least one register is an extended register. */
1779 /* The three operand add instruction on the am33 is a win iff the
1780 output register is an extended register, or if both source
1781 registers are extended registers. */
1782 if (dest_class
== EXTENDED_REGS
|| src1_class
== src2_class
)
1783 return "add %2,%1,%0";
1785 /* It is better to copy one of the sources to the destination, then
1786 perform a 2 address add. The destination in this case must be
1787 an address or data register and one of the sources must be an
1788 extended register and the remaining source must not be an extended
1791 The best code for this case is to copy the extended reg to the
1792 destination, then emit a two address add. */
1793 if (src1_class
== EXTENDED_REGS
)
1794 return "mov %1,%0\n\tadd %2,%0";
1796 return "mov %2,%0\n\tadd %1,%0";
1799 /* Return 1 if X contains a symbolic expression. We know these
1800 expressions will have one of a few well defined forms, so
1801 we need only check those forms. */
1804 mn10300_symbolic_operand (rtx op
,
1805 machine_mode mode ATTRIBUTE_UNUSED
)
1807 switch (GET_CODE (op
))
1814 return ((GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
1815 || GET_CODE (XEXP (op
, 0)) == LABEL_REF
)
1816 && CONST_INT_P (XEXP (op
, 1)));
1822 /* Try machine dependent ways of modifying an illegitimate address
1823 to be legitimate. If we find one, return the new valid address.
1824 This macro is used in only one place: `memory_address' in explow.c.
1826 OLDX is the address as it was before break_out_memory_refs was called.
1827 In some cases it is useful to look at this to decide what needs to be done.
1829 Normally it is always safe for this macro to do nothing. It exists to
1830 recognize opportunities to optimize the output.
1832 But on a few ports with segmented architectures and indexed addressing
1833 (mn10300, hppa) it is used to rewrite certain problematical addresses. */
1836 mn10300_legitimize_address (rtx x
, rtx oldx ATTRIBUTE_UNUSED
,
1837 machine_mode mode ATTRIBUTE_UNUSED
)
1839 if (flag_pic
&& ! mn10300_legitimate_pic_operand_p (x
))
1840 x
= mn10300_legitimize_pic_address (oldx
, NULL_RTX
);
1842 /* Uh-oh. We might have an address for x[n-100000]. This needs
1843 special handling to avoid creating an indexed memory address
1844 with x-100000 as the base. */
1845 if (GET_CODE (x
) == PLUS
1846 && mn10300_symbolic_operand (XEXP (x
, 1), VOIDmode
))
1848 /* Ugly. We modify things here so that the address offset specified
1849 by the index expression is computed first, then added to x to form
1850 the entire address. */
1852 rtx regx1
, regy1
, regy2
, y
;
1854 /* Strip off any CONST. */
1856 if (GET_CODE (y
) == CONST
)
1859 if (GET_CODE (y
) == PLUS
|| GET_CODE (y
) == MINUS
)
1861 regx1
= force_reg (Pmode
, force_operand (XEXP (x
, 0), 0));
1862 regy1
= force_reg (Pmode
, force_operand (XEXP (y
, 0), 0));
1863 regy2
= force_reg (Pmode
, force_operand (XEXP (y
, 1), 0));
1864 regx1
= force_reg (Pmode
,
1865 gen_rtx_fmt_ee (GET_CODE (y
), Pmode
, regx1
,
1867 return force_reg (Pmode
, gen_rtx_PLUS (Pmode
, regx1
, regy1
));
1873 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
1874 @GOTOFF in `reg'. */
1877 mn10300_legitimize_pic_address (rtx orig
, rtx reg
)
1881 if (GET_CODE (orig
) == LABEL_REF
1882 || (GET_CODE (orig
) == SYMBOL_REF
1883 && (CONSTANT_POOL_ADDRESS_P (orig
)
1884 || ! MN10300_GLOBAL_P (orig
))))
1887 reg
= gen_reg_rtx (Pmode
);
1889 x
= gen_rtx_UNSPEC (SImode
, gen_rtvec (1, orig
), UNSPEC_GOTOFF
);
1890 x
= gen_rtx_CONST (SImode
, x
);
1891 emit_move_insn (reg
, x
);
1893 x
= emit_insn (gen_addsi3 (reg
, reg
, pic_offset_table_rtx
));
1895 else if (GET_CODE (orig
) == SYMBOL_REF
)
1898 reg
= gen_reg_rtx (Pmode
);
1900 x
= gen_rtx_UNSPEC (SImode
, gen_rtvec (1, orig
), UNSPEC_GOT
);
1901 x
= gen_rtx_CONST (SImode
, x
);
1902 x
= gen_rtx_PLUS (SImode
, pic_offset_table_rtx
, x
);
1903 x
= gen_const_mem (SImode
, x
);
1905 x
= emit_move_insn (reg
, x
);
1910 set_unique_reg_note (x
, REG_EQUAL
, orig
);
1914 /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol
1915 isn't protected by a PIC unspec; nonzero otherwise. */
1918 mn10300_legitimate_pic_operand_p (rtx x
)
1923 if (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
)
1926 if (GET_CODE (x
) == UNSPEC
1927 && (XINT (x
, 1) == UNSPEC_PIC
1928 || XINT (x
, 1) == UNSPEC_GOT
1929 || XINT (x
, 1) == UNSPEC_GOTOFF
1930 || XINT (x
, 1) == UNSPEC_PLT
1931 || XINT (x
, 1) == UNSPEC_GOTSYM_OFF
))
1934 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
1935 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
1941 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1942 if (! mn10300_legitimate_pic_operand_p (XVECEXP (x
, i
, j
)))
1945 else if (fmt
[i
] == 'e'
1946 && ! mn10300_legitimate_pic_operand_p (XEXP (x
, i
)))
1953 /* Return TRUE if the address X, taken from a (MEM:MODE X) rtx, is
1954 legitimate, and FALSE otherwise.
1956 On the mn10300, the value in the address register must be
1957 in the same memory space/segment as the effective address.
1959 This is problematical for reload since it does not understand
1960 that base+index != index+base in a memory reference.
1962 Note it is still possible to use reg+reg addressing modes,
1963 it's just much more difficult. For a discussion of a possible
1964 workaround and solution, see the comments in pa.c before the
1965 function record_unscaled_index_insn_codes. */
1968 mn10300_legitimate_address_p (machine_mode mode
, rtx x
, bool strict
)
1972 if (CONSTANT_ADDRESS_P (x
))
1973 return !flag_pic
|| mn10300_legitimate_pic_operand_p (x
);
1975 if (RTX_OK_FOR_BASE_P (x
, strict
))
1978 if (TARGET_AM33
&& (mode
== SImode
|| mode
== SFmode
|| mode
== HImode
))
1980 if (GET_CODE (x
) == POST_INC
)
1981 return RTX_OK_FOR_BASE_P (XEXP (x
, 0), strict
);
1982 if (GET_CODE (x
) == POST_MODIFY
)
1983 return (RTX_OK_FOR_BASE_P (XEXP (x
, 0), strict
)
1984 && CONSTANT_ADDRESS_P (XEXP (x
, 1)));
1987 if (GET_CODE (x
) != PLUS
)
1991 index
= XEXP (x
, 1);
1997 /* ??? Without AM33 generalized (Ri,Rn) addressing, reg+reg
1998 addressing is hard to satisfy. */
2002 return (REGNO_GENERAL_P (REGNO (base
), strict
)
2003 && REGNO_GENERAL_P (REGNO (index
), strict
));
2006 if (!REGNO_STRICT_OK_FOR_BASE_P (REGNO (base
), strict
))
2009 if (CONST_INT_P (index
))
2010 return IN_RANGE (INTVAL (index
), -1 - 0x7fffffff, 0x7fffffff);
2012 if (CONSTANT_ADDRESS_P (index
))
2013 return !flag_pic
|| mn10300_legitimate_pic_operand_p (index
);
2019 mn10300_regno_in_class_p (unsigned regno
, int rclass
, bool strict
)
2021 if (regno
>= FIRST_PSEUDO_REGISTER
)
2027 regno
= reg_renumber
[regno
];
2028 if (regno
== INVALID_REGNUM
)
2031 return TEST_HARD_REG_BIT (reg_class_contents
[rclass
], regno
);
2035 mn10300_legitimize_reload_address (rtx x
,
2036 machine_mode mode ATTRIBUTE_UNUSED
,
2037 int opnum
, int type
,
2038 int ind_levels ATTRIBUTE_UNUSED
)
2040 bool any_change
= false;
2042 /* See above re disabling reg+reg addressing for MN103. */
2046 if (GET_CODE (x
) != PLUS
)
2049 if (XEXP (x
, 0) == stack_pointer_rtx
)
2051 push_reload (XEXP (x
, 0), NULL_RTX
, &XEXP (x
, 0), NULL
,
2052 GENERAL_REGS
, GET_MODE (x
), VOIDmode
, 0, 0,
2053 opnum
, (enum reload_type
) type
);
2056 if (XEXP (x
, 1) == stack_pointer_rtx
)
2058 push_reload (XEXP (x
, 1), NULL_RTX
, &XEXP (x
, 1), NULL
,
2059 GENERAL_REGS
, GET_MODE (x
), VOIDmode
, 0, 0,
2060 opnum
, (enum reload_type
) type
);
2064 return any_change
? x
: NULL_RTX
;
2067 /* Implement TARGET_LEGITIMATE_CONSTANT_P. Returns TRUE if X is a valid
2068 constant. Note that some "constants" aren't valid, such as TLS
2069 symbols and unconverted GOT-based references, so we eliminate
2073 mn10300_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2075 switch (GET_CODE (x
))
2080 if (GET_CODE (x
) == PLUS
)
2082 if (! CONST_INT_P (XEXP (x
, 1)))
2087 /* Only some unspecs are valid as "constants". */
2088 if (GET_CODE (x
) == UNSPEC
)
2090 switch (XINT (x
, 1))
2102 /* We must have drilled down to a symbol. */
2103 if (! mn10300_symbolic_operand (x
, Pmode
))
2114 /* Undo pic address legitimization for the benefit of debug info. */
2117 mn10300_delegitimize_address (rtx orig_x
)
2119 rtx x
= orig_x
, ret
, addend
= NULL
;
2124 if (GET_CODE (x
) != PLUS
|| GET_MODE (x
) != Pmode
)
2127 if (XEXP (x
, 0) == pic_offset_table_rtx
)
2129 /* With the REG+REG addressing of AM33, var-tracking can re-assemble
2130 some odd-looking "addresses" that were never valid in the first place.
2131 We need to look harder to avoid warnings being emitted. */
2132 else if (GET_CODE (XEXP (x
, 0)) == PLUS
)
2134 rtx x0
= XEXP (x
, 0);
2135 rtx x00
= XEXP (x0
, 0);
2136 rtx x01
= XEXP (x0
, 1);
2138 if (x00
== pic_offset_table_rtx
)
2140 else if (x01
== pic_offset_table_rtx
)
2150 if (GET_CODE (x
) != CONST
)
2153 if (GET_CODE (x
) != UNSPEC
)
2156 ret
= XVECEXP (x
, 0, 0);
2157 if (XINT (x
, 1) == UNSPEC_GOTOFF
)
2159 else if (XINT (x
, 1) == UNSPEC_GOT
)
2164 gcc_assert (GET_CODE (ret
) == SYMBOL_REF
);
2165 if (need_mem
!= MEM_P (orig_x
))
2167 if (need_mem
&& addend
)
2170 ret
= gen_rtx_PLUS (Pmode
, addend
, ret
);
2174 /* For addresses, costs are relative to "MOV (Rm),Rn". For AM33 this is
2175 the 3-byte fully general instruction; for MN103 this is the 2-byte form
2176 with an address register. */
2179 mn10300_address_cost (rtx x
, machine_mode mode ATTRIBUTE_UNUSED
,
2180 addr_space_t as ATTRIBUTE_UNUSED
, bool speed
)
2185 switch (GET_CODE (x
))
2190 /* We assume all of these require a 32-bit constant, even though
2191 some symbol and label references can be relaxed. */
2192 return speed
? 1 : 4;
2200 /* Assume any symbolic offset is a 32-bit constant. */
2201 i
= (CONST_INT_P (XEXP (x
, 1)) ? INTVAL (XEXP (x
, 1)) : 0x12345678);
2202 if (IN_RANGE (i
, -128, 127))
2203 return speed
? 0 : 1;
2206 if (IN_RANGE (i
, -0x800000, 0x7fffff))
2212 index
= XEXP (x
, 1);
2213 if (register_operand (index
, SImode
))
2215 /* Attempt to minimize the number of registers in the address.
2216 This is similar to what other ports do. */
2217 if (register_operand (base
, SImode
))
2221 index
= XEXP (x
, 0);
2224 /* Assume any symbolic offset is a 32-bit constant. */
2225 i
= (CONST_INT_P (XEXP (x
, 1)) ? INTVAL (XEXP (x
, 1)) : 0x12345678);
2226 if (IN_RANGE (i
, -128, 127))
2227 return speed
? 0 : 1;
2228 if (IN_RANGE (i
, -32768, 32767))
2229 return speed
? 0 : 2;
2230 return speed
? 2 : 6;
2233 return rtx_cost (x
, MEM
, 0, speed
);
2237 /* Implement the TARGET_REGISTER_MOVE_COST hook.
2239 Recall that the base value of 2 is required by assumptions elsewhere
2240 in the body of the compiler, and that cost 2 is special-cased as an
2241 early exit from reload meaning no work is required. */
2244 mn10300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
2245 reg_class_t ifrom
, reg_class_t ito
)
2247 enum reg_class from
= (enum reg_class
) ifrom
;
2248 enum reg_class to
= (enum reg_class
) ito
;
2249 enum reg_class scratch
, test
;
2251 /* Simplify the following code by unifying the fp register classes. */
2252 if (to
== FP_ACC_REGS
)
2254 if (from
== FP_ACC_REGS
)
2257 /* Diagnose invalid moves by costing them as two moves. */
2262 scratch
= (TARGET_AM33
? GENERAL_REGS
: ADDRESS_REGS
);
2263 else if (to
== MDR_REGS
)
2264 scratch
= DATA_REGS
;
2265 else if (to
== FP_REGS
&& to
!= from
)
2266 scratch
= GENERAL_REGS
;
2270 if (from
== SP_REGS
)
2271 scratch
= (TARGET_AM33
? GENERAL_REGS
: ADDRESS_REGS
);
2272 else if (from
== MDR_REGS
)
2273 scratch
= DATA_REGS
;
2274 else if (from
== FP_REGS
&& to
!= from
)
2275 scratch
= GENERAL_REGS
;
2277 if (scratch
!= NO_REGS
&& !reg_class_subset_p (test
, scratch
))
2278 return (mn10300_register_move_cost (VOIDmode
, from
, scratch
)
2279 + mn10300_register_move_cost (VOIDmode
, scratch
, to
));
2281 /* From here on, all we need consider are legal combinations. */
2285 /* The scale here is bytes * 2. */
2287 if (from
== to
&& (to
== ADDRESS_REGS
|| to
== DATA_REGS
))
2290 if (from
== SP_REGS
)
2291 return (to
== ADDRESS_REGS
? 2 : 6);
2293 /* For MN103, all remaining legal moves are two bytes. */
2298 return (from
== ADDRESS_REGS
? 4 : 6);
2300 if ((from
== ADDRESS_REGS
|| from
== DATA_REGS
)
2301 && (to
== ADDRESS_REGS
|| to
== DATA_REGS
))
2304 if (to
== EXTENDED_REGS
)
2305 return (to
== from
? 6 : 4);
2307 /* What's left are SP_REGS, FP_REGS, or combinations of the above. */
2312 /* The scale here is cycles * 2. */
2316 if (from
== FP_REGS
)
2319 /* All legal moves between integral registers are single cycle. */
2324 /* Implement the TARGET_MEMORY_MOVE_COST hook.
2326 Given lack of the form of the address, this must be speed-relative,
2327 though we should never be less expensive than a size-relative register
2328 move cost above. This is not a problem. */
2331 mn10300_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
2332 reg_class_t iclass
, bool in ATTRIBUTE_UNUSED
)
2334 enum reg_class rclass
= (enum reg_class
) iclass
;
2336 if (rclass
== FP_REGS
)
2341 /* Implement the TARGET_RTX_COSTS hook.
2343 Speed-relative costs are relative to COSTS_N_INSNS, which is intended
2344 to represent cycles. Size-relative costs are in bytes. */
2347 mn10300_rtx_costs (rtx x
, int code
, int outer_code
, int opno ATTRIBUTE_UNUSED
,
2348 int *ptotal
, bool speed
)
2350 /* This value is used for SYMBOL_REF etc where we want to pretend
2351 we have a full 32-bit constant. */
2352 HOST_WIDE_INT i
= 0x12345678;
2362 if (outer_code
== SET
)
2364 /* 16-bit integer loads have latency 1, 32-bit loads 2. */
2365 if (IN_RANGE (i
, -32768, 32767))
2366 total
= COSTS_N_INSNS (1);
2368 total
= COSTS_N_INSNS (2);
2372 /* 16-bit integer operands don't affect latency;
2373 24-bit and 32-bit operands add a cycle. */
2374 if (IN_RANGE (i
, -32768, 32767))
2377 total
= COSTS_N_INSNS (1);
2382 if (outer_code
== SET
)
2386 else if (IN_RANGE (i
, -128, 127))
2388 else if (IN_RANGE (i
, -32768, 32767))
2395 /* Reference here is ADD An,Dn, vs ADD imm,Dn. */
2396 if (IN_RANGE (i
, -128, 127))
2398 else if (IN_RANGE (i
, -32768, 32767))
2400 else if (TARGET_AM33
&& IN_RANGE (i
, -0x01000000, 0x00ffffff))
2412 /* We assume all of these require a 32-bit constant, even though
2413 some symbol and label references can be relaxed. */
2417 switch (XINT (x
, 1))
2423 case UNSPEC_GOTSYM_OFF
:
2424 /* The PIC unspecs also resolve to a 32-bit constant. */
2428 /* Assume any non-listed unspec is some sort of arithmetic. */
2429 goto do_arith_costs
;
2433 /* Notice the size difference of INC and INC4. */
2434 if (!speed
&& outer_code
== SET
&& CONST_INT_P (XEXP (x
, 1)))
2436 i
= INTVAL (XEXP (x
, 1));
2437 if (i
== 1 || i
== 4)
2439 total
= 1 + rtx_cost (XEXP (x
, 0), PLUS
, 0, speed
);
2443 goto do_arith_costs
;
2457 total
= (speed
? COSTS_N_INSNS (1) : 2);
2461 /* Notice the size difference of ASL2 and variants. */
2462 if (!speed
&& CONST_INT_P (XEXP (x
, 1)))
2463 switch (INTVAL (XEXP (x
, 1)))
2478 total
= (speed
? COSTS_N_INSNS (1) : 3);
2482 total
= (speed
? COSTS_N_INSNS (3) : 2);
2489 total
= (speed
? COSTS_N_INSNS (39)
2490 /* Include space to load+retrieve MDR. */
2491 : code
== MOD
|| code
== UMOD
? 6 : 4);
2495 total
= mn10300_address_cost (XEXP (x
, 0), GET_MODE (x
),
2496 MEM_ADDR_SPACE (x
), speed
);
2498 total
= COSTS_N_INSNS (2 + total
);
2502 /* Probably not implemented. Assume external call. */
2503 total
= (speed
? COSTS_N_INSNS (10) : 7);
2515 /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
2516 may access it using GOTOFF instead of GOT. */
2519 mn10300_encode_section_info (tree decl
, rtx rtl
, int first
)
2523 default_encode_section_info (decl
, rtl
, first
);
2528 symbol
= XEXP (rtl
, 0);
2529 if (GET_CODE (symbol
) != SYMBOL_REF
)
2533 SYMBOL_REF_FLAG (symbol
) = (*targetm
.binds_local_p
) (decl
);
2536 /* Dispatch tables on the mn10300 are extremely expensive in terms of code
2537 and readonly data size. So we crank up the case threshold value to
2538 encourage a series of if/else comparisons to implement many small switch
2539 statements. In theory, this value could be increased much more if we
2540 were solely optimizing for space, but we keep it "reasonable" to avoid
2541 serious code efficiency lossage. */
2544 mn10300_case_values_threshold (void)
2549 /* Worker function for TARGET_TRAMPOLINE_INIT. */
2552 mn10300_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
2554 rtx mem
, disp
, fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
2556 /* This is a strict alignment target, which means that we play
2557 some games to make sure that the locations at which we need
2558 to store <chain> and <disp> wind up at aligned addresses.
2561 0xfc 0xdd mov chain,a1
2563 0xf8 0xed 0x00 btst 0,d1
2567 Note that the two extra insns are effectively nops; they
2568 clobber the flags but do not affect the contents of D0 or D1. */
2570 disp
= expand_binop (SImode
, sub_optab
, fnaddr
,
2571 plus_constant (Pmode
, XEXP (m_tramp
, 0), 11),
2572 NULL_RTX
, 1, OPTAB_DIRECT
);
2574 mem
= adjust_address (m_tramp
, SImode
, 0);
2575 emit_move_insn (mem
, gen_int_mode (0xddfc0028, SImode
));
2576 mem
= adjust_address (m_tramp
, SImode
, 4);
2577 emit_move_insn (mem
, chain_value
);
2578 mem
= adjust_address (m_tramp
, SImode
, 8);
2579 emit_move_insn (mem
, gen_int_mode (0xdc00edf8, SImode
));
2580 mem
= adjust_address (m_tramp
, SImode
, 12);
2581 emit_move_insn (mem
, disp
);
2584 /* Output the assembler code for a C++ thunk function.
2585 THUNK_DECL is the declaration for the thunk function itself, FUNCTION
2586 is the decl for the target function. DELTA is an immediate constant
2587 offset to be added to the THIS parameter. If VCALL_OFFSET is nonzero
2588 the word at the adjusted address *(*THIS' + VCALL_OFFSET) should be
2589 additionally added to THIS. Finally jump to the entry point of
2593 mn10300_asm_output_mi_thunk (FILE * file
,
2594 tree thunk_fndecl ATTRIBUTE_UNUSED
,
2595 HOST_WIDE_INT delta
,
2596 HOST_WIDE_INT vcall_offset
,
2601 /* Get the register holding the THIS parameter. Handle the case
2602 where there is a hidden first argument for a returned structure. */
2603 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)), function
))
2604 _this
= reg_names
[FIRST_ARGUMENT_REGNUM
+ 1];
2606 _this
= reg_names
[FIRST_ARGUMENT_REGNUM
];
2608 fprintf (file
, "\t%s Thunk Entry Point:\n", ASM_COMMENT_START
);
2611 fprintf (file
, "\tadd %d, %s\n", (int) delta
, _this
);
2615 const char * scratch
= reg_names
[FIRST_ADDRESS_REGNUM
+ 1];
2617 fprintf (file
, "\tmov %s, %s\n", _this
, scratch
);
2618 fprintf (file
, "\tmov (%s), %s\n", scratch
, scratch
);
2619 fprintf (file
, "\tadd %d, %s\n", (int) vcall_offset
, scratch
);
2620 fprintf (file
, "\tmov (%s), %s\n", scratch
, scratch
);
2621 fprintf (file
, "\tadd %s, %s\n", scratch
, _this
);
2624 fputs ("\tjmp ", file
);
2625 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
2629 /* Return true if mn10300_output_mi_thunk would be able to output the
2630 assembler code for the thunk function specified by the arguments
2631 it is passed, and false otherwise. */
2634 mn10300_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED
,
2635 HOST_WIDE_INT delta ATTRIBUTE_UNUSED
,
2636 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
2637 const_tree function ATTRIBUTE_UNUSED
)
2643 mn10300_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
2645 if (REGNO_REG_CLASS (regno
) == FP_REGS
2646 || REGNO_REG_CLASS (regno
) == FP_ACC_REGS
)
2647 /* Do not store integer values in FP registers. */
2648 return GET_MODE_CLASS (mode
) == MODE_FLOAT
&& ((regno
& 1) == 0);
2650 if (! TARGET_AM33
&& REGNO_REG_CLASS (regno
) == EXTENDED_REGS
)
2653 if (((regno
) & 1) == 0 || GET_MODE_SIZE (mode
) == 4)
2656 if (REGNO_REG_CLASS (regno
) == DATA_REGS
2657 || (TARGET_AM33
&& REGNO_REG_CLASS (regno
) == ADDRESS_REGS
)
2658 || REGNO_REG_CLASS (regno
) == EXTENDED_REGS
)
2659 return GET_MODE_SIZE (mode
) <= 4;
2665 mn10300_modes_tieable (machine_mode mode1
, machine_mode mode2
)
2667 if (GET_MODE_CLASS (mode1
) == MODE_FLOAT
2668 && GET_MODE_CLASS (mode2
) != MODE_FLOAT
)
2671 if (GET_MODE_CLASS (mode2
) == MODE_FLOAT
2672 && GET_MODE_CLASS (mode1
) != MODE_FLOAT
)
2677 || (GET_MODE_SIZE (mode1
) <= 4 && GET_MODE_SIZE (mode2
) <= 4))
2684 cc_flags_for_mode (machine_mode mode
)
2689 return CC_FLAG_Z
| CC_FLAG_N
| CC_FLAG_C
| CC_FLAG_V
;
2691 return CC_FLAG_Z
| CC_FLAG_N
| CC_FLAG_C
;
2693 return CC_FLAG_Z
| CC_FLAG_N
;
2702 cc_flags_for_code (enum rtx_code code
)
2715 case GT
: /* ~(Z|(N^V)) */
2716 case LE
: /* Z|(N^V) */
2717 return CC_FLAG_Z
| CC_FLAG_N
| CC_FLAG_V
;
2723 case GTU
: /* ~(C | Z) */
2724 case LEU
: /* C | Z */
2725 return CC_FLAG_Z
| CC_FLAG_C
;
2743 mn10300_select_cc_mode (enum rtx_code code
, rtx x
, rtx y ATTRIBUTE_UNUSED
)
2747 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
2748 return CC_FLOATmode
;
2750 req
= cc_flags_for_code (code
);
2752 if (req
& CC_FLAG_V
)
2754 if (req
& CC_FLAG_C
)
2760 set_is_load_p (rtx set
)
2762 return MEM_P (SET_SRC (set
));
2766 set_is_store_p (rtx set
)
2768 return MEM_P (SET_DEST (set
));
2771 /* Update scheduling costs for situations that cannot be
2772 described using the attributes and DFA machinery.
2773 DEP is the insn being scheduled.
2774 INSN is the previous insn.
2775 COST is the current cycle cost for DEP. */
2778 mn10300_adjust_sched_cost (rtx_insn
*insn
, rtx link
, rtx_insn
*dep
, int cost
)
2787 /* We are only interested in pairs of SET. */
2788 insn_set
= single_set (insn
);
2792 dep_set
= single_set (dep
);
2796 /* For the AM34 a load instruction that follows a
2797 store instruction incurs an extra cycle of delay. */
2798 if (mn10300_tune_cpu
== PROCESSOR_AM34
2799 && set_is_load_p (dep_set
)
2800 && set_is_store_p (insn_set
))
2803 /* For the AM34 a non-store, non-branch FPU insn that follows
2804 another FPU insn incurs a one cycle throughput increase. */
2805 else if (mn10300_tune_cpu
== PROCESSOR_AM34
2806 && ! set_is_store_p (insn_set
)
2808 && GET_MODE_CLASS (GET_MODE (SET_SRC (dep_set
))) == MODE_FLOAT
2809 && GET_MODE_CLASS (GET_MODE (SET_SRC (insn_set
))) == MODE_FLOAT
)
2812 /* Resolve the conflict described in section 1-7-4 of
2813 Chapter 3 of the MN103E Series Instruction Manual
2816 "When the preceding instruction is a CPU load or
2817 store instruction, a following FPU instruction
2818 cannot be executed until the CPU completes the
2819 latency period even though there are no register
2820 or flag dependencies between them." */
2822 /* Only the AM33-2 (and later) CPUs have FPU instructions. */
2823 if (! TARGET_AM33_2
)
2826 /* If a data dependence already exists then the cost is correct. */
2827 if (REG_NOTE_KIND (link
) == 0)
2830 /* Check that the instruction about to scheduled is an FPU instruction. */
2831 if (GET_MODE_CLASS (GET_MODE (SET_SRC (dep_set
))) != MODE_FLOAT
)
2834 /* Now check to see if the previous instruction is a load or store. */
2835 if (! set_is_load_p (insn_set
) && ! set_is_store_p (insn_set
))
2838 /* XXX: Verify: The text of 1-7-4 implies that the restriction
2839 only applies when an INTEGER load/store precedes an FPU
2840 instruction, but is this true ? For now we assume that it is. */
2841 if (GET_MODE_CLASS (GET_MODE (SET_SRC (insn_set
))) != MODE_INT
)
2844 /* Extract the latency value from the timings attribute. */
2845 timings
= get_attr_timings (insn
);
2846 return timings
< 100 ? (timings
% 10) : (timings
% 100);
2850 mn10300_conditional_register_usage (void)
2856 for (i
= FIRST_EXTENDED_REGNUM
;
2857 i
<= LAST_EXTENDED_REGNUM
; i
++)
2858 fixed_regs
[i
] = call_used_regs
[i
] = 1;
2862 for (i
= FIRST_FP_REGNUM
;
2863 i
<= LAST_FP_REGNUM
; i
++)
2864 fixed_regs
[i
] = call_used_regs
[i
] = 1;
2867 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
] =
2868 call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
2871 /* Worker function for TARGET_MD_ASM_CLOBBERS.
2872 We do this in the mn10300 backend to maintain source compatibility
2873 with the old cc0-based compiler. */
2876 mn10300_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED
,
2877 tree inputs ATTRIBUTE_UNUSED
,
2880 clobbers
= tree_cons (NULL_TREE
, build_string (5, "EPSW"),
2885 /* A helper function for splitting cbranch patterns after reload. */
2888 mn10300_split_cbranch (machine_mode cmp_mode
, rtx cmp_op
, rtx label_ref
)
2892 flags
= gen_rtx_REG (cmp_mode
, CC_REG
);
2893 x
= gen_rtx_COMPARE (cmp_mode
, XEXP (cmp_op
, 0), XEXP (cmp_op
, 1));
2894 x
= gen_rtx_SET (VOIDmode
, flags
, x
);
2897 x
= gen_rtx_fmt_ee (GET_CODE (cmp_op
), VOIDmode
, flags
, const0_rtx
);
2898 x
= gen_rtx_IF_THEN_ELSE (VOIDmode
, x
, label_ref
, pc_rtx
);
2899 x
= gen_rtx_SET (VOIDmode
, pc_rtx
, x
);
2903 /* A helper function for matching parallels that set the flags. */
2906 mn10300_match_ccmode (rtx insn
, machine_mode cc_mode
)
2909 machine_mode flags_mode
;
2911 gcc_checking_assert (XVECLEN (PATTERN (insn
), 0) == 2);
2913 op1
= XVECEXP (PATTERN (insn
), 0, 1);
2914 gcc_checking_assert (GET_CODE (SET_SRC (op1
)) == COMPARE
);
2916 flags
= SET_DEST (op1
);
2917 flags_mode
= GET_MODE (flags
);
2919 if (GET_MODE (SET_SRC (op1
)) != flags_mode
)
2921 if (GET_MODE_CLASS (flags_mode
) != MODE_CC
)
2924 /* Ensure that the mode of FLAGS is compatible with CC_MODE. */
2925 if (cc_flags_for_mode (flags_mode
) & ~cc_flags_for_mode (cc_mode
))
2931 /* This function is used to help split:
2933 (set (reg) (and (reg) (int)))
2937 (set (reg) (shift (reg) (int))
2938 (set (reg) (shift (reg) (int))
2940 where the shitfs will be shorter than the "and" insn.
2942 It returns the number of bits that should be shifted. A positive
2943 values means that the low bits are to be cleared (and hence the
2944 shifts should be right followed by left) whereas a negative value
2945 means that the high bits are to be cleared (left followed by right).
2946 Zero is returned when it would not be economical to split the AND. */
2949 mn10300_split_and_operand_count (rtx op
)
2951 HOST_WIDE_INT val
= INTVAL (op
);
2956 /* High bit is set, look for bits clear at the bottom. */
2957 count
= exact_log2 (-val
);
2960 /* This is only size win if we can use the asl2 insn. Otherwise we
2961 would be replacing 1 6-byte insn with 2 3-byte insns. */
2962 if (count
> (optimize_insn_for_speed_p () ? 2 : 4))
2968 /* High bit is clear, look for bits set at the bottom. */
2969 count
= exact_log2 (val
+ 1);
2971 /* Again, this is only a size win with asl2. */
2972 if (count
> (optimize_insn_for_speed_p () ? 2 : 4))
2981 enum attr_liw_op op
;
2986 /* Decide if the given insn is a candidate for LIW bundling. If it is then
2987 extract the operands and LIW attributes from the insn and use them to fill
2988 in the liw_data structure. Return true upon success or false if the insn
2989 cannot be bundled. */
2992 extract_bundle (rtx_insn
*insn
, struct liw_data
* pdata
)
2994 bool allow_consts
= true;
2997 gcc_assert (pdata
!= NULL
);
3001 /* Make sure that we are dealing with a simple SET insn. */
3002 p
= single_set (insn
);
3006 /* Make sure that it could go into one of the LIW pipelines. */
3007 pdata
->slot
= get_attr_liw (insn
);
3008 if (pdata
->slot
== LIW_BOTH
)
3011 pdata
->op
= get_attr_liw_op (insn
);
3016 pdata
->dest
= SET_DEST (p
);
3017 pdata
->src
= SET_SRC (p
);
3020 pdata
->dest
= XEXP (SET_SRC (p
), 0);
3021 pdata
->src
= XEXP (SET_SRC (p
), 1);
3028 /* The AND, OR and XOR long instruction words only accept register arguments. */
3029 allow_consts
= false;
3032 pdata
->dest
= SET_DEST (p
);
3033 pdata
->src
= XEXP (SET_SRC (p
), 1);
3037 if (! REG_P (pdata
->dest
))
3040 if (REG_P (pdata
->src
))
3043 return allow_consts
&& satisfies_constraint_O (pdata
->src
);
3046 /* Make sure that it is OK to execute LIW1 and LIW2 in parallel. GCC generated
3047 the instructions with the assumption that LIW1 would be executed before LIW2
3048 so we must check for overlaps between their sources and destinations. */
3051 check_liw_constraints (struct liw_data
* pliw1
, struct liw_data
* pliw2
)
3053 /* Check for slot conflicts. */
3054 if (pliw2
->slot
== pliw1
->slot
&& pliw1
->slot
!= LIW_EITHER
)
3057 /* If either operation is a compare, then "dest" is really an input; the real
3058 destination is CC_REG. So these instructions need different checks. */
3060 /* Changing "CMP ; OP" into "CMP | OP" is OK because the comparison will
3061 check its values prior to any changes made by OP. */
3062 if (pliw1
->op
== LIW_OP_CMP
)
3064 /* Two sequential comparisons means dead code, which ought to
3065 have been eliminated given that bundling only happens with
3066 optimization. We cannot bundle them in any case. */
3067 gcc_assert (pliw1
->op
!= pliw2
->op
);
3071 /* Changing "OP ; CMP" into "OP | CMP" does not work if the value being compared
3072 is the destination of OP, as the CMP will look at the old value, not the new
3074 if (pliw2
->op
== LIW_OP_CMP
)
3076 if (REGNO (pliw2
->dest
) == REGNO (pliw1
->dest
))
3079 if (REG_P (pliw2
->src
))
3080 return REGNO (pliw2
->src
) != REGNO (pliw1
->dest
);
3085 /* Changing "OP1 ; OP2" into "OP1 | OP2" does not work if they both write to the
3086 same destination register. */
3087 if (REGNO (pliw2
->dest
) == REGNO (pliw1
->dest
))
3090 /* Changing "OP1 ; OP2" into "OP1 | OP2" generally does not work if the destination
3091 of OP1 is the source of OP2. The exception is when OP1 is a MOVE instruction when
3092 we can replace the source in OP2 with the source of OP1. */
3093 if (REG_P (pliw2
->src
) && REGNO (pliw2
->src
) == REGNO (pliw1
->dest
))
3095 if (pliw1
->op
== LIW_OP_MOV
&& REG_P (pliw1
->src
))
3097 if (! REG_P (pliw1
->src
)
3098 && (pliw2
->op
== LIW_OP_AND
3099 || pliw2
->op
== LIW_OP_OR
3100 || pliw2
->op
== LIW_OP_XOR
))
3103 pliw2
->src
= pliw1
->src
;
3109 /* Everything else is OK. */
3113 /* Combine pairs of insns into LIW bundles. */
3116 mn10300_bundle_liw (void)
3120 for (r
= get_insns (); r
!= NULL
; r
= next_nonnote_nondebug_insn (r
))
3122 rtx_insn
*insn1
, *insn2
;
3123 struct liw_data liw1
, liw2
;
3126 if (! extract_bundle (insn1
, & liw1
))
3129 insn2
= next_nonnote_nondebug_insn (insn1
);
3130 if (! extract_bundle (insn2
, & liw2
))
3133 /* Check for source/destination overlap. */
3134 if (! check_liw_constraints (& liw1
, & liw2
))
3137 if (liw1
.slot
== LIW_OP2
|| liw2
.slot
== LIW_OP1
)
3139 struct liw_data temp
;
3146 delete_insn (insn2
);
3149 if (liw1
.op
== LIW_OP_CMP
)
3150 insn2_pat
= gen_cmp_liw (liw2
.dest
, liw2
.src
, liw1
.dest
, liw1
.src
,
3152 else if (liw2
.op
== LIW_OP_CMP
)
3153 insn2_pat
= gen_liw_cmp (liw1
.dest
, liw1
.src
, liw2
.dest
, liw2
.src
,
3156 insn2_pat
= gen_liw (liw1
.dest
, liw2
.dest
, liw1
.src
, liw2
.src
,
3157 GEN_INT (liw1
.op
), GEN_INT (liw2
.op
));
3159 insn2
= emit_insn_after (insn2_pat
, insn1
);
3160 delete_insn (insn1
);
3165 #define DUMP(reason, insn) \
3170 fprintf (dump_file, reason "\n"); \
3171 if (insn != NULL_RTX) \
3172 print_rtl_single (dump_file, insn); \
3173 fprintf(dump_file, "\n"); \
3178 /* Replace the BRANCH insn with a Lcc insn that goes to LABEL.
3179 Insert a SETLB insn just before LABEL. */
3182 mn10300_insert_setlb_lcc (rtx label
, rtx branch
)
3184 rtx lcc
, comparison
, cmp_reg
;
3186 if (LABEL_NUSES (label
) > 1)
3190 /* This label is used both as an entry point to the loop
3191 and as a loop-back point for the loop. We need to separate
3192 these two functions so that the SETLB happens upon entry,
3193 but the loop-back does not go to the SETLB instruction. */
3194 DUMP ("Inserting SETLB insn after:", label
);
3195 insn
= emit_insn_after (gen_setlb (), label
);
3196 label
= gen_label_rtx ();
3197 emit_label_after (label
, insn
);
3198 DUMP ("Created new loop-back label:", label
);
3202 DUMP ("Inserting SETLB insn before:", label
);
3203 emit_insn_before (gen_setlb (), label
);
3206 comparison
= XEXP (SET_SRC (PATTERN (branch
)), 0);
3207 cmp_reg
= XEXP (comparison
, 0);
3208 gcc_assert (REG_P (cmp_reg
));
3210 /* If the comparison has not already been split out of the branch
3212 gcc_assert (REGNO (cmp_reg
) == CC_REG
);
3214 if (GET_MODE (cmp_reg
) == CC_FLOATmode
)
3215 lcc
= gen_FLcc (comparison
, label
);
3217 lcc
= gen_Lcc (comparison
, label
);
3219 rtx_insn
*jump
= emit_jump_insn_before (lcc
, branch
);
3220 mark_jump_label (XVECEXP (PATTERN (lcc
), 0, 0), jump
, 0);
3221 JUMP_LABEL (jump
) = label
;
3222 DUMP ("Replacing branch insn...", branch
);
3223 DUMP ("... with Lcc insn:", jump
);
3224 delete_insn (branch
);
3228 mn10300_block_contains_call (basic_block block
)
3232 FOR_BB_INSNS (block
, insn
)
3240 mn10300_loop_contains_call_insn (loop_p loop
)
3243 bool result
= false;
3246 bbs
= get_loop_body (loop
);
3248 for (i
= 0; i
< loop
->num_nodes
; i
++)
3249 if (mn10300_block_contains_call (bbs
[i
]))
3260 mn10300_scan_for_setlb_lcc (void)
3264 DUMP ("Looking for loops that can use the SETLB insn", NULL_RTX
);
3267 compute_bb_for_insn ();
3269 /* Find the loops. */
3270 loop_optimizer_init (AVOID_CFG_MODIFICATIONS
);
3272 /* FIXME: For now we only investigate innermost loops. In practice however
3273 if an inner loop is not suitable for use with the SETLB/Lcc insns, it may
3274 be the case that its parent loop is suitable. Thus we should check all
3275 loops, but work from the innermost outwards. */
3276 FOR_EACH_LOOP (loop
, LI_ONLY_INNERMOST
)
3278 const char * reason
= NULL
;
3280 /* Check to see if we can modify this loop. If we cannot
3281 then set 'reason' to describe why it could not be done. */
3282 if (loop
->latch
== NULL
)
3283 reason
= "it contains multiple latches";
3284 else if (loop
->header
!= loop
->latch
)
3285 /* FIXME: We could handle loops that span multiple blocks,
3286 but this requires a lot more work tracking down the branches
3287 that need altering, so for now keep things simple. */
3288 reason
= "the loop spans multiple blocks";
3289 else if (mn10300_loop_contains_call_insn (loop
))
3290 reason
= "it contains CALL insns";
3293 rtx_insn
*branch
= BB_END (loop
->latch
);
3295 gcc_assert (JUMP_P (branch
));
3296 if (single_set (branch
) == NULL_RTX
|| ! any_condjump_p (branch
))
3297 /* We cannot optimize tablejumps and the like. */
3298 /* FIXME: We could handle unconditional jumps. */
3299 reason
= "it is not a simple loop";
3305 flow_loop_dump (loop
, dump_file
, NULL
, 0);
3307 label
= BB_HEAD (loop
->header
);
3308 gcc_assert (LABEL_P (label
));
3310 mn10300_insert_setlb_lcc (label
, branch
);
3314 if (dump_file
&& reason
!= NULL
)
3315 fprintf (dump_file
, "Loop starting with insn %d is not suitable because %s\n",
3316 INSN_UID (BB_HEAD (loop
->header
)),
3320 loop_optimizer_finalize ();
3322 df_finish_pass (false);
3324 DUMP ("SETLB scan complete", NULL_RTX
);
3328 mn10300_reorg (void)
3330 /* These are optimizations, so only run them if optimizing. */
3331 if (TARGET_AM33
&& (optimize
> 0 || optimize_size
))
3333 if (TARGET_ALLOW_SETLB
)
3334 mn10300_scan_for_setlb_lcc ();
3336 if (TARGET_ALLOW_LIW
)
3337 mn10300_bundle_liw ();
3341 /* Initialize the GCC target structure. */
3343 #undef TARGET_MACHINE_DEPENDENT_REORG
3344 #define TARGET_MACHINE_DEPENDENT_REORG mn10300_reorg
3346 #undef TARGET_ASM_ALIGNED_HI_OP
3347 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
3349 #undef TARGET_LEGITIMIZE_ADDRESS
3350 #define TARGET_LEGITIMIZE_ADDRESS mn10300_legitimize_address
3352 #undef TARGET_ADDRESS_COST
3353 #define TARGET_ADDRESS_COST mn10300_address_cost
3354 #undef TARGET_REGISTER_MOVE_COST
3355 #define TARGET_REGISTER_MOVE_COST mn10300_register_move_cost
3356 #undef TARGET_MEMORY_MOVE_COST
3357 #define TARGET_MEMORY_MOVE_COST mn10300_memory_move_cost
3358 #undef TARGET_RTX_COSTS
3359 #define TARGET_RTX_COSTS mn10300_rtx_costs
3361 #undef TARGET_ASM_FILE_START
3362 #define TARGET_ASM_FILE_START mn10300_file_start
3363 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
3364 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
3366 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
3367 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA mn10300_asm_output_addr_const_extra
3369 #undef TARGET_OPTION_OVERRIDE
3370 #define TARGET_OPTION_OVERRIDE mn10300_option_override
3372 #undef TARGET_ENCODE_SECTION_INFO
3373 #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info
3375 #undef TARGET_PROMOTE_PROTOTYPES
3376 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
3377 #undef TARGET_RETURN_IN_MEMORY
3378 #define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory
3379 #undef TARGET_PASS_BY_REFERENCE
3380 #define TARGET_PASS_BY_REFERENCE mn10300_pass_by_reference
3381 #undef TARGET_CALLEE_COPIES
3382 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
3383 #undef TARGET_ARG_PARTIAL_BYTES
3384 #define TARGET_ARG_PARTIAL_BYTES mn10300_arg_partial_bytes
3385 #undef TARGET_FUNCTION_ARG
3386 #define TARGET_FUNCTION_ARG mn10300_function_arg
3387 #undef TARGET_FUNCTION_ARG_ADVANCE
3388 #define TARGET_FUNCTION_ARG_ADVANCE mn10300_function_arg_advance
3390 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
3391 #define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs
3392 #undef TARGET_EXPAND_BUILTIN_VA_START
3393 #define TARGET_EXPAND_BUILTIN_VA_START mn10300_va_start
3395 #undef TARGET_CASE_VALUES_THRESHOLD
3396 #define TARGET_CASE_VALUES_THRESHOLD mn10300_case_values_threshold
3398 #undef TARGET_LEGITIMATE_ADDRESS_P
3399 #define TARGET_LEGITIMATE_ADDRESS_P mn10300_legitimate_address_p
3400 #undef TARGET_DELEGITIMIZE_ADDRESS
3401 #define TARGET_DELEGITIMIZE_ADDRESS mn10300_delegitimize_address
3402 #undef TARGET_LEGITIMATE_CONSTANT_P
3403 #define TARGET_LEGITIMATE_CONSTANT_P mn10300_legitimate_constant_p
3405 #undef TARGET_PREFERRED_RELOAD_CLASS
3406 #define TARGET_PREFERRED_RELOAD_CLASS mn10300_preferred_reload_class
3407 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
3408 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS \
3409 mn10300_preferred_output_reload_class
3410 #undef TARGET_SECONDARY_RELOAD
3411 #define TARGET_SECONDARY_RELOAD mn10300_secondary_reload
3413 #undef TARGET_TRAMPOLINE_INIT
3414 #define TARGET_TRAMPOLINE_INIT mn10300_trampoline_init
3416 #undef TARGET_FUNCTION_VALUE
3417 #define TARGET_FUNCTION_VALUE mn10300_function_value
3418 #undef TARGET_LIBCALL_VALUE
3419 #define TARGET_LIBCALL_VALUE mn10300_libcall_value
3421 #undef TARGET_ASM_OUTPUT_MI_THUNK
3422 #define TARGET_ASM_OUTPUT_MI_THUNK mn10300_asm_output_mi_thunk
3423 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
3424 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK mn10300_can_output_mi_thunk
3426 #undef TARGET_SCHED_ADJUST_COST
3427 #define TARGET_SCHED_ADJUST_COST mn10300_adjust_sched_cost
3429 #undef TARGET_CONDITIONAL_REGISTER_USAGE
3430 #define TARGET_CONDITIONAL_REGISTER_USAGE mn10300_conditional_register_usage
3432 #undef TARGET_MD_ASM_CLOBBERS
3433 #define TARGET_MD_ASM_CLOBBERS mn10300_md_asm_clobbers
3435 #undef TARGET_FLAGS_REGNUM
3436 #define TARGET_FLAGS_REGNUM CC_REG
3438 struct gcc_target targetm
= TARGET_INITIALIZER
;