1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987-2018 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
36 #include "diagnostic-core.h"
37 #include "fold-const.h"
38 #include "stor-layout.h"
42 #include "langhooks.h"
43 #include "tree-vector-builder.h"
45 struct target_expmed default_target_expmed
;
47 struct target_expmed
*this_target_expmed
= &default_target_expmed
;
50 static bool store_integral_bit_field (rtx
, opt_scalar_int_mode
,
51 unsigned HOST_WIDE_INT
,
52 unsigned HOST_WIDE_INT
,
53 poly_uint64
, poly_uint64
,
54 machine_mode
, rtx
, bool, bool);
55 static void store_fixed_bit_field (rtx
, opt_scalar_int_mode
,
56 unsigned HOST_WIDE_INT
,
57 unsigned HOST_WIDE_INT
,
58 poly_uint64
, poly_uint64
,
59 rtx
, scalar_int_mode
, bool);
60 static void store_fixed_bit_field_1 (rtx
, scalar_int_mode
,
61 unsigned HOST_WIDE_INT
,
62 unsigned HOST_WIDE_INT
,
63 rtx
, scalar_int_mode
, bool);
64 static void store_split_bit_field (rtx
, opt_scalar_int_mode
,
65 unsigned HOST_WIDE_INT
,
66 unsigned HOST_WIDE_INT
,
67 poly_uint64
, poly_uint64
,
68 rtx
, scalar_int_mode
, bool);
69 static rtx
extract_integral_bit_field (rtx
, opt_scalar_int_mode
,
70 unsigned HOST_WIDE_INT
,
71 unsigned HOST_WIDE_INT
, int, rtx
,
72 machine_mode
, machine_mode
, bool, bool);
73 static rtx
extract_fixed_bit_field (machine_mode
, rtx
, opt_scalar_int_mode
,
74 unsigned HOST_WIDE_INT
,
75 unsigned HOST_WIDE_INT
, rtx
, int, bool);
76 static rtx
extract_fixed_bit_field_1 (machine_mode
, rtx
, scalar_int_mode
,
77 unsigned HOST_WIDE_INT
,
78 unsigned HOST_WIDE_INT
, rtx
, int, bool);
79 static rtx
lshift_value (machine_mode
, unsigned HOST_WIDE_INT
, int);
80 static rtx
extract_split_bit_field (rtx
, opt_scalar_int_mode
,
81 unsigned HOST_WIDE_INT
,
82 unsigned HOST_WIDE_INT
, int, bool);
83 static void do_cmp_and_jump (rtx
, rtx
, enum rtx_code
, machine_mode
, rtx_code_label
*);
84 static rtx
expand_smod_pow2 (scalar_int_mode
, rtx
, HOST_WIDE_INT
);
85 static rtx
expand_sdiv_pow2 (scalar_int_mode
, rtx
, HOST_WIDE_INT
);
87 /* Return a constant integer mask value of mode MODE with BITSIZE ones
88 followed by BITPOS zeros, or the complement of that if COMPLEMENT.
89 The mask is truncated if necessary to the width of mode MODE. The
90 mask is zero-extended if BITSIZE+BITPOS is too small for MODE. */
93 mask_rtx (scalar_int_mode mode
, int bitpos
, int bitsize
, bool complement
)
95 return immed_wide_int_const
96 (wi::shifted_mask (bitpos
, bitsize
, complement
,
97 GET_MODE_PRECISION (mode
)), mode
);
100 /* Test whether a value is zero of a power of two. */
101 #define EXACT_POWER_OF_2_OR_ZERO_P(x) \
102 (((x) & ((x) - HOST_WIDE_INT_1U)) == 0)
104 struct init_expmed_rtl
125 rtx pow2
[MAX_BITS_PER_WORD
];
126 rtx cint
[MAX_BITS_PER_WORD
];
130 init_expmed_one_conv (struct init_expmed_rtl
*all
, scalar_int_mode to_mode
,
131 scalar_int_mode from_mode
, bool speed
)
133 int to_size
, from_size
;
136 to_size
= GET_MODE_PRECISION (to_mode
);
137 from_size
= GET_MODE_PRECISION (from_mode
);
139 /* Most partial integers have a precision less than the "full"
140 integer it requires for storage. In case one doesn't, for
141 comparison purposes here, reduce the bit size by one in that
143 if (GET_MODE_CLASS (to_mode
) == MODE_PARTIAL_INT
144 && pow2p_hwi (to_size
))
146 if (GET_MODE_CLASS (from_mode
) == MODE_PARTIAL_INT
147 && pow2p_hwi (from_size
))
150 /* Assume cost of zero-extend and sign-extend is the same. */
151 which
= (to_size
< from_size
? all
->trunc
: all
->zext
);
153 PUT_MODE (all
->reg
, from_mode
);
154 set_convert_cost (to_mode
, from_mode
, speed
,
155 set_src_cost (which
, to_mode
, speed
));
159 init_expmed_one_mode (struct init_expmed_rtl
*all
,
160 machine_mode mode
, int speed
)
162 int m
, n
, mode_bitsize
;
163 machine_mode mode_from
;
165 mode_bitsize
= GET_MODE_UNIT_BITSIZE (mode
);
167 PUT_MODE (all
->reg
, mode
);
168 PUT_MODE (all
->plus
, mode
);
169 PUT_MODE (all
->neg
, mode
);
170 PUT_MODE (all
->mult
, mode
);
171 PUT_MODE (all
->sdiv
, mode
);
172 PUT_MODE (all
->udiv
, mode
);
173 PUT_MODE (all
->sdiv_32
, mode
);
174 PUT_MODE (all
->smod_32
, mode
);
175 PUT_MODE (all
->wide_trunc
, mode
);
176 PUT_MODE (all
->shift
, mode
);
177 PUT_MODE (all
->shift_mult
, mode
);
178 PUT_MODE (all
->shift_add
, mode
);
179 PUT_MODE (all
->shift_sub0
, mode
);
180 PUT_MODE (all
->shift_sub1
, mode
);
181 PUT_MODE (all
->zext
, mode
);
182 PUT_MODE (all
->trunc
, mode
);
184 set_add_cost (speed
, mode
, set_src_cost (all
->plus
, mode
, speed
));
185 set_neg_cost (speed
, mode
, set_src_cost (all
->neg
, mode
, speed
));
186 set_mul_cost (speed
, mode
, set_src_cost (all
->mult
, mode
, speed
));
187 set_sdiv_cost (speed
, mode
, set_src_cost (all
->sdiv
, mode
, speed
));
188 set_udiv_cost (speed
, mode
, set_src_cost (all
->udiv
, mode
, speed
));
190 set_sdiv_pow2_cheap (speed
, mode
, (set_src_cost (all
->sdiv_32
, mode
, speed
)
191 <= 2 * add_cost (speed
, mode
)));
192 set_smod_pow2_cheap (speed
, mode
, (set_src_cost (all
->smod_32
, mode
, speed
)
193 <= 4 * add_cost (speed
, mode
)));
195 set_shift_cost (speed
, mode
, 0, 0);
197 int cost
= add_cost (speed
, mode
);
198 set_shiftadd_cost (speed
, mode
, 0, cost
);
199 set_shiftsub0_cost (speed
, mode
, 0, cost
);
200 set_shiftsub1_cost (speed
, mode
, 0, cost
);
203 n
= MIN (MAX_BITS_PER_WORD
, mode_bitsize
);
204 for (m
= 1; m
< n
; m
++)
206 XEXP (all
->shift
, 1) = all
->cint
[m
];
207 XEXP (all
->shift_mult
, 1) = all
->pow2
[m
];
209 set_shift_cost (speed
, mode
, m
, set_src_cost (all
->shift
, mode
, speed
));
210 set_shiftadd_cost (speed
, mode
, m
, set_src_cost (all
->shift_add
, mode
,
212 set_shiftsub0_cost (speed
, mode
, m
, set_src_cost (all
->shift_sub0
, mode
,
214 set_shiftsub1_cost (speed
, mode
, m
, set_src_cost (all
->shift_sub1
, mode
,
218 scalar_int_mode int_mode_to
;
219 if (is_a
<scalar_int_mode
> (mode
, &int_mode_to
))
221 for (mode_from
= MIN_MODE_INT
; mode_from
<= MAX_MODE_INT
;
222 mode_from
= (machine_mode
)(mode_from
+ 1))
223 init_expmed_one_conv (all
, int_mode_to
,
224 as_a
<scalar_int_mode
> (mode_from
), speed
);
226 scalar_int_mode wider_mode
;
227 if (GET_MODE_CLASS (int_mode_to
) == MODE_INT
228 && GET_MODE_WIDER_MODE (int_mode_to
).exists (&wider_mode
))
230 PUT_MODE (all
->zext
, wider_mode
);
231 PUT_MODE (all
->wide_mult
, wider_mode
);
232 PUT_MODE (all
->wide_lshr
, wider_mode
);
233 XEXP (all
->wide_lshr
, 1)
234 = gen_int_shift_amount (wider_mode
, mode_bitsize
);
236 set_mul_widen_cost (speed
, wider_mode
,
237 set_src_cost (all
->wide_mult
, wider_mode
, speed
));
238 set_mul_highpart_cost (speed
, int_mode_to
,
239 set_src_cost (all
->wide_trunc
,
240 int_mode_to
, speed
));
248 struct init_expmed_rtl all
;
249 machine_mode mode
= QImode
;
252 memset (&all
, 0, sizeof all
);
253 for (m
= 1; m
< MAX_BITS_PER_WORD
; m
++)
255 all
.pow2
[m
] = GEN_INT (HOST_WIDE_INT_1
<< m
);
256 all
.cint
[m
] = GEN_INT (m
);
259 /* Avoid using hard regs in ways which may be unsupported. */
260 all
.reg
= gen_raw_REG (mode
, LAST_VIRTUAL_REGISTER
+ 1);
261 all
.plus
= gen_rtx_PLUS (mode
, all
.reg
, all
.reg
);
262 all
.neg
= gen_rtx_NEG (mode
, all
.reg
);
263 all
.mult
= gen_rtx_MULT (mode
, all
.reg
, all
.reg
);
264 all
.sdiv
= gen_rtx_DIV (mode
, all
.reg
, all
.reg
);
265 all
.udiv
= gen_rtx_UDIV (mode
, all
.reg
, all
.reg
);
266 all
.sdiv_32
= gen_rtx_DIV (mode
, all
.reg
, all
.pow2
[5]);
267 all
.smod_32
= gen_rtx_MOD (mode
, all
.reg
, all
.pow2
[5]);
268 all
.zext
= gen_rtx_ZERO_EXTEND (mode
, all
.reg
);
269 all
.wide_mult
= gen_rtx_MULT (mode
, all
.zext
, all
.zext
);
270 all
.wide_lshr
= gen_rtx_LSHIFTRT (mode
, all
.wide_mult
, all
.reg
);
271 all
.wide_trunc
= gen_rtx_TRUNCATE (mode
, all
.wide_lshr
);
272 all
.shift
= gen_rtx_ASHIFT (mode
, all
.reg
, all
.reg
);
273 all
.shift_mult
= gen_rtx_MULT (mode
, all
.reg
, all
.reg
);
274 all
.shift_add
= gen_rtx_PLUS (mode
, all
.shift_mult
, all
.reg
);
275 all
.shift_sub0
= gen_rtx_MINUS (mode
, all
.shift_mult
, all
.reg
);
276 all
.shift_sub1
= gen_rtx_MINUS (mode
, all
.reg
, all
.shift_mult
);
277 all
.trunc
= gen_rtx_TRUNCATE (mode
, all
.reg
);
279 for (speed
= 0; speed
< 2; speed
++)
281 crtl
->maybe_hot_insn_p
= speed
;
282 set_zero_cost (speed
, set_src_cost (const0_rtx
, mode
, speed
));
284 for (mode
= MIN_MODE_INT
; mode
<= MAX_MODE_INT
;
285 mode
= (machine_mode
)(mode
+ 1))
286 init_expmed_one_mode (&all
, mode
, speed
);
288 if (MIN_MODE_PARTIAL_INT
!= VOIDmode
)
289 for (mode
= MIN_MODE_PARTIAL_INT
; mode
<= MAX_MODE_PARTIAL_INT
;
290 mode
= (machine_mode
)(mode
+ 1))
291 init_expmed_one_mode (&all
, mode
, speed
);
293 if (MIN_MODE_VECTOR_INT
!= VOIDmode
)
294 for (mode
= MIN_MODE_VECTOR_INT
; mode
<= MAX_MODE_VECTOR_INT
;
295 mode
= (machine_mode
)(mode
+ 1))
296 init_expmed_one_mode (&all
, mode
, speed
);
299 if (alg_hash_used_p ())
301 struct alg_hash_entry
*p
= alg_hash_entry_ptr (0);
302 memset (p
, 0, sizeof (*p
) * NUM_ALG_HASH_ENTRIES
);
305 set_alg_hash_used_p (true);
306 default_rtl_profile ();
308 ggc_free (all
.trunc
);
309 ggc_free (all
.shift_sub1
);
310 ggc_free (all
.shift_sub0
);
311 ggc_free (all
.shift_add
);
312 ggc_free (all
.shift_mult
);
313 ggc_free (all
.shift
);
314 ggc_free (all
.wide_trunc
);
315 ggc_free (all
.wide_lshr
);
316 ggc_free (all
.wide_mult
);
318 ggc_free (all
.smod_32
);
319 ggc_free (all
.sdiv_32
);
328 /* Return an rtx representing minus the value of X.
329 MODE is the intended mode of the result,
330 useful if X is a CONST_INT. */
333 negate_rtx (machine_mode mode
, rtx x
)
335 rtx result
= simplify_unary_operation (NEG
, mode
, x
, mode
);
338 result
= expand_unop (mode
, neg_optab
, x
, NULL_RTX
, 0);
343 /* Whether reverse storage order is supported on the target. */
344 static int reverse_storage_order_supported
= -1;
346 /* Check whether reverse storage order is supported on the target. */
349 check_reverse_storage_order_support (void)
351 if (BYTES_BIG_ENDIAN
!= WORDS_BIG_ENDIAN
)
353 reverse_storage_order_supported
= 0;
354 sorry ("reverse scalar storage order");
357 reverse_storage_order_supported
= 1;
360 /* Whether reverse FP storage order is supported on the target. */
361 static int reverse_float_storage_order_supported
= -1;
363 /* Check whether reverse FP storage order is supported on the target. */
366 check_reverse_float_storage_order_support (void)
368 if (FLOAT_WORDS_BIG_ENDIAN
!= WORDS_BIG_ENDIAN
)
370 reverse_float_storage_order_supported
= 0;
371 sorry ("reverse floating-point scalar storage order");
374 reverse_float_storage_order_supported
= 1;
377 /* Return an rtx representing value of X with reverse storage order.
378 MODE is the intended mode of the result,
379 useful if X is a CONST_INT. */
382 flip_storage_order (machine_mode mode
, rtx x
)
384 scalar_int_mode int_mode
;
390 if (COMPLEX_MODE_P (mode
))
392 rtx real
= read_complex_part (x
, false);
393 rtx imag
= read_complex_part (x
, true);
395 real
= flip_storage_order (GET_MODE_INNER (mode
), real
);
396 imag
= flip_storage_order (GET_MODE_INNER (mode
), imag
);
398 return gen_rtx_CONCAT (mode
, real
, imag
);
401 if (__builtin_expect (reverse_storage_order_supported
< 0, 0))
402 check_reverse_storage_order_support ();
404 if (!is_a
<scalar_int_mode
> (mode
, &int_mode
))
406 if (FLOAT_MODE_P (mode
)
407 && __builtin_expect (reverse_float_storage_order_supported
< 0, 0))
408 check_reverse_float_storage_order_support ();
410 if (!int_mode_for_size (GET_MODE_PRECISION (mode
), 0).exists (&int_mode
))
412 sorry ("reverse storage order for %smode", GET_MODE_NAME (mode
));
415 x
= gen_lowpart (int_mode
, x
);
418 result
= simplify_unary_operation (BSWAP
, int_mode
, x
, int_mode
);
420 result
= expand_unop (int_mode
, bswap_optab
, x
, NULL_RTX
, 1);
422 if (int_mode
!= mode
)
423 result
= gen_lowpart (mode
, result
);
428 /* If MODE is set, adjust bitfield memory MEM so that it points to the
429 first unit of mode MODE that contains a bitfield of size BITSIZE at
430 bit position BITNUM. If MODE is not set, return a BLKmode reference
431 to every byte in the bitfield. Set *NEW_BITNUM to the bit position
432 of the field within the new memory. */
435 narrow_bit_field_mem (rtx mem
, opt_scalar_int_mode mode
,
436 unsigned HOST_WIDE_INT bitsize
,
437 unsigned HOST_WIDE_INT bitnum
,
438 unsigned HOST_WIDE_INT
*new_bitnum
)
440 scalar_int_mode imode
;
441 if (mode
.exists (&imode
))
443 unsigned int unit
= GET_MODE_BITSIZE (imode
);
444 *new_bitnum
= bitnum
% unit
;
445 HOST_WIDE_INT offset
= (bitnum
- *new_bitnum
) / BITS_PER_UNIT
;
446 return adjust_bitfield_address (mem
, imode
, offset
);
450 *new_bitnum
= bitnum
% BITS_PER_UNIT
;
451 HOST_WIDE_INT offset
= bitnum
/ BITS_PER_UNIT
;
452 HOST_WIDE_INT size
= ((*new_bitnum
+ bitsize
+ BITS_PER_UNIT
- 1)
454 return adjust_bitfield_address_size (mem
, BLKmode
, offset
, size
);
458 /* The caller wants to perform insertion or extraction PATTERN on a
459 bitfield of size BITSIZE at BITNUM bits into memory operand OP0.
460 BITREGION_START and BITREGION_END are as for store_bit_field
461 and FIELDMODE is the natural mode of the field.
463 Search for a mode that is compatible with the memory access
464 restrictions and (where applicable) with a register insertion or
465 extraction. Return the new memory on success, storing the adjusted
466 bit position in *NEW_BITNUM. Return null otherwise. */
469 adjust_bit_field_mem_for_reg (enum extraction_pattern pattern
,
470 rtx op0
, HOST_WIDE_INT bitsize
,
471 HOST_WIDE_INT bitnum
,
472 poly_uint64 bitregion_start
,
473 poly_uint64 bitregion_end
,
474 machine_mode fieldmode
,
475 unsigned HOST_WIDE_INT
*new_bitnum
)
477 bit_field_mode_iterator
iter (bitsize
, bitnum
, bitregion_start
,
478 bitregion_end
, MEM_ALIGN (op0
),
479 MEM_VOLATILE_P (op0
));
480 scalar_int_mode best_mode
;
481 if (iter
.next_mode (&best_mode
))
483 /* We can use a memory in BEST_MODE. See whether this is true for
484 any wider modes. All other things being equal, we prefer to
485 use the widest mode possible because it tends to expose more
486 CSE opportunities. */
487 if (!iter
.prefer_smaller_modes ())
489 /* Limit the search to the mode required by the corresponding
490 register insertion or extraction instruction, if any. */
491 scalar_int_mode limit_mode
= word_mode
;
492 extraction_insn insn
;
493 if (get_best_reg_extraction_insn (&insn
, pattern
,
494 GET_MODE_BITSIZE (best_mode
),
496 limit_mode
= insn
.field_mode
;
498 scalar_int_mode wider_mode
;
499 while (iter
.next_mode (&wider_mode
)
500 && GET_MODE_SIZE (wider_mode
) <= GET_MODE_SIZE (limit_mode
))
501 best_mode
= wider_mode
;
503 return narrow_bit_field_mem (op0
, best_mode
, bitsize
, bitnum
,
509 /* Return true if a bitfield of size BITSIZE at bit number BITNUM within
510 a structure of mode STRUCT_MODE represents a lowpart subreg. The subreg
511 offset is then BITNUM / BITS_PER_UNIT. */
514 lowpart_bit_field_p (poly_uint64 bitnum
, poly_uint64 bitsize
,
515 machine_mode struct_mode
)
517 poly_uint64 regsize
= REGMODE_NATURAL_SIZE (struct_mode
);
518 if (BYTES_BIG_ENDIAN
)
519 return (multiple_p (bitnum
, BITS_PER_UNIT
)
520 && (known_eq (bitnum
+ bitsize
, GET_MODE_BITSIZE (struct_mode
))
521 || multiple_p (bitnum
+ bitsize
,
522 regsize
* BITS_PER_UNIT
)));
524 return multiple_p (bitnum
, regsize
* BITS_PER_UNIT
);
527 /* Return true if -fstrict-volatile-bitfields applies to an access of OP0
528 containing BITSIZE bits starting at BITNUM, with field mode FIELDMODE.
529 Return false if the access would touch memory outside the range
530 BITREGION_START to BITREGION_END for conformance to the C++ memory
534 strict_volatile_bitfield_p (rtx op0
, unsigned HOST_WIDE_INT bitsize
,
535 unsigned HOST_WIDE_INT bitnum
,
536 scalar_int_mode fieldmode
,
537 poly_uint64 bitregion_start
,
538 poly_uint64 bitregion_end
)
540 unsigned HOST_WIDE_INT modesize
= GET_MODE_BITSIZE (fieldmode
);
542 /* -fstrict-volatile-bitfields must be enabled and we must have a
545 || !MEM_VOLATILE_P (op0
)
546 || flag_strict_volatile_bitfields
<= 0)
549 /* The bit size must not be larger than the field mode, and
550 the field mode must not be larger than a word. */
551 if (bitsize
> modesize
|| modesize
> BITS_PER_WORD
)
554 /* Check for cases of unaligned fields that must be split. */
555 if (bitnum
% modesize
+ bitsize
> modesize
)
558 /* The memory must be sufficiently aligned for a MODESIZE access.
559 This condition guarantees, that the memory access will not
560 touch anything after the end of the structure. */
561 if (MEM_ALIGN (op0
) < modesize
)
564 /* Check for cases where the C++ memory model applies. */
565 if (maybe_ne (bitregion_end
, 0U)
566 && (maybe_lt (bitnum
- bitnum
% modesize
, bitregion_start
)
567 || maybe_gt (bitnum
- bitnum
% modesize
+ modesize
- 1,
574 /* Return true if OP is a memory and if a bitfield of size BITSIZE at
575 bit number BITNUM can be treated as a simple value of mode MODE.
576 Store the byte offset in *BYTENUM if so. */
579 simple_mem_bitfield_p (rtx op0
, poly_uint64 bitsize
, poly_uint64 bitnum
,
580 machine_mode mode
, poly_uint64
*bytenum
)
583 && multiple_p (bitnum
, BITS_PER_UNIT
, bytenum
)
584 && known_eq (bitsize
, GET_MODE_BITSIZE (mode
))
585 && (!targetm
.slow_unaligned_access (mode
, MEM_ALIGN (op0
))
586 || (multiple_p (bitnum
, GET_MODE_ALIGNMENT (mode
))
587 && MEM_ALIGN (op0
) >= GET_MODE_ALIGNMENT (mode
))));
590 /* Try to use instruction INSV to store VALUE into a field of OP0.
591 If OP0_MODE is defined, it is the mode of OP0, otherwise OP0 is a
592 BLKmode MEM. VALUE_MODE is the mode of VALUE. BITSIZE and BITNUM
593 are as for store_bit_field. */
596 store_bit_field_using_insv (const extraction_insn
*insv
, rtx op0
,
597 opt_scalar_int_mode op0_mode
,
598 unsigned HOST_WIDE_INT bitsize
,
599 unsigned HOST_WIDE_INT bitnum
,
600 rtx value
, scalar_int_mode value_mode
)
602 struct expand_operand ops
[4];
605 rtx_insn
*last
= get_last_insn ();
606 bool copy_back
= false;
608 scalar_int_mode op_mode
= insv
->field_mode
;
609 unsigned int unit
= GET_MODE_BITSIZE (op_mode
);
610 if (bitsize
== 0 || bitsize
> unit
)
614 /* Get a reference to the first byte of the field. */
615 xop0
= narrow_bit_field_mem (xop0
, insv
->struct_mode
, bitsize
, bitnum
,
619 /* Convert from counting within OP0 to counting in OP_MODE. */
620 if (BYTES_BIG_ENDIAN
)
621 bitnum
+= unit
- GET_MODE_BITSIZE (op0_mode
.require ());
623 /* If xop0 is a register, we need it in OP_MODE
624 to make it acceptable to the format of insv. */
625 if (GET_CODE (xop0
) == SUBREG
)
626 /* We can't just change the mode, because this might clobber op0,
627 and we will need the original value of op0 if insv fails. */
628 xop0
= gen_rtx_SUBREG (op_mode
, SUBREG_REG (xop0
), SUBREG_BYTE (xop0
));
629 if (REG_P (xop0
) && GET_MODE (xop0
) != op_mode
)
630 xop0
= gen_lowpart_SUBREG (op_mode
, xop0
);
633 /* If the destination is a paradoxical subreg such that we need a
634 truncate to the inner mode, perform the insertion on a temporary and
635 truncate the result to the original destination. Note that we can't
636 just truncate the paradoxical subreg as (truncate:N (subreg:W (reg:N
637 X) 0)) is (reg:N X). */
638 if (GET_CODE (xop0
) == SUBREG
639 && REG_P (SUBREG_REG (xop0
))
640 && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (SUBREG_REG (xop0
)),
643 rtx tem
= gen_reg_rtx (op_mode
);
644 emit_move_insn (tem
, xop0
);
649 /* There are similar overflow check at the start of store_bit_field_1,
650 but that only check the situation where the field lies completely
651 outside the register, while there do have situation where the field
652 lies partialy in the register, we need to adjust bitsize for this
653 partial overflow situation. Without this fix, pr48335-2.c on big-endian
654 will broken on those arch support bit insert instruction, like arm, aarch64
656 if (bitsize
+ bitnum
> unit
&& bitnum
< unit
)
658 warning (OPT_Wextra
, "write of %wu-bit data outside the bound of "
659 "destination object, data truncated into %wu-bit",
660 bitsize
, unit
- bitnum
);
661 bitsize
= unit
- bitnum
;
664 /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
665 "backwards" from the size of the unit we are inserting into.
666 Otherwise, we count bits from the most significant on a
667 BYTES/BITS_BIG_ENDIAN machine. */
669 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
670 bitnum
= unit
- bitsize
- bitnum
;
672 /* Convert VALUE to op_mode (which insv insn wants) in VALUE1. */
674 if (value_mode
!= op_mode
)
676 if (GET_MODE_BITSIZE (value_mode
) >= bitsize
)
679 /* Optimization: Don't bother really extending VALUE
680 if it has all the bits we will actually use. However,
681 if we must narrow it, be sure we do it correctly. */
683 if (GET_MODE_SIZE (value_mode
) < GET_MODE_SIZE (op_mode
))
685 tmp
= simplify_subreg (op_mode
, value1
, value_mode
, 0);
687 tmp
= simplify_gen_subreg (op_mode
,
688 force_reg (value_mode
, value1
),
693 tmp
= gen_lowpart_if_possible (op_mode
, value1
);
695 tmp
= gen_lowpart (op_mode
, force_reg (value_mode
, value1
));
699 else if (CONST_INT_P (value
))
700 value1
= gen_int_mode (INTVAL (value
), op_mode
);
702 /* Parse phase is supposed to make VALUE's data type
703 match that of the component reference, which is a type
704 at least as wide as the field; so VALUE should have
705 a mode that corresponds to that type. */
706 gcc_assert (CONSTANT_P (value
));
709 create_fixed_operand (&ops
[0], xop0
);
710 create_integer_operand (&ops
[1], bitsize
);
711 create_integer_operand (&ops
[2], bitnum
);
712 create_input_operand (&ops
[3], value1
, op_mode
);
713 if (maybe_expand_insn (insv
->icode
, 4, ops
))
716 convert_move (op0
, xop0
, true);
719 delete_insns_since (last
);
723 /* A subroutine of store_bit_field, with the same arguments. Return true
724 if the operation could be implemented.
726 If FALLBACK_P is true, fall back to store_fixed_bit_field if we have
727 no other way of implementing the operation. If FALLBACK_P is false,
728 return false instead. */
731 store_bit_field_1 (rtx str_rtx
, poly_uint64 bitsize
, poly_uint64 bitnum
,
732 poly_uint64 bitregion_start
, poly_uint64 bitregion_end
,
733 machine_mode fieldmode
,
734 rtx value
, bool reverse
, bool fallback_p
)
738 while (GET_CODE (op0
) == SUBREG
)
740 bitnum
+= subreg_memory_offset (op0
) * BITS_PER_UNIT
;
741 op0
= SUBREG_REG (op0
);
744 /* No action is needed if the target is a register and if the field
745 lies completely outside that register. This can occur if the source
746 code contains an out-of-bounds access to a small array. */
747 if (REG_P (op0
) && known_ge (bitnum
, GET_MODE_BITSIZE (GET_MODE (op0
))))
750 /* Use vec_set patterns for inserting parts of vectors whenever
752 machine_mode outermode
= GET_MODE (op0
);
753 scalar_mode innermode
= GET_MODE_INNER (outermode
);
755 if (VECTOR_MODE_P (outermode
)
757 && optab_handler (vec_set_optab
, outermode
) != CODE_FOR_nothing
758 && fieldmode
== innermode
759 && known_eq (bitsize
, GET_MODE_BITSIZE (innermode
))
760 && multiple_p (bitnum
, GET_MODE_BITSIZE (innermode
), &pos
))
762 struct expand_operand ops
[3];
763 enum insn_code icode
= optab_handler (vec_set_optab
, outermode
);
765 create_fixed_operand (&ops
[0], op0
);
766 create_input_operand (&ops
[1], value
, innermode
);
767 create_integer_operand (&ops
[2], pos
);
768 if (maybe_expand_insn (icode
, 3, ops
))
772 /* If the target is a register, overwriting the entire object, or storing
773 a full-word or multi-word field can be done with just a SUBREG. */
775 && known_eq (bitsize
, GET_MODE_BITSIZE (fieldmode
)))
777 /* Use the subreg machinery either to narrow OP0 to the required
778 words or to cope with mode punning between equal-sized modes.
779 In the latter case, use subreg on the rhs side, not lhs. */
781 HOST_WIDE_INT regnum
;
782 poly_uint64 regsize
= REGMODE_NATURAL_SIZE (GET_MODE (op0
));
783 if (known_eq (bitnum
, 0U)
784 && known_eq (bitsize
, GET_MODE_BITSIZE (GET_MODE (op0
))))
786 sub
= simplify_gen_subreg (GET_MODE (op0
), value
, fieldmode
, 0);
790 sub
= flip_storage_order (GET_MODE (op0
), sub
);
791 emit_move_insn (op0
, sub
);
795 else if (constant_multiple_p (bitnum
, regsize
* BITS_PER_UNIT
, ®num
)
796 && multiple_p (bitsize
, regsize
* BITS_PER_UNIT
))
798 sub
= simplify_gen_subreg (fieldmode
, op0
, GET_MODE (op0
),
803 value
= flip_storage_order (fieldmode
, value
);
804 emit_move_insn (sub
, value
);
810 /* If the target is memory, storing any naturally aligned field can be
811 done with a simple store. For targets that support fast unaligned
812 memory, any naturally sized, unit aligned field can be done directly. */
814 if (simple_mem_bitfield_p (op0
, bitsize
, bitnum
, fieldmode
, &bytenum
))
816 op0
= adjust_bitfield_address (op0
, fieldmode
, bytenum
);
818 value
= flip_storage_order (fieldmode
, value
);
819 emit_move_insn (op0
, value
);
823 /* It's possible we'll need to handle other cases here for
824 polynomial bitnum and bitsize. */
826 /* From here on we need to be looking at a fixed-size insertion. */
827 unsigned HOST_WIDE_INT ibitsize
= bitsize
.to_constant ();
828 unsigned HOST_WIDE_INT ibitnum
= bitnum
.to_constant ();
830 /* Make sure we are playing with integral modes. Pun with subregs
831 if we aren't. This must come after the entire register case above,
832 since that case is valid for any mode. The following cases are only
833 valid for integral modes. */
834 opt_scalar_int_mode op0_mode
= int_mode_for_mode (GET_MODE (op0
));
835 scalar_int_mode imode
;
836 if (!op0_mode
.exists (&imode
) || imode
!= GET_MODE (op0
))
839 op0
= adjust_bitfield_address_size (op0
, op0_mode
.else_blk (),
842 op0
= gen_lowpart (op0_mode
.require (), op0
);
845 return store_integral_bit_field (op0
, op0_mode
, ibitsize
, ibitnum
,
846 bitregion_start
, bitregion_end
,
847 fieldmode
, value
, reverse
, fallback_p
);
850 /* Subroutine of store_bit_field_1, with the same arguments, except
851 that BITSIZE and BITNUM are constant. Handle cases specific to
852 integral modes. If OP0_MODE is defined, it is the mode of OP0,
853 otherwise OP0 is a BLKmode MEM. */
856 store_integral_bit_field (rtx op0
, opt_scalar_int_mode op0_mode
,
857 unsigned HOST_WIDE_INT bitsize
,
858 unsigned HOST_WIDE_INT bitnum
,
859 poly_uint64 bitregion_start
,
860 poly_uint64 bitregion_end
,
861 machine_mode fieldmode
,
862 rtx value
, bool reverse
, bool fallback_p
)
864 /* Storing an lsb-aligned field in a register
865 can be done with a movstrict instruction. */
869 && lowpart_bit_field_p (bitnum
, bitsize
, op0_mode
.require ())
870 && known_eq (bitsize
, GET_MODE_BITSIZE (fieldmode
))
871 && optab_handler (movstrict_optab
, fieldmode
) != CODE_FOR_nothing
)
873 struct expand_operand ops
[2];
874 enum insn_code icode
= optab_handler (movstrict_optab
, fieldmode
);
876 unsigned HOST_WIDE_INT subreg_off
;
878 if (GET_CODE (arg0
) == SUBREG
)
880 /* Else we've got some float mode source being extracted into
881 a different float mode destination -- this combination of
882 subregs results in Severe Tire Damage. */
883 gcc_assert (GET_MODE (SUBREG_REG (arg0
)) == fieldmode
884 || GET_MODE_CLASS (fieldmode
) == MODE_INT
885 || GET_MODE_CLASS (fieldmode
) == MODE_PARTIAL_INT
);
886 arg0
= SUBREG_REG (arg0
);
889 subreg_off
= bitnum
/ BITS_PER_UNIT
;
890 if (validate_subreg (fieldmode
, GET_MODE (arg0
), arg0
, subreg_off
))
892 arg0
= gen_rtx_SUBREG (fieldmode
, arg0
, subreg_off
);
894 create_fixed_operand (&ops
[0], arg0
);
895 /* Shrink the source operand to FIELDMODE. */
896 create_convert_operand_to (&ops
[1], value
, fieldmode
, false);
897 if (maybe_expand_insn (icode
, 2, ops
))
902 /* Handle fields bigger than a word. */
904 if (bitsize
> BITS_PER_WORD
)
906 /* Here we transfer the words of the field
907 in the order least significant first.
908 This is because the most significant word is the one which may
910 However, only do that if the value is not BLKmode. */
912 const bool backwards
= WORDS_BIG_ENDIAN
&& fieldmode
!= BLKmode
;
913 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
917 /* This is the mode we must force value to, so that there will be enough
918 subwords to extract. Note that fieldmode will often (always?) be
919 VOIDmode, because that is what store_field uses to indicate that this
920 is a bit field, but passing VOIDmode to operand_subword_force
923 The mode must be fixed-size, since insertions into variable-sized
924 objects are meant to be handled before calling this function. */
925 fixed_size_mode value_mode
= as_a
<fixed_size_mode
> (GET_MODE (value
));
926 if (value_mode
== VOIDmode
)
927 value_mode
= smallest_int_mode_for_size (nwords
* BITS_PER_WORD
);
929 last
= get_last_insn ();
930 for (i
= 0; i
< nwords
; i
++)
932 /* If I is 0, use the low-order word in both field and target;
933 if I is 1, use the next to lowest word; and so on. */
934 unsigned int wordnum
= (backwards
935 ? GET_MODE_SIZE (value_mode
) / UNITS_PER_WORD
938 unsigned int bit_offset
= (backwards
^ reverse
939 ? MAX ((int) bitsize
- ((int) i
+ 1)
942 : (int) i
* BITS_PER_WORD
);
943 rtx value_word
= operand_subword_force (value
, wordnum
, value_mode
);
944 unsigned HOST_WIDE_INT new_bitsize
=
945 MIN (BITS_PER_WORD
, bitsize
- i
* BITS_PER_WORD
);
947 /* If the remaining chunk doesn't have full wordsize we have
948 to make sure that for big-endian machines the higher order
950 if (new_bitsize
< BITS_PER_WORD
&& BYTES_BIG_ENDIAN
&& !backwards
)
952 int shift
= BITS_PER_WORD
- new_bitsize
;
953 rtx shift_rtx
= gen_int_shift_amount (word_mode
, shift
);
954 value_word
= simplify_expand_binop (word_mode
, lshr_optab
,
955 value_word
, shift_rtx
,
960 if (!store_bit_field_1 (op0
, new_bitsize
,
962 bitregion_start
, bitregion_end
,
964 value_word
, reverse
, fallback_p
))
966 delete_insns_since (last
);
973 /* If VALUE has a floating-point or complex mode, access it as an
974 integer of the corresponding size. This can occur on a machine
975 with 64 bit registers that uses SFmode for float. It can also
976 occur for unaligned float or complex fields. */
977 rtx orig_value
= value
;
978 scalar_int_mode value_mode
;
979 if (GET_MODE (value
) == VOIDmode
)
980 /* By this point we've dealt with values that are bigger than a word,
981 so word_mode is a conservatively correct choice. */
982 value_mode
= word_mode
;
983 else if (!is_a
<scalar_int_mode
> (GET_MODE (value
), &value_mode
))
985 value_mode
= int_mode_for_mode (GET_MODE (value
)).require ();
986 value
= gen_reg_rtx (value_mode
);
987 emit_move_insn (gen_lowpart (GET_MODE (orig_value
), value
), orig_value
);
990 /* If OP0 is a multi-word register, narrow it to the affected word.
991 If the region spans two words, defer to store_split_bit_field.
992 Don't do this if op0 is a single hard register wider than word
993 such as a float or vector register. */
995 && GET_MODE_SIZE (op0_mode
.require ()) > UNITS_PER_WORD
997 || !HARD_REGISTER_P (op0
)
998 || hard_regno_nregs (REGNO (op0
), op0_mode
.require ()) != 1))
1000 if (bitnum
% BITS_PER_WORD
+ bitsize
> BITS_PER_WORD
)
1005 store_split_bit_field (op0
, op0_mode
, bitsize
, bitnum
,
1006 bitregion_start
, bitregion_end
,
1007 value
, value_mode
, reverse
);
1010 op0
= simplify_gen_subreg (word_mode
, op0
, op0_mode
.require (),
1011 bitnum
/ BITS_PER_WORD
* UNITS_PER_WORD
);
1013 op0_mode
= word_mode
;
1014 bitnum
%= BITS_PER_WORD
;
1017 /* From here on we can assume that the field to be stored in fits
1018 within a word. If the destination is a register, it too fits
1021 extraction_insn insv
;
1024 && get_best_reg_extraction_insn (&insv
, EP_insv
,
1025 GET_MODE_BITSIZE (op0_mode
.require ()),
1027 && store_bit_field_using_insv (&insv
, op0
, op0_mode
,
1028 bitsize
, bitnum
, value
, value_mode
))
1031 /* If OP0 is a memory, try copying it to a register and seeing if a
1032 cheap register alternative is available. */
1033 if (MEM_P (op0
) && !reverse
)
1035 if (get_best_mem_extraction_insn (&insv
, EP_insv
, bitsize
, bitnum
,
1037 && store_bit_field_using_insv (&insv
, op0
, op0_mode
,
1038 bitsize
, bitnum
, value
, value_mode
))
1041 rtx_insn
*last
= get_last_insn ();
1043 /* Try loading part of OP0 into a register, inserting the bitfield
1044 into that, and then copying the result back to OP0. */
1045 unsigned HOST_WIDE_INT bitpos
;
1046 rtx xop0
= adjust_bit_field_mem_for_reg (EP_insv
, op0
, bitsize
, bitnum
,
1047 bitregion_start
, bitregion_end
,
1048 fieldmode
, &bitpos
);
1051 rtx tempreg
= copy_to_reg (xop0
);
1052 if (store_bit_field_1 (tempreg
, bitsize
, bitpos
,
1053 bitregion_start
, bitregion_end
,
1054 fieldmode
, orig_value
, reverse
, false))
1056 emit_move_insn (xop0
, tempreg
);
1059 delete_insns_since (last
);
1066 store_fixed_bit_field (op0
, op0_mode
, bitsize
, bitnum
, bitregion_start
,
1067 bitregion_end
, value
, value_mode
, reverse
);
1071 /* Generate code to store value from rtx VALUE
1072 into a bit-field within structure STR_RTX
1073 containing BITSIZE bits starting at bit BITNUM.
1075 BITREGION_START is bitpos of the first bitfield in this region.
1076 BITREGION_END is the bitpos of the ending bitfield in this region.
1077 These two fields are 0, if the C++ memory model does not apply,
1078 or we are not interested in keeping track of bitfield regions.
1080 FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
1082 If REVERSE is true, the store is to be done in reverse order. */
1085 store_bit_field (rtx str_rtx
, poly_uint64 bitsize
, poly_uint64 bitnum
,
1086 poly_uint64 bitregion_start
, poly_uint64 bitregion_end
,
1087 machine_mode fieldmode
,
1088 rtx value
, bool reverse
)
1090 /* Handle -fstrict-volatile-bitfields in the cases where it applies. */
1091 unsigned HOST_WIDE_INT ibitsize
= 0, ibitnum
= 0;
1092 scalar_int_mode int_mode
;
1093 if (bitsize
.is_constant (&ibitsize
)
1094 && bitnum
.is_constant (&ibitnum
)
1095 && is_a
<scalar_int_mode
> (fieldmode
, &int_mode
)
1096 && strict_volatile_bitfield_p (str_rtx
, ibitsize
, ibitnum
, int_mode
,
1097 bitregion_start
, bitregion_end
))
1099 /* Storing of a full word can be done with a simple store.
1100 We know here that the field can be accessed with one single
1101 instruction. For targets that support unaligned memory,
1102 an unaligned access may be necessary. */
1103 if (ibitsize
== GET_MODE_BITSIZE (int_mode
))
1105 str_rtx
= adjust_bitfield_address (str_rtx
, int_mode
,
1106 ibitnum
/ BITS_PER_UNIT
);
1108 value
= flip_storage_order (int_mode
, value
);
1109 gcc_assert (ibitnum
% BITS_PER_UNIT
== 0);
1110 emit_move_insn (str_rtx
, value
);
1116 str_rtx
= narrow_bit_field_mem (str_rtx
, int_mode
, ibitsize
,
1118 gcc_assert (ibitnum
+ ibitsize
<= GET_MODE_BITSIZE (int_mode
));
1119 temp
= copy_to_reg (str_rtx
);
1120 if (!store_bit_field_1 (temp
, ibitsize
, ibitnum
, 0, 0,
1121 int_mode
, value
, reverse
, true))
1124 emit_move_insn (str_rtx
, temp
);
1130 /* Under the C++0x memory model, we must not touch bits outside the
1131 bit region. Adjust the address to start at the beginning of the
1133 if (MEM_P (str_rtx
) && maybe_ne (bitregion_start
, 0U))
1135 scalar_int_mode best_mode
;
1136 machine_mode addr_mode
= VOIDmode
;
1138 poly_uint64 offset
= exact_div (bitregion_start
, BITS_PER_UNIT
);
1139 bitnum
-= bitregion_start
;
1140 poly_int64 size
= bits_to_bytes_round_up (bitnum
+ bitsize
);
1141 bitregion_end
-= bitregion_start
;
1142 bitregion_start
= 0;
1143 if (bitsize
.is_constant (&ibitsize
)
1144 && bitnum
.is_constant (&ibitnum
)
1145 && get_best_mode (ibitsize
, ibitnum
,
1146 bitregion_start
, bitregion_end
,
1147 MEM_ALIGN (str_rtx
), INT_MAX
,
1148 MEM_VOLATILE_P (str_rtx
), &best_mode
))
1149 addr_mode
= best_mode
;
1150 str_rtx
= adjust_bitfield_address_size (str_rtx
, addr_mode
,
1154 if (!store_bit_field_1 (str_rtx
, bitsize
, bitnum
,
1155 bitregion_start
, bitregion_end
,
1156 fieldmode
, value
, reverse
, true))
1160 /* Use shifts and boolean operations to store VALUE into a bit field of
1161 width BITSIZE in OP0, starting at bit BITNUM. If OP0_MODE is defined,
1162 it is the mode of OP0, otherwise OP0 is a BLKmode MEM. VALUE_MODE is
1165 If REVERSE is true, the store is to be done in reverse order. */
1168 store_fixed_bit_field (rtx op0
, opt_scalar_int_mode op0_mode
,
1169 unsigned HOST_WIDE_INT bitsize
,
1170 unsigned HOST_WIDE_INT bitnum
,
1171 poly_uint64 bitregion_start
, poly_uint64 bitregion_end
,
1172 rtx value
, scalar_int_mode value_mode
, bool reverse
)
1174 /* There is a case not handled here:
1175 a structure with a known alignment of just a halfword
1176 and a field split across two aligned halfwords within the structure.
1177 Or likewise a structure with a known alignment of just a byte
1178 and a field split across two bytes.
1179 Such cases are not supposed to be able to occur. */
1181 scalar_int_mode best_mode
;
1184 unsigned int max_bitsize
= BITS_PER_WORD
;
1185 scalar_int_mode imode
;
1186 if (op0_mode
.exists (&imode
) && GET_MODE_BITSIZE (imode
) < max_bitsize
)
1187 max_bitsize
= GET_MODE_BITSIZE (imode
);
1189 if (!get_best_mode (bitsize
, bitnum
, bitregion_start
, bitregion_end
,
1190 MEM_ALIGN (op0
), max_bitsize
, MEM_VOLATILE_P (op0
),
1193 /* The only way this should occur is if the field spans word
1195 store_split_bit_field (op0
, op0_mode
, bitsize
, bitnum
,
1196 bitregion_start
, bitregion_end
,
1197 value
, value_mode
, reverse
);
1201 op0
= narrow_bit_field_mem (op0
, best_mode
, bitsize
, bitnum
, &bitnum
);
1204 best_mode
= op0_mode
.require ();
1206 store_fixed_bit_field_1 (op0
, best_mode
, bitsize
, bitnum
,
1207 value
, value_mode
, reverse
);
1210 /* Helper function for store_fixed_bit_field, stores
1211 the bit field always using MODE, which is the mode of OP0. The other
1212 arguments are as for store_fixed_bit_field. */
1215 store_fixed_bit_field_1 (rtx op0
, scalar_int_mode mode
,
1216 unsigned HOST_WIDE_INT bitsize
,
1217 unsigned HOST_WIDE_INT bitnum
,
1218 rtx value
, scalar_int_mode value_mode
, bool reverse
)
1224 /* Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode)
1225 for invalid input, such as f5 from gcc.dg/pr48335-2.c. */
1227 if (reverse
? !BYTES_BIG_ENDIAN
: BYTES_BIG_ENDIAN
)
1228 /* BITNUM is the distance between our msb
1229 and that of the containing datum.
1230 Convert it to the distance from the lsb. */
1231 bitnum
= GET_MODE_BITSIZE (mode
) - bitsize
- bitnum
;
1233 /* Now BITNUM is always the distance between our lsb
1236 /* Shift VALUE left by BITNUM bits. If VALUE is not constant,
1237 we must first convert its mode to MODE. */
1239 if (CONST_INT_P (value
))
1241 unsigned HOST_WIDE_INT v
= UINTVAL (value
);
1243 if (bitsize
< HOST_BITS_PER_WIDE_INT
)
1244 v
&= (HOST_WIDE_INT_1U
<< bitsize
) - 1;
1248 else if ((bitsize
< HOST_BITS_PER_WIDE_INT
1249 && v
== (HOST_WIDE_INT_1U
<< bitsize
) - 1)
1250 || (bitsize
== HOST_BITS_PER_WIDE_INT
1251 && v
== HOST_WIDE_INT_M1U
))
1254 value
= lshift_value (mode
, v
, bitnum
);
1258 int must_and
= (GET_MODE_BITSIZE (value_mode
) != bitsize
1259 && bitnum
+ bitsize
!= GET_MODE_BITSIZE (mode
));
1261 if (value_mode
!= mode
)
1262 value
= convert_to_mode (mode
, value
, 1);
1265 value
= expand_binop (mode
, and_optab
, value
,
1266 mask_rtx (mode
, 0, bitsize
, 0),
1267 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1269 value
= expand_shift (LSHIFT_EXPR
, mode
, value
,
1270 bitnum
, NULL_RTX
, 1);
1274 value
= flip_storage_order (mode
, value
);
1276 /* Now clear the chosen bits in OP0,
1277 except that if VALUE is -1 we need not bother. */
1278 /* We keep the intermediates in registers to allow CSE to combine
1279 consecutive bitfield assignments. */
1281 temp
= force_reg (mode
, op0
);
1285 rtx mask
= mask_rtx (mode
, bitnum
, bitsize
, 1);
1287 mask
= flip_storage_order (mode
, mask
);
1288 temp
= expand_binop (mode
, and_optab
, temp
, mask
,
1289 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1290 temp
= force_reg (mode
, temp
);
1293 /* Now logical-or VALUE into OP0, unless it is zero. */
1297 temp
= expand_binop (mode
, ior_optab
, temp
, value
,
1298 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
1299 temp
= force_reg (mode
, temp
);
1304 op0
= copy_rtx (op0
);
1305 emit_move_insn (op0
, temp
);
1309 /* Store a bit field that is split across multiple accessible memory objects.
1311 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
1312 BITSIZE is the field width; BITPOS the position of its first bit
1314 VALUE is the value to store, which has mode VALUE_MODE.
1315 If OP0_MODE is defined, it is the mode of OP0, otherwise OP0 is
1318 If REVERSE is true, the store is to be done in reverse order.
1320 This does not yet handle fields wider than BITS_PER_WORD. */
1323 store_split_bit_field (rtx op0
, opt_scalar_int_mode op0_mode
,
1324 unsigned HOST_WIDE_INT bitsize
,
1325 unsigned HOST_WIDE_INT bitpos
,
1326 poly_uint64 bitregion_start
, poly_uint64 bitregion_end
,
1327 rtx value
, scalar_int_mode value_mode
, bool reverse
)
1329 unsigned int unit
, total_bits
, bitsdone
= 0;
1331 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1333 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
1334 unit
= BITS_PER_WORD
;
1336 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
1338 /* If OP0 is a memory with a mode, then UNIT must not be larger than
1339 OP0's mode as well. Otherwise, store_fixed_bit_field will call us
1340 again, and we will mutually recurse forever. */
1341 if (MEM_P (op0
) && op0_mode
.exists ())
1342 unit
= MIN (unit
, GET_MODE_BITSIZE (op0_mode
.require ()));
1344 /* If VALUE is a constant other than a CONST_INT, get it into a register in
1345 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
1346 that VALUE might be a floating-point constant. */
1347 if (CONSTANT_P (value
) && !CONST_INT_P (value
))
1349 rtx word
= gen_lowpart_common (word_mode
, value
);
1351 if (word
&& (value
!= word
))
1354 value
= gen_lowpart_common (word_mode
, force_reg (value_mode
, value
));
1355 value_mode
= word_mode
;
1358 total_bits
= GET_MODE_BITSIZE (value_mode
);
1360 while (bitsdone
< bitsize
)
1362 unsigned HOST_WIDE_INT thissize
;
1363 unsigned HOST_WIDE_INT thispos
;
1364 unsigned HOST_WIDE_INT offset
;
1367 offset
= (bitpos
+ bitsdone
) / unit
;
1368 thispos
= (bitpos
+ bitsdone
) % unit
;
1370 /* When region of bytes we can touch is restricted, decrease
1371 UNIT close to the end of the region as needed. If op0 is a REG
1372 or SUBREG of REG, don't do this, as there can't be data races
1373 on a register and we can expand shorter code in some cases. */
1374 if (maybe_ne (bitregion_end
, 0U)
1375 && unit
> BITS_PER_UNIT
1376 && maybe_gt (bitpos
+ bitsdone
- thispos
+ unit
, bitregion_end
+ 1)
1378 && (GET_CODE (op0
) != SUBREG
|| !REG_P (SUBREG_REG (op0
))))
1384 /* THISSIZE must not overrun a word boundary. Otherwise,
1385 store_fixed_bit_field will call us again, and we will mutually
1387 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
1388 thissize
= MIN (thissize
, unit
- thispos
);
1390 if (reverse
? !BYTES_BIG_ENDIAN
: BYTES_BIG_ENDIAN
)
1392 /* Fetch successively less significant portions. */
1393 if (CONST_INT_P (value
))
1394 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
1395 >> (bitsize
- bitsdone
- thissize
))
1396 & ((HOST_WIDE_INT_1
<< thissize
) - 1));
1397 /* Likewise, but the source is little-endian. */
1399 part
= extract_fixed_bit_field (word_mode
, value
, value_mode
,
1401 bitsize
- bitsdone
- thissize
,
1402 NULL_RTX
, 1, false);
1404 /* The args are chosen so that the last part includes the
1405 lsb. Give extract_bit_field the value it needs (with
1406 endianness compensation) to fetch the piece we want. */
1407 part
= extract_fixed_bit_field (word_mode
, value
, value_mode
,
1409 total_bits
- bitsize
+ bitsdone
,
1410 NULL_RTX
, 1, false);
1414 /* Fetch successively more significant portions. */
1415 if (CONST_INT_P (value
))
1416 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
1418 & ((HOST_WIDE_INT_1
<< thissize
) - 1));
1419 /* Likewise, but the source is big-endian. */
1421 part
= extract_fixed_bit_field (word_mode
, value
, value_mode
,
1423 total_bits
- bitsdone
- thissize
,
1424 NULL_RTX
, 1, false);
1426 part
= extract_fixed_bit_field (word_mode
, value
, value_mode
,
1427 thissize
, bitsdone
, NULL_RTX
,
1431 /* If OP0 is a register, then handle OFFSET here. */
1432 rtx op0_piece
= op0
;
1433 opt_scalar_int_mode op0_piece_mode
= op0_mode
;
1434 if (SUBREG_P (op0
) || REG_P (op0
))
1436 scalar_int_mode imode
;
1437 if (op0_mode
.exists (&imode
)
1438 && GET_MODE_SIZE (imode
) < UNITS_PER_WORD
)
1441 op0_piece
= const0_rtx
;
1445 op0_piece
= operand_subword_force (op0
,
1446 offset
* unit
/ BITS_PER_WORD
,
1448 op0_piece_mode
= word_mode
;
1450 offset
&= BITS_PER_WORD
/ unit
- 1;
1453 /* OFFSET is in UNITs, and UNIT is in bits. If WORD is const0_rtx,
1454 it is just an out-of-bounds access. Ignore it. */
1455 if (op0_piece
!= const0_rtx
)
1456 store_fixed_bit_field (op0_piece
, op0_piece_mode
, thissize
,
1457 offset
* unit
+ thispos
, bitregion_start
,
1458 bitregion_end
, part
, word_mode
, reverse
);
1459 bitsdone
+= thissize
;
1463 /* A subroutine of extract_bit_field_1 that converts return value X
1464 to either MODE or TMODE. MODE, TMODE and UNSIGNEDP are arguments
1465 to extract_bit_field. */
1468 convert_extracted_bit_field (rtx x
, machine_mode mode
,
1469 machine_mode tmode
, bool unsignedp
)
1471 if (GET_MODE (x
) == tmode
|| GET_MODE (x
) == mode
)
1474 /* If the x mode is not a scalar integral, first convert to the
1475 integer mode of that size and then access it as a floating-point
1476 value via a SUBREG. */
1477 if (!SCALAR_INT_MODE_P (tmode
))
1479 scalar_int_mode int_mode
= int_mode_for_mode (tmode
).require ();
1480 x
= convert_to_mode (int_mode
, x
, unsignedp
);
1481 x
= force_reg (int_mode
, x
);
1482 return gen_lowpart (tmode
, x
);
1485 return convert_to_mode (tmode
, x
, unsignedp
);
1488 /* Try to use an ext(z)v pattern to extract a field from OP0.
1489 Return the extracted value on success, otherwise return null.
1490 EXTV describes the extraction instruction to use. If OP0_MODE
1491 is defined, it is the mode of OP0, otherwise OP0 is a BLKmode MEM.
1492 The other arguments are as for extract_bit_field. */
1495 extract_bit_field_using_extv (const extraction_insn
*extv
, rtx op0
,
1496 opt_scalar_int_mode op0_mode
,
1497 unsigned HOST_WIDE_INT bitsize
,
1498 unsigned HOST_WIDE_INT bitnum
,
1499 int unsignedp
, rtx target
,
1500 machine_mode mode
, machine_mode tmode
)
1502 struct expand_operand ops
[4];
1503 rtx spec_target
= target
;
1504 rtx spec_target_subreg
= 0;
1505 scalar_int_mode ext_mode
= extv
->field_mode
;
1506 unsigned unit
= GET_MODE_BITSIZE (ext_mode
);
1508 if (bitsize
== 0 || unit
< bitsize
)
1512 /* Get a reference to the first byte of the field. */
1513 op0
= narrow_bit_field_mem (op0
, extv
->struct_mode
, bitsize
, bitnum
,
1517 /* Convert from counting within OP0 to counting in EXT_MODE. */
1518 if (BYTES_BIG_ENDIAN
)
1519 bitnum
+= unit
- GET_MODE_BITSIZE (op0_mode
.require ());
1521 /* If op0 is a register, we need it in EXT_MODE to make it
1522 acceptable to the format of ext(z)v. */
1523 if (GET_CODE (op0
) == SUBREG
&& op0_mode
.require () != ext_mode
)
1525 if (REG_P (op0
) && op0_mode
.require () != ext_mode
)
1526 op0
= gen_lowpart_SUBREG (ext_mode
, op0
);
1529 /* If BITS_BIG_ENDIAN is zero on a BYTES_BIG_ENDIAN machine, we count
1530 "backwards" from the size of the unit we are extracting from.
1531 Otherwise, we count bits from the most significant on a
1532 BYTES/BITS_BIG_ENDIAN machine. */
1534 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
1535 bitnum
= unit
- bitsize
- bitnum
;
1538 target
= spec_target
= gen_reg_rtx (tmode
);
1540 if (GET_MODE (target
) != ext_mode
)
1542 /* Don't use LHS paradoxical subreg if explicit truncation is needed
1543 between the mode of the extraction (word_mode) and the target
1544 mode. Instead, create a temporary and use convert_move to set
1547 && TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (target
), ext_mode
))
1549 target
= gen_lowpart (ext_mode
, target
);
1550 if (partial_subreg_p (GET_MODE (spec_target
), ext_mode
))
1551 spec_target_subreg
= target
;
1554 target
= gen_reg_rtx (ext_mode
);
1557 create_output_operand (&ops
[0], target
, ext_mode
);
1558 create_fixed_operand (&ops
[1], op0
);
1559 create_integer_operand (&ops
[2], bitsize
);
1560 create_integer_operand (&ops
[3], bitnum
);
1561 if (maybe_expand_insn (extv
->icode
, 4, ops
))
1563 target
= ops
[0].value
;
1564 if (target
== spec_target
)
1566 if (target
== spec_target_subreg
)
1568 return convert_extracted_bit_field (target
, mode
, tmode
, unsignedp
);
1573 /* See whether it would be valid to extract the part of OP0 described
1574 by BITNUM and BITSIZE into a value of mode MODE using a subreg
1575 operation. Return the subreg if so, otherwise return null. */
1578 extract_bit_field_as_subreg (machine_mode mode
, rtx op0
,
1579 poly_uint64 bitsize
, poly_uint64 bitnum
)
1581 poly_uint64 bytenum
;
1582 if (multiple_p (bitnum
, BITS_PER_UNIT
, &bytenum
)
1583 && known_eq (bitsize
, GET_MODE_BITSIZE (mode
))
1584 && lowpart_bit_field_p (bitnum
, bitsize
, GET_MODE (op0
))
1585 && TRULY_NOOP_TRUNCATION_MODES_P (mode
, GET_MODE (op0
)))
1586 return simplify_gen_subreg (mode
, op0
, GET_MODE (op0
), bytenum
);
1590 /* A subroutine of extract_bit_field, with the same arguments.
1591 If FALLBACK_P is true, fall back to extract_fixed_bit_field
1592 if we can find no other means of implementing the operation.
1593 if FALLBACK_P is false, return NULL instead. */
1596 extract_bit_field_1 (rtx str_rtx
, poly_uint64 bitsize
, poly_uint64 bitnum
,
1597 int unsignedp
, rtx target
, machine_mode mode
,
1598 machine_mode tmode
, bool reverse
, bool fallback_p
,
1604 if (tmode
== VOIDmode
)
1607 while (GET_CODE (op0
) == SUBREG
)
1609 bitnum
+= SUBREG_BYTE (op0
) * BITS_PER_UNIT
;
1610 op0
= SUBREG_REG (op0
);
1613 /* If we have an out-of-bounds access to a register, just return an
1614 uninitialized register of the required mode. This can occur if the
1615 source code contains an out-of-bounds access to a small array. */
1616 if (REG_P (op0
) && known_ge (bitnum
, GET_MODE_BITSIZE (GET_MODE (op0
))))
1617 return gen_reg_rtx (tmode
);
1620 && mode
== GET_MODE (op0
)
1621 && known_eq (bitnum
, 0U)
1622 && known_eq (bitsize
, GET_MODE_BITSIZE (GET_MODE (op0
))))
1625 op0
= flip_storage_order (mode
, op0
);
1626 /* We're trying to extract a full register from itself. */
1630 /* First try to check for vector from vector extractions. */
1631 if (VECTOR_MODE_P (GET_MODE (op0
))
1633 && VECTOR_MODE_P (tmode
)
1634 && known_eq (bitsize
, GET_MODE_SIZE (tmode
))
1635 && maybe_gt (GET_MODE_SIZE (GET_MODE (op0
)), GET_MODE_SIZE (tmode
)))
1637 machine_mode new_mode
= GET_MODE (op0
);
1638 if (GET_MODE_INNER (new_mode
) != GET_MODE_INNER (tmode
))
1640 scalar_mode inner_mode
= GET_MODE_INNER (tmode
);
1642 if (!multiple_p (GET_MODE_BITSIZE (GET_MODE (op0
)),
1643 GET_MODE_UNIT_BITSIZE (tmode
), &nunits
)
1644 || !mode_for_vector (inner_mode
, nunits
).exists (&new_mode
)
1645 || !VECTOR_MODE_P (new_mode
)
1646 || maybe_ne (GET_MODE_SIZE (new_mode
),
1647 GET_MODE_SIZE (GET_MODE (op0
)))
1648 || GET_MODE_INNER (new_mode
) != GET_MODE_INNER (tmode
)
1649 || !targetm
.vector_mode_supported_p (new_mode
))
1650 new_mode
= VOIDmode
;
1653 if (new_mode
!= VOIDmode
1654 && (convert_optab_handler (vec_extract_optab
, new_mode
, tmode
)
1655 != CODE_FOR_nothing
)
1656 && multiple_p (bitnum
, GET_MODE_BITSIZE (tmode
), &pos
))
1658 struct expand_operand ops
[3];
1659 machine_mode outermode
= new_mode
;
1660 machine_mode innermode
= tmode
;
1661 enum insn_code icode
1662 = convert_optab_handler (vec_extract_optab
, outermode
, innermode
);
1664 if (new_mode
!= GET_MODE (op0
))
1665 op0
= gen_lowpart (new_mode
, op0
);
1666 create_output_operand (&ops
[0], target
, innermode
);
1668 create_input_operand (&ops
[1], op0
, outermode
);
1669 create_integer_operand (&ops
[2], pos
);
1670 if (maybe_expand_insn (icode
, 3, ops
))
1672 if (alt_rtl
&& ops
[0].target
)
1674 target
= ops
[0].value
;
1675 if (GET_MODE (target
) != mode
)
1676 return gen_lowpart (tmode
, target
);
1682 /* See if we can get a better vector mode before extracting. */
1683 if (VECTOR_MODE_P (GET_MODE (op0
))
1685 && GET_MODE_INNER (GET_MODE (op0
)) != tmode
)
1687 machine_mode new_mode
;
1689 if (GET_MODE_CLASS (tmode
) == MODE_FLOAT
)
1690 new_mode
= MIN_MODE_VECTOR_FLOAT
;
1691 else if (GET_MODE_CLASS (tmode
) == MODE_FRACT
)
1692 new_mode
= MIN_MODE_VECTOR_FRACT
;
1693 else if (GET_MODE_CLASS (tmode
) == MODE_UFRACT
)
1694 new_mode
= MIN_MODE_VECTOR_UFRACT
;
1695 else if (GET_MODE_CLASS (tmode
) == MODE_ACCUM
)
1696 new_mode
= MIN_MODE_VECTOR_ACCUM
;
1697 else if (GET_MODE_CLASS (tmode
) == MODE_UACCUM
)
1698 new_mode
= MIN_MODE_VECTOR_UACCUM
;
1700 new_mode
= MIN_MODE_VECTOR_INT
;
1702 FOR_EACH_MODE_FROM (new_mode
, new_mode
)
1703 if (known_eq (GET_MODE_SIZE (new_mode
), GET_MODE_SIZE (GET_MODE (op0
)))
1704 && known_eq (GET_MODE_UNIT_SIZE (new_mode
), GET_MODE_SIZE (tmode
))
1705 && targetm
.vector_mode_supported_p (new_mode
))
1707 if (new_mode
!= VOIDmode
)
1708 op0
= gen_lowpart (new_mode
, op0
);
1711 /* Use vec_extract patterns for extracting parts of vectors whenever
1713 machine_mode outermode
= GET_MODE (op0
);
1714 scalar_mode innermode
= GET_MODE_INNER (outermode
);
1716 if (VECTOR_MODE_P (outermode
)
1718 && (convert_optab_handler (vec_extract_optab
, outermode
, innermode
)
1719 != CODE_FOR_nothing
)
1720 && known_eq (bitsize
, GET_MODE_BITSIZE (innermode
))
1721 && multiple_p (bitnum
, GET_MODE_BITSIZE (innermode
), &pos
))
1723 struct expand_operand ops
[3];
1724 enum insn_code icode
1725 = convert_optab_handler (vec_extract_optab
, outermode
, innermode
);
1727 create_output_operand (&ops
[0], target
, innermode
);
1729 create_input_operand (&ops
[1], op0
, outermode
);
1730 create_integer_operand (&ops
[2], pos
);
1731 if (maybe_expand_insn (icode
, 3, ops
))
1733 if (alt_rtl
&& ops
[0].target
)
1735 target
= ops
[0].value
;
1736 if (GET_MODE (target
) != mode
)
1737 return gen_lowpart (tmode
, target
);
1742 /* Make sure we are playing with integral modes. Pun with subregs
1744 opt_scalar_int_mode op0_mode
= int_mode_for_mode (GET_MODE (op0
));
1745 scalar_int_mode imode
;
1746 if (!op0_mode
.exists (&imode
) || imode
!= GET_MODE (op0
))
1749 op0
= adjust_bitfield_address_size (op0
, op0_mode
.else_blk (),
1751 else if (op0_mode
.exists (&imode
))
1753 op0
= gen_lowpart (imode
, op0
);
1755 /* If we got a SUBREG, force it into a register since we
1756 aren't going to be able to do another SUBREG on it. */
1757 if (GET_CODE (op0
) == SUBREG
)
1758 op0
= force_reg (imode
, op0
);
1762 poly_int64 size
= GET_MODE_SIZE (GET_MODE (op0
));
1763 rtx mem
= assign_stack_temp (GET_MODE (op0
), size
);
1764 emit_move_insn (mem
, op0
);
1765 op0
= adjust_bitfield_address_size (mem
, BLKmode
, 0, size
);
1769 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1770 If that's wrong, the solution is to test for it and set TARGET to 0
1773 /* Get the mode of the field to use for atomic access or subreg
1775 if (!SCALAR_INT_MODE_P (tmode
)
1776 || !mode_for_size (bitsize
, GET_MODE_CLASS (tmode
), 0).exists (&mode1
))
1778 gcc_assert (mode1
!= BLKmode
);
1780 /* Extraction of a full MODE1 value can be done with a subreg as long
1781 as the least significant bit of the value is the least significant
1782 bit of either OP0 or a word of OP0. */
1783 if (!MEM_P (op0
) && !reverse
)
1785 rtx sub
= extract_bit_field_as_subreg (mode1
, op0
, bitsize
, bitnum
);
1787 return convert_extracted_bit_field (sub
, mode
, tmode
, unsignedp
);
1790 /* Extraction of a full MODE1 value can be done with a load as long as
1791 the field is on a byte boundary and is sufficiently aligned. */
1792 poly_uint64 bytenum
;
1793 if (simple_mem_bitfield_p (op0
, bitsize
, bitnum
, mode1
, &bytenum
))
1795 op0
= adjust_bitfield_address (op0
, mode1
, bytenum
);
1797 op0
= flip_storage_order (mode1
, op0
);
1798 return convert_extracted_bit_field (op0
, mode
, tmode
, unsignedp
);
1801 /* If we have a memory source and a non-constant bit offset, restrict
1802 the memory to the referenced bytes. This is a worst-case fallback
1803 but is useful for things like vector booleans. */
1804 if (MEM_P (op0
) && !bitnum
.is_constant ())
1806 bytenum
= bits_to_bytes_round_down (bitnum
);
1807 bitnum
= num_trailing_bits (bitnum
);
1808 poly_uint64 bytesize
= bits_to_bytes_round_up (bitnum
+ bitsize
);
1809 op0
= adjust_bitfield_address_size (op0
, BLKmode
, bytenum
, bytesize
);
1810 op0_mode
= opt_scalar_int_mode ();
1813 /* It's possible we'll need to handle other cases here for
1814 polynomial bitnum and bitsize. */
1816 /* From here on we need to be looking at a fixed-size insertion. */
1817 return extract_integral_bit_field (op0
, op0_mode
, bitsize
.to_constant (),
1818 bitnum
.to_constant (), unsignedp
,
1819 target
, mode
, tmode
, reverse
, fallback_p
);
1822 /* Subroutine of extract_bit_field_1, with the same arguments, except
1823 that BITSIZE and BITNUM are constant. Handle cases specific to
1824 integral modes. If OP0_MODE is defined, it is the mode of OP0,
1825 otherwise OP0 is a BLKmode MEM. */
1828 extract_integral_bit_field (rtx op0
, opt_scalar_int_mode op0_mode
,
1829 unsigned HOST_WIDE_INT bitsize
,
1830 unsigned HOST_WIDE_INT bitnum
, int unsignedp
,
1831 rtx target
, machine_mode mode
, machine_mode tmode
,
1832 bool reverse
, bool fallback_p
)
1834 /* Handle fields bigger than a word. */
1836 if (bitsize
> BITS_PER_WORD
)
1838 /* Here we transfer the words of the field
1839 in the order least significant first.
1840 This is because the most significant word is the one which may
1841 be less than full. */
1843 const bool backwards
= WORDS_BIG_ENDIAN
;
1844 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
1848 if (target
== 0 || !REG_P (target
) || !valid_multiword_target_p (target
))
1849 target
= gen_reg_rtx (mode
);
1851 /* In case we're about to clobber a base register or something
1852 (see gcc.c-torture/execute/20040625-1.c). */
1853 if (reg_mentioned_p (target
, op0
))
1854 target
= gen_reg_rtx (mode
);
1856 /* Indicate for flow that the entire target reg is being set. */
1857 emit_clobber (target
);
1859 /* The mode must be fixed-size, since extract_bit_field_1 handles
1860 extractions from variable-sized objects before calling this
1862 unsigned int target_size
1863 = GET_MODE_SIZE (GET_MODE (target
)).to_constant ();
1864 last
= get_last_insn ();
1865 for (i
= 0; i
< nwords
; i
++)
1867 /* If I is 0, use the low-order word in both field and target;
1868 if I is 1, use the next to lowest word; and so on. */
1869 /* Word number in TARGET to use. */
1870 unsigned int wordnum
1871 = (backwards
? target_size
/ UNITS_PER_WORD
- i
- 1 : i
);
1872 /* Offset from start of field in OP0. */
1873 unsigned int bit_offset
= (backwards
^ reverse
1874 ? MAX ((int) bitsize
- ((int) i
+ 1)
1877 : (int) i
* BITS_PER_WORD
);
1878 rtx target_part
= operand_subword (target
, wordnum
, 1, VOIDmode
);
1880 = extract_bit_field_1 (op0
, MIN (BITS_PER_WORD
,
1881 bitsize
- i
* BITS_PER_WORD
),
1882 bitnum
+ bit_offset
, 1, target_part
,
1883 mode
, word_mode
, reverse
, fallback_p
, NULL
);
1885 gcc_assert (target_part
);
1888 delete_insns_since (last
);
1892 if (result_part
!= target_part
)
1893 emit_move_insn (target_part
, result_part
);
1898 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1899 need to be zero'd out. */
1900 if (target_size
> nwords
* UNITS_PER_WORD
)
1902 unsigned int i
, total_words
;
1904 total_words
= target_size
/ UNITS_PER_WORD
;
1905 for (i
= nwords
; i
< total_words
; i
++)
1907 (operand_subword (target
,
1908 backwards
? total_words
- i
- 1 : i
,
1915 /* Signed bit field: sign-extend with two arithmetic shifts. */
1916 target
= expand_shift (LSHIFT_EXPR
, mode
, target
,
1917 GET_MODE_BITSIZE (mode
) - bitsize
, NULL_RTX
, 0);
1918 return expand_shift (RSHIFT_EXPR
, mode
, target
,
1919 GET_MODE_BITSIZE (mode
) - bitsize
, NULL_RTX
, 0);
1922 /* If OP0 is a multi-word register, narrow it to the affected word.
1923 If the region spans two words, defer to extract_split_bit_field. */
1924 if (!MEM_P (op0
) && GET_MODE_SIZE (op0_mode
.require ()) > UNITS_PER_WORD
)
1926 if (bitnum
% BITS_PER_WORD
+ bitsize
> BITS_PER_WORD
)
1930 target
= extract_split_bit_field (op0
, op0_mode
, bitsize
, bitnum
,
1931 unsignedp
, reverse
);
1932 return convert_extracted_bit_field (target
, mode
, tmode
, unsignedp
);
1934 op0
= simplify_gen_subreg (word_mode
, op0
, op0_mode
.require (),
1935 bitnum
/ BITS_PER_WORD
* UNITS_PER_WORD
);
1936 op0_mode
= word_mode
;
1937 bitnum
%= BITS_PER_WORD
;
1940 /* From here on we know the desired field is smaller than a word.
1941 If OP0 is a register, it too fits within a word. */
1942 enum extraction_pattern pattern
= unsignedp
? EP_extzv
: EP_extv
;
1943 extraction_insn extv
;
1946 /* ??? We could limit the structure size to the part of OP0 that
1947 contains the field, with appropriate checks for endianness
1948 and TARGET_TRULY_NOOP_TRUNCATION. */
1949 && get_best_reg_extraction_insn (&extv
, pattern
,
1950 GET_MODE_BITSIZE (op0_mode
.require ()),
1953 rtx result
= extract_bit_field_using_extv (&extv
, op0
, op0_mode
,
1955 unsignedp
, target
, mode
,
1961 /* If OP0 is a memory, try copying it to a register and seeing if a
1962 cheap register alternative is available. */
1963 if (MEM_P (op0
) & !reverse
)
1965 if (get_best_mem_extraction_insn (&extv
, pattern
, bitsize
, bitnum
,
1968 rtx result
= extract_bit_field_using_extv (&extv
, op0
, op0_mode
,
1970 unsignedp
, target
, mode
,
1976 rtx_insn
*last
= get_last_insn ();
1978 /* Try loading part of OP0 into a register and extracting the
1979 bitfield from that. */
1980 unsigned HOST_WIDE_INT bitpos
;
1981 rtx xop0
= adjust_bit_field_mem_for_reg (pattern
, op0
, bitsize
, bitnum
,
1982 0, 0, tmode
, &bitpos
);
1985 xop0
= copy_to_reg (xop0
);
1986 rtx result
= extract_bit_field_1 (xop0
, bitsize
, bitpos
,
1988 mode
, tmode
, reverse
, false, NULL
);
1991 delete_insns_since (last
);
1998 /* Find a correspondingly-sized integer field, so we can apply
1999 shifts and masks to it. */
2000 scalar_int_mode int_mode
;
2001 if (!int_mode_for_mode (tmode
).exists (&int_mode
))
2002 /* If this fails, we should probably push op0 out to memory and then
2004 int_mode
= int_mode_for_mode (mode
).require ();
2006 target
= extract_fixed_bit_field (int_mode
, op0
, op0_mode
, bitsize
,
2007 bitnum
, target
, unsignedp
, reverse
);
2009 /* Complex values must be reversed piecewise, so we need to undo the global
2010 reversal, convert to the complex mode and reverse again. */
2011 if (reverse
&& COMPLEX_MODE_P (tmode
))
2013 target
= flip_storage_order (int_mode
, target
);
2014 target
= convert_extracted_bit_field (target
, mode
, tmode
, unsignedp
);
2015 target
= flip_storage_order (tmode
, target
);
2018 target
= convert_extracted_bit_field (target
, mode
, tmode
, unsignedp
);
2023 /* Generate code to extract a byte-field from STR_RTX
2024 containing BITSIZE bits, starting at BITNUM,
2025 and put it in TARGET if possible (if TARGET is nonzero).
2026 Regardless of TARGET, we return the rtx for where the value is placed.
2028 STR_RTX is the structure containing the byte (a REG or MEM).
2029 UNSIGNEDP is nonzero if this is an unsigned bit field.
2030 MODE is the natural mode of the field value once extracted.
2031 TMODE is the mode the caller would like the value to have;
2032 but the value may be returned with type MODE instead.
2034 If REVERSE is true, the extraction is to be done in reverse order.
2036 If a TARGET is specified and we can store in it at no extra cost,
2037 we do so, and return TARGET.
2038 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
2039 if they are equally easy. */
2042 extract_bit_field (rtx str_rtx
, poly_uint64 bitsize
, poly_uint64 bitnum
,
2043 int unsignedp
, rtx target
, machine_mode mode
,
2044 machine_mode tmode
, bool reverse
, rtx
*alt_rtl
)
2048 /* Handle -fstrict-volatile-bitfields in the cases where it applies. */
2049 if (maybe_ne (GET_MODE_BITSIZE (GET_MODE (str_rtx
)), 0))
2050 mode1
= GET_MODE (str_rtx
);
2051 else if (target
&& maybe_ne (GET_MODE_BITSIZE (GET_MODE (target
)), 0))
2052 mode1
= GET_MODE (target
);
2056 unsigned HOST_WIDE_INT ibitsize
, ibitnum
;
2057 scalar_int_mode int_mode
;
2058 if (bitsize
.is_constant (&ibitsize
)
2059 && bitnum
.is_constant (&ibitnum
)
2060 && is_a
<scalar_int_mode
> (mode1
, &int_mode
)
2061 && strict_volatile_bitfield_p (str_rtx
, ibitsize
, ibitnum
,
2064 /* Extraction of a full INT_MODE value can be done with a simple load.
2065 We know here that the field can be accessed with one single
2066 instruction. For targets that support unaligned memory,
2067 an unaligned access may be necessary. */
2068 if (ibitsize
== GET_MODE_BITSIZE (int_mode
))
2070 rtx result
= adjust_bitfield_address (str_rtx
, int_mode
,
2071 ibitnum
/ BITS_PER_UNIT
);
2073 result
= flip_storage_order (int_mode
, result
);
2074 gcc_assert (ibitnum
% BITS_PER_UNIT
== 0);
2075 return convert_extracted_bit_field (result
, mode
, tmode
, unsignedp
);
2078 str_rtx
= narrow_bit_field_mem (str_rtx
, int_mode
, ibitsize
, ibitnum
,
2080 gcc_assert (ibitnum
+ ibitsize
<= GET_MODE_BITSIZE (int_mode
));
2081 str_rtx
= copy_to_reg (str_rtx
);
2082 return extract_bit_field_1 (str_rtx
, ibitsize
, ibitnum
, unsignedp
,
2083 target
, mode
, tmode
, reverse
, true, alt_rtl
);
2086 return extract_bit_field_1 (str_rtx
, bitsize
, bitnum
, unsignedp
,
2087 target
, mode
, tmode
, reverse
, true, alt_rtl
);
2090 /* Use shifts and boolean operations to extract a field of BITSIZE bits
2091 from bit BITNUM of OP0. If OP0_MODE is defined, it is the mode of OP0,
2092 otherwise OP0 is a BLKmode MEM.
2094 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
2095 If REVERSE is true, the extraction is to be done in reverse order.
2097 If TARGET is nonzero, attempts to store the value there
2098 and return TARGET, but this is not guaranteed.
2099 If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */
2102 extract_fixed_bit_field (machine_mode tmode
, rtx op0
,
2103 opt_scalar_int_mode op0_mode
,
2104 unsigned HOST_WIDE_INT bitsize
,
2105 unsigned HOST_WIDE_INT bitnum
, rtx target
,
2106 int unsignedp
, bool reverse
)
2108 scalar_int_mode mode
;
2111 if (!get_best_mode (bitsize
, bitnum
, 0, 0, MEM_ALIGN (op0
),
2112 BITS_PER_WORD
, MEM_VOLATILE_P (op0
), &mode
))
2113 /* The only way this should occur is if the field spans word
2115 return extract_split_bit_field (op0
, op0_mode
, bitsize
, bitnum
,
2116 unsignedp
, reverse
);
2118 op0
= narrow_bit_field_mem (op0
, mode
, bitsize
, bitnum
, &bitnum
);
2121 mode
= op0_mode
.require ();
2123 return extract_fixed_bit_field_1 (tmode
, op0
, mode
, bitsize
, bitnum
,
2124 target
, unsignedp
, reverse
);
2127 /* Helper function for extract_fixed_bit_field, extracts
2128 the bit field always using MODE, which is the mode of OP0.
2129 The other arguments are as for extract_fixed_bit_field. */
2132 extract_fixed_bit_field_1 (machine_mode tmode
, rtx op0
, scalar_int_mode mode
,
2133 unsigned HOST_WIDE_INT bitsize
,
2134 unsigned HOST_WIDE_INT bitnum
, rtx target
,
2135 int unsignedp
, bool reverse
)
2137 /* Note that bitsize + bitnum can be greater than GET_MODE_BITSIZE (mode)
2138 for invalid input, such as extract equivalent of f5 from
2139 gcc.dg/pr48335-2.c. */
2141 if (reverse
? !BYTES_BIG_ENDIAN
: BYTES_BIG_ENDIAN
)
2142 /* BITNUM is the distance between our msb and that of OP0.
2143 Convert it to the distance from the lsb. */
2144 bitnum
= GET_MODE_BITSIZE (mode
) - bitsize
- bitnum
;
2146 /* Now BITNUM is always the distance between the field's lsb and that of OP0.
2147 We have reduced the big-endian case to the little-endian case. */
2149 op0
= flip_storage_order (mode
, op0
);
2155 /* If the field does not already start at the lsb,
2156 shift it so it does. */
2157 /* Maybe propagate the target for the shift. */
2158 rtx subtarget
= (target
!= 0 && REG_P (target
) ? target
: 0);
2161 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
, bitnum
, subtarget
, 1);
2163 /* Convert the value to the desired mode. TMODE must also be a
2164 scalar integer for this conversion to make sense, since we
2165 shouldn't reinterpret the bits. */
2166 scalar_int_mode new_mode
= as_a
<scalar_int_mode
> (tmode
);
2167 if (mode
!= new_mode
)
2168 op0
= convert_to_mode (new_mode
, op0
, 1);
2170 /* Unless the msb of the field used to be the msb when we shifted,
2171 mask out the upper bits. */
2173 if (GET_MODE_BITSIZE (mode
) != bitnum
+ bitsize
)
2174 return expand_binop (new_mode
, and_optab
, op0
,
2175 mask_rtx (new_mode
, 0, bitsize
, 0),
2176 target
, 1, OPTAB_LIB_WIDEN
);
2180 /* To extract a signed bit-field, first shift its msb to the msb of the word,
2181 then arithmetic-shift its lsb to the lsb of the word. */
2182 op0
= force_reg (mode
, op0
);
2184 /* Find the narrowest integer mode that contains the field. */
2186 opt_scalar_int_mode mode_iter
;
2187 FOR_EACH_MODE_IN_CLASS (mode_iter
, MODE_INT
)
2188 if (GET_MODE_BITSIZE (mode_iter
.require ()) >= bitsize
+ bitnum
)
2191 mode
= mode_iter
.require ();
2192 op0
= convert_to_mode (mode
, op0
, 0);
2197 if (GET_MODE_BITSIZE (mode
) != (bitsize
+ bitnum
))
2199 int amount
= GET_MODE_BITSIZE (mode
) - (bitsize
+ bitnum
);
2200 /* Maybe propagate the target for the shift. */
2201 rtx subtarget
= (target
!= 0 && REG_P (target
) ? target
: 0);
2202 op0
= expand_shift (LSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
2205 return expand_shift (RSHIFT_EXPR
, mode
, op0
,
2206 GET_MODE_BITSIZE (mode
) - bitsize
, target
, 0);
2209 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
2213 lshift_value (machine_mode mode
, unsigned HOST_WIDE_INT value
,
2216 return immed_wide_int_const (wi::lshift (value
, bitpos
), mode
);
2219 /* Extract a bit field that is split across two words
2220 and return an RTX for the result.
2222 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
2223 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
2224 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend.
2225 If OP0_MODE is defined, it is the mode of OP0, otherwise OP0 is
2228 If REVERSE is true, the extraction is to be done in reverse order. */
2231 extract_split_bit_field (rtx op0
, opt_scalar_int_mode op0_mode
,
2232 unsigned HOST_WIDE_INT bitsize
,
2233 unsigned HOST_WIDE_INT bitpos
, int unsignedp
,
2237 unsigned int bitsdone
= 0;
2238 rtx result
= NULL_RTX
;
2241 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
2243 if (REG_P (op0
) || GET_CODE (op0
) == SUBREG
)
2244 unit
= BITS_PER_WORD
;
2246 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
2248 while (bitsdone
< bitsize
)
2250 unsigned HOST_WIDE_INT thissize
;
2252 unsigned HOST_WIDE_INT thispos
;
2253 unsigned HOST_WIDE_INT offset
;
2255 offset
= (bitpos
+ bitsdone
) / unit
;
2256 thispos
= (bitpos
+ bitsdone
) % unit
;
2258 /* THISSIZE must not overrun a word boundary. Otherwise,
2259 extract_fixed_bit_field will call us again, and we will mutually
2261 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
2262 thissize
= MIN (thissize
, unit
- thispos
);
2264 /* If OP0 is a register, then handle OFFSET here. */
2265 rtx op0_piece
= op0
;
2266 opt_scalar_int_mode op0_piece_mode
= op0_mode
;
2267 if (SUBREG_P (op0
) || REG_P (op0
))
2269 op0_piece
= operand_subword_force (op0
, offset
, op0_mode
.require ());
2270 op0_piece_mode
= word_mode
;
2274 /* Extract the parts in bit-counting order,
2275 whose meaning is determined by BYTES_PER_UNIT.
2276 OFFSET is in UNITs, and UNIT is in bits. */
2277 part
= extract_fixed_bit_field (word_mode
, op0_piece
, op0_piece_mode
,
2278 thissize
, offset
* unit
+ thispos
,
2280 bitsdone
+= thissize
;
2282 /* Shift this part into place for the result. */
2283 if (reverse
? !BYTES_BIG_ENDIAN
: BYTES_BIG_ENDIAN
)
2285 if (bitsize
!= bitsdone
)
2286 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
2287 bitsize
- bitsdone
, 0, 1);
2291 if (bitsdone
!= thissize
)
2292 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
2293 bitsdone
- thissize
, 0, 1);
2299 /* Combine the parts with bitwise or. This works
2300 because we extracted each part as an unsigned bit field. */
2301 result
= expand_binop (word_mode
, ior_optab
, part
, result
, NULL_RTX
, 1,
2307 /* Unsigned bit field: we are done. */
2310 /* Signed bit field: sign-extend with two arithmetic shifts. */
2311 result
= expand_shift (LSHIFT_EXPR
, word_mode
, result
,
2312 BITS_PER_WORD
- bitsize
, NULL_RTX
, 0);
2313 return expand_shift (RSHIFT_EXPR
, word_mode
, result
,
2314 BITS_PER_WORD
- bitsize
, NULL_RTX
, 0);
2317 /* Try to read the low bits of SRC as an rvalue of mode MODE, preserving
2318 the bit pattern. SRC_MODE is the mode of SRC; if this is smaller than
2319 MODE, fill the upper bits with zeros. Fail if the layout of either
2320 mode is unknown (as for CC modes) or if the extraction would involve
2321 unprofitable mode punning. Return the value on success, otherwise
2324 This is different from gen_lowpart* in these respects:
2326 - the returned value must always be considered an rvalue
2328 - when MODE is wider than SRC_MODE, the extraction involves
2331 - when MODE is smaller than SRC_MODE, the extraction involves
2332 a truncation (and is thus subject to TARGET_TRULY_NOOP_TRUNCATION).
2334 In other words, this routine performs a computation, whereas the
2335 gen_lowpart* routines are conceptually lvalue or rvalue subreg
2339 extract_low_bits (machine_mode mode
, machine_mode src_mode
, rtx src
)
2341 scalar_int_mode int_mode
, src_int_mode
;
2343 if (mode
== src_mode
)
2346 if (CONSTANT_P (src
))
2348 /* simplify_gen_subreg can't be used here, as if simplify_subreg
2349 fails, it will happily create (subreg (symbol_ref)) or similar
2351 poly_uint64 byte
= subreg_lowpart_offset (mode
, src_mode
);
2352 rtx ret
= simplify_subreg (mode
, src
, src_mode
, byte
);
2356 if (GET_MODE (src
) == VOIDmode
2357 || !validate_subreg (mode
, src_mode
, src
, byte
))
2360 src
= force_reg (GET_MODE (src
), src
);
2361 return gen_rtx_SUBREG (mode
, src
, byte
);
2364 if (GET_MODE_CLASS (mode
) == MODE_CC
|| GET_MODE_CLASS (src_mode
) == MODE_CC
)
2367 if (known_eq (GET_MODE_BITSIZE (mode
), GET_MODE_BITSIZE (src_mode
))
2368 && targetm
.modes_tieable_p (mode
, src_mode
))
2370 rtx x
= gen_lowpart_common (mode
, src
);
2375 if (!int_mode_for_mode (src_mode
).exists (&src_int_mode
)
2376 || !int_mode_for_mode (mode
).exists (&int_mode
))
2379 if (!targetm
.modes_tieable_p (src_int_mode
, src_mode
))
2381 if (!targetm
.modes_tieable_p (int_mode
, mode
))
2384 src
= gen_lowpart (src_int_mode
, src
);
2385 src
= convert_modes (int_mode
, src_int_mode
, src
, true);
2386 src
= gen_lowpart (mode
, src
);
2390 /* Add INC into TARGET. */
2393 expand_inc (rtx target
, rtx inc
)
2395 rtx value
= expand_binop (GET_MODE (target
), add_optab
,
2397 target
, 0, OPTAB_LIB_WIDEN
);
2398 if (value
!= target
)
2399 emit_move_insn (target
, value
);
2402 /* Subtract DEC from TARGET. */
2405 expand_dec (rtx target
, rtx dec
)
2407 rtx value
= expand_binop (GET_MODE (target
), sub_optab
,
2409 target
, 0, OPTAB_LIB_WIDEN
);
2410 if (value
!= target
)
2411 emit_move_insn (target
, value
);
2414 /* Output a shift instruction for expression code CODE,
2415 with SHIFTED being the rtx for the value to shift,
2416 and AMOUNT the rtx for the amount to shift by.
2417 Store the result in the rtx TARGET, if that is convenient.
2418 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2419 Return the rtx for where the value is.
2420 If that cannot be done, abort the compilation unless MAY_FAIL is true,
2421 in which case 0 is returned. */
2424 expand_shift_1 (enum tree_code code
, machine_mode mode
, rtx shifted
,
2425 rtx amount
, rtx target
, int unsignedp
, bool may_fail
= false)
2428 int left
= (code
== LSHIFT_EXPR
|| code
== LROTATE_EXPR
);
2429 int rotate
= (code
== LROTATE_EXPR
|| code
== RROTATE_EXPR
);
2430 optab lshift_optab
= ashl_optab
;
2431 optab rshift_arith_optab
= ashr_optab
;
2432 optab rshift_uns_optab
= lshr_optab
;
2433 optab lrotate_optab
= rotl_optab
;
2434 optab rrotate_optab
= rotr_optab
;
2435 machine_mode op1_mode
;
2436 scalar_mode scalar_mode
= GET_MODE_INNER (mode
);
2438 bool speed
= optimize_insn_for_speed_p ();
2441 op1_mode
= GET_MODE (op1
);
2443 /* Determine whether the shift/rotate amount is a vector, or scalar. If the
2444 shift amount is a vector, use the vector/vector shift patterns. */
2445 if (VECTOR_MODE_P (mode
) && VECTOR_MODE_P (op1_mode
))
2447 lshift_optab
= vashl_optab
;
2448 rshift_arith_optab
= vashr_optab
;
2449 rshift_uns_optab
= vlshr_optab
;
2450 lrotate_optab
= vrotl_optab
;
2451 rrotate_optab
= vrotr_optab
;
2454 /* Previously detected shift-counts computed by NEGATE_EXPR
2455 and shifted in the other direction; but that does not work
2458 if (SHIFT_COUNT_TRUNCATED
)
2460 if (CONST_INT_P (op1
)
2461 && ((unsigned HOST_WIDE_INT
) INTVAL (op1
) >=
2462 (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (scalar_mode
)))
2463 op1
= gen_int_shift_amount (mode
,
2464 (unsigned HOST_WIDE_INT
) INTVAL (op1
)
2465 % GET_MODE_BITSIZE (scalar_mode
));
2466 else if (GET_CODE (op1
) == SUBREG
2467 && subreg_lowpart_p (op1
)
2468 && SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (op1
)))
2469 && SCALAR_INT_MODE_P (GET_MODE (op1
)))
2470 op1
= SUBREG_REG (op1
);
2473 /* Canonicalize rotates by constant amount. If op1 is bitsize / 2,
2474 prefer left rotation, if op1 is from bitsize / 2 + 1 to
2475 bitsize - 1, use other direction of rotate with 1 .. bitsize / 2 - 1
2478 && CONST_INT_P (op1
)
2479 && IN_RANGE (INTVAL (op1
), GET_MODE_BITSIZE (scalar_mode
) / 2 + left
,
2480 GET_MODE_BITSIZE (scalar_mode
) - 1))
2482 op1
= gen_int_shift_amount (mode
, (GET_MODE_BITSIZE (scalar_mode
)
2485 code
= left
? LROTATE_EXPR
: RROTATE_EXPR
;
2488 /* Rotation of 16bit values by 8 bits is effectively equivalent to a bswaphi.
2489 Note that this is not the case for bigger values. For instance a rotation
2490 of 0x01020304 by 16 bits gives 0x03040102 which is different from
2491 0x04030201 (bswapsi). */
2493 && CONST_INT_P (op1
)
2494 && INTVAL (op1
) == BITS_PER_UNIT
2495 && GET_MODE_SIZE (scalar_mode
) == 2
2496 && optab_handler (bswap_optab
, mode
) != CODE_FOR_nothing
)
2497 return expand_unop (mode
, bswap_optab
, shifted
, NULL_RTX
, unsignedp
);
2499 if (op1
== const0_rtx
)
2502 /* Check whether its cheaper to implement a left shift by a constant
2503 bit count by a sequence of additions. */
2504 if (code
== LSHIFT_EXPR
2505 && CONST_INT_P (op1
)
2507 && INTVAL (op1
) < GET_MODE_PRECISION (scalar_mode
)
2508 && INTVAL (op1
) < MAX_BITS_PER_WORD
2509 && (shift_cost (speed
, mode
, INTVAL (op1
))
2510 > INTVAL (op1
) * add_cost (speed
, mode
))
2511 && shift_cost (speed
, mode
, INTVAL (op1
)) != MAX_COST
)
2514 for (i
= 0; i
< INTVAL (op1
); i
++)
2516 temp
= force_reg (mode
, shifted
);
2517 shifted
= expand_binop (mode
, add_optab
, temp
, temp
, NULL_RTX
,
2518 unsignedp
, OPTAB_LIB_WIDEN
);
2523 for (attempt
= 0; temp
== 0 && attempt
< 3; attempt
++)
2525 enum optab_methods methods
;
2528 methods
= OPTAB_DIRECT
;
2529 else if (attempt
== 1)
2530 methods
= OPTAB_WIDEN
;
2532 methods
= OPTAB_LIB_WIDEN
;
2536 /* Widening does not work for rotation. */
2537 if (methods
== OPTAB_WIDEN
)
2539 else if (methods
== OPTAB_LIB_WIDEN
)
2541 /* If we have been unable to open-code this by a rotation,
2542 do it as the IOR of two shifts. I.e., to rotate A
2544 (A << N) | ((unsigned) A >> ((-N) & (C - 1)))
2545 where C is the bitsize of A.
2547 It is theoretically possible that the target machine might
2548 not be able to perform either shift and hence we would
2549 be making two libcalls rather than just the one for the
2550 shift (similarly if IOR could not be done). We will allow
2551 this extremely unlikely lossage to avoid complicating the
2554 rtx subtarget
= target
== shifted
? 0 : target
;
2555 rtx new_amount
, other_amount
;
2559 if (op1
== const0_rtx
)
2561 else if (CONST_INT_P (op1
))
2562 other_amount
= gen_int_shift_amount
2563 (mode
, GET_MODE_BITSIZE (scalar_mode
) - INTVAL (op1
));
2567 = simplify_gen_unary (NEG
, GET_MODE (op1
),
2568 op1
, GET_MODE (op1
));
2569 HOST_WIDE_INT mask
= GET_MODE_PRECISION (scalar_mode
) - 1;
2571 = simplify_gen_binary (AND
, GET_MODE (op1
), other_amount
,
2572 gen_int_mode (mask
, GET_MODE (op1
)));
2575 shifted
= force_reg (mode
, shifted
);
2577 temp
= expand_shift_1 (left
? LSHIFT_EXPR
: RSHIFT_EXPR
,
2578 mode
, shifted
, new_amount
, 0, 1);
2579 temp1
= expand_shift_1 (left
? RSHIFT_EXPR
: LSHIFT_EXPR
,
2580 mode
, shifted
, other_amount
,
2582 return expand_binop (mode
, ior_optab
, temp
, temp1
, target
,
2583 unsignedp
, methods
);
2586 temp
= expand_binop (mode
,
2587 left
? lrotate_optab
: rrotate_optab
,
2588 shifted
, op1
, target
, unsignedp
, methods
);
2591 temp
= expand_binop (mode
,
2592 left
? lshift_optab
: rshift_uns_optab
,
2593 shifted
, op1
, target
, unsignedp
, methods
);
2595 /* Do arithmetic shifts.
2596 Also, if we are going to widen the operand, we can just as well
2597 use an arithmetic right-shift instead of a logical one. */
2598 if (temp
== 0 && ! rotate
2599 && (! unsignedp
|| (! left
&& methods
== OPTAB_WIDEN
)))
2601 enum optab_methods methods1
= methods
;
2603 /* If trying to widen a log shift to an arithmetic shift,
2604 don't accept an arithmetic shift of the same size. */
2606 methods1
= OPTAB_MUST_WIDEN
;
2608 /* Arithmetic shift */
2610 temp
= expand_binop (mode
,
2611 left
? lshift_optab
: rshift_arith_optab
,
2612 shifted
, op1
, target
, unsignedp
, methods1
);
2615 /* We used to try extzv here for logical right shifts, but that was
2616 only useful for one machine, the VAX, and caused poor code
2617 generation there for lshrdi3, so the code was deleted and a
2618 define_expand for lshrsi3 was added to vax.md. */
2621 gcc_assert (temp
!= NULL_RTX
|| may_fail
);
2625 /* Output a shift instruction for expression code CODE,
2626 with SHIFTED being the rtx for the value to shift,
2627 and AMOUNT the amount to shift by.
2628 Store the result in the rtx TARGET, if that is convenient.
2629 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2630 Return the rtx for where the value is. */
2633 expand_shift (enum tree_code code
, machine_mode mode
, rtx shifted
,
2634 poly_int64 amount
, rtx target
, int unsignedp
)
2636 return expand_shift_1 (code
, mode
, shifted
,
2637 gen_int_shift_amount (mode
, amount
),
2641 /* Likewise, but return 0 if that cannot be done. */
2644 maybe_expand_shift (enum tree_code code
, machine_mode mode
, rtx shifted
,
2645 int amount
, rtx target
, int unsignedp
)
2647 return expand_shift_1 (code
, mode
,
2648 shifted
, GEN_INT (amount
), target
, unsignedp
, true);
2651 /* Output a shift instruction for expression code CODE,
2652 with SHIFTED being the rtx for the value to shift,
2653 and AMOUNT the tree for the amount to shift by.
2654 Store the result in the rtx TARGET, if that is convenient.
2655 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
2656 Return the rtx for where the value is. */
2659 expand_variable_shift (enum tree_code code
, machine_mode mode
, rtx shifted
,
2660 tree amount
, rtx target
, int unsignedp
)
2662 return expand_shift_1 (code
, mode
,
2663 shifted
, expand_normal (amount
), target
, unsignedp
);
2667 static void synth_mult (struct algorithm
*, unsigned HOST_WIDE_INT
,
2668 const struct mult_cost
*, machine_mode mode
);
2669 static rtx
expand_mult_const (machine_mode
, rtx
, HOST_WIDE_INT
, rtx
,
2670 const struct algorithm
*, enum mult_variant
);
2671 static unsigned HOST_WIDE_INT
invert_mod2n (unsigned HOST_WIDE_INT
, int);
2672 static rtx
extract_high_half (scalar_int_mode
, rtx
);
2673 static rtx
expmed_mult_highpart (scalar_int_mode
, rtx
, rtx
, rtx
, int, int);
2674 static rtx
expmed_mult_highpart_optab (scalar_int_mode
, rtx
, rtx
, rtx
,
2676 /* Compute and return the best algorithm for multiplying by T.
2677 The algorithm must cost less than cost_limit
2678 If retval.cost >= COST_LIMIT, no algorithm was found and all
2679 other field of the returned struct are undefined.
2680 MODE is the machine mode of the multiplication. */
2683 synth_mult (struct algorithm
*alg_out
, unsigned HOST_WIDE_INT t
,
2684 const struct mult_cost
*cost_limit
, machine_mode mode
)
2687 struct algorithm
*alg_in
, *best_alg
;
2688 struct mult_cost best_cost
;
2689 struct mult_cost new_limit
;
2690 int op_cost
, op_latency
;
2691 unsigned HOST_WIDE_INT orig_t
= t
;
2692 unsigned HOST_WIDE_INT q
;
2693 int maxm
, hash_index
;
2694 bool cache_hit
= false;
2695 enum alg_code cache_alg
= alg_zero
;
2696 bool speed
= optimize_insn_for_speed_p ();
2697 scalar_int_mode imode
;
2698 struct alg_hash_entry
*entry_ptr
;
2700 /* Indicate that no algorithm is yet found. If no algorithm
2701 is found, this value will be returned and indicate failure. */
2702 alg_out
->cost
.cost
= cost_limit
->cost
+ 1;
2703 alg_out
->cost
.latency
= cost_limit
->latency
+ 1;
2705 if (cost_limit
->cost
< 0
2706 || (cost_limit
->cost
== 0 && cost_limit
->latency
<= 0))
2709 /* Be prepared for vector modes. */
2710 imode
= as_a
<scalar_int_mode
> (GET_MODE_INNER (mode
));
2712 maxm
= MIN (BITS_PER_WORD
, GET_MODE_BITSIZE (imode
));
2714 /* Restrict the bits of "t" to the multiplication's mode. */
2715 t
&= GET_MODE_MASK (imode
);
2717 /* t == 1 can be done in zero cost. */
2721 alg_out
->cost
.cost
= 0;
2722 alg_out
->cost
.latency
= 0;
2723 alg_out
->op
[0] = alg_m
;
2727 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2731 if (MULT_COST_LESS (cost_limit
, zero_cost (speed
)))
2736 alg_out
->cost
.cost
= zero_cost (speed
);
2737 alg_out
->cost
.latency
= zero_cost (speed
);
2738 alg_out
->op
[0] = alg_zero
;
2743 /* We'll be needing a couple extra algorithm structures now. */
2745 alg_in
= XALLOCA (struct algorithm
);
2746 best_alg
= XALLOCA (struct algorithm
);
2747 best_cost
= *cost_limit
;
2749 /* Compute the hash index. */
2750 hash_index
= (t
^ (unsigned int) mode
^ (speed
* 256)) % NUM_ALG_HASH_ENTRIES
;
2752 /* See if we already know what to do for T. */
2753 entry_ptr
= alg_hash_entry_ptr (hash_index
);
2754 if (entry_ptr
->t
== t
2755 && entry_ptr
->mode
== mode
2756 && entry_ptr
->speed
== speed
2757 && entry_ptr
->alg
!= alg_unknown
)
2759 cache_alg
= entry_ptr
->alg
;
2761 if (cache_alg
== alg_impossible
)
2763 /* The cache tells us that it's impossible to synthesize
2764 multiplication by T within entry_ptr->cost. */
2765 if (!CHEAPER_MULT_COST (&entry_ptr
->cost
, cost_limit
))
2766 /* COST_LIMIT is at least as restrictive as the one
2767 recorded in the hash table, in which case we have no
2768 hope of synthesizing a multiplication. Just
2772 /* If we get here, COST_LIMIT is less restrictive than the
2773 one recorded in the hash table, so we may be able to
2774 synthesize a multiplication. Proceed as if we didn't
2775 have the cache entry. */
2779 if (CHEAPER_MULT_COST (cost_limit
, &entry_ptr
->cost
))
2780 /* The cached algorithm shows that this multiplication
2781 requires more cost than COST_LIMIT. Just return. This
2782 way, we don't clobber this cache entry with
2783 alg_impossible but retain useful information. */
2795 goto do_alg_addsub_t_m2
;
2797 case alg_add_factor
:
2798 case alg_sub_factor
:
2799 goto do_alg_addsub_factor
;
2802 goto do_alg_add_t2_m
;
2805 goto do_alg_sub_t2_m
;
2813 /* If we have a group of zero bits at the low-order part of T, try
2814 multiplying by the remaining bits and then doing a shift. */
2819 m
= ctz_or_zero (t
); /* m = number of low zero bits */
2823 /* The function expand_shift will choose between a shift and
2824 a sequence of additions, so the observed cost is given as
2825 MIN (m * add_cost(speed, mode), shift_cost(speed, mode, m)). */
2826 op_cost
= m
* add_cost (speed
, mode
);
2827 if (shift_cost (speed
, mode
, m
) < op_cost
)
2828 op_cost
= shift_cost (speed
, mode
, m
);
2829 new_limit
.cost
= best_cost
.cost
- op_cost
;
2830 new_limit
.latency
= best_cost
.latency
- op_cost
;
2831 synth_mult (alg_in
, q
, &new_limit
, mode
);
2833 alg_in
->cost
.cost
+= op_cost
;
2834 alg_in
->cost
.latency
+= op_cost
;
2835 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2837 best_cost
= alg_in
->cost
;
2838 std::swap (alg_in
, best_alg
);
2839 best_alg
->log
[best_alg
->ops
] = m
;
2840 best_alg
->op
[best_alg
->ops
] = alg_shift
;
2843 /* See if treating ORIG_T as a signed number yields a better
2844 sequence. Try this sequence only for a negative ORIG_T
2845 as it would be useless for a non-negative ORIG_T. */
2846 if ((HOST_WIDE_INT
) orig_t
< 0)
2848 /* Shift ORIG_T as follows because a right shift of a
2849 negative-valued signed type is implementation
2851 q
= ~(~orig_t
>> m
);
2852 /* The function expand_shift will choose between a shift
2853 and a sequence of additions, so the observed cost is
2854 given as MIN (m * add_cost(speed, mode),
2855 shift_cost(speed, mode, m)). */
2856 op_cost
= m
* add_cost (speed
, mode
);
2857 if (shift_cost (speed
, mode
, m
) < op_cost
)
2858 op_cost
= shift_cost (speed
, mode
, m
);
2859 new_limit
.cost
= best_cost
.cost
- op_cost
;
2860 new_limit
.latency
= best_cost
.latency
- op_cost
;
2861 synth_mult (alg_in
, q
, &new_limit
, mode
);
2863 alg_in
->cost
.cost
+= op_cost
;
2864 alg_in
->cost
.latency
+= op_cost
;
2865 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2867 best_cost
= alg_in
->cost
;
2868 std::swap (alg_in
, best_alg
);
2869 best_alg
->log
[best_alg
->ops
] = m
;
2870 best_alg
->op
[best_alg
->ops
] = alg_shift
;
2878 /* If we have an odd number, add or subtract one. */
2881 unsigned HOST_WIDE_INT w
;
2884 for (w
= 1; (w
& t
) != 0; w
<<= 1)
2886 /* If T was -1, then W will be zero after the loop. This is another
2887 case where T ends with ...111. Handling this with (T + 1) and
2888 subtract 1 produces slightly better code and results in algorithm
2889 selection much faster than treating it like the ...0111 case
2893 /* Reject the case where t is 3.
2894 Thus we prefer addition in that case. */
2897 /* T ends with ...111. Multiply by (T + 1) and subtract T. */
2899 op_cost
= add_cost (speed
, mode
);
2900 new_limit
.cost
= best_cost
.cost
- op_cost
;
2901 new_limit
.latency
= best_cost
.latency
- op_cost
;
2902 synth_mult (alg_in
, t
+ 1, &new_limit
, mode
);
2904 alg_in
->cost
.cost
+= op_cost
;
2905 alg_in
->cost
.latency
+= op_cost
;
2906 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2908 best_cost
= alg_in
->cost
;
2909 std::swap (alg_in
, best_alg
);
2910 best_alg
->log
[best_alg
->ops
] = 0;
2911 best_alg
->op
[best_alg
->ops
] = alg_sub_t_m2
;
2916 /* T ends with ...01 or ...011. Multiply by (T - 1) and add T. */
2918 op_cost
= add_cost (speed
, mode
);
2919 new_limit
.cost
= best_cost
.cost
- op_cost
;
2920 new_limit
.latency
= best_cost
.latency
- op_cost
;
2921 synth_mult (alg_in
, t
- 1, &new_limit
, mode
);
2923 alg_in
->cost
.cost
+= op_cost
;
2924 alg_in
->cost
.latency
+= op_cost
;
2925 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2927 best_cost
= alg_in
->cost
;
2928 std::swap (alg_in
, best_alg
);
2929 best_alg
->log
[best_alg
->ops
] = 0;
2930 best_alg
->op
[best_alg
->ops
] = alg_add_t_m2
;
2934 /* We may be able to calculate a * -7, a * -15, a * -31, etc
2935 quickly with a - a * n for some appropriate constant n. */
2936 m
= exact_log2 (-orig_t
+ 1);
2937 if (m
>= 0 && m
< maxm
)
2939 op_cost
= add_cost (speed
, mode
) + shift_cost (speed
, mode
, m
);
2940 /* If the target has a cheap shift-and-subtract insn use
2941 that in preference to a shift insn followed by a sub insn.
2942 Assume that the shift-and-sub is "atomic" with a latency
2943 equal to it's cost, otherwise assume that on superscalar
2944 hardware the shift may be executed concurrently with the
2945 earlier steps in the algorithm. */
2946 if (shiftsub1_cost (speed
, mode
, m
) <= op_cost
)
2948 op_cost
= shiftsub1_cost (speed
, mode
, m
);
2949 op_latency
= op_cost
;
2952 op_latency
= add_cost (speed
, mode
);
2954 new_limit
.cost
= best_cost
.cost
- op_cost
;
2955 new_limit
.latency
= best_cost
.latency
- op_latency
;
2956 synth_mult (alg_in
, (unsigned HOST_WIDE_INT
) (-orig_t
+ 1) >> m
,
2959 alg_in
->cost
.cost
+= op_cost
;
2960 alg_in
->cost
.latency
+= op_latency
;
2961 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
2963 best_cost
= alg_in
->cost
;
2964 std::swap (alg_in
, best_alg
);
2965 best_alg
->log
[best_alg
->ops
] = m
;
2966 best_alg
->op
[best_alg
->ops
] = alg_sub_t_m2
;
2974 /* Look for factors of t of the form
2975 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2976 If we find such a factor, we can multiply by t using an algorithm that
2977 multiplies by q, shift the result by m and add/subtract it to itself.
2979 We search for large factors first and loop down, even if large factors
2980 are less probable than small; if we find a large factor we will find a
2981 good sequence quickly, and therefore be able to prune (by decreasing
2982 COST_LIMIT) the search. */
2984 do_alg_addsub_factor
:
2985 for (m
= floor_log2 (t
- 1); m
>= 2; m
--)
2987 unsigned HOST_WIDE_INT d
;
2989 d
= (HOST_WIDE_INT_1U
<< m
) + 1;
2990 if (t
% d
== 0 && t
> d
&& m
< maxm
2991 && (!cache_hit
|| cache_alg
== alg_add_factor
))
2993 op_cost
= add_cost (speed
, mode
) + shift_cost (speed
, mode
, m
);
2994 if (shiftadd_cost (speed
, mode
, m
) <= op_cost
)
2995 op_cost
= shiftadd_cost (speed
, mode
, m
);
2997 op_latency
= op_cost
;
3000 new_limit
.cost
= best_cost
.cost
- op_cost
;
3001 new_limit
.latency
= best_cost
.latency
- op_latency
;
3002 synth_mult (alg_in
, t
/ d
, &new_limit
, mode
);
3004 alg_in
->cost
.cost
+= op_cost
;
3005 alg_in
->cost
.latency
+= op_latency
;
3006 if (alg_in
->cost
.latency
< op_cost
)
3007 alg_in
->cost
.latency
= op_cost
;
3008 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
3010 best_cost
= alg_in
->cost
;
3011 std::swap (alg_in
, best_alg
);
3012 best_alg
->log
[best_alg
->ops
] = m
;
3013 best_alg
->op
[best_alg
->ops
] = alg_add_factor
;
3015 /* Other factors will have been taken care of in the recursion. */
3019 d
= (HOST_WIDE_INT_1U
<< m
) - 1;
3020 if (t
% d
== 0 && t
> d
&& m
< maxm
3021 && (!cache_hit
|| cache_alg
== alg_sub_factor
))
3023 op_cost
= add_cost (speed
, mode
) + shift_cost (speed
, mode
, m
);
3024 if (shiftsub0_cost (speed
, mode
, m
) <= op_cost
)
3025 op_cost
= shiftsub0_cost (speed
, mode
, m
);
3027 op_latency
= op_cost
;
3029 new_limit
.cost
= best_cost
.cost
- op_cost
;
3030 new_limit
.latency
= best_cost
.latency
- op_latency
;
3031 synth_mult (alg_in
, t
/ d
, &new_limit
, mode
);
3033 alg_in
->cost
.cost
+= op_cost
;
3034 alg_in
->cost
.latency
+= op_latency
;
3035 if (alg_in
->cost
.latency
< op_cost
)
3036 alg_in
->cost
.latency
= op_cost
;
3037 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
3039 best_cost
= alg_in
->cost
;
3040 std::swap (alg_in
, best_alg
);
3041 best_alg
->log
[best_alg
->ops
] = m
;
3042 best_alg
->op
[best_alg
->ops
] = alg_sub_factor
;
3050 /* Try shift-and-add (load effective address) instructions,
3051 i.e. do a*3, a*5, a*9. */
3059 op_cost
= shiftadd_cost (speed
, mode
, m
);
3060 new_limit
.cost
= best_cost
.cost
- op_cost
;
3061 new_limit
.latency
= best_cost
.latency
- op_cost
;
3062 synth_mult (alg_in
, (t
- 1) >> m
, &new_limit
, mode
);
3064 alg_in
->cost
.cost
+= op_cost
;
3065 alg_in
->cost
.latency
+= op_cost
;
3066 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
3068 best_cost
= alg_in
->cost
;
3069 std::swap (alg_in
, best_alg
);
3070 best_alg
->log
[best_alg
->ops
] = m
;
3071 best_alg
->op
[best_alg
->ops
] = alg_add_t2_m
;
3082 op_cost
= shiftsub0_cost (speed
, mode
, m
);
3083 new_limit
.cost
= best_cost
.cost
- op_cost
;
3084 new_limit
.latency
= best_cost
.latency
- op_cost
;
3085 synth_mult (alg_in
, (t
+ 1) >> m
, &new_limit
, mode
);
3087 alg_in
->cost
.cost
+= op_cost
;
3088 alg_in
->cost
.latency
+= op_cost
;
3089 if (CHEAPER_MULT_COST (&alg_in
->cost
, &best_cost
))
3091 best_cost
= alg_in
->cost
;
3092 std::swap (alg_in
, best_alg
);
3093 best_alg
->log
[best_alg
->ops
] = m
;
3094 best_alg
->op
[best_alg
->ops
] = alg_sub_t2_m
;
3102 /* If best_cost has not decreased, we have not found any algorithm. */
3103 if (!CHEAPER_MULT_COST (&best_cost
, cost_limit
))
3105 /* We failed to find an algorithm. Record alg_impossible for
3106 this case (that is, <T, MODE, COST_LIMIT>) so that next time
3107 we are asked to find an algorithm for T within the same or
3108 lower COST_LIMIT, we can immediately return to the
3111 entry_ptr
->mode
= mode
;
3112 entry_ptr
->speed
= speed
;
3113 entry_ptr
->alg
= alg_impossible
;
3114 entry_ptr
->cost
= *cost_limit
;
3118 /* Cache the result. */
3122 entry_ptr
->mode
= mode
;
3123 entry_ptr
->speed
= speed
;
3124 entry_ptr
->alg
= best_alg
->op
[best_alg
->ops
];
3125 entry_ptr
->cost
.cost
= best_cost
.cost
;
3126 entry_ptr
->cost
.latency
= best_cost
.latency
;
3129 /* If we are getting a too long sequence for `struct algorithm'
3130 to record, make this search fail. */
3131 if (best_alg
->ops
== MAX_BITS_PER_WORD
)
3134 /* Copy the algorithm from temporary space to the space at alg_out.
3135 We avoid using structure assignment because the majority of
3136 best_alg is normally undefined, and this is a critical function. */
3137 alg_out
->ops
= best_alg
->ops
+ 1;
3138 alg_out
->cost
= best_cost
;
3139 memcpy (alg_out
->op
, best_alg
->op
,
3140 alg_out
->ops
* sizeof *alg_out
->op
);
3141 memcpy (alg_out
->log
, best_alg
->log
,
3142 alg_out
->ops
* sizeof *alg_out
->log
);
3145 /* Find the cheapest way of multiplying a value of mode MODE by VAL.
3146 Try three variations:
3148 - a shift/add sequence based on VAL itself
3149 - a shift/add sequence based on -VAL, followed by a negation
3150 - a shift/add sequence based on VAL - 1, followed by an addition.
3152 Return true if the cheapest of these cost less than MULT_COST,
3153 describing the algorithm in *ALG and final fixup in *VARIANT. */
3156 choose_mult_variant (machine_mode mode
, HOST_WIDE_INT val
,
3157 struct algorithm
*alg
, enum mult_variant
*variant
,
3160 struct algorithm alg2
;
3161 struct mult_cost limit
;
3163 bool speed
= optimize_insn_for_speed_p ();
3165 /* Fail quickly for impossible bounds. */
3169 /* Ensure that mult_cost provides a reasonable upper bound.
3170 Any constant multiplication can be performed with less
3171 than 2 * bits additions. */
3172 op_cost
= 2 * GET_MODE_UNIT_BITSIZE (mode
) * add_cost (speed
, mode
);
3173 if (mult_cost
> op_cost
)
3174 mult_cost
= op_cost
;
3176 *variant
= basic_variant
;
3177 limit
.cost
= mult_cost
;
3178 limit
.latency
= mult_cost
;
3179 synth_mult (alg
, val
, &limit
, mode
);
3181 /* This works only if the inverted value actually fits in an
3183 if (HOST_BITS_PER_INT
>= GET_MODE_UNIT_BITSIZE (mode
))
3185 op_cost
= neg_cost (speed
, mode
);
3186 if (MULT_COST_LESS (&alg
->cost
, mult_cost
))
3188 limit
.cost
= alg
->cost
.cost
- op_cost
;
3189 limit
.latency
= alg
->cost
.latency
- op_cost
;
3193 limit
.cost
= mult_cost
- op_cost
;
3194 limit
.latency
= mult_cost
- op_cost
;
3197 synth_mult (&alg2
, -val
, &limit
, mode
);
3198 alg2
.cost
.cost
+= op_cost
;
3199 alg2
.cost
.latency
+= op_cost
;
3200 if (CHEAPER_MULT_COST (&alg2
.cost
, &alg
->cost
))
3201 *alg
= alg2
, *variant
= negate_variant
;
3204 /* This proves very useful for division-by-constant. */
3205 op_cost
= add_cost (speed
, mode
);
3206 if (MULT_COST_LESS (&alg
->cost
, mult_cost
))
3208 limit
.cost
= alg
->cost
.cost
- op_cost
;
3209 limit
.latency
= alg
->cost
.latency
- op_cost
;
3213 limit
.cost
= mult_cost
- op_cost
;
3214 limit
.latency
= mult_cost
- op_cost
;
3217 synth_mult (&alg2
, val
- 1, &limit
, mode
);
3218 alg2
.cost
.cost
+= op_cost
;
3219 alg2
.cost
.latency
+= op_cost
;
3220 if (CHEAPER_MULT_COST (&alg2
.cost
, &alg
->cost
))
3221 *alg
= alg2
, *variant
= add_variant
;
3223 return MULT_COST_LESS (&alg
->cost
, mult_cost
);
3226 /* A subroutine of expand_mult, used for constant multiplications.
3227 Multiply OP0 by VAL in mode MODE, storing the result in TARGET if
3228 convenient. Use the shift/add sequence described by ALG and apply
3229 the final fixup specified by VARIANT. */
3232 expand_mult_const (machine_mode mode
, rtx op0
, HOST_WIDE_INT val
,
3233 rtx target
, const struct algorithm
*alg
,
3234 enum mult_variant variant
)
3236 unsigned HOST_WIDE_INT val_so_far
;
3242 /* Avoid referencing memory over and over and invalid sharing
3244 op0
= force_reg (mode
, op0
);
3246 /* ACCUM starts out either as OP0 or as a zero, depending on
3247 the first operation. */
3249 if (alg
->op
[0] == alg_zero
)
3251 accum
= copy_to_mode_reg (mode
, CONST0_RTX (mode
));
3254 else if (alg
->op
[0] == alg_m
)
3256 accum
= copy_to_mode_reg (mode
, op0
);
3262 for (opno
= 1; opno
< alg
->ops
; opno
++)
3264 int log
= alg
->log
[opno
];
3265 rtx shift_subtarget
= optimize
? 0 : accum
;
3267 = (opno
== alg
->ops
- 1 && target
!= 0 && variant
!= add_variant
3270 rtx accum_target
= optimize
? 0 : accum
;
3273 switch (alg
->op
[opno
])
3276 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
, log
, NULL_RTX
, 0);
3277 /* REG_EQUAL note will be attached to the following insn. */
3278 emit_move_insn (accum
, tem
);
3283 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
, log
, NULL_RTX
, 0);
3284 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
3285 add_target
? add_target
: accum_target
);
3286 val_so_far
+= HOST_WIDE_INT_1U
<< log
;
3290 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
, log
, NULL_RTX
, 0);
3291 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, tem
),
3292 add_target
? add_target
: accum_target
);
3293 val_so_far
-= HOST_WIDE_INT_1U
<< log
;
3297 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
3298 log
, shift_subtarget
, 0);
3299 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
),
3300 add_target
? add_target
: accum_target
);
3301 val_so_far
= (val_so_far
<< log
) + 1;
3305 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
3306 log
, shift_subtarget
, 0);
3307 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, op0
),
3308 add_target
? add_target
: accum_target
);
3309 val_so_far
= (val_so_far
<< log
) - 1;
3312 case alg_add_factor
:
3313 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
, log
, NULL_RTX
, 0);
3314 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
3315 add_target
? add_target
: accum_target
);
3316 val_so_far
+= val_so_far
<< log
;
3319 case alg_sub_factor
:
3320 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
, log
, NULL_RTX
, 0);
3321 accum
= force_operand (gen_rtx_MINUS (mode
, tem
, accum
),
3323 ? add_target
: (optimize
? 0 : tem
)));
3324 val_so_far
= (val_so_far
<< log
) - val_so_far
;
3331 if (SCALAR_INT_MODE_P (mode
))
3333 /* Write a REG_EQUAL note on the last insn so that we can cse
3334 multiplication sequences. Note that if ACCUM is a SUBREG,
3335 we've set the inner register and must properly indicate that. */
3336 tem
= op0
, nmode
= mode
;
3337 accum_inner
= accum
;
3338 if (GET_CODE (accum
) == SUBREG
)
3340 accum_inner
= SUBREG_REG (accum
);
3341 nmode
= GET_MODE (accum_inner
);
3342 tem
= gen_lowpart (nmode
, op0
);
3345 insn
= get_last_insn ();
3346 set_dst_reg_note (insn
, REG_EQUAL
,
3347 gen_rtx_MULT (nmode
, tem
,
3348 gen_int_mode (val_so_far
, nmode
)),
3353 if (variant
== negate_variant
)
3355 val_so_far
= -val_so_far
;
3356 accum
= expand_unop (mode
, neg_optab
, accum
, target
, 0);
3358 else if (variant
== add_variant
)
3360 val_so_far
= val_so_far
+ 1;
3361 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
), target
);
3364 /* Compare only the bits of val and val_so_far that are significant
3365 in the result mode, to avoid sign-/zero-extension confusion. */
3366 nmode
= GET_MODE_INNER (mode
);
3367 val
&= GET_MODE_MASK (nmode
);
3368 val_so_far
&= GET_MODE_MASK (nmode
);
3369 gcc_assert (val
== (HOST_WIDE_INT
) val_so_far
);
3374 /* Perform a multiplication and return an rtx for the result.
3375 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3376 TARGET is a suggestion for where to store the result (an rtx).
3378 We check specially for a constant integer as OP1.
3379 If you want this check for OP0 as well, then before calling
3380 you should swap the two operands if OP0 would be constant. */
3383 expand_mult (machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3384 int unsignedp
, bool no_libcall
)
3386 enum mult_variant variant
;
3387 struct algorithm algorithm
;
3390 bool speed
= optimize_insn_for_speed_p ();
3391 bool do_trapv
= flag_trapv
&& SCALAR_INT_MODE_P (mode
) && !unsignedp
;
3393 if (CONSTANT_P (op0
))
3394 std::swap (op0
, op1
);
3396 /* For vectors, there are several simplifications that can be made if
3397 all elements of the vector constant are identical. */
3398 scalar_op1
= unwrap_const_vec_duplicate (op1
);
3400 if (INTEGRAL_MODE_P (mode
))
3403 HOST_WIDE_INT coeff
;
3407 if (op1
== CONST0_RTX (mode
))
3409 if (op1
== CONST1_RTX (mode
))
3411 if (op1
== CONSTM1_RTX (mode
))
3412 return expand_unop (mode
, do_trapv
? negv_optab
: neg_optab
,
3418 /* If mode is integer vector mode, check if the backend supports
3419 vector lshift (by scalar or vector) at all. If not, we can't use
3420 synthetized multiply. */
3421 if (GET_MODE_CLASS (mode
) == MODE_VECTOR_INT
3422 && optab_handler (vashl_optab
, mode
) == CODE_FOR_nothing
3423 && optab_handler (ashl_optab
, mode
) == CODE_FOR_nothing
)
3426 /* These are the operations that are potentially turned into
3427 a sequence of shifts and additions. */
3428 mode_bitsize
= GET_MODE_UNIT_BITSIZE (mode
);
3430 /* synth_mult does an `unsigned int' multiply. As long as the mode is
3431 less than or equal in size to `unsigned int' this doesn't matter.
3432 If the mode is larger than `unsigned int', then synth_mult works
3433 only if the constant value exactly fits in an `unsigned int' without
3434 any truncation. This means that multiplying by negative values does
3435 not work; results are off by 2^32 on a 32 bit machine. */
3436 if (CONST_INT_P (scalar_op1
))
3438 coeff
= INTVAL (scalar_op1
);
3441 #if TARGET_SUPPORTS_WIDE_INT
3442 else if (CONST_WIDE_INT_P (scalar_op1
))
3444 else if (CONST_DOUBLE_AS_INT_P (scalar_op1
))
3447 int shift
= wi::exact_log2 (rtx_mode_t (scalar_op1
, mode
));
3448 /* Perfect power of 2 (other than 1, which is handled above). */
3450 return expand_shift (LSHIFT_EXPR
, mode
, op0
,
3451 shift
, target
, unsignedp
);
3458 /* We used to test optimize here, on the grounds that it's better to
3459 produce a smaller program when -O is not used. But this causes
3460 such a terrible slowdown sometimes that it seems better to always
3463 /* Special case powers of two. */
3464 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff
)
3465 && !(is_neg
&& mode_bitsize
> HOST_BITS_PER_WIDE_INT
))
3466 return expand_shift (LSHIFT_EXPR
, mode
, op0
,
3467 floor_log2 (coeff
), target
, unsignedp
);
3469 fake_reg
= gen_raw_REG (mode
, LAST_VIRTUAL_REGISTER
+ 1);
3471 /* Attempt to handle multiplication of DImode values by negative
3472 coefficients, by performing the multiplication by a positive
3473 multiplier and then inverting the result. */
3474 if (is_neg
&& mode_bitsize
> HOST_BITS_PER_WIDE_INT
)
3476 /* Its safe to use -coeff even for INT_MIN, as the
3477 result is interpreted as an unsigned coefficient.
3478 Exclude cost of op0 from max_cost to match the cost
3479 calculation of the synth_mult. */
3480 coeff
= -(unsigned HOST_WIDE_INT
) coeff
;
3481 max_cost
= (set_src_cost (gen_rtx_MULT (mode
, fake_reg
, op1
),
3483 - neg_cost (speed
, mode
));
3487 /* Special case powers of two. */
3488 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff
))
3490 rtx temp
= expand_shift (LSHIFT_EXPR
, mode
, op0
,
3491 floor_log2 (coeff
), target
, unsignedp
);
3492 return expand_unop (mode
, neg_optab
, temp
, target
, 0);
3495 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
,
3498 rtx temp
= expand_mult_const (mode
, op0
, coeff
, NULL_RTX
,
3499 &algorithm
, variant
);
3500 return expand_unop (mode
, neg_optab
, temp
, target
, 0);
3505 /* Exclude cost of op0 from max_cost to match the cost
3506 calculation of the synth_mult. */
3507 max_cost
= set_src_cost (gen_rtx_MULT (mode
, fake_reg
, op1
), mode
, speed
);
3508 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
, max_cost
))
3509 return expand_mult_const (mode
, op0
, coeff
, target
,
3510 &algorithm
, variant
);
3514 /* Expand x*2.0 as x+x. */
3515 if (CONST_DOUBLE_AS_FLOAT_P (scalar_op1
)
3516 && real_equal (CONST_DOUBLE_REAL_VALUE (scalar_op1
), &dconst2
))
3518 op0
= force_reg (GET_MODE (op0
), op0
);
3519 return expand_binop (mode
, add_optab
, op0
, op0
,
3521 no_libcall
? OPTAB_WIDEN
: OPTAB_LIB_WIDEN
);
3524 /* This used to use umul_optab if unsigned, but for non-widening multiply
3525 there is no difference between signed and unsigned. */
3526 op0
= expand_binop (mode
, do_trapv
? smulv_optab
: smul_optab
,
3527 op0
, op1
, target
, unsignedp
,
3528 no_libcall
? OPTAB_WIDEN
: OPTAB_LIB_WIDEN
);
3529 gcc_assert (op0
|| no_libcall
);
3533 /* Return a cost estimate for multiplying a register by the given
3534 COEFFicient in the given MODE and SPEED. */
3537 mult_by_coeff_cost (HOST_WIDE_INT coeff
, machine_mode mode
, bool speed
)
3540 struct algorithm algorithm
;
3541 enum mult_variant variant
;
3543 rtx fake_reg
= gen_raw_REG (mode
, LAST_VIRTUAL_REGISTER
+ 1);
3544 max_cost
= set_src_cost (gen_rtx_MULT (mode
, fake_reg
, fake_reg
),
3546 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
, max_cost
))
3547 return algorithm
.cost
.cost
;
3552 /* Perform a widening multiplication and return an rtx for the result.
3553 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
3554 TARGET is a suggestion for where to store the result (an rtx).
3555 THIS_OPTAB is the optab we should use, it must be either umul_widen_optab
3556 or smul_widen_optab.
3558 We check specially for a constant integer as OP1, comparing the
3559 cost of a widening multiply against the cost of a sequence of shifts
3563 expand_widening_mult (machine_mode mode
, rtx op0
, rtx op1
, rtx target
,
3564 int unsignedp
, optab this_optab
)
3566 bool speed
= optimize_insn_for_speed_p ();
3569 if (CONST_INT_P (op1
)
3570 && GET_MODE (op0
) != VOIDmode
3571 && (cop1
= convert_modes (mode
, GET_MODE (op0
), op1
,
3572 this_optab
== umul_widen_optab
))
3573 && CONST_INT_P (cop1
)
3574 && (INTVAL (cop1
) >= 0
3575 || HWI_COMPUTABLE_MODE_P (mode
)))
3577 HOST_WIDE_INT coeff
= INTVAL (cop1
);
3579 enum mult_variant variant
;
3580 struct algorithm algorithm
;
3583 return CONST0_RTX (mode
);
3585 /* Special case powers of two. */
3586 if (EXACT_POWER_OF_2_OR_ZERO_P (coeff
))
3588 op0
= convert_to_mode (mode
, op0
, this_optab
== umul_widen_optab
);
3589 return expand_shift (LSHIFT_EXPR
, mode
, op0
,
3590 floor_log2 (coeff
), target
, unsignedp
);
3593 /* Exclude cost of op0 from max_cost to match the cost
3594 calculation of the synth_mult. */
3595 max_cost
= mul_widen_cost (speed
, mode
);
3596 if (choose_mult_variant (mode
, coeff
, &algorithm
, &variant
,
3599 op0
= convert_to_mode (mode
, op0
, this_optab
== umul_widen_optab
);
3600 return expand_mult_const (mode
, op0
, coeff
, target
,
3601 &algorithm
, variant
);
3604 return expand_binop (mode
, this_optab
, op0
, op1
, target
,
3605 unsignedp
, OPTAB_LIB_WIDEN
);
3608 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
3609 replace division by D, and put the least significant N bits of the result
3610 in *MULTIPLIER_PTR and return the most significant bit.
3612 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
3613 needed precision is in PRECISION (should be <= N).
3615 PRECISION should be as small as possible so this function can choose
3616 multiplier more freely.
3618 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
3619 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
3621 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
3622 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
3624 unsigned HOST_WIDE_INT
3625 choose_multiplier (unsigned HOST_WIDE_INT d
, int n
, int precision
,
3626 unsigned HOST_WIDE_INT
*multiplier_ptr
,
3627 int *post_shift_ptr
, int *lgup_ptr
)
3629 int lgup
, post_shift
;
3632 /* lgup = ceil(log2(divisor)); */
3633 lgup
= ceil_log2 (d
);
3635 gcc_assert (lgup
<= n
);
3638 pow2
= n
+ lgup
- precision
;
3640 /* mlow = 2^(N + lgup)/d */
3641 wide_int val
= wi::set_bit_in_zero (pow
, HOST_BITS_PER_DOUBLE_INT
);
3642 wide_int mlow
= wi::udiv_trunc (val
, d
);
3644 /* mhigh = (2^(N + lgup) + 2^(N + lgup - precision))/d */
3645 val
|= wi::set_bit_in_zero (pow2
, HOST_BITS_PER_DOUBLE_INT
);
3646 wide_int mhigh
= wi::udiv_trunc (val
, d
);
3648 /* If precision == N, then mlow, mhigh exceed 2^N
3649 (but they do not exceed 2^(N+1)). */
3651 /* Reduce to lowest terms. */
3652 for (post_shift
= lgup
; post_shift
> 0; post_shift
--)
3654 unsigned HOST_WIDE_INT ml_lo
= wi::extract_uhwi (mlow
, 1,
3655 HOST_BITS_PER_WIDE_INT
);
3656 unsigned HOST_WIDE_INT mh_lo
= wi::extract_uhwi (mhigh
, 1,
3657 HOST_BITS_PER_WIDE_INT
);
3661 mlow
= wi::uhwi (ml_lo
, HOST_BITS_PER_DOUBLE_INT
);
3662 mhigh
= wi::uhwi (mh_lo
, HOST_BITS_PER_DOUBLE_INT
);
3665 *post_shift_ptr
= post_shift
;
3667 if (n
< HOST_BITS_PER_WIDE_INT
)
3669 unsigned HOST_WIDE_INT mask
= (HOST_WIDE_INT_1U
<< n
) - 1;
3670 *multiplier_ptr
= mhigh
.to_uhwi () & mask
;
3671 return mhigh
.to_uhwi () >= mask
;
3675 *multiplier_ptr
= mhigh
.to_uhwi ();
3676 return wi::extract_uhwi (mhigh
, HOST_BITS_PER_WIDE_INT
, 1);
3680 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
3681 congruent to 1 (mod 2**N). */
3683 static unsigned HOST_WIDE_INT
3684 invert_mod2n (unsigned HOST_WIDE_INT x
, int n
)
3686 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
3688 /* The algorithm notes that the choice y = x satisfies
3689 x*y == 1 mod 2^3, since x is assumed odd.
3690 Each iteration doubles the number of bits of significance in y. */
3692 unsigned HOST_WIDE_INT mask
;
3693 unsigned HOST_WIDE_INT y
= x
;
3696 mask
= (n
== HOST_BITS_PER_WIDE_INT
3698 : (HOST_WIDE_INT_1U
<< n
) - 1);
3702 y
= y
* (2 - x
*y
) & mask
; /* Modulo 2^N */
3708 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
3709 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
3710 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
3711 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
3714 The result is put in TARGET if that is convenient.
3716 MODE is the mode of operation. */
3719 expand_mult_highpart_adjust (scalar_int_mode mode
, rtx adj_operand
, rtx op0
,
3720 rtx op1
, rtx target
, int unsignedp
)
3723 enum rtx_code adj_code
= unsignedp
? PLUS
: MINUS
;
3725 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
3726 GET_MODE_BITSIZE (mode
) - 1, NULL_RTX
, 0);
3727 tem
= expand_and (mode
, tem
, op1
, NULL_RTX
);
3729 = force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
3732 tem
= expand_shift (RSHIFT_EXPR
, mode
, op1
,
3733 GET_MODE_BITSIZE (mode
) - 1, NULL_RTX
, 0);
3734 tem
= expand_and (mode
, tem
, op0
, NULL_RTX
);
3735 target
= force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
3741 /* Subroutine of expmed_mult_highpart. Return the MODE high part of OP. */
3744 extract_high_half (scalar_int_mode mode
, rtx op
)
3746 if (mode
== word_mode
)
3747 return gen_highpart (mode
, op
);
3749 scalar_int_mode wider_mode
= GET_MODE_WIDER_MODE (mode
).require ();
3751 op
= expand_shift (RSHIFT_EXPR
, wider_mode
, op
,
3752 GET_MODE_BITSIZE (mode
), 0, 1);
3753 return convert_modes (mode
, wider_mode
, op
, 0);
3756 /* Like expmed_mult_highpart, but only consider using a multiplication
3757 optab. OP1 is an rtx for the constant operand. */
3760 expmed_mult_highpart_optab (scalar_int_mode mode
, rtx op0
, rtx op1
,
3761 rtx target
, int unsignedp
, int max_cost
)
3763 rtx narrow_op1
= gen_int_mode (INTVAL (op1
), mode
);
3767 bool speed
= optimize_insn_for_speed_p ();
3769 scalar_int_mode wider_mode
= GET_MODE_WIDER_MODE (mode
).require ();
3771 size
= GET_MODE_BITSIZE (mode
);
3773 /* Firstly, try using a multiplication insn that only generates the needed
3774 high part of the product, and in the sign flavor of unsignedp. */
3775 if (mul_highpart_cost (speed
, mode
) < max_cost
)
3777 moptab
= unsignedp
? umul_highpart_optab
: smul_highpart_optab
;
3778 tem
= expand_binop (mode
, moptab
, op0
, narrow_op1
, target
,
3779 unsignedp
, OPTAB_DIRECT
);
3784 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
3785 Need to adjust the result after the multiplication. */
3786 if (size
- 1 < BITS_PER_WORD
3787 && (mul_highpart_cost (speed
, mode
)
3788 + 2 * shift_cost (speed
, mode
, size
-1)
3789 + 4 * add_cost (speed
, mode
) < max_cost
))
3791 moptab
= unsignedp
? smul_highpart_optab
: umul_highpart_optab
;
3792 tem
= expand_binop (mode
, moptab
, op0
, narrow_op1
, target
,
3793 unsignedp
, OPTAB_DIRECT
);
3795 /* We used the wrong signedness. Adjust the result. */
3796 return expand_mult_highpart_adjust (mode
, tem
, op0
, narrow_op1
,
3800 /* Try widening multiplication. */
3801 moptab
= unsignedp
? umul_widen_optab
: smul_widen_optab
;
3802 if (convert_optab_handler (moptab
, wider_mode
, mode
) != CODE_FOR_nothing
3803 && mul_widen_cost (speed
, wider_mode
) < max_cost
)
3805 tem
= expand_binop (wider_mode
, moptab
, op0
, narrow_op1
, 0,
3806 unsignedp
, OPTAB_WIDEN
);
3808 return extract_high_half (mode
, tem
);
3811 /* Try widening the mode and perform a non-widening multiplication. */
3812 if (optab_handler (smul_optab
, wider_mode
) != CODE_FOR_nothing
3813 && size
- 1 < BITS_PER_WORD
3814 && (mul_cost (speed
, wider_mode
) + shift_cost (speed
, mode
, size
-1)
3820 /* We need to widen the operands, for example to ensure the
3821 constant multiplier is correctly sign or zero extended.
3822 Use a sequence to clean-up any instructions emitted by
3823 the conversions if things don't work out. */
3825 wop0
= convert_modes (wider_mode
, mode
, op0
, unsignedp
);
3826 wop1
= convert_modes (wider_mode
, mode
, op1
, unsignedp
);
3827 tem
= expand_binop (wider_mode
, smul_optab
, wop0
, wop1
, 0,
3828 unsignedp
, OPTAB_WIDEN
);
3829 insns
= get_insns ();
3835 return extract_high_half (mode
, tem
);
3839 /* Try widening multiplication of opposite signedness, and adjust. */
3840 moptab
= unsignedp
? smul_widen_optab
: umul_widen_optab
;
3841 if (convert_optab_handler (moptab
, wider_mode
, mode
) != CODE_FOR_nothing
3842 && size
- 1 < BITS_PER_WORD
3843 && (mul_widen_cost (speed
, wider_mode
)
3844 + 2 * shift_cost (speed
, mode
, size
-1)
3845 + 4 * add_cost (speed
, mode
) < max_cost
))
3847 tem
= expand_binop (wider_mode
, moptab
, op0
, narrow_op1
,
3848 NULL_RTX
, ! unsignedp
, OPTAB_WIDEN
);
3851 tem
= extract_high_half (mode
, tem
);
3852 /* We used the wrong signedness. Adjust the result. */
3853 return expand_mult_highpart_adjust (mode
, tem
, op0
, narrow_op1
,
3861 /* Emit code to multiply OP0 and OP1 (where OP1 is an integer constant),
3862 putting the high half of the result in TARGET if that is convenient,
3863 and return where the result is. If the operation can not be performed,
3866 MODE is the mode of operation and result.
3868 UNSIGNEDP nonzero means unsigned multiply.
3870 MAX_COST is the total allowed cost for the expanded RTL. */
3873 expmed_mult_highpart (scalar_int_mode mode
, rtx op0
, rtx op1
,
3874 rtx target
, int unsignedp
, int max_cost
)
3876 unsigned HOST_WIDE_INT cnst1
;
3878 bool sign_adjust
= false;
3879 enum mult_variant variant
;
3880 struct algorithm alg
;
3882 bool speed
= optimize_insn_for_speed_p ();
3884 /* We can't support modes wider than HOST_BITS_PER_INT. */
3885 gcc_assert (HWI_COMPUTABLE_MODE_P (mode
));
3887 cnst1
= INTVAL (op1
) & GET_MODE_MASK (mode
);
3889 /* We can't optimize modes wider than BITS_PER_WORD.
3890 ??? We might be able to perform double-word arithmetic if
3891 mode == word_mode, however all the cost calculations in
3892 synth_mult etc. assume single-word operations. */
3893 scalar_int_mode wider_mode
= GET_MODE_WIDER_MODE (mode
).require ();
3894 if (GET_MODE_BITSIZE (wider_mode
) > BITS_PER_WORD
)
3895 return expmed_mult_highpart_optab (mode
, op0
, op1
, target
,
3896 unsignedp
, max_cost
);
3898 extra_cost
= shift_cost (speed
, mode
, GET_MODE_BITSIZE (mode
) - 1);
3900 /* Check whether we try to multiply by a negative constant. */
3901 if (!unsignedp
&& ((cnst1
>> (GET_MODE_BITSIZE (mode
) - 1)) & 1))
3904 extra_cost
+= add_cost (speed
, mode
);
3907 /* See whether shift/add multiplication is cheap enough. */
3908 if (choose_mult_variant (wider_mode
, cnst1
, &alg
, &variant
,
3909 max_cost
- extra_cost
))
3911 /* See whether the specialized multiplication optabs are
3912 cheaper than the shift/add version. */
3913 tem
= expmed_mult_highpart_optab (mode
, op0
, op1
, target
, unsignedp
,
3914 alg
.cost
.cost
+ extra_cost
);
3918 tem
= convert_to_mode (wider_mode
, op0
, unsignedp
);
3919 tem
= expand_mult_const (wider_mode
, tem
, cnst1
, 0, &alg
, variant
);
3920 tem
= extract_high_half (mode
, tem
);
3922 /* Adjust result for signedness. */
3924 tem
= force_operand (gen_rtx_MINUS (mode
, tem
, op0
), tem
);
3928 return expmed_mult_highpart_optab (mode
, op0
, op1
, target
,
3929 unsignedp
, max_cost
);
3933 /* Expand signed modulus of OP0 by a power of two D in mode MODE. */
3936 expand_smod_pow2 (scalar_int_mode mode
, rtx op0
, HOST_WIDE_INT d
)
3938 rtx result
, temp
, shift
;
3939 rtx_code_label
*label
;
3941 int prec
= GET_MODE_PRECISION (mode
);
3943 logd
= floor_log2 (d
);
3944 result
= gen_reg_rtx (mode
);
3946 /* Avoid conditional branches when they're expensive. */
3947 if (BRANCH_COST (optimize_insn_for_speed_p (), false) >= 2
3948 && optimize_insn_for_speed_p ())
3950 rtx signmask
= emit_store_flag (result
, LT
, op0
, const0_rtx
,
3954 HOST_WIDE_INT masklow
= (HOST_WIDE_INT_1
<< logd
) - 1;
3955 signmask
= force_reg (mode
, signmask
);
3956 shift
= gen_int_shift_amount (mode
, GET_MODE_BITSIZE (mode
) - logd
);
3958 /* Use the rtx_cost of a LSHIFTRT instruction to determine
3959 which instruction sequence to use. If logical right shifts
3960 are expensive the use 2 XORs, 2 SUBs and an AND, otherwise
3961 use a LSHIFTRT, 1 ADD, 1 SUB and an AND. */
3963 temp
= gen_rtx_LSHIFTRT (mode
, result
, shift
);
3964 if (optab_handler (lshr_optab
, mode
) == CODE_FOR_nothing
3965 || (set_src_cost (temp
, mode
, optimize_insn_for_speed_p ())
3966 > COSTS_N_INSNS (2)))
3968 temp
= expand_binop (mode
, xor_optab
, op0
, signmask
,
3969 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3970 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3971 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3972 temp
= expand_binop (mode
, and_optab
, temp
,
3973 gen_int_mode (masklow
, mode
),
3974 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3975 temp
= expand_binop (mode
, xor_optab
, temp
, signmask
,
3976 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3977 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3978 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3982 signmask
= expand_binop (mode
, lshr_optab
, signmask
, shift
,
3983 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3984 signmask
= force_reg (mode
, signmask
);
3986 temp
= expand_binop (mode
, add_optab
, op0
, signmask
,
3987 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3988 temp
= expand_binop (mode
, and_optab
, temp
,
3989 gen_int_mode (masklow
, mode
),
3990 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3991 temp
= expand_binop (mode
, sub_optab
, temp
, signmask
,
3992 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3998 /* Mask contains the mode's signbit and the significant bits of the
3999 modulus. By including the signbit in the operation, many targets
4000 can avoid an explicit compare operation in the following comparison
4002 wide_int mask
= wi::mask (logd
, false, prec
);
4003 mask
= wi::set_bit (mask
, prec
- 1);
4005 temp
= expand_binop (mode
, and_optab
, op0
,
4006 immed_wide_int_const (mask
, mode
),
4007 result
, 1, OPTAB_LIB_WIDEN
);
4009 emit_move_insn (result
, temp
);
4011 label
= gen_label_rtx ();
4012 do_cmp_and_jump (result
, const0_rtx
, GE
, mode
, label
);
4014 temp
= expand_binop (mode
, sub_optab
, result
, const1_rtx
, result
,
4015 0, OPTAB_LIB_WIDEN
);
4017 mask
= wi::mask (logd
, true, prec
);
4018 temp
= expand_binop (mode
, ior_optab
, temp
,
4019 immed_wide_int_const (mask
, mode
),
4020 result
, 1, OPTAB_LIB_WIDEN
);
4021 temp
= expand_binop (mode
, add_optab
, temp
, const1_rtx
, result
,
4022 0, OPTAB_LIB_WIDEN
);
4024 emit_move_insn (result
, temp
);
4029 /* Expand signed division of OP0 by a power of two D in mode MODE.
4030 This routine is only called for positive values of D. */
4033 expand_sdiv_pow2 (scalar_int_mode mode
, rtx op0
, HOST_WIDE_INT d
)
4036 rtx_code_label
*label
;
4039 logd
= floor_log2 (d
);
4042 && BRANCH_COST (optimize_insn_for_speed_p (),
4045 temp
= gen_reg_rtx (mode
);
4046 temp
= emit_store_flag (temp
, LT
, op0
, const0_rtx
, mode
, 0, 1);
4047 temp
= expand_binop (mode
, add_optab
, temp
, op0
, NULL_RTX
,
4048 0, OPTAB_LIB_WIDEN
);
4049 return expand_shift (RSHIFT_EXPR
, mode
, temp
, logd
, NULL_RTX
, 0);
4052 if (HAVE_conditional_move
4053 && BRANCH_COST (optimize_insn_for_speed_p (), false) >= 2)
4058 temp2
= copy_to_mode_reg (mode
, op0
);
4059 temp
= expand_binop (mode
, add_optab
, temp2
, gen_int_mode (d
- 1, mode
),
4060 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
4061 temp
= force_reg (mode
, temp
);
4063 /* Construct "temp2 = (temp2 < 0) ? temp : temp2". */
4064 temp2
= emit_conditional_move (temp2
, LT
, temp2
, const0_rtx
,
4065 mode
, temp
, temp2
, mode
, 0);
4068 rtx_insn
*seq
= get_insns ();
4071 return expand_shift (RSHIFT_EXPR
, mode
, temp2
, logd
, NULL_RTX
, 0);
4076 if (BRANCH_COST (optimize_insn_for_speed_p (),
4079 int ushift
= GET_MODE_BITSIZE (mode
) - logd
;
4081 temp
= gen_reg_rtx (mode
);
4082 temp
= emit_store_flag (temp
, LT
, op0
, const0_rtx
, mode
, 0, -1);
4083 if (GET_MODE_BITSIZE (mode
) >= BITS_PER_WORD
4084 || shift_cost (optimize_insn_for_speed_p (), mode
, ushift
)
4085 > COSTS_N_INSNS (1))
4086 temp
= expand_binop (mode
, and_optab
, temp
, gen_int_mode (d
- 1, mode
),
4087 NULL_RTX
, 0, OPTAB_LIB_WIDEN
);
4089 temp
= expand_shift (RSHIFT_EXPR
, mode
, temp
,
4090 ushift
, NULL_RTX
, 1);
4091 temp
= expand_binop (mode
, add_optab
, temp
, op0
, NULL_RTX
,
4092 0, OPTAB_LIB_WIDEN
);
4093 return expand_shift (RSHIFT_EXPR
, mode
, temp
, logd
, NULL_RTX
, 0);
4096 label
= gen_label_rtx ();
4097 temp
= copy_to_mode_reg (mode
, op0
);
4098 do_cmp_and_jump (temp
, const0_rtx
, GE
, mode
, label
);
4099 expand_inc (temp
, gen_int_mode (d
- 1, mode
));
4101 return expand_shift (RSHIFT_EXPR
, mode
, temp
, logd
, NULL_RTX
, 0);
4104 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
4105 if that is convenient, and returning where the result is.
4106 You may request either the quotient or the remainder as the result;
4107 specify REM_FLAG nonzero to get the remainder.
4109 CODE is the expression code for which kind of division this is;
4110 it controls how rounding is done. MODE is the machine mode to use.
4111 UNSIGNEDP nonzero means do unsigned division. */
4113 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
4114 and then correct it by or'ing in missing high bits
4115 if result of ANDI is nonzero.
4116 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
4117 This could optimize to a bfexts instruction.
4118 But C doesn't use these operations, so their optimizations are
4120 /* ??? For modulo, we don't actually need the highpart of the first product,
4121 the low part will do nicely. And for small divisors, the second multiply
4122 can also be a low-part only multiply or even be completely left out.
4123 E.g. to calculate the remainder of a division by 3 with a 32 bit
4124 multiply, multiply with 0x55555556 and extract the upper two bits;
4125 the result is exact for inputs up to 0x1fffffff.
4126 The input range can be reduced by using cross-sum rules.
4127 For odd divisors >= 3, the following table gives right shift counts
4128 so that if a number is shifted by an integer multiple of the given
4129 amount, the remainder stays the same:
4130 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
4131 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
4132 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
4133 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
4134 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
4136 Cross-sum rules for even numbers can be derived by leaving as many bits
4137 to the right alone as the divisor has zeros to the right.
4138 E.g. if x is an unsigned 32 bit number:
4139 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
4143 expand_divmod (int rem_flag
, enum tree_code code
, machine_mode mode
,
4144 rtx op0
, rtx op1
, rtx target
, int unsignedp
)
4146 machine_mode compute_mode
;
4148 rtx quotient
= 0, remainder
= 0;
4151 optab optab1
, optab2
;
4152 int op1_is_constant
, op1_is_pow2
= 0;
4153 int max_cost
, extra_cost
;
4154 static HOST_WIDE_INT last_div_const
= 0;
4155 bool speed
= optimize_insn_for_speed_p ();
4157 op1_is_constant
= CONST_INT_P (op1
);
4158 if (op1_is_constant
)
4160 wide_int ext_op1
= rtx_mode_t (op1
, mode
);
4161 op1_is_pow2
= (wi::popcount (ext_op1
) == 1
4163 && wi::popcount (wi::neg (ext_op1
)) == 1));
4167 This is the structure of expand_divmod:
4169 First comes code to fix up the operands so we can perform the operations
4170 correctly and efficiently.
4172 Second comes a switch statement with code specific for each rounding mode.
4173 For some special operands this code emits all RTL for the desired
4174 operation, for other cases, it generates only a quotient and stores it in
4175 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
4176 to indicate that it has not done anything.
4178 Last comes code that finishes the operation. If QUOTIENT is set and
4179 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
4180 QUOTIENT is not set, it is computed using trunc rounding.
4182 We try to generate special code for division and remainder when OP1 is a
4183 constant. If |OP1| = 2**n we can use shifts and some other fast
4184 operations. For other values of OP1, we compute a carefully selected
4185 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
4188 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
4189 half of the product. Different strategies for generating the product are
4190 implemented in expmed_mult_highpart.
4192 If what we actually want is the remainder, we generate that by another
4193 by-constant multiplication and a subtraction. */
4195 /* We shouldn't be called with OP1 == const1_rtx, but some of the
4196 code below will malfunction if we are, so check here and handle
4197 the special case if so. */
4198 if (op1
== const1_rtx
)
4199 return rem_flag
? const0_rtx
: op0
;
4201 /* When dividing by -1, we could get an overflow.
4202 negv_optab can handle overflows. */
4203 if (! unsignedp
&& op1
== constm1_rtx
)
4207 return expand_unop (mode
, flag_trapv
&& GET_MODE_CLASS (mode
) == MODE_INT
4208 ? negv_optab
: neg_optab
, op0
, target
, 0);
4212 /* Don't use the function value register as a target
4213 since we have to read it as well as write it,
4214 and function-inlining gets confused by this. */
4215 && ((REG_P (target
) && REG_FUNCTION_VALUE_P (target
))
4216 /* Don't clobber an operand while doing a multi-step calculation. */
4217 || ((rem_flag
|| op1_is_constant
)
4218 && (reg_mentioned_p (target
, op0
)
4219 || (MEM_P (op0
) && MEM_P (target
))))
4220 || reg_mentioned_p (target
, op1
)
4221 || (MEM_P (op1
) && MEM_P (target
))))
4224 /* Get the mode in which to perform this computation. Normally it will
4225 be MODE, but sometimes we can't do the desired operation in MODE.
4226 If so, pick a wider mode in which we can do the operation. Convert
4227 to that mode at the start to avoid repeated conversions.
4229 First see what operations we need. These depend on the expression
4230 we are evaluating. (We assume that divxx3 insns exist under the
4231 same conditions that modxx3 insns and that these insns don't normally
4232 fail. If these assumptions are not correct, we may generate less
4233 efficient code in some cases.)
4235 Then see if we find a mode in which we can open-code that operation
4236 (either a division, modulus, or shift). Finally, check for the smallest
4237 mode for which we can do the operation with a library call. */
4239 /* We might want to refine this now that we have division-by-constant
4240 optimization. Since expmed_mult_highpart tries so many variants, it is
4241 not straightforward to generalize this. Maybe we should make an array
4242 of possible modes in init_expmed? Save this for GCC 2.7. */
4244 optab1
= (op1_is_pow2
4245 ? (unsignedp
? lshr_optab
: ashr_optab
)
4246 : (unsignedp
? udiv_optab
: sdiv_optab
));
4247 optab2
= (op1_is_pow2
? optab1
4248 : (unsignedp
? udivmod_optab
: sdivmod_optab
));
4250 FOR_EACH_MODE_FROM (compute_mode
, mode
)
4251 if (optab_handler (optab1
, compute_mode
) != CODE_FOR_nothing
4252 || optab_handler (optab2
, compute_mode
) != CODE_FOR_nothing
)
4255 if (compute_mode
== VOIDmode
)
4256 FOR_EACH_MODE_FROM (compute_mode
, mode
)
4257 if (optab_libfunc (optab1
, compute_mode
)
4258 || optab_libfunc (optab2
, compute_mode
))
4261 /* If we still couldn't find a mode, use MODE, but expand_binop will
4263 if (compute_mode
== VOIDmode
)
4264 compute_mode
= mode
;
4266 if (target
&& GET_MODE (target
) == compute_mode
)
4269 tquotient
= gen_reg_rtx (compute_mode
);
4272 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
4273 (mode), and thereby get better code when OP1 is a constant. Do that
4274 later. It will require going over all usages of SIZE below. */
4275 size
= GET_MODE_BITSIZE (mode
);
4278 /* Only deduct something for a REM if the last divide done was
4279 for a different constant. Then set the constant of the last
4281 max_cost
= (unsignedp
4282 ? udiv_cost (speed
, compute_mode
)
4283 : sdiv_cost (speed
, compute_mode
));
4284 if (rem_flag
&& ! (last_div_const
!= 0 && op1_is_constant
4285 && INTVAL (op1
) == last_div_const
))
4286 max_cost
-= (mul_cost (speed
, compute_mode
)
4287 + add_cost (speed
, compute_mode
));
4289 last_div_const
= ! rem_flag
&& op1_is_constant
? INTVAL (op1
) : 0;
4291 /* Now convert to the best mode to use. */
4292 if (compute_mode
!= mode
)
4294 op0
= convert_modes (compute_mode
, mode
, op0
, unsignedp
);
4295 op1
= convert_modes (compute_mode
, mode
, op1
, unsignedp
);
4297 /* convert_modes may have placed op1 into a register, so we
4298 must recompute the following. */
4299 op1_is_constant
= CONST_INT_P (op1
);
4300 if (op1_is_constant
)
4302 wide_int ext_op1
= rtx_mode_t (op1
, compute_mode
);
4303 op1_is_pow2
= (wi::popcount (ext_op1
) == 1
4305 && wi::popcount (wi::neg (ext_op1
)) == 1));
4311 /* If one of the operands is a volatile MEM, copy it into a register. */
4313 if (MEM_P (op0
) && MEM_VOLATILE_P (op0
))
4314 op0
= force_reg (compute_mode
, op0
);
4315 if (MEM_P (op1
) && MEM_VOLATILE_P (op1
))
4316 op1
= force_reg (compute_mode
, op1
);
4318 /* If we need the remainder or if OP1 is constant, we need to
4319 put OP0 in a register in case it has any queued subexpressions. */
4320 if (rem_flag
|| op1_is_constant
)
4321 op0
= force_reg (compute_mode
, op0
);
4323 last
= get_last_insn ();
4325 /* Promote floor rounding to trunc rounding for unsigned operations. */
4328 if (code
== FLOOR_DIV_EXPR
)
4329 code
= TRUNC_DIV_EXPR
;
4330 if (code
== FLOOR_MOD_EXPR
)
4331 code
= TRUNC_MOD_EXPR
;
4332 if (code
== EXACT_DIV_EXPR
&& op1_is_pow2
)
4333 code
= TRUNC_DIV_EXPR
;
4336 if (op1
!= const0_rtx
)
4339 case TRUNC_MOD_EXPR
:
4340 case TRUNC_DIV_EXPR
:
4341 if (op1_is_constant
)
4343 scalar_int_mode int_mode
= as_a
<scalar_int_mode
> (compute_mode
);
4344 int size
= GET_MODE_BITSIZE (int_mode
);
4347 unsigned HOST_WIDE_INT mh
, ml
;
4348 int pre_shift
, post_shift
;
4350 wide_int wd
= rtx_mode_t (op1
, int_mode
);
4351 unsigned HOST_WIDE_INT d
= wd
.to_uhwi ();
4353 if (wi::popcount (wd
) == 1)
4355 pre_shift
= floor_log2 (d
);
4358 unsigned HOST_WIDE_INT mask
4359 = (HOST_WIDE_INT_1U
<< pre_shift
) - 1;
4361 = expand_binop (int_mode
, and_optab
, op0
,
4362 gen_int_mode (mask
, int_mode
),
4366 return gen_lowpart (mode
, remainder
);
4368 quotient
= expand_shift (RSHIFT_EXPR
, int_mode
, op0
,
4369 pre_shift
, tquotient
, 1);
4371 else if (size
<= HOST_BITS_PER_WIDE_INT
)
4373 if (d
>= (HOST_WIDE_INT_1U
<< (size
- 1)))
4375 /* Most significant bit of divisor is set; emit an scc
4377 quotient
= emit_store_flag_force (tquotient
, GEU
, op0
, op1
,
4382 /* Find a suitable multiplier and right shift count
4383 instead of multiplying with D. */
4385 mh
= choose_multiplier (d
, size
, size
,
4386 &ml
, &post_shift
, &dummy
);
4388 /* If the suggested multiplier is more than SIZE bits,
4389 we can do better for even divisors, using an
4390 initial right shift. */
4391 if (mh
!= 0 && (d
& 1) == 0)
4393 pre_shift
= ctz_or_zero (d
);
4394 mh
= choose_multiplier (d
>> pre_shift
, size
,
4396 &ml
, &post_shift
, &dummy
);
4406 if (post_shift
- 1 >= BITS_PER_WORD
)
4410 = (shift_cost (speed
, int_mode
, post_shift
- 1)
4411 + shift_cost (speed
, int_mode
, 1)
4412 + 2 * add_cost (speed
, int_mode
));
4413 t1
= expmed_mult_highpart
4414 (int_mode
, op0
, gen_int_mode (ml
, int_mode
),
4415 NULL_RTX
, 1, max_cost
- extra_cost
);
4418 t2
= force_operand (gen_rtx_MINUS (int_mode
,
4421 t3
= expand_shift (RSHIFT_EXPR
, int_mode
,
4422 t2
, 1, NULL_RTX
, 1);
4423 t4
= force_operand (gen_rtx_PLUS (int_mode
,
4426 quotient
= expand_shift
4427 (RSHIFT_EXPR
, int_mode
, t4
,
4428 post_shift
- 1, tquotient
, 1);
4434 if (pre_shift
>= BITS_PER_WORD
4435 || post_shift
>= BITS_PER_WORD
)
4439 (RSHIFT_EXPR
, int_mode
, op0
,
4440 pre_shift
, NULL_RTX
, 1);
4442 = (shift_cost (speed
, int_mode
, pre_shift
)
4443 + shift_cost (speed
, int_mode
, post_shift
));
4444 t2
= expmed_mult_highpart
4446 gen_int_mode (ml
, int_mode
),
4447 NULL_RTX
, 1, max_cost
- extra_cost
);
4450 quotient
= expand_shift
4451 (RSHIFT_EXPR
, int_mode
, t2
,
4452 post_shift
, tquotient
, 1);
4456 else /* Too wide mode to use tricky code */
4459 insn
= get_last_insn ();
4461 set_dst_reg_note (insn
, REG_EQUAL
,
4462 gen_rtx_UDIV (int_mode
, op0
, op1
),
4465 else /* TRUNC_DIV, signed */
4467 unsigned HOST_WIDE_INT ml
;
4468 int lgup
, post_shift
;
4470 HOST_WIDE_INT d
= INTVAL (op1
);
4471 unsigned HOST_WIDE_INT abs_d
;
4473 /* Since d might be INT_MIN, we have to cast to
4474 unsigned HOST_WIDE_INT before negating to avoid
4475 undefined signed overflow. */
4477 ? (unsigned HOST_WIDE_INT
) d
4478 : - (unsigned HOST_WIDE_INT
) d
);
4480 /* n rem d = n rem -d */
4481 if (rem_flag
&& d
< 0)
4484 op1
= gen_int_mode (abs_d
, int_mode
);
4490 quotient
= expand_unop (int_mode
, neg_optab
, op0
,
4492 else if (size
<= HOST_BITS_PER_WIDE_INT
4493 && abs_d
== HOST_WIDE_INT_1U
<< (size
- 1))
4495 /* This case is not handled correctly below. */
4496 quotient
= emit_store_flag (tquotient
, EQ
, op0
, op1
,
4501 else if (EXACT_POWER_OF_2_OR_ZERO_P (d
)
4502 && (size
<= HOST_BITS_PER_WIDE_INT
|| d
>= 0)
4504 ? smod_pow2_cheap (speed
, int_mode
)
4505 : sdiv_pow2_cheap (speed
, int_mode
))
4506 /* We assume that cheap metric is true if the
4507 optab has an expander for this mode. */
4508 && ((optab_handler ((rem_flag
? smod_optab
4511 != CODE_FOR_nothing
)
4512 || (optab_handler (sdivmod_optab
, int_mode
)
4513 != CODE_FOR_nothing
)))
4515 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d
)
4516 && (size
<= HOST_BITS_PER_WIDE_INT
4517 || abs_d
!= (unsigned HOST_WIDE_INT
) d
))
4521 remainder
= expand_smod_pow2 (int_mode
, op0
, d
);
4523 return gen_lowpart (mode
, remainder
);
4526 if (sdiv_pow2_cheap (speed
, int_mode
)
4527 && ((optab_handler (sdiv_optab
, int_mode
)
4528 != CODE_FOR_nothing
)
4529 || (optab_handler (sdivmod_optab
, int_mode
)
4530 != CODE_FOR_nothing
)))
4531 quotient
= expand_divmod (0, TRUNC_DIV_EXPR
,
4533 gen_int_mode (abs_d
,
4537 quotient
= expand_sdiv_pow2 (int_mode
, op0
, abs_d
);
4539 /* We have computed OP0 / abs(OP1). If OP1 is negative,
4540 negate the quotient. */
4543 insn
= get_last_insn ();
4545 && abs_d
< (HOST_WIDE_INT_1U
4546 << (HOST_BITS_PER_WIDE_INT
- 1)))
4547 set_dst_reg_note (insn
, REG_EQUAL
,
4548 gen_rtx_DIV (int_mode
, op0
,
4554 quotient
= expand_unop (int_mode
, neg_optab
,
4555 quotient
, quotient
, 0);
4558 else if (size
<= HOST_BITS_PER_WIDE_INT
)
4560 choose_multiplier (abs_d
, size
, size
- 1,
4561 &ml
, &post_shift
, &lgup
);
4562 if (ml
< HOST_WIDE_INT_1U
<< (size
- 1))
4566 if (post_shift
>= BITS_PER_WORD
4567 || size
- 1 >= BITS_PER_WORD
)
4570 extra_cost
= (shift_cost (speed
, int_mode
, post_shift
)
4571 + shift_cost (speed
, int_mode
, size
- 1)
4572 + add_cost (speed
, int_mode
));
4573 t1
= expmed_mult_highpart
4574 (int_mode
, op0
, gen_int_mode (ml
, int_mode
),
4575 NULL_RTX
, 0, max_cost
- extra_cost
);
4579 (RSHIFT_EXPR
, int_mode
, t1
,
4580 post_shift
, NULL_RTX
, 0);
4582 (RSHIFT_EXPR
, int_mode
, op0
,
4583 size
- 1, NULL_RTX
, 0);
4586 = force_operand (gen_rtx_MINUS (int_mode
, t3
, t2
),
4590 = force_operand (gen_rtx_MINUS (int_mode
, t2
, t3
),
4597 if (post_shift
>= BITS_PER_WORD
4598 || size
- 1 >= BITS_PER_WORD
)
4601 ml
|= HOST_WIDE_INT_M1U
<< (size
- 1);
4602 mlr
= gen_int_mode (ml
, int_mode
);
4603 extra_cost
= (shift_cost (speed
, int_mode
, post_shift
)
4604 + shift_cost (speed
, int_mode
, size
- 1)
4605 + 2 * add_cost (speed
, int_mode
));
4606 t1
= expmed_mult_highpart (int_mode
, op0
, mlr
,
4608 max_cost
- extra_cost
);
4611 t2
= force_operand (gen_rtx_PLUS (int_mode
, t1
, op0
),
4614 (RSHIFT_EXPR
, int_mode
, t2
,
4615 post_shift
, NULL_RTX
, 0);
4617 (RSHIFT_EXPR
, int_mode
, op0
,
4618 size
- 1, NULL_RTX
, 0);
4621 = force_operand (gen_rtx_MINUS (int_mode
, t4
, t3
),
4625 = force_operand (gen_rtx_MINUS (int_mode
, t3
, t4
),
4629 else /* Too wide mode to use tricky code */
4632 insn
= get_last_insn ();
4634 set_dst_reg_note (insn
, REG_EQUAL
,
4635 gen_rtx_DIV (int_mode
, op0
, op1
),
4641 delete_insns_since (last
);
4644 case FLOOR_DIV_EXPR
:
4645 case FLOOR_MOD_EXPR
:
4646 /* We will come here only for signed operations. */
4647 if (op1_is_constant
&& HWI_COMPUTABLE_MODE_P (compute_mode
))
4649 scalar_int_mode int_mode
= as_a
<scalar_int_mode
> (compute_mode
);
4650 int size
= GET_MODE_BITSIZE (int_mode
);
4651 unsigned HOST_WIDE_INT mh
, ml
;
4652 int pre_shift
, lgup
, post_shift
;
4653 HOST_WIDE_INT d
= INTVAL (op1
);
4657 /* We could just as easily deal with negative constants here,
4658 but it does not seem worth the trouble for GCC 2.6. */
4659 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
4661 pre_shift
= floor_log2 (d
);
4664 unsigned HOST_WIDE_INT mask
4665 = (HOST_WIDE_INT_1U
<< pre_shift
) - 1;
4666 remainder
= expand_binop
4667 (int_mode
, and_optab
, op0
,
4668 gen_int_mode (mask
, int_mode
),
4669 remainder
, 0, OPTAB_LIB_WIDEN
);
4671 return gen_lowpart (mode
, remainder
);
4673 quotient
= expand_shift
4674 (RSHIFT_EXPR
, int_mode
, op0
,
4675 pre_shift
, tquotient
, 0);
4681 mh
= choose_multiplier (d
, size
, size
- 1,
4682 &ml
, &post_shift
, &lgup
);
4685 if (post_shift
< BITS_PER_WORD
4686 && size
- 1 < BITS_PER_WORD
)
4689 (RSHIFT_EXPR
, int_mode
, op0
,
4690 size
- 1, NULL_RTX
, 0);
4691 t2
= expand_binop (int_mode
, xor_optab
, op0
, t1
,
4692 NULL_RTX
, 0, OPTAB_WIDEN
);
4693 extra_cost
= (shift_cost (speed
, int_mode
, post_shift
)
4694 + shift_cost (speed
, int_mode
, size
- 1)
4695 + 2 * add_cost (speed
, int_mode
));
4696 t3
= expmed_mult_highpart
4697 (int_mode
, t2
, gen_int_mode (ml
, int_mode
),
4698 NULL_RTX
, 1, max_cost
- extra_cost
);
4702 (RSHIFT_EXPR
, int_mode
, t3
,
4703 post_shift
, NULL_RTX
, 1);
4704 quotient
= expand_binop (int_mode
, xor_optab
,
4705 t4
, t1
, tquotient
, 0,
4713 rtx nsign
, t1
, t2
, t3
, t4
;
4714 t1
= force_operand (gen_rtx_PLUS (int_mode
,
4715 op0
, constm1_rtx
), NULL_RTX
);
4716 t2
= expand_binop (int_mode
, ior_optab
, op0
, t1
, NULL_RTX
,
4718 nsign
= expand_shift (RSHIFT_EXPR
, int_mode
, t2
,
4719 size
- 1, NULL_RTX
, 0);
4720 t3
= force_operand (gen_rtx_MINUS (int_mode
, t1
, nsign
),
4722 t4
= expand_divmod (0, TRUNC_DIV_EXPR
, int_mode
, t3
, op1
,
4727 t5
= expand_unop (int_mode
, one_cmpl_optab
, nsign
,
4729 quotient
= force_operand (gen_rtx_PLUS (int_mode
, t4
, t5
),
4737 delete_insns_since (last
);
4739 /* Try using an instruction that produces both the quotient and
4740 remainder, using truncation. We can easily compensate the quotient
4741 or remainder to get floor rounding, once we have the remainder.
4742 Notice that we compute also the final remainder value here,
4743 and return the result right away. */
4744 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4745 target
= gen_reg_rtx (compute_mode
);
4750 = REG_P (target
) ? target
: gen_reg_rtx (compute_mode
);
4751 quotient
= gen_reg_rtx (compute_mode
);
4756 = REG_P (target
) ? target
: gen_reg_rtx (compute_mode
);
4757 remainder
= gen_reg_rtx (compute_mode
);
4760 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
,
4761 quotient
, remainder
, 0))
4763 /* This could be computed with a branch-less sequence.
4764 Save that for later. */
4766 rtx_code_label
*label
= gen_label_rtx ();
4767 do_cmp_and_jump (remainder
, const0_rtx
, EQ
, compute_mode
, label
);
4768 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4769 NULL_RTX
, 0, OPTAB_WIDEN
);
4770 do_cmp_and_jump (tem
, const0_rtx
, GE
, compute_mode
, label
);
4771 expand_dec (quotient
, const1_rtx
);
4772 expand_inc (remainder
, op1
);
4774 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4777 /* No luck with division elimination or divmod. Have to do it
4778 by conditionally adjusting op0 *and* the result. */
4780 rtx_code_label
*label1
, *label2
, *label3
, *label4
, *label5
;
4784 quotient
= gen_reg_rtx (compute_mode
);
4785 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4786 label1
= gen_label_rtx ();
4787 label2
= gen_label_rtx ();
4788 label3
= gen_label_rtx ();
4789 label4
= gen_label_rtx ();
4790 label5
= gen_label_rtx ();
4791 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
4792 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
, compute_mode
, label1
);
4793 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4794 quotient
, 0, OPTAB_LIB_WIDEN
);
4795 if (tem
!= quotient
)
4796 emit_move_insn (quotient
, tem
);
4797 emit_jump_insn (targetm
.gen_jump (label5
));
4799 emit_label (label1
);
4800 expand_inc (adjusted_op0
, const1_rtx
);
4801 emit_jump_insn (targetm
.gen_jump (label4
));
4803 emit_label (label2
);
4804 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
, compute_mode
, label3
);
4805 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4806 quotient
, 0, OPTAB_LIB_WIDEN
);
4807 if (tem
!= quotient
)
4808 emit_move_insn (quotient
, tem
);
4809 emit_jump_insn (targetm
.gen_jump (label5
));
4811 emit_label (label3
);
4812 expand_dec (adjusted_op0
, const1_rtx
);
4813 emit_label (label4
);
4814 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
4815 quotient
, 0, OPTAB_LIB_WIDEN
);
4816 if (tem
!= quotient
)
4817 emit_move_insn (quotient
, tem
);
4818 expand_dec (quotient
, const1_rtx
);
4819 emit_label (label5
);
4828 && EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
4829 && (HWI_COMPUTABLE_MODE_P (compute_mode
)
4830 || INTVAL (op1
) >= 0))
4832 scalar_int_mode int_mode
4833 = as_a
<scalar_int_mode
> (compute_mode
);
4835 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
4836 t1
= expand_shift (RSHIFT_EXPR
, int_mode
, op0
,
4837 floor_log2 (d
), tquotient
, 1);
4838 t2
= expand_binop (int_mode
, and_optab
, op0
,
4839 gen_int_mode (d
- 1, int_mode
),
4840 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4841 t3
= gen_reg_rtx (int_mode
);
4842 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
, int_mode
, 1, 1);
4845 rtx_code_label
*lab
;
4846 lab
= gen_label_rtx ();
4847 do_cmp_and_jump (t2
, const0_rtx
, EQ
, int_mode
, lab
);
4848 expand_inc (t1
, const1_rtx
);
4853 quotient
= force_operand (gen_rtx_PLUS (int_mode
, t1
, t3
),
4858 /* Try using an instruction that produces both the quotient and
4859 remainder, using truncation. We can easily compensate the
4860 quotient or remainder to get ceiling rounding, once we have the
4861 remainder. Notice that we compute also the final remainder
4862 value here, and return the result right away. */
4863 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4864 target
= gen_reg_rtx (compute_mode
);
4868 remainder
= (REG_P (target
)
4869 ? target
: gen_reg_rtx (compute_mode
));
4870 quotient
= gen_reg_rtx (compute_mode
);
4874 quotient
= (REG_P (target
)
4875 ? target
: gen_reg_rtx (compute_mode
));
4876 remainder
= gen_reg_rtx (compute_mode
);
4879 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
,
4882 /* This could be computed with a branch-less sequence.
4883 Save that for later. */
4884 rtx_code_label
*label
= gen_label_rtx ();
4885 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
4886 compute_mode
, label
);
4887 expand_inc (quotient
, const1_rtx
);
4888 expand_dec (remainder
, op1
);
4890 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4893 /* No luck with division elimination or divmod. Have to do it
4894 by conditionally adjusting op0 *and* the result. */
4896 rtx_code_label
*label1
, *label2
;
4897 rtx adjusted_op0
, tem
;
4899 quotient
= gen_reg_rtx (compute_mode
);
4900 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
4901 label1
= gen_label_rtx ();
4902 label2
= gen_label_rtx ();
4903 do_cmp_and_jump (adjusted_op0
, const0_rtx
, NE
,
4904 compute_mode
, label1
);
4905 emit_move_insn (quotient
, const0_rtx
);
4906 emit_jump_insn (targetm
.gen_jump (label2
));
4908 emit_label (label1
);
4909 expand_dec (adjusted_op0
, const1_rtx
);
4910 tem
= expand_binop (compute_mode
, udiv_optab
, adjusted_op0
, op1
,
4911 quotient
, 1, OPTAB_LIB_WIDEN
);
4912 if (tem
!= quotient
)
4913 emit_move_insn (quotient
, tem
);
4914 expand_inc (quotient
, const1_rtx
);
4915 emit_label (label2
);
4920 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
4921 && INTVAL (op1
) >= 0)
4923 /* This is extremely similar to the code for the unsigned case
4924 above. For 2.7 we should merge these variants, but for
4925 2.6.1 I don't want to touch the code for unsigned since that
4926 get used in C. The signed case will only be used by other
4930 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
4931 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
4932 floor_log2 (d
), tquotient
, 0);
4933 t2
= expand_binop (compute_mode
, and_optab
, op0
,
4934 gen_int_mode (d
- 1, compute_mode
),
4935 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
4936 t3
= gen_reg_rtx (compute_mode
);
4937 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
4938 compute_mode
, 1, 1);
4941 rtx_code_label
*lab
;
4942 lab
= gen_label_rtx ();
4943 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
4944 expand_inc (t1
, const1_rtx
);
4949 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
4955 /* Try using an instruction that produces both the quotient and
4956 remainder, using truncation. We can easily compensate the
4957 quotient or remainder to get ceiling rounding, once we have the
4958 remainder. Notice that we compute also the final remainder
4959 value here, and return the result right away. */
4960 if (target
== 0 || GET_MODE (target
) != compute_mode
)
4961 target
= gen_reg_rtx (compute_mode
);
4964 remainder
= (REG_P (target
)
4965 ? target
: gen_reg_rtx (compute_mode
));
4966 quotient
= gen_reg_rtx (compute_mode
);
4970 quotient
= (REG_P (target
)
4971 ? target
: gen_reg_rtx (compute_mode
));
4972 remainder
= gen_reg_rtx (compute_mode
);
4975 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
,
4978 /* This could be computed with a branch-less sequence.
4979 Save that for later. */
4981 rtx_code_label
*label
= gen_label_rtx ();
4982 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
4983 compute_mode
, label
);
4984 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
4985 NULL_RTX
, 0, OPTAB_WIDEN
);
4986 do_cmp_and_jump (tem
, const0_rtx
, LT
, compute_mode
, label
);
4987 expand_inc (quotient
, const1_rtx
);
4988 expand_dec (remainder
, op1
);
4990 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4993 /* No luck with division elimination or divmod. Have to do it
4994 by conditionally adjusting op0 *and* the result. */
4996 rtx_code_label
*label1
, *label2
, *label3
, *label4
, *label5
;
5000 quotient
= gen_reg_rtx (compute_mode
);
5001 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
5002 label1
= gen_label_rtx ();
5003 label2
= gen_label_rtx ();
5004 label3
= gen_label_rtx ();
5005 label4
= gen_label_rtx ();
5006 label5
= gen_label_rtx ();
5007 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
5008 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
,
5009 compute_mode
, label1
);
5010 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
5011 quotient
, 0, OPTAB_LIB_WIDEN
);
5012 if (tem
!= quotient
)
5013 emit_move_insn (quotient
, tem
);
5014 emit_jump_insn (targetm
.gen_jump (label5
));
5016 emit_label (label1
);
5017 expand_dec (adjusted_op0
, const1_rtx
);
5018 emit_jump_insn (targetm
.gen_jump (label4
));
5020 emit_label (label2
);
5021 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
,
5022 compute_mode
, label3
);
5023 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
5024 quotient
, 0, OPTAB_LIB_WIDEN
);
5025 if (tem
!= quotient
)
5026 emit_move_insn (quotient
, tem
);
5027 emit_jump_insn (targetm
.gen_jump (label5
));
5029 emit_label (label3
);
5030 expand_inc (adjusted_op0
, const1_rtx
);
5031 emit_label (label4
);
5032 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
5033 quotient
, 0, OPTAB_LIB_WIDEN
);
5034 if (tem
!= quotient
)
5035 emit_move_insn (quotient
, tem
);
5036 expand_inc (quotient
, const1_rtx
);
5037 emit_label (label5
);
5042 case EXACT_DIV_EXPR
:
5043 if (op1_is_constant
&& HWI_COMPUTABLE_MODE_P (compute_mode
))
5045 scalar_int_mode int_mode
= as_a
<scalar_int_mode
> (compute_mode
);
5046 int size
= GET_MODE_BITSIZE (int_mode
);
5047 HOST_WIDE_INT d
= INTVAL (op1
);
5048 unsigned HOST_WIDE_INT ml
;
5052 pre_shift
= ctz_or_zero (d
);
5053 ml
= invert_mod2n (d
>> pre_shift
, size
);
5054 t1
= expand_shift (RSHIFT_EXPR
, int_mode
, op0
,
5055 pre_shift
, NULL_RTX
, unsignedp
);
5056 quotient
= expand_mult (int_mode
, t1
, gen_int_mode (ml
, int_mode
),
5059 insn
= get_last_insn ();
5060 set_dst_reg_note (insn
, REG_EQUAL
,
5061 gen_rtx_fmt_ee (unsignedp
? UDIV
: DIV
,
5062 int_mode
, op0
, op1
),
5067 case ROUND_DIV_EXPR
:
5068 case ROUND_MOD_EXPR
:
5071 scalar_int_mode int_mode
= as_a
<scalar_int_mode
> (compute_mode
);
5073 rtx_code_label
*label
;
5074 label
= gen_label_rtx ();
5075 quotient
= gen_reg_rtx (int_mode
);
5076 remainder
= gen_reg_rtx (int_mode
);
5077 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
, remainder
, 1) == 0)
5080 quotient
= expand_binop (int_mode
, udiv_optab
, op0
, op1
,
5081 quotient
, 1, OPTAB_LIB_WIDEN
);
5082 tem
= expand_mult (int_mode
, quotient
, op1
, NULL_RTX
, 1);
5083 remainder
= expand_binop (int_mode
, sub_optab
, op0
, tem
,
5084 remainder
, 1, OPTAB_LIB_WIDEN
);
5086 tem
= plus_constant (int_mode
, op1
, -1);
5087 tem
= expand_shift (RSHIFT_EXPR
, int_mode
, tem
, 1, NULL_RTX
, 1);
5088 do_cmp_and_jump (remainder
, tem
, LEU
, int_mode
, label
);
5089 expand_inc (quotient
, const1_rtx
);
5090 expand_dec (remainder
, op1
);
5095 scalar_int_mode int_mode
= as_a
<scalar_int_mode
> (compute_mode
);
5096 int size
= GET_MODE_BITSIZE (int_mode
);
5097 rtx abs_rem
, abs_op1
, tem
, mask
;
5098 rtx_code_label
*label
;
5099 label
= gen_label_rtx ();
5100 quotient
= gen_reg_rtx (int_mode
);
5101 remainder
= gen_reg_rtx (int_mode
);
5102 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
, remainder
, 0) == 0)
5105 quotient
= expand_binop (int_mode
, sdiv_optab
, op0
, op1
,
5106 quotient
, 0, OPTAB_LIB_WIDEN
);
5107 tem
= expand_mult (int_mode
, quotient
, op1
, NULL_RTX
, 0);
5108 remainder
= expand_binop (int_mode
, sub_optab
, op0
, tem
,
5109 remainder
, 0, OPTAB_LIB_WIDEN
);
5111 abs_rem
= expand_abs (int_mode
, remainder
, NULL_RTX
, 1, 0);
5112 abs_op1
= expand_abs (int_mode
, op1
, NULL_RTX
, 1, 0);
5113 tem
= expand_shift (LSHIFT_EXPR
, int_mode
, abs_rem
,
5115 do_cmp_and_jump (tem
, abs_op1
, LTU
, int_mode
, label
);
5116 tem
= expand_binop (int_mode
, xor_optab
, op0
, op1
,
5117 NULL_RTX
, 0, OPTAB_WIDEN
);
5118 mask
= expand_shift (RSHIFT_EXPR
, int_mode
, tem
,
5119 size
- 1, NULL_RTX
, 0);
5120 tem
= expand_binop (int_mode
, xor_optab
, mask
, const1_rtx
,
5121 NULL_RTX
, 0, OPTAB_WIDEN
);
5122 tem
= expand_binop (int_mode
, sub_optab
, tem
, mask
,
5123 NULL_RTX
, 0, OPTAB_WIDEN
);
5124 expand_inc (quotient
, tem
);
5125 tem
= expand_binop (int_mode
, xor_optab
, mask
, op1
,
5126 NULL_RTX
, 0, OPTAB_WIDEN
);
5127 tem
= expand_binop (int_mode
, sub_optab
, tem
, mask
,
5128 NULL_RTX
, 0, OPTAB_WIDEN
);
5129 expand_dec (remainder
, tem
);
5132 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
5140 if (target
&& GET_MODE (target
) != compute_mode
)
5145 /* Try to produce the remainder without producing the quotient.
5146 If we seem to have a divmod pattern that does not require widening,
5147 don't try widening here. We should really have a WIDEN argument
5148 to expand_twoval_binop, since what we'd really like to do here is
5149 1) try a mod insn in compute_mode
5150 2) try a divmod insn in compute_mode
5151 3) try a div insn in compute_mode and multiply-subtract to get
5153 4) try the same things with widening allowed. */
5155 = sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
5158 ((optab_handler (optab2
, compute_mode
)
5159 != CODE_FOR_nothing
)
5160 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
5163 /* No luck there. Can we do remainder and divide at once
5164 without a library call? */
5165 remainder
= gen_reg_rtx (compute_mode
);
5166 if (! expand_twoval_binop ((unsignedp
5170 NULL_RTX
, remainder
, unsignedp
))
5175 return gen_lowpart (mode
, remainder
);
5178 /* Produce the quotient. Try a quotient insn, but not a library call.
5179 If we have a divmod in this mode, use it in preference to widening
5180 the div (for this test we assume it will not fail). Note that optab2
5181 is set to the one of the two optabs that the call below will use. */
5183 = sign_expand_binop (compute_mode
, udiv_optab
, sdiv_optab
,
5184 op0
, op1
, rem_flag
? NULL_RTX
: target
,
5186 ((optab_handler (optab2
, compute_mode
)
5187 != CODE_FOR_nothing
)
5188 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
5192 /* No luck there. Try a quotient-and-remainder insn,
5193 keeping the quotient alone. */
5194 quotient
= gen_reg_rtx (compute_mode
);
5195 if (! expand_twoval_binop (unsignedp
? udivmod_optab
: sdivmod_optab
,
5197 quotient
, NULL_RTX
, unsignedp
))
5201 /* Still no luck. If we are not computing the remainder,
5202 use a library call for the quotient. */
5203 quotient
= sign_expand_binop (compute_mode
,
5204 udiv_optab
, sdiv_optab
,
5206 unsignedp
, OPTAB_LIB_WIDEN
);
5213 if (target
&& GET_MODE (target
) != compute_mode
)
5218 /* No divide instruction either. Use library for remainder. */
5219 remainder
= sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
5221 unsignedp
, OPTAB_LIB_WIDEN
);
5222 /* No remainder function. Try a quotient-and-remainder
5223 function, keeping the remainder. */
5226 remainder
= gen_reg_rtx (compute_mode
);
5227 if (!expand_twoval_binop_libfunc
5228 (unsignedp
? udivmod_optab
: sdivmod_optab
,
5230 NULL_RTX
, remainder
,
5231 unsignedp
? UMOD
: MOD
))
5232 remainder
= NULL_RTX
;
5237 /* We divided. Now finish doing X - Y * (X / Y). */
5238 remainder
= expand_mult (compute_mode
, quotient
, op1
,
5239 NULL_RTX
, unsignedp
);
5240 remainder
= expand_binop (compute_mode
, sub_optab
, op0
,
5241 remainder
, target
, unsignedp
,
5246 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
5249 /* Return a tree node with data type TYPE, describing the value of X.
5250 Usually this is an VAR_DECL, if there is no obvious better choice.
5251 X may be an expression, however we only support those expressions
5252 generated by loop.c. */
5255 make_tree (tree type
, rtx x
)
5259 switch (GET_CODE (x
))
5262 case CONST_WIDE_INT
:
5263 t
= wide_int_to_tree (type
, rtx_mode_t (x
, TYPE_MODE (type
)));
5267 STATIC_ASSERT (HOST_BITS_PER_WIDE_INT
* 2 <= MAX_BITSIZE_MODE_ANY_INT
);
5268 if (TARGET_SUPPORTS_WIDE_INT
== 0 && GET_MODE (x
) == VOIDmode
)
5269 t
= wide_int_to_tree (type
,
5270 wide_int::from_array (&CONST_DOUBLE_LOW (x
), 2,
5271 HOST_BITS_PER_WIDE_INT
* 2));
5273 t
= build_real (type
, *CONST_DOUBLE_REAL_VALUE (x
));
5279 unsigned int npatterns
= CONST_VECTOR_NPATTERNS (x
);
5280 unsigned int nelts_per_pattern
= CONST_VECTOR_NELTS_PER_PATTERN (x
);
5281 tree itype
= TREE_TYPE (type
);
5283 /* Build a tree with vector elements. */
5284 tree_vector_builder
elts (type
, npatterns
, nelts_per_pattern
);
5285 unsigned int count
= elts
.encoded_nelts ();
5286 for (unsigned int i
= 0; i
< count
; ++i
)
5288 rtx elt
= CONST_VECTOR_ELT (x
, i
);
5289 elts
.quick_push (make_tree (itype
, elt
));
5292 return elts
.build ();
5296 return fold_build2 (PLUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
5297 make_tree (type
, XEXP (x
, 1)));
5300 return fold_build2 (MINUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
5301 make_tree (type
, XEXP (x
, 1)));
5304 return fold_build1 (NEGATE_EXPR
, type
, make_tree (type
, XEXP (x
, 0)));
5307 return fold_build2 (MULT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
5308 make_tree (type
, XEXP (x
, 1)));
5311 return fold_build2 (LSHIFT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
5312 make_tree (type
, XEXP (x
, 1)));
5315 t
= unsigned_type_for (type
);
5316 return fold_convert (type
, build2 (RSHIFT_EXPR
, t
,
5317 make_tree (t
, XEXP (x
, 0)),
5318 make_tree (type
, XEXP (x
, 1))));
5321 t
= signed_type_for (type
);
5322 return fold_convert (type
, build2 (RSHIFT_EXPR
, t
,
5323 make_tree (t
, XEXP (x
, 0)),
5324 make_tree (type
, XEXP (x
, 1))));
5327 if (TREE_CODE (type
) != REAL_TYPE
)
5328 t
= signed_type_for (type
);
5332 return fold_convert (type
, build2 (TRUNC_DIV_EXPR
, t
,
5333 make_tree (t
, XEXP (x
, 0)),
5334 make_tree (t
, XEXP (x
, 1))));
5336 t
= unsigned_type_for (type
);
5337 return fold_convert (type
, build2 (TRUNC_DIV_EXPR
, t
,
5338 make_tree (t
, XEXP (x
, 0)),
5339 make_tree (t
, XEXP (x
, 1))));
5343 t
= lang_hooks
.types
.type_for_mode (GET_MODE (XEXP (x
, 0)),
5344 GET_CODE (x
) == ZERO_EXTEND
);
5345 return fold_convert (type
, make_tree (t
, XEXP (x
, 0)));
5349 rtx op
= XEXP (x
, 0);
5350 if (GET_CODE (op
) == VEC_DUPLICATE
)
5352 tree elt_tree
= make_tree (TREE_TYPE (type
), XEXP (op
, 0));
5353 return build_vector_from_val (type
, elt_tree
);
5355 if (GET_CODE (op
) == VEC_SERIES
)
5357 tree itype
= TREE_TYPE (type
);
5358 tree base_tree
= make_tree (itype
, XEXP (op
, 0));
5359 tree step_tree
= make_tree (itype
, XEXP (op
, 1));
5360 return build_vec_series (type
, base_tree
, step_tree
);
5362 return make_tree (type
, op
);
5366 t
= SYMBOL_REF_DECL (x
);
5368 return fold_convert (type
, build_fold_addr_expr (t
));
5372 if (CONST_POLY_INT_P (x
))
5373 return wide_int_to_tree (t
, const_poly_int_value (x
));
5375 t
= build_decl (RTL_LOCATION (x
), VAR_DECL
, NULL_TREE
, type
);
5377 /* If TYPE is a POINTER_TYPE, we might need to convert X from
5378 address mode to pointer mode. */
5379 if (POINTER_TYPE_P (type
))
5380 x
= convert_memory_address_addr_space
5381 (SCALAR_INT_TYPE_MODE (type
), x
, TYPE_ADDR_SPACE (TREE_TYPE (type
)));
5383 /* Note that we do *not* use SET_DECL_RTL here, because we do not
5384 want set_decl_rtl to go adjusting REG_ATTRS for this temporary. */
5385 t
->decl_with_rtl
.rtl
= x
;
5391 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
5392 and returning TARGET.
5394 If TARGET is 0, a pseudo-register or constant is returned. */
5397 expand_and (machine_mode mode
, rtx op0
, rtx op1
, rtx target
)
5401 if (GET_MODE (op0
) == VOIDmode
&& GET_MODE (op1
) == VOIDmode
)
5402 tem
= simplify_binary_operation (AND
, mode
, op0
, op1
);
5404 tem
= expand_binop (mode
, and_optab
, op0
, op1
, target
, 0, OPTAB_LIB_WIDEN
);
5408 else if (tem
!= target
)
5409 emit_move_insn (target
, tem
);
5413 /* Helper function for emit_store_flag. */
5415 emit_cstore (rtx target
, enum insn_code icode
, enum rtx_code code
,
5416 machine_mode mode
, machine_mode compare_mode
,
5417 int unsignedp
, rtx x
, rtx y
, int normalizep
,
5418 machine_mode target_mode
)
5420 struct expand_operand ops
[4];
5421 rtx op0
, comparison
, subtarget
;
5423 scalar_int_mode result_mode
= targetm
.cstore_mode (icode
);
5424 scalar_int_mode int_target_mode
;
5426 last
= get_last_insn ();
5427 x
= prepare_operand (icode
, x
, 2, mode
, compare_mode
, unsignedp
);
5428 y
= prepare_operand (icode
, y
, 3, mode
, compare_mode
, unsignedp
);
5431 delete_insns_since (last
);
5435 if (target_mode
== VOIDmode
)
5436 int_target_mode
= result_mode
;
5438 int_target_mode
= as_a
<scalar_int_mode
> (target_mode
);
5440 target
= gen_reg_rtx (int_target_mode
);
5442 comparison
= gen_rtx_fmt_ee (code
, result_mode
, x
, y
);
5444 create_output_operand (&ops
[0], optimize
? NULL_RTX
: target
, result_mode
);
5445 create_fixed_operand (&ops
[1], comparison
);
5446 create_fixed_operand (&ops
[2], x
);
5447 create_fixed_operand (&ops
[3], y
);
5448 if (!maybe_expand_insn (icode
, 4, ops
))
5450 delete_insns_since (last
);
5453 subtarget
= ops
[0].value
;
5455 /* If we are converting to a wider mode, first convert to
5456 INT_TARGET_MODE, then normalize. This produces better combining
5457 opportunities on machines that have a SIGN_EXTRACT when we are
5458 testing a single bit. This mostly benefits the 68k.
5460 If STORE_FLAG_VALUE does not have the sign bit set when
5461 interpreted in MODE, we can do this conversion as unsigned, which
5462 is usually more efficient. */
5463 if (GET_MODE_SIZE (int_target_mode
) > GET_MODE_SIZE (result_mode
))
5465 convert_move (target
, subtarget
,
5466 val_signbit_known_clear_p (result_mode
,
5469 result_mode
= int_target_mode
;
5474 /* If we want to keep subexpressions around, don't reuse our last
5479 /* Now normalize to the proper value in MODE. Sometimes we don't
5480 have to do anything. */
5481 if (normalizep
== 0 || normalizep
== STORE_FLAG_VALUE
)
5483 /* STORE_FLAG_VALUE might be the most negative number, so write
5484 the comparison this way to avoid a compiler-time warning. */
5485 else if (- normalizep
== STORE_FLAG_VALUE
)
5486 op0
= expand_unop (result_mode
, neg_optab
, op0
, subtarget
, 0);
5488 /* We don't want to use STORE_FLAG_VALUE < 0 below since this makes
5489 it hard to use a value of just the sign bit due to ANSI integer
5490 constant typing rules. */
5491 else if (val_signbit_known_set_p (result_mode
, STORE_FLAG_VALUE
))
5492 op0
= expand_shift (RSHIFT_EXPR
, result_mode
, op0
,
5493 GET_MODE_BITSIZE (result_mode
) - 1, subtarget
,
5497 gcc_assert (STORE_FLAG_VALUE
& 1);
5499 op0
= expand_and (result_mode
, op0
, const1_rtx
, subtarget
);
5500 if (normalizep
== -1)
5501 op0
= expand_unop (result_mode
, neg_optab
, op0
, op0
, 0);
5504 /* If we were converting to a smaller mode, do the conversion now. */
5505 if (int_target_mode
!= result_mode
)
5507 convert_move (target
, op0
, 0);
5515 /* A subroutine of emit_store_flag only including "tricks" that do not
5516 need a recursive call. These are kept separate to avoid infinite
5520 emit_store_flag_1 (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5521 machine_mode mode
, int unsignedp
, int normalizep
,
5522 machine_mode target_mode
)
5525 enum insn_code icode
;
5526 machine_mode compare_mode
;
5527 enum mode_class mclass
;
5528 enum rtx_code scode
;
5531 code
= unsigned_condition (code
);
5532 scode
= swap_condition (code
);
5534 /* If one operand is constant, make it the second one. Only do this
5535 if the other operand is not constant as well. */
5537 if (swap_commutative_operands_p (op0
, op1
))
5539 std::swap (op0
, op1
);
5540 code
= swap_condition (code
);
5543 if (mode
== VOIDmode
)
5544 mode
= GET_MODE (op0
);
5546 /* For some comparisons with 1 and -1, we can convert this to
5547 comparisons with zero. This will often produce more opportunities for
5548 store-flag insns. */
5553 if (op1
== const1_rtx
)
5554 op1
= const0_rtx
, code
= LE
;
5557 if (op1
== constm1_rtx
)
5558 op1
= const0_rtx
, code
= LT
;
5561 if (op1
== const1_rtx
)
5562 op1
= const0_rtx
, code
= GT
;
5565 if (op1
== constm1_rtx
)
5566 op1
= const0_rtx
, code
= GE
;
5569 if (op1
== const1_rtx
)
5570 op1
= const0_rtx
, code
= NE
;
5573 if (op1
== const1_rtx
)
5574 op1
= const0_rtx
, code
= EQ
;
5580 /* If we are comparing a double-word integer with zero or -1, we can
5581 convert the comparison into one involving a single word. */
5582 scalar_int_mode int_mode
;
5583 if (is_int_mode (mode
, &int_mode
)
5584 && GET_MODE_BITSIZE (int_mode
) == BITS_PER_WORD
* 2
5585 && (!MEM_P (op0
) || ! MEM_VOLATILE_P (op0
)))
5588 if ((code
== EQ
|| code
== NE
)
5589 && (op1
== const0_rtx
|| op1
== constm1_rtx
))
5593 /* Do a logical OR or AND of the two words and compare the
5595 op00
= simplify_gen_subreg (word_mode
, op0
, int_mode
, 0);
5596 op01
= simplify_gen_subreg (word_mode
, op0
, int_mode
, UNITS_PER_WORD
);
5597 tem
= expand_binop (word_mode
,
5598 op1
== const0_rtx
? ior_optab
: and_optab
,
5599 op00
, op01
, NULL_RTX
, unsignedp
,
5603 tem
= emit_store_flag (NULL_RTX
, code
, tem
, op1
, word_mode
,
5604 unsignedp
, normalizep
);
5606 else if ((code
== LT
|| code
== GE
) && op1
== const0_rtx
)
5610 /* If testing the sign bit, can just test on high word. */
5611 op0h
= simplify_gen_subreg (word_mode
, op0
, int_mode
,
5612 subreg_highpart_offset (word_mode
,
5614 tem
= emit_store_flag (NULL_RTX
, code
, op0h
, op1
, word_mode
,
5615 unsignedp
, normalizep
);
5622 if (target_mode
== VOIDmode
|| GET_MODE (tem
) == target_mode
)
5625 target
= gen_reg_rtx (target_mode
);
5627 convert_move (target
, tem
,
5628 !val_signbit_known_set_p (word_mode
,
5629 (normalizep
? normalizep
5630 : STORE_FLAG_VALUE
)));
5635 /* If this is A < 0 or A >= 0, we can do this by taking the ones
5636 complement of A (for GE) and shifting the sign bit to the low bit. */
5637 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
5638 && is_int_mode (mode
, &int_mode
)
5639 && (normalizep
|| STORE_FLAG_VALUE
== 1
5640 || val_signbit_p (int_mode
, STORE_FLAG_VALUE
)))
5642 scalar_int_mode int_target_mode
;
5646 int_target_mode
= int_mode
;
5649 /* If the result is to be wider than OP0, it is best to convert it
5650 first. If it is to be narrower, it is *incorrect* to convert it
5652 int_target_mode
= as_a
<scalar_int_mode
> (target_mode
);
5653 if (GET_MODE_SIZE (int_target_mode
) > GET_MODE_SIZE (int_mode
))
5655 op0
= convert_modes (int_target_mode
, int_mode
, op0
, 0);
5656 int_mode
= int_target_mode
;
5660 if (int_target_mode
!= int_mode
)
5664 op0
= expand_unop (int_mode
, one_cmpl_optab
, op0
,
5665 ((STORE_FLAG_VALUE
== 1 || normalizep
)
5666 ? 0 : subtarget
), 0);
5668 if (STORE_FLAG_VALUE
== 1 || normalizep
)
5669 /* If we are supposed to produce a 0/1 value, we want to do
5670 a logical shift from the sign bit to the low-order bit; for
5671 a -1/0 value, we do an arithmetic shift. */
5672 op0
= expand_shift (RSHIFT_EXPR
, int_mode
, op0
,
5673 GET_MODE_BITSIZE (int_mode
) - 1,
5674 subtarget
, normalizep
!= -1);
5676 if (int_mode
!= int_target_mode
)
5677 op0
= convert_modes (int_target_mode
, int_mode
, op0
, 0);
5682 mclass
= GET_MODE_CLASS (mode
);
5683 FOR_EACH_MODE_FROM (compare_mode
, mode
)
5685 machine_mode optab_mode
= mclass
== MODE_CC
? CCmode
: compare_mode
;
5686 icode
= optab_handler (cstore_optab
, optab_mode
);
5687 if (icode
!= CODE_FOR_nothing
)
5689 do_pending_stack_adjust ();
5690 rtx tem
= emit_cstore (target
, icode
, code
, mode
, compare_mode
,
5691 unsignedp
, op0
, op1
, normalizep
, target_mode
);
5695 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5697 tem
= emit_cstore (target
, icode
, scode
, mode
, compare_mode
,
5698 unsignedp
, op1
, op0
, normalizep
, target_mode
);
5709 /* Subroutine of emit_store_flag that handles cases in which the operands
5710 are scalar integers. SUBTARGET is the target to use for temporary
5711 operations and TRUEVAL is the value to store when the condition is
5712 true. All other arguments are as for emit_store_flag. */
5715 emit_store_flag_int (rtx target
, rtx subtarget
, enum rtx_code code
, rtx op0
,
5716 rtx op1
, scalar_int_mode mode
, int unsignedp
,
5717 int normalizep
, rtx trueval
)
5719 machine_mode target_mode
= target
? GET_MODE (target
) : VOIDmode
;
5720 rtx_insn
*last
= get_last_insn ();
5722 /* If this is an equality comparison of integers, we can try to exclusive-or
5723 (or subtract) the two operands and use a recursive call to try the
5724 comparison with zero. Don't do any of these cases if branches are
5727 if ((code
== EQ
|| code
== NE
) && op1
!= const0_rtx
)
5729 rtx tem
= expand_binop (mode
, xor_optab
, op0
, op1
, subtarget
, 1,
5733 tem
= expand_binop (mode
, sub_optab
, op0
, op1
, subtarget
, 1,
5736 tem
= emit_store_flag (target
, code
, tem
, const0_rtx
,
5737 mode
, unsignedp
, normalizep
);
5741 delete_insns_since (last
);
5744 /* For integer comparisons, try the reverse comparison. However, for
5745 small X and if we'd have anyway to extend, implementing "X != 0"
5746 as "-(int)X >> 31" is still cheaper than inverting "(int)X == 0". */
5747 rtx_code rcode
= reverse_condition (code
);
5748 if (can_compare_p (rcode
, mode
, ccp_store_flag
)
5749 && ! (optab_handler (cstore_optab
, mode
) == CODE_FOR_nothing
5751 && GET_MODE_SIZE (mode
) < UNITS_PER_WORD
5752 && op1
== const0_rtx
))
5754 int want_add
= ((STORE_FLAG_VALUE
== 1 && normalizep
== -1)
5755 || (STORE_FLAG_VALUE
== -1 && normalizep
== 1));
5757 /* Again, for the reverse comparison, use either an addition or a XOR. */
5759 && rtx_cost (GEN_INT (normalizep
), mode
, PLUS
, 1,
5760 optimize_insn_for_speed_p ()) == 0)
5762 rtx tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
5763 STORE_FLAG_VALUE
, target_mode
);
5765 tem
= expand_binop (target_mode
, add_optab
, tem
,
5766 gen_int_mode (normalizep
, target_mode
),
5767 target
, 0, OPTAB_WIDEN
);
5772 && rtx_cost (trueval
, mode
, XOR
, 1,
5773 optimize_insn_for_speed_p ()) == 0)
5775 rtx tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
5776 normalizep
, target_mode
);
5778 tem
= expand_binop (target_mode
, xor_optab
, tem
, trueval
, target
,
5779 INTVAL (trueval
) >= 0, OPTAB_WIDEN
);
5784 delete_insns_since (last
);
5787 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
5788 the constant zero. Reject all other comparisons at this point. Only
5789 do LE and GT if branches are expensive since they are expensive on
5790 2-operand machines. */
5792 if (op1
!= const0_rtx
5793 || (code
!= EQ
&& code
!= NE
5794 && (BRANCH_COST (optimize_insn_for_speed_p (),
5795 false) <= 1 || (code
!= LE
&& code
!= GT
))))
5798 /* Try to put the result of the comparison in the sign bit. Assume we can't
5799 do the necessary operation below. */
5803 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
5804 the sign bit set. */
5808 /* This is destructive, so SUBTARGET can't be OP0. */
5809 if (rtx_equal_p (subtarget
, op0
))
5812 tem
= expand_binop (mode
, sub_optab
, op0
, const1_rtx
, subtarget
, 0,
5815 tem
= expand_binop (mode
, ior_optab
, op0
, tem
, subtarget
, 0,
5819 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
5820 number of bits in the mode of OP0, minus one. */
5824 if (rtx_equal_p (subtarget
, op0
))
5827 tem
= maybe_expand_shift (RSHIFT_EXPR
, mode
, op0
,
5828 GET_MODE_BITSIZE (mode
) - 1,
5831 tem
= expand_binop (mode
, sub_optab
, tem
, op0
, subtarget
, 0,
5835 if (code
== EQ
|| code
== NE
)
5837 /* For EQ or NE, one way to do the comparison is to apply an operation
5838 that converts the operand into a positive number if it is nonzero
5839 or zero if it was originally zero. Then, for EQ, we subtract 1 and
5840 for NE we negate. This puts the result in the sign bit. Then we
5841 normalize with a shift, if needed.
5843 Two operations that can do the above actions are ABS and FFS, so try
5844 them. If that doesn't work, and MODE is smaller than a full word,
5845 we can use zero-extension to the wider mode (an unsigned conversion)
5846 as the operation. */
5848 /* Note that ABS doesn't yield a positive number for INT_MIN, but
5849 that is compensated by the subsequent overflow when subtracting
5852 if (optab_handler (abs_optab
, mode
) != CODE_FOR_nothing
)
5853 tem
= expand_unop (mode
, abs_optab
, op0
, subtarget
, 1);
5854 else if (optab_handler (ffs_optab
, mode
) != CODE_FOR_nothing
)
5855 tem
= expand_unop (mode
, ffs_optab
, op0
, subtarget
, 1);
5856 else if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
5858 tem
= convert_modes (word_mode
, mode
, op0
, 1);
5865 tem
= expand_binop (mode
, sub_optab
, tem
, const1_rtx
, subtarget
,
5868 tem
= expand_unop (mode
, neg_optab
, tem
, subtarget
, 0);
5871 /* If we couldn't do it that way, for NE we can "or" the two's complement
5872 of the value with itself. For EQ, we take the one's complement of
5873 that "or", which is an extra insn, so we only handle EQ if branches
5878 || BRANCH_COST (optimize_insn_for_speed_p (),
5881 if (rtx_equal_p (subtarget
, op0
))
5884 tem
= expand_unop (mode
, neg_optab
, op0
, subtarget
, 0);
5885 tem
= expand_binop (mode
, ior_optab
, tem
, op0
, subtarget
, 0,
5888 if (tem
&& code
== EQ
)
5889 tem
= expand_unop (mode
, one_cmpl_optab
, tem
, subtarget
, 0);
5893 if (tem
&& normalizep
)
5894 tem
= maybe_expand_shift (RSHIFT_EXPR
, mode
, tem
,
5895 GET_MODE_BITSIZE (mode
) - 1,
5896 subtarget
, normalizep
== 1);
5902 else if (GET_MODE (tem
) != target_mode
)
5904 convert_move (target
, tem
, 0);
5907 else if (!subtarget
)
5909 emit_move_insn (target
, tem
);
5914 delete_insns_since (last
);
5919 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
5920 and storing in TARGET. Normally return TARGET.
5921 Return 0 if that cannot be done.
5923 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
5924 it is VOIDmode, they cannot both be CONST_INT.
5926 UNSIGNEDP is for the case where we have to widen the operands
5927 to perform the operation. It says to use zero-extension.
5929 NORMALIZEP is 1 if we should convert the result to be either zero
5930 or one. Normalize is -1 if we should convert the result to be
5931 either zero or -1. If NORMALIZEP is zero, the result will be left
5932 "raw" out of the scc insn. */
5935 emit_store_flag (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
5936 machine_mode mode
, int unsignedp
, int normalizep
)
5938 machine_mode target_mode
= target
? GET_MODE (target
) : VOIDmode
;
5939 enum rtx_code rcode
;
5944 /* If we compare constants, we shouldn't use a store-flag operation,
5945 but a constant load. We can get there via the vanilla route that
5946 usually generates a compare-branch sequence, but will in this case
5947 fold the comparison to a constant, and thus elide the branch. */
5948 if (CONSTANT_P (op0
) && CONSTANT_P (op1
))
5951 tem
= emit_store_flag_1 (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
,
5956 /* If we reached here, we can't do this with a scc insn, however there
5957 are some comparisons that can be done in other ways. Don't do any
5958 of these cases if branches are very cheap. */
5959 if (BRANCH_COST (optimize_insn_for_speed_p (), false) == 0)
5962 /* See what we need to return. We can only return a 1, -1, or the
5965 if (normalizep
== 0)
5967 if (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
5968 normalizep
= STORE_FLAG_VALUE
;
5970 else if (val_signbit_p (mode
, STORE_FLAG_VALUE
))
5976 last
= get_last_insn ();
5978 /* If optimizing, use different pseudo registers for each insn, instead
5979 of reusing the same pseudo. This leads to better CSE, but slows
5980 down the compiler, since there are more pseudos. */
5981 subtarget
= (!optimize
5982 && (target_mode
== mode
)) ? target
: NULL_RTX
;
5983 trueval
= GEN_INT (normalizep
? normalizep
: STORE_FLAG_VALUE
);
5985 /* For floating-point comparisons, try the reverse comparison or try
5986 changing the "orderedness" of the comparison. */
5987 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
5989 enum rtx_code first_code
;
5992 rcode
= reverse_condition_maybe_unordered (code
);
5993 if (can_compare_p (rcode
, mode
, ccp_store_flag
)
5994 && (code
== ORDERED
|| code
== UNORDERED
5995 || (! HONOR_NANS (mode
) && (code
== LTGT
|| code
== UNEQ
))
5996 || (! HONOR_SNANS (mode
) && (code
== EQ
|| code
== NE
))))
5998 int want_add
= ((STORE_FLAG_VALUE
== 1 && normalizep
== -1)
5999 || (STORE_FLAG_VALUE
== -1 && normalizep
== 1));
6001 /* For the reverse comparison, use either an addition or a XOR. */
6003 && rtx_cost (GEN_INT (normalizep
), mode
, PLUS
, 1,
6004 optimize_insn_for_speed_p ()) == 0)
6006 tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
6007 STORE_FLAG_VALUE
, target_mode
);
6009 return expand_binop (target_mode
, add_optab
, tem
,
6010 gen_int_mode (normalizep
, target_mode
),
6011 target
, 0, OPTAB_WIDEN
);
6014 && rtx_cost (trueval
, mode
, XOR
, 1,
6015 optimize_insn_for_speed_p ()) == 0)
6017 tem
= emit_store_flag_1 (subtarget
, rcode
, op0
, op1
, mode
, 0,
6018 normalizep
, target_mode
);
6020 return expand_binop (target_mode
, xor_optab
, tem
, trueval
,
6021 target
, INTVAL (trueval
) >= 0,
6026 delete_insns_since (last
);
6028 /* Cannot split ORDERED and UNORDERED, only try the above trick. */
6029 if (code
== ORDERED
|| code
== UNORDERED
)
6032 and_them
= split_comparison (code
, mode
, &first_code
, &code
);
6034 /* If there are no NaNs, the first comparison should always fall through.
6035 Effectively change the comparison to the other one. */
6036 if (!HONOR_NANS (mode
))
6038 gcc_assert (first_code
== (and_them
? ORDERED
: UNORDERED
));
6039 return emit_store_flag_1 (target
, code
, op0
, op1
, mode
, 0, normalizep
,
6043 if (!HAVE_conditional_move
)
6046 /* Try using a setcc instruction for ORDERED/UNORDERED, followed by a
6047 conditional move. */
6048 tem
= emit_store_flag_1 (subtarget
, first_code
, op0
, op1
, mode
, 0,
6049 normalizep
, target_mode
);
6054 tem
= emit_conditional_move (target
, code
, op0
, op1
, mode
,
6055 tem
, const0_rtx
, GET_MODE (tem
), 0);
6057 tem
= emit_conditional_move (target
, code
, op0
, op1
, mode
,
6058 trueval
, tem
, GET_MODE (tem
), 0);
6061 delete_insns_since (last
);
6065 /* The remaining tricks only apply to integer comparisons. */
6067 scalar_int_mode int_mode
;
6068 if (is_int_mode (mode
, &int_mode
))
6069 return emit_store_flag_int (target
, subtarget
, code
, op0
, op1
, int_mode
,
6070 unsignedp
, normalizep
, trueval
);
6075 /* Like emit_store_flag, but always succeeds. */
6078 emit_store_flag_force (rtx target
, enum rtx_code code
, rtx op0
, rtx op1
,
6079 machine_mode mode
, int unsignedp
, int normalizep
)
6082 rtx_code_label
*label
;
6083 rtx trueval
, falseval
;
6085 /* First see if emit_store_flag can do the job. */
6086 tem
= emit_store_flag (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
);
6091 target
= gen_reg_rtx (word_mode
);
6093 /* If this failed, we have to do this with set/compare/jump/set code.
6094 For foo != 0, if foo is in OP0, just replace it with 1 if nonzero. */
6095 trueval
= normalizep
? GEN_INT (normalizep
) : const1_rtx
;
6097 && GET_MODE_CLASS (mode
) == MODE_INT
6100 && op1
== const0_rtx
)
6102 label
= gen_label_rtx ();
6103 do_compare_rtx_and_jump (target
, const0_rtx
, EQ
, unsignedp
, mode
,
6104 NULL_RTX
, NULL
, label
,
6105 profile_probability::uninitialized ());
6106 emit_move_insn (target
, trueval
);
6112 || reg_mentioned_p (target
, op0
) || reg_mentioned_p (target
, op1
))
6113 target
= gen_reg_rtx (GET_MODE (target
));
6115 /* Jump in the right direction if the target cannot implement CODE
6116 but can jump on its reverse condition. */
6117 falseval
= const0_rtx
;
6118 if (! can_compare_p (code
, mode
, ccp_jump
)
6119 && (! FLOAT_MODE_P (mode
)
6120 || code
== ORDERED
|| code
== UNORDERED
6121 || (! HONOR_NANS (mode
) && (code
== LTGT
|| code
== UNEQ
))
6122 || (! HONOR_SNANS (mode
) && (code
== EQ
|| code
== NE
))))
6124 enum rtx_code rcode
;
6125 if (FLOAT_MODE_P (mode
))
6126 rcode
= reverse_condition_maybe_unordered (code
);
6128 rcode
= reverse_condition (code
);
6130 /* Canonicalize to UNORDERED for the libcall. */
6131 if (can_compare_p (rcode
, mode
, ccp_jump
)
6132 || (code
== ORDERED
&& ! can_compare_p (ORDERED
, mode
, ccp_jump
)))
6135 trueval
= const0_rtx
;
6140 emit_move_insn (target
, trueval
);
6141 label
= gen_label_rtx ();
6142 do_compare_rtx_and_jump (op0
, op1
, code
, unsignedp
, mode
, NULL_RTX
, NULL
,
6143 label
, profile_probability::uninitialized ());
6145 emit_move_insn (target
, falseval
);
6151 /* Perform possibly multi-word comparison and conditional jump to LABEL
6152 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE. This is
6153 now a thin wrapper around do_compare_rtx_and_jump. */
6156 do_cmp_and_jump (rtx arg1
, rtx arg2
, enum rtx_code op
, machine_mode mode
,
6157 rtx_code_label
*label
)
6159 int unsignedp
= (op
== LTU
|| op
== LEU
|| op
== GTU
|| op
== GEU
);
6160 do_compare_rtx_and_jump (arg1
, arg2
, op
, unsignedp
, mode
, NULL_RTX
,
6161 NULL
, label
, profile_probability::uninitialized ());