1 /* Perform simple optimizations to clean up the result of reload.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997,
3 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
48 #include "tree-pass.h"
52 static int reload_cse_noop_set_p (rtx
);
53 static void reload_cse_simplify (rtx
, rtx
);
54 static void reload_cse_regs_1 (rtx
);
55 static int reload_cse_simplify_set (rtx
, rtx
);
56 static int reload_cse_simplify_operands (rtx
, rtx
);
58 static void reload_combine (void);
59 static void reload_combine_note_use (rtx
*, rtx
);
60 static void reload_combine_note_store (rtx
, const_rtx
, void *);
62 static void reload_cse_move2add (rtx
);
63 static void move2add_note_store (rtx
, const_rtx
, void *);
65 /* Call cse / combine like post-reload optimization phases.
66 FIRST is the first instruction. */
68 reload_cse_regs (rtx first ATTRIBUTE_UNUSED
)
70 reload_cse_regs_1 (first
);
72 reload_cse_move2add (first
);
73 if (flag_expensive_optimizations
)
74 reload_cse_regs_1 (first
);
77 /* See whether a single set SET is a noop. */
79 reload_cse_noop_set_p (rtx set
)
81 if (cselib_reg_set_mode (SET_DEST (set
)) != GET_MODE (SET_DEST (set
)))
84 return rtx_equal_for_cselib_p (SET_DEST (set
), SET_SRC (set
));
87 /* Try to simplify INSN. */
89 reload_cse_simplify (rtx insn
, rtx testreg
)
91 rtx body
= PATTERN (insn
);
93 if (GET_CODE (body
) == SET
)
97 /* Simplify even if we may think it is a no-op.
98 We may think a memory load of a value smaller than WORD_SIZE
99 is redundant because we haven't taken into account possible
100 implicit extension. reload_cse_simplify_set() will bring
101 this out, so it's safer to simplify before we delete. */
102 count
+= reload_cse_simplify_set (body
, insn
);
104 if (!count
&& reload_cse_noop_set_p (body
))
106 rtx value
= SET_DEST (body
);
108 && ! REG_FUNCTION_VALUE_P (value
))
110 delete_insn_and_edges (insn
);
115 apply_change_group ();
117 reload_cse_simplify_operands (insn
, testreg
);
119 else if (GET_CODE (body
) == PARALLEL
)
123 rtx value
= NULL_RTX
;
125 /* Registers mentioned in the clobber list for an asm cannot be reused
126 within the body of the asm. Invalidate those registers now so that
127 we don't try to substitute values for them. */
128 if (asm_noperands (body
) >= 0)
130 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
132 rtx part
= XVECEXP (body
, 0, i
);
133 if (GET_CODE (part
) == CLOBBER
&& REG_P (XEXP (part
, 0)))
134 cselib_invalidate_rtx (XEXP (part
, 0));
138 /* If every action in a PARALLEL is a noop, we can delete
139 the entire PARALLEL. */
140 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
142 rtx part
= XVECEXP (body
, 0, i
);
143 if (GET_CODE (part
) == SET
)
145 if (! reload_cse_noop_set_p (part
))
147 if (REG_P (SET_DEST (part
))
148 && REG_FUNCTION_VALUE_P (SET_DEST (part
)))
152 value
= SET_DEST (part
);
155 else if (GET_CODE (part
) != CLOBBER
)
161 delete_insn_and_edges (insn
);
162 /* We're done with this insn. */
166 /* It's not a no-op, but we can try to simplify it. */
167 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
168 if (GET_CODE (XVECEXP (body
, 0, i
)) == SET
)
169 count
+= reload_cse_simplify_set (XVECEXP (body
, 0, i
), insn
);
172 apply_change_group ();
174 reload_cse_simplify_operands (insn
, testreg
);
178 /* Do a very simple CSE pass over the hard registers.
180 This function detects no-op moves where we happened to assign two
181 different pseudo-registers to the same hard register, and then
182 copied one to the other. Reload will generate a useless
183 instruction copying a register to itself.
185 This function also detects cases where we load a value from memory
186 into two different registers, and (if memory is more expensive than
187 registers) changes it to simply copy the first register into the
190 Another optimization is performed that scans the operands of each
191 instruction to see whether the value is already available in a
192 hard register. It then replaces the operand with the hard register
193 if possible, much like an optional reload would. */
196 reload_cse_regs_1 (rtx first
)
199 rtx testreg
= gen_rtx_REG (VOIDmode
, -1);
202 init_alias_analysis ();
204 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
))
207 reload_cse_simplify (insn
, testreg
);
209 cselib_process_insn (insn
);
213 end_alias_analysis ();
217 /* Try to simplify a single SET instruction. SET is the set pattern.
218 INSN is the instruction it came from.
219 This function only handles one case: if we set a register to a value
220 which is not a register, we try to find that value in some other register
221 and change the set into a register copy. */
224 reload_cse_simplify_set (rtx set
, rtx insn
)
229 enum reg_class dclass
;
232 struct elt_loc_list
*l
;
233 #ifdef LOAD_EXTEND_OP
234 enum rtx_code extend_op
= UNKNOWN
;
237 dreg
= true_regnum (SET_DEST (set
));
242 if (side_effects_p (src
) || true_regnum (src
) >= 0)
245 dclass
= REGNO_REG_CLASS (dreg
);
247 #ifdef LOAD_EXTEND_OP
248 /* When replacing a memory with a register, we need to honor assumptions
249 that combine made wrt the contents of sign bits. We'll do this by
250 generating an extend instruction instead of a reg->reg copy. Thus
251 the destination must be a register that we can widen. */
253 && GET_MODE_BITSIZE (GET_MODE (src
)) < BITS_PER_WORD
254 && (extend_op
= LOAD_EXTEND_OP (GET_MODE (src
))) != UNKNOWN
255 && !REG_P (SET_DEST (set
)))
259 val
= cselib_lookup (src
, GET_MODE (SET_DEST (set
)), 0);
263 /* If memory loads are cheaper than register copies, don't change them. */
265 old_cost
= MEMORY_MOVE_COST (GET_MODE (src
), dclass
, 1);
266 else if (REG_P (src
))
267 old_cost
= REGISTER_MOVE_COST (GET_MODE (src
),
268 REGNO_REG_CLASS (REGNO (src
)), dclass
);
270 old_cost
= rtx_cost (src
, SET
);
272 for (l
= val
->locs
; l
; l
= l
->next
)
274 rtx this_rtx
= l
->loc
;
277 if (CONSTANT_P (this_rtx
) && ! references_value_p (this_rtx
, 0))
279 #ifdef LOAD_EXTEND_OP
280 if (extend_op
!= UNKNOWN
)
282 HOST_WIDE_INT this_val
;
284 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
285 constants, such as SYMBOL_REF, cannot be extended. */
286 if (GET_CODE (this_rtx
) != CONST_INT
)
289 this_val
= INTVAL (this_rtx
);
293 this_val
&= GET_MODE_MASK (GET_MODE (src
));
296 /* ??? In theory we're already extended. */
297 if (this_val
== trunc_int_for_mode (this_val
, GET_MODE (src
)))
302 this_rtx
= GEN_INT (this_val
);
305 this_cost
= rtx_cost (this_rtx
, SET
);
307 else if (REG_P (this_rtx
))
309 #ifdef LOAD_EXTEND_OP
310 if (extend_op
!= UNKNOWN
)
312 this_rtx
= gen_rtx_fmt_e (extend_op
, word_mode
, this_rtx
);
313 this_cost
= rtx_cost (this_rtx
, SET
);
317 this_cost
= REGISTER_MOVE_COST (GET_MODE (this_rtx
),
318 REGNO_REG_CLASS (REGNO (this_rtx
)),
324 /* If equal costs, prefer registers over anything else. That
325 tends to lead to smaller instructions on some machines. */
326 if (this_cost
< old_cost
327 || (this_cost
== old_cost
329 && !REG_P (SET_SRC (set
))))
331 #ifdef LOAD_EXTEND_OP
332 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set
))) < BITS_PER_WORD
333 && extend_op
!= UNKNOWN
334 #ifdef CANNOT_CHANGE_MODE_CLASS
335 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set
)),
337 REGNO_REG_CLASS (REGNO (SET_DEST (set
))))
341 rtx wide_dest
= gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
)));
342 ORIGINAL_REGNO (wide_dest
) = ORIGINAL_REGNO (SET_DEST (set
));
343 validate_change (insn
, &SET_DEST (set
), wide_dest
, 1);
347 validate_unshare_change (insn
, &SET_SRC (set
), this_rtx
, 1);
348 old_cost
= this_cost
, did_change
= 1;
355 /* Try to replace operands in INSN with equivalent values that are already
356 in registers. This can be viewed as optional reloading.
358 For each non-register operand in the insn, see if any hard regs are
359 known to be equivalent to that operand. Record the alternatives which
360 can accept these hard registers. Among all alternatives, select the
361 ones which are better or equal to the one currently matching, where
362 "better" is in terms of '?' and '!' constraints. Among the remaining
363 alternatives, select the one which replaces most operands with
367 reload_cse_simplify_operands (rtx insn
, rtx testreg
)
371 /* For each operand, all registers that are equivalent to it. */
372 HARD_REG_SET equiv_regs
[MAX_RECOG_OPERANDS
];
374 const char *constraints
[MAX_RECOG_OPERANDS
];
376 /* Vector recording how bad an alternative is. */
377 int *alternative_reject
;
378 /* Vector recording how many registers can be introduced by choosing
380 int *alternative_nregs
;
381 /* Array of vectors recording, for each operand and each alternative,
382 which hard register to substitute, or -1 if the operand should be
384 int *op_alt_regno
[MAX_RECOG_OPERANDS
];
385 /* Array of alternatives, sorted in order of decreasing desirability. */
386 int *alternative_order
;
390 if (recog_data
.n_alternatives
== 0 || recog_data
.n_operands
== 0)
393 /* Figure out which alternative currently matches. */
394 if (! constrain_operands (1))
395 fatal_insn_not_found (insn
);
397 alternative_reject
= alloca (recog_data
.n_alternatives
* sizeof (int));
398 alternative_nregs
= alloca (recog_data
.n_alternatives
* sizeof (int));
399 alternative_order
= alloca (recog_data
.n_alternatives
* sizeof (int));
400 memset (alternative_reject
, 0, recog_data
.n_alternatives
* sizeof (int));
401 memset (alternative_nregs
, 0, recog_data
.n_alternatives
* sizeof (int));
403 /* For each operand, find out which regs are equivalent. */
404 for (i
= 0; i
< recog_data
.n_operands
; i
++)
407 struct elt_loc_list
*l
;
409 enum machine_mode mode
;
411 CLEAR_HARD_REG_SET (equiv_regs
[i
]);
413 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
414 right, so avoid the problem here. Likewise if we have a constant
415 and the insn pattern doesn't tell us the mode we need. */
416 if (LABEL_P (recog_data
.operand
[i
])
417 || (CONSTANT_P (recog_data
.operand
[i
])
418 && recog_data
.operand_mode
[i
] == VOIDmode
))
421 op
= recog_data
.operand
[i
];
422 mode
= GET_MODE (op
);
423 #ifdef LOAD_EXTEND_OP
425 && GET_MODE_BITSIZE (mode
) < BITS_PER_WORD
426 && LOAD_EXTEND_OP (mode
) != UNKNOWN
)
428 rtx set
= single_set (insn
);
430 /* We might have multiple sets, some of which do implicit
431 extension. Punt on this for now. */
434 /* If the destination is also a MEM or a STRICT_LOW_PART, no
436 Also, if there is an explicit extension, we don't have to
437 worry about an implicit one. */
438 else if (MEM_P (SET_DEST (set
))
439 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
440 || GET_CODE (SET_SRC (set
)) == ZERO_EXTEND
441 || GET_CODE (SET_SRC (set
)) == SIGN_EXTEND
)
442 ; /* Continue ordinary processing. */
443 #ifdef CANNOT_CHANGE_MODE_CLASS
444 /* If the register cannot change mode to word_mode, it follows that
445 it cannot have been used in word_mode. */
446 else if (REG_P (SET_DEST (set
))
447 && CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set
)),
449 REGNO_REG_CLASS (REGNO (SET_DEST (set
)))))
450 ; /* Continue ordinary processing. */
452 /* If this is a straight load, make the extension explicit. */
453 else if (REG_P (SET_DEST (set
))
454 && recog_data
.n_operands
== 2
455 && SET_SRC (set
) == op
456 && SET_DEST (set
) == recog_data
.operand
[1-i
])
458 validate_change (insn
, recog_data
.operand_loc
[i
],
459 gen_rtx_fmt_e (LOAD_EXTEND_OP (mode
),
462 validate_change (insn
, recog_data
.operand_loc
[1-i
],
463 gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
))),
465 if (! apply_change_group ())
467 return reload_cse_simplify_operands (insn
, testreg
);
470 /* ??? There might be arithmetic operations with memory that are
471 safe to optimize, but is it worth the trouble? */
474 #endif /* LOAD_EXTEND_OP */
475 v
= cselib_lookup (op
, recog_data
.operand_mode
[i
], 0);
479 for (l
= v
->locs
; l
; l
= l
->next
)
481 SET_HARD_REG_BIT (equiv_regs
[i
], REGNO (l
->loc
));
484 for (i
= 0; i
< recog_data
.n_operands
; i
++)
486 enum machine_mode mode
;
490 op_alt_regno
[i
] = alloca (recog_data
.n_alternatives
* sizeof (int));
491 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
492 op_alt_regno
[i
][j
] = -1;
494 p
= constraints
[i
] = recog_data
.constraints
[i
];
495 mode
= recog_data
.operand_mode
[i
];
497 /* Add the reject values for each alternative given by the constraints
506 alternative_reject
[j
] += 3;
508 alternative_reject
[j
] += 300;
511 /* We won't change operands which are already registers. We
512 also don't want to modify output operands. */
513 regno
= true_regnum (recog_data
.operand
[i
]);
515 || constraints
[i
][0] == '='
516 || constraints
[i
][0] == '+')
519 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
521 int class = (int) NO_REGS
;
523 if (! TEST_HARD_REG_BIT (equiv_regs
[i
], regno
))
526 SET_REGNO (testreg
, regno
);
527 PUT_MODE (testreg
, mode
);
529 /* We found a register equal to this operand. Now look for all
530 alternatives that can accept this register and have not been
531 assigned a register they can use yet. */
540 case '=': case '+': case '?':
541 case '#': case '&': case '!':
543 case '0': case '1': case '2': case '3': case '4':
544 case '5': case '6': case '7': case '8': case '9':
545 case 'm': case '<': case '>': case 'V': case 'o':
546 case 'E': case 'F': case 'G': case 'H':
547 case 's': case 'i': case 'n':
548 case 'I': case 'J': case 'K': case 'L':
549 case 'M': case 'N': case 'O': case 'P':
551 /* These don't say anything we care about. */
555 class = reg_class_subunion
[(int) class][(int) GENERAL_REGS
];
560 = (reg_class_subunion
562 [(int) REG_CLASS_FROM_CONSTRAINT ((unsigned char) c
, p
)]);
566 /* See if REGNO fits this alternative, and set it up as the
567 replacement register if we don't have one for this
568 alternative yet and the operand being replaced is not
569 a cheap CONST_INT. */
570 if (op_alt_regno
[i
][j
] == -1
571 && reg_fits_class_p (testreg
, class, 0, mode
)
572 && (GET_CODE (recog_data
.operand
[i
]) != CONST_INT
573 || (rtx_cost (recog_data
.operand
[i
], SET
)
574 > rtx_cost (testreg
, SET
))))
576 alternative_nregs
[j
]++;
577 op_alt_regno
[i
][j
] = regno
;
580 class = (int) NO_REGS
;
583 p
+= CONSTRAINT_LEN (c
, p
);
591 /* Record all alternatives which are better or equal to the currently
592 matching one in the alternative_order array. */
593 for (i
= j
= 0; i
< recog_data
.n_alternatives
; i
++)
594 if (alternative_reject
[i
] <= alternative_reject
[which_alternative
])
595 alternative_order
[j
++] = i
;
596 recog_data
.n_alternatives
= j
;
598 /* Sort it. Given a small number of alternatives, a dumb algorithm
599 won't hurt too much. */
600 for (i
= 0; i
< recog_data
.n_alternatives
- 1; i
++)
603 int best_reject
= alternative_reject
[alternative_order
[i
]];
604 int best_nregs
= alternative_nregs
[alternative_order
[i
]];
607 for (j
= i
+ 1; j
< recog_data
.n_alternatives
; j
++)
609 int this_reject
= alternative_reject
[alternative_order
[j
]];
610 int this_nregs
= alternative_nregs
[alternative_order
[j
]];
612 if (this_reject
< best_reject
613 || (this_reject
== best_reject
&& this_nregs
> best_nregs
))
616 best_reject
= this_reject
;
617 best_nregs
= this_nregs
;
621 tmp
= alternative_order
[best
];
622 alternative_order
[best
] = alternative_order
[i
];
623 alternative_order
[i
] = tmp
;
626 /* Substitute the operands as determined by op_alt_regno for the best
628 j
= alternative_order
[0];
630 for (i
= 0; i
< recog_data
.n_operands
; i
++)
632 enum machine_mode mode
= recog_data
.operand_mode
[i
];
633 if (op_alt_regno
[i
][j
] == -1)
636 validate_change (insn
, recog_data
.operand_loc
[i
],
637 gen_rtx_REG (mode
, op_alt_regno
[i
][j
]), 1);
640 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
642 int op
= recog_data
.dup_num
[i
];
643 enum machine_mode mode
= recog_data
.operand_mode
[op
];
645 if (op_alt_regno
[op
][j
] == -1)
648 validate_change (insn
, recog_data
.dup_loc
[i
],
649 gen_rtx_REG (mode
, op_alt_regno
[op
][j
]), 1);
652 return apply_change_group ();
655 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
657 This code might also be useful when reload gave up on reg+reg addressing
658 because of clashes between the return register and INDEX_REG_CLASS. */
660 /* The maximum number of uses of a register we can keep track of to
661 replace them with reg+reg addressing. */
662 #define RELOAD_COMBINE_MAX_USES 6
664 /* INSN is the insn where a register has ben used, and USEP points to the
665 location of the register within the rtl. */
666 struct reg_use
{ rtx insn
, *usep
; };
668 /* If the register is used in some unknown fashion, USE_INDEX is negative.
669 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
670 indicates where it becomes live again.
671 Otherwise, USE_INDEX is the index of the last encountered use of the
672 register (which is first among these we have seen since we scan backwards),
673 OFFSET contains the constant offset that is added to the register in
674 all encountered uses, and USE_RUID indicates the first encountered, i.e.
676 STORE_RUID is always meaningful if we only want to use a value in a
677 register in a different place: it denotes the next insn in the insn
678 stream (i.e. the last encountered) that sets or clobbers the register. */
681 struct reg_use reg_use
[RELOAD_COMBINE_MAX_USES
];
686 } reg_state
[FIRST_PSEUDO_REGISTER
];
688 /* Reverse linear uid. This is increased in reload_combine while scanning
689 the instructions from last to first. It is used to set last_label_ruid
690 and the store_ruid / use_ruid fields in reg_state. */
691 static int reload_combine_ruid
;
693 #define LABEL_LIVE(LABEL) \
694 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
697 reload_combine (void)
700 int first_index_reg
= -1;
701 int last_index_reg
= 0;
706 int min_labelno
, n_labels
;
707 HARD_REG_SET ever_live_at_start
, *label_live
;
709 /* If reg+reg can be used in offsetable memory addresses, the main chunk of
710 reload has already used it where appropriate, so there is no use in
711 trying to generate it now. */
712 if (double_reg_address_ok
&& INDEX_REG_CLASS
!= NO_REGS
)
715 /* To avoid wasting too much time later searching for an index register,
716 determine the minimum and maximum index register numbers. */
717 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
718 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], r
))
720 if (first_index_reg
== -1)
726 /* If no index register is available, we can quit now. */
727 if (first_index_reg
== -1)
730 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
731 information is a bit fuzzy immediately after reload, but it's
732 still good enough to determine which registers are live at a jump
734 min_labelno
= get_first_label_num ();
735 n_labels
= max_label_num () - min_labelno
;
736 label_live
= XNEWVEC (HARD_REG_SET
, n_labels
);
737 CLEAR_HARD_REG_SET (ever_live_at_start
);
739 FOR_EACH_BB_REVERSE (bb
)
745 bitmap live_in
= df_get_live_in (bb
);
747 REG_SET_TO_HARD_REG_SET (live
, live_in
);
748 compute_use_by_pseudos (&live
, live_in
);
749 COPY_HARD_REG_SET (LABEL_LIVE (insn
), live
);
750 IOR_HARD_REG_SET (ever_live_at_start
, live
);
754 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
755 last_label_ruid
= reload_combine_ruid
= 0;
756 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
758 reg_state
[r
].store_ruid
= reload_combine_ruid
;
760 reg_state
[r
].use_index
= -1;
762 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
765 for (insn
= get_last_insn (); insn
; insn
= PREV_INSN (insn
))
769 /* We cannot do our optimization across labels. Invalidating all the use
770 information we have would be costly, so we just note where the label
771 is and then later disable any optimization that would cross it. */
773 last_label_ruid
= reload_combine_ruid
;
774 else if (BARRIER_P (insn
))
775 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
777 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
782 reload_combine_ruid
++;
784 /* Look for (set (REGX) (CONST_INT))
785 (set (REGX) (PLUS (REGX) (REGY)))
789 (set (REGZ) (CONST_INT))
791 ... (MEM (PLUS (REGZ) (REGY)))... .
793 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
794 and that we know all uses of REGX before it dies.
795 Also, explicitly check that REGX != REGY; our life information
796 does not yet show whether REGY changes in this insn. */
797 set
= single_set (insn
);
799 && REG_P (SET_DEST (set
))
800 && (hard_regno_nregs
[REGNO (SET_DEST (set
))]
801 [GET_MODE (SET_DEST (set
))]
803 && GET_CODE (SET_SRC (set
)) == PLUS
804 && REG_P (XEXP (SET_SRC (set
), 1))
805 && rtx_equal_p (XEXP (SET_SRC (set
), 0), SET_DEST (set
))
806 && !rtx_equal_p (XEXP (SET_SRC (set
), 1), SET_DEST (set
))
807 && last_label_ruid
< reg_state
[REGNO (SET_DEST (set
))].use_ruid
)
809 rtx reg
= SET_DEST (set
);
810 rtx plus
= SET_SRC (set
);
811 rtx base
= XEXP (plus
, 1);
812 rtx prev
= prev_nonnote_insn (insn
);
813 rtx prev_set
= prev
? single_set (prev
) : NULL_RTX
;
814 unsigned int regno
= REGNO (reg
);
815 rtx const_reg
= NULL_RTX
;
816 rtx reg_sum
= NULL_RTX
;
818 /* Now, we need an index register.
819 We'll set index_reg to this index register, const_reg to the
820 register that is to be loaded with the constant
821 (denoted as REGZ in the substitution illustration above),
822 and reg_sum to the register-register that we want to use to
823 substitute uses of REG (typically in MEMs) with.
824 First check REG and BASE for being index registers;
825 we can use them even if they are not dead. */
826 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], regno
)
827 || TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
835 /* Otherwise, look for a free index register. Since we have
836 checked above that neither REG nor BASE are index registers,
837 if we find anything at all, it will be different from these
839 for (i
= first_index_reg
; i
<= last_index_reg
; i
++)
841 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
843 && reg_state
[i
].use_index
== RELOAD_COMBINE_MAX_USES
844 && reg_state
[i
].store_ruid
<= reg_state
[regno
].use_ruid
845 && hard_regno_nregs
[i
][GET_MODE (reg
)] == 1)
847 rtx index_reg
= gen_rtx_REG (GET_MODE (reg
), i
);
849 const_reg
= index_reg
;
850 reg_sum
= gen_rtx_PLUS (GET_MODE (reg
), index_reg
, base
);
856 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
857 (REGY), i.e. BASE, is not clobbered before the last use we'll
860 && GET_CODE (SET_SRC (prev_set
)) == CONST_INT
861 && rtx_equal_p (SET_DEST (prev_set
), reg
)
862 && reg_state
[regno
].use_index
>= 0
863 && (reg_state
[REGNO (base
)].store_ruid
864 <= reg_state
[regno
].use_ruid
)
869 /* Change destination register and, if necessary, the
870 constant value in PREV, the constant loading instruction. */
871 validate_change (prev
, &SET_DEST (prev_set
), const_reg
, 1);
872 if (reg_state
[regno
].offset
!= const0_rtx
)
873 validate_change (prev
,
875 GEN_INT (INTVAL (SET_SRC (prev_set
))
876 + INTVAL (reg_state
[regno
].offset
)),
879 /* Now for every use of REG that we have recorded, replace REG
881 for (i
= reg_state
[regno
].use_index
;
882 i
< RELOAD_COMBINE_MAX_USES
; i
++)
883 validate_unshare_change (reg_state
[regno
].reg_use
[i
].insn
,
884 reg_state
[regno
].reg_use
[i
].usep
,
885 /* Each change must have its own
889 if (apply_change_group ())
891 /* Delete the reg-reg addition. */
894 if (reg_state
[regno
].offset
!= const0_rtx
)
895 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
897 remove_reg_equal_equiv_notes (prev
);
899 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
900 reg_state
[REGNO (const_reg
)].store_ruid
901 = reload_combine_ruid
;
907 note_stores (PATTERN (insn
), reload_combine_note_store
, NULL
);
912 HARD_REG_SET used_regs
;
914 get_call_invalidated_used_regs (insn
, &used_regs
, false);
915 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
916 if (TEST_HARD_REG_BIT (used_regs
, r
))
918 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
919 reg_state
[r
].store_ruid
= reload_combine_ruid
;
922 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
;
923 link
= XEXP (link
, 1))
925 rtx usage_rtx
= XEXP (XEXP (link
, 0), 0);
926 if (REG_P (usage_rtx
))
929 unsigned int start_reg
= REGNO (usage_rtx
);
930 unsigned int num_regs
=
931 hard_regno_nregs
[start_reg
][GET_MODE (usage_rtx
)];
932 unsigned int end_reg
= start_reg
+ num_regs
- 1;
933 for (i
= start_reg
; i
<= end_reg
; i
++)
934 if (GET_CODE (XEXP (link
, 0)) == CLOBBER
)
936 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
937 reg_state
[i
].store_ruid
= reload_combine_ruid
;
940 reg_state
[i
].use_index
= -1;
945 else if (JUMP_P (insn
)
946 && GET_CODE (PATTERN (insn
)) != RETURN
)
948 /* Non-spill registers might be used at the call destination in
949 some unknown fashion, so we have to mark the unknown use. */
952 if ((condjump_p (insn
) || condjump_in_parallel_p (insn
))
953 && JUMP_LABEL (insn
))
954 live
= &LABEL_LIVE (JUMP_LABEL (insn
));
956 live
= &ever_live_at_start
;
958 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; --i
)
959 if (TEST_HARD_REG_BIT (*live
, i
))
960 reg_state
[i
].use_index
= -1;
963 reload_combine_note_use (&PATTERN (insn
), insn
);
964 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
966 if (REG_NOTE_KIND (note
) == REG_INC
967 && REG_P (XEXP (note
, 0)))
969 int regno
= REGNO (XEXP (note
, 0));
971 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
972 reg_state
[regno
].use_index
= -1;
980 /* Check if DST is a register or a subreg of a register; if it is,
981 update reg_state[regno].store_ruid and reg_state[regno].use_index
982 accordingly. Called via note_stores from reload_combine. */
985 reload_combine_note_store (rtx dst
, const_rtx set
, void *data ATTRIBUTE_UNUSED
)
989 enum machine_mode mode
= GET_MODE (dst
);
991 if (GET_CODE (dst
) == SUBREG
)
993 regno
= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
994 GET_MODE (SUBREG_REG (dst
)),
997 dst
= SUBREG_REG (dst
);
1001 regno
+= REGNO (dst
);
1003 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
1004 careful with registers / register parts that are not full words.
1005 Similarly for ZERO_EXTRACT. */
1006 if (GET_CODE (set
) != SET
1007 || GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
1008 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
1010 for (i
= hard_regno_nregs
[regno
][mode
] - 1 + regno
; i
>= regno
; i
--)
1012 reg_state
[i
].use_index
= -1;
1013 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1018 for (i
= hard_regno_nregs
[regno
][mode
] - 1 + regno
; i
>= regno
; i
--)
1020 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1021 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
1026 /* XP points to a piece of rtl that has to be checked for any uses of
1028 *XP is the pattern of INSN, or a part of it.
1029 Called from reload_combine, and recursively by itself. */
1031 reload_combine_note_use (rtx
*xp
, rtx insn
)
1034 enum rtx_code code
= x
->code
;
1037 rtx offset
= const0_rtx
; /* For the REG case below. */
1042 if (REG_P (SET_DEST (x
)))
1044 reload_combine_note_use (&SET_SRC (x
), insn
);
1050 /* If this is the USE of a return value, we can't change it. */
1051 if (REG_P (XEXP (x
, 0)) && REG_FUNCTION_VALUE_P (XEXP (x
, 0)))
1053 /* Mark the return register as used in an unknown fashion. */
1054 rtx reg
= XEXP (x
, 0);
1055 int regno
= REGNO (reg
);
1056 int nregs
= hard_regno_nregs
[regno
][GET_MODE (reg
)];
1058 while (--nregs
>= 0)
1059 reg_state
[regno
+ nregs
].use_index
= -1;
1065 if (REG_P (SET_DEST (x
)))
1067 /* No spurious CLOBBERs of pseudo registers may remain. */
1068 gcc_assert (REGNO (SET_DEST (x
)) < FIRST_PSEUDO_REGISTER
);
1074 /* We are interested in (plus (reg) (const_int)) . */
1075 if (!REG_P (XEXP (x
, 0))
1076 || GET_CODE (XEXP (x
, 1)) != CONST_INT
)
1078 offset
= XEXP (x
, 1);
1083 int regno
= REGNO (x
);
1087 /* No spurious USEs of pseudo registers may remain. */
1088 gcc_assert (regno
< FIRST_PSEUDO_REGISTER
);
1090 nregs
= hard_regno_nregs
[regno
][GET_MODE (x
)];
1092 /* We can't substitute into multi-hard-reg uses. */
1095 while (--nregs
>= 0)
1096 reg_state
[regno
+ nregs
].use_index
= -1;
1100 /* If this register is already used in some unknown fashion, we
1102 If we decrement the index from zero to -1, we can't store more
1103 uses, so this register becomes used in an unknown fashion. */
1104 use_index
= --reg_state
[regno
].use_index
;
1108 if (use_index
!= RELOAD_COMBINE_MAX_USES
- 1)
1110 /* We have found another use for a register that is already
1111 used later. Check if the offsets match; if not, mark the
1112 register as used in an unknown fashion. */
1113 if (! rtx_equal_p (offset
, reg_state
[regno
].offset
))
1115 reg_state
[regno
].use_index
= -1;
1121 /* This is the first use of this register we have seen since we
1122 marked it as dead. */
1123 reg_state
[regno
].offset
= offset
;
1124 reg_state
[regno
].use_ruid
= reload_combine_ruid
;
1126 reg_state
[regno
].reg_use
[use_index
].insn
= insn
;
1127 reg_state
[regno
].reg_use
[use_index
].usep
= xp
;
1135 /* Recursively process the components of X. */
1136 fmt
= GET_RTX_FORMAT (code
);
1137 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1140 reload_combine_note_use (&XEXP (x
, i
), insn
);
1141 else if (fmt
[i
] == 'E')
1143 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1144 reload_combine_note_use (&XVECEXP (x
, i
, j
), insn
);
1149 /* See if we can reduce the cost of a constant by replacing a move
1150 with an add. We track situations in which a register is set to a
1151 constant or to a register plus a constant. */
1152 /* We cannot do our optimization across labels. Invalidating all the
1153 information about register contents we have would be costly, so we
1154 use move2add_last_label_luid to note where the label is and then
1155 later disable any optimization that would cross it.
1156 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
1157 reg_set_luid[n] is greater than move2add_last_label_luid. */
1158 static int reg_set_luid
[FIRST_PSEUDO_REGISTER
];
1160 /* If reg_base_reg[n] is negative, register n has been set to
1161 reg_offset[n] in mode reg_mode[n] .
1162 If reg_base_reg[n] is non-negative, register n has been set to the
1163 sum of reg_offset[n] and the value of register reg_base_reg[n]
1164 before reg_set_luid[n], calculated in mode reg_mode[n] . */
1165 static HOST_WIDE_INT reg_offset
[FIRST_PSEUDO_REGISTER
];
1166 static int reg_base_reg
[FIRST_PSEUDO_REGISTER
];
1167 static enum machine_mode reg_mode
[FIRST_PSEUDO_REGISTER
];
1169 /* move2add_luid is linearly increased while scanning the instructions
1170 from first to last. It is used to set reg_set_luid in
1171 reload_cse_move2add and move2add_note_store. */
1172 static int move2add_luid
;
1174 /* move2add_last_label_luid is set whenever a label is found. Labels
1175 invalidate all previously collected reg_offset data. */
1176 static int move2add_last_label_luid
;
1178 /* ??? We don't know how zero / sign extension is handled, hence we
1179 can't go from a narrower to a wider mode. */
1180 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
1181 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
1182 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
1183 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
1184 GET_MODE_BITSIZE (INMODE))))
1187 reload_cse_move2add (rtx first
)
1192 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
1193 reg_set_luid
[i
] = 0;
1195 move2add_last_label_luid
= 0;
1197 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
), move2add_luid
++)
1203 move2add_last_label_luid
= move2add_luid
;
1204 /* We're going to increment move2add_luid twice after a
1205 label, so that we can use move2add_last_label_luid + 1 as
1206 the luid for constants. */
1210 if (! INSN_P (insn
))
1212 pat
= PATTERN (insn
);
1213 /* For simplicity, we only perform this optimization on
1214 straightforward SETs. */
1215 if (GET_CODE (pat
) == SET
1216 && REG_P (SET_DEST (pat
)))
1218 rtx reg
= SET_DEST (pat
);
1219 int regno
= REGNO (reg
);
1220 rtx src
= SET_SRC (pat
);
1222 /* Check if we have valid information on the contents of this
1223 register in the mode of REG. */
1224 if (reg_set_luid
[regno
] > move2add_last_label_luid
1225 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg
), reg_mode
[regno
])
1226 && dbg_cnt (cse2_move2add
))
1228 /* Try to transform (set (REGX) (CONST_INT A))
1230 (set (REGX) (CONST_INT B))
1232 (set (REGX) (CONST_INT A))
1234 (set (REGX) (plus (REGX) (CONST_INT B-A)))
1236 (set (REGX) (CONST_INT A))
1238 (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
1241 if (GET_CODE (src
) == CONST_INT
&& reg_base_reg
[regno
] < 0)
1243 rtx new_src
= gen_int_mode (INTVAL (src
) - reg_offset
[regno
],
1245 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1246 use (set (reg) (reg)) instead.
1247 We don't delete this insn, nor do we convert it into a
1248 note, to avoid losing register notes or the return
1249 value flag. jump2 already knows how to get rid of
1251 if (new_src
== const0_rtx
)
1253 /* If the constants are different, this is a
1254 truncation, that, if turned into (set (reg)
1255 (reg)), would be discarded. Maybe we should
1256 try a truncMN pattern? */
1257 if (INTVAL (src
) == reg_offset
[regno
])
1258 validate_change (insn
, &SET_SRC (pat
), reg
, 0);
1260 else if (rtx_cost (new_src
, PLUS
) < rtx_cost (src
, SET
)
1261 && have_add2_insn (reg
, new_src
))
1263 rtx tem
= gen_rtx_PLUS (GET_MODE (reg
), reg
, new_src
);
1264 validate_change (insn
, &SET_SRC (pat
), tem
, 0);
1266 else if (GET_MODE (reg
) != BImode
)
1268 enum machine_mode narrow_mode
;
1269 for (narrow_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
1270 narrow_mode
!= VOIDmode
1271 && narrow_mode
!= GET_MODE (reg
);
1272 narrow_mode
= GET_MODE_WIDER_MODE (narrow_mode
))
1274 if (have_insn_for (STRICT_LOW_PART
, narrow_mode
)
1275 && ((reg_offset
[regno
]
1276 & ~GET_MODE_MASK (narrow_mode
))
1278 & ~GET_MODE_MASK (narrow_mode
))))
1280 rtx narrow_reg
= gen_rtx_REG (narrow_mode
,
1282 rtx narrow_src
= gen_int_mode (INTVAL (src
),
1285 gen_rtx_SET (VOIDmode
,
1286 gen_rtx_STRICT_LOW_PART (VOIDmode
,
1289 if (validate_change (insn
, &PATTERN (insn
),
1295 reg_set_luid
[regno
] = move2add_luid
;
1296 reg_mode
[regno
] = GET_MODE (reg
);
1297 reg_offset
[regno
] = INTVAL (src
);
1301 /* Try to transform (set (REGX) (REGY))
1302 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1305 (set (REGX) (PLUS (REGX) (CONST_INT B)))
1308 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1310 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
1311 else if (REG_P (src
)
1312 && reg_set_luid
[regno
] == reg_set_luid
[REGNO (src
)]
1313 && reg_base_reg
[regno
] == reg_base_reg
[REGNO (src
)]
1314 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg
),
1315 reg_mode
[REGNO (src
)]))
1317 rtx next
= next_nonnote_insn (insn
);
1320 set
= single_set (next
);
1322 && SET_DEST (set
) == reg
1323 && GET_CODE (SET_SRC (set
)) == PLUS
1324 && XEXP (SET_SRC (set
), 0) == reg
1325 && GET_CODE (XEXP (SET_SRC (set
), 1)) == CONST_INT
)
1327 rtx src3
= XEXP (SET_SRC (set
), 1);
1328 HOST_WIDE_INT added_offset
= INTVAL (src3
);
1329 HOST_WIDE_INT base_offset
= reg_offset
[REGNO (src
)];
1330 HOST_WIDE_INT regno_offset
= reg_offset
[regno
];
1332 gen_int_mode (added_offset
1338 if (new_src
== const0_rtx
)
1339 /* See above why we create (set (reg) (reg)) here. */
1341 = validate_change (next
, &SET_SRC (set
), reg
, 0);
1342 else if ((rtx_cost (new_src
, PLUS
)
1343 < COSTS_N_INSNS (1) + rtx_cost (src3
, SET
))
1344 && have_add2_insn (reg
, new_src
))
1346 rtx newpat
= gen_rtx_SET (VOIDmode
,
1348 gen_rtx_PLUS (GET_MODE (reg
),
1352 = validate_change (next
, &PATTERN (next
),
1358 reg_mode
[regno
] = GET_MODE (reg
);
1360 trunc_int_for_mode (added_offset
+ base_offset
,
1368 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
1370 if (REG_NOTE_KIND (note
) == REG_INC
1371 && REG_P (XEXP (note
, 0)))
1373 /* Reset the information about this register. */
1374 int regno
= REGNO (XEXP (note
, 0));
1375 if (regno
< FIRST_PSEUDO_REGISTER
)
1376 reg_set_luid
[regno
] = 0;
1379 note_stores (PATTERN (insn
), move2add_note_store
, NULL
);
1381 /* If INSN is a conditional branch, we try to extract an
1382 implicit set out of it. */
1383 if (any_condjump_p (insn
))
1385 rtx cnd
= fis_get_condition (insn
);
1388 && GET_CODE (cnd
) == NE
1389 && REG_P (XEXP (cnd
, 0))
1390 && !reg_set_p (XEXP (cnd
, 0), insn
)
1391 /* The following two checks, which are also in
1392 move2add_note_store, are intended to reduce the
1393 number of calls to gen_rtx_SET to avoid memory
1394 allocation if possible. */
1395 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd
, 0)))
1396 && hard_regno_nregs
[REGNO (XEXP (cnd
, 0))][GET_MODE (XEXP (cnd
, 0))] == 1
1397 && GET_CODE (XEXP (cnd
, 1)) == CONST_INT
)
1400 gen_rtx_SET (VOIDmode
, XEXP (cnd
, 0), XEXP (cnd
, 1));
1401 move2add_note_store (SET_DEST (implicit_set
), implicit_set
, 0);
1405 /* If this is a CALL_INSN, all call used registers are stored with
1409 HARD_REG_SET used_regs
;
1411 get_call_invalidated_used_regs (insn
, &used_regs
, false);
1412 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
1414 if (TEST_HARD_REG_BIT (used_regs
, i
))
1415 /* Reset the information about this register. */
1416 reg_set_luid
[i
] = 0;
1422 /* SET is a SET or CLOBBER that sets DST.
1423 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
1424 Called from reload_cse_move2add via note_stores. */
1427 move2add_note_store (rtx dst
, const_rtx set
, void *data ATTRIBUTE_UNUSED
)
1429 unsigned int regno
= 0;
1430 unsigned int nregs
= 0;
1432 enum machine_mode mode
= GET_MODE (dst
);
1434 if (GET_CODE (dst
) == SUBREG
)
1436 regno
= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
1437 GET_MODE (SUBREG_REG (dst
)),
1440 nregs
= subreg_nregs (dst
);
1441 dst
= SUBREG_REG (dst
);
1444 /* Some targets do argument pushes without adding REG_INC notes. */
1448 dst
= XEXP (dst
, 0);
1449 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_INC
1450 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
)
1451 reg_set_luid
[REGNO (XEXP (dst
, 0))] = 0;
1457 regno
+= REGNO (dst
);
1459 nregs
= hard_regno_nregs
[regno
][mode
];
1461 if (SCALAR_INT_MODE_P (GET_MODE (dst
))
1462 && nregs
== 1 && GET_CODE (set
) == SET
1463 && GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
1464 && GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
)
1466 rtx src
= SET_SRC (set
);
1468 HOST_WIDE_INT offset
;
1470 /* This may be different from mode, if SET_DEST (set) is a
1472 enum machine_mode dst_mode
= GET_MODE (dst
);
1474 switch (GET_CODE (src
))
1477 if (REG_P (XEXP (src
, 0)))
1479 base_reg
= XEXP (src
, 0);
1481 if (GET_CODE (XEXP (src
, 1)) == CONST_INT
)
1482 offset
= INTVAL (XEXP (src
, 1));
1483 else if (REG_P (XEXP (src
, 1))
1484 && (reg_set_luid
[REGNO (XEXP (src
, 1))]
1485 > move2add_last_label_luid
)
1486 && (MODES_OK_FOR_MOVE2ADD
1487 (dst_mode
, reg_mode
[REGNO (XEXP (src
, 1))])))
1489 if (reg_base_reg
[REGNO (XEXP (src
, 1))] < 0)
1490 offset
= reg_offset
[REGNO (XEXP (src
, 1))];
1491 /* Maybe the first register is known to be a
1493 else if (reg_set_luid
[REGNO (base_reg
)]
1494 > move2add_last_label_luid
1495 && (MODES_OK_FOR_MOVE2ADD
1496 (dst_mode
, reg_mode
[REGNO (XEXP (src
, 1))]))
1497 && reg_base_reg
[REGNO (base_reg
)] < 0)
1499 offset
= reg_offset
[REGNO (base_reg
)];
1500 base_reg
= XEXP (src
, 1);
1519 /* Start tracking the register as a constant. */
1520 reg_base_reg
[regno
] = -1;
1521 reg_offset
[regno
] = INTVAL (SET_SRC (set
));
1522 /* We assign the same luid to all registers set to constants. */
1523 reg_set_luid
[regno
] = move2add_last_label_luid
+ 1;
1524 reg_mode
[regno
] = mode
;
1529 /* Invalidate the contents of the register. */
1530 reg_set_luid
[regno
] = 0;
1534 base_regno
= REGNO (base_reg
);
1535 /* If information about the base register is not valid, set it
1536 up as a new base register, pretending its value is known
1537 starting from the current insn. */
1538 if (reg_set_luid
[base_regno
] <= move2add_last_label_luid
)
1540 reg_base_reg
[base_regno
] = base_regno
;
1541 reg_offset
[base_regno
] = 0;
1542 reg_set_luid
[base_regno
] = move2add_luid
;
1543 reg_mode
[base_regno
] = mode
;
1545 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode
,
1546 reg_mode
[base_regno
]))
1549 reg_mode
[regno
] = mode
;
1551 /* Copy base information from our base register. */
1552 reg_set_luid
[regno
] = reg_set_luid
[base_regno
];
1553 reg_base_reg
[regno
] = reg_base_reg
[base_regno
];
1555 /* Compute the sum of the offsets or constants. */
1556 reg_offset
[regno
] = trunc_int_for_mode (offset
1557 + reg_offset
[base_regno
],
1562 unsigned int endregno
= regno
+ nregs
;
1564 for (i
= regno
; i
< endregno
; i
++)
1565 /* Reset the information about this register. */
1566 reg_set_luid
[i
] = 0;
1571 gate_handle_postreload (void)
1573 return (optimize
> 0);
1578 rest_of_handle_postreload (void)
1580 if (!dbg_cnt (postreload_cse
))
1583 /* Do a very simple CSE pass over just the hard registers. */
1584 reload_cse_regs (get_insns ());
1585 /* Reload_cse_regs can eliminate potentially-trapping MEMs.
1586 Remove any EH edges associated with them. */
1587 if (flag_non_call_exceptions
)
1588 purge_all_dead_edges ();
1593 struct tree_opt_pass pass_postreload_cse
=
1595 "postreload", /* name */
1596 gate_handle_postreload
, /* gate */
1597 rest_of_handle_postreload
, /* execute */
1600 0, /* static_pass_number */
1601 TV_RELOAD_CSE_REGS
, /* tv_id */
1602 0, /* properties_required */
1603 0, /* properties_provided */
1604 0, /* properties_destroyed */
1605 0, /* todo_flags_start */
1607 TODO_dump_func
, /* todo_flags_finish */