| blob | 39f9200913623e11983c605c9fcbd893bb370ed3 |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2014 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
102 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
125 /* Number of attempts to combine instructions in this function. */
129 /* Number of attempts that got as far as substitution in this function. */
133 /* Number of instructions combined with added SETs in this function. */
137 /* Number of instructions combined in this function. */
141 /* Totals over entire compilation. */
145 /* combine_instructions may try to replace the right hand side of the
146 second instruction with the value of an associated REG_EQUAL note
147 before throwing it at try_combine. That is problematic when there
148 is a REG_DEAD note for a register used in the old right hand side
149 and can cause distribute_notes to do wrong things. This is the
150 second instruction if it has been so modified, null otherwise. */
154 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
158 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
161 \f
163 /* Record last point of death of (hard or pseudo) register n. */
166 /* Record last point of modification of (hard or pseudo) register n. */
169 /* The next group of fields allows the recording of the last value assigned
170 to (hard or pseudo) register n. We use this information to see if an
171 operation being processed is redundant given a prior operation performed
172 on the register. For example, an `and' with a constant is redundant if
173 all the zero bits are already known to be turned off.
175 We use an approach similar to that used by cse, but change it in the
176 following ways:
178 (1) We do not want to reinitialize at each label.
179 (2) It is useful, but not critical, to know the actual value assigned
180 to a register. Often just its form is helpful.
182 Therefore, we maintain the following fields:
184 last_set_value the last value assigned
185 last_set_label records the value of label_tick when the
186 register was assigned
187 last_set_table_tick records the value of label_tick when a
188 value using the register is assigned
189 last_set_invalid set to nonzero when it is not valid
190 to use the value of this register in some
191 register's value
193 To understand the usage of these tables, it is important to understand
194 the distinction between the value in last_set_value being valid and
195 the register being validly contained in some other expression in the
196 table.
198 (The next two parameters are out of date).
200 reg_stat[i].last_set_value is valid if it is nonzero, and either
201 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
203 Register I may validly appear in any expression returned for the value
204 of another register if reg_n_sets[i] is 1. It may also appear in the
205 value for register J if reg_stat[j].last_set_invalid is zero, or
206 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
208 If an expression is found in the table containing a register which may
209 not validly appear in an expression, the register is replaced by
210 something that won't match, (clobber (const_int 0)). */
212 /* Record last value assigned to (hard or pseudo) register n. */
214 rtx last_set_value;
216 /* Record the value of label_tick when an expression involving register n
217 is placed in last_set_value. */
221 /* Record the value of label_tick when the value for register n is placed in
222 last_set_value. */
226 /* These fields are maintained in parallel with last_set_value and are
227 used to store the mode in which the register was last set, the bits
228 that were known to be zero when it was last set, and the number of
229 sign bits copies it was known to have when it was last set. */
235 /* Set nonzero if references to register n in expressions should not be
236 used. last_set_invalid is set nonzero when this register is being
237 assigned to and last_set_table_tick == label_tick. */
241 /* Some registers that are set more than once and used in more than one
242 basic block are nevertheless always set in similar ways. For example,
243 a QImode register may be loaded from memory in two places on a machine
244 where byte loads zero extend.
246 We record in the following fields if a register has some leading bits
247 that are always equal to the sign bit, and what we know about the
248 nonzero bits of a register, specifically which bits are known to be
249 zero.
251 If an entry is zero, it means that we don't know anything special. */
257 /* Record the value of the label_tick when the last truncation
258 happened. The field truncated_to_mode is only valid if
259 truncation_label == label_tick. */
263 /* Record the last truncation seen for this register. If truncation
264 is not a nop to this mode we might be able to save an explicit
265 truncation if we know that value already contains a truncated
266 value. */
274 /* Record the luid of the last insn that invalidated memory
275 (anything that writes memory, and subroutine calls, but not pushes). */
279 /* Record the luid of the last CALL_INSN
280 so we can tell whether a potential combination crosses any calls. */
284 /* When `subst' is called, this is the insn that is being modified
285 (by combining in a previous insn). The PATTERN of this insn
286 is still the old pattern partially modified and it should not be
287 looked at, but this may be used to examine the successors of the insn
288 to judge whether a simplification is valid. */
292 /* This is the lowest LUID that `subst' is currently dealing with.
293 get_last_value will not return a value if the register was set at or
294 after this LUID. If not for this mechanism, we could get confused if
295 I2 or I1 in try_combine were an insn that used the old value of a register
296 to obtain a new value. In that case, we might erroneously get the
297 new value of the register when we wanted the old one. */
301 /* This contains any hard registers that are used in newpat; reg_dead_at_p
302 must consider all these registers to be always live. */
306 /* This is an insn to which a LOG_LINKS entry has been added. If this
307 insn is the earlier than I2 or I3, combine should rescan starting at
308 that location. */
312 /* Basic block in which we are performing combines. */
316 \f
317 /* Length of the currently allocated uid_insn_cost array. */
321 /* The following array records the insn_rtx_cost for every insn
322 in the instruction stream. */
326 /* The following array records the LOG_LINKS for every insn in the
327 instruction stream as struct insn_link pointers. */
333 };
337 #define INSN_COST(INSN) (uid_insn_cost[INSN_UID (INSN)])
338 #define LOG_LINKS(INSN) (uid_log_links[INSN_UID (INSN)])
340 #define FOR_EACH_LOG_LINK(L, INSN) \
341 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
343 /* Links for LOG_LINKS are allocated from this obstack. */
347 /* Allocate a link. */
351 {
359 }
361 /* Incremented for each basic block. */
365 /* Reset to label_tick for each extended basic block in scanning order. */
369 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
370 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
374 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
375 be safely used. It is zero while computing them and after combine has
376 completed. This former test prevents propagating values based on
377 previously set values, which can be incorrect if a variable is modified
378 in a loop. */
382 \f
383 /* Record one modification to rtl structure
384 to be undone by storing old_contents into *where. */
388 struct undo
389 {
394 };
396 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
397 num_undo says how many are currently recorded.
399 other_insn is nonzero if we have modified some other insn in the process
400 of working on subst_insn. It must be verified too. */
402 struct undobuf
403 {
407 };
411 /* Number of times the pseudo being substituted for
412 was found and replaced. */
417 machine_mode,
421 machine_mode,
493 \f
495 /* It is not safe to use ordinary gen_lowpart in combine.
496 See comments in gen_lowpart_for_combine. */
497 #undef RTL_HOOKS_GEN_LOWPART
498 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
500 /* Our implementation of gen_lowpart never emits a new pseudo. */
501 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
502 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
504 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
505 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
507 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
508 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
510 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
511 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
515 \f
516 /* Convenience wrapper for the canonicalize_comparison target hook.
517 Target hooks cannot use enum rtx_code. */
521 {
525 }
527 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
528 PATTERN can not be split. Otherwise, it returns an insn sequence.
529 This is a wrapper around split_insns which ensures that the
530 reg_stat vector is made larger if the splitter creates a new
531 register. */
535 {
544 }
546 /* This is used by find_single_use to locate an rtx in LOC that
547 contains exactly one use of DEST, which is typically either a REG
548 or CC0. It returns a pointer to the innermost rtx expression
549 containing DEST. Appearances of DEST that are being used to
550 totally replace it are not counted. */
554 {
563 {
567 CASE_CONST_ANY:
572 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
573 of a REG that occupies all of the REG, the insn uses DEST if
574 it is mentioned in the destination or the source. Otherwise, we
575 need just check the source. */
595 }
597 /* If it wasn't one of the common cases above, check each expression and
598 vector of this code. Look for a unique usage of DEST. */
602 {
604 {
609 else
615 /* Duplicate usage. */
617 }
619 {
623 {
629 else
636 }
637 }
638 }
641 }
644 /* See if DEST, produced in INSN, is used only a single time in the
645 sequel. If so, return a pointer to the innermost rtx expression in which
646 it is used.
648 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
650 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
651 care about REG_DEAD notes or LOG_LINKS.
653 Otherwise, we find the single use by finding an insn that has a
654 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
655 only referenced once in that insn, we know that it must be the first
656 and last insn referencing DEST. */
660 {
661 basic_block bb;
666 #ifdef HAVE_cc0
668 {
678 }
679 #endif
689 {
695 {
700 }
701 }
704 }
705 \f
706 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
707 insn. The substitution can be undone by undo_all. If INTO is already
708 set to NEWVAL, do not record this change. Because computing NEWVAL might
709 also call SUBST, we have to compute it before we put anything into
710 the undo table. */
712 static void
714 {
721 /* We'd like to catch as many invalid transformations here as
722 possible. Unfortunately, there are way too many mode changes
723 that are perfectly valid, so we'd waste too much effort for
724 little gain doing the checks here. Focus on catching invalid
725 transformations involving integer constants. */
728 {
729 /* Sanity check that we're replacing oldval with a CONST_INT
730 that is a valid sign-extension for the original mode. */
734 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
735 CONST_INT is not valid, because after the replacement, the
736 original mode would be gone. Unfortunately, we can't tell
737 when do_SUBST is called to replace the operand thereof, so we
738 perform this test on oldval instead, checking whether an
739 invalid replacement took place before we got here. */
744 }
748 else
757 }
759 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
761 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
762 for the value of a HOST_WIDE_INT value (including CONST_INT) is
763 not safe. */
765 static void
767 {
776 else
785 }
787 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
789 /* Similar to SUBST, but just substitute the mode. This is used when
790 changing the mode of a pseudo-register, so that any other
791 references to the entry in the regno_reg_rtx array will change as
792 well. */
794 static void
796 {
805 else
814 }
816 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
818 #ifndef HAVE_cc0
819 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
821 static void
823 {
832 else
841 }
843 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
844 #endif
845 \f
846 /* Subroutine of try_combine. Determine whether the replacement patterns
847 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
848 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
849 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
850 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
851 of all the instructions can be estimated and the replacements are more
852 expensive than the original sequence. */
854 static bool
857 {
862 /* Lookup the original insn_rtx_costs. */
867 {
870 {
874 }
875 else
876 {
880 }
881 }
882 else
883 {
886 }
888 /* Calculate the replacement insn_rtx_costs. */
891 {
895 }
896 else
897 {
900 }
903 {
909 {
912 }
913 else
915 }
917 /* Disallow this combination if both new_cost and old_cost are greater than
918 zero, and new_cost is greater than old cost. */
922 {
941 else
943 }
948 /* Update the uid_insn_cost array with the replacement costs. */
952 {
956 }
959 }
962 /* Delete any insns that copy a register to itself. */
964 static void
966 {
968 basic_block bb;
971 {
973 {
976 {
981 }
982 }
983 }
984 }
986 \f
987 /* Return false if we do not want to (or cannot) combine DEF. */
988 static bool
990 {
991 /* Do not consider if it is pre/post modification in MEM. */
997 /* Do not combine frame pointer adjustments. */
1000 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1003 #endif
1004 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1006 #endif
1007 )
1011 }
1013 /* Return false if we do not want to (or cannot) combine USE. */
1014 static bool
1016 {
1017 /* Do not consider the usage of the stack pointer by function call. */
1022 }
1024 /* Fill in log links field for all insns. */
1026 static void
1028 {
1029 basic_block bb;
1036 /* Pass through each block from the end, recording the uses of each
1037 register and establishing log links when def is encountered.
1038 Note that we do not clear next_use array in order to save time,
1039 so we have to test whether the use is in the same basic block as def.
1041 There are a few cases below when we do not consider the definition or
1042 usage -- these are taken from original flow.c did. Don't ask me why it is
1043 done this way; I don't know and if it works, I don't want to know. */
1046 {
1048 {
1052 /* Log links are created only once. */
1056 {
1072 /* flow.c claimed:
1074 We don't build a LOG_LINK for hard registers contained
1075 in ASM_OPERANDs. If these registers get replaced,
1076 we might wind up changing the semantics of the insn,
1077 even if reload can make what appear to be valid
1078 assignments later. */
1083 /* Don't add duplicate links between instructions. */
1092 }
1097 }
1098 }
1101 }
1103 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1104 true if we found a LOG_LINK that proves that A feeds B. This only works
1105 if there are no instructions between A and B which could have a link
1106 depending on A, since in that case we would not record a link for B.
1107 We also check the implicit dependency created by a cc0 setter/user
1108 pair. */
1110 static bool
1112 {
1117 #ifdef HAVE_cc0
1120 #endif
1122 }
1123 \f
1124 /* Main entry point for combiner. F is the first insn of the function.
1125 NREGS is the first unused pseudo-reg number.
1127 Return nonzero if the combiner has turned an indirect jump
1128 instruction into a direct jump. */
1129 static int
1131 {
1133 #ifdef HAVE_cc0
1135 #endif
1138 basic_block last_bb;
1158 /* Allocate array for insn info. */
1166 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1167 problems when, for example, we have j <<= 1 in a loop. */
1172 /* Scan all SETs and see if we can deduce anything about what
1173 bits are known to be zero for some registers and how many copies
1174 of the sign bit are known to exist for those registers.
1176 Also set any known values so that we can use it while searching
1177 for what bits are known to be set. */
1180 /* Allow the entry block and the first block to fall into the same EBB.
1181 Conceptually the incoming promotions are assigned to the entry block. */
1186 {
1191 label_tick++;
1199 {
1200 #ifdef AUTO_INC_DEC
1201 rtx links;
1202 #endif
1208 insn);
1211 #ifdef AUTO_INC_DEC
1215 insn);
1216 #endif
1218 /* Record the current insn_rtx_cost of this instruction. */
1221 optimize_this_for_speed_p);
1225 }
1226 }
1230 /* Now scan all the insns in forward order. */
1238 {
1244 label_tick++;
1254 {
1268 /* See if we know about function return values before this
1269 insn based upon SUBREG flags. */
1272 /* See if we can find hardregs and subreg of pseudos in
1273 narrower modes. This could help turning TRUNCATEs
1274 into SUBREGs. */
1277 /* Try this insn with each insn it links back to. */
1283 {
1286 }
1288 /* Try each sequence of three linked insns ending with this one. */
1292 {
1295 /* If the linked insn has been replaced by a note, then there
1296 is no point in pursuing this chain any further. */
1304 {
1307 }
1308 }
1310 #ifdef HAVE_cc0
1311 /* Try to combine a jump insn that uses CC0
1312 with a preceding insn that sets CC0, and maybe with its
1313 logical predecessor as well.
1314 This is how we make decrement-and-branch insns.
1315 We need this special code because data flow connections
1316 via CC0 do not get entered in LOG_LINKS. */
1322 {
1333 }
1335 /* Do the same for an insn that explicitly references CC0. */
1342 {
1353 }
1355 /* Finally, see if any of the insns that this insn links to
1356 explicitly references CC0. If so, try this insn, that insn,
1357 and its predecessor if it sets CC0. */
1369 #endif
1371 /* Try combining an insn with two different insns whose results it
1372 uses. */
1382 {
1385 }
1387 /* Try four-instruction combinations. */
1390 {
1394 /* If the linked insn has been replaced by a note, then there
1395 is no point in pursuing this chain any further. */
1400 {
1404 /* I0 -> I1 -> I2 -> I3. */
1410 {
1413 }
1414 /* I0, I1 -> I2, I2 -> I3. */
1421 {
1424 }
1425 }
1428 {
1432 /* I0 -> I2; I1, I2 -> I3. */
1438 {
1441 }
1442 /* I0 -> I1; I1, I2 -> I3. */
1448 {
1451 }
1452 }
1453 }
1455 /* Try this insn with each REG_EQUAL note it links back to. */
1457 {
1463 /* Avoid using a register that may already been marked
1464 dead by an earlier instruction. */
1469 {
1470 /* Temporarily replace the set's source with the
1471 contents of the REG_EQUAL note. The insn will
1472 be deleted or recognized by try_combine. */
1480 last_combined_insn);
1483 {
1486 }
1488 }
1489 }
1494 retry:
1495 ;
1496 }
1497 }
1504 /* Clean up. */
1510 {
1513 {
1516 }
1518 }
1528 /* Make recognizer allow volatile MEMs again. */
1532 }
1534 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1536 static void
1538 {
1544 }
1545 \f
1546 /* Set up any promoted values for incoming argument registers. */
1548 static void
1550 {
1551 tree arg;
1556 {
1561 /* Only continue if the incoming argument is in a register. */
1565 /* Determine, if possible, whether all call sites of the current
1566 function lie within the current compilation unit. (This does
1567 take into account the exporting of a function via taking its
1568 address, and so forth.) */
1571 /* The mode and signedness of the argument before any promotions happen
1572 (equal to the mode of the pseudo holding it at that stage). */
1576 /* The mode and signedness of the argument after any source language and
1577 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1581 /* The mode and signedness of the argument as it is actually passed,
1582 see assign_parm_setup_reg in function.c. */
1586 /* The mode of the register in which the argument is being passed. */
1589 /* Eliminate sign extensions in the callee when:
1590 (a) A mode promotion has occurred; */
1593 /* (b) The mode of the register is the same as the mode of
1594 the argument as it is passed; */
1597 /* (c) There's no language level extension; */
1599 ;
1600 /* (c.1) All callers are from the current compilation unit. If that's
1601 the case we don't have to rely on an ABI, we only have to know
1602 what we're generating right now, and we know that we will do the
1603 mode1 to mode2 promotion with the given sign. */
1606 /* (c.2) The combination of the two promotions is useful. This is
1607 true when the signs match, or if the first promotion is unsigned.
1608 In the later case, (sign_extend (zero_extend x)) is the same as
1609 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1615 /* Record that the value was promoted from mode1 to mode3,
1616 so that any sign extension at the head of the current
1617 function may be eliminated. */
1621 }
1622 }
1624 /* Called via note_stores. If X is a pseudo that is narrower than
1625 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1627 If we are setting only a portion of X and we can't figure out what
1628 portion, assume all bits will be used since we don't know what will
1629 be happening.
1631 Similarly, set how many bits of X are known to be copies of the sign bit
1632 at all locations in the function. This is the smallest number implied
1633 by any set of X. */
1635 static void
1637 {
1643 /* If this register is undefined at the start of the file, we can't
1644 say what its contents were. */
1645 && ! REGNO_REG_SET_P
1648 {
1652 {
1656 }
1658 /* If this register is being initialized using itself, and the
1659 register is uninitialized in this basic block, and there are
1660 no LOG_LINKS which set the register, then part of the
1661 register is uninitialized. In that case we can't assume
1662 anything about the number of nonzero bits.
1664 ??? We could do better if we checked this in
1665 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1666 could avoid making assumptions about the insn which initially
1667 sets the register, while still using the information in other
1668 insns. We would have to be careful to check every insn
1669 involved in the combination. */
1675 {
1682 {
1686 }
1687 }
1689 /* If this is a complex assignment, see if we can convert it into a
1690 simple assignment. */
1693 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1694 set what we know about X. */
1699 {
1702 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1703 /* If X is narrower than a word and SRC is a non-negative
1704 constant that would appear negative in the mode of X,
1705 sign-extend it for use in reg_stat[].nonzero_bits because some
1706 machines (maybe most) will actually do the sign-extension
1707 and this is the conservative approach.
1709 ??? For 2.5, try to tighten up the MD files in this regard
1710 instead of this kludge. */
1717 #endif
1719 /* Don't call nonzero_bits if it cannot change anything. */
1726 }
1727 else
1728 {
1731 }
1732 }
1733 }
1734 \f
1735 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1736 optionally insns that were previously combined into I3 or that will be
1737 combined into the merger of INSN and I3. The order is PRED, PRED2,
1738 INSN, SUCC, SUCC2, I3.
1740 Return 0 if the combination is not allowed for any reason.
1742 If the combination is allowed, *PDEST will be set to the single
1743 destination of INSN and *PSRC to the single source, and this function
1744 will return 1. */
1746 static int
1750 {
1755 #ifdef AUTO_INC_DEC
1756 rtx link;
1757 #endif
1762 {
1764 {
1769 }
1774 }
1778 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1779 or a PARALLEL consisting of such a SET and CLOBBERs.
1781 If INSN has CLOBBER parallel parts, ignore them for our processing.
1782 By definition, these happen during the execution of the insn. When it
1783 is merged with another insn, all bets are off. If they are, in fact,
1784 needed and aren't also supplied in I3, they may be added by
1785 recog_for_combine. Otherwise, it won't match.
1787 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1788 note.
1790 Get the source and destination of INSN. If more than one, can't
1791 combine. */
1797 {
1799 {
1803 {
1804 /* This is important to combine floating point insns
1805 for the SH4 port. */
1807 /* Combining an isolated USE doesn't make sense.
1808 We depend here on combinable_i3pat to reject them. */
1809 /* The code below this loop only verifies that the inputs of
1810 the SET in INSN do not change. We call reg_set_between_p
1811 to verify that the REG in the USE does not change between
1812 I3 and INSN.
1813 If the USE in INSN was for a pseudo register, the matching
1814 insn pattern will likely match any register; combining this
1815 with any other USE would only be safe if we knew that the
1816 used registers have identical values, or if there was
1817 something to tell them apart, e.g. different modes. For
1818 now, we forgo such complicated tests and simply disallow
1819 combining of USES of pseudo registers with any other USE. */
1822 {
1827 do
1828 {
1838 }
1840 }
1843 /* We can ignore CLOBBERs. */
1848 /* Ignore SETs whose result isn't used but not those that
1849 have side-effects. */
1855 /* If we have already found a SET, this is a second one and
1856 so we cannot combine with this insn. */
1864 /* Anything else means we can't combine. */
1866 }
1867 }
1870 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1871 so don't do anything with it. */
1874 }
1875 else
1881 /* The simplification in expand_field_assignment may call back to
1882 get_last_value, so set safe guard here. */
1888 /* Don't eliminate a store in the stack pointer. */
1890 /* Don't combine with an insn that sets a register to itself if it has
1891 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1893 /* Can't merge an ASM_OPERANDS. */
1895 /* Can't merge a function call. */
1897 /* Don't eliminate a function call argument. */
1903 /* Don't substitute into an incremented register. */
1907 /* Don't substitute into a non-local goto, this confuses CFG. */
1909 /* Make sure that DEST is not used after SUCC but before I3. */
1910 || (!all_adjacent
1911 && ((succ2
1915 /* Make sure that the value that is to be substituted for the register
1916 does not use any registers whose values alter in between. However,
1917 If the insns are adjacent, a use can't cross a set even though we
1918 think it might (this can happen for a sequence of insns each setting
1919 the same destination; last_set of that register might point to
1920 a NOTE). If INSN has a REG_EQUIV note, the register is always
1921 equivalent to the memory so the substitution is valid even if there
1922 are intervening stores. Also, don't move a volatile asm or
1923 UNSPEC_VOLATILE across any other insns. */
1924 || (! all_adjacent
1930 /* Don't combine across a CALL_INSN, because that would possibly
1931 change whether the life span of some REGs crosses calls or not,
1932 and it is a pain to update that information.
1933 Exception: if source is a constant, moving it later can't hurt.
1934 Accept that as a special case. */
1938 /* DEST must either be a REG or CC0. */
1940 {
1941 /* If register alignment is being enforced for multi-word items in all
1942 cases except for parameters, it is possible to have a register copy
1943 insn referencing a hard register that is not allowed to contain the
1944 mode being copied and which would not be valid as an operand of most
1945 insns. Eliminate this problem by not combining with such an insn.
1947 Also, on some machines we don't want to extend the life of a hard
1948 register. */
1953 /* Don't extend the life of a hard register unless it is
1954 user variable (if we have few registers) or it can't
1955 fit into the desired register (meaning something special
1956 is going on).
1957 Also avoid substituting a return register into I3, because
1958 reload can't handle a conflict with constraints of other
1959 inputs. */
1963 }
1971 {
1974 /* If the clobber represents an earlyclobber operand, we must not
1975 substitute an expression containing the clobbered register.
1976 As we do not analyze the constraint strings here, we have to
1977 make the conservative assumption. However, if the register is
1978 a fixed hard reg, the clobber cannot represent any operand;
1979 we leave it up to the machine description to either accept or
1980 reject use-and-clobber patterns. */
1986 }
1988 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1989 or not), reject, unless nothing volatile comes between it and I3 */
1992 {
1993 /* Make sure neither succ nor succ2 contains a volatile reference. */
1998 /* We'll check insns between INSN and I3 below. */
1999 }
2001 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2002 to be an explicit register variable, and was chosen for a reason. */
2008 /* If INSN contains volatile references (specifically volatile MEMs),
2009 we cannot combine across any other volatile references.
2010 Even if INSN doesn't contain volatile references, any intervening
2011 volatile insn might affect machine state. */
2014 ? volatile_refs_p
2021 /* If INSN contains an autoincrement or autodecrement, make sure that
2022 register is not used between there and I3, and not already used in
2023 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2024 Also insist that I3 not be a jump; if it were one
2025 and the incremented register were spilled, we would lose. */
2027 #ifdef AUTO_INC_DEC
2042 #endif
2044 #ifdef HAVE_cc0
2045 /* Don't combine an insn that follows a CC0-setting insn.
2046 An insn that uses CC0 must not be separated from the one that sets it.
2047 We do, however, allow I2 to follow a CC0-setting insn if that insn
2048 is passed as I1; in that case it will be deleted also.
2049 We also allow combining in this case if all the insns are adjacent
2050 because that would leave the two CC0 insns adjacent as well.
2051 It would be more logical to test whether CC0 occurs inside I1 or I2,
2052 but that would be much slower, and this ought to be equivalent. */
2058 #endif
2060 /* If we get here, we have passed all the tests and the combination is
2061 to be allowed. */
2067 }
2068 \f
2069 /* LOC is the location within I3 that contains its pattern or the component
2070 of a PARALLEL of the pattern. We validate that it is valid for combining.
2072 One problem is if I3 modifies its output, as opposed to replacing it
2073 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2074 doing so would produce an insn that is not equivalent to the original insns.
2076 Consider:
2078 (set (reg:DI 101) (reg:DI 100))
2079 (set (subreg:SI (reg:DI 101) 0) <foo>)
2081 This is NOT equivalent to:
2083 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2084 (set (reg:DI 101) (reg:DI 100))])
2086 Not only does this modify 100 (in which case it might still be valid
2087 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2089 We can also run into a problem if I2 sets a register that I1
2090 uses and I1 gets directly substituted into I3 (not via I2). In that
2091 case, we would be getting the wrong value of I2DEST into I3, so we
2092 must reject the combination. This case occurs when I2 and I1 both
2093 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2094 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2095 of a SET must prevent combination from occurring. The same situation
2096 can occur for I0, in which case I0_NOT_IN_SRC is set.
2098 Before doing the above check, we first try to expand a field assignment
2099 into a set of logical operations.
2101 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2102 we place a register that is both set and used within I3. If more than one
2103 such register is detected, we fail.
2105 Return 1 if the combination is valid, zero otherwise. */
2107 static int
2110 {
2114 {
2119 rtx subdest;
2126 /* Check for the case where I3 modifies its output, as discussed
2127 above. We don't want to prevent pseudos from being combined
2128 into the address of a MEM, so only prevent the combination if
2129 i1 or i2 set the same MEM. */
2139 /* This is the same test done in can_combine_p except we can't test
2140 all_adjacent; we don't have to, since this instruction will stay
2141 in place, thus we are not considering increasing the lifetime of
2142 INNER_DEST.
2144 Also, if this insn sets a function argument, combining it with
2145 something that might need a spill could clobber a previous
2146 function argument; the all_adjacent test in can_combine_p also
2147 checks this; here, we do a more specific test for this case. */
2157 /* If DEST is used in I3, it is being killed in this insn, so
2158 record that for later. We have to consider paradoxical
2159 subregs here, since they kill the whole register, but we
2160 ignore partial subregs, STRICT_LOW_PART, etc.
2161 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2162 STACK_POINTER_REGNUM, since these are always considered to be
2163 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2173 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2175 #endif
2176 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2179 #endif
2181 {
2186 }
2187 }
2190 {
2197 }
2200 }
2201 \f
2202 /* Return 1 if X is an arithmetic expression that contains a multiplication
2203 and division. We don't count multiplications by powers of two here. */
2205 static int
2207 {
2209 {
2225 }
2226 }
2227 \f
2228 /* Determine whether INSN can be used in a combination. Return nonzero if
2229 not. This is used in try_combine to detect early some cases where we
2230 can't perform combinations. */
2232 static int
2234 {
2235 rtx set;
2238 /* If this isn't really an insn, we can't do anything.
2239 This can occur when flow deletes an insn that it has merged into an
2240 auto-increment address. */
2244 /* Never combine loads and stores involving hard regs that are likely
2245 to be spilled. The register allocator can usually handle such
2246 reg-reg moves by tying. If we allow the combiner to make
2247 substitutions of likely-spilled regs, reload might die.
2248 As an exception, we allow combinations involving fixed regs; these are
2249 not available to the register allocator so there's no risk involved. */
2270 }
2272 struct likely_spilled_retval_info
2273 {
2276 };
2278 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2279 hard registers that are known to be written to / clobbered in full. */
2280 static void
2282 {
2299 else
2302 }
2304 /* Return nonzero iff part of the return value is live during INSN, and
2305 it is likely spilled. This can happen when more than one insn is needed
2306 to copy the return value, e.g. when we consider to combine into the
2307 second copy insn for a complex value. */
2309 static int
2311 {
2313 rtx reg;
2316 /* We assume here that no machine mode needs more than
2317 32 hard registers when the value overlaps with a register
2318 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2333 /* Disregard parts of the return value that are set later. */
2342 /* Check if any of the (probably) live return value registers is
2343 likely spilled. */
2344 nregs --;
2345 do
2346 {
2352 }
2354 /* Adjust INSN after we made a change to its destination.
2356 Changing the destination can invalidate notes that say something about
2357 the results of the insn and a LOG_LINK pointing to the insn. */
2359 static void
2361 {
2362 /* For notes, be conservative and simply remove them. */
2365 /* The new insn will have a destination that was previously the destination
2366 of an insn just above it. Call distribute_links to make a LOG_LINK from
2367 the next use of that destination. */
2383 }
2385 /* Return TRUE if combine can reuse reg X in mode MODE.
2386 ADDED_SETS is nonzero if the original set is still required. */
2387 static bool
2389 {
2396 /* Allow hard registers if the new mode is legal, and occupies no more
2397 registers than the old mode. */
2403 /* Or a pseudo that is only used once. */
2406 }
2409 /* Check whether X, the destination of a set, refers to part of
2410 the register specified by REG. */
2412 static bool
2414 {
2415 /* Check that reg is an integer mode register. */
2426 }
2428 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2429 Note that the INSN should be deleted *after* removing dead edges, so
2430 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2431 but not for a (set (pc) (label_ref FOO)). */
2433 static void
2435 {
2443 {
2448 /* Remove barriers from the footer if there are any. */
2451 {
2454 else
2458 }
2461 }
2462 }
2464 #ifndef HAVE_cc0
2465 /* Return whether INSN is a PARALLEL of exactly N register SETs followed
2466 by an arbitrary number of CLOBBERs. */
2467 static bool
2469 {
2489 }
2491 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2492 CLOBBERs), can be split into individual SETs in that order, without
2493 changing semantics. */
2494 static bool
2496 {
2504 {
2513 }
2516 }
2517 #endif
2519 /* Try to combine the insns I0, I1 and I2 into I3.
2520 Here I0, I1 and I2 appear earlier than I3.
2521 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2522 I3.
2524 If we are combining more than two insns and the resulting insn is not
2525 recognized, try splitting it into two insns. If that happens, I2 and I3
2526 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2527 Otherwise, I0, I1 and I2 are pseudo-deleted.
2529 Return 0 if the combination does not work. Then nothing is changed.
2530 If we did the combination, return the insn at which combine should
2531 resume scanning.
2533 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2534 new direct jump instruction.
2536 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2537 been I3 passed to an earlier try_combine within the same basic
2538 block. */
2543 {
2544 /* New patterns for I3 and I2, respectively. */
2548 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2549 dead. */
2551 /* Total number of SETs to put into I3. */
2553 /* Nonzero if I2's or I1's body now appears in I3. */
2555 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2557 /* Contains I3 if the destination of I3 is used in its source, which means
2558 that the old life of I3 is being killed. If that usage is placed into
2559 I2 and not in I3, a REG_DEAD note must be made. */
2561 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2563 /* Copy of SET_SRC of I1 and I0, if needed. */
2565 /* Set if I2DEST was reused as a scratch register. */
2567 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2569 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2574 /* Notes that must be added to REG_NOTES in I3 and I2. */
2576 /* Notes that we substituted I3 into I2 instead of the normal case. */
2578 /* Notes that I1, I2 or I3 is a MULT operation. */
2585 rtx temp_expr;
2588 rtx new_other_notes;
2591 /* Only try four-insn combinations when there's high likelihood of
2592 success. Look for simple insns, such as loads of constants or
2593 binary operations involving a constant. */
2595 {
2604 {
2607 rtx src;
2612 {
2615 }
2617 ngood++;
2620 nshift++;
2621 }
2624 }
2626 /* Exit early if one of the insns involved can't be used for
2627 combinations. */
2638 combine_attempts++;
2641 /* Reset the hard register usage information. */
2645 {
2652 else
2655 }
2657 /* If multiple insns feed into one of I2 or I3, they can be in any
2658 order. To simplify the code below, reorder them in sequence. */
2668 /* First check for one important special case that the code below will
2669 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2670 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2671 we may be able to replace that destination with the destination of I3.
2672 This occurs in the common code where we compute both a quotient and
2673 remainder into a structure, in which case we want to do the computation
2674 directly into the structure to avoid register-register copies.
2676 Note that this case handles both multiple sets in I2 and also cases
2677 where I2 has a number of CLOBBERs inside the PARALLEL.
2679 We make very conservative checks below and only try to handle the
2680 most common cases of this. For example, we only handle the case
2681 where I2 and I3 are adjacent to avoid making difficult register
2682 usage tests. */
2690 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2691 below would need to check what is inside (and reg_overlap_mentioned_p
2692 doesn't support those codes anyway). Don't allow those destinations;
2693 the resulting insn isn't likely to be recognized anyway. */
2699 {
2702 /* Make sure that the destination of I3,
2703 which we are going to substitute into one output of I2,
2704 is not used within another output of I2. We must avoid making this:
2705 (parallel [(set (mem (reg 69)) ...)
2706 (set (reg 69) ...)])
2707 which is not well-defined as to order of actions.
2708 (Besides, reload can't handle output reloads for this.)
2710 The problem can also happen if the dest of I3 is a memory ref,
2711 if another dest in I2 is an indirect memory ref. */
2723 {
2724 combine_merges++;
2734 /* Replace the dest in I2 with our dest and make the resulting
2735 insn the new pattern for I3. Then skip to where we validate
2736 the pattern. Everything was set up above. */
2741 }
2742 }
2744 /* If I2 is setting a pseudo to a constant and I3 is setting some
2745 sub-part of it to another constant, merge them by making a new
2746 constant. */
2753 {
2759 {
2762 {
2768 }
2769 }
2770 else
2771 {
2776 }
2779 {
2780 /* If this is the low part, we're done. */
2782 ;
2783 /* Handle the case where inner is twice the size of outer. */
2787 /* Otherwise give up for now. */
2788 else
2790 }
2793 {
2797 wide_int o
2802 combine_merges++;
2809 /* Replace the source in I2 with the new constant and make the
2810 resulting insn the new pattern for I3. Then skip to where we
2811 validate the pattern. Everything was set up above. */
2817 /* The dest of I3 has been replaced with the dest of I2. */
2820 }
2821 }
2823 #ifndef HAVE_cc0
2824 /* If we have no I1 and I2 looks like:
2825 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2826 (set Y OP)])
2827 make up a dummy I1 that is
2828 (set Y OP)
2829 and change I2 to be
2830 (set (reg:CC X) (compare:CC Y (const_int 0)))
2832 (We can ignore any trailing CLOBBERs.)
2834 This undoes a previous combination and allows us to match a branch-and-
2835 decrement insn. */
2847 {
2848 /* We make I1 with the same INSN_UID as I2. This gives it
2849 the same DF_INSN_LUID for value tracking. Our fake I1 will
2850 never appear in the insn stream so giving it the same INSN_UID
2851 as I2 will not cause a problem. */
2864 }
2866 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2867 make those two SETs separate I1 and I2 insns, and make an I0 that is
2868 the original I1. */
2874 {
2875 /* If there is no I1, there is no I0 either. */
2878 /* We make I1 with the same INSN_UID as I2. This gives it
2879 the same DF_INSN_LUID for value tracking. Our fake I1 will
2880 never appear in the insn stream so giving it the same INSN_UID
2881 as I2 will not cause a problem. */
2889 }
2890 #endif
2892 /* Verify that I2 and I1 are valid for combining. */
2898 {
2901 }
2903 /* Record whether I2DEST is used in I2SRC and similarly for the other
2904 cases. Knowing this will help in register status updating below. */
2915 /* For the earlier insns, determine which of the subsequent ones they
2916 feed. */
2923 /* Ensure that I3's pattern can be the destination of combines. */
2929 {
2932 }
2934 /* See if any of the insns is a MULT operation. Unless one is, we will
2935 reject a combination that is, since it must be slower. Be conservative
2936 here. */
2944 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2945 We used to do this EXCEPT in one case: I3 has a post-inc in an
2946 output operand. However, that exception can give rise to insns like
2947 mov r3,(r3)+
2948 which is a famous insn on the PDP-11 where the value of r3 used as the
2949 source was model-dependent. Avoid this sort of thing. */
2951 #if 0
2957 /* It's not the exception. */
2958 #endif
2959 #ifdef AUTO_INC_DEC
2960 {
2961 rtx link;
2967 {
2970 }
2971 }
2972 #endif
2974 /* See if the SETs in I1 or I2 need to be kept around in the merged
2975 instruction: whenever the value set there is still needed past I3.
2976 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
2978 For the SET in I1, we have two cases: if I1 and I2 independently feed
2979 into I3, the set in I1 needs to be kept around unless I1DEST dies
2980 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2981 in I1 needs to be kept around unless I1DEST dies or is set in either
2982 I2 or I3. The same considerations apply to I0. */
2989 else
2997 else
3000 /* We are about to copy insns for the case where they need to be kept
3001 around. Check that they can be copied in the merged instruction. */
3007 {
3010 }
3012 /* If the set in I2 needs to be kept around, we must make a copy of
3013 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3014 PATTERN (I2), we are only substituting for the original I1DEST, not into
3015 an already-substituted copy. This also prevents making self-referential
3016 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3017 I2DEST. */
3020 {
3023 else
3025 }
3028 {
3031 else
3033 }
3036 {
3039 else
3041 }
3043 combine_merges++;
3045 /* Substitute in the latest insn for the regs set by the earlier ones. */
3051 #ifndef HAVE_cc0
3052 /* Many machines that don't use CC0 have insns that can both perform an
3053 arithmetic operation and set the condition code. These operations will
3054 be represented as a PARALLEL with the first element of the vector
3055 being a COMPARE of an arithmetic operation with the constant zero.
3056 The second element of the vector will set some pseudo to the result
3057 of the same arithmetic operation. If we simplify the COMPARE, we won't
3058 match such a pattern and so will generate an extra insn. Here we test
3059 for this case, where both the comparison and the operation result are
3060 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3061 I2SRC. Later we will make the PARALLEL that contains I2. */
3067 {
3068 rtx newpat_dest;
3082 {
3087 }
3089 /* Do the rest only if op1 is const0_rtx, which may be the
3090 result of simplification. */
3092 {
3093 /* If a single use of the CC is found, prepare to modify it
3094 when SELECT_CC_MODE returns a new CC-class mode, or when
3095 the above simplify_compare_const() returned a new comparison
3096 operator. undobuf.other_insn is assigned the CC use insn
3097 when modifying it. */
3099 {
3100 #ifdef SELECT_CC_MODE
3101 machine_mode new_mode
3106 {
3111 else
3112 {
3115 }
3116 }
3117 #endif
3118 /* Cases for modifying the CC-using comparison. */
3120 /* ??? Do we need to verify the zero rtx? */
3122 {
3123 /* Replace cc_use_loc with entire new RTX. */
3128 }
3130 {
3131 /* Just replace the CC reg with a new mode. */
3134 }
3135 }
3137 /* Now we modify the current newpat:
3138 First, SET_DEST(newpat) is updated if the CC mode has been
3139 altered. For targets without SELECT_CC_MODE, this should be
3140 optimized away. */
3143 /* This is always done to propagate i2src into newpat. */
3146 /* Create new version of i2pat if needed; the below PARALLEL
3147 creation needs this to work correctly. */
3151 }
3152 }
3153 #endif
3156 {
3157 /* It is possible that the source of I2 or I1 may be performing
3158 an unneeded operation, such as a ZERO_EXTEND of something
3159 that is known to have the high part zero. Handle that case
3160 by letting subst look at the inner insns.
3162 Another way to do this would be to have a function that tries
3163 to simplify a single insn instead of merging two or more
3164 insns. We don't do this because of the potential of infinite
3165 loops and because of the potential extra memory required.
3166 However, doing it the way we are is a bit of a kludge and
3167 doesn't catch all cases.
3169 But only do this if -fexpensive-optimizations since it slows
3170 things down and doesn't usually win.
3172 This is not done in the COMPARE case above because the
3173 unmodified I2PAT is used in the PARALLEL and so a pattern
3174 with a modified I2SRC would not match. */
3177 {
3178 /* Pass pc_rtx so no substitutions are done, just
3179 simplifications. */
3181 {
3184 }
3188 }
3193 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3194 copy of I2SRC each time we substitute it, in order to avoid creating
3195 self-referential RTL when we will be substituting I1SRC for I1DEST
3196 later. Likewise if I0 feeds into I2, either directly or indirectly
3197 through I1, and I0DEST is in I0SRC. */
3204 /* Record whether I2's body now appears within I3's body. */
3206 }
3208 /* If we already got a failure, don't try to do more. Otherwise, try to
3209 substitute I1 if we have it. */
3212 {
3213 /* Check that an autoincrement side-effect on I1 has not been lost.
3214 This happens if I1DEST is mentioned in I2 and dies there, and
3215 has disappeared from the new pattern. */
3217 && i1_feeds_i2_n
3220 /* Before we can do this substitution, we must redo the test done
3221 above (see detailed comments there) that ensures I1DEST isn't
3222 mentioned in any SETs in NEWPAT that are field assignments. */
3225 {
3228 }
3233 /* If the following substitution will modify I1SRC, make a copy of it
3234 for the case where it is substituted for I1DEST in I2PAT later. */
3238 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3239 copy of I1SRC each time we substitute it, in order to avoid creating
3240 self-referential RTL when we will be substituting I0SRC for I0DEST
3241 later. */
3246 /* Record whether I1's body now appears within I3's body. */
3248 }
3250 /* Likewise for I0 if we have it. */
3253 {
3260 {
3263 }
3265 /* If the following substitution will modify I0SRC, make a copy of it
3266 for the case where it is substituted for I0DEST in I1PAT later. */
3269 /* And a copy for I0DEST in I2PAT substitution. */
3278 }
3280 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3281 to count all the ways that I2SRC and I1SRC can be used. */
3292 /* Fail if we tried to make a new register. */
3294 /* Fail if we couldn't do something and have a CLOBBER. */
3296 /* Fail if this new pattern is a MULT and we didn't have one before
3297 at the outer level. */
3300 {
3303 }
3305 /* If the actions of the earlier insns must be kept
3306 in addition to substituting them into the latest one,
3307 we must make a new PARALLEL for the latest insn
3308 to hold additional the SETs. */
3311 {
3313 combine_extras++;
3316 {
3322 }
3323 else
3324 {
3329 }
3335 {
3341 }
3343 {
3352 }
3353 }
3355 validate_replacement:
3357 /* Note which hard regs this insn has as inputs. */
3360 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3361 consider splitting this pattern, we might need these clobbers. */
3364 {
3370 }
3372 /* We have recognized nothing yet. */
3375 /* See if this is a PARALLEL of two SETs where one SET's destination is
3376 a register that is unused and this isn't marked as an instruction that
3377 might trap in an EH region. In that case, we just need the other SET.
3378 We prefer this over the PARALLEL.
3380 This can occur when simplifying a divmod insn. We *must* test for this
3381 case here because the code below that splits two independent SETs doesn't
3382 handle this case correctly when it updates the register status.
3384 It's pointless doing this if we originally had two sets, one from
3385 i3, and one from i2. Combining then splitting the parallel results
3386 in the original i2 again plus an invalid insn (which we delete).
3387 The net effect is only to move instructions around, which makes
3388 debug info less accurate. */
3396 {
3407 {
3410 }
3419 {
3425 }
3429 }
3431 /* Is the result of combination a valid instruction? */
3435 /* If we were combining three insns and the result is a simple SET
3436 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3437 insns. There are two ways to do this. It can be split using a
3438 machine-specific method (like when you have an addition of a large
3439 constant) or by combine in the function find_split_point. */
3443 {
3447 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3448 use I2DEST as a scratch register will help. In the latter case,
3449 convert I2DEST to the mode of the source of NEWPAT if we can. */
3453 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3454 inputs of NEWPAT. */
3456 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3457 possible to try that as a scratch reg. This would require adding
3458 more code to make it work though. */
3461 {
3464 /* First try to split using the original register as a
3465 scratch register. */
3469 i2dest)));
3472 /* If that didn't work, try changing the mode of I2DEST if
3473 we can. */
3478 {
3480 rtx ni2dest;
3484 else
3485 {
3488 }
3490 parallel = (gen_rtx_PARALLEL
3494 ni2dest))));
3499 {
3507 }
3508 }
3511 }
3513 /* If recog_for_combine has discarded clobbers, try to use them
3514 again for the split. */
3516 {
3519 }
3522 {
3527 }
3531 {
3541 /* If I2 or I3 has multiple SETs, we won't know how to track
3542 register status, so don't use these insns. If I2's destination
3543 is used between I2 and I3, we also can't use these insns. */
3553 /* It is possible that both insns now set the destination of I3.
3554 If so, we must show an extra use of it. */
3557 {
3575 }
3576 }
3578 /* If we can split it and use I2DEST, go ahead and see if that
3579 helps things be recognized. Verify that none of the registers
3580 are set between I2 and I3. */
3583 #ifdef HAVE_cc0
3585 #endif
3586 /* We need I2DEST in the proper mode. If it is a hard register
3587 or the only use of a pseudo, we can change its mode.
3588 Make sure we don't change a hard register to have a mode that
3589 isn't valid for it, or change the number of registers. */
3596 /* We can't overwrite I2DEST if its value is still used by
3597 NEWPAT. */
3599 {
3608 /* *SPLIT may be part of I2SRC, so make sure we have the
3609 original expression around for later debug processing.
3610 We should not need I2SRC any more in other cases. */
3613 else
3616 /* Get NEWDEST as a register in the proper mode. We have already
3617 validated that we can do this. */
3619 {
3622 else
3623 {
3626 }
3627 }
3629 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3630 an ASHIFT. This can occur if it was inside a PLUS and hence
3631 appeared to be a memory address. This is a kludge. */
3636 {
3639 /* Update split_code because we may not have a multiply
3640 anymore. */
3642 }
3644 #ifdef INSN_SCHEDULING
3645 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3646 be written as a ZERO_EXTEND. */
3648 {
3649 #ifdef LOAD_EXTEND_OP
3650 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3651 what it really is. */
3656 else
3657 #endif
3660 }
3661 #endif
3663 /* Attempt to split binary operators using arithmetic identities. */
3667 {
3674 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3676 {
3681 }
3682 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3689 {
3695 /* Split both "((X op Y) op X) op Y" and
3696 "((X op Y) op Y) op X" as "T op T" where T is
3697 "X op Y". */
3700 {
3706 }
3707 /* Split "((X op X) op Y) op Y)" as "T op T" where
3708 T is "X op Y". */
3710 {
3716 }
3717 }
3718 }
3721 {
3724 }
3728 /* recog_for_combine might have added CLOBBERs to newi2pat.
3729 Make sure NEWPAT does not depend on the clobbered regs. */
3733 {
3736 {
3739 }
3740 }
3742 /* If the split point was a MULT and we didn't have one before,
3743 don't use one now. */
3746 }
3747 }
3749 /* Check for a case where we loaded from memory in a narrow mode and
3750 then sign extended it, but we need both registers. In that case,
3751 we have a PARALLEL with both loads from the same memory location.
3752 We can split this into a load from memory followed by a register-register
3753 copy. This saves at least one insn, more if register allocation can
3754 eliminate the copy.
3756 We cannot do this if the destination of the first assignment is a
3757 condition code register or cc0. We eliminate this case by making sure
3758 the SET_DEST and SET_SRC have the same mode.
3760 We cannot do this if the destination of the second assignment is
3761 a register that we have already assumed is zero-extended. Similarly
3762 for a SUBREG of such a register. */
3797 {
3798 rtx ni2dest;
3812 }
3814 /* Similarly, check for a case where we have a PARALLEL of two independent
3815 SETs but we started with three insns. In this case, we can do the sets
3816 as two separate insns. This case occurs when some SET allows two
3817 other insns to combine, but the destination of that SET is still live.
3819 Also do this if we started with two insns and (at least) one of the
3820 resulting sets is a noop; this noop will be deleted later. */
3839 {
3843 /* Normally, it doesn't matter which of the two is done first,
3844 but the one that references cc0 can't be the second, and
3845 one which uses any regs/memory set in between i2 and i3 can't
3846 be first. The PARALLEL might also have been pre-existing in i3,
3847 so we need to make sure that we won't wrongly hoist a SET to i2
3848 that would conflict with a death note present in there. */
3855 #ifdef HAVE_cc0
3857 #endif
3858 /* If I3 is a jump, ensure that set0 is a jump so that
3859 we do not create invalid RTL. */
3861 )
3862 {
3865 }
3872 #ifdef HAVE_cc0
3874 #endif
3875 /* If I3 is a jump, ensure that set1 is a jump so that
3876 we do not create invalid RTL. */
3878 )
3879 {
3882 }
3883 else
3884 {
3887 }
3892 {
3893 /* recog_for_combine might have added CLOBBERs to newi2pat.
3894 Make sure NEWPAT does not depend on the clobbered regs. */
3896 {
3899 {
3902 {
3905 }
3906 }
3907 }
3910 }
3911 }
3913 /* If it still isn't recognized, fail and change things back the way they
3914 were. */
3916 /* Is the result a reasonable ASM_OPERANDS? */
3918 {
3921 }
3923 /* If we had to change another insn, make sure it is valid also. */
3925 {
3933 {
3936 }
3937 }
3939 #ifdef HAVE_cc0
3940 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3941 they are adjacent to each other or not. */
3942 {
3946 {
3949 }
3950 }
3951 #endif
3953 /* Only allow this combination if insn_rtx_costs reports that the
3954 replacement instructions are cheaper than the originals. */
3956 {
3959 }
3962 {
3967 {
3972 /* Temporarily revert mode back. */
3976 {
3977 /* If we used i2dest as a scratch register with a
3978 different mode, substitute it for the original
3979 i2src while its original mode is temporarily
3980 restored, and then clear i2scratch so that we don't
3981 do it again later. */
3983 this_basic_block);
3985 /* Put back the new mode. */
3987 }
3988 else
3989 {
3994 {
3997 }
3998 else
3999 {
4006 }
4008 /* We're dealing with a reg that changed mode but not
4009 meaning, so we want to turn it into a subreg for
4010 the new mode. However, because of REG sharing and
4011 because its mode had already changed, we have to do
4012 it in two steps. First, replace any debug uses of
4013 reg, with its original mode temporarily restored,
4014 with this copy we have created; then, replace the
4015 copy with the SUBREG of the original shared reg,
4016 once again changed to the new mode. */
4018 this_basic_block);
4022 this_basic_block);
4023 }
4024 }
4025 }
4027 /* If we will be able to accept this, we have made a
4028 change to the destination of I3. This requires us to
4029 do a few adjustments. */
4032 {
4035 }
4037 /* We now know that we can do this combination. Merge the insns and
4038 update the status of registers and LOG_LINKS. */
4041 {
4046 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4047 ensure that they are still valid. Then add any non-duplicate
4048 notes added by recog_for_combine. */
4050 {
4060 }
4064 NULL_RTX);
4065 }
4068 {
4071 rtx ni2dest;
4073 /* I3 now uses what used to be its destination and which is now
4074 I2's destination. This requires us to do a few adjustments. */
4078 /* We need a LOG_LINK from I3 to I2. But we used to have one,
4079 so we still will.
4081 However, some later insn might be using I2's dest and have
4082 a LOG_LINK pointing at I3. We must remove this link.
4083 The simplest way to remove the link is to point it at I1,
4084 which we know will be a NOTE. */
4086 /* newi2pat is usually a SET here; however, recog_for_combine might
4087 have added some clobbers. */
4090 else
4097 {
4099 {
4105 }
4106 }
4107 }
4109 {
4114 /* Compute which registers we expect to eliminate. newi2pat may be setting
4115 either i3dest or i2dest, so we must check it. Also, i1dest may be the
4116 same as i3dest, in which case newi2pat may be setting i1dest. */
4119 || !i2dest_killed
4123 || !i1dest_killed
4127 || !i0dest_killed
4130 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4131 clear them. */
4139 /* Ensure that we do not have something that should not be shared but
4140 occurs multiple times in the new insns. Check this by first
4141 resetting all the `used' flags and then copying anything is shared. */
4165 {
4172 {
4173 /* I2SRC must still be meaningful at this point. Some splitting
4174 operations can invalidate I2SRC, but those operations do not
4175 apply to calls. */
4178 }
4186 }
4191 /* We had one special case above where I2 had more than one set and
4192 we replaced a destination of one of those sets with the destination
4193 of I3. In that case, we have to update LOG_LINKS of insns later
4194 in this basic block. Note that this (expensive) case is rare.
4196 Also, in this case, we must pretend that all REG_NOTEs for I2
4197 actually came from I3, so that REG_UNUSED notes from I2 will be
4198 properly handled. */
4201 {
4210 temp_insn
4220 {
4225 }
4226 else
4229 }
4237 {
4240 this_basic_block);
4243 }
4244 else
4245 {
4248 this_basic_block);
4250 }
4253 {
4258 this_basic_block);
4260 }
4263 {
4268 this_basic_block);
4270 }
4272 /* Get death notes for everything that is now used in either I3 or
4273 I2 and used to die in a previous insn. If we built two new
4274 patterns, move from I1 to I2 then I2 to I3 so that we get the
4275 proper movement on registers that I2 modifies. */
4281 else
4287 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4304 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4305 know these are REG_UNUSED and want them to go to the desired insn,
4306 so we always pass it as i3. */
4310 NULL_RTX);
4314 NULL_RTX);
4316 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4317 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4318 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4319 in that case, it might delete I2. Similarly for I2 and I1.
4320 Show an additional death due to the REG_DEAD note we make here. If
4321 we discard it in distribute_notes, we will decrement it again. */
4324 {
4329 else
4332 }
4335 {
4340 else
4343 }
4346 {
4351 else
4354 }
4357 {
4362 else
4365 }
4373 {
4378 /* The insn that used to set this register doesn't exist, and
4379 this life of the register may not exist either. See if one of
4380 I3's links points to an insn that sets I2DEST. If it does,
4381 that is now the last known value for I2DEST. If we don't update
4382 this and I2 set the register to a value that depended on its old
4383 contents, we will get confused. If this insn is used, thing
4384 will be set correctly in combine_instructions. */
4392 /* If the reg formerly set in I2 died only once and that was in I3,
4393 zero its use count so it won't make `reload' do any work. */
4398 }
4401 {
4415 }
4418 {
4432 }
4434 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4435 been made to this insn. The order is important, because newi2pat
4436 can affect nonzero_bits of newpat. */
4440 }
4443 {
4445 {
4448 }
4450 }
4453 {
4455 {
4458 }
4460 }
4463 {
4465 {
4468 }
4470 }
4473 {
4475 {
4478 }
4480 }
4483 {
4485 {
4488 }
4490 }
4492 /* Set new_direct_jump_p if a new return or simple jump instruction
4493 has been created. Adjust the CFG accordingly. */
4495 {
4499 }
4504 {
4507 }
4509 /* A noop might also need cleaning up of CFG, if it comes from the
4510 simplification of a jump. */
4515 {
4518 }
4525 {
4528 }
4530 combine_successes++;
4537 else
4539 }
4540 \f
4541 /* Undo all the modifications recorded in undobuf. */
4543 static void
4545 {
4549 {
4552 {
4567 }
4571 }
4574 }
4576 /* We've committed to accepting the changes we made. Move all
4577 of the undos to the free list. */
4579 static void
4581 {
4585 {
4589 }
4591 }
4592 \f
4593 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4594 where we have an arithmetic expression and return that point. LOC will
4595 be inside INSN.
4597 try_combine will call this function to see if an insn can be split into
4598 two insns. */
4602 {
4611 /* First special-case some codes. */
4613 {
4615 #ifdef INSN_SCHEDULING
4616 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4617 point. */
4620 #endif
4624 #ifdef HAVE_lo_sum
4625 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4626 using LO_SUM and HIGH. */
4629 {
4637 }
4638 #endif
4640 /* If we have a PLUS whose second operand is a constant and the
4641 address is not valid, perhaps will can split it up using
4642 the machine-specific way to split large constants. We use
4643 the first pseudo-reg (one of the virtual regs) as a placeholder;
4644 it will not remain in the result. */
4649 {
4653 subst_insn);
4655 /* This should have produced two insns, each of which sets our
4656 placeholder. If the source of the second is a valid address,
4657 we can make put both sources together and make a split point
4658 in the middle. */
4671 && memory_address_addr_space_p
4674 {
4678 /* Replace the placeholder in SRC2 with SRC1. If we can
4679 find where in SRC2 it was placed, that can become our
4680 split point and we can replace this address with SRC2.
4681 Just try two obvious places. */
4692 {
4695 }
4696 }
4698 /* If that didn't work, perhaps the first operand is complex and
4699 needs to be computed separately, so make a split point there.
4700 This will occur on machines that just support REG + CONST
4701 and have a constant moved through some previous computation. */
4707 }
4709 /* If we have a PLUS whose first operand is complex, try computing it
4710 separately by making a split there. */
4721 #ifdef HAVE_cc0
4722 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4723 ZERO_EXTRACT, the most likely reason why this doesn't match is that
4724 we need to put the operand into a register. So split at that
4725 point. */
4734 #endif
4736 /* See if we can split SET_SRC as it stands. */
4741 /* See if we can split SET_DEST as it stands. */
4746 /* See if this is a bitfield assignment with everything constant. If
4747 so, this is an IOR of an AND, so split it into that. */
4757 {
4763 unsigned HOST_WIDE_INT mask
4765 rtx or_mask;
4774 else
4775 {
4781 or_mask));
4782 }
4789 }
4791 /* Otherwise, see if this is an operation that we can split into two.
4792 If so, try to split that. */
4796 {
4798 /* If we are AND'ing with a large constant that is only a single
4799 bit and the result is only being used in a context where we
4800 need to know if it is zero or nonzero, replace it with a bit
4801 extraction. This will avoid the large constant, which might
4802 have taken more than one insn to make. If the constant were
4803 not a valid argument to the AND but took only one insn to make,
4804 this is no worse, but if it took more than one insn, it will
4805 be better. */
4815 {
4820 {
4823 }
4824 }
4828 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4829 is known to be on, this can be converted into a NEG of a shift. */
4835 {
4847 }
4853 /* We can't optimize if either mode is a partial integer
4854 mode as we don't know how many bits are significant
4855 in those modes. */
4869 {
4877 }
4882 }
4886 {
4889 /* For unsigned, we have a choice of a shift followed by an
4890 AND or two shifts. Use two shifts for field sizes where the
4891 constant might be too large. We assume here that we can
4892 always at least get 8-bit constants in an AND insn, which is
4893 true for every current RISC. */
4896 {
4897 unsigned HOST_WIDE_INT mask
4901 gen_rtx_LSHIFTRT
4909 }
4910 else
4911 {
4913 gen_rtx_fmt_ee
4924 }
4925 }
4927 /* See if this is a simple operation with a constant as the second
4928 operand. It might be that this constant is out of range and hence
4929 could be used as a split point. */
4937 /* Finally, see if this is a simple operation with its first operand
4938 not in a register. The operation might require this operand in a
4939 register, so return it as a split point. We can always do this
4940 because if the first operand were another operation, we would have
4941 already found it as a split point. */
4950 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4951 it is better to write this as (not (ior A B)) so we can split it.
4952 Similarly for IOR. */
4954 {
4962 }
4964 /* Many RISC machines have a large set of logical insns. If the
4965 second operand is a NOT, put it first so we will try to split the
4966 other operand first. */
4968 {
4972 }
4977 /* Canonicalization can produce (minus A (mult B C)), where C is a
4978 constant. It may be better to try splitting (plus (mult B -C) A)
4979 instead if this isn't a multiply by a power of two. */
4983 {
4991 mode)),
4994 }
4996 /* Split at a multiply-accumulate instruction. However if this is
4997 the SET_SRC, we likely do not have such an instruction and it's
4998 worthless to try this split. */
5004 }
5006 /* Otherwise, select our actions depending on our rtx class. */
5008 {
5014 /* ... fall through ... */
5022 /* ... fall through ... */
5024 /* Some machines have (and (shift ...) ...) insns. If X is not
5025 an AND, but XEXP (X, 0) is, use it as our split point. */
5035 /* Otherwise, we don't have a split point. */
5037 }
5038 }
5039 \f
5040 /* Throughout X, replace FROM with TO, and return the result.
5041 The result is TO if X is FROM;
5042 otherwise the result is X, but its contents may have been modified.
5043 If they were modified, a record was made in undobuf so that
5044 undo_all will (among other things) return X to its original state.
5046 If the number of changes necessary is too much to record to undo,
5047 the excess changes are not made, so the result is invalid.
5048 The changes already made can still be undone.
5049 undobuf.num_undo is incremented for such changes, so by testing that
5050 the caller can tell whether the result is valid.
5052 `n_occurrences' is incremented each time FROM is replaced.
5054 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5056 IN_COND is nonzero if we are at the top level of a condition.
5058 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5059 by copying if `n_occurrences' is nonzero. */
5061 static rtx
5063 {
5068 rtx new_rtx;
5070 /* Two expressions are equal if they are identical copies of a shared
5071 RTX or if they are both registers with the same register number
5072 and mode. */
5074 #define COMBINE_RTX_EQUAL_P(X,Y) \
5075 ((X) == (Y) \
5076 || (REG_P (X) && REG_P (Y) \
5077 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5079 /* Do not substitute into clobbers of regs -- this will never result in
5080 valid RTL. */
5085 {
5086 n_occurrences++;
5088 }
5090 /* If X and FROM are the same register but different modes, they
5091 will not have been seen as equal above. However, the log links code
5092 will make a LOG_LINKS entry for that case. If we do nothing, we
5093 will try to rerecognize our original insn and, when it succeeds,
5094 we will delete the feeding insn, which is incorrect.
5096 So force this insn not to match in this (rare) case. */
5101 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5102 of which may contain things that can be combined. */
5106 /* It is possible to have a subexpression appear twice in the insn.
5107 Suppose that FROM is a register that appears within TO.
5108 Then, after that subexpression has been scanned once by `subst',
5109 the second time it is scanned, TO may be found. If we were
5110 to scan TO here, we would find FROM within it and create a
5111 self-referent rtl structure which is completely wrong. */
5115 /* Parallel asm_operands need special attention because all of the
5116 inputs are shared across the arms. Furthermore, unsharing the
5117 rtl results in recognition failures. Failure to handle this case
5118 specially can result in circular rtl.
5120 Solve this by doing a normal pass across the first entry of the
5121 parallel, and only processing the SET_DESTs of the subsequent
5122 entries. Ug. */
5127 {
5130 /* If this substitution failed, this whole thing fails. */
5138 {
5144 {
5147 /* If this substitution failed, this whole thing fails. */
5153 }
5154 }
5155 }
5156 else
5157 {
5161 /* We don't need to process a SET_DEST that is a register, CC0,
5162 or PC, so set up to skip this common case. All other cases
5163 where we want to suppress replacing something inside a
5164 SET_SRC are handled via the IN_DEST operand. */
5171 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5172 constant. */
5177 {
5179 {
5182 {
5184 {
5187 n_occurrences++;
5188 }
5189 else
5190 {
5192 unique_copy);
5194 /* If this substitution failed, this whole thing
5195 fails. */
5199 }
5202 }
5203 }
5205 {
5206 /* If this is a register being set, ignore it. */
5213 ;
5216 {
5217 /* In general, don't install a subreg involving two
5218 modes not tieable. It can worsen register
5219 allocation, and can even make invalid reload
5220 insns, since the reg inside may need to be copied
5221 from in the outside mode, and that may be invalid
5222 if it is an fp reg copied in integer mode.
5224 We allow two exceptions to this: It is valid if
5225 it is inside another SUBREG and the mode of that
5226 SUBREG and the mode of the inside of TO is
5227 tieable and it is valid if X is a SET that copies
5228 FROM to CC0. */
5236 #ifdef HAVE_cc0
5238 #endif
5239 )
5251 n_occurrences++;
5252 }
5253 else
5254 /* If we are in a SET_DEST, suppress most cases unless we
5255 have gone inside a MEM, in which case we want to
5256 simplify the address. We assume here that things that
5257 are actually part of the destination have their inner
5258 parts in the first expression. This is true for SUBREG,
5259 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5260 things aside from REG and MEM that should appear in a
5261 SET_DEST. */
5263 (((in_dest
5269 unique_copy);
5271 /* If we found that we will have to reject this combination,
5272 indicate that by returning the CLOBBER ourselves, rather than
5273 an expression containing it. This will speed things up as
5274 well as prevent accidents where two CLOBBERs are considered
5275 to be equal, thus producing an incorrect simplification. */
5281 {
5289 }
5292 {
5296 }
5297 else
5299 }
5300 }
5301 }
5303 /* Check if we are loading something from the constant pool via float
5304 extension; in this case we would undo compress_float_constant
5305 optimization and degenerate constant load to an immediate value. */
5309 {
5313 }
5315 /* Try to simplify X. If the simplification changed the code, it is likely
5316 that further simplification will help, so loop, but limit the number
5317 of repetitions that will be performed. */
5320 {
5321 /* If X is sufficiently simple, don't bother trying to do anything
5322 with it. */
5331 /* We no longer know the original mode of operand 0 since we
5332 have changed the form of X) */
5334 }
5337 }
5338 \f
5339 /* Simplify X, a piece of RTL. We just operate on the expression at the
5340 outer level; call `subst' to simplify recursively. Return the new
5341 expression.
5343 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5344 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5345 of a condition. */
5347 static rtx
5350 {
5353 rtx temp;
5356 /* If this is a commutative operation, put a constant last and a complex
5357 expression first. We don't need to do this for comparisons here. */
5360 {
5364 }
5366 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5367 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5368 things. Check for cases where both arms are testing the same
5369 condition.
5371 Don't do anything if all operands are very simple. */
5384 {
5389 /* If everything is a comparison, what we have is highly unlikely
5390 to be simpler, so don't use it. */
5393 {
5400 /* Simplify the alternative arms; this may collapse the true and
5401 false arms to store-flag values. Be careful to use copy_rtx
5402 here since true_rtx or false_rtx might share RTL with x as a
5403 result of the if_then_else_cond call above. */
5407 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5408 is unlikely to be simpler. */
5411 {
5414 /* Restarting if we generate a store-flag expression will cause
5415 us to loop. Just drop through in this case. */
5417 /* If the result values are STORE_FLAG_VALUE and zero, we can
5418 just make the comparison operation. */
5429 /* Likewise, we can make the negate of a comparison operation
5430 if the result values are - STORE_FLAG_VALUE and zero. */
5438 mode);
5449 mode);
5450 else
5453 mode,
5454 VOIDmode,
5455 cond,
5456 cop1),
5461 }
5462 }
5463 }
5465 /* Try to fold this expression in case we have constants that weren't
5466 present before. */
5469 {
5477 {
5480 {
5484 }
5487 }
5500 }
5503 {
5508 }
5510 /* First see if we can apply the inverse distributive law. */
5513 {
5517 }
5519 /* If CODE is an associative operation not otherwise handled, see if we
5520 can associate some operands. This can win if they are constants or
5521 if they are logically related (i.e. (a & b) & a). */
5527 {
5529 {
5533 rtx inner;
5535 /* Make sure we pass the constant operand if any as the second
5536 one if this is a commutative operation. */
5538 {
5542 }
5548 /* For commutative operations, try the other pair if that one
5549 didn't simplify. */
5551 {
5556 }
5560 }
5561 }
5563 /* A little bit of algebraic simplification here. */
5565 {
5567 /* Ensure that our address has any ASHIFTs converted to MULT in case
5568 address-recognizing predicates are called later. */
5577 /* See if this can be moved to simplify_subreg. */
5580 /* Don't call gen_lowpart if the inner mode
5581 is VOIDmode and we cannot simplify it, as SUBREG without
5582 inner mode is invalid. */
5589 {
5590 rtx temp;
5596 /* If op is known to have all lower bits zero, the result is zero. */
5606 }
5608 /* Don't change the mode of the MEM if that would change the meaning
5609 of the address. */
5616 /* Note that we cannot do any narrowing for non-constants since
5617 we might have been counting on using the fact that some bits were
5618 zero. We now do this in the SET. */
5625 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5626 replaced by (lshiftrt X C). This will convert
5627 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5635 /* If X has only a single bit that might be nonzero, say, bit I, convert
5636 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5637 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5638 (sign_extract X 1 Y). But only do this if TEMP isn't a register
5639 or a SUBREG of one since we'd be making the expression more
5640 complex if it was just a register. */
5646 {
5647 rtx temp1 = simplify_shift_const
5653 /* If all we did was surround TEMP with the two shifts, we
5654 haven't improved anything, so don't use it. Otherwise,
5655 we are better off with TEMP1. */
5660 }
5664 /* We can't handle truncation to a partial integer mode here
5665 because we don't know the real bitsize of the partial
5666 integer mode. */
5675 /* We can truncate a constant value and return it. */
5679 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5680 whose value is a comparison can be replaced with a subreg if
5681 STORE_FLAG_VALUE permits. */
5690 /* (const (const X)) can become (const X). Do it this way rather than
5691 returning the inner CONST since CONST can be shared with a
5692 REG_EQUAL note. */
5697 #ifdef HAVE_lo_sum
5699 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
5700 can add in an offset. find_split_point will split this address up
5701 again if it doesn't match. */
5706 #endif
5709 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5710 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5711 bit-field and can be replaced by either a sign_extend or a
5712 sign_extract. The `and' may be a zero_extend and the two
5713 <c>, -<c> constants may be reversed. */
5728 return simplify_shift_const
5735 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5736 can become (ashiftrt (ashift (xor x 1) C) C) where C is
5737 the bitsize of the mode - 1. This allows simplification of
5738 "a = (b & 8) == 0;" */
5750 /* If we are adding two things that have no bits in common, convert
5751 the addition into an IOR. This will often be further simplified,
5752 for example in cases like ((a & 1) + (a & 2)), which can
5753 become a & 3. */
5758 {
5759 /* Try to simplify the expression further. */
5763 /* If we could, great. If not, do not go ahead with the IOR
5764 replacement, since PLUS appears in many special purpose
5765 address arithmetic instructions. */
5773 }
5777 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5778 (and <foo> (const_int pow2-1)) */
5788 /* If we have (mult (plus A B) C), apply the distributive law and then
5789 the inverse distributive law to see if things simplify. This
5790 occurs mostly in addresses, often when unrolling loops. */
5793 {
5797 }
5799 /* Try simplify a*(b/c) as (a*b)/c. */
5802 {
5808 }
5812 /* If this is a divide by a power of two, treat it as a shift if
5813 its first operand is a shift. */
5831 /* If the first operand is a condition code, we can't do anything
5832 with it. */
5836 {
5844 /* Simplify our comparison, if possible. */
5847 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5848 if only the low-order bit is possibly nonzero in X (such as when
5849 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
5850 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
5851 known to be either 0 or -1, NE becomes a NEG and EQ becomes
5852 (plus X 1).
5854 Remove any ZERO_EXTRACT we made when thinking this was a
5855 comparison. It may now be simpler to use, e.g., an AND. If a
5856 ZERO_EXTRACT is indeed appropriate, it will be placed back by
5857 the call to make_compound_operation in the SET case.
5859 Don't apply these optimizations if the caller would
5860 prefer a comparison rather than a value.
5861 E.g., for the condition in an IF_THEN_ELSE most targets need
5862 an explicit comparison. */
5865 ;
5881 {
5885 mode);
5886 }
5893 {
5897 const1_rtx);
5898 }
5906 {
5909 }
5911 /* If STORE_FLAG_VALUE is -1, we have cases similar to
5912 those above. */
5914 ;
5930 {
5934 mode);
5935 }
5943 {
5947 mode);
5948 }
5950 /* If X is 0/1, (eq X 0) is X-1. */
5956 {
5959 }
5961 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5962 one bit that might be nonzero, we can convert (ne x 0) to
5963 (ashift x c) where C puts the bit in the sign bit. Remove any
5964 AND with STORE_FLAG_VALUE when we are done, since we are only
5965 going to test the sign bit. */
5972 {
5978 else
5980 }
5982 /* If the code changed, return a whole new comparison.
5983 We also need to avoid using SUBST in cases where
5984 simplify_comparison has widened a comparison with a CONST_INT,
5985 since in that case the wider CONST_INT may fail the sanity
5986 checks in do_SUBST. */
5993 /* Otherwise, keep this operation, but maybe change its operands.
5994 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
5997 }
6007 /* If we are processing SET_DEST, we are done. */
6025 /* If this is a shift by a constant amount, simplify it. */
6041 }
6044 }
6045 \f
6046 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6048 static rtx
6050 {
6057 rtx temp;
6060 rtx reversed;
6062 /* Simplify storing of the truth value. */
6067 /* Also when the truth value has to be reversed. */
6073 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6074 in it is being compared against certain values. Get the true and false
6075 comparisons and see if that says anything about the value of each arm. */
6081 {
6082 HOST_WIDE_INT nzb;
6088 /* If FALSE_CODE is EQ, swap the codes and arms. */
6091 {
6094 }
6096 /* If we are comparing against zero and the expression being tested has
6097 only a single bit that might be nonzero, that is its value when it is
6098 not equal to zero. Similarly if it is known to be -1 or 0. */
6102 {
6105 }
6109 {
6112 }
6114 /* Now simplify an arm if we know the value of the register in the
6115 branch and it is used in the arm. Be careful due to the potential
6116 of locally-shared RTL. */
6133 }
6135 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6136 reversed, do so to avoid needing two sets of patterns for
6137 subtract-and-branch insns. Similarly if we have a constant in the true
6138 arm, the false arm is the same as the first operand of the comparison, or
6139 the false arm is more complicated than the true arm. */
6152 {
6161 /* It is possible that the conditional has been simplified out. */
6164 }
6166 /* If the two arms are identical, we don't need the comparison. */
6171 /* Convert a == b ? b : a to "a". */
6183 /* Look for cases where we have (abs x) or (neg (abs X)). */
6186 && comparison_p
6193 {
6199 return
6202 mode);
6205 }
6207 /* Look for MIN or MAX. */
6210 && comparison_p
6215 {
6230 }
6232 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6233 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6234 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6235 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6236 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6237 neither 1 or -1, but it isn't worth checking for. */
6240 && comparison_p
6243 {
6259 /* If an identity-zero op is commutative, check whether there
6260 would be a match if we swapped the operands. */
6280 {
6284 }
6296 {
6300 }
6316 {
6320 }
6332 {
6336 }
6339 {
6345 const_true_rtx));
6353 }
6354 }
6356 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6357 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6358 negation of a single bit, we can convert this operation to a shift. We
6359 can actually do this more generally, but it doesn't seem worth it. */
6368 return
6372 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
6382 }
6383 \f
6384 /* Simplify X, a SET expression. Return the new expression. */
6386 static rtx
6388 {
6391 machine_mode mode
6396 /* (set (pc) (return)) gets written as (return). */
6400 /* Now that we know for sure which bits of SRC we are using, see if we can
6401 simplify the expression for the object knowing that we only need the
6402 low-order bits. */
6405 {
6408 }
6410 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6411 the comparison result and try to simplify it unless we already have used
6412 undobuf.other_insn. */
6420 {
6429 {
6432 {
6435 }
6436 }
6437 else
6445 {
6449 }
6450 else
6451 {
6456 /* Attempt to simplify CC user. */
6458 {
6462 }
6464 /* Convert X into a no-op move. */
6468 }
6470 /* Simplify our comparison, if possible. */
6473 #ifdef SELECT_CC_MODE
6474 /* If this machine has CC modes other than CCmode, check to see if we
6475 need to use a different CC mode here. */
6484 else
6487 #ifndef HAVE_cc0
6488 /* If the mode changed, we have to change SET_DEST, the mode in the
6489 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6490 a hard register, just build new versions with the proper mode. If it
6491 is a pseudo, we lose unless it is only time we set the pseudo, in
6492 which case we can safely change its mode. */
6494 {
6496 {
6498 rtx new_dest;
6502 else
6503 {
6506 }
6513 }
6514 }
6518 /* If the code changed, we have to build a new comparison in
6519 undobuf.other_insn. */
6521 {
6530 /* If the only change we made was to change an EQ into an NE or
6531 vice versa, OP0 has only one bit that might be nonzero, and OP1
6532 is zero, check if changing the user of the condition code will
6533 produce a valid insn. If it won't, we can keep the original code
6534 in that insn by surrounding our operation with an XOR. */
6541 {
6546 {
6553 }
6554 }
6555 }
6560 /* Otherwise, if we didn't previously have a COMPARE in the
6561 correct mode, we need one. */
6563 {
6566 }
6568 {
6571 }
6572 /* Otherwise, update the COMPARE if needed. */
6574 {
6577 }
6578 }
6579 else
6580 {
6581 /* Get SET_SRC in a form where we have placed back any
6582 compound expressions. Then do the checks below. */
6585 }
6587 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6588 and X being a REG or (subreg (reg)), we may be able to convert this to
6589 (set (subreg:m2 x) (op)).
6591 We can always do this if M1 is narrower than M2 because that means that
6592 we only care about the low bits of the result.
6594 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6595 perform a narrower operation than requested since the high-order bits will
6596 be undefined. On machine where it is defined, this transformation is safe
6597 as long as M1 and M2 have the same number of words. */
6605 #ifndef WORD_REGISTER_OPERATIONS
6608 #endif
6609 #ifdef CANNOT_CHANGE_MODE_CLASS
6614 #endif
6618 {
6621 dest));
6625 }
6627 #ifdef HAVE_cc0
6628 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6629 in SRC. */
6635 {
6639 /* Here we make sure that we don't have a sign bit on. */
6642 {
6645 }
6646 }
6647 #endif
6649 #ifdef LOAD_EXTEND_OP
6650 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6651 would require a paradoxical subreg. Replace the subreg with a
6652 zero_extend to avoid the reload that would otherwise be required. */
6660 {
6666 }
6667 #endif
6669 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6670 are comparing an item known to be 0 or -1 against 0, use a logical
6671 operation instead. Check for one of the arms being an IOR of the other
6672 arm with some value. We compute three terms to be IOR'ed together. In
6673 practice, at most two will be nonzero. Then we do the IOR's. */
6681 #ifdef HAVE_conditional_move
6683 #endif
6688 {
6714 false_rtx);
6720 term3));
6723 }
6725 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6726 whole thing fail. */
6731 else
6732 /* Convert this into a field assignment operation, if possible. */
6734 }
6735 \f
6736 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6737 result. */
6739 static rtx
6741 {
6747 {
6749 /* We can call simplify_and_const_int only if we don't lose
6750 any (sign) bits when converting INTVAL (op1) to
6751 "unsigned HOST_WIDE_INT". */
6755 {
6762 }
6764 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6765 apply the distributive law and then the inverse distributive
6766 law to see if things simplify. */
6768 {
6772 }
6774 {
6778 }
6782 /* If we have (ior (and A B) C), apply the distributive law and then
6783 the inverse distributive law to see if things simplify. */
6786 {
6790 }
6793 {
6797 }
6802 }
6805 }
6806 \f
6807 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6808 operations" because they can be replaced with two more basic operations.
6809 ZERO_EXTEND is also considered "compound" because it can be replaced with
6810 an AND operation, which is simpler, though only one operation.
6812 The function expand_compound_operation is called with an rtx expression
6813 and will convert it to the appropriate shifts and AND operations,
6814 simplifying at each stage.
6816 The function make_compound_operation is called to convert an expression
6817 consisting of shifts and ANDs into the equivalent compound expression.
6818 It is the inverse of this function, loosely speaking. */
6820 static rtx
6822 {
6826 rtx tem;
6829 {
6833 /* We can't necessarily use a const_int for a multiword mode;
6834 it depends on implicitly extending the value.
6835 Since we don't know the right way to extend it,
6836 we can't tell whether the implicit way is right.
6838 Even for a mode that is no wider than a const_int,
6839 we can't win, because we need to sign extend one of its bits through
6840 the rest of it, and we don't know which bit. */
6844 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6845 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
6846 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6847 reloaded. If not for that, MEM's would very rarely be safe.
6849 Reject MODEs bigger than a word, because we might not be able
6850 to reference a two-register group starting with an arbitrary register
6851 (and currently gen_lowpart might crash for a SUBREG). */
6856 /* Reject MODEs that aren't scalar integers because turning vector
6857 or complex modes into shifts causes problems. */
6863 /* If the inner object has VOIDmode (the only way this can happen
6864 is if it is an ASM_OPERANDS), we can't do anything since we don't
6865 know how much masking to do. */
6874 /* ... fall through ... */
6877 /* If the operand is a CLOBBER, just return it. */
6886 /* Reject MODEs that aren't scalar integers because turning vector
6887 or complex modes into shifts causes problems. */
6895 /* This should stay within the object being extracted, fail otherwise. */
6906 }
6907 /* Convert sign extension to zero extension, if we know that the high
6908 bit is not set, as this is easier to optimize. It will be converted
6909 back to cheaper alternative in make_extraction. */
6917 {
6921 /* Make sure this is a profitable operation. */
6928 else
6930 }
6932 /* We can optimize some special cases of ZERO_EXTEND. */
6934 {
6935 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6936 know that the last value didn't have any inappropriate bits
6937 set. */
6945 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6954 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6955 is a comparison and STORE_FLAG_VALUE permits. This is like
6956 the first case, but it works even when GET_MODE (x) is larger
6957 than HOST_WIDE_INT. */
6966 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
6976 }
6978 /* If we reach here, we want to return a pair of shifts. The inner
6979 shift is a left shift of BITSIZE - POS - LEN bits. The outer
6980 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
6981 logical depending on the value of UNSIGNEDP.
6983 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6984 converted into an AND of a shift.
6986 We must check for the case where the left shift would have a negative
6987 count. This can happen in a case like (x >> 31) & 255 on machines
6988 that can't shift by a constant. On those machines, we would first
6989 combine the shift with the AND to produce a variable-position
6990 extraction. Then the constant of 31 would be substituted in
6991 to produce such a position. */
6995 {
7004 }
7011 else
7012 /* Any other cases we can't handle. */
7015 /* If we couldn't do this for some reason, return the original
7016 expression. */
7021 }
7022 \f
7023 /* X is a SET which contains an assignment of one object into
7024 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7025 or certain SUBREGS). If possible, convert it into a series of
7026 logical operations.
7028 We half-heartedly support variable positions, but do not at all
7029 support variable lengths. */
7031 static const_rtx
7033 {
7034 rtx inner;
7038 machine_mode compute_mode;
7040 /* Loop until we find something we can't simplify. */
7042 {
7045 {
7049 }
7052 {
7057 /* A constant position should stay within the width of INNER. */
7063 {
7071 /* If position is ADJUST - X, new position is X. */
7073 else
7074 {
7079 pos);
7080 }
7081 }
7082 }
7084 /* A SUBREG between two modes that occupy the same numbers of words
7085 can be done by moving the SUBREG to the source. */
7087 /* We need SUBREGs to compute nonzero_bits properly. */
7088 && nonzero_sign_valid
7093 {
7095 gen_lowpart
7099 }
7100 else
7108 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7110 {
7111 machine_mode imode;
7113 /* Don't do anything for vector or complex integral types. */
7117 /* Try to find an integral mode to pun with. */
7124 }
7126 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7130 /* Now compute the equivalent expression. Make a copy of INNER
7131 for the SET_DEST in case it is a MEM into which we will substitute;
7132 we don't want shared RTL in that case. */
7134 compute_mode);
7138 compute_mode,
7140 compute_mode),
7141 inner);
7146 mask),
7147 pos);
7152 }
7155 }
7156 \f
7157 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7158 it is an RTX that represents the (variable) starting position; otherwise,
7159 POS is the (constant) starting bit position. Both are counted from the LSB.
7161 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7163 IN_DEST is nonzero if this is a reference in the destination of a SET.
7164 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7165 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7166 be used.
7168 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7169 ZERO_EXTRACT should be built even for bits starting at bit 0.
7171 MODE is the desired mode of the result (if IN_DEST == 0).
7173 The result is an RTX for the extraction or NULL_RTX if the target
7174 can't handle it. */
7176 static rtx
7180 {
7181 /* This mode describes the size of the storage area
7182 to fetch the overall value from. Within that, we
7183 ignore the POS lowest bits, etc. */
7185 machine_mode inner_mode;
7186 machine_mode wanted_inner_mode;
7193 HOST_WIDE_INT orig_pos;
7199 {
7200 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7201 consider just the QI as the memory to extract from.
7202 The subreg adds or removes high bits; its mode is
7203 irrelevant to the meaning of this extraction,
7204 since POS and LEN count from the lsb. */
7208 }
7213 {
7214 /* We're extracting the least significant bits of an rtx
7215 (ashift X (const_int C)), where LEN > C. Extract the
7216 least significant (LEN - C) bits of X, giving an rtx
7217 whose mode is MODE, then shift it left C times. */
7223 }
7229 /* See if this can be done without an extraction. We never can if the
7230 width of the field is not the same as that of some integer mode. For
7231 registers, we can only avoid the extraction if the position is at the
7232 low-order bit and this is either not in the destination or we have the
7233 appropriate STRICT_LOW_PART operation available.
7235 For MEM, we can avoid an extract if the field starts on an appropriate
7236 boundary and we can change the mode of the memory reference. */
7245 && (! in_dest
7249 && (pos
7252 /* We can't do this if we are widening INNER_MODE (it
7253 may not be aligned, for one thing). */
7259 {
7260 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7261 field. If the original and current mode are the same, we need not
7262 adjust the offset. Otherwise, we do if bytes big endian.
7264 If INNER is not a MEM, get a piece consisting of just the field
7265 of interest (in this case POS % BITS_PER_WORD must be 0). */
7268 {
7269 HOST_WIDE_INT offset;
7271 /* POS counts from lsb, but make OFFSET count in memory order. */
7274 else
7278 }
7280 {
7282 {
7283 /* We can't call gen_lowpart in a DEST since we
7284 always want a SUBREG (see below) and it would sometimes
7285 return a new hard register. */
7287 {
7302 /* Avoid creating invalid subregs, for example when
7303 simplifying (x>>32)&255. */
7308 }
7309 else
7311 }
7312 else
7314 }
7315 else
7317 len >= HOST_BITS_PER_WIDE_INT
7322 /* If this extraction is going into the destination of a SET,
7323 make a STRICT_LOW_PART unless we made a MEM. */
7338 /* If we know that no extraneous bits are set, and that the high
7339 bit is not set, convert the extraction to the cheaper of
7340 sign and zero extension, that are equivalent in these cases. */
7346 {
7350 /* Prefer ZERO_EXTENSION, since it gives more information to
7351 backends. */
7356 }
7358 /* Otherwise, sign- or zero-extend unless we already are in the
7359 proper mode. */
7363 }
7365 /* Unless this is a COMPARE or we have a funny memory reference,
7366 don't do anything with zero-extending field extracts starting at
7367 the low-order bit since they are simple AND operations. */
7372 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7373 if the position is not a constant and the length is not 1. In all
7374 other cases, we would only be going outside our object in cases when
7375 an original shift would have been undefined. */
7384 /* If INNER is not from memory, we want it to have the mode of a register
7385 extraction pattern's structure operand, or word_mode if there is no
7386 such pattern. The same applies to extraction_mode and pos_mode
7387 and their respective operands.
7389 For memory, assume that the desired extraction_mode and pos_mode
7390 are the same as for a register operation, since at present we don't
7391 have named patterns for aligned memory structures. */
7395 {
7399 }
7401 /* Never narrow an object, since that might not be safe. */
7409 else
7410 {
7411 /* Be careful not to go beyond the extracted object and maintain the
7412 natural alignment of the memory. */
7416 {
7419 }
7420 }
7425 {
7426 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7427 BITS_BIG_ENDIAN style. If position is constant, compute new
7428 position. Otherwise, build subtraction.
7429 Note that POS is relative to the mode of the original argument.
7430 If it's a MEM we need to recompute POS relative to that.
7431 However, if we're extracting from (or inserting into) a register,
7432 we want to recompute POS relative to wanted_inner_mode. */
7439 else
7440 pos_rtx
7443 pos_rtx);
7444 /* POS may be less than 0 now, but we check for that below.
7445 Note that it can only be less than 0 if !MEM_P (inner). */
7446 }
7448 /* If INNER has a wider mode, and this is a constant extraction, try to
7449 make it smaller and adjust the byte to point to the byte containing
7450 the value. */
7453 && ! pos_rtx
7458 {
7461 /* The computations below will be correct if the machine is big
7462 endian in both bits and bytes or little endian in bits and bytes.
7463 If it is mixed, we must adjust. */
7465 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7466 adjust OFFSET to compensate. */
7471 /* We can now move to the desired byte. */
7482 }
7484 /* If INNER is not memory, get it into the proper mode. If we are changing
7485 its mode, POS must be a constant and smaller than the size of the new
7486 mode. */
7488 {
7489 /* On the LHS, don't create paradoxical subregs implicitely truncating
7490 the register unless TRULY_NOOP_TRUNCATION. */
7493 wanted_inner_mode))
7505 pos_rtx
7511 }
7513 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7514 have to zero extend. Otherwise, we can just use a SUBREG. */
7517 {
7521 /* If we know that no extraneous bits are set, and that the high
7522 bit is not set, convert extraction to cheaper one - either
7523 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7524 cases. */
7532 {
7536 /* Prefer ZERO_EXTENSION, since it gives more information to
7537 backends. */
7541 }
7543 }
7545 /* Make POS_RTX unless we already have it and it is correct. If we don't
7546 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7547 be a CONST_INT. */
7554 /* Make the required operation. See if we can use existing rtx. */
7561 }
7562 \f
7563 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7564 with any other operations in X. Return X without that shift if so. */
7566 static rtx
7568 {
7571 rtx tem;
7574 {
7576 /* This is the shift itself. If it is wide enough, we will return
7577 either the value being shifted if the shift count is equal to
7578 COUNT or a shift for the difference. */
7592 /* If we can safely shift this constant and we find the inner shift,
7593 make a new operation. */
7598 {
7602 }
7607 }
7610 }
7611 \f
7612 /* Look at the expression rooted at X. Look for expressions
7613 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7614 Form these expressions.
7616 Return the new rtx, usually just X.
7618 Also, for machines like the VAX that don't have logical shift insns,
7619 try to convert logical to arithmetic shift operations in cases where
7620 they are equivalent. This undoes the canonicalizations to logical
7621 shifts done elsewhere.
7623 We try, as much as possible, to re-use rtl expressions to save memory.
7625 IN_CODE says what kind of expression we are processing. Normally, it is
7626 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
7627 being kludges), it is MEM. When processing the arguments of a comparison
7628 or a COMPARE against zero, it is COMPARE. */
7630 rtx
7632 {
7640 rtx tem;
7643 /* Select the code to be used in recursive calls. Once we are inside an
7644 address, we stay there. If we have a comparison, set to COMPARE,
7645 but once inside, go back to our default of SET. */
7654 /* Process depending on the code of this operation. If NEW is set
7655 nonzero, it will be returned. */
7658 {
7660 /* Convert shifts by constants into multiplications if inside
7661 an address. */
7666 {
7672 {
7675 }
7678 }
7688 {
7692 }
7695 {
7699 mode));
7701 }
7702 else
7703 {
7707 }
7718 {
7722 }
7725 {
7729 mode));
7731 }
7732 else
7733 {
7737 }
7741 /* If the second operand is not a constant, we can't do anything
7742 with it. */
7746 /* If the constant is a power of two minus one and the first operand
7747 is a logical right shift, make an extraction. */
7750 {
7754 }
7756 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
7761 {
7763 next_code);
7767 }
7768 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
7774 {
7775 /* Apply the distributive law, and then try to make extractions. */
7782 }
7784 /* If we are have (and (rotate X C) M) and C is larger than the number
7785 of bits in M, this is an extraction. */
7791 {
7797 }
7799 /* On machines without logical shifts, if the operand of the AND is
7800 a logical shift and our mask turns off all the propagated sign
7801 bits, we can replace the logical shift with an arithmetic shift. */
7809 {
7816 make_compound_operation
7819 }
7821 /* If the constant is one less than a power of two, this might be
7822 representable by an extraction even if no shift is present.
7823 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7824 we are in a COMPARE. */
7828 next_code),
7831 /* If we are in a comparison and this is an AND with a power of two,
7832 convert this into the appropriate bit extract. */
7837 next_code),
7843 /* If the sign bit is known to be zero, replace this with an
7844 arithmetic shift. */
7849 {
7852 next_code),
7855 }
7857 /* ... fall through ... */
7863 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7864 this is a SIGN_EXTRACT. */
7871 {
7878 }
7880 /* See if we have operations between an ASHIFTRT and an ASHIFT.
7881 If so, try to merge the shifts into a SIGN_EXTEND. We could
7882 also do this for some cases of SIGN_EXTRACT, but it doesn't
7883 seem worth the effort; the case checked for occurs on Alpha. */
7899 /* Call ourselves recursively on the inner expression. If we are
7900 narrowing the object and it has a different RTL code from
7901 what it originally did, do this SUBREG as a force_to_mode. */
7902 {
7906 /* If in_code is COMPARE, it isn't always safe to pass it through
7907 to the recursive make_compound_operation call. */
7911 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
7912 is (const_int 0), rather than
7913 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0). */
7923 simplified
7931 {
7932 rtx newer
7935 /* If we have something other than a SUBREG, we might have
7936 done an expansion, so rerun ourselves. */
7940 /* force_to_mode can expand compounds. If it just re-expanded the
7941 compound, use gen_lowpart to convert to the desired mode. */
7943 /* Likewise if it re-expanded the compound only partially.
7944 This happens for SUBREG of ZERO_EXTRACT if they extract
7945 the same number of bits. */
7954 }
7958 }
7963 }
7966 {
7969 }
7971 /* Now recursively process each operand of this operation. We need to
7972 handle ZERO_EXTEND specially so that we don't lose track of the
7973 inner mode. */
7975 {
7983 }
7988 {
7991 }
7994 {
7997 }
7999 maybe_swap:
8000 /* If this is a commutative operation, the changes to the operands
8001 may have made it noncanonical. */
8004 {
8008 }
8011 }
8012 \f
8013 /* Given M see if it is a value that would select a field of bits
8014 within an item, but not the entire word. Return -1 if not.
8015 Otherwise, return the starting position of the field, where 0 is the
8016 low-order bit.
8018 *PLEN is set to the length of the field. */
8020 static int
8022 {
8023 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8028 /* Now shift off the low-order zero bits and see if we have a
8029 power of two minus 1. */
8037 }
8038 \f
8039 /* If X refers to a register that equals REG in value, replace these
8040 references with REG. */
8041 static rtx
8043 {
8051 {
8087 {
8091 else
8093 }
8095 /* fall through */
8102 {
8105 {
8107 {
8110 }
8112 }
8113 }
8115 {
8118 {
8121 {
8123 {
8126 }
8128 }
8129 }
8130 }
8133 }
8136 }
8138 /* Return X converted to MODE. If the value is already truncated to
8139 MODE we can just return a subreg even though in the general case we
8140 would need an explicit truncation. */
8142 static rtx
8144 {
8149 {
8150 /* Bit-cast X into an integer mode. */
8155 }
8158 }
8160 /* See if X can be simplified knowing that we will only refer to it in
8161 MODE and will only refer to those bits that are nonzero in MASK.
8162 If other bits are being computed or if masking operations are done
8163 that select a superset of the bits in MASK, they can sometimes be
8164 ignored.
8166 Return a possibly simplified expression, but always convert X to
8167 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8169 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8170 are all off in X. This is used when X will be complemented, by either
8171 NOT, NEG, or XOR. */
8173 static rtx
8176 {
8179 machine_mode op_mode;
8183 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8184 code below will do the wrong thing since the mode of such an
8185 expression is VOIDmode.
8187 Also do nothing if X is a CLOBBER; this can happen if X was
8188 the return value from a call to gen_lowpart. */
8192 /* We want to perform the operation in its present mode unless we know
8193 that the operation is valid in MODE, in which case we do the operation
8194 in MODE. */
8199 /* It is not valid to do a right-shift in a narrower mode
8200 than the one it came in with. */
8205 /* Truncate MASK to fit OP_MODE. */
8209 /* When we have an arithmetic operation, or a shift whose count we
8210 do not know, we need to assume that all bits up to the highest-order
8211 bit in MASK will be needed. This is how we form such a mask. */
8214 else
8218 /* Determine what bits of X are guaranteed to be (non)zero. */
8221 /* If none of the bits in X are needed, return a zero. */
8225 /* If X is a CONST_INT, return a new one. Do this here since the
8226 test below will fail. */
8228 {
8231 else
8232 {
8235 }
8236 }
8238 /* If X is narrower than MODE and we want all the bits in X's mode, just
8239 get X in the proper mode. */
8244 /* We can ignore the effect of a SUBREG if it narrows the mode or
8245 if the constant masks to zero all the bits the mode doesn't have. */
8255 /* The arithmetic simplifications here only work for scalar integer modes. */
8260 {
8262 /* If X is a (clobber (const_int)), return it since we know we are
8263 generating something that won't match. */
8276 /* Similarly for a truncate. */
8280 /* If this is an AND with a constant, convert it into an AND
8281 whose constant is the AND of that constant with MASK. If it
8282 remains an AND of MASK, delete it since it is redundant. */
8285 {
8289 /* If X is still an AND, see if it is an AND with a mask that
8290 is just some low-order bits. If so, and it is MASK, we don't
8291 need it. */
8298 /* If it remains an AND, try making another AND with the bits
8299 in the mode mask that aren't in MASK turned on. If the
8300 constant in the AND is wide enough, this might make a
8301 cheaper constant. */
8306 {
8307 unsigned HOST_WIDE_INT cval
8310 rtx y;
8317 }
8320 }
8325 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8326 low-order bits (as in an alignment operation) and FOO is already
8327 aligned to that boundary, mask C1 to that boundary as well.
8328 This may eliminate that PLUS and, later, the AND. */
8330 {
8334 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8335 number, sign extend it. */
8348 }
8350 /* ... fall through ... */
8353 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8354 most significant bit in MASK since carries from those bits will
8355 affect the bits we are interested in. */
8360 /* If X is (minus C Y) where C's least set bit is larger than any bit
8361 in the mask, then we may replace with (neg Y). */
8364 {
8368 }
8370 /* Similarly, if C contains every bit in the fuller_mask, then we may
8371 replace with (not Y). */
8374 {
8378 }
8385 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8386 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8387 operation which may be a bitfield extraction. Ensure that the
8388 constant we form is not wider than the mode of X. */
8400 {
8409 }
8411 binop:
8412 /* For most binary operations, just propagate into the operation and
8413 change the mode if we have an operation of that mode. */
8418 /* If we ended up truncating both operands, truncate the result of the
8419 operation instead. */
8422 {
8425 }
8435 /* For left shifts, do the same, but just for the first operand.
8436 However, we cannot do anything with shifts where we cannot
8437 guarantee that the counts are smaller than the size of the mode
8438 because such a count will have a different meaning in a
8439 wider mode. */
8449 /* If the shift count is a constant and we can do arithmetic in
8450 the mode of the shift, refine which bits we need. Otherwise, use the
8451 conservative form of the mask. */
8457 else
8469 /* Here we can only do something if the shift count is a constant,
8470 this shift constant is valid for the host, and we can do arithmetic
8471 in OP_MODE. */
8477 {
8481 /* Select the mask of the bits we need for the shift operand. */
8484 /* We can only change the mode of the shift if we can do arithmetic
8485 in the mode of the shift and INNER_MASK is no wider than the
8486 width of X's mode. */
8494 }
8496 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8497 shift and AND produces only copies of the sign bit (C2 is one less
8498 than a power of two), we can do this with just a shift. */
8502 /* The shift puts one of the sign bit copies in the least significant
8503 bit. */
8508 /* Number of bits left after the shift must be more than the mask
8509 needs. */
8512 /* Must be more sign bit copies than the mask needs. */
8522 /* If we are just looking for the sign bit, we don't need this shift at
8523 all, even if it has a variable count. */
8527 /* If this is a shift by a constant, get a mask that contains those bits
8528 that are not copies of the sign bit. We then have two cases: If
8529 MASK only includes those bits, this can be a logical shift, which may
8530 allow simplifications. If MASK is a single-bit field not within
8531 those bits, we are requesting a copy of the sign bit and hence can
8532 shift the sign bit to the appropriate location. */
8536 {
8539 /* If the considered data is wider than HOST_WIDE_INT, we can't
8540 represent a mask for all its bits in a single scalar.
8541 But we only care about the lower bits, so calculate these. */
8544 {
8547 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8548 is the number of bits a full-width mask would have set.
8549 We need only shift if these are fewer than nonzero can
8550 hold. If not, we must keep all bits set in nonzero. */
8555 + HOST_BITS_PER_WIDE_INT
8557 }
8558 else
8559 {
8562 }
8565 {
8570 }
8573 {
8574 x = simplify_shift_const
8580 }
8581 }
8583 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
8584 even if the shift count isn't a constant. */
8589 shiftrt:
8591 /* If this is a zero- or sign-extension operation that just affects bits
8592 we don't care about, remove it. Be sure the call above returned
8593 something that is still a shift. */
8603 next_select);
8609 /* If the shift count is constant and we can do computations
8610 in the mode of X, compute where the bits we care about are.
8611 Otherwise, we can't do anything. Don't change the mode of
8612 the shift or propagate MODE into the shift, though. */
8615 {
8625 }
8629 /* If we just want the low-order bit, the NEG isn't needed since it
8630 won't change the low-order bit. */
8634 /* We need any bits less significant than the most significant bit in
8635 MASK since carries from those bits will affect the bits we are
8636 interested in. */
8641 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8642 same as the XOR case above. Ensure that the constant we form is not
8643 wider than the mode of X. */
8651 {
8660 }
8662 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8663 use the full mask inside the NOT. */
8666 unop:
8669 next_select));
8675 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8676 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8677 which is equal to STORE_FLAG_VALUE. */
8689 /* We have no way of knowing if the IF_THEN_ELSE can itself be
8690 written in a narrower mode. We play it safe and do not do so. */
8706 }
8708 /* Ensure we return a value of the proper mode. */
8710 }
8711 \f
8712 /* Return nonzero if X is an expression that has one of two values depending on
8713 whether some other value is zero or nonzero. In that case, we return the
8714 value that is being tested, *PTRUE is set to the value if the rtx being
8715 returned has a nonzero value, and *PFALSE is set to the other alternative.
8717 If we return zero, we set *PTRUE and *PFALSE to X. */
8719 static rtx
8721 {
8727 /* If we are comparing a value against zero, we are done. */
8730 {
8734 }
8736 /* If this is a unary operation whose operand has one of two values, apply
8737 our opcode to compute those values. */
8740 {
8745 }
8747 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8748 make can't possibly match and would suppress other optimizations. */
8750 ;
8752 /* If this is a binary operation, see if either side has only one of two
8753 values. If either one does or if both do and they are conditional on
8754 the same value, compute the new true and false values. */
8756 {
8762 {
8763 /* If if_then_else_cond returned zero, then true/false are the
8764 same rtl. We must copy one of them to prevent invalid rtl
8765 sharing. */
8772 {
8777 }
8778 else
8779 {
8782 }
8785 }
8787 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8788 operands is zero when the other is nonzero, and vice-versa,
8789 and STORE_FLAG_VALUE is 1 or -1. */
8795 {
8812 {
8819 const_true_rtx);
8821 }
8822 }
8824 /* Similarly for MULT, AND and UMIN, except that for these the result
8825 is always zero. */
8829 {
8843 {
8846 }
8847 }
8848 }
8851 {
8852 /* If we have IF_THEN_ELSE already, extract the condition and
8853 canonicalize it if it is NE or EQ. */
8859 {
8862 }
8863 else
8865 }
8867 /* If X is a SUBREG, we can narrow both the true and false values
8868 if the inner expression, if there is a condition. */
8872 {
8878 {
8882 }
8883 }
8885 /* If X is a constant, this isn't special and will cause confusions
8886 if we treat it as such. Likewise if it is equivalent to a constant. */
8889 ;
8891 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8892 will be least confusing to the rest of the compiler. */
8894 {
8897 }
8899 /* If X is known to be either 0 or -1, those are the true and
8900 false values when testing X. */
8904 {
8907 }
8909 /* Likewise for 0 or a single bit. */
8912 {
8915 }
8917 /* Otherwise fail; show no condition with true and false values the same. */
8920 }
8921 \f
8922 /* Return the value of expression X given the fact that condition COND
8923 is known to be true when applied to REG as its first operand and VAL
8924 as its second. X is known to not be shared and so can be modified in
8925 place.
8927 We only handle the simplest cases, and specifically those cases that
8928 arise with IF_THEN_ELSE expressions. */
8930 static rtx
8932 {
8934 rtx temp;
8941 /* If either operand of the condition is a floating point value,
8942 then we have to avoid collapsing an EQ comparison. */
8952 /* If X is (abs REG) and we know something about REG's relationship
8953 with zero, we may be able to simplify this. */
8957 {
8966 }
8968 /* The only other cases we handle are MIN, MAX, and comparisons if the
8969 operands are the same as REG and VAL. */
8972 {
8977 {
8979 {
8987 else
8989 }
8992 {
8995 /* Do not reverse the condition when it is NE or EQ.
8996 This is because we cannot conclude anything about
8997 the value of 'SMAX (x, y)' when x is not equal to y,
8998 but we can when x equals y. */
9004 {
9015 }
9016 }
9017 }
9018 }
9020 {
9025 {
9026 /* We must simplify subreg here, before we lose track of the
9027 original inner_mode. */
9032 else
9034 }
9037 }
9038 /* We don't have to handle SIGN_EXTEND here, because even in the
9039 case of replacing something with a modeless CONST_INT, a
9040 CONST_INT is already (supposed to be) a valid sign extension for
9041 its narrower mode, which implies it's already properly
9042 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9043 story is different. */
9045 {
9050 {
9051 /* We must simplify the zero_extend here, before we lose
9052 track of the original inner_mode. */
9057 else
9059 }
9062 }
9066 {
9073 }
9076 }
9077 \f
9078 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9079 assignment as a field assignment. */
9081 static int
9083 {
9090 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9091 Note that all SUBREGs of MEM are paradoxical; otherwise they
9092 would have been rewritten. */
9105 /* We used to see if get_last_value of X and Y were the same but that's
9106 not correct. In one direction, we'll cause the assignment to have
9107 the wrong destination and in the case, we'll import a register into this
9108 insn that might have already have been dead. So fail if none of the
9109 above cases are true. */
9111 }
9112 \f
9113 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9114 Return that assignment if so.
9116 We only handle the most common cases. */
9118 static rtx
9120 {
9123 rtx assign;
9125 HOST_WIDE_INT c1;
9126 HOST_WIDE_INT pos;
9128 rtx other;
9129 machine_mode mode;
9131 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9132 a clear of a one-bit field. We will have changed it to
9133 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9134 for a SUBREG. */
9140 {
9146 }
9156 {
9163 }
9165 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9166 one-bit field. */
9170 {
9176 }
9178 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9179 SRC is an AND with all bits of that field set, then we can discard
9180 the AND. */
9185 {
9192 else
9195 /* Complete overlap. We can remove the source AND. */
9199 /* Partial overlap. We can reduce the source AND. */
9201 {
9206 }
9207 }
9209 /* The other case we handle is assignments into a constant-position
9210 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9211 a mask that has all one bits except for a group of zero bits and
9212 OTHER is known to have zeros where C1 has ones, this is such an
9213 assignment. Compute the position and length from C1. Shift OTHER
9214 to the appropriate position, force it to the required mode, and
9215 make the extraction. Check for the AND in both operands. */
9231 else
9244 /* The mode to use for the source is the mode of the assignment, or of
9245 what is inside a possible STRICT_LOW_PART. */
9249 /* Shift OTHER right POS places and make it the source, restricting it
9250 to the proper length and mode. */
9255 dest);
9262 /* If SRC is masked by an AND that does not make a difference in
9263 the value being stored, strip it. */
9274 }
9275 \f
9276 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9277 if so. */
9279 static rtx
9281 {
9285 rtx tem;
9287 /* Distributivity is not true for floating point as it can change the
9288 value. So we don't do it unless -funsafe-math-optimizations. */
9293 /* The outer operation can only be one of the following: */
9301 /* If either operand is a primitive we can't do anything, so get out
9302 fast. */
9312 /* See if the inner and outer operations distribute. */
9314 {
9319 /* These all distribute except over PLUS. */
9330 /* This is also a multiply, so it distributes over everything. */
9333 /* This used to handle SUBREG, but this turned out to be counter-
9334 productive, since (subreg (op ...)) usually is not handled by
9335 insn patterns, and this "optimization" therefore transformed
9336 recognizable patterns into unrecognizable ones. Therefore the
9337 SUBREG case was removed from here.
9339 It is possible that distributing SUBREG over arithmetic operations
9340 leads to an intermediate result than can then be optimized further,
9341 e.g. by moving the outer SUBREG to the other side of a SET as done
9342 in simplify_set. This seems to have been the original intent of
9343 handling SUBREGs here.
9345 However, with current GCC this does not appear to actually happen,
9346 at least on major platforms. If some case is found where removing
9347 the SUBREG case here prevents follow-on optimizations, distributing
9348 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9352 }
9354 /* Set LHS and RHS to the inner operands (A and B in the example
9355 above) and set OTHER to the common operand (C in the example).
9356 There is only one way to do this unless the inner operation is
9357 commutative. */
9369 else
9372 /* Form the new inner operation, seeing if it simplifies first. */
9375 /* There is one exception to the general way of distributing:
9376 (a | c) ^ (b | c) -> (a ^ b) & ~c */
9378 {
9381 }
9383 /* We may be able to continuing distributing the result, so call
9384 ourselves recursively on the inner operation before forming the
9385 outer operation, which we return. */
9388 }
9390 /* See if X is of the form (* (+ A B) C), and if so convert to
9391 (+ (* A C) (* B C)) and try to simplify.
9393 Most of the time, this results in no change. However, if some of
9394 the operands are the same or inverses of each other, simplifications
9395 will result.
9397 For example, (and (ior A B) (not B)) can occur as the result of
9398 expanding a bit field assignment. When we apply the distributive
9399 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9400 which then simplifies to (and (A (not B))).
9402 Note that no checks happen on the validity of applying the inverse
9403 distributive law. This is pointless since we can do it in the
9404 few places where this routine is called.
9406 N is the index of the term that is decomposed (the arithmetic operation,
9407 i.e. (+ A B) in the first example above). !N is the index of the term that
9408 is distributed, i.e. of C in the first example above. */
9409 static rtx
9411 {
9412 machine_mode mode;
9416 /* Distributivity is not true for floating point as it can change the
9417 value. So we don't do it unless -funsafe-math-optimizations. */
9434 /* Special case (and (xor B C) (not A)), which is equivalent to
9435 (xor (ior A B) (ior A C)) */
9437 {
9440 }
9443 {
9444 /* Distribute the second term. */
9447 }
9448 else
9449 {
9450 /* Distribute the first term. */
9453 }
9463 }
9464 \f
9465 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9466 in MODE. Return an equivalent form, if different from (and VAROP
9467 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
9469 static rtx
9472 {
9475 rtx orig_varop;
9483 /* Simplify VAROP knowing that we will be only looking at some of the
9484 bits in it.
9486 Note by passing in CONSTOP, we guarantee that the bits not set in
9487 CONSTOP are not significant and will never be examined. We must
9488 ensure that is the case by explicitly masking out those bits
9489 before returning. */
9492 /* If VAROP is a CLOBBER, we will fail so return it. */
9496 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9497 to VAROP and return the new constant. */
9501 /* See what bits may be nonzero in VAROP. Unlike the general case of
9502 a call to nonzero_bits, here we don't care about bits outside
9503 MODE. */
9507 /* Turn off all bits in the constant that are known to already be zero.
9508 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9509 which is tested below. */
9513 /* If we don't have any bits left, return zero. */
9517 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9518 a power of two, we can replace this with an ASHIFT. */
9523 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9524 or XOR, then try to apply the distributive law. This may eliminate
9525 operations if either branch can be simplified because of the AND.
9526 It may also make some cases more complex, but those cases probably
9527 won't match a pattern either with or without this. */
9530 return
9531 gen_lowpart
9533 apply_distributive_law
9538 constop),
9542 constop))));
9544 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9545 the AND and see if one of the operands simplifies to zero. If so, we
9546 may eliminate it. */
9550 {
9559 }
9561 /* Make a SUBREG if necessary. If we can't make it, fail. */
9566 /* If we are only masking insignificant bits, return VAROP. */
9573 /* Otherwise, return an AND. */
9575 }
9578 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9579 in MODE.
9581 Return an equivalent form, if different from X. Otherwise, return X. If
9582 X is zero, we are to always construct the equivalent form. */
9584 static rtx
9587 {
9598 }
9599 \f
9600 /* Given a REG, X, compute which bits in X can be nonzero.
9601 We don't care about bits outside of those defined in MODE.
9603 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9604 a shift, AND, or zero_extract, we can do better. */
9606 static rtx
9608 const_rtx known_x ATTRIBUTE_UNUSED,
9609 machine_mode known_mode ATTRIBUTE_UNUSED,
9612 {
9613 rtx tem;
9616 /* If X is a register whose nonzero bits value is current, use it.
9617 Otherwise, if X is a register whose value we can find, use that
9618 value. Otherwise, use the previously-computed global nonzero bits
9619 for this register. */
9632 && !REGNO_REG_SET_P
9635 {
9639 /* We don't know anything about the upper bits. */
9644 }
9649 {
9650 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9651 /* If X is narrower than MODE and TEM is a non-negative
9652 constant that would appear negative in the mode of X,
9653 sign-extend it for use in reg_nonzero_bits because some
9654 machines (maybe most) will actually do the sign-extension
9655 and this is the conservative approach.
9657 ??? For 2.5, try to tighten up the MD files in this regard
9658 instead of this kludge. */
9665 #endif
9667 }
9669 {
9673 /* We don't know anything about the upper bits. */
9677 }
9680 }
9682 /* Return the number of bits at the high-order end of X that are known to
9683 be equal to the sign bit. X will be used in mode MODE; if MODE is
9684 VOIDmode, X will be used in its own mode. The returned value will always
9685 be between 1 and the number of bits in MODE. */
9687 static rtx
9689 const_rtx known_x ATTRIBUTE_UNUSED,
9690 machine_mode known_mode
9691 ATTRIBUTE_UNUSED,
9694 {
9695 rtx tem;
9707 && !REGNO_REG_SET_P
9710 {
9713 }
9724 }
9725 \f
9726 /* Return the number of "extended" bits there are in X, when interpreted
9727 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
9728 unsigned quantities, this is the number of high-order zero bits.
9729 For signed quantities, this is the number of copies of the sign bit
9730 minus 1. In both case, this function returns the number of "spare"
9731 bits. For example, if two quantities for which this function returns
9732 at least 1 are added, the addition is known not to overflow.
9734 This function will always return 0 unless called during combine, which
9735 implies that it must be called from a define_split. */
9737 unsigned int
9739 {
9749 }
9751 /* This function is called from `simplify_shift_const' to merge two
9752 outer operations. Specifically, we have already found that we need
9753 to perform operation *POP0 with constant *PCONST0 at the outermost
9754 position. We would now like to also perform OP1 with constant CONST1
9755 (with *POP0 being done last).
9757 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9758 the resulting operation. *PCOMP_P is set to 1 if we would need to
9759 complement the innermost operand, otherwise it is unchanged.
9761 MODE is the mode in which the operation will be done. No bits outside
9762 the width of this mode matter. It is assumed that the width of this mode
9763 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9765 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
9766 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
9767 result is simply *PCONST0.
9769 If the resulting operation cannot be expressed as one operation, we
9770 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
9772 static int
9773 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
9774 {
9781 /* If OP0 is an AND, clear unimportant bits in CONST1. */
9785 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
9786 if OP0 is SET. */
9795 {
9797 {
9815 }
9816 }
9818 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
9822 /* If the two constants aren't the same, we can't do anything. The
9823 remaining six cases can all be done. */
9827 else
9829 {
9832 /* (a & b) | b == b */
9835 /* (a ^ b) | b == a | b */
9836 {;}
9841 /* (a & b) ^ b == (~a) & b */
9844 /* (a | b) ^ b == a & ~b */
9850 /* (a | b) & b == b */
9853 /* (a ^ b) & b) == (~a) & b */
9858 }
9860 /* Check for NO-OP cases. */
9873 /* ??? Slightly redundant with the above mask, but not entirely.
9874 Moving this above means we'd have to sign-extend the mode mask
9875 for the final test. */
9880 }
9881 \f
9882 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9883 the shift in. The original shift operation CODE is performed on OP in
9884 ORIG_MODE. Return the wider mode MODE if we can perform the operation
9885 in that mode. Return ORIG_MODE otherwise. We can also assume that the
9886 result of the shift is subject to operation OUTER_CODE with operand
9887 OUTER_CONST. */
9889 static machine_mode
9893 {
9898 /* In general we can't perform in wider mode for right shift and rotate. */
9900 {
9902 /* We can still widen if the bits brought in from the left are identical
9903 to the sign bit of ORIG_MODE. */
9911 /* Similarly here but with zero bits. */
9916 /* We can also widen if the bits brought in will be masked off. This
9917 operation is performed in ORIG_MODE. */
9919 {
9925 }
9926 /* fall through */
9936 }
9937 }
9939 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
9940 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
9941 if we cannot simplify it. Otherwise, return a simplified value.
9943 The shift is normally computed in the widest mode we find in VAROP, as
9944 long as it isn't a different number of words than RESULT_MODE. Exceptions
9945 are ASHIFTRT and ROTATE, which are always done in their original mode. */
9947 static rtx
9950 {
9956 unsigned int mode_words
9958 /* We form (outer_op (code varop count) (outer_const)). */
9964 /* Make sure and truncate the "natural" shift on the way in. We don't
9965 want to do this inside the loop as it makes it more difficult to
9966 combine shifts. */
9970 /* If we were given an invalid count, don't do anything except exactly
9971 what was requested. */
9978 /* Unless one of the branches of the `if' in this loop does a `continue',
9979 we will `break' the loop after the `if'. */
9982 {
9983 /* If we have an operand of (clobber (const_int 0)), fail. */
9987 /* Convert ROTATERT to ROTATE. */
9989 {
9994 else
9996 }
10001 /* Handle cases where the count is greater than the size of the mode
10002 minus 1. For ASHIFT, use the size minus one as the count (this can
10003 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10004 take the count modulo the size. For other shifts, the result is
10005 zero.
10007 Since these shifts are being produced by the compiler by combining
10008 multiple operations, each of which are defined, we know what the
10009 result is supposed to be. */
10012 {
10017 else
10018 {
10019 /* We can't simply return zero because there may be an
10020 outer op. */
10024 }
10025 }
10027 /* If we discovered we had to complement VAROP, leave. Making a NOT
10028 here would cause an infinite loop. */
10032 /* An arithmetic right shift of a quantity known to be -1 or 0
10033 is a no-op. */
10037 {
10040 }
10042 /* If we are doing an arithmetic right shift and discarding all but
10043 the sign bit copies, this is equivalent to doing a shift by the
10044 bitsize minus one. Convert it into that shift because it will often
10045 allow other simplifications. */
10052 /* We simplify the tests below and elsewhere by converting
10053 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10054 `make_compound_operation' will convert it to an ASHIFTRT for
10055 those machines (such as VAX) that don't have an LSHIFTRT. */
10072 {
10079 {
10082 }
10086 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10087 minus the width of a smaller mode, we can do this with a
10088 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10095 {
10104 }
10108 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10109 the same number of words as what we've seen so far. Then store
10110 the widest mode in MODE. */
10116 == mode_words
10119 {
10124 }
10128 /* Some machines use MULT instead of ASHIFT because MULT
10129 is cheaper. But it is still better on those machines to
10130 merge two shifts into one. */
10133 {
10134 varop
10140 }
10144 /* Similar, for when divides are cheaper. */
10147 {
10148 varop
10154 }
10158 /* If we are extracting just the sign bit of an arithmetic
10159 right shift, that shift is not needed. However, the sign
10160 bit of a wider mode may be different from what would be
10161 interpreted as the sign bit in a narrower mode, so, if
10162 the result is narrower, don't discard the shift. */
10167 {
10170 }
10172 /* ... fall through ... */
10177 /* Here we have two nested shifts. The result is usually the
10178 AND of a new shift with a mask. We compute the result below. */
10185 {
10189 rtx mask_rtx;
10191 /* We have one common special case. We can't do any merging if
10192 the inner code is an ASHIFTRT of a smaller mode. However, if
10193 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10194 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10195 we can convert it to
10196 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10197 This simplifies certain SIGN_EXTEND operations. */
10201 {
10202 /* C3 has the low-order C1 bits zero. */
10214 }
10216 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10217 than C1 high-order bits equal to the sign bit, we can convert
10218 this to either an ASHIFT or an ASHIFTRT depending on the
10219 two counts.
10221 We cannot do this if VAROP's mode is not SHIFT_MODE. */
10227 {
10231 {
10234 }
10237 }
10239 /* There are some cases we can't do. If CODE is ASHIFTRT,
10240 we can only do this if FIRST_CODE is also ASHIFTRT.
10242 We can't do the case when CODE is ROTATE and FIRST_CODE is
10243 ASHIFTRT.
10245 If the mode of this shift is not the mode of the outer shift,
10246 we can't do this if either shift is a right shift or ROTATE.
10248 Finally, we can't do any of these if the mode is too wide
10249 unless the codes are the same.
10251 Handle the case where the shift codes are the same
10252 first. */
10255 {
10264 }
10275 /* To compute the mask to apply after the shift, shift the
10276 nonzero bits of the inner shift the same way the
10277 outer shift will. */
10280 result_mode);
10282 mask_rtx
10286 /* Give up if we can't compute an outer operation to use. */
10294 /* If the shifts are in the same direction, we add the
10295 counts. Otherwise, we subtract them. */
10299 else
10302 /* If COUNT is positive, the new shift is usually CODE,
10303 except for the two exceptions below, in which case it is
10304 FIRST_CODE. If the count is negative, FIRST_CODE should
10305 always be used */
10315 }
10317 /* If we have (A << B << C) for any shift, we can convert this to
10318 (A << C << B). This wins if A is a constant. Only try this if
10319 B is not a constant. */
10324 {
10331 }
10338 /* Make this fit the case below. */
10345 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10346 with C the size of VAROP - 1 and the shift is logical if
10347 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10348 we have an (le X 0) operation. If we have an arithmetic shift
10349 and STORE_FLAG_VALUE is 1 or we have a logical shift with
10350 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10358 {
10361 const0_rtx);
10367 }
10369 /* If we have (shift (logical)), move the logical to the outside
10370 to allow it to possibly combine with another logical and the
10371 shift to combine with another shift. This also canonicalizes to
10372 what a ZERO_EXTRACT looks like. Also, some machines have
10373 (and (shift)) insns. */
10376 /* We can't do this if we have (ashiftrt (xor)) and the
10377 constant has its sign bit set in shift_mode with shift_mode
10378 wider than result_mode. */
10382 shift_mode))
10390 {
10393 }
10395 /* If we can't do that, try to simplify the shift in each arm of the
10396 logical expression, make a new logical expression, and apply
10397 the inverse distributive law. This also can't be done for
10398 (ashiftrt (xor)) where we've widened the shift and the constant
10399 changes the sign bit. */
10404 shift_mode)))
10405 {
10417 }
10421 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10422 says that the sign bit can be tested, FOO has mode MODE, C is
10423 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10424 that may be nonzero. */
10434 {
10438 }
10442 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10443 than the number of bits in the mode is equivalent to A. */
10447 {
10451 }
10453 /* NEG commutes with ASHIFT since it is multiplication. Move the
10454 NEG outside to allow shifts to combine. */
10458 {
10461 }
10465 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10466 is one less than the number of bits in the mode is
10467 equivalent to (xor A 1). */
10474 {
10478 }
10480 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10481 that might be nonzero in BAR are those being shifted out and those
10482 bits are known zero in FOO, we can replace the PLUS with FOO.
10483 Similarly in the other operand order. This code occurs when
10484 we are computing the size of a variable-size array. */
10491 {
10494 }
10502 result_mode)))
10503 {
10506 }
10508 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
10518 {
10521 }
10523 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10524 signbit', and attempt to change the PLUS to an XOR and move it to
10525 the outer operation as is done above in the AND/IOR/XOR case
10526 leg for shift(logical). See details in logical handling above
10527 for reasoning in doing so. */
10538 {
10541 }
10546 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10547 with C the size of VAROP - 1 and the shift is logical if
10548 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10549 we have a (gt X 0) operation. If the shift is arithmetic with
10550 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10551 we have a (neg (gt X 0)) operation. */
10560 {
10563 const0_rtx);
10569 }
10573 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10574 if the truncate does not affect the value. */
10581 {
10584 varop_inner
10587 GEN_INT
10592 }
10597 }
10600 }
10605 /* We have now finished analyzing the shift. The result should be
10606 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
10607 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10608 to the result of the shift. OUTER_CONST is the relevant constant,
10609 but we must turn off all bits turned off in the shift. */
10617 /* Make a SUBREG if necessary. If we can't make it, fail. */
10622 /* If we have an outer operation and we just made a shift, it is
10623 possible that we could have simplified the shift were it not
10624 for the outer operation. So try to do the simplification
10625 recursively. */
10629 else
10635 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10636 turn off all the bits that the shift would have turned off. */
10641 /* Do the remainder of the processing in RESULT_MODE. */
10644 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10645 operation. */
10650 {
10658 {
10659 /* This means that we have determined that the result is
10660 equivalent to a constant. This should be rare. */
10663 }
10666 else
10669 }
10672 }
10674 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
10675 The result of the shift is RESULT_MODE. If we cannot simplify it,
10676 return X or, if it is NULL, synthesize the expression with
10677 simplify_gen_binary. Otherwise, return a simplified value.
10679 The shift is normally computed in the widest mode we find in VAROP, as
10680 long as it isn't a different number of words than RESULT_MODE. Exceptions
10681 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10683 static rtx
10686 {
10696 }
10698 \f
10699 /* Like recog, but we receive the address of a pointer to a new pattern.
10700 We try to match the rtx that the pointer points to.
10701 If that fails, we may try to modify or replace the pattern,
10702 storing the replacement into the same pointer object.
10704 Modifications include deletion or addition of CLOBBERs.
10706 PNOTES is a pointer to a location where any REG_UNUSED notes added for
10707 the CLOBBERs are placed.
10709 The value is the final insn code from the pattern ultimately matched,
10710 or -1. */
10712 static int
10714 {
10716 rtx pat_without_clobbers;
10724 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10725 we use to indicate that something didn't match. If we find such a
10726 thing, force rejection. */
10740 {
10743 else
10746 }
10748 /* If it isn't, there is the possibility that we previously had an insn
10749 that clobbered some register as a side effect, but the combined
10750 insn doesn't need to do that. So try once more without the clobbers
10751 unless this represents an ASM insn. */
10755 {
10760 {
10763 pos++;
10764 }
10774 {
10777 else
10780 }
10781 }
10788 /* Recognize all noop sets, these will be killed by followup pass. */
10792 /* If we had any clobbers to add, make a new pattern than contains
10793 them. Then check to make sure that all of them are dead. */
10795 {
10805 else
10812 {
10817 {
10821 }
10822 }
10824 }
10828 {
10835 /* Allow targets to reject combined insn. */
10837 {
10840 dump_file);
10842 /* Callers expect recog_for_combine to strip
10843 clobbers from the pattern on failure. */
10848 }
10853 }
10859 }
10860 \f
10861 /* Like gen_lowpart_general but for use by combine. In combine it
10862 is not possible to create any new pseudoregs. However, it is
10863 safe to create invalid memory addresses, because combine will
10864 try to recognize them and all they will do is make the combine
10865 attempt fail.
10867 If for some reason this cannot do its job, an rtx
10868 (clobber (const_int 0)) is returned.
10869 An insn containing that will not be recognized. */
10871 static rtx
10873 {
10877 rtx result;
10882 /* We can only support MODE being wider than a word if X is a
10883 constant integer or has a mode the same size. */
10888 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
10889 won't know what to do. So we will strip off the SUBREG here and
10890 process normally. */
10892 {
10895 /* For use in case we fall down into the address adjustments
10896 further below, we need to adjust the known mode and size of
10897 x; imode and isize, since we just adjusted x. */
10904 }
10912 {
10915 /* Refuse to work on a volatile memory ref or one with a mode-dependent
10916 address. */
10921 /* If we want to refer to something bigger than the original memref,
10922 generate a paradoxical subreg instead. That will force a reload
10923 of the original memref X. */
10930 /* Adjust the address so that the address-after-the-data is
10931 unchanged. */
10936 }
10938 /* If X is a comparison operator, rewrite it in a new mode. This
10939 probably won't match, but may allow further simplifications. */
10943 /* If we couldn't simplify X any other way, just enclose it in a
10944 SUBREG. Normally, this SUBREG won't match, but some patterns may
10945 include an explicit SUBREG or we may simplify it further in combine. */
10946 else
10947 {
10949 rtx res;
10953 {
10958 }
10962 }
10964 fail:
10966 }
10967 \f
10968 /* Try to simplify a comparison between OP0 and a constant OP1,
10969 where CODE is the comparison code that will be tested, into a
10970 (CODE OP0 const0_rtx) form.
10972 The result is a possibly different comparison code to use.
10973 *POP1 may be updated. */
10975 static enum rtx_code
10978 {
10982 /* Get the constant we are comparing against and turn off all bits
10983 not on in our mode. */
10987 /* If we are comparing against a constant power of two and the value
10988 being compared can only have that single bit nonzero (e.g., it was
10989 `and'ed with that bit), we can replace this with a comparison
10990 with zero. */
10998 {
11001 }
11003 /* Similarly, if we are comparing a value known to be either -1 or
11004 0 with -1, change it to the opposite comparison against zero. */
11009 {
11012 }
11014 /* Do some canonicalizations based on the comparison code. We prefer
11015 comparisons against zero and then prefer equality comparisons.
11016 If we can reduce the size of a constant, we will do that too. */
11018 {
11020 /* < C is equivalent to <= (C - 1) */
11022 {
11025 /* ... fall through to LE case below. */
11026 }
11027 else
11031 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11033 {
11036 }
11038 /* If we are doing a <= 0 comparison on a value known to have
11039 a zero sign bit, we can replace this with == 0. */
11049 /* >= C is equivalent to > (C - 1). */
11051 {
11054 /* ... fall through to GT below. */
11055 }
11056 else
11060 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11062 {
11065 }
11067 /* If we are doing a > 0 comparison on a value known to have
11068 a zero sign bit, we can replace this with != 0. */
11078 /* < C is equivalent to <= (C - 1). */
11080 {
11083 /* ... fall through ... */
11084 }
11085 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11089 {
11093 }
11094 else
11098 /* unsigned <= 0 is equivalent to == 0 */
11101 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11105 {
11108 }
11112 /* >= C is equivalent to > (C - 1). */
11114 {
11117 /* ... fall through ... */
11118 }
11120 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
11124 {
11128 }
11129 else
11133 /* unsigned > 0 is equivalent to != 0 */
11136 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
11140 {
11143 }
11148 }
11152 }
11153 \f
11154 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11155 comparison code that will be tested.
11157 The result is a possibly different comparison code to use. *POP0 and
11158 *POP1 may be updated.
11160 It is possible that we might detect that a comparison is either always
11161 true or always false. However, we do not perform general constant
11162 folding in combine, so this knowledge isn't useful. Such tautologies
11163 should have been detected earlier. Hence we ignore all such cases. */
11165 static enum rtx_code
11167 {
11174 /* Try a few ways of applying the same transformation to both operands. */
11176 {
11177 #ifndef WORD_REGISTER_OPERATIONS
11178 /* The test below this one won't handle SIGN_EXTENDs on these machines,
11179 so check specially. */
11194 - (GET_MODE_PRECISION
11196 {
11199 }
11200 #endif
11202 /* If both operands are the same constant shift, see if we can ignore the
11203 shift. We can if the shift is a rotate or if the bits shifted out of
11204 this shift are known to be zero for both inputs and if the type of
11205 comparison is compatible with the shift. */
11218 {
11231 else
11233 }
11235 /* If both operands are AND's of a paradoxical SUBREG by constant, the
11236 SUBREGs are of the same mode, and, in both cases, the AND would
11237 be redundant if the comparison was done in the narrower mode,
11238 do the comparison in the narrower mode (e.g., we are AND'ing with 1
11239 and the operand's possibly nonzero bits are 0xffffff01; in that case
11240 if we only care about QImode, we don't need the AND). This case
11241 occurs if the output mode of an scc insn is not SImode and
11242 STORE_FLAG_VALUE == 1 (e.g., the 386).
11244 Similarly, check for a case where the AND's are ZERO_EXTEND
11245 operations from some narrower mode even though a SUBREG is not
11246 present. */
11251 {
11268 {
11272 /* The resulting comparison is always unsigned since we masked
11273 off the original sign bit. */
11277 }
11284 {
11290 }
11294 }
11296 /* If both operands are NOT, we can strip off the outer operation
11297 and adjust the comparison code for swapped operands; similarly for
11298 NEG, except that this must be an equality comparison. */
11304 else
11306 }
11308 /* If the first operand is a constant, swap the operands and adjust the
11309 comparison code appropriately, but don't do this if the second operand
11310 is already a constant integer. */
11312 {
11315 }
11317 /* We now enter a loop during which we will try to simplify the comparison.
11318 For the most part, we only are concerned with comparisons with zero,
11319 but some things may really be comparisons with zero but not start
11320 out looking that way. */
11323 {
11330 HOST_WIDE_INT const_op;
11332 /* We only want to handle integral modes. This catches VOIDmode,
11333 CCmode, and the floating-point modes. An exception is that we
11334 can handle VOIDmode if OP0 is a COMPARE or a comparison
11335 operation. */
11342 /* Try to simplify the compare to constant, possibly changing the
11343 comparison op, and/or changing op1 to zero. */
11347 /* Compute some predicates to simplify code below. */
11354 /* If this is a sign bit comparison and we can do arithmetic in
11355 MODE, say that we will only be needing the sign bit of OP0. */
11362 /* Now try cases based on the opcode of OP0. If none of the cases
11363 does a "continue", we exit this loop immediately after the
11364 switch. */
11367 {
11369 /* If we are extracting a single bit from a variable position in
11370 a constant that has only a single bit set and are comparing it
11371 with zero, we can convert this into an equality comparison
11372 between the position and the location of the single bit. */
11373 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11374 have already reduced the shift count modulo the word size. */
11380 {
11388 /* Result is nonzero iff shift count is equal to I. */
11391 }
11393 /* ... fall through ... */
11398 {
11401 }
11405 /* If testing for equality, we can take the NOT of the constant. */
11408 {
11412 }
11414 /* If just looking at the sign bit, reverse the sense of the
11415 comparison. */
11417 {
11421 }
11425 /* If testing for equality, we can take the NEG of the constant. */
11428 {
11432 }
11434 /* The remaining cases only apply to comparisons with zero. */
11438 /* When X is ABS or is known positive,
11439 (neg X) is < 0 if and only if X != 0. */
11447 {
11451 }
11453 /* If we have NEG of something whose two high-order bits are the
11454 same, we know that "(-a) < 0" is equivalent to "a > 0". */
11456 {
11460 }
11464 /* If we are testing equality and our count is a constant, we
11465 can perform the inverse operation on our RHS. */
11469 {
11473 }
11475 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11476 a particular bit. Convert it to an AND of a constant of that
11477 bit. This will be converted into a ZERO_EXTRACT. */
11481 {
11488 }
11490 /* Fall through. */
11493 /* ABS is ignorable inside an equality comparison with zero. */
11495 {
11498 }
11502 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11503 (compare FOO CONST) if CONST fits in FOO's mode and we
11504 are either testing inequality or have an unsigned
11505 comparison with ZERO_EXTEND or a signed comparison with
11506 SIGN_EXTEND. But don't do it if we don't have a compare
11507 insn of the given mode, since we'd have to revert it
11508 later on, and then we wouldn't know whether to sign- or
11509 zero-extend. */
11512 && ! unsigned_comparison_p
11516 {
11519 }
11523 /* Check for the case where we are comparing A - C1 with C2, that is
11525 (subreg:MODE (plus (A) (-C1))) op (C2)
11527 with C1 a constant, and try to lift the SUBREG, i.e. to do the
11528 comparison in the wider mode. One of the following two conditions
11529 must be true in order for this to be valid:
11531 1. The mode extension results in the same bit pattern being added
11532 on both sides and the comparison is equality or unsigned. As
11533 C2 has been truncated to fit in MODE, the pattern can only be
11534 all 0s or all 1s.
11536 2. The mode extension results in the sign bit being copied on
11537 each side.
11539 The difficulty here is that we have predicates for A but not for
11540 (A - C1) so we need to check that C1 is within proper bounds so
11541 as to perturbate A as little as possible. */
11548 {
11557 /* (A - C1) zero-extends if it is positive and sign-extends
11558 if it is negative, C2 both zero- and sign-extends. */
11562 /* (A - C1) sign-extends if it is positive and 1-extends
11563 if it is negative, C2 both sign- and 1-extends. */
11570 /* (A - C1) always sign-extends, like C2. */
11574 {
11577 }
11578 }
11580 /* If the inner mode is narrower and we are extracting the low part,
11581 we can treat the SUBREG as if it were a ZERO_EXTEND. */
11585 else
11588 /* ... fall through ... */
11598 {
11601 }
11605 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
11606 this for equality comparisons due to pathological cases involving
11607 overflows. */
11611 {
11615 }
11617 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
11620 {
11624 }
11628 /* We used to optimize signed comparisons against zero, but that
11629 was incorrect. Unsigned comparisons against zero (GTU, LEU)
11630 arrive here as equality comparisons, or (GEU, LTU) are
11631 optimized away. No need to special-case them. */
11633 /* (eq (minus A B) C) -> (eq A (plus B C)) or
11634 (eq B (minus A C)), whichever simplifies. We can only do
11635 this for equality comparisons due to pathological cases involving
11636 overflows. */
11640 {
11644 }
11649 {
11653 }
11655 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11656 of bits in X minus 1, is one iff X > 0. */
11661 {
11665 }
11669 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
11670 if C is zero or B is a constant. */
11674 {
11678 }
11686 /* We can't do anything if OP0 is a condition code value, rather
11687 than an actual data value. */
11693 /* Get the two operands being compared. */
11696 else
11699 /* Check for the cases where we simply want the result of the
11700 earlier test or the opposite of that result. */
11704 {
11708 else
11712 {
11717 }
11718 }
11722 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11723 iff X <= 0. */
11727 {
11731 }
11735 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
11736 will be converted to a ZERO_EXTRACT later. */
11740 {
11745 }
11747 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11748 zero and X is a comparison and C1 and C2 describe only bits set
11749 in STORE_FLAG_VALUE, we can compare with X. */
11757 {
11764 {
11767 }
11768 }
11770 /* If we are doing an equality comparison of an AND of a bit equal
11771 to the sign bit, replace this with a LT or GE comparison of
11772 the underlying value. */
11779 {
11783 }
11785 /* If this AND operation is really a ZERO_EXTEND from a narrower
11786 mode, the constant fits within that mode, and this is either an
11787 equality or unsigned comparison, try to do this comparison in
11788 the narrower mode.
11790 Note that in:
11792 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11793 -> (ne:DI (reg:SI 4) (const_int 0))
11795 unless TRULY_NOOP_TRUNCATION allows it or the register is
11796 known to hold a value of the required mode the
11797 transformation is invalid. */
11808 {
11811 }
11813 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11814 fits in both M1 and M2 and the SUBREG is either paradoxical
11815 or represents the low part, permute the SUBREG and the AND
11816 and try again. */
11818 {
11821 /* Require an integral mode, to avoid creating something like
11822 (AND:SF ...). */
11824 /* It is unsafe to commute the AND into the SUBREG if the
11825 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11826 not defined. As originally written the upper bits
11827 have a defined value due to the AND operation.
11828 However, if we commute the AND inside the SUBREG then
11829 they no longer have defined values and the meaning of
11830 the code has been changed. */
11832 #ifdef WORD_REGISTER_OPERATIONS
11835 #endif
11845 {
11851 }
11852 }
11854 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
11858 {
11863 }
11865 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11866 (eq (and (lshiftrt X) 1) 0).
11867 Also handle the case where (not X) is expressed using xor. */
11871 {
11883 {
11884 op0
11889 }
11890 }
11894 /* If we have (compare (ashift FOO N) (const_int C)) and
11895 the high order N bits of FOO (N+1 if an inequality comparison)
11896 are known to be zero, we can do this by comparing FOO with C
11897 shifted right N bits so long as the low-order N bits of C are
11898 zero. */
11910 {
11911 /* We must perform a logical shift, not an arithmetic one,
11912 as we want the top N bits of C to be zero. */
11919 }
11921 /* If we are doing a sign bit comparison, it means we are testing
11922 a particular bit. Convert it to the appropriate AND. */
11925 {
11932 }
11934 /* If this an equality comparison with zero and we are shifting
11935 the low bit to the sign bit, we can convert this to an AND of the
11936 low-order bit. */
11940 {
11943 }
11947 /* If this is an equality comparison with zero, we can do this
11948 as a logical shift, which might be much simpler. */
11951 {
11956 }
11958 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11959 do the comparison in a narrower mode. */
11969 {
11972 }
11974 /* Likewise if OP0 is a PLUS of a sign extension with a
11975 constant, which is usually represented with the PLUS
11976 between the shifts. */
11988 {
11996 new_const);
11998 }
12000 /* ... fall through ... */
12002 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12003 the low order N bits of FOO are known to be zero, we can do this
12004 by comparing FOO with C shifted left N bits so long as no
12005 overflow occurs. Even if the low order N bits of FOO aren't known
12006 to be zero, if the comparison is >= or < we can use the same
12007 optimization and for > or <= by setting all the low
12008 order N bits in the comparison constant. */
12019 {
12020 unsigned HOST_WIDE_INT low_bits
12025 {
12026 /* If the shift was logical, then we must make the condition
12027 unsigned. */
12035 const_op
12040 }
12041 }
12043 /* If we are using this shift to extract just the sign bit, we
12044 can replace this with an LT or GE comparison. */
12049 {
12053 }
12058 }
12061 }
12063 /* Now make any compound operations involved in this comparison. Then,
12064 check for an outmost SUBREG on OP0 that is not doing anything or is
12065 paradoxical. The latter transformation must only be performed when
12066 it is known that the "extra" bits will be the same in op0 and op1 or
12067 that they don't matter. There are three cases to consider:
12069 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12070 care bits and we can assume they have any convenient value. So
12071 making the transformation is safe.
12073 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
12074 In this case the upper bits of op0 are undefined. We should not make
12075 the simplification in that case as we do not know the contents of
12076 those bits.
12078 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
12079 UNKNOWN. In that case we know those bits are zeros or ones. We must
12080 also be sure that they are the same as the upper bits of op1.
12082 We can never remove a SUBREG for a non-equality comparison because
12083 the sign bit is in a different place in the underlying object. */
12092 {
12094 {
12095 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
12096 implemented. */
12098 {
12101 }
12102 }
12108 {
12114 }
12115 }
12117 /* We now do the opposite procedure: Some machines don't have compare
12118 insns in all modes. If OP0's mode is an integer mode smaller than a
12119 word and we can't do a compare in that mode, see if there is a larger
12120 mode for which we can do the compare. There are a number of cases in
12121 which we can use the wider mode. */
12131 {
12134 /* If this is a test for negative, we can make an explicit
12135 test of the sign bit. Test this first so we can use
12136 a paradoxical subreg to extend OP0. */
12140 {
12141 unsigned HOST_WIDE_INT sign
12148 }
12150 /* If the only nonzero bits in OP0 and OP1 are those in the
12151 narrower mode and this is an equality or unsigned comparison,
12152 we can use the wider mode. Similarly for sign-extended
12153 values, in which case it is true for all comparisons. */
12170 {
12171 /* If OP0 is an AND and we don't have an AND in MODE either,
12172 make a new AND in the proper mode. */
12180 else
12181 {
12183 {
12186 }
12187 else
12188 {
12191 }
12193 }
12194 }
12195 }
12197 /* We may have changed the comparison operands. Re-canonicalize. */
12199 {
12202 }
12204 /* If this machine only supports a subset of valid comparisons, see if we
12205 can convert an unsupported one into a supported one. */
12212 }
12213 \f
12214 /* Utility function for record_value_for_reg. Count number of
12215 rtxs in X. */
12216 static int
12218 {
12225 {
12245 }
12256 }
12257 \f
12258 /* Utility function for following routine. Called when X is part of a value
12259 being stored into last_set_value. Sets last_set_table_tick
12260 for each register mentioned. Similar to mention_regs in cse.c */
12262 static void
12264 {
12270 {
12276 {
12279 }
12282 }
12286 {
12287 /* Check for identical subexpressions. If x contains
12288 identical subexpression we only have to traverse one of
12289 them. */
12291 {
12292 /* Note that at this point x1 has already been
12293 processed. */
12297 /* If x0 and x1 are identical then there is no need to
12298 process x0. */
12302 /* If x0 is identical to a subexpression of x1 then while
12303 processing x1, x0 has already been processed. Thus we
12304 are done with x. */
12309 /* If x1 is identical to a subexpression of x0 then we
12310 still have to process the rest of x0. */
12313 {
12316 }
12317 }
12320 }
12324 }
12326 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
12327 are saying that the register is clobbered and we no longer know its
12328 value. If INSN is zero, don't update reg_stat[].last_set; this is
12329 only permitted with VALUE also zero and is used to invalidate the
12330 register. */
12332 static void
12334 {
12340 /* If VALUE contains REG and we have a previous value for REG, substitute
12341 the previous value. */
12343 {
12344 rtx tem;
12346 /* Set things up so get_last_value is allowed to see anything set up to
12347 our insn. */
12351 /* If TEM is simply a binary operation with two CLOBBERs as operands,
12352 it isn't going to be useful and will take a lot of time to process,
12353 so just use the CLOBBER. */
12356 {
12362 {
12363 /* If there are two or more occurrences of REG in VALUE,
12364 prevent the value from growing too much. */
12367 }
12370 }
12371 }
12373 /* For each register modified, show we don't know its value, that
12374 we don't know about its bitwise content, that its value has been
12375 updated, and that we don't know the location of the death of the
12376 register. */
12378 {
12390 }
12392 /* Mark registers that are being referenced in this value. */
12396 /* Now update the status of each register being set.
12397 If someone is using this register in this block, set this register
12398 to invalid since we will get confused between the two lives in this
12399 basic block. This makes using this register always invalid. In cse, we
12400 scan the table to invalidate all entries using this register, but this
12401 is too much work for us. */
12404 {
12410 else
12412 }
12414 /* The value being assigned might refer to X (like in "x++;"). In that
12415 case, we must replace it with (clobber (const_int 0)) to prevent
12416 infinite loops. */
12419 {
12423 }
12425 /* For the main register being modified, update the value, the mode, the
12426 nonzero bits, and the number of sign bit copies. */
12431 {
12439 rsp->last_set_sign_bit_copies
12441 }
12442 }
12444 /* Called via note_stores from record_dead_and_set_regs to handle one
12445 SET or CLOBBER in an insn. DATA is the instruction in which the
12446 set is occurring. */
12448 static void
12450 {
12457 {
12461 }
12464 {
12465 /* If we are setting the whole register, we know its value. Otherwise
12466 show that we don't know the value. We can handle SUBREG in
12467 some cases. */
12478 else
12480 }
12482 /* Ignore pushes, they clobber nothing. */
12485 }
12487 /* Update the records of when each REG was most recently set or killed
12488 for the things done by INSN. This is the last thing done in processing
12489 INSN in the combiner loop.
12491 We update reg_stat[], in particular fields last_set, last_set_value,
12492 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12493 last_death, and also the similar information mem_last_set (which insn
12494 most recently modified memory) and last_call_luid (which insn was the
12495 most recent subroutine call). */
12497 static void
12499 {
12500 rtx link;
12504 {
12507 {
12512 {
12517 }
12518 }
12521 }
12524 {
12525 hard_reg_set_iterator hrsi;
12527 {
12539 }
12543 /* We can't combine into a call pattern. Remember, though, that
12544 the return value register is set at this LUID. We could
12545 still replace a register with the return value from the
12546 wrong subroutine call! */
12548 }
12549 else
12551 }
12553 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12554 register present in the SUBREG, so for each such SUBREG go back and
12555 adjust nonzero and sign bit information of the registers that are
12556 known to have some zero/sign bits set.
12558 This is needed because when combine blows the SUBREGs away, the
12559 information on zero/sign bits is lost and further combines can be
12560 missed because of that. */
12562 static void
12564 {
12566 rtx set;
12574 {
12583 {
12586 }
12590 {
12593 }
12596 {
12599 }
12600 else
12602 }
12603 }
12605 /* Check if X, a register, is known to contain a value already
12606 truncated to MODE. In this case we can use a subreg to refer to
12607 the truncated value even though in the generic case we would need
12608 an explicit truncation. */
12610 static bool
12612 {
12624 }
12626 /* If X is a hard reg or a subreg record the mode that the register is
12627 accessed in. For non-TRULY_NOOP_TRUNCATION targets we might be able
12628 to turn a truncate into a subreg using this information. Return true
12629 if traversing X is complete. */
12631 static bool
12633 {
12634 machine_mode truncated_mode;
12638 {
12649 }
12650 /* ??? For hard-regs we now record everything. We might be able to
12651 optimize this using last_set_mode. */
12654 else
12662 {
12665 }
12668 }
12670 /* Callback for note_uses. Find hardregs and subregs of pseudos and
12671 the modes they are used in. This can help truning TRUNCATEs into
12672 SUBREGs. */
12674 static void
12676 {
12681 }
12683 /* Scan X for promoted SUBREGs. For each one found,
12684 note what it implies to the registers used in it. */
12686 static void
12688 {
12693 else
12694 {
12700 {
12710 }
12711 }
12712 }
12713 \f
12714 /* Verify that all the registers and memory references mentioned in *LOC are
12715 still valid. *LOC was part of a value set in INSN when label_tick was
12716 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
12717 the invalid references with (clobber (const_int 0)) and return 1. This
12718 replacement is useful because we often can get useful information about
12719 the form of a value (e.g., if it was produced by a shift that always
12720 produces -1 or 0) even though we don't know exactly what registers it
12721 was produced from. */
12723 static int
12725 {
12732 {
12738 {
12741 /* If this is a pseudo-register that was only set once and not
12742 live at the beginning of the function, it is always valid. */
12745 && (!REGNO_REG_SET_P
12747 regno)))
12749 {
12753 }
12754 }
12757 }
12758 /* If this is a memory reference, make sure that there were no stores after
12759 it that might have clobbered the value. We don't have alias info, so we
12760 assume any store invalidates it. Moreover, we only have local UIDs, so
12761 we also assume that there were stores in the intervening basic blocks. */
12764 {
12768 }
12771 {
12773 {
12774 /* Check for identical subexpressions. If x contains
12775 identical subexpression we only have to traverse one of
12776 them. */
12778 {
12779 /* Note that at this point x0 has already been checked
12780 and found valid. */
12784 /* If x0 and x1 are identical then x is also valid. */
12788 /* If x1 is identical to a subexpression of x0 then
12789 while checking x0, x1 has already been checked. Thus
12790 it is valid and so as x. */
12795 /* If x0 is identical to a subexpression of x1 then x is
12796 valid iff the rest of x1 is valid. */
12799 return
12803 }
12808 }
12814 }
12816 /* If we haven't found a reason for it to be invalid, it is valid. */
12818 }
12820 /* Get the last value assigned to X, if known. Some registers
12821 in the value may be replaced with (clobber (const_int 0)) if their value
12822 is known longer known reliably. */
12824 static rtx
12826 {
12828 rtx value;
12831 /* If this is a non-paradoxical SUBREG, get the value of its operand and
12832 then convert it to the desired mode. If this is a paradoxical SUBREG,
12833 we cannot predict what values the "extra" bits might have. */
12847 /* If we don't have a value, or if it isn't for this basic block and
12848 it's either a hard register, set more than once, or it's a live
12849 at the beginning of the function, return 0.
12851 Because if it's not live at the beginning of the function then the reg
12852 is always set before being used (is never used without being set).
12853 And, if it's set only once, and it's always set before use, then all
12854 uses must have the same last value, even if it's not from this basic
12855 block. */
12861 || REGNO_REG_SET_P
12865 /* If the value was set in a later insn than the ones we are processing,
12866 we can't use it even if the register was only set once. */
12871 /* If the value has all its registers valid, return it. */
12875 /* Otherwise, make a copy and replace any invalid register with
12876 (clobber (const_int 0)). If that fails for some reason, return 0. */
12883 }
12884 \f
12885 /* Return nonzero if expression X refers to a REG or to memory
12886 that is set in an instruction more recent than FROM_LUID. */
12888 static int
12890 {
12896 {
12900 #ifdef PUSH_ROUNDING
12901 /* Don't allow uses of the stack pointer to be moved,
12902 because we don't know whether the move crosses a push insn. */
12905 #endif
12907 {
12913 }
12915 }
12923 {
12925 {
12930 }
12934 }
12936 }
12937 \f
12938 /* Define three variables used for communication between the following
12939 routines. */
12944 /* Function called via note_stores from reg_dead_at_p.
12946 If DEST is within [reg_dead_regno, reg_dead_endregno), set
12947 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
12949 static void
12951 {
12961 }
12963 /* Return nonzero if REG is known to be dead at INSN.
12965 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
12966 referencing REG, it is dead. If we hit a SET referencing REG, it is
12967 live. Otherwise, see if it is live or dead at the start of the basic
12968 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
12969 must be assumed to be always live. */
12971 static int
12973 {
12974 basic_block block;
12977 /* Set variables for reg_dead_at_p_1. */
12983 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
12984 we allow the machine description to decide whether use-and-clobber
12985 patterns are OK. */
12987 {
12991 }
12993 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12994 beginning of basic block. */
12997 {
12999 {
13009 }
13015 }
13017 /* Look at live-in sets for the basic block that we were in. */
13023 }
13024 \f
13025 /* Note hard registers in X that are used. */
13027 static void
13029 {
13035 {
13039 CASE_CONST_ANY:
13044 #ifdef HAVE_cc0
13045 /* CC0 must die in the insn after it is set, so we don't need to take
13046 special note of it here. */
13048 #endif
13052 /* If we are clobbering a MEM, mark any hard registers inside the
13053 address as used. */
13060 /* A hard reg in a wide mode may really be multiple registers.
13061 If so, mark all of them just like the first. */
13063 {
13064 /* None of this applies to the stack, frame or arg pointers. */
13066 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
13068 #endif
13069 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
13071 #endif
13076 }
13080 {
13081 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13082 the address. */
13094 }
13099 }
13101 /* Recursively scan the operands of this expression. */
13103 {
13107 {
13111 {
13116 }
13117 }
13118 }
13119 }
13120 \f
13121 /* Remove register number REGNO from the dead registers list of INSN.
13123 Return the note used to record the death, if there was one. */
13125 rtx
13127 {
13134 }
13136 /* For each register (hardware or pseudo) used within expression X, if its
13137 death is in an instruction with luid between FROM_LUID (inclusive) and
13138 TO_INSN (exclusive), put a REG_DEAD note for that register in the
13139 list headed by PNOTES.
13141 That said, don't move registers killed by maybe_kill_insn.
13143 This is done when X is being merged by combination into TO_INSN. These
13144 notes will then be distributed as needed. */
13146 static void
13149 {
13155 {
13159 /* Don't move the register if it gets killed in between from and to. */
13168 {
13171 /* It is possible for the call above to return 0. This can occur
13172 when last_death points to I2 or I1 that we combined with.
13173 In that case make a new note.
13175 We must also check for the case where X is a hard register
13176 and NOTE is a death note for a range of hard registers
13177 including X. In that case, we must put REG_DEAD notes for
13178 the remaining registers in place of NOTE. */
13183 {
13192 }
13194 /* If we didn't find any note, or if we found a REG_DEAD note that
13195 covers only part of the given reg, and we have a multi-reg hard
13196 register, then to be safe we must check for REG_DEAD notes
13197 for each register other than the first. They could have
13198 their own REG_DEAD notes lying around. */
13205 {
13212 else
13218 }
13221 {
13224 }
13225 else
13227 }
13230 }
13233 {
13238 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13239 that accesses one word of a multi-word item, some
13240 piece of everything register in the expression is used by
13241 this insn, so remove any old death. */
13242 /* ??? So why do we test for equality of the sizes? */
13251 {
13254 }
13256 /* If this is some other SUBREG, we know it replaces the entire
13257 value, so use that as the destination. */
13261 /* If this is a MEM, adjust deaths of anything used in the address.
13262 For a REG (the only other possibility), the entire value is
13263 being replaced so the old value is not used in this insn. */
13269 }
13278 {
13280 {
13285 }
13288 }
13289 }
13290 \f
13291 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13292 pattern of an insn. X must be a REG. */
13294 static int
13296 {
13300 {
13302 rtx target;
13309 else
13326 }
13334 }
13335 \f
13336 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13337 as appropriate. I3 and I2 are the insns resulting from the combination
13338 insns including FROM (I2 may be zero).
13340 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13341 not need REG_DEAD notes because they are being substituted for. This
13342 saves searching in the most common cases.
13344 Each note in the list is either ignored or placed on some insns, depending
13345 on the type of note. */
13347 static void
13350 {
13352 rtx tem_note;
13356 {
13361 {
13364 /* Doesn't matter much where we put this, as long as it's somewhere.
13365 It is preferable to keep these notes on branches, which is most
13366 likely to be i3. */
13373 else
13374 {
13377 }
13381 /* These notes must remain with the call or trapping instruction. */
13386 else
13387 {
13393 /* ??? Otherwise assume we've combined things such that we
13394 can now prove that the instructions can't trap. Drop the
13395 note in this case. */
13396 }
13400 /* ??? How to distribute between i3-i1. Assume i3 contains the
13401 entire adjustment. Assert i3 contains at least some adjust. */
13403 {
13405 /* fixup_args_size_notes looks at REG_NORETURN note,
13406 so ensure the note is placed there first. */
13408 {
13412 {
13418 }
13419 }
13421 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13422 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
13425 && !ACCUMULATE_OUTGOING_ARGS
13427 }
13434 /* These notes must remain with the call. It should not be
13435 possible for both I2 and I3 to be a call. */
13438 else
13439 {
13442 }
13446 /* Any clobbers for i3 may still exist, and so we must process
13447 REG_UNUSED notes from that insn.
13449 Any clobbers from i2 or i1 can only exist if they were added by
13450 recog_for_combine. In that case, recog_for_combine created the
13451 necessary REG_UNUSED notes. Trying to keep any original
13452 REG_UNUSED notes from these insns can cause incorrect output
13453 if it is for the same register as the original i3 dest.
13454 In that case, we will notice that the register is set in i3,
13455 and then add a REG_UNUSED note for the destination of i3, which
13456 is wrong. However, it is possible to have REG_UNUSED notes from
13457 i2 or i1 for register which were both used and clobbered, so
13458 we keep notes from i2 or i1 if they will turn into REG_DEAD
13459 notes. */
13461 /* If this register is set or clobbered in I3, put the note there
13462 unless there is one already. */
13464 {
13472 }
13473 /* Otherwise, if this register is used by I3, then this register
13474 now dies here, so we must put a REG_DEAD note here unless there
13475 is one already. */
13481 {
13484 }
13490 /* These notes say something about results of an insn. We can
13491 only support them if they used to be on I3 in which case they
13492 remain on I3. Otherwise they are ignored.
13494 If the note refers to an expression that is not a constant, we
13495 must also ignore the note since we cannot tell whether the
13496 equivalence is still true. It might be possible to do
13497 slightly better than this (we only have a problem if I2DEST
13498 or I1DEST is present in the expression), but it doesn't
13499 seem worth the trouble. */
13507 /* These notes say something about how a register is used. They must
13508 be present on any use of the register in I2 or I3. */
13513 {
13516 else
13518 }
13523 /* This can show up in several ways -- either directly in the
13524 pattern, or hidden off in the constant pool with (or without?)
13525 a REG_EQUAL note. */
13526 /* ??? Ignore the without-reg_equal-note problem for now. */
13538 {
13541 else
13543 }
13545 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13546 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13547 there. */
13552 {
13559 }
13565 {
13573 }
13577 /* This note says something about the value of a register prior
13578 to the execution of an insn. It is too much trouble to see
13579 if the note is still correct in all situations. It is better
13580 to simply delete it. */
13584 /* If we replaced the right hand side of FROM_INSN with a
13585 REG_EQUAL note, the original use of the dying register
13586 will not have been combined into I3 and I2. In such cases,
13587 FROM_INSN is guaranteed to be the first of the combined
13588 instructions, so we simply need to search back before
13589 FROM_INSN for the previous use or set of this register,
13590 then alter the notes there appropriately.
13592 If the register is used as an input in I3, it dies there.
13593 Similarly for I2, if it is nonzero and adjacent to I3.
13595 If the register is not used as an input in either I3 or I2
13596 and it is not one of the registers we were supposed to eliminate,
13597 there are two possibilities. We might have a non-adjacent I2
13598 or we might have somehow eliminated an additional register
13599 from a computation. For example, we might have had A & B where
13600 we discover that B will always be zero. In this case we will
13601 eliminate the reference to A.
13603 In both cases, we must search to see if we can find a previous
13604 use of A and put the death note there. */
13610 else
13611 {
13622 && !(i2mod
13624 i2mod_old_rhs)))
13629 }
13632 {
13636 {
13638 {
13642 }
13644 /* If the register is being set at TEM_INSN, see if that is all
13645 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
13646 into a REG_UNUSED note instead. Don't delete sets to
13647 global register vars. */
13651 {
13654 #ifdef HAVE_cc0
13656 #endif
13664 ;
13666 /* Verify that it was the set, and not a clobber that
13667 modified the register.
13669 CC0 targets must be careful to maintain setter/user
13670 pairs. If we cannot delete the setter due to side
13671 effects, mark the user with an UNUSED note instead
13672 of deleting it. */
13676 #ifdef HAVE_cc0
13680 #endif
13681 )
13682 {
13683 /* Move the notes and links of TEM_INSN elsewhere.
13684 This might delete other dead insns recursively.
13685 First set the pattern to something that won't use
13686 any register. */
13700 #ifdef HAVE_cc0
13701 /* Delete the setter too. */
13703 {
13716 }
13717 #endif
13718 }
13719 else
13720 {
13723 /* If there isn't already a REG_UNUSED note, put one
13724 here. Do not place a REG_DEAD note, even if
13725 the register is also used here; that would not
13726 match the algorithm used in lifetime analysis
13727 and can cause the consistency check in the
13728 scheduler to fail. */
13733 }
13734 }
13738 {
13741 /* If we are doing a 3->2 combination, and we have a
13742 register which formerly died in i3 and was not used
13743 by i2, which now no longer dies in i3 and is used in
13744 i2 but does not die in i2, and place is between i2
13745 and i3, then we may need to move a link from place to
13746 i2. */
13748 && from_insn
13751 {
13755 }
13757 }
13761 }
13763 }
13765 /* If the register is set or already dead at PLACE, we needn't do
13766 anything with this note if it is still a REG_DEAD note.
13767 We check here if it is set at all, not if is it totally replaced,
13768 which is what `dead_or_set_p' checks, so also check for it being
13769 set partially. */
13772 {
13778 {
13779 /* Unless the register previously died in PLACE, clear
13780 last_death. [I no longer understand why this is
13781 being done.] */
13785 }
13786 else
13789 /* If this is a death note for a hard reg that is occupying
13790 multiple registers, ensure that we are still using all
13791 parts of the object. If we find a piece of the object
13792 that is unused, we must arrange for an appropriate REG_DEAD
13793 note to be added for it. However, we can't just emit a USE
13794 and tag the note to it, since the register might actually
13795 be dead; so we recourse, and the recursive call then finds
13796 the previous insn that used this register. */
13800 {
13809 {
13812 }
13815 {
13816 /* Put only REG_DEAD notes for pieces that are
13817 not already dead or set. */
13821 {
13828 {
13830 NULL_RTX);
13834 NULL_RTX);
13835 }
13841 {
13843 {
13847 }
13851 {
13854 }
13855 }
13856 }
13859 }
13860 }
13861 }
13865 /* Any other notes should not be present at this point in the
13866 compilation. */
13868 }
13871 {
13874 }
13878 }
13879 }
13880 \f
13881 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13882 I3, I2, and I1 to new locations. This is also called to add a link
13883 pointing at I3 when I3's destination is changed. */
13885 static void
13887 {
13891 {
13898 /* If the insn that this link points to is a NOTE, ignore it. */
13907 {
13910 {
13926 }
13929 }
13930 else
13940 /* A LOG_LINK is defined as being placed on the first insn that uses
13941 a register and points to the insn that sets the register. Start
13942 searching at the next insn after the target of the link and stop
13943 when we reach a set of the register or the end of the basic block.
13945 Note that this correctly handles the link that used to point from
13946 I3 to I2. Also note that not much searching is typically done here
13947 since most links don't point very far away. */
13956 {
13960 }
13963 {
13966 }
13970 /* If we found a place to put the link, place it there unless there
13971 is already a link to the same insn as LINK at that point. */
13974 {
13982 {
13986 /* Set added_links_insn to the earliest insn we added a
13987 link to. */
13991 }
13992 }
13993 }
13994 }
13995 \f
13996 /* Check for any register or memory mentioned in EQUIV that is not
13997 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
13998 of EXPR where some registers may have been replaced by constants. */
14000 static bool
14002 {
14005 {
14010 }
14012 }
14013 \f
14014 DEBUG_FUNCTION void
14016 {
14017 fprintf
14019 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
14021 }
14023 void
14025 {
14026 fprintf
14028 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
14030 }
14031 \f
14032 /* Try combining insns through substitution. */
14033 static unsigned int
14035 {
14044 rebuild_jump_labels_after_combine
14047 /* Combining insns may have turned an indirect jump into a
14048 direct jump. Rebuild the JUMP_LABEL fields of jumping
14049 instructions. */
14051 {
14056 }
14060 }
14065 {
14075 };
14078 {
14082 {}
14084 /* opt_pass methods: */
14087 {
14089 }
14095 rtl_opt_pass *
14097 {
14099 }