| blob | e616c57aa7ef8ba8d3ae860fb326ae2780e321c2 |
1 ;; Machine description for Sunplus S+CORE
2 ;; Copyright (C) 2005, 2007
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Sunnorth.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; any later version.
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24 ; branch conditional branch
25 ; jump unconditional jump
26 ; call unconditional call
27 ; load load instruction(s)
28 ; store store instruction(s)
29 ; cmp integer compare
30 ; arith integer arithmetic instruction
31 ; move data movement within same register set
32 ; const load constant
33 ; nop no operation
34 ; mul integer multiply
35 ; div integer divide
36 ; cndmv conditional moves
37 ; fce transfer from hi/lo registers
38 ; tce transfer to hi/lo registers
39 ; fsr transfer from special registers
40 ; tsr transfer to special registers
42 (define_constants
43 [(CC_REGNUM 33)
44 (T_REGNUM 34)
45 (RA_REGNUM 3)
46 (SP_REGNUM 0)
47 (AT_REGNUM 1)
48 (FP_REGNUM 2)
49 (RT_REGNUM 4)
50 (GP_REGNUM 28)
51 (EH_REGNUM 29)
52 (HI_REGNUM 48)
53 (LO_REGNUM 49)
54 (CN_REGNUM 50)
55 (LC_REGNUM 51)
56 (SC_REGNUM 52)])
58 (define_constants
59 [(BITTST 0)
60 (CPLOAD 1)
61 (CPRESTORE 2)
63 (SCB 3)
64 (SCW 4)
65 (SCE 5)
66 (SCLC 6)
68 (LCB 7)
69 (LCW 8)
70 (LCE 9)
72 (SFFS 10)])
74 (define_attr "type"
75 "unknown,branch,jump,call,load,store,cmp,arith,move,const,nop,mul,div,cndmv,fce,tce,fsr,tsr,fcr,tcr"
76 (const_string "unknown"))
78 (define_attr "mode" "unknown,QI,HI,SI,DI"
79 (const_string "unknown"))
81 (define_attr "length" "" (const_int 4))
83 (define_attr "up_c" "yes,no"
84 (const_string "no"))
86 (include "score-generic.md")
87 (include "predicates.md")
89 (define_expand "movqi"
90 [(set (match_operand:QI 0 "nonimmediate_operand")
91 (match_operand:QI 1 "general_operand"))]
92 ""
93 {
94 if (MEM_P (operands[0])
95 && !register_operand (operands[1], QImode))
96 {
97 operands[1] = force_reg (QImode, operands[1]);
98 }
99 })
101 (define_insn "*movqi_insns_score7"
102 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a")
103 (match_operand:QI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))]
104 "(!MEM_P (operands[0]) || register_operand (operands[1], QImode))
105 && (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
106 {
107 switch (which_alternative)
108 {
109 case 0: return score_limm (operands);
110 case 1: return score_move (operands);
111 case 2: return score_linsn (operands, SCORE_BYTE, false);
112 case 3: return score_sinsn (operands, SCORE_BYTE);
113 case 4: return TARGET_SCORE7D ? \"mf%1%S0 %0\" : \"mf%1 %0\";
114 case 5: return TARGET_SCORE7D ? \"mt%0%S1 %1\" : \"mt%0 %1\";
115 case 6: return \"mfsr\t%0, %1\";
116 case 7: return \"mtsr\t%1, %0\";
117 default: gcc_unreachable ();
118 }
119 }
120 [(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr")
121 (set_attr "mode" "QI")])
123 (define_insn "*movqi_insns_score3"
124 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a")
125 (match_operand:QI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))]
126 "(!MEM_P (operands[0]) || register_operand (operands[1], QImode))
127 && (TARGET_SCORE3)"
128 {
129 switch (which_alternative)
130 {
131 case 0: return score_limm (operands);
132 case 1: return \"mv!\t%0, %1\";
133 case 2: return score_linsn (operands, SCORE_BYTE, false);
134 case 3: return score_sinsn (operands, SCORE_BYTE);
135 case 4: return TARGET_SCORE3D ? \"mf%1%S0\t%0\" : \"mf%1\t%0\";
136 case 5: return TARGET_SCORE3D ? \"mt%0%S1\t%1\" : \"mt%0\t%1\";
137 case 6: return \"mfsr\t%0, %1\";
138 case 7: return \"mtsr\t%1, %0\";
139 default: gcc_unreachable ();
140 }
141 }
142 [(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr")
143 (set_attr "length" "6,2,6,6,4,4,4,4")
144 (set_attr "mode" "QI")])
146 (define_expand "movhi"
147 [(set (match_operand:HI 0 "nonimmediate_operand")
148 (match_operand:HI 1 "general_operand"))]
149 ""
150 {
151 if (MEM_P (operands[0])
152 && !register_operand (operands[1], HImode))
153 {
154 operands[1] = force_reg (HImode, operands[1]);
155 }
156 })
158 (define_insn "*movhi_insns_score7"
159 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a")
160 (match_operand:HI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))]
161 "(!MEM_P (operands[0]) || register_operand (operands[1], HImode))
162 && (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
163 {
164 switch (which_alternative)
165 {
166 case 0: return score_limm (operands);
167 case 1: return score_move (operands);
168 case 2: return score_linsn (operands, SCORE_HWORD, false);
169 case 3: return score_sinsn (operands, SCORE_HWORD);
170 case 4: return TARGET_SCORE7D ? \"mf%1%S0 %0\" : \"mf%1 %0\";
171 case 5: return TARGET_SCORE7D ? \"mt%0%S1 %1\" : \"mt%0 %1\";
172 case 6: return \"mfsr\t%0, %1\";
173 case 7: return \"mtsr\t%1, %0\";
174 default: gcc_unreachable ();
175 }
176 }
177 [(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr")
178 (set_attr "mode" "HI")])
180 (define_insn "*movhi_insns_score3"
181 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a")
182 (match_operand:HI 1 "general_operand" "i,d,m,d,*x,d,*a,d"))]
183 "(!MEM_P (operands[0]) || register_operand (operands[1], HImode))
184 && (TARGET_SCORE3)"
185 {
186 switch (which_alternative)
187 {
188 case 0: return score_limm (operands);
189 case 1: return \"mv!\t%0, %1\";
190 case 2: return score_linsn (operands, SCORE_HWORD, false);
191 case 3: return score_sinsn (operands, SCORE_HWORD);
192 case 4: return TARGET_SCORE3D ? \"mf%1%S0\t%0\" : \"mf%1\t%0\";
193 case 5: return TARGET_SCORE3D ? \"mt%0%S1\t%1\" : \"mt%0\t%1\";
194 case 6: return \"mfsr\t%0, %1\";
195 case 7: return \"mtsr\t%1, %0\";
196 default: gcc_unreachable ();
197 }
198 }
199 [(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr")
200 (set_attr "length" "6,2,6,6,4,4,4,4")
201 (set_attr "mode" "HI")])
203 (define_expand "movsi"
204 [(set (match_operand:SI 0 "nonimmediate_operand")
205 (match_operand:SI 1 "general_operand"))]
206 ""
207 {
208 if (MEM_P (operands[0])
209 && !register_operand (operands[1], SImode))
210 {
211 operands[1] = force_reg (SImode, operands[1]);
212 }
213 })
215 (define_insn "*movsi_insns_score7"
216 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,m,d,*x,d,*a,d,*c")
217 (match_operand:SI 1 "general_operand" "i,d,m,d,*x,d,*a,d,*c,d"))]
218 "(!MEM_P (operands[0]) || register_operand (operands[1], SImode))
219 && (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
220 {
221 switch (which_alternative)
222 {
223 case 0:
224 if (GET_CODE (operands[1]) != CONST_INT)
225 return \"la\t%0, %1\";
226 else
227 return score_limm (operands);
228 case 1: return score_move (operands);
229 case 2: return score_linsn (operands, SCORE_WORD, false);
230 case 3: return score_sinsn (operands, SCORE_WORD);
231 case 4: return TARGET_SCORE7D ? \"mf%1%S0 %0\" : \"mf%1 %0\";
232 case 5: return TARGET_SCORE7D ? \"mt%0%S1 %1\" : \"mt%0 %1\";
233 case 6: return \"mfsr\t%0, %1\";
234 case 7: return \"mtsr\t%1, %0\";
235 case 8: return \"mfcr\t%0, %1\";
236 case 9: return \"mtcr\t%1, %0\";
237 default: gcc_unreachable ();
238 }
239 }
240 [(set_attr "type" "arith,move,load,store,fce,tce,fsr,tsr,fcr,tcr")
241 (set_attr "mode" "SI")])
243 (define_insn "*movsi_insns_score3"
244 [(set (match_operand:SI 0 "nonimmediate_operand" "=ed,e,d,d,m,d,*x,d,*a")
245 (match_operand:SI 1 "general_operand" "i,e,d,m,d,*x,d,*a,d"))]
246 "(!MEM_P (operands[0]) || register_operand (operands[1], SImode))
247 && (TARGET_SCORE3)"
248 {
249 switch (which_alternative)
250 {
251 case 0:
252 if (GET_CODE (operands[1]) != CONST_INT)
253 return \"ldi48\t%0, %1\";
254 else
255 return score_limm (operands);
256 case 1: return \"mv!\t%0, %1\";
257 case 2: return \"mv!\t%0, %1\";
258 case 3: return score_linsn (operands, SCORE_WORD, false);
259 case 4: return score_sinsn (operands, SCORE_WORD);
260 case 5: return TARGET_SCORE3D ? \"mf%1%S0\t%0\" : \"mf%1\t%0\";
261 case 6: return TARGET_SCORE3D ? \"mt%0%S1\t%1\" : \"mt%0\t%1\";
262 case 7: return \"mfsr\t%0, %1\";
263 case 8: return \"mtsr\t%1, %0\";
264 default: gcc_unreachable ();
265 }
266 }
267 [(set_attr "type" "arith,move,move,load,store,fce,tce,fsr,tsr")
268 (set_attr "length" "6,2,2,6,6,4,4,4,4")
269 (set_attr "mode" "SI")])
271 (define_insn_and_split "movdi"
272 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,d,*x")
273 (match_operand:DI 1 "general_operand" "i,d,m,d,*x,d"))]
274 ""
275 "#"
276 "reload_completed"
277 [(const_int 0)]
278 {
279 score_movdi (operands);
280 DONE;
281 })
283 (define_expand "movsf"
284 [(set (match_operand:SF 0 "nonimmediate_operand")
285 (match_operand:SF 1 "general_operand"))]
286 ""
287 {
288 if (MEM_P (operands[0])
289 && !register_operand (operands[1], SFmode))
290 {
291 operands[1] = force_reg (SFmode, operands[1]);
292 }
293 })
295 (define_insn "*movsf_insns_score7"
296 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,m")
297 (match_operand:SF 1 "general_operand" "i,d,m,d"))]
298 "(!MEM_P (operands[0]) || register_operand (operands[1], SFmode))
299 && (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
300 {
301 switch (which_alternative)
302 {
303 case 0: return \"li\t%0, %D1\";;
304 case 1: return score_move (operands);
305 case 2: return score_linsn (operands, SCORE_WORD, false);
306 case 3: return score_sinsn (operands, SCORE_WORD);
307 default: gcc_unreachable ();
308 }
309 }
310 [(set_attr "type" "arith,move,load,store")
311 (set_attr "mode" "SI")])
313 (define_insn "*movsf_insns_score3"
314 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,m")
315 (match_operand:SF 1 "general_operand" "i,d,m,d"))]
316 "(!MEM_P (operands[0]) || register_operand (operands[1], SFmode))
317 && (TARGET_SCORE3)"
318 {
319 switch (which_alternative)
320 {
321 case 0: return \"li\t%0, %D1\";
322 case 1: return \"mv!\t%0, %1\";
323 case 2: return score_linsn (operands, SCORE_WORD, false);
324 case 3: return score_sinsn (operands, SCORE_WORD);
325 default: gcc_unreachable ();
326 }
327 }
328 [(set_attr "type" "arith,move,load,store")
329 (set_attr "length" "4,2,6,6")
330 (set_attr "mode" "SI")])
332 (define_insn_and_split "movdf"
333 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,m")
334 (match_operand:DF 1 "general_operand" "i,d,m,d"))]
335 ""
336 "#"
337 "reload_completed"
338 [(const_int 0)]
339 {
340 score_movdi (operands);
341 DONE;
342 })
344 (define_expand "addsi3"
345 [(set (match_operand:SI 0 "score_register_operand" )
346 (plus:SI (match_operand:SI 1 "score_register_operand")
347 (match_operand:SI 2 "arith_operand")))]
348 ""
349 ""
350 )
352 (define_insn "*addsi3_score7"
353 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
354 (plus:SI (match_operand:SI 1 "register_operand" "0,0,d,d")
355 (match_operand:SI 2 "arith_operand" "I,L,N,d")))]
356 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
357 {
358 switch (which_alternative)
359 {
360 case 0: return \"addis\t%0, %U2\";
361 case 1: return score_select_add_imm (operands, false);
362 case 2: return \"addri\t%0, %1, %c2\";
363 case 3: return score_select (operands, "add", true, "", false);
364 default: gcc_unreachable ();
365 }
366 }
367 [(set_attr "type" "arith")
368 (set_attr "mode" "SI")])
370 (define_insn "*addsi3_score3"
371 [(set (match_operand:SI 0 "score_register_operand" "=d,d,d,d")
372 (plus:SI (match_operand:SI 1 "score_register_operand" "%0,0,d,d")
373 (match_operand:SI 2 "arith_operand" "I,L,N,d")))]
374 "(TARGET_SCORE3)"
375 {
376 switch (which_alternative)
377 {
378 case 0: return \"addis\t%0, %U2\";
379 case 1: return score_select_add_imm (operands, false);
380 case 2: return \"addri\t%0, %1, %c2\";
381 case 3: return score_select (operands, "add", true, "", false);
382 default: gcc_unreachable ();
383 }
384 }
385 [(set_attr "type" "arith")
386 (set_attr "length" "4,4,4,4")
387 (set_attr "mode" "SI")])
389 (define_insn "*addsi3_cmp_score7"
390 [(set (reg:CC_NZ CC_REGNUM)
391 (compare:CC_NZ (plus:SI
392 (match_operand:SI 1 "register_operand" "0,0,d,d")
393 (match_operand:SI 2 "arith_operand" "I,L,N,d"))
394 (const_int 0)))
395 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
396 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
397 {
398 switch (which_alternative)
399 {
400 case 0: return \"addis.c\t%0, %U2\";
401 case 1: return score_select_add_imm (operands, true);
402 case 2: return \"addri.c\t%0, %1, %c2\";
403 case 3: return score_select (operands, "add", true, "", true);
404 default: gcc_unreachable ();
405 }
406 }
407 [(set_attr "type" "arith")
408 (set_attr "up_c" "yes")
409 (set_attr "mode" "SI")])
411 (define_insn "*addsi3_cmp_score3"
412 [(set (reg:CC_NZ CC_REGNUM)
413 (compare:CC_NZ (plus:SI
414 (match_operand:SI 1 "score_register_operand" "0,0,d,d")
415 (match_operand:SI 2 "arith_operand" "I,L,N,d"))
416 (const_int 0)))
417 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
418 "(TARGET_SCORE3)"
419 {
420 switch (which_alternative)
421 {
422 case 0: return \"addis.c\t%0, %U2\";
423 case 1: return score_select_add_imm (operands, true);
424 case 2: return \"addri.c\t%0, %1, %c2\";
425 case 3: return score_select (operands, "add", true, "", true);
426 default: gcc_unreachable ();
427 }
428 }
429 [(set_attr "type" "arith")
430 (set_attr "length" "4,4,4,4")
431 (set_attr "up_c" "yes")
432 (set_attr "mode" "SI")])
434 (define_insn "*addsi3_ucc_score7"
435 [(set (reg:CC_NZ CC_REGNUM)
436 (compare:CC_NZ (plus:SI
437 (match_operand:SI 1 "register_operand" "0,0,d,d")
438 (match_operand:SI 2 "arith_operand" "I,L,N,d"))
439 (const_int 0)))
440 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
441 (plus:SI (match_dup 1) (match_dup 2)))]
442 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
443 {
444 switch (which_alternative)
445 {
446 case 0: return \"addis.c\t%0, %U2\";
447 case 1: return score_select_add_imm (operands, true);
448 case 2: return \"addri.c\t%0, %1, %c2\";
449 case 3: return score_select (operands, "add", true, "", true);
450 default: gcc_unreachable ();
451 }
452 }
453 [(set_attr "type" "arith")
454 (set_attr "up_c" "yes")
455 (set_attr "mode" "SI")])
457 (define_insn "*addsi3_ucc_score3"
458 [(set (reg:CC_NZ CC_REGNUM)
459 (compare:CC_NZ (plus:SI
460 (match_operand:SI 1 "score_register_operand" "0,0,d,d")
461 (match_operand:SI 2 "arith_operand" "I,L,N,d"))
462 (const_int 0)))
463 (set (match_operand:SI 0 "score_register_operand" "=d,d,d,d")
464 (plus:SI (match_dup 1) (match_dup 2)))]
465 "(TARGET_SCORE3)"
466 {
467 switch (which_alternative)
468 {
469 case 0: return \"addis.c\t%0, %U2\";
470 case 1: return score_select_add_imm (operands, true);
471 case 2: return \"addri.c\t%0, %1, %c2\";
472 case 3: return score_select (operands, "add", true, "", true);
473 default: gcc_unreachable ();
474 }
475 }
476 [(set_attr "type" "arith")
477 (set_attr "length" "4,4,4,4")
478 (set_attr "up_c" "yes")
479 (set_attr "mode" "SI")])
481 (define_expand "adddi3"
482 [(parallel
483 [(set (match_operand:DI 0 "score_register_operand")
484 (plus:DI (match_operand:DI 1 "score_register_operand")
485 (match_operand:DI 2 "score_register_operand")))
486 (clobber (reg:CC CC_REGNUM))])]
487 ""
488 ""
489 )
491 (define_insn "*adddi3_score7"
492 [(set (match_operand:DI 0 "register_operand" "=e,d")
493 (plus:DI (match_operand:DI 1 "register_operand" "0,d")
494 (match_operand:DI 2 "register_operand" "e,d")))
495 (clobber (reg:CC CC_REGNUM))]
496 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
497 "@
498 add! %L0, %L2\;addc! %H0, %H2
499 add.c %L0, %L1, %L2\;addc %H0, %H1, %H2"
500 [(set_attr "type" "arith")
501 (set_attr "mode" "DI")])
503 (define_insn "*adddi3_score3"
504 [(set (match_operand:DI 0 "score_register_operand" "=d")
505 (plus:DI (match_operand:DI 1 "score_register_operand" "d")
506 (match_operand:DI 2 "score_register_operand" "d")))
507 (clobber (reg:CC CC_REGNUM))]
508 "(TARGET_SCORE3)"
509 "add.c\t%L0, %L1, %L2\;addc\t%H0, %H1, %H2"
510 [(set_attr "type" "arith")
511 (set_attr "length" "8")
512 (set_attr "mode" "DI")])
514 (define_expand "subsi3"
515 [(set (match_operand:SI 0 "score_register_operand")
516 (minus:SI (match_operand:SI 1 "score_register_operand")
517 (match_operand:SI 2 "score_register_operand")))]
518 ""
519 ""
520 )
522 (define_insn "*subsi3_score7"
523 [(set (match_operand:SI 0 "register_operand" "=d")
524 (minus:SI (match_operand:SI 1 "register_operand" "d")
525 (match_operand:SI 2 "register_operand" "d")))]
526 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
527 {
528 return score_select (operands, "sub", false, "", false);
529 }
530 [(set_attr "type" "arith")
531 (set_attr "mode" "SI")])
533 (define_insn "*subsi3_score3"
534 [(set (match_operand:SI 0 "score_register_operand" "=e,d")
535 (minus:SI (match_operand:SI 1 "score_register_operand" "0,d")
536 (match_operand:SI 2 "score_register_operand" "e,d")))]
537 "(TARGET_SCORE3)"
538 {
539 switch (which_alternative)
540 {
541 case 0: return \"sub!\t%0, %2\";
542 case 1: return score_select (operands, "sub", false, "", false);
543 default: gcc_unreachable ();
544 }
545 }
546 [(set_attr "type" "arith")
547 (set_attr "length" "2,4")
548 (set_attr "mode" "SI")])
550 (define_insn "*subsi3_cmp_score7"
551 [(set (reg:CC_NZ CC_REGNUM)
552 (compare:CC_NZ (minus:SI (match_operand:SI 1 "register_operand" "d")
553 (match_operand:SI 2 "register_operand" "d"))
554 (const_int 0)))
555 (clobber (match_scratch:SI 0 "=d"))]
556 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
557 {
558 return score_select (operands, "sub", false, "", true);
559 }
560 [(set_attr "type" "arith")
561 (set_attr "up_c" "yes")
562 (set_attr "mode" "SI")])
564 (define_insn "*subsi3_cmp_score3"
565 [(set (reg:CC_NZ CC_REGNUM)
566 (compare:CC_NZ (minus:SI (match_operand:SI 1 "score_register_operand" "d")
567 (match_operand:SI 2 "score_register_operand" "d"))
568 (const_int 0)))
569 (clobber (match_scratch:SI 0 "=d"))]
570 "(TARGET_SCORE3)"
571 {
572 return score_select (operands, "sub", false, "", true);
573 }
574 [(set_attr "type" "arith")
575 (set_attr "length" "4")
576 (set_attr "up_c" "yes")
577 (set_attr "mode" "SI")])
579 (define_peephole2
580 [(set (match_operand:SI 0 "g32reg_operand" "")
581 (minus:SI (match_operand:SI 1 "g32reg_operand" "")
582 (match_operand:SI 2 "g32reg_operand" "")))
583 (set (reg:CC CC_REGNUM)
584 (compare:CC (match_dup 1) (match_dup 2)))]
585 ""
586 [(set (reg:CC CC_REGNUM)
587 (compare:CC (match_dup 1) (match_dup 2)))
588 (set (match_dup 0)
589 (minus:SI (match_dup 1) (match_dup 2)))])
591 (define_insn "subsi3_ucc_pcmp"
592 [(parallel
593 [(set (reg:CC CC_REGNUM)
594 (compare:CC (match_operand:SI 1 "score_register_operand" "d")
595 (match_operand:SI 2 "score_register_operand" "d")))
596 (set (match_operand:SI 0 "score_register_operand" "=d")
597 (minus:SI (match_dup 1) (match_dup 2)))])]
598 ""
599 {
600 return score_select (operands, "sub", false, "", true);
601 }
602 [(set_attr "type" "arith")
603 (set_attr "length" "4")
604 (set_attr "up_c" "yes")
605 (set_attr "mode" "SI")])
607 (define_insn "subsi3_ucc"
608 [(set (reg:CC_NZ CC_REGNUM)
609 (compare:CC_NZ (minus:SI (match_operand:SI 1 "score_register_operand" "d")
610 (match_operand:SI 2 "score_register_operand" "d"))
611 (const_int 0)))
612 (set (match_operand:SI 0 "score_register_operand" "=d")
613 (minus:SI (match_dup 1) (match_dup 2)))]
614 ""
615 {
616 return score_select (operands, "sub", false, "", true);
617 }
618 [(set_attr "type" "arith")
619 (set_attr "length" "4")
620 (set_attr "up_c" "yes")
621 (set_attr "mode" "SI")])
623 (define_expand "subdi3"
624 [(parallel
625 [(set (match_operand:DI 0 "score_register_operand")
626 (minus:DI (match_operand:DI 1 "score_register_operand")
627 (match_operand:DI 2 "score_register_operand")))
628 (clobber (reg:CC CC_REGNUM))])]
629 ""
630 ""
631 )
633 (define_insn "*subdi3_score7"
634 [(set (match_operand:DI 0 "register_operand" "=e,d")
635 (minus:DI (match_operand:DI 1 "register_operand" "0,d")
636 (match_operand:DI 2 "register_operand" "e,d")))
637 (clobber (reg:CC CC_REGNUM))]
638 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
639 "@
640 sub! %L0, %L2\;subc %H0, %H1, %H2
641 sub.c %L0, %L1, %L2\;subc %H0, %H1, %H2"
642 [(set_attr "type" "arith")
643 (set_attr "mode" "DI")])
645 (define_insn "*subdi3_score3"
646 [(set (match_operand:DI 0 "score_register_operand" "=d")
647 (minus:DI (match_operand:DI 1 "score_register_operand" "d")
648 (match_operand:DI 2 "score_register_operand" "d")))
649 (clobber (reg:CC CC_REGNUM))]
650 "(TARGET_SCORE3)"
651 "sub.c\t%L0, %L1, %L2\;subc\t%H0, %H1, %H2"
652 [(set_attr "type" "arith")
653 (set_attr "length" "8")
654 (set_attr "mode" "DI")])
656 (define_expand "andsi3"
657 [(set (match_operand:SI 0 "score_register_operand")
658 (and:SI (match_operand:SI 1 "score_register_operand")
659 (match_operand:SI 2 "arith_operand")))]
660 ""
661 ""
662 )
664 (define_insn "*andsi3_score7"
665 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
666 (and:SI (match_operand:SI 1 "register_operand" "0,0,d,d")
667 (match_operand:SI 2 "arith_operand" "I,K,M,d")))]
668 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
669 {
670 switch (which_alternative)
671 {
672 case 0: return \"andis\t%0, %U2\";
673 case 1: return \"andi\t%0, %c2";
674 case 2: return \"andri\t%0, %1, %c2\";
675 case 3: return score_select (operands, "and", true, "", false);
676 default: gcc_unreachable ();
677 }
678 }
679 [(set_attr "type" "arith")
680 (set_attr "mode" "SI")])
682 (define_insn "*andsi3_score3"
683 [(set (match_operand:SI 0 "score_register_operand" "=e,d,d,d,d")
684 (and:SI (match_operand:SI 1 "score_register_operand" "%0,0,0,d,d")
685 (match_operand:SI 2 "arith_operand" "e,I,K,M,d")))]
686 "(TARGET_SCORE3)"
687 {
688 switch (which_alternative)
689 {
690 case 0: return \"and!\t%0, %2\";
691 case 1: return \"andis\t%0, %U2\";
692 case 2: return \"andi\t%0, %c2";
693 case 3: return \"andri\t%0, %1, %c2\";
694 case 4: return score_select (operands, "and", true, "", false);
695 default: gcc_unreachable ();
696 }
697 }
698 [(set_attr "type" "arith")
699 (set_attr "length" "2,4,4,4,4")
700 (set_attr "mode" "SI")])
702 (define_insn "andsi3_cmp_score7"
703 [(set (reg:CC_NZ CC_REGNUM)
704 (compare:CC_NZ (and:SI (match_operand:SI 1 "register_operand" "0,0,0,d")
705 (match_operand:SI 2 "arith_operand" "I,K,M,d"))
706 (const_int 0)))
707 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
708 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
709 {
710 switch (which_alternative)
711 {
712 case 0: return \"andis.c\t%0, %U2\";
713 case 1: return \"andi.c\t%0, %c2";
714 case 2: return \"andri.c\t%0, %1, %c2\";
715 case 3: return score_select (operands, "and", true, "", true);
716 default: gcc_unreachable ();
717 }
718 }
719 [(set_attr "type" "arith")
720 (set_attr "up_c" "yes")
721 (set_attr "mode" "SI")])
723 (define_insn "andsi3_cmp_score3"
724 [(set (reg:CC_NZ CC_REGNUM)
725 (compare:CC_NZ (and:SI (match_operand:SI 1 "score_register_operand" "0,0,0,d")
726 (match_operand:SI 2 "arith_operand" "I,K,M,d"))
727 (const_int 0)))
728 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
729 ""
730 {
731 switch (which_alternative)
732 {
733 case 0: return \"andis.c\t%0, %U2\";
734 case 1: return \"andi.c\t%0, %c2";
735 case 2: return \"andri.c\t%0, %1, %c2\";
736 case 3: return score_select (operands, "and", true, "", true);
737 default: gcc_unreachable ();
738 }
739 }
740 [(set_attr "type" "arith")
741 (set_attr "length" "4,4,4,4")
742 (set_attr "up_c" "yes")
743 (set_attr "mode" "SI")])
745 (define_insn "*andsi3_ucc_score7"
746 [(set (reg:CC_NZ CC_REGNUM)
747 (compare:CC_NZ (and:SI
748 (match_operand:SI 1 "register_operand" "0,0,d,d")
749 (match_operand:SI 2 "arith_operand" "I,K,M,d"))
750 (const_int 0)))
751 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
752 (and:SI (match_dup 1) (match_dup 2)))]
753 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
754 {
755 switch (which_alternative)
756 {
757 case 0: return \"andis.c\t%0, %U2\";
758 case 1: return \"andi.c\t%0, %c2";
759 case 2: return \"andri.c\t%0, %1, %c2\";
760 case 3: return score_select (operands, "and", true, "", true);
761 default: gcc_unreachable ();
762 }
763 }
764 [(set_attr "type" "arith")
765 (set_attr "up_c" "yes")
766 (set_attr "mode" "SI")])
768 (define_insn "*andsi3_ucc_score3"
769 [(set (reg:CC_NZ CC_REGNUM)
770 (compare:CC_NZ (and:SI
771 (match_operand:SI 1 "score_register_operand" "0,0,d,d")
772 (match_operand:SI 2 "arith_operand" "I,K,M,d"))
773 (const_int 0)))
774 (set (match_operand:SI 0 "score_register_operand" "=d,d,d,d")
775 (and:SI (match_dup 1) (match_dup 2)))]
776 "(TARGET_SCORE3)"
777 {
778 switch (which_alternative)
779 {
780 case 0: return \"andis.c\t%0, %U2\";
781 case 1: return \"andi.c\t%0, %c2";
782 case 2: return \"andri.c\t%0, %1, %c2\";
783 case 3: return score_select (operands, "and", true, "", true);
784 default: gcc_unreachable ();
785 }
786 }
787 [(set_attr "type" "arith")
788 (set_attr "length" "4,4,4,4")
789 (set_attr "up_c" "yes")
790 (set_attr "mode" "SI")])
793 (define_insn_and_split "*zero_extract_andi"
794 [(set (reg:CC CC_REGNUM)
795 (compare:CC (zero_extract:SI
796 (match_operand:SI 0 "score_register_operand" "d")
797 (match_operand:SI 1 "const_uimm5" "")
798 (match_operand:SI 2 "const_uimm5" ""))
799 (const_int 0)))]
800 ""
801 "#"
802 ""
803 [(const_int 1)]
804 {
805 score_zero_extract_andi (operands);
806 DONE;
807 })
809 (define_expand "iorsi3"
810 [(set (match_operand:SI 0 "score_register_operand")
811 (ior:SI (match_operand:SI 1 "score_register_operand")
812 (match_operand:SI 2 "arith_operand")))]
813 ""
814 ""
815 )
817 (define_insn "*iorsi3_score7"
818 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
819 (ior:SI (match_operand:SI 1 "register_operand" "0,0,d,d")
820 (match_operand:SI 2 "arith_operand" "I,K,M,d")))]
821 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
822 {
823 switch (which_alternative)
824 {
825 case 0: return \"oris\t%0, %U2\";
826 case 1: return \"ori\t%0, %c2\";
827 case 2: return \"orri\t%0, %1, %c2\";
828 case 3: return score_select (operands, "or", true, "", false);
829 default: gcc_unreachable ();
830 }
831 }
832 [(set_attr "type" "arith")
833 (set_attr "mode" "SI")])
835 (define_insn "*iorsi3_score3"
836 [(set (match_operand:SI 0 "score_register_operand" "=e,d,d,d,d")
837 (ior:SI (match_operand:SI 1 "score_register_operand" "%0,0,0,d,d")
838 (match_operand:SI 2 "arith_operand" "e,I,K,M,d")))]
839 "(TARGET_SCORE3)"
840 {
841 switch (which_alternative)
842 {
843 case 0: return \"or!\t%0, %2\";
844 case 1: return \"oris\t%0, %U2\";
845 case 2: return \"ori\t%0, %c2\";
846 case 3: return \"orri\t%0, %1, %c2\";
847 case 4: return score_select (operands, "or", true, "", false);
848 default: gcc_unreachable ();
849 }
850 }
851 [(set_attr "type" "arith")
852 (set_attr "length" "2,4,4,4,4")
853 (set_attr "mode" "SI")])
855 (define_insn "*iorsi3_ucc_score7"
856 [(set (reg:CC_NZ CC_REGNUM)
857 (compare:CC_NZ (ior:SI
858 (match_operand:SI 1 "register_operand" "0,0,d,d")
859 (match_operand:SI 2 "arith_operand" "I,K,M,d"))
860 (const_int 0)))
861 (set (match_operand:SI 0 "register_operand" "=d,d,d,d")
862 (ior:SI (match_dup 1) (match_dup 2)))]
863 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
864 {
865 switch (which_alternative)
866 {
867 case 0: return \"oris.c\t%0, %U2\";
868 case 1: return \"ori.c\t%0, %c2\";
869 case 2: return \"orri.c\t%0, %1, %c2\";
870 case 3: return score_select (operands, "or", true, "", true);
871 default: gcc_unreachable ();
872 }
873 }
874 [(set_attr "type" "arith")
875 (set_attr "up_c" "yes")
876 (set_attr "mode" "SI")])
878 (define_insn "*iorsi3_ucc_score3"
879 [(set (reg:CC_NZ CC_REGNUM)
880 (compare:CC_NZ (ior:SI
881 (match_operand:SI 1 "score_register_operand" "0,0,d,d")
882 (match_operand:SI 2 "arith_operand" "I,K,M,d"))
883 (const_int 0)))
884 (set (match_operand:SI 0 "score_register_operand" "=d,d,d,d")
885 (ior:SI (match_dup 1) (match_dup 2)))]
886 "(TARGET_SCORE3)"
887 {
888 switch (which_alternative)
889 {
890 case 0: return \"oris.c\t%0, %U2\";
891 case 1: return \"ori.c\t%0, %c2\";
892 case 2: return \"orri.c\t%0, %1, %c2\";
893 case 3: return score_select (operands, "or", true, "", true);
894 default: gcc_unreachable ();
895 }
896 }
897 [(set_attr "type" "arith")
898 (set_attr "length" "4,4,4,4")
899 (set_attr "up_c" "yes")
900 (set_attr "mode" "SI")])
902 (define_insn "*iorsi3_cmp_score7"
903 [(set (reg:CC_NZ CC_REGNUM)
904 (compare:CC_NZ (ior:SI
905 (match_operand:SI 1 "register_operand" "0,0,d,d")
906 (match_operand:SI 2 "arith_operand" "I,K,M,d"))
907 (const_int 0)))
908 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
909 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
910 {
911 switch (which_alternative)
912 {
913 case 0: return \"oris.c\t%0, %U2\";
914 case 1: return \"ori.c\t%0, %c2\";
915 case 2: return \"orri.c\t%0, %1, %c2\";
916 case 3: return score_select (operands, "or", true, "", true);
917 default: gcc_unreachable ();
918 }
919 }
920 [(set_attr "type" "arith")
921 (set_attr "up_c" "yes")
922 (set_attr "mode" "SI")])
924 (define_insn "*iorsi3_cmp_score3"
925 [(set (reg:CC_NZ CC_REGNUM)
926 (compare:CC_NZ (ior:SI
927 (match_operand:SI 1 "score_register_operand" "0,0,d,d")
928 (match_operand:SI 2 "arith_operand" "I,K,M,d"))
929 (const_int 0)))
930 (clobber (match_scratch:SI 0 "=d,d,d,d"))]
931 "(TARGET_SCORE3)"
932 {
933 switch (which_alternative)
934 {
935 case 0: return \"oris.c\t%0, %U2\";
936 case 1: return \"ori.c\t%0, %c2\";
937 case 2: return \"orri.c\t%0, %1, %c2\";
938 case 3: return score_select (operands, "or", true, "", true);
939 default: gcc_unreachable ();
940 }
941 }
942 [(set_attr "type" "arith")
943 (set_attr "length" "4,4,4,4")
944 (set_attr "up_c" "yes")
945 (set_attr "mode" "SI")])
947 (define_expand "xorsi3"
948 [(set (match_operand:SI 0 "score_register_operand")
949 (xor:SI (match_operand:SI 1 "score_register_operand")
950 (match_operand:SI 2 "score_register_operand")))]
951 ""
952 ""
953 )
955 (define_insn "*xorsi3_score7"
956 [(set (match_operand:SI 0 "register_operand" "=d")
957 (xor:SI (match_operand:SI 1 "register_operand" "d")
958 (match_operand:SI 2 "register_operand" "d")))]
959 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
960 {
961 return score_select (operands, "xor", true, "", false);
962 }
963 [(set_attr "type" "arith")
964 (set_attr "mode" "SI")])
966 (define_insn "*xorsi3_score3"
967 [(set (match_operand:SI 0 "score_register_operand" "=d")
968 (xor:SI (match_operand:SI 1 "score_register_operand" "d")
969 (match_operand:SI 2 "score_register_operand" "d")))]
970 "(TARGET_SCORE3)"
971 {
972 return score_select (operands, "xor", true, "", false);
973 }
974 [(set_attr "type" "arith")
975 (set_attr "length" "4")
976 (set_attr "mode" "SI")])
979 (define_insn "*xorsi3_ucc_score7"
980 [(set (reg:CC_NZ CC_REGNUM)
981 (compare:CC_NZ (xor:SI (match_operand:SI 1 "register_operand" "d")
982 (match_operand:SI 2 "register_operand" "d"))
983 (const_int 0)))
984 (set (match_operand:SI 0 "register_operand" "=d")
985 (xor:SI (match_dup 1) (match_dup 2)))]
986 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
987 {
988 return score_select (operands, "xor", true, "", true);
989 }
990 [(set_attr "type" "arith")
991 (set_attr "up_c" "yes")
992 (set_attr "mode" "SI")])
994 (define_insn "*xorsi3_ucc_score3"
995 [(set (reg:CC_NZ CC_REGNUM)
996 (compare:CC_NZ (xor:SI (match_operand:SI 1 "score_register_operand" "d")
997 (match_operand:SI 2 "score_register_operand" "d"))
998 (const_int 0)))
999 (set (match_operand:SI 0 "score_register_operand" "=d")
1000 (xor:SI (match_dup 1) (match_dup 2)))]
1001 "(TARGET_SCORE3)"
1002 {
1003 return score_select (operands, "xor", true, "", true);
1004 }
1005 [(set_attr "type" "arith")
1006 (set_attr "length" "4")
1007 (set_attr "up_c" "yes")
1008 (set_attr "mode" "SI")])
1011 (define_insn "*xorsi3_cmp_score7"
1012 [(set (reg:CC_NZ CC_REGNUM)
1013 (compare:CC_NZ (xor:SI (match_operand:SI 1 "register_operand" "d")
1014 (match_operand:SI 2 "register_operand" "d"))
1015 (const_int 0)))
1016 (clobber (match_scratch:SI 0 "=d"))]
1017 ""
1018 {
1019 return score_select (operands, "xor", true, "", true);
1020 }
1021 [(set_attr "type" "arith")
1022 (set_attr "up_c" "yes")
1023 (set_attr "mode" "SI")])
1025 (define_insn "*xorsi3_cmp_score3"
1026 [(set (reg:CC_NZ CC_REGNUM)
1027 (compare:CC_NZ (xor:SI (match_operand:SI 1 "score_register_operand" "d")
1028 (match_operand:SI 2 "score_register_operand" "d"))
1029 (const_int 0)))
1030 (clobber (match_scratch:SI 0 "=d"))]
1031 ""
1032 {
1033 return score_select (operands, "xor", true, "", true);
1034 }
1035 [(set_attr "type" "arith")
1036 (set_attr "length" "4")
1037 (set_attr "up_c" "yes")
1038 (set_attr "mode" "SI")])
1040 (define_expand "extendqisi2"
1041 [(set (match_operand:SI 0 "score_register_operand")
1042 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand")))]
1043 ""
1044 ""
1045 )
1047 (define_insn "*extendqisi2_score7"
1048 [(set (match_operand:SI 0 "register_operand" "=d,d")
1049 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1050 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
1051 {
1052 switch (which_alternative)
1053 {
1054 case 0: return \"extsb\t%0, %1\";
1055 case 1: return score_linsn (operands, SCORE_BYTE, true);
1056 default: gcc_unreachable ();
1057 }
1058 }
1059 [(set_attr "type" "arith,load")
1060 (set_attr "mode" "SI")])
1062 (define_insn "*extendqisi2_score3"
1063 [(set (match_operand:SI 0 "score_register_operand" "=d,d")
1064 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1065 "(TARGET_SCORE3)"
1066 {
1067 switch (which_alternative)
1068 {
1069 case 0: return \"extsb\t%0, %1\";
1070 case 1: return score_linsn (operands, SCORE_BYTE, true);
1071 default: gcc_unreachable ();
1072 }
1073 }
1074 [(set_attr "type" "arith,load")
1075 (set_attr "length" "4,4")
1076 (set_attr "mode" "SI")])
1078 (define_insn "*extendqisi2_ucc_score7"
1079 [(set (reg:CC_N CC_REGNUM)
1080 (compare:CC_N (ashiftrt:SI
1081 (ashift:SI (match_operand:SI 1 "register_operand" "d")
1082 (const_int 24))
1083 (const_int 24))
1084 (const_int 0)))
1085 (set (match_operand:SI 0 "register_operand" "=d")
1086 (sign_extend:SI (match_operand:QI 2 "register_operand" "0")))]
1087 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
1088 "extsb.c %0, %1"
1089 [(set_attr "type" "arith")
1090 (set_attr "up_c" "yes")
1091 (set_attr "mode" "SI")])
1093 (define_insn "*extendqisi2_ucc_score3"
1094 [(set (reg:CC_N CC_REGNUM)
1095 (compare:CC_N (ashiftrt:SI
1096 (ashift:SI (match_operand:SI 1 "score_register_operand" "d")
1097 (const_int 24))
1098 (const_int 24))
1099 (const_int 0)))
1100 (set (match_operand:SI 0 "score_register_operand" "=d")
1101 (sign_extend:SI (match_operand:QI 2 "score_register_operand" "0")))]
1102 "(TARGET_SCORE3)"
1103 "extsb.c\t%0, %1"
1104 [(set_attr "type" "arith")
1105 (set_attr "length" "4")
1106 (set_attr "up_c" "yes")
1107 (set_attr "mode" "SI")])
1109 (define_insn "*extendqisi2_cmp_score7"
1110 [(set (reg:CC_N CC_REGNUM)
1111 (compare:CC_N (ashiftrt:SI
1112 (ashift:SI (match_operand:SI 1 "register_operand" "d")
1113 (const_int 24))
1114 (const_int 24))
1115 (const_int 0)))
1116 (clobber (match_scratch:SI 0 "=d"))]
1117 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
1118 "extsb.c %0, %1"
1119 [(set_attr "type" "arith")
1120 (set_attr "up_c" "yes")
1121 (set_attr "mode" "SI")])
1123 (define_insn "*extendqisi2_cmp_score3"
1124 [(set (reg:CC_N CC_REGNUM)
1125 (compare:CC_N (ashiftrt:SI
1126 (ashift:SI (match_operand:SI 1 "score_register_operand" "d")
1127 (const_int 24))
1128 (const_int 24))
1129 (const_int 0)))
1130 (clobber (match_scratch:SI 0 "=d"))]
1131 "(TARGET_SCORE3)"
1132 "extsb.c\t%0, %1"
1133 [(set_attr "type" "arith")
1134 (set_attr "length" "4")
1135 (set_attr "up_c" "yes")
1136 (set_attr "mode" "SI")])
1138 (define_expand "extendhisi2"
1139 [(set (match_operand:SI 0 "score_register_operand")
1140 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand")))]
1141 ""
1142 ""
1143 )
1145 (define_insn "*extendhisi2_score7"
1146 [(set (match_operand:SI 0 "register_operand" "=d,d")
1147 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
1148 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
1149 {
1150 switch (which_alternative)
1151 {
1152 case 0: return \"extsh\t%0, %1\";
1153 case 1: return score_linsn (operands, SCORE_HWORD, true);
1154 default: gcc_unreachable ();
1155 }
1156 }
1157 [(set_attr "type" "arith, load")
1158 (set_attr "mode" "SI")])
1160 (define_insn "*extendhisi2_score3"
1161 [(set (match_operand:SI 0 "score_register_operand" "=d,d")
1162 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
1163 "(TARGET_SCORE3)"
1164 {
1165 switch (which_alternative)
1166 {
1167 case 0: return \"extsh\t%0, %1\";
1168 case 1: return score_linsn (operands, SCORE_HWORD, true);
1169 default: gcc_unreachable ();
1170 }
1171 }
1172 [(set_attr "type" "arith, load")
1173 (set_attr "length" "4,4")
1174 (set_attr "mode" "SI")])
1176 (define_insn "*extendhisi2_ucc_score7"
1177 [(set (reg:CC_N CC_REGNUM)
1178 (compare:CC_N (ashiftrt:SI
1179 (ashift:SI (match_operand:SI 1 "register_operand" "d")
1180 (const_int 16))
1181 (const_int 16))
1182 (const_int 0)))
1183 (set (match_operand:SI 0 "register_operand" "=d")
1184 (sign_extend:SI (match_operand:HI 2 "register_operand" "0")))]
1185 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
1186 "extsh.c %0, %1"
1187 [(set_attr "type" "arith")
1188 (set_attr "up_c" "yes")
1189 (set_attr "mode" "SI")])
1191 (define_insn "*extendhisi2_ucc_score3"
1192 [(set (reg:CC_N CC_REGNUM)
1193 (compare:CC_N (ashiftrt:SI
1194 (ashift:SI (match_operand:SI 1 "score_register_operand" "d")
1195 (const_int 16))
1196 (const_int 16))
1197 (const_int 0)))
1198 (set (match_operand:SI 0 "score_register_operand" "=d")
1199 (sign_extend:SI (match_operand:HI 2 "score_register_operand" "0")))]
1200 "(TARGET_SCORE3)"
1201 "extsh.c\t%0, %1"
1202 [(set_attr "type" "arith")
1203 (set_attr "length" "4")
1204 (set_attr "up_c" "yes")
1205 (set_attr "mode" "SI")])
1207 (define_insn "*extendhisi2_cmp_score7"
1208 [(set (reg:CC_N CC_REGNUM)
1209 (compare:CC_N (ashiftrt:SI
1210 (ashift:SI (match_operand:SI 1 "register_operand" "d")
1211 (const_int 16))
1212 (const_int 16))
1213 (const_int 0)))
1214 (clobber (match_scratch:SI 0 "=d"))]
1215 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
1216 "extsh.c %0, %1"
1217 [(set_attr "type" "arith")
1218 (set_attr "up_c" "yes")
1219 (set_attr "mode" "SI")])
1221 (define_insn "*extendhisi2_cmp_score3"
1222 [(set (reg:CC_N CC_REGNUM)
1223 (compare:CC_N (ashiftrt:SI
1224 (ashift:SI (match_operand:SI 1 "score_register_operand" "d")
1225 (const_int 16))
1226 (const_int 16))
1227 (const_int 0)))
1228 (clobber (match_scratch:SI 0 "=d"))]
1229 "(TARGET_SCORE3)"
1230 "extsh.c\t%0, %1"
1231 [(set_attr "type" "arith")
1232 (set_attr "length" "4")
1233 (set_attr "up_c" "yes")
1234 (set_attr "mode" "SI")])
1236 (define_expand "zero_extendqisi2"
1237 [(set (match_operand:SI 0 "score_register_operand")
1238 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand")))]
1239 ""
1240 ""
1241 )
1243 (define_insn "*zero_extendqisi2_score7"
1244 [(set (match_operand:SI 0 "register_operand" "=d,d")
1245 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1246 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
1247 {
1248 switch (which_alternative)
1249 {
1250 case 0: return \"extzb\t%0, %1\";
1251 case 1: return score_linsn (operands, SCORE_BYTE, false);
1252 default: gcc_unreachable ();
1253 }
1254 }
1255 [(set_attr "type" "arith, load")
1256 (set_attr "mode" "SI")])
1258 (define_insn "*zero_extendqisi2_score3"
1259 [(set (match_operand:SI 0 "score_register_operand" "=d,d")
1260 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1261 "(TARGET_SCORE3)"
1262 {
1263 switch (which_alternative)
1264 {
1265 case 0: return \"extzb\t%0, %1\";
1266 case 1: return score_linsn (operands, SCORE_BYTE, false);
1267 default: gcc_unreachable ();
1268 }
1269 }
1270 [(set_attr "type" "arith, load")
1271 (set_attr "length" "4,4")
1272 (set_attr "mode" "SI")])
1274 (define_insn "*zero_extendqisi2_ucc_score7"
1275 [(set (reg:CC_N CC_REGNUM)
1276 (compare:CC_N (lshiftrt:SI
1277 (ashift:SI (match_operand:SI 1 "register_operand" "d")
1278 (const_int 24))
1279 (const_int 24))
1280 (const_int 0)))
1281 (set (match_operand:SI 0 "register_operand" "=d")
1282 (zero_extend:SI (match_operand:QI 2 "register_operand" "0")))]
1283 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
1284 "extzb.c %0, %1"
1285 [(set_attr "type" "arith")
1286 (set_attr "up_c" "yes")
1287 (set_attr "mode" "SI")])
1289 (define_insn "*zero_extendqisi2_ucc_score3"
1290 [(set (reg:CC_N CC_REGNUM)
1291 (compare:CC_N (lshiftrt:SI
1292 (ashift:SI (match_operand:SI 1 "score_register_operand" "d")
1293 (const_int 24))
1294 (const_int 24))
1295 (const_int 0)))
1296 (set (match_operand:SI 0 "score_register_operand" "=d")
1297 (zero_extend:SI (match_operand:QI 2 "score_register_operand" "0")))]
1298 "(TARGET_SCORE3)"
1299 "extzb.c\t%0, %1"
1300 [(set_attr "type" "arith")
1301 (set_attr "length" "4")
1302 (set_attr "up_c" "yes")
1303 (set_attr "mode" "SI")])
1305 (define_insn "*zero_extendqisi2_cmp_score7"
1306 [(set (reg:CC_N CC_REGNUM)
1307 (compare:CC_N (lshiftrt:SI
1308 (ashift:SI (match_operand:SI 1 "register_operand" "d")
1309 (const_int 24))
1310 (const_int 24))
1311 (const_int 0)))
1312 (clobber (match_scratch:SI 0 "=d"))]
1313 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
1314 "extzb.c %0, %1"
1315 [(set_attr "type" "arith")
1316 (set_attr "up_c" "yes")
1317 (set_attr "mode" "SI")])
1319 (define_insn "*zero_extendqisi2_cmp_score3"
1320 [(set (reg:CC_N CC_REGNUM)
1321 (compare:CC_N (lshiftrt:SI
1322 (ashift:SI (match_operand:SI 1 "score_register_operand" "d")
1323 (const_int 24))
1324 (const_int 24))
1325 (const_int 0)))
1326 (clobber (match_scratch:SI 0 "=d"))]
1327 "(TARGET_SCORE3)"
1328 "extzb.c\t%0, %1"
1329 [(set_attr "type" "arith")
1330 (set_attr "length" "4")
1331 (set_attr "up_c" "yes")
1332 (set_attr "mode" "SI")])
1334 (define_expand "zero_extendhisi2"
1335 [(set (match_operand:SI 0 "score_register_operand")
1336 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand")))]
1337 ""
1338 ""
1339 )
1341 (define_insn "*zero_extendhisi2_score7"
1342 [(set (match_operand:SI 0 "register_operand" "=d,d")
1343 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
1344 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
1345 {
1346 switch (which_alternative)
1347 {
1348 case 0: return \"extzh\t%0, %1\";
1349 case 1: return score_linsn (operands, SCORE_HWORD, false);
1350 default: gcc_unreachable ();
1351 }
1352 }
1353 [(set_attr "type" "arith, load")
1354 (set_attr "mode" "SI")])
1356 (define_insn "*zero_extendhisi2_score3"
1357 [(set (match_operand:SI 0 "score_register_operand" "=d,d")
1358 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,m")))]
1359 "(TARGET_SCORE3)"
1360 {
1361 switch (which_alternative)
1362 {
1363 case 0: return \"extzh\t%0, %1\";
1364 case 1: return score_linsn (operands, SCORE_HWORD, false);
1365 default: gcc_unreachable ();
1366 }
1367 }
1368 [(set_attr "type" "arith, load")
1369 (set_attr "length" "4,4")
1370 (set_attr "mode" "SI")])
1372 (define_insn "*zero_extendhisi2_ucc_score7"
1373 [(set (reg:CC_N CC_REGNUM)
1374 (compare:CC_N (lshiftrt:SI
1375 (ashift:SI (match_operand:SI 1 "register_operand" "d")
1376 (const_int 16))
1377 (const_int 16))
1378 (const_int 0)))
1379 (set (match_operand:SI 0 "register_operand" "=d")
1380 (zero_extend:SI (match_operand:HI 2 "register_operand" "0")))]
1381 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
1382 "extzh.c %0, %1"
1383 [(set_attr "type" "arith")
1384 (set_attr "up_c" "yes")
1385 (set_attr "mode" "SI")])
1387 (define_insn "*zero_extendhisi2_ucc_score3"
1388 [(set (reg:CC_N CC_REGNUM)
1389 (compare:CC_N (lshiftrt:SI
1390 (ashift:SI (match_operand:SI 1 "score_register_operand" "d")
1391 (const_int 16))
1392 (const_int 16))
1393 (const_int 0)))
1394 (set (match_operand:SI 0 "score_register_operand" "=d")
1395 (zero_extend:SI (match_operand:HI 2 "score_register_operand" "0")))]
1396 "(TARGET_SCORE3)"
1397 "extzh.c\t%0, %1"
1398 [(set_attr "type" "arith")
1399 (set_attr "length" "4")
1400 (set_attr "up_c" "yes")
1401 (set_attr "mode" "SI")])
1403 (define_insn "*zero_extendhisi2_cmp_score7"
1404 [(set (reg:CC_N CC_REGNUM)
1405 (compare:CC_N (lshiftrt:SI
1406 (ashift:SI (match_operand:SI 1 "register_operand" "d")
1407 (const_int 16))
1408 (const_int 16))
1409 (const_int 0)))
1410 (clobber (match_scratch:SI 0 "=d"))]
1411 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
1412 "extzh.c %0, %1"
1413 [(set_attr "type" "arith")
1414 (set_attr "up_c" "yes")
1415 (set_attr "mode" "SI")])
1417 (define_insn "*zero_extendhisi2_cmp_score3"
1418 [(set (reg:CC_N CC_REGNUM)
1419 (compare:CC_N (lshiftrt:SI
1420 (ashift:SI (match_operand:SI 1 "score_register_operand" "d")
1421 (const_int 16))
1422 (const_int 16))
1423 (const_int 0)))
1424 (clobber (match_scratch:SI 0 "=d"))]
1425 "(TARGET_SCORE3)"
1426 "extzh.c\t%0, %1"
1427 [(set_attr "type" "arith")
1428 (set_attr "length" "4")
1429 (set_attr "up_c" "yes")
1430 (set_attr "mode" "SI")])
1432 (define_expand "mulsi3"
1433 [(set (match_operand:SI 0 "score_register_operand")
1434 (mult:SI (match_operand:SI 1 "score_register_operand")
1435 (match_operand:SI 2 "score_register_operand")))]
1436 ""
1437 {
1438 if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
1439 emit_insn (gen_mulsi3_score7 (operands[0], operands[1], operands[2]));
1440 else if (TARGET_SCORE3)
1441 emit_insn (gen_mulsi3_score3 (operands[0], operands[1], operands[2]));
1442 DONE;
1443 })
1445 (define_insn "mulsi3_score7"
1446 [(set (match_operand:SI 0 "register_operand" "=l")
1447 (mult:SI (match_operand:SI 1 "register_operand" "d")
1448 (match_operand:SI 2 "register_operand" "d")))
1449 (clobber (reg:SI HI_REGNUM))]
1450 "(TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)"
1451 "mul %1, %2"
1452 [(set_attr "type" "mul")
1453 (set_attr "mode" "SI")])
1455 (define_insn "mulsi3_score3"
1456 [(set (match_operand:SI 0 "score_register_operand" "=d")
1457 (mult:SI (match_operand:SI 1 "score_register_operand" "d")
1458 (match_operand:SI 2 "score_register_operand" "d")))]
1459 "(TARGET_SCORE3)"
1460 "mulr.l\t%0, %1, %2"
1461 [(set_attr "type" "mul")
1462 (set_attr "length" "4")
1463 (set_attr "mode" "SI")])
1465 (define_expand "mulsidi3"
1466 [(set (match_operand:DI 0 "score_register_operand")
1467 (mult:DI (sign_extend:DI
1468 (match_operand:SI 1 "score_register_operand"))
1469 (sign_extend:DI
1470 (match_operand:SI 2 "score_register_operand"))))]
1471 ""
1472 {
1473 if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
1474 emit_insn (gen_mulsidi3_score7 (operands[0], operands[1], operands[2]));
1475 else if (TARGET_SCORE3)
1476 emit_insn (gen_mulsidi3_score3 (operands[0], operands[1], operands[2]));
1477 DONE;
1478 })
1480 (define_insn "mulsidi3_score7"
1481 [(set (match_operand:DI 0 "register_operand" "=x")
1482 (mult:DI (sign_extend:DI
1483 (match_operand:SI 1 "register_operand" "d"))
1484 (sign_extend:DI
1485 (match_operand:SI 2 "register_operand" "d"))))]
1486 "(TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)"
1487 "mul %1, %2"
1488 [(set_attr "type" "mul")
1489 (set_attr "mode" "DI")])
1491 (define_insn "mulsidi3_score3"
1492 [(set (match_operand:DI 0 "score_register_operand" "=d")
1493 (mult:DI (sign_extend:DI
1494 (match_operand:SI 1 "score_register_operand" "d"))
1495 (sign_extend:DI
1496 (match_operand:SI 2 "score_register_operand" "d"))))]
1497 "(TARGET_SCORE3)"
1498 "mulr\t%0, %1, %2"
1499 [(set_attr "type" "mul")
1500 (set_attr "length" "4")
1501 (set_attr "mode" "DI")])
1503 (define_expand "umulsidi3"
1504 [(set (match_operand:DI 0 "score_register_operand")
1505 (mult:DI (zero_extend:DI
1506 (match_operand:SI 1 "score_register_operand"))
1507 (zero_extend:DI
1508 (match_operand:SI 2 "score_register_operand"))))]
1509 ""
1510 {
1511 if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
1512 emit_insn (gen_umulsidi3_score7 (operands[0], operands[1], operands[2]));
1513 else if (TARGET_SCORE3)
1514 emit_insn (gen_umulsidi3_score3 (operands[0], operands[1], operands[2]));
1515 DONE;
1516 })
1518 (define_insn "umulsidi3_score7"
1519 [(set (match_operand:DI 0 "register_operand" "=x")
1520 (mult:DI (zero_extend:DI
1521 (match_operand:SI 1 "register_operand" "d"))
1522 (zero_extend:DI
1523 (match_operand:SI 2 "register_operand" "d"))))]
1524 "(TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)"
1525 "mulu %1, %2"
1526 [(set_attr "type" "mul")
1527 (set_attr "mode" "DI")])
1529 (define_insn "umulsidi3_score3"
1530 [(set (match_operand:DI 0 "score_register_operand" "=d")
1531 (mult:DI (zero_extend:DI
1532 (match_operand:SI 1 "score_register_operand" "d"))
1533 (zero_extend:DI
1534 (match_operand:SI 2 "score_register_operand" "d"))))]
1535 "(TARGET_SCORE3)"
1536 "mulur\t%0, %1, %2"
1537 [(set_attr "type" "mul")
1538 (set_attr "length" "4")
1539 (set_attr "mode" "DI")])
1541 (define_expand "divmodsi4"
1542 [(parallel
1543 [(set (match_operand:SI 0 "score_register_operand")
1544 (div:SI (match_operand:SI 1 "score_register_operand")
1545 (match_operand:SI 2 "score_register_operand")))
1546 (set (match_operand:SI 3 "score_register_operand")
1547 (mod:SI (match_dup 1) (match_dup 2)))])]
1548 ""
1549 ""
1550 )
1552 (define_insn "*divmodsi4_score7"
1553 [(set (match_operand:SI 0 "register_operand" "=l")
1554 (div:SI (match_operand:SI 1 "register_operand" "d")
1555 (match_operand:SI 2 "register_operand" "d")))
1556 (set (match_operand:SI 3 "register_operand" "=h")
1557 (mod:SI (match_dup 1) (match_dup 2)))]
1558 "(TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)"
1559 "div %1, %2"
1560 [(set_attr "type" "div")
1561 (set_attr "mode" "SI")])
1563 (define_insn "*divmodsi4_score3"
1564 [(set (match_operand:SI 0 "score_register_operand" "=l")
1565 (div:SI (match_operand:SI 1 "score_register_operand" "d")
1566 (match_operand:SI 2 "score_register_operand" "d")))
1567 (set (match_operand:SI 3 "score_register_operand" "=h")
1568 (mod:SI (match_dup 1) (match_dup 2)))]
1569 "(TARGET_SCORE3)"
1570 "div\t%1, %2"
1571 [(set_attr "type" "div")
1572 (set_attr "mode" "SI")])
1574 (define_expand "udivmodsi4"
1575 [(parallel
1576 [(set (match_operand:SI 0 "score_register_operand")
1577 (udiv:SI (match_operand:SI 1 "score_register_operand")
1578 (match_operand:SI 2 "score_register_operand")))
1579 (set (match_operand:SI 3 "score_register_operand")
1580 (umod:SI (match_dup 1) (match_dup 2)))])]
1581 ""
1582 ""
1583 )
1585 (define_insn "*udivmodsi4_score7"
1586 [(set (match_operand:SI 0 "register_operand" "=l")
1587 (udiv:SI (match_operand:SI 1 "register_operand" "d")
1588 (match_operand:SI 2 "register_operand" "d")))
1589 (set (match_operand:SI 3 "register_operand" "=h")
1590 (umod:SI (match_dup 1) (match_dup 2)))]
1591 "(TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)"
1592 "divu %1, %2"
1593 [(set_attr "type" "div")
1594 (set_attr "mode" "SI")])
1596 (define_insn "*udivmodsi4_score3"
1597 [(set (match_operand:SI 0 "score_register_operand" "=l")
1598 (udiv:SI (match_operand:SI 1 "score_register_operand" "d")
1599 (match_operand:SI 2 "score_register_operand" "d")))
1600 (set (match_operand:SI 3 "score_register_operand" "=h")
1601 (umod:SI (match_dup 1) (match_dup 2)))]
1602 "(TARGET_SCORE3)"
1603 "divu\t%1, %2"
1604 [(set_attr "type" "div")
1605 (set_attr "mode" "SI")])
1607 (define_expand "ashlsi3"
1608 [(set (match_operand:SI 0 "score_register_operand")
1609 (ashift:SI (match_operand:SI 1 "score_register_operand")
1610 (match_operand:SI 2 "arith_operand")))]
1611 ""
1612 ""
1613 )
1615 (define_insn "*ashlsi3_score7"
1616 [(set (match_operand:SI 0 "register_operand" "=d,d")
1617 (ashift:SI (match_operand:SI 1 "register_operand" "d,d")
1618 (match_operand:SI 2 "arith_operand" "J,d")))]
1619 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
1620 "@
1621 slli %0, %1, %c2
1622 sll %0, %1, %2"
1623 [(set_attr "type" "arith")
1624 (set_attr "mode" "SI")])
1626 (define_insn "*ashlsi3_score3"
1627 [(set (match_operand:SI 0 "score_register_operand" "=e,d,d")
1628 (ashift:SI (match_operand:SI 1 "score_register_operand" "0,d,d")
1629 (match_operand:SI 2 "arith_operand" "J,J,d")))]
1630 "(TARGET_SCORE3)"
1631 "@
1632 slli!\t%0, %c2
1633 slli\t%0, %1, %c2
1634 sll\t%0, %1, %2"
1635 [(set_attr "type" "arith")
1636 (set_attr "length" "2,4,4")
1637 (set_attr "mode" "SI")])
1639 (define_insn "*ashlsi3_ucc_score7"
1640 [(set (reg:CC_NZ CC_REGNUM)
1641 (compare:CC_NZ (ashift:SI
1642 (match_operand:SI 1 "register_operand" "d,d")
1643 (match_operand:SI 2 "arith_operand" "J,d"))
1644 (const_int 0)))
1645 (set (match_operand:SI 0 "register_operand" "=d,d")
1646 (ashift:SI (match_dup 1) (match_dup 2)))]
1647 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
1648 {
1649 switch (which_alternative)
1650 {
1651 case 0: return score_select (operands, "slli", false, "c", true);
1652 case 1: return score_select (operands, "sll", false, "", true);
1653 default: gcc_unreachable ();
1654 }
1655 }
1656 [(set_attr "type" "arith")
1657 (set_attr "up_c" "yes")
1658 (set_attr "mode" "SI")])
1660 (define_insn "*ashlsi3_ucc_score3"
1661 [(set (reg:CC_NZ CC_REGNUM)
1662 (compare:CC_NZ (ashift:SI
1663 (match_operand:SI 1 "score_register_operand" "d,d")
1664 (match_operand:SI 2 "arith_operand" "J,d"))
1665 (const_int 0)))
1666 (set (match_operand:SI 0 "score_register_operand" "=d,d")
1667 (ashift:SI (match_dup 1) (match_dup 2)))]
1668 "(TARGET_SCORE3)"
1669 {
1670 switch (which_alternative)
1671 {
1672 case 0: return score_select (operands, "slli", false, "c", true);
1673 case 1: return score_select (operands, "sll", false, "", true);
1674 default: gcc_unreachable ();
1675 }
1676 }
1677 [(set_attr "type" "arith")
1678 (set_attr "length" "4,4")
1679 (set_attr "up_c" "yes")
1680 (set_attr "mode" "SI")])
1682 (define_insn "*ashlsi3_cmp_score7"
1683 [(set (reg:CC_NZ CC_REGNUM)
1684 (compare:CC_NZ (ashift:SI
1685 (match_operand:SI 1 "register_operand" "d,d")
1686 (match_operand:SI 2 "arith_operand" "J,d"))
1687 (const_int 0)))
1688 (clobber (match_scratch:SI 0 "=d,d"))]
1689 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
1690 {
1691 switch (which_alternative)
1692 {
1693 case 0: return score_select (operands, "slli", false, "c", true);
1694 case 1: return score_select (operands, "sll", false, "", true);
1695 default: gcc_unreachable ();
1696 }
1697 }
1698 [(set_attr "type" "arith")
1699 (set_attr "up_c" "yes")
1700 (set_attr "mode" "SI")])
1702 (define_insn "*ashlsi3_cmp_score3"
1703 [(set (reg:CC_NZ CC_REGNUM)
1704 (compare:CC_NZ (ashift:SI
1705 (match_operand:SI 1 "score_register_operand" "d,d")
1706 (match_operand:SI 2 "arith_operand" "J,d"))
1707 (const_int 0)))
1708 (clobber (match_scratch:SI 0 "=d,d"))]
1709 "(TARGET_SCORE3)"
1710 {
1711 switch (which_alternative)
1712 {
1713 case 0: return score_select (operands, "slli", false, "c", true);
1714 case 1: return score_select (operands, "sll", false, "", true);
1715 default: gcc_unreachable ();
1716 }
1717 }
1718 [(set_attr "type" "arith")
1719 (set_attr "length" "4,4")
1720 (set_attr "up_c" "yes")
1721 (set_attr "mode" "SI")])
1724 (define_expand "ashrsi3"
1725 [(set (match_operand:SI 0 "score_register_operand")
1726 (ashiftrt:SI (match_operand:SI 1 "score_register_operand")
1727 (match_operand:SI 2 "arith_operand")))]
1728 ""
1729 ""
1730 )
1732 (define_insn "*ashrsi3_score7"
1733 [(set (match_operand:SI 0 "register_operand" "=d,d")
1734 (ashiftrt:SI (match_operand:SI 1 "register_operand" "d,d")
1735 (match_operand:SI 2 "arith_operand" "J,d")))]
1736 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
1737 "@
1738 srai %0, %1, %c2
1739 sra %0, %1, %2"
1740 [(set_attr "type" "arith")
1741 (set_attr "mode" "SI")])
1743 (define_insn "*ashrsi3_score3"
1744 [(set (match_operand:SI 0 "score_register_operand" "=d,d")
1745 (ashiftrt:SI (match_operand:SI 1 "score_register_operand" "d,d")
1746 (match_operand:SI 2 "arith_operand" "J,d")))]
1747 "(TARGET_SCORE3)"
1748 "@
1749 srai\t%0, %1, %c2
1750 sra\t%0, %1, %2"
1751 [(set_attr "type" "arith")
1752 (set_attr "length" "4,4")
1753 (set_attr "mode" "SI")])
1755 (define_insn "*ashrsi3_ucc_score7"
1756 [(set (reg:CC_NZ CC_REGNUM)
1757 (compare:CC_NZ (ashiftrt:SI
1758 (match_operand:SI 1 "register_operand" "d,d")
1759 (match_operand:SI 2 "arith_operand" "J,d"))
1760 (const_int 0)))
1761 (set (match_operand:SI 0 "register_operand" "=d,d")
1762 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
1763 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
1764 {
1765 switch (which_alternative)
1766 {
1767 case 0: return \"srai.c\t%0, %1, %c2\";
1768 case 1: return score_select (operands, "sra", false, "", true);
1769 default: gcc_unreachable ();
1770 }
1771 }
1772 [(set_attr "type" "arith")
1773 (set_attr "up_c" "yes")
1774 (set_attr "mode" "SI")])
1776 (define_insn "*ashrsi3_ucc_score3"
1777 [(set (reg:CC_NZ CC_REGNUM)
1778 (compare:CC_NZ (ashiftrt:SI
1779 (match_operand:SI 1 "score_register_operand" "d,d")
1780 (match_operand:SI 2 "arith_operand" "J,d"))
1781 (const_int 0)))
1782 (set (match_operand:SI 0 "score_register_operand" "=d,d")
1783 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
1784 "(TARGET_SCORE3)"
1785 {
1786 switch (which_alternative)
1787 {
1788 case 0: return \"srai.c\t%0, %1, %c2\";
1789 case 1: return score_select (operands, "sra", false, "", true);
1790 default: gcc_unreachable ();
1791 }
1792 }
1793 [(set_attr "type" "arith")
1794 (set_attr "length" "4,4")
1795 (set_attr "up_c" "yes")
1796 (set_attr "mode" "SI")])
1798 (define_insn "*ashrsi3_cmp_score7"
1799 [(set (reg:CC_NZ CC_REGNUM)
1800 (compare:CC_NZ (ashiftrt:SI
1801 (match_operand:SI 1 "register_operand" "d,d")
1802 (match_operand:SI 2 "arith_operand" "J,d"))
1803 (const_int 0)))
1804 (clobber (match_scratch:SI 0 "=d,d"))]
1805 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
1806 {
1807 switch (which_alternative)
1808 {
1809 case 0: return \"srai.c\t%0, %1, %c2\";
1810 case 1: return score_select (operands, "sra", false, "", true);
1811 default: gcc_unreachable ();
1812 }
1813 }
1814 [(set_attr "type" "arith")
1815 (set_attr "up_c" "yes")
1816 (set_attr "mode" "SI")])
1818 (define_insn "ashrsi3_cmp_score3"
1819 [(set (reg:CC_NZ CC_REGNUM)
1820 (compare:CC_NZ (ashiftrt:SI
1821 (match_operand:SI 1 "score_register_operand" "d,d")
1822 (match_operand:SI 2 "arith_operand" "J,d"))
1823 (const_int 0)))
1824 (clobber (match_scratch:SI 0 "=d,d"))]
1825 "(TARGET_SCORE3)"
1826 {
1827 switch (which_alternative)
1828 {
1829 case 0: return \"srai.c\t%0, %1, %c2\";
1830 case 1: return score_select (operands, "sra", false, "", true);
1831 default: gcc_unreachable ();
1832 }
1833 }
1834 [(set_attr "type" "arith")
1835 (set_attr "length" "4,4")
1836 (set_attr "up_c" "yes")
1837 (set_attr "mode" "SI")])
1839 (define_expand "lshrsi3"
1840 [(set (match_operand:SI 0 "score_register_operand")
1841 (lshiftrt:SI (match_operand:SI 1 "score_register_operand")
1842 (match_operand:SI 2 "arith_operand")))]
1843 ""
1844 ""
1845 )
1847 (define_insn "*lshrsi3_score7"
1848 [(set (match_operand:SI 0 "register_operand" "=d,d")
1849 (lshiftrt:SI (match_operand:SI 1 "register_operand" "d,d")
1850 (match_operand:SI 2 "arith_operand" "J,d")))]
1851 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
1852 "@
1853 srli %0, %1, %c2
1854 srl %0, %1, %2"
1855 [(set_attr "type" "arith")
1856 (set_attr "mode" "SI")])
1858 (define_insn "*lshrsi3_score3"
1859 [(set (match_operand:SI 0 "score_register_operand" "=e,d,d")
1860 (lshiftrt:SI (match_operand:SI 1 "score_register_operand" "0,d,d")
1861 (match_operand:SI 2 "arith_operand" "J,J,d")))]
1862 "(TARGET_SCORE3)"
1863 "@
1864 srli!\t%0, %c2
1865 srli\t%0, %1, %c2
1866 srl\t%0, %1, %2"
1867 [(set_attr "type" "arith")
1868 (set_attr "length" "2,4,4")
1869 (set_attr "mode" "SI")])
1871 (define_insn "*lshrsi3_ucc_score7"
1872 [(set (reg:CC_NZ CC_REGNUM)
1873 (compare:CC_NZ (lshiftrt:SI
1874 (match_operand:SI 1 "register_operand" "d,d")
1875 (match_operand:SI 2 "arith_operand" "J,d"))
1876 (const_int 0)))
1877 (set (match_operand:SI 0 "register_operand" "=d,d")
1878 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
1879 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
1880 {
1881 switch (which_alternative)
1882 {
1883 case 0: return score_select (operands, "srli", false, "c", true);
1884 case 1: return score_select (operands, "srl", false, "", true);
1885 default: gcc_unreachable ();
1886 }
1887 }
1888 [(set_attr "type" "arith")
1889 (set_attr "up_c" "yes")
1890 (set_attr "mode" "SI")])
1892 (define_insn "*lshrsi3_ucc_score3"
1893 [(set (reg:CC_NZ CC_REGNUM)
1894 (compare:CC_NZ (lshiftrt:SI
1895 (match_operand:SI 1 "score_register_operand" "d,d")
1896 (match_operand:SI 2 "arith_operand" "J,d"))
1897 (const_int 0)))
1898 (set (match_operand:SI 0 "score_register_operand" "=d,d")
1899 (lshiftrt:SI (match_dup 1) (match_dup 2)))]
1900 "(TARGET_SCORE3)"
1901 {
1902 switch (which_alternative)
1903 {
1904 case 0: return score_select (operands, "srli", false, "c", true);
1905 case 1: return score_select (operands, "srl", false, "", true);
1906 default: gcc_unreachable ();
1907 }
1908 }
1909 [(set_attr "type" "arith")
1910 (set_attr "length" "4,4")
1911 (set_attr "up_c" "yes")
1912 (set_attr "mode" "SI")])
1914 (define_insn "*lshrsi3_cmp_score7"
1915 [(set (reg:CC_NZ CC_REGNUM)
1916 (compare:CC_NZ (lshiftrt:SI
1917 (match_operand:SI 1 "register_operand" "d,d")
1918 (match_operand:SI 2 "arith_operand" "J,d"))
1919 (const_int 0)))
1920 (clobber (match_scratch:SI 0 "=d,d"))]
1921 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
1922 {
1923 switch (which_alternative)
1924 {
1925 case 0: return score_select (operands, "srli", false, "c", true);
1926 case 1: return score_select (operands, "srl", false, "", true);
1927 default: gcc_unreachable ();
1928 }
1929 }
1930 [(set_attr "type" "arith")
1931 (set_attr "up_c" "yes")
1932 (set_attr "mode" "SI")])
1934 (define_insn "*lshrsi3_cmp_score3"
1935 [(set (reg:CC_NZ CC_REGNUM)
1936 (compare:CC_NZ (lshiftrt:SI
1937 (match_operand:SI 1 "score_register_operand" "d,d")
1938 (match_operand:SI 2 "arith_operand" "J,d"))
1939 (const_int 0)))
1940 (clobber (match_scratch:SI 0 "=d,d"))]
1941 "(TARGET_SCORE3)"
1942 {
1943 switch (which_alternative)
1944 {
1945 case 0: return score_select (operands, "srli", false, "c", true);
1946 case 1: return score_select (operands, "srl", false, "", true);
1947 default: gcc_unreachable ();
1948 }
1949 }
1950 [(set_attr "type" "arith")
1951 (set_attr "length" "4,4")
1952 (set_attr "up_c" "yes")
1953 (set_attr "mode" "SI")])
1955 (define_expand "negsi2"
1956 [(set (match_operand:SI 0 "score_register_operand")
1957 (neg:SI (match_operand:SI 1 "score_register_operand")))]
1958 ""
1959 ""
1960 )
1962 (define_insn "*negsi2_score7"
1963 [(set (match_operand:SI 0 "register_operand" "=d")
1964 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
1965 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
1966 "neg %0, %1"
1967 [(set_attr "type" "arith")
1968 (set_attr "mode" "SI")])
1970 (define_insn "*negsi2_score3"
1971 [(set (match_operand:SI 0 "score_register_operand" "=d")
1972 (neg:SI (match_operand:SI 1 "score_register_operand" "d")))]
1973 "(TARGET_SCORE3)"
1974 "neg\t%0, %1"
1975 [(set_attr "type" "arith")
1976 (set_attr "length" "4")
1977 (set_attr "mode" "SI")])
1979 (define_insn "*negsi2_cmp_score7"
1980 [(set (reg:CC_NZ CC_REGNUM)
1981 (compare:CC_NZ (neg:SI (match_operand:SI 1 "register_operand" "e,d"))
1982 (const_int 0)))
1983 (clobber (match_scratch:SI 0 "=e,d"))]
1984 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
1985 "@
1986 neg! %0, %1
1987 neg.c %0, %1"
1988 [(set_attr "type" "arith")
1989 (set_attr "up_c" "yes")
1990 (set_attr "mode" "SI")])
1992 (define_insn "*negsi2_cmp_score3"
1993 [(set (reg:CC_NZ CC_REGNUM)
1994 (compare:CC_NZ (neg:SI (match_operand:SI 1 "score_register_operand" "d"))
1995 (const_int 0)))
1996 (clobber (match_scratch:SI 0 "=d"))]
1997 "(TARGET_SCORE3)"
1998 "neg.c\t%0, %1"
1999 [(set_attr "type" "arith")
2000 (set_attr "length" "4")
2001 (set_attr "up_c" "yes")
2002 (set_attr "mode" "SI")])
2004 (define_insn "*negsi2_ucc_score7"
2005 [(set (reg:CC_NZ CC_REGNUM)
2006 (compare:CC_NZ (neg:SI (match_operand:SI 1 "register_operand" "e,d"))
2007 (const_int 0)))
2008 (set (match_operand:SI 0 "register_operand" "=e,d")
2009 (neg:SI (match_dup 1)))]
2010 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
2011 "@
2012 neg! %0, %1
2013 neg.c %0, %1"
2014 [(set_attr "type" "arith")
2015 (set_attr "up_c" "yes")
2016 (set_attr "mode" "SI")])
2018 (define_insn "*negsi2_ucc_score3"
2019 [(set (reg:CC_NZ CC_REGNUM)
2020 (compare:CC_NZ (neg:SI (match_operand:SI 1 "score_register_operand" "d"))
2021 (const_int 0)))
2022 (set (match_operand:SI 0 "score_register_operand" "=d")
2023 (neg:SI (match_dup 1)))]
2024 "(TARGET_SCORE3)"
2025 "neg.c\t%0, %1"
2026 [(set_attr "type" "arith")
2027 (set_attr "length" "4")
2028 (set_attr "up_c" "yes")
2029 (set_attr "mode" "SI")])
2032 (define_expand "one_cmplsi2"
2033 [(set (match_operand:SI 0 "score_register_operand")
2034 (not:SI (match_operand:SI 1 "score_register_operand")))]
2035 ""
2036 ""
2037 )
2039 (define_insn "*one_cmplsi2_score7"
2040 [(set (match_operand:SI 0 "register_operand" "=d")
2041 (not:SI (match_operand:SI 1 "register_operand" "d")))]
2042 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
2043 "not\t%0, %1"
2044 [(set_attr "type" "arith")
2045 (set_attr "mode" "SI")])
2047 (define_insn "*one_cmplsi2_score3"
2048 [(set (match_operand:SI 0 "score_register_operand" "=d")
2049 (not:SI (match_operand:SI 1 "score_register_operand" "d")))]
2050 "(TARGET_SCORE3)"
2051 "not\t%0, %1"
2052 [(set_attr "type" "arith")
2053 (set_attr "length" "4")
2054 (set_attr "mode" "SI")])
2056 (define_insn "*one_cmplsi2_ucc_score7"
2057 [(set (reg:CC_NZ CC_REGNUM)
2058 (compare:CC_NZ (not:SI (match_operand:SI 1 "register_operand" "e,d"))
2059 (const_int 0)))
2060 (set (match_operand:SI 0 "register_operand" "=e,d")
2061 (not:SI (match_dup 1)))]
2062 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
2063 "@
2064 not! %0, %1
2065 not.c %0, %1"
2066 [(set_attr "type" "arith")
2067 (set_attr "up_c" "yes")
2068 (set_attr "mode" "SI")])
2070 (define_insn "*one_cmplsi2_ucc_score3"
2071 [(set (reg:CC_NZ CC_REGNUM)
2072 (compare:CC_NZ (not:SI (match_operand:SI 1 "score_register_operand" "d"))
2073 (const_int 0)))
2074 (set (match_operand:SI 0 "score_register_operand" "=d")
2075 (not:SI (match_dup 1)))]
2076 "(TARGET_SCORE3)"
2077 "not.c\t%0, %1"
2078 [(set_attr "type" "arith")
2079 (set_attr "length" "4")
2080 (set_attr "up_c" "yes")
2081 (set_attr "mode" "SI")])
2083 (define_insn "*one_cmplsi2_cmp_score7"
2084 [(set (reg:CC_NZ CC_REGNUM)
2085 (compare:CC_NZ (not:SI (match_operand:SI 1 "register_operand" "e,d"))
2086 (const_int 0)))
2087 (clobber (match_scratch:SI 0 "=e,d"))]
2088 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
2089 "@
2090 not! %0, %1
2091 not.c %0, %1"
2092 [(set_attr "type" "arith")
2093 (set_attr "up_c" "yes")
2094 (set_attr "mode" "SI")])
2096 (define_insn "*one_cmplsi2_cmp_score3"
2097 [(set (reg:CC_NZ CC_REGNUM)
2098 (compare:CC_NZ (not:SI (match_operand:SI 1 "score_register_operand" "d"))
2099 (const_int 0)))
2100 (clobber (match_scratch:SI 0 "=d"))]
2101 "(TARGET_SCORE3)"
2102 "not.c\t%0, %1"
2103 [(set_attr "type" "arith")
2104 (set_attr "length" "4")
2105 (set_attr "up_c" "yes")
2106 (set_attr "mode" "SI")])
2108 (define_expand "rotlsi3"
2109 [(parallel
2110 [(set (match_operand:SI 0 "score_register_operand")
2111 (rotate:SI (match_operand:SI 1 "score_register_operand")
2112 (match_operand:SI 2 "arith_operand")))
2113 (clobber (reg:CC CC_REGNUM))])]
2114 ""
2115 ""
2116 )
2118 (define_insn "*rotlsi3_score7"
2119 [(set (match_operand:SI 0 "register_operand" "=d,d")
2120 (rotate:SI (match_operand:SI 1 "register_operand" "d,d")
2121 (match_operand:SI 2 "arith_operand" "J,d")))
2122 (clobber (reg:CC CC_REGNUM))]
2123 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
2124 "@
2125 roli.c %0, %1, %c2
2126 rol.c %0, %1, %2"
2127 [(set_attr "type" "arith")
2128 (set_attr "mode" "SI")])
2130 (define_insn "*rotlsi3_score3"
2131 [(set (match_operand:SI 0 "score_register_operand" "=d,d")
2132 (rotate:SI (match_operand:SI 1 "score_register_operand" "d,d")
2133 (match_operand:SI 2 "arith_operand" "J,d")))
2134 (clobber (reg:CC CC_REGNUM))]
2135 "(TARGET_SCORE3)"
2136 "@
2137 roli.c\t%0, %1, %c2
2138 rol.c\t%0, %1, %2"
2139 [(set_attr "type" "arith")
2140 (set_attr "length" "4,4")
2141 (set_attr "mode" "SI")])
2143 (define_expand "rotrsi3"
2144 [(parallel
2145 [(set (match_operand:SI 0 "score_register_operand")
2146 (rotatert:SI (match_operand:SI 1 "score_register_operand")
2147 (match_operand:SI 2 "arith_operand")))
2148 (clobber (reg:CC CC_REGNUM))])]
2149 ""
2150 ""
2151 )
2153 (define_insn "*rotrsi3_score7"
2154 [(set (match_operand:SI 0 "register_operand" "=d,d")
2155 (rotatert:SI (match_operand:SI 1 "register_operand" "d,d")
2156 (match_operand:SI 2 "arith_operand" "J,d")))
2157 (clobber (reg:CC CC_REGNUM))]
2158 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
2159 "@
2160 rori.c %0, %1, %c2
2161 ror.c %0, %1, %2"
2162 [(set_attr "type" "arith")
2163 (set_attr "mode" "SI")])
2165 (define_insn "*rotrsi3_score3"
2166 [(set (match_operand:SI 0 "score_register_operand" "=d,d")
2167 (rotatert:SI (match_operand:SI 1 "score_register_operand" "d,d")
2168 (match_operand:SI 2 "arith_operand" "J,d")))
2169 (clobber (reg:CC CC_REGNUM))]
2170 "(TARGET_SCORE3)"
2171 "@
2172 rori.c\t%0, %1, %c2
2173 ror.c\t%0, %1, %2"
2174 [(set_attr "type" "arith")
2175 (set_attr "length" "4,4")
2176 (set_attr "mode" "SI")])
2178 (define_insn "cbrancheqz"
2179 [(set (pc) (if_then_else
2180 (eq (match_operand:SI 0 "score_register_operand" "d")
2181 (const_int 0))
2182 (label_ref (match_operand 1 "" ""))
2183 (pc)))
2184 (clobber (reg:CC CC_REGNUM))]
2185 "(TARGET_SCORE3)"
2186 {
2187 if (get_attr_length (insn) == 4)
2188 return \"bcmpeqz\t%0, %1\";
2189 else
2190 return \"cmpi!\t%0, 0\;beq!\t%1\";
2191 }
2192 [(set (attr "length")
2193 (if_then_else
2194 (and (ge (minus (match_dup 1) (pc)) (const_int -504))
2195 (le (minus (match_dup 1) (pc)) (const_int 502)))
2196 (const_int 4)
2197 (const_int 6)))])
2199 (define_insn "cbrancheq"
2200 [(set (pc) (if_then_else
2201 (eq (match_operand:SI 0 "score_register_operand" "d")
2202 (match_operand:SI 1 "score_register_operand" "d"))
2203 (label_ref (match_operand 2 "" ""))
2204 (pc)))
2205 (clobber (reg:CC CC_REGNUM))]
2206 "(TARGET_SCORE3)"
2207 {
2208 if (get_attr_length (insn) == 4)
2209 return \"bcmpeq\t%0, %1, %2\";
2210 else
2211 return \"cmp!\t%0, %1\;beq!\t%2\";
2212 }
2213 [(set (attr "length")
2214 (if_then_else
2215 (and (ge (minus (match_dup 2) (pc)) (const_int -504))
2216 (le (minus (match_dup 2) (pc)) (const_int 502)))
2217 (const_int 4)
2218 (const_int 6)))])
2220 (define_insn "cbranchnez"
2221 [(set (pc) (if_then_else
2222 (ne (match_operand:SI 0 "score_register_operand" "d")
2223 (const_int 0))
2224 (label_ref (match_operand 1 "" ""))
2225 (pc)))
2226 (clobber (reg:CC CC_REGNUM))]
2227 "(TARGET_SCORE3)"
2228 {
2229 if (get_attr_length (insn) == 4)
2230 return \"bcmpnez\t%0, %1\";
2231 else
2232 return \"cmpi!\t%0, 0\;bne\t%1\";
2233 }
2234 [(set (attr "length")
2235 (if_then_else
2236 (and (ge (minus (match_dup 1) (pc)) (const_int -504))
2237 (le (minus (match_dup 1) (pc)) (const_int 502)))
2238 (const_int 4)
2239 (const_int 6)))])
2241 (define_insn "cbranchne"
2242 [(set (pc) (if_then_else
2243 (ne (match_operand:SI 0 "score_register_operand" "d")
2244 (match_operand:SI 1 "score_register_operand" "d"))
2245 (label_ref (match_operand 2 "" ""))
2246 (pc)))
2247 (clobber (reg:CC CC_REGNUM))]
2248 "(TARGET_SCORE3)"
2249 {
2250 if (get_attr_length (insn) == 4)
2251 return \"bcmpne\t%0, %1, %2\";
2252 else
2253 return \"cmp!\t%0, %1\;bne\t%2\";
2254 }
2255 [(set (attr "length")
2256 (if_then_else
2257 (and (ge (minus (match_dup 2) (pc)) (const_int -504))
2258 (le (minus (match_dup 2) (pc)) (const_int 502)))
2259 (const_int 4)
2260 (const_int 6)))])
2262 (define_expand "cmpsi"
2263 [(match_operand:SI 0 "score_register_operand")
2264 (match_operand:SI 1 "arith_operand")]
2265 ""
2266 {
2267 cmp_op0 = operands[0];
2268 cmp_op1 = operands[1];
2269 DONE;
2270 })
2272 (define_insn "cmpsi_nz_score7"
2273 [(set (reg:CC_NZ CC_REGNUM)
2274 (compare:CC_NZ (match_operand:SI 0 "register_operand" "d,e,d")
2275 (match_operand:SI 1 "arith_operand" "L,e,d")))]
2276 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
2277 "@
2278 cmpi.c %0, %c1
2279 cmp! %0, %1
2280 cmp.c %0, %1"
2281 [(set_attr "type" "cmp")
2282 (set_attr "up_c" "yes")
2283 (set_attr "mode" "SI")])
2285 (define_insn "cmpsi_nz_score3"
2286 [(set (reg:CC_NZ CC_REGNUM)
2287 (compare:CC_NZ (match_operand:SI 0 "score_register_operand" "d,d,d")
2288 (match_operand:SI 1 "arith_operand" "O,L,d")))]
2289 "(TARGET_SCORE3)"
2290 "@
2291 cmpi!\t%0, %c1
2292 cmpi.c\t%0, %c1
2293 cmp!\t %0, %1"
2294 [(set_attr "type" "cmp")
2295 (set_attr "length" "2,4,2")
2296 (set_attr "up_c" "yes")
2297 (set_attr "mode" "SI")])
2299 (define_insn "cmpsi_n_score7"
2300 [(set (reg:CC_N CC_REGNUM)
2301 (compare:CC_N (match_operand:SI 0 "register_operand" "d,e,d")
2302 (match_operand:SI 1 "arith_operand" "L,e,d")))]
2303 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
2304 "@
2305 cmpi.c %0, %c1
2306 cmp! %0, %1
2307 cmp.c %0, %1"
2308 [(set_attr "type" "cmp")
2309 (set_attr "up_c" "yes")
2310 (set_attr "mode" "SI")])
2312 (define_insn "cmpsi_n_score3"
2313 [(set (reg:CC_N CC_REGNUM)
2314 (compare:CC_N (match_operand:SI 0 "score_register_operand" "d,d,d")
2315 (match_operand:SI 1 "arith_operand" "O,L,d")))]
2316 "(TARGET_SCORE3)"
2317 "@
2318 cmpi!\t%0, %c1
2319 cmpi.c\t%0, %c1
2320 cmp!\t%0, %1"
2321 [(set_attr "type" "cmp")
2322 (set_attr "length" "2,4,2")
2323 (set_attr "up_c" "yes")
2324 (set_attr "mode" "SI")])
2326 (define_insn "*cmpsi_to_addsi_score7"
2327 [(set (reg:CC_NZ CC_REGNUM)
2328 (compare:CC_NZ (match_operand:SI 1 "register_operand" "0,d")
2329 (neg:SI (match_operand:SI 2 "register_operand" "e,d"))))
2330 (clobber (match_scratch:SI 0 "=e,d"))]
2331 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
2332 "@
2333 add! %0, %2
2334 add.c %0, %1, %2"
2335 [(set_attr "type" "cmp")
2336 (set_attr "up_c" "yes")
2337 (set_attr "mode" "SI")])
2339 (define_insn "*cmpsi_to_addsi_score3"
2340 [(set (reg:CC_NZ CC_REGNUM)
2341 (compare:CC_NZ (match_operand:SI 1 "score_register_operand" "d")
2342 (neg:SI (match_operand:SI 2 "score_register_operand" "d"))))
2343 (clobber (match_scratch:SI 0 "=d"))]
2344 "(TARGET_SCORE3)"
2345 "add.c\t%0, %1, %2"
2346 [(set_attr "type" "cmp")
2347 (set_attr "length" "4")
2348 (set_attr "up_c" "yes")
2349 (set_attr "mode" "SI")])
2351 (define_insn "cmpsi_cc_score7"
2352 [(set (reg:CC CC_REGNUM)
2353 (compare:CC (match_operand:SI 0 "register_operand" "d,e,d")
2354 (match_operand:SI 1 "arith_operand" "L,e,d")))]
2355 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
2356 "@
2357 cmpi.c %0, %c1
2358 cmp! %0, %1
2359 cmp.c %0, %1"
2360 [(set_attr "type" "cmp")
2361 (set_attr "up_c" "yes")
2362 (set_attr "mode" "SI")])
2364 (define_insn "cmpsi_cc_score3"
2365 [(set (reg:CC CC_REGNUM)
2366 (compare:CC (match_operand:SI 0 "score_register_operand" "d,d,d")
2367 (match_operand:SI 1 "arith_operand" "O,L,d")))]
2368 "(TARGET_SCORE3)"
2369 "@
2370 cmpi!\t%0, %c1
2371 cmpi.c\t%0, %c1
2372 cmp!\t%0, %1"
2373 [(set_attr "type" "cmp")
2374 (set_attr "length" "2,4,2")
2375 (set_attr "up_c" "yes")
2376 (set_attr "mode" "SI")])
2378 (define_expand "beq"
2379 [(set (pc)
2380 (if_then_else (eq (reg:CC CC_REGNUM) (const_int 0))
2381 (label_ref (match_operand 0 "" ""))
2382 (pc)))]
2383 ""
2384 {
2385 score_gen_cmp (CCmode);
2386 })
2388 (define_expand "bne"
2389 [(set (pc)
2390 (if_then_else (ne (reg:CC CC_REGNUM) (const_int 0))
2391 (label_ref (match_operand 0 "" ""))
2392 (pc)))]
2393 ""
2394 {
2395 score_gen_cmp (CCmode);
2396 })
2398 (define_expand "bgt"
2399 [(set (pc)
2400 (if_then_else (gt (reg:CC CC_REGNUM) (const_int 0))
2401 (label_ref (match_operand 0 "" ""))
2402 (pc)))]
2403 ""
2404 {
2405 score_gen_cmp (CCmode);
2406 })
2408 (define_expand "ble"
2409 [(set (pc)
2410 (if_then_else (le (reg:CC CC_REGNUM) (const_int 0))
2411 (label_ref (match_operand 0 "" ""))
2412 (pc)))]
2413 ""
2414 {
2415 score_gen_cmp (CCmode);
2416 })
2418 (define_expand "bge"
2419 [(set (pc)
2420 (if_then_else (ge (reg:CC CC_REGNUM) (const_int 0))
2421 (label_ref (match_operand 0 "" ""))
2422 (pc)))]
2423 ""
2424 {
2425 score_gen_cmp (CCmode);
2426 })
2428 (define_expand "blt"
2429 [(set (pc)
2430 (if_then_else (lt (reg:CC CC_REGNUM) (const_int 0))
2431 (label_ref (match_operand 0 "" ""))
2432 (pc)))]
2433 ""
2434 {
2435 score_gen_cmp (CCmode);
2436 })
2438 (define_expand "bgtu"
2439 [(set (pc)
2440 (if_then_else (gtu (reg:CC CC_REGNUM) (const_int 0))
2441 (label_ref (match_operand 0 "" ""))
2442 (pc)))]
2443 ""
2444 {
2445 score_gen_cmp (CCmode);
2446 })
2448 (define_expand "bleu"
2449 [(set (pc)
2450 (if_then_else (leu (reg:CC CC_REGNUM) (const_int 0))
2451 (label_ref (match_operand 0 "" ""))
2452 (pc)))]
2453 ""
2454 {
2455 score_gen_cmp (CCmode);
2456 })
2458 (define_expand "bgeu"
2459 [(set (pc)
2460 (if_then_else (geu (reg:CC CC_REGNUM) (const_int 0))
2461 (label_ref (match_operand 0 "" ""))
2462 (pc)))]
2463 ""
2464 {
2465 score_gen_cmp (CCmode);
2466 })
2468 (define_expand "bltu"
2469 [(set (pc)
2470 (if_then_else (ltu (reg:CC CC_REGNUM) (const_int 0))
2471 (label_ref (match_operand 0 "" ""))
2472 (pc)))]
2473 ""
2474 {
2475 score_gen_cmp (CCmode);
2476 })
2478 (define_insn "*branch_n_score7"
2479 [(set (pc)
2480 (if_then_else
2481 (match_operator 0 "branch_n_operator"
2482 [(reg:CC_N CC_REGNUM)
2483 (const_int 0)])
2484 (label_ref (match_operand 1 "" ""))
2485 (pc)))]
2486 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
2487 "b%C0 %1"
2488 [(set_attr "type" "branch")])
2490 (define_insn "*branch_n_score3"
2491 [(set (pc)
2492 (if_then_else
2493 (match_operator 0 "branch_n_operator"
2494 [(reg:CC_N CC_REGNUM)
2495 (const_int 0)])
2496 (label_ref (match_operand 1 "" ""))
2497 (pc)))]
2498 "(TARGET_SCORE3)"
2499 "b%C0\t%1"
2500 [(set_attr "type" "branch")
2501 (set_attr "length" "4")])
2503 (define_insn "*branch_nz_score7"
2504 [(set (pc)
2505 (if_then_else
2506 (match_operator 0 "branch_nz_operator"
2507 [(reg:CC_NZ CC_REGNUM)
2508 (const_int 0)])
2509 (label_ref (match_operand 1 "" ""))
2510 (pc)))]
2511 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
2512 "b%C0 %1"
2513 [(set_attr "type" "branch")])
2515 (define_insn "*branch_nz_score3"
2516 [(set (pc)
2517 (if_then_else
2518 (match_operator 0 "branch_nz_operator"
2519 [(reg:CC_NZ CC_REGNUM)
2520 (const_int 0)])
2521 (label_ref (match_operand 1 "" ""))
2522 (pc)))]
2523 "(TARGET_SCORE3)"
2524 "b%C0\t%1"
2525 [(set_attr "type" "branch")
2526 (set_attr "length" "4")])
2529 (define_insn "*branch_cc_score7"
2530 [(set (pc)
2531 (if_then_else
2532 (match_operator 0 "comparison_operator"
2533 [(reg:CC CC_REGNUM)
2534 (const_int 0)])
2535 (label_ref (match_operand 1 "" ""))
2536 (pc)))]
2537 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
2538 "b%C0 %1"
2539 [(set_attr "type" "branch")])
2541 (define_insn "*branch_cc_score3"
2542 [(set (pc)
2543 (if_then_else
2544 (match_operator 0 "comparison_operator"
2545 [(reg:CC CC_REGNUM)
2546 (const_int 0)])
2547 (label_ref (match_operand 1 "" ""))
2548 (pc)))]
2549 "(TARGET_SCORE3)"
2550 "b%C0\t%1"
2551 [(set_attr "type" "branch")
2552 (set_attr "length" "4")])
2554 (define_insn "jump"
2555 [(set (pc)
2556 (label_ref (match_operand 0 "" "")))]
2557 ""
2558 {
2559 if (!flag_pic)
2560 return \"j\t%0\";
2561 else
2562 return \"b\t%0\";
2563 }
2564 [(set_attr "type" "jump")
2565 (set_attr "length" "4")])
2567 (define_expand "sibcall"
2568 [(parallel [(call (match_operand 0 "" "")
2569 (match_operand 1 "" ""))
2570 (use (match_operand 2 "" ""))])]
2571 ""
2572 {
2573 score_call (operands, true);
2574 DONE;
2575 })
2577 (define_insn "sibcall_internal_score7"
2578 [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "t,Z"))
2579 (match_operand 1 "" ""))
2580 (clobber (reg:SI RT_REGNUM))]
2581 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
2582 && SIBLING_CALL_P (insn)"
2583 {
2584 if (!flag_pic)
2585 switch (which_alternative)
2586 {
2587 case 0: return \"br%S0\t%0\";
2588 case 1: return \"j\t%0\";
2589 default: gcc_unreachable ();
2590 }
2591 else
2592 switch (which_alternative)
2593 {
2594 case 0: return \"mv\tr29, %0\;br\tr29\";
2595 case 1: return \"la\tr29, %0\;br\tr29\";
2596 default: gcc_unreachable ();
2597 }
2598 }
2599 [(set_attr "type" "call")])
2601 (define_insn "sibcall_internal_score3"
2602 [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "t,Z"))
2603 (match_operand 1 "" ""))
2604 (clobber (reg:SI RT_REGNUM))]
2605 "(TARGET_SCORE3) && (SIBLING_CALL_P (insn))"
2606 {
2607 if (!flag_pic)
2608 switch (which_alternative)
2609 {
2610 case 0: return \"br%S0\t%0\";
2611 case 1: return \"j\t%0\";
2612 default: gcc_unreachable ();
2613 }
2614 else
2615 switch (which_alternative)
2616 {
2617 case 0: return \"mv!\tr29, %0\;br!\tr29\";
2618 case 1: return \"ldi48\tr29, %0\;br!\tr29\";
2619 default: gcc_unreachable ();
2620 }
2621 }
2622 [(set_attr "type" "call")
2623 (set_attr "length" "4,8")])
2625 (define_expand "sibcall_value"
2626 [(parallel [(set (match_operand 0 "" "")
2627 (call (match_operand 1 "" "") (match_operand 2 "" "")))
2628 (use (match_operand 3 "" ""))])]
2629 ""
2630 {
2631 score_call_value (operands, true);
2632 DONE;
2633 })
2635 (define_insn "sibcall_value_internal_score7"
2636 [(set (match_operand 0 "register_operand" "=d,d")
2637 (call (mem:SI (match_operand:SI 1 "call_insn_operand" "t,Z"))
2638 (match_operand 2 "" "")))
2639 (clobber (reg:SI RT_REGNUM))]
2640 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
2641 && SIBLING_CALL_P (insn)"
2642 {
2643 if (!flag_pic)
2644 switch (which_alternative)
2645 {
2646 case 0: return \"br%S1\t%1\";
2647 case 1: return \"j\t%1\";
2648 default: gcc_unreachable ();
2649 }
2650 else
2651 switch (which_alternative)
2652 {
2653 case 0: return \"mv\tr29, %1\;br\tr29\";
2654 case 1: return \"la\tr29, %1\;br\tr29\";
2655 default: gcc_unreachable ();
2656 }
2657 }
2658 [(set_attr "type" "call")])
2660 (define_insn "sibcall_value_internal_score3"
2661 [(set (match_operand 0 "score_register_operand" "=d,d")
2662 (call (mem:SI (match_operand:SI 1 "call_insn_operand" "t,Z"))
2663 (match_operand 2 "" "")))
2664 (clobber (reg:SI RT_REGNUM))]
2665 "(TARGET_SCORE3) && (SIBLING_CALL_P (insn))"
2666 {
2667 if (!flag_pic)
2668 switch (which_alternative)
2669 {
2670 case 0: return \"br%S1\t%1\";
2671 case 1: return \"j\t%1\";
2672 default: gcc_unreachable ();
2673 }
2674 else
2675 switch (which_alternative)
2676 {
2677 case 0: return \"mv!\tr29, %1\;br!\tr29\";
2678 case 1: return \"ldi48\tr29, %1\;br!\tr29\";
2679 default: gcc_unreachable ();
2680 }
2681 }
2682 [(set_attr "length" "4,8")
2683 (set_attr "type" "call")])
2685 (define_expand "call"
2686 [(parallel [(call (match_operand 0 "" "") (match_operand 1 "" ""))
2687 (use (match_operand 2 "" ""))])]
2688 ""
2689 {
2690 score_call (operands, false);
2691 DONE;
2692 })
2694 (define_insn "call_internal_score7"
2695 [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "d,Z"))
2696 (match_operand 1 "" ""))
2697 (clobber (reg:SI RA_REGNUM))]
2698 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
2699 {
2700 if (!flag_pic)
2701 switch (which_alternative)
2702 {
2703 case 0: return \"brl%S0\t%0\";
2704 case 1: return \"jl\t%0\";
2705 default: gcc_unreachable ();
2706 }
2707 else
2708 switch (which_alternative)
2709 {
2710 case 0: return \"mv\tr29, %0\;brl\tr29\";
2711 case 1: return \"la\tr29, %0\;brl\tr29\";
2712 default: gcc_unreachable ();
2713 }
2714 }
2715 [(set_attr "type" "call")])
2717 (define_insn "call_internal_score3"
2718 [(call (mem:SI (match_operand:SI 0 "call_insn_operand" "d,Z"))
2719 (match_operand 1 "" ""))
2720 (clobber (reg:SI RA_REGNUM))]
2721 "(TARGET_SCORE3)"
2722 {
2723 if (!flag_pic)
2724 switch (which_alternative)
2725 {
2726 case 0: return \"brl!\t%0\";
2727 case 1: return \"jl\t%0\";
2728 default: gcc_unreachable ();
2729 }
2730 else
2731 switch (which_alternative)
2732 {
2733 case 0: return \"mv!\tr29, %0\;brl!\tr29\";
2734 case 1: return \"ldi48\tr29, %0\;brl!\tr29\";
2735 default: gcc_unreachable ();
2736 }
2737 }
2738 [(set_attr "length" "4,8")
2739 (set_attr "type" "call")])
2741 (define_expand "call_value"
2742 [(parallel [(set (match_operand 0 "" "")
2743 (call (match_operand 1 "" "") (match_operand 2 "" "")))
2744 (use (match_operand 3 "" ""))])]
2745 ""
2746 {
2747 score_call_value (operands, false);
2748 DONE;
2749 })
2751 (define_insn "call_value_internal_score7"
2752 [(set (match_operand 0 "register_operand" "=d,d")
2753 (call (mem:SI (match_operand:SI 1 "call_insn_operand" "d,Z"))
2754 (match_operand 2 "" "")))
2755 (clobber (reg:SI RA_REGNUM))]
2756 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
2757 {
2758 if (!flag_pic)
2759 switch (which_alternative)
2760 {
2761 case 0: return \"brl%S1\t%1\";
2762 case 1: return \"jl\t%1\";
2763 default: gcc_unreachable ();
2764 }
2765 else
2766 switch (which_alternative)
2767 {
2768 case 0: return \"mv\tr29, %1\;brl\tr29\";
2769 case 1: return \"la\tr29, %1\;brl\tr29\";
2770 default: gcc_unreachable ();
2771 }
2772 }
2773 [(set_attr "type" "call")])
2775 (define_insn "call_value_internal_score3"
2776 [(set (match_operand 0 "score_register_operand" "=d,d")
2777 (call (mem:SI (match_operand:SI 1 "call_insn_operand" "d,Z"))
2778 (match_operand 2 "" "")))
2779 (clobber (reg:SI RA_REGNUM))]
2780 "(TARGET_SCORE3)"
2781 {
2782 if (!flag_pic)
2783 switch (which_alternative)
2784 {
2785 case 0: return \"brl!\t%1\";
2786 case 1: return \"jl\t%1\";
2787 default: gcc_unreachable ();
2788 }
2789 else
2790 switch (which_alternative)
2791 {
2792 case 0: return \"mv!\tr29, %1\;brl!\tr29\";
2793 case 1: return \"ldi48\tr29, %1\;brl!\tr29\";
2794 default: gcc_unreachable ();
2795 }
2796 }
2797 [(set_attr "length" "4,8")
2798 (set_attr "type" "call")])
2800 (define_expand "indirect_jump"
2801 [(set (pc) (match_operand 0 "score_register_operand" "d"))]
2802 ""
2803 {
2804 rtx dest;
2805 dest = operands[0];
2806 if (GET_CODE (dest) != REG
2807 || GET_MODE (dest) != Pmode)
2808 operands[0] = copy_to_mode_reg (Pmode, dest);
2810 emit_jump_insn (gen_indirect_jump_internal_score (operands[0]));
2811 DONE;
2812 })
2814 (define_insn "indirect_jump_internal_score"
2815 [(set (pc) (match_operand:SI 0 "score_register_operand" "d"))]
2816 ""
2817 "br%S0 %0"
2818 [(set_attr "type" "jump")])
2820 (define_expand "casesi"
2821 [(match_operand:SI 0 "score_register_operand" "") ; index to jump on
2822 (match_operand:SI 1 "const_int_operand" "") ; lower bound
2823 (match_operand:SI 2 "const_int_operand" "") ; total range
2824 (match_operand:SI 3 "" "") ; table label
2825 (match_operand:SI 4 "" "")] ; Out of range label
2826 "TARGET_SCORE3"
2827 {
2828 rtx reg;
2829 if (operands[1] != const0_rtx)
2830 {
2831 reg = gen_reg_rtx (SImode);
2832 emit_insn (gen_addsi3 (reg, operands[0],
2833 GEN_INT (-INTVAL (operands[1]))));
2834 operands[0] = reg;
2835 }
2837 if (!CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'L'))
2838 operands[2] = force_reg (SImode, operands[2]);
2840 reg = gen_reg_rtx (SImode);
2841 emit_jump_insn (gen_score3_casesi_internal (operands[0], operands[2],
2842 operands[3], operands[4], reg));
2843 DONE;
2844 })
2846 (define_insn "score3_casesi_internal"
2847 [(parallel [(set (pc)
2848 (if_then_else
2849 (leu (match_operand:SI 0 "score_register_operand" "e")
2850 (match_operand:SI 1 "arith_operand" "dL"))
2851 (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
2852 (label_ref (match_operand 2 "" ""))))
2853 (label_ref (match_operand 3 "" ""))))
2854 (clobber (reg:CC CC_REGNUM))
2855 (clobber (match_operand:SI 4 "score_register_operand" "=e"))
2856 (use (label_ref (match_dup 2)))])]
2857 "TARGET_SCORE3 && !flag_pic"
2858 "*
2859 return score_output_casesi(operands);
2860 "
2861 [(set_attr "length" "20")])
2863 (define_expand "tablejump"
2864 [(set (pc)
2865 (match_operand 0 "score_register_operand" "d"))
2866 (use (label_ref (match_operand 1 "" "")))]
2867 ""
2868 {
2869 if (TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
2870 emit_jump_insn (gen_tablejump_internal_score7 (operands[0], operands[1]));
2871 else if (TARGET_SCORE3)
2872 emit_jump_insn (gen_tablejump_internal_score3 (operands[0], operands[1]));
2874 DONE;
2875 })
2877 (define_insn "tablejump_internal_score7"
2878 [(set (pc)
2879 (match_operand:SI 0 "register_operand" "d"))
2880 (use (label_ref (match_operand 1 "" "")))]
2881 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
2882 {
2883 if (flag_pic)
2884 return \"mv\tr29, %0\;.cpadd\tr29\;br\tr29\";
2885 else
2886 return \"br%S0\t%0\";
2887 }
2888 [(set_attr "type" "jump")])
2890 (define_insn "tablejump_internal_score3"
2891 [(set (pc)
2892 (match_operand:SI 0 "score_register_operand" "d"))
2893 (use (label_ref (match_operand 1 "" "")))]
2894 "(TARGET_SCORE3)"
2895 {
2896 if (flag_pic)
2897 return \"mv!\tr29, %0\;.cpadd\tr29\;br!\tr29\";
2898 else
2899 return \"br%S0\t%0\";
2900 }
2901 [(set_attr "type" "jump")
2902 (set_attr "length" "8")])
2904 (define_expand "prologue"
2905 [(const_int 1)]
2906 ""
2907 {
2908 score_prologue ();
2909 DONE;
2910 })
2912 (define_expand "epilogue"
2913 [(const_int 2)]
2914 ""
2915 {
2916 score_epilogue (false);
2917 DONE;
2918 })
2920 (define_expand "sibcall_epilogue"
2921 [(const_int 2)]
2922 ""
2923 {
2924 score_epilogue (true);
2925 DONE;
2926 })
2928 (define_insn "return_internal_score7"
2929 [(return)
2930 (use (match_operand 0 "pmode_register_operand" "d"))]
2931 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
2932 "br%S0\t%0")
2934 (define_insn "return_internal_score3"
2935 [(return)
2936 (use (match_operand 0 "pmode_register_operand" "d"))]
2937 "(TARGET_SCORE3)"
2938 "br%S0\t%0"
2939 [(set_attr "length" "4")])
2941 (define_insn "nop"
2942 [(const_int 0)]
2943 ""
2944 "#nop!"
2945 )
2947 (define_insn "cpload_score7"
2948 [(unspec_volatile:SI [(const_int 1)] CPLOAD)]
2949 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
2950 && flag_pic"
2951 ".cpload\tr29"
2952 )
2954 (define_insn "cpload_score3"
2955 [(unspec_volatile:SI [(const_int 1)] CPLOAD)]
2956 "(TARGET_SCORE3) && flag_pic"
2957 ".cpload\tr29"
2958 [(set_attr "length" "4")])
2960 (define_insn "cprestore_use_fp_score7"
2961 [(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE)
2962 (use (reg:SI FP_REGNUM))]
2963 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
2964 && flag_pic"
2965 ".cprestore\tr2, %0"
2966 )
2968 (define_insn "cprestore_use_fp_score3"
2969 [(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE)
2970 (use (reg:SI FP_REGNUM))]
2971 "(TARGET_SCORE3) && flag_pic"
2972 ".cprestore\tr2, %0"
2973 [(set_attr "length" "4")])
2975 (define_insn "cprestore_use_sp_score7"
2976 [(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE)
2977 (use (reg:SI SP_REGNUM))]
2978 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)
2979 && flag_pic"
2980 ".cprestore\tr0, %0"
2981 )
2983 (define_insn "cprestore_use_sp_score3"
2984 [(unspec_volatile:SI [(match_operand:SI 0 "" "")] CPRESTORE)
2985 (use (reg:SI SP_REGNUM))]
2986 "(TARGET_SCORE3) && flag_pic"
2987 ".cprestore\tr0, %0"
2988 [(set_attr "length" "4")])
2990 (define_expand "doloop_end"
2991 [(use (match_operand 0 "" "")) ; loop pseudo
2992 (use (match_operand 1 "" "")) ; iterations; zero if unknown
2993 (use (match_operand 2 "" "")) ; max iterations
2994 (use (match_operand 3 "" "")) ; loop level
2995 (use (match_operand 4 "" ""))] ; label
2996 "!TARGET_NHWLOOP"
2997 {
2998 if (INTVAL (operands[3]) > 1)
2999 FAIL;
3001 if (GET_MODE (operands[0]) == SImode)
3002 {
3003 rtx sr0 = gen_rtx_REG (SImode, CN_REGNUM);
3004 emit_jump_insn (gen_doloop_end_si (sr0, operands[4]));
3005 }
3006 else
3007 FAIL;
3009 DONE;
3010 })
3012 (define_insn "doloop_end_si"
3013 [(set (pc)
3014 (if_then_else
3015 (ne (match_operand:SI 0 "sr0_operand" "")
3016 (const_int 0))
3017 (label_ref (match_operand 1 "" ""))
3018 (pc)))
3019 (set (match_dup 0)
3020 (plus:SI (match_dup 0)
3021 (const_int -1)))
3022 (clobber (reg:CC CC_REGNUM))]
3023 "!TARGET_NHWLOOP"
3024 "bcnz %1"
3025 [(set_attr "type" "branch")
3026 (set_attr "length" "4")])
3028 (define_insn "pushsi_score7"
3029 [(set (match_operand:SI 0 "push_operand" "=<")
3030 (match_operand:SI 1 "register_operand" "d"))]
3031 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
3032 "push!\t%1, [r0]"
3033 [(set_attr "type" "store")
3034 (set_attr "mode" "SI")])
3036 (define_insn "pushsi_score3"
3037 [(set (match_operand:SI 0 "push_operand" "=<")
3038 (match_operand:SI 1 "register_operand" "d"))]
3039 "(TARGET_SCORE3)"
3040 "push!\t%1"
3041 [(set_attr "type" "store")
3042 (set_attr "length" "2")
3043 (set_attr "mode" "SI")])
3045 (define_insn "popsi_score7"
3046 [(set (match_operand:SI 0 "register_operand" "=d")
3047 (match_operand:SI 1 "pop_operand" ">"))]
3048 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
3049 "pop!\t%0, [r0]"
3050 [(set_attr "type" "store")
3051 (set_attr "mode" "SI")])
3053 (define_insn "popsi_score3"
3054 [(set (match_operand:SI 0 "register_operand" "=d")
3055 (match_operand:SI 1 "pop_operand" ">"))]
3056 "(TARGET_SCORE3)"
3057 "pop!\t%0"
3058 [(set_attr "type" "store")
3059 (set_attr "length" "2")
3060 (set_attr "mode" "SI")])
3062 (define_expand "load_multiple"
3063 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
3064 (match_operand:SI 1 "" ""))
3065 (use (match_operand:SI 2 "" ""))
3066 (clobber (reg:SI 0))])]
3067 "(TARGET_SCORE3)"
3068 {
3069 int regno, count, i;
3071 if (GET_CODE (operands[2]) != CONST_INT
3072 || INTVAL (operands[2]) < 2
3073 || GET_CODE (operands[1]) != MEM
3074 || XEXP (operands[1], 0) != stack_pointer_rtx
3075 || GET_CODE (operands[0]) != REG)
3076 FAIL;
3078 count = INTVAL (operands[2]);
3079 regno = REGNO (operands[0]);
3081 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
3083 for (i = 0; i < count; i++)
3084 XVECEXP (operands[3], 0, i)
3085 = gen_rtx_SET (VOIDmode,
3086 gen_rtx_REG (SImode, regno + i),
3087 gen_rtx_MEM (SImode, gen_rtx_POST_INC (SImode, stack_pointer_rtx)));
3088 })
3090 (define_insn ""
3091 [(match_parallel 0 "score_load_multiple_operation"
3092 [(set (match_operand:SI 1 "register_operand" "=d")
3093 (mem:SI (post_inc:SI (reg:SI SP_REGNUM))))])]
3094 "(TARGET_SCORE3)"
3095 {
3096 return score_rpop (operands);
3097 }
3098 [(set_attr "length" "2")])
3100 (define_expand "store_multiple"
3101 [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
3102 (match_operand:SI 1 "" ""))
3103 (use (match_operand:SI 2 "" ""))
3104 (clobber (reg:SI 0))])]
3105 "(TARGET_SCORE3)"
3106 {
3107 int regno, count, i;
3109 if (GET_CODE (operands[2]) != CONST_INT
3110 || INTVAL (operands[2]) < 2
3111 || GET_CODE (operands[0]) != MEM
3112 || XEXP (operands[0], 0) != stack_pointer_rtx
3113 || GET_CODE (operands[1]) != REG)
3114 FAIL;
3116 count = INTVAL (operands[2]);
3117 regno = REGNO (operands[1]);
3119 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
3121 for (i = 0; i < count; i++)
3122 XVECEXP (operands[3], 0, i)
3123 = gen_rtx_SET (VOIDmode,
3124 gen_rtx_MEM (SImode, gen_rtx_PRE_DEC (SImode, stack_pointer_rtx)),
3125 gen_rtx_REG (SImode, regno + i));
3126 })
3128 (define_insn ""
3129 [(match_parallel 0 "score_store_multiple_operation"
3130 [(set (mem:SI (pre_dec:SI (reg:SI SP_REGNUM)))
3131 (match_operand:SI 1 "register_operand" "d"))])]
3132 "(TARGET_SCORE3)"
3133 {
3134 return score_rpush (operands);
3135 }
3136 [(set_attr "length" "2")])
3138 (define_peephole2
3139 [(set (match_operand:SI 0 "g32reg_operand" "")
3140 (match_operand:SI 1 "loreg_operand" ""))
3141 (set (match_operand:SI 2 "g32reg_operand" "")
3142 (match_operand:SI 3 "hireg_operand" ""))]
3143 ""
3144 [(parallel
3145 [(set (match_dup 0) (match_dup 1))
3146 (set (match_dup 2) (match_dup 3))])])
3148 (define_peephole2
3149 [(set (match_operand:SI 0 "g32reg_operand" "")
3150 (match_operand:SI 1 "hireg_operand" ""))
3151 (set (match_operand:SI 2 "g32reg_operand" "")
3152 (match_operand:SI 3 "loreg_operand" ""))]
3153 ""
3154 [(parallel
3155 [(set (match_dup 2) (match_dup 3))
3156 (set (match_dup 0) (match_dup 1))])])
3158 (define_insn "movhilo"
3159 [(parallel
3160 [(set (match_operand:SI 0 "register_operand" "=d")
3161 (match_operand:SI 1 "loreg_operand" ""))
3162 (set (match_operand:SI 2 "register_operand" "=d")
3163 (match_operand:SI 3 "hireg_operand" ""))])]
3164 ""
3165 "mfcehl\t%2, %0"
3166 [(set_attr "type" "fce")
3167 (set_attr "mode" "SI")])
3169 (define_expand "movsicc"
3170 [(set (match_operand:SI 0 "register_operand" "")
3171 (if_then_else:SI (match_operator 1 "comparison_operator"
3172 [(reg:CC CC_REGNUM) (const_int 0)])
3173 (match_operand:SI 2 "register_operand" "")
3174 (match_operand:SI 3 "register_operand" "")))]
3175 ""
3176 {
3177 score_movsicc (operands);
3178 })
3180 (define_insn "movsicc_internal_score7"
3181 [(set (match_operand:SI 0 "register_operand" "=d")
3182 (if_then_else:SI (match_operator 1 "comparison_operator"
3183 [(reg:CC CC_REGNUM) (const_int 0)])
3184 (match_operand:SI 2 "arith_operand" "d")
3185 (match_operand:SI 3 "arith_operand" "0")))]
3186 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
3187 "mv%C1\t%0, %2"
3188 [(set_attr "type" "cndmv")
3189 (set_attr "mode" "SI")])
3191 (define_insn "movsicc_internal_score3"
3192 [(set (match_operand:SI 0 "register_operand" "=d")
3193 (if_then_else:SI (match_operator 1 "comparison_operator"
3194 [(reg:CC CC_REGNUM) (const_int 0)])
3195 (match_operand:SI 2 "arith_operand" "d")
3196 (match_operand:SI 3 "arith_operand" "0")))]
3197 "(TARGET_SCORE3)"
3198 "mv%G1\t%0, %2"
3199 [(set_attr "type" "cndmv")
3200 (set_attr "length" "4")
3201 (set_attr "mode" "SI")])
3203 (define_insn "zero_extract_bittst_score7"
3204 [(set (reg:CC_NZ CC_REGNUM)
3205 (compare:CC_NZ (unspec:SI
3206 [(match_operand:SI 0 "register_operand" "*e,d")
3207 (match_operand:SI 1 "const_uimm5" "")]
3208 BITTST)
3209 (const_int 0)))]
3210 "(TARGET_SCORE5 || TARGET_SCORE5U || TARGET_SCORE7 || TARGET_SCORE7D)"
3211 "@
3212 bittst!\t%0, %c1
3213 bittst.c\t%0, %c1"
3214 [(set_attr "type" "arith")
3215 (set_attr "up_c" "yes")
3216 (set_attr "mode" "SI")])
3218 (define_insn "zero_extract_bittst_score3"
3219 [(set (reg:CC_NZ CC_REGNUM)
3220 (compare:CC_NZ (unspec:SI
3221 [(match_operand:SI 0 "register_operand" "e,d")
3222 (match_operand:SI 1 "const_uimm5" "")]
3223 BITTST)
3224 (const_int 0)))]
3225 "(TARGET_SCORE3)"
3226 "@
3227 bittst!\t%0, %c1
3228 bittst.c\t%0, %c1"
3229 [(set_attr "type" "arith")
3230 (set_attr "length" "2,4")
3231 (set_attr "up_c" "yes")
3232 (set_attr "mode" "SI")])
3234 (define_expand "extzv"
3235 [(set (match_operand:SI 0 "register_operand" "")
3236 (zero_extract (match_operand:SI 1 "memory_operand" "")
3237 (match_operand:SI 2 "immediate_operand" "")
3238 (match_operand:SI 3 "immediate_operand" "")))]
3239 "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
3240 && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
3241 || (TARGET_SCORE3 && TARGET_ULS)"
3242 {
3243 if (score_unaligned_load (operands))
3244 DONE;
3245 else
3246 FAIL;
3247 })
3249 (define_expand "insv"
3250 [(set (zero_extract (match_operand:SI 0 "memory_operand" "")
3251 (match_operand:SI 1 "immediate_operand" "")
3252 (match_operand:SI 2 "immediate_operand" ""))
3253 (match_operand:SI 3 "register_operand" ""))]
3254 "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
3255 && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
3256 || (TARGET_SCORE3 && TARGET_ULS)"
3257 {
3258 if (score_unaligned_store (operands))
3259 DONE;
3260 else
3261 FAIL;
3262 })
3264 (define_expand "extv"
3265 [(set (match_operand:SI 0 "register_operand" "")
3266 (sign_extract (match_operand:SI 1 "memory_operand" "")
3267 (match_operand:SI 2 "immediate_operand" "")
3268 (match_operand:SI 3 "immediate_operand" "")))]
3269 "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
3270 && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
3271 || (TARGET_SCORE3 && TARGET_ULS)"
3272 {
3273 if (score_unaligned_load (operands))
3274 DONE;
3275 else
3276 FAIL;
3277 })
3279 (define_expand "movmemsi"
3280 [(parallel [(set (match_operand:BLK 0 "general_operand")
3281 (match_operand:BLK 1 "general_operand"))
3282 (use (match_operand:SI 2 ""))
3283 (use (match_operand:SI 3 "const_int_operand"))])]
3284 "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
3285 && (TARGET_ULS))
3286 || (TARGET_SCORE3 && TARGET_ULS)"
3287 {
3288 if (score_block_move (operands))
3289 DONE;
3290 else
3291 FAIL;
3292 })
3294 (define_insn "move_lbu_a"
3295 [(set (match_operand:SI 0 "register_operand" "=d")
3296 (plus:SI (match_operand:SI 1 "register_operand" "0")
3297 (match_operand:SI 2 "const_simm12" "")))
3298 (set (match_operand:QI 3 "register_operand" "=d")
3299 (mem:QI (match_dup 1)))]
3300 ""
3301 "lbu\t%3, [%1]+, %2"
3302 [(set_attr "type" "load")
3303 (set_attr "length" "4")
3304 (set_attr "mode" "QI")])
3306 (define_insn "move_lhu_a"
3307 [(set (match_operand:SI 0 "register_operand" "=d")
3308 (plus:SI (match_operand:SI 1 "register_operand" "0")
3309 (match_operand:SI 2 "const_simm12" "")))
3310 (set (match_operand:HI 3 "register_operand" "=d")
3311 (mem:HI (match_dup 1)))]
3312 ""
3313 "lhu\t%3, [%1]+, %2"
3314 [(set_attr "type" "load")
3315 (set_attr "length" "4")
3316 (set_attr "mode" "HI")])
3318 (define_insn "move_lw_a"
3319 [(set (match_operand:SI 0 "register_operand" "=d")
3320 (plus:SI (match_operand:SI 1 "register_operand" "0")
3321 (match_operand:SI 2 "const_simm12" "")))
3322 (set (match_operand:SI 3 "register_operand" "=d")
3323 (mem:SI (match_dup 1)))]
3324 ""
3325 "lw\t%3, [%1]+, %2"
3326 [(set_attr "type" "load")
3327 (set_attr "length" "4")
3328 (set_attr "mode" "SI")])
3330 (define_insn "move_sb_a"
3331 [(set (match_operand:SI 0 "register_operand" "=d")
3332 (plus:SI (match_operand:SI 1 "register_operand" "0")
3333 (match_operand:SI 2 "const_simm12" "")))
3334 (set (mem:QI (match_dup 1))
3335 (match_operand:QI 3 "register_operand" "d"))]
3336 ""
3337 "sb\t%3, [%1]+, %2"
3338 [(set_attr "type" "store")
3339 (set_attr "length" "4")
3340 (set_attr "mode" "QI")])
3342 (define_insn "move_sh_a"
3343 [(set (match_operand:SI 0 "register_operand" "=d")
3344 (plus:SI (match_operand:SI 1 "register_operand" "0")
3345 (match_operand:SI 2 "const_simm12" "")))
3346 (set (mem:HI (match_dup 1))
3347 (match_operand:HI 3 "register_operand" "d"))]
3348 ""
3349 "sh\t%3, [%1]+, %2"
3350 [(set_attr "type" "store")
3351 (set_attr "length" "4")
3352 (set_attr "mode" "HI")])
3354 (define_insn "move_sw_a"
3355 [(set (match_operand:SI 0 "register_operand" "=d")
3356 (plus:SI (match_operand:SI 1 "register_operand" "0")
3357 (match_operand:SI 2 "const_simm12" "")))
3358 (set (mem:SI (match_dup 1))
3359 (match_operand:SI 3 "register_operand" "d"))]
3360 ""
3361 "sw\t%3, [%1]+, %2"
3362 [(set_attr "type" "store")
3363 (set_attr "length" "4")
3364 (set_attr "mode" "SI")])
3366 (define_insn "move_lbu_b"
3367 [(set (match_operand:SI 0 "register_operand" "=d")
3368 (plus:SI (match_operand:SI 1 "register_operand" "0")
3369 (match_operand:SI 2 "const_simm12" "")))
3370 (set (match_operand:QI 3 "register_operand" "=d")
3371 (mem:QI (plus:SI (match_dup 1)
3372 (match_dup 2))))]
3373 ""
3374 "lbu\t%3, [%1, %2]+"
3375 [(set_attr "type" "load")
3376 (set_attr "length" "4")
3377 (set_attr "mode" "QI")])
3379 (define_insn "move_lhu_b"
3380 [(set (match_operand:SI 0 "register_operand" "=d")
3381 (plus:SI (match_operand:SI 1 "register_operand" "0")
3382 (match_operand:SI 2 "const_simm12" "")))
3383 (set (match_operand:HI 3 "register_operand" "=d")
3384 (mem:HI (plus:SI (match_dup 1)
3385 (match_dup 2))))]
3386 ""
3387 "lhu\t%3, [%1, %2]+"
3388 [(set_attr "type" "load")
3389 (set_attr "length" "4")
3390 (set_attr "mode" "HI")])
3392 (define_insn "move_lw_b"
3393 [(set (match_operand:SI 0 "register_operand" "=d")
3394 (plus:SI (match_operand:SI 1 "register_operand" "0")
3395 (match_operand:SI 2 "const_simm12" "")))
3396 (set (match_operand:SI 3 "register_operand" "=d")
3397 (mem:SI (plus:SI (match_dup 1)
3398 (match_dup 2))))]
3399 ""
3400 "lw\t%3, [%1, %2]+"
3401 [(set_attr "type" "load")
3402 (set_attr "length" "4")
3403 (set_attr "mode" "SI")])
3405 (define_insn "move_sb_b"
3406 [(set (match_operand:SI 0 "register_operand" "=d")
3407 (plus:SI (match_operand:SI 1 "register_operand" "0")
3408 (match_operand:SI 2 "const_simm12" "")))
3409 (set (mem:QI (plus:SI (match_dup 1)
3410 (match_dup 2)))
3411 (match_operand:QI 3 "register_operand" "d"))]
3412 ""
3413 "sb\t%3, [%1, %2]+"
3414 [(set_attr "type" "store")
3415 (set_attr "length" "4")
3416 (set_attr "mode" "QI")])
3418 (define_insn "move_sh_b"
3419 [(set (match_operand:SI 0 "register_operand" "=d")
3420 (plus:SI (match_operand:SI 1 "register_operand" "0")
3421 (match_operand:SI 2 "const_simm12" "")))
3422 (set (mem:HI (plus:SI (match_dup 1)
3423 (match_dup 2)))
3424 (match_operand:HI 3 "register_operand" "d"))]
3425 ""
3426 "sh\t%3, [%1, %2]+"
3427 [(set_attr "type" "store")
3428 (set_attr "length" "4")
3429 (set_attr "mode" "HI")])
3431 (define_insn "move_sw_b"
3432 [(set (match_operand:SI 0 "register_operand" "=d")
3433 (plus:SI (match_operand:SI 1 "register_operand" "0")
3434 (match_operand:SI 2 "const_simm12" "")))
3435 (set (mem:SI (plus:SI (match_dup 1)
3436 (match_dup 2)))
3437 (match_operand:SI 3 "register_operand" "d"))]
3438 ""
3439 "sw\t%3, [%1, %2]+"
3440 [(set_attr "type" "store")
3441 (set_attr "length" "4")
3442 (set_attr "mode" "SI")])
3444 (define_insn "move_lcb"
3445 [(set (match_operand:SI 0 "register_operand" "=d")
3446 (plus:SI (match_operand:SI 1 "register_operand" "0")
3447 (const_int 4)))
3448 (set (reg:SI LC_REGNUM)
3449 (unspec:SI [(mem:BLK (match_dup 1))] LCB))]
3450 "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
3451 && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
3452 || (TARGET_SCORE3 && TARGET_ULS)"
3453 "lcb\t[%1]+"
3454 [(set_attr "type" "load")
3455 (set_attr "length" "4")
3456 (set_attr "mode" "SI")])
3458 (define_insn "move_lcw"
3459 [(set (match_operand:SI 0 "register_operand" "=d")
3460 (plus:SI (match_operand:SI 1 "register_operand" "0")
3461 (const_int 4)))
3462 (set (match_operand:SI 2 "register_operand" "=d")
3463 (unspec:SI [(mem:BLK (match_dup 1))
3464 (reg:SI LC_REGNUM)] LCW))
3465 (set (reg:SI LC_REGNUM)
3466 (unspec:SI [(mem:BLK (match_dup 1))] LCB))]
3467 "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
3468 && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
3469 || (TARGET_SCORE3 && TARGET_ULS)"
3470 "lcw\t%2, [%1]+"
3471 [(set_attr "type" "load")
3472 (set_attr "length" "4")
3473 (set_attr "mode" "SI")])
3475 (define_insn "move_lce"
3476 [(set (match_operand:SI 0 "register_operand" "=d")
3477 (plus:SI (match_operand:SI 1 "register_operand" "0")
3478 (const_int 4)))
3479 (set (match_operand:SI 2 "register_operand" "=d")
3480 (unspec:SI [(mem:BLK (match_dup 1))
3481 (reg:SI LC_REGNUM)] LCE))]
3482 "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
3483 && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
3484 || (TARGET_SCORE3 && TARGET_ULS)"
3485 "lce\t%2, [%1]+"
3486 [(set_attr "type" "load")
3487 (set_attr "length" "4")
3488 (set_attr "mode" "SI")])
3490 (define_insn "move_scb"
3491 [(set (match_operand:SI 0 "register_operand" "=d")
3492 (plus:SI (match_operand:SI 1 "register_operand" "0")
3493 (const_int 4)))
3494 (set (mem:BLK (match_dup 1))
3495 (unspec:BLK [(match_operand:SI 2 "register_operand" "d")] SCB))
3496 (set (reg:SI SC_REGNUM)
3497 (unspec:SI [(match_dup 2)] SCLC))]
3498 "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
3499 && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
3500 || (TARGET_SCORE3 && TARGET_ULS)"
3501 "scb\t%2, [%1]+"
3502 [(set_attr "type" "store")
3503 (set_attr "length" "4")
3504 (set_attr "mode" "SI")])
3506 (define_insn "move_scw"
3507 [(set (match_operand:SI 0 "register_operand" "=d")
3508 (plus:SI (match_operand:SI 1 "register_operand" "0")
3509 (const_int 4)))
3510 (set (mem:BLK (match_dup 1))
3511 (unspec:BLK [(match_operand:SI 2 "register_operand" "d")
3512 (reg:SI SC_REGNUM)] SCW))
3513 (set (reg:SI SC_REGNUM)
3514 (unspec:SI [(match_dup 2)] SCLC))]
3515 "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
3516 && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
3517 || (TARGET_SCORE3 && TARGET_ULS)"
3518 "scw\t%2, [%1]+"
3519 [(set_attr "type" "store")
3520 (set_attr "length" "4")
3521 (set_attr "mode" "SI")])
3523 (define_insn "move_sce"
3524 [(set (match_operand:SI 0 "register_operand" "=d")
3525 (plus:SI (match_operand:SI 1 "register_operand" "0")
3526 (const_int 4)))
3527 (set (mem:BLK (match_dup 1))
3528 (unspec:BLK [(reg:SI SC_REGNUM)] SCE))]
3529 "((TARGET_SCORE5 || TARGET_SCORE7 || TARGET_SCORE7D)
3530 && (!TARGET_LITTLE_ENDIAN) && (TARGET_ULS))
3531 || (TARGET_SCORE3 && TARGET_ULS)"
3532 "sce [%1]+"
3533 [(set_attr "type" "store")
3534 (set_attr "length" "4")
3535 (set_attr "mode" "SI")])
3537 (define_insn "andsi3_extzh"
3538 [(set (match_operand:SI 0 "register_operand" "=d")
3539 (and:SI (match_operand:SI 1 "register_operand" "d")
3540 (const_int 65535)))]
3541 ""
3542 "extzh\t%0, %1"
3543 [(set_attr "type" "arith")
3544 (set_attr "length" "4")
3545 (set_attr "mode" "SI")])
3547 (define_insn "clzsi2"
3548 [(set (match_operand:SI 0 "register_operand" "=d")
3549 (clz:SI (match_operand:SI 1 "register_operand" "d")))]
3550 "(TARGET_SCORE7D || TARGET_SCORE3)"
3551 "clz\t%0, %1"
3552 [(set_attr "type" "arith")
3553 (set_attr "mode" "SI")])
3555 (define_insn "smaxsi3"
3556 [(set (match_operand:SI 0 "register_operand" "=d")
3557 (smax:SI (match_operand:SI 1 "register_operand" "d")
3558 (match_operand:SI 2 "register_operand" "d")))]
3559 "(TARGET_SCORE7D || TARGET_SCORE3D)"
3560 "max\t%0, %1, %2"
3561 [(set_attr "type" "arith")
3562 (set_attr "mode" "SI")])
3564 (define_insn "sminsi3"
3565 [(set (match_operand:SI 0 "register_operand" "=d")
3566 (smin:SI (match_operand:SI 1 "register_operand" "d")
3567 (match_operand:SI 2 "register_operand" "d")))]
3568 "(TARGET_SCORE7D || TARGET_SCORE3D)"
3569 "min\t%0, %1, %2"
3570 [(set_attr "type" "arith")
3571 (set_attr "mode" "SI")])
3573 (define_insn "abssi2"
3574 [(set (match_operand:SI 0 "register_operand" "=d")
3575 (abs:SI (match_operand:SI 1 "register_operand" "d")))]
3576 "(TARGET_SCORE7D || TARGET_SCORE3D)"
3577 "abs\t%0, %1"
3578 [(set_attr "type" "arith")
3579 (set_attr "mode" "SI")])
3581 (define_insn "sffs"
3582 [(set (match_operand:SI 0 "register_operand" "=d")
3583 (unspec:SI [(match_operand:SI 1 "register_operand" "d")] SFFS))]
3584 "(TARGET_SCORE7D || TARGET_SCORE3D)"
3585 "bitrev\t%0, %1, r0\;clz\t%0, %0\;addi\t%0, 0x1"
3586 [(set_attr "type" "arith")
3587 (set_attr "mode" "SI")])
3589 (define_expand "ffssi2"
3590 [(set (match_operand:SI 0 "register_operand")
3591 (ffs:SI (match_operand:SI 1 "register_operand")))]
3592 "(TARGET_SCORE7D || TARGET_SCORE3D)"
3593 {
3594 emit_insn (gen_sffs (operands[0], operands[1]));
3595 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (CC_NZmode, CC_REGNUM),
3596 gen_rtx_COMPARE (CC_NZmode, operands[0],
3597 GEN_INT (33))));
3598 if (TARGET_SCORE7D)
3599 emit_insn (gen_movsicc_internal_score7 (operands[0],
3600 gen_rtx_fmt_ee (EQ, VOIDmode, operands[0], GEN_INT (33)),
3601 GEN_INT (0),
3602 operands[0]));
3603 else
3604 emit_insn (gen_movsicc_internal_score3 (operands[0],
3605 gen_rtx_fmt_ee (EQ, VOIDmode, operands[0], GEN_INT (33)),
3606 GEN_INT (0),
3607 operands[0]));
3608 DONE;
3609 })
3611 (define_peephole2
3612 [(set (match_operand:SI 0 "loreg_operand" "")
3613 (match_operand:SI 1 "register_operand" ""))
3614 (set (match_operand:SI 2 "hireg_operand" "")
3615 (match_operand:SI 3 "register_operand" ""))]
3616 "(TARGET_SCORE7D || TARGET_SCORE3D)"
3617 [(parallel
3618 [(set (match_dup 0) (match_dup 1))
3619 (set (match_dup 2) (match_dup 3))])])
3621 (define_peephole2
3622 [(set (match_operand:SI 0 "hireg_operand" "")
3623 (match_operand:SI 1 "register_operand" ""))
3624 (set (match_operand:SI 2 "loreg_operand" "")
3625 (match_operand:SI 3 "register_operand" ""))]
3626 "(TARGET_SCORE7D || TARGET_SCORE3D)"
3627 [(parallel
3628 [(set (match_dup 2) (match_dup 3))
3629 (set (match_dup 0) (match_dup 1))])])
3631 (define_insn "movtohilo"
3632 [(parallel
3633 [(set (match_operand:SI 0 "loreg_operand" "=l")
3634 (match_operand:SI 1 "register_operand" "d"))
3635 (set (match_operand:SI 2 "hireg_operand" "=h")
3636 (match_operand:SI 3 "register_operand" "d"))])]
3637 "(TARGET_SCORE7D || TARGET_SCORE3D)"
3638 "mtcehl\t%3, %1"
3639 [(set_attr "type" "fce")
3640 (set_attr "mode" "SI")])
3642 (define_insn "mulsi3addsi"
3643 [(set (match_operand:SI 0 "register_operand" "=l,l,d")
3644 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
3645 (match_operand:SI 3 "register_operand" "d,d,d"))
3646 (match_operand:SI 1 "register_operand" "0,d,l")))
3647 (clobber (reg:SI HI_REGNUM))]
3648 "(TARGET_SCORE7D || TARGET_SCORE3D)"
3649 "@
3650 mad\t%2, %3
3651 mtcel%S1\t%1\;mad\t%2, %3
3652 mad\t%2, %3\;mfcel%S0\t%0"
3653 [(set_attr "mode" "SI")])
3655 (define_insn "mulsi3subsi"
3656 [(set (match_operand:SI 0 "register_operand" "=l,l,d")
3657 (minus:SI (match_operand:SI 1 "register_operand" "0,d,l")
3658 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
3659 (match_operand:SI 3 "register_operand" "d,d,d"))))
3660 (clobber (reg:SI HI_REGNUM))]
3661 "(TARGET_SCORE7D || TARGET_SCORE3D)"
3662 "@
3663 msb\t%2, %3
3664 mtcel%S1\t%1\;msb\t%2, %3
3665 msb\t%2, %3\;mfcel%S0\t%0"
3666 [(set_attr "mode" "SI")])
3668 (define_insn "mulsidi3adddi"
3669 [(set (match_operand:DI 0 "register_operand" "=x")
3670 (plus:DI (mult:DI
3671 (sign_extend:DI (match_operand:SI 2 "register_operand" "%d"))
3672 (sign_extend:DI (match_operand:SI 3 "register_operand" "d")))
3673 (match_operand:DI 1 "register_operand" "0")))]
3674 "(TARGET_SCORE7D || TARGET_SCORE3D)"
3675 "mad\t%2, %3"
3676 [(set_attr "mode" "DI")])
3678 (define_insn "umulsidi3adddi"
3679 [(set (match_operand:DI 0 "register_operand" "=x")
3680 (plus:DI (mult:DI
3681 (zero_extend:DI (match_operand:SI 2 "register_operand" "%d"))
3682 (zero_extend:DI (match_operand:SI 3 "register_operand" "d")))
3683 (match_operand:DI 1 "register_operand" "0")))]
3684 "(TARGET_SCORE7D || TARGET_SCORE3D)"
3685 "madu\t%2, %3"
3686 [(set_attr "mode" "DI")])
3688 (define_insn "mulsidi3subdi"
3689 [(set (match_operand:DI 0 "register_operand" "=x")
3690 (minus:DI
3691 (match_operand:DI 1 "register_operand" "0")
3692 (mult:DI
3693 (sign_extend:DI (match_operand:SI 2 "register_operand" "%d"))
3694 (sign_extend:DI (match_operand:SI 3 "register_operand" "d")))))]
3695 "(TARGET_SCORE7D || TARGET_SCORE3D)"
3696 "msb\t%2, %3"
3697 [(set_attr "mode" "DI")])
3699 (define_insn "umulsidi3subdi"
3700 [(set (match_operand:DI 0 "register_operand" "=x")
3701 (minus:DI
3702 (match_operand:DI 1 "register_operand" "0")
3703 (mult:DI (zero_extend:DI
3704 (match_operand:SI 2 "register_operand" "%d"))
3705 (zero_extend:DI
3706 (match_operand:SI 3 "register_operand" "d")))))]
3707 "(TARGET_SCORE7D || TARGET_SCORE3D)"
3708 "msbu\t%2, %3"
3709 [(set_attr "mode" "DI")])