1 /* Output routines for GCC for ARM.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
4 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
5 and Martin Simmons (@harleqn.co.uk).
6 More major hacks by Richard Earnshaw (rearnsha@arm.com).
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
31 #include "hard-reg-set.h"
33 #include "insn-config.h"
34 #include "conditions.h"
36 #include "insn-attr.h"
47 #include "integrate.h"
50 #include "target-def.h"
52 /* Forward definitions of types. */
53 typedef struct minipool_node Mnode
;
54 typedef struct minipool_fixup Mfix
;
56 /* In order to improve the layout of the prototypes below
57 some short type abbreviations are defined here. */
58 #define Hint HOST_WIDE_INT
59 #define Mmode enum machine_mode
60 #define Ulong unsigned long
61 #define Ccstar const char *
63 const struct attribute_spec arm_attribute_table
[];
65 /* Forward function declarations. */
66 static void arm_add_gc_roots
PARAMS ((void));
67 static int arm_gen_constant
PARAMS ((enum rtx_code
, Mmode
, Hint
, rtx
, rtx
, int, int));
68 static Ulong bit_count
PARAMS ((signed int));
69 static int const_ok_for_op
PARAMS ((Hint
, enum rtx_code
));
70 static int eliminate_lr2ip
PARAMS ((rtx
*));
71 static rtx emit_multi_reg_push
PARAMS ((int));
72 static rtx emit_sfm
PARAMS ((int, int));
74 static bool arm_assemble_integer
PARAMS ((rtx
, unsigned int, int));
76 static Ccstar fp_const_from_val
PARAMS ((REAL_VALUE_TYPE
*));
77 static arm_cc get_arm_condition_code
PARAMS ((rtx
));
78 static void init_fpa_table
PARAMS ((void));
79 static Hint int_log2
PARAMS ((Hint
));
80 static rtx is_jump_table
PARAMS ((rtx
));
81 static Ccstar output_multi_immediate
PARAMS ((rtx
*, Ccstar
, Ccstar
, int, Hint
));
82 static void print_multi_reg
PARAMS ((FILE *, Ccstar
, int, int));
83 static Mmode select_dominance_cc_mode
PARAMS ((rtx
, rtx
, Hint
));
84 static Ccstar shift_op
PARAMS ((rtx
, Hint
*));
85 static struct machine_function
* arm_init_machine_status
PARAMS ((void));
86 static int number_of_first_bit_set
PARAMS ((int));
87 static void replace_symbols_in_block
PARAMS ((tree
, rtx
, rtx
));
88 static void thumb_exit
PARAMS ((FILE *, int, rtx
));
89 static void thumb_pushpop
PARAMS ((FILE *, int, int));
90 static Ccstar thumb_condition_code
PARAMS ((rtx
, int));
91 static rtx is_jump_table
PARAMS ((rtx
));
92 static Hint get_jump_table_size
PARAMS ((rtx
));
93 static Mnode
* move_minipool_fix_forward_ref
PARAMS ((Mnode
*, Mnode
*, Hint
));
94 static Mnode
* add_minipool_forward_ref
PARAMS ((Mfix
*));
95 static Mnode
* move_minipool_fix_backward_ref
PARAMS ((Mnode
*, Mnode
*, Hint
));
96 static Mnode
* add_minipool_backward_ref
PARAMS ((Mfix
*));
97 static void assign_minipool_offsets
PARAMS ((Mfix
*));
98 static void arm_print_value
PARAMS ((FILE *, rtx
));
99 static void dump_minipool
PARAMS ((rtx
));
100 static int arm_barrier_cost
PARAMS ((rtx
));
101 static Mfix
* create_fix_barrier
PARAMS ((Mfix
*, Hint
));
102 static void push_minipool_barrier
PARAMS ((rtx
, Hint
));
103 static void push_minipool_fix
PARAMS ((rtx
, Hint
, rtx
*, Mmode
, rtx
));
104 static void note_invalid_constants
PARAMS ((rtx
, Hint
));
105 static int current_file_function_operand
PARAMS ((rtx
));
106 static Ulong arm_compute_save_reg0_reg12_mask
PARAMS ((void));
107 static Ulong arm_compute_save_reg_mask
PARAMS ((void));
108 static Ulong arm_isr_value
PARAMS ((tree
));
109 static Ulong arm_compute_func_type
PARAMS ((void));
110 static tree arm_handle_fndecl_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
111 static tree arm_handle_isr_attribute
PARAMS ((tree
*, tree
, tree
, int, bool *));
112 static void arm_output_function_epilogue
PARAMS ((FILE *, Hint
));
113 static void arm_output_function_prologue
PARAMS ((FILE *, Hint
));
114 static void thumb_output_function_prologue
PARAMS ((FILE *, Hint
));
115 static int arm_comp_type_attributes
PARAMS ((tree
, tree
));
116 static void arm_set_default_type_attributes
PARAMS ((tree
));
117 static int arm_adjust_cost
PARAMS ((rtx
, rtx
, rtx
, int));
118 static int count_insns_for_constant
PARAMS ((HOST_WIDE_INT
, int));
119 static int arm_get_strip_length
PARAMS ((int));
120 #ifdef OBJECT_FORMAT_ELF
121 static void arm_elf_asm_named_section
PARAMS ((const char *, unsigned int));
124 static void arm_encode_section_info
PARAMS ((tree
, int));
127 static void aof_globalize_label
PARAMS ((FILE *, const char *));
129 static void arm_output_mi_thunk
PARAMS ((FILE *, tree
,
131 HOST_WIDE_INT
, tree
));
138 /* Initialize the GCC target structure. */
139 #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES
140 #undef TARGET_MERGE_DECL_ATTRIBUTES
141 #define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
144 #undef TARGET_ATTRIBUTE_TABLE
145 #define TARGET_ATTRIBUTE_TABLE arm_attribute_table
148 #undef TARGET_ASM_BYTE_OP
149 #define TARGET_ASM_BYTE_OP "\tDCB\t"
150 #undef TARGET_ASM_ALIGNED_HI_OP
151 #define TARGET_ASM_ALIGNED_HI_OP "\tDCW\t"
152 #undef TARGET_ASM_ALIGNED_SI_OP
153 #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t"
154 #undef TARGET_ASM_GLOBALIZE_LABEL
155 #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label
157 #undef TARGET_ASM_ALIGNED_SI_OP
158 #define TARGET_ASM_ALIGNED_SI_OP NULL
159 #undef TARGET_ASM_INTEGER
160 #define TARGET_ASM_INTEGER arm_assemble_integer
163 #undef TARGET_ASM_FUNCTION_PROLOGUE
164 #define TARGET_ASM_FUNCTION_PROLOGUE arm_output_function_prologue
166 #undef TARGET_ASM_FUNCTION_EPILOGUE
167 #define TARGET_ASM_FUNCTION_EPILOGUE arm_output_function_epilogue
169 #undef TARGET_COMP_TYPE_ATTRIBUTES
170 #define TARGET_COMP_TYPE_ATTRIBUTES arm_comp_type_attributes
172 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
173 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes
175 #undef TARGET_INIT_BUILTINS
176 #define TARGET_INIT_BUILTINS arm_init_builtins
178 #undef TARGET_EXPAND_BUILTIN
179 #define TARGET_EXPAND_BUILTIN arm_expand_builtin
181 #undef TARGET_SCHED_ADJUST_COST
182 #define TARGET_SCHED_ADJUST_COST arm_adjust_cost
184 #undef TARGET_ENCODE_SECTION_INFO
186 #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info
188 #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info
191 #undef TARGET_STRIP_NAME_ENCODING
192 #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding
194 #undef TARGET_ASM_OUTPUT_MI_THUNK
195 #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk
196 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
197 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
199 struct gcc_target targetm
= TARGET_INITIALIZER
;
201 /* Obstack for minipool constant handling. */
202 static struct obstack minipool_obstack
;
203 static char * minipool_startobj
;
205 /* The maximum number of insns skipped which
206 will be conditionalised if possible. */
207 static int max_insns_skipped
= 5;
209 extern FILE * asm_out_file
;
211 /* True if we are currently building a constant table. */
212 int making_const_table
;
214 /* Define the information needed to generate branch insns. This is
215 stored from the compare operation. */
216 rtx arm_compare_op0
, arm_compare_op1
;
218 /* What type of floating point are we tuning for? */
219 enum floating_point_type arm_fpu
;
221 /* What type of floating point instructions are available? */
222 enum floating_point_type arm_fpu_arch
;
224 /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */
225 enum prog_mode_type arm_prgmode
;
227 /* Set by the -mfp=... option. */
228 const char * target_fp_name
= NULL
;
230 /* Used to parse -mstructure_size_boundary command line option. */
231 const char * structure_size_string
= NULL
;
232 int arm_structure_size_boundary
= DEFAULT_STRUCTURE_SIZE_BOUNDARY
;
234 /* Bit values used to identify processor capabilities. */
235 #define FL_CO_PROC (1 << 0) /* Has external co-processor bus */
236 #define FL_FAST_MULT (1 << 1) /* Fast multiply */
237 #define FL_MODE26 (1 << 2) /* 26-bit mode support */
238 #define FL_MODE32 (1 << 3) /* 32-bit mode support */
239 #define FL_ARCH4 (1 << 4) /* Architecture rel 4 */
240 #define FL_ARCH5 (1 << 5) /* Architecture rel 5 */
241 #define FL_THUMB (1 << 6) /* Thumb aware */
242 #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */
243 #define FL_STRONG (1 << 8) /* StrongARM */
244 #define FL_ARCH5E (1 << 9) /* DSP extenstions to v5 */
245 #define FL_XSCALE (1 << 10) /* XScale */
247 /* The bits in this mask specify which
248 instructions we are allowed to generate. */
249 static int insn_flags
= 0;
251 /* The bits in this mask specify which instruction scheduling options should
252 be used. Note - there is an overlap with the FL_FAST_MULT. For some
253 hardware we want to be able to generate the multiply instructions, but to
254 tune as if they were not present in the architecture. */
255 static int tune_flags
= 0;
257 /* The following are used in the arm.md file as equivalents to bits
258 in the above two flag variables. */
260 /* Nonzero if this is an "M" variant of the processor. */
261 int arm_fast_multiply
= 0;
263 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */
266 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */
269 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */
272 /* Nonzero if this chip can benefit from load scheduling. */
273 int arm_ld_sched
= 0;
275 /* Nonzero if this chip is a StrongARM. */
276 int arm_is_strong
= 0;
278 /* Nonzero if this chip is an XScale. */
279 int arm_is_xscale
= 0;
281 /* Nonzero if this chip is an ARM6 or an ARM7. */
282 int arm_is_6_or_7
= 0;
284 /* Nonzero if generating Thumb instructions. */
287 /* In case of a PRE_INC, POST_INC, PRE_DEC, POST_DEC memory reference, we
288 must report the mode of the memory reference from PRINT_OPERAND to
289 PRINT_OPERAND_ADDRESS. */
290 enum machine_mode output_memory_reference_mode
;
292 /* The register number to be used for the PIC offset register. */
293 const char * arm_pic_register_string
= NULL
;
294 int arm_pic_register
= INVALID_REGNUM
;
296 /* Set to 1 when a return insn is output, this means that the epilogue
298 int return_used_this_function
;
300 /* Set to 1 after arm_reorg has started. Reset to start at the start of
301 the next function. */
302 static int after_arm_reorg
= 0;
304 /* The maximum number of insns to be used when loading a constant. */
305 static int arm_constant_limit
= 3;
307 /* For an explanation of these variables, see final_prescan_insn below. */
309 enum arm_cond_code arm_current_cc
;
311 int arm_target_label
;
313 /* The condition codes of the ARM, and the inverse function. */
314 static const char * const arm_condition_codes
[] =
316 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
317 "hi", "ls", "ge", "lt", "gt", "le", "al", "nv"
320 #define streq(string1, string2) (strcmp (string1, string2) == 0)
322 /* Initialization code. */
326 const char *const name
;
327 const unsigned int flags
;
330 /* Not all of these give usefully different compilation alternatives,
331 but there is no simple way of generalizing them. */
332 static const struct processors all_cores
[] =
336 {"arm2", FL_CO_PROC
| FL_MODE26
},
337 {"arm250", FL_CO_PROC
| FL_MODE26
},
338 {"arm3", FL_CO_PROC
| FL_MODE26
},
339 {"arm6", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
340 {"arm60", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
341 {"arm600", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
342 {"arm610", FL_MODE26
| FL_MODE32
},
343 {"arm620", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
344 {"arm7", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
345 /* arm7m doesn't exist on its own, but only with D, (and I), but
346 those don't alter the code, so arm7m is sometimes used. */
347 {"arm7m", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
348 {"arm7d", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
349 {"arm7dm", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
350 {"arm7di", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
351 {"arm7dmi", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
352 {"arm70", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
353 {"arm700", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
354 {"arm700i", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
355 {"arm710", FL_MODE26
| FL_MODE32
},
356 {"arm710t", FL_MODE26
| FL_MODE32
| FL_THUMB
},
357 {"arm720", FL_MODE26
| FL_MODE32
},
358 {"arm720t", FL_MODE26
| FL_MODE32
| FL_THUMB
},
359 {"arm740t", FL_MODE26
| FL_MODE32
| FL_THUMB
},
360 {"arm710c", FL_MODE26
| FL_MODE32
},
361 {"arm7100", FL_MODE26
| FL_MODE32
},
362 {"arm7500", FL_MODE26
| FL_MODE32
},
363 /* Doesn't have an external co-proc, but does have embedded fpu. */
364 {"arm7500fe", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
365 {"arm7tdmi", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
366 {"arm8", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
367 {"arm810", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
368 {"arm9", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
369 {"arm920", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
370 {"arm920t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
371 {"arm940t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
372 {"arm9tdmi", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
},
373 {"arm9e", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
},
374 {"strongarm", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
375 {"strongarm110", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
376 {"strongarm1100", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
377 {"strongarm1110", FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_LDSCHED
| FL_STRONG
},
378 {"arm10tdmi", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_ARCH5
},
379 {"arm1020t", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_ARCH5
},
380 {"xscale", FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_LDSCHED
| FL_STRONG
| FL_ARCH5
| FL_ARCH5E
| FL_XSCALE
},
385 static const struct processors all_architectures
[] =
387 /* ARM Architectures */
389 { "armv2", FL_CO_PROC
| FL_MODE26
},
390 { "armv2a", FL_CO_PROC
| FL_MODE26
},
391 { "armv3", FL_CO_PROC
| FL_MODE26
| FL_MODE32
},
392 { "armv3m", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
},
393 { "armv4", FL_CO_PROC
| FL_MODE26
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
},
394 /* Strictly, FL_MODE26 is a permitted option for v4t, but there are no
395 implementations that support it, so we will leave it out for now. */
396 { "armv4t", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
},
397 { "armv5", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
},
398 { "armv5t", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
},
399 { "armv5te", FL_CO_PROC
| FL_MODE32
| FL_FAST_MULT
| FL_ARCH4
| FL_THUMB
| FL_ARCH5
| FL_ARCH5E
},
403 /* This is a magic stucture. The 'string' field is magically filled in
404 with a pointer to the value specified by the user on the command line
405 assuming that the user has specified such a value. */
407 struct arm_cpu_select arm_select
[] =
409 /* string name processors */
410 { NULL
, "-mcpu=", all_cores
},
411 { NULL
, "-march=", all_architectures
},
412 { NULL
, "-mtune=", all_cores
}
415 /* Return the number of bits set in value' */
420 unsigned long count
= 0;
424 value
&= ~(value
& -value
);
431 /* Fix up any incompatible options that the user has specified.
432 This has now turned into a maze. */
434 arm_override_options ()
438 /* Set up the flags based on the cpu/architecture selected by the user. */
439 for (i
= ARRAY_SIZE (arm_select
); i
--;)
441 struct arm_cpu_select
* ptr
= arm_select
+ i
;
443 if (ptr
->string
!= NULL
&& ptr
->string
[0] != '\0')
445 const struct processors
* sel
;
447 for (sel
= ptr
->processors
; sel
->name
!= NULL
; sel
++)
448 if (streq (ptr
->string
, sel
->name
))
451 tune_flags
= sel
->flags
;
454 /* If we have been given an architecture and a processor
455 make sure that they are compatible. We only generate
456 a warning though, and we prefer the CPU over the
458 if (insn_flags
!= 0 && (insn_flags
^ sel
->flags
))
459 warning ("switch -mcpu=%s conflicts with -march= switch",
462 insn_flags
= sel
->flags
;
468 if (sel
->name
== NULL
)
469 error ("bad value (%s) for %s switch", ptr
->string
, ptr
->name
);
473 /* If the user did not specify a processor, choose one for them. */
476 const struct processors
* sel
;
478 static const struct cpu_default
481 const char *const name
;
485 { TARGET_CPU_arm2
, "arm2" },
486 { TARGET_CPU_arm6
, "arm6" },
487 { TARGET_CPU_arm610
, "arm610" },
488 { TARGET_CPU_arm710
, "arm710" },
489 { TARGET_CPU_arm7m
, "arm7m" },
490 { TARGET_CPU_arm7500fe
, "arm7500fe" },
491 { TARGET_CPU_arm7tdmi
, "arm7tdmi" },
492 { TARGET_CPU_arm8
, "arm8" },
493 { TARGET_CPU_arm810
, "arm810" },
494 { TARGET_CPU_arm9
, "arm9" },
495 { TARGET_CPU_strongarm
, "strongarm" },
496 { TARGET_CPU_xscale
, "xscale" },
497 { TARGET_CPU_generic
, "arm" },
500 const struct cpu_default
* def
;
502 /* Find the default. */
503 for (def
= cpu_defaults
; def
->name
; def
++)
504 if (def
->cpu
== TARGET_CPU_DEFAULT
)
507 /* Make sure we found the default CPU. */
508 if (def
->name
== NULL
)
511 /* Find the default CPU's flags. */
512 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
513 if (streq (def
->name
, sel
->name
))
516 if (sel
->name
== NULL
)
519 insn_flags
= sel
->flags
;
521 /* Now check to see if the user has specified some command line
522 switch that require certain abilities from the cpu. */
525 if (TARGET_INTERWORK
|| TARGET_THUMB
)
527 sought
|= (FL_THUMB
| FL_MODE32
);
529 /* Force apcs-32 to be used for interworking. */
530 target_flags
|= ARM_FLAG_APCS_32
;
532 /* There are no ARM processors that support both APCS-26 and
533 interworking. Therefore we force FL_MODE26 to be removed
534 from insn_flags here (if it was set), so that the search
535 below will always be able to find a compatible processor. */
536 insn_flags
&= ~FL_MODE26
;
538 else if (!TARGET_APCS_32
)
541 if (sought
!= 0 && ((sought
& insn_flags
) != sought
))
543 /* Try to locate a CPU type that supports all of the abilities
544 of the default CPU, plus the extra abilities requested by
546 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
547 if ((sel
->flags
& sought
) == (sought
| insn_flags
))
550 if (sel
->name
== NULL
)
552 unsigned int current_bit_count
= 0;
553 const struct processors
* best_fit
= NULL
;
555 /* Ideally we would like to issue an error message here
556 saying that it was not possible to find a CPU compatible
557 with the default CPU, but which also supports the command
558 line options specified by the programmer, and so they
559 ought to use the -mcpu=<name> command line option to
560 override the default CPU type.
562 Unfortunately this does not work with multilibing. We
563 need to be able to support multilibs for -mapcs-26 and for
564 -mthumb-interwork and there is no CPU that can support both
565 options. Instead if we cannot find a cpu that has both the
566 characteristics of the default cpu and the given command line
567 options we scan the array again looking for a best match. */
568 for (sel
= all_cores
; sel
->name
!= NULL
; sel
++)
569 if ((sel
->flags
& sought
) == sought
)
573 count
= bit_count (sel
->flags
& insn_flags
);
575 if (count
>= current_bit_count
)
578 current_bit_count
= count
;
582 if (best_fit
== NULL
)
588 insn_flags
= sel
->flags
;
592 /* If tuning has not been specified, tune for whichever processor or
593 architecture has been selected. */
595 tune_flags
= insn_flags
;
597 /* Make sure that the processor choice does not conflict with any of the
598 other command line choices. */
599 if (TARGET_APCS_32
&& !(insn_flags
& FL_MODE32
))
601 /* If APCS-32 was not the default then it must have been set by the
602 user, so issue a warning message. If the user has specified
603 "-mapcs-32 -mcpu=arm2" then we loose here. */
604 if ((TARGET_DEFAULT
& ARM_FLAG_APCS_32
) == 0)
605 warning ("target CPU does not support APCS-32" );
606 target_flags
&= ~ARM_FLAG_APCS_32
;
608 else if (!TARGET_APCS_32
&& !(insn_flags
& FL_MODE26
))
610 warning ("target CPU does not support APCS-26" );
611 target_flags
|= ARM_FLAG_APCS_32
;
614 if (TARGET_INTERWORK
&& !(insn_flags
& FL_THUMB
))
616 warning ("target CPU does not support interworking" );
617 target_flags
&= ~ARM_FLAG_INTERWORK
;
620 if (TARGET_THUMB
&& !(insn_flags
& FL_THUMB
))
622 warning ("target CPU does not support THUMB instructions");
623 target_flags
&= ~ARM_FLAG_THUMB
;
626 if (TARGET_APCS_FRAME
&& TARGET_THUMB
)
628 /* warning ("ignoring -mapcs-frame because -mthumb was used"); */
629 target_flags
&= ~ARM_FLAG_APCS_FRAME
;
632 /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done
633 from here where no function is being compiled currently. */
634 if ((target_flags
& (THUMB_FLAG_LEAF_BACKTRACE
| THUMB_FLAG_BACKTRACE
))
636 warning ("enabling backtrace support is only meaningful when compiling for the Thumb");
638 if (TARGET_ARM
&& TARGET_CALLEE_INTERWORKING
)
639 warning ("enabling callee interworking support is only meaningful when compiling for the Thumb");
641 if (TARGET_ARM
&& TARGET_CALLER_INTERWORKING
)
642 warning ("enabling caller interworking support is only meaningful when compiling for the Thumb");
644 /* If interworking is enabled then APCS-32 must be selected as well. */
645 if (TARGET_INTERWORK
)
648 warning ("interworking forces APCS-32 to be used" );
649 target_flags
|= ARM_FLAG_APCS_32
;
652 if (TARGET_APCS_STACK
&& !TARGET_APCS_FRAME
)
654 warning ("-mapcs-stack-check incompatible with -mno-apcs-frame");
655 target_flags
|= ARM_FLAG_APCS_FRAME
;
658 if (TARGET_POKE_FUNCTION_NAME
)
659 target_flags
|= ARM_FLAG_APCS_FRAME
;
661 if (TARGET_APCS_REENT
&& flag_pic
)
662 error ("-fpic and -mapcs-reent are incompatible");
664 if (TARGET_APCS_REENT
)
665 warning ("APCS reentrant code not supported. Ignored");
667 /* If this target is normally configured to use APCS frames, warn if they
668 are turned off and debugging is turned on. */
670 && write_symbols
!= NO_DEBUG
671 && !TARGET_APCS_FRAME
672 && (TARGET_DEFAULT
& ARM_FLAG_APCS_FRAME
))
673 warning ("-g with -mno-apcs-frame may not give sensible debugging");
675 /* If stack checking is disabled, we can use r10 as the PIC register,
676 which keeps r9 available. */
678 arm_pic_register
= TARGET_APCS_STACK
? 9 : 10;
680 if (TARGET_APCS_FLOAT
)
681 warning ("passing floating point arguments in fp regs not yet supported");
683 /* Initialize boolean versions of the flags, for use in the arm.md file. */
684 arm_fast_multiply
= (insn_flags
& FL_FAST_MULT
) != 0;
685 arm_arch4
= (insn_flags
& FL_ARCH4
) != 0;
686 arm_arch5
= (insn_flags
& FL_ARCH5
) != 0;
687 arm_arch5e
= (insn_flags
& FL_ARCH5E
) != 0;
688 arm_is_xscale
= (insn_flags
& FL_XSCALE
) != 0;
690 arm_ld_sched
= (tune_flags
& FL_LDSCHED
) != 0;
691 arm_is_strong
= (tune_flags
& FL_STRONG
) != 0;
692 thumb_code
= (TARGET_ARM
== 0);
693 arm_is_6_or_7
= (((tune_flags
& (FL_MODE26
| FL_MODE32
))
694 && !(tune_flags
& FL_ARCH4
))) != 0;
696 /* Default value for floating point code... if no co-processor
697 bus, then schedule for emulated floating point. Otherwise,
698 assume the user has an FPA.
699 Note: this does not prevent use of floating point instructions,
700 -msoft-float does that. */
701 arm_fpu
= (tune_flags
& FL_CO_PROC
) ? FP_HARD
: FP_SOFT3
;
705 if (streq (target_fp_name
, "2"))
706 arm_fpu_arch
= FP_SOFT2
;
707 else if (streq (target_fp_name
, "3"))
708 arm_fpu_arch
= FP_SOFT3
;
710 error ("invalid floating point emulation option: -mfpe-%s",
714 arm_fpu_arch
= FP_DEFAULT
;
716 if (TARGET_FPE
&& arm_fpu
!= FP_HARD
)
719 /* For arm2/3 there is no need to do any scheduling if there is only
720 a floating point emulator, or we are doing software floating-point. */
721 if ((TARGET_SOFT_FLOAT
|| arm_fpu
!= FP_HARD
)
722 && (tune_flags
& FL_MODE32
) == 0)
723 flag_schedule_insns
= flag_schedule_insns_after_reload
= 0;
725 arm_prgmode
= TARGET_APCS_32
? PROG_MODE_PROG32
: PROG_MODE_PROG26
;
727 if (structure_size_string
!= NULL
)
729 int size
= strtol (structure_size_string
, NULL
, 0);
731 if (size
== 8 || size
== 32)
732 arm_structure_size_boundary
= size
;
734 warning ("structure size boundary can only be set to 8 or 32");
737 if (arm_pic_register_string
!= NULL
)
739 int pic_register
= decode_reg_name (arm_pic_register_string
);
742 warning ("-mpic-register= is useless without -fpic");
744 /* Prevent the user from choosing an obviously stupid PIC register. */
745 else if (pic_register
< 0 || call_used_regs
[pic_register
]
746 || pic_register
== HARD_FRAME_POINTER_REGNUM
747 || pic_register
== STACK_POINTER_REGNUM
748 || pic_register
>= PC_REGNUM
)
749 error ("unable to use '%s' for PIC register", arm_pic_register_string
);
751 arm_pic_register
= pic_register
;
754 if (TARGET_THUMB
&& flag_schedule_insns
)
756 /* Don't warn since it's on by default in -O2. */
757 flag_schedule_insns
= 0;
760 /* If optimizing for space, don't synthesize constants.
761 For processors with load scheduling, it never costs more than 2 cycles
762 to load a constant, and the load scheduler may well reduce that to 1. */
763 if (optimize_size
|| (tune_flags
& FL_LDSCHED
))
764 arm_constant_limit
= 1;
767 arm_constant_limit
= 2;
769 /* If optimizing for size, bump the number of instructions that we
770 are prepared to conditionally execute (even on a StrongARM).
771 Otherwise for the StrongARM, which has early execution of branches,
772 a sequence that is worth skipping is shorter. */
774 max_insns_skipped
= 6;
775 else if (arm_is_strong
)
776 max_insns_skipped
= 3;
778 /* Register global variables with the garbage collector. */
785 gcc_obstack_init(&minipool_obstack
);
786 minipool_startobj
= (char *) obstack_alloc (&minipool_obstack
, 0);
789 /* A table of known ARM exception types.
790 For use with the interrupt function attribute. */
794 const char *const arg
;
795 const unsigned long return_value
;
799 static const isr_attribute_arg isr_attribute_args
[] =
801 { "IRQ", ARM_FT_ISR
},
802 { "irq", ARM_FT_ISR
},
803 { "FIQ", ARM_FT_FIQ
},
804 { "fiq", ARM_FT_FIQ
},
805 { "ABORT", ARM_FT_ISR
},
806 { "abort", ARM_FT_ISR
},
807 { "ABORT", ARM_FT_ISR
},
808 { "abort", ARM_FT_ISR
},
809 { "UNDEF", ARM_FT_EXCEPTION
},
810 { "undef", ARM_FT_EXCEPTION
},
811 { "SWI", ARM_FT_EXCEPTION
},
812 { "swi", ARM_FT_EXCEPTION
},
813 { NULL
, ARM_FT_NORMAL
}
816 /* Returns the (interrupt) function type of the current
817 function, or ARM_FT_UNKNOWN if the type cannot be determined. */
820 arm_isr_value (argument
)
823 const isr_attribute_arg
* ptr
;
826 /* No argument - default to IRQ. */
827 if (argument
== NULL_TREE
)
830 /* Get the value of the argument. */
831 if (TREE_VALUE (argument
) == NULL_TREE
832 || TREE_CODE (TREE_VALUE (argument
)) != STRING_CST
)
833 return ARM_FT_UNKNOWN
;
835 arg
= TREE_STRING_POINTER (TREE_VALUE (argument
));
837 /* Check it against the list of known arguments. */
838 for (ptr
= isr_attribute_args
; ptr
->arg
!= NULL
; ptr
++)
839 if (streq (arg
, ptr
->arg
))
840 return ptr
->return_value
;
842 /* An unrecognized interrupt type. */
843 return ARM_FT_UNKNOWN
;
846 /* Computes the type of the current function. */
849 arm_compute_func_type ()
851 unsigned long type
= ARM_FT_UNKNOWN
;
855 if (TREE_CODE (current_function_decl
) != FUNCTION_DECL
)
858 /* Decide if the current function is volatile. Such functions
859 never return, and many memory cycles can be saved by not storing
860 register values that will never be needed again. This optimization
861 was added to speed up context switching in a kernel application. */
863 && current_function_nothrow
864 && TREE_THIS_VOLATILE (current_function_decl
))
865 type
|= ARM_FT_VOLATILE
;
867 if (current_function_needs_context
)
868 type
|= ARM_FT_NESTED
;
870 attr
= DECL_ATTRIBUTES (current_function_decl
);
872 a
= lookup_attribute ("naked", attr
);
874 type
|= ARM_FT_NAKED
;
876 if (cfun
->machine
->eh_epilogue_sp_ofs
!= NULL_RTX
)
877 type
|= ARM_FT_EXCEPTION_HANDLER
;
880 a
= lookup_attribute ("isr", attr
);
882 a
= lookup_attribute ("interrupt", attr
);
885 type
|= TARGET_INTERWORK
? ARM_FT_INTERWORKED
: ARM_FT_NORMAL
;
887 type
|= arm_isr_value (TREE_VALUE (a
));
893 /* Returns the type of the current function. */
896 arm_current_func_type ()
898 if (ARM_FUNC_TYPE (cfun
->machine
->func_type
) == ARM_FT_UNKNOWN
)
899 cfun
->machine
->func_type
= arm_compute_func_type ();
901 return cfun
->machine
->func_type
;
904 /* Return 1 if it is possible to return using a single instruction. */
907 use_return_insn (iscond
)
911 unsigned int func_type
;
912 unsigned long saved_int_regs
;
914 /* Never use a return instruction before reload has run. */
915 if (!reload_completed
)
918 func_type
= arm_current_func_type ();
920 /* Naked functions and volatile functions need special
922 if (func_type
& (ARM_FT_VOLATILE
| ARM_FT_NAKED
))
925 /* As do variadic functions. */
926 if (current_function_pretend_args_size
927 || cfun
->machine
->uses_anonymous_args
928 /* Of if the function calls __builtin_eh_return () */
929 || ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
930 /* Or if there is no frame pointer and there is a stack adjustment. */
931 || ((get_frame_size () + current_function_outgoing_args_size
!= 0)
932 && !frame_pointer_needed
))
935 saved_int_regs
= arm_compute_save_reg_mask ();
937 /* Can't be done if interworking with Thumb, and any registers have been
939 if (TARGET_INTERWORK
&& saved_int_regs
!= 0)
942 /* On StrongARM, conditional returns are expensive if they aren't
943 taken and multiple registers have been stacked. */
944 if (iscond
&& arm_is_strong
)
946 /* Conditional return when just the LR is stored is a simple
947 conditional-load instruction, that's not expensive. */
948 if (saved_int_regs
!= 0 && saved_int_regs
!= (1 << LR_REGNUM
))
951 if (flag_pic
&& regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
955 /* If there are saved registers but the LR isn't saved, then we need
956 two instructions for the return. */
957 if (saved_int_regs
&& !(saved_int_regs
& (1 << LR_REGNUM
)))
960 /* Can't be done if any of the FPU regs are pushed,
961 since this also requires an insn. */
962 if (TARGET_HARD_FLOAT
)
963 for (regno
= FIRST_ARM_FP_REGNUM
; regno
<= LAST_ARM_FP_REGNUM
; regno
++)
964 if (regs_ever_live
[regno
] && !call_used_regs
[regno
])
970 /* Return TRUE if int I is a valid immediate ARM constant. */
976 unsigned HOST_WIDE_INT mask
= ~(unsigned HOST_WIDE_INT
)0xFF;
978 /* For machines with >32 bit HOST_WIDE_INT, the bits above bit 31 must
979 be all zero, or all one. */
980 if ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff) != 0
981 && ((i
& ~(unsigned HOST_WIDE_INT
) 0xffffffff)
982 != ((~(unsigned HOST_WIDE_INT
) 0)
983 & ~(unsigned HOST_WIDE_INT
) 0xffffffff)))
986 /* Fast return for 0 and powers of 2 */
987 if ((i
& (i
- 1)) == 0)
992 if ((i
& mask
& (unsigned HOST_WIDE_INT
) 0xffffffff) == 0)
995 (mask
<< 2) | ((mask
& (unsigned HOST_WIDE_INT
) 0xffffffff)
996 >> (32 - 2)) | ~(unsigned HOST_WIDE_INT
) 0xffffffff;
998 while (mask
!= ~(unsigned HOST_WIDE_INT
) 0xFF);
1003 /* Return true if I is a valid constant for the operation CODE. */
1005 const_ok_for_op (i
, code
)
1009 if (const_ok_for_arm (i
))
1015 return const_ok_for_arm (ARM_SIGN_EXTEND (-i
));
1017 case MINUS
: /* Should only occur with (MINUS I reg) => rsb */
1023 return const_ok_for_arm (ARM_SIGN_EXTEND (~i
));
1030 /* Emit a sequence of insns to handle a large constant.
1031 CODE is the code of the operation required, it can be any of SET, PLUS,
1032 IOR, AND, XOR, MINUS;
1033 MODE is the mode in which the operation is being performed;
1034 VAL is the integer to operate on;
1035 SOURCE is the other operand (a register, or a null-pointer for SET);
1036 SUBTARGETS means it is safe to create scratch registers if that will
1037 either produce a simpler sequence, or we will want to cse the values.
1038 Return value is the number of insns emitted. */
1041 arm_split_constant (code
, mode
, val
, target
, source
, subtargets
)
1043 enum machine_mode mode
;
1049 if (subtargets
|| code
== SET
1050 || (GET_CODE (target
) == REG
&& GET_CODE (source
) == REG
1051 && REGNO (target
) != REGNO (source
)))
1053 /* After arm_reorg has been called, we can't fix up expensive
1054 constants by pushing them into memory so we must synthesize
1055 them in-line, regardless of the cost. This is only likely to
1056 be more costly on chips that have load delay slots and we are
1057 compiling without running the scheduler (so no splitting
1058 occurred before the final instruction emission).
1060 Ref: gcc -O1 -mcpu=strongarm gcc.c-torture/compile/980506-2.c
1062 if (!after_arm_reorg
1063 && (arm_gen_constant (code
, mode
, val
, target
, source
, 1, 0)
1064 > arm_constant_limit
+ (code
!= SET
)))
1068 /* Currently SET is the only monadic value for CODE, all
1069 the rest are diadic. */
1070 emit_insn (gen_rtx_SET (VOIDmode
, target
, GEN_INT (val
)));
1075 rtx temp
= subtargets
? gen_reg_rtx (mode
) : target
;
1077 emit_insn (gen_rtx_SET (VOIDmode
, temp
, GEN_INT (val
)));
1078 /* For MINUS, the value is subtracted from, since we never
1079 have subtraction of a constant. */
1081 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1082 gen_rtx_MINUS (mode
, temp
, source
)));
1084 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1085 gen_rtx (code
, mode
, source
, temp
)));
1091 return arm_gen_constant (code
, mode
, val
, target
, source
, subtargets
, 1);
1095 count_insns_for_constant (remainder
, i
)
1096 HOST_WIDE_INT remainder
;
1099 HOST_WIDE_INT temp1
;
1107 if (remainder
& (3 << (i
- 2)))
1112 temp1
= remainder
& ((0x0ff << end
)
1113 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1114 remainder
&= ~temp1
;
1119 } while (remainder
);
1123 /* As above, but extra parameter GENERATE which, if clear, suppresses
1127 arm_gen_constant (code
, mode
, val
, target
, source
, subtargets
, generate
)
1129 enum machine_mode mode
;
1138 int can_negate_initial
= 0;
1141 int num_bits_set
= 0;
1142 int set_sign_bit_copies
= 0;
1143 int clear_sign_bit_copies
= 0;
1144 int clear_zero_bit_copies
= 0;
1145 int set_zero_bit_copies
= 0;
1147 unsigned HOST_WIDE_INT temp1
, temp2
;
1148 unsigned HOST_WIDE_INT remainder
= val
& 0xffffffff;
1150 /* Find out which operations are safe for a given CODE. Also do a quick
1151 check for degenerate cases; these can occur when DImode operations
1163 can_negate_initial
= 1;
1167 if (remainder
== 0xffffffff)
1170 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1171 GEN_INT (ARM_SIGN_EXTEND (val
))));
1176 if (reload_completed
&& rtx_equal_p (target
, source
))
1179 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
1188 emit_insn (gen_rtx_SET (VOIDmode
, target
, const0_rtx
));
1191 if (remainder
== 0xffffffff)
1193 if (reload_completed
&& rtx_equal_p (target
, source
))
1196 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
1205 if (reload_completed
&& rtx_equal_p (target
, source
))
1208 emit_insn (gen_rtx_SET (VOIDmode
, target
, source
));
1211 if (remainder
== 0xffffffff)
1214 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1215 gen_rtx_NOT (mode
, source
)));
1219 /* We don't know how to handle this yet below. */
1223 /* We treat MINUS as (val - source), since (source - val) is always
1224 passed as (source + (-val)). */
1228 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1229 gen_rtx_NEG (mode
, source
)));
1232 if (const_ok_for_arm (val
))
1235 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1236 gen_rtx_MINUS (mode
, GEN_INT (val
),
1248 /* If we can do it in one insn get out quickly. */
1249 if (const_ok_for_arm (val
)
1250 || (can_negate_initial
&& const_ok_for_arm (-val
))
1251 || (can_invert
&& const_ok_for_arm (~val
)))
1254 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1255 (source
? gen_rtx (code
, mode
, source
,
1261 /* Calculate a few attributes that may be useful for specific
1263 for (i
= 31; i
>= 0; i
--)
1265 if ((remainder
& (1 << i
)) == 0)
1266 clear_sign_bit_copies
++;
1271 for (i
= 31; i
>= 0; i
--)
1273 if ((remainder
& (1 << i
)) != 0)
1274 set_sign_bit_copies
++;
1279 for (i
= 0; i
<= 31; i
++)
1281 if ((remainder
& (1 << i
)) == 0)
1282 clear_zero_bit_copies
++;
1287 for (i
= 0; i
<= 31; i
++)
1289 if ((remainder
& (1 << i
)) != 0)
1290 set_zero_bit_copies
++;
1298 /* See if we can do this by sign_extending a constant that is known
1299 to be negative. This is a good, way of doing it, since the shift
1300 may well merge into a subsequent insn. */
1301 if (set_sign_bit_copies
> 1)
1303 if (const_ok_for_arm
1304 (temp1
= ARM_SIGN_EXTEND (remainder
1305 << (set_sign_bit_copies
- 1))))
1309 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1310 emit_insn (gen_rtx_SET (VOIDmode
, new_src
,
1312 emit_insn (gen_ashrsi3 (target
, new_src
,
1313 GEN_INT (set_sign_bit_copies
- 1)));
1317 /* For an inverted constant, we will need to set the low bits,
1318 these will be shifted out of harm's way. */
1319 temp1
|= (1 << (set_sign_bit_copies
- 1)) - 1;
1320 if (const_ok_for_arm (~temp1
))
1324 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1325 emit_insn (gen_rtx_SET (VOIDmode
, new_src
,
1327 emit_insn (gen_ashrsi3 (target
, new_src
,
1328 GEN_INT (set_sign_bit_copies
- 1)));
1334 /* See if we can generate this by setting the bottom (or the top)
1335 16 bits, and then shifting these into the other half of the
1336 word. We only look for the simplest cases, to do more would cost
1337 too much. Be careful, however, not to generate this when the
1338 alternative would take fewer insns. */
1339 if (val
& 0xffff0000)
1341 temp1
= remainder
& 0xffff0000;
1342 temp2
= remainder
& 0x0000ffff;
1344 /* Overlaps outside this range are best done using other methods. */
1345 for (i
= 9; i
< 24; i
++)
1347 if ((((temp2
| (temp2
<< i
)) & 0xffffffff) == remainder
)
1348 && !const_ok_for_arm (temp2
))
1350 rtx new_src
= (subtargets
1351 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1353 insns
= arm_gen_constant (code
, mode
, temp2
, new_src
,
1354 source
, subtargets
, generate
);
1357 emit_insn (gen_rtx_SET
1360 gen_rtx_ASHIFT (mode
, source
,
1367 /* Don't duplicate cases already considered. */
1368 for (i
= 17; i
< 24; i
++)
1370 if (((temp1
| (temp1
>> i
)) == remainder
)
1371 && !const_ok_for_arm (temp1
))
1373 rtx new_src
= (subtargets
1374 ? (generate
? gen_reg_rtx (mode
) : NULL_RTX
)
1376 insns
= arm_gen_constant (code
, mode
, temp1
, new_src
,
1377 source
, subtargets
, generate
);
1381 (gen_rtx_SET (VOIDmode
, target
,
1384 gen_rtx_LSHIFTRT (mode
, source
,
1395 /* If we have IOR or XOR, and the constant can be loaded in a
1396 single instruction, and we can find a temporary to put it in,
1397 then this can be done in two instructions instead of 3-4. */
1399 /* TARGET can't be NULL if SUBTARGETS is 0 */
1400 || (reload_completed
&& !reg_mentioned_p (target
, source
)))
1402 if (const_ok_for_arm (ARM_SIGN_EXTEND (~val
)))
1406 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1408 emit_insn (gen_rtx_SET (VOIDmode
, sub
, GEN_INT (val
)));
1409 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1410 gen_rtx (code
, mode
, source
, sub
)));
1419 if (set_sign_bit_copies
> 8
1420 && (val
& (-1 << (32 - set_sign_bit_copies
))) == val
)
1424 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1425 rtx shift
= GEN_INT (set_sign_bit_copies
);
1427 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1429 gen_rtx_ASHIFT (mode
,
1432 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1434 gen_rtx_LSHIFTRT (mode
, sub
,
1440 if (set_zero_bit_copies
> 8
1441 && (remainder
& ((1 << set_zero_bit_copies
) - 1)) == remainder
)
1445 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1446 rtx shift
= GEN_INT (set_zero_bit_copies
);
1448 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1450 gen_rtx_LSHIFTRT (mode
,
1453 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1455 gen_rtx_ASHIFT (mode
, sub
,
1461 if (const_ok_for_arm (temp1
= ARM_SIGN_EXTEND (~val
)))
1465 rtx sub
= subtargets
? gen_reg_rtx (mode
) : target
;
1466 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1467 gen_rtx_NOT (mode
, source
)));
1470 sub
= gen_reg_rtx (mode
);
1471 emit_insn (gen_rtx_SET (VOIDmode
, sub
,
1472 gen_rtx_AND (mode
, source
,
1474 emit_insn (gen_rtx_SET (VOIDmode
, target
,
1475 gen_rtx_NOT (mode
, sub
)));
1482 /* See if two shifts will do 2 or more insn's worth of work. */
1483 if (clear_sign_bit_copies
>= 16 && clear_sign_bit_copies
< 24)
1485 HOST_WIDE_INT shift_mask
= ((0xffffffff
1486 << (32 - clear_sign_bit_copies
))
1489 if ((remainder
| shift_mask
) != 0xffffffff)
1493 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1494 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1495 new_src
, source
, subtargets
, 1);
1500 rtx targ
= subtargets
? NULL_RTX
: target
;
1501 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1502 targ
, source
, subtargets
, 0);
1508 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1509 rtx shift
= GEN_INT (clear_sign_bit_copies
);
1511 emit_insn (gen_ashlsi3 (new_src
, source
, shift
));
1512 emit_insn (gen_lshrsi3 (target
, new_src
, shift
));
1518 if (clear_zero_bit_copies
>= 16 && clear_zero_bit_copies
< 24)
1520 HOST_WIDE_INT shift_mask
= (1 << clear_zero_bit_copies
) - 1;
1522 if ((remainder
| shift_mask
) != 0xffffffff)
1526 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1528 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1529 new_src
, source
, subtargets
, 1);
1534 rtx targ
= subtargets
? NULL_RTX
: target
;
1536 insns
= arm_gen_constant (AND
, mode
, remainder
| shift_mask
,
1537 targ
, source
, subtargets
, 0);
1543 rtx new_src
= subtargets
? gen_reg_rtx (mode
) : target
;
1544 rtx shift
= GEN_INT (clear_zero_bit_copies
);
1546 emit_insn (gen_lshrsi3 (new_src
, source
, shift
));
1547 emit_insn (gen_ashlsi3 (target
, new_src
, shift
));
1559 for (i
= 0; i
< 32; i
++)
1560 if (remainder
& (1 << i
))
1563 if (code
== AND
|| (can_invert
&& num_bits_set
> 16))
1564 remainder
= (~remainder
) & 0xffffffff;
1565 else if (code
== PLUS
&& num_bits_set
> 16)
1566 remainder
= (-remainder
) & 0xffffffff;
1573 /* Now try and find a way of doing the job in either two or three
1575 We start by looking for the largest block of zeros that are aligned on
1576 a 2-bit boundary, we then fill up the temps, wrapping around to the
1577 top of the word when we drop off the bottom.
1578 In the worst case this code should produce no more than four insns. */
1581 int best_consecutive_zeros
= 0;
1583 for (i
= 0; i
< 32; i
+= 2)
1585 int consecutive_zeros
= 0;
1587 if (!(remainder
& (3 << i
)))
1589 while ((i
< 32) && !(remainder
& (3 << i
)))
1591 consecutive_zeros
+= 2;
1594 if (consecutive_zeros
> best_consecutive_zeros
)
1596 best_consecutive_zeros
= consecutive_zeros
;
1597 best_start
= i
- consecutive_zeros
;
1603 /* So long as it won't require any more insns to do so, it's
1604 desirable to emit a small constant (in bits 0...9) in the last
1605 insn. This way there is more chance that it can be combined with
1606 a later addressing insn to form a pre-indexed load or store
1607 operation. Consider:
1609 *((volatile int *)0xe0000100) = 1;
1610 *((volatile int *)0xe0000110) = 2;
1612 We want this to wind up as:
1616 str rB, [rA, #0x100]
1618 str rB, [rA, #0x110]
1620 rather than having to synthesize both large constants from scratch.
1622 Therefore, we calculate how many insns would be required to emit
1623 the constant starting from `best_start', and also starting from
1624 zero (ie with bit 31 first to be output). If `best_start' doesn't
1625 yield a shorter sequence, we may as well use zero. */
1627 && ((((unsigned HOST_WIDE_INT
) 1) << best_start
) < remainder
)
1628 && (count_insns_for_constant (remainder
, 0) <=
1629 count_insns_for_constant (remainder
, best_start
)))
1632 /* Now start emitting the insns. */
1640 if (remainder
& (3 << (i
- 2)))
1645 temp1
= remainder
& ((0x0ff << end
)
1646 | ((i
< end
) ? (0xff >> (32 - end
)) : 0));
1647 remainder
&= ~temp1
;
1651 rtx new_src
, temp1_rtx
;
1653 if (code
== SET
|| code
== MINUS
)
1655 new_src
= (subtargets
? gen_reg_rtx (mode
) : target
);
1656 if (can_invert
&& code
!= MINUS
)
1661 if (remainder
&& subtargets
)
1662 new_src
= gen_reg_rtx (mode
);
1667 else if (can_negate
)
1671 temp1
= trunc_int_for_mode (temp1
, mode
);
1672 temp1_rtx
= GEN_INT (temp1
);
1676 else if (code
== MINUS
)
1677 temp1_rtx
= gen_rtx_MINUS (mode
, temp1_rtx
, source
);
1679 temp1_rtx
= gen_rtx_fmt_ee (code
, mode
, source
, temp1_rtx
);
1681 emit_insn (gen_rtx_SET (VOIDmode
, new_src
, temp1_rtx
));
1690 else if (code
== MINUS
)
1704 /* Canonicalize a comparison so that we are more likely to recognize it.
1705 This can be done for a few constant compares, where we can make the
1706 immediate value easier to load. */
1709 arm_canonicalize_comparison (code
, op1
)
1713 unsigned HOST_WIDE_INT i
= INTVAL (*op1
);
1723 if (i
!= ((((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1)) - 1)
1724 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
1726 *op1
= GEN_INT (i
+ 1);
1727 return code
== GT
? GE
: LT
;
1733 if (i
!= (((unsigned HOST_WIDE_INT
) 1) << (HOST_BITS_PER_WIDE_INT
- 1))
1734 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
1736 *op1
= GEN_INT (i
- 1);
1737 return code
== GE
? GT
: LE
;
1743 if (i
!= ~((unsigned HOST_WIDE_INT
) 0)
1744 && (const_ok_for_arm (i
+ 1) || const_ok_for_arm (-(i
+ 1))))
1746 *op1
= GEN_INT (i
+ 1);
1747 return code
== GTU
? GEU
: LTU
;
1754 && (const_ok_for_arm (i
- 1) || const_ok_for_arm (-(i
- 1))))
1756 *op1
= GEN_INT (i
- 1);
1757 return code
== GEU
? GTU
: LEU
;
1768 /* Decide whether a type should be returned in memory (true)
1769 or in a register (false). This is called by the macro
1770 RETURN_IN_MEMORY. */
1773 arm_return_in_memory (type
)
1778 if (!AGGREGATE_TYPE_P (type
))
1779 /* All simple types are returned in registers. */
1782 size
= int_size_in_bytes (type
);
1786 /* ATPCS returns aggregate types in memory only if they are
1787 larger than a word (or are variable size). */
1788 return (size
< 0 || size
> UNITS_PER_WORD
);
1791 /* For the arm-wince targets we choose to be compitable with Microsoft's
1792 ARM and Thumb compilers, which always return aggregates in memory. */
1794 /* All structures/unions bigger than one word are returned in memory.
1795 Also catch the case where int_size_in_bytes returns -1. In this case
1796 the aggregate is either huge or of varaible size, and in either case
1797 we will want to return it via memory and not in a register. */
1798 if (size
< 0 || size
> UNITS_PER_WORD
)
1801 if (TREE_CODE (type
) == RECORD_TYPE
)
1805 /* For a struct the APCS says that we only return in a register
1806 if the type is 'integer like' and every addressable element
1807 has an offset of zero. For practical purposes this means
1808 that the structure can have at most one non bit-field element
1809 and that this element must be the first one in the structure. */
1811 /* Find the first field, ignoring non FIELD_DECL things which will
1812 have been created by C++. */
1813 for (field
= TYPE_FIELDS (type
);
1814 field
&& TREE_CODE (field
) != FIELD_DECL
;
1815 field
= TREE_CHAIN (field
))
1819 return 0; /* An empty structure. Allowed by an extension to ANSI C. */
1821 /* Check that the first field is valid for returning in a register. */
1823 /* ... Floats are not allowed */
1824 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
1827 /* ... Aggregates that are not themselves valid for returning in
1828 a register are not allowed. */
1829 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
1832 /* Now check the remaining fields, if any. Only bitfields are allowed,
1833 since they are not addressable. */
1834 for (field
= TREE_CHAIN (field
);
1836 field
= TREE_CHAIN (field
))
1838 if (TREE_CODE (field
) != FIELD_DECL
)
1841 if (!DECL_BIT_FIELD_TYPE (field
))
1848 if (TREE_CODE (type
) == UNION_TYPE
)
1852 /* Unions can be returned in registers if every element is
1853 integral, or can be returned in an integer register. */
1854 for (field
= TYPE_FIELDS (type
);
1856 field
= TREE_CHAIN (field
))
1858 if (TREE_CODE (field
) != FIELD_DECL
)
1861 if (FLOAT_TYPE_P (TREE_TYPE (field
)))
1864 if (RETURN_IN_MEMORY (TREE_TYPE (field
)))
1870 #endif /* not ARM_WINCE */
1872 /* Return all other types in memory. */
1876 /* Indicate whether or not words of a double are in big-endian order. */
1879 arm_float_words_big_endian ()
1882 /* For FPA, float words are always big-endian. For VFP, floats words
1883 follow the memory system mode. */
1885 if (TARGET_HARD_FLOAT
)
1887 /* FIXME: TARGET_HARD_FLOAT currently implies FPA. */
1892 return (TARGET_BIG_END
? 1 : 0);
1897 /* Initialize a variable CUM of type CUMULATIVE_ARGS
1898 for a call to a function whose data type is FNTYPE.
1899 For a library call, FNTYPE is NULL. */
1901 arm_init_cumulative_args (pcum
, fntype
, libname
, indirect
)
1902 CUMULATIVE_ARGS
* pcum
;
1904 rtx libname ATTRIBUTE_UNUSED
;
1905 int indirect ATTRIBUTE_UNUSED
;
1907 /* On the ARM, the offset starts at 0. */
1908 pcum
->nregs
= ((fntype
&& aggregate_value_p (TREE_TYPE (fntype
))) ? 1 : 0);
1910 pcum
->call_cookie
= CALL_NORMAL
;
1912 if (TARGET_LONG_CALLS
)
1913 pcum
->call_cookie
= CALL_LONG
;
1915 /* Check for long call/short call attributes. The attributes
1916 override any command line option. */
1919 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (fntype
)))
1920 pcum
->call_cookie
= CALL_SHORT
;
1921 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype
)))
1922 pcum
->call_cookie
= CALL_LONG
;
1926 /* Determine where to put an argument to a function.
1927 Value is zero to push the argument on the stack,
1928 or a hard register in which to store the argument.
1930 MODE is the argument's machine mode.
1931 TYPE is the data type of the argument (as a tree).
1932 This is null for libcalls where that information may
1934 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1935 the preceding args and about the function being called.
1936 NAMED is nonzero if this argument is a named parameter
1937 (otherwise it is an extra parameter matching an ellipsis). */
1940 arm_function_arg (pcum
, mode
, type
, named
)
1941 CUMULATIVE_ARGS
* pcum
;
1942 enum machine_mode mode
;
1943 tree type ATTRIBUTE_UNUSED
;
1946 if (mode
== VOIDmode
)
1947 /* Compute operand 2 of the call insn. */
1948 return GEN_INT (pcum
->call_cookie
);
1950 if (!named
|| pcum
->nregs
>= NUM_ARG_REGS
)
1953 return gen_rtx_REG (mode
, pcum
->nregs
);
1956 /* Encode the current state of the #pragma [no_]long_calls. */
1959 OFF
, /* No #pramgma [no_]long_calls is in effect. */
1960 LONG
, /* #pragma long_calls is in effect. */
1961 SHORT
/* #pragma no_long_calls is in effect. */
1964 static arm_pragma_enum arm_pragma_long_calls
= OFF
;
1967 arm_pr_long_calls (pfile
)
1968 cpp_reader
* pfile ATTRIBUTE_UNUSED
;
1970 arm_pragma_long_calls
= LONG
;
1974 arm_pr_no_long_calls (pfile
)
1975 cpp_reader
* pfile ATTRIBUTE_UNUSED
;
1977 arm_pragma_long_calls
= SHORT
;
1981 arm_pr_long_calls_off (pfile
)
1982 cpp_reader
* pfile ATTRIBUTE_UNUSED
;
1984 arm_pragma_long_calls
= OFF
;
1987 /* Table of machine attributes. */
1988 const struct attribute_spec arm_attribute_table
[] =
1990 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
1991 /* Function calls made to this symbol must be done indirectly, because
1992 it may lie outside of the 26 bit addressing range of a normal function
1994 { "long_call", 0, 0, false, true, true, NULL
},
1995 /* Whereas these functions are always known to reside within the 26 bit
1996 addressing range. */
1997 { "short_call", 0, 0, false, true, true, NULL
},
1998 /* Interrupt Service Routines have special prologue and epilogue requirements. */
1999 { "isr", 0, 1, false, false, false, arm_handle_isr_attribute
},
2000 { "interrupt", 0, 1, false, false, false, arm_handle_isr_attribute
},
2001 { "naked", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2003 /* ARM/PE has three new attributes:
2005 dllexport - for exporting a function/variable that will live in a dll
2006 dllimport - for importing a function/variable from a dll
2008 Microsoft allows multiple declspecs in one __declspec, separating
2009 them with spaces. We do NOT support this. Instead, use __declspec
2012 { "dllimport", 0, 0, true, false, false, NULL
},
2013 { "dllexport", 0, 0, true, false, false, NULL
},
2014 { "interfacearm", 0, 0, true, false, false, arm_handle_fndecl_attribute
},
2016 { NULL
, 0, 0, false, false, false, NULL
}
2019 /* Handle an attribute requiring a FUNCTION_DECL;
2020 arguments as in struct attribute_spec.handler. */
2023 arm_handle_fndecl_attribute (node
, name
, args
, flags
, no_add_attrs
)
2026 tree args ATTRIBUTE_UNUSED
;
2027 int flags ATTRIBUTE_UNUSED
;
2028 bool * no_add_attrs
;
2030 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2032 warning ("`%s' attribute only applies to functions",
2033 IDENTIFIER_POINTER (name
));
2034 *no_add_attrs
= true;
2040 /* Handle an "interrupt" or "isr" attribute;
2041 arguments as in struct attribute_spec.handler. */
2044 arm_handle_isr_attribute (node
, name
, args
, flags
, no_add_attrs
)
2049 bool * no_add_attrs
;
2053 if (TREE_CODE (*node
) != FUNCTION_DECL
)
2055 warning ("`%s' attribute only applies to functions",
2056 IDENTIFIER_POINTER (name
));
2057 *no_add_attrs
= true;
2059 /* FIXME: the argument if any is checked for type attributes;
2060 should it be checked for decl ones? */
2064 if (TREE_CODE (*node
) == FUNCTION_TYPE
2065 || TREE_CODE (*node
) == METHOD_TYPE
)
2067 if (arm_isr_value (args
) == ARM_FT_UNKNOWN
)
2069 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
2070 *no_add_attrs
= true;
2073 else if (TREE_CODE (*node
) == POINTER_TYPE
2074 && (TREE_CODE (TREE_TYPE (*node
)) == FUNCTION_TYPE
2075 || TREE_CODE (TREE_TYPE (*node
)) == METHOD_TYPE
)
2076 && arm_isr_value (args
) != ARM_FT_UNKNOWN
)
2078 *node
= build_type_copy (*node
);
2079 TREE_TYPE (*node
) = build_type_attribute_variant
2081 tree_cons (name
, args
, TYPE_ATTRIBUTES (TREE_TYPE (*node
))));
2082 *no_add_attrs
= true;
2086 /* Possibly pass this attribute on from the type to a decl. */
2087 if (flags
& ((int) ATTR_FLAG_DECL_NEXT
2088 | (int) ATTR_FLAG_FUNCTION_NEXT
2089 | (int) ATTR_FLAG_ARRAY_NEXT
))
2091 *no_add_attrs
= true;
2092 return tree_cons (name
, args
, NULL_TREE
);
2096 warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name
));
2104 /* Return 0 if the attributes for two types are incompatible, 1 if they
2105 are compatible, and 2 if they are nearly compatible (which causes a
2106 warning to be generated). */
2109 arm_comp_type_attributes (type1
, type2
)
2115 /* Check for mismatch of non-default calling convention. */
2116 if (TREE_CODE (type1
) != FUNCTION_TYPE
)
2119 /* Check for mismatched call attributes. */
2120 l1
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2121 l2
= lookup_attribute ("long_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2122 s1
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type1
)) != NULL
;
2123 s2
= lookup_attribute ("short_call", TYPE_ATTRIBUTES (type2
)) != NULL
;
2125 /* Only bother to check if an attribute is defined. */
2126 if (l1
| l2
| s1
| s2
)
2128 /* If one type has an attribute, the other must have the same attribute. */
2129 if ((l1
!= l2
) || (s1
!= s2
))
2132 /* Disallow mixed attributes. */
2133 if ((l1
& s2
) || (l2
& s1
))
2137 /* Check for mismatched ISR attribute. */
2138 l1
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type1
)) != NULL
;
2140 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1
)) != NULL
;
2141 l2
= lookup_attribute ("isr", TYPE_ATTRIBUTES (type2
)) != NULL
;
2143 l1
= lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2
)) != NULL
;
2150 /* Encode long_call or short_call attribute by prefixing
2151 symbol name in DECL with a special character FLAG. */
2154 arm_encode_call_attribute (decl
, flag
)
2158 const char * str
= XSTR (XEXP (DECL_RTL (decl
), 0), 0);
2159 int len
= strlen (str
);
2162 /* Do not allow weak functions to be treated as short call. */
2163 if (DECL_WEAK (decl
) && flag
== SHORT_CALL_FLAG_CHAR
)
2166 newstr
= alloca (len
+ 2);
2168 strcpy (newstr
+ 1, str
);
2170 newstr
= (char *) ggc_alloc_string (newstr
, len
+ 1);
2171 XSTR (XEXP (DECL_RTL (decl
), 0), 0) = newstr
;
2174 /* Assigns default attributes to newly defined type. This is used to
2175 set short_call/long_call attributes for function types of
2176 functions defined inside corresponding #pragma scopes. */
2179 arm_set_default_type_attributes (type
)
2182 /* Add __attribute__ ((long_call)) to all functions, when
2183 inside #pragma long_calls or __attribute__ ((short_call)),
2184 when inside #pragma no_long_calls. */
2185 if (TREE_CODE (type
) == FUNCTION_TYPE
|| TREE_CODE (type
) == METHOD_TYPE
)
2187 tree type_attr_list
, attr_name
;
2188 type_attr_list
= TYPE_ATTRIBUTES (type
);
2190 if (arm_pragma_long_calls
== LONG
)
2191 attr_name
= get_identifier ("long_call");
2192 else if (arm_pragma_long_calls
== SHORT
)
2193 attr_name
= get_identifier ("short_call");
2197 type_attr_list
= tree_cons (attr_name
, NULL_TREE
, type_attr_list
);
2198 TYPE_ATTRIBUTES (type
) = type_attr_list
;
2202 /* Return 1 if the operand is a SYMBOL_REF for a function known to be
2203 defined within the current compilation unit. If this caanot be
2204 determined, then 0 is returned. */
2207 current_file_function_operand (sym_ref
)
2210 /* This is a bit of a fib. A function will have a short call flag
2211 applied to its name if it has the short call attribute, or it has
2212 already been defined within the current compilation unit. */
2213 if (ENCODED_SHORT_CALL_ATTR_P (XSTR (sym_ref
, 0)))
2216 /* The current function is always defined within the current compilation
2217 unit. if it s a weak definition however, then this may not be the real
2218 definition of the function, and so we have to say no. */
2219 if (sym_ref
== XEXP (DECL_RTL (current_function_decl
), 0)
2220 && !DECL_WEAK (current_function_decl
))
2223 /* We cannot make the determination - default to returning 0. */
2227 /* Return nonzero if a 32 bit "long_call" should be generated for
2228 this call. We generate a long_call if the function:
2230 a. has an __attribute__((long call))
2231 or b. is within the scope of a #pragma long_calls
2232 or c. the -mlong-calls command line switch has been specified
2234 However we do not generate a long call if the function:
2236 d. has an __attribute__ ((short_call))
2237 or e. is inside the scope of a #pragma no_long_calls
2238 or f. has an __attribute__ ((section))
2239 or g. is defined within the current compilation unit.
2241 This function will be called by C fragments contained in the machine
2242 description file. CALL_REF and CALL_COOKIE correspond to the matched
2243 rtl operands. CALL_SYMBOL is used to distinguish between
2244 two different callers of the function. It is set to 1 in the
2245 "call_symbol" and "call_symbol_value" patterns and to 0 in the "call"
2246 and "call_value" patterns. This is because of the difference in the
2247 SYM_REFs passed by these patterns. */
2250 arm_is_longcall_p (sym_ref
, call_cookie
, call_symbol
)
2257 if (GET_CODE (sym_ref
) != MEM
)
2260 sym_ref
= XEXP (sym_ref
, 0);
2263 if (GET_CODE (sym_ref
) != SYMBOL_REF
)
2266 if (call_cookie
& CALL_SHORT
)
2269 if (TARGET_LONG_CALLS
&& flag_function_sections
)
2272 if (current_file_function_operand (sym_ref
))
2275 return (call_cookie
& CALL_LONG
)
2276 || ENCODED_LONG_CALL_ATTR_P (XSTR (sym_ref
, 0))
2277 || TARGET_LONG_CALLS
;
2280 /* Return nonzero if it is ok to make a tail-call to DECL. */
2283 arm_function_ok_for_sibcall (decl
)
2286 int call_type
= TARGET_LONG_CALLS
? CALL_LONG
: CALL_NORMAL
;
2288 /* Never tailcall something for which we have no decl, or if we
2289 are in Thumb mode. */
2290 if (decl
== NULL
|| TARGET_THUMB
)
2293 /* Get the calling method. */
2294 if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2295 call_type
= CALL_SHORT
;
2296 else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (TREE_TYPE (decl
))))
2297 call_type
= CALL_LONG
;
2299 /* Cannot tail-call to long calls, since these are out of range of
2300 a branch instruction. However, if not compiling PIC, we know
2301 we can reach the symbol if it is in this compilation unit. */
2302 if (call_type
== CALL_LONG
&& (flag_pic
|| !TREE_ASM_WRITTEN (decl
)))
2305 /* If we are interworking and the function is not declared static
2306 then we can't tail-call it unless we know that it exists in this
2307 compilation unit (since it might be a Thumb routine). */
2308 if (TARGET_INTERWORK
&& TREE_PUBLIC (decl
) && !TREE_ASM_WRITTEN (decl
))
2311 /* Never tailcall from an ISR routine - it needs a special exit sequence. */
2312 if (IS_INTERRUPT (arm_current_func_type ()))
2315 /* Everything else is ok. */
2321 legitimate_pic_operand_p (x
)
2326 && (GET_CODE (x
) == SYMBOL_REF
2327 || (GET_CODE (x
) == CONST
2328 && GET_CODE (XEXP (x
, 0)) == PLUS
2329 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == SYMBOL_REF
)))
2336 legitimize_pic_address (orig
, mode
, reg
)
2338 enum machine_mode mode
;
2341 if (GET_CODE (orig
) == SYMBOL_REF
2342 || GET_CODE (orig
) == LABEL_REF
)
2344 #ifndef AOF_ASSEMBLER
2345 rtx pic_ref
, address
;
2355 reg
= gen_reg_rtx (Pmode
);
2360 #ifdef AOF_ASSEMBLER
2361 /* The AOF assembler can generate relocations for these directly, and
2362 understands that the PIC register has to be added into the offset. */
2363 insn
= emit_insn (gen_pic_load_addr_based (reg
, orig
));
2366 address
= gen_reg_rtx (Pmode
);
2371 emit_insn (gen_pic_load_addr_arm (address
, orig
));
2373 emit_insn (gen_pic_load_addr_thumb (address
, orig
));
2375 if ((GET_CODE (orig
) == LABEL_REF
2376 || (GET_CODE (orig
) == SYMBOL_REF
&&
2377 ENCODED_SHORT_CALL_ATTR_P (XSTR (orig
, 0))))
2379 pic_ref
= gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
, address
);
2382 pic_ref
= gen_rtx_MEM (Pmode
,
2383 gen_rtx_PLUS (Pmode
, pic_offset_table_rtx
,
2385 RTX_UNCHANGING_P (pic_ref
) = 1;
2388 insn
= emit_move_insn (reg
, pic_ref
);
2390 current_function_uses_pic_offset_table
= 1;
2391 /* Put a REG_EQUAL note on this insn, so that it can be optimized
2393 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_EQUAL
, orig
,
2397 else if (GET_CODE (orig
) == CONST
)
2401 if (GET_CODE (XEXP (orig
, 0)) == PLUS
2402 && XEXP (XEXP (orig
, 0), 0) == pic_offset_table_rtx
)
2410 reg
= gen_reg_rtx (Pmode
);
2413 if (GET_CODE (XEXP (orig
, 0)) == PLUS
)
2415 base
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 0), Pmode
, reg
);
2416 offset
= legitimize_pic_address (XEXP (XEXP (orig
, 0), 1), Pmode
,
2417 base
== reg
? 0 : reg
);
2422 if (GET_CODE (offset
) == CONST_INT
)
2424 /* The base register doesn't really matter, we only want to
2425 test the index for the appropriate mode. */
2426 ARM_GO_IF_LEGITIMATE_INDEX (mode
, 0, offset
, win
);
2428 if (!no_new_pseudos
)
2429 offset
= force_reg (Pmode
, offset
);
2434 if (GET_CODE (offset
) == CONST_INT
)
2435 return plus_constant (base
, INTVAL (offset
));
2438 if (GET_MODE_SIZE (mode
) > 4
2439 && (GET_MODE_CLASS (mode
) == MODE_INT
2440 || TARGET_SOFT_FLOAT
))
2442 emit_insn (gen_addsi3 (reg
, base
, offset
));
2446 return gen_rtx_PLUS (Pmode
, base
, offset
);
2452 /* Generate code to load the PIC register. PROLOGUE is true if
2453 called from arm_expand_prologue (in which case we want the
2454 generated insns at the start of the function); false if called
2455 by an exception receiver that needs the PIC register reloaded
2456 (in which case the insns are just dumped at the current location). */
2459 arm_finalize_pic (prologue
)
2460 int prologue ATTRIBUTE_UNUSED
;
2462 #ifndef AOF_ASSEMBLER
2463 rtx l1
, pic_tmp
, pic_tmp2
, seq
, pic_rtx
;
2464 rtx global_offset_table
;
2466 if (current_function_uses_pic_offset_table
== 0 || TARGET_SINGLE_PIC_BASE
)
2473 l1
= gen_label_rtx ();
2475 global_offset_table
= gen_rtx_SYMBOL_REF (Pmode
, "_GLOBAL_OFFSET_TABLE_");
2476 /* On the ARM the PC register contains 'dot + 8' at the time of the
2477 addition, on the Thumb it is 'dot + 4'. */
2478 pic_tmp
= plus_constant (gen_rtx_LABEL_REF (Pmode
, l1
), TARGET_ARM
? 8 : 4);
2480 pic_tmp2
= gen_rtx_CONST (VOIDmode
,
2481 gen_rtx_PLUS (Pmode
, global_offset_table
, pc_rtx
));
2483 pic_tmp2
= gen_rtx_CONST (VOIDmode
, global_offset_table
);
2485 pic_rtx
= gen_rtx_CONST (Pmode
, gen_rtx_MINUS (Pmode
, pic_tmp2
, pic_tmp
));
2489 emit_insn (gen_pic_load_addr_arm (pic_offset_table_rtx
, pic_rtx
));
2490 emit_insn (gen_pic_add_dot_plus_eight (pic_offset_table_rtx
, l1
));
2494 emit_insn (gen_pic_load_addr_thumb (pic_offset_table_rtx
, pic_rtx
));
2495 emit_insn (gen_pic_add_dot_plus_four (pic_offset_table_rtx
, l1
));
2501 emit_insn_after (seq
, get_insns ());
2505 /* Need to emit this whether or not we obey regdecls,
2506 since setjmp/longjmp can cause life info to screw up. */
2507 emit_insn (gen_rtx_USE (VOIDmode
, pic_offset_table_rtx
));
2508 #endif /* AOF_ASSEMBLER */
2511 #define REG_OR_SUBREG_REG(X) \
2512 (GET_CODE (X) == REG \
2513 || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG))
2515 #define REG_OR_SUBREG_RTX(X) \
2516 (GET_CODE (X) == REG ? (X) : SUBREG_REG (X))
2518 #ifndef COSTS_N_INSNS
2519 #define COSTS_N_INSNS(N) ((N) * 4 - 2)
2523 arm_rtx_costs (x
, code
, outer
)
2526 enum rtx_code outer
;
2528 enum machine_mode mode
= GET_MODE (x
);
2529 enum rtx_code subcode
;
2545 return COSTS_N_INSNS (1);
2548 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2551 unsigned HOST_WIDE_INT i
= INTVAL (XEXP (x
, 1));
2558 return COSTS_N_INSNS (2) + cycles
;
2560 return COSTS_N_INSNS (1) + 16;
2563 return (COSTS_N_INSNS (1)
2564 + 4 * ((GET_CODE (SET_SRC (x
)) == MEM
)
2565 + GET_CODE (SET_DEST (x
)) == MEM
));
2570 if ((unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
2572 if (thumb_shiftable_const (INTVAL (x
)))
2573 return COSTS_N_INSNS (2);
2574 return COSTS_N_INSNS (3);
2576 else if (outer
== PLUS
2577 && INTVAL (x
) < 256 && INTVAL (x
) > -256)
2579 else if (outer
== COMPARE
2580 && (unsigned HOST_WIDE_INT
) INTVAL (x
) < 256)
2582 else if (outer
== ASHIFT
|| outer
== ASHIFTRT
2583 || outer
== LSHIFTRT
)
2585 return COSTS_N_INSNS (2);
2591 return COSTS_N_INSNS (3);
2610 /* XXX another guess. */
2611 /* Memory costs quite a lot for the first word, but subsequent words
2612 load at the equivalent of a single insn each. */
2613 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
2614 + ((GET_CODE (x
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (x
))
2619 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
2624 /* XXX still guessing. */
2625 switch (GET_MODE (XEXP (x
, 0)))
2628 return (1 + (mode
== DImode
? 4 : 0)
2629 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2632 return (4 + (mode
== DImode
? 4 : 0)
2633 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2636 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2650 fprintf (stderr
, "unexpected code for thumb in rtx_costs: %s\n",
2660 /* Memory costs quite a lot for the first word, but subsequent words
2661 load at the equivalent of a single insn each. */
2662 return (10 + 4 * ((GET_MODE_SIZE (mode
) - 1) / UNITS_PER_WORD
)
2663 + (GET_CODE (x
) == SYMBOL_REF
2664 && CONSTANT_POOL_ADDRESS_P (x
) ? 4 : 0));
2671 if (mode
== SImode
&& GET_CODE (XEXP (x
, 1)) == REG
)
2678 case ASHIFT
: case LSHIFTRT
: case ASHIFTRT
:
2680 return (8 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : 8)
2681 + ((GET_CODE (XEXP (x
, 0)) == REG
2682 || (GET_CODE (XEXP (x
, 0)) == SUBREG
2683 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
2685 return (1 + ((GET_CODE (XEXP (x
, 0)) == REG
2686 || (GET_CODE (XEXP (x
, 0)) == SUBREG
2687 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == REG
))
2689 + ((GET_CODE (XEXP (x
, 1)) == REG
2690 || (GET_CODE (XEXP (x
, 1)) == SUBREG
2691 && GET_CODE (SUBREG_REG (XEXP (x
, 1))) == REG
)
2692 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
))
2697 return (4 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 8)
2698 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
2699 || (GET_CODE (XEXP (x
, 0)) == CONST_INT
2700 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))))
2703 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2704 return (2 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
2705 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
2706 && const_double_rtx_ok_for_fpu (XEXP (x
, 1))))
2708 + ((REG_OR_SUBREG_REG (XEXP (x
, 0))
2709 || (GET_CODE (XEXP (x
, 0)) == CONST_DOUBLE
2710 && const_double_rtx_ok_for_fpu (XEXP (x
, 0))))
2713 if (((GET_CODE (XEXP (x
, 0)) == CONST_INT
2714 && const_ok_for_arm (INTVAL (XEXP (x
, 0)))
2715 && REG_OR_SUBREG_REG (XEXP (x
, 1))))
2716 || (((subcode
= GET_CODE (XEXP (x
, 1))) == ASHIFT
2717 || subcode
== ASHIFTRT
|| subcode
== LSHIFTRT
2718 || subcode
== ROTATE
|| subcode
== ROTATERT
2720 && GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
2721 && ((INTVAL (XEXP (XEXP (x
, 1), 1)) &
2722 (INTVAL (XEXP (XEXP (x
, 1), 1)) - 1)) == 0)))
2723 && REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 0))
2724 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 1), 1))
2725 || GET_CODE (XEXP (XEXP (x
, 1), 1)) == CONST_INT
)
2726 && REG_OR_SUBREG_REG (XEXP (x
, 0))))
2731 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2732 return (2 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
2733 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
2734 || (GET_CODE (XEXP (x
, 1)) == CONST_DOUBLE
2735 && const_double_rtx_ok_for_fpu (XEXP (x
, 1))))
2739 case AND
: case XOR
: case IOR
:
2742 /* Normally the frame registers will be spilt into reg+const during
2743 reload, so it is a bad idea to combine them with other instructions,
2744 since then they might not be moved outside of loops. As a compromise
2745 we allow integration with ops that have a constant as their second
2747 if ((REG_OR_SUBREG_REG (XEXP (x
, 0))
2748 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))
2749 && GET_CODE (XEXP (x
, 1)) != CONST_INT
)
2750 || (REG_OR_SUBREG_REG (XEXP (x
, 0))
2751 && ARM_FRAME_RTX (REG_OR_SUBREG_RTX (XEXP (x
, 0)))))
2755 return (4 + extra_cost
+ (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 8)
2756 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
2757 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
2758 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
2761 if (REG_OR_SUBREG_REG (XEXP (x
, 0)))
2762 return (1 + (GET_CODE (XEXP (x
, 1)) == CONST_INT
? 0 : extra_cost
)
2763 + ((REG_OR_SUBREG_REG (XEXP (x
, 1))
2764 || (GET_CODE (XEXP (x
, 1)) == CONST_INT
2765 && const_ok_for_op (INTVAL (XEXP (x
, 1)), code
)))
2768 else if (REG_OR_SUBREG_REG (XEXP (x
, 1)))
2769 return (1 + extra_cost
2770 + ((((subcode
= GET_CODE (XEXP (x
, 0))) == ASHIFT
2771 || subcode
== LSHIFTRT
|| subcode
== ASHIFTRT
2772 || subcode
== ROTATE
|| subcode
== ROTATERT
2774 && GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
2775 && ((INTVAL (XEXP (XEXP (x
, 0), 1)) &
2776 (INTVAL (XEXP (XEXP (x
, 0), 1)) - 1)) == 0)))
2777 && (REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 0)))
2778 && ((REG_OR_SUBREG_REG (XEXP (XEXP (x
, 0), 1)))
2779 || GET_CODE (XEXP (XEXP (x
, 0), 1)) == CONST_INT
))
2785 /* There is no point basing this on the tuning, since it is always the
2786 fast variant if it exists at all. */
2787 if (arm_fast_multiply
&& mode
== DImode
2788 && (GET_CODE (XEXP (x
, 0)) == GET_CODE (XEXP (x
, 1)))
2789 && (GET_CODE (XEXP (x
, 0)) == ZERO_EXTEND
2790 || GET_CODE (XEXP (x
, 0)) == SIGN_EXTEND
))
2793 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
2797 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
2799 unsigned HOST_WIDE_INT i
= (INTVAL (XEXP (x
, 1))
2800 & (unsigned HOST_WIDE_INT
) 0xffffffff);
2801 int add_cost
= const_ok_for_arm (i
) ? 4 : 8;
2804 /* Tune as appropriate. */
2805 int booth_unit_size
= ((tune_flags
& FL_FAST_MULT
) ? 8 : 2);
2807 for (j
= 0; i
&& j
< 32; j
+= booth_unit_size
)
2809 i
>>= booth_unit_size
;
2816 return (((tune_flags
& FL_FAST_MULT
) ? 8 : 30)
2817 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4)
2818 + (REG_OR_SUBREG_REG (XEXP (x
, 1)) ? 0 : 4));
2821 if (arm_fast_multiply
&& mode
== SImode
2822 && GET_CODE (XEXP (x
, 0)) == LSHIFTRT
2823 && GET_CODE (XEXP (XEXP (x
, 0), 0)) == MULT
2824 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0))
2825 == GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 1)))
2826 && (GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == ZERO_EXTEND
2827 || GET_CODE (XEXP (XEXP (XEXP (x
, 0), 0), 0)) == SIGN_EXTEND
))
2832 if (GET_MODE_CLASS (mode
) == MODE_FLOAT
)
2833 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 6);
2837 return 4 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
2839 return 1 + (REG_OR_SUBREG_REG (XEXP (x
, 0)) ? 0 : 4);
2842 if (GET_CODE (XEXP (x
, 1)) == PC
|| GET_CODE (XEXP (x
, 2)) == PC
)
2850 return 4 + (mode
== DImode
? 4 : 0);
2853 if (GET_MODE (XEXP (x
, 0)) == QImode
)
2854 return (4 + (mode
== DImode
? 4 : 0)
2855 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2858 switch (GET_MODE (XEXP (x
, 0)))
2861 return (1 + (mode
== DImode
? 4 : 0)
2862 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2865 return (4 + (mode
== DImode
? 4 : 0)
2866 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2869 return (1 + (GET_CODE (XEXP (x
, 0)) == MEM
? 10 : 0));
2877 if (const_ok_for_arm (INTVAL (x
)))
2878 return outer
== SET
? 2 : -1;
2879 else if (outer
== AND
2880 && const_ok_for_arm (~INTVAL (x
)))
2882 else if ((outer
== COMPARE
2883 || outer
== PLUS
|| outer
== MINUS
)
2884 && const_ok_for_arm (-INTVAL (x
)))
2895 if (const_double_rtx_ok_for_fpu (x
))
2896 return outer
== SET
? 2 : -1;
2897 else if ((outer
== COMPARE
|| outer
== PLUS
)
2898 && neg_const_double_rtx_ok_for_fpu (x
))
2908 arm_adjust_cost (insn
, link
, dep
, cost
)
2916 /* Some true dependencies can have a higher cost depending
2917 on precisely how certain input operands are used. */
2919 && REG_NOTE_KIND (link
) == 0
2920 && recog_memoized (insn
) < 0
2921 && recog_memoized (dep
) < 0)
2923 int shift_opnum
= get_attr_shift (insn
);
2924 enum attr_type attr_type
= get_attr_type (dep
);
2926 /* If nonzero, SHIFT_OPNUM contains the operand number of a shifted
2927 operand for INSN. If we have a shifted input operand and the
2928 instruction we depend on is another ALU instruction, then we may
2929 have to account for an additional stall. */
2930 if (shift_opnum
!= 0 && attr_type
== TYPE_NORMAL
)
2932 rtx shifted_operand
;
2935 /* Get the shifted operand. */
2936 extract_insn (insn
);
2937 shifted_operand
= recog_data
.operand
[shift_opnum
];
2939 /* Iterate over all the operands in DEP. If we write an operand
2940 that overlaps with SHIFTED_OPERAND, then we have increase the
2941 cost of this dependency. */
2943 preprocess_constraints ();
2944 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
2946 /* We can ignore strict inputs. */
2947 if (recog_data
.operand_type
[opno
] == OP_IN
)
2950 if (reg_overlap_mentioned_p (recog_data
.operand
[opno
],
2957 /* XXX This is not strictly true for the FPA. */
2958 if (REG_NOTE_KIND (link
) == REG_DEP_ANTI
2959 || REG_NOTE_KIND (link
) == REG_DEP_OUTPUT
)
2962 /* Call insns don't incur a stall, even if they follow a load. */
2963 if (REG_NOTE_KIND (link
) == 0
2964 && GET_CODE (insn
) == CALL_INSN
)
2967 if ((i_pat
= single_set (insn
)) != NULL
2968 && GET_CODE (SET_SRC (i_pat
)) == MEM
2969 && (d_pat
= single_set (dep
)) != NULL
2970 && GET_CODE (SET_DEST (d_pat
)) == MEM
)
2972 rtx src_mem
= XEXP (SET_SRC (i_pat
), 0);
2973 /* This is a load after a store, there is no conflict if the load reads
2974 from a cached area. Assume that loads from the stack, and from the
2975 constant pool are cached, and that others will miss. This is a
2978 if ((GET_CODE (src_mem
) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (src_mem
))
2979 || reg_mentioned_p (stack_pointer_rtx
, src_mem
)
2980 || reg_mentioned_p (frame_pointer_rtx
, src_mem
)
2981 || reg_mentioned_p (hard_frame_pointer_rtx
, src_mem
))
2988 /* This code has been fixed for cross compilation. */
2990 static int fpa_consts_inited
= 0;
2992 static const char * const strings_fpa
[8] =
2995 "4", "5", "0.5", "10"
2998 static REAL_VALUE_TYPE values_fpa
[8];
3006 for (i
= 0; i
< 8; i
++)
3008 r
= REAL_VALUE_ATOF (strings_fpa
[i
], DFmode
);
3012 fpa_consts_inited
= 1;
3015 /* Return TRUE if rtx X is a valid immediate FPU constant. */
3018 const_double_rtx_ok_for_fpu (x
)
3024 if (!fpa_consts_inited
)
3027 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3028 if (REAL_VALUE_MINUS_ZERO (r
))
3031 for (i
= 0; i
< 8; i
++)
3032 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
3038 /* Return TRUE if rtx X is a valid immediate FPU constant. */
3041 neg_const_double_rtx_ok_for_fpu (x
)
3047 if (!fpa_consts_inited
)
3050 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
3051 r
= REAL_VALUE_NEGATE (r
);
3052 if (REAL_VALUE_MINUS_ZERO (r
))
3055 for (i
= 0; i
< 8; i
++)
3056 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
3062 /* Predicates for `match_operand' and `match_operator'. */
3064 /* s_register_operand is the same as register_operand, but it doesn't accept
3067 This function exists because at the time it was put in it led to better
3068 code. SUBREG(MEM) always needs a reload in the places where
3069 s_register_operand is used, and this seemed to lead to excessive
3073 s_register_operand (op
, mode
)
3075 enum machine_mode mode
;
3077 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3080 if (GET_CODE (op
) == SUBREG
)
3081 op
= SUBREG_REG (op
);
3083 /* We don't consider registers whose class is NO_REGS
3084 to be a register operand. */
3085 /* XXX might have to check for lo regs only for thumb ??? */
3086 return (GET_CODE (op
) == REG
3087 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3088 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
3091 /* A hard register operand (even before reload. */
3094 arm_hard_register_operand (op
, mode
)
3096 enum machine_mode mode
;
3098 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3101 return (GET_CODE (op
) == REG
3102 && REGNO (op
) < FIRST_PSEUDO_REGISTER
);
3105 /* Only accept reg, subreg(reg), const_int. */
3108 reg_or_int_operand (op
, mode
)
3110 enum machine_mode mode
;
3112 if (GET_CODE (op
) == CONST_INT
)
3115 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3118 if (GET_CODE (op
) == SUBREG
)
3119 op
= SUBREG_REG (op
);
3121 /* We don't consider registers whose class is NO_REGS
3122 to be a register operand. */
3123 return (GET_CODE (op
) == REG
3124 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3125 || REGNO_REG_CLASS (REGNO (op
)) != NO_REGS
));
3128 /* Return 1 if OP is an item in memory, given that we are in reload. */
3131 arm_reload_memory_operand (op
, mode
)
3133 enum machine_mode mode ATTRIBUTE_UNUSED
;
3135 int regno
= true_regnum (op
);
3137 return (!CONSTANT_P (op
)
3139 || (GET_CODE (op
) == REG
3140 && REGNO (op
) >= FIRST_PSEUDO_REGISTER
)));
3143 /* Return 1 if OP is a valid memory address, but not valid for a signed byte
3144 memory access (architecture V4).
3145 MODE is QImode if called when computing constraints, or VOIDmode when
3146 emitting patterns. In this latter case we cannot use memory_operand()
3147 because it will fail on badly formed MEMs, which is precisly what we are
3151 bad_signed_byte_operand (op
, mode
)
3153 enum machine_mode mode ATTRIBUTE_UNUSED
;
3156 if ((mode
== QImode
&& !memory_operand (op
, mode
)) || GET_CODE (op
) != MEM
)
3159 if (GET_CODE (op
) != MEM
)
3164 /* A sum of anything more complex than reg + reg or reg + const is bad. */
3165 if ((GET_CODE (op
) == PLUS
|| GET_CODE (op
) == MINUS
)
3166 && (!s_register_operand (XEXP (op
, 0), VOIDmode
)
3167 || (!s_register_operand (XEXP (op
, 1), VOIDmode
)
3168 && GET_CODE (XEXP (op
, 1)) != CONST_INT
)))
3171 /* Big constants are also bad. */
3172 if (GET_CODE (op
) == PLUS
&& GET_CODE (XEXP (op
, 1)) == CONST_INT
3173 && (INTVAL (XEXP (op
, 1)) > 0xff
3174 || -INTVAL (XEXP (op
, 1)) > 0xff))
3177 /* Everything else is good, or can will automatically be made so. */
3181 /* Return TRUE for valid operands for the rhs of an ARM instruction. */
3184 arm_rhs_operand (op
, mode
)
3186 enum machine_mode mode
;
3188 return (s_register_operand (op
, mode
)
3189 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
))));
3192 /* Return TRUE for valid operands for the
3193 rhs of an ARM instruction, or a load. */
3196 arm_rhsm_operand (op
, mode
)
3198 enum machine_mode mode
;
3200 return (s_register_operand (op
, mode
)
3201 || (GET_CODE (op
) == CONST_INT
&& const_ok_for_arm (INTVAL (op
)))
3202 || memory_operand (op
, mode
));
3205 /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a
3206 constant that is valid when negated. */
3209 arm_add_operand (op
, mode
)
3211 enum machine_mode mode
;
3214 return thumb_cmp_operand (op
, mode
);
3216 return (s_register_operand (op
, mode
)
3217 || (GET_CODE (op
) == CONST_INT
3218 && (const_ok_for_arm (INTVAL (op
))
3219 || const_ok_for_arm (-INTVAL (op
)))));
3223 arm_not_operand (op
, mode
)
3225 enum machine_mode mode
;
3227 return (s_register_operand (op
, mode
)
3228 || (GET_CODE (op
) == CONST_INT
3229 && (const_ok_for_arm (INTVAL (op
))
3230 || const_ok_for_arm (~INTVAL (op
)))));
3233 /* Return TRUE if the operand is a memory reference which contains an
3234 offsettable address. */
3237 offsettable_memory_operand (op
, mode
)
3239 enum machine_mode mode
;
3241 if (mode
== VOIDmode
)
3242 mode
= GET_MODE (op
);
3244 return (mode
== GET_MODE (op
)
3245 && GET_CODE (op
) == MEM
3246 && offsettable_address_p (reload_completed
| reload_in_progress
,
3247 mode
, XEXP (op
, 0)));
3250 /* Return TRUE if the operand is a memory reference which is, or can be
3251 made word aligned by adjusting the offset. */
3254 alignable_memory_operand (op
, mode
)
3256 enum machine_mode mode
;
3260 if (mode
== VOIDmode
)
3261 mode
= GET_MODE (op
);
3263 if (mode
!= GET_MODE (op
) || GET_CODE (op
) != MEM
)
3268 return ((GET_CODE (reg
= op
) == REG
3269 || (GET_CODE (op
) == SUBREG
3270 && GET_CODE (reg
= SUBREG_REG (op
)) == REG
)
3271 || (GET_CODE (op
) == PLUS
3272 && GET_CODE (XEXP (op
, 1)) == CONST_INT
3273 && (GET_CODE (reg
= XEXP (op
, 0)) == REG
3274 || (GET_CODE (XEXP (op
, 0)) == SUBREG
3275 && GET_CODE (reg
= SUBREG_REG (XEXP (op
, 0))) == REG
))))
3276 && REGNO_POINTER_ALIGN (REGNO (reg
)) >= 32);
3279 /* Similar to s_register_operand, but does not allow hard integer
3283 f_register_operand (op
, mode
)
3285 enum machine_mode mode
;
3287 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3290 if (GET_CODE (op
) == SUBREG
)
3291 op
= SUBREG_REG (op
);
3293 /* We don't consider registers whose class is NO_REGS
3294 to be a register operand. */
3295 return (GET_CODE (op
) == REG
3296 && (REGNO (op
) >= FIRST_PSEUDO_REGISTER
3297 || REGNO_REG_CLASS (REGNO (op
)) == FPU_REGS
));
3300 /* Return TRUE for valid operands for the rhs of an FPU instruction. */
3303 fpu_rhs_operand (op
, mode
)
3305 enum machine_mode mode
;
3307 if (s_register_operand (op
, mode
))
3310 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3313 if (GET_CODE (op
) == CONST_DOUBLE
)
3314 return const_double_rtx_ok_for_fpu (op
);
3320 fpu_add_operand (op
, mode
)
3322 enum machine_mode mode
;
3324 if (s_register_operand (op
, mode
))
3327 if (GET_MODE (op
) != mode
&& mode
!= VOIDmode
)
3330 if (GET_CODE (op
) == CONST_DOUBLE
)
3331 return (const_double_rtx_ok_for_fpu (op
)
3332 || neg_const_double_rtx_ok_for_fpu (op
));
3337 /* Return nonzero if OP is a constant power of two. */
3340 power_of_two_operand (op
, mode
)
3342 enum machine_mode mode ATTRIBUTE_UNUSED
;
3344 if (GET_CODE (op
) == CONST_INT
)
3346 HOST_WIDE_INT value
= INTVAL (op
);
3348 return value
!= 0 && (value
& (value
- 1)) == 0;
3354 /* Return TRUE for a valid operand of a DImode operation.
3355 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
3356 Note that this disallows MEM(REG+REG), but allows
3357 MEM(PRE/POST_INC/DEC(REG)). */
3360 di_operand (op
, mode
)
3362 enum machine_mode mode
;
3364 if (s_register_operand (op
, mode
))
3367 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != DImode
)
3370 if (GET_CODE (op
) == SUBREG
)
3371 op
= SUBREG_REG (op
);
3373 switch (GET_CODE (op
))
3380 return memory_address_p (DImode
, XEXP (op
, 0));
3387 /* Like di_operand, but don't accept constants. */
3390 nonimmediate_di_operand (op
, mode
)
3392 enum machine_mode mode
;
3394 if (s_register_operand (op
, mode
))
3397 if (mode
!= VOIDmode
&& GET_MODE (op
) != VOIDmode
&& GET_MODE (op
) != DImode
)
3400 if (GET_CODE (op
) == SUBREG
)
3401 op
= SUBREG_REG (op
);
3403 if (GET_CODE (op
) == MEM
)
3404 return memory_address_p (DImode
, XEXP (op
, 0));
3409 /* Return TRUE for a valid operand of a DFmode operation when -msoft-float.
3410 Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address).
3411 Note that this disallows MEM(REG+REG), but allows
3412 MEM(PRE/POST_INC/DEC(REG)). */
3415 soft_df_operand (op
, mode
)
3417 enum machine_mode mode
;
3419 if (s_register_operand (op
, mode
))
3422 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
3425 if (GET_CODE (op
) == SUBREG
&& CONSTANT_P (SUBREG_REG (op
)))
3428 if (GET_CODE (op
) == SUBREG
)
3429 op
= SUBREG_REG (op
);
3431 switch (GET_CODE (op
))
3437 return memory_address_p (DFmode
, XEXP (op
, 0));
3444 /* Like soft_df_operand, but don't accept constants. */
3447 nonimmediate_soft_df_operand (op
, mode
)
3449 enum machine_mode mode
;
3451 if (s_register_operand (op
, mode
))
3454 if (mode
!= VOIDmode
&& GET_MODE (op
) != mode
)
3457 if (GET_CODE (op
) == SUBREG
)
3458 op
= SUBREG_REG (op
);
3460 if (GET_CODE (op
) == MEM
)
3461 return memory_address_p (DFmode
, XEXP (op
, 0));
3465 /* Return TRUE for valid index operands. */
3468 index_operand (op
, mode
)
3470 enum machine_mode mode
;
3472 return (s_register_operand (op
, mode
)
3473 || (immediate_operand (op
, mode
)
3474 && (GET_CODE (op
) != CONST_INT
3475 || (INTVAL (op
) < 4096 && INTVAL (op
) > -4096))));
3478 /* Return TRUE for valid shifts by a constant. This also accepts any
3479 power of two on the (somewhat overly relaxed) assumption that the
3480 shift operator in this case was a mult. */
3483 const_shift_operand (op
, mode
)
3485 enum machine_mode mode
;
3487 return (power_of_two_operand (op
, mode
)
3488 || (immediate_operand (op
, mode
)
3489 && (GET_CODE (op
) != CONST_INT
3490 || (INTVAL (op
) < 32 && INTVAL (op
) > 0))));
3493 /* Return TRUE for arithmetic operators which can be combined with a multiply
3497 shiftable_operator (x
, mode
)
3499 enum machine_mode mode
;
3503 if (GET_MODE (x
) != mode
)
3506 code
= GET_CODE (x
);
3508 return (code
== PLUS
|| code
== MINUS
3509 || code
== IOR
|| code
== XOR
|| code
== AND
);
3512 /* Return TRUE for binary logical operators. */
3515 logical_binary_operator (x
, mode
)
3517 enum machine_mode mode
;
3521 if (GET_MODE (x
) != mode
)
3524 code
= GET_CODE (x
);
3526 return (code
== IOR
|| code
== XOR
|| code
== AND
);
3529 /* Return TRUE for shift operators. */
3532 shift_operator (x
, mode
)
3534 enum machine_mode mode
;
3538 if (GET_MODE (x
) != mode
)
3541 code
= GET_CODE (x
);
3544 return power_of_two_operand (XEXP (x
, 1), mode
);
3546 return (code
== ASHIFT
|| code
== ASHIFTRT
|| code
== LSHIFTRT
3547 || code
== ROTATERT
);
3550 /* Return TRUE if x is EQ or NE. */
3553 equality_operator (x
, mode
)
3555 enum machine_mode mode ATTRIBUTE_UNUSED
;
3557 return GET_CODE (x
) == EQ
|| GET_CODE (x
) == NE
;
3560 /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */
3563 arm_comparison_operator (x
, mode
)
3565 enum machine_mode mode
;
3567 return (comparison_operator (x
, mode
)
3568 && GET_CODE (x
) != LTGT
3569 && GET_CODE (x
) != UNEQ
);
3572 /* Return TRUE for SMIN SMAX UMIN UMAX operators. */
3575 minmax_operator (x
, mode
)
3577 enum machine_mode mode
;
3579 enum rtx_code code
= GET_CODE (x
);
3581 if (GET_MODE (x
) != mode
)
3584 return code
== SMIN
|| code
== SMAX
|| code
== UMIN
|| code
== UMAX
;
3587 /* Return TRUE if this is the condition code register, if we aren't given
3588 a mode, accept any class CCmode register. */
3591 cc_register (x
, mode
)
3593 enum machine_mode mode
;
3595 if (mode
== VOIDmode
)
3597 mode
= GET_MODE (x
);
3599 if (GET_MODE_CLASS (mode
) != MODE_CC
)
3603 if ( GET_MODE (x
) == mode
3604 && GET_CODE (x
) == REG
3605 && REGNO (x
) == CC_REGNUM
)
3611 /* Return TRUE if this is the condition code register, if we aren't given
3612 a mode, accept any class CCmode register which indicates a dominance
3616 dominant_cc_register (x
, mode
)
3618 enum machine_mode mode
;
3620 if (mode
== VOIDmode
)
3622 mode
= GET_MODE (x
);
3624 if (GET_MODE_CLASS (mode
) != MODE_CC
)
3628 if ( mode
!= CC_DNEmode
&& mode
!= CC_DEQmode
3629 && mode
!= CC_DLEmode
&& mode
!= CC_DLTmode
3630 && mode
!= CC_DGEmode
&& mode
!= CC_DGTmode
3631 && mode
!= CC_DLEUmode
&& mode
!= CC_DLTUmode
3632 && mode
!= CC_DGEUmode
&& mode
!= CC_DGTUmode
)
3635 return cc_register (x
, mode
);
3638 /* Return TRUE if X references a SYMBOL_REF. */
3641 symbol_mentioned_p (x
)
3647 if (GET_CODE (x
) == SYMBOL_REF
)
3650 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3652 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3658 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3659 if (symbol_mentioned_p (XVECEXP (x
, i
, j
)))
3662 else if (fmt
[i
] == 'e' && symbol_mentioned_p (XEXP (x
, i
)))
3669 /* Return TRUE if X references a LABEL_REF. */
3672 label_mentioned_p (x
)
3678 if (GET_CODE (x
) == LABEL_REF
)
3681 fmt
= GET_RTX_FORMAT (GET_CODE (x
));
3682 for (i
= GET_RTX_LENGTH (GET_CODE (x
)) - 1; i
>= 0; i
--)
3688 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
3689 if (label_mentioned_p (XVECEXP (x
, i
, j
)))
3692 else if (fmt
[i
] == 'e' && label_mentioned_p (XEXP (x
, i
)))
3703 enum rtx_code code
= GET_CODE (x
);
3707 else if (code
== SMIN
)
3709 else if (code
== UMIN
)
3711 else if (code
== UMAX
)
3717 /* Return 1 if memory locations are adjacent. */
3720 adjacent_mem_locations (a
, b
)
3723 if ((GET_CODE (XEXP (a
, 0)) == REG
3724 || (GET_CODE (XEXP (a
, 0)) == PLUS
3725 && GET_CODE (XEXP (XEXP (a
, 0), 1)) == CONST_INT
))
3726 && (GET_CODE (XEXP (b
, 0)) == REG
3727 || (GET_CODE (XEXP (b
, 0)) == PLUS
3728 && GET_CODE (XEXP (XEXP (b
, 0), 1)) == CONST_INT
)))
3730 int val0
= 0, val1
= 0;
3733 if (GET_CODE (XEXP (a
, 0)) == PLUS
)
3735 reg0
= REGNO (XEXP (XEXP (a
, 0), 0));
3736 val0
= INTVAL (XEXP (XEXP (a
, 0), 1));
3739 reg0
= REGNO (XEXP (a
, 0));
3741 if (GET_CODE (XEXP (b
, 0)) == PLUS
)
3743 reg1
= REGNO (XEXP (XEXP (b
, 0), 0));
3744 val1
= INTVAL (XEXP (XEXP (b
, 0), 1));
3747 reg1
= REGNO (XEXP (b
, 0));
3749 return (reg0
== reg1
) && ((val1
- val0
) == 4 || (val0
- val1
) == 4);
3754 /* Return 1 if OP is a load multiple operation. It is known to be
3755 parallel and the first section will be tested. */
3758 load_multiple_operation (op
, mode
)
3760 enum machine_mode mode ATTRIBUTE_UNUSED
;
3762 HOST_WIDE_INT count
= XVECLEN (op
, 0);
3765 HOST_WIDE_INT i
= 1, base
= 0;
3769 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
3772 /* Check to see if this might be a write-back. */
3773 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
3778 /* Now check it more carefully. */
3779 if (GET_CODE (SET_DEST (elt
)) != REG
3780 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
3781 || REGNO (XEXP (SET_SRC (elt
), 0)) != REGNO (SET_DEST (elt
))
3782 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
3783 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 1) * 4)
3787 /* Perform a quick check so we don't blow up below. */
3789 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
3790 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != REG
3791 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != MEM
)
3794 dest_regno
= REGNO (SET_DEST (XVECEXP (op
, 0, i
- 1)));
3795 src_addr
= XEXP (SET_SRC (XVECEXP (op
, 0, i
- 1)), 0);
3797 for (; i
< count
; i
++)
3799 elt
= XVECEXP (op
, 0, i
);
3801 if (GET_CODE (elt
) != SET
3802 || GET_CODE (SET_DEST (elt
)) != REG
3803 || GET_MODE (SET_DEST (elt
)) != SImode
3804 || REGNO (SET_DEST (elt
)) != (unsigned int)(dest_regno
+ i
- base
)
3805 || GET_CODE (SET_SRC (elt
)) != MEM
3806 || GET_MODE (SET_SRC (elt
)) != SImode
3807 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
3808 || !rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
3809 || GET_CODE (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != CONST_INT
3810 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != (i
- base
) * 4)
3817 /* Return 1 if OP is a store multiple operation. It is known to be
3818 parallel and the first section will be tested. */
3821 store_multiple_operation (op
, mode
)
3823 enum machine_mode mode ATTRIBUTE_UNUSED
;
3825 HOST_WIDE_INT count
= XVECLEN (op
, 0);
3828 HOST_WIDE_INT i
= 1, base
= 0;
3832 || GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
3835 /* Check to see if this might be a write-back. */
3836 if (GET_CODE (SET_SRC (elt
= XVECEXP (op
, 0, 0))) == PLUS
)
3841 /* Now check it more carefully. */
3842 if (GET_CODE (SET_DEST (elt
)) != REG
3843 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != REG
3844 || REGNO (XEXP (SET_SRC (elt
), 0)) != REGNO (SET_DEST (elt
))
3845 || GET_CODE (XEXP (SET_SRC (elt
), 1)) != CONST_INT
3846 || INTVAL (XEXP (SET_SRC (elt
), 1)) != (count
- 1) * 4)
3850 /* Perform a quick check so we don't blow up below. */
3852 || GET_CODE (XVECEXP (op
, 0, i
- 1)) != SET
3853 || GET_CODE (SET_DEST (XVECEXP (op
, 0, i
- 1))) != MEM
3854 || GET_CODE (SET_SRC (XVECEXP (op
, 0, i
- 1))) != REG
)
3857 src_regno
= REGNO (SET_SRC (XVECEXP (op
, 0, i
- 1)));
3858 dest_addr
= XEXP (SET_DEST (XVECEXP (op
, 0, i
- 1)), 0);
3860 for (; i
< count
; i
++)
3862 elt
= XVECEXP (op
, 0, i
);
3864 if (GET_CODE (elt
) != SET
3865 || GET_CODE (SET_SRC (elt
)) != REG
3866 || GET_MODE (SET_SRC (elt
)) != SImode
3867 || REGNO (SET_SRC (elt
)) != (unsigned int)(src_regno
+ i
- base
)
3868 || GET_CODE (SET_DEST (elt
)) != MEM
3869 || GET_MODE (SET_DEST (elt
)) != SImode
3870 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
3871 || !rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_addr
)
3872 || GET_CODE (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != CONST_INT
3873 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != (i
- base
) * 4)
3881 load_multiple_sequence (operands
, nops
, regs
, base
, load_offset
)
3886 HOST_WIDE_INT
* load_offset
;
3888 int unsorted_regs
[4];
3889 HOST_WIDE_INT unsorted_offsets
[4];
3894 /* Can only handle 2, 3, or 4 insns at present,
3895 though could be easily extended if required. */
3896 if (nops
< 2 || nops
> 4)
3899 /* Loop over the operands and check that the memory references are
3900 suitable (ie immediate offsets from the same base register). At
3901 the same time, extract the target register, and the memory
3903 for (i
= 0; i
< nops
; i
++)
3908 /* Convert a subreg of a mem into the mem itself. */
3909 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
3910 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
3912 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
3915 /* Don't reorder volatile memory references; it doesn't seem worth
3916 looking for the case where the order is ok anyway. */
3917 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
3920 offset
= const0_rtx
;
3922 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
3923 || (GET_CODE (reg
) == SUBREG
3924 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
3925 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
3926 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
3928 || (GET_CODE (reg
) == SUBREG
3929 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
3930 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
3935 base_reg
= REGNO (reg
);
3936 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
3937 ? REGNO (operands
[i
])
3938 : REGNO (SUBREG_REG (operands
[i
])));
3943 if (base_reg
!= (int) REGNO (reg
))
3944 /* Not addressed from the same base register. */
3947 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
3948 ? REGNO (operands
[i
])
3949 : REGNO (SUBREG_REG (operands
[i
])));
3950 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
3954 /* If it isn't an integer register, or if it overwrites the
3955 base register but isn't the last insn in the list, then
3956 we can't do this. */
3957 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14
3958 || (i
!= nops
- 1 && unsorted_regs
[i
] == base_reg
))
3961 unsorted_offsets
[i
] = INTVAL (offset
);
3964 /* Not a suitable memory address. */
3968 /* All the useful information has now been extracted from the
3969 operands into unsorted_regs and unsorted_offsets; additionally,
3970 order[0] has been set to the lowest numbered register in the
3971 list. Sort the registers into order, and check that the memory
3972 offsets are ascending and adjacent. */
3974 for (i
= 1; i
< nops
; i
++)
3978 order
[i
] = order
[i
- 1];
3979 for (j
= 0; j
< nops
; j
++)
3980 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
3981 && (order
[i
] == order
[i
- 1]
3982 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
3985 /* Have we found a suitable register? if not, one must be used more
3987 if (order
[i
] == order
[i
- 1])
3990 /* Is the memory address adjacent and ascending? */
3991 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
3999 for (i
= 0; i
< nops
; i
++)
4000 regs
[i
] = unsorted_regs
[order
[i
]];
4002 *load_offset
= unsorted_offsets
[order
[0]];
4005 if (unsorted_offsets
[order
[0]] == 0)
4006 return 1; /* ldmia */
4008 if (unsorted_offsets
[order
[0]] == 4)
4009 return 2; /* ldmib */
4011 if (unsorted_offsets
[order
[nops
- 1]] == 0)
4012 return 3; /* ldmda */
4014 if (unsorted_offsets
[order
[nops
- 1]] == -4)
4015 return 4; /* ldmdb */
4017 /* For ARM8,9 & StrongARM, 2 ldr instructions are faster than an ldm
4018 if the offset isn't small enough. The reason 2 ldrs are faster
4019 is because these ARMs are able to do more than one cache access
4020 in a single cycle. The ARM9 and StrongARM have Harvard caches,
4021 whilst the ARM8 has a double bandwidth cache. This means that
4022 these cores can do both an instruction fetch and a data fetch in
4023 a single cycle, so the trick of calculating the address into a
4024 scratch register (one of the result regs) and then doing a load
4025 multiple actually becomes slower (and no smaller in code size).
4026 That is the transformation
4028 ldr rd1, [rbase + offset]
4029 ldr rd2, [rbase + offset + 4]
4033 add rd1, rbase, offset
4034 ldmia rd1, {rd1, rd2}
4036 produces worse code -- '3 cycles + any stalls on rd2' instead of
4037 '2 cycles + any stalls on rd2'. On ARMs with only one cache
4038 access per cycle, the first sequence could never complete in less
4039 than 6 cycles, whereas the ldm sequence would only take 5 and
4040 would make better use of sequential accesses if not hitting the
4043 We cheat here and test 'arm_ld_sched' which we currently know to
4044 only be true for the ARM8, ARM9 and StrongARM. If this ever
4045 changes, then the test below needs to be reworked. */
4046 if (nops
== 2 && arm_ld_sched
)
4049 /* Can't do it without setting up the offset, only do this if it takes
4050 no more than one insn. */
4051 return (const_ok_for_arm (unsorted_offsets
[order
[0]])
4052 || const_ok_for_arm (-unsorted_offsets
[order
[0]])) ? 5 : 0;
4056 emit_ldm_seq (operands
, nops
)
4062 HOST_WIDE_INT offset
;
4066 switch (load_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
4069 strcpy (buf
, "ldm%?ia\t");
4073 strcpy (buf
, "ldm%?ib\t");
4077 strcpy (buf
, "ldm%?da\t");
4081 strcpy (buf
, "ldm%?db\t");
4086 sprintf (buf
, "add%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
4087 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
4090 sprintf (buf
, "sub%%?\t%s%s, %s%s, #%ld", REGISTER_PREFIX
,
4091 reg_names
[regs
[0]], REGISTER_PREFIX
, reg_names
[base_reg
],
4093 output_asm_insn (buf
, operands
);
4095 strcpy (buf
, "ldm%?ia\t");
4102 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
4103 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
4105 for (i
= 1; i
< nops
; i
++)
4106 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
4107 reg_names
[regs
[i
]]);
4109 strcat (buf
, "}\t%@ phole ldm");
4111 output_asm_insn (buf
, operands
);
4116 store_multiple_sequence (operands
, nops
, regs
, base
, load_offset
)
4121 HOST_WIDE_INT
* load_offset
;
4123 int unsorted_regs
[4];
4124 HOST_WIDE_INT unsorted_offsets
[4];
4129 /* Can only handle 2, 3, or 4 insns at present, though could be easily
4130 extended if required. */
4131 if (nops
< 2 || nops
> 4)
4134 /* Loop over the operands and check that the memory references are
4135 suitable (ie immediate offsets from the same base register). At
4136 the same time, extract the target register, and the memory
4138 for (i
= 0; i
< nops
; i
++)
4143 /* Convert a subreg of a mem into the mem itself. */
4144 if (GET_CODE (operands
[nops
+ i
]) == SUBREG
)
4145 operands
[nops
+ i
] = alter_subreg (operands
+ (nops
+ i
));
4147 if (GET_CODE (operands
[nops
+ i
]) != MEM
)
4150 /* Don't reorder volatile memory references; it doesn't seem worth
4151 looking for the case where the order is ok anyway. */
4152 if (MEM_VOLATILE_P (operands
[nops
+ i
]))
4155 offset
= const0_rtx
;
4157 if ((GET_CODE (reg
= XEXP (operands
[nops
+ i
], 0)) == REG
4158 || (GET_CODE (reg
) == SUBREG
4159 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
4160 || (GET_CODE (XEXP (operands
[nops
+ i
], 0)) == PLUS
4161 && ((GET_CODE (reg
= XEXP (XEXP (operands
[nops
+ i
], 0), 0))
4163 || (GET_CODE (reg
) == SUBREG
4164 && GET_CODE (reg
= SUBREG_REG (reg
)) == REG
))
4165 && (GET_CODE (offset
= XEXP (XEXP (operands
[nops
+ i
], 0), 1))
4170 base_reg
= REGNO (reg
);
4171 unsorted_regs
[0] = (GET_CODE (operands
[i
]) == REG
4172 ? REGNO (operands
[i
])
4173 : REGNO (SUBREG_REG (operands
[i
])));
4178 if (base_reg
!= (int) REGNO (reg
))
4179 /* Not addressed from the same base register. */
4182 unsorted_regs
[i
] = (GET_CODE (operands
[i
]) == REG
4183 ? REGNO (operands
[i
])
4184 : REGNO (SUBREG_REG (operands
[i
])));
4185 if (unsorted_regs
[i
] < unsorted_regs
[order
[0]])
4189 /* If it isn't an integer register, then we can't do this. */
4190 if (unsorted_regs
[i
] < 0 || unsorted_regs
[i
] > 14)
4193 unsorted_offsets
[i
] = INTVAL (offset
);
4196 /* Not a suitable memory address. */
4200 /* All the useful information has now been extracted from the
4201 operands into unsorted_regs and unsorted_offsets; additionally,
4202 order[0] has been set to the lowest numbered register in the
4203 list. Sort the registers into order, and check that the memory
4204 offsets are ascending and adjacent. */
4206 for (i
= 1; i
< nops
; i
++)
4210 order
[i
] = order
[i
- 1];
4211 for (j
= 0; j
< nops
; j
++)
4212 if (unsorted_regs
[j
] > unsorted_regs
[order
[i
- 1]]
4213 && (order
[i
] == order
[i
- 1]
4214 || unsorted_regs
[j
] < unsorted_regs
[order
[i
]]))
4217 /* Have we found a suitable register? if not, one must be used more
4219 if (order
[i
] == order
[i
- 1])
4222 /* Is the memory address adjacent and ascending? */
4223 if (unsorted_offsets
[order
[i
]] != unsorted_offsets
[order
[i
- 1]] + 4)
4231 for (i
= 0; i
< nops
; i
++)
4232 regs
[i
] = unsorted_regs
[order
[i
]];
4234 *load_offset
= unsorted_offsets
[order
[0]];
4237 if (unsorted_offsets
[order
[0]] == 0)
4238 return 1; /* stmia */
4240 if (unsorted_offsets
[order
[0]] == 4)
4241 return 2; /* stmib */
4243 if (unsorted_offsets
[order
[nops
- 1]] == 0)
4244 return 3; /* stmda */
4246 if (unsorted_offsets
[order
[nops
- 1]] == -4)
4247 return 4; /* stmdb */
4253 emit_stm_seq (operands
, nops
)
4259 HOST_WIDE_INT offset
;
4263 switch (store_multiple_sequence (operands
, nops
, regs
, &base_reg
, &offset
))
4266 strcpy (buf
, "stm%?ia\t");
4270 strcpy (buf
, "stm%?ib\t");
4274 strcpy (buf
, "stm%?da\t");
4278 strcpy (buf
, "stm%?db\t");
4285 sprintf (buf
+ strlen (buf
), "%s%s, {%s%s", REGISTER_PREFIX
,
4286 reg_names
[base_reg
], REGISTER_PREFIX
, reg_names
[regs
[0]]);
4288 for (i
= 1; i
< nops
; i
++)
4289 sprintf (buf
+ strlen (buf
), ", %s%s", REGISTER_PREFIX
,
4290 reg_names
[regs
[i
]]);
4292 strcat (buf
, "}\t%@ phole stm");
4294 output_asm_insn (buf
, operands
);
4299 multi_register_push (op
, mode
)
4301 enum machine_mode mode ATTRIBUTE_UNUSED
;
4303 if (GET_CODE (op
) != PARALLEL
4304 || (GET_CODE (XVECEXP (op
, 0, 0)) != SET
)
4305 || (GET_CODE (SET_SRC (XVECEXP (op
, 0, 0))) != UNSPEC
)
4306 || (XINT (SET_SRC (XVECEXP (op
, 0, 0)), 1) != UNSPEC_PUSH_MULT
))
4312 /* Routines for use in generating RTL. */
4315 arm_gen_load_multiple (base_regno
, count
, from
, up
, write_back
, unchanging_p
,
4316 in_struct_p
, scalar_p
)
4328 int sign
= up
? 1 : -1;
4331 /* XScale has load-store double instructions, but they have stricter
4332 alignment requirements than load-store multiple, so we can not
4335 For XScale ldm requires 2 + NREGS cycles to complete and blocks
4336 the pipeline until completion.
4344 An ldr instruction takes 1-3 cycles, but does not block the
4353 Best case ldr will always win. However, the more ldr instructions
4354 we issue, the less likely we are to be able to schedule them well.
4355 Using ldr instructions also increases code size.
4357 As a compromise, we use ldr for counts of 1 or 2 regs, and ldm
4358 for counts of 3 or 4 regs. */
4359 if (arm_is_xscale
&& count
<= 2 && ! optimize_size
)
4365 for (i
= 0; i
< count
; i
++)
4367 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, i
* 4 * sign
));
4368 RTX_UNCHANGING_P (mem
) = unchanging_p
;
4369 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
4370 MEM_SCALAR_P (mem
) = scalar_p
;
4371 emit_move_insn (gen_rtx_REG (SImode
, base_regno
+ i
), mem
);
4375 emit_move_insn (from
, plus_constant (from
, count
* 4 * sign
));
4383 result
= gen_rtx_PARALLEL (VOIDmode
,
4384 rtvec_alloc (count
+ (write_back
? 1 : 0)));
4387 XVECEXP (result
, 0, 0)
4388 = gen_rtx_SET (GET_MODE (from
), from
,
4389 plus_constant (from
, count
* 4 * sign
));
4394 for (j
= 0; i
< count
; i
++, j
++)
4396 mem
= gen_rtx_MEM (SImode
, plus_constant (from
, j
* 4 * sign
));
4397 RTX_UNCHANGING_P (mem
) = unchanging_p
;
4398 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
4399 MEM_SCALAR_P (mem
) = scalar_p
;
4400 XVECEXP (result
, 0, i
)
4401 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, base_regno
+ j
), mem
);
4408 arm_gen_store_multiple (base_regno
, count
, to
, up
, write_back
, unchanging_p
,
4409 in_struct_p
, scalar_p
)
4421 int sign
= up
? 1 : -1;
4424 /* See arm_gen_load_multiple for discussion of
4425 the pros/cons of ldm/stm usage for XScale. */
4426 if (arm_is_xscale
&& count
<= 2 && ! optimize_size
)
4432 for (i
= 0; i
< count
; i
++)
4434 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, i
* 4 * sign
));
4435 RTX_UNCHANGING_P (mem
) = unchanging_p
;
4436 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
4437 MEM_SCALAR_P (mem
) = scalar_p
;
4438 emit_move_insn (mem
, gen_rtx_REG (SImode
, base_regno
+ i
));
4442 emit_move_insn (to
, plus_constant (to
, count
* 4 * sign
));
4450 result
= gen_rtx_PARALLEL (VOIDmode
,
4451 rtvec_alloc (count
+ (write_back
? 1 : 0)));
4454 XVECEXP (result
, 0, 0)
4455 = gen_rtx_SET (GET_MODE (to
), to
,
4456 plus_constant (to
, count
* 4 * sign
));
4461 for (j
= 0; i
< count
; i
++, j
++)
4463 mem
= gen_rtx_MEM (SImode
, plus_constant (to
, j
* 4 * sign
));
4464 RTX_UNCHANGING_P (mem
) = unchanging_p
;
4465 MEM_IN_STRUCT_P (mem
) = in_struct_p
;
4466 MEM_SCALAR_P (mem
) = scalar_p
;
4468 XVECEXP (result
, 0, i
)
4469 = gen_rtx_SET (VOIDmode
, mem
, gen_rtx_REG (SImode
, base_regno
+ j
));
4476 arm_gen_movstrqi (operands
)
4479 HOST_WIDE_INT in_words_to_go
, out_words_to_go
, last_bytes
;
4482 rtx st_src
, st_dst
, fin_src
, fin_dst
;
4483 rtx part_bytes_reg
= NULL
;
4485 int dst_unchanging_p
, dst_in_struct_p
, src_unchanging_p
, src_in_struct_p
;
4486 int dst_scalar_p
, src_scalar_p
;
4488 if (GET_CODE (operands
[2]) != CONST_INT
4489 || GET_CODE (operands
[3]) != CONST_INT
4490 || INTVAL (operands
[2]) > 64
4491 || INTVAL (operands
[3]) & 3)
4494 st_dst
= XEXP (operands
[0], 0);
4495 st_src
= XEXP (operands
[1], 0);
4497 dst_unchanging_p
= RTX_UNCHANGING_P (operands
[0]);
4498 dst_in_struct_p
= MEM_IN_STRUCT_P (operands
[0]);
4499 dst_scalar_p
= MEM_SCALAR_P (operands
[0]);
4500 src_unchanging_p
= RTX_UNCHANGING_P (operands
[1]);
4501 src_in_struct_p
= MEM_IN_STRUCT_P (operands
[1]);
4502 src_scalar_p
= MEM_SCALAR_P (operands
[1]);
4504 fin_dst
= dst
= copy_to_mode_reg (SImode
, st_dst
);
4505 fin_src
= src
= copy_to_mode_reg (SImode
, st_src
);
4507 in_words_to_go
= ARM_NUM_INTS (INTVAL (operands
[2]));
4508 out_words_to_go
= INTVAL (operands
[2]) / 4;
4509 last_bytes
= INTVAL (operands
[2]) & 3;
4511 if (out_words_to_go
!= in_words_to_go
&& ((in_words_to_go
- 1) & 3) != 0)
4512 part_bytes_reg
= gen_rtx_REG (SImode
, (in_words_to_go
- 1) & 3);
4514 for (i
= 0; in_words_to_go
>= 2; i
+=4)
4516 if (in_words_to_go
> 4)
4517 emit_insn (arm_gen_load_multiple (0, 4, src
, TRUE
, TRUE
,
4522 emit_insn (arm_gen_load_multiple (0, in_words_to_go
, src
, TRUE
,
4523 FALSE
, src_unchanging_p
,
4524 src_in_struct_p
, src_scalar_p
));
4526 if (out_words_to_go
)
4528 if (out_words_to_go
> 4)
4529 emit_insn (arm_gen_store_multiple (0, 4, dst
, TRUE
, TRUE
,
4533 else if (out_words_to_go
!= 1)
4534 emit_insn (arm_gen_store_multiple (0, out_words_to_go
,
4543 mem
= gen_rtx_MEM (SImode
, dst
);
4544 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
4545 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
4546 MEM_SCALAR_P (mem
) = dst_scalar_p
;
4547 emit_move_insn (mem
, gen_rtx_REG (SImode
, 0));
4548 if (last_bytes
!= 0)
4549 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (4)));
4553 in_words_to_go
-= in_words_to_go
< 4 ? in_words_to_go
: 4;
4554 out_words_to_go
-= out_words_to_go
< 4 ? out_words_to_go
: 4;
4557 /* OUT_WORDS_TO_GO will be zero here if there are byte stores to do. */
4558 if (out_words_to_go
)
4562 mem
= gen_rtx_MEM (SImode
, src
);
4563 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
4564 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
4565 MEM_SCALAR_P (mem
) = src_scalar_p
;
4566 emit_move_insn (sreg
= gen_reg_rtx (SImode
), mem
);
4567 emit_move_insn (fin_src
= gen_reg_rtx (SImode
), plus_constant (src
, 4));
4569 mem
= gen_rtx_MEM (SImode
, dst
);
4570 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
4571 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
4572 MEM_SCALAR_P (mem
) = dst_scalar_p
;
4573 emit_move_insn (mem
, sreg
);
4574 emit_move_insn (fin_dst
= gen_reg_rtx (SImode
), plus_constant (dst
, 4));
4577 if (in_words_to_go
) /* Sanity check */
4583 if (in_words_to_go
< 0)
4586 mem
= gen_rtx_MEM (SImode
, src
);
4587 RTX_UNCHANGING_P (mem
) = src_unchanging_p
;
4588 MEM_IN_STRUCT_P (mem
) = src_in_struct_p
;
4589 MEM_SCALAR_P (mem
) = src_scalar_p
;
4590 part_bytes_reg
= copy_to_mode_reg (SImode
, mem
);
4593 if (last_bytes
&& part_bytes_reg
== NULL
)
4596 if (BYTES_BIG_ENDIAN
&& last_bytes
)
4598 rtx tmp
= gen_reg_rtx (SImode
);
4600 /* The bytes we want are in the top end of the word. */
4601 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
,
4602 GEN_INT (8 * (4 - last_bytes
))));
4603 part_bytes_reg
= tmp
;
4607 mem
= gen_rtx_MEM (QImode
, plus_constant (dst
, last_bytes
- 1));
4608 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
4609 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
4610 MEM_SCALAR_P (mem
) = dst_scalar_p
;
4611 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
4615 tmp
= gen_reg_rtx (SImode
);
4616 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (8)));
4617 part_bytes_reg
= tmp
;
4626 mem
= gen_rtx_MEM (HImode
, dst
);
4627 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
4628 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
4629 MEM_SCALAR_P (mem
) = dst_scalar_p
;
4630 emit_move_insn (mem
, gen_lowpart (HImode
, part_bytes_reg
));
4634 rtx tmp
= gen_reg_rtx (SImode
);
4636 emit_insn (gen_addsi3 (dst
, dst
, GEN_INT (2)));
4637 emit_insn (gen_lshrsi3 (tmp
, part_bytes_reg
, GEN_INT (16)));
4638 part_bytes_reg
= tmp
;
4644 mem
= gen_rtx_MEM (QImode
, dst
);
4645 RTX_UNCHANGING_P (mem
) = dst_unchanging_p
;
4646 MEM_IN_STRUCT_P (mem
) = dst_in_struct_p
;
4647 MEM_SCALAR_P (mem
) = dst_scalar_p
;
4648 emit_move_insn (mem
, gen_lowpart (QImode
, part_bytes_reg
));
4655 /* Generate a memory reference for a half word, such that it will be loaded
4656 into the top 16 bits of the word. We can assume that the address is
4657 known to be alignable and of the form reg, or plus (reg, const). */
4660 arm_gen_rotated_half_load (memref
)
4663 HOST_WIDE_INT offset
= 0;
4664 rtx base
= XEXP (memref
, 0);
4666 if (GET_CODE (base
) == PLUS
)
4668 offset
= INTVAL (XEXP (base
, 1));
4669 base
= XEXP (base
, 0);
4672 /* If we aren't allowed to generate unaligned addresses, then fail. */
4673 if (TARGET_MMU_TRAPS
4674 && ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 0)))
4677 base
= gen_rtx_MEM (SImode
, plus_constant (base
, offset
& ~2));
4679 if ((BYTES_BIG_ENDIAN
? 1 : 0) ^ ((offset
& 2) == 2))
4682 return gen_rtx_ROTATE (SImode
, base
, GEN_INT (16));
4685 /* Select a dominance comparison mode if possible. We support three forms.
4686 COND_OR == 0 => (X && Y)
4687 COND_OR == 1 => ((! X( || Y)
4688 COND_OR == 2 => (X || Y)
4689 If we are unable to support a dominance comparsison we return CC mode.
4690 This will then fail to match for the RTL expressions that generate this
4693 static enum machine_mode
4694 select_dominance_cc_mode (x
, y
, cond_or
)
4697 HOST_WIDE_INT cond_or
;
4699 enum rtx_code cond1
, cond2
;
4702 /* Currently we will probably get the wrong result if the individual
4703 comparisons are not simple. This also ensures that it is safe to
4704 reverse a comparison if necessary. */
4705 if ((arm_select_cc_mode (cond1
= GET_CODE (x
), XEXP (x
, 0), XEXP (x
, 1))
4707 || (arm_select_cc_mode (cond2
= GET_CODE (y
), XEXP (y
, 0), XEXP (y
, 1))
4711 /* The if_then_else variant of this tests the second condition if the
4712 first passes, but is true if the first fails. Reverse the first
4713 condition to get a true "inclusive-or" expression. */
4715 cond1
= reverse_condition (cond1
);
4717 /* If the comparisons are not equal, and one doesn't dominate the other,
4718 then we can't do this. */
4720 && !comparison_dominates_p (cond1
, cond2
)
4721 && (swapped
= 1, !comparison_dominates_p (cond2
, cond1
)))
4726 enum rtx_code temp
= cond1
;
4734 if (cond2
== EQ
|| !cond_or
)
4739 case LE
: return CC_DLEmode
;
4740 case LEU
: return CC_DLEUmode
;
4741 case GE
: return CC_DGEmode
;
4742 case GEU
: return CC_DGEUmode
;
4749 if (cond2
== LT
|| !cond_or
)
4758 if (cond2
== GT
|| !cond_or
)
4767 if (cond2
== LTU
|| !cond_or
)
4776 if (cond2
== GTU
|| !cond_or
)
4784 /* The remaining cases only occur when both comparisons are the
4809 arm_select_cc_mode (op
, x
, y
)
4814 /* All floating point compares return CCFP if it is an equality
4815 comparison, and CCFPE otherwise. */
4816 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
4843 /* A compare with a shifted operand. Because of canonicalization, the
4844 comparison will have to be swapped when we emit the assembler. */
4845 if (GET_MODE (y
) == SImode
&& GET_CODE (y
) == REG
4846 && (GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
4847 || GET_CODE (x
) == LSHIFTRT
|| GET_CODE (x
) == ROTATE
4848 || GET_CODE (x
) == ROTATERT
))
4851 /* This is a special case that is used by combine to allow a
4852 comparison of a shifted byte load to be split into a zero-extend
4853 followed by a comparison of the shifted integer (only valid for
4854 equalities and unsigned inequalities). */
4855 if (GET_MODE (x
) == SImode
4856 && GET_CODE (x
) == ASHIFT
4857 && GET_CODE (XEXP (x
, 1)) == CONST_INT
&& INTVAL (XEXP (x
, 1)) == 24
4858 && GET_CODE (XEXP (x
, 0)) == SUBREG
4859 && GET_CODE (SUBREG_REG (XEXP (x
, 0))) == MEM
4860 && GET_MODE (SUBREG_REG (XEXP (x
, 0))) == QImode
4861 && (op
== EQ
|| op
== NE
4862 || op
== GEU
|| op
== GTU
|| op
== LTU
|| op
== LEU
)
4863 && GET_CODE (y
) == CONST_INT
)
4866 /* A construct for a conditional compare, if the false arm contains
4867 0, then both conditions must be true, otherwise either condition
4868 must be true. Not all conditions are possible, so CCmode is
4869 returned if it can't be done. */
4870 if (GET_CODE (x
) == IF_THEN_ELSE
4871 && (XEXP (x
, 2) == const0_rtx
4872 || XEXP (x
, 2) == const1_rtx
)
4873 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4874 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
4875 return select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1),
4876 INTVAL (XEXP (x
, 2)));
4878 /* Alternate canonicalizations of the above. These are somewhat cleaner. */
4879 if (GET_CODE (x
) == AND
4880 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4881 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
4882 return select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1), 0);
4884 if (GET_CODE (x
) == IOR
4885 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 0))) == '<'
4886 && GET_RTX_CLASS (GET_CODE (XEXP (x
, 1))) == '<')
4887 return select_dominance_cc_mode (XEXP (x
, 0), XEXP (x
, 1), 2);
4889 /* An operation that sets the condition codes as a side-effect, the
4890 V flag is not set correctly, so we can only use comparisons where
4891 this doesn't matter. (For LT and GE we can use "mi" and "pl"
4893 if (GET_MODE (x
) == SImode
4895 && (op
== EQ
|| op
== NE
|| op
== LT
|| op
== GE
)
4896 && (GET_CODE (x
) == PLUS
|| GET_CODE (x
) == MINUS
4897 || GET_CODE (x
) == AND
|| GET_CODE (x
) == IOR
4898 || GET_CODE (x
) == XOR
|| GET_CODE (x
) == MULT
4899 || GET_CODE (x
) == NOT
|| GET_CODE (x
) == NEG
4900 || GET_CODE (x
) == LSHIFTRT
4901 || GET_CODE (x
) == ASHIFT
|| GET_CODE (x
) == ASHIFTRT
4902 || GET_CODE (x
) == ROTATERT
|| GET_CODE (x
) == ZERO_EXTRACT
))
4905 if (GET_MODE (x
) == QImode
&& (op
== EQ
|| op
== NE
))
4908 if (GET_MODE (x
) == SImode
&& (op
== LTU
|| op
== GEU
)
4909 && GET_CODE (x
) == PLUS
4910 && (rtx_equal_p (XEXP (x
, 0), y
) || rtx_equal_p (XEXP (x
, 1), y
)))
4916 /* X and Y are two things to compare using CODE. Emit the compare insn and
4917 return the rtx for register 0 in the proper mode. FP means this is a
4918 floating point compare: I don't think that it is needed on the arm. */
4921 arm_gen_compare_reg (code
, x
, y
)
4925 enum machine_mode mode
= SELECT_CC_MODE (code
, x
, y
);
4926 rtx cc_reg
= gen_rtx_REG (mode
, CC_REGNUM
);
4928 emit_insn (gen_rtx_SET (VOIDmode
, cc_reg
,
4929 gen_rtx_COMPARE (mode
, x
, y
)));
4934 /* Generate a sequence of insns that will generate the correct return
4935 address mask depending on the physical architecture that the program
4939 arm_gen_return_addr_mask ()
4941 rtx reg
= gen_reg_rtx (Pmode
);
4943 emit_insn (gen_return_addr_mask (reg
));
4948 arm_reload_in_hi (operands
)
4951 rtx ref
= operands
[1];
4953 HOST_WIDE_INT offset
= 0;
4955 if (GET_CODE (ref
) == SUBREG
)
4957 offset
= SUBREG_BYTE (ref
);
4958 ref
= SUBREG_REG (ref
);
4961 if (GET_CODE (ref
) == REG
)
4963 /* We have a pseudo which has been spilt onto the stack; there
4964 are two cases here: the first where there is a simple
4965 stack-slot replacement and a second where the stack-slot is
4966 out of range, or is used as a subreg. */
4967 if (reg_equiv_mem
[REGNO (ref
)])
4969 ref
= reg_equiv_mem
[REGNO (ref
)];
4970 base
= find_replacement (&XEXP (ref
, 0));
4973 /* The slot is out of range, or was dressed up in a SUBREG. */
4974 base
= reg_equiv_address
[REGNO (ref
)];
4977 base
= find_replacement (&XEXP (ref
, 0));
4979 /* Handle the case where the address is too complex to be offset by 1. */
4980 if (GET_CODE (base
) == MINUS
4981 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
4983 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
4985 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
4988 else if (GET_CODE (base
) == PLUS
)
4990 /* The addend must be CONST_INT, or we would have dealt with it above. */
4991 HOST_WIDE_INT hi
, lo
;
4993 offset
+= INTVAL (XEXP (base
, 1));
4994 base
= XEXP (base
, 0);
4996 /* Rework the address into a legal sequence of insns. */
4997 /* Valid range for lo is -4095 -> 4095 */
5000 : -((-offset
) & 0xfff));
5002 /* Corner case, if lo is the max offset then we would be out of range
5003 once we have added the additional 1 below, so bump the msb into the
5004 pre-loading insn(s). */
5008 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
5009 ^ (HOST_WIDE_INT
) 0x80000000)
5010 - (HOST_WIDE_INT
) 0x80000000);
5012 if (hi
+ lo
!= offset
)
5017 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5019 /* Get the base address; addsi3 knows how to handle constants
5020 that require more than one insn. */
5021 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
5027 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
5028 emit_insn (gen_zero_extendqisi2 (scratch
,
5029 gen_rtx_MEM (QImode
,
5030 plus_constant (base
,
5032 emit_insn (gen_zero_extendqisi2 (gen_rtx_SUBREG (SImode
, operands
[0], 0),
5033 gen_rtx_MEM (QImode
,
5034 plus_constant (base
,
5036 if (!BYTES_BIG_ENDIAN
)
5037 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
5038 gen_rtx_IOR (SImode
,
5041 gen_rtx_SUBREG (SImode
, operands
[0], 0),
5045 emit_insn (gen_rtx_SET (VOIDmode
, gen_rtx_SUBREG (SImode
, operands
[0], 0),
5046 gen_rtx_IOR (SImode
,
5047 gen_rtx_ASHIFT (SImode
, scratch
,
5049 gen_rtx_SUBREG (SImode
, operands
[0],
5053 /* Handle storing a half-word to memory during reload by synthesising as two
5054 byte stores. Take care not to clobber the input values until after we
5055 have moved them somewhere safe. This code assumes that if the DImode
5056 scratch in operands[2] overlaps either the input value or output address
5057 in some way, then that value must die in this insn (we absolutely need
5058 two scratch registers for some corner cases). */
5061 arm_reload_out_hi (operands
)
5064 rtx ref
= operands
[0];
5065 rtx outval
= operands
[1];
5067 HOST_WIDE_INT offset
= 0;
5069 if (GET_CODE (ref
) == SUBREG
)
5071 offset
= SUBREG_BYTE (ref
);
5072 ref
= SUBREG_REG (ref
);
5075 if (GET_CODE (ref
) == REG
)
5077 /* We have a pseudo which has been spilt onto the stack; there
5078 are two cases here: the first where there is a simple
5079 stack-slot replacement and a second where the stack-slot is
5080 out of range, or is used as a subreg. */
5081 if (reg_equiv_mem
[REGNO (ref
)])
5083 ref
= reg_equiv_mem
[REGNO (ref
)];
5084 base
= find_replacement (&XEXP (ref
, 0));
5087 /* The slot is out of range, or was dressed up in a SUBREG. */
5088 base
= reg_equiv_address
[REGNO (ref
)];
5091 base
= find_replacement (&XEXP (ref
, 0));
5093 scratch
= gen_rtx_REG (SImode
, REGNO (operands
[2]));
5095 /* Handle the case where the address is too complex to be offset by 1. */
5096 if (GET_CODE (base
) == MINUS
5097 || (GET_CODE (base
) == PLUS
&& GET_CODE (XEXP (base
, 1)) != CONST_INT
))
5099 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5101 /* Be careful not to destroy OUTVAL. */
5102 if (reg_overlap_mentioned_p (base_plus
, outval
))
5104 /* Updating base_plus might destroy outval, see if we can
5105 swap the scratch and base_plus. */
5106 if (!reg_overlap_mentioned_p (scratch
, outval
))
5109 scratch
= base_plus
;
5114 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
5116 /* Be conservative and copy OUTVAL into the scratch now,
5117 this should only be necessary if outval is a subreg
5118 of something larger than a word. */
5119 /* XXX Might this clobber base? I can't see how it can,
5120 since scratch is known to overlap with OUTVAL, and
5121 must be wider than a word. */
5122 emit_insn (gen_movhi (scratch_hi
, outval
));
5123 outval
= scratch_hi
;
5127 emit_insn (gen_rtx_SET (VOIDmode
, base_plus
, base
));
5130 else if (GET_CODE (base
) == PLUS
)
5132 /* The addend must be CONST_INT, or we would have dealt with it above. */
5133 HOST_WIDE_INT hi
, lo
;
5135 offset
+= INTVAL (XEXP (base
, 1));
5136 base
= XEXP (base
, 0);
5138 /* Rework the address into a legal sequence of insns. */
5139 /* Valid range for lo is -4095 -> 4095 */
5142 : -((-offset
) & 0xfff));
5144 /* Corner case, if lo is the max offset then we would be out of range
5145 once we have added the additional 1 below, so bump the msb into the
5146 pre-loading insn(s). */
5150 hi
= ((((offset
- lo
) & (HOST_WIDE_INT
) 0xffffffff)
5151 ^ (HOST_WIDE_INT
) 0x80000000)
5152 - (HOST_WIDE_INT
) 0x80000000);
5154 if (hi
+ lo
!= offset
)
5159 rtx base_plus
= gen_rtx_REG (SImode
, REGNO (operands
[2]) + 1);
5161 /* Be careful not to destroy OUTVAL. */
5162 if (reg_overlap_mentioned_p (base_plus
, outval
))
5164 /* Updating base_plus might destroy outval, see if we
5165 can swap the scratch and base_plus. */
5166 if (!reg_overlap_mentioned_p (scratch
, outval
))
5169 scratch
= base_plus
;
5174 rtx scratch_hi
= gen_rtx_REG (HImode
, REGNO (operands
[2]));
5176 /* Be conservative and copy outval into scratch now,
5177 this should only be necessary if outval is a
5178 subreg of something larger than a word. */
5179 /* XXX Might this clobber base? I can't see how it
5180 can, since scratch is known to overlap with
5182 emit_insn (gen_movhi (scratch_hi
, outval
));
5183 outval
= scratch_hi
;
5187 /* Get the base address; addsi3 knows how to handle constants
5188 that require more than one insn. */
5189 emit_insn (gen_addsi3 (base_plus
, base
, GEN_INT (hi
)));
5195 if (BYTES_BIG_ENDIAN
)
5197 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
5198 plus_constant (base
, offset
+ 1)),
5199 gen_lowpart (QImode
, outval
)));
5200 emit_insn (gen_lshrsi3 (scratch
,
5201 gen_rtx_SUBREG (SImode
, outval
, 0),
5203 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
5204 gen_lowpart (QImode
, scratch
)));
5208 emit_insn (gen_movqi (gen_rtx_MEM (QImode
, plus_constant (base
, offset
)),
5209 gen_lowpart (QImode
, outval
)));
5210 emit_insn (gen_lshrsi3 (scratch
,
5211 gen_rtx_SUBREG (SImode
, outval
, 0),
5213 emit_insn (gen_movqi (gen_rtx_MEM (QImode
,
5214 plus_constant (base
, offset
+ 1)),
5215 gen_lowpart (QImode
, scratch
)));
5219 /* Print a symbolic form of X to the debug file, F. */
5222 arm_print_value (f
, x
)
5226 switch (GET_CODE (x
))
5229 fprintf (f
, HOST_WIDE_INT_PRINT_HEX
, INTVAL (x
));
5233 fprintf (f
, "<0x%lx,0x%lx>", (long)XWINT (x
, 2), (long)XWINT (x
, 3));
5237 fprintf (f
, "\"%s\"", XSTR (x
, 0));
5241 fprintf (f
, "`%s'", XSTR (x
, 0));
5245 fprintf (f
, "L%d", INSN_UID (XEXP (x
, 0)));
5249 arm_print_value (f
, XEXP (x
, 0));
5253 arm_print_value (f
, XEXP (x
, 0));
5255 arm_print_value (f
, XEXP (x
, 1));
5263 fprintf (f
, "????");
5268 /* Routines for manipulation of the constant pool. */
5270 /* Arm instructions cannot load a large constant directly into a
5271 register; they have to come from a pc relative load. The constant
5272 must therefore be placed in the addressable range of the pc
5273 relative load. Depending on the precise pc relative load
5274 instruction the range is somewhere between 256 bytes and 4k. This
5275 means that we often have to dump a constant inside a function, and
5276 generate code to branch around it.
5278 It is important to minimize this, since the branches will slow
5279 things down and make the code larger.
5281 Normally we can hide the table after an existing unconditional
5282 branch so that there is no interruption of the flow, but in the
5283 worst case the code looks like this:
5301 We fix this by performing a scan after scheduling, which notices
5302 which instructions need to have their operands fetched from the
5303 constant table and builds the table.
5305 The algorithm starts by building a table of all the constants that
5306 need fixing up and all the natural barriers in the function (places
5307 where a constant table can be dropped without breaking the flow).
5308 For each fixup we note how far the pc-relative replacement will be
5309 able to reach and the offset of the instruction into the function.
5311 Having built the table we then group the fixes together to form
5312 tables that are as large as possible (subject to addressing
5313 constraints) and emit each table of constants after the last
5314 barrier that is within range of all the instructions in the group.
5315 If a group does not contain a barrier, then we forcibly create one
5316 by inserting a jump instruction into the flow. Once the table has
5317 been inserted, the insns are then modified to reference the
5318 relevant entry in the pool.
5320 Possible enhancements to the algorithm (not implemented) are:
5322 1) For some processors and object formats, there may be benefit in
5323 aligning the pools to the start of cache lines; this alignment
5324 would need to be taken into account when calculating addressability
5327 /* These typedefs are located at the start of this file, so that
5328 they can be used in the prototypes there. This comment is to
5329 remind readers of that fact so that the following structures
5330 can be understood more easily.
5332 typedef struct minipool_node Mnode;
5333 typedef struct minipool_fixup Mfix; */
5335 struct minipool_node
5337 /* Doubly linked chain of entries. */
5340 /* The maximum offset into the code that this entry can be placed. While
5341 pushing fixes for forward references, all entries are sorted in order
5342 of increasing max_address. */
5343 HOST_WIDE_INT max_address
;
5344 /* Similarly for an entry inserted for a backwards ref. */
5345 HOST_WIDE_INT min_address
;
5346 /* The number of fixes referencing this entry. This can become zero
5347 if we "unpush" an entry. In this case we ignore the entry when we
5348 come to emit the code. */
5350 /* The offset from the start of the minipool. */
5351 HOST_WIDE_INT offset
;
5352 /* The value in table. */
5354 /* The mode of value. */
5355 enum machine_mode mode
;
5359 struct minipool_fixup
5363 HOST_WIDE_INT address
;
5365 enum machine_mode mode
;
5369 HOST_WIDE_INT forwards
;
5370 HOST_WIDE_INT backwards
;
5373 /* Fixes less than a word need padding out to a word boundary. */
5374 #define MINIPOOL_FIX_SIZE(mode) \
5375 (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)
5377 static Mnode
* minipool_vector_head
;
5378 static Mnode
* minipool_vector_tail
;
5379 static rtx minipool_vector_label
;
5381 /* The linked list of all minipool fixes required for this function. */
5382 Mfix
* minipool_fix_head
;
5383 Mfix
* minipool_fix_tail
;
5384 /* The fix entry for the current minipool, once it has been placed. */
5385 Mfix
* minipool_barrier
;
5387 /* Determines if INSN is the start of a jump table. Returns the end
5388 of the TABLE or NULL_RTX. */
5391 is_jump_table (insn
)
5396 if (GET_CODE (insn
) == JUMP_INSN
5397 && JUMP_LABEL (insn
) != NULL
5398 && ((table
= next_real_insn (JUMP_LABEL (insn
)))
5399 == next_real_insn (insn
))
5401 && GET_CODE (table
) == JUMP_INSN
5402 && (GET_CODE (PATTERN (table
)) == ADDR_VEC
5403 || GET_CODE (PATTERN (table
)) == ADDR_DIFF_VEC
))
5409 #ifndef JUMP_TABLES_IN_TEXT_SECTION
5410 #define JUMP_TABLES_IN_TEXT_SECTION 0
5413 static HOST_WIDE_INT
5414 get_jump_table_size (insn
)
5417 /* ADDR_VECs only take room if read-only data does into the text
5419 if (JUMP_TABLES_IN_TEXT_SECTION
5420 #if !defined(READONLY_DATA_SECTION) && !defined(READONLY_DATA_SECTION_ASM_OP)
5425 rtx body
= PATTERN (insn
);
5426 int elt
= GET_CODE (body
) == ADDR_DIFF_VEC
? 1 : 0;
5428 return GET_MODE_SIZE (GET_MODE (body
)) * XVECLEN (body
, elt
);
5434 /* Move a minipool fix MP from its current location to before MAX_MP.
5435 If MAX_MP is NULL, then MP doesn't need moving, but the addressing
5436 contrains may need updating. */
5439 move_minipool_fix_forward_ref (mp
, max_mp
, max_address
)
5442 HOST_WIDE_INT max_address
;
5444 /* This should never be true and the code below assumes these are
5451 if (max_address
< mp
->max_address
)
5452 mp
->max_address
= max_address
;
5456 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
5457 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
5459 mp
->max_address
= max_address
;
5461 /* Unlink MP from its current position. Since max_mp is non-null,
5462 mp->prev must be non-null. */
5463 mp
->prev
->next
= mp
->next
;
5464 if (mp
->next
!= NULL
)
5465 mp
->next
->prev
= mp
->prev
;
5467 minipool_vector_tail
= mp
->prev
;
5469 /* Re-insert it before MAX_MP. */
5471 mp
->prev
= max_mp
->prev
;
5474 if (mp
->prev
!= NULL
)
5475 mp
->prev
->next
= mp
;
5477 minipool_vector_head
= mp
;
5480 /* Save the new entry. */
5483 /* Scan over the preceding entries and adjust their addresses as
5485 while (mp
->prev
!= NULL
5486 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
5488 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
5495 /* Add a constant to the minipool for a forward reference. Returns the
5496 node added or NULL if the constant will not fit in this pool. */
5499 add_minipool_forward_ref (fix
)
5502 /* If set, max_mp is the first pool_entry that has a lower
5503 constraint than the one we are trying to add. */
5504 Mnode
* max_mp
= NULL
;
5505 HOST_WIDE_INT max_address
= fix
->address
+ fix
->forwards
;
5508 /* If this fix's address is greater than the address of the first
5509 entry, then we can't put the fix in this pool. We subtract the
5510 size of the current fix to ensure that if the table is fully
5511 packed we still have enough room to insert this value by suffling
5512 the other fixes forwards. */
5513 if (minipool_vector_head
&&
5514 fix
->address
>= minipool_vector_head
->max_address
- fix
->fix_size
)
5517 /* Scan the pool to see if a constant with the same value has
5518 already been added. While we are doing this, also note the
5519 location where we must insert the constant if it doesn't already
5521 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
5523 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
5524 && fix
->mode
== mp
->mode
5525 && (GET_CODE (fix
->value
) != CODE_LABEL
5526 || (CODE_LABEL_NUMBER (fix
->value
)
5527 == CODE_LABEL_NUMBER (mp
->value
)))
5528 && rtx_equal_p (fix
->value
, mp
->value
))
5530 /* More than one fix references this entry. */
5532 return move_minipool_fix_forward_ref (mp
, max_mp
, max_address
);
5535 /* Note the insertion point if necessary. */
5537 && mp
->max_address
> max_address
)
5541 /* The value is not currently in the minipool, so we need to create
5542 a new entry for it. If MAX_MP is NULL, the entry will be put on
5543 the end of the list since the placement is less constrained than
5544 any existing entry. Otherwise, we insert the new fix before
5545 MAX_MP and, if neceesary, adjust the constraints on the other
5547 mp
= xmalloc (sizeof (* mp
));
5548 mp
->fix_size
= fix
->fix_size
;
5549 mp
->mode
= fix
->mode
;
5550 mp
->value
= fix
->value
;
5552 /* Not yet required for a backwards ref. */
5553 mp
->min_address
= -65536;
5557 mp
->max_address
= max_address
;
5559 mp
->prev
= minipool_vector_tail
;
5561 if (mp
->prev
== NULL
)
5563 minipool_vector_head
= mp
;
5564 minipool_vector_label
= gen_label_rtx ();
5567 mp
->prev
->next
= mp
;
5569 minipool_vector_tail
= mp
;
5573 if (max_address
> max_mp
->max_address
- mp
->fix_size
)
5574 mp
->max_address
= max_mp
->max_address
- mp
->fix_size
;
5576 mp
->max_address
= max_address
;
5579 mp
->prev
= max_mp
->prev
;
5581 if (mp
->prev
!= NULL
)
5582 mp
->prev
->next
= mp
;
5584 minipool_vector_head
= mp
;
5587 /* Save the new entry. */
5590 /* Scan over the preceding entries and adjust their addresses as
5592 while (mp
->prev
!= NULL
5593 && mp
->prev
->max_address
> mp
->max_address
- mp
->prev
->fix_size
)
5595 mp
->prev
->max_address
= mp
->max_address
- mp
->prev
->fix_size
;
5603 move_minipool_fix_backward_ref (mp
, min_mp
, min_address
)
5606 HOST_WIDE_INT min_address
;
5608 HOST_WIDE_INT offset
;
5610 /* This should never be true, and the code below assumes these are
5617 if (min_address
> mp
->min_address
)
5618 mp
->min_address
= min_address
;
5622 /* We will adjust this below if it is too loose. */
5623 mp
->min_address
= min_address
;
5625 /* Unlink MP from its current position. Since min_mp is non-null,
5626 mp->next must be non-null. */
5627 mp
->next
->prev
= mp
->prev
;
5628 if (mp
->prev
!= NULL
)
5629 mp
->prev
->next
= mp
->next
;
5631 minipool_vector_head
= mp
->next
;
5633 /* Reinsert it after MIN_MP. */
5635 mp
->next
= min_mp
->next
;
5637 if (mp
->next
!= NULL
)
5638 mp
->next
->prev
= mp
;
5640 minipool_vector_tail
= mp
;
5646 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
5648 mp
->offset
= offset
;
5649 if (mp
->refcount
> 0)
5650 offset
+= mp
->fix_size
;
5652 if (mp
->next
&& mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
5653 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
5659 /* Add a constant to the minipool for a backward reference. Returns the
5660 node added or NULL if the constant will not fit in this pool.
5662 Note that the code for insertion for a backwards reference can be
5663 somewhat confusing because the calculated offsets for each fix do
5664 not take into account the size of the pool (which is still under
5668 add_minipool_backward_ref (fix
)
5671 /* If set, min_mp is the last pool_entry that has a lower constraint
5672 than the one we are trying to add. */
5673 Mnode
* min_mp
= NULL
;
5674 /* This can be negative, since it is only a constraint. */
5675 HOST_WIDE_INT min_address
= fix
->address
- fix
->backwards
;
5678 /* If we can't reach the current pool from this insn, or if we can't
5679 insert this entry at the end of the pool without pushing other
5680 fixes out of range, then we don't try. This ensures that we
5681 can't fail later on. */
5682 if (min_address
>= minipool_barrier
->address
5683 || (minipool_vector_tail
->min_address
+ fix
->fix_size
5684 >= minipool_barrier
->address
))
5687 /* Scan the pool to see if a constant with the same value has
5688 already been added. While we are doing this, also note the
5689 location where we must insert the constant if it doesn't already
5691 for (mp
= minipool_vector_tail
; mp
!= NULL
; mp
= mp
->prev
)
5693 if (GET_CODE (fix
->value
) == GET_CODE (mp
->value
)
5694 && fix
->mode
== mp
->mode
5695 && (GET_CODE (fix
->value
) != CODE_LABEL
5696 || (CODE_LABEL_NUMBER (fix
->value
)
5697 == CODE_LABEL_NUMBER (mp
->value
)))
5698 && rtx_equal_p (fix
->value
, mp
->value
)
5699 /* Check that there is enough slack to move this entry to the
5700 end of the table (this is conservative). */
5702 > (minipool_barrier
->address
5703 + minipool_vector_tail
->offset
5704 + minipool_vector_tail
->fix_size
)))
5707 return move_minipool_fix_backward_ref (mp
, min_mp
, min_address
);
5711 mp
->min_address
+= fix
->fix_size
;
5714 /* Note the insertion point if necessary. */
5715 if (mp
->min_address
< min_address
)
5717 else if (mp
->max_address
5718 < minipool_barrier
->address
+ mp
->offset
+ fix
->fix_size
)
5720 /* Inserting before this entry would push the fix beyond
5721 its maximum address (which can happen if we have
5722 re-located a forwards fix); force the new fix to come
5725 min_address
= mp
->min_address
+ fix
->fix_size
;
5730 /* We need to create a new entry. */
5731 mp
= xmalloc (sizeof (* mp
));
5732 mp
->fix_size
= fix
->fix_size
;
5733 mp
->mode
= fix
->mode
;
5734 mp
->value
= fix
->value
;
5736 mp
->max_address
= minipool_barrier
->address
+ 65536;
5738 mp
->min_address
= min_address
;
5743 mp
->next
= minipool_vector_head
;
5745 if (mp
->next
== NULL
)
5747 minipool_vector_tail
= mp
;
5748 minipool_vector_label
= gen_label_rtx ();
5751 mp
->next
->prev
= mp
;
5753 minipool_vector_head
= mp
;
5757 mp
->next
= min_mp
->next
;
5761 if (mp
->next
!= NULL
)
5762 mp
->next
->prev
= mp
;
5764 minipool_vector_tail
= mp
;
5767 /* Save the new entry. */
5775 /* Scan over the following entries and adjust their offsets. */
5776 while (mp
->next
!= NULL
)
5778 if (mp
->next
->min_address
< mp
->min_address
+ mp
->fix_size
)
5779 mp
->next
->min_address
= mp
->min_address
+ mp
->fix_size
;
5782 mp
->next
->offset
= mp
->offset
+ mp
->fix_size
;
5784 mp
->next
->offset
= mp
->offset
;
5793 assign_minipool_offsets (barrier
)
5796 HOST_WIDE_INT offset
= 0;
5799 minipool_barrier
= barrier
;
5801 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= mp
->next
)
5803 mp
->offset
= offset
;
5805 if (mp
->refcount
> 0)
5806 offset
+= mp
->fix_size
;
5810 /* Output the literal table */
5812 dump_minipool (scan
)
5819 fprintf (rtl_dump_file
,
5820 ";; Emitting minipool after insn %u; address %ld\n",
5821 INSN_UID (scan
), (unsigned long) minipool_barrier
->address
);
5823 scan
= emit_label_after (gen_label_rtx (), scan
);
5824 scan
= emit_insn_after (gen_align_4 (), scan
);
5825 scan
= emit_label_after (minipool_vector_label
, scan
);
5827 for (mp
= minipool_vector_head
; mp
!= NULL
; mp
= nmp
)
5829 if (mp
->refcount
> 0)
5833 fprintf (rtl_dump_file
,
5834 ";; Offset %u, min %ld, max %ld ",
5835 (unsigned) mp
->offset
, (unsigned long) mp
->min_address
,
5836 (unsigned long) mp
->max_address
);
5837 arm_print_value (rtl_dump_file
, mp
->value
);
5838 fputc ('\n', rtl_dump_file
);
5841 switch (mp
->fix_size
)
5843 #ifdef HAVE_consttable_1
5845 scan
= emit_insn_after (gen_consttable_1 (mp
->value
), scan
);
5849 #ifdef HAVE_consttable_2
5851 scan
= emit_insn_after (gen_consttable_2 (mp
->value
), scan
);
5855 #ifdef HAVE_consttable_4
5857 scan
= emit_insn_after (gen_consttable_4 (mp
->value
), scan
);
5861 #ifdef HAVE_consttable_8
5863 scan
= emit_insn_after (gen_consttable_8 (mp
->value
), scan
);
5877 minipool_vector_head
= minipool_vector_tail
= NULL
;
5878 scan
= emit_insn_after (gen_consttable_end (), scan
);
5879 scan
= emit_barrier_after (scan
);
5882 /* Return the cost of forcibly inserting a barrier after INSN. */
5885 arm_barrier_cost (insn
)
5888 /* Basing the location of the pool on the loop depth is preferable,
5889 but at the moment, the basic block information seems to be
5890 corrupt by this stage of the compilation. */
5892 rtx next
= next_nonnote_insn (insn
);
5894 if (next
!= NULL
&& GET_CODE (next
) == CODE_LABEL
)
5897 switch (GET_CODE (insn
))
5900 /* It will always be better to place the table before the label, rather
5909 return base_cost
- 10;
5912 return base_cost
+ 10;
5916 /* Find the best place in the insn stream in the range
5917 (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
5918 Create the barrier by inserting a jump and add a new fix entry for
5922 create_fix_barrier (fix
, max_address
)
5924 HOST_WIDE_INT max_address
;
5926 HOST_WIDE_INT count
= 0;
5928 rtx from
= fix
->insn
;
5929 rtx selected
= from
;
5931 HOST_WIDE_INT selected_address
;
5933 HOST_WIDE_INT max_count
= max_address
- fix
->address
;
5934 rtx label
= gen_label_rtx ();
5936 selected_cost
= arm_barrier_cost (from
);
5937 selected_address
= fix
->address
;
5939 while (from
&& count
< max_count
)
5944 /* This code shouldn't have been called if there was a natural barrier
5946 if (GET_CODE (from
) == BARRIER
)
5949 /* Count the length of this insn. */
5950 count
+= get_attr_length (from
);
5952 /* If there is a jump table, add its length. */
5953 tmp
= is_jump_table (from
);
5956 count
+= get_jump_table_size (tmp
);
5958 /* Jump tables aren't in a basic block, so base the cost on
5959 the dispatch insn. If we select this location, we will
5960 still put the pool after the table. */
5961 new_cost
= arm_barrier_cost (from
);
5963 if (count
< max_count
&& new_cost
<= selected_cost
)
5966 selected_cost
= new_cost
;
5967 selected_address
= fix
->address
+ count
;
5970 /* Continue after the dispatch table. */
5971 from
= NEXT_INSN (tmp
);
5975 new_cost
= arm_barrier_cost (from
);
5977 if (count
< max_count
&& new_cost
<= selected_cost
)
5980 selected_cost
= new_cost
;
5981 selected_address
= fix
->address
+ count
;
5984 from
= NEXT_INSN (from
);
5987 /* Create a new JUMP_INSN that branches around a barrier. */
5988 from
= emit_jump_insn_after (gen_jump (label
), selected
);
5989 JUMP_LABEL (from
) = label
;
5990 barrier
= emit_barrier_after (from
);
5991 emit_label_after (label
, barrier
);
5993 /* Create a minipool barrier entry for the new barrier. */
5994 new_fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* new_fix
));
5995 new_fix
->insn
= barrier
;
5996 new_fix
->address
= selected_address
;
5997 new_fix
->next
= fix
->next
;
5998 fix
->next
= new_fix
;
6003 /* Record that there is a natural barrier in the insn stream at
6006 push_minipool_barrier (insn
, address
)
6008 HOST_WIDE_INT address
;
6010 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
6013 fix
->address
= address
;
6016 if (minipool_fix_head
!= NULL
)
6017 minipool_fix_tail
->next
= fix
;
6019 minipool_fix_head
= fix
;
6021 minipool_fix_tail
= fix
;
6024 /* Record INSN, which will need fixing up to load a value from the
6025 minipool. ADDRESS is the offset of the insn since the start of the
6026 function; LOC is a pointer to the part of the insn which requires
6027 fixing; VALUE is the constant that must be loaded, which is of type
6030 push_minipool_fix (insn
, address
, loc
, mode
, value
)
6032 HOST_WIDE_INT address
;
6034 enum machine_mode mode
;
6037 Mfix
* fix
= (Mfix
*) obstack_alloc (&minipool_obstack
, sizeof (* fix
));
6039 #ifdef AOF_ASSEMBLER
6040 /* PIC symbol refereneces need to be converted into offsets into the
6042 /* XXX This shouldn't be done here. */
6043 if (flag_pic
&& GET_CODE (value
) == SYMBOL_REF
)
6044 value
= aof_pic_entry (value
);
6045 #endif /* AOF_ASSEMBLER */
6048 fix
->address
= address
;
6051 fix
->fix_size
= MINIPOOL_FIX_SIZE (mode
);
6053 fix
->forwards
= get_attr_pool_range (insn
);
6054 fix
->backwards
= get_attr_neg_pool_range (insn
);
6055 fix
->minipool
= NULL
;
6057 /* If an insn doesn't have a range defined for it, then it isn't
6058 expecting to be reworked by this code. Better to abort now than
6059 to generate duff assembly code. */
6060 if (fix
->forwards
== 0 && fix
->backwards
== 0)
6065 fprintf (rtl_dump_file
,
6066 ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
6067 GET_MODE_NAME (mode
),
6068 INSN_UID (insn
), (unsigned long) address
,
6069 -1 * (long)fix
->backwards
, (long)fix
->forwards
);
6070 arm_print_value (rtl_dump_file
, fix
->value
);
6071 fprintf (rtl_dump_file
, "\n");
6074 /* Add it to the chain of fixes. */
6077 if (minipool_fix_head
!= NULL
)
6078 minipool_fix_tail
->next
= fix
;
6080 minipool_fix_head
= fix
;
6082 minipool_fix_tail
= fix
;
6085 /* Scan INSN and note any of its operands that need fixing. */
6088 note_invalid_constants (insn
, address
)
6090 HOST_WIDE_INT address
;
6094 extract_insn (insn
);
6096 if (!constrain_operands (1))
6097 fatal_insn_not_found (insn
);
6099 /* Fill in recog_op_alt with information about the constraints of this
6101 preprocess_constraints ();
6103 for (opno
= 0; opno
< recog_data
.n_operands
; opno
++)
6105 /* Things we need to fix can only occur in inputs. */
6106 if (recog_data
.operand_type
[opno
] != OP_IN
)
6109 /* If this alternative is a memory reference, then any mention
6110 of constants in this alternative is really to fool reload
6111 into allowing us to accept one there. We need to fix them up
6112 now so that we output the right code. */
6113 if (recog_op_alt
[opno
][which_alternative
].memory_ok
)
6115 rtx op
= recog_data
.operand
[opno
];
6117 if (CONSTANT_P (op
))
6118 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
6119 recog_data
.operand_mode
[opno
], op
);
6121 /* RWE: Now we look correctly at the operands for the insn,
6122 this shouldn't be needed any more. */
6123 #ifndef AOF_ASSEMBLER
6124 /* XXX Is this still needed? */
6125 else if (GET_CODE (op
) == UNSPEC
&& XINT (op
, 1) == UNSPEC_PIC_SYM
)
6126 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
6127 recog_data
.operand_mode
[opno
],
6128 XVECEXP (op
, 0, 0));
6131 else if (GET_CODE (op
) == MEM
6132 && GET_CODE (XEXP (op
, 0)) == SYMBOL_REF
6133 && CONSTANT_POOL_ADDRESS_P (XEXP (op
, 0)))
6134 push_minipool_fix (insn
, address
, recog_data
.operand_loc
[opno
],
6135 recog_data
.operand_mode
[opno
],
6136 get_pool_constant (XEXP (op
, 0)));
6146 HOST_WIDE_INT address
= 0;
6149 minipool_fix_head
= minipool_fix_tail
= NULL
;
6151 /* The first insn must always be a note, or the code below won't
6152 scan it properly. */
6153 if (GET_CODE (first
) != NOTE
)
6156 /* Scan all the insns and record the operands that will need fixing. */
6157 for (insn
= next_nonnote_insn (first
); insn
; insn
= next_nonnote_insn (insn
))
6159 if (GET_CODE (insn
) == BARRIER
)
6160 push_minipool_barrier (insn
, address
);
6161 else if (GET_CODE (insn
) == INSN
|| GET_CODE (insn
) == CALL_INSN
6162 || GET_CODE (insn
) == JUMP_INSN
)
6166 note_invalid_constants (insn
, address
);
6167 address
+= get_attr_length (insn
);
6169 /* If the insn is a vector jump, add the size of the table
6170 and skip the table. */
6171 if ((table
= is_jump_table (insn
)) != NULL
)
6173 address
+= get_jump_table_size (table
);
6179 fix
= minipool_fix_head
;
6181 /* Now scan the fixups and perform the required changes. */
6186 Mfix
* last_added_fix
;
6187 Mfix
* last_barrier
= NULL
;
6190 /* Skip any further barriers before the next fix. */
6191 while (fix
&& GET_CODE (fix
->insn
) == BARRIER
)
6194 /* No more fixes. */
6198 last_added_fix
= NULL
;
6200 for (ftmp
= fix
; ftmp
; ftmp
= ftmp
->next
)
6202 if (GET_CODE (ftmp
->insn
) == BARRIER
)
6204 if (ftmp
->address
>= minipool_vector_head
->max_address
)
6207 last_barrier
= ftmp
;
6209 else if ((ftmp
->minipool
= add_minipool_forward_ref (ftmp
)) == NULL
)
6212 last_added_fix
= ftmp
; /* Keep track of the last fix added. */
6215 /* If we found a barrier, drop back to that; any fixes that we
6216 could have reached but come after the barrier will now go in
6217 the next mini-pool. */
6218 if (last_barrier
!= NULL
)
6220 /* Reduce the refcount for those fixes that won't go into this
6222 for (fdel
= last_barrier
->next
;
6223 fdel
&& fdel
!= ftmp
;
6226 fdel
->minipool
->refcount
--;
6227 fdel
->minipool
= NULL
;
6230 ftmp
= last_barrier
;
6234 /* ftmp is first fix that we can't fit into this pool and
6235 there no natural barriers that we could use. Insert a
6236 new barrier in the code somewhere between the previous
6237 fix and this one, and arrange to jump around it. */
6238 HOST_WIDE_INT max_address
;
6240 /* The last item on the list of fixes must be a barrier, so
6241 we can never run off the end of the list of fixes without
6242 last_barrier being set. */
6246 max_address
= minipool_vector_head
->max_address
;
6247 /* Check that there isn't another fix that is in range that
6248 we couldn't fit into this pool because the pool was
6249 already too large: we need to put the pool before such an
6251 if (ftmp
->address
< max_address
)
6252 max_address
= ftmp
->address
;
6254 last_barrier
= create_fix_barrier (last_added_fix
, max_address
);
6257 assign_minipool_offsets (last_barrier
);
6261 if (GET_CODE (ftmp
->insn
) != BARRIER
6262 && ((ftmp
->minipool
= add_minipool_backward_ref (ftmp
))
6269 /* Scan over the fixes we have identified for this pool, fixing them
6270 up and adding the constants to the pool itself. */
6271 for (this_fix
= fix
; this_fix
&& ftmp
!= this_fix
;
6272 this_fix
= this_fix
->next
)
6273 if (GET_CODE (this_fix
->insn
) != BARRIER
)
6276 = plus_constant (gen_rtx_LABEL_REF (VOIDmode
,
6277 minipool_vector_label
),
6278 this_fix
->minipool
->offset
);
6279 *this_fix
->loc
= gen_rtx_MEM (this_fix
->mode
, addr
);
6282 dump_minipool (last_barrier
->insn
);
6286 /* From now on we must synthesize any constants that we can't handle
6287 directly. This can happen if the RTL gets split during final
6288 instruction generation. */
6289 after_arm_reorg
= 1;
6291 /* Free the minipool memory. */
6292 obstack_free (&minipool_obstack
, minipool_startobj
);
6295 /* Routines to output assembly language. */
6297 /* If the rtx is the correct value then return the string of the number.
6298 In this way we can ensure that valid double constants are generated even
6299 when cross compiling. */
6302 fp_immediate_constant (x
)
6308 if (!fpa_consts_inited
)
6311 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
6312 for (i
= 0; i
< 8; i
++)
6313 if (REAL_VALUES_EQUAL (r
, values_fpa
[i
]))
6314 return strings_fpa
[i
];
6319 /* As for fp_immediate_constant, but value is passed directly, not in rtx. */
6322 fp_const_from_val (r
)
6323 REAL_VALUE_TYPE
* r
;
6327 if (!fpa_consts_inited
)
6330 for (i
= 0; i
< 8; i
++)
6331 if (REAL_VALUES_EQUAL (*r
, values_fpa
[i
]))
6332 return strings_fpa
[i
];
6337 /* Output the operands of a LDM/STM instruction to STREAM.
6338 MASK is the ARM register set mask of which only bits 0-15 are important.
6339 REG is the base register, either the frame pointer or the stack pointer,
6340 INSTR is the possibly suffixed load or store instruction. */
6343 print_multi_reg (stream
, instr
, reg
, mask
)
6350 int not_first
= FALSE
;
6352 fputc ('\t', stream
);
6353 asm_fprintf (stream
, instr
, reg
);
6354 fputs (", {", stream
);
6356 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
6357 if (mask
& (1 << i
))
6360 fprintf (stream
, ", ");
6362 asm_fprintf (stream
, "%r", i
);
6366 fprintf (stream
, "}%s\n", TARGET_APCS_32
? "" : "^");
6369 /* Output a 'call' insn. */
6372 output_call (operands
)
6375 /* Handle calls to lr using ip (which may be clobbered in subr anyway). */
6377 if (REGNO (operands
[0]) == LR_REGNUM
)
6379 operands
[0] = gen_rtx_REG (SImode
, IP_REGNUM
);
6380 output_asm_insn ("mov%?\t%0, %|lr", operands
);
6383 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
6385 if (TARGET_INTERWORK
)
6386 output_asm_insn ("bx%?\t%0", operands
);
6388 output_asm_insn ("mov%?\t%|pc, %0", operands
);
6397 int something_changed
= 0;
6399 int code
= GET_CODE (x0
);
6406 if (REGNO (x0
) == LR_REGNUM
)
6408 *x
= gen_rtx_REG (SImode
, IP_REGNUM
);
6413 /* Scan through the sub-elements and change any references there. */
6414 fmt
= GET_RTX_FORMAT (code
);
6416 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
6418 something_changed
|= eliminate_lr2ip (&XEXP (x0
, i
));
6419 else if (fmt
[i
] == 'E')
6420 for (j
= 0; j
< XVECLEN (x0
, i
); j
++)
6421 something_changed
|= eliminate_lr2ip (&XVECEXP (x0
, i
, j
));
6423 return something_changed
;
6427 /* Output a 'call' insn that is a reference in memory. */
6430 output_call_mem (operands
)
6433 operands
[0] = copy_rtx (operands
[0]); /* Be ultra careful. */
6434 /* Handle calls using lr by using ip (which may be clobbered in subr anyway). */
6435 if (eliminate_lr2ip (&operands
[0]))
6436 output_asm_insn ("mov%?\t%|ip, %|lr", operands
);
6438 if (TARGET_INTERWORK
)
6440 output_asm_insn ("ldr%?\t%|ip, %0", operands
);
6441 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
6442 output_asm_insn ("bx%?\t%|ip", operands
);
6446 output_asm_insn ("mov%?\t%|lr, %|pc", operands
);
6447 output_asm_insn ("ldr%?\t%|pc, %0", operands
);
6454 /* Output a move from arm registers to an fpu registers.
6455 OPERANDS[0] is an fpu register.
6456 OPERANDS[1] is the first registers of an arm register pair. */
6459 output_mov_long_double_fpu_from_arm (operands
)
6462 int arm_reg0
= REGNO (operands
[1]);
6465 if (arm_reg0
== IP_REGNUM
)
6468 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
6469 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
6470 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
6472 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1, %2}", ops
);
6473 output_asm_insn ("ldf%?e\t%0, [%|sp], #12", operands
);
6478 /* Output a move from an fpu register to arm registers.
6479 OPERANDS[0] is the first registers of an arm register pair.
6480 OPERANDS[1] is an fpu register. */
6483 output_mov_long_double_arm_from_fpu (operands
)
6486 int arm_reg0
= REGNO (operands
[0]);
6489 if (arm_reg0
== IP_REGNUM
)
6492 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
6493 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
6494 ops
[2] = gen_rtx_REG (SImode
, 2 + arm_reg0
);
6496 output_asm_insn ("stf%?e\t%1, [%|sp, #-12]!", operands
);
6497 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1, %2}", ops
);
6501 /* Output a move from arm registers to arm registers of a long double
6502 OPERANDS[0] is the destination.
6503 OPERANDS[1] is the source. */
6506 output_mov_long_double_arm_from_arm (operands
)
6509 /* We have to be careful here because the two might overlap. */
6510 int dest_start
= REGNO (operands
[0]);
6511 int src_start
= REGNO (operands
[1]);
6515 if (dest_start
< src_start
)
6517 for (i
= 0; i
< 3; i
++)
6519 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
6520 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
6521 output_asm_insn ("mov%?\t%0, %1", ops
);
6526 for (i
= 2; i
>= 0; i
--)
6528 ops
[0] = gen_rtx_REG (SImode
, dest_start
+ i
);
6529 ops
[1] = gen_rtx_REG (SImode
, src_start
+ i
);
6530 output_asm_insn ("mov%?\t%0, %1", ops
);
6538 /* Output a move from arm registers to an fpu registers.
6539 OPERANDS[0] is an fpu register.
6540 OPERANDS[1] is the first registers of an arm register pair. */
6543 output_mov_double_fpu_from_arm (operands
)
6546 int arm_reg0
= REGNO (operands
[1]);
6549 if (arm_reg0
== IP_REGNUM
)
6552 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
6553 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
6554 output_asm_insn ("stm%?fd\t%|sp!, {%0, %1}", ops
);
6555 output_asm_insn ("ldf%?d\t%0, [%|sp], #8", operands
);
6559 /* Output a move from an fpu register to arm registers.
6560 OPERANDS[0] is the first registers of an arm register pair.
6561 OPERANDS[1] is an fpu register. */
6564 output_mov_double_arm_from_fpu (operands
)
6567 int arm_reg0
= REGNO (operands
[0]);
6570 if (arm_reg0
== IP_REGNUM
)
6573 ops
[0] = gen_rtx_REG (SImode
, arm_reg0
);
6574 ops
[1] = gen_rtx_REG (SImode
, 1 + arm_reg0
);
6575 output_asm_insn ("stf%?d\t%1, [%|sp, #-8]!", operands
);
6576 output_asm_insn ("ldm%?fd\t%|sp!, {%0, %1}", ops
);
6580 /* Output a move between double words.
6581 It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM
6582 or MEM<-REG and all MEMs must be offsettable addresses. */
6585 output_move_double (operands
)
6588 enum rtx_code code0
= GET_CODE (operands
[0]);
6589 enum rtx_code code1
= GET_CODE (operands
[1]);
6594 int reg0
= REGNO (operands
[0]);
6596 otherops
[0] = gen_rtx_REG (SImode
, 1 + reg0
);
6600 int reg1
= REGNO (operands
[1]);
6601 if (reg1
== IP_REGNUM
)
6604 /* Ensure the second source is not overwritten. */
6605 if (reg1
== reg0
+ (WORDS_BIG_ENDIAN
? -1 : 1))
6606 output_asm_insn ("mov%?\t%Q0, %Q1\n\tmov%?\t%R0, %R1", operands
);
6608 output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands
);
6610 else if (code1
== CONST_DOUBLE
)
6612 if (GET_MODE (operands
[1]) == DFmode
)
6617 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[1]);
6618 REAL_VALUE_TO_TARGET_DOUBLE (r
, l
);
6619 otherops
[1] = GEN_INT (l
[1]);
6620 operands
[1] = GEN_INT (l
[0]);
6622 else if (GET_MODE (operands
[1]) != VOIDmode
)
6624 else if (WORDS_BIG_ENDIAN
)
6626 otherops
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
6627 operands
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
6631 otherops
[1] = GEN_INT (CONST_DOUBLE_HIGH (operands
[1]));
6632 operands
[1] = GEN_INT (CONST_DOUBLE_LOW (operands
[1]));
6635 output_mov_immediate (operands
);
6636 output_mov_immediate (otherops
);
6638 else if (code1
== CONST_INT
)
6640 #if HOST_BITS_PER_WIDE_INT > 32
6641 /* If HOST_WIDE_INT is more than 32 bits, the intval tells us
6642 what the upper word is. */
6643 if (WORDS_BIG_ENDIAN
)
6645 otherops
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
6646 operands
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
6650 otherops
[1] = GEN_INT (INTVAL (operands
[1]) >> 32);
6651 operands
[1] = GEN_INT (ARM_SIGN_EXTEND (INTVAL (operands
[1])));
6654 /* Sign extend the intval into the high-order word. */
6655 if (WORDS_BIG_ENDIAN
)
6657 otherops
[1] = operands
[1];
6658 operands
[1] = (INTVAL (operands
[1]) < 0
6659 ? constm1_rtx
: const0_rtx
);
6662 otherops
[1] = INTVAL (operands
[1]) < 0 ? constm1_rtx
: const0_rtx
;
6664 output_mov_immediate (otherops
);
6665 output_mov_immediate (operands
);
6667 else if (code1
== MEM
)
6669 switch (GET_CODE (XEXP (operands
[1], 0)))
6672 output_asm_insn ("ldm%?ia\t%m1, %M0", operands
);
6676 abort (); /* Should never happen now. */
6680 output_asm_insn ("ldm%?db\t%m1!, %M0", operands
);
6684 output_asm_insn ("ldm%?ia\t%m1!, %M0", operands
);
6688 abort (); /* Should never happen now. */
6693 output_asm_insn ("adr%?\t%0, %1", operands
);
6694 output_asm_insn ("ldm%?ia\t%0, %M0", operands
);
6698 if (arm_add_operand (XEXP (XEXP (operands
[1], 0), 1),
6699 GET_MODE (XEXP (XEXP (operands
[1], 0), 1))))
6701 otherops
[0] = operands
[0];
6702 otherops
[1] = XEXP (XEXP (operands
[1], 0), 0);
6703 otherops
[2] = XEXP (XEXP (operands
[1], 0), 1);
6705 if (GET_CODE (XEXP (operands
[1], 0)) == PLUS
)
6707 if (GET_CODE (otherops
[2]) == CONST_INT
)
6709 switch (INTVAL (otherops
[2]))
6712 output_asm_insn ("ldm%?db\t%1, %M0", otherops
);
6715 output_asm_insn ("ldm%?da\t%1, %M0", otherops
);
6718 output_asm_insn ("ldm%?ib\t%1, %M0", otherops
);
6722 if (!(const_ok_for_arm (INTVAL (otherops
[2]))))
6723 output_asm_insn ("sub%?\t%0, %1, #%n2", otherops
);
6725 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
6728 output_asm_insn ("add%?\t%0, %1, %2", otherops
);
6731 output_asm_insn ("sub%?\t%0, %1, %2", otherops
);
6733 return "ldm%?ia\t%0, %M0";
6737 otherops
[1] = adjust_address (operands
[1], VOIDmode
, 4);
6738 /* Take care of overlapping base/data reg. */
6739 if (reg_mentioned_p (operands
[0], operands
[1]))
6741 output_asm_insn ("ldr%?\t%0, %1", otherops
);
6742 output_asm_insn ("ldr%?\t%0, %1", operands
);
6746 output_asm_insn ("ldr%?\t%0, %1", operands
);
6747 output_asm_insn ("ldr%?\t%0, %1", otherops
);
6753 abort (); /* Constraints should prevent this. */
6755 else if (code0
== MEM
&& code1
== REG
)
6757 if (REGNO (operands
[1]) == IP_REGNUM
)
6760 switch (GET_CODE (XEXP (operands
[0], 0)))
6763 output_asm_insn ("stm%?ia\t%m0, %M1", operands
);
6767 abort (); /* Should never happen now. */
6771 output_asm_insn ("stm%?db\t%m0!, %M1", operands
);
6775 output_asm_insn ("stm%?ia\t%m0!, %M1", operands
);
6779 abort (); /* Should never happen now. */
6783 if (GET_CODE (XEXP (XEXP (operands
[0], 0), 1)) == CONST_INT
)
6785 switch (INTVAL (XEXP (XEXP (operands
[0], 0), 1)))
6788 output_asm_insn ("stm%?db\t%m0, %M1", operands
);
6792 output_asm_insn ("stm%?da\t%m0, %M1", operands
);
6796 output_asm_insn ("stm%?ib\t%m0, %M1", operands
);
6803 otherops
[0] = adjust_address (operands
[0], VOIDmode
, 4);
6804 otherops
[1] = gen_rtx_REG (SImode
, 1 + REGNO (operands
[1]));
6805 output_asm_insn ("str%?\t%1, %0", operands
);
6806 output_asm_insn ("str%?\t%1, %0", otherops
);
6810 /* Constraints should prevent this. */
6817 /* Output an arbitrary MOV reg, #n.
6818 OPERANDS[0] is a register. OPERANDS[1] is a const_int. */
6821 output_mov_immediate (operands
)
6824 HOST_WIDE_INT n
= INTVAL (operands
[1]);
6826 /* Try to use one MOV. */
6827 if (const_ok_for_arm (n
))
6828 output_asm_insn ("mov%?\t%0, %1", operands
);
6830 /* Try to use one MVN. */
6831 else if (const_ok_for_arm (~n
))
6833 operands
[1] = GEN_INT (~n
);
6834 output_asm_insn ("mvn%?\t%0, %1", operands
);
6841 /* If all else fails, make it out of ORRs or BICs as appropriate. */
6842 for (i
= 0; i
< 32; i
++)
6846 if (n_ones
> 16) /* Shorter to use MVN with BIC in this case. */
6847 output_multi_immediate (operands
, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n
);
6849 output_multi_immediate (operands
, "mov%?\t%0, %1", "orr%?\t%0, %0, %1", 1, n
);
6855 /* Output an ADD r, s, #n where n may be too big for one instruction.
6856 If adding zero to one register, output nothing. */
6859 output_add_immediate (operands
)
6862 HOST_WIDE_INT n
= INTVAL (operands
[2]);
6864 if (n
!= 0 || REGNO (operands
[0]) != REGNO (operands
[1]))
6867 output_multi_immediate (operands
,
6868 "sub%?\t%0, %1, %2", "sub%?\t%0, %0, %2", 2,
6871 output_multi_immediate (operands
,
6872 "add%?\t%0, %1, %2", "add%?\t%0, %0, %2", 2,
6879 /* Output a multiple immediate operation.
6880 OPERANDS is the vector of operands referred to in the output patterns.
6881 INSTR1 is the output pattern to use for the first constant.
6882 INSTR2 is the output pattern to use for subsequent constants.
6883 IMMED_OP is the index of the constant slot in OPERANDS.
6884 N is the constant value. */
6887 output_multi_immediate (operands
, instr1
, instr2
, immed_op
, n
)
6889 const char * instr1
;
6890 const char * instr2
;
6894 #if HOST_BITS_PER_WIDE_INT > 32
6900 /* Quick and easy output. */
6901 operands
[immed_op
] = const0_rtx
;
6902 output_asm_insn (instr1
, operands
);
6907 const char * instr
= instr1
;
6909 /* Note that n is never zero here (which would give no output). */
6910 for (i
= 0; i
< 32; i
+= 2)
6914 operands
[immed_op
] = GEN_INT (n
& (255 << i
));
6915 output_asm_insn (instr
, operands
);
6925 /* Return the appropriate ARM instruction for the operation code.
6926 The returned result should not be overwritten. OP is the rtx of the
6927 operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator
6931 arithmetic_instr (op
, shift_first_arg
)
6933 int shift_first_arg
;
6935 switch (GET_CODE (op
))
6941 return shift_first_arg
? "rsb" : "sub";
6957 /* Ensure valid constant shifts and return the appropriate shift mnemonic
6958 for the operation code. The returned result should not be overwritten.
6959 OP is the rtx code of the shift.
6960 On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant
6964 shift_op (op
, amountp
)
6966 HOST_WIDE_INT
*amountp
;
6969 enum rtx_code code
= GET_CODE (op
);
6971 if (GET_CODE (XEXP (op
, 1)) == REG
|| GET_CODE (XEXP (op
, 1)) == SUBREG
)
6973 else if (GET_CODE (XEXP (op
, 1)) == CONST_INT
)
6974 *amountp
= INTVAL (XEXP (op
, 1));
6997 /* We never have to worry about the amount being other than a
6998 power of 2, since this case can never be reloaded from a reg. */
7000 *amountp
= int_log2 (*amountp
);
7011 /* This is not 100% correct, but follows from the desire to merge
7012 multiplication by a power of 2 with the recognizer for a
7013 shift. >=32 is not a valid shift for "asl", so we must try and
7014 output a shift that produces the correct arithmetical result.
7015 Using lsr #32 is identical except for the fact that the carry bit
7016 is not set correctly if we set the flags; but we never use the
7017 carry bit from such an operation, so we can ignore that. */
7018 if (code
== ROTATERT
)
7019 /* Rotate is just modulo 32. */
7021 else if (*amountp
!= (*amountp
& 31))
7028 /* Shifts of 0 are no-ops. */
7036 /* Obtain the shift from the POWER of two. */
7038 static HOST_WIDE_INT
7040 HOST_WIDE_INT power
;
7042 HOST_WIDE_INT shift
= 0;
7044 while ((((HOST_WIDE_INT
) 1 << shift
) & power
) == 0)
7054 /* Output a .ascii pseudo-op, keeping track of lengths. This is because
7055 /bin/as is horribly restrictive. */
7056 #define MAX_ASCII_LEN 51
7059 output_ascii_pseudo_op (stream
, p
, len
)
7061 const unsigned char * p
;
7067 fputs ("\t.ascii\t\"", stream
);
7069 for (i
= 0; i
< len
; i
++)
7073 if (len_so_far
>= MAX_ASCII_LEN
)
7075 fputs ("\"\n\t.ascii\t\"", stream
);
7082 fputs ("\\t", stream
);
7087 fputs ("\\f", stream
);
7092 fputs ("\\b", stream
);
7097 fputs ("\\r", stream
);
7101 case TARGET_NEWLINE
:
7102 fputs ("\\n", stream
);
7104 if ((c
>= ' ' && c
<= '~')
7106 /* This is a good place for a line break. */
7107 len_so_far
= MAX_ASCII_LEN
;
7114 putc ('\\', stream
);
7119 if (c
>= ' ' && c
<= '~')
7126 fprintf (stream
, "\\%03o", c
);
7133 fputs ("\"\n", stream
);
7136 /* Compute the register sabe mask for registers 0 through 12
7137 inclusive. This code is used by both arm_compute_save_reg_mask
7138 and arm_compute_initial_elimination_offset. */
7140 static unsigned long
7141 arm_compute_save_reg0_reg12_mask ()
7143 unsigned long func_type
= arm_current_func_type ();
7144 unsigned int save_reg_mask
= 0;
7147 if (IS_INTERRUPT (func_type
))
7149 unsigned int max_reg
;
7150 /* Interrupt functions must not corrupt any registers,
7151 even call clobbered ones. If this is a leaf function
7152 we can just examine the registers used by the RTL, but
7153 otherwise we have to assume that whatever function is
7154 called might clobber anything, and so we have to save
7155 all the call-clobbered registers as well. */
7156 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_FIQ
)
7157 /* FIQ handlers have registers r8 - r12 banked, so
7158 we only need to check r0 - r7, Normal ISRs only
7159 bank r14 and r15, so we must check up to r12.
7160 r13 is the stack pointer which is always preserved,
7161 so we do not need to consider it here. */
7166 for (reg
= 0; reg
<= max_reg
; reg
++)
7167 if (regs_ever_live
[reg
]
7168 || (! current_function_is_leaf
&& call_used_regs
[reg
]))
7169 save_reg_mask
|= (1 << reg
);
7173 /* In the normal case we only need to save those registers
7174 which are call saved and which are used by this function. */
7175 for (reg
= 0; reg
<= 10; reg
++)
7176 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
7177 save_reg_mask
|= (1 << reg
);
7179 /* Handle the frame pointer as a special case. */
7180 if (! TARGET_APCS_FRAME
7181 && ! frame_pointer_needed
7182 && regs_ever_live
[HARD_FRAME_POINTER_REGNUM
]
7183 && ! call_used_regs
[HARD_FRAME_POINTER_REGNUM
])
7184 save_reg_mask
|= 1 << HARD_FRAME_POINTER_REGNUM
;
7186 /* If we aren't loading the PIC register,
7187 don't stack it even though it may be live. */
7189 && ! TARGET_SINGLE_PIC_BASE
7190 && regs_ever_live
[PIC_OFFSET_TABLE_REGNUM
])
7191 save_reg_mask
|= 1 << PIC_OFFSET_TABLE_REGNUM
;
7194 return save_reg_mask
;
7197 /* Compute a bit mask of which registers need to be
7198 saved on the stack for the current function. */
7200 static unsigned long
7201 arm_compute_save_reg_mask ()
7203 unsigned int save_reg_mask
= 0;
7204 unsigned long func_type
= arm_current_func_type ();
7206 if (IS_NAKED (func_type
))
7207 /* This should never really happen. */
7210 /* If we are creating a stack frame, then we must save the frame pointer,
7211 IP (which will hold the old stack pointer), LR and the PC. */
7212 if (frame_pointer_needed
)
7214 (1 << ARM_HARD_FRAME_POINTER_REGNUM
)
7219 /* Volatile functions do not return, so there
7220 is no need to save any other registers. */
7221 if (IS_VOLATILE (func_type
))
7222 return save_reg_mask
;
7224 save_reg_mask
|= arm_compute_save_reg0_reg12_mask ();
7226 /* Decide if we need to save the link register.
7227 Interrupt routines have their own banked link register,
7228 so they never need to save it.
7229 Otherwise if we do not use the link register we do not need to save
7230 it. If we are pushing other registers onto the stack however, we
7231 can save an instruction in the epilogue by pushing the link register
7232 now and then popping it back into the PC. This incurs extra memory
7233 accesses though, so we only do it when optimising for size, and only
7234 if we know that we will not need a fancy return sequence. */
7235 if (regs_ever_live
[LR_REGNUM
]
7238 && ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
))
7239 save_reg_mask
|= 1 << LR_REGNUM
;
7241 if (cfun
->machine
->lr_save_eliminated
)
7242 save_reg_mask
&= ~ (1 << LR_REGNUM
);
7244 return save_reg_mask
;
7247 /* Generate a function exit sequence. If REALLY_RETURN is true, then do
7248 everything bar the final return instruction. */
7251 output_return_instruction (operand
, really_return
, reverse
)
7256 char conditional
[10];
7259 unsigned long live_regs_mask
;
7260 unsigned long func_type
;
7262 func_type
= arm_current_func_type ();
7264 if (IS_NAKED (func_type
))
7267 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
7269 /* If this function was declared non-returning, and we have found a tail
7270 call, then we have to trust that the called function won't return. */
7275 /* Otherwise, trap an attempted return by aborting. */
7277 ops
[1] = gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)"
7279 assemble_external_libcall (ops
[1]);
7280 output_asm_insn (reverse
? "bl%D0\t%a1" : "bl%d0\t%a1", ops
);
7286 if (current_function_calls_alloca
&& !really_return
)
7289 sprintf (conditional
, "%%?%%%c0", reverse
? 'D' : 'd');
7291 return_used_this_function
= 1;
7293 live_regs_mask
= arm_compute_save_reg_mask ();
7297 const char * return_reg
;
7299 /* If we do not have any special requirements for function exit
7300 (eg interworking, or ISR) then we can load the return address
7301 directly into the PC. Otherwise we must load it into LR. */
7303 && ! TARGET_INTERWORK
)
7304 return_reg
= reg_names
[PC_REGNUM
];
7306 return_reg
= reg_names
[LR_REGNUM
];
7308 if ((live_regs_mask
& (1 << IP_REGNUM
)) == (1 << IP_REGNUM
))
7309 /* There are two possible reasons for the IP register being saved.
7310 Either a stack frame was created, in which case IP contains the
7311 old stack pointer, or an ISR routine corrupted it. If this in an
7312 ISR routine then just restore IP, otherwise restore IP into SP. */
7313 if (! IS_INTERRUPT (func_type
))
7315 live_regs_mask
&= ~ (1 << IP_REGNUM
);
7316 live_regs_mask
|= (1 << SP_REGNUM
);
7319 /* On some ARM architectures it is faster to use LDR rather than
7320 LDM to load a single register. On other architectures, the
7321 cost is the same. In 26 bit mode, or for exception handlers,
7322 we have to use LDM to load the PC so that the CPSR is also
7324 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
7326 if (live_regs_mask
== (unsigned int)(1 << reg
))
7329 if (reg
<= LAST_ARM_REGNUM
7330 && (reg
!= LR_REGNUM
7332 || (TARGET_APCS_32
&& ! IS_INTERRUPT (func_type
))))
7334 sprintf (instr
, "ldr%s\t%%|%s, [%%|sp], #4", conditional
,
7335 (reg
== LR_REGNUM
) ? return_reg
: reg_names
[reg
]);
7342 /* Generate the load multiple instruction to restore the registers. */
7343 if (frame_pointer_needed
)
7344 sprintf (instr
, "ldm%sea\t%%|fp, {", conditional
);
7345 else if (live_regs_mask
& (1 << SP_REGNUM
))
7346 sprintf (instr
, "ldm%sfd\t%%|sp, {", conditional
);
7348 sprintf (instr
, "ldm%sfd\t%%|sp!, {", conditional
);
7350 p
= instr
+ strlen (instr
);
7352 for (reg
= 0; reg
<= SP_REGNUM
; reg
++)
7353 if (live_regs_mask
& (1 << reg
))
7355 int l
= strlen (reg_names
[reg
]);
7361 memcpy (p
, ", ", 2);
7365 memcpy (p
, "%|", 2);
7366 memcpy (p
+ 2, reg_names
[reg
], l
);
7370 if (live_regs_mask
& (1 << LR_REGNUM
))
7372 int l
= strlen (return_reg
);
7376 memcpy (p
, ", ", 2);
7380 memcpy (p
, "%|", 2);
7381 memcpy (p
+ 2, return_reg
, l
);
7382 strcpy (p
+ 2 + l
, ((TARGET_APCS_32
7383 && !IS_INTERRUPT (func_type
))
7391 output_asm_insn (instr
, & operand
);
7393 /* See if we need to generate an extra instruction to
7394 perform the actual function return. */
7396 && func_type
!= ARM_FT_INTERWORKED
7397 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
7399 /* The return has already been handled
7400 by loading the LR into the PC. */
7407 switch ((int) ARM_FUNC_TYPE (func_type
))
7411 sprintf (instr
, "sub%ss\t%%|pc, %%|lr, #4", conditional
);
7414 case ARM_FT_INTERWORKED
:
7415 sprintf (instr
, "bx%s\t%%|lr", conditional
);
7418 case ARM_FT_EXCEPTION
:
7419 sprintf (instr
, "mov%ss\t%%|pc, %%|lr", conditional
);
7423 /* ARMv5 implementations always provide BX, so interworking
7424 is the default unless APCS-26 is in use. */
7425 if ((insn_flags
& FL_ARCH5
) != 0 && TARGET_APCS_32
)
7426 sprintf (instr
, "bx%s\t%%|lr", conditional
);
7428 sprintf (instr
, "mov%s%s\t%%|pc, %%|lr",
7429 conditional
, TARGET_APCS_32
? "" : "s");
7433 output_asm_insn (instr
, & operand
);
7439 /* Write the function name into the code section, directly preceding
7440 the function prologue.
7442 Code will be output similar to this:
7444 .ascii "arm_poke_function_name", 0
7447 .word 0xff000000 + (t1 - t0)
7448 arm_poke_function_name
7450 stmfd sp!, {fp, ip, lr, pc}
7453 When performing a stack backtrace, code can inspect the value
7454 of 'pc' stored at 'fp' + 0. If the trace function then looks
7455 at location pc - 12 and the top 8 bits are set, then we know
7456 that there is a function name embedded immediately preceding this
7457 location and has length ((pc[-3]) & 0xff000000).
7459 We assume that pc is declared as a pointer to an unsigned long.
7461 It is of no benefit to output the function name if we are assembling
7462 a leaf function. These function types will not contain a stack
7463 backtrace structure, therefore it is not possible to determine the
7467 arm_poke_function_name (stream
, name
)
7471 unsigned long alignlength
;
7472 unsigned long length
;
7475 length
= strlen (name
) + 1;
7476 alignlength
= ROUND_UP (length
);
7478 ASM_OUTPUT_ASCII (stream
, name
, length
);
7479 ASM_OUTPUT_ALIGN (stream
, 2);
7480 x
= GEN_INT ((unsigned HOST_WIDE_INT
) 0xff000000 + alignlength
);
7481 assemble_aligned_integer (UNITS_PER_WORD
, x
);
7484 /* Place some comments into the assembler stream
7485 describing the current function. */
7488 arm_output_function_prologue (f
, frame_size
)
7490 HOST_WIDE_INT frame_size
;
7492 unsigned long func_type
;
7496 thumb_output_function_prologue (f
, frame_size
);
7501 if (arm_ccfsm_state
|| arm_target_insn
)
7504 func_type
= arm_current_func_type ();
7506 switch ((int) ARM_FUNC_TYPE (func_type
))
7511 case ARM_FT_INTERWORKED
:
7512 asm_fprintf (f
, "\t%@ Function supports interworking.\n");
7514 case ARM_FT_EXCEPTION_HANDLER
:
7515 asm_fprintf (f
, "\t%@ C++ Exception Handler.\n");
7518 asm_fprintf (f
, "\t%@ Interrupt Service Routine.\n");
7521 asm_fprintf (f
, "\t%@ Fast Interrupt Service Routine.\n");
7523 case ARM_FT_EXCEPTION
:
7524 asm_fprintf (f
, "\t%@ ARM Exception Handler.\n");
7528 if (IS_NAKED (func_type
))
7529 asm_fprintf (f
, "\t%@ Naked Function: prologue and epilogue provided by programmer.\n");
7531 if (IS_VOLATILE (func_type
))
7532 asm_fprintf (f
, "\t%@ Volatile: function does not return.\n");
7534 if (IS_NESTED (func_type
))
7535 asm_fprintf (f
, "\t%@ Nested: function declared inside another function.\n");
7537 asm_fprintf (f
, "\t%@ args = %d, pretend = %d, frame = %d\n",
7538 current_function_args_size
,
7539 current_function_pretend_args_size
, frame_size
);
7541 asm_fprintf (f
, "\t%@ frame_needed = %d, uses_anonymous_args = %d\n",
7542 frame_pointer_needed
,
7543 cfun
->machine
->uses_anonymous_args
);
7545 if (cfun
->machine
->lr_save_eliminated
)
7546 asm_fprintf (f
, "\t%@ link register save eliminated.\n");
7548 #ifdef AOF_ASSEMBLER
7550 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, PIC_OFFSET_TABLE_REGNUM
);
7553 return_used_this_function
= 0;
7557 arm_output_epilogue (really_return
)
7561 unsigned long saved_regs_mask
;
7562 unsigned long func_type
;
7563 /* Floats_offset is the offset from the "virtual" frame. In an APCS
7564 frame that is $fp + 4 for a non-variadic function. */
7565 int floats_offset
= 0;
7567 int frame_size
= get_frame_size ();
7568 FILE * f
= asm_out_file
;
7569 rtx eh_ofs
= cfun
->machine
->eh_epilogue_sp_ofs
;
7571 /* If we have already generated the return instruction
7572 then it is futile to generate anything else. */
7573 if (use_return_insn (FALSE
) && return_used_this_function
)
7576 func_type
= arm_current_func_type ();
7578 if (IS_NAKED (func_type
))
7579 /* Naked functions don't have epilogues. */
7582 if (IS_VOLATILE (func_type
) && TARGET_ABORT_NORETURN
)
7586 /* A volatile function should never return. Call abort. */
7587 op
= gen_rtx_SYMBOL_REF (Pmode
, NEED_PLT_RELOC
? "abort(PLT)" : "abort");
7588 assemble_external_libcall (op
);
7589 output_asm_insn ("bl\t%a0", &op
);
7594 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
7596 /* If we are throwing an exception, then we really must
7597 be doing a return, so we can't tail-call. */
7600 saved_regs_mask
= arm_compute_save_reg_mask ();
7602 /* XXX We should adjust floats_offset for any anonymous args, and then
7603 re-adjust vfp_offset below to compensate. */
7605 /* Compute how far away the floats will be. */
7606 for (reg
= 0; reg
<= LAST_ARM_REGNUM
; reg
++)
7607 if (saved_regs_mask
& (1 << reg
))
7610 if (frame_pointer_needed
)
7614 if (arm_fpu_arch
== FP_SOFT2
)
7616 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
7617 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
7619 floats_offset
+= 12;
7620 asm_fprintf (f
, "\tldfe\t%r, [%r, #-%d]\n",
7621 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
7626 int start_reg
= LAST_ARM_FP_REGNUM
;
7628 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
7630 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
7632 floats_offset
+= 12;
7634 /* We can't unstack more than four registers at once. */
7635 if (start_reg
- reg
== 3)
7637 asm_fprintf (f
, "\tlfm\t%r, 4, [%r, #-%d]\n",
7638 reg
, FP_REGNUM
, floats_offset
- vfp_offset
);
7639 start_reg
= reg
- 1;
7644 if (reg
!= start_reg
)
7645 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
7646 reg
+ 1, start_reg
- reg
,
7647 FP_REGNUM
, floats_offset
- vfp_offset
);
7648 start_reg
= reg
- 1;
7652 /* Just in case the last register checked also needs unstacking. */
7653 if (reg
!= start_reg
)
7654 asm_fprintf (f
, "\tlfm\t%r, %d, [%r, #-%d]\n",
7655 reg
+ 1, start_reg
- reg
,
7656 FP_REGNUM
, floats_offset
- vfp_offset
);
7659 /* saved_regs_mask should contain the IP, which at the time of stack
7660 frame generation actually contains the old stack pointer. So a
7661 quick way to unwind the stack is just pop the IP register directly
7662 into the stack pointer. */
7663 if ((saved_regs_mask
& (1 << IP_REGNUM
)) == 0)
7665 saved_regs_mask
&= ~ (1 << IP_REGNUM
);
7666 saved_regs_mask
|= (1 << SP_REGNUM
);
7668 /* There are two registers left in saved_regs_mask - LR and PC. We
7669 only need to restore the LR register (the return address), but to
7670 save time we can load it directly into the PC, unless we need a
7671 special function exit sequence, or we are not really returning. */
7672 if (really_return
&& ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
)
7673 /* Delete the LR from the register mask, so that the LR on
7674 the stack is loaded into the PC in the register mask. */
7675 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
7677 saved_regs_mask
&= ~ (1 << PC_REGNUM
);
7679 print_multi_reg (f
, "ldmea\t%r", FP_REGNUM
, saved_regs_mask
);
7681 if (IS_INTERRUPT (func_type
))
7682 /* Interrupt handlers will have pushed the
7683 IP onto the stack, so restore it now. */
7684 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, 1 << IP_REGNUM
);
7688 /* Restore stack pointer if necessary. */
7689 if (frame_size
+ current_function_outgoing_args_size
!= 0)
7691 operands
[0] = operands
[1] = stack_pointer_rtx
;
7692 operands
[2] = GEN_INT (frame_size
7693 + current_function_outgoing_args_size
);
7694 output_add_immediate (operands
);
7697 if (arm_fpu_arch
== FP_SOFT2
)
7699 for (reg
= FIRST_ARM_FP_REGNUM
; reg
<= LAST_ARM_FP_REGNUM
; reg
++)
7700 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
7701 asm_fprintf (f
, "\tldfe\t%r, [%r], #12\n",
7706 int start_reg
= FIRST_ARM_FP_REGNUM
;
7708 for (reg
= FIRST_ARM_FP_REGNUM
; reg
<= LAST_ARM_FP_REGNUM
; reg
++)
7710 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
7712 if (reg
- start_reg
== 3)
7714 asm_fprintf (f
, "\tlfmfd\t%r, 4, [%r]!\n",
7715 start_reg
, SP_REGNUM
);
7716 start_reg
= reg
+ 1;
7721 if (reg
!= start_reg
)
7722 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
7723 start_reg
, reg
- start_reg
,
7726 start_reg
= reg
+ 1;
7730 /* Just in case the last register checked also needs unstacking. */
7731 if (reg
!= start_reg
)
7732 asm_fprintf (f
, "\tlfmfd\t%r, %d, [%r]!\n",
7733 start_reg
, reg
- start_reg
, SP_REGNUM
);
7736 /* If we can, restore the LR into the PC. */
7737 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
7739 && current_function_pretend_args_size
== 0
7740 && saved_regs_mask
& (1 << LR_REGNUM
))
7742 saved_regs_mask
&= ~ (1 << LR_REGNUM
);
7743 saved_regs_mask
|= (1 << PC_REGNUM
);
7746 /* Load the registers off the stack. If we only have one register
7747 to load use the LDR instruction - it is faster. */
7748 if (saved_regs_mask
== (1 << LR_REGNUM
))
7750 /* The exception handler ignores the LR, so we do
7751 not really need to load it off the stack. */
7753 asm_fprintf (f
, "\tadd\t%r, %r, #4\n", SP_REGNUM
, SP_REGNUM
);
7755 asm_fprintf (f
, "\tldr\t%r, [%r], #4\n", LR_REGNUM
, SP_REGNUM
);
7757 else if (saved_regs_mask
)
7759 if (saved_regs_mask
& (1 << SP_REGNUM
))
7760 /* Note - write back to the stack register is not enabled
7761 (ie "ldmfd sp!..."). We know that the stack pointer is
7762 in the list of registers and if we add writeback the
7763 instruction becomes UNPREDICTABLE. */
7764 print_multi_reg (f
, "ldmfd\t%r", SP_REGNUM
, saved_regs_mask
);
7766 print_multi_reg (f
, "ldmfd\t%r!", SP_REGNUM
, saved_regs_mask
);
7769 if (current_function_pretend_args_size
)
7771 /* Unwind the pre-pushed regs. */
7772 operands
[0] = operands
[1] = stack_pointer_rtx
;
7773 operands
[2] = GEN_INT (current_function_pretend_args_size
);
7774 output_add_immediate (operands
);
7779 if (ARM_FUNC_TYPE (func_type
) == ARM_FT_EXCEPTION_HANDLER
)
7780 /* Adjust the stack to remove the exception handler stuff. */
7781 asm_fprintf (f
, "\tadd\t%r, %r, %r\n", SP_REGNUM
, SP_REGNUM
,
7786 || (ARM_FUNC_TYPE (func_type
) == ARM_FT_NORMAL
7787 && current_function_pretend_args_size
== 0
7788 && saved_regs_mask
& (1 << PC_REGNUM
)))
7791 /* Generate the return instruction. */
7792 switch ((int) ARM_FUNC_TYPE (func_type
))
7794 case ARM_FT_EXCEPTION_HANDLER
:
7795 /* Even in 26-bit mode we do a mov (rather than a movs)
7796 because we don't have the PSR bits set in the address. */
7797 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, EXCEPTION_LR_REGNUM
);
7802 asm_fprintf (f
, "\tsubs\t%r, %r, #4\n", PC_REGNUM
, LR_REGNUM
);
7805 case ARM_FT_EXCEPTION
:
7806 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
7809 case ARM_FT_INTERWORKED
:
7810 asm_fprintf (f
, "\tbx\t%r\n", LR_REGNUM
);
7814 if (frame_pointer_needed
)
7815 /* If we used the frame pointer then the return adddress
7816 will have been loaded off the stack directly into the
7817 PC, so there is no need to issue a MOV instruction
7820 else if (current_function_pretend_args_size
== 0
7821 && (saved_regs_mask
& (1 << LR_REGNUM
)))
7822 /* Similarly we may have been able to load LR into the PC
7823 even if we did not create a stack frame. */
7825 else if (TARGET_APCS_32
)
7826 asm_fprintf (f
, "\tmov\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
7828 asm_fprintf (f
, "\tmovs\t%r, %r\n", PC_REGNUM
, LR_REGNUM
);
7836 arm_output_function_epilogue (file
, frame_size
)
7837 FILE *file ATTRIBUTE_UNUSED
;
7838 HOST_WIDE_INT frame_size
;
7842 /* ??? Probably not safe to set this here, since it assumes that a
7843 function will be emitted as assembly immediately after we generate
7844 RTL for it. This does not happen for inline functions. */
7845 return_used_this_function
= 0;
7849 if (use_return_insn (FALSE
)
7850 && return_used_this_function
7851 && (frame_size
+ current_function_outgoing_args_size
) != 0
7852 && !frame_pointer_needed
)
7855 /* Reset the ARM-specific per-function variables. */
7856 after_arm_reorg
= 0;
7860 /* Generate and emit an insn that we will recognize as a push_multi.
7861 Unfortunately, since this insn does not reflect very well the actual
7862 semantics of the operation, we need to annotate the insn for the benefit
7863 of DWARF2 frame unwind information. */
7866 emit_multi_reg_push (mask
)
7874 int dwarf_par_index
;
7877 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
7878 if (mask
& (1 << i
))
7881 if (num_regs
== 0 || num_regs
> 16)
7884 /* We don't record the PC in the dwarf frame information. */
7885 num_dwarf_regs
= num_regs
;
7886 if (mask
& (1 << PC_REGNUM
))
7889 /* For the body of the insn we are going to generate an UNSPEC in
7890 parallel with several USEs. This allows the insn to be recognized
7891 by the push_multi pattern in the arm.md file. The insn looks
7892 something like this:
7895 (set (mem:BLK (pre_dec:BLK (reg:SI sp)))
7896 (unspec:BLK [(reg:SI r4)] UNSPEC_PUSH_MULT))
7897 (use (reg:SI 11 fp))
7898 (use (reg:SI 12 ip))
7899 (use (reg:SI 14 lr))
7900 (use (reg:SI 15 pc))
7903 For the frame note however, we try to be more explicit and actually
7904 show each register being stored into the stack frame, plus a (single)
7905 decrement of the stack pointer. We do it this way in order to be
7906 friendly to the stack unwinding code, which only wants to see a single
7907 stack decrement per instruction. The RTL we generate for the note looks
7908 something like this:
7911 (set (reg:SI sp) (plus:SI (reg:SI sp) (const_int -20)))
7912 (set (mem:SI (reg:SI sp)) (reg:SI r4))
7913 (set (mem:SI (plus:SI (reg:SI sp) (const_int 4))) (reg:SI fp))
7914 (set (mem:SI (plus:SI (reg:SI sp) (const_int 8))) (reg:SI ip))
7915 (set (mem:SI (plus:SI (reg:SI sp) (const_int 12))) (reg:SI lr))
7918 This sequence is used both by the code to support stack unwinding for
7919 exceptions handlers and the code to generate dwarf2 frame debugging. */
7921 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (num_regs
));
7922 dwarf
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (num_dwarf_regs
+ 1));
7923 dwarf_par_index
= 1;
7925 for (i
= 0; i
<= LAST_ARM_REGNUM
; i
++)
7927 if (mask
& (1 << i
))
7929 reg
= gen_rtx_REG (SImode
, i
);
7932 = gen_rtx_SET (VOIDmode
,
7933 gen_rtx_MEM (BLKmode
,
7934 gen_rtx_PRE_DEC (BLKmode
,
7935 stack_pointer_rtx
)),
7936 gen_rtx_UNSPEC (BLKmode
,
7942 tmp
= gen_rtx_SET (VOIDmode
,
7943 gen_rtx_MEM (SImode
, stack_pointer_rtx
),
7945 RTX_FRAME_RELATED_P (tmp
) = 1;
7946 XVECEXP (dwarf
, 0, dwarf_par_index
) = tmp
;
7954 for (j
= 1, i
++; j
< num_regs
; i
++)
7956 if (mask
& (1 << i
))
7958 reg
= gen_rtx_REG (SImode
, i
);
7960 XVECEXP (par
, 0, j
) = gen_rtx_USE (VOIDmode
, reg
);
7964 tmp
= gen_rtx_SET (VOIDmode
,
7965 gen_rtx_MEM (SImode
,
7966 plus_constant (stack_pointer_rtx
,
7969 RTX_FRAME_RELATED_P (tmp
) = 1;
7970 XVECEXP (dwarf
, 0, dwarf_par_index
++) = tmp
;
7977 par
= emit_insn (par
);
7979 tmp
= gen_rtx_SET (SImode
,
7981 gen_rtx_PLUS (SImode
,
7983 GEN_INT (-4 * num_regs
)));
7984 RTX_FRAME_RELATED_P (tmp
) = 1;
7985 XVECEXP (dwarf
, 0, 0) = tmp
;
7987 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
7993 emit_sfm (base_reg
, count
)
8002 par
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
8003 dwarf
= gen_rtx_PARALLEL (VOIDmode
, rtvec_alloc (count
));
8005 reg
= gen_rtx_REG (XFmode
, base_reg
++);
8008 = gen_rtx_SET (VOIDmode
,
8009 gen_rtx_MEM (BLKmode
,
8010 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
8011 gen_rtx_UNSPEC (BLKmode
,
8015 = gen_rtx_SET (VOIDmode
,
8016 gen_rtx_MEM (XFmode
,
8017 gen_rtx_PRE_DEC (BLKmode
, stack_pointer_rtx
)),
8019 RTX_FRAME_RELATED_P (tmp
) = 1;
8020 XVECEXP (dwarf
, 0, count
- 1) = tmp
;
8022 for (i
= 1; i
< count
; i
++)
8024 reg
= gen_rtx_REG (XFmode
, base_reg
++);
8025 XVECEXP (par
, 0, i
) = gen_rtx_USE (VOIDmode
, reg
);
8027 tmp
= gen_rtx_SET (VOIDmode
,
8028 gen_rtx_MEM (XFmode
,
8029 gen_rtx_PRE_DEC (BLKmode
,
8030 stack_pointer_rtx
)),
8032 RTX_FRAME_RELATED_P (tmp
) = 1;
8033 XVECEXP (dwarf
, 0, count
- i
- 1) = tmp
;
8036 par
= emit_insn (par
);
8037 REG_NOTES (par
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
, dwarf
,
8042 /* Compute the distance from register FROM to register TO.
8043 These can be the arg pointer (26), the soft frame pointer (25),
8044 the stack pointer (13) or the hard frame pointer (11).
8045 Typical stack layout looks like this:
8047 old stack pointer -> | |
8050 | | saved arguments for
8051 | | vararg functions
8054 hard FP & arg pointer -> | | \
8062 soft frame pointer -> | | /
8072 current stack pointer -> | | /
8075 For a given function some or all of these stack components
8076 may not be needed, giving rise to the possibility of
8077 eliminating some of the registers.
8079 The values returned by this function must reflect the behavior
8080 of arm_expand_prologue() and arm_compute_save_reg_mask().
8082 The sign of the number returned reflects the direction of stack
8083 growth, so the values are positive for all eliminations except
8084 from the soft frame pointer to the hard frame pointer. */
8087 arm_compute_initial_elimination_offset (from
, to
)
8091 unsigned int local_vars
= (get_frame_size () + 3) & ~3;
8092 unsigned int outgoing_args
= current_function_outgoing_args_size
;
8093 unsigned int stack_frame
;
8094 unsigned int call_saved_registers
;
8095 unsigned long func_type
;
8097 func_type
= arm_current_func_type ();
8099 /* Volatile functions never return, so there is
8100 no need to save call saved registers. */
8101 call_saved_registers
= 0;
8102 if (! IS_VOLATILE (func_type
))
8104 unsigned int reg_mask
;
8107 /* Make sure that we compute which registers will be saved
8108 on the stack using the same algorithm that is used by
8109 arm_compute_save_reg_mask(). */
8110 reg_mask
= arm_compute_save_reg0_reg12_mask ();
8112 /* Now count the number of bits set in save_reg_mask.
8113 For each set bit we need 4 bytes of stack space. */
8116 call_saved_registers
+= 4;
8117 reg_mask
= reg_mask
& ~ (reg_mask
& - reg_mask
);
8120 if (regs_ever_live
[LR_REGNUM
]
8121 /* If a stack frame is going to be created, the LR will
8122 be saved as part of that, so we do not need to allow
8124 && ! frame_pointer_needed
)
8125 call_saved_registers
+= 4;
8127 /* If the hard floating point registers are going to be
8128 used then they must be saved on the stack as well.
8129 Each register occupies 12 bytes of stack space. */
8130 for (reg
= FIRST_ARM_FP_REGNUM
; reg
<= LAST_ARM_FP_REGNUM
; reg
++)
8131 if (regs_ever_live
[reg
] && ! call_used_regs
[reg
])
8132 call_saved_registers
+= 12;
8135 /* The stack frame contains 4 registers - the old frame pointer,
8136 the old stack pointer, the return address and PC of the start
8138 stack_frame
= frame_pointer_needed
? 16 : 0;
8140 /* OK, now we have enough information to compute the distances.
8141 There must be an entry in these switch tables for each pair
8142 of registers in ELIMINABLE_REGS, even if some of the entries
8143 seem to be redundant or useless. */
8146 case ARG_POINTER_REGNUM
:
8149 case THUMB_HARD_FRAME_POINTER_REGNUM
:
8152 case FRAME_POINTER_REGNUM
:
8153 /* This is the reverse of the soft frame pointer
8154 to hard frame pointer elimination below. */
8155 if (call_saved_registers
== 0 && stack_frame
== 0)
8157 return (call_saved_registers
+ stack_frame
- 4);
8159 case ARM_HARD_FRAME_POINTER_REGNUM
:
8160 /* If there is no stack frame then the hard
8161 frame pointer and the arg pointer coincide. */
8162 if (stack_frame
== 0 && call_saved_registers
!= 0)
8164 /* FIXME: Not sure about this. Maybe we should always return 0 ? */
8165 return (frame_pointer_needed
8166 && current_function_needs_context
8167 && ! cfun
->machine
->uses_anonymous_args
) ? 4 : 0;
8169 case STACK_POINTER_REGNUM
:
8170 /* If nothing has been pushed on the stack at all
8171 then this will return -4. This *is* correct! */
8172 return call_saved_registers
+ stack_frame
+ local_vars
+ outgoing_args
- 4;
8179 case FRAME_POINTER_REGNUM
:
8182 case THUMB_HARD_FRAME_POINTER_REGNUM
:
8185 case ARM_HARD_FRAME_POINTER_REGNUM
:
8186 /* The hard frame pointer points to the top entry in the
8187 stack frame. The soft frame pointer to the bottom entry
8188 in the stack frame. If there is no stack frame at all,
8189 then they are identical. */
8190 if (call_saved_registers
== 0 && stack_frame
== 0)
8192 return - (call_saved_registers
+ stack_frame
- 4);
8194 case STACK_POINTER_REGNUM
:
8195 return local_vars
+ outgoing_args
;
8203 /* You cannot eliminate from the stack pointer.
8204 In theory you could eliminate from the hard frame
8205 pointer to the stack pointer, but this will never
8206 happen, since if a stack frame is not needed the
8207 hard frame pointer will never be used. */
8212 /* Generate the prologue instructions for entry into an ARM function. */
8215 arm_expand_prologue ()
8221 unsigned long live_regs_mask
;
8222 unsigned long func_type
;
8224 int saved_pretend_args
= 0;
8225 unsigned int args_to_push
;
8227 func_type
= arm_current_func_type ();
8229 /* Naked functions don't have prologues. */
8230 if (IS_NAKED (func_type
))
8233 /* Make a copy of c_f_p_a_s as we may need to modify it locally. */
8234 args_to_push
= current_function_pretend_args_size
;
8236 /* Compute which register we will have to save onto the stack. */
8237 live_regs_mask
= arm_compute_save_reg_mask ();
8239 ip_rtx
= gen_rtx_REG (SImode
, IP_REGNUM
);
8241 if (frame_pointer_needed
)
8243 if (IS_INTERRUPT (func_type
))
8245 /* Interrupt functions must not corrupt any registers.
8246 Creating a frame pointer however, corrupts the IP
8247 register, so we must push it first. */
8248 insn
= emit_multi_reg_push (1 << IP_REGNUM
);
8250 /* Do not set RTX_FRAME_RELATED_P on this insn.
8251 The dwarf stack unwinding code only wants to see one
8252 stack decrement per function, and this is not it. If
8253 this instruction is labeled as being part of the frame
8254 creation sequence then dwarf2out_frame_debug_expr will
8255 abort when it encounters the assignment of IP to FP
8256 later on, since the use of SP here establishes SP as
8257 the CFA register and not IP.
8259 Anyway this instruction is not really part of the stack
8260 frame creation although it is part of the prologue. */
8262 else if (IS_NESTED (func_type
))
8264 /* The Static chain register is the same as the IP register
8265 used as a scratch register during stack frame creation.
8266 To get around this need to find somewhere to store IP
8267 whilst the frame is being created. We try the following
8270 1. The last argument register.
8271 2. A slot on the stack above the frame. (This only
8272 works if the function is not a varargs function).
8273 3. Register r3, after pushing the argument registers
8276 Note - we only need to tell the dwarf2 backend about the SP
8277 adjustment in the second variant; the static chain register
8278 doesn't need to be unwound, as it doesn't contain a value
8279 inherited from the caller. */
8281 if (regs_ever_live
[3] == 0)
8283 insn
= gen_rtx_REG (SImode
, 3);
8284 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
8285 insn
= emit_insn (insn
);
8287 else if (args_to_push
== 0)
8290 insn
= gen_rtx_PRE_DEC (SImode
, stack_pointer_rtx
);
8291 insn
= gen_rtx_MEM (SImode
, insn
);
8292 insn
= gen_rtx_SET (VOIDmode
, insn
, ip_rtx
);
8293 insn
= emit_insn (insn
);
8297 /* Just tell the dwarf backend that we adjusted SP. */
8298 dwarf
= gen_rtx_SET (VOIDmode
, stack_pointer_rtx
,
8299 gen_rtx_PLUS (SImode
, stack_pointer_rtx
,
8300 GEN_INT (-fp_offset
)));
8301 RTX_FRAME_RELATED_P (insn
) = 1;
8302 REG_NOTES (insn
) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
8303 dwarf
, REG_NOTES (insn
));
8307 /* Store the args on the stack. */
8308 if (cfun
->machine
->uses_anonymous_args
)
8309 insn
= emit_multi_reg_push
8310 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
8313 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
8314 GEN_INT (- args_to_push
)));
8316 RTX_FRAME_RELATED_P (insn
) = 1;
8318 saved_pretend_args
= 1;
8319 fp_offset
= args_to_push
;
8322 /* Now reuse r3 to preserve IP. */
8323 insn
= gen_rtx_REG (SImode
, 3);
8324 insn
= gen_rtx_SET (SImode
, insn
, ip_rtx
);
8325 (void) emit_insn (insn
);
8331 insn
= gen_rtx_PLUS (SImode
, stack_pointer_rtx
, GEN_INT (fp_offset
));
8332 insn
= gen_rtx_SET (SImode
, ip_rtx
, insn
);
8335 insn
= gen_movsi (ip_rtx
, stack_pointer_rtx
);
8337 insn
= emit_insn (insn
);
8338 RTX_FRAME_RELATED_P (insn
) = 1;
8343 /* Push the argument registers, or reserve space for them. */
8344 if (cfun
->machine
->uses_anonymous_args
)
8345 insn
= emit_multi_reg_push
8346 ((0xf0 >> (args_to_push
/ 4)) & 0xf);
8349 (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
8350 GEN_INT (- args_to_push
)));
8351 RTX_FRAME_RELATED_P (insn
) = 1;
8354 /* If this is an interrupt service routine, and the link register is
8355 going to be pushed, subtracting four now will mean that the
8356 function return can be done with a single instruction. */
8357 if ((func_type
== ARM_FT_ISR
|| func_type
== ARM_FT_FIQ
)
8358 && (live_regs_mask
& (1 << LR_REGNUM
)) != 0)
8360 emit_insn (gen_rtx_SET (SImode
,
8361 gen_rtx_REG (SImode
, LR_REGNUM
),
8362 gen_rtx_PLUS (SImode
,
8363 gen_rtx_REG (SImode
, LR_REGNUM
),
8369 insn
= emit_multi_reg_push (live_regs_mask
);
8370 RTX_FRAME_RELATED_P (insn
) = 1;
8373 if (! IS_VOLATILE (func_type
))
8375 /* Save any floating point call-saved registers used by this function. */
8376 if (arm_fpu_arch
== FP_SOFT2
)
8378 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
8379 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8381 insn
= gen_rtx_PRE_DEC (XFmode
, stack_pointer_rtx
);
8382 insn
= gen_rtx_MEM (XFmode
, insn
);
8383 insn
= emit_insn (gen_rtx_SET (VOIDmode
, insn
,
8384 gen_rtx_REG (XFmode
, reg
)));
8385 RTX_FRAME_RELATED_P (insn
) = 1;
8390 int start_reg
= LAST_ARM_FP_REGNUM
;
8392 for (reg
= LAST_ARM_FP_REGNUM
; reg
>= FIRST_ARM_FP_REGNUM
; reg
--)
8394 if (regs_ever_live
[reg
] && !call_used_regs
[reg
])
8396 if (start_reg
- reg
== 3)
8398 insn
= emit_sfm (reg
, 4);
8399 RTX_FRAME_RELATED_P (insn
) = 1;
8400 start_reg
= reg
- 1;
8405 if (start_reg
!= reg
)
8407 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
8408 RTX_FRAME_RELATED_P (insn
) = 1;
8410 start_reg
= reg
- 1;
8414 if (start_reg
!= reg
)
8416 insn
= emit_sfm (reg
+ 1, start_reg
- reg
);
8417 RTX_FRAME_RELATED_P (insn
) = 1;
8422 if (frame_pointer_needed
)
8424 /* Create the new frame pointer. */
8425 insn
= GEN_INT (-(4 + args_to_push
+ fp_offset
));
8426 insn
= emit_insn (gen_addsi3 (hard_frame_pointer_rtx
, ip_rtx
, insn
));
8427 RTX_FRAME_RELATED_P (insn
) = 1;
8429 if (IS_NESTED (func_type
))
8431 /* Recover the static chain register. */
8432 if (regs_ever_live
[3] == 0
8433 || saved_pretend_args
)
8434 insn
= gen_rtx_REG (SImode
, 3);
8435 else /* if (current_function_pretend_args_size == 0) */
8437 insn
= gen_rtx_PLUS (SImode
, hard_frame_pointer_rtx
, GEN_INT (4));
8438 insn
= gen_rtx_MEM (SImode
, insn
);
8441 emit_insn (gen_rtx_SET (SImode
, ip_rtx
, insn
));
8442 /* Add a USE to stop propagate_one_insn() from barfing. */
8443 emit_insn (gen_prologue_use (ip_rtx
));
8447 amount
= GEN_INT (-(get_frame_size ()
8448 + current_function_outgoing_args_size
));
8450 if (amount
!= const0_rtx
)
8452 /* This add can produce multiple insns for a large constant, so we
8453 need to get tricky. */
8454 rtx last
= get_last_insn ();
8455 insn
= emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
8459 last
= last
? NEXT_INSN (last
) : get_insns ();
8460 RTX_FRAME_RELATED_P (last
) = 1;
8462 while (last
!= insn
);
8464 /* If the frame pointer is needed, emit a special barrier that
8465 will prevent the scheduler from moving stores to the frame
8466 before the stack adjustment. */
8467 if (frame_pointer_needed
)
8468 insn
= emit_insn (gen_stack_tie (stack_pointer_rtx
,
8469 hard_frame_pointer_rtx
));
8472 /* If we are profiling, make sure no instructions are scheduled before
8473 the call to mcount. Similarly if the user has requested no
8474 scheduling in the prolog. */
8475 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
8476 emit_insn (gen_blockage ());
8478 /* If the link register is being kept alive, with the return address in it,
8479 then make sure that it does not get reused by the ce2 pass. */
8480 if ((live_regs_mask
& (1 << LR_REGNUM
)) == 0)
8482 emit_insn (gen_prologue_use (gen_rtx_REG (SImode
, LR_REGNUM
)));
8483 cfun
->machine
->lr_save_eliminated
= 1;
8487 /* If CODE is 'd', then the X is a condition operand and the instruction
8488 should only be executed if the condition is true.
8489 if CODE is 'D', then the X is a condition operand and the instruction
8490 should only be executed if the condition is false: however, if the mode
8491 of the comparison is CCFPEmode, then always execute the instruction -- we
8492 do this because in these circumstances !GE does not necessarily imply LT;
8493 in these cases the instruction pattern will take care to make sure that
8494 an instruction containing %d will follow, thereby undoing the effects of
8495 doing this instruction unconditionally.
8496 If CODE is 'N' then X is a floating point operand that must be negated
8498 If CODE is 'B' then output a bitwise inverted value of X (a const int).
8499 If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */
8502 arm_print_operand (stream
, x
, code
)
8510 fputs (ASM_COMMENT_START
, stream
);
8514 fputs (user_label_prefix
, stream
);
8518 fputs (REGISTER_PREFIX
, stream
);
8522 if (arm_ccfsm_state
== 3 || arm_ccfsm_state
== 4)
8524 if (TARGET_THUMB
|| current_insn_predicate
!= NULL
)
8527 fputs (arm_condition_codes
[arm_current_cc
], stream
);
8529 else if (current_insn_predicate
)
8531 enum arm_cond_code code
;
8536 code
= get_arm_condition_code (current_insn_predicate
);
8537 fputs (arm_condition_codes
[code
], stream
);
8544 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
8545 r
= REAL_VALUE_NEGATE (r
);
8546 fprintf (stream
, "%s", fp_const_from_val (&r
));
8551 if (GET_CODE (x
) == CONST_INT
)
8554 val
= ARM_SIGN_EXTEND (~INTVAL (x
));
8555 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
8560 output_addr_const (stream
, x
);
8565 fprintf (stream
, "%s", arithmetic_instr (x
, 1));
8569 fprintf (stream
, "%s", arithmetic_instr (x
, 0));
8575 const char * shift
= shift_op (x
, &val
);
8579 fprintf (stream
, ", %s ", shift_op (x
, &val
));
8581 arm_print_operand (stream
, XEXP (x
, 1), 0);
8584 fputc ('#', stream
);
8585 fprintf (stream
, HOST_WIDE_INT_PRINT_DEC
, val
);
8591 /* An explanation of the 'Q', 'R' and 'H' register operands:
8593 In a pair of registers containing a DI or DF value the 'Q'
8594 operand returns the register number of the register containing
8595 the least signficant part of the value. The 'R' operand returns
8596 the register number of the register containing the most
8597 significant part of the value.
8599 The 'H' operand returns the higher of the two register numbers.
8600 On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the
8601 same as the 'Q' operand, since the most signficant part of the
8602 value is held in the lower number register. The reverse is true
8603 on systems where WORDS_BIG_ENDIAN is false.
8605 The purpose of these operands is to distinguish between cases
8606 where the endian-ness of the values is important (for example
8607 when they are added together), and cases where the endian-ness
8608 is irrelevant, but the order of register operations is important.
8609 For example when loading a value from memory into a register
8610 pair, the endian-ness does not matter. Provided that the value
8611 from the lower memory address is put into the lower numbered
8612 register, and the value from the higher address is put into the
8613 higher numbered register, the load will work regardless of whether
8614 the value being loaded is big-wordian or little-wordian. The
8615 order of the two register loads can matter however, if the address
8616 of the memory location is actually held in one of the registers
8617 being overwritten by the load. */
8619 if (REGNO (x
) > LAST_ARM_REGNUM
)
8621 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 1 : 0));
8625 if (REGNO (x
) > LAST_ARM_REGNUM
)
8627 asm_fprintf (stream
, "%r", REGNO (x
) + (WORDS_BIG_ENDIAN
? 0 : 1));
8631 if (REGNO (x
) > LAST_ARM_REGNUM
)
8633 asm_fprintf (stream
, "%r", REGNO (x
) + 1);
8637 asm_fprintf (stream
, "%r",
8638 GET_CODE (XEXP (x
, 0)) == REG
8639 ? REGNO (XEXP (x
, 0)) : REGNO (XEXP (XEXP (x
, 0), 0)));
8643 asm_fprintf (stream
, "{%r-%r}",
8645 REGNO (x
) + ARM_NUM_REGS (GET_MODE (x
)) - 1);
8649 /* CONST_TRUE_RTX means always -- that's the default. */
8650 if (x
== const_true_rtx
)
8654 fputs (arm_condition_codes
[get_arm_condition_code (x
)],
8657 fputs (thumb_condition_code (x
, 0), stream
);
8661 /* CONST_TRUE_RTX means not always -- ie never. We shouldn't ever
8663 if (x
== const_true_rtx
)
8667 fputs (arm_condition_codes
[ARM_INVERSE_CONDITION_CODE
8668 (get_arm_condition_code (x
))],
8671 fputs (thumb_condition_code (x
, 1), stream
);
8678 if (GET_CODE (x
) == REG
)
8679 asm_fprintf (stream
, "%r", REGNO (x
));
8680 else if (GET_CODE (x
) == MEM
)
8682 output_memory_reference_mode
= GET_MODE (x
);
8683 output_address (XEXP (x
, 0));
8685 else if (GET_CODE (x
) == CONST_DOUBLE
)
8686 fprintf (stream
, "#%s", fp_immediate_constant (x
));
8687 else if (GET_CODE (x
) == NEG
)
8688 abort (); /* This should never happen now. */
8691 fputc ('#', stream
);
8692 output_addr_const (stream
, x
);
8697 #ifndef AOF_ASSEMBLER
8698 /* Target hook for assembling integer objects. The ARM version needs to
8699 handle word-sized values specially. */
8702 arm_assemble_integer (x
, size
, aligned_p
)
8707 if (size
== UNITS_PER_WORD
&& aligned_p
)
8709 fputs ("\t.word\t", asm_out_file
);
8710 output_addr_const (asm_out_file
, x
);
8712 /* Mark symbols as position independent. We only do this in the
8713 .text segment, not in the .data segment. */
8714 if (NEED_GOT_RELOC
&& flag_pic
&& making_const_table
&&
8715 (GET_CODE (x
) == SYMBOL_REF
|| GET_CODE (x
) == LABEL_REF
))
8717 if (GET_CODE (x
) == SYMBOL_REF
8718 && (CONSTANT_POOL_ADDRESS_P (x
)
8719 || ENCODED_SHORT_CALL_ATTR_P (XSTR (x
, 0))))
8720 fputs ("(GOTOFF)", asm_out_file
);
8721 else if (GET_CODE (x
) == LABEL_REF
)
8722 fputs ("(GOTOFF)", asm_out_file
);
8724 fputs ("(GOT)", asm_out_file
);
8726 fputc ('\n', asm_out_file
);
8730 return default_assemble_integer (x
, size
, aligned_p
);
8734 /* A finite state machine takes care of noticing whether or not instructions
8735 can be conditionally executed, and thus decrease execution time and code
8736 size by deleting branch instructions. The fsm is controlled by
8737 final_prescan_insn, and controls the actions of ASM_OUTPUT_OPCODE. */
8739 /* The state of the fsm controlling condition codes are:
8740 0: normal, do nothing special
8741 1: make ASM_OUTPUT_OPCODE not output this instruction
8742 2: make ASM_OUTPUT_OPCODE not output this instruction
8743 3: make instructions conditional
8744 4: make instructions conditional
8746 State transitions (state->state by whom under condition):
8747 0 -> 1 final_prescan_insn if the `target' is a label
8748 0 -> 2 final_prescan_insn if the `target' is an unconditional branch
8749 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch
8750 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch
8751 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached
8752 (the target label has CODE_LABEL_NUMBER equal to arm_target_label).
8753 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached
8754 (the target insn is arm_target_insn).
8756 If the jump clobbers the conditions then we use states 2 and 4.
8758 A similar thing can be done with conditional return insns.
8760 XXX In case the `target' is an unconditional branch, this conditionalising
8761 of the instructions always reduces code size, but not always execution
8762 time. But then, I want to reduce the code size to somewhere near what
8763 /bin/cc produces. */
8765 /* Returns the index of the ARM condition code string in
8766 `arm_condition_codes'. COMPARISON should be an rtx like
8767 `(eq (...) (...))'. */
8769 static enum arm_cond_code
8770 get_arm_condition_code (comparison
)
8773 enum machine_mode mode
= GET_MODE (XEXP (comparison
, 0));
8775 enum rtx_code comp_code
= GET_CODE (comparison
);
8777 if (GET_MODE_CLASS (mode
) != MODE_CC
)
8778 mode
= SELECT_CC_MODE (comp_code
, XEXP (comparison
, 0),
8779 XEXP (comparison
, 1));
8783 case CC_DNEmode
: code
= ARM_NE
; goto dominance
;
8784 case CC_DEQmode
: code
= ARM_EQ
; goto dominance
;
8785 case CC_DGEmode
: code
= ARM_GE
; goto dominance
;
8786 case CC_DGTmode
: code
= ARM_GT
; goto dominance
;
8787 case CC_DLEmode
: code
= ARM_LE
; goto dominance
;
8788 case CC_DLTmode
: code
= ARM_LT
; goto dominance
;
8789 case CC_DGEUmode
: code
= ARM_CS
; goto dominance
;
8790 case CC_DGTUmode
: code
= ARM_HI
; goto dominance
;
8791 case CC_DLEUmode
: code
= ARM_LS
; goto dominance
;
8792 case CC_DLTUmode
: code
= ARM_CC
;
8795 if (comp_code
!= EQ
&& comp_code
!= NE
)
8798 if (comp_code
== EQ
)
8799 return ARM_INVERSE_CONDITION_CODE (code
);
8805 case NE
: return ARM_NE
;
8806 case EQ
: return ARM_EQ
;
8807 case GE
: return ARM_PL
;
8808 case LT
: return ARM_MI
;
8815 case NE
: return ARM_NE
;
8816 case EQ
: return ARM_EQ
;
8822 /* These encodings assume that AC=1 in the FPA system control
8823 byte. This allows us to handle all cases except UNEQ and
8827 case GE
: return ARM_GE
;
8828 case GT
: return ARM_GT
;
8829 case LE
: return ARM_LS
;
8830 case LT
: return ARM_MI
;
8831 case NE
: return ARM_NE
;
8832 case EQ
: return ARM_EQ
;
8833 case ORDERED
: return ARM_VC
;
8834 case UNORDERED
: return ARM_VS
;
8835 case UNLT
: return ARM_LT
;
8836 case UNLE
: return ARM_LE
;
8837 case UNGT
: return ARM_HI
;
8838 case UNGE
: return ARM_PL
;
8839 /* UNEQ and LTGT do not have a representation. */
8840 case UNEQ
: /* Fall through. */
8841 case LTGT
: /* Fall through. */
8848 case NE
: return ARM_NE
;
8849 case EQ
: return ARM_EQ
;
8850 case GE
: return ARM_LE
;
8851 case GT
: return ARM_LT
;
8852 case LE
: return ARM_GE
;
8853 case LT
: return ARM_GT
;
8854 case GEU
: return ARM_LS
;
8855 case GTU
: return ARM_CC
;
8856 case LEU
: return ARM_CS
;
8857 case LTU
: return ARM_HI
;
8864 case LTU
: return ARM_CS
;
8865 case GEU
: return ARM_CC
;
8872 case NE
: return ARM_NE
;
8873 case EQ
: return ARM_EQ
;
8874 case GE
: return ARM_GE
;
8875 case GT
: return ARM_GT
;
8876 case LE
: return ARM_LE
;
8877 case LT
: return ARM_LT
;
8878 case GEU
: return ARM_CS
;
8879 case GTU
: return ARM_HI
;
8880 case LEU
: return ARM_LS
;
8881 case LTU
: return ARM_CC
;
8893 arm_final_prescan_insn (insn
)
8896 /* BODY will hold the body of INSN. */
8897 rtx body
= PATTERN (insn
);
8899 /* This will be 1 if trying to repeat the trick, and things need to be
8900 reversed if it appears to fail. */
8903 /* JUMP_CLOBBERS will be one implies that the conditions if a branch is
8904 taken are clobbered, even if the rtl suggests otherwise. It also
8905 means that we have to grub around within the jump expression to find
8906 out what the conditions are when the jump isn't taken. */
8907 int jump_clobbers
= 0;
8909 /* If we start with a return insn, we only succeed if we find another one. */
8910 int seeking_return
= 0;
8912 /* START_INSN will hold the insn from where we start looking. This is the
8913 first insn after the following code_label if REVERSE is true. */
8914 rtx start_insn
= insn
;
8916 /* If in state 4, check if the target branch is reached, in order to
8917 change back to state 0. */
8918 if (arm_ccfsm_state
== 4)
8920 if (insn
== arm_target_insn
)
8922 arm_target_insn
= NULL
;
8923 arm_ccfsm_state
= 0;
8928 /* If in state 3, it is possible to repeat the trick, if this insn is an
8929 unconditional branch to a label, and immediately following this branch
8930 is the previous target label which is only used once, and the label this
8931 branch jumps to is not too far off. */
8932 if (arm_ccfsm_state
== 3)
8934 if (simplejump_p (insn
))
8936 start_insn
= next_nonnote_insn (start_insn
);
8937 if (GET_CODE (start_insn
) == BARRIER
)
8939 /* XXX Isn't this always a barrier? */
8940 start_insn
= next_nonnote_insn (start_insn
);
8942 if (GET_CODE (start_insn
) == CODE_LABEL
8943 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
8944 && LABEL_NUSES (start_insn
) == 1)
8949 else if (GET_CODE (body
) == RETURN
)
8951 start_insn
= next_nonnote_insn (start_insn
);
8952 if (GET_CODE (start_insn
) == BARRIER
)
8953 start_insn
= next_nonnote_insn (start_insn
);
8954 if (GET_CODE (start_insn
) == CODE_LABEL
8955 && CODE_LABEL_NUMBER (start_insn
) == arm_target_label
8956 && LABEL_NUSES (start_insn
) == 1)
8968 if (arm_ccfsm_state
!= 0 && !reverse
)
8970 if (GET_CODE (insn
) != JUMP_INSN
)
8973 /* This jump might be paralleled with a clobber of the condition codes
8974 the jump should always come first */
8975 if (GET_CODE (body
) == PARALLEL
&& XVECLEN (body
, 0) > 0)
8976 body
= XVECEXP (body
, 0, 0);
8979 /* If this is a conditional return then we don't want to know */
8980 if (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
8981 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
8982 && (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
8983 || GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
))
8988 || (GET_CODE (body
) == SET
&& GET_CODE (SET_DEST (body
)) == PC
8989 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
))
8992 int fail
= FALSE
, succeed
= FALSE
;
8993 /* Flag which part of the IF_THEN_ELSE is the LABEL_REF. */
8994 int then_not_else
= TRUE
;
8995 rtx this_insn
= start_insn
, label
= 0;
8997 /* If the jump cannot be done with one instruction, we cannot
8998 conditionally execute the instruction in the inverse case. */
8999 if (get_attr_conds (insn
) == CONDS_JUMP_CLOB
)
9005 /* Register the insn jumped to. */
9008 if (!seeking_return
)
9009 label
= XEXP (SET_SRC (body
), 0);
9011 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == LABEL_REF
)
9012 label
= XEXP (XEXP (SET_SRC (body
), 1), 0);
9013 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == LABEL_REF
)
9015 label
= XEXP (XEXP (SET_SRC (body
), 2), 0);
9016 then_not_else
= FALSE
;
9018 else if (GET_CODE (XEXP (SET_SRC (body
), 1)) == RETURN
)
9020 else if (GET_CODE (XEXP (SET_SRC (body
), 2)) == RETURN
)
9023 then_not_else
= FALSE
;
9028 /* See how many insns this branch skips, and what kind of insns. If all
9029 insns are okay, and the label or unconditional branch to the same
9030 label is not too far away, succeed. */
9031 for (insns_skipped
= 0;
9032 !fail
&& !succeed
&& insns_skipped
++ < max_insns_skipped
;)
9036 this_insn
= next_nonnote_insn (this_insn
);
9040 switch (GET_CODE (this_insn
))
9043 /* Succeed if it is the target label, otherwise fail since
9044 control falls in from somewhere else. */
9045 if (this_insn
== label
)
9049 arm_ccfsm_state
= 2;
9050 this_insn
= next_nonnote_insn (this_insn
);
9053 arm_ccfsm_state
= 1;
9061 /* Succeed if the following insn is the target label.
9063 If return insns are used then the last insn in a function
9064 will be a barrier. */
9065 this_insn
= next_nonnote_insn (this_insn
);
9066 if (this_insn
&& this_insn
== label
)
9070 arm_ccfsm_state
= 2;
9071 this_insn
= next_nonnote_insn (this_insn
);
9074 arm_ccfsm_state
= 1;
9082 /* If using 32-bit addresses the cc is not preserved over
9086 /* Succeed if the following insn is the target label,
9087 or if the following two insns are a barrier and
9088 the target label. */
9089 this_insn
= next_nonnote_insn (this_insn
);
9090 if (this_insn
&& GET_CODE (this_insn
) == BARRIER
)
9091 this_insn
= next_nonnote_insn (this_insn
);
9093 if (this_insn
&& this_insn
== label
9094 && insns_skipped
< max_insns_skipped
)
9098 arm_ccfsm_state
= 2;
9099 this_insn
= next_nonnote_insn (this_insn
);
9102 arm_ccfsm_state
= 1;
9111 /* If this is an unconditional branch to the same label, succeed.
9112 If it is to another label, do nothing. If it is conditional,
9114 /* XXX Probably, the tests for SET and the PC are unnecessary. */
9116 scanbody
= PATTERN (this_insn
);
9117 if (GET_CODE (scanbody
) == SET
9118 && GET_CODE (SET_DEST (scanbody
)) == PC
)
9120 if (GET_CODE (SET_SRC (scanbody
)) == LABEL_REF
9121 && XEXP (SET_SRC (scanbody
), 0) == label
&& !reverse
)
9123 arm_ccfsm_state
= 2;
9126 else if (GET_CODE (SET_SRC (scanbody
)) == IF_THEN_ELSE
)
9129 /* Fail if a conditional return is undesirable (eg on a
9130 StrongARM), but still allow this if optimizing for size. */
9131 else if (GET_CODE (scanbody
) == RETURN
9132 && !use_return_insn (TRUE
)
9135 else if (GET_CODE (scanbody
) == RETURN
9138 arm_ccfsm_state
= 2;
9141 else if (GET_CODE (scanbody
) == PARALLEL
)
9143 switch (get_attr_conds (this_insn
))
9153 fail
= TRUE
; /* Unrecognized jump (eg epilogue). */
9158 /* Instructions using or affecting the condition codes make it
9160 scanbody
= PATTERN (this_insn
);
9161 if (!(GET_CODE (scanbody
) == SET
9162 || GET_CODE (scanbody
) == PARALLEL
)
9163 || get_attr_conds (this_insn
) != CONDS_NOCOND
)
9173 if ((!seeking_return
) && (arm_ccfsm_state
== 1 || reverse
))
9174 arm_target_label
= CODE_LABEL_NUMBER (label
);
9175 else if (seeking_return
|| arm_ccfsm_state
== 2)
9177 while (this_insn
&& GET_CODE (PATTERN (this_insn
)) == USE
)
9179 this_insn
= next_nonnote_insn (this_insn
);
9180 if (this_insn
&& (GET_CODE (this_insn
) == BARRIER
9181 || GET_CODE (this_insn
) == CODE_LABEL
))
9186 /* Oh, dear! we ran off the end.. give up */
9187 recog (PATTERN (insn
), insn
, NULL
);
9188 arm_ccfsm_state
= 0;
9189 arm_target_insn
= NULL
;
9192 arm_target_insn
= this_insn
;
9201 get_arm_condition_code (XEXP (XEXP (XEXP (SET_SRC (body
),
9203 if (GET_CODE (XEXP (XEXP (SET_SRC (body
), 0), 0)) == AND
)
9204 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
9205 if (GET_CODE (XEXP (SET_SRC (body
), 0)) == NE
)
9206 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
9210 /* If REVERSE is true, ARM_CURRENT_CC needs to be inverted from
9213 arm_current_cc
= get_arm_condition_code (XEXP (SET_SRC (body
),
9217 if (reverse
|| then_not_else
)
9218 arm_current_cc
= ARM_INVERSE_CONDITION_CODE (arm_current_cc
);
9221 /* Restore recog_data (getting the attributes of other insns can
9222 destroy this array, but final.c assumes that it remains intact
9223 across this call; since the insn has been recognized already we
9224 call recog direct). */
9225 recog (PATTERN (insn
), insn
, NULL
);
9229 /* Returns true if REGNO is a valid register
9230 for holding a quantity of tyoe MODE. */
9233 arm_hard_regno_mode_ok (regno
, mode
)
9235 enum machine_mode mode
;
9237 if (GET_MODE_CLASS (mode
) == MODE_CC
)
9238 return regno
== CC_REGNUM
;
9241 /* For the Thumb we only allow values bigger than SImode in
9242 registers 0 - 6, so that there is always a second low
9243 register available to hold the upper part of the value.
9244 We probably we ought to ensure that the register is the
9245 start of an even numbered register pair. */
9246 return (ARM_NUM_REGS (mode
) < 2) || (regno
< LAST_LO_REGNUM
);
9248 if (regno
<= LAST_ARM_REGNUM
)
9249 /* We allow any value to be stored in the general regisetrs. */
9252 if ( regno
== FRAME_POINTER_REGNUM
9253 || regno
== ARG_POINTER_REGNUM
)
9254 /* We only allow integers in the fake hard registers. */
9255 return GET_MODE_CLASS (mode
) == MODE_INT
;
9257 /* The only registers left are the FPU registers
9258 which we only allow to hold FP values. */
9259 return GET_MODE_CLASS (mode
) == MODE_FLOAT
9260 && regno
>= FIRST_ARM_FP_REGNUM
9261 && regno
<= LAST_ARM_FP_REGNUM
;
9265 arm_regno_class (regno
)
9270 if (regno
== STACK_POINTER_REGNUM
)
9272 if (regno
== CC_REGNUM
)
9279 if ( regno
<= LAST_ARM_REGNUM
9280 || regno
== FRAME_POINTER_REGNUM
9281 || regno
== ARG_POINTER_REGNUM
)
9282 return GENERAL_REGS
;
9284 if (regno
== CC_REGNUM
)
9290 /* Handle a special case when computing the offset
9291 of an argument from the frame pointer. */
9294 arm_debugger_arg_offset (value
, addr
)
9300 /* We are only interested if dbxout_parms() failed to compute the offset. */
9304 /* We can only cope with the case where the address is held in a register. */
9305 if (GET_CODE (addr
) != REG
)
9308 /* If we are using the frame pointer to point at the argument, then
9309 an offset of 0 is correct. */
9310 if (REGNO (addr
) == (unsigned) HARD_FRAME_POINTER_REGNUM
)
9313 /* If we are using the stack pointer to point at the
9314 argument, then an offset of 0 is correct. */
9315 if ((TARGET_THUMB
|| !frame_pointer_needed
)
9316 && REGNO (addr
) == SP_REGNUM
)
9319 /* Oh dear. The argument is pointed to by a register rather
9320 than being held in a register, or being stored at a known
9321 offset from the frame pointer. Since GDB only understands
9322 those two kinds of argument we must translate the address
9323 held in the register into an offset from the frame pointer.
9324 We do this by searching through the insns for the function
9325 looking to see where this register gets its value. If the
9326 register is initialized from the frame pointer plus an offset
9327 then we are in luck and we can continue, otherwise we give up.
9329 This code is exercised by producing debugging information
9330 for a function with arguments like this:
9332 double func (double a, double b, int c, double d) {return d;}
9334 Without this code the stab for parameter 'd' will be set to
9335 an offset of 0 from the frame pointer, rather than 8. */
9337 /* The if() statement says:
9339 If the insn is a normal instruction
9340 and if the insn is setting the value in a register
9341 and if the register being set is the register holding the address of the argument
9342 and if the address is computing by an addition
9343 that involves adding to a register
9344 which is the frame pointer
9349 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9351 if ( GET_CODE (insn
) == INSN
9352 && GET_CODE (PATTERN (insn
)) == SET
9353 && REGNO (XEXP (PATTERN (insn
), 0)) == REGNO (addr
)
9354 && GET_CODE (XEXP (PATTERN (insn
), 1)) == PLUS
9355 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 0)) == REG
9356 && REGNO (XEXP (XEXP (PATTERN (insn
), 1), 0)) == (unsigned) HARD_FRAME_POINTER_REGNUM
9357 && GET_CODE (XEXP (XEXP (PATTERN (insn
), 1), 1)) == CONST_INT
9360 value
= INTVAL (XEXP (XEXP (PATTERN (insn
), 1), 1));
9369 warning ("unable to compute real location of stacked parameter");
9370 value
= 8; /* XXX magic hack */
9376 #define def_builtin(NAME, TYPE, CODE) \
9377 builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE)
9380 arm_init_builtins ()
9382 tree endlink
= void_list_node
;
9383 tree int_endlink
= tree_cons (NULL_TREE
, integer_type_node
, endlink
);
9384 tree pchar_type_node
= build_pointer_type (char_type_node
);
9386 tree int_ftype_int
, void_ftype_pchar
;
9388 /* void func (char *) */
9390 = build_function_type_list (void_type_node
, pchar_type_node
, NULL_TREE
);
9392 /* int func (int) */
9394 = build_function_type (integer_type_node
, int_endlink
);
9396 /* Initialize arm V5 builtins. */
9398 def_builtin ("__builtin_clz", int_ftype_int
, ARM_BUILTIN_CLZ
);
9401 /* Expand an expression EXP that calls a built-in function,
9402 with result going to TARGET if that's convenient
9403 (and in mode MODE if that's convenient).
9404 SUBTARGET may be used as the target for computing one of EXP's operands.
9405 IGNORE is nonzero if the value is to be ignored. */
9408 arm_expand_builtin (exp
, target
, subtarget
, mode
, ignore
)
9411 rtx subtarget ATTRIBUTE_UNUSED
;
9412 enum machine_mode mode ATTRIBUTE_UNUSED
;
9413 int ignore ATTRIBUTE_UNUSED
;
9415 enum insn_code icode
;
9416 tree fndecl
= TREE_OPERAND (TREE_OPERAND (exp
, 0), 0);
9417 tree arglist
= TREE_OPERAND (exp
, 1);
9420 enum machine_mode tmode
, mode0
;
9421 int fcode
= DECL_FUNCTION_CODE (fndecl
);
9428 case ARM_BUILTIN_CLZ
:
9429 icode
= CODE_FOR_clz
;
9430 arg0
= TREE_VALUE (arglist
);
9431 op0
= expand_expr (arg0
, NULL_RTX
, VOIDmode
, 0);
9432 tmode
= insn_data
[icode
].operand
[0].mode
;
9433 mode0
= insn_data
[icode
].operand
[1].mode
;
9435 if (! (*insn_data
[icode
].operand
[1].predicate
) (op0
, mode0
))
9436 op0
= copy_to_mode_reg (mode0
, op0
);
9438 || GET_MODE (target
) != tmode
9439 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, tmode
))
9440 target
= gen_reg_rtx (tmode
);
9441 pat
= GEN_FCN (icode
) (target
, op0
);
9448 /* @@@ Should really do something sensible here. */
9452 /* Recursively search through all of the blocks in a function
9453 checking to see if any of the variables created in that
9454 function match the RTX called 'orig'. If they do then
9455 replace them with the RTX called 'new'. */
9458 replace_symbols_in_block (block
, orig
, new)
9463 for (; block
; block
= BLOCK_CHAIN (block
))
9467 if (!TREE_USED (block
))
9470 for (sym
= BLOCK_VARS (block
); sym
; sym
= TREE_CHAIN (sym
))
9472 if ( (DECL_NAME (sym
) == 0 && TREE_CODE (sym
) != TYPE_DECL
)
9473 || DECL_IGNORED_P (sym
)
9474 || TREE_CODE (sym
) != VAR_DECL
9475 || DECL_EXTERNAL (sym
)
9476 || !rtx_equal_p (DECL_RTL (sym
), orig
)
9480 SET_DECL_RTL (sym
, new);
9483 replace_symbols_in_block (BLOCK_SUBBLOCKS (block
), orig
, new);
9487 /* Return the number (counting from 0) of
9488 the least significant set bit in MASK. */
9494 number_of_first_bit_set (mask
)
9500 (mask
& (1 << bit
)) == 0;
9507 /* Generate code to return from a thumb function.
9508 If 'reg_containing_return_addr' is -1, then the return address is
9509 actually on the stack, at the stack pointer. */
9511 thumb_exit (f
, reg_containing_return_addr
, eh_ofs
)
9513 int reg_containing_return_addr
;
9516 unsigned regs_available_for_popping
;
9517 unsigned regs_to_pop
;
9523 int restore_a4
= FALSE
;
9525 /* Compute the registers we need to pop. */
9529 /* There is an assumption here, that if eh_ofs is not NULL, the
9530 normal return address will have been pushed. */
9531 if (reg_containing_return_addr
== -1 || eh_ofs
)
9533 /* When we are generating a return for __builtin_eh_return,
9534 reg_containing_return_addr must specify the return regno. */
9535 if (eh_ofs
&& reg_containing_return_addr
== -1)
9538 regs_to_pop
|= 1 << LR_REGNUM
;
9542 if (TARGET_BACKTRACE
)
9544 /* Restore the (ARM) frame pointer and stack pointer. */
9545 regs_to_pop
|= (1 << ARM_HARD_FRAME_POINTER_REGNUM
) | (1 << SP_REGNUM
);
9549 /* If there is nothing to pop then just emit the BX instruction and
9551 if (pops_needed
== 0)
9554 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
9556 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
9559 /* Otherwise if we are not supporting interworking and we have not created
9560 a backtrace structure and the function was not entered in ARM mode then
9561 just pop the return address straight into the PC. */
9562 else if (!TARGET_INTERWORK
9563 && !TARGET_BACKTRACE
9564 && !is_called_in_ARM_mode (current_function_decl
))
9568 asm_fprintf (f
, "\tadd\t%r, #4\n", SP_REGNUM
);
9569 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
9570 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
9573 asm_fprintf (f
, "\tpop\t{%r}\n", PC_REGNUM
);
9578 /* Find out how many of the (return) argument registers we can corrupt. */
9579 regs_available_for_popping
= 0;
9581 /* If returning via __builtin_eh_return, the bottom three registers
9582 all contain information needed for the return. */
9588 /* If we can deduce the registers used from the function's
9589 return value. This is more reliable that examining
9590 regs_ever_live[] because that will be set if the register is
9591 ever used in the function, not just if the register is used
9592 to hold a return value. */
9594 if (current_function_return_rtx
!= 0)
9595 mode
= GET_MODE (current_function_return_rtx
);
9598 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
9600 size
= GET_MODE_SIZE (mode
);
9604 /* In a void function we can use any argument register.
9605 In a function that returns a structure on the stack
9606 we can use the second and third argument registers. */
9607 if (mode
== VOIDmode
)
9608 regs_available_for_popping
=
9609 (1 << ARG_REGISTER (1))
9610 | (1 << ARG_REGISTER (2))
9611 | (1 << ARG_REGISTER (3));
9613 regs_available_for_popping
=
9614 (1 << ARG_REGISTER (2))
9615 | (1 << ARG_REGISTER (3));
9618 regs_available_for_popping
=
9619 (1 << ARG_REGISTER (2))
9620 | (1 << ARG_REGISTER (3));
9622 regs_available_for_popping
=
9623 (1 << ARG_REGISTER (3));
9626 /* Match registers to be popped with registers into which we pop them. */
9627 for (available
= regs_available_for_popping
,
9628 required
= regs_to_pop
;
9629 required
!= 0 && available
!= 0;
9630 available
&= ~(available
& - available
),
9631 required
&= ~(required
& - required
))
9634 /* If we have any popping registers left over, remove them. */
9636 regs_available_for_popping
&= ~available
;
9638 /* Otherwise if we need another popping register we can use
9639 the fourth argument register. */
9640 else if (pops_needed
)
9642 /* If we have not found any free argument registers and
9643 reg a4 contains the return address, we must move it. */
9644 if (regs_available_for_popping
== 0
9645 && reg_containing_return_addr
== LAST_ARG_REGNUM
)
9647 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
9648 reg_containing_return_addr
= LR_REGNUM
;
9652 /* Register a4 is being used to hold part of the return value,
9653 but we have dire need of a free, low register. */
9656 asm_fprintf (f
, "\tmov\t%r, %r\n",IP_REGNUM
, LAST_ARG_REGNUM
);
9659 if (reg_containing_return_addr
!= LAST_ARG_REGNUM
)
9661 /* The fourth argument register is available. */
9662 regs_available_for_popping
|= 1 << LAST_ARG_REGNUM
;
9668 /* Pop as many registers as we can. */
9669 thumb_pushpop (f
, regs_available_for_popping
, FALSE
);
9671 /* Process the registers we popped. */
9672 if (reg_containing_return_addr
== -1)
9674 /* The return address was popped into the lowest numbered register. */
9675 regs_to_pop
&= ~(1 << LR_REGNUM
);
9677 reg_containing_return_addr
=
9678 number_of_first_bit_set (regs_available_for_popping
);
9680 /* Remove this register for the mask of available registers, so that
9681 the return address will not be corrupted by futher pops. */
9682 regs_available_for_popping
&= ~(1 << reg_containing_return_addr
);
9685 /* If we popped other registers then handle them here. */
9686 if (regs_available_for_popping
)
9690 /* Work out which register currently contains the frame pointer. */
9691 frame_pointer
= number_of_first_bit_set (regs_available_for_popping
);
9693 /* Move it into the correct place. */
9694 asm_fprintf (f
, "\tmov\t%r, %r\n",
9695 ARM_HARD_FRAME_POINTER_REGNUM
, frame_pointer
);
9697 /* (Temporarily) remove it from the mask of popped registers. */
9698 regs_available_for_popping
&= ~(1 << frame_pointer
);
9699 regs_to_pop
&= ~(1 << ARM_HARD_FRAME_POINTER_REGNUM
);
9701 if (regs_available_for_popping
)
9705 /* We popped the stack pointer as well,
9706 find the register that contains it. */
9707 stack_pointer
= number_of_first_bit_set (regs_available_for_popping
);
9709 /* Move it into the stack register. */
9710 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, stack_pointer
);
9712 /* At this point we have popped all necessary registers, so
9713 do not worry about restoring regs_available_for_popping
9714 to its correct value:
9716 assert (pops_needed == 0)
9717 assert (regs_available_for_popping == (1 << frame_pointer))
9718 assert (regs_to_pop == (1 << STACK_POINTER)) */
9722 /* Since we have just move the popped value into the frame
9723 pointer, the popping register is available for reuse, and
9724 we know that we still have the stack pointer left to pop. */
9725 regs_available_for_popping
|= (1 << frame_pointer
);
9729 /* If we still have registers left on the stack, but we no longer have
9730 any registers into which we can pop them, then we must move the return
9731 address into the link register and make available the register that
9733 if (regs_available_for_popping
== 0 && pops_needed
> 0)
9735 regs_available_for_popping
|= 1 << reg_containing_return_addr
;
9737 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
,
9738 reg_containing_return_addr
);
9740 reg_containing_return_addr
= LR_REGNUM
;
9743 /* If we have registers left on the stack then pop some more.
9744 We know that at most we will want to pop FP and SP. */
9745 if (pops_needed
> 0)
9750 thumb_pushpop (f
, regs_available_for_popping
, FALSE
);
9752 /* We have popped either FP or SP.
9753 Move whichever one it is into the correct register. */
9754 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
9755 move_to
= number_of_first_bit_set (regs_to_pop
);
9757 asm_fprintf (f
, "\tmov\t%r, %r\n", move_to
, popped_into
);
9759 regs_to_pop
&= ~(1 << move_to
);
9764 /* If we still have not popped everything then we must have only
9765 had one register available to us and we are now popping the SP. */
9766 if (pops_needed
> 0)
9770 thumb_pushpop (f
, regs_available_for_popping
, FALSE
);
9772 popped_into
= number_of_first_bit_set (regs_available_for_popping
);
9774 asm_fprintf (f
, "\tmov\t%r, %r\n", SP_REGNUM
, popped_into
);
9776 assert (regs_to_pop == (1 << STACK_POINTER))
9777 assert (pops_needed == 1)
9781 /* If necessary restore the a4 register. */
9784 if (reg_containing_return_addr
!= LR_REGNUM
)
9786 asm_fprintf (f
, "\tmov\t%r, %r\n", LR_REGNUM
, LAST_ARG_REGNUM
);
9787 reg_containing_return_addr
= LR_REGNUM
;
9790 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
9794 asm_fprintf (f
, "\tadd\t%r, %r\n", SP_REGNUM
, REGNO (eh_ofs
));
9796 /* Return to caller. */
9797 asm_fprintf (f
, "\tbx\t%r\n", reg_containing_return_addr
);
9800 /* Emit code to push or pop registers to or from the stack. */
9803 thumb_pushpop (f
, mask
, push
)
9809 int lo_mask
= mask
& 0xFF;
9811 if (lo_mask
== 0 && !push
&& (mask
& (1 << 15)))
9813 /* Special case. Do not generate a POP PC statement here, do it in
9815 thumb_exit (f
, -1, NULL_RTX
);
9819 fprintf (f
, "\t%s\t{", push
? "push" : "pop");
9821 /* Look at the low registers first. */
9822 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++, lo_mask
>>= 1)
9826 asm_fprintf (f
, "%r", regno
);
9828 if ((lo_mask
& ~1) != 0)
9833 if (push
&& (mask
& (1 << LR_REGNUM
)))
9835 /* Catch pushing the LR. */
9839 asm_fprintf (f
, "%r", LR_REGNUM
);
9841 else if (!push
&& (mask
& (1 << PC_REGNUM
)))
9843 /* Catch popping the PC. */
9844 if (TARGET_INTERWORK
|| TARGET_BACKTRACE
)
9846 /* The PC is never poped directly, instead
9847 it is popped into r3 and then BX is used. */
9850 thumb_exit (f
, -1, NULL_RTX
);
9859 asm_fprintf (f
, "%r", PC_REGNUM
);
9867 thumb_final_prescan_insn (insn
)
9870 if (flag_print_asm_name
)
9871 asm_fprintf (asm_out_file
, "%@ 0x%04x\n",
9872 INSN_ADDRESSES (INSN_UID (insn
)));
9876 thumb_shiftable_const (val
)
9877 unsigned HOST_WIDE_INT val
;
9879 unsigned HOST_WIDE_INT mask
= 0xff;
9882 if (val
== 0) /* XXX */
9885 for (i
= 0; i
< 25; i
++)
9886 if ((val
& (mask
<< i
)) == val
)
9892 /* Returns nonzero if the current function contains,
9893 or might contain a far jump. */
9896 thumb_far_jump_used_p (in_prologue
)
9901 /* This test is only important for leaf functions. */
9902 /* assert (!leaf_function_p ()); */
9904 /* If we have already decided that far jumps may be used,
9905 do not bother checking again, and always return true even if
9906 it turns out that they are not being used. Once we have made
9907 the decision that far jumps are present (and that hence the link
9908 register will be pushed onto the stack) we cannot go back on it. */
9909 if (cfun
->machine
->far_jump_used
)
9912 /* If this function is not being called from the prologue/epilogue
9913 generation code then it must be being called from the
9914 INITIAL_ELIMINATION_OFFSET macro. */
9917 /* In this case we know that we are being asked about the elimination
9918 of the arg pointer register. If that register is not being used,
9919 then there are no arguments on the stack, and we do not have to
9920 worry that a far jump might force the prologue to push the link
9921 register, changing the stack offsets. In this case we can just
9922 return false, since the presence of far jumps in the function will
9923 not affect stack offsets.
9925 If the arg pointer is live (or if it was live, but has now been
9926 eliminated and so set to dead) then we do have to test to see if
9927 the function might contain a far jump. This test can lead to some
9928 false negatives, since before reload is completed, then length of
9929 branch instructions is not known, so gcc defaults to returning their
9930 longest length, which in turn sets the far jump attribute to true.
9932 A false negative will not result in bad code being generated, but it
9933 will result in a needless push and pop of the link register. We
9934 hope that this does not occur too often. */
9935 if (regs_ever_live
[ARG_POINTER_REGNUM
])
9936 cfun
->machine
->arg_pointer_live
= 1;
9937 else if (!cfun
->machine
->arg_pointer_live
)
9941 /* Check to see if the function contains a branch
9942 insn with the far jump attribute set. */
9943 for (insn
= get_insns (); insn
; insn
= NEXT_INSN (insn
))
9945 if (GET_CODE (insn
) == JUMP_INSN
9946 /* Ignore tablejump patterns. */
9947 && GET_CODE (PATTERN (insn
)) != ADDR_VEC
9948 && GET_CODE (PATTERN (insn
)) != ADDR_DIFF_VEC
9949 && get_attr_far_jump (insn
) == FAR_JUMP_YES
9952 /* Record the fact that we have decied that
9953 the function does use far jumps. */
9954 cfun
->machine
->far_jump_used
= 1;
9962 /* Return nonzero if FUNC must be entered in ARM mode. */
9965 is_called_in_ARM_mode (func
)
9968 if (TREE_CODE (func
) != FUNCTION_DECL
)
9971 /* Ignore the problem about functions whoes address is taken. */
9972 if (TARGET_CALLEE_INTERWORKING
&& TREE_PUBLIC (func
))
9976 return lookup_attribute ("interfacearm", DECL_ATTRIBUTES (func
)) != NULL_TREE
;
9982 /* The bits which aren't usefully expanded as rtl. */
9985 thumb_unexpanded_epilogue ()
9988 int live_regs_mask
= 0;
9989 int high_regs_pushed
= 0;
9990 int leaf_function
= leaf_function_p ();
9992 rtx eh_ofs
= cfun
->machine
->eh_epilogue_sp_ofs
;
9994 if (return_used_this_function
)
9997 if (IS_NAKED (arm_current_func_type ()))
10000 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
10001 if (THUMB_REG_PUSHED_P (regno
))
10002 live_regs_mask
|= 1 << regno
;
10004 for (regno
= 8; regno
< 13; regno
++)
10005 if (THUMB_REG_PUSHED_P (regno
))
10006 high_regs_pushed
++;
10008 /* The prolog may have pushed some high registers to use as
10009 work registers. eg the testuite file:
10010 gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c
10011 compiles to produce:
10012 push {r4, r5, r6, r7, lr}
10016 as part of the prolog. We have to undo that pushing here. */
10018 if (high_regs_pushed
)
10020 int mask
= live_regs_mask
;
10026 /* If we can deduce the registers used from the function's return value.
10027 This is more reliable that examining regs_ever_live[] because that
10028 will be set if the register is ever used in the function, not just if
10029 the register is used to hold a return value. */
10031 if (current_function_return_rtx
!= 0)
10032 mode
= GET_MODE (current_function_return_rtx
);
10035 mode
= DECL_MODE (DECL_RESULT (current_function_decl
));
10037 size
= GET_MODE_SIZE (mode
);
10039 /* Unless we are returning a type of size > 12 register r3 is
10045 /* Oh dear! We have no low registers into which we can pop
10048 ("no low registers available for popping high registers");
10050 for (next_hi_reg
= 8; next_hi_reg
< 13; next_hi_reg
++)
10051 if (THUMB_REG_PUSHED_P (next_hi_reg
))
10054 while (high_regs_pushed
)
10056 /* Find lo register(s) into which the high register(s) can
10058 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
10060 if (mask
& (1 << regno
))
10061 high_regs_pushed
--;
10062 if (high_regs_pushed
== 0)
10066 mask
&= (2 << regno
) - 1; /* A noop if regno == 8 */
10068 /* Pop the values into the low register(s). */
10069 thumb_pushpop (asm_out_file
, mask
, 0);
10071 /* Move the value(s) into the high registers. */
10072 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
10074 if (mask
& (1 << regno
))
10076 asm_fprintf (asm_out_file
, "\tmov\t%r, %r\n", next_hi_reg
,
10079 for (next_hi_reg
++; next_hi_reg
< 13; next_hi_reg
++)
10080 if (THUMB_REG_PUSHED_P (next_hi_reg
))
10087 had_to_push_lr
= (live_regs_mask
|| !leaf_function
10088 || thumb_far_jump_used_p (1));
10090 if (TARGET_BACKTRACE
10091 && ((live_regs_mask
& 0xFF) == 0)
10092 && regs_ever_live
[LAST_ARG_REGNUM
] != 0)
10094 /* The stack backtrace structure creation code had to
10095 push R7 in order to get a work register, so we pop
10097 live_regs_mask
|= (1 << LAST_LO_REGNUM
);
10100 if (current_function_pretend_args_size
== 0 || TARGET_BACKTRACE
)
10103 && !is_called_in_ARM_mode (current_function_decl
)
10105 live_regs_mask
|= 1 << PC_REGNUM
;
10107 /* Either no argument registers were pushed or a backtrace
10108 structure was created which includes an adjusted stack
10109 pointer, so just pop everything. */
10110 if (live_regs_mask
)
10111 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
);
10114 thumb_exit (asm_out_file
, 2, eh_ofs
);
10115 /* We have either just popped the return address into the
10116 PC or it is was kept in LR for the entire function or
10117 it is still on the stack because we do not want to
10118 return by doing a pop {pc}. */
10119 else if ((live_regs_mask
& (1 << PC_REGNUM
)) == 0)
10120 thumb_exit (asm_out_file
,
10122 && is_called_in_ARM_mode (current_function_decl
)) ?
10123 -1 : LR_REGNUM
, NULL_RTX
);
10127 /* Pop everything but the return address. */
10128 live_regs_mask
&= ~(1 << PC_REGNUM
);
10130 if (live_regs_mask
)
10131 thumb_pushpop (asm_out_file
, live_regs_mask
, FALSE
);
10133 if (had_to_push_lr
)
10134 /* Get the return address into a temporary register. */
10135 thumb_pushpop (asm_out_file
, 1 << LAST_ARG_REGNUM
, 0);
10137 /* Remove the argument registers that were pushed onto the stack. */
10138 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, #%d\n",
10139 SP_REGNUM
, SP_REGNUM
,
10140 current_function_pretend_args_size
);
10143 thumb_exit (asm_out_file
, 2, eh_ofs
);
10145 thumb_exit (asm_out_file
,
10146 had_to_push_lr
? LAST_ARG_REGNUM
: LR_REGNUM
, NULL_RTX
);
10152 /* Functions to save and restore machine-specific function data. */
10154 static struct machine_function
*
10155 arm_init_machine_status ()
10157 struct machine_function
*machine
;
10158 machine
= (machine_function
*) ggc_alloc_cleared (sizeof (machine_function
));
10160 #if ARM_FT_UNKNOWN != 0
10161 machine
->func_type
= ARM_FT_UNKNOWN
;
10166 /* Return an RTX indicating where the return address to the
10167 calling function can be found. */
10170 arm_return_addr (count
, frame
)
10172 rtx frame ATTRIBUTE_UNUSED
;
10177 if (TARGET_APCS_32
)
10178 return get_hard_reg_initial_val (Pmode
, LR_REGNUM
);
10181 rtx lr
= gen_rtx_AND (Pmode
, gen_rtx_REG (Pmode
, LR_REGNUM
),
10182 GEN_INT (RETURN_ADDR_MASK26
));
10183 return get_func_hard_reg_initial_val (cfun
, lr
);
10187 /* Do anything needed before RTL is emitted for each function. */
10190 arm_init_expanders ()
10192 /* Arrange to initialize and mark the machine per-function status. */
10193 init_machine_status
= arm_init_machine_status
;
10196 /* Generate the rest of a function's prologue. */
10199 thumb_expand_prologue ()
10201 HOST_WIDE_INT amount
= (get_frame_size ()
10202 + current_function_outgoing_args_size
);
10203 unsigned long func_type
;
10205 func_type
= arm_current_func_type ();
10207 /* Naked functions don't have prologues. */
10208 if (IS_NAKED (func_type
))
10211 if (IS_INTERRUPT (func_type
))
10213 error ("interrupt Service Routines cannot be coded in Thumb mode");
10217 if (frame_pointer_needed
)
10218 emit_insn (gen_movsi (hard_frame_pointer_rtx
, stack_pointer_rtx
));
10222 amount
= ROUND_UP (amount
);
10225 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10226 GEN_INT (- amount
)));
10232 /* The stack decrement is too big for an immediate value in a single
10233 insn. In theory we could issue multiple subtracts, but after
10234 three of them it becomes more space efficient to place the full
10235 value in the constant pool and load into a register. (Also the
10236 ARM debugger really likes to see only one stack decrement per
10237 function). So instead we look for a scratch register into which
10238 we can load the decrement, and then we subtract this from the
10239 stack pointer. Unfortunately on the thumb the only available
10240 scratch registers are the argument registers, and we cannot use
10241 these as they may hold arguments to the function. Instead we
10242 attempt to locate a call preserved register which is used by this
10243 function. If we can find one, then we know that it will have
10244 been pushed at the start of the prologue and so we can corrupt
10246 for (regno
= LAST_ARG_REGNUM
+ 1; regno
<= LAST_LO_REGNUM
; regno
++)
10247 if (THUMB_REG_PUSHED_P (regno
)
10248 && !(frame_pointer_needed
10249 && (regno
== THUMB_HARD_FRAME_POINTER_REGNUM
)))
10252 if (regno
> LAST_LO_REGNUM
) /* Very unlikely. */
10254 rtx spare
= gen_rtx (REG
, SImode
, IP_REGNUM
);
10256 /* Choose an arbitary, non-argument low register. */
10257 reg
= gen_rtx (REG
, SImode
, LAST_LO_REGNUM
);
10259 /* Save it by copying it into a high, scratch register. */
10260 emit_insn (gen_movsi (spare
, reg
));
10261 /* Add a USE to stop propagate_one_insn() from barfing. */
10262 emit_insn (gen_prologue_use (spare
));
10264 /* Decrement the stack. */
10265 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
10266 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10269 /* Restore the low register's original value. */
10270 emit_insn (gen_movsi (reg
, spare
));
10272 /* Emit a USE of the restored scratch register, so that flow
10273 analysis will not consider the restore redundant. The
10274 register won't be used again in this function and isn't
10275 restored by the epilogue. */
10276 emit_insn (gen_prologue_use (reg
));
10280 reg
= gen_rtx (REG
, SImode
, regno
);
10282 emit_insn (gen_movsi (reg
, GEN_INT (- amount
)));
10283 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10289 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
10290 emit_insn (gen_blockage ());
10294 thumb_expand_epilogue ()
10296 HOST_WIDE_INT amount
= (get_frame_size ()
10297 + current_function_outgoing_args_size
);
10299 /* Naked functions don't have prologues. */
10300 if (IS_NAKED (arm_current_func_type ()))
10303 if (frame_pointer_needed
)
10304 emit_insn (gen_movsi (stack_pointer_rtx
, hard_frame_pointer_rtx
));
10307 amount
= ROUND_UP (amount
);
10310 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
,
10311 GEN_INT (amount
)));
10314 /* r3 is always free in the epilogue. */
10315 rtx reg
= gen_rtx (REG
, SImode
, LAST_ARG_REGNUM
);
10317 emit_insn (gen_movsi (reg
, GEN_INT (amount
)));
10318 emit_insn (gen_addsi3 (stack_pointer_rtx
, stack_pointer_rtx
, reg
));
10322 /* Emit a USE (stack_pointer_rtx), so that
10323 the stack adjustment will not be deleted. */
10324 emit_insn (gen_prologue_use (stack_pointer_rtx
));
10326 if (current_function_profile
|| TARGET_NO_SCHED_PRO
)
10327 emit_insn (gen_blockage ());
10331 thumb_output_function_prologue (f
, size
)
10333 HOST_WIDE_INT size ATTRIBUTE_UNUSED
;
10335 int live_regs_mask
= 0;
10336 int high_regs_pushed
= 0;
10339 if (IS_NAKED (arm_current_func_type ()))
10342 if (is_called_in_ARM_mode (current_function_decl
))
10346 if (GET_CODE (DECL_RTL (current_function_decl
)) != MEM
)
10348 if (GET_CODE (XEXP (DECL_RTL (current_function_decl
), 0)) != SYMBOL_REF
)
10350 name
= XSTR (XEXP (DECL_RTL (current_function_decl
), 0), 0);
10352 /* Generate code sequence to switch us into Thumb mode. */
10353 /* The .code 32 directive has already been emitted by
10354 ASM_DECLARE_FUNCTION_NAME. */
10355 asm_fprintf (f
, "\torr\t%r, %r, #1\n", IP_REGNUM
, PC_REGNUM
);
10356 asm_fprintf (f
, "\tbx\t%r\n", IP_REGNUM
);
10358 /* Generate a label, so that the debugger will notice the
10359 change in instruction sets. This label is also used by
10360 the assembler to bypass the ARM code when this function
10361 is called from a Thumb encoded function elsewhere in the
10362 same file. Hence the definition of STUB_NAME here must
10363 agree with the definition in gas/config/tc-arm.c */
10365 #define STUB_NAME ".real_start_of"
10367 fprintf (f
, "\t.code\t16\n");
10369 if (arm_dllexport_name_p (name
))
10370 name
= arm_strip_name_encoding (name
);
10372 asm_fprintf (f
, "\t.globl %s%U%s\n", STUB_NAME
, name
);
10373 fprintf (f
, "\t.thumb_func\n");
10374 asm_fprintf (f
, "%s%U%s:\n", STUB_NAME
, name
);
10377 if (current_function_pretend_args_size
)
10379 if (cfun
->machine
->uses_anonymous_args
)
10383 fprintf (f
, "\tpush\t{");
10385 num_pushes
= ARM_NUM_INTS (current_function_pretend_args_size
);
10387 for (regno
= LAST_ARG_REGNUM
+ 1 - num_pushes
;
10388 regno
<= LAST_ARG_REGNUM
;
10390 asm_fprintf (f
, "%r%s", regno
,
10391 regno
== LAST_ARG_REGNUM
? "" : ", ");
10393 fprintf (f
, "}\n");
10396 asm_fprintf (f
, "\tsub\t%r, %r, #%d\n",
10397 SP_REGNUM
, SP_REGNUM
,
10398 current_function_pretend_args_size
);
10401 for (regno
= 0; regno
<= LAST_LO_REGNUM
; regno
++)
10402 if (THUMB_REG_PUSHED_P (regno
))
10403 live_regs_mask
|= 1 << regno
;
10405 if (live_regs_mask
|| !leaf_function_p () || thumb_far_jump_used_p (1))
10406 live_regs_mask
|= 1 << LR_REGNUM
;
10408 if (TARGET_BACKTRACE
)
10411 int work_register
= 0;
10414 /* We have been asked to create a stack backtrace structure.
10415 The code looks like this:
10419 0 sub SP, #16 Reserve space for 4 registers.
10420 2 push {R7} Get a work register.
10421 4 add R7, SP, #20 Get the stack pointer before the push.
10422 6 str R7, [SP, #8] Store the stack pointer (before reserving the space).
10423 8 mov R7, PC Get hold of the start of this code plus 12.
10424 10 str R7, [SP, #16] Store it.
10425 12 mov R7, FP Get hold of the current frame pointer.
10426 14 str R7, [SP, #4] Store it.
10427 16 mov R7, LR Get hold of the current return address.
10428 18 str R7, [SP, #12] Store it.
10429 20 add R7, SP, #16 Point at the start of the backtrace structure.
10430 22 mov FP, R7 Put this value into the frame pointer. */
10432 if ((live_regs_mask
& 0xFF) == 0)
10434 /* See if the a4 register is free. */
10436 if (regs_ever_live
[LAST_ARG_REGNUM
] == 0)
10437 work_register
= LAST_ARG_REGNUM
;
10438 else /* We must push a register of our own */
10439 live_regs_mask
|= (1 << LAST_LO_REGNUM
);
10442 if (work_register
== 0)
10444 /* Select a register from the list that will be pushed to
10445 use as our work register. */
10446 for (work_register
= (LAST_LO_REGNUM
+ 1); work_register
--;)
10447 if ((1 << work_register
) & live_regs_mask
)
10452 (f
, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n",
10453 SP_REGNUM
, SP_REGNUM
);
10455 if (live_regs_mask
)
10456 thumb_pushpop (f
, live_regs_mask
, 1);
10458 for (offset
= 0, wr
= 1 << 15; wr
!= 0; wr
>>= 1)
10459 if (wr
& live_regs_mask
)
10462 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
10463 offset
+ 16 + current_function_pretend_args_size
);
10465 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
10468 /* Make sure that the instruction fetching the PC is in the right place
10469 to calculate "start of backtrace creation code + 12". */
10470 if (live_regs_mask
)
10472 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
10473 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
10475 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
10476 ARM_HARD_FRAME_POINTER_REGNUM
);
10477 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
10482 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
,
10483 ARM_HARD_FRAME_POINTER_REGNUM
);
10484 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
10486 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, PC_REGNUM
);
10487 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
10491 asm_fprintf (f
, "\tmov\t%r, %r\n", work_register
, LR_REGNUM
);
10492 asm_fprintf (f
, "\tstr\t%r, [%r, #%d]\n", work_register
, SP_REGNUM
,
10494 asm_fprintf (f
, "\tadd\t%r, %r, #%d\n", work_register
, SP_REGNUM
,
10496 asm_fprintf (f
, "\tmov\t%r, %r\t\t%@ Backtrace structure created\n",
10497 ARM_HARD_FRAME_POINTER_REGNUM
, work_register
);
10499 else if (live_regs_mask
)
10500 thumb_pushpop (f
, live_regs_mask
, 1);
10502 for (regno
= 8; regno
< 13; regno
++)
10503 if (THUMB_REG_PUSHED_P (regno
))
10504 high_regs_pushed
++;
10506 if (high_regs_pushed
)
10508 int pushable_regs
= 0;
10509 int mask
= live_regs_mask
& 0xff;
10512 for (next_hi_reg
= 12; next_hi_reg
> LAST_LO_REGNUM
; next_hi_reg
--)
10513 if (THUMB_REG_PUSHED_P (next_hi_reg
))
10516 pushable_regs
= mask
;
10518 if (pushable_regs
== 0)
10520 /* Desperation time -- this probably will never happen. */
10521 if (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM
))
10522 asm_fprintf (f
, "\tmov\t%r, %r\n", IP_REGNUM
, LAST_ARG_REGNUM
);
10523 mask
= 1 << LAST_ARG_REGNUM
;
10526 while (high_regs_pushed
> 0)
10528 for (regno
= LAST_LO_REGNUM
; regno
>= 0; regno
--)
10530 if (mask
& (1 << regno
))
10532 asm_fprintf (f
, "\tmov\t%r, %r\n", regno
, next_hi_reg
);
10534 high_regs_pushed
--;
10536 if (high_regs_pushed
)
10538 for (next_hi_reg
--; next_hi_reg
> LAST_LO_REGNUM
;
10540 if (THUMB_REG_PUSHED_P (next_hi_reg
))
10545 mask
&= ~((1 << regno
) - 1);
10551 thumb_pushpop (f
, mask
, 1);
10554 if (pushable_regs
== 0
10555 && (THUMB_REG_PUSHED_P (LAST_ARG_REGNUM
)))
10556 asm_fprintf (f
, "\tmov\t%r, %r\n", LAST_ARG_REGNUM
, IP_REGNUM
);
10560 /* Handle the case of a double word load into a low register from
10561 a computed memory address. The computed address may involve a
10562 register which is overwritten by the load. */
10565 thumb_load_double_from_address (operands
)
10574 if (GET_CODE (operands
[0]) != REG
)
10577 if (GET_CODE (operands
[1]) != MEM
)
10580 /* Get the memory address. */
10581 addr
= XEXP (operands
[1], 0);
10583 /* Work out how the memory address is computed. */
10584 switch (GET_CODE (addr
))
10587 operands
[2] = gen_rtx (MEM
, SImode
,
10588 plus_constant (XEXP (operands
[1], 0), 4));
10590 if (REGNO (operands
[0]) == REGNO (addr
))
10592 output_asm_insn ("ldr\t%H0, %2", operands
);
10593 output_asm_insn ("ldr\t%0, %1", operands
);
10597 output_asm_insn ("ldr\t%0, %1", operands
);
10598 output_asm_insn ("ldr\t%H0, %2", operands
);
10603 /* Compute <address> + 4 for the high order load. */
10604 operands
[2] = gen_rtx (MEM
, SImode
,
10605 plus_constant (XEXP (operands
[1], 0), 4));
10607 output_asm_insn ("ldr\t%0, %1", operands
);
10608 output_asm_insn ("ldr\t%H0, %2", operands
);
10612 arg1
= XEXP (addr
, 0);
10613 arg2
= XEXP (addr
, 1);
10615 if (CONSTANT_P (arg1
))
10616 base
= arg2
, offset
= arg1
;
10618 base
= arg1
, offset
= arg2
;
10620 if (GET_CODE (base
) != REG
)
10623 /* Catch the case of <address> = <reg> + <reg> */
10624 if (GET_CODE (offset
) == REG
)
10626 int reg_offset
= REGNO (offset
);
10627 int reg_base
= REGNO (base
);
10628 int reg_dest
= REGNO (operands
[0]);
10630 /* Add the base and offset registers together into the
10631 higher destination register. */
10632 asm_fprintf (asm_out_file
, "\tadd\t%r, %r, %r",
10633 reg_dest
+ 1, reg_base
, reg_offset
);
10635 /* Load the lower destination register from the address in
10636 the higher destination register. */
10637 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #0]",
10638 reg_dest
, reg_dest
+ 1);
10640 /* Load the higher destination register from its own address
10642 asm_fprintf (asm_out_file
, "\tldr\t%r, [%r, #4]",
10643 reg_dest
+ 1, reg_dest
+ 1);
10647 /* Compute <address> + 4 for the high order load. */
10648 operands
[2] = gen_rtx (MEM
, SImode
,
10649 plus_constant (XEXP (operands
[1], 0), 4));
10651 /* If the computed address is held in the low order register
10652 then load the high order register first, otherwise always
10653 load the low order register first. */
10654 if (REGNO (operands
[0]) == REGNO (base
))
10656 output_asm_insn ("ldr\t%H0, %2", operands
);
10657 output_asm_insn ("ldr\t%0, %1", operands
);
10661 output_asm_insn ("ldr\t%0, %1", operands
);
10662 output_asm_insn ("ldr\t%H0, %2", operands
);
10668 /* With no registers to worry about we can just load the value
10670 operands
[2] = gen_rtx (MEM
, SImode
,
10671 plus_constant (XEXP (operands
[1], 0), 4));
10673 output_asm_insn ("ldr\t%H0, %2", operands
);
10674 output_asm_insn ("ldr\t%0, %1", operands
);
10687 thumb_output_move_mem_multiple (n
, operands
)
10696 if (REGNO (operands
[4]) > REGNO (operands
[5]))
10699 operands
[4] = operands
[5];
10702 output_asm_insn ("ldmia\t%1!, {%4, %5}", operands
);
10703 output_asm_insn ("stmia\t%0!, {%4, %5}", operands
);
10707 if (REGNO (operands
[4]) > REGNO (operands
[5]))
10710 operands
[4] = operands
[5];
10713 if (REGNO (operands
[5]) > REGNO (operands
[6]))
10716 operands
[5] = operands
[6];
10719 if (REGNO (operands
[4]) > REGNO (operands
[5]))
10722 operands
[4] = operands
[5];
10726 output_asm_insn ("ldmia\t%1!, {%4, %5, %6}", operands
);
10727 output_asm_insn ("stmia\t%0!, {%4, %5, %6}", operands
);
10737 /* Routines for generating rtl. */
10740 thumb_expand_movstrqi (operands
)
10743 rtx out
= copy_to_mode_reg (SImode
, XEXP (operands
[0], 0));
10744 rtx in
= copy_to_mode_reg (SImode
, XEXP (operands
[1], 0));
10745 HOST_WIDE_INT len
= INTVAL (operands
[2]);
10746 HOST_WIDE_INT offset
= 0;
10750 emit_insn (gen_movmem12b (out
, in
, out
, in
));
10756 emit_insn (gen_movmem8b (out
, in
, out
, in
));
10762 rtx reg
= gen_reg_rtx (SImode
);
10763 emit_insn (gen_movsi (reg
, gen_rtx (MEM
, SImode
, in
)));
10764 emit_insn (gen_movsi (gen_rtx (MEM
, SImode
, out
), reg
));
10771 rtx reg
= gen_reg_rtx (HImode
);
10772 emit_insn (gen_movhi (reg
, gen_rtx (MEM
, HImode
,
10773 plus_constant (in
, offset
))));
10774 emit_insn (gen_movhi (gen_rtx (MEM
, HImode
, plus_constant (out
, offset
)),
10782 rtx reg
= gen_reg_rtx (QImode
);
10783 emit_insn (gen_movqi (reg
, gen_rtx (MEM
, QImode
,
10784 plus_constant (in
, offset
))));
10785 emit_insn (gen_movqi (gen_rtx (MEM
, QImode
, plus_constant (out
, offset
)),
10791 thumb_cmp_operand (op
, mode
)
10793 enum machine_mode mode
;
10795 return ((GET_CODE (op
) == CONST_INT
10796 && (unsigned HOST_WIDE_INT
) (INTVAL (op
)) < 256)
10797 || register_operand (op
, mode
));
10800 static const char *
10801 thumb_condition_code (x
, invert
)
10805 static const char * const conds
[] =
10807 "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
10808 "hi", "ls", "ge", "lt", "gt", "le"
10812 switch (GET_CODE (x
))
10814 case EQ
: val
= 0; break;
10815 case NE
: val
= 1; break;
10816 case GEU
: val
= 2; break;
10817 case LTU
: val
= 3; break;
10818 case GTU
: val
= 8; break;
10819 case LEU
: val
= 9; break;
10820 case GE
: val
= 10; break;
10821 case LT
: val
= 11; break;
10822 case GT
: val
= 12; break;
10823 case LE
: val
= 13; break;
10828 return conds
[val
^ invert
];
10831 /* Handle storing a half-word to memory during reload. */
10834 thumb_reload_out_hi (operands
)
10837 emit_insn (gen_thumb_movhi_clobber (operands
[0], operands
[1], operands
[2]));
10840 /* Handle storing a half-word to memory during reload. */
10843 thumb_reload_in_hi (operands
)
10844 rtx
* operands ATTRIBUTE_UNUSED
;
10849 /* Return the length of a function name prefix
10850 that starts with the character 'c'. */
10853 arm_get_strip_length (c
)
10858 ARM_NAME_ENCODING_LENGTHS
10863 /* Return a pointer to a function's name with any
10864 and all prefix encodings stripped from it. */
10867 arm_strip_name_encoding (name
)
10872 while ((skip
= arm_get_strip_length (* name
)))
10878 /* If there is a '*' anywhere in the name's prefix, then
10879 emit the stripped name verbatim, otherwise prepend an
10880 underscore if leading underscores are being used. */
10883 arm_asm_output_labelref (stream
, name
)
10890 while ((skip
= arm_get_strip_length (* name
)))
10892 verbatim
|= (*name
== '*');
10897 fputs (name
, stream
);
10899 asm_fprintf (stream
, "%U%s", name
);
10904 #ifdef AOF_ASSEMBLER
10905 /* Special functions only needed when producing AOF syntax assembler. */
10909 struct pic_chain
* next
;
10910 const char * symname
;
10913 static struct pic_chain
* aof_pic_chain
= NULL
;
10919 struct pic_chain
** chainp
;
10922 if (aof_pic_label
== NULL_RTX
)
10924 aof_pic_label
= gen_rtx_SYMBOL_REF (Pmode
, "x$adcons");
10927 for (offset
= 0, chainp
= &aof_pic_chain
; *chainp
;
10928 offset
+= 4, chainp
= &(*chainp
)->next
)
10929 if ((*chainp
)->symname
== XSTR (x
, 0))
10930 return plus_constant (aof_pic_label
, offset
);
10932 *chainp
= (struct pic_chain
*) xmalloc (sizeof (struct pic_chain
));
10933 (*chainp
)->next
= NULL
;
10934 (*chainp
)->symname
= XSTR (x
, 0);
10935 return plus_constant (aof_pic_label
, offset
);
10939 aof_dump_pic_table (f
)
10942 struct pic_chain
* chain
;
10944 if (aof_pic_chain
== NULL
)
10947 asm_fprintf (f
, "\tAREA |%r$$adcons|, BASED %r\n",
10948 PIC_OFFSET_TABLE_REGNUM
,
10949 PIC_OFFSET_TABLE_REGNUM
);
10950 fputs ("|x$adcons|\n", f
);
10952 for (chain
= aof_pic_chain
; chain
; chain
= chain
->next
)
10954 fputs ("\tDCD\t", f
);
10955 assemble_name (f
, chain
->symname
);
10960 int arm_text_section_count
= 1;
10963 aof_text_section ()
10965 static char buf
[100];
10966 sprintf (buf
, "\tAREA |C$$code%d|, CODE, READONLY",
10967 arm_text_section_count
++);
10969 strcat (buf
, ", PIC, REENTRANT");
10973 static int arm_data_section_count
= 1;
10976 aof_data_section ()
10978 static char buf
[100];
10979 sprintf (buf
, "\tAREA |C$$data%d|, DATA", arm_data_section_count
++);
10983 /* The AOF assembler is religiously strict about declarations of
10984 imported and exported symbols, so that it is impossible to declare
10985 a function as imported near the beginning of the file, and then to
10986 export it later on. It is, however, possible to delay the decision
10987 until all the functions in the file have been compiled. To get
10988 around this, we maintain a list of the imports and exports, and
10989 delete from it any that are subsequently defined. At the end of
10990 compilation we spit the remainder of the list out before the END
10995 struct import
* next
;
10999 static struct import
* imports_list
= NULL
;
11002 aof_add_import (name
)
11005 struct import
* new;
11007 for (new = imports_list
; new; new = new->next
)
11008 if (new->name
== name
)
11011 new = (struct import
*) xmalloc (sizeof (struct import
));
11012 new->next
= imports_list
;
11013 imports_list
= new;
11018 aof_delete_import (name
)
11021 struct import
** old
;
11023 for (old
= &imports_list
; *old
; old
= & (*old
)->next
)
11025 if ((*old
)->name
== name
)
11027 *old
= (*old
)->next
;
11033 int arm_main_function
= 0;
11036 aof_dump_imports (f
)
11039 /* The AOF assembler needs this to cause the startup code to be extracted
11040 from the library. Brining in __main causes the whole thing to work
11042 if (arm_main_function
)
11045 fputs ("\tIMPORT __main\n", f
);
11046 fputs ("\tDCD __main\n", f
);
11049 /* Now dump the remaining imports. */
11050 while (imports_list
)
11052 fprintf (f
, "\tIMPORT\t");
11053 assemble_name (f
, imports_list
->name
);
11055 imports_list
= imports_list
->next
;
11060 aof_globalize_label (stream
, name
)
11064 default_globalize_label (stream
, name
);
11065 if (! strcmp (name
, "main"))
11066 arm_main_function
= 1;
11068 #endif /* AOF_ASSEMBLER */
11070 #ifdef OBJECT_FORMAT_ELF
11071 /* Switch to an arbitrary section NAME with attributes as specified
11072 by FLAGS. ALIGN specifies any known alignment requirements for
11073 the section; 0 if the default should be used.
11075 Differs from the default elf version only in the prefix character
11076 used before the section type. */
11079 arm_elf_asm_named_section (name
, flags
)
11081 unsigned int flags
;
11083 char flagchars
[10], *f
= flagchars
;
11085 if (! named_section_first_declaration (name
))
11087 fprintf (asm_out_file
, "\t.section\t%s\n", name
);
11091 if (!(flags
& SECTION_DEBUG
))
11093 if (flags
& SECTION_WRITE
)
11095 if (flags
& SECTION_CODE
)
11097 if (flags
& SECTION_SMALL
)
11099 if (flags
& SECTION_MERGE
)
11101 if (flags
& SECTION_STRINGS
)
11103 if (flags
& SECTION_TLS
)
11107 fprintf (asm_out_file
, "\t.section\t%s,\"%s\"", name
, flagchars
);
11109 if (!(flags
& SECTION_NOTYPE
))
11113 if (flags
& SECTION_BSS
)
11118 fprintf (asm_out_file
, ",%%%s", type
);
11120 if (flags
& SECTION_ENTSIZE
)
11121 fprintf (asm_out_file
, ",%d", flags
& SECTION_ENTSIZE
);
11124 putc ('\n', asm_out_file
);
11129 /* Symbols in the text segment can be accessed without indirecting via the
11130 constant pool; it may take an extra binary operation, but this is still
11131 faster than indirecting via memory. Don't do this when not optimizing,
11132 since we won't be calculating al of the offsets necessary to do this
11136 arm_encode_section_info (decl
, first
)
11140 /* This doesn't work with AOF syntax, since the string table may be in
11141 a different AREA. */
11142 #ifndef AOF_ASSEMBLER
11143 if (optimize
> 0 && TREE_CONSTANT (decl
)
11144 && (!flag_writable_strings
|| TREE_CODE (decl
) != STRING_CST
))
11146 rtx rtl
= (TREE_CODE_CLASS (TREE_CODE (decl
)) != 'd'
11147 ? TREE_CST_RTL (decl
) : DECL_RTL (decl
));
11148 SYMBOL_REF_FLAG (XEXP (rtl
, 0)) = 1;
11152 /* If we are referencing a function that is weak then encode a long call
11153 flag in the function name, otherwise if the function is static or
11154 or known to be defined in this file then encode a short call flag. */
11155 if (first
&& TREE_CODE_CLASS (TREE_CODE (decl
)) == 'd')
11157 if (TREE_CODE (decl
) == FUNCTION_DECL
&& DECL_WEAK (decl
))
11158 arm_encode_call_attribute (decl
, LONG_CALL_FLAG_CHAR
);
11159 else if (! TREE_PUBLIC (decl
))
11160 arm_encode_call_attribute (decl
, SHORT_CALL_FLAG_CHAR
);
11163 #endif /* !ARM_PE */
11165 /* Output code to add DELTA to the first argument, and then jump
11166 to FUNCTION. Used for C++ multiple inheritance. */
11169 arm_output_mi_thunk (file
, thunk
, delta
, vcall_offset
, function
)
11171 tree thunk ATTRIBUTE_UNUSED
;
11172 HOST_WIDE_INT delta
;
11173 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
;
11176 int mi_delta
= delta
;
11177 const char *const mi_op
= mi_delta
< 0 ? "sub" : "add";
11179 int this_regno
= (aggregate_value_p (TREE_TYPE (TREE_TYPE (function
)))
11182 mi_delta
= - mi_delta
;
11183 while (mi_delta
!= 0)
11185 if ((mi_delta
& (3 << shift
)) == 0)
11189 asm_fprintf (file
, "\t%s\t%r, %r, #%d\n",
11190 mi_op
, this_regno
, this_regno
,
11191 mi_delta
& (0xff << shift
));
11192 mi_delta
&= ~(0xff << shift
);
11196 fputs ("\tb\t", file
);
11197 assemble_name (file
, XSTR (XEXP (DECL_RTL (function
), 0), 0));
11198 if (NEED_PLT_RELOC
)
11199 fputs ("(PLT)", file
);
11200 fputc ('\n', file
);