1 /* Perform simple optimizations to clean up the result of reload.
2 Copyright (C) 1987-2016 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
38 #include "cfgcleanup.h"
41 #include "tree-pass.h"
44 #ifndef LOAD_EXTEND_OP
45 #define LOAD_EXTEND_OP(M) UNKNOWN
48 static int reload_cse_noop_set_p (rtx
);
49 static bool reload_cse_simplify (rtx_insn
*, rtx
);
50 static void reload_cse_regs_1 (void);
51 static int reload_cse_simplify_set (rtx
, rtx_insn
*);
52 static int reload_cse_simplify_operands (rtx_insn
*, rtx
);
54 static void reload_combine (void);
55 static void reload_combine_note_use (rtx
*, rtx_insn
*, int, rtx
);
56 static void reload_combine_note_store (rtx
, const_rtx
, void *);
58 static bool reload_cse_move2add (rtx_insn
*);
59 static void move2add_note_store (rtx
, const_rtx
, void *);
61 /* Call cse / combine like post-reload optimization phases.
62 FIRST is the first instruction. */
65 reload_cse_regs (rtx_insn
*first ATTRIBUTE_UNUSED
)
70 moves_converted
= reload_cse_move2add (first
);
71 if (flag_expensive_optimizations
)
79 /* See whether a single set SET is a noop. */
81 reload_cse_noop_set_p (rtx set
)
83 if (cselib_reg_set_mode (SET_DEST (set
)) != GET_MODE (SET_DEST (set
)))
86 return rtx_equal_for_cselib_p (SET_DEST (set
), SET_SRC (set
));
89 /* Try to simplify INSN. Return true if the CFG may have changed. */
91 reload_cse_simplify (rtx_insn
*insn
, rtx testreg
)
93 rtx body
= PATTERN (insn
);
94 basic_block insn_bb
= BLOCK_FOR_INSN (insn
);
95 unsigned insn_bb_succs
= EDGE_COUNT (insn_bb
->succs
);
97 if (GET_CODE (body
) == SET
)
101 /* Simplify even if we may think it is a no-op.
102 We may think a memory load of a value smaller than WORD_SIZE
103 is redundant because we haven't taken into account possible
104 implicit extension. reload_cse_simplify_set() will bring
105 this out, so it's safer to simplify before we delete. */
106 count
+= reload_cse_simplify_set (body
, insn
);
108 if (!count
&& reload_cse_noop_set_p (body
))
110 if (check_for_inc_dec (insn
))
111 delete_insn_and_edges (insn
);
112 /* We're done with this insn. */
117 apply_change_group ();
119 reload_cse_simplify_operands (insn
, testreg
);
121 else if (GET_CODE (body
) == PARALLEL
)
125 rtx value
= NULL_RTX
;
127 /* Registers mentioned in the clobber list for an asm cannot be reused
128 within the body of the asm. Invalidate those registers now so that
129 we don't try to substitute values for them. */
130 if (asm_noperands (body
) >= 0)
132 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
134 rtx part
= XVECEXP (body
, 0, i
);
135 if (GET_CODE (part
) == CLOBBER
&& REG_P (XEXP (part
, 0)))
136 cselib_invalidate_rtx (XEXP (part
, 0));
140 /* If every action in a PARALLEL is a noop, we can delete
141 the entire PARALLEL. */
142 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
144 rtx part
= XVECEXP (body
, 0, i
);
145 if (GET_CODE (part
) == SET
)
147 if (! reload_cse_noop_set_p (part
))
149 if (REG_P (SET_DEST (part
))
150 && REG_FUNCTION_VALUE_P (SET_DEST (part
)))
154 value
= SET_DEST (part
);
157 else if (GET_CODE (part
) != CLOBBER
158 && GET_CODE (part
) != USE
)
164 if (check_for_inc_dec (insn
))
165 delete_insn_and_edges (insn
);
166 /* We're done with this insn. */
170 /* It's not a no-op, but we can try to simplify it. */
171 for (i
= XVECLEN (body
, 0) - 1; i
>= 0; --i
)
172 if (GET_CODE (XVECEXP (body
, 0, i
)) == SET
)
173 count
+= reload_cse_simplify_set (XVECEXP (body
, 0, i
), insn
);
176 apply_change_group ();
178 reload_cse_simplify_operands (insn
, testreg
);
182 return (EDGE_COUNT (insn_bb
->succs
) != insn_bb_succs
);
185 /* Do a very simple CSE pass over the hard registers.
187 This function detects no-op moves where we happened to assign two
188 different pseudo-registers to the same hard register, and then
189 copied one to the other. Reload will generate a useless
190 instruction copying a register to itself.
192 This function also detects cases where we load a value from memory
193 into two different registers, and (if memory is more expensive than
194 registers) changes it to simply copy the first register into the
197 Another optimization is performed that scans the operands of each
198 instruction to see whether the value is already available in a
199 hard register. It then replaces the operand with the hard register
200 if possible, much like an optional reload would. */
203 reload_cse_regs_1 (void)
205 bool cfg_changed
= false;
208 rtx testreg
= gen_rtx_REG (word_mode
, LAST_VIRTUAL_REGISTER
+ 1);
210 cselib_init (CSELIB_RECORD_MEMORY
);
211 init_alias_analysis ();
213 FOR_EACH_BB_FN (bb
, cfun
)
214 FOR_BB_INSNS (bb
, insn
)
217 cfg_changed
|= reload_cse_simplify (insn
, testreg
);
219 cselib_process_insn (insn
);
223 end_alias_analysis ();
229 /* Try to simplify a single SET instruction. SET is the set pattern.
230 INSN is the instruction it came from.
231 This function only handles one case: if we set a register to a value
232 which is not a register, we try to find that value in some other register
233 and change the set into a register copy. */
236 reload_cse_simplify_set (rtx set
, rtx_insn
*insn
)
244 struct elt_loc_list
*l
;
245 enum rtx_code extend_op
= UNKNOWN
;
246 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
248 dreg
= true_regnum (SET_DEST (set
));
253 if (side_effects_p (src
) || true_regnum (src
) >= 0)
256 dclass
= REGNO_REG_CLASS (dreg
);
258 /* When replacing a memory with a register, we need to honor assumptions
259 that combine made wrt the contents of sign bits. We'll do this by
260 generating an extend instruction instead of a reg->reg copy. Thus
261 the destination must be a register that we can widen. */
263 && GET_MODE_BITSIZE (GET_MODE (src
)) < BITS_PER_WORD
264 && (extend_op
= LOAD_EXTEND_OP (GET_MODE (src
))) != UNKNOWN
265 && !REG_P (SET_DEST (set
)))
268 val
= cselib_lookup (src
, GET_MODE (SET_DEST (set
)), 0, VOIDmode
);
272 /* If memory loads are cheaper than register copies, don't change them. */
274 old_cost
= memory_move_cost (GET_MODE (src
), dclass
, true);
275 else if (REG_P (src
))
276 old_cost
= register_move_cost (GET_MODE (src
),
277 REGNO_REG_CLASS (REGNO (src
)), dclass
);
279 old_cost
= set_src_cost (src
, GET_MODE (SET_DEST (set
)), speed
);
281 for (l
= val
->locs
; l
; l
= l
->next
)
283 rtx this_rtx
= l
->loc
;
286 if (CONSTANT_P (this_rtx
) && ! references_value_p (this_rtx
, 0))
288 if (extend_op
!= UNKNOWN
)
292 if (!CONST_SCALAR_INT_P (this_rtx
))
298 result
= wide_int::from (std::make_pair (this_rtx
,
300 BITS_PER_WORD
, UNSIGNED
);
303 result
= wide_int::from (std::make_pair (this_rtx
,
305 BITS_PER_WORD
, SIGNED
);
310 this_rtx
= immed_wide_int_const (result
, word_mode
);
313 this_cost
= set_src_cost (this_rtx
, GET_MODE (SET_DEST (set
)), speed
);
315 else if (REG_P (this_rtx
))
317 if (extend_op
!= UNKNOWN
)
319 this_rtx
= gen_rtx_fmt_e (extend_op
, word_mode
, this_rtx
);
320 this_cost
= set_src_cost (this_rtx
, word_mode
, speed
);
323 this_cost
= register_move_cost (GET_MODE (this_rtx
),
324 REGNO_REG_CLASS (REGNO (this_rtx
)),
330 /* If equal costs, prefer registers over anything else. That
331 tends to lead to smaller instructions on some machines. */
332 if (this_cost
< old_cost
333 || (this_cost
== old_cost
335 && !REG_P (SET_SRC (set
))))
337 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set
))) < BITS_PER_WORD
338 && extend_op
!= UNKNOWN
339 #ifdef CANNOT_CHANGE_MODE_CLASS
340 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set
)),
342 REGNO_REG_CLASS (REGNO (SET_DEST (set
))))
346 rtx wide_dest
= gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
)));
347 ORIGINAL_REGNO (wide_dest
) = ORIGINAL_REGNO (SET_DEST (set
));
348 validate_change (insn
, &SET_DEST (set
), wide_dest
, 1);
351 validate_unshare_change (insn
, &SET_SRC (set
), this_rtx
, 1);
352 old_cost
= this_cost
, did_change
= 1;
359 /* Try to replace operands in INSN with equivalent values that are already
360 in registers. This can be viewed as optional reloading.
362 For each non-register operand in the insn, see if any hard regs are
363 known to be equivalent to that operand. Record the alternatives which
364 can accept these hard registers. Among all alternatives, select the
365 ones which are better or equal to the one currently matching, where
366 "better" is in terms of '?' and '!' constraints. Among the remaining
367 alternatives, select the one which replaces most operands with
371 reload_cse_simplify_operands (rtx_insn
*insn
, rtx testreg
)
375 /* For each operand, all registers that are equivalent to it. */
376 HARD_REG_SET equiv_regs
[MAX_RECOG_OPERANDS
];
378 const char *constraints
[MAX_RECOG_OPERANDS
];
380 /* Vector recording how bad an alternative is. */
381 int *alternative_reject
;
382 /* Vector recording how many registers can be introduced by choosing
384 int *alternative_nregs
;
385 /* Array of vectors recording, for each operand and each alternative,
386 which hard register to substitute, or -1 if the operand should be
388 int *op_alt_regno
[MAX_RECOG_OPERANDS
];
389 /* Array of alternatives, sorted in order of decreasing desirability. */
390 int *alternative_order
;
392 extract_constrain_insn (insn
);
394 if (recog_data
.n_alternatives
== 0 || recog_data
.n_operands
== 0)
397 alternative_reject
= XALLOCAVEC (int, recog_data
.n_alternatives
);
398 alternative_nregs
= XALLOCAVEC (int, recog_data
.n_alternatives
);
399 alternative_order
= XALLOCAVEC (int, recog_data
.n_alternatives
);
400 memset (alternative_reject
, 0, recog_data
.n_alternatives
* sizeof (int));
401 memset (alternative_nregs
, 0, recog_data
.n_alternatives
* sizeof (int));
403 /* For each operand, find out which regs are equivalent. */
404 for (i
= 0; i
< recog_data
.n_operands
; i
++)
407 struct elt_loc_list
*l
;
410 CLEAR_HARD_REG_SET (equiv_regs
[i
]);
412 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
413 right, so avoid the problem here. Likewise if we have a constant
414 and the insn pattern doesn't tell us the mode we need. */
415 if (LABEL_P (recog_data
.operand
[i
])
416 || (CONSTANT_P (recog_data
.operand
[i
])
417 && recog_data
.operand_mode
[i
] == VOIDmode
))
420 op
= recog_data
.operand
[i
];
422 && GET_MODE_BITSIZE (GET_MODE (op
)) < BITS_PER_WORD
423 && LOAD_EXTEND_OP (GET_MODE (op
)) != UNKNOWN
)
425 rtx set
= single_set (insn
);
427 /* We might have multiple sets, some of which do implicit
428 extension. Punt on this for now. */
431 /* If the destination is also a MEM or a STRICT_LOW_PART, no
433 Also, if there is an explicit extension, we don't have to
434 worry about an implicit one. */
435 else if (MEM_P (SET_DEST (set
))
436 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
437 || GET_CODE (SET_SRC (set
)) == ZERO_EXTEND
438 || GET_CODE (SET_SRC (set
)) == SIGN_EXTEND
)
439 ; /* Continue ordinary processing. */
440 #ifdef CANNOT_CHANGE_MODE_CLASS
441 /* If the register cannot change mode to word_mode, it follows that
442 it cannot have been used in word_mode. */
443 else if (REG_P (SET_DEST (set
))
444 && CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set
)),
446 REGNO_REG_CLASS (REGNO (SET_DEST (set
)))))
447 ; /* Continue ordinary processing. */
449 /* If this is a straight load, make the extension explicit. */
450 else if (REG_P (SET_DEST (set
))
451 && recog_data
.n_operands
== 2
452 && SET_SRC (set
) == op
453 && SET_DEST (set
) == recog_data
.operand
[1-i
])
455 validate_change (insn
, recog_data
.operand_loc
[i
],
456 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (op
)),
459 validate_change (insn
, recog_data
.operand_loc
[1-i
],
460 gen_rtx_REG (word_mode
, REGNO (SET_DEST (set
))),
462 if (! apply_change_group ())
464 return reload_cse_simplify_operands (insn
, testreg
);
467 /* ??? There might be arithmetic operations with memory that are
468 safe to optimize, but is it worth the trouble? */
472 if (side_effects_p (op
))
474 v
= cselib_lookup (op
, recog_data
.operand_mode
[i
], 0, VOIDmode
);
478 for (l
= v
->locs
; l
; l
= l
->next
)
480 SET_HARD_REG_BIT (equiv_regs
[i
], REGNO (l
->loc
));
483 alternative_mask preferred
= get_preferred_alternatives (insn
);
484 for (i
= 0; i
< recog_data
.n_operands
; i
++)
490 op_alt_regno
[i
] = XALLOCAVEC (int, recog_data
.n_alternatives
);
491 for (j
= 0; j
< recog_data
.n_alternatives
; j
++)
492 op_alt_regno
[i
][j
] = -1;
494 p
= constraints
[i
] = recog_data
.constraints
[i
];
495 mode
= recog_data
.operand_mode
[i
];
497 /* Add the reject values for each alternative given by the constraints
506 alternative_reject
[j
] += 3;
508 alternative_reject
[j
] += 300;
511 /* We won't change operands which are already registers. We
512 also don't want to modify output operands. */
513 regno
= true_regnum (recog_data
.operand
[i
]);
515 || constraints
[i
][0] == '='
516 || constraints
[i
][0] == '+')
519 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
521 enum reg_class rclass
= NO_REGS
;
523 if (! TEST_HARD_REG_BIT (equiv_regs
[i
], regno
))
526 set_mode_and_regno (testreg
, mode
, regno
);
528 /* We found a register equal to this operand. Now look for all
529 alternatives that can accept this register and have not been
530 assigned a register they can use yet. */
540 rclass
= reg_class_subunion
[rclass
][GENERAL_REGS
];
545 = (reg_class_subunion
547 [reg_class_for_constraint (lookup_constraint (p
))]);
551 /* See if REGNO fits this alternative, and set it up as the
552 replacement register if we don't have one for this
553 alternative yet and the operand being replaced is not
554 a cheap CONST_INT. */
555 if (op_alt_regno
[i
][j
] == -1
556 && TEST_BIT (preferred
, j
)
557 && reg_fits_class_p (testreg
, rclass
, 0, mode
)
558 && (!CONST_INT_P (recog_data
.operand
[i
])
559 || (set_src_cost (recog_data
.operand
[i
], mode
,
560 optimize_bb_for_speed_p
561 (BLOCK_FOR_INSN (insn
)))
562 > set_src_cost (testreg
, mode
,
563 optimize_bb_for_speed_p
564 (BLOCK_FOR_INSN (insn
))))))
566 alternative_nregs
[j
]++;
567 op_alt_regno
[i
][j
] = regno
;
573 p
+= CONSTRAINT_LEN (c
, p
);
581 /* Record all alternatives which are better or equal to the currently
582 matching one in the alternative_order array. */
583 for (i
= j
= 0; i
< recog_data
.n_alternatives
; i
++)
584 if (alternative_reject
[i
] <= alternative_reject
[which_alternative
])
585 alternative_order
[j
++] = i
;
586 recog_data
.n_alternatives
= j
;
588 /* Sort it. Given a small number of alternatives, a dumb algorithm
589 won't hurt too much. */
590 for (i
= 0; i
< recog_data
.n_alternatives
- 1; i
++)
593 int best_reject
= alternative_reject
[alternative_order
[i
]];
594 int best_nregs
= alternative_nregs
[alternative_order
[i
]];
596 for (j
= i
+ 1; j
< recog_data
.n_alternatives
; j
++)
598 int this_reject
= alternative_reject
[alternative_order
[j
]];
599 int this_nregs
= alternative_nregs
[alternative_order
[j
]];
601 if (this_reject
< best_reject
602 || (this_reject
== best_reject
&& this_nregs
> best_nregs
))
605 best_reject
= this_reject
;
606 best_nregs
= this_nregs
;
610 std::swap (alternative_order
[best
], alternative_order
[i
]);
613 /* Substitute the operands as determined by op_alt_regno for the best
615 j
= alternative_order
[0];
617 for (i
= 0; i
< recog_data
.n_operands
; i
++)
619 machine_mode mode
= recog_data
.operand_mode
[i
];
620 if (op_alt_regno
[i
][j
] == -1)
623 validate_change (insn
, recog_data
.operand_loc
[i
],
624 gen_rtx_REG (mode
, op_alt_regno
[i
][j
]), 1);
627 for (i
= recog_data
.n_dups
- 1; i
>= 0; i
--)
629 int op
= recog_data
.dup_num
[i
];
630 machine_mode mode
= recog_data
.operand_mode
[op
];
632 if (op_alt_regno
[op
][j
] == -1)
635 validate_change (insn
, recog_data
.dup_loc
[i
],
636 gen_rtx_REG (mode
, op_alt_regno
[op
][j
]), 1);
639 return apply_change_group ();
642 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
644 This code might also be useful when reload gave up on reg+reg addressing
645 because of clashes between the return register and INDEX_REG_CLASS. */
647 /* The maximum number of uses of a register we can keep track of to
648 replace them with reg+reg addressing. */
649 #define RELOAD_COMBINE_MAX_USES 16
651 /* Describes a recorded use of a register. */
654 /* The insn where a register has been used. */
656 /* Points to the memory reference enclosing the use, if any, NULL_RTX
659 /* Location of the register within INSN. */
661 /* The reverse uid of the insn. */
665 /* If the register is used in some unknown fashion, USE_INDEX is negative.
666 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
667 indicates where it is first set or clobbered.
668 Otherwise, USE_INDEX is the index of the last encountered use of the
669 register (which is first among these we have seen since we scan backwards).
670 USE_RUID indicates the first encountered, i.e. last, of these uses.
671 If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS
672 with a constant offset; OFFSET contains this constant in that case.
673 STORE_RUID is always meaningful if we only want to use a value in a
674 register in a different place: it denotes the next insn in the insn
675 stream (i.e. the last encountered) that sets or clobbers the register.
676 REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */
679 struct reg_use reg_use
[RELOAD_COMBINE_MAX_USES
];
685 bool all_offsets_match
;
686 } reg_state
[FIRST_PSEUDO_REGISTER
];
688 /* Reverse linear uid. This is increased in reload_combine while scanning
689 the instructions from last to first. It is used to set last_label_ruid
690 and the store_ruid / use_ruid fields in reg_state. */
691 static int reload_combine_ruid
;
693 /* The RUID of the last label we encountered in reload_combine. */
694 static int last_label_ruid
;
696 /* The RUID of the last jump we encountered in reload_combine. */
697 static int last_jump_ruid
;
699 /* The register numbers of the first and last index register. A value of
700 -1 in LAST_INDEX_REG indicates that we've previously computed these
701 values and found no suitable index registers. */
702 static int first_index_reg
= -1;
703 static int last_index_reg
;
705 #define LABEL_LIVE(LABEL) \
706 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
708 /* Subroutine of reload_combine_split_ruids, called to fix up a single
709 ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */
712 reload_combine_split_one_ruid (int *pruid
, int split_ruid
)
714 if (*pruid
> split_ruid
)
718 /* Called when we insert a new insn in a position we've already passed in
719 the scan. Examine all our state, increasing all ruids that are higher
720 than SPLIT_RUID by one in order to make room for a new insn. */
723 reload_combine_split_ruids (int split_ruid
)
727 reload_combine_split_one_ruid (&reload_combine_ruid
, split_ruid
);
728 reload_combine_split_one_ruid (&last_label_ruid
, split_ruid
);
729 reload_combine_split_one_ruid (&last_jump_ruid
, split_ruid
);
731 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
733 int j
, idx
= reg_state
[i
].use_index
;
734 reload_combine_split_one_ruid (®_state
[i
].use_ruid
, split_ruid
);
735 reload_combine_split_one_ruid (®_state
[i
].store_ruid
, split_ruid
);
736 reload_combine_split_one_ruid (®_state
[i
].real_store_ruid
,
740 for (j
= idx
; j
< RELOAD_COMBINE_MAX_USES
; j
++)
742 reload_combine_split_one_ruid (®_state
[i
].reg_use
[j
].ruid
,
748 /* Called when we are about to rescan a previously encountered insn with
749 reload_combine_note_use after modifying some part of it. This clears all
750 information about uses in that particular insn. */
753 reload_combine_purge_insn_uses (rtx_insn
*insn
)
757 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
759 int j
, k
, idx
= reg_state
[i
].use_index
;
762 j
= k
= RELOAD_COMBINE_MAX_USES
;
765 if (reg_state
[i
].reg_use
[j
].insn
!= insn
)
769 reg_state
[i
].reg_use
[k
] = reg_state
[i
].reg_use
[j
];
772 reg_state
[i
].use_index
= k
;
776 /* Called when we need to forget about all uses of REGNO after an insn
777 which is identified by RUID. */
780 reload_combine_purge_reg_uses_after_ruid (unsigned regno
, int ruid
)
782 int j
, k
, idx
= reg_state
[regno
].use_index
;
785 j
= k
= RELOAD_COMBINE_MAX_USES
;
788 if (reg_state
[regno
].reg_use
[j
].ruid
>= ruid
)
792 reg_state
[regno
].reg_use
[k
] = reg_state
[regno
].reg_use
[j
];
795 reg_state
[regno
].use_index
= k
;
798 /* Find the use of REGNO with the ruid that is highest among those
799 lower than RUID_LIMIT, and return it if it is the only use of this
800 reg in the insn. Return NULL otherwise. */
802 static struct reg_use
*
803 reload_combine_closest_single_use (unsigned regno
, int ruid_limit
)
805 int i
, best_ruid
= 0;
806 int use_idx
= reg_state
[regno
].use_index
;
807 struct reg_use
*retval
;
812 for (i
= use_idx
; i
< RELOAD_COMBINE_MAX_USES
; i
++)
814 struct reg_use
*use
= reg_state
[regno
].reg_use
+ i
;
815 int this_ruid
= use
->ruid
;
816 if (this_ruid
>= ruid_limit
)
818 if (this_ruid
> best_ruid
)
820 best_ruid
= this_ruid
;
823 else if (this_ruid
== best_ruid
)
826 if (last_label_ruid
>= best_ruid
)
831 /* After we've moved an add insn, fix up any debug insns that occur
832 between the old location of the add and the new location. REG is
833 the destination register of the add insn; REPLACEMENT is the
834 SET_SRC of the add. FROM and TO specify the range in which we
835 should make this change on debug insns. */
838 fixup_debug_insns (rtx reg
, rtx replacement
, rtx_insn
*from
, rtx_insn
*to
)
841 for (insn
= from
; insn
!= to
; insn
= NEXT_INSN (insn
))
845 if (!DEBUG_INSN_P (insn
))
848 t
= INSN_VAR_LOCATION_LOC (insn
);
849 t
= simplify_replace_rtx (t
, reg
, replacement
);
850 validate_change (insn
, &INSN_VAR_LOCATION_LOC (insn
), t
, 0);
854 /* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG
855 with SRC in the insn described by USE, taking costs into account. Return
856 true if we made the replacement. */
859 try_replace_in_use (struct reg_use
*use
, rtx reg
, rtx src
)
861 rtx_insn
*use_insn
= use
->insn
;
862 rtx mem
= use
->containing_mem
;
863 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn
));
867 addr_space_t as
= MEM_ADDR_SPACE (mem
);
868 rtx oldaddr
= XEXP (mem
, 0);
869 rtx newaddr
= NULL_RTX
;
870 int old_cost
= address_cost (oldaddr
, GET_MODE (mem
), as
, speed
);
873 newaddr
= simplify_replace_rtx (oldaddr
, reg
, src
);
874 if (memory_address_addr_space_p (GET_MODE (mem
), newaddr
, as
))
876 XEXP (mem
, 0) = newaddr
;
877 new_cost
= address_cost (newaddr
, GET_MODE (mem
), as
, speed
);
878 XEXP (mem
, 0) = oldaddr
;
879 if (new_cost
<= old_cost
880 && validate_change (use_insn
,
881 &XEXP (mem
, 0), newaddr
, 0))
887 rtx new_set
= single_set (use_insn
);
889 && REG_P (SET_DEST (new_set
))
890 && GET_CODE (SET_SRC (new_set
)) == PLUS
891 && REG_P (XEXP (SET_SRC (new_set
), 0))
892 && CONSTANT_P (XEXP (SET_SRC (new_set
), 1)))
895 machine_mode mode
= GET_MODE (SET_DEST (new_set
));
896 int old_cost
= set_src_cost (SET_SRC (new_set
), mode
, speed
);
898 gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set
), 0), reg
));
899 new_src
= simplify_replace_rtx (SET_SRC (new_set
), reg
, src
);
901 if (set_src_cost (new_src
, mode
, speed
) <= old_cost
902 && validate_change (use_insn
, &SET_SRC (new_set
),
910 /* Called by reload_combine when scanning INSN. This function tries to detect
911 patterns where a constant is added to a register, and the result is used
913 Return true if no further processing is needed on INSN; false if it wasn't
914 recognized and should be handled normally. */
917 reload_combine_recognize_const_pattern (rtx_insn
*insn
)
919 int from_ruid
= reload_combine_ruid
;
920 rtx set
, pat
, reg
, src
, addreg
;
924 rtx_insn
*add_moved_after_insn
= NULL
;
925 int add_moved_after_ruid
= 0;
926 int clobbered_regno
= -1;
928 set
= single_set (insn
);
932 reg
= SET_DEST (set
);
935 || REG_NREGS (reg
) != 1
936 || GET_MODE (reg
) != Pmode
937 || reg
== stack_pointer_rtx
)
942 /* We look for a REG1 = REG2 + CONSTANT insn, followed by either
943 uses of REG1 inside an address, or inside another add insn. If
944 possible and profitable, merge the addition into subsequent
946 if (GET_CODE (src
) != PLUS
947 || !REG_P (XEXP (src
, 0))
948 || !CONSTANT_P (XEXP (src
, 1)))
951 addreg
= XEXP (src
, 0);
952 must_move_add
= rtx_equal_p (reg
, addreg
);
954 pat
= PATTERN (insn
);
955 if (must_move_add
&& set
!= pat
)
957 /* We have to be careful when moving the add; apart from the
958 single_set there may also be clobbers. Recognize one special
959 case, that of one clobber alongside the set (likely a clobber
960 of the CC register). */
961 gcc_assert (GET_CODE (PATTERN (insn
)) == PARALLEL
);
962 if (XVECLEN (pat
, 0) != 2 || XVECEXP (pat
, 0, 0) != set
963 || GET_CODE (XVECEXP (pat
, 0, 1)) != CLOBBER
964 || !REG_P (XEXP (XVECEXP (pat
, 0, 1), 0)))
966 clobbered_regno
= REGNO (XEXP (XVECEXP (pat
, 0, 1), 0));
971 use
= reload_combine_closest_single_use (regno
, from_ruid
);
974 /* Start the search for the next use from here. */
975 from_ruid
= use
->ruid
;
977 if (use
&& GET_MODE (*use
->usep
) == Pmode
)
979 bool delete_add
= false;
980 rtx_insn
*use_insn
= use
->insn
;
981 int use_ruid
= use
->ruid
;
983 /* Avoid moving the add insn past a jump. */
984 if (must_move_add
&& use_ruid
<= last_jump_ruid
)
987 /* If the add clobbers another hard reg in parallel, don't move
988 it past a real set of this hard reg. */
989 if (must_move_add
&& clobbered_regno
>= 0
990 && reg_state
[clobbered_regno
].real_store_ruid
>= use_ruid
)
993 /* Do not separate cc0 setter and cc0 user on HAVE_cc0 targets. */
994 if (HAVE_cc0
&& must_move_add
&& sets_cc0_p (PATTERN (use_insn
)))
997 gcc_assert (reg_state
[regno
].store_ruid
<= use_ruid
);
998 /* Avoid moving a use of ADDREG past a point where it is stored. */
999 if (reg_state
[REGNO (addreg
)].store_ruid
> use_ruid
)
1002 /* We also must not move the addition past an insn that sets
1003 the same register, unless we can combine two add insns. */
1004 if (must_move_add
&& reg_state
[regno
].store_ruid
== use_ruid
)
1006 if (use
->containing_mem
== NULL_RTX
)
1012 if (try_replace_in_use (use
, reg
, src
))
1014 reload_combine_purge_insn_uses (use_insn
);
1015 reload_combine_note_use (&PATTERN (use_insn
), use_insn
,
1016 use_ruid
, NULL_RTX
);
1020 fixup_debug_insns (reg
, src
, insn
, use_insn
);
1026 add_moved_after_insn
= use_insn
;
1027 add_moved_after_ruid
= use_ruid
;
1032 /* If we get here, we couldn't handle this use. */
1038 if (!must_move_add
|| add_moved_after_insn
== NULL_RTX
)
1039 /* Process the add normally. */
1042 fixup_debug_insns (reg
, src
, insn
, add_moved_after_insn
);
1044 reorder_insns (insn
, insn
, add_moved_after_insn
);
1045 reload_combine_purge_reg_uses_after_ruid (regno
, add_moved_after_ruid
);
1046 reload_combine_split_ruids (add_moved_after_ruid
- 1);
1047 reload_combine_note_use (&PATTERN (insn
), insn
,
1048 add_moved_after_ruid
, NULL_RTX
);
1049 reg_state
[regno
].store_ruid
= add_moved_after_ruid
;
1054 /* Called by reload_combine when scanning INSN. Try to detect a pattern we
1055 can handle and improve. Return true if no further processing is needed on
1056 INSN; false if it wasn't recognized and should be handled normally. */
1059 reload_combine_recognize_pattern (rtx_insn
*insn
)
1063 set
= single_set (insn
);
1064 if (set
== NULL_RTX
)
1067 reg
= SET_DEST (set
);
1068 src
= SET_SRC (set
);
1069 if (!REG_P (reg
) || REG_NREGS (reg
) != 1)
1072 unsigned int regno
= REGNO (reg
);
1073 machine_mode mode
= GET_MODE (reg
);
1075 if (reg_state
[regno
].use_index
< 0
1076 || reg_state
[regno
].use_index
>= RELOAD_COMBINE_MAX_USES
)
1079 for (int i
= reg_state
[regno
].use_index
;
1080 i
< RELOAD_COMBINE_MAX_USES
; i
++)
1082 struct reg_use
*use
= reg_state
[regno
].reg_use
+ i
;
1083 if (GET_MODE (*use
->usep
) != mode
)
1087 /* Look for (set (REGX) (CONST_INT))
1088 (set (REGX) (PLUS (REGX) (REGY)))
1090 ... (MEM (REGX)) ...
1092 (set (REGZ) (CONST_INT))
1094 ... (MEM (PLUS (REGZ) (REGY)))... .
1096 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
1097 and that we know all uses of REGX before it dies.
1098 Also, explicitly check that REGX != REGY; our life information
1099 does not yet show whether REGY changes in this insn. */
1101 if (GET_CODE (src
) == PLUS
1102 && reg_state
[regno
].all_offsets_match
1103 && last_index_reg
!= -1
1104 && REG_P (XEXP (src
, 1))
1105 && rtx_equal_p (XEXP (src
, 0), reg
)
1106 && !rtx_equal_p (XEXP (src
, 1), reg
)
1107 && last_label_ruid
< reg_state
[regno
].use_ruid
)
1109 rtx base
= XEXP (src
, 1);
1110 rtx_insn
*prev
= prev_nonnote_nondebug_insn (insn
);
1111 rtx prev_set
= prev
? single_set (prev
) : NULL_RTX
;
1112 rtx index_reg
= NULL_RTX
;
1113 rtx reg_sum
= NULL_RTX
;
1116 /* Now we need to set INDEX_REG to an index register (denoted as
1117 REGZ in the illustration above) and REG_SUM to the expression
1118 register+register that we want to use to substitute uses of REG
1119 (typically in MEMs) with. First check REG and BASE for being
1120 index registers; we can use them even if they are not dead. */
1121 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], regno
)
1122 || TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
],
1130 /* Otherwise, look for a free index register. Since we have
1131 checked above that neither REG nor BASE are index registers,
1132 if we find anything at all, it will be different from these
1134 for (i
= first_index_reg
; i
<= last_index_reg
; i
++)
1136 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], i
)
1137 && reg_state
[i
].use_index
== RELOAD_COMBINE_MAX_USES
1138 && reg_state
[i
].store_ruid
<= reg_state
[regno
].use_ruid
1139 && (call_used_regs
[i
] || df_regs_ever_live_p (i
))
1140 && (!frame_pointer_needed
|| i
!= HARD_FRAME_POINTER_REGNUM
)
1141 && !fixed_regs
[i
] && !global_regs
[i
]
1142 && hard_regno_nregs
[i
][GET_MODE (reg
)] == 1
1143 && targetm
.hard_regno_scratch_ok (i
))
1145 index_reg
= gen_rtx_REG (GET_MODE (reg
), i
);
1146 reg_sum
= gen_rtx_PLUS (GET_MODE (reg
), index_reg
, base
);
1152 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
1153 (REGY), i.e. BASE, is not clobbered before the last use we'll
1157 && CONST_INT_P (SET_SRC (prev_set
))
1158 && rtx_equal_p (SET_DEST (prev_set
), reg
)
1159 && (reg_state
[REGNO (base
)].store_ruid
1160 <= reg_state
[regno
].use_ruid
))
1162 /* Change destination register and, if necessary, the constant
1163 value in PREV, the constant loading instruction. */
1164 validate_change (prev
, &SET_DEST (prev_set
), index_reg
, 1);
1165 if (reg_state
[regno
].offset
!= const0_rtx
)
1166 validate_change (prev
,
1167 &SET_SRC (prev_set
),
1168 GEN_INT (INTVAL (SET_SRC (prev_set
))
1169 + INTVAL (reg_state
[regno
].offset
)),
1172 /* Now for every use of REG that we have recorded, replace REG
1174 for (i
= reg_state
[regno
].use_index
;
1175 i
< RELOAD_COMBINE_MAX_USES
; i
++)
1176 validate_unshare_change (reg_state
[regno
].reg_use
[i
].insn
,
1177 reg_state
[regno
].reg_use
[i
].usep
,
1178 /* Each change must have its own
1182 if (apply_change_group ())
1184 struct reg_use
*lowest_ruid
= NULL
;
1186 /* For every new use of REG_SUM, we have to record the use
1187 of BASE therein, i.e. operand 1. */
1188 for (i
= reg_state
[regno
].use_index
;
1189 i
< RELOAD_COMBINE_MAX_USES
; i
++)
1191 struct reg_use
*use
= reg_state
[regno
].reg_use
+ i
;
1192 reload_combine_note_use (&XEXP (*use
->usep
, 1), use
->insn
,
1193 use
->ruid
, use
->containing_mem
);
1194 if (lowest_ruid
== NULL
|| use
->ruid
< lowest_ruid
->ruid
)
1198 fixup_debug_insns (reg
, reg_sum
, insn
, lowest_ruid
->insn
);
1200 /* Delete the reg-reg addition. */
1203 if (reg_state
[regno
].offset
!= const0_rtx
)
1204 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
1206 remove_reg_equal_equiv_notes (prev
);
1208 reg_state
[regno
].use_index
= RELOAD_COMBINE_MAX_USES
;
1217 reload_combine (void)
1219 rtx_insn
*insn
, *prev
;
1222 int min_labelno
, n_labels
;
1223 HARD_REG_SET ever_live_at_start
, *label_live
;
1225 /* To avoid wasting too much time later searching for an index register,
1226 determine the minimum and maximum index register numbers. */
1227 if (INDEX_REG_CLASS
== NO_REGS
)
1228 last_index_reg
= -1;
1229 else if (first_index_reg
== -1 && last_index_reg
== 0)
1231 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1232 if (TEST_HARD_REG_BIT (reg_class_contents
[INDEX_REG_CLASS
], r
))
1234 if (first_index_reg
== -1)
1235 first_index_reg
= r
;
1240 /* If no index register is available, we can quit now. Set LAST_INDEX_REG
1241 to -1 so we'll know to quit early the next time we get here. */
1242 if (first_index_reg
== -1)
1244 last_index_reg
= -1;
1249 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
1250 information is a bit fuzzy immediately after reload, but it's
1251 still good enough to determine which registers are live at a jump
1253 min_labelno
= get_first_label_num ();
1254 n_labels
= max_label_num () - min_labelno
;
1255 label_live
= XNEWVEC (HARD_REG_SET
, n_labels
);
1256 CLEAR_HARD_REG_SET (ever_live_at_start
);
1258 FOR_EACH_BB_REVERSE_FN (bb
, cfun
)
1260 insn
= BB_HEAD (bb
);
1264 bitmap live_in
= df_get_live_in (bb
);
1266 REG_SET_TO_HARD_REG_SET (live
, live_in
);
1267 compute_use_by_pseudos (&live
, live_in
);
1268 COPY_HARD_REG_SET (LABEL_LIVE (insn
), live
);
1269 IOR_HARD_REG_SET (ever_live_at_start
, live
);
1273 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
1274 last_label_ruid
= last_jump_ruid
= reload_combine_ruid
= 0;
1275 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1277 reg_state
[r
].store_ruid
= 0;
1278 reg_state
[r
].real_store_ruid
= 0;
1280 reg_state
[r
].use_index
= -1;
1282 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1285 for (insn
= get_last_insn (); insn
; insn
= prev
)
1287 bool control_flow_insn
;
1290 prev
= PREV_INSN (insn
);
1292 /* We cannot do our optimization across labels. Invalidating all the use
1293 information we have would be costly, so we just note where the label
1294 is and then later disable any optimization that would cross it. */
1296 last_label_ruid
= reload_combine_ruid
;
1297 else if (BARRIER_P (insn
))
1299 /* Crossing a barrier resets all the use information. */
1300 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1301 if (! fixed_regs
[r
])
1302 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1304 else if (INSN_P (insn
) && volatile_insn_p (PATTERN (insn
)))
1305 /* Optimizations across insns being marked as volatile must be
1306 prevented. All the usage information is invalidated
1308 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1310 && reg_state
[r
].use_index
!= RELOAD_COMBINE_MAX_USES
)
1311 reg_state
[r
].use_index
= -1;
1313 if (! NONDEBUG_INSN_P (insn
))
1316 reload_combine_ruid
++;
1318 control_flow_insn
= control_flow_insn_p (insn
);
1319 if (control_flow_insn
)
1320 last_jump_ruid
= reload_combine_ruid
;
1322 if (reload_combine_recognize_const_pattern (insn
)
1323 || reload_combine_recognize_pattern (insn
))
1326 note_stores (PATTERN (insn
), reload_combine_note_store
, NULL
);
1331 HARD_REG_SET used_regs
;
1333 get_call_reg_set_usage (insn
, &used_regs
, call_used_reg_set
);
1335 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1336 if (TEST_HARD_REG_BIT (used_regs
, r
))
1338 reg_state
[r
].use_index
= RELOAD_COMBINE_MAX_USES
;
1339 reg_state
[r
].store_ruid
= reload_combine_ruid
;
1342 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
;
1343 link
= XEXP (link
, 1))
1345 rtx setuse
= XEXP (link
, 0);
1346 rtx usage_rtx
= XEXP (setuse
, 0);
1347 if ((GET_CODE (setuse
) == USE
|| GET_CODE (setuse
) == CLOBBER
)
1348 && REG_P (usage_rtx
))
1350 unsigned int end_regno
= END_REGNO (usage_rtx
);
1351 for (unsigned int i
= REGNO (usage_rtx
); i
< end_regno
; ++i
)
1352 if (GET_CODE (XEXP (link
, 0)) == CLOBBER
)
1354 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
1355 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1358 reg_state
[i
].use_index
= -1;
1363 if (control_flow_insn
&& !ANY_RETURN_P (PATTERN (insn
)))
1365 /* Non-spill registers might be used at the call destination in
1366 some unknown fashion, so we have to mark the unknown use. */
1369 if ((condjump_p (insn
) || condjump_in_parallel_p (insn
))
1370 && JUMP_LABEL (insn
))
1372 if (ANY_RETURN_P (JUMP_LABEL (insn
)))
1375 live
= &LABEL_LIVE (JUMP_LABEL (insn
));
1378 live
= &ever_live_at_start
;
1381 for (r
= 0; r
< FIRST_PSEUDO_REGISTER
; r
++)
1382 if (TEST_HARD_REG_BIT (*live
, r
))
1383 reg_state
[r
].use_index
= -1;
1386 reload_combine_note_use (&PATTERN (insn
), insn
, reload_combine_ruid
,
1389 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
1391 if (REG_NOTE_KIND (note
) == REG_INC
&& REG_P (XEXP (note
, 0)))
1393 int regno
= REGNO (XEXP (note
, 0));
1394 reg_state
[regno
].store_ruid
= reload_combine_ruid
;
1395 reg_state
[regno
].real_store_ruid
= reload_combine_ruid
;
1396 reg_state
[regno
].use_index
= -1;
1404 /* Check if DST is a register or a subreg of a register; if it is,
1405 update store_ruid, real_store_ruid and use_index in the reg_state
1406 structure accordingly. Called via note_stores from reload_combine. */
1409 reload_combine_note_store (rtx dst
, const_rtx set
, void *data ATTRIBUTE_UNUSED
)
1413 machine_mode mode
= GET_MODE (dst
);
1415 if (GET_CODE (dst
) == SUBREG
)
1417 regno
= subreg_regno_offset (REGNO (SUBREG_REG (dst
)),
1418 GET_MODE (SUBREG_REG (dst
)),
1421 dst
= SUBREG_REG (dst
);
1424 /* Some targets do argument pushes without adding REG_INC notes. */
1428 dst
= XEXP (dst
, 0);
1429 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_INC
1430 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
1431 || GET_CODE (dst
) == PRE_MODIFY
|| GET_CODE (dst
) == POST_MODIFY
)
1433 unsigned int end_regno
= END_REGNO (XEXP (dst
, 0));
1434 for (unsigned int i
= REGNO (XEXP (dst
, 0)); i
< end_regno
; ++i
)
1436 /* We could probably do better, but for now mark the register
1437 as used in an unknown fashion and set/clobbered at this
1439 reg_state
[i
].use_index
= -1;
1440 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1441 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1450 regno
+= REGNO (dst
);
1452 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
1453 careful with registers / register parts that are not full words.
1454 Similarly for ZERO_EXTRACT. */
1455 if (GET_CODE (SET_DEST (set
)) == ZERO_EXTRACT
1456 || GET_CODE (SET_DEST (set
)) == STRICT_LOW_PART
)
1458 for (i
= hard_regno_nregs
[regno
][mode
] - 1 + regno
; i
>= regno
; i
--)
1460 reg_state
[i
].use_index
= -1;
1461 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1462 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1467 for (i
= hard_regno_nregs
[regno
][mode
] - 1 + regno
; i
>= regno
; i
--)
1469 reg_state
[i
].store_ruid
= reload_combine_ruid
;
1470 if (GET_CODE (set
) == SET
)
1471 reg_state
[i
].real_store_ruid
= reload_combine_ruid
;
1472 reg_state
[i
].use_index
= RELOAD_COMBINE_MAX_USES
;
1477 /* XP points to a piece of rtl that has to be checked for any uses of
1479 *XP is the pattern of INSN, or a part of it.
1480 Called from reload_combine, and recursively by itself. */
1482 reload_combine_note_use (rtx
*xp
, rtx_insn
*insn
, int ruid
, rtx containing_mem
)
1485 enum rtx_code code
= x
->code
;
1488 rtx offset
= const0_rtx
; /* For the REG case below. */
1493 if (REG_P (SET_DEST (x
)))
1495 reload_combine_note_use (&SET_SRC (x
), insn
, ruid
, NULL_RTX
);
1501 /* If this is the USE of a return value, we can't change it. */
1502 if (REG_P (XEXP (x
, 0)) && REG_FUNCTION_VALUE_P (XEXP (x
, 0)))
1504 /* Mark the return register as used in an unknown fashion. */
1505 rtx reg
= XEXP (x
, 0);
1506 unsigned int end_regno
= END_REGNO (reg
);
1507 for (unsigned int regno
= REGNO (reg
); regno
< end_regno
; ++regno
)
1508 reg_state
[regno
].use_index
= -1;
1514 if (REG_P (SET_DEST (x
)))
1516 /* No spurious CLOBBERs of pseudo registers may remain. */
1517 gcc_assert (REGNO (SET_DEST (x
)) < FIRST_PSEUDO_REGISTER
);
1523 /* We are interested in (plus (reg) (const_int)) . */
1524 if (!REG_P (XEXP (x
, 0))
1525 || !CONST_INT_P (XEXP (x
, 1)))
1527 offset
= XEXP (x
, 1);
1532 int regno
= REGNO (x
);
1536 /* No spurious USEs of pseudo registers may remain. */
1537 gcc_assert (regno
< FIRST_PSEUDO_REGISTER
);
1539 nregs
= REG_NREGS (x
);
1541 /* We can't substitute into multi-hard-reg uses. */
1544 while (--nregs
>= 0)
1545 reg_state
[regno
+ nregs
].use_index
= -1;
1549 /* We may be called to update uses in previously seen insns.
1550 Don't add uses beyond the last store we saw. */
1551 if (ruid
< reg_state
[regno
].store_ruid
)
1554 /* If this register is already used in some unknown fashion, we
1556 If we decrement the index from zero to -1, we can't store more
1557 uses, so this register becomes used in an unknown fashion. */
1558 use_index
= --reg_state
[regno
].use_index
;
1562 if (use_index
== RELOAD_COMBINE_MAX_USES
- 1)
1564 /* This is the first use of this register we have seen since we
1565 marked it as dead. */
1566 reg_state
[regno
].offset
= offset
;
1567 reg_state
[regno
].all_offsets_match
= true;
1568 reg_state
[regno
].use_ruid
= ruid
;
1572 if (reg_state
[regno
].use_ruid
> ruid
)
1573 reg_state
[regno
].use_ruid
= ruid
;
1575 if (! rtx_equal_p (offset
, reg_state
[regno
].offset
))
1576 reg_state
[regno
].all_offsets_match
= false;
1579 reg_state
[regno
].reg_use
[use_index
].insn
= insn
;
1580 reg_state
[regno
].reg_use
[use_index
].ruid
= ruid
;
1581 reg_state
[regno
].reg_use
[use_index
].containing_mem
= containing_mem
;
1582 reg_state
[regno
].reg_use
[use_index
].usep
= xp
;
1594 /* Recursively process the components of X. */
1595 fmt
= GET_RTX_FORMAT (code
);
1596 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1599 reload_combine_note_use (&XEXP (x
, i
), insn
, ruid
, containing_mem
);
1600 else if (fmt
[i
] == 'E')
1602 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1603 reload_combine_note_use (&XVECEXP (x
, i
, j
), insn
, ruid
,
1609 /* See if we can reduce the cost of a constant by replacing a move
1610 with an add. We track situations in which a register is set to a
1611 constant or to a register plus a constant. */
1612 /* We cannot do our optimization across labels. Invalidating all the
1613 information about register contents we have would be costly, so we
1614 use move2add_last_label_luid to note where the label is and then
1615 later disable any optimization that would cross it.
1616 reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n]
1617 are only valid if reg_set_luid[n] is greater than
1618 move2add_last_label_luid.
1619 For a set that established a new (potential) base register with
1620 non-constant value, we use move2add_luid from the place where the
1621 setting insn is encountered; registers based off that base then
1622 get the same reg_set_luid. Constants all get
1623 move2add_last_label_luid + 1 as their reg_set_luid. */
1624 static int reg_set_luid
[FIRST_PSEUDO_REGISTER
];
1626 /* If reg_base_reg[n] is negative, register n has been set to
1627 reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n].
1628 If reg_base_reg[n] is non-negative, register n has been set to the
1629 sum of reg_offset[n] and the value of register reg_base_reg[n]
1630 before reg_set_luid[n], calculated in mode reg_mode[n] .
1631 For multi-hard-register registers, all but the first one are
1632 recorded as BLKmode in reg_mode. Setting reg_mode to VOIDmode
1633 marks it as invalid. */
1634 static HOST_WIDE_INT reg_offset
[FIRST_PSEUDO_REGISTER
];
1635 static int reg_base_reg
[FIRST_PSEUDO_REGISTER
];
1636 static rtx reg_symbol_ref
[FIRST_PSEUDO_REGISTER
];
1637 static machine_mode reg_mode
[FIRST_PSEUDO_REGISTER
];
1639 /* move2add_luid is linearly increased while scanning the instructions
1640 from first to last. It is used to set reg_set_luid in
1641 reload_cse_move2add and move2add_note_store. */
1642 static int move2add_luid
;
1644 /* move2add_last_label_luid is set whenever a label is found. Labels
1645 invalidate all previously collected reg_offset data. */
1646 static int move2add_last_label_luid
;
1648 /* ??? We don't know how zero / sign extension is handled, hence we
1649 can't go from a narrower to a wider mode. */
1650 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
1651 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
1652 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
1653 && TRULY_NOOP_TRUNCATION_MODES_P (OUTMODE, INMODE)))
1655 /* Record that REG is being set to a value with the mode of REG. */
1658 move2add_record_mode (rtx reg
)
1661 machine_mode mode
= GET_MODE (reg
);
1663 if (GET_CODE (reg
) == SUBREG
)
1665 regno
= subreg_regno (reg
);
1666 nregs
= subreg_nregs (reg
);
1668 else if (REG_P (reg
))
1670 regno
= REGNO (reg
);
1671 nregs
= REG_NREGS (reg
);
1675 for (int i
= nregs
- 1; i
> 0; i
--)
1676 reg_mode
[regno
+ i
] = BLKmode
;
1677 reg_mode
[regno
] = mode
;
1680 /* Record that REG is being set to the sum of SYM and OFF. */
1683 move2add_record_sym_value (rtx reg
, rtx sym
, rtx off
)
1685 int regno
= REGNO (reg
);
1687 move2add_record_mode (reg
);
1688 reg_set_luid
[regno
] = move2add_luid
;
1689 reg_base_reg
[regno
] = -1;
1690 reg_symbol_ref
[regno
] = sym
;
1691 reg_offset
[regno
] = INTVAL (off
);
1694 /* Check if REGNO contains a valid value in MODE. */
1697 move2add_valid_value_p (int regno
, machine_mode mode
)
1699 if (reg_set_luid
[regno
] <= move2add_last_label_luid
)
1702 if (mode
!= reg_mode
[regno
])
1704 if (!MODES_OK_FOR_MOVE2ADD (mode
, reg_mode
[regno
]))
1706 /* The value loaded into regno in reg_mode[regno] is also valid in
1707 mode after truncation only if (REG:mode regno) is the lowpart of
1708 (REG:reg_mode[regno] regno). Now, for big endian, the starting
1709 regno of the lowpart might be different. */
1710 int s_off
= subreg_lowpart_offset (mode
, reg_mode
[regno
]);
1711 s_off
= subreg_regno_offset (regno
, reg_mode
[regno
], s_off
, mode
);
1713 /* We could in principle adjust regno, check reg_mode[regno] to be
1714 BLKmode, and return s_off to the caller (vs. -1 for failure),
1715 but we currently have no callers that could make use of this
1720 for (int i
= hard_regno_nregs
[regno
][mode
] - 1; i
> 0; i
--)
1721 if (reg_mode
[regno
+ i
] != BLKmode
)
1726 /* This function is called with INSN that sets REG to (SYM + OFF),
1727 while REG is known to already have value (SYM + offset).
1728 This function tries to change INSN into an add instruction
1729 (set (REG) (plus (REG) (OFF - offset))) using the known value.
1730 It also updates the information about REG's known value.
1731 Return true if we made a change. */
1734 move2add_use_add2_insn (rtx reg
, rtx sym
, rtx off
, rtx_insn
*insn
)
1736 rtx pat
= PATTERN (insn
);
1737 rtx src
= SET_SRC (pat
);
1738 int regno
= REGNO (reg
);
1739 rtx new_src
= gen_int_mode (UINTVAL (off
) - reg_offset
[regno
],
1741 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
1742 bool changed
= false;
1744 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1745 use (set (reg) (reg)) instead.
1746 We don't delete this insn, nor do we convert it into a
1747 note, to avoid losing register notes or the return
1748 value flag. jump2 already knows how to get rid of
1750 if (new_src
== const0_rtx
)
1752 /* If the constants are different, this is a
1753 truncation, that, if turned into (set (reg)
1754 (reg)), would be discarded. Maybe we should
1755 try a truncMN pattern? */
1756 if (INTVAL (off
) == reg_offset
[regno
])
1757 changed
= validate_change (insn
, &SET_SRC (pat
), reg
, 0);
1761 struct full_rtx_costs oldcst
, newcst
;
1762 rtx tem
= gen_rtx_PLUS (GET_MODE (reg
), reg
, new_src
);
1764 get_full_set_rtx_cost (pat
, &oldcst
);
1765 SET_SRC (pat
) = tem
;
1766 get_full_set_rtx_cost (pat
, &newcst
);
1767 SET_SRC (pat
) = src
;
1769 if (costs_lt_p (&newcst
, &oldcst
, speed
)
1770 && have_add2_insn (reg
, new_src
))
1771 changed
= validate_change (insn
, &SET_SRC (pat
), tem
, 0);
1772 else if (sym
== NULL_RTX
&& GET_MODE (reg
) != BImode
)
1774 machine_mode narrow_mode
;
1775 for (narrow_mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
1776 narrow_mode
!= VOIDmode
1777 && narrow_mode
!= GET_MODE (reg
);
1778 narrow_mode
= GET_MODE_WIDER_MODE (narrow_mode
))
1780 if (have_insn_for (STRICT_LOW_PART
, narrow_mode
)
1781 && ((reg_offset
[regno
] & ~GET_MODE_MASK (narrow_mode
))
1782 == (INTVAL (off
) & ~GET_MODE_MASK (narrow_mode
))))
1784 rtx narrow_reg
= gen_lowpart_common (narrow_mode
, reg
);
1785 rtx narrow_src
= gen_int_mode (INTVAL (off
),
1788 = gen_rtx_SET (gen_rtx_STRICT_LOW_PART (VOIDmode
,
1791 get_full_set_rtx_cost (new_set
, &newcst
);
1792 if (costs_lt_p (&newcst
, &oldcst
, speed
))
1794 changed
= validate_change (insn
, &PATTERN (insn
),
1803 move2add_record_sym_value (reg
, sym
, off
);
1808 /* This function is called with INSN that sets REG to (SYM + OFF),
1809 but REG doesn't have known value (SYM + offset). This function
1810 tries to find another register which is known to already have
1811 value (SYM + offset) and change INSN into an add instruction
1812 (set (REG) (plus (the found register) (OFF - offset))) if such
1813 a register is found. It also updates the information about
1815 Return true iff we made a change. */
1818 move2add_use_add3_insn (rtx reg
, rtx sym
, rtx off
, rtx_insn
*insn
)
1820 rtx pat
= PATTERN (insn
);
1821 rtx src
= SET_SRC (pat
);
1822 int regno
= REGNO (reg
);
1824 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
1826 bool changed
= false;
1827 struct full_rtx_costs oldcst
, newcst
, mincst
;
1830 init_costs_to_max (&mincst
);
1831 get_full_set_rtx_cost (pat
, &oldcst
);
1833 plus_expr
= gen_rtx_PLUS (GET_MODE (reg
), reg
, const0_rtx
);
1834 SET_SRC (pat
) = plus_expr
;
1836 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
1837 if (move2add_valid_value_p (i
, GET_MODE (reg
))
1838 && reg_base_reg
[i
] < 0
1839 && reg_symbol_ref
[i
] != NULL_RTX
1840 && rtx_equal_p (sym
, reg_symbol_ref
[i
]))
1842 rtx new_src
= gen_int_mode (UINTVAL (off
) - reg_offset
[i
],
1844 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
1845 use (set (reg) (reg)) instead.
1846 We don't delete this insn, nor do we convert it into a
1847 note, to avoid losing register notes or the return
1848 value flag. jump2 already knows how to get rid of
1850 if (new_src
== const0_rtx
)
1852 init_costs_to_zero (&mincst
);
1858 XEXP (plus_expr
, 1) = new_src
;
1859 get_full_set_rtx_cost (pat
, &newcst
);
1861 if (costs_lt_p (&newcst
, &mincst
, speed
))
1868 SET_SRC (pat
) = src
;
1870 if (costs_lt_p (&mincst
, &oldcst
, speed
))
1874 tem
= gen_rtx_REG (GET_MODE (reg
), min_regno
);
1877 rtx new_src
= gen_int_mode (UINTVAL (off
) - reg_offset
[min_regno
],
1879 tem
= gen_rtx_PLUS (GET_MODE (reg
), tem
, new_src
);
1881 if (validate_change (insn
, &SET_SRC (pat
), tem
, 0))
1884 reg_set_luid
[regno
] = move2add_luid
;
1885 move2add_record_sym_value (reg
, sym
, off
);
1889 /* Convert move insns with constant inputs to additions if they are cheaper.
1890 Return true if any changes were made. */
1892 reload_cse_move2add (rtx_insn
*first
)
1896 bool changed
= false;
1898 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
1900 reg_set_luid
[i
] = 0;
1902 reg_base_reg
[i
] = 0;
1903 reg_symbol_ref
[i
] = NULL_RTX
;
1904 reg_mode
[i
] = VOIDmode
;
1907 move2add_last_label_luid
= 0;
1909 for (insn
= first
; insn
; insn
= NEXT_INSN (insn
), move2add_luid
++)
1915 move2add_last_label_luid
= move2add_luid
;
1916 /* We're going to increment move2add_luid twice after a
1917 label, so that we can use move2add_last_label_luid + 1 as
1918 the luid for constants. */
1922 if (! INSN_P (insn
))
1924 pat
= PATTERN (insn
);
1925 /* For simplicity, we only perform this optimization on
1926 straightforward SETs. */
1927 if (GET_CODE (pat
) == SET
1928 && REG_P (SET_DEST (pat
)))
1930 rtx reg
= SET_DEST (pat
);
1931 int regno
= REGNO (reg
);
1932 rtx src
= SET_SRC (pat
);
1934 /* Check if we have valid information on the contents of this
1935 register in the mode of REG. */
1936 if (move2add_valid_value_p (regno
, GET_MODE (reg
))
1937 && dbg_cnt (cse2_move2add
))
1939 /* Try to transform (set (REGX) (CONST_INT A))
1941 (set (REGX) (CONST_INT B))
1943 (set (REGX) (CONST_INT A))
1945 (set (REGX) (plus (REGX) (CONST_INT B-A)))
1947 (set (REGX) (CONST_INT A))
1949 (set (STRICT_LOW_PART (REGX)) (CONST_INT B))
1952 if (CONST_INT_P (src
)
1953 && reg_base_reg
[regno
] < 0
1954 && reg_symbol_ref
[regno
] == NULL_RTX
)
1956 changed
|= move2add_use_add2_insn (reg
, NULL_RTX
, src
, insn
);
1960 /* Try to transform (set (REGX) (REGY))
1961 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1964 (set (REGX) (PLUS (REGX) (CONST_INT B)))
1967 (set (REGX) (PLUS (REGX) (CONST_INT A)))
1969 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
1970 else if (REG_P (src
)
1971 && reg_set_luid
[regno
] == reg_set_luid
[REGNO (src
)]
1972 && reg_base_reg
[regno
] == reg_base_reg
[REGNO (src
)]
1973 && move2add_valid_value_p (REGNO (src
), GET_MODE (reg
)))
1975 rtx_insn
*next
= next_nonnote_nondebug_insn (insn
);
1978 set
= single_set (next
);
1980 && SET_DEST (set
) == reg
1981 && GET_CODE (SET_SRC (set
)) == PLUS
1982 && XEXP (SET_SRC (set
), 0) == reg
1983 && CONST_INT_P (XEXP (SET_SRC (set
), 1)))
1985 rtx src3
= XEXP (SET_SRC (set
), 1);
1986 unsigned HOST_WIDE_INT added_offset
= UINTVAL (src3
);
1987 HOST_WIDE_INT base_offset
= reg_offset
[REGNO (src
)];
1988 HOST_WIDE_INT regno_offset
= reg_offset
[regno
];
1990 gen_int_mode (added_offset
1994 bool success
= false;
1995 bool speed
= optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn
));
1997 if (new_src
== const0_rtx
)
1998 /* See above why we create (set (reg) (reg)) here. */
2000 = validate_change (next
, &SET_SRC (set
), reg
, 0);
2003 rtx old_src
= SET_SRC (set
);
2004 struct full_rtx_costs oldcst
, newcst
;
2005 rtx tem
= gen_rtx_PLUS (GET_MODE (reg
), reg
, new_src
);
2007 get_full_set_rtx_cost (set
, &oldcst
);
2008 SET_SRC (set
) = tem
;
2009 get_full_set_src_cost (tem
, GET_MODE (reg
), &newcst
);
2010 SET_SRC (set
) = old_src
;
2011 costs_add_n_insns (&oldcst
, 1);
2013 if (costs_lt_p (&newcst
, &oldcst
, speed
)
2014 && have_add2_insn (reg
, new_src
))
2016 rtx newpat
= gen_rtx_SET (reg
, tem
);
2018 = validate_change (next
, &PATTERN (next
),
2026 move2add_record_mode (reg
);
2028 = trunc_int_for_mode (added_offset
+ base_offset
,
2036 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
2038 (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B))))
2040 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
2042 (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */
2043 if ((GET_CODE (src
) == SYMBOL_REF
2044 || (GET_CODE (src
) == CONST
2045 && GET_CODE (XEXP (src
, 0)) == PLUS
2046 && GET_CODE (XEXP (XEXP (src
, 0), 0)) == SYMBOL_REF
2047 && CONST_INT_P (XEXP (XEXP (src
, 0), 1))))
2048 && dbg_cnt (cse2_move2add
))
2052 if (GET_CODE (src
) == SYMBOL_REF
)
2059 sym
= XEXP (XEXP (src
, 0), 0);
2060 off
= XEXP (XEXP (src
, 0), 1);
2063 /* If the reg already contains the value which is sum of
2064 sym and some constant value, we can use an add2 insn. */
2065 if (move2add_valid_value_p (regno
, GET_MODE (reg
))
2066 && reg_base_reg
[regno
] < 0
2067 && reg_symbol_ref
[regno
] != NULL_RTX
2068 && rtx_equal_p (sym
, reg_symbol_ref
[regno
]))
2069 changed
|= move2add_use_add2_insn (reg
, sym
, off
, insn
);
2071 /* Otherwise, we have to find a register whose value is sum
2072 of sym and some constant value. */
2074 changed
|= move2add_use_add3_insn (reg
, sym
, off
, insn
);
2080 for (note
= REG_NOTES (insn
); note
; note
= XEXP (note
, 1))
2082 if (REG_NOTE_KIND (note
) == REG_INC
2083 && REG_P (XEXP (note
, 0)))
2085 /* Reset the information about this register. */
2086 int regno
= REGNO (XEXP (note
, 0));
2087 if (regno
< FIRST_PSEUDO_REGISTER
)
2089 move2add_record_mode (XEXP (note
, 0));
2090 reg_mode
[regno
] = VOIDmode
;
2094 note_stores (PATTERN (insn
), move2add_note_store
, insn
);
2096 /* If INSN is a conditional branch, we try to extract an
2097 implicit set out of it. */
2098 if (any_condjump_p (insn
))
2100 rtx cnd
= fis_get_condition (insn
);
2103 && GET_CODE (cnd
) == NE
2104 && REG_P (XEXP (cnd
, 0))
2105 && !reg_set_p (XEXP (cnd
, 0), insn
)
2106 /* The following two checks, which are also in
2107 move2add_note_store, are intended to reduce the
2108 number of calls to gen_rtx_SET to avoid memory
2109 allocation if possible. */
2110 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd
, 0)))
2111 && REG_NREGS (XEXP (cnd
, 0)) == 1
2112 && CONST_INT_P (XEXP (cnd
, 1)))
2115 gen_rtx_SET (XEXP (cnd
, 0), XEXP (cnd
, 1));
2116 move2add_note_store (SET_DEST (implicit_set
), implicit_set
, insn
);
2120 /* If this is a CALL_INSN, all call used registers are stored with
2126 for (i
= FIRST_PSEUDO_REGISTER
- 1; i
>= 0; i
--)
2128 if (call_used_regs
[i
])
2129 /* Reset the information about this register. */
2130 reg_mode
[i
] = VOIDmode
;
2133 for (link
= CALL_INSN_FUNCTION_USAGE (insn
); link
;
2134 link
= XEXP (link
, 1))
2136 rtx setuse
= XEXP (link
, 0);
2137 rtx usage_rtx
= XEXP (setuse
, 0);
2138 if (GET_CODE (setuse
) == CLOBBER
2139 && REG_P (usage_rtx
))
2141 unsigned int end_regno
= END_REGNO (usage_rtx
);
2142 for (unsigned int r
= REGNO (usage_rtx
); r
< end_regno
; ++r
)
2143 /* Reset the information about this register. */
2144 reg_mode
[r
] = VOIDmode
;
2152 /* SET is a SET or CLOBBER that sets DST. DATA is the insn which
2154 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
2155 Called from reload_cse_move2add via note_stores. */
2158 move2add_note_store (rtx dst
, const_rtx set
, void *data
)
2160 rtx_insn
*insn
= (rtx_insn
*) data
;
2161 unsigned int regno
= 0;
2162 machine_mode mode
= GET_MODE (dst
);
2164 /* Some targets do argument pushes without adding REG_INC notes. */
2168 dst
= XEXP (dst
, 0);
2169 if (GET_CODE (dst
) == PRE_INC
|| GET_CODE (dst
) == POST_INC
2170 || GET_CODE (dst
) == PRE_DEC
|| GET_CODE (dst
) == POST_DEC
)
2171 reg_mode
[REGNO (XEXP (dst
, 0))] = VOIDmode
;
2175 if (GET_CODE (dst
) == SUBREG
)
2176 regno
= subreg_regno (dst
);
2177 else if (REG_P (dst
))
2178 regno
= REGNO (dst
);
2182 if (SCALAR_INT_MODE_P (mode
)
2183 && GET_CODE (set
) == SET
)
2185 rtx note
, sym
= NULL_RTX
;
2188 note
= find_reg_equal_equiv_note (insn
);
2189 if (note
&& GET_CODE (XEXP (note
, 0)) == SYMBOL_REF
)
2191 sym
= XEXP (note
, 0);
2194 else if (note
&& GET_CODE (XEXP (note
, 0)) == CONST
2195 && GET_CODE (XEXP (XEXP (note
, 0), 0)) == PLUS
2196 && GET_CODE (XEXP (XEXP (XEXP (note
, 0), 0), 0)) == SYMBOL_REF
2197 && CONST_INT_P (XEXP (XEXP (XEXP (note
, 0), 0), 1)))
2199 sym
= XEXP (XEXP (XEXP (note
, 0), 0), 0);
2200 off
= XEXP (XEXP (XEXP (note
, 0), 0), 1);
2203 if (sym
!= NULL_RTX
)
2205 move2add_record_sym_value (dst
, sym
, off
);
2210 if (SCALAR_INT_MODE_P (mode
)
2211 && GET_CODE (set
) == SET
2212 && GET_CODE (SET_DEST (set
)) != ZERO_EXTRACT
2213 && GET_CODE (SET_DEST (set
)) != STRICT_LOW_PART
)
2215 rtx src
= SET_SRC (set
);
2217 unsigned HOST_WIDE_INT offset
;
2220 switch (GET_CODE (src
))
2223 if (REG_P (XEXP (src
, 0)))
2225 base_reg
= XEXP (src
, 0);
2227 if (CONST_INT_P (XEXP (src
, 1)))
2228 offset
= UINTVAL (XEXP (src
, 1));
2229 else if (REG_P (XEXP (src
, 1))
2230 && move2add_valid_value_p (REGNO (XEXP (src
, 1)), mode
))
2232 if (reg_base_reg
[REGNO (XEXP (src
, 1))] < 0
2233 && reg_symbol_ref
[REGNO (XEXP (src
, 1))] == NULL_RTX
)
2234 offset
= reg_offset
[REGNO (XEXP (src
, 1))];
2235 /* Maybe the first register is known to be a
2237 else if (move2add_valid_value_p (REGNO (base_reg
), mode
)
2238 && reg_base_reg
[REGNO (base_reg
)] < 0
2239 && reg_symbol_ref
[REGNO (base_reg
)] == NULL_RTX
)
2241 offset
= reg_offset
[REGNO (base_reg
)];
2242 base_reg
= XEXP (src
, 1);
2261 /* Start tracking the register as a constant. */
2262 reg_base_reg
[regno
] = -1;
2263 reg_symbol_ref
[regno
] = NULL_RTX
;
2264 reg_offset
[regno
] = INTVAL (SET_SRC (set
));
2265 /* We assign the same luid to all registers set to constants. */
2266 reg_set_luid
[regno
] = move2add_last_label_luid
+ 1;
2267 move2add_record_mode (dst
);
2274 base_regno
= REGNO (base_reg
);
2275 /* If information about the base register is not valid, set it
2276 up as a new base register, pretending its value is known
2277 starting from the current insn. */
2278 if (!move2add_valid_value_p (base_regno
, mode
))
2280 reg_base_reg
[base_regno
] = base_regno
;
2281 reg_symbol_ref
[base_regno
] = NULL_RTX
;
2282 reg_offset
[base_regno
] = 0;
2283 reg_set_luid
[base_regno
] = move2add_luid
;
2284 gcc_assert (GET_MODE (base_reg
) == mode
);
2285 move2add_record_mode (base_reg
);
2288 /* Copy base information from our base register. */
2289 reg_set_luid
[regno
] = reg_set_luid
[base_regno
];
2290 reg_base_reg
[regno
] = reg_base_reg
[base_regno
];
2291 reg_symbol_ref
[regno
] = reg_symbol_ref
[base_regno
];
2293 /* Compute the sum of the offsets or constants. */
2295 = trunc_int_for_mode (offset
+ reg_offset
[base_regno
], mode
);
2297 move2add_record_mode (dst
);
2302 /* Invalidate the contents of the register. */
2303 move2add_record_mode (dst
);
2304 reg_mode
[regno
] = VOIDmode
;
2310 const pass_data pass_data_postreload_cse
=
2312 RTL_PASS
, /* type */
2313 "postreload", /* name */
2314 OPTGROUP_NONE
, /* optinfo_flags */
2315 TV_RELOAD_CSE_REGS
, /* tv_id */
2316 0, /* properties_required */
2317 0, /* properties_provided */
2318 0, /* properties_destroyed */
2319 0, /* todo_flags_start */
2320 TODO_df_finish
, /* todo_flags_finish */
2323 class pass_postreload_cse
: public rtl_opt_pass
2326 pass_postreload_cse (gcc::context
*ctxt
)
2327 : rtl_opt_pass (pass_data_postreload_cse
, ctxt
)
2330 /* opt_pass methods: */
2331 virtual bool gate (function
*) { return (optimize
> 0 && reload_completed
); }
2333 virtual unsigned int execute (function
*);
2335 }; // class pass_postreload_cse
2338 pass_postreload_cse::execute (function
*fun
)
2340 if (!dbg_cnt (postreload_cse
))
2343 /* Do a very simple CSE pass over just the hard registers. */
2344 reload_cse_regs (get_insns ());
2345 /* Reload_cse_regs can eliminate potentially-trapping MEMs.
2346 Remove any EH edges associated with them. */
2347 if (fun
->can_throw_non_call_exceptions
2348 && purge_all_dead_edges ())
2357 make_pass_postreload_cse (gcc::context
*ctxt
)
2359 return new pass_postreload_cse (ctxt
);