| blob | 1be922df614237dfe4050a2082b697aa2608b0cf |
1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987-2019 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify it under
7 the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 3, or (at your option) any later
9 version.
11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
20 /* This module is essentially the "combiner" phase of the U. of Arizona
21 Portable Optimizer, but redone to work on our list-structured
22 representation for RTL instead of their string representation.
24 The LOG_LINKS of each insn identify the most recent assignment
25 to each REG used in the insn. It is a list of previous insns,
26 each of which contains a SET for a REG that is used in this insn
27 and not used or set in between. LOG_LINKs never cross basic blocks.
28 They were set up by the preceding pass (lifetime analysis).
30 We try to combine each pair of insns joined by a logical link.
31 We also try to combine triplets of insns A, B and C when C has
32 a link back to B and B has a link back to A. Likewise for a
33 small number of quadruplets of insns A, B, C and D for which
34 there's high likelihood of success.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with modified_between_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information isn't
53 completely updated (however this is only a local issue since it is
54 regenerated before the next pass that uses it):
56 - reg_live_length is not updated
57 - reg_n_refs is not adjusted in the rare case when a register is
58 no longer required in a computation
59 - there are extremely rare cases (see distribute_notes) when a
60 REG_DEAD note is lost
61 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
62 removed because there is no way to know which register it was
63 linking
65 To simplify substitution, we combine only when the earlier insn(s)
66 consist of only a single assignment. To simplify updating afterward,
67 we never combine when a subroutine call appears in the middle.
69 Since we do not represent assignments to CC0 explicitly except when that
70 is all an insn does, there is no LOG_LINKS entry in an insn that uses
71 the condition code for the insn that set the condition code.
72 Fortunately, these two insns must be consecutive.
73 Therefore, every JUMP_INSN is taken to have an implicit logical link
74 to the preceding insn. This is not quite right, since non-jumps can
75 also use the condition code; but in practice such insns would not
76 combine anyway. */
98 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
109 /* Number of attempts to combine instructions in this function. */
113 /* Number of attempts that got as far as substitution in this function. */
117 /* Number of instructions combined with added SETs in this function. */
121 /* Number of instructions combined in this function. */
125 /* Totals over entire compilation. */
129 /* combine_instructions may try to replace the right hand side of the
130 second instruction with the value of an associated REG_EQUAL note
131 before throwing it at try_combine. That is problematic when there
132 is a REG_DEAD note for a register used in the old right hand side
133 and can cause distribute_notes to do wrong things. This is the
134 second instruction if it has been so modified, null otherwise. */
138 /* When I2MOD is nonnull, this is a copy of the old right hand side. */
142 /* When I2MOD is nonnull, this is a copy of the new right hand side. */
145 \f
147 /* Record last point of death of (hard or pseudo) register n. */
150 /* Record last point of modification of (hard or pseudo) register n. */
153 /* The next group of fields allows the recording of the last value assigned
154 to (hard or pseudo) register n. We use this information to see if an
155 operation being processed is redundant given a prior operation performed
156 on the register. For example, an `and' with a constant is redundant if
157 all the zero bits are already known to be turned off.
159 We use an approach similar to that used by cse, but change it in the
160 following ways:
162 (1) We do not want to reinitialize at each label.
163 (2) It is useful, but not critical, to know the actual value assigned
164 to a register. Often just its form is helpful.
166 Therefore, we maintain the following fields:
168 last_set_value the last value assigned
169 last_set_label records the value of label_tick when the
170 register was assigned
171 last_set_table_tick records the value of label_tick when a
172 value using the register is assigned
173 last_set_invalid set to nonzero when it is not valid
174 to use the value of this register in some
175 register's value
177 To understand the usage of these tables, it is important to understand
178 the distinction between the value in last_set_value being valid and
179 the register being validly contained in some other expression in the
180 table.
182 (The next two parameters are out of date).
184 reg_stat[i].last_set_value is valid if it is nonzero, and either
185 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
187 Register I may validly appear in any expression returned for the value
188 of another register if reg_n_sets[i] is 1. It may also appear in the
189 value for register J if reg_stat[j].last_set_invalid is zero, or
190 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
192 If an expression is found in the table containing a register which may
193 not validly appear in an expression, the register is replaced by
194 something that won't match, (clobber (const_int 0)). */
196 /* Record last value assigned to (hard or pseudo) register n. */
198 rtx last_set_value;
200 /* Record the value of label_tick when an expression involving register n
201 is placed in last_set_value. */
205 /* Record the value of label_tick when the value for register n is placed in
206 last_set_value. */
210 /* These fields are maintained in parallel with last_set_value and are
211 used to store the mode in which the register was last set, the bits
212 that were known to be zero when it was last set, and the number of
213 sign bits copies it was known to have when it was last set. */
219 /* Set nonzero if references to register n in expressions should not be
220 used. last_set_invalid is set nonzero when this register is being
221 assigned to and last_set_table_tick == label_tick. */
225 /* Some registers that are set more than once and used in more than one
226 basic block are nevertheless always set in similar ways. For example,
227 a QImode register may be loaded from memory in two places on a machine
228 where byte loads zero extend.
230 We record in the following fields if a register has some leading bits
231 that are always equal to the sign bit, and what we know about the
232 nonzero bits of a register, specifically which bits are known to be
233 zero.
235 If an entry is zero, it means that we don't know anything special. */
241 /* Record the value of the label_tick when the last truncation
242 happened. The field truncated_to_mode is only valid if
243 truncation_label == label_tick. */
247 /* Record the last truncation seen for this register. If truncation
248 is not a nop to this mode we might be able to save an explicit
249 truncation if we know that value already contains a truncated
250 value. */
253 };
258 /* One plus the highest pseudo for which we track REG_N_SETS.
259 regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
260 but during combine_split_insns new pseudos can be created. As we don't have
261 updated DF information in that case, it is hard to initialize the array
262 after growing. The combiner only cares about REG_N_SETS (regno) == 1,
263 so instead of growing the arrays, just assume all newly created pseudos
264 during combine might be set multiple times. */
268 /* Record the luid of the last insn that invalidated memory
269 (anything that writes memory, and subroutine calls, but not pushes). */
273 /* Record the luid of the last CALL_INSN
274 so we can tell whether a potential combination crosses any calls. */
278 /* When `subst' is called, this is the insn that is being modified
279 (by combining in a previous insn). The PATTERN of this insn
280 is still the old pattern partially modified and it should not be
281 looked at, but this may be used to examine the successors of the insn
282 to judge whether a simplification is valid. */
286 /* This is the lowest LUID that `subst' is currently dealing with.
287 get_last_value will not return a value if the register was set at or
288 after this LUID. If not for this mechanism, we could get confused if
289 I2 or I1 in try_combine were an insn that used the old value of a register
290 to obtain a new value. In that case, we might erroneously get the
291 new value of the register when we wanted the old one. */
295 /* This contains any hard registers that are used in newpat; reg_dead_at_p
296 must consider all these registers to be always live. */
300 /* This is an insn to which a LOG_LINKS entry has been added. If this
301 insn is the earlier than I2 or I3, combine should rescan starting at
302 that location. */
306 /* And similarly, for notes. */
310 /* Basic block in which we are performing combines. */
314 \f
315 /* Length of the currently allocated uid_insn_cost array. */
319 /* The following array records the insn_cost for every insn
320 in the instruction stream. */
324 /* The following array records the LOG_LINKS for every insn in the
325 instruction stream as struct insn_link pointers. */
331 };
337 {
341 }
343 #define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
344 #define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
346 #define FOR_EACH_LOG_LINK(L, INSN) \
347 for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
349 /* Links for LOG_LINKS are allocated from this obstack. */
353 /* Allocate a link. */
357 {
365 }
367 /* Incremented for each basic block. */
371 /* Reset to label_tick for each extended basic block in scanning order. */
375 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
376 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
380 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
381 be safely used. It is zero while computing them and after combine has
382 completed. This former test prevents propagating values based on
383 previously set values, which can be incorrect if a variable is modified
384 in a loop. */
388 \f
389 /* Record one modification to rtl structure
390 to be undone by storing old_contents into *where. */
394 struct undo
395 {
400 };
402 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
403 num_undo says how many are currently recorded.
405 other_insn is nonzero if we have modified some other insn in the process
406 of working on subst_insn. It must be verified too. */
408 struct undobuf
409 {
413 };
417 /* Number of times the pseudo being substituted for
418 was found and replaced. */
423 scalar_int_mode,
426 scalar_int_mode,
498 \f
500 /* It is not safe to use ordinary gen_lowpart in combine.
501 See comments in gen_lowpart_for_combine. */
502 #undef RTL_HOOKS_GEN_LOWPART
503 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
505 /* Our implementation of gen_lowpart never emits a new pseudo. */
506 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
507 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
509 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
510 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
512 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
513 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
515 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
516 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
520 \f
521 /* Convenience wrapper for the canonicalize_comparison target hook.
522 Target hooks cannot use enum rtx_code. */
526 {
530 }
532 /* Try to split PATTERN found in INSN. This returns NULL_RTX if
533 PATTERN cannot be split. Otherwise, it returns an insn sequence.
534 This is a wrapper around split_insns which ensures that the
535 reg_stat vector is made larger if the splitter creates a new
536 register. */
540 {
549 }
551 /* This is used by find_single_use to locate an rtx in LOC that
552 contains exactly one use of DEST, which is typically either a REG
553 or CC0. It returns a pointer to the innermost rtx expression
554 containing DEST. Appearances of DEST that are being used to
555 totally replace it are not counted. */
559 {
568 {
572 CASE_CONST_ANY:
578 /* If the destination is anything other than CC0, PC, a REG or a SUBREG
579 of a REG that occupies all of the REG, the insn uses DEST if
580 it is mentioned in the destination or the source. Otherwise, we
581 need just check the source. */
598 }
600 /* If it wasn't one of the common cases above, check each expression and
601 vector of this code. Look for a unique usage of DEST. */
605 {
607 {
612 else
618 /* Duplicate usage. */
620 }
622 {
626 {
632 else
639 }
640 }
641 }
644 }
647 /* See if DEST, produced in INSN, is used only a single time in the
648 sequel. If so, return a pointer to the innermost rtx expression in which
649 it is used.
651 If PLOC is nonzero, *PLOC is set to the insn containing the single use.
653 If DEST is cc0_rtx, we look only at the next insn. In that case, we don't
654 care about REG_DEAD notes or LOG_LINKS.
656 Otherwise, we find the single use by finding an insn that has a
657 LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
658 only referenced once in that insn, we know that it must be the first
659 and last insn referencing DEST. */
663 {
664 basic_block bb;
670 {
680 }
690 {
696 {
701 }
702 }
705 }
706 \f
707 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
708 insn. The substitution can be undone by undo_all. If INTO is already
709 set to NEWVAL, do not record this change. Because computing NEWVAL might
710 also call SUBST, we have to compute it before we put anything into
711 the undo table. */
713 static void
715 {
722 /* We'd like to catch as many invalid transformations here as
723 possible. Unfortunately, there are way too many mode changes
724 that are perfectly valid, so we'd waste too much effort for
725 little gain doing the checks here. Focus on catching invalid
726 transformations involving integer constants. */
729 {
730 /* Sanity check that we're replacing oldval with a CONST_INT
731 that is a valid sign-extension for the original mode. */
735 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
736 CONST_INT is not valid, because after the replacement, the
737 original mode would be gone. Unfortunately, we can't tell
738 when do_SUBST is called to replace the operand thereof, so we
739 perform this test on oldval instead, checking whether an
740 invalid replacement took place before we got here. */
745 }
749 else
758 }
760 #define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
762 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
763 for the value of a HOST_WIDE_INT value (including CONST_INT) is
764 not safe. */
766 static void
768 {
777 else
786 }
788 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
790 /* Similar to SUBST, but just substitute the mode. This is used when
791 changing the mode of a pseudo-register, so that any other
792 references to the entry in the regno_reg_rtx array will change as
793 well. */
795 static void
797 {
806 else
815 }
817 #define SUBST_MODE(INTO, NEWVAL) do_SUBST_MODE (&(INTO), (NEWVAL))
819 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
821 static void
823 {
832 else
841 }
843 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
844 \f
845 /* Subroutine of try_combine. Determine whether the replacement patterns
846 NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_cost
847 than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
848 that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
849 undobuf.other_insn may also both be NULL_RTX. Return false if the cost
850 of all the instructions can be estimated and the replacements are more
851 expensive than the original sequence. */
853 static bool
856 {
861 /* Lookup the original insn_costs. */
866 {
869 {
873 }
874 else
875 {
879 }
880 }
881 else
882 {
885 }
887 /* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
888 correct that. */
893 /* Calculate the replacement insn_costs. */
902 {
912 }
913 else
914 {
917 }
920 {
929 optimize_this_for_speed_p);
933 {
936 }
937 else
939 }
941 /* Disallow this combination if both new_cost and old_cost are greater than
942 zero, and new_cost is greater than old cost. */
946 {
965 else
967 }
972 /* Update the uid_insn_cost array with the replacement costs. */
976 {
980 }
983 }
986 /* Delete any insns that copy a register to itself.
987 Return true if the CFG was changed. */
989 static bool
991 {
993 basic_block bb;
998 {
1000 {
1003 {
1008 }
1009 }
1010 }
1013 }
1015 \f
1016 /* Return false if we do not want to (or cannot) combine DEF. */
1017 static bool
1019 {
1020 /* Do not consider if it is pre/post modification in MEM. */
1026 /* Do not combine frame pointer adjustments. */
1029 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
1037 }
1039 /* Return false if we do not want to (or cannot) combine USE. */
1040 static bool
1042 {
1043 /* Do not consider the usage of the stack pointer by function call. */
1048 }
1050 /* Fill in log links field for all insns. */
1052 static void
1054 {
1055 basic_block bb;
1062 /* Pass through each block from the end, recording the uses of each
1063 register and establishing log links when def is encountered.
1064 Note that we do not clear next_use array in order to save time,
1065 so we have to test whether the use is in the same basic block as def.
1067 There are a few cases below when we do not consider the definition or
1068 usage -- these are taken from original flow.c did. Don't ask me why it is
1069 done this way; I don't know and if it works, I don't want to know. */
1072 {
1074 {
1078 /* Log links are created only once. */
1082 {
1098 /* flow.c claimed:
1100 We don't build a LOG_LINK for hard registers contained
1101 in ASM_OPERANDs. If these registers get replaced,
1102 we might wind up changing the semantics of the insn,
1103 even if reload can make what appear to be valid
1104 assignments later. */
1109 /* Don't add duplicate links between instructions. */
1118 }
1123 }
1124 }
1127 }
1129 /* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1130 true if we found a LOG_LINK that proves that A feeds B. This only works
1131 if there are no instructions between A and B which could have a link
1132 depending on A, since in that case we would not record a link for B.
1133 We also check the implicit dependency created by a cc0 setter/user
1134 pair. */
1136 static bool
1138 {
1146 }
1147 \f
1148 /* Main entry point for combiner. F is the first insn of the function.
1149 NREGS is the first unused pseudo-reg number.
1151 Return nonzero if the CFG was changed (e.g. if the combiner has
1152 turned an indirect jump instruction into a direct jump). */
1153 static int
1155 {
1160 basic_block last_bb;
1180 /* Allocate array for insn info. */
1188 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1189 problems when, for example, we have j <<= 1 in a loop. */
1194 /* Scan all SETs and see if we can deduce anything about what
1195 bits are known to be zero for some registers and how many copies
1196 of the sign bit are known to exist for those registers.
1198 Also set any known values so that we can use it while searching
1199 for what bits are known to be set. */
1202 /* Allow the entry block and the first block to fall into the same EBB.
1203 Conceptually the incoming promotions are assigned to the entry block. */
1208 {
1213 label_tick++;
1221 {
1222 rtx links;
1228 insn);
1235 insn);
1237 /* Record the current insn_cost of this instruction. */
1241 {
1244 }
1245 }
1246 }
1250 /* Now scan all the insns in forward order. */
1258 {
1261 /* Ignore instruction combination in basic blocks that are going to
1262 be removed as unreachable anyway. See PR82386. */
1270 label_tick++;
1280 {
1294 /* See if we know about function return values before this
1295 insn based upon SUBREG flags. */
1298 /* See if we can find hardregs and subreg of pseudos in
1299 narrower modes. This could help turning TRUNCATEs
1300 into SUBREGs. */
1303 /* Try this insn with each insn it links back to. */
1309 {
1312 }
1314 /* Try each sequence of three linked insns ending with this one. */
1318 {
1321 /* If the linked insn has been replaced by a note, then there
1322 is no point in pursuing this chain any further. */
1330 {
1333 }
1334 }
1336 /* Try to combine a jump insn that uses CC0
1337 with a preceding insn that sets CC0, and maybe with its
1338 logical predecessor as well.
1339 This is how we make decrement-and-branch insns.
1340 We need this special code because data flow connections
1341 via CC0 do not get entered in LOG_LINKS. */
1348 {
1359 }
1361 /* Do the same for an insn that explicitly references CC0. */
1368 {
1379 }
1381 /* Finally, see if any of the insns that this insn links to
1382 explicitly references CC0. If so, try this insn, that insn,
1383 and its predecessor if it sets CC0. */
1385 {
1397 }
1399 /* Try combining an insn with two different insns whose results it
1400 uses. */
1410 {
1413 }
1415 /* Try four-instruction combinations. */
1418 {
1422 /* If the linked insn has been replaced by a note, then there
1423 is no point in pursuing this chain any further. */
1428 {
1432 /* I0 -> I1 -> I2 -> I3. */
1438 {
1441 }
1442 /* I0, I1 -> I2, I2 -> I3. */
1449 {
1452 }
1453 }
1456 {
1460 /* I0 -> I2; I1, I2 -> I3. */
1466 {
1469 }
1470 /* I0 -> I1; I1, I2 -> I3. */
1476 {
1479 }
1480 }
1481 }
1483 /* Try this insn with each REG_EQUAL note it links back to. */
1485 {
1491 /* Avoid using a register that may already been marked
1492 dead by an earlier instruction. */
1500 {
1501 /* Temporarily replace the set's source with the
1502 contents of the REG_EQUAL note. The insn will
1503 be deleted or recognized by try_combine. */
1514 last_combined_insn);
1517 {
1520 }
1523 }
1524 }
1529 retry:
1530 ;
1531 }
1532 }
1539 /* Clean up. */
1545 {
1548 {
1551 }
1553 }
1563 /* Make recognizer allow volatile MEMs again. */
1567 }
1569 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1571 static void
1573 {
1579 }
1580 \f
1581 /* Set up any promoted values for incoming argument registers. */
1583 static void
1585 {
1586 tree arg;
1591 {
1596 /* Only continue if the incoming argument is in a register. */
1600 /* Determine, if possible, whether all call sites of the current
1601 function lie within the current compilation unit. (This does
1602 take into account the exporting of a function via taking its
1603 address, and so forth.) */
1606 /* The mode and signedness of the argument before any promotions happen
1607 (equal to the mode of the pseudo holding it at that stage). */
1611 /* The mode and signedness of the argument after any source language and
1612 TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1616 /* The mode and signedness of the argument as it is actually passed,
1617 see assign_parm_setup_reg in function.c. */
1621 /* The mode of the register in which the argument is being passed. */
1624 /* Eliminate sign extensions in the callee when:
1625 (a) A mode promotion has occurred; */
1628 /* (b) The mode of the register is the same as the mode of
1629 the argument as it is passed; */
1632 /* (c) There's no language level extension; */
1634 ;
1635 /* (c.1) All callers are from the current compilation unit. If that's
1636 the case we don't have to rely on an ABI, we only have to know
1637 what we're generating right now, and we know that we will do the
1638 mode1 to mode2 promotion with the given sign. */
1641 /* (c.2) The combination of the two promotions is useful. This is
1642 true when the signs match, or if the first promotion is unsigned.
1643 In the later case, (sign_extend (zero_extend x)) is the same as
1644 (zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1650 /* Record that the value was promoted from mode1 to mode3,
1651 so that any sign extension at the head of the current
1652 function may be eliminated. */
1656 }
1657 }
1659 /* If MODE has a precision lower than PREC and SRC is a non-negative constant
1660 that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1661 because some machines (maybe most) will actually do the sign-extension and
1662 this is the conservative approach.
1664 ??? For 2.5, try to tighten up the MD files in this regard instead of this
1665 kludge. */
1667 static rtx
1669 {
1670 scalar_int_mode int_mode;
1679 }
1681 /* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1682 and SET. */
1684 static void
1686 rtx x)
1687 {
1697 {
1701 }
1703 /* Don't call nonzero_bits if it cannot change anything. */
1705 {
1714 }
1716 /* Don't call num_sign_bit_copies if it cannot change anything. */
1718 {
1721 {
1725 }
1728 }
1729 }
1731 /* Called via note_stores. If X is a pseudo that is narrower than
1732 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1734 If we are setting only a portion of X and we can't figure out what
1735 portion, assume all bits will be used since we don't know what will
1736 be happening.
1738 Similarly, set how many bits of X are known to be copies of the sign bit
1739 at all locations in the function. This is the smallest number implied
1740 by any set of X. */
1742 static void
1744 {
1746 scalar_int_mode mode;
1750 /* If this register is undefined at the start of the file, we can't
1751 say what its contents were. */
1752 && ! REGNO_REG_SET_P
1756 {
1760 {
1764 }
1766 /* Should not happen as we only using pseduo registers. */
1769 /* If this register is being initialized using itself, and the
1770 register is uninitialized in this basic block, and there are
1771 no LOG_LINKS which set the register, then part of the
1772 register is uninitialized. In that case we can't assume
1773 anything about the number of nonzero bits.
1775 ??? We could do better if we checked this in
1776 reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1777 could avoid making assumptions about the insn which initially
1778 sets the register, while still using the information in other
1779 insns. We would have to be careful to check every insn
1780 involved in the combination. */
1786 {
1793 {
1797 }
1798 }
1800 /* If this is a complex assignment, see if we can convert it into a
1801 simple assignment. */
1804 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1805 set what we know about X. */
1811 else
1812 {
1815 }
1816 }
1817 }
1818 \f
1819 /* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1820 optionally insns that were previously combined into I3 or that will be
1821 combined into the merger of INSN and I3. The order is PRED, PRED2,
1822 INSN, SUCC, SUCC2, I3.
1824 Return 0 if the combination is not allowed for any reason.
1826 If the combination is allowed, *PDEST will be set to the single
1827 destination of INSN and *PSRC to the single source, and this function
1828 will return 1. */
1830 static int
1834 {
1839 rtx link;
1844 {
1846 {
1851 }
1856 }
1860 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1861 or a PARALLEL consisting of such a SET and CLOBBERs.
1863 If INSN has CLOBBER parallel parts, ignore them for our processing.
1864 By definition, these happen during the execution of the insn. When it
1865 is merged with another insn, all bets are off. If they are, in fact,
1866 needed and aren't also supplied in I3, they may be added by
1867 recog_for_combine. Otherwise, it won't match.
1869 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1870 note.
1872 Get the source and destination of INSN. If more than one, can't
1873 combine. */
1879 {
1881 {
1885 {
1886 /* This is important to combine floating point insns
1887 for the SH4 port. */
1889 /* Combining an isolated USE doesn't make sense.
1890 We depend here on combinable_i3pat to reject them. */
1891 /* The code below this loop only verifies that the inputs of
1892 the SET in INSN do not change. We call reg_set_between_p
1893 to verify that the REG in the USE does not change between
1894 I3 and INSN.
1895 If the USE in INSN was for a pseudo register, the matching
1896 insn pattern will likely match any register; combining this
1897 with any other USE would only be safe if we knew that the
1898 used registers have identical values, or if there was
1899 something to tell them apart, e.g. different modes. For
1900 now, we forgo such complicated tests and simply disallow
1901 combining of USES of pseudo registers with any other USE. */
1904 {
1909 do
1910 {
1920 }
1922 }
1925 /* We can ignore CLOBBERs. */
1931 /* Ignore SETs whose result isn't used but not those that
1932 have side-effects. */
1938 /* If we have already found a SET, this is a second one and
1939 so we cannot combine with this insn. */
1947 /* Anything else means we can't combine. */
1949 }
1950 }
1953 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1954 so don't do anything with it. */
1957 }
1958 else
1964 /* The simplification in expand_field_assignment may call back to
1965 get_last_value, so set safe guard here. */
1971 /* Do not eliminate user-specified register if it is in an
1972 asm input because we may break the register asm usage defined
1973 in GCC manual if allow to do so.
1974 Be aware that this may cover more cases than we expect but this
1975 should be harmless. */
1980 /* Don't eliminate a store in the stack pointer. */
1982 /* Don't combine with an insn that sets a register to itself if it has
1983 a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1985 /* Can't merge an ASM_OPERANDS. */
1987 /* Can't merge a function call. */
1989 /* Don't eliminate a function call argument. */
1995 /* Don't substitute into an incremented register. */
1999 /* Don't substitute into a non-local goto, this confuses CFG. */
2001 /* Make sure that DEST is not used after INSN but before SUCC, or
2002 after SUCC and before SUCC2, or after SUCC2 but before I3. */
2003 || (!all_adjacent
2004 && ((succ2
2009 || (succ
2010 /* SUCC and SUCC2 can be split halves from a PARALLEL; in
2011 that case SUCC is not in the insn stream, so use SUCC2
2012 instead for this test. */
2014 succ2
2017 /* Make sure that the value that is to be substituted for the register
2018 does not use any registers whose values alter in between. However,
2019 If the insns are adjacent, a use can't cross a set even though we
2020 think it might (this can happen for a sequence of insns each setting
2021 the same destination; last_set of that register might point to
2022 a NOTE). If INSN has a REG_EQUIV note, the register is always
2023 equivalent to the memory so the substitution is valid even if there
2024 are intervening stores. Also, don't move a volatile asm or
2025 UNSPEC_VOLATILE across any other insns. */
2026 || (! all_adjacent
2032 /* Don't combine across a CALL_INSN, because that would possibly
2033 change whether the life span of some REGs crosses calls or not,
2034 and it is a pain to update that information.
2035 Exception: if source is a constant, moving it later can't hurt.
2036 Accept that as a special case. */
2040 /* DEST must either be a REG or CC0. */
2042 {
2043 /* If register alignment is being enforced for multi-word items in all
2044 cases except for parameters, it is possible to have a register copy
2045 insn referencing a hard register that is not allowed to contain the
2046 mode being copied and which would not be valid as an operand of most
2047 insns. Eliminate this problem by not combining with such an insn.
2049 Also, on some machines we don't want to extend the life of a hard
2050 register. */
2055 /* Don't extend the life of a hard register unless it is
2056 user variable (if we have few registers) or it can't
2057 fit into the desired register (meaning something special
2058 is going on).
2059 Also avoid substituting a return register into I3, because
2060 reload can't handle a conflict with constraints of other
2061 inputs. */
2066 }
2074 {
2077 /* If the clobber represents an earlyclobber operand, we must not
2078 substitute an expression containing the clobbered register.
2079 As we do not analyze the constraint strings here, we have to
2080 make the conservative assumption. However, if the register is
2081 a fixed hard reg, the clobber cannot represent any operand;
2082 we leave it up to the machine description to either accept or
2083 reject use-and-clobber patterns. */
2089 }
2091 /* If INSN contains anything volatile, or is an `asm' (whether volatile
2092 or not), reject, unless nothing volatile comes between it and I3 */
2095 {
2096 /* Make sure neither succ nor succ2 contains a volatile reference. */
2101 /* We'll check insns between INSN and I3 below. */
2102 }
2104 /* If INSN is an asm, and DEST is a hard register, reject, since it has
2105 to be an explicit register variable, and was chosen for a reason. */
2111 /* If INSN contains volatile references (specifically volatile MEMs),
2112 we cannot combine across any other volatile references.
2113 Even if INSN doesn't contain volatile references, any intervening
2114 volatile insn might affect machine state. */
2117 ? volatile_refs_p
2124 /* If INSN contains an autoincrement or autodecrement, make sure that
2125 register is not used between there and I3, and not already used in
2126 I3 either. Neither must it be used in PRED or SUCC, if they exist.
2127 Also insist that I3 not be a jump; if it were one
2128 and the incremented register were spilled, we would lose. */
2146 /* Don't combine an insn that follows a CC0-setting insn.
2147 An insn that uses CC0 must not be separated from the one that sets it.
2148 We do, however, allow I2 to follow a CC0-setting insn if that insn
2149 is passed as I1; in that case it will be deleted also.
2150 We also allow combining in this case if all the insns are adjacent
2151 because that would leave the two CC0 insns adjacent as well.
2152 It would be more logical to test whether CC0 occurs inside I1 or I2,
2153 but that would be much slower, and this ought to be equivalent. */
2156 {
2161 }
2163 /* If we get here, we have passed all the tests and the combination is
2164 to be allowed. */
2170 }
2171 \f
2172 /* LOC is the location within I3 that contains its pattern or the component
2173 of a PARALLEL of the pattern. We validate that it is valid for combining.
2175 One problem is if I3 modifies its output, as opposed to replacing it
2176 entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2177 doing so would produce an insn that is not equivalent to the original insns.
2179 Consider:
2181 (set (reg:DI 101) (reg:DI 100))
2182 (set (subreg:SI (reg:DI 101) 0) <foo>)
2184 This is NOT equivalent to:
2186 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2187 (set (reg:DI 101) (reg:DI 100))])
2189 Not only does this modify 100 (in which case it might still be valid
2190 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2192 We can also run into a problem if I2 sets a register that I1
2193 uses and I1 gets directly substituted into I3 (not via I2). In that
2194 case, we would be getting the wrong value of I2DEST into I3, so we
2195 must reject the combination. This case occurs when I2 and I1 both
2196 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2197 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2198 of a SET must prevent combination from occurring. The same situation
2199 can occur for I0, in which case I0_NOT_IN_SRC is set.
2201 Before doing the above check, we first try to expand a field assignment
2202 into a set of logical operations.
2204 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2205 we place a register that is both set and used within I3. If more than one
2206 such register is detected, we fail.
2208 Return 1 if the combination is valid, zero otherwise. */
2210 static int
2213 {
2217 {
2222 rtx subdest;
2229 /* Check for the case where I3 modifies its output, as discussed
2230 above. We don't want to prevent pseudos from being combined
2231 into the address of a MEM, so only prevent the combination if
2232 i1 or i2 set the same MEM. */
2242 /* This is the same test done in can_combine_p except we can't test
2243 all_adjacent; we don't have to, since this instruction will stay
2244 in place, thus we are not considering increasing the lifetime of
2245 INNER_DEST.
2247 Also, if this insn sets a function argument, combining it with
2248 something that might need a spill could clobber a previous
2249 function argument; the all_adjacent test in can_combine_p also
2250 checks this; here, we do a more specific test for this case. */
2260 /* If DEST is used in I3, it is being killed in this insn, so
2261 record that for later. We have to consider paradoxical
2262 subregs here, since they kill the whole register, but we
2263 ignore partial subregs, STRICT_LOW_PART, etc.
2264 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2265 STACK_POINTER_REGNUM, since these are always considered to be
2266 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2274 && (HARD_FRAME_POINTER_IS_FRAME_POINTER
2280 {
2285 }
2286 }
2289 {
2296 }
2299 }
2300 \f
2301 /* Return 1 if X is an arithmetic expression that contains a multiplication
2302 and division. We don't count multiplications by powers of two here. */
2304 static int
2306 {
2308 {
2324 }
2325 }
2326 \f
2327 /* Determine whether INSN can be used in a combination. Return nonzero if
2328 not. This is used in try_combine to detect early some cases where we
2329 can't perform combinations. */
2331 static int
2333 {
2334 rtx set;
2337 /* If this isn't really an insn, we can't do anything.
2338 This can occur when flow deletes an insn that it has merged into an
2339 auto-increment address. */
2343 /* Never combine loads and stores involving hard regs that are likely
2344 to be spilled. The register allocator can usually handle such
2345 reg-reg moves by tying. If we allow the combiner to make
2346 substitutions of likely-spilled regs, reload might die.
2347 As an exception, we allow combinations involving fixed regs; these are
2348 not available to the register allocator so there's no risk involved. */
2362 #ifdef LEAF_REGISTERS
2364 #else
2365 )
2366 #endif
2373 }
2375 struct likely_spilled_retval_info
2376 {
2379 };
2381 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2382 hard registers that are known to be written to / clobbered in full. */
2383 static void
2385 {
2402 else
2405 }
2407 /* Return nonzero iff part of the return value is live during INSN, and
2408 it is likely spilled. This can happen when more than one insn is needed
2409 to copy the return value, e.g. when we consider to combine into the
2410 second copy insn for a complex value. */
2412 static int
2414 {
2416 rtx reg;
2419 /* We assume here that no machine mode needs more than
2420 32 hard registers when the value overlaps with a register
2421 for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2436 /* Disregard parts of the return value that are set later. */
2445 /* Check if any of the (probably) live return value registers is
2446 likely spilled. */
2447 nregs --;
2448 do
2449 {
2455 }
2457 /* Adjust INSN after we made a change to its destination.
2459 Changing the destination can invalidate notes that say something about
2460 the results of the insn and a LOG_LINK pointing to the insn. */
2462 static void
2464 {
2465 /* For notes, be conservative and simply remove them. */
2468 /* The new insn will have a destination that was previously the destination
2469 of an insn just above it. Call distribute_links to make a LOG_LINK from
2470 the next use of that destination. */
2486 }
2488 /* Return TRUE if combine can reuse reg X in mode MODE.
2489 ADDED_SETS is nonzero if the original set is still required. */
2490 static bool
2492 {
2498 /* Don't change between modes with different underlying register sizes,
2499 since this could lead to invalid subregs. */
2505 /* Allow hard registers if the new mode is legal, and occupies no more
2506 registers than the old mode. */
2511 /* Or a pseudo that is only used once. */
2514 && !added_sets
2516 }
2519 /* Check whether X, the destination of a set, refers to part of
2520 the register specified by REG. */
2522 static bool
2524 {
2525 /* Check that reg is an integer mode register. */
2536 }
2538 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2539 Note that the INSN should be deleted *after* removing dead edges, so
2540 that the kept edge is the fallthrough edge for a (set (pc) (pc))
2541 but not for a (set (pc) (label_ref FOO)). */
2543 static void
2545 {
2553 {
2558 /* Remove barriers from the footer if there are any. */
2561 {
2564 else
2568 }
2571 }
2572 }
2574 /* Return whether PAT is a PARALLEL of exactly N register SETs followed
2575 by an arbitrary number of CLOBBERs. */
2576 static bool
2578 {
2593 {
2602 }
2604 }
2606 /* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2607 CLOBBERs), can be split into individual SETs in that order, without
2608 changing semantics. */
2609 static bool
2611 {
2619 {
2628 }
2631 }
2633 /* Return whether X is just a single set, with the source
2634 a general_operand. */
2635 static bool
2637 {
2642 }
2644 /* Callback function to count autoincs. */
2646 static int
2648 {
2652 }
2654 /* Try to combine the insns I0, I1 and I2 into I3.
2655 Here I0, I1 and I2 appear earlier than I3.
2656 I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2657 I3.
2659 If we are combining more than two insns and the resulting insn is not
2660 recognized, try splitting it into two insns. If that happens, I2 and I3
2661 are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2662 Otherwise, I0, I1 and I2 are pseudo-deleted.
2664 Return 0 if the combination does not work. Then nothing is changed.
2665 If we did the combination, return the insn at which combine should
2666 resume scanning.
2668 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2669 new direct jump instruction.
2671 LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2672 been I3 passed to an earlier try_combine within the same basic
2673 block. */
2678 {
2679 /* New patterns for I3 and I2, respectively. */
2683 /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2684 dead. */
2686 /* Total number of SETs to put into I3. */
2688 /* Nonzero if I2's or I1's body now appears in I3. */
2690 /* INSN_CODEs for new I3, new I2, and user of condition code. */
2692 /* Contains I3 if the destination of I3 is used in its source, which means
2693 that the old life of I3 is being killed. If that usage is placed into
2694 I2 and not in I3, a REG_DEAD note must be made. */
2696 /* SET_DEST and SET_SRC of I2, I1 and I0. */
2698 /* Copy of SET_SRC of I1 and I0, if needed. */
2700 /* Set if I2DEST was reused as a scratch register. */
2702 /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2704 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2709 /* Notes that must be added to REG_NOTES in I3 and I2. */
2711 /* Notes that we substituted I3 into I2 instead of the normal case. */
2713 /* Notes that I1, I2 or I3 is a MULT operation. */
2723 rtx temp_expr;
2726 rtx new_other_notes;
2730 /* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2731 never be). */
2735 /* Only try four-insn combinations when there's high likelihood of
2736 success. Look for simple insns, such as loads of constants or
2737 binary operations involving a constant. */
2739 {
2749 {
2752 rtx src;
2757 {
2760 }
2762 ngood++;
2765 nshift++;
2766 }
2768 /* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2769 are likely manipulating its value. Ideally we'll be able to combine
2770 all four insns into a bitfield insertion of some kind.
2772 Note the source in I0 might be inside a sign/zero extension and the
2773 memory modes in I0 and I3 might be different. So extract the address
2774 from the destination of I3 and search for it in the source of I0.
2776 In the event that there's a match but the source/dest do not actually
2777 refer to the same memory, the worst that happens is we try some
2778 combinations that we wouldn't have otherwise. */
2780 /* Ensure the source of SET0 is a MEM, possibly buried inside
2781 an extension. */
2787 /* Ensure the destination of SET3 is a MEM. */
2789 /* Would it be better to extract the base address for the MEM
2790 in SET3 and look for that? I don't have cases where it matters
2791 but I could envision such cases. */
2797 }
2799 /* Exit early if one of the insns involved can't be used for
2800 combinations. */
2811 combine_attempts++;
2814 /* Reset the hard register usage information. */
2818 {
2825 else
2835 }
2837 /* If multiple insns feed into one of I2 or I3, they can be in any
2838 order. To simplify the code below, reorder them in sequence. */
2849 /* First check for one important special case that the code below will
2850 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2851 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2852 we may be able to replace that destination with the destination of I3.
2853 This occurs in the common code where we compute both a quotient and
2854 remainder into a structure, in which case we want to do the computation
2855 directly into the structure to avoid register-register copies.
2857 Note that this case handles both multiple sets in I2 and also cases
2858 where I2 has a number of CLOBBERs inside the PARALLEL.
2860 We make very conservative checks below and only try to handle the
2861 most common cases of this. For example, we only handle the case
2862 where I2 and I3 are adjacent to avoid making difficult register
2863 usage tests. */
2871 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2872 below would need to check what is inside (and reg_overlap_mentioned_p
2873 doesn't support those codes anyway). Don't allow those destinations;
2874 the resulting insn isn't likely to be recognized anyway. */
2880 {
2883 /* Make sure that the destination of I3,
2884 which we are going to substitute into one output of I2,
2885 is not used within another output of I2. We must avoid making this:
2886 (parallel [(set (mem (reg 69)) ...)
2887 (set (reg 69) ...)])
2888 which is not well-defined as to order of actions.
2889 (Besides, reload can't handle output reloads for this.)
2891 The problem can also happen if the dest of I3 is a memory ref,
2892 if another dest in I2 is an indirect memory ref.
2894 Neither can this PARALLEL be an asm. We do not allow combining
2895 that usually (see can_combine_p), so do not here either. */
2898 {
2908 }
2914 {
2915 combine_merges++;
2925 /* Replace the dest in I2 with our dest and make the resulting
2926 insn the new pattern for I3. Then skip to where we validate
2927 the pattern. Everything was set up above. */
2932 }
2933 }
2935 /* If I2 is setting a pseudo to a constant and I3 is setting some
2936 sub-part of it to another constant, merge them by making a new
2937 constant. */
2945 {
2952 {
2957 {
2963 }
2964 }
2965 else
2966 {
2970 {
2973 }
2974 }
2977 {
2978 /* If this is the low part, we're done. */
2980 ;
2981 /* Handle the case where inner is twice the size of outer. */
2985 /* Otherwise give up for now. */
2986 else
2988 }
2991 {
2999 combine_merges++;
3006 /* Replace the source in I2 with the new constant and make the
3007 resulting insn the new pattern for I3. Then skip to where we
3008 validate the pattern. Everything was set up above. */
3014 /* The dest of I3 has been replaced with the dest of I2. */
3017 }
3018 }
3020 /* If we have no I1 and I2 looks like:
3021 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
3022 (set Y OP)])
3023 make up a dummy I1 that is
3024 (set Y OP)
3025 and change I2 to be
3026 (set (reg:CC X) (compare:CC Y (const_int 0)))
3028 (We can ignore any trailing CLOBBERs.)
3030 This undoes a previous combination and allows us to match a branch-and-
3031 decrement insn. */
3043 {
3044 /* We make I1 with the same INSN_UID as I2. This gives it
3045 the same DF_INSN_LUID for value tracking. Our fake I1 will
3046 never appear in the insn stream so giving it the same INSN_UID
3047 as I2 will not cause a problem. */
3060 }
3062 /* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
3063 make those two SETs separate I1 and I2 insns, and make an I0 that is
3064 the original I1. */
3072 {
3073 /* If there is no I1, there is no I0 either. */
3076 /* We make I1 with the same INSN_UID as I2. This gives it
3077 the same DF_INSN_LUID for value tracking. Our fake I1 will
3078 never appear in the insn stream so giving it the same INSN_UID
3079 as I2 will not cause a problem. */
3087 }
3089 /* Verify that I2 and maybe I1 and I0 can be combined into I3. */
3091 {
3096 }
3098 {
3103 }
3105 {
3110 }
3112 /* Record whether i2 and i3 are trivial moves. */
3116 /* Record whether I2DEST is used in I2SRC and similarly for the other
3117 cases. Knowing this will help in register status updating below. */
3128 /* For the earlier insns, determine which of the subsequent ones they
3129 feed. */
3136 /* Ensure that I3's pattern can be the destination of combines. */
3142 {
3145 }
3147 /* See if any of the insns is a MULT operation. Unless one is, we will
3148 reject a combination that is, since it must be slower. Be conservative
3149 here. */
3157 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3158 We used to do this EXCEPT in one case: I3 has a post-inc in an
3159 output operand. However, that exception can give rise to insns like
3160 mov r3,(r3)+
3161 which is a famous insn on the PDP-11 where the value of r3 used as the
3162 source was model-dependent. Avoid this sort of thing. */
3164 #if 0
3170 /* It's not the exception. */
3171 #endif
3173 {
3174 rtx link;
3180 {
3183 }
3184 }
3186 /* See if the SETs in I1 or I2 need to be kept around in the merged
3187 instruction: whenever the value set there is still needed past I3.
3188 For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3190 For the SET in I1, we have two cases: if I1 and I2 independently feed
3191 into I3, the set in I1 needs to be kept around unless I1DEST dies
3192 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3193 in I1 needs to be kept around unless I1DEST dies or is set in either
3194 I2 or I3. The same considerations apply to I0. */
3201 else
3209 else
3212 /* We are about to copy insns for the case where they need to be kept
3213 around. Check that they can be copied in the merged instruction. */
3219 {
3222 }
3224 /* Count how many auto_inc expressions there were in the original insns;
3225 we need to have the same number in the resulting patterns. */
3234 /* If the set in I2 needs to be kept around, we must make a copy of
3235 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3236 PATTERN (I2), we are only substituting for the original I1DEST, not into
3237 an already-substituted copy. This also prevents making self-referential
3238 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3239 I2DEST. */
3242 {
3245 else
3247 }
3250 {
3253 else
3255 }
3258 {
3261 else
3263 }
3265 combine_merges++;
3267 /* Substitute in the latest insn for the regs set by the earlier ones. */
3273 /* Many machines that don't use CC0 have insns that can both perform an
3274 arithmetic operation and set the condition code. These operations will
3275 be represented as a PARALLEL with the first element of the vector
3276 being a COMPARE of an arithmetic operation with the constant zero.
3277 The second element of the vector will set some pseudo to the result
3278 of the same arithmetic operation. If we simplify the COMPARE, we won't
3279 match such a pattern and so will generate an extra insn. Here we test
3280 for this case, where both the comparison and the operation result are
3281 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3282 I2SRC. Later we will make the PARALLEL that contains I2. */
3288 {
3289 rtx newpat_dest;
3295 scalar_int_mode mode;
3304 {
3310 }
3312 /* Do the rest only if op1 is const0_rtx, which may be the
3313 result of simplification. */
3315 {
3316 /* If a single use of the CC is found, prepare to modify it
3317 when SELECT_CC_MODE returns a new CC-class mode, or when
3318 the above simplify_compare_const() returned a new comparison
3319 operator. undobuf.other_insn is assigned the CC use insn
3320 when modifying it. */
3322 {
3323 #ifdef SELECT_CC_MODE
3324 machine_mode new_mode
3329 {
3334 else
3335 {
3338 }
3339 }
3340 #endif
3341 /* Cases for modifying the CC-using comparison. */
3343 /* ??? Do we need to verify the zero rtx? */
3345 {
3346 /* Replace cc_use_loc with entire new RTX. */
3351 }
3353 {
3354 /* Just replace the CC reg with a new mode. */
3357 }
3358 }
3360 /* Now we modify the current newpat:
3361 First, SET_DEST(newpat) is updated if the CC mode has been
3362 altered. For targets without SELECT_CC_MODE, this should be
3363 optimized away. */
3366 /* This is always done to propagate i2src into newpat. */
3369 /* Create new version of i2pat if needed; the below PARALLEL
3370 creation needs this to work correctly. */
3374 }
3375 }
3378 {
3379 /* It is possible that the source of I2 or I1 may be performing
3380 an unneeded operation, such as a ZERO_EXTEND of something
3381 that is known to have the high part zero. Handle that case
3382 by letting subst look at the inner insns.
3384 Another way to do this would be to have a function that tries
3385 to simplify a single insn instead of merging two or more
3386 insns. We don't do this because of the potential of infinite
3387 loops and because of the potential extra memory required.
3388 However, doing it the way we are is a bit of a kludge and
3389 doesn't catch all cases.
3391 But only do this if -fexpensive-optimizations since it slows
3392 things down and doesn't usually win.
3394 This is not done in the COMPARE case above because the
3395 unmodified I2PAT is used in the PARALLEL and so a pattern
3396 with a modified I2SRC would not match. */
3399 {
3400 /* Pass pc_rtx so no substitutions are done, just
3401 simplifications. */
3403 {
3406 }
3410 }
3415 /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3416 copy of I2SRC each time we substitute it, in order to avoid creating
3417 self-referential RTL when we will be substituting I1SRC for I1DEST
3418 later. Likewise if I0 feeds into I2, either directly or indirectly
3419 through I1, and I0DEST is in I0SRC. */
3426 /* Record whether I2's body now appears within I3's body. */
3428 }
3430 /* If we already got a failure, don't try to do more. Otherwise, try to
3431 substitute I1 if we have it. */
3434 {
3435 /* Before we can do this substitution, we must redo the test done
3436 above (see detailed comments there) that ensures I1DEST isn't
3437 mentioned in any SETs in NEWPAT that are field assignments. */
3440 {
3443 }
3448 /* If the following substitution will modify I1SRC, make a copy of it
3449 for the case where it is substituted for I1DEST in I2PAT later. */
3453 /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3454 copy of I1SRC each time we substitute it, in order to avoid creating
3455 self-referential RTL when we will be substituting I0SRC for I0DEST
3456 later. */
3461 /* Record whether I1's body now appears within I3's body. */
3463 }
3465 /* Likewise for I0 if we have it. */
3468 {
3471 {
3474 }
3476 /* If the following substitution will modify I0SRC, make a copy of it
3477 for the case where it is substituted for I0DEST in I1PAT later. */
3480 /* And a copy for I0DEST in I2PAT substitution. */
3489 }
3492 {
3497 {
3502 }
3503 }
3505 /* Fail if an autoincrement side-effect has been duplicated. Be careful
3506 to count all the ways that I2SRC and I1SRC can be used. */
3517 /* Fail if we tried to make a new register. */
3519 /* Fail if we couldn't do something and have a CLOBBER. */
3521 /* Fail if this new pattern is a MULT and we didn't have one before
3522 at the outer level. */
3525 {
3528 }
3530 /* If the actions of the earlier insns must be kept
3531 in addition to substituting them into the latest one,
3532 we must make a new PARALLEL for the latest insn
3533 to hold additional the SETs. */
3536 {
3538 combine_extras++;
3541 {
3547 }
3548 else
3549 {
3554 }
3560 {
3566 }
3568 {
3577 }
3578 }
3580 validate_replacement:
3582 /* Note which hard regs this insn has as inputs. */
3585 /* If recog_for_combine fails, it strips existing clobbers. If we'll
3586 consider splitting this pattern, we might need these clobbers. */
3589 {
3595 }
3597 /* We have recognized nothing yet. */
3600 /* See if this is a PARALLEL of two SETs where one SET's destination is
3601 a register that is unused and this isn't marked as an instruction that
3602 might trap in an EH region. In that case, we just need the other SET.
3603 We prefer this over the PARALLEL.
3605 This can occur when simplifying a divmod insn. We *must* test for this
3606 case here because the code below that splits two independent SETs doesn't
3607 handle this case correctly when it updates the register status.
3609 It's pointless doing this if we originally had two sets, one from
3610 i3, and one from i2. Combining then splitting the parallel results
3611 in the original i2 again plus an invalid insn (which we delete).
3612 The net effect is only to move instructions around, which makes
3613 debug info less accurate.
3615 If the remaining SET came from I2 its destination should not be used
3616 between I2 and I3. See PR82024. */
3621 {
3632 {
3635 }
3644 {
3649 {
3655 }
3656 }
3660 }
3662 /* Is the result of combination a valid instruction? */
3666 /* If we were combining three insns and the result is a simple SET
3667 with no ASM_OPERANDS that wasn't recognized, try to split it into two
3668 insns. There are two ways to do this. It can be split using a
3669 machine-specific method (like when you have an addition of a large
3670 constant) or by combine in the function find_split_point. */
3674 {
3678 /* See if the MD file can split NEWPAT. If it can't, see if letting it
3679 use I2DEST as a scratch register will help. In the latter case,
3680 convert I2DEST to the mode of the source of NEWPAT if we can. */
3684 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3685 inputs of NEWPAT. */
3687 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3688 possible to try that as a scratch reg. This would require adding
3689 more code to make it work though. */
3692 {
3695 /* ??? Reusing i2dest without resetting the reg_stat entry for it
3696 (temporarily, until we are committed to this instruction
3697 combination) does not work: for example, any call to nonzero_bits
3698 on the register (from a splitter in the MD file, for example)
3699 will get the old information, which is invalid.
3701 Since nowadays we can create registers during combine just fine,
3702 we should just create a new one here, not reuse i2dest. */
3704 /* First try to split using the original register as a
3705 scratch register. */
3709 i2dest)));
3712 /* If that didn't work, try changing the mode of I2DEST if
3713 we can. */
3718 {
3720 rtx ni2dest;
3724 else
3725 {
3728 }
3730 parallel = (gen_rtx_PARALLEL
3734 ni2dest))));
3739 {
3747 }
3748 }
3751 }
3753 /* If recog_for_combine has discarded clobbers, try to use them
3754 again for the split. */
3756 {
3759 }
3762 {
3767 }
3771 {
3781 /* If I2 or I3 has multiple SETs, we won't know how to track
3782 register status, so don't use these insns. If I2's destination
3783 is used between I2 and I3, we also can't use these insns. */
3793 /* It is possible that both insns now set the destination of I3.
3794 If so, we must show an extra use of it. */
3797 {
3816 }
3817 }
3819 /* If we can split it and use I2DEST, go ahead and see if that
3820 helps things be recognized. Verify that none of the registers
3821 are set between I2 and I3. */
3825 /* We need I2DEST in the proper mode. If it is a hard register
3826 or the only use of a pseudo, we can change its mode.
3827 Make sure we don't change a hard register to have a mode that
3828 isn't valid for it, or change the number of registers. */
3835 /* We can't overwrite I2DEST if its value is still used by
3836 NEWPAT. */
3838 {
3847 /* *SPLIT may be part of I2SRC, so make sure we have the
3848 original expression around for later debug processing.
3849 We should not need I2SRC any more in other cases. */
3852 else
3855 /* Get NEWDEST as a register in the proper mode. We have already
3856 validated that we can do this. */
3858 {
3861 else
3862 {
3865 }
3866 }
3868 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3869 an ASHIFT. This can occur if it was inside a PLUS and hence
3870 appeared to be a memory address. This is a kludge. */
3875 {
3879 /* Update split_code because we may not have a multiply
3880 anymore. */
3882 }
3884 /* Similarly for (plus (mult FOO (const_int pow2))). */
3890 {
3895 i_rtx));
3896 /* Update split_code because we may not have a multiply
3897 anymore. */
3899 }
3901 #ifdef INSN_SCHEDULING
3902 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3903 be written as a ZERO_EXTEND. */
3905 {
3906 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3907 what it really is. */
3912 else
3915 }
3916 #endif
3918 /* Attempt to split binary operators using arithmetic identities. */
3922 {
3929 /* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3931 {
3936 }
3937 /* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3944 {
3950 /* Split both "((X op Y) op X) op Y" and
3951 "((X op Y) op Y) op X" as "T op T" where T is
3952 "X op Y". */
3955 {
3960 }
3961 /* Split "((X op X) op Y) op Y)" as "T op T" where
3962 T is "X op Y". */
3964 {
3970 }
3971 }
3972 }
3975 {
3978 }
3982 /* recog_for_combine might have added CLOBBERs to newi2pat.
3983 Make sure NEWPAT does not depend on the clobbered regs. */
3987 {
3990 {
3993 }
3994 }
3996 /* If the split point was a MULT and we didn't have one before,
3997 don't use one now. */
4000 }
4001 }
4003 /* Check for a case where we loaded from memory in a narrow mode and
4004 then sign extended it, but we need both registers. In that case,
4005 we have a PARALLEL with both loads from the same memory location.
4006 We can split this into a load from memory followed by a register-register
4007 copy. This saves at least one insn, more if register allocation can
4008 eliminate the copy.
4010 We cannot do this if the destination of the first assignment is a
4011 condition code register or cc0. We eliminate this case by making sure
4012 the SET_DEST and SET_SRC have the same mode.
4014 We cannot do this if the destination of the second assignment is
4015 a register that we have already assumed is zero-extended. Similarly
4016 for a SUBREG of such a register. */
4035 BITS_PER_WORD)
4037 HOST_BITS_PER_INT)
4045 BITS_PER_WORD)
4047 HOST_BITS_PER_INT)
4054 {
4055 rtx ni2dest;
4069 }
4071 /* Similarly, check for a case where we have a PARALLEL of two independent
4072 SETs but we started with three insns. In this case, we can do the sets
4073 as two separate insns. This case occurs when some SET allows two
4074 other insns to combine, but the destination of that SET is still live.
4076 Also do this if we started with two insns and (at least) one of the
4077 resulting sets is a noop; this noop will be deleted later.
4079 Also do this if we started with two insns neither of which was a simple
4080 move. */
4087 && (i1
4101 {
4105 /* Normally, it doesn't matter which of the two is done first,
4106 but the one that references cc0 can't be the second, and
4107 one which uses any regs/memory set in between i2 and i3 can't
4108 be first. The PARALLEL might also have been pre-existing in i3,
4109 so we need to make sure that we won't wrongly hoist a SET to i2
4110 that would conflict with a death note present in there, or would
4111 have its dest modified between i2 and i3. */
4120 /* If I3 is a jump, ensure that set0 is a jump so that
4121 we do not create invalid RTL. */
4123 )
4124 {
4127 }
4136 /* If I3 is a jump, ensure that set1 is a jump so that
4137 we do not create invalid RTL. */
4139 )
4140 {
4143 }
4144 else
4145 {
4148 }
4153 {
4154 /* recog_for_combine might have added CLOBBERs to newi2pat.
4155 Make sure NEWPAT does not depend on the clobbered regs. */
4157 {
4160 {
4163 {
4166 }
4167 }
4168 }
4174 }
4175 }
4177 /* If it still isn't recognized, fail and change things back the way they
4178 were. */
4180 /* Is the result a reasonable ASM_OPERANDS? */
4182 {
4185 }
4187 /* If we had to change another insn, make sure it is valid also. */
4189 {
4197 {
4200 }
4201 }
4203 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
4204 they are adjacent to each other or not. */
4206 {
4210 {
4213 }
4214 }
4216 /* Only allow this combination if insn_cost reports that the
4217 replacement instructions are cheaper than the originals. */
4219 {
4222 }
4225 {
4230 {
4235 /* Temporarily revert mode back. */
4239 {
4240 /* If we used i2dest as a scratch register with a
4241 different mode, substitute it for the original
4242 i2src while its original mode is temporarily
4243 restored, and then clear i2scratch so that we don't
4244 do it again later. */
4246 this_basic_block);
4248 /* Put back the new mode. */
4250 }
4251 else
4252 {
4257 {
4260 }
4261 else
4262 {
4269 }
4271 /* We're dealing with a reg that changed mode but not
4272 meaning, so we want to turn it into a subreg for
4273 the new mode. However, because of REG sharing and
4274 because its mode had already changed, we have to do
4275 it in two steps. First, replace any debug uses of
4276 reg, with its original mode temporarily restored,
4277 with this copy we have created; then, replace the
4278 copy with the SUBREG of the original shared reg,
4279 once again changed to the new mode. */
4281 this_basic_block);
4285 this_basic_block);
4286 }
4287 }
4288 }
4290 /* If we will be able to accept this, we have made a
4291 change to the destination of I3. This requires us to
4292 do a few adjustments. */
4295 {
4298 }
4300 /* We now know that we can do this combination. Merge the insns and
4301 update the status of registers and LOG_LINKS. */
4304 {
4309 /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4310 ensure that they are still valid. Then add any non-duplicate
4311 notes added by recog_for_combine. */
4313 {
4322 /* Simply drop equal note since it may be no longer valid
4323 for other_insn. It may be possible to record that CC
4324 register is changed and only discard those notes, but
4325 in practice it's unnecessary complication and doesn't
4326 give any meaningful improvement.
4328 See PR78559. */
4332 }
4336 NULL_RTX);
4337 }
4340 {
4341 /* I3 now uses what used to be its destination and which is now
4342 I2's destination. This requires us to do a few adjustments. */
4345 }
4348 {
4349 /* We might need a LOG_LINK from I3 to I2. But then we used to
4350 have one, so we still will.
4352 However, some later insn might be using I2's dest and have
4353 a LOG_LINK pointing at I3. We should change it to point at
4354 I2 instead. */
4356 /* newi2pat is usually a SET here; however, recog_for_combine might
4357 have added some clobbers. */
4362 /* It can only be a SET of a REG or of a SUBREG of a REG. */
4367 !done
4368 && insn
4372 {
4376 {
4380 }
4381 }
4382 }
4384 {
4389 /* Compute which registers we expect to eliminate. newi2pat may be setting
4390 either i3dest or i2dest, so we must check it. */
4393 || !i2dest_killed
4395 /* For i1, we need to compute both local elimination and global
4396 elimination information with respect to newi2pat because i1dest
4397 may be the same as i3dest, in which case newi2pat may be setting
4398 i1dest. Global information is used when distributing REG_DEAD
4399 note for i2 and i3, in which case it does matter if newi2pat sets
4400 i1dest or not.
4402 Local information is used when distributing REG_DEAD note for i1,
4403 in which case it doesn't matter if newi2pat sets i1dest or not.
4404 See PR62151, if we have four insns combination:
4405 i0: r0 <- i0src
4406 i1: r1 <- i1src (using r0)
4407 REG_DEAD (r0)
4408 i2: r0 <- i2src (using r1)
4409 i3: r3 <- i3src (using r0)
4410 ix: using r0
4411 From i1's point of view, r0 is eliminated, no matter if it is set
4412 by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4413 should be discarded.
4415 Note local information only affects cases in forms like "I1->I2->I3",
4416 "I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4417 "I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4418 i0dest anyway. */
4420 || !i1dest_killed
4425 /* Same case as i1. */
4432 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4433 clear them. */
4441 /* Ensure that we do not have something that should not be shared but
4442 occurs multiple times in the new insns. Check this by first
4443 resetting all the `used' flags and then copying anything is shared. */
4467 {
4470 {
4472 {
4473 /* I2SRC must still be meaningful at this point. Some
4474 splitting operations can invalidate I2SRC, but those
4475 operations do not apply to calls. */
4479 }
4486 }
4487 }
4492 /* We had one special case above where I2 had more than one set and
4493 we replaced a destination of one of those sets with the destination
4494 of I3. In that case, we have to update LOG_LINKS of insns later
4495 in this basic block. Note that this (expensive) case is rare.
4497 Also, in this case, we must pretend that all REG_NOTEs for I2
4498 actually came from I3, so that REG_UNUSED notes from I2 will be
4499 properly handled. */
4502 {
4511 temp_insn
4521 {
4526 }
4527 else
4530 }
4538 {
4541 this_basic_block);
4544 }
4545 else
4546 {
4549 this_basic_block);
4551 }
4554 {
4559 this_basic_block);
4561 }
4564 {
4569 this_basic_block);
4571 }
4573 /* Get death notes for everything that is now used in either I3 or
4574 I2 and used to die in a previous insn. If we built two new
4575 patterns, move from I1 to I2 then I2 to I3 so that we get the
4576 proper movement on registers that I2 modifies. */
4582 else
4588 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4605 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
4606 know these are REG_UNUSED and want them to go to the desired insn,
4607 so we always pass it as i3. */
4611 NULL_RTX);
4615 NULL_RTX);
4617 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
4618 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4619 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4620 in that case, it might delete I2. Similarly for I2 and I1.
4621 Show an additional death due to the REG_DEAD note we make here. If
4622 we discard it in distribute_notes, we will decrement it again. */
4625 {
4630 else
4633 }
4636 {
4641 else
4644 }
4647 {
4652 else
4655 }
4658 {
4663 else
4666 }
4674 {
4679 /* The insn that used to set this register doesn't exist, and
4680 this life of the register may not exist either. See if one of
4681 I3's links points to an insn that sets I2DEST. If it does,
4682 that is now the last known value for I2DEST. If we don't update
4683 this and I2 set the register to a value that depended on its old
4684 contents, we will get confused. If this insn is used, thing
4685 will be set correctly in combine_instructions. */
4693 /* If the reg formerly set in I2 died only once and that was in I3,
4694 zero its use count so it won't make `reload' do any work. */
4697 && ! i2dest_in_i2src
4700 }
4703 {
4716 && ! i1dest_in_i1src
4719 }
4722 {
4735 && ! i0dest_in_i0src
4738 }
4740 /* Update reg_stat[].nonzero_bits et al for any changes that may have
4741 been made to this insn. The order is important, because newi2pat
4742 can affect nonzero_bits of newpat. */
4746 }
4749 {
4751 {
4754 }
4756 }
4759 {
4761 {
4764 }
4766 }
4769 {
4771 {
4774 }
4776 }
4779 {
4781 {
4784 }
4786 }
4789 {
4791 {
4794 }
4796 }
4798 /* Set new_direct_jump_p if a new return or simple jump instruction
4799 has been created. Adjust the CFG accordingly. */
4801 {
4805 }
4810 {
4813 }
4817 {
4823 }
4828 {
4834 }
4836 /* A noop might also need cleaning up of CFG, if it comes from the
4837 simplification of a jump. */
4842 {
4845 }
4852 {
4855 }
4857 combine_successes++;
4867 }
4868 \f
4869 /* Get a marker for undoing to the current state. */
4873 {
4875 }
4877 /* Undo the modifications up to the marker. */
4879 static void
4881 {
4885 {
4890 {
4905 }
4909 }
4912 }
4914 /* Undo all the modifications recorded in undobuf. */
4916 static void
4918 {
4920 }
4922 /* We've committed to accepting the changes we made. Move all
4923 of the undos to the free list. */
4925 static void
4927 {
4931 {
4935 }
4937 }
4938 \f
4939 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4940 where we have an arithmetic expression and return that point. LOC will
4941 be inside INSN.
4943 try_combine will call this function to see if an insn can be split into
4944 two insns. */
4948 {
4958 /* First special-case some codes. */
4960 {
4962 #ifdef INSN_SCHEDULING
4963 /* If we are making a paradoxical SUBREG invalid, it becomes a split
4964 point. */
4967 #endif
4971 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4972 using LO_SUM and HIGH. */
4975 {
4983 }
4985 /* If we have a PLUS whose second operand is a constant and the
4986 address is not valid, perhaps we can split it up using
4987 the machine-specific way to split large constants. We use
4988 the first pseudo-reg (one of the virtual regs) as a placeholder;
4989 it will not remain in the result. */
4994 {
4997 subst_insn);
4999 /* This should have produced two insns, each of which sets our
5000 placeholder. If the source of the second is a valid address,
5001 we can put both sources together and make a split point
5002 in the middle. */
5015 && memory_address_addr_space_p
5018 {
5022 /* Replace the placeholder in SRC2 with SRC1. If we can
5023 find where in SRC2 it was placed, that can become our
5024 split point and we can replace this address with SRC2.
5025 Just try two obvious places. */
5036 {
5039 }
5040 }
5042 /* If that didn't work and we have a nested plus, like:
5043 ((REG1 * CONST1) + REG2) + CONST2 and (REG1 + REG2) + CONST2
5044 is valid address, try to split (REG1 * CONST1). */
5051 {
5056 {
5059 }
5061 }
5068 {
5073 {
5076 }
5078 }
5080 /* If that didn't work, perhaps the first operand is complex and
5081 needs to be computed separately, so make a split point there.
5082 This will occur on machines that just support REG + CONST
5083 and have a constant moved through some previous computation. */
5088 }
5090 /* If we have a PLUS whose first operand is complex, try computing it
5091 separately by making a split there. */
5102 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
5103 ZERO_EXTRACT, the most likely reason why this doesn't match is that
5104 we need to put the operand into a register. So split at that
5105 point. */
5115 /* See if we can split SET_SRC as it stands. */
5120 /* See if we can split SET_DEST as it stands. */
5125 /* See if this is a bitfield assignment with everything constant. If
5126 so, this is an IOR of an AND, so split it into that. */
5138 {
5143 unsigned HOST_WIDE_INT mask
5145 rtx or_mask;
5154 else
5155 {
5161 or_mask));
5162 }
5169 }
5171 /* Otherwise, see if this is an operation that we can split into two.
5172 If so, try to split that. */
5176 {
5178 /* If we are AND'ing with a large constant that is only a single
5179 bit and the result is only being used in a context where we
5180 need to know if it is zero or nonzero, replace it with a bit
5181 extraction. This will avoid the large constant, which might
5182 have taken more than one insn to make. If the constant were
5183 not a valid argument to the AND but took only one insn to make,
5184 this is no worse, but if it took more than one insn, it will
5185 be better. */
5195 {
5200 {
5203 }
5204 }
5208 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5209 is known to be on, this can be converted into a NEG of a shift. */
5215 {
5222 pos_rtx)));
5227 }
5233 /* We can't optimize if either mode is a partial integer
5234 mode as we don't know how many bits are significant
5235 in those modes. */
5251 {
5259 }
5264 }
5270 {
5271 /* For unsigned, we have a choice of a shift followed by an
5272 AND or two shifts. Use two shifts for field sizes where the
5273 constant might be too large. We assume here that we can
5274 always at least get 8-bit constants in an AND insn, which is
5275 true for every current RISC. */
5278 {
5279 unsigned HOST_WIDE_INT mask
5284 gen_rtx_LSHIFTRT
5291 }
5292 else
5293 {
5297 gen_rtx_fmt_ee
5307 }
5308 }
5310 /* See if this is a simple operation with a constant as the second
5311 operand. It might be that this constant is out of range and hence
5312 could be used as a split point. */
5320 /* Finally, see if this is a simple operation with its first operand
5321 not in a register. The operation might require this operand in a
5322 register, so return it as a split point. We can always do this
5323 because if the first operand were another operation, we would have
5324 already found it as a split point. */
5333 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5334 it is better to write this as (not (ior A B)) so we can split it.
5335 Similarly for IOR. */
5337 {
5345 }
5347 /* Many RISC machines have a large set of logical insns. If the
5348 second operand is a NOT, put it first so we will try to split the
5349 other operand first. */
5351 {
5355 }
5360 /* Canonicalization can produce (minus A (mult B C)), where C is a
5361 constant. It may be better to try splitting (plus (mult B -C) A)
5362 instead if this isn't a multiply by a power of two. */
5366 {
5374 mode)),
5377 }
5379 /* Split at a multiply-accumulate instruction. However if this is
5380 the SET_SRC, we likely do not have such an instruction and it's
5381 worthless to try this split. */
5390 }
5392 /* Otherwise, select our actions depending on our rtx class. */
5394 {
5400 /* fall through */
5408 /* fall through */
5410 /* Some machines have (and (shift ...) ...) insns. If X is not
5411 an AND, but XEXP (X, 0) is, use it as our split point. */
5421 /* Otherwise, we don't have a split point. */
5423 }
5424 }
5425 \f
5426 /* Throughout X, replace FROM with TO, and return the result.
5427 The result is TO if X is FROM;
5428 otherwise the result is X, but its contents may have been modified.
5429 If they were modified, a record was made in undobuf so that
5430 undo_all will (among other things) return X to its original state.
5432 If the number of changes necessary is too much to record to undo,
5433 the excess changes are not made, so the result is invalid.
5434 The changes already made can still be undone.
5435 undobuf.num_undo is incremented for such changes, so by testing that
5436 the caller can tell whether the result is valid.
5438 `n_occurrences' is incremented each time FROM is replaced.
5440 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5442 IN_COND is nonzero if we are at the top level of a condition.
5444 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
5445 by copying if `n_occurrences' is nonzero. */
5447 static rtx
5449 {
5454 rtx new_rtx;
5456 /* Two expressions are equal if they are identical copies of a shared
5457 RTX or if they are both registers with the same register number
5458 and mode. */
5460 #define COMBINE_RTX_EQUAL_P(X,Y) \
5461 ((X) == (Y) \
5462 || (REG_P (X) && REG_P (Y) \
5463 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5465 /* Do not substitute into clobbers of regs -- this will never result in
5466 valid RTL. */
5471 {
5472 n_occurrences++;
5474 }
5476 /* If X and FROM are the same register but different modes, they
5477 will not have been seen as equal above. However, the log links code
5478 will make a LOG_LINKS entry for that case. If we do nothing, we
5479 will try to rerecognize our original insn and, when it succeeds,
5480 we will delete the feeding insn, which is incorrect.
5482 So force this insn not to match in this (rare) case. */
5487 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5488 of which may contain things that can be combined. */
5492 /* It is possible to have a subexpression appear twice in the insn.
5493 Suppose that FROM is a register that appears within TO.
5494 Then, after that subexpression has been scanned once by `subst',
5495 the second time it is scanned, TO may be found. If we were
5496 to scan TO here, we would find FROM within it and create a
5497 self-referent rtl structure which is completely wrong. */
5501 /* Parallel asm_operands need special attention because all of the
5502 inputs are shared across the arms. Furthermore, unsharing the
5503 rtl results in recognition failures. Failure to handle this case
5504 specially can result in circular rtl.
5506 Solve this by doing a normal pass across the first entry of the
5507 parallel, and only processing the SET_DESTs of the subsequent
5508 entries. Ug. */
5513 {
5516 /* If this substitution failed, this whole thing fails. */
5524 {
5530 {
5533 /* If this substitution failed, this whole thing fails. */
5539 }
5540 }
5541 }
5542 else
5543 {
5547 /* We don't need to process a SET_DEST that is a register, CC0,
5548 or PC, so set up to skip this common case. All other cases
5549 where we want to suppress replacing something inside a
5550 SET_SRC are handled via the IN_DEST operand. */
5557 /* Trying to simplify the operands of a widening MULT is not likely
5558 to create RTL matching a machine insn. */
5570 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5571 constant. */
5576 {
5578 {
5581 {
5583 {
5586 n_occurrences++;
5587 }
5588 else
5589 {
5591 unique_copy);
5593 /* If this substitution failed, this whole thing
5594 fails. */
5598 }
5601 }
5602 }
5604 {
5605 /* If this is a register being set, ignore it. */
5612 ;
5615 {
5616 /* In general, don't install a subreg involving two
5617 modes not tieable. It can worsen register
5618 allocation, and can even make invalid reload
5619 insns, since the reg inside may need to be copied
5620 from in the outside mode, and that may be invalid
5621 if it is an fp reg copied in integer mode.
5623 We allow two exceptions to this: It is valid if
5624 it is inside another SUBREG and the mode of that
5625 SUBREG and the mode of the inside of TO is
5626 tieable and it is valid if X is a SET that copies
5627 FROM to CC0. */
5635 && (!HAVE_cc0
5650 n_occurrences++;
5651 }
5652 else
5653 /* If we are in a SET_DEST, suppress most cases unless we
5654 have gone inside a MEM, in which case we want to
5655 simplify the address. We assume here that things that
5656 are actually part of the destination have their inner
5657 parts in the first expression. This is true for SUBREG,
5658 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5659 things aside from REG and MEM that should appear in a
5660 SET_DEST. */
5662 (((in_dest
5668 unique_copy);
5670 /* If we found that we will have to reject this combination,
5671 indicate that by returning the CLOBBER ourselves, rather than
5672 an expression containing it. This will speed things up as
5673 well as prevent accidents where two CLOBBERs are considered
5674 to be equal, thus producing an incorrect simplification. */
5680 {
5688 }
5693 {
5695 new_rtx,
5699 }
5700 else
5702 }
5703 }
5704 }
5706 /* Check if we are loading something from the constant pool via float
5707 extension; in this case we would undo compress_float_constant
5708 optimization and degenerate constant load to an immediate value. */
5712 {
5716 }
5718 /* Try to simplify X. If the simplification changed the code, it is likely
5719 that further simplification will help, so loop, but limit the number
5720 of repetitions that will be performed. */
5723 {
5724 /* If X is sufficiently simple, don't bother trying to do anything
5725 with it. */
5734 /* We no longer know the original mode of operand 0 since we
5735 have changed the form of X) */
5737 }
5740 }
5741 \f
5742 /* If X is a commutative operation whose operands are not in the canonical
5743 order, use substitutions to swap them. */
5745 static void
5747 {
5750 {
5754 }
5755 }
5757 /* Simplify X, a piece of RTL. We just operate on the expression at the
5758 outer level; call `subst' to simplify recursively. Return the new
5759 expression.
5761 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
5762 if we are inside a SET_DEST. IN_COND is nonzero if we are at the top level
5763 of a condition. */
5765 static rtx
5768 {
5771 scalar_int_mode int_mode;
5772 rtx temp;
5775 /* If this is a commutative operation, put a constant last and a complex
5776 expression first. We don't need to do this for comparisons here. */
5779 /* Try to fold this expression in case we have constants that weren't
5780 present before. */
5783 {
5791 {
5794 {
5798 }
5801 }
5814 }
5817 {
5822 }
5824 /* If this is a simple operation applied to an IF_THEN_ELSE, try
5825 applying it to the arms of the IF_THEN_ELSE. This often simplifies
5826 things. Check for cases where both arms are testing the same
5827 condition.
5829 Don't do anything if all operands are very simple. */
5842 {
5847 /* If everything is a comparison, what we have is highly unlikely
5848 to be simpler, so don't use it. */
5851 /* Similarly, if we end up with one of the expressions the same
5852 as the original, it is certainly not simpler. */
5855 {
5862 /* Simplify the alternative arms; this may collapse the true and
5863 false arms to store-flag values. Be careful to use copy_rtx
5864 here since true_rtx or false_rtx might share RTL with x as a
5865 result of the if_then_else_cond call above. */
5869 /* If true_rtx and false_rtx are not general_operands, an if_then_else
5870 is unlikely to be simpler. */
5873 {
5876 /* Restarting if we generate a store-flag expression will cause
5877 us to loop. Just drop through in this case. */
5879 /* If the result values are STORE_FLAG_VALUE and zero, we can
5880 just make the comparison operation. */
5891 /* Likewise, we can make the negate of a comparison operation
5892 if the result values are - STORE_FLAG_VALUE and zero. */
5900 mode);
5911 mode);
5915 }
5916 }
5917 }
5919 /* First see if we can apply the inverse distributive law. */
5922 {
5926 }
5928 /* If CODE is an associative operation not otherwise handled, see if we
5929 can associate some operands. This can win if they are constants or
5930 if they are logically related (i.e. (a & b) & a). */
5936 {
5938 {
5942 rtx inner;
5944 /* Make sure we pass the constant operand if any as the second
5945 one if this is a commutative operation. */
5953 /* For commutative operations, try the other pair if that one
5954 didn't simplify. */
5956 {
5961 }
5965 }
5966 }
5968 /* A little bit of algebraic simplification here. */
5970 {
5972 /* Ensure that our address has any ASHIFTs converted to MULT in case
5973 address-recognizing predicates are called later. */
5982 /* See if this can be moved to simplify_subreg. */
5985 /* Don't call gen_lowpart if the inner mode
5986 is VOIDmode and we cannot simplify it, as SUBREG without
5987 inner mode is invalid. */
5994 {
5995 rtx temp;
6001 /* If op is known to have all lower bits zero, the result is zero. */
6015 }
6017 /* Don't change the mode of the MEM if that would change the meaning
6018 of the address. */
6025 /* Note that we cannot do any narrowing for non-constants since
6026 we might have been counting on using the fact that some bits were
6027 zero. We now do this in the SET. */
6034 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
6035 replaced by (lshiftrt X C). This will convert
6036 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
6044 /* If X has only a single bit that might be nonzero, say, bit I, convert
6045 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
6046 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
6047 (sign_extract X 1 Y). But only do this if TEMP isn't a register
6048 or a SUBREG of one since we'd be making the expression more
6049 complex if it was just a register. */
6056 {
6057 rtx temp1 = simplify_shift_const
6063 /* If all we did was surround TEMP with the two shifts, we
6064 haven't improved anything, so don't use it. Otherwise,
6065 we are better off with TEMP1. */
6070 }
6074 /* We can't handle truncation to a partial integer mode here
6075 because we don't know the real bitsize of the partial
6076 integer mode. */
6085 /* We can truncate a constant value and return it. */
6086 {
6087 poly_int64 c;
6090 }
6092 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
6093 whose value is a comparison can be replaced with a subreg if
6094 STORE_FLAG_VALUE permits. */
6103 /* (const (const X)) can become (const X). Do it this way rather than
6104 returning the inner CONST since CONST can be shared with a
6105 REG_EQUAL note. */
6111 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
6112 can add in an offset. find_split_point will split this address up
6113 again if it doesn't match. */
6120 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
6121 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
6122 bit-field and can be replaced by either a sign_extend or a
6123 sign_extract. The `and' may be a zero_extend and the two
6124 <c>, -<c> constants may be reversed. */
6141 return simplify_shift_const
6148 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
6149 can become (ashiftrt (ashift (xor x 1) C) C) where C is
6150 the bitsize of the mode - 1. This allows simplification of
6151 "a = (b & 8) == 0;" */
6158 return simplify_shift_const
6162 const1_rtx),
6166 /* If we are adding two things that have no bits in common, convert
6167 the addition into an IOR. This will often be further simplified,
6168 for example in cases like ((a & 1) + (a & 2)), which can
6169 become a & 3. */
6174 {
6175 /* Try to simplify the expression further. */
6179 /* If we could, great. If not, do not go ahead with the IOR
6180 replacement, since PLUS appears in many special purpose
6181 address arithmetic instructions. */
6189 }
6191 /* Canonicalize x + x into x << 1. */
6200 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
6201 (and <foo> (const_int pow2-1)) */
6212 /* If we have (mult (plus A B) C), apply the distributive law and then
6213 the inverse distributive law to see if things simplify. This
6214 occurs mostly in addresses, often when unrolling loops. */
6217 {
6221 }
6223 /* Try simplify a*(b/c) as (a*b)/c. */
6226 {
6232 }
6236 /* If this is a divide by a power of two, treat it as a shift if
6237 its first operand is a shift. */
6257 /* If the first operand is a condition code, we can't do anything
6258 with it. */
6262 {
6270 /* Simplify our comparison, if possible. */
6273 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6274 if only the low-order bit is possibly nonzero in X (such as when
6275 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6276 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
6277 known to be either 0 or -1, NE becomes a NEG and EQ becomes
6278 (plus X 1).
6280 Remove any ZERO_EXTRACT we made when thinking this was a
6281 comparison. It may now be simpler to use, e.g., an AND. If a
6282 ZERO_EXTRACT is indeed appropriate, it will be placed back by
6283 the call to make_compound_operation in the SET case.
6285 Don't apply these optimizations if the caller would
6286 prefer a comparison rather than a value.
6287 E.g., for the condition in an IF_THEN_ELSE most targets need
6288 an explicit comparison. */
6291 ;
6309 {
6313 int_mode);
6314 }
6322 {
6326 const1_rtx);
6327 }
6336 {
6339 }
6341 /* If STORE_FLAG_VALUE is -1, we have cases similar to
6342 those above. */
6344 ;
6361 {
6365 int_mode);
6366 }
6375 {
6379 int_mode);
6380 }
6382 /* If X is 0/1, (eq X 0) is X-1. */
6389 {
6392 }
6394 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6395 one bit that might be nonzero, we can convert (ne x 0) to
6396 (ashift x c) where C puts the bit in the sign bit. Remove any
6397 AND with STORE_FLAG_VALUE when we are done, since we are only
6398 going to test the sign bit. */
6406 {
6412 else
6414 }
6416 /* If the code changed, return a whole new comparison.
6417 We also need to avoid using SUBST in cases where
6418 simplify_comparison has widened a comparison with a CONST_INT,
6419 since in that case the wider CONST_INT may fail the sanity
6420 checks in do_SUBST. */
6427 /* Otherwise, keep this operation, but maybe change its operands.
6428 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6431 }
6441 /* If we are processing SET_DEST, we are done. */
6459 /* If this is a shift by a constant amount, simplify it. */
6467 (HOST_WIDE_INT_1U
6476 }
6479 }
6480 \f
6481 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6483 static rtx
6485 {
6492 rtx temp;
6495 rtx reversed;
6498 /* Simplify storing of the truth value. */
6503 /* Also when the truth value has to be reversed. */
6509 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6510 in it is being compared against certain values. Get the true and false
6511 comparisons and see if that says anything about the value of each arm. */
6517 {
6518 HOST_WIDE_INT nzb;
6524 /* If FALSE_CODE is EQ, swap the codes and arms. */
6527 {
6530 }
6532 scalar_int_mode from_mode;
6534 {
6535 /* If we are comparing against zero and the expression being
6536 tested has only a single bit that might be nonzero, that is
6537 its value when it is not equal to zero. Similarly if it is
6538 known to be -1 or 0. */
6542 {
6545 }
6550 {
6553 }
6554 }
6556 /* Now simplify an arm if we know the value of the register in the
6557 branch and it is used in the arm. Be careful due to the potential
6558 of locally-shared RTL. */
6575 }
6577 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6578 reversed, do so to avoid needing two sets of patterns for
6579 subtract-and-branch insns. Similarly if we have a constant in the true
6580 arm, the false arm is the same as the first operand of the comparison, or
6581 the false arm is more complicated than the true arm. */
6594 {
6602 /* It is possible that the conditional has been simplified out. */
6605 }
6607 /* If the two arms are identical, we don't need the comparison. */
6612 /* Convert a == b ? b : a to "a". */
6624 /* Look for cases where we have (abs x) or (neg (abs X)). */
6627 && comparison_p
6634 {
6640 return
6643 mode);
6646 }
6648 /* Look for MIN or MAX. */
6651 && comparison_p
6656 {
6671 }
6673 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6674 second operand is zero, this can be done as (OP Z (mult COND C2)) where
6675 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6676 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6677 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6678 neither 1 or -1, but it isn't worth checking for. */
6681 && comparison_p
6684 {
6700 /* If an identity-zero op is commutative, check whether there
6701 would be a match if we swapped the operands. */
6722 {
6726 }
6739 {
6743 }
6760 {
6764 }
6777 {
6781 }
6784 {
6794 const_true_rtx));
6802 }
6803 }
6805 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6806 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6807 negation of a single bit, we can convert this operation to a shift. We
6808 can actually do this more generally, but it doesn't seem worth it. */
6820 return
6824 /* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6825 non-zero bit in A is C1. */
6833 {
6839 }
6842 }
6843 \f
6844 /* Simplify X, a SET expression. Return the new expression. */
6846 static rtx
6848 {
6851 machine_mode mode
6855 scalar_int_mode int_mode;
6857 /* (set (pc) (return)) gets written as (return). */
6861 /* Now that we know for sure which bits of SRC we are using, see if we can
6862 simplify the expression for the object knowing that we only need the
6863 low-order bits. */
6866 {
6869 }
6871 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6872 the comparison result and try to simplify it unless we already have used
6873 undobuf.other_insn. */
6881 {
6890 {
6893 {
6896 }
6897 }
6898 else
6906 {
6910 }
6911 else
6912 {
6917 /* Attempt to simplify CC user. */
6919 {
6923 }
6925 /* Convert X into a no-op move. */
6929 }
6931 /* Simplify our comparison, if possible. */
6934 #ifdef SELECT_CC_MODE
6935 /* If this machine has CC modes other than CCmode, check to see if we
6936 need to use a different CC mode here. */
6945 else
6948 /* If the mode changed, we have to change SET_DEST, the mode in the
6949 compare, and the mode in the place SET_DEST is used. If SET_DEST is
6950 a hard register, just build new versions with the proper mode. If it
6951 is a pseudo, we lose unless it is only time we set the pseudo, in
6952 which case we can safely change its mode. */
6954 {
6956 {
6958 rtx new_dest;
6962 else
6963 {
6966 }
6973 }
6974 }
6977 /* If the code changed, we have to build a new comparison in
6978 undobuf.other_insn. */
6980 {
6989 /* If the only change we made was to change an EQ into an NE or
6990 vice versa, OP0 has only one bit that might be nonzero, and OP1
6991 is zero, check if changing the user of the condition code will
6992 produce a valid insn. If it won't, we can keep the original code
6993 in that insn by surrounding our operation with an XOR. */
7000 {
7005 {
7012 }
7013 }
7014 }
7019 /* Don't generate a compare of a CC with 0, just use that CC. */
7021 {
7024 }
7025 /* Otherwise, if we didn't previously have the same COMPARE we
7026 want, create it from scratch. */
7029 {
7032 }
7033 }
7034 else
7035 {
7036 /* Get SET_SRC in a form where we have placed back any
7037 compound expressions. Then do the checks below. */
7040 }
7042 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
7043 and X being a REG or (subreg (reg)), we may be able to convert this to
7044 (set (subreg:m2 x) (op)).
7046 We can always do this if M1 is narrower than M2 because that means that
7047 we only care about the low bits of the result.
7049 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
7050 perform a narrower operation than requested since the high-order bits will
7051 be undefined. On machine where it is defined, this transformation is safe
7052 as long as M1 and M2 have the same number of words. */
7056 && (known_equal_after_align_up
7059 UNITS_PER_WORD))
7068 {
7071 dest));
7075 }
7077 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
7078 in SRC. */
7082 {
7086 /* Here we make sure that we don't have a sign bit on. */
7089 {
7092 }
7093 }
7095 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
7096 would require a paradoxical subreg. Replace the subreg with a
7097 zero_extend to avoid the reload that would otherwise be required.
7098 Don't do this unless we have a scalar integer mode, otherwise the
7099 transformation is incorrect. */
7106 {
7111 }
7113 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
7114 are comparing an item known to be 0 or -1 against 0, use a logical
7115 operation instead. Check for one of the arms being an IOR of the other
7116 arm with some value. We compute three terms to be IOR'ed together. In
7117 practice, at most two will be nonzero. Then we do the IOR's. */
7125 && (!HAVE_conditional_move
7130 {
7155 int_mode),
7156 false_rtx);
7162 term3));
7165 }
7167 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7168 whole thing fail. */
7173 else
7174 /* Convert this into a field assignment operation, if possible. */
7176 }
7177 \f
7178 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7179 result. */
7181 static rtx
7183 {
7186 scalar_int_mode mode;
7189 {
7191 /* We can call simplify_and_const_int only if we don't lose
7192 any (sign) bits when converting INTVAL (op1) to
7193 "unsigned HOST_WIDE_INT". */
7198 {
7205 }
7207 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
7208 apply the distributive law and then the inverse distributive
7209 law to see if things simplify. */
7211 {
7215 }
7217 {
7221 }
7225 /* If we have (ior (and A B) C), apply the distributive law and then
7226 the inverse distributive law to see if things simplify. */
7229 {
7233 }
7236 {
7240 }
7245 }
7248 }
7249 \f
7250 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7251 operations" because they can be replaced with two more basic operations.
7252 ZERO_EXTEND is also considered "compound" because it can be replaced with
7253 an AND operation, which is simpler, though only one operation.
7255 The function expand_compound_operation is called with an rtx expression
7256 and will convert it to the appropriate shifts and AND operations,
7257 simplifying at each stage.
7259 The function make_compound_operation is called to convert an expression
7260 consisting of shifts and ANDs into the equivalent compound expression.
7261 It is the inverse of this function, loosely speaking. */
7263 static rtx
7265 {
7269 rtx tem;
7270 scalar_int_mode inner_mode;
7273 {
7276 /* FALLTHRU */
7278 /* We can't necessarily use a const_int for a multiword mode;
7279 it depends on implicitly extending the value.
7280 Since we don't know the right way to extend it,
7281 we can't tell whether the implicit way is right.
7283 Even for a mode that is no wider than a const_int,
7284 we can't win, because we need to sign extend one of its bits through
7285 the rest of it, and we don't know which bit. */
7289 /* Reject modes that aren't scalar integers because turning vector
7290 or complex modes into shifts causes problems. */
7294 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
7295 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7296 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7297 reloaded. If not for that, MEM's would very rarely be safe.
7299 Reject modes bigger than a word, because we might not be able
7300 to reference a two-register group starting with an arbitrary register
7301 (and currently gen_lowpart might crash for a SUBREG). */
7307 /* If the inner object has VOIDmode (the only way this can happen
7308 is if it is an ASM_OPERANDS), we can't do anything since we don't
7309 know how much masking to do. */
7318 /* fall through */
7321 /* If the operand is a CLOBBER, just return it. */
7329 /* Reject modes that aren't scalar integers because turning vector
7330 or complex modes into shifts causes problems. */
7337 /* This should stay within the object being extracted, fail otherwise. */
7348 }
7350 /* We've rejected non-scalar operations by now. */
7353 /* Convert sign extension to zero extension, if we know that the high
7354 bit is not set, as this is easier to optimize. It will be converted
7355 back to cheaper alternative in make_extraction. */
7361 {
7365 /* Make sure this is a profitable operation. */
7372 else
7374 }
7376 /* We can optimize some special cases of ZERO_EXTEND. */
7378 {
7379 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7380 know that the last value didn't have any inappropriate bits
7381 set. */
7389 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7398 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7399 is a comparison and STORE_FLAG_VALUE permits. This is like
7400 the first case, but it works even when MODE is larger
7401 than HOST_WIDE_INT. */
7409 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7418 }
7420 /* If we reach here, we want to return a pair of shifts. The inner
7421 shift is a left shift of BITSIZE - POS - LEN bits. The outer
7422 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7423 logical depending on the value of UNSIGNEDP.
7425 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7426 converted into an AND of a shift.
7428 We must check for the case where the left shift would have a negative
7429 count. This can happen in a case like (x >> 31) & 255 on machines
7430 that can't shift by a constant. On those machines, we would first
7431 combine the shift with the AND to produce a variable-position
7432 extraction. Then the constant of 31 would be substituted in
7433 to produce such a position. */
7437 {
7445 }
7450 pos),
7452 else
7453 /* Any other cases we can't handle. */
7456 /* If we couldn't do this for some reason, return the original
7457 expression. */
7462 }
7463 \f
7464 /* X is a SET which contains an assignment of one object into
7465 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7466 or certain SUBREGS). If possible, convert it into a series of
7467 logical operations.
7469 We half-heartedly support variable positions, but do not at all
7470 support variable lengths. */
7472 static const_rtx
7474 {
7475 rtx inner;
7479 scalar_int_mode compute_mode;
7481 /* Loop until we find something we can't simplify. */
7483 {
7486 {
7492 MAX_MODE_INT);
7493 }
7496 {
7504 /* A constant position should stay within the width of INNER. */
7509 {
7515 /* If position is ADJUST - X, new position is X. */
7517 else
7521 pos);
7522 }
7523 }
7525 /* If the destination is a subreg that overwrites the whole of the inner
7526 register, we can move the subreg to the source. */
7528 /* We need SUBREGs to compute nonzero_bits properly. */
7529 && nonzero_sign_valid
7531 {
7533 gen_lowpart
7537 }
7538 else
7544 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
7546 {
7547 /* Don't do anything for vector or complex integral types. */
7551 /* Try to find an integral mode to pun with. */
7557 }
7559 /* Compute a mask of LEN bits, if we can do this on the host machine. */
7563 /* Don't try to compute in too wide unsupported modes. */
7567 /* Now compute the equivalent expression. Make a copy of INNER
7568 for the SET_DEST in case it is a MEM into which we will substitute;
7569 we don't want shared RTL in that case. */
7571 compute_mode);
7575 compute_mode,
7577 compute_mode),
7578 inner);
7583 mask),
7584 pos);
7589 }
7592 }
7593 \f
7594 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7595 it is an RTX that represents the (variable) starting position; otherwise,
7596 POS is the (constant) starting bit position. Both are counted from the LSB.
7598 UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7600 IN_DEST is nonzero if this is a reference in the destination of a SET.
7601 This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7602 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7603 be used.
7605 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
7606 ZERO_EXTRACT should be built even for bits starting at bit 0.
7608 MODE is the desired mode of the result (if IN_DEST == 0).
7610 The result is an RTX for the extraction or NULL_RTX if the target
7611 can't handle it. */
7613 static rtx
7617 {
7618 /* This mode describes the size of the storage area
7619 to fetch the overall value from. Within that, we
7620 ignore the POS lowest bits, etc. */
7622 machine_mode inner_mode;
7623 scalar_int_mode wanted_inner_mode;
7629 HOST_WIDE_INT orig_pos;
7637 /* If trying or potentionally trying to extract
7638 bits outside of is_mode, don't look through
7639 non-paradoxical SUBREGs. See PR82192. */
7642 {
7643 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7644 consider just the QI as the memory to extract from.
7645 The subreg adds or removes high bits; its mode is
7646 irrelevant to the meaning of this extraction,
7647 since POS and LEN count from the lsb. */
7651 }
7656 {
7657 /* We're extracting the least significant bits of an rtx
7658 (ashift X (const_int C)), where LEN > C. Extract the
7659 least significant (LEN - C) bits of X, giving an rtx
7660 whose mode is MODE, then shift it left C times. */
7666 }
7668 /* If trying or potentionally trying to extract
7669 bits outside of is_mode, don't look through
7670 TRUNCATE. See PR82192. */
7677 /* See if this can be done without an extraction. We never can if the
7678 width of the field is not the same as that of some integer mode. For
7679 registers, we can only avoid the extraction if the position is at the
7680 low-order bit and this is either not in the destination or we have the
7681 appropriate STRICT_LOW_PART operation available.
7683 For MEM, we can avoid an extract if the field starts on an appropriate
7684 boundary and we can change the mode of the memory reference. */
7686 scalar_int_mode tmode;
7695 && (! in_dest
7699 && (pos
7702 /* We can't do this if we are widening INNER_MODE (it
7703 may not be aligned, for one thing). */
7710 {
7711 /* If INNER is a MEM, make a new MEM that encompasses just the desired
7712 field. If the original and current mode are the same, we need not
7713 adjust the offset. Otherwise, we do if bytes big endian.
7715 If INNER is not a MEM, get a piece consisting of just the field
7716 of interest (in this case POS % BITS_PER_WORD must be 0). */
7719 {
7720 poly_int64 offset;
7722 /* POS counts from lsb, but make OFFSET count in memory order. */
7726 else
7730 }
7732 {
7734 {
7735 /* We can't call gen_lowpart in a DEST since we
7736 always want a SUBREG (see below) and it would sometimes
7737 return a new hard register. */
7739 {
7740 poly_uint64 offset
7743 /* Avoid creating invalid subregs, for example when
7744 simplifying (x>>32)&255. */
7749 }
7750 else
7752 }
7753 else
7755 }
7756 else
7758 len >= HOST_BITS_PER_WIDE_INT
7759 ? HOST_WIDE_INT_M1U
7762 /* If this extraction is going into the destination of a SET,
7763 make a STRICT_LOW_PART unless we made a MEM. */
7778 /* If we know that no extraneous bits are set, and that the high
7779 bit is not set, convert the extraction to the cheaper of
7780 sign and zero extension, that are equivalent in these cases. */
7786 {
7790 /* Prefer ZERO_EXTENSION, since it gives more information to
7791 backends. */
7796 }
7798 /* Otherwise, sign- or zero-extend unless we already are in the
7799 proper mode. */
7803 }
7805 /* Unless this is a COMPARE or we have a funny memory reference,
7806 don't do anything with zero-extending field extracts starting at
7807 the low-order bit since they are simple AND operations. */
7812 /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7813 if the position is not a constant and the length is not 1. In all
7814 other cases, we would only be going outside our object in cases when
7815 an original shift would have been undefined. */
7824 /* If INNER is not from memory, we want it to have the mode of a register
7825 extraction pattern's structure operand, or word_mode if there is no
7826 such pattern. The same applies to extraction_mode and pos_mode
7827 and their respective operands.
7829 For memory, assume that the desired extraction_mode and pos_mode
7830 are the same as for a register operation, since at present we don't
7831 have named patterns for aligned memory structures. */
7836 {
7840 }
7842 /* Never narrow an object, since that might not be safe. */
7848 /* Punt if len is too large for extraction_mode. */
7854 else
7855 {
7856 /* Be careful not to go beyond the extracted object and maintain the
7857 natural alignment of the memory. */
7862 }
7867 {
7868 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7869 BITS_BIG_ENDIAN style. If position is constant, compute new
7870 position. Otherwise, build subtraction.
7871 Note that POS is relative to the mode of the original argument.
7872 If it's a MEM we need to recompute POS relative to that.
7873 However, if we're extracting from (or inserting into) a register,
7874 we want to recompute POS relative to wanted_inner_mode. */
7883 else
7884 pos_rtx
7887 pos_rtx);
7888 /* POS may be less than 0 now, but we check for that below.
7889 Note that it can only be less than 0 if !MEM_P (inner). */
7890 }
7892 /* If INNER has a wider mode, and this is a constant extraction, try to
7893 make it smaller and adjust the byte to point to the byte containing
7894 the value. */
7897 && ! pos_rtx
7902 {
7905 /* The computations below will be correct if the machine is big
7906 endian in both bits and bytes or little endian in bits and bytes.
7907 If it is mixed, we must adjust. */
7909 /* If bytes are big endian and we had a paradoxical SUBREG, we must
7910 adjust OFFSET to compensate. */
7915 /* We can now move to the desired byte. */
7926 }
7928 /* If INNER is not memory, get it into the proper mode. If we are changing
7929 its mode, POS must be a constant and smaller than the size of the new
7930 mode. */
7932 {
7933 /* On the LHS, don't create paradoxical subregs implicitely truncating
7934 the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7937 wanted_inner_mode))
7949 pos_rtx
7951 ? HOST_WIDE_INT_M1U
7955 }
7957 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7958 have to zero extend. Otherwise, we can just use a SUBREG.
7960 We dealt with constant rtxes earlier, so pos_rtx cannot
7961 have VOIDmode at this point. */
7965 {
7969 /* If we know that no extraneous bits are set, and that the high
7970 bit is not set, convert extraction to cheaper one - either
7971 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7972 cases. */
7980 {
7984 /* Prefer ZERO_EXTENSION, since it gives more information to
7985 backends. */
7989 }
7991 }
7993 /* Make POS_RTX unless we already have it and it is correct. If we don't
7994 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7995 be a CONST_INT. */
8002 /* Make the required operation. See if we can use existing rtx. */
8009 }
8010 \f
8011 /* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
8012 can be commuted with any other operations in X. Return X without
8013 that shift if so. */
8015 static rtx
8017 {
8019 rtx tem;
8022 {
8024 /* This is the shift itself. If it is wide enough, we will return
8025 either the value being shifted if the shift count is equal to
8026 COUNT or a shift for the difference. */
8040 /* If we can safely shift this constant and we find the inner shift,
8041 make a new operation. */
8046 {
8050 }
8055 }
8058 }
8059 \f
8060 /* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
8061 level of the expression and MODE is its mode. IN_CODE is as for
8062 make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
8063 that should be used when recursing on operands of *X_PTR.
8065 There are two possible actions:
8067 - Return null. This tells the caller to recurse on *X_PTR with IN_CODE
8068 equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
8070 - Return a new rtx, which the caller returns directly. */
8072 static rtx
8076 {
8084 rtx tem;
8085 scalar_int_mode inner_mode;
8089 {
8092 }
8094 /* Process depending on the code of this operation. If NEW is set
8095 nonzero, it will be returned. */
8098 {
8100 /* Convert shifts by constants into multiplications if inside
8101 an address. */
8105 {
8111 {
8114 }
8117 }
8126 {
8130 }
8133 {
8137 mode));
8139 }
8140 else
8141 {
8144 }
8154 {
8158 }
8161 {
8165 mode));
8167 }
8168 else
8169 {
8173 }
8176 /* If the second operand is not a constant, we can't do anything
8177 with it. */
8181 /* If the constant is a power of two minus one and the first operand
8182 is a logical right shift, make an extraction. */
8185 {
8189 }
8191 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8198 {
8205 /* If we narrowed the mode when dropping the subreg, then we lose. */
8209 /* If that didn't give anything, see if the AND simplifies on
8210 its own. */
8212 {
8216 }
8217 }
8218 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8224 {
8225 /* Apply the distributive law, and then try to make extractions. */
8232 }
8234 /* If we are have (and (rotate X C) M) and C is larger than the number
8235 of bits in M, this is an extraction. */
8241 {
8247 }
8249 /* On machines without logical shifts, if the operand of the AND is
8250 a logical shift and our mask turns off all the propagated sign
8251 bits, we can replace the logical shift with an arithmetic shift. */
8259 {
8269 next_code),
8271 }
8273 /* If the constant is one less than a power of two, this might be
8274 representable by an extraction even if no shift is present.
8275 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8276 we are in a COMPARE. */
8280 next_code),
8283 /* If we are in a comparison and this is an AND with a power of two,
8284 convert this into the appropriate bit extract. */
8290 next_code),
8293 /* If the one operand is a paradoxical subreg of a register or memory and
8294 the constant (limited to the smaller mode) has only zero bits where
8295 the sub expression has known zero bits, this can be expressed as
8296 a zero_extend. */
8298 {
8299 rtx sub;
8307 {
8311 /* original AND constant with all the known zero bits set */
8314 {
8318 }
8319 }
8320 }
8325 /* If the sign bit is known to be zero, replace this with an
8326 arithmetic shift. */
8331 {
8334 next_code),
8337 }
8339 /* fall through */
8345 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8346 this is a SIGN_EXTRACT. */
8353 {
8360 }
8362 /* See if we have operations between an ASHIFTRT and an ASHIFT.
8363 If so, try to merge the shifts into a SIGN_EXTEND. We could
8364 also do this for some cases of SIGN_EXTRACT, but it doesn't
8365 seem worth the effort; the case checked for occurs on Alpha. */
8376 next_code),
8383 /* Call ourselves recursively on the inner expression. If we are
8384 narrowing the object and it has a different RTL code from
8385 what it originally did, do this SUBREG as a force_to_mode. */
8386 {
8390 /* If the SUBREG is masking of a logical right shift,
8391 make an extraction. */
8398 {
8407 }
8409 /* If in_code is COMPARE, it isn't always safe to pass it through
8410 to the recursive make_compound_operation call. */
8414 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8415 is (const_int 0), rather than
8416 (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8417 Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8418 for non-equality comparisons against 0 is not equivalent
8419 to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8429 simplified
8437 {
8438 rtx newer
8441 /* If we have something other than a SUBREG, we might have
8442 done an expansion, so rerun ourselves. */
8446 /* force_to_mode can expand compounds. If it just re-expanded
8447 the compound, use gen_lowpart to convert to the desired
8448 mode. */
8450 /* Likewise if it re-expanded the compound only partially.
8451 This happens for SUBREG of ZERO_EXTRACT if they extract
8452 the same number of bits. */
8461 }
8465 }
8470 }
8476 }
8478 /* Look at the expression rooted at X. Look for expressions
8479 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8480 Form these expressions.
8482 Return the new rtx, usually just X.
8484 Also, for machines like the VAX that don't have logical shift insns,
8485 try to convert logical to arithmetic shift operations in cases where
8486 they are equivalent. This undoes the canonicalizations to logical
8487 shifts done elsewhere.
8489 We try, as much as possible, to re-use rtl expressions to save memory.
8491 IN_CODE says what kind of expression we are processing. Normally, it is
8492 SET. In a memory address it is MEM. When processing the arguments of
8493 a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8494 precisely it is an equality comparison against zero. */
8496 rtx
8498 {
8505 /* Select the code to be used in recursive calls. Once we are inside an
8506 address, we stay there. If we have a comparison, set to COMPARE,
8507 but once inside, go back to our default of SET. */
8514 scalar_int_mode mode;
8516 {
8522 }
8524 /* Now recursively process each operand of this operation. We need to
8525 handle ZERO_EXTEND specially so that we don't lose track of the
8526 inner mode. */
8528 {
8536 }
8541 {
8544 }
8547 {
8550 }
8554 }
8555 \f
8556 /* Given M see if it is a value that would select a field of bits
8557 within an item, but not the entire word. Return -1 if not.
8558 Otherwise, return the starting position of the field, where 0 is the
8559 low-order bit.
8561 *PLEN is set to the length of the field. */
8563 static int
8565 {
8566 /* Get the bit number of the first 1 bit from the right, -1 if none. */
8571 /* Now shift off the low-order zero bits and see if we have a
8572 power of two minus 1. */
8580 }
8581 \f
8582 /* If X refers to a register that equals REG in value, replace these
8583 references with REG. */
8584 static rtx
8586 {
8594 {
8627 /* FALLTHRU */
8631 {
8635 else
8637 }
8639 /* fall through */
8646 {
8649 {
8651 {
8654 }
8656 }
8657 }
8659 {
8662 {
8665 {
8667 {
8670 }
8672 }
8673 }
8674 }
8677 }
8680 }
8682 /* Return X converted to MODE. If the value is already truncated to
8683 MODE we can just return a subreg even though in the general case we
8684 would need an explicit truncation. */
8686 static rtx
8688 {
8693 {
8694 /* Bit-cast X into an integer mode. */
8699 }
8702 }
8704 /* See if X can be simplified knowing that we will only refer to it in
8705 MODE and will only refer to those bits that are nonzero in MASK.
8706 If other bits are being computed or if masking operations are done
8707 that select a superset of the bits in MASK, they can sometimes be
8708 ignored.
8710 Return a possibly simplified expression, but always convert X to
8711 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8713 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8714 are all off in X. This is used when X will be complemented, by either
8715 NOT, NEG, or XOR. */
8717 static rtx
8720 {
8723 machine_mode op_mode;
8726 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8727 code below will do the wrong thing since the mode of such an
8728 expression is VOIDmode.
8730 Also do nothing if X is a CLOBBER; this can happen if X was
8731 the return value from a call to gen_lowpart. */
8735 /* We want to perform the operation in its present mode unless we know
8736 that the operation is valid in MODE, in which case we do the operation
8737 in MODE. */
8742 /* It is not valid to do a right-shift in a narrower mode
8743 than the one it came in with. */
8748 /* Truncate MASK to fit OP_MODE. */
8752 /* Determine what bits of X are guaranteed to be (non)zero. */
8755 /* If none of the bits in X are needed, return a zero. */
8759 /* If X is a CONST_INT, return a new one. Do this here since the
8760 test below will fail. */
8762 {
8765 else
8766 {
8769 }
8770 }
8772 /* If X is narrower than MODE and we want all the bits in X's mode, just
8773 get X in the proper mode. */
8778 /* We can ignore the effect of a SUBREG if it narrows the mode or
8779 if the constant masks to zero all the bits the mode doesn't have. */
8783 || (mask
8791 /* OP_MODE is either MODE or XMODE, so it must be a scalar
8792 integer too. */
8798 }
8800 /* Subroutine of force_to_mode that handles cases in which both X and
8801 the result are scalar integers. MODE is the mode of the result,
8802 XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8803 is preferred for simplified versions of X. The other arguments
8804 are as for force_to_mode. */
8806 static rtx
8810 {
8815 poly_int64 const_op0;
8817 /* When we have an arithmetic operation, or a shift whose count we
8818 do not know, we need to assume that all bits up to the highest-order
8819 bit in MASK will be needed. This is how we form such a mask. */
8822 else
8827 {
8829 /* If X is a (clobber (const_int)), return it since we know we are
8830 generating something that won't match. */
8843 /* Similarly for a truncate. */
8847 /* If this is an AND with a constant, convert it into an AND
8848 whose constant is the AND of that constant with MASK. If it
8849 remains an AND of MASK, delete it since it is redundant. */
8852 {
8857 /* If X is still an AND, see if it is an AND with a mask that
8858 is just some low-order bits. If so, and it is MASK, we don't
8859 need it. */
8865 /* If it remains an AND, try making another AND with the bits
8866 in the mode mask that aren't in MASK turned on. If the
8867 constant in the AND is wide enough, this might make a
8868 cheaper constant. */
8873 {
8874 unsigned HOST_WIDE_INT cval
8876 rtx y;
8883 }
8886 }
8891 /* In (and (plus FOO C1) M), if M is a mask that just turns off
8892 low-order bits (as in an alignment operation) and FOO is already
8893 aligned to that boundary, mask C1 to that boundary as well.
8894 This may eliminate that PLUS and, later, the AND. */
8896 {
8900 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8901 number, sign extend it. */
8914 }
8916 /* fall through */
8919 /* Substituting into the operands of a widening MULT is not likely to
8920 create RTL matching a machine insn. */
8930 /* For PLUS, MINUS and MULT, we need any bits less significant than the
8931 most significant bit in MASK since carries from those bits will
8932 affect the bits we are interested in. */
8937 /* If X is (minus C Y) where C's least set bit is larger than any bit
8938 in the mask, then we may replace with (neg Y). */
8941 {
8944 }
8946 /* Similarly, if C contains every bit in the fuller_mask, then we may
8947 replace with (not Y). */
8950 {
8953 }
8960 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8961 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8962 operation which may be a bitfield extraction. Ensure that the
8963 constant we form is not wider than the mode of X. */
8975 {
8978 xmode);
8984 }
8986 binop:
8987 /* For most binary operations, just propagate into the operation and
8988 change the mode if we have an operation of that mode. */
8993 /* If we ended up truncating both operands, truncate the result of the
8994 operation instead. */
8997 {
9000 }
9006 {
9009 }
9013 /* For left shifts, do the same, but just for the first operand.
9014 However, we cannot do anything with shifts where we cannot
9015 guarantee that the counts are smaller than the size of the mode
9016 because such a count will have a different meaning in a
9017 wider mode. */
9027 /* If the shift count is a constant and we can do arithmetic in
9028 the mode of the shift, refine which bits we need. Otherwise, use the
9029 conservative form of the mask. */
9035 else
9043 {
9046 }
9050 /* Here we can only do something if the shift count is a constant,
9051 this shift constant is valid for the host, and we can do arithmetic
9052 in OP_MODE. */
9058 {
9062 /* Select the mask of the bits we need for the shift operand. */
9065 /* We can only change the mode of the shift if we can do arithmetic
9066 in the mode of the shift and INNER_MASK is no wider than the
9067 width of X's mode. */
9074 {
9077 }
9078 }
9080 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
9081 shift and AND produces only copies of the sign bit (C2 is one less
9082 than a power of two), we can do this with just a shift. */
9086 /* The shift puts one of the sign bit copies in the least significant
9087 bit. */
9092 /* Number of bits left after the shift must be more than the mask
9093 needs. */
9096 /* Must be more sign bit copies than the mask needs. */
9099 {
9103 }
9107 /* If we are just looking for the sign bit, we don't need this shift at
9108 all, even if it has a variable count. */
9112 /* If this is a shift by a constant, get a mask that contains those bits
9113 that are not copies of the sign bit. We then have two cases: If
9114 MASK only includes those bits, this can be a logical shift, which may
9115 allow simplifications. If MASK is a single-bit field not within
9116 those bits, we are requesting a copy of the sign bit and hence can
9117 shift the sign bit to the appropriate location. */
9121 {
9125 /* If the considered data is wider than HOST_WIDE_INT, we can't
9126 represent a mask for all its bits in a single scalar.
9127 But we only care about the lower bits, so calculate these. */
9130 {
9133 /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
9134 is the number of bits a full-width mask would have set.
9135 We need only shift if these are fewer than nonzero can
9136 hold. If not, we must keep all bits set in nonzero. */
9141 + HOST_BITS_PER_WIDE_INT
9143 }
9144 else
9145 {
9148 }
9151 {
9156 }
9159 {
9160 x = simplify_shift_const
9166 }
9167 }
9169 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
9170 even if the shift count isn't a constant. */
9174 shiftrt:
9176 /* If this is a zero- or sign-extension operation that just affects bits
9177 we don't care about, remove it. Be sure the call above returned
9178 something that is still a shift. */
9188 next_select);
9194 /* If the shift count is constant and we can do computations
9195 in the mode of X, compute where the bits we care about are.
9196 Otherwise, we can't do anything. Don't change the mode of
9197 the shift or propagate MODE into the shift, though. */
9200 {
9209 }
9213 /* If we just want the low-order bit, the NEG isn't needed since it
9214 won't change the low-order bit. */
9218 /* We need any bits less significant than the most significant bit in
9219 MASK since carries from those bits will affect the bits we are
9220 interested in. */
9225 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9226 same as the XOR case above. Ensure that the constant we form is not
9227 wider than the mode of X. */
9235 {
9242 }
9244 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9245 use the full mask inside the NOT. */
9248 unop:
9251 next_select));
9253 {
9256 }
9260 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9261 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9262 which is equal to STORE_FLAG_VALUE. */
9274 /* We have no way of knowing if the IF_THEN_ELSE can itself be
9275 written in a narrower mode. We play it safe and do not do so. */
9291 }
9293 /* Ensure we return a value of the proper mode. */
9295 }
9296 \f
9297 /* Return nonzero if X is an expression that has one of two values depending on
9298 whether some other value is zero or nonzero. In that case, we return the
9299 value that is being tested, *PTRUE is set to the value if the rtx being
9300 returned has a nonzero value, and *PFALSE is set to the other alternative.
9302 If we return zero, we set *PTRUE and *PFALSE to X. */
9304 static rtx
9306 {
9311 scalar_int_mode int_mode;
9313 /* If we are comparing a value against zero, we are done. */
9316 {
9320 }
9322 /* If this is a unary operation whose operand has one of two values, apply
9323 our opcode to compute those values. */
9326 {
9331 }
9333 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9334 make can't possibly match and would suppress other optimizations. */
9336 ;
9338 /* If this is a binary operation, see if either side has only one of two
9339 values. If either one does or if both do and they are conditional on
9340 the same value, compute the new true and false values. */
9342 {
9350 {
9351 /* Try to enable a simplification by undoing work done by
9352 if_then_else_cond if it converted a REG into something more
9353 complex. */
9355 {
9358 }
9359 else
9360 {
9363 }
9364 }
9368 {
9369 /* If if_then_else_cond returned zero, then true/false are the
9370 same rtl. We must copy one of them to prevent invalid rtl
9371 sharing. */
9378 {
9383 }
9384 else
9385 {
9388 }
9391 }
9393 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9394 operands is zero when the other is nonzero, and vice-versa,
9395 and STORE_FLAG_VALUE is 1 or -1. */
9401 {
9419 {
9426 const_true_rtx);
9428 }
9429 }
9431 /* Similarly for MULT, AND and UMIN, except that for these the result
9432 is always zero. */
9436 {
9450 {
9453 }
9454 }
9455 }
9458 {
9459 /* If we have IF_THEN_ELSE already, extract the condition and
9460 canonicalize it if it is NE or EQ. */
9466 {
9469 }
9470 else
9472 }
9474 /* If X is a SUBREG, we can narrow both the true and false values
9475 if the inner expression, if there is a condition. */
9479 {
9485 {
9489 }
9490 }
9492 /* If X is a constant, this isn't special and will cause confusions
9493 if we treat it as such. Likewise if it is equivalent to a constant. */
9496 ;
9498 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9499 will be least confusing to the rest of the compiler. */
9501 {
9504 }
9506 /* If X is known to be either 0 or -1, those are the true and
9507 false values when testing X. */
9512 {
9515 }
9517 /* Likewise for 0 or a single bit. */
9520 {
9523 }
9525 /* Otherwise fail; show no condition with true and false values the same. */
9528 }
9529 \f
9530 /* Return the value of expression X given the fact that condition COND
9531 is known to be true when applied to REG as its first operand and VAL
9532 as its second. X is known to not be shared and so can be modified in
9533 place.
9535 We only handle the simplest cases, and specifically those cases that
9536 arise with IF_THEN_ELSE expressions. */
9538 static rtx
9540 {
9548 /* If either operand of the condition is a floating point value,
9549 then we have to avoid collapsing an EQ comparison. */
9559 /* If X is (abs REG) and we know something about REG's relationship
9560 with zero, we may be able to simplify this. */
9564 {
9573 }
9575 /* The only other cases we handle are MIN, MAX, and comparisons if the
9576 operands are the same as REG and VAL. */
9579 {
9581 {
9584 }
9587 {
9589 {
9597 else
9599 }
9602 {
9605 /* Do not reverse the condition when it is NE or EQ.
9606 This is because we cannot conclude anything about
9607 the value of 'SMAX (x, y)' when x is not equal to y,
9608 but we can when x equals y. */
9614 {
9625 }
9626 }
9627 }
9628 }
9630 {
9635 {
9636 /* We must simplify subreg here, before we lose track of the
9637 original inner_mode. */
9642 else
9644 }
9647 }
9648 /* We don't have to handle SIGN_EXTEND here, because even in the
9649 case of replacing something with a modeless CONST_INT, a
9650 CONST_INT is already (supposed to be) a valid sign extension for
9651 its narrower mode, which implies it's already properly
9652 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9653 story is different. */
9655 {
9660 {
9661 /* We must simplify the zero_extend here, before we lose
9662 track of the original inner_mode. */
9667 else
9669 }
9672 }
9676 {
9683 }
9686 }
9687 \f
9688 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9689 assignment as a field assignment. */
9691 static int
9693 {
9695 {
9703 }
9711 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9712 Note that all SUBREGs of MEM are paradoxical; otherwise they
9713 would have been rewritten. */
9726 /* We used to see if get_last_value of X and Y were the same but that's
9727 not correct. In one direction, we'll cause the assignment to have
9728 the wrong destination and in the case, we'll import a register into this
9729 insn that might have already have been dead. So fail if none of the
9730 above cases are true. */
9732 }
9733 \f
9734 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9735 Return that assignment if so.
9737 We only handle the most common cases. */
9739 static rtx
9741 {
9744 rtx assign;
9746 HOST_WIDE_INT c1;
9747 HOST_WIDE_INT pos;
9749 rtx other;
9751 /* All the rules in this function are specific to scalar integers. */
9752 scalar_int_mode mode;
9756 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9757 a clear of a one-bit field. We will have changed it to
9758 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
9759 for a SUBREG. */
9765 {
9771 }
9780 {
9787 }
9789 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9790 one-bit field. */
9794 {
9800 }
9802 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9803 SRC is an AND with all bits of that field set, then we can discard
9804 the AND. */
9809 {
9816 else
9819 /* Complete overlap. We can remove the source AND. */
9823 /* Partial overlap. We can reduce the source AND. */
9825 {
9829 }
9830 }
9832 /* The other case we handle is assignments into a constant-position
9833 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9834 a mask that has all one bits except for a group of zero bits and
9835 OTHER is known to have zeros where C1 has ones, this is such an
9836 assignment. Compute the position and length from C1. Shift OTHER
9837 to the appropriate position, force it to the required mode, and
9838 make the extraction. Check for the AND in both operands. */
9840 /* One or more SUBREGs might obscure the constant-position field
9841 assignment. The first one we are likely to encounter is an outer
9842 narrowing SUBREG, which we can just strip for the purposes of
9843 identifying the constant-field assignment. */
9860 /* The second SUBREG that might get in the way is a paradoxical
9861 SUBREG around the first operand of the AND. We want to
9862 pretend the operand is as wide as the destination here. We
9863 do this by adjusting the MEM to wider mode for the sole
9864 purpose of the call to rtx_equal_for_field_assignment_p. Also
9865 note this trick only works for MEMs. */
9877 /* The second SUBREG that might get in the way is a paradoxical
9878 SUBREG around the first operand of the AND. We want to
9879 pretend the operand is as wide as the destination here. We
9880 do this by adjusting the MEM to wider mode for the sole
9881 purpose of the call to rtx_equal_for_field_assignment_p. Also
9882 note this trick only works for MEMs. */
9890 else
9904 /* The mode to use for the source is the mode of the assignment, or of
9905 what is inside a possible STRICT_LOW_PART. */
9909 /* Shift OTHER right POS places and make it the source, restricting it
9910 to the proper length and mode. */
9914 dest);
9916 len >= HOST_BITS_PER_WIDE_INT
9917 ? HOST_WIDE_INT_M1U
9921 /* If SRC is masked by an AND that does not make a difference in
9922 the value being stored, strip it. */
9933 }
9934 \f
9935 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9936 if so. */
9938 static rtx
9940 {
9944 rtx tem;
9946 /* Distributivity is not true for floating point as it can change the
9947 value. So we don't do it unless -funsafe-math-optimizations. */
9952 /* The outer operation can only be one of the following: */
9960 /* If either operand is a primitive we can't do anything, so get out
9961 fast. */
9971 /* See if the inner and outer operations distribute. */
9973 {
9978 /* These all distribute except over PLUS. */
9989 /* This is also a multiply, so it distributes over everything. */
9992 /* This used to handle SUBREG, but this turned out to be counter-
9993 productive, since (subreg (op ...)) usually is not handled by
9994 insn patterns, and this "optimization" therefore transformed
9995 recognizable patterns into unrecognizable ones. Therefore the
9996 SUBREG case was removed from here.
9998 It is possible that distributing SUBREG over arithmetic operations
9999 leads to an intermediate result than can then be optimized further,
10000 e.g. by moving the outer SUBREG to the other side of a SET as done
10001 in simplify_set. This seems to have been the original intent of
10002 handling SUBREGs here.
10004 However, with current GCC this does not appear to actually happen,
10005 at least on major platforms. If some case is found where removing
10006 the SUBREG case here prevents follow-on optimizations, distributing
10007 SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
10011 }
10013 /* Set LHS and RHS to the inner operands (A and B in the example
10014 above) and set OTHER to the common operand (C in the example).
10015 There is only one way to do this unless the inner operation is
10016 commutative. */
10028 else
10031 /* Form the new inner operation, seeing if it simplifies first. */
10034 /* There is one exception to the general way of distributing:
10035 (a | c) ^ (b | c) -> (a ^ b) & ~c */
10037 {
10040 }
10042 /* We may be able to continuing distributing the result, so call
10043 ourselves recursively on the inner operation before forming the
10044 outer operation, which we return. */
10047 }
10049 /* See if X is of the form (* (+ A B) C), and if so convert to
10050 (+ (* A C) (* B C)) and try to simplify.
10052 Most of the time, this results in no change. However, if some of
10053 the operands are the same or inverses of each other, simplifications
10054 will result.
10056 For example, (and (ior A B) (not B)) can occur as the result of
10057 expanding a bit field assignment. When we apply the distributive
10058 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
10059 which then simplifies to (and (A (not B))).
10061 Note that no checks happen on the validity of applying the inverse
10062 distributive law. This is pointless since we can do it in the
10063 few places where this routine is called.
10065 N is the index of the term that is decomposed (the arithmetic operation,
10066 i.e. (+ A B) in the first example above). !N is the index of the term that
10067 is distributed, i.e. of C in the first example above. */
10068 static rtx
10070 {
10071 machine_mode mode;
10075 /* Distributivity is not true for floating point as it can change the
10076 value. So we don't do it unless -funsafe-math-optimizations. */
10093 /* Special case (and (xor B C) (not A)), which is equivalent to
10094 (xor (ior A B) (ior A C)) */
10096 {
10099 }
10102 {
10103 /* Distribute the second term. */
10106 }
10107 else
10108 {
10109 /* Distribute the first term. */
10112 }
10122 }
10123 \f
10124 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
10125 in MODE. Return an equivalent form, if different from (and VAROP
10126 (const_int CONSTOP)). Otherwise, return NULL_RTX. */
10128 static rtx
10131 {
10134 rtx orig_varop;
10142 /* Simplify VAROP knowing that we will be only looking at some of the
10143 bits in it.
10145 Note by passing in CONSTOP, we guarantee that the bits not set in
10146 CONSTOP are not significant and will never be examined. We must
10147 ensure that is the case by explicitly masking out those bits
10148 before returning. */
10151 /* If VAROP is a CLOBBER, we will fail so return it. */
10155 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10156 to VAROP and return the new constant. */
10160 /* See what bits may be nonzero in VAROP. Unlike the general case of
10161 a call to nonzero_bits, here we don't care about bits outside
10162 MODE. */
10166 /* Turn off all bits in the constant that are known to already be zero.
10167 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10168 which is tested below. */
10172 /* If we don't have any bits left, return zero. */
10176 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10177 a power of two, we can replace this with an ASHIFT. */
10182 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10183 or XOR, then try to apply the distributive law. This may eliminate
10184 operations if either branch can be simplified because of the AND.
10185 It may also make some cases more complex, but those cases probably
10186 won't match a pattern either with or without this. */
10189 {
10191 return
10192 gen_lowpart
10194 apply_distributive_law
10198 constop),
10201 constop))));
10202 }
10204 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10205 the AND and see if one of the operands simplifies to zero. If so, we
10206 may eliminate it. */
10210 {
10219 }
10221 /* Make a SUBREG if necessary. If we can't make it, fail. */
10226 /* If we are only masking insignificant bits, return VAROP. */
10233 /* Otherwise, return an AND. */
10235 }
10238 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10239 in MODE.
10241 Return an equivalent form, if different from X. Otherwise, return X. If
10242 X is zero, we are to always construct the equivalent form. */
10244 static rtx
10247 {
10258 }
10259 \f
10260 /* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10261 We don't care about bits outside of those defined in MODE.
10262 We DO care about all the bits in MODE, even if XMODE is smaller than MODE.
10264 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10265 a shift, AND, or zero_extract, we can do better. */
10267 static rtx
10269 scalar_int_mode mode,
10271 {
10272 rtx tem;
10275 /* If X is a register whose nonzero bits value is current, use it.
10276 Otherwise, if X is a register whose value we can find, use that
10277 value. Otherwise, use the previously-computed global nonzero bits
10278 for this register. */
10293 && !REGNO_REG_SET_P
10296 {
10297 /* Note that, even if the precision of last_set_mode is lower than that
10298 of mode, record_value_for_reg invoked nonzero_bits on the register
10299 with nonzero_bits_mode (because last_set_mode is necessarily integral
10300 and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10301 are all valid, hence in mode too since nonzero_bits_mode is defined
10302 to the largest HWI_COMPUTABLE_MODE_P mode. */
10305 }
10309 {
10314 }
10317 {
10321 /* We don't know anything about the upper bits. */
10325 }
10328 }
10330 /* Given a reg X of mode XMODE, return the number of bits at the high-order
10331 end of X that are known to be equal to the sign bit. X will be used
10332 in mode MODE; the returned value will always be between 1 and the
10333 number of bits in MODE. */
10335 static rtx
10337 scalar_int_mode mode,
10339 {
10340 rtx tem;
10353 && !REGNO_REG_SET_P
10356 {
10359 }
10370 }
10371 \f
10372 /* Return the number of "extended" bits there are in X, when interpreted
10373 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10374 unsigned quantities, this is the number of high-order zero bits.
10375 For signed quantities, this is the number of copies of the sign bit
10376 minus 1. In both case, this function returns the number of "spare"
10377 bits. For example, if two quantities for which this function returns
10378 at least 1 are added, the addition is known not to overflow.
10380 This function will always return 0 unless called during combine, which
10381 implies that it must be called from a define_split. */
10383 unsigned int
10385 {
10389 scalar_int_mode int_mode;
10397 }
10399 /* This function is called from `simplify_shift_const' to merge two
10400 outer operations. Specifically, we have already found that we need
10401 to perform operation *POP0 with constant *PCONST0 at the outermost
10402 position. We would now like to also perform OP1 with constant CONST1
10403 (with *POP0 being done last).
10405 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
10406 the resulting operation. *PCOMP_P is set to 1 if we would need to
10407 complement the innermost operand, otherwise it is unchanged.
10409 MODE is the mode in which the operation will be done. No bits outside
10410 the width of this mode matter. It is assumed that the width of this mode
10411 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10413 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10414 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10415 result is simply *PCONST0.
10417 If the resulting operation cannot be expressed as one operation, we
10418 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
10420 static int
10421 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
10422 {
10429 /* If OP0 is an AND, clear unimportant bits in CONST1. */
10433 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10434 if OP0 is SET. */
10443 {
10445 {
10463 }
10464 }
10466 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10470 /* If the two constants aren't the same, we can't do anything. The
10471 remaining six cases can all be done. */
10475 else
10477 {
10480 /* (a & b) | b == b */
10483 /* (a ^ b) | b == a | b */
10484 {;}
10489 /* (a & b) ^ b == (~a) & b */
10492 /* (a | b) ^ b == a & ~b */
10498 /* (a | b) & b == b */
10501 /* (a ^ b) & b) == (~a) & b */
10506 }
10508 /* Check for NO-OP cases. */
10521 /* ??? Slightly redundant with the above mask, but not entirely.
10522 Moving this above means we'd have to sign-extend the mode mask
10523 for the final test. */
10528 }
10529 \f
10530 /* A helper to simplify_shift_const_1 to determine the mode we can perform
10531 the shift in. The original shift operation CODE is performed on OP in
10532 ORIG_MODE. Return the wider mode MODE if we can perform the operation
10533 in that mode. Return ORIG_MODE otherwise. We can also assume that the
10534 result of the shift is subject to operation OUTER_CODE with operand
10535 OUTER_CONST. */
10537 static scalar_int_mode
10541 {
10544 /* In general we can't perform in wider mode for right shift and rotate. */
10546 {
10548 /* We can still widen if the bits brought in from the left are identical
10549 to the sign bit of ORIG_MODE. */
10557 /* Similarly here but with zero bits. */
10562 /* We can also widen if the bits brought in will be masked off. This
10563 operation is performed in ORIG_MODE. */
10565 {
10571 }
10572 /* fall through */
10582 }
10583 }
10585 /* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10586 of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10587 if we cannot simplify it. Otherwise, return a simplified value.
10589 The shift is normally computed in the widest mode we find in VAROP, as
10590 long as it isn't a different number of words than RESULT_MODE. Exceptions
10591 are ASHIFTRT and ROTATE, which are always done in their original mode. */
10593 static rtx
10596 {
10601 machine_mode shift_mode;
10603 /* We form (outer_op (code varop count) (outer_const)). */
10609 /* Make sure and truncate the "natural" shift on the way in. We don't
10610 want to do this inside the loop as it makes it more difficult to
10611 combine shifts. */
10615 /* If we were given an invalid count, don't do anything except exactly
10616 what was requested. */
10623 /* Unless one of the branches of the `if' in this loop does a `continue',
10624 we will `break' the loop after the `if'. */
10627 {
10628 /* If we have an operand of (clobber (const_int 0)), fail. */
10632 /* Convert ROTATERT to ROTATE. */
10634 {
10638 }
10642 {
10643 /* We only change the modes of scalar shifts. */
10649 }
10651 scalar_int_mode shift_unit_mode
10654 /* Handle cases where the count is greater than the size of the mode
10655 minus 1. For ASHIFT, use the size minus one as the count (this can
10656 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10657 take the count modulo the size. For other shifts, the result is
10658 zero.
10660 Since these shifts are being produced by the compiler by combining
10661 multiple operations, each of which are defined, we know what the
10662 result is supposed to be. */
10665 {
10670 else
10671 {
10672 /* We can't simply return zero because there may be an
10673 outer op. */
10677 }
10678 }
10680 /* If we discovered we had to complement VAROP, leave. Making a NOT
10681 here would cause an infinite loop. */
10686 {
10687 /* An arithmetic right shift of a quantity known to be -1 or 0
10688 is a no-op. */
10692 {
10695 }
10697 /* If we are doing an arithmetic right shift and discarding all but
10698 the sign bit copies, this is equivalent to doing a shift by the
10699 bitsize minus one. Convert it into that shift because it will
10700 often allow other simplifications. */
10707 /* We simplify the tests below and elsewhere by converting
10708 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10709 `make_compound_operation' will convert it to an ASHIFTRT for
10710 those machines (such as VAX) that don't have an LSHIFTRT. */
10715 shift_unit_mode)))
10727 }
10730 {
10737 {
10740 }
10744 /* The following rules apply only to scalars. */
10749 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10750 minus the width of a smaller mode, we can do this with a
10751 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10758 {
10767 }
10771 /* The following rules apply only to scalars. */
10777 /* If VAROP is a SUBREG, strip it as long as the inner operand has
10778 the same number of words as what we've seen so far. Then store
10779 the widest mode in MODE. */
10786 {
10791 }
10795 /* Some machines use MULT instead of ASHIFT because MULT
10796 is cheaper. But it is still better on those machines to
10797 merge two shifts into one. */
10800 {
10805 }
10809 /* Similar, for when divides are cheaper. */
10812 {
10817 }
10821 /* If we are extracting just the sign bit of an arithmetic
10822 right shift, that shift is not needed. However, the sign
10823 bit of a wider mode may be different from what would be
10824 interpreted as the sign bit in a narrower mode, so, if
10825 the result is narrower, don't discard the shift. */
10830 {
10833 }
10835 /* fall through */
10840 /* The following rules apply only to scalars. */
10847 /* Here we have two nested shifts. The result is usually the
10848 AND of a new shift with a mask. We compute the result below. */
10854 {
10858 rtx mask_rtx;
10860 /* We have one common special case. We can't do any merging if
10861 the inner code is an ASHIFTRT of a smaller mode. However, if
10862 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10863 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10864 we can convert it to
10865 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10866 This simplifies certain SIGN_EXTEND operations. */
10870 {
10871 /* C3 has the low-order C1 bits zero. */
10883 }
10885 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10886 than C1 high-order bits equal to the sign bit, we can convert
10887 this to either an ASHIFT or an ASHIFTRT depending on the
10888 two counts.
10890 We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10896 {
10900 {
10903 }
10906 }
10908 /* There are some cases we can't do. If CODE is ASHIFTRT,
10909 we can only do this if FIRST_CODE is also ASHIFTRT.
10911 We can't do the case when CODE is ROTATE and FIRST_CODE is
10912 ASHIFTRT.
10914 If the mode of this shift is not the mode of the outer shift,
10915 we can't do this if either shift is a right shift or ROTATE.
10917 Finally, we can't do any of these if the mode is too wide
10918 unless the codes are the same.
10920 Handle the case where the shift codes are the same
10921 first. */
10924 {
10933 }
10944 /* To compute the mask to apply after the shift, shift the
10945 nonzero bits of the inner shift the same way the
10946 outer shift will. */
10949 int_result_mode);
10951 mask_rtx
10955 /* Give up if we can't compute an outer operation to use. */
10963 /* If the shifts are in the same direction, we add the
10964 counts. Otherwise, we subtract them. */
10968 else
10971 /* If COUNT is positive, the new shift is usually CODE,
10972 except for the two exceptions below, in which case it is
10973 FIRST_CODE. If the count is negative, FIRST_CODE should
10974 always be used */
10984 }
10986 /* If we have (A << B << C) for any shift, we can convert this to
10987 (A << C << B). This wins if A is a constant. Only try this if
10988 B is not a constant. */
10993 {
10994 /* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10995 sure the result will be masked. See PR70222. */
11003 /* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
11004 up outer sign extension (often left and right shift) is
11005 hardly more efficient than the original. See PR70429. */
11012 count_rtx);
11016 }
11020 /* The following rules apply only to scalars. */
11024 /* Make this fit the case below. */
11031 /* The following rules apply only to scalars. */
11037 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
11038 with C the size of VAROP - 1 and the shift is logical if
11039 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11040 we have an (le X 0) operation. If we have an arithmetic shift
11041 and STORE_FLAG_VALUE is 1 or we have a logical shift with
11042 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
11050 {
11053 const0_rtx);
11059 }
11061 /* If we have (shift (logical)), move the logical to the outside
11062 to allow it to possibly combine with another logical and the
11063 shift to combine with another shift. This also canonicalizes to
11064 what a ZERO_EXTRACT looks like. Also, some machines have
11065 (and (shift)) insns. */
11068 /* We can't do this if we have (ashiftrt (xor)) and the
11069 constant has its sign bit set in shift_unit_mode with
11070 shift_unit_mode wider than result_mode. */
11083 {
11086 }
11088 /* If we can't do that, try to simplify the shift in each arm of the
11089 logical expression, make a new logical expression, and apply
11090 the inverse distributive law. This also can't be done for
11091 (ashiftrt (xor)) where we've widened the shift and the constant
11092 changes the sign bit. */
11098 {
11110 }
11114 /* The following rules apply only to scalars. */
11119 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
11120 says that the sign bit can be tested, FOO has mode MODE, C is
11121 GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
11122 that may be nonzero. */
11132 {
11136 }
11140 /* The following rules apply only to scalars. */
11145 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
11146 than the number of bits in the mode is equivalent to A. */
11150 {
11154 }
11156 /* NEG commutes with ASHIFT since it is multiplication. Move the
11157 NEG outside to allow shifts to combine. */
11161 {
11164 }
11168 /* The following rules apply only to scalars. */
11173 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11174 is one less than the number of bits in the mode is
11175 equivalent to (xor A 1). */
11182 {
11186 }
11188 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11189 that might be nonzero in BAR are those being shifted out and those
11190 bits are known zero in FOO, we can replace the PLUS with FOO.
11191 Similarly in the other operand order. This code occurs when
11192 we are computing the size of a variable-size array. */
11199 {
11202 }
11210 {
11213 }
11215 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11226 {
11229 }
11231 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
11232 signbit', and attempt to change the PLUS to an XOR and move it to
11233 the outer operation as is done above in the AND/IOR/XOR case
11234 leg for shift(logical). See details in logical handling above
11235 for reasoning in doing so. */
11247 {
11250 }
11255 /* The following rules apply only to scalars. */
11260 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11261 with C the size of VAROP - 1 and the shift is logical if
11262 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11263 we have a (gt X 0) operation. If the shift is arithmetic with
11264 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11265 we have a (neg (gt X 0)) operation. */
11274 {
11277 const0_rtx);
11283 }
11287 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11288 if the truncate does not affect the value. */
11295 {
11299 new_count);
11302 new_count_rtx);
11306 }
11311 }
11314 }
11318 {
11319 /* We only change the modes of scalar shifts. */
11324 }
11326 /* We have now finished analyzing the shift. The result should be
11327 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11328 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11329 to the result of the shift. OUTER_CONST is the relevant constant,
11330 but we must turn off all bits turned off in the shift. */
11338 /* Make a SUBREG if necessary. If we can't make it, fail. */
11343 /* If we have an outer operation and we just made a shift, it is
11344 possible that we could have simplified the shift were it not
11345 for the outer operation. So try to do the simplification
11346 recursively. */
11350 else
11357 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
11358 turn off all the bits that the shift would have turned off. */
11360 /* We only change the modes of scalar shifts. */
11364 /* Do the remainder of the processing in RESULT_MODE. */
11367 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
11368 operation. */
11373 {
11383 {
11384 /* This means that we have determined that the result is
11385 equivalent to a constant. This should be rare. */
11388 }
11391 else
11394 }
11397 }
11399 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11400 The result of the shift is RESULT_MODE. If we cannot simplify it,
11401 return X or, if it is NULL, synthesize the expression with
11402 simplify_gen_binary. Otherwise, return a simplified value.
11404 The shift is normally computed in the widest mode we find in VAROP, as
11405 long as it isn't a different number of words than RESULT_MODE. Exceptions
11406 are ASHIFTRT and ROTATE, which are always done in their original mode. */
11408 static rtx
11411 {
11422 }
11424 \f
11425 /* A subroutine of recog_for_combine. See there for arguments and
11426 return value. */
11428 static int
11430 {
11432 rtx pat_without_clobbers;
11440 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11441 we use to indicate that something didn't match. If we find such a
11442 thing, force rejection. */
11456 {
11459 else
11462 }
11464 /* If it isn't, there is the possibility that we previously had an insn
11465 that clobbered some register as a side effect, but the combined
11466 insn doesn't need to do that. So try once more without the clobbers
11467 unless this represents an ASM insn. */
11471 {
11476 {
11479 pos++;
11480 }
11490 {
11493 else
11496 }
11497 }
11504 /* Recognize all noop sets, these will be killed by followup pass. */
11508 /* If we had any clobbers to add, make a new pattern than contains
11509 them. Then check to make sure that all of them are dead. */
11511 {
11521 else
11528 {
11533 {
11537 }
11538 }
11540 }
11544 {
11552 /* Allow targets to reject combined insn. */
11554 {
11557 dump_file);
11559 /* Callers expect recog_for_combine to strip
11560 clobbers from the pattern on failure. */
11565 }
11570 }
11576 }
11578 /* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11579 expressed as an AND and maybe an LSHIFTRT, to that formulation.
11580 Return whether anything was so changed. */
11582 static bool
11584 {
11590 {
11602 {
11612 else
11616 {
11622 }
11623 }
11629 {
11634 {
11640 }
11641 }
11646 {
11650 }
11651 else
11657 {
11660 }
11664 }
11671 scalar_int_mode mode;
11677 {
11691 else
11699 }
11702 }
11704 /* Like recog, but we receive the address of a pointer to a new pattern.
11705 We try to match the rtx that the pointer points to.
11706 If that fails, we may try to modify or replace the pattern,
11707 storing the replacement into the same pointer object.
11709 Modifications include deletion or addition of CLOBBERs. If the
11710 instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11711 to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11712 (and undo if that fails).
11714 PNOTES is a pointer to a location where any REG_UNUSED notes added for
11715 the CLOBBERs are placed.
11717 The value is the final insn code from the pattern ultimately matched,
11718 or -1. */
11720 static int
11722 {
11734 {
11737 {
11741 }
11742 }
11745 {
11750 }
11753 }
11754 \f
11755 /* Like gen_lowpart_general but for use by combine. In combine it
11756 is not possible to create any new pseudoregs. However, it is
11757 safe to create invalid memory addresses, because combine will
11758 try to recognize them and all they will do is make the combine
11759 attempt fail.
11761 If for some reason this cannot do its job, an rtx
11762 (clobber (const_int 0)) is returned.
11763 An insn containing that will not be recognized. */
11765 static rtx
11767 {
11769 rtx result;
11774 /* We can only support MODE being wider than a word if X is a
11775 constant integer or has a mode the same size. */
11781 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11782 won't know what to do. So we will strip off the SUBREG here and
11783 process normally. */
11785 {
11788 /* For use in case we fall down into the address adjustments
11789 further below, we need to adjust the known mode and size of
11790 x; imode and isize, since we just adjusted x. */
11795 }
11803 {
11804 /* Refuse to work on a volatile memory ref or one with a mode-dependent
11805 address. */
11810 /* If we want to refer to something bigger than the original memref,
11811 generate a paradoxical subreg instead. That will force a reload
11812 of the original memref X. */
11818 }
11820 /* If X is a comparison operator, rewrite it in a new mode. This
11821 probably won't match, but may allow further simplifications. */
11825 /* If we couldn't simplify X any other way, just enclose it in a
11826 SUBREG. Normally, this SUBREG won't match, but some patterns may
11827 include an explicit SUBREG or we may simplify it further in combine. */
11828 else
11829 {
11830 rtx res;
11833 {
11838 }
11842 }
11844 fail:
11846 }
11847 \f
11848 /* Try to simplify a comparison between OP0 and a constant OP1,
11849 where CODE is the comparison code that will be tested, into a
11850 (CODE OP0 const0_rtx) form.
11852 The result is a possibly different comparison code to use.
11853 *POP1 may be updated. */
11855 static enum rtx_code
11858 {
11859 scalar_int_mode int_mode;
11862 /* Get the constant we are comparing against and turn off all bits
11863 not on in our mode. */
11867 /* If we are comparing against a constant power of two and the value
11868 being compared can only have that single bit nonzero (e.g., it was
11869 `and'ed with that bit), we can replace this with a comparison
11870 with zero. */
11879 {
11882 }
11884 /* Similarly, if we are comparing a value known to be either -1 or
11885 0 with -1, change it to the opposite comparison against zero. */
11891 {
11894 }
11896 /* Do some canonicalizations based on the comparison code. We prefer
11897 comparisons against zero and then prefer equality comparisons.
11898 If we can reduce the size of a constant, we will do that too. */
11900 {
11902 /* < C is equivalent to <= (C - 1) */
11904 {
11907 /* ... fall through to LE case below. */
11909 }
11910 else
11914 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
11916 {
11919 }
11921 /* If we are doing a <= 0 comparison on a value known to have
11922 a zero sign bit, we can replace this with == 0. */
11933 /* >= C is equivalent to > (C - 1). */
11935 {
11938 /* ... fall through to GT below. */
11940 }
11941 else
11945 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
11947 {
11950 }
11952 /* If we are doing a > 0 comparison on a value known to have
11953 a zero sign bit, we can replace this with != 0. */
11964 /* < C is equivalent to <= (C - 1). */
11966 {
11969 /* ... fall through ... */
11971 }
11972 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
11977 {
11981 }
11982 else
11986 /* unsigned <= 0 is equivalent to == 0 */
11989 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11993 == ((HOST_WIDE_INT_1U
11995 {
11998 }
12002 /* >= C is equivalent to > (C - 1). */
12004 {
12007 /* ... fall through ... */
12009 }
12011 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
12016 {
12020 }
12021 else
12025 /* unsigned > 0 is equivalent to != 0 */
12028 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
12032 == (HOST_WIDE_INT_1U
12034 {
12037 }
12042 }
12046 }
12047 \f
12048 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
12049 comparison code that will be tested.
12051 The result is a possibly different comparison code to use. *POP0 and
12052 *POP1 may be updated.
12054 It is possible that we might detect that a comparison is either always
12055 true or always false. However, we do not perform general constant
12056 folding in combine, so this knowledge isn't useful. Such tautologies
12057 should have been detected earlier. Hence we ignore all such cases. */
12059 static enum rtx_code
12061 {
12067 opt_scalar_int_mode tmode_iter;
12069 /* Try a few ways of applying the same transformation to both operands. */
12071 {
12072 /* The test below this one won't handle SIGN_EXTENDs on these machines,
12073 so check specially. */
12092 {
12095 }
12097 /* If both operands are the same constant shift, see if we can ignore the
12098 shift. We can if the shift is a rotate or if the bits shifted out of
12099 this shift are known to be zero for both inputs and if the type of
12100 comparison is compatible with the shift. */
12113 {
12126 else
12128 }
12130 /* If both operands are AND's of a paradoxical SUBREG by constant, the
12131 SUBREGs are of the same mode, and, in both cases, the AND would
12132 be redundant if the comparison was done in the narrower mode,
12133 do the comparison in the narrower mode (e.g., we are AND'ing with 1
12134 and the operand's possibly nonzero bits are 0xffffff01; in that case
12135 if we only care about QImode, we don't need the AND). This case
12136 occurs if the output mode of an scc insn is not SImode and
12137 STORE_FLAG_VALUE == 1 (e.g., the 386).
12139 Similarly, check for a case where the AND's are ZERO_EXTEND
12140 operations from some narrower mode even though a SUBREG is not
12141 present. */
12146 {
12162 {
12166 /* The resulting comparison is always unsigned since we masked
12167 off the original sign bit. */
12171 }
12177 {
12183 }
12187 }
12189 /* If both operands are NOT, we can strip off the outer operation
12190 and adjust the comparison code for swapped operands; similarly for
12191 NEG, except that this must be an equality comparison. */
12197 else
12199 }
12201 /* If the first operand is a constant, swap the operands and adjust the
12202 comparison code appropriately, but don't do this if the second operand
12203 is already a constant integer. */
12205 {
12208 }
12210 /* We now enter a loop during which we will try to simplify the comparison.
12211 For the most part, we only are concerned with comparisons with zero,
12212 but some things may really be comparisons with zero but not start
12213 out looking that way. */
12216 {
12218 scalar_int_mode int_mode;
12222 HOST_WIDE_INT const_op;
12224 /* We only want to handle integral modes. This catches VOIDmode,
12225 CCmode, and the floating-point modes. An exception is that we
12226 can handle VOIDmode if OP0 is a COMPARE or a comparison
12227 operation. */
12234 /* Try to simplify the compare to constant, possibly changing the
12235 comparison op, and/or changing op1 to zero. */
12239 /* Compute some predicates to simplify code below. */
12246 /* If this is a sign bit comparison and we can do arithmetic in
12247 MODE, say that we will only be needing the sign bit of OP0. */
12252 HOST_WIDE_INT_1U
12257 {
12258 /* We can't do anything if OP0 is a condition code value, rather
12259 than an actual data value. */
12265 /* Get the two operands being compared. */
12268 else
12271 /* Check for the cases where we simply want the result of the
12272 earlier test or the opposite of that result. */
12276 {
12280 else
12284 {
12289 }
12290 }
12292 }
12298 /* Now try cases based on the opcode of OP0. If none of the cases
12299 does a "continue", we exit this loop immediately after the
12300 switch. */
12305 {
12307 /* If we are extracting a single bit from a variable position in
12308 a constant that has only a single bit set and are comparing it
12309 with zero, we can convert this into an equality comparison
12310 between the position and the location of the single bit. */
12311 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12312 have already reduced the shift count modulo the word size. */
12318 {
12326 /* Result is nonzero iff shift count is equal to I. */
12329 }
12331 /* fall through */
12336 {
12339 }
12343 /* If testing for equality, we can take the NOT of the constant. */
12346 {
12350 }
12352 /* If just looking at the sign bit, reverse the sense of the
12353 comparison. */
12355 {
12359 }
12363 /* If testing for equality, we can take the NEG of the constant. */
12366 {
12370 }
12372 /* The remaining cases only apply to comparisons with zero. */
12376 /* When X is ABS or is known positive,
12377 (neg X) is < 0 if and only if X != 0. */
12385 {
12389 }
12391 /* If we have NEG of something whose two high-order bits are the
12392 same, we know that "(-a) < 0" is equivalent to "a > 0". */
12394 {
12398 }
12402 /* If we are testing equality and our count is a constant, we
12403 can perform the inverse operation on our RHS. */
12407 {
12411 }
12413 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
12414 a particular bit. Convert it to an AND of a constant of that
12415 bit. This will be converted into a ZERO_EXTRACT. */
12419 {
12421 (HOST_WIDE_INT_1U
12426 }
12428 /* Fall through. */
12431 /* ABS is ignorable inside an equality comparison with zero. */
12433 {
12436 }
12440 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
12441 (compare FOO CONST) if CONST fits in FOO's mode and we
12442 are either testing inequality or have an unsigned
12443 comparison with ZERO_EXTEND or a signed comparison with
12444 SIGN_EXTEND. But don't do it if we don't have a compare
12445 insn of the given mode, since we'd have to revert it
12446 later on, and then we wouldn't know whether to sign- or
12447 zero-extend. */
12449 && ! unsigned_comparison_p
12453 {
12456 }
12460 /* Check for the case where we are comparing A - C1 with C2, that is
12462 (subreg:MODE (plus (A) (-C1))) op (C2)
12464 with C1 a constant, and try to lift the SUBREG, i.e. to do the
12465 comparison in the wider mode. One of the following two conditions
12466 must be true in order for this to be valid:
12468 1. The mode extension results in the same bit pattern being added
12469 on both sides and the comparison is equality or unsigned. As
12470 C2 has been truncated to fit in MODE, the pattern can only be
12471 all 0s or all 1s.
12473 2. The mode extension results in the sign bit being copied on
12474 each side.
12476 The difficulty here is that we have predicates for A but not for
12477 (A - C1) so we need to check that C1 is within proper bounds so
12478 as to perturbate A as little as possible. */
12487 {
12495 /* (A - C1) zero-extends if it is positive and sign-extends
12496 if it is negative, C2 both zero- and sign-extends. */
12500 /* (A - C1) sign-extends if it is positive and 1-extends
12501 if it is negative, C2 both sign- and 1-extends. */
12508 /* (A - C1) always sign-extends, like C2. */
12512 {
12515 }
12516 }
12518 /* If the inner mode is narrower and we are extracting the low part,
12519 we can treat the SUBREG as if it were a ZERO_EXTEND. */
12521 ;
12530 {
12531 /* Remove outer subregs that don't do anything. */
12536 {
12540 }
12542 }
12543 else
12546 /* FALLTHROUGH */
12555 {
12558 }
12562 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12563 this for equality comparisons due to pathological cases involving
12564 overflows. */
12568 {
12572 }
12574 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12577 {
12581 }
12585 /* We used to optimize signed comparisons against zero, but that
12586 was incorrect. Unsigned comparisons against zero (GTU, LEU)
12587 arrive here as equality comparisons, or (GEU, LTU) are
12588 optimized away. No need to special-case them. */
12590 /* (eq (minus A B) C) -> (eq A (plus B C)) or
12591 (eq B (minus A C)), whichever simplifies. We can only do
12592 this for equality comparisons due to pathological cases involving
12593 overflows. */
12597 {
12601 }
12606 {
12610 }
12612 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
12613 of bits in X minus 1, is one iff X > 0. */
12618 {
12622 }
12626 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12627 if C is zero or B is a constant. */
12631 {
12635 }
12640 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12641 iff X <= 0. */
12645 {
12649 }
12653 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12654 will be converted to a ZERO_EXTRACT later. */
12658 {
12663 }
12665 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
12666 zero and X is a comparison and C1 and C2 describe only bits set
12667 in STORE_FLAG_VALUE, we can compare with X. */
12675 {
12682 {
12685 }
12686 }
12688 /* If we are doing an equality comparison of an AND of a bit equal
12689 to the sign bit, replace this with a LT or GE comparison of
12690 the underlying value. */
12697 {
12701 }
12703 /* If this AND operation is really a ZERO_EXTEND from a narrower
12704 mode, the constant fits within that mode, and this is either an
12705 equality or unsigned comparison, try to do this comparison in
12706 the narrower mode.
12708 Note that in:
12710 (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12711 -> (ne:DI (reg:SI 4) (const_int 0))
12713 unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12714 known to hold a value of the required mode the
12715 transformation is invalid. */
12723 {
12726 }
12728 /* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12729 fits in both M1 and M2 and the SUBREG is either paradoxical
12730 or represents the low part, permute the SUBREG and the AND
12731 and try again. */
12734 {
12736 /* Require an integral mode, to avoid creating something like
12737 (AND:SF ...). */
12740 /* It is unsafe to commute the AND into the SUBREG if the
12741 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12742 not defined. As originally written the upper bits
12743 have a defined value due to the AND operation.
12744 However, if we commute the AND inside the SUBREG then
12745 they no longer have defined values and the meaning of
12746 the code has been changed.
12747 Also C1 should not change value in the smaller mode,
12748 see PR67028 (a positive C1 can become negative in the
12749 smaller mode, so that the AND does no longer mask the
12750 upper bits). */
12751 && ((WORD_REGISTER_OPERATIONS
12763 {
12769 }
12770 }
12772 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12776 {
12781 }
12783 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12784 (eq (and (lshiftrt X) 1) 0).
12785 Also handle the case where (not X) is expressed using xor. */
12789 {
12799 == HOST_WIDE_INT_1U
12801 {
12802 op0
12807 }
12808 }
12812 /* If we have (compare (ashift FOO N) (const_int C)) and
12813 the high order N bits of FOO (N+1 if an inequality comparison)
12814 are known to be zero, we can do this by comparing FOO with C
12815 shifted right N bits so long as the low-order N bits of C are
12816 zero. */
12828 {
12829 /* We must perform a logical shift, not an arithmetic one,
12830 as we want the top N bits of C to be zero. */
12837 }
12839 /* If we are doing a sign bit comparison, it means we are testing
12840 a particular bit. Convert it to the appropriate AND. */
12843 {
12845 (HOST_WIDE_INT_1U
12850 }
12852 /* If this an equality comparison with zero and we are shifting
12853 the low bit to the sign bit, we can convert this to an AND of the
12854 low-order bit. */
12858 {
12861 }
12865 /* If this is an equality comparison with zero, we can do this
12866 as a logical shift, which might be much simpler. */
12869 {
12874 }
12876 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
12877 do the comparison in a narrower mode. */
12887 {
12890 }
12892 /* Likewise if OP0 is a PLUS of a sign extension with a
12893 constant, which is usually represented with the PLUS
12894 between the shifts. */
12906 {
12914 new_const);
12916 }
12918 /* FALLTHROUGH */
12920 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
12921 the low order N bits of FOO are known to be zero, we can do this
12922 by comparing FOO with C shifted left N bits so long as no
12923 overflow occurs. Even if the low order N bits of FOO aren't known
12924 to be zero, if the comparison is >= or < we can use the same
12925 optimization and for > or <= by setting all the low
12926 order N bits in the comparison constant. */
12937 {
12938 unsigned HOST_WIDE_INT low_bits
12940 & ((HOST_WIDE_INT_1U
12943 {
12944 /* If the shift was logical, then we must make the condition
12945 unsigned. */
12954 const_op
12959 }
12960 }
12962 /* If we are using this shift to extract just the sign bit, we
12963 can replace this with an LT or GE comparison. */
12968 {
12972 }
12977 }
12980 }
12982 /* Now make any compound operations involved in this comparison. Then,
12983 check for an outmost SUBREG on OP0 that is not doing anything or is
12984 paradoxical. The latter transformation must only be performed when
12985 it is known that the "extra" bits will be the same in op0 and op1 or
12986 that they don't matter. There are three cases to consider:
12988 1. SUBREG_REG (op0) is a register. In this case the bits are don't
12989 care bits and we can assume they have any convenient value. So
12990 making the transformation is safe.
12992 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
12993 In this case the upper bits of op0 are undefined. We should not make
12994 the simplification in that case as we do not know the contents of
12995 those bits.
12997 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
12998 In that case we know those bits are zeros or ones. We must also be
12999 sure that they are the same as the upper bits of op1.
13001 We can never remove a SUBREG for a non-equality comparison because
13002 the sign bit is in a different place in the underlying object. */
13015 {
13017 {
13018 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
13019 implemented. */
13021 {
13024 }
13025 }
13029 {
13034 }
13035 }
13037 /* We now do the opposite procedure: Some machines don't have compare
13038 insns in all modes. If OP0's mode is an integer mode smaller than a
13039 word and we can't do a compare in that mode, see if there is a larger
13040 mode for which we can do the compare. There are a number of cases in
13041 which we can use the wider mode. */
13047 {
13052 {
13055 /* If this is a test for negative, we can make an explicit
13056 test of the sign bit. Test this first so we can use
13057 a paradoxical subreg to extend OP0. */
13061 {
13062 unsigned HOST_WIDE_INT sign
13069 }
13071 /* If the only nonzero bits in OP0 and OP1 are those in the
13072 narrower mode and this is an equality or unsigned comparison,
13073 we can use the wider mode. Similarly for sign-extended
13074 values, in which case it is true for all comparisons. */
13091 {
13092 /* If OP0 is an AND and we don't have an AND in MODE either,
13093 make a new AND in the proper mode. */
13101 else
13102 {
13104 {
13109 }
13110 else
13111 {
13116 }
13118 }
13119 }
13120 }
13121 }
13123 /* We may have changed the comparison operands. Re-canonicalize. */
13125 {
13128 }
13130 /* If this machine only supports a subset of valid comparisons, see if we
13131 can convert an unsupported one into a supported one. */
13138 }
13139 \f
13140 /* Utility function for record_value_for_reg. Count number of
13141 rtxs in X. */
13142 static int
13144 {
13151 {
13171 }
13182 }
13183 \f
13184 /* Utility function for following routine. Called when X is part of a value
13185 being stored into last_set_value. Sets last_set_table_tick
13186 for each register mentioned. Similar to mention_regs in cse.c */
13188 static void
13190 {
13196 {
13202 {
13205 }
13208 }
13212 {
13213 /* Check for identical subexpressions. If x contains
13214 identical subexpression we only have to traverse one of
13215 them. */
13217 {
13218 /* Note that at this point x1 has already been
13219 processed. */
13223 /* If x0 and x1 are identical then there is no need to
13224 process x0. */
13228 /* If x0 is identical to a subexpression of x1 then while
13229 processing x1, x0 has already been processed. Thus we
13230 are done with x. */
13235 /* If x1 is identical to a subexpression of x0 then we
13236 still have to process the rest of x0. */
13239 {
13242 }
13243 }
13246 }
13250 }
13252 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13253 are saying that the register is clobbered and we no longer know its
13254 value. If INSN is zero, don't update reg_stat[].last_set; this is
13255 only permitted with VALUE also zero and is used to invalidate the
13256 register. */
13258 static void
13260 {
13266 /* If VALUE contains REG and we have a previous value for REG, substitute
13267 the previous value. */
13269 {
13270 rtx tem;
13272 /* Set things up so get_last_value is allowed to see anything set up to
13273 our insn. */
13277 /* If TEM is simply a binary operation with two CLOBBERs as operands,
13278 it isn't going to be useful and will take a lot of time to process,
13279 so just use the CLOBBER. */
13282 {
13288 {
13289 /* If there are two or more occurrences of REG in VALUE,
13290 prevent the value from growing too much. */
13293 }
13296 }
13297 }
13299 /* For each register modified, show we don't know its value, that
13300 we don't know about its bitwise content, that its value has been
13301 updated, and that we don't know the location of the death of the
13302 register. */
13304 {
13316 }
13318 /* Mark registers that are being referenced in this value. */
13322 /* Now update the status of each register being set.
13323 If someone is using this register in this block, set this register
13324 to invalid since we will get confused between the two lives in this
13325 basic block. This makes using this register always invalid. In cse, we
13326 scan the table to invalidate all entries using this register, but this
13327 is too much work for us. */
13330 {
13336 else
13338 }
13340 /* The value being assigned might refer to X (like in "x++;"). In that
13341 case, we must replace it with (clobber (const_int 0)) to prevent
13342 infinite loops. */
13345 {
13349 }
13351 /* For the main register being modified, update the value, the mode, the
13352 nonzero bits, and the number of sign bit copies. */
13357 {
13365 rsp->last_set_sign_bit_copies
13367 }
13368 }
13370 /* Called via note_stores from record_dead_and_set_regs to handle one
13371 SET or CLOBBER in an insn. DATA is the instruction in which the
13372 set is occurring. */
13374 static void
13376 {
13383 {
13387 }
13390 {
13391 /* If we are setting the whole register, we know its value. Otherwise
13392 show that we don't know the value. We can handle a SUBREG if it's
13393 the low part, but we must be careful with paradoxical SUBREGs on
13394 RISC architectures because we cannot strip e.g. an extension around
13395 a load and record the naked load since the RTL middle-end considers
13396 that the upper bits are defined according to LOAD_EXTEND_OP. */
13403 BITS_PER_WORD)
13406 WORD_REGISTER_OPERATIONS
13413 {
13416 && reg_is_clobbered_by_clobber_high
13420 }
13421 else
13423 }
13425 /* Ignore pushes, they clobber nothing. */
13428 }
13430 /* Update the records of when each REG was most recently set or killed
13431 for the things done by INSN. This is the last thing done in processing
13432 INSN in the combiner loop.
13434 We update reg_stat[], in particular fields last_set, last_set_value,
13435 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13436 last_death, and also the similar information mem_last_set (which insn
13437 most recently modified memory) and last_call_luid (which insn was the
13438 most recent subroutine call). */
13440 static void
13442 {
13443 rtx link;
13447 {
13450 {
13455 {
13460 }
13461 }
13464 }
13467 {
13468 hard_reg_set_iterator hrsi;
13470 {
13482 }
13486 /* We can't combine into a call pattern. Remember, though, that
13487 the return value register is set at this LUID. We could
13488 still replace a register with the return value from the
13489 wrong subroutine call! */
13491 }
13492 else
13494 }
13496 /* If a SUBREG has the promoted bit set, it is in fact a property of the
13497 register present in the SUBREG, so for each such SUBREG go back and
13498 adjust nonzero and sign bit information of the registers that are
13499 known to have some zero/sign bits set.
13501 This is needed because when combine blows the SUBREGs away, the
13502 information on zero/sign bits is lost and further combines can be
13503 missed because of that. */
13505 static void
13507 {
13509 rtx set;
13517 {
13526 {
13529 }
13533 {
13536 }
13539 {
13542 }
13543 else
13545 }
13546 }
13548 /* Check if X, a register, is known to contain a value already
13549 truncated to MODE. In this case we can use a subreg to refer to
13550 the truncated value even though in the generic case we would need
13551 an explicit truncation. */
13553 static bool
13555 {
13567 }
13569 /* If X is a hard reg or a subreg record the mode that the register is
13570 accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13571 able to turn a truncate into a subreg using this information. Return true
13572 if traversing X is complete. */
13574 static bool
13576 {
13577 machine_mode truncated_mode;
13581 {
13593 }
13594 /* ??? For hard-regs we now record everything. We might be able to
13595 optimize this using last_set_mode. */
13598 else
13605 {
13608 }
13611 }
13613 /* Callback for note_uses. Find hardregs and subregs of pseudos and
13614 the modes they are used in. This can help truning TRUNCATEs into
13615 SUBREGs. */
13617 static void
13619 {
13624 }
13626 /* Scan X for promoted SUBREGs. For each one found,
13627 note what it implies to the registers used in it. */
13629 static void
13631 {
13636 else
13637 {
13643 {
13653 }
13654 }
13655 }
13656 \f
13657 /* Verify that all the registers and memory references mentioned in *LOC are
13658 still valid. *LOC was part of a value set in INSN when label_tick was
13659 equal to TICK. Return 0 if some are not. If REPLACE is nonzero, replace
13660 the invalid references with (clobber (const_int 0)) and return 1. This
13661 replacement is useful because we often can get useful information about
13662 the form of a value (e.g., if it was produced by a shift that always
13663 produces -1 or 0) even though we don't know exactly what registers it
13664 was produced from. */
13666 static int
13668 {
13675 {
13681 {
13684 /* If this is a pseudo-register that was only set once and not
13685 live at the beginning of the function, it is always valid. */
13689 && (!REGNO_REG_SET_P
13691 regno)))
13693 {
13697 }
13698 }
13701 }
13702 /* If this is a memory reference, make sure that there were no stores after
13703 it that might have clobbered the value. We don't have alias info, so we
13704 assume any store invalidates it. Moreover, we only have local UIDs, so
13705 we also assume that there were stores in the intervening basic blocks. */
13708 {
13712 }
13715 {
13717 {
13718 /* Check for identical subexpressions. If x contains
13719 identical subexpression we only have to traverse one of
13720 them. */
13722 {
13723 /* Note that at this point x0 has already been checked
13724 and found valid. */
13728 /* If x0 and x1 are identical then x is also valid. */
13732 /* If x1 is identical to a subexpression of x0 then
13733 while checking x0, x1 has already been checked. Thus
13734 it is valid and so as x. */
13739 /* If x0 is identical to a subexpression of x1 then x is
13740 valid iff the rest of x1 is valid. */
13743 return
13747 }
13752 }
13758 }
13760 /* If we haven't found a reason for it to be invalid, it is valid. */
13762 }
13764 /* Get the last value assigned to X, if known. Some registers
13765 in the value may be replaced with (clobber (const_int 0)) if their value
13766 is known longer known reliably. */
13768 static rtx
13770 {
13772 rtx value;
13775 /* If this is a non-paradoxical SUBREG, get the value of its operand and
13776 then convert it to the desired mode. If this is a paradoxical SUBREG,
13777 we cannot predict what values the "extra" bits might have. */
13791 /* If we don't have a value, or if it isn't for this basic block and
13792 it's either a hard register, set more than once, or it's a live
13793 at the beginning of the function, return 0.
13795 Because if it's not live at the beginning of the function then the reg
13796 is always set before being used (is never used without being set).
13797 And, if it's set only once, and it's always set before use, then all
13798 uses must have the same last value, even if it's not from this basic
13799 block. */
13806 || REGNO_REG_SET_P
13810 /* If the value was set in a later insn than the ones we are processing,
13811 we can't use it even if the register was only set once. */
13816 /* If fewer bits were set than what we are asked for now, we cannot use
13817 the value. */
13822 /* If the value has all its registers valid, return it. */
13826 /* Otherwise, make a copy and replace any invalid register with
13827 (clobber (const_int 0)). If that fails for some reason, return 0. */
13834 }
13835 \f
13836 /* Define three variables used for communication between the following
13837 routines. */
13841 rtx reg_dead_reg;
13843 /* Function called via note_stores from reg_dead_at_p.
13845 If DEST is within [reg_dead_regno, reg_dead_endregno), set
13846 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13848 static void
13850 {
13864 }
13866 /* Return nonzero if REG is known to be dead at INSN.
13868 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13869 referencing REG, it is dead. If we hit a SET referencing REG, it is
13870 live. Otherwise, see if it is live or dead at the start of the basic
13871 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13872 must be assumed to be always live. */
13874 static int
13876 {
13877 basic_block block;
13880 /* Set variables for reg_dead_at_p_1. */
13887 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13888 we allow the machine description to decide whether use-and-clobber
13889 patterns are OK. */
13891 {
13895 }
13897 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13898 beginning of basic block. */
13901 {
13903 {
13913 }
13919 }
13921 /* Look at live-in sets for the basic block that we were in. */
13927 }
13928 \f
13929 /* Note hard registers in X that are used. */
13931 static void
13933 {
13939 {
13943 CASE_CONST_ANY:
13948 /* CC0 must die in the insn after it is set, so we don't need to take
13949 special note of it here. */
13954 /* If we are clobbering a MEM, mark any hard registers inside the
13955 address as used. */
13962 /* A hard reg in a wide mode may really be multiple registers.
13963 If so, mark all of them just like the first. */
13965 {
13966 /* None of this applies to the stack, frame or arg pointers. */
13968 || (!HARD_FRAME_POINTER_IS_FRAME_POINTER
13976 }
13980 {
13981 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
13982 the address. */
13994 }
13999 }
14001 /* Recursively scan the operands of this expression. */
14003 {
14007 {
14011 {
14016 }
14017 }
14018 }
14019 }
14020 \f
14021 /* Remove register number REGNO from the dead registers list of INSN.
14023 Return the note used to record the death, if there was one. */
14025 rtx
14027 {
14034 }
14036 /* For each register (hardware or pseudo) used within expression X, if its
14037 death is in an instruction with luid between FROM_LUID (inclusive) and
14038 TO_INSN (exclusive), put a REG_DEAD note for that register in the
14039 list headed by PNOTES.
14041 That said, don't move registers killed by maybe_kill_insn.
14043 This is done when X is being merged by combination into TO_INSN. These
14044 notes will then be distributed as needed. */
14046 static void
14049 {
14055 {
14059 /* If we do not know where the register died, it may still die between
14060 FROM_LUID and TO_INSN. If so, find it. This is PR83304. */
14062 {
14067 {
14069 {
14073 }
14076 }
14077 }
14079 /* Don't move the register if it gets killed in between from and to. */
14088 {
14091 /* It is possible for the call above to return 0. This can occur
14092 when last_death points to I2 or I1 that we combined with.
14093 In that case make a new note.
14095 We must also check for the case where X is a hard register
14096 and NOTE is a death note for a range of hard registers
14097 including X. In that case, we must put REG_DEAD notes for
14098 the remaining registers in place of NOTE. */
14102 {
14111 }
14113 /* If we didn't find any note, or if we found a REG_DEAD note that
14114 covers only part of the given reg, and we have a multi-reg hard
14115 register, then to be safe we must check for REG_DEAD notes
14116 for each register other than the first. They could have
14117 their own REG_DEAD notes lying around. */
14124 {
14131 else
14137 }
14140 {
14143 }
14144 else
14146 }
14149 }
14152 {
14157 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
14158 that accesses one word of a multi-word item, some
14159 piece of everything register in the expression is used by
14160 this insn, so remove any old death. */
14161 /* ??? So why do we test for equality of the sizes? */
14167 {
14170 }
14172 /* If this is some other SUBREG, we know it replaces the entire
14173 value, so use that as the destination. */
14177 /* If this is a MEM, adjust deaths of anything used in the address.
14178 For a REG (the only other possibility), the entire value is
14179 being replaced so the old value is not used in this insn. */
14185 }
14194 {
14196 {
14201 }
14204 }
14205 }
14206 \f
14207 /* Return 1 if X is the target of a bit-field assignment in BODY, the
14208 pattern of an insn. X must be a REG. */
14210 static int
14212 {
14216 {
14218 rtx target;
14225 else
14242 }
14250 }
14251 \f
14252 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14253 as appropriate. I3 and I2 are the insns resulting from the combination
14254 insns including FROM (I2 may be zero).
14256 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14257 not need REG_DEAD notes because they are being substituted for. This
14258 saves searching in the most common cases.
14260 Each note in the list is either ignored or placed on some insns, depending
14261 on the type of note. */
14263 static void
14266 {
14268 rtx tem_note;
14272 {
14277 {
14280 /* Doesn't matter much where we put this, as long as it's somewhere.
14281 It is preferable to keep these notes on branches, which is most
14282 likely to be i3. */
14289 else
14290 {
14293 }
14297 /* These notes must remain with the call or trapping instruction. */
14302 else
14303 {
14309 /* ??? Otherwise assume we've combined things such that we
14310 can now prove that the instructions can't trap. Drop the
14311 note in this case. */
14312 }
14316 /* ??? How to distribute between i3-i1. Assume i3 contains the
14317 entire adjustment. Assert i3 contains at least some adjust. */
14319 {
14321 /* fixup_args_size_notes looks at REG_NORETURN note,
14322 so ensure the note is placed there first. */
14324 {
14328 {
14334 }
14335 }
14337 /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14338 REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14341 && !ACCUMULATE_OUTGOING_ARGS
14343 }
14351 /* These notes must remain with the call. It should not be
14352 possible for both I2 and I3 to be a call. */
14355 else
14356 {
14359 }
14363 /* Any clobbers for i3 may still exist, and so we must process
14364 REG_UNUSED notes from that insn.
14366 Any clobbers from i2 or i1 can only exist if they were added by
14367 recog_for_combine. In that case, recog_for_combine created the
14368 necessary REG_UNUSED notes. Trying to keep any original
14369 REG_UNUSED notes from these insns can cause incorrect output
14370 if it is for the same register as the original i3 dest.
14371 In that case, we will notice that the register is set in i3,
14372 and then add a REG_UNUSED note for the destination of i3, which
14373 is wrong. However, it is possible to have REG_UNUSED notes from
14374 i2 or i1 for register which were both used and clobbered, so
14375 we keep notes from i2 or i1 if they will turn into REG_DEAD
14376 notes. */
14378 /* If this register is set or clobbered in I3, put the note there
14379 unless there is one already. */
14381 {
14389 }
14390 /* Otherwise, if this register is used by I3, then this register
14391 now dies here, so we must put a REG_DEAD note here unless there
14392 is one already. */
14398 {
14401 }
14403 /* A SET or CLOBBER of the REG_UNUSED reg has been removed,
14404 but we can't tell which at this point. We must reset any
14405 expectations we had about the value that was previously
14406 stored in the reg. ??? Ideally, we'd adjust REG_N_SETS
14407 and, if appropriate, restore its previous value, but we
14408 don't have enough information for that at this point. */
14409 else
14410 {
14413 /* Otherwise, if this register is now referenced in i2
14414 then the register used to be modified in one of the
14415 original insns. If it was i3 (say, in an unused
14416 parallel), it's now completely gone, so the note can
14417 be discarded. But if it was modified in i2, i1 or i0
14418 and we still reference it in i2, then we're
14419 referencing the previous value, and since the
14420 register was modified and REG_UNUSED, we know that
14421 the previous value is now dead. So, if we only
14422 reference the register in i2, we change the note to
14423 REG_DEAD, to reflect the previous value. However, if
14424 we're also setting or clobbering the register as
14425 scratch, we know (because the register was not
14426 referenced in i3) that it's unused, just as it was
14427 unused before, and we place the note in i2. */
14430 {
14439 }
14440 }
14447 /* These notes say something about results of an insn. We can
14448 only support them if they used to be on I3 in which case they
14449 remain on I3. Otherwise they are ignored.
14451 If the note refers to an expression that is not a constant, we
14452 must also ignore the note since we cannot tell whether the
14453 equivalence is still true. It might be possible to do
14454 slightly better than this (we only have a problem if I2DEST
14455 or I1DEST is present in the expression), but it doesn't
14456 seem worth the trouble. */
14464 /* These notes say something about how a register is used. They must
14465 be present on any use of the register in I2 or I3. */
14470 {
14473 else
14475 }
14480 /* This can show up in several ways -- either directly in the
14481 pattern, or hidden off in the constant pool with (or without?)
14482 a REG_EQUAL note. */
14483 /* ??? Ignore the without-reg_equal-note problem for now. */
14495 {
14498 else
14500 }
14502 /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14503 as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14504 there. */
14509 {
14516 }
14522 {
14530 }
14534 /* This note says something about the value of a register prior
14535 to the execution of an insn. It is too much trouble to see
14536 if the note is still correct in all situations. It is better
14537 to simply delete it. */
14541 /* If we replaced the right hand side of FROM_INSN with a
14542 REG_EQUAL note, the original use of the dying register
14543 will not have been combined into I3 and I2. In such cases,
14544 FROM_INSN is guaranteed to be the first of the combined
14545 instructions, so we simply need to search back before
14546 FROM_INSN for the previous use or set of this register,
14547 then alter the notes there appropriately.
14549 If the register is used as an input in I3, it dies there.
14550 Similarly for I2, if it is nonzero and adjacent to I3.
14552 If the register is not used as an input in either I3 or I2
14553 and it is not one of the registers we were supposed to eliminate,
14554 there are two possibilities. We might have a non-adjacent I2
14555 or we might have somehow eliminated an additional register
14556 from a computation. For example, we might have had A & B where
14557 we discover that B will always be zero. In this case we will
14558 eliminate the reference to A.
14560 In both cases, we must search to see if we can find a previous
14561 use of A and put the death note there. */
14567 else
14568 {
14574 {
14575 /* If the new I2 sets the same register that is marked
14576 dead in the note, we do not in general know where to
14577 put the note. One important case we _can_ handle is
14578 when the note comes from I3. */
14581 else
14583 }
14590 && !(i2mod
14592 i2mod_old_rhs)))
14597 }
14600 {
14604 {
14606 {
14610 }
14612 /* If the register is being set at TEM_INSN, see if that is all
14613 TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14614 into a REG_UNUSED note instead. Don't delete sets to
14615 global register vars. */
14619 {
14630 ;
14632 /* Verify that it was the set, and not a clobber that
14633 modified the register.
14635 CC0 targets must be careful to maintain setter/user
14636 pairs. If we cannot delete the setter due to side
14637 effects, mark the user with an UNUSED note instead
14638 of deleting it. */
14642 && (!HAVE_cc0
14646 {
14647 /* Move the notes and links of TEM_INSN elsewhere.
14648 This might delete other dead insns recursively.
14649 First set the pattern to something that won't use
14650 any register. */
14669 /* Delete the setter too. */
14671 {
14684 }
14685 }
14686 else
14687 {
14690 /* If there isn't already a REG_UNUSED note, put one
14691 here. Do not place a REG_DEAD note, even if
14692 the register is also used here; that would not
14693 match the algorithm used in lifetime analysis
14694 and can cause the consistency check in the
14695 scheduler to fail. */
14700 }
14701 }
14705 {
14708 /* If we are doing a 3->2 combination, and we have a
14709 register which formerly died in i3 and was not used
14710 by i2, which now no longer dies in i3 and is used in
14711 i2 but does not die in i2, and place is between i2
14712 and i3, then we may need to move a link from place to
14713 i2. */
14715 && from_insn
14718 {
14722 }
14724 }
14728 }
14730 }
14732 /* If the register is set or already dead at PLACE, we needn't do
14733 anything with this note if it is still a REG_DEAD note.
14734 We check here if it is set at all, not if is it totally replaced,
14735 which is what `dead_or_set_p' checks, so also check for it being
14736 set partially. */
14739 {
14745 {
14746 /* Unless the register previously died in PLACE, clear
14747 last_death. [I no longer understand why this is
14748 being done.] */
14752 }
14753 else
14756 /* If this is a death note for a hard reg that is occupying
14757 multiple registers, ensure that we are still using all
14758 parts of the object. If we find a piece of the object
14759 that is unused, we must arrange for an appropriate REG_DEAD
14760 note to be added for it. However, we can't just emit a USE
14761 and tag the note to it, since the register might actually
14762 be dead; so we recourse, and the recursive call then finds
14763 the previous insn that used this register. */
14766 {
14775 {
14778 }
14781 {
14782 /* Put only REG_DEAD notes for pieces that are
14783 not already dead or set. */
14787 {
14794 {
14796 NULL_RTX);
14800 NULL_RTX);
14801 }
14806 {
14808 {
14812 }
14816 {
14819 }
14820 }
14821 }
14824 }
14825 }
14826 }
14830 /* Any other notes should not be present at this point in the
14831 compilation. */
14833 }
14836 {
14840 /* Set added_notes_insn to the earliest insn we added a note to. */
14844 }
14847 {
14850 /* Set added_notes_insn to the earliest insn we added a note to. */
14854 }
14855 }
14856 }
14857 \f
14858 /* Similarly to above, distribute the LOG_LINKS that used to be present on
14859 I3, I2, and I1 to new locations. This is also called to add a link
14860 pointing at I3 when I3's destination is changed. */
14862 static void
14864 {
14868 {
14875 /* If the insn that this link points to is a NOTE, ignore it. */
14884 {
14887 {
14903 }
14906 }
14907 else
14920 /* A LOG_LINK is defined as being placed on the first insn that uses
14921 a register and points to the insn that sets the register. Start
14922 searching at the next insn after the target of the link and stop
14923 when we reach a set of the register or the end of the basic block.
14925 Note that this correctly handles the link that used to point from
14926 I3 to I2. Also note that not much searching is typically done here
14927 since most links don't point very far away. */
14936 {
14940 }
14943 {
14946 }
14950 /* If we found a place to put the link, place it there unless there
14951 is already a link to the same insn as LINK at that point. */
14954 {
14962 {
14966 /* Set added_links_insn to the earliest insn we added a
14967 link to. */
14971 }
14972 }
14973 }
14974 }
14975 \f
14976 /* Check for any register or memory mentioned in EQUIV that is not
14977 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
14978 of EXPR where some registers may have been replaced by constants. */
14980 static bool
14982 {
14985 {
14990 }
14992 }
14993 \f
14994 DEBUG_FUNCTION void
14996 {
14997 fprintf
14999 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
15001 }
15003 void
15005 {
15006 fprintf
15008 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
15010 }
15011 \f
15012 /* Make pseudo-to-pseudo copies after every hard-reg-to-pseudo-copy, because
15013 the reg-to-reg copy can usefully combine with later instructions, but we
15014 do not want to combine the hard reg into later instructions, for that
15015 restricts register allocation. */
15016 static void
15018 {
15019 basic_block bb;
15022 {
15026 {
15049 }
15050 }
15051 }
15053 /* Try combining insns through substitution. */
15054 static unsigned int
15056 {
15066 int rebuild_jump_labels_after_combine
15069 /* Combining insns may have turned an indirect jump into a
15070 direct jump. Rebuild the JUMP_LABEL fields of jumping
15071 instructions. */
15073 {
15080 }
15084 }
15089 {
15099 };
15102 {
15106 {}
15108 /* opt_pass methods: */
15111 {
15113 }
15119 rtl_opt_pass *
15121 {
15123 }