1 /* Subroutines for gcc2 for pdp11.
2 Copyright (C) 1994-2018 Free Software Foundation, Inc.
3 Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
25 #include "coretypes.h"
30 #include "stringpool.h"
35 #include "insn-config.h"
39 #include "conditions.h"
41 #include "stor-layout.h"
49 /* This file should be included last. */
50 #include "target-def.h"
52 /* this is the current value returned by the macro FIRST_PARM_OFFSET
54 int current_first_parm_offset
;
56 /* Routines to encode/decode pdp11 floats */
57 static void encode_pdp11_f (const struct real_format
*fmt
,
58 long *, const REAL_VALUE_TYPE
*);
59 static void decode_pdp11_f (const struct real_format
*,
60 REAL_VALUE_TYPE
*, const long *);
61 static void encode_pdp11_d (const struct real_format
*fmt
,
62 long *, const REAL_VALUE_TYPE
*);
63 static void decode_pdp11_d (const struct real_format
*,
64 REAL_VALUE_TYPE
*, const long *);
66 /* These two are taken from the corresponding vax descriptors
67 in real.c, changing only the encode/decode routine pointers. */
68 const struct real_format pdp11_f_format
=
91 const struct real_format pdp11_d_format
=
115 encode_pdp11_f (const struct real_format
*fmt ATTRIBUTE_UNUSED
, long *buf
,
116 const REAL_VALUE_TYPE
*r
)
118 (*vax_f_format
.encode
) (fmt
, buf
, r
);
119 buf
[0] = ((buf
[0] >> 16) & 0xffff) | ((buf
[0] & 0xffff) << 16);
123 decode_pdp11_f (const struct real_format
*fmt ATTRIBUTE_UNUSED
,
124 REAL_VALUE_TYPE
*r
, const long *buf
)
127 tbuf
= ((buf
[0] >> 16) & 0xffff) | ((buf
[0] & 0xffff) << 16);
128 (*vax_f_format
.decode
) (fmt
, r
, &tbuf
);
132 encode_pdp11_d (const struct real_format
*fmt ATTRIBUTE_UNUSED
, long *buf
,
133 const REAL_VALUE_TYPE
*r
)
135 (*vax_d_format
.encode
) (fmt
, buf
, r
);
136 buf
[0] = ((buf
[0] >> 16) & 0xffff) | ((buf
[0] & 0xffff) << 16);
137 buf
[1] = ((buf
[1] >> 16) & 0xffff) | ((buf
[1] & 0xffff) << 16);
141 decode_pdp11_d (const struct real_format
*fmt ATTRIBUTE_UNUSED
,
142 REAL_VALUE_TYPE
*r
, const long *buf
)
145 tbuf
[0] = ((buf
[0] >> 16) & 0xffff) | ((buf
[0] & 0xffff) << 16);
146 tbuf
[1] = ((buf
[1] >> 16) & 0xffff) | ((buf
[1] & 0xffff) << 16);
147 (*vax_d_format
.decode
) (fmt
, r
, tbuf
);
150 static const char *singlemove_string (rtx
*);
151 static bool pdp11_assemble_integer (rtx
, unsigned int, int);
152 static bool pdp11_rtx_costs (rtx
, machine_mode
, int, int, int *, bool);
153 static bool pdp11_return_in_memory (const_tree
, const_tree
);
154 static rtx
pdp11_function_value (const_tree
, const_tree
, bool);
155 static rtx
pdp11_libcall_value (machine_mode
, const_rtx
);
156 static bool pdp11_function_value_regno_p (const unsigned int);
157 static void pdp11_trampoline_init (rtx
, tree
, rtx
);
158 static rtx
pdp11_function_arg (cumulative_args_t
, machine_mode
,
160 static void pdp11_function_arg_advance (cumulative_args_t
,
161 machine_mode
, const_tree
, bool);
162 static void pdp11_conditional_register_usage (void);
163 static bool pdp11_legitimate_constant_p (machine_mode
, rtx
);
165 static bool pdp11_scalar_mode_supported_p (scalar_mode
);
167 /* Initialize the GCC target structure. */
168 #undef TARGET_ASM_BYTE_OP
169 #define TARGET_ASM_BYTE_OP NULL
170 #undef TARGET_ASM_ALIGNED_HI_OP
171 #define TARGET_ASM_ALIGNED_HI_OP NULL
172 #undef TARGET_ASM_ALIGNED_SI_OP
173 #define TARGET_ASM_ALIGNED_SI_OP NULL
174 #undef TARGET_ASM_INTEGER
175 #define TARGET_ASM_INTEGER pdp11_assemble_integer
177 #undef TARGET_ASM_OPEN_PAREN
178 #define TARGET_ASM_OPEN_PAREN "["
179 #undef TARGET_ASM_CLOSE_PAREN
180 #define TARGET_ASM_CLOSE_PAREN "]"
182 #undef TARGET_RTX_COSTS
183 #define TARGET_RTX_COSTS pdp11_rtx_costs
185 #undef TARGET_FUNCTION_ARG
186 #define TARGET_FUNCTION_ARG pdp11_function_arg
187 #undef TARGET_FUNCTION_ARG_ADVANCE
188 #define TARGET_FUNCTION_ARG_ADVANCE pdp11_function_arg_advance
190 #undef TARGET_RETURN_IN_MEMORY
191 #define TARGET_RETURN_IN_MEMORY pdp11_return_in_memory
193 #undef TARGET_FUNCTION_VALUE
194 #define TARGET_FUNCTION_VALUE pdp11_function_value
195 #undef TARGET_LIBCALL_VALUE
196 #define TARGET_LIBCALL_VALUE pdp11_libcall_value
197 #undef TARGET_FUNCTION_VALUE_REGNO_P
198 #define TARGET_FUNCTION_VALUE_REGNO_P pdp11_function_value_regno_p
200 #undef TARGET_TRAMPOLINE_INIT
201 #define TARGET_TRAMPOLINE_INIT pdp11_trampoline_init
203 #undef TARGET_SECONDARY_RELOAD
204 #define TARGET_SECONDARY_RELOAD pdp11_secondary_reload
206 #undef TARGET_REGISTER_MOVE_COST
207 #define TARGET_REGISTER_MOVE_COST pdp11_register_move_cost
209 #undef TARGET_PREFERRED_RELOAD_CLASS
210 #define TARGET_PREFERRED_RELOAD_CLASS pdp11_preferred_reload_class
212 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
213 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS pdp11_preferred_output_reload_class
216 #define TARGET_LRA_P hook_bool_void_false
218 #undef TARGET_LEGITIMATE_ADDRESS_P
219 #define TARGET_LEGITIMATE_ADDRESS_P pdp11_legitimate_address_p
221 #undef TARGET_CONDITIONAL_REGISTER_USAGE
222 #define TARGET_CONDITIONAL_REGISTER_USAGE pdp11_conditional_register_usage
224 #undef TARGET_OPTION_OVERRIDE
225 #define TARGET_OPTION_OVERRIDE pdp11_option_override
227 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
228 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
230 #undef TARGET_ASM_OUTPUT_IDENT
231 #define TARGET_ASM_OUTPUT_IDENT pdp11_output_ident
233 #undef TARGET_ASM_FUNCTION_SECTION
234 #define TARGET_ASM_FUNCTION_SECTION pdp11_function_section
236 #undef TARGET_ASM_NAMED_SECTION
237 #define TARGET_ASM_NAMED_SECTION pdp11_asm_named_section
239 #undef TARGET_ASM_INIT_SECTIONS
240 #define TARGET_ASM_INIT_SECTIONS pdp11_asm_init_sections
242 #undef TARGET_ASM_FILE_START
243 #define TARGET_ASM_FILE_START pdp11_file_start
245 #undef TARGET_ASM_FILE_END
246 #define TARGET_ASM_FILE_END pdp11_file_end
248 #undef TARGET_PRINT_OPERAND
249 #define TARGET_PRINT_OPERAND pdp11_asm_print_operand
251 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
252 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P pdp11_asm_print_operand_punct_valid_p
254 #undef TARGET_LEGITIMATE_CONSTANT_P
255 #define TARGET_LEGITIMATE_CONSTANT_P pdp11_legitimate_constant_p
257 #undef TARGET_SCALAR_MODE_SUPPORTED_P
258 #define TARGET_SCALAR_MODE_SUPPORTED_P pdp11_scalar_mode_supported_p
260 #undef TARGET_HARD_REGNO_NREGS
261 #define TARGET_HARD_REGNO_NREGS pdp11_hard_regno_nregs
263 #undef TARGET_HARD_REGNO_MODE_OK
264 #define TARGET_HARD_REGNO_MODE_OK pdp11_hard_regno_mode_ok
266 #undef TARGET_MODES_TIEABLE_P
267 #define TARGET_MODES_TIEABLE_P pdp11_modes_tieable_p
269 #undef TARGET_SECONDARY_MEMORY_NEEDED
270 #define TARGET_SECONDARY_MEMORY_NEEDED pdp11_secondary_memory_needed
272 #undef TARGET_CAN_CHANGE_MODE_CLASS
273 #define TARGET_CAN_CHANGE_MODE_CLASS pdp11_can_change_mode_class
275 /* A helper function to determine if REGNO should be saved in the
276 current function's stack frame. */
279 pdp11_saved_regno (unsigned regno
)
281 return !call_used_regs
[regno
] && df_regs_ever_live_p (regno
);
284 /* Expand the function prologue. */
287 pdp11_expand_prologue (void)
289 HOST_WIDE_INT fsize
= get_frame_size ();
291 rtx x
, via_ac
= NULL
;
293 /* If we are outputting code for main, the switch FPU to the
294 right mode if TARGET_FPU. */
295 if (MAIN_NAME_P (DECL_NAME (current_function_decl
)) && TARGET_FPU
)
297 emit_insn (gen_setd ());
298 emit_insn (gen_seti ());
301 if (frame_pointer_needed
)
303 x
= gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
);
304 x
= gen_frame_mem (Pmode
, x
);
305 emit_move_insn (x
, hard_frame_pointer_rtx
);
307 emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
313 emit_insn (gen_addhi3 (stack_pointer_rtx
, stack_pointer_rtx
,
316 /* Prevent frame references via the frame pointer from being
317 scheduled before the frame is allocated. */
318 if (frame_pointer_needed
)
319 emit_insn (gen_blockage ());
322 /* Save CPU registers. */
323 for (regno
= R0_REGNUM
; regno
<= PC_REGNUM
; regno
++)
324 if (pdp11_saved_regno (regno
)
325 && (regno
!= HARD_FRAME_POINTER_REGNUM
|| !frame_pointer_needed
))
327 x
= gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
);
328 x
= gen_frame_mem (Pmode
, x
);
329 emit_move_insn (x
, gen_rtx_REG (Pmode
, regno
));
332 /* Save FPU registers. */
333 for (regno
= AC0_REGNUM
; regno
<= AC3_REGNUM
; regno
++)
334 if (pdp11_saved_regno (regno
))
336 x
= gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
);
337 x
= gen_frame_mem (DFmode
, x
);
338 via_ac
= gen_rtx_REG (DFmode
, regno
);
339 emit_move_insn (x
, via_ac
);
342 /* ??? Maybe make ac4, ac5 call used regs?? */
343 for (regno
= AC4_REGNUM
; regno
<= AC5_REGNUM
; regno
++)
344 if (pdp11_saved_regno (regno
))
346 gcc_assert (via_ac
!= NULL
);
347 emit_move_insn (via_ac
, gen_rtx_REG (DFmode
, regno
));
349 x
= gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
);
350 x
= gen_frame_mem (DFmode
, x
);
351 emit_move_insn (x
, via_ac
);
355 /* The function epilogue should not depend on the current stack pointer!
356 It should use the frame pointer only. This is mandatory because
357 of alloca; we also take advantage of it to omit stack adjustments
360 /* Maybe we can make leaf functions faster by switching to the
361 second register file - this way we don't have to save regs!
362 leaf functions are ~ 50% of all functions (dynamically!)
364 set/clear bit 11 (dec. 2048) of status word for switching register files -
365 but how can we do this? the pdp11/45 manual says bit may only
366 be set (p.24), but not cleared!
368 switching to kernel is probably more expensive, so we'll leave it
369 like this and not use the second set of registers...
371 maybe as option if you want to generate code for kernel mode? */
374 pdp11_expand_epilogue (void)
376 HOST_WIDE_INT fsize
= get_frame_size ();
378 rtx x
, reg
, via_ac
= NULL
;
380 if (pdp11_saved_regno (AC4_REGNUM
) || pdp11_saved_regno (AC5_REGNUM
))
382 /* Find a temporary with which to restore AC4/5. */
383 for (regno
= AC0_REGNUM
; regno
<= AC3_REGNUM
; regno
++)
384 if (pdp11_saved_regno (regno
))
386 via_ac
= gen_rtx_REG (DFmode
, regno
);
391 /* If possible, restore registers via pops. */
392 if (!frame_pointer_needed
|| crtl
->sp_is_unchanging
)
394 /* Restore registers via pops. */
396 for (regno
= AC5_REGNUM
; regno
>= AC0_REGNUM
; regno
--)
397 if (pdp11_saved_regno (regno
))
399 x
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
400 x
= gen_frame_mem (DFmode
, x
);
401 reg
= gen_rtx_REG (DFmode
, regno
);
403 if (LOAD_FPU_REG_P (regno
))
404 emit_move_insn (reg
, x
);
407 emit_move_insn (via_ac
, x
);
408 emit_move_insn (reg
, via_ac
);
412 for (regno
= PC_REGNUM
; regno
>= R0_REGNUM
+ 2; regno
--)
413 if (pdp11_saved_regno (regno
)
414 && (regno
!= HARD_FRAME_POINTER_REGNUM
|| !frame_pointer_needed
))
416 x
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
417 x
= gen_frame_mem (Pmode
, x
);
418 emit_move_insn (gen_rtx_REG (Pmode
, regno
), x
);
423 /* Restore registers via moves. */
424 /* ??? If more than a few registers need to be restored, it's smaller
425 to generate a pointer through which we can emit pops. Consider
426 that moves cost 2*NREG words and pops cost NREG+3 words. This
427 means that the crossover is NREG=3.
429 Possible registers to use are:
430 (1) The first call-saved general register. This register will
431 be restored with the last pop.
432 (2) R1, if it's not used as a return register.
433 (3) FP itself. This option may result in +4 words, since we
434 may need two add imm,rn instructions instead of just one.
435 This also has the downside that we're not representing
436 the unwind info in any way, so during the epilogue the
437 debugger may get lost. */
439 HOST_WIDE_INT ofs
= -pdp11_sp_frame_offset ();
441 for (regno
= AC5_REGNUM
; regno
>= AC0_REGNUM
; regno
--)
442 if (pdp11_saved_regno (regno
))
444 x
= plus_constant (Pmode
, hard_frame_pointer_rtx
, ofs
);
445 x
= gen_frame_mem (DFmode
, x
);
446 reg
= gen_rtx_REG (DFmode
, regno
);
448 if (LOAD_FPU_REG_P (regno
))
449 emit_move_insn (reg
, x
);
452 emit_move_insn (via_ac
, x
);
453 emit_move_insn (reg
, via_ac
);
458 for (regno
= PC_REGNUM
; regno
>= R0_REGNUM
+ 2; regno
--)
459 if (pdp11_saved_regno (regno
)
460 && (regno
!= HARD_FRAME_POINTER_REGNUM
|| !frame_pointer_needed
))
462 x
= plus_constant (Pmode
, hard_frame_pointer_rtx
, ofs
);
463 x
= gen_frame_mem (Pmode
, x
);
464 emit_move_insn (gen_rtx_REG (Pmode
, regno
), x
);
469 /* Deallocate the stack frame. */
472 /* Prevent frame references via any pointer from being
473 scheduled after the frame is deallocated. */
474 emit_insn (gen_blockage ());
476 if (frame_pointer_needed
)
478 /* We can deallocate the frame with a single move. */
479 emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
482 emit_insn (gen_addhi3 (stack_pointer_rtx
, stack_pointer_rtx
,
486 if (frame_pointer_needed
)
488 x
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
489 x
= gen_frame_mem (Pmode
, x
);
490 emit_move_insn (hard_frame_pointer_rtx
, x
);
493 emit_jump_insn (gen_return ());
496 /* Return the best assembler insn template
497 for moving operands[1] into operands[0] as a fullword. */
499 singlemove_string (rtx
*operands
)
501 if (operands
[1] != const0_rtx
)
508 /* Expand multi-word operands (SImode or DImode) into the 2 or 4
509 corresponding HImode operands. The number of operands is given
510 as the third argument, and the required order of the parts as
511 the fourth argument. */
513 pdp11_expand_operands (rtx
*operands
, rtx exops
[][2], int opcount
,
514 pdp11_action
*action
, pdp11_partorder order
)
516 int words
, op
, w
, i
, sh
;
517 pdp11_partorder useorder
;
518 bool sameoff
= false;
519 enum { REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
} optype
;
522 words
= GET_MODE_BITSIZE (GET_MODE (operands
[0])) / 16;
524 /* If either piece order is accepted and one is pre-decrement
525 while the other is post-increment, set order to be high order
526 word first. That will force the pre-decrement to be turned
527 into a pointer adjust, then offset addressing.
528 Otherwise, if either operand uses pre-decrement, that means
529 the order is low order first.
530 Otherwise, if both operands are registers and destination is
531 higher than source and they overlap, do low order word (highest
532 register number) first. */
536 if (!REG_P (operands
[0]) && !REG_P (operands
[1]) &&
537 !(CONSTANT_P (operands
[1]) ||
538 GET_CODE (operands
[1]) == CONST_DOUBLE
) &&
539 ((GET_CODE (XEXP (operands
[0], 0)) == POST_INC
&&
540 GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
) ||
541 (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
&&
542 GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)))
544 else if ((!REG_P (operands
[0]) &&
545 GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
) ||
546 (!REG_P (operands
[1]) &&
547 !(CONSTANT_P (operands
[1]) ||
548 GET_CODE (operands
[1]) == CONST_DOUBLE
) &&
549 GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
))
551 else if (REG_P (operands
[0]) && REG_P (operands
[1]) &&
552 REGNO (operands
[0]) > REGNO (operands
[1]) &&
553 REGNO (operands
[0]) < REGNO (operands
[1]) + words
)
556 /* Check for source == offset from register and dest == push of
557 the same register. In that case, we have to use the same
558 offset (the one for the low order word) for all words, because
559 the push increases the offset to each source word.
560 In theory there are other cases like this, for example dest == pop,
561 but those don't occur in real life so ignore those. */
562 if (GET_CODE (operands
[0]) == MEM
563 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
564 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
565 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
569 /* If the caller didn't specify order, use the one we computed,
570 or high word first if we don't care either. If the caller did
571 specify, verify we don't have a problem with that order.
572 (If it matters to the caller, constraints need to be used to
573 ensure this case doesn't occur). */
575 order
= (useorder
== either
) ? big
: useorder
;
577 gcc_assert (useorder
== either
|| useorder
== order
);
580 for (op
= 0; op
< opcount
; op
++)
582 /* First classify the operand. */
583 if (REG_P (operands
[op
]))
585 else if (CONSTANT_P (operands
[op
])
586 || GET_CODE (operands
[op
]) == CONST_DOUBLE
)
588 else if (GET_CODE (XEXP (operands
[op
], 0)) == POST_INC
)
590 else if (GET_CODE (XEXP (operands
[op
], 0)) == PRE_DEC
)
592 else if (!reload_in_progress
|| offsettable_memref_p (operands
[op
]))
594 else if (GET_CODE (operands
[op
]) == MEM
)
599 /* Check for the cases that the operand constraints are not
600 supposed to allow to happen. Return failure for such cases. */
605 action
[op
] = no_action
;
607 /* If the operand uses pre-decrement addressing but we
608 want to get the parts high order first,
609 decrement the former register explicitly
610 and change the operand into ordinary indexing. */
611 if (optype
== PUSHOP
&& order
== big
)
613 gcc_assert (action
!= NULL
);
614 action
[op
] = dec_before
;
615 operands
[op
] = gen_rtx_MEM (GET_MODE (operands
[op
]),
616 XEXP (XEXP (operands
[op
], 0), 0));
619 /* If the operand uses post-increment mode but we want
620 to get the parts low order first, change the operand
621 into ordinary indexing and remember to increment
622 the register explicitly when we're done. */
623 else if (optype
== POPOP
&& order
== little
)
625 gcc_assert (action
!= NULL
);
626 action
[op
] = inc_after
;
627 operands
[op
] = gen_rtx_MEM (GET_MODE (operands
[op
]),
628 XEXP (XEXP (operands
[op
], 0), 0));
632 if (GET_CODE (operands
[op
]) == CONST_DOUBLE
)
633 REAL_VALUE_TO_TARGET_DOUBLE
634 (*CONST_DOUBLE_REAL_VALUE (operands
[op
]), sval
);
636 for (i
= 0; i
< words
; i
++)
645 /* Set the output operand to be word "w" of the input. */
647 exops
[i
][op
] = gen_rtx_REG (HImode
, REGNO (operands
[op
]) + w
);
648 else if (optype
== OFFSOP
)
649 exops
[i
][op
] = adjust_address (operands
[op
], HImode
, w
* 2);
650 else if (optype
== CNSTOP
)
652 if (GET_CODE (operands
[op
]) == CONST_DOUBLE
)
654 sh
= 16 - (w
& 1) * 16;
655 exops
[i
][op
] = gen_rtx_CONST_INT (HImode
, (sval
[w
/ 2] >> sh
) & 0xffff);
659 sh
= ((words
- 1 - w
) * 16);
660 exops
[i
][op
] = gen_rtx_CONST_INT (HImode
, trunc_int_for_mode (INTVAL(operands
[op
]) >> sh
, HImode
));
664 exops
[i
][op
] = operands
[op
];
670 /* Output assembler code to perform a multiple-word move insn
671 with operands OPERANDS. This moves 2 or 4 words depending
672 on the machine mode of the operands. */
675 output_move_multiple (rtx
*operands
)
678 pdp11_action action
[2];
681 words
= GET_MODE_BITSIZE (GET_MODE (operands
[0])) / 16;
683 pdp11_expand_operands (operands
, exops
, 2, action
, either
);
685 /* Check for explicit decrement before. */
686 if (action
[0] == dec_before
)
688 operands
[0] = XEXP (operands
[0], 0);
689 output_asm_insn ("sub\t%#4,%0", operands
);
691 if (action
[1] == dec_before
)
693 operands
[1] = XEXP (operands
[1], 0);
694 output_asm_insn ("sub\t%#4,%1", operands
);
698 for (i
= 0; i
< words
; i
++)
699 output_asm_insn (singlemove_string (exops
[i
]), exops
[i
]);
701 /* Check for increment after. */
702 if (action
[0] == inc_after
)
704 operands
[0] = XEXP (operands
[0], 0);
705 output_asm_insn ("add\t%#4,%0", operands
);
707 if (action
[1] == inc_after
)
709 operands
[1] = XEXP (operands
[1], 0);
710 output_asm_insn ("add\t%#4,%1", operands
);
716 /* Build an internal label. */
718 pdp11_gen_int_label (char *label
, const char *prefix
, int num
)
721 /* +1 because GCC numbers labels starting at zero. */
722 sprintf (label
, "*%lu$", num
+ 1);
724 sprintf (label
, "*%s_%lu", prefix
, num
);
727 /* Output an ascii string. */
729 output_ascii (FILE *file
, const char *p
, int size
)
732 const char *pseudo
= "\t.ascii\t";
737 if (p
[size
- 1] == '\0')
739 pseudo
= "\t.asciz\t";
742 fputs (pseudo
, file
);
743 for (i
= 0; i
< size
; i
++)
746 if (c
< 32 || c
== '"' || c
> 126)
750 fprintf (file
, "<%o%>", c
);
767 fprintf (file
, "\t.byte ");
769 for (i
= 0; i
< size
; i
++)
771 fprintf (file
, "%#o", *p
++ & 0xff);
780 pdp11_asm_output_var (FILE *file
, const char *name
, int size
,
781 int align
, bool global
)
784 fprintf (file
, "\t.even\n");
787 fprintf (file
, ".globl ");
788 assemble_name (file
, name
);
790 fprintf (file
, "\n");
791 assemble_name (file
, name
);
793 ASM_OUTPUT_SKIP (file
, size
);
796 /* Special format operators handled here:
797 # -- output the correct immediate operand marker for the assembler
799 @ -- output the correct indirect marker for the assembler dialect.
800 o -- emit a constant value as a number (not an immediate operand)
803 pdp11_asm_print_operand (FILE *file
, rtx x
, int code
)
814 else if (code
== '@')
821 else if (GET_CODE (x
) == REG
)
822 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
823 else if (GET_CODE (x
) == MEM
)
824 output_address (GET_MODE (x
), XEXP (x
, 0));
825 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) != SImode
)
827 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x
), sval
);
829 fprintf (file
, "#%lo", (sval
[0] >> 16) & 0xffff);
831 fprintf (file
, "$%#lo", (sval
[0] >> 16) & 0xffff);
842 output_addr_const_pdp11 (file
, x
);
847 pdp11_asm_print_operand_punct_valid_p (unsigned char c
)
849 return (c
== '#' || c
== '@');
853 print_operand_address (FILE *file
, register rtx addr
)
861 switch (GET_CODE (addr
))
868 addr
= XEXP (addr
, 0);
873 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
878 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
883 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
889 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0))
890 || GET_CODE (XEXP (addr
, 0)) == MEM
)
892 offset
= XEXP (addr
, 0);
893 addr
= XEXP (addr
, 1);
895 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1))
896 || GET_CODE (XEXP (addr
, 1)) == MEM
)
898 offset
= XEXP (addr
, 1);
899 addr
= XEXP (addr
, 0);
901 if (GET_CODE (addr
) != PLUS
)
903 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
905 breg
= XEXP (addr
, 0);
906 addr
= XEXP (addr
, 1);
908 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
910 breg
= XEXP (addr
, 1);
911 addr
= XEXP (addr
, 0);
913 if (GET_CODE (addr
) == REG
)
915 gcc_assert (breg
== 0);
921 gcc_assert (addr
== 0);
925 output_addr_const_pdp11 (file
, addr
);
928 gcc_assert (GET_CODE (breg
) == REG
);
929 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
934 if (!again
&& GET_CODE (addr
) == CONST_INT
)
936 /* Absolute (integer number) address. */
938 fprintf (file
, "@#");
939 else if (!TARGET_UNIX_ASM
)
940 fprintf (file
, "@$");
942 output_addr_const_pdp11 (file
, addr
);
946 /* Target hook to assemble integer objects. We need to use the
947 pdp-specific version of output_addr_const. */
950 pdp11_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
956 fprintf (asm_out_file
, "\t.byte\t");
957 output_addr_const_pdp11 (asm_out_file
, GEN_INT (INTVAL (x
) & 0xff));
958 fputs ("\n", asm_out_file
);
962 fprintf (asm_out_file
, TARGET_UNIX_ASM
? "\t" : "\t.word\t");
963 output_addr_const_pdp11 (asm_out_file
, x
);
964 fputs ("\n", asm_out_file
);
967 return default_assemble_integer (x
, size
, aligned_p
);
971 /* Register to register moves are cheap if both are general registers.
972 The same is true for FPU, but there we return cost of 3 rather than
973 2 to make reload look at the constraints. The raeson is that
974 load/store double require extra care since load touches condition
975 codes and store doesn't, which is (partly anyway) described by
978 pdp11_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
979 reg_class_t c1
, reg_class_t c2
)
981 if (((c1
== MUL_REGS
|| c1
== GENERAL_REGS
) &&
982 (c2
== MUL_REGS
|| c2
== GENERAL_REGS
)))
984 else if ((c1
>= LOAD_FPU_REGS
&& c1
<= FPU_REGS
&& c2
== LOAD_FPU_REGS
) ||
985 (c2
>= LOAD_FPU_REGS
&& c2
<= FPU_REGS
&& c1
== LOAD_FPU_REGS
))
993 pdp11_rtx_costs (rtx x
, machine_mode mode
, int outer_code ATTRIBUTE_UNUSED
,
994 int opno ATTRIBUTE_UNUSED
, int *total
,
995 bool speed ATTRIBUTE_UNUSED
)
997 int code
= GET_CODE (x
);
1002 if (INTVAL (x
) == 0 || INTVAL (x
) == -1 || INTVAL (x
) == 1)
1012 /* Twice as expensive as REG. */
1017 /* Twice (or 4 times) as expensive as 16 bit. */
1022 /* ??? There is something wrong in MULT because MULT is not
1023 as cheap as total = 2 even if we can shift! */
1024 /* If optimizing for size make mult etc cheap, but not 1, so when
1025 in doubt the faster insn is chosen. */
1027 *total
= COSTS_N_INSNS (2);
1029 *total
= COSTS_N_INSNS (11);
1034 *total
= COSTS_N_INSNS (2);
1036 *total
= COSTS_N_INSNS (25);
1041 *total
= COSTS_N_INSNS (2);
1043 *total
= COSTS_N_INSNS (26);
1047 /* Equivalent to length, so same for optimize_size. */
1048 *total
= COSTS_N_INSNS (3);
1052 /* Only used for qi->hi. */
1053 *total
= COSTS_N_INSNS (1);
1058 *total
= COSTS_N_INSNS (1);
1059 else if (mode
== SImode
)
1060 *total
= COSTS_N_INSNS (6);
1062 *total
= COSTS_N_INSNS (2);
1068 *total
= COSTS_N_INSNS (1);
1069 else if (mode
== QImode
)
1071 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
1072 *total
= COSTS_N_INSNS (8); /* worst case */
1074 *total
= COSTS_N_INSNS (INTVAL (XEXP (x
, 1)));
1076 else if (mode
== HImode
)
1078 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1080 if (abs (INTVAL (XEXP (x
, 1))) == 1)
1081 *total
= COSTS_N_INSNS (1);
1083 *total
= COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x
, 1)));
1086 *total
= COSTS_N_INSNS (10); /* worst case */
1088 else if (mode
== SImode
)
1090 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1091 *total
= COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x
, 1)));
1092 else /* worst case */
1093 *total
= COSTS_N_INSNS (18);
1099 *total
= COSTS_N_INSNS (2);
1100 else if (mode
== QImode
)
1102 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
1103 *total
= COSTS_N_INSNS (12); /* worst case */
1105 *total
= COSTS_N_INSNS (1 + INTVAL (XEXP (x
, 1)));
1107 else if (mode
== HImode
)
1109 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1111 if (abs (INTVAL (XEXP (x
, 1))) == 1)
1112 *total
= COSTS_N_INSNS (2);
1114 *total
= COSTS_N_INSNS (3.5 + 0.5 * INTVAL (XEXP (x
, 1)));
1117 *total
= COSTS_N_INSNS (12); /* worst case */
1119 else if (mode
== SImode
)
1121 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1122 *total
= COSTS_N_INSNS (3.5 + 0.5 * INTVAL (XEXP (x
, 1)));
1123 else /* worst case */
1124 *total
= COSTS_N_INSNS (20);
1134 output_jump (rtx
*operands
, int ccnz
, int length
)
1137 static char buf
[100];
1138 const char *pos
, *neg
;
1139 enum rtx_code code
= GET_CODE (operands
[0]);
1143 /* These are the branches valid for CCNZmode, i.e., a comparison
1144 with zero where the V bit is not set to zero. These cases
1145 occur when CC or FCC are set as a side effect of some data
1146 manipulation, such as the ADD instruction. */
1149 case EQ
: pos
= "beq", neg
= "bne"; break;
1150 case NE
: pos
= "bne", neg
= "beq"; break;
1151 case LT
: pos
= "bmi", neg
= "bpl"; break;
1152 case GE
: pos
= "bpl", neg
= "bmi"; break;
1153 default: gcc_unreachable ();
1160 case EQ
: pos
= "beq", neg
= "bne"; break;
1161 case NE
: pos
= "bne", neg
= "beq"; break;
1162 case GT
: pos
= "bgt", neg
= "ble"; break;
1163 case GTU
: pos
= "bhi", neg
= "blos"; break;
1164 case LT
: pos
= "blt", neg
= "bge"; break;
1165 case LTU
: pos
= "blo", neg
= "bhis"; break;
1166 case GE
: pos
= "bge", neg
= "blt"; break;
1167 case GEU
: pos
= "bhis", neg
= "blo"; break;
1168 case LE
: pos
= "ble", neg
= "bgt"; break;
1169 case LEU
: pos
= "blos", neg
= "bhi"; break;
1170 default: gcc_unreachable ();
1176 sprintf (buf
, "%s\t%%l1", pos
);
1179 tmpop
[0] = gen_label_rtx ();
1180 sprintf (buf
, "%s\t%%l0", neg
);
1181 output_asm_insn (buf
, tmpop
);
1182 output_asm_insn ("jmp\t%l1", operands
);
1183 output_asm_label (tmpop
[0]);
1184 fputs (":\n", asm_out_file
);
1191 /* Select the CC mode to be used for the side effect compare with
1192 zero, given the compare operation code in op and the compare
1193 operands in x in and y. */
1195 pdp11_cc_mode (enum rtx_code op
, rtx x
, rtx y
)
1197 if (FLOAT_MODE_P (GET_MODE (x
)))
1199 switch (GET_CODE (x
))
1212 switch (GET_CODE (x
))
1230 simple_memory_operand(rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
1234 /* Eliminate non-memory operations */
1235 if (GET_CODE (op
) != MEM
)
1238 /* Decode the address now. */
1242 addr
= XEXP (op
, 0);
1244 switch (GET_CODE (addr
))
1247 /* (R0) - no extra cost */
1254 /* -(R0), (R0)+ - cheap! */
1258 /* cheap - is encoded in addressing mode info!
1260 -- except for @(R0), which has to be @0(R0) !!! */
1262 if (GET_CODE (XEXP (addr
, 0)) == REG
)
1272 /* @#address - extra cost */
1276 /* X(R0) - extra cost */
1286 /* Similar to simple_memory_operand but doesn't match push/pop. */
1288 no_side_effect_operand(rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
1292 /* Eliminate non-memory operations */
1293 if (GET_CODE (op
) != MEM
)
1296 /* Decode the address now. */
1300 addr
= XEXP (op
, 0);
1302 switch (GET_CODE (addr
))
1305 /* (R0) - no extra cost */
1315 /* cheap - is encoded in addressing mode info!
1317 -- except for @(R0), which has to be @0(R0) !!! */
1319 if (GET_CODE (XEXP (addr
, 0)) == REG
)
1329 /* @#address - extra cost */
1333 /* X(R0) - extra cost */
1345 * output a block move:
1347 * operands[0] ... to
1348 * operands[1] ... from
1349 * operands[2] ... length
1350 * operands[3] ... alignment
1351 * operands[4] ... scratch register
1356 output_block_move(rtx
*operands
)
1358 static int count
= 0;
1363 /* Move of zero bytes is a NOP. */
1364 if (operands
[2] == const0_rtx
)
1367 /* Look for moves by small constant byte counts, those we'll
1368 expand to straight line code. */
1369 if (CONSTANT_P (operands
[2]))
1371 if (INTVAL (operands
[2]) < 16
1372 && (!optimize_size
|| INTVAL (operands
[2]) < 5)
1373 && INTVAL (operands
[3]) == 1)
1377 for (i
= 1; i
<= INTVAL (operands
[2]); i
++)
1378 output_asm_insn("movb\t(%1)+,(%0)+", operands
);
1382 else if (INTVAL(operands
[2]) < 32
1383 && (!optimize_size
|| INTVAL (operands
[2]) < 9)
1384 && INTVAL (operands
[3]) >= 2)
1388 for (i
= 1; i
<= INTVAL (operands
[2]) / 2; i
++)
1389 output_asm_insn ("mov\t(%1)+,(%0)+", operands
);
1390 if (INTVAL (operands
[2]) & 1)
1391 output_asm_insn ("movb\t(%1),(%0)", operands
);
1397 /* Ideally we'd look for moves that are multiples of 4 or 8
1398 bytes and handle those by unrolling the move loop. That
1399 makes for a lot of code if done at run time, but it's ok
1400 for constant counts. Also, for variable counts we have
1401 to worry about odd byte count with even aligned pointers.
1402 On 11/40 and up we handle that case; on older machines
1403 we don't and just use byte-wise moves all the time. */
1405 if (CONSTANT_P (operands
[2]) )
1407 if (INTVAL (operands
[3]) < 2)
1411 lastbyte
= INTVAL (operands
[2]) & 1;
1413 if (optimize_size
|| INTVAL (operands
[2]) & 2)
1415 else if (INTVAL (operands
[2]) & 4)
1421 /* Loop count is byte count scaled by unroll. */
1422 operands
[2] = GEN_INT (INTVAL (operands
[2]) >> unroll
);
1423 output_asm_insn ("mov\t%2,%4", operands
);
1427 /* Variable byte count; use the input register
1429 operands
[4] = operands
[2];
1431 /* Decide whether to move by words, and check
1432 the byte count for zero. */
1433 if (TARGET_40_PLUS
&& INTVAL (operands
[3]) > 1)
1436 output_asm_insn ("asr\t%4", operands
);
1441 output_asm_insn ("tst\t%4", operands
);
1443 sprintf (buf
, "beq movestrhi%d", count
+ 1);
1444 output_asm_insn (buf
, NULL
);
1447 /* Output the loop label. */
1448 sprintf (buf
, "\nmovestrhi%d:", count
);
1449 output_asm_insn (buf
, NULL
);
1451 /* Output the appropriate move instructions. */
1455 output_asm_insn ("movb\t(%1)+,(%0)+", operands
);
1459 output_asm_insn ("mov\t(%1)+,(%0)+", operands
);
1463 output_asm_insn ("mov\t(%1)+,(%0)+", operands
);
1464 output_asm_insn ("mov\t(%1)+,(%0)+", operands
);
1468 output_asm_insn ("mov\t(%1)+,(%0)+", operands
);
1469 output_asm_insn ("mov\t(%1)+,(%0)+", operands
);
1470 output_asm_insn ("mov\t(%1)+,(%0)+", operands
);
1471 output_asm_insn ("mov\t(%1)+,(%0)+", operands
);
1475 /* Output the decrement and test. */
1478 sprintf (buf
, "sob\t%%4, movestrhi%d", count
);
1479 output_asm_insn (buf
, operands
);
1483 output_asm_insn ("dec\t%4", operands
);
1484 sprintf (buf
, "bgt movestrhi%d", count
);
1485 output_asm_insn (buf
, NULL
);
1489 /* If constant odd byte count, move the last byte. */
1491 output_asm_insn ("movb\t(%1),(%0)", operands
);
1492 else if (!CONSTANT_P (operands
[2]))
1494 /* Output the destination label for the zero byte count check. */
1495 sprintf (buf
, "\nmovestrhi%d:", count
);
1496 output_asm_insn (buf
, NULL
);
1499 /* If we did word moves, check for trailing last byte. */
1502 sprintf (buf
, "bcc movestrhi%d", count
);
1503 output_asm_insn (buf
, NULL
);
1504 output_asm_insn ("movb\t(%1),(%0)", operands
);
1505 sprintf (buf
, "\nmovestrhi%d:", count
);
1506 output_asm_insn (buf
, NULL
);
1514 /* This function checks whether a real value can be encoded as
1515 a literal, i.e., addressing mode 27. In that mode, real values
1516 are one word values, so the remaining 48 bits have to be zero. */
1518 legitimate_const_double_p (rtx address
)
1521 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (address
), sval
);
1522 if ((sval
[0] & 0xffff) == 0 && sval
[1] == 0)
1527 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
1529 pdp11_can_change_mode_class (machine_mode from
,
1533 /* Also, FPU registers contain a whole float value and the parts of
1534 it are not separately accessible.
1536 So we disallow all mode changes involving FPRs. */
1537 if (FLOAT_MODE_P (from
) != FLOAT_MODE_P (to
))
1540 return !reg_classes_intersect_p (FPU_REGS
, rclass
);
1543 /* TARGET_PREFERRED_RELOAD_CLASS
1545 Given an rtx X being reloaded into a reg required to be
1546 in class CLASS, return the class of reg to actually use.
1547 In general this is just CLASS; but on some machines
1548 in some cases it is preferable to use a more restrictive class.
1550 loading is easier into LOAD_FPU_REGS than FPU_REGS! */
1553 pdp11_preferred_reload_class (rtx x
, reg_class_t rclass
)
1555 if (rclass
== FPU_REGS
)
1556 return LOAD_FPU_REGS
;
1557 if (rclass
== ALL_REGS
)
1559 if (FLOAT_MODE_P (GET_MODE (x
)))
1560 return LOAD_FPU_REGS
;
1562 return GENERAL_REGS
;
1567 /* TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
1569 Given an rtx X being reloaded into a reg required to be
1570 in class CLASS, return the class of reg to actually use.
1571 In general this is just CLASS; but on some machines
1572 in some cases it is preferable to use a more restrictive class.
1574 loading is easier into LOAD_FPU_REGS than FPU_REGS! */
1577 pdp11_preferred_output_reload_class (rtx x
, reg_class_t rclass
)
1579 if (rclass
== FPU_REGS
)
1580 return LOAD_FPU_REGS
;
1581 if (rclass
== ALL_REGS
)
1583 if (FLOAT_MODE_P (GET_MODE (x
)))
1584 return LOAD_FPU_REGS
;
1586 return GENERAL_REGS
;
1592 /* TARGET_SECONDARY_RELOAD.
1594 FPU registers AC4 and AC5 (class NO_LOAD_FPU_REGS) require an
1595 intermediate register (AC0-AC3: LOAD_FPU_REGS). Everything else
1596 can be loaded/stored directly. */
1598 pdp11_secondary_reload (bool in_p ATTRIBUTE_UNUSED
,
1600 reg_class_t reload_class
,
1601 machine_mode reload_mode ATTRIBUTE_UNUSED
,
1602 secondary_reload_info
*sri ATTRIBUTE_UNUSED
)
1604 if (reload_class
!= NO_LOAD_FPU_REGS
|| GET_CODE (x
) != REG
||
1605 REGNO_REG_CLASS (REGNO (x
)) == LOAD_FPU_REGS
)
1608 return LOAD_FPU_REGS
;
1611 /* Implement TARGET_SECONDARY_MEMORY_NEEDED.
1613 The answer is yes if we're going between general register and FPU
1614 registers. The mode doesn't matter in making this check. */
1616 pdp11_secondary_memory_needed (machine_mode
, reg_class_t c1
, reg_class_t c2
)
1618 int fromfloat
= (c1
== LOAD_FPU_REGS
|| c1
== NO_LOAD_FPU_REGS
||
1620 int tofloat
= (c2
== LOAD_FPU_REGS
|| c2
== NO_LOAD_FPU_REGS
||
1623 return (fromfloat
!= tofloat
);
1626 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
1627 that is a valid memory address for an instruction.
1628 The MODE argument is the machine mode for the MEM expression
1629 that wants to use this address.
1634 pdp11_legitimate_address_p (machine_mode mode
,
1635 rtx operand
, bool strict
)
1639 /* accept @#address */
1640 if (CONSTANT_ADDRESS_P (operand
))
1643 switch (GET_CODE (operand
))
1647 return !strict
|| REGNO_OK_FOR_BASE_P (REGNO (operand
));
1651 return GET_CODE (XEXP (operand
, 0)) == REG
1652 && (!strict
|| REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand
, 0))))
1653 && CONSTANT_ADDRESS_P (XEXP (operand
, 1));
1657 return GET_CODE (XEXP (operand
, 0)) == REG
1658 && (!strict
|| REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand
, 0))));
1662 return GET_CODE (XEXP (operand
, 0)) == REG
1663 && (!strict
|| REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand
, 0))));
1666 /* accept -(SP) -- which uses PRE_MODIFY for byte mode */
1667 return GET_CODE (XEXP (operand
, 0)) == REG
1668 && REGNO (XEXP (operand
, 0)) == STACK_POINTER_REGNUM
1669 && GET_CODE ((xfoob
= XEXP (operand
, 1))) == PLUS
1670 && GET_CODE (XEXP (xfoob
, 0)) == REG
1671 && REGNO (XEXP (xfoob
, 0)) == STACK_POINTER_REGNUM
1672 && CONSTANT_P (XEXP (xfoob
, 1))
1673 && INTVAL (XEXP (xfoob
,1)) == -2;
1676 /* accept (SP)+ -- which uses POST_MODIFY for byte mode */
1677 return GET_CODE (XEXP (operand
, 0)) == REG
1678 && REGNO (XEXP (operand
, 0)) == STACK_POINTER_REGNUM
1679 && GET_CODE ((xfoob
= XEXP (operand
, 1))) == PLUS
1680 && GET_CODE (XEXP (xfoob
, 0)) == REG
1681 && REGNO (XEXP (xfoob
, 0)) == STACK_POINTER_REGNUM
1682 && CONSTANT_P (XEXP (xfoob
, 1))
1683 && INTVAL (XEXP (xfoob
,1)) == 2;
1686 /* handle another level of indirection ! */
1687 xfoob
= XEXP (operand
, 0);
1689 /* (MEM:xx (MEM:xx ())) is not valid for SI, DI and currently
1690 also forbidden for float, because we have to handle this
1691 in output_move_double and/or output_move_quad() - we could
1692 do it, but currently it's not worth it!!!
1693 now that DFmode cannot go into CPU register file,
1694 maybe I should allow float ...
1695 but then I have to handle memory-to-memory moves in movdf ?? */
1696 if (GET_MODE_BITSIZE(mode
) > 16)
1699 /* accept @address */
1700 if (CONSTANT_ADDRESS_P (xfoob
))
1703 switch (GET_CODE (xfoob
))
1706 /* accept @(R0) - which is @0(R0) */
1707 return !strict
|| REGNO_OK_FOR_BASE_P(REGNO (xfoob
));
1711 return GET_CODE (XEXP (xfoob
, 0)) == REG
1712 && (!strict
|| REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob
, 0))))
1713 && CONSTANT_ADDRESS_P (XEXP (xfoob
, 1));
1717 return GET_CODE (XEXP (xfoob
, 0)) == REG
1718 && (!strict
|| REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob
, 0))));
1722 return GET_CODE (XEXP (xfoob
, 0)) == REG
1723 && (!strict
|| REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob
, 0))));
1726 /* anything else is invalid */
1731 /* anything else is invalid */
1736 /* Return the class number of the smallest class containing
1737 reg number REGNO. */
1739 pdp11_regno_reg_class (int regno
)
1741 if (regno
== FRAME_POINTER_REGNUM
|| regno
== ARG_POINTER_REGNUM
)
1742 return GENERAL_REGS
;
1743 else if (regno
== CC_REGNUM
|| regno
== FCC_REGNUM
)
1745 else if (regno
> AC3_REGNUM
)
1746 return NO_LOAD_FPU_REGS
;
1747 else if (regno
>= AC0_REGNUM
)
1748 return LOAD_FPU_REGS
;
1752 return GENERAL_REGS
;
1755 /* Return the regnums of the CC registers. */
1757 pdp11_fixed_cc_regs (unsigned int *p1
, unsigned int *p2
)
1765 pdp11_sp_frame_offset (void)
1767 int offset
= 0, regno
;
1768 offset
= get_frame_size();
1769 for (regno
= 0; regno
<= PC_REGNUM
; regno
++)
1770 if (pdp11_saved_regno (regno
))
1772 for (regno
= AC0_REGNUM
; regno
<= AC5_REGNUM
; regno
++)
1773 if (pdp11_saved_regno (regno
))
1779 /* Return the offset between two registers, one to be eliminated, and the other
1780 its replacement, at the start of a routine. */
1783 pdp11_initial_elimination_offset (int from
, int to
)
1787 if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
1789 else if (from
== FRAME_POINTER_REGNUM
1790 && to
== HARD_FRAME_POINTER_REGNUM
)
1794 gcc_assert (to
== STACK_POINTER_REGNUM
);
1796 /* Get the size of the register save area. */
1797 spoff
= pdp11_sp_frame_offset ();
1798 if (from
== FRAME_POINTER_REGNUM
)
1801 gcc_assert (from
== ARG_POINTER_REGNUM
);
1803 /* If there is a frame pointer, that is saved too. */
1804 if (frame_pointer_needed
)
1807 /* Account for the saved PC in the function call. */
1812 /* A copy of output_addr_const modified for pdp11 expression syntax.
1813 output_addr_const also gets called for %cDIGIT and %nDIGIT, which we don't
1814 use, and for debugging output, which we don't support with this port either.
1815 So this copy should get called whenever needed.
1818 output_addr_const_pdp11 (FILE *file
, rtx x
)
1824 switch (GET_CODE (x
))
1827 gcc_assert (flag_pic
);
1832 assemble_name (file
, XSTR (x
, 0));
1836 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (XEXP (x
, 0)));
1837 assemble_name (file
, buf
);
1841 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (x
));
1842 assemble_name (file
, buf
);
1850 fprintf (file
, "-");
1853 fprintf (file
, "%o", i
& 0xffff);
1855 fprintf (file
, "%#o", i
& 0xffff);
1859 output_addr_const_pdp11 (file
, XEXP (x
, 0));
1863 if (GET_MODE (x
) == VOIDmode
)
1865 /* We can use %o if the number is one word and positive. */
1866 gcc_assert (!CONST_DOUBLE_HIGH (x
));
1868 fprintf (file
, "%ho", CONST_DOUBLE_LOW (x
) & 0xffff);
1870 fprintf (file
, "%#ho", CONST_DOUBLE_LOW (x
) & 0xffff);
1873 /* We can't handle floating point constants;
1874 PRINT_OPERAND must handle them. */
1875 output_operand_lossage ("floating constant misused");
1879 /* Some assemblers need integer constants to appear last (e.g. masm). */
1880 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
1882 output_addr_const_pdp11 (file
, XEXP (x
, 1));
1883 if (INTVAL (XEXP (x
, 0)) >= 0)
1884 fprintf (file
, "+");
1885 output_addr_const_pdp11 (file
, XEXP (x
, 0));
1889 output_addr_const_pdp11 (file
, XEXP (x
, 0));
1890 if (INTVAL (XEXP (x
, 1)) >= 0)
1891 fprintf (file
, "+");
1892 output_addr_const_pdp11 (file
, XEXP (x
, 1));
1897 /* Avoid outputting things like x-x or x+5-x,
1898 since some assemblers can't handle that. */
1899 x
= simplify_subtraction (x
);
1900 if (GET_CODE (x
) != MINUS
)
1903 output_addr_const_pdp11 (file
, XEXP (x
, 0));
1904 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
1905 || INTVAL (XEXP (x
, 1)) >= 0)
1906 fprintf (file
, "-");
1907 output_addr_const_pdp11 (file
, XEXP (x
, 1));
1912 output_addr_const_pdp11 (file
, XEXP (x
, 0));
1916 output_operand_lossage ("invalid expression as operand");
1920 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1923 pdp11_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
1925 /* Integers 32 bits and under, and scalar floats (if FPU), are returned
1926 in registers. The rest go into memory. */
1927 return (TYPE_MODE (type
) == DImode
1928 || (FLOAT_MODE_P (TYPE_MODE (type
)) && ! TARGET_AC0
)
1929 || TREE_CODE (type
) == VECTOR_TYPE
1930 || COMPLEX_MODE_P (TYPE_MODE (type
)));
1933 /* Worker function for TARGET_FUNCTION_VALUE.
1935 On the pdp11 the value is found in R0 (or ac0??? not without FPU!!!! ) */
1938 pdp11_function_value (const_tree valtype
,
1939 const_tree fntype_or_decl ATTRIBUTE_UNUSED
,
1940 bool outgoing ATTRIBUTE_UNUSED
)
1942 return gen_rtx_REG (TYPE_MODE (valtype
),
1943 BASE_RETURN_VALUE_REG(TYPE_MODE(valtype
)));
1946 /* Worker function for TARGET_LIBCALL_VALUE. */
1949 pdp11_libcall_value (machine_mode mode
,
1950 const_rtx fun ATTRIBUTE_UNUSED
)
1952 return gen_rtx_REG (mode
, BASE_RETURN_VALUE_REG(mode
));
1955 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
1957 On the pdp, the first "output" reg is the only register thus used.
1959 maybe ac0 ? - as option someday! */
1962 pdp11_function_value_regno_p (const unsigned int regno
)
1964 return (regno
== RETVAL_REGNUM
) || (TARGET_AC0
&& (regno
== AC0_REGNUM
));
1967 /* Used for O constraint, matches if shift count is "small". */
1969 pdp11_small_shift (int n
)
1971 return (unsigned) n
< 4;
1974 /* Expand a shift insn. Returns true if the expansion was done,
1975 false if it needs to be handled by the caller. */
1977 pdp11_expand_shift (rtx
*operands
, rtx (*shift_sc
) (rtx
, rtx
, rtx
),
1978 rtx (*shift_base
) (rtx
, rtx
, rtx
))
1983 if (CONSTANT_P (operands
[2]) && pdp11_small_shift (INTVAL (operands
[2])))
1984 emit_insn ((*shift_sc
) (operands
[0], operands
[1], operands
[2]));
1985 else if (TARGET_40_PLUS
)
1989 lb
= gen_label_rtx ();
1990 r
= gen_reg_rtx (HImode
);
1991 emit_move_insn (operands
[0], operands
[1]);
1992 emit_move_insn (r
, operands
[2]);
1993 if (!CONSTANT_P (operands
[2]))
1995 test
= gen_rtx_LE (HImode
, r
, const0_rtx
);
1996 emit_jump_insn (gen_cbranchhi4 (test
, r
, const0_rtx
, lb
));
1998 /* It would be nice to expand the loop here, but that's not
1999 possible because shifts may be generated by the loop unroll
2000 optimizer and it doesn't appreciate flow changes happening
2001 while it's doing things. */
2002 emit_insn ((*shift_base
) (operands
[0], operands
[1], r
));
2003 if (!CONSTANT_P (operands
[2]))
2007 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2008 fields, and can't be used for REG_NOTES anyway). */
2009 emit_use (stack_pointer_rtx
);
2015 /* Emit the instructions needed to produce a shift by a small constant
2016 amount (unrolled), or a shift made from a loop for the base machine
2019 pdp11_assemble_shift (rtx
*operands
, machine_mode m
, int code
)
2024 pdp11_action action
[2];
2025 const bool small
= CONSTANT_P (operands
[2]) && pdp11_small_shift (INTVAL (operands
[2]));
2027 gcc_assert (small
|| !TARGET_40_PLUS
);
2030 pdp11_expand_operands (operands
, exops
, 1, action
, either
);
2034 /* Loop case, generate the top of loop label. */
2035 lb
[0] = gen_label_rtx ();
2036 output_asm_label (lb
[0]);
2037 fputs (":\n", asm_out_file
);
2041 n
= INTVAL (operands
[2]);
2042 if (code
== LSHIFTRT
)
2044 output_asm_insn ("clc", NULL
);
2048 output_asm_insn ("rorb\t%0", operands
);
2051 output_asm_insn ("ror\t%0", operands
);
2054 output_asm_insn ("ror\t%0", exops
[0]);
2055 output_asm_insn ("ror\t%0", exops
[1]);
2062 for (i
= 0; i
< n
; i
++)
2071 output_asm_insn ("asrb\t%0", operands
);
2074 output_asm_insn ("asr\t%0", operands
);
2077 output_asm_insn ("asr\t%0", exops
[0]);
2078 output_asm_insn ("ror\t%0", exops
[1]);
2088 output_asm_insn ("aslb\t%0", operands
);
2091 output_asm_insn ("asl\t%0", operands
);
2094 output_asm_insn ("asl\t%0", exops
[1]);
2095 output_asm_insn ("rol\t%0", exops
[0]);
2105 /* Loop case, emit the count-down and branch if not done. */
2106 output_asm_insn ("dec\t%2", operands
);
2107 output_asm_insn ("bne\t%l0", lb
);
2112 /* Figure out the length of the instructions that will be produced for
2113 the given operands by pdp11_assemble_shift above. */
2115 pdp11_shift_length (rtx
*operands
, machine_mode m
, int code
, bool simple_operand_p
)
2119 /* Shift by 1 is 2 bytes if simple operand, 4 bytes if 2-word addressing mode. */
2120 shift_size
= simple_operand_p
? 2 : 4;
2122 /* In SImode, two shifts are needed per data item. */
2126 /* If shifting by a small constant, the loop is unrolled by the
2127 shift count. Otherwise, account for the size of the decrement
2129 if (CONSTANT_P (operands
[2]) && pdp11_small_shift (INTVAL (operands
[2])))
2130 shift_size
*= INTVAL (operands
[2]);
2134 /* Logical right shift takes one more instruction (CLC). */
2135 if (code
== LSHIFTRT
)
2141 /* Worker function for TARGET_TRAMPOLINE_INIT.
2143 trampoline - how should i do it in separate i+d ?
2144 have some allocate_trampoline magic???
2146 the following should work for shared I/D:
2148 MOV #STATIC, $4 01270Y 0x0000 <- STATIC; Y = STATIC_CHAIN_REGNUM
2149 JMP @#FUNCTION 000137 0x0000 <- FUNCTION
2152 pdp11_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
2154 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
2157 gcc_assert (!TARGET_SPLIT
);
2159 mem
= adjust_address (m_tramp
, HImode
, 0);
2160 emit_move_insn (mem
, GEN_INT (012700+STATIC_CHAIN_REGNUM
));
2161 mem
= adjust_address (m_tramp
, HImode
, 2);
2162 emit_move_insn (mem
, chain_value
);
2163 mem
= adjust_address (m_tramp
, HImode
, 4);
2164 emit_move_insn (mem
, GEN_INT (000137));
2165 emit_move_insn (mem
, fnaddr
);
2168 /* Worker function for TARGET_FUNCTION_ARG.
2170 Determine where to put an argument to a function.
2171 Value is zero to push the argument on the stack,
2172 or a hard register in which to store the argument.
2174 MODE is the argument's machine mode.
2175 TYPE is the data type of the argument (as a tree).
2176 This is null for libcalls where that information may
2178 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2179 the preceding args and about the function being called.
2180 NAMED is nonzero if this argument is a named parameter
2181 (otherwise it is an extra parameter matching an ellipsis). */
2184 pdp11_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED
,
2185 machine_mode mode ATTRIBUTE_UNUSED
,
2186 const_tree type ATTRIBUTE_UNUSED
,
2187 bool named ATTRIBUTE_UNUSED
)
2192 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE.
2194 Update the data in CUM to advance over an argument of mode MODE and
2195 data type TYPE. (TYPE is null for libcalls where that information
2196 may not be available.) */
2199 pdp11_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
2200 const_tree type
, bool named ATTRIBUTE_UNUSED
)
2202 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2204 *cum
+= (mode
!= BLKmode
2205 ? GET_MODE_SIZE (mode
)
2206 : int_size_in_bytes (type
));
2209 /* Make sure everything's fine if we *don't* have an FPU.
2210 This assumes that putting a register in fixed_regs will keep the
2211 compiler's mitts completely off it. We don't bother to zero it out
2212 of register classes. Also fix incompatible register naming with
2213 the UNIX assembler. */
2216 pdp11_conditional_register_usage (void)
2222 COPY_HARD_REG_SET (x
, reg_class_contents
[(int)FPU_REGS
]);
2223 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++ )
2224 if (TEST_HARD_REG_BIT (x
, i
))
2225 fixed_regs
[i
] = call_used_regs
[i
] = 1;
2229 call_used_regs
[AC0_REGNUM
] = 1;
2230 if (TARGET_UNIX_ASM
)
2232 /* Change names of FPU registers for the UNIX assembler. */
2233 reg_names
[8] = "fr0";
2234 reg_names
[9] = "fr1";
2235 reg_names
[10] = "fr2";
2236 reg_names
[11] = "fr3";
2237 reg_names
[12] = "fr4";
2238 reg_names
[13] = "fr5";
2243 pdp11_function_section (tree decl ATTRIBUTE_UNUSED
,
2244 enum node_frequency freq ATTRIBUTE_UNUSED
,
2245 bool startup ATTRIBUTE_UNUSED
,
2246 bool exit ATTRIBUTE_UNUSED
)
2251 /* Support #ident for DEC assembler, but don't process the
2252 auto-generated ident string that names the compiler (since its
2253 syntax is not correct for DEC .ident). */
2254 static void pdp11_output_ident (const char *ident
)
2258 if (strncmp (ident
, "GCC:", 4) != 0)
2259 fprintf (asm_out_file
, "\t.ident\t\"%s\"\n", ident
);
2264 /* This emits a (user) label, which gets a "_" prefix except for DEC
2265 assembler output. */
2267 pdp11_output_labelref (FILE *file
, const char *name
)
2269 if (!TARGET_DEC_ASM
)
2270 fputs (USER_LABEL_PREFIX
, file
);
2274 /* This equates name with value. */
2276 pdp11_output_def (FILE *file
, const char *label1
, const char *label2
)
2280 assemble_name (file
, label1
);
2282 assemble_name (file
, label2
);
2286 fputs (".set", file
);
2287 assemble_name (file
, label1
);
2289 assemble_name (file
, label2
);
2295 pdp11_output_addr_vec_elt (FILE *file
, int value
)
2299 pdp11_gen_int_label (buf
, "L", value
);
2300 if (!TARGET_UNIX_ASM
)
2301 fprintf (file
, "\t.word");
2302 fprintf (file
, "\t%s\n", buf
+ 1);
2305 /* This overrides some target hooks that are initializer elements so
2306 they can't be variables in the #define. */
2308 pdp11_option_override (void)
2312 targetm
.asm_out
.open_paren
= "<";
2313 targetm
.asm_out
.close_paren
= ">";
2318 pdp11_asm_named_section (const char *name
, unsigned int flags
,
2319 tree decl ATTRIBUTE_UNUSED
)
2321 const char *rwro
= (flags
& SECTION_WRITE
) ? "rw" : "ro";
2322 const char *insdat
= (flags
& SECTION_CODE
) ? "i" : "d";
2324 gcc_assert (TARGET_DEC_ASM
);
2325 fprintf (asm_out_file
, "\t.psect\t%s,con,%s,%s\n", name
, insdat
, rwro
);
2329 pdp11_asm_init_sections (void)
2333 bss_section
= data_section
;
2335 else if (TARGET_GNU_ASM
)
2337 bss_section
= get_unnamed_section (SECTION_WRITE
| SECTION_BSS
,
2338 output_section_asm_op
,
2344 pdp11_file_start (void)
2346 default_file_start ();
2349 fprintf (asm_out_file
, "\t.enabl\tlsb,reg\n\n");
2353 pdp11_file_end (void)
2356 fprintf (asm_out_file
, "\t.end\n");
2359 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
2362 pdp11_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
2364 return GET_CODE (x
) != CONST_DOUBLE
|| legitimate_const_double_p (x
);
2367 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
2370 pdp11_scalar_mode_supported_p (scalar_mode mode
)
2372 /* Support SFmode even with -mfloat64. */
2375 return default_scalar_mode_supported_p (mode
);
2378 /* Implement TARGET_HARD_REGNO_NREGS. */
2381 pdp11_hard_regno_nregs (unsigned int regno
, machine_mode mode
)
2383 if (regno
<= PC_REGNUM
)
2384 return CEIL (GET_MODE_SIZE (mode
), UNITS_PER_WORD
);
2388 /* Implement TARGET_HARD_REGNO_MODE_OK. On the pdp, the cpu registers
2389 can hold any mode other than float (because otherwise we may end up
2390 being asked to move from CPU to FPU register, which isn't a valid
2391 operation on the PDP11). For CPU registers, check alignment.
2393 FPU accepts SF and DF but actually holds a DF - simplifies life! */
2396 pdp11_hard_regno_mode_ok (unsigned int regno
, machine_mode mode
)
2398 if (regno
<= PC_REGNUM
)
2399 return (GET_MODE_BITSIZE (mode
) <= 16
2400 || (GET_MODE_BITSIZE (mode
) >= 32
2402 && !FLOAT_MODE_P (mode
)));
2404 return FLOAT_MODE_P (mode
);
2407 /* Implement TARGET_MODES_TIEABLE_P. */
2410 pdp11_modes_tieable_p (machine_mode mode1
, machine_mode mode2
)
2412 return mode1
== HImode
&& mode2
== QImode
;
2415 /* Implement PUSH_ROUNDING. On the pdp11, the stack is on an even
2419 pdp11_push_rounding (poly_int64 bytes
)
2421 return (bytes
+ 1) & ~1;
2424 struct gcc_target targetm
= TARGET_INITIALIZER
;