| blob | 8c9cf6d6aac7eaeb67de1462c97ae2bcb9c3d022 |
1 ;; .........................
2 ;;
3 ;; DFA-based pipeline description for Sandcraft SR3 (MIPS64 based)
4 ;;
5 ;; The SR3 is described as:
6 ;; - nine-stage pipeline, insn buffering with out-of-order issue to
7 ;; multiple function units, with an average dispatch rate of 2
8 ;; insn.s per cycle (max 6 insns: 2 fpu, 4 cpu).
9 ;;
10 ;; The details on this are scant except for a diagram in
11 ;; Chap. 6 of Rev. 1.0 SR3 Spec.
12 ;;
13 ;; The model employed below is designed to closely approximate the
14 ;; published latencies. Emulation of out-of-order issue and the insn
15 ;; buffering is done via a VLIW dispatch style (with a packing of 6 insns);
16 ;; the function unit reservations restrictions (define_*_set) are
17 ;; contrived to support published timings.
18 ;;
19 ;; Reference:
20 ;; "SR3 Microporocessor Specification, System development information,"
21 ;; Revision 1.0, 13 December 2000.
22 ;;
23 ;;
24 ;; Reservation model is based on:
25 ;; 1) Figure 6-1, from the 1.0 specification.
26 ;; 2) Chapter 19, from the 1.0 specification.
27 ;; 3) following questions(Red Hat)/answers(Sandcraft):
28 ;; RH> From Section 19.1
29 ;; RH> 1) In terms of figure 6-1, are all the instructions in
30 ;; RH> table 19-1 restricted
31 ;; RH> to ALUx? When ALUx is not in use for an instruction in table;; RH> 19-1 is
32 ;; RH> it fully compatible with all insns that issue to ALUy?
33 ;;
34 ;; Yes, all the instructions in Table 19-1 only go to ALUX, and all the
35 ;; instructions that can be issued to ALUY can also be issued to ALUX.
36 ;;
37 ;;
38 ;; RH> From Section 19.2
39 ;; RH> 2) Explain conditional moves execution path (in terms of
40 ;; RH> figure 6-1)
41 ;;
42 ;; Conditional move of integer registers (based on floating point condition
43 ;; codes or integer register value) go to ALUX or ALUY.
44 ;;
45 ;; RH> 3) Explain floating point store execution path (in terms of
46 ;; RH> figure 6-1)
47 ;;
48 ;; Floating point stores go to Ld/St and go to MOV in the floating point
49 ;; pipeline.
50 ;;
51 ;; Floating point loads go to Ld/St and go to LOAD in the floating point
52 ;; pipeline.
53 ;;
54 ;; RH> 4) Explain branch on floating condition (in terms of figure 6-1);;
55 ;; Branch on floating condition go to BRU.
56 ;;
57 ;; RH> 5) Is the column for single RECIP instruction latency correct?
58 ;; RH> What about for RSQRT single and double?
59 ;;
60 ;; The latency/repeat for RECIP and RSQRT are correct.
61 ;;
63 ;;
64 ;; Use four automata to isolate long latency operations, and to
65 ;; reduce the complexity of cpu+fpu, reducing space.
66 ;;
67 (define_automaton "sr71_cpu, sr71_cpu1, sr71_cp1, sr71_cp2, sr71_fextra, sr71_imacc")
69 ;; feeders for CPU function units and feeders for fpu (CP1 interface)
70 (define_cpu_unit "sr_iss0,sr_iss1,sr_iss2,sr_iss3,sr_iss4,sr_iss5" "sr71_cpu")
72 ;; CPU function units
73 (define_cpu_unit "ipu_bru" "sr71_cpu1")
74 (define_cpu_unit "ipu_alux" "sr71_cpu1")
75 (define_cpu_unit "ipu_aluy" "sr71_cpu1")
76 (define_cpu_unit "ipu_ldst" "sr71_cpu1")
77 (define_cpu_unit "ipu_macc_iter" "sr71_imacc")
80 ;; Floating-point unit (Co-processor interface 1).
81 (define_cpu_unit "fpu_mov" "sr71_cp1")
82 (define_cpu_unit "fpu_load" "sr71_cp1")
83 (define_cpu_unit "fpu_fpu" "sr71_cp2")
85 ;; fictitous unit to track long float insns with separate automaton
86 (define_cpu_unit "fpu_iter" "sr71_fextra")
89 ;;
90 ;; Define common execution path (reservation) combinations
91 ;;
93 ;;
94 (define_reservation "cpu_iss" "sr_iss0|sr_iss1|sr_iss2|sr_iss3")
96 ;; two cycles are used for instruction using the fpu as it runs
97 ;; at half the clock speed of the cpu. By adding an extra cycle
98 ;; to the issue units, the default/minimum "repeat" dispatch delay is
99 ;; accounted for all insn.s
100 (define_reservation "cp1_iss" "(sr_iss4*2)|(sr_iss5*2)")
102 (define_reservation "serial_dispatch" "sr_iss0+sr_iss1+sr_iss2+sr_iss3+sr_iss4+sr_iss5")
104 ;; Simulate a 6 insn VLIW dispatch, 1 cycle in dispatch followed by
105 ;; reservation of function unit.
106 (define_reservation "ri_insns" "cpu_iss,(ipu_alux|ipu_aluy)")
107 (define_reservation "ri_mem" "cpu_iss,ipu_ldst")
108 (define_reservation "ri_alux" "cpu_iss,ipu_alux")
109 (define_reservation "ri_branch" "cpu_iss,ipu_bru")
111 (define_reservation "rf_insn" "cp1_iss,fpu_fpu")
112 (define_reservation "rf_ldmem" "cp1_iss,fpu_load")
114 ; simultaneous reservation of pseudo-unit keeps cp1 fpu tied
115 ; up until long cycle insn is finished...
116 (define_reservation "rf_multi1" "rf_insn+fpu_iter")
118 ;;
119 ;; The ordering of the instruction-execution-path/resource-usage
120 ;; descriptions (also known as reservation RTL) is roughly ordered
121 ;; based on the define attribute RTL for the "type" classification.
122 ;; When modifying, remember that the first test that matches is the
123 ;; reservation used!
124 ;;
127 (define_insn_reservation "ir_sr70_unknown"
128 1
129 (and (eq_attr "cpu" "sr71000")
130 (eq_attr "type" "unknown"))
131 "serial_dispatch")
134 ;; Assume prediction fails.
135 (define_insn_reservation "ir_sr70_branch"
136 6
137 (and (eq_attr "cpu" "sr71000")
138 (eq_attr "type" "branch,jump,call"))
139 "ri_branch")
141 (define_insn_reservation "ir_sr70_load"
142 2
143 (and (eq_attr "cpu" "sr71000")
144 (eq_attr "type" "load"))
145 "ri_mem")
147 (define_insn_reservation "ir_sr70_store"
148 1
149 (and (eq_attr "cpu" "sr71000")
150 (eq_attr "type" "store"))
151 "ri_mem")
154 ;;
155 ;; float loads/stores flow through both cpu and cp1...
156 ;;
157 (define_insn_reservation "ir_sr70_fload"
158 9
159 (and (eq_attr "cpu" "sr71000")
160 (eq_attr "type" "fpload,fpidxload"))
161 "(cpu_iss+cp1_iss),(ri_mem+rf_ldmem)")
163 (define_insn_reservation "ir_sr70_fstore"
164 1
165 (and (eq_attr "cpu" "sr71000")
166 (eq_attr "type" "fpstore,fpidxstore"))
167 "(cpu_iss+cp1_iss),(fpu_mov+ri_mem)")
170 ;; This reservation is for conditional move based on integer
171 ;; or floating point CC.
172 (define_insn_reservation "ir_sr70_condmove"
173 4
174 (and (eq_attr "cpu" "sr71000")
175 (eq_attr "type" "condmove"))
176 "ri_insns")
178 ;; Try to discriminate move-from-cp1 versus move-to-cp1 as latencies
179 ;; are different. Like float load/store, these insns use multiple
180 ;; resources simultaneously
181 (define_insn_reservation "ir_sr70_xfer_from"
182 6
183 (and (eq_attr "cpu" "sr71000")
184 (and (eq_attr "type" "xfer")
185 (eq_attr "mode" "!SF,DF,FPSW")))
186 "(cpu_iss+cp1_iss),(fpu_mov+ri_mem)")
188 (define_insn_reservation "ir_sr70_xfer_to"
189 9
190 (and (eq_attr "cpu" "sr71000")
191 (and (eq_attr "type" "xfer")
192 (eq_attr "mode" "SF,DF")))
193 "(cpu_iss+cp1_iss),(ri_mem+rf_ldmem)")
195 (define_insn_reservation "ir_sr70_hilo"
196 1
197 (and (eq_attr "cpu" "sr71000")
198 (eq_attr "type" "hilo"))
199 "ri_insns")
201 (define_insn_reservation "ir_sr70_arith"
202 1
203 (and (eq_attr "cpu" "sr71000")
204 (eq_attr "type" "move,arith,darith,const"))
205 "ri_insns")
207 ;; emulate repeat (dispatch stall) by spending extra cycle(s) in
208 ;; in iter unit
209 (define_insn_reservation "ir_sr70_imul_si"
210 4
211 (and (eq_attr "cpu" "sr71000")
212 (and (eq_attr "type" "imul,imadd")
213 (eq_attr "mode" "SI")))
214 "ri_alux,ipu_alux,ipu_macc_iter")
216 (define_insn_reservation "ir_sr70_imul_di"
217 6
218 (and (eq_attr "cpu" "sr71000")
219 (and (eq_attr "type" "imul,imadd")
220 (eq_attr "mode" "DI")))
221 "ri_alux,ipu_alux,(ipu_macc_iter*3)")
223 ;; Divide algorithm is early out with best latency of 7 pcycles.
224 ;; Use worst case for scheduling purposes.
225 (define_insn_reservation "ir_sr70_idiv_si"
226 41
227 (and (eq_attr "cpu" "sr71000")
228 (and (eq_attr "type" "idiv")
229 (eq_attr "mode" "SI")))
230 "ri_alux,ipu_alux,(ipu_macc_iter*38)")
232 (define_insn_reservation "ir_sr70_idiv_di"
233 73
234 (and (eq_attr "cpu" "sr71000")
235 (and (eq_attr "type" "idiv")
236 (eq_attr "mode" "DI")))
237 "ri_alux,ipu_alux,(ipu_macc_iter*70)")
239 (define_insn_reservation "ir_sr70_icmp"
240 1
241 (and (eq_attr "cpu" "sr71000")
242 (eq_attr "type" "icmp"))
243 "ri_insns")
245 ;; extra reservations of fpu_fpu are for repeat latency
246 (define_insn_reservation "ir_sr70_fadd_sf"
247 8
248 (and (eq_attr "cpu" "sr71000")
249 (and (eq_attr "type" "fadd")
250 (eq_attr "mode" "SF")))
251 "rf_insn,fpu_fpu")
253 (define_insn_reservation "ir_sr70_fadd_df"
254 10
255 (and (eq_attr "cpu" "sr71000")
256 (and (eq_attr "type" "fadd")
257 (eq_attr "mode" "DF")))
258 "rf_insn,fpu_fpu")
260 ;; Latencies for MADD,MSUB, NMADD, NMSUB assume the Multiply is fused
261 ;; with the sub or add.
262 (define_insn_reservation "ir_sr70_fmul_sf"
263 8
264 (and (eq_attr "cpu" "sr71000")
265 (and (eq_attr "type" "fmul,fmadd")
266 (eq_attr "mode" "SF")))
267 "rf_insn,fpu_fpu")
269 ;; tie up the fpu unit to emulate the balance for the "repeat
270 ;; rate" of 8 (2 are spent in the iss unit)
271 (define_insn_reservation "ir_sr70_fmul_df"
272 16
273 (and (eq_attr "cpu" "sr71000")
274 (and (eq_attr "type" "fmul,fmadd")
275 (eq_attr "mode" "DF")))
276 "rf_insn,fpu_fpu*6")
279 ;; RECIP insn uses same type attr as div, and for SR3, has same
280 ;; timings for double. However, single RECIP has a latency of
281 ;; 28 -- only way to fix this is to introduce new insn attrs.
282 ;; cycles spent in iter unit are designed to satisfy balance
283 ;; of "repeat" latency after insn uses up rf_multi1 reservation
284 (define_insn_reservation "ir_sr70_fdiv_sf"
285 60
286 (and (eq_attr "cpu" "sr71000")
287 (and (eq_attr "type" "fdiv")
288 (eq_attr "mode" "SF")))
289 "rf_multi1+(fpu_iter*51)")
291 (define_insn_reservation "ir_sr70_fdiv_df"
292 120
293 (and (eq_attr "cpu" "sr71000")
294 (and (eq_attr "type" "fdiv")
295 (eq_attr "mode" "DF")))
296 "rf_multi1+(fpu_iter*109)")
298 (define_insn_reservation "ir_sr70_fabs"
299 4
300 (and (eq_attr "cpu" "sr71000")
301 (eq_attr "type" "fabs,fneg"))
302 "rf_insn,fpu_fpu")
304 (define_insn_reservation "ir_sr70_fcmp"
305 10
306 (and (eq_attr "cpu" "sr71000")
307 (eq_attr "type" "fcmp"))
308 "rf_insn,fpu_fpu")
310 ;; "fcvt" type attribute covers a number of diff insns, most have the same
311 ;; latency descriptions, a few vary. We use the
312 ;; most common timing (which is also worst case).
313 (define_insn_reservation "ir_sr70_fcvt"
314 12
315 (and (eq_attr "cpu" "sr71000")
316 (eq_attr "type" "fcvt"))
317 "rf_insn,fpu_fpu*4")
319 (define_insn_reservation "ir_sr70_fsqrt_sf"
320 62
321 (and (eq_attr "cpu" "sr71000")
322 (and (eq_attr "type" "fsqrt")
323 (eq_attr "mode" "SF")))
324 "rf_multi1+(fpu_iter*53)")
326 (define_insn_reservation "ir_sr70_fsqrt_df"
327 122
328 (and (eq_attr "cpu" "sr71000")
329 (and (eq_attr "type" "fsqrt")
330 (eq_attr "mode" "DF")))
331 "rf_multi1+(fpu_iter*111)")
333 (define_insn_reservation "ir_sr70_frsqrt_sf"
334 48
335 (and (eq_attr "cpu" "sr71000")
336 (and (eq_attr "type" "frsqrt")
337 (eq_attr "mode" "SF")))
338 "rf_multi1+(fpu_iter*39)")
340 (define_insn_reservation "ir_sr70_frsqrt_df"
341 240
342 (and (eq_attr "cpu" "sr71000")
343 (and (eq_attr "type" "frsqrt")
344 (eq_attr "mode" "DF")))
345 "rf_multi1+(fpu_iter*229)")
347 (define_insn_reservation "ir_sr70_multi"
348 1
349 (and (eq_attr "cpu" "sr71000")
350 (eq_attr "type" "multi"))
351 "serial_dispatch")
353 (define_insn_reservation "ir_sr70_nop"
354 1
355 (and (eq_attr "cpu" "sr71000")
356 (eq_attr "type" "nop"))
357 "ri_insns")