1 ;;- Machine description for GNU compiler -- S/390 / zSeries version.
2 ;; Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and
5 ;; Ulrich Weigand (uweigand@de.ibm.com).
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify it under
10 ;; the terms of the GNU General Public License as published by the Free
11 ;; Software Foundation; either version 2, or (at your option) any later
14 ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to the Free
21 ;; Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 ;; Special constraints for s/390 machine description:
27 ;; a -- Any address register from 1 to 15.
28 ;; c -- Condition code register 33.
29 ;; d -- Any register from 0 to 15.
30 ;; I -- An 8-bit constant (0..255).
31 ;; J -- A 12-bit constant (0..4095).
32 ;; K -- A 16-bit constant (-32768..32767).
33 ;; L -- Value appropriate as displacement.
34 ;; (0..4095) for short displacement
35 ;; (-524288..524287) for long displacement
36 ;; M -- Constant integer with a value of 0x7fffffff.
37 ;; N -- Multiple letter constraint followed by 4 parameter letters.
38 ;; 0..9,x: number of the part counting from most to least significant
39 ;; H,Q: mode of the part
40 ;; D,S,H: mode of the containing operand
41 ;; 0,F: value of the other parts (F - all bits set)
43 ;; The constraint matches if the specified part of a constant
44 ;; has a value different from its other parts. If the letter x
45 ;; is specified instead of a part number, the constraint matches
46 ;; if there is any single part with non-default value.
47 ;; Q -- Memory reference without index register and with short displacement.
48 ;; R -- Memory reference with index register and short displacement.
49 ;; S -- Memory reference without index register but with long displacement.
50 ;; T -- Memory reference with index register and long displacement.
51 ;; A -- Multiple letter constraint followed by Q, R, S, or T:
52 ;; Offsettable memory reference of type specified by second letter.
53 ;; B -- Multiple letter constraint followed by Q, R, S, or T:
54 ;; Memory reference of the type specified by second letter that
55 ;; does *not* refer to a literal pool entry.
56 ;; U -- Pointer with short displacement.
57 ;; W -- Pointer with long displacement.
58 ;; Y -- Shift count operand.
60 ;; Special formats used for outputting 390 instructions.
62 ;; %C: print opcode suffix for branch condition.
63 ;; %D: print opcode suffix for inverse branch condition.
64 ;; %J: print tls_load/tls_gdcall/tls_ldcall suffix
65 ;; %O: print only the displacement of a memory reference.
66 ;; %R: print only the base register of a memory reference.
67 ;; %S: print S-type memory reference (base+displacement).
68 ;; %N: print the second word of a DImode operand.
69 ;; %M: print the second word of a TImode operand.
71 ;; %b: print integer X as if it's an unsigned byte.
72 ;; %x: print integer X as if it's an unsigned word.
73 ;; %h: print integer X as if it's a signed word.
74 ;; %i: print the first nonzero HImode part of X
75 ;; %j: print the first HImode part unequal to 0xffff of X
78 ;; We have a special constraint for pattern matching.
80 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
93 ; GOT/PLT and lt-relative accesses
94 (UNSPEC_LTREL_OFFSET 100)
95 (UNSPEC_LTREL_BASE 101)
103 (UNSPEC_RELOAD_BASE 210)
104 (UNSPEC_MAIN_BASE 211)
109 ; TLS relocation specifiers
114 (UNSPEC_GOTNTPOFF 504)
115 (UNSPEC_INDNTPOFF 505)
118 (UNSPEC_TLSLDM_NTPOFF 511)
119 (UNSPEC_TLS_LOAD 512)
126 ;; UNSPEC_VOLATILE usage
134 (UNSPECV_TPF_PROLOGUE 20)
135 (UNSPECV_TPF_EPILOGUE 21)
139 (UNSPECV_POOL_SECTION 201)
140 (UNSPECV_POOL_ALIGN 202)
141 (UNSPECV_POOL_ENTRY 203)
142 (UNSPECV_MAIN_POOL 300)
149 ;; Instruction operand type as used in the Principles of Operation.
150 ;; Used to determine defaults for length and other attribute values.
152 (define_attr "op_type"
153 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
156 ;; Instruction type attribute used for scheduling.
158 (define_attr "type" "none,integer,load,lr,la,larl,lm,stm,
159 cs,vs,store,imul,idiv,
160 branch,jsr,fsimpd,fsimps,
161 floadd,floads,fstored, fstores,
162 fmuld,fmuls,fdivd,fdivs,
163 ftoi,itof,fsqrtd,fsqrts,
165 (cond [(eq_attr "op_type" "NN") (const_string "other")
166 (eq_attr "op_type" "SS") (const_string "cs")]
167 (const_string "integer")))
169 ;; Another attribute used for scheduling purposes:
170 ;; agen: Instruction uses the address generation unit
171 ;; reg: Instruction does not use the agen unit
173 (define_attr "atype" "agen,reg"
174 (cond [(eq_attr "op_type" "E") (const_string "reg")
175 (eq_attr "op_type" "RR") (const_string "reg")
176 (eq_attr "op_type" "RX") (const_string "agen")
177 (eq_attr "op_type" "RI") (const_string "reg")
178 (eq_attr "op_type" "RRE") (const_string "reg")
179 (eq_attr "op_type" "RS") (const_string "agen")
180 (eq_attr "op_type" "RSI") (const_string "agen")
181 (eq_attr "op_type" "S") (const_string "agen")
182 (eq_attr "op_type" "SI") (const_string "agen")
183 (eq_attr "op_type" "SS") (const_string "agen")
184 (eq_attr "op_type" "SSE") (const_string "agen")
185 (eq_attr "op_type" "RXE") (const_string "agen")
186 (eq_attr "op_type" "RSE") (const_string "agen")
187 (eq_attr "op_type" "RIL") (const_string "agen")
188 (eq_attr "op_type" "RXY") (const_string "agen")
189 (eq_attr "op_type" "RSY") (const_string "agen")
190 (eq_attr "op_type" "SIY") (const_string "agen")]
191 (const_string "agen")))
195 (define_attr "length" ""
196 (cond [(eq_attr "op_type" "E") (const_int 2)
197 (eq_attr "op_type" "RR") (const_int 2)
198 (eq_attr "op_type" "RX") (const_int 4)
199 (eq_attr "op_type" "RI") (const_int 4)
200 (eq_attr "op_type" "RRE") (const_int 4)
201 (eq_attr "op_type" "RS") (const_int 4)
202 (eq_attr "op_type" "RSI") (const_int 4)
203 (eq_attr "op_type" "S") (const_int 4)
204 (eq_attr "op_type" "SI") (const_int 4)
205 (eq_attr "op_type" "SS") (const_int 6)
206 (eq_attr "op_type" "SSE") (const_int 6)
207 (eq_attr "op_type" "RXE") (const_int 6)
208 (eq_attr "op_type" "RSE") (const_int 6)
209 (eq_attr "op_type" "RIL") (const_int 6)
210 (eq_attr "op_type" "RXY") (const_int 6)
211 (eq_attr "op_type" "RSY") (const_int 6)
212 (eq_attr "op_type" "SIY") (const_int 6)]
216 ;; Processor type. This attribute must exactly match the processor_type
217 ;; enumeration in s390.h. The current machine description does not
218 ;; distinguish between g5 and g6, but there are differences between the two
219 ;; CPUs could in theory be modeled.
221 (define_attr "cpu" "g5,g6,z900,z990"
222 (const (symbol_ref "s390_tune")))
224 ;; Pipeline description for z900. For lack of anything better,
225 ;; this description is also used for the g5 and g6.
228 ;; Pipeline description for z990.
232 ;;- Compare instructions.
235 (define_expand "cmpdi"
237 (compare:CC (match_operand:DI 0 "register_operand" "")
238 (match_operand:DI 1 "general_operand" "")))]
241 s390_compare_op0 = operands[0];
242 s390_compare_op1 = operands[1];
246 (define_expand "cmpsi"
248 (compare:CC (match_operand:SI 0 "register_operand" "")
249 (match_operand:SI 1 "general_operand" "")))]
252 s390_compare_op0 = operands[0];
253 s390_compare_op1 = operands[1];
257 (define_expand "cmpdf"
259 (compare:CC (match_operand:DF 0 "register_operand" "")
260 (match_operand:DF 1 "general_operand" "")))]
263 s390_compare_op0 = operands[0];
264 s390_compare_op1 = operands[1];
268 (define_expand "cmpsf"
270 (compare:CC (match_operand:SF 0 "register_operand" "")
271 (match_operand:SF 1 "general_operand" "")))]
274 s390_compare_op0 = operands[0];
275 s390_compare_op1 = operands[1];
280 ; Test-under-Mask instructions
282 (define_insn "*tmqi_mem"
284 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S")
285 (match_operand:QI 1 "immediate_operand" "n,n"))
286 (match_operand:QI 2 "immediate_operand" "n,n")))]
287 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 0))"
291 [(set_attr "op_type" "SI,SIY")])
293 (define_insn "*tmdi_reg"
295 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d")
296 (match_operand:DI 1 "immediate_operand"
297 "N0HD0,N1HD0,N2HD0,N3HD0"))
298 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))]
300 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
301 && s390_single_part (operands[1], DImode, HImode, 0) >= 0"
307 [(set_attr "op_type" "RI")])
309 (define_insn "*tmsi_reg"
311 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d")
312 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0"))
313 (match_operand:SI 2 "immediate_operand" "n,n")))]
314 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], 1))
315 && s390_single_part (operands[1], SImode, HImode, 0) >= 0"
319 [(set_attr "op_type" "RI")])
321 (define_insn "*tmhi_full"
323 (compare (match_operand:HI 0 "register_operand" "d")
324 (match_operand:HI 1 "immediate_operand" "n")))]
325 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))"
327 [(set_attr "op_type" "RI")])
329 (define_insn "*tmqi_full"
331 (compare (match_operand:QI 0 "register_operand" "d")
332 (match_operand:QI 1 "immediate_operand" "n")))]
333 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], 1))"
335 [(set_attr "op_type" "RI")])
338 ; Load-and-Test instructions
340 (define_insn "*tstdi_sign"
342 (compare (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 0 "register_operand" "d") 0)
343 (const_int 32)) (const_int 32))
344 (match_operand:DI 1 "const0_operand" "")))
345 (set (match_operand:DI 2 "register_operand" "=d")
346 (sign_extend:DI (match_dup 0)))]
347 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
349 [(set_attr "op_type" "RRE")])
351 (define_insn "*tstdi"
353 (compare (match_operand:DI 0 "register_operand" "d")
354 (match_operand:DI 1 "const0_operand" "")))
355 (set (match_operand:DI 2 "register_operand" "=d")
357 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
359 [(set_attr "op_type" "RRE")])
361 (define_insn "*tstdi_cconly"
363 (compare (match_operand:DI 0 "register_operand" "d")
364 (match_operand:DI 1 "const0_operand" "")))]
365 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
367 [(set_attr "op_type" "RRE")])
369 (define_insn "*tstdi_cconly_31"
371 (compare (match_operand:DI 0 "register_operand" "d")
372 (match_operand:DI 1 "const0_operand" "")))]
373 "s390_match_ccmode(insn, CCSmode) && !TARGET_64BIT"
375 [(set_attr "op_type" "RS")
376 (set_attr "atype" "reg")])
379 (define_insn "*tstsi"
381 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
382 (match_operand:SI 1 "const0_operand" "")))
383 (set (match_operand:SI 2 "register_operand" "=d,d,d")
385 "s390_match_ccmode(insn, CCSmode)"
390 [(set_attr "op_type" "RR,RS,RSY")])
392 (define_insn "*tstsi_cconly"
394 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S")
395 (match_operand:SI 1 "const0_operand" "")))
396 (clobber (match_scratch:SI 2 "=X,d,d"))]
397 "s390_match_ccmode(insn, CCSmode)"
402 [(set_attr "op_type" "RR,RS,RSY")])
404 (define_insn "*tstsi_cconly2"
406 (compare (match_operand:SI 0 "register_operand" "d")
407 (match_operand:SI 1 "const0_operand" "")))]
408 "s390_match_ccmode(insn, CCSmode)"
410 [(set_attr "op_type" "RR")])
412 (define_insn "*tsthiCCT"
414 (compare (match_operand:HI 0 "nonimmediate_operand" "?Q,?S,d")
415 (match_operand:HI 1 "const0_operand" "")))
416 (set (match_operand:HI 2 "register_operand" "=d,d,0")
418 "s390_match_ccmode(insn, CCTmode)"
423 [(set_attr "op_type" "RS,RSY,RI")])
425 (define_insn "*tsthiCCT_cconly"
427 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d")
428 (match_operand:HI 1 "const0_operand" "")))
429 (clobber (match_scratch:HI 2 "=d,d,X"))]
430 "s390_match_ccmode(insn, CCTmode)"
435 [(set_attr "op_type" "RS,RSY,RI")])
437 (define_insn "*tsthi"
439 (compare (match_operand:HI 0 "s_operand" "Q,S")
440 (match_operand:HI 1 "const0_operand" "")))
441 (set (match_operand:HI 2 "register_operand" "=d,d")
443 "s390_match_ccmode(insn, CCSmode)"
447 [(set_attr "op_type" "RS,RSY")])
449 (define_insn "*tsthi_cconly"
451 (compare (match_operand:HI 0 "s_operand" "Q,S")
452 (match_operand:HI 1 "const0_operand" "")))
453 (clobber (match_scratch:HI 2 "=d,d"))]
454 "s390_match_ccmode(insn, CCSmode)"
458 [(set_attr "op_type" "RS,RSY")])
460 (define_insn "*tstqiCCT"
462 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
463 (match_operand:QI 1 "const0_operand" "")))
464 (set (match_operand:QI 2 "register_operand" "=d,d,0")
466 "s390_match_ccmode(insn, CCTmode)"
471 [(set_attr "op_type" "RS,RSY,RI")])
473 (define_insn "*tstqiCCT_cconly"
475 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d")
476 (match_operand:QI 1 "const0_operand" "")))]
477 "s390_match_ccmode(insn, CCTmode)"
482 [(set_attr "op_type" "SI,SIY,RI")])
484 (define_insn "*tstqi"
486 (compare (match_operand:QI 0 "s_operand" "Q,S")
487 (match_operand:QI 1 "const0_operand" "")))
488 (set (match_operand:QI 2 "register_operand" "=d,d")
490 "s390_match_ccmode(insn, CCSmode)"
494 [(set_attr "op_type" "RS,RSY")])
496 (define_insn "*tstqi_cconly"
498 (compare (match_operand:QI 0 "s_operand" "Q,S")
499 (match_operand:QI 1 "const0_operand" "")))
500 (clobber (match_scratch:QI 2 "=d,d"))]
501 "s390_match_ccmode(insn, CCSmode)"
505 [(set_attr "op_type" "RS,RSY")])
508 ; Compare (equality) instructions
510 (define_insn "*cmpdi_cct"
512 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,Q")
513 (match_operand:DI 1 "general_operand" "d,K,m,BQ")))]
514 "s390_match_ccmode (insn, CCTmode) && TARGET_64BIT"
520 [(set_attr "op_type" "RRE,RI,RXY,SS")])
522 (define_insn "*cmpsi_cct"
524 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,Q")
525 (match_operand:SI 1 "general_operand" "d,K,R,T,BQ")))]
526 "s390_match_ccmode (insn, CCTmode)"
533 [(set_attr "op_type" "RR,RI,RX,RXY,SS")])
536 ; Compare (signed) instructions
538 (define_insn "*cmpdi_ccs_sign"
540 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
541 (match_operand:DI 0 "register_operand" "d,d")))]
542 "s390_match_ccmode(insn, CCSRmode) && TARGET_64BIT"
546 [(set_attr "op_type" "RRE,RXY")])
548 (define_insn "*cmpdi_ccs"
550 (compare (match_operand:DI 0 "register_operand" "d,d,d")
551 (match_operand:DI 1 "general_operand" "d,K,m")))]
552 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
557 [(set_attr "op_type" "RRE,RI,RXY")])
559 (define_insn "*cmpsi_ccs_sign"
561 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T"))
562 (match_operand:SI 0 "register_operand" "d,d")))]
563 "s390_match_ccmode(insn, CCSRmode)"
567 [(set_attr "op_type" "RX,RXY")])
569 (define_insn "*cmpsi_ccs"
571 (compare (match_operand:SI 0 "register_operand" "d,d,d,d")
572 (match_operand:SI 1 "general_operand" "d,K,R,T")))]
573 "s390_match_ccmode(insn, CCSmode)"
579 [(set_attr "op_type" "RR,RI,RX,RXY")])
582 ; Compare (unsigned) instructions
584 (define_insn "*cmpdi_ccu_zero"
586 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m"))
587 (match_operand:DI 0 "register_operand" "d,d")))]
588 "s390_match_ccmode (insn, CCURmode) && TARGET_64BIT"
592 [(set_attr "op_type" "RRE,RXY")])
594 (define_insn "*cmpdi_ccu"
596 (compare (match_operand:DI 0 "nonimmediate_operand" "d,d,Q,BQ")
597 (match_operand:DI 1 "general_operand" "d,m,BQ,Q")))]
598 "s390_match_ccmode (insn, CCUmode) && TARGET_64BIT"
604 [(set_attr "op_type" "RRE,RXY,SS,SS")])
606 (define_insn "*cmpsi_ccu"
608 (compare (match_operand:SI 0 "nonimmediate_operand" "d,d,d,Q,BQ")
609 (match_operand:SI 1 "general_operand" "d,R,T,BQ,Q")))]
610 "s390_match_ccmode (insn, CCUmode)"
617 [(set_attr "op_type" "RR,RX,RXY,SS,SS")])
619 (define_insn "*cmphi_ccu"
621 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,BQ")
622 (match_operand:HI 1 "general_operand" "Q,S,BQ,Q")))]
623 "s390_match_ccmode (insn, CCUmode)
624 && !register_operand (operands[1], HImode)"
630 [(set_attr "op_type" "RS,RSY,SS,SS")])
632 (define_insn "*cmpqi_ccu"
634 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ")
635 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))]
636 "s390_match_ccmode (insn, CCUmode)
637 && !register_operand (operands[1], QImode)"
645 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS")])
648 ; Block compare (CLC) instruction patterns.
652 (compare (match_operand:BLK 0 "memory_operand" "Q")
653 (match_operand:BLK 1 "memory_operand" "Q")))
654 (use (match_operand 2 "const_int_operand" "n"))]
655 "s390_match_ccmode (insn, CCUmode)
656 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
657 "clc\t%O0(%2,%R0),%S1"
658 [(set_attr "op_type" "SS")])
662 (compare (match_operand 0 "memory_operand" "")
663 (match_operand 1 "memory_operand" "")))]
665 && s390_match_ccmode (insn, CCUmode)
666 && GET_MODE (operands[0]) == GET_MODE (operands[1])
667 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
669 [(set (match_dup 0) (match_dup 1))
670 (use (match_dup 2))])]
672 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
673 operands[0] = adjust_address (operands[0], BLKmode, 0);
674 operands[1] = adjust_address (operands[1], BLKmode, 0);
676 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))),
677 operands[0], operands[1]);
678 operands[0] = SET_DEST (PATTERN (curr_insn));
684 (define_insn "*cmpdf_ccs_0"
686 (compare (match_operand:DF 0 "register_operand" "f")
687 (match_operand:DF 1 "const0_operand" "")))]
688 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
690 [(set_attr "op_type" "RRE")
691 (set_attr "type" "fsimpd")])
693 (define_insn "*cmpdf_ccs_0_ibm"
695 (compare (match_operand:DF 0 "register_operand" "f")
696 (match_operand:DF 1 "const0_operand" "")))]
697 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
699 [(set_attr "op_type" "RR")
700 (set_attr "type" "fsimpd")])
702 (define_insn "*cmpdf_ccs"
704 (compare (match_operand:DF 0 "register_operand" "f,f")
705 (match_operand:DF 1 "general_operand" "f,R")))]
706 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
710 [(set_attr "op_type" "RRE,RXE")
711 (set_attr "type" "fsimpd")])
713 (define_insn "*cmpdf_ccs_ibm"
715 (compare (match_operand:DF 0 "register_operand" "f,f")
716 (match_operand:DF 1 "general_operand" "f,R")))]
717 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
721 [(set_attr "op_type" "RR,RX")
722 (set_attr "type" "fsimpd")])
727 (define_insn "*cmpsf_ccs_0"
729 (compare (match_operand:SF 0 "register_operand" "f")
730 (match_operand:SF 1 "const0_operand" "")))]
731 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
733 [(set_attr "op_type" "RRE")
734 (set_attr "type" "fsimps")])
736 (define_insn "*cmpsf_ccs_0_ibm"
738 (compare (match_operand:SF 0 "register_operand" "f")
739 (match_operand:SF 1 "const0_operand" "")))]
740 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
742 [(set_attr "op_type" "RR")
743 (set_attr "type" "fsimps")])
745 (define_insn "*cmpsf_ccs"
747 (compare (match_operand:SF 0 "register_operand" "f,f")
748 (match_operand:SF 1 "general_operand" "f,R")))]
749 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
753 [(set_attr "op_type" "RRE,RXE")
754 (set_attr "type" "fsimps")])
756 (define_insn "*cmpsf_ccs"
758 (compare (match_operand:SF 0 "register_operand" "f,f")
759 (match_operand:SF 1 "general_operand" "f,R")))]
760 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
764 [(set_attr "op_type" "RR,RX")
765 (set_attr "type" "fsimps")])
769 ;;- Move instructions.
773 ; movti instruction pattern(s).
777 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,d,o,Q")
778 (match_operand:TI 1 "general_operand" "QS,d,dKm,d,Q"))]
786 [(set_attr "op_type" "RSY,RSY,*,*,SS")
787 (set_attr "type" "lm,stm,*,*,*")])
790 [(set (match_operand:TI 0 "nonimmediate_operand" "")
791 (match_operand:TI 1 "general_operand" ""))]
792 "TARGET_64BIT && reload_completed
793 && s390_split_ok_p (operands[0], operands[1], TImode, 0)"
794 [(set (match_dup 2) (match_dup 4))
795 (set (match_dup 3) (match_dup 5))]
797 operands[2] = operand_subword (operands[0], 0, 0, TImode);
798 operands[3] = operand_subword (operands[0], 1, 0, TImode);
799 operands[4] = operand_subword (operands[1], 0, 0, TImode);
800 operands[5] = operand_subword (operands[1], 1, 0, TImode);
804 [(set (match_operand:TI 0 "nonimmediate_operand" "")
805 (match_operand:TI 1 "general_operand" ""))]
806 "TARGET_64BIT && reload_completed
807 && s390_split_ok_p (operands[0], operands[1], TImode, 1)"
808 [(set (match_dup 2) (match_dup 4))
809 (set (match_dup 3) (match_dup 5))]
811 operands[2] = operand_subword (operands[0], 1, 0, TImode);
812 operands[3] = operand_subword (operands[0], 0, 0, TImode);
813 operands[4] = operand_subword (operands[1], 1, 0, TImode);
814 operands[5] = operand_subword (operands[1], 0, 0, TImode);
818 [(set (match_operand:TI 0 "register_operand" "")
819 (match_operand:TI 1 "memory_operand" ""))]
820 "TARGET_64BIT && reload_completed
821 && !s_operand (operands[1], VOIDmode)"
822 [(set (match_dup 0) (match_dup 1))]
824 rtx addr = operand_subword (operands[0], 1, 0, TImode);
825 s390_load_address (addr, XEXP (operands[1], 0));
826 operands[1] = replace_equiv_address (operands[1], addr);
829 (define_expand "reload_outti"
830 [(parallel [(match_operand:TI 0 "" "")
831 (match_operand:TI 1 "register_operand" "d")
832 (match_operand:DI 2 "register_operand" "=&a")])]
835 gcc_assert (MEM_P (operands[0]));
836 s390_load_address (operands[2], XEXP (operands[0], 0));
837 operands[0] = replace_equiv_address (operands[0], operands[2]);
838 emit_move_insn (operands[0], operands[1]);
843 ; movdi instruction pattern(s).
846 (define_expand "movdi"
847 [(set (match_operand:DI 0 "general_operand" "")
848 (match_operand:DI 1 "general_operand" ""))]
851 /* Handle symbolic constants. */
852 if (TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
853 emit_symbolic_move (operands);
856 (define_insn "*movdi_larl"
857 [(set (match_operand:DI 0 "register_operand" "=d")
858 (match_operand:DI 1 "larl_operand" "X"))]
860 && !FP_REG_P (operands[0])"
862 [(set_attr "op_type" "RIL")
863 (set_attr "type" "larl")])
865 (define_insn "*movdi_64"
866 [(set (match_operand:DI 0 "nonimmediate_operand"
867 "=d,d,d,d,d,d,d,d,m,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
868 (match_operand:DI 1 "general_operand"
869 "K,N0HD0,N1HD0,N2HD0,N3HD0,L,d,m,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
891 [(set_attr "op_type" "RI,RI,RI,RI,RI,RXY,RRE,RXY,RXY,
892 RR,RX,RXY,RX,RXY,*,*,RS,RS,SS")
893 (set_attr "type" "*,*,*,*,*,la,lr,load,store,
894 floadd,floadd,floadd,fstored,fstored,*,*,*,*,*")])
897 [(set (match_operand:DI 0 "register_operand" "")
898 (match_operand:DI 1 "register_operand" ""))]
899 "TARGET_64BIT && ACCESS_REG_P (operands[1])"
900 [(set (match_dup 2) (match_dup 3))
901 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
902 (set (strict_low_part (match_dup 2)) (match_dup 4))]
903 "operands[2] = gen_lowpart (SImode, operands[0]);
904 s390_split_access_reg (operands[1], &operands[4], &operands[3]);")
907 [(set (match_operand:DI 0 "register_operand" "")
908 (match_operand:DI 1 "register_operand" ""))]
909 "TARGET_64BIT && ACCESS_REG_P (operands[0])
910 && dead_or_set_p (insn, operands[1])"
911 [(set (match_dup 3) (match_dup 2))
912 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32)))
913 (set (match_dup 4) (match_dup 2))]
914 "operands[2] = gen_lowpart (SImode, operands[1]);
915 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
918 [(set (match_operand:DI 0 "register_operand" "")
919 (match_operand:DI 1 "register_operand" ""))]
920 "TARGET_64BIT && ACCESS_REG_P (operands[0])
921 && !dead_or_set_p (insn, operands[1])"
922 [(set (match_dup 3) (match_dup 2))
923 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))
924 (set (match_dup 4) (match_dup 2))
925 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))]
926 "operands[2] = gen_lowpart (SImode, operands[1]);
927 s390_split_access_reg (operands[0], &operands[3], &operands[4]);")
929 (define_insn "*movdi_31"
930 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,Q,d,o,!*f,!*f,!*f,!R,!T,Q")
931 (match_operand:DI 1 "general_operand" "Q,d,dKm,d,*f,R,T,*f,*f,Q"))]
944 [(set_attr "op_type" "RS,RS,*,*,RR,RX,RXY,RX,RXY,SS")
945 (set_attr "type" "lm,stm,*,*,floadd,floadd,floadd,fstored,fstored,*")])
948 [(set (match_operand:DI 0 "nonimmediate_operand" "")
949 (match_operand:DI 1 "general_operand" ""))]
950 "!TARGET_64BIT && reload_completed
951 && s390_split_ok_p (operands[0], operands[1], DImode, 0)"
952 [(set (match_dup 2) (match_dup 4))
953 (set (match_dup 3) (match_dup 5))]
955 operands[2] = operand_subword (operands[0], 0, 0, DImode);
956 operands[3] = operand_subword (operands[0], 1, 0, DImode);
957 operands[4] = operand_subword (operands[1], 0, 0, DImode);
958 operands[5] = operand_subword (operands[1], 1, 0, DImode);
962 [(set (match_operand:DI 0 "nonimmediate_operand" "")
963 (match_operand:DI 1 "general_operand" ""))]
964 "!TARGET_64BIT && reload_completed
965 && s390_split_ok_p (operands[0], operands[1], DImode, 1)"
966 [(set (match_dup 2) (match_dup 4))
967 (set (match_dup 3) (match_dup 5))]
969 operands[2] = operand_subword (operands[0], 1, 0, DImode);
970 operands[3] = operand_subword (operands[0], 0, 0, DImode);
971 operands[4] = operand_subword (operands[1], 1, 0, DImode);
972 operands[5] = operand_subword (operands[1], 0, 0, DImode);
976 [(set (match_operand:DI 0 "register_operand" "")
977 (match_operand:DI 1 "memory_operand" ""))]
978 "!TARGET_64BIT && reload_completed
979 && !FP_REG_P (operands[0])
980 && !s_operand (operands[1], VOIDmode)"
981 [(set (match_dup 0) (match_dup 1))]
983 rtx addr = operand_subword (operands[0], 1, 0, DImode);
984 s390_load_address (addr, XEXP (operands[1], 0));
985 operands[1] = replace_equiv_address (operands[1], addr);
988 (define_expand "reload_outdi"
989 [(parallel [(match_operand:DI 0 "" "")
990 (match_operand:DI 1 "register_operand" "d")
991 (match_operand:SI 2 "register_operand" "=&a")])]
994 gcc_assert (MEM_P (operands[0]));
995 s390_load_address (operands[2], XEXP (operands[0], 0));
996 operands[0] = replace_equiv_address (operands[0], operands[2]);
997 emit_move_insn (operands[0], operands[1]);
1002 [(set (match_operand:DI 0 "register_operand" "")
1003 (mem:DI (match_operand 1 "address_operand" "")))]
1005 && !FP_REG_P (operands[0])
1006 && GET_CODE (operands[1]) == SYMBOL_REF
1007 && CONSTANT_POOL_ADDRESS_P (operands[1])
1008 && get_pool_mode (operands[1]) == DImode
1009 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1010 [(set (match_dup 0) (match_dup 2))]
1011 "operands[2] = get_pool_constant (operands[1]);")
1013 (define_insn "*la_64"
1014 [(set (match_operand:DI 0 "register_operand" "=d,d")
1015 (match_operand:QI 1 "address_operand" "U,W"))]
1020 [(set_attr "op_type" "RX,RXY")
1021 (set_attr "type" "la")])
1025 [(set (match_operand:DI 0 "register_operand" "")
1026 (match_operand:QI 1 "address_operand" ""))
1027 (clobber (reg:CC 33))])]
1029 && preferred_la_operand_p (operands[1], const0_rtx)"
1030 [(set (match_dup 0) (match_dup 1))]
1034 [(set (match_operand:DI 0 "register_operand" "")
1035 (match_operand:DI 1 "register_operand" ""))
1038 (plus:DI (match_dup 0)
1039 (match_operand:DI 2 "nonmemory_operand" "")))
1040 (clobber (reg:CC 33))])]
1042 && !reg_overlap_mentioned_p (operands[0], operands[2])
1043 && preferred_la_operand_p (operands[1], operands[2])"
1044 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
1047 (define_expand "reload_indi"
1048 [(parallel [(match_operand:DI 0 "register_operand" "=a")
1049 (match_operand:DI 1 "s390_plus_operand" "")
1050 (match_operand:DI 2 "register_operand" "=&a")])]
1053 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1058 ; movsi instruction pattern(s).
1061 (define_expand "movsi"
1062 [(set (match_operand:SI 0 "general_operand" "")
1063 (match_operand:SI 1 "general_operand" ""))]
1066 /* Handle symbolic constants. */
1067 if (!TARGET_64BIT && SYMBOLIC_CONST (operands[1]))
1068 emit_symbolic_move (operands);
1071 (define_insn "*movsi_larl"
1072 [(set (match_operand:SI 0 "register_operand" "=d")
1073 (match_operand:SI 1 "larl_operand" "X"))]
1074 "!TARGET_64BIT && TARGET_CPU_ZARCH
1075 && !FP_REG_P (operands[0])"
1077 [(set_attr "op_type" "RIL")
1078 (set_attr "type" "larl")])
1080 (define_insn "*movsi_zarch"
1081 [(set (match_operand:SI 0 "nonimmediate_operand"
1082 "=d,d,d,d,d,d,d,R,T,!*f,!*f,!*f,!R,!T,d,t,Q,t,?Q")
1083 (match_operand:SI 1 "general_operand"
1084 "K,N0HS0,N1HS0,L,d,R,T,d,d,*f,R,T,*f,*f,t,d,t,Q,?Q"))]
1106 [(set_attr "op_type" "RI,RI,RI,RXY,RR,RX,RXY,RX,RXY,
1107 RR,RX,RXY,RX,RXY,RRE,RRE,RS,RS,SS")
1108 (set_attr "type" "*,*,*,la,lr,load,load,store,store,
1109 floads,floads,floads,fstores,fstores,*,*,*,*,*")])
1111 (define_insn "*movsi_esa"
1112 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!R,d,t,Q,t,?Q")
1113 (match_operand:SI 1 "general_operand" "K,d,R,d,*f,R,*f,t,d,t,Q,?Q"))]
1128 [(set_attr "op_type" "RI,RR,RX,RX,RR,RX,RX,RRE,RRE,RS,RS,SS")
1129 (set_attr "type" "*,lr,load,store,floads,floads,fstores,*,*,*,*,*")])
1132 [(set (match_operand:SI 0 "register_operand" "")
1133 (mem:SI (match_operand 1 "address_operand" "")))]
1134 "!FP_REG_P (operands[0])
1135 && GET_CODE (operands[1]) == SYMBOL_REF
1136 && CONSTANT_POOL_ADDRESS_P (operands[1])
1137 && get_pool_mode (operands[1]) == SImode
1138 && legitimate_reload_constant_p (get_pool_constant (operands[1]))"
1139 [(set (match_dup 0) (match_dup 2))]
1140 "operands[2] = get_pool_constant (operands[1]);")
1142 (define_insn "*la_31"
1143 [(set (match_operand:SI 0 "register_operand" "=d,d")
1144 (match_operand:QI 1 "address_operand" "U,W"))]
1145 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])"
1149 [(set_attr "op_type" "RX,RXY")
1150 (set_attr "type" "la")])
1154 [(set (match_operand:SI 0 "register_operand" "")
1155 (match_operand:QI 1 "address_operand" ""))
1156 (clobber (reg:CC 33))])]
1158 && preferred_la_operand_p (operands[1], const0_rtx)"
1159 [(set (match_dup 0) (match_dup 1))]
1163 [(set (match_operand:SI 0 "register_operand" "")
1164 (match_operand:SI 1 "register_operand" ""))
1167 (plus:SI (match_dup 0)
1168 (match_operand:SI 2 "nonmemory_operand" "")))
1169 (clobber (reg:CC 33))])]
1171 && !reg_overlap_mentioned_p (operands[0], operands[2])
1172 && preferred_la_operand_p (operands[1], operands[2])"
1173 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
1176 (define_insn "*la_31_and"
1177 [(set (match_operand:SI 0 "register_operand" "=d,d")
1178 (and:SI (match_operand:QI 1 "address_operand" "U,W")
1179 (const_int 2147483647)))]
1184 [(set_attr "op_type" "RX,RXY")
1185 (set_attr "type" "la")])
1187 (define_insn_and_split "*la_31_and_cc"
1188 [(set (match_operand:SI 0 "register_operand" "=d")
1189 (and:SI (match_operand:QI 1 "address_operand" "p")
1190 (const_int 2147483647)))
1191 (clobber (reg:CC 33))]
1194 "&& reload_completed"
1196 (and:SI (match_dup 1) (const_int 2147483647)))]
1198 [(set_attr "op_type" "RX")
1199 (set_attr "type" "la")])
1201 (define_insn "force_la_31"
1202 [(set (match_operand:SI 0 "register_operand" "=d,d")
1203 (match_operand:QI 1 "address_operand" "U,W"))
1204 (use (const_int 0))]
1209 [(set_attr "op_type" "RX")
1210 (set_attr "type" "la")])
1212 (define_expand "reload_insi"
1213 [(parallel [(match_operand:SI 0 "register_operand" "=a")
1214 (match_operand:SI 1 "s390_plus_operand" "")
1215 (match_operand:SI 2 "register_operand" "=&a")])]
1218 s390_expand_plus_operand (operands[0], operands[1], operands[2]);
1223 ; movhi instruction pattern(s).
1226 (define_expand "movhi"
1227 [(set (match_operand:HI 0 "nonimmediate_operand" "")
1228 (match_operand:HI 1 "general_operand" ""))]
1231 /* Make it explicit that loading a register from memory
1232 always sign-extends (at least) to SImode. */
1233 if (optimize && !no_new_pseudos
1234 && register_operand (operands[0], VOIDmode)
1235 && GET_CODE (operands[1]) == MEM)
1237 rtx tmp = gen_reg_rtx (SImode);
1238 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
1239 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1240 operands[1] = gen_lowpart (HImode, tmp);
1244 (define_insn "*movhi"
1245 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,T,?Q")
1246 (match_operand:HI 1 "general_operand" "d,n,R,T,d,d,?Q"))]
1256 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SS")
1257 (set_attr "type" "lr,*,*,*,store,store,*")])
1260 [(set (match_operand:HI 0 "register_operand" "")
1261 (mem:HI (match_operand 1 "address_operand" "")))]
1262 "GET_CODE (operands[1]) == SYMBOL_REF
1263 && CONSTANT_POOL_ADDRESS_P (operands[1])
1264 && get_pool_mode (operands[1]) == HImode
1265 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1266 [(set (match_dup 0) (match_dup 2))]
1267 "operands[2] = get_pool_constant (operands[1]);")
1270 ; movqi instruction pattern(s).
1273 (define_expand "movqi"
1274 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1275 (match_operand:QI 1 "general_operand" ""))]
1278 /* On z/Architecture, zero-extending from memory to register
1279 is just as fast as a QImode load. */
1280 if (TARGET_ZARCH && optimize && !no_new_pseudos
1281 && register_operand (operands[0], VOIDmode)
1282 && GET_CODE (operands[1]) == MEM)
1284 rtx tmp = gen_reg_rtx (word_mode);
1285 rtx ext = gen_rtx_ZERO_EXTEND (word_mode, operands[1]);
1286 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext));
1287 operands[1] = gen_lowpart (QImode, tmp);
1291 (define_insn "*movqi"
1292 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q")
1293 (match_operand:QI 1 "general_operand" "d,n,R,T,d,d,n,n,?Q"))]
1305 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS")
1306 (set_attr "type" "lr,*,*,*,store,store,store,store,*")])
1309 [(set (match_operand:QI 0 "nonimmediate_operand" "")
1310 (mem:QI (match_operand 1 "address_operand" "")))]
1311 "GET_CODE (operands[1]) == SYMBOL_REF
1312 && CONSTANT_POOL_ADDRESS_P (operands[1])
1313 && get_pool_mode (operands[1]) == QImode
1314 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
1315 [(set (match_dup 0) (match_dup 2))]
1316 "operands[2] = get_pool_constant (operands[1]);")
1319 ; movstrictqi instruction pattern(s).
1322 (define_insn "*movstrictqi"
1323 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d"))
1324 (match_operand:QI 1 "memory_operand" "R,T"))]
1329 [(set_attr "op_type" "RX,RXY")])
1332 ; movstricthi instruction pattern(s).
1335 (define_insn "*movstricthi"
1336 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d"))
1337 (match_operand:HI 1 "memory_operand" "Q,S"))
1338 (clobber (reg:CC 33))]
1343 [(set_attr "op_type" "RS,RSY")])
1346 ; movstrictsi instruction pattern(s).
1349 (define_insn "movstrictsi"
1350 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d"))
1351 (match_operand:SI 1 "general_operand" "d,R,T,t"))]
1358 [(set_attr "op_type" "RR,RX,RXY,RRE")
1359 (set_attr "type" "lr,load,load,*")])
1362 ; movdf instruction pattern(s).
1365 (define_expand "movdf"
1366 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1367 (match_operand:DF 1 "general_operand" ""))]
1371 (define_insn "*movdf_64"
1372 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,m,?Q")
1373 (match_operand:DF 1 "general_operand" "f,R,T,f,f,d,m,d,?Q"))]
1385 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RRE,RXY,RXY,SS")
1386 (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lr,load,store,*")])
1388 (define_insn "*movdf_31"
1389 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,T,d,Q,d,o,Q")
1390 (match_operand:DF 1 "general_operand" "f,R,T,f,f,Q,d,dKm,d,Q"))]
1403 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RS,RS,*,*,SS")
1404 (set_attr "type" "floadd,floadd,floadd,fstored,fstored,lm,stm,*,*,*")])
1407 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1408 (match_operand:DF 1 "general_operand" ""))]
1409 "!TARGET_64BIT && reload_completed
1410 && s390_split_ok_p (operands[0], operands[1], DFmode, 0)"
1411 [(set (match_dup 2) (match_dup 4))
1412 (set (match_dup 3) (match_dup 5))]
1414 operands[2] = operand_subword (operands[0], 0, 0, DFmode);
1415 operands[3] = operand_subword (operands[0], 1, 0, DFmode);
1416 operands[4] = operand_subword (operands[1], 0, 0, DFmode);
1417 operands[5] = operand_subword (operands[1], 1, 0, DFmode);
1421 [(set (match_operand:DF 0 "nonimmediate_operand" "")
1422 (match_operand:DF 1 "general_operand" ""))]
1423 "!TARGET_64BIT && reload_completed
1424 && s390_split_ok_p (operands[0], operands[1], DFmode, 1)"
1425 [(set (match_dup 2) (match_dup 4))
1426 (set (match_dup 3) (match_dup 5))]
1428 operands[2] = operand_subword (operands[0], 1, 0, DFmode);
1429 operands[3] = operand_subword (operands[0], 0, 0, DFmode);
1430 operands[4] = operand_subword (operands[1], 1, 0, DFmode);
1431 operands[5] = operand_subword (operands[1], 0, 0, DFmode);
1435 [(set (match_operand:DF 0 "register_operand" "")
1436 (match_operand:DF 1 "memory_operand" ""))]
1437 "!TARGET_64BIT && reload_completed
1438 && !FP_REG_P (operands[0])
1439 && !s_operand (operands[1], VOIDmode)"
1440 [(set (match_dup 0) (match_dup 1))]
1442 rtx addr = operand_subword (operands[0], 1, 0, DFmode);
1443 s390_load_address (addr, XEXP (operands[1], 0));
1444 operands[1] = replace_equiv_address (operands[1], addr);
1447 (define_expand "reload_outdf"
1448 [(parallel [(match_operand:DF 0 "" "")
1449 (match_operand:DF 1 "register_operand" "d")
1450 (match_operand:SI 2 "register_operand" "=&a")])]
1453 gcc_assert (MEM_P (operands[0]));
1454 s390_load_address (operands[2], XEXP (operands[0], 0));
1455 operands[0] = replace_equiv_address (operands[0], operands[2]);
1456 emit_move_insn (operands[0], operands[1]);
1461 ; movsf instruction pattern(s).
1464 (define_insn "movsf"
1465 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,R,T,d,d,d,R,T,?Q")
1466 (match_operand:SF 1 "general_operand" "f,R,T,f,f,d,R,T,d,d,?Q"))]
1480 [(set_attr "op_type" "RR,RX,RXY,RX,RXY,RR,RX,RXY,RX,RXY,SS")
1481 (set_attr "type" "floads,floads,floads,fstores,fstores,
1482 lr,load,load,store,store,*")])
1485 ; movcc instruction pattern
1488 (define_insn "movcc"
1489 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T")
1490 (match_operand:CC 1 "nonimmediate_operand" "d,d,c,R,T,d,d"))]
1500 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
1501 (set_attr "type" "lr,*,*,store,store,load,load")])
1504 ; Block move (MVC) patterns.
1508 [(set (match_operand:BLK 0 "memory_operand" "=Q")
1509 (match_operand:BLK 1 "memory_operand" "Q"))
1510 (use (match_operand 2 "const_int_operand" "n"))]
1511 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
1512 "mvc\t%O0(%2,%R0),%S1"
1513 [(set_attr "op_type" "SS")])
1516 [(set (match_operand 0 "memory_operand" "")
1517 (match_operand 1 "memory_operand" ""))]
1519 && GET_MODE (operands[0]) == GET_MODE (operands[1])
1520 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
1522 [(set (match_dup 0) (match_dup 1))
1523 (use (match_dup 2))])]
1525 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
1526 operands[0] = adjust_address (operands[0], BLKmode, 0);
1527 operands[1] = adjust_address (operands[1], BLKmode, 0);
1532 [(set (match_operand:BLK 0 "memory_operand" "")
1533 (match_operand:BLK 1 "memory_operand" ""))
1534 (use (match_operand 2 "const_int_operand" ""))])
1536 [(set (match_operand:BLK 3 "memory_operand" "")
1537 (match_operand:BLK 4 "memory_operand" ""))
1538 (use (match_operand 5 "const_int_operand" ""))])]
1539 "s390_offset_p (operands[0], operands[3], operands[2])
1540 && s390_offset_p (operands[1], operands[4], operands[2])
1541 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
1543 [(set (match_dup 6) (match_dup 7))
1544 (use (match_dup 8))])]
1545 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
1546 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
1547 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
1551 ; load_multiple pattern(s).
1553 ; ??? Due to reload problems with replacing registers inside match_parallel
1554 ; we currently support load_multiple/store_multiple only after reload.
1557 (define_expand "load_multiple"
1558 [(match_par_dup 3 [(set (match_operand 0 "" "")
1559 (match_operand 1 "" ""))
1560 (use (match_operand 2 "" ""))])]
1563 enum machine_mode mode;
1569 /* Support only loading a constant number of fixed-point registers from
1570 memory and only bother with this if more than two */
1571 if (GET_CODE (operands[2]) != CONST_INT
1572 || INTVAL (operands[2]) < 2
1573 || INTVAL (operands[2]) > 16
1574 || GET_CODE (operands[1]) != MEM
1575 || GET_CODE (operands[0]) != REG
1576 || REGNO (operands[0]) >= 16)
1579 count = INTVAL (operands[2]);
1580 regno = REGNO (operands[0]);
1581 mode = GET_MODE (operands[0]);
1582 if (mode != SImode && mode != word_mode)
1585 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1588 if (GET_CODE (XEXP (operands[1], 0)) == REG)
1590 from = XEXP (operands[1], 0);
1593 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
1594 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
1595 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
1597 from = XEXP (XEXP (operands[1], 0), 0);
1598 off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
1605 from = force_reg (Pmode, XEXP (operands[1], 0));
1609 for (i = 0; i < count; i++)
1610 XVECEXP (operands[3], 0, i)
1611 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i),
1612 change_address (operands[1], mode,
1613 plus_constant (from, off + i * GET_MODE_SIZE (mode))));
1616 (define_insn "*load_multiple_di"
1617 [(match_parallel 0 "load_multiple_operation"
1618 [(set (match_operand:DI 1 "register_operand" "=r")
1619 (match_operand:DI 2 "s_operand" "QS"))])]
1620 "reload_completed && word_mode == DImode"
1622 int words = XVECLEN (operands[0], 0);
1623 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1);
1624 return "lmg\t%1,%0,%S2";
1626 [(set_attr "op_type" "RSY")
1627 (set_attr "type" "lm")])
1629 (define_insn "*load_multiple_si"
1630 [(match_parallel 0 "load_multiple_operation"
1631 [(set (match_operand:SI 1 "register_operand" "=r,r")
1632 (match_operand:SI 2 "s_operand" "Q,S"))])]
1635 int words = XVECLEN (operands[0], 0);
1636 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1);
1637 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2";
1639 [(set_attr "op_type" "RS,RSY")
1640 (set_attr "type" "lm")])
1643 ; store multiple pattern(s).
1646 (define_expand "store_multiple"
1647 [(match_par_dup 3 [(set (match_operand 0 "" "")
1648 (match_operand 1 "" ""))
1649 (use (match_operand 2 "" ""))])]
1652 enum machine_mode mode;
1658 /* Support only storing a constant number of fixed-point registers to
1659 memory and only bother with this if more than two. */
1660 if (GET_CODE (operands[2]) != CONST_INT
1661 || INTVAL (operands[2]) < 2
1662 || INTVAL (operands[2]) > 16
1663 || GET_CODE (operands[0]) != MEM
1664 || GET_CODE (operands[1]) != REG
1665 || REGNO (operands[1]) >= 16)
1668 count = INTVAL (operands[2]);
1669 regno = REGNO (operands[1]);
1670 mode = GET_MODE (operands[1]);
1671 if (mode != SImode && mode != word_mode)
1674 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
1678 if (GET_CODE (XEXP (operands[0], 0)) == REG)
1680 to = XEXP (operands[0], 0);
1683 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
1684 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
1685 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
1687 to = XEXP (XEXP (operands[0], 0), 0);
1688 off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
1695 to = force_reg (Pmode, XEXP (operands[0], 0));
1699 for (i = 0; i < count; i++)
1700 XVECEXP (operands[3], 0, i)
1701 = gen_rtx_SET (VOIDmode,
1702 change_address (operands[0], mode,
1703 plus_constant (to, off + i * GET_MODE_SIZE (mode))),
1704 gen_rtx_REG (mode, regno + i));
1707 (define_insn "*store_multiple_di"
1708 [(match_parallel 0 "store_multiple_operation"
1709 [(set (match_operand:DI 1 "s_operand" "=QS")
1710 (match_operand:DI 2 "register_operand" "r"))])]
1711 "reload_completed && word_mode == DImode"
1713 int words = XVECLEN (operands[0], 0);
1714 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1);
1715 return "stmg\t%2,%0,%S1";
1717 [(set_attr "op_type" "RSY")
1718 (set_attr "type" "stm")])
1721 (define_insn "*store_multiple_si"
1722 [(match_parallel 0 "store_multiple_operation"
1723 [(set (match_operand:SI 1 "s_operand" "=Q,S")
1724 (match_operand:SI 2 "register_operand" "r,r"))])]
1727 int words = XVECLEN (operands[0], 0);
1728 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1);
1729 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1";
1731 [(set_attr "op_type" "RS,RSY")
1732 (set_attr "type" "stm")])
1735 ;; String instructions.
1738 (define_insn "*execute"
1739 [(match_parallel 0 ""
1740 [(unspec [(match_operand 1 "register_operand" "a")
1741 (match_operand:BLK 2 "memory_operand" "R")
1742 (match_operand 3 "" "")] UNSPEC_EXECUTE)])]
1743 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT
1744 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD"
1746 [(set_attr "op_type" "RX")
1747 (set_attr "type" "cs")])
1751 ; strlenM instruction pattern(s).
1754 (define_expand "strlendi"
1755 [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" ""))
1758 (unspec:DI [(const_int 0)
1759 (match_operand:BLK 1 "memory_operand" "")
1761 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
1762 (clobber (scratch:DI))
1763 (clobber (reg:CC 33))])
1765 [(set (match_operand:DI 0 "register_operand" "")
1766 (minus:DI (match_dup 4) (match_dup 5)))
1767 (clobber (reg:CC 33))])]
1770 operands[4] = gen_reg_rtx (DImode);
1771 operands[5] = gen_reg_rtx (DImode);
1772 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
1773 operands[1] = replace_equiv_address (operands[1], operands[5]);
1776 (define_insn "*strlendi"
1777 [(set (match_operand:DI 0 "register_operand" "=a")
1778 (unspec:DI [(match_operand:DI 2 "general_operand" "0")
1779 (mem:BLK (match_operand:DI 3 "register_operand" "1"))
1781 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
1782 (clobber (match_scratch:DI 1 "=a"))
1783 (clobber (reg:CC 33))]
1785 "srst\t%0,%1\;jo\t.-4"
1786 [(set_attr "length" "8")
1787 (set_attr "type" "vs")])
1789 (define_expand "strlensi"
1790 [(set (reg:QI 0) (match_operand:QI 2 "immediate_operand" ""))
1793 (unspec:SI [(const_int 0)
1794 (match_operand:BLK 1 "memory_operand" "")
1796 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST))
1797 (clobber (scratch:SI))
1798 (clobber (reg:CC 33))])
1800 [(set (match_operand:SI 0 "register_operand" "")
1801 (minus:SI (match_dup 4) (match_dup 5)))
1802 (clobber (reg:CC 33))])]
1805 operands[4] = gen_reg_rtx (SImode);
1806 operands[5] = gen_reg_rtx (SImode);
1807 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX));
1808 operands[1] = replace_equiv_address (operands[1], operands[5]);
1811 (define_insn "*strlensi"
1812 [(set (match_operand:SI 0 "register_operand" "=a")
1813 (unspec:SI [(match_operand:SI 2 "general_operand" "0")
1814 (mem:BLK (match_operand:SI 3 "register_operand" "1"))
1816 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST))
1817 (clobber (match_scratch:SI 1 "=a"))
1818 (clobber (reg:CC 33))]
1820 "srst\t%0,%1\;jo\t.-4"
1821 [(set_attr "length" "8")
1822 (set_attr "type" "vs")])
1825 ; movmemM instruction pattern(s).
1828 (define_expand "movmemdi"
1829 [(set (match_operand:BLK 0 "memory_operand" "")
1830 (match_operand:BLK 1 "memory_operand" ""))
1831 (use (match_operand:DI 2 "general_operand" ""))
1832 (match_operand 3 "" "")]
1834 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
1836 (define_expand "movmemsi"
1837 [(set (match_operand:BLK 0 "memory_operand" "")
1838 (match_operand:BLK 1 "memory_operand" ""))
1839 (use (match_operand:SI 2 "general_operand" ""))
1840 (match_operand 3 "" "")]
1842 "s390_expand_movmem (operands[0], operands[1], operands[2]); DONE;")
1844 ; Move a block that is up to 256 bytes in length.
1845 ; The block length is taken as (operands[2] % 256) + 1.
1847 (define_expand "movmem_short"
1849 [(set (match_operand:BLK 0 "memory_operand" "")
1850 (match_operand:BLK 1 "memory_operand" ""))
1851 (use (match_operand 2 "nonmemory_operand" ""))
1852 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1853 (clobber (match_dup 3))])]
1855 "operands[3] = gen_rtx_SCRATCH (Pmode);")
1857 (define_insn "*movmem_short"
1858 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
1859 (match_operand:BLK 1 "memory_operand" "Q,Q,Q"))
1860 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
1861 (use (match_operand 3 "immediate_operand" "X,R,X"))
1862 (clobber (match_scratch 4 "=X,X,&a"))]
1863 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
1864 && GET_MODE (operands[4]) == Pmode"
1866 [(set_attr "type" "cs")])
1869 [(set (match_operand:BLK 0 "memory_operand" "")
1870 (match_operand:BLK 1 "memory_operand" ""))
1871 (use (match_operand 2 "const_int_operand" ""))
1872 (use (match_operand 3 "immediate_operand" ""))
1873 (clobber (scratch))]
1876 [(set (match_dup 0) (match_dup 1))
1877 (use (match_dup 2))])]
1878 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
1881 [(set (match_operand:BLK 0 "memory_operand" "")
1882 (match_operand:BLK 1 "memory_operand" ""))
1883 (use (match_operand 2 "register_operand" ""))
1884 (use (match_operand 3 "memory_operand" ""))
1885 (clobber (scratch))]
1888 [(unspec [(match_dup 2) (match_dup 3)
1889 (const_int 0)] UNSPEC_EXECUTE)
1890 (set (match_dup 0) (match_dup 1))
1891 (use (const_int 1))])]
1895 [(set (match_operand:BLK 0 "memory_operand" "")
1896 (match_operand:BLK 1 "memory_operand" ""))
1897 (use (match_operand 2 "register_operand" ""))
1898 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1899 (clobber (match_operand 3 "register_operand" ""))]
1900 "reload_completed && TARGET_CPU_ZARCH"
1901 [(set (match_dup 3) (label_ref (match_dup 4)))
1903 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
1904 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
1905 (set (match_dup 0) (match_dup 1))
1906 (use (const_int 1))])]
1907 "operands[4] = gen_label_rtx ();")
1909 ; Move a block of arbitrary length.
1911 (define_expand "movmem_long"
1913 [(clobber (match_dup 2))
1914 (clobber (match_dup 3))
1915 (set (match_operand:BLK 0 "memory_operand" "")
1916 (match_operand:BLK 1 "memory_operand" ""))
1917 (use (match_operand 2 "general_operand" ""))
1919 (clobber (reg:CC 33))])]
1922 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
1923 rtx reg0 = gen_reg_rtx (dword_mode);
1924 rtx reg1 = gen_reg_rtx (dword_mode);
1925 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
1926 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
1927 rtx len0 = gen_lowpart (Pmode, reg0);
1928 rtx len1 = gen_lowpart (Pmode, reg1);
1930 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
1931 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
1932 emit_move_insn (len0, operands[2]);
1934 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
1935 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
1936 emit_move_insn (len1, operands[2]);
1938 operands[0] = replace_equiv_address_nv (operands[0], addr0);
1939 operands[1] = replace_equiv_address_nv (operands[1], addr1);
1944 (define_insn "*movmem_long_64"
1945 [(clobber (match_operand:TI 0 "register_operand" "=d"))
1946 (clobber (match_operand:TI 1 "register_operand" "=d"))
1947 (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
1948 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0)))
1951 (clobber (reg:CC 33))]
1953 "mvcle\t%0,%1,0\;jo\t.-4"
1954 [(set_attr "length" "8")
1955 (set_attr "type" "vs")])
1957 (define_insn "*movmem_long_31"
1958 [(clobber (match_operand:DI 0 "register_operand" "=d"))
1959 (clobber (match_operand:DI 1 "register_operand" "=d"))
1960 (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
1961 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0)))
1964 (clobber (reg:CC 33))]
1966 "mvcle\t%0,%1,0\;jo\t.-4"
1967 [(set_attr "length" "8")
1968 (set_attr "type" "vs")])
1971 ; clrmemM instruction pattern(s).
1974 (define_expand "clrmemdi"
1975 [(set (match_operand:BLK 0 "memory_operand" "")
1977 (use (match_operand:DI 1 "general_operand" ""))
1978 (match_operand 2 "" "")]
1980 "s390_expand_clrmem (operands[0], operands[1]); DONE;")
1982 (define_expand "clrmemsi"
1983 [(set (match_operand:BLK 0 "memory_operand" "")
1985 (use (match_operand:SI 1 "general_operand" ""))
1986 (match_operand 2 "" "")]
1988 "s390_expand_clrmem (operands[0], operands[1]); DONE;")
1990 ; Clear a block that is up to 256 bytes in length.
1991 ; The block length is taken as (operands[1] % 256) + 1.
1993 (define_expand "clrmem_short"
1995 [(set (match_operand:BLK 0 "memory_operand" "")
1997 (use (match_operand 1 "nonmemory_operand" ""))
1998 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
1999 (clobber (match_dup 2))
2000 (clobber (reg:CC 33))])]
2002 "operands[2] = gen_rtx_SCRATCH (Pmode);")
2004 (define_insn "*clrmem_short"
2005 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q")
2007 (use (match_operand 1 "nonmemory_operand" "n,a,a"))
2008 (use (match_operand 2 "immediate_operand" "X,R,X"))
2009 (clobber (match_scratch 3 "=X,X,&a"))
2010 (clobber (reg:CC 33))]
2011 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)
2012 && GET_MODE (operands[3]) == Pmode"
2014 [(set_attr "type" "cs")])
2017 [(set (match_operand:BLK 0 "memory_operand" "")
2019 (use (match_operand 1 "const_int_operand" ""))
2020 (use (match_operand 2 "immediate_operand" ""))
2022 (clobber (reg:CC 33))]
2025 [(set (match_dup 0) (const_int 0))
2027 (clobber (reg:CC 33))])]
2028 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);")
2031 [(set (match_operand:BLK 0 "memory_operand" "")
2033 (use (match_operand 1 "register_operand" ""))
2034 (use (match_operand 2 "memory_operand" ""))
2036 (clobber (reg:CC 33))]
2039 [(unspec [(match_dup 1) (match_dup 2)
2040 (const_int 0)] UNSPEC_EXECUTE)
2041 (set (match_dup 0) (const_int 0))
2043 (clobber (reg:CC 33))])]
2047 [(set (match_operand:BLK 0 "memory_operand" "")
2049 (use (match_operand 1 "register_operand" ""))
2050 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2051 (clobber (match_operand 2 "register_operand" ""))
2052 (clobber (reg:CC 33))]
2053 "reload_completed && TARGET_CPU_ZARCH"
2054 [(set (match_dup 2) (label_ref (match_dup 3)))
2056 [(unspec [(match_dup 1) (mem:BLK (match_dup 2))
2057 (label_ref (match_dup 3))] UNSPEC_EXECUTE)
2058 (set (match_dup 0) (const_int 0))
2060 (clobber (reg:CC 33))])]
2061 "operands[3] = gen_label_rtx ();")
2063 ; Clear a block of arbitrary length.
2065 (define_expand "clrmem_long"
2067 [(clobber (match_dup 1))
2068 (set (match_operand:BLK 0 "memory_operand" "")
2070 (use (match_operand 1 "general_operand" ""))
2072 (clobber (reg:CC 33))])]
2075 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2076 rtx reg0 = gen_reg_rtx (dword_mode);
2077 rtx reg1 = gen_reg_rtx (dword_mode);
2078 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2079 rtx len0 = gen_lowpart (Pmode, reg0);
2081 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2082 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2083 emit_move_insn (len0, operands[1]);
2085 emit_move_insn (reg1, const0_rtx);
2087 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2092 (define_insn "*clrmem_long_64"
2093 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2094 (set (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2097 (use (match_operand:TI 1 "register_operand" "d"))
2098 (clobber (reg:CC 33))]
2100 "mvcle\t%0,%1,0\;jo\t.-4"
2101 [(set_attr "length" "8")
2102 (set_attr "type" "vs")])
2104 (define_insn "*clrmem_long_31"
2105 [(clobber (match_operand:DI 0 "register_operand" "=d"))
2106 (set (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2109 (use (match_operand:DI 1 "register_operand" "d"))
2110 (clobber (reg:CC 33))]
2112 "mvcle\t%0,%1,0\;jo\t.-4"
2113 [(set_attr "length" "8")
2114 (set_attr "type" "vs")])
2117 ; cmpmemM instruction pattern(s).
2120 (define_expand "cmpmemsi"
2121 [(set (match_operand:SI 0 "register_operand" "")
2122 (compare:SI (match_operand:BLK 1 "memory_operand" "")
2123 (match_operand:BLK 2 "memory_operand" "") ) )
2124 (use (match_operand:SI 3 "general_operand" ""))
2125 (use (match_operand:SI 4 "" ""))]
2127 "s390_expand_cmpmem (operands[0], operands[1],
2128 operands[2], operands[3]); DONE;")
2130 ; Compare a block that is up to 256 bytes in length.
2131 ; The block length is taken as (operands[2] % 256) + 1.
2133 (define_expand "cmpmem_short"
2136 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2137 (match_operand:BLK 1 "memory_operand" "")))
2138 (use (match_operand 2 "nonmemory_operand" ""))
2139 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2140 (clobber (match_dup 3))])]
2142 "operands[3] = gen_rtx_SCRATCH (Pmode);")
2144 (define_insn "*cmpmem_short"
2146 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q")
2147 (match_operand:BLK 1 "memory_operand" "Q,Q,Q")))
2148 (use (match_operand 2 "nonmemory_operand" "n,a,a"))
2149 (use (match_operand 3 "immediate_operand" "X,R,X"))
2150 (clobber (match_scratch 4 "=X,X,&a"))]
2151 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)
2152 && GET_MODE (operands[4]) == Pmode"
2154 [(set_attr "type" "cs")])
2158 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2159 (match_operand:BLK 1 "memory_operand" "")))
2160 (use (match_operand 2 "const_int_operand" ""))
2161 (use (match_operand 3 "immediate_operand" ""))
2162 (clobber (scratch))]
2165 [(set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1)))
2166 (use (match_dup 2))])]
2167 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);")
2171 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2172 (match_operand:BLK 1 "memory_operand" "")))
2173 (use (match_operand 2 "register_operand" ""))
2174 (use (match_operand 3 "memory_operand" ""))
2175 (clobber (scratch))]
2178 [(unspec [(match_dup 2) (match_dup 3)
2179 (const_int 0)] UNSPEC_EXECUTE)
2180 (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1)))
2181 (use (const_int 1))])]
2186 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2187 (match_operand:BLK 1 "memory_operand" "")))
2188 (use (match_operand 2 "register_operand" ""))
2189 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN)))
2190 (clobber (match_operand 3 "register_operand" ""))]
2191 "reload_completed && TARGET_CPU_ZARCH"
2192 [(set (match_dup 3) (label_ref (match_dup 4)))
2194 [(unspec [(match_dup 2) (mem:BLK (match_dup 3))
2195 (label_ref (match_dup 4))] UNSPEC_EXECUTE)
2196 (set (reg:CCU 33) (compare:CCU (match_dup 0) (match_dup 1)))
2197 (use (const_int 1))])]
2198 "operands[4] = gen_label_rtx ();")
2200 ; Compare a block of arbitrary length.
2202 (define_expand "cmpmem_long"
2204 [(clobber (match_dup 2))
2205 (clobber (match_dup 3))
2207 (compare:CCU (match_operand:BLK 0 "memory_operand" "")
2208 (match_operand:BLK 1 "memory_operand" "")))
2209 (use (match_operand 2 "general_operand" ""))
2210 (use (match_dup 3))])]
2213 enum machine_mode dword_mode = word_mode == DImode ? TImode : DImode;
2214 rtx reg0 = gen_reg_rtx (dword_mode);
2215 rtx reg1 = gen_reg_rtx (dword_mode);
2216 rtx addr0 = gen_lowpart (Pmode, gen_highpart (word_mode, reg0));
2217 rtx addr1 = gen_lowpart (Pmode, gen_highpart (word_mode, reg1));
2218 rtx len0 = gen_lowpart (Pmode, reg0);
2219 rtx len1 = gen_lowpart (Pmode, reg1);
2221 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg0));
2222 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX));
2223 emit_move_insn (len0, operands[2]);
2225 emit_insn (gen_rtx_CLOBBER (VOIDmode, reg1));
2226 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX));
2227 emit_move_insn (len1, operands[2]);
2229 operands[0] = replace_equiv_address_nv (operands[0], addr0);
2230 operands[1] = replace_equiv_address_nv (operands[1], addr1);
2235 (define_insn "*cmpmem_long_64"
2236 [(clobber (match_operand:TI 0 "register_operand" "=d"))
2237 (clobber (match_operand:TI 1 "register_operand" "=d"))
2239 (compare:CCU (mem:BLK (subreg:DI (match_operand:TI 2 "register_operand" "0") 0))
2240 (mem:BLK (subreg:DI (match_operand:TI 3 "register_operand" "1") 0))))
2242 (use (match_dup 3))]
2244 "clcle\t%0,%1,0\;jo\t.-4"
2245 [(set_attr "length" "8")
2246 (set_attr "type" "vs")])
2248 (define_insn "*cmpmem_long_31"
2249 [(clobber (match_operand:DI 0 "register_operand" "=d"))
2250 (clobber (match_operand:DI 1 "register_operand" "=d"))
2252 (compare:CCU (mem:BLK (subreg:SI (match_operand:DI 2 "register_operand" "0") 0))
2253 (mem:BLK (subreg:SI (match_operand:DI 3 "register_operand" "1") 0))))
2255 (use (match_dup 3))]
2257 "clcle\t%0,%1,0\;jo\t.-4"
2258 [(set_attr "length" "8")
2259 (set_attr "type" "vs")])
2261 ; Convert CCUmode condition code to integer.
2262 ; Result is zero if EQ, positive if LTU, negative if GTU.
2264 (define_insn_and_split "cmpint"
2265 [(set (match_operand:SI 0 "register_operand" "=d")
2266 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2268 (clobber (reg:CC 33))]
2272 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2274 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))
2275 (clobber (reg:CC 33))])])
2277 (define_insn_and_split "*cmpint_cc"
2279 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2282 (set (match_operand:SI 0 "register_operand" "=d")
2283 (unspec:SI [(match_dup 1)] UNSPEC_CMPINT))]
2284 "s390_match_ccmode (insn, CCSmode)"
2286 "&& reload_completed"
2287 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2)))
2289 [(set (match_dup 2) (match_dup 3))
2290 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])]
2292 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30));
2293 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2294 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2297 (define_insn_and_split "*cmpint_sign"
2298 [(set (match_operand:DI 0 "register_operand" "=d")
2299 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2301 (clobber (reg:CC 33))]
2304 "&& reload_completed"
2305 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2307 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))
2308 (clobber (reg:CC 33))])])
2310 (define_insn_and_split "*cmpint_sign_cc"
2312 (compare (ashiftrt:DI (ashift:DI (subreg:DI
2313 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")]
2315 (const_int 32)) (const_int 32))
2317 (set (match_operand:DI 0 "register_operand" "=d")
2318 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_CMPINT)))]
2319 "s390_match_ccmode (insn, CCSmode) && TARGET_64BIT"
2321 "&& reload_completed"
2322 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34)))
2324 [(set (match_dup 2) (match_dup 3))
2325 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])]
2327 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62));
2328 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0));
2329 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx);
2334 ;;- Conversion instructions.
2337 (define_insn "*sethighqisi"
2338 [(set (match_operand:SI 0 "register_operand" "=d,d")
2339 (unspec:SI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2340 (clobber (reg:CC 33))]
2345 [(set_attr "op_type" "RS,RSY")])
2347 (define_insn "*sethighhisi"
2348 [(set (match_operand:SI 0 "register_operand" "=d,d")
2349 (unspec:SI [(match_operand:HI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2350 (clobber (reg:CC 33))]
2355 [(set_attr "op_type" "RS,RSY")])
2357 (define_insn "*sethighqidi_64"
2358 [(set (match_operand:DI 0 "register_operand" "=d")
2359 (unspec:DI [(match_operand:QI 1 "s_operand" "QS")] UNSPEC_SETHIGH))
2360 (clobber (reg:CC 33))]
2363 [(set_attr "op_type" "RSY")])
2365 (define_insn "*sethighqidi_31"
2366 [(set (match_operand:DI 0 "register_operand" "=d,d")
2367 (unspec:DI [(match_operand:QI 1 "s_operand" "Q,S")] UNSPEC_SETHIGH))
2368 (clobber (reg:CC 33))]
2373 [(set_attr "op_type" "RS,RSY")])
2375 (define_insn_and_split "*extractqi"
2376 [(set (match_operand:SI 0 "register_operand" "=d")
2377 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2378 (match_operand 2 "const_int_operand" "n")
2380 (clobber (reg:CC 33))]
2382 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 8"
2384 "&& reload_completed"
2386 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2387 (clobber (reg:CC 33))])
2388 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2390 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2391 operands[1] = change_address (operands[1], QImode, 0);
2394 (define_insn_and_split "*extracthi"
2395 [(set (match_operand:SI 0 "register_operand" "=d")
2396 (zero_extract:SI (match_operand:QI 1 "s_operand" "Q")
2397 (match_operand 2 "const_int_operand" "n")
2399 (clobber (reg:CC 33))]
2401 && INTVAL (operands[2]) >= 8 && INTVAL (operands[2]) < 16"
2403 "&& reload_completed"
2405 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2406 (clobber (reg:CC 33))])
2407 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
2409 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
2410 operands[1] = change_address (operands[1], HImode, 0);
2414 ; extendsidi2 instruction pattern(s).
2417 (define_expand "extendsidi2"
2418 [(set (match_operand:DI 0 "register_operand" "")
2419 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2425 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2426 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]);
2427 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx);
2428 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32)));
2434 (define_insn "*extendsidi2"
2435 [(set (match_operand:DI 0 "register_operand" "=d,d")
2436 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2441 [(set_attr "op_type" "RRE,RXY")])
2444 ; extendhidi2 instruction pattern(s).
2447 (define_expand "extendhidi2"
2448 [(set (match_operand:DI 0 "register_operand" "")
2449 (sign_extend:DI (match_operand:HI 1 "register_operand" "")))]
2455 rtx tmp = gen_reg_rtx (SImode);
2456 emit_insn (gen_extendhisi2 (tmp, operands[1]));
2457 emit_insn (gen_extendsidi2 (operands[0], tmp));
2462 operands[1] = gen_lowpart (DImode, operands[1]);
2463 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2464 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (48)));
2470 (define_insn "*extendhidi2"
2471 [(set (match_operand:DI 0 "register_operand" "=d")
2472 (sign_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2475 [(set_attr "op_type" "RXY")])
2478 ; extendqidi2 instruction pattern(s).
2481 (define_expand "extendqidi2"
2482 [(set (match_operand:DI 0 "register_operand" "")
2483 (sign_extend:DI (match_operand:QI 1 "register_operand" "")))]
2489 rtx tmp = gen_reg_rtx (SImode);
2490 emit_insn (gen_extendqisi2 (tmp, operands[1]));
2491 emit_insn (gen_extendsidi2 (operands[0], tmp));
2496 operands[1] = gen_lowpart (DImode, operands[1]);
2497 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2498 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (56)));
2504 (define_insn "*extendqidi2"
2505 [(set (match_operand:DI 0 "register_operand" "=d")
2506 (sign_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2507 "TARGET_64BIT && TARGET_LONG_DISPLACEMENT"
2509 [(set_attr "op_type" "RXY")])
2511 (define_insn_and_split "*extendqidi2_short_displ"
2512 [(set (match_operand:DI 0 "register_operand" "=d")
2513 (sign_extend:DI (match_operand:QI 1 "s_operand" "Q")))
2514 (clobber (reg:CC 33))]
2515 "TARGET_64BIT && !TARGET_LONG_DISPLACEMENT"
2517 "&& reload_completed"
2519 [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_SETHIGH))
2520 (clobber (reg:CC 33))])
2522 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 56)))
2523 (clobber (reg:CC 33))])]
2527 ; extendhisi2 instruction pattern(s).
2530 (define_expand "extendhisi2"
2531 [(set (match_operand:SI 0 "register_operand" "")
2532 (sign_extend:SI (match_operand:HI 1 "register_operand" "")))]
2536 operands[1] = gen_lowpart (SImode, operands[1]);
2537 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (16)));
2538 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (16)));
2543 (define_insn "*extendhisi2"
2544 [(set (match_operand:SI 0 "register_operand" "=d,d")
2545 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))]
2550 [(set_attr "op_type" "RX,RXY")])
2553 ; extendqisi2 instruction pattern(s).
2556 (define_expand "extendqisi2"
2557 [(set (match_operand:SI 0 "register_operand" "")
2558 (sign_extend:SI (match_operand:QI 1 "register_operand" "")))]
2562 operands[1] = gen_lowpart (SImode, operands[1]);
2563 emit_insn (gen_ashlsi3 (operands[0], operands[1], GEN_INT (24)));
2564 emit_insn (gen_ashrsi3 (operands[0], operands[0], GEN_INT (24)));
2569 (define_insn "*extendqisi2"
2570 [(set (match_operand:SI 0 "register_operand" "=d")
2571 (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2572 "TARGET_LONG_DISPLACEMENT"
2574 [(set_attr "op_type" "RXY")])
2576 (define_insn_and_split "*extendqisi2_short_displ"
2577 [(set (match_operand:SI 0 "register_operand" "=d")
2578 (sign_extend:SI (match_operand:QI 1 "s_operand" "Q")))
2579 (clobber (reg:CC 33))]
2580 "!TARGET_LONG_DISPLACEMENT"
2582 "&& reload_completed"
2584 [(set (match_dup 0) (unspec:SI [(match_dup 1)] UNSPEC_SETHIGH))
2585 (clobber (reg:CC 33))])
2587 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 24)))
2588 (clobber (reg:CC 33))])]
2592 ; extendqihi2 instruction pattern(s).
2597 ; zero_extendsidi2 instruction pattern(s).
2600 (define_expand "zero_extendsidi2"
2601 [(set (match_operand:DI 0 "register_operand" "")
2602 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
2608 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[0]));
2609 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]);
2610 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
2616 (define_insn "*zero_extendsidi2"
2617 [(set (match_operand:DI 0 "register_operand" "=d,d")
2618 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,m")))]
2623 [(set_attr "op_type" "RRE,RXY")])
2626 ; zero_extendhidi2 instruction pattern(s).
2629 (define_expand "zero_extendhidi2"
2630 [(set (match_operand:DI 0 "register_operand" "")
2631 (zero_extend:DI (match_operand:HI 1 "register_operand" "")))]
2637 rtx tmp = gen_reg_rtx (SImode);
2638 emit_insn (gen_zero_extendhisi2 (tmp, operands[1]));
2639 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2644 operands[1] = gen_lowpart (DImode, operands[1]);
2645 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (48)));
2646 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (48)));
2652 (define_insn "*zero_extendhidi2"
2653 [(set (match_operand:DI 0 "register_operand" "=d")
2654 (zero_extend:DI (match_operand:HI 1 "memory_operand" "m")))]
2657 [(set_attr "op_type" "RXY")])
2660 ; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
2663 (define_insn "*llgt_sisi"
2664 [(set (match_operand:SI 0 "register_operand" "=d,d")
2665 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
2666 (const_int 2147483647)))]
2671 [(set_attr "op_type" "RRE,RXE")])
2674 [(set (match_operand:SI 0 "register_operand" "")
2675 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
2676 (const_int 2147483647)))
2677 (clobber (reg:CC 33))]
2678 "TARGET_64BIT && reload_completed"
2680 (and:SI (match_dup 1)
2681 (const_int 2147483647)))]
2684 (define_insn "*llgt_didi"
2685 [(set (match_operand:DI 0 "register_operand" "=d,d")
2686 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
2687 (const_int 2147483647)))]
2692 [(set_attr "op_type" "RRE,RXE")])
2695 [(set (match_operand:DI 0 "register_operand" "")
2696 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
2697 (const_int 2147483647)))
2698 (clobber (reg:CC 33))]
2699 "TARGET_64BIT && reload_completed"
2701 (and:DI (match_dup 1)
2702 (const_int 2147483647)))]
2705 (define_insn "*llgt_sidi"
2706 [(set (match_operand:DI 0 "register_operand" "=d")
2707 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2708 (const_int 2147483647)))]
2711 [(set_attr "op_type" "RXE")])
2713 (define_insn_and_split "*llgt_sidi_split"
2714 [(set (match_operand:DI 0 "register_operand" "=d")
2715 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
2716 (const_int 2147483647)))
2717 (clobber (reg:CC 33))]
2720 "&& reload_completed"
2722 (and:DI (subreg:DI (match_dup 1) 0)
2723 (const_int 2147483647)))]
2727 ; zero_extendqidi2 instruction pattern(s)
2730 (define_expand "zero_extendqidi2"
2731 [(set (match_operand:DI 0 "register_operand" "")
2732 (zero_extend:DI (match_operand:QI 1 "register_operand" "")))]
2738 rtx tmp = gen_reg_rtx (SImode);
2739 emit_insn (gen_zero_extendqisi2 (tmp, operands[1]));
2740 emit_insn (gen_zero_extendsidi2 (operands[0], tmp));
2745 operands[1] = gen_lowpart (DImode, operands[1]);
2746 emit_insn (gen_ashldi3 (operands[0], operands[1], GEN_INT (56)));
2747 emit_insn (gen_lshrdi3 (operands[0], operands[0], GEN_INT (56)));
2753 (define_insn "*zero_extendqidi2"
2754 [(set (match_operand:DI 0 "register_operand" "=d")
2755 (zero_extend:DI (match_operand:QI 1 "memory_operand" "m")))]
2758 [(set_attr "op_type" "RXY")])
2761 ; zero_extendhisi2 instruction pattern(s).
2764 (define_expand "zero_extendhisi2"
2765 [(set (match_operand:SI 0 "register_operand" "")
2766 (zero_extend:SI (match_operand:HI 1 "register_operand" "")))]
2770 operands[1] = gen_lowpart (SImode, operands[1]);
2771 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xffff)));
2776 (define_insn "*zero_extendhisi2_64"
2777 [(set (match_operand:SI 0 "register_operand" "=d")
2778 (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
2781 [(set_attr "op_type" "RXY")])
2783 (define_insn_and_split "*zero_extendhisi2_31"
2784 [(set (match_operand:SI 0 "register_operand" "=&d")
2785 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS")))
2786 (clobber (reg:CC 33))]
2789 "&& reload_completed"
2790 [(set (match_dup 0) (const_int 0))
2792 [(set (strict_low_part (match_dup 2)) (match_dup 1))
2793 (clobber (reg:CC 33))])]
2794 "operands[2] = gen_lowpart (HImode, operands[0]);")
2797 ; zero_extendqisi2 instruction pattern(s).
2800 (define_expand "zero_extendqisi2"
2801 [(set (match_operand:SI 0 "register_operand" "")
2802 (zero_extend:SI (match_operand:QI 1 "register_operand" "")))]
2806 operands[1] = gen_lowpart (SImode, operands[1]);
2807 emit_insn (gen_andsi3 (operands[0], operands[1], GEN_INT (0xff)));
2812 (define_insn "*zero_extendqisi2_64"
2813 [(set (match_operand:SI 0 "register_operand" "=d")
2814 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2817 [(set_attr "op_type" "RXY")])
2819 (define_insn_and_split "*zero_extendqisi2_31"
2820 [(set (match_operand:SI 0 "register_operand" "=&d")
2821 (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
2824 "&& reload_completed"
2825 [(set (match_dup 0) (const_int 0))
2826 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2827 "operands[2] = gen_lowpart (QImode, operands[0]);")
2830 ; zero_extendqihi2 instruction pattern(s).
2833 (define_expand "zero_extendqihi2"
2834 [(set (match_operand:HI 0 "register_operand" "")
2835 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))]
2839 operands[1] = gen_lowpart (HImode, operands[1]);
2840 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff)));
2845 (define_insn "*zero_extendqihi2_64"
2846 [(set (match_operand:HI 0 "register_operand" "=d")
2847 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2850 [(set_attr "op_type" "RXY")])
2852 (define_insn_and_split "*zero_extendqihi2_31"
2853 [(set (match_operand:HI 0 "register_operand" "=&d")
2854 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2857 "&& reload_completed"
2858 [(set (match_dup 0) (const_int 0))
2859 (set (strict_low_part (match_dup 2)) (match_dup 1))]
2860 "operands[2] = gen_lowpart (QImode, operands[0]);")
2864 ; fixuns_truncdfdi2 and fix_truncdfsi2 instruction pattern(s).
2867 (define_expand "fixuns_truncdfdi2"
2868 [(set (match_operand:DI 0 "register_operand" "")
2869 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
2870 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2872 rtx label1 = gen_label_rtx ();
2873 rtx label2 = gen_label_rtx ();
2874 rtx temp = gen_reg_rtx (DFmode);
2875 operands[1] = force_reg (DFmode, operands[1]);
2877 emit_insn (gen_cmpdf (operands[1],
2878 CONST_DOUBLE_FROM_REAL_VALUE (
2879 REAL_VALUE_ATOF ("9223372036854775808.0", DFmode), DFmode)));
2880 emit_jump_insn (gen_blt (label1));
2881 emit_insn (gen_subdf3 (temp, operands[1],
2882 CONST_DOUBLE_FROM_REAL_VALUE (
2883 REAL_VALUE_ATOF ("18446744073709551616.0", DFmode), DFmode)));
2884 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], temp, GEN_INT(7)));
2887 emit_label (label1);
2888 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2889 emit_label (label2);
2893 (define_expand "fix_truncdfdi2"
2894 [(set (match_operand:DI 0 "register_operand" "")
2895 (fix:DI (match_operand:DF 1 "nonimmediate_operand" "")))]
2896 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2898 operands[1] = force_reg (DFmode, operands[1]);
2899 emit_insn (gen_fix_truncdfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
2903 (define_insn "fix_truncdfdi2_ieee"
2904 [(set (match_operand:DI 0 "register_operand" "=d")
2905 (fix:DI (match_operand:DF 1 "register_operand" "f")))
2906 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
2907 (clobber (reg:CC 33))]
2908 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2910 [(set_attr "op_type" "RRE")
2911 (set_attr "type" "ftoi")])
2914 ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s).
2917 (define_expand "fixuns_truncdfsi2"
2918 [(set (match_operand:SI 0 "register_operand" "")
2919 (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2920 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2922 rtx label1 = gen_label_rtx ();
2923 rtx label2 = gen_label_rtx ();
2924 rtx temp = gen_reg_rtx (DFmode);
2926 operands[1] = force_reg (DFmode,operands[1]);
2927 emit_insn (gen_cmpdf (operands[1],
2928 CONST_DOUBLE_FROM_REAL_VALUE (
2929 REAL_VALUE_ATOF ("2147483648.0", DFmode), DFmode)));
2930 emit_jump_insn (gen_blt (label1));
2931 emit_insn (gen_subdf3 (temp, operands[1],
2932 CONST_DOUBLE_FROM_REAL_VALUE (
2933 REAL_VALUE_ATOF ("4294967296.0", DFmode), DFmode)));
2934 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], temp, GEN_INT (7)));
2937 emit_label (label1);
2938 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2939 emit_label (label2);
2943 (define_expand "fix_truncdfsi2"
2944 [(set (match_operand:SI 0 "register_operand" "")
2945 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "")))]
2948 if (TARGET_IBM_FLOAT)
2950 /* This is the algorithm from POP chapter A.5.7.2. */
2952 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
2953 rtx two31r = s390_gen_rtx_const_DI (0x4f000000, 0x08000000);
2954 rtx two32 = s390_gen_rtx_const_DI (0x4e000001, 0x00000000);
2956 operands[1] = force_reg (DFmode, operands[1]);
2957 emit_insn (gen_fix_truncdfsi2_ibm (operands[0], operands[1],
2958 two31r, two32, temp));
2962 operands[1] = force_reg (DFmode, operands[1]);
2963 emit_insn (gen_fix_truncdfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
2969 (define_insn "fix_truncdfsi2_ieee"
2970 [(set (match_operand:SI 0 "register_operand" "=d")
2971 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2972 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND)
2973 (clobber (reg:CC 33))]
2974 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
2976 [(set_attr "op_type" "RRE")
2977 (set_attr "type" "ftoi")])
2979 (define_insn "fix_truncdfsi2_ibm"
2980 [(set (match_operand:SI 0 "register_operand" "=d")
2981 (fix:SI (match_operand:DF 1 "nonimmediate_operand" "+f")))
2982 (use (match_operand:DI 2 "immediate_operand" "m"))
2983 (use (match_operand:DI 3 "immediate_operand" "m"))
2984 (use (match_operand:BLK 4 "memory_operand" "m"))
2985 (clobber (reg:CC 33))]
2986 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
2988 output_asm_insn ("sd\t%1,%2", operands);
2989 output_asm_insn ("aw\t%1,%3", operands);
2990 output_asm_insn ("std\t%1,%4", operands);
2991 output_asm_insn ("xi\t%N4,128", operands);
2994 [(set_attr "length" "20")])
2997 ; fixuns_truncsfdi2 and fix_truncsfdi2 instruction pattern(s).
3000 (define_expand "fixuns_truncsfdi2"
3001 [(set (match_operand:DI 0 "register_operand" "")
3002 (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
3003 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3005 rtx label1 = gen_label_rtx ();
3006 rtx label2 = gen_label_rtx ();
3007 rtx temp = gen_reg_rtx (SFmode);
3009 operands[1] = force_reg (SFmode, operands[1]);
3010 emit_insn (gen_cmpsf (operands[1],
3011 CONST_DOUBLE_FROM_REAL_VALUE (
3012 REAL_VALUE_ATOF ("9223372036854775808.0", SFmode), SFmode)));
3013 emit_jump_insn (gen_blt (label1));
3015 emit_insn (gen_subsf3 (temp, operands[1],
3016 CONST_DOUBLE_FROM_REAL_VALUE (
3017 REAL_VALUE_ATOF ("18446744073709551616.0", SFmode), SFmode)));
3018 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], temp, GEN_INT(7)));
3021 emit_label (label1);
3022 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
3023 emit_label (label2);
3027 (define_expand "fix_truncsfdi2"
3028 [(set (match_operand:DI 0 "register_operand" "")
3029 (fix:DI (match_operand:SF 1 "nonimmediate_operand" "")))]
3030 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3032 operands[1] = force_reg (SFmode, operands[1]);
3033 emit_insn (gen_fix_truncsfdi2_ieee (operands[0], operands[1], GEN_INT(5)));
3037 (define_insn "fix_truncsfdi2_ieee"
3038 [(set (match_operand:DI 0 "register_operand" "=d")
3039 (fix:DI (match_operand:SF 1 "register_operand" "f")))
3040 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND)
3041 (clobber (reg:CC 33))]
3042 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3044 [(set_attr "op_type" "RRE")
3045 (set_attr "type" "ftoi")])
3048 ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s).
3051 (define_expand "fixuns_truncsfsi2"
3052 [(set (match_operand:SI 0 "register_operand" "")
3053 (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
3054 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3056 rtx label1 = gen_label_rtx ();
3057 rtx label2 = gen_label_rtx ();
3058 rtx temp = gen_reg_rtx (SFmode);
3060 operands[1] = force_reg (SFmode, operands[1]);
3061 emit_insn (gen_cmpsf (operands[1],
3062 CONST_DOUBLE_FROM_REAL_VALUE (
3063 REAL_VALUE_ATOF ("2147483648.0", SFmode), SFmode)));
3064 emit_jump_insn (gen_blt (label1));
3065 emit_insn (gen_subsf3 (temp, operands[1],
3066 CONST_DOUBLE_FROM_REAL_VALUE (
3067 REAL_VALUE_ATOF ("4294967296.0", SFmode), SFmode)));
3068 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], temp, GEN_INT (7)));
3071 emit_label (label1);
3072 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3073 emit_label (label2);
3077 (define_expand "fix_truncsfsi2"
3078 [(set (match_operand:SI 0 "register_operand" "")
3079 (fix:SI (match_operand:SF 1 "nonimmediate_operand" "")))]
3082 if (TARGET_IBM_FLOAT)
3084 /* Convert to DFmode and then use the POP algorithm. */
3085 rtx temp = gen_reg_rtx (DFmode);
3086 emit_insn (gen_extendsfdf2 (temp, operands[1]));
3087 emit_insn (gen_fix_truncdfsi2 (operands[0], temp));
3091 operands[1] = force_reg (SFmode, operands[1]);
3092 emit_insn (gen_fix_truncsfsi2_ieee (operands[0], operands[1], GEN_INT (5)));
3098 (define_insn "fix_truncsfsi2_ieee"
3099 [(set (match_operand:SI 0 "register_operand" "=d")
3100 (fix:SI (match_operand:SF 1 "register_operand" "f")))
3101 (unspec:SI [(match_operand:SI 2 "immediate_operand" "K")] UNSPEC_ROUND)
3102 (clobber (reg:CC 33))]
3103 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3105 [(set_attr "op_type" "RRE")
3106 (set_attr "type" "ftoi")])
3109 ; floatdidf2 instruction pattern(s).
3112 (define_insn "floatdidf2"
3113 [(set (match_operand:DF 0 "register_operand" "=f")
3114 (float:DF (match_operand:DI 1 "register_operand" "d")))]
3115 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3117 [(set_attr "op_type" "RRE")
3118 (set_attr "type" "itof" )])
3121 ; floatdisf2 instruction pattern(s).
3124 (define_insn "floatdisf2"
3125 [(set (match_operand:SF 0 "register_operand" "=f")
3126 (float:SF (match_operand:DI 1 "register_operand" "d")))]
3127 "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3129 [(set_attr "op_type" "RRE")
3130 (set_attr "type" "itof" )])
3133 ; floatsidf2 instruction pattern(s).
3136 (define_expand "floatsidf2"
3137 [(set (match_operand:DF 0 "register_operand" "")
3138 (float:DF (match_operand:SI 1 "register_operand" "")))]
3141 if (TARGET_IBM_FLOAT)
3143 /* This is the algorithm from POP chapter A.5.7.1. */
3145 rtx temp = assign_stack_local (BLKmode, 8, BITS_PER_WORD);
3146 rtx two31 = s390_gen_rtx_const_DI (0x4e000000, 0x80000000);
3148 emit_insn (gen_floatsidf2_ibm (operands[0], operands[1], two31, temp));
3153 (define_insn "floatsidf2_ieee"
3154 [(set (match_operand:DF 0 "register_operand" "=f")
3155 (float:DF (match_operand:SI 1 "register_operand" "d")))]
3156 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3158 [(set_attr "op_type" "RRE")
3159 (set_attr "type" "itof" )])
3161 (define_insn "floatsidf2_ibm"
3162 [(set (match_operand:DF 0 "register_operand" "=f")
3163 (float:DF (match_operand:SI 1 "register_operand" "d")))
3164 (use (match_operand:DI 2 "immediate_operand" "m"))
3165 (use (match_operand:BLK 3 "memory_operand" "m"))
3166 (clobber (reg:CC 33))]
3167 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3169 output_asm_insn ("st\t%1,%N3", operands);
3170 output_asm_insn ("xi\t%N3,128", operands);
3171 output_asm_insn ("mvc\t%O3(4,%R3),%2", operands);
3172 output_asm_insn ("ld\t%0,%3", operands);
3175 [(set_attr "length" "20")])
3178 ; floatsisf2 instruction pattern(s).
3181 (define_expand "floatsisf2"
3182 [(set (match_operand:SF 0 "register_operand" "")
3183 (float:SF (match_operand:SI 1 "register_operand" "")))]
3186 if (TARGET_IBM_FLOAT)
3188 /* Use the POP algorithm to convert to DFmode and then truncate. */
3189 rtx temp = gen_reg_rtx (DFmode);
3190 emit_insn (gen_floatsidf2 (temp, operands[1]));
3191 emit_insn (gen_truncdfsf2 (operands[0], temp));
3196 (define_insn "floatsisf2_ieee"
3197 [(set (match_operand:SF 0 "register_operand" "=f")
3198 (float:SF (match_operand:SI 1 "register_operand" "d")))]
3199 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3201 [(set_attr "op_type" "RRE")
3202 (set_attr "type" "itof" )])
3205 ; truncdfsf2 instruction pattern(s).
3208 (define_expand "truncdfsf2"
3209 [(set (match_operand:SF 0 "register_operand" "")
3210 (float_truncate:SF (match_operand:DF 1 "register_operand" "")))]
3214 (define_insn "truncdfsf2_ieee"
3215 [(set (match_operand:SF 0 "register_operand" "=f")
3216 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
3217 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3219 [(set_attr "op_type" "RRE")])
3221 (define_insn "truncdfsf2_ibm"
3222 [(set (match_operand:SF 0 "register_operand" "=f,f")
3223 (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "f,R")))]
3224 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3228 [(set_attr "op_type" "RR,RX")
3229 (set_attr "type" "floads,floads")])
3232 ; extendsfdf2 instruction pattern(s).
3235 (define_expand "extendsfdf2"
3236 [(set (match_operand:DF 0 "register_operand" "")
3237 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
3240 if (TARGET_IBM_FLOAT)
3242 emit_insn (gen_extendsfdf2_ibm (operands[0], operands[1]));
3247 (define_insn "extendsfdf2_ieee"
3248 [(set (match_operand:DF 0 "register_operand" "=f,f")
3249 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))]
3250 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3254 [(set_attr "op_type" "RRE,RXE")
3255 (set_attr "type" "floads,floads")])
3257 (define_insn "extendsfdf2_ibm"
3258 [(set (match_operand:DF 0 "register_operand" "=f,f")
3259 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R")))
3260 (clobber (reg:CC 33))]
3261 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3263 sdr\t%0,%0\;ler\t%0,%1
3264 sdr\t%0,%0\;le\t%0,%1"
3265 [(set_attr "length" "4,6")
3266 (set_attr "type" "floads,floads")])
3270 ;; ARITHMETIC OPERATIONS
3272 ; arithmetic operations set the ConditionCode,
3273 ; because of unpredictable Bits in Register for Halfword and Byte
3274 ; the ConditionCode can be set wrong in operations for Halfword and Byte
3277 ;;- Add instructions.
3281 ; addti3 instruction pattern(s).
3284 (define_insn_and_split "addti3"
3285 [(set (match_operand:TI 0 "register_operand" "=&d")
3286 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0")
3287 (match_operand:TI 2 "general_operand" "do") ) )
3288 (clobber (reg:CC 33))]
3291 "&& reload_completed"
3294 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8))
3296 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))])
3298 [(set (match_dup 3) (plus:DI (plus:DI (match_dup 4) (match_dup 5))
3299 (ltu:DI (reg:CCL1 33) (const_int 0))))
3300 (clobber (reg:CC 33))])]
3301 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3302 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3303 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3304 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3305 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3306 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3309 ; adddi3 instruction pattern(s).
3312 (define_insn "*adddi3_sign"
3313 [(set (match_operand:DI 0 "register_operand" "=d,d")
3314 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3315 (match_operand:DI 1 "register_operand" "0,0")))
3316 (clobber (reg:CC 33))]
3321 [(set_attr "op_type" "RRE,RXY")])
3323 (define_insn "*adddi3_zero_cc"
3325 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3326 (match_operand:DI 1 "register_operand" "0,0"))
3328 (set (match_operand:DI 0 "register_operand" "=d,d")
3329 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))]
3330 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3334 [(set_attr "op_type" "RRE,RXY")])
3336 (define_insn "*adddi3_zero_cconly"
3338 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3339 (match_operand:DI 1 "register_operand" "0,0"))
3341 (clobber (match_scratch:DI 0 "=d,d"))]
3342 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3346 [(set_attr "op_type" "RRE,RXY")])
3348 (define_insn "*adddi3_zero"
3349 [(set (match_operand:DI 0 "register_operand" "=d,d")
3350 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))
3351 (match_operand:DI 1 "register_operand" "0,0")))
3352 (clobber (reg:CC 33))]
3357 [(set_attr "op_type" "RRE,RXY")])
3359 (define_insn "*adddi3_imm_cc"
3361 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "0")
3362 (match_operand:DI 2 "const_int_operand" "K"))
3364 (set (match_operand:DI 0 "register_operand" "=d")
3365 (plus:DI (match_dup 1) (match_dup 2)))]
3367 && s390_match_ccmode (insn, CCAmode)
3368 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3370 [(set_attr "op_type" "RI")])
3372 (define_insn "*adddi3_carry1_cc"
3374 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3375 (match_operand:DI 2 "general_operand" "d,m"))
3377 (set (match_operand:DI 0 "register_operand" "=d,d")
3378 (plus:DI (match_dup 1) (match_dup 2)))]
3379 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3383 [(set_attr "op_type" "RRE,RXY")])
3385 (define_insn "*adddi3_carry1_cconly"
3387 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3388 (match_operand:DI 2 "general_operand" "d,m"))
3390 (clobber (match_scratch:DI 0 "=d,d"))]
3391 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3395 [(set_attr "op_type" "RRE,RXY")])
3397 (define_insn "*adddi3_carry2_cc"
3399 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3400 (match_operand:DI 2 "general_operand" "d,m"))
3402 (set (match_operand:DI 0 "register_operand" "=d,d")
3403 (plus:DI (match_dup 1) (match_dup 2)))]
3404 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3408 [(set_attr "op_type" "RRE,RXY")])
3410 (define_insn "*adddi3_carry2_cconly"
3412 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3413 (match_operand:DI 2 "general_operand" "d,m"))
3415 (clobber (match_scratch:DI 0 "=d,d"))]
3416 "s390_match_ccmode (insn, CCL1mode) && TARGET_64BIT"
3420 [(set_attr "op_type" "RRE,RXY")])
3422 (define_insn "*adddi3_cc"
3424 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3425 (match_operand:DI 2 "general_operand" "d,m"))
3427 (set (match_operand:DI 0 "register_operand" "=d,d")
3428 (plus:DI (match_dup 1) (match_dup 2)))]
3429 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3433 [(set_attr "op_type" "RRE,RXY")])
3435 (define_insn "*adddi3_cconly"
3437 (compare (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3438 (match_operand:DI 2 "general_operand" "d,m"))
3440 (clobber (match_scratch:DI 0 "=d,d"))]
3441 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3445 [(set_attr "op_type" "RRE,RXY")])
3447 (define_insn "*adddi3_cconly2"
3449 (compare (match_operand:DI 1 "nonimmediate_operand" "%0,0")
3450 (neg:SI (match_operand:DI 2 "general_operand" "d,m"))))
3451 (clobber (match_scratch:DI 0 "=d,d"))]
3452 "s390_match_ccmode(insn, CCLmode) && TARGET_64BIT"
3456 [(set_attr "op_type" "RRE,RXY")])
3458 (define_insn "*adddi3_64"
3459 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
3460 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
3461 (match_operand:DI 2 "general_operand" "d,K,m") ) )
3462 (clobber (reg:CC 33))]
3468 [(set_attr "op_type" "RRE,RI,RXY")])
3470 (define_insn_and_split "*adddi3_31z"
3471 [(set (match_operand:DI 0 "register_operand" "=&d")
3472 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3473 (match_operand:DI 2 "general_operand" "do") ) )
3474 (clobber (reg:CC 33))]
3475 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3477 "&& reload_completed"
3480 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3482 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3484 [(set (match_dup 3) (plus:SI (plus:SI (match_dup 4) (match_dup 5))
3485 (ltu:SI (reg:CCL1 33) (const_int 0))))
3486 (clobber (reg:CC 33))])]
3487 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3488 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3489 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3490 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3491 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3492 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3494 (define_insn_and_split "*adddi3_31"
3495 [(set (match_operand:DI 0 "register_operand" "=&d")
3496 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
3497 (match_operand:DI 2 "general_operand" "do") ) )
3498 (clobber (reg:CC 33))]
3501 "&& reload_completed"
3503 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5)))
3504 (clobber (reg:CC 33))])
3507 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8))
3509 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))])
3511 (if_then_else (ltu (reg:CCL1 33) (const_int 0))
3513 (label_ref (match_dup 9))))
3515 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1)))
3516 (clobber (reg:CC 33))])
3518 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3519 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3520 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3521 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3522 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3523 operands[8] = operand_subword (operands[2], 1, 0, DImode);
3524 operands[9] = gen_label_rtx ();")
3526 (define_expand "adddi3"
3528 [(set (match_operand:DI 0 "register_operand" "")
3529 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "")
3530 (match_operand:DI 2 "general_operand" "")))
3531 (clobber (reg:CC 33))])]
3536 ; addsi3 instruction pattern(s).
3539 (define_insn "*addsi3_imm_cc"
3541 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "0")
3542 (match_operand:SI 2 "const_int_operand" "K"))
3544 (set (match_operand:SI 0 "register_operand" "=d")
3545 (plus:SI (match_dup 1) (match_dup 2)))]
3546 "s390_match_ccmode (insn, CCAmode)
3547 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\")"
3549 [(set_attr "op_type" "RI")])
3551 (define_insn "*addsi3_carry1_cc"
3553 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3554 (match_operand:SI 2 "general_operand" "d,R,T"))
3556 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3557 (plus:SI (match_dup 1) (match_dup 2)))]
3558 "s390_match_ccmode (insn, CCL1mode)"
3563 [(set_attr "op_type" "RR,RX,RXY")])
3565 (define_insn "*addsi3_carry1_cconly"
3567 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3568 (match_operand:SI 2 "general_operand" "d,R,T"))
3570 (clobber (match_scratch:SI 0 "=d,d,d"))]
3571 "s390_match_ccmode (insn, CCL1mode)"
3576 [(set_attr "op_type" "RR,RX,RXY")])
3578 (define_insn "*addsi3_carry2_cc"
3580 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3581 (match_operand:SI 2 "general_operand" "d,R,T"))
3583 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3584 (plus:SI (match_dup 1) (match_dup 2)))]
3585 "s390_match_ccmode (insn, CCL1mode)"
3590 [(set_attr "op_type" "RR,RX,RXY")])
3592 (define_insn "*addsi3_carry2_cconly"
3594 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3595 (match_operand:SI 2 "general_operand" "d,R,T"))
3597 (clobber (match_scratch:SI 0 "=d,d,d"))]
3598 "s390_match_ccmode (insn, CCL1mode)"
3603 [(set_attr "op_type" "RR,RX,RXY")])
3605 (define_insn "*addsi3_cc"
3607 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3608 (match_operand:SI 2 "general_operand" "d,R,T"))
3610 (set (match_operand:SI 0 "register_operand" "=d,d,d")
3611 (plus:SI (match_dup 1) (match_dup 2)))]
3612 "s390_match_ccmode (insn, CCLmode)"
3617 [(set_attr "op_type" "RR,RX,RXY")])
3619 (define_insn "*addsi3_cconly"
3621 (compare (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3622 (match_operand:SI 2 "general_operand" "d,R,T"))
3624 (clobber (match_scratch:SI 0 "=d,d,d"))]
3625 "s390_match_ccmode (insn, CCLmode)"
3630 [(set_attr "op_type" "RR,RX,RXY")])
3632 (define_insn "*addsi3_cconly2"
3634 (compare (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
3635 (neg:SI (match_operand:SI 2 "general_operand" "d,R,T"))))
3636 (clobber (match_scratch:SI 0 "=d,d,d"))]
3637 "s390_match_ccmode (insn, CCLmode)"
3642 [(set_attr "op_type" "RR,RX,RXY")])
3644 (define_insn "*addsi3_sign"
3645 [(set (match_operand:SI 0 "register_operand" "=d,d")
3646 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))
3647 (match_operand:SI 1 "register_operand" "0,0")))
3648 (clobber (reg:CC 33))]
3653 [(set_attr "op_type" "RX,RXY")])
3655 (define_insn "addsi3"
3656 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
3657 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
3658 (match_operand:SI 2 "general_operand" "d,K,R,T")))
3659 (clobber (reg:CC 33))]
3666 [(set_attr "op_type" "RR,RI,RX,RXY")])
3669 ; adddf3 instruction pattern(s).
3672 (define_expand "adddf3"
3674 [(set (match_operand:DF 0 "register_operand" "=f,f")
3675 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3676 (match_operand:DF 2 "general_operand" "f,R")))
3677 (clobber (reg:CC 33))])]
3681 (define_insn "*adddf3"
3682 [(set (match_operand:DF 0 "register_operand" "=f,f")
3683 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3684 (match_operand:DF 2 "general_operand" "f,R")))
3685 (clobber (reg:CC 33))]
3686 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3690 [(set_attr "op_type" "RRE,RXE")
3691 (set_attr "type" "fsimpd,fsimpd")])
3693 (define_insn "*adddf3_cc"
3695 (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3696 (match_operand:DF 2 "general_operand" "f,R"))
3697 (match_operand:DF 3 "const0_operand" "")))
3698 (set (match_operand:DF 0 "register_operand" "=f,f")
3699 (plus:DF (match_dup 1) (match_dup 2)))]
3700 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3704 [(set_attr "op_type" "RRE,RXE")
3705 (set_attr "type" "fsimpd,fsimpd")])
3707 (define_insn "*adddf3_cconly"
3709 (compare (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3710 (match_operand:DF 2 "general_operand" "f,R"))
3711 (match_operand:DF 3 "const0_operand" "")))
3712 (clobber (match_scratch:DF 0 "=f,f"))]
3713 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3717 [(set_attr "op_type" "RRE,RXE")
3718 (set_attr "type" "fsimpd,fsimpd")])
3720 (define_insn "*adddf3_ibm"
3721 [(set (match_operand:DF 0 "register_operand" "=f,f")
3722 (plus:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
3723 (match_operand:DF 2 "general_operand" "f,R")))
3724 (clobber (reg:CC 33))]
3725 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3729 [(set_attr "op_type" "RR,RX")
3730 (set_attr "type" "fsimpd,fsimpd")])
3733 ; addsf3 instruction pattern(s).
3736 (define_expand "addsf3"
3738 [(set (match_operand:SF 0 "register_operand" "=f,f")
3739 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3740 (match_operand:SF 2 "general_operand" "f,R")))
3741 (clobber (reg:CC 33))])]
3745 (define_insn "*addsf3"
3746 [(set (match_operand:SF 0 "register_operand" "=f,f")
3747 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3748 (match_operand:SF 2 "general_operand" "f,R")))
3749 (clobber (reg:CC 33))]
3750 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3754 [(set_attr "op_type" "RRE,RXE")
3755 (set_attr "type" "fsimps,fsimps")])
3757 (define_insn "*addsf3_cc"
3759 (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3760 (match_operand:SF 2 "general_operand" "f,R"))
3761 (match_operand:SF 3 "const0_operand" "")))
3762 (set (match_operand:SF 0 "register_operand" "=f,f")
3763 (plus:SF (match_dup 1) (match_dup 2)))]
3764 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3768 [(set_attr "op_type" "RRE,RXE")
3769 (set_attr "type" "fsimps,fsimps")])
3771 (define_insn "*addsf3_cconly"
3773 (compare (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3774 (match_operand:SF 2 "general_operand" "f,R"))
3775 (match_operand:SF 3 "const0_operand" "")))
3776 (clobber (match_scratch:SF 0 "=f,f"))]
3777 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
3781 [(set_attr "op_type" "RRE,RXE")
3782 (set_attr "type" "fsimps,fsimps")])
3784 (define_insn "*addsf3"
3785 [(set (match_operand:SF 0 "register_operand" "=f,f")
3786 (plus:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
3787 (match_operand:SF 2 "general_operand" "f,R")))
3788 (clobber (reg:CC 33))]
3789 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
3793 [(set_attr "op_type" "RR,RX")
3794 (set_attr "type" "fsimps,fsimps")])
3798 ;;- Subtract instructions.
3802 ; subti3 instruction pattern(s).
3805 (define_insn_and_split "subti3"
3806 [(set (match_operand:TI 0 "register_operand" "=&d")
3807 (minus:TI (match_operand:TI 1 "register_operand" "0")
3808 (match_operand:TI 2 "general_operand" "do") ) )
3809 (clobber (reg:CC 33))]
3812 "&& reload_completed"
3815 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8))
3817 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))])
3819 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5))
3820 (gtu:DI (reg:CCL2 33) (const_int 0))))
3821 (clobber (reg:CC 33))])]
3822 "operands[3] = operand_subword (operands[0], 0, 0, TImode);
3823 operands[4] = operand_subword (operands[1], 0, 0, TImode);
3824 operands[5] = operand_subword (operands[2], 0, 0, TImode);
3825 operands[6] = operand_subword (operands[0], 1, 0, TImode);
3826 operands[7] = operand_subword (operands[1], 1, 0, TImode);
3827 operands[8] = operand_subword (operands[2], 1, 0, TImode);")
3830 ; subdi3 instruction pattern(s).
3833 (define_insn "*subdi3_sign"
3834 [(set (match_operand:DI 0 "register_operand" "=d,d")
3835 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3836 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3837 (clobber (reg:CC 33))]
3842 [(set_attr "op_type" "RRE,RXY")])
3844 (define_insn "*subdi3_zero_cc"
3846 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3847 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3849 (set (match_operand:DI 0 "register_operand" "=d,d")
3850 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))]
3851 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3855 [(set_attr "op_type" "RRE,RXY")])
3857 (define_insn "*subdi3_zero_cconly"
3859 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3860 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m")))
3862 (clobber (match_scratch:DI 0 "=d,d"))]
3863 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3867 [(set_attr "op_type" "RRE,RXY")])
3869 (define_insn "*subdi3_zero"
3870 [(set (match_operand:DI 0 "register_operand" "=d,d")
3871 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3872 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,m"))))
3873 (clobber (reg:CC 33))]
3878 [(set_attr "op_type" "RRE,RXY")])
3880 (define_insn "*subdi3_borrow_cc"
3882 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3883 (match_operand:DI 2 "general_operand" "d,m"))
3885 (set (match_operand:DI 0 "register_operand" "=d,d")
3886 (minus:DI (match_dup 1) (match_dup 2)))]
3887 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3891 [(set_attr "op_type" "RRE,RXY")])
3893 (define_insn "*subdi3_borrow_cconly"
3895 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3896 (match_operand:DI 2 "general_operand" "d,m"))
3898 (clobber (match_scratch:DI 0 "=d,d"))]
3899 "s390_match_ccmode (insn, CCL2mode) && TARGET_64BIT"
3903 [(set_attr "op_type" "RRE,RXY")])
3905 (define_insn "*subdi3_cc"
3907 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3908 (match_operand:DI 2 "general_operand" "d,m"))
3910 (set (match_operand:DI 0 "register_operand" "=d,d")
3911 (minus:DI (match_dup 1) (match_dup 2)))]
3912 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3916 [(set_attr "op_type" "RRE,RXY")])
3918 (define_insn "*subdi3_cc2"
3920 (compare (match_operand:DI 1 "register_operand" "0,0")
3921 (match_operand:DI 2 "general_operand" "d,m")))
3922 (set (match_operand:DI 0 "register_operand" "=d,d")
3923 (minus:DI (match_dup 1) (match_dup 2)))]
3924 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3928 [(set_attr "op_type" "RRE,RXY")])
3930 (define_insn "*subdi3_cconly"
3932 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3933 (match_operand:DI 2 "general_operand" "d,m"))
3935 (clobber (match_scratch:DI 0 "=d,d"))]
3936 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
3940 [(set_attr "op_type" "RRE,RXY")])
3942 (define_insn "*subdi3_cconly2"
3944 (compare (match_operand:DI 1 "register_operand" "0,0")
3945 (match_operand:DI 2 "general_operand" "d,m")))
3946 (clobber (match_scratch:DI 0 "=d,d"))]
3947 "s390_match_ccmode (insn, CCL3mode) && TARGET_64BIT"
3951 [(set_attr "op_type" "RRE,RXY")])
3953 (define_insn "*subdi3_64"
3954 [(set (match_operand:DI 0 "register_operand" "=d,d")
3955 (minus:DI (match_operand:DI 1 "register_operand" "0,0")
3956 (match_operand:DI 2 "general_operand" "d,m") ) )
3957 (clobber (reg:CC 33))]
3962 [(set_attr "op_type" "RRE,RRE")])
3964 (define_insn_and_split "*subdi3_31z"
3965 [(set (match_operand:DI 0 "register_operand" "=&d")
3966 (minus:DI (match_operand:DI 1 "register_operand" "0")
3967 (match_operand:DI 2 "general_operand" "do") ) )
3968 (clobber (reg:CC 33))]
3969 "!TARGET_64BIT && TARGET_CPU_ZARCH"
3971 "&& reload_completed"
3974 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
3976 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
3978 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5))
3979 (gtu:SI (reg:CCL2 33) (const_int 0))))
3980 (clobber (reg:CC 33))])]
3981 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
3982 operands[4] = operand_subword (operands[1], 0, 0, DImode);
3983 operands[5] = operand_subword (operands[2], 0, 0, DImode);
3984 operands[6] = operand_subword (operands[0], 1, 0, DImode);
3985 operands[7] = operand_subword (operands[1], 1, 0, DImode);
3986 operands[8] = operand_subword (operands[2], 1, 0, DImode);")
3988 (define_insn_and_split "*subdi3_31"
3989 [(set (match_operand:DI 0 "register_operand" "=&d")
3990 (minus:DI (match_operand:DI 1 "register_operand" "0")
3991 (match_operand:DI 2 "general_operand" "do") ) )
3992 (clobber (reg:CC 33))]
3995 "&& reload_completed"
3997 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5)))
3998 (clobber (reg:CC 33))])
4001 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8))
4003 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))])
4005 (if_then_else (gtu (reg:CCL2 33) (const_int 0))
4007 (label_ref (match_dup 9))))
4009 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))
4010 (clobber (reg:CC 33))])
4012 "operands[3] = operand_subword (operands[0], 0, 0, DImode);
4013 operands[4] = operand_subword (operands[1], 0, 0, DImode);
4014 operands[5] = operand_subword (operands[2], 0, 0, DImode);
4015 operands[6] = operand_subword (operands[0], 1, 0, DImode);
4016 operands[7] = operand_subword (operands[1], 1, 0, DImode);
4017 operands[8] = operand_subword (operands[2], 1, 0, DImode);
4018 operands[9] = gen_label_rtx ();")
4020 (define_expand "subdi3"
4022 [(set (match_operand:DI 0 "register_operand" "")
4023 (minus:DI (match_operand:DI 1 "register_operand" "")
4024 (match_operand:DI 2 "general_operand" "")))
4025 (clobber (reg:CC 33))])]
4030 ; subsi3 instruction pattern(s).
4033 (define_insn "*subsi3_borrow_cc"
4035 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4036 (match_operand:SI 2 "general_operand" "d,R,T"))
4038 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4039 (minus:SI (match_dup 1) (match_dup 2)))]
4040 "s390_match_ccmode (insn, CCL2mode)"
4045 [(set_attr "op_type" "RR,RX,RXY")])
4047 (define_insn "*subsi3_borrow_cconly"
4049 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4050 (match_operand:SI 2 "general_operand" "d,R,T"))
4052 (clobber (match_scratch:SI 0 "=d,d,d"))]
4053 "s390_match_ccmode (insn, CCL2mode)"
4058 [(set_attr "op_type" "RR,RX,RXY")])
4060 (define_insn "*subsi3_cc"
4062 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4063 (match_operand:SI 2 "general_operand" "d,R,T"))
4065 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4066 (minus:SI (match_dup 1) (match_dup 2)))]
4067 "s390_match_ccmode (insn, CCLmode)"
4072 [(set_attr "op_type" "RR,RX,RXY")])
4074 (define_insn "*subsi3_cc2"
4076 (compare (match_operand:SI 1 "register_operand" "0,0,0")
4077 (match_operand:SI 2 "general_operand" "d,R,T")))
4078 (set (match_operand:SI 0 "register_operand" "=d,d,d")
4079 (minus:SI (match_dup 1) (match_dup 2)))]
4080 "s390_match_ccmode (insn, CCL3mode)"
4085 [(set_attr "op_type" "RR,RX,RXY")])
4087 (define_insn "*subsi3_cconly"
4089 (compare (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4090 (match_operand:SI 2 "general_operand" "d,R,T"))
4092 (clobber (match_scratch:SI 0 "=d,d,d"))]
4093 "s390_match_ccmode (insn, CCLmode)"
4098 [(set_attr "op_type" "RR,RX,RXY")])
4100 (define_insn "*subsi3_cconly2"
4102 (compare (match_operand:SI 1 "register_operand" "0,0,0")
4103 (match_operand:SI 2 "general_operand" "d,R,T")))
4104 (clobber (match_scratch:SI 0 "=d,d,d"))]
4105 "s390_match_ccmode (insn, CCL3mode)"
4110 [(set_attr "op_type" "RR,RX,RXY")])
4112 (define_insn "*subsi3_sign"
4113 [(set (match_operand:SI 0 "register_operand" "=d,d")
4114 (minus:SI (match_operand:SI 1 "register_operand" "0,0")
4115 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T"))))
4116 (clobber (reg:CC 33))]
4121 [(set_attr "op_type" "RX,RXY")])
4123 (define_insn "subsi3"
4124 [(set (match_operand:SI 0 "register_operand" "=d,d,d")
4125 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0")
4126 (match_operand:SI 2 "general_operand" "d,R,T")))
4127 (clobber (reg:CC 33))]
4133 [(set_attr "op_type" "RR,RX,RXY")])
4137 ; subdf3 instruction pattern(s).
4140 (define_expand "subdf3"
4142 [(set (match_operand:DF 0 "register_operand" "=f,f")
4143 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
4144 (match_operand:DF 2 "general_operand" "f,R")))
4145 (clobber (reg:CC 33))])]
4149 (define_insn "*subdf3"
4150 [(set (match_operand:DF 0 "register_operand" "=f,f")
4151 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
4152 (match_operand:DF 2 "general_operand" "f,R")))
4153 (clobber (reg:CC 33))]
4154 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4158 [(set_attr "op_type" "RRE,RXE")
4159 (set_attr "type" "fsimpd,fsimpd")])
4161 (define_insn "*subdf3_cc"
4163 (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")
4164 (match_operand:DF 2 "general_operand" "f,R"))
4165 (match_operand:DF 3 "const0_operand" "")))
4166 (set (match_operand:DF 0 "register_operand" "=f,f")
4167 (minus:DF (match_dup 1) (match_dup 2)))]
4168 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4172 [(set_attr "op_type" "RRE,RXE")
4173 (set_attr "type" "fsimpd,fsimpd")])
4175 (define_insn "*subdf3_cconly"
4177 (compare (minus:DF (match_operand:DF 1 "nonimmediate_operand" "0,0")
4178 (match_operand:DF 2 "general_operand" "f,R"))
4179 (match_operand:DF 3 "const0_operand" "")))
4180 (clobber (match_scratch:DF 0 "=f,f"))]
4181 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4185 [(set_attr "op_type" "RRE,RXE")
4186 (set_attr "type" "fsimpd,fsimpd")])
4188 (define_insn "*subdf3_ibm"
4189 [(set (match_operand:DF 0 "register_operand" "=f,f")
4190 (minus:DF (match_operand:DF 1 "register_operand" "0,0")
4191 (match_operand:DF 2 "general_operand" "f,R")))
4192 (clobber (reg:CC 33))]
4193 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4197 [(set_attr "op_type" "RR,RX")
4198 (set_attr "type" "fsimpd,fsimpd")])
4201 ; subsf3 instruction pattern(s).
4204 (define_expand "subsf3"
4206 [(set (match_operand:SF 0 "register_operand" "=f,f")
4207 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
4208 (match_operand:SF 2 "general_operand" "f,R")))
4209 (clobber (reg:CC 33))])]
4213 (define_insn "*subsf3"
4214 [(set (match_operand:SF 0 "register_operand" "=f,f")
4215 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
4216 (match_operand:SF 2 "general_operand" "f,R")))
4217 (clobber (reg:CC 33))]
4218 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4222 [(set_attr "op_type" "RRE,RXE")
4223 (set_attr "type" "fsimps,fsimps")])
4225 (define_insn "*subsf3_cc"
4227 (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
4228 (match_operand:SF 2 "general_operand" "f,R"))
4229 (match_operand:SF 3 "const0_operand" "")))
4230 (set (match_operand:SF 0 "register_operand" "=f,f")
4231 (minus:SF (match_dup 1) (match_dup 2)))]
4232 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4236 [(set_attr "op_type" "RRE,RXE")
4237 (set_attr "type" "fsimps,fsimps")])
4239 (define_insn "*subsf3_cconly"
4241 (compare (minus:SF (match_operand:SF 1 "nonimmediate_operand" "0,0")
4242 (match_operand:SF 2 "general_operand" "f,R"))
4243 (match_operand:SF 3 "const0_operand" "")))
4244 (clobber (match_scratch:SF 0 "=f,f"))]
4245 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4249 [(set_attr "op_type" "RRE,RXE")
4250 (set_attr "type" "fsimps,fsimps")])
4252 (define_insn "*subsf3_ibm"
4253 [(set (match_operand:SF 0 "register_operand" "=f,f")
4254 (minus:SF (match_operand:SF 1 "register_operand" "0,0")
4255 (match_operand:SF 2 "general_operand" "f,R")))
4256 (clobber (reg:CC 33))]
4257 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4261 [(set_attr "op_type" "RR,RX")
4262 (set_attr "type" "fsimps,fsimps")])
4266 ;;- Conditional add/subtract instructions.
4270 ; adddicc instruction pattern(s).
4273 (define_insn "*adddi3_alc_cc"
4276 (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4277 (match_operand:DI 2 "general_operand" "d,m"))
4278 (match_operand:DI 3 "s390_alc_comparison" ""))
4280 (set (match_operand:DI 0 "register_operand" "=d,d")
4281 (plus:DI (plus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4282 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4286 [(set_attr "op_type" "RRE,RXY")])
4288 (define_insn "*adddi3_alc"
4289 [(set (match_operand:DI 0 "register_operand" "=d,d")
4290 (plus:DI (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
4291 (match_operand:DI 2 "general_operand" "d,m"))
4292 (match_operand:DI 3 "s390_alc_comparison" "")))
4293 (clobber (reg:CC 33))]
4298 [(set_attr "op_type" "RRE,RXY")])
4300 (define_insn "*subdi3_slb_cc"
4303 (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
4304 (match_operand:DI 2 "general_operand" "d,m"))
4305 (match_operand:DI 3 "s390_slb_comparison" ""))
4307 (set (match_operand:DI 0 "register_operand" "=d,d")
4308 (minus:DI (minus:DI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4309 "s390_match_ccmode (insn, CCLmode) && TARGET_64BIT"
4313 [(set_attr "op_type" "RRE,RXY")])
4315 (define_insn "*subdi3_slb"
4316 [(set (match_operand:DI 0 "register_operand" "=d,d")
4317 (minus:DI (minus:DI (match_operand:DI 1 "nonimmediate_operand" "0,0")
4318 (match_operand:DI 2 "general_operand" "d,m"))
4319 (match_operand:DI 3 "s390_slb_comparison" "")))
4320 (clobber (reg:CC 33))]
4325 [(set_attr "op_type" "RRE,RXY")])
4327 (define_expand "adddicc"
4328 [(match_operand:DI 0 "register_operand" "")
4329 (match_operand 1 "comparison_operator" "")
4330 (match_operand:DI 2 "register_operand" "")
4331 (match_operand:DI 3 "const_int_operand" "")]
4333 "if (!s390_expand_addcc (GET_CODE (operands[1]),
4334 s390_compare_op0, s390_compare_op1,
4335 operands[0], operands[2],
4336 operands[3])) FAIL; DONE;")
4339 ; addsicc instruction pattern(s).
4342 (define_insn "*addsi3_alc_cc"
4345 (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4346 (match_operand:SI 2 "general_operand" "d,m"))
4347 (match_operand:SI 3 "s390_alc_comparison" ""))
4349 (set (match_operand:SI 0 "register_operand" "=d,d")
4350 (plus:SI (plus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4351 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4355 [(set_attr "op_type" "RRE,RXY")])
4357 (define_insn "*addsi3_alc"
4358 [(set (match_operand:SI 0 "register_operand" "=d,d")
4359 (plus:SI (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
4360 (match_operand:SI 2 "general_operand" "d,m"))
4361 (match_operand:SI 3 "s390_alc_comparison" "")))
4362 (clobber (reg:CC 33))]
4367 [(set_attr "op_type" "RRE,RXY")])
4369 (define_insn "*subsi3_slb_cc"
4372 (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
4373 (match_operand:SI 2 "general_operand" "d,m"))
4374 (match_operand:SI 3 "s390_slb_comparison" ""))
4376 (set (match_operand:SI 0 "register_operand" "=d,d")
4377 (minus:SI (minus:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
4378 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH"
4382 [(set_attr "op_type" "RRE,RXY")])
4384 (define_insn "*subsi3_slb"
4385 [(set (match_operand:SI 0 "register_operand" "=d,d")
4386 (minus:SI (minus:SI (match_operand:SI 1 "nonimmediate_operand" "0,0")
4387 (match_operand:SI 2 "general_operand" "d,m"))
4388 (match_operand:SI 3 "s390_slb_comparison" "")))
4389 (clobber (reg:CC 33))]
4394 [(set_attr "op_type" "RRE,RXY")])
4396 (define_expand "addsicc"
4397 [(match_operand:SI 0 "register_operand" "")
4398 (match_operand 1 "comparison_operator" "")
4399 (match_operand:SI 2 "register_operand" "")
4400 (match_operand:SI 3 "const_int_operand" "")]
4402 "if (!s390_expand_addcc (GET_CODE (operands[1]),
4403 s390_compare_op0, s390_compare_op1,
4404 operands[0], operands[2],
4405 operands[3])) FAIL; DONE;")
4408 ; scond instruction pattern(s).
4411 (define_insn_and_split "*sconddi"
4412 [(set (match_operand:DI 0 "register_operand" "=&d")
4413 (match_operand:DI 1 "s390_alc_comparison" ""))
4414 (clobber (reg:CC 33))]
4417 "&& reload_completed"
4418 [(set (match_dup 0) (const_int 0))
4420 [(set (match_dup 0) (plus:DI (plus:DI (match_dup 0) (match_dup 0))
4422 (clobber (reg:CC 33))])]
4425 (define_insn_and_split "*scondsi"
4426 [(set (match_operand:SI 0 "register_operand" "=&d")
4427 (match_operand:SI 1 "s390_alc_comparison" ""))
4428 (clobber (reg:CC 33))]
4431 "&& reload_completed"
4432 [(set (match_dup 0) (const_int 0))
4434 [(set (match_dup 0) (plus:SI (plus:SI (match_dup 0) (match_dup 0))
4436 (clobber (reg:CC 33))])]
4439 (define_insn_and_split "*sconddi_neg"
4440 [(set (match_operand:DI 0 "register_operand" "=&d")
4441 (match_operand:DI 1 "s390_slb_comparison" ""))
4442 (clobber (reg:CC 33))]
4445 "&& reload_completed"
4446 [(set (match_dup 0) (const_int 0))
4448 [(set (match_dup 0) (minus:DI (minus:DI (match_dup 0) (match_dup 0))
4450 (clobber (reg:CC 33))])
4452 [(set (match_dup 0) (neg:DI (match_dup 0)))
4453 (clobber (reg:CC 33))])]
4456 (define_insn_and_split "*scondsi_neg"
4457 [(set (match_operand:SI 0 "register_operand" "=&d")
4458 (match_operand:SI 1 "s390_slb_comparison" ""))
4459 (clobber (reg:CC 33))]
4462 "&& reload_completed"
4463 [(set (match_dup 0) (const_int 0))
4465 [(set (match_dup 0) (minus:SI (minus:SI (match_dup 0) (match_dup 0))
4467 (clobber (reg:CC 33))])
4469 [(set (match_dup 0) (neg:SI (match_dup 0)))
4470 (clobber (reg:CC 33))])]
4473 (define_expand "sltu"
4474 [(match_operand:SI 0 "register_operand" "")]
4476 "if (!s390_expand_addcc (LTU, s390_compare_op0, s390_compare_op1,
4477 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4479 (define_expand "sgtu"
4480 [(match_operand:SI 0 "register_operand" "")]
4482 "if (!s390_expand_addcc (GTU, s390_compare_op0, s390_compare_op1,
4483 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4485 (define_expand "sleu"
4486 [(match_operand:SI 0 "register_operand" "")]
4488 "if (!s390_expand_addcc (LEU, s390_compare_op0, s390_compare_op1,
4489 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4491 (define_expand "sgeu"
4492 [(match_operand:SI 0 "register_operand" "")]
4494 "if (!s390_expand_addcc (GEU, s390_compare_op0, s390_compare_op1,
4495 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;")
4499 ;;- Multiply instructions.
4503 ; muldi3 instruction pattern(s).
4506 (define_insn "*muldi3_sign"
4507 [(set (match_operand:DI 0 "register_operand" "=d,d")
4508 (mult:DI (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "d,m"))
4509 (match_operand:DI 1 "register_operand" "0,0")))]
4514 [(set_attr "op_type" "RRE,RXY")
4515 (set_attr "type" "imul")])
4517 (define_insn "muldi3"
4518 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
4519 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0")
4520 (match_operand:DI 2 "general_operand" "d,K,m")))]
4526 [(set_attr "op_type" "RRE,RI,RXY")
4527 (set_attr "type" "imul")])
4530 ; mulsi3 instruction pattern(s).
4533 (define_insn "*mulsi3_sign"
4534 [(set (match_operand:SI 0 "register_operand" "=d")
4535 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R"))
4536 (match_operand:SI 1 "register_operand" "0")))]
4539 [(set_attr "op_type" "RX")
4540 (set_attr "type" "imul")])
4542 (define_insn "mulsi3"
4543 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d")
4544 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
4545 (match_operand:SI 2 "general_operand" "d,K,R,T")))]
4552 [(set_attr "op_type" "RRE,RI,RX,RXY")
4553 (set_attr "type" "imul")])
4556 ; mulsidi3 instruction pattern(s).
4559 (define_insn "mulsidi3"
4560 [(set (match_operand:DI 0 "register_operand" "=d,d")
4561 (mult:DI (sign_extend:DI
4562 (match_operand:SI 1 "register_operand" "%0,0"))
4564 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))]
4569 [(set_attr "op_type" "RR,RX")
4570 (set_attr "type" "imul")])
4573 ; umulsidi3 instruction pattern(s).
4576 (define_insn "umulsidi3"
4577 [(set (match_operand:DI 0 "register_operand" "=d,d")
4578 (mult:DI (zero_extend:DI
4579 (match_operand:SI 1 "register_operand" "%0,0"))
4581 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))]
4582 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4586 [(set_attr "op_type" "RRE,RXY")
4587 (set_attr "type" "imul")])
4590 ; muldf3 instruction pattern(s).
4593 (define_expand "muldf3"
4594 [(set (match_operand:DF 0 "register_operand" "=f,f")
4595 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
4596 (match_operand:DF 2 "general_operand" "f,R")))]
4600 (define_insn "*muldf3"
4601 [(set (match_operand:DF 0 "register_operand" "=f,f")
4602 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
4603 (match_operand:DF 2 "general_operand" "f,R")))]
4604 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4608 [(set_attr "op_type" "RRE,RXE")
4609 (set_attr "type" "fmuld")])
4611 (define_insn "*muldf3_ibm"
4612 [(set (match_operand:DF 0 "register_operand" "=f,f")
4613 (mult:DF (match_operand:DF 1 "nonimmediate_operand" "%0,0")
4614 (match_operand:DF 2 "general_operand" "f,R")))]
4615 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4619 [(set_attr "op_type" "RR,RX")
4620 (set_attr "type" "fmuld")])
4622 (define_insn "*fmadddf"
4623 [(set (match_operand:DF 0 "register_operand" "=f,f")
4624 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "%f,f")
4625 (match_operand:DF 2 "nonimmediate_operand" "f,R"))
4626 (match_operand:DF 3 "register_operand" "0,0")))]
4627 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4631 [(set_attr "op_type" "RRE,RXE")
4632 (set_attr "type" "fmuld")])
4634 (define_insn "*fmsubdf"
4635 [(set (match_operand:DF 0 "register_operand" "=f,f")
4636 (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "f,f")
4637 (match_operand:DF 2 "nonimmediate_operand" "f,R"))
4638 (match_operand:DF 3 "register_operand" "0,0")))]
4639 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4643 [(set_attr "op_type" "RRE,RXE")
4644 (set_attr "type" "fmuld")])
4647 ; mulsf3 instruction pattern(s).
4650 (define_expand "mulsf3"
4651 [(set (match_operand:SF 0 "register_operand" "=f,f")
4652 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
4653 (match_operand:SF 2 "general_operand" "f,R")))]
4657 (define_insn "*mulsf3"
4658 [(set (match_operand:SF 0 "register_operand" "=f,f")
4659 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
4660 (match_operand:SF 2 "general_operand" "f,R")))]
4661 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
4665 [(set_attr "op_type" "RRE,RXE")
4666 (set_attr "type" "fmuls")])
4668 (define_insn "*mulsf3_ibm"
4669 [(set (match_operand:SF 0 "register_operand" "=f,f")
4670 (mult:SF (match_operand:SF 1 "nonimmediate_operand" "%0,0")
4671 (match_operand:SF 2 "general_operand" "f,R")))]
4672 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
4676 [(set_attr "op_type" "RR,RX")
4677 (set_attr "type" "fmuls")])
4679 (define_insn "*fmaddsf"
4680 [(set (match_operand:SF 0 "register_operand" "=f,f")
4681 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "%f,f")
4682 (match_operand:SF 2 "nonimmediate_operand" "f,R"))
4683 (match_operand:SF 3 "register_operand" "0,0")))]
4684 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4688 [(set_attr "op_type" "RRE,RXE")
4689 (set_attr "type" "fmuls")])
4691 (define_insn "*fmsubsf"
4692 [(set (match_operand:SF 0 "register_operand" "=f,f")
4693 (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "f,f")
4694 (match_operand:SF 2 "nonimmediate_operand" "f,R"))
4695 (match_operand:SF 3 "register_operand" "0,0")))]
4696 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT && TARGET_FUSED_MADD"
4700 [(set_attr "op_type" "RRE,RXE")
4701 (set_attr "type" "fmuls")])
4704 ;;- Divide and modulo instructions.
4708 ; divmoddi4 instruction pattern(s).
4711 (define_expand "divmoddi4"
4712 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4713 (div:DI (match_operand:DI 1 "register_operand" "")
4714 (match_operand:DI 2 "general_operand" "")))
4715 (set (match_operand:DI 3 "general_operand" "")
4716 (mod:DI (match_dup 1) (match_dup 2)))])
4717 (clobber (match_dup 4))]
4720 rtx insn, div_equal, mod_equal;
4722 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]);
4723 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]);
4725 operands[4] = gen_reg_rtx(TImode);
4726 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2]));
4728 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4730 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4732 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4734 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4739 (define_insn "divmodtidi3"
4740 [(set (match_operand:TI 0 "register_operand" "=d,d")
4744 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4745 (match_operand:DI 2 "general_operand" "d,m")))
4747 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))]
4752 [(set_attr "op_type" "RRE,RXY")
4753 (set_attr "type" "idiv")])
4755 (define_insn "divmodtisi3"
4756 [(set (match_operand:TI 0 "register_operand" "=d,d")
4760 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4762 (match_operand:SI 2 "nonimmediate_operand" "d,m"))))
4765 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))]
4770 [(set_attr "op_type" "RRE,RXY")
4771 (set_attr "type" "idiv")])
4774 ; udivmoddi4 instruction pattern(s).
4777 (define_expand "udivmoddi4"
4778 [(parallel [(set (match_operand:DI 0 "general_operand" "")
4779 (udiv:DI (match_operand:DI 1 "general_operand" "")
4780 (match_operand:DI 2 "nonimmediate_operand" "")))
4781 (set (match_operand:DI 3 "general_operand" "")
4782 (umod:DI (match_dup 1) (match_dup 2)))])
4783 (clobber (match_dup 4))]
4786 rtx insn, div_equal, mod_equal, equal;
4788 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]);
4789 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]);
4790 equal = gen_rtx_IOR (TImode,
4791 gen_rtx_ASHIFT (TImode,
4792 gen_rtx_ZERO_EXTEND (TImode, mod_equal),
4794 gen_rtx_ZERO_EXTEND (TImode, div_equal));
4796 operands[4] = gen_reg_rtx(TImode);
4797 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4798 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]);
4799 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx);
4800 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2]));
4802 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4804 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4]));
4806 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4808 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4]));
4810 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4815 (define_insn "udivmodtidi3"
4816 [(set (match_operand:TI 0 "register_operand" "=d,d")
4821 (umod:TI (match_operand:TI 1 "register_operand" "0,0")
4823 (match_operand:DI 2 "nonimmediate_operand" "d,m")))))
4827 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))]
4832 [(set_attr "op_type" "RRE,RXY")
4833 (set_attr "type" "idiv")])
4836 ; divmodsi4 instruction pattern(s).
4839 (define_expand "divmodsi4"
4840 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4841 (div:SI (match_operand:SI 1 "general_operand" "")
4842 (match_operand:SI 2 "nonimmediate_operand" "")))
4843 (set (match_operand:SI 3 "general_operand" "")
4844 (mod:SI (match_dup 1) (match_dup 2)))])
4845 (clobber (match_dup 4))]
4848 rtx insn, div_equal, mod_equal, equal;
4850 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]);
4851 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]);
4852 equal = gen_rtx_IOR (DImode,
4853 gen_rtx_ASHIFT (DImode,
4854 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4856 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4858 operands[4] = gen_reg_rtx(DImode);
4859 emit_insn (gen_extendsidi2 (operands[4], operands[1]));
4860 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2]));
4862 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4864 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4866 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4868 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4870 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4875 (define_insn "divmoddisi3"
4876 [(set (match_operand:DI 0 "register_operand" "=d,d")
4881 (mod:DI (match_operand:DI 1 "register_operand" "0,0")
4883 (match_operand:SI 2 "nonimmediate_operand" "d,R")))))
4887 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))]
4892 [(set_attr "op_type" "RR,RX")
4893 (set_attr "type" "idiv")])
4896 ; udivsi3 and umodsi3 instruction pattern(s).
4899 (define_expand "udivmodsi4"
4900 [(parallel [(set (match_operand:SI 0 "general_operand" "")
4901 (udiv:SI (match_operand:SI 1 "general_operand" "")
4902 (match_operand:SI 2 "nonimmediate_operand" "")))
4903 (set (match_operand:SI 3 "general_operand" "")
4904 (umod:SI (match_dup 1) (match_dup 2)))])
4905 (clobber (match_dup 4))]
4906 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4908 rtx insn, div_equal, mod_equal, equal;
4910 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4911 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4912 equal = gen_rtx_IOR (DImode,
4913 gen_rtx_ASHIFT (DImode,
4914 gen_rtx_ZERO_EXTEND (DImode, mod_equal),
4916 gen_rtx_ZERO_EXTEND (DImode, div_equal));
4918 operands[4] = gen_reg_rtx(DImode);
4919 emit_insn (gen_rtx_CLOBBER (VOIDmode, operands[4]));
4920 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]);
4921 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx);
4922 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2]));
4924 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
4926 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4]));
4928 gen_rtx_EXPR_LIST (REG_EQUAL, div_equal, REG_NOTES (insn));
4930 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4]));
4932 gen_rtx_EXPR_LIST (REG_EQUAL, mod_equal, REG_NOTES (insn));
4937 (define_insn "udivmoddisi3"
4938 [(set (match_operand:DI 0 "register_operand" "=d,d")
4943 (umod:DI (match_operand:DI 1 "register_operand" "0,0")
4945 (match_operand:SI 2 "nonimmediate_operand" "d,m")))))
4949 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))]
4950 "!TARGET_64BIT && TARGET_CPU_ZARCH"
4954 [(set_attr "op_type" "RRE,RXY")
4955 (set_attr "type" "idiv")])
4957 (define_expand "udivsi3"
4958 [(set (match_operand:SI 0 "register_operand" "=d")
4959 (udiv:SI (match_operand:SI 1 "general_operand" "")
4960 (match_operand:SI 2 "general_operand" "")))
4961 (clobber (match_dup 3))]
4962 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
4964 rtx insn, udiv_equal, umod_equal, equal;
4966 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
4967 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
4968 equal = gen_rtx_IOR (DImode,
4969 gen_rtx_ASHIFT (DImode,
4970 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
4972 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
4974 operands[3] = gen_reg_rtx (DImode);
4976 if (CONSTANT_P (operands[2]))
4978 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4980 rtx label1 = gen_label_rtx ();
4982 operands[1] = make_safe_from (operands[1], operands[0]);
4983 emit_move_insn (operands[0], const0_rtx);
4984 emit_insn (gen_cmpsi (operands[1], operands[2]));
4985 emit_jump_insn (gen_bltu (label1));
4986 emit_move_insn (operands[0], const1_rtx);
4987 emit_label (label1);
4991 operands[2] = force_reg (SImode, operands[2]);
4992 operands[2] = make_safe_from (operands[2], operands[0]);
4994 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
4995 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
4998 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
5000 insn = emit_move_insn (operands[0],
5001 gen_lowpart (SImode, operands[3]));
5003 gen_rtx_EXPR_LIST (REG_EQUAL,
5004 udiv_equal, REG_NOTES (insn));
5009 rtx label1 = gen_label_rtx ();
5010 rtx label2 = gen_label_rtx ();
5011 rtx label3 = gen_label_rtx ();
5013 operands[1] = force_reg (SImode, operands[1]);
5014 operands[1] = make_safe_from (operands[1], operands[0]);
5015 operands[2] = force_reg (SImode, operands[2]);
5016 operands[2] = make_safe_from (operands[2], operands[0]);
5018 emit_move_insn (operands[0], const0_rtx);
5019 emit_insn (gen_cmpsi (operands[2], operands[1]));
5020 emit_jump_insn (gen_bgtu (label3));
5021 emit_insn (gen_cmpsi (operands[2], const0_rtx));
5022 emit_jump_insn (gen_blt (label2));
5023 emit_insn (gen_cmpsi (operands[2], const1_rtx));
5024 emit_jump_insn (gen_beq (label1));
5025 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5026 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5029 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
5031 insn = emit_move_insn (operands[0],
5032 gen_lowpart (SImode, operands[3]));
5034 gen_rtx_EXPR_LIST (REG_EQUAL,
5035 udiv_equal, REG_NOTES (insn));
5037 emit_label (label1);
5038 emit_move_insn (operands[0], operands[1]);
5040 emit_label (label2);
5041 emit_move_insn (operands[0], const1_rtx);
5042 emit_label (label3);
5044 emit_move_insn (operands[0], operands[0]);
5048 (define_expand "umodsi3"
5049 [(set (match_operand:SI 0 "register_operand" "=d")
5050 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "")
5051 (match_operand:SI 2 "nonimmediate_operand" "")))
5052 (clobber (match_dup 3))]
5053 "!TARGET_64BIT && !TARGET_CPU_ZARCH"
5055 rtx insn, udiv_equal, umod_equal, equal;
5057 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]);
5058 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]);
5059 equal = gen_rtx_IOR (DImode,
5060 gen_rtx_ASHIFT (DImode,
5061 gen_rtx_ZERO_EXTEND (DImode, umod_equal),
5063 gen_rtx_ZERO_EXTEND (DImode, udiv_equal));
5065 operands[3] = gen_reg_rtx (DImode);
5067 if (CONSTANT_P (operands[2]))
5069 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0)
5071 rtx label1 = gen_label_rtx ();
5073 operands[1] = make_safe_from (operands[1], operands[0]);
5074 emit_move_insn (operands[0], operands[1]);
5075 emit_insn (gen_cmpsi (operands[0], operands[2]));
5076 emit_jump_insn (gen_bltu (label1));
5077 emit_insn (gen_abssi2 (operands[0], operands[2]));
5078 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1]));
5079 emit_label (label1);
5083 operands[2] = force_reg (SImode, operands[2]);
5084 operands[2] = make_safe_from (operands[2], operands[0]);
5086 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5087 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5090 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
5092 insn = emit_move_insn (operands[0],
5093 gen_highpart (SImode, operands[3]));
5095 gen_rtx_EXPR_LIST (REG_EQUAL,
5096 umod_equal, REG_NOTES (insn));
5101 rtx label1 = gen_label_rtx ();
5102 rtx label2 = gen_label_rtx ();
5103 rtx label3 = gen_label_rtx ();
5105 operands[1] = force_reg (SImode, operands[1]);
5106 operands[1] = make_safe_from (operands[1], operands[0]);
5107 operands[2] = force_reg (SImode, operands[2]);
5108 operands[2] = make_safe_from (operands[2], operands[0]);
5110 emit_move_insn(operands[0], operands[1]);
5111 emit_insn (gen_cmpsi (operands[2], operands[1]));
5112 emit_jump_insn (gen_bgtu (label3));
5113 emit_insn (gen_cmpsi (operands[2], const0_rtx));
5114 emit_jump_insn (gen_blt (label2));
5115 emit_insn (gen_cmpsi (operands[2], const1_rtx));
5116 emit_jump_insn (gen_beq (label1));
5117 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1]));
5118 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3],
5121 gen_rtx_EXPR_LIST (REG_EQUAL, equal, REG_NOTES (insn));
5123 insn = emit_move_insn (operands[0],
5124 gen_highpart (SImode, operands[3]));
5126 gen_rtx_EXPR_LIST (REG_EQUAL,
5127 umod_equal, REG_NOTES (insn));
5129 emit_label (label1);
5130 emit_move_insn (operands[0], const0_rtx);
5132 emit_label (label2);
5133 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2]));
5134 emit_label (label3);
5140 ; divdf3 instruction pattern(s).
5143 (define_expand "divdf3"
5144 [(set (match_operand:DF 0 "register_operand" "=f,f")
5145 (div:DF (match_operand:DF 1 "register_operand" "0,0")
5146 (match_operand:DF 2 "general_operand" "f,R")))]
5150 (define_insn "*divdf3"
5151 [(set (match_operand:DF 0 "register_operand" "=f,f")
5152 (div:DF (match_operand:DF 1 "register_operand" "0,0")
5153 (match_operand:DF 2 "general_operand" "f,R")))]
5154 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5158 [(set_attr "op_type" "RRE,RXE")
5159 (set_attr "type" "fdivd")])
5161 (define_insn "*divdf3_ibm"
5162 [(set (match_operand:DF 0 "register_operand" "=f,f")
5163 (div:DF (match_operand:DF 1 "register_operand" "0,0")
5164 (match_operand:DF 2 "general_operand" "f,R")))]
5165 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5169 [(set_attr "op_type" "RR,RX")
5170 (set_attr "type" "fdivd")])
5173 ; divsf3 instruction pattern(s).
5176 (define_expand "divsf3"
5177 [(set (match_operand:SF 0 "register_operand" "=f,f")
5178 (div:SF (match_operand:SF 1 "register_operand" "0,0")
5179 (match_operand:SF 2 "general_operand" "f,R")))]
5183 (define_insn "*divsf3"
5184 [(set (match_operand:SF 0 "register_operand" "=f,f")
5185 (div:SF (match_operand:SF 1 "register_operand" "0,0")
5186 (match_operand:SF 2 "general_operand" "f,R")))]
5187 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
5191 [(set_attr "op_type" "RRE,RXE")
5192 (set_attr "type" "fdivs")])
5194 (define_insn "*divsf3"
5195 [(set (match_operand:SF 0 "register_operand" "=f,f")
5196 (div:SF (match_operand:SF 1 "register_operand" "0,0")
5197 (match_operand:SF 2 "general_operand" "f,R")))]
5198 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
5202 [(set_attr "op_type" "RR,RX")
5203 (set_attr "type" "fdivs")])
5207 ;;- And instructions.
5211 ; anddi3 instruction pattern(s).
5214 (define_insn "*anddi3_cc"
5216 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5217 (match_operand:DI 2 "general_operand" "d,m"))
5219 (set (match_operand:DI 0 "register_operand" "=d,d")
5220 (and:DI (match_dup 1) (match_dup 2)))]
5221 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5225 [(set_attr "op_type" "RRE,RXY")])
5227 (define_insn "*anddi3_cconly"
5229 (compare (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5230 (match_operand:DI 2 "general_operand" "d,m"))
5232 (clobber (match_scratch:DI 0 "=d,d"))]
5233 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT
5234 /* Do not steal TM patterns. */
5235 && s390_single_part (operands[2], DImode, HImode, 0) < 0"
5239 [(set_attr "op_type" "RRE,RXY")])
5241 (define_insn "*anddi3"
5242 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,d,AQ,Q")
5243 (and:DI (match_operand:DI 1 "nonimmediate_operand"
5244 "%d,o,0,0,0,0,0,0,0,0")
5245 (match_operand:DI 2 "general_operand"
5246 "M,M,N0HDF,N1HDF,N2HDF,N3HDF,d,m,NxQDF,Q")))
5247 (clobber (reg:CC 33))]
5248 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5260 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RRE,RXY,SI,SS")])
5263 [(set (match_operand:DI 0 "s_operand" "")
5264 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5265 (clobber (reg:CC 33))]
5268 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5269 (clobber (reg:CC 33))])]
5270 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5272 (define_expand "anddi3"
5273 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5274 (and:DI (match_operand:DI 1 "nonimmediate_operand" "")
5275 (match_operand:DI 2 "general_operand" "")))
5276 (clobber (reg:CC 33))]
5278 "s390_expand_logical_operator (AND, DImode, operands); DONE;")
5281 ; andsi3 instruction pattern(s).
5284 (define_insn "*andsi3_cc"
5286 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5287 (match_operand:SI 2 "general_operand" "d,R,T"))
5289 (set (match_operand:SI 0 "register_operand" "=d,d,d")
5290 (and:SI (match_dup 1) (match_dup 2)))]
5291 "s390_match_ccmode(insn, CCTmode)"
5296 [(set_attr "op_type" "RR,RX,RXY")])
5298 (define_insn "*andsi3_cconly"
5300 (compare (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5301 (match_operand:SI 2 "general_operand" "d,R,T"))
5303 (clobber (match_scratch:SI 0 "=d,d,d"))]
5304 "s390_match_ccmode(insn, CCTmode)
5305 /* Do not steal TM patterns. */
5306 && s390_single_part (operands[2], SImode, HImode, 0) < 0"
5311 [(set_attr "op_type" "RR,RX,RXY")])
5313 (define_insn "*andsi3_zarch"
5314 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,d,AQ,Q")
5315 (and:SI (match_operand:SI 1 "nonimmediate_operand"
5316 "%d,o,0,0,0,0,0,0,0")
5317 (match_operand:SI 2 "general_operand"
5318 "M,M,N0HSF,N1HSF,d,R,T,NxQSF,Q")))
5319 (clobber (reg:CC 33))]
5320 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5331 [(set_attr "op_type" "RRE,RXE,RI,RI,RR,RX,RXY,SI,SS")])
5333 (define_insn "*andsi3_esa"
5334 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5335 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5336 (match_operand:SI 2 "general_operand" "d,R,NxQSF,Q")))
5337 (clobber (reg:CC 33))]
5338 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5344 [(set_attr "op_type" "RR,RX,SI,SS")])
5347 [(set (match_operand:SI 0 "s_operand" "")
5348 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5349 (clobber (reg:CC 33))]
5352 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5353 (clobber (reg:CC 33))])]
5354 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5356 (define_expand "andsi3"
5357 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5358 (and:SI (match_operand:SI 1 "nonimmediate_operand" "")
5359 (match_operand:SI 2 "general_operand" "")))
5360 (clobber (reg:CC 33))]
5362 "s390_expand_logical_operator (AND, SImode, operands); DONE;")
5365 ; andhi3 instruction pattern(s).
5368 (define_insn "*andhi3_zarch"
5369 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5370 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5371 (match_operand:HI 2 "general_operand" "d,n,NxQHF,Q")))
5372 (clobber (reg:CC 33))]
5373 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5379 [(set_attr "op_type" "RR,RI,SI,SS")])
5381 (define_insn "*andhi3_esa"
5382 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5383 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5384 (match_operand:HI 2 "general_operand" "d,NxQHF,Q")))
5385 (clobber (reg:CC 33))]
5386 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5391 [(set_attr "op_type" "RR,SI,SS")])
5394 [(set (match_operand:HI 0 "s_operand" "")
5395 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5396 (clobber (reg:CC 33))]
5399 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1)))
5400 (clobber (reg:CC 33))])]
5401 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);")
5403 (define_expand "andhi3"
5404 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5405 (and:HI (match_operand:HI 1 "nonimmediate_operand" "")
5406 (match_operand:HI 2 "general_operand" "")))
5407 (clobber (reg:CC 33))]
5409 "s390_expand_logical_operator (AND, HImode, operands); DONE;")
5412 ; andqi3 instruction pattern(s).
5415 (define_insn "*andqi3_zarch"
5416 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5417 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5418 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5419 (clobber (reg:CC 33))]
5420 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5427 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5429 (define_insn "*andqi3_esa"
5430 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5431 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5432 (match_operand:QI 2 "general_operand" "d,n,Q")))
5433 (clobber (reg:CC 33))]
5434 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5439 [(set_attr "op_type" "RR,SI,SS")])
5441 (define_expand "andqi3"
5442 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5443 (and:QI (match_operand:QI 1 "nonimmediate_operand" "")
5444 (match_operand:QI 2 "general_operand" "")))
5445 (clobber (reg:CC 33))]
5447 "s390_expand_logical_operator (AND, QImode, operands); DONE;")
5450 ; Block and (NC) patterns.
5454 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5455 (and:BLK (match_dup 0)
5456 (match_operand:BLK 1 "memory_operand" "Q")))
5457 (use (match_operand 2 "const_int_operand" "n"))
5458 (clobber (reg:CC 33))]
5459 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5460 "nc\t%O0(%2,%R0),%S1"
5461 [(set_attr "op_type" "SS")])
5464 [(set (match_operand 0 "memory_operand" "")
5466 (match_operand 1 "memory_operand" "")))
5467 (clobber (reg:CC 33))]
5469 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5470 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5472 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1)))
5474 (clobber (reg:CC 33))])]
5476 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5477 operands[0] = adjust_address (operands[0], BLKmode, 0);
5478 operands[1] = adjust_address (operands[1], BLKmode, 0);
5483 [(set (match_operand:BLK 0 "memory_operand" "")
5484 (and:BLK (match_dup 0)
5485 (match_operand:BLK 1 "memory_operand" "")))
5486 (use (match_operand 2 "const_int_operand" ""))
5487 (clobber (reg:CC 33))])
5489 [(set (match_operand:BLK 3 "memory_operand" "")
5490 (and:BLK (match_dup 3)
5491 (match_operand:BLK 4 "memory_operand" "")))
5492 (use (match_operand 5 "const_int_operand" ""))
5493 (clobber (reg:CC 33))])]
5494 "s390_offset_p (operands[0], operands[3], operands[2])
5495 && s390_offset_p (operands[1], operands[4], operands[2])
5496 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5498 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7)))
5500 (clobber (reg:CC 33))])]
5501 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5502 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5503 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5507 ;;- Bit set (inclusive or) instructions.
5511 ; iordi3 instruction pattern(s).
5514 (define_insn "*iordi3_cc"
5516 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5517 (match_operand:DI 2 "general_operand" "d,m"))
5519 (set (match_operand:DI 0 "register_operand" "=d,d")
5520 (ior:DI (match_dup 1) (match_dup 2)))]
5521 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5525 [(set_attr "op_type" "RRE,RXY")])
5527 (define_insn "*iordi3_cconly"
5529 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5530 (match_operand:DI 2 "general_operand" "d,m"))
5532 (clobber (match_scratch:DI 0 "=d,d"))]
5533 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5537 [(set_attr "op_type" "RRE,RXY")])
5539 (define_insn "*iordi3"
5540 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,AQ,Q")
5541 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0,0")
5542 (match_operand:DI 2 "general_operand"
5543 "N0HD0,N1HD0,N2HD0,N3HD0,d,m,NxQD0,Q")))
5544 (clobber (reg:CC 33))]
5545 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5555 [(set_attr "op_type" "RI,RI,RI,RI,RRE,RXY,SI,SS")])
5558 [(set (match_operand:DI 0 "s_operand" "")
5559 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5560 (clobber (reg:CC 33))]
5563 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5564 (clobber (reg:CC 33))])]
5565 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5567 (define_expand "iordi3"
5568 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5569 (ior:DI (match_operand:DI 1 "nonimmediate_operand" "")
5570 (match_operand:DI 2 "general_operand" "")))
5571 (clobber (reg:CC 33))]
5573 "s390_expand_logical_operator (IOR, DImode, operands); DONE;")
5576 ; iorsi3 instruction pattern(s).
5579 (define_insn "*iorsi3_cc"
5581 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5582 (match_operand:SI 2 "general_operand" "d,R,T"))
5584 (set (match_operand:SI 0 "register_operand" "=d,d,d")
5585 (ior:SI (match_dup 1) (match_dup 2)))]
5586 "s390_match_ccmode(insn, CCTmode)"
5591 [(set_attr "op_type" "RR,RX,RXY")])
5593 (define_insn "*iorsi3_cconly"
5595 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5596 (match_operand:SI 2 "general_operand" "d,R,T"))
5598 (clobber (match_scratch:SI 0 "=d,d,d"))]
5599 "s390_match_ccmode(insn, CCTmode)"
5604 [(set_attr "op_type" "RR,RX,RXY")])
5606 (define_insn "*iorsi3_zarch"
5607 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,AQ,Q")
5608 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0,0,0")
5609 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,d,R,T,NxQS0,Q")))
5610 (clobber (reg:CC 33))]
5611 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5620 [(set_attr "op_type" "RI,RI,RR,RX,RXY,SI,SS")])
5622 (define_insn "*iorsi3_esa"
5623 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5624 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0")
5625 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q")))
5626 (clobber (reg:CC 33))]
5627 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5633 [(set_attr "op_type" "RR,RX,SI,SS")])
5636 [(set (match_operand:SI 0 "s_operand" "")
5637 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5638 (clobber (reg:CC 33))]
5641 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5642 (clobber (reg:CC 33))])]
5643 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5645 (define_expand "iorsi3"
5646 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5647 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "")
5648 (match_operand:SI 2 "general_operand" "")))
5649 (clobber (reg:CC 33))]
5651 "s390_expand_logical_operator (IOR, SImode, operands); DONE;")
5654 ; iorhi3 instruction pattern(s).
5657 (define_insn "*iorhi3_zarch"
5658 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5659 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0,0")
5660 (match_operand:HI 2 "general_operand" "d,n,NxQH0,Q")))
5661 (clobber (reg:CC 33))]
5662 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5668 [(set_attr "op_type" "RR,RI,SI,SS")])
5670 (define_insn "*iorhi3_esa"
5671 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5672 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5673 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5674 (clobber (reg:CC 33))]
5675 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5680 [(set_attr "op_type" "RR,SI,SS")])
5683 [(set (match_operand:HI 0 "s_operand" "")
5684 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5685 (clobber (reg:CC 33))]
5688 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1)))
5689 (clobber (reg:CC 33))])]
5690 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);")
5692 (define_expand "iorhi3"
5693 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5694 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "")
5695 (match_operand:HI 2 "general_operand" "")))
5696 (clobber (reg:CC 33))]
5698 "s390_expand_logical_operator (IOR, HImode, operands); DONE;")
5701 ; iorqi3 instruction pattern(s).
5704 (define_insn "*iorqi3_zarch"
5705 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,Q,S,Q")
5706 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0,0")
5707 (match_operand:QI 2 "general_operand" "d,n,n,n,Q")))
5708 (clobber (reg:CC 33))]
5709 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5716 [(set_attr "op_type" "RR,RI,SI,SIY,SS")])
5718 (define_insn "*iorqi3_esa"
5719 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q")
5720 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0")
5721 (match_operand:QI 2 "general_operand" "d,n,Q")))
5722 (clobber (reg:CC 33))]
5723 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)"
5728 [(set_attr "op_type" "RR,SI,SS")])
5730 (define_expand "iorqi3"
5731 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5732 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "")
5733 (match_operand:QI 2 "general_operand" "")))
5734 (clobber (reg:CC 33))]
5736 "s390_expand_logical_operator (IOR, QImode, operands); DONE;")
5739 ; Block inclusive or (OC) patterns.
5743 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5744 (ior:BLK (match_dup 0)
5745 (match_operand:BLK 1 "memory_operand" "Q")))
5746 (use (match_operand 2 "const_int_operand" "n"))
5747 (clobber (reg:CC 33))]
5748 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5749 "oc\t%O0(%2,%R0),%S1"
5750 [(set_attr "op_type" "SS")])
5753 [(set (match_operand 0 "memory_operand" "")
5755 (match_operand 1 "memory_operand" "")))
5756 (clobber (reg:CC 33))]
5758 && GET_MODE (operands[0]) == GET_MODE (operands[1])
5759 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
5761 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1)))
5763 (clobber (reg:CC 33))])]
5765 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
5766 operands[0] = adjust_address (operands[0], BLKmode, 0);
5767 operands[1] = adjust_address (operands[1], BLKmode, 0);
5772 [(set (match_operand:BLK 0 "memory_operand" "")
5773 (ior:BLK (match_dup 0)
5774 (match_operand:BLK 1 "memory_operand" "")))
5775 (use (match_operand 2 "const_int_operand" ""))
5776 (clobber (reg:CC 33))])
5778 [(set (match_operand:BLK 3 "memory_operand" "")
5779 (ior:BLK (match_dup 3)
5780 (match_operand:BLK 4 "memory_operand" "")))
5781 (use (match_operand 5 "const_int_operand" ""))
5782 (clobber (reg:CC 33))])]
5783 "s390_offset_p (operands[0], operands[3], operands[2])
5784 && s390_offset_p (operands[1], operands[4], operands[2])
5785 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
5787 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7)))
5789 (clobber (reg:CC 33))])]
5790 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
5791 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
5792 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
5796 ;;- Xor instructions.
5800 ; xordi3 instruction pattern(s).
5803 (define_insn "*xordi3_cc"
5805 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5806 (match_operand:DI 2 "general_operand" "d,m"))
5808 (set (match_operand:DI 0 "register_operand" "=d,d")
5809 (xor:DI (match_dup 1) (match_dup 2)))]
5810 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5814 [(set_attr "op_type" "RRE,RXY")])
5816 (define_insn "*xordi3_cconly"
5818 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
5819 (match_operand:DI 2 "general_operand" "d,m"))
5821 (clobber (match_scratch:DI 0 "=d,d"))]
5822 "s390_match_ccmode(insn, CCTmode) && TARGET_64BIT"
5826 [(set_attr "op_type" "RRE,RXY")])
5828 (define_insn "*xordi3"
5829 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,AQ,Q")
5830 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0")
5831 (match_operand:DI 2 "general_operand" "d,m,NxQD0,Q")))
5832 (clobber (reg:CC 33))]
5833 "TARGET_64BIT && s390_logical_operator_ok_p (operands)"
5839 [(set_attr "op_type" "RRE,RXY,SI,SS")])
5842 [(set (match_operand:DI 0 "s_operand" "")
5843 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" "")))
5844 (clobber (reg:CC 33))]
5847 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5848 (clobber (reg:CC 33))])]
5849 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5851 (define_expand "xordi3"
5852 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5853 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "")
5854 (match_operand:DI 2 "general_operand" "")))
5855 (clobber (reg:CC 33))]
5857 "s390_expand_logical_operator (XOR, DImode, operands); DONE;")
5860 ; xorsi3 instruction pattern(s).
5863 (define_insn "*xorsi3_cc"
5865 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5866 (match_operand:SI 2 "general_operand" "d,R,T"))
5868 (set (match_operand:SI 0 "register_operand" "=d,d,d")
5869 (xor:SI (match_dup 1) (match_dup 2)))]
5870 "s390_match_ccmode(insn, CCTmode)"
5875 [(set_attr "op_type" "RR,RX,RXY")])
5877 (define_insn "*xorsi3_cconly"
5879 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0")
5880 (match_operand:SI 2 "general_operand" "d,R,T"))
5882 (clobber (match_scratch:SI 0 "=d,d,d"))]
5883 "s390_match_ccmode(insn, CCTmode)"
5888 [(set_attr "op_type" "RR,RX,RXY")])
5890 (define_insn "*xorsi3"
5891 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,AQ,Q")
5892 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0")
5893 (match_operand:SI 2 "general_operand" "d,R,T,NxQS0,Q")))
5894 (clobber (reg:CC 33))]
5895 "s390_logical_operator_ok_p (operands)"
5902 [(set_attr "op_type" "RR,RX,RXY,SI,SS")])
5905 [(set (match_operand:SI 0 "s_operand" "")
5906 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" "")))
5907 (clobber (reg:CC 33))]
5910 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5911 (clobber (reg:CC 33))])]
5912 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5914 (define_expand "xorsi3"
5915 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5916 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "")
5917 (match_operand:SI 2 "general_operand" "")))
5918 (clobber (reg:CC 33))]
5920 "s390_expand_logical_operator (XOR, SImode, operands); DONE;")
5923 ; xorhi3 instruction pattern(s).
5926 (define_insn "*xorhi3"
5927 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q")
5928 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0")
5929 (match_operand:HI 2 "general_operand" "d,NxQH0,Q")))
5930 (clobber (reg:CC 33))]
5931 "s390_logical_operator_ok_p (operands)"
5936 [(set_attr "op_type" "RR,SI,SS")])
5939 [(set (match_operand:HI 0 "s_operand" "")
5940 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" "")))
5941 (clobber (reg:CC 33))]
5944 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1)))
5945 (clobber (reg:CC 33))])]
5946 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);")
5948 (define_expand "xorhi3"
5949 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5950 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "")
5951 (match_operand:HI 2 "general_operand" "")))
5952 (clobber (reg:CC 33))]
5954 "s390_expand_logical_operator (XOR, HImode, operands); DONE;")
5957 ; xorqi3 instruction pattern(s).
5960 (define_insn "*xorqi3"
5961 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,S,Q")
5962 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0,0")
5963 (match_operand:QI 2 "general_operand" "d,n,n,Q")))
5964 (clobber (reg:CC 33))]
5965 "s390_logical_operator_ok_p (operands)"
5971 [(set_attr "op_type" "RR,SI,SIY,SS")])
5973 (define_expand "xorqi3"
5974 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5975 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "")
5976 (match_operand:QI 2 "general_operand" "")))
5977 (clobber (reg:CC 33))]
5979 "s390_expand_logical_operator (XOR, QImode, operands); DONE;")
5982 ; Block exclusive or (XC) patterns.
5986 [(set (match_operand:BLK 0 "memory_operand" "=Q")
5987 (xor:BLK (match_dup 0)
5988 (match_operand:BLK 1 "memory_operand" "Q")))
5989 (use (match_operand 2 "const_int_operand" "n"))
5990 (clobber (reg:CC 33))]
5991 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256"
5992 "xc\t%O0(%2,%R0),%S1"
5993 [(set_attr "op_type" "SS")])
5996 [(set (match_operand 0 "memory_operand" "")
5998 (match_operand 1 "memory_operand" "")))
5999 (clobber (reg:CC 33))]
6001 && GET_MODE (operands[0]) == GET_MODE (operands[1])
6002 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0"
6004 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1)))
6006 (clobber (reg:CC 33))])]
6008 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0])));
6009 operands[0] = adjust_address (operands[0], BLKmode, 0);
6010 operands[1] = adjust_address (operands[1], BLKmode, 0);
6015 [(set (match_operand:BLK 0 "memory_operand" "")
6016 (xor:BLK (match_dup 0)
6017 (match_operand:BLK 1 "memory_operand" "")))
6018 (use (match_operand 2 "const_int_operand" ""))
6019 (clobber (reg:CC 33))])
6021 [(set (match_operand:BLK 3 "memory_operand" "")
6022 (xor:BLK (match_dup 3)
6023 (match_operand:BLK 4 "memory_operand" "")))
6024 (use (match_operand 5 "const_int_operand" ""))
6025 (clobber (reg:CC 33))])]
6026 "s390_offset_p (operands[0], operands[3], operands[2])
6027 && s390_offset_p (operands[1], operands[4], operands[2])
6028 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256"
6030 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7)))
6032 (clobber (reg:CC 33))])]
6033 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6034 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0));
6035 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));")
6038 ; Block xor (XC) patterns with src == dest.
6041 (define_insn "*xc_zero"
6042 [(set (match_operand:BLK 0 "memory_operand" "=Q")
6044 (use (match_operand 1 "const_int_operand" "n"))
6045 (clobber (reg:CC 33))]
6046 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256"
6047 "xc\t%O0(%1,%R0),%S0"
6048 [(set_attr "op_type" "SS")])
6052 [(set (match_operand:BLK 0 "memory_operand" "")
6054 (use (match_operand 1 "const_int_operand" ""))
6055 (clobber (reg:CC 33))])
6057 [(set (match_operand:BLK 2 "memory_operand" "")
6059 (use (match_operand 3 "const_int_operand" ""))
6060 (clobber (reg:CC 33))])]
6061 "s390_offset_p (operands[0], operands[2], operands[1])
6062 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256"
6064 [(set (match_dup 4) (const_int 0))
6066 (clobber (reg:CC 33))])]
6067 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0));
6068 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));")
6072 ;;- Negate instructions.
6076 ; negdi2 instruction pattern(s).
6079 (define_expand "negdi2"
6081 [(set (match_operand:DI 0 "register_operand" "=d")
6082 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6083 (clobber (reg:CC 33))])]
6087 (define_insn "*negdi2_sign_cc"
6089 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI
6090 (match_operand:SI 1 "register_operand" "d") 0)
6091 (const_int 32)) (const_int 32)))
6093 (set (match_operand:DI 0 "register_operand" "=d")
6094 (neg:DI (sign_extend:DI (match_dup 1))))]
6095 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6097 [(set_attr "op_type" "RRE")])
6099 (define_insn "*negdi2_sign"
6100 [(set (match_operand:DI 0 "register_operand" "=d")
6101 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6102 (clobber (reg:CC 33))]
6105 [(set_attr "op_type" "RRE")])
6107 (define_insn "*negdi2_cc"
6109 (compare (neg:DI (match_operand:DI 1 "register_operand" "d"))
6111 (set (match_operand:DI 0 "register_operand" "=d")
6112 (neg:DI (match_dup 1)))]
6113 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6115 [(set_attr "op_type" "RRE")])
6117 (define_insn "*negdi2_cconly"
6119 (compare (neg:DI (match_operand:DI 1 "register_operand" "d"))
6121 (clobber (match_scratch:DI 0 "=d"))]
6122 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6124 [(set_attr "op_type" "RRE")])
6126 (define_insn "*negdi2_64"
6127 [(set (match_operand:DI 0 "register_operand" "=d")
6128 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6129 (clobber (reg:CC 33))]
6132 [(set_attr "op_type" "RRE")])
6134 (define_insn_and_split "*negdi2_31"
6135 [(set (match_operand:DI 0 "register_operand" "=d")
6136 (neg:DI (match_operand:DI 1 "register_operand" "d")))
6137 (clobber (reg:CC 33))]
6140 "&& reload_completed"
6142 [(set (match_dup 2) (neg:SI (match_dup 3)))
6143 (clobber (reg:CC 33))])
6146 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0)))
6147 (set (match_dup 4) (neg:SI (match_dup 5)))])
6149 (if_then_else (ne (reg:CCAP 33) (const_int 0))
6151 (label_ref (match_dup 6))))
6153 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1)))
6154 (clobber (reg:CC 33))])
6156 "operands[2] = operand_subword (operands[0], 0, 0, DImode);
6157 operands[3] = operand_subword (operands[1], 0, 0, DImode);
6158 operands[4] = operand_subword (operands[0], 1, 0, DImode);
6159 operands[5] = operand_subword (operands[1], 1, 0, DImode);
6160 operands[6] = gen_label_rtx ();")
6163 ; negsi2 instruction pattern(s).
6166 (define_insn "*negsi2_cc"
6168 (compare (neg:SI (match_operand:SI 1 "register_operand" "d"))
6170 (set (match_operand:SI 0 "register_operand" "=d")
6171 (neg:SI (match_dup 1)))]
6172 "s390_match_ccmode (insn, CCAmode)"
6174 [(set_attr "op_type" "RR")])
6176 (define_insn "*negsi2_cconly"
6178 (compare (neg:SI (match_operand:SI 1 "register_operand" "d"))
6180 (clobber (match_scratch:SI 0 "=d"))]
6181 "s390_match_ccmode (insn, CCAmode)"
6183 [(set_attr "op_type" "RR")])
6185 (define_insn "negsi2"
6186 [(set (match_operand:SI 0 "register_operand" "=d")
6187 (neg:SI (match_operand:SI 1 "register_operand" "d")))
6188 (clobber (reg:CC 33))]
6191 [(set_attr "op_type" "RR")])
6194 ; negdf2 instruction pattern(s).
6197 (define_expand "negdf2"
6199 [(set (match_operand:DF 0 "register_operand" "=f")
6200 (neg:DF (match_operand:DF 1 "register_operand" "f")))
6201 (clobber (reg:CC 33))])]
6205 (define_insn "*negdf2_cc"
6207 (compare (neg:DF (match_operand:DF 1 "register_operand" "f"))
6208 (match_operand:DF 2 "const0_operand" "")))
6209 (set (match_operand:DF 0 "register_operand" "=f")
6210 (neg:DF (match_dup 1)))]
6211 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6213 [(set_attr "op_type" "RRE")
6214 (set_attr "type" "fsimpd")])
6216 (define_insn "*negdf2_cconly"
6218 (compare (neg:DF (match_operand:DF 1 "register_operand" "f"))
6219 (match_operand:DF 2 "const0_operand" "")))
6220 (clobber (match_scratch:DF 0 "=f"))]
6221 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6223 [(set_attr "op_type" "RRE")
6224 (set_attr "type" "fsimpd")])
6226 (define_insn "*negdf2"
6227 [(set (match_operand:DF 0 "register_operand" "=f")
6228 (neg:DF (match_operand:DF 1 "register_operand" "f")))
6229 (clobber (reg:CC 33))]
6230 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6232 [(set_attr "op_type" "RRE")
6233 (set_attr "type" "fsimpd")])
6235 (define_insn "*negdf2_ibm"
6236 [(set (match_operand:DF 0 "register_operand" "=f")
6237 (neg:DF (match_operand:DF 1 "register_operand" "f")))
6238 (clobber (reg:CC 33))]
6239 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6241 [(set_attr "op_type" "RR")
6242 (set_attr "type" "fsimpd")])
6245 ; negsf2 instruction pattern(s).
6248 (define_expand "negsf2"
6250 [(set (match_operand:SF 0 "register_operand" "=f")
6251 (neg:SF (match_operand:SF 1 "register_operand" "f")))
6252 (clobber (reg:CC 33))])]
6256 (define_insn "*negsf2_cc"
6258 (compare (neg:SF (match_operand:SF 1 "register_operand" "f"))
6259 (match_operand:SF 2 "const0_operand" "")))
6260 (set (match_operand:SF 0 "register_operand" "=f")
6261 (neg:SF (match_dup 1)))]
6262 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6264 [(set_attr "op_type" "RRE")
6265 (set_attr "type" "fsimps")])
6267 (define_insn "*negsf2_cconly"
6269 (compare (neg:SF (match_operand:SF 1 "register_operand" "f"))
6270 (match_operand:SF 2 "const0_operand" "")))
6271 (clobber (match_scratch:SF 0 "=f"))]
6272 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6274 [(set_attr "op_type" "RRE")
6275 (set_attr "type" "fsimps")])
6277 (define_insn "*negsf2"
6278 [(set (match_operand:SF 0 "register_operand" "=f")
6279 (neg:SF (match_operand:SF 1 "register_operand" "f")))
6280 (clobber (reg:CC 33))]
6281 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6283 [(set_attr "op_type" "RRE")
6284 (set_attr "type" "fsimps")])
6286 (define_insn "*negsf2"
6287 [(set (match_operand:SF 0 "register_operand" "=f")
6288 (neg:SF (match_operand:SF 1 "register_operand" "f")))
6289 (clobber (reg:CC 33))]
6290 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6292 [(set_attr "op_type" "RR")
6293 (set_attr "type" "fsimps")])
6297 ;;- Absolute value instructions.
6301 ; absdi2 instruction pattern(s).
6304 (define_insn "*absdi2_sign_cc"
6306 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6307 (match_operand:SI 1 "register_operand" "d") 0)
6308 (const_int 32)) (const_int 32)))
6310 (set (match_operand:DI 0 "register_operand" "=d")
6311 (abs:DI (sign_extend:DI (match_dup 1))))]
6312 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6314 [(set_attr "op_type" "RRE")])
6316 (define_insn "*absdi2_sign"
6317 [(set (match_operand:DI 0 "register_operand" "=d")
6318 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))))
6319 (clobber (reg:CC 33))]
6322 [(set_attr "op_type" "RRE")])
6324 (define_insn "*absdi2_cc"
6326 (compare (abs:DI (match_operand:DI 1 "register_operand" "d"))
6328 (set (match_operand:DI 0 "register_operand" "=d")
6329 (abs:DI (match_dup 1)))]
6330 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6332 [(set_attr "op_type" "RRE")])
6334 (define_insn "*absdi2_cconly"
6336 (compare (abs:DI (match_operand:DI 1 "register_operand" "d"))
6338 (clobber (match_scratch:DI 0 "=d"))]
6339 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6341 [(set_attr "op_type" "RRE")])
6343 (define_insn "absdi2"
6344 [(set (match_operand:DI 0 "register_operand" "=d")
6345 (abs:DI (match_operand:DI 1 "register_operand" "d")))
6346 (clobber (reg:CC 33))]
6349 [(set_attr "op_type" "RRE")])
6352 ; abssi2 instruction pattern(s).
6355 (define_insn "*abssi2_cc"
6357 (compare (abs:SI (match_operand:SI 1 "register_operand" "d"))
6359 (set (match_operand:SI 0 "register_operand" "=d")
6360 (abs:SI (match_dup 1)))]
6361 "s390_match_ccmode (insn, CCAmode)"
6363 [(set_attr "op_type" "RR")])
6365 (define_insn "*abssi2_cconly"
6367 (compare (abs:SI (match_operand:SI 1 "register_operand" "d"))
6369 (clobber (match_scratch:SI 0 "=d"))]
6370 "s390_match_ccmode (insn, CCAmode)"
6372 [(set_attr "op_type" "RR")])
6374 (define_insn "abssi2"
6375 [(set (match_operand:SI 0 "register_operand" "=d")
6376 (abs:SI (match_operand:SI 1 "register_operand" "d")))
6377 (clobber (reg:CC 33))]
6380 [(set_attr "op_type" "RR")])
6383 ; absdf2 instruction pattern(s).
6386 (define_expand "absdf2"
6388 [(set (match_operand:DF 0 "register_operand" "=f")
6389 (abs:DF (match_operand:DF 1 "register_operand" "f")))
6390 (clobber (reg:CC 33))])]
6394 (define_insn "*absdf2_cc"
6396 (compare (abs:DF (match_operand:DF 1 "register_operand" "f"))
6397 (match_operand:DF 2 "const0_operand" "")))
6398 (set (match_operand:DF 0 "register_operand" "=f")
6399 (abs:DF (match_dup 1)))]
6400 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6402 [(set_attr "op_type" "RRE")
6403 (set_attr "type" "fsimpd")])
6405 (define_insn "*absdf2_cconly"
6407 (compare (abs:DF (match_operand:DF 1 "register_operand" "f"))
6408 (match_operand:DF 2 "const0_operand" "")))
6409 (clobber (match_scratch:DF 0 "=f"))]
6410 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6412 [(set_attr "op_type" "RRE")
6413 (set_attr "type" "fsimpd")])
6415 (define_insn "*absdf2"
6416 [(set (match_operand:DF 0 "register_operand" "=f")
6417 (abs:DF (match_operand:DF 1 "register_operand" "f")))
6418 (clobber (reg:CC 33))]
6419 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6421 [(set_attr "op_type" "RRE")
6422 (set_attr "type" "fsimpd")])
6424 (define_insn "*absdf2_ibm"
6425 [(set (match_operand:DF 0 "register_operand" "=f")
6426 (abs:DF (match_operand:DF 1 "register_operand" "f")))
6427 (clobber (reg:CC 33))]
6428 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6430 [(set_attr "op_type" "RR")
6431 (set_attr "type" "fsimpd")])
6434 ; abssf2 instruction pattern(s).
6437 (define_expand "abssf2"
6439 [(set (match_operand:SF 0 "register_operand" "=f")
6440 (abs:SF (match_operand:SF 1 "register_operand" "f")))
6441 (clobber (reg:CC 33))])]
6445 (define_insn "*abssf2_cc"
6447 (compare (abs:SF (match_operand:SF 1 "register_operand" "f"))
6448 (match_operand:SF 2 "const0_operand" "")))
6449 (set (match_operand:SF 0 "register_operand" "=f")
6450 (abs:SF (match_dup 1)))]
6451 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6453 [(set_attr "op_type" "RRE")
6454 (set_attr "type" "fsimps")])
6456 (define_insn "*abssf2_cconly"
6458 (compare (abs:SF (match_operand:SF 1 "register_operand" "f"))
6459 (match_operand:SF 2 "const0_operand" "")))
6460 (clobber (match_scratch:SF 0 "=f"))]
6461 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6463 [(set_attr "op_type" "RRE")
6464 (set_attr "type" "fsimps")])
6466 (define_insn "*abssf2"
6467 [(set (match_operand:SF 0 "register_operand" "=f")
6468 (abs:SF (match_operand:SF 1 "register_operand" "f")))
6469 (clobber (reg:CC 33))]
6470 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6472 [(set_attr "op_type" "RRE")
6473 (set_attr "type" "fsimps")])
6475 (define_insn "*abssf2_ibm"
6476 [(set (match_operand:SF 0 "register_operand" "=f")
6477 (abs:SF (match_operand:SF 1 "register_operand" "f")))
6478 (clobber (reg:CC 33))]
6479 "TARGET_HARD_FLOAT && TARGET_IBM_FLOAT"
6481 [(set_attr "op_type" "RR")
6482 (set_attr "type" "fsimps")])
6485 ;;- Negated absolute value instructions
6492 (define_insn "*negabsdi2_sign_cc"
6494 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI
6495 (match_operand:SI 1 "register_operand" "d") 0)
6496 (const_int 32)) (const_int 32))))
6498 (set (match_operand:DI 0 "register_operand" "=d")
6499 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
6500 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6502 [(set_attr "op_type" "RRE")])
6504 (define_insn "*negabsdi2_sign"
6505 [(set (match_operand:DI 0 "register_operand" "=d")
6506 (neg:DI (abs:DI (sign_extend:DI
6507 (match_operand:SI 1 "register_operand" "d")))))
6508 (clobber (reg:CC 33))]
6511 [(set_attr "op_type" "RRE")])
6513 (define_insn "*negabsdi2_cc"
6515 (compare (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d")))
6517 (set (match_operand:DI 0 "register_operand" "=d")
6518 (neg:DI (abs:DI (match_dup 1))))]
6519 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6521 [(set_attr "op_type" "RRE")])
6523 (define_insn "*negabsdi2_cconly"
6525 (compare (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d")))
6527 (clobber (match_scratch:DI 0 "=d"))]
6528 "TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
6530 [(set_attr "op_type" "RRE")])
6532 (define_insn "*negabsdi2"
6533 [(set (match_operand:DI 0 "register_operand" "=d")
6534 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" "d"))))
6535 (clobber (reg:CC 33))]
6538 [(set_attr "op_type" "RRE")])
6540 (define_insn "*negabssi2_cc"
6542 (compare (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d")))
6544 (set (match_operand:SI 0 "register_operand" "=d")
6545 (neg:SI (abs:SI (match_dup 1))))]
6546 "s390_match_ccmode (insn, CCAmode)"
6548 [(set_attr "op_type" "RR")])
6550 (define_insn "*negabssi2_cconly"
6552 (compare (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d")))
6554 (clobber (match_scratch:SI 0 "=d"))]
6555 "s390_match_ccmode (insn, CCAmode)"
6557 [(set_attr "op_type" "RR")])
6559 (define_insn "*negabssi2"
6560 [(set (match_operand:SI 0 "register_operand" "=d")
6561 (neg:SI (abs:SI (match_operand:SI 1 "register_operand" "d"))))
6562 (clobber (reg:CC 33))]
6565 [(set_attr "op_type" "RR")])
6571 (define_insn "*negabsdf2_cc"
6573 (compare (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))
6574 (match_operand:DF 2 "const0_operand" "")))
6575 (set (match_operand:DF 0 "register_operand" "=f")
6576 (neg:DF (abs:DF (match_dup 1))))]
6577 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6579 [(set_attr "op_type" "RRE")
6580 (set_attr "type" "fsimpd")])
6582 (define_insn "*negabsdf2_cconly"
6584 (compare (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f")))
6585 (match_operand:DF 2 "const0_operand" "")))
6586 (clobber (match_scratch:DF 0 "=f"))]
6587 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6589 [(set_attr "op_type" "RRE")
6590 (set_attr "type" "fsimpd")])
6592 (define_insn "*negabsdf2"
6593 [(set (match_operand:DF 0 "register_operand" "=f")
6594 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6595 (clobber (reg:CC 33))]
6596 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6598 [(set_attr "op_type" "RRE")
6599 (set_attr "type" "fsimpd")])
6601 (define_insn "*negabssf2_cc"
6603 (compare (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))
6604 (match_operand:SF 2 "const0_operand" "")))
6605 (set (match_operand:SF 0 "register_operand" "=f")
6606 (neg:SF (abs:SF (match_dup 1))))]
6607 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6609 [(set_attr "op_type" "RRE")
6610 (set_attr "type" "fsimps")])
6612 (define_insn "*negabssf2_cconly"
6614 (compare (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f")))
6615 (match_operand:SF 2 "const0_operand" "")))
6616 (clobber (match_scratch:SF 0 "=f"))]
6617 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6619 [(set_attr "op_type" "RRE")
6620 (set_attr "type" "fsimps")])
6622 (define_insn "*negabssf2"
6623 [(set (match_operand:SF 0 "register_operand" "=f")
6624 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6625 (clobber (reg:CC 33))]
6626 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6628 [(set_attr "op_type" "RRE")
6629 (set_attr "type" "fsimps")])
6632 ;;- Square root instructions.
6636 ; sqrtdf2 instruction pattern(s).
6639 (define_insn "sqrtdf2"
6640 [(set (match_operand:DF 0 "register_operand" "=f,f")
6641 (sqrt:DF (match_operand:DF 1 "general_operand" "f,R")))]
6642 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6646 [(set_attr "op_type" "RRE,RXE")
6647 (set_attr "type" "fsqrtd")])
6650 ; sqrtsf2 instruction pattern(s).
6653 (define_insn "sqrtsf2"
6654 [(set (match_operand:SF 0 "register_operand" "=f,f")
6655 (sqrt:SF (match_operand:SF 1 "general_operand" "f,R")))]
6656 "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT"
6660 [(set_attr "op_type" "RRE,RXE")
6661 (set_attr "type" "fsqrts")])
6664 ;;- One complement instructions.
6668 ; one_cmpldi2 instruction pattern(s).
6671 (define_expand "one_cmpldi2"
6673 [(set (match_operand:DI 0 "register_operand" "")
6674 (xor:DI (match_operand:DI 1 "register_operand" "")
6676 (clobber (reg:CC 33))])]
6681 ; one_cmplsi2 instruction pattern(s).
6684 (define_expand "one_cmplsi2"
6686 [(set (match_operand:SI 0 "register_operand" "")
6687 (xor:SI (match_operand:SI 1 "register_operand" "")
6689 (clobber (reg:CC 33))])]
6694 ; one_cmplhi2 instruction pattern(s).
6697 (define_expand "one_cmplhi2"
6699 [(set (match_operand:HI 0 "register_operand" "")
6700 (xor:HI (match_operand:HI 1 "register_operand" "")
6702 (clobber (reg:CC 33))])]
6707 ; one_cmplqi2 instruction pattern(s).
6710 (define_expand "one_cmplqi2"
6712 [(set (match_operand:QI 0 "register_operand" "")
6713 (xor:QI (match_operand:QI 1 "register_operand" "")
6715 (clobber (reg:CC 33))])]
6721 ;;- Rotate instructions.
6725 ; rotldi3 instruction pattern(s).
6728 (define_insn "rotldi3"
6729 [(set (match_operand:DI 0 "register_operand" "=d")
6730 (rotate:DI (match_operand:DI 1 "register_operand" "d")
6731 (match_operand:SI 2 "shift_count_operand" "Y")))]
6734 [(set_attr "op_type" "RSE")
6735 (set_attr "atype" "reg")])
6738 ; rotlsi3 instruction pattern(s).
6741 (define_insn "rotlsi3"
6742 [(set (match_operand:SI 0 "register_operand" "=d")
6743 (rotate:SI (match_operand:SI 1 "register_operand" "d")
6744 (match_operand:SI 2 "shift_count_operand" "Y")))]
6747 [(set_attr "op_type" "RSE")
6748 (set_attr "atype" "reg")])
6752 ;;- Arithmetic shift instructions.
6756 ; ashldi3 instruction pattern(s).
6759 (define_expand "ashldi3"
6760 [(set (match_operand:DI 0 "register_operand" "")
6761 (ashift:DI (match_operand:DI 1 "register_operand" "")
6762 (match_operand:SI 2 "shift_count_operand" "")))]
6766 (define_insn "*ashldi3_31"
6767 [(set (match_operand:DI 0 "register_operand" "=d")
6768 (ashift:DI (match_operand:DI 1 "register_operand" "0")
6769 (match_operand:SI 2 "shift_count_operand" "Y")))]
6772 [(set_attr "op_type" "RS")
6773 (set_attr "atype" "reg")])
6775 (define_insn "*ashldi3_64"
6776 [(set (match_operand:DI 0 "register_operand" "=d")
6777 (ashift:DI (match_operand:DI 1 "register_operand" "d")
6778 (match_operand:SI 2 "shift_count_operand" "Y")))]
6781 [(set_attr "op_type" "RSE")
6782 (set_attr "atype" "reg")])
6785 ; ashrdi3 instruction pattern(s).
6788 (define_expand "ashrdi3"
6790 [(set (match_operand:DI 0 "register_operand" "")
6791 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6792 (match_operand:SI 2 "shift_count_operand" "")))
6793 (clobber (reg:CC 33))])]
6797 (define_insn "*ashrdi3_cc_31"
6799 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6800 (match_operand:SI 2 "shift_count_operand" "Y"))
6802 (set (match_operand:DI 0 "register_operand" "=d")
6803 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6804 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6806 [(set_attr "op_type" "RS")
6807 (set_attr "atype" "reg")])
6809 (define_insn "*ashrdi3_cconly_31"
6811 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6812 (match_operand:SI 2 "shift_count_operand" "Y"))
6814 (clobber (match_scratch:DI 0 "=d"))]
6815 "!TARGET_64BIT && s390_match_ccmode(insn, CCSmode)"
6817 [(set_attr "op_type" "RS")
6818 (set_attr "atype" "reg")])
6820 (define_insn "*ashrdi3_31"
6821 [(set (match_operand:DI 0 "register_operand" "=d")
6822 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
6823 (match_operand:SI 2 "shift_count_operand" "Y")))
6824 (clobber (reg:CC 33))]
6827 [(set_attr "op_type" "RS")
6828 (set_attr "atype" "reg")])
6830 (define_insn "*ashrdi3_cc_64"
6832 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6833 (match_operand:SI 2 "shift_count_operand" "Y"))
6835 (set (match_operand:DI 0 "register_operand" "=d")
6836 (ashiftrt:DI (match_dup 1) (match_dup 2)))]
6837 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
6839 [(set_attr "op_type" "RSE")
6840 (set_attr "atype" "reg")])
6842 (define_insn "*ashrdi3_cconly_64"
6844 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6845 (match_operand:SI 2 "shift_count_operand" "Y"))
6847 (clobber (match_scratch:DI 0 "=d"))]
6848 "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT"
6850 [(set_attr "op_type" "RSE")
6851 (set_attr "atype" "reg")])
6853 (define_insn "*ashrdi3_64"
6854 [(set (match_operand:DI 0 "register_operand" "=d")
6855 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
6856 (match_operand:SI 2 "shift_count_operand" "Y")))
6857 (clobber (reg:CC 33))]
6860 [(set_attr "op_type" "RSE")
6861 (set_attr "atype" "reg")])
6865 ; ashlsi3 instruction pattern(s).
6868 (define_insn "ashlsi3"
6869 [(set (match_operand:SI 0 "register_operand" "=d")
6870 (ashift:SI (match_operand:SI 1 "register_operand" "0")
6871 (match_operand:SI 2 "shift_count_operand" "Y")))]
6874 [(set_attr "op_type" "RS")
6875 (set_attr "atype" "reg")])
6878 ; ashrsi3 instruction pattern(s).
6881 (define_insn "*ashrsi3_cc"
6883 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6884 (match_operand:SI 2 "shift_count_operand" "Y"))
6886 (set (match_operand:SI 0 "register_operand" "=d")
6887 (ashiftrt:SI (match_dup 1) (match_dup 2)))]
6888 "s390_match_ccmode(insn, CCSmode)"
6890 [(set_attr "op_type" "RS")
6891 (set_attr "atype" "reg")])
6894 (define_insn "*ashrsi3_cconly"
6896 (compare (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6897 (match_operand:SI 2 "shift_count_operand" "Y"))
6899 (clobber (match_scratch:SI 0 "=d"))]
6900 "s390_match_ccmode(insn, CCSmode)"
6902 [(set_attr "op_type" "RS")
6903 (set_attr "atype" "reg")])
6905 (define_insn "ashrsi3"
6906 [(set (match_operand:SI 0 "register_operand" "=d")
6907 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
6908 (match_operand:SI 2 "shift_count_operand" "Y")))
6909 (clobber (reg:CC 33))]
6912 [(set_attr "op_type" "RS")
6913 (set_attr "atype" "reg")])
6917 ;;- logical shift instructions.
6921 ; lshrdi3 instruction pattern(s).
6924 (define_expand "lshrdi3"
6925 [(set (match_operand:DI 0 "register_operand" "")
6926 (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
6927 (match_operand:SI 2 "shift_count_operand" "")))]
6931 (define_insn "*lshrdi3_31"
6932 [(set (match_operand:DI 0 "register_operand" "=d")
6933 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0")
6934 (match_operand:SI 2 "shift_count_operand" "Y")))]
6937 [(set_attr "op_type" "RS")
6938 (set_attr "atype" "reg")])
6940 (define_insn "*lshrdi3_64"
6941 [(set (match_operand:DI 0 "register_operand" "=d")
6942 (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
6943 (match_operand:SI 2 "shift_count_operand" "Y")))]
6946 [(set_attr "op_type" "RSE")
6947 (set_attr "atype" "reg")])
6950 ; lshrsi3 instruction pattern(s).
6953 (define_insn "lshrsi3"
6954 [(set (match_operand:SI 0 "register_operand" "=d")
6955 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
6956 (match_operand:SI 2 "shift_count_operand" "Y")))]
6959 [(set_attr "op_type" "RS")
6960 (set_attr "atype" "reg")])
6964 ;; Branch instruction patterns.
6967 (define_expand "beq"
6968 [(match_operand 0 "" "")]
6970 "s390_emit_jump (operands[0],
6971 s390_emit_compare (EQ, s390_compare_op0, s390_compare_op1)); DONE;")
6973 (define_expand "bne"
6974 [(match_operand 0 "" "")]
6976 "s390_emit_jump (operands[0],
6977 s390_emit_compare (NE, s390_compare_op0, s390_compare_op1)); DONE;")
6979 (define_expand "bgt"
6980 [(match_operand 0 "" "")]
6982 "s390_emit_jump (operands[0],
6983 s390_emit_compare (GT, s390_compare_op0, s390_compare_op1)); DONE;")
6985 (define_expand "bgtu"
6986 [(match_operand 0 "" "")]
6988 "s390_emit_jump (operands[0],
6989 s390_emit_compare (GTU, s390_compare_op0, s390_compare_op1)); DONE;")
6991 (define_expand "blt"
6992 [(match_operand 0 "" "")]
6994 "s390_emit_jump (operands[0],
6995 s390_emit_compare (LT, s390_compare_op0, s390_compare_op1)); DONE;")
6997 (define_expand "bltu"
6998 [(match_operand 0 "" "")]
7000 "s390_emit_jump (operands[0],
7001 s390_emit_compare (LTU, s390_compare_op0, s390_compare_op1)); DONE;")
7003 (define_expand "bge"
7004 [(match_operand 0 "" "")]
7006 "s390_emit_jump (operands[0],
7007 s390_emit_compare (GE, s390_compare_op0, s390_compare_op1)); DONE;")
7009 (define_expand "bgeu"
7010 [(match_operand 0 "" "")]
7012 "s390_emit_jump (operands[0],
7013 s390_emit_compare (GEU, s390_compare_op0, s390_compare_op1)); DONE;")
7015 (define_expand "ble"
7016 [(match_operand 0 "" "")]
7018 "s390_emit_jump (operands[0],
7019 s390_emit_compare (LE, s390_compare_op0, s390_compare_op1)); DONE;")
7021 (define_expand "bleu"
7022 [(match_operand 0 "" "")]
7024 "s390_emit_jump (operands[0],
7025 s390_emit_compare (LEU, s390_compare_op0, s390_compare_op1)); DONE;")
7027 (define_expand "bunordered"
7028 [(match_operand 0 "" "")]
7030 "s390_emit_jump (operands[0],
7031 s390_emit_compare (UNORDERED, s390_compare_op0, s390_compare_op1)); DONE;")
7033 (define_expand "bordered"
7034 [(match_operand 0 "" "")]
7036 "s390_emit_jump (operands[0],
7037 s390_emit_compare (ORDERED, s390_compare_op0, s390_compare_op1)); DONE;")
7039 (define_expand "buneq"
7040 [(match_operand 0 "" "")]
7042 "s390_emit_jump (operands[0],
7043 s390_emit_compare (UNEQ, s390_compare_op0, s390_compare_op1)); DONE;")
7045 (define_expand "bunlt"
7046 [(match_operand 0 "" "")]
7048 "s390_emit_jump (operands[0],
7049 s390_emit_compare (UNLT, s390_compare_op0, s390_compare_op1)); DONE;")
7051 (define_expand "bungt"
7052 [(match_operand 0 "" "")]
7054 "s390_emit_jump (operands[0],
7055 s390_emit_compare (UNGT, s390_compare_op0, s390_compare_op1)); DONE;")
7057 (define_expand "bunle"
7058 [(match_operand 0 "" "")]
7060 "s390_emit_jump (operands[0],
7061 s390_emit_compare (UNLE, s390_compare_op0, s390_compare_op1)); DONE;")
7063 (define_expand "bunge"
7064 [(match_operand 0 "" "")]
7066 "s390_emit_jump (operands[0],
7067 s390_emit_compare (UNGE, s390_compare_op0, s390_compare_op1)); DONE;")
7069 (define_expand "bltgt"
7070 [(match_operand 0 "" "")]
7072 "s390_emit_jump (operands[0],
7073 s390_emit_compare (LTGT, s390_compare_op0, s390_compare_op1)); DONE;")
7077 ;;- Conditional jump instructions.
7080 (define_insn "*cjump_64"
7083 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
7084 (label_ref (match_operand 0 "" ""))
7088 if (get_attr_length (insn) == 4)
7091 return "jg%C1\t%l0";
7093 [(set_attr "op_type" "RI")
7094 (set_attr "type" "branch")
7095 (set (attr "length")
7096 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7097 (const_int 4) (const_int 6)))])
7099 (define_insn "*cjump_31"
7102 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
7103 (label_ref (match_operand 0 "" ""))
7107 if (get_attr_length (insn) == 4)
7112 [(set_attr "op_type" "RI")
7113 (set_attr "type" "branch")
7114 (set (attr "length")
7115 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7116 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7117 (const_int 4) (const_int 6))
7118 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7119 (const_int 4) (const_int 8))))])
7121 (define_insn "*cjump_long"
7124 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
7125 (match_operand 0 "address_operand" "U")
7129 if (get_attr_op_type (insn) == OP_TYPE_RR)
7134 [(set (attr "op_type")
7135 (if_then_else (match_operand 0 "register_operand" "")
7136 (const_string "RR") (const_string "RX")))
7137 (set_attr "type" "branch")
7138 (set_attr "atype" "agen")])
7142 ;;- Negated conditional jump instructions.
7145 (define_insn "*icjump_64"
7148 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
7150 (label_ref (match_operand 0 "" ""))))]
7153 if (get_attr_length (insn) == 4)
7156 return "jg%D1\t%l0";
7158 [(set_attr "op_type" "RI")
7159 (set_attr "type" "branch")
7160 (set (attr "length")
7161 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7162 (const_int 4) (const_int 6)))])
7164 (define_insn "*icjump_31"
7167 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
7169 (label_ref (match_operand 0 "" ""))))]
7172 if (get_attr_length (insn) == 4)
7177 [(set_attr "op_type" "RI")
7178 (set_attr "type" "branch")
7179 (set (attr "length")
7180 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7181 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7182 (const_int 4) (const_int 6))
7183 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7184 (const_int 4) (const_int 8))))])
7186 (define_insn "*icjump_long"
7189 (match_operator 1 "s390_comparison" [(reg 33) (const_int 0)])
7191 (match_operand 0 "address_operand" "U")))]
7194 if (get_attr_op_type (insn) == OP_TYPE_RR)
7199 [(set (attr "op_type")
7200 (if_then_else (match_operand 0 "register_operand" "")
7201 (const_string "RR") (const_string "RX")))
7202 (set_attr "type" "branch")
7203 (set_attr "atype" "agen")])
7206 ;;- Trap instructions.
7210 [(trap_if (const_int 1) (const_int 0))]
7213 [(set_attr "op_type" "RI")
7214 (set_attr "type" "branch")])
7216 (define_expand "conditional_trap"
7217 [(trap_if (match_operand 0 "comparison_operator" "")
7218 (match_operand 1 "general_operand" ""))]
7221 if (operands[1] != const0_rtx) FAIL;
7222 operands[0] = s390_emit_compare (GET_CODE (operands[0]),
7223 s390_compare_op0, s390_compare_op1);
7226 (define_insn "*trap"
7227 [(trap_if (match_operator 0 "s390_comparison" [(reg 33) (const_int 0)])
7231 [(set_attr "op_type" "RI")
7232 (set_attr "type" "branch")])
7235 ;;- Loop instructions.
7237 ;; This is all complicated by the fact that since this is a jump insn
7238 ;; we must handle our own output reloads.
7240 (define_expand "doloop_end"
7241 [(use (match_operand 0 "" "")) ; loop pseudo
7242 (use (match_operand 1 "" "")) ; iterations; zero if unknown
7243 (use (match_operand 2 "" "")) ; max iterations
7244 (use (match_operand 3 "" "")) ; loop level
7245 (use (match_operand 4 "" ""))] ; label
7248 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH)
7249 emit_jump_insn (gen_doloop_si31 (operands[4], operands[0], operands[0]));
7250 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH)
7251 emit_jump_insn (gen_doloop_si64 (operands[4], operands[0], operands[0]));
7252 else if (GET_MODE (operands[0]) == DImode && TARGET_64BIT)
7253 emit_jump_insn (gen_doloop_di (operands[4], operands[0], operands[0]));
7260 (define_insn_and_split "doloop_si64"
7263 (ne (match_operand:SI 1 "register_operand" "d,d")
7265 (label_ref (match_operand 0 "" ""))
7267 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
7268 (plus:SI (match_dup 1) (const_int -1)))
7269 (clobber (match_scratch:SI 3 "=X,&1"))
7270 (clobber (reg:CC 33))]
7273 if (which_alternative != 0)
7275 else if (get_attr_length (insn) == 4)
7276 return "brct\t%1,%l0";
7278 return "ahi\t%1,-1\;jgne\t%l0";
7280 "&& reload_completed
7281 && (! REG_P (operands[2])
7282 || ! rtx_equal_p (operands[1], operands[2]))"
7283 [(parallel [(set (reg:CCAN 33)
7284 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7286 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7287 (set (match_dup 2) (match_dup 3))
7288 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
7289 (label_ref (match_dup 0))
7292 [(set_attr "op_type" "RI")
7293 (set_attr "type" "branch")
7294 (set (attr "length")
7295 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7296 (const_int 4) (const_int 10)))])
7298 (define_insn_and_split "doloop_si31"
7301 (ne (match_operand:SI 1 "register_operand" "d,d")
7303 (label_ref (match_operand 0 "" ""))
7305 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?*m*d")
7306 (plus:SI (match_dup 1) (const_int -1)))
7307 (clobber (match_scratch:SI 3 "=X,&1"))
7308 (clobber (reg:CC 33))]
7311 if (which_alternative != 0)
7313 else if (get_attr_length (insn) == 4)
7314 return "brct\t%1,%l0";
7318 "&& reload_completed
7319 && (! REG_P (operands[2])
7320 || ! rtx_equal_p (operands[1], operands[2]))"
7321 [(parallel [(set (reg:CCAN 33)
7322 (compare:CCAN (plus:SI (match_dup 3) (const_int -1))
7324 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))])
7325 (set (match_dup 2) (match_dup 3))
7326 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
7327 (label_ref (match_dup 0))
7330 [(set_attr "op_type" "RI")
7331 (set_attr "type" "branch")
7332 (set (attr "length")
7333 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7334 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7335 (const_int 4) (const_int 6))
7336 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7337 (const_int 4) (const_int 8))))])
7339 (define_insn "*doloop_si_long"
7342 (ne (match_operand:SI 1 "register_operand" "d,d")
7344 (match_operand 0 "address_operand" "U,U")
7346 (set (match_operand:SI 2 "register_operand" "=1,?*m*d")
7347 (plus:SI (match_dup 1) (const_int -1)))
7348 (clobber (match_scratch:SI 3 "=X,&1"))
7349 (clobber (reg:CC 33))]
7352 if (get_attr_op_type (insn) == OP_TYPE_RR)
7353 return "bctr\t%1,%0";
7355 return "bct\t%1,%a0";
7357 [(set (attr "op_type")
7358 (if_then_else (match_operand 0 "register_operand" "")
7359 (const_string "RR") (const_string "RX")))
7360 (set_attr "type" "branch")
7361 (set_attr "atype" "agen")])
7363 (define_insn_and_split "doloop_di"
7366 (ne (match_operand:DI 1 "register_operand" "d,d")
7368 (label_ref (match_operand 0 "" ""))
7370 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?*m*d")
7371 (plus:DI (match_dup 1) (const_int -1)))
7372 (clobber (match_scratch:DI 3 "=X,&1"))
7373 (clobber (reg:CC 33))]
7376 if (which_alternative != 0)
7378 else if (get_attr_length (insn) == 4)
7379 return "brctg\t%1,%l0";
7381 return "aghi\t%1,-1\;jgne\t%l0";
7383 "&& reload_completed
7384 && (! REG_P (operands[2])
7385 || ! rtx_equal_p (operands[1], operands[2]))"
7386 [(parallel [(set (reg:CCAN 33)
7387 (compare:CCAN (plus:DI (match_dup 3) (const_int -1))
7389 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))])
7390 (set (match_dup 2) (match_dup 3))
7391 (set (pc) (if_then_else (ne (reg:CCAN 33) (const_int 0))
7392 (label_ref (match_dup 0))
7395 [(set_attr "op_type" "RI")
7396 (set_attr "type" "branch")
7397 (set (attr "length")
7398 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7399 (const_int 4) (const_int 10)))])
7402 ;;- Unconditional jump instructions.
7406 ; jump instruction pattern(s).
7409 (define_expand "jump"
7410 [(match_operand 0 "" "")]
7412 "s390_emit_jump (operands[0], NULL_RTX); DONE;")
7414 (define_insn "*jump64"
7415 [(set (pc) (label_ref (match_operand 0 "" "")))]
7418 if (get_attr_length (insn) == 4)
7423 [(set_attr "op_type" "RI")
7424 (set_attr "type" "branch")
7425 (set (attr "length")
7426 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7427 (const_int 4) (const_int 6)))])
7429 (define_insn "*jump31"
7430 [(set (pc) (label_ref (match_operand 0 "" "")))]
7433 if (get_attr_length (insn) == 4)
7438 [(set_attr "op_type" "RI")
7439 (set_attr "type" "branch")
7440 (set (attr "length")
7441 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
7442 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7443 (const_int 4) (const_int 6))
7444 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
7445 (const_int 4) (const_int 8))))])
7448 ; indirect-jump instruction pattern(s).
7451 (define_insn "indirect_jump"
7452 [(set (pc) (match_operand 0 "address_operand" "U"))]
7455 if (get_attr_op_type (insn) == OP_TYPE_RR)
7460 [(set (attr "op_type")
7461 (if_then_else (match_operand 0 "register_operand" "")
7462 (const_string "RR") (const_string "RX")))
7463 (set_attr "type" "branch")
7464 (set_attr "atype" "agen")])
7467 ; casesi instruction pattern(s).
7470 (define_insn "casesi_jump"
7471 [(set (pc) (match_operand 0 "address_operand" "U"))
7472 (use (label_ref (match_operand 1 "" "")))]
7475 if (get_attr_op_type (insn) == OP_TYPE_RR)
7480 [(set (attr "op_type")
7481 (if_then_else (match_operand 0 "register_operand" "")
7482 (const_string "RR") (const_string "RX")))
7483 (set_attr "type" "branch")
7484 (set_attr "atype" "agen")])
7486 (define_expand "casesi"
7487 [(match_operand:SI 0 "general_operand" "")
7488 (match_operand:SI 1 "general_operand" "")
7489 (match_operand:SI 2 "general_operand" "")
7490 (label_ref (match_operand 3 "" ""))
7491 (label_ref (match_operand 4 "" ""))]
7494 rtx index = gen_reg_rtx (SImode);
7495 rtx base = gen_reg_rtx (Pmode);
7496 rtx target = gen_reg_rtx (Pmode);
7498 emit_move_insn (index, operands[0]);
7499 emit_insn (gen_subsi3 (index, index, operands[1]));
7500 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1,
7503 if (Pmode != SImode)
7504 index = convert_to_mode (Pmode, index, 1);
7505 if (GET_CODE (index) != REG)
7506 index = copy_to_mode_reg (Pmode, index);
7509 emit_insn (gen_ashldi3 (index, index, GEN_INT (3)));
7511 emit_insn (gen_ashlsi3 (index, index, const2_rtx));
7513 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3]));
7515 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index));
7516 emit_move_insn (target, index);
7519 target = gen_rtx_PLUS (Pmode, base, target);
7520 emit_jump_insn (gen_casesi_jump (target, operands[3]));
7527 ;;- Jump to subroutine.
7532 ; untyped call instruction pattern(s).
7535 ;; Call subroutine returning any type.
7536 (define_expand "untyped_call"
7537 [(parallel [(call (match_operand 0 "" "")
7539 (match_operand 1 "" "")
7540 (match_operand 2 "" "")])]
7545 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx));
7547 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7549 rtx set = XVECEXP (operands[2], 0, i);
7550 emit_move_insn (SET_DEST (set), SET_SRC (set));
7553 /* The optimizer does not know that the call sets the function value
7554 registers we stored in the result block. We avoid problems by
7555 claiming that all hard registers are used and clobbered at this
7557 emit_insn (gen_blockage ());
7562 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
7563 ;; all of memory. This blocks insns from being moved across this point.
7565 (define_insn "blockage"
7566 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
7569 [(set_attr "type" "none")
7570 (set_attr "length" "0")])
7576 (define_expand "sibcall"
7577 [(call (match_operand 0 "" "")
7578 (match_operand 1 "" ""))]
7581 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX);
7585 (define_insn "*sibcall_br"
7586 [(call (mem:QI (reg 1))
7587 (match_operand 0 "const_int_operand" "n"))]
7588 "SIBLING_CALL_P (insn)
7589 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode"
7591 [(set_attr "op_type" "RR")
7592 (set_attr "type" "branch")
7593 (set_attr "atype" "agen")])
7595 (define_insn "*sibcall_brc"
7596 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7597 (match_operand 1 "const_int_operand" "n"))]
7598 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7600 [(set_attr "op_type" "RI")
7601 (set_attr "type" "branch")])
7603 (define_insn "*sibcall_brcl"
7604 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7605 (match_operand 1 "const_int_operand" "n"))]
7606 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7608 [(set_attr "op_type" "RIL")
7609 (set_attr "type" "branch")])
7612 ; sibcall_value patterns
7615 (define_expand "sibcall_value"
7616 [(set (match_operand 0 "" "")
7617 (call (match_operand 1 "" "")
7618 (match_operand 2 "" "")))]
7621 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX);
7625 (define_insn "*sibcall_value_br"
7626 [(set (match_operand 0 "" "")
7627 (call (mem:QI (reg 1))
7628 (match_operand 1 "const_int_operand" "n")))]
7629 "SIBLING_CALL_P (insn)
7630 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode"
7632 [(set_attr "op_type" "RR")
7633 (set_attr "type" "branch")
7634 (set_attr "atype" "agen")])
7636 (define_insn "*sibcall_value_brc"
7637 [(set (match_operand 0 "" "")
7638 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7639 (match_operand 2 "const_int_operand" "n")))]
7640 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC"
7642 [(set_attr "op_type" "RI")
7643 (set_attr "type" "branch")])
7645 (define_insn "*sibcall_value_brcl"
7646 [(set (match_operand 0 "" "")
7647 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7648 (match_operand 2 "const_int_operand" "n")))]
7649 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH"
7651 [(set_attr "op_type" "RIL")
7652 (set_attr "type" "branch")])
7656 ; call instruction pattern(s).
7659 (define_expand "call"
7660 [(call (match_operand 0 "" "")
7661 (match_operand 1 "" ""))
7662 (use (match_operand 2 "" ""))]
7665 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX,
7666 gen_rtx_REG (Pmode, RETURN_REGNUM));
7670 (define_insn "*bras"
7671 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7672 (match_operand 1 "const_int_operand" "n"))
7673 (clobber (match_operand 2 "register_operand" "=r"))]
7674 "!SIBLING_CALL_P (insn)
7675 && TARGET_SMALL_EXEC
7676 && GET_MODE (operands[2]) == Pmode"
7678 [(set_attr "op_type" "RI")
7679 (set_attr "type" "jsr")])
7681 (define_insn "*brasl"
7682 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X"))
7683 (match_operand 1 "const_int_operand" "n"))
7684 (clobber (match_operand 2 "register_operand" "=r"))]
7685 "!SIBLING_CALL_P (insn)
7687 && GET_MODE (operands[2]) == Pmode"
7689 [(set_attr "op_type" "RIL")
7690 (set_attr "type" "jsr")])
7692 (define_insn "*basr"
7693 [(call (mem:QI (match_operand 0 "address_operand" "U"))
7694 (match_operand 1 "const_int_operand" "n"))
7695 (clobber (match_operand 2 "register_operand" "=r"))]
7696 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode"
7698 if (get_attr_op_type (insn) == OP_TYPE_RR)
7699 return "basr\t%2,%0";
7701 return "bas\t%2,%a0";
7703 [(set (attr "op_type")
7704 (if_then_else (match_operand 0 "register_operand" "")
7705 (const_string "RR") (const_string "RX")))
7706 (set_attr "type" "jsr")
7707 (set_attr "atype" "agen")])
7710 ; call_value instruction pattern(s).
7713 (define_expand "call_value"
7714 [(set (match_operand 0 "" "")
7715 (call (match_operand 1 "" "")
7716 (match_operand 2 "" "")))
7717 (use (match_operand 3 "" ""))]
7720 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0],
7721 gen_rtx_REG (Pmode, RETURN_REGNUM));
7725 (define_insn "*bras_r"
7726 [(set (match_operand 0 "" "")
7727 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7728 (match_operand:SI 2 "const_int_operand" "n")))
7729 (clobber (match_operand 3 "register_operand" "=r"))]
7730 "!SIBLING_CALL_P (insn)
7731 && TARGET_SMALL_EXEC
7732 && GET_MODE (operands[3]) == Pmode"
7734 [(set_attr "op_type" "RI")
7735 (set_attr "type" "jsr")])
7737 (define_insn "*brasl_r"
7738 [(set (match_operand 0 "" "")
7739 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7740 (match_operand 2 "const_int_operand" "n")))
7741 (clobber (match_operand 3 "register_operand" "=r"))]
7742 "!SIBLING_CALL_P (insn)
7744 && GET_MODE (operands[3]) == Pmode"
7746 [(set_attr "op_type" "RIL")
7747 (set_attr "type" "jsr")])
7749 (define_insn "*basr_r"
7750 [(set (match_operand 0 "" "")
7751 (call (mem:QI (match_operand 1 "address_operand" "U"))
7752 (match_operand 2 "const_int_operand" "n")))
7753 (clobber (match_operand 3 "register_operand" "=r"))]
7754 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7756 if (get_attr_op_type (insn) == OP_TYPE_RR)
7757 return "basr\t%3,%1";
7759 return "bas\t%3,%a1";
7761 [(set (attr "op_type")
7762 (if_then_else (match_operand 1 "register_operand" "")
7763 (const_string "RR") (const_string "RX")))
7764 (set_attr "type" "jsr")
7765 (set_attr "atype" "agen")])
7768 ;;- Thread-local storage support.
7771 (define_expand "get_tp_64"
7772 [(set (match_operand:DI 0 "nonimmediate_operand" "") (reg:DI 36))]
7776 (define_expand "get_tp_31"
7777 [(set (match_operand:SI 0 "nonimmediate_operand" "") (reg:SI 36))]
7781 (define_expand "set_tp_64"
7782 [(set (reg:DI 36) (match_operand:DI 0 "nonimmediate_operand" ""))
7783 (unspec_volatile [(reg:DI 36)] UNSPECV_SET_TP)]
7787 (define_expand "set_tp_31"
7788 [(set (reg:SI 36) (match_operand:SI 0 "nonimmediate_operand" ""))
7789 (unspec_volatile [(reg:SI 36)] UNSPECV_SET_TP)]
7793 (define_insn "*set_tp"
7794 [(unspec_volatile [(reg 36)] UNSPECV_SET_TP)]
7797 [(set_attr "type" "none")
7798 (set_attr "length" "0")])
7800 (define_insn "*tls_load_64"
7801 [(set (match_operand:DI 0 "register_operand" "=d")
7802 (unspec:DI [(match_operand:DI 1 "memory_operand" "m")
7803 (match_operand:DI 2 "" "")]
7807 [(set_attr "op_type" "RXE")])
7809 (define_insn "*tls_load_31"
7810 [(set (match_operand:SI 0 "register_operand" "=d,d")
7811 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T")
7812 (match_operand:SI 2 "" "")]
7818 [(set_attr "op_type" "RX,RXY")])
7820 (define_insn "*bras_tls"
7821 [(set (match_operand 0 "" "")
7822 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7823 (match_operand 2 "const_int_operand" "n")))
7824 (clobber (match_operand 3 "register_operand" "=r"))
7825 (use (match_operand 4 "" ""))]
7826 "!SIBLING_CALL_P (insn)
7827 && TARGET_SMALL_EXEC
7828 && GET_MODE (operands[3]) == Pmode"
7830 [(set_attr "op_type" "RI")
7831 (set_attr "type" "jsr")])
7833 (define_insn "*brasl_tls"
7834 [(set (match_operand 0 "" "")
7835 (call (mem:QI (match_operand 1 "bras_sym_operand" "X"))
7836 (match_operand 2 "const_int_operand" "n")))
7837 (clobber (match_operand 3 "register_operand" "=r"))
7838 (use (match_operand 4 "" ""))]
7839 "!SIBLING_CALL_P (insn)
7841 && GET_MODE (operands[3]) == Pmode"
7843 [(set_attr "op_type" "RIL")
7844 (set_attr "type" "jsr")])
7846 (define_insn "*basr_tls"
7847 [(set (match_operand 0 "" "")
7848 (call (mem:QI (match_operand 1 "address_operand" "U"))
7849 (match_operand 2 "const_int_operand" "n")))
7850 (clobber (match_operand 3 "register_operand" "=r"))
7851 (use (match_operand 4 "" ""))]
7852 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode"
7854 if (get_attr_op_type (insn) == OP_TYPE_RR)
7855 return "basr\t%3,%1%J4";
7857 return "bas\t%3,%a1%J4";
7859 [(set (attr "op_type")
7860 (if_then_else (match_operand 1 "register_operand" "")
7861 (const_string "RR") (const_string "RX")))
7862 (set_attr "type" "jsr")
7863 (set_attr "atype" "agen")])
7866 ;;- Miscellaneous instructions.
7870 ; allocate stack instruction pattern(s).
7873 (define_expand "allocate_stack"
7874 [(match_operand 0 "general_operand" "")
7875 (match_operand 1 "general_operand" "")]
7878 rtx temp = gen_reg_rtx (Pmode);
7880 emit_move_insn (temp, s390_back_chain_rtx ());
7881 anti_adjust_stack (operands[1]);
7882 emit_move_insn (s390_back_chain_rtx (), temp);
7884 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
7890 ; setjmp instruction pattern.
7893 (define_expand "builtin_setjmp_receiver"
7894 [(match_operand 0 "" "")]
7897 emit_insn (s390_load_got ());
7898 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
7902 ;; These patterns say how to save and restore the stack pointer. We need not
7903 ;; save the stack pointer at function level since we are careful to
7904 ;; preserve the backchain. At block level, we have to restore the backchain
7905 ;; when we restore the stack pointer.
7907 ;; For nonlocal gotos, we must save both the stack pointer and its
7908 ;; backchain and restore both. Note that in the nonlocal case, the
7909 ;; save area is a memory location.
7911 (define_expand "save_stack_function"
7912 [(match_operand 0 "general_operand" "")
7913 (match_operand 1 "general_operand" "")]
7917 (define_expand "restore_stack_function"
7918 [(match_operand 0 "general_operand" "")
7919 (match_operand 1 "general_operand" "")]
7923 (define_expand "restore_stack_block"
7924 [(match_operand 0 "register_operand" "")
7925 (match_operand 1 "register_operand" "")]
7928 rtx temp = gen_reg_rtx (Pmode);
7930 emit_move_insn (temp, s390_back_chain_rtx ());
7931 emit_move_insn (operands[0], operands[1]);
7932 emit_move_insn (s390_back_chain_rtx (), temp);
7937 (define_expand "save_stack_nonlocal"
7938 [(match_operand 0 "memory_operand" "")
7939 (match_operand 1 "register_operand" "")]
7942 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7943 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7945 /* Copy the backchain to the first word, sp to the second and the
7946 literal pool base to the third. */
7948 if (TARGET_BACKCHAIN)
7950 rtx temp = force_reg (Pmode, s390_back_chain_rtx ());
7951 emit_move_insn (operand_subword (operands[0], 0, 0, mode), temp);
7954 emit_move_insn (operand_subword (operands[0], 1, 0, mode), operands[1]);
7955 emit_move_insn (operand_subword (operands[0], 2, 0, mode), base);
7960 (define_expand "restore_stack_nonlocal"
7961 [(match_operand 0 "register_operand" "")
7962 (match_operand 1 "memory_operand" "")]
7965 enum machine_mode mode = TARGET_64BIT ? OImode : TImode;
7966 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM);
7967 rtx temp = NULL_RTX;
7969 /* Restore the backchain from the first word, sp from the second and the
7970 literal pool base from the third. */
7972 if (TARGET_BACKCHAIN)
7973 temp = force_reg (Pmode, operand_subword (operands[1], 0, 0, mode));
7975 emit_move_insn (base, operand_subword (operands[1], 2, 0, mode));
7976 emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, mode));
7979 emit_move_insn (s390_back_chain_rtx (), temp);
7981 emit_insn (gen_rtx_USE (VOIDmode, base));
7987 ; nop instruction pattern(s).
7994 [(set_attr "op_type" "RR")])
7998 ; Special literal pool access instruction pattern(s).
8001 (define_insn "*pool_entry"
8002 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")]
8003 UNSPECV_POOL_ENTRY)]
8006 enum machine_mode mode = GET_MODE (PATTERN (insn));
8007 unsigned int align = GET_MODE_BITSIZE (mode);
8008 s390_output_pool_entry (operands[0], mode, align);
8011 [(set (attr "length")
8012 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))])
8014 (define_insn "pool_align"
8015 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")]
8016 UNSPECV_POOL_ALIGN)]
8019 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
8021 (define_insn "pool_section_start"
8022 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)]
8025 [(set_attr "length" "0")])
8027 (define_insn "pool_section_end"
8028 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)]
8031 [(set_attr "length" "0")])
8033 (define_insn "main_base_31_small"
8034 [(set (match_operand 0 "register_operand" "=a")
8035 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
8036 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8038 [(set_attr "op_type" "RR")
8039 (set_attr "type" "la")])
8041 (define_insn "main_base_31_large"
8042 [(set (match_operand 0 "register_operand" "=a")
8043 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))
8044 (set (pc) (label_ref (match_operand 2 "" "")))]
8045 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8047 [(set_attr "op_type" "RI")])
8049 (define_insn "main_base_64"
8050 [(set (match_operand 0 "register_operand" "=a")
8051 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))]
8052 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8054 [(set_attr "op_type" "RIL")
8055 (set_attr "type" "larl")])
8057 (define_insn "main_pool"
8058 [(set (match_operand 0 "register_operand" "=a")
8059 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))]
8060 "GET_MODE (operands[0]) == Pmode"
8063 (if_then_else (ne (symbol_ref "TARGET_CPU_ZARCH") (const_int 0))
8064 (const_string "larl") (const_string "la")))])
8066 (define_insn "reload_base_31"
8067 [(set (match_operand 0 "register_operand" "=a")
8068 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
8069 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8070 "basr\t%0,0\;la\t%0,%1-.(%0)"
8071 [(set_attr "length" "6")
8072 (set_attr "type" "la")])
8074 (define_insn "reload_base_64"
8075 [(set (match_operand 0 "register_operand" "=a")
8076 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))]
8077 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode"
8079 [(set_attr "op_type" "RIL")
8080 (set_attr "type" "larl")])
8083 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
8086 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))])
8089 ;; Insns related to generating the function prologue and epilogue.
8093 (define_expand "prologue"
8094 [(use (const_int 0))]
8096 "s390_emit_prologue (); DONE;")
8098 (define_insn "prologue_tpf"
8099 [(unspec_volatile [(const_int 0)] UNSPECV_TPF_PROLOGUE)
8100 (clobber (reg:DI 1))]
8101 "TARGET_TPF_PROFILING"
8103 [(set_attr "type" "jsr")
8104 (set_attr "op_type" "RX")])
8106 (define_expand "epilogue"
8107 [(use (const_int 1))]
8109 "s390_emit_epilogue (false); DONE;")
8111 (define_insn "epilogue_tpf"
8112 [(unspec_volatile [(const_int 0)] UNSPECV_TPF_EPILOGUE)
8113 (clobber (reg:DI 1))]
8114 "TARGET_TPF_PROFILING"
8116 [(set_attr "type" "jsr")
8117 (set_attr "op_type" "RX")])
8120 (define_expand "sibcall_epilogue"
8121 [(use (const_int 0))]
8123 "s390_emit_epilogue (true); DONE;")
8125 (define_insn "*return"
8127 (use (match_operand 0 "register_operand" "a"))]
8128 "GET_MODE (operands[0]) == Pmode"
8130 [(set_attr "op_type" "RR")
8131 (set_attr "type" "jsr")
8132 (set_attr "atype" "agen")])
8135 ;; Instruction definition to extend a 31-bit pointer into a 64-bit
8136 ;; pointer. This is used for compatibility.
8138 (define_expand "ptr_extend"
8139 [(set (match_operand:DI 0 "register_operand" "=r")
8140 (match_operand:SI 1 "register_operand" "r"))]
8143 emit_insn (gen_anddi3 (operands[0],
8144 gen_lowpart (DImode, operands[1]),
8145 GEN_INT (0x7fffffff)));
8149 ;; Instruction definition to expand eh_return macro to support
8150 ;; swapping in special linkage return addresses.
8152 (define_expand "eh_return"
8153 [(use (match_operand 0 "register_operand" ""))]
8156 s390_emit_tpf_eh_return (operands[0]);