gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987-2014 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify it under
   7 the terms of the GNU General Public License as published by the Free
   8 Software Foundation; either version 3, or (at your option) any later
   9 version.
  10
  11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  12 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14 for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 /* This module is essentially the "combiner" phase of the U. of Arizona
  21    Portable Optimizer, but redone to work on our list-structured
  22    representation for RTL instead of their string representation.
  23
  24    The LOG_LINKS of each insn identify the most recent assignment
  25    to each REG used in the insn.  It is a list of previous insns,
  26    each of which contains a SET for a REG that is used in this insn
  27    and not used or set in between.  LOG_LINKs never cross basic blocks.
  28    They were set up by the preceding pass (lifetime analysis).
  29
  30    We try to combine each pair of insns joined by a logical link.
  31    We also try to combine triplets of insns A, B and C when C has
  32    a link back to B and B has a link back to A.  Likewise for a
  33    small number of quadruplets of insns A, B, C and D for which
  34    there's high likelihood of of success.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information isn't
  53    completely updated (however this is only a local issue since it is
  54    regenerated before the next pass that uses it):
  55
  56    - reg_live_length is not updated
  57    - reg_n_refs is not adjusted in the rare case when a register is
  58      no longer required in a computation
  59    - there are extremely rare cases (see distribute_notes) when a
  60      REG_DEAD note is lost
  61    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  62      removed because there is no way to know which register it was
  63      linking
  64
  65    To simplify substitution, we combine only when the earlier insn(s)
  66    consist of only a single assignment.  To simplify updating afterward,
  67    we never combine when a subroutine call appears in the middle.
  68
  69    Since we do not represent assignments to CC0 explicitly except when that
  70    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  71    the condition code for the insn that set the condition code.
  72    Fortunately, these two insns must be consecutive.
  73    Therefore, every JUMP_INSN is taken to have an implicit logical link
  74    to the preceding insn.  This is not quite right, since non-jumps can
  75    also use the condition code; but in practice such insns would not
  76    combine anyway.  */
  77
  78 #include "config.h"
  79 #include "system.h"
  80 #include "coretypes.h"
  81 #include "tm.h"
  82 #include "rtl.h"
  83 #include "tree.h"
  84 #include "stor-layout.h"
  85 #include "tm_p.h"
  86 #include "flags.h"
  87 #include "regs.h"
  88 #include "hard-reg-set.h"
  89 #include "predict.h"
  90 #include "vec.h"
  91 #include "hashtab.h"
  92 #include "hash-set.h"
  93 #include "machmode.h"
  94 #include "input.h"
  95 #include "function.h"
  96 #include "dominance.h"
  97 #include "cfg.h"
  98 #include "cfgrtl.h"
  99 #include "cfgcleanup.h"
 100 #include "basic-block.h"
 101 #include "insn-config.h"
 102 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
 103 #include "expr.h"
 104 #include "insn-attr.h"
 105 #include "recog.h"
 106 #include "diagnostic-core.h"
 107 #include "target.h"
 108 #include "insn-codes.h"
 109 #include "optabs.h"
 110 #include "rtlhooks-def.h"
 111 #include "params.h"
 112 #include "tree-pass.h"
 113 #include "df.h"
 114 #include "valtrack.h"
 115 #include "hash-map.h"
 116 #include "is-a.h"
 117 #include "plugin-api.h"
 118 #include "ipa-ref.h"
 119 #include "cgraph.h"
 120 #include "obstack.h"
 121 #include "statistics.h"
 122 #include "params.h"
 123 #include "rtl-iter.h"
 124
 125 /* Number of attempts to combine instructions in this function.  */
 126
 127 static int combine_attempts;
 128
 129 /* Number of attempts that got as far as substitution in this function.  */
 130
 131 static int combine_merges;
 132
 133 /* Number of instructions combined with added SETs in this function.  */
 134
 135 static int combine_extras;
 136
 137 /* Number of instructions combined in this function.  */
 138
 139 static int combine_successes;
 140
 141 /* Totals over entire compilation.  */
 142
 143 static int total_attempts, total_merges, total_extras, total_successes;
 144
 145 /* combine_instructions may try to replace the right hand side of the
 146    second instruction with the value of an associated REG_EQUAL note
 147    before throwing it at try_combine.  That is problematic when there
 148    is a REG_DEAD note for a register used in the old right hand side
 149    and can cause distribute_notes to do wrong things.  This is the
 150    second instruction if it has been so modified, null otherwise.  */
 151
 152 static rtx_insn *i2mod;
 153
 154 /* When I2MOD is nonnull, this is a copy of the old right hand side.  */
 155
 156 static rtx i2mod_old_rhs;
 157
 158 /* When I2MOD is nonnull, this is a copy of the new right hand side.  */
 159
 160 static rtx i2mod_new_rhs;
 161 \f
 162 typedef struct reg_stat_struct {
 163   /* Record last point of death of (hard or pseudo) register n.  */
 164   rtx_insn                      *last_death;
 165
 166   /* Record last point of modification of (hard or pseudo) register n.  */
 167   rtx_insn                      *last_set;
 168
 169   /* The next group of fields allows the recording of the last value assigned
 170      to (hard or pseudo) register n.  We use this information to see if an
 171      operation being processed is redundant given a prior operation performed
 172      on the register.  For example, an `and' with a constant is redundant if
 173      all the zero bits are already known to be turned off.
 174
 175      We use an approach similar to that used by cse, but change it in the
 176      following ways:
 177
 178      (1) We do not want to reinitialize at each label.
 179      (2) It is useful, but not critical, to know the actual value assigned
 180          to a register.  Often just its form is helpful.
 181
 182      Therefore, we maintain the following fields:
 183
 184      last_set_value             the last value assigned
 185      last_set_label             records the value of label_tick when the
 186                                 register was assigned
 187      last_set_table_tick        records the value of label_tick when a
 188                                 value using the register is assigned
 189      last_set_invalid           set to nonzero when it is not valid
 190                                 to use the value of this register in some
 191                                 register's value
 192
 193      To understand the usage of these tables, it is important to understand
 194      the distinction between the value in last_set_value being valid and
 195      the register being validly contained in some other expression in the
 196      table.
 197
 198      (The next two parameters are out of date).
 199
 200      reg_stat[i].last_set_value is valid if it is nonzero, and either
 201      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 202
 203      Register I may validly appear in any expression returned for the value
 204      of another register if reg_n_sets[i] is 1.  It may also appear in the
 205      value for register J if reg_stat[j].last_set_invalid is zero, or
 206      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 207
 208      If an expression is found in the table containing a register which may
 209      not validly appear in an expression, the register is replaced by
 210      something that won't match, (clobber (const_int 0)).  */
 211
 212   /* Record last value assigned to (hard or pseudo) register n.  */
 213
 214   rtx                           last_set_value;
 215
 216   /* Record the value of label_tick when an expression involving register n
 217      is placed in last_set_value.  */
 218
 219   int                           last_set_table_tick;
 220
 221   /* Record the value of label_tick when the value for register n is placed in
 222      last_set_value.  */
 223
 224   int                           last_set_label;
 225
 226   /* These fields are maintained in parallel with last_set_value and are
 227      used to store the mode in which the register was last set, the bits
 228      that were known to be zero when it was last set, and the number of
 229      sign bits copies it was known to have when it was last set.  */
 230
 231   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 232   char                          last_set_sign_bit_copies;
 233   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 234
 235   /* Set nonzero if references to register n in expressions should not be
 236      used.  last_set_invalid is set nonzero when this register is being
 237      assigned to and last_set_table_tick == label_tick.  */
 238
 239   char                          last_set_invalid;
 240
 241   /* Some registers that are set more than once and used in more than one
 242      basic block are nevertheless always set in similar ways.  For example,
 243      a QImode register may be loaded from memory in two places on a machine
 244      where byte loads zero extend.
 245
 246      We record in the following fields if a register has some leading bits
 247      that are always equal to the sign bit, and what we know about the
 248      nonzero bits of a register, specifically which bits are known to be
 249      zero.
 250
 251      If an entry is zero, it means that we don't know anything special.  */
 252
 253   unsigned char                 sign_bit_copies;
 254
 255   unsigned HOST_WIDE_INT        nonzero_bits;
 256
 257   /* Record the value of the label_tick when the last truncation
 258      happened.  The field truncated_to_mode is only valid if
 259      truncation_label == label_tick.  */
 260
 261   int                           truncation_label;
 262
 263   /* Record the last truncation seen for this register.  If truncation
 264      is not a nop to this mode we might be able to save an explicit
 265      truncation if we know that value already contains a truncated
 266      value.  */
 267
 268   ENUM_BITFIELD(machine_mode)   truncated_to_mode : 8;
 269 } reg_stat_type;
 270
 271
 272 static vec<reg_stat_type> reg_stat;
 273
 274 /* Record the luid of the last insn that invalidated memory
 275    (anything that writes memory, and subroutine calls, but not pushes).  */
 276
 277 static int mem_last_set;
 278
 279 /* Record the luid of the last CALL_INSN
 280    so we can tell whether a potential combination crosses any calls.  */
 281
 282 static int last_call_luid;
 283
 284 /* When `subst' is called, this is the insn that is being modified
 285    (by combining in a previous insn).  The PATTERN of this insn
 286    is still the old pattern partially modified and it should not be
 287    looked at, but this may be used to examine the successors of the insn
 288    to judge whether a simplification is valid.  */
 289
 290 static rtx_insn *subst_insn;
 291
 292 /* This is the lowest LUID that `subst' is currently dealing with.
 293    get_last_value will not return a value if the register was set at or
 294    after this LUID.  If not for this mechanism, we could get confused if
 295    I2 or I1 in try_combine were an insn that used the old value of a register
 296    to obtain a new value.  In that case, we might erroneously get the
 297    new value of the register when we wanted the old one.  */
 298
 299 static int subst_low_luid;
 300
 301 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 302    must consider all these registers to be always live.  */
 303
 304 static HARD_REG_SET newpat_used_regs;
 305
 306 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 307    insn is the earlier than I2 or I3, combine should rescan starting at
 308    that location.  */
 309
 310 static rtx_insn *added_links_insn;
 311
 312 /* Basic block in which we are performing combines.  */
 313 static basic_block this_basic_block;
 314 static bool optimize_this_for_speed_p;
 315
 316 \f
 317 /* Length of the currently allocated uid_insn_cost array.  */
 318
 319 static int max_uid_known;
 320
 321 /* The following array records the insn_rtx_cost for every insn
 322    in the instruction stream.  */
 323
 324 static int *uid_insn_cost;
 325
 326 /* The following array records the LOG_LINKS for every insn in the
 327    instruction stream as struct insn_link pointers.  */
 328
 329 struct insn_link {
 330   rtx_insn *insn;
 331   struct insn_link *next;
 332 };
 333
 334 static struct insn_link **uid_log_links;
 335
 336 #define INSN_COST(INSN)         (uid_insn_cost[INSN_UID (INSN)])
 337 #define LOG_LINKS(INSN)         (uid_log_links[INSN_UID (INSN)])
 338
 339 #define FOR_EACH_LOG_LINK(L, INSN)                              \
 340   for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
 341
 342 /* Links for LOG_LINKS are allocated from this obstack.  */
 343
 344 static struct obstack insn_link_obstack;
 345
 346 /* Allocate a link.  */
 347
 348 static inline struct insn_link *
 349 alloc_insn_link (rtx_insn *insn, struct insn_link *next)
 350 {
 351   struct insn_link *l
 352     = (struct insn_link *) obstack_alloc (&insn_link_obstack,
 353                                           sizeof (struct insn_link));
 354   l->insn = insn;
 355   l->next = next;
 356   return l;
 357 }
 358
 359 /* Incremented for each basic block.  */
 360
 361 static int label_tick;
 362
 363 /* Reset to label_tick for each extended basic block in scanning order.  */
 364
 365 static int label_tick_ebb_start;
 366
 367 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 368    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 369
 370 static machine_mode nonzero_bits_mode;
 371
 372 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 373    be safely used.  It is zero while computing them and after combine has
 374    completed.  This former test prevents propagating values based on
 375    previously set values, which can be incorrect if a variable is modified
 376    in a loop.  */
 377
 378 static int nonzero_sign_valid;
 379
 380 \f
 381 /* Record one modification to rtl structure
 382    to be undone by storing old_contents into *where.  */
 383
 384 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
 385
 386 struct undo
 387 {
 388   struct undo *next;
 389   enum undo_kind kind;
 390   union { rtx r; int i; machine_mode m; struct insn_link *l; } old_contents;
 391   union { rtx *r; int *i; struct insn_link **l; } where;
 392 };
 393
 394 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 395    num_undo says how many are currently recorded.
 396
 397    other_insn is nonzero if we have modified some other insn in the process
 398    of working on subst_insn.  It must be verified too.  */
 399
 400 struct undobuf
 401 {
 402   struct undo *undos;
 403   struct undo *frees;
 404   rtx_insn *other_insn;
 405 };
 406
 407 static struct undobuf undobuf;
 408
 409 /* Number of times the pseudo being substituted for
 410    was found and replaced.  */
 411
 412 static int n_occurrences;
 413
 414 static rtx reg_nonzero_bits_for_combine (const_rtx, machine_mode, const_rtx,
 415                                          machine_mode,
 416                                          unsigned HOST_WIDE_INT,
 417                                          unsigned HOST_WIDE_INT *);
 418 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, machine_mode, const_rtx,
 419                                                 machine_mode,
 420                                                 unsigned int, unsigned int *);
 421 static void do_SUBST (rtx *, rtx);
 422 static void do_SUBST_INT (int *, int);
 423 static void init_reg_last (void);
 424 static void setup_incoming_promotions (rtx_insn *);
 425 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
 426 static int cant_combine_insn_p (rtx_insn *);
 427 static int can_combine_p (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
 428                           rtx_insn *, rtx_insn *, rtx *, rtx *);
 429 static int combinable_i3pat (rtx_insn *, rtx *, rtx, rtx, rtx, int, int, rtx *);
 430 static int contains_muldiv (rtx);
 431 static rtx_insn *try_combine (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
 432                               int *, rtx_insn *);
 433 static void undo_all (void);
 434 static void undo_commit (void);
 435 static rtx *find_split_point (rtx *, rtx_insn *, bool);
 436 static rtx subst (rtx, rtx, rtx, int, int, int);
 437 static rtx combine_simplify_rtx (rtx, machine_mode, int, int);
 438 static rtx simplify_if_then_else (rtx);
 439 static rtx simplify_set (rtx);
 440 static rtx simplify_logical (rtx);
 441 static rtx expand_compound_operation (rtx);
 442 static const_rtx expand_field_assignment (const_rtx);
 443 static rtx make_extraction (machine_mode, rtx, HOST_WIDE_INT,
 444                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 445 static rtx extract_left_shift (rtx, int);
 446 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 447                               unsigned HOST_WIDE_INT *);
 448 static rtx canon_reg_for_combine (rtx, rtx);
 449 static rtx force_to_mode (rtx, machine_mode,
 450                           unsigned HOST_WIDE_INT, int);
 451 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 452 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 453 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 454 static rtx make_field_assignment (rtx);
 455 static rtx apply_distributive_law (rtx);
 456 static rtx distribute_and_simplify_rtx (rtx, int);
 457 static rtx simplify_and_const_int_1 (machine_mode, rtx,
 458                                      unsigned HOST_WIDE_INT);
 459 static rtx simplify_and_const_int (rtx, machine_mode, rtx,
 460                                    unsigned HOST_WIDE_INT);
 461 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 462                             HOST_WIDE_INT, machine_mode, int *);
 463 static rtx simplify_shift_const_1 (enum rtx_code, machine_mode, rtx, int);
 464 static rtx simplify_shift_const (rtx, enum rtx_code, machine_mode, rtx,
 465                                  int);
 466 static int recog_for_combine (rtx *, rtx_insn *, rtx *);
 467 static rtx gen_lowpart_for_combine (machine_mode, rtx);
 468 static enum rtx_code simplify_compare_const (enum rtx_code, machine_mode,
 469                                              rtx, rtx *);
 470 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 471 static void update_table_tick (rtx);
 472 static void record_value_for_reg (rtx, rtx_insn *, rtx);
 473 static void check_promoted_subreg (rtx_insn *, rtx);
 474 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
 475 static void record_dead_and_set_regs (rtx_insn *);
 476 static int get_last_value_validate (rtx *, rtx_insn *, int, int);
 477 static rtx get_last_value (const_rtx);
 478 static int use_crosses_set_p (const_rtx, int);
 479 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
 480 static int reg_dead_at_p (rtx, rtx_insn *);
 481 static void move_deaths (rtx, rtx, int, rtx_insn *, rtx *);
 482 static int reg_bitfield_target_p (rtx, rtx);
 483 static void distribute_notes (rtx, rtx_insn *, rtx_insn *, rtx_insn *, rtx, rtx, rtx);
 484 static void distribute_links (struct insn_link *);
 485 static void mark_used_regs_combine (rtx);
 486 static void record_promoted_value (rtx_insn *, rtx);
 487 static bool unmentioned_reg_p (rtx, rtx);
 488 static void record_truncated_values (rtx *, void *);
 489 static bool reg_truncated_to_mode (machine_mode, const_rtx);
 490 static rtx gen_lowpart_or_truncate (machine_mode, rtx);
 491 \f
 492
 493 /* It is not safe to use ordinary gen_lowpart in combine.
 494    See comments in gen_lowpart_for_combine.  */
 495 #undef RTL_HOOKS_GEN_LOWPART
 496 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 497
 498 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 499 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 500 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 501
 502 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 503 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 504
 505 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 506 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 507
 508 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
 509 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE    reg_truncated_to_mode
 510
 511 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 512
 513 \f
 514 /* Convenience wrapper for the canonicalize_comparison target hook.
 515    Target hooks cannot use enum rtx_code.  */
 516 static inline void
 517 target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1,
 518                                 bool op0_preserve_value)
 519 {
 520   int code_int = (int)*code;
 521   targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value);
 522   *code = (enum rtx_code)code_int;
 523 }
 524
 525 /* Try to split PATTERN found in INSN.  This returns NULL_RTX if
 526    PATTERN can not be split.  Otherwise, it returns an insn sequence.
 527    This is a wrapper around split_insns which ensures that the
 528    reg_stat vector is made larger if the splitter creates a new
 529    register.  */
 530
 531 static rtx_insn *
 532 combine_split_insns (rtx pattern, rtx insn)
 533 {
 534   rtx_insn *ret;
 535   unsigned int nregs;
 536
 537   ret = safe_as_a <rtx_insn *> (split_insns (pattern, insn));
 538   nregs = max_reg_num ();
 539   if (nregs > reg_stat.length ())
 540     reg_stat.safe_grow_cleared (nregs);
 541   return ret;
 542 }
 543
 544 /* This is used by find_single_use to locate an rtx in LOC that
 545    contains exactly one use of DEST, which is typically either a REG
 546    or CC0.  It returns a pointer to the innermost rtx expression
 547    containing DEST.  Appearances of DEST that are being used to
 548    totally replace it are not counted.  */
 549
 550 static rtx *
 551 find_single_use_1 (rtx dest, rtx *loc)
 552 {
 553   rtx x = *loc;
 554   enum rtx_code code = GET_CODE (x);
 555   rtx *result = NULL;
 556   rtx *this_result;
 557   int i;
 558   const char *fmt;
 559
 560   switch (code)
 561     {
 562     case CONST:
 563     case LABEL_REF:
 564     case SYMBOL_REF:
 565     CASE_CONST_ANY:
 566     case CLOBBER:
 567       return 0;
 568
 569     case SET:
 570       /* If the destination is anything other than CC0, PC, a REG or a SUBREG
 571          of a REG that occupies all of the REG, the insn uses DEST if
 572          it is mentioned in the destination or the source.  Otherwise, we
 573          need just check the source.  */
 574       if (GET_CODE (SET_DEST (x)) != CC0
 575           && GET_CODE (SET_DEST (x)) != PC
 576           && !REG_P (SET_DEST (x))
 577           && ! (GET_CODE (SET_DEST (x)) == SUBREG
 578                 && REG_P (SUBREG_REG (SET_DEST (x)))
 579                 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
 580                       + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
 581                     == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
 582                          + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
 583         break;
 584
 585       return find_single_use_1 (dest, &SET_SRC (x));
 586
 587     case MEM:
 588     case SUBREG:
 589       return find_single_use_1 (dest, &XEXP (x, 0));
 590
 591     default:
 592       break;
 593     }
 594
 595   /* If it wasn't one of the common cases above, check each expression and
 596      vector of this code.  Look for a unique usage of DEST.  */
 597
 598   fmt = GET_RTX_FORMAT (code);
 599   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
 600     {
 601       if (fmt[i] == 'e')
 602         {
 603           if (dest == XEXP (x, i)
 604               || (REG_P (dest) && REG_P (XEXP (x, i))
 605                   && REGNO (dest) == REGNO (XEXP (x, i))))
 606             this_result = loc;
 607           else
 608             this_result = find_single_use_1 (dest, &XEXP (x, i));
 609
 610           if (result == NULL)
 611             result = this_result;
 612           else if (this_result)
 613             /* Duplicate usage.  */
 614             return NULL;
 615         }
 616       else if (fmt[i] == 'E')
 617         {
 618           int j;
 619
 620           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
 621             {
 622               if (XVECEXP (x, i, j) == dest
 623                   || (REG_P (dest)
 624                       && REG_P (XVECEXP (x, i, j))
 625                       && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
 626                 this_result = loc;
 627               else
 628                 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
 629
 630               if (result == NULL)
 631                 result = this_result;
 632               else if (this_result)
 633                 return NULL;
 634             }
 635         }
 636     }
 637
 638   return result;
 639 }
 640
 641
 642 /* See if DEST, produced in INSN, is used only a single time in the
 643    sequel.  If so, return a pointer to the innermost rtx expression in which
 644    it is used.
 645
 646    If PLOC is nonzero, *PLOC is set to the insn containing the single use.
 647
 648    If DEST is cc0_rtx, we look only at the next insn.  In that case, we don't
 649    care about REG_DEAD notes or LOG_LINKS.
 650
 651    Otherwise, we find the single use by finding an insn that has a
 652    LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST.  If DEST is
 653    only referenced once in that insn, we know that it must be the first
 654    and last insn referencing DEST.  */
 655
 656 static rtx *
 657 find_single_use (rtx dest, rtx_insn *insn, rtx_insn **ploc)
 658 {
 659   basic_block bb;
 660   rtx_insn *next;
 661   rtx *result;
 662   struct insn_link *link;
 663
 664 #ifdef HAVE_cc0
 665   if (dest == cc0_rtx)
 666     {
 667       next = NEXT_INSN (insn);
 668       if (next == 0
 669           || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
 670         return 0;
 671
 672       result = find_single_use_1 (dest, &PATTERN (next));
 673       if (result && ploc)
 674         *ploc = next;
 675       return result;
 676     }
 677 #endif
 678
 679   if (!REG_P (dest))
 680     return 0;
 681
 682   bb = BLOCK_FOR_INSN (insn);
 683   for (next = NEXT_INSN (insn);
 684        next && BLOCK_FOR_INSN (next) == bb;
 685        next = NEXT_INSN (next))
 686     if (INSN_P (next) && dead_or_set_p (next, dest))
 687       {
 688         FOR_EACH_LOG_LINK (link, next)
 689           if (link->insn == insn)
 690             break;
 691
 692         if (link)
 693           {
 694             result = find_single_use_1 (dest, &PATTERN (next));
 695             if (ploc)
 696               *ploc = next;
 697             return result;
 698           }
 699       }
 700
 701   return 0;
 702 }
 703 \f
 704 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 705    insn.  The substitution can be undone by undo_all.  If INTO is already
 706    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 707    also call SUBST, we have to compute it before we put anything into
 708    the undo table.  */
 709
 710 static void
 711 do_SUBST (rtx *into, rtx newval)
 712 {
 713   struct undo *buf;
 714   rtx oldval = *into;
 715
 716   if (oldval == newval)
 717     return;
 718
 719   /* We'd like to catch as many invalid transformations here as
 720      possible.  Unfortunately, there are way too many mode changes
 721      that are perfectly valid, so we'd waste too much effort for
 722      little gain doing the checks here.  Focus on catching invalid
 723      transformations involving integer constants.  */
 724   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 725       && CONST_INT_P (newval))
 726     {
 727       /* Sanity check that we're replacing oldval with a CONST_INT
 728          that is a valid sign-extension for the original mode.  */
 729       gcc_assert (INTVAL (newval)
 730                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 731
 732       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 733          CONST_INT is not valid, because after the replacement, the
 734          original mode would be gone.  Unfortunately, we can't tell
 735          when do_SUBST is called to replace the operand thereof, so we
 736          perform this test on oldval instead, checking whether an
 737          invalid replacement took place before we got here.  */
 738       gcc_assert (!(GET_CODE (oldval) == SUBREG
 739                     && CONST_INT_P (SUBREG_REG (oldval))));
 740       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 741                     && CONST_INT_P (XEXP (oldval, 0))));
 742     }
 743
 744   if (undobuf.frees)
 745     buf = undobuf.frees, undobuf.frees = buf->next;
 746   else
 747     buf = XNEW (struct undo);
 748
 749   buf->kind = UNDO_RTX;
 750   buf->where.r = into;
 751   buf->old_contents.r = oldval;
 752   *into = newval;
 753
 754   buf->next = undobuf.undos, undobuf.undos = buf;
 755 }
 756
 757 #define SUBST(INTO, NEWVAL)     do_SUBST (&(INTO), (NEWVAL))
 758
 759 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 760    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 761    not safe.  */
 762
 763 static void
 764 do_SUBST_INT (int *into, int newval)
 765 {
 766   struct undo *buf;
 767   int oldval = *into;
 768
 769   if (oldval == newval)
 770     return;
 771
 772   if (undobuf.frees)
 773     buf = undobuf.frees, undobuf.frees = buf->next;
 774   else
 775     buf = XNEW (struct undo);
 776
 777   buf->kind = UNDO_INT;
 778   buf->where.i = into;
 779   buf->old_contents.i = oldval;
 780   *into = newval;
 781
 782   buf->next = undobuf.undos, undobuf.undos = buf;
 783 }
 784
 785 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT (&(INTO), (NEWVAL))
 786
 787 /* Similar to SUBST, but just substitute the mode.  This is used when
 788    changing the mode of a pseudo-register, so that any other
 789    references to the entry in the regno_reg_rtx array will change as
 790    well.  */
 791
 792 static void
 793 do_SUBST_MODE (rtx *into, machine_mode newval)
 794 {
 795   struct undo *buf;
 796   machine_mode oldval = GET_MODE (*into);
 797
 798   if (oldval == newval)
 799     return;
 800
 801   if (undobuf.frees)
 802     buf = undobuf.frees, undobuf.frees = buf->next;
 803   else
 804     buf = XNEW (struct undo);
 805
 806   buf->kind = UNDO_MODE;
 807   buf->where.r = into;
 808   buf->old_contents.m = oldval;
 809   adjust_reg_mode (*into, newval);
 810
 811   buf->next = undobuf.undos, undobuf.undos = buf;
 812 }
 813
 814 #define SUBST_MODE(INTO, NEWVAL)  do_SUBST_MODE (&(INTO), (NEWVAL))
 815
 816 #ifndef HAVE_cc0
 817 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression.  */
 818
 819 static void
 820 do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
 821 {
 822   struct undo *buf;
 823   struct insn_link * oldval = *into;
 824
 825   if (oldval == newval)
 826     return;
 827
 828   if (undobuf.frees)
 829     buf = undobuf.frees, undobuf.frees = buf->next;
 830   else
 831     buf = XNEW (struct undo);
 832
 833   buf->kind = UNDO_LINKS;
 834   buf->where.l = into;
 835   buf->old_contents.l = oldval;
 836   *into = newval;
 837
 838   buf->next = undobuf.undos, undobuf.undos = buf;
 839 }
 840
 841 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
 842 #endif
 843 \f
 844 /* Subroutine of try_combine.  Determine whether the replacement patterns
 845    NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
 846    than the original sequence I0, I1, I2, I3 and undobuf.other_insn.  Note
 847    that I0, I1 and/or NEWI2PAT may be NULL_RTX.  Similarly, NEWOTHERPAT and
 848    undobuf.other_insn may also both be NULL_RTX.  Return false if the cost
 849    of all the instructions can be estimated and the replacements are more
 850    expensive than the original sequence.  */
 851
 852 static bool
 853 combine_validate_cost (rtx_insn *i0, rtx_insn *i1, rtx_insn *i2, rtx_insn *i3,
 854                        rtx newpat, rtx newi2pat, rtx newotherpat)
 855 {
 856   int i0_cost, i1_cost, i2_cost, i3_cost;
 857   int new_i2_cost, new_i3_cost;
 858   int old_cost, new_cost;
 859
 860   /* Lookup the original insn_rtx_costs.  */
 861   i2_cost = INSN_COST (i2);
 862   i3_cost = INSN_COST (i3);
 863
 864   if (i1)
 865     {
 866       i1_cost = INSN_COST (i1);
 867       if (i0)
 868         {
 869           i0_cost = INSN_COST (i0);
 870           old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 871                       ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
 872         }
 873       else
 874         {
 875           old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 876                       ? i1_cost + i2_cost + i3_cost : 0);
 877           i0_cost = 0;
 878         }
 879     }
 880   else
 881     {
 882       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 883       i1_cost = i0_cost = 0;
 884     }
 885
 886   /* Calculate the replacement insn_rtx_costs.  */
 887   new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
 888   if (newi2pat)
 889     {
 890       new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
 891       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 892                  ? new_i2_cost + new_i3_cost : 0;
 893     }
 894   else
 895     {
 896       new_cost = new_i3_cost;
 897       new_i2_cost = 0;
 898     }
 899
 900   if (undobuf.other_insn)
 901     {
 902       int old_other_cost, new_other_cost;
 903
 904       old_other_cost = INSN_COST (undobuf.other_insn);
 905       new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
 906       if (old_other_cost > 0 && new_other_cost > 0)
 907         {
 908           old_cost += old_other_cost;
 909           new_cost += new_other_cost;
 910         }
 911       else
 912         old_cost = 0;
 913     }
 914
 915   /* Disallow this combination if both new_cost and old_cost are greater than
 916      zero, and new_cost is greater than old cost.  */
 917   int reject = old_cost > 0 && new_cost > old_cost;
 918
 919   if (dump_file)
 920     {
 921       fprintf (dump_file, "%s combination of insns ",
 922                reject ? "rejecting" : "allowing");
 923       if (i0)
 924         fprintf (dump_file, "%d, ", INSN_UID (i0));
 925       if (i1)
 926         fprintf (dump_file, "%d, ", INSN_UID (i1));
 927       fprintf (dump_file, "%d and %d\n", INSN_UID (i2), INSN_UID (i3));
 928
 929       fprintf (dump_file, "original costs ");
 930       if (i0)
 931         fprintf (dump_file, "%d + ", i0_cost);
 932       if (i1)
 933         fprintf (dump_file, "%d + ", i1_cost);
 934       fprintf (dump_file, "%d + %d = %d\n", i2_cost, i3_cost, old_cost);
 935
 936       if (newi2pat)
 937         fprintf (dump_file, "replacement costs %d + %d = %d\n",
 938                  new_i2_cost, new_i3_cost, new_cost);
 939       else
 940         fprintf (dump_file, "replacement cost %d\n", new_cost);
 941     }
 942
 943   if (reject)
 944     return false;
 945
 946   /* Update the uid_insn_cost array with the replacement costs.  */
 947   INSN_COST (i2) = new_i2_cost;
 948   INSN_COST (i3) = new_i3_cost;
 949   if (i1)
 950     {
 951       INSN_COST (i1) = 0;
 952       if (i0)
 953         INSN_COST (i0) = 0;
 954     }
 955
 956   return true;
 957 }
 958
 959
 960 /* Delete any insns that copy a register to itself.  */
 961
 962 static void
 963 delete_noop_moves (void)
 964 {
 965   rtx_insn *insn, *next;
 966   basic_block bb;
 967
 968   FOR_EACH_BB_FN (bb, cfun)
 969     {
 970       for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
 971         {
 972           next = NEXT_INSN (insn);
 973           if (INSN_P (insn) && noop_move_p (insn))
 974             {
 975               if (dump_file)
 976                 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
 977
 978               delete_insn_and_edges (insn);
 979             }
 980         }
 981     }
 982 }
 983
 984 \f
 985 /* Fill in log links field for all insns.  */
 986
 987 static void
 988 create_log_links (void)
 989 {
 990   basic_block bb;
 991   rtx_insn **next_use;
 992   rtx_insn *insn;
 993   df_ref def, use;
 994
 995   next_use = XCNEWVEC (rtx_insn *, max_reg_num ());
 996
 997   /* Pass through each block from the end, recording the uses of each
 998      register and establishing log links when def is encountered.
 999      Note that we do not clear next_use array in order to save time,
1000      so we have to test whether the use is in the same basic block as def.
1001
1002      There are a few cases below when we do not consider the definition or
1003      usage -- these are taken from original flow.c did. Don't ask me why it is
1004      done this way; I don't know and if it works, I don't want to know.  */
1005
1006   FOR_EACH_BB_FN (bb, cfun)
1007     {
1008       FOR_BB_INSNS_REVERSE (bb, insn)
1009         {
1010           if (!NONDEBUG_INSN_P (insn))
1011             continue;
1012
1013           /* Log links are created only once.  */
1014           gcc_assert (!LOG_LINKS (insn));
1015
1016           FOR_EACH_INSN_DEF (def, insn)
1017             {
1018               int regno = DF_REF_REGNO (def);
1019               rtx_insn *use_insn;
1020
1021               if (!next_use[regno])
1022                 continue;
1023
1024               /* Do not consider if it is pre/post modification in MEM.  */
1025               if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
1026                 continue;
1027
1028               /* Do not make the log link for frame pointer.  */
1029               if ((regno == FRAME_POINTER_REGNUM
1030                    && (! reload_completed || frame_pointer_needed))
1031 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1032                   || (regno == HARD_FRAME_POINTER_REGNUM
1033                       && (! reload_completed || frame_pointer_needed))
1034 #endif
1035 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1036                   || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
1037 #endif
1038                   )
1039                 continue;
1040
1041               use_insn = next_use[regno];
1042               if (BLOCK_FOR_INSN (use_insn) == bb)
1043                 {
1044                   /* flow.c claimed:
1045
1046                      We don't build a LOG_LINK for hard registers contained
1047                      in ASM_OPERANDs.  If these registers get replaced,
1048                      we might wind up changing the semantics of the insn,
1049                      even if reload can make what appear to be valid
1050                      assignments later.  */
1051                   if (regno >= FIRST_PSEUDO_REGISTER
1052                       || asm_noperands (PATTERN (use_insn)) < 0)
1053                     {
1054                       /* Don't add duplicate links between instructions.  */
1055                       struct insn_link *links;
1056                       FOR_EACH_LOG_LINK (links, use_insn)
1057                         if (insn == links->insn)
1058                           break;
1059
1060                       if (!links)
1061                         LOG_LINKS (use_insn)
1062                           = alloc_insn_link (insn, LOG_LINKS (use_insn));
1063                     }
1064                 }
1065               next_use[regno] = NULL;
1066             }
1067
1068           FOR_EACH_INSN_USE (use, insn)
1069             {
1070               int regno = DF_REF_REGNO (use);
1071
1072               /* Do not consider the usage of the stack pointer
1073                  by function call.  */
1074               if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1075                 continue;
1076
1077               next_use[regno] = insn;
1078             }
1079         }
1080     }
1081
1082   free (next_use);
1083 }
1084
1085 /* Walk the LOG_LINKS of insn B to see if we find a reference to A.  Return
1086    true if we found a LOG_LINK that proves that A feeds B.  This only works
1087    if there are no instructions between A and B which could have a link
1088    depending on A, since in that case we would not record a link for B.
1089    We also check the implicit dependency created by a cc0 setter/user
1090    pair.  */
1091
1092 static bool
1093 insn_a_feeds_b (rtx_insn *a, rtx_insn *b)
1094 {
1095   struct insn_link *links;
1096   FOR_EACH_LOG_LINK (links, b)
1097     if (links->insn == a)
1098       return true;
1099 #ifdef HAVE_cc0
1100   if (sets_cc0_p (a))
1101     return true;
1102 #endif
1103   return false;
1104 }
1105 \f
1106 /* Main entry point for combiner.  F is the first insn of the function.
1107    NREGS is the first unused pseudo-reg number.
1108
1109    Return nonzero if the combiner has turned an indirect jump
1110    instruction into a direct jump.  */
1111 static int
1112 combine_instructions (rtx_insn *f, unsigned int nregs)
1113 {
1114   rtx_insn *insn, *next;
1115 #ifdef HAVE_cc0
1116   rtx_insn *prev;
1117 #endif
1118   struct insn_link *links, *nextlinks;
1119   rtx_insn *first;
1120   basic_block last_bb;
1121
1122   int new_direct_jump_p = 0;
1123
1124   for (first = f; first && !INSN_P (first); )
1125     first = NEXT_INSN (first);
1126   if (!first)
1127     return 0;
1128
1129   combine_attempts = 0;
1130   combine_merges = 0;
1131   combine_extras = 0;
1132   combine_successes = 0;
1133
1134   rtl_hooks = combine_rtl_hooks;
1135
1136   reg_stat.safe_grow_cleared (nregs);
1137
1138   init_recog_no_volatile ();
1139
1140   /* Allocate array for insn info.  */
1141   max_uid_known = get_max_uid ();
1142   uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1143   uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1144   gcc_obstack_init (&insn_link_obstack);
1145
1146   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1147
1148   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
1149      problems when, for example, we have j <<= 1 in a loop.  */
1150
1151   nonzero_sign_valid = 0;
1152   label_tick = label_tick_ebb_start = 1;
1153
1154   /* Scan all SETs and see if we can deduce anything about what
1155      bits are known to be zero for some registers and how many copies
1156      of the sign bit are known to exist for those registers.
1157
1158      Also set any known values so that we can use it while searching
1159      for what bits are known to be set.  */
1160
1161   setup_incoming_promotions (first);
1162   /* Allow the entry block and the first block to fall into the same EBB.
1163      Conceptually the incoming promotions are assigned to the entry block.  */
1164   last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1165
1166   create_log_links ();
1167   FOR_EACH_BB_FN (this_basic_block, cfun)
1168     {
1169       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1170       last_call_luid = 0;
1171       mem_last_set = -1;
1172
1173       label_tick++;
1174       if (!single_pred_p (this_basic_block)
1175           || single_pred (this_basic_block) != last_bb)
1176         label_tick_ebb_start = label_tick;
1177       last_bb = this_basic_block;
1178
1179       FOR_BB_INSNS (this_basic_block, insn)
1180         if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1181           {
1182 #ifdef AUTO_INC_DEC
1183             rtx links;
1184 #endif
1185
1186             subst_low_luid = DF_INSN_LUID (insn);
1187             subst_insn = insn;
1188
1189             note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1190                          insn);
1191             record_dead_and_set_regs (insn);
1192
1193 #ifdef AUTO_INC_DEC
1194             for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1195               if (REG_NOTE_KIND (links) == REG_INC)
1196                 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1197                                                   insn);
1198 #endif
1199
1200             /* Record the current insn_rtx_cost of this instruction.  */
1201             if (NONJUMP_INSN_P (insn))
1202               INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1203                                                 optimize_this_for_speed_p);
1204             if (dump_file)
1205               fprintf (dump_file, "insn_cost %d: %d\n",
1206                        INSN_UID (insn), INSN_COST (insn));
1207           }
1208     }
1209
1210   nonzero_sign_valid = 1;
1211
1212   /* Now scan all the insns in forward order.  */
1213   label_tick = label_tick_ebb_start = 1;
1214   init_reg_last ();
1215   setup_incoming_promotions (first);
1216   last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1217   int max_combine = PARAM_VALUE (PARAM_MAX_COMBINE_INSNS);
1218
1219   FOR_EACH_BB_FN (this_basic_block, cfun)
1220     {
1221       rtx_insn *last_combined_insn = NULL;
1222       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1223       last_call_luid = 0;
1224       mem_last_set = -1;
1225
1226       label_tick++;
1227       if (!single_pred_p (this_basic_block)
1228           || single_pred (this_basic_block) != last_bb)
1229         label_tick_ebb_start = label_tick;
1230       last_bb = this_basic_block;
1231
1232       rtl_profile_for_bb (this_basic_block);
1233       for (insn = BB_HEAD (this_basic_block);
1234            insn != NEXT_INSN (BB_END (this_basic_block));
1235            insn = next ? next : NEXT_INSN (insn))
1236         {
1237           next = 0;
1238           if (!NONDEBUG_INSN_P (insn))
1239             continue;
1240
1241           while (last_combined_insn
1242                  && last_combined_insn->deleted ())
1243             last_combined_insn = PREV_INSN (last_combined_insn);
1244           if (last_combined_insn == NULL_RTX
1245               || BARRIER_P (last_combined_insn)
1246               || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1247               || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1248             last_combined_insn = insn;
1249
1250           /* See if we know about function return values before this
1251              insn based upon SUBREG flags.  */
1252           check_promoted_subreg (insn, PATTERN (insn));
1253
1254           /* See if we can find hardregs and subreg of pseudos in
1255              narrower modes.  This could help turning TRUNCATEs
1256              into SUBREGs.  */
1257           note_uses (&PATTERN (insn), record_truncated_values, NULL);
1258
1259           /* Try this insn with each insn it links back to.  */
1260
1261           FOR_EACH_LOG_LINK (links, insn)
1262             if ((next = try_combine (insn, links->insn, NULL,
1263                                      NULL, &new_direct_jump_p,
1264                                      last_combined_insn)) != 0)
1265               {
1266                 statistics_counter_event (cfun, "two-insn combine", 1);
1267                 goto retry;
1268               }
1269
1270           /* Try each sequence of three linked insns ending with this one.  */
1271
1272           if (max_combine >= 3)
1273             FOR_EACH_LOG_LINK (links, insn)
1274               {
1275                 rtx_insn *link = links->insn;
1276
1277                 /* If the linked insn has been replaced by a note, then there
1278                    is no point in pursuing this chain any further.  */
1279                 if (NOTE_P (link))
1280                   continue;
1281
1282                 FOR_EACH_LOG_LINK (nextlinks, link)
1283                   if ((next = try_combine (insn, link, nextlinks->insn,
1284                                            NULL, &new_direct_jump_p,
1285                                            last_combined_insn)) != 0)
1286                     {
1287                       statistics_counter_event (cfun, "three-insn combine", 1);
1288                       goto retry;
1289                     }
1290               }
1291
1292 #ifdef HAVE_cc0
1293           /* Try to combine a jump insn that uses CC0
1294              with a preceding insn that sets CC0, and maybe with its
1295              logical predecessor as well.
1296              This is how we make decrement-and-branch insns.
1297              We need this special code because data flow connections
1298              via CC0 do not get entered in LOG_LINKS.  */
1299
1300           if (JUMP_P (insn)
1301               && (prev = prev_nonnote_insn (insn)) != 0
1302               && NONJUMP_INSN_P (prev)
1303               && sets_cc0_p (PATTERN (prev)))
1304             {
1305               if ((next = try_combine (insn, prev, NULL, NULL,
1306                                        &new_direct_jump_p,
1307                                        last_combined_insn)) != 0)
1308                 goto retry;
1309
1310               FOR_EACH_LOG_LINK (nextlinks, prev)
1311                   if ((next = try_combine (insn, prev, nextlinks->insn,
1312                                            NULL, &new_direct_jump_p,
1313                                            last_combined_insn)) != 0)
1314                     goto retry;
1315             }
1316
1317           /* Do the same for an insn that explicitly references CC0.  */
1318           if (NONJUMP_INSN_P (insn)
1319               && (prev = prev_nonnote_insn (insn)) != 0
1320               && NONJUMP_INSN_P (prev)
1321               && sets_cc0_p (PATTERN (prev))
1322               && GET_CODE (PATTERN (insn)) == SET
1323               && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1324             {
1325               if ((next = try_combine (insn, prev, NULL, NULL,
1326                                        &new_direct_jump_p,
1327                                        last_combined_insn)) != 0)
1328                 goto retry;
1329
1330               FOR_EACH_LOG_LINK (nextlinks, prev)
1331                   if ((next = try_combine (insn, prev, nextlinks->insn,
1332                                            NULL, &new_direct_jump_p,
1333                                            last_combined_insn)) != 0)
1334                     goto retry;
1335             }
1336
1337           /* Finally, see if any of the insns that this insn links to
1338              explicitly references CC0.  If so, try this insn, that insn,
1339              and its predecessor if it sets CC0.  */
1340           FOR_EACH_LOG_LINK (links, insn)
1341               if (NONJUMP_INSN_P (links->insn)
1342                   && GET_CODE (PATTERN (links->insn)) == SET
1343                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
1344                   && (prev = prev_nonnote_insn (links->insn)) != 0
1345                   && NONJUMP_INSN_P (prev)
1346                   && sets_cc0_p (PATTERN (prev))
1347                   && (next = try_combine (insn, links->insn,
1348                                           prev, NULL, &new_direct_jump_p,
1349                                           last_combined_insn)) != 0)
1350                 goto retry;
1351 #endif
1352
1353           /* Try combining an insn with two different insns whose results it
1354              uses.  */
1355           if (max_combine >= 3)
1356             FOR_EACH_LOG_LINK (links, insn)
1357               for (nextlinks = links->next; nextlinks;
1358                    nextlinks = nextlinks->next)
1359                 if ((next = try_combine (insn, links->insn,
1360                                          nextlinks->insn, NULL,
1361                                          &new_direct_jump_p,
1362                                          last_combined_insn)) != 0)
1363
1364                   {
1365                     statistics_counter_event (cfun, "three-insn combine", 1);
1366                     goto retry;
1367                   }
1368
1369           /* Try four-instruction combinations.  */
1370           if (max_combine >= 4)
1371             FOR_EACH_LOG_LINK (links, insn)
1372               {
1373                 struct insn_link *next1;
1374                 rtx_insn *link = links->insn;
1375
1376                 /* If the linked insn has been replaced by a note, then there
1377                    is no point in pursuing this chain any further.  */
1378                 if (NOTE_P (link))
1379                   continue;
1380
1381                 FOR_EACH_LOG_LINK (next1, link)
1382                   {
1383                     rtx_insn *link1 = next1->insn;
1384                     if (NOTE_P (link1))
1385                       continue;
1386                     /* I0 -> I1 -> I2 -> I3.  */
1387                     FOR_EACH_LOG_LINK (nextlinks, link1)
1388                       if ((next = try_combine (insn, link, link1,
1389                                                nextlinks->insn,
1390                                                &new_direct_jump_p,
1391                                                last_combined_insn)) != 0)
1392                         {
1393                           statistics_counter_event (cfun, "four-insn combine", 1);
1394                           goto retry;
1395                         }
1396                     /* I0, I1 -> I2, I2 -> I3.  */
1397                     for (nextlinks = next1->next; nextlinks;
1398                          nextlinks = nextlinks->next)
1399                       if ((next = try_combine (insn, link, link1,
1400                                                nextlinks->insn,
1401                                                &new_direct_jump_p,
1402                                                last_combined_insn)) != 0)
1403                         {
1404                           statistics_counter_event (cfun, "four-insn combine", 1);
1405                           goto retry;
1406                         }
1407                   }
1408
1409                 for (next1 = links->next; next1; next1 = next1->next)
1410                   {
1411                     rtx_insn *link1 = next1->insn;
1412                     if (NOTE_P (link1))
1413                       continue;
1414                     /* I0 -> I2; I1, I2 -> I3.  */
1415                     FOR_EACH_LOG_LINK (nextlinks, link)
1416                       if ((next = try_combine (insn, link, link1,
1417                                                nextlinks->insn,
1418                                                &new_direct_jump_p,
1419                                                last_combined_insn)) != 0)
1420                         {
1421                           statistics_counter_event (cfun, "four-insn combine", 1);
1422                           goto retry;
1423                         }
1424                     /* I0 -> I1; I1, I2 -> I3.  */
1425                     FOR_EACH_LOG_LINK (nextlinks, link1)
1426                       if ((next = try_combine (insn, link, link1,
1427                                                nextlinks->insn,
1428                                                &new_direct_jump_p,
1429                                                last_combined_insn)) != 0)
1430                         {
1431                           statistics_counter_event (cfun, "four-insn combine", 1);
1432                           goto retry;
1433                         }
1434                   }
1435               }
1436
1437           /* Try this insn with each REG_EQUAL note it links back to.  */
1438           FOR_EACH_LOG_LINK (links, insn)
1439             {
1440               rtx set, note;
1441               rtx_insn *temp = links->insn;
1442               if ((set = single_set (temp)) != 0
1443                   && (note = find_reg_equal_equiv_note (temp)) != 0
1444                   && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1445                   /* Avoid using a register that may already been marked
1446                      dead by an earlier instruction.  */
1447                   && ! unmentioned_reg_p (note, SET_SRC (set))
1448                   && (GET_MODE (note) == VOIDmode
1449                       ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1450                       : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1451                 {
1452                   /* Temporarily replace the set's source with the
1453                      contents of the REG_EQUAL note.  The insn will
1454                      be deleted or recognized by try_combine.  */
1455                   rtx orig = SET_SRC (set);
1456                   SET_SRC (set) = note;
1457                   i2mod = temp;
1458                   i2mod_old_rhs = copy_rtx (orig);
1459                   i2mod_new_rhs = copy_rtx (note);
1460                   next = try_combine (insn, i2mod, NULL, NULL,
1461                                       &new_direct_jump_p,
1462                                       last_combined_insn);
1463                   i2mod = NULL;
1464                   if (next)
1465                     {
1466                       statistics_counter_event (cfun, "insn-with-note combine", 1);
1467                       goto retry;
1468                     }
1469                   SET_SRC (set) = orig;
1470                 }
1471             }
1472
1473           if (!NOTE_P (insn))
1474             record_dead_and_set_regs (insn);
1475
1476 retry:
1477           ;
1478         }
1479     }
1480
1481   default_rtl_profile ();
1482   clear_bb_flags ();
1483   new_direct_jump_p |= purge_all_dead_edges ();
1484   delete_noop_moves ();
1485
1486   /* Clean up.  */
1487   obstack_free (&insn_link_obstack, NULL);
1488   free (uid_log_links);
1489   free (uid_insn_cost);
1490   reg_stat.release ();
1491
1492   {
1493     struct undo *undo, *next;
1494     for (undo = undobuf.frees; undo; undo = next)
1495       {
1496         next = undo->next;
1497         free (undo);
1498       }
1499     undobuf.frees = 0;
1500   }
1501
1502   total_attempts += combine_attempts;
1503   total_merges += combine_merges;
1504   total_extras += combine_extras;
1505   total_successes += combine_successes;
1506
1507   nonzero_sign_valid = 0;
1508   rtl_hooks = general_rtl_hooks;
1509
1510   /* Make recognizer allow volatile MEMs again.  */
1511   init_recog ();
1512
1513   return new_direct_jump_p;
1514 }
1515
1516 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
1517
1518 static void
1519 init_reg_last (void)
1520 {
1521   unsigned int i;
1522   reg_stat_type *p;
1523
1524   FOR_EACH_VEC_ELT (reg_stat, i, p)
1525     memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1526 }
1527 \f
1528 /* Set up any promoted values for incoming argument registers.  */
1529
1530 static void
1531 setup_incoming_promotions (rtx_insn *first)
1532 {
1533   tree arg;
1534   bool strictly_local = false;
1535
1536   for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1537        arg = DECL_CHAIN (arg))
1538     {
1539       rtx x, reg = DECL_INCOMING_RTL (arg);
1540       int uns1, uns3;
1541       machine_mode mode1, mode2, mode3, mode4;
1542
1543       /* Only continue if the incoming argument is in a register.  */
1544       if (!REG_P (reg))
1545         continue;
1546
1547       /* Determine, if possible, whether all call sites of the current
1548          function lie within the current compilation unit.  (This does
1549          take into account the exporting of a function via taking its
1550          address, and so forth.)  */
1551       strictly_local = cgraph_node::local_info (current_function_decl)->local;
1552
1553       /* The mode and signedness of the argument before any promotions happen
1554          (equal to the mode of the pseudo holding it at that stage).  */
1555       mode1 = TYPE_MODE (TREE_TYPE (arg));
1556       uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1557
1558       /* The mode and signedness of the argument after any source language and
1559          TARGET_PROMOTE_PROTOTYPES-driven promotions.  */
1560       mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1561       uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1562
1563       /* The mode and signedness of the argument as it is actually passed,
1564          after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions.  */
1565       mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1566                                      TREE_TYPE (cfun->decl), 0);
1567
1568       /* The mode of the register in which the argument is being passed.  */
1569       mode4 = GET_MODE (reg);
1570
1571       /* Eliminate sign extensions in the callee when:
1572          (a) A mode promotion has occurred;  */
1573       if (mode1 == mode3)
1574         continue;
1575       /* (b) The mode of the register is the same as the mode of
1576              the argument as it is passed; */
1577       if (mode3 != mode4)
1578         continue;
1579       /* (c) There's no language level extension;  */
1580       if (mode1 == mode2)
1581         ;
1582       /* (c.1) All callers are from the current compilation unit.  If that's
1583          the case we don't have to rely on an ABI, we only have to know
1584          what we're generating right now, and we know that we will do the
1585          mode1 to mode2 promotion with the given sign.  */
1586       else if (!strictly_local)
1587         continue;
1588       /* (c.2) The combination of the two promotions is useful.  This is
1589          true when the signs match, or if the first promotion is unsigned.
1590          In the later case, (sign_extend (zero_extend x)) is the same as
1591          (zero_extend (zero_extend x)), so make sure to force UNS3 true.  */
1592       else if (uns1)
1593         uns3 = true;
1594       else if (uns3)
1595         continue;
1596
1597       /* Record that the value was promoted from mode1 to mode3,
1598          so that any sign extension at the head of the current
1599          function may be eliminated.  */
1600       x = gen_rtx_CLOBBER (mode1, const0_rtx);
1601       x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1602       record_value_for_reg (reg, first, x);
1603     }
1604 }
1605
1606 /* Called via note_stores.  If X is a pseudo that is narrower than
1607    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1608
1609    If we are setting only a portion of X and we can't figure out what
1610    portion, assume all bits will be used since we don't know what will
1611    be happening.
1612
1613    Similarly, set how many bits of X are known to be copies of the sign bit
1614    at all locations in the function.  This is the smallest number implied
1615    by any set of X.  */
1616
1617 static void
1618 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1619 {
1620   rtx_insn *insn = (rtx_insn *) data;
1621   unsigned int num;
1622
1623   if (REG_P (x)
1624       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1625       /* If this register is undefined at the start of the file, we can't
1626          say what its contents were.  */
1627       && ! REGNO_REG_SET_P
1628            (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), REGNO (x))
1629       && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
1630     {
1631       reg_stat_type *rsp = &reg_stat[REGNO (x)];
1632
1633       if (set == 0 || GET_CODE (set) == CLOBBER)
1634         {
1635           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1636           rsp->sign_bit_copies = 1;
1637           return;
1638         }
1639
1640       /* If this register is being initialized using itself, and the
1641          register is uninitialized in this basic block, and there are
1642          no LOG_LINKS which set the register, then part of the
1643          register is uninitialized.  In that case we can't assume
1644          anything about the number of nonzero bits.
1645
1646          ??? We could do better if we checked this in
1647          reg_{nonzero_bits,num_sign_bit_copies}_for_combine.  Then we
1648          could avoid making assumptions about the insn which initially
1649          sets the register, while still using the information in other
1650          insns.  We would have to be careful to check every insn
1651          involved in the combination.  */
1652
1653       if (insn
1654           && reg_referenced_p (x, PATTERN (insn))
1655           && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1656                                REGNO (x)))
1657         {
1658           struct insn_link *link;
1659
1660           FOR_EACH_LOG_LINK (link, insn)
1661             if (dead_or_set_p (link->insn, x))
1662               break;
1663           if (!link)
1664             {
1665               rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1666               rsp->sign_bit_copies = 1;
1667               return;
1668             }
1669         }
1670
1671       /* If this is a complex assignment, see if we can convert it into a
1672          simple assignment.  */
1673       set = expand_field_assignment (set);
1674
1675       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1676          set what we know about X.  */
1677
1678       if (SET_DEST (set) == x
1679           || (paradoxical_subreg_p (SET_DEST (set))
1680               && SUBREG_REG (SET_DEST (set)) == x))
1681         {
1682           rtx src = SET_SRC (set);
1683
1684 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1685           /* If X is narrower than a word and SRC is a non-negative
1686              constant that would appear negative in the mode of X,
1687              sign-extend it for use in reg_stat[].nonzero_bits because some
1688              machines (maybe most) will actually do the sign-extension
1689              and this is the conservative approach.
1690
1691              ??? For 2.5, try to tighten up the MD files in this regard
1692              instead of this kludge.  */
1693
1694           if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD
1695               && CONST_INT_P (src)
1696               && INTVAL (src) > 0
1697               && val_signbit_known_set_p (GET_MODE (x), INTVAL (src)))
1698             src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (GET_MODE (x)));
1699 #endif
1700
1701           /* Don't call nonzero_bits if it cannot change anything.  */
1702           if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1703             rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1704           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1705           if (rsp->sign_bit_copies == 0
1706               || rsp->sign_bit_copies > num)
1707             rsp->sign_bit_copies = num;
1708         }
1709       else
1710         {
1711           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1712           rsp->sign_bit_copies = 1;
1713         }
1714     }
1715 }
1716 \f
1717 /* See if INSN can be combined into I3.  PRED, PRED2, SUCC and SUCC2 are
1718    optionally insns that were previously combined into I3 or that will be
1719    combined into the merger of INSN and I3.  The order is PRED, PRED2,
1720    INSN, SUCC, SUCC2, I3.
1721
1722    Return 0 if the combination is not allowed for any reason.
1723
1724    If the combination is allowed, *PDEST will be set to the single
1725    destination of INSN and *PSRC to the single source, and this function
1726    will return 1.  */
1727
1728 static int
1729 can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED,
1730                rtx_insn *pred2 ATTRIBUTE_UNUSED, rtx_insn *succ, rtx_insn *succ2,
1731                rtx *pdest, rtx *psrc)
1732 {
1733   int i;
1734   const_rtx set = 0;
1735   rtx src, dest;
1736   rtx_insn *p;
1737 #ifdef AUTO_INC_DEC
1738   rtx link;
1739 #endif
1740   bool all_adjacent = true;
1741   int (*is_volatile_p) (const_rtx);
1742
1743   if (succ)
1744     {
1745       if (succ2)
1746         {
1747           if (next_active_insn (succ2) != i3)
1748             all_adjacent = false;
1749           if (next_active_insn (succ) != succ2)
1750             all_adjacent = false;
1751         }
1752       else if (next_active_insn (succ) != i3)
1753         all_adjacent = false;
1754       if (next_active_insn (insn) != succ)
1755         all_adjacent = false;
1756     }
1757   else if (next_active_insn (insn) != i3)
1758     all_adjacent = false;
1759
1760   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1761      or a PARALLEL consisting of such a SET and CLOBBERs.
1762
1763      If INSN has CLOBBER parallel parts, ignore them for our processing.
1764      By definition, these happen during the execution of the insn.  When it
1765      is merged with another insn, all bets are off.  If they are, in fact,
1766      needed and aren't also supplied in I3, they may be added by
1767      recog_for_combine.  Otherwise, it won't match.
1768
1769      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1770      note.
1771
1772      Get the source and destination of INSN.  If more than one, can't
1773      combine.  */
1774
1775   if (GET_CODE (PATTERN (insn)) == SET)
1776     set = PATTERN (insn);
1777   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1778            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1779     {
1780       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1781         {
1782           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1783
1784           switch (GET_CODE (elt))
1785             {
1786             /* This is important to combine floating point insns
1787                for the SH4 port.  */
1788             case USE:
1789               /* Combining an isolated USE doesn't make sense.
1790                  We depend here on combinable_i3pat to reject them.  */
1791               /* The code below this loop only verifies that the inputs of
1792                  the SET in INSN do not change.  We call reg_set_between_p
1793                  to verify that the REG in the USE does not change between
1794                  I3 and INSN.
1795                  If the USE in INSN was for a pseudo register, the matching
1796                  insn pattern will likely match any register; combining this
1797                  with any other USE would only be safe if we knew that the
1798                  used registers have identical values, or if there was
1799                  something to tell them apart, e.g. different modes.  For
1800                  now, we forgo such complicated tests and simply disallow
1801                  combining of USES of pseudo registers with any other USE.  */
1802               if (REG_P (XEXP (elt, 0))
1803                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1804                 {
1805                   rtx i3pat = PATTERN (i3);
1806                   int i = XVECLEN (i3pat, 0) - 1;
1807                   unsigned int regno = REGNO (XEXP (elt, 0));
1808
1809                   do
1810                     {
1811                       rtx i3elt = XVECEXP (i3pat, 0, i);
1812
1813                       if (GET_CODE (i3elt) == USE
1814                           && REG_P (XEXP (i3elt, 0))
1815                           && (REGNO (XEXP (i3elt, 0)) == regno
1816                               ? reg_set_between_p (XEXP (elt, 0),
1817                                                    PREV_INSN (insn), i3)
1818                               : regno >= FIRST_PSEUDO_REGISTER))
1819                         return 0;
1820                     }
1821                   while (--i >= 0);
1822                 }
1823               break;
1824
1825               /* We can ignore CLOBBERs.  */
1826             case CLOBBER:
1827               break;
1828
1829             case SET:
1830               /* Ignore SETs whose result isn't used but not those that
1831                  have side-effects.  */
1832               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1833                   && insn_nothrow_p (insn)
1834                   && !side_effects_p (elt))
1835                 break;
1836
1837               /* If we have already found a SET, this is a second one and
1838                  so we cannot combine with this insn.  */
1839               if (set)
1840                 return 0;
1841
1842               set = elt;
1843               break;
1844
1845             default:
1846               /* Anything else means we can't combine.  */
1847               return 0;
1848             }
1849         }
1850
1851       if (set == 0
1852           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1853              so don't do anything with it.  */
1854           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1855         return 0;
1856     }
1857   else
1858     return 0;
1859
1860   if (set == 0)
1861     return 0;
1862
1863   /* The simplification in expand_field_assignment may call back to
1864      get_last_value, so set safe guard here.  */
1865   subst_low_luid = DF_INSN_LUID (insn);
1866
1867   set = expand_field_assignment (set);
1868   src = SET_SRC (set), dest = SET_DEST (set);
1869
1870   /* Don't eliminate a store in the stack pointer.  */
1871   if (dest == stack_pointer_rtx
1872       /* Don't combine with an insn that sets a register to itself if it has
1873          a REG_EQUAL note.  This may be part of a LIBCALL sequence.  */
1874       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1875       /* Can't merge an ASM_OPERANDS.  */
1876       || GET_CODE (src) == ASM_OPERANDS
1877       /* Can't merge a function call.  */
1878       || GET_CODE (src) == CALL
1879       /* Don't eliminate a function call argument.  */
1880       || (CALL_P (i3)
1881           && (find_reg_fusage (i3, USE, dest)
1882               || (REG_P (dest)
1883                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1884                   && global_regs[REGNO (dest)])))
1885       /* Don't substitute into an incremented register.  */
1886       || FIND_REG_INC_NOTE (i3, dest)
1887       || (succ && FIND_REG_INC_NOTE (succ, dest))
1888       || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1889       /* Don't substitute into a non-local goto, this confuses CFG.  */
1890       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1891       /* Make sure that DEST is not used after SUCC but before I3.  */
1892       || (!all_adjacent
1893           && ((succ2
1894                && (reg_used_between_p (dest, succ2, i3)
1895                    || reg_used_between_p (dest, succ, succ2)))
1896               || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1897       /* Make sure that the value that is to be substituted for the register
1898          does not use any registers whose values alter in between.  However,
1899          If the insns are adjacent, a use can't cross a set even though we
1900          think it might (this can happen for a sequence of insns each setting
1901          the same destination; last_set of that register might point to
1902          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1903          equivalent to the memory so the substitution is valid even if there
1904          are intervening stores.  Also, don't move a volatile asm or
1905          UNSPEC_VOLATILE across any other insns.  */
1906       || (! all_adjacent
1907           && (((!MEM_P (src)
1908                 || ! find_reg_note (insn, REG_EQUIV, src))
1909                && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1910               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1911               || GET_CODE (src) == UNSPEC_VOLATILE))
1912       /* Don't combine across a CALL_INSN, because that would possibly
1913          change whether the life span of some REGs crosses calls or not,
1914          and it is a pain to update that information.
1915          Exception: if source is a constant, moving it later can't hurt.
1916          Accept that as a special case.  */
1917       || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1918     return 0;
1919
1920   /* DEST must either be a REG or CC0.  */
1921   if (REG_P (dest))
1922     {
1923       /* If register alignment is being enforced for multi-word items in all
1924          cases except for parameters, it is possible to have a register copy
1925          insn referencing a hard register that is not allowed to contain the
1926          mode being copied and which would not be valid as an operand of most
1927          insns.  Eliminate this problem by not combining with such an insn.
1928
1929          Also, on some machines we don't want to extend the life of a hard
1930          register.  */
1931
1932       if (REG_P (src)
1933           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1934                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1935               /* Don't extend the life of a hard register unless it is
1936                  user variable (if we have few registers) or it can't
1937                  fit into the desired register (meaning something special
1938                  is going on).
1939                  Also avoid substituting a return register into I3, because
1940                  reload can't handle a conflict with constraints of other
1941                  inputs.  */
1942               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1943                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1944         return 0;
1945     }
1946   else if (GET_CODE (dest) != CC0)
1947     return 0;
1948
1949
1950   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1951     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1952       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1953         {
1954           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1955
1956           /* If the clobber represents an earlyclobber operand, we must not
1957              substitute an expression containing the clobbered register.
1958              As we do not analyze the constraint strings here, we have to
1959              make the conservative assumption.  However, if the register is
1960              a fixed hard reg, the clobber cannot represent any operand;
1961              we leave it up to the machine description to either accept or
1962              reject use-and-clobber patterns.  */
1963           if (!REG_P (reg)
1964               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1965               || !fixed_regs[REGNO (reg)])
1966             if (reg_overlap_mentioned_p (reg, src))
1967               return 0;
1968         }
1969
1970   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1971      or not), reject, unless nothing volatile comes between it and I3 */
1972
1973   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1974     {
1975       /* Make sure neither succ nor succ2 contains a volatile reference.  */
1976       if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1977         return 0;
1978       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1979         return 0;
1980       /* We'll check insns between INSN and I3 below.  */
1981     }
1982
1983   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1984      to be an explicit register variable, and was chosen for a reason.  */
1985
1986   if (GET_CODE (src) == ASM_OPERANDS
1987       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1988     return 0;
1989
1990   /* If INSN contains volatile references (specifically volatile MEMs),
1991      we cannot combine across any other volatile references.
1992      Even if INSN doesn't contain volatile references, any intervening
1993      volatile insn might affect machine state.  */
1994
1995   is_volatile_p = volatile_refs_p (PATTERN (insn))
1996     ? volatile_refs_p
1997     : volatile_insn_p;
1998
1999   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
2000     if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (p)))
2001       return 0;
2002
2003   /* If INSN contains an autoincrement or autodecrement, make sure that
2004      register is not used between there and I3, and not already used in
2005      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
2006      Also insist that I3 not be a jump; if it were one
2007      and the incremented register were spilled, we would lose.  */
2008
2009 #ifdef AUTO_INC_DEC
2010   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
2011     if (REG_NOTE_KIND (link) == REG_INC
2012         && (JUMP_P (i3)
2013             || reg_used_between_p (XEXP (link, 0), insn, i3)
2014             || (pred != NULL_RTX
2015                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
2016             || (pred2 != NULL_RTX
2017                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
2018             || (succ != NULL_RTX
2019                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
2020             || (succ2 != NULL_RTX
2021                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
2022             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
2023       return 0;
2024 #endif
2025
2026 #ifdef HAVE_cc0
2027   /* Don't combine an insn that follows a CC0-setting insn.
2028      An insn that uses CC0 must not be separated from the one that sets it.
2029      We do, however, allow I2 to follow a CC0-setting insn if that insn
2030      is passed as I1; in that case it will be deleted also.
2031      We also allow combining in this case if all the insns are adjacent
2032      because that would leave the two CC0 insns adjacent as well.
2033      It would be more logical to test whether CC0 occurs inside I1 or I2,
2034      but that would be much slower, and this ought to be equivalent.  */
2035
2036   p = prev_nonnote_insn (insn);
2037   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
2038       && ! all_adjacent)
2039     return 0;
2040 #endif
2041
2042   /* If we get here, we have passed all the tests and the combination is
2043      to be allowed.  */
2044
2045   *pdest = dest;
2046   *psrc = src;
2047
2048   return 1;
2049 }
2050 \f
2051 /* LOC is the location within I3 that contains its pattern or the component
2052    of a PARALLEL of the pattern.  We validate that it is valid for combining.
2053
2054    One problem is if I3 modifies its output, as opposed to replacing it
2055    entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2056    doing so would produce an insn that is not equivalent to the original insns.
2057
2058    Consider:
2059
2060          (set (reg:DI 101) (reg:DI 100))
2061          (set (subreg:SI (reg:DI 101) 0) <foo>)
2062
2063    This is NOT equivalent to:
2064
2065          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2066                     (set (reg:DI 101) (reg:DI 100))])
2067
2068    Not only does this modify 100 (in which case it might still be valid
2069    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2070
2071    We can also run into a problem if I2 sets a register that I1
2072    uses and I1 gets directly substituted into I3 (not via I2).  In that
2073    case, we would be getting the wrong value of I2DEST into I3, so we
2074    must reject the combination.  This case occurs when I2 and I1 both
2075    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2076    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2077    of a SET must prevent combination from occurring.  The same situation
2078    can occur for I0, in which case I0_NOT_IN_SRC is set.
2079
2080    Before doing the above check, we first try to expand a field assignment
2081    into a set of logical operations.
2082
2083    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2084    we place a register that is both set and used within I3.  If more than one
2085    such register is detected, we fail.
2086
2087    Return 1 if the combination is valid, zero otherwise.  */
2088
2089 static int
2090 combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2091                   int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2092 {
2093   rtx x = *loc;
2094
2095   if (GET_CODE (x) == SET)
2096     {
2097       rtx set = x ;
2098       rtx dest = SET_DEST (set);
2099       rtx src = SET_SRC (set);
2100       rtx inner_dest = dest;
2101       rtx subdest;
2102
2103       while (GET_CODE (inner_dest) == STRICT_LOW_PART
2104              || GET_CODE (inner_dest) == SUBREG
2105              || GET_CODE (inner_dest) == ZERO_EXTRACT)
2106         inner_dest = XEXP (inner_dest, 0);
2107
2108       /* Check for the case where I3 modifies its output, as discussed
2109          above.  We don't want to prevent pseudos from being combined
2110          into the address of a MEM, so only prevent the combination if
2111          i1 or i2 set the same MEM.  */
2112       if ((inner_dest != dest &&
2113            (!MEM_P (inner_dest)
2114             || rtx_equal_p (i2dest, inner_dest)
2115             || (i1dest && rtx_equal_p (i1dest, inner_dest))
2116             || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2117            && (reg_overlap_mentioned_p (i2dest, inner_dest)
2118                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2119                || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2120
2121           /* This is the same test done in can_combine_p except we can't test
2122              all_adjacent; we don't have to, since this instruction will stay
2123              in place, thus we are not considering increasing the lifetime of
2124              INNER_DEST.
2125
2126              Also, if this insn sets a function argument, combining it with
2127              something that might need a spill could clobber a previous
2128              function argument; the all_adjacent test in can_combine_p also
2129              checks this; here, we do a more specific test for this case.  */
2130
2131           || (REG_P (inner_dest)
2132               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2133               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2134                                         GET_MODE (inner_dest))))
2135           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2136           || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2137         return 0;
2138
2139       /* If DEST is used in I3, it is being killed in this insn, so
2140          record that for later.  We have to consider paradoxical
2141          subregs here, since they kill the whole register, but we
2142          ignore partial subregs, STRICT_LOW_PART, etc.
2143          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2144          STACK_POINTER_REGNUM, since these are always considered to be
2145          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
2146       subdest = dest;
2147       if (GET_CODE (subdest) == SUBREG
2148           && (GET_MODE_SIZE (GET_MODE (subdest))
2149               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2150         subdest = SUBREG_REG (subdest);
2151       if (pi3dest_killed
2152           && REG_P (subdest)
2153           && reg_referenced_p (subdest, PATTERN (i3))
2154           && REGNO (subdest) != FRAME_POINTER_REGNUM
2155 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2156           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2157 #endif
2158 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2159           && (REGNO (subdest) != ARG_POINTER_REGNUM
2160               || ! fixed_regs [REGNO (subdest)])
2161 #endif
2162           && REGNO (subdest) != STACK_POINTER_REGNUM)
2163         {
2164           if (*pi3dest_killed)
2165             return 0;
2166
2167           *pi3dest_killed = subdest;
2168         }
2169     }
2170
2171   else if (GET_CODE (x) == PARALLEL)
2172     {
2173       int i;
2174
2175       for (i = 0; i < XVECLEN (x, 0); i++)
2176         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2177                                 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2178           return 0;
2179     }
2180
2181   return 1;
2182 }
2183 \f
2184 /* Return 1 if X is an arithmetic expression that contains a multiplication
2185    and division.  We don't count multiplications by powers of two here.  */
2186
2187 static int
2188 contains_muldiv (rtx x)
2189 {
2190   switch (GET_CODE (x))
2191     {
2192     case MOD:  case DIV:  case UMOD:  case UDIV:
2193       return 1;
2194
2195     case MULT:
2196       return ! (CONST_INT_P (XEXP (x, 1))
2197                 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0);
2198     default:
2199       if (BINARY_P (x))
2200         return contains_muldiv (XEXP (x, 0))
2201             || contains_muldiv (XEXP (x, 1));
2202
2203       if (UNARY_P (x))
2204         return contains_muldiv (XEXP (x, 0));
2205
2206       return 0;
2207     }
2208 }
2209 \f
2210 /* Determine whether INSN can be used in a combination.  Return nonzero if
2211    not.  This is used in try_combine to detect early some cases where we
2212    can't perform combinations.  */
2213
2214 static int
2215 cant_combine_insn_p (rtx_insn *insn)
2216 {
2217   rtx set;
2218   rtx src, dest;
2219
2220   /* If this isn't really an insn, we can't do anything.
2221      This can occur when flow deletes an insn that it has merged into an
2222      auto-increment address.  */
2223   if (! INSN_P (insn))
2224     return 1;
2225
2226   /* Never combine loads and stores involving hard regs that are likely
2227      to be spilled.  The register allocator can usually handle such
2228      reg-reg moves by tying.  If we allow the combiner to make
2229      substitutions of likely-spilled regs, reload might die.
2230      As an exception, we allow combinations involving fixed regs; these are
2231      not available to the register allocator so there's no risk involved.  */
2232
2233   set = single_set (insn);
2234   if (! set)
2235     return 0;
2236   src = SET_SRC (set);
2237   dest = SET_DEST (set);
2238   if (GET_CODE (src) == SUBREG)
2239     src = SUBREG_REG (src);
2240   if (GET_CODE (dest) == SUBREG)
2241     dest = SUBREG_REG (dest);
2242   if (REG_P (src) && REG_P (dest)
2243       && ((HARD_REGISTER_P (src)
2244            && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2245            && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2246           || (HARD_REGISTER_P (dest)
2247               && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2248               && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2249     return 1;
2250
2251   return 0;
2252 }
2253
2254 struct likely_spilled_retval_info
2255 {
2256   unsigned regno, nregs;
2257   unsigned mask;
2258 };
2259
2260 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
2261    hard registers that are known to be written to / clobbered in full.  */
2262 static void
2263 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2264 {
2265   struct likely_spilled_retval_info *const info =
2266     (struct likely_spilled_retval_info *) data;
2267   unsigned regno, nregs;
2268   unsigned new_mask;
2269
2270   if (!REG_P (XEXP (set, 0)))
2271     return;
2272   regno = REGNO (x);
2273   if (regno >= info->regno + info->nregs)
2274     return;
2275   nregs = hard_regno_nregs[regno][GET_MODE (x)];
2276   if (regno + nregs <= info->regno)
2277     return;
2278   new_mask = (2U << (nregs - 1)) - 1;
2279   if (regno < info->regno)
2280     new_mask >>= info->regno - regno;
2281   else
2282     new_mask <<= regno - info->regno;
2283   info->mask &= ~new_mask;
2284 }
2285
2286 /* Return nonzero iff part of the return value is live during INSN, and
2287    it is likely spilled.  This can happen when more than one insn is needed
2288    to copy the return value, e.g. when we consider to combine into the
2289    second copy insn for a complex value.  */
2290
2291 static int
2292 likely_spilled_retval_p (rtx_insn *insn)
2293 {
2294   rtx_insn *use = BB_END (this_basic_block);
2295   rtx reg;
2296   rtx_insn *p;
2297   unsigned regno, nregs;
2298   /* We assume here that no machine mode needs more than
2299      32 hard registers when the value overlaps with a register
2300      for which TARGET_FUNCTION_VALUE_REGNO_P is true.  */
2301   unsigned mask;
2302   struct likely_spilled_retval_info info;
2303
2304   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2305     return 0;
2306   reg = XEXP (PATTERN (use), 0);
2307   if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2308     return 0;
2309   regno = REGNO (reg);
2310   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2311   if (nregs == 1)
2312     return 0;
2313   mask = (2U << (nregs - 1)) - 1;
2314
2315   /* Disregard parts of the return value that are set later.  */
2316   info.regno = regno;
2317   info.nregs = nregs;
2318   info.mask = mask;
2319   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2320     if (INSN_P (p))
2321       note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2322   mask = info.mask;
2323
2324   /* Check if any of the (probably) live return value registers is
2325      likely spilled.  */
2326   nregs --;
2327   do
2328     {
2329       if ((mask & 1 << nregs)
2330           && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2331         return 1;
2332     } while (nregs--);
2333   return 0;
2334 }
2335
2336 /* Adjust INSN after we made a change to its destination.
2337
2338    Changing the destination can invalidate notes that say something about
2339    the results of the insn and a LOG_LINK pointing to the insn.  */
2340
2341 static void
2342 adjust_for_new_dest (rtx_insn *insn)
2343 {
2344   /* For notes, be conservative and simply remove them.  */
2345   remove_reg_equal_equiv_notes (insn);
2346
2347   /* The new insn will have a destination that was previously the destination
2348      of an insn just above it.  Call distribute_links to make a LOG_LINK from
2349      the next use of that destination.  */
2350   distribute_links (alloc_insn_link (insn, NULL));
2351
2352   df_insn_rescan (insn);
2353 }
2354
2355 /* Return TRUE if combine can reuse reg X in mode MODE.
2356    ADDED_SETS is nonzero if the original set is still required.  */
2357 static bool
2358 can_change_dest_mode (rtx x, int added_sets, machine_mode mode)
2359 {
2360   unsigned int regno;
2361
2362   if (!REG_P (x))
2363     return false;
2364
2365   regno = REGNO (x);
2366   /* Allow hard registers if the new mode is legal, and occupies no more
2367      registers than the old mode.  */
2368   if (regno < FIRST_PSEUDO_REGISTER)
2369     return (HARD_REGNO_MODE_OK (regno, mode)
2370             && (hard_regno_nregs[regno][GET_MODE (x)]
2371                 >= hard_regno_nregs[regno][mode]));
2372
2373   /* Or a pseudo that is only used once.  */
2374   return (REG_N_SETS (regno) == 1 && !added_sets
2375           && !REG_USERVAR_P (x));
2376 }
2377
2378
2379 /* Check whether X, the destination of a set, refers to part of
2380    the register specified by REG.  */
2381
2382 static bool
2383 reg_subword_p (rtx x, rtx reg)
2384 {
2385   /* Check that reg is an integer mode register.  */
2386   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2387     return false;
2388
2389   if (GET_CODE (x) == STRICT_LOW_PART
2390       || GET_CODE (x) == ZERO_EXTRACT)
2391     x = XEXP (x, 0);
2392
2393   return GET_CODE (x) == SUBREG
2394          && SUBREG_REG (x) == reg
2395          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2396 }
2397
2398 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2399    Note that the INSN should be deleted *after* removing dead edges, so
2400    that the kept edge is the fallthrough edge for a (set (pc) (pc))
2401    but not for a (set (pc) (label_ref FOO)).  */
2402
2403 static void
2404 update_cfg_for_uncondjump (rtx_insn *insn)
2405 {
2406   basic_block bb = BLOCK_FOR_INSN (insn);
2407   gcc_assert (BB_END (bb) == insn);
2408
2409   purge_dead_edges (bb);
2410
2411   delete_insn (insn);
2412   if (EDGE_COUNT (bb->succs) == 1)
2413     {
2414       rtx_insn *insn;
2415
2416       single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2417
2418       /* Remove barriers from the footer if there are any.  */
2419       for (insn = BB_FOOTER (bb); insn; insn = NEXT_INSN (insn))
2420         if (BARRIER_P (insn))
2421           {
2422             if (PREV_INSN (insn))
2423               SET_NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2424             else
2425               BB_FOOTER (bb) = NEXT_INSN (insn);
2426             if (NEXT_INSN (insn))
2427               SET_PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2428           }
2429         else if (LABEL_P (insn))
2430           break;
2431     }
2432 }
2433
2434 /* Try to combine the insns I0, I1 and I2 into I3.
2435    Here I0, I1 and I2 appear earlier than I3.
2436    I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2437    I3.
2438
2439    If we are combining more than two insns and the resulting insn is not
2440    recognized, try splitting it into two insns.  If that happens, I2 and I3
2441    are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2442    Otherwise, I0, I1 and I2 are pseudo-deleted.
2443
2444    Return 0 if the combination does not work.  Then nothing is changed.
2445    If we did the combination, return the insn at which combine should
2446    resume scanning.
2447
2448    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2449    new direct jump instruction.
2450
2451    LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2452    been I3 passed to an earlier try_combine within the same basic
2453    block.  */
2454
2455 static rtx_insn *
2456 try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
2457              int *new_direct_jump_p, rtx_insn *last_combined_insn)
2458 {
2459   /* New patterns for I3 and I2, respectively.  */
2460   rtx newpat, newi2pat = 0;
2461   rtvec newpat_vec_with_clobbers = 0;
2462   int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2463   /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2464      dead.  */
2465   int added_sets_0, added_sets_1, added_sets_2;
2466   /* Total number of SETs to put into I3.  */
2467   int total_sets;
2468   /* Nonzero if I2's or I1's body now appears in I3.  */
2469   int i2_is_used = 0, i1_is_used = 0;
2470   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
2471   int insn_code_number, i2_code_number = 0, other_code_number = 0;
2472   /* Contains I3 if the destination of I3 is used in its source, which means
2473      that the old life of I3 is being killed.  If that usage is placed into
2474      I2 and not in I3, a REG_DEAD note must be made.  */
2475   rtx i3dest_killed = 0;
2476   /* SET_DEST and SET_SRC of I2, I1 and I0.  */
2477   rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2478   /* Copy of SET_SRC of I1 and I0, if needed.  */
2479   rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2480   /* Set if I2DEST was reused as a scratch register.  */
2481   bool i2scratch = false;
2482   /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases.  */
2483   rtx i0pat = 0, i1pat = 0, i2pat = 0;
2484   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
2485   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2486   int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2487   int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2488   int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2489   /* Notes that must be added to REG_NOTES in I3 and I2.  */
2490   rtx new_i3_notes, new_i2_notes;
2491   /* Notes that we substituted I3 into I2 instead of the normal case.  */
2492   int i3_subst_into_i2 = 0;
2493   /* Notes that I1, I2 or I3 is a MULT operation.  */
2494   int have_mult = 0;
2495   int swap_i2i3 = 0;
2496   int changed_i3_dest = 0;
2497
2498   int maxreg;
2499   rtx_insn *temp_insn;
2500   rtx temp_expr;
2501   struct insn_link *link;
2502   rtx other_pat = 0;
2503   rtx new_other_notes;
2504   int i;
2505
2506   /* Only try four-insn combinations when there's high likelihood of
2507      success.  Look for simple insns, such as loads of constants or
2508      binary operations involving a constant.  */
2509   if (i0)
2510     {
2511       int i;
2512       int ngood = 0;
2513       int nshift = 0;
2514
2515       if (!flag_expensive_optimizations)
2516         return 0;
2517
2518       for (i = 0; i < 4; i++)
2519         {
2520           rtx_insn *insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2521           rtx set = single_set (insn);
2522           rtx src;
2523           if (!set)
2524             continue;
2525           src = SET_SRC (set);
2526           if (CONSTANT_P (src))
2527             {
2528               ngood += 2;
2529               break;
2530             }
2531           else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2532             ngood++;
2533           else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2534                    || GET_CODE (src) == LSHIFTRT)
2535             nshift++;
2536         }
2537       if (ngood < 2 && nshift < 2)
2538         return 0;
2539     }
2540
2541   /* Exit early if one of the insns involved can't be used for
2542      combinations.  */
2543   if (CALL_P (i2)
2544       || (i1 && CALL_P (i1))
2545       || (i0 && CALL_P (i0))
2546       || cant_combine_insn_p (i3)
2547       || cant_combine_insn_p (i2)
2548       || (i1 && cant_combine_insn_p (i1))
2549       || (i0 && cant_combine_insn_p (i0))
2550       || likely_spilled_retval_p (i3))
2551     return 0;
2552
2553   combine_attempts++;
2554   undobuf.other_insn = 0;
2555
2556   /* Reset the hard register usage information.  */
2557   CLEAR_HARD_REG_SET (newpat_used_regs);
2558
2559   if (dump_file && (dump_flags & TDF_DETAILS))
2560     {
2561       if (i0)
2562         fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2563                  INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2564       else if (i1)
2565         fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2566                  INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2567       else
2568         fprintf (dump_file, "\nTrying %d -> %d:\n",
2569                  INSN_UID (i2), INSN_UID (i3));
2570     }
2571
2572   /* If multiple insns feed into one of I2 or I3, they can be in any
2573      order.  To simplify the code below, reorder them in sequence.  */
2574   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2575     temp_insn = i2, i2 = i0, i0 = temp_insn;
2576   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2577     temp_insn = i1, i1 = i0, i0 = temp_insn;
2578   if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2579     temp_insn = i1, i1 = i2, i2 = temp_insn;
2580
2581   added_links_insn = 0;
2582
2583   /* First check for one important special case that the code below will
2584      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
2585      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
2586      we may be able to replace that destination with the destination of I3.
2587      This occurs in the common code where we compute both a quotient and
2588      remainder into a structure, in which case we want to do the computation
2589      directly into the structure to avoid register-register copies.
2590
2591      Note that this case handles both multiple sets in I2 and also cases
2592      where I2 has a number of CLOBBERs inside the PARALLEL.
2593
2594      We make very conservative checks below and only try to handle the
2595      most common cases of this.  For example, we only handle the case
2596      where I2 and I3 are adjacent to avoid making difficult register
2597      usage tests.  */
2598
2599   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2600       && REG_P (SET_SRC (PATTERN (i3)))
2601       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2602       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2603       && GET_CODE (PATTERN (i2)) == PARALLEL
2604       && ! side_effects_p (SET_DEST (PATTERN (i3)))
2605       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2606          below would need to check what is inside (and reg_overlap_mentioned_p
2607          doesn't support those codes anyway).  Don't allow those destinations;
2608          the resulting insn isn't likely to be recognized anyway.  */
2609       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2610       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2611       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2612                                     SET_DEST (PATTERN (i3)))
2613       && next_active_insn (i2) == i3)
2614     {
2615       rtx p2 = PATTERN (i2);
2616
2617       /* Make sure that the destination of I3,
2618          which we are going to substitute into one output of I2,
2619          is not used within another output of I2.  We must avoid making this:
2620          (parallel [(set (mem (reg 69)) ...)
2621                     (set (reg 69) ...)])
2622          which is not well-defined as to order of actions.
2623          (Besides, reload can't handle output reloads for this.)
2624
2625          The problem can also happen if the dest of I3 is a memory ref,
2626          if another dest in I2 is an indirect memory ref.  */
2627       for (i = 0; i < XVECLEN (p2, 0); i++)
2628         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2629              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2630             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2631                                         SET_DEST (XVECEXP (p2, 0, i))))
2632           break;
2633
2634       if (i == XVECLEN (p2, 0))
2635         for (i = 0; i < XVECLEN (p2, 0); i++)
2636           if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2637               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2638             {
2639               combine_merges++;
2640
2641               subst_insn = i3;
2642               subst_low_luid = DF_INSN_LUID (i2);
2643
2644               added_sets_2 = added_sets_1 = added_sets_0 = 0;
2645               i2src = SET_SRC (XVECEXP (p2, 0, i));
2646               i2dest = SET_DEST (XVECEXP (p2, 0, i));
2647               i2dest_killed = dead_or_set_p (i2, i2dest);
2648
2649               /* Replace the dest in I2 with our dest and make the resulting
2650                  insn the new pattern for I3.  Then skip to where we validate
2651                  the pattern.  Everything was set up above.  */
2652               SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2653               newpat = p2;
2654               i3_subst_into_i2 = 1;
2655               goto validate_replacement;
2656             }
2657     }
2658
2659   /* If I2 is setting a pseudo to a constant and I3 is setting some
2660      sub-part of it to another constant, merge them by making a new
2661      constant.  */
2662   if (i1 == 0
2663       && (temp_expr = single_set (i2)) != 0
2664       && CONST_SCALAR_INT_P (SET_SRC (temp_expr))
2665       && GET_CODE (PATTERN (i3)) == SET
2666       && CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3)))
2667       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp_expr)))
2668     {
2669       rtx dest = SET_DEST (PATTERN (i3));
2670       int offset = -1;
2671       int width = 0;
2672
2673       if (GET_CODE (dest) == ZERO_EXTRACT)
2674         {
2675           if (CONST_INT_P (XEXP (dest, 1))
2676               && CONST_INT_P (XEXP (dest, 2)))
2677             {
2678               width = INTVAL (XEXP (dest, 1));
2679               offset = INTVAL (XEXP (dest, 2));
2680               dest = XEXP (dest, 0);
2681               if (BITS_BIG_ENDIAN)
2682                 offset = GET_MODE_PRECISION (GET_MODE (dest)) - width - offset;
2683             }
2684         }
2685       else
2686         {
2687           if (GET_CODE (dest) == STRICT_LOW_PART)
2688             dest = XEXP (dest, 0);
2689           width = GET_MODE_PRECISION (GET_MODE (dest));
2690           offset = 0;
2691         }
2692
2693       if (offset >= 0)
2694         {
2695           /* If this is the low part, we're done.  */
2696           if (subreg_lowpart_p (dest))
2697             ;
2698           /* Handle the case where inner is twice the size of outer.  */
2699           else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp_expr)))
2700                    == 2 * GET_MODE_PRECISION (GET_MODE (dest)))
2701             offset += GET_MODE_PRECISION (GET_MODE (dest));
2702           /* Otherwise give up for now.  */
2703           else
2704             offset = -1;
2705         }
2706
2707       if (offset >= 0)
2708         {
2709           rtx inner = SET_SRC (PATTERN (i3));
2710           rtx outer = SET_SRC (temp_expr);
2711
2712           wide_int o
2713             = wi::insert (std::make_pair (outer, GET_MODE (SET_DEST (temp_expr))),
2714                           std::make_pair (inner, GET_MODE (dest)),
2715                           offset, width);
2716
2717           combine_merges++;
2718           subst_insn = i3;
2719           subst_low_luid = DF_INSN_LUID (i2);
2720           added_sets_2 = added_sets_1 = added_sets_0 = 0;
2721           i2dest = SET_DEST (temp_expr);
2722           i2dest_killed = dead_or_set_p (i2, i2dest);
2723
2724           /* Replace the source in I2 with the new constant and make the
2725              resulting insn the new pattern for I3.  Then skip to where we
2726              validate the pattern.  Everything was set up above.  */
2727           SUBST (SET_SRC (temp_expr),
2728                  immed_wide_int_const (o, GET_MODE (SET_DEST (temp_expr))));
2729
2730           newpat = PATTERN (i2);
2731
2732           /* The dest of I3 has been replaced with the dest of I2.  */
2733           changed_i3_dest = 1;
2734           goto validate_replacement;
2735         }
2736     }
2737
2738 #ifndef HAVE_cc0
2739   /* If we have no I1 and I2 looks like:
2740         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2741                    (set Y OP)])
2742      make up a dummy I1 that is
2743         (set Y OP)
2744      and change I2 to be
2745         (set (reg:CC X) (compare:CC Y (const_int 0)))
2746
2747      (We can ignore any trailing CLOBBERs.)
2748
2749      This undoes a previous combination and allows us to match a branch-and-
2750      decrement insn.  */
2751
2752   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2753       && XVECLEN (PATTERN (i2), 0) >= 2
2754       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2755       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2756           == MODE_CC)
2757       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2758       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2759       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2760       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2761       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2762                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2763     {
2764       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2765         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2766           break;
2767
2768       if (i == 1)
2769         {
2770           /* We make I1 with the same INSN_UID as I2.  This gives it
2771              the same DF_INSN_LUID for value tracking.  Our fake I1 will
2772              never appear in the insn stream so giving it the same INSN_UID
2773              as I2 will not cause a problem.  */
2774
2775           i1 = gen_rtx_INSN (VOIDmode, NULL, i2, BLOCK_FOR_INSN (i2),
2776                              XVECEXP (PATTERN (i2), 0, 1), INSN_LOCATION (i2),
2777                              -1, NULL_RTX);
2778           INSN_UID (i1) = INSN_UID (i2);
2779
2780           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2781           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2782                  SET_DEST (PATTERN (i1)));
2783           SUBST_LINK (LOG_LINKS (i2), alloc_insn_link (i1, LOG_LINKS (i2)));
2784         }
2785     }
2786 #endif
2787
2788   /* Verify that I2 and I1 are valid for combining.  */
2789   if (! can_combine_p (i2, i3, i0, i1, NULL, NULL, &i2dest, &i2src)
2790       || (i1 && ! can_combine_p (i1, i3, i0, NULL, i2, NULL,
2791                                  &i1dest, &i1src))
2792       || (i0 && ! can_combine_p (i0, i3, NULL, NULL, i1, i2,
2793                                  &i0dest, &i0src)))
2794     {
2795       undo_all ();
2796       return 0;
2797     }
2798
2799   /* Record whether I2DEST is used in I2SRC and similarly for the other
2800      cases.  Knowing this will help in register status updating below.  */
2801   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2802   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2803   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2804   i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2805   i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2806   i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2807   i2dest_killed = dead_or_set_p (i2, i2dest);
2808   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2809   i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2810
2811   /* For the earlier insns, determine which of the subsequent ones they
2812      feed.  */
2813   i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2814   i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2815   i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2816                           : (!reg_overlap_mentioned_p (i1dest, i0dest)
2817                              && reg_overlap_mentioned_p (i0dest, i2src))));
2818
2819   /* Ensure that I3's pattern can be the destination of combines.  */
2820   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2821                           i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2822                           i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2823                                  || (i1dest_in_i0src && !i0_feeds_i1_n)),
2824                           &i3dest_killed))
2825     {
2826       undo_all ();
2827       return 0;
2828     }
2829
2830   /* See if any of the insns is a MULT operation.  Unless one is, we will
2831      reject a combination that is, since it must be slower.  Be conservative
2832      here.  */
2833   if (GET_CODE (i2src) == MULT
2834       || (i1 != 0 && GET_CODE (i1src) == MULT)
2835       || (i0 != 0 && GET_CODE (i0src) == MULT)
2836       || (GET_CODE (PATTERN (i3)) == SET
2837           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2838     have_mult = 1;
2839
2840   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2841      We used to do this EXCEPT in one case: I3 has a post-inc in an
2842      output operand.  However, that exception can give rise to insns like
2843         mov r3,(r3)+
2844      which is a famous insn on the PDP-11 where the value of r3 used as the
2845      source was model-dependent.  Avoid this sort of thing.  */
2846
2847 #if 0
2848   if (!(GET_CODE (PATTERN (i3)) == SET
2849         && REG_P (SET_SRC (PATTERN (i3)))
2850         && MEM_P (SET_DEST (PATTERN (i3)))
2851         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2852             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2853     /* It's not the exception.  */
2854 #endif
2855 #ifdef AUTO_INC_DEC
2856     {
2857       rtx link;
2858       for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2859         if (REG_NOTE_KIND (link) == REG_INC
2860             && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2861                 || (i1 != 0
2862                     && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2863           {
2864             undo_all ();
2865             return 0;
2866           }
2867     }
2868 #endif
2869
2870   /* See if the SETs in I1 or I2 need to be kept around in the merged
2871      instruction: whenever the value set there is still needed past I3.
2872      For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
2873
2874      For the SET in I1, we have two cases: if I1 and I2 independently feed
2875      into I3, the set in I1 needs to be kept around unless I1DEST dies
2876      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2877      in I1 needs to be kept around unless I1DEST dies or is set in either
2878      I2 or I3.  The same considerations apply to I0.  */
2879
2880   added_sets_2 = !dead_or_set_p (i3, i2dest);
2881
2882   if (i1)
2883     added_sets_1 = !(dead_or_set_p (i3, i1dest)
2884                      || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
2885   else
2886     added_sets_1 = 0;
2887
2888   if (i0)
2889     added_sets_0 =  !(dead_or_set_p (i3, i0dest)
2890                       || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest))
2891                       || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
2892                           && dead_or_set_p (i2, i0dest)));
2893   else
2894     added_sets_0 = 0;
2895
2896   /* We are about to copy insns for the case where they need to be kept
2897      around.  Check that they can be copied in the merged instruction.  */
2898
2899   if (targetm.cannot_copy_insn_p
2900       && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
2901           || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
2902           || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
2903     {
2904       undo_all ();
2905       return 0;
2906     }
2907
2908   /* If the set in I2 needs to be kept around, we must make a copy of
2909      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2910      PATTERN (I2), we are only substituting for the original I1DEST, not into
2911      an already-substituted copy.  This also prevents making self-referential
2912      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2913      I2DEST.  */
2914
2915   if (added_sets_2)
2916     {
2917       if (GET_CODE (PATTERN (i2)) == PARALLEL)
2918         i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
2919       else
2920         i2pat = copy_rtx (PATTERN (i2));
2921     }
2922
2923   if (added_sets_1)
2924     {
2925       if (GET_CODE (PATTERN (i1)) == PARALLEL)
2926         i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
2927       else
2928         i1pat = copy_rtx (PATTERN (i1));
2929     }
2930
2931   if (added_sets_0)
2932     {
2933       if (GET_CODE (PATTERN (i0)) == PARALLEL)
2934         i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
2935       else
2936         i0pat = copy_rtx (PATTERN (i0));
2937     }
2938
2939   combine_merges++;
2940
2941   /* Substitute in the latest insn for the regs set by the earlier ones.  */
2942
2943   maxreg = max_reg_num ();
2944
2945   subst_insn = i3;
2946
2947 #ifndef HAVE_cc0
2948   /* Many machines that don't use CC0 have insns that can both perform an
2949      arithmetic operation and set the condition code.  These operations will
2950      be represented as a PARALLEL with the first element of the vector
2951      being a COMPARE of an arithmetic operation with the constant zero.
2952      The second element of the vector will set some pseudo to the result
2953      of the same arithmetic operation.  If we simplify the COMPARE, we won't
2954      match such a pattern and so will generate an extra insn.   Here we test
2955      for this case, where both the comparison and the operation result are
2956      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2957      I2SRC.  Later we will make the PARALLEL that contains I2.  */
2958
2959   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2960       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2961       && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
2962       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2963     {
2964       rtx newpat_dest;
2965       rtx *cc_use_loc = NULL;
2966       rtx_insn *cc_use_insn = NULL;
2967       rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
2968       machine_mode compare_mode, orig_compare_mode;
2969       enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
2970
2971       newpat = PATTERN (i3);
2972       newpat_dest = SET_DEST (newpat);
2973       compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
2974
2975       if (undobuf.other_insn == 0
2976           && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
2977                                             &cc_use_insn)))
2978         {
2979           compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
2980           compare_code = simplify_compare_const (compare_code,
2981                                                  GET_MODE (i2dest), op0, &op1);
2982           target_canonicalize_comparison (&compare_code, &op0, &op1, 1);
2983         }
2984
2985       /* Do the rest only if op1 is const0_rtx, which may be the
2986          result of simplification.  */
2987       if (op1 == const0_rtx)
2988         {
2989           /* If a single use of the CC is found, prepare to modify it
2990              when SELECT_CC_MODE returns a new CC-class mode, or when
2991              the above simplify_compare_const() returned a new comparison
2992              operator.  undobuf.other_insn is assigned the CC use insn
2993              when modifying it.  */
2994           if (cc_use_loc)
2995             {
2996 #ifdef SELECT_CC_MODE
2997               machine_mode new_mode
2998                 = SELECT_CC_MODE (compare_code, op0, op1);
2999               if (new_mode != orig_compare_mode
3000                   && can_change_dest_mode (SET_DEST (newpat),
3001                                            added_sets_2, new_mode))
3002                 {
3003                   unsigned int regno = REGNO (newpat_dest);
3004                   compare_mode = new_mode;
3005                   if (regno < FIRST_PSEUDO_REGISTER)
3006                     newpat_dest = gen_rtx_REG (compare_mode, regno);
3007                   else
3008                     {
3009                       SUBST_MODE (regno_reg_rtx[regno], compare_mode);
3010                       newpat_dest = regno_reg_rtx[regno];
3011                     }
3012                 }
3013 #endif
3014               /* Cases for modifying the CC-using comparison.  */
3015               if (compare_code != orig_compare_code
3016                   /* ??? Do we need to verify the zero rtx?  */
3017                   && XEXP (*cc_use_loc, 1) == const0_rtx)
3018                 {
3019                   /* Replace cc_use_loc with entire new RTX.  */
3020                   SUBST (*cc_use_loc,
3021                          gen_rtx_fmt_ee (compare_code, compare_mode,
3022                                          newpat_dest, const0_rtx));
3023                   undobuf.other_insn = cc_use_insn;
3024                 }
3025               else if (compare_mode != orig_compare_mode)
3026                 {
3027                   /* Just replace the CC reg with a new mode.  */
3028                   SUBST (XEXP (*cc_use_loc, 0), newpat_dest);
3029                   undobuf.other_insn = cc_use_insn;
3030                 }
3031             }
3032
3033           /* Now we modify the current newpat:
3034              First, SET_DEST(newpat) is updated if the CC mode has been
3035              altered. For targets without SELECT_CC_MODE, this should be
3036              optimized away.  */
3037           if (compare_mode != orig_compare_mode)
3038             SUBST (SET_DEST (newpat), newpat_dest);
3039           /* This is always done to propagate i2src into newpat.  */
3040           SUBST (SET_SRC (newpat),
3041                  gen_rtx_COMPARE (compare_mode, op0, op1));
3042           /* Create new version of i2pat if needed; the below PARALLEL
3043              creation needs this to work correctly.  */
3044           if (! rtx_equal_p (i2src, op0))
3045             i2pat = gen_rtx_SET (VOIDmode, i2dest, op0);
3046           i2_is_used = 1;
3047         }
3048     }
3049 #endif
3050
3051   if (i2_is_used == 0)
3052     {
3053       /* It is possible that the source of I2 or I1 may be performing
3054          an unneeded operation, such as a ZERO_EXTEND of something
3055          that is known to have the high part zero.  Handle that case
3056          by letting subst look at the inner insns.
3057
3058          Another way to do this would be to have a function that tries
3059          to simplify a single insn instead of merging two or more
3060          insns.  We don't do this because of the potential of infinite
3061          loops and because of the potential extra memory required.
3062          However, doing it the way we are is a bit of a kludge and
3063          doesn't catch all cases.
3064
3065          But only do this if -fexpensive-optimizations since it slows
3066          things down and doesn't usually win.
3067
3068          This is not done in the COMPARE case above because the
3069          unmodified I2PAT is used in the PARALLEL and so a pattern
3070          with a modified I2SRC would not match.  */
3071
3072       if (flag_expensive_optimizations)
3073         {
3074           /* Pass pc_rtx so no substitutions are done, just
3075              simplifications.  */
3076           if (i1)
3077             {
3078               subst_low_luid = DF_INSN_LUID (i1);
3079               i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
3080             }
3081
3082           subst_low_luid = DF_INSN_LUID (i2);
3083           i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
3084         }
3085
3086       n_occurrences = 0;                /* `subst' counts here */
3087       subst_low_luid = DF_INSN_LUID (i2);
3088
3089       /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3090          copy of I2SRC each time we substitute it, in order to avoid creating
3091          self-referential RTL when we will be substituting I1SRC for I1DEST
3092          later.  Likewise if I0 feeds into I2, either directly or indirectly
3093          through I1, and I0DEST is in I0SRC.  */
3094       newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
3095                       (i1_feeds_i2_n && i1dest_in_i1src)
3096                       || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3097                           && i0dest_in_i0src));
3098       substed_i2 = 1;
3099
3100       /* Record whether I2's body now appears within I3's body.  */
3101       i2_is_used = n_occurrences;
3102     }
3103
3104   /* If we already got a failure, don't try to do more.  Otherwise, try to
3105      substitute I1 if we have it.  */
3106
3107   if (i1 && GET_CODE (newpat) != CLOBBER)
3108     {
3109       /* Check that an autoincrement side-effect on I1 has not been lost.
3110          This happens if I1DEST is mentioned in I2 and dies there, and
3111          has disappeared from the new pattern.  */
3112       if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3113            && i1_feeds_i2_n
3114            && dead_or_set_p (i2, i1dest)
3115            && !reg_overlap_mentioned_p (i1dest, newpat))
3116            /* Before we can do this substitution, we must redo the test done
3117               above (see detailed comments there) that ensures I1DEST isn't
3118               mentioned in any SETs in NEWPAT that are field assignments.  */
3119           || !combinable_i3pat (NULL, &newpat, i1dest, NULL_RTX, NULL_RTX,
3120                                 0, 0, 0))
3121         {
3122           undo_all ();
3123           return 0;
3124         }
3125
3126       n_occurrences = 0;
3127       subst_low_luid = DF_INSN_LUID (i1);
3128
3129       /* If the following substitution will modify I1SRC, make a copy of it
3130          for the case where it is substituted for I1DEST in I2PAT later.  */
3131       if (added_sets_2 && i1_feeds_i2_n)
3132         i1src_copy = copy_rtx (i1src);
3133
3134       /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3135          copy of I1SRC each time we substitute it, in order to avoid creating
3136          self-referential RTL when we will be substituting I0SRC for I0DEST
3137          later.  */
3138       newpat = subst (newpat, i1dest, i1src, 0, 0,
3139                       i0_feeds_i1_n && i0dest_in_i0src);
3140       substed_i1 = 1;
3141
3142       /* Record whether I1's body now appears within I3's body.  */
3143       i1_is_used = n_occurrences;
3144     }
3145
3146   /* Likewise for I0 if we have it.  */
3147
3148   if (i0 && GET_CODE (newpat) != CLOBBER)
3149     {
3150       if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3151            && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3152                || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3153            && !reg_overlap_mentioned_p (i0dest, newpat))
3154           || !combinable_i3pat (NULL, &newpat, i0dest, NULL_RTX, NULL_RTX,
3155                                 0, 0, 0))
3156         {
3157           undo_all ();
3158           return 0;
3159         }
3160
3161       /* If the following substitution will modify I0SRC, make a copy of it
3162          for the case where it is substituted for I0DEST in I1PAT later.  */
3163       if (added_sets_1 && i0_feeds_i1_n)
3164         i0src_copy = copy_rtx (i0src);
3165       /* And a copy for I0DEST in I2PAT substitution.  */
3166       if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3167                            || (i0_feeds_i2_n)))
3168         i0src_copy2 = copy_rtx (i0src);
3169
3170       n_occurrences = 0;
3171       subst_low_luid = DF_INSN_LUID (i0);
3172       newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
3173       substed_i0 = 1;
3174     }
3175
3176   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
3177      to count all the ways that I2SRC and I1SRC can be used.  */
3178   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3179        && i2_is_used + added_sets_2 > 1)
3180       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3181           && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3182               > 1))
3183       || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3184           && (n_occurrences + added_sets_0
3185               + (added_sets_1 && i0_feeds_i1_n)
3186               + (added_sets_2 && i0_feeds_i2_n)
3187               > 1))
3188       /* Fail if we tried to make a new register.  */
3189       || max_reg_num () != maxreg
3190       /* Fail if we couldn't do something and have a CLOBBER.  */
3191       || GET_CODE (newpat) == CLOBBER
3192       /* Fail if this new pattern is a MULT and we didn't have one before
3193          at the outer level.  */
3194       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3195           && ! have_mult))
3196     {
3197       undo_all ();
3198       return 0;
3199     }
3200
3201   /* If the actions of the earlier insns must be kept
3202      in addition to substituting them into the latest one,
3203      we must make a new PARALLEL for the latest insn
3204      to hold additional the SETs.  */
3205
3206   if (added_sets_0 || added_sets_1 || added_sets_2)
3207     {
3208       int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3209       combine_extras++;
3210
3211       if (GET_CODE (newpat) == PARALLEL)
3212         {
3213           rtvec old = XVEC (newpat, 0);
3214           total_sets = XVECLEN (newpat, 0) + extra_sets;
3215           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3216           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3217                   sizeof (old->elem[0]) * old->num_elem);
3218         }
3219       else
3220         {
3221           rtx old = newpat;
3222           total_sets = 1 + extra_sets;
3223           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3224           XVECEXP (newpat, 0, 0) = old;
3225         }
3226
3227       if (added_sets_0)
3228         XVECEXP (newpat, 0, --total_sets) = i0pat;
3229
3230       if (added_sets_1)
3231         {
3232           rtx t = i1pat;
3233           if (i0_feeds_i1_n)
3234             t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src, 0, 0, 0);
3235
3236           XVECEXP (newpat, 0, --total_sets) = t;
3237         }
3238       if (added_sets_2)
3239         {
3240           rtx t = i2pat;
3241           if (i1_feeds_i2_n)
3242             t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
3243                        i0_feeds_i1_n && i0dest_in_i0src);
3244           if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3245             t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src, 0, 0, 0);
3246
3247           XVECEXP (newpat, 0, --total_sets) = t;
3248         }
3249     }
3250
3251  validate_replacement:
3252
3253   /* Note which hard regs this insn has as inputs.  */
3254   mark_used_regs_combine (newpat);
3255
3256   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
3257      consider splitting this pattern, we might need these clobbers.  */
3258   if (i1 && GET_CODE (newpat) == PARALLEL
3259       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3260     {
3261       int len = XVECLEN (newpat, 0);
3262
3263       newpat_vec_with_clobbers = rtvec_alloc (len);
3264       for (i = 0; i < len; i++)
3265         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3266     }
3267
3268   /* We have recognized nothing yet.  */
3269   insn_code_number = -1;
3270
3271   /* See if this is a PARALLEL of two SETs where one SET's destination is
3272      a register that is unused and this isn't marked as an instruction that
3273      might trap in an EH region.  In that case, we just need the other SET.
3274      We prefer this over the PARALLEL.
3275
3276      This can occur when simplifying a divmod insn.  We *must* test for this
3277      case here because the code below that splits two independent SETs doesn't
3278      handle this case correctly when it updates the register status.
3279
3280      It's pointless doing this if we originally had two sets, one from
3281      i3, and one from i2.  Combining then splitting the parallel results
3282      in the original i2 again plus an invalid insn (which we delete).
3283      The net effect is only to move instructions around, which makes
3284      debug info less accurate.  */
3285
3286   if (!(added_sets_2 && i1 == 0)
3287       && GET_CODE (newpat) == PARALLEL
3288       && XVECLEN (newpat, 0) == 2
3289       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3290       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3291       && asm_noperands (newpat) < 0)
3292     {
3293       rtx set0 = XVECEXP (newpat, 0, 0);
3294       rtx set1 = XVECEXP (newpat, 0, 1);
3295       rtx oldpat = newpat;
3296
3297       if (((REG_P (SET_DEST (set1))
3298             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3299            || (GET_CODE (SET_DEST (set1)) == SUBREG
3300                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3301           && insn_nothrow_p (i3)
3302           && !side_effects_p (SET_SRC (set1)))
3303         {
3304           newpat = set0;
3305           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3306         }
3307
3308       else if (((REG_P (SET_DEST (set0))
3309                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3310                 || (GET_CODE (SET_DEST (set0)) == SUBREG
3311                     && find_reg_note (i3, REG_UNUSED,
3312                                       SUBREG_REG (SET_DEST (set0)))))
3313                && insn_nothrow_p (i3)
3314                && !side_effects_p (SET_SRC (set0)))
3315         {
3316           newpat = set1;
3317           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3318
3319           if (insn_code_number >= 0)
3320             changed_i3_dest = 1;
3321         }
3322
3323       if (insn_code_number < 0)
3324         newpat = oldpat;
3325     }
3326
3327   /* Is the result of combination a valid instruction?  */
3328   if (insn_code_number < 0)
3329     insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3330
3331   /* If we were combining three insns and the result is a simple SET
3332      with no ASM_OPERANDS that wasn't recognized, try to split it into two
3333      insns.  There are two ways to do this.  It can be split using a
3334      machine-specific method (like when you have an addition of a large
3335      constant) or by combine in the function find_split_point.  */
3336
3337   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3338       && asm_noperands (newpat) < 0)
3339     {
3340       rtx parallel, *split;
3341       rtx_insn *m_split_insn;
3342
3343       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
3344          use I2DEST as a scratch register will help.  In the latter case,
3345          convert I2DEST to the mode of the source of NEWPAT if we can.  */
3346
3347       m_split_insn = combine_split_insns (newpat, i3);
3348
3349       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3350          inputs of NEWPAT.  */
3351
3352       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3353          possible to try that as a scratch reg.  This would require adding
3354          more code to make it work though.  */
3355
3356       if (m_split_insn == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3357         {
3358           machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3359
3360           /* First try to split using the original register as a
3361              scratch register.  */
3362           parallel = gen_rtx_PARALLEL (VOIDmode,
3363                                        gen_rtvec (2, newpat,
3364                                                   gen_rtx_CLOBBER (VOIDmode,
3365                                                                    i2dest)));
3366           m_split_insn = combine_split_insns (parallel, i3);
3367
3368           /* If that didn't work, try changing the mode of I2DEST if
3369              we can.  */
3370           if (m_split_insn == 0
3371               && new_mode != GET_MODE (i2dest)
3372               && new_mode != VOIDmode
3373               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3374             {
3375               machine_mode old_mode = GET_MODE (i2dest);
3376               rtx ni2dest;
3377
3378               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3379                 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3380               else
3381                 {
3382                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3383                   ni2dest = regno_reg_rtx[REGNO (i2dest)];
3384                 }
3385
3386               parallel = (gen_rtx_PARALLEL
3387                           (VOIDmode,
3388                            gen_rtvec (2, newpat,
3389                                       gen_rtx_CLOBBER (VOIDmode,
3390                                                        ni2dest))));
3391               m_split_insn = combine_split_insns (parallel, i3);
3392
3393               if (m_split_insn == 0
3394                   && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3395                 {
3396                   struct undo *buf;
3397
3398                   adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3399                   buf = undobuf.undos;
3400                   undobuf.undos = buf->next;
3401                   buf->next = undobuf.frees;
3402                   undobuf.frees = buf;
3403                 }
3404             }
3405
3406           i2scratch = m_split_insn != 0;
3407         }
3408
3409       /* If recog_for_combine has discarded clobbers, try to use them
3410          again for the split.  */
3411       if (m_split_insn == 0 && newpat_vec_with_clobbers)
3412         {
3413           parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3414           m_split_insn = combine_split_insns (parallel, i3);
3415         }
3416
3417       if (m_split_insn && NEXT_INSN (m_split_insn) == NULL_RTX)
3418         {
3419           rtx m_split_pat = PATTERN (m_split_insn);
3420           insn_code_number = recog_for_combine (&m_split_pat, i3, &new_i3_notes);
3421           if (insn_code_number >= 0)
3422             newpat = m_split_pat;
3423         }
3424       else if (m_split_insn && NEXT_INSN (NEXT_INSN (m_split_insn)) == NULL_RTX
3425                && (next_nonnote_nondebug_insn (i2) == i3
3426                    || ! use_crosses_set_p (PATTERN (m_split_insn), DF_INSN_LUID (i2))))
3427         {
3428           rtx i2set, i3set;
3429           rtx newi3pat = PATTERN (NEXT_INSN (m_split_insn));
3430           newi2pat = PATTERN (m_split_insn);
3431
3432           i3set = single_set (NEXT_INSN (m_split_insn));
3433           i2set = single_set (m_split_insn);
3434
3435           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3436
3437           /* If I2 or I3 has multiple SETs, we won't know how to track
3438              register status, so don't use these insns.  If I2's destination
3439              is used between I2 and I3, we also can't use these insns.  */
3440
3441           if (i2_code_number >= 0 && i2set && i3set
3442               && (next_nonnote_nondebug_insn (i2) == i3
3443                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3444             insn_code_number = recog_for_combine (&newi3pat, i3,
3445                                                   &new_i3_notes);
3446           if (insn_code_number >= 0)
3447             newpat = newi3pat;
3448
3449           /* It is possible that both insns now set the destination of I3.
3450              If so, we must show an extra use of it.  */
3451
3452           if (insn_code_number >= 0)
3453             {
3454               rtx new_i3_dest = SET_DEST (i3set);
3455               rtx new_i2_dest = SET_DEST (i2set);
3456
3457               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3458                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3459                      || GET_CODE (new_i3_dest) == SUBREG)
3460                 new_i3_dest = XEXP (new_i3_dest, 0);
3461
3462               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3463                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3464                      || GET_CODE (new_i2_dest) == SUBREG)
3465                 new_i2_dest = XEXP (new_i2_dest, 0);
3466
3467               if (REG_P (new_i3_dest)
3468                   && REG_P (new_i2_dest)
3469                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3470                 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3471             }
3472         }
3473
3474       /* If we can split it and use I2DEST, go ahead and see if that
3475          helps things be recognized.  Verify that none of the registers
3476          are set between I2 and I3.  */
3477       if (insn_code_number < 0
3478           && (split = find_split_point (&newpat, i3, false)) != 0
3479 #ifdef HAVE_cc0
3480           && REG_P (i2dest)
3481 #endif
3482           /* We need I2DEST in the proper mode.  If it is a hard register
3483              or the only use of a pseudo, we can change its mode.
3484              Make sure we don't change a hard register to have a mode that
3485              isn't valid for it, or change the number of registers.  */
3486           && (GET_MODE (*split) == GET_MODE (i2dest)
3487               || GET_MODE (*split) == VOIDmode
3488               || can_change_dest_mode (i2dest, added_sets_2,
3489                                        GET_MODE (*split)))
3490           && (next_nonnote_nondebug_insn (i2) == i3
3491               || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3492           /* We can't overwrite I2DEST if its value is still used by
3493              NEWPAT.  */
3494           && ! reg_referenced_p (i2dest, newpat))
3495         {
3496           rtx newdest = i2dest;
3497           enum rtx_code split_code = GET_CODE (*split);
3498           machine_mode split_mode = GET_MODE (*split);
3499           bool subst_done = false;
3500           newi2pat = NULL_RTX;
3501
3502           i2scratch = true;
3503
3504           /* *SPLIT may be part of I2SRC, so make sure we have the
3505              original expression around for later debug processing.
3506              We should not need I2SRC any more in other cases.  */
3507           if (MAY_HAVE_DEBUG_INSNS)
3508             i2src = copy_rtx (i2src);
3509           else
3510             i2src = NULL;
3511
3512           /* Get NEWDEST as a register in the proper mode.  We have already
3513              validated that we can do this.  */
3514           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3515             {
3516               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3517                 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3518               else
3519                 {
3520                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3521                   newdest = regno_reg_rtx[REGNO (i2dest)];
3522                 }
3523             }
3524
3525           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3526              an ASHIFT.  This can occur if it was inside a PLUS and hence
3527              appeared to be a memory address.  This is a kludge.  */
3528           if (split_code == MULT
3529               && CONST_INT_P (XEXP (*split, 1))
3530               && INTVAL (XEXP (*split, 1)) > 0
3531               && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3532             {
3533               SUBST (*split, gen_rtx_ASHIFT (split_mode,
3534                                              XEXP (*split, 0), GEN_INT (i)));
3535               /* Update split_code because we may not have a multiply
3536                  anymore.  */
3537               split_code = GET_CODE (*split);
3538             }
3539
3540 #ifdef INSN_SCHEDULING
3541           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3542              be written as a ZERO_EXTEND.  */
3543           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3544             {
3545 #ifdef LOAD_EXTEND_OP
3546               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3547                  what it really is.  */
3548               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3549                   == SIGN_EXTEND)
3550                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3551                                                     SUBREG_REG (*split)));
3552               else
3553 #endif
3554                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3555                                                     SUBREG_REG (*split)));
3556             }
3557 #endif
3558
3559           /* Attempt to split binary operators using arithmetic identities.  */
3560           if (BINARY_P (SET_SRC (newpat))
3561               && split_mode == GET_MODE (SET_SRC (newpat))
3562               && ! side_effects_p (SET_SRC (newpat)))
3563             {
3564               rtx setsrc = SET_SRC (newpat);
3565               machine_mode mode = GET_MODE (setsrc);
3566               enum rtx_code code = GET_CODE (setsrc);
3567               rtx src_op0 = XEXP (setsrc, 0);
3568               rtx src_op1 = XEXP (setsrc, 1);
3569
3570               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
3571               if (rtx_equal_p (src_op0, src_op1))
3572                 {
3573                   newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3574                   SUBST (XEXP (setsrc, 0), newdest);
3575                   SUBST (XEXP (setsrc, 1), newdest);
3576                   subst_done = true;
3577                 }
3578               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
3579               else if ((code == PLUS || code == MULT)
3580                        && GET_CODE (src_op0) == code
3581                        && GET_CODE (XEXP (src_op0, 0)) == code
3582                        && (INTEGRAL_MODE_P (mode)
3583                            || (FLOAT_MODE_P (mode)
3584                                && flag_unsafe_math_optimizations)))
3585                 {
3586                   rtx p = XEXP (XEXP (src_op0, 0), 0);
3587                   rtx q = XEXP (XEXP (src_op0, 0), 1);
3588                   rtx r = XEXP (src_op0, 1);
3589                   rtx s = src_op1;
3590
3591                   /* Split both "((X op Y) op X) op Y" and
3592                      "((X op Y) op Y) op X" as "T op T" where T is
3593                      "X op Y".  */
3594                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3595                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3596                     {
3597                       newi2pat = gen_rtx_SET (VOIDmode, newdest,
3598                                               XEXP (src_op0, 0));
3599                       SUBST (XEXP (setsrc, 0), newdest);
3600                       SUBST (XEXP (setsrc, 1), newdest);
3601                       subst_done = true;
3602                     }
3603                   /* Split "((X op X) op Y) op Y)" as "T op T" where
3604                      T is "X op Y".  */
3605                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3606                     {
3607                       rtx tmp = simplify_gen_binary (code, mode, p, r);
3608                       newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3609                       SUBST (XEXP (setsrc, 0), newdest);
3610                       SUBST (XEXP (setsrc, 1), newdest);
3611                       subst_done = true;
3612                     }
3613                 }
3614             }
3615
3616           if (!subst_done)
3617             {
3618               newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3619               SUBST (*split, newdest);
3620             }
3621
3622           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3623
3624           /* recog_for_combine might have added CLOBBERs to newi2pat.
3625              Make sure NEWPAT does not depend on the clobbered regs.  */
3626           if (GET_CODE (newi2pat) == PARALLEL)
3627             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3628               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3629                 {
3630                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3631                   if (reg_overlap_mentioned_p (reg, newpat))
3632                     {
3633                       undo_all ();
3634                       return 0;
3635                     }
3636                 }
3637
3638           /* If the split point was a MULT and we didn't have one before,
3639              don't use one now.  */
3640           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3641             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3642         }
3643     }
3644
3645   /* Check for a case where we loaded from memory in a narrow mode and
3646      then sign extended it, but we need both registers.  In that case,
3647      we have a PARALLEL with both loads from the same memory location.
3648      We can split this into a load from memory followed by a register-register
3649      copy.  This saves at least one insn, more if register allocation can
3650      eliminate the copy.
3651
3652      We cannot do this if the destination of the first assignment is a
3653      condition code register or cc0.  We eliminate this case by making sure
3654      the SET_DEST and SET_SRC have the same mode.
3655
3656      We cannot do this if the destination of the second assignment is
3657      a register that we have already assumed is zero-extended.  Similarly
3658      for a SUBREG of such a register.  */
3659
3660   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3661            && GET_CODE (newpat) == PARALLEL
3662            && XVECLEN (newpat, 0) == 2
3663            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3664            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3665            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3666                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3667            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3668            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3669                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3670            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3671                                    DF_INSN_LUID (i2))
3672            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3673            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3674            && ! (temp_expr = SET_DEST (XVECEXP (newpat, 0, 1)),
3675                  (REG_P (temp_expr)
3676                   && reg_stat[REGNO (temp_expr)].nonzero_bits != 0
3677                   && GET_MODE_PRECISION (GET_MODE (temp_expr)) < BITS_PER_WORD
3678                   && GET_MODE_PRECISION (GET_MODE (temp_expr)) < HOST_BITS_PER_INT
3679                   && (reg_stat[REGNO (temp_expr)].nonzero_bits
3680                       != GET_MODE_MASK (word_mode))))
3681            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3682                  && (temp_expr = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3683                      (REG_P (temp_expr)
3684                       && reg_stat[REGNO (temp_expr)].nonzero_bits != 0
3685                       && GET_MODE_PRECISION (GET_MODE (temp_expr)) < BITS_PER_WORD
3686                       && GET_MODE_PRECISION (GET_MODE (temp_expr)) < HOST_BITS_PER_INT
3687                       && (reg_stat[REGNO (temp_expr)].nonzero_bits
3688                           != GET_MODE_MASK (word_mode)))))
3689            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3690                                          SET_SRC (XVECEXP (newpat, 0, 1)))
3691            && ! find_reg_note (i3, REG_UNUSED,
3692                                SET_DEST (XVECEXP (newpat, 0, 0))))
3693     {
3694       rtx ni2dest;
3695
3696       newi2pat = XVECEXP (newpat, 0, 0);
3697       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3698       newpat = XVECEXP (newpat, 0, 1);
3699       SUBST (SET_SRC (newpat),
3700              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3701       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3702
3703       if (i2_code_number >= 0)
3704         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3705
3706       if (insn_code_number >= 0)
3707         swap_i2i3 = 1;
3708     }
3709
3710   /* Similarly, check for a case where we have a PARALLEL of two independent
3711      SETs but we started with three insns.  In this case, we can do the sets
3712      as two separate insns.  This case occurs when some SET allows two
3713      other insns to combine, but the destination of that SET is still live.  */
3714
3715   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3716            && GET_CODE (newpat) == PARALLEL
3717            && XVECLEN (newpat, 0) == 2
3718            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3719            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3720            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3721            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3722            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3723            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3724            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3725                                   XVECEXP (newpat, 0, 0))
3726            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3727                                   XVECEXP (newpat, 0, 1))
3728            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3729                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3730     {
3731       rtx set0 = XVECEXP (newpat, 0, 0);
3732       rtx set1 = XVECEXP (newpat, 0, 1);
3733
3734       /* Normally, it doesn't matter which of the two is done first,
3735          but the one that references cc0 can't be the second, and
3736          one which uses any regs/memory set in between i2 and i3 can't
3737          be first.  The PARALLEL might also have been pre-existing in i3,
3738          so we need to make sure that we won't wrongly hoist a SET to i2
3739          that would conflict with a death note present in there.  */
3740       if (!use_crosses_set_p (SET_SRC (set1), DF_INSN_LUID (i2))
3741           && !(REG_P (SET_DEST (set1))
3742                && find_reg_note (i2, REG_DEAD, SET_DEST (set1)))
3743           && !(GET_CODE (SET_DEST (set1)) == SUBREG
3744                && find_reg_note (i2, REG_DEAD,
3745                                  SUBREG_REG (SET_DEST (set1))))
3746 #ifdef HAVE_cc0
3747           && !reg_referenced_p (cc0_rtx, set0)
3748 #endif
3749           /* If I3 is a jump, ensure that set0 is a jump so that
3750              we do not create invalid RTL.  */
3751           && (!JUMP_P (i3) || SET_DEST (set0) == pc_rtx)
3752          )
3753         {
3754           newi2pat = set1;
3755           newpat = set0;
3756         }
3757       else if (!use_crosses_set_p (SET_SRC (set0), DF_INSN_LUID (i2))
3758                && !(REG_P (SET_DEST (set0))
3759                     && find_reg_note (i2, REG_DEAD, SET_DEST (set0)))
3760                && !(GET_CODE (SET_DEST (set0)) == SUBREG
3761                     && find_reg_note (i2, REG_DEAD,
3762                                       SUBREG_REG (SET_DEST (set0))))
3763 #ifdef HAVE_cc0
3764                && !reg_referenced_p (cc0_rtx, set1)
3765 #endif
3766                /* If I3 is a jump, ensure that set1 is a jump so that
3767                   we do not create invalid RTL.  */
3768                && (!JUMP_P (i3) || SET_DEST (set1) == pc_rtx)
3769               )
3770         {
3771           newi2pat = set0;
3772           newpat = set1;
3773         }
3774       else
3775         {
3776           undo_all ();
3777           return 0;
3778         }
3779
3780       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3781
3782       if (i2_code_number >= 0)
3783         {
3784           /* recog_for_combine might have added CLOBBERs to newi2pat.
3785              Make sure NEWPAT does not depend on the clobbered regs.  */
3786           if (GET_CODE (newi2pat) == PARALLEL)
3787             {
3788               for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3789                 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3790                   {
3791                     rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3792                     if (reg_overlap_mentioned_p (reg, newpat))
3793                       {
3794                         undo_all ();
3795                         return 0;
3796                       }
3797                   }
3798             }
3799
3800           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3801         }
3802     }
3803
3804   /* If it still isn't recognized, fail and change things back the way they
3805      were.  */
3806   if ((insn_code_number < 0
3807        /* Is the result a reasonable ASM_OPERANDS?  */
3808        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3809     {
3810       undo_all ();
3811       return 0;
3812     }
3813
3814   /* If we had to change another insn, make sure it is valid also.  */
3815   if (undobuf.other_insn)
3816     {
3817       CLEAR_HARD_REG_SET (newpat_used_regs);
3818
3819       other_pat = PATTERN (undobuf.other_insn);
3820       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3821                                              &new_other_notes);
3822
3823       if (other_code_number < 0 && ! check_asm_operands (other_pat))
3824         {
3825           undo_all ();
3826           return 0;
3827         }
3828     }
3829
3830 #ifdef HAVE_cc0
3831   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3832      they are adjacent to each other or not.  */
3833   {
3834     rtx_insn *p = prev_nonnote_insn (i3);
3835     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3836         && sets_cc0_p (newi2pat))
3837       {
3838         undo_all ();
3839         return 0;
3840       }
3841   }
3842 #endif
3843
3844   /* Only allow this combination if insn_rtx_costs reports that the
3845      replacement instructions are cheaper than the originals.  */
3846   if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3847     {
3848       undo_all ();
3849       return 0;
3850     }
3851
3852   if (MAY_HAVE_DEBUG_INSNS)
3853     {
3854       struct undo *undo;
3855
3856       for (undo = undobuf.undos; undo; undo = undo->next)
3857         if (undo->kind == UNDO_MODE)
3858           {
3859             rtx reg = *undo->where.r;
3860             machine_mode new_mode = GET_MODE (reg);
3861             machine_mode old_mode = undo->old_contents.m;
3862
3863             /* Temporarily revert mode back.  */
3864             adjust_reg_mode (reg, old_mode);
3865
3866             if (reg == i2dest && i2scratch)
3867               {
3868                 /* If we used i2dest as a scratch register with a
3869                    different mode, substitute it for the original
3870                    i2src while its original mode is temporarily
3871                    restored, and then clear i2scratch so that we don't
3872                    do it again later.  */
3873                 propagate_for_debug (i2, last_combined_insn, reg, i2src,
3874                                      this_basic_block);
3875                 i2scratch = false;
3876                 /* Put back the new mode.  */
3877                 adjust_reg_mode (reg, new_mode);
3878               }
3879             else
3880               {
3881                 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3882                 rtx_insn *first, *last;
3883
3884                 if (reg == i2dest)
3885                   {
3886                     first = i2;
3887                     last = last_combined_insn;
3888                   }
3889                 else
3890                   {
3891                     first = i3;
3892                     last = undobuf.other_insn;
3893                     gcc_assert (last);
3894                     if (DF_INSN_LUID (last)
3895                         < DF_INSN_LUID (last_combined_insn))
3896                       last = last_combined_insn;
3897                   }
3898
3899                 /* We're dealing with a reg that changed mode but not
3900                    meaning, so we want to turn it into a subreg for
3901                    the new mode.  However, because of REG sharing and
3902                    because its mode had already changed, we have to do
3903                    it in two steps.  First, replace any debug uses of
3904                    reg, with its original mode temporarily restored,
3905                    with this copy we have created; then, replace the
3906                    copy with the SUBREG of the original shared reg,
3907                    once again changed to the new mode.  */
3908                 propagate_for_debug (first, last, reg, tempreg,
3909                                      this_basic_block);
3910                 adjust_reg_mode (reg, new_mode);
3911                 propagate_for_debug (first, last, tempreg,
3912                                      lowpart_subreg (old_mode, reg, new_mode),
3913                                      this_basic_block);
3914               }
3915           }
3916     }
3917
3918   /* If we will be able to accept this, we have made a
3919      change to the destination of I3.  This requires us to
3920      do a few adjustments.  */
3921
3922   if (changed_i3_dest)
3923     {
3924       PATTERN (i3) = newpat;
3925       adjust_for_new_dest (i3);
3926     }
3927
3928   /* We now know that we can do this combination.  Merge the insns and
3929      update the status of registers and LOG_LINKS.  */
3930
3931   if (undobuf.other_insn)
3932     {
3933       rtx note, next;
3934
3935       PATTERN (undobuf.other_insn) = other_pat;
3936
3937       /* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
3938          ensure that they are still valid.  Then add any non-duplicate
3939          notes added by recog_for_combine.  */
3940       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
3941         {
3942           next = XEXP (note, 1);
3943
3944           if ((REG_NOTE_KIND (note) == REG_DEAD
3945                && !reg_referenced_p (XEXP (note, 0),
3946                                      PATTERN (undobuf.other_insn)))
3947               ||(REG_NOTE_KIND (note) == REG_UNUSED
3948                  && !reg_set_p (XEXP (note, 0),
3949                                 PATTERN (undobuf.other_insn))))
3950             remove_note (undobuf.other_insn, note);
3951         }
3952
3953       distribute_notes  (new_other_notes, undobuf.other_insn,
3954                         undobuf.other_insn, NULL, NULL_RTX, NULL_RTX,
3955                         NULL_RTX);
3956     }
3957
3958   if (swap_i2i3)
3959     {
3960       rtx_insn *insn;
3961       struct insn_link *link;
3962       rtx ni2dest;
3963
3964       /* I3 now uses what used to be its destination and which is now
3965          I2's destination.  This requires us to do a few adjustments.  */
3966       PATTERN (i3) = newpat;
3967       adjust_for_new_dest (i3);
3968
3969       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
3970          so we still will.
3971
3972          However, some later insn might be using I2's dest and have
3973          a LOG_LINK pointing at I3.  We must remove this link.
3974          The simplest way to remove the link is to point it at I1,
3975          which we know will be a NOTE.  */
3976
3977       /* newi2pat is usually a SET here; however, recog_for_combine might
3978          have added some clobbers.  */
3979       if (GET_CODE (newi2pat) == PARALLEL)
3980         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
3981       else
3982         ni2dest = SET_DEST (newi2pat);
3983
3984       for (insn = NEXT_INSN (i3);
3985            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
3986                     || insn != BB_HEAD (this_basic_block->next_bb));
3987            insn = NEXT_INSN (insn))
3988         {
3989           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
3990             {
3991               FOR_EACH_LOG_LINK (link, insn)
3992                 if (link->insn == i3)
3993                   link->insn = i1;
3994
3995               break;
3996             }
3997         }
3998     }
3999
4000   {
4001     rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
4002     struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
4003     rtx midnotes = 0;
4004     int from_luid;
4005     /* Compute which registers we expect to eliminate.  newi2pat may be setting
4006        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
4007        same as i3dest, in which case newi2pat may be setting i1dest.  */
4008     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
4009                    || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
4010                    || !i2dest_killed
4011                    ? 0 : i2dest);
4012     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
4013                    || (newi2pat && reg_set_p (i1dest, newi2pat))
4014                    || !i1dest_killed
4015                    ? 0 : i1dest);
4016     rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
4017                    || (newi2pat && reg_set_p (i0dest, newi2pat))
4018                    || !i0dest_killed
4019                    ? 0 : i0dest);
4020
4021     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4022        clear them.  */
4023     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
4024     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
4025     if (i1)
4026       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
4027     if (i0)
4028       i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4029
4030     /* Ensure that we do not have something that should not be shared but
4031        occurs multiple times in the new insns.  Check this by first
4032        resetting all the `used' flags and then copying anything is shared.  */
4033
4034     reset_used_flags (i3notes);
4035     reset_used_flags (i2notes);
4036     reset_used_flags (i1notes);
4037     reset_used_flags (i0notes);
4038     reset_used_flags (newpat);
4039     reset_used_flags (newi2pat);
4040     if (undobuf.other_insn)
4041       reset_used_flags (PATTERN (undobuf.other_insn));
4042
4043     i3notes = copy_rtx_if_shared (i3notes);
4044     i2notes = copy_rtx_if_shared (i2notes);
4045     i1notes = copy_rtx_if_shared (i1notes);
4046     i0notes = copy_rtx_if_shared (i0notes);
4047     newpat = copy_rtx_if_shared (newpat);
4048     newi2pat = copy_rtx_if_shared (newi2pat);
4049     if (undobuf.other_insn)
4050       reset_used_flags (PATTERN (undobuf.other_insn));
4051
4052     INSN_CODE (i3) = insn_code_number;
4053     PATTERN (i3) = newpat;
4054
4055     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4056       {
4057         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4058
4059         reset_used_flags (call_usage);
4060         call_usage = copy_rtx (call_usage);
4061
4062         if (substed_i2)
4063           {
4064             /* I2SRC must still be meaningful at this point.  Some splitting
4065                operations can invalidate I2SRC, but those operations do not
4066                apply to calls.  */
4067             gcc_assert (i2src);
4068             replace_rtx (call_usage, i2dest, i2src);
4069           }
4070
4071         if (substed_i1)
4072           replace_rtx (call_usage, i1dest, i1src);
4073         if (substed_i0)
4074           replace_rtx (call_usage, i0dest, i0src);
4075
4076         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4077       }
4078
4079     if (undobuf.other_insn)
4080       INSN_CODE (undobuf.other_insn) = other_code_number;
4081
4082     /* We had one special case above where I2 had more than one set and
4083        we replaced a destination of one of those sets with the destination
4084        of I3.  In that case, we have to update LOG_LINKS of insns later
4085        in this basic block.  Note that this (expensive) case is rare.
4086
4087        Also, in this case, we must pretend that all REG_NOTEs for I2
4088        actually came from I3, so that REG_UNUSED notes from I2 will be
4089        properly handled.  */
4090
4091     if (i3_subst_into_i2)
4092       {
4093         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4094           if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4095                || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4096               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4097               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4098               && ! find_reg_note (i2, REG_UNUSED,
4099                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4100             for (temp_insn = NEXT_INSN (i2);
4101                  temp_insn
4102                  && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
4103                           || BB_HEAD (this_basic_block) != temp_insn);
4104                  temp_insn = NEXT_INSN (temp_insn))
4105               if (temp_insn != i3 && INSN_P (temp_insn))
4106                 FOR_EACH_LOG_LINK (link, temp_insn)
4107                   if (link->insn == i2)
4108                     link->insn = i3;
4109
4110         if (i3notes)
4111           {
4112             rtx link = i3notes;
4113             while (XEXP (link, 1))
4114               link = XEXP (link, 1);
4115             XEXP (link, 1) = i2notes;
4116           }
4117         else
4118           i3notes = i2notes;
4119         i2notes = 0;
4120       }
4121
4122     LOG_LINKS (i3) = NULL;
4123     REG_NOTES (i3) = 0;
4124     LOG_LINKS (i2) = NULL;
4125     REG_NOTES (i2) = 0;
4126
4127     if (newi2pat)
4128       {
4129         if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4130           propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4131                                this_basic_block);
4132         INSN_CODE (i2) = i2_code_number;
4133         PATTERN (i2) = newi2pat;
4134       }
4135     else
4136       {
4137         if (MAY_HAVE_DEBUG_INSNS && i2src)
4138           propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4139                                this_basic_block);
4140         SET_INSN_DELETED (i2);
4141       }
4142
4143     if (i1)
4144       {
4145         LOG_LINKS (i1) = NULL;
4146         REG_NOTES (i1) = 0;
4147         if (MAY_HAVE_DEBUG_INSNS)
4148           propagate_for_debug (i1, last_combined_insn, i1dest, i1src,
4149                                this_basic_block);
4150         SET_INSN_DELETED (i1);
4151       }
4152
4153     if (i0)
4154       {
4155         LOG_LINKS (i0) = NULL;
4156         REG_NOTES (i0) = 0;
4157         if (MAY_HAVE_DEBUG_INSNS)
4158           propagate_for_debug (i0, last_combined_insn, i0dest, i0src,
4159                                this_basic_block);
4160         SET_INSN_DELETED (i0);
4161       }
4162
4163     /* Get death notes for everything that is now used in either I3 or
4164        I2 and used to die in a previous insn.  If we built two new
4165        patterns, move from I1 to I2 then I2 to I3 so that we get the
4166        proper movement on registers that I2 modifies.  */
4167
4168     if (i0)
4169       from_luid = DF_INSN_LUID (i0);
4170     else if (i1)
4171       from_luid = DF_INSN_LUID (i1);
4172     else
4173       from_luid = DF_INSN_LUID (i2);
4174     if (newi2pat)
4175       move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4176     move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4177
4178     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
4179     if (i3notes)
4180       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL,
4181                         elim_i2, elim_i1, elim_i0);
4182     if (i2notes)
4183       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL,
4184                         elim_i2, elim_i1, elim_i0);
4185     if (i1notes)
4186       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL,
4187                         elim_i2, elim_i1, elim_i0);
4188     if (i0notes)
4189       distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL,
4190                         elim_i2, elim_i1, elim_i0);
4191     if (midnotes)
4192       distribute_notes (midnotes, NULL, i3, newi2pat ? i2 : NULL,
4193                         elim_i2, elim_i1, elim_i0);
4194
4195     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
4196        know these are REG_UNUSED and want them to go to the desired insn,
4197        so we always pass it as i3.  */
4198
4199     if (newi2pat && new_i2_notes)
4200       distribute_notes (new_i2_notes, i2, i2, NULL, NULL_RTX, NULL_RTX,
4201                         NULL_RTX);
4202
4203     if (new_i3_notes)
4204       distribute_notes (new_i3_notes, i3, i3, NULL, NULL_RTX, NULL_RTX,
4205                         NULL_RTX);
4206
4207     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
4208        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
4209        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
4210        in that case, it might delete I2.  Similarly for I2 and I1.
4211        Show an additional death due to the REG_DEAD note we make here.  If
4212        we discard it in distribute_notes, we will decrement it again.  */
4213
4214     if (i3dest_killed)
4215       {
4216         rtx new_note = alloc_reg_note (REG_DEAD, i3dest_killed, NULL_RTX);
4217         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4218           distribute_notes (new_note, NULL, i2, NULL, elim_i2,
4219                             elim_i1, elim_i0);
4220         else
4221           distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4222                             elim_i2, elim_i1, elim_i0);
4223       }
4224
4225     if (i2dest_in_i2src)
4226       {
4227         rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4228         if (newi2pat && reg_set_p (i2dest, newi2pat))
4229           distribute_notes (new_note,  NULL, i2, NULL, NULL_RTX,
4230                             NULL_RTX, NULL_RTX);
4231         else
4232           distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4233                             NULL_RTX, NULL_RTX, NULL_RTX);
4234       }
4235
4236     if (i1dest_in_i1src)
4237       {
4238         rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4239         if (newi2pat && reg_set_p (i1dest, newi2pat))
4240           distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4241                             NULL_RTX, NULL_RTX);
4242         else
4243           distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4244                             NULL_RTX, NULL_RTX, NULL_RTX);
4245       }
4246
4247     if (i0dest_in_i0src)
4248       {
4249         rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4250         if (newi2pat && reg_set_p (i0dest, newi2pat))
4251           distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4252                             NULL_RTX, NULL_RTX);
4253         else
4254           distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4255                             NULL_RTX, NULL_RTX, NULL_RTX);
4256       }
4257
4258     distribute_links (i3links);
4259     distribute_links (i2links);
4260     distribute_links (i1links);
4261     distribute_links (i0links);
4262
4263     if (REG_P (i2dest))
4264       {
4265         struct insn_link *link;
4266         rtx_insn *i2_insn = 0;
4267         rtx i2_val = 0, set;
4268
4269         /* The insn that used to set this register doesn't exist, and
4270            this life of the register may not exist either.  See if one of
4271            I3's links points to an insn that sets I2DEST.  If it does,
4272            that is now the last known value for I2DEST. If we don't update
4273            this and I2 set the register to a value that depended on its old
4274            contents, we will get confused.  If this insn is used, thing
4275            will be set correctly in combine_instructions.  */
4276         FOR_EACH_LOG_LINK (link, i3)
4277           if ((set = single_set (link->insn)) != 0
4278               && rtx_equal_p (i2dest, SET_DEST (set)))
4279             i2_insn = link->insn, i2_val = SET_SRC (set);
4280
4281         record_value_for_reg (i2dest, i2_insn, i2_val);
4282
4283         /* If the reg formerly set in I2 died only once and that was in I3,
4284            zero its use count so it won't make `reload' do any work.  */
4285         if (! added_sets_2
4286             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4287             && ! i2dest_in_i2src)
4288           INC_REG_N_SETS (REGNO (i2dest), -1);
4289       }
4290
4291     if (i1 && REG_P (i1dest))
4292       {
4293         struct insn_link *link;
4294         rtx_insn *i1_insn = 0;
4295         rtx i1_val = 0, set;
4296
4297         FOR_EACH_LOG_LINK (link, i3)
4298           if ((set = single_set (link->insn)) != 0
4299               && rtx_equal_p (i1dest, SET_DEST (set)))
4300             i1_insn = link->insn, i1_val = SET_SRC (set);
4301
4302         record_value_for_reg (i1dest, i1_insn, i1_val);
4303
4304         if (! added_sets_1 && ! i1dest_in_i1src)
4305           INC_REG_N_SETS (REGNO (i1dest), -1);
4306       }
4307
4308     if (i0 && REG_P (i0dest))
4309       {
4310         struct insn_link *link;
4311         rtx_insn *i0_insn = 0;
4312         rtx i0_val = 0, set;
4313
4314         FOR_EACH_LOG_LINK (link, i3)
4315           if ((set = single_set (link->insn)) != 0
4316               && rtx_equal_p (i0dest, SET_DEST (set)))
4317             i0_insn = link->insn, i0_val = SET_SRC (set);
4318
4319         record_value_for_reg (i0dest, i0_insn, i0_val);
4320
4321         if (! added_sets_0 && ! i0dest_in_i0src)
4322           INC_REG_N_SETS (REGNO (i0dest), -1);
4323       }
4324
4325     /* Update reg_stat[].nonzero_bits et al for any changes that may have
4326        been made to this insn.  The order is important, because newi2pat
4327        can affect nonzero_bits of newpat.  */
4328     if (newi2pat)
4329       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4330     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4331   }
4332
4333   if (undobuf.other_insn != NULL_RTX)
4334     {
4335       if (dump_file)
4336         {
4337           fprintf (dump_file, "modifying other_insn ");
4338           dump_insn_slim (dump_file, undobuf.other_insn);
4339         }
4340       df_insn_rescan (undobuf.other_insn);
4341     }
4342
4343   if (i0 && !(NOTE_P (i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4344     {
4345       if (dump_file)
4346         {
4347           fprintf (dump_file, "modifying insn i0 ");
4348           dump_insn_slim (dump_file, i0);
4349         }
4350       df_insn_rescan (i0);
4351     }
4352
4353   if (i1 && !(NOTE_P (i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4354     {
4355       if (dump_file)
4356         {
4357           fprintf (dump_file, "modifying insn i1 ");
4358           dump_insn_slim (dump_file, i1);
4359         }
4360       df_insn_rescan (i1);
4361     }
4362
4363   if (i2 && !(NOTE_P (i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4364     {
4365       if (dump_file)
4366         {
4367           fprintf (dump_file, "modifying insn i2 ");
4368           dump_insn_slim (dump_file, i2);
4369         }
4370       df_insn_rescan (i2);
4371     }
4372
4373   if (i3 && !(NOTE_P (i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4374     {
4375       if (dump_file)
4376         {
4377           fprintf (dump_file, "modifying insn i3 ");
4378           dump_insn_slim (dump_file, i3);
4379         }
4380       df_insn_rescan (i3);
4381     }
4382
4383   /* Set new_direct_jump_p if a new return or simple jump instruction
4384      has been created.  Adjust the CFG accordingly.  */
4385   if (returnjump_p (i3) || any_uncondjump_p (i3))
4386     {
4387       *new_direct_jump_p = 1;
4388       mark_jump_label (PATTERN (i3), i3, 0);
4389       update_cfg_for_uncondjump (i3);
4390     }
4391
4392   if (undobuf.other_insn != NULL_RTX
4393       && (returnjump_p (undobuf.other_insn)
4394           || any_uncondjump_p (undobuf.other_insn)))
4395     {
4396       *new_direct_jump_p = 1;
4397       update_cfg_for_uncondjump (undobuf.other_insn);
4398     }
4399
4400   /* A noop might also need cleaning up of CFG, if it comes from the
4401      simplification of a jump.  */
4402   if (JUMP_P (i3)
4403       && GET_CODE (newpat) == SET
4404       && SET_SRC (newpat) == pc_rtx
4405       && SET_DEST (newpat) == pc_rtx)
4406     {
4407       *new_direct_jump_p = 1;
4408       update_cfg_for_uncondjump (i3);
4409     }
4410
4411   if (undobuf.other_insn != NULL_RTX
4412       && JUMP_P (undobuf.other_insn)
4413       && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4414       && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4415       && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4416     {
4417       *new_direct_jump_p = 1;
4418       update_cfg_for_uncondjump (undobuf.other_insn);
4419     }
4420
4421   combine_successes++;
4422   undo_commit ();
4423
4424   if (added_links_insn
4425       && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4426       && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4427     return added_links_insn;
4428   else
4429     return newi2pat ? i2 : i3;
4430 }
4431 \f
4432 /* Undo all the modifications recorded in undobuf.  */
4433
4434 static void
4435 undo_all (void)
4436 {
4437   struct undo *undo, *next;
4438
4439   for (undo = undobuf.undos; undo; undo = next)
4440     {
4441       next = undo->next;
4442       switch (undo->kind)
4443         {
4444         case UNDO_RTX:
4445           *undo->where.r = undo->old_contents.r;
4446           break;
4447         case UNDO_INT:
4448           *undo->where.i = undo->old_contents.i;
4449           break;
4450         case UNDO_MODE:
4451           adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4452           break;
4453         case UNDO_LINKS:
4454           *undo->where.l = undo->old_contents.l;
4455           break;
4456         default:
4457           gcc_unreachable ();
4458         }
4459
4460       undo->next = undobuf.frees;
4461       undobuf.frees = undo;
4462     }
4463
4464   undobuf.undos = 0;
4465 }
4466
4467 /* We've committed to accepting the changes we made.  Move all
4468    of the undos to the free list.  */
4469
4470 static void
4471 undo_commit (void)
4472 {
4473   struct undo *undo, *next;
4474
4475   for (undo = undobuf.undos; undo; undo = next)
4476     {
4477       next = undo->next;
4478       undo->next = undobuf.frees;
4479       undobuf.frees = undo;
4480     }
4481   undobuf.undos = 0;
4482 }
4483 \f
4484 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4485    where we have an arithmetic expression and return that point.  LOC will
4486    be inside INSN.
4487
4488    try_combine will call this function to see if an insn can be split into
4489    two insns.  */
4490
4491 static rtx *
4492 find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
4493 {
4494   rtx x = *loc;
4495   enum rtx_code code = GET_CODE (x);
4496   rtx *split;
4497   unsigned HOST_WIDE_INT len = 0;
4498   HOST_WIDE_INT pos = 0;
4499   int unsignedp = 0;
4500   rtx inner = NULL_RTX;
4501
4502   /* First special-case some codes.  */
4503   switch (code)
4504     {
4505     case SUBREG:
4506 #ifdef INSN_SCHEDULING
4507       /* If we are making a paradoxical SUBREG invalid, it becomes a split
4508          point.  */
4509       if (MEM_P (SUBREG_REG (x)))
4510         return loc;
4511 #endif
4512       return find_split_point (&SUBREG_REG (x), insn, false);
4513
4514     case MEM:
4515 #ifdef HAVE_lo_sum
4516       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4517          using LO_SUM and HIGH.  */
4518       if (GET_CODE (XEXP (x, 0)) == CONST
4519           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4520         {
4521           machine_mode address_mode = get_address_mode (x);
4522
4523           SUBST (XEXP (x, 0),
4524                  gen_rtx_LO_SUM (address_mode,
4525                                  gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4526                                  XEXP (x, 0)));
4527           return &XEXP (XEXP (x, 0), 0);
4528         }
4529 #endif
4530
4531       /* If we have a PLUS whose second operand is a constant and the
4532          address is not valid, perhaps will can split it up using
4533          the machine-specific way to split large constants.  We use
4534          the first pseudo-reg (one of the virtual regs) as a placeholder;
4535          it will not remain in the result.  */
4536       if (GET_CODE (XEXP (x, 0)) == PLUS
4537           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4538           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4539                                             MEM_ADDR_SPACE (x)))
4540         {
4541           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4542           rtx_insn *seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4543                                                             XEXP (x, 0)),
4544                                                subst_insn);
4545
4546           /* This should have produced two insns, each of which sets our
4547              placeholder.  If the source of the second is a valid address,
4548              we can make put both sources together and make a split point
4549              in the middle.  */
4550
4551           if (seq
4552               && NEXT_INSN (seq) != NULL_RTX
4553               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4554               && NONJUMP_INSN_P (seq)
4555               && GET_CODE (PATTERN (seq)) == SET
4556               && SET_DEST (PATTERN (seq)) == reg
4557               && ! reg_mentioned_p (reg,
4558                                     SET_SRC (PATTERN (seq)))
4559               && NONJUMP_INSN_P (NEXT_INSN (seq))
4560               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4561               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4562               && memory_address_addr_space_p
4563                    (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4564                     MEM_ADDR_SPACE (x)))
4565             {
4566               rtx src1 = SET_SRC (PATTERN (seq));
4567               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4568
4569               /* Replace the placeholder in SRC2 with SRC1.  If we can
4570                  find where in SRC2 it was placed, that can become our
4571                  split point and we can replace this address with SRC2.
4572                  Just try two obvious places.  */
4573
4574               src2 = replace_rtx (src2, reg, src1);
4575               split = 0;
4576               if (XEXP (src2, 0) == src1)
4577                 split = &XEXP (src2, 0);
4578               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4579                        && XEXP (XEXP (src2, 0), 0) == src1)
4580                 split = &XEXP (XEXP (src2, 0), 0);
4581
4582               if (split)
4583                 {
4584                   SUBST (XEXP (x, 0), src2);
4585                   return split;
4586                 }
4587             }
4588
4589           /* If that didn't work, perhaps the first operand is complex and
4590              needs to be computed separately, so make a split point there.
4591              This will occur on machines that just support REG + CONST
4592              and have a constant moved through some previous computation.  */
4593
4594           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4595                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4596                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4597             return &XEXP (XEXP (x, 0), 0);
4598         }
4599
4600       /* If we have a PLUS whose first operand is complex, try computing it
4601          separately by making a split there.  */
4602       if (GET_CODE (XEXP (x, 0)) == PLUS
4603           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4604                                             MEM_ADDR_SPACE (x))
4605           && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4606           && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4607                 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4608         return &XEXP (XEXP (x, 0), 0);
4609       break;
4610
4611     case SET:
4612 #ifdef HAVE_cc0
4613       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4614          ZERO_EXTRACT, the most likely reason why this doesn't match is that
4615          we need to put the operand into a register.  So split at that
4616          point.  */
4617
4618       if (SET_DEST (x) == cc0_rtx
4619           && GET_CODE (SET_SRC (x)) != COMPARE
4620           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4621           && !OBJECT_P (SET_SRC (x))
4622           && ! (GET_CODE (SET_SRC (x)) == SUBREG
4623                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4624         return &SET_SRC (x);
4625 #endif
4626
4627       /* See if we can split SET_SRC as it stands.  */
4628       split = find_split_point (&SET_SRC (x), insn, true);
4629       if (split && split != &SET_SRC (x))
4630         return split;
4631
4632       /* See if we can split SET_DEST as it stands.  */
4633       split = find_split_point (&SET_DEST (x), insn, false);
4634       if (split && split != &SET_DEST (x))
4635         return split;
4636
4637       /* See if this is a bitfield assignment with everything constant.  If
4638          so, this is an IOR of an AND, so split it into that.  */
4639       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4640           && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x), 0)))
4641           && CONST_INT_P (XEXP (SET_DEST (x), 1))
4642           && CONST_INT_P (XEXP (SET_DEST (x), 2))
4643           && CONST_INT_P (SET_SRC (x))
4644           && ((INTVAL (XEXP (SET_DEST (x), 1))
4645                + INTVAL (XEXP (SET_DEST (x), 2)))
4646               <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0))))
4647           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4648         {
4649           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4650           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4651           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4652           rtx dest = XEXP (SET_DEST (x), 0);
4653           machine_mode mode = GET_MODE (dest);
4654           unsigned HOST_WIDE_INT mask
4655             = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4656           rtx or_mask;
4657
4658           if (BITS_BIG_ENDIAN)
4659             pos = GET_MODE_PRECISION (mode) - len - pos;
4660
4661           or_mask = gen_int_mode (src << pos, mode);
4662           if (src == mask)
4663             SUBST (SET_SRC (x),
4664                    simplify_gen_binary (IOR, mode, dest, or_mask));
4665           else
4666             {
4667               rtx negmask = gen_int_mode (~(mask << pos), mode);
4668               SUBST (SET_SRC (x),
4669                      simplify_gen_binary (IOR, mode,
4670                                           simplify_gen_binary (AND, mode,
4671                                                                dest, negmask),
4672                                           or_mask));
4673             }
4674
4675           SUBST (SET_DEST (x), dest);
4676
4677           split = find_split_point (&SET_SRC (x), insn, true);
4678           if (split && split != &SET_SRC (x))
4679             return split;
4680         }
4681
4682       /* Otherwise, see if this is an operation that we can split into two.
4683          If so, try to split that.  */
4684       code = GET_CODE (SET_SRC (x));
4685
4686       switch (code)
4687         {
4688         case AND:
4689           /* If we are AND'ing with a large constant that is only a single
4690              bit and the result is only being used in a context where we
4691              need to know if it is zero or nonzero, replace it with a bit
4692              extraction.  This will avoid the large constant, which might
4693              have taken more than one insn to make.  If the constant were
4694              not a valid argument to the AND but took only one insn to make,
4695              this is no worse, but if it took more than one insn, it will
4696              be better.  */
4697
4698           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4699               && REG_P (XEXP (SET_SRC (x), 0))
4700               && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4701               && REG_P (SET_DEST (x))
4702               && (split = find_single_use (SET_DEST (x), insn, NULL)) != 0
4703               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4704               && XEXP (*split, 0) == SET_DEST (x)
4705               && XEXP (*split, 1) == const0_rtx)
4706             {
4707               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4708                                                 XEXP (SET_SRC (x), 0),
4709                                                 pos, NULL_RTX, 1, 1, 0, 0);
4710               if (extraction != 0)
4711                 {
4712                   SUBST (SET_SRC (x), extraction);
4713                   return find_split_point (loc, insn, false);
4714                 }
4715             }
4716           break;
4717
4718         case NE:
4719           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4720              is known to be on, this can be converted into a NEG of a shift.  */
4721           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4722               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4723               && 1 <= (pos = exact_log2
4724                        (nonzero_bits (XEXP (SET_SRC (x), 0),
4725                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
4726             {
4727               machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4728
4729               SUBST (SET_SRC (x),
4730                      gen_rtx_NEG (mode,
4731                                   gen_rtx_LSHIFTRT (mode,
4732                                                     XEXP (SET_SRC (x), 0),
4733                                                     GEN_INT (pos))));
4734
4735               split = find_split_point (&SET_SRC (x), insn, true);
4736               if (split && split != &SET_SRC (x))
4737                 return split;
4738             }
4739           break;
4740
4741         case SIGN_EXTEND:
4742           inner = XEXP (SET_SRC (x), 0);
4743
4744           /* We can't optimize if either mode is a partial integer
4745              mode as we don't know how many bits are significant
4746              in those modes.  */
4747           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4748               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4749             break;
4750
4751           pos = 0;
4752           len = GET_MODE_PRECISION (GET_MODE (inner));
4753           unsignedp = 0;
4754           break;
4755
4756         case SIGN_EXTRACT:
4757         case ZERO_EXTRACT:
4758           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4759               && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4760             {
4761               inner = XEXP (SET_SRC (x), 0);
4762               len = INTVAL (XEXP (SET_SRC (x), 1));
4763               pos = INTVAL (XEXP (SET_SRC (x), 2));
4764
4765               if (BITS_BIG_ENDIAN)
4766                 pos = GET_MODE_PRECISION (GET_MODE (inner)) - len - pos;
4767               unsignedp = (code == ZERO_EXTRACT);
4768             }
4769           break;
4770
4771         default:
4772           break;
4773         }
4774
4775       if (len && pos >= 0
4776           && pos + len <= GET_MODE_PRECISION (GET_MODE (inner)))
4777         {
4778           machine_mode mode = GET_MODE (SET_SRC (x));
4779
4780           /* For unsigned, we have a choice of a shift followed by an
4781              AND or two shifts.  Use two shifts for field sizes where the
4782              constant might be too large.  We assume here that we can
4783              always at least get 8-bit constants in an AND insn, which is
4784              true for every current RISC.  */
4785
4786           if (unsignedp && len <= 8)
4787             {
4788               unsigned HOST_WIDE_INT mask
4789                 = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4790               SUBST (SET_SRC (x),
4791                      gen_rtx_AND (mode,
4792                                   gen_rtx_LSHIFTRT
4793                                   (mode, gen_lowpart (mode, inner),
4794                                    GEN_INT (pos)),
4795                                   gen_int_mode (mask, mode)));
4796
4797               split = find_split_point (&SET_SRC (x), insn, true);
4798               if (split && split != &SET_SRC (x))
4799                 return split;
4800             }
4801           else
4802             {
4803               SUBST (SET_SRC (x),
4804                      gen_rtx_fmt_ee
4805                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4806                       gen_rtx_ASHIFT (mode,
4807                                       gen_lowpart (mode, inner),
4808                                       GEN_INT (GET_MODE_PRECISION (mode)
4809                                                - len - pos)),
4810                       GEN_INT (GET_MODE_PRECISION (mode) - len)));
4811
4812               split = find_split_point (&SET_SRC (x), insn, true);
4813               if (split && split != &SET_SRC (x))
4814                 return split;
4815             }
4816         }
4817
4818       /* See if this is a simple operation with a constant as the second
4819          operand.  It might be that this constant is out of range and hence
4820          could be used as a split point.  */
4821       if (BINARY_P (SET_SRC (x))
4822           && CONSTANT_P (XEXP (SET_SRC (x), 1))
4823           && (OBJECT_P (XEXP (SET_SRC (x), 0))
4824               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4825                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4826         return &XEXP (SET_SRC (x), 1);
4827
4828       /* Finally, see if this is a simple operation with its first operand
4829          not in a register.  The operation might require this operand in a
4830          register, so return it as a split point.  We can always do this
4831          because if the first operand were another operation, we would have
4832          already found it as a split point.  */
4833       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4834           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4835         return &XEXP (SET_SRC (x), 0);
4836
4837       return 0;
4838
4839     case AND:
4840     case IOR:
4841       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4842          it is better to write this as (not (ior A B)) so we can split it.
4843          Similarly for IOR.  */
4844       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4845         {
4846           SUBST (*loc,
4847                  gen_rtx_NOT (GET_MODE (x),
4848                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4849                                               GET_MODE (x),
4850                                               XEXP (XEXP (x, 0), 0),
4851                                               XEXP (XEXP (x, 1), 0))));
4852           return find_split_point (loc, insn, set_src);
4853         }
4854
4855       /* Many RISC machines have a large set of logical insns.  If the
4856          second operand is a NOT, put it first so we will try to split the
4857          other operand first.  */
4858       if (GET_CODE (XEXP (x, 1)) == NOT)
4859         {
4860           rtx tem = XEXP (x, 0);
4861           SUBST (XEXP (x, 0), XEXP (x, 1));
4862           SUBST (XEXP (x, 1), tem);
4863         }
4864       break;
4865
4866     case PLUS:
4867     case MINUS:
4868       /* Canonicalization can produce (minus A (mult B C)), where C is a
4869          constant.  It may be better to try splitting (plus (mult B -C) A)
4870          instead if this isn't a multiply by a power of two.  */
4871       if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4872           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4873           && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4874         {
4875           machine_mode mode = GET_MODE (x);
4876           unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4877           HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4878           SUBST (*loc, gen_rtx_PLUS (mode,
4879                                      gen_rtx_MULT (mode,
4880                                                    XEXP (XEXP (x, 1), 0),
4881                                                    gen_int_mode (other_int,
4882                                                                  mode)),
4883                                      XEXP (x, 0)));
4884           return find_split_point (loc, insn, set_src);
4885         }
4886
4887       /* Split at a multiply-accumulate instruction.  However if this is
4888          the SET_SRC, we likely do not have such an instruction and it's
4889          worthless to try this split.  */
4890       if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4891         return loc;
4892
4893     default:
4894       break;
4895     }
4896
4897   /* Otherwise, select our actions depending on our rtx class.  */
4898   switch (GET_RTX_CLASS (code))
4899     {
4900     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
4901     case RTX_TERNARY:
4902       split = find_split_point (&XEXP (x, 2), insn, false);
4903       if (split)
4904         return split;
4905       /* ... fall through ...  */
4906     case RTX_BIN_ARITH:
4907     case RTX_COMM_ARITH:
4908     case RTX_COMPARE:
4909     case RTX_COMM_COMPARE:
4910       split = find_split_point (&XEXP (x, 1), insn, false);
4911       if (split)
4912         return split;
4913       /* ... fall through ...  */
4914     case RTX_UNARY:
4915       /* Some machines have (and (shift ...) ...) insns.  If X is not
4916          an AND, but XEXP (X, 0) is, use it as our split point.  */
4917       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4918         return &XEXP (x, 0);
4919
4920       split = find_split_point (&XEXP (x, 0), insn, false);
4921       if (split)
4922         return split;
4923       return loc;
4924
4925     default:
4926       /* Otherwise, we don't have a split point.  */
4927       return 0;
4928     }
4929 }
4930 \f
4931 /* Throughout X, replace FROM with TO, and return the result.
4932    The result is TO if X is FROM;
4933    otherwise the result is X, but its contents may have been modified.
4934    If they were modified, a record was made in undobuf so that
4935    undo_all will (among other things) return X to its original state.
4936
4937    If the number of changes necessary is too much to record to undo,
4938    the excess changes are not made, so the result is invalid.
4939    The changes already made can still be undone.
4940    undobuf.num_undo is incremented for such changes, so by testing that
4941    the caller can tell whether the result is valid.
4942
4943    `n_occurrences' is incremented each time FROM is replaced.
4944
4945    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
4946
4947    IN_COND is nonzero if we are at the top level of a condition.
4948
4949    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
4950    by copying if `n_occurrences' is nonzero.  */
4951
4952 static rtx
4953 subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
4954 {
4955   enum rtx_code code = GET_CODE (x);
4956   machine_mode op0_mode = VOIDmode;
4957   const char *fmt;
4958   int len, i;
4959   rtx new_rtx;
4960
4961 /* Two expressions are equal if they are identical copies of a shared
4962    RTX or if they are both registers with the same register number
4963    and mode.  */
4964
4965 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
4966   ((X) == (Y)                                           \
4967    || (REG_P (X) && REG_P (Y)   \
4968        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
4969
4970   /* Do not substitute into clobbers of regs -- this will never result in
4971      valid RTL.  */
4972   if (GET_CODE (x) == CLOBBER && REG_P (XEXP (x, 0)))
4973     return x;
4974
4975   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
4976     {
4977       n_occurrences++;
4978       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
4979     }
4980
4981   /* If X and FROM are the same register but different modes, they
4982      will not have been seen as equal above.  However, the log links code
4983      will make a LOG_LINKS entry for that case.  If we do nothing, we
4984      will try to rerecognize our original insn and, when it succeeds,
4985      we will delete the feeding insn, which is incorrect.
4986
4987      So force this insn not to match in this (rare) case.  */
4988   if (! in_dest && code == REG && REG_P (from)
4989       && reg_overlap_mentioned_p (x, from))
4990     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
4991
4992   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
4993      of which may contain things that can be combined.  */
4994   if (code != MEM && code != LO_SUM && OBJECT_P (x))
4995     return x;
4996
4997   /* It is possible to have a subexpression appear twice in the insn.
4998      Suppose that FROM is a register that appears within TO.
4999      Then, after that subexpression has been scanned once by `subst',
5000      the second time it is scanned, TO may be found.  If we were
5001      to scan TO here, we would find FROM within it and create a
5002      self-referent rtl structure which is completely wrong.  */
5003   if (COMBINE_RTX_EQUAL_P (x, to))
5004     return to;
5005
5006   /* Parallel asm_operands need special attention because all of the
5007      inputs are shared across the arms.  Furthermore, unsharing the
5008      rtl results in recognition failures.  Failure to handle this case
5009      specially can result in circular rtl.
5010
5011      Solve this by doing a normal pass across the first entry of the
5012      parallel, and only processing the SET_DESTs of the subsequent
5013      entries.  Ug.  */
5014
5015   if (code == PARALLEL
5016       && GET_CODE (XVECEXP (x, 0, 0)) == SET
5017       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
5018     {
5019       new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
5020
5021       /* If this substitution failed, this whole thing fails.  */
5022       if (GET_CODE (new_rtx) == CLOBBER
5023           && XEXP (new_rtx, 0) == const0_rtx)
5024         return new_rtx;
5025
5026       SUBST (XVECEXP (x, 0, 0), new_rtx);
5027
5028       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
5029         {
5030           rtx dest = SET_DEST (XVECEXP (x, 0, i));
5031
5032           if (!REG_P (dest)
5033               && GET_CODE (dest) != CC0
5034               && GET_CODE (dest) != PC)
5035             {
5036               new_rtx = subst (dest, from, to, 0, 0, unique_copy);
5037
5038               /* If this substitution failed, this whole thing fails.  */
5039               if (GET_CODE (new_rtx) == CLOBBER
5040                   && XEXP (new_rtx, 0) == const0_rtx)
5041                 return new_rtx;
5042
5043               SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
5044             }
5045         }
5046     }
5047   else
5048     {
5049       len = GET_RTX_LENGTH (code);
5050       fmt = GET_RTX_FORMAT (code);
5051
5052       /* We don't need to process a SET_DEST that is a register, CC0,
5053          or PC, so set up to skip this common case.  All other cases
5054          where we want to suppress replacing something inside a
5055          SET_SRC are handled via the IN_DEST operand.  */
5056       if (code == SET
5057           && (REG_P (SET_DEST (x))
5058               || GET_CODE (SET_DEST (x)) == CC0
5059               || GET_CODE (SET_DEST (x)) == PC))
5060         fmt = "ie";
5061
5062       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5063          constant.  */
5064       if (fmt[0] == 'e')
5065         op0_mode = GET_MODE (XEXP (x, 0));
5066
5067       for (i = 0; i < len; i++)
5068         {
5069           if (fmt[i] == 'E')
5070             {
5071               int j;
5072               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5073                 {
5074                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5075                     {
5076                       new_rtx = (unique_copy && n_occurrences
5077                              ? copy_rtx (to) : to);
5078                       n_occurrences++;
5079                     }
5080                   else
5081                     {
5082                       new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
5083                                        unique_copy);
5084
5085                       /* If this substitution failed, this whole thing
5086                          fails.  */
5087                       if (GET_CODE (new_rtx) == CLOBBER
5088                           && XEXP (new_rtx, 0) == const0_rtx)
5089                         return new_rtx;
5090                     }
5091
5092                   SUBST (XVECEXP (x, i, j), new_rtx);
5093                 }
5094             }
5095           else if (fmt[i] == 'e')
5096             {
5097               /* If this is a register being set, ignore it.  */
5098               new_rtx = XEXP (x, i);
5099               if (in_dest
5100                   && i == 0
5101                   && (((code == SUBREG || code == ZERO_EXTRACT)
5102                        && REG_P (new_rtx))
5103                       || code == STRICT_LOW_PART))
5104                 ;
5105
5106               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5107                 {
5108                   /* In general, don't install a subreg involving two
5109                      modes not tieable.  It can worsen register
5110                      allocation, and can even make invalid reload
5111                      insns, since the reg inside may need to be copied
5112                      from in the outside mode, and that may be invalid
5113                      if it is an fp reg copied in integer mode.
5114
5115                      We allow two exceptions to this: It is valid if
5116                      it is inside another SUBREG and the mode of that
5117                      SUBREG and the mode of the inside of TO is
5118                      tieable and it is valid if X is a SET that copies
5119                      FROM to CC0.  */
5120
5121                   if (GET_CODE (to) == SUBREG
5122                       && ! MODES_TIEABLE_P (GET_MODE (to),
5123                                             GET_MODE (SUBREG_REG (to)))
5124                       && ! (code == SUBREG
5125                             && MODES_TIEABLE_P (GET_MODE (x),
5126                                                 GET_MODE (SUBREG_REG (to))))
5127 #ifdef HAVE_cc0
5128                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5129 #endif
5130                       )
5131                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5132
5133                   if (code == SUBREG
5134                       && REG_P (to)
5135                       && REGNO (to) < FIRST_PSEUDO_REGISTER
5136                       && simplify_subreg_regno (REGNO (to), GET_MODE (to),
5137                                                 SUBREG_BYTE (x),
5138                                                 GET_MODE (x)) < 0)
5139                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5140
5141                   new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5142                   n_occurrences++;
5143                 }
5144               else
5145                 /* If we are in a SET_DEST, suppress most cases unless we
5146                    have gone inside a MEM, in which case we want to
5147                    simplify the address.  We assume here that things that
5148                    are actually part of the destination have their inner
5149                    parts in the first expression.  This is true for SUBREG,
5150                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5151                    things aside from REG and MEM that should appear in a
5152                    SET_DEST.  */
5153                 new_rtx = subst (XEXP (x, i), from, to,
5154                              (((in_dest
5155                                 && (code == SUBREG || code == STRICT_LOW_PART
5156                                     || code == ZERO_EXTRACT))
5157                                || code == SET)
5158                               && i == 0),
5159                                  code == IF_THEN_ELSE && i == 0,
5160                                  unique_copy);
5161
5162               /* If we found that we will have to reject this combination,
5163                  indicate that by returning the CLOBBER ourselves, rather than
5164                  an expression containing it.  This will speed things up as
5165                  well as prevent accidents where two CLOBBERs are considered
5166                  to be equal, thus producing an incorrect simplification.  */
5167
5168               if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5169                 return new_rtx;
5170
5171               if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx))
5172                 {
5173                   machine_mode mode = GET_MODE (x);
5174
5175                   x = simplify_subreg (GET_MODE (x), new_rtx,
5176                                        GET_MODE (SUBREG_REG (x)),
5177                                        SUBREG_BYTE (x));
5178                   if (! x)
5179                     x = gen_rtx_CLOBBER (mode, const0_rtx);
5180                 }
5181               else if (CONST_SCALAR_INT_P (new_rtx)
5182                        && GET_CODE (x) == ZERO_EXTEND)
5183                 {
5184                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5185                                                 new_rtx, GET_MODE (XEXP (x, 0)));
5186                   gcc_assert (x);
5187                 }
5188               else
5189                 SUBST (XEXP (x, i), new_rtx);
5190             }
5191         }
5192     }
5193
5194   /* Check if we are loading something from the constant pool via float
5195      extension; in this case we would undo compress_float_constant
5196      optimization and degenerate constant load to an immediate value.  */
5197   if (GET_CODE (x) == FLOAT_EXTEND
5198       && MEM_P (XEXP (x, 0))
5199       && MEM_READONLY_P (XEXP (x, 0)))
5200     {
5201       rtx tmp = avoid_constant_pool_reference (x);
5202       if (x != tmp)
5203         return x;
5204     }
5205
5206   /* Try to simplify X.  If the simplification changed the code, it is likely
5207      that further simplification will help, so loop, but limit the number
5208      of repetitions that will be performed.  */
5209
5210   for (i = 0; i < 4; i++)
5211     {
5212       /* If X is sufficiently simple, don't bother trying to do anything
5213          with it.  */
5214       if (code != CONST_INT && code != REG && code != CLOBBER)
5215         x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5216
5217       if (GET_CODE (x) == code)
5218         break;
5219
5220       code = GET_CODE (x);
5221
5222       /* We no longer know the original mode of operand 0 since we
5223          have changed the form of X)  */
5224       op0_mode = VOIDmode;
5225     }
5226
5227   return x;
5228 }
5229 \f
5230 /* Simplify X, a piece of RTL.  We just operate on the expression at the
5231    outer level; call `subst' to simplify recursively.  Return the new
5232    expression.
5233
5234    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
5235    if we are inside a SET_DEST.  IN_COND is nonzero if we are at the top level
5236    of a condition.  */
5237
5238 static rtx
5239 combine_simplify_rtx (rtx x, machine_mode op0_mode, int in_dest,
5240                       int in_cond)
5241 {
5242   enum rtx_code code = GET_CODE (x);
5243   machine_mode mode = GET_MODE (x);
5244   rtx temp;
5245   int i;
5246
5247   /* If this is a commutative operation, put a constant last and a complex
5248      expression first.  We don't need to do this for comparisons here.  */
5249   if (COMMUTATIVE_ARITH_P (x)
5250       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5251     {
5252       temp = XEXP (x, 0);
5253       SUBST (XEXP (x, 0), XEXP (x, 1));
5254       SUBST (XEXP (x, 1), temp);
5255     }
5256
5257   /* If this is a simple operation applied to an IF_THEN_ELSE, try
5258      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
5259      things.  Check for cases where both arms are testing the same
5260      condition.
5261
5262      Don't do anything if all operands are very simple.  */
5263
5264   if ((BINARY_P (x)
5265        && ((!OBJECT_P (XEXP (x, 0))
5266             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5267                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5268            || (!OBJECT_P (XEXP (x, 1))
5269                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5270                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5271       || (UNARY_P (x)
5272           && (!OBJECT_P (XEXP (x, 0))
5273                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5274                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5275     {
5276       rtx cond, true_rtx, false_rtx;
5277
5278       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5279       if (cond != 0
5280           /* If everything is a comparison, what we have is highly unlikely
5281              to be simpler, so don't use it.  */
5282           && ! (COMPARISON_P (x)
5283                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5284         {
5285           rtx cop1 = const0_rtx;
5286           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5287
5288           if (cond_code == NE && COMPARISON_P (cond))
5289             return x;
5290
5291           /* Simplify the alternative arms; this may collapse the true and
5292              false arms to store-flag values.  Be careful to use copy_rtx
5293              here since true_rtx or false_rtx might share RTL with x as a
5294              result of the if_then_else_cond call above.  */
5295           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5296           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5297
5298           /* If true_rtx and false_rtx are not general_operands, an if_then_else
5299              is unlikely to be simpler.  */
5300           if (general_operand (true_rtx, VOIDmode)
5301               && general_operand (false_rtx, VOIDmode))
5302             {
5303               enum rtx_code reversed;
5304
5305               /* Restarting if we generate a store-flag expression will cause
5306                  us to loop.  Just drop through in this case.  */
5307
5308               /* If the result values are STORE_FLAG_VALUE and zero, we can
5309                  just make the comparison operation.  */
5310               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5311                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5312                                              cond, cop1);
5313               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5314                        && ((reversed = reversed_comparison_code_parts
5315                                         (cond_code, cond, cop1, NULL))
5316                            != UNKNOWN))
5317                 x = simplify_gen_relational (reversed, mode, VOIDmode,
5318                                              cond, cop1);
5319
5320               /* Likewise, we can make the negate of a comparison operation
5321                  if the result values are - STORE_FLAG_VALUE and zero.  */
5322               else if (CONST_INT_P (true_rtx)
5323                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5324                        && false_rtx == const0_rtx)
5325                 x = simplify_gen_unary (NEG, mode,
5326                                         simplify_gen_relational (cond_code,
5327                                                                  mode, VOIDmode,
5328                                                                  cond, cop1),
5329                                         mode);
5330               else if (CONST_INT_P (false_rtx)
5331                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5332                        && true_rtx == const0_rtx
5333                        && ((reversed = reversed_comparison_code_parts
5334                                         (cond_code, cond, cop1, NULL))
5335                            != UNKNOWN))
5336                 x = simplify_gen_unary (NEG, mode,
5337                                         simplify_gen_relational (reversed,
5338                                                                  mode, VOIDmode,
5339                                                                  cond, cop1),
5340                                         mode);
5341               else
5342                 return gen_rtx_IF_THEN_ELSE (mode,
5343                                              simplify_gen_relational (cond_code,
5344                                                                       mode,
5345                                                                       VOIDmode,
5346                                                                       cond,
5347                                                                       cop1),
5348                                              true_rtx, false_rtx);
5349
5350               code = GET_CODE (x);
5351               op0_mode = VOIDmode;
5352             }
5353         }
5354     }
5355
5356   /* Try to fold this expression in case we have constants that weren't
5357      present before.  */
5358   temp = 0;
5359   switch (GET_RTX_CLASS (code))
5360     {
5361     case RTX_UNARY:
5362       if (op0_mode == VOIDmode)
5363         op0_mode = GET_MODE (XEXP (x, 0));
5364       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5365       break;
5366     case RTX_COMPARE:
5367     case RTX_COMM_COMPARE:
5368       {
5369         machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5370         if (cmp_mode == VOIDmode)
5371           {
5372             cmp_mode = GET_MODE (XEXP (x, 1));
5373             if (cmp_mode == VOIDmode)
5374               cmp_mode = op0_mode;
5375           }
5376         temp = simplify_relational_operation (code, mode, cmp_mode,
5377                                               XEXP (x, 0), XEXP (x, 1));
5378       }
5379       break;
5380     case RTX_COMM_ARITH:
5381     case RTX_BIN_ARITH:
5382       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5383       break;
5384     case RTX_BITFIELD_OPS:
5385     case RTX_TERNARY:
5386       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5387                                          XEXP (x, 1), XEXP (x, 2));
5388       break;
5389     default:
5390       break;
5391     }
5392
5393   if (temp)
5394     {
5395       x = temp;
5396       code = GET_CODE (temp);
5397       op0_mode = VOIDmode;
5398       mode = GET_MODE (temp);
5399     }
5400
5401   /* First see if we can apply the inverse distributive law.  */
5402   if (code == PLUS || code == MINUS
5403       || code == AND || code == IOR || code == XOR)
5404     {
5405       x = apply_distributive_law (x);
5406       code = GET_CODE (x);
5407       op0_mode = VOIDmode;
5408     }
5409
5410   /* If CODE is an associative operation not otherwise handled, see if we
5411      can associate some operands.  This can win if they are constants or
5412      if they are logically related (i.e. (a & b) & a).  */
5413   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5414        || code == AND || code == IOR || code == XOR
5415        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5416       && ((INTEGRAL_MODE_P (mode) && code != DIV)
5417           || (flag_associative_math && FLOAT_MODE_P (mode))))
5418     {
5419       if (GET_CODE (XEXP (x, 0)) == code)
5420         {
5421           rtx other = XEXP (XEXP (x, 0), 0);
5422           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5423           rtx inner_op1 = XEXP (x, 1);
5424           rtx inner;
5425
5426           /* Make sure we pass the constant operand if any as the second
5427              one if this is a commutative operation.  */
5428           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5429             {
5430               rtx tem = inner_op0;
5431               inner_op0 = inner_op1;
5432               inner_op1 = tem;
5433             }
5434           inner = simplify_binary_operation (code == MINUS ? PLUS
5435                                              : code == DIV ? MULT
5436                                              : code,
5437                                              mode, inner_op0, inner_op1);
5438
5439           /* For commutative operations, try the other pair if that one
5440              didn't simplify.  */
5441           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5442             {
5443               other = XEXP (XEXP (x, 0), 1);
5444               inner = simplify_binary_operation (code, mode,
5445                                                  XEXP (XEXP (x, 0), 0),
5446                                                  XEXP (x, 1));
5447             }
5448
5449           if (inner)
5450             return simplify_gen_binary (code, mode, other, inner);
5451         }
5452     }
5453
5454   /* A little bit of algebraic simplification here.  */
5455   switch (code)
5456     {
5457     case MEM:
5458       /* Ensure that our address has any ASHIFTs converted to MULT in case
5459          address-recognizing predicates are called later.  */
5460       temp = make_compound_operation (XEXP (x, 0), MEM);
5461       SUBST (XEXP (x, 0), temp);
5462       break;
5463
5464     case SUBREG:
5465       if (op0_mode == VOIDmode)
5466         op0_mode = GET_MODE (SUBREG_REG (x));
5467
5468       /* See if this can be moved to simplify_subreg.  */
5469       if (CONSTANT_P (SUBREG_REG (x))
5470           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5471              /* Don't call gen_lowpart if the inner mode
5472                 is VOIDmode and we cannot simplify it, as SUBREG without
5473                 inner mode is invalid.  */
5474           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5475               || gen_lowpart_common (mode, SUBREG_REG (x))))
5476         return gen_lowpart (mode, SUBREG_REG (x));
5477
5478       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5479         break;
5480       {
5481         rtx temp;
5482         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5483                                 SUBREG_BYTE (x));
5484         if (temp)
5485           return temp;
5486
5487         /* If op is known to have all lower bits zero, the result is zero.  */
5488         if (!in_dest
5489             && SCALAR_INT_MODE_P (mode)
5490             && SCALAR_INT_MODE_P (op0_mode)
5491             && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (op0_mode)
5492             && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5493             && HWI_COMPUTABLE_MODE_P (op0_mode)
5494             && (nonzero_bits (SUBREG_REG (x), op0_mode)
5495                 & GET_MODE_MASK (mode)) == 0)
5496           return CONST0_RTX (mode);
5497       }
5498
5499       /* Don't change the mode of the MEM if that would change the meaning
5500          of the address.  */
5501       if (MEM_P (SUBREG_REG (x))
5502           && (MEM_VOLATILE_P (SUBREG_REG (x))
5503               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0),
5504                                            MEM_ADDR_SPACE (SUBREG_REG (x)))))
5505         return gen_rtx_CLOBBER (mode, const0_rtx);
5506
5507       /* Note that we cannot do any narrowing for non-constants since
5508          we might have been counting on using the fact that some bits were
5509          zero.  We now do this in the SET.  */
5510
5511       break;
5512
5513     case NEG:
5514       temp = expand_compound_operation (XEXP (x, 0));
5515
5516       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5517          replaced by (lshiftrt X C).  This will convert
5518          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
5519
5520       if (GET_CODE (temp) == ASHIFTRT
5521           && CONST_INT_P (XEXP (temp, 1))
5522           && INTVAL (XEXP (temp, 1)) == GET_MODE_PRECISION (mode) - 1)
5523         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5524                                      INTVAL (XEXP (temp, 1)));
5525
5526       /* If X has only a single bit that might be nonzero, say, bit I, convert
5527          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5528          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
5529          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
5530          or a SUBREG of one since we'd be making the expression more
5531          complex if it was just a register.  */
5532
5533       if (!REG_P (temp)
5534           && ! (GET_CODE (temp) == SUBREG
5535                 && REG_P (SUBREG_REG (temp)))
5536           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5537         {
5538           rtx temp1 = simplify_shift_const
5539             (NULL_RTX, ASHIFTRT, mode,
5540              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5541                                    GET_MODE_PRECISION (mode) - 1 - i),
5542              GET_MODE_PRECISION (mode) - 1 - i);
5543
5544           /* If all we did was surround TEMP with the two shifts, we
5545              haven't improved anything, so don't use it.  Otherwise,
5546              we are better off with TEMP1.  */
5547           if (GET_CODE (temp1) != ASHIFTRT
5548               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5549               || XEXP (XEXP (temp1, 0), 0) != temp)
5550             return temp1;
5551         }
5552       break;
5553
5554     case TRUNCATE:
5555       /* We can't handle truncation to a partial integer mode here
5556          because we don't know the real bitsize of the partial
5557          integer mode.  */
5558       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5559         break;
5560
5561       if (HWI_COMPUTABLE_MODE_P (mode))
5562         SUBST (XEXP (x, 0),
5563                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5564                               GET_MODE_MASK (mode), 0));
5565
5566       /* We can truncate a constant value and return it.  */
5567       if (CONST_INT_P (XEXP (x, 0)))
5568         return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5569
5570       /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5571          whose value is a comparison can be replaced with a subreg if
5572          STORE_FLAG_VALUE permits.  */
5573       if (HWI_COMPUTABLE_MODE_P (mode)
5574           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5575           && (temp = get_last_value (XEXP (x, 0)))
5576           && COMPARISON_P (temp))
5577         return gen_lowpart (mode, XEXP (x, 0));
5578       break;
5579
5580     case CONST:
5581       /* (const (const X)) can become (const X).  Do it this way rather than
5582          returning the inner CONST since CONST can be shared with a
5583          REG_EQUAL note.  */
5584       if (GET_CODE (XEXP (x, 0)) == CONST)
5585         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5586       break;
5587
5588 #ifdef HAVE_lo_sum
5589     case LO_SUM:
5590       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
5591          can add in an offset.  find_split_point will split this address up
5592          again if it doesn't match.  */
5593       if (GET_CODE (XEXP (x, 0)) == HIGH
5594           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5595         return XEXP (x, 1);
5596       break;
5597 #endif
5598
5599     case PLUS:
5600       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5601          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5602          bit-field and can be replaced by either a sign_extend or a
5603          sign_extract.  The `and' may be a zero_extend and the two
5604          <c>, -<c> constants may be reversed.  */
5605       if (GET_CODE (XEXP (x, 0)) == XOR
5606           && CONST_INT_P (XEXP (x, 1))
5607           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5608           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5609           && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5610               || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
5611           && HWI_COMPUTABLE_MODE_P (mode)
5612           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5613                && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5614                && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5615                    == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1))
5616               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5617                   && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5618                       == (unsigned int) i + 1))))
5619         return simplify_shift_const
5620           (NULL_RTX, ASHIFTRT, mode,
5621            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5622                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
5623                                  GET_MODE_PRECISION (mode) - (i + 1)),
5624            GET_MODE_PRECISION (mode) - (i + 1));
5625
5626       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5627          can become (ashiftrt (ashift (xor x 1) C) C) where C is
5628          the bitsize of the mode - 1.  This allows simplification of
5629          "a = (b & 8) == 0;"  */
5630       if (XEXP (x, 1) == constm1_rtx
5631           && !REG_P (XEXP (x, 0))
5632           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5633                 && REG_P (SUBREG_REG (XEXP (x, 0))))
5634           && nonzero_bits (XEXP (x, 0), mode) == 1)
5635         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5636            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5637                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5638                                  GET_MODE_PRECISION (mode) - 1),
5639            GET_MODE_PRECISION (mode) - 1);
5640
5641       /* If we are adding two things that have no bits in common, convert
5642          the addition into an IOR.  This will often be further simplified,
5643          for example in cases like ((a & 1) + (a & 2)), which can
5644          become a & 3.  */
5645
5646       if (HWI_COMPUTABLE_MODE_P (mode)
5647           && (nonzero_bits (XEXP (x, 0), mode)
5648               & nonzero_bits (XEXP (x, 1), mode)) == 0)
5649         {
5650           /* Try to simplify the expression further.  */
5651           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5652           temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
5653
5654           /* If we could, great.  If not, do not go ahead with the IOR
5655              replacement, since PLUS appears in many special purpose
5656              address arithmetic instructions.  */
5657           if (GET_CODE (temp) != CLOBBER
5658               && (GET_CODE (temp) != IOR
5659                   || ((XEXP (temp, 0) != XEXP (x, 0)
5660                        || XEXP (temp, 1) != XEXP (x, 1))
5661                       && (XEXP (temp, 0) != XEXP (x, 1)
5662                           || XEXP (temp, 1) != XEXP (x, 0)))))
5663             return temp;
5664         }
5665       break;
5666
5667     case MINUS:
5668       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5669          (and <foo> (const_int pow2-1))  */
5670       if (GET_CODE (XEXP (x, 1)) == AND
5671           && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5672           && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5673           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5674         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5675                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5676       break;
5677
5678     case MULT:
5679       /* If we have (mult (plus A B) C), apply the distributive law and then
5680          the inverse distributive law to see if things simplify.  This
5681          occurs mostly in addresses, often when unrolling loops.  */
5682
5683       if (GET_CODE (XEXP (x, 0)) == PLUS)
5684         {
5685           rtx result = distribute_and_simplify_rtx (x, 0);
5686           if (result)
5687             return result;
5688         }
5689
5690       /* Try simplify a*(b/c) as (a*b)/c.  */
5691       if (FLOAT_MODE_P (mode) && flag_associative_math
5692           && GET_CODE (XEXP (x, 0)) == DIV)
5693         {
5694           rtx tem = simplify_binary_operation (MULT, mode,
5695                                                XEXP (XEXP (x, 0), 0),
5696                                                XEXP (x, 1));
5697           if (tem)
5698             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5699         }
5700       break;
5701
5702     case UDIV:
5703       /* If this is a divide by a power of two, treat it as a shift if
5704          its first operand is a shift.  */
5705       if (CONST_INT_P (XEXP (x, 1))
5706           && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
5707           && (GET_CODE (XEXP (x, 0)) == ASHIFT
5708               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5709               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5710               || GET_CODE (XEXP (x, 0)) == ROTATE
5711               || GET_CODE (XEXP (x, 0)) == ROTATERT))
5712         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5713       break;
5714
5715     case EQ:  case NE:
5716     case GT:  case GTU:  case GE:  case GEU:
5717     case LT:  case LTU:  case LE:  case LEU:
5718     case UNEQ:  case LTGT:
5719     case UNGT:  case UNGE:
5720     case UNLT:  case UNLE:
5721     case UNORDERED: case ORDERED:
5722       /* If the first operand is a condition code, we can't do anything
5723          with it.  */
5724       if (GET_CODE (XEXP (x, 0)) == COMPARE
5725           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5726               && ! CC0_P (XEXP (x, 0))))
5727         {
5728           rtx op0 = XEXP (x, 0);
5729           rtx op1 = XEXP (x, 1);
5730           enum rtx_code new_code;
5731
5732           if (GET_CODE (op0) == COMPARE)
5733             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5734
5735           /* Simplify our comparison, if possible.  */
5736           new_code = simplify_comparison (code, &op0, &op1);
5737
5738           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5739              if only the low-order bit is possibly nonzero in X (such as when
5740              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
5741              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
5742              known to be either 0 or -1, NE becomes a NEG and EQ becomes
5743              (plus X 1).
5744
5745              Remove any ZERO_EXTRACT we made when thinking this was a
5746              comparison.  It may now be simpler to use, e.g., an AND.  If a
5747              ZERO_EXTRACT is indeed appropriate, it will be placed back by
5748              the call to make_compound_operation in the SET case.
5749
5750              Don't apply these optimizations if the caller would
5751              prefer a comparison rather than a value.
5752              E.g., for the condition in an IF_THEN_ELSE most targets need
5753              an explicit comparison.  */
5754
5755           if (in_cond)
5756             ;
5757
5758           else if (STORE_FLAG_VALUE == 1
5759               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5760               && op1 == const0_rtx
5761               && mode == GET_MODE (op0)
5762               && nonzero_bits (op0, mode) == 1)
5763             return gen_lowpart (mode,
5764                                 expand_compound_operation (op0));
5765
5766           else if (STORE_FLAG_VALUE == 1
5767                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5768                    && op1 == const0_rtx
5769                    && mode == GET_MODE (op0)
5770                    && (num_sign_bit_copies (op0, mode)
5771                        == GET_MODE_PRECISION (mode)))
5772             {
5773               op0 = expand_compound_operation (op0);
5774               return simplify_gen_unary (NEG, mode,
5775                                          gen_lowpart (mode, op0),
5776                                          mode);
5777             }
5778
5779           else if (STORE_FLAG_VALUE == 1
5780                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5781                    && op1 == const0_rtx
5782                    && mode == GET_MODE (op0)
5783                    && nonzero_bits (op0, mode) == 1)
5784             {
5785               op0 = expand_compound_operation (op0);
5786               return simplify_gen_binary (XOR, mode,
5787                                           gen_lowpart (mode, op0),
5788                                           const1_rtx);
5789             }
5790
5791           else if (STORE_FLAG_VALUE == 1
5792                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5793                    && op1 == const0_rtx
5794                    && mode == GET_MODE (op0)
5795                    && (num_sign_bit_copies (op0, mode)
5796                        == GET_MODE_PRECISION (mode)))
5797             {
5798               op0 = expand_compound_operation (op0);
5799               return plus_constant (mode, gen_lowpart (mode, op0), 1);
5800             }
5801
5802           /* If STORE_FLAG_VALUE is -1, we have cases similar to
5803              those above.  */
5804           if (in_cond)
5805             ;
5806
5807           else if (STORE_FLAG_VALUE == -1
5808                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5809                    && op1 == const0_rtx
5810                    && mode == GET_MODE (op0)
5811                    && (num_sign_bit_copies (op0, mode)
5812                        == GET_MODE_PRECISION (mode)))
5813             return gen_lowpart (mode,
5814                                 expand_compound_operation (op0));
5815
5816           else if (STORE_FLAG_VALUE == -1
5817                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5818                    && op1 == const0_rtx
5819                    && mode == GET_MODE (op0)
5820                    && nonzero_bits (op0, mode) == 1)
5821             {
5822               op0 = expand_compound_operation (op0);
5823               return simplify_gen_unary (NEG, mode,
5824                                          gen_lowpart (mode, op0),
5825                                          mode);
5826             }
5827
5828           else if (STORE_FLAG_VALUE == -1
5829                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5830                    && op1 == const0_rtx
5831                    && mode == GET_MODE (op0)
5832                    && (num_sign_bit_copies (op0, mode)
5833                        == GET_MODE_PRECISION (mode)))
5834             {
5835               op0 = expand_compound_operation (op0);
5836               return simplify_gen_unary (NOT, mode,
5837                                          gen_lowpart (mode, op0),
5838                                          mode);
5839             }
5840
5841           /* If X is 0/1, (eq X 0) is X-1.  */
5842           else if (STORE_FLAG_VALUE == -1
5843                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5844                    && op1 == const0_rtx
5845                    && mode == GET_MODE (op0)
5846                    && nonzero_bits (op0, mode) == 1)
5847             {
5848               op0 = expand_compound_operation (op0);
5849               return plus_constant (mode, gen_lowpart (mode, op0), -1);
5850             }
5851
5852           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5853              one bit that might be nonzero, we can convert (ne x 0) to
5854              (ashift x c) where C puts the bit in the sign bit.  Remove any
5855              AND with STORE_FLAG_VALUE when we are done, since we are only
5856              going to test the sign bit.  */
5857           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5858               && HWI_COMPUTABLE_MODE_P (mode)
5859               && val_signbit_p (mode, STORE_FLAG_VALUE)
5860               && op1 == const0_rtx
5861               && mode == GET_MODE (op0)
5862               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5863             {
5864               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5865                                         expand_compound_operation (op0),
5866                                         GET_MODE_PRECISION (mode) - 1 - i);
5867               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5868                 return XEXP (x, 0);
5869               else
5870                 return x;
5871             }
5872
5873           /* If the code changed, return a whole new comparison.
5874              We also need to avoid using SUBST in cases where
5875              simplify_comparison has widened a comparison with a CONST_INT,
5876              since in that case the wider CONST_INT may fail the sanity
5877              checks in do_SUBST.  */
5878           if (new_code != code
5879               || (CONST_INT_P (op1)
5880                   && GET_MODE (op0) != GET_MODE (XEXP (x, 0))
5881                   && GET_MODE (op0) != GET_MODE (XEXP (x, 1))))
5882             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5883
5884           /* Otherwise, keep this operation, but maybe change its operands.
5885              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
5886           SUBST (XEXP (x, 0), op0);
5887           SUBST (XEXP (x, 1), op1);
5888         }
5889       break;
5890
5891     case IF_THEN_ELSE:
5892       return simplify_if_then_else (x);
5893
5894     case ZERO_EXTRACT:
5895     case SIGN_EXTRACT:
5896     case ZERO_EXTEND:
5897     case SIGN_EXTEND:
5898       /* If we are processing SET_DEST, we are done.  */
5899       if (in_dest)
5900         return x;
5901
5902       return expand_compound_operation (x);
5903
5904     case SET:
5905       return simplify_set (x);
5906
5907     case AND:
5908     case IOR:
5909       return simplify_logical (x);
5910
5911     case ASHIFT:
5912     case LSHIFTRT:
5913     case ASHIFTRT:
5914     case ROTATE:
5915     case ROTATERT:
5916       /* If this is a shift by a constant amount, simplify it.  */
5917       if (CONST_INT_P (XEXP (x, 1)))
5918         return simplify_shift_const (x, code, mode, XEXP (x, 0),
5919                                      INTVAL (XEXP (x, 1)));
5920
5921       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5922         SUBST (XEXP (x, 1),
5923                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5924                               ((unsigned HOST_WIDE_INT) 1
5925                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5926                               - 1,
5927                               0));
5928       break;
5929
5930     default:
5931       break;
5932     }
5933
5934   return x;
5935 }
5936 \f
5937 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
5938
5939 static rtx
5940 simplify_if_then_else (rtx x)
5941 {
5942   machine_mode mode = GET_MODE (x);
5943   rtx cond = XEXP (x, 0);
5944   rtx true_rtx = XEXP (x, 1);
5945   rtx false_rtx = XEXP (x, 2);
5946   enum rtx_code true_code = GET_CODE (cond);
5947   int comparison_p = COMPARISON_P (cond);
5948   rtx temp;
5949   int i;
5950   enum rtx_code false_code;
5951   rtx reversed;
5952
5953   /* Simplify storing of the truth value.  */
5954   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
5955     return simplify_gen_relational (true_code, mode, VOIDmode,
5956                                     XEXP (cond, 0), XEXP (cond, 1));
5957
5958   /* Also when the truth value has to be reversed.  */
5959   if (comparison_p
5960       && true_rtx == const0_rtx && false_rtx == const_true_rtx
5961       && (reversed = reversed_comparison (cond, mode)))
5962     return reversed;
5963
5964   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
5965      in it is being compared against certain values.  Get the true and false
5966      comparisons and see if that says anything about the value of each arm.  */
5967
5968   if (comparison_p
5969       && ((false_code = reversed_comparison_code (cond, NULL))
5970           != UNKNOWN)
5971       && REG_P (XEXP (cond, 0)))
5972     {
5973       HOST_WIDE_INT nzb;
5974       rtx from = XEXP (cond, 0);
5975       rtx true_val = XEXP (cond, 1);
5976       rtx false_val = true_val;
5977       int swapped = 0;
5978
5979       /* If FALSE_CODE is EQ, swap the codes and arms.  */
5980
5981       if (false_code == EQ)
5982         {
5983           swapped = 1, true_code = EQ, false_code = NE;
5984           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
5985         }
5986
5987       /* If we are comparing against zero and the expression being tested has
5988          only a single bit that might be nonzero, that is its value when it is
5989          not equal to zero.  Similarly if it is known to be -1 or 0.  */
5990
5991       if (true_code == EQ && true_val == const0_rtx
5992           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
5993         {
5994           false_code = EQ;
5995           false_val = gen_int_mode (nzb, GET_MODE (from));
5996         }
5997       else if (true_code == EQ && true_val == const0_rtx
5998                && (num_sign_bit_copies (from, GET_MODE (from))
5999                    == GET_MODE_PRECISION (GET_MODE (from))))
6000         {
6001           false_code = EQ;
6002           false_val = constm1_rtx;
6003         }
6004
6005       /* Now simplify an arm if we know the value of the register in the
6006          branch and it is used in the arm.  Be careful due to the potential
6007          of locally-shared RTL.  */
6008
6009       if (reg_mentioned_p (from, true_rtx))
6010         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
6011                                       from, true_val),
6012                           pc_rtx, pc_rtx, 0, 0, 0);
6013       if (reg_mentioned_p (from, false_rtx))
6014         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
6015                                    from, false_val),
6016                            pc_rtx, pc_rtx, 0, 0, 0);
6017
6018       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
6019       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
6020
6021       true_rtx = XEXP (x, 1);
6022       false_rtx = XEXP (x, 2);
6023       true_code = GET_CODE (cond);
6024     }
6025
6026   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6027      reversed, do so to avoid needing two sets of patterns for
6028      subtract-and-branch insns.  Similarly if we have a constant in the true
6029      arm, the false arm is the same as the first operand of the comparison, or
6030      the false arm is more complicated than the true arm.  */
6031
6032   if (comparison_p
6033       && reversed_comparison_code (cond, NULL) != UNKNOWN
6034       && (true_rtx == pc_rtx
6035           || (CONSTANT_P (true_rtx)
6036               && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
6037           || true_rtx == const0_rtx
6038           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
6039           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
6040               && !OBJECT_P (false_rtx))
6041           || reg_mentioned_p (true_rtx, false_rtx)
6042           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
6043     {
6044       true_code = reversed_comparison_code (cond, NULL);
6045       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
6046       SUBST (XEXP (x, 1), false_rtx);
6047       SUBST (XEXP (x, 2), true_rtx);
6048
6049       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
6050       cond = XEXP (x, 0);
6051
6052       /* It is possible that the conditional has been simplified out.  */
6053       true_code = GET_CODE (cond);
6054       comparison_p = COMPARISON_P (cond);
6055     }
6056
6057   /* If the two arms are identical, we don't need the comparison.  */
6058
6059   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6060     return true_rtx;
6061
6062   /* Convert a == b ? b : a to "a".  */
6063   if (true_code == EQ && ! side_effects_p (cond)
6064       && !HONOR_NANS (mode)
6065       && rtx_equal_p (XEXP (cond, 0), false_rtx)
6066       && rtx_equal_p (XEXP (cond, 1), true_rtx))
6067     return false_rtx;
6068   else if (true_code == NE && ! side_effects_p (cond)
6069            && !HONOR_NANS (mode)
6070            && rtx_equal_p (XEXP (cond, 0), true_rtx)
6071            && rtx_equal_p (XEXP (cond, 1), false_rtx))
6072     return true_rtx;
6073
6074   /* Look for cases where we have (abs x) or (neg (abs X)).  */
6075
6076   if (GET_MODE_CLASS (mode) == MODE_INT
6077       && comparison_p
6078       && XEXP (cond, 1) == const0_rtx
6079       && GET_CODE (false_rtx) == NEG
6080       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6081       && rtx_equal_p (true_rtx, XEXP (cond, 0))
6082       && ! side_effects_p (true_rtx))
6083     switch (true_code)
6084       {
6085       case GT:
6086       case GE:
6087         return simplify_gen_unary (ABS, mode, true_rtx, mode);
6088       case LT:
6089       case LE:
6090         return
6091           simplify_gen_unary (NEG, mode,
6092                               simplify_gen_unary (ABS, mode, true_rtx, mode),
6093                               mode);
6094       default:
6095         break;
6096       }
6097
6098   /* Look for MIN or MAX.  */
6099
6100   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6101       && comparison_p
6102       && rtx_equal_p (XEXP (cond, 0), true_rtx)
6103       && rtx_equal_p (XEXP (cond, 1), false_rtx)
6104       && ! side_effects_p (cond))
6105     switch (true_code)
6106       {
6107       case GE:
6108       case GT:
6109         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6110       case LE:
6111       case LT:
6112         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6113       case GEU:
6114       case GTU:
6115         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6116       case LEU:
6117       case LTU:
6118         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6119       default:
6120         break;
6121       }
6122
6123   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6124      second operand is zero, this can be done as (OP Z (mult COND C2)) where
6125      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6126      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6127      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6128      neither 1 or -1, but it isn't worth checking for.  */
6129
6130   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6131       && comparison_p
6132       && GET_MODE_CLASS (mode) == MODE_INT
6133       && ! side_effects_p (x))
6134     {
6135       rtx t = make_compound_operation (true_rtx, SET);
6136       rtx f = make_compound_operation (false_rtx, SET);
6137       rtx cond_op0 = XEXP (cond, 0);
6138       rtx cond_op1 = XEXP (cond, 1);
6139       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6140       machine_mode m = mode;
6141       rtx z = 0, c1 = NULL_RTX;
6142
6143       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6144            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6145            || GET_CODE (t) == ASHIFT
6146            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6147           && rtx_equal_p (XEXP (t, 0), f))
6148         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6149
6150       /* If an identity-zero op is commutative, check whether there
6151          would be a match if we swapped the operands.  */
6152       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6153                 || GET_CODE (t) == XOR)
6154                && rtx_equal_p (XEXP (t, 1), f))
6155         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6156       else if (GET_CODE (t) == SIGN_EXTEND
6157                && (GET_CODE (XEXP (t, 0)) == PLUS
6158                    || GET_CODE (XEXP (t, 0)) == MINUS
6159                    || GET_CODE (XEXP (t, 0)) == IOR
6160                    || GET_CODE (XEXP (t, 0)) == XOR
6161                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6162                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6163                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6164                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6165                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6166                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6167                && (num_sign_bit_copies (f, GET_MODE (f))
6168                    > (unsigned int)
6169                      (GET_MODE_PRECISION (mode)
6170                       - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6171         {
6172           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6173           extend_op = SIGN_EXTEND;
6174           m = GET_MODE (XEXP (t, 0));
6175         }
6176       else if (GET_CODE (t) == SIGN_EXTEND
6177                && (GET_CODE (XEXP (t, 0)) == PLUS
6178                    || GET_CODE (XEXP (t, 0)) == IOR
6179                    || GET_CODE (XEXP (t, 0)) == XOR)
6180                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6181                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6182                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6183                && (num_sign_bit_copies (f, GET_MODE (f))
6184                    > (unsigned int)
6185                      (GET_MODE_PRECISION (mode)
6186                       - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6187         {
6188           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6189           extend_op = SIGN_EXTEND;
6190           m = GET_MODE (XEXP (t, 0));
6191         }
6192       else if (GET_CODE (t) == ZERO_EXTEND
6193                && (GET_CODE (XEXP (t, 0)) == PLUS
6194                    || GET_CODE (XEXP (t, 0)) == MINUS
6195                    || GET_CODE (XEXP (t, 0)) == IOR
6196                    || GET_CODE (XEXP (t, 0)) == XOR
6197                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6198                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6199                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6200                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6201                && HWI_COMPUTABLE_MODE_P (mode)
6202                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6203                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6204                && ((nonzero_bits (f, GET_MODE (f))
6205                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6206                    == 0))
6207         {
6208           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6209           extend_op = ZERO_EXTEND;
6210           m = GET_MODE (XEXP (t, 0));
6211         }
6212       else if (GET_CODE (t) == ZERO_EXTEND
6213                && (GET_CODE (XEXP (t, 0)) == PLUS
6214                    || GET_CODE (XEXP (t, 0)) == IOR
6215                    || GET_CODE (XEXP (t, 0)) == XOR)
6216                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6217                && HWI_COMPUTABLE_MODE_P (mode)
6218                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6219                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6220                && ((nonzero_bits (f, GET_MODE (f))
6221                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6222                    == 0))
6223         {
6224           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6225           extend_op = ZERO_EXTEND;
6226           m = GET_MODE (XEXP (t, 0));
6227         }
6228
6229       if (z)
6230         {
6231           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6232                                                  cond_op0, cond_op1),
6233                         pc_rtx, pc_rtx, 0, 0, 0);
6234           temp = simplify_gen_binary (MULT, m, temp,
6235                                       simplify_gen_binary (MULT, m, c1,
6236                                                            const_true_rtx));
6237           temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
6238           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6239
6240           if (extend_op != UNKNOWN)
6241             temp = simplify_gen_unary (extend_op, mode, temp, m);
6242
6243           return temp;
6244         }
6245     }
6246
6247   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6248      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6249      negation of a single bit, we can convert this operation to a shift.  We
6250      can actually do this more generally, but it doesn't seem worth it.  */
6251
6252   if (true_code == NE && XEXP (cond, 1) == const0_rtx
6253       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6254       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6255            && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6256           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6257                == GET_MODE_PRECISION (mode))
6258               && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6259     return
6260       simplify_shift_const (NULL_RTX, ASHIFT, mode,
6261                             gen_lowpart (mode, XEXP (cond, 0)), i);
6262
6263   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
6264   if (true_code == NE && XEXP (cond, 1) == const0_rtx
6265       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6266       && GET_MODE (XEXP (cond, 0)) == mode
6267       && (UINTVAL (true_rtx) & GET_MODE_MASK (mode))
6268           == nonzero_bits (XEXP (cond, 0), mode)
6269       && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6270     return XEXP (cond, 0);
6271
6272   return x;
6273 }
6274 \f
6275 /* Simplify X, a SET expression.  Return the new expression.  */
6276
6277 static rtx
6278 simplify_set (rtx x)
6279 {
6280   rtx src = SET_SRC (x);
6281   rtx dest = SET_DEST (x);
6282   machine_mode mode
6283     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6284   rtx_insn *other_insn;
6285   rtx *cc_use;
6286
6287   /* (set (pc) (return)) gets written as (return).  */
6288   if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6289     return src;
6290
6291   /* Now that we know for sure which bits of SRC we are using, see if we can
6292      simplify the expression for the object knowing that we only need the
6293      low-order bits.  */
6294
6295   if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6296     {
6297       src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
6298       SUBST (SET_SRC (x), src);
6299     }
6300
6301   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6302      the comparison result and try to simplify it unless we already have used
6303      undobuf.other_insn.  */
6304   if ((GET_MODE_CLASS (mode) == MODE_CC
6305        || GET_CODE (src) == COMPARE
6306        || CC0_P (dest))
6307       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6308       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6309       && COMPARISON_P (*cc_use)
6310       && rtx_equal_p (XEXP (*cc_use, 0), dest))
6311     {
6312       enum rtx_code old_code = GET_CODE (*cc_use);
6313       enum rtx_code new_code;
6314       rtx op0, op1, tmp;
6315       int other_changed = 0;
6316       rtx inner_compare = NULL_RTX;
6317       machine_mode compare_mode = GET_MODE (dest);
6318
6319       if (GET_CODE (src) == COMPARE)
6320         {
6321           op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6322           if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6323             {
6324               inner_compare = op0;
6325               op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6326             }
6327         }
6328       else
6329         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6330
6331       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6332                                            op0, op1);
6333       if (!tmp)
6334         new_code = old_code;
6335       else if (!CONSTANT_P (tmp))
6336         {
6337           new_code = GET_CODE (tmp);
6338           op0 = XEXP (tmp, 0);
6339           op1 = XEXP (tmp, 1);
6340         }
6341       else
6342         {
6343           rtx pat = PATTERN (other_insn);
6344           undobuf.other_insn = other_insn;
6345           SUBST (*cc_use, tmp);
6346
6347           /* Attempt to simplify CC user.  */
6348           if (GET_CODE (pat) == SET)
6349             {
6350               rtx new_rtx = simplify_rtx (SET_SRC (pat));
6351               if (new_rtx != NULL_RTX)
6352                 SUBST (SET_SRC (pat), new_rtx);
6353             }
6354
6355           /* Convert X into a no-op move.  */
6356           SUBST (SET_DEST (x), pc_rtx);
6357           SUBST (SET_SRC (x), pc_rtx);
6358           return x;
6359         }
6360
6361       /* Simplify our comparison, if possible.  */
6362       new_code = simplify_comparison (new_code, &op0, &op1);
6363
6364 #ifdef SELECT_CC_MODE
6365       /* If this machine has CC modes other than CCmode, check to see if we
6366          need to use a different CC mode here.  */
6367       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6368         compare_mode = GET_MODE (op0);
6369       else if (inner_compare
6370                && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6371                && new_code == old_code
6372                && op0 == XEXP (inner_compare, 0)
6373                && op1 == XEXP (inner_compare, 1))
6374         compare_mode = GET_MODE (inner_compare);
6375       else
6376         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6377
6378 #ifndef HAVE_cc0
6379       /* If the mode changed, we have to change SET_DEST, the mode in the
6380          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
6381          a hard register, just build new versions with the proper mode.  If it
6382          is a pseudo, we lose unless it is only time we set the pseudo, in
6383          which case we can safely change its mode.  */
6384       if (compare_mode != GET_MODE (dest))
6385         {
6386           if (can_change_dest_mode (dest, 0, compare_mode))
6387             {
6388               unsigned int regno = REGNO (dest);
6389               rtx new_dest;
6390
6391               if (regno < FIRST_PSEUDO_REGISTER)
6392                 new_dest = gen_rtx_REG (compare_mode, regno);
6393               else
6394                 {
6395                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6396                   new_dest = regno_reg_rtx[regno];
6397                 }
6398
6399               SUBST (SET_DEST (x), new_dest);
6400               SUBST (XEXP (*cc_use, 0), new_dest);
6401               other_changed = 1;
6402
6403               dest = new_dest;
6404             }
6405         }
6406 #endif  /* cc0 */
6407 #endif  /* SELECT_CC_MODE */
6408
6409       /* If the code changed, we have to build a new comparison in
6410          undobuf.other_insn.  */
6411       if (new_code != old_code)
6412         {
6413           int other_changed_previously = other_changed;
6414           unsigned HOST_WIDE_INT mask;
6415           rtx old_cc_use = *cc_use;
6416
6417           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6418                                           dest, const0_rtx));
6419           other_changed = 1;
6420
6421           /* If the only change we made was to change an EQ into an NE or
6422              vice versa, OP0 has only one bit that might be nonzero, and OP1
6423              is zero, check if changing the user of the condition code will
6424              produce a valid insn.  If it won't, we can keep the original code
6425              in that insn by surrounding our operation with an XOR.  */
6426
6427           if (((old_code == NE && new_code == EQ)
6428                || (old_code == EQ && new_code == NE))
6429               && ! other_changed_previously && op1 == const0_rtx
6430               && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
6431               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6432             {
6433               rtx pat = PATTERN (other_insn), note = 0;
6434
6435               if ((recog_for_combine (&pat, other_insn, &note) < 0
6436                    && ! check_asm_operands (pat)))
6437                 {
6438                   *cc_use = old_cc_use;
6439                   other_changed = 0;
6440
6441                   op0 = simplify_gen_binary (XOR, GET_MODE (op0), op0,
6442                                              gen_int_mode (mask,
6443                                                            GET_MODE (op0)));
6444                 }
6445             }
6446         }
6447
6448       if (other_changed)
6449         undobuf.other_insn = other_insn;
6450
6451       /* Otherwise, if we didn't previously have a COMPARE in the
6452          correct mode, we need one.  */
6453       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6454         {
6455           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6456           src = SET_SRC (x);
6457         }
6458       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6459         {
6460           SUBST (SET_SRC (x), op0);
6461           src = SET_SRC (x);
6462         }
6463       /* Otherwise, update the COMPARE if needed.  */
6464       else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6465         {
6466           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6467           src = SET_SRC (x);
6468         }
6469     }
6470   else
6471     {
6472       /* Get SET_SRC in a form where we have placed back any
6473          compound expressions.  Then do the checks below.  */
6474       src = make_compound_operation (src, SET);
6475       SUBST (SET_SRC (x), src);
6476     }
6477
6478   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6479      and X being a REG or (subreg (reg)), we may be able to convert this to
6480      (set (subreg:m2 x) (op)).
6481
6482      We can always do this if M1 is narrower than M2 because that means that
6483      we only care about the low bits of the result.
6484
6485      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6486      perform a narrower operation than requested since the high-order bits will
6487      be undefined.  On machine where it is defined, this transformation is safe
6488      as long as M1 and M2 have the same number of words.  */
6489
6490   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6491       && !OBJECT_P (SUBREG_REG (src))
6492       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6493            / UNITS_PER_WORD)
6494           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6495                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6496 #ifndef WORD_REGISTER_OPERATIONS
6497       && (GET_MODE_SIZE (GET_MODE (src))
6498         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6499 #endif
6500 #ifdef CANNOT_CHANGE_MODE_CLASS
6501       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6502             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6503                                          GET_MODE (SUBREG_REG (src)),
6504                                          GET_MODE (src)))
6505 #endif
6506       && (REG_P (dest)
6507           || (GET_CODE (dest) == SUBREG
6508               && REG_P (SUBREG_REG (dest)))))
6509     {
6510       SUBST (SET_DEST (x),
6511              gen_lowpart (GET_MODE (SUBREG_REG (src)),
6512                                       dest));
6513       SUBST (SET_SRC (x), SUBREG_REG (src));
6514
6515       src = SET_SRC (x), dest = SET_DEST (x);
6516     }
6517
6518 #ifdef HAVE_cc0
6519   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6520      in SRC.  */
6521   if (dest == cc0_rtx
6522       && GET_CODE (src) == SUBREG
6523       && subreg_lowpart_p (src)
6524       && (GET_MODE_PRECISION (GET_MODE (src))
6525           < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src)))))
6526     {
6527       rtx inner = SUBREG_REG (src);
6528       machine_mode inner_mode = GET_MODE (inner);
6529
6530       /* Here we make sure that we don't have a sign bit on.  */
6531       if (val_signbit_known_clear_p (GET_MODE (src),
6532                                      nonzero_bits (inner, inner_mode)))
6533         {
6534           SUBST (SET_SRC (x), inner);
6535           src = SET_SRC (x);
6536         }
6537     }
6538 #endif
6539
6540 #ifdef LOAD_EXTEND_OP
6541   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6542      would require a paradoxical subreg.  Replace the subreg with a
6543      zero_extend to avoid the reload that would otherwise be required.  */
6544
6545   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6546       && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6547       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6548       && SUBREG_BYTE (src) == 0
6549       && paradoxical_subreg_p (src)
6550       && MEM_P (SUBREG_REG (src)))
6551     {
6552       SUBST (SET_SRC (x),
6553              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6554                             GET_MODE (src), SUBREG_REG (src)));
6555
6556       src = SET_SRC (x);
6557     }
6558 #endif
6559
6560   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6561      are comparing an item known to be 0 or -1 against 0, use a logical
6562      operation instead. Check for one of the arms being an IOR of the other
6563      arm with some value.  We compute three terms to be IOR'ed together.  In
6564      practice, at most two will be nonzero.  Then we do the IOR's.  */
6565
6566   if (GET_CODE (dest) != PC
6567       && GET_CODE (src) == IF_THEN_ELSE
6568       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6569       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6570       && XEXP (XEXP (src, 0), 1) == const0_rtx
6571       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6572 #ifdef HAVE_conditional_move
6573       && ! can_conditionally_move_p (GET_MODE (src))
6574 #endif
6575       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6576                                GET_MODE (XEXP (XEXP (src, 0), 0)))
6577           == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src, 0), 0))))
6578       && ! side_effects_p (src))
6579     {
6580       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6581                       ? XEXP (src, 1) : XEXP (src, 2));
6582       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6583                    ? XEXP (src, 2) : XEXP (src, 1));
6584       rtx term1 = const0_rtx, term2, term3;
6585
6586       if (GET_CODE (true_rtx) == IOR
6587           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6588         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6589       else if (GET_CODE (true_rtx) == IOR
6590                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6591         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6592       else if (GET_CODE (false_rtx) == IOR
6593                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6594         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6595       else if (GET_CODE (false_rtx) == IOR
6596                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6597         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6598
6599       term2 = simplify_gen_binary (AND, GET_MODE (src),
6600                                    XEXP (XEXP (src, 0), 0), true_rtx);
6601       term3 = simplify_gen_binary (AND, GET_MODE (src),
6602                                    simplify_gen_unary (NOT, GET_MODE (src),
6603                                                        XEXP (XEXP (src, 0), 0),
6604                                                        GET_MODE (src)),
6605                                    false_rtx);
6606
6607       SUBST (SET_SRC (x),
6608              simplify_gen_binary (IOR, GET_MODE (src),
6609                                   simplify_gen_binary (IOR, GET_MODE (src),
6610                                                        term1, term2),
6611                                   term3));
6612
6613       src = SET_SRC (x);
6614     }
6615
6616   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6617      whole thing fail.  */
6618   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6619     return src;
6620   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6621     return dest;
6622   else
6623     /* Convert this into a field assignment operation, if possible.  */
6624     return make_field_assignment (x);
6625 }
6626 \f
6627 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6628    result.  */
6629
6630 static rtx
6631 simplify_logical (rtx x)
6632 {
6633   machine_mode mode = GET_MODE (x);
6634   rtx op0 = XEXP (x, 0);
6635   rtx op1 = XEXP (x, 1);
6636
6637   switch (GET_CODE (x))
6638     {
6639     case AND:
6640       /* We can call simplify_and_const_int only if we don't lose
6641          any (sign) bits when converting INTVAL (op1) to
6642          "unsigned HOST_WIDE_INT".  */
6643       if (CONST_INT_P (op1)
6644           && (HWI_COMPUTABLE_MODE_P (mode)
6645               || INTVAL (op1) > 0))
6646         {
6647           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6648           if (GET_CODE (x) != AND)
6649             return x;
6650
6651           op0 = XEXP (x, 0);
6652           op1 = XEXP (x, 1);
6653         }
6654
6655       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6656          apply the distributive law and then the inverse distributive
6657          law to see if things simplify.  */
6658       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6659         {
6660           rtx result = distribute_and_simplify_rtx (x, 0);
6661           if (result)
6662             return result;
6663         }
6664       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6665         {
6666           rtx result = distribute_and_simplify_rtx (x, 1);
6667           if (result)
6668             return result;
6669         }
6670       break;
6671
6672     case IOR:
6673       /* If we have (ior (and A B) C), apply the distributive law and then
6674          the inverse distributive law to see if things simplify.  */
6675
6676       if (GET_CODE (op0) == AND)
6677         {
6678           rtx result = distribute_and_simplify_rtx (x, 0);
6679           if (result)
6680             return result;
6681         }
6682
6683       if (GET_CODE (op1) == AND)
6684         {
6685           rtx result = distribute_and_simplify_rtx (x, 1);
6686           if (result)
6687             return result;
6688         }
6689       break;
6690
6691     default:
6692       gcc_unreachable ();
6693     }
6694
6695   return x;
6696 }
6697 \f
6698 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6699    operations" because they can be replaced with two more basic operations.
6700    ZERO_EXTEND is also considered "compound" because it can be replaced with
6701    an AND operation, which is simpler, though only one operation.
6702
6703    The function expand_compound_operation is called with an rtx expression
6704    and will convert it to the appropriate shifts and AND operations,
6705    simplifying at each stage.
6706
6707    The function make_compound_operation is called to convert an expression
6708    consisting of shifts and ANDs into the equivalent compound expression.
6709    It is the inverse of this function, loosely speaking.  */
6710
6711 static rtx
6712 expand_compound_operation (rtx x)
6713 {
6714   unsigned HOST_WIDE_INT pos = 0, len;
6715   int unsignedp = 0;
6716   unsigned int modewidth;
6717   rtx tem;
6718
6719   switch (GET_CODE (x))
6720     {
6721     case ZERO_EXTEND:
6722       unsignedp = 1;
6723     case SIGN_EXTEND:
6724       /* We can't necessarily use a const_int for a multiword mode;
6725          it depends on implicitly extending the value.
6726          Since we don't know the right way to extend it,
6727          we can't tell whether the implicit way is right.
6728
6729          Even for a mode that is no wider than a const_int,
6730          we can't win, because we need to sign extend one of its bits through
6731          the rest of it, and we don't know which bit.  */
6732       if (CONST_INT_P (XEXP (x, 0)))
6733         return x;
6734
6735       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6736          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
6737          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6738          reloaded. If not for that, MEM's would very rarely be safe.
6739
6740          Reject MODEs bigger than a word, because we might not be able
6741          to reference a two-register group starting with an arbitrary register
6742          (and currently gen_lowpart might crash for a SUBREG).  */
6743
6744       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6745         return x;
6746
6747       /* Reject MODEs that aren't scalar integers because turning vector
6748          or complex modes into shifts causes problems.  */
6749
6750       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6751         return x;
6752
6753       len = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)));
6754       /* If the inner object has VOIDmode (the only way this can happen
6755          is if it is an ASM_OPERANDS), we can't do anything since we don't
6756          know how much masking to do.  */
6757       if (len == 0)
6758         return x;
6759
6760       break;
6761
6762     case ZERO_EXTRACT:
6763       unsignedp = 1;
6764
6765       /* ... fall through ...  */
6766
6767     case SIGN_EXTRACT:
6768       /* If the operand is a CLOBBER, just return it.  */
6769       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6770         return XEXP (x, 0);
6771
6772       if (!CONST_INT_P (XEXP (x, 1))
6773           || !CONST_INT_P (XEXP (x, 2))
6774           || GET_MODE (XEXP (x, 0)) == VOIDmode)
6775         return x;
6776
6777       /* Reject MODEs that aren't scalar integers because turning vector
6778          or complex modes into shifts causes problems.  */
6779
6780       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6781         return x;
6782
6783       len = INTVAL (XEXP (x, 1));
6784       pos = INTVAL (XEXP (x, 2));
6785
6786       /* This should stay within the object being extracted, fail otherwise.  */
6787       if (len + pos > GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))))
6788         return x;
6789
6790       if (BITS_BIG_ENDIAN)
6791         pos = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) - len - pos;
6792
6793       break;
6794
6795     default:
6796       return x;
6797     }
6798   /* Convert sign extension to zero extension, if we know that the high
6799      bit is not set, as this is easier to optimize.  It will be converted
6800      back to cheaper alternative in make_extraction.  */
6801   if (GET_CODE (x) == SIGN_EXTEND
6802       && (HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6803           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6804                 & ~(((unsigned HOST_WIDE_INT)
6805                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6806                      >> 1))
6807                == 0)))
6808     {
6809       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6810       rtx temp2 = expand_compound_operation (temp);
6811
6812       /* Make sure this is a profitable operation.  */
6813       if (set_src_cost (x, optimize_this_for_speed_p)
6814           > set_src_cost (temp2, optimize_this_for_speed_p))
6815        return temp2;
6816       else if (set_src_cost (x, optimize_this_for_speed_p)
6817                > set_src_cost (temp, optimize_this_for_speed_p))
6818        return temp;
6819       else
6820        return x;
6821     }
6822
6823   /* We can optimize some special cases of ZERO_EXTEND.  */
6824   if (GET_CODE (x) == ZERO_EXTEND)
6825     {
6826       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6827          know that the last value didn't have any inappropriate bits
6828          set.  */
6829       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6830           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6831           && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6832           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6833               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6834         return XEXP (XEXP (x, 0), 0);
6835
6836       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6837       if (GET_CODE (XEXP (x, 0)) == SUBREG
6838           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6839           && subreg_lowpart_p (XEXP (x, 0))
6840           && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6841           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6842               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6843         return SUBREG_REG (XEXP (x, 0));
6844
6845       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6846          is a comparison and STORE_FLAG_VALUE permits.  This is like
6847          the first case, but it works even when GET_MODE (x) is larger
6848          than HOST_WIDE_INT.  */
6849       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6850           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6851           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6852           && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6853               <= HOST_BITS_PER_WIDE_INT)
6854           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6855         return XEXP (XEXP (x, 0), 0);
6856
6857       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6858       if (GET_CODE (XEXP (x, 0)) == SUBREG
6859           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6860           && subreg_lowpart_p (XEXP (x, 0))
6861           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6862           && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6863               <= HOST_BITS_PER_WIDE_INT)
6864           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6865         return SUBREG_REG (XEXP (x, 0));
6866
6867     }
6868
6869   /* If we reach here, we want to return a pair of shifts.  The inner
6870      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
6871      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
6872      logical depending on the value of UNSIGNEDP.
6873
6874      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6875      converted into an AND of a shift.
6876
6877      We must check for the case where the left shift would have a negative
6878      count.  This can happen in a case like (x >> 31) & 255 on machines
6879      that can't shift by a constant.  On those machines, we would first
6880      combine the shift with the AND to produce a variable-position
6881      extraction.  Then the constant of 31 would be substituted in
6882      to produce such a position.  */
6883
6884   modewidth = GET_MODE_PRECISION (GET_MODE (x));
6885   if (modewidth >= pos + len)
6886     {
6887       machine_mode mode = GET_MODE (x);
6888       tem = gen_lowpart (mode, XEXP (x, 0));
6889       if (!tem || GET_CODE (tem) == CLOBBER)
6890         return x;
6891       tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6892                                   tem, modewidth - pos - len);
6893       tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6894                                   mode, tem, modewidth - len);
6895     }
6896   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6897     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6898                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
6899                                                         GET_MODE (x),
6900                                                         XEXP (x, 0), pos),
6901                                   ((unsigned HOST_WIDE_INT) 1 << len) - 1);
6902   else
6903     /* Any other cases we can't handle.  */
6904     return x;
6905
6906   /* If we couldn't do this for some reason, return the original
6907      expression.  */
6908   if (GET_CODE (tem) == CLOBBER)
6909     return x;
6910
6911   return tem;
6912 }
6913 \f
6914 /* X is a SET which contains an assignment of one object into
6915    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6916    or certain SUBREGS). If possible, convert it into a series of
6917    logical operations.
6918
6919    We half-heartedly support variable positions, but do not at all
6920    support variable lengths.  */
6921
6922 static const_rtx
6923 expand_field_assignment (const_rtx x)
6924 {
6925   rtx inner;
6926   rtx pos;                      /* Always counts from low bit.  */
6927   int len;
6928   rtx mask, cleared, masked;
6929   machine_mode compute_mode;
6930
6931   /* Loop until we find something we can't simplify.  */
6932   while (1)
6933     {
6934       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6935           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6936         {
6937           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6938           len = GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0)));
6939           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6940         }
6941       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6942                && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6943         {
6944           inner = XEXP (SET_DEST (x), 0);
6945           len = INTVAL (XEXP (SET_DEST (x), 1));
6946           pos = XEXP (SET_DEST (x), 2);
6947
6948           /* A constant position should stay within the width of INNER.  */
6949           if (CONST_INT_P (pos)
6950               && INTVAL (pos) + len > GET_MODE_PRECISION (GET_MODE (inner)))
6951             break;
6952
6953           if (BITS_BIG_ENDIAN)
6954             {
6955               if (CONST_INT_P (pos))
6956                 pos = GEN_INT (GET_MODE_PRECISION (GET_MODE (inner)) - len
6957                                - INTVAL (pos));
6958               else if (GET_CODE (pos) == MINUS
6959                        && CONST_INT_P (XEXP (pos, 1))
6960                        && (INTVAL (XEXP (pos, 1))
6961                            == GET_MODE_PRECISION (GET_MODE (inner)) - len))
6962                 /* If position is ADJUST - X, new position is X.  */
6963                 pos = XEXP (pos, 0);
6964               else
6965                 {
6966                   HOST_WIDE_INT prec = GET_MODE_PRECISION (GET_MODE (inner));
6967                   pos = simplify_gen_binary (MINUS, GET_MODE (pos),
6968                                              gen_int_mode (prec - len,
6969                                                            GET_MODE (pos)),
6970                                              pos);
6971                 }
6972             }
6973         }
6974
6975       /* A SUBREG between two modes that occupy the same numbers of words
6976          can be done by moving the SUBREG to the source.  */
6977       else if (GET_CODE (SET_DEST (x)) == SUBREG
6978                /* We need SUBREGs to compute nonzero_bits properly.  */
6979                && nonzero_sign_valid
6980                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
6981                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
6982                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
6983                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
6984         {
6985           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
6986                            gen_lowpart
6987                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
6988                             SET_SRC (x)));
6989           continue;
6990         }
6991       else
6992         break;
6993
6994       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
6995         inner = SUBREG_REG (inner);
6996
6997       compute_mode = GET_MODE (inner);
6998
6999       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
7000       if (! SCALAR_INT_MODE_P (compute_mode))
7001         {
7002           machine_mode imode;
7003
7004           /* Don't do anything for vector or complex integral types.  */
7005           if (! FLOAT_MODE_P (compute_mode))
7006             break;
7007
7008           /* Try to find an integral mode to pun with.  */
7009           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
7010           if (imode == BLKmode)
7011             break;
7012
7013           compute_mode = imode;
7014           inner = gen_lowpart (imode, inner);
7015         }
7016
7017       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
7018       if (len >= HOST_BITS_PER_WIDE_INT)
7019         break;
7020
7021       /* Now compute the equivalent expression.  Make a copy of INNER
7022          for the SET_DEST in case it is a MEM into which we will substitute;
7023          we don't want shared RTL in that case.  */
7024       mask = gen_int_mode (((unsigned HOST_WIDE_INT) 1 << len) - 1,
7025                            compute_mode);
7026       cleared = simplify_gen_binary (AND, compute_mode,
7027                                      simplify_gen_unary (NOT, compute_mode,
7028                                        simplify_gen_binary (ASHIFT,
7029                                                             compute_mode,
7030                                                             mask, pos),
7031                                        compute_mode),
7032                                      inner);
7033       masked = simplify_gen_binary (ASHIFT, compute_mode,
7034                                     simplify_gen_binary (
7035                                       AND, compute_mode,
7036                                       gen_lowpart (compute_mode, SET_SRC (x)),
7037                                       mask),
7038                                     pos);
7039
7040       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
7041                        simplify_gen_binary (IOR, compute_mode,
7042                                             cleared, masked));
7043     }
7044
7045   return x;
7046 }
7047 \f
7048 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
7049    it is an RTX that represents the (variable) starting position; otherwise,
7050    POS is the (constant) starting bit position.  Both are counted from the LSB.
7051
7052    UNSIGNEDP is nonzero for an unsigned reference and zero for a signed one.
7053
7054    IN_DEST is nonzero if this is a reference in the destination of a SET.
7055    This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
7056    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7057    be used.
7058
7059    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
7060    ZERO_EXTRACT should be built even for bits starting at bit 0.
7061
7062    MODE is the desired mode of the result (if IN_DEST == 0).
7063
7064    The result is an RTX for the extraction or NULL_RTX if the target
7065    can't handle it.  */
7066
7067 static rtx
7068 make_extraction (machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7069                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
7070                  int in_dest, int in_compare)
7071 {
7072   /* This mode describes the size of the storage area
7073      to fetch the overall value from.  Within that, we
7074      ignore the POS lowest bits, etc.  */
7075   machine_mode is_mode = GET_MODE (inner);
7076   machine_mode inner_mode;
7077   machine_mode wanted_inner_mode;
7078   machine_mode wanted_inner_reg_mode = word_mode;
7079   machine_mode pos_mode = word_mode;
7080   machine_mode extraction_mode = word_mode;
7081   machine_mode tmode = mode_for_size (len, MODE_INT, 1);
7082   rtx new_rtx = 0;
7083   rtx orig_pos_rtx = pos_rtx;
7084   HOST_WIDE_INT orig_pos;
7085
7086   if (pos_rtx && CONST_INT_P (pos_rtx))
7087     pos = INTVAL (pos_rtx), pos_rtx = 0;
7088
7089   if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7090     {
7091       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7092          consider just the QI as the memory to extract from.
7093          The subreg adds or removes high bits; its mode is
7094          irrelevant to the meaning of this extraction,
7095          since POS and LEN count from the lsb.  */
7096       if (MEM_P (SUBREG_REG (inner)))
7097         is_mode = GET_MODE (SUBREG_REG (inner));
7098       inner = SUBREG_REG (inner);
7099     }
7100   else if (GET_CODE (inner) == ASHIFT
7101            && CONST_INT_P (XEXP (inner, 1))
7102            && pos_rtx == 0 && pos == 0
7103            && len > UINTVAL (XEXP (inner, 1)))
7104     {
7105       /* We're extracting the least significant bits of an rtx
7106          (ashift X (const_int C)), where LEN > C.  Extract the
7107          least significant (LEN - C) bits of X, giving an rtx
7108          whose mode is MODE, then shift it left C times.  */
7109       new_rtx = make_extraction (mode, XEXP (inner, 0),
7110                              0, 0, len - INTVAL (XEXP (inner, 1)),
7111                              unsignedp, in_dest, in_compare);
7112       if (new_rtx != 0)
7113         return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7114     }
7115   else if (GET_CODE (inner) == TRUNCATE)
7116     inner = XEXP (inner, 0);
7117
7118   inner_mode = GET_MODE (inner);
7119
7120   /* See if this can be done without an extraction.  We never can if the
7121      width of the field is not the same as that of some integer mode. For
7122      registers, we can only avoid the extraction if the position is at the
7123      low-order bit and this is either not in the destination or we have the
7124      appropriate STRICT_LOW_PART operation available.
7125
7126      For MEM, we can avoid an extract if the field starts on an appropriate
7127      boundary and we can change the mode of the memory reference.  */
7128
7129   if (tmode != BLKmode
7130       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7131            && !MEM_P (inner)
7132            && (inner_mode == tmode
7133                || !REG_P (inner)
7134                || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7135                || reg_truncated_to_mode (tmode, inner))
7136            && (! in_dest
7137                || (REG_P (inner)
7138                    && have_insn_for (STRICT_LOW_PART, tmode))))
7139           || (MEM_P (inner) && pos_rtx == 0
7140               && (pos
7141                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7142                      : BITS_PER_UNIT)) == 0
7143               /* We can't do this if we are widening INNER_MODE (it
7144                  may not be aligned, for one thing).  */
7145               && GET_MODE_PRECISION (inner_mode) >= GET_MODE_PRECISION (tmode)
7146               && (inner_mode == tmode
7147                   || (! mode_dependent_address_p (XEXP (inner, 0),
7148                                                   MEM_ADDR_SPACE (inner))
7149                       && ! MEM_VOLATILE_P (inner))))))
7150     {
7151       /* If INNER is a MEM, make a new MEM that encompasses just the desired
7152          field.  If the original and current mode are the same, we need not
7153          adjust the offset.  Otherwise, we do if bytes big endian.
7154
7155          If INNER is not a MEM, get a piece consisting of just the field
7156          of interest (in this case POS % BITS_PER_WORD must be 0).  */
7157
7158       if (MEM_P (inner))
7159         {
7160           HOST_WIDE_INT offset;
7161
7162           /* POS counts from lsb, but make OFFSET count in memory order.  */
7163           if (BYTES_BIG_ENDIAN)
7164             offset = (GET_MODE_PRECISION (is_mode) - len - pos) / BITS_PER_UNIT;
7165           else
7166             offset = pos / BITS_PER_UNIT;
7167
7168           new_rtx = adjust_address_nv (inner, tmode, offset);
7169         }
7170       else if (REG_P (inner))
7171         {
7172           if (tmode != inner_mode)
7173             {
7174               /* We can't call gen_lowpart in a DEST since we
7175                  always want a SUBREG (see below) and it would sometimes
7176                  return a new hard register.  */
7177               if (pos || in_dest)
7178                 {
7179                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7180
7181                   if (WORDS_BIG_ENDIAN
7182                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7183                     final_word = ((GET_MODE_SIZE (inner_mode)
7184                                    - GET_MODE_SIZE (tmode))
7185                                   / UNITS_PER_WORD) - final_word;
7186
7187                   final_word *= UNITS_PER_WORD;
7188                   if (BYTES_BIG_ENDIAN &&
7189                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7190                     final_word += (GET_MODE_SIZE (inner_mode)
7191                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7192
7193                   /* Avoid creating invalid subregs, for example when
7194                      simplifying (x>>32)&255.  */
7195                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
7196                     return NULL_RTX;
7197
7198                   new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7199                 }
7200               else
7201                 new_rtx = gen_lowpart (tmode, inner);
7202             }
7203           else
7204             new_rtx = inner;
7205         }
7206       else
7207         new_rtx = force_to_mode (inner, tmode,
7208                              len >= HOST_BITS_PER_WIDE_INT
7209                              ? ~(unsigned HOST_WIDE_INT) 0
7210                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7211                              0);
7212
7213       /* If this extraction is going into the destination of a SET,
7214          make a STRICT_LOW_PART unless we made a MEM.  */
7215
7216       if (in_dest)
7217         return (MEM_P (new_rtx) ? new_rtx
7218                 : (GET_CODE (new_rtx) != SUBREG
7219                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
7220                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7221
7222       if (mode == tmode)
7223         return new_rtx;
7224
7225       if (CONST_SCALAR_INT_P (new_rtx))
7226         return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7227                                          mode, new_rtx, tmode);
7228
7229       /* If we know that no extraneous bits are set, and that the high
7230          bit is not set, convert the extraction to the cheaper of
7231          sign and zero extension, that are equivalent in these cases.  */
7232       if (flag_expensive_optimizations
7233           && (HWI_COMPUTABLE_MODE_P (tmode)
7234               && ((nonzero_bits (new_rtx, tmode)
7235                    & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7236                   == 0)))
7237         {
7238           rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7239           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7240
7241           /* Prefer ZERO_EXTENSION, since it gives more information to
7242              backends.  */
7243           if (set_src_cost (temp, optimize_this_for_speed_p)
7244               <= set_src_cost (temp1, optimize_this_for_speed_p))
7245             return temp;
7246           return temp1;
7247         }
7248
7249       /* Otherwise, sign- or zero-extend unless we already are in the
7250          proper mode.  */
7251
7252       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7253                              mode, new_rtx));
7254     }
7255
7256   /* Unless this is a COMPARE or we have a funny memory reference,
7257      don't do anything with zero-extending field extracts starting at
7258      the low-order bit since they are simple AND operations.  */
7259   if (pos_rtx == 0 && pos == 0 && ! in_dest
7260       && ! in_compare && unsignedp)
7261     return 0;
7262
7263   /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7264      if the position is not a constant and the length is not 1.  In all
7265      other cases, we would only be going outside our object in cases when
7266      an original shift would have been undefined.  */
7267   if (MEM_P (inner)
7268       && ((pos_rtx == 0 && pos + len > GET_MODE_PRECISION (is_mode))
7269           || (pos_rtx != 0 && len != 1)))
7270     return 0;
7271
7272   enum extraction_pattern pattern = (in_dest ? EP_insv
7273                                      : unsignedp ? EP_extzv : EP_extv);
7274
7275   /* If INNER is not from memory, we want it to have the mode of a register
7276      extraction pattern's structure operand, or word_mode if there is no
7277      such pattern.  The same applies to extraction_mode and pos_mode
7278      and their respective operands.
7279
7280      For memory, assume that the desired extraction_mode and pos_mode
7281      are the same as for a register operation, since at present we don't
7282      have named patterns for aligned memory structures.  */
7283   struct extraction_insn insn;
7284   if (get_best_reg_extraction_insn (&insn, pattern,
7285                                     GET_MODE_BITSIZE (inner_mode), mode))
7286     {
7287       wanted_inner_reg_mode = insn.struct_mode;
7288       pos_mode = insn.pos_mode;
7289       extraction_mode = insn.field_mode;
7290     }
7291
7292   /* Never narrow an object, since that might not be safe.  */
7293
7294   if (mode != VOIDmode
7295       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7296     extraction_mode = mode;
7297
7298   if (!MEM_P (inner))
7299     wanted_inner_mode = wanted_inner_reg_mode;
7300   else
7301     {
7302       /* Be careful not to go beyond the extracted object and maintain the
7303          natural alignment of the memory.  */
7304       wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7305       while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7306              > GET_MODE_BITSIZE (wanted_inner_mode))
7307         {
7308           wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7309           gcc_assert (wanted_inner_mode != VOIDmode);
7310         }
7311     }
7312
7313   orig_pos = pos;
7314
7315   if (BITS_BIG_ENDIAN)
7316     {
7317       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7318          BITS_BIG_ENDIAN style.  If position is constant, compute new
7319          position.  Otherwise, build subtraction.
7320          Note that POS is relative to the mode of the original argument.
7321          If it's a MEM we need to recompute POS relative to that.
7322          However, if we're extracting from (or inserting into) a register,
7323          we want to recompute POS relative to wanted_inner_mode.  */
7324       int width = (MEM_P (inner)
7325                    ? GET_MODE_BITSIZE (is_mode)
7326                    : GET_MODE_BITSIZE (wanted_inner_mode));
7327
7328       if (pos_rtx == 0)
7329         pos = width - len - pos;
7330       else
7331         pos_rtx
7332           = gen_rtx_MINUS (GET_MODE (pos_rtx),
7333                            gen_int_mode (width - len, GET_MODE (pos_rtx)),
7334                            pos_rtx);
7335       /* POS may be less than 0 now, but we check for that below.
7336          Note that it can only be less than 0 if !MEM_P (inner).  */
7337     }
7338
7339   /* If INNER has a wider mode, and this is a constant extraction, try to
7340      make it smaller and adjust the byte to point to the byte containing
7341      the value.  */
7342   if (wanted_inner_mode != VOIDmode
7343       && inner_mode != wanted_inner_mode
7344       && ! pos_rtx
7345       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7346       && MEM_P (inner)
7347       && ! mode_dependent_address_p (XEXP (inner, 0), MEM_ADDR_SPACE (inner))
7348       && ! MEM_VOLATILE_P (inner))
7349     {
7350       int offset = 0;
7351
7352       /* The computations below will be correct if the machine is big
7353          endian in both bits and bytes or little endian in bits and bytes.
7354          If it is mixed, we must adjust.  */
7355
7356       /* If bytes are big endian and we had a paradoxical SUBREG, we must
7357          adjust OFFSET to compensate.  */
7358       if (BYTES_BIG_ENDIAN
7359           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7360         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7361
7362       /* We can now move to the desired byte.  */
7363       offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7364                 * GET_MODE_SIZE (wanted_inner_mode);
7365       pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7366
7367       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7368           && is_mode != wanted_inner_mode)
7369         offset = (GET_MODE_SIZE (is_mode)
7370                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
7371
7372       inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7373     }
7374
7375   /* If INNER is not memory, get it into the proper mode.  If we are changing
7376      its mode, POS must be a constant and smaller than the size of the new
7377      mode.  */
7378   else if (!MEM_P (inner))
7379     {
7380       /* On the LHS, don't create paradoxical subregs implicitely truncating
7381          the register unless TRULY_NOOP_TRUNCATION.  */
7382       if (in_dest
7383           && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7384                                              wanted_inner_mode))
7385         return NULL_RTX;
7386
7387       if (GET_MODE (inner) != wanted_inner_mode
7388           && (pos_rtx != 0
7389               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7390         return NULL_RTX;
7391
7392       if (orig_pos < 0)
7393         return NULL_RTX;
7394
7395       inner = force_to_mode (inner, wanted_inner_mode,
7396                              pos_rtx
7397                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7398                              ? ~(unsigned HOST_WIDE_INT) 0
7399                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7400                                 << orig_pos),
7401                              0);
7402     }
7403
7404   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
7405      have to zero extend.  Otherwise, we can just use a SUBREG.  */
7406   if (pos_rtx != 0
7407       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7408     {
7409       rtx temp = simplify_gen_unary (ZERO_EXTEND, pos_mode, pos_rtx,
7410                                      GET_MODE (pos_rtx));
7411
7412       /* If we know that no extraneous bits are set, and that the high
7413          bit is not set, convert extraction to cheaper one - either
7414          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7415          cases.  */
7416       if (flag_expensive_optimizations
7417           && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7418               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7419                    & ~(((unsigned HOST_WIDE_INT)
7420                         GET_MODE_MASK (GET_MODE (pos_rtx)))
7421                        >> 1))
7422                   == 0)))
7423         {
7424           rtx temp1 = simplify_gen_unary (SIGN_EXTEND, pos_mode, pos_rtx,
7425                                           GET_MODE (pos_rtx));
7426
7427           /* Prefer ZERO_EXTENSION, since it gives more information to
7428              backends.  */
7429           if (set_src_cost (temp1, optimize_this_for_speed_p)
7430               < set_src_cost (temp, optimize_this_for_speed_p))
7431             temp = temp1;
7432         }
7433       pos_rtx = temp;
7434     }
7435
7436   /* Make POS_RTX unless we already have it and it is correct.  If we don't
7437      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7438      be a CONST_INT.  */
7439   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7440     pos_rtx = orig_pos_rtx;
7441
7442   else if (pos_rtx == 0)
7443     pos_rtx = GEN_INT (pos);
7444
7445   /* Make the required operation.  See if we can use existing rtx.  */
7446   new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7447                          extraction_mode, inner, GEN_INT (len), pos_rtx);
7448   if (! in_dest)
7449     new_rtx = gen_lowpart (mode, new_rtx);
7450
7451   return new_rtx;
7452 }
7453 \f
7454 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7455    with any other operations in X.  Return X without that shift if so.  */
7456
7457 static rtx
7458 extract_left_shift (rtx x, int count)
7459 {
7460   enum rtx_code code = GET_CODE (x);
7461   machine_mode mode = GET_MODE (x);
7462   rtx tem;
7463
7464   switch (code)
7465     {
7466     case ASHIFT:
7467       /* This is the shift itself.  If it is wide enough, we will return
7468          either the value being shifted if the shift count is equal to
7469          COUNT or a shift for the difference.  */
7470       if (CONST_INT_P (XEXP (x, 1))
7471           && INTVAL (XEXP (x, 1)) >= count)
7472         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7473                                      INTVAL (XEXP (x, 1)) - count);
7474       break;
7475
7476     case NEG:  case NOT:
7477       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7478         return simplify_gen_unary (code, mode, tem, mode);
7479
7480       break;
7481
7482     case PLUS:  case IOR:  case XOR:  case AND:
7483       /* If we can safely shift this constant and we find the inner shift,
7484          make a new operation.  */
7485       if (CONST_INT_P (XEXP (x, 1))
7486           && (UINTVAL (XEXP (x, 1))
7487               & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0
7488           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7489         {
7490           HOST_WIDE_INT val = INTVAL (XEXP (x, 1)) >> count;
7491           return simplify_gen_binary (code, mode, tem,
7492                                       gen_int_mode (val, mode));
7493         }
7494       break;
7495
7496     default:
7497       break;
7498     }
7499
7500   return 0;
7501 }
7502 \f
7503 /* Look at the expression rooted at X.  Look for expressions
7504    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7505    Form these expressions.
7506
7507    Return the new rtx, usually just X.
7508
7509    Also, for machines like the VAX that don't have logical shift insns,
7510    try to convert logical to arithmetic shift operations in cases where
7511    they are equivalent.  This undoes the canonicalizations to logical
7512    shifts done elsewhere.
7513
7514    We try, as much as possible, to re-use rtl expressions to save memory.
7515
7516    IN_CODE says what kind of expression we are processing.  Normally, it is
7517    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
7518    being kludges), it is MEM.  When processing the arguments of a comparison
7519    or a COMPARE against zero, it is COMPARE.  */
7520
7521 rtx
7522 make_compound_operation (rtx x, enum rtx_code in_code)
7523 {
7524   enum rtx_code code = GET_CODE (x);
7525   machine_mode mode = GET_MODE (x);
7526   int mode_width = GET_MODE_PRECISION (mode);
7527   rtx rhs, lhs;
7528   enum rtx_code next_code;
7529   int i, j;
7530   rtx new_rtx = 0;
7531   rtx tem;
7532   const char *fmt;
7533
7534   /* Select the code to be used in recursive calls.  Once we are inside an
7535      address, we stay there.  If we have a comparison, set to COMPARE,
7536      but once inside, go back to our default of SET.  */
7537
7538   next_code = (code == MEM ? MEM
7539                : ((code == PLUS || code == MINUS)
7540                   && SCALAR_INT_MODE_P (mode)) ? MEM
7541                : ((code == COMPARE || COMPARISON_P (x))
7542                   && XEXP (x, 1) == const0_rtx) ? COMPARE
7543                : in_code == COMPARE ? SET : in_code);
7544
7545   /* Process depending on the code of this operation.  If NEW is set
7546      nonzero, it will be returned.  */
7547
7548   switch (code)
7549     {
7550     case ASHIFT:
7551       /* Convert shifts by constants into multiplications if inside
7552          an address.  */
7553       if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7554           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7555           && INTVAL (XEXP (x, 1)) >= 0
7556           && SCALAR_INT_MODE_P (mode))
7557         {
7558           HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7559           HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7560
7561           new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7562           if (GET_CODE (new_rtx) == NEG)
7563             {
7564               new_rtx = XEXP (new_rtx, 0);
7565               multval = -multval;
7566             }
7567           multval = trunc_int_for_mode (multval, mode);
7568           new_rtx = gen_rtx_MULT (mode, new_rtx, gen_int_mode (multval, mode));
7569         }
7570       break;
7571
7572     case PLUS:
7573       lhs = XEXP (x, 0);
7574       rhs = XEXP (x, 1);
7575       lhs = make_compound_operation (lhs, next_code);
7576       rhs = make_compound_operation (rhs, next_code);
7577       if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7578           && SCALAR_INT_MODE_P (mode))
7579         {
7580           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7581                                      XEXP (lhs, 1));
7582           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7583         }
7584       else if (GET_CODE (lhs) == MULT
7585                && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7586         {
7587           tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7588                                      simplify_gen_unary (NEG, mode,
7589                                                          XEXP (lhs, 1),
7590                                                          mode));
7591           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7592         }
7593       else
7594         {
7595           SUBST (XEXP (x, 0), lhs);
7596           SUBST (XEXP (x, 1), rhs);
7597           goto maybe_swap;
7598         }
7599       x = gen_lowpart (mode, new_rtx);
7600       goto maybe_swap;
7601
7602     case MINUS:
7603       lhs = XEXP (x, 0);
7604       rhs = XEXP (x, 1);
7605       lhs = make_compound_operation (lhs, next_code);
7606       rhs = make_compound_operation (rhs, next_code);
7607       if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7608           && SCALAR_INT_MODE_P (mode))
7609         {
7610           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7611                                      XEXP (rhs, 1));
7612           new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7613         }
7614       else if (GET_CODE (rhs) == MULT
7615                && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7616         {
7617           tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7618                                      simplify_gen_unary (NEG, mode,
7619                                                          XEXP (rhs, 1),
7620                                                          mode));
7621           new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7622         }
7623       else
7624         {
7625           SUBST (XEXP (x, 0), lhs);
7626           SUBST (XEXP (x, 1), rhs);
7627           return x;
7628         }
7629       return gen_lowpart (mode, new_rtx);
7630
7631     case AND:
7632       /* If the second operand is not a constant, we can't do anything
7633          with it.  */
7634       if (!CONST_INT_P (XEXP (x, 1)))
7635         break;
7636
7637       /* If the constant is a power of two minus one and the first operand
7638          is a logical right shift, make an extraction.  */
7639       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7640           && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7641         {
7642           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7643           new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7644                                  0, in_code == COMPARE);
7645         }
7646
7647       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
7648       else if (GET_CODE (XEXP (x, 0)) == SUBREG
7649                && subreg_lowpart_p (XEXP (x, 0))
7650                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7651                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7652         {
7653           new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7654                                          next_code);
7655           new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7656                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7657                                  0, in_code == COMPARE);
7658         }
7659       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
7660       else if ((GET_CODE (XEXP (x, 0)) == XOR
7661                 || GET_CODE (XEXP (x, 0)) == IOR)
7662                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7663                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7664                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7665         {
7666           /* Apply the distributive law, and then try to make extractions.  */
7667           new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7668                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7669                                              XEXP (x, 1)),
7670                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7671                                              XEXP (x, 1)));
7672           new_rtx = make_compound_operation (new_rtx, in_code);
7673         }
7674
7675       /* If we are have (and (rotate X C) M) and C is larger than the number
7676          of bits in M, this is an extraction.  */
7677
7678       else if (GET_CODE (XEXP (x, 0)) == ROTATE
7679                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7680                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
7681                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7682         {
7683           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7684           new_rtx = make_extraction (mode, new_rtx,
7685                                  (GET_MODE_PRECISION (mode)
7686                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
7687                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
7688         }
7689
7690       /* On machines without logical shifts, if the operand of the AND is
7691          a logical shift and our mask turns off all the propagated sign
7692          bits, we can replace the logical shift with an arithmetic shift.  */
7693       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7694                && !have_insn_for (LSHIFTRT, mode)
7695                && have_insn_for (ASHIFTRT, mode)
7696                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7697                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7698                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7699                && mode_width <= HOST_BITS_PER_WIDE_INT)
7700         {
7701           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7702
7703           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7704           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7705             SUBST (XEXP (x, 0),
7706                    gen_rtx_ASHIFTRT (mode,
7707                                      make_compound_operation
7708                                      (XEXP (XEXP (x, 0), 0), next_code),
7709                                      XEXP (XEXP (x, 0), 1)));
7710         }
7711
7712       /* If the constant is one less than a power of two, this might be
7713          representable by an extraction even if no shift is present.
7714          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7715          we are in a COMPARE.  */
7716       else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7717         new_rtx = make_extraction (mode,
7718                                make_compound_operation (XEXP (x, 0),
7719                                                         next_code),
7720                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7721
7722       /* If we are in a comparison and this is an AND with a power of two,
7723          convert this into the appropriate bit extract.  */
7724       else if (in_code == COMPARE
7725                && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
7726         new_rtx = make_extraction (mode,
7727                                make_compound_operation (XEXP (x, 0),
7728                                                         next_code),
7729                                i, NULL_RTX, 1, 1, 0, 1);
7730
7731       break;
7732
7733     case LSHIFTRT:
7734       /* If the sign bit is known to be zero, replace this with an
7735          arithmetic shift.  */
7736       if (have_insn_for (ASHIFTRT, mode)
7737           && ! have_insn_for (LSHIFTRT, mode)
7738           && mode_width <= HOST_BITS_PER_WIDE_INT
7739           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7740         {
7741           new_rtx = gen_rtx_ASHIFTRT (mode,
7742                                   make_compound_operation (XEXP (x, 0),
7743                                                            next_code),
7744                                   XEXP (x, 1));
7745           break;
7746         }
7747
7748       /* ... fall through ...  */
7749
7750     case ASHIFTRT:
7751       lhs = XEXP (x, 0);
7752       rhs = XEXP (x, 1);
7753
7754       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7755          this is a SIGN_EXTRACT.  */
7756       if (CONST_INT_P (rhs)
7757           && GET_CODE (lhs) == ASHIFT
7758           && CONST_INT_P (XEXP (lhs, 1))
7759           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7760           && INTVAL (XEXP (lhs, 1)) >= 0
7761           && INTVAL (rhs) < mode_width)
7762         {
7763           new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7764           new_rtx = make_extraction (mode, new_rtx,
7765                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7766                                  NULL_RTX, mode_width - INTVAL (rhs),
7767                                  code == LSHIFTRT, 0, in_code == COMPARE);
7768           break;
7769         }
7770
7771       /* See if we have operations between an ASHIFTRT and an ASHIFT.
7772          If so, try to merge the shifts into a SIGN_EXTEND.  We could
7773          also do this for some cases of SIGN_EXTRACT, but it doesn't
7774          seem worth the effort; the case checked for occurs on Alpha.  */
7775
7776       if (!OBJECT_P (lhs)
7777           && ! (GET_CODE (lhs) == SUBREG
7778                 && (OBJECT_P (SUBREG_REG (lhs))))
7779           && CONST_INT_P (rhs)
7780           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7781           && INTVAL (rhs) < mode_width
7782           && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7783         new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7784                                0, NULL_RTX, mode_width - INTVAL (rhs),
7785                                code == LSHIFTRT, 0, in_code == COMPARE);
7786
7787       break;
7788
7789     case SUBREG:
7790       /* Call ourselves recursively on the inner expression.  If we are
7791          narrowing the object and it has a different RTL code from
7792          what it originally did, do this SUBREG as a force_to_mode.  */
7793       {
7794         rtx inner = SUBREG_REG (x), simplified;
7795         enum rtx_code subreg_code = in_code;
7796
7797         /* If in_code is COMPARE, it isn't always safe to pass it through
7798            to the recursive make_compound_operation call.  */
7799         if (subreg_code == COMPARE
7800             && (!subreg_lowpart_p (x)
7801                 || GET_CODE (inner) == SUBREG
7802                 /* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
7803                    is (const_int 0), rather than
7804                    (subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).  */
7805                 || (GET_CODE (inner) == AND
7806                     && CONST_INT_P (XEXP (inner, 1))
7807                     && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7808                     && exact_log2 (UINTVAL (XEXP (inner, 1)))
7809                        >= GET_MODE_BITSIZE (mode))))
7810           subreg_code = SET;
7811
7812         tem = make_compound_operation (inner, subreg_code);
7813
7814         simplified
7815           = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7816         if (simplified)
7817           tem = simplified;
7818
7819         if (GET_CODE (tem) != GET_CODE (inner)
7820             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7821             && subreg_lowpart_p (x))
7822           {
7823             rtx newer
7824               = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
7825
7826             /* If we have something other than a SUBREG, we might have
7827                done an expansion, so rerun ourselves.  */
7828             if (GET_CODE (newer) != SUBREG)
7829               newer = make_compound_operation (newer, in_code);
7830
7831             /* force_to_mode can expand compounds.  If it just re-expanded the
7832                compound, use gen_lowpart to convert to the desired mode.  */
7833             if (rtx_equal_p (newer, x)
7834                 /* Likewise if it re-expanded the compound only partially.
7835                    This happens for SUBREG of ZERO_EXTRACT if they extract
7836                    the same number of bits.  */
7837                 || (GET_CODE (newer) == SUBREG
7838                     && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7839                         || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7840                     && GET_CODE (inner) == AND
7841                     && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7842               return gen_lowpart (GET_MODE (x), tem);
7843
7844             return newer;
7845           }
7846
7847         if (simplified)
7848           return tem;
7849       }
7850       break;
7851
7852     default:
7853       break;
7854     }
7855
7856   if (new_rtx)
7857     {
7858       x = gen_lowpart (mode, new_rtx);
7859       code = GET_CODE (x);
7860     }
7861
7862   /* Now recursively process each operand of this operation.  We need to
7863      handle ZERO_EXTEND specially so that we don't lose track of the
7864      inner mode.  */
7865   if (GET_CODE (x) == ZERO_EXTEND)
7866     {
7867       new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7868       tem = simplify_const_unary_operation (ZERO_EXTEND, GET_MODE (x),
7869                                             new_rtx, GET_MODE (XEXP (x, 0)));
7870       if (tem)
7871         return tem;
7872       SUBST (XEXP (x, 0), new_rtx);
7873       return x;
7874     }
7875
7876   fmt = GET_RTX_FORMAT (code);
7877   for (i = 0; i < GET_RTX_LENGTH (code); i++)
7878     if (fmt[i] == 'e')
7879       {
7880         new_rtx = make_compound_operation (XEXP (x, i), next_code);
7881         SUBST (XEXP (x, i), new_rtx);
7882       }
7883     else if (fmt[i] == 'E')
7884       for (j = 0; j < XVECLEN (x, i); j++)
7885         {
7886           new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7887           SUBST (XVECEXP (x, i, j), new_rtx);
7888         }
7889
7890  maybe_swap:
7891   /* If this is a commutative operation, the changes to the operands
7892      may have made it noncanonical.  */
7893   if (COMMUTATIVE_ARITH_P (x)
7894       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7895     {
7896       tem = XEXP (x, 0);
7897       SUBST (XEXP (x, 0), XEXP (x, 1));
7898       SUBST (XEXP (x, 1), tem);
7899     }
7900
7901   return x;
7902 }
7903 \f
7904 /* Given M see if it is a value that would select a field of bits
7905    within an item, but not the entire word.  Return -1 if not.
7906    Otherwise, return the starting position of the field, where 0 is the
7907    low-order bit.
7908
7909    *PLEN is set to the length of the field.  */
7910
7911 static int
7912 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7913 {
7914   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
7915   int pos = m ? ctz_hwi (m) : -1;
7916   int len = 0;
7917
7918   if (pos >= 0)
7919     /* Now shift off the low-order zero bits and see if we have a
7920        power of two minus 1.  */
7921     len = exact_log2 ((m >> pos) + 1);
7922
7923   if (len <= 0)
7924     pos = -1;
7925
7926   *plen = len;
7927   return pos;
7928 }
7929 \f
7930 /* If X refers to a register that equals REG in value, replace these
7931    references with REG.  */
7932 static rtx
7933 canon_reg_for_combine (rtx x, rtx reg)
7934 {
7935   rtx op0, op1, op2;
7936   const char *fmt;
7937   int i;
7938   bool copied;
7939
7940   enum rtx_code code = GET_CODE (x);
7941   switch (GET_RTX_CLASS (code))
7942     {
7943     case RTX_UNARY:
7944       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7945       if (op0 != XEXP (x, 0))
7946         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7947                                    GET_MODE (reg));
7948       break;
7949
7950     case RTX_BIN_ARITH:
7951     case RTX_COMM_ARITH:
7952       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7953       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7954       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7955         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
7956       break;
7957
7958     case RTX_COMPARE:
7959     case RTX_COMM_COMPARE:
7960       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7961       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7962       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
7963         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
7964                                         GET_MODE (op0), op0, op1);
7965       break;
7966
7967     case RTX_TERNARY:
7968     case RTX_BITFIELD_OPS:
7969       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7970       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7971       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
7972       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
7973         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
7974                                      GET_MODE (op0), op0, op1, op2);
7975
7976     case RTX_OBJ:
7977       if (REG_P (x))
7978         {
7979           if (rtx_equal_p (get_last_value (reg), x)
7980               || rtx_equal_p (reg, get_last_value (x)))
7981             return reg;
7982           else
7983             break;
7984         }
7985
7986       /* fall through */
7987
7988     default:
7989       fmt = GET_RTX_FORMAT (code);
7990       copied = false;
7991       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7992         if (fmt[i] == 'e')
7993           {
7994             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
7995             if (op != XEXP (x, i))
7996               {
7997                 if (!copied)
7998                   {
7999                     copied = true;
8000                     x = copy_rtx (x);
8001                   }
8002                 XEXP (x, i) = op;
8003               }
8004           }
8005         else if (fmt[i] == 'E')
8006           {
8007             int j;
8008             for (j = 0; j < XVECLEN (x, i); j++)
8009               {
8010                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
8011                 if (op != XVECEXP (x, i, j))
8012                   {
8013                     if (!copied)
8014                       {
8015                         copied = true;
8016                         x = copy_rtx (x);
8017                       }
8018                     XVECEXP (x, i, j) = op;
8019                   }
8020               }
8021           }
8022
8023       break;
8024     }
8025
8026   return x;
8027 }
8028
8029 /* Return X converted to MODE.  If the value is already truncated to
8030    MODE we can just return a subreg even though in the general case we
8031    would need an explicit truncation.  */
8032
8033 static rtx
8034 gen_lowpart_or_truncate (machine_mode mode, rtx x)
8035 {
8036   if (!CONST_INT_P (x)
8037       && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8038       && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
8039       && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
8040     {
8041       /* Bit-cast X into an integer mode.  */
8042       if (!SCALAR_INT_MODE_P (GET_MODE (x)))
8043         x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
8044       x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
8045                               x, GET_MODE (x));
8046     }
8047
8048   return gen_lowpart (mode, x);
8049 }
8050
8051 /* See if X can be simplified knowing that we will only refer to it in
8052    MODE and will only refer to those bits that are nonzero in MASK.
8053    If other bits are being computed or if masking operations are done
8054    that select a superset of the bits in MASK, they can sometimes be
8055    ignored.
8056
8057    Return a possibly simplified expression, but always convert X to
8058    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
8059
8060    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8061    are all off in X.  This is used when X will be complemented, by either
8062    NOT, NEG, or XOR.  */
8063
8064 static rtx
8065 force_to_mode (rtx x, machine_mode mode, unsigned HOST_WIDE_INT mask,
8066                int just_select)
8067 {
8068   enum rtx_code code = GET_CODE (x);
8069   int next_select = just_select || code == XOR || code == NOT || code == NEG;
8070   machine_mode op_mode;
8071   unsigned HOST_WIDE_INT fuller_mask, nonzero;
8072   rtx op0, op1, temp;
8073
8074   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
8075      code below will do the wrong thing since the mode of such an
8076      expression is VOIDmode.
8077
8078      Also do nothing if X is a CLOBBER; this can happen if X was
8079      the return value from a call to gen_lowpart.  */
8080   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8081     return x;
8082
8083   /* We want to perform the operation in its present mode unless we know
8084      that the operation is valid in MODE, in which case we do the operation
8085      in MODE.  */
8086   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8087               && have_insn_for (code, mode))
8088              ? mode : GET_MODE (x));
8089
8090   /* It is not valid to do a right-shift in a narrower mode
8091      than the one it came in with.  */
8092   if ((code == LSHIFTRT || code == ASHIFTRT)
8093       && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (GET_MODE (x)))
8094     op_mode = GET_MODE (x);
8095
8096   /* Truncate MASK to fit OP_MODE.  */
8097   if (op_mode)
8098     mask &= GET_MODE_MASK (op_mode);
8099
8100   /* When we have an arithmetic operation, or a shift whose count we
8101      do not know, we need to assume that all bits up to the highest-order
8102      bit in MASK will be needed.  This is how we form such a mask.  */
8103   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
8104     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
8105   else
8106     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
8107                    - 1);
8108
8109   /* Determine what bits of X are guaranteed to be (non)zero.  */
8110   nonzero = nonzero_bits (x, mode);
8111
8112   /* If none of the bits in X are needed, return a zero.  */
8113   if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8114     x = const0_rtx;
8115
8116   /* If X is a CONST_INT, return a new one.  Do this here since the
8117      test below will fail.  */
8118   if (CONST_INT_P (x))
8119     {
8120       if (SCALAR_INT_MODE_P (mode))
8121         return gen_int_mode (INTVAL (x) & mask, mode);
8122       else
8123         {
8124           x = GEN_INT (INTVAL (x) & mask);
8125           return gen_lowpart_common (mode, x);
8126         }
8127     }
8128
8129   /* If X is narrower than MODE and we want all the bits in X's mode, just
8130      get X in the proper mode.  */
8131   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8132       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8133     return gen_lowpart (mode, x);
8134
8135   /* We can ignore the effect of a SUBREG if it narrows the mode or
8136      if the constant masks to zero all the bits the mode doesn't have.  */
8137   if (GET_CODE (x) == SUBREG
8138       && subreg_lowpart_p (x)
8139       && ((GET_MODE_SIZE (GET_MODE (x))
8140            < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8141           || (0 == (mask
8142                     & GET_MODE_MASK (GET_MODE (x))
8143                     & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8144     return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8145
8146   /* The arithmetic simplifications here only work for scalar integer modes.  */
8147   if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8148     return gen_lowpart_or_truncate (mode, x);
8149
8150   switch (code)
8151     {
8152     case CLOBBER:
8153       /* If X is a (clobber (const_int)), return it since we know we are
8154          generating something that won't match.  */
8155       return x;
8156
8157     case SIGN_EXTEND:
8158     case ZERO_EXTEND:
8159     case ZERO_EXTRACT:
8160     case SIGN_EXTRACT:
8161       x = expand_compound_operation (x);
8162       if (GET_CODE (x) != code)
8163         return force_to_mode (x, mode, mask, next_select);
8164       break;
8165
8166     case TRUNCATE:
8167       /* Similarly for a truncate.  */
8168       return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8169
8170     case AND:
8171       /* If this is an AND with a constant, convert it into an AND
8172          whose constant is the AND of that constant with MASK.  If it
8173          remains an AND of MASK, delete it since it is redundant.  */
8174
8175       if (CONST_INT_P (XEXP (x, 1)))
8176         {
8177           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8178                                       mask & INTVAL (XEXP (x, 1)));
8179
8180           /* If X is still an AND, see if it is an AND with a mask that
8181              is just some low-order bits.  If so, and it is MASK, we don't
8182              need it.  */
8183
8184           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8185               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8186                   == mask))
8187             x = XEXP (x, 0);
8188
8189           /* If it remains an AND, try making another AND with the bits
8190              in the mode mask that aren't in MASK turned on.  If the
8191              constant in the AND is wide enough, this might make a
8192              cheaper constant.  */
8193
8194           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8195               && GET_MODE_MASK (GET_MODE (x)) != mask
8196               && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
8197             {
8198               unsigned HOST_WIDE_INT cval
8199                 = UINTVAL (XEXP (x, 1))
8200                   | (GET_MODE_MASK (GET_MODE (x)) & ~mask);
8201               rtx y;
8202
8203               y = simplify_gen_binary (AND, GET_MODE (x), XEXP (x, 0),
8204                                        gen_int_mode (cval, GET_MODE (x)));
8205               if (set_src_cost (y, optimize_this_for_speed_p)
8206                   < set_src_cost (x, optimize_this_for_speed_p))
8207                 x = y;
8208             }
8209
8210           break;
8211         }
8212
8213       goto binop;
8214
8215     case PLUS:
8216       /* In (and (plus FOO C1) M), if M is a mask that just turns off
8217          low-order bits (as in an alignment operation) and FOO is already
8218          aligned to that boundary, mask C1 to that boundary as well.
8219          This may eliminate that PLUS and, later, the AND.  */
8220
8221       {
8222         unsigned int width = GET_MODE_PRECISION (mode);
8223         unsigned HOST_WIDE_INT smask = mask;
8224
8225         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8226            number, sign extend it.  */
8227
8228         if (width < HOST_BITS_PER_WIDE_INT
8229             && (smask & (HOST_WIDE_INT_1U << (width - 1))) != 0)
8230           smask |= HOST_WIDE_INT_M1U << width;
8231
8232         if (CONST_INT_P (XEXP (x, 1))
8233             && exact_log2 (- smask) >= 0
8234             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8235             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8236           return force_to_mode (plus_constant (GET_MODE (x), XEXP (x, 0),
8237                                                (INTVAL (XEXP (x, 1)) & smask)),
8238                                 mode, smask, next_select);
8239       }
8240
8241       /* ... fall through ...  */
8242
8243     case MULT:
8244       /* For PLUS, MINUS and MULT, we need any bits less significant than the
8245          most significant bit in MASK since carries from those bits will
8246          affect the bits we are interested in.  */
8247       mask = fuller_mask;
8248       goto binop;
8249
8250     case MINUS:
8251       /* If X is (minus C Y) where C's least set bit is larger than any bit
8252          in the mask, then we may replace with (neg Y).  */
8253       if (CONST_INT_P (XEXP (x, 0))
8254           && ((UINTVAL (XEXP (x, 0)) & -UINTVAL (XEXP (x, 0))) > mask))
8255         {
8256           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8257                                   GET_MODE (x));
8258           return force_to_mode (x, mode, mask, next_select);
8259         }
8260
8261       /* Similarly, if C contains every bit in the fuller_mask, then we may
8262          replace with (not Y).  */
8263       if (CONST_INT_P (XEXP (x, 0))
8264           && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8265         {
8266           x = simplify_gen_unary (NOT, GET_MODE (x),
8267                                   XEXP (x, 1), GET_MODE (x));
8268           return force_to_mode (x, mode, mask, next_select);
8269         }
8270
8271       mask = fuller_mask;
8272       goto binop;
8273
8274     case IOR:
8275     case XOR:
8276       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8277          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8278          operation which may be a bitfield extraction.  Ensure that the
8279          constant we form is not wider than the mode of X.  */
8280
8281       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8282           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8283           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8284           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8285           && CONST_INT_P (XEXP (x, 1))
8286           && ((INTVAL (XEXP (XEXP (x, 0), 1))
8287                + floor_log2 (INTVAL (XEXP (x, 1))))
8288               < GET_MODE_PRECISION (GET_MODE (x)))
8289           && (UINTVAL (XEXP (x, 1))
8290               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8291         {
8292           temp = gen_int_mode ((INTVAL (XEXP (x, 1)) & mask)
8293                                << INTVAL (XEXP (XEXP (x, 0), 1)),
8294                                GET_MODE (x));
8295           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8296                                       XEXP (XEXP (x, 0), 0), temp);
8297           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8298                                    XEXP (XEXP (x, 0), 1));
8299           return force_to_mode (x, mode, mask, next_select);
8300         }
8301
8302     binop:
8303       /* For most binary operations, just propagate into the operation and
8304          change the mode if we have an operation of that mode.  */
8305
8306       op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8307       op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8308
8309       /* If we ended up truncating both operands, truncate the result of the
8310          operation instead.  */
8311       if (GET_CODE (op0) == TRUNCATE
8312           && GET_CODE (op1) == TRUNCATE)
8313         {
8314           op0 = XEXP (op0, 0);
8315           op1 = XEXP (op1, 0);
8316         }
8317
8318       op0 = gen_lowpart_or_truncate (op_mode, op0);
8319       op1 = gen_lowpart_or_truncate (op_mode, op1);
8320
8321       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8322         x = simplify_gen_binary (code, op_mode, op0, op1);
8323       break;
8324
8325     case ASHIFT:
8326       /* For left shifts, do the same, but just for the first operand.
8327          However, we cannot do anything with shifts where we cannot
8328          guarantee that the counts are smaller than the size of the mode
8329          because such a count will have a different meaning in a
8330          wider mode.  */
8331
8332       if (! (CONST_INT_P (XEXP (x, 1))
8333              && INTVAL (XEXP (x, 1)) >= 0
8334              && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
8335           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8336                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8337                     < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
8338         break;
8339
8340       /* If the shift count is a constant and we can do arithmetic in
8341          the mode of the shift, refine which bits we need.  Otherwise, use the
8342          conservative form of the mask.  */
8343       if (CONST_INT_P (XEXP (x, 1))
8344           && INTVAL (XEXP (x, 1)) >= 0
8345           && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode)
8346           && HWI_COMPUTABLE_MODE_P (op_mode))
8347         mask >>= INTVAL (XEXP (x, 1));
8348       else
8349         mask = fuller_mask;
8350
8351       op0 = gen_lowpart_or_truncate (op_mode,
8352                                      force_to_mode (XEXP (x, 0), op_mode,
8353                                                     mask, next_select));
8354
8355       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8356         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8357       break;
8358
8359     case LSHIFTRT:
8360       /* Here we can only do something if the shift count is a constant,
8361          this shift constant is valid for the host, and we can do arithmetic
8362          in OP_MODE.  */
8363
8364       if (CONST_INT_P (XEXP (x, 1))
8365           && INTVAL (XEXP (x, 1)) >= 0
8366           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8367           && HWI_COMPUTABLE_MODE_P (op_mode))
8368         {
8369           rtx inner = XEXP (x, 0);
8370           unsigned HOST_WIDE_INT inner_mask;
8371
8372           /* Select the mask of the bits we need for the shift operand.  */
8373           inner_mask = mask << INTVAL (XEXP (x, 1));
8374
8375           /* We can only change the mode of the shift if we can do arithmetic
8376              in the mode of the shift and INNER_MASK is no wider than the
8377              width of X's mode.  */
8378           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8379             op_mode = GET_MODE (x);
8380
8381           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8382
8383           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8384             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8385         }
8386
8387       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8388          shift and AND produces only copies of the sign bit (C2 is one less
8389          than a power of two), we can do this with just a shift.  */
8390
8391       if (GET_CODE (x) == LSHIFTRT
8392           && CONST_INT_P (XEXP (x, 1))
8393           /* The shift puts one of the sign bit copies in the least significant
8394              bit.  */
8395           && ((INTVAL (XEXP (x, 1))
8396                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8397               >= GET_MODE_PRECISION (GET_MODE (x)))
8398           && exact_log2 (mask + 1) >= 0
8399           /* Number of bits left after the shift must be more than the mask
8400              needs.  */
8401           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8402               <= GET_MODE_PRECISION (GET_MODE (x)))
8403           /* Must be more sign bit copies than the mask needs.  */
8404           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8405               >= exact_log2 (mask + 1)))
8406         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8407                                  GEN_INT (GET_MODE_PRECISION (GET_MODE (x))
8408                                           - exact_log2 (mask + 1)));
8409
8410       goto shiftrt;
8411
8412     case ASHIFTRT:
8413       /* If we are just looking for the sign bit, we don't need this shift at
8414          all, even if it has a variable count.  */
8415       if (val_signbit_p (GET_MODE (x), mask))
8416         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8417
8418       /* If this is a shift by a constant, get a mask that contains those bits
8419          that are not copies of the sign bit.  We then have two cases:  If
8420          MASK only includes those bits, this can be a logical shift, which may
8421          allow simplifications.  If MASK is a single-bit field not within
8422          those bits, we are requesting a copy of the sign bit and hence can
8423          shift the sign bit to the appropriate location.  */
8424
8425       if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8426           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8427         {
8428           int i;
8429
8430           /* If the considered data is wider than HOST_WIDE_INT, we can't
8431              represent a mask for all its bits in a single scalar.
8432              But we only care about the lower bits, so calculate these.  */
8433
8434           if (GET_MODE_PRECISION (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8435             {
8436               nonzero = ~(unsigned HOST_WIDE_INT) 0;
8437
8438               /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8439                  is the number of bits a full-width mask would have set.
8440                  We need only shift if these are fewer than nonzero can
8441                  hold.  If not, we must keep all bits set in nonzero.  */
8442
8443               if (GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8444                   < HOST_BITS_PER_WIDE_INT)
8445                 nonzero >>= INTVAL (XEXP (x, 1))
8446                             + HOST_BITS_PER_WIDE_INT
8447                             - GET_MODE_PRECISION (GET_MODE (x)) ;
8448             }
8449           else
8450             {
8451               nonzero = GET_MODE_MASK (GET_MODE (x));
8452               nonzero >>= INTVAL (XEXP (x, 1));
8453             }
8454
8455           if ((mask & ~nonzero) == 0)
8456             {
8457               x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8458                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
8459               if (GET_CODE (x) != ASHIFTRT)
8460                 return force_to_mode (x, mode, mask, next_select);
8461             }
8462
8463           else if ((i = exact_log2 (mask)) >= 0)
8464             {
8465               x = simplify_shift_const
8466                   (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8467                    GET_MODE_PRECISION (GET_MODE (x)) - 1 - i);
8468
8469               if (GET_CODE (x) != ASHIFTRT)
8470                 return force_to_mode (x, mode, mask, next_select);
8471             }
8472         }
8473
8474       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
8475          even if the shift count isn't a constant.  */
8476       if (mask == 1)
8477         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8478                                  XEXP (x, 0), XEXP (x, 1));
8479
8480     shiftrt:
8481
8482       /* If this is a zero- or sign-extension operation that just affects bits
8483          we don't care about, remove it.  Be sure the call above returned
8484          something that is still a shift.  */
8485
8486       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8487           && CONST_INT_P (XEXP (x, 1))
8488           && INTVAL (XEXP (x, 1)) >= 0
8489           && (INTVAL (XEXP (x, 1))
8490               <= GET_MODE_PRECISION (GET_MODE (x)) - (floor_log2 (mask) + 1))
8491           && GET_CODE (XEXP (x, 0)) == ASHIFT
8492           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8493         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8494                               next_select);
8495
8496       break;
8497
8498     case ROTATE:
8499     case ROTATERT:
8500       /* If the shift count is constant and we can do computations
8501          in the mode of X, compute where the bits we care about are.
8502          Otherwise, we can't do anything.  Don't change the mode of
8503          the shift or propagate MODE into the shift, though.  */
8504       if (CONST_INT_P (XEXP (x, 1))
8505           && INTVAL (XEXP (x, 1)) >= 0)
8506         {
8507           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8508                                             GET_MODE (x),
8509                                             gen_int_mode (mask, GET_MODE (x)),
8510                                             XEXP (x, 1));
8511           if (temp && CONST_INT_P (temp))
8512             x = simplify_gen_binary (code, GET_MODE (x),
8513                                      force_to_mode (XEXP (x, 0), GET_MODE (x),
8514                                                     INTVAL (temp), next_select),
8515                                      XEXP (x, 1));
8516         }
8517       break;
8518
8519     case NEG:
8520       /* If we just want the low-order bit, the NEG isn't needed since it
8521          won't change the low-order bit.  */
8522       if (mask == 1)
8523         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8524
8525       /* We need any bits less significant than the most significant bit in
8526          MASK since carries from those bits will affect the bits we are
8527          interested in.  */
8528       mask = fuller_mask;
8529       goto unop;
8530
8531     case NOT:
8532       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8533          same as the XOR case above.  Ensure that the constant we form is not
8534          wider than the mode of X.  */
8535
8536       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8537           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8538           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8539           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8540               < GET_MODE_PRECISION (GET_MODE (x)))
8541           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8542         {
8543           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8544                                GET_MODE (x));
8545           temp = simplify_gen_binary (XOR, GET_MODE (x),
8546                                       XEXP (XEXP (x, 0), 0), temp);
8547           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8548                                    temp, XEXP (XEXP (x, 0), 1));
8549
8550           return force_to_mode (x, mode, mask, next_select);
8551         }
8552
8553       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8554          use the full mask inside the NOT.  */
8555       mask = fuller_mask;
8556
8557     unop:
8558       op0 = gen_lowpart_or_truncate (op_mode,
8559                                      force_to_mode (XEXP (x, 0), mode, mask,
8560                                                     next_select));
8561       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8562         x = simplify_gen_unary (code, op_mode, op0, op_mode);
8563       break;
8564
8565     case NE:
8566       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8567          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8568          which is equal to STORE_FLAG_VALUE.  */
8569       if ((mask & ~STORE_FLAG_VALUE) == 0
8570           && XEXP (x, 1) == const0_rtx
8571           && GET_MODE (XEXP (x, 0)) == mode
8572           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8573           && (nonzero_bits (XEXP (x, 0), mode)
8574               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8575         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8576
8577       break;
8578
8579     case IF_THEN_ELSE:
8580       /* We have no way of knowing if the IF_THEN_ELSE can itself be
8581          written in a narrower mode.  We play it safe and do not do so.  */
8582
8583       op0 = gen_lowpart_or_truncate (GET_MODE (x),
8584                                      force_to_mode (XEXP (x, 1), mode,
8585                                                     mask, next_select));
8586       op1 = gen_lowpart_or_truncate (GET_MODE (x),
8587                                      force_to_mode (XEXP (x, 2), mode,
8588                                                     mask, next_select));
8589       if (op0 != XEXP (x, 1) || op1 != XEXP (x, 2))
8590         x = simplify_gen_ternary (IF_THEN_ELSE, GET_MODE (x),
8591                                   GET_MODE (XEXP (x, 0)), XEXP (x, 0),
8592                                   op0, op1);
8593       break;
8594
8595     default:
8596       break;
8597     }
8598
8599   /* Ensure we return a value of the proper mode.  */
8600   return gen_lowpart_or_truncate (mode, x);
8601 }
8602 \f
8603 /* Return nonzero if X is an expression that has one of two values depending on
8604    whether some other value is zero or nonzero.  In that case, we return the
8605    value that is being tested, *PTRUE is set to the value if the rtx being
8606    returned has a nonzero value, and *PFALSE is set to the other alternative.
8607
8608    If we return zero, we set *PTRUE and *PFALSE to X.  */
8609
8610 static rtx
8611 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8612 {
8613   machine_mode mode = GET_MODE (x);
8614   enum rtx_code code = GET_CODE (x);
8615   rtx cond0, cond1, true0, true1, false0, false1;
8616   unsigned HOST_WIDE_INT nz;
8617
8618   /* If we are comparing a value against zero, we are done.  */
8619   if ((code == NE || code == EQ)
8620       && XEXP (x, 1) == const0_rtx)
8621     {
8622       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8623       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8624       return XEXP (x, 0);
8625     }
8626
8627   /* If this is a unary operation whose operand has one of two values, apply
8628      our opcode to compute those values.  */
8629   else if (UNARY_P (x)
8630            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8631     {
8632       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8633       *pfalse = simplify_gen_unary (code, mode, false0,
8634                                     GET_MODE (XEXP (x, 0)));
8635       return cond0;
8636     }
8637
8638   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8639      make can't possibly match and would suppress other optimizations.  */
8640   else if (code == COMPARE)
8641     ;
8642
8643   /* If this is a binary operation, see if either side has only one of two
8644      values.  If either one does or if both do and they are conditional on
8645      the same value, compute the new true and false values.  */
8646   else if (BINARY_P (x))
8647     {
8648       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8649       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8650
8651       if ((cond0 != 0 || cond1 != 0)
8652           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8653         {
8654           /* If if_then_else_cond returned zero, then true/false are the
8655              same rtl.  We must copy one of them to prevent invalid rtl
8656              sharing.  */
8657           if (cond0 == 0)
8658             true0 = copy_rtx (true0);
8659           else if (cond1 == 0)
8660             true1 = copy_rtx (true1);
8661
8662           if (COMPARISON_P (x))
8663             {
8664               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8665                                                 true0, true1);
8666               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8667                                                  false0, false1);
8668              }
8669           else
8670             {
8671               *ptrue = simplify_gen_binary (code, mode, true0, true1);
8672               *pfalse = simplify_gen_binary (code, mode, false0, false1);
8673             }
8674
8675           return cond0 ? cond0 : cond1;
8676         }
8677
8678       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8679          operands is zero when the other is nonzero, and vice-versa,
8680          and STORE_FLAG_VALUE is 1 or -1.  */
8681
8682       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8683           && (code == PLUS || code == IOR || code == XOR || code == MINUS
8684               || code == UMAX)
8685           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8686         {
8687           rtx op0 = XEXP (XEXP (x, 0), 1);
8688           rtx op1 = XEXP (XEXP (x, 1), 1);
8689
8690           cond0 = XEXP (XEXP (x, 0), 0);
8691           cond1 = XEXP (XEXP (x, 1), 0);
8692
8693           if (COMPARISON_P (cond0)
8694               && COMPARISON_P (cond1)
8695               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8696                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8697                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8698                   || ((swap_condition (GET_CODE (cond0))
8699                        == reversed_comparison_code (cond1, NULL))
8700                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8701                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8702               && ! side_effects_p (x))
8703             {
8704               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8705               *pfalse = simplify_gen_binary (MULT, mode,
8706                                              (code == MINUS
8707                                               ? simplify_gen_unary (NEG, mode,
8708                                                                     op1, mode)
8709                                               : op1),
8710                                               const_true_rtx);
8711               return cond0;
8712             }
8713         }
8714
8715       /* Similarly for MULT, AND and UMIN, except that for these the result
8716          is always zero.  */
8717       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8718           && (code == MULT || code == AND || code == UMIN)
8719           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8720         {
8721           cond0 = XEXP (XEXP (x, 0), 0);
8722           cond1 = XEXP (XEXP (x, 1), 0);
8723
8724           if (COMPARISON_P (cond0)
8725               && COMPARISON_P (cond1)
8726               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8727                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8728                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8729                   || ((swap_condition (GET_CODE (cond0))
8730                        == reversed_comparison_code (cond1, NULL))
8731                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8732                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8733               && ! side_effects_p (x))
8734             {
8735               *ptrue = *pfalse = const0_rtx;
8736               return cond0;
8737             }
8738         }
8739     }
8740
8741   else if (code == IF_THEN_ELSE)
8742     {
8743       /* If we have IF_THEN_ELSE already, extract the condition and
8744          canonicalize it if it is NE or EQ.  */
8745       cond0 = XEXP (x, 0);
8746       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8747       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8748         return XEXP (cond0, 0);
8749       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8750         {
8751           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8752           return XEXP (cond0, 0);
8753         }
8754       else
8755         return cond0;
8756     }
8757
8758   /* If X is a SUBREG, we can narrow both the true and false values
8759      if the inner expression, if there is a condition.  */
8760   else if (code == SUBREG
8761            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8762                                                &true0, &false0)))
8763     {
8764       true0 = simplify_gen_subreg (mode, true0,
8765                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8766       false0 = simplify_gen_subreg (mode, false0,
8767                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8768       if (true0 && false0)
8769         {
8770           *ptrue = true0;
8771           *pfalse = false0;
8772           return cond0;
8773         }
8774     }
8775
8776   /* If X is a constant, this isn't special and will cause confusions
8777      if we treat it as such.  Likewise if it is equivalent to a constant.  */
8778   else if (CONSTANT_P (x)
8779            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8780     ;
8781
8782   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8783      will be least confusing to the rest of the compiler.  */
8784   else if (mode == BImode)
8785     {
8786       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8787       return x;
8788     }
8789
8790   /* If X is known to be either 0 or -1, those are the true and
8791      false values when testing X.  */
8792   else if (x == constm1_rtx || x == const0_rtx
8793            || (mode != VOIDmode
8794                && num_sign_bit_copies (x, mode) == GET_MODE_PRECISION (mode)))
8795     {
8796       *ptrue = constm1_rtx, *pfalse = const0_rtx;
8797       return x;
8798     }
8799
8800   /* Likewise for 0 or a single bit.  */
8801   else if (HWI_COMPUTABLE_MODE_P (mode)
8802            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8803     {
8804       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8805       return x;
8806     }
8807
8808   /* Otherwise fail; show no condition with true and false values the same.  */
8809   *ptrue = *pfalse = x;
8810   return 0;
8811 }
8812 \f
8813 /* Return the value of expression X given the fact that condition COND
8814    is known to be true when applied to REG as its first operand and VAL
8815    as its second.  X is known to not be shared and so can be modified in
8816    place.
8817
8818    We only handle the simplest cases, and specifically those cases that
8819    arise with IF_THEN_ELSE expressions.  */
8820
8821 static rtx
8822 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8823 {
8824   enum rtx_code code = GET_CODE (x);
8825   rtx temp;
8826   const char *fmt;
8827   int i, j;
8828
8829   if (side_effects_p (x))
8830     return x;
8831
8832   /* If either operand of the condition is a floating point value,
8833      then we have to avoid collapsing an EQ comparison.  */
8834   if (cond == EQ
8835       && rtx_equal_p (x, reg)
8836       && ! FLOAT_MODE_P (GET_MODE (x))
8837       && ! FLOAT_MODE_P (GET_MODE (val)))
8838     return val;
8839
8840   if (cond == UNEQ && rtx_equal_p (x, reg))
8841     return val;
8842
8843   /* If X is (abs REG) and we know something about REG's relationship
8844      with zero, we may be able to simplify this.  */
8845
8846   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8847     switch (cond)
8848       {
8849       case GE:  case GT:  case EQ:
8850         return XEXP (x, 0);
8851       case LT:  case LE:
8852         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8853                                    XEXP (x, 0),
8854                                    GET_MODE (XEXP (x, 0)));
8855       default:
8856         break;
8857       }
8858
8859   /* The only other cases we handle are MIN, MAX, and comparisons if the
8860      operands are the same as REG and VAL.  */
8861
8862   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8863     {
8864       if (rtx_equal_p (XEXP (x, 0), val))
8865         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8866
8867       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8868         {
8869           if (COMPARISON_P (x))
8870             {
8871               if (comparison_dominates_p (cond, code))
8872                 return const_true_rtx;
8873
8874               code = reversed_comparison_code (x, NULL);
8875               if (code != UNKNOWN
8876                   && comparison_dominates_p (cond, code))
8877                 return const0_rtx;
8878               else
8879                 return x;
8880             }
8881           else if (code == SMAX || code == SMIN
8882                    || code == UMIN || code == UMAX)
8883             {
8884               int unsignedp = (code == UMIN || code == UMAX);
8885
8886               /* Do not reverse the condition when it is NE or EQ.
8887                  This is because we cannot conclude anything about
8888                  the value of 'SMAX (x, y)' when x is not equal to y,
8889                  but we can when x equals y.  */
8890               if ((code == SMAX || code == UMAX)
8891                   && ! (cond == EQ || cond == NE))
8892                 cond = reverse_condition (cond);
8893
8894               switch (cond)
8895                 {
8896                 case GE:   case GT:
8897                   return unsignedp ? x : XEXP (x, 1);
8898                 case LE:   case LT:
8899                   return unsignedp ? x : XEXP (x, 0);
8900                 case GEU:  case GTU:
8901                   return unsignedp ? XEXP (x, 1) : x;
8902                 case LEU:  case LTU:
8903                   return unsignedp ? XEXP (x, 0) : x;
8904                 default:
8905                   break;
8906                 }
8907             }
8908         }
8909     }
8910   else if (code == SUBREG)
8911     {
8912       machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8913       rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8914
8915       if (SUBREG_REG (x) != r)
8916         {
8917           /* We must simplify subreg here, before we lose track of the
8918              original inner_mode.  */
8919           new_rtx = simplify_subreg (GET_MODE (x), r,
8920                                  inner_mode, SUBREG_BYTE (x));
8921           if (new_rtx)
8922             return new_rtx;
8923           else
8924             SUBST (SUBREG_REG (x), r);
8925         }
8926
8927       return x;
8928     }
8929   /* We don't have to handle SIGN_EXTEND here, because even in the
8930      case of replacing something with a modeless CONST_INT, a
8931      CONST_INT is already (supposed to be) a valid sign extension for
8932      its narrower mode, which implies it's already properly
8933      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
8934      story is different.  */
8935   else if (code == ZERO_EXTEND)
8936     {
8937       machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8938       rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8939
8940       if (XEXP (x, 0) != r)
8941         {
8942           /* We must simplify the zero_extend here, before we lose
8943              track of the original inner_mode.  */
8944           new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8945                                           r, inner_mode);
8946           if (new_rtx)
8947             return new_rtx;
8948           else
8949             SUBST (XEXP (x, 0), r);
8950         }
8951
8952       return x;
8953     }
8954
8955   fmt = GET_RTX_FORMAT (code);
8956   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8957     {
8958       if (fmt[i] == 'e')
8959         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
8960       else if (fmt[i] == 'E')
8961         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8962           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
8963                                                 cond, reg, val));
8964     }
8965
8966   return x;
8967 }
8968 \f
8969 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
8970    assignment as a field assignment.  */
8971
8972 static int
8973 rtx_equal_for_field_assignment_p (rtx x, rtx y)
8974 {
8975   if (x == y || rtx_equal_p (x, y))
8976     return 1;
8977
8978   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
8979     return 0;
8980
8981   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
8982      Note that all SUBREGs of MEM are paradoxical; otherwise they
8983      would have been rewritten.  */
8984   if (MEM_P (x) && GET_CODE (y) == SUBREG
8985       && MEM_P (SUBREG_REG (y))
8986       && rtx_equal_p (SUBREG_REG (y),
8987                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
8988     return 1;
8989
8990   if (MEM_P (y) && GET_CODE (x) == SUBREG
8991       && MEM_P (SUBREG_REG (x))
8992       && rtx_equal_p (SUBREG_REG (x),
8993                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
8994     return 1;
8995
8996   /* We used to see if get_last_value of X and Y were the same but that's
8997      not correct.  In one direction, we'll cause the assignment to have
8998      the wrong destination and in the case, we'll import a register into this
8999      insn that might have already have been dead.   So fail if none of the
9000      above cases are true.  */
9001   return 0;
9002 }
9003 \f
9004 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9005    Return that assignment if so.
9006
9007    We only handle the most common cases.  */
9008
9009 static rtx
9010 make_field_assignment (rtx x)
9011 {
9012   rtx dest = SET_DEST (x);
9013   rtx src = SET_SRC (x);
9014   rtx assign;
9015   rtx rhs, lhs;
9016   HOST_WIDE_INT c1;
9017   HOST_WIDE_INT pos;
9018   unsigned HOST_WIDE_INT len;
9019   rtx other;
9020   machine_mode mode;
9021
9022   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9023      a clear of a one-bit field.  We will have changed it to
9024      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
9025      for a SUBREG.  */
9026
9027   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
9028       && CONST_INT_P (XEXP (XEXP (src, 0), 0))
9029       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
9030       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9031     {
9032       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9033                                 1, 1, 1, 0);
9034       if (assign != 0)
9035         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9036       return x;
9037     }
9038
9039   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
9040       && subreg_lowpart_p (XEXP (src, 0))
9041       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
9042           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
9043       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
9044       && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
9045       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
9046       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9047     {
9048       assign = make_extraction (VOIDmode, dest, 0,
9049                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
9050                                 1, 1, 1, 0);
9051       if (assign != 0)
9052         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9053       return x;
9054     }
9055
9056   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9057      one-bit field.  */
9058   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9059       && XEXP (XEXP (src, 0), 0) == const1_rtx
9060       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9061     {
9062       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9063                                 1, 1, 1, 0);
9064       if (assign != 0)
9065         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
9066       return x;
9067     }
9068
9069   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9070      SRC is an AND with all bits of that field set, then we can discard
9071      the AND.  */
9072   if (GET_CODE (dest) == ZERO_EXTRACT
9073       && CONST_INT_P (XEXP (dest, 1))
9074       && GET_CODE (src) == AND
9075       && CONST_INT_P (XEXP (src, 1)))
9076     {
9077       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9078       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9079       unsigned HOST_WIDE_INT ze_mask;
9080
9081       if (width >= HOST_BITS_PER_WIDE_INT)
9082         ze_mask = -1;
9083       else
9084         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9085
9086       /* Complete overlap.  We can remove the source AND.  */
9087       if ((and_mask & ze_mask) == ze_mask)
9088         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
9089
9090       /* Partial overlap.  We can reduce the source AND.  */
9091       if ((and_mask & ze_mask) != and_mask)
9092         {
9093           mode = GET_MODE (src);
9094           src = gen_rtx_AND (mode, XEXP (src, 0),
9095                              gen_int_mode (and_mask & ze_mask, mode));
9096           return gen_rtx_SET (VOIDmode, dest, src);
9097         }
9098     }
9099
9100   /* The other case we handle is assignments into a constant-position
9101      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
9102      a mask that has all one bits except for a group of zero bits and
9103      OTHER is known to have zeros where C1 has ones, this is such an
9104      assignment.  Compute the position and length from C1.  Shift OTHER
9105      to the appropriate position, force it to the required mode, and
9106      make the extraction.  Check for the AND in both operands.  */
9107
9108   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9109     return x;
9110
9111   rhs = expand_compound_operation (XEXP (src, 0));
9112   lhs = expand_compound_operation (XEXP (src, 1));
9113
9114   if (GET_CODE (rhs) == AND
9115       && CONST_INT_P (XEXP (rhs, 1))
9116       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9117     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9118   else if (GET_CODE (lhs) == AND
9119            && CONST_INT_P (XEXP (lhs, 1))
9120            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9121     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9122   else
9123     return x;
9124
9125   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9126   if (pos < 0 || pos + len > GET_MODE_PRECISION (GET_MODE (dest))
9127       || GET_MODE_PRECISION (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9128       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9129     return x;
9130
9131   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9132   if (assign == 0)
9133     return x;
9134
9135   /* The mode to use for the source is the mode of the assignment, or of
9136      what is inside a possible STRICT_LOW_PART.  */
9137   mode = (GET_CODE (assign) == STRICT_LOW_PART
9138           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9139
9140   /* Shift OTHER right POS places and make it the source, restricting it
9141      to the proper length and mode.  */
9142
9143   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9144                                                      GET_MODE (src),
9145                                                      other, pos),
9146                                dest);
9147   src = force_to_mode (src, mode,
9148                        GET_MODE_PRECISION (mode) >= HOST_BITS_PER_WIDE_INT
9149                        ? ~(unsigned HOST_WIDE_INT) 0
9150                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9151                        0);
9152
9153   /* If SRC is masked by an AND that does not make a difference in
9154      the value being stored, strip it.  */
9155   if (GET_CODE (assign) == ZERO_EXTRACT
9156       && CONST_INT_P (XEXP (assign, 1))
9157       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9158       && GET_CODE (src) == AND
9159       && CONST_INT_P (XEXP (src, 1))
9160       && UINTVAL (XEXP (src, 1))
9161          == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)
9162     src = XEXP (src, 0);
9163
9164   return gen_rtx_SET (VOIDmode, assign, src);
9165 }
9166 \f
9167 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9168    if so.  */
9169
9170 static rtx
9171 apply_distributive_law (rtx x)
9172 {
9173   enum rtx_code code = GET_CODE (x);
9174   enum rtx_code inner_code;
9175   rtx lhs, rhs, other;
9176   rtx tem;
9177
9178   /* Distributivity is not true for floating point as it can change the
9179      value.  So we don't do it unless -funsafe-math-optimizations.  */
9180   if (FLOAT_MODE_P (GET_MODE (x))
9181       && ! flag_unsafe_math_optimizations)
9182     return x;
9183
9184   /* The outer operation can only be one of the following:  */
9185   if (code != IOR && code != AND && code != XOR
9186       && code != PLUS && code != MINUS)
9187     return x;
9188
9189   lhs = XEXP (x, 0);
9190   rhs = XEXP (x, 1);
9191
9192   /* If either operand is a primitive we can't do anything, so get out
9193      fast.  */
9194   if (OBJECT_P (lhs) || OBJECT_P (rhs))
9195     return x;
9196
9197   lhs = expand_compound_operation (lhs);
9198   rhs = expand_compound_operation (rhs);
9199   inner_code = GET_CODE (lhs);
9200   if (inner_code != GET_CODE (rhs))
9201     return x;
9202
9203   /* See if the inner and outer operations distribute.  */
9204   switch (inner_code)
9205     {
9206     case LSHIFTRT:
9207     case ASHIFTRT:
9208     case AND:
9209     case IOR:
9210       /* These all distribute except over PLUS.  */
9211       if (code == PLUS || code == MINUS)
9212         return x;
9213       break;
9214
9215     case MULT:
9216       if (code != PLUS && code != MINUS)
9217         return x;
9218       break;
9219
9220     case ASHIFT:
9221       /* This is also a multiply, so it distributes over everything.  */
9222       break;
9223
9224     /* This used to handle SUBREG, but this turned out to be counter-
9225        productive, since (subreg (op ...)) usually is not handled by
9226        insn patterns, and this "optimization" therefore transformed
9227        recognizable patterns into unrecognizable ones.  Therefore the
9228        SUBREG case was removed from here.
9229
9230        It is possible that distributing SUBREG over arithmetic operations
9231        leads to an intermediate result than can then be optimized further,
9232        e.g. by moving the outer SUBREG to the other side of a SET as done
9233        in simplify_set.  This seems to have been the original intent of
9234        handling SUBREGs here.
9235
9236        However, with current GCC this does not appear to actually happen,
9237        at least on major platforms.  If some case is found where removing
9238        the SUBREG case here prevents follow-on optimizations, distributing
9239        SUBREGs ought to be re-added at that place, e.g. in simplify_set.  */
9240
9241     default:
9242       return x;
9243     }
9244
9245   /* Set LHS and RHS to the inner operands (A and B in the example
9246      above) and set OTHER to the common operand (C in the example).
9247      There is only one way to do this unless the inner operation is
9248      commutative.  */
9249   if (COMMUTATIVE_ARITH_P (lhs)
9250       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9251     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9252   else if (COMMUTATIVE_ARITH_P (lhs)
9253            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9254     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9255   else if (COMMUTATIVE_ARITH_P (lhs)
9256            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9257     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9258   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9259     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9260   else
9261     return x;
9262
9263   /* Form the new inner operation, seeing if it simplifies first.  */
9264   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9265
9266   /* There is one exception to the general way of distributing:
9267      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
9268   if (code == XOR && inner_code == IOR)
9269     {
9270       inner_code = AND;
9271       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9272     }
9273
9274   /* We may be able to continuing distributing the result, so call
9275      ourselves recursively on the inner operation before forming the
9276      outer operation, which we return.  */
9277   return simplify_gen_binary (inner_code, GET_MODE (x),
9278                               apply_distributive_law (tem), other);
9279 }
9280
9281 /* See if X is of the form (* (+ A B) C), and if so convert to
9282    (+ (* A C) (* B C)) and try to simplify.
9283
9284    Most of the time, this results in no change.  However, if some of
9285    the operands are the same or inverses of each other, simplifications
9286    will result.
9287
9288    For example, (and (ior A B) (not B)) can occur as the result of
9289    expanding a bit field assignment.  When we apply the distributive
9290    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9291    which then simplifies to (and (A (not B))).
9292
9293    Note that no checks happen on the validity of applying the inverse
9294    distributive law.  This is pointless since we can do it in the
9295    few places where this routine is called.
9296
9297    N is the index of the term that is decomposed (the arithmetic operation,
9298    i.e. (+ A B) in the first example above).  !N is the index of the term that
9299    is distributed, i.e. of C in the first example above.  */
9300 static rtx
9301 distribute_and_simplify_rtx (rtx x, int n)
9302 {
9303   machine_mode mode;
9304   enum rtx_code outer_code, inner_code;
9305   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9306
9307   /* Distributivity is not true for floating point as it can change the
9308      value.  So we don't do it unless -funsafe-math-optimizations.  */
9309   if (FLOAT_MODE_P (GET_MODE (x))
9310       && ! flag_unsafe_math_optimizations)
9311     return NULL_RTX;
9312
9313   decomposed = XEXP (x, n);
9314   if (!ARITHMETIC_P (decomposed))
9315     return NULL_RTX;
9316
9317   mode = GET_MODE (x);
9318   outer_code = GET_CODE (x);
9319   distributed = XEXP (x, !n);
9320
9321   inner_code = GET_CODE (decomposed);
9322   inner_op0 = XEXP (decomposed, 0);
9323   inner_op1 = XEXP (decomposed, 1);
9324
9325   /* Special case (and (xor B C) (not A)), which is equivalent to
9326      (xor (ior A B) (ior A C))  */
9327   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9328     {
9329       distributed = XEXP (distributed, 0);
9330       outer_code = IOR;
9331     }
9332
9333   if (n == 0)
9334     {
9335       /* Distribute the second term.  */
9336       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9337       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9338     }
9339   else
9340     {
9341       /* Distribute the first term.  */
9342       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9343       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9344     }
9345
9346   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9347                                                      new_op0, new_op1));
9348   if (GET_CODE (tmp) != outer_code
9349       && (set_src_cost (tmp, optimize_this_for_speed_p)
9350           < set_src_cost (x, optimize_this_for_speed_p)))
9351     return tmp;
9352
9353   return NULL_RTX;
9354 }
9355 \f
9356 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9357    in MODE.  Return an equivalent form, if different from (and VAROP
9358    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
9359
9360 static rtx
9361 simplify_and_const_int_1 (machine_mode mode, rtx varop,
9362                           unsigned HOST_WIDE_INT constop)
9363 {
9364   unsigned HOST_WIDE_INT nonzero;
9365   unsigned HOST_WIDE_INT orig_constop;
9366   rtx orig_varop;
9367   int i;
9368
9369   orig_varop = varop;
9370   orig_constop = constop;
9371   if (GET_CODE (varop) == CLOBBER)
9372     return NULL_RTX;
9373
9374   /* Simplify VAROP knowing that we will be only looking at some of the
9375      bits in it.
9376
9377      Note by passing in CONSTOP, we guarantee that the bits not set in
9378      CONSTOP are not significant and will never be examined.  We must
9379      ensure that is the case by explicitly masking out those bits
9380      before returning.  */
9381   varop = force_to_mode (varop, mode, constop, 0);
9382
9383   /* If VAROP is a CLOBBER, we will fail so return it.  */
9384   if (GET_CODE (varop) == CLOBBER)
9385     return varop;
9386
9387   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9388      to VAROP and return the new constant.  */
9389   if (CONST_INT_P (varop))
9390     return gen_int_mode (INTVAL (varop) & constop, mode);
9391
9392   /* See what bits may be nonzero in VAROP.  Unlike the general case of
9393      a call to nonzero_bits, here we don't care about bits outside
9394      MODE.  */
9395
9396   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9397
9398   /* Turn off all bits in the constant that are known to already be zero.
9399      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9400      which is tested below.  */
9401
9402   constop &= nonzero;
9403
9404   /* If we don't have any bits left, return zero.  */
9405   if (constop == 0)
9406     return const0_rtx;
9407
9408   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9409      a power of two, we can replace this with an ASHIFT.  */
9410   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9411       && (i = exact_log2 (constop)) >= 0)
9412     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9413
9414   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9415      or XOR, then try to apply the distributive law.  This may eliminate
9416      operations if either branch can be simplified because of the AND.
9417      It may also make some cases more complex, but those cases probably
9418      won't match a pattern either with or without this.  */
9419
9420   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9421     return
9422       gen_lowpart
9423         (mode,
9424          apply_distributive_law
9425          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9426                                simplify_and_const_int (NULL_RTX,
9427                                                        GET_MODE (varop),
9428                                                        XEXP (varop, 0),
9429                                                        constop),
9430                                simplify_and_const_int (NULL_RTX,
9431                                                        GET_MODE (varop),
9432                                                        XEXP (varop, 1),
9433                                                        constop))));
9434
9435   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9436      the AND and see if one of the operands simplifies to zero.  If so, we
9437      may eliminate it.  */
9438
9439   if (GET_CODE (varop) == PLUS
9440       && exact_log2 (constop + 1) >= 0)
9441     {
9442       rtx o0, o1;
9443
9444       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9445       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9446       if (o0 == const0_rtx)
9447         return o1;
9448       if (o1 == const0_rtx)
9449         return o0;
9450     }
9451
9452   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
9453   varop = gen_lowpart (mode, varop);
9454   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9455     return NULL_RTX;
9456
9457   /* If we are only masking insignificant bits, return VAROP.  */
9458   if (constop == nonzero)
9459     return varop;
9460
9461   if (varop == orig_varop && constop == orig_constop)
9462     return NULL_RTX;
9463
9464   /* Otherwise, return an AND.  */
9465   return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9466 }
9467
9468
9469 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9470    in MODE.
9471
9472    Return an equivalent form, if different from X.  Otherwise, return X.  If
9473    X is zero, we are to always construct the equivalent form.  */
9474
9475 static rtx
9476 simplify_and_const_int (rtx x, machine_mode mode, rtx varop,
9477                         unsigned HOST_WIDE_INT constop)
9478 {
9479   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9480   if (tem)
9481     return tem;
9482
9483   if (!x)
9484     x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9485                              gen_int_mode (constop, mode));
9486   if (GET_MODE (x) != mode)
9487     x = gen_lowpart (mode, x);
9488   return x;
9489 }
9490 \f
9491 /* Given a REG, X, compute which bits in X can be nonzero.
9492    We don't care about bits outside of those defined in MODE.
9493
9494    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9495    a shift, AND, or zero_extract, we can do better.  */
9496
9497 static rtx
9498 reg_nonzero_bits_for_combine (const_rtx x, machine_mode mode,
9499                               const_rtx known_x ATTRIBUTE_UNUSED,
9500                               machine_mode known_mode ATTRIBUTE_UNUSED,
9501                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9502                               unsigned HOST_WIDE_INT *nonzero)
9503 {
9504   rtx tem;
9505   reg_stat_type *rsp;
9506
9507   /* If X is a register whose nonzero bits value is current, use it.
9508      Otherwise, if X is a register whose value we can find, use that
9509      value.  Otherwise, use the previously-computed global nonzero bits
9510      for this register.  */
9511
9512   rsp = &reg_stat[REGNO (x)];
9513   if (rsp->last_set_value != 0
9514       && (rsp->last_set_mode == mode
9515           || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9516               && GET_MODE_CLASS (mode) == MODE_INT))
9517       && ((rsp->last_set_label >= label_tick_ebb_start
9518            && rsp->last_set_label < label_tick)
9519           || (rsp->last_set_label == label_tick
9520               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9521           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9522               && REG_N_SETS (REGNO (x)) == 1
9523               && !REGNO_REG_SET_P
9524                   (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
9525                    REGNO (x)))))
9526     {
9527       unsigned HOST_WIDE_INT mask = rsp->last_set_nonzero_bits;
9528
9529       if (GET_MODE_PRECISION (rsp->last_set_mode) < GET_MODE_PRECISION (mode))
9530         /* We don't know anything about the upper bits.  */
9531         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (rsp->last_set_mode);
9532
9533       *nonzero &= mask;
9534       return NULL;
9535     }
9536
9537   tem = get_last_value (x);
9538
9539   if (tem)
9540     {
9541 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9542       /* If X is narrower than MODE and TEM is a non-negative
9543          constant that would appear negative in the mode of X,
9544          sign-extend it for use in reg_nonzero_bits because some
9545          machines (maybe most) will actually do the sign-extension
9546          and this is the conservative approach.
9547
9548          ??? For 2.5, try to tighten up the MD files in this regard
9549          instead of this kludge.  */
9550
9551       if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode)
9552           && CONST_INT_P (tem)
9553           && INTVAL (tem) > 0
9554           && val_signbit_known_set_p (GET_MODE (x), INTVAL (tem)))
9555         tem = GEN_INT (INTVAL (tem) | ~GET_MODE_MASK (GET_MODE (x)));
9556 #endif
9557       return tem;
9558     }
9559   else if (nonzero_sign_valid && rsp->nonzero_bits)
9560     {
9561       unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9562
9563       if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode))
9564         /* We don't know anything about the upper bits.  */
9565         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9566
9567       *nonzero &= mask;
9568     }
9569
9570   return NULL;
9571 }
9572
9573 /* Return the number of bits at the high-order end of X that are known to
9574    be equal to the sign bit.  X will be used in mode MODE; if MODE is
9575    VOIDmode, X will be used in its own mode.  The returned value  will always
9576    be between 1 and the number of bits in MODE.  */
9577
9578 static rtx
9579 reg_num_sign_bit_copies_for_combine (const_rtx x, machine_mode mode,
9580                                      const_rtx known_x ATTRIBUTE_UNUSED,
9581                                      machine_mode known_mode
9582                                      ATTRIBUTE_UNUSED,
9583                                      unsigned int known_ret ATTRIBUTE_UNUSED,
9584                                      unsigned int *result)
9585 {
9586   rtx tem;
9587   reg_stat_type *rsp;
9588
9589   rsp = &reg_stat[REGNO (x)];
9590   if (rsp->last_set_value != 0
9591       && rsp->last_set_mode == mode
9592       && ((rsp->last_set_label >= label_tick_ebb_start
9593            && rsp->last_set_label < label_tick)
9594           || (rsp->last_set_label == label_tick
9595               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9596           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9597               && REG_N_SETS (REGNO (x)) == 1
9598               && !REGNO_REG_SET_P
9599                   (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
9600                    REGNO (x)))))
9601     {
9602       *result = rsp->last_set_sign_bit_copies;
9603       return NULL;
9604     }
9605
9606   tem = get_last_value (x);
9607   if (tem != 0)
9608     return tem;
9609
9610   if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9611       && GET_MODE_PRECISION (GET_MODE (x)) == GET_MODE_PRECISION (mode))
9612     *result = rsp->sign_bit_copies;
9613
9614   return NULL;
9615 }
9616 \f
9617 /* Return the number of "extended" bits there are in X, when interpreted
9618    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
9619    unsigned quantities, this is the number of high-order zero bits.
9620    For signed quantities, this is the number of copies of the sign bit
9621    minus 1.  In both case, this function returns the number of "spare"
9622    bits.  For example, if two quantities for which this function returns
9623    at least 1 are added, the addition is known not to overflow.
9624
9625    This function will always return 0 unless called during combine, which
9626    implies that it must be called from a define_split.  */
9627
9628 unsigned int
9629 extended_count (const_rtx x, machine_mode mode, int unsignedp)
9630 {
9631   if (nonzero_sign_valid == 0)
9632     return 0;
9633
9634   return (unsignedp
9635           ? (HWI_COMPUTABLE_MODE_P (mode)
9636              ? (unsigned int) (GET_MODE_PRECISION (mode) - 1
9637                                - floor_log2 (nonzero_bits (x, mode)))
9638              : 0)
9639           : num_sign_bit_copies (x, mode) - 1);
9640 }
9641
9642 /* This function is called from `simplify_shift_const' to merge two
9643    outer operations.  Specifically, we have already found that we need
9644    to perform operation *POP0 with constant *PCONST0 at the outermost
9645    position.  We would now like to also perform OP1 with constant CONST1
9646    (with *POP0 being done last).
9647
9648    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9649    the resulting operation.  *PCOMP_P is set to 1 if we would need to
9650    complement the innermost operand, otherwise it is unchanged.
9651
9652    MODE is the mode in which the operation will be done.  No bits outside
9653    the width of this mode matter.  It is assumed that the width of this mode
9654    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9655
9656    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
9657    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
9658    result is simply *PCONST0.
9659
9660    If the resulting operation cannot be expressed as one operation, we
9661    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
9662
9663 static int
9664 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, machine_mode mode, int *pcomp_p)
9665 {
9666   enum rtx_code op0 = *pop0;
9667   HOST_WIDE_INT const0 = *pconst0;
9668
9669   const0 &= GET_MODE_MASK (mode);
9670   const1 &= GET_MODE_MASK (mode);
9671
9672   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
9673   if (op0 == AND)
9674     const1 &= const0;
9675
9676   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
9677      if OP0 is SET.  */
9678
9679   if (op1 == UNKNOWN || op0 == SET)
9680     return 1;
9681
9682   else if (op0 == UNKNOWN)
9683     op0 = op1, const0 = const1;
9684
9685   else if (op0 == op1)
9686     {
9687       switch (op0)
9688         {
9689         case AND:
9690           const0 &= const1;
9691           break;
9692         case IOR:
9693           const0 |= const1;
9694           break;
9695         case XOR:
9696           const0 ^= const1;
9697           break;
9698         case PLUS:
9699           const0 += const1;
9700           break;
9701         case NEG:
9702           op0 = UNKNOWN;
9703           break;
9704         default:
9705           break;
9706         }
9707     }
9708
9709   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
9710   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9711     return 0;
9712
9713   /* If the two constants aren't the same, we can't do anything.  The
9714      remaining six cases can all be done.  */
9715   else if (const0 != const1)
9716     return 0;
9717
9718   else
9719     switch (op0)
9720       {
9721       case IOR:
9722         if (op1 == AND)
9723           /* (a & b) | b == b */
9724           op0 = SET;
9725         else /* op1 == XOR */
9726           /* (a ^ b) | b == a | b */
9727           {;}
9728         break;
9729
9730       case XOR:
9731         if (op1 == AND)
9732           /* (a & b) ^ b == (~a) & b */
9733           op0 = AND, *pcomp_p = 1;
9734         else /* op1 == IOR */
9735           /* (a | b) ^ b == a & ~b */
9736           op0 = AND, const0 = ~const0;
9737         break;
9738
9739       case AND:
9740         if (op1 == IOR)
9741           /* (a | b) & b == b */
9742         op0 = SET;
9743         else /* op1 == XOR */
9744           /* (a ^ b) & b) == (~a) & b */
9745           *pcomp_p = 1;
9746         break;
9747       default:
9748         break;
9749       }
9750
9751   /* Check for NO-OP cases.  */
9752   const0 &= GET_MODE_MASK (mode);
9753   if (const0 == 0
9754       && (op0 == IOR || op0 == XOR || op0 == PLUS))
9755     op0 = UNKNOWN;
9756   else if (const0 == 0 && op0 == AND)
9757     op0 = SET;
9758   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9759            && op0 == AND)
9760     op0 = UNKNOWN;
9761
9762   *pop0 = op0;
9763
9764   /* ??? Slightly redundant with the above mask, but not entirely.
9765      Moving this above means we'd have to sign-extend the mode mask
9766      for the final test.  */
9767   if (op0 != UNKNOWN && op0 != NEG)
9768     *pconst0 = trunc_int_for_mode (const0, mode);
9769
9770   return 1;
9771 }
9772 \f
9773 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9774    the shift in.  The original shift operation CODE is performed on OP in
9775    ORIG_MODE.  Return the wider mode MODE if we can perform the operation
9776    in that mode.  Return ORIG_MODE otherwise.  We can also assume that the
9777    result of the shift is subject to operation OUTER_CODE with operand
9778    OUTER_CONST.  */
9779
9780 static machine_mode
9781 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9782                       machine_mode orig_mode, machine_mode mode,
9783                       enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9784 {
9785   if (orig_mode == mode)
9786     return mode;
9787   gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
9788
9789   /* In general we can't perform in wider mode for right shift and rotate.  */
9790   switch (code)
9791     {
9792     case ASHIFTRT:
9793       /* We can still widen if the bits brought in from the left are identical
9794          to the sign bit of ORIG_MODE.  */
9795       if (num_sign_bit_copies (op, mode)
9796           > (unsigned) (GET_MODE_PRECISION (mode)
9797                         - GET_MODE_PRECISION (orig_mode)))
9798         return mode;
9799       return orig_mode;
9800
9801     case LSHIFTRT:
9802       /* Similarly here but with zero bits.  */
9803       if (HWI_COMPUTABLE_MODE_P (mode)
9804           && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9805         return mode;
9806
9807       /* We can also widen if the bits brought in will be masked off.  This
9808          operation is performed in ORIG_MODE.  */
9809       if (outer_code == AND)
9810         {
9811           int care_bits = low_bitmask_len (orig_mode, outer_const);
9812
9813           if (care_bits >= 0
9814               && GET_MODE_PRECISION (orig_mode) - care_bits >= count)
9815             return mode;
9816         }
9817       /* fall through */
9818
9819     case ROTATE:
9820       return orig_mode;
9821
9822     case ROTATERT:
9823       gcc_unreachable ();
9824
9825     default:
9826       return mode;
9827     }
9828 }
9829
9830 /* Simplify a shift of VAROP by ORIG_COUNT bits.  CODE says what kind
9831    of shift.  The result of the shift is RESULT_MODE.  Return NULL_RTX
9832    if we cannot simplify it.  Otherwise, return a simplified value.
9833
9834    The shift is normally computed in the widest mode we find in VAROP, as
9835    long as it isn't a different number of words than RESULT_MODE.  Exceptions
9836    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
9837
9838 static rtx
9839 simplify_shift_const_1 (enum rtx_code code, machine_mode result_mode,
9840                         rtx varop, int orig_count)
9841 {
9842   enum rtx_code orig_code = code;
9843   rtx orig_varop = varop;
9844   int count;
9845   machine_mode mode = result_mode;
9846   machine_mode shift_mode, tmode;
9847   unsigned int mode_words
9848     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9849   /* We form (outer_op (code varop count) (outer_const)).  */
9850   enum rtx_code outer_op = UNKNOWN;
9851   HOST_WIDE_INT outer_const = 0;
9852   int complement_p = 0;
9853   rtx new_rtx, x;
9854
9855   /* Make sure and truncate the "natural" shift on the way in.  We don't
9856      want to do this inside the loop as it makes it more difficult to
9857      combine shifts.  */
9858   if (SHIFT_COUNT_TRUNCATED)
9859     orig_count &= GET_MODE_BITSIZE (mode) - 1;
9860
9861   /* If we were given an invalid count, don't do anything except exactly
9862      what was requested.  */
9863
9864   if (orig_count < 0 || orig_count >= (int) GET_MODE_PRECISION (mode))
9865     return NULL_RTX;
9866
9867   count = orig_count;
9868
9869   /* Unless one of the branches of the `if' in this loop does a `continue',
9870      we will `break' the loop after the `if'.  */
9871
9872   while (count != 0)
9873     {
9874       /* If we have an operand of (clobber (const_int 0)), fail.  */
9875       if (GET_CODE (varop) == CLOBBER)
9876         return NULL_RTX;
9877
9878       /* Convert ROTATERT to ROTATE.  */
9879       if (code == ROTATERT)
9880         {
9881           unsigned int bitsize = GET_MODE_PRECISION (result_mode);
9882           code = ROTATE;
9883           if (VECTOR_MODE_P (result_mode))
9884             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9885           else
9886             count = bitsize - count;
9887         }
9888
9889       shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9890                                          mode, outer_op, outer_const);
9891
9892       /* Handle cases where the count is greater than the size of the mode
9893          minus 1.  For ASHIFT, use the size minus one as the count (this can
9894          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
9895          take the count modulo the size.  For other shifts, the result is
9896          zero.
9897
9898          Since these shifts are being produced by the compiler by combining
9899          multiple operations, each of which are defined, we know what the
9900          result is supposed to be.  */
9901
9902       if (count > (GET_MODE_PRECISION (shift_mode) - 1))
9903         {
9904           if (code == ASHIFTRT)
9905             count = GET_MODE_PRECISION (shift_mode) - 1;
9906           else if (code == ROTATE || code == ROTATERT)
9907             count %= GET_MODE_PRECISION (shift_mode);
9908           else
9909             {
9910               /* We can't simply return zero because there may be an
9911                  outer op.  */
9912               varop = const0_rtx;
9913               count = 0;
9914               break;
9915             }
9916         }
9917
9918       /* If we discovered we had to complement VAROP, leave.  Making a NOT
9919          here would cause an infinite loop.  */
9920       if (complement_p)
9921         break;
9922
9923       /* An arithmetic right shift of a quantity known to be -1 or 0
9924          is a no-op.  */
9925       if (code == ASHIFTRT
9926           && (num_sign_bit_copies (varop, shift_mode)
9927               == GET_MODE_PRECISION (shift_mode)))
9928         {
9929           count = 0;
9930           break;
9931         }
9932
9933       /* If we are doing an arithmetic right shift and discarding all but
9934          the sign bit copies, this is equivalent to doing a shift by the
9935          bitsize minus one.  Convert it into that shift because it will often
9936          allow other simplifications.  */
9937
9938       if (code == ASHIFTRT
9939           && (count + num_sign_bit_copies (varop, shift_mode)
9940               >= GET_MODE_PRECISION (shift_mode)))
9941         count = GET_MODE_PRECISION (shift_mode) - 1;
9942
9943       /* We simplify the tests below and elsewhere by converting
9944          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9945          `make_compound_operation' will convert it to an ASHIFTRT for
9946          those machines (such as VAX) that don't have an LSHIFTRT.  */
9947       if (code == ASHIFTRT
9948           && val_signbit_known_clear_p (shift_mode,
9949                                         nonzero_bits (varop, shift_mode)))
9950         code = LSHIFTRT;
9951
9952       if (((code == LSHIFTRT
9953             && HWI_COMPUTABLE_MODE_P (shift_mode)
9954             && !(nonzero_bits (varop, shift_mode) >> count))
9955            || (code == ASHIFT
9956                && HWI_COMPUTABLE_MODE_P (shift_mode)
9957                && !((nonzero_bits (varop, shift_mode) << count)
9958                     & GET_MODE_MASK (shift_mode))))
9959           && !side_effects_p (varop))
9960         varop = const0_rtx;
9961
9962       switch (GET_CODE (varop))
9963         {
9964         case SIGN_EXTEND:
9965         case ZERO_EXTEND:
9966         case SIGN_EXTRACT:
9967         case ZERO_EXTRACT:
9968           new_rtx = expand_compound_operation (varop);
9969           if (new_rtx != varop)
9970             {
9971               varop = new_rtx;
9972               continue;
9973             }
9974           break;
9975
9976         case MEM:
9977           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
9978              minus the width of a smaller mode, we can do this with a
9979              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
9980           if ((code == ASHIFTRT || code == LSHIFTRT)
9981               && ! mode_dependent_address_p (XEXP (varop, 0),
9982                                              MEM_ADDR_SPACE (varop))
9983               && ! MEM_VOLATILE_P (varop)
9984               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
9985                                          MODE_INT, 1)) != BLKmode)
9986             {
9987               new_rtx = adjust_address_nv (varop, tmode,
9988                                        BYTES_BIG_ENDIAN ? 0
9989                                        : count / BITS_PER_UNIT);
9990
9991               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
9992                                      : ZERO_EXTEND, mode, new_rtx);
9993               count = 0;
9994               continue;
9995             }
9996           break;
9997
9998         case SUBREG:
9999           /* If VAROP is a SUBREG, strip it as long as the inner operand has
10000              the same number of words as what we've seen so far.  Then store
10001              the widest mode in MODE.  */
10002           if (subreg_lowpart_p (varop)
10003               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
10004                   > GET_MODE_SIZE (GET_MODE (varop)))
10005               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
10006                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
10007                  == mode_words
10008               && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
10009               && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
10010             {
10011               varop = SUBREG_REG (varop);
10012               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
10013                 mode = GET_MODE (varop);
10014               continue;
10015             }
10016           break;
10017
10018         case MULT:
10019           /* Some machines use MULT instead of ASHIFT because MULT
10020              is cheaper.  But it is still better on those machines to
10021              merge two shifts into one.  */
10022           if (CONST_INT_P (XEXP (varop, 1))
10023               && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10024             {
10025               varop
10026                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
10027                                        XEXP (varop, 0),
10028                                        GEN_INT (exact_log2 (
10029                                                 UINTVAL (XEXP (varop, 1)))));
10030               continue;
10031             }
10032           break;
10033
10034         case UDIV:
10035           /* Similar, for when divides are cheaper.  */
10036           if (CONST_INT_P (XEXP (varop, 1))
10037               && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10038             {
10039               varop
10040                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
10041                                        XEXP (varop, 0),
10042                                        GEN_INT (exact_log2 (
10043                                                 UINTVAL (XEXP (varop, 1)))));
10044               continue;
10045             }
10046           break;
10047
10048         case ASHIFTRT:
10049           /* If we are extracting just the sign bit of an arithmetic
10050              right shift, that shift is not needed.  However, the sign
10051              bit of a wider mode may be different from what would be
10052              interpreted as the sign bit in a narrower mode, so, if
10053              the result is narrower, don't discard the shift.  */
10054           if (code == LSHIFTRT
10055               && count == (GET_MODE_BITSIZE (result_mode) - 1)
10056               && (GET_MODE_BITSIZE (result_mode)
10057                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
10058             {
10059               varop = XEXP (varop, 0);
10060               continue;
10061             }
10062
10063           /* ... fall through ...  */
10064
10065         case LSHIFTRT:
10066         case ASHIFT:
10067         case ROTATE:
10068           /* Here we have two nested shifts.  The result is usually the
10069              AND of a new shift with a mask.  We compute the result below.  */
10070           if (CONST_INT_P (XEXP (varop, 1))
10071               && INTVAL (XEXP (varop, 1)) >= 0
10072               && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (GET_MODE (varop))
10073               && HWI_COMPUTABLE_MODE_P (result_mode)
10074               && HWI_COMPUTABLE_MODE_P (mode)
10075               && !VECTOR_MODE_P (result_mode))
10076             {
10077               enum rtx_code first_code = GET_CODE (varop);
10078               unsigned int first_count = INTVAL (XEXP (varop, 1));
10079               unsigned HOST_WIDE_INT mask;
10080               rtx mask_rtx;
10081
10082               /* We have one common special case.  We can't do any merging if
10083                  the inner code is an ASHIFTRT of a smaller mode.  However, if
10084                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10085                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10086                  we can convert it to
10087                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10088                  This simplifies certain SIGN_EXTEND operations.  */
10089               if (code == ASHIFT && first_code == ASHIFTRT
10090                   && count == (GET_MODE_PRECISION (result_mode)
10091                                - GET_MODE_PRECISION (GET_MODE (varop))))
10092                 {
10093                   /* C3 has the low-order C1 bits zero.  */
10094
10095                   mask = GET_MODE_MASK (mode)
10096                          & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1);
10097
10098                   varop = simplify_and_const_int (NULL_RTX, result_mode,
10099                                                   XEXP (varop, 0), mask);
10100                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
10101                                                 varop, count);
10102                   count = first_count;
10103                   code = ASHIFTRT;
10104                   continue;
10105                 }
10106
10107               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10108                  than C1 high-order bits equal to the sign bit, we can convert
10109                  this to either an ASHIFT or an ASHIFTRT depending on the
10110                  two counts.
10111
10112                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
10113
10114               if (code == ASHIFTRT && first_code == ASHIFT
10115                   && GET_MODE (varop) == shift_mode
10116                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10117                       > first_count))
10118                 {
10119                   varop = XEXP (varop, 0);
10120                   count -= first_count;
10121                   if (count < 0)
10122                     {
10123                       count = -count;
10124                       code = ASHIFT;
10125                     }
10126
10127                   continue;
10128                 }
10129
10130               /* There are some cases we can't do.  If CODE is ASHIFTRT,
10131                  we can only do this if FIRST_CODE is also ASHIFTRT.
10132
10133                  We can't do the case when CODE is ROTATE and FIRST_CODE is
10134                  ASHIFTRT.
10135
10136                  If the mode of this shift is not the mode of the outer shift,
10137                  we can't do this if either shift is a right shift or ROTATE.
10138
10139                  Finally, we can't do any of these if the mode is too wide
10140                  unless the codes are the same.
10141
10142                  Handle the case where the shift codes are the same
10143                  first.  */
10144
10145               if (code == first_code)
10146                 {
10147                   if (GET_MODE (varop) != result_mode
10148                       && (code == ASHIFTRT || code == LSHIFTRT
10149                           || code == ROTATE))
10150                     break;
10151
10152                   count += first_count;
10153                   varop = XEXP (varop, 0);
10154                   continue;
10155                 }
10156
10157               if (code == ASHIFTRT
10158                   || (code == ROTATE && first_code == ASHIFTRT)
10159                   || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
10160                   || (GET_MODE (varop) != result_mode
10161                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
10162                           || first_code == ROTATE
10163                           || code == ROTATE)))
10164                 break;
10165
10166               /* To compute the mask to apply after the shift, shift the
10167                  nonzero bits of the inner shift the same way the
10168                  outer shift will.  */
10169
10170               mask_rtx = gen_int_mode (nonzero_bits (varop, GET_MODE (varop)),
10171                                        result_mode);
10172
10173               mask_rtx
10174                 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10175                                                    GEN_INT (count));
10176
10177               /* Give up if we can't compute an outer operation to use.  */
10178               if (mask_rtx == 0
10179                   || !CONST_INT_P (mask_rtx)
10180                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
10181                                         INTVAL (mask_rtx),
10182                                         result_mode, &complement_p))
10183                 break;
10184
10185               /* If the shifts are in the same direction, we add the
10186                  counts.  Otherwise, we subtract them.  */
10187               if ((code == ASHIFTRT || code == LSHIFTRT)
10188                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10189                 count += first_count;
10190               else
10191                 count -= first_count;
10192
10193               /* If COUNT is positive, the new shift is usually CODE,
10194                  except for the two exceptions below, in which case it is
10195                  FIRST_CODE.  If the count is negative, FIRST_CODE should
10196                  always be used  */
10197               if (count > 0
10198                   && ((first_code == ROTATE && code == ASHIFT)
10199                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
10200                 code = first_code;
10201               else if (count < 0)
10202                 code = first_code, count = -count;
10203
10204               varop = XEXP (varop, 0);
10205               continue;
10206             }
10207
10208           /* If we have (A << B << C) for any shift, we can convert this to
10209              (A << C << B).  This wins if A is a constant.  Only try this if
10210              B is not a constant.  */
10211
10212           else if (GET_CODE (varop) == code
10213                    && CONST_INT_P (XEXP (varop, 0))
10214                    && !CONST_INT_P (XEXP (varop, 1)))
10215             {
10216               rtx new_rtx = simplify_const_binary_operation (code, mode,
10217                                                          XEXP (varop, 0),
10218                                                          GEN_INT (count));
10219               varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10220               count = 0;
10221               continue;
10222             }
10223           break;
10224
10225         case NOT:
10226           if (VECTOR_MODE_P (mode))
10227             break;
10228
10229           /* Make this fit the case below.  */
10230           varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx);
10231           continue;
10232
10233         case IOR:
10234         case AND:
10235         case XOR:
10236           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10237              with C the size of VAROP - 1 and the shift is logical if
10238              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10239              we have an (le X 0) operation.   If we have an arithmetic shift
10240              and STORE_FLAG_VALUE is 1 or we have a logical shift with
10241              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
10242
10243           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10244               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10245               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10246               && (code == LSHIFTRT || code == ASHIFTRT)
10247               && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10248               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10249             {
10250               count = 0;
10251               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10252                                   const0_rtx);
10253
10254               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10255                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10256
10257               continue;
10258             }
10259
10260           /* If we have (shift (logical)), move the logical to the outside
10261              to allow it to possibly combine with another logical and the
10262              shift to combine with another shift.  This also canonicalizes to
10263              what a ZERO_EXTRACT looks like.  Also, some machines have
10264              (and (shift)) insns.  */
10265
10266           if (CONST_INT_P (XEXP (varop, 1))
10267               /* We can't do this if we have (ashiftrt (xor))  and the
10268                  constant has its sign bit set in shift_mode with shift_mode
10269                  wider than result_mode.  */
10270               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10271                    && result_mode != shift_mode
10272                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10273                                               shift_mode))
10274               && (new_rtx = simplify_const_binary_operation
10275                   (code, result_mode,
10276                    gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode),
10277                    GEN_INT (count))) != 0
10278               && CONST_INT_P (new_rtx)
10279               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10280                                   INTVAL (new_rtx), result_mode, &complement_p))
10281             {
10282               varop = XEXP (varop, 0);
10283               continue;
10284             }
10285
10286           /* If we can't do that, try to simplify the shift in each arm of the
10287              logical expression, make a new logical expression, and apply
10288              the inverse distributive law.  This also can't be done for
10289              (ashiftrt (xor)) where we've widened the shift and the constant
10290              changes the sign bit.  */
10291           if (CONST_INT_P (XEXP (varop, 1))
10292              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10293                   && result_mode != shift_mode
10294                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10295                                              shift_mode)))
10296             {
10297               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10298                                               XEXP (varop, 0), count);
10299               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10300                                               XEXP (varop, 1), count);
10301
10302               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10303                                            lhs, rhs);
10304               varop = apply_distributive_law (varop);
10305
10306               count = 0;
10307               continue;
10308             }
10309           break;
10310
10311         case EQ:
10312           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10313              says that the sign bit can be tested, FOO has mode MODE, C is
10314              GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10315              that may be nonzero.  */
10316           if (code == LSHIFTRT
10317               && XEXP (varop, 1) == const0_rtx
10318               && GET_MODE (XEXP (varop, 0)) == result_mode
10319               && count == (GET_MODE_PRECISION (result_mode) - 1)
10320               && HWI_COMPUTABLE_MODE_P (result_mode)
10321               && STORE_FLAG_VALUE == -1
10322               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10323               && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10324                                   &complement_p))
10325             {
10326               varop = XEXP (varop, 0);
10327               count = 0;
10328               continue;
10329             }
10330           break;
10331
10332         case NEG:
10333           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10334              than the number of bits in the mode is equivalent to A.  */
10335           if (code == LSHIFTRT
10336               && count == (GET_MODE_PRECISION (result_mode) - 1)
10337               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10338             {
10339               varop = XEXP (varop, 0);
10340               count = 0;
10341               continue;
10342             }
10343
10344           /* NEG commutes with ASHIFT since it is multiplication.  Move the
10345              NEG outside to allow shifts to combine.  */
10346           if (code == ASHIFT
10347               && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode,
10348                                   &complement_p))
10349             {
10350               varop = XEXP (varop, 0);
10351               continue;
10352             }
10353           break;
10354
10355         case PLUS:
10356           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10357              is one less than the number of bits in the mode is
10358              equivalent to (xor A 1).  */
10359           if (code == LSHIFTRT
10360               && count == (GET_MODE_PRECISION (result_mode) - 1)
10361               && XEXP (varop, 1) == constm1_rtx
10362               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10363               && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10364                                   &complement_p))
10365             {
10366               count = 0;
10367               varop = XEXP (varop, 0);
10368               continue;
10369             }
10370
10371           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10372              that might be nonzero in BAR are those being shifted out and those
10373              bits are known zero in FOO, we can replace the PLUS with FOO.
10374              Similarly in the other operand order.  This code occurs when
10375              we are computing the size of a variable-size array.  */
10376
10377           if ((code == ASHIFTRT || code == LSHIFTRT)
10378               && count < HOST_BITS_PER_WIDE_INT
10379               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10380               && (nonzero_bits (XEXP (varop, 1), result_mode)
10381                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10382             {
10383               varop = XEXP (varop, 0);
10384               continue;
10385             }
10386           else if ((code == ASHIFTRT || code == LSHIFTRT)
10387                    && count < HOST_BITS_PER_WIDE_INT
10388                    && HWI_COMPUTABLE_MODE_P (result_mode)
10389                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10390                             >> count)
10391                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10392                             & nonzero_bits (XEXP (varop, 1),
10393                                                  result_mode)))
10394             {
10395               varop = XEXP (varop, 1);
10396               continue;
10397             }
10398
10399           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
10400           if (code == ASHIFT
10401               && CONST_INT_P (XEXP (varop, 1))
10402               && (new_rtx = simplify_const_binary_operation
10403                   (ASHIFT, result_mode,
10404                    gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode),
10405                    GEN_INT (count))) != 0
10406               && CONST_INT_P (new_rtx)
10407               && merge_outer_ops (&outer_op, &outer_const, PLUS,
10408                                   INTVAL (new_rtx), result_mode, &complement_p))
10409             {
10410               varop = XEXP (varop, 0);
10411               continue;
10412             }
10413
10414           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10415              signbit', and attempt to change the PLUS to an XOR and move it to
10416              the outer operation as is done above in the AND/IOR/XOR case
10417              leg for shift(logical). See details in logical handling above
10418              for reasoning in doing so.  */
10419           if (code == LSHIFTRT
10420               && CONST_INT_P (XEXP (varop, 1))
10421               && mode_signbit_p (result_mode, XEXP (varop, 1))
10422               && (new_rtx = simplify_const_binary_operation
10423                   (code, result_mode,
10424                    gen_int_mode (INTVAL (XEXP (varop, 1)), result_mode),
10425                    GEN_INT (count))) != 0
10426               && CONST_INT_P (new_rtx)
10427               && merge_outer_ops (&outer_op, &outer_const, XOR,
10428                                   INTVAL (new_rtx), result_mode, &complement_p))
10429             {
10430               varop = XEXP (varop, 0);
10431               continue;
10432             }
10433
10434           break;
10435
10436         case MINUS:
10437           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10438              with C the size of VAROP - 1 and the shift is logical if
10439              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10440              we have a (gt X 0) operation.  If the shift is arithmetic with
10441              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10442              we have a (neg (gt X 0)) operation.  */
10443
10444           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10445               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10446               && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10447               && (code == LSHIFTRT || code == ASHIFTRT)
10448               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10449               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10450               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10451             {
10452               count = 0;
10453               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10454                                   const0_rtx);
10455
10456               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10457                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10458
10459               continue;
10460             }
10461           break;
10462
10463         case TRUNCATE:
10464           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10465              if the truncate does not affect the value.  */
10466           if (code == LSHIFTRT
10467               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10468               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10469               && (INTVAL (XEXP (XEXP (varop, 0), 1))
10470                   >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop, 0)))
10471                       - GET_MODE_PRECISION (GET_MODE (varop)))))
10472             {
10473               rtx varop_inner = XEXP (varop, 0);
10474
10475               varop_inner
10476                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10477                                     XEXP (varop_inner, 0),
10478                                     GEN_INT
10479                                     (count + INTVAL (XEXP (varop_inner, 1))));
10480               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10481               count = 0;
10482               continue;
10483             }
10484           break;
10485
10486         default:
10487           break;
10488         }
10489
10490       break;
10491     }
10492
10493   shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10494                                      outer_op, outer_const);
10495
10496   /* We have now finished analyzing the shift.  The result should be
10497      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
10498      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10499      to the result of the shift.  OUTER_CONST is the relevant constant,
10500      but we must turn off all bits turned off in the shift.  */
10501
10502   if (outer_op == UNKNOWN
10503       && orig_code == code && orig_count == count
10504       && varop == orig_varop
10505       && shift_mode == GET_MODE (varop))
10506     return NULL_RTX;
10507
10508   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
10509   varop = gen_lowpart (shift_mode, varop);
10510   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10511     return NULL_RTX;
10512
10513   /* If we have an outer operation and we just made a shift, it is
10514      possible that we could have simplified the shift were it not
10515      for the outer operation.  So try to do the simplification
10516      recursively.  */
10517
10518   if (outer_op != UNKNOWN)
10519     x = simplify_shift_const_1 (code, shift_mode, varop, count);
10520   else
10521     x = NULL_RTX;
10522
10523   if (x == NULL_RTX)
10524     x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10525
10526   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10527      turn off all the bits that the shift would have turned off.  */
10528   if (orig_code == LSHIFTRT && result_mode != shift_mode)
10529     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10530                                 GET_MODE_MASK (result_mode) >> orig_count);
10531
10532   /* Do the remainder of the processing in RESULT_MODE.  */
10533   x = gen_lowpart_or_truncate (result_mode, x);
10534
10535   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10536      operation.  */
10537   if (complement_p)
10538     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10539
10540   if (outer_op != UNKNOWN)
10541     {
10542       if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10543           && GET_MODE_PRECISION (result_mode) < HOST_BITS_PER_WIDE_INT)
10544         outer_const = trunc_int_for_mode (outer_const, result_mode);
10545
10546       if (outer_op == AND)
10547         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10548       else if (outer_op == SET)
10549         {
10550           /* This means that we have determined that the result is
10551              equivalent to a constant.  This should be rare.  */
10552           if (!side_effects_p (x))
10553             x = GEN_INT (outer_const);
10554         }
10555       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10556         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10557       else
10558         x = simplify_gen_binary (outer_op, result_mode, x,
10559                                  GEN_INT (outer_const));
10560     }
10561
10562   return x;
10563 }
10564
10565 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
10566    The result of the shift is RESULT_MODE.  If we cannot simplify it,
10567    return X or, if it is NULL, synthesize the expression with
10568    simplify_gen_binary.  Otherwise, return a simplified value.
10569
10570    The shift is normally computed in the widest mode we find in VAROP, as
10571    long as it isn't a different number of words than RESULT_MODE.  Exceptions
10572    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
10573
10574 static rtx
10575 simplify_shift_const (rtx x, enum rtx_code code, machine_mode result_mode,
10576                       rtx varop, int count)
10577 {
10578   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10579   if (tem)
10580     return tem;
10581
10582   if (!x)
10583     x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10584   if (GET_MODE (x) != result_mode)
10585     x = gen_lowpart (result_mode, x);
10586   return x;
10587 }
10588
10589 \f
10590 /* Like recog, but we receive the address of a pointer to a new pattern.
10591    We try to match the rtx that the pointer points to.
10592    If that fails, we may try to modify or replace the pattern,
10593    storing the replacement into the same pointer object.
10594
10595    Modifications include deletion or addition of CLOBBERs.
10596
10597    PNOTES is a pointer to a location where any REG_UNUSED notes added for
10598    the CLOBBERs are placed.
10599
10600    The value is the final insn code from the pattern ultimately matched,
10601    or -1.  */
10602
10603 static int
10604 recog_for_combine (rtx *pnewpat, rtx_insn *insn, rtx *pnotes)
10605 {
10606   rtx pat = *pnewpat;
10607   rtx pat_without_clobbers;
10608   int insn_code_number;
10609   int num_clobbers_to_add = 0;
10610   int i;
10611   rtx notes = NULL_RTX;
10612   rtx old_notes, old_pat;
10613   int old_icode;
10614
10615   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10616      we use to indicate that something didn't match.  If we find such a
10617      thing, force rejection.  */
10618   if (GET_CODE (pat) == PARALLEL)
10619     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10620       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10621           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10622         return -1;
10623
10624   old_pat = PATTERN (insn);
10625   old_notes = REG_NOTES (insn);
10626   PATTERN (insn) = pat;
10627   REG_NOTES (insn) = NULL_RTX;
10628
10629   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10630   if (dump_file && (dump_flags & TDF_DETAILS))
10631     {
10632       if (insn_code_number < 0)
10633         fputs ("Failed to match this instruction:\n", dump_file);
10634       else
10635         fputs ("Successfully matched this instruction:\n", dump_file);
10636       print_rtl_single (dump_file, pat);
10637     }
10638
10639   /* If it isn't, there is the possibility that we previously had an insn
10640      that clobbered some register as a side effect, but the combined
10641      insn doesn't need to do that.  So try once more without the clobbers
10642      unless this represents an ASM insn.  */
10643
10644   if (insn_code_number < 0 && ! check_asm_operands (pat)
10645       && GET_CODE (pat) == PARALLEL)
10646     {
10647       int pos;
10648
10649       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10650         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10651           {
10652             if (i != pos)
10653               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10654             pos++;
10655           }
10656
10657       SUBST_INT (XVECLEN (pat, 0), pos);
10658
10659       if (pos == 1)
10660         pat = XVECEXP (pat, 0, 0);
10661
10662       PATTERN (insn) = pat;
10663       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10664       if (dump_file && (dump_flags & TDF_DETAILS))
10665         {
10666           if (insn_code_number < 0)
10667             fputs ("Failed to match this instruction:\n", dump_file);
10668           else
10669             fputs ("Successfully matched this instruction:\n", dump_file);
10670           print_rtl_single (dump_file, pat);
10671         }
10672     }
10673
10674   pat_without_clobbers = pat;
10675
10676   PATTERN (insn) = old_pat;
10677   REG_NOTES (insn) = old_notes;
10678
10679   /* Recognize all noop sets, these will be killed by followup pass.  */
10680   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10681     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10682
10683   /* If we had any clobbers to add, make a new pattern than contains
10684      them.  Then check to make sure that all of them are dead.  */
10685   if (num_clobbers_to_add)
10686     {
10687       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10688                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
10689                                                   ? (XVECLEN (pat, 0)
10690                                                      + num_clobbers_to_add)
10691                                                   : num_clobbers_to_add + 1));
10692
10693       if (GET_CODE (pat) == PARALLEL)
10694         for (i = 0; i < XVECLEN (pat, 0); i++)
10695           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10696       else
10697         XVECEXP (newpat, 0, 0) = pat;
10698
10699       add_clobbers (newpat, insn_code_number);
10700
10701       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10702            i < XVECLEN (newpat, 0); i++)
10703         {
10704           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10705               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10706             return -1;
10707           if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10708             {
10709               gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10710               notes = alloc_reg_note (REG_UNUSED,
10711                                       XEXP (XVECEXP (newpat, 0, i), 0), notes);
10712             }
10713         }
10714       pat = newpat;
10715     }
10716
10717   if (insn_code_number >= 0
10718       && insn_code_number != NOOP_MOVE_INSN_CODE)
10719     {
10720       old_pat = PATTERN (insn);
10721       old_notes = REG_NOTES (insn);
10722       old_icode = INSN_CODE (insn);
10723       PATTERN (insn) = pat;
10724       REG_NOTES (insn) = notes;
10725
10726       /* Allow targets to reject combined insn.  */
10727       if (!targetm.legitimate_combined_insn (insn))
10728         {
10729           if (dump_file && (dump_flags & TDF_DETAILS))
10730             fputs ("Instruction not appropriate for target.",
10731                    dump_file);
10732
10733           /* Callers expect recog_for_combine to strip
10734              clobbers from the pattern on failure.  */
10735           pat = pat_without_clobbers;
10736           notes = NULL_RTX;
10737
10738           insn_code_number = -1;
10739         }
10740
10741       PATTERN (insn) = old_pat;
10742       REG_NOTES (insn) = old_notes;
10743       INSN_CODE (insn) = old_icode;
10744     }
10745
10746   *pnewpat = pat;
10747   *pnotes = notes;
10748
10749   return insn_code_number;
10750 }
10751 \f
10752 /* Like gen_lowpart_general but for use by combine.  In combine it
10753    is not possible to create any new pseudoregs.  However, it is
10754    safe to create invalid memory addresses, because combine will
10755    try to recognize them and all they will do is make the combine
10756    attempt fail.
10757
10758    If for some reason this cannot do its job, an rtx
10759    (clobber (const_int 0)) is returned.
10760    An insn containing that will not be recognized.  */
10761
10762 static rtx
10763 gen_lowpart_for_combine (machine_mode omode, rtx x)
10764 {
10765   machine_mode imode = GET_MODE (x);
10766   unsigned int osize = GET_MODE_SIZE (omode);
10767   unsigned int isize = GET_MODE_SIZE (imode);
10768   rtx result;
10769
10770   if (omode == imode)
10771     return x;
10772
10773   /* We can only support MODE being wider than a word if X is a
10774      constant integer or has a mode the same size.  */
10775   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10776       && ! (CONST_SCALAR_INT_P (x) || isize == osize))
10777     goto fail;
10778
10779   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
10780      won't know what to do.  So we will strip off the SUBREG here and
10781      process normally.  */
10782   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10783     {
10784       x = SUBREG_REG (x);
10785
10786       /* For use in case we fall down into the address adjustments
10787          further below, we need to adjust the known mode and size of
10788          x; imode and isize, since we just adjusted x.  */
10789       imode = GET_MODE (x);
10790
10791       if (imode == omode)
10792         return x;
10793
10794       isize = GET_MODE_SIZE (imode);
10795     }
10796
10797   result = gen_lowpart_common (omode, x);
10798
10799   if (result)
10800     return result;
10801
10802   if (MEM_P (x))
10803     {
10804       int offset = 0;
10805
10806       /* Refuse to work on a volatile memory ref or one with a mode-dependent
10807          address.  */
10808       if (MEM_VOLATILE_P (x)
10809           || mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x)))
10810         goto fail;
10811
10812       /* If we want to refer to something bigger than the original memref,
10813          generate a paradoxical subreg instead.  That will force a reload
10814          of the original memref X.  */
10815       if (isize < osize)
10816         return gen_rtx_SUBREG (omode, x, 0);
10817
10818       if (WORDS_BIG_ENDIAN)
10819         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10820
10821       /* Adjust the address so that the address-after-the-data is
10822          unchanged.  */
10823       if (BYTES_BIG_ENDIAN)
10824         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10825
10826       return adjust_address_nv (x, omode, offset);
10827     }
10828
10829   /* If X is a comparison operator, rewrite it in a new mode.  This
10830      probably won't match, but may allow further simplifications.  */
10831   else if (COMPARISON_P (x))
10832     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10833
10834   /* If we couldn't simplify X any other way, just enclose it in a
10835      SUBREG.  Normally, this SUBREG won't match, but some patterns may
10836      include an explicit SUBREG or we may simplify it further in combine.  */
10837   else
10838     {
10839       int offset = 0;
10840       rtx res;
10841
10842       offset = subreg_lowpart_offset (omode, imode);
10843       if (imode == VOIDmode)
10844         {
10845           imode = int_mode_for_mode (omode);
10846           x = gen_lowpart_common (imode, x);
10847           if (x == NULL)
10848             goto fail;
10849         }
10850       res = simplify_gen_subreg (omode, x, imode, offset);
10851       if (res)
10852         return res;
10853     }
10854
10855  fail:
10856   return gen_rtx_CLOBBER (omode, const0_rtx);
10857 }
10858 \f
10859 /* Try to simplify a comparison between OP0 and a constant OP1,
10860    where CODE is the comparison code that will be tested, into a
10861    (CODE OP0 const0_rtx) form.
10862
10863    The result is a possibly different comparison code to use.
10864    *POP1 may be updated.  */
10865
10866 static enum rtx_code
10867 simplify_compare_const (enum rtx_code code, machine_mode mode,
10868                         rtx op0, rtx *pop1)
10869 {
10870   unsigned int mode_width = GET_MODE_PRECISION (mode);
10871   HOST_WIDE_INT const_op = INTVAL (*pop1);
10872
10873   /* Get the constant we are comparing against and turn off all bits
10874      not on in our mode.  */
10875   if (mode != VOIDmode)
10876     const_op = trunc_int_for_mode (const_op, mode);
10877
10878   /* If we are comparing against a constant power of two and the value
10879      being compared can only have that single bit nonzero (e.g., it was
10880      `and'ed with that bit), we can replace this with a comparison
10881      with zero.  */
10882   if (const_op
10883       && (code == EQ || code == NE || code == GE || code == GEU
10884           || code == LT || code == LTU)
10885       && mode_width - 1 < HOST_BITS_PER_WIDE_INT
10886       && exact_log2 (const_op & GET_MODE_MASK (mode)) >= 0
10887       && (nonzero_bits (op0, mode)
10888           == (unsigned HOST_WIDE_INT) (const_op & GET_MODE_MASK (mode))))
10889     {
10890       code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10891       const_op = 0;
10892     }
10893
10894   /* Similarly, if we are comparing a value known to be either -1 or
10895      0 with -1, change it to the opposite comparison against zero.  */
10896   if (const_op == -1
10897       && (code == EQ || code == NE || code == GT || code == LE
10898           || code == GEU || code == LTU)
10899       && num_sign_bit_copies (op0, mode) == mode_width)
10900     {
10901       code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10902       const_op = 0;
10903     }
10904
10905   /* Do some canonicalizations based on the comparison code.  We prefer
10906      comparisons against zero and then prefer equality comparisons.
10907      If we can reduce the size of a constant, we will do that too.  */
10908   switch (code)
10909     {
10910     case LT:
10911       /* < C is equivalent to <= (C - 1) */
10912       if (const_op > 0)
10913         {
10914           const_op -= 1;
10915           code = LE;
10916           /* ... fall through to LE case below.  */
10917         }
10918       else
10919         break;
10920
10921     case LE:
10922       /* <= C is equivalent to < (C + 1); we do this for C < 0  */
10923       if (const_op < 0)
10924         {
10925           const_op += 1;
10926           code = LT;
10927         }
10928
10929       /* If we are doing a <= 0 comparison on a value known to have
10930          a zero sign bit, we can replace this with == 0.  */
10931       else if (const_op == 0
10932                && mode_width - 1 < HOST_BITS_PER_WIDE_INT
10933                && (nonzero_bits (op0, mode)
10934                    & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10935                == 0)
10936         code = EQ;
10937       break;
10938
10939     case GE:
10940       /* >= C is equivalent to > (C - 1).  */
10941       if (const_op > 0)
10942         {
10943           const_op -= 1;
10944           code = GT;
10945           /* ... fall through to GT below.  */
10946         }
10947       else
10948         break;
10949
10950     case GT:
10951       /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
10952       if (const_op < 0)
10953         {
10954           const_op += 1;
10955           code = GE;
10956         }
10957
10958       /* If we are doing a > 0 comparison on a value known to have
10959          a zero sign bit, we can replace this with != 0.  */
10960       else if (const_op == 0
10961                && mode_width - 1 < HOST_BITS_PER_WIDE_INT
10962                && (nonzero_bits (op0, mode)
10963                    & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10964                == 0)
10965         code = NE;
10966       break;
10967
10968     case LTU:
10969       /* < C is equivalent to <= (C - 1).  */
10970       if (const_op > 0)
10971         {
10972           const_op -= 1;
10973           code = LEU;
10974           /* ... fall through ...  */
10975         }
10976       /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
10977       else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT
10978                && (unsigned HOST_WIDE_INT) const_op
10979                == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
10980         {
10981           const_op = 0;
10982           code = GE;
10983           break;
10984         }
10985       else
10986         break;
10987
10988     case LEU:
10989       /* unsigned <= 0 is equivalent to == 0 */
10990       if (const_op == 0)
10991         code = EQ;
10992       /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
10993       else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT
10994                && (unsigned HOST_WIDE_INT) const_op
10995                == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
10996         {
10997           const_op = 0;
10998           code = GE;
10999         }
11000       break;
11001
11002     case GEU:
11003       /* >= C is equivalent to > (C - 1).  */
11004       if (const_op > 1)
11005         {
11006           const_op -= 1;
11007           code = GTU;
11008           /* ... fall through ...  */
11009         }
11010
11011       /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
11012       else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT
11013                && (unsigned HOST_WIDE_INT) const_op
11014                == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11015         {
11016           const_op = 0;
11017           code = LT;
11018           break;
11019         }
11020       else
11021         break;
11022
11023     case GTU:
11024       /* unsigned > 0 is equivalent to != 0 */
11025       if (const_op == 0)
11026         code = NE;
11027       /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
11028       else if (mode_width - 1 < HOST_BITS_PER_WIDE_INT
11029                && (unsigned HOST_WIDE_INT) const_op
11030                == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11031         {
11032           const_op = 0;
11033           code = LT;
11034         }
11035       break;
11036
11037     default:
11038       break;
11039     }
11040
11041   *pop1 = GEN_INT (const_op);
11042   return code;
11043 }
11044 \f
11045 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11046    comparison code that will be tested.
11047
11048    The result is a possibly different comparison code to use.  *POP0 and
11049    *POP1 may be updated.
11050
11051    It is possible that we might detect that a comparison is either always
11052    true or always false.  However, we do not perform general constant
11053    folding in combine, so this knowledge isn't useful.  Such tautologies
11054    should have been detected earlier.  Hence we ignore all such cases.  */
11055
11056 static enum rtx_code
11057 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
11058 {
11059   rtx op0 = *pop0;
11060   rtx op1 = *pop1;
11061   rtx tem, tem1;
11062   int i;
11063   machine_mode mode, tmode;
11064
11065   /* Try a few ways of applying the same transformation to both operands.  */
11066   while (1)
11067     {
11068 #ifndef WORD_REGISTER_OPERATIONS
11069       /* The test below this one won't handle SIGN_EXTENDs on these machines,
11070          so check specially.  */
11071       if (code != GTU && code != GEU && code != LTU && code != LEU
11072           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
11073           && GET_CODE (XEXP (op0, 0)) == ASHIFT
11074           && GET_CODE (XEXP (op1, 0)) == ASHIFT
11075           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
11076           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
11077           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
11078               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
11079           && CONST_INT_P (XEXP (op0, 1))
11080           && XEXP (op0, 1) == XEXP (op1, 1)
11081           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11082           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
11083           && (INTVAL (XEXP (op0, 1))
11084               == (GET_MODE_PRECISION (GET_MODE (op0))
11085                   - (GET_MODE_PRECISION
11086                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
11087         {
11088           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
11089           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
11090         }
11091 #endif
11092
11093       /* If both operands are the same constant shift, see if we can ignore the
11094          shift.  We can if the shift is a rotate or if the bits shifted out of
11095          this shift are known to be zero for both inputs and if the type of
11096          comparison is compatible with the shift.  */
11097       if (GET_CODE (op0) == GET_CODE (op1)
11098           && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
11099           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
11100               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
11101                   && (code != GT && code != LT && code != GE && code != LE))
11102               || (GET_CODE (op0) == ASHIFTRT
11103                   && (code != GTU && code != LTU
11104                       && code != GEU && code != LEU)))
11105           && CONST_INT_P (XEXP (op0, 1))
11106           && INTVAL (XEXP (op0, 1)) >= 0
11107           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11108           && XEXP (op0, 1) == XEXP (op1, 1))
11109         {
11110           machine_mode mode = GET_MODE (op0);
11111           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11112           int shift_count = INTVAL (XEXP (op0, 1));
11113
11114           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
11115             mask &= (mask >> shift_count) << shift_count;
11116           else if (GET_CODE (op0) == ASHIFT)
11117             mask = (mask & (mask << shift_count)) >> shift_count;
11118
11119           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
11120               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
11121             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
11122           else
11123             break;
11124         }
11125
11126       /* If both operands are AND's of a paradoxical SUBREG by constant, the
11127          SUBREGs are of the same mode, and, in both cases, the AND would
11128          be redundant if the comparison was done in the narrower mode,
11129          do the comparison in the narrower mode (e.g., we are AND'ing with 1
11130          and the operand's possibly nonzero bits are 0xffffff01; in that case
11131          if we only care about QImode, we don't need the AND).  This case
11132          occurs if the output mode of an scc insn is not SImode and
11133          STORE_FLAG_VALUE == 1 (e.g., the 386).
11134
11135          Similarly, check for a case where the AND's are ZERO_EXTEND
11136          operations from some narrower mode even though a SUBREG is not
11137          present.  */
11138
11139       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
11140                && CONST_INT_P (XEXP (op0, 1))
11141                && CONST_INT_P (XEXP (op1, 1)))
11142         {
11143           rtx inner_op0 = XEXP (op0, 0);
11144           rtx inner_op1 = XEXP (op1, 0);
11145           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
11146           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
11147           int changed = 0;
11148
11149           if (paradoxical_subreg_p (inner_op0)
11150               && GET_CODE (inner_op1) == SUBREG
11151               && (GET_MODE (SUBREG_REG (inner_op0))
11152                   == GET_MODE (SUBREG_REG (inner_op1)))
11153               && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0)))
11154                   <= HOST_BITS_PER_WIDE_INT)
11155               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
11156                                              GET_MODE (SUBREG_REG (inner_op0)))))
11157               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
11158                                              GET_MODE (SUBREG_REG (inner_op1))))))
11159             {
11160               op0 = SUBREG_REG (inner_op0);
11161               op1 = SUBREG_REG (inner_op1);
11162
11163               /* The resulting comparison is always unsigned since we masked
11164                  off the original sign bit.  */
11165               code = unsigned_condition (code);
11166
11167               changed = 1;
11168             }
11169
11170           else if (c0 == c1)
11171             for (tmode = GET_CLASS_NARROWEST_MODE
11172                  (GET_MODE_CLASS (GET_MODE (op0)));
11173                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
11174               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
11175                 {
11176                   op0 = gen_lowpart (tmode, inner_op0);
11177                   op1 = gen_lowpart (tmode, inner_op1);
11178                   code = unsigned_condition (code);
11179                   changed = 1;
11180                   break;
11181                 }
11182
11183           if (! changed)
11184             break;
11185         }
11186
11187       /* If both operands are NOT, we can strip off the outer operation
11188          and adjust the comparison code for swapped operands; similarly for
11189          NEG, except that this must be an equality comparison.  */
11190       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
11191                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
11192                    && (code == EQ || code == NE)))
11193         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
11194
11195       else
11196         break;
11197     }
11198
11199   /* If the first operand is a constant, swap the operands and adjust the
11200      comparison code appropriately, but don't do this if the second operand
11201      is already a constant integer.  */
11202   if (swap_commutative_operands_p (op0, op1))
11203     {
11204       tem = op0, op0 = op1, op1 = tem;
11205       code = swap_condition (code);
11206     }
11207
11208   /* We now enter a loop during which we will try to simplify the comparison.
11209      For the most part, we only are concerned with comparisons with zero,
11210      but some things may really be comparisons with zero but not start
11211      out looking that way.  */
11212
11213   while (CONST_INT_P (op1))
11214     {
11215       machine_mode mode = GET_MODE (op0);
11216       unsigned int mode_width = GET_MODE_PRECISION (mode);
11217       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11218       int equality_comparison_p;
11219       int sign_bit_comparison_p;
11220       int unsigned_comparison_p;
11221       HOST_WIDE_INT const_op;
11222
11223       /* We only want to handle integral modes.  This catches VOIDmode,
11224          CCmode, and the floating-point modes.  An exception is that we
11225          can handle VOIDmode if OP0 is a COMPARE or a comparison
11226          operation.  */
11227
11228       if (GET_MODE_CLASS (mode) != MODE_INT
11229           && ! (mode == VOIDmode
11230                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
11231         break;
11232
11233       /* Try to simplify the compare to constant, possibly changing the
11234          comparison op, and/or changing op1 to zero.  */
11235       code = simplify_compare_const (code, mode, op0, &op1);
11236       const_op = INTVAL (op1);
11237
11238       /* Compute some predicates to simplify code below.  */
11239
11240       equality_comparison_p = (code == EQ || code == NE);
11241       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11242       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11243                                || code == GEU);
11244
11245       /* If this is a sign bit comparison and we can do arithmetic in
11246          MODE, say that we will only be needing the sign bit of OP0.  */
11247       if (sign_bit_comparison_p && HWI_COMPUTABLE_MODE_P (mode))
11248         op0 = force_to_mode (op0, mode,
11249                              (unsigned HOST_WIDE_INT) 1
11250                              << (GET_MODE_PRECISION (mode) - 1),
11251                              0);
11252
11253       /* Now try cases based on the opcode of OP0.  If none of the cases
11254          does a "continue", we exit this loop immediately after the
11255          switch.  */
11256
11257       switch (GET_CODE (op0))
11258         {
11259         case ZERO_EXTRACT:
11260           /* If we are extracting a single bit from a variable position in
11261              a constant that has only a single bit set and are comparing it
11262              with zero, we can convert this into an equality comparison
11263              between the position and the location of the single bit.  */
11264           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11265              have already reduced the shift count modulo the word size.  */
11266           if (!SHIFT_COUNT_TRUNCATED
11267               && CONST_INT_P (XEXP (op0, 0))
11268               && XEXP (op0, 1) == const1_rtx
11269               && equality_comparison_p && const_op == 0
11270               && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
11271             {
11272               if (BITS_BIG_ENDIAN)
11273                 i = BITS_PER_WORD - 1 - i;
11274
11275               op0 = XEXP (op0, 2);
11276               op1 = GEN_INT (i);
11277               const_op = i;
11278
11279               /* Result is nonzero iff shift count is equal to I.  */
11280               code = reverse_condition (code);
11281               continue;
11282             }
11283
11284           /* ... fall through ...  */
11285
11286         case SIGN_EXTRACT:
11287           tem = expand_compound_operation (op0);
11288           if (tem != op0)
11289             {
11290               op0 = tem;
11291               continue;
11292             }
11293           break;
11294
11295         case NOT:
11296           /* If testing for equality, we can take the NOT of the constant.  */
11297           if (equality_comparison_p
11298               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11299             {
11300               op0 = XEXP (op0, 0);
11301               op1 = tem;
11302               continue;
11303             }
11304
11305           /* If just looking at the sign bit, reverse the sense of the
11306              comparison.  */
11307           if (sign_bit_comparison_p)
11308             {
11309               op0 = XEXP (op0, 0);
11310               code = (code == GE ? LT : GE);
11311               continue;
11312             }
11313           break;
11314
11315         case NEG:
11316           /* If testing for equality, we can take the NEG of the constant.  */
11317           if (equality_comparison_p
11318               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11319             {
11320               op0 = XEXP (op0, 0);
11321               op1 = tem;
11322               continue;
11323             }
11324
11325           /* The remaining cases only apply to comparisons with zero.  */
11326           if (const_op != 0)
11327             break;
11328
11329           /* When X is ABS or is known positive,
11330              (neg X) is < 0 if and only if X != 0.  */
11331
11332           if (sign_bit_comparison_p
11333               && (GET_CODE (XEXP (op0, 0)) == ABS
11334                   || (mode_width <= HOST_BITS_PER_WIDE_INT
11335                       && (nonzero_bits (XEXP (op0, 0), mode)
11336                           & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11337                          == 0)))
11338             {
11339               op0 = XEXP (op0, 0);
11340               code = (code == LT ? NE : EQ);
11341               continue;
11342             }
11343
11344           /* If we have NEG of something whose two high-order bits are the
11345              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
11346           if (num_sign_bit_copies (op0, mode) >= 2)
11347             {
11348               op0 = XEXP (op0, 0);
11349               code = swap_condition (code);
11350               continue;
11351             }
11352           break;
11353
11354         case ROTATE:
11355           /* If we are testing equality and our count is a constant, we
11356              can perform the inverse operation on our RHS.  */
11357           if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11358               && (tem = simplify_binary_operation (ROTATERT, mode,
11359                                                    op1, XEXP (op0, 1))) != 0)
11360             {
11361               op0 = XEXP (op0, 0);
11362               op1 = tem;
11363               continue;
11364             }
11365
11366           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11367              a particular bit.  Convert it to an AND of a constant of that
11368              bit.  This will be converted into a ZERO_EXTRACT.  */
11369           if (const_op == 0 && sign_bit_comparison_p
11370               && CONST_INT_P (XEXP (op0, 1))
11371               && mode_width <= HOST_BITS_PER_WIDE_INT)
11372             {
11373               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11374                                             ((unsigned HOST_WIDE_INT) 1
11375                                              << (mode_width - 1
11376                                                  - INTVAL (XEXP (op0, 1)))));
11377               code = (code == LT ? NE : EQ);
11378               continue;
11379             }
11380
11381           /* Fall through.  */
11382
11383         case ABS:
11384           /* ABS is ignorable inside an equality comparison with zero.  */
11385           if (const_op == 0 && equality_comparison_p)
11386             {
11387               op0 = XEXP (op0, 0);
11388               continue;
11389             }
11390           break;
11391
11392         case SIGN_EXTEND:
11393           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11394              (compare FOO CONST) if CONST fits in FOO's mode and we
11395              are either testing inequality or have an unsigned
11396              comparison with ZERO_EXTEND or a signed comparison with
11397              SIGN_EXTEND.  But don't do it if we don't have a compare
11398              insn of the given mode, since we'd have to revert it
11399              later on, and then we wouldn't know whether to sign- or
11400              zero-extend.  */
11401           mode = GET_MODE (XEXP (op0, 0));
11402           if (GET_MODE_CLASS (mode) == MODE_INT
11403               && ! unsigned_comparison_p
11404               && HWI_COMPUTABLE_MODE_P (mode)
11405               && trunc_int_for_mode (const_op, mode) == const_op
11406               && have_insn_for (COMPARE, mode))
11407             {
11408               op0 = XEXP (op0, 0);
11409               continue;
11410             }
11411           break;
11412
11413         case SUBREG:
11414           /* Check for the case where we are comparing A - C1 with C2, that is
11415
11416                (subreg:MODE (plus (A) (-C1))) op (C2)
11417
11418              with C1 a constant, and try to lift the SUBREG, i.e. to do the
11419              comparison in the wider mode.  One of the following two conditions
11420              must be true in order for this to be valid:
11421
11422                1. The mode extension results in the same bit pattern being added
11423                   on both sides and the comparison is equality or unsigned.  As
11424                   C2 has been truncated to fit in MODE, the pattern can only be
11425                   all 0s or all 1s.
11426
11427                2. The mode extension results in the sign bit being copied on
11428                   each side.
11429
11430              The difficulty here is that we have predicates for A but not for
11431              (A - C1) so we need to check that C1 is within proper bounds so
11432              as to perturbate A as little as possible.  */
11433
11434           if (mode_width <= HOST_BITS_PER_WIDE_INT
11435               && subreg_lowpart_p (op0)
11436               && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) > mode_width
11437               && GET_CODE (SUBREG_REG (op0)) == PLUS
11438               && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11439             {
11440               machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11441               rtx a = XEXP (SUBREG_REG (op0), 0);
11442               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11443
11444               if ((c1 > 0
11445                    && (unsigned HOST_WIDE_INT) c1
11446                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11447                    && (equality_comparison_p || unsigned_comparison_p)
11448                    /* (A - C1) zero-extends if it is positive and sign-extends
11449                       if it is negative, C2 both zero- and sign-extends.  */
11450                    && ((0 == (nonzero_bits (a, inner_mode)
11451                               & ~GET_MODE_MASK (mode))
11452                         && const_op >= 0)
11453                        /* (A - C1) sign-extends if it is positive and 1-extends
11454                           if it is negative, C2 both sign- and 1-extends.  */
11455                        || (num_sign_bit_copies (a, inner_mode)
11456                            > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11457                                              - mode_width)
11458                            && const_op < 0)))
11459                   || ((unsigned HOST_WIDE_INT) c1
11460                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11461                       /* (A - C1) always sign-extends, like C2.  */
11462                       && num_sign_bit_copies (a, inner_mode)
11463                          > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11464                                            - (mode_width - 1))))
11465                 {
11466                   op0 = SUBREG_REG (op0);
11467                   continue;
11468                 }
11469             }
11470
11471           /* If the inner mode is narrower and we are extracting the low part,
11472              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
11473           if (subreg_lowpart_p (op0)
11474               && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) < mode_width)
11475             /* Fall through */ ;
11476           else
11477             break;
11478
11479           /* ... fall through ...  */
11480
11481         case ZERO_EXTEND:
11482           mode = GET_MODE (XEXP (op0, 0));
11483           if (GET_MODE_CLASS (mode) == MODE_INT
11484               && (unsigned_comparison_p || equality_comparison_p)
11485               && HWI_COMPUTABLE_MODE_P (mode)
11486               && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
11487               && const_op >= 0
11488               && have_insn_for (COMPARE, mode))
11489             {
11490               op0 = XEXP (op0, 0);
11491               continue;
11492             }
11493           break;
11494
11495         case PLUS:
11496           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
11497              this for equality comparisons due to pathological cases involving
11498              overflows.  */
11499           if (equality_comparison_p
11500               && 0 != (tem = simplify_binary_operation (MINUS, mode,
11501                                                         op1, XEXP (op0, 1))))
11502             {
11503               op0 = XEXP (op0, 0);
11504               op1 = tem;
11505               continue;
11506             }
11507
11508           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
11509           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11510               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11511             {
11512               op0 = XEXP (XEXP (op0, 0), 0);
11513               code = (code == LT ? EQ : NE);
11514               continue;
11515             }
11516           break;
11517
11518         case MINUS:
11519           /* We used to optimize signed comparisons against zero, but that
11520              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
11521              arrive here as equality comparisons, or (GEU, LTU) are
11522              optimized away.  No need to special-case them.  */
11523
11524           /* (eq (minus A B) C) -> (eq A (plus B C)) or
11525              (eq B (minus A C)), whichever simplifies.  We can only do
11526              this for equality comparisons due to pathological cases involving
11527              overflows.  */
11528           if (equality_comparison_p
11529               && 0 != (tem = simplify_binary_operation (PLUS, mode,
11530                                                         XEXP (op0, 1), op1)))
11531             {
11532               op0 = XEXP (op0, 0);
11533               op1 = tem;
11534               continue;
11535             }
11536
11537           if (equality_comparison_p
11538               && 0 != (tem = simplify_binary_operation (MINUS, mode,
11539                                                         XEXP (op0, 0), op1)))
11540             {
11541               op0 = XEXP (op0, 1);
11542               op1 = tem;
11543               continue;
11544             }
11545
11546           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11547              of bits in X minus 1, is one iff X > 0.  */
11548           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11549               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11550               && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
11551               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11552             {
11553               op0 = XEXP (op0, 1);
11554               code = (code == GE ? LE : GT);
11555               continue;
11556             }
11557           break;
11558
11559         case XOR:
11560           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
11561              if C is zero or B is a constant.  */
11562           if (equality_comparison_p
11563               && 0 != (tem = simplify_binary_operation (XOR, mode,
11564                                                         XEXP (op0, 1), op1)))
11565             {
11566               op0 = XEXP (op0, 0);
11567               op1 = tem;
11568               continue;
11569             }
11570           break;
11571
11572         case EQ:  case NE:
11573         case UNEQ:  case LTGT:
11574         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
11575         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
11576         case UNORDERED: case ORDERED:
11577           /* We can't do anything if OP0 is a condition code value, rather
11578              than an actual data value.  */
11579           if (const_op != 0
11580               || CC0_P (XEXP (op0, 0))
11581               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11582             break;
11583
11584           /* Get the two operands being compared.  */
11585           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11586             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11587           else
11588             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11589
11590           /* Check for the cases where we simply want the result of the
11591              earlier test or the opposite of that result.  */
11592           if (code == NE || code == EQ
11593               || (val_signbit_known_set_p (GET_MODE (op0), STORE_FLAG_VALUE)
11594                   && (code == LT || code == GE)))
11595             {
11596               enum rtx_code new_code;
11597               if (code == LT || code == NE)
11598                 new_code = GET_CODE (op0);
11599               else
11600                 new_code = reversed_comparison_code (op0, NULL);
11601
11602               if (new_code != UNKNOWN)
11603                 {
11604                   code = new_code;
11605                   op0 = tem;
11606                   op1 = tem1;
11607                   continue;
11608                 }
11609             }
11610           break;
11611
11612         case IOR:
11613           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11614              iff X <= 0.  */
11615           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11616               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11617               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11618             {
11619               op0 = XEXP (op0, 1);
11620               code = (code == GE ? GT : LE);
11621               continue;
11622             }
11623           break;
11624
11625         case AND:
11626           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
11627              will be converted to a ZERO_EXTRACT later.  */
11628           if (const_op == 0 && equality_comparison_p
11629               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11630               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11631             {
11632               op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
11633                                       XEXP (XEXP (op0, 0), 1));
11634               op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11635               continue;
11636             }
11637
11638           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11639              zero and X is a comparison and C1 and C2 describe only bits set
11640              in STORE_FLAG_VALUE, we can compare with X.  */
11641           if (const_op == 0 && equality_comparison_p
11642               && mode_width <= HOST_BITS_PER_WIDE_INT
11643               && CONST_INT_P (XEXP (op0, 1))
11644               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11645               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11646               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11647               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11648             {
11649               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11650                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
11651               if ((~STORE_FLAG_VALUE & mask) == 0
11652                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11653                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11654                           && COMPARISON_P (tem))))
11655                 {
11656                   op0 = XEXP (XEXP (op0, 0), 0);
11657                   continue;
11658                 }
11659             }
11660
11661           /* If we are doing an equality comparison of an AND of a bit equal
11662              to the sign bit, replace this with a LT or GE comparison of
11663              the underlying value.  */
11664           if (equality_comparison_p
11665               && const_op == 0
11666               && CONST_INT_P (XEXP (op0, 1))
11667               && mode_width <= HOST_BITS_PER_WIDE_INT
11668               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11669                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11670             {
11671               op0 = XEXP (op0, 0);
11672               code = (code == EQ ? GE : LT);
11673               continue;
11674             }
11675
11676           /* If this AND operation is really a ZERO_EXTEND from a narrower
11677              mode, the constant fits within that mode, and this is either an
11678              equality or unsigned comparison, try to do this comparison in
11679              the narrower mode.
11680
11681              Note that in:
11682
11683              (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11684              -> (ne:DI (reg:SI 4) (const_int 0))
11685
11686              unless TRULY_NOOP_TRUNCATION allows it or the register is
11687              known to hold a value of the required mode the
11688              transformation is invalid.  */
11689           if ((equality_comparison_p || unsigned_comparison_p)
11690               && CONST_INT_P (XEXP (op0, 1))
11691               && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
11692                                    & GET_MODE_MASK (mode))
11693                                   + 1)) >= 0
11694               && const_op >> i == 0
11695               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11696               && (TRULY_NOOP_TRUNCATION_MODES_P (tmode, GET_MODE (op0))
11697                   || (REG_P (XEXP (op0, 0))
11698                       && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11699             {
11700               op0 = gen_lowpart (tmode, XEXP (op0, 0));
11701               continue;
11702             }
11703
11704           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11705              fits in both M1 and M2 and the SUBREG is either paradoxical
11706              or represents the low part, permute the SUBREG and the AND
11707              and try again.  */
11708           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11709             {
11710               unsigned HOST_WIDE_INT c1;
11711               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11712               /* Require an integral mode, to avoid creating something like
11713                  (AND:SF ...).  */
11714               if (SCALAR_INT_MODE_P (tmode)
11715                   /* It is unsafe to commute the AND into the SUBREG if the
11716                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11717                      not defined.  As originally written the upper bits
11718                      have a defined value due to the AND operation.
11719                      However, if we commute the AND inside the SUBREG then
11720                      they no longer have defined values and the meaning of
11721                      the code has been changed.  */
11722                   && (0
11723 #ifdef WORD_REGISTER_OPERATIONS
11724                       || (mode_width > GET_MODE_PRECISION (tmode)
11725                           && mode_width <= BITS_PER_WORD)
11726 #endif
11727                       || (mode_width <= GET_MODE_PRECISION (tmode)
11728                           && subreg_lowpart_p (XEXP (op0, 0))))
11729                   && CONST_INT_P (XEXP (op0, 1))
11730                   && mode_width <= HOST_BITS_PER_WIDE_INT
11731                   && HWI_COMPUTABLE_MODE_P (tmode)
11732                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11733                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
11734                   && c1 != mask
11735                   && c1 != GET_MODE_MASK (tmode))
11736                 {
11737                   op0 = simplify_gen_binary (AND, tmode,
11738                                              SUBREG_REG (XEXP (op0, 0)),
11739                                              gen_int_mode (c1, tmode));
11740                   op0 = gen_lowpart (mode, op0);
11741                   continue;
11742                 }
11743             }
11744
11745           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
11746           if (const_op == 0 && equality_comparison_p
11747               && XEXP (op0, 1) == const1_rtx
11748               && GET_CODE (XEXP (op0, 0)) == NOT)
11749             {
11750               op0 = simplify_and_const_int (NULL_RTX, mode,
11751                                             XEXP (XEXP (op0, 0), 0), 1);
11752               code = (code == NE ? EQ : NE);
11753               continue;
11754             }
11755
11756           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11757              (eq (and (lshiftrt X) 1) 0).
11758              Also handle the case where (not X) is expressed using xor.  */
11759           if (const_op == 0 && equality_comparison_p
11760               && XEXP (op0, 1) == const1_rtx
11761               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11762             {
11763               rtx shift_op = XEXP (XEXP (op0, 0), 0);
11764               rtx shift_count = XEXP (XEXP (op0, 0), 1);
11765
11766               if (GET_CODE (shift_op) == NOT
11767                   || (GET_CODE (shift_op) == XOR
11768                       && CONST_INT_P (XEXP (shift_op, 1))
11769                       && CONST_INT_P (shift_count)
11770                       && HWI_COMPUTABLE_MODE_P (mode)
11771                       && (UINTVAL (XEXP (shift_op, 1))
11772                           == (unsigned HOST_WIDE_INT) 1
11773                                << INTVAL (shift_count))))
11774                 {
11775                   op0
11776                     = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
11777                   op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11778                   code = (code == NE ? EQ : NE);
11779                   continue;
11780                 }
11781             }
11782           break;
11783
11784         case ASHIFT:
11785           /* If we have (compare (ashift FOO N) (const_int C)) and
11786              the high order N bits of FOO (N+1 if an inequality comparison)
11787              are known to be zero, we can do this by comparing FOO with C
11788              shifted right N bits so long as the low-order N bits of C are
11789              zero.  */
11790           if (CONST_INT_P (XEXP (op0, 1))
11791               && INTVAL (XEXP (op0, 1)) >= 0
11792               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11793                   < HOST_BITS_PER_WIDE_INT)
11794               && (((unsigned HOST_WIDE_INT) const_op
11795                    & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1)))
11796                       - 1)) == 0)
11797               && mode_width <= HOST_BITS_PER_WIDE_INT
11798               && (nonzero_bits (XEXP (op0, 0), mode)
11799                   & ~(mask >> (INTVAL (XEXP (op0, 1))
11800                                + ! equality_comparison_p))) == 0)
11801             {
11802               /* We must perform a logical shift, not an arithmetic one,
11803                  as we want the top N bits of C to be zero.  */
11804               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11805
11806               temp >>= INTVAL (XEXP (op0, 1));
11807               op1 = gen_int_mode (temp, mode);
11808               op0 = XEXP (op0, 0);
11809               continue;
11810             }
11811
11812           /* If we are doing a sign bit comparison, it means we are testing
11813              a particular bit.  Convert it to the appropriate AND.  */
11814           if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11815               && mode_width <= HOST_BITS_PER_WIDE_INT)
11816             {
11817               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11818                                             ((unsigned HOST_WIDE_INT) 1
11819                                              << (mode_width - 1
11820                                                  - INTVAL (XEXP (op0, 1)))));
11821               code = (code == LT ? NE : EQ);
11822               continue;
11823             }
11824
11825           /* If this an equality comparison with zero and we are shifting
11826              the low bit to the sign bit, we can convert this to an AND of the
11827              low-order bit.  */
11828           if (const_op == 0 && equality_comparison_p
11829               && CONST_INT_P (XEXP (op0, 1))
11830               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11831             {
11832               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
11833               continue;
11834             }
11835           break;
11836
11837         case ASHIFTRT:
11838           /* If this is an equality comparison with zero, we can do this
11839              as a logical shift, which might be much simpler.  */
11840           if (equality_comparison_p && const_op == 0
11841               && CONST_INT_P (XEXP (op0, 1)))
11842             {
11843               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11844                                           XEXP (op0, 0),
11845                                           INTVAL (XEXP (op0, 1)));
11846               continue;
11847             }
11848
11849           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11850              do the comparison in a narrower mode.  */
11851           if (! unsigned_comparison_p
11852               && CONST_INT_P (XEXP (op0, 1))
11853               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11854               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11855               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11856                                          MODE_INT, 1)) != BLKmode
11857               && (((unsigned HOST_WIDE_INT) const_op
11858                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11859                   <= GET_MODE_MASK (tmode)))
11860             {
11861               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11862               continue;
11863             }
11864
11865           /* Likewise if OP0 is a PLUS of a sign extension with a
11866              constant, which is usually represented with the PLUS
11867              between the shifts.  */
11868           if (! unsigned_comparison_p
11869               && CONST_INT_P (XEXP (op0, 1))
11870               && GET_CODE (XEXP (op0, 0)) == PLUS
11871               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11872               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11873               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11874               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11875                                          MODE_INT, 1)) != BLKmode
11876               && (((unsigned HOST_WIDE_INT) const_op
11877                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11878                   <= GET_MODE_MASK (tmode)))
11879             {
11880               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11881               rtx add_const = XEXP (XEXP (op0, 0), 1);
11882               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11883                                                    add_const, XEXP (op0, 1));
11884
11885               op0 = simplify_gen_binary (PLUS, tmode,
11886                                          gen_lowpart (tmode, inner),
11887                                          new_const);
11888               continue;
11889             }
11890
11891           /* ... fall through ...  */
11892         case LSHIFTRT:
11893           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11894              the low order N bits of FOO are known to be zero, we can do this
11895              by comparing FOO with C shifted left N bits so long as no
11896              overflow occurs.  Even if the low order N bits of FOO aren't known
11897              to be zero, if the comparison is >= or < we can use the same
11898              optimization and for > or <= by setting all the low
11899              order N bits in the comparison constant.  */
11900           if (CONST_INT_P (XEXP (op0, 1))
11901               && INTVAL (XEXP (op0, 1)) > 0
11902               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11903               && mode_width <= HOST_BITS_PER_WIDE_INT
11904               && (((unsigned HOST_WIDE_INT) const_op
11905                    + (GET_CODE (op0) != LSHIFTRT
11906                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11907                          + 1)
11908                       : 0))
11909                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11910             {
11911               unsigned HOST_WIDE_INT low_bits
11912                 = (nonzero_bits (XEXP (op0, 0), mode)
11913                    & (((unsigned HOST_WIDE_INT) 1
11914                        << INTVAL (XEXP (op0, 1))) - 1));
11915               if (low_bits == 0 || !equality_comparison_p)
11916                 {
11917                   /* If the shift was logical, then we must make the condition
11918                      unsigned.  */
11919                   if (GET_CODE (op0) == LSHIFTRT)
11920                     code = unsigned_condition (code);
11921
11922                   const_op <<= INTVAL (XEXP (op0, 1));
11923                   if (low_bits != 0
11924                       && (code == GT || code == GTU
11925                           || code == LE || code == LEU))
11926                     const_op
11927                       |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
11928                   op1 = GEN_INT (const_op);
11929                   op0 = XEXP (op0, 0);
11930                   continue;
11931                 }
11932             }
11933
11934           /* If we are using this shift to extract just the sign bit, we
11935              can replace this with an LT or GE comparison.  */
11936           if (const_op == 0
11937               && (equality_comparison_p || sign_bit_comparison_p)
11938               && CONST_INT_P (XEXP (op0, 1))
11939               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11940             {
11941               op0 = XEXP (op0, 0);
11942               code = (code == NE || code == GT ? LT : GE);
11943               continue;
11944             }
11945           break;
11946
11947         default:
11948           break;
11949         }
11950
11951       break;
11952     }
11953
11954   /* Now make any compound operations involved in this comparison.  Then,
11955      check for an outmost SUBREG on OP0 that is not doing anything or is
11956      paradoxical.  The latter transformation must only be performed when
11957      it is known that the "extra" bits will be the same in op0 and op1 or
11958      that they don't matter.  There are three cases to consider:
11959
11960      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
11961      care bits and we can assume they have any convenient value.  So
11962      making the transformation is safe.
11963
11964      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11965      In this case the upper bits of op0 are undefined.  We should not make
11966      the simplification in that case as we do not know the contents of
11967      those bits.
11968
11969      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11970      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
11971      also be sure that they are the same as the upper bits of op1.
11972
11973      We can never remove a SUBREG for a non-equality comparison because
11974      the sign bit is in a different place in the underlying object.  */
11975
11976   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
11977   op1 = make_compound_operation (op1, SET);
11978
11979   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
11980       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
11981       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
11982       && (code == NE || code == EQ))
11983     {
11984       if (paradoxical_subreg_p (op0))
11985         {
11986           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
11987              implemented.  */
11988           if (REG_P (SUBREG_REG (op0)))
11989             {
11990               op0 = SUBREG_REG (op0);
11991               op1 = gen_lowpart (GET_MODE (op0), op1);
11992             }
11993         }
11994       else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0)))
11995                 <= HOST_BITS_PER_WIDE_INT)
11996                && (nonzero_bits (SUBREG_REG (op0),
11997                                  GET_MODE (SUBREG_REG (op0)))
11998                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
11999         {
12000           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
12001
12002           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
12003                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
12004             op0 = SUBREG_REG (op0), op1 = tem;
12005         }
12006     }
12007
12008   /* We now do the opposite procedure: Some machines don't have compare
12009      insns in all modes.  If OP0's mode is an integer mode smaller than a
12010      word and we can't do a compare in that mode, see if there is a larger
12011      mode for which we can do the compare.  There are a number of cases in
12012      which we can use the wider mode.  */
12013
12014   mode = GET_MODE (op0);
12015   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
12016       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
12017       && ! have_insn_for (COMPARE, mode))
12018     for (tmode = GET_MODE_WIDER_MODE (mode);
12019          (tmode != VOIDmode && HWI_COMPUTABLE_MODE_P (tmode));
12020          tmode = GET_MODE_WIDER_MODE (tmode))
12021       if (have_insn_for (COMPARE, tmode))
12022         {
12023           int zero_extended;
12024
12025           /* If this is a test for negative, we can make an explicit
12026              test of the sign bit.  Test this first so we can use
12027              a paradoxical subreg to extend OP0.  */
12028
12029           if (op1 == const0_rtx && (code == LT || code == GE)
12030               && HWI_COMPUTABLE_MODE_P (mode))
12031             {
12032               unsigned HOST_WIDE_INT sign
12033                 = (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1);
12034               op0 = simplify_gen_binary (AND, tmode,
12035                                          gen_lowpart (tmode, op0),
12036                                          gen_int_mode (sign, tmode));
12037               code = (code == LT) ? NE : EQ;
12038               break;
12039             }
12040
12041           /* If the only nonzero bits in OP0 and OP1 are those in the
12042              narrower mode and this is an equality or unsigned comparison,
12043              we can use the wider mode.  Similarly for sign-extended
12044              values, in which case it is true for all comparisons.  */
12045           zero_extended = ((code == EQ || code == NE
12046                             || code == GEU || code == GTU
12047                             || code == LEU || code == LTU)
12048                            && (nonzero_bits (op0, tmode)
12049                                & ~GET_MODE_MASK (mode)) == 0
12050                            && ((CONST_INT_P (op1)
12051                                 || (nonzero_bits (op1, tmode)
12052                                     & ~GET_MODE_MASK (mode)) == 0)));
12053
12054           if (zero_extended
12055               || ((num_sign_bit_copies (op0, tmode)
12056                    > (unsigned int) (GET_MODE_PRECISION (tmode)
12057                                      - GET_MODE_PRECISION (mode)))
12058                   && (num_sign_bit_copies (op1, tmode)
12059                       > (unsigned int) (GET_MODE_PRECISION (tmode)
12060                                         - GET_MODE_PRECISION (mode)))))
12061             {
12062               /* If OP0 is an AND and we don't have an AND in MODE either,
12063                  make a new AND in the proper mode.  */
12064               if (GET_CODE (op0) == AND
12065                   && !have_insn_for (AND, mode))
12066                 op0 = simplify_gen_binary (AND, tmode,
12067                                            gen_lowpart (tmode,
12068                                                         XEXP (op0, 0)),
12069                                            gen_lowpart (tmode,
12070                                                         XEXP (op0, 1)));
12071               else
12072                 {
12073                   if (zero_extended)
12074                     {
12075                       op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
12076                       op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
12077                     }
12078                   else
12079                     {
12080                       op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
12081                       op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
12082                     }
12083                   break;
12084                 }
12085             }
12086         }
12087
12088   /* We may have changed the comparison operands.  Re-canonicalize.  */
12089   if (swap_commutative_operands_p (op0, op1))
12090     {
12091       tem = op0, op0 = op1, op1 = tem;
12092       code = swap_condition (code);
12093     }
12094
12095   /* If this machine only supports a subset of valid comparisons, see if we
12096      can convert an unsupported one into a supported one.  */
12097   target_canonicalize_comparison (&code, &op0, &op1, 0);
12098
12099   *pop0 = op0;
12100   *pop1 = op1;
12101
12102   return code;
12103 }
12104 \f
12105 /* Utility function for record_value_for_reg.  Count number of
12106    rtxs in X.  */
12107 static int
12108 count_rtxs (rtx x)
12109 {
12110   enum rtx_code code = GET_CODE (x);
12111   const char *fmt;
12112   int i, j, ret = 1;
12113
12114   if (GET_RTX_CLASS (code) == RTX_BIN_ARITH
12115       || GET_RTX_CLASS (code) == RTX_COMM_ARITH)
12116     {
12117       rtx x0 = XEXP (x, 0);
12118       rtx x1 = XEXP (x, 1);
12119
12120       if (x0 == x1)
12121         return 1 + 2 * count_rtxs (x0);
12122
12123       if ((GET_RTX_CLASS (GET_CODE (x1)) == RTX_BIN_ARITH
12124            || GET_RTX_CLASS (GET_CODE (x1)) == RTX_COMM_ARITH)
12125           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12126         return 2 + 2 * count_rtxs (x0)
12127                + count_rtxs (x == XEXP (x1, 0)
12128                              ? XEXP (x1, 1) : XEXP (x1, 0));
12129
12130       if ((GET_RTX_CLASS (GET_CODE (x0)) == RTX_BIN_ARITH
12131            || GET_RTX_CLASS (GET_CODE (x0)) == RTX_COMM_ARITH)
12132           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12133         return 2 + 2 * count_rtxs (x1)
12134                + count_rtxs (x == XEXP (x0, 0)
12135                              ? XEXP (x0, 1) : XEXP (x0, 0));
12136     }
12137
12138   fmt = GET_RTX_FORMAT (code);
12139   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12140     if (fmt[i] == 'e')
12141       ret += count_rtxs (XEXP (x, i));
12142     else if (fmt[i] == 'E')
12143       for (j = 0; j < XVECLEN (x, i); j++)
12144         ret += count_rtxs (XVECEXP (x, i, j));
12145
12146   return ret;
12147 }
12148 \f
12149 /* Utility function for following routine.  Called when X is part of a value
12150    being stored into last_set_value.  Sets last_set_table_tick
12151    for each register mentioned.  Similar to mention_regs in cse.c  */
12152
12153 static void
12154 update_table_tick (rtx x)
12155 {
12156   enum rtx_code code = GET_CODE (x);
12157   const char *fmt = GET_RTX_FORMAT (code);
12158   int i, j;
12159
12160   if (code == REG)
12161     {
12162       unsigned int regno = REGNO (x);
12163       unsigned int endregno = END_REGNO (x);
12164       unsigned int r;
12165
12166       for (r = regno; r < endregno; r++)
12167         {
12168           reg_stat_type *rsp = &reg_stat[r];
12169           rsp->last_set_table_tick = label_tick;
12170         }
12171
12172       return;
12173     }
12174
12175   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12176     if (fmt[i] == 'e')
12177       {
12178         /* Check for identical subexpressions.  If x contains
12179            identical subexpression we only have to traverse one of
12180            them.  */
12181         if (i == 0 && ARITHMETIC_P (x))
12182           {
12183             /* Note that at this point x1 has already been
12184                processed.  */
12185             rtx x0 = XEXP (x, 0);
12186             rtx x1 = XEXP (x, 1);
12187
12188             /* If x0 and x1 are identical then there is no need to
12189                process x0.  */
12190             if (x0 == x1)
12191               break;
12192
12193             /* If x0 is identical to a subexpression of x1 then while
12194                processing x1, x0 has already been processed.  Thus we
12195                are done with x.  */
12196             if (ARITHMETIC_P (x1)
12197                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12198               break;
12199
12200             /* If x1 is identical to a subexpression of x0 then we
12201                still have to process the rest of x0.  */
12202             if (ARITHMETIC_P (x0)
12203                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12204               {
12205                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12206                 break;
12207               }
12208           }
12209
12210         update_table_tick (XEXP (x, i));
12211       }
12212     else if (fmt[i] == 'E')
12213       for (j = 0; j < XVECLEN (x, i); j++)
12214         update_table_tick (XVECEXP (x, i, j));
12215 }
12216
12217 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
12218    are saying that the register is clobbered and we no longer know its
12219    value.  If INSN is zero, don't update reg_stat[].last_set; this is
12220    only permitted with VALUE also zero and is used to invalidate the
12221    register.  */
12222
12223 static void
12224 record_value_for_reg (rtx reg, rtx_insn *insn, rtx value)
12225 {
12226   unsigned int regno = REGNO (reg);
12227   unsigned int endregno = END_REGNO (reg);
12228   unsigned int i;
12229   reg_stat_type *rsp;
12230
12231   /* If VALUE contains REG and we have a previous value for REG, substitute
12232      the previous value.  */
12233   if (value && insn && reg_overlap_mentioned_p (reg, value))
12234     {
12235       rtx tem;
12236
12237       /* Set things up so get_last_value is allowed to see anything set up to
12238          our insn.  */
12239       subst_low_luid = DF_INSN_LUID (insn);
12240       tem = get_last_value (reg);
12241
12242       /* If TEM is simply a binary operation with two CLOBBERs as operands,
12243          it isn't going to be useful and will take a lot of time to process,
12244          so just use the CLOBBER.  */
12245
12246       if (tem)
12247         {
12248           if (ARITHMETIC_P (tem)
12249               && GET_CODE (XEXP (tem, 0)) == CLOBBER
12250               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12251             tem = XEXP (tem, 0);
12252           else if (count_occurrences (value, reg, 1) >= 2)
12253             {
12254               /* If there are two or more occurrences of REG in VALUE,
12255                  prevent the value from growing too much.  */
12256               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12257                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12258             }
12259
12260           value = replace_rtx (copy_rtx (value), reg, tem);
12261         }
12262     }
12263
12264   /* For each register modified, show we don't know its value, that
12265      we don't know about its bitwise content, that its value has been
12266      updated, and that we don't know the location of the death of the
12267      register.  */
12268   for (i = regno; i < endregno; i++)
12269     {
12270       rsp = &reg_stat[i];
12271
12272       if (insn)
12273         rsp->last_set = insn;
12274
12275       rsp->last_set_value = 0;
12276       rsp->last_set_mode = VOIDmode;
12277       rsp->last_set_nonzero_bits = 0;
12278       rsp->last_set_sign_bit_copies = 0;
12279       rsp->last_death = 0;
12280       rsp->truncated_to_mode = VOIDmode;
12281     }
12282
12283   /* Mark registers that are being referenced in this value.  */
12284   if (value)
12285     update_table_tick (value);
12286
12287   /* Now update the status of each register being set.
12288      If someone is using this register in this block, set this register
12289      to invalid since we will get confused between the two lives in this
12290      basic block.  This makes using this register always invalid.  In cse, we
12291      scan the table to invalidate all entries using this register, but this
12292      is too much work for us.  */
12293
12294   for (i = regno; i < endregno; i++)
12295     {
12296       rsp = &reg_stat[i];
12297       rsp->last_set_label = label_tick;
12298       if (!insn
12299           || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12300         rsp->last_set_invalid = 1;
12301       else
12302         rsp->last_set_invalid = 0;
12303     }
12304
12305   /* The value being assigned might refer to X (like in "x++;").  In that
12306      case, we must replace it with (clobber (const_int 0)) to prevent
12307      infinite loops.  */
12308   rsp = &reg_stat[regno];
12309   if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12310     {
12311       value = copy_rtx (value);
12312       if (!get_last_value_validate (&value, insn, label_tick, 1))
12313         value = 0;
12314     }
12315
12316   /* For the main register being modified, update the value, the mode, the
12317      nonzero bits, and the number of sign bit copies.  */
12318
12319   rsp->last_set_value = value;
12320
12321   if (value)
12322     {
12323       machine_mode mode = GET_MODE (reg);
12324       subst_low_luid = DF_INSN_LUID (insn);
12325       rsp->last_set_mode = mode;
12326       if (GET_MODE_CLASS (mode) == MODE_INT
12327           && HWI_COMPUTABLE_MODE_P (mode))
12328         mode = nonzero_bits_mode;
12329       rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12330       rsp->last_set_sign_bit_copies
12331         = num_sign_bit_copies (value, GET_MODE (reg));
12332     }
12333 }
12334
12335 /* Called via note_stores from record_dead_and_set_regs to handle one
12336    SET or CLOBBER in an insn.  DATA is the instruction in which the
12337    set is occurring.  */
12338
12339 static void
12340 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12341 {
12342   rtx_insn *record_dead_insn = (rtx_insn *) data;
12343
12344   if (GET_CODE (dest) == SUBREG)
12345     dest = SUBREG_REG (dest);
12346
12347   if (!record_dead_insn)
12348     {
12349       if (REG_P (dest))
12350         record_value_for_reg (dest, NULL, NULL_RTX);
12351       return;
12352     }
12353
12354   if (REG_P (dest))
12355     {
12356       /* If we are setting the whole register, we know its value.  Otherwise
12357          show that we don't know the value.  We can handle SUBREG in
12358          some cases.  */
12359       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12360         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12361       else if (GET_CODE (setter) == SET
12362                && GET_CODE (SET_DEST (setter)) == SUBREG
12363                && SUBREG_REG (SET_DEST (setter)) == dest
12364                && GET_MODE_PRECISION (GET_MODE (dest)) <= BITS_PER_WORD
12365                && subreg_lowpart_p (SET_DEST (setter)))
12366         record_value_for_reg (dest, record_dead_insn,
12367                               gen_lowpart (GET_MODE (dest),
12368                                                        SET_SRC (setter)));
12369       else
12370         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12371     }
12372   else if (MEM_P (dest)
12373            /* Ignore pushes, they clobber nothing.  */
12374            && ! push_operand (dest, GET_MODE (dest)))
12375     mem_last_set = DF_INSN_LUID (record_dead_insn);
12376 }
12377
12378 /* Update the records of when each REG was most recently set or killed
12379    for the things done by INSN.  This is the last thing done in processing
12380    INSN in the combiner loop.
12381
12382    We update reg_stat[], in particular fields last_set, last_set_value,
12383    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12384    last_death, and also the similar information mem_last_set (which insn
12385    most recently modified memory) and last_call_luid (which insn was the
12386    most recent subroutine call).  */
12387
12388 static void
12389 record_dead_and_set_regs (rtx_insn *insn)
12390 {
12391   rtx link;
12392   unsigned int i;
12393
12394   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12395     {
12396       if (REG_NOTE_KIND (link) == REG_DEAD
12397           && REG_P (XEXP (link, 0)))
12398         {
12399           unsigned int regno = REGNO (XEXP (link, 0));
12400           unsigned int endregno = END_REGNO (XEXP (link, 0));
12401
12402           for (i = regno; i < endregno; i++)
12403             {
12404               reg_stat_type *rsp;
12405
12406               rsp = &reg_stat[i];
12407               rsp->last_death = insn;
12408             }
12409         }
12410       else if (REG_NOTE_KIND (link) == REG_INC)
12411         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12412     }
12413
12414   if (CALL_P (insn))
12415     {
12416       hard_reg_set_iterator hrsi;
12417       EXECUTE_IF_SET_IN_HARD_REG_SET (regs_invalidated_by_call, 0, i, hrsi)
12418         {
12419           reg_stat_type *rsp;
12420
12421           rsp = &reg_stat[i];
12422           rsp->last_set_invalid = 1;
12423           rsp->last_set = insn;
12424           rsp->last_set_value = 0;
12425           rsp->last_set_mode = VOIDmode;
12426           rsp->last_set_nonzero_bits = 0;
12427           rsp->last_set_sign_bit_copies = 0;
12428           rsp->last_death = 0;
12429           rsp->truncated_to_mode = VOIDmode;
12430         }
12431
12432       last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12433
12434       /* We can't combine into a call pattern.  Remember, though, that
12435          the return value register is set at this LUID.  We could
12436          still replace a register with the return value from the
12437          wrong subroutine call!  */
12438       note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12439     }
12440   else
12441     note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12442 }
12443
12444 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12445    register present in the SUBREG, so for each such SUBREG go back and
12446    adjust nonzero and sign bit information of the registers that are
12447    known to have some zero/sign bits set.
12448
12449    This is needed because when combine blows the SUBREGs away, the
12450    information on zero/sign bits is lost and further combines can be
12451    missed because of that.  */
12452
12453 static void
12454 record_promoted_value (rtx_insn *insn, rtx subreg)
12455 {
12456   struct insn_link *links;
12457   rtx set;
12458   unsigned int regno = REGNO (SUBREG_REG (subreg));
12459   machine_mode mode = GET_MODE (subreg);
12460
12461   if (GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT)
12462     return;
12463
12464   for (links = LOG_LINKS (insn); links;)
12465     {
12466       reg_stat_type *rsp;
12467
12468       insn = links->insn;
12469       set = single_set (insn);
12470
12471       if (! set || !REG_P (SET_DEST (set))
12472           || REGNO (SET_DEST (set)) != regno
12473           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12474         {
12475           links = links->next;
12476           continue;
12477         }
12478
12479       rsp = &reg_stat[regno];
12480       if (rsp->last_set == insn)
12481         {
12482           if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
12483             rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12484         }
12485
12486       if (REG_P (SET_SRC (set)))
12487         {
12488           regno = REGNO (SET_SRC (set));
12489           links = LOG_LINKS (insn);
12490         }
12491       else
12492         break;
12493     }
12494 }
12495
12496 /* Check if X, a register, is known to contain a value already
12497    truncated to MODE.  In this case we can use a subreg to refer to
12498    the truncated value even though in the generic case we would need
12499    an explicit truncation.  */
12500
12501 static bool
12502 reg_truncated_to_mode (machine_mode mode, const_rtx x)
12503 {
12504   reg_stat_type *rsp = &reg_stat[REGNO (x)];
12505   machine_mode truncated = rsp->truncated_to_mode;
12506
12507   if (truncated == 0
12508       || rsp->truncation_label < label_tick_ebb_start)
12509     return false;
12510   if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12511     return true;
12512   if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
12513     return true;
12514   return false;
12515 }
12516
12517 /* If X is a hard reg or a subreg record the mode that the register is
12518    accessed in.  For non-TRULY_NOOP_TRUNCATION targets we might be able
12519    to turn a truncate into a subreg using this information.  Return true
12520    if traversing X is complete.  */
12521
12522 static bool
12523 record_truncated_value (rtx x)
12524 {
12525   machine_mode truncated_mode;
12526   reg_stat_type *rsp;
12527
12528   if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12529     {
12530       machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12531       truncated_mode = GET_MODE (x);
12532
12533       if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12534         return true;
12535
12536       if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
12537         return true;
12538
12539       x = SUBREG_REG (x);
12540     }
12541   /* ??? For hard-regs we now record everything.  We might be able to
12542      optimize this using last_set_mode.  */
12543   else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12544     truncated_mode = GET_MODE (x);
12545   else
12546     return false;
12547
12548   rsp = &reg_stat[REGNO (x)];
12549   if (rsp->truncated_to_mode == 0
12550       || rsp->truncation_label < label_tick_ebb_start
12551       || (GET_MODE_SIZE (truncated_mode)
12552           < GET_MODE_SIZE (rsp->truncated_to_mode)))
12553     {
12554       rsp->truncated_to_mode = truncated_mode;
12555       rsp->truncation_label = label_tick;
12556     }
12557
12558   return true;
12559 }
12560
12561 /* Callback for note_uses.  Find hardregs and subregs of pseudos and
12562    the modes they are used in.  This can help truning TRUNCATEs into
12563    SUBREGs.  */
12564
12565 static void
12566 record_truncated_values (rtx *loc, void *data ATTRIBUTE_UNUSED)
12567 {
12568   subrtx_var_iterator::array_type array;
12569   FOR_EACH_SUBRTX_VAR (iter, array, *loc, NONCONST)
12570     if (record_truncated_value (*iter))
12571       iter.skip_subrtxes ();
12572 }
12573
12574 /* Scan X for promoted SUBREGs.  For each one found,
12575    note what it implies to the registers used in it.  */
12576
12577 static void
12578 check_promoted_subreg (rtx_insn *insn, rtx x)
12579 {
12580   if (GET_CODE (x) == SUBREG
12581       && SUBREG_PROMOTED_VAR_P (x)
12582       && REG_P (SUBREG_REG (x)))
12583     record_promoted_value (insn, x);
12584   else
12585     {
12586       const char *format = GET_RTX_FORMAT (GET_CODE (x));
12587       int i, j;
12588
12589       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12590         switch (format[i])
12591           {
12592           case 'e':
12593             check_promoted_subreg (insn, XEXP (x, i));
12594             break;
12595           case 'V':
12596           case 'E':
12597             if (XVEC (x, i) != 0)
12598               for (j = 0; j < XVECLEN (x, i); j++)
12599                 check_promoted_subreg (insn, XVECEXP (x, i, j));
12600             break;
12601           }
12602     }
12603 }
12604 \f
12605 /* Verify that all the registers and memory references mentioned in *LOC are
12606    still valid.  *LOC was part of a value set in INSN when label_tick was
12607    equal to TICK.  Return 0 if some are not.  If REPLACE is nonzero, replace
12608    the invalid references with (clobber (const_int 0)) and return 1.  This
12609    replacement is useful because we often can get useful information about
12610    the form of a value (e.g., if it was produced by a shift that always
12611    produces -1 or 0) even though we don't know exactly what registers it
12612    was produced from.  */
12613
12614 static int
12615 get_last_value_validate (rtx *loc, rtx_insn *insn, int tick, int replace)
12616 {
12617   rtx x = *loc;
12618   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12619   int len = GET_RTX_LENGTH (GET_CODE (x));
12620   int i, j;
12621
12622   if (REG_P (x))
12623     {
12624       unsigned int regno = REGNO (x);
12625       unsigned int endregno = END_REGNO (x);
12626       unsigned int j;
12627
12628       for (j = regno; j < endregno; j++)
12629         {
12630           reg_stat_type *rsp = &reg_stat[j];
12631           if (rsp->last_set_invalid
12632               /* If this is a pseudo-register that was only set once and not
12633                  live at the beginning of the function, it is always valid.  */
12634               || (! (regno >= FIRST_PSEUDO_REGISTER
12635                      && REG_N_SETS (regno) == 1
12636                      && (!REGNO_REG_SET_P
12637                          (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
12638                           regno)))
12639                   && rsp->last_set_label > tick))
12640           {
12641             if (replace)
12642               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12643             return replace;
12644           }
12645         }
12646
12647       return 1;
12648     }
12649   /* If this is a memory reference, make sure that there were no stores after
12650      it that might have clobbered the value.  We don't have alias info, so we
12651      assume any store invalidates it.  Moreover, we only have local UIDs, so
12652      we also assume that there were stores in the intervening basic blocks.  */
12653   else if (MEM_P (x) && !MEM_READONLY_P (x)
12654            && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12655     {
12656       if (replace)
12657         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12658       return replace;
12659     }
12660
12661   for (i = 0; i < len; i++)
12662     {
12663       if (fmt[i] == 'e')
12664         {
12665           /* Check for identical subexpressions.  If x contains
12666              identical subexpression we only have to traverse one of
12667              them.  */
12668           if (i == 1 && ARITHMETIC_P (x))
12669             {
12670               /* Note that at this point x0 has already been checked
12671                  and found valid.  */
12672               rtx x0 = XEXP (x, 0);
12673               rtx x1 = XEXP (x, 1);
12674
12675               /* If x0 and x1 are identical then x is also valid.  */
12676               if (x0 == x1)
12677                 return 1;
12678
12679               /* If x1 is identical to a subexpression of x0 then
12680                  while checking x0, x1 has already been checked.  Thus
12681                  it is valid and so as x.  */
12682               if (ARITHMETIC_P (x0)
12683                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12684                 return 1;
12685
12686               /* If x0 is identical to a subexpression of x1 then x is
12687                  valid iff the rest of x1 is valid.  */
12688               if (ARITHMETIC_P (x1)
12689                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12690                 return
12691                   get_last_value_validate (&XEXP (x1,
12692                                                   x0 == XEXP (x1, 0) ? 1 : 0),
12693                                            insn, tick, replace);
12694             }
12695
12696           if (get_last_value_validate (&XEXP (x, i), insn, tick,
12697                                        replace) == 0)
12698             return 0;
12699         }
12700       else if (fmt[i] == 'E')
12701         for (j = 0; j < XVECLEN (x, i); j++)
12702           if (get_last_value_validate (&XVECEXP (x, i, j),
12703                                        insn, tick, replace) == 0)
12704             return 0;
12705     }
12706
12707   /* If we haven't found a reason for it to be invalid, it is valid.  */
12708   return 1;
12709 }
12710
12711 /* Get the last value assigned to X, if known.  Some registers
12712    in the value may be replaced with (clobber (const_int 0)) if their value
12713    is known longer known reliably.  */
12714
12715 static rtx
12716 get_last_value (const_rtx x)
12717 {
12718   unsigned int regno;
12719   rtx value;
12720   reg_stat_type *rsp;
12721
12722   /* If this is a non-paradoxical SUBREG, get the value of its operand and
12723      then convert it to the desired mode.  If this is a paradoxical SUBREG,
12724      we cannot predict what values the "extra" bits might have.  */
12725   if (GET_CODE (x) == SUBREG
12726       && subreg_lowpart_p (x)
12727       && !paradoxical_subreg_p (x)
12728       && (value = get_last_value (SUBREG_REG (x))) != 0)
12729     return gen_lowpart (GET_MODE (x), value);
12730
12731   if (!REG_P (x))
12732     return 0;
12733
12734   regno = REGNO (x);
12735   rsp = &reg_stat[regno];
12736   value = rsp->last_set_value;
12737
12738   /* If we don't have a value, or if it isn't for this basic block and
12739      it's either a hard register, set more than once, or it's a live
12740      at the beginning of the function, return 0.
12741
12742      Because if it's not live at the beginning of the function then the reg
12743      is always set before being used (is never used without being set).
12744      And, if it's set only once, and it's always set before use, then all
12745      uses must have the same last value, even if it's not from this basic
12746      block.  */
12747
12748   if (value == 0
12749       || (rsp->last_set_label < label_tick_ebb_start
12750           && (regno < FIRST_PSEUDO_REGISTER
12751               || REG_N_SETS (regno) != 1
12752               || REGNO_REG_SET_P
12753                  (DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), regno))))
12754     return 0;
12755
12756   /* If the value was set in a later insn than the ones we are processing,
12757      we can't use it even if the register was only set once.  */
12758   if (rsp->last_set_label == label_tick
12759       && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12760     return 0;
12761
12762   /* If the value has all its registers valid, return it.  */
12763   if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12764     return value;
12765
12766   /* Otherwise, make a copy and replace any invalid register with
12767      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
12768
12769   value = copy_rtx (value);
12770   if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12771     return value;
12772
12773   return 0;
12774 }
12775 \f
12776 /* Return nonzero if expression X refers to a REG or to memory
12777    that is set in an instruction more recent than FROM_LUID.  */
12778
12779 static int
12780 use_crosses_set_p (const_rtx x, int from_luid)
12781 {
12782   const char *fmt;
12783   int i;
12784   enum rtx_code code = GET_CODE (x);
12785
12786   if (code == REG)
12787     {
12788       unsigned int regno = REGNO (x);
12789       unsigned endreg = END_REGNO (x);
12790
12791 #ifdef PUSH_ROUNDING
12792       /* Don't allow uses of the stack pointer to be moved,
12793          because we don't know whether the move crosses a push insn.  */
12794       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12795         return 1;
12796 #endif
12797       for (; regno < endreg; regno++)
12798         {
12799           reg_stat_type *rsp = &reg_stat[regno];
12800           if (rsp->last_set
12801               && rsp->last_set_label == label_tick
12802               && DF_INSN_LUID (rsp->last_set) > from_luid)
12803             return 1;
12804         }
12805       return 0;
12806     }
12807
12808   if (code == MEM && mem_last_set > from_luid)
12809     return 1;
12810
12811   fmt = GET_RTX_FORMAT (code);
12812
12813   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12814     {
12815       if (fmt[i] == 'E')
12816         {
12817           int j;
12818           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12819             if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12820               return 1;
12821         }
12822       else if (fmt[i] == 'e'
12823                && use_crosses_set_p (XEXP (x, i), from_luid))
12824         return 1;
12825     }
12826   return 0;
12827 }
12828 \f
12829 /* Define three variables used for communication between the following
12830    routines.  */
12831
12832 static unsigned int reg_dead_regno, reg_dead_endregno;
12833 static int reg_dead_flag;
12834
12835 /* Function called via note_stores from reg_dead_at_p.
12836
12837    If DEST is within [reg_dead_regno, reg_dead_endregno), set
12838    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
12839
12840 static void
12841 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12842 {
12843   unsigned int regno, endregno;
12844
12845   if (!REG_P (dest))
12846     return;
12847
12848   regno = REGNO (dest);
12849   endregno = END_REGNO (dest);
12850   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12851     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12852 }
12853
12854 /* Return nonzero if REG is known to be dead at INSN.
12855
12856    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
12857    referencing REG, it is dead.  If we hit a SET referencing REG, it is
12858    live.  Otherwise, see if it is live or dead at the start of the basic
12859    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
12860    must be assumed to be always live.  */
12861
12862 static int
12863 reg_dead_at_p (rtx reg, rtx_insn *insn)
12864 {
12865   basic_block block;
12866   unsigned int i;
12867
12868   /* Set variables for reg_dead_at_p_1.  */
12869   reg_dead_regno = REGNO (reg);
12870   reg_dead_endregno = END_REGNO (reg);
12871
12872   reg_dead_flag = 0;
12873
12874   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
12875      we allow the machine description to decide whether use-and-clobber
12876      patterns are OK.  */
12877   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12878     {
12879       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12880         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12881           return 0;
12882     }
12883
12884   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12885      beginning of basic block.  */
12886   block = BLOCK_FOR_INSN (insn);
12887   for (;;)
12888     {
12889       if (INSN_P (insn))
12890         {
12891           note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12892           if (reg_dead_flag)
12893             return reg_dead_flag == 1 ? 1 : 0;
12894
12895           if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12896             return 1;
12897         }
12898
12899       if (insn == BB_HEAD (block))
12900         break;
12901
12902       insn = PREV_INSN (insn);
12903     }
12904
12905   /* Look at live-in sets for the basic block that we were in.  */
12906   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12907     if (REGNO_REG_SET_P (df_get_live_in (block), i))
12908       return 0;
12909
12910   return 1;
12911 }
12912 \f
12913 /* Note hard registers in X that are used.  */
12914
12915 static void
12916 mark_used_regs_combine (rtx x)
12917 {
12918   RTX_CODE code = GET_CODE (x);
12919   unsigned int regno;
12920   int i;
12921
12922   switch (code)
12923     {
12924     case LABEL_REF:
12925     case SYMBOL_REF:
12926     case CONST:
12927     CASE_CONST_ANY:
12928     case PC:
12929     case ADDR_VEC:
12930     case ADDR_DIFF_VEC:
12931     case ASM_INPUT:
12932 #ifdef HAVE_cc0
12933     /* CC0 must die in the insn after it is set, so we don't need to take
12934        special note of it here.  */
12935     case CC0:
12936 #endif
12937       return;
12938
12939     case CLOBBER:
12940       /* If we are clobbering a MEM, mark any hard registers inside the
12941          address as used.  */
12942       if (MEM_P (XEXP (x, 0)))
12943         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12944       return;
12945
12946     case REG:
12947       regno = REGNO (x);
12948       /* A hard reg in a wide mode may really be multiple registers.
12949          If so, mark all of them just like the first.  */
12950       if (regno < FIRST_PSEUDO_REGISTER)
12951         {
12952           /* None of this applies to the stack, frame or arg pointers.  */
12953           if (regno == STACK_POINTER_REGNUM
12954 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12955               || regno == HARD_FRAME_POINTER_REGNUM
12956 #endif
12957 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12958               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12959 #endif
12960               || regno == FRAME_POINTER_REGNUM)
12961             return;
12962
12963           add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12964         }
12965       return;
12966
12967     case SET:
12968       {
12969         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12970            the address.  */
12971         rtx testreg = SET_DEST (x);
12972
12973         while (GET_CODE (testreg) == SUBREG
12974                || GET_CODE (testreg) == ZERO_EXTRACT
12975                || GET_CODE (testreg) == STRICT_LOW_PART)
12976           testreg = XEXP (testreg, 0);
12977
12978         if (MEM_P (testreg))
12979           mark_used_regs_combine (XEXP (testreg, 0));
12980
12981         mark_used_regs_combine (SET_SRC (x));
12982       }
12983       return;
12984
12985     default:
12986       break;
12987     }
12988
12989   /* Recursively scan the operands of this expression.  */
12990
12991   {
12992     const char *fmt = GET_RTX_FORMAT (code);
12993
12994     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12995       {
12996         if (fmt[i] == 'e')
12997           mark_used_regs_combine (XEXP (x, i));
12998         else if (fmt[i] == 'E')
12999           {
13000             int j;
13001
13002             for (j = 0; j < XVECLEN (x, i); j++)
13003               mark_used_regs_combine (XVECEXP (x, i, j));
13004           }
13005       }
13006   }
13007 }
13008 \f
13009 /* Remove register number REGNO from the dead registers list of INSN.
13010
13011    Return the note used to record the death, if there was one.  */
13012
13013 rtx
13014 remove_death (unsigned int regno, rtx_insn *insn)
13015 {
13016   rtx note = find_regno_note (insn, REG_DEAD, regno);
13017
13018   if (note)
13019     remove_note (insn, note);
13020
13021   return note;
13022 }
13023
13024 /* For each register (hardware or pseudo) used within expression X, if its
13025    death is in an instruction with luid between FROM_LUID (inclusive) and
13026    TO_INSN (exclusive), put a REG_DEAD note for that register in the
13027    list headed by PNOTES.
13028
13029    That said, don't move registers killed by maybe_kill_insn.
13030
13031    This is done when X is being merged by combination into TO_INSN.  These
13032    notes will then be distributed as needed.  */
13033
13034 static void
13035 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx_insn *to_insn,
13036              rtx *pnotes)
13037 {
13038   const char *fmt;
13039   int len, i;
13040   enum rtx_code code = GET_CODE (x);
13041
13042   if (code == REG)
13043     {
13044       unsigned int regno = REGNO (x);
13045       rtx_insn *where_dead = reg_stat[regno].last_death;
13046
13047       /* Don't move the register if it gets killed in between from and to.  */
13048       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
13049           && ! reg_referenced_p (x, maybe_kill_insn))
13050         return;
13051
13052       if (where_dead
13053           && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
13054           && DF_INSN_LUID (where_dead) >= from_luid
13055           && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
13056         {
13057           rtx note = remove_death (regno, where_dead);
13058
13059           /* It is possible for the call above to return 0.  This can occur
13060              when last_death points to I2 or I1 that we combined with.
13061              In that case make a new note.
13062
13063              We must also check for the case where X is a hard register
13064              and NOTE is a death note for a range of hard registers
13065              including X.  In that case, we must put REG_DEAD notes for
13066              the remaining registers in place of NOTE.  */
13067
13068           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
13069               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13070                   > GET_MODE_SIZE (GET_MODE (x))))
13071             {
13072               unsigned int deadregno = REGNO (XEXP (note, 0));
13073               unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
13074               unsigned int ourend = END_HARD_REGNO (x);
13075               unsigned int i;
13076
13077               for (i = deadregno; i < deadend; i++)
13078                 if (i < regno || i >= ourend)
13079                   add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
13080             }
13081
13082           /* If we didn't find any note, or if we found a REG_DEAD note that
13083              covers only part of the given reg, and we have a multi-reg hard
13084              register, then to be safe we must check for REG_DEAD notes
13085              for each register other than the first.  They could have
13086              their own REG_DEAD notes lying around.  */
13087           else if ((note == 0
13088                     || (note != 0
13089                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13090                             < GET_MODE_SIZE (GET_MODE (x)))))
13091                    && regno < FIRST_PSEUDO_REGISTER
13092                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
13093             {
13094               unsigned int ourend = END_HARD_REGNO (x);
13095               unsigned int i, offset;
13096               rtx oldnotes = 0;
13097
13098               if (note)
13099                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
13100               else
13101                 offset = 1;
13102
13103               for (i = regno + offset; i < ourend; i++)
13104                 move_deaths (regno_reg_rtx[i],
13105                              maybe_kill_insn, from_luid, to_insn, &oldnotes);
13106             }
13107
13108           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
13109             {
13110               XEXP (note, 1) = *pnotes;
13111               *pnotes = note;
13112             }
13113           else
13114             *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
13115         }
13116
13117       return;
13118     }
13119
13120   else if (GET_CODE (x) == SET)
13121     {
13122       rtx dest = SET_DEST (x);
13123
13124       move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
13125
13126       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13127          that accesses one word of a multi-word item, some
13128          piece of everything register in the expression is used by
13129          this insn, so remove any old death.  */
13130       /* ??? So why do we test for equality of the sizes?  */
13131
13132       if (GET_CODE (dest) == ZERO_EXTRACT
13133           || GET_CODE (dest) == STRICT_LOW_PART
13134           || (GET_CODE (dest) == SUBREG
13135               && (((GET_MODE_SIZE (GET_MODE (dest))
13136                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13137                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13138                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13139         {
13140           move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13141           return;
13142         }
13143
13144       /* If this is some other SUBREG, we know it replaces the entire
13145          value, so use that as the destination.  */
13146       if (GET_CODE (dest) == SUBREG)
13147         dest = SUBREG_REG (dest);
13148
13149       /* If this is a MEM, adjust deaths of anything used in the address.
13150          For a REG (the only other possibility), the entire value is
13151          being replaced so the old value is not used in this insn.  */
13152
13153       if (MEM_P (dest))
13154         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13155                      to_insn, pnotes);
13156       return;
13157     }
13158
13159   else if (GET_CODE (x) == CLOBBER)
13160     return;
13161
13162   len = GET_RTX_LENGTH (code);
13163   fmt = GET_RTX_FORMAT (code);
13164
13165   for (i = 0; i < len; i++)
13166     {
13167       if (fmt[i] == 'E')
13168         {
13169           int j;
13170           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13171             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13172                          to_insn, pnotes);
13173         }
13174       else if (fmt[i] == 'e')
13175         move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13176     }
13177 }
13178 \f
13179 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13180    pattern of an insn.  X must be a REG.  */
13181
13182 static int
13183 reg_bitfield_target_p (rtx x, rtx body)
13184 {
13185   int i;
13186
13187   if (GET_CODE (body) == SET)
13188     {
13189       rtx dest = SET_DEST (body);
13190       rtx target;
13191       unsigned int regno, tregno, endregno, endtregno;
13192
13193       if (GET_CODE (dest) == ZERO_EXTRACT)
13194         target = XEXP (dest, 0);
13195       else if (GET_CODE (dest) == STRICT_LOW_PART)
13196         target = SUBREG_REG (XEXP (dest, 0));
13197       else
13198         return 0;
13199
13200       if (GET_CODE (target) == SUBREG)
13201         target = SUBREG_REG (target);
13202
13203       if (!REG_P (target))
13204         return 0;
13205
13206       tregno = REGNO (target), regno = REGNO (x);
13207       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13208         return target == x;
13209
13210       endtregno = end_hard_regno (GET_MODE (target), tregno);
13211       endregno = end_hard_regno (GET_MODE (x), regno);
13212
13213       return endregno > tregno && regno < endtregno;
13214     }
13215
13216   else if (GET_CODE (body) == PARALLEL)
13217     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13218       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13219         return 1;
13220
13221   return 0;
13222 }
13223 \f
13224 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13225    as appropriate.  I3 and I2 are the insns resulting from the combination
13226    insns including FROM (I2 may be zero).
13227
13228    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13229    not need REG_DEAD notes because they are being substituted for.  This
13230    saves searching in the most common cases.
13231
13232    Each note in the list is either ignored or placed on some insns, depending
13233    on the type of note.  */
13234
13235 static void
13236 distribute_notes (rtx notes, rtx_insn *from_insn, rtx_insn *i3, rtx_insn *i2,
13237                   rtx elim_i2, rtx elim_i1, rtx elim_i0)
13238 {
13239   rtx note, next_note;
13240   rtx tem_note;
13241   rtx_insn *tem_insn;
13242
13243   for (note = notes; note; note = next_note)
13244     {
13245       rtx_insn *place = 0, *place2 = 0;
13246
13247       next_note = XEXP (note, 1);
13248       switch (REG_NOTE_KIND (note))
13249         {
13250         case REG_BR_PROB:
13251         case REG_BR_PRED:
13252           /* Doesn't matter much where we put this, as long as it's somewhere.
13253              It is preferable to keep these notes on branches, which is most
13254              likely to be i3.  */
13255           place = i3;
13256           break;
13257
13258         case REG_NON_LOCAL_GOTO:
13259           if (JUMP_P (i3))
13260             place = i3;
13261           else
13262             {
13263               gcc_assert (i2 && JUMP_P (i2));
13264               place = i2;
13265             }
13266           break;
13267
13268         case REG_EH_REGION:
13269           /* These notes must remain with the call or trapping instruction.  */
13270           if (CALL_P (i3))
13271             place = i3;
13272           else if (i2 && CALL_P (i2))
13273             place = i2;
13274           else
13275             {
13276               gcc_assert (cfun->can_throw_non_call_exceptions);
13277               if (may_trap_p (i3))
13278                 place = i3;
13279               else if (i2 && may_trap_p (i2))
13280                 place = i2;
13281               /* ??? Otherwise assume we've combined things such that we
13282                  can now prove that the instructions can't trap.  Drop the
13283                  note in this case.  */
13284             }
13285           break;
13286
13287         case REG_ARGS_SIZE:
13288           /* ??? How to distribute between i3-i1.  Assume i3 contains the
13289              entire adjustment.  Assert i3 contains at least some adjust.  */
13290           if (!noop_move_p (i3))
13291             {
13292               int old_size, args_size = INTVAL (XEXP (note, 0));
13293               /* fixup_args_size_notes looks at REG_NORETURN note,
13294                  so ensure the note is placed there first.  */
13295               if (CALL_P (i3))
13296                 {
13297                   rtx *np;
13298                   for (np = &next_note; *np; np = &XEXP (*np, 1))
13299                     if (REG_NOTE_KIND (*np) == REG_NORETURN)
13300                       {
13301                         rtx n = *np;
13302                         *np = XEXP (n, 1);
13303                         XEXP (n, 1) = REG_NOTES (i3);
13304                         REG_NOTES (i3) = n;
13305                         break;
13306                       }
13307                 }
13308               old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size);
13309               /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13310                  REG_ARGS_SIZE note to all noreturn calls, allow that here.  */
13311               gcc_assert (old_size != args_size
13312                           || (CALL_P (i3)
13313                               && !ACCUMULATE_OUTGOING_ARGS
13314                               && find_reg_note (i3, REG_NORETURN, NULL_RTX)));
13315             }
13316           break;
13317
13318         case REG_NORETURN:
13319         case REG_SETJMP:
13320         case REG_TM:
13321         case REG_CALL_DECL:
13322           /* These notes must remain with the call.  It should not be
13323              possible for both I2 and I3 to be a call.  */
13324           if (CALL_P (i3))
13325             place = i3;
13326           else
13327             {
13328               gcc_assert (i2 && CALL_P (i2));
13329               place = i2;
13330             }
13331           break;
13332
13333         case REG_UNUSED:
13334           /* Any clobbers for i3 may still exist, and so we must process
13335              REG_UNUSED notes from that insn.
13336
13337              Any clobbers from i2 or i1 can only exist if they were added by
13338              recog_for_combine.  In that case, recog_for_combine created the
13339              necessary REG_UNUSED notes.  Trying to keep any original
13340              REG_UNUSED notes from these insns can cause incorrect output
13341              if it is for the same register as the original i3 dest.
13342              In that case, we will notice that the register is set in i3,
13343              and then add a REG_UNUSED note for the destination of i3, which
13344              is wrong.  However, it is possible to have REG_UNUSED notes from
13345              i2 or i1 for register which were both used and clobbered, so
13346              we keep notes from i2 or i1 if they will turn into REG_DEAD
13347              notes.  */
13348
13349           /* If this register is set or clobbered in I3, put the note there
13350              unless there is one already.  */
13351           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13352             {
13353               if (from_insn != i3)
13354                 break;
13355
13356               if (! (REG_P (XEXP (note, 0))
13357                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13358                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13359                 place = i3;
13360             }
13361           /* Otherwise, if this register is used by I3, then this register
13362              now dies here, so we must put a REG_DEAD note here unless there
13363              is one already.  */
13364           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13365                    && ! (REG_P (XEXP (note, 0))
13366                          ? find_regno_note (i3, REG_DEAD,
13367                                             REGNO (XEXP (note, 0)))
13368                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13369             {
13370               PUT_REG_NOTE_KIND (note, REG_DEAD);
13371               place = i3;
13372             }
13373           break;
13374
13375         case REG_EQUAL:
13376         case REG_EQUIV:
13377         case REG_NOALIAS:
13378           /* These notes say something about results of an insn.  We can
13379              only support them if they used to be on I3 in which case they
13380              remain on I3.  Otherwise they are ignored.
13381
13382              If the note refers to an expression that is not a constant, we
13383              must also ignore the note since we cannot tell whether the
13384              equivalence is still true.  It might be possible to do
13385              slightly better than this (we only have a problem if I2DEST
13386              or I1DEST is present in the expression), but it doesn't
13387              seem worth the trouble.  */
13388
13389           if (from_insn == i3
13390               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13391             place = i3;
13392           break;
13393
13394         case REG_INC:
13395           /* These notes say something about how a register is used.  They must
13396              be present on any use of the register in I2 or I3.  */
13397           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13398             place = i3;
13399
13400           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13401             {
13402               if (place)
13403                 place2 = i2;
13404               else
13405                 place = i2;
13406             }
13407           break;
13408
13409         case REG_LABEL_TARGET:
13410         case REG_LABEL_OPERAND:
13411           /* This can show up in several ways -- either directly in the
13412              pattern, or hidden off in the constant pool with (or without?)
13413              a REG_EQUAL note.  */
13414           /* ??? Ignore the without-reg_equal-note problem for now.  */
13415           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13416               || ((tem_note = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13417                   && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
13418                   && LABEL_REF_LABEL (XEXP (tem_note, 0)) == XEXP (note, 0)))
13419             place = i3;
13420
13421           if (i2
13422               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13423                   || ((tem_note = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13424                       && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
13425                       && LABEL_REF_LABEL (XEXP (tem_note, 0)) == XEXP (note, 0))))
13426             {
13427               if (place)
13428                 place2 = i2;
13429               else
13430                 place = i2;
13431             }
13432
13433           /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13434              as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13435              there.  */
13436           if (place && JUMP_P (place)
13437               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13438               && (JUMP_LABEL (place) == NULL
13439                   || JUMP_LABEL (place) == XEXP (note, 0)))
13440             {
13441               rtx label = JUMP_LABEL (place);
13442
13443               if (!label)
13444                 JUMP_LABEL (place) = XEXP (note, 0);
13445               else if (LABEL_P (label))
13446                 LABEL_NUSES (label)--;
13447             }
13448
13449           if (place2 && JUMP_P (place2)
13450               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13451               && (JUMP_LABEL (place2) == NULL
13452                   || JUMP_LABEL (place2) == XEXP (note, 0)))
13453             {
13454               rtx label = JUMP_LABEL (place2);
13455
13456               if (!label)
13457                 JUMP_LABEL (place2) = XEXP (note, 0);
13458               else if (LABEL_P (label))
13459                 LABEL_NUSES (label)--;
13460               place2 = 0;
13461             }
13462           break;
13463
13464         case REG_NONNEG:
13465           /* This note says something about the value of a register prior
13466              to the execution of an insn.  It is too much trouble to see
13467              if the note is still correct in all situations.  It is better
13468              to simply delete it.  */
13469           break;
13470
13471         case REG_DEAD:
13472           /* If we replaced the right hand side of FROM_INSN with a
13473              REG_EQUAL note, the original use of the dying register
13474              will not have been combined into I3 and I2.  In such cases,
13475              FROM_INSN is guaranteed to be the first of the combined
13476              instructions, so we simply need to search back before
13477              FROM_INSN for the previous use or set of this register,
13478              then alter the notes there appropriately.
13479
13480              If the register is used as an input in I3, it dies there.
13481              Similarly for I2, if it is nonzero and adjacent to I3.
13482
13483              If the register is not used as an input in either I3 or I2
13484              and it is not one of the registers we were supposed to eliminate,
13485              there are two possibilities.  We might have a non-adjacent I2
13486              or we might have somehow eliminated an additional register
13487              from a computation.  For example, we might have had A & B where
13488              we discover that B will always be zero.  In this case we will
13489              eliminate the reference to A.
13490
13491              In both cases, we must search to see if we can find a previous
13492              use of A and put the death note there.  */
13493
13494           if (from_insn
13495               && from_insn == i2mod
13496               && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13497             tem_insn = from_insn;
13498           else
13499             {
13500               if (from_insn
13501                   && CALL_P (from_insn)
13502                   && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13503                 place = from_insn;
13504               else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13505                 place = i3;
13506               else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13507                        && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13508                 place = i2;
13509               else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13510                         && !(i2mod
13511                              && reg_overlap_mentioned_p (XEXP (note, 0),
13512                                                          i2mod_old_rhs)))
13513                        || rtx_equal_p (XEXP (note, 0), elim_i1)
13514                        || rtx_equal_p (XEXP (note, 0), elim_i0))
13515                 break;
13516               tem_insn = i3;
13517             }
13518
13519           if (place == 0)
13520             {
13521               basic_block bb = this_basic_block;
13522
13523               for (tem_insn = PREV_INSN (tem_insn); place == 0; tem_insn = PREV_INSN (tem_insn))
13524                 {
13525                   if (!NONDEBUG_INSN_P (tem_insn))
13526                     {
13527                       if (tem_insn == BB_HEAD (bb))
13528                         break;
13529                       continue;
13530                     }
13531
13532                   /* If the register is being set at TEM_INSN, see if that is all
13533                      TEM_INSN is doing.  If so, delete TEM_INSN.  Otherwise, make this
13534                      into a REG_UNUSED note instead. Don't delete sets to
13535                      global register vars.  */
13536                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13537                        || !global_regs[REGNO (XEXP (note, 0))])
13538                       && reg_set_p (XEXP (note, 0), PATTERN (tem_insn)))
13539                     {
13540                       rtx set = single_set (tem_insn);
13541                       rtx inner_dest = 0;
13542 #ifdef HAVE_cc0
13543                       rtx_insn *cc0_setter = NULL;
13544 #endif
13545
13546                       if (set != 0)
13547                         for (inner_dest = SET_DEST (set);
13548                              (GET_CODE (inner_dest) == STRICT_LOW_PART
13549                               || GET_CODE (inner_dest) == SUBREG
13550                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
13551                              inner_dest = XEXP (inner_dest, 0))
13552                           ;
13553
13554                       /* Verify that it was the set, and not a clobber that
13555                          modified the register.
13556
13557                          CC0 targets must be careful to maintain setter/user
13558                          pairs.  If we cannot delete the setter due to side
13559                          effects, mark the user with an UNUSED note instead
13560                          of deleting it.  */
13561
13562                       if (set != 0 && ! side_effects_p (SET_SRC (set))
13563                           && rtx_equal_p (XEXP (note, 0), inner_dest)
13564 #ifdef HAVE_cc0
13565                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13566                               || ((cc0_setter = prev_cc0_setter (tem_insn)) != NULL
13567                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13568 #endif
13569                           )
13570                         {
13571                           /* Move the notes and links of TEM_INSN elsewhere.
13572                              This might delete other dead insns recursively.
13573                              First set the pattern to something that won't use
13574                              any register.  */
13575                           rtx old_notes = REG_NOTES (tem_insn);
13576
13577                           PATTERN (tem_insn) = pc_rtx;
13578                           REG_NOTES (tem_insn) = NULL;
13579
13580                           distribute_notes (old_notes, tem_insn, tem_insn, NULL,
13581                                             NULL_RTX, NULL_RTX, NULL_RTX);
13582                           distribute_links (LOG_LINKS (tem_insn));
13583
13584                           SET_INSN_DELETED (tem_insn);
13585                           if (tem_insn == i2)
13586                             i2 = NULL;
13587
13588 #ifdef HAVE_cc0
13589                           /* Delete the setter too.  */
13590                           if (cc0_setter)
13591                             {
13592                               PATTERN (cc0_setter) = pc_rtx;
13593                               old_notes = REG_NOTES (cc0_setter);
13594                               REG_NOTES (cc0_setter) = NULL;
13595
13596                               distribute_notes (old_notes, cc0_setter,
13597                                                 cc0_setter, NULL,
13598                                                 NULL_RTX, NULL_RTX, NULL_RTX);
13599                               distribute_links (LOG_LINKS (cc0_setter));
13600
13601                               SET_INSN_DELETED (cc0_setter);
13602                               if (cc0_setter == i2)
13603                                 i2 = NULL;
13604                             }
13605 #endif
13606                         }
13607                       else
13608                         {
13609                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
13610
13611                           /*  If there isn't already a REG_UNUSED note, put one
13612                               here.  Do not place a REG_DEAD note, even if
13613                               the register is also used here; that would not
13614                               match the algorithm used in lifetime analysis
13615                               and can cause the consistency check in the
13616                               scheduler to fail.  */
13617                           if (! find_regno_note (tem_insn, REG_UNUSED,
13618                                                  REGNO (XEXP (note, 0))))
13619                             place = tem_insn;
13620                           break;
13621                         }
13622                     }
13623                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem_insn))
13624                            || (CALL_P (tem_insn)
13625                                && find_reg_fusage (tem_insn, USE, XEXP (note, 0))))
13626                     {
13627                       place = tem_insn;
13628
13629                       /* If we are doing a 3->2 combination, and we have a
13630                          register which formerly died in i3 and was not used
13631                          by i2, which now no longer dies in i3 and is used in
13632                          i2 but does not die in i2, and place is between i2
13633                          and i3, then we may need to move a link from place to
13634                          i2.  */
13635                       if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13636                           && from_insn
13637                           && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13638                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13639                         {
13640                           struct insn_link *links = LOG_LINKS (place);
13641                           LOG_LINKS (place) = NULL;
13642                           distribute_links (links);
13643                         }
13644                       break;
13645                     }
13646
13647                   if (tem_insn == BB_HEAD (bb))
13648                     break;
13649                 }
13650
13651             }
13652
13653           /* If the register is set or already dead at PLACE, we needn't do
13654              anything with this note if it is still a REG_DEAD note.
13655              We check here if it is set at all, not if is it totally replaced,
13656              which is what `dead_or_set_p' checks, so also check for it being
13657              set partially.  */
13658
13659           if (place && REG_NOTE_KIND (note) == REG_DEAD)
13660             {
13661               unsigned int regno = REGNO (XEXP (note, 0));
13662               reg_stat_type *rsp = &reg_stat[regno];
13663
13664               if (dead_or_set_p (place, XEXP (note, 0))
13665                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13666                 {
13667                   /* Unless the register previously died in PLACE, clear
13668                      last_death.  [I no longer understand why this is
13669                      being done.] */
13670                   if (rsp->last_death != place)
13671                     rsp->last_death = 0;
13672                   place = 0;
13673                 }
13674               else
13675                 rsp->last_death = place;
13676
13677               /* If this is a death note for a hard reg that is occupying
13678                  multiple registers, ensure that we are still using all
13679                  parts of the object.  If we find a piece of the object
13680                  that is unused, we must arrange for an appropriate REG_DEAD
13681                  note to be added for it.  However, we can't just emit a USE
13682                  and tag the note to it, since the register might actually
13683                  be dead; so we recourse, and the recursive call then finds
13684                  the previous insn that used this register.  */
13685
13686               if (place && regno < FIRST_PSEUDO_REGISTER
13687                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13688                 {
13689                   unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13690                   bool all_used = true;
13691                   unsigned int i;
13692
13693                   for (i = regno; i < endregno; i++)
13694                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13695                          && ! find_regno_fusage (place, USE, i))
13696                         || dead_or_set_regno_p (place, i))
13697                       {
13698                         all_used = false;
13699                         break;
13700                       }
13701
13702                   if (! all_used)
13703                     {
13704                       /* Put only REG_DEAD notes for pieces that are
13705                          not already dead or set.  */
13706
13707                       for (i = regno; i < endregno;
13708                            i += hard_regno_nregs[i][reg_raw_mode[i]])
13709                         {
13710                           rtx piece = regno_reg_rtx[i];
13711                           basic_block bb = this_basic_block;
13712
13713                           if (! dead_or_set_p (place, piece)
13714                               && ! reg_bitfield_target_p (piece,
13715                                                           PATTERN (place)))
13716                             {
13717                               rtx new_note = alloc_reg_note (REG_DEAD, piece,
13718                                                              NULL_RTX);
13719
13720                               distribute_notes (new_note, place, place,
13721                                                 NULL, NULL_RTX, NULL_RTX,
13722                                                 NULL_RTX);
13723                             }
13724                           else if (! refers_to_regno_p (i, i + 1,
13725                                                         PATTERN (place), 0)
13726                                    && ! find_regno_fusage (place, USE, i))
13727                             for (tem_insn = PREV_INSN (place); ;
13728                                  tem_insn = PREV_INSN (tem_insn))
13729                               {
13730                                 if (!NONDEBUG_INSN_P (tem_insn))
13731                                   {
13732                                     if (tem_insn == BB_HEAD (bb))
13733                                       break;
13734                                     continue;
13735                                   }
13736                                 if (dead_or_set_p (tem_insn, piece)
13737                                     || reg_bitfield_target_p (piece,
13738                                                               PATTERN (tem_insn)))
13739                                   {
13740                                     add_reg_note (tem_insn, REG_UNUSED, piece);
13741                                     break;
13742                                   }
13743                               }
13744                         }
13745
13746                       place = 0;
13747                     }
13748                 }
13749             }
13750           break;
13751
13752         default:
13753           /* Any other notes should not be present at this point in the
13754              compilation.  */
13755           gcc_unreachable ();
13756         }
13757
13758       if (place)
13759         {
13760           XEXP (note, 1) = REG_NOTES (place);
13761           REG_NOTES (place) = note;
13762         }
13763
13764       if (place2)
13765         add_shallow_copy_of_reg_note (place2, note);
13766     }
13767 }
13768 \f
13769 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13770    I3, I2, and I1 to new locations.  This is also called to add a link
13771    pointing at I3 when I3's destination is changed.  */
13772
13773 static void
13774 distribute_links (struct insn_link *links)
13775 {
13776   struct insn_link *link, *next_link;
13777
13778   for (link = links; link; link = next_link)
13779     {
13780       rtx_insn *place = 0;
13781       rtx_insn *insn;
13782       rtx set, reg;
13783
13784       next_link = link->next;
13785
13786       /* If the insn that this link points to is a NOTE or isn't a single
13787          set, ignore it.  In the latter case, it isn't clear what we
13788          can do other than ignore the link, since we can't tell which
13789          register it was for.  Such links wouldn't be used by combine
13790          anyway.
13791
13792          It is not possible for the destination of the target of the link to
13793          have been changed by combine.  The only potential of this is if we
13794          replace I3, I2, and I1 by I3 and I2.  But in that case the
13795          destination of I2 also remains unchanged.  */
13796
13797       if (NOTE_P (link->insn)
13798           || (set = single_set (link->insn)) == 0)
13799         continue;
13800
13801       reg = SET_DEST (set);
13802       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13803              || GET_CODE (reg) == STRICT_LOW_PART)
13804         reg = XEXP (reg, 0);
13805
13806       /* A LOG_LINK is defined as being placed on the first insn that uses
13807          a register and points to the insn that sets the register.  Start
13808          searching at the next insn after the target of the link and stop
13809          when we reach a set of the register or the end of the basic block.
13810
13811          Note that this correctly handles the link that used to point from
13812          I3 to I2.  Also note that not much searching is typically done here
13813          since most links don't point very far away.  */
13814
13815       for (insn = NEXT_INSN (link->insn);
13816            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
13817                      || BB_HEAD (this_basic_block->next_bb) != insn));
13818            insn = NEXT_INSN (insn))
13819         if (DEBUG_INSN_P (insn))
13820           continue;
13821         else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13822           {
13823             if (reg_referenced_p (reg, PATTERN (insn)))
13824               place = insn;
13825             break;
13826           }
13827         else if (CALL_P (insn)
13828                  && find_reg_fusage (insn, USE, reg))
13829           {
13830             place = insn;
13831             break;
13832           }
13833         else if (INSN_P (insn) && reg_set_p (reg, insn))
13834           break;
13835
13836       /* If we found a place to put the link, place it there unless there
13837          is already a link to the same insn as LINK at that point.  */
13838
13839       if (place)
13840         {
13841           struct insn_link *link2;
13842
13843           FOR_EACH_LOG_LINK (link2, place)
13844             if (link2->insn == link->insn)
13845               break;
13846
13847           if (link2 == NULL)
13848             {
13849               link->next = LOG_LINKS (place);
13850               LOG_LINKS (place) = link;
13851
13852               /* Set added_links_insn to the earliest insn we added a
13853                  link to.  */
13854               if (added_links_insn == 0
13855                   || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13856                 added_links_insn = place;
13857             }
13858         }
13859     }
13860 }
13861 \f
13862 /* Check for any register or memory mentioned in EQUIV that is not
13863    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
13864    of EXPR where some registers may have been replaced by constants.  */
13865
13866 static bool
13867 unmentioned_reg_p (rtx equiv, rtx expr)
13868 {
13869   subrtx_iterator::array_type array;
13870   FOR_EACH_SUBRTX (iter, array, equiv, NONCONST)
13871     {
13872       const_rtx x = *iter;
13873       if ((REG_P (x) || MEM_P (x))
13874           && !reg_mentioned_p (x, expr))
13875         return true;
13876     }
13877   return false;
13878 }
13879 \f
13880 DEBUG_FUNCTION void
13881 dump_combine_stats (FILE *file)
13882 {
13883   fprintf
13884     (file,
13885      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13886      combine_attempts, combine_merges, combine_extras, combine_successes);
13887 }
13888
13889 void
13890 dump_combine_total_stats (FILE *file)
13891 {
13892   fprintf
13893     (file,
13894      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13895      total_attempts, total_merges, total_extras, total_successes);
13896 }
13897 \f
13898 /* Try combining insns through substitution.  */
13899 static unsigned int
13900 rest_of_handle_combine (void)
13901 {
13902   int rebuild_jump_labels_after_combine;
13903
13904   df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13905   df_note_add_problem ();
13906   df_analyze ();
13907
13908   regstat_init_n_sets_and_refs ();
13909
13910   rebuild_jump_labels_after_combine
13911     = combine_instructions (get_insns (), max_reg_num ());
13912
13913   /* Combining insns may have turned an indirect jump into a
13914      direct jump.  Rebuild the JUMP_LABEL fields of jumping
13915      instructions.  */
13916   if (rebuild_jump_labels_after_combine)
13917     {
13918       timevar_push (TV_JUMP);
13919       rebuild_jump_labels (get_insns ());
13920       cleanup_cfg (0);
13921       timevar_pop (TV_JUMP);
13922     }
13923
13924   regstat_free_n_sets_and_refs ();
13925   return 0;
13926 }
13927
13928 namespace {
13929
13930 const pass_data pass_data_combine =
13931 {
13932   RTL_PASS, /* type */
13933   "combine", /* name */
13934   OPTGROUP_NONE, /* optinfo_flags */
13935   TV_COMBINE, /* tv_id */
13936   PROP_cfglayout, /* properties_required */
13937   0, /* properties_provided */
13938   0, /* properties_destroyed */
13939   0, /* todo_flags_start */
13940   TODO_df_finish, /* todo_flags_finish */
13941 };
13942
13943 class pass_combine : public rtl_opt_pass
13944 {
13945 public:
13946   pass_combine (gcc::context *ctxt)
13947     : rtl_opt_pass (pass_data_combine, ctxt)
13948   {}
13949
13950   /* opt_pass methods: */
13951   virtual bool gate (function *) { return (optimize > 0); }
13952   virtual unsigned int execute (function *)
13953     {
13954       return rest_of_handle_combine ();
13955     }
13956
13957 }; // class pass_combine
13958
13959 } // anon namespace
13960
13961 rtl_opt_pass *
13962 make_pass_combine (gcc::context *ctxt)
13963 {
13964   return new pass_combine (ctxt);
13965 }