1 /* LRA (local register allocator) driver and LRA utilities.
2 Copyright (C) 2010-2017 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
22 /* The Local Register Allocator (LRA) is a replacement of former
23 reload pass. It is focused to simplify code solving the reload
24 pass tasks, to make the code maintenance easier, and to implement new
25 perspective optimizations.
27 The major LRA design solutions are:
28 o division small manageable, separated sub-tasks
29 o reflection of all transformations and decisions in RTL as more
31 o insn constraints as a primary source of the info (minimizing
32 number of target-depended macros/hooks)
34 In brief LRA works by iterative insn process with the final goal is
35 to satisfy all insn and address constraints:
36 o New reload insns (in brief reloads) and reload pseudos might be
38 o Some pseudos might be spilled to assign hard registers to
40 o Recalculating spilled pseudo values (rematerialization);
41 o Changing spilled pseudos to stack memory or their equivalences;
42 o Allocation stack memory changes the address displacement and
43 new iteration is needed.
45 Here is block diagram of LRA passes:
47 ------------------------
48 --------------- | Undo inheritance for | ---------------
49 | Memory-memory | | spilled pseudos, | | New (and old) |
50 | move coalesce |<---| splits for pseudos got |<-- | pseudos |
51 --------------- | the same hard regs, | | assignment |
52 Start | | and optional reloads | ---------------
53 | | ------------------------ ^
54 V | ---------------- |
55 ----------- V | Update virtual | |
56 | Remove |----> ------------>| register | |
57 | scratches | ^ | displacements | |
58 ----------- | ---------------- |
61 | ------------ pseudos -------------------
62 | |Constraints:| or insns | Inheritance/split |
63 | | RTL |--------->| transformations |
64 | | transfor- | | in EBB scope |
65 | substi- | mations | -------------------
66 | tutions ------------
69 | Spilled pseudo | -------------------
70 | to memory |<----| Rematerialization |
71 | substitution | -------------------
75 -------------------------
76 | Hard regs substitution, |
77 | devirtalization, and |------> Finish
78 | restoring scratches got |
80 -------------------------
82 To speed up the process:
83 o We process only insns affected by changes on previous
85 o We don't use DFA-infrastructure because it results in much slower
86 compiler speed than a special IR described below does;
87 o We use a special insn representation for quick access to insn
88 info which is always *synchronized* with the current RTL;
89 o Insn IR is minimized by memory. It is divided on three parts:
90 o one specific for each insn in RTL (only operand locations);
91 o one common for all insns in RTL with the same insn code
92 (different operand attributes from machine descriptions);
93 o one oriented for maintenance of live info (list of pseudos).
95 o all insns where the pseudo is referenced;
96 o live info (conflicting hard regs, live ranges, # of
98 o data used for assigning (preferred hard regs, costs etc).
100 This file contains LRA driver, LRA utility functions and data, and
101 code for dealing with scratches. */
105 #include "coretypes.h"
112 #include "memmodel.h"
120 #include "cfgbuild.h"
123 #include "print-rtl.h"
125 /* Dump bitmap SET with TITLE and BB INDEX. */
127 lra_dump_bitmap_with_title (const char *title
, bitmap set
, int index
)
132 static const int max_nums_on_line
= 10;
134 if (bitmap_empty_p (set
))
136 fprintf (lra_dump_file
, " %s %d:", title
, index
);
137 fprintf (lra_dump_file
, "\n");
138 count
= max_nums_on_line
+ 1;
139 EXECUTE_IF_SET_IN_BITMAP (set
, 0, i
, bi
)
141 if (count
> max_nums_on_line
)
143 fprintf (lra_dump_file
, "\n ");
146 fprintf (lra_dump_file
, " %4u", i
);
149 fprintf (lra_dump_file
, "\n");
152 /* Hard registers currently not available for allocation. It can
153 changed after some hard registers become not eliminable. */
154 HARD_REG_SET lra_no_alloc_regs
;
156 static int get_new_reg_value (void);
157 static void expand_reg_info (void);
158 static void invalidate_insn_recog_data (int);
159 static int get_insn_freq (rtx_insn
*);
160 static void invalidate_insn_data_regno_info (lra_insn_recog_data_t
,
163 /* Expand all regno related info needed for LRA. */
165 expand_reg_data (int old
)
169 ira_expand_reg_equiv ();
170 for (int i
= (int) max_reg_num () - 1; i
>= old
; i
--)
171 lra_change_class (i
, ALL_REGS
, " Set", true);
174 /* Create and return a new reg of ORIGINAL mode. If ORIGINAL is NULL
175 or of VOIDmode, use MD_MODE for the new reg. Initialize its
176 register class to RCLASS. Print message about assigning class
177 RCLASS containing new register name TITLE unless it is NULL. Use
178 attributes of ORIGINAL if it is a register. The created register
179 will have unique held value. */
181 lra_create_new_reg_with_unique_value (machine_mode md_mode
, rtx original
,
182 enum reg_class rclass
, const char *title
)
187 if (original
== NULL_RTX
|| (mode
= GET_MODE (original
)) == VOIDmode
)
189 lra_assert (mode
!= VOIDmode
);
190 new_reg
= gen_reg_rtx (mode
);
191 if (original
== NULL_RTX
|| ! REG_P (original
))
193 if (lra_dump_file
!= NULL
)
194 fprintf (lra_dump_file
, " Creating newreg=%i", REGNO (new_reg
));
198 if (ORIGINAL_REGNO (original
) >= FIRST_PSEUDO_REGISTER
)
199 ORIGINAL_REGNO (new_reg
) = ORIGINAL_REGNO (original
);
200 REG_USERVAR_P (new_reg
) = REG_USERVAR_P (original
);
201 REG_POINTER (new_reg
) = REG_POINTER (original
);
202 REG_ATTRS (new_reg
) = REG_ATTRS (original
);
203 if (lra_dump_file
!= NULL
)
204 fprintf (lra_dump_file
, " Creating newreg=%i from oldreg=%i",
205 REGNO (new_reg
), REGNO (original
));
207 if (lra_dump_file
!= NULL
)
210 fprintf (lra_dump_file
, ", assigning class %s to%s%s r%d",
211 reg_class_names
[rclass
], *title
== '\0' ? "" : " ",
212 title
, REGNO (new_reg
));
213 fprintf (lra_dump_file
, "\n");
215 expand_reg_data (max_reg_num ());
216 setup_reg_classes (REGNO (new_reg
), rclass
, NO_REGS
, rclass
);
220 /* Analogous to the previous function but also inherits value of
223 lra_create_new_reg (machine_mode md_mode
, rtx original
,
224 enum reg_class rclass
, const char *title
)
229 = lra_create_new_reg_with_unique_value (md_mode
, original
, rclass
, title
);
230 if (original
!= NULL_RTX
&& REG_P (original
))
231 lra_assign_reg_val (REGNO (original
), REGNO (new_reg
));
235 /* Set up for REGNO unique hold value. */
237 lra_set_regno_unique_value (int regno
)
239 lra_reg_info
[regno
].val
= get_new_reg_value ();
242 /* Invalidate INSN related info used by LRA. The info should never be
245 lra_invalidate_insn_data (rtx_insn
*insn
)
247 lra_invalidate_insn_regno_info (insn
);
248 invalidate_insn_recog_data (INSN_UID (insn
));
251 /* Mark INSN deleted and invalidate the insn related info used by
254 lra_set_insn_deleted (rtx_insn
*insn
)
256 lra_invalidate_insn_data (insn
);
257 SET_INSN_DELETED (insn
);
260 /* Delete an unneeded INSN and any previous insns who sole purpose is
261 loading data that is dead in INSN. */
263 lra_delete_dead_insn (rtx_insn
*insn
)
265 rtx_insn
*prev
= prev_real_insn (insn
);
268 /* If the previous insn sets a register that dies in our insn,
270 if (prev
&& GET_CODE (PATTERN (prev
)) == SET
271 && (prev_dest
= SET_DEST (PATTERN (prev
)), REG_P (prev_dest
))
272 && reg_mentioned_p (prev_dest
, PATTERN (insn
))
273 && find_regno_note (insn
, REG_DEAD
, REGNO (prev_dest
))
274 && ! side_effects_p (SET_SRC (PATTERN (prev
))))
275 lra_delete_dead_insn (prev
);
277 lra_set_insn_deleted (insn
);
280 /* Emit insn x = y + z. Return NULL if we failed to do it.
281 Otherwise, return the insn. We don't use gen_add3_insn as it might
284 emit_add3_insn (rtx x
, rtx y
, rtx z
)
288 last
= get_last_insn ();
290 if (have_addptr3_insn (x
, y
, z
))
292 rtx_insn
*insn
= gen_addptr3_insn (x
, y
, z
);
294 /* If the target provides an "addptr" pattern it hopefully does
295 for a reason. So falling back to the normal add would be
297 lra_assert (insn
!= NULL_RTX
);
302 rtx_insn
*insn
= emit_insn (gen_rtx_SET (x
, gen_rtx_PLUS (GET_MODE (y
),
304 if (recog_memoized (insn
) < 0)
306 delete_insns_since (last
);
312 /* Emit insn x = x + y. Return the insn. We use gen_add2_insn as the
315 emit_add2_insn (rtx x
, rtx y
)
317 rtx_insn
*insn
= emit_add3_insn (x
, x
, y
);
318 if (insn
== NULL_RTX
)
320 insn
= gen_add2_insn (x
, y
);
321 if (insn
!= NULL_RTX
)
327 /* Target checks operands through operand predicates to recognize an
328 insn. We should have a special precaution to generate add insns
329 which are frequent results of elimination.
331 Emit insns for x = y + z. X can be used to store intermediate
332 values and should be not in Y and Z when we use X to store an
333 intermediate value. Y + Z should form [base] [+ index[ * scale]] [
334 + disp] where base and index are registers, disp and scale are
335 constants. Y should contain base if it is present, Z should
336 contain disp if any. index[*scale] can be part of Y or Z. */
338 lra_emit_add (rtx x
, rtx y
, rtx z
)
342 rtx a1
, a2
, base
, index
, disp
, scale
, index_scale
;
345 rtx_insn
*add3_insn
= emit_add3_insn (x
, y
, z
);
346 old
= max_reg_num ();
347 if (add3_insn
!= NULL
)
351 disp
= a2
= NULL_RTX
;
352 if (GET_CODE (y
) == PLUS
)
366 index_scale
= scale
= NULL_RTX
;
367 if (GET_CODE (a1
) == MULT
)
370 index
= XEXP (a1
, 0);
371 scale
= XEXP (a1
, 1);
374 else if (a2
!= NULL_RTX
&& GET_CODE (a2
) == MULT
)
377 index
= XEXP (a2
, 0);
378 scale
= XEXP (a2
, 1);
386 if ((base
!= NULL_RTX
&& ! (REG_P (base
) || GET_CODE (base
) == SUBREG
))
387 || (index
!= NULL_RTX
388 && ! (REG_P (index
) || GET_CODE (index
) == SUBREG
))
389 || (disp
!= NULL_RTX
&& ! CONSTANT_P (disp
))
390 || (scale
!= NULL_RTX
&& ! CONSTANT_P (scale
)))
392 /* Probably we have no 3 op add. Last chance is to use 2-op
393 add insn. To succeed, don't move Z to X as an address
394 segment always comes in Y. Otherwise, we might fail when
395 adding the address segment to register. */
396 lra_assert (x
!= y
&& x
!= z
);
397 emit_move_insn (x
, y
);
398 rtx_insn
*insn
= emit_add2_insn (x
, z
);
399 lra_assert (insn
!= NULL_RTX
);
403 if (index_scale
== NULL_RTX
)
405 if (disp
== NULL_RTX
)
407 /* Generate x = index_scale; x = x + base. */
408 lra_assert (index_scale
!= NULL_RTX
&& base
!= NULL_RTX
);
409 emit_move_insn (x
, index_scale
);
410 rtx_insn
*insn
= emit_add2_insn (x
, base
);
411 lra_assert (insn
!= NULL_RTX
);
413 else if (scale
== NULL_RTX
)
415 /* Try x = base + disp. */
416 lra_assert (base
!= NULL_RTX
);
417 last
= get_last_insn ();
418 rtx_insn
*move_insn
=
419 emit_move_insn (x
, gen_rtx_PLUS (GET_MODE (base
), base
, disp
));
420 if (recog_memoized (move_insn
) < 0)
422 delete_insns_since (last
);
423 /* Generate x = disp; x = x + base. */
424 emit_move_insn (x
, disp
);
425 rtx_insn
*add2_insn
= emit_add2_insn (x
, base
);
426 lra_assert (add2_insn
!= NULL_RTX
);
428 /* Generate x = x + index. */
429 if (index
!= NULL_RTX
)
431 rtx_insn
*insn
= emit_add2_insn (x
, index
);
432 lra_assert (insn
!= NULL_RTX
);
437 /* Try x = index_scale; x = x + disp; x = x + base. */
438 last
= get_last_insn ();
439 rtx_insn
*move_insn
= emit_move_insn (x
, index_scale
);
441 if (recog_memoized (move_insn
) >= 0)
443 rtx_insn
*insn
= emit_add2_insn (x
, disp
);
444 if (insn
!= NULL_RTX
)
446 if (base
== NULL_RTX
)
450 insn
= emit_add2_insn (x
, base
);
451 if (insn
!= NULL_RTX
)
460 delete_insns_since (last
);
461 /* Generate x = disp; x = x + base; x = x + index_scale. */
462 emit_move_insn (x
, disp
);
463 if (base
!= NULL_RTX
)
465 insn
= emit_add2_insn (x
, base
);
466 lra_assert (insn
!= NULL_RTX
);
468 insn
= emit_add2_insn (x
, index_scale
);
469 lra_assert (insn
!= NULL_RTX
);
474 /* Functions emit_... can create pseudos -- so expand the pseudo
476 if (old
!= max_reg_num ())
477 expand_reg_data (old
);
480 /* The number of emitted reload insns so far. */
481 int lra_curr_reload_num
;
483 /* Emit x := y, processing special case when y = u + v or y = u + v *
484 scale + w through emit_add (Y can be an address which is base +
485 index reg * scale + displacement in general case). X may be used
486 as intermediate result therefore it should be not in Y. */
488 lra_emit_move (rtx x
, rtx y
)
492 if (GET_CODE (y
) != PLUS
)
494 if (rtx_equal_p (x
, y
))
496 old
= max_reg_num ();
497 emit_move_insn (x
, y
);
499 lra_reg_info
[ORIGINAL_REGNO (x
)].last_reload
= ++lra_curr_reload_num
;
500 /* Function emit_move can create pseudos -- so expand the pseudo
502 if (old
!= max_reg_num ())
503 expand_reg_data (old
);
506 lra_emit_add (x
, XEXP (y
, 0), XEXP (y
, 1));
509 /* Update insn operands which are duplication of operands whose
510 numbers are in array of NOPS (with end marker -1). The insn is
511 represented by its LRA internal representation ID. */
513 lra_update_dups (lra_insn_recog_data_t id
, signed char *nops
)
516 struct lra_static_insn_data
*static_id
= id
->insn_static_data
;
518 for (i
= 0; i
< static_id
->n_dups
; i
++)
519 for (j
= 0; (nop
= nops
[j
]) >= 0; j
++)
520 if (static_id
->dup_num
[i
] == nop
)
521 *id
->dup_loc
[i
] = *id
->operand_loc
[nop
];
526 /* This page contains code dealing with info about registers in the
529 /* Pools for insn reg info. */
530 object_allocator
<lra_insn_reg
> lra_insn_reg_pool ("insn regs");
532 /* Create LRA insn related info about a reference to REGNO in INSN
533 with TYPE (in/out/inout), biggest reference mode MODE, flag that it
534 is reference through subreg (SUBREG_P), flag that is early
535 clobbered in the insn (EARLY_CLOBBER), and reference to the next
536 insn reg info (NEXT). If REGNO can be early clobbered,
537 alternatives in which it can be early clobbered are given by
538 EARLY_CLOBBER_ALTS. */
539 static struct lra_insn_reg
*
540 new_insn_reg (rtx_insn
*insn
, int regno
, enum op_type type
,
542 bool subreg_p
, bool early_clobber
,
543 alternative_mask early_clobber_alts
,
544 struct lra_insn_reg
*next
)
546 lra_insn_reg
*ir
= lra_insn_reg_pool
.allocate ();
548 ir
->biggest_mode
= mode
;
549 if (NONDEBUG_INSN_P (insn
)
550 && partial_subreg_p (lra_reg_info
[regno
].biggest_mode
, mode
))
551 lra_reg_info
[regno
].biggest_mode
= mode
;
552 ir
->subreg_p
= subreg_p
;
553 ir
->early_clobber
= early_clobber
;
554 ir
->early_clobber_alts
= early_clobber_alts
;
560 /* Free insn reg info list IR. */
562 free_insn_regs (struct lra_insn_reg
*ir
)
564 struct lra_insn_reg
*next_ir
;
566 for (; ir
!= NULL
; ir
= next_ir
)
569 lra_insn_reg_pool
.remove (ir
);
573 /* Finish pool for insn reg info. */
575 finish_insn_regs (void)
577 lra_insn_reg_pool
.release ();
582 /* This page contains code dealing LRA insn info (or in other words
583 LRA internal insn representation). */
585 /* Map INSN_CODE -> the static insn data. This info is valid during
586 all translation unit. */
587 struct lra_static_insn_data
*insn_code_data
[NUM_INSN_CODES
];
589 /* Debug insns are represented as a special insn with one input
590 operand which is RTL expression in var_location. */
592 /* The following data are used as static insn operand data for all
593 debug insns. If structure lra_operand_data is changed, the
594 initializer should be changed too. */
595 static struct lra_operand_data debug_operand_data
=
597 NULL
, /* alternative */
598 0, /* early_clobber_alts */
599 E_VOIDmode
, /* We are not interesting in the operand mode. */
604 /* The following data are used as static insn data for all debug
605 insns. If structure lra_static_insn_data is changed, the
606 initializer should be changed too. */
607 static struct lra_static_insn_data debug_insn_static_data
=
610 0, /* Duplication operands #. */
611 -1, /* Commutative operand #. */
612 1, /* Operands #. There is only one operand which is debug RTL
614 0, /* Duplications #. */
615 0, /* Alternatives #. We are not interesting in alternatives
616 because we does not proceed debug_insns for reloads. */
617 NULL
, /* Hard registers referenced in machine description. */
618 NULL
/* Descriptions of operands in alternatives. */
621 /* Called once per compiler work to initialize some LRA data related
624 init_insn_code_data_once (void)
626 memset (insn_code_data
, 0, sizeof (insn_code_data
));
629 /* Called once per compiler work to finalize some LRA data related to
632 finish_insn_code_data_once (void)
634 for (unsigned int i
= 0; i
< NUM_INSN_CODES
; i
++)
636 if (insn_code_data
[i
] != NULL
)
637 free (insn_code_data
[i
]);
641 /* Return static insn data, allocate and setup if necessary. Although
642 dup_num is static data (it depends only on icode), to set it up we
643 need to extract insn first. So recog_data should be valid for
644 normal insn (ICODE >= 0) before the call. */
645 static struct lra_static_insn_data
*
646 get_static_insn_data (int icode
, int nop
, int ndup
, int nalt
)
648 struct lra_static_insn_data
*data
;
651 lra_assert (icode
< (int) NUM_INSN_CODES
);
652 if (icode
>= 0 && (data
= insn_code_data
[icode
]) != NULL
)
654 lra_assert (nop
>= 0 && ndup
>= 0 && nalt
>= 0);
655 n_bytes
= sizeof (struct lra_static_insn_data
)
656 + sizeof (struct lra_operand_data
) * nop
657 + sizeof (int) * ndup
;
658 data
= XNEWVAR (struct lra_static_insn_data
, n_bytes
);
659 data
->operand_alternative
= NULL
;
660 data
->n_operands
= nop
;
662 data
->n_alternatives
= nalt
;
663 data
->operand
= ((struct lra_operand_data
*)
664 ((char *) data
+ sizeof (struct lra_static_insn_data
)));
665 data
->dup_num
= ((int *) ((char *) data
->operand
666 + sizeof (struct lra_operand_data
) * nop
));
671 insn_code_data
[icode
] = data
;
672 for (i
= 0; i
< nop
; i
++)
674 data
->operand
[i
].constraint
675 = insn_data
[icode
].operand
[i
].constraint
;
676 data
->operand
[i
].mode
= insn_data
[icode
].operand
[i
].mode
;
677 data
->operand
[i
].strict_low
= insn_data
[icode
].operand
[i
].strict_low
;
678 data
->operand
[i
].is_operator
679 = insn_data
[icode
].operand
[i
].is_operator
;
680 data
->operand
[i
].type
681 = (data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
682 : data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
684 data
->operand
[i
].is_address
= false;
686 for (i
= 0; i
< ndup
; i
++)
687 data
->dup_num
[i
] = recog_data
.dup_num
[i
];
692 /* The current length of the following array. */
693 int lra_insn_recog_data_len
;
695 /* Map INSN_UID -> the insn recog data (NULL if unknown). */
696 lra_insn_recog_data_t
*lra_insn_recog_data
;
698 /* Initialize LRA data about insns. */
700 init_insn_recog_data (void)
702 lra_insn_recog_data_len
= 0;
703 lra_insn_recog_data
= NULL
;
706 /* Expand, if necessary, LRA data about insns. */
708 check_and_expand_insn_recog_data (int index
)
712 if (lra_insn_recog_data_len
> index
)
714 old
= lra_insn_recog_data_len
;
715 lra_insn_recog_data_len
= index
* 3 / 2 + 1;
716 lra_insn_recog_data
= XRESIZEVEC (lra_insn_recog_data_t
,
718 lra_insn_recog_data_len
);
719 for (i
= old
; i
< lra_insn_recog_data_len
; i
++)
720 lra_insn_recog_data
[i
] = NULL
;
723 /* Finish LRA DATA about insn. */
725 free_insn_recog_data (lra_insn_recog_data_t data
)
727 if (data
->operand_loc
!= NULL
)
728 free (data
->operand_loc
);
729 if (data
->dup_loc
!= NULL
)
730 free (data
->dup_loc
);
731 if (data
->arg_hard_regs
!= NULL
)
732 free (data
->arg_hard_regs
);
733 if (data
->icode
< 0 && NONDEBUG_INSN_P (data
->insn
))
735 if (data
->insn_static_data
->operand_alternative
!= NULL
)
736 free (const_cast <operand_alternative
*>
737 (data
->insn_static_data
->operand_alternative
));
738 free_insn_regs (data
->insn_static_data
->hard_regs
);
739 free (data
->insn_static_data
);
741 free_insn_regs (data
->regs
);
746 /* Pools for copies. */
747 static object_allocator
<lra_copy
> lra_copy_pool ("lra copies");
749 /* Finish LRA data about all insns. */
751 finish_insn_recog_data (void)
754 lra_insn_recog_data_t data
;
756 for (i
= 0; i
< lra_insn_recog_data_len
; i
++)
757 if ((data
= lra_insn_recog_data
[i
]) != NULL
)
758 free_insn_recog_data (data
);
760 lra_copy_pool
.release ();
761 lra_insn_reg_pool
.release ();
762 free (lra_insn_recog_data
);
765 /* Setup info about operands in alternatives of LRA DATA of insn. */
767 setup_operand_alternative (lra_insn_recog_data_t data
,
768 const operand_alternative
*op_alt
)
771 int icode
= data
->icode
;
772 struct lra_static_insn_data
*static_data
= data
->insn_static_data
;
774 static_data
->commutative
= -1;
775 nop
= static_data
->n_operands
;
776 nalt
= static_data
->n_alternatives
;
777 static_data
->operand_alternative
= op_alt
;
778 for (i
= 0; i
< nop
; i
++)
780 static_data
->operand
[i
].early_clobber_alts
= 0;
781 static_data
->operand
[i
].early_clobber
= false;
782 static_data
->operand
[i
].is_address
= false;
783 if (static_data
->operand
[i
].constraint
[0] == '%')
785 /* We currently only support one commutative pair of operands. */
786 if (static_data
->commutative
< 0)
787 static_data
->commutative
= i
;
789 lra_assert (icode
< 0); /* Asm */
790 /* The last operand should not be marked commutative. */
791 lra_assert (i
!= nop
- 1);
794 for (j
= 0; j
< nalt
; j
++)
795 for (i
= 0; i
< nop
; i
++, op_alt
++)
797 static_data
->operand
[i
].early_clobber
|= op_alt
->earlyclobber
;
798 if (op_alt
->earlyclobber
)
799 static_data
->operand
[i
].early_clobber_alts
|= (alternative_mask
) 1 << j
;
800 static_data
->operand
[i
].is_address
|= op_alt
->is_address
;
804 /* Recursively process X and collect info about registers, which are
805 not the insn operands, in X with TYPE (in/out/inout) and flag that
806 it is early clobbered in the insn (EARLY_CLOBBER) and add the info
807 to LIST. X is a part of insn given by DATA. Return the result
809 static struct lra_insn_reg
*
810 collect_non_operand_hard_regs (rtx
*x
, lra_insn_recog_data_t data
,
811 struct lra_insn_reg
*list
,
812 enum op_type type
, bool early_clobber
)
814 int i
, j
, regno
, last
;
817 struct lra_insn_reg
*curr
;
819 enum rtx_code code
= GET_CODE (op
);
820 const char *fmt
= GET_RTX_FORMAT (code
);
822 for (i
= 0; i
< data
->insn_static_data
->n_operands
; i
++)
823 if (x
== data
->operand_loc
[i
])
824 /* It is an operand loc. Stop here. */
826 for (i
= 0; i
< data
->insn_static_data
->n_dups
; i
++)
827 if (x
== data
->dup_loc
[i
])
828 /* It is a dup loc. Stop here. */
830 mode
= GET_MODE (op
);
834 op
= SUBREG_REG (op
);
835 code
= GET_CODE (op
);
836 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (op
)))
838 mode
= GET_MODE (op
);
839 if (GET_MODE_SIZE (mode
) > REGMODE_NATURAL_SIZE (mode
))
845 if ((regno
= REGNO (op
)) >= FIRST_PSEUDO_REGISTER
)
847 /* Process all regs even unallocatable ones as we need info
848 about all regs for rematerialization pass. */
849 for (last
= end_hard_regno (mode
, regno
); regno
< last
; regno
++)
851 for (curr
= list
; curr
!= NULL
; curr
= curr
->next
)
852 if (curr
->regno
== regno
&& curr
->subreg_p
== subreg_p
853 && curr
->biggest_mode
== mode
)
855 if (curr
->type
!= type
)
856 curr
->type
= OP_INOUT
;
859 curr
->early_clobber
= true;
860 curr
->early_clobber_alts
= ALL_ALTERNATIVES
;
866 /* This is a new hard regno or the info can not be
867 integrated into the found structure. */
871 /* This clobber is to inform popping floating
873 && ! (FIRST_STACK_REG
<= regno
874 && regno
<= LAST_STACK_REG
));
876 list
= new_insn_reg (data
->insn
, regno
, type
, mode
, subreg_p
,
878 early_clobber
? ALL_ALTERNATIVES
: 0, list
);
886 list
= collect_non_operand_hard_regs (&SET_DEST (op
), data
,
887 list
, OP_OUT
, false);
888 list
= collect_non_operand_hard_regs (&SET_SRC (op
), data
,
892 /* We treat clobber of non-operand hard registers as early
893 clobber (the behavior is expected from asm). */
894 list
= collect_non_operand_hard_regs (&XEXP (op
, 0), data
,
897 case PRE_INC
: case PRE_DEC
: case POST_INC
: case POST_DEC
:
898 list
= collect_non_operand_hard_regs (&XEXP (op
, 0), data
,
899 list
, OP_INOUT
, false);
901 case PRE_MODIFY
: case POST_MODIFY
:
902 list
= collect_non_operand_hard_regs (&XEXP (op
, 0), data
,
903 list
, OP_INOUT
, false);
904 list
= collect_non_operand_hard_regs (&XEXP (op
, 1), data
,
908 fmt
= GET_RTX_FORMAT (code
);
909 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
912 list
= collect_non_operand_hard_regs (&XEXP (op
, i
), data
,
914 else if (fmt
[i
] == 'E')
915 for (j
= XVECLEN (op
, i
) - 1; j
>= 0; j
--)
916 list
= collect_non_operand_hard_regs (&XVECEXP (op
, i
, j
), data
,
923 /* Set up and return info about INSN. Set up the info if it is not set up
925 lra_insn_recog_data_t
926 lra_set_insn_recog_data (rtx_insn
*insn
)
928 lra_insn_recog_data_t data
;
931 unsigned int uid
= INSN_UID (insn
);
932 struct lra_static_insn_data
*insn_static_data
;
934 check_and_expand_insn_recog_data (uid
);
935 if (DEBUG_INSN_P (insn
))
939 icode
= INSN_CODE (insn
);
941 /* It might be a new simple insn which is not recognized yet. */
942 INSN_CODE (insn
) = icode
= recog_memoized (insn
);
944 data
= XNEW (struct lra_insn_recog_data
);
945 lra_insn_recog_data
[uid
] = data
;
947 data
->used_insn_alternative
= -1;
950 if (DEBUG_INSN_P (insn
))
952 data
->insn_static_data
= &debug_insn_static_data
;
953 data
->dup_loc
= NULL
;
954 data
->arg_hard_regs
= NULL
;
955 data
->preferred_alternatives
= ALL_ALTERNATIVES
;
956 data
->operand_loc
= XNEWVEC (rtx
*, 1);
957 data
->operand_loc
[0] = &INSN_VAR_LOCATION_LOC (insn
);
963 machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
964 const char *constraints
[MAX_RECOG_OPERANDS
];
966 nop
= asm_noperands (PATTERN (insn
));
967 data
->operand_loc
= data
->dup_loc
= NULL
;
971 /* It is a special insn like USE or CLOBBER. We should
972 recognize any regular insn otherwise LRA can do nothing
974 gcc_assert (GET_CODE (PATTERN (insn
)) == USE
975 || GET_CODE (PATTERN (insn
)) == CLOBBER
976 || GET_CODE (PATTERN (insn
)) == ASM_INPUT
);
977 data
->insn_static_data
= insn_static_data
978 = get_static_insn_data (-1, 0, 0, nalt
);
982 /* expand_asm_operands makes sure there aren't too many
984 lra_assert (nop
<= MAX_RECOG_OPERANDS
);
986 data
->operand_loc
= XNEWVEC (rtx
*, nop
);
987 /* Now get the operand values and constraints out of the
989 decode_asm_operands (PATTERN (insn
), NULL
,
991 constraints
, operand_mode
, NULL
);
994 const char *p
= recog_data
.constraints
[0];
996 for (p
= constraints
[0]; *p
; p
++)
999 data
->insn_static_data
= insn_static_data
1000 = get_static_insn_data (-1, nop
, 0, nalt
);
1001 for (i
= 0; i
< nop
; i
++)
1003 insn_static_data
->operand
[i
].mode
= operand_mode
[i
];
1004 insn_static_data
->operand
[i
].constraint
= constraints
[i
];
1005 insn_static_data
->operand
[i
].strict_low
= false;
1006 insn_static_data
->operand
[i
].is_operator
= false;
1007 insn_static_data
->operand
[i
].is_address
= false;
1010 for (i
= 0; i
< insn_static_data
->n_operands
; i
++)
1011 insn_static_data
->operand
[i
].type
1012 = (insn_static_data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
1013 : insn_static_data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
1015 data
->preferred_alternatives
= ALL_ALTERNATIVES
;
1018 operand_alternative
*op_alt
= XCNEWVEC (operand_alternative
,
1020 preprocess_constraints (nop
, nalt
, constraints
, op_alt
);
1021 setup_operand_alternative (data
, op_alt
);
1026 insn_extract (insn
);
1027 data
->insn_static_data
= insn_static_data
1028 = get_static_insn_data (icode
, insn_data
[icode
].n_operands
,
1029 insn_data
[icode
].n_dups
,
1030 insn_data
[icode
].n_alternatives
);
1031 n
= insn_static_data
->n_operands
;
1036 locs
= XNEWVEC (rtx
*, n
);
1037 memcpy (locs
, recog_data
.operand_loc
, n
* sizeof (rtx
*));
1039 data
->operand_loc
= locs
;
1040 n
= insn_static_data
->n_dups
;
1045 locs
= XNEWVEC (rtx
*, n
);
1046 memcpy (locs
, recog_data
.dup_loc
, n
* sizeof (rtx
*));
1048 data
->dup_loc
= locs
;
1049 data
->preferred_alternatives
= get_preferred_alternatives (insn
);
1050 const operand_alternative
*op_alt
= preprocess_insn_constraints (icode
);
1051 if (!insn_static_data
->operand_alternative
)
1052 setup_operand_alternative (data
, op_alt
);
1053 else if (op_alt
!= insn_static_data
->operand_alternative
)
1054 insn_static_data
->operand_alternative
= op_alt
;
1056 if (GET_CODE (PATTERN (insn
)) == CLOBBER
|| GET_CODE (PATTERN (insn
)) == USE
)
1057 insn_static_data
->hard_regs
= NULL
;
1059 insn_static_data
->hard_regs
1060 = collect_non_operand_hard_regs (&PATTERN (insn
), data
,
1061 NULL
, OP_IN
, false);
1062 data
->arg_hard_regs
= NULL
;
1067 int n_hard_regs
, regno
, arg_hard_regs
[FIRST_PSEUDO_REGISTER
];
1070 /* Finding implicit hard register usage. We believe it will be
1071 not changed whatever transformations are used. Call insns
1072 are such example. */
1073 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
1075 link
= XEXP (link
, 1))
1076 if (((use_p
= GET_CODE (XEXP (link
, 0)) == USE
)
1077 || GET_CODE (XEXP (link
, 0)) == CLOBBER
)
1078 && REG_P (XEXP (XEXP (link
, 0), 0)))
1080 regno
= REGNO (XEXP (XEXP (link
, 0), 0));
1081 lra_assert (regno
< FIRST_PSEUDO_REGISTER
);
1082 /* It is an argument register. */
1083 for (i
= REG_NREGS (XEXP (XEXP (link
, 0), 0)) - 1; i
>= 0; i
--)
1084 arg_hard_regs
[n_hard_regs
++]
1085 = regno
+ i
+ (use_p
? 0 : FIRST_PSEUDO_REGISTER
);
1087 if (n_hard_regs
!= 0)
1089 arg_hard_regs
[n_hard_regs
++] = -1;
1090 data
->arg_hard_regs
= XNEWVEC (int, n_hard_regs
);
1091 memcpy (data
->arg_hard_regs
, arg_hard_regs
,
1092 sizeof (int) * n_hard_regs
);
1095 /* Some output operand can be recognized only from the context not
1096 from the constraints which are empty in this case. Call insn may
1097 contain a hard register in set destination with empty constraint
1098 and extract_insn treats them as an input. */
1099 for (i
= 0; i
< insn_static_data
->n_operands
; i
++)
1103 struct lra_operand_data
*operand
= &insn_static_data
->operand
[i
];
1105 /* ??? Should we treat 'X' the same way. It looks to me that
1106 'X' means anything and empty constraint means we do not
1108 if (operand
->type
!= OP_IN
|| *operand
->constraint
!= '\0'
1109 || operand
->is_operator
)
1111 pat
= PATTERN (insn
);
1112 if (GET_CODE (pat
) == SET
)
1114 if (data
->operand_loc
[i
] != &SET_DEST (pat
))
1117 else if (GET_CODE (pat
) == PARALLEL
)
1119 for (j
= XVECLEN (pat
, 0) - 1; j
>= 0; j
--)
1121 set
= XVECEXP (PATTERN (insn
), 0, j
);
1122 if (GET_CODE (set
) == SET
1123 && &SET_DEST (set
) == data
->operand_loc
[i
])
1131 operand
->type
= OP_OUT
;
1136 /* Return info about insn give by UID. The info should be already set
1138 static lra_insn_recog_data_t
1139 get_insn_recog_data_by_uid (int uid
)
1141 lra_insn_recog_data_t data
;
1143 data
= lra_insn_recog_data
[uid
];
1144 lra_assert (data
!= NULL
);
1148 /* Invalidate all info about insn given by its UID. */
1150 invalidate_insn_recog_data (int uid
)
1152 lra_insn_recog_data_t data
;
1154 data
= lra_insn_recog_data
[uid
];
1155 lra_assert (data
!= NULL
);
1156 free_insn_recog_data (data
);
1157 lra_insn_recog_data
[uid
] = NULL
;
1160 /* Update all the insn info about INSN. It is usually called when
1161 something in the insn was changed. Return the updated info. */
1162 lra_insn_recog_data_t
1163 lra_update_insn_recog_data (rtx_insn
*insn
)
1165 lra_insn_recog_data_t data
;
1167 unsigned int uid
= INSN_UID (insn
);
1168 struct lra_static_insn_data
*insn_static_data
;
1169 HOST_WIDE_INT sp_offset
= 0;
1171 check_and_expand_insn_recog_data (uid
);
1172 if ((data
= lra_insn_recog_data
[uid
]) != NULL
1173 && data
->icode
!= INSN_CODE (insn
))
1175 sp_offset
= data
->sp_offset
;
1176 invalidate_insn_data_regno_info (data
, insn
, get_insn_freq (insn
));
1177 invalidate_insn_recog_data (uid
);
1182 data
= lra_get_insn_recog_data (insn
);
1183 /* Initiate or restore SP offset. */
1184 data
->sp_offset
= sp_offset
;
1187 insn_static_data
= data
->insn_static_data
;
1188 data
->used_insn_alternative
= -1;
1189 if (DEBUG_INSN_P (insn
))
1191 if (data
->icode
< 0)
1194 machine_mode operand_mode
[MAX_RECOG_OPERANDS
];
1195 const char *constraints
[MAX_RECOG_OPERANDS
];
1197 nop
= asm_noperands (PATTERN (insn
));
1200 lra_assert (nop
== data
->insn_static_data
->n_operands
);
1201 /* Now get the operand values and constraints out of the
1203 decode_asm_operands (PATTERN (insn
), NULL
,
1205 constraints
, operand_mode
, NULL
);
1208 for (int i
= 0; i
< nop
; i
++)
1210 (insn_static_data
->operand
[i
].mode
== operand_mode
[i
]
1211 && insn_static_data
->operand
[i
].constraint
== constraints
[i
]
1212 && ! insn_static_data
->operand
[i
].is_operator
);
1216 for (int i
= 0; i
< insn_static_data
->n_operands
; i
++)
1218 (insn_static_data
->operand
[i
].type
1219 == (insn_static_data
->operand
[i
].constraint
[0] == '=' ? OP_OUT
1220 : insn_static_data
->operand
[i
].constraint
[0] == '+' ? OP_INOUT
1225 insn_extract (insn
);
1226 n
= insn_static_data
->n_operands
;
1228 memcpy (data
->operand_loc
, recog_data
.operand_loc
, n
* sizeof (rtx
*));
1229 n
= insn_static_data
->n_dups
;
1231 memcpy (data
->dup_loc
, recog_data
.dup_loc
, n
* sizeof (rtx
*));
1232 lra_assert (check_bool_attrs (insn
));
1237 /* Set up that INSN is using alternative ALT now. */
1239 lra_set_used_insn_alternative (rtx_insn
*insn
, int alt
)
1241 lra_insn_recog_data_t data
;
1243 data
= lra_get_insn_recog_data (insn
);
1244 data
->used_insn_alternative
= alt
;
1247 /* Set up that insn with UID is using alternative ALT now. The insn
1248 info should be already set up. */
1250 lra_set_used_insn_alternative_by_uid (int uid
, int alt
)
1252 lra_insn_recog_data_t data
;
1254 check_and_expand_insn_recog_data (uid
);
1255 data
= lra_insn_recog_data
[uid
];
1256 lra_assert (data
!= NULL
);
1257 data
->used_insn_alternative
= alt
;
1262 /* This page contains code dealing with common register info and
1265 /* The size of the following array. */
1266 static int reg_info_size
;
1267 /* Common info about each register. */
1268 struct lra_reg
*lra_reg_info
;
1270 /* Last register value. */
1271 static int last_reg_value
;
1273 /* Return new register value. */
1275 get_new_reg_value (void)
1277 return ++last_reg_value
;
1280 /* Vec referring to pseudo copies. */
1281 static vec
<lra_copy_t
> copy_vec
;
1283 /* Initialize I-th element of lra_reg_info. */
1285 initialize_lra_reg_info_element (int i
)
1287 bitmap_initialize (&lra_reg_info
[i
].insn_bitmap
, ®_obstack
);
1289 lra_reg_info
[i
].no_stack_p
= false;
1291 CLEAR_HARD_REG_SET (lra_reg_info
[i
].conflict_hard_regs
);
1292 CLEAR_HARD_REG_SET (lra_reg_info
[i
].actual_call_used_reg_set
);
1293 lra_reg_info
[i
].preferred_hard_regno1
= -1;
1294 lra_reg_info
[i
].preferred_hard_regno2
= -1;
1295 lra_reg_info
[i
].preferred_hard_regno_profit1
= 0;
1296 lra_reg_info
[i
].preferred_hard_regno_profit2
= 0;
1297 lra_reg_info
[i
].biggest_mode
= VOIDmode
;
1298 lra_reg_info
[i
].live_ranges
= NULL
;
1299 lra_reg_info
[i
].nrefs
= lra_reg_info
[i
].freq
= 0;
1300 lra_reg_info
[i
].last_reload
= 0;
1301 lra_reg_info
[i
].restore_rtx
= NULL_RTX
;
1302 lra_reg_info
[i
].val
= get_new_reg_value ();
1303 lra_reg_info
[i
].offset
= 0;
1304 lra_reg_info
[i
].copies
= NULL
;
1307 /* Initialize common reg info and copies. */
1309 init_reg_info (void)
1314 reg_info_size
= max_reg_num () * 3 / 2 + 1;
1315 lra_reg_info
= XNEWVEC (struct lra_reg
, reg_info_size
);
1316 for (i
= 0; i
< reg_info_size
; i
++)
1317 initialize_lra_reg_info_element (i
);
1318 copy_vec
.truncate (0);
1322 /* Finish common reg info and copies. */
1324 finish_reg_info (void)
1328 for (i
= 0; i
< reg_info_size
; i
++)
1329 bitmap_clear (&lra_reg_info
[i
].insn_bitmap
);
1330 free (lra_reg_info
);
1334 /* Expand common reg info if it is necessary. */
1336 expand_reg_info (void)
1338 int i
, old
= reg_info_size
;
1340 if (reg_info_size
> max_reg_num ())
1342 reg_info_size
= max_reg_num () * 3 / 2 + 1;
1343 lra_reg_info
= XRESIZEVEC (struct lra_reg
, lra_reg_info
, reg_info_size
);
1344 for (i
= old
; i
< reg_info_size
; i
++)
1345 initialize_lra_reg_info_element (i
);
1348 /* Free all copies. */
1350 lra_free_copies (void)
1354 while (copy_vec
.length () != 0)
1356 cp
= copy_vec
.pop ();
1357 lra_reg_info
[cp
->regno1
].copies
= lra_reg_info
[cp
->regno2
].copies
= NULL
;
1358 lra_copy_pool
.remove (cp
);
1362 /* Create copy of two pseudos REGNO1 and REGNO2. The copy execution
1363 frequency is FREQ. */
1365 lra_create_copy (int regno1
, int regno2
, int freq
)
1370 lra_assert (regno1
!= regno2
);
1371 regno1_dest_p
= true;
1372 if (regno1
> regno2
)
1374 std::swap (regno1
, regno2
);
1375 regno1_dest_p
= false;
1377 cp
= lra_copy_pool
.allocate ();
1378 copy_vec
.safe_push (cp
);
1379 cp
->regno1_dest_p
= regno1_dest_p
;
1381 cp
->regno1
= regno1
;
1382 cp
->regno2
= regno2
;
1383 cp
->regno1_next
= lra_reg_info
[regno1
].copies
;
1384 lra_reg_info
[regno1
].copies
= cp
;
1385 cp
->regno2_next
= lra_reg_info
[regno2
].copies
;
1386 lra_reg_info
[regno2
].copies
= cp
;
1387 if (lra_dump_file
!= NULL
)
1388 fprintf (lra_dump_file
, " Creating copy r%d%sr%d@%d\n",
1389 regno1
, regno1_dest_p
? "<-" : "->", regno2
, freq
);
1392 /* Return N-th (0, 1, ...) copy. If there is no copy, return
1395 lra_get_copy (int n
)
1397 if (n
>= (int) copy_vec
.length ())
1404 /* This page contains code dealing with info about registers in
1407 /* Process X of insn UID recursively and add info (operand type is
1408 given by TYPE, flag of that it is early clobber is EARLY_CLOBBER)
1409 about registers in X to the insn DATA. If X can be early clobbered,
1410 alternatives in which it can be early clobbered are given by
1411 EARLY_CLOBBER_ALTS. */
1413 add_regs_to_insn_regno_info (lra_insn_recog_data_t data
, rtx x
, int uid
,
1414 enum op_type type
, bool early_clobber
,
1415 alternative_mask early_clobber_alts
)
1422 struct lra_insn_reg
*curr
;
1424 code
= GET_CODE (x
);
1425 mode
= GET_MODE (x
);
1427 if (GET_CODE (x
) == SUBREG
)
1430 code
= GET_CODE (x
);
1431 if (GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (x
)))
1433 mode
= GET_MODE (x
);
1434 if (GET_MODE_SIZE (mode
) > REGMODE_NATURAL_SIZE (mode
))
1441 /* Process all regs even unallocatable ones as we need info about
1442 all regs for rematerialization pass. */
1444 if (bitmap_set_bit (&lra_reg_info
[regno
].insn_bitmap
, uid
))
1446 data
->regs
= new_insn_reg (data
->insn
, regno
, type
, mode
, subreg_p
,
1447 early_clobber
, early_clobber_alts
,
1453 for (curr
= data
->regs
; curr
!= NULL
; curr
= curr
->next
)
1454 if (curr
->regno
== regno
)
1456 if (curr
->subreg_p
!= subreg_p
|| curr
->biggest_mode
!= mode
)
1457 /* The info can not be integrated into the found
1459 data
->regs
= new_insn_reg (data
->insn
, regno
, type
, mode
,
1460 subreg_p
, early_clobber
,
1461 early_clobber_alts
, data
->regs
);
1464 if (curr
->type
!= type
)
1465 curr
->type
= OP_INOUT
;
1466 if (curr
->early_clobber
!= early_clobber
)
1467 curr
->early_clobber
= true;
1468 curr
->early_clobber_alts
|= early_clobber_alts
;
1479 add_regs_to_insn_regno_info (data
, SET_DEST (x
), uid
, OP_OUT
, false, 0);
1480 add_regs_to_insn_regno_info (data
, SET_SRC (x
), uid
, OP_IN
, false, 0);
1483 /* We treat clobber of non-operand hard registers as early
1484 clobber (the behavior is expected from asm). */
1485 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), uid
, OP_OUT
, true, ALL_ALTERNATIVES
);
1487 case PRE_INC
: case PRE_DEC
: case POST_INC
: case POST_DEC
:
1488 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), uid
, OP_INOUT
, false, 0);
1490 case PRE_MODIFY
: case POST_MODIFY
:
1491 add_regs_to_insn_regno_info (data
, XEXP (x
, 0), uid
, OP_INOUT
, false, 0);
1492 add_regs_to_insn_regno_info (data
, XEXP (x
, 1), uid
, OP_IN
, false, 0);
1495 if ((code
!= PARALLEL
&& code
!= EXPR_LIST
) || type
!= OP_OUT
)
1496 /* Some targets place small structures in registers for return
1497 values of functions, and those registers are wrapped in
1498 PARALLEL that we may see as the destination of a SET. Here
1501 (call_insn 13 12 14 2 (set (parallel:BLK [
1502 (expr_list:REG_DEP_TRUE (reg:DI 0 ax)
1504 (expr_list:REG_DEP_TRUE (reg:DI 1 dx)
1505 (const_int 8 [0x8]))
1507 (call (mem:QI (symbol_ref:DI (... */
1509 fmt
= GET_RTX_FORMAT (code
);
1510 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1513 add_regs_to_insn_regno_info (data
, XEXP (x
, i
), uid
, type
, false, 0);
1514 else if (fmt
[i
] == 'E')
1516 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1517 add_regs_to_insn_regno_info (data
, XVECEXP (x
, i
, j
), uid
,
1524 /* Return execution frequency of INSN. */
1526 get_insn_freq (rtx_insn
*insn
)
1528 basic_block bb
= BLOCK_FOR_INSN (insn
);
1530 gcc_checking_assert (bb
!= NULL
);
1531 return REG_FREQ_FROM_BB (bb
);
1534 /* Invalidate all reg info of INSN with DATA and execution frequency
1535 FREQ. Update common info about the invalidated registers. */
1537 invalidate_insn_data_regno_info (lra_insn_recog_data_t data
, rtx_insn
*insn
,
1543 struct lra_insn_reg
*ir
, *next_ir
;
1545 uid
= INSN_UID (insn
);
1546 debug_p
= DEBUG_INSN_P (insn
);
1547 for (ir
= data
->regs
; ir
!= NULL
; ir
= next_ir
)
1551 lra_insn_reg_pool
.remove (ir
);
1552 bitmap_clear_bit (&lra_reg_info
[i
].insn_bitmap
, uid
);
1553 if (i
>= FIRST_PSEUDO_REGISTER
&& ! debug_p
)
1555 lra_reg_info
[i
].nrefs
--;
1556 lra_reg_info
[i
].freq
-= freq
;
1557 lra_assert (lra_reg_info
[i
].nrefs
>= 0 && lra_reg_info
[i
].freq
>= 0);
1563 /* Invalidate all reg info of INSN. Update common info about the
1564 invalidated registers. */
1566 lra_invalidate_insn_regno_info (rtx_insn
*insn
)
1568 invalidate_insn_data_regno_info (lra_get_insn_recog_data (insn
), insn
,
1569 get_insn_freq (insn
));
1572 /* Update common reg info from reg info of insn given by its DATA and
1573 execution frequency FREQ. */
1575 setup_insn_reg_info (lra_insn_recog_data_t data
, int freq
)
1578 struct lra_insn_reg
*ir
;
1580 for (ir
= data
->regs
; ir
!= NULL
; ir
= ir
->next
)
1581 if ((i
= ir
->regno
) >= FIRST_PSEUDO_REGISTER
)
1583 lra_reg_info
[i
].nrefs
++;
1584 lra_reg_info
[i
].freq
+= freq
;
1588 /* Set up insn reg info of INSN. Update common reg info from reg info
1591 lra_update_insn_regno_info (rtx_insn
*insn
)
1594 lra_insn_recog_data_t data
;
1595 struct lra_static_insn_data
*static_data
;
1599 if (! INSN_P (insn
))
1601 data
= lra_get_insn_recog_data (insn
);
1602 static_data
= data
->insn_static_data
;
1603 freq
= get_insn_freq (insn
);
1604 invalidate_insn_data_regno_info (data
, insn
, freq
);
1605 uid
= INSN_UID (insn
);
1606 for (i
= static_data
->n_operands
- 1; i
>= 0; i
--)
1607 add_regs_to_insn_regno_info (data
, *data
->operand_loc
[i
], uid
,
1608 static_data
->operand
[i
].type
,
1609 static_data
->operand
[i
].early_clobber
,
1610 static_data
->operand
[i
].early_clobber_alts
);
1611 if ((code
= GET_CODE (PATTERN (insn
))) == CLOBBER
|| code
== USE
)
1612 add_regs_to_insn_regno_info (data
, XEXP (PATTERN (insn
), 0), uid
,
1613 code
== USE
? OP_IN
: OP_OUT
, false, 0);
1615 /* On some targets call insns can refer to pseudos in memory in
1616 CALL_INSN_FUNCTION_USAGE list. Process them in order to
1617 consider their occurrences in calls for different
1618 transformations (e.g. inheritance) with given pseudos. */
1619 for (link
= CALL_INSN_FUNCTION_USAGE (insn
);
1621 link
= XEXP (link
, 1))
1622 if (((code
= GET_CODE (XEXP (link
, 0))) == USE
|| code
== CLOBBER
)
1623 && MEM_P (XEXP (XEXP (link
, 0), 0)))
1624 add_regs_to_insn_regno_info (data
, XEXP (XEXP (link
, 0), 0), uid
,
1625 code
== USE
? OP_IN
: OP_OUT
, false, 0);
1626 if (NONDEBUG_INSN_P (insn
))
1627 setup_insn_reg_info (data
, freq
);
1630 /* Return reg info of insn given by it UID. */
1631 struct lra_insn_reg
*
1632 lra_get_insn_regs (int uid
)
1634 lra_insn_recog_data_t data
;
1636 data
= get_insn_recog_data_by_uid (uid
);
1642 /* Recursive hash function for RTL X. */
1644 lra_rtx_hash (rtx x
)
1654 code
= GET_CODE (x
);
1655 val
+= (int) code
+ 4095;
1657 /* Some RTL can be compared nonrecursively. */
1661 return val
+ REGNO (x
);
1664 return iterative_hash_object (XEXP (x
, 0), val
);
1667 return iterative_hash_object (XSTR (x
, 0), val
);
1679 /* Hash the elements. */
1680 fmt
= GET_RTX_FORMAT (code
);
1681 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1686 val
+= XWINT (x
, i
);
1696 val
+= XVECLEN (x
, i
);
1698 for (j
= 0; j
< XVECLEN (x
, i
); j
++)
1699 val
+= lra_rtx_hash (XVECEXP (x
, i
, j
));
1703 val
+= lra_rtx_hash (XEXP (x
, i
));
1708 val
+= htab_hash_string (XSTR (x
, i
));
1716 /* It is believed that rtx's at this level will never
1717 contain anything but integers and other rtx's, except for
1718 within LABEL_REFs and SYMBOL_REFs. */
1728 /* This page contains code dealing with stack of the insns which
1729 should be processed by the next constraint pass. */
1731 /* Bitmap used to put an insn on the stack only in one exemplar. */
1732 static sbitmap lra_constraint_insn_stack_bitmap
;
1734 /* The stack itself. */
1735 vec
<rtx_insn
*> lra_constraint_insn_stack
;
1737 /* Put INSN on the stack. If ALWAYS_UPDATE is true, always update the reg
1738 info for INSN, otherwise only update it if INSN is not already on the
1741 lra_push_insn_1 (rtx_insn
*insn
, bool always_update
)
1743 unsigned int uid
= INSN_UID (insn
);
1745 lra_update_insn_regno_info (insn
);
1746 if (uid
>= SBITMAP_SIZE (lra_constraint_insn_stack_bitmap
))
1747 lra_constraint_insn_stack_bitmap
=
1748 sbitmap_resize (lra_constraint_insn_stack_bitmap
, 3 * uid
/ 2, 0);
1749 if (bitmap_bit_p (lra_constraint_insn_stack_bitmap
, uid
))
1751 bitmap_set_bit (lra_constraint_insn_stack_bitmap
, uid
);
1752 if (! always_update
)
1753 lra_update_insn_regno_info (insn
);
1754 lra_constraint_insn_stack
.safe_push (insn
);
1757 /* Put INSN on the stack. */
1759 lra_push_insn (rtx_insn
*insn
)
1761 lra_push_insn_1 (insn
, false);
1764 /* Put INSN on the stack and update its reg info. */
1766 lra_push_insn_and_update_insn_regno_info (rtx_insn
*insn
)
1768 lra_push_insn_1 (insn
, true);
1771 /* Put insn with UID on the stack. */
1773 lra_push_insn_by_uid (unsigned int uid
)
1775 lra_push_insn (lra_insn_recog_data
[uid
]->insn
);
1778 /* Take the last-inserted insns off the stack and return it. */
1782 rtx_insn
*insn
= lra_constraint_insn_stack
.pop ();
1783 bitmap_clear_bit (lra_constraint_insn_stack_bitmap
, INSN_UID (insn
));
1787 /* Return the current size of the insn stack. */
1789 lra_insn_stack_length (void)
1791 return lra_constraint_insn_stack
.length ();
1794 /* Push insns FROM to TO (excluding it) going in reverse order. */
1796 push_insns (rtx_insn
*from
, rtx_insn
*to
)
1800 if (from
== NULL_RTX
)
1802 for (insn
= from
; insn
!= to
; insn
= PREV_INSN (insn
))
1804 lra_push_insn (insn
);
1807 /* Set up sp offset for insn in range [FROM, LAST]. The offset is
1808 taken from the next BB insn after LAST or zero if there in such
1811 setup_sp_offset (rtx_insn
*from
, rtx_insn
*last
)
1813 rtx_insn
*before
= next_nonnote_insn_bb (last
);
1814 HOST_WIDE_INT offset
= (before
== NULL_RTX
|| ! INSN_P (before
)
1815 ? 0 : lra_get_insn_recog_data (before
)->sp_offset
);
1817 for (rtx_insn
*insn
= from
; insn
!= NEXT_INSN (last
); insn
= NEXT_INSN (insn
))
1818 lra_get_insn_recog_data (insn
)->sp_offset
= offset
;
1821 /* Emit insns BEFORE before INSN and insns AFTER after INSN. Put the
1822 insns onto the stack. Print about emitting the insns with
1825 lra_process_new_insns (rtx_insn
*insn
, rtx_insn
*before
, rtx_insn
*after
,
1830 if (before
== NULL_RTX
&& after
== NULL_RTX
)
1832 if (lra_dump_file
!= NULL
)
1834 dump_insn_slim (lra_dump_file
, insn
);
1835 if (before
!= NULL_RTX
)
1837 fprintf (lra_dump_file
," %s before:\n", title
);
1838 dump_rtl_slim (lra_dump_file
, before
, NULL
, -1, 0);
1840 if (after
!= NULL_RTX
)
1842 fprintf (lra_dump_file
, " %s after:\n", title
);
1843 dump_rtl_slim (lra_dump_file
, after
, NULL
, -1, 0);
1845 fprintf (lra_dump_file
, "\n");
1847 if (before
!= NULL_RTX
)
1849 if (cfun
->can_throw_non_call_exceptions
)
1850 copy_reg_eh_region_note_forward (insn
, before
, NULL
);
1851 emit_insn_before (before
, insn
);
1852 push_insns (PREV_INSN (insn
), PREV_INSN (before
));
1853 setup_sp_offset (before
, PREV_INSN (insn
));
1855 if (after
!= NULL_RTX
)
1857 if (cfun
->can_throw_non_call_exceptions
)
1858 copy_reg_eh_region_note_forward (insn
, after
, NULL
);
1859 for (last
= after
; NEXT_INSN (last
) != NULL_RTX
; last
= NEXT_INSN (last
))
1861 emit_insn_after (after
, insn
);
1862 push_insns (last
, insn
);
1863 setup_sp_offset (after
, last
);
1865 if (cfun
->can_throw_non_call_exceptions
)
1867 rtx note
= find_reg_note (insn
, REG_EH_REGION
, NULL_RTX
);
1868 if (note
&& !insn_could_throw_p (insn
))
1869 remove_note (insn
, note
);
1874 /* Replace all references to register OLD_REGNO in *LOC with pseudo
1875 register NEW_REG. Try to simplify subreg of constant if SUBREG_P.
1876 Return true if any change was made. */
1878 lra_substitute_pseudo (rtx
*loc
, int old_regno
, rtx new_reg
, bool subreg_p
)
1881 bool result
= false;
1889 code
= GET_CODE (x
);
1890 if (code
== SUBREG
&& subreg_p
)
1892 rtx subst
, inner
= SUBREG_REG (x
);
1893 /* Transform subreg of constant while we still have inner mode
1894 of the subreg. The subreg internal should not be an insn
1896 if (REG_P (inner
) && (int) REGNO (inner
) == old_regno
1897 && CONSTANT_P (new_reg
)
1898 && (subst
= simplify_subreg (GET_MODE (x
), new_reg
, GET_MODE (inner
),
1899 SUBREG_BYTE (x
))) != NULL_RTX
)
1906 else if (code
== REG
&& (int) REGNO (x
) == old_regno
)
1908 machine_mode mode
= GET_MODE (x
);
1909 machine_mode inner_mode
= GET_MODE (new_reg
);
1911 if (mode
!= inner_mode
1912 && ! (CONST_INT_P (new_reg
) && SCALAR_INT_MODE_P (mode
)))
1914 if (!partial_subreg_p (mode
, inner_mode
)
1915 || ! SCALAR_INT_MODE_P (inner_mode
))
1916 new_reg
= gen_rtx_SUBREG (mode
, new_reg
, 0);
1918 new_reg
= gen_lowpart_SUBREG (mode
, new_reg
);
1924 /* Scan all the operand sub-expressions. */
1925 fmt
= GET_RTX_FORMAT (code
);
1926 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
1930 if (lra_substitute_pseudo (&XEXP (x
, i
), old_regno
,
1934 else if (fmt
[i
] == 'E')
1936 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
1937 if (lra_substitute_pseudo (&XVECEXP (x
, i
, j
), old_regno
,
1945 /* Call lra_substitute_pseudo within an insn. Try to simplify subreg
1946 of constant if SUBREG_P. This won't update the insn ptr, just the
1947 contents of the insn. */
1949 lra_substitute_pseudo_within_insn (rtx_insn
*insn
, int old_regno
,
1950 rtx new_reg
, bool subreg_p
)
1953 return lra_substitute_pseudo (&loc
, old_regno
, new_reg
, subreg_p
);
1958 /* This page contains code dealing with scratches (changing them onto
1959 pseudos and restoring them from the pseudos).
1961 We change scratches into pseudos at the beginning of LRA to
1962 simplify dealing with them (conflicts, hard register assignments).
1964 If the pseudo denoting scratch was spilled it means that we do need
1965 a hard register for it. Such pseudos are transformed back to
1966 scratches at the end of LRA. */
1968 /* Description of location of a former scratch operand. */
1971 rtx_insn
*insn
; /* Insn where the scratch was. */
1972 int nop
; /* Number of the operand which was a scratch. */
1975 typedef struct sloc
*sloc_t
;
1977 /* Locations of the former scratches. */
1978 static vec
<sloc_t
> scratches
;
1980 /* Bitmap of scratch regnos. */
1981 static bitmap_head scratch_bitmap
;
1983 /* Bitmap of scratch operands. */
1984 static bitmap_head scratch_operand_bitmap
;
1986 /* Return true if pseudo REGNO is made of SCRATCH. */
1988 lra_former_scratch_p (int regno
)
1990 return bitmap_bit_p (&scratch_bitmap
, regno
);
1993 /* Return true if the operand NOP of INSN is a former scratch. */
1995 lra_former_scratch_operand_p (rtx_insn
*insn
, int nop
)
1997 return bitmap_bit_p (&scratch_operand_bitmap
,
1998 INSN_UID (insn
) * MAX_RECOG_OPERANDS
+ nop
) != 0;
2001 /* Register operand NOP in INSN as a former scratch. It will be
2002 changed to scratch back, if it is necessary, at the LRA end. */
2004 lra_register_new_scratch_op (rtx_insn
*insn
, int nop
)
2006 lra_insn_recog_data_t id
= lra_get_insn_recog_data (insn
);
2007 rtx op
= *id
->operand_loc
[nop
];
2008 sloc_t loc
= XNEW (struct sloc
);
2009 lra_assert (REG_P (op
));
2012 scratches
.safe_push (loc
);
2013 bitmap_set_bit (&scratch_bitmap
, REGNO (op
));
2014 bitmap_set_bit (&scratch_operand_bitmap
,
2015 INSN_UID (insn
) * MAX_RECOG_OPERANDS
+ nop
);
2016 add_reg_note (insn
, REG_UNUSED
, op
);
2019 /* Change scratches onto pseudos and save their location. */
2021 remove_scratches (void)
2024 bool insn_changed_p
;
2028 lra_insn_recog_data_t id
;
2029 struct lra_static_insn_data
*static_id
;
2031 scratches
.create (get_max_uid ());
2032 bitmap_initialize (&scratch_bitmap
, ®_obstack
);
2033 bitmap_initialize (&scratch_operand_bitmap
, ®_obstack
);
2034 FOR_EACH_BB_FN (bb
, cfun
)
2035 FOR_BB_INSNS (bb
, insn
)
2038 id
= lra_get_insn_recog_data (insn
);
2039 static_id
= id
->insn_static_data
;
2040 insn_changed_p
= false;
2041 for (i
= 0; i
< static_id
->n_operands
; i
++)
2042 if (GET_CODE (*id
->operand_loc
[i
]) == SCRATCH
2043 && GET_MODE (*id
->operand_loc
[i
]) != VOIDmode
)
2045 insn_changed_p
= true;
2046 *id
->operand_loc
[i
] = reg
2047 = lra_create_new_reg (static_id
->operand
[i
].mode
,
2048 *id
->operand_loc
[i
], ALL_REGS
, NULL
);
2049 lra_register_new_scratch_op (insn
, i
);
2050 if (lra_dump_file
!= NULL
)
2051 fprintf (lra_dump_file
,
2052 "Removing SCRATCH in insn #%u (nop %d)\n",
2053 INSN_UID (insn
), i
);
2056 /* Because we might use DF right after caller-saves sub-pass
2057 we need to keep DF info up to date. */
2058 df_insn_rescan (insn
);
2062 /* Changes pseudos created by function remove_scratches onto scratches. */
2064 restore_scratches (void)
2069 rtx_insn
*last
= NULL
;
2070 lra_insn_recog_data_t id
= NULL
;
2072 for (i
= 0; scratches
.iterate (i
, &loc
); i
++)
2074 /* Ignore already deleted insns. */
2075 if (NOTE_P (loc
->insn
)
2076 && NOTE_KIND (loc
->insn
) == NOTE_INSN_DELETED
)
2078 if (last
!= loc
->insn
)
2081 id
= lra_get_insn_recog_data (last
);
2083 if (REG_P (*id
->operand_loc
[loc
->nop
])
2084 && ((regno
= REGNO (*id
->operand_loc
[loc
->nop
]))
2085 >= FIRST_PSEUDO_REGISTER
)
2086 && lra_get_regno_hard_regno (regno
) < 0)
2088 /* It should be only case when scratch register with chosen
2089 constraint 'X' did not get memory or hard register. */
2090 lra_assert (lra_former_scratch_p (regno
));
2091 *id
->operand_loc
[loc
->nop
]
2092 = gen_rtx_SCRATCH (GET_MODE (*id
->operand_loc
[loc
->nop
]));
2093 lra_update_dup (id
, loc
->nop
);
2094 if (lra_dump_file
!= NULL
)
2095 fprintf (lra_dump_file
, "Restoring SCRATCH in insn #%u(nop %d)\n",
2096 INSN_UID (loc
->insn
), loc
->nop
);
2099 for (i
= 0; scratches
.iterate (i
, &loc
); i
++)
2101 scratches
.release ();
2102 bitmap_clear (&scratch_bitmap
);
2103 bitmap_clear (&scratch_operand_bitmap
);
2108 /* Function checks RTL for correctness. If FINAL_P is true, it is
2109 done at the end of LRA and the check is more rigorous. */
2111 check_rtl (bool final_p
)
2116 lra_assert (! final_p
|| reload_completed
);
2117 FOR_EACH_BB_FN (bb
, cfun
)
2118 FOR_BB_INSNS (bb
, insn
)
2119 if (NONDEBUG_INSN_P (insn
)
2120 && GET_CODE (PATTERN (insn
)) != USE
2121 && GET_CODE (PATTERN (insn
)) != CLOBBER
2122 && GET_CODE (PATTERN (insn
)) != ASM_INPUT
)
2126 extract_constrain_insn (insn
);
2129 /* LRA code is based on assumption that all addresses can be
2130 correctly decomposed. LRA can generate reloads for
2131 decomposable addresses. The decomposition code checks the
2132 correctness of the addresses. So we don't need to check
2133 the addresses here. Don't call insn_invalid_p here, it can
2134 change the code at this stage. */
2135 if (recog_memoized (insn
) < 0 && asm_noperands (PATTERN (insn
)) < 0)
2136 fatal_insn_not_found (insn
);
2140 /* Determine if the current function has an exception receiver block
2141 that reaches the exit block via non-exceptional edges */
2143 has_nonexceptional_receiver (void)
2147 basic_block
*tos
, *worklist
, bb
;
2149 /* If we're not optimizing, then just err on the safe side. */
2153 /* First determine which blocks can reach exit via normal paths. */
2154 tos
= worklist
= XNEWVEC (basic_block
, n_basic_blocks_for_fn (cfun
) + 1);
2156 FOR_EACH_BB_FN (bb
, cfun
)
2157 bb
->flags
&= ~BB_REACHABLE
;
2159 /* Place the exit block on our worklist. */
2160 EXIT_BLOCK_PTR_FOR_FN (cfun
)->flags
|= BB_REACHABLE
;
2161 *tos
++ = EXIT_BLOCK_PTR_FOR_FN (cfun
);
2163 /* Iterate: find everything reachable from what we've already seen. */
2164 while (tos
!= worklist
)
2168 FOR_EACH_EDGE (e
, ei
, bb
->preds
)
2169 if (e
->flags
& EDGE_ABNORMAL
)
2176 basic_block src
= e
->src
;
2178 if (!(src
->flags
& BB_REACHABLE
))
2180 src
->flags
|= BB_REACHABLE
;
2186 /* No exceptional block reached exit unexceptionally. */
2191 /* Process recursively X of INSN and add REG_INC notes if necessary. */
2193 add_auto_inc_notes (rtx_insn
*insn
, rtx x
)
2195 enum rtx_code code
= GET_CODE (x
);
2199 if (code
== MEM
&& auto_inc_p (XEXP (x
, 0)))
2201 add_reg_note (insn
, REG_INC
, XEXP (XEXP (x
, 0), 0));
2205 /* Scan all X sub-expressions. */
2206 fmt
= GET_RTX_FORMAT (code
);
2207 for (i
= GET_RTX_LENGTH (code
) - 1; i
>= 0; i
--)
2210 add_auto_inc_notes (insn
, XEXP (x
, i
));
2211 else if (fmt
[i
] == 'E')
2212 for (j
= XVECLEN (x
, i
) - 1; j
>= 0; j
--)
2213 add_auto_inc_notes (insn
, XVECEXP (x
, i
, j
));
2218 /* Remove all REG_DEAD and REG_UNUSED notes and regenerate REG_INC.
2219 We change pseudos by hard registers without notification of DF and
2220 that can make the notes obsolete. DF-infrastructure does not deal
2221 with REG_INC notes -- so we should regenerate them here. */
2223 update_inc_notes (void)
2229 FOR_EACH_BB_FN (bb
, cfun
)
2230 FOR_BB_INSNS (bb
, insn
)
2231 if (NONDEBUG_INSN_P (insn
))
2233 pnote
= ®_NOTES (insn
);
2236 if (REG_NOTE_KIND (*pnote
) == REG_DEAD
2237 || REG_NOTE_KIND (*pnote
) == REG_UNUSED
2238 || REG_NOTE_KIND (*pnote
) == REG_INC
)
2239 *pnote
= XEXP (*pnote
, 1);
2241 pnote
= &XEXP (*pnote
, 1);
2245 add_auto_inc_notes (insn
, PATTERN (insn
));
2249 /* Set to 1 while in lra. */
2250 int lra_in_progress
;
2252 /* Start of pseudo regnos before the LRA. */
2253 int lra_new_regno_start
;
2255 /* Start of reload pseudo regnos before the new spill pass. */
2256 int lra_constraint_new_regno_start
;
2258 /* Avoid spilling pseudos with regno more than the following value if
2260 int lra_bad_spill_regno_start
;
2262 /* Inheritance pseudo regnos before the new spill pass. */
2263 bitmap_head lra_inheritance_pseudos
;
2265 /* Split regnos before the new spill pass. */
2266 bitmap_head lra_split_regs
;
2268 /* Reload pseudo regnos before the new assignment pass which still can
2269 be spilled after the assignment pass as memory is also accepted in
2270 insns for the reload pseudos. */
2271 bitmap_head lra_optional_reload_pseudos
;
2273 /* Pseudo regnos used for subreg reloads before the new assignment
2274 pass. Such pseudos still can be spilled after the assignment
2276 bitmap_head lra_subreg_reload_pseudos
;
2278 /* File used for output of LRA debug information. */
2279 FILE *lra_dump_file
;
2281 /* True if we should try spill into registers of different classes
2282 instead of memory. */
2283 bool lra_reg_spill_p
;
2285 /* Set up value LRA_REG_SPILL_P. */
2287 setup_reg_spill_flag (void)
2291 if (targetm
.spill_class
!= NULL
)
2292 for (cl
= 0; cl
< (int) LIM_REG_CLASSES
; cl
++)
2293 for (mode
= 0; mode
< MAX_MACHINE_MODE
; mode
++)
2294 if (targetm
.spill_class ((enum reg_class
) cl
,
2295 (machine_mode
) mode
) != NO_REGS
)
2297 lra_reg_spill_p
= true;
2300 lra_reg_spill_p
= false;
2303 /* True if the current function is too big to use regular algorithms
2304 in LRA. In other words, we should use simpler and faster algorithms
2305 in LRA. It also means we should not worry about generation code
2306 for caller saves. The value is set up in IRA. */
2309 /* Major LRA entry function. F is a file should be used to dump LRA
2315 bool live_p
, inserted_p
;
2319 timevar_push (TV_LRA
);
2321 /* Make sure that the last insn is a note. Some subsequent passes
2323 emit_note (NOTE_INSN_DELETED
);
2325 COPY_HARD_REG_SET (lra_no_alloc_regs
, ira_no_alloc_regs
);
2330 init_insn_recog_data ();
2332 /* Some quick check on RTL generated by previous passes. */
2336 lra_in_progress
= 1;
2338 lra_live_range_iter
= lra_coalesce_iter
= lra_constraint_iter
= 0;
2339 lra_assignment_iter
= lra_assignment_iter_after_spill
= 0;
2340 lra_inheritance_iter
= lra_undo_inheritance_iter
= 0;
2341 lra_rematerialization_iter
= 0;
2343 setup_reg_spill_flag ();
2345 /* Function remove_scratches can creates new pseudos for clobbers --
2346 so set up lra_constraint_new_regno_start before its call to
2347 permit changing reg classes for pseudos created by this
2349 lra_constraint_new_regno_start
= lra_new_regno_start
= max_reg_num ();
2350 lra_bad_spill_regno_start
= INT_MAX
;
2351 remove_scratches ();
2353 /* A function that has a non-local label that can reach the exit
2354 block via non-exceptional paths must save all call-saved
2356 if (cfun
->has_nonlocal_label
&& has_nonexceptional_receiver ())
2357 crtl
->saves_all_registers
= 1;
2359 if (crtl
->saves_all_registers
)
2360 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++)
2361 if (! call_used_regs
[i
] && ! fixed_regs
[i
] && ! LOCAL_REGNO (i
))
2362 df_set_regs_ever_live (i
, true);
2364 /* We don't DF from now and avoid its using because it is to
2365 expensive when a lot of RTL changes are made. */
2366 df_set_flags (DF_NO_INSN_RESCAN
);
2367 lra_constraint_insn_stack
.create (get_max_uid ());
2368 lra_constraint_insn_stack_bitmap
= sbitmap_alloc (get_max_uid ());
2369 bitmap_clear (lra_constraint_insn_stack_bitmap
);
2370 lra_live_ranges_init ();
2371 lra_constraints_init ();
2372 lra_curr_reload_num
= 0;
2373 push_insns (get_last_insn (), NULL
);
2374 /* It is needed for the 1st coalescing. */
2375 bitmap_initialize (&lra_inheritance_pseudos
, ®_obstack
);
2376 bitmap_initialize (&lra_split_regs
, ®_obstack
);
2377 bitmap_initialize (&lra_optional_reload_pseudos
, ®_obstack
);
2378 bitmap_initialize (&lra_subreg_reload_pseudos
, ®_obstack
);
2380 if (get_frame_size () != 0 && crtl
->stack_alignment_needed
)
2381 /* If we have a stack frame, we must align it now. The stack size
2382 may be a part of the offset computation for register
2384 assign_stack_local (BLKmode
, 0, crtl
->stack_alignment_needed
);
2390 bool reloads_p
= lra_constraints (lra_constraint_iter
== 0);
2391 /* Constraint transformations may result in that eliminable
2392 hard regs become uneliminable and pseudos which use them
2393 should be spilled. It is better to do it before pseudo
2396 For example, rs6000 can make
2397 RS6000_PIC_OFFSET_TABLE_REGNUM uneliminable if we started
2398 to use a constant pool. */
2399 lra_eliminate (false, false);
2400 /* We should try to assign hard registers to scratches even
2401 if there were no RTL transformations in lra_constraints.
2402 Also we should check IRA assignments on the first
2403 iteration as they can be wrong because of early clobbers
2404 operands which are ignored in IRA. */
2405 if (! reloads_p
&& lra_constraint_iter
> 1)
2407 /* Stack is not empty here only when there are changes
2408 during the elimination sub-pass. */
2409 if (bitmap_empty_p (lra_constraint_insn_stack_bitmap
))
2412 /* If there are no reloads but changing due
2413 elimination, restart the constraint sub-pass
2417 /* Do inheritance only for regular algorithms. */
2423 lra_clear_live_ranges ();
2424 /* As a side-effect of lra_create_live_ranges, we calculate
2425 actual_call_used_reg_set, which is needed during
2427 lra_create_live_ranges (true, true);
2433 lra_clear_live_ranges ();
2434 /* We need live ranges for lra_assign -- so build them. But
2435 don't remove dead insns or change global live info as we
2436 can undo inheritance transformations after inheritance
2437 pseudo assigning. */
2438 lra_create_live_ranges (true, false);
2440 /* If we don't spill non-reload and non-inheritance pseudos,
2441 there is no sense to run memory-memory move coalescing.
2442 If inheritance pseudos were spilled, the memory-memory
2443 moves involving them will be removed by pass undoing
2449 bool spill_p
= !lra_assign ();
2451 if (lra_undo_inheritance ())
2457 lra_create_live_ranges (true, true);
2460 if (lra_coalesce ())
2464 lra_clear_live_ranges ();
2467 /* Don't clear optional reloads bitmap until all constraints are
2468 satisfied as we need to differ them from regular reloads. */
2469 bitmap_clear (&lra_optional_reload_pseudos
);
2470 bitmap_clear (&lra_subreg_reload_pseudos
);
2471 bitmap_clear (&lra_inheritance_pseudos
);
2472 bitmap_clear (&lra_split_regs
);
2475 /* We need full live info for spilling pseudos into
2476 registers instead of memory. */
2477 lra_create_live_ranges (lra_reg_spill_p
, true);
2480 /* We should check necessity for spilling here as the above live
2481 range pass can remove spilled pseudos. */
2482 if (! lra_need_for_spills_p ())
2484 /* Now we know what pseudos should be spilled. Try to
2485 rematerialize them first. */
2488 /* We need full live info -- see the comment above. */
2489 lra_create_live_ranges (lra_reg_spill_p
, true);
2491 if (! lra_need_for_spills_p ())
2495 /* Assignment of stack slots changes elimination offsets for
2496 some eliminations. So update the offsets here. */
2497 lra_eliminate (false, false);
2498 lra_constraint_new_regno_start
= max_reg_num ();
2499 if (lra_bad_spill_regno_start
== INT_MAX
2500 && lra_inheritance_iter
> LRA_MAX_INHERITANCE_PASSES
2501 && lra_rematerialization_iter
> LRA_MAX_REMATERIALIZATION_PASSES
)
2502 /* After switching off inheritance and rematerialization
2503 passes, avoid spilling reload pseudos will be created to
2504 prevent LRA cycling in some complicated cases. */
2505 lra_bad_spill_regno_start
= lra_constraint_new_regno_start
;
2506 lra_assignment_iter_after_spill
= 0;
2508 restore_scratches ();
2509 lra_eliminate (true, false);
2510 lra_final_code_change ();
2511 lra_in_progress
= 0;
2513 lra_clear_live_ranges ();
2514 lra_live_ranges_finish ();
2515 lra_constraints_finish ();
2517 sbitmap_free (lra_constraint_insn_stack_bitmap
);
2518 lra_constraint_insn_stack
.release ();
2519 finish_insn_recog_data ();
2520 regstat_free_n_sets_and_refs ();
2522 reload_completed
= 1;
2523 update_inc_notes ();
2525 inserted_p
= fixup_abnormal_edges ();
2527 /* We've possibly turned single trapping insn into multiple ones. */
2528 if (cfun
->can_throw_non_call_exceptions
)
2530 auto_sbitmap
blocks (last_basic_block_for_fn (cfun
));
2531 bitmap_ones (blocks
);
2532 find_many_sub_basic_blocks (blocks
);
2536 commit_edge_insertions ();
2538 /* Replacing pseudos with their memory equivalents might have
2539 created shared rtx. Subsequent passes would get confused
2540 by this, so unshare everything here. */
2541 unshare_all_rtl_again (get_insns ());
2546 timevar_pop (TV_LRA
);
2549 /* Called once per compiler to initialize LRA data once. */
2551 lra_init_once (void)
2553 init_insn_code_data_once ();
2556 /* Called once per compiler to finish LRA data which are initialize
2559 lra_finish_once (void)
2561 finish_insn_code_data_once ();