| blob | d28a0ff07f052cb877fd3cfe7c0e10d20aae66b6 |
1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2013 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
70 #ifndef CHECK_STACK_LIMIT
71 #define CHECK_STACK_LIMIT (-1)
72 #endif
74 /* Return index of given mode in mult and division cost tables. */
75 #define MODE_INDEX(mode) \
76 ((mode) == QImode ? 0 \
77 : (mode) == HImode ? 1 \
78 : (mode) == SImode ? 2 \
79 : (mode) == DImode ? 3 \
80 : 4)
82 /* Processor costs (relative to an add) */
83 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
84 #define COSTS_N_BYTES(N) ((N) * 2)
86 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
88 const
111 in QImode, HImode and SImode.
112 Relative to reg-reg move (2). */
116 in SFmode, DFmode and XFmode */
118 in SFmode, DFmode and XFmode */
121 in SImode and DImode */
123 in SImode and DImode */
126 in SImode, DImode and TImode */
128 in SImode, DImode and TImode */
156 };
158 /* Processor costs (relative to an add) */
159 static const
182 in QImode, HImode and SImode.
183 Relative to reg-reg move (2). */
187 in SFmode, DFmode and XFmode */
189 in SFmode, DFmode and XFmode */
192 in SImode and DImode */
194 in SImode and DImode */
197 in SImode, DImode and TImode */
199 in SImode, DImode and TImode */
213 DUMMY_STRINGOP_ALGS},
215 DUMMY_STRINGOP_ALGS},
227 };
229 static const
252 in QImode, HImode and SImode.
253 Relative to reg-reg move (2). */
257 in SFmode, DFmode and XFmode */
259 in SFmode, DFmode and XFmode */
262 in SImode and DImode */
264 in SImode and DImode */
267 in SImode, DImode and TImode */
269 in SImode, DImode and TImode */
272 shared for code and data, so 4kB is
273 not really precise. */
285 DUMMY_STRINGOP_ALGS},
287 DUMMY_STRINGOP_ALGS},
299 };
301 static const
324 in QImode, HImode and SImode.
325 Relative to reg-reg move (2). */
329 in SFmode, DFmode and XFmode */
331 in SFmode, DFmode and XFmode */
334 in SImode and DImode */
336 in SImode and DImode */
339 in SImode, DImode and TImode */
341 in SImode, DImode and TImode */
355 DUMMY_STRINGOP_ALGS},
357 DUMMY_STRINGOP_ALGS},
369 };
371 static const
394 in QImode, HImode and SImode.
395 Relative to reg-reg move (2). */
399 in SFmode, DFmode and XFmode */
401 in SFmode, DFmode and XFmode */
404 in SImode and DImode */
406 in SImode and DImode */
409 in SImode, DImode and TImode */
411 in SImode, DImode and TImode */
424 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
425 (we ensure the alignment). For small blocks inline loop is still a
426 noticeable win, for bigger blocks either rep movsl or rep movsb is
427 way to go. Rep movsb has apparently more expensive startup time in CPU,
428 but after 4K the difference is down in the noise. */
432 DUMMY_STRINGOP_ALGS},
436 DUMMY_STRINGOP_ALGS},
448 };
450 static const
473 in QImode, HImode and SImode.
474 Relative to reg-reg move (2). */
478 in SFmode, DFmode and XFmode */
480 in SFmode, DFmode and XFmode */
484 in SImode and DImode */
486 in SImode and DImode */
489 in SImode, DImode and TImode */
491 in SImode, DImode and TImode */
505 DUMMY_STRINGOP_ALGS},
507 DUMMY_STRINGOP_ALGS},
519 };
521 static const
544 in QImode, HImode and SImode.
545 Relative to reg-reg move (2). */
549 in SFmode, DFmode and XFmode */
551 in SFmode, DFmode and XFmode */
554 in SImode and DImode */
556 in SImode and DImode */
559 in SImode, DImode and TImode */
561 in SImode, DImode and TImode */
565 have integrated l2 cache, but
566 optimizing for k6 is not important
567 enough to worry about that. */
578 DUMMY_STRINGOP_ALGS},
580 DUMMY_STRINGOP_ALGS},
592 };
594 static const
617 in QImode, HImode and SImode.
618 Relative to reg-reg move (2). */
622 in SFmode, DFmode and XFmode */
624 in SFmode, DFmode and XFmode */
627 in SImode and DImode */
629 in SImode and DImode */
632 in SImode, DImode and TImode */
634 in SImode, DImode and TImode */
647 /* For some reason, Athlon deals better with REP prefix (relative to loops)
648 compared to K8. Alignment becomes important after 8 bytes for memcpy and
649 128 bytes for memset. */
651 DUMMY_STRINGOP_ALGS},
653 DUMMY_STRINGOP_ALGS},
665 };
667 static const
690 in QImode, HImode and SImode.
691 Relative to reg-reg move (2). */
695 in SFmode, DFmode and XFmode */
697 in SFmode, DFmode and XFmode */
700 in SImode and DImode */
702 in SImode and DImode */
705 in SImode, DImode and TImode */
707 in SImode, DImode and TImode */
712 /* New AMD processors never drop prefetches; if they cannot be performed
713 immediately, they are queued. We set number of simultaneous prefetches
714 to a large constant to reflect this (it probably is not a good idea not
715 to limit number of prefetches at all, as their execution also takes some
716 time). */
725 /* K8 has optimized REP instruction for medium sized blocks, but for very
726 small blocks it is better to use loop. For large blocks, libcall can
727 do nontemporary accesses and beat inline considerably. */
747 };
771 in QImode, HImode and SImode.
772 Relative to reg-reg move (2). */
776 in SFmode, DFmode and XFmode */
778 in SFmode, DFmode and XFmode */
781 in SImode and DImode */
783 in SImode and DImode */
786 in SImode, DImode and TImode */
788 in SImode, DImode and TImode */
790 /* On K8:
791 MOVD reg64, xmmreg Double FSTORE 4
792 MOVD reg32, xmmreg Double FSTORE 4
793 On AMDFAM10:
794 MOVD reg64, xmmreg Double FADD 3
795 1/1 1/1
796 MOVD reg32, xmmreg Double FADD 3
797 1/1 1/1 */
801 /* New AMD processors never drop prefetches; if they cannot be performed
802 immediately, they are queued. We set number of simultaneous prefetches
803 to a large constant to reflect this (it probably is not a good idea not
804 to limit number of prefetches at all, as their execution also takes some
805 time). */
815 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
816 very small blocks it is better to use loop. For large blocks, libcall can
817 do nontemporary accesses and beat inline considerably. */
837 };
861 in QImode, HImode and SImode.
862 Relative to reg-reg move (2). */
866 in SFmode, DFmode and XFmode */
868 in SFmode, DFmode and XFmode */
871 in SImode and DImode */
873 in SImode and DImode */
876 in SImode, DImode and TImode */
878 in SImode, DImode and TImode */
880 /* On K8:
881 MOVD reg64, xmmreg Double FSTORE 4
882 MOVD reg32, xmmreg Double FSTORE 4
883 On AMDFAM10:
884 MOVD reg64, xmmreg Double FADD 3
885 1/1 1/1
886 MOVD reg32, xmmreg Double FADD 3
887 1/1 1/1 */
891 /* New AMD processors never drop prefetches; if they cannot be performed
892 immediately, they are queued. We set number of simultaneous prefetches
893 to a large constant to reflect this (it probably is not a good idea not
894 to limit number of prefetches at all, as their execution also takes some
895 time). */
905 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
906 very small blocks it is better to use loop. For large blocks, libcall
907 can do nontemporary accesses and beat inline considerably. */
927 };
951 in QImode, HImode and SImode.
952 Relative to reg-reg move (2). */
956 in SFmode, DFmode and XFmode */
958 in SFmode, DFmode and XFmode */
961 in SImode and DImode */
963 in SImode and DImode */
966 in SImode, DImode and TImode */
968 in SImode, DImode and TImode */
970 /* On K8:
971 MOVD reg64, xmmreg Double FSTORE 4
972 MOVD reg32, xmmreg Double FSTORE 4
973 On AMDFAM10:
974 MOVD reg64, xmmreg Double FADD 3
975 1/1 1/1
976 MOVD reg32, xmmreg Double FADD 3
977 1/1 1/1 */
981 /* New AMD processors never drop prefetches; if they cannot be performed
982 immediately, they are queued. We set number of simultaneous prefetches
983 to a large constant to reflect this (it probably is not a good idea not
984 to limit number of prefetches at all, as their execution also takes some
985 time). */
995 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
996 very small blocks it is better to use loop. For large blocks, libcall
997 can do nontemporary accesses and beat inline considerably. */
1017 };
1041 in QImode, HImode and SImode.
1042 Relative to reg-reg move (2). */
1046 in SFmode, DFmode and XFmode */
1048 in SFmode, DFmode and XFmode */
1051 in SImode and DImode */
1053 in SImode and DImode */
1056 in SImode, DImode and TImode */
1058 in SImode, DImode and TImode */
1063 /* New AMD processors never drop prefetches; if they cannot be performed
1064 immediately, they are queued. We set number of simultaneous prefetches
1065 to a large constant to reflect this (it probably is not a good idea not
1066 to limit number of prefetches at all, as their execution also takes some
1067 time). */
1077 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1078 very small blocks it is better to use loop. For large blocks, libcall
1079 can do nontemporary accesses and beat inline considerably. */
1099 };
1123 in QImode, HImode and SImode.
1124 Relative to reg-reg move (2). */
1128 in SFmode, DFmode and XFmode */
1130 in SFmode, DFmode and XFmode */
1133 in SImode and DImode */
1135 in SImode and DImode */
1138 in SImode, DImode and TImode */
1140 in SImode, DImode and TImode */
1142 /* On K8:
1143 MOVD reg64, xmmreg Double FSTORE 4
1144 MOVD reg32, xmmreg Double FSTORE 4
1145 On AMDFAM10:
1146 MOVD reg64, xmmreg Double FADD 3
1147 1/1 1/1
1148 MOVD reg32, xmmreg Double FADD 3
1149 1/1 1/1 */
1162 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1163 very small blocks it is better to use loop. For large blocks, libcall can
1164 do nontemporary accesses and beat inline considerably. */
1184 };
1208 in QImode, HImode and SImode.
1209 Relative to reg-reg move (2). */
1213 in SFmode, DFmode and XFmode */
1215 in SFmode, DFmode and XFmode */
1218 in SImode and DImode */
1220 in SImode and DImode */
1223 in SImode, DImode and TImode */
1225 in SImode, DImode and TImode */
1227 /* On K8:
1228 MOVD reg64, xmmreg Double FSTORE 4
1229 MOVD reg32, xmmreg Double FSTORE 4
1230 On AMDFAM10:
1231 MOVD reg64, xmmreg Double FADD 3
1232 1/1 1/1
1233 MOVD reg32, xmmreg Double FADD 3
1234 1/1 1/1 */
1266 };
1268 static const
1291 in QImode, HImode and SImode.
1292 Relative to reg-reg move (2). */
1296 in SFmode, DFmode and XFmode */
1298 in SFmode, DFmode and XFmode */
1301 in SImode and DImode */
1303 in SImode and DImode */
1306 in SImode, DImode and TImode */
1308 in SImode, DImode and TImode */
1322 DUMMY_STRINGOP_ALGS},
1325 DUMMY_STRINGOP_ALGS},
1337 };
1339 static const
1362 in QImode, HImode and SImode.
1363 Relative to reg-reg move (2). */
1367 in SFmode, DFmode and XFmode */
1369 in SFmode, DFmode and XFmode */
1372 in SImode and DImode */
1374 in SImode and DImode */
1377 in SImode, DImode and TImode */
1379 in SImode, DImode and TImode */
1410 };
1412 static const
1435 in QImode, HImode and SImode.
1436 Relative to reg-reg move (2). */
1440 in SFmode, DFmode and XFmode */
1442 in SFmode, DFmode and XFmode */
1445 in SImode and DImode */
1447 in SImode and DImode */
1450 in SImode, DImode and TImode */
1452 in SImode, DImode and TImode */
1483 };
1485 /* Generic64 should produce code tuned for Nocona and K8. */
1486 static const
1489 /* On all chips taken into consideration lea is 2 cycles and more. With
1490 this cost however our current implementation of synth_mult results in
1491 use of unnecessary temporary registers causing regression on several
1492 SPECfp benchmarks. */
1513 in QImode, HImode and SImode.
1514 Relative to reg-reg move (2). */
1518 in SFmode, DFmode and XFmode */
1520 in SFmode, DFmode and XFmode */
1523 in SImode and DImode */
1525 in SImode and DImode */
1528 in SImode, DImode and TImode */
1530 in SImode, DImode and TImode */
1536 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1537 value is increased to perhaps more appropriate value of 5. */
1562 };
1564 /* core_cost should produce code tuned for Core familly of CPUs. */
1565 static const
1568 /* On all chips taken into consideration lea is 2 cycles and more. With
1569 this cost however our current implementation of synth_mult results in
1570 use of unnecessary temporary registers causing regression on several
1571 SPECfp benchmarks. */
1592 in QImode, HImode and SImode.
1593 Relative to reg-reg move (2). */
1597 in SFmode, DFmode and XFmode */
1599 in SFmode, DFmode and XFmode */
1602 in SImode and DImode */
1604 in SImode and DImode */
1607 in SImode, DImode and TImode */
1609 in SImode, DImode and TImode */
1615 /* FIXME perhaps more appropriate value is 5. */
1643 };
1645 /* Generic32 should produce code tuned for PPro, Pentium4, Nocona,
1646 Athlon and K8. */
1647 static const
1670 in QImode, HImode and SImode.
1671 Relative to reg-reg move (2). */
1675 in SFmode, DFmode and XFmode */
1677 in SFmode, DFmode and XFmode */
1680 in SImode and DImode */
1682 in SImode and DImode */
1685 in SImode, DImode and TImode */
1687 in SImode, DImode and TImode */
1702 DUMMY_STRINGOP_ALGS},
1705 DUMMY_STRINGOP_ALGS},
1717 };
1719 /* Set by -mtune. */
1722 /* Set by -mtune or -Os. */
1725 /* Processor feature/optimization bitmasks. */
1726 #define m_386 (1<<PROCESSOR_I386)
1727 #define m_486 (1<<PROCESSOR_I486)
1728 #define m_PENT (1<<PROCESSOR_PENTIUM)
1729 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
1730 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
1731 #define m_NOCONA (1<<PROCESSOR_NOCONA)
1732 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
1733 #define m_CORE2 (1<<PROCESSOR_CORE2)
1734 #define m_COREI7 (1<<PROCESSOR_COREI7)
1735 #define m_HASWELL (1<<PROCESSOR_HASWELL)
1736 #define m_CORE_ALL (m_CORE2 | m_COREI7 | m_HASWELL)
1737 #define m_ATOM (1<<PROCESSOR_ATOM)
1739 #define m_GEODE (1<<PROCESSOR_GEODE)
1740 #define m_K6 (1<<PROCESSOR_K6)
1741 #define m_K6_GEODE (m_K6 | m_GEODE)
1742 #define m_K8 (1<<PROCESSOR_K8)
1743 #define m_ATHLON (1<<PROCESSOR_ATHLON)
1744 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
1745 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
1746 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
1747 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
1748 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
1749 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
1750 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
1751 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3)
1752 #define m_BTVER (m_BTVER1 | m_BTVER2)
1753 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
1755 #define m_GENERIC32 (1<<PROCESSOR_GENERIC32)
1756 #define m_GENERIC64 (1<<PROCESSOR_GENERIC64)
1758 /* Generic instruction choice should be common subset of supported CPUs
1759 (PPro/PENT4/NOCONA/CORE2/Athlon/K8). */
1760 #define m_GENERIC (m_GENERIC32 | m_GENERIC64)
1762 /* Feature tests against the various tunings. */
1765 /* Feature tests against the various tunings used to create ix86_tune_features
1766 based on the processor mask. */
1768 /* X86_TUNE_USE_LEAVE: Leave does not affect Nocona SPEC2000 results
1769 negatively, so enabling for Generic64 seems like good code size
1770 tradeoff. We can't enable it for 32bit generic because it does not
1771 work well with PPro base chips. */
1774 /* X86_TUNE_PUSH_MEMORY */
1777 /* X86_TUNE_ZERO_EXTEND_WITH_AND */
1780 /* X86_TUNE_UNROLL_STRLEN */
1783 /* X86_TUNE_BRANCH_PREDICTION_HINTS: Branch hints were put in P4 based
1784 on simulation result. But after P4 was made, no performance benefit
1785 was observed with branch hints. It also increases the code size.
1786 As a result, icc never generates branch hints. */
1789 /* X86_TUNE_DOUBLE_WITH_ADD */
1792 /* X86_TUNE_USE_SAHF */
1793 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_ATOM | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER | m_GENERIC,
1795 /* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
1796 partial dependencies. */
1799 /* X86_TUNE_PARTIAL_REG_STALL: We probably ought to watch for partial
1800 register stalls on Generic32 compilation setting as well. However
1801 in current implementation the partial register stalls are not eliminated
1802 very well - they can be introduced via subregs synthesized by combine
1803 and can happen in caller/callee saving sequences. Because this option
1804 pays back little on PPro based chips and is in conflict with partial reg
1805 dependencies used by Athlon/P4 based chips, it is better to leave it off
1806 for generic32 for now. */
1807 m_PPRO,
1809 /* X86_TUNE_PARTIAL_FLAG_REG_STALL */
1812 /* X86_TUNE_LCP_STALL: Avoid an expensive length-changing prefix stall
1813 * on 16-bit immediate moves into memory on Core2 and Corei7. */
1816 /* X86_TUNE_USE_HIMODE_FIOP */
1819 /* X86_TUNE_USE_SIMODE_FIOP */
1822 /* X86_TUNE_USE_MOV0 */
1823 m_K6,
1825 /* X86_TUNE_USE_CLTD */
1828 /* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
1829 m_PENT4,
1831 /* X86_TUNE_SPLIT_LONG_MOVES */
1832 m_PPRO,
1834 /* X86_TUNE_READ_MODIFY_WRITE */
1837 /* X86_TUNE_READ_MODIFY */
1840 /* X86_TUNE_PROMOTE_QIMODE */
1843 /* X86_TUNE_FAST_PREFIX */
1846 /* X86_TUNE_SINGLE_STRINGOP */
1849 /* X86_TUNE_QIMODE_MATH */
1852 /* X86_TUNE_HIMODE_MATH: On PPro this flag is meant to avoid partial
1853 register stalls. Just like X86_TUNE_PARTIAL_REG_STALL this option
1854 might be considered for Generic32 if our scheme for avoiding partial
1855 stalls was more effective. */
1858 /* X86_TUNE_PROMOTE_QI_REGS */
1861 /* X86_TUNE_PROMOTE_HI_REGS */
1862 m_PPRO,
1864 /* X86_TUNE_SINGLE_POP: Enable if single pop insn is preferred
1865 over esp addition. */
1868 /* X86_TUNE_DOUBLE_POP: Enable if double pop insn is preferred
1869 over esp addition. */
1870 m_PENT,
1872 /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
1873 over esp subtraction. */
1876 /* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
1877 over esp subtraction. */
1880 /* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
1881 for DFmode copies */
1884 /* X86_TUNE_PARTIAL_REG_DEPENDENCY */
1887 /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: In the Generic model we have a
1888 conflict here in between PPro/Pentium4 based chips that thread 128bit
1889 SSE registers as single units versus K8 based chips that divide SSE
1890 registers to two 64bit halves. This knob promotes all store destinations
1891 to be 128bit to allow register renaming on 128bit SSE units, but usually
1892 results in one extra microop on 64bit SSE units. Experimental results
1893 shows that disabling this option on P4 brings over 20% SPECfp regression,
1894 while enabling it on K8 brings roughly 2.4% regression that can be partly
1895 masked by careful scheduling of moves. */
1898 /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */
1901 /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */
1904 /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */
1905 m_BDVER ,
1907 /* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
1908 are resolved on SSE register parts instead of whole registers, so we may
1909 maintain just lower part of scalar values in proper format leaving the
1910 upper part undefined. */
1911 m_ATHLON_K8,
1913 /* X86_TUNE_SSE_TYPELESS_STORES */
1914 m_AMD_MULTIPLE,
1916 /* X86_TUNE_SSE_LOAD0_BY_PXOR */
1919 /* X86_TUNE_MEMORY_MISMATCH_STALL */
1922 /* X86_TUNE_PROLOGUE_USING_MOVE */
1925 /* X86_TUNE_EPILOGUE_USING_MOVE */
1928 /* X86_TUNE_SHIFT1 */
1931 /* X86_TUNE_USE_FFREEP */
1932 m_AMD_MULTIPLE,
1934 /* X86_TUNE_INTER_UNIT_MOVES_TO_VEC */
1937 /* X86_TUNE_INTER_UNIT_MOVES_FROM_VEC */
1940 /* X86_TUNE_INTER_UNIT_CONVERSIONS */
1943 /* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
1944 than 4 branch instructions in the 16 byte window. */
1947 /* X86_TUNE_SCHEDULE */
1950 /* X86_TUNE_USE_BT */
1953 /* X86_TUNE_USE_INCDEC */
1956 /* X86_TUNE_PAD_RETURNS */
1959 /* X86_TUNE_PAD_SHORT_FUNCTION: Pad short funtion. */
1960 m_ATOM,
1962 /* X86_TUNE_EXT_80387_CONSTANTS */
1965 /* X86_TUNE_AVOID_VECTOR_DECODE */
1968 /* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
1969 and SImode multiply, but 386 and 486 do HImode multiply faster. */
1972 /* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
1973 vector path on AMD machines. */
1976 /* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
1977 machines. */
1980 /* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
1981 than a MOV. */
1982 m_PENT,
1984 /* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
1985 but one byte longer. */
1986 m_PENT,
1988 /* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
1989 operand that cannot be represented using a modRM byte. The XOR
1990 replacement is long decoded, so this split helps here as well. */
1991 m_K6,
1993 /* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
1994 from FP to FP. */
1997 /* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
1998 from integer to FP. */
1999 m_AMDFAM10,
2001 /* X86_TUNE_FUSE_CMP_AND_BRANCH: Fuse a compare or test instruction
2002 with a subsequent conditional jump instruction into a single
2003 compare-and-branch uop. */
2004 m_BDVER,
2006 /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
2007 will impact LEA instruction selection. */
2008 m_ATOM,
2010 /* X86_TUNE_VECTORIZE_DOUBLE: Enable double precision vector
2011 instructions. */
2014 /* X86_SOFTARE_PREFETCHING_BENEFICIAL: Enable software prefetching
2015 at -O3. For the moment, the prefetching seems badly tuned for Intel
2016 chips. */
2019 /* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for
2020 the auto-vectorizer. */
2023 /* X86_TUNE_REASSOC_INT_TO_PARALLEL: Try to produce parallel computations
2024 during reassociation of integer computation. */
2025 m_ATOM,
2027 /* X86_TUNE_REASSOC_FP_TO_PARALLEL: Try to produce parallel computations
2028 during reassociation of fp computation. */
2031 /* X86_TUNE_GENERAL_REGS_SSE_SPILL: Try to spill general regs to SSE
2032 regs instead of memory. */
2033 m_CORE_ALL,
2035 /* X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE: Try to avoid memory operands for
2036 a conditional move. */
2037 m_ATOM
2038 };
2040 /* Feature tests against the various architecture variations. */
2043 /* Feature tests against the various architecture variations, used to create
2044 ix86_arch_features based on the processor mask. */
2046 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2049 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2052 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2055 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2058 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2060 };
2062 static const unsigned int x86_accumulate_outgoing_args
2065 static const unsigned int x86_arch_always_fancy_math_387
2068 static const unsigned int x86_avx256_split_unaligned_load
2071 static const unsigned int x86_avx256_split_unaligned_store
2074 /* In case the average insn count for single function invocation is
2075 lower than this constant, emit fast (but longer) prologue and
2076 epilogue code. */
2077 #define FAST_PROLOGUE_INSN_COUNT 20
2079 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2084 /* Array of the smallest class containing reg number REGNO, indexed by
2085 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2088 {
2089 /* ax, dx, cx, bx */
2091 /* si, di, bp, sp */
2093 /* FP registers */
2096 /* arg pointer */
2097 NON_Q_REGS,
2098 /* flags, fpsr, fpcr, frame */
2100 /* SSE registers */
2103 /* MMX registers */
2106 /* REX registers */
2109 /* SSE REX registers */
2112 };
2114 /* The "default" register map used in 32bit mode. */
2117 {
2125 };
2127 /* The "default" register map used in 64bit mode. */
2130 {
2138 };
2140 /* Define the register numbers to be used in Dwarf debugging information.
2141 The SVR4 reference port C compiler uses the following register numbers
2142 in its Dwarf output code:
2143 0 for %eax (gcc regno = 0)
2144 1 for %ecx (gcc regno = 2)
2145 2 for %edx (gcc regno = 1)
2146 3 for %ebx (gcc regno = 3)
2147 4 for %esp (gcc regno = 7)
2148 5 for %ebp (gcc regno = 6)
2149 6 for %esi (gcc regno = 4)
2150 7 for %edi (gcc regno = 5)
2151 The following three DWARF register numbers are never generated by
2152 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2153 believes these numbers have these meanings.
2154 8 for %eip (no gcc equivalent)
2155 9 for %eflags (gcc regno = 17)
2156 10 for %trapno (no gcc equivalent)
2157 It is not at all clear how we should number the FP stack registers
2158 for the x86 architecture. If the version of SDB on x86/svr4 were
2159 a bit less brain dead with respect to floating-point then we would
2160 have a precedent to follow with respect to DWARF register numbers
2161 for x86 FP registers, but the SDB on x86/svr4 is so completely
2162 broken with respect to FP registers that it is hardly worth thinking
2163 of it as something to strive for compatibility with.
2164 The version of x86/svr4 SDB I have at the moment does (partially)
2165 seem to believe that DWARF register number 11 is associated with
2166 the x86 register %st(0), but that's about all. Higher DWARF
2167 register numbers don't seem to be associated with anything in
2168 particular, and even for DWARF regno 11, SDB only seems to under-
2169 stand that it should say that a variable lives in %st(0) (when
2170 asked via an `=' command) if we said it was in DWARF regno 11,
2171 but SDB still prints garbage when asked for the value of the
2172 variable in question (via a `/' command).
2173 (Also note that the labels SDB prints for various FP stack regs
2174 when doing an `x' command are all wrong.)
2175 Note that these problems generally don't affect the native SVR4
2176 C compiler because it doesn't allow the use of -O with -g and
2177 because when it is *not* optimizing, it allocates a memory
2178 location for each floating-point variable, and the memory
2179 location is what gets described in the DWARF AT_location
2180 attribute for the variable in question.
2181 Regardless of the severe mental illness of the x86/svr4 SDB, we
2182 do something sensible here and we use the following DWARF
2183 register numbers. Note that these are all stack-top-relative
2184 numbers.
2185 11 for %st(0) (gcc regno = 8)
2186 12 for %st(1) (gcc regno = 9)
2187 13 for %st(2) (gcc regno = 10)
2188 14 for %st(3) (gcc regno = 11)
2189 15 for %st(4) (gcc regno = 12)
2190 16 for %st(5) (gcc regno = 13)
2191 17 for %st(6) (gcc regno = 14)
2192 18 for %st(7) (gcc regno = 15)
2193 */
2195 {
2203 };
2205 /* Define parameter passing and return registers. */
2208 {
2210 };
2213 {
2215 };
2218 {
2220 };
2222 /* Additional registers that are clobbered by SYSV calls. */
2225 {
2230 };
2232 /* Define the structure for the machine field in struct function. */
2237 rtx rtl;
2239 };
2241 /* Structure describing stack frame layout.
2242 Stack grows downward:
2244 [arguments]
2245 <- ARG_POINTER
2246 saved pc
2248 saved static chain if ix86_static_chain_on_stack
2250 saved frame pointer if frame_pointer_needed
2251 <- HARD_FRAME_POINTER
2252 [saved regs]
2253 <- regs_save_offset
2254 [padding0]
2256 [saved SSE regs]
2257 <- sse_regs_save_offset
2258 [padding1] |
2259 | <- FRAME_POINTER
2260 [va_arg registers] |
2261 |
2262 [frame] |
2263 |
2264 [padding2] | = to_allocate
2265 <- STACK_POINTER
2266 */
2267 struct ix86_frame
2268 {
2275 /* The offsets relative to ARG_POINTER. */
2276 HOST_WIDE_INT frame_pointer_offset;
2277 HOST_WIDE_INT hard_frame_pointer_offset;
2278 HOST_WIDE_INT stack_pointer_offset;
2279 HOST_WIDE_INT hfp_save_offset;
2280 HOST_WIDE_INT reg_save_offset;
2281 HOST_WIDE_INT sse_reg_save_offset;
2283 /* When save_regs_using_mov is set, emit prologue using
2284 move instead of push instructions. */
2286 };
2288 /* Which cpu are we scheduling for. */
2291 /* Which cpu are we optimizing for. */
2294 /* Which instruction set architecture to use. */
2297 /* True if processor has SSE prefetch instruction. */
2300 /* -mstackrealign option */
2317 /* Preferred alignment for stack boundary in bits. */
2320 /* Alignment for incoming stack boundary in bits specified at
2321 command line. */
2324 /* Default alignment for incoming stack boundary in bits. */
2327 /* Alignment for incoming stack boundary in bits. */
2330 /* Calling abi specific va_list type nodes. */
2334 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2338 /* Fence to use after loop using movnt. */
2339 tree x86_mfence;
2341 /* Register class used for passing given 64bit part of the argument.
2342 These represent classes as documented by the PS ABI, with the exception
2343 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2344 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2346 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2347 whenever possible (upper half does contain padding). */
2348 enum x86_64_reg_class
2349 {
2350 X86_64_NO_CLASS,
2351 X86_64_INTEGER_CLASS,
2352 X86_64_INTEGERSI_CLASS,
2353 X86_64_SSE_CLASS,
2354 X86_64_SSESF_CLASS,
2355 X86_64_SSEDF_CLASS,
2356 X86_64_SSEUP_CLASS,
2357 X86_64_X87_CLASS,
2358 X86_64_X87UP_CLASS,
2359 X86_64_COMPLEX_X87_CLASS,
2360 X86_64_MEMORY_CLASS
2361 };
2363 #define MAX_CLASSES 4
2365 /* Table of constants used by fldpi, fldln2, etc.... */
2369 \f
2374 const_tree);
2386 enum ix86_function_specific_strings
2387 {
2388 IX86_FUNCTION_SPECIFIC_ARCH,
2389 IX86_FUNCTION_SPECIFIC_TUNE,
2390 IX86_FUNCTION_SPECIFIC_MAX
2391 };
2409 \f
2410 #ifndef SUBTARGET32_DEFAULT_CPU
2412 #endif
2414 /* Whether -mtune= or -march= were specified */
2418 /* Vectorization library interface and handlers. */
2424 /* Processor target table, indexed by processor number */
2425 struct ptt
2426 {
2433 };
2436 {
2447 /* Core 2 */
2449 /* Core i7 */
2451 /* Core avx2 */
2462 };
2465 {
2494 "btver2"
2495 };
2496 \f
2497 static bool
2499 {
2501 }
2503 static unsigned int
2505 {
2508 /* vzeroupper instructions are inserted immediately after reload to
2509 account for possible spills from 256bit registers. The pass
2510 reuses mode switching infrastructure by re-running mode insertion
2511 pass, so disable entities that have already been processed. */
2517 /* Call optimize_mode_switching. */
2520 }
2523 {
2524 {
2525 RTL_PASS,
2540 }
2541 };
2543 /* Return true if a red-zone is in use. */
2547 {
2549 }
2550 \f
2551 /* Return a string that documents the current -m options. The caller is
2552 responsible for freeing the string. */
2558 {
2559 struct ix86_target_opts
2560 {
2563 };
2565 /* This table is ordered so that options like -msse4.2 that imply
2566 preceding options while match those first. */
2568 {
2604 };
2606 /* Flag options. */
2608 {
2636 };
2653 /* Add -march= option. */
2655 {
2658 }
2660 /* Add -mtune= option. */
2662 {
2665 }
2667 /* Add -m32/-m64/-mx32. */
2669 {
2672 else
2674 isa &= ~ (OPTION_MASK_ISA_64BIT
2675 | OPTION_MASK_ABI_64
2677 }
2678 else
2682 /* Pick out the options in isa options. */
2684 {
2686 {
2689 }
2690 }
2693 {
2696 isa);
2697 }
2699 /* Add flag options. */
2701 {
2703 {
2706 }
2707 }
2710 {
2713 }
2715 /* Add -fpmath= option. */
2717 {
2720 {
2735 }
2736 }
2738 /* Any options? */
2744 /* Size the string. */
2748 {
2753 }
2755 /* Build the string. */
2760 {
2767 {
2769 line_len++;
2772 {
2776 }
2777 }
2781 {
2785 }
2786 }
2792 }
2794 /* Return true, if profiling code should be emitted before
2795 prologue. Otherwise it returns false.
2796 Note: For x86 with "hotfix" it is sorried. */
2797 static bool
2799 {
2801 }
2803 /* Function that is callable from the debugger to print the current
2804 options. */
2805 void
2807 {
2813 {
2816 }
2817 else
2821 }
2822 \f
2823 /* Override various settings based on options. If MAIN_ARGS_P, the
2824 options are from the command line, otherwise they are from
2825 attributes. */
2827 static void
2829 {
2837 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
2838 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
2839 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
2840 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
2841 #define PTA_AES (HOST_WIDE_INT_1 << 4)
2842 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
2843 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
2844 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
2845 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
2846 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
2847 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
2848 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
2849 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
2850 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
2851 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
2852 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
2853 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
2854 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
2855 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
2856 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
2857 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
2858 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
2859 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
2860 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
2861 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
2862 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
2863 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
2864 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
2865 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
2866 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
2867 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
2868 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
2869 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
2870 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
2871 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
2872 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
2873 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
2874 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
2875 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
2876 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
2878 /* if this reaches 64, need to widen struct pta flags below */
2880 static struct pta
2881 {
2886 }
2888 {
3018 PTA_64BIT
3020 };
3022 /* -mrecip options. */
3023 static struct
3024 {
3027 }
3029 {
3036 };
3040 /* Set up prefix/suffix so the error messages refer to either the command
3041 line argument, or the attribute(target). */
3043 {
3047 }
3048 else
3049 {
3053 }
3055 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3056 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3059 #ifdef TARGET_BI_ARCH
3060 else
3061 {
3062 #if TARGET_BI_ARCH == 1
3063 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3064 is on and OPTION_MASK_ABI_X32 is off. We turn off
3065 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3066 -mx32. */
3069 #else
3070 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3071 on and OPTION_MASK_ABI_64 is off. We turn off
3072 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3073 -m64. */
3076 #endif
3077 }
3078 #endif
3081 {
3082 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3083 OPTION_MASK_ABI_64 for TARGET_X32. */
3086 }
3088 {
3089 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3090 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3093 }
3095 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3096 SUBTARGET_OVERRIDE_OPTIONS;
3097 #endif
3099 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3100 SUBSUBTARGET_OVERRIDE_OPTIONS;
3101 #endif
3103 /* -fPIC is the default for x86_64. */
3107 /* Need to check -mtune=generic first. */
3109 {
3112 /* As special support for cross compilers we read -mtune=native
3113 as -mtune=generic. With native compilers we won't see the
3114 -mtune=native, as it was changed by the driver. */
3116 {
3119 else
3121 }
3122 /* If this call is for setting the option attribute, allow the
3123 generic32/generic64 that was previously set. */
3127 ;
3135 }
3136 else
3137 {
3141 {
3144 }
3146 /* ix86_tune_string is set to ix86_arch_string or defaulted. We
3147 need to use a sensible tune option. */
3151 {
3154 else
3156 }
3157 }
3160 {
3161 /* rep; movq isn't available in 32-bit code. */
3164 }
3168 else
3172 {
3178 }
3179 else
3186 {
3188 {
3232 {
3235 }
3243 }
3244 }
3245 else
3246 {
3247 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3248 use of rip-relative addressing. This eliminates fixups that
3249 would otherwise be needed if this object is to be placed in a
3250 DLL, and is essentially just as efficient as direct addressing. */
3255 else
3257 }
3259 {
3262 }
3269 {
3272 /* Default cpu tuning to the architecture. */
3397 }
3412 {
3416 {
3418 {
3420 {
3428 }
3429 else
3432 }
3433 }
3434 else
3435 {
3436 /* Adjust tuning when compiling for 32-bit ABI. */
3438 {
3446 }
3447 }
3448 /* Intel CPUs have always interpreted SSE prefetch instructions as
3449 NOPs; so, we can enable SSE prefetch instructions even when
3450 -mtune (rather than -march) points us to a processor that has them.
3451 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3452 higher processors. */
3457 }
3467 #ifndef USE_IX86_FRAME_POINTER
3468 #define USE_IX86_FRAME_POINTER 0
3469 #endif
3471 #ifndef USE_X86_64_FRAME_POINTER
3472 #define USE_X86_64_FRAME_POINTER 0
3473 #endif
3475 /* Set the default values for switches whose default depends on TARGET_64BIT
3476 in case they weren't overwritten by command line options. */
3478 {
3485 }
3486 else
3487 {
3494 }
3499 else
3502 /* Arrange to set up i386_stack_locals for all functions. */
3505 /* Validate -mregparm= value. */
3507 {
3511 {
3515 }
3516 }
3520 /* Default align_* from the processor table. */
3522 {
3525 }
3527 {
3530 }
3532 {
3534 }
3536 /* Provide default for -mbranch-cost= value. */
3541 {
3544 /* Enable by default the SSE and MMX builtins. Do allow the user to
3545 explicitly disable any of these. In particular, disabling SSE and
3546 MMX for kernel code is extremely useful. */
3548 ix86_isa_flags
3554 }
3555 else
3556 {
3560 ix86_isa_flags
3563 /* i386 ABI does not specify red zone. It still makes sense to use it
3564 when programmer takes care to stack from being destroyed. */
3567 }
3569 /* Keep nonleaf frame pointers. */
3575 /* If we're doing fast math, we don't care about comparison order
3576 wrt NaNs. This lets us use a shorter comparison sequence. */
3580 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3581 since the insns won't need emulation. */
3585 /* Likewise, if the target doesn't have a 387, or we've specified
3586 software floating point, don't use 387 inline intrinsics. */
3590 /* Turn on MMX builtins for -msse. */
3594 /* Enable SSE prefetch. */
3598 /* Turn on popcnt instruction for -msse4.2 or -mabm. */
3602 /* Turn on lzcnt instruction for -mabm. */
3606 /* Validate -mpreferred-stack-boundary= value or default it to
3607 PREFERRED_STACK_BOUNDARY_DEFAULT. */
3610 {
3616 {
3620 else
3623 }
3624 else
3625 ix86_preferred_stack_boundary
3627 }
3629 /* Set the default value for -mstackrealign. */
3635 /* Validate -mincoming-stack-boundary= value or default it to
3636 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
3639 {
3644 else
3645 {
3646 ix86_user_incoming_stack_boundary
3648 ix86_incoming_stack_boundary
3650 }
3651 }
3653 /* Accept -msseregparm only if at least SSE support is enabled. */
3659 {
3661 {
3663 {
3666 }
3668 {
3671 }
3672 }
3673 }
3674 else
3677 /* If the i387 is disabled, then do not return values in it. */
3681 /* Use external vectorized library in vectorizing intrinsics. */
3684 {
3695 }
3703 /* ??? Unwind info is not correct around the CFG unless either a frame
3704 pointer is present or M_A_O_A is set. Fixing this requires rewriting
3705 unwind info generation to be aware of the CFG and propagating states
3706 around edges. */
3709 && flag_omit_frame_pointer
3711 {
3717 }
3719 /* If stack probes are required, the space used for large function
3720 arguments on the stack must also be probed, so enable
3721 -maccumulate-outgoing-args so this happens in the prologue. */
3724 {
3729 }
3731 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
3732 {
3738 }
3740 /* When scheduling description is not available, disable scheduler pass
3741 so it won't slow down the compilation and make x87 code slower. */
3762 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
3764 && HAVE_prefetch
3769 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
3770 can be optimized to ap = __builtin_next_arg (0). */
3775 {
3778 {
3781 ix86_gen_tls_local_dynamic_base_64
3783 }
3784 else
3785 {
3788 ix86_gen_tls_local_dynamic_base_64
3790 }
3791 }
3792 else
3793 {
3796 }
3799 {
3808 }
3809 else
3810 {
3819 }
3821 #ifdef USE_IX86_CLD
3822 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
3825 #endif
3828 {
3833 }
3835 {
3839 }
3841 {
3842 #if defined(PROFILE_BEFORE_PROLOGUE)
3844 #else
3846 #endif
3847 }
3850 {
3851 /* When not optimize for size, enable vzeroupper optimization for
3852 TARGET_AVX with -fexpensive-optimizations and split 32-byte
3853 AVX unaligned load/store. */
3855 {
3865 /* Enable 128-bit AVX instruction generation
3866 for the auto-vectorizer. */
3870 }
3871 }
3872 else
3873 {
3874 /* Disable vzeroupper pass if TARGET_AVX is disabled. */
3876 }
3879 {
3886 {
3889 {
3891 q++;
3892 }
3893 else
3898 else
3899 {
3902 {
3905 }
3908 {
3912 }
3913 }
3918 else
3920 }
3921 }
3928 /* Default long double to 64-bit for Bionic. */
3933 /* Save the initial options in case the user does function specific
3934 options. */
3936 target_option_default_node = target_option_current_node
3939 /* Handle stack protector */
3942 }
3944 /* Implement the TARGET_OPTION_OVERRIDE hook. */
3946 static void
3948 {
3949 static struct register_pass_info insert_vzeroupper_info
3952 };
3957 /* This needs to be done at start up. It's convenient to do it here. */
3959 }
3961 /* Update register usage after having seen the compiler flags. */
3963 static void
3965 {
3969 /* The PIC register, if it exists, is fixed. */
3974 /* For 32-bit targets, squash the REX registers. */
3976 {
3981 }
3983 /* See the definition of CALL_USED_REGISTERS in i386.h. */
3991 {
3992 /* Set/reset conditionally defined registers from
3993 CALL_USED_REGISTERS initializer. */
3997 /* Calculate registers of CLOBBERED_REGS register set
3998 as call used registers from GENERAL_REGS register set. */
4002 }
4004 /* If MMX is disabled, squash the registers. */
4010 /* If SSE is disabled, squash the registers. */
4016 /* If the FPU is disabled, squash the registers. */
4021 }
4023 \f
4024 /* Save the current options */
4026 static void
4028 {
4039 /* The fields are char but the variables are not; make sure the
4040 values fit in the fields. */
4045 }
4047 /* Restore the current options */
4049 static void
4051 {
4067 /* Recreate the arch feature tests if the arch changed */
4069 {
4074 }
4076 /* Recreate the tune optimization tests */
4078 {
4083 }
4084 }
4086 /* Print the current options */
4088 static void
4091 {
4113 {
4116 }
4117 }
4119 \f
4120 /* Inner function to process the attribute((target(...))), take an argument and
4121 set the current options from the argument. If we have a list, recursively go
4122 over the list. */
4124 static bool
4127 {
4131 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4132 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4133 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4134 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4135 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4137 enum ix86_opt_type
4138 {
4139 ix86_opt_unknown,
4140 ix86_opt_yes,
4141 ix86_opt_no,
4142 ix86_opt_str,
4143 ix86_opt_enum,
4144 ix86_opt_isa
4145 };
4147 static const struct
4148 {
4155 /* isa options */
4192 /* enum options */
4195 /* string options */
4199 /* flag options */
4201 OPT_mcld,
4202 MASK_CLD),
4205 OPT_mfancy_math_387,
4206 MASK_NO_FANCY_MATH_387),
4209 OPT_mieee_fp,
4210 MASK_IEEE_FP),
4213 OPT_minline_all_stringops,
4214 MASK_INLINE_ALL_STRINGOPS),
4217 OPT_minline_stringops_dynamically,
4218 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4221 OPT_mno_align_stringops,
4222 MASK_NO_ALIGN_STRINGOPS),
4225 OPT_mrecip,
4226 MASK_RECIP),
4228 };
4230 /* If this is a list, recurse to get the options. */
4232 {
4242 }
4245 {
4248 }
4250 /* Handle multiple arguments separated by commas. */
4254 {
4268 {
4272 }
4273 else
4274 {
4277 }
4279 /* Recognize no-xxx. */
4281 {
4285 }
4286 else
4289 /* Find the option. */
4293 {
4301 {
4306 }
4307 }
4309 /* Process the option. */
4311 {
4314 }
4317 {
4323 }
4326 {
4332 else
4334 }
4337 {
4339 {
4342 }
4343 else
4345 }
4348 {
4356 global_dc);
4357 else
4358 {
4361 }
4362 }
4364 else
4366 }
4369 }
4371 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4373 tree
4375 {
4390 /* Process each of the options on the chain. */
4395 /* If the changed options are different from the default, rerun
4396 ix86_option_override_internal, and then save the options away.
4397 The string options are are attribute options, and will be undone
4398 when we copy the save structure. */
4404 {
4405 /* If we are using the default tune= or arch=, undo the string assigned,
4406 and use the default. */
4417 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
4421 {
4424 }
4426 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
4429 /* Add any builtin functions with the new isa if any. */
4432 /* Save the current options unless we are validating options for
4433 #pragma. */
4440 /* Free up memory allocated to hold the strings */
4443 }
4446 }
4448 /* Hook to validate attribute((target("string"))). */
4450 static bool
4453 tree args,
4455 {
4459 /* attribute((target("default"))) does nothing, beyond
4460 affecting multi-versioning. */
4471 /* If the function changed the optimization levels as well as setting target
4472 options, start with the optimizations specified. */
4477 /* The target attributes may also change some optimization flags, so update
4478 the optimization options if necessary. */
4487 {
4492 }
4501 }
4503 \f
4504 /* Hook to determine if one function can safely inline another. */
4506 static bool
4508 {
4513 /* If callee has no option attributes, then it is ok to inline. */
4517 /* If caller has no option attributes, but callee does then it is not ok to
4518 inline. */
4522 else
4523 {
4527 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
4528 can inline a SSE2 function but a SSE2 function can't inline a SSE4
4529 function. */
4534 /* See if we have the same non-isa options. */
4538 /* See if arch, tune, etc. are the same. */
4551 else
4553 }
4556 }
4558 \f
4559 /* Remember the last target of ix86_set_current_function. */
4562 /* Establish appropriate back-end context for processing the function
4563 FNDECL. The argument might be NULL to indicate processing at top
4564 level, outside of any function scope. */
4565 static void
4567 {
4568 /* Only change the context if the function changes. This hook is called
4569 several times in the course of compiling a function, and we don't want to
4570 slow things down too much or call target_reinit when it isn't safe. */
4572 {
4573 tree old_tree = (ix86_previous_fndecl
4577 tree new_tree = (fndecl
4583 ;
4586 {
4590 }
4593 {
4599 }
4600 }
4601 }
4603 \f
4604 /* Return true if this goes in large data/bss. */
4606 static bool
4608 {
4612 /* Functions are never large data. */
4617 {
4623 }
4624 else
4625 {
4628 /* If this is an incomplete type with size 0, then we can't put it
4629 in data because it might be too big when completed. */
4632 }
4635 }
4637 /* Switch to the appropriate section for output of DECL.
4638 DECL is either a `VAR_DECL' node or a constant of some sort.
4639 RELOC indicates whether forming the initial value of DECL requires
4640 link-time relocations. */
4643 ATTRIBUTE_UNUSED;
4648 {
4651 {
4655 {
4689 /* We don't split these for medium model. Place them into
4690 default sections and hope for best. */
4692 }
4694 {
4695 /* We might get called with string constants, but get_named_section
4696 doesn't like them as they are not DECLs. Also, we need to set
4697 flags in that case. */
4701 }
4702 }
4704 }
4706 /* Build up a unique section name, expressed as a
4707 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
4708 RELOC indicates whether the initial value of EXP requires
4709 link-time relocations. */
4711 static void ATTRIBUTE_UNUSED
4713 {
4716 {
4718 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
4722 {
4746 /* We don't split these for medium model. Place them into
4747 default sections and hope for best. */
4749 }
4751 {
4758 /* If we're using one_only, then there needs to be a .gnu.linkonce
4759 prefix to the section name. */
4766 }
4767 }
4769 }
4771 #ifdef COMMON_ASM_OP
4772 /* This says how to output assembler code to declare an
4773 uninitialized external linkage data object.
4775 For medium model x86-64 we need to use .largecomm opcode for
4776 large objects. */
4777 void
4781 {
4785 else
4790 }
4791 #endif
4793 /* Utility function for targets to use in implementing
4794 ASM_OUTPUT_ALIGNED_BSS. */
4796 void
4800 {
4804 else
4807 #ifdef ASM_DECLARE_OBJECT_NAME
4810 #else
4811 /* Standard thing is just output label for the object. */
4815 }
4816 \f
4817 /* Decide whether we must probe the stack before any space allocation
4818 on this target. It's essentially TARGET_STACK_PROBE except when
4819 -fstack-check causes the stack to be already probed differently. */
4821 bool
4823 {
4824 /* Do not probe the stack twice if static stack checking is enabled. */
4829 }
4830 \f
4831 /* Decide whether we can make a sibling call to a function. DECL is the
4832 declaration of the function being targeted by the call and EXP is the
4833 CALL_EXPR representing the call. */
4835 static bool
4837 {
4841 /* If we are generating position-independent code, we cannot sibcall
4842 optimize any indirect call, or a direct call to a global function,
4843 as the PLT requires %ebx be live. (Darwin does not have a PLT.) */
4845 && !TARGET_64BIT
4846 && flag_pic
4850 /* If we need to align the outgoing stack, then sibcalling would
4851 unalign the stack, which may break the called function. */
4857 {
4860 }
4861 else
4862 {
4863 /* We're looking at the CALL_EXPR, we need the type of the function. */
4868 }
4870 /* Check that the return value locations are the same. Like
4871 if we are returning floats on the 80387 register stack, we cannot
4872 make a sibcall from a function that doesn't return a float to a
4873 function that does or, conversely, from a function that does return
4874 a float to a function that doesn't; the necessary stack adjustment
4875 would not be executed. This is also the place we notice
4876 differences in the return value ABI. Note that it is ok for one
4877 of the functions to have void return type as long as the return
4878 value of the other is passed in a register. */
4883 {
4886 }
4888 ;
4893 {
4894 /* The SYSV ABI has more call-clobbered registers;
4895 disallow sibcalls from MS to SYSV. */
4899 }
4900 else
4901 {
4902 /* If this call is indirect, we'll need to be able to use a
4903 call-clobbered register for the address of the target function.
4904 Make sure that all such registers are not used for passing
4905 parameters. Note that DLLIMPORT functions are indirect. */
4908 {
4910 {
4911 /* ??? Need to count the actual number of registers to be used,
4912 not the possible number of registers. Fix later. */
4914 }
4915 }
4916 }
4918 /* Otherwise okay. That also includes certain types of indirect calls. */
4920 }
4922 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
4923 and "sseregparm" calling convention attributes;
4924 arguments as in struct attribute_spec.handler. */
4926 static tree
4928 tree args,
4931 {
4936 {
4938 name);
4941 }
4943 /* Can combine regparm with all attributes but fastcall, and thiscall. */
4945 {
4946 tree cst;
4949 {
4951 }
4954 {
4956 }
4960 {
4963 name);
4965 }
4967 {
4971 }
4974 }
4977 {
4978 /* Do not warn when emulating the MS ABI. */
4983 name);
4986 }
4988 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
4990 {
4992 {
4994 }
4996 {
4998 }
5000 {
5002 }
5004 {
5006 }
5007 }
5009 /* Can combine stdcall with fastcall (redundant), regparm and
5010 sseregparm. */
5012 {
5014 {
5016 }
5018 {
5020 }
5022 {
5024 }
5025 }
5027 /* Can combine cdecl with regparm and sseregparm. */
5029 {
5031 {
5033 }
5035 {
5037 }
5039 {
5041 }
5042 }
5044 {
5047 name);
5049 {
5051 }
5053 {
5055 }
5057 {
5059 }
5060 }
5062 /* Can combine sseregparm with all attributes. */
5065 }
5067 /* The transactional memory builtins are implicitly regparm or fastcall
5068 depending on the ABI. Override the generic do-nothing attribute that
5069 these builtins were declared with, and replace it with one of the two
5070 attributes that we expect elsewhere. */
5072 static tree
5074 tree args ATTRIBUTE_UNUSED,
5077 {
5078 tree alt;
5080 /* In no case do we want to add the placeholder attribute. */
5083 /* The 64-bit ABI is unchanged for transactional memory. */
5087 /* ??? Is there a better way to validate 32-bit windows? We have
5088 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5091 else
5092 {
5095 }
5099 }
5101 /* This function determines from TYPE the calling-convention. */
5103 unsigned int
5105 {
5108 tree attrs;
5115 {
5125 /* Regparam isn't allowed for thiscall and fastcall. */
5127 {
5132 }
5136 }
5143 || is_stdarg
5149 }
5151 /* Return 0 if the attributes for two types are incompatible, 1 if they
5152 are compatible, and 2 if they are nearly compatible (which causes a
5153 warning to be generated). */
5155 static int
5157 {
5173 }
5174 \f
5175 /* Return the regparm value for a function with the indicated TYPE and DECL.
5176 DECL may be NULL when calling function indirectly
5177 or considering a libcall. */
5179 static int
5181 {
5182 tree attr;
5193 {
5196 {
5199 }
5200 }
5206 /* Use register calling convention for local functions when possible. */
5209 && optimize
5211 {
5212 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5215 {
5218 /* Make sure no regparm register is taken by a
5219 fixed register variable. */
5224 /* We don't want to use regparm(3) for nested functions as
5225 these use a static chain pointer in the third argument. */
5229 /* In 32-bit mode save a register for the split stack. */
5233 /* Each fixed register usage increases register pressure,
5234 so less registers should be used for argument passing.
5235 This functionality can be overriden by an explicit
5236 regparm value. */
5239 globals++;
5241 local_regparm
5246 }
5247 }
5250 }
5252 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5253 DFmode (2) arguments in SSE registers for a function with the
5254 indicated TYPE and DECL. DECL may be NULL when calling function
5255 indirectly or considering a libcall. Otherwise return 0. */
5257 static int
5259 {
5262 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5263 by the sseregparm attribute. */
5266 {
5268 {
5270 {
5274 else
5277 }
5279 }
5282 }
5284 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5285 (and DFmode for SSE2) arguments in SSE registers. */
5288 {
5289 /* FIXME: remove this CONST_CAST when cgraph.[ch] is constified. */
5293 }
5296 }
5298 /* Return true if EAX is live at the start of the function. Used by
5299 ix86_expand_prologue to determine if we need special help before
5300 calling allocate_stack_worker. */
5302 static bool
5304 {
5305 /* Cheat. Don't bother working forward from ix86_function_regparm
5306 to the function type to whether an actual argument is located in
5307 eax. Instead just look at cfg info, which is still close enough
5308 to correct at this point. This gives false positives for broken
5309 functions that might use uninitialized data that happens to be
5310 allocated in eax, but who cares? */
5312 }
5314 static bool
5316 {
5317 tree attr;
5320 {
5326 /* For 32-bit MS-ABI the default is to keep aggregate
5327 return pointer. */
5330 }
5332 }
5334 /* Value is the number of bytes of arguments automatically
5335 popped when returning from a subroutine call.
5336 FUNDECL is the declaration node of the function (as a tree),
5337 FUNTYPE is the data type of the function (as a tree),
5338 or for a library call it is an identifier node for the subroutine name.
5339 SIZE is the number of bytes of arguments passed on the stack.
5341 On the 80386, the RTD insn may be used to pop them if the number
5342 of args is fixed, but if the number is variable then the caller
5343 must pop them all. RTD can't be used for library calls now
5344 because the library is compiled with the Unix compiler.
5345 Use of RTD is a selectable option, since it is incompatible with
5346 standard Unix calling sequences. If the option is not selected,
5347 the caller must always pop the args.
5349 The attribute stdcall is equivalent to RTD on a per module basis. */
5351 static int
5353 {
5356 /* None of the 64-bit ABIs pop arguments. */
5367 /* Lose any fake structure return argument if it is passed on the stack. */
5370 {
5374 }
5377 }
5379 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
5381 static bool
5383 {
5384 /* Check operand constraints in case hard registers were propagated
5385 into insn pattern. This check prevents combine pass from
5386 generating insn patterns with invalid hard register operands.
5387 These invalid insns can eventually confuse reload to error out
5388 with a spill failure. See also PRs 46829 and 46843. */
5390 {
5397 {
5405 /* A unary operator may be accepted by the predicate, but it
5406 is irrelevant for matching constraints. */
5411 {
5419 }
5426 /* Operand has no constraints, anything is OK. */
5430 {
5433 && operands_match_p
5437 {
5440 }
5441 }
5445 }
5446 }
5449 }
5450 \f
5451 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
5453 static unsigned HOST_WIDE_INT
5455 {
5459 }
5460 \f
5461 /* Argument support functions. */
5463 /* Return true when register may be used to pass function parameters. */
5464 bool
5466 {
5471 {
5475 else
5481 }
5484 {
5487 }
5488 else
5489 {
5493 }
5495 /* TODO: The function should depend on current function ABI but
5496 builtins.c would need updating then. Therefore we use the
5497 default ABI. */
5499 /* RAX is used as hidden argument to va_arg functions. */
5505 else
5512 }
5514 /* Return if we do not know how to pass TYPE solely in registers. */
5516 static bool
5518 {
5522 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
5523 The layout_type routine is crafty and tries to trick us into passing
5524 currently unsupported vector types on the stack by using TImode. */
5527 }
5529 /* It returns the size, in bytes, of the area reserved for arguments passed
5530 in registers for the function represented by fndecl dependent to the used
5531 abi format. */
5532 int
5534 {
5538 else
5543 }
5545 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
5546 call abi used. */
5547 enum calling_abi
5549 {
5551 {
5554 {
5557 }
5561 }
5563 }
5565 static bool
5567 {
5569 {
5573 else
5575 }
5577 }
5579 static enum calling_abi
5581 {
5585 }
5587 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
5588 call abi used. */
5589 enum calling_abi
5591 {
5595 }
5597 /* Write the extra assembler code needed to declare a function properly. */
5599 void
5601 tree decl)
5602 {
5606 {
5612 }
5614 #ifdef SUBTARGET_ASM_UNWIND_INIT
5616 #endif
5620 /* Output magic byte marker, if hot-patch attribute is set. */
5622 {
5624 {
5625 /* leaq [%rsp + 0], %rsp */
5628 }
5629 else
5630 {
5631 /* movl.s %edi, %edi
5632 push %ebp
5633 movl.s %esp, %ebp */
5636 }
5637 }
5638 }
5640 /* regclass.c */
5643 /* Implementation of call abi switching target hook. Specific to FNDECL
5644 the specific call register sets are set. See also
5645 ix86_conditional_register_usage for more details. */
5646 void
5648 {
5651 else
5653 }
5655 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
5656 expensive re-initialization of init_regs each time we switch function context
5657 since this is needed only during RTL expansion. */
5658 static void
5660 {
5664 }
5666 /* Initialize a variable CUM of type CUMULATIVE_ARGS
5667 for a call to a function whose data type is FNTYPE.
5668 For a library call, FNTYPE is 0. */
5670 void
5674 tree fndecl,
5676 {
5682 {
5685 }
5686 else
5687 {
5690 }
5694 /* Set up the number of registers to use for passing arguments. */
5701 {
5703 ? X86_64_REGPARM_MAX
5705 }
5707 {
5710 {
5712 ? X86_64_SSE_REGPARM_MAX
5714 }
5715 }
5722 /* Because type might mismatch in between caller and callee, we need to
5723 use actual type of function for local calls.
5724 FIXME: cgraph_analyze can be told to actually record if function uses
5725 va_start so for local functions maybe_vaarg can be made aggressive
5726 helping K&R code.
5727 FIXME: once typesytem is fixed, we won't need this code anymore. */
5735 {
5736 /* If there are variable arguments, then we won't pass anything
5737 in registers in 32-bit mode. */
5739 {
5747 }
5749 /* Use ecx and edx registers if function has fastcall attribute,
5750 else look for regparm information. */
5752 {
5755 {
5758 }
5760 {
5763 }
5764 else
5766 }
5768 /* Set up the number of SSE registers used for passing SFmode
5769 and DFmode arguments. Warn for mismatching ABI. */
5771 }
5772 }
5774 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
5775 But in the case of vector types, it is some vector mode.
5777 When we have only some of our vector isa extensions enabled, then there
5778 are some modes for which vector_mode_supported_p is false. For these
5779 modes, the generic vector support in gcc will choose some non-vector mode
5780 in order to implement the type. By computing the natural mode, we'll
5781 select the proper ABI location for the operand and not depend on whatever
5782 the middle-end decides to do with these vector types.
5784 The midde-end can't deal with the vector types > 16 bytes. In this
5785 case, we return the original mode and warn ABI change if CUM isn't
5786 NULL. */
5788 static enum machine_mode
5790 {
5794 {
5797 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
5799 {
5804 else
5807 /* Get the mode which has this inner mode and number of units. */
5811 {
5813 {
5817 && !warnedavx
5819 {
5823 }
5825 }
5827 {
5831 && !warnedsse
5833 {
5837 }
5839 }
5840 else
5842 }
5845 }
5846 }
5849 }
5851 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
5852 this may not agree with the mode that the type system has chosen for the
5853 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
5854 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
5856 static rtx
5859 {
5860 rtx tmp;
5864 else
5865 {
5869 }
5872 }
5874 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
5875 of this code is to classify each 8bytes of incoming argument by the register
5876 class and assign registers accordingly. */
5878 /* Return the union class of CLASS1 and CLASS2.
5879 See the x86-64 PS ABI for details. */
5881 static enum x86_64_reg_class
5883 {
5884 /* Rule #1: If both classes are equal, this is the resulting class. */
5888 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
5889 the other class. */
5895 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
5899 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
5907 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
5908 MEMORY is used. */
5917 /* Rule #6: Otherwise class SSE is used. */
5919 }
5921 /* Classify the argument of type TYPE and mode MODE.
5922 CLASSES will be filled by the register class used to pass each word
5923 of the operand. The number of words is returned. In case the parameter
5924 should be passed in memory, 0 is returned. As a special case for zero
5925 sized containers, classes[0] will be NO_CLASS and 1 is returned.
5927 BIT_OFFSET is used internally for handling records and specifies offset
5928 of the offset in bits modulo 256 to avoid overflow cases.
5930 See the x86-64 PS ABI for details.
5931 */
5933 static int
5936 {
5937 HOST_WIDE_INT bytes =
5939 int words
5942 /* Variable sized entities are always passed/returned in memory. */
5951 {
5953 tree field;
5956 /* On x86-64 we pass structures larger than 32 bytes on the stack. */
5963 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
5964 signalize memory class, so handle it as special case. */
5966 {
5969 }
5971 /* Classify each field of record and merge classes. */
5973 {
5975 /* And now merge the fields of structure. */
5977 {
5979 {
5985 /* Bitfields are always classified as integer. Handle them
5986 early, since later code would consider them to be
5987 misaligned integers. */
5989 {
5998 }
5999 else
6000 {
6005 /* Flexible array member is ignored. */
6012 {
6016 {
6019 "the ABI of passing struct with"
6020 " a flexible array member has"
6022 }
6024 }
6026 subclasses,
6036 }
6037 }
6038 }
6042 /* Arrays are handled as small records. */
6043 {
6050 /* The partial classes are now full classes. */
6061 }
6064 /* Unions are similar to RECORD_TYPE but offset is always 0.
6065 */
6067 {
6069 {
6077 bit_offset);
6082 }
6083 }
6088 }
6091 {
6092 /* When size > 16 bytes, if the first one isn't
6093 X86_64_SSE_CLASS or any other ones aren't
6094 X86_64_SSEUP_CLASS, everything should be passed in
6095 memory. */
6102 }
6104 /* Final merger cleanup. */
6106 {
6107 /* If one class is MEMORY, everything should be passed in
6108 memory. */
6112 /* The X86_64_SSEUP_CLASS should be always preceded by
6113 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6117 {
6118 /* The first one should never be X86_64_SSEUP_CLASS. */
6121 }
6123 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6124 everything should be passed in memory. */
6127 {
6130 /* The first one should never be X86_64_X87UP_CLASS. */
6133 {
6136 "the ABI of passing union with long double"
6138 }
6140 }
6141 }
6143 }
6145 /* Compute alignment needed. We align all types to natural boundaries with
6146 exception of XFmode that is aligned to 64bits. */
6148 {
6157 /* Misaligned fields are always returned in memory. */
6160 }
6162 /* for V1xx modes, just use the base mode */
6167 /* Classification of atomic types. */
6169 {
6185 {
6189 {
6192 }
6194 {
6197 }
6199 {
6203 }
6205 {
6208 }
6209 else
6211 }
6218 /* OImode shouldn't be used directly. */
6225 else
6243 else
6244 {
6248 {
6251 "the ABI of passing structure with complex float"
6253 }
6256 }
6265 /* This modes is larger than 16 bytes. */
6308 else
6312 }
6313 }
6315 /* Examine the argument and return set number of register required in each
6316 class. Return 0 iff parameter should be passed in memory. */
6317 static int
6320 {
6330 {
6352 }
6354 }
6356 /* Construct container for the argument used by GCC interface. See
6357 FUNCTION_ARG for the detailed description. */
6359 static rtx
6363 {
6364 /* The following variables hold the static issued_error state. */
6378 rtx ret;
6389 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
6390 some less clueful developer tries to use floating-point anyway. */
6392 {
6394 {
6396 {
6399 }
6400 }
6402 {
6405 }
6407 }
6409 /* Likewise, error if the ABI requires us to return values in the
6410 x87 registers and the user specified -mno-80387. */
6416 {
6418 {
6421 }
6423 }
6425 /* First construct simple cases. Avoid SCmode, since we want to use
6426 single register to pass this type. */
6429 {
6444 /* Zero sized array, struct or class. */
6448 }
6475 /* Otherwise figure out the entries of the PARALLEL. */
6477 {
6481 {
6486 /* Merge TImodes on aligned occasions here too. */
6488 tmpmode
6492 else
6494 /* We've requested 24 bytes we
6495 don't have mode for. Use DImode. */
6502 intreg++;
6510 sse_regno++;
6518 sse_regno++;
6523 {
6529 {
6531 i++;
6532 }
6533 else
6546 }
6552 sse_regno++;
6556 }
6557 }
6559 /* Empty aligned struct, union or class. */
6567 }
6569 /* Update the data in CUM to advance over an argument of mode MODE
6570 and data type TYPE. (TYPE is null for libcalls where that information
6571 may not be available.) */
6573 static void
6576 HOST_WIDE_INT words)
6577 {
6579 {
6586 /* FALLTHRU */
6597 {
6600 }
6604 /* OImode shouldn't be used directly. */
6613 /* FALLTHRU */
6629 {
6634 {
6637 }
6638 }
6648 {
6653 {
6656 }
6657 }
6659 }
6660 }
6662 static void
6665 {
6668 /* Unnamed 256bit vector mode parameters are passed on stack. */
6674 {
6679 }
6680 else
6681 {
6685 }
6686 }
6688 static void
6690 HOST_WIDE_INT words)
6691 {
6692 /* Otherwise, this should be passed indirect. */
6697 {
6700 }
6701 }
6703 /* Update the data in CUM to advance over an argument of mode MODE and
6704 data type TYPE. (TYPE is null for libcalls where that information
6705 may not be available.) */
6707 static void
6710 {
6716 else
6727 else
6729 }
6731 /* Define where to put the arguments to a function.
6732 Value is zero to push the argument on the stack,
6733 or a hard register in which to store the argument.
6735 MODE is the argument's machine mode.
6736 TYPE is the data type of the argument (as a tree).
6737 This is null for libcalls where that information may
6738 not be available.
6739 CUM is a variable of type CUMULATIVE_ARGS which gives info about
6740 the preceding args and about the function being called.
6741 NAMED is nonzero if this argument is a named parameter
6742 (otherwise it is an extra parameter matching an ellipsis). */
6744 static rtx
6748 {
6751 /* Avoid the AL settings for the Unix64 ABI. */
6756 {
6763 /* FALLTHRU */
6769 {
6772 /* Fastcall allocates the first two DWORD (SImode) or
6773 smaller arguments to ECX and EDX if it isn't an
6774 aggregate type . */
6776 {
6782 /* ECX not EAX is the first allocated register. */
6785 }
6787 }
6796 /* FALLTHRU */
6798 /* In 32bit, we pass TImode in xmm registers. */
6806 {
6808 {
6812 }
6816 }
6820 /* OImode shouldn't be used directly. */
6830 {
6834 }
6844 {
6846 {
6850 }
6854 }
6856 }
6859 }
6861 static rtx
6864 {
6865 /* Handle a hidden AL argument containing number of registers
6866 for varargs x86-64 functions. */
6870 ? X86_64_SSE_REGPARM_MAX
6875 {
6885 /* Unnamed 256bit vector mode parameters are passed on stack. */
6889 }
6895 }
6897 static rtx
6900 HOST_WIDE_INT bytes)
6901 {
6904 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
6905 We use value of -2 to specify that current function call is MSABI. */
6909 /* If we've run out of registers, it goes on the stack. */
6915 /* Only floating point modes are passed in anything but integer regs. */
6917 {
6920 else
6921 {
6924 /* Unnamed floating parameters are passed in both the
6925 SSE and integer registers. */
6931 }
6932 }
6933 /* Handle aggregated types passed in register. */
6935 {
6940 }
6943 }
6945 /* Return where to put the arguments to a function.
6946 Return zero to push the argument on the stack, or a hard register in which to store the argument.
6948 MODE is the argument's machine mode. TYPE is the data type of the
6949 argument. It is null for libcalls where that information may not be
6950 available. CUM gives information about the preceding args and about
6951 the function being called. NAMED is nonzero if this argument is a
6952 named parameter (otherwise it is an extra parameter matching an
6953 ellipsis). */
6955 static rtx
6958 {
6962 rtx arg;
6966 else
6970 /* To simplify the code below, represent vector types with a vector mode
6971 even if MMX/SSE are not active. */
6979 else
6983 }
6985 /* A C expression that indicates when an argument must be passed by
6986 reference. If nonzero for an argument, a copy of that argument is
6987 made in memory and a pointer to the argument is passed instead of
6988 the argument itself. The pointer is passed in whatever way is
6989 appropriate for passing a pointer to that type. */
6991 static bool
6995 {
6998 /* See Windows x64 Software Convention. */
7000 {
7003 {
7004 /* Arrays are passed by reference. */
7009 {
7010 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
7011 are passed by reference. */
7013 }
7014 }
7016 /* __m128 is passed by reference. */
7022 }
7023 }
7028 }
7030 /* Return true when TYPE should be 128bit aligned for 32bit argument
7031 passing ABI. XXX: This function is obsolete and is only used for
7032 checking psABI compatibility with previous versions of GCC. */
7034 static bool
7036 {
7048 {
7049 /* Walk the aggregates recursively. */
7051 {
7055 {
7056 tree field;
7058 /* Walk all the structure fields. */
7060 {
7064 }
7066 }
7069 /* Just for use if some languages passes arrays by value. */
7076 }
7077 }
7079 }
7081 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
7082 XXX: This function is obsolete and is only used for checking psABI
7083 compatibility with previous versions of GCC. */
7085 static unsigned int
7088 {
7089 /* In 32bit, only _Decimal128 and __float128 are aligned to their
7090 natural boundaries. */
7092 {
7093 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
7094 make an exception for SSE modes since these require 128bit
7095 alignment.
7097 The handling here differs from field_alignment. ICC aligns MMX
7098 arguments to 4 byte boundaries, while structure fields are aligned
7099 to 8 byte boundaries. */
7101 {
7104 }
7105 else
7106 {
7109 }
7110 }
7114 }
7116 /* Return true when TYPE should be 128bit aligned for 32bit argument
7117 passing ABI. */
7119 static bool
7121 {
7131 {
7132 /* Walk the aggregates recursively. */
7134 {
7138 {
7139 tree field;
7141 /* Walk all the structure fields. */
7143 field;
7145 {
7149 }
7151 }
7154 /* Just for use if some languages passes arrays by value. */
7161 }
7162 }
7163 else
7167 }
7169 /* Gives the alignment boundary, in bits, of an argument with the
7170 specified mode and type. */
7172 static unsigned int
7174 {
7177 {
7178 /* Since the main variant type is used for call, we convert it to
7179 the main variant type. */
7182 }
7183 else
7187 else
7188 {
7193 {
7194 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
7196 {
7199 }
7205 }
7208 && !warned
7210 saved_align))
7211 {
7214 "The ABI for passing parameters with %d-byte"
7217 }
7218 }
7221 }
7223 /* Return true if N is a possible register number of function value. */
7225 static bool
7227 {
7229 {
7234 /* TODO: The function should depend on current function ABI but
7235 builtins.c would need updating then. Therefore we use the
7236 default ABI. */
7248 }
7251 }
7253 /* Define how to find the value returned by a function.
7254 VALTYPE is the data type of the value (as a tree).
7255 If the precise function being called is known, FUNC is its FUNCTION_DECL;
7256 otherwise, FUNC is 0. */
7258 static rtx
7261 {
7264 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
7265 we normally prevent this case when mmx is not available. However
7266 some ABIs may require the result to be returned like DImode. */
7270 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
7271 we prevent this case when sse is not available. However some ABIs
7272 may require the result to be returned like integer TImode. */
7277 /* 32-byte vector modes in %ymm0. */
7281 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
7284 else
7285 /* Most things go in %eax. */
7288 /* Override FP return register with %xmm0 for local functions when
7289 SSE math is enabled or for functions with sseregparm attribute. */
7291 {
7296 }
7298 /* OImode shouldn't be used directly. */
7302 }
7304 static rtx
7306 const_tree valtype)
7307 {
7308 rtx ret;
7310 /* Handle libcalls, which don't provide a type node. */
7312 {
7316 {
7335 }
7338 }
7340 {
7341 /* Pointers are always returned in word_mode. */
7343 }
7349 /* For zero sized structures, construct_container returns NULL, but we
7350 need to keep rest of compiler happy by returning meaningful value. */
7355 }
7357 static rtx
7359 const_tree valtype)
7360 {
7364 {
7366 {
7385 }
7386 }
7388 }
7390 static rtx
7393 {
7405 else
7407 }
7409 static rtx
7412 {
7418 }
7420 /* Pointer function arguments and return values are promoted to
7421 word_mode. */
7423 static enum machine_mode
7427 {
7429 {
7432 }
7434 for_return);
7435 }
7437 /* Return true if a structure, union or array with MODE containing FIELD
7438 should be accessed using BLKmode. */
7440 static bool
7442 {
7443 /* Union with XFmode must be in BLKmode. */
7447 }
7449 rtx
7451 {
7453 }
7455 /* Return true iff type is returned in memory. */
7457 static bool ATTRIBUTE_UNUSED
7459 {
7460 HOST_WIDE_INT size;
7471 {
7472 /* User-created vectors small enough to fit in EAX. */
7476 /* MMX/3dNow values are returned in MM0,
7477 except when it doesn't exits or the ABI prescribes otherwise. */
7481 /* SSE values are returned in XMM0, except when it doesn't exist. */
7485 /* AVX values are returned in YMM0, except when it doesn't exist. */
7488 }
7496 /* OImode shouldn't be used directly. */
7500 }
7502 static bool ATTRIBUTE_UNUSED
7504 {
7507 }
7509 static bool ATTRIBUTE_UNUSED
7511 {
7514 /* __m128 is returned in xmm0. */
7521 /* Otherwise, the size must be exactly in [1248]. */
7523 }
7525 static bool
7527 {
7528 #ifdef SUBTARGET_RETURN_IN_MEMORY
7530 #else
7534 {
7537 else
7539 }
7540 else
7542 #endif
7543 }
7545 /* When returning SSE vector types, we have a choice of either
7546 (1) being abi incompatible with a -march switch, or
7547 (2) generating an error.
7548 Given no good solution, I think the safest thing is one warning.
7549 The user won't be able to use -Werror, but....
7551 Choose the STRUCT_VALUE_RTX hook because that's (at present) only
7552 called in response to actually generating a caller or callee that
7553 uses such a type. As opposed to TARGET_RETURN_IN_MEMORY, which is called
7554 via aggregate_value_p for general type probing from tree-ssa. */
7556 static rtx
7558 {
7562 {
7563 /* Look at the return type of the function, not the function type. */
7567 {
7570 {
7574 }
7575 }
7578 {
7580 {
7584 }
7585 }
7586 }
7589 }
7591 \f
7592 /* Create the va_list data type. */
7594 /* Returns the calling convention specific va_list date type.
7595 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
7597 static tree
7599 {
7602 /* For i386 we use plain pointer to argument area. */
7612 unsigned_type_node);
7615 unsigned_type_node);
7618 ptr_type_node);
7621 ptr_type_node);
7640 /* The correct type is an array type of one element. */
7642 }
7644 /* Setup the builtin va_list data type and for 64-bit the additional
7645 calling convention specific va_list data types. */
7647 static tree
7649 {
7652 /* Initialize abi specific va_list builtin types. */
7654 {
7655 tree t;
7657 {
7662 }
7663 else
7664 {
7669 }
7671 {
7676 }
7677 else
7678 {
7683 }
7684 }
7687 }
7689 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
7691 static void
7693 {
7695 alias_set_type set;
7698 /* GPR size of varargs save area. */
7701 else
7704 /* FPR size of varargs save area. We don't need it if we don't pass
7705 anything in SSE registers. */
7708 else
7722 {
7730 }
7733 {
7737 /* Now emit code to save SSE registers. The AX parameter contains number
7738 of SSE parameter registers used to call this function, though all we
7739 actually check here is the zero/non-zero status. */
7744 label));
7746 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
7747 we used movdqa (i.e. TImode) instead? Perhaps even better would
7748 be if we could determine the real mode of the data, via a hook
7749 into pass_stdarg. Ignore all that for now. */
7759 {
7768 }
7771 }
7772 }
7774 static void
7776 {
7780 /* Reset to zero, as there might be a sysv vaarg used
7781 before. */
7786 {
7797 }
7798 }
7800 static void
7804 {
7806 CUMULATIVE_ARGS next_cum;
7807 tree fntype;
7809 /* This argument doesn't appear to be used anymore. Which is good,
7810 because the old code here didn't suppress rtl generation. */
7818 /* For varargs, we do not want to skip the dummy va_dcl argument.
7819 For stdargs, we do want to skip the last named argument. */
7827 else
7829 }
7831 /* Checks if TYPE is of kind va_list char *. */
7833 static bool
7835 {
7836 tree canonic;
7838 /* For 32-bit it is always true. */
7844 }
7846 /* Implement va_start. */
7848 static void
7850 {
7854 tree type;
7855 rtx ovf_rtx;
7859 {
7862 /* When we are splitting the stack, we can't refer to the stack
7863 arguments using internal_arg_pointer, because they may be on
7864 the old stack. The split stack prologue will arrange to
7865 leave a pointer to the old stack arguments in a scratch
7866 register, which we here copy to a pseudo-register. The split
7867 stack prologue can't set the pseudo-register directly because
7868 it (the prologue) runs before any registers have been saved. */
7872 {
7886 }
7887 }
7889 /* Only 64bit target needs something special. */
7891 {
7894 else
7895 {
7904 }
7906 }
7915 /* The following should be folded into the MEM_REF offset. */
7925 /* Count number of gp and fp argument registers used. */
7931 {
7937 }
7940 {
7946 }
7948 /* Find the overflow area. */
7952 else
7962 {
7963 /* Find the register save area.
7964 Prologue of the function save it right above stack frame. */
7972 }
7973 }
7975 /* Implement va_arg. */
7977 static tree
7980 {
7987 rtx container;
7989 tree ptrtype;
7993 /* Only 64bit target needs something special. */
8017 {
8024 /* Unnamed 256bit vector mode parameters are passed on stack. */
8026 {
8029 }
8037 }
8039 /* Pull the value out of the saved registers. */
8044 {
8058 /* In case we are passing structure, verify that it is consecutive block
8059 on the register save area. If not we need to do moves. */
8061 {
8062 /* Verify that all registers are strictly consecutive */
8064 {
8068 {
8073 }
8074 }
8075 else
8076 {
8080 {
8085 }
8086 }
8087 }
8089 {
8092 }
8093 else
8094 {
8097 }
8099 /* First ensure that we fit completely in registers. */
8101 {
8108 }
8110 {
8118 }
8120 /* Compute index to start of area used for integer regs. */
8122 {
8123 /* int_addr = gpr + sav; */
8126 }
8128 {
8129 /* sse_addr = fpr + sav; */
8132 }
8134 {
8138 /* addr = &temp; */
8143 {
8147 tree piece_type;
8148 tree addr_type;
8149 tree daddr_type;
8158 {
8163 }
8167 else
8174 {
8177 }
8178 else
8179 {
8182 }
8189 {
8194 }
8195 else
8196 {
8197 tree copy
8202 }
8204 }
8205 }
8208 {
8212 }
8215 {
8219 }
8224 }
8226 /* ... otherwise out of the overflow area. */
8228 /* When we align parameter on stack for caller, if the parameter
8229 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
8230 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
8231 here with caller. */
8236 /* Care for on-stack alignment if needed. */
8239 else
8240 {
8245 }
8262 }
8263 \f
8264 /* Return true if OPNUM's MEM should be matched
8265 in movabs* patterns. */
8267 bool
8269 {
8281 }
8282 \f
8283 /* Initialize the table of extra 80387 mathematical constants. */
8285 static void
8287 {
8289 {
8295 };
8299 {
8301 /* Ensure each constant is rounded to XFmode precision. */
8304 }
8307 }
8309 /* Return non-zero if the constant is something that
8310 can be loaded with a special instruction. */
8312 int
8314 {
8317 REAL_VALUE_TYPE r;
8329 /* For XFmode constants, try to find a special 80387 instruction when
8330 optimizing for size or on those CPUs that benefit from them. */
8333 {
8342 }
8344 /* Load of the constant -0.0 or -1.0 will be split as
8345 fldz;fchs or fld1;fchs sequence. */
8352 }
8354 /* Return the opcode of the special instruction to be used to load
8355 the constant X. */
8359 {
8361 {
8381 }
8382 }
8384 /* Return the CONST_DOUBLE representing the 80387 constant that is
8385 loaded by the specified special instruction. The argument IDX
8386 matches the return value from standard_80387_constant_p. */
8388 rtx
8390 {
8397 {
8408 }
8411 XFmode);
8412 }
8414 /* Return 1 if X is all 0s and 2 if x is all 1s
8415 in supported SSE/AVX vector mode. */
8417 int
8419 {
8426 {
8441 }
8444 }
8446 /* Return the opcode of the special instruction to be used to load
8447 the constant X. */
8451 {
8453 {
8456 {
8473 }
8478 else
8483 }
8485 }
8487 /* Returns true if OP contains a symbol reference */
8489 bool
8491 {
8500 {
8502 {
8508 }
8512 }
8515 }
8517 /* Return true if it is appropriate to emit `ret' instructions in the
8518 body of a function. Do this only if the epilogue is simple, needing a
8519 couple of insns. Prior to reloading, we can't tell how many registers
8520 must be saved, so return false then. Return false if there is no frame
8521 marker to de-allocate. */
8523 bool
8525 {
8531 /* Don't allow more than 32k pop, since that's all we can do
8532 with one instruction. */
8539 }
8540 \f
8541 /* Value should be nonzero if functions must have frame pointers.
8542 Zero means the frame pointer need not be set up (and parms may
8543 be accessed via the stack pointer) in functions that seem suitable. */
8545 static bool
8547 {
8548 /* If we accessed previous frames, then the generated code expects
8549 to be able to access the saved ebp value in our frame. */
8553 /* Several x86 os'es need a frame pointer for other reasons,
8554 usually pertaining to setjmp. */
8558 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
8562 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
8563 allocation is 4GB. */
8567 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
8568 turns off the frame pointer by default. Turn it back on now if
8569 we've not got a leaf function. */
8579 }
8581 /* Record that the current function accesses previous call frames. */
8583 void
8585 {
8587 }
8588 \f
8589 #ifndef USE_HIDDEN_LINKONCE
8590 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
8591 # define USE_HIDDEN_LINKONCE 1
8592 # else
8593 # define USE_HIDDEN_LINKONCE 0
8594 # endif
8595 #endif
8599 /* Fills in the label name that should be used for a pc thunk for
8600 the given register. */
8602 static void
8604 {
8609 else
8611 }
8614 /* This function generates code for -fpic that loads %ebx with
8615 the return address of the caller and then returns. */
8617 static void
8619 {
8624 {
8626 tree decl;
8642 #if TARGET_MACHO
8644 {
8653 }
8654 else
8655 #endif
8657 {
8668 }
8669 else
8670 {
8673 }
8679 /* Make sure unwind info is emitted for the thunk if needed. */
8682 /* Pad stack IP move with 4 instructions (two NOPs count
8683 as one instruction). */
8685 {
8690 }
8701 }
8705 }
8707 /* Emit code for the SET_GOT patterns. */
8711 {
8717 {
8718 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
8723 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
8724 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
8725 an unadorned address. */
8730 }
8735 {
8740 #if TARGET_MACHO
8741 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8742 is what will be referenced by the Mach-O PIC subsystem. */
8745 #endif
8749 }
8750 else
8751 {
8759 /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This
8760 is what will be referenced by the Mach-O PIC subsystem. */
8761 #if TARGET_MACHO
8764 else
8767 #endif
8768 }
8774 }
8776 /* Generate an "push" pattern for input ARG. */
8778 static rtx
8780 {
8793 stack_pointer_rtx)),
8794 arg);
8795 }
8797 /* Generate an "pop" pattern for input ARG. */
8799 static rtx
8801 {
8806 arg,
8809 stack_pointer_rtx)));
8810 }
8812 /* Return >= 0 if there is an unused call-clobbered register available
8813 for the entire function. */
8815 static unsigned int
8817 {
8821 {
8823 /* Can't use the same register for both PIC and DRAP. */
8826 else
8831 }
8834 }
8836 /* Return TRUE if we need to save REGNO. */
8838 static bool
8840 {
8850 {
8853 {
8859 }
8860 }
8869 }
8871 /* Return number of saved general prupose registers. */
8873 static int
8875 {
8881 nregs ++;
8883 }
8885 /* Return number of saved SSE registrers. */
8887 static int
8889 {
8897 nregs ++;
8899 }
8901 /* Given FROM and TO register numbers, say whether this elimination is
8902 allowed. If stack alignment is needed, we can only replace argument
8903 pointer with hard frame pointer, or replace frame pointer with stack
8904 pointer. Otherwise, frame pointer elimination is automatically
8905 handled and all other eliminations are valid. */
8907 static bool
8909 {
8915 else
8917 }
8919 /* Return the offset between two registers, one to be eliminated, and the other
8920 its replacement, at the start of a routine. */
8922 HOST_WIDE_INT
8924 {
8933 else
8934 {
8942 }
8943 }
8945 /* In a dynamically-aligned function, we can't know the offset from
8946 stack pointer to frame pointer, so we must ensure that setjmp
8947 eliminates fp against the hard fp (%ebp) rather than trying to
8948 index from %esp up to the top of the frame across a gap that is
8949 of unknown (at compile-time) size. */
8950 static rtx
8952 {
8954 }
8956 /* When using -fsplit-stack, the allocation routines set a field in
8957 the TCB to the bottom of the stack plus this much space, measured
8958 in bytes. */
8960 #define SPLIT_STACK_AVAILABLE 256
8962 /* Fill structure ix86_frame about frame of currently computed function. */
8964 static void
8966 {
8968 HOST_WIDE_INT offset;
8971 HOST_WIDE_INT to_allocate;
8979 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
8980 function prologues and leaf. */
8984 {
8989 }
8995 /* For SEH we have to limit the amount of code movement into the prologue.
8996 At present we do this via a BLOCKAGE, at which point there's very little
8997 scheduling that can be done, which means that there's very little point
8998 in doing anything except PUSHs. */
9002 /* During reload iteration the amount of registers saved can change.
9003 Recompute the value as needed. Do not recompute when amount of registers
9004 didn't change as reload does multiple calls to the function and does not
9005 expect the decision to change within single iteration. */
9008 {
9014 /* The fast prologue uses move instead of push to save registers. This
9015 is significantly longer, but also executes faster as modern hardware
9016 can execute the moves in parallel, but can't do that for push/pop.
9018 Be careful about choosing what prologue to emit: When function takes
9019 many instructions to execute we may use slow version as well as in
9020 case function is known to be outside hot spot (this is known with
9021 feedback only). Weight the size of function by number of registers
9022 to save as it is cheap to use one or two push instructions but very
9023 slow to use many of them. */
9027 || (flag_branch_probabilities
9030 else
9033 }
9035 frame->save_regs_using_mov
9037 /* If static stack checking is enabled and done with probes,
9038 the registers need to be saved before allocating the frame. */
9041 /* Skip return address. */
9044 /* Skip pushed static chain. */
9048 /* Skip saved base pointer. */
9053 /* The traditional frame pointer location is at the top of the frame. */
9056 /* Register save area */
9060 /* On SEH target, registers are pushed just before the frame pointer
9061 location. */
9065 /* Align and set SSE register save area. */
9067 {
9068 /* The only ABI that has saved SSE registers (Win64) also has a
9069 16-byte aligned default stack, and thus we don't need to be
9070 within the re-aligned local stack frame to save them. */
9074 }
9077 /* The re-aligned stack starts here. Values before this point are not
9078 directly comparable with values below this point. In order to make
9079 sure that no value happens to be the same before and after, force
9080 the alignment computation below to add a non-zero value. */
9084 /* Va-arg area */
9088 /* Align start of frame for local function. */
9097 /* Frame pointer points here. */
9102 /* Add outgoing arguments area. Can be skipped if we eliminated
9103 all the function calls as dead code.
9104 Skipping is however impossible when function calls alloca. Alloca
9105 expander assumes that last crtl->outgoing_args_size
9106 of stack frame are unused. */
9110 {
9113 }
9114 else
9117 /* Align stack boundary. Only needed if we're calling another function
9118 or using alloca. */
9123 /* We've reached end of stack frame. */
9126 /* Size prologue needs to allocate. */
9137 {
9143 }
9144 else
9148 /* The SEH frame pointer location is near the bottom of the frame.
9149 This is enforced by the fact that the difference between the
9150 stack pointer and the frame pointer is limited to 240 bytes in
9151 the unwind data structure. */
9153 {
9154 HOST_WIDE_INT diff;
9156 /* If we can leave the frame pointer where it is, do so. Also, returns
9157 the establisher frame for __builtin_frame_address (0). */
9162 {
9163 /* Ideally we'd determine what portion of the local stack frame
9164 (within the constraint of the lowest 240) is most heavily used.
9165 But without that complication, simply bias the frame pointer
9166 by 128 bytes so as to maximize the amount of the local stack
9167 frame that is addressable with 8-bit offsets. */
9169 }
9170 }
9171 }
9173 /* This is semi-inlined memory_address_length, but simplified
9174 since we know that we're always dealing with reg+offset, and
9175 to avoid having to create and discard all that rtl. */
9179 {
9183 {
9184 /* EBP and R13 cannot be encoded without an offset. */
9186 }
9190 /* ESP and R12 must be encoded with a SIB byte. */
9192 len++;
9195 }
9197 /* Return an RTX that points to CFA_OFFSET within the stack frame.
9198 The valid base registers are taken from CFUN->MACHINE->FS. */
9200 static rtx
9202 {
9208 {
9209 /* Choose the base register most likely to allow the most scheduling
9210 opportunities. Generally FP is valid throughout the function,
9211 while DRAP must be reloaded within the epilogue. But choose either
9212 over the SP due to increased encoding size. */
9215 {
9218 }
9220 {
9223 }
9225 {
9228 }
9229 }
9230 else
9231 {
9232 HOST_WIDE_INT toffset;
9235 /* Choose the base register with the smallest address encoding.
9236 With a tie, choose FP > DRAP > SP. */
9238 {
9242 }
9244 {
9248 {
9252 }
9253 }
9255 {
9259 {
9263 }
9264 }
9265 }
9269 }
9271 /* Emit code to save registers in the prologue. */
9273 static void
9275 {
9277 rtx insn;
9281 {
9284 }
9285 }
9287 /* Emit a single register save at CFA - CFA_OFFSET. */
9289 static void
9291 HOST_WIDE_INT cfa_offset)
9292 {
9300 /* For SSE saves, we need to indicate the 128-bit alignment. */
9311 /* When saving registers into a re-aligned local stack frame, avoid
9312 any tricky guessing by dwarf2out. */
9314 {
9318 {
9319 /* A bit of a hack. We force the DRAP register to be saved in
9320 the re-aligned stack frame, which provides us with a copy
9321 of the CFA that will last past the prologue. Install it. */
9327 }
9328 else
9329 {
9330 /* The frame pointer is a stable reference within the
9331 aligned frame. Use it. */
9338 }
9339 }
9341 /* The memory may not be relative to the current CFA register,
9342 which means that we may need to generate a new pattern for
9343 use by the unwind info. */
9345 {
9350 }
9351 }
9353 /* Emit code to save registers using MOV insns.
9354 First register is stored at CFA - CFA_OFFSET. */
9355 static void
9357 {
9362 {
9365 }
9366 }
9368 /* Emit code to save SSE registers using MOV insns.
9369 First register is stored at CFA - CFA_OFFSET. */
9370 static void
9372 {
9377 {
9380 }
9381 }
9385 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
9386 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
9387 Don't add the note if the previously saved value will be left untouched
9388 within stack red-zone till return, as unwinders can find the same value
9389 in the register and on the stack. */
9391 static void
9393 {
9399 {
9402 }
9403 else
9404 queued_cfa_restores
9406 }
9408 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
9410 static void
9412 {
9413 rtx last;
9417 ;
9422 }
9424 /* Expand prologue or epilogue stack adjustment.
9425 The pattern exist to put a dependency on all ebp-based memory accesses.
9426 STYLE should be negative if instructions should be marked as frame related,
9427 zero if %r11 register is live and cannot be freely used and positive
9428 otherwise. */
9430 static void
9433 {
9435 rtx insn;
9442 else
9443 {
9444 rtx tmp;
9445 /* r11 is used by indirect sibcall return as well, set before the
9446 epilogue and used after the epilogue. */
9449 else
9450 {
9454 }
9460 }
9467 {
9468 rtx r;
9478 }
9480 {
9483 {
9487 }
9488 }
9491 {
9496 {
9499 }
9501 {
9504 }
9505 else
9506 {
9507 /* Else there are two possibilities: SP itself, which we set
9508 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
9509 taken care of this by hand along the eh_return path. */
9512 }
9516 }
9517 }
9519 /* Find an available register to be used as dynamic realign argument
9520 pointer regsiter. Such a register will be written in prologue and
9521 used in begin of body, so it must not be
9522 1. parameter passing register.
9523 2. GOT pointer.
9524 We reuse static-chain register if it is available. Otherwise, we
9525 use DI for i386 and R13 for x86-64. We chose R13 since it has
9526 shorter encoding.
9528 Return: the regno of chosen register. */
9530 static unsigned int
9532 {
9536 {
9537 /* Use R13 for nested function or function need static chain.
9538 Since function with tail call may use any caller-saved
9539 registers in epilogue, DRAP must not use caller-saved
9540 register in such case. */
9545 }
9546 else
9547 {
9548 /* Use DI for nested function or function need static chain.
9549 Since function with tail call may use any caller-saved
9550 registers in epilogue, DRAP must not use caller-saved
9551 register in such case. */
9555 /* Reuse static chain register if it isn't used for parameter
9556 passing. */
9558 {
9562 }
9564 }
9565 }
9567 /* Return minimum incoming stack alignment. */
9569 static unsigned int
9571 {
9574 /* Prefer the one specified at command line. */
9577 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
9578 if -mstackrealign is used, it isn't used for sibcall check and
9579 estimated stack alignment is 128bit. */
9581 && !TARGET_64BIT
9582 && ix86_force_align_arg_pointer
9585 else
9588 /* Incoming stack alignment can be changed on individual functions
9589 via force_align_arg_pointer attribute. We use the smallest
9590 incoming stack boundary. */
9596 /* The incoming stack frame has to be aligned at least at
9597 parm_stack_boundary. */
9601 /* Stack at entrance of main is aligned by runtime. We use the
9602 smallest incoming stack boundary. */
9610 }
9612 /* Update incoming stack boundary and estimated stack alignment. */
9614 static void
9616 {
9617 ix86_incoming_stack_boundary
9620 /* x86_64 vararg needs 16byte stack alignment for register save
9621 area. */
9626 }
9628 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
9629 needed or an rtx for DRAP otherwise. */
9631 static rtx
9633 {
9638 {
9639 /* Assign DRAP to vDRAP and returns vDRAP */
9641 rtx drap_vreg;
9642 rtx arg_ptr;
9655 {
9658 }
9660 }
9661 else
9663 }
9665 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
9667 static rtx
9669 {
9671 }
9674 rtx reg;
9676 };
9678 /* Return a short-lived scratch register for use on function entry.
9679 In 32-bit mode, it is valid only after the registers are saved
9680 in the prologue. This register must be released by means of
9681 release_scratch_register_on_entry once it is dead. */
9683 static void
9685 {
9691 {
9692 /* We always use R11 in 64-bit mode. */
9694 }
9695 else
9696 {
9698 bool fastcall_p
9700 bool thiscall_p
9704 int drap_regno
9707 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
9708 for the static chain register. */
9712 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
9713 for the static chain register. */
9718 /* ecx is the static chain register. */
9720 && !static_chain_p
9725 /* esi is the static chain register. */
9731 else
9732 {
9735 }
9736 }
9740 {
9743 }
9744 }
9746 /* Release a scratch register obtained from the preceding function. */
9748 static void
9750 {
9752 {
9756 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
9762 }
9763 }
9765 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
9767 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
9769 static void
9771 {
9772 /* We skip the probe for the first interval + a small dope of 4 words and
9773 probe that many bytes past the specified size to maintain a protection
9774 area at the botton of the stack. */
9778 /* See if we have a constant small number of probes to generate. If so,
9779 that's the easy case. The run-time loop is made up of 11 insns in the
9780 generic case while the compile-time loop is made up of 3+2*(n-1) insns
9781 for n # of intervals. */
9783 {
9787 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
9788 values of N from 1 until it exceeds SIZE. If only one probe is
9789 needed, this will not generate any code. Then adjust and probe
9790 to PROBE_INTERVAL + SIZE. */
9792 {
9794 {
9797 }
9798 else
9805 }
9809 else
9817 /* Adjust back to account for the additional first interval. */
9821 }
9823 /* Otherwise, do the same as above, but in a loop. Note that we must be
9824 extra careful with variables wrapping around because we might be at
9825 the very top (or the very bottom) of the address space and we have
9826 to be able to handle this case properly; in particular, we use an
9827 equality test for the loop condition. */
9828 else
9829 {
9830 HOST_WIDE_INT rounded_size;
9836 /* Step 1: round SIZE to the previous multiple of the interval. */
9841 /* Step 2: compute initial and final value of the loop counter. */
9843 /* SP = SP_0 + PROBE_INTERVAL. */
9848 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
9852 stack_pointer_rtx)));
9855 /* Step 3: the loop
9857 while (SP != LAST_ADDR)
9858 {
9859 SP = SP + PROBE_INTERVAL
9860 probe at SP
9861 }
9863 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
9864 values of N from 1 until it is equal to ROUNDED_SIZE. */
9869 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
9870 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
9873 {
9878 }
9880 /* Adjust back to account for the additional first interval. */
9886 }
9890 /* Even if the stack pointer isn't the CFA register, we need to correctly
9891 describe the adjustments made to it, in particular differentiate the
9892 frame-related ones from the frame-unrelated ones. */
9894 {
9907 }
9909 /* Make sure nothing is scheduled before we are done. */
9911 }
9913 /* Adjust the stack pointer up to REG while probing it. */
9917 {
9927 /* Jump to END_LAB if SP == LAST_ADDR. */
9935 /* SP = SP + PROBE_INTERVAL. */
9939 /* Probe at SP. */
9950 }
9952 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
9953 inclusive. These are offsets from the current stack pointer. */
9955 static void
9957 {
9958 /* See if we have a constant small number of probes to generate. If so,
9959 that's the easy case. The run-time loop is made up of 7 insns in the
9960 generic case while the compile-time loop is made up of n insns for n #
9961 of intervals. */
9963 {
9964 HOST_WIDE_INT i;
9966 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
9967 it exceeds SIZE. If only one probe is needed, this will not
9968 generate any code. Then probe at FIRST + SIZE. */
9975 }
9977 /* Otherwise, do the same as above, but in a loop. Note that we must be
9978 extra careful with variables wrapping around because we might be at
9979 the very top (or the very bottom) of the address space and we have
9980 to be able to handle this case properly; in particular, we use an
9981 equality test for the loop condition. */
9982 else
9983 {
9990 /* Step 1: round SIZE to the previous multiple of the interval. */
9995 /* Step 2: compute initial and final value of the loop counter. */
9997 /* TEST_OFFSET = FIRST. */
10000 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
10004 /* Step 3: the loop
10006 while (TEST_ADDR != LAST_ADDR)
10007 {
10008 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
10009 probe at TEST_ADDR
10010 }
10012 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
10013 until it is equal to ROUNDED_SIZE. */
10018 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
10019 that SIZE is equal to ROUNDED_SIZE. */
10024 stack_pointer_rtx,
10029 }
10031 /* Make sure nothing is scheduled before we are done. */
10033 }
10035 /* Probe a range of stack addresses from REG to END, inclusive. These are
10036 offsets from the current stack pointer. */
10040 {
10050 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
10058 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
10062 /* Probe at TEST_ADDR. */
10075 }
10077 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
10078 to be generated in correct form. */
10079 static void
10081 {
10082 /* Check if stack realign is really needed after reload, and
10083 stores result in cfun */
10084 unsigned int incoming_stack_boundary
10093 {
10094 /* After stack_realign_needed is finalized, we can't no longer
10095 change it. */
10098 }
10100 /* If the only reason for frame_pointer_needed is that we conservatively
10101 assumed stack realignment might be needed, but in the end nothing that
10102 needed the stack alignment had been spilled, clear frame_pointer_needed
10103 and say we don't need stack realignment. */
10106 && frame_pointer_needed
10108 && flag_omit_frame_pointer
10110 && !ix86_current_function_calls_tls_descriptor
10119 {
10121 basic_block bb;
10128 HARD_FRAME_POINTER_REGNUM);
10130 {
10131 rtx insn;
10135 set_up_by_prologue))
10136 {
10140 }
10141 }
10155 }
10159 }
10161 /* Expand the prologue into a bunch of separate insns. */
10163 void
10165 {
10170 HOST_WIDE_INT allocate;
10176 /* DRAP should not coexist with stack_realign_fp */
10181 /* Initialize CFA state for before the prologue. */
10185 /* Track SP offset to the CFA. We continue tracking this after we've
10186 swapped the CFA register away from SP. In the case of re-alignment
10187 this is fudged; we're interested to offsets within the local frame. */
10194 {
10195 /* We should have already generated an error for any use of
10196 ms_hook on a nested function. */
10199 /* Check if profiling is active and we shall use profiling before
10200 prologue variant. If so sorry. */
10205 /* In ix86_asm_output_function_label we emitted:
10206 8b ff movl.s %edi,%edi
10207 55 push %ebp
10208 8b ec movl.s %esp,%ebp
10210 This matches the hookable function prologue in Win32 API
10211 functions in Microsoft Windows XP Service Pack 2 and newer.
10212 Wine uses this to enable Windows apps to hook the Win32 API
10213 functions provided by Wine.
10215 What that means is that we've already set up the frame pointer. */
10219 {
10222 /* We've decided to use the frame pointer already set up.
10223 Describe this to the unwinder by pretending that both
10224 push and mov insns happen right here.
10226 Putting the unwind info here at the end of the ms_hook
10227 is done so that we can make absolutely certain we get
10228 the required byte sequence at the start of the function,
10229 rather than relying on an assembler that can produce
10230 the exact encoding required.
10232 However it does mean (in the unpatched case) that we have
10233 a 1 insn window where the asynchronous unwind info is
10234 incorrect. However, if we placed the unwind info at
10235 its correct location we would have incorrect unwind info
10236 in the patched case. Which is probably all moot since
10237 I don't expect Wine generates dwarf2 unwind info for the
10238 system libraries that use this feature. */
10244 stack_pointer_rtx);
10252 /* Note that gen_push incremented m->fs.cfa_offset, even
10253 though we didn't emit the push insn here. */
10257 }
10258 else
10259 {
10260 /* The frame pointer is not needed so pop %ebp again.
10261 This leaves us with a pristine state. */
10263 }
10264 }
10266 /* The first insn of a function that accepts its static chain on the
10267 stack is to push the register that would be filled in by a direct
10268 call. This insn will be skipped by the trampoline. */
10270 {
10274 /* We don't want to interpret this push insn as a register save,
10275 only as a stack adjustment. The real copy of the register as
10276 a save will be done later, if needed. */
10281 }
10283 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
10284 of DRAP is needed and stack realignment is really needed after reload */
10286 {
10289 /* Only need to push parameter pointer reg if it is caller saved. */
10291 {
10292 /* Push arg pointer reg */
10295 }
10297 /* Grab the argument pointer. */
10304 /* Align the stack. */
10306 stack_pointer_rtx,
10310 /* Replicate the return address on the stack so that return
10311 address can be reached via (argp - 1) slot. This is needed
10312 to implement macro RETURN_ADDR_RTX and intrinsic function
10313 expand_builtin_return_addr etc. */
10319 /* For the purposes of frame and register save area addressing,
10320 we've started over with a new frame. */
10323 }
10329 {
10330 /* Note: AT&T enter does NOT have reversed args. Enter is probably
10331 slower on all targets. Also sdb doesn't like it. */
10335 /* Push registers now, before setting the frame pointer
10336 on SEH target. */
10338 && TARGET_SEH
10340 {
10344 }
10347 {
10355 }
10356 }
10359 {
10360 /* If saving registers via PUSH, do so now. */
10362 {
10366 }
10368 /* When using red zone we may start register saving before allocating
10369 the stack frame saving one cycle of the prologue. However, avoid
10370 doing this if we have to probe the stack; at least on x86_64 the
10371 stack probe can turn into a call that clobbers a red zone location. */
10373 && (! TARGET_STACK_PROBE
10375 {
10378 }
10379 }
10382 {
10386 /* The computation of the size of the re-aligned stack frame means
10387 that we must allocate the size of the register save area before
10388 performing the actual alignment. Otherwise we cannot guarantee
10389 that there's enough storage above the realignment point. */
10396 /* Align the stack. */
10398 stack_pointer_rtx,
10401 /* For the purposes of register save area addressing, the stack
10402 pointer is no longer valid. As for the value of sp_offset,
10403 see ix86_compute_frame_layout, which we need to match in order
10404 to pass verification of stack_pointer_offset at the end. */
10407 }
10412 {
10413 /* We start to count from ARG_POINTER. */
10416 /* If it was realigned, take into account the fake frame. */
10418 {
10425 /* This over-estimates by 1 minimal-stack-alignment-unit but
10426 mitigates that by counting in the new return address slot. */
10427 current_function_dynamic_stack_size
10429 }
10432 }
10434 /* On SEH target with very large frame size, allocate an area to save
10435 SSE registers (as the very large allocation won't be described). */
10439 {
10440 HOST_WIDE_INT sse_size =
10445 /* No need to do stack checking as the area will be immediately
10446 written. */
10453 }
10455 /* The stack has already been decremented by the instruction calling us
10456 so probe if the size is non-negative to preserve the protection area. */
10458 {
10459 /* We expect the registers to be saved when probes are used. */
10463 {
10466 }
10467 else
10468 {
10476 else
10478 }
10479 }
10482 ;
10485 {
10489 }
10490 else
10491 {
10504 /* Note that SEH directives need to continue tracking the stack
10505 pointer even after the frame pointer has been set up. */
10507 {
10511 {
10515 }
10516 }
10519 {
10524 {
10528 }
10529 }
10534 /* Use the fact that AX still contains ALLOCATE. */
10536 ? gen_pro_epilogue_adjust_stack_di_sub
10543 {
10551 }
10555 {
10562 }
10564 {
10569 }
10570 }
10573 /* If we havn't already set up the frame pointer, do so now. */
10575 {
10587 }
10595 /* We don't use pic-register for pe-coff target. */
10600 {
10607 }
10610 {
10612 {
10614 {
10624 label));
10628 }
10629 else
10631 }
10632 else
10633 {
10637 }
10638 }
10640 /* In the pic_reg_used case, make sure that the got load isn't deleted
10641 when mcount needs it. Blockage to avoid call movement across mcount
10642 call is emitted in generic code after the NOTE_INSN_PROLOGUE_END
10643 note. */
10648 {
10649 /* vDRAP is setup but after reload it turns out stack realign
10650 isn't necessary, here we will emit prologue to setup DRAP
10651 without stack realign adjustment */
10654 }
10656 /* Prevent instructions from being scheduled into register save push
10657 sequence when access to the redzone area is done through frame pointer.
10658 The offset between the frame pointer and the stack pointer is calculated
10659 relative to the value of the stack pointer at the end of the function
10660 prologue, and moving instructions that access redzone area via frame
10661 pointer inside push sequence violates this assumption. */
10665 /* Emit cld instruction if stringops are used in the function. */
10669 /* SEH requires that the prologue end within 256 bytes of the start of
10670 the function. Prevent instruction schedules that would extend that.
10671 Further, prevent alloca modifications to the stack pointer from being
10672 combined with prologue modifications. */
10675 }
10677 /* Emit code to restore REG using a POP insn. */
10679 static void
10681 {
10690 {
10691 /* Previously we'd represented the CFA as an expression
10692 like *(%ebp - 8). We've just popped that value from
10693 the stack, which means we need to reset the CFA to
10694 the drap register. This will remain until we restore
10695 the stack pointer. */
10699 /* This means that the DRAP register is valid for addressing too. */
10702 }
10705 {
10712 }
10714 /* When the frame pointer is the CFA, and we pop it, we are
10715 swapping back to the stack pointer as the CFA. This happens
10716 for stack frames that don't allocate other data, so we assume
10717 the stack pointer is now pointing at the return address, i.e.
10718 the function entry state, which makes the offset be 1 word. */
10720 {
10723 {
10731 }
10732 }
10733 }
10735 /* Emit code to restore saved registers using POP insns. */
10737 static void
10739 {
10745 }
10747 /* Emit code and notes for the LEAVE instruction. */
10749 static void
10751 {
10763 {
10771 }
10774 }
10776 /* Emit code to restore saved registers using MOV insns.
10777 First register is restored from CFA - CFA_OFFSET. */
10778 static void
10781 {
10787 {
10796 {
10797 /* Previously we'd represented the CFA as an expression
10798 like *(%ebp - 8). We've just popped that value from
10799 the stack, which means we need to reset the CFA to
10800 the drap register. This will remain until we restore
10801 the stack pointer. */
10805 /* This means that the DRAP register is valid for addressing. */
10807 }
10808 else
10812 }
10813 }
10815 /* Emit code to restore saved registers using MOV insns.
10816 First register is restored from CFA - CFA_OFFSET. */
10817 static void
10820 {
10825 {
10827 rtx mem;
10837 }
10838 }
10840 /* Restore function stack, frame, and registers. */
10842 void
10844 {
10860 /* The FP must be valid if the frame pointer is present. */
10865 /* We must have *some* valid pointer to the stack frame. */
10868 /* The DRAP is never valid at this point. */
10871 /* See the comment about red zone and frame
10872 pointer usage in ix86_expand_prologue. */
10879 /* Determine the CFA offset of the end of the red-zone. */
10882 {
10883 /* The red-zone begins below the return address. */
10886 /* When the register save area is in the aligned portion of
10887 the stack, determine the maximum runtime displacement that
10888 matches up with the aligned frame. */
10892 }
10894 /* Special care must be taken for the normal return case of a function
10895 using eh_return: the eax and edx registers are marked as saved, but
10896 not restored along this path. Adjust the save location to match. */
10900 /* EH_RETURN requires the use of moves to function properly. */
10903 /* SEH requires the use of pops to identify the epilogue. */
10906 /* If we're only restoring one register and sp is not valid then
10907 using a move instruction to restore the register since it's
10908 less work than reloading sp and popping the register. */
10921 && TARGET_USE_LEAVE
10925 else
10929 {
10930 /* Ensure that the entire register save area is addressable via
10931 the stack pointer, if we will restore via sp. */
10936 {
10940 style,
10942 }
10943 }
10945 /* If there are any SSE registers to restore, then we have to do it
10946 via moves, since there's obviously no pop for SSE regs. */
10952 {
10953 rtx t;
10958 /* eh_return epilogues need %ecx added to the stack pointer. */
10960 {
10963 /* Stack align doesn't work with eh_return. */
10965 /* Neither does regparm nested functions. */
10969 {
10977 /* Note that we use SA as a temporary CFA, as the return
10978 address is at the proper place relative to it. We
10979 pretend this happens at the FP restore insn because
10980 prior to this insn the FP would be stored at the wrong
10981 offset relative to SA, and after this insn we have no
10982 other reasonable register to use for the CFA. We don't
10983 bother resetting the CFA to the SP for the duration of
10984 the return insn. */
10997 }
10998 else
10999 {
11007 {
11011 UNITS_PER_WORD));
11013 }
11014 }
11017 }
11018 }
11019 else
11020 {
11021 /* SEH requires that the function end with (1) a stack adjustment
11022 if necessary, (2) a sequence of pops, and (3) a return or
11023 jump instruction. Prevent insns from the function body from
11024 being scheduled into this sequence. */
11026 {
11027 /* Prevent a catch region from being adjacent to the standard
11028 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
11029 several other flags that would be interesting to test are
11030 not yet set up. */
11033 else
11035 }
11037 /* First step is to deallocate the stack frame so that we can
11038 pop the registers. Also do it on SEH target for very large
11039 frame as the emitted instructions aren't allowed by the ABI in
11040 epilogues. */
11042 || (TARGET_SEH
11045 {
11050 }
11052 {
11056 style,
11058 }
11061 }
11063 /* If we used a stack pointer and haven't already got rid of it,
11064 then do so now. */
11066 {
11067 /* If the stack pointer is valid and pointing at the frame
11068 pointer store address, then we only need a pop. */
11071 /* Leave results in shorter dependency chains on CPUs that are
11072 able to grok it fast. */
11077 else
11078 {
11080 hard_frame_pointer_rtx,
11083 }
11084 }
11087 {
11089 rtx insn;
11115 }
11117 /* At this point the stack pointer must be valid, and we must have
11118 restored all of the registers. We may not have deallocated the
11119 entire stack frame. We've delayed this until now because it may
11120 be possible to merge the local stack deallocation with the
11121 deallocation forced by ix86_static_chain_on_stack. */
11126 {
11130 }
11131 else
11134 /* Sibcall epilogues don't want a return instruction. */
11136 {
11139 }
11142 {
11145 /* i386 can only pop 64K bytes. If asked to pop more, pop return
11146 address, do explicit add, and jump indirectly to the caller. */
11149 {
11151 rtx insn;
11153 /* There is no "pascal" calling convention in any 64bit ABI. */
11169 }
11170 else
11172 }
11173 else
11176 /* Restore the state back to the state from the prologue,
11177 so that it's correct for the next epilogue. */
11179 }
11181 /* Reset from the function's potential modifications. */
11183 static void
11185 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
11186 {
11189 #if TARGET_MACHO
11190 /* Mach-O doesn't support labels at the end of objects, so if
11191 it looks like we might want one, insert a NOP. */
11192 {
11198 {
11199 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
11200 notes only, instead set their CODE_LABEL_NUMBER to -1,
11201 otherwise there would be code generation differences
11202 in between -g and -g0. */
11206 }
11216 }
11217 #endif
11219 }
11221 /* Return a scratch register to use in the split stack prologue. The
11222 split stack prologue is used for -fsplit-stack. It is the first
11223 instructions in the function, even before the regular prologue.
11224 The scratch register can be any caller-saved register which is not
11225 used for parameters or for the static chain. */
11227 static unsigned int
11229 {
11232 else
11233 {
11246 {
11248 {
11252 }
11254 }
11256 {
11260 }
11262 {
11265 else
11266 {
11268 {
11272 }
11274 }
11275 }
11276 else
11277 {
11278 /* FIXME: We could make this work by pushing a register
11279 around the addition and comparison. */
11282 }
11283 }
11284 }
11286 /* A SYMBOL_REF for the function which allocates new stackspace for
11287 -fsplit-stack. */
11291 /* A SYMBOL_REF for the more stack function when using the large
11292 model. */
11296 /* Handle -fsplit-stack. These are the first instructions in the
11297 function, even before the regular prologue. */
11299 void
11301 {
11303 HOST_WIDE_INT allocate;
11308 rtx fn;
11316 /* This is the label we will branch to if we have enough stack
11317 space. We expect the basic block reordering pass to reverse this
11318 branch if optimizing, so that we branch in the unlikely case. */
11321 /* We need to compare the stack pointer minus the frame size with
11322 the stack boundary in the TCB. The stack boundary always gives
11323 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
11324 can compare directly. Otherwise we need to do an addition. */
11327 UNSPEC_STACK_CHECK);
11332 else
11333 {
11335 rtx offset;
11337 /* We need a scratch register to hold the stack pointer minus
11338 the required frame size. Since this is the very start of the
11339 function, the scratch register can be any caller-saved
11340 register which is not used for parameters. */
11347 {
11348 /* We don't use ix86_gen_add3 in this case because it will
11349 want to split to lea, but when not optimizing the insn
11350 will not be split after this point. */
11353 offset)));
11354 }
11355 else
11356 {
11359 stack_pointer_rtx));
11360 }
11362 }
11368 /* Mark the jump as very likely to be taken. */
11376 /* Get more stack space. We pass in the desired stack space and the
11377 size of the arguments to copy to the new stack. In 32-bit mode
11378 we push the parameters; __morestack will return on a new stack
11379 anyhow. In 64-bit mode we pass the parameters in r10 and
11380 r11. */
11385 {
11391 /* If this function uses a static chain, it will be in %r10.
11392 Preserve it across the call to __morestack. */
11394 {
11395 rtx rax;
11400 }
11404 {
11405 HOST_WIDE_INT argval;
11408 /* When using the large model we need to load the address
11409 into a register, and we've run out of registers. So we
11410 switch to a different calling convention, and we call a
11411 different function: __morestack_large. We pass the
11412 argument size in the upper 32 bits of r10 and pass the
11413 frame size in the lower 32 bits. */
11418 split_stack_fn_large =
11422 {
11432 UNSPEC_GOT);
11438 }
11439 else
11446 }
11447 else
11448 {
11452 }
11455 }
11456 else
11457 {
11460 }
11466 /* In order to make call/return prediction work right, we now need
11467 to execute a return instruction. See
11468 libgcc/config/i386/morestack.S for the details on how this works.
11470 For flow purposes gcc must not see this as a return
11471 instruction--we need control flow to continue at the subsequent
11472 label. Therefore, we use an unspec. */
11476 /* If we are in 64-bit mode and this function uses a static chain,
11477 we saved %r10 in %rax before calling _morestack. */
11482 /* If this function calls va_start, we need to store a pointer to
11483 the arguments on the old stack, because they may not have been
11484 all copied to the new stack. At this point the old stack can be
11485 found at the frame pointer value used by __morestack, because
11486 __morestack has set that up before calling back to us. Here we
11487 store that pointer in a scratch register, and in
11488 ix86_expand_prologue we store the scratch register in a stack
11489 slot. */
11491 {
11493 rtx frame_reg;
11500 /* 64-bit:
11501 fp -> old fp value
11502 return address within this function
11503 return address of caller of this function
11504 stack arguments
11505 So we add three words to get to the stack arguments.
11507 32-bit:
11508 fp -> old fp value
11509 return address within this function
11510 first argument to __morestack
11511 second argument to __morestack
11512 return address of caller of this function
11513 stack arguments
11514 So we add five words to get to the stack arguments.
11515 */
11526 }
11531 /* If this function calls va_start, we now have to set the scratch
11532 register for the case where we do not call __morestack. In this
11533 case we need to set it based on the stack pointer. */
11535 {
11542 }
11543 }
11545 /* We may have to tell the dataflow pass that the split stack prologue
11546 is initializing a scratch register. */
11548 static void
11550 {
11552 {
11555 }
11556 }
11557 \f
11558 /* Determine if op is suitable SUBREG RTX for address. */
11560 static bool
11562 {
11573 /* Don't allow SUBREGs that span more than a word. It can lead to spill
11574 failures when the register is one word out of a two word structure. */
11578 /* Allow only SUBREGs of non-eliminable hard registers. */
11580 }
11582 /* Extract the parts of an RTL expression that is a valid memory address
11583 for an instruction. Return 0 if the structure of the address is
11584 grossly off. Return -1 if the address contains ASHIFT, so it is not
11585 strictly valid, but still used for computing length of lea instruction. */
11587 int
11589 {
11594 rtx tmp;
11598 /* Allow zero-extended SImode addresses,
11599 they will be emitted with addr32 prefix. */
11601 {
11604 {
11608 }
11611 {
11618 }
11619 }
11621 /* Allow SImode subregs of DImode addresses,
11622 they will be emitted with addr32 prefix. */
11624 {
11627 {
11631 }
11632 }
11637 {
11640 else
11642 }
11644 {
11649 do
11650 {
11655 }
11662 {
11665 {
11690 /* FALLTHRU */
11694 && TARGET_TLS_DIRECT_SEG_REFS
11697 else
11704 /* FALLTHRU */
11711 else
11726 }
11727 }
11728 }
11730 {
11733 }
11735 {
11736 /* We're called for lea too, which implements ashift on occasion. */
11746 }
11748 {
11752 /* Constant addresses are sign extended to 64bit, we have to
11753 prevent addresses from 0x80000000 to 0xffffffff in x32 mode. */
11759 }
11760 else
11764 {
11766 ;
11769 ;
11770 else
11772 }
11774 /* Address override works only on the (%reg) part of %fs:(%reg). */
11780 /* Extract the integral value of scale. */
11782 {
11786 }
11791 /* Avoid useless 0 displacement. */
11795 /* Allow arg pointer and stack pointer as index if there is not scaling. */
11800 {
11801 rtx tmp;
11804 }
11806 /* Special case: %ebp cannot be encoded as a base without a displacement.
11807 Similarly %r13. */
11809 && base_reg
11818 /* Special case: on K6, [%esi] makes the instruction vector decoded.
11819 Avoid this by transforming to [%esi+0].
11820 Reload calls address legitimization without cfun defined, so we need
11821 to test cfun for being non-NULL. */
11827 /* Special case: encode reg+reg instead of reg*2. */
11831 /* Special case: scaling cannot be encoded without base or displacement. */
11842 }
11843 \f
11844 /* Return cost of the memory address x.
11845 For i386, it is better to use a complex address than let gcc copy
11846 the address into a reg and make a new pseudo. But not if the address
11847 requires to two regs - that would mean more pseudos with longer
11848 lifetimes. */
11849 static int
11851 addr_space_t as ATTRIBUTE_UNUSED,
11853 {
11865 /* Attempt to minimize number of registers in the address. */
11871 cost++;
11878 cost++;
11880 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
11881 since it's predecode logic can't detect the length of instructions
11882 and it degenerates to vector decoded. Increase cost of such
11883 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
11884 to split such addresses or even refuse such addresses at all.
11886 Following addressing modes are affected:
11887 [base+scale*index]
11888 [scale*index+disp]
11889 [base+index]
11891 The first and last case may be avoidable by explicitly coding the zero in
11892 memory address, but I don't have AMD-K6 machine handy to check this
11893 theory. */
11902 }
11903 \f
11904 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
11905 this is used for to form addresses to local data when -fPIC is in
11906 use. */
11908 static bool
11910 {
11913 }
11915 /* Determine if a given RTX is a valid constant. We already know this
11916 satisfies CONSTANT_P. */
11918 static bool
11920 {
11922 {
11927 {
11931 }
11936 /* Only some unspecs are valid as "constants". */
11939 {
11955 }
11957 /* We must have drilled down to a symbol. */
11962 /* FALLTHRU */
11965 /* TLS symbols are never valid. */
11969 /* DLLIMPORT symbols are never valid. */
11974 #if TARGET_MACHO
11975 /* mdynamic-no-pic */
11978 #endif
11994 }
11996 /* Otherwise we handle everything else in the move patterns. */
11998 }
12000 /* Determine if it's legal to put X into the constant pool. This
12001 is not possible for the address of thread-local symbols, which
12002 is checked above. */
12004 static bool
12006 {
12007 /* We can always put integral constants and vectors in memory. */
12009 {
12017 }
12019 }
12021 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
12022 otherwise zero. */
12024 static bool
12026 {
12032 }
12035 /* Nonzero if the constant value X is a legitimate general operand
12036 when generating PIC code. It is given that flag_pic is on and
12037 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
12039 bool
12041 {
12042 rtx inner;
12045 {
12052 /* Only some unspecs are valid as "constants". */
12055 {
12068 }
12069 /* FALLTHRU */
12077 }
12078 }
12080 /* Determine if a given CONST RTX is a valid memory displacement
12081 in PIC mode. */
12083 bool
12085 {
12088 /* In 64bit mode we can allow direct addresses of symbols and labels
12089 when they are not dynamic symbols. */
12091 {
12095 {
12119 /* FALLTHRU */
12122 /* TLS references should always be enclosed in UNSPEC.
12123 The dllimported symbol needs always to be resolved. */
12129 {
12137 /* Function-symbols need to be resolved only for
12138 large-model.
12139 For the small-model we don't need to resolve anything
12140 here. */
12145 /* Non-external symbols don't need to be resolved for
12146 large, and medium-model. */
12151 }
12160 }
12161 }
12167 {
12168 /* We are unsafe to allow PLUS expressions. This limit allowed distance
12169 of GOT tables. We should not need these anyway. */
12181 }
12185 {
12190 }
12199 {
12203 /* We need to check for both symbols and labels because VxWorks loads
12204 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
12205 details. */
12209 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
12210 While ABI specify also 32bit relocation but we don't produce it in
12211 small PIC model at all. */
12233 }
12236 }
12238 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
12239 replace the input X, or the original X if no replacement is called for.
12240 The output parameter *WIN is 1 if the calling macro should goto WIN,
12241 0 if it should not. */
12243 bool
12248 {
12249 /* Reload can generate:
12251 (plus:DI (plus:DI (unspec:DI [(const_int 0 [0])] UNSPEC_TP)
12252 (reg:DI 97))
12253 (reg:DI 2 cx))
12255 This RTX is rejected from ix86_legitimate_address_p due to
12256 non-strictness of base register 97. Following this rejection,
12257 reload pushes all three components into separate registers,
12258 creating invalid memory address RTX.
12260 Following code reloads only the invalid part of the
12261 memory address RTX. */
12267 {
12273 {
12278 }
12282 {
12287 }
12291 }
12294 }
12296 /* Recognizes RTL expressions that are valid memory addresses for an
12297 instruction. The MODE argument is the machine mode for the MEM
12298 expression that wants to use this address.
12300 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
12301 convert common non-canonical forms to canonical form so that they will
12302 be recognized. */
12304 static bool
12307 {
12310 HOST_WIDE_INT scale;
12313 /* Decomposition failed. */
12321 /* Validate base register. */
12323 {
12324 rtx reg;
12330 else
12331 /* Base is not a register. */
12339 /* Base is not valid. */
12341 }
12343 /* Validate index register. */
12345 {
12346 rtx reg;
12352 else
12353 /* Index is not a register. */
12361 /* Index is not valid. */
12363 }
12365 /* Index and base should have the same mode. */
12370 /* Validate scale factor. */
12372 {
12374 /* Scale without index. */
12378 /* Scale is not a valid multiplier. */
12380 }
12382 /* Validate displacement. */
12384 {
12389 {
12390 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
12391 used. While ABI specify also 32bit relocations, we don't produce
12392 them at all and use IP relative instead. */
12399 /* 64bit address unspec. */
12419 /* Invalid address unspec. */
12421 }
12424 && (flag_pic
12425 || (TARGET_MACHO
12426 #if TARGET_MACHO
12427 && MACHOPIC_INDIRECT
12429 #endif
12430 )))
12431 {
12433 is_legitimate_pic:
12435 {
12436 /* foo@dtpoff(%rX) is ok. */
12443 /* Non-constant pic memory reference. */
12445 }
12448 /* Displacement is an invalid pic construct. */
12450 #if TARGET_MACHO
12453 /* displacment must be referenced via non_lazy_pointer */
12455 #endif
12457 /* This code used to verify that a symbolic pic displacement
12458 includes the pic_offset_table_rtx register.
12460 While this is good idea, unfortunately these constructs may
12461 be created by "adds using lea" optimization for incorrect
12462 code like:
12464 int a;
12465 int foo(int i)
12466 {
12467 return *(&a+i);
12468 }
12470 This code is nonsensical, but results in addressing
12471 GOT table with pic_offset_table_rtx base. We can't
12472 just refuse it easily, since it gets matched by
12473 "addsi3" pattern, that later gets split to lea in the
12474 case output register differs from input. While this
12475 can be handled by separate addsi pattern for this case
12476 that never results in lea, this seems to be easier and
12477 correct fix for crash to disable this test. */
12478 }
12485 /* Displacement is not constant. */
12489 /* Displacement is out of range. */
12491 }
12493 /* Everything looks valid. */
12495 }
12497 /* Determine if a given RTX is a valid constant address. */
12499 bool
12501 {
12503 }
12504 \f
12505 /* Return a unique alias set for the GOT. */
12507 static alias_set_type
12509 {
12514 }
12516 /* Return a legitimate reference for ORIG (an address) using the
12517 register REG. If REG is 0, a new pseudo is generated.
12519 There are two types of references that must be handled:
12521 1. Global data references must load the address from the GOT, via
12522 the PIC reg. An insn is emitted to do this load, and the reg is
12523 returned.
12525 2. Static data references, constant pool addresses, and code labels
12526 compute the address as an offset from the GOT, whose base is in
12527 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
12528 differentiate them from global data objects. The returned
12529 address is the PIC reg + an unspec constant.
12531 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
12532 reg also appears in the address. */
12534 static rtx
12536 {
12540 #if TARGET_MACHO
12542 {
12545 /* Use the generic Mach-O PIC machinery. */
12547 }
12548 #endif
12551 {
12555 }
12561 {
12562 rtx tmpreg;
12563 /* This symbol may be referenced via a displacement from the PIC
12564 base address (@GOTOFF). */
12571 {
12573 UNSPEC_GOTOFF);
12575 }
12576 else
12581 else
12586 {
12590 }
12591 else
12593 }
12595 {
12596 /* This symbol may be referenced via a displacement from the PIC
12597 base address (@GOTOFF). */
12604 {
12606 UNSPEC_GOTOFF);
12608 }
12609 else
12615 {
12618 }
12619 }
12621 /* We can't use @GOTOFF for text labels on VxWorks;
12622 see gotoff_operand. */
12624 {
12629 /* For x64 PE-COFF there is no GOT table. So we use address
12630 directly. */
12632 {
12640 }
12642 {
12650 /* Use directly gen_movsi, otherwise the address is loaded
12651 into register for CSE. We don't want to CSE this addresses,
12652 instead we CSE addresses from the GOT table, so skip this. */
12655 }
12656 else
12657 {
12658 /* This symbol must be referenced via a load from the
12659 Global Offset Table (@GOT). */
12675 }
12676 }
12677 else
12678 {
12681 {
12683 {
12686 }
12687 else
12689 }
12691 {
12694 /* We must match stuff we generate before. Assume the only
12695 unspecs that can get here are ours. Not that we could do
12696 anything with them anyway.... */
12702 }
12704 {
12707 /* Check first to see if this is a constant offset from a @GOTOFF
12708 symbol reference. */
12711 {
12713 {
12717 UNSPEC_GOTOFF);
12723 {
12726 }
12727 }
12728 else
12729 {
12732 {
12736 }
12737 }
12738 }
12739 else
12740 {
12743 new_rtx
12747 {
12750 {
12753 new_rtx
12755 }
12756 else
12758 }
12759 else
12760 {
12763 {
12766 }
12768 }
12769 }
12770 }
12771 }
12773 }
12774 \f
12775 /* Load the thread pointer. If TO_REG is true, force it into a register. */
12777 static rtx
12779 {
12783 {
12788 }
12794 }
12796 /* Construct the SYMBOL_REF for the tls_get_addr function. */
12800 static rtx
12802 {
12804 {
12810 }
12813 }
12815 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
12819 rtx
12821 {
12823 {
12824 ix86_tls_module_base_symbol
12829 }
12832 }
12834 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
12835 false if we expect this to be used for a memory address and true if
12836 we expect to load the address into a register. */
12838 static rtx
12840 {
12847 {
12852 {
12855 else
12856 {
12859 }
12860 }
12863 {
12866 else
12876 }
12877 else
12878 {
12882 {
12884 rtx insns;
12887 emit_call_insn
12897 }
12898 else
12900 }
12907 {
12910 else
12911 {
12914 }
12915 }
12918 {
12923 else
12929 }
12930 else
12931 {
12935 {
12940 emit_call_insn
12945 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
12946 share the LD_BASE result with other LD model accesses. */
12948 UNSPEC_TLS_LD_BASE);
12952 }
12953 else
12955 }
12963 {
12970 }
12975 {
12977 {
12978 /* The Sun linker took the AMD64 TLS spec literally
12979 and can only handle %rax as destination of the
12980 initial executable code sequence. */
12985 }
12987 /* Generate DImode references to avoid %fs:(%reg32)
12988 problems and linker IE->LE relaxation bug. */
12992 }
12994 {
12999 }
13001 {
13005 }
13006 else
13007 {
13010 }
13020 {
13025 }
13026 else
13027 {
13031 }
13041 {
13045 }
13046 else
13047 {
13051 }
13056 }
13059 }
13061 /* Create or return the unique __imp_DECL dllimport symbol corresponding
13062 to symbol DECL if BEIMPORT is true. Otherwise create or return the
13063 unique refptr-DECL symbol corresponding to symbol DECL. */
13066 htab_t dllimport_map;
13068 static tree
13070 {
13077 tree to;
13078 rtx rtl;
13105 else
13118 {
13120 #ifdef SUB_TARGET_RECORD_STUB
13122 #endif
13123 }
13132 }
13134 /* Expand SYMBOL into its corresponding far-addresse symbol.
13135 WANT_REG is true if we require the result be a register. */
13137 static rtx
13139 {
13140 tree imp_decl;
13141 rtx x;
13150 }
13152 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
13153 true if we require the result be a register. */
13155 static rtx
13157 {
13158 tree imp_decl;
13159 rtx x;
13168 }
13170 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
13171 is true if we require the result be a register. */
13173 static rtx
13175 {
13180 {
13187 {
13190 }
13191 }
13207 {
13210 }
13212 }
13214 /* Try machine-dependent ways of modifying an illegitimate address
13215 to be legitimate. If we find one, return the new, valid address.
13216 This macro is used in only one place: `memory_address' in explow.c.
13218 OLDX is the address as it was before break_out_memory_refs was called.
13219 In some cases it is useful to look at this to decide what needs to be done.
13221 It is always safe for this macro to do nothing. It exists to recognize
13222 opportunities to optimize the output.
13224 For the 80386, we handle X+REG by loading X into a register R and
13225 using R+REG. R will go in a general reg and indexing will be used.
13226 However, if REG is a broken-out memory address or multiplication,
13227 nothing needs to be done because REG can certainly go in a general reg.
13229 When -fpic is used, special handling is needed for symbolic references.
13230 See comments by legitimize_pic_address in i386.c for details. */
13232 static rtx
13235 {
13246 {
13250 }
13253 {
13257 }
13262 #if TARGET_MACHO
13265 #endif
13267 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
13271 {
13276 }
13279 {
13280 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
13285 {
13291 }
13296 {
13302 }
13304 /* Put multiply first if it isn't already. */
13306 {
13311 }
13313 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
13314 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
13315 created by virtual register instantiation, register elimination, and
13316 similar optimizations. */
13318 {
13324 }
13326 /* Canonicalize
13327 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
13328 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
13333 {
13334 rtx constant;
13338 {
13341 }
13343 {
13346 }
13347 else
13351 {
13358 }
13359 }
13365 {
13368 }
13371 {
13374 }
13382 {
13385 }
13391 {
13395 {
13398 }
13402 }
13405 {
13409 {
13412 }
13416 }
13417 }
13420 }
13421 \f
13422 /* Print an integer constant expression in assembler syntax. Addition
13423 and subtraction are the only arithmetic that may appear in these
13424 expressions. FILE is the stdio stream to write to, X is the rtx, and
13425 CODE is the operand print code from the output string. */
13427 static void
13429 {
13433 {
13442 else
13443 {
13446 /* Mark the decl as referenced so that cgraph will
13447 output the function. */
13451 #if TARGET_MACHO
13455 #endif
13457 }
13465 /* FALLTHRU */
13476 /* This used to output parentheses around the expression,
13477 but that does not work on the 386 (either ATT or BSD assembler). */
13483 {
13484 /* We can use %d if the number is <32 bits and positive. */
13489 else
13491 }
13492 else
13493 /* We can't handle floating point constants;
13494 TARGET_PRINT_OPERAND must handle them. */
13499 /* Some assemblers need integer constants to appear first. */
13501 {
13505 }
13506 else
13507 {
13512 }
13527 {
13531 }
13536 {
13555 /* FIXME: This might be @TPOFF in Sun ld too. */
13564 else
13574 else
13580 #if TARGET_MACHO
13585 #endif
13589 }
13594 }
13595 }
13597 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
13598 We need to emit DTP-relative relocations. */
13600 static void ATTRIBUTE_UNUSED
13602 {
13607 {
13615 }
13616 }
13618 /* Return true if X is a representation of the PIC register. This copes
13619 with calls from ix86_find_base_term, where the register might have
13620 been replaced by a cselib value. */
13622 static bool
13624 {
13628 else
13630 }
13632 /* Helper function for ix86_delegitimize_address.
13633 Attempt to delegitimize TLS local-exec accesses. */
13635 static rtx
13637 {
13662 {
13667 }
13673 }
13675 /* In the name of slightly smaller debug output, and to cater to
13676 general assembler lossage, recognize PIC+GOTOFF and turn it back
13677 into a direct symbol reference.
13679 On Darwin, this is necessary to avoid a crash, because Darwin
13680 has a different PIC label for each routine but the DWARF debugging
13681 information is not associated with any particular routine, so it's
13682 necessary to remove references to the PIC label from RTL stored by
13683 the DWARF output code. */
13685 static rtx
13687 {
13689 /* addend is NULL or some rtx if x is something+GOTOFF where
13690 something doesn't include the PIC register. */
13692 /* reg_addend is NULL or a multiple of some register. */
13694 /* const_addend is NULL or a const_int. */
13696 /* This is the result, or NULL. */
13705 {
13712 {
13718 }
13727 {
13732 }
13734 }
13741 /* %ebx + GOT/GOTOFF */
13742 ;
13744 {
13745 /* %ebx + %reg * scale + GOT/GOTOFF */
13751 else
13752 {
13755 }
13756 }
13757 else
13763 {
13766 }
13785 {
13786 /* If the rest of original X doesn't involve the PIC register, add
13787 addend and subtract pic_offset_table_rtx. This can happen e.g.
13788 for code like:
13789 leal (%ebx, %ecx, 4), %ecx
13790 ...
13791 movl foo@GOTOFF(%ecx), %edx
13792 in which case we return (%ecx - %ebx) + foo. */
13795 pic_offset_table_rtx),
13796 result);
13797 else
13799 }
13801 {
13805 }
13807 }
13809 /* If X is a machine specific address (i.e. a symbol or label being
13810 referenced as a displacement from the GOT implemented using an
13811 UNSPEC), then return the base term. Otherwise return X. */
13813 rtx
13815 {
13816 rtx term;
13819 {
13833 }
13836 }
13837 \f
13838 static void
13841 {
13845 {
13848 }
13853 {
13856 {
13875 }
13879 {
13898 }
13905 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
13906 Those same assemblers have the same but opposite lossage on cmov. */
13911 else
13916 {
13929 }
13937 {
13950 }
13953 /* ??? As above. */
13962 /* ??? As above. */
13967 else
13978 }
13980 }
13982 /* Print the name of register X to FILE based on its machine mode and number.
13983 If CODE is 'w', pretend the mode is HImode.
13984 If CODE is 'b', pretend the mode is QImode.
13985 If CODE is 'k', pretend the mode is SImode.
13986 If CODE is 'q', pretend the mode is DImode.
13987 If CODE is 'x', pretend the mode is V4SFmode.
13988 If CODE is 't', pretend the mode is V8SFmode.
13989 If CODE is 'h', pretend the reg is the 'high' byte register.
13990 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
13991 If CODE is 'd', duplicate the operand for AVX instruction.
13992 */
13994 void
13996 {
14005 {
14009 }
14034 else
14037 /* Irritatingly, AMD extended registers use different naming convention
14038 from the normal registers: "r%d[bwd]" */
14040 {
14045 {
14059 /* no suffix */
14064 }
14066 }
14070 {
14073 {
14076 }
14077 /* FALLTHRU */
14083 /* FALLTHRU */
14086 normal:
14101 {
14106 }
14110 }
14114 {
14117 else
14119 }
14120 }
14122 /* Locate some local-dynamic symbol still in use by this function
14123 so that we can print its name in some tls_local_dynamic_base
14124 pattern. */
14126 static int
14128 {
14133 {
14136 }
14139 }
14143 {
14144 rtx insn;
14155 }
14157 /* Meaning of CODE:
14158 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
14159 C -- print opcode suffix for set/cmov insn.
14160 c -- like C, but print reversed condition
14161 F,f -- likewise, but for floating-point.
14162 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
14163 otherwise nothing
14164 R -- print the prefix for register names.
14165 z -- print the opcode suffix for the size of the current operand.
14166 Z -- likewise, with special suffixes for x87 instructions.
14167 * -- print a star (in certain assembler syntax)
14168 A -- print an absolute memory reference.
14169 E -- print address with DImode register names if TARGET_64BIT.
14170 w -- print the operand as if it's a "word" (HImode) even if it isn't.
14171 s -- print a shift double count, followed by the assemblers argument
14172 delimiter.
14173 b -- print the QImode name of the register for the indicated operand.
14174 %b0 would print %al if operands[0] is reg 0.
14175 w -- likewise, print the HImode name of the register.
14176 k -- likewise, print the SImode name of the register.
14177 q -- likewise, print the DImode name of the register.
14178 x -- likewise, print the V4SFmode name of the register.
14179 t -- likewise, print the V8SFmode name of the register.
14180 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
14181 y -- print "st(0)" instead of "st" as a register.
14182 d -- print duplicated register operand for AVX instruction.
14183 D -- print condition for SSE cmp instruction.
14184 P -- if PIC, print an @PLT suffix.
14185 p -- print raw symbol name.
14186 X -- don't print any sort of PIC '@' suffix for a symbol.
14187 & -- print some in-use local-dynamic symbol name.
14188 H -- print a memory address offset by 8; used for sse high-parts
14189 Y -- print condition for XOP pcom* instruction.
14190 + -- print a branch hint as 'cs' or 'ds' prefix
14191 ; -- print a semicolon (after prefixes due to bug in older gas).
14192 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
14193 @ -- print a segment register of thread base pointer load
14194 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
14195 */
14197 void
14199 {
14201 {
14203 {
14206 {
14212 /* Intel syntax. For absolute addresses, registers should not
14213 be surrounded by braces. */
14215 {
14220 }
14225 }
14231 /* Wrap address in an UNSPEC to declare special handling. */
14269 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14274 {
14288 output_operand_lossage
14291 }
14294 #endif
14299 {
14300 /* Opcodes don't get size suffixes if using Intel opcodes. */
14305 {
14323 output_operand_lossage
14326 }
14327 }
14330 warning
14332 /* FALLTHRU */
14335 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
14340 {
14342 {
14344 #ifdef HAVE_AS_IX86_FILDS
14346 #endif
14354 #ifdef HAVE_AS_IX86_FILDQ
14356 #else
14358 #endif
14363 }
14364 }
14366 {
14367 /* 387 opcodes don't get size suffixes
14368 if the operands are registers. */
14373 {
14389 }
14390 }
14391 else
14392 {
14393 output_operand_lossage
14396 }
14398 output_operand_lossage
14418 {
14421 }
14426 {
14477 }
14481 /* Little bit of braindamage here. The SSE compare instructions
14482 does use completely different names for the comparisons that the
14483 fp conditional moves. */
14485 {
14488 {
14491 }
14497 {
14500 }
14506 {
14509 }
14518 {
14521 }
14527 {
14530 }
14536 {
14539 }
14550 }
14555 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
14558 #endif
14563 {
14567 }
14571 file);
14576 {
14580 }
14581 /* It doesn't actually matter what mode we use here, as we're
14582 only going to use this for printing. */
14590 #ifdef HAVE_AS_IX86_HLE
14592 #else
14594 #endif
14596 #ifdef HAVE_AS_IX86_HLE
14598 #else
14600 #endif
14601 /* We do not want to print value of the operand. */
14610 {
14615 else
14618 }
14621 {
14622 rtx x;
14631 {
14636 {
14638 bool cputaken
14641 /* Emit hints only in the case default branch prediction
14642 heuristics would fail. */
14644 {
14645 /* We use 3e (DS) prefix for taken branches and
14646 2e (CS) prefix for not taken branches. */
14649 else
14651 }
14652 }
14653 }
14655 }
14658 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
14660 #endif
14667 /* The kernel uses a different segment register for performance
14668 reasons; a system call would not have to trash the userspace
14669 segment register, which would be expensive. */
14672 else
14687 }
14688 }
14694 {
14695 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
14698 {
14701 {
14710 else
14716 }
14718 /* Check for explicit size override (codes 'b', 'w', 'k',
14719 'q' and 'x') */
14733 }
14736 /* Avoid (%rip) for call operands. */
14742 else
14744 }
14747 {
14748 REAL_VALUE_TYPE r;
14756 /* Sign extend 32bit SFmode immediate to 8 bytes. */
14760 else
14762 }
14765 {
14766 REAL_VALUE_TYPE r;
14775 }
14777 /* These float cases don't actually occur as immediate operands. */
14779 {
14784 }
14786 else
14787 {
14788 /* We have patterns that allow zero sets of memory, for instance.
14789 In 64-bit mode, we should probably support all 8-byte vectors,
14790 since we can in fact encode that into an immediate. */
14792 {
14795 }
14798 {
14800 {
14803 }
14806 {
14809 else
14811 }
14812 }
14817 else
14819 }
14820 }
14822 static bool
14824 {
14827 }
14828 \f
14829 /* Print a memory operand whose address is ADDR. */
14831 static void
14833 {
14842 {
14849 }
14851 {
14855 }
14856 else
14867 {
14878 }
14880 /* Use one byte shorter RIP relative addressing for 64bit mode. */
14882 {
14894 }
14896 {
14897 /* Displacement only requires special attention. */
14900 {
14904 }
14907 else
14909 }
14910 else
14911 {
14912 /* Print SImode register names to force addr32 prefix. */
14914 {
14915 #ifdef ENABLE_CHECKING
14918 {
14929 }
14930 #endif
14933 }
14935 && TARGET_X32
14936 && disp
14939 {
14940 /* X32 runs in 64-bit mode, where displacement, DISP, in
14941 address DISP(%r64), is encoded as 32-bit immediate sign-
14942 extended from 32-bit to 64-bit. For -0x40000300(%r64),
14943 address is %r64 + 0xffffffffbffffd00. When %r64 <
14944 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
14945 which is invalid for x32. The correct address is %r64
14946 - 0x40000300 == 0xf7ffdd64. To properly encode
14947 -0x40000300(%r64) for x32, we zero-extend negative
14948 displacement by forcing addr32 prefix which truncates
14949 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
14950 zero-extend all negative displacements, including -1(%rsp).
14951 However, for small negative displacements, sign-extension
14952 won't cause overflow. We only zero-extend negative
14953 displacements if they < -16*1024*1024, which is also used
14954 to check legitimate address displacements for PIC. */
14956 }
14959 {
14961 {
14966 else
14968 }
14974 {
14979 }
14981 }
14982 else
14983 {
14987 {
14988 /* Pull out the offset of a symbol; print any symbol itself. */
14992 {
14996 }
15004 else
15006 }
15010 {
15013 {
15017 }
15018 }
15021 else
15025 {
15030 }
15032 }
15033 }
15034 }
15036 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
15038 static bool
15040 {
15041 rtx op;
15048 {
15051 /* FIXME: This might be @TPOFF in Sun ld. */
15062 else
15074 else
15081 #if TARGET_MACHO
15087 #endif
15090 {
15095 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
15097 #else
15099 #endif
15102 }
15107 }
15110 }
15111 \f
15112 /* Split one or more double-mode RTL references into pairs of half-mode
15113 references. The RTL can be REG, offsettable MEM, integer constant, or
15114 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
15115 split and "num" is its length. lo_half and hi_half are output arrays
15116 that parallel "operands". */
15118 void
15121 {
15126 {
15135 }
15140 {
15143 /* simplify_subreg refuse to split volatile memory addresses,
15144 but we still have to handle it. */
15146 {
15149 }
15150 else
15151 {
15158 }
15159 }
15160 }
15161 \f
15162 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
15163 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
15164 is the expression of the binary operation. The output may either be
15165 emitted here, or returned to the caller, like all output_* functions.
15167 There is no guarantee that the operands are the same mode, as they
15168 might be within FLOAT or FLOAT_EXTEND expressions. */
15170 #ifndef SYSV386_COMPAT
15171 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
15172 wants to fix the assemblers because that causes incompatibility
15173 with gcc. No-one wants to fix gcc because that causes
15174 incompatibility with assemblers... You can use the option of
15175 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
15176 #define SYSV386_COMPAT 1
15177 #endif
15181 {
15187 #ifdef ENABLE_CHECKING
15188 /* Even if we do not want to check the inputs, this documents input
15189 constraints. Which helps in understanding the following code. */
15199 else
15201 #endif
15204 {
15209 else
15218 else
15227 else
15236 else
15243 }
15246 {
15248 {
15252 else
15254 }
15255 else
15256 {
15260 else
15262 }
15264 }
15268 {
15272 {
15276 }
15278 /* know operands[0] == operands[1]. */
15281 {
15284 }
15287 {
15289 /* How is it that we are storing to a dead operand[2]?
15290 Well, presumably operands[1] is dead too. We can't
15291 store the result to st(0) as st(0) gets popped on this
15292 instruction. Instead store to operands[2] (which I
15293 think has to be st(1)). st(1) will be popped later.
15294 gcc <= 2.8.1 didn't have this check and generated
15295 assembly code that the Unixware assembler rejected. */
15297 else
15300 }
15304 else
15311 {
15314 }
15317 {
15320 }
15323 {
15324 #if SYSV386_COMPAT
15325 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
15326 derived assemblers, confusingly reverse the direction of
15327 the operation for fsub{r} and fdiv{r} when the
15328 destination register is not st(0). The Intel assembler
15329 doesn't have this brain damage. Read !SYSV386_COMPAT to
15330 figure out what the hardware really does. */
15333 else
15335 #else
15337 /* As above for fmul/fadd, we can't store to st(0). */
15339 else
15341 #endif
15343 }
15346 {
15347 #if SYSV386_COMPAT
15350 else
15352 #else
15355 else
15357 #endif
15359 }
15362 {
15365 else
15368 }
15370 {
15371 #if SYSV386_COMPAT
15373 #else
15375 #endif
15376 }
15377 else
15378 {
15379 #if SYSV386_COMPAT
15381 #else
15383 #endif
15384 }
15389 }
15393 }
15395 /* Check if a 256bit AVX register is referenced inside of EXP. */
15397 static int
15399 {
15410 }
15412 /* Return needed mode for entity in optimize_mode_switching pass. */
15414 static int
15416 {
15418 {
15419 rtx link;
15421 /* Needed mode is set to AVX_U128_CLEAN if there are
15422 no 256bit modes used in function arguments. */
15424 link;
15426 {
15428 {
15433 }
15434 }
15437 }
15439 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
15440 changes state only when a 256bit register is written to, but we need
15441 to prevent the compiler from moving optimal insertion point above
15442 eventual read from 256bit register. */
15447 }
15449 /* Return mode that i387 must be switched into
15450 prior to the execution of insn. */
15452 static int
15454 {
15457 /* The mode UNINITIALIZED is used to store control word after a
15458 function call or ASM pattern. The mode ANY specify that function
15459 has no requirements on the control word and make no changes in the
15460 bits we are interested in. */
15474 {
15497 }
15500 }
15502 /* Return mode that entity must be switched into
15503 prior to the execution of insn. */
15505 int
15507 {
15509 {
15519 }
15521 }
15523 /* Check if a 256bit AVX register is referenced in stores. */
15525 static void
15527 {
15529 {
15532 }
15533 }
15535 /* Calculate mode of upper 128bit AVX registers after the insn. */
15537 static int
15539 {
15546 /* We know that state is clean after CALL insn if there are no
15547 256bit registers used in the function return register. */
15549 {
15554 }
15556 /* Otherwise, return current mode. Remember that if insn
15557 references AVX 256bit registers, the mode was already changed
15558 to DIRTY from MODE_NEEDED. */
15560 }
15562 /* Return the mode that an insn results in. */
15564 int
15566 {
15568 {
15578 }
15579 }
15581 static int
15583 {
15584 tree arg;
15586 /* Entry mode is set to AVX_U128_DIRTY if there are
15587 256bit modes used in function arguments. */
15590 {
15595 }
15598 }
15600 /* Return a mode that ENTITY is assumed to be
15601 switched to at function entry. */
15603 int
15605 {
15607 {
15617 }
15618 }
15620 static int
15622 {
15625 /* Exit mode is set to AVX_U128_DIRTY if there are
15626 256bit modes used in the function return register. */
15631 }
15633 /* Return a mode that ENTITY is assumed to be
15634 switched to at function exit. */
15636 int
15638 {
15640 {
15650 }
15651 }
15653 /* Output code to initialize control word copies used by trunc?f?i and
15654 rounding patterns. CURRENT_MODE is set to current control word,
15655 while NEW_MODE is set to new control word. */
15657 static void
15659 {
15661 rtx new_mode;
15672 {
15674 {
15676 /* round toward zero (truncate) */
15682 /* round down toward -oo */
15689 /* round up toward +oo */
15696 /* mask precision exception for nearbyint() */
15703 }
15704 }
15705 else
15706 {
15708 {
15710 /* round toward zero (truncate) */
15716 /* round down toward -oo */
15722 /* round up toward +oo */
15728 /* mask precision exception for nearbyint() */
15735 }
15736 }
15742 }
15744 /* Emit vzeroupper. */
15746 void
15748 {
15751 /* Cancel automatic vzeroupper insertion if there are
15752 live call-saved SSE registers at the insertion point. */
15764 }
15766 /* Generate one or more insns to set ENTITY to MODE. */
15768 void
15770 {
15772 {
15787 }
15788 }
15790 /* Output code for INSN to convert a float to a signed int. OPERANDS
15791 are the insn operands. The output may be [HSD]Imode and the input
15792 operand may be [SDX]Fmode. */
15796 {
15801 /* Jump through a hoop or two for DImode, since the hardware has no
15802 non-popping instruction. We used to do this a different way, but
15803 that was somewhat fragile and broke with post-reload splitters. */
15813 else
15814 {
15819 else
15823 }
15826 }
15828 /* Output code for x87 ffreep insn. The OPNO argument, which may only
15829 have the values zero or one, indicates the ffreep insn's operand
15830 from the OPERANDS array. */
15834 {
15836 #ifdef HAVE_AS_IX86_FFREEP
15838 #else
15839 {
15849 }
15850 #endif
15853 }
15856 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
15857 should be used. UNORDERED_P is true when fucom should be used. */
15861 {
15867 {
15870 }
15871 else
15872 {
15875 }
15878 {
15882 else
15884 else
15887 else
15889 }
15896 {
15898 {
15901 }
15902 else
15904 }
15907 && stack_top_dies
15910 {
15911 /* If both the top of the 387 stack dies, and the other operand
15912 is also a stack register that dies, then this must be a
15913 `fcompp' float compare */
15916 {
15917 /* There is no double popping fcomi variant. Fortunately,
15918 eflags is immune from the fstp's cc clobbering. */
15921 else
15924 }
15925 else
15926 {
15929 else
15931 }
15932 }
15933 else
15934 {
15935 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
15938 {
15946 NULL,
15947 NULL,
15954 NULL,
15955 NULL,
15956 NULL,
15957 NULL
15958 };
15973 }
15974 }
15976 void
15978 {
15981 #ifdef ASM_QUAD
15984 #else
15986 #endif
15989 }
15991 void
15993 {
15996 #ifdef ASM_QUAD
15999 #else
16001 #endif
16002 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
16008 #if TARGET_MACHO
16010 {
16014 }
16015 #endif
16016 else
16019 }
16020 \f
16021 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
16022 for the target. */
16024 void
16026 {
16027 rtx tmp;
16029 /* We play register width games, which are only valid after reload. */
16032 /* Avoid HImode and its attendant prefix byte. */
16037 /* This predicate should match that for movsi_xor and movdi_xor_rex64. */
16039 {
16042 }
16045 }
16047 /* X is an unchanging MEM. If it is a constant pool reference, return
16048 the constant pool rtx, else NULL. */
16050 rtx
16052 {
16059 }
16061 void
16063 {
16071 {
16072 rtx tmp;
16076 {
16082 }
16085 }
16089 {
16092 rtx tmp;
16097 else
16101 {
16108 }
16109 }
16113 {
16115 {
16116 #if TARGET_MACHO
16117 /* dynamic-no-pic */
16119 {
16120 rtx temp = ((reload_in_progress
16128 }
16130 {
16134 }
16137 else
16138 {
16146 }
16147 /* dynamic-no-pic */
16148 #endif
16149 }
16150 else
16151 {
16155 {
16161 }
16162 }
16163 }
16164 else
16165 {
16176 /* Force large constants in 64bit compilation into register
16177 to get them CSEed. */
16189 {
16190 /* If we are loading a floating point constant to a register,
16191 force the value to memory now, since we'll get better code
16192 out the back end. */
16196 {
16201 }
16202 }
16203 }
16206 }
16208 void
16210 {
16214 /* Force constants other than zero into memory. We do not know how
16215 the instructions used to build constants modify the upper 64 bits
16216 of the register, once we have that information we may be able
16217 to handle some of them more efficiently. */
16226 /* We need to check memory alignment for SSE mode since attribute
16227 can make operands unaligned. */
16232 {
16235 /* ix86_expand_vector_move_misalign() does not like constants ... */
16241 /* ... nor both arguments in memory. */
16249 }
16251 /* Make operand1 a register if it isn't already. */
16255 {
16258 }
16261 }
16263 /* Split 32-byte AVX unaligned load and store if needed. */
16265 static void
16267 {
16268 rtx m;
16275 {
16296 }
16299 {
16301 {
16308 }
16309 else
16311 }
16313 {
16315 {
16320 }
16321 else
16323 }
16324 else
16326 }
16328 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
16329 straight to ix86_expand_vector_move. */
16330 /* Code generation for scalar reg-reg moves of single and double precision data:
16331 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
16332 movaps reg, reg
16333 else
16334 movss reg, reg
16335 if (x86_sse_partial_reg_dependency == true)
16336 movapd reg, reg
16337 else
16338 movsd reg, reg
16340 Code generation for scalar loads of double precision data:
16341 if (x86_sse_split_regs == true)
16342 movlpd mem, reg (gas syntax)
16343 else
16344 movsd mem, reg
16346 Code generation for unaligned packed loads of single precision data
16347 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
16348 if (x86_sse_unaligned_move_optimal)
16349 movups mem, reg
16351 if (x86_sse_partial_reg_dependency == true)
16352 {
16353 xorps reg, reg
16354 movlps mem, reg
16355 movhps mem+8, reg
16356 }
16357 else
16358 {
16359 movlps mem, reg
16360 movhps mem+8, reg
16361 }
16363 Code generation for unaligned packed loads of double precision data
16364 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
16365 if (x86_sse_unaligned_move_optimal)
16366 movupd mem, reg
16368 if (x86_sse_split_regs == true)
16369 {
16370 movlpd mem, reg
16371 movhpd mem+8, reg
16372 }
16373 else
16374 {
16375 movsd mem, reg
16376 movhpd mem+8, reg
16377 }
16378 */
16380 void
16382 {
16390 {
16392 {
16397 /* FALLTHRU */
16405 }
16408 }
16411 {
16412 /* ??? If we have typed data, then it would appear that using
16413 movdqu is the only way to get unaligned data loaded with
16414 integer type. */
16416 {
16419 /* We will eventually emit movups based on insn attributes. */
16421 }
16423 {
16424 rtx zero;
16427 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
16428 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16430 {
16431 /* We will eventually emit movups based on insn attributes. */
16434 }
16436 /* When SSE registers are split into halves, we can avoid
16437 writing to the top half twice. */
16439 {
16442 }
16443 else
16444 {
16445 /* ??? Not sure about the best option for the Intel chips.
16446 The following would seem to satisfy; the register is
16447 entirely cleared, breaking the dependency chain. We
16448 then store to the upper half, with a dependency depth
16449 of one. A rumor has it that Intel recommends two movsd
16450 followed by an unpacklpd, but this is unconfirmed. And
16451 given that the dependency depth of the unpacklpd would
16452 still be one, I'm not sure why this would be better. */
16454 }
16460 }
16461 else
16462 {
16464 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
16465 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16467 {
16472 }
16476 else
16486 }
16487 }
16489 {
16491 {
16494 /* We will eventually emit movups based on insn attributes. */
16496 }
16498 {
16500 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16501 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16503 /* We will eventually emit movups based on insn attributes. */
16505 else
16506 {
16511 }
16512 }
16513 else
16514 {
16519 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
16520 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16522 {
16525 }
16526 else
16527 {
16532 }
16533 }
16534 }
16535 else
16537 }
16539 /* Expand a push in MODE. This is some mode for which we do not support
16540 proper push instructions, at least from the registers that we expect
16541 the value to live in. */
16543 void
16545 {
16546 rtx tmp;
16556 /* When we push an operand onto stack, it has to be aligned at least
16557 at the function argument boundary. However since we don't have
16558 the argument type, we can't determine the actual argument
16559 boundary. */
16561 }
16563 /* Helper function of ix86_fixup_binary_operands to canonicalize
16564 operand order. Returns true if the operands should be swapped. */
16566 static bool
16568 rtx operands[])
16569 {
16574 /* If the operation is not commutative, we can't do anything. */
16578 /* Highest priority is that src1 should match dst. */
16584 /* Next highest priority is that immediate constants come second. */
16590 /* Lowest priority is that memory references should come second. */
16597 }
16600 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
16601 destination to use for the operation. If different from the true
16602 destination in operands[0], a copy operation will be required. */
16604 rtx
16606 rtx operands[])
16607 {
16612 /* Canonicalize operand order. */
16614 {
16615 rtx temp;
16617 /* It is invalid to swap operands of different modes. */
16623 }
16625 /* Both source operands cannot be in memory. */
16627 {
16628 /* Optimization: Only read from memory once. */
16630 {
16633 }
16634 else
16636 }
16638 /* If the destination is memory, and we do not have matching source
16639 operands, do things in registers. */
16643 /* Source 1 cannot be a constant. */
16647 /* Source 1 cannot be a non-matching memory. */
16651 /* Improve address combine. */
16660 }
16662 /* Similarly, but assume that the destination has already been
16663 set up properly. */
16665 void
16668 {
16671 }
16673 /* Attempt to expand a binary operator. Make the expansion closer to the
16674 actual machine, then just general_operand, which will allow 3 separate
16675 memory references (one output, two input) in a single insn. */
16677 void
16679 rtx operands[])
16680 {
16687 /* Emit the instruction. */
16691 {
16692 /* Reload doesn't know about the flags register, and doesn't know that
16693 it doesn't want to clobber it. We can only do this with PLUS. */
16696 }
16700 {
16701 /* This is going to be an LEA; avoid splitting it later. */
16703 }
16704 else
16705 {
16708 }
16710 /* Fix up the destination if needed. */
16713 }
16715 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
16716 the given OPERANDS. */
16718 void
16720 rtx operands[])
16721 {
16724 {
16727 }
16729 {
16732 }
16733 /* Optimize (__m128i) d | (__m128i) e and similar code
16734 when d and e are float vectors into float vector logical
16735 insn. In C/C++ without using intrinsics there is no other way
16736 to express vector logical operation on float vectors than
16737 to cast them temporarily to integer vectors. */
16739 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
16748 {
16749 rtx dst;
16751 {
16758 {
16761 }
16762 else
16763 {
16768 }
16779 }
16780 }
16789 }
16791 /* Return TRUE or FALSE depending on whether the binary operator meets the
16792 appropriate constraints. */
16794 bool
16797 {
16802 /* Both source operands cannot be in memory. */
16806 /* Canonicalize operand order for commutative operators. */
16808 {
16812 }
16814 /* If the destination is memory, we must have a matching source operand. */
16818 /* Source 1 cannot be a constant. */
16822 /* Source 1 cannot be a non-matching memory. */
16824 /* Support "andhi/andsi/anddi" as a zero-extending move. */
16832 }
16834 /* Attempt to expand a unary operator. Make the expansion closer to the
16835 actual machine, then just general_operand, which will allow 2 separate
16836 memory references (one output, one input) in a single insn. */
16838 void
16840 rtx operands[])
16841 {
16848 /* If the destination is memory, and we do not have matching source
16849 operands, do things in registers. */
16852 {
16855 else
16857 }
16859 /* When source operand is memory, destination must match. */
16863 /* Emit the instruction. */
16867 {
16868 /* Reload doesn't know about the flags register, and doesn't know that
16869 it doesn't want to clobber it. */
16872 }
16873 else
16874 {
16877 }
16879 /* Fix up the destination if needed. */
16882 }
16884 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
16885 divisor are within the range [0-255]. */
16887 void
16890 {
16899 {
16912 }
16919 /* Use 8bit unsigned divimod if dividend and divisor are within
16920 the range [0-255]. */
16929 pc_rtx);
16934 /* Generate original signed/unsigned divimod. */
16939 /* Branch to the end. */
16943 /* Generate 8bit unsigned divide. */
16945 /* Don't use operands[0] for result of 8bit divide since not all
16946 registers support QImode ZERO_EXTRACT. */
16953 {
16956 }
16957 else
16958 {
16961 }
16963 /* Extract remainder from AH. */
16967 else
16968 {
16969 /* Need a new scratch register since the old one has result
16970 of 8bit divide. */
16974 }
16977 /* Zero extend quotient from AL. */
16983 }
16985 #define LEA_MAX_STALL (3)
16986 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
16988 /* Increase given DISTANCE in half-cycles according to
16989 dependencies between PREV and NEXT instructions.
16990 Add 1 half-cycle if there is no dependency and
16991 go to next cycle if there is some dependecy. */
16993 static unsigned int
16995 {
17012 }
17014 /* Function checks if instruction INSN defines register number
17015 REGNO1 or REGNO2. */
17017 static bool
17019 rtx insn)
17020 {
17028 {
17030 }
17033 }
17035 /* Function checks if instruction INSN uses register number
17036 REGNO as a part of address expression. */
17038 static bool
17040 {
17048 }
17050 /* Search backward for non-agu definition of register number REGNO1
17051 or register number REGNO2 in basic block starting from instruction
17052 START up to head of basic block or instruction INSN.
17054 Function puts true value into *FOUND var if definition was found
17055 and false otherwise.
17057 Distance in half-cycles between START and found instruction or head
17058 of BB is added to DISTANCE and returned. */
17060 static int
17064 {
17074 {
17076 {
17079 {
17082 {
17085 }
17086 }
17089 }
17094 }
17097 }
17099 /* Search backward for non-agu definition of register number REGNO1
17100 or register number REGNO2 in INSN's basic block until
17101 1. Pass LEA_SEARCH_THRESHOLD instructions, or
17102 2. Reach neighbour BBs boundary, or
17103 3. Reach agu definition.
17104 Returns the distance between the non-agu definition point and INSN.
17105 If no definition point, returns -1. */
17107 static int
17109 rtx insn)
17110 {
17121 {
17122 edge e;
17123 edge_iterator ei;
17128 {
17131 }
17137 else
17138 {
17143 {
17144 int bb_dist
17150 {
17157 }
17158 }
17161 }
17162 }
17164 /* get_attr_type may modify recog data. We want to make sure
17165 that recog data is valid for instruction INSN, on which
17166 distance_non_agu_define is called. INSN is unchanged here. */
17173 }
17175 /* Return the distance in half-cycles between INSN and the next
17176 insn that uses register number REGNO in memory address added
17177 to DISTANCE. Return -1 if REGNO0 is set.
17179 Put true value into *FOUND if register usage was found and
17180 false otherwise.
17181 Put true value into *REDEFINED if register redefinition was
17182 found and false otherwise. */
17184 static int
17188 {
17199 {
17201 {
17204 {
17205 /* Return DISTANCE if OP0 is used in memory
17206 address in NEXT. */
17209 }
17212 {
17213 /* Return -1 if OP0 is set in NEXT. */
17216 }
17219 }
17225 }
17228 }
17230 /* Return the distance between INSN and the next insn that uses
17231 register number REGNO0 in memory address. Return -1 if no such
17232 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
17234 static int
17236 {
17248 {
17249 edge e;
17250 edge_iterator ei;
17255 {
17258 }
17264 else
17265 {
17271 {
17272 int bb_dist
17277 {
17284 }
17285 }
17288 }
17289 }
17295 }
17297 /* Define this macro to tune LEA priority vs ADD, it take effect when
17298 there is a dilemma of choicing LEA or ADD
17299 Negative value: ADD is more preferred than LEA
17300 Zero: Netrual
17301 Positive value: LEA is more preferred than ADD*/
17302 #define IX86_LEA_PRIORITY 0
17304 /* Return true if usage of lea INSN has performance advantage
17305 over a sequence of instructions. Instructions sequence has
17306 SPLIT_COST cycles higher latency than lea latency. */
17308 static bool
17311 {
17318 {
17319 /* If there is no non AGU operand definition, no AGU
17320 operand usage and split cost is 0 then both lea
17321 and non lea variants have same priority. Currently
17322 we prefer lea for 64 bit code and non lea on 32 bit
17323 code. */
17326 else
17328 }
17330 /* With longer definitions distance lea is more preferable.
17331 Here we change it to take into account splitting cost and
17332 lea priority. */
17335 /* If there is no use in memory addess then we just check
17336 that split cost exceeds AGU stall. */
17340 /* If this insn has both backward non-agu dependence and forward
17341 agu dependence, the one with short distance takes effect. */
17343 }
17345 /* Return true if it is legal to clobber flags by INSN and
17346 false otherwise. */
17348 static bool
17350 {
17353 bitmap live;
17356 {
17358 {
17365 }
17371 }
17375 }
17377 /* Return true if we need to split op0 = op1 + op2 into a sequence of
17378 move and add to avoid AGU stalls. */
17380 bool
17382 {
17385 /* Check if we need to optimize. */
17389 /* Check it is correct to split here. */
17397 /* We need to split only adds with non destructive
17398 destination operand. */
17401 else
17403 }
17405 /* Return true if we should emit lea instruction instead of mov
17406 instruction. */
17408 bool
17410 {
17413 /* Check if we need to optimize. */
17417 /* Use lea for reg to reg moves only. */
17425 }
17427 /* Return true if we need to split lea into a sequence of
17428 instructions to avoid AGU stalls. */
17430 bool
17432 {
17438 /* Check we need to optimize. */
17442 /* Check it is correct to split here. */
17449 /* There should be at least two components in the address. */
17454 /* We should not split into add if non legitimate pic
17455 operand is used as displacement. */
17470 /* Compute how many cycles we will add to execution time
17471 if split lea into a sequence of instructions. */
17473 {
17474 /* Have to use mov instruction if non desctructive
17475 destination form is used. */
17479 /* Have to add index to base if both exist. */
17483 /* Have to use shift and adds if scale is 2 or greater. */
17485 {
17490 else
17492 }
17494 /* Have to use add instruction with immediate if
17495 disp is non zero. */
17499 /* Subtract the price of lea. */
17501 }
17504 }
17506 /* Emit x86 binary operand CODE in mode MODE, where the first operand
17507 matches destination. RTX includes clobber of FLAGS_REG. */
17509 static void
17512 {
17519 }
17521 /* Return true if regno1 def is nearest to the insn. */
17523 static bool
17525 {
17532 {
17534 {
17537 }
17543 }
17545 /* None of the regs is defined in the bb. */
17547 }
17549 /* Split lea instructions into a sequence of instructions
17550 which are executed on ALU to avoid AGU stalls.
17551 It is assumed that it is allowed to clobber flags register
17552 at lea position. */
17554 void
17556 {
17572 {
17575 }
17578 {
17581 }
17587 {
17588 /* Case r1 = r1 + ... */
17590 {
17591 /* If we have a case r1 = r1 + C * r1 then we
17592 should use multiplication which is very
17593 expensive. Assume cost model is wrong if we
17594 have such case here. */
17599 }
17600 else
17601 {
17602 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
17606 /* Use shift for scaling. */
17615 }
17616 }
17618 {
17621 }
17622 else
17623 {
17625 {
17628 }
17630 {
17633 }
17634 else
17635 {
17640 else
17641 {
17642 rtx tmp1;
17644 /* Find better operand for SET instruction, depending
17645 on which definition is farther from the insn. */
17648 else
17658 }
17661 }
17665 }
17666 }
17668 /* Return true if it is ok to optimize an ADD operation to LEA
17669 operation to avoid flag register consumation. For most processors,
17670 ADD is faster than LEA. For the processors like ATOM, if the
17671 destination register of LEA holds an actual address which will be
17672 used soon, LEA is better and otherwise ADD is better. */
17674 bool
17676 {
17681 /* If a = b + c, (a!=b && a!=c), must use lea form. */
17689 }
17691 /* Return true if destination reg of SET_BODY is shift count of
17692 USE_BODY. */
17694 static bool
17696 {
17697 rtx set_dest;
17698 rtx shift_rtx;
17701 /* Retrieve destination of SET_BODY. */
17703 {
17712 use_body))
17717 }
17719 /* Retrieve shift count of USE_BODY. */
17721 {
17733 }
17741 {
17744 /* Return true if shift count is dest of SET_BODY. */
17746 {
17747 /* Add check since it can be invoked before register
17748 allocation in pre-reload schedule. */
17754 }
17755 }
17758 }
17760 /* Return true if destination reg of SET_INSN is shift count of
17761 USE_INSN. */
17763 bool
17765 {
17768 }
17770 /* Return TRUE or FALSE depending on whether the unary operator meets the
17771 appropriate constraints. */
17773 bool
17777 {
17778 /* If one of operands is memory, source and destination must match. */
17784 }
17786 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
17787 are ok, keeping in mind the possible movddup alternative. */
17789 bool
17791 {
17797 }
17799 /* Post-reload splitter for converting an SF or DFmode value in an
17800 SSE register into an unsigned SImode. */
17802 void
17804 {
17815 /* Load up the value into the low element. We must ensure that the other
17816 elements are valid floats -- zero is the easiest such value. */
17818 {
17821 else
17823 }
17824 else
17825 {
17830 else
17832 }
17852 else
17857 }
17859 /* Convert an unsigned DImode value into a DFmode, using only SSE.
17860 Expects the 64-bit DImode to be supplied in a pair of integral
17861 registers. Requires SSE2; will use SSE3 if available. For x86_32,
17862 -mfpmath=sse, !optimize_size only. */
17864 void
17866 {
17870 rtx x;
17876 {
17879 }
17880 else
17881 {
17885 }
17893 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
17896 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
17897 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
17898 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
17899 (0x1.0p84 + double(fp_value_hi_xmm)).
17900 Note these exponents differ by 32. */
17904 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
17905 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
17914 /* Add the upper and lower DFmode values together. */
17917 else
17918 {
17922 }
17925 }
17927 /* Not used, but eases macroization of patterns. */
17928 void
17930 rtx input ATTRIBUTE_UNUSED)
17931 {
17933 }
17935 /* Convert an unsigned SImode value into a DFmode. Only currently used
17936 for SSE, but applicable anywhere. */
17938 void
17940 {
17941 REAL_VALUE_TYPE TWO31r;
17956 }
17958 /* Convert a signed DImode value into a DFmode. Only used for SSE in
17959 32-bit mode; otherwise we have a direct convert instruction. */
17961 void
17963 {
17964 REAL_VALUE_TYPE TWO32r;
17982 }
17984 /* Convert an unsigned SImode value into a SFmode, using only SSE.
17985 For x86_32, -mfpmath=sse, !optimize_size only. */
17986 void
17988 {
17989 REAL_VALUE_TYPE ONE16r;
18008 }
18010 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
18011 a vector of unsigned ints VAL to vector of floats TARGET. */
18013 void
18015 {
18017 REAL_VALUE_TYPE TWO16r;
18024 else
18029 OPTAB_DIRECT);
18040 OPTAB_DIRECT);
18042 OPTAB_DIRECT);
18045 }
18047 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
18048 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
18049 This is done by doing just signed conversion if < 0x1p31, and otherwise by
18050 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
18052 rtx
18054 {
18055 REAL_VALUE_TYPE TWO31r;
18070 {
18076 }
18085 OPTAB_DIRECT);
18086 else
18087 {
18093 OPTAB_DIRECT);
18094 }
18097 }
18099 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
18100 then replicate the value for all elements of the vector
18101 register. */
18103 rtx
18105 {
18107 rtvec v;
18111 {
18138 }
18139 }
18141 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
18142 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
18143 for an SSE register. If VECT is true, then replicate the mask for
18144 all elements of the vector register. If INVERT is true, then create
18145 a mask excluding the sign bit. */
18147 rtx
18149 {
18153 rtx v;
18154 rtx mask;
18156 /* Find the sign bit, sign extended to 2*HWI. */
18158 {
18178 else
18186 {
18189 }
18190 else
18191 {
18192 rtvec vec;
18198 {
18201 }
18202 else
18212 }
18217 }
18222 /* Force this value into the low part of a fp vector constant. */
18231 }
18233 /* Generate code for floating point ABS or NEG. */
18235 void
18237 rtx operands[])
18238 {
18249 {
18255 }
18257 /* NEG and ABS performed with SSE use bitwise mask operations.
18258 Create the appropriate mask now. */
18261 else
18271 {
18273 rtvec par;
18278 else
18279 {
18282 }
18284 }
18285 else
18287 }
18289 /* Expand a copysign operation. Special case operand 0 being a constant. */
18291 void
18293 {
18307 else
18311 {
18318 {
18321 else
18322 {
18326 }
18327 }
18337 else
18341 }
18342 else
18343 {
18353 else
18357 }
18358 }
18360 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
18361 be a constant, and so has already been expanded into a vector constant. */
18363 void
18365 {
18381 {
18384 }
18385 }
18387 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
18388 so we have to do two masks. */
18390 void
18392 {
18407 {
18408 /* Shouldn't happen often (it's useless, obviously), but when it does
18409 we'd generate incorrect code if we continue below. */
18412 }
18415 {
18426 }
18427 else
18428 {
18430 {
18432 }
18434 {
18438 }
18442 {
18445 }
18447 {
18452 }
18454 }
18458 }
18460 /* Return TRUE or FALSE depending on whether the first SET in INSN
18461 has source and destination with matching CC modes, and that the
18462 CC mode is at least as constrained as REQ_MODE. */
18464 bool
18466 {
18467 rtx set;
18478 {
18488 /* FALLTHRU */
18492 /* FALLTHRU */
18496 /* FALLTHRU */
18510 }
18513 }
18515 /* Generate insn patterns to do an integer compare of OPERANDS. */
18517 static rtx
18519 {
18526 /* This is very simple, but making the interface the same as in the
18527 FP case makes the rest of the code easier. */
18531 /* Return the test that should be put into the flags user, i.e.
18532 the bcc, scc, or cmov instruction. */
18534 }
18536 /* Figure out whether to use ordered or unordered fp comparisons.
18537 Return the appropriate mode to use. */
18539 enum machine_mode
18541 {
18542 /* ??? In order to make all comparisons reversible, we do all comparisons
18543 non-trapping when compiling for IEEE. Once gcc is able to distinguish
18544 all forms trapping and nontrapping comparisons, we can make inequality
18545 comparisons trapping again, since it results in better code when using
18546 FCOM based compares. */
18548 }
18550 enum machine_mode
18552 {
18556 {
18559 }
18562 {
18563 /* Only zero flag is needed. */
18567 /* Codes needing carry flag. */
18570 /* Detect overflow checks. They need just the carry flag. */
18574 else
18578 /* Detect overflow checks. They need just the carry flag. */
18582 else
18584 /* Codes possibly doable only with sign flag when
18585 comparing against zero. */
18590 else
18591 /* For other cases Carry flag is not required. */
18593 /* Codes doable only with sign flag when comparing
18594 against zero, but we miss jump instruction for it
18595 so we need to use relational tests against overflow
18596 that thus needs to be zero. */
18601 else
18603 /* strcmp pattern do (use flags) and combine may ask us for proper
18604 mode. */
18609 }
18610 }
18612 /* Return the fixed registers used for condition codes. */
18614 static bool
18616 {
18620 }
18622 /* If two condition code modes are compatible, return a condition code
18623 mode which is compatible with both. Otherwise, return
18624 VOIDmode. */
18626 static enum machine_mode
18628 {
18645 {
18659 {
18673 }
18677 /* These are only compatible with themselves, which we already
18678 checked above. */
18680 }
18681 }
18684 /* Return a comparison we can do and that it is equivalent to
18685 swap_condition (code) apart possibly from orderedness.
18686 But, never change orderedness if TARGET_IEEE_FP, returning
18687 UNKNOWN in that case if necessary. */
18689 static enum rtx_code
18691 {
18693 {
18704 }
18705 }
18707 /* Return cost of comparison CODE using the best strategy for performance.
18708 All following functions do use number of instructions as a cost metrics.
18709 In future this should be tweaked to compute bytes for optimize_size and
18710 take into account performance of various instructions on various CPUs. */
18712 static int
18714 {
18717 /* The cost of code using bit-twiddling on %ah. */
18719 {
18742 }
18745 {
18752 }
18753 }
18755 /* Return strategy to use for floating-point. We assume that fcomi is always
18756 preferrable where available, since that is also true when looking at size
18757 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
18759 enum ix86_fpcmp_strategy
18761 {
18762 /* Do fcomi/sahf based test when profitable. */
18771 }
18773 /* Swap, force into registers, or otherwise massage the two operands
18774 to a fp comparison. The operands are updated in place; the new
18775 comparison code is returned. */
18777 static enum rtx_code
18779 {
18785 /* All of the unordered compare instructions only work on registers.
18786 The same is true of the fcomi compare instructions. The XFmode
18787 compare instructions require registers except when comparing
18788 against zero or when converting operand 1 from fixed point to
18789 floating point. */
18798 {
18801 }
18802 else
18803 {
18804 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
18805 things around if they appear profitable, otherwise force op0
18806 into a register. */
18812 {
18815 {
18816 rtx tmp;
18819 }
18820 }
18826 {
18831 {
18834 }
18835 else
18837 }
18838 }
18840 /* Try to rearrange the comparison to make it cheaper. */
18844 {
18845 rtx tmp;
18850 }
18855 }
18857 /* Convert comparison codes we use to represent FP comparison to integer
18858 code that will result in proper branch. Return UNKNOWN if no such code
18859 is available. */
18861 enum rtx_code
18863 {
18865 {
18888 }
18889 }
18891 /* Generate insn patterns to do a floating point compare of OPERANDS. */
18893 static rtx
18895 {
18902 /* Do fcomi/sahf based test when profitable. */
18904 {
18909 tmp);
18917 tmp);
18926 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
18933 /* In the unordered case, we have to check C2 for NaN's, which
18934 doesn't happen to work out to anything nice combination-wise.
18935 So do some bit twiddling on the value we've got in AH to come
18936 up with an appropriate set of condition codes. */
18940 {
18944 {
18947 }
18948 else
18949 {
18955 }
18960 {
18965 }
18966 else
18967 {
18970 }
18975 {
18978 }
18979 else
18980 {
18984 }
18989 {
18995 }
18996 else
18997 {
19000 }
19005 {
19010 }
19011 else
19012 {
19015 }
19020 {
19025 }
19026 else
19027 {
19030 }
19044 }
19049 }
19051 /* Return the test that should be put into the flags user, i.e.
19052 the bcc, scc, or cmov instruction. */
19055 const0_rtx);
19056 }
19058 static rtx
19060 {
19061 rtx ret;
19067 {
19070 }
19071 else
19075 }
19077 void
19079 {
19081 rtx tmp;
19084 {
19091 simple:
19095 pc_rtx);
19103 /* Expand DImode branch into multiple compare+branch. */
19104 {
19110 {
19113 }
19120 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
19121 avoid two branches. This costs one extra insn, so disable when
19122 optimizing for size. */
19127 {
19145 }
19147 /* Otherwise, if we are doing less-than or greater-or-equal-than,
19148 op1 is a constant and the low word is zero, then we can just
19149 examine the high word. Similarly for low word -1 and
19150 less-or-equal-than or greater-than. */
19154 {
19157 {
19160 }
19164 {
19167 }
19171 }
19173 /* Otherwise, we need two or three jumps. */
19182 {
19196 }
19198 /*
19199 * a < b =>
19200 * if (hi(a) < hi(b)) goto true;
19201 * if (hi(a) > hi(b)) goto false;
19202 * if (lo(a) < lo(b)) goto true;
19203 * false:
19204 */
19216 }
19221 }
19222 }
19224 /* Split branch based on floating point condition. */
19225 void
19228 {
19229 rtx condition;
19230 rtx i;
19233 {
19238 }
19241 tmp);
19243 /* Remove pushed operand from stack. */
19253 }
19255 void
19257 {
19258 rtx ret;
19265 }
19267 /* Expand comparison setting or clearing carry flag. Return true when
19268 successful and set pop for the operation. */
19269 static bool
19271 {
19275 /* Do not handle double-mode compares that go through special path. */
19280 {
19285 /* Shortcut: following common codes never translate
19286 into carry flag compares. */
19291 /* These comparisons require zero flag; swap operands so they won't. */
19294 {
19299 }
19301 /* Try to expand the comparison and verify that we end up with
19302 carry flag based comparison. This fails to be true only when
19303 we decide to expand comparison using arithmetic that is not
19304 too common scenario. */
19313 else
19322 }
19328 {
19333 /* Convert a==0 into (unsigned)a<1. */
19342 /* Convert a>b into b<a or a>=b-1. */
19346 {
19348 /* Bail out on overflow. We still can swap operands but that
19349 would force loading of the constant into register. */
19354 }
19355 else
19356 {
19361 }
19364 /* Convert a>=0 into (unsigned)a<0x80000000. */
19382 }
19383 /* Swapping operands may cause constant to appear as first operand. */
19385 {
19389 }
19393 }
19395 bool
19397 {
19421 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
19422 HImode insns, we'd be swallowed in word prefix ops. */
19428 {
19432 HOST_WIDE_INT diff;
19435 /* Sign bit compares are better done using shifts than we do by using
19436 sbb. */
19439 {
19440 /* Detect overlap between destination and compare sources. */
19444 {
19445 rtx flags;
19454 {
19456 compare_code
19458 }
19460 /* To simplify rest of code, restrict to the GEU case. */
19462 {
19468 }
19469 else
19470 {
19473 reverse_condition_maybe_unordered
19475 else
19478 }
19487 else
19490 }
19491 else
19492 {
19495 else
19496 {
19501 }
19503 }
19506 {
19507 /*
19508 * cmpl op0,op1
19509 * sbbl dest,dest
19510 * [addl dest, ct]
19511 *
19512 * Size 5 - 8.
19513 */
19518 }
19520 {
19521 /*
19522 * cmpl op0,op1
19523 * sbbl dest,dest
19524 * orl $ct, dest
19525 *
19526 * Size 8.
19527 */
19531 }
19533 {
19534 /*
19535 * cmpl op0,op1
19536 * sbbl dest,dest
19537 * notl dest
19538 * [addl dest, cf]
19539 *
19540 * Size 8 - 11.
19541 */
19547 }
19548 else
19549 {
19550 /*
19551 * cmpl op0,op1
19552 * sbbl dest,dest
19553 * [notl dest]
19554 * andl cf - ct, dest
19555 * [addl dest, ct]
19556 *
19557 * Size 8 - 11.
19558 */
19561 {
19565 }
19575 }
19581 }
19584 {
19587 HOST_WIDE_INT tmp;
19592 {
19595 /* We may be reversing unordered compare to normal compare, that
19596 is not valid in general (we may convert non-trapping condition
19597 to trapping one), however on i386 we currently emit all
19598 comparisons unordered. */
19601 }
19602 else
19603 {
19606 }
19607 }
19612 {
19617 {
19622 }
19623 }
19625 /* Optimize dest = (op0 < 0) ? -1 : cf. */
19629 {
19630 /* If lea code below could be used, only optimize
19631 if it results in a 2 insn sequence. */
19637 {
19638 /*
19639 * notl op1 (if necessary)
19640 * sarl $31, op1
19641 * orl cf, op1
19642 */
19644 {
19648 }
19659 }
19660 }
19668 {
19669 /*
19670 * xorl dest,dest
19671 * cmpl op1,op2
19672 * setcc dest
19673 * lea cf(dest*(ct-cf)),dest
19674 *
19675 * Size 14.
19676 *
19677 * This also catches the degenerate setcc-only case.
19678 */
19680 rtx tmp;
19686 /* On x86_64 the lea instruction operates on Pmode, so we need
19687 to get arithmetics done in proper mode to match. */
19690 else
19691 {
19692 rtx out1;
19695 nops++;
19697 {
19699 nops++;
19700 }
19701 }
19703 {
19705 nops++;
19706 }
19708 {
19711 else
19713 }
19718 }
19720 /*
19721 * General case: Jumpful:
19722 * xorl dest,dest cmpl op1, op2
19723 * cmpl op1, op2 movl ct, dest
19724 * setcc dest jcc 1f
19725 * decl dest movl cf, dest
19726 * andl (cf-ct),dest 1:
19727 * addl ct,dest
19728 *
19729 * Size 20. Size 14.
19730 *
19731 * This is reasonably steep, but branch mispredict costs are
19732 * high on modern cpus, so consider failing only if optimizing
19733 * for space.
19734 */
19739 {
19741 {
19748 {
19751 /* We may be reversing unordered compare to normal compare,
19752 that is not valid in general (we may convert non-trapping
19753 condition to trapping one), however on i386 we currently
19754 emit all comparisons unordered. */
19756 }
19757 else
19758 {
19762 }
19763 }
19766 {
19767 /* notl op1 (if needed)
19768 sarl $31, op1
19769 andl (cf-ct), op1
19770 addl ct, op1
19772 For x < 0 (resp. x <= -1) there will be no notl,
19773 so if possible swap the constants to get rid of the
19774 complement.
19775 True/false will be -1/0 while code below (store flag
19776 followed by decrement) is 0/-1, so the constants need
19777 to be exchanged once more. */
19780 {
19783 }
19784 else
19785 {
19789 }
19792 }
19793 else
19794 {
19798 constm1_rtx,
19800 }
19812 }
19813 }
19816 {
19817 /* Try a few things more with specific constants and a variable. */
19819 optab op;
19825 /* If one of the two operands is an interesting constant, load a
19826 constant with the above and mask it in with a logical operation. */
19829 {
19835 else
19837 }
19839 {
19845 else
19847 }
19848 else
19855 /* Recurse to get the constant loaded. */
19859 /* Mask in the interesting variable. */
19861 OPTAB_WIDEN);
19866 }
19868 /*
19869 * For comparison with above,
19870 *
19871 * movl cf,dest
19872 * movl ct,tmp
19873 * cmpl op1,op2
19874 * cmovcc tmp,dest
19875 *
19876 * Size 15.
19877 */
19899 }
19901 /* Swap, force into registers, or otherwise massage the two operands
19902 to an sse comparison with a mask result. Thus we differ a bit from
19903 ix86_prepare_fp_compare_args which expects to produce a flags result.
19905 The DEST operand exists to help determine whether to commute commutative
19906 operators. The POP0/POP1 operands are updated in place. The new
19907 comparison code is returned, or UNKNOWN if not implementable. */
19909 static enum rtx_code
19912 {
19913 rtx tmp;
19916 {
19919 /* AVX supports all the needed comparisons. */
19922 /* We have no LTGT as an operator. We could implement it with
19923 NE & ORDERED, but this requires an extra temporary. It's
19924 not clear that it's worth it. */
19931 /* These are supported directly. */
19938 /* AVX has 3 operand comparisons, no need to swap anything. */
19941 /* For commutative operators, try to canonicalize the destination
19942 operand to be first in the comparison - this helps reload to
19943 avoid extra moves. */
19946 /* FALLTHRU */
19952 /* These are not supported directly before AVX, and furthermore
19953 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
19954 comparison operands to transform into something that is
19955 supported. */
19964 }
19967 }
19969 /* Detect conditional moves that exactly match min/max operational
19970 semantics. Note that this is IEEE safe, as long as we don't
19971 interchange the operands.
19973 Returns FALSE if this conditional move doesn't match a MIN/MAX,
19974 and TRUE if the operation is successful and instructions are emitted. */
19976 static bool
19979 {
19982 rtx tmp;
19985 ;
19987 {
19991 }
19992 else
19999 else
20004 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
20005 but MODE may be a vector mode and thus not appropriate. */
20007 {
20009 rtvec v;
20014 }
20015 else
20016 {
20019 }
20023 }
20025 /* Expand an sse vector comparison. Return the register with the result. */
20027 static rtx
20030 {
20033 rtx x;
20046 {
20049 }
20050 else
20054 }
20056 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
20057 operations. This is used for both scalar and vector conditional moves. */
20059 static void
20061 {
20067 {
20069 }
20071 {
20075 }
20077 {
20082 }
20084 {
20088 }
20090 {
20098 op_true,
20099 op_false)));
20100 }
20101 else
20102 {
20111 {
20125 {
20131 }
20146 {
20152 }
20156 }
20160 else
20161 {
20167 else
20179 }
20180 }
20181 }
20183 /* Expand a floating-point conditional move. Return true if successful. */
20185 bool
20187 {
20195 {
20198 /* Since we've no cmove for sse registers, don't force bad register
20199 allocation just to gain access to it. Deny movcc when the
20200 comparison mode doesn't match the move mode. */
20219 }
20226 /* The floating point conditional move instructions don't directly
20227 support conditions resulting from a signed integer comparison. */
20231 {
20236 }
20243 }
20245 /* Expand a floating-point vector conditional move; a vcond operation
20246 rather than a movcc operation. */
20248 bool
20250 {
20252 rtx cmp;
20257 {
20258 rtx temp;
20260 {
20277 }
20279 OPTAB_DIRECT);
20282 }
20292 }
20294 /* Expand a signed/unsigned integral vector conditional move. */
20296 bool
20298 {
20308 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
20309 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
20318 {
20322 {
20328 }
20331 {
20337 }
20338 }
20347 /* XOP supports all of the comparisons on all 128-bit vector int types. */
20351 ;
20352 else
20353 {
20354 /* Canonicalize the comparison to EQ, GT, GTU. */
20356 {
20373 /* FALLTHRU */
20383 }
20385 /* Only SSE4.1/SSE4.2 supports V2DImode. */
20387 {
20389 {
20391 /* SSE4.1 supports EQ. */
20398 /* SSE4.2 supports GT/GTU. */
20405 }
20406 }
20408 /* Unsigned parallel compare is not supported by the hardware.
20409 Play some tricks to turn this into a signed comparison
20410 against 0. */
20412 {
20416 {
20421 {
20426 {
20433 }
20434 /* Subtract (-(INT MAX) - 1) from both operands to make
20435 them signed. */
20446 }
20453 /* Perform a parallel unsigned saturating subtraction. */
20466 }
20467 }
20468 }
20470 /* Allow the comparison to be done in one mode, but the movcc to
20471 happen in another mode. */
20473 {
20476 }
20477 else
20478 {
20484 }
20489 }
20491 /* Expand a variable vector permutation. */
20493 void
20495 {
20506 /* Number of elements in the vector. */
20512 {
20514 {
20515 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
20516 an constant shuffle operand. With a tiny bit of effort we can
20517 use VPERMD instead. A re-interpretation stall for V4DFmode is
20518 unfortunate but there's no avoiding it.
20519 Similarly for V16HImode we don't have instructions for variable
20520 shuffling, while for V32QImode we can use after preparing suitable
20521 masks vpshufb; vpshufb; vpermq; vpor. */
20524 {
20528 }
20529 else
20530 {
20534 }
20537 /* Replicate the low bits of the V4DImode mask into V8SImode:
20538 mask = { A B C D }
20539 t1 = { A A B B C C D D }. */
20547 else
20550 /* Multiply the shuffle indicies by two. */
20552 OPTAB_DIRECT);
20554 /* Add one to the odd shuffle indicies:
20555 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
20557 {
20560 }
20564 OPTAB_DIRECT);
20566 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
20571 }
20574 {
20576 /* The VPERMD and VPERMPS instructions already properly ignore
20577 the high bits of the shuffle elements. No need for us to
20578 perform an AND ourselves. */
20581 else
20582 {
20588 }
20595 else
20596 {
20602 }
20606 /* By combining the two 128-bit input vectors into one 256-bit
20607 input vector, we can use VPERMD and VPERMPS for the full
20608 two-operand shuffle. */
20640 /* From mask create two adjusted masks, which contain the same
20641 bits as mask in the low 7 bits of each vector element.
20642 The first mask will have the most significant bit clear
20643 if it requests element from the same 128-bit lane
20644 and MSB set if it requests element from the other 128-bit lane.
20645 The second mask will have the opposite values of the MSB,
20646 and additionally will have its 128-bit lanes swapped.
20647 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
20648 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
20649 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
20650 stands for other 12 bytes. */
20651 /* The bit whether element is from the same lane or the other
20652 lane is bit 4, so shift it up by 3 to the MSB position. */
20656 /* Clear MSB bits from the mask just in case it had them set. */
20658 /* After this t1 will have MSB set for elements from other lane. */
20660 /* Clear bits other than MSB. */
20662 /* Or in the lower bits from mask into t3. */
20664 /* And invert MSB bits in t1, so MSB is set for elements from the same
20665 lane. */
20667 /* Swap 128-bit lanes in t3. */
20672 /* And or in the lower bits from mask into t1. */
20675 {
20676 /* Each of these shuffles will put 0s in places where
20677 element from the other 128-bit lane is needed, otherwise
20678 will shuffle in the requested value. */
20681 /* For t3 the 128-bit lanes are swapped again. */
20686 /* And oring both together leads to the result. */
20689 }
20692 /* Similarly to the above one_operand_shuffle code,
20693 just for repeated twice for each operand. merge_two:
20694 code will merge the two results together. */
20716 }
20717 }
20720 {
20721 /* The XOP VPPERM insn supports three inputs. By ignoring the
20722 one_operand_shuffle special case, we avoid creating another
20723 set of constant vectors in memory. */
20726 /* mask = mask & {2*w-1, ...} */
20728 }
20729 else
20730 {
20731 /* mask = mask & {w-1, ...} */
20733 }
20741 /* For non-QImode operations, convert the word permutation control
20742 into a byte permutation control. */
20744 {
20749 /* Convert mask to vector of chars. */
20752 /* Replicate each of the input bytes into byte positions:
20753 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
20754 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
20755 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
20762 else
20765 /* Convert it into the byte positions by doing
20766 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
20772 }
20774 /* The actual shuffle operations all operate on V16QImode. */
20780 {
20782 }
20784 {
20786 }
20787 else
20788 {
20792 /* Shuffle the two input vectors independently. */
20798 merge_two:
20799 /* Then merge them together. The key is whether any given control
20800 element contained a bit set that indicates the second word. */
20804 {
20805 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
20806 more shuffle to convert the V2DI input mask into a V4SI
20807 input mask. At which point the masking that expand_int_vcond
20808 will work as desired. */
20816 }
20833 }
20834 }
20836 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
20837 true if we should do zero extension, else sign extension. HIGH_P is
20838 true if we want the N/2 high elements, else the low elements. */
20840 void
20842 {
20844 rtx tmp;
20847 {
20853 {
20857 else
20860 extract
20866 else
20869 extract
20875 else
20878 extract
20884 else
20890 else
20896 else
20901 }
20904 {
20907 }
20909 {
20910 /* Shift higher 8 bytes to lower 8 bytes. */
20915 }
20916 else
20920 }
20921 else
20922 {
20926 {
20930 else
20936 else
20942 else
20947 }
20951 else
20956 }
20957 }
20959 /* Expand conditional increment or decrement using adb/sbb instructions.
20960 The default case using setcc followed by the conditional move can be
20961 done by generic code. */
20962 bool
20964 {
20966 rtx flags;
20968 rtx compare_op;
20986 {
20989 }
20992 {
20996 reverse_condition_maybe_unordered
20998 else
21000 }
21004 /* Construct either adc or sbb insn. */
21006 {
21008 {
21023 }
21024 }
21025 else
21026 {
21028 {
21043 }
21044 }
21048 }
21051 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
21052 but works for floating pointer parameters and nonoffsetable memories.
21053 For pushes, it returns just stack offsets; the values will be saved
21054 in the right order. Maximally three parts are generated. */
21056 static int
21058 {
21063 else
21069 /* Optimize constant pool reference to immediates. This is used by fp
21070 moves, that force all constants to memory to allow combining. */
21072 {
21076 }
21079 {
21080 /* The only non-offsetable memories we handle are pushes. */
21089 }
21092 {
21094 /* Caution: if we looked through a constant pool memory above,
21095 the operand may actually have a different mode now. That's
21096 ok, since we want to pun this all the way back to an integer. */
21100 }
21103 {
21106 else
21107 {
21111 {
21115 }
21117 {
21122 }
21124 {
21125 REAL_VALUE_TYPE r;
21130 {
21137 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
21138 long double may not be 80-bit. */
21147 }
21150 }
21151 else
21153 }
21154 }
21155 else
21156 {
21160 {
21163 {
21167 }
21169 {
21173 }
21175 {
21176 REAL_VALUE_TYPE r;
21182 /* Do not use shift by 32 to avoid warning on 32bit systems. */
21185 = gen_int_mode
21188 DImode);
21189 else
21196 = gen_int_mode
21199 DImode);
21200 else
21202 }
21203 else
21205 }
21206 }
21209 }
21211 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
21212 Return false when normal moves are needed; true when all required
21213 insns have been emitted. Operands 2-4 contain the input values
21214 int the correct order; operands 5-7 contain the output values. */
21216 void
21218 {
21226 /* The DFmode expanders may ask us to move double.
21227 For 64bit target this is single move. By hiding the fact
21228 here we simplify i386.md splitters. */
21230 {
21231 /* Optimize constant pool reference to immediates. This is used by
21232 fp moves, that force all constants to memory to allow combining. */
21239 {
21242 }
21243 else
21248 }
21250 /* The only non-offsettable memory we handle is push. */
21253 else
21260 /* When emitting push, take care for source operands on the stack. */
21263 {
21266 /* Compensate for the stack decrement by 4. */
21271 /* src_base refers to the stack pointer and is
21272 automatically decreased by emitted push. */
21276 }
21278 /* We need to do copy in the right order in case an address register
21279 of the source overlaps the destination. */
21281 {
21282 rtx tmp;
21285 {
21289 collisions++;
21290 }
21292 /* Collision in the middle part can be handled by reordering. */
21294 {
21297 }
21301 {
21303 {
21306 }
21307 else
21308 {
21311 }
21312 }
21314 /* If there are more collisions, we can't handle it by reordering.
21315 Do an lea to the last part and use only one colliding move. */
21317 {
21318 rtx base;
21324 /* Handle the case when the last part isn't valid for lea.
21325 Happens in 64-bit mode storing the 12-byte XFmode. */
21332 {
21335 }
21336 }
21337 }
21340 {
21342 {
21344 {
21349 }
21351 {
21354 }
21355 }
21356 else
21357 {
21358 /* In 64bit mode we don't have 32bit push available. In case this is
21359 register, it is OK - we will just use larger counterpart. We also
21360 retype memory - these comes from attempt to avoid REX prefix on
21361 moving of second half of TFmode value. */
21363 {
21365 {
21376 }
21380 }
21381 }
21385 }
21387 /* Choose correct order to not overwrite the source before it is copied. */
21397 {
21399 {
21402 }
21403 }
21404 else
21405 {
21407 {
21410 }
21411 }
21413 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
21415 {
21424 }
21430 }
21432 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
21433 left shift by a constant, either using a single shift or
21434 a sequence of add instructions. */
21436 static void
21438 {
21444 {
21448 }
21449 else
21450 {
21453 }
21454 }
21456 void
21458 {
21467 {
21472 {
21478 }
21479 else
21480 {
21488 }
21490 }
21497 {
21498 /* Assuming we've chosen a QImode capable registers, then 1 << N
21499 can be done with two 32/64-bit shifts, no branches, no cmoves. */
21501 {
21517 }
21519 /* Otherwise, we can get the same results by manually performing
21520 a bit extract operation on bit 5/6, and then performing the two
21521 shifts. The two methods of getting 0/1 into low/high are exactly
21522 the same size. Avoiding the shift in the bit extract case helps
21523 pentium4 a bit; no one else seems to care much either way. */
21524 else
21525 {
21530 HOST_WIDE_INT bits;
21531 rtx x;
21534 {
21540 }
21541 else
21542 {
21548 }
21552 else
21560 }
21565 }
21568 {
21569 /* For -1 << N, we can avoid the shld instruction, because we
21570 know that we're shifting 0...31/63 ones into a -1. */
21574 else
21576 }
21577 else
21578 {
21586 }
21591 {
21597 }
21598 else
21599 {
21604 }
21605 }
21607 void
21609 {
21619 {
21624 {
21630 }
21632 {
21641 }
21642 else
21643 {
21651 }
21652 }
21653 else
21654 {
21666 {
21674 scratch));
21675 }
21676 else
21677 {
21682 }
21683 }
21684 }
21686 void
21688 {
21698 {
21703 {
21710 }
21711 else
21712 {
21720 }
21721 }
21722 else
21723 {
21735 {
21741 scratch));
21742 }
21743 else
21744 {
21749 }
21750 }
21751 }
21753 /* Predict just emitted jump instruction to be taken with probability PROB. */
21754 static void
21756 {
21760 }
21762 /* Helper function for the string operations below. Dest VARIABLE whether
21763 it is aligned to VALUE bytes. If true, jump to the label. */
21764 static rtx
21766 {
21771 else
21777 else
21780 }
21782 /* Adjust COUNTER by the VALUE. */
21783 static void
21785 {
21790 }
21792 /* Zero extend possibly SImode EXP to Pmode register. */
21793 rtx
21795 {
21797 }
21799 /* Divide COUNTREG by SCALE. */
21800 static rtx
21802 {
21803 rtx sc;
21815 }
21817 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
21818 DImode for constant loop counts. */
21820 static enum machine_mode
21822 {
21830 }
21832 /* When SRCPTR is non-NULL, output simple loop to move memory
21833 pointer to SRCPTR to DESTPTR via chunks of MODE unrolled UNROLL times,
21834 overall size is COUNT specified in bytes. When SRCPTR is NULL, output the
21835 equivalent loop to set memory by VALUE (supposed to be in MODE).
21837 The size is rounded down to whole number of chunk size moved at once.
21838 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
21841 static void
21846 {
21851 rtx size;
21852 rtx x_addr;
21853 rtx y_addr;
21862 /* Those two should combine. */
21864 {
21868 }
21878 {
21882 /* When unrolling for chips that reorder memory reads and writes,
21883 we can save registers by using single temporary.
21884 Also using 4 temporaries is overkill in 32bit mode. */
21886 {
21888 {
21890 {
21891 destmem =
21893 srcmem =
21895 }
21897 }
21898 }
21899 else
21900 {
21904 {
21907 {
21908 srcmem =
21910 }
21912 }
21914 {
21916 {
21917 destmem =
21919 }
21921 }
21922 }
21923 }
21924 else
21926 {
21928 destmem =
21931 }
21941 {
21947 else
21949 }
21950 else
21958 {
21963 }
21965 }
21967 /* Output "rep; mov" instruction.
21968 Arguments have same meaning as for previous function */
21969 static void
21972 rtx count,
21974 {
21975 rtx destexp;
21976 rtx srcexp;
21977 rtx countreg;
21978 HOST_WIDE_INT rounded_count;
21980 /* If the size is known, it is shorter to use rep movs. */
21991 {
21998 }
21999 else
22000 {
22003 }
22005 {
22012 }
22013 else
22014 {
22019 }
22022 }
22024 /* Output "rep; stos" instruction.
22025 Arguments have same meaning as for previous function */
22026 static void
22029 rtx orig_value)
22030 {
22031 rtx destexp;
22032 rtx countreg;
22033 HOST_WIDE_INT rounded_count;
22040 {
22044 }
22045 else
22048 {
22053 }
22057 }
22059 static void
22062 {
22066 }
22068 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
22069 static void
22072 {
22075 {
22080 {
22082 {
22085 }
22086 else
22089 }
22091 {
22094 else
22095 {
22098 }
22100 }
22102 {
22105 }
22107 {
22110 }
22112 {
22115 }
22117 }
22119 {
22125 }
22127 /* When there are stringops, we can cheaply increase dest and src pointers.
22128 Otherwise we save code size by maintaining offset (zero is readily
22129 available from preceding rep operation) and using x86 addressing modes.
22130 */
22132 {
22134 {
22141 }
22143 {
22150 }
22152 {
22159 }
22160 }
22161 else
22162 {
22164 rtx tmp;
22167 {
22178 }
22180 {
22193 }
22195 {
22204 }
22205 }
22206 }
22208 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
22209 static void
22212 {
22213 count =
22219 }
22221 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
22222 static void
22224 {
22225 rtx dest;
22228 {
22233 {
22235 {
22240 }
22241 else
22244 }
22246 {
22248 {
22251 }
22252 else
22253 {
22258 }
22260 }
22262 {
22266 }
22268 {
22272 }
22274 {
22278 }
22280 }
22282 {
22285 }
22287 {
22290 {
22294 }
22295 else
22296 {
22302 }
22305 }
22307 {
22310 {
22313 }
22314 else
22315 {
22319 }
22322 }
22324 {
22330 }
22332 {
22338 }
22340 {
22346 }
22347 }
22349 /* Copy enough from DEST to SRC to align DEST known to by aligned by ALIGN to
22350 DESIRED_ALIGNMENT. */
22351 static void
22355 {
22357 {
22365 }
22367 {
22375 }
22377 {
22385 }
22387 }
22389 /* Copy enough from DST to SRC to align DST known to DESIRED_ALIGN.
22390 ALIGN_BYTES is how many bytes need to be copied. */
22391 static rtx
22394 {
22403 {
22408 }
22410 {
22421 }
22423 {
22429 {
22437 }
22440 }
22446 {
22458 }
22465 }
22467 /* Set enough from DEST to align DEST known to by aligned by ALIGN to
22468 DESIRED_ALIGNMENT. */
22469 static void
22472 {
22474 {
22481 }
22483 {
22490 }
22492 {
22499 }
22501 }
22503 /* Set enough from DST to align DST known to by aligned by ALIGN to
22504 DESIRED_ALIGN. ALIGN_BYTES is how many bytes need to be stored. */
22505 static rtx
22508 {
22512 {
22517 }
22519 {
22526 }
22528 {
22535 }
22542 }
22544 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
22545 static enum stringop_alg
22548 {
22551 /* Algorithms using the rep prefix want at least edi and ecx;
22552 additionally, memset wants eax and memcpy wants esi. Don't
22553 consider such algorithms if the user has appropriated those
22554 registers for their own purposes. */
22556 || (memset
22560 #define ALG_USABLE_P(alg) (rep_prefix_usable \
22561 || (alg != rep_prefix_1_byte \
22562 && alg != rep_prefix_4_byte \
22563 && alg != rep_prefix_8_byte))
22566 /* Even if the string operation call is cold, we still might spend a lot
22567 of time processing large blocks. */
22572 else
22580 else
22584 /* rep; movq or rep; movl is the smallest variant. */
22586 {
22589 else
22591 }
22592 /* Very tiny blocks are best handled via the loop, REP is expensive to setup.
22593 */
22597 {
22601 {
22602 /* We get here if the algorithms that were not libcall-based
22603 were rep-prefix based and we are unable to use rep prefixes
22604 based on global register usage. Break out of the loop and
22605 use the heuristic below. */
22609 {
22614 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
22615 last non-libcall inline algorithm. */
22617 {
22618 /* When the current size is best to be copied by a libcall,
22619 but we are still forced to inline, run the heuristic below
22620 that will pick code for medium sized blocks. */
22624 }
22626 {
22629 }
22630 }
22631 }
22633 }
22634 /* When asked to inline the call anyway, try to pick meaningful choice.
22635 We look for maximal size of block that is faster to copy by hand and
22636 take blocks of at most of that size guessing that average size will
22637 be roughly half of the block.
22639 If this turns out to be bad, we might simply specify the preferred
22640 choice in ix86_costs. */
22643 {
22650 {
22657 }
22658 /* If there aren't any usable algorithms, then recursing on
22659 smaller sizes isn't going to find anything. Just return the
22660 simple byte-at-a-time copy loop. */
22662 {
22663 /* Pick something reasonable. */
22667 }
22676 }
22678 #undef ALG_USABLE_P
22679 }
22681 /* Decide on alignment. We know that the operand is already aligned to ALIGN
22682 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
22683 static int
22687 {
22690 {
22701 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
22702 copying whole cacheline at once. */
22705 else
22709 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
22710 copying whole cacheline at once. */
22713 else
22721 }
22730 }
22732 /* Return the smallest power of 2 greater than VAL. */
22733 static int
22735 {
22740 }
22742 /* Expand string move (memcpy) operation. Use i386 string operations
22743 when profitable. expand_setmem contains similar code. The code
22744 depends upon architecture, block size and alignment, but always has
22745 the same overall structure:
22747 1) Prologue guard: Conditional that jumps up to epilogues for small
22748 blocks that can be handled by epilogue alone. This is faster
22749 but also needed for correctness, since prologue assume the block
22750 is larger than the desired alignment.
22752 Optional dynamic check for size and libcall for large
22753 blocks is emitted here too, with -minline-stringops-dynamically.
22755 2) Prologue: copy first few bytes in order to get destination
22756 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
22757 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
22758 copied. We emit either a jump tree on power of two sized
22759 blocks, or a byte loop.
22761 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
22762 with specified algorithm.
22764 4) Epilogue: code copying tail of the block that is too small to be
22765 handled by main body (or up to size guarded by prologue guard). */
22767 bool
22770 {
22771 rtx destreg;
22772 rtx srcreg;
22774 rtx tmp;
22788 /* i386 can do misaligned access on reasonably increased cost. */
22792 /* ALIGN is the minimum of destination and source alignment, but we care here
22793 just about destination alignment. */
22802 /* Make sure we don't need to care about overflow later on. */
22806 /* Step 0: Decide on preferred algorithm, desired alignment and
22807 size of chunks to be copied by main loop. */
22823 {
22848 }
22852 /* Step 1: Prologue guard. */
22854 /* Alignment code needs count to be in register. */
22856 {
22859 {
22860 align_bytes
22864 else
22866 }
22869 }
22872 /* Ensure that alignment prologue won't copy past end of block. */
22874 {
22876 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
22877 Make sure it is power of 2. */
22881 {
22883 {
22884 /* If main algorithm works on QImode, no epilogue is needed.
22885 For small sizes just don't align anything. */
22888 else
22890 }
22891 }
22892 else
22893 {
22900 else
22902 }
22903 }
22905 /* Emit code to decide on runtime whether library call or inline should be
22906 used. */
22908 {
22910 {
22912 {
22916 }
22917 }
22918 else
22919 {
22928 }
22929 }
22931 /* Step 2: Alignment prologue. */
22934 {
22936 {
22937 /* Except for the first move in epilogue, we no longer know
22938 constant offset in aliasing info. It don't seems to worth
22939 the pain to maintain it for the first move, so throw away
22940 the info early. */
22944 desired_align);
22945 }
22946 else
22947 {
22948 /* If we know how many bytes need to be stored before dst is
22949 sufficiently aligned, maintain aliasing info accurately. */
22955 }
22961 {
22962 /* It is possible that we copied enough so the main loop will not
22963 execute. */
22973 else
22975 }
22976 }
22978 {
22983 }
22987 /* Step 3: Main loop. */
22990 {
23003 /* Unroll only by factor of 2 in 32bit mode, since we don't have enough
23004 registers for 4 temporaries anyway. */
23007 expected_size);
23011 DImode);
23015 SImode);
23019 QImode);
23021 }
23022 /* Adjust properly the offset of src and dest memory for aliasing. */
23024 {
23029 }
23030 else
23031 {
23034 }
23036 /* Step 4: Epilogue to copy the remaining bytes. */
23037 epilogue:
23039 {
23040 /* When the main loop is done, COUNT_EXP might hold original count,
23041 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
23042 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
23043 bytes. Compensate if needed. */
23046 {
23047 tmp =
23050 OPTAB_DIRECT);
23053 }
23056 }
23060 epilogue_size_needed);
23064 }
23066 /* Helper function for memcpy. For QImode value 0xXY produce
23067 0xXYXYXYXY of wide specified by MODE. This is essentially
23068 a * 0x10101010, but we can do slightly better than
23069 synth_mult by unwinding the sequence by hand on CPUs with
23070 slow multiply. */
23071 static rtx
23073 {
23075 rtx tmp;
23082 {
23090 }
23099 nops--;
23104 {
23108 OPTAB_DIRECT);
23109 }
23110 else
23111 {
23117 else
23119 else
23120 {
23123 reg =
23125 }
23135 }
23136 }
23138 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
23139 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
23140 alignment from ALIGN to DESIRED_ALIGN. */
23141 static rtx
23143 {
23144 rtx promoted_val;
23153 else
23157 }
23159 /* Expand string clear operation (bzero). Use i386 string operations when
23160 profitable. See expand_movmem comment for explanation of individual
23161 steps performed. */
23162 bool
23165 {
23166 rtx destreg;
23168 rtx tmp;
23184 /* i386 can do misaligned access on reasonably increased cost. */
23193 /* Make sure we don't need to care about overflow later on. */
23197 /* Step 0: Decide on preferred algorithm, desired alignment and
23198 size of chunks to be copied by main loop. */
23213 {
23238 }
23241 /* Step 1: Prologue guard. */
23243 /* Alignment code needs count to be in register. */
23245 {
23248 {
23249 align_bytes
23253 else
23255 }
23257 {
23262 }
23263 }
23264 /* Do the cheap promotion to allow better CSE across the
23265 main loop and epilogue (ie one load of the big constant in the
23266 front of all code. */
23270 /* Ensure that alignment prologue won't copy past end of block. */
23272 {
23274 /* Epilogue always copies COUNT_EXP & (EPILOGUE_SIZE_NEEDED - 1) bytes.
23275 Make sure it is power of 2. */
23278 /* To improve performance of small blocks, we jump around the VAL
23279 promoting mode. This mean that if the promoted VAL is not constant,
23280 we might not use it in the epilogue and have to use byte
23281 loop variant. */
23285 {
23287 {
23288 /* If main algorithm works on QImode, no epilogue is needed.
23289 For small sizes just don't align anything. */
23292 else
23294 }
23295 }
23296 else
23297 {
23304 else
23306 }
23307 }
23309 {
23318 }
23320 /* Step 2: Alignment prologue. */
23322 /* Do the expensive promotion once we branched off the small blocks. */
23329 {
23331 {
23332 /* Except for the first move in epilogue, we no longer know
23333 constant offset in aliasing info. It don't seems to worth
23334 the pain to maintain it for the first move, so throw away
23335 the info early. */
23338 desired_align);
23339 }
23340 else
23341 {
23342 /* If we know how many bytes need to be stored before dst is
23343 sufficiently aligned, maintain aliasing info accurately. */
23349 }
23355 {
23356 /* It is possible that we copied enough so the main loop will not
23357 execute. */
23367 else
23369 }
23370 }
23372 {
23378 }
23382 /* Step 3: Main loop. */
23385 {
23413 }
23414 /* Adjust properly the offset of src and dest memory for aliasing. */
23418 else
23421 /* Step 4: Epilogue to copy the remaining bytes. */
23424 {
23425 /* When the main loop is done, COUNT_EXP might hold original count,
23426 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
23427 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
23428 bytes. Compensate if needed. */
23431 {
23432 tmp =
23435 OPTAB_DIRECT);
23438 }
23441 }
23442 epilogue:
23444 {
23447 epilogue_size_needed);
23448 else
23450 epilogue_size_needed);
23451 }
23455 }
23457 /* Expand the appropriate insns for doing strlen if not just doing
23458 repnz; scasb
23460 out = result, initialized with the start address
23461 align_rtx = alignment of the address.
23462 scratch = scratch register, initialized with the startaddress when
23463 not aligned, otherwise undefined
23465 This is just the body. It needs the initializations mentioned above and
23466 some address computing at the end. These things are done in i386.md. */
23468 static void
23470 {
23472 rtx tmp;
23477 rtx mem;
23480 rtx cmp;
23486 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
23488 /* Is there a known alignment and is it less than 4? */
23490 {
23493 /* Is there a known alignment and is it not 2? */
23495 {
23499 /* Leave just the 3 lower bits. */
23509 }
23510 else
23511 {
23512 /* Since the alignment is 2, we have to check 2 or 0 bytes;
23513 check if is aligned to 4 - byte. */
23520 }
23524 /* Now compare the bytes. */
23526 /* Compare the first n unaligned byte on a byte per byte basis. */
23530 /* Increment the address. */
23533 /* Not needed with an alignment of 2 */
23535 {
23539 end_0_label);
23544 }
23547 end_0_label);
23550 }
23552 /* Generate loop to check 4 bytes at a time. It is not a good idea to
23553 align this loop. It gives only huge programs, but does not help to
23554 speed up. */
23561 /* This formula yields a nonzero result iff one of the bytes is zero.
23562 This saves three branches inside loop and many cycles. */
23570 align_4_label);
23573 {
23579 /* If zero is not in the first two bytes, move two bytes forward. */
23585 reg,
23586 tmpreg)));
23587 /* Emit lea manually to avoid clobbering of flags. */
23595 reg2,
23596 out)));
23597 }
23598 else
23599 {
23601 /* Is zero in the first two bytes? */
23608 pc_rtx);
23612 /* Not in the first two. Move two bytes forward. */
23618 }
23620 /* Avoid branch in fixing the byte. */
23628 }
23630 /* Expand strlen. */
23632 bool
23634 {
23637 /* The generic case of strlen expander is long. Avoid it's
23638 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
23641 && !TARGET_INLINE_ALL_STRINGOPS
23651 {
23652 /* Well it seems that some optimizer does not combine a call like
23653 foo(strlen(bar), strlen(bar));
23654 when the move and the subtraction is done here. It does calculate
23655 the length just once when these instructions are done inside of
23656 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
23657 often used and I use one fewer register for the lifetime of
23658 output_strlen_unroll() this is better. */
23664 /* strlensi_unroll_1 returns the address of the zero at the end of
23665 the string, like memchr(), so compute the length by subtracting
23666 the start address. */
23668 }
23669 else
23670 {
23671 rtx unspec;
23673 /* Can't use this if the user has appropriated eax, ecx, or edi. */
23686 /* If .md starts supporting :P, this can be done in .md. */
23692 }
23694 }
23696 /* For given symbol (function) construct code to compute address of it's PLT
23697 entry in large x86-64 PIC model. */
23698 static rtx
23700 {
23713 }
23715 rtx
23717 rtx callarg2,
23719 {
23720 unsigned int const cregs_size
23731 {
23732 #if TARGET_MACHO
23735 #endif
23736 }
23737 else
23738 {
23739 /* Static functions and indirect calls don't need the pic register. */
23741 && (!TARGET_64BIT
23747 }
23750 {
23754 }
23765 {
23768 }
23776 {
23780 }
23784 {
23788 UNSPEC_MS_TO_SYSV_CALL);
23791 {
23797 }
23798 }
23807 }
23809 /* Output the assembly for a call instruction. */
23813 {
23819 {
23822 /* SEH epilogue detection requires the indirect branch case
23823 to include REX.W. */
23826 else
23831 }
23833 /* SEH unwinding can require an extra nop to be emitted in several
23834 circumstances. Determine if we have one of those. */
23836 {
23837 rtx i;
23840 {
23841 /* If we get to another real insn, we don't need the nop. */
23845 /* If we get to the epilogue note, prevent a catch region from
23846 being adjacent to the standard epilogue sequence. If non-
23847 call-exceptions, we'll have done this during epilogue emission. */
23849 && !flag_non_call_exceptions
23851 {
23854 }
23855 }
23857 /* If we didn't find a real insn following the call, prevent the
23858 unwinder from looking into the next function. */
23861 }
23865 else
23874 }
23875 \f
23876 /* Clear stack slot assignments remembered from previous functions.
23877 This is called from INIT_EXPANDERS once before RTL is emitted for each
23878 function. */
23882 {
23890 }
23892 /* Return a MEM corresponding to a stack slot with mode MODE.
23893 Allocate a new slot if necessary.
23895 The RTL for a function can have several slots available: N is
23896 which slot to use. */
23898 rtx
23900 {
23917 }
23919 static void
23921 {
23927 }
23928 \f
23929 /* Calculate the length of the memory address in the instruction encoding.
23930 Includes addr32 prefix, does not include the one-byte modrm, opcode,
23931 or other prefixes. We never generate addr32 prefix for LEA insn. */
23933 int
23935 {
23952 /* If this is not LEA instruction, add the length of addr32 prefix. */
23957 len++;
23971 /* Rule of thumb:
23972 - esp as the base always wants an index,
23973 - ebp as the base always wants a displacement,
23974 - r12 as the base always wants an index,
23975 - r13 as the base always wants a displacement. */
23977 /* Register Indirect. */
23979 {
23980 /* esp (for its index) and ebp (for its displacement) need
23981 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
23982 code. */
23989 len++;
23990 }
23992 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
23993 is not disp32, but disp32(%rip), so for disp32
23994 SIB byte is needed, unless print_operand_address
23995 optimizes it into disp32(%rip) or (%rip) is implied
23996 by UNSPEC. */
23998 {
24001 {
24017 len++;
24018 }
24019 }
24020 else
24021 {
24022 /* Find the length of the displacement constant. */
24024 {
24027 else
24029 }
24030 /* ebp always wants a displacement. Similarly r13. */
24032 len++;
24034 /* An index requires the two-byte modrm form.... */
24036 /* ...like esp (or r12), which always wants an index. */
24040 len++;
24041 }
24044 }
24046 /* Compute default value for "length_immediate" attribute. When SHORTFORM
24047 is set, expect that insn have 8bit immediate alternative. */
24048 int
24050 {
24056 {
24061 {
24064 {
24076 }
24078 {
24081 }
24082 }
24084 {
24094 /* Immediates for DImode instructions are encoded
24095 as 32bit sign extended values. */
24101 }
24102 }
24104 }
24106 /* Compute default value for "length_address" attribute. */
24107 int
24109 {
24113 {
24124 }
24129 {
24132 {
24137 constraints++;
24140 ;
24141 /* Skip ignored operands. */
24144 }
24146 }
24148 }
24150 /* Compute default value for "length_vex" attribute. It includes
24151 2 or 3 byte VEX prefix and 1 opcode byte. */
24153 int
24155 {
24158 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
24159 byte VEX prefix. */
24163 /* We can always use 2 byte VEX prefix in 32bit. */
24171 {
24172 /* REX.W bit uses 3 byte VEX prefix. */
24176 }
24177 else
24178 {
24179 /* REX.X or REX.B bits use 3 byte VEX prefix. */
24183 }
24186 }
24187 \f
24188 /* Return the maximum number of instructions a cpu can issue. */
24190 static int
24192 {
24194 {
24220 }
24221 }
24223 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
24224 by DEP_INSN and nothing set by DEP_INSN. */
24226 static bool
24228 {
24231 /* Simplify the test for uninteresting insns. */
24239 {
24242 }
24247 {
24250 }
24251 else
24257 /* This test is true if the dependent insn reads the flags but
24258 not any other potentially set register. */
24266 }
24268 /* Return true iff USE_INSN has a memory address with operands set by
24269 SET_INSN. */
24271 bool
24273 {
24278 {
24281 }
24283 }
24285 static int
24287 {
24293 /* Anti and output dependencies have zero cost on all CPUs. */
24299 /* If we can't recognize the insns, we can't really do anything. */
24307 {
24309 /* Address Generation Interlock adds a cycle of latency. */
24311 {
24322 }
24326 /* ??? Compares pair with jump/setcc. */
24330 /* Floating point stores require value to be ready one cycle earlier. */
24340 /* INT->FP conversion is expensive. */
24344 /* There is one cycle extra latency between an FP op and a store. */
24352 /* Show ability of reorder buffer to hide latency of load by executing
24353 in parallel with previous instruction in case
24354 previous instruction is not needed to compute the address. */
24357 {
24358 /* Claim moves to take one cycle, as core can issue one load
24359 at time and the next load can start cycle later. */
24364 cost--;
24365 }
24371 /* The esp dependency is resolved before the instruction is really
24372 finished. */
24377 /* INT->FP conversion is expensive. */
24381 /* Show ability of reorder buffer to hide latency of load by executing
24382 in parallel with previous instruction in case
24383 previous instruction is not needed to compute the address. */
24386 {
24387 /* Claim moves to take one cycle, as core can issue one load
24388 at time and the next load can start cycle later. */
24394 else
24396 }
24412 /* Show ability of reorder buffer to hide latency of load by executing
24413 in parallel with previous instruction in case
24414 previous instruction is not needed to compute the address. */
24417 {
24421 /* Because of the difference between the length of integer and
24422 floating unit pipeline preparation stages, the memory operands
24423 for floating point are cheaper.
24425 ??? For Athlon it the difference is most probably 2. */
24428 else
24433 else
24435 }
24439 }
24442 }
24444 /* How many alternative schedules to try. This should be as wide as the
24445 scheduling freedom in the DFA, but no wider. Making this value too
24446 large results extra work for the scheduler. */
24448 static int
24450 {
24452 {
24464 /* Generally, we want haifa-sched:max_issue() to look ahead as far
24465 as many instructions can be executed on a cycle, i.e.,
24466 issue_rate. I wonder why tuning for many CPUs does not do this. */
24469 /* Don't use lookahead for pre-reload schedule to save compile time. */
24474 }
24475 }
24477 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
24478 execution. It is applied if
24479 (1) IMUL instruction is on the top of list;
24480 (2) There exists the only producer of independent IMUL instruction in
24481 ready list;
24482 (3) Put found producer on the top of ready list.
24483 Returns issue rate. */
24485 static int
24488 {
24493 sd_iterator_def sd_it;
24494 dep_t dep;
24497 /* Set up issue rate. */
24500 /* Do reodering for Atom only. */
24503 /* Do not perform ready list reodering for pre-reload schedule pass. */
24506 /* Nothing to do if ready list contains only 1 instruction. */
24510 /* Check that IMUL instruction is on the top of ready list. */
24523 /* Search for producer of independent IMUL instruction. */
24525 {
24529 /* Skip IMUL instruction. */
24539 {
24540 rtx con;
24551 {
24552 sd_iterator_def sd_it1;
24553 dep_t dep1;
24554 /* Check if there is no other dependee for IMUL. */
24557 {
24558 rtx pro;
24564 }
24567 }
24568 }
24571 }
24579 /* Put IMUL producer (ready[index]) at the top of ready list. */
24586 }
24588 static bool
24591 /* Returns true if lhs of insn is HW function argument register and set up
24592 is_spilled to true if it is likely spilled HW register. */
24593 static bool
24595 {
24596 rtx dst;
24600 /* Call instructions are not movable, ignore it. */
24611 {
24612 /* Is it likely spilled HW register? */
24617 }
24619 }
24621 /* Add output dependencies for chain of function adjacent arguments if only
24622 there is a move to likely spilled HW register. Return first argument
24623 if at least one dependence was added or NULL otherwise. */
24624 static rtx
24626 {
24627 rtx insn;
24634 /* Find nearest to call argument passing instruction. */
24636 {
24645 }
24649 {
24656 {
24659 }
24661 {
24662 /* Add output depdendence between two function arguments if chain
24663 of output arguments contains likely spilled HW registers. */
24667 }
24668 else
24670 }
24674 }
24676 /* Add output or anti dependency from insn to first_arg to restrict its code
24677 motion. */
24678 static void
24680 {
24681 rtx set;
24682 rtx tmp;
24689 {
24690 /* Add output dependency to the first function argument. */
24693 }
24694 /* Add anti dependency. */
24696 }
24698 /* Avoid cross block motion of function argument through adding dependency
24699 from the first non-jump instruction in bb. */
24700 static void
24702 {
24706 {
24708 {
24711 {
24714 }
24715 }
24719 }
24720 }
24722 /* Hook for pre-reload schedule - avoid motion of function arguments
24723 passed in likely spilled HW registers. */
24724 static void
24726 {
24727 rtx insn;
24735 {
24738 {
24739 /* Add dependee for first argument to predecessors if only
24740 region contains more than one block. */
24744 /* Skip trivial regions and region head blocks that can have
24745 predecessors outside of region. */
24747 {
24748 edge e;
24749 edge_iterator ei;
24750 /* Assume that region is SCC, i.e. all immediate predecessors
24751 of non-head block are in the same region. */
24753 {
24754 /* Avoid creating of loop-carried dependencies through
24755 using topological odering in region. */
24758 }
24759 }
24763 }
24764 }
24767 }
24769 /* Hook for pre-reload schedule - set priority of moves from likely spilled
24770 HW registers to maximum, to schedule them at soon as possible. These are
24771 moves from function argument registers at the top of the function entry
24772 and moves from function return value registers after call. */
24773 static int
24775 {
24776 rtx set;
24786 {
24793 }
24796 }
24798 /* Model decoder of Core 2/i7.
24799 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
24800 track the instruction fetch block boundaries and make sure that long
24801 (9+ bytes) instructions are assigned to D0. */
24803 /* Maximum length of an insn that can be handled by
24804 a secondary decoder unit. '8' for Core 2/i7. */
24807 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
24808 '16' for Core 2/i7. */
24811 /* Maximum number of instructions decoder can handle per cycle.
24812 '6' for Core 2/i7. */
24816 ix86_first_cycle_multipass_data_t;
24818 const_ix86_first_cycle_multipass_data_t;
24820 /* A variable to store target state across calls to max_issue within
24821 one cycle. */
24825 /* Initialize DATA. */
24826 static void
24828 {
24829 ix86_first_cycle_multipass_data_t data
24836 }
24838 /* Advancing the cycle; reset ifetch block counts. */
24839 static void
24841 {
24848 }
24852 /* Filter out insns from ready_try that the core will not be able to issue
24853 on current cycle due to decoder. */
24854 static void
24855 core2i7_first_cycle_multipass_filter_ready_try
24858 {
24860 {
24861 rtx insn;
24871 (!first_cycle_insn_p
24873 /* ... or it would not fit into the ifetch block ... */
24875 /* ... or the decoder is full already ... */
24877 /* ... mask the insn out. */
24878 {
24883 }
24884 }
24885 }
24887 /* Prepare for a new round of multipass lookahead scheduling. */
24888 static void
24891 {
24892 ix86_first_cycle_multipass_data_t data
24894 const_ix86_first_cycle_multipass_data_t prev_data
24897 /* Restore the state from the end of the previous round. */
24901 /* Filter instructions that cannot be issued on current cycle due to
24902 decoder restrictions. */
24904 first_cycle_insn_p);
24905 }
24907 /* INSN is being issued in current solution. Account for its impact on
24908 the decoder model. */
24909 static void
24912 {
24913 ix86_first_cycle_multipass_data_t data
24915 const_ix86_first_cycle_multipass_data_t prev_data
24925 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
24927 {
24930 }
24932 {
24936 }
24939 /* Filter out insns from ready_try that the core will not be able to issue
24940 on current cycle due to decoder. */
24943 }
24945 /* Revert the effect on ready_try. */
24946 static void
24950 {
24951 const_ix86_first_cycle_multipass_data_t data
24954 sbitmap_iterator sbi;
24958 {
24960 }
24961 }
24963 /* Save the result of multipass lookahead scheduling for the next round. */
24964 static void
24966 {
24967 const_ix86_first_cycle_multipass_data_t data
24969 ix86_first_cycle_multipass_data_t next_data
24973 {
24976 }
24977 }
24979 /* Deallocate target data. */
24980 static void
24982 {
24983 ix86_first_cycle_multipass_data_t data
24987 {
24991 }
24992 }
24994 /* Prepare for scheduling pass. */
24995 static void
24999 {
25000 /* Install scheduling hooks for current CPU. Some of these hooks are used
25001 in time-critical parts of the scheduler, so we only set them up when
25002 they are actually used. */
25004 {
25008 /* Do not perform multipass scheduling for pre-reload schedule
25009 to save compile time. */
25011 {
25027 /* Set decoder parameters. */
25032 }
25033 /* ... Fall through ... */
25043 }
25044 }
25046 \f
25047 /* Compute the alignment given to a constant that is being placed in memory.
25048 EXP is the constant and ALIGN is the alignment that the object would
25049 ordinarily have.
25050 The value of this function is used instead of that alignment to align
25051 the object. */
25053 int
25055 {
25058 {
25063 }
25069 }
25071 /* Compute the alignment for a static variable.
25072 TYPE is the data type, and ALIGN is the alignment that
25073 the object would ordinarily have. The value of this function is used
25074 instead of that alignment to align the object. */
25076 int
25078 {
25089 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
25090 to 16byte boundary. */
25092 {
25099 }
25102 {
25107 }
25109 {
25116 }
25121 {
25126 }
25129 {
25134 }
25137 }
25139 /* Compute the alignment for a local variable or a stack slot. EXP is
25140 the data type or decl itself, MODE is the widest mode available and
25141 ALIGN is the alignment that the object would ordinarily have. The
25142 value of this macro is used instead of that alignment to align the
25143 object. */
25145 unsigned int
25148 {
25152 {
25155 }
25156 else
25157 {
25160 }
25162 /* Don't do dynamic stack realignment for long long objects with
25163 -mpreferred-stack-boundary=2. */
25172 /* If TYPE is NULL, we are allocating a stack slot for caller-save
25173 register in MODE. We will return the largest alignment of XF
25174 and DF. */
25176 {
25180 }
25182 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
25183 to 16byte boundary. Exact wording is:
25185 An array uses the same alignment as its elements, except that a local or
25186 global array variable of length at least 16 bytes or
25187 a C99 variable-length array variable always has alignment of at least 16 bytes.
25189 This was added to allow use of aligned SSE instructions at arrays. This
25190 rule is meant for static storage (where compiler can not do the analysis
25191 by itself). We follow it for automatic variables only when convenient.
25192 We fully control everything in the function compiled and functions from
25193 other unit can not rely on the alignment.
25195 Exclude va_list type. It is the common case of local array where
25196 we can not benefit from the alignment. */
25199 {
25209 }
25211 {
25216 }
25218 {
25224 }
25229 {
25234 }
25237 {
25243 }
25245 }
25247 /* Compute the minimum required alignment for dynamic stack realignment
25248 purposes for a local variable, parameter or a stack slot. EXP is
25249 the data type or decl itself, MODE is its mode and ALIGN is the
25250 alignment that the object would ordinarily have. */
25252 unsigned int
25255 {
25259 {
25262 }
25263 else
25264 {
25267 }
25272 /* Don't do dynamic stack realignment for long long objects with
25273 -mpreferred-stack-boundary=2. */
25280 }
25281 \f
25282 /* Find a location for the static chain incoming to a nested function.
25283 This is a register, unless all free registers are used by arguments. */
25285 static rtx
25287 {
25294 {
25295 /* We always use R10 in 64-bit mode. */
25297 }
25298 else
25299 {
25300 tree fntype;
25303 /* By default in 32-bit mode we use ECX to pass the static chain. */
25309 {
25310 /* Fastcall functions use ecx/edx for arguments, which leaves
25311 us with EAX for the static chain.
25312 Thiscall functions use ecx for arguments, which also
25313 leaves us with EAX for the static chain. */
25315 }
25317 {
25318 /* Thiscall functions use ecx for arguments, which leaves
25319 us with EAX and EDX for the static chain.
25320 We are using for abi-compatibility EAX. */
25322 }
25324 {
25325 /* For regparm 3, we have no free call-clobbered registers in
25326 which to store the static chain. In order to implement this,
25327 we have the trampoline push the static chain to the stack.
25328 However, we can't push a value below the return address when
25329 we call the nested function directly, so we have to use an
25330 alternate entry point. For this we use ESI, and have the
25331 alternate entry point push ESI, so that things appear the
25332 same once we're executing the nested function. */
25334 {
25340 }
25342 }
25343 }
25346 }
25348 /* Emit RTL insns to initialize the variable parts of a trampoline.
25349 FNDECL is the decl of the target address; M_TRAMP is a MEM for
25350 the trampoline, and CHAIN_VALUE is an RTX for the static chain
25351 to be passed to the target function. */
25353 static void
25355 {
25363 {
25366 /* Load the function address to r11. Try to load address using
25367 the shorter movl instead of movabs. We may want to support
25368 movq for kernel mode, but kernel does not use trampolines at
25369 the moment. FNADDR is a 32bit address and may not be in
25370 DImode when ptr_mode == SImode. Always use movl in this
25371 case. */
25374 {
25383 }
25384 else
25385 {
25392 }
25394 /* Load static chain using movabs to r10. Use the shorter movl
25395 instead of movabs when ptr_mode == SImode. */
25397 {
25400 }
25401 else
25402 {
25405 }
25414 /* Jump to r11; the last (unused) byte is a nop, only there to
25415 pad the write out to a single 32-bit store. */
25419 }
25420 else
25421 {
25424 /* Depending on the static chain location, either load a register
25425 with a constant, or push the constant to the stack. All of the
25426 instructions are the same size. */
25429 {
25431 {
25438 }
25439 }
25440 else
25455 /* Compute offset from the end of the jmp to the target function.
25456 In the case in which the trampoline stores the static chain on
25457 the stack, we need to skip the first insn which pushes the
25458 (call-saved) register static chain; this push is 1 byte. */
25465 }
25469 #ifdef HAVE_ENABLE_EXECUTE_STACK
25470 #ifdef CHECK_EXECUTE_STACK_ENABLED
25472 #endif
25475 #endif
25476 }
25477 \f
25478 /* The following file contains several enumerations and data structures
25479 built from the definitions in i386-builtin-types.def. */
25483 /* Table for the ix86 builtin non-function types. */
25486 /* Retrieve an element from the above table, building some of
25487 the types lazily. */
25489 static tree
25491 {
25503 {
25511 }
25512 else
25513 {
25519 else
25527 }
25531 }
25533 /* Table for the ix86 builtin function types. */
25536 /* Retrieve an element from the above table, building some of
25537 the types lazily. */
25539 static tree
25541 {
25542 tree type;
25551 {
25559 {
25562 }
25565 }
25566 else
25567 {
25573 }
25577 }
25580 /* Codes for all the SSE/MMX builtins. */
25581 enum ix86_builtins
25582 {
25583 IX86_BUILTIN_ADDPS,
25584 IX86_BUILTIN_ADDSS,
25585 IX86_BUILTIN_DIVPS,
25586 IX86_BUILTIN_DIVSS,
25587 IX86_BUILTIN_MULPS,
25588 IX86_BUILTIN_MULSS,
25589 IX86_BUILTIN_SUBPS,
25590 IX86_BUILTIN_SUBSS,
25592 IX86_BUILTIN_CMPEQPS,
25593 IX86_BUILTIN_CMPLTPS,
25594 IX86_BUILTIN_CMPLEPS,
25595 IX86_BUILTIN_CMPGTPS,
25596 IX86_BUILTIN_CMPGEPS,
25597 IX86_BUILTIN_CMPNEQPS,
25598 IX86_BUILTIN_CMPNLTPS,
25599 IX86_BUILTIN_CMPNLEPS,
25600 IX86_BUILTIN_CMPNGTPS,
25601 IX86_BUILTIN_CMPNGEPS,
25602 IX86_BUILTIN_CMPORDPS,
25603 IX86_BUILTIN_CMPUNORDPS,
25604 IX86_BUILTIN_CMPEQSS,
25605 IX86_BUILTIN_CMPLTSS,
25606 IX86_BUILTIN_CMPLESS,
25607 IX86_BUILTIN_CMPNEQSS,
25608 IX86_BUILTIN_CMPNLTSS,
25609 IX86_BUILTIN_CMPNLESS,
25610 IX86_BUILTIN_CMPNGTSS,
25611 IX86_BUILTIN_CMPNGESS,
25612 IX86_BUILTIN_CMPORDSS,
25613 IX86_BUILTIN_CMPUNORDSS,
25615 IX86_BUILTIN_COMIEQSS,
25616 IX86_BUILTIN_COMILTSS,
25617 IX86_BUILTIN_COMILESS,
25618 IX86_BUILTIN_COMIGTSS,
25619 IX86_BUILTIN_COMIGESS,
25620 IX86_BUILTIN_COMINEQSS,
25621 IX86_BUILTIN_UCOMIEQSS,
25622 IX86_BUILTIN_UCOMILTSS,
25623 IX86_BUILTIN_UCOMILESS,
25624 IX86_BUILTIN_UCOMIGTSS,
25625 IX86_BUILTIN_UCOMIGESS,
25626 IX86_BUILTIN_UCOMINEQSS,
25628 IX86_BUILTIN_CVTPI2PS,
25629 IX86_BUILTIN_CVTPS2PI,
25630 IX86_BUILTIN_CVTSI2SS,
25631 IX86_BUILTIN_CVTSI642SS,
25632 IX86_BUILTIN_CVTSS2SI,
25633 IX86_BUILTIN_CVTSS2SI64,
25634 IX86_BUILTIN_CVTTPS2PI,
25635 IX86_BUILTIN_CVTTSS2SI,
25636 IX86_BUILTIN_CVTTSS2SI64,
25638 IX86_BUILTIN_MAXPS,
25639 IX86_BUILTIN_MAXSS,
25640 IX86_BUILTIN_MINPS,
25641 IX86_BUILTIN_MINSS,
25643 IX86_BUILTIN_LOADUPS,
25644 IX86_BUILTIN_STOREUPS,
25645 IX86_BUILTIN_MOVSS,
25647 IX86_BUILTIN_MOVHLPS,
25648 IX86_BUILTIN_MOVLHPS,
25649 IX86_BUILTIN_LOADHPS,
25650 IX86_BUILTIN_LOADLPS,
25651 IX86_BUILTIN_STOREHPS,
25652 IX86_BUILTIN_STORELPS,
25654 IX86_BUILTIN_MASKMOVQ,
25655 IX86_BUILTIN_MOVMSKPS,
25656 IX86_BUILTIN_PMOVMSKB,
25658 IX86_BUILTIN_MOVNTPS,
25659 IX86_BUILTIN_MOVNTQ,
25661 IX86_BUILTIN_LOADDQU,
25662 IX86_BUILTIN_STOREDQU,
25664 IX86_BUILTIN_PACKSSWB,
25665 IX86_BUILTIN_PACKSSDW,
25666 IX86_BUILTIN_PACKUSWB,
25668 IX86_BUILTIN_PADDB,
25669 IX86_BUILTIN_PADDW,
25670 IX86_BUILTIN_PADDD,
25671 IX86_BUILTIN_PADDQ,
25672 IX86_BUILTIN_PADDSB,
25673 IX86_BUILTIN_PADDSW,
25674 IX86_BUILTIN_PADDUSB,
25675 IX86_BUILTIN_PADDUSW,
25676 IX86_BUILTIN_PSUBB,
25677 IX86_BUILTIN_PSUBW,
25678 IX86_BUILTIN_PSUBD,
25679 IX86_BUILTIN_PSUBQ,
25680 IX86_BUILTIN_PSUBSB,
25681 IX86_BUILTIN_PSUBSW,
25682 IX86_BUILTIN_PSUBUSB,
25683 IX86_BUILTIN_PSUBUSW,
25685 IX86_BUILTIN_PAND,
25686 IX86_BUILTIN_PANDN,
25687 IX86_BUILTIN_POR,
25688 IX86_BUILTIN_PXOR,
25690 IX86_BUILTIN_PAVGB,
25691 IX86_BUILTIN_PAVGW,
25693 IX86_BUILTIN_PCMPEQB,
25694 IX86_BUILTIN_PCMPEQW,
25695 IX86_BUILTIN_PCMPEQD,
25696 IX86_BUILTIN_PCMPGTB,
25697 IX86_BUILTIN_PCMPGTW,
25698 IX86_BUILTIN_PCMPGTD,
25700 IX86_BUILTIN_PMADDWD,
25702 IX86_BUILTIN_PMAXSW,
25703 IX86_BUILTIN_PMAXUB,
25704 IX86_BUILTIN_PMINSW,
25705 IX86_BUILTIN_PMINUB,
25707 IX86_BUILTIN_PMULHUW,
25708 IX86_BUILTIN_PMULHW,
25709 IX86_BUILTIN_PMULLW,
25711 IX86_BUILTIN_PSADBW,
25712 IX86_BUILTIN_PSHUFW,
25714 IX86_BUILTIN_PSLLW,
25715 IX86_BUILTIN_PSLLD,
25716 IX86_BUILTIN_PSLLQ,
25717 IX86_BUILTIN_PSRAW,
25718 IX86_BUILTIN_PSRAD,
25719 IX86_BUILTIN_PSRLW,
25720 IX86_BUILTIN_PSRLD,
25721 IX86_BUILTIN_PSRLQ,
25722 IX86_BUILTIN_PSLLWI,
25723 IX86_BUILTIN_PSLLDI,
25724 IX86_BUILTIN_PSLLQI,
25725 IX86_BUILTIN_PSRAWI,
25726 IX86_BUILTIN_PSRADI,
25727 IX86_BUILTIN_PSRLWI,
25728 IX86_BUILTIN_PSRLDI,
25729 IX86_BUILTIN_PSRLQI,
25731 IX86_BUILTIN_PUNPCKHBW,
25732 IX86_BUILTIN_PUNPCKHWD,
25733 IX86_BUILTIN_PUNPCKHDQ,
25734 IX86_BUILTIN_PUNPCKLBW,
25735 IX86_BUILTIN_PUNPCKLWD,
25736 IX86_BUILTIN_PUNPCKLDQ,
25738 IX86_BUILTIN_SHUFPS,
25740 IX86_BUILTIN_RCPPS,
25741 IX86_BUILTIN_RCPSS,
25742 IX86_BUILTIN_RSQRTPS,
25743 IX86_BUILTIN_RSQRTPS_NR,
25744 IX86_BUILTIN_RSQRTSS,
25745 IX86_BUILTIN_RSQRTF,
25746 IX86_BUILTIN_SQRTPS,
25747 IX86_BUILTIN_SQRTPS_NR,
25748 IX86_BUILTIN_SQRTSS,
25750 IX86_BUILTIN_UNPCKHPS,
25751 IX86_BUILTIN_UNPCKLPS,
25753 IX86_BUILTIN_ANDPS,
25754 IX86_BUILTIN_ANDNPS,
25755 IX86_BUILTIN_ORPS,
25756 IX86_BUILTIN_XORPS,
25758 IX86_BUILTIN_EMMS,
25759 IX86_BUILTIN_LDMXCSR,
25760 IX86_BUILTIN_STMXCSR,
25761 IX86_BUILTIN_SFENCE,
25763 IX86_BUILTIN_FXSAVE,
25764 IX86_BUILTIN_FXRSTOR,
25765 IX86_BUILTIN_FXSAVE64,
25766 IX86_BUILTIN_FXRSTOR64,
25768 IX86_BUILTIN_XSAVE,
25769 IX86_BUILTIN_XRSTOR,
25770 IX86_BUILTIN_XSAVE64,
25771 IX86_BUILTIN_XRSTOR64,
25773 IX86_BUILTIN_XSAVEOPT,
25774 IX86_BUILTIN_XSAVEOPT64,
25776 /* 3DNow! Original */
25777 IX86_BUILTIN_FEMMS,
25778 IX86_BUILTIN_PAVGUSB,
25779 IX86_BUILTIN_PF2ID,
25780 IX86_BUILTIN_PFACC,
25781 IX86_BUILTIN_PFADD,
25782 IX86_BUILTIN_PFCMPEQ,
25783 IX86_BUILTIN_PFCMPGE,
25784 IX86_BUILTIN_PFCMPGT,
25785 IX86_BUILTIN_PFMAX,
25786 IX86_BUILTIN_PFMIN,
25787 IX86_BUILTIN_PFMUL,
25788 IX86_BUILTIN_PFRCP,
25789 IX86_BUILTIN_PFRCPIT1,
25790 IX86_BUILTIN_PFRCPIT2,
25791 IX86_BUILTIN_PFRSQIT1,
25792 IX86_BUILTIN_PFRSQRT,
25793 IX86_BUILTIN_PFSUB,
25794 IX86_BUILTIN_PFSUBR,
25795 IX86_BUILTIN_PI2FD,
25796 IX86_BUILTIN_PMULHRW,
25798 /* 3DNow! Athlon Extensions */
25799 IX86_BUILTIN_PF2IW,
25800 IX86_BUILTIN_PFNACC,
25801 IX86_BUILTIN_PFPNACC,
25802 IX86_BUILTIN_PI2FW,
25803 IX86_BUILTIN_PSWAPDSI,
25804 IX86_BUILTIN_PSWAPDSF,
25806 /* SSE2 */
25807 IX86_BUILTIN_ADDPD,
25808 IX86_BUILTIN_ADDSD,
25809 IX86_BUILTIN_DIVPD,
25810 IX86_BUILTIN_DIVSD,
25811 IX86_BUILTIN_MULPD,
25812 IX86_BUILTIN_MULSD,
25813 IX86_BUILTIN_SUBPD,
25814 IX86_BUILTIN_SUBSD,
25816 IX86_BUILTIN_CMPEQPD,
25817 IX86_BUILTIN_CMPLTPD,
25818 IX86_BUILTIN_CMPLEPD,
25819 IX86_BUILTIN_CMPGTPD,
25820 IX86_BUILTIN_CMPGEPD,
25821 IX86_BUILTIN_CMPNEQPD,
25822 IX86_BUILTIN_CMPNLTPD,
25823 IX86_BUILTIN_CMPNLEPD,
25824 IX86_BUILTIN_CMPNGTPD,
25825 IX86_BUILTIN_CMPNGEPD,
25826 IX86_BUILTIN_CMPORDPD,
25827 IX86_BUILTIN_CMPUNORDPD,
25828 IX86_BUILTIN_CMPEQSD,
25829 IX86_BUILTIN_CMPLTSD,
25830 IX86_BUILTIN_CMPLESD,
25831 IX86_BUILTIN_CMPNEQSD,
25832 IX86_BUILTIN_CMPNLTSD,
25833 IX86_BUILTIN_CMPNLESD,
25834 IX86_BUILTIN_CMPORDSD,
25835 IX86_BUILTIN_CMPUNORDSD,
25837 IX86_BUILTIN_COMIEQSD,
25838 IX86_BUILTIN_COMILTSD,
25839 IX86_BUILTIN_COMILESD,
25840 IX86_BUILTIN_COMIGTSD,
25841 IX86_BUILTIN_COMIGESD,
25842 IX86_BUILTIN_COMINEQSD,
25843 IX86_BUILTIN_UCOMIEQSD,
25844 IX86_BUILTIN_UCOMILTSD,
25845 IX86_BUILTIN_UCOMILESD,
25846 IX86_BUILTIN_UCOMIGTSD,
25847 IX86_BUILTIN_UCOMIGESD,
25848 IX86_BUILTIN_UCOMINEQSD,
25850 IX86_BUILTIN_MAXPD,
25851 IX86_BUILTIN_MAXSD,
25852 IX86_BUILTIN_MINPD,
25853 IX86_BUILTIN_MINSD,
25855 IX86_BUILTIN_ANDPD,
25856 IX86_BUILTIN_ANDNPD,
25857 IX86_BUILTIN_ORPD,
25858 IX86_BUILTIN_XORPD,
25860 IX86_BUILTIN_SQRTPD,
25861 IX86_BUILTIN_SQRTSD,
25863 IX86_BUILTIN_UNPCKHPD,
25864 IX86_BUILTIN_UNPCKLPD,
25866 IX86_BUILTIN_SHUFPD,
25868 IX86_BUILTIN_LOADUPD,
25869 IX86_BUILTIN_STOREUPD,
25870 IX86_BUILTIN_MOVSD,
25872 IX86_BUILTIN_LOADHPD,
25873 IX86_BUILTIN_LOADLPD,
25875 IX86_BUILTIN_CVTDQ2PD,
25876 IX86_BUILTIN_CVTDQ2PS,
25878 IX86_BUILTIN_CVTPD2DQ,
25879 IX86_BUILTIN_CVTPD2PI,
25880 IX86_BUILTIN_CVTPD2PS,
25881 IX86_BUILTIN_CVTTPD2DQ,
25882 IX86_BUILTIN_CVTTPD2PI,
25884 IX86_BUILTIN_CVTPI2PD,
25885 IX86_BUILTIN_CVTSI2SD,
25886 IX86_BUILTIN_CVTSI642SD,
25888 IX86_BUILTIN_CVTSD2SI,
25889 IX86_BUILTIN_CVTSD2SI64,
25890 IX86_BUILTIN_CVTSD2SS,
25891 IX86_BUILTIN_CVTSS2SD,
25892 IX86_BUILTIN_CVTTSD2SI,
25893 IX86_BUILTIN_CVTTSD2SI64,
25895 IX86_BUILTIN_CVTPS2DQ,
25896 IX86_BUILTIN_CVTPS2PD,
25897 IX86_BUILTIN_CVTTPS2DQ,
25899 IX86_BUILTIN_MOVNTI,
25900 IX86_BUILTIN_MOVNTI64,
25901 IX86_BUILTIN_MOVNTPD,
25902 IX86_BUILTIN_MOVNTDQ,
25904 IX86_BUILTIN_MOVQ128,
25906 /* SSE2 MMX */
25907 IX86_BUILTIN_MASKMOVDQU,
25908 IX86_BUILTIN_MOVMSKPD,
25909 IX86_BUILTIN_PMOVMSKB128,
25911 IX86_BUILTIN_PACKSSWB128,
25912 IX86_BUILTIN_PACKSSDW128,
25913 IX86_BUILTIN_PACKUSWB128,
25915 IX86_BUILTIN_PADDB128,
25916 IX86_BUILTIN_PADDW128,
25917 IX86_BUILTIN_PADDD128,
25918 IX86_BUILTIN_PADDQ128,
25919 IX86_BUILTIN_PADDSB128,
25920 IX86_BUILTIN_PADDSW128,
25921 IX86_BUILTIN_PADDUSB128,
25922 IX86_BUILTIN_PADDUSW128,
25923 IX86_BUILTIN_PSUBB128,
25924 IX86_BUILTIN_PSUBW128,
25925 IX86_BUILTIN_PSUBD128,
25926 IX86_BUILTIN_PSUBQ128,
25927 IX86_BUILTIN_PSUBSB128,
25928 IX86_BUILTIN_PSUBSW128,
25929 IX86_BUILTIN_PSUBUSB128,
25930 IX86_BUILTIN_PSUBUSW128,
25932 IX86_BUILTIN_PAND128,
25933 IX86_BUILTIN_PANDN128,
25934 IX86_BUILTIN_POR128,
25935 IX86_BUILTIN_PXOR128,
25937 IX86_BUILTIN_PAVGB128,
25938 IX86_BUILTIN_PAVGW128,
25940 IX86_BUILTIN_PCMPEQB128,
25941 IX86_BUILTIN_PCMPEQW128,
25942 IX86_BUILTIN_PCMPEQD128,
25943 IX86_BUILTIN_PCMPGTB128,
25944 IX86_BUILTIN_PCMPGTW128,
25945 IX86_BUILTIN_PCMPGTD128,
25947 IX86_BUILTIN_PMADDWD128,
25949 IX86_BUILTIN_PMAXSW128,
25950 IX86_BUILTIN_PMAXUB128,
25951 IX86_BUILTIN_PMINSW128,
25952 IX86_BUILTIN_PMINUB128,
25954 IX86_BUILTIN_PMULUDQ,
25955 IX86_BUILTIN_PMULUDQ128,
25956 IX86_BUILTIN_PMULHUW128,
25957 IX86_BUILTIN_PMULHW128,
25958 IX86_BUILTIN_PMULLW128,
25960 IX86_BUILTIN_PSADBW128,
25961 IX86_BUILTIN_PSHUFHW,
25962 IX86_BUILTIN_PSHUFLW,
25963 IX86_BUILTIN_PSHUFD,
25965 IX86_BUILTIN_PSLLDQI128,
25966 IX86_BUILTIN_PSLLWI128,
25967 IX86_BUILTIN_PSLLDI128,
25968 IX86_BUILTIN_PSLLQI128,
25969 IX86_BUILTIN_PSRAWI128,
25970 IX86_BUILTIN_PSRADI128,
25971 IX86_BUILTIN_PSRLDQI128,
25972 IX86_BUILTIN_PSRLWI128,
25973 IX86_BUILTIN_PSRLDI128,
25974 IX86_BUILTIN_PSRLQI128,
25976 IX86_BUILTIN_PSLLDQ128,
25977 IX86_BUILTIN_PSLLW128,
25978 IX86_BUILTIN_PSLLD128,
25979 IX86_BUILTIN_PSLLQ128,
25980 IX86_BUILTIN_PSRAW128,
25981 IX86_BUILTIN_PSRAD128,
25982 IX86_BUILTIN_PSRLW128,
25983 IX86_BUILTIN_PSRLD128,
25984 IX86_BUILTIN_PSRLQ128,
25986 IX86_BUILTIN_PUNPCKHBW128,
25987 IX86_BUILTIN_PUNPCKHWD128,
25988 IX86_BUILTIN_PUNPCKHDQ128,
25989 IX86_BUILTIN_PUNPCKHQDQ128,
25990 IX86_BUILTIN_PUNPCKLBW128,
25991 IX86_BUILTIN_PUNPCKLWD128,
25992 IX86_BUILTIN_PUNPCKLDQ128,
25993 IX86_BUILTIN_PUNPCKLQDQ128,
25995 IX86_BUILTIN_CLFLUSH,
25996 IX86_BUILTIN_MFENCE,
25997 IX86_BUILTIN_LFENCE,
25998 IX86_BUILTIN_PAUSE,
26000 IX86_BUILTIN_BSRSI,
26001 IX86_BUILTIN_BSRDI,
26002 IX86_BUILTIN_RDPMC,
26003 IX86_BUILTIN_RDTSC,
26004 IX86_BUILTIN_RDTSCP,
26005 IX86_BUILTIN_ROLQI,
26006 IX86_BUILTIN_ROLHI,
26007 IX86_BUILTIN_RORQI,
26008 IX86_BUILTIN_RORHI,
26010 /* SSE3. */
26011 IX86_BUILTIN_ADDSUBPS,
26012 IX86_BUILTIN_HADDPS,
26013 IX86_BUILTIN_HSUBPS,
26014 IX86_BUILTIN_MOVSHDUP,
26015 IX86_BUILTIN_MOVSLDUP,
26016 IX86_BUILTIN_ADDSUBPD,
26017 IX86_BUILTIN_HADDPD,
26018 IX86_BUILTIN_HSUBPD,
26019 IX86_BUILTIN_LDDQU,
26021 IX86_BUILTIN_MONITOR,
26022 IX86_BUILTIN_MWAIT,
26024 /* SSSE3. */
26025 IX86_BUILTIN_PHADDW,
26026 IX86_BUILTIN_PHADDD,
26027 IX86_BUILTIN_PHADDSW,
26028 IX86_BUILTIN_PHSUBW,
26029 IX86_BUILTIN_PHSUBD,
26030 IX86_BUILTIN_PHSUBSW,
26031 IX86_BUILTIN_PMADDUBSW,
26032 IX86_BUILTIN_PMULHRSW,
26033 IX86_BUILTIN_PSHUFB,
26034 IX86_BUILTIN_PSIGNB,
26035 IX86_BUILTIN_PSIGNW,
26036 IX86_BUILTIN_PSIGND,
26037 IX86_BUILTIN_PALIGNR,
26038 IX86_BUILTIN_PABSB,
26039 IX86_BUILTIN_PABSW,
26040 IX86_BUILTIN_PABSD,
26042 IX86_BUILTIN_PHADDW128,
26043 IX86_BUILTIN_PHADDD128,
26044 IX86_BUILTIN_PHADDSW128,
26045 IX86_BUILTIN_PHSUBW128,
26046 IX86_BUILTIN_PHSUBD128,
26047 IX86_BUILTIN_PHSUBSW128,
26048 IX86_BUILTIN_PMADDUBSW128,
26049 IX86_BUILTIN_PMULHRSW128,
26050 IX86_BUILTIN_PSHUFB128,
26051 IX86_BUILTIN_PSIGNB128,
26052 IX86_BUILTIN_PSIGNW128,
26053 IX86_BUILTIN_PSIGND128,
26054 IX86_BUILTIN_PALIGNR128,
26055 IX86_BUILTIN_PABSB128,
26056 IX86_BUILTIN_PABSW128,
26057 IX86_BUILTIN_PABSD128,
26059 /* AMDFAM10 - SSE4A New Instructions. */
26060 IX86_BUILTIN_MOVNTSD,
26061 IX86_BUILTIN_MOVNTSS,
26062 IX86_BUILTIN_EXTRQI,
26063 IX86_BUILTIN_EXTRQ,
26064 IX86_BUILTIN_INSERTQI,
26065 IX86_BUILTIN_INSERTQ,
26067 /* SSE4.1. */
26068 IX86_BUILTIN_BLENDPD,
26069 IX86_BUILTIN_BLENDPS,
26070 IX86_BUILTIN_BLENDVPD,
26071 IX86_BUILTIN_BLENDVPS,
26072 IX86_BUILTIN_PBLENDVB128,
26073 IX86_BUILTIN_PBLENDW128,
26075 IX86_BUILTIN_DPPD,
26076 IX86_BUILTIN_DPPS,
26078 IX86_BUILTIN_INSERTPS128,
26080 IX86_BUILTIN_MOVNTDQA,
26081 IX86_BUILTIN_MPSADBW128,
26082 IX86_BUILTIN_PACKUSDW128,
26083 IX86_BUILTIN_PCMPEQQ,
26084 IX86_BUILTIN_PHMINPOSUW128,
26086 IX86_BUILTIN_PMAXSB128,
26087 IX86_BUILTIN_PMAXSD128,
26088 IX86_BUILTIN_PMAXUD128,
26089 IX86_BUILTIN_PMAXUW128,
26091 IX86_BUILTIN_PMINSB128,
26092 IX86_BUILTIN_PMINSD128,
26093 IX86_BUILTIN_PMINUD128,
26094 IX86_BUILTIN_PMINUW128,
26096 IX86_BUILTIN_PMOVSXBW128,
26097 IX86_BUILTIN_PMOVSXBD128,
26098 IX86_BUILTIN_PMOVSXBQ128,
26099 IX86_BUILTIN_PMOVSXWD128,
26100 IX86_BUILTIN_PMOVSXWQ128,
26101 IX86_BUILTIN_PMOVSXDQ128,
26103 IX86_BUILTIN_PMOVZXBW128,
26104 IX86_BUILTIN_PMOVZXBD128,
26105 IX86_BUILTIN_PMOVZXBQ128,
26106 IX86_BUILTIN_PMOVZXWD128,
26107 IX86_BUILTIN_PMOVZXWQ128,
26108 IX86_BUILTIN_PMOVZXDQ128,
26110 IX86_BUILTIN_PMULDQ128,
26111 IX86_BUILTIN_PMULLD128,
26113 IX86_BUILTIN_ROUNDSD,
26114 IX86_BUILTIN_ROUNDSS,
26116 IX86_BUILTIN_ROUNDPD,
26117 IX86_BUILTIN_ROUNDPS,
26119 IX86_BUILTIN_FLOORPD,
26120 IX86_BUILTIN_CEILPD,
26121 IX86_BUILTIN_TRUNCPD,
26122 IX86_BUILTIN_RINTPD,
26123 IX86_BUILTIN_ROUNDPD_AZ,
26125 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
26126 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
26127 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
26129 IX86_BUILTIN_FLOORPS,
26130 IX86_BUILTIN_CEILPS,
26131 IX86_BUILTIN_TRUNCPS,
26132 IX86_BUILTIN_RINTPS,
26133 IX86_BUILTIN_ROUNDPS_AZ,
26135 IX86_BUILTIN_FLOORPS_SFIX,
26136 IX86_BUILTIN_CEILPS_SFIX,
26137 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
26139 IX86_BUILTIN_PTESTZ,
26140 IX86_BUILTIN_PTESTC,
26141 IX86_BUILTIN_PTESTNZC,
26143 IX86_BUILTIN_VEC_INIT_V2SI,
26144 IX86_BUILTIN_VEC_INIT_V4HI,
26145 IX86_BUILTIN_VEC_INIT_V8QI,
26146 IX86_BUILTIN_VEC_EXT_V2DF,
26147 IX86_BUILTIN_VEC_EXT_V2DI,
26148 IX86_BUILTIN_VEC_EXT_V4SF,
26149 IX86_BUILTIN_VEC_EXT_V4SI,
26150 IX86_BUILTIN_VEC_EXT_V8HI,
26151 IX86_BUILTIN_VEC_EXT_V2SI,
26152 IX86_BUILTIN_VEC_EXT_V4HI,
26153 IX86_BUILTIN_VEC_EXT_V16QI,
26154 IX86_BUILTIN_VEC_SET_V2DI,
26155 IX86_BUILTIN_VEC_SET_V4SF,
26156 IX86_BUILTIN_VEC_SET_V4SI,
26157 IX86_BUILTIN_VEC_SET_V8HI,
26158 IX86_BUILTIN_VEC_SET_V4HI,
26159 IX86_BUILTIN_VEC_SET_V16QI,
26161 IX86_BUILTIN_VEC_PACK_SFIX,
26162 IX86_BUILTIN_VEC_PACK_SFIX256,
26164 /* SSE4.2. */
26165 IX86_BUILTIN_CRC32QI,
26166 IX86_BUILTIN_CRC32HI,
26167 IX86_BUILTIN_CRC32SI,
26168 IX86_BUILTIN_CRC32DI,
26170 IX86_BUILTIN_PCMPESTRI128,
26171 IX86_BUILTIN_PCMPESTRM128,
26172 IX86_BUILTIN_PCMPESTRA128,
26173 IX86_BUILTIN_PCMPESTRC128,
26174 IX86_BUILTIN_PCMPESTRO128,
26175 IX86_BUILTIN_PCMPESTRS128,
26176 IX86_BUILTIN_PCMPESTRZ128,
26177 IX86_BUILTIN_PCMPISTRI128,
26178 IX86_BUILTIN_PCMPISTRM128,
26179 IX86_BUILTIN_PCMPISTRA128,
26180 IX86_BUILTIN_PCMPISTRC128,
26181 IX86_BUILTIN_PCMPISTRO128,
26182 IX86_BUILTIN_PCMPISTRS128,
26183 IX86_BUILTIN_PCMPISTRZ128,
26185 IX86_BUILTIN_PCMPGTQ,
26187 /* AES instructions */
26188 IX86_BUILTIN_AESENC128,
26189 IX86_BUILTIN_AESENCLAST128,
26190 IX86_BUILTIN_AESDEC128,
26191 IX86_BUILTIN_AESDECLAST128,
26192 IX86_BUILTIN_AESIMC128,
26193 IX86_BUILTIN_AESKEYGENASSIST128,
26195 /* PCLMUL instruction */
26196 IX86_BUILTIN_PCLMULQDQ128,
26198 /* AVX */
26199 IX86_BUILTIN_ADDPD256,
26200 IX86_BUILTIN_ADDPS256,
26201 IX86_BUILTIN_ADDSUBPD256,
26202 IX86_BUILTIN_ADDSUBPS256,
26203 IX86_BUILTIN_ANDPD256,
26204 IX86_BUILTIN_ANDPS256,
26205 IX86_BUILTIN_ANDNPD256,
26206 IX86_BUILTIN_ANDNPS256,
26207 IX86_BUILTIN_BLENDPD256,
26208 IX86_BUILTIN_BLENDPS256,
26209 IX86_BUILTIN_BLENDVPD256,
26210 IX86_BUILTIN_BLENDVPS256,
26211 IX86_BUILTIN_DIVPD256,
26212 IX86_BUILTIN_DIVPS256,
26213 IX86_BUILTIN_DPPS256,
26214 IX86_BUILTIN_HADDPD256,
26215 IX86_BUILTIN_HADDPS256,
26216 IX86_BUILTIN_HSUBPD256,
26217 IX86_BUILTIN_HSUBPS256,
26218 IX86_BUILTIN_MAXPD256,
26219 IX86_BUILTIN_MAXPS256,
26220 IX86_BUILTIN_MINPD256,
26221 IX86_BUILTIN_MINPS256,
26222 IX86_BUILTIN_MULPD256,
26223 IX86_BUILTIN_MULPS256,
26224 IX86_BUILTIN_ORPD256,
26225 IX86_BUILTIN_ORPS256,
26226 IX86_BUILTIN_SHUFPD256,
26227 IX86_BUILTIN_SHUFPS256,
26228 IX86_BUILTIN_SUBPD256,
26229 IX86_BUILTIN_SUBPS256,
26230 IX86_BUILTIN_XORPD256,
26231 IX86_BUILTIN_XORPS256,
26232 IX86_BUILTIN_CMPSD,
26233 IX86_BUILTIN_CMPSS,
26234 IX86_BUILTIN_CMPPD,
26235 IX86_BUILTIN_CMPPS,
26236 IX86_BUILTIN_CMPPD256,
26237 IX86_BUILTIN_CMPPS256,
26238 IX86_BUILTIN_CVTDQ2PD256,
26239 IX86_BUILTIN_CVTDQ2PS256,
26240 IX86_BUILTIN_CVTPD2PS256,
26241 IX86_BUILTIN_CVTPS2DQ256,
26242 IX86_BUILTIN_CVTPS2PD256,
26243 IX86_BUILTIN_CVTTPD2DQ256,
26244 IX86_BUILTIN_CVTPD2DQ256,
26245 IX86_BUILTIN_CVTTPS2DQ256,
26246 IX86_BUILTIN_EXTRACTF128PD256,
26247 IX86_BUILTIN_EXTRACTF128PS256,
26248 IX86_BUILTIN_EXTRACTF128SI256,
26249 IX86_BUILTIN_VZEROALL,
26250 IX86_BUILTIN_VZEROUPPER,
26251 IX86_BUILTIN_VPERMILVARPD,
26252 IX86_BUILTIN_VPERMILVARPS,
26253 IX86_BUILTIN_VPERMILVARPD256,
26254 IX86_BUILTIN_VPERMILVARPS256,
26255 IX86_BUILTIN_VPERMILPD,
26256 IX86_BUILTIN_VPERMILPS,
26257 IX86_BUILTIN_VPERMILPD256,
26258 IX86_BUILTIN_VPERMILPS256,
26259 IX86_BUILTIN_VPERMIL2PD,
26260 IX86_BUILTIN_VPERMIL2PS,
26261 IX86_BUILTIN_VPERMIL2PD256,
26262 IX86_BUILTIN_VPERMIL2PS256,
26263 IX86_BUILTIN_VPERM2F128PD256,
26264 IX86_BUILTIN_VPERM2F128PS256,
26265 IX86_BUILTIN_VPERM2F128SI256,
26266 IX86_BUILTIN_VBROADCASTSS,
26267 IX86_BUILTIN_VBROADCASTSD256,
26268 IX86_BUILTIN_VBROADCASTSS256,
26269 IX86_BUILTIN_VBROADCASTPD256,
26270 IX86_BUILTIN_VBROADCASTPS256,
26271 IX86_BUILTIN_VINSERTF128PD256,
26272 IX86_BUILTIN_VINSERTF128PS256,
26273 IX86_BUILTIN_VINSERTF128SI256,
26274 IX86_BUILTIN_LOADUPD256,
26275 IX86_BUILTIN_LOADUPS256,
26276 IX86_BUILTIN_STOREUPD256,
26277 IX86_BUILTIN_STOREUPS256,
26278 IX86_BUILTIN_LDDQU256,
26279 IX86_BUILTIN_MOVNTDQ256,
26280 IX86_BUILTIN_MOVNTPD256,
26281 IX86_BUILTIN_MOVNTPS256,
26282 IX86_BUILTIN_LOADDQU256,
26283 IX86_BUILTIN_STOREDQU256,
26284 IX86_BUILTIN_MASKLOADPD,
26285 IX86_BUILTIN_MASKLOADPS,
26286 IX86_BUILTIN_MASKSTOREPD,
26287 IX86_BUILTIN_MASKSTOREPS,
26288 IX86_BUILTIN_MASKLOADPD256,
26289 IX86_BUILTIN_MASKLOADPS256,
26290 IX86_BUILTIN_MASKSTOREPD256,
26291 IX86_BUILTIN_MASKSTOREPS256,
26292 IX86_BUILTIN_MOVSHDUP256,
26293 IX86_BUILTIN_MOVSLDUP256,
26294 IX86_BUILTIN_MOVDDUP256,
26296 IX86_BUILTIN_SQRTPD256,
26297 IX86_BUILTIN_SQRTPS256,
26298 IX86_BUILTIN_SQRTPS_NR256,
26299 IX86_BUILTIN_RSQRTPS256,
26300 IX86_BUILTIN_RSQRTPS_NR256,
26302 IX86_BUILTIN_RCPPS256,
26304 IX86_BUILTIN_ROUNDPD256,
26305 IX86_BUILTIN_ROUNDPS256,
26307 IX86_BUILTIN_FLOORPD256,
26308 IX86_BUILTIN_CEILPD256,
26309 IX86_BUILTIN_TRUNCPD256,
26310 IX86_BUILTIN_RINTPD256,
26311 IX86_BUILTIN_ROUNDPD_AZ256,
26313 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
26314 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
26315 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
26317 IX86_BUILTIN_FLOORPS256,
26318 IX86_BUILTIN_CEILPS256,
26319 IX86_BUILTIN_TRUNCPS256,
26320 IX86_BUILTIN_RINTPS256,
26321 IX86_BUILTIN_ROUNDPS_AZ256,
26323 IX86_BUILTIN_FLOORPS_SFIX256,
26324 IX86_BUILTIN_CEILPS_SFIX256,
26325 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
26327 IX86_BUILTIN_UNPCKHPD256,
26328 IX86_BUILTIN_UNPCKLPD256,
26329 IX86_BUILTIN_UNPCKHPS256,
26330 IX86_BUILTIN_UNPCKLPS256,
26332 IX86_BUILTIN_SI256_SI,
26333 IX86_BUILTIN_PS256_PS,
26334 IX86_BUILTIN_PD256_PD,
26335 IX86_BUILTIN_SI_SI256,
26336 IX86_BUILTIN_PS_PS256,
26337 IX86_BUILTIN_PD_PD256,
26339 IX86_BUILTIN_VTESTZPD,
26340 IX86_BUILTIN_VTESTCPD,
26341 IX86_BUILTIN_VTESTNZCPD,
26342 IX86_BUILTIN_VTESTZPS,
26343 IX86_BUILTIN_VTESTCPS,
26344 IX86_BUILTIN_VTESTNZCPS,
26345 IX86_BUILTIN_VTESTZPD256,
26346 IX86_BUILTIN_VTESTCPD256,
26347 IX86_BUILTIN_VTESTNZCPD256,
26348 IX86_BUILTIN_VTESTZPS256,
26349 IX86_BUILTIN_VTESTCPS256,
26350 IX86_BUILTIN_VTESTNZCPS256,
26351 IX86_BUILTIN_PTESTZ256,
26352 IX86_BUILTIN_PTESTC256,
26353 IX86_BUILTIN_PTESTNZC256,
26355 IX86_BUILTIN_MOVMSKPD256,
26356 IX86_BUILTIN_MOVMSKPS256,
26358 /* AVX2 */
26359 IX86_BUILTIN_MPSADBW256,
26360 IX86_BUILTIN_PABSB256,
26361 IX86_BUILTIN_PABSW256,
26362 IX86_BUILTIN_PABSD256,
26363 IX86_BUILTIN_PACKSSDW256,
26364 IX86_BUILTIN_PACKSSWB256,
26365 IX86_BUILTIN_PACKUSDW256,
26366 IX86_BUILTIN_PACKUSWB256,
26367 IX86_BUILTIN_PADDB256,
26368 IX86_BUILTIN_PADDW256,
26369 IX86_BUILTIN_PADDD256,
26370 IX86_BUILTIN_PADDQ256,
26371 IX86_BUILTIN_PADDSB256,
26372 IX86_BUILTIN_PADDSW256,
26373 IX86_BUILTIN_PADDUSB256,
26374 IX86_BUILTIN_PADDUSW256,
26375 IX86_BUILTIN_PALIGNR256,
26376 IX86_BUILTIN_AND256I,
26377 IX86_BUILTIN_ANDNOT256I,
26378 IX86_BUILTIN_PAVGB256,
26379 IX86_BUILTIN_PAVGW256,
26380 IX86_BUILTIN_PBLENDVB256,
26381 IX86_BUILTIN_PBLENDVW256,
26382 IX86_BUILTIN_PCMPEQB256,
26383 IX86_BUILTIN_PCMPEQW256,
26384 IX86_BUILTIN_PCMPEQD256,
26385 IX86_BUILTIN_PCMPEQQ256,
26386 IX86_BUILTIN_PCMPGTB256,
26387 IX86_BUILTIN_PCMPGTW256,
26388 IX86_BUILTIN_PCMPGTD256,
26389 IX86_BUILTIN_PCMPGTQ256,
26390 IX86_BUILTIN_PHADDW256,
26391 IX86_BUILTIN_PHADDD256,
26392 IX86_BUILTIN_PHADDSW256,
26393 IX86_BUILTIN_PHSUBW256,
26394 IX86_BUILTIN_PHSUBD256,
26395 IX86_BUILTIN_PHSUBSW256,
26396 IX86_BUILTIN_PMADDUBSW256,
26397 IX86_BUILTIN_PMADDWD256,
26398 IX86_BUILTIN_PMAXSB256,
26399 IX86_BUILTIN_PMAXSW256,
26400 IX86_BUILTIN_PMAXSD256,
26401 IX86_BUILTIN_PMAXUB256,
26402 IX86_BUILTIN_PMAXUW256,
26403 IX86_BUILTIN_PMAXUD256,
26404 IX86_BUILTIN_PMINSB256,
26405 IX86_BUILTIN_PMINSW256,
26406 IX86_BUILTIN_PMINSD256,
26407 IX86_BUILTIN_PMINUB256,
26408 IX86_BUILTIN_PMINUW256,
26409 IX86_BUILTIN_PMINUD256,
26410 IX86_BUILTIN_PMOVMSKB256,
26411 IX86_BUILTIN_PMOVSXBW256,
26412 IX86_BUILTIN_PMOVSXBD256,
26413 IX86_BUILTIN_PMOVSXBQ256,
26414 IX86_BUILTIN_PMOVSXWD256,
26415 IX86_BUILTIN_PMOVSXWQ256,
26416 IX86_BUILTIN_PMOVSXDQ256,
26417 IX86_BUILTIN_PMOVZXBW256,
26418 IX86_BUILTIN_PMOVZXBD256,
26419 IX86_BUILTIN_PMOVZXBQ256,
26420 IX86_BUILTIN_PMOVZXWD256,
26421 IX86_BUILTIN_PMOVZXWQ256,
26422 IX86_BUILTIN_PMOVZXDQ256,
26423 IX86_BUILTIN_PMULDQ256,
26424 IX86_BUILTIN_PMULHRSW256,
26425 IX86_BUILTIN_PMULHUW256,
26426 IX86_BUILTIN_PMULHW256,
26427 IX86_BUILTIN_PMULLW256,
26428 IX86_BUILTIN_PMULLD256,
26429 IX86_BUILTIN_PMULUDQ256,
26430 IX86_BUILTIN_POR256,
26431 IX86_BUILTIN_PSADBW256,
26432 IX86_BUILTIN_PSHUFB256,
26433 IX86_BUILTIN_PSHUFD256,
26434 IX86_BUILTIN_PSHUFHW256,
26435 IX86_BUILTIN_PSHUFLW256,
26436 IX86_BUILTIN_PSIGNB256,
26437 IX86_BUILTIN_PSIGNW256,
26438 IX86_BUILTIN_PSIGND256,
26439 IX86_BUILTIN_PSLLDQI256,
26440 IX86_BUILTIN_PSLLWI256,
26441 IX86_BUILTIN_PSLLW256,
26442 IX86_BUILTIN_PSLLDI256,
26443 IX86_BUILTIN_PSLLD256,
26444 IX86_BUILTIN_PSLLQI256,
26445 IX86_BUILTIN_PSLLQ256,
26446 IX86_BUILTIN_PSRAWI256,
26447 IX86_BUILTIN_PSRAW256,
26448 IX86_BUILTIN_PSRADI256,
26449 IX86_BUILTIN_PSRAD256,
26450 IX86_BUILTIN_PSRLDQI256,
26451 IX86_BUILTIN_PSRLWI256,
26452 IX86_BUILTIN_PSRLW256,
26453 IX86_BUILTIN_PSRLDI256,
26454 IX86_BUILTIN_PSRLD256,
26455 IX86_BUILTIN_PSRLQI256,
26456 IX86_BUILTIN_PSRLQ256,
26457 IX86_BUILTIN_PSUBB256,
26458 IX86_BUILTIN_PSUBW256,
26459 IX86_BUILTIN_PSUBD256,
26460 IX86_BUILTIN_PSUBQ256,
26461 IX86_BUILTIN_PSUBSB256,
26462 IX86_BUILTIN_PSUBSW256,
26463 IX86_BUILTIN_PSUBUSB256,
26464 IX86_BUILTIN_PSUBUSW256,
26465 IX86_BUILTIN_PUNPCKHBW256,
26466 IX86_BUILTIN_PUNPCKHWD256,
26467 IX86_BUILTIN_PUNPCKHDQ256,
26468 IX86_BUILTIN_PUNPCKHQDQ256,
26469 IX86_BUILTIN_PUNPCKLBW256,
26470 IX86_BUILTIN_PUNPCKLWD256,
26471 IX86_BUILTIN_PUNPCKLDQ256,
26472 IX86_BUILTIN_PUNPCKLQDQ256,
26473 IX86_BUILTIN_PXOR256,
26474 IX86_BUILTIN_MOVNTDQA256,
26475 IX86_BUILTIN_VBROADCASTSS_PS,
26476 IX86_BUILTIN_VBROADCASTSS_PS256,
26477 IX86_BUILTIN_VBROADCASTSD_PD256,
26478 IX86_BUILTIN_VBROADCASTSI256,
26479 IX86_BUILTIN_PBLENDD256,
26480 IX86_BUILTIN_PBLENDD128,
26481 IX86_BUILTIN_PBROADCASTB256,
26482 IX86_BUILTIN_PBROADCASTW256,
26483 IX86_BUILTIN_PBROADCASTD256,
26484 IX86_BUILTIN_PBROADCASTQ256,
26485 IX86_BUILTIN_PBROADCASTB128,
26486 IX86_BUILTIN_PBROADCASTW128,
26487 IX86_BUILTIN_PBROADCASTD128,
26488 IX86_BUILTIN_PBROADCASTQ128,
26489 IX86_BUILTIN_VPERMVARSI256,
26490 IX86_BUILTIN_VPERMDF256,
26491 IX86_BUILTIN_VPERMVARSF256,
26492 IX86_BUILTIN_VPERMDI256,
26493 IX86_BUILTIN_VPERMTI256,
26494 IX86_BUILTIN_VEXTRACT128I256,
26495 IX86_BUILTIN_VINSERT128I256,
26496 IX86_BUILTIN_MASKLOADD,
26497 IX86_BUILTIN_MASKLOADQ,
26498 IX86_BUILTIN_MASKLOADD256,
26499 IX86_BUILTIN_MASKLOADQ256,
26500 IX86_BUILTIN_MASKSTORED,
26501 IX86_BUILTIN_MASKSTOREQ,
26502 IX86_BUILTIN_MASKSTORED256,
26503 IX86_BUILTIN_MASKSTOREQ256,
26504 IX86_BUILTIN_PSLLVV4DI,
26505 IX86_BUILTIN_PSLLVV2DI,
26506 IX86_BUILTIN_PSLLVV8SI,
26507 IX86_BUILTIN_PSLLVV4SI,
26508 IX86_BUILTIN_PSRAVV8SI,
26509 IX86_BUILTIN_PSRAVV4SI,
26510 IX86_BUILTIN_PSRLVV4DI,
26511 IX86_BUILTIN_PSRLVV2DI,
26512 IX86_BUILTIN_PSRLVV8SI,
26513 IX86_BUILTIN_PSRLVV4SI,
26515 IX86_BUILTIN_GATHERSIV2DF,
26516 IX86_BUILTIN_GATHERSIV4DF,
26517 IX86_BUILTIN_GATHERDIV2DF,
26518 IX86_BUILTIN_GATHERDIV4DF,
26519 IX86_BUILTIN_GATHERSIV4SF,
26520 IX86_BUILTIN_GATHERSIV8SF,
26521 IX86_BUILTIN_GATHERDIV4SF,
26522 IX86_BUILTIN_GATHERDIV8SF,
26523 IX86_BUILTIN_GATHERSIV2DI,
26524 IX86_BUILTIN_GATHERSIV4DI,
26525 IX86_BUILTIN_GATHERDIV2DI,
26526 IX86_BUILTIN_GATHERDIV4DI,
26527 IX86_BUILTIN_GATHERSIV4SI,
26528 IX86_BUILTIN_GATHERSIV8SI,
26529 IX86_BUILTIN_GATHERDIV4SI,
26530 IX86_BUILTIN_GATHERDIV8SI,
26532 /* Alternate 4 element gather for the vectorizer where
26533 all operands are 32-byte wide. */
26534 IX86_BUILTIN_GATHERALTSIV4DF,
26535 IX86_BUILTIN_GATHERALTDIV8SF,
26536 IX86_BUILTIN_GATHERALTSIV4DI,
26537 IX86_BUILTIN_GATHERALTDIV8SI,
26539 /* TFmode support builtins. */
26540 IX86_BUILTIN_INFQ,
26541 IX86_BUILTIN_HUGE_VALQ,
26542 IX86_BUILTIN_FABSQ,
26543 IX86_BUILTIN_COPYSIGNQ,
26545 /* Vectorizer support builtins. */
26546 IX86_BUILTIN_CPYSGNPS,
26547 IX86_BUILTIN_CPYSGNPD,
26548 IX86_BUILTIN_CPYSGNPS256,
26549 IX86_BUILTIN_CPYSGNPD256,
26551 /* FMA4 instructions. */
26552 IX86_BUILTIN_VFMADDSS,
26553 IX86_BUILTIN_VFMADDSD,
26554 IX86_BUILTIN_VFMADDPS,
26555 IX86_BUILTIN_VFMADDPD,
26556 IX86_BUILTIN_VFMADDPS256,
26557 IX86_BUILTIN_VFMADDPD256,
26558 IX86_BUILTIN_VFMADDSUBPS,
26559 IX86_BUILTIN_VFMADDSUBPD,
26560 IX86_BUILTIN_VFMADDSUBPS256,
26561 IX86_BUILTIN_VFMADDSUBPD256,
26563 /* FMA3 instructions. */
26564 IX86_BUILTIN_VFMADDSS3,
26565 IX86_BUILTIN_VFMADDSD3,
26567 /* XOP instructions. */
26568 IX86_BUILTIN_VPCMOV,
26569 IX86_BUILTIN_VPCMOV_V2DI,
26570 IX86_BUILTIN_VPCMOV_V4SI,
26571 IX86_BUILTIN_VPCMOV_V8HI,
26572 IX86_BUILTIN_VPCMOV_V16QI,
26573 IX86_BUILTIN_VPCMOV_V4SF,
26574 IX86_BUILTIN_VPCMOV_V2DF,
26575 IX86_BUILTIN_VPCMOV256,
26576 IX86_BUILTIN_VPCMOV_V4DI256,
26577 IX86_BUILTIN_VPCMOV_V8SI256,
26578 IX86_BUILTIN_VPCMOV_V16HI256,
26579 IX86_BUILTIN_VPCMOV_V32QI256,
26580 IX86_BUILTIN_VPCMOV_V8SF256,
26581 IX86_BUILTIN_VPCMOV_V4DF256,
26583 IX86_BUILTIN_VPPERM,
26585 IX86_BUILTIN_VPMACSSWW,
26586 IX86_BUILTIN_VPMACSWW,
26587 IX86_BUILTIN_VPMACSSWD,
26588 IX86_BUILTIN_VPMACSWD,
26589 IX86_BUILTIN_VPMACSSDD,
26590 IX86_BUILTIN_VPMACSDD,
26591 IX86_BUILTIN_VPMACSSDQL,
26592 IX86_BUILTIN_VPMACSSDQH,
26593 IX86_BUILTIN_VPMACSDQL,
26594 IX86_BUILTIN_VPMACSDQH,
26595 IX86_BUILTIN_VPMADCSSWD,
26596 IX86_BUILTIN_VPMADCSWD,
26598 IX86_BUILTIN_VPHADDBW,
26599 IX86_BUILTIN_VPHADDBD,
26600 IX86_BUILTIN_VPHADDBQ,
26601 IX86_BUILTIN_VPHADDWD,
26602 IX86_BUILTIN_VPHADDWQ,
26603 IX86_BUILTIN_VPHADDDQ,
26604 IX86_BUILTIN_VPHADDUBW,
26605 IX86_BUILTIN_VPHADDUBD,
26606 IX86_BUILTIN_VPHADDUBQ,
26607 IX86_BUILTIN_VPHADDUWD,
26608 IX86_BUILTIN_VPHADDUWQ,
26609 IX86_BUILTIN_VPHADDUDQ,
26610 IX86_BUILTIN_VPHSUBBW,
26611 IX86_BUILTIN_VPHSUBWD,
26612 IX86_BUILTIN_VPHSUBDQ,
26614 IX86_BUILTIN_VPROTB,
26615 IX86_BUILTIN_VPROTW,
26616 IX86_BUILTIN_VPROTD,
26617 IX86_BUILTIN_VPROTQ,
26618 IX86_BUILTIN_VPROTB_IMM,
26619 IX86_BUILTIN_VPROTW_IMM,
26620 IX86_BUILTIN_VPROTD_IMM,
26621 IX86_BUILTIN_VPROTQ_IMM,
26623 IX86_BUILTIN_VPSHLB,
26624 IX86_BUILTIN_VPSHLW,
26625 IX86_BUILTIN_VPSHLD,
26626 IX86_BUILTIN_VPSHLQ,
26627 IX86_BUILTIN_VPSHAB,
26628 IX86_BUILTIN_VPSHAW,
26629 IX86_BUILTIN_VPSHAD,
26630 IX86_BUILTIN_VPSHAQ,
26632 IX86_BUILTIN_VFRCZSS,
26633 IX86_BUILTIN_VFRCZSD,
26634 IX86_BUILTIN_VFRCZPS,
26635 IX86_BUILTIN_VFRCZPD,
26636 IX86_BUILTIN_VFRCZPS256,
26637 IX86_BUILTIN_VFRCZPD256,
26639 IX86_BUILTIN_VPCOMEQUB,
26640 IX86_BUILTIN_VPCOMNEUB,
26641 IX86_BUILTIN_VPCOMLTUB,
26642 IX86_BUILTIN_VPCOMLEUB,
26643 IX86_BUILTIN_VPCOMGTUB,
26644 IX86_BUILTIN_VPCOMGEUB,
26645 IX86_BUILTIN_VPCOMFALSEUB,
26646 IX86_BUILTIN_VPCOMTRUEUB,
26648 IX86_BUILTIN_VPCOMEQUW,
26649 IX86_BUILTIN_VPCOMNEUW,
26650 IX86_BUILTIN_VPCOMLTUW,
26651 IX86_BUILTIN_VPCOMLEUW,
26652 IX86_BUILTIN_VPCOMGTUW,
26653 IX86_BUILTIN_VPCOMGEUW,
26654 IX86_BUILTIN_VPCOMFALSEUW,
26655 IX86_BUILTIN_VPCOMTRUEUW,
26657 IX86_BUILTIN_VPCOMEQUD,
26658 IX86_BUILTIN_VPCOMNEUD,
26659 IX86_BUILTIN_VPCOMLTUD,
26660 IX86_BUILTIN_VPCOMLEUD,
26661 IX86_BUILTIN_VPCOMGTUD,
26662 IX86_BUILTIN_VPCOMGEUD,
26663 IX86_BUILTIN_VPCOMFALSEUD,
26664 IX86_BUILTIN_VPCOMTRUEUD,
26666 IX86_BUILTIN_VPCOMEQUQ,
26667 IX86_BUILTIN_VPCOMNEUQ,
26668 IX86_BUILTIN_VPCOMLTUQ,
26669 IX86_BUILTIN_VPCOMLEUQ,
26670 IX86_BUILTIN_VPCOMGTUQ,
26671 IX86_BUILTIN_VPCOMGEUQ,
26672 IX86_BUILTIN_VPCOMFALSEUQ,
26673 IX86_BUILTIN_VPCOMTRUEUQ,
26675 IX86_BUILTIN_VPCOMEQB,
26676 IX86_BUILTIN_VPCOMNEB,
26677 IX86_BUILTIN_VPCOMLTB,
26678 IX86_BUILTIN_VPCOMLEB,
26679 IX86_BUILTIN_VPCOMGTB,
26680 IX86_BUILTIN_VPCOMGEB,
26681 IX86_BUILTIN_VPCOMFALSEB,
26682 IX86_BUILTIN_VPCOMTRUEB,
26684 IX86_BUILTIN_VPCOMEQW,
26685 IX86_BUILTIN_VPCOMNEW,
26686 IX86_BUILTIN_VPCOMLTW,
26687 IX86_BUILTIN_VPCOMLEW,
26688 IX86_BUILTIN_VPCOMGTW,
26689 IX86_BUILTIN_VPCOMGEW,
26690 IX86_BUILTIN_VPCOMFALSEW,
26691 IX86_BUILTIN_VPCOMTRUEW,
26693 IX86_BUILTIN_VPCOMEQD,
26694 IX86_BUILTIN_VPCOMNED,
26695 IX86_BUILTIN_VPCOMLTD,
26696 IX86_BUILTIN_VPCOMLED,
26697 IX86_BUILTIN_VPCOMGTD,
26698 IX86_BUILTIN_VPCOMGED,
26699 IX86_BUILTIN_VPCOMFALSED,
26700 IX86_BUILTIN_VPCOMTRUED,
26702 IX86_BUILTIN_VPCOMEQQ,
26703 IX86_BUILTIN_VPCOMNEQ,
26704 IX86_BUILTIN_VPCOMLTQ,
26705 IX86_BUILTIN_VPCOMLEQ,
26706 IX86_BUILTIN_VPCOMGTQ,
26707 IX86_BUILTIN_VPCOMGEQ,
26708 IX86_BUILTIN_VPCOMFALSEQ,
26709 IX86_BUILTIN_VPCOMTRUEQ,
26711 /* LWP instructions. */
26712 IX86_BUILTIN_LLWPCB,
26713 IX86_BUILTIN_SLWPCB,
26714 IX86_BUILTIN_LWPVAL32,
26715 IX86_BUILTIN_LWPVAL64,
26716 IX86_BUILTIN_LWPINS32,
26717 IX86_BUILTIN_LWPINS64,
26719 IX86_BUILTIN_CLZS,
26721 /* RTM */
26722 IX86_BUILTIN_XBEGIN,
26723 IX86_BUILTIN_XEND,
26724 IX86_BUILTIN_XABORT,
26725 IX86_BUILTIN_XTEST,
26727 /* BMI instructions. */
26728 IX86_BUILTIN_BEXTR32,
26729 IX86_BUILTIN_BEXTR64,
26730 IX86_BUILTIN_CTZS,
26732 /* TBM instructions. */
26733 IX86_BUILTIN_BEXTRI32,
26734 IX86_BUILTIN_BEXTRI64,
26736 /* BMI2 instructions. */
26737 IX86_BUILTIN_BZHI32,
26738 IX86_BUILTIN_BZHI64,
26739 IX86_BUILTIN_PDEP32,
26740 IX86_BUILTIN_PDEP64,
26741 IX86_BUILTIN_PEXT32,
26742 IX86_BUILTIN_PEXT64,
26744 /* ADX instructions. */
26745 IX86_BUILTIN_ADDCARRYX32,
26746 IX86_BUILTIN_ADDCARRYX64,
26748 /* FSGSBASE instructions. */
26749 IX86_BUILTIN_RDFSBASE32,
26750 IX86_BUILTIN_RDFSBASE64,
26751 IX86_BUILTIN_RDGSBASE32,
26752 IX86_BUILTIN_RDGSBASE64,
26753 IX86_BUILTIN_WRFSBASE32,
26754 IX86_BUILTIN_WRFSBASE64,
26755 IX86_BUILTIN_WRGSBASE32,
26756 IX86_BUILTIN_WRGSBASE64,
26758 /* RDRND instructions. */
26759 IX86_BUILTIN_RDRAND16_STEP,
26760 IX86_BUILTIN_RDRAND32_STEP,
26761 IX86_BUILTIN_RDRAND64_STEP,
26763 /* RDSEED instructions. */
26764 IX86_BUILTIN_RDSEED16_STEP,
26765 IX86_BUILTIN_RDSEED32_STEP,
26766 IX86_BUILTIN_RDSEED64_STEP,
26768 /* F16C instructions. */
26769 IX86_BUILTIN_CVTPH2PS,
26770 IX86_BUILTIN_CVTPH2PS256,
26771 IX86_BUILTIN_CVTPS2PH,
26772 IX86_BUILTIN_CVTPS2PH256,
26774 /* CFString built-in for darwin */
26775 IX86_BUILTIN_CFSTRING,
26777 /* Builtins to get CPU type and supported features. */
26778 IX86_BUILTIN_CPU_INIT,
26779 IX86_BUILTIN_CPU_IS,
26780 IX86_BUILTIN_CPU_SUPPORTS,
26782 IX86_BUILTIN_MAX
26783 };
26785 /* Table for the ix86 builtin decls. */
26788 /* Table of all of the builtin functions that are possible with different ISA's
26789 but are waiting to be built until a function is declared to use that
26790 ISA. */
26797 };
26802 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
26803 of which isa_flags to use in the ix86_builtins_isa array. Stores the
26804 function decl in the ix86_builtins array. Returns the function decl or
26805 NULL_TREE, if the builtin was not added.
26807 If the front end has a special hook for builtin functions, delay adding
26808 builtin functions that aren't in the current ISA until the ISA is changed
26809 with function specific optimization. Doing so, can save about 300K for the
26810 default compiler. When the builtin is expanded, check at that time whether
26811 it is valid.
26813 If the front end doesn't have a special hook, record all builtins, even if
26814 it isn't an instruction set in the current ISA in case the user uses
26815 function specific options for a different ISA, so that we don't get scope
26816 errors if a builtin is added in the middle of a function scope. */
26822 {
26826 {
26835 {
26841 }
26842 else
26843 {
26849 }
26850 }
26853 }
26855 /* Like def_builtin, but also marks the function decl "const". */
26860 {
26864 else
26868 }
26870 /* Add any new builtin functions for a given ISA that may not have been
26871 declared. This saves a bit of space compared to adding all of the
26872 declarations to the tree, even if we didn't use them. */
26874 static void
26876 {
26880 {
26883 {
26886 /* Don't define the builtin again. */
26892 NULL_TREE);
26897 }
26898 }
26899 }
26901 /* Bits for builtin_description.flag. */
26903 /* Set when we don't support the comparison natively, and should
26904 swap_comparison in order to support it. */
26905 #define BUILTIN_DESC_SWAP_OPERANDS 1
26907 struct builtin_description
26908 {
26915 };
26918 {
26919 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
26920 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
26921 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
26922 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
26923 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
26924 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
26925 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
26926 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
26927 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
26928 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
26929 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
26930 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
26931 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
26932 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
26933 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
26934 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
26935 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
26936 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
26937 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
26938 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
26939 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
26940 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
26941 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
26942 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
26943 };
26946 {
26947 /* SSE4.2 */
26948 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
26949 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
26950 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
26951 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
26952 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
26953 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
26954 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
26955 };
26958 {
26959 /* SSE4.2 */
26960 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
26961 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
26962 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
26963 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
26964 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
26965 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
26966 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
26967 };
26969 /* Special builtins with variable number of arguments. */
26971 {
26972 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
26973 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
26974 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
26976 /* MMX */
26977 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
26979 /* 3DNow! */
26980 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
26982 /* FXSR, XSAVE and XSAVEOPT */
26983 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
26984 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
26985 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26986 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26987 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26989 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
26990 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
26991 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26992 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26993 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
26995 /* SSE */
26996 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26997 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
26998 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
27000 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
27001 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
27002 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
27003 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
27005 /* SSE or 3DNow!A */
27006 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
27007 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
27009 /* SSE2 */
27010 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
27011 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
27012 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
27013 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedqu, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
27014 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
27015 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
27016 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
27017 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
27018 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
27019 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddqu, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
27021 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
27022 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
27024 /* SSE3 */
27025 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
27027 /* SSE4.1 */
27028 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
27030 /* SSE4A */
27031 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
27032 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
27034 /* AVX */
27035 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
27036 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
27038 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
27039 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
27040 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
27041 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
27042 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
27044 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
27045 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
27046 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
27047 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
27048 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddqu256, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
27049 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedqu256, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
27050 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
27052 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
27053 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
27054 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
27056 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
27057 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
27058 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
27059 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
27060 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
27061 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
27062 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
27063 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
27065 /* AVX2 */
27066 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
27067 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
27068 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
27069 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
27070 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
27071 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
27072 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
27073 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
27074 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
27076 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
27077 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
27078 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
27079 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
27080 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
27081 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
27083 /* FSGSBASE */
27084 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
27085 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
27086 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
27087 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
27088 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
27089 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
27090 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
27091 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
27093 /* RTM */
27094 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
27095 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
27096 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
27097 };
27099 /* Builtins with variable number of arguments. */
27101 {
27102 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
27103 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
27104 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
27105 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
27106 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
27107 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
27108 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
27110 /* MMX */
27111 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27112 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27113 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27114 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27115 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27116 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27118 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27119 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27120 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27121 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27122 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27123 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27124 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27125 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27127 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27128 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27130 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27131 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27132 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27133 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27135 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27136 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27137 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27138 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27139 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27140 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27142 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27143 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27144 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27145 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27146 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
27147 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
27149 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
27150 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
27151 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
27153 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
27155 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27156 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27157 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
27158 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27159 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27160 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
27162 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27163 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27164 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
27165 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27166 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27167 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
27169 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
27170 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
27171 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
27172 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
27174 /* 3DNow! */
27175 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
27176 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
27177 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27178 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27180 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27181 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27182 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27183 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27184 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27185 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
27186 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27187 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27188 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27189 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27190 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27191 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27192 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27193 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27194 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27196 /* 3DNow!A */
27197 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
27198 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
27199 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
27200 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
27201 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27202 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
27204 /* SSE */
27205 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
27206 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27207 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27208 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27209 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27210 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27211 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
27212 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
27213 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
27214 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
27215 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
27216 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
27218 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27220 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27221 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27222 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27223 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27224 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27225 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27226 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27227 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27229 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
27230 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
27231 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
27232 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27233 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27234 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27235 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
27236 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
27237 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
27238 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27239 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
27240 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27241 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
27242 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
27243 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
27244 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27245 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
27246 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
27247 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
27248 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27249 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
27250 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
27252 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27253 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27254 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27255 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27257 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27258 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27259 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27260 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27262 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27264 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27265 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27266 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27267 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27268 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27270 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
27271 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
27272 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
27274 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
27276 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27277 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27278 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
27280 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
27281 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
27283 /* SSE MMX or 3Dnow!A */
27284 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27285 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27286 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27288 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27289 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27290 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27291 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27293 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
27294 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
27296 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
27298 /* SSE2 */
27299 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27301 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
27302 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
27303 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
27304 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
27305 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
27307 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
27308 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
27309 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
27310 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
27311 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
27313 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
27315 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
27316 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
27317 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
27318 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
27320 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2dq, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27321 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
27322 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27324 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27325 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27326 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27327 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27328 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27329 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27330 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27331 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27333 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
27334 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
27335 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
27336 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27337 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
27338 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27339 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
27340 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
27341 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
27342 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27343 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
27344 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27345 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
27346 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
27347 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
27348 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27349 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
27350 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
27351 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
27352 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
27354 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27355 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27356 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27357 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27359 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27360 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27361 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27362 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27364 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27366 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27367 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27368 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27370 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
27372 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27373 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27374 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27375 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27376 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27377 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27378 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27379 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27381 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27382 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27383 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27384 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27385 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27386 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27387 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27388 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27390 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27391 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
27393 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27394 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27395 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27396 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27398 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27399 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27401 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27402 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27403 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27404 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27405 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27406 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27408 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27409 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27410 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27411 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27413 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27414 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27415 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27416 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27417 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27418 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27419 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27420 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27422 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
27423 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
27424 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
27426 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27427 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
27429 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
27430 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
27432 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
27434 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
27435 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
27436 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
27437 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
27439 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
27440 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27441 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27442 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
27443 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27444 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27445 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
27447 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
27448 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27449 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27450 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
27451 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27452 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27453 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
27455 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
27456 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
27457 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
27458 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
27460 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
27461 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
27462 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
27464 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
27466 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27468 /* SSE2 MMX */
27469 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
27470 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
27472 /* SSE3 */
27473 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
27474 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27476 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27477 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27478 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27479 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27480 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
27481 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
27483 /* SSSE3 */
27484 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
27485 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
27486 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27487 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
27488 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
27489 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
27491 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27492 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27493 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27494 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27495 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27496 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27497 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27498 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27499 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27500 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27501 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27502 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27503 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
27504 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
27505 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27506 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27507 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27508 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27509 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27510 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
27511 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27512 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
27513 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27514 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
27516 /* SSSE3. */
27517 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
27518 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
27520 /* SSE4.1 */
27521 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27522 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27523 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
27524 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
27525 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27526 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27527 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27528 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
27529 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
27530 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
27532 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
27533 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
27534 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
27535 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
27536 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
27537 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
27538 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
27539 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
27540 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
27541 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
27542 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
27543 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
27544 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27546 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
27547 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27548 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27549 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27550 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27551 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27552 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
27553 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27554 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27555 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
27556 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
27557 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27559 /* SSE4.1 */
27560 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
27561 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
27562 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27563 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27565 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
27566 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
27567 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
27568 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
27570 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
27571 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
27573 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
27574 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
27576 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
27577 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
27578 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
27579 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
27581 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
27582 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
27584 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27585 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
27587 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27588 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27589 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
27591 /* SSE4.2 */
27592 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27593 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
27594 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
27595 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27596 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27598 /* SSE4A */
27599 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
27600 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
27601 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
27602 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27604 /* AES */
27605 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
27606 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27608 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27609 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27610 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27611 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27613 /* PCLMUL */
27614 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
27616 /* AVX */
27617 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27618 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27619 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27620 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27621 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27622 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27623 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27624 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27625 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27626 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27627 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27628 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27629 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27630 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27631 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27632 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27633 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27634 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27635 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27636 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27637 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27638 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27639 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27640 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27641 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27642 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27644 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
27645 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
27646 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
27647 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
27649 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27650 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27651 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
27652 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
27653 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27654 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27655 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27656 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27657 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27658 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
27659 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
27660 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27661 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27662 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
27663 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
27664 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
27665 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
27666 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
27667 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
27668 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2dq256, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27669 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
27670 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
27671 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
27672 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27673 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
27674 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
27675 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
27676 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
27677 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
27678 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27679 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
27680 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
27681 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
27682 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
27684 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27685 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27686 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27688 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27689 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27690 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27691 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27692 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27694 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27696 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27697 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
27699 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
27700 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
27701 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
27702 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
27704 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
27705 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
27707 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
27708 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
27710 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
27711 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
27712 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
27713 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
27715 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
27716 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
27718 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
27719 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
27721 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27722 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27723 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27724 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27726 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
27727 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
27728 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
27729 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
27730 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
27731 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
27733 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27734 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27735 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
27736 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27737 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27738 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
27739 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27740 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27741 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
27742 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27743 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27744 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
27745 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27746 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27747 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
27749 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
27750 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
27752 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
27753 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
27755 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
27757 /* AVX2 */
27758 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
27759 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
27760 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
27761 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
27762 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
27763 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
27764 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
27765 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
27766 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27767 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27768 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27769 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27770 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27771 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27772 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27773 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27774 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
27775 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27776 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27777 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27778 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27779 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
27780 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
27781 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27782 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27783 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27784 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27785 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27786 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27787 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27788 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27789 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27790 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27791 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27792 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27793 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27794 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27795 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
27796 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
27797 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27798 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27799 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27800 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27801 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27802 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27803 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27804 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27805 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27806 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27807 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27808 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27809 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
27810 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
27811 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
27812 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
27813 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
27814 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
27815 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
27816 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
27817 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
27818 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
27819 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
27820 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
27821 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
27822 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
27823 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27824 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27825 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27826 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27827 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27828 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
27829 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27830 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
27831 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27832 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
27833 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
27834 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
27835 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27836 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27837 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27838 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
27839 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27840 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27841 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27842 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27843 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
27844 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
27845 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27846 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27847 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27848 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27849 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
27850 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
27851 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
27852 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
27853 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
27854 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
27855 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
27856 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27857 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27858 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27859 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27860 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27861 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27862 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27863 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27864 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27865 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27866 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27867 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27868 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
27869 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
27870 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27871 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27872 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27873 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
27874 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
27875 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
27876 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
27877 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
27878 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
27879 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
27880 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
27881 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
27882 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
27883 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
27884 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
27885 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
27886 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
27887 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27888 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
27889 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
27890 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
27891 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
27892 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_extracti128, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
27893 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_inserti128, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
27894 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27895 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27896 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27897 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27898 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27899 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27900 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
27901 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
27902 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
27903 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
27905 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
27907 /* BMI */
27908 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27909 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27910 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
27912 /* TBM */
27913 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27914 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27916 /* F16C */
27917 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
27918 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
27919 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
27920 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
27922 /* BMI2 */
27923 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27924 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27925 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27926 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27927 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
27928 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
27929 };
27931 /* FMA4 and XOP. */
27932 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
27933 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
27934 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
27935 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
27936 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
27937 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
27938 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
27939 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
27940 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
27941 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
27942 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
27943 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
27944 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
27945 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
27946 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
27947 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
27948 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
27949 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
27950 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
27951 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
27952 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
27953 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
27954 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
27955 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
27956 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
27957 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
27958 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
27959 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
27960 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
27961 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
27962 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
27963 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
27964 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
27965 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
27966 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
27967 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
27968 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
27969 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
27970 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
27971 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
27972 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
27973 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
27974 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
27975 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
27976 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
27977 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
27978 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
27979 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
27980 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
27981 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
27982 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
27983 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
27986 {
28027 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
28028 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
28029 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
28030 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
28031 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
28032 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
28033 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
28035 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
28036 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
28037 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
28038 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
28039 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
28040 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
28041 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
28043 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
28045 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
28046 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
28047 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
28048 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
28049 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
28050 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
28051 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
28052 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
28053 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
28054 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
28055 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
28056 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
28058 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
28059 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
28060 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
28061 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
28062 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
28063 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
28064 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
28065 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
28066 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
28067 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
28068 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
28069 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
28070 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
28071 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
28072 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
28073 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
28075 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
28076 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
28077 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
28078 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
28079 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
28080 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
28082 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
28083 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
28084 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
28085 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
28086 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
28087 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
28088 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
28089 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
28090 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
28091 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
28092 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
28093 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
28094 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
28095 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
28096 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
28098 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
28099 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
28100 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
28101 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
28102 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
28103 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
28104 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
28106 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
28107 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
28108 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
28109 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
28110 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
28111 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
28112 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
28114 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
28115 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
28116 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
28117 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
28118 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
28119 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
28120 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
28122 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
28123 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
28124 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
28125 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
28126 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
28127 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
28128 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
28130 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
28131 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
28132 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
28133 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
28134 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
28135 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
28136 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
28138 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
28139 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
28140 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
28141 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
28142 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
28143 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
28144 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
28146 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
28147 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
28148 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
28149 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
28150 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
28151 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
28152 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
28154 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
28155 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
28156 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
28157 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
28158 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
28159 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
28160 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
28162 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
28163 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
28164 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
28165 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
28166 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
28167 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
28168 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
28169 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
28171 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
28172 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
28173 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
28174 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
28175 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
28176 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
28177 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
28178 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
28180 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
28181 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
28182 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
28183 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
28185 };
28186 \f
28187 /* TM vector builtins. */
28189 /* Reuse the existing x86-specific `struct builtin_description' cause
28190 we're lazy. Add casts to make them fit. */
28192 {
28193 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28194 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28195 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
28196 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28197 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28198 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28199 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
28201 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28202 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28203 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
28204 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28205 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28206 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28207 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
28209 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28210 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28211 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
28212 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28213 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28214 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28215 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
28217 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
28218 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
28219 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
28220 };
28222 /* TM callbacks. */
28224 /* Return the builtin decl needed to load a vector of TYPE. */
28226 static tree
28228 {
28230 {
28232 {
28239 }
28240 }
28242 }
28244 /* Return the builtin decl needed to store a vector of TYPE. */
28246 static tree
28248 {
28250 {
28252 {
28259 }
28260 }
28262 }
28263 \f
28264 /* Initialize the transactional memory vector load/store builtins. */
28266 static void
28268 {
28272 tree decl;
28279 /* If there are no builtins defined, we must be compiling in a
28280 language without trans-mem support. */
28284 /* Use whatever attributes a normal TM load has. */
28288 /* Use whatever attributes a normal TM store has. */
28292 /* Use whatever attributes a normal TM log has. */
28300 {
28304 {
28312 {
28315 }
28317 {
28320 }
28321 else
28322 {
28325 }
28327 /* The builtin without the prefix for
28328 calling it directly. */
28330 attrs);
28331 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
28332 set the TYPE_ATTRIBUTES. */
28336 }
28337 }
28338 }
28340 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
28341 in the current target ISA to allow the user to compile particular modules
28342 with different target specific options that differ from the command line
28343 options. */
28344 static void
28346 {
28351 /* Add all special builtins with variable number of operands. */
28355 {
28361 }
28363 /* Add all builtins with variable number of operands. */
28367 {
28373 }
28375 /* pcmpestr[im] insns. */
28379 {
28382 else
28385 }
28387 /* pcmpistr[im] insns. */
28391 {
28394 else
28397 }
28399 /* comi/ucomi insns. */
28401 {
28404 else
28407 }
28409 /* SSE */
28415 /* SSE or 3DNow!A */
28418 IX86_BUILTIN_MASKMOVQ);
28420 /* SSE2 */
28429 /* SSE3. */
28435 /* AES */
28449 /* PCLMUL */
28453 /* RDRND */
28460 IX86_BUILTIN_RDRAND64_STEP);
28462 /* AVX2 */
28464 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
28465 IX86_BUILTIN_GATHERSIV2DF);
28468 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
28469 IX86_BUILTIN_GATHERSIV4DF);
28472 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
28473 IX86_BUILTIN_GATHERDIV2DF);
28476 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
28477 IX86_BUILTIN_GATHERDIV4DF);
28480 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
28481 IX86_BUILTIN_GATHERSIV4SF);
28484 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
28485 IX86_BUILTIN_GATHERSIV8SF);
28488 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
28489 IX86_BUILTIN_GATHERDIV4SF);
28492 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
28493 IX86_BUILTIN_GATHERDIV8SF);
28496 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
28497 IX86_BUILTIN_GATHERSIV2DI);
28500 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
28501 IX86_BUILTIN_GATHERSIV4DI);
28504 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
28505 IX86_BUILTIN_GATHERDIV2DI);
28508 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
28509 IX86_BUILTIN_GATHERDIV4DI);
28512 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
28513 IX86_BUILTIN_GATHERSIV4SI);
28516 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
28517 IX86_BUILTIN_GATHERSIV8SI);
28520 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
28521 IX86_BUILTIN_GATHERDIV4SI);
28524 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
28525 IX86_BUILTIN_GATHERDIV8SI);
28528 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
28529 IX86_BUILTIN_GATHERALTSIV4DF);
28532 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
28533 IX86_BUILTIN_GATHERALTDIV8SF);
28536 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
28537 IX86_BUILTIN_GATHERALTSIV4DI);
28540 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
28541 IX86_BUILTIN_GATHERALTDIV8SI);
28543 /* RTM. */
28547 /* MMX access to the vec_init patterns. */
28552 V4HI_FTYPE_HI_HI_HI_HI,
28553 IX86_BUILTIN_VEC_INIT_V4HI);
28556 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
28557 IX86_BUILTIN_VEC_INIT_V8QI);
28559 /* Access to the vec_extract patterns. */
28581 /* Access to the vec_set patterns. */
28602 /* RDSEED */
28611 /* ADCX */
28616 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
28617 IX86_BUILTIN_ADDCARRYX64);
28619 /* Add FMA4 multi-arg argument instructions */
28621 {
28627 }
28628 }
28630 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
28631 to return a pointer to VERSION_DECL if the outcome of the expression
28632 formed by PREDICATE_CHAIN is true. This function will be called during
28633 version dispatch to decide which function version to execute. It returns
28634 the basic block at the end, to which more conditions can be added. */
28636 static basic_block
28639 {
28640 gimple return_stmt;
28642 gimple convert_stmt;
28643 gimple call_cond_stmt;
28644 gimple if_else_stmt;
28650 gimple_seq gseq;
28667 {
28675 }
28678 {
28693 else
28694 {
28695 gimple assign_stmt;
28696 /* Use MIN_EXPR to check if any integer is zero?.
28697 and_expr_var = min_expr <cond_var, and_expr_var> */
28705 }
28706 }
28709 integer_zero_node,
28739 }
28741 /* This parses the attribute arguments to target in DECL and determines
28742 the right builtin to use to match the platform specification.
28743 It returns the priority value for this version decl. If PREDICATE_LIST
28744 is not NULL, it stores the list of cpu features that need to be checked
28745 before dispatching this function. */
28747 static unsigned int
28749 {
28750 tree attrs;
28752 tree target_node;
28759 /* Priority of i386 features, greater value is higher priority. This is
28760 used to decide the order in which function dispatch must happen. For
28761 instance, a version specialized for SSE4.2 should be checked for dispatch
28762 before a version for SSE3, as SSE4.2 implies SSE3. */
28763 enum feature_priority
28764 {
28766 P_MMX,
28767 P_SSE,
28768 P_SSE2,
28769 P_SSE3,
28770 P_SSSE3,
28771 P_PROC_SSSE3,
28772 P_SSE4_a,
28773 P_PROC_SSE4_a,
28774 P_SSE4_1,
28775 P_SSE4_2,
28776 P_PROC_SSE4_2,
28777 P_POPCNT,
28778 P_AVX,
28779 P_AVX2,
28780 P_FMA,
28781 P_PROC_FMA
28782 };
28786 /* These are the target attribute strings for which a dispatcher is
28787 available, from fold_builtin_cpu. */
28789 static struct _feature_list
28790 {
28793 }
28795 {
28806 };
28809 static unsigned int NUM_FEATURES
28825 /* Return priority zero for default function. */
28829 /* Handle arch= if specified. For priority, set it to be 1 more than
28830 the best instruction set the processor can handle. For instance, if
28831 there is a version for atom and a version for ssse3 (the highest ISA
28832 priority for atom), the atom version must be checked for dispatch
28833 before the ssse3 version. */
28835 {
28844 {
28846 {
28871 }
28872 }
28877 {
28881 }
28884 {
28886 /* For a C string literal the length includes the trailing NULL. */
28889 predicate_chain);
28890 }
28891 }
28893 /* Process feature name. */
28900 {
28901 /* Do not process "arch=" */
28903 {
28906 }
28908 {
28910 {
28912 {
28917 predicate_chain);
28918 }
28919 /* Find the maximum priority feature. */
28924 }
28925 }
28927 {
28931 }
28933 }
28937 {
28940 attrs_str);
28942 }
28944 {
28947 }
28950 }
28952 /* This compares the priority of target features in function DECL1
28953 and DECL2. It returns positive value if DECL1 is higher priority,
28954 negative value if DECL2 is higher priority and 0 if they are the
28955 same. */
28957 static int
28959 {
28964 }
28966 /* V1 and V2 point to function versions with different priorities
28967 based on the target ISA. This function compares their priorities. */
28969 static int
28971 {
28973 {
28974 tree version_decl;
28975 tree predicate_chain;
28982 }
28984 /* This function generates the dispatch function for
28985 multi-versioned functions. DISPATCH_DECL is the function which will
28986 contain the dispatch logic. FNDECLS are the function choices for
28987 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
28988 in DISPATCH_DECL in which the dispatch code is generated. */
28990 static int
28994 {
28995 tree default_decl;
28996 gimple ifunc_cpu_init_stmt;
28997 gimple_seq gseq;
28999 tree ele;
29005 struct _function_version_info
29006 {
29007 tree version_decl;
29008 tree predicate_chain;
29016 /*fndecls_p is actually a vector. */
29019 /* At least one more version other than the default. */
29026 /* The first version in the vector is the default decl. */
29032 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
29033 constructors, so explicity call __builtin_cpu_init here. */
29044 {
29048 /* Get attribute string, parse it and find the right predicate decl.
29049 The predicate function could be a lengthy combination of many
29050 features, like arch-type and various isa-variants. */
29057 actual_versions++;
29061 }
29063 /* Sort the versions according to descending order of dispatch priority. The
29064 priority is based on the ISA. This is not a perfect solution. There
29065 could still be ambiguity. If more than one function version is suitable
29066 to execute, which one should be dispatched? In future, allow the user
29067 to specify a dispatch priority next to the version. */
29077 /* dispatch default version at the end. */
29083 }
29085 /* Comparator function to be used in qsort routine to sort attribute
29086 specification strings to "target". */
29088 static int
29090 {
29094 }
29096 /* ARGLIST is the argument to target attribute. This function tokenizes
29097 the comma separated arguments, sorts them and returns a string which
29098 is a unique identifier for the comma separated arguments. It also
29099 replaces non-identifier characters "=,-" with "_". */
29103 {
29104 tree arg;
29113 {
29118 argnum++;
29121 argnum++;
29122 }
29127 {
29133 }
29135 /* Replace "=,-" with "_". */
29148 {
29150 i++;
29152 }
29159 {
29164 }
29169 }
29171 /* This function changes the assembler name for functions that are
29172 versions. If DECL is a function version and has a "target"
29173 attribute, it appends the attribute string to its assembler name. */
29175 static tree
29177 {
29178 tree version_attr;
29186 "Function versions cannot be marked as gnu_inline,"
29195 /* target attribute string cannot be NULL. */
29199 version_string
29210 /* Allow assembler name to be modified if already set. */
29218 }
29220 /* This function returns true if FN1 and FN2 are versions of the same function,
29221 that is, the target strings of the function decls are different. This assumes
29222 that FN1 and FN2 have the same signature. */
29224 static bool
29226 {
29238 /* At least one function decl should have the target attribute specified. */
29242 /* Diagnose missing target attribute if one of the decls is already
29243 multi-versioned. */
29245 {
29247 {
29249 {
29254 }
29257 fn2);
29260 /* Prevent diagnosing of the same error multiple times. */
29265 }
29267 }
29272 /* The sorted target strings must be different for fn1 and fn2
29273 to be versions. */
29276 else
29283 }
29285 static tree
29287 {
29288 /* For function version, add the target suffix to the assembler name. */
29292 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
29294 #endif
29297 }
29299 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
29300 is true, append the full path name of the source file. */
29304 {
29312 /* Get a unique name that can be used globally without any chances
29313 of collision at link time. */
29323 /* Use '.' to concatenate names as it is demangler friendly. */
29326 suffix);
29327 else
29331 }
29333 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
29335 /* Make a dispatcher declaration for the multi-versioned function DECL.
29336 Calls to DECL function will be replaced with calls to the dispatcher
29337 by the front-end. Return the decl created. */
29339 static tree
29341 {
29342 tree func_decl;
29362 /* Mark this func as external, the resolver will flip it again if
29363 it gets generated. */
29365 /* This will be of type IFUNCs have to be externally visible. */
29369 }
29371 #endif
29373 /* Returns true if decl is multi-versioned and DECL is the default function,
29374 that is it is not tagged with target specific optimization. */
29376 static bool
29378 {
29387 }
29389 /* Make a dispatcher declaration for the multi-versioned function DECL.
29390 Calls to DECL function will be replaced with calls to the dispatcher
29391 by the front-end. Returns the decl of the dispatcher function. */
29393 static tree
29395 {
29417 /* Find the default version and make it the first node. */
29419 /* Go to the beginnig of the chain. */
29424 {
29429 }
29431 /* If there is no default node, just return NULL. */
29435 /* Make default info the first node. */
29437 {
29444 }
29448 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
29450 {
29455 /* Right now, the dispatching is done via ifunc. */
29461 dispatcher_version_info
29466 /* Set the dispatcher for all the versions. */
29469 {
29472 }
29473 }
29474 else
29475 #endif
29476 {
29478 "multiversioning needs ifunc which is not supported "
29480 }
29483 }
29485 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
29486 it to CHAIN. */
29488 static tree
29490 {
29491 tree attr_name;
29492 tree attr_arg_name;
29493 tree attr_args;
29494 tree attr;
29501 }
29503 /* Make the resolver function decl to dispatch the versions of
29504 a multi-versioned function, DEFAULT_DECL. Create an
29505 empty basic block in the resolver and store the pointer in
29506 EMPTY_BB. Return the decl of the resolver function. */
29508 static tree
29512 {
29517 /* IFUNC's have to be globally visible. So, if the default_decl is
29518 not, then the name of the IFUNC should be made unique. */
29522 /* Append the filename to the resolver function if the versions are
29523 not externally visible. This is because the resolver function has
29524 to be externally visible for the loader to find it. So, appending
29525 the filename will prevent conflicts with a resolver function from
29526 another module which is based on the same version name. */
29529 /* The resolver function should return a (void *). */
29540 /* IFUNC resolvers have to be externally visible. */
29544 /* Resolver is not external, body is generated. */
29554 {
29555 /* In this case, each translation unit with a call to this
29556 versioned function will put out a resolver. Ensure it
29557 is comdat to keep just one copy. */
29560 }
29561 /* Build result decl and add to function_decl. */
29577 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
29581 /* Create the alias for dispatch to resolver here. */
29582 /*cgraph_create_function_alias (dispatch_decl, decl);*/
29586 }
29588 /* Generate the dispatching code body to dispatch multi-versioned function
29589 DECL. The target hook is called to process the "target" attributes and
29590 provide the code to dispatch the right function at run-time. NODE points
29591 to the dispatcher decl whose body will be created. */
29593 static tree
29595 {
29596 tree resolver_decl;
29597 basic_block empty_bb;
29599 tree default_ver_decl;
29615 /* The first version in the chain corresponds to the default version. */
29618 /* node is going to be an alias, so remove the finalized bit. */
29632 {
29634 /* Check for virtual functions here again, as by this time it should
29635 have been determined if this function needs a vtable index or
29636 not. This happens for methods in derived classes that override
29637 virtual methods in base classes but are not explicitly marked as
29638 virtual. */
29643 }
29650 }
29651 /* This builds the processor_model struct type defined in
29652 libgcc/config/i386/cpuinfo.c */
29654 static tree
29656 {
29663 /* The first 3 fields are unsigned int. */
29665 {
29671 }
29673 /* The last field is an array of unsigned integers of size one. */
29684 }
29686 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
29688 static tree
29690 {
29691 tree new_decl;
29694 VAR_DECL,
29696 type);
29709 }
29711 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
29712 into an integer defined in libgcc/config/i386/cpuinfo.c */
29714 static tree
29716 {
29722 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
29723 enum processor_features
29724 {
29726 F_MMX,
29727 F_POPCNT,
29728 F_SSE,
29729 F_SSE2,
29730 F_SSE3,
29731 F_SSSE3,
29732 F_SSE4_1,
29733 F_SSE4_2,
29734 F_AVX,
29735 F_AVX2,
29736 F_MAX
29737 };
29739 /* These are the values for vendor types and cpu types and subtypes
29740 in cpuinfo.c. Cpu types and subtypes should be subtracted by
29741 the corresponding start value. */
29742 enum processor_model
29743 {
29745 M_AMD,
29746 M_CPU_TYPE_START,
29747 M_INTEL_ATOM,
29748 M_INTEL_CORE2,
29749 M_INTEL_COREI7,
29750 M_AMDFAM10H,
29751 M_AMDFAM15H,
29752 M_CPU_SUBTYPE_START,
29753 M_INTEL_COREI7_NEHALEM,
29754 M_INTEL_COREI7_WESTMERE,
29755 M_INTEL_COREI7_SANDYBRIDGE,
29756 M_AMDFAM10H_BARCELONA,
29757 M_AMDFAM10H_SHANGHAI,
29758 M_AMDFAM10H_ISTANBUL,
29759 M_AMDFAM15H_BDVER1,
29760 M_AMDFAM15H_BDVER2,
29761 M_AMDFAM15H_BDVER3
29762 };
29764 static struct _arch_names_table
29765 {
29768 }
29770 {
29787 };
29789 static struct _isa_names_table
29790 {
29793 }
29795 {
29807 };
29818 {
29819 /* *args must be a expr that can contain other EXPRS leading to a
29820 STRING_CST. */
29822 {
29825 }
29827 }
29832 {
29833 tree ref;
29834 tree field;
29835 tree final;
29838 unsigned int NUM_ARCH_NAMES
29847 {
29851 }
29856 /* CPU types are stored in the next field. */
29859 {
29862 }
29864 /* CPU subtypes are stored in the next field. */
29866 {
29869 }
29871 /* Get the appropriate field in __cpu_model. */
29875 /* Check the value. */
29879 }
29881 {
29882 tree ref;
29883 tree array_elt;
29884 tree field;
29885 tree final;
29888 unsigned int NUM_ISA_NAMES
29897 {
29901 }
29904 /* Get the last field, which is __cpu_features. */
29908 /* Get the appropriate field: __cpu_model.__cpu_features */
29912 /* Access the 0th element of __cpu_features array. */
29917 /* Return __cpu_model.__cpu_features[0] & field_val */
29921 }
29923 }
29925 static tree
29928 {
29930 {
29935 {
29938 }
29939 }
29941 #ifdef SUBTARGET_FOLD_BUILTIN
29943 #endif
29946 }
29948 /* Make builtins to detect cpu type and features supported. NAME is
29949 the builtin name, CODE is the builtin code, and FTYPE is the function
29950 type of the builtin. */
29952 static void
29955 {
29956 tree decl;
29957 tree type;
29965 }
29967 /* Make builtins to get CPU type and features supported. The created
29968 builtins are :
29970 __builtin_cpu_init (), to detect cpu type and features,
29971 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
29972 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
29973 */
29975 static void
29977 {
29984 }
29986 /* Internal method for ix86_init_builtins. */
29988 static void
29990 {
30002 sysv_va_ref =
30005 fnvoid_va_end_ms =
30007 fnvoid_va_start_ms =
30009 fnvoid_va_end_sysv =
30011 fnvoid_va_start_sysv =
30013 NULL_TREE);
30014 fnvoid_va_copy_ms =
30016 NULL_TREE);
30017 fnvoid_va_copy_sysv =
30033 }
30035 static void
30037 {
30040 /* The __float80 type. */
30043 {
30044 /* The __float80 type. */
30049 }
30052 /* The __float128 type. */
30058 /* This macro is built by i386-builtin-types.awk. */
30059 DEFINE_BUILTIN_PRIMITIVE_TYPES;
30060 }
30062 static void
30064 {
30065 tree t;
30069 /* Builtins to get CPU type and features. */
30072 /* TFmode support builtins. */
30078 /* We will expand them to normal call if SSE isn't available since
30079 they are used by libgcc. */
30098 #ifdef SUBTARGET_INIT_BUILTINS
30099 SUBTARGET_INIT_BUILTINS;
30100 #endif
30101 }
30103 /* Return the ix86 builtin for CODE. */
30105 static tree
30107 {
30112 }
30114 /* Errors in the source file can cause expand_expr to return const0_rtx
30115 where we expect a vector. To avoid crashing, use one of the vector
30116 clear instructions. */
30117 static rtx
30119 {
30123 }
30125 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
30127 static rtx
30129 {
30130 rtx pat;
30150 {
30154 }
30168 }
30170 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
30172 static rtx
30176 {
30177 rtx pat;
30185 rtx op;
30192 {
30272 }
30282 {
30289 {
30291 {
30294 {
30312 xop_rotl:
30314 {
30317 gcc_checking_assert
30319 }
30320 else
30321 {
30322 gcc_checking_assert
30333 }
30337 }
30338 }
30339 }
30340 else
30341 {
30342 non_constant:
30346 /* If we aren't optimizing, only allow one memory operand to be
30347 generated. */
30349 num_memory++;
30357 }
30361 }
30364 {
30375 else
30376 {
30382 }
30395 }
30402 }
30404 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
30405 insns with vec_merge. */
30407 static rtx
30409 rtx target)
30410 {
30411 rtx pat;
30438 }
30440 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
30442 static rtx
30445 {
30446 rtx pat;
30451 rtx op2;
30462 /* Swap operands if we have a comparison that isn't available in
30463 hardware. */
30465 {
30470 }
30490 }
30492 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
30494 static rtx
30496 rtx target)
30497 {
30498 rtx pat;
30512 /* Swap operands if we have a comparison that isn't available in
30513 hardware. */
30515 {
30519 }
30540 const0_rtx)));
30543 }
30545 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
30547 static rtx
30549 rtx target)
30550 {
30551 rtx pat;
30576 }
30578 static rtx
30581 {
30582 rtx pat;
30587 rtx op2;
30614 }
30616 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
30618 static rtx
30620 rtx target)
30621 {
30622 rtx pat;
30655 const0_rtx)));
30658 }
30660 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
30662 static rtx
30665 {
30666 rtx pat;
30704 {
30707 }
30710 {
30719 }
30721 {
30730 }
30731 else
30732 {
30739 }
30747 {
30752 emit_insn
30756 FLAGS_REG),
30757 const0_rtx)));
30759 }
30760 else
30762 }
30765 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
30767 static rtx
30770 {
30771 rtx pat;
30799 {
30802 }
30805 {
30814 }
30816 {
30825 }
30826 else
30827 {
30834 }
30842 {
30847 emit_insn
30851 FLAGS_REG),
30852 const0_rtx)));
30854 }
30855 else
30857 }
30859 /* Subroutine of ix86_expand_builtin to take care of insns with
30860 variable number of operands. */
30862 static rtx
30865 {
30870 struct
30871 {
30872 rtx op;
30884 {
31163 }
31168 {
31171 }
31174 {
31181 }
31182 else
31183 {
31186 }
31189 {
31196 {
31197 /* SIMD shift insns take either an 8-bit immediate or
31198 register as count. But builtin functions take int as
31199 count. If count doesn't match, we put it in register. */
31201 {
31205 }
31206 }
31208 {
31211 {
31265 {
31268 {
31271 }
31277 }
31279 }
31280 }
31281 else
31282 {
31286 /* If we aren't optimizing, only allow one memory operand to
31287 be generated. */
31289 num_memory++;
31292 {
31295 }
31296 else
31297 {
31300 }
31301 }
31305 }
31308 {
31325 }
31332 }
31334 /* Subroutine of ix86_expand_builtin to take care of special insns
31335 with variable number of operands. */
31337 static rtx
31340 {
31341 tree arg;
31344 struct
31345 {
31346 rtx op;
31356 {
31404 /* Reserve memory operand for target. */
31435 /* Reserve memory operand for target. */
31449 }
31454 {
31459 {
31462 }
31463 else
31466 }
31467 else
31468 {
31475 }
31478 {
31487 {
31489 {
31495 else
31498 }
31499 }
31500 else
31501 {
31503 {
31504 /* This must be the memory operand. */
31509 }
31510 else
31511 {
31512 /* This must be register. */
31519 }
31520 }
31524 }
31527 {
31542 }
31548 }
31550 /* Return the integer constant in ARG. Constrain it to be in the range
31551 of the subparts of VEC_TYPE; issue an error if not. */
31553 static int
31555 {
31560 {
31563 }
31566 }
31568 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31569 ix86_expand_vector_init. We DO have language-level syntax for this, in
31570 the form of (type){ init-list }. Except that since we can't place emms
31571 instructions from inside the compiler, we can't allow the use of MMX
31572 registers unless the user explicitly asks for it. So we do *not* define
31573 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
31574 we have builtins invoked by mmintrin.h that gives us license to emit
31575 these sorts of instructions. */
31577 static rtx
31579 {
31589 {
31592 }
31599 }
31601 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31602 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
31603 had a language-level syntax for referencing vector elements. */
31605 static rtx
31607 {
31611 rtx op0;
31631 }
31633 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
31634 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
31635 a language-level syntax for referencing vector elements. */
31637 static rtx
31639 {
31663 /* OP0 is the source of these builtin functions and shouldn't be
31664 modified. Create a copy, use it and return it as target. */
31670 }
31672 /* Expand an expression EXP that calls a built-in function,
31673 with result going to TARGET if that's convenient
31674 (and in mode MODE if that's convenient).
31675 SUBTARGET may be used as the target for computing one of EXP's operands.
31676 IGNORE is nonzero if the value is to be ignored. */
31678 static rtx
31682 {
31692 /* For CPU builtins that can be folded, fold first and expand the fold. */
31694 {
31696 {
31697 /* Make it call __cpu_indicator_init in libgcc. */
31703 }
31706 {
31711 }
31712 }
31714 /* Determine whether the builtin function is available under the current ISA.
31715 Originally the builtin was not created if it wasn't applicable to the
31716 current ISA based on the command line switches. With function specific
31717 options, we need to check in the context of the function making the call
31718 whether it is supported. */
31721 {
31727 else
31728 {
31732 }
31734 }
31737 {
31741 ? CODE_FOR_mmx_maskmovq
31743 /* Note the arg order is different from the operand order. */
31844 {
31845 REAL_VALUE_TYPE inf;
31846 rtx tmp;
31858 }
31868 {
31874 insn = (TARGET_64BIT
31878 }
31880 {
31881 insn = (TARGET_64BIT
31885 }
31886 else
31887 {
31890 insn = (TARGET_64BIT
31898 {
31901 }
31903 }
31909 {
31914 }
31924 {
31939 }
31945 {
31948 }
31968 {
31971 }
31977 {
31981 {
32002 }
32007 }
32008 else
32009 {
32011 {
32023 }
32025 }
32055 ? CODE_FOR_tbm_bextri_si
32058 {
32061 }
32062 else
32063 {
32072 }
32088 rdrand_step:
32095 {
32098 }
32104 /* Emit SImode conditional move. */
32106 {
32109 }
32112 else
32119 const0_rtx);
32138 rdseed_step:
32145 {
32148 }
32154 const0_rtx);
32172 addcarryx:
32180 /* Generate CF from input operand. */
32185 /* Gen ADCX instruction to compute X+Y+CF. */
32200 /* Store the result. */
32203 {
32206 }
32209 /* Return current CF value. */
32278 gather_gen:
32289 /* Note the arg order is different from the operand order. */
32298 else
32303 {
32309 }
32312 {
32317 else
32327 }
32329 /* Force memory operand only with base register here. But we
32330 don't want to do it on memory operand for other builtin
32331 functions. */
32343 {
32346 }
32348 /* Optimize. If mask is known to have all high bits set,
32349 replace op0 with pc_rtx to signal that the instruction
32350 overwrites the whole destination and doesn't use its
32351 previous contents. */
32353 {
32355 {
32358 {
32362 negative++;
32365 negative++;
32366 }
32369 }
32371 {
32372 /* Recognize also when mask is like:
32373 __v2df src = _mm_setzero_pd ();
32374 __v2df mask = _mm_cmpeq_pd (src, src);
32375 or
32376 __v8sf src = _mm256_setzero_ps ();
32377 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
32378 as that is a cheaper way to load all ones into
32379 a register than having to load a constant from
32380 memory. */
32383 {
32388 {
32395 /* FALLTHRU */
32405 }
32406 }
32407 }
32408 }
32417 {
32424 else
32426 }
32427 else
32438 {
32441 }
32447 }
32460 {
32464 /* Emit a normal call if SSE isn't available. */
32468 }
32493 }
32495 /* Returns a function decl for a vectorized version of the builtin function
32496 with builtin function code FN and the result vector type TYPE, or NULL_TREE
32497 if it is not available. */
32499 static tree
32501 tree type_in)
32502 {
32518 {
32521 {
32526 }
32531 {
32536 }
32542 /* The round insn does not trap on denormals. */
32547 {
32552 }
32558 /* The round insn does not trap on denormals. */
32563 {
32568 }
32574 /* The round insn does not trap on denormals. */
32579 {
32584 }
32590 /* The round insn does not trap on denormals. */
32595 {
32600 }
32607 {
32612 }
32619 {
32624 }
32630 /* The round insn does not trap on denormals. */
32635 {
32640 }
32646 /* The round insn does not trap on denormals. */
32651 {
32656 }
32661 {
32666 }
32671 {
32676 }
32680 /* The round insn does not trap on denormals. */
32685 {
32690 }
32694 /* The round insn does not trap on denormals. */
32699 {
32704 }
32708 /* The round insn does not trap on denormals. */
32713 {
32718 }
32722 /* The round insn does not trap on denormals. */
32727 {
32732 }
32736 /* The round insn does not trap on denormals. */
32741 {
32746 }
32750 /* The round insn does not trap on denormals. */
32755 {
32760 }
32764 /* The round insn does not trap on denormals. */
32769 {
32774 }
32778 /* The round insn does not trap on denormals. */
32783 {
32788 }
32792 /* The round insn does not trap on denormals. */
32797 {
32802 }
32806 /* The round insn does not trap on denormals. */
32811 {
32816 }
32821 {
32826 }
32831 {
32836 }
32841 }
32843 /* Dispatch to a handler for a vectorization library. */
32846 type_in);
32849 }
32851 /* Handler for an SVML-style interface to
32852 a library with vectorized intrinsics. */
32854 static tree
32856 {
32864 /* The SVML is suitable for unsafe math only. */
32877 {
32924 }
32933 {
32936 }
32937 else
32940 /* Convert to uppercase. */
32945 args;
32947 arity++;
32951 else
32954 /* Build a function declaration for the vectorized function. */
32963 }
32965 /* Handler for an ACML-style interface to
32966 a library with vectorized intrinsics. */
32968 static tree
32970 {
32978 /* The ACML is 64bits only and suitable for unsafe math only as
32979 it does not correctly support parts of IEEE with the required
32980 precision such as denormals. */
32994 {
33024 }
33031 args;
33033 arity++;
33037 else
33040 /* Build a function declaration for the vectorized function. */
33049 }
33051 /* Returns a decl of a function that implements gather load with
33052 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
33053 Return NULL_TREE if it is not available. */
33055 static tree
33058 {
33074 /* v*gather* insn sign extends index to pointer mode. */
33086 {
33113 }
33116 }
33118 /* Returns a code for a target-specific builtin that implements
33119 reciprocal of the function, or NULL_TREE if not available. */
33121 static tree
33124 {
33131 /* Machine dependent builtins. */
33133 {
33134 /* Vectorized version of sqrt to rsqrt conversion. */
33143 }
33144 else
33145 /* Normal builtins. */
33147 {
33148 /* Sqrt to rsqrt conversion. */
33154 }
33155 }
33156 \f
33157 /* Helper for avx_vpermilps256_operand et al. This is also used by
33158 the expansion functions to turn the parallel back into a mask.
33159 The return value is 0 for no match and the imm8+1 for a match. */
33161 int
33163 {
33171 /* Validate that all of the elements are constants, and not totally
33172 out of range. Copy the data into an integral array to make the
33173 subsequent checks easier. */
33175 {
33185 }
33188 {
33190 /* In the 256-bit DFmode case, we can only move elements within
33191 a 128-bit lane. */
33193 {
33197 }
33199 {
33203 }
33207 /* In the 256-bit SFmode case, we have full freedom of movement
33208 within the low 128-bit lane, but the high 128-bit lane must
33209 mirror the exact same pattern. */
33214 /* FALLTHRU */
33218 /* In the 128-bit case, we've full freedom in the placement of
33219 the elements from the source operand. */
33226 }
33228 /* Make sure success has a non-zero value by adding one. */
33230 }
33232 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
33233 the expansion functions to turn the parallel back into a mask.
33234 The return value is 0 for no match and the imm8+1 for a match. */
33236 int
33238 {
33246 /* Validate that all of the elements are constants, and not totally
33247 out of range. Copy the data into an integral array to make the
33248 subsequent checks easier. */
33250 {
33260 }
33262 /* Validate that the halves of the permute are halves. */
33270 /* Reconstruct the mask. */
33272 {
33278 }
33280 /* Make sure success has a non-zero value by adding one. */
33282 }
33283 \f
33284 /* Store OPERAND to the memory after reload is completed. This means
33285 that we can't easily use assign_stack_local. */
33286 rtx
33288 {
33289 rtx result;
33293 {
33296 stack_pointer_rtx,
33299 }
33301 {
33303 {
33307 /* FALLTHRU */
33313 stack_pointer_rtx)),
33314 operand));
33318 }
33320 }
33321 else
33322 {
33324 {
33326 {
33333 stack_pointer_rtx)),
33339 stack_pointer_rtx)),
33341 }
33344 /* Store HImodes as SImodes. */
33346 /* FALLTHRU */
33352 stack_pointer_rtx)),
33353 operand));
33357 }
33359 }
33361 }
33363 /* Free operand from the memory. */
33364 void
33366 {
33368 {
33373 else
33375 /* Use LEA to deallocate stack space. In peephole2 it will be converted
33376 to pop or add instruction if registers are available. */
33380 }
33381 }
33383 /* Return a register priority for hard reg REGNO. */
33384 static int
33386 {
33387 /* ebp and r13 as the base always wants a displacement, r12 as the
33388 base always wants an index. So discourage their usage in an
33389 address. */
33394 /* New x86-64 int registers result in bigger code size. Discourage
33395 them. */
33398 /* New x86-64 SSE registers result in bigger code size. Discourage
33399 them. */
33402 /* Usage of AX register results in smaller code. Prefer it. */
33406 }
33408 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
33410 Put float CONST_DOUBLE in the constant pool instead of fp regs.
33411 QImode must go into class Q_REGS.
33412 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
33413 movdf to do mem-to-mem moves through integer regs. */
33415 static reg_class_t
33417 {
33420 /* We're only allowed to return a subclass of CLASS. Many of the
33421 following checks fail for NO_REGS, so eliminate that early. */
33425 /* All classes can load zeros. */
33429 /* Force constants into memory if we are loading a (nonzero) constant into
33430 an MMX or SSE register. This is because there are no MMX/SSE instructions
33431 to load from a constant. */
33436 /* Prefer SSE regs only, if we can use them for math. */
33440 /* Floating-point constants need more complex checks. */
33442 {
33443 /* General regs can load everything. */
33447 /* Floats can load 0 and 1 plus some others. Note that we eliminated
33448 zero above. We only want to wind up preferring 80387 registers if
33449 we plan on doing computation with them. */
33452 {
33453 /* Limit class to non-sse. */
33462 }
33465 }
33467 /* Generally when we see PLUS here, it's the function invariant
33468 (plus soft-fp const_int). Which can only be computed into general
33469 regs. */
33473 /* QImode constants are easy to load, but non-constant QImode data
33474 must go into Q_REGS. */
33476 {
33482 }
33485 }
33487 /* Discourage putting floating-point values in SSE registers unless
33488 SSE math is being used, and likewise for the 387 registers. */
33489 static reg_class_t
33491 {
33494 /* Restrict the output reload class to the register bank that we are doing
33495 math on. If we would like not to return a subset of CLASS, reject this
33496 alternative: if reload cannot do this, it will still use its choice. */
33502 {
33507 else
33509 }
33512 }
33514 static reg_class_t
33517 {
33518 /* Double-word spills from general registers to non-offsettable memory
33519 references (zero-extended addresses) require special handling. */
33525 {
33527 ? CODE_FOR_reload_noff_load
33529 /* Add the cost of moving address to a temporary. */
33533 }
33535 /* QImode spills from non-QI registers require
33536 intermediate register on 32bit targets. */
33545 {
33550 else
33556 /* Return Q_REGS if the operand is in memory. */
33559 }
33561 /* This condition handles corner case where an expression involving
33562 pointers gets vectorized. We're trying to use the address of a
33563 stack slot as a vector initializer.
33565 (set (reg:V2DI 74 [ vect_cst_.2 ])
33566 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
33568 Eventually frame gets turned into sp+offset like this:
33570 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33571 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
33572 (const_int 392 [0x188]))))
33574 That later gets turned into:
33576 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33577 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
33578 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
33580 We'll have the following reload recorded:
33582 Reload 0: reload_in (DI) =
33583 (plus:DI (reg/f:DI 7 sp)
33584 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
33585 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33586 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
33587 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
33588 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
33589 reload_reg_rtx: (reg:V2DI 22 xmm1)
33591 Which isn't going to work since SSE instructions can't handle scalar
33592 additions. Returning GENERAL_REGS forces the addition into integer
33593 register and reload can handle subsequent reloads without problems. */
33601 }
33603 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
33605 static bool
33607 {
33609 {
33624 }
33627 }
33629 /* If we are copying between general and FP registers, we need a memory
33630 location. The same is true for SSE and MMX registers.
33632 To optimize register_move_cost performance, allow inline variant.
33634 The macro can't work reliably when one of the CLASSES is class containing
33635 registers from multiple units (SSE, MMX, integer). We avoid this by never
33636 combining those units in single alternative in the machine description.
33637 Ensure that this constraint holds to avoid unexpected surprises.
33639 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
33640 enforce these sanity checks. */
33645 {
33652 {
33655 }
33660 /* ??? This is a lie. We do have moves between mmx/general, and for
33661 mmx/sse2. But by saying we need secondary memory we discourage the
33662 register allocator from using the mmx registers unless needed. */
33667 {
33668 /* SSE1 doesn't have any direct moves from other classes. */
33672 /* If the target says that inter-unit moves are more expensive
33673 than moving through memory, then don't generate them. */
33678 /* Between SSE and general, we have moves no larger than word size. */
33681 }
33684 }
33686 bool
33689 {
33691 }
33693 /* Implement the TARGET_CLASS_MAX_NREGS hook.
33695 On the 80386, this is the size of MODE in words,
33696 except in the FP regs, where a single reg is always enough. */
33698 static unsigned char
33700 {
33702 {
33707 else
33709 }
33710 else
33711 {
33714 else
33716 }
33717 }
33719 /* Return true if the registers in CLASS cannot represent the change from
33720 modes FROM to TO. */
33722 bool
33725 {
33729 /* x87 registers can't do subreg at all, as all values are reformatted
33730 to extended precision. */
33735 {
33736 /* Vector registers do not support QI or HImode loads. If we don't
33737 disallow a change to these modes, reload will assume it's ok to
33738 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
33739 the vec_dupv4hi pattern. */
33743 /* Vector registers do not support subreg with nonzero offsets, which
33744 are otherwise valid for integer registers. Since we can't see
33745 whether we have a nonzero offset from here, prohibit all
33746 nonparadoxical subregs changing size. */
33749 }
33752 }
33754 /* Return the cost of moving data of mode M between a
33755 register and memory. A value of 2 is the default; this cost is
33756 relative to those in `REGISTER_MOVE_COST'.
33758 This function is used extensively by register_move_cost that is used to
33759 build tables at startup. Make it inline in this case.
33760 When IN is 2, return maximum of in and out move cost.
33762 If moving between registers and memory is more expensive than
33763 between two registers, you should define this macro to express the
33764 relative cost.
33766 Model also increased moving costs of QImode registers in non
33767 Q_REGS classes.
33768 */
33772 {
33775 {
33778 {
33790 }
33794 }
33796 {
33799 {
33811 }
33815 }
33817 {
33820 {
33829 }
33833 }
33835 {
33838 {
33844 else
33849 }
33850 else
33851 {
33856 else
33858 }
33865 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
33872 else
33876 }
33877 }
33879 static int
33882 {
33884 }
33887 /* Return the cost of moving data from a register in class CLASS1 to
33888 one in class CLASS2.
33890 It is not required that the cost always equal 2 when FROM is the same as TO;
33891 on some machines it is expensive to move between registers if they are not
33892 general registers. */
33894 static int
33896 reg_class_t class2_i)
33897 {
33901 /* In case we require secondary memory, compute cost of the store followed
33902 by load. In order to avoid bad register allocation choices, we need
33903 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
33906 {
33912 /* In case of copying from general_purpose_register we may emit multiple
33913 stores followed by single load causing memory size mismatch stall.
33914 Count this as arbitrarily high cost of 20. */
33919 /* In the case of FP/MMX moves, the registers actually overlap, and we
33920 have to switch modes in order to treat them differently. */
33926 }
33928 /* Moves between SSE/MMX and integer unit are expensive. */
33932 /* ??? By keeping returned value relatively high, we limit the number
33933 of moves between integer and MMX/SSE registers for all targets.
33934 Additionally, high value prevents problem with x86_modes_tieable_p(),
33935 where integer modes in MMX/SSE registers are not tieable
33936 because of missing QImode and HImode moves to, from or between
33937 MMX/SSE registers. */
33947 }
33949 /* Return TRUE if hard register REGNO can hold a value of machine-mode
33950 MODE. */
33952 bool
33954 {
33955 /* Flags and only flags can only hold CCmode values. */
33965 {
33966 /* We implement the move patterns for all vector modes into and
33967 out of SSE registers, even when no operation instructions
33968 are available. OImode move is available only when AVX is
33969 enabled. */
33976 }
33978 {
33979 /* We implement the move patterns for 3DNOW modes even in MMX mode,
33980 so if the register is available at all, then we can move data of
33981 the given mode into or out of it. */
33984 }
33987 {
33988 /* Take care for QImode values - they can be in non-QI regs,
33989 but then they do cause partial register stalls. */
33994 /* LRA checks if the hard register is OK for the given mode.
33995 QImode values can live in non-QI regs, so we allow all
33996 registers here. */
34000 }
34001 /* We handle both integer and floats in the general purpose registers. */
34008 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
34009 on to use that value in smaller contexts, this can easily force a
34010 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
34011 supporting DImode, allow it. */
34016 }
34018 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
34019 tieable integer mode. */
34021 static bool
34023 {
34025 {
34038 }
34039 }
34041 /* Return true if MODE1 is accessible in a register that can hold MODE2
34042 without copying. That is, all register classes that can hold MODE2
34043 can also hold MODE1. */
34045 bool
34047 {
34055 /* MODE2 being XFmode implies fp stack or general regs, which means we
34056 can tie any smaller floating point modes to it. Note that we do not
34057 tie this with TFmode. */
34061 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
34062 that we can tie it with SFmode. */
34066 /* If MODE2 is only appropriate for an SSE register, then tie with
34067 any other mode acceptable to SSE registers. */
34077 /* If MODE2 is appropriate for an MMX register, then tie
34078 with any other mode acceptable to MMX registers. */
34085 }
34087 /* Return the cost of moving between two registers of mode MODE. */
34089 static int
34091 {
34095 {
34126 }
34128 /* Return the cost of moving between two registers of mode MODE,
34129 assuming that the move will be in pieces of at most UNITS bytes. */
34131 }
34133 /* Compute a (partial) cost for rtx X. Return true if the complete
34134 cost has been computed, and false if subexpressions should be
34135 scanned. In either case, *TOTAL contains the cost result. */
34137 static bool
34140 {
34147 {
34151 {
34154 }
34166 && (!TARGET_64BIT
34171 else
34177 {
34180 }
34182 {
34192 }
34194 {
34197 {
34206 }
34207 }
34208 /* Fall back to (MEM (SYMBOL_REF)), since that's where
34209 it'll probably end up. Add a penalty for size. */
34216 /* The zero extensions is often completely free on x86_64, so make
34217 it as cheap as possible. */
34223 else
34235 {
34238 {
34241 }
34244 {
34247 }
34248 }
34249 /* FALLTHRU */
34256 {
34257 /* ??? Should be SSE vector operation cost. */
34258 /* At least for published AMD latencies, this really is the same
34259 as the latency for a simple fpu operation like fabs. */
34260 /* V*QImode is emulated with 1-11 insns. */
34262 {
34265 {
34266 /* For XOP we use vpshab, which requires a broadcast of the
34267 value to the variable shift insn. For constants this
34268 means a V16Q const in mem; even when we can perform the
34269 shift with one insn set the cost to prefer paddb. */
34271 {
34276 }
34278 }
34282 }
34283 else
34285 }
34287 {
34289 {
34292 else
34294 }
34295 else
34296 {
34299 else
34301 }
34302 }
34303 else
34304 {
34309 {
34310 /* Return the cost after shift-and truncation. */
34313 }
34314 else
34316 }
34320 {
34321 rtx sub;
34326 /* ??? SSE scalar/vector cost should be used here. */
34327 /* ??? Bald assumption that fma has the same cost as fmul. */
34331 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
34342 }
34346 {
34347 /* ??? SSE scalar cost should be used here. */
34350 }
34352 {
34355 }
34357 {
34358 /* ??? SSE vector cost should be used here. */
34361 }
34363 {
34364 /* V*QImode is emulated with 7-13 insns. */
34366 {
34373 }
34374 /* V*DImode is emulated with 5-8 insns. */
34376 {
34379 else
34381 }
34382 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
34383 insns, including two PMULUDQ. */
34386 else
34389 }
34390 else
34391 {
34396 {
34399 nbits++;
34400 }
34401 else
34402 /* This is arbitrary. */
34405 /* Compute costs correctly for widening multiplication. */
34409 {
34416 {
34420 else
34422 }
34426 }
34434 }
34441 /* ??? SSE cost should be used here. */
34446 /* ??? SSE vector cost should be used here. */
34448 else
34455 {
34460 {
34463 {
34471 }
34472 }
34475 {
34478 {
34484 }
34485 }
34487 {
34495 }
34496 }
34497 /* FALLTHRU */
34501 {
34502 /* ??? SSE cost should be used here. */
34505 }
34507 {
34510 }
34512 {
34513 /* ??? SSE vector cost should be used here. */
34516 }
34517 /* FALLTHRU */
34524 {
34531 }
34532 /* FALLTHRU */
34536 {
34537 /* ??? SSE cost should be used here. */
34540 }
34542 {
34545 }
34547 {
34548 /* ??? SSE vector cost should be used here. */
34551 }
34552 /* FALLTHRU */
34556 {
34557 /* ??? Should be SSE vector operation cost. */
34558 /* At least for published AMD latencies, this really is the same
34559 as the latency for a simple fpu operation like fabs. */
34561 }
34564 else
34573 {
34574 /* This kind of construct is implemented using test[bwl].
34575 Treat it as if we had an AND. */
34580 }
34590 /* ??? SSE cost should be used here. */
34595 /* ??? SSE vector cost should be used here. */
34601 /* ??? SSE cost should be used here. */
34606 /* ??? SSE vector cost should be used here. */
34619 /* ??? Assume all of these vector manipulation patterns are
34620 recognizable. In which case they all pretty much have the
34621 same cost. */
34627 }
34628 }
34630 #if TARGET_MACHO
34634 /* Given a symbol name and its associated stub, write out the
34635 definition of the stub. */
34637 void
34639 {
34644 /* For 64-bit we shouldn't get here. */
34647 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
34664 else
34671 {
34673 }
34675 {
34676 /* PIC stub. */
34677 /* 25-byte PIC stub using "CALL get_pc_thunk". */
34683 }
34684 else
34687 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
34688 it needs no stub-binding-helper. */
34695 {
34698 }
34699 else
34704 /* N.B. Keep the correspondence of these
34705 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
34706 old-pic/new-pic/non-pic stubs; altering this will break
34707 compatibility with existing dylibs. */
34709 {
34710 /* 25-byte PIC stub using "CALL get_pc_thunk". */
34712 }
34713 else
34714 /* 16-byte -mdynamic-no-pic stub. */
34720 }
34723 /* Order the registers for register allocator. */
34725 void
34727 {
34731 /* First allocate the local general purpose registers. */
34736 /* Global general purpose registers. */
34741 /* x87 registers come first in case we are doing FP math
34742 using them. */
34747 /* SSE registers. */
34753 /* x87 registers. */
34761 /* Initialize the rest of array as we do not allocate some registers
34762 at all. */
34765 }
34767 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
34768 in struct attribute_spec handler. */
34769 static tree
34771 tree args,
34774 {
34779 {
34781 name);
34784 }
34786 {
34788 name);
34791 }
34793 {
34794 tree cst;
34798 {
34801 name);
34803 }
34806 {
34809 name);
34811 }
34814 }
34817 }
34819 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
34820 struct attribute_spec.handler. */
34821 static tree
34823 tree args ATTRIBUTE_UNUSED,
34825 {
34830 {
34832 name);
34835 }
34837 /* Can combine regparm with all attributes but fastcall. */
34839 {
34841 {
34843 }
34846 }
34848 {
34850 {
34852 }
34855 }
34858 }
34860 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
34861 struct attribute_spec.handler. */
34862 static tree
34864 tree args ATTRIBUTE_UNUSED,
34866 {
34869 {
34872 }
34873 else
34877 {
34879 name);
34881 }
34887 {
34889 name);
34891 }
34894 }
34896 static tree
34898 tree args ATTRIBUTE_UNUSED,
34900 {
34902 {
34904 name);
34906 }
34908 }
34910 static bool
34912 {
34916 }
34918 /* Returns an expression indicating where the this parameter is
34919 located on entry to the FUNCTION. */
34921 static rtx
34923 {
34929 {
34934 else
34937 }
34942 {
34949 {
34954 }
34955 else
34956 {
34959 {
34965 }
34966 }
34968 }
34972 }
34974 /* Determine whether x86_output_mi_thunk can succeed. */
34976 static bool
34978 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
34980 {
34981 /* 64-bit can handle anything. */
34985 /* For 32-bit, everything's fine if we have one free register. */
34989 /* Need a free register for vcall_offset. */
34993 /* Need a free register for GOT references. */
34997 /* Otherwise ok. */
34999 }
35001 /* Output the assembler code for a thunk function. THUNK_DECL is the
35002 declaration for the thunk function itself, FUNCTION is the decl for
35003 the target function. DELTA is an immediate constant offset to be
35004 added to THIS. If VCALL_OFFSET is nonzero, the word at
35005 *(*this + vcall_offset) should be added to THIS. */
35007 static void
35011 {
35018 else
35019 {
35025 else
35027 }
35031 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
35032 pull it in now and let DELTA benefit. */
35036 {
35037 /* Put the this parameter into %eax. */
35040 }
35041 else
35044 /* Adjust the this parameter by a fixed constant. */
35046 {
35051 {
35053 {
35057 }
35058 }
35061 }
35063 /* Adjust the this parameter by a value stored in the vtable. */
35065 {
35075 /* Adjust the this parameter. */
35079 {
35083 }
35090 vcall_mem));
35091 else
35093 }
35095 /* If necessary, drop THIS back to its stack slot. */
35101 {
35104 ;
35105 else
35106 {
35110 }
35111 }
35112 else
35113 {
35115 ;
35116 #if TARGET_MACHO
35118 {
35121 }
35123 else
35124 {
35131 }
35132 }
35134 /* Our sibling call patterns do not allow memories, because we have no
35135 predicate that can distinguish between frame and non-frame memory.
35136 For our purposes here, we can get away with (ab)using a jump pattern,
35137 because we're going to do no optimization. */
35140 else
35141 {
35147 {
35153 }
35159 }
35162 /* Emit just enough of rest_of_compilation to get the insns emitted.
35163 Note that use_thunk calls assemble_start_function et al. */
35169 }
35171 static void
35173 {
35175 #if TARGET_MACHO
35177 #endif
35184 }
35186 int
35188 {
35200 }
35202 /* Output assembler code to FILE to increment profiler label # LABELNO
35203 for profiling a function entry. */
35204 void
35206 {
35211 {
35212 #ifndef NO_PROFILE_COUNTERS
35214 #endif
35218 else
35220 }
35222 {
35223 #ifndef NO_PROFILE_COUNTERS
35226 #endif
35228 }
35229 else
35230 {
35231 #ifndef NO_PROFILE_COUNTERS
35234 #endif
35236 }
35237 }
35239 /* We don't have exact information about the insn sizes, but we may assume
35240 quite safely that we are informed about all 1 byte insns and memory
35241 address sizes. This is enough to eliminate unnecessary padding in
35242 99% of cases. */
35244 static int
35246 {
35252 /* Discard alignments we've emit and jump instructions. */
35257 /* Important case - calls are always 5 bytes.
35258 It is common to have many calls in the row. */
35267 /* For normal instructions we rely on get_attr_length being exact,
35268 with a few exceptions. */
35270 {
35274 {
35284 /* Otherwise trust get_attr_length. */
35286 }
35291 }
35294 else
35296 }
35298 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
35300 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
35301 window. */
35303 static void
35305 {
35310 /* Look for all minimal intervals of instructions containing 4 jumps.
35311 The intervals are bounded by START and INSN. NBYTES is the total
35312 size of instructions in the interval including INSN and not including
35313 START. When the NBYTES is smaller than 16 bytes, it is possible
35314 that the end of START and INSN ends up in the same 16byte page.
35316 The smallest offset in the page INSN can start is the case where START
35317 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
35318 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
35319 */
35321 {
35325 {
35331 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
35332 already in the current 16 byte page, because otherwise
35333 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
35334 bytes to reach 16 byte boundary. */
35342 {
35344 {
35348 else
35351 }
35352 }
35354 }
35362 njumps++;
35363 else
35367 {
35371 else
35374 }
35381 {
35388 }
35389 }
35390 }
35391 #endif
35393 /* AMD Athlon works faster
35394 when RET is not destination of conditional jump or directly preceded
35395 by other jump instruction. We avoid the penalty by inserting NOP just
35396 before the RET instructions in such cases. */
35397 static void
35399 {
35400 edge e;
35401 edge_iterator ei;
35404 {
35407 rtx prev;
35417 {
35418 edge e;
35419 edge_iterator ei;
35425 }
35427 {
35433 /* Empty functions get branch mispredict even when
35434 the jump destination is not visible to us. */
35437 }
35439 {
35442 }
35443 }
35444 }
35446 /* Count the minimum number of instructions in BB. Return 4 if the
35447 number of instructions >= 4. */
35449 static int
35451 {
35452 rtx insn;
35455 /* Count number of instructions in this block. Return 4 if the number
35456 of instructions >= 4. */
35458 {
35459 /* Only happen in exit blocks. */
35467 {
35468 insn_count++;
35471 }
35472 }
35475 }
35478 /* Count the minimum number of instructions in code path in BB.
35479 Return 4 if the number of instructions >= 4. */
35481 static int
35483 {
35484 edge e;
35485 edge_iterator ei;
35488 /* Only bother counting instructions along paths with no
35489 more than 2 basic blocks between entry and exit. Given
35490 that BB has an edge to exit, determine if a predecessor
35491 of BB has an edge from entry. If so, compute the number
35492 of instructions in the predecessor block. If there
35493 happen to be multiple such blocks, compute the minimum. */
35496 {
35497 edge prev_e;
35498 edge_iterator prev_ei;
35501 {
35504 }
35506 {
35508 {
35513 }
35514 }
35515 }
35521 }
35523 /* Pad short function to 4 instructions. */
35525 static void
35527 {
35528 edge e;
35529 edge_iterator ei;
35532 {
35535 {
35538 /* Pad short function. */
35540 {
35543 /* Find epilogue. */
35552 /* Two NOPs count as one instruction. */
35555 }
35556 }
35557 }
35558 }
35560 /* Implement machine specific optimizations. We implement padding of returns
35561 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
35562 static void
35564 {
35565 /* We are freeing block_for_insn in the toplev to keep compatibility
35566 with old MDEP_REORGS that are not CFG based. Recompute it now. */
35570 {
35575 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
35578 #endif
35579 }
35580 }
35582 /* Return nonzero when QImode register that must be represented via REX prefix
35583 is used. */
35584 bool
35586 {
35594 }
35596 /* Return nonzero when P points to register encoded via REX prefix.
35597 Called via for_each_rtx. */
35598 static int
35600 {
35606 }
35608 /* Return true when INSN mentions register that must be encoded using REX
35609 prefix. */
35610 bool
35612 {
35615 }
35617 /* If profitable, negate (without causing overflow) integer constant
35618 of mode MODE at location LOC. Return true in this case. */
35619 bool
35621 {
35622 HOST_WIDE_INT val;
35628 {
35630 /* DImode x86_64 constants must fit in 32 bits. */
35643 }
35645 /* Avoid overflows. */
35651 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
35652 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
35655 {
35658 }
35661 }
35663 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
35664 optabs would emit if we didn't have TFmode patterns. */
35666 void
35668 {
35702 }
35703 \f
35704 /* AVX2 does support 32-byte integer vector operations,
35705 thus the longest vector we are faced with is V32QImode. */
35706 #define MAX_VECT_LEN 32
35708 struct expand_vec_perm_d
35709 {
35716 };
35722 /* Get a vector mode of the same size as the original but with elements
35723 twice as wide. This is only guaranteed to apply to integral vectors. */
35727 {
35728 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
35733 }
35735 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35736 with all elements equal to VAR. Return true if successful. */
35738 static bool
35741 {
35745 {
35750 /* FALLTHRU */
35760 {
35763 /* First attempt to recognize VAL as-is. */
35767 {
35768 rtx seq;
35769 /* If that fails, force VAL into a register. */
35780 }
35781 }
35788 {
35789 rtx x;
35796 }
35806 {
35810 permute:
35818 /* Extend to SImode using a paradoxical SUBREG. */
35822 /* Insert the SImode value as low element of a V4SImode vector. */
35830 }
35838 widen:
35839 /* Replicate the value once into the next wider mode and recurse. */
35840 {
35842 rtx x;
35858 }
35862 {
35871 }
35876 }
35877 }
35879 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
35880 whose ONE_VAR element is VAR, and other elements are zero. Return true
35881 if successful. */
35883 static bool
35886 {
35888 rtx new_target;
35893 {
35895 /* For SSE4.1, we normally use vector set. But if the second
35896 element is zero and inter-unit moves are OK, we use movq
35897 instead. */
35899 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
35921 /* Use ix86_expand_vector_set in 64bit mode only. */
35926 }
35929 {
35934 }
35937 {
35942 /* FALLTHRU */
35957 else
35964 {
35965 /* We need to shuffle the value to the correct position, so
35966 create a new pseudo to store the intermediate result. */
35968 /* With SSE2, we can use the integer shuffle insns. */
35970 {
35972 const1_rtx,
35979 }
35981 /* Otherwise convert the intermediate result to V4SFmode and
35982 use the SSE1 shuffle instructions. */
35984 {
35987 }
35988 else
35992 const1_rtx,
36001 }
36016 widen:
36020 /* Zero extend the variable element to SImode and recurse. */
36033 }
36034 }
36036 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
36037 consisting of the values in VALS. It is known that all elements
36038 except ONE_VAR are constants. Return true if successful. */
36040 static bool
36043 {
36053 {
36058 /* For the two element vectors, it's just as easy to use
36059 the general case. */
36063 /* Use ix86_expand_vector_set in 64bit mode only. */
36085 widen:
36086 /* There's no way to set one QImode entry easily. Combine
36087 the variable value with its adjacent constant value, and
36088 promote to an HImode set. */
36091 {
36096 }
36097 else
36098 {
36101 }
36115 }
36120 }
36122 /* A subroutine of ix86_expand_vector_init_general. Use vector
36123 concatenate to handle the most general case: all values variable,
36124 and none identical. */
36126 static void
36129 {
36132 rtvec v;
36136 {
36139 {
36172 }
36185 {
36200 }
36205 {
36216 }
36219 half:
36220 /* FIXME: We process inputs backward to help RA. PR 36222. */
36224 {
36229 }
36233 {
36236 {
36240 }
36243 }
36244 else
36250 }
36251 }
36253 /* A subroutine of ix86_expand_vector_init_general. Use vector
36254 interleave to handle the most general case: all values variable,
36255 and none identical. */
36257 static void
36260 {
36269 {
36290 }
36293 {
36294 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
36298 /* Insert the SImode value as low element of V4SImode vector. */
36302 op0),
36304 const1_rtx);
36307 /* Cast the V4SImode vector back to a vector in orignal mode. */
36311 /* Load even elements into the second positon. */
36315 const1_rtx));
36317 /* Cast vector to FIRST_IMODE vector. */
36320 }
36322 /* Interleave low FIRST_IMODE vectors. */
36324 {
36328 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
36331 }
36333 /* Interleave low SECOND_IMODE vectors. */
36335 {
36338 {
36343 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
36344 vector. */
36347 }
36350 /* FALLTHRU */
36357 /* Cast the SECOND_IMODE vector back to a vector on original
36358 mode. */
36365 }
36366 }
36368 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
36369 all values variable, and none identical. */
36371 static void
36374 {
36380 {
36385 /* FALLTHRU */
36409 half:
36426 /* FALLTHRU */
36432 /* Don't use ix86_expand_vector_init_interleave if we can't
36433 move from GPR to SSE register directly. */
36449 }
36451 {
36463 {
36467 {
36473 else
36474 {
36479 }
36480 }
36483 }
36488 {
36494 }
36496 {
36502 }
36503 else
36505 }
36506 }
36508 /* Initialize vector TARGET via VALS. Suppress the use of MMX
36509 instructions unless MMX_OK is true. */
36511 void
36513 {
36520 rtx x;
36523 {
36533 }
36535 /* Constants are best loaded from the constant pool. */
36537 {
36540 }
36542 /* If all values are identical, broadcast the value. */
36548 /* Values where only one field is non-constant are best loaded from
36549 the pool and overwritten via move later. */
36551 {
36555 one_var))
36560 }
36563 }
36565 void
36567 {
36572 rtx tmp;
36574 = {
36581 };
36583 = {
36590 };
36594 {
36598 {
36603 else
36607 }
36619 else
36625 {
36628 /* For the two element vectors, we implement a VEC_CONCAT with
36629 the extraction of the other element. */
36636 else
36641 }
36650 {
36656 /* tmp = target = A B C D */
36658 /* target = A A B B */
36660 /* target = X A B B */
36662 /* target = A X C D */
36669 /* tmp = target = A B C D */
36671 /* tmp = X B C D */
36673 /* target = A B X D */
36680 /* tmp = target = A B C D */
36682 /* tmp = X B C D */
36684 /* target = A B X D */
36692 }
36700 /* Element 0 handled by vec_merge below. */
36702 {
36705 }
36708 {
36709 /* With SSE2, use integer shuffles to swap element 0 and ELT,
36710 store into element 0, then shuffle them back. */
36727 }
36728 else
36729 {
36730 /* For SSE1, we have to reuse the V4SF code. */
36733 }
36786 half:
36787 /* Compute offset. */
36793 /* Extract the half. */
36797 /* Put val in tmp at elt. */
36800 /* Put it back. */
36806 }
36809 {
36813 }
36814 else
36815 {
36824 }
36825 }
36827 void
36829 {
36833 rtx tmp;
36836 {
36841 /* FALLTHRU */
36854 {
36874 }
36886 {
36888 {
36908 }
36912 }
36913 else
36914 {
36915 /* For SSE1, we have to reuse the V4SF code. */
36919 }
36935 {
36939 else
36943 }
36948 {
36952 else
36956 }
36961 {
36965 else
36969 }
36974 {
36978 else
36982 }
36987 {
36991 else
36995 }
37000 {
37004 else
37008 }
37012 /* ??? Could extract the appropriate HImode element and shift. */
37015 }
37018 {
37022 /* Let the rtl optimizers know about the zero extension performed. */
37024 {
37027 }
37030 }
37031 else
37032 {
37039 }
37040 }
37042 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
37043 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
37044 The upper bits of DEST are undefined, though they shouldn't cause
37045 exceptions (some bits from src or all zeros are ok). */
37047 static void
37049 {
37050 rtx tem;
37052 {
37056 else
37074 else
37081 else
37092 const1_rtx);
37093 else
37100 }
37102 }
37104 /* Expand a vector reduction. FN is the binary pattern to reduce;
37105 DEST is the destination; IN is the input vector. */
37107 void
37109 {
37114 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
37118 {
37121 }
37126 {
37131 else
37135 }
37136 }
37137 \f
37138 /* Target hook for scalar_mode_supported_p. */
37139 static bool
37141 {
37146 else
37148 }
37150 /* Implements target hook vector_mode_supported_p. */
37151 static bool
37153 {
37165 }
37167 /* Target hook for c_mode_for_suffix. */
37168 static enum machine_mode
37170 {
37177 }
37179 /* Worker function for TARGET_MD_ASM_CLOBBERS.
37181 We do this in the new i386 backend to maintain source compatibility
37182 with the old cc0-based compiler. */
37184 static tree
37186 tree inputs ATTRIBUTE_UNUSED,
37187 tree clobbers)
37188 {
37190 clobbers);
37192 clobbers);
37194 }
37196 /* Implements target vector targetm.asm.encode_section_info. */
37198 static void ATTRIBUTE_UNUSED
37200 {
37207 }
37209 /* Worker function for REVERSE_CONDITION. */
37211 enum rtx_code
37213 {
37217 }
37219 /* Output code to perform an x87 FP register move, from OPERANDS[1]
37220 to OPERANDS[0]. */
37224 {
37226 {
37229 {
37233 }
37237 }
37239 {
37243 else
37244 {
37245 /* There is no non-popping store to memory for XFmode.
37246 So if we need one, follow the store with a load. */
37249 else
37251 }
37252 }
37253 else
37255 }
37257 /* Output code to perform a conditional jump to LABEL, if C2 flag in
37258 FP status register is set. */
37260 void
37262 {
37264 rtx temp;
37269 {
37274 }
37275 else
37276 {
37281 }
37285 pc_rtx);
37290 }
37292 /* Output code to perform a log1p XFmode calculation. */
37295 {
37301 rtx test;
37307 XFmode));
37321 }
37323 /* Emit code for round calculation. */
37325 {
37332 rtx insn;
37337 {
37349 }
37352 {
37373 }
37381 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
37383 /* scratch = fxam(op1) */
37386 UNSPEC_FXAM)));
37387 /* e1 = fabs(op1) */
37390 /* e2 = e1 + 0.5 */
37395 /* res = floor(e2) */
37397 {
37402 }
37403 else
37407 {
37410 {
37417 UNSPEC_TRUNC_NOOP)));
37418 }
37434 }
37436 /* flags = signbit(a) */
37439 /* if (flags) then res = -res */
37443 pc_rtx);
37454 }
37456 /* Output code to perform a Newton-Rhapson approximation of a single precision
37457 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
37460 {
37468 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
37472 /* x0 = rcp(b) estimate */
37475 UNSPEC_RCP)));
37476 /* e0 = x0 * b */
37480 /* e0 = x0 * e0 */
37484 /* e1 = x0 + x0 */
37488 /* x1 = e1 - e0 */
37492 /* res = a * x1 */
37495 }
37497 /* Output code to perform a Newton-Rhapson approximation of a
37498 single precision floating point [reciprocal] square root. */
37502 {
37504 REAL_VALUE_TYPE r;
37519 {
37522 }
37524 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
37525 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
37529 /* x0 = rsqrt(a) estimate */
37532 UNSPEC_RSQRT)));
37534 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
37536 {
37548 }
37550 /* e0 = x0 * a */
37553 /* e1 = e0 * x0 */
37557 /* e2 = e1 - 3. */
37564 /* e3 = -.5 * x0 */
37567 else
37568 /* e3 = -.5 * e0 */
37571 /* ret = e2 * e3 */
37574 }
37576 #ifdef TARGET_SOLARIS
37577 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
37579 static void
37581 tree decl)
37582 {
37583 /* With Binutils 2.15, the "@unwind" marker must be specified on
37584 every occurrence of the ".eh_frame" section, not just the first
37585 one. */
37588 {
37592 }
37594 #ifndef USE_GAS
37596 {
37599 }
37600 #endif
37603 }
37606 /* Return the mangling of TYPE if it is an extended fundamental type. */
37610 {
37618 {
37620 /* __float128 is "g". */
37623 /* "long double" or __float80 is "e". */
37627 }
37628 }
37630 /* For 32-bit code we can save PIC register setup by using
37631 __stack_chk_fail_local hidden function instead of calling
37632 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
37633 register, so it is better to call __stack_chk_fail directly. */
37635 static tree ATTRIBUTE_UNUSED
37637 {
37638 return TARGET_64BIT
37641 }
37643 /* Select a format to encode pointers in exception handling data. CODE
37644 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
37645 true if the symbol may be affected by dynamic relocations.
37647 ??? All x86 object file formats are capable of representing this.
37648 After all, the relocation needed is the same as for the call insn.
37649 Whether or not a particular assembler allows us to enter such, I
37650 guess we'll have to see. */
37651 int
37653 {
37655 {
37662 }
37667 }
37668 \f
37669 /* Expand copysign from SIGN to the positive value ABS_VALUE
37670 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
37671 the sign-bit. */
37672 static void
37674 {
37678 {
37685 else
37690 {
37691 /* We need to generate a scalar mode mask in this case. */
37696 }
37697 }
37698 else
37704 }
37706 /* Expand fabs (OP0) and return a new rtx that holds the result. The
37707 mask for masking out the sign-bit is stored in *SMASK, if that is
37708 non-null. */
37709 static rtx
37711 {
37720 else
37724 {
37725 /* We need to generate a scalar mode mask in this case. */
37730 }
37738 }
37740 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
37741 swapping the operands if SWAP_OPERANDS is true. The expanded
37742 code is a forward jump to a newly created label in case the
37743 comparison is true. The generated label rtx is returned. */
37744 static rtx
37747 {
37751 {
37755 }
37768 }
37770 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
37771 using comparison code CODE. Operands are swapped for the comparison if
37772 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
37773 static rtx
37776 {
37782 {
37786 }
37793 }
37795 /* Generate and return a rtx of mode MODE for 2**n where n is the number
37796 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
37797 static rtx
37799 {
37800 REAL_VALUE_TYPE TWO52r;
37801 rtx TWO52;
37808 }
37810 /* Expand SSE sequence for computing lround from OP1 storing
37811 into OP0. */
37812 void
37814 {
37815 /* C code for the stuff we're doing below:
37816 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
37817 return (long)tmp;
37818 */
37822 rtx adj;
37824 /* load nextafter (0.5, 0.0) */
37829 /* adj = copysign (0.5, op1) */
37833 /* adj = op1 + adj */
37836 /* op0 = (imode)adj */
37838 }
37840 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
37841 into OPERAND0. */
37842 void
37844 {
37845 /* C code for the stuff we're doing below (for do_floor):
37846 xi = (long)op1;
37847 xi -= (double)xi > op1 ? 1 : 0;
37848 return xi;
37849 */
37854 /* reg = (long)op1 */
37858 /* freg = (double)reg */
37862 /* ireg = (freg > op1) ? ireg - 1 : ireg */
37873 }
37875 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
37876 result in OPERAND0. */
37877 void
37879 {
37880 /* C code for the stuff we're doing below:
37881 xa = fabs (operand1);
37882 if (!isless (xa, 2**52))
37883 return operand1;
37884 xa = xa + 2**52 - 2**52;
37885 return copysign (xa, operand1);
37886 */
37893 /* xa = abs (operand1) */
37896 /* if (!isless (xa, TWO52)) goto label; */
37909 }
37911 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
37912 into OPERAND0. */
37913 void
37915 {
37916 /* C code for the stuff we expand below.
37917 double xa = fabs (x), x2;
37918 if (!isless (xa, TWO52))
37919 return x;
37920 xa = xa + TWO52 - TWO52;
37921 x2 = copysign (xa, x);
37922 Compensate. Floor:
37923 if (x2 > x)
37924 x2 -= 1;
37925 Compensate. Ceil:
37926 if (x2 < x)
37927 x2 -= -1;
37928 return x2;
37929 */
37935 /* Temporary for holding the result, initialized to the input
37936 operand to ease control flow. */
37940 /* xa = abs (operand1) */
37943 /* if (!isless (xa, TWO52)) goto label; */
37946 /* xa = xa + TWO52 - TWO52; */
37950 /* xa = copysign (xa, operand1) */
37953 /* generate 1.0 or -1.0 */
37958 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
37962 /* We always need to subtract here to preserve signed zero. */
37971 }
37973 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
37974 into OPERAND0. */
37975 void
37977 {
37978 /* C code for the stuff we expand below.
37979 double xa = fabs (x), x2;
37980 if (!isless (xa, TWO52))
37981 return x;
37982 x2 = (double)(long)x;
37983 Compensate. Floor:
37984 if (x2 > x)
37985 x2 -= 1;
37986 Compensate. Ceil:
37987 if (x2 < x)
37988 x2 += 1;
37989 if (HONOR_SIGNED_ZEROS (mode))
37990 return copysign (x2, x);
37991 return x2;
37992 */
37998 /* Temporary for holding the result, initialized to the input
37999 operand to ease control flow. */
38003 /* xa = abs (operand1) */
38006 /* if (!isless (xa, TWO52)) goto label; */
38009 /* xa = (double)(long)x */
38014 /* generate 1.0 */
38017 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
38032 }
38034 /* Expand SSE sequence for computing round from OPERAND1 storing
38035 into OPERAND0. Sequence that works without relying on DImode truncation
38036 via cvttsd2siq that is only available on 64bit targets. */
38037 void
38039 {
38040 /* C code for the stuff we expand below.
38041 double xa = fabs (x), xa2, x2;
38042 if (!isless (xa, TWO52))
38043 return x;
38044 Using the absolute value and copying back sign makes
38045 -0.0 -> -0.0 correct.
38046 xa2 = xa + TWO52 - TWO52;
38047 Compensate.
38048 dxa = xa2 - xa;
38049 if (dxa <= -0.5)
38050 xa2 += 1;
38051 else if (dxa > 0.5)
38052 xa2 -= 1;
38053 x2 = copysign (xa2, x);
38054 return x2;
38055 */
38061 /* Temporary for holding the result, initialized to the input
38062 operand to ease control flow. */
38066 /* xa = abs (operand1) */
38069 /* if (!isless (xa, TWO52)) goto label; */
38072 /* xa2 = xa + TWO52 - TWO52; */
38076 /* dxa = xa2 - xa; */
38079 /* generate 0.5, 1.0 and -0.5 */
38085 /* Compensate. */
38087 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
38092 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
38098 /* res = copysign (xa2, operand1) */
38105 }
38107 /* Expand SSE sequence for computing trunc from OPERAND1 storing
38108 into OPERAND0. */
38109 void
38111 {
38112 /* C code for SSE variant we expand below.
38113 double xa = fabs (x), x2;
38114 if (!isless (xa, TWO52))
38115 return x;
38116 x2 = (double)(long)x;
38117 if (HONOR_SIGNED_ZEROS (mode))
38118 return copysign (x2, x);
38119 return x2;
38120 */
38126 /* Temporary for holding the result, initialized to the input
38127 operand to ease control flow. */
38131 /* xa = abs (operand1) */
38134 /* if (!isless (xa, TWO52)) goto label; */
38137 /* x = (double)(long)x */
38149 }
38151 /* Expand SSE sequence for computing trunc from OPERAND1 storing
38152 into OPERAND0. */
38153 void
38155 {
38159 /* C code for SSE variant we expand below.
38160 double xa = fabs (x), x2;
38161 if (!isless (xa, TWO52))
38162 return x;
38163 xa2 = xa + TWO52 - TWO52;
38164 Compensate:
38165 if (xa2 > xa)
38166 xa2 -= 1.0;
38167 x2 = copysign (xa2, x);
38168 return x2;
38169 */
38173 /* Temporary for holding the result, initialized to the input
38174 operand to ease control flow. */
38178 /* xa = abs (operand1) */
38181 /* if (!isless (xa, TWO52)) goto label; */
38184 /* res = xa + TWO52 - TWO52; */
38189 /* generate 1.0 */
38192 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
38200 /* res = copysign (res, operand1) */
38207 }
38209 /* Expand SSE sequence for computing round from OPERAND1 storing
38210 into OPERAND0. */
38211 void
38213 {
38214 /* C code for the stuff we're doing below:
38215 double xa = fabs (x);
38216 if (!isless (xa, TWO52))
38217 return x;
38218 xa = (double)(long)(xa + nextafter (0.5, 0.0));
38219 return copysign (xa, x);
38220 */
38226 /* Temporary for holding the result, initialized to the input
38227 operand to ease control flow. */
38235 /* load nextafter (0.5, 0.0) */
38240 /* xa = xa + 0.5 */
38244 /* xa = (double)(int64_t)xa */
38249 /* res = copysign (xa, operand1) */
38256 }
38258 /* Expand SSE sequence for computing round
38259 from OP1 storing into OP0 using sse4 round insn. */
38260 void
38262 {
38271 {
38282 }
38284 /* round (a) = trunc (a + copysign (0.5, a)) */
38286 /* load nextafter (0.5, 0.0) */
38292 /* e1 = copysign (0.5, op1) */
38296 /* e2 = op1 + e1 */
38299 /* res = trunc (e2) */
38304 }
38305 \f
38307 /* Table of valid machine attributes. */
38309 {
38310 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
38311 affects_type_identity } */
38312 /* Stdcall attribute says callee is responsible for popping arguments
38313 if they are not variable. */
38316 /* Fastcall attribute says callee is responsible for popping arguments
38317 if they are not variable. */
38320 /* Thiscall attribute says callee is responsible for popping arguments
38321 if they are not variable. */
38324 /* Cdecl attribute says the callee is a normal C declaration */
38327 /* Regparm attribute specifies how many integer arguments are to be
38328 passed in registers. */
38331 /* Sseregparm attribute says we are using x86_64 calling conventions
38332 for FP arguments. */
38335 /* The transactional memory builtins are implicitly regparm or fastcall
38336 depending on the ABI. Override the generic do-nothing attribute that
38337 these builtins were declared with. */
38340 /* force_align_arg_pointer says this function realigns the stack at entry. */
38343 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
38348 #endif
38353 #ifdef SUBTARGET_ATTRIBUTE_TABLE
38354 SUBTARGET_ATTRIBUTE_TABLE,
38355 #endif
38356 /* ms_abi and sysv_abi calling convention function attributes. */
38363 /* End element. */
38365 };
38367 /* Implement targetm.vectorize.builtin_vectorization_cost. */
38368 static int
38370 tree vectype,
38372 {
38376 {
38421 }
38422 }
38424 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
38425 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
38426 insn every time. */
38430 /* Initialize vselect_insn. */
38432 static void
38434 {
38436 rtx x;
38447 }
38449 /* Construct (set target (vec_select op0 (parallel perm))) and
38450 return true if that's a valid instruction in the active ISA. */
38452 static bool
38455 {
38481 }
38483 /* Similar, but generate a vec_concat from op0 and op1 as well. */
38485 static bool
38489 {
38491 rtx x;
38506 }
38508 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38509 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
38511 static bool
38513 {
38522 ;
38524 ;
38526 ;
38527 else
38530 /* This is a blend, not a permute. Elements must stay in their
38531 respective lanes. */
38533 {
38537 }
38542 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
38543 decision should be extracted elsewhere, so that we only try that
38544 sequence once all budget==3 options have been tried. */
38551 {
38575 /* See if bytes move in pairs so we can use pblendw with
38576 an immediate argument, rather than pblendvb with a vector
38577 argument. */
38580 {
38581 use_pblendvb:
38585 finish_pblendvb:
38591 else
38594 }
38599 /* FALLTHRU */
38601 do_subreg:
38608 /* See if bytes move in pairs. If not, vpblendvb must be used. */
38612 /* See if bytes move in quadruplets. If yes, vpblendd
38613 with immediate can be used. */
38618 {
38619 /* See if bytes move the same in both lanes. If yes,
38620 vpblendw with immediate can be used. */
38625 /* Use vpblendw. */
38630 }
38632 /* Use vpblendd. */
38639 /* See if words move in pairs. If yes, vpblendd can be used. */
38644 {
38645 /* See if words move the same in both lanes. If not,
38646 vpblendvb must be used. */
38649 {
38650 /* Use vpblendvb. */
38660 }
38662 /* Use vpblendw. */
38666 }
38668 /* Use vpblendd. */
38675 /* Use vpblendd. */
38683 }
38685 /* This matches five different patterns with the different modes. */
38691 }
38693 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38694 in terms of the variable form of vpermilps.
38696 Note that we will have already failed the immediate input vpermilps,
38697 which requires that the high and low part shuffle be identical; the
38698 variable form doesn't require that. */
38700 static bool
38702 {
38709 /* We can only permute within the 128-bit lane. */
38711 {
38715 }
38721 {
38724 /* Within each 128-bit lane, the elements of op0 are numbered
38725 from 0 and the elements of op1 are numbered from 4. */
38732 }
38739 }
38741 /* Return true if permutation D can be performed as VMODE permutation
38742 instead. */
38744 static bool
38746 {
38761 else
38767 }
38769 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
38770 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
38772 static bool
38774 {
38783 {
38785 {
38788 {
38792 /* Use vperm2i128 insn. The pattern uses
38793 V4DImode instead of V2TImode. */
38802 }
38804 }
38805 }
38806 else
38807 {
38809 {
38812 }
38814 {
38818 /* V4DImode should be already handled through
38819 expand_vselect by vpermq instruction. */
38826 {
38827 /* First see if vpermq can be used for
38828 V8SImode/V16HImode/V32QImode. */
38830 {
38838 }
38840 /* Next see if vpermd can be used. */
38843 }
38844 /* Or if vpermps can be used. */
38849 {
38850 /* vpshufb only works intra lanes, it is not
38851 possible to shuffle bytes in between the lanes. */
38855 }
38856 }
38857 else
38859 }
38867 else
38868 {
38874 else
38878 {
38882 }
38883 }
38892 {
38899 else
38901 }
38902 else
38903 {
38906 }
38909 }
38911 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
38912 in a single instruction. */
38914 static bool
38916 {
38920 /* Check plain VEC_SELECT first, because AVX has instructions that could
38921 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
38922 input where SEL+CONCAT may not. */
38924 {
38930 {
38936 }
38939 {
38943 }
38945 {
38946 /* Use vpbroadcast{b,w,d}. */
38949 {
38968 /* For other modes prefer other shuffles this function creates. */
38970 }
38972 {
38976 }
38977 }
38982 /* There are plenty of patterns in sse.md that are written for
38983 SEL+CONCAT and are not replicated for a single op. Perhaps
38984 that should be changed, to avoid the nastiness here. */
38986 /* Recognize interleave style patterns, which means incrementing
38987 every other permutation operand. */
38989 {
38992 }
38997 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
38999 {
39001 {
39006 }
39011 }
39012 }
39014 /* Finally, try the fully general two operand permute. */
39019 /* Recognize interleave style patterns with reversed operands. */
39021 {
39023 {
39027 else
39030 }
39035 }
39037 /* Try the SSE4.1 blend variable merge instructions. */
39041 /* Try one of the AVX vpermil variable permutations. */
39045 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
39046 vpshufb, vpermd, vpermps or vpermq variable permutation. */
39051 }
39053 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
39054 in terms of a pair of pshuflw + pshufhw instructions. */
39056 static bool
39058 {
39066 /* The two permutations only operate in 64-bit lanes. */
39077 /* Emit the pshuflw. */
39084 /* Emit the pshufhw. */
39092 }
39094 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39095 the permutation using the SSSE3 palignr instruction. This succeeds
39096 when all of the elements in PERM fit within one vector and we merely
39097 need to shift them down so that a single vector permutation has a
39098 chance to succeed. */
39100 static bool
39102 {
39106 rtx shift;
39108 /* Even with AVX, palignr only operates on 128-bit vectors. */
39114 {
39120 }
39124 /* Given that we have SSSE3, we know we'll be able to implement the
39125 single operand permutation after the palignr with pshufb. */
39139 {
39144 }
39146 /* Test for the degenerate case where the alignment by itself
39147 produces the desired permutation. */
39155 }
39159 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39160 a two vector permutation into a single vector permutation by using
39161 an interleave operation to merge the vectors. */
39163 static bool
39165 {
39170 rtx seq;
39174 {
39177 }
39179 {
39182 /* For 32-byte modes allow even d->one_operand_p.
39183 The lack of cross-lane shuffling in some instructions
39184 might prevent a single insn shuffle. */
39187 /* If expand_vec_perm_interleave3 can expand this into
39188 a 3 insn sequence, give up and let it be expanded as
39189 3 insn sequence. While that is one insn longer,
39190 it doesn't need a memory operand and in the common
39191 case that both interleave low and high permutations
39192 with the same operands are adjacent needs 4 insns
39193 for both after CSE. */
39196 }
39197 else
39200 /* Examine from whence the elements come. */
39209 {
39212 /* Split the two input vectors into 4 halves. */
39218 /* If the elements from the low halves use interleave low, and similarly
39219 for interleave high. If the elements are from mis-matched halves, we
39220 can use shufps for V4SF/V4SI or do a DImode shuffle. */
39222 {
39223 /* punpckl* */
39225 {
39230 }
39233 }
39235 {
39236 /* punpckh* */
39238 {
39243 }
39246 }
39248 {
39249 /* shufps */
39251 {
39256 }
39258 {
39259 /* shufpd */
39264 }
39265 }
39267 {
39268 /* shufps */
39270 {
39275 }
39277 {
39278 /* shufpd */
39283 }
39284 }
39285 else
39287 }
39288 else
39289 {
39294 /* Split the two input vectors into 8 quarters. */
39300 {
39303 }
39306 {
39310 }
39312 {
39315 }
39318 {
39320 {
39321 /* Attempt to increase the likelihood that dfinal
39322 shuffle will be intra-lane. */
39326 }
39328 /* vperm2f128 or vperm2i128. */
39330 {
39335 }
39340 {
39344 {
39347 }
39348 }
39349 }
39354 {
39355 /* vpunpckl* */
39357 {
39366 }
39367 }
39370 {
39371 /* vpunpckh* */
39373 {
39382 }
39383 }
39384 else
39386 }
39388 /* Use the remapping array set up above to move the elements from their
39389 swizzled locations into their final destinations. */
39392 {
39395 /* If same_halves is true, both halves of the remapped vector are the
39396 same. Avoid cross-lane accesses if possible. */
39398 {
39401 }
39402 else
39404 }
39410 /* Test if the final remap can be done with a single insn. For V4SFmode or
39411 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
39424 {
39428 }
39435 }
39437 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39438 a single vector cross-lane permutation into vpermq followed
39439 by any of the single insn permutations. */
39441 static bool
39443 {
39457 {
39460 }
39463 {
39468 }
39481 {
39488 }
39495 {
39500 ;
39503 else
39505 }
39514 }
39516 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
39517 a vector permutation using two instructions, vperm2f128 resp.
39518 vperm2i128 followed by any single in-lane permutation. */
39520 static bool
39522 {
39536 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
39537 immediate. For perm < 16 the second permutation uses
39538 d->op0 as first operand, for perm >= 16 it uses d->op1
39539 as first operand. The second operand is the result of
39540 vperm2[fi]128. */
39542 {
39543 /* Ignore permutations which do not move anything cross-lane. */
39545 {
39546 /* The second shuffle for e.g. V4DFmode has
39547 0123 and ABCD operands.
39548 Ignore AB23, as 23 is already in the second lane
39549 of the first operand. */
39551 /* And 01CD, as 01 is in the first lane of the first
39552 operand. */
39554 /* And 4567, as then the vperm2[fi]128 doesn't change
39555 anything on the original 4567 second operand. */
39557 }
39558 else
39559 {
39560 /* The second shuffle for e.g. V4DFmode has
39561 4567 and ABCD operands.
39562 Ignore AB67, as 67 is already in the second lane
39563 of the first operand. */
39565 /* And 45CD, as 45 is in the first lane of the first
39566 operand. */
39568 /* And 0123, as then the vperm2[fi]128 doesn't change
39569 anything on the original 0123 first operand. */
39571 }
39574 {
39580 else
39582 }
39585 {
39589 }
39590 else
39594 {
39598 /* Found a usable second shuffle. dfirst will be
39599 vperm2f128 on d->op0 and d->op1. */
39610 /* And dsecond is some single insn shuffle, taking
39611 d->op0 and result of vperm2f128 (if perm < 16) or
39612 d->op1 and result of vperm2f128 (otherwise). */
39621 }
39623 /* For one operand, the only useful vperm2f128 permutation is 0x10. */
39626 }
39629 }
39631 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
39632 a two vector permutation using 2 intra-lane interleave insns
39633 and cross-lane shuffle for 32-byte vectors. */
39635 static bool
39637 {
39644 ;
39646 ;
39647 else
39662 {
39666 else
39672 else
39678 else
39684 else
39690 else
39696 else
39701 }
39705 }
39707 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
39708 a single vector permutation using a single intra-lane vector
39709 permutation, vperm2f128 swapping the lanes and vblend* insn blending
39710 the non-swapped and swapped vectors together. */
39712 static bool
39714 {
39717 rtx seq;
39722 || TARGET_AVX2
39731 {
39738 }
39773 }
39775 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
39776 permutation using two vperm2f128, followed by a vshufpd insn blending
39777 the two vectors together. */
39779 static bool
39781 {
39824 }
39826 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
39827 permutation with two pshufb insns and an ior. We should have already
39828 failed all two instruction sequences. */
39830 static bool
39832 {
39843 /* Generate two permutation masks. If the required element is within
39844 the given vector it is shuffled into the proper lane. If the required
39845 element is in the other vector, force a zero into the lane by setting
39846 bit 7 in the permutation mask. */
39849 {
39856 {
39859 }
39860 }
39880 }
39882 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
39883 with two vpshufb insns, vpermq and vpor. We should have already failed
39884 all two or three instruction sequences. */
39886 static bool
39888 {
39903 /* Generate two permutation masks. If the required element is within
39904 the same lane, it is shuffled in. If the required element from the
39905 other lane, force a zero by setting bit 7 in the permutation mask.
39906 In the other mask the mask has non-negative elements if element
39907 is requested from the other lane, but also moved to the other lane,
39908 so that the result of vpshufb can have the two V2TImode halves
39909 swapped. */
39912 {
39917 {
39920 }
39921 }
39930 /* Swap the 128-byte lanes of h into hp. */
39934 const1_rtx));
39947 }
39949 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
39950 and extract-odd permutations of two V32QImode and V16QImode operand
39951 with two vpshufb insns, vpor and vpermq. We should have already
39952 failed all two or three instruction sequences. */
39954 static bool
39956 {
39975 /* Generate two permutation masks. In the first permutation mask
39976 the first quarter will contain indexes for the first half
39977 of the op0, the second quarter will contain bit 7 set, third quarter
39978 will contain indexes for the second half of the op0 and the
39979 last quarter bit 7 set. In the second permutation mask
39980 the first quarter will contain bit 7 set, the second quarter
39981 indexes for the first half of the op1, the third quarter bit 7 set
39982 and last quarter indexes for the second half of the op1.
39983 I.e. the first mask e.g. for V32QImode extract even will be:
39984 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
39985 (all values masked with 0xf except for -128) and second mask
39986 for extract even will be
39987 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
39990 {
39996 {
39999 }
40000 }
40019 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
40026 }
40028 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
40029 and extract-odd permutations. */
40031 static bool
40033 {
40037 {
40042 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
40046 /* Now an unpck[lh]pd will produce the result required. */
40049 else
40055 {
40062 /* Shuffle within the 128-bit lanes to produce:
40063 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
40067 /* Shuffle the lanes around to produce:
40068 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
40072 /* Shuffle within the 128-bit lanes to produce:
40073 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
40076 /* Shuffle within the 128-bit lanes to produce:
40077 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
40080 /* Shuffle the lanes around to produce:
40081 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
40084 }
40091 /* These are always directly implementable by expand_vec_perm_1. */
40097 else
40098 {
40099 /* We need 2*log2(N)-1 operations to achieve odd/even
40100 with interleave. */
40109 else
40112 }
40118 else
40119 {
40131 else
40134 }
40143 {
40150 }
40155 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
40159 /* Now an vpunpck[lh]qdq will produce the result required. */
40162 else
40169 {
40176 }
40181 /* Shuffle the lanes around into
40182 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
40192 /* Swap the 2nd and 3rd position in each lane into
40193 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
40199 /* Now an vpunpck[lh]qdq will produce
40200 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
40205 else
40214 }
40217 }
40219 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
40220 extract-even and extract-odd permutations. */
40222 static bool
40224 {
40236 }
40238 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
40239 permutations. We assume that expand_vec_perm_1 has already failed. */
40241 static bool
40243 {
40251 {
40254 /* These are special-cased in sse.md so that we can optionally
40255 use the vbroadcast instruction. They expand to two insns
40256 if the input happens to be in a register. */
40263 /* These are always implementable using standard shuffle patterns. */
40268 /* These can be implemented via interleave. We save one insn by
40269 stopping once we have promoted to V4SImode and then use pshufd. */
40270 do
40271 {
40272 rtx dest;
40278 {
40282 }
40289 }
40302 /* For AVX2 broadcasts of the first element vpbroadcast* or
40303 vpermq should be used by expand_vec_perm_1. */
40309 }
40310 }
40312 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
40313 broadcast permutations. */
40315 static bool
40317 {
40329 }
40331 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
40332 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
40333 all the shorter instruction sequences. */
40335 static bool
40337 {
40353 /* Generate 4 permutation masks. If the required element is within
40354 the same lane, it is shuffled in. If the required element from the
40355 other lane, force a zero by setting bit 7 in the permutation mask.
40356 In the other mask the mask has non-negative elements if element
40357 is requested from the other lane, but also moved to the other lane,
40358 so that the result of vpshufb can have the two V2TImode halves
40359 swapped. */
40362 {
40367 }
40373 {
40381 }
40384 {
40386 {
40389 }
40396 }
40398 /* Swap the 128-byte lanes of h[X]. */
40400 {
40406 const1_rtx));
40408 }
40411 {
40413 {
40416 }
40422 }
40425 {
40427 {
40431 }
40434 }
40440 }
40442 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
40443 With all of the interface bits taken care of, perform the expansion
40444 in D and return true on success. */
40446 static bool
40448 {
40449 /* Try a single instruction expansion. */
40453 /* Try sequences of two instructions. */
40473 /* Try sequences of three instructions. */
40487 /* Try sequences of four instructions. */
40495 /* ??? Look for narrow permutations whose element orderings would
40496 allow the promotion to a wider mode. */
40498 /* ??? Look for sequences of interleave or a wider permute that place
40499 the data into the correct lanes for a half-vector shuffle like
40500 pshuf[lh]w or vpermilps. */
40502 /* ??? Look for sequences of interleave that produce the desired results.
40503 The combinatorics of punpck[lh] get pretty ugly... */
40508 /* Even longer sequences. */
40513 }
40515 /* If a permutation only uses one operand, make it clear. Returns true
40516 if the permutation references both operands. */
40518 static bool
40520 {
40528 {
40534 {
40537 }
40538 /* The elements of PERM do not suggest that only the first operand
40539 is used, but both operands are identical. Allow easier matching
40540 of the permutation by folding the permutation into the single
40541 input vector. */
40542 /* FALLTHRU */
40553 }
40556 }
40558 bool
40560 {
40565 rtx sel;
40582 {
40587 }
40594 /* If the selector says both arguments are needed, but the operands are the
40595 same, the above tried to expand with one_operand_p and flattened selector.
40596 If that didn't work, retry without one_operand_p; we succeeded with that
40597 during testing. */
40599 {
40603 }
40606 }
40608 /* Implement targetm.vectorize.vec_perm_const_ok. */
40610 static bool
40613 {
40622 /* Given sufficient ISA support we can just return true here
40623 for selected vector modes. */
40625 {
40626 /* All implementable with a single vpperm insn. */
40629 /* All implementable with 2 pshufb + 1 ior. */
40632 /* All implementable with shufpd or unpck[lh]pd. */
40635 }
40637 /* Extract the values from the vector CST into the permutation
40638 array in D. */
40641 {
40645 }
40647 /* For all elements from second vector, fold the elements to first. */
40652 /* Check whether the mask can be applied to the vector type. */
40655 /* Implementable with shufps or pshufd. */
40659 /* Otherwise we have to go through the motions and see if we can
40660 figure out how to generate the requested permutation. */
40671 }
40673 void
40675 {
40690 /* We'll either be able to implement the permutation directly... */
40694 /* ... or we use the special-case patterns. */
40696 }
40698 static void
40700 {
40715 {
40718 }
40720 /* Note that for AVX this isn't one instruction. */
40723 }
40726 /* Expand a vector operation CODE for a V*QImode in terms of the
40727 same operation on V*HImode. */
40729 void
40731 {
40743 {
40756 }
40760 {
40762 /* Unpack data such that we've got a source byte in each low byte of
40763 each word. We don't care what goes into the high byte of each word.
40764 Rather than trying to get zero in there, most convenient is to let
40765 it be a copy of the low byte. */
40770 /* FALLTHRU */
40782 /* FALLTHRU */
40792 }
40794 /* Perform the operation. */
40801 /* Merge the data back into the right place. */
40811 {
40812 /* For SSE2, we used an full interleave, so the desired
40813 results are in the even elements. */
40816 }
40817 else
40818 {
40819 /* For AVX, the interleave used above was not cross-lane. So the
40820 extraction is evens but with the second and third quarter swapped.
40821 Happily, that is even one insn shorter than even extraction. */
40824 }
40831 }
40833 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
40834 if op is CONST_VECTOR with all odd elements equal to their
40835 preceeding element. */
40837 static bool
40839 {
40849 }
40851 void
40854 {
40857 rtx x;
40865 /* We only play even/odd games with vectors of SImode. */
40868 /* If we're looking for the odd results, shift those members down to
40869 the even slots. For some cpus this is faster than a PSHUFD. */
40871 {
40872 /* For XOP use vpmacsdqh, but only for smult, as it is only
40873 signed. */
40875 {
40879 }
40890 }
40893 {
40896 else
40898 }
40903 else
40904 {
40907 /* The easiest way to implement this without PMULDQ is to go through
40908 the motions as if we are performing a full 64-bit multiply. With
40909 the exception that we need to do less shuffling of the elements. */
40911 /* Compute the sign-extension, aka highparts, of the two operands. */
40917 /* Multiply LO(A) * HI(B), and vice-versa. */
40923 /* Multiply LO(A) * LO(B). */
40927 /* Combine and shift the highparts into place. */
40932 /* Combine high and low parts. */
40935 }
40937 }
40939 void
40942 {
40948 {
40953 {
40954 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
40955 shuffle the elements once so that all elements are in the right
40956 place for immediate use: { A C B D }. */
40961 }
40962 else
40963 {
40964 /* Put the elements into place for the multiply. */
40968 }
40973 /* Shuffle the elements between the lanes. After this we
40974 have { A B E F | C D G H } for each operand. */
40984 /* Shuffle the elements within the lanes. After this we
40985 have { A A B B | C C D D } or { E E F F | G G H H }. */
41021 }
41022 }
41024 void
41026 {
41036 /* Move the results in element 2 down to element 1; we don't care
41037 what goes in elements 2 and 3. Then we can merge the parts
41038 back together with an interleave.
41040 Note that two other sequences were tried:
41041 (1) Use interleaves at the start instead of psrldq, which allows
41042 us to use a single shufps to merge things back at the end.
41043 (2) Use shufps here to combine the two vectors, then pshufd to
41044 put the elements in the correct order.
41045 In both cases the cost of the reformatting stall was too high
41046 and the overall sequence slower. */
41055 }
41057 void
41059 {
41064 {
41065 /* op1: A,B,C,D, op2: E,F,G,H */
41074 /* t1: B,A,D,C */
41081 /* t2: (B*E),(A*F),(D*G),(C*H) */
41084 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
41087 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
41090 /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */
41092 }
41093 else
41094 {
41099 {
41102 }
41104 {
41107 }
41108 else
41112 /* Multiply low parts. */
41116 /* Shift input vectors right 32 bits so we can multiply high parts. */
41121 /* Multiply high parts by low parts. */
41127 /* Combine and shift the highparts back. */
41131 /* Combine high and low parts. */
41133 }
41137 }
41139 /* Expand an insert into a vector register through pinsr insn.
41140 Return true if successful. */
41142 bool
41144 {
41152 {
41155 }
41161 {
41166 {
41173 {
41205 }
41214 }
41218 }
41219 }
41220 \f
41221 /* This function returns the calling abi specific va_list type node.
41222 It returns the FNDECL specific va_list type. */
41224 static tree
41226 {
41233 else
41235 }
41237 /* Returns the canonical va_list type specified by TYPE. If there
41238 is no valid TYPE provided, it return NULL_TREE. */
41240 static tree
41242 {
41245 /* Resolve references and pointers to va_list type. */
41254 {
41259 {
41260 /* If va_list is an array type, the argument may have decayed
41261 to a pointer type, e.g. by being passed to another function.
41262 In that case, unwrap both types so that we can compare the
41263 underlying records. */
41266 {
41269 }
41270 }
41277 {
41278 /* If va_list is an array type, the argument may have decayed
41279 to a pointer type, e.g. by being passed to another function.
41280 In that case, unwrap both types so that we can compare the
41281 underlying records. */
41284 {
41287 }
41288 }
41295 {
41296 /* If va_list is an array type, the argument may have decayed
41297 to a pointer type, e.g. by being passed to another function.
41298 In that case, unwrap both types so that we can compare the
41299 underlying records. */
41302 {
41305 }
41306 }
41310 }
41312 }
41314 /* Iterate through the target-specific builtin types for va_list.
41315 IDX denotes the iterator, *PTREE is set to the result type of
41316 the va_list builtin, and *PNAME to its internal type.
41317 Returns zero if there is no element for this index, otherwise
41318 IDX should be increased upon the next call.
41319 Note, do not iterate a base builtin's name like __builtin_va_list.
41320 Used from c_common_nodes_and_builtins. */
41322 static int
41324 {
41326 {
41328 {
41341 }
41342 }
41345 }
41347 #undef TARGET_SCHED_DISPATCH
41348 #define TARGET_SCHED_DISPATCH has_dispatch
41349 #undef TARGET_SCHED_DISPATCH_DO
41350 #define TARGET_SCHED_DISPATCH_DO do_dispatch
41351 #undef TARGET_SCHED_REASSOCIATION_WIDTH
41352 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
41353 #undef TARGET_SCHED_REORDER
41354 #define TARGET_SCHED_REORDER ix86_sched_reorder
41355 #undef TARGET_SCHED_ADJUST_PRIORITY
41356 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
41357 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
41358 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK ix86_dependencies_evaluation_hook
41360 /* The size of the dispatch window is the total number of bytes of
41361 object code allowed in a window. */
41362 #define DISPATCH_WINDOW_SIZE 16
41364 /* Number of dispatch windows considered for scheduling. */
41365 #define MAX_DISPATCH_WINDOWS 3
41367 /* Maximum number of instructions in a window. */
41368 #define MAX_INSN 4
41370 /* Maximum number of immediate operands in a window. */
41371 #define MAX_IMM 4
41373 /* Maximum number of immediate bits allowed in a window. */
41374 #define MAX_IMM_SIZE 128
41376 /* Maximum number of 32 bit immediates allowed in a window. */
41377 #define MAX_IMM_32 4
41379 /* Maximum number of 64 bit immediates allowed in a window. */
41380 #define MAX_IMM_64 2
41382 /* Maximum total of loads or prefetches allowed in a window. */
41383 #define MAX_LOAD 2
41385 /* Maximum total of stores allowed in a window. */
41386 #define MAX_STORE 1
41388 #undef BIG
41389 #define BIG 100
41392 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
41395 disp_load,
41396 disp_store,
41397 disp_load_store,
41398 disp_prefetch,
41399 disp_imm,
41400 disp_imm_32,
41401 disp_imm_64,
41402 disp_branch,
41403 disp_cmp,
41404 disp_jcc,
41405 disp_last
41406 };
41408 /* Number of allowable groups in a dispatch window. It is an array
41409 indexed by dispatch_group enum. 100 is used as a big number,
41410 because the number of these kind of operations does not have any
41411 effect in dispatch window, but we need them for other reasons in
41412 the table. */
41415 };
41421 };
41423 /* Instruction path. */
41429 last_path
41430 };
41432 /* sched_insn_info defines a window to the instructions scheduled in
41433 the basic block. It contains a pointer to the insn_info table and
41434 the instruction scheduled.
41436 Windows are allocated for each basic block and are linked
41437 together. */
41439 rtx insn;
41446 /* Linked list of dispatch windows. This is a two way list of
41447 dispatch windows of a basic block. It contains information about
41448 the number of uops in the window and the total number of
41449 instructions and of bytes in the object code for this dispatch
41450 window. */
41468 /* Immediate valuse used in an insn. */
41470 {
41479 /* Get dispatch group of insn. */
41481 static enum dispatch_group
41483 {
41499 }
41501 /* Return true if insn is a compare instruction. */
41503 static bool
41505 {
41513 }
41515 /* Return true if a dispatch violation encountered. */
41517 static bool
41519 {
41523 }
41525 /* Return true if insn is a branch instruction. */
41527 static bool
41529 {
41531 }
41533 /* Return true if insn is a prefetch instruction. */
41535 static bool
41537 {
41539 }
41541 /* This function initializes a dispatch window and the list container holding a
41542 pointer to the window. */
41544 static void
41546 {
41552 else
41570 {
41576 }
41578 }
41580 /* This function allocates and initializes a dispatch window and the
41581 list container holding a pointer to the window. */
41585 {
41590 }
41592 /* This routine initializes the dispatch scheduling information. It
41593 initiates building dispatch scheduler tables and constructs the
41594 first dispatch window. */
41596 static void
41598 {
41599 /* Allocate a dispatch list and a window. */
41604 }
41606 /* This function returns true if a branch is detected. End of a basic block
41607 does not have to be a branch, but here we assume only branches end a
41608 window. */
41610 static bool
41612 {
41614 }
41616 /* This function is called when the end of a window processing is reached. */
41618 static void
41620 {
41623 {
41628 }
41630 }
41632 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
41633 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
41634 for 48 bytes of instructions. Note that these windows are not dispatch
41635 windows that their sizes are DISPATCH_WINDOW_SIZE. */
41639 {
41641 {
41646 }
41652 }
41654 /* Increment the number of immediate operands of an instruction. */
41656 static int
41658 {
41663 {
41670 else
41681 {
41684 }
41689 }
41692 }
41694 /* Compute number of immediate operands of an instruction. */
41696 static void
41698 {
41701 }
41703 /* Return total size of immediate operands of an instruction along with number
41704 of corresponding immediate-operands. It initializes its parameters to zero
41705 befor calling FIND_CONSTANT.
41706 INSN is the input instruction. IMM is the total of immediates.
41707 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
41708 bit immediates. */
41710 static int
41712 {
41720 }
41722 /* This function indicates if an operand of an instruction is an
41723 immediate. */
41725 static bool
41727 {
41736 }
41738 /* Return single or double path for instructions. */
41740 static enum insn_path
41742 {
41752 }
41754 /* Return insn dispatch group. */
41756 static enum dispatch_group
41758 {
41776 }
41778 /* Count number of GROUP restricted instructions in a dispatch
41779 window WINDOW_LIST. */
41781 static int
41783 {
41794 {
41813 }
41826 }
41828 /* This function returns true if insn satisfies dispatch rules on the
41829 last window scheduled. */
41831 static bool
41833 {
41841 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
41842 instructions should be given the lowest priority in the
41843 scheduling process in Haifa scheduler to make sure they will be
41844 scheduled in the same dispatch window as the reference to them. */
41848 /* Check nonrestricted. */
41852 /* Get last dispatch window. */
41857 {
41862 /* Window 1 is full. Go for next window. */
41864 }
41871 /* See if it fits in the first window. */
41873 {
41874 /* The first widow should have only single and double path
41875 uops. */
41881 }
41883 }
41885 /* Add an instruction INSN with NUM_UOPS micro-operations to the
41886 dispatch window WINDOW_LIST. */
41888 static void
41890 {
41908 /* Initialize window with new instruction. */
41929 {
41932 }
41933 }
41935 /* Adds a scheduled instruction, INSN, to the current dispatch window.
41936 If the total bytes of instructions or the number of instructions in
41937 the window exceed allowable, it allocates a new window. */
41939 static void
41941 {
41964 /* Get the last dispatch window. */
41972 else
41975 /* If current window is full, get a new window.
41976 Window number zero is full, if MAX_INSN uops are scheduled in it.
41977 Window number one is full, if window zero's bytes plus window
41978 one's bytes is 32, or if the bytes of the new instruction added
41979 to the total makes it greater than 48, or it has already MAX_INSN
41980 instructions in it. */
41989 {
41992 }
41995 {
41999 {
42002 }
42003 }
42005 {
42010 {
42013 }
42016 }
42017 else
42021 {
42022 /* End of basic block is reached do end-basic-block process. */
42025 }
42026 }
42028 /* Print the dispatch window, WINDOW_NUM, to FILE. */
42030 DEBUG_FUNCTION static void
42032 {
42038 else
42052 {
42055 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
42061 }
42062 }
42064 /* Print to stdout a dispatch window. */
42066 DEBUG_FUNCTION void
42068 {
42070 }
42072 /* Print INSN dispatch information to FILE. */
42074 DEBUG_FUNCTION static void
42076 {
42099 }
42101 /* Print to STDERR the status of the ready list with respect to
42102 dispatch windows. */
42104 DEBUG_FUNCTION void
42106 {
42114 }
42116 /* This routine is the driver of the dispatch scheduler. */
42118 static void
42120 {
42125 }
42127 /* Return TRUE if Dispatch Scheduling is supported. */
42129 static bool
42131 {
42135 {
42151 }
42154 }
42156 /* Implementation of reassociation_width target hook used by
42157 reassoc phase to identify parallelism level in reassociated
42158 tree. Statements tree_code is passed in OPC. Arguments type
42159 is passed in MODE.
42161 Currently parallel reassociation is enabled for Atom
42162 processors only and we set reassociation width to be 2
42163 because Atom may issue up to 2 instructions per cycle.
42165 Return value should be fixed if parallel reassociation is
42166 enabled for other processors. */
42168 static int
42171 {
42180 }
42182 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
42183 place emms and femms instructions. */
42185 static enum machine_mode
42187 {
42192 {
42205 else
42215 /* FALLTHRU */
42219 }
42220 }
42222 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
42223 vectors. */
42225 static unsigned int
42227 {
42229 }
42231 \f
42233 /* Return class of registers which could be used for pseudo of MODE
42234 and of class RCLASS for spilling instead of memory. Return NO_REGS
42235 if it is not possible or non-profitable. */
42236 static reg_class_t
42238 {
42244 }
42246 /* Implement targetm.vectorize.init_cost. */
42250 {
42254 }
42256 /* Implement targetm.vectorize.add_stmt_cost. */
42258 static unsigned
42262 {
42267 {
42271 /* Statements in an inner loop relative to the loop being
42272 vectorized are weighted more heavily. The value here is
42273 arbitrary and could potentially be improved with analysis. */
42279 }
42282 }
42284 /* Implement targetm.vectorize.finish_cost. */
42286 static void
42289 {
42294 }
42296 /* Implement targetm.vectorize.destroy_cost_data. */
42298 static void
42300 {
42302 }
42304 /* Validate target specific memory model bits in VAL. */
42306 static unsigned HOST_WIDE_INT
42308 {
42315 {
42319 }
42322 {
42326 }
42328 {
42332 }
42334 }
42336 /* Initialize the GCC target structure. */
42337 #undef TARGET_RETURN_IN_MEMORY
42338 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
42340 #undef TARGET_LEGITIMIZE_ADDRESS
42341 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
42343 #undef TARGET_ATTRIBUTE_TABLE
42344 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
42345 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42346 # undef TARGET_MERGE_DECL_ATTRIBUTES
42347 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
42348 #endif
42350 #undef TARGET_COMP_TYPE_ATTRIBUTES
42351 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
42353 #undef TARGET_INIT_BUILTINS
42354 #define TARGET_INIT_BUILTINS ix86_init_builtins
42355 #undef TARGET_BUILTIN_DECL
42356 #define TARGET_BUILTIN_DECL ix86_builtin_decl
42357 #undef TARGET_EXPAND_BUILTIN
42358 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
42360 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
42361 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
42362 ix86_builtin_vectorized_function
42364 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
42365 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
42367 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
42368 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
42370 #undef TARGET_VECTORIZE_BUILTIN_GATHER
42371 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
42373 #undef TARGET_BUILTIN_RECIPROCAL
42374 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
42376 #undef TARGET_ASM_FUNCTION_EPILOGUE
42377 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
42379 #undef TARGET_ENCODE_SECTION_INFO
42380 #ifndef SUBTARGET_ENCODE_SECTION_INFO
42381 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
42382 #else
42383 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
42384 #endif
42386 #undef TARGET_ASM_OPEN_PAREN
42388 #undef TARGET_ASM_CLOSE_PAREN
42391 #undef TARGET_ASM_BYTE_OP
42392 #define TARGET_ASM_BYTE_OP ASM_BYTE
42394 #undef TARGET_ASM_ALIGNED_HI_OP
42395 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
42396 #undef TARGET_ASM_ALIGNED_SI_OP
42397 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
42398 #ifdef ASM_QUAD
42399 #undef TARGET_ASM_ALIGNED_DI_OP
42400 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
42401 #endif
42403 #undef TARGET_PROFILE_BEFORE_PROLOGUE
42404 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
42406 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
42407 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
42409 #undef TARGET_ASM_UNALIGNED_HI_OP
42410 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
42411 #undef TARGET_ASM_UNALIGNED_SI_OP
42412 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
42413 #undef TARGET_ASM_UNALIGNED_DI_OP
42414 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
42416 #undef TARGET_PRINT_OPERAND
42417 #define TARGET_PRINT_OPERAND ix86_print_operand
42418 #undef TARGET_PRINT_OPERAND_ADDRESS
42419 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
42420 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
42421 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
42422 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
42423 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
42425 #undef TARGET_SCHED_INIT_GLOBAL
42426 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
42427 #undef TARGET_SCHED_ADJUST_COST
42428 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
42429 #undef TARGET_SCHED_ISSUE_RATE
42430 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
42431 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
42432 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
42433 ia32_multipass_dfa_lookahead
42435 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
42436 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
42438 #undef TARGET_MEMMODEL_CHECK
42439 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
42441 #ifdef HAVE_AS_TLS
42442 #undef TARGET_HAVE_TLS
42443 #define TARGET_HAVE_TLS true
42444 #endif
42445 #undef TARGET_CANNOT_FORCE_CONST_MEM
42446 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
42447 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
42448 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
42450 #undef TARGET_DELEGITIMIZE_ADDRESS
42451 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
42453 #undef TARGET_MS_BITFIELD_LAYOUT_P
42454 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
42456 #if TARGET_MACHO
42457 #undef TARGET_BINDS_LOCAL_P
42458 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
42459 #endif
42460 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
42461 #undef TARGET_BINDS_LOCAL_P
42462 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
42463 #endif
42465 #undef TARGET_ASM_OUTPUT_MI_THUNK
42466 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
42467 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
42468 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
42470 #undef TARGET_ASM_FILE_START
42471 #define TARGET_ASM_FILE_START x86_file_start
42473 #undef TARGET_OPTION_OVERRIDE
42474 #define TARGET_OPTION_OVERRIDE ix86_option_override
42476 #undef TARGET_REGISTER_MOVE_COST
42477 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
42478 #undef TARGET_MEMORY_MOVE_COST
42479 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
42480 #undef TARGET_RTX_COSTS
42481 #define TARGET_RTX_COSTS ix86_rtx_costs
42482 #undef TARGET_ADDRESS_COST
42483 #define TARGET_ADDRESS_COST ix86_address_cost
42485 #undef TARGET_FIXED_CONDITION_CODE_REGS
42486 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
42487 #undef TARGET_CC_MODES_COMPATIBLE
42488 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
42490 #undef TARGET_MACHINE_DEPENDENT_REORG
42491 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
42493 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
42494 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
42496 #undef TARGET_BUILD_BUILTIN_VA_LIST
42497 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
42499 #undef TARGET_FOLD_BUILTIN
42500 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
42502 #undef TARGET_COMPARE_VERSION_PRIORITY
42503 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
42505 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
42506 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
42507 ix86_generate_version_dispatcher_body
42509 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
42510 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
42511 ix86_get_function_versions_dispatcher
42513 #undef TARGET_ENUM_VA_LIST_P
42514 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
42516 #undef TARGET_FN_ABI_VA_LIST
42517 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
42519 #undef TARGET_CANONICAL_VA_LIST_TYPE
42520 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
42522 #undef TARGET_EXPAND_BUILTIN_VA_START
42523 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
42525 #undef TARGET_MD_ASM_CLOBBERS
42526 #define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers
42528 #undef TARGET_PROMOTE_PROTOTYPES
42529 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
42530 #undef TARGET_STRUCT_VALUE_RTX
42531 #define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx
42532 #undef TARGET_SETUP_INCOMING_VARARGS
42533 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
42534 #undef TARGET_MUST_PASS_IN_STACK
42535 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
42536 #undef TARGET_FUNCTION_ARG_ADVANCE
42537 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
42538 #undef TARGET_FUNCTION_ARG
42539 #define TARGET_FUNCTION_ARG ix86_function_arg
42540 #undef TARGET_FUNCTION_ARG_BOUNDARY
42541 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
42542 #undef TARGET_PASS_BY_REFERENCE
42543 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
42544 #undef TARGET_INTERNAL_ARG_POINTER
42545 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
42546 #undef TARGET_UPDATE_STACK_BOUNDARY
42547 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
42548 #undef TARGET_GET_DRAP_RTX
42549 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
42550 #undef TARGET_STRICT_ARGUMENT_NAMING
42551 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
42552 #undef TARGET_STATIC_CHAIN
42553 #define TARGET_STATIC_CHAIN ix86_static_chain
42554 #undef TARGET_TRAMPOLINE_INIT
42555 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
42556 #undef TARGET_RETURN_POPS_ARGS
42557 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
42559 #undef TARGET_LEGITIMATE_COMBINED_INSN
42560 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
42562 #undef TARGET_ASAN_SHADOW_OFFSET
42563 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
42565 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
42566 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
42568 #undef TARGET_SCALAR_MODE_SUPPORTED_P
42569 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
42571 #undef TARGET_VECTOR_MODE_SUPPORTED_P
42572 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
42574 #undef TARGET_C_MODE_FOR_SUFFIX
42575 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
42577 #ifdef HAVE_AS_TLS
42578 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
42579 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
42580 #endif
42582 #ifdef SUBTARGET_INSERT_ATTRIBUTES
42583 #undef TARGET_INSERT_ATTRIBUTES
42584 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
42585 #endif
42587 #undef TARGET_MANGLE_TYPE
42588 #define TARGET_MANGLE_TYPE ix86_mangle_type
42590 #if !TARGET_MACHO
42591 #undef TARGET_STACK_PROTECT_FAIL
42592 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
42593 #endif
42595 #undef TARGET_FUNCTION_VALUE
42596 #define TARGET_FUNCTION_VALUE ix86_function_value
42598 #undef TARGET_FUNCTION_VALUE_REGNO_P
42599 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
42601 #undef TARGET_PROMOTE_FUNCTION_MODE
42602 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
42604 #undef TARGET_MEMBER_TYPE_FORCES_BLK
42605 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
42607 #undef TARGET_INSTANTIATE_DECLS
42608 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
42610 #undef TARGET_SECONDARY_RELOAD
42611 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
42613 #undef TARGET_CLASS_MAX_NREGS
42614 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
42616 #undef TARGET_PREFERRED_RELOAD_CLASS
42617 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
42618 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
42619 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
42620 #undef TARGET_CLASS_LIKELY_SPILLED_P
42621 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
42623 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
42624 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
42625 ix86_builtin_vectorization_cost
42626 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
42627 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
42628 ix86_vectorize_vec_perm_const_ok
42629 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
42630 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
42631 ix86_preferred_simd_mode
42632 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
42633 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
42634 ix86_autovectorize_vector_sizes
42635 #undef TARGET_VECTORIZE_INIT_COST
42636 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
42637 #undef TARGET_VECTORIZE_ADD_STMT_COST
42638 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
42639 #undef TARGET_VECTORIZE_FINISH_COST
42640 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
42641 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
42642 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
42644 #undef TARGET_SET_CURRENT_FUNCTION
42645 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
42647 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
42648 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
42650 #undef TARGET_OPTION_SAVE
42651 #define TARGET_OPTION_SAVE ix86_function_specific_save
42653 #undef TARGET_OPTION_RESTORE
42654 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
42656 #undef TARGET_OPTION_PRINT
42657 #define TARGET_OPTION_PRINT ix86_function_specific_print
42659 #undef TARGET_OPTION_FUNCTION_VERSIONS
42660 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
42662 #undef TARGET_CAN_INLINE_P
42663 #define TARGET_CAN_INLINE_P ix86_can_inline_p
42665 #undef TARGET_EXPAND_TO_RTL_HOOK
42666 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
42668 #undef TARGET_LEGITIMATE_ADDRESS_P
42669 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
42671 #undef TARGET_LRA_P
42672 #define TARGET_LRA_P hook_bool_void_true
42674 #undef TARGET_REGISTER_PRIORITY
42675 #define TARGET_REGISTER_PRIORITY ix86_register_priority
42677 #undef TARGET_LEGITIMATE_CONSTANT_P
42678 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
42680 #undef TARGET_FRAME_POINTER_REQUIRED
42681 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
42683 #undef TARGET_CAN_ELIMINATE
42684 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
42686 #undef TARGET_EXTRA_LIVE_ON_ENTRY
42687 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
42689 #undef TARGET_ASM_CODE_END
42690 #define TARGET_ASM_CODE_END ix86_code_end
42692 #undef TARGET_CONDITIONAL_REGISTER_USAGE
42693 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
42695 #if TARGET_MACHO
42696 #undef TARGET_INIT_LIBFUNCS
42697 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
42698 #endif
42700 #undef TARGET_SPILL_CLASS
42701 #define TARGET_SPILL_CLASS ix86_spill_class
42704 \f