1 /* Definitions for GCC. Part of the machine description for CRIS.
2 Copyright (C) 1998-2014 Free Software Foundation, Inc.
3 Contributed by Axis Communications. Written by Hans-Peter Nilsson.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-attr.h"
34 #include "stor-layout.h"
40 #include "diagnostic-core.h"
46 #include "tm-constrs.h"
48 #include "target-def.h"
56 /* Usable when we have an amount to add or subtract, and want the
57 optimal size of the insn. */
58 #define ADDITIVE_SIZE_MODIFIER(size) \
59 ((size) <= 63 ? "q" : (size) <= 255 ? "u.b" : (size) <= 65535 ? "u.w" : ".d")
61 #define LOSE_AND_RETURN(msgid, x) \
64 cris_operand_lossage (msgid, x); \
68 enum cris_retinsn_type
69 { CRIS_RETINSN_UNKNOWN
= 0, CRIS_RETINSN_RET
, CRIS_RETINSN_JUMP
};
71 /* Per-function machine data. */
72 struct GTY(()) machine_function
74 int needs_return_address_on_stack
;
76 /* This is the number of registers we save in the prologue due to
80 enum cris_retinsn_type return_type
;
83 /* This little fix suppresses the 'u' or 's' when '%e' in assembly
85 static char cris_output_insn_is_bound
= 0;
87 /* In code for output macros, this is how we know whether e.g. constant
88 goes in code or in a static initializer. */
89 static int in_code
= 0;
91 /* Fix for reg_overlap_mentioned_p. */
92 static int cris_reg_overlap_mentioned_p (rtx
, rtx
);
94 static enum machine_mode
cris_promote_function_mode (const_tree
, enum machine_mode
,
95 int *, const_tree
, int);
97 static unsigned int cris_atomic_align_for_mode (enum machine_mode
);
99 static void cris_print_base (rtx
, FILE *);
101 static void cris_print_index (rtx
, FILE *);
103 static void cris_output_addr_const (FILE *, rtx
);
105 static struct machine_function
* cris_init_machine_status (void);
107 static rtx
cris_struct_value_rtx (tree
, int);
109 static void cris_setup_incoming_varargs (cumulative_args_t
, enum machine_mode
,
110 tree type
, int *, int);
112 static int cris_initial_frame_pointer_offset (void);
114 static void cris_operand_lossage (const char *, rtx
);
116 static int cris_reg_saved_in_regsave_area (unsigned int, bool);
118 static void cris_print_operand (FILE *, rtx
, int);
120 static void cris_print_operand_address (FILE *, rtx
);
122 static bool cris_print_operand_punct_valid_p (unsigned char code
);
124 static bool cris_output_addr_const_extra (FILE *, rtx
);
126 static void cris_conditional_register_usage (void);
128 static void cris_asm_output_mi_thunk
129 (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
131 static void cris_file_start (void);
132 static void cris_init_libfuncs (void);
134 static reg_class_t
cris_preferred_reload_class (rtx
, reg_class_t
);
136 static int cris_register_move_cost (enum machine_mode
, reg_class_t
, reg_class_t
);
137 static int cris_memory_move_cost (enum machine_mode
, reg_class_t
, bool);
138 static bool cris_rtx_costs (rtx
, int, int, int, int *, bool);
139 static int cris_address_cost (rtx
, enum machine_mode
, addr_space_t
, bool);
140 static bool cris_pass_by_reference (cumulative_args_t
, enum machine_mode
,
142 static int cris_arg_partial_bytes (cumulative_args_t
, enum machine_mode
,
144 static rtx
cris_function_arg (cumulative_args_t
, enum machine_mode
,
146 static rtx
cris_function_incoming_arg (cumulative_args_t
,
147 enum machine_mode
, const_tree
, bool);
148 static void cris_function_arg_advance (cumulative_args_t
, enum machine_mode
,
150 static tree
cris_md_asm_clobbers (tree
, tree
, tree
);
151 static bool cris_cannot_force_const_mem (enum machine_mode
, rtx
);
153 static void cris_option_override (void);
155 static bool cris_frame_pointer_required (void);
157 static void cris_asm_trampoline_template (FILE *);
158 static void cris_trampoline_init (rtx
, tree
, rtx
);
160 static rtx
cris_function_value(const_tree
, const_tree
, bool);
161 static rtx
cris_libcall_value (enum machine_mode
, const_rtx
);
162 static bool cris_function_value_regno_p (const unsigned int);
163 static void cris_file_end (void);
165 /* This is the parsed result of the "-max-stack-stackframe=" option. If
166 it (still) is zero, then there was no such option given. */
167 int cris_max_stackframe
= 0;
169 /* This is the parsed result of the "-march=" option, if given. */
170 int cris_cpu_version
= CRIS_DEFAULT_CPU_VERSION
;
172 #undef TARGET_ASM_ALIGNED_HI_OP
173 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t"
174 #undef TARGET_ASM_ALIGNED_SI_OP
175 #define TARGET_ASM_ALIGNED_SI_OP "\t.dword\t"
176 #undef TARGET_ASM_ALIGNED_DI_OP
177 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
179 /* We need to define these, since the 2byte, 4byte, 8byte op:s are only
180 available in ELF. These "normal" pseudos do not have any alignment
181 constraints or side-effects. */
182 #undef TARGET_ASM_UNALIGNED_HI_OP
183 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
185 #undef TARGET_ASM_UNALIGNED_SI_OP
186 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
188 #undef TARGET_ASM_UNALIGNED_DI_OP
189 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
191 #undef TARGET_PRINT_OPERAND
192 #define TARGET_PRINT_OPERAND cris_print_operand
193 #undef TARGET_PRINT_OPERAND_ADDRESS
194 #define TARGET_PRINT_OPERAND_ADDRESS cris_print_operand_address
195 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
196 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P cris_print_operand_punct_valid_p
197 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
198 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA cris_output_addr_const_extra
200 #undef TARGET_CONDITIONAL_REGISTER_USAGE
201 #define TARGET_CONDITIONAL_REGISTER_USAGE cris_conditional_register_usage
203 #undef TARGET_ASM_OUTPUT_MI_THUNK
204 #define TARGET_ASM_OUTPUT_MI_THUNK cris_asm_output_mi_thunk
205 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
206 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
208 #undef TARGET_ASM_FILE_START
209 #define TARGET_ASM_FILE_START cris_file_start
210 #undef TARGET_ASM_FILE_END
211 #define TARGET_ASM_FILE_END cris_file_end
213 #undef TARGET_INIT_LIBFUNCS
214 #define TARGET_INIT_LIBFUNCS cris_init_libfuncs
216 #undef TARGET_LEGITIMATE_ADDRESS_P
217 #define TARGET_LEGITIMATE_ADDRESS_P cris_legitimate_address_p
219 #undef TARGET_LEGITIMATE_CONSTANT_P
220 #define TARGET_LEGITIMATE_CONSTANT_P cris_legitimate_constant_p
222 #undef TARGET_PREFERRED_RELOAD_CLASS
223 #define TARGET_PREFERRED_RELOAD_CLASS cris_preferred_reload_class
225 #undef TARGET_REGISTER_MOVE_COST
226 #define TARGET_REGISTER_MOVE_COST cris_register_move_cost
227 #undef TARGET_MEMORY_MOVE_COST
228 #define TARGET_MEMORY_MOVE_COST cris_memory_move_cost
229 #undef TARGET_RTX_COSTS
230 #define TARGET_RTX_COSTS cris_rtx_costs
231 #undef TARGET_ADDRESS_COST
232 #define TARGET_ADDRESS_COST cris_address_cost
234 #undef TARGET_PROMOTE_FUNCTION_MODE
235 #define TARGET_PROMOTE_FUNCTION_MODE cris_promote_function_mode
237 #undef TARGET_ATOMIC_ALIGN_FOR_MODE
238 #define TARGET_ATOMIC_ALIGN_FOR_MODE cris_atomic_align_for_mode
240 #undef TARGET_STRUCT_VALUE_RTX
241 #define TARGET_STRUCT_VALUE_RTX cris_struct_value_rtx
242 #undef TARGET_SETUP_INCOMING_VARARGS
243 #define TARGET_SETUP_INCOMING_VARARGS cris_setup_incoming_varargs
244 #undef TARGET_PASS_BY_REFERENCE
245 #define TARGET_PASS_BY_REFERENCE cris_pass_by_reference
246 #undef TARGET_ARG_PARTIAL_BYTES
247 #define TARGET_ARG_PARTIAL_BYTES cris_arg_partial_bytes
248 #undef TARGET_FUNCTION_ARG
249 #define TARGET_FUNCTION_ARG cris_function_arg
250 #undef TARGET_FUNCTION_INCOMING_ARG
251 #define TARGET_FUNCTION_INCOMING_ARG cris_function_incoming_arg
252 #undef TARGET_FUNCTION_ARG_ADVANCE
253 #define TARGET_FUNCTION_ARG_ADVANCE cris_function_arg_advance
254 #undef TARGET_MD_ASM_CLOBBERS
255 #define TARGET_MD_ASM_CLOBBERS cris_md_asm_clobbers
257 #undef TARGET_CANNOT_FORCE_CONST_MEM
258 #define TARGET_CANNOT_FORCE_CONST_MEM cris_cannot_force_const_mem
260 #undef TARGET_FRAME_POINTER_REQUIRED
261 #define TARGET_FRAME_POINTER_REQUIRED cris_frame_pointer_required
263 #undef TARGET_OPTION_OVERRIDE
264 #define TARGET_OPTION_OVERRIDE cris_option_override
266 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
267 #define TARGET_ASM_TRAMPOLINE_TEMPLATE cris_asm_trampoline_template
268 #undef TARGET_TRAMPOLINE_INIT
269 #define TARGET_TRAMPOLINE_INIT cris_trampoline_init
271 #undef TARGET_FUNCTION_VALUE
272 #define TARGET_FUNCTION_VALUE cris_function_value
273 #undef TARGET_LIBCALL_VALUE
274 #define TARGET_LIBCALL_VALUE cris_libcall_value
275 #undef TARGET_FUNCTION_VALUE_REGNO_P
276 #define TARGET_FUNCTION_VALUE_REGNO_P cris_function_value_regno_p
278 struct gcc_target targetm
= TARGET_INITIALIZER
;
280 /* Helper for cris_load_multiple_op and cris_ret_movem_op. */
283 cris_movem_load_rest_p (rtx op
, int offs
)
285 unsigned int reg_count
= XVECLEN (op
, 0) - offs
;
291 unsigned int regno
= 0;
293 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
294 other than (MEM reg). */
296 || GET_CODE (XVECEXP (op
, 0, offs
)) != SET
297 || !REG_P (SET_DEST (XVECEXP (op
, 0, offs
)))
298 || !MEM_P (SET_SRC (XVECEXP (op
, 0, offs
))))
301 /* Check a possible post-inc indicator. */
302 if (GET_CODE (SET_SRC (XVECEXP (op
, 0, offs
+ 1))) == PLUS
)
304 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, offs
+ 1)), 0);
305 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, offs
+ 1)), 1);
311 || !REG_P (SET_DEST (XVECEXP (op
, 0, offs
+ 1)))
312 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, offs
+ 1)))
313 || !CONST_INT_P (inc
)
314 || INTVAL (inc
) != (HOST_WIDE_INT
) reg_count
* 4)
324 regno
= reg_count
- 1;
327 elt
= XVECEXP (op
, 0, offs
);
328 src_addr
= XEXP (SET_SRC (elt
), 0);
330 if (GET_CODE (elt
) != SET
331 || !REG_P (SET_DEST (elt
))
332 || GET_MODE (SET_DEST (elt
)) != SImode
333 || REGNO (SET_DEST (elt
)) != regno
334 || !MEM_P (SET_SRC (elt
))
335 || GET_MODE (SET_SRC (elt
)) != SImode
336 || !memory_address_p (SImode
, src_addr
))
339 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
341 rtx elt
= XVECEXP (op
, 0, i
);
344 if (GET_CODE (elt
) != SET
345 || !REG_P (SET_DEST (elt
))
346 || GET_MODE (SET_DEST (elt
)) != SImode
347 || REGNO (SET_DEST (elt
)) != regno
348 || !MEM_P (SET_SRC (elt
))
349 || GET_MODE (SET_SRC (elt
)) != SImode
350 || GET_CODE (XEXP (SET_SRC (elt
), 0)) != PLUS
351 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt
), 0), 0), src_addr
)
352 || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt
), 0), 1))
353 || INTVAL (XEXP (XEXP (SET_SRC (elt
), 0), 1)) != setno
* 4)
360 /* Worker function for predicate for the parallel contents in a movem
364 cris_store_multiple_op_p (rtx op
)
366 int reg_count
= XVECLEN (op
, 0);
377 /* Perform a quick check so we don't blow up below. FIXME: Adjust for
378 other than (MEM reg) and (MEM (PLUS reg const)). */
382 elt
= XVECEXP (op
, 0, 0);
384 if (GET_CODE (elt
) != SET
)
387 dest
= SET_DEST (elt
);
389 if (!REG_P (SET_SRC (elt
)) || !MEM_P (dest
))
392 dest_addr
= XEXP (dest
, 0);
394 /* Check a possible post-inc indicator. */
395 if (GET_CODE (SET_SRC (XVECEXP (op
, 0, 1))) == PLUS
)
397 rtx reg
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 0);
398 rtx inc
= XEXP (SET_SRC (XVECEXP (op
, 0, 1)), 1);
404 || !REG_P (SET_DEST (XVECEXP (op
, 0, 1)))
405 || REGNO (reg
) != REGNO (SET_DEST (XVECEXP (op
, 0, 1)))
406 || !CONST_INT_P (inc
)
407 /* Support increment by number of registers, and by the offset
408 of the destination, if it has the form (MEM (PLUS reg
410 || !((REG_P (dest_addr
)
411 && REGNO (dest_addr
) == REGNO (reg
)
412 && INTVAL (inc
) == (HOST_WIDE_INT
) reg_count
* 4)
413 || (GET_CODE (dest_addr
) == PLUS
414 && REG_P (XEXP (dest_addr
, 0))
415 && REGNO (XEXP (dest_addr
, 0)) == REGNO (reg
)
416 && CONST_INT_P (XEXP (dest_addr
, 1))
417 && INTVAL (XEXP (dest_addr
, 1)) == INTVAL (inc
))))
428 regno
= reg_count
- 1;
431 if (GET_CODE (elt
) != SET
432 || !REG_P (SET_SRC (elt
))
433 || GET_MODE (SET_SRC (elt
)) != SImode
434 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
435 || !MEM_P (SET_DEST (elt
))
436 || GET_MODE (SET_DEST (elt
)) != SImode
)
439 if (REG_P (dest_addr
))
441 dest_base
= dest_addr
;
444 else if (GET_CODE (dest_addr
) == PLUS
445 && REG_P (XEXP (dest_addr
, 0))
446 && CONST_INT_P (XEXP (dest_addr
, 1)))
448 dest_base
= XEXP (dest_addr
, 0);
449 offset
= INTVAL (XEXP (dest_addr
, 1));
454 for (setno
= 1; i
< XVECLEN (op
, 0); setno
++, i
++)
456 rtx elt
= XVECEXP (op
, 0, i
);
459 if (GET_CODE (elt
) != SET
460 || !REG_P (SET_SRC (elt
))
461 || GET_MODE (SET_SRC (elt
)) != SImode
462 || REGNO (SET_SRC (elt
)) != (unsigned int) regno
463 || !MEM_P (SET_DEST (elt
))
464 || GET_MODE (SET_DEST (elt
)) != SImode
465 || GET_CODE (XEXP (SET_DEST (elt
), 0)) != PLUS
466 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt
), 0), 0), dest_base
)
467 || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt
), 0), 1))
468 || INTVAL (XEXP (XEXP (SET_DEST (elt
), 0), 1)) != setno
* 4 + offset
)
475 /* The TARGET_CONDITIONAL_REGISTER_USAGE worker. */
478 cris_conditional_register_usage (void)
480 /* FIXME: This isn't nice. We should be able to use that register for
481 something else if the PIC table isn't needed. */
483 fixed_regs
[PIC_OFFSET_TABLE_REGNUM
]
484 = call_used_regs
[PIC_OFFSET_TABLE_REGNUM
] = 1;
486 /* Allow use of ACR (PC in pre-V32) and tweak order. */
489 static const int reg_alloc_order_v32
[] = REG_ALLOC_ORDER_V32
;
492 fixed_regs
[CRIS_ACR_REGNUM
] = 0;
495 i
< sizeof (reg_alloc_order_v32
)/sizeof (reg_alloc_order_v32
[0]);
497 reg_alloc_order
[i
] = reg_alloc_order_v32
[i
];
500 if (TARGET_HAS_MUL_INSNS
)
501 fixed_regs
[CRIS_MOF_REGNUM
] = 0;
503 /* On early versions, we must use the 16-bit condition-code register,
504 which has another name. */
505 if (cris_cpu_version
< 8)
506 reg_names
[CRIS_CC0_REGNUM
] = "ccr";
509 /* Return crtl->uses_pic_offset_table. For use in cris.md,
510 since some generated files do not include function.h. */
513 cris_cfun_uses_pic_table (void)
515 return crtl
->uses_pic_offset_table
;
518 /* Worker function for TARGET_CANNOT_FORCE_CONST_MEM.
519 We can't put PIC addresses in the constant pool, not even the ones that
520 can be reached as pc-relative as we can't tell when or how to do that. */
523 cris_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
525 enum cris_symbol_type t
= cris_symbol_type_of (x
);
529 || t
== cris_got_symbol
530 || t
== cris_rel_symbol
;
533 /* Given an rtx, return the text string corresponding to the CODE of X.
534 Intended for use in the assembly language output section of a
540 cris_output_insn_is_bound
= 0;
541 switch (GET_CODE (x
))
552 /* This function is for retrieving a part of an instruction name for
553 an operator, for immediate output. If that ever happens for
554 MULT, we need to apply TARGET_MUL_BUG in the caller. Make sure
556 internal_error ("MULT case in cris_op_str");
592 /* Used to control the sign/zero-extend character for the 'E' modifier.
594 cris_output_insn_is_bound
= 1;
599 return "Unknown operator";
604 /* Emit an error message when we're in an asm, and a fatal error for
605 "normal" insns. Formatted output isn't easily implemented, since we
606 use output_operand_lossage to output the actual message and handle the
607 categorization of the error. */
610 cris_operand_lossage (const char *msgid
, rtx op
)
613 output_operand_lossage ("%s", msgid
);
616 /* Print an index part of an address to file. */
619 cris_print_index (rtx index
, FILE *file
)
621 /* Make the index "additive" unless we'll output a negative number, in
622 which case the sign character is free (as in free beer). */
623 if (!CONST_INT_P (index
) || INTVAL (index
) >= 0)
627 fprintf (file
, "$%s.b", reg_names
[REGNO (index
)]);
628 else if (CRIS_CONSTANT_P (index
))
629 cris_output_addr_const (file
, index
);
630 else if (GET_CODE (index
) == MULT
)
632 fprintf (file
, "$%s.",
633 reg_names
[REGNO (XEXP (index
, 0))]);
635 putc (INTVAL (XEXP (index
, 1)) == 2 ? 'w' : 'd', file
);
637 else if (GET_CODE (index
) == SIGN_EXTEND
&& MEM_P (XEXP (index
, 0)))
639 rtx inner
= XEXP (index
, 0);
640 rtx inner_inner
= XEXP (inner
, 0);
642 if (GET_CODE (inner_inner
) == POST_INC
)
644 fprintf (file
, "[$%s+].",
645 reg_names
[REGNO (XEXP (inner_inner
, 0))]);
646 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
650 fprintf (file
, "[$%s].", reg_names
[REGNO (inner_inner
)]);
652 putc (GET_MODE (inner
) == HImode
? 'w' : 'b', file
);
655 else if (MEM_P (index
))
657 rtx inner
= XEXP (index
, 0);
658 if (GET_CODE (inner
) == POST_INC
)
659 fprintf (file
, "[$%s+].d", reg_names
[REGNO (XEXP (inner
, 0))]);
661 fprintf (file
, "[$%s].d", reg_names
[REGNO (inner
)]);
664 cris_operand_lossage ("unexpected index-type in cris_print_index",
668 /* Print a base rtx of an address to file. */
671 cris_print_base (rtx base
, FILE *file
)
674 fprintf (file
, "$%s", reg_names
[REGNO (base
)]);
675 else if (GET_CODE (base
) == POST_INC
)
677 gcc_assert (REGNO (XEXP (base
, 0)) != CRIS_ACR_REGNUM
);
678 fprintf (file
, "$%s+", reg_names
[REGNO (XEXP (base
, 0))]);
681 cris_operand_lossage ("unexpected base-type in cris_print_base",
685 /* Usable as a guard in expressions. */
688 cris_fatal (char *arg
)
690 internal_error (arg
);
692 /* We'll never get here; this is just to appease compilers. */
696 /* Return nonzero if REGNO is an ordinary register that *needs* to be
697 saved together with other registers, possibly by a MOVEM instruction,
698 or is saved for target-independent reasons. There may be
699 target-dependent reasons to save the register anyway; this is just a
700 wrapper for a complicated conditional. */
703 cris_reg_saved_in_regsave_area (unsigned int regno
, bool got_really_used
)
706 (((df_regs_ever_live_p (regno
)
707 && !call_used_regs
[regno
])
708 || (regno
== PIC_OFFSET_TABLE_REGNUM
710 /* It is saved anyway, if there would be a gap. */
712 && df_regs_ever_live_p (regno
+ 1)
713 && !call_used_regs
[regno
+ 1]))))
714 && (regno
!= FRAME_POINTER_REGNUM
|| !frame_pointer_needed
)
715 && regno
!= CRIS_SRP_REGNUM
)
716 || (crtl
->calls_eh_return
717 && (regno
== EH_RETURN_DATA_REGNO (0)
718 || regno
== EH_RETURN_DATA_REGNO (1)
719 || regno
== EH_RETURN_DATA_REGNO (2)
720 || regno
== EH_RETURN_DATA_REGNO (3)));
723 /* The PRINT_OPERAND worker. */
726 cris_print_operand (FILE *file
, rtx x
, int code
)
730 /* Size-strings corresponding to MULT expressions. */
731 static const char *const mults
[] = { "BAD:0", ".b", ".w", "BAD:3", ".d" };
733 /* New code entries should just be added to the switch below. If
734 handling is finished, just return. If handling was just a
735 modification of the operand, the modified operand should be put in
736 "operand", and then do a break to let default handling
737 (zero-modifier) output the operand. */
742 /* Print the unsigned supplied integer as if it were signed
743 and < 0, i.e print 255 or 65535 as -1, 254, 65534 as -2, etc. */
744 if (!satisfies_constraint_O (x
))
745 LOSE_AND_RETURN ("invalid operand for 'b' modifier", x
);
746 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
747 INTVAL (x
)| (INTVAL (x
) <= 255 ? ~255 : ~65535));
751 /* Print assembler code for operator. */
752 fprintf (file
, "%s", cris_op_str (operand
));
757 /* A movem modifier working on a parallel; output the register
761 if (GET_CODE (x
) != PARALLEL
)
762 LOSE_AND_RETURN ("invalid operand for 'o' modifier", x
);
764 /* The second item can be (set reg (plus reg const)) to denote a
767 = (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
769 : XVECLEN (x
, 0) - 1);
771 fprintf (file
, "$%s", reg_names
[regno
]);
777 /* A similar movem modifier; output the memory operand. */
780 if (GET_CODE (x
) != PARALLEL
)
781 LOSE_AND_RETURN ("invalid operand for 'O' modifier", x
);
783 /* The lowest mem operand is in the first item, but perhaps it
784 needs to be output as postincremented. */
785 addr
= MEM_P (SET_SRC (XVECEXP (x
, 0, 0)))
786 ? XEXP (SET_SRC (XVECEXP (x
, 0, 0)), 0)
787 : XEXP (SET_DEST (XVECEXP (x
, 0, 0)), 0);
789 /* The second item can be a (set reg (plus reg const)) to denote
791 if (GET_CODE (SET_SRC (XVECEXP (x
, 0, 1))) == PLUS
)
793 /* It's a post-increment, if the address is a naked (reg). */
795 addr
= gen_rtx_POST_INC (SImode
, addr
);
798 /* Otherwise, it's a side-effect; RN=RN+M. */
799 fprintf (file
, "[$%s=$%s%s%d]",
800 reg_names
[REGNO (SET_DEST (XVECEXP (x
, 0, 1)))],
801 reg_names
[REGNO (XEXP (addr
, 0))],
802 INTVAL (XEXP (addr
, 1)) < 0 ? "" : "+",
803 (int) INTVAL (XEXP (addr
, 1)));
807 output_address (addr
);
812 /* Adjust a power of two to its log2. */
813 if (!CONST_INT_P (x
) || exact_log2 (INTVAL (x
)) < 0 )
814 LOSE_AND_RETURN ("invalid operand for 'p' modifier", x
);
815 fprintf (file
, "%d", exact_log2 (INTVAL (x
)));
819 /* For an integer, print 'b' or 'w' if <= 255 or <= 65535
820 respectively. This modifier also terminates the inhibiting
821 effects of the 'x' modifier. */
822 cris_output_insn_is_bound
= 0;
823 if (GET_MODE (x
) == VOIDmode
&& CONST_INT_P (x
))
827 if (INTVAL (x
) <= 255)
829 else if (INTVAL (x
) <= 65535)
839 /* For a non-integer, print the size of the operand. */
840 putc ((GET_MODE (x
) == SImode
|| GET_MODE (x
) == SFmode
)
841 ? 'd' : GET_MODE (x
) == HImode
? 'w'
842 : GET_MODE (x
) == QImode
? 'b'
843 /* If none of the above, emit an erroneous size letter. */
849 /* Const_int: print b for -127 <= x <= 255,
850 w for -32768 <= x <= 65535, else die. */
852 || INTVAL (x
) < -32768 || INTVAL (x
) > 65535)
853 LOSE_AND_RETURN ("invalid operand for 'z' modifier", x
);
854 putc (INTVAL (x
) >= -128 && INTVAL (x
) <= 255 ? 'b' : 'w', file
);
858 /* If this is a GOT-symbol, print the size-letter corresponding to
859 -fpic/-fPIC. For everything else, print "d". */
861 && GET_CODE (x
) == CONST
862 && GET_CODE (XEXP (x
, 0)) == UNSPEC
863 && XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_GOTREAD
)
868 /* Output a 'nop' if there's nothing for the delay slot.
869 This method stolen from the sparc files. */
870 if (dbr_sequence_length () == 0)
871 fputs ("\n\tnop", file
);
875 /* Output directive for alignment padded with "nop" insns.
876 Optimizing for size, it's plain 4-byte alignment, otherwise we
877 align the section to a cache-line (32 bytes) and skip at max 2
878 bytes, i.e. we skip if it's the last insn on a cache-line. The
879 latter is faster by a small amount (for two test-programs 99.6%
880 and 99.9%) and larger by a small amount (ditto 100.1% and
881 100.2%). This is supposed to be the simplest yet performance-
882 wise least intrusive way to make sure the immediately following
883 (supposed) muls/mulu insn isn't located at the end of a
887 ? ".p2alignw 2,0x050f\n\t"
888 : ".p2alignw 5,0x050f,2\n\t", file
);
892 /* The PIC register. */
894 internal_error ("invalid use of ':' modifier");
895 fprintf (file
, "$%s", reg_names
[PIC_OFFSET_TABLE_REGNUM
]);
899 /* Print high (most significant) part of something. */
900 switch (GET_CODE (operand
))
903 /* If we're having 64-bit HOST_WIDE_INTs, the whole (DImode)
904 value is kept here, and so may be other than 0 or -1. */
905 fprintf (file
, HOST_WIDE_INT_PRINT_DEC
,
906 INTVAL (operand_subword (operand
, 1, 0, DImode
)));
910 /* High part of a long long constant. */
911 if (GET_MODE (operand
) == VOIDmode
)
913 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_HIGH (x
));
917 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
920 /* Print reg + 1. Check that there's not an attempt to print
921 high-parts of registers like stack-pointer or higher, except
922 for SRP (where the "high part" is MOF). */
923 if (REGNO (operand
) > STACK_POINTER_REGNUM
- 2
924 && (REGNO (operand
) != CRIS_SRP_REGNUM
925 || CRIS_SRP_REGNUM
+ 1 != CRIS_MOF_REGNUM
926 || fixed_regs
[CRIS_MOF_REGNUM
] != 0))
927 LOSE_AND_RETURN ("bad register", operand
);
928 fprintf (file
, "$%s", reg_names
[REGNO (operand
) + 1]);
932 /* Adjust memory address to high part. */
934 rtx adj_mem
= operand
;
936 = GET_MODE_BITSIZE (GET_MODE (operand
)) / BITS_PER_UNIT
;
938 /* Adjust so we can use two SImode in DImode.
939 Calling adj_offsettable_operand will make sure it is an
940 offsettable address. Don't do this for a postincrement
941 though; it should remain as it was. */
942 if (GET_CODE (XEXP (adj_mem
, 0)) != POST_INC
)
944 = adjust_address (adj_mem
, GET_MODE (adj_mem
), size
/ 2);
946 output_address (XEXP (adj_mem
, 0));
951 LOSE_AND_RETURN ("invalid operand for 'H' modifier", x
);
955 /* Strip the MEM expression. */
956 operand
= XEXP (operand
, 0);
960 /* Like 'E', but ignore state set by 'x'. FIXME: Use code
961 iterators and attributes in cris.md to avoid the need for %x
962 and %E (and %e) and state passed between those modifiers. */
963 cris_output_insn_is_bound
= 0;
966 /* Print 's' if operand is SIGN_EXTEND or 'u' if ZERO_EXTEND unless
967 cris_output_insn_is_bound is nonzero. */
968 if (GET_CODE (operand
) != SIGN_EXTEND
969 && GET_CODE (operand
) != ZERO_EXTEND
970 && !CONST_INT_P (operand
))
971 LOSE_AND_RETURN ("invalid operand for 'e' modifier", x
);
973 if (cris_output_insn_is_bound
)
975 cris_output_insn_is_bound
= 0;
979 putc (GET_CODE (operand
) == SIGN_EXTEND
980 || (CONST_INT_P (operand
) && INTVAL (operand
) < 0)
985 /* Print the size letter of the inner element. We can do it by
986 calling ourselves with the 's' modifier. */
987 if (GET_CODE (operand
) != SIGN_EXTEND
&& GET_CODE (operand
) != ZERO_EXTEND
)
988 LOSE_AND_RETURN ("invalid operand for 'm' modifier", x
);
989 cris_print_operand (file
, XEXP (operand
, 0), 's');
993 /* Print the least significant part of operand. */
994 if (GET_CODE (operand
) == CONST_DOUBLE
)
996 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
, CONST_DOUBLE_LOW (x
));
999 else if (HOST_BITS_PER_WIDE_INT
> 32 && CONST_INT_P (operand
))
1001 fprintf (file
, HOST_WIDE_INT_PRINT_HEX
,
1002 INTVAL (x
) & ((unsigned int) 0x7fffffff * 2 + 1));
1005 /* Otherwise the least significant part equals the normal part,
1006 so handle it normally. */
1010 /* When emitting an add for the high part of a DImode constant, we
1011 want to use addq for 0 and adds.w for -1. */
1012 if (!CONST_INT_P (operand
))
1013 LOSE_AND_RETURN ("invalid operand for 'A' modifier", x
);
1014 fprintf (file
, INTVAL (operand
) < 0 ? "adds.w" : "addq");
1018 /* For const_int operands, print the additive mnemonic and the
1019 modified operand (byte-sized operands don't save anything):
1020 N=MIN_INT..-65536: add.d N
1021 -65535..-64: subu.w -N
1025 65536..MAX_INT: add.d N.
1026 (Emitted mnemonics are capitalized to simplify testing.)
1027 For anything else (N.B: only register is valid), print "add.d". */
1028 if (REG_P (operand
))
1030 fprintf (file
, "Add.d ");
1032 /* Deal with printing the operand by dropping through to the
1039 gcc_assert (CONST_INT_P (operand
));
1041 val
= INTVAL (operand
);
1042 if (!IN_RANGE (val
, -65535, 65535))
1043 fprintf (file
, "Add.d %d", val
);
1044 else if (val
<= -64)
1045 fprintf (file
, "Subu.w %d", -val
);
1047 fprintf (file
, "Subq %d", -val
);
1049 fprintf (file
, "Addq %d", val
);
1050 else if (val
<= 65535)
1051 fprintf (file
, "Addu.w %d", val
);
1057 /* If the operand is an integer -31..31, print "q" else ".d". */
1058 if (CONST_INT_P (operand
) && IN_RANGE (INTVAL (operand
), -31, 31))
1059 fprintf (file
, "q");
1061 fprintf (file
, ".d");
1065 /* If this is a GOT symbol, force it to be emitted as :GOT and
1066 :GOTPLT regardless of -fpic (i.e. not as :GOT16, :GOTPLT16).
1067 Avoid making this too much of a special case. */
1068 if (flag_pic
== 1 && CRIS_CONSTANT_P (operand
))
1070 int flag_pic_save
= flag_pic
;
1073 cris_output_addr_const (file
, operand
);
1074 flag_pic
= flag_pic_save
;
1080 /* When emitting an sub for the high part of a DImode constant, we
1081 want to use subq for 0 and subs.w for -1. */
1082 if (!CONST_INT_P (operand
))
1083 LOSE_AND_RETURN ("invalid operand for 'D' modifier", x
);
1084 fprintf (file
, INTVAL (operand
) < 0 ? "subs.w" : "subq");
1088 /* Print the operand as the index-part of an address.
1089 Easiest way out is to use cris_print_index. */
1090 cris_print_index (operand
, file
);
1094 /* Print the size letter for an operand to a MULT, which must be a
1095 const_int with a suitable value. */
1096 if (!CONST_INT_P (operand
) || INTVAL (operand
) > 4)
1097 LOSE_AND_RETURN ("invalid operand for 'T' modifier", x
);
1098 fprintf (file
, "%s", mults
[INTVAL (operand
)]);
1102 /* Print "u.w" if a GOT symbol and flag_pic == 1, else ".d". */
1104 && GET_CODE (operand
) == CONST
1105 && GET_CODE (XEXP (operand
, 0)) == UNSPEC
1106 && XINT (XEXP (operand
, 0), 1) == CRIS_UNSPEC_GOTREAD
)
1107 fprintf (file
, "u.w");
1109 fprintf (file
, ".d");
1113 /* No code, print as usual. */
1117 LOSE_AND_RETURN ("invalid operand modifier letter", x
);
1120 /* Print an operand as without a modifier letter. */
1121 switch (GET_CODE (operand
))
1124 if (REGNO (operand
) > 15
1125 && REGNO (operand
) != CRIS_MOF_REGNUM
1126 && REGNO (operand
) != CRIS_SRP_REGNUM
1127 && REGNO (operand
) != CRIS_CC0_REGNUM
)
1128 internal_error ("internal error: bad register: %d", REGNO (operand
));
1129 fprintf (file
, "$%s", reg_names
[REGNO (operand
)]);
1133 output_address (XEXP (operand
, 0));
1137 if (GET_MODE (operand
) == VOIDmode
)
1138 /* A long long constant. */
1139 output_addr_const (file
, operand
);
1142 /* Only single precision is allowed as plain operands the
1143 moment. FIXME: REAL_VALUE_FROM_CONST_DOUBLE isn't
1148 /* FIXME: Perhaps check overflow of the "single". */
1149 REAL_VALUE_FROM_CONST_DOUBLE (r
, operand
);
1150 REAL_VALUE_TO_TARGET_SINGLE (r
, l
);
1152 fprintf (file
, "0x%lx", l
);
1159 cris_output_addr_const (file
, operand
);
1165 /* For a (MULT (reg X) const_int) we output "rX.S". */
1166 int i
= CONST_INT_P (XEXP (operand
, 1))
1167 ? INTVAL (XEXP (operand
, 1)) : INTVAL (XEXP (operand
, 0));
1168 rtx reg
= CONST_INT_P (XEXP (operand
, 1))
1169 ? XEXP (operand
, 0) : XEXP (operand
, 1);
1172 || (!CONST_INT_P (XEXP (operand
, 0))
1173 && !CONST_INT_P (XEXP (operand
, 1))))
1174 LOSE_AND_RETURN ("unexpected multiplicative operand", x
);
1176 cris_print_base (reg
, file
);
1177 fprintf (file
, ".%c",
1178 i
== 0 || (i
== 1 && GET_CODE (operand
) == MULT
) ? 'b'
1180 : (i
== 2 && GET_CODE (operand
) == MULT
) || i
== 1 ? 'w'
1186 /* No need to handle all strange variants, let output_addr_const
1188 if (CRIS_CONSTANT_P (operand
))
1190 cris_output_addr_const (file
, operand
);
1194 LOSE_AND_RETURN ("unexpected operand", x
);
1199 cris_print_operand_punct_valid_p (unsigned char code
)
1201 return (code
== '#' || code
== '!' || code
== ':');
1204 /* The PRINT_OPERAND_ADDRESS worker. */
1207 cris_print_operand_address (FILE *file
, rtx x
)
1209 /* All these were inside MEM:s so output indirection characters. */
1212 if (CONSTANT_ADDRESS_P (x
))
1213 cris_output_addr_const (file
, x
);
1214 else if (cris_base_or_autoincr_p (x
, true))
1215 cris_print_base (x
, file
);
1216 else if (GET_CODE (x
) == PLUS
)
1222 if (cris_base_p (x1
, true))
1224 cris_print_base (x1
, file
);
1225 cris_print_index (x2
, file
);
1227 else if (cris_base_p (x2
, true))
1229 cris_print_base (x2
, file
);
1230 cris_print_index (x1
, file
);
1233 LOSE_AND_RETURN ("unrecognized address", x
);
1237 /* A DIP. Output more indirection characters. */
1239 cris_print_base (XEXP (x
, 0), file
);
1243 LOSE_AND_RETURN ("unrecognized address", x
);
1248 /* The RETURN_ADDR_RTX worker.
1249 We mark that the return address is used, either by EH or
1250 __builtin_return_address, for use by the function prologue and
1251 epilogue. FIXME: This isn't optimal; we just use the mark in the
1252 prologue and epilogue to say that the return address is to be stored
1253 in the stack frame. We could return SRP for leaf-functions and use the
1254 initial-value machinery. */
1257 cris_return_addr_rtx (int count
, rtx frameaddr ATTRIBUTE_UNUSED
)
1259 cfun
->machine
->needs_return_address_on_stack
= 1;
1261 /* The return-address is stored just above the saved frame-pointer (if
1262 present). Apparently we can't eliminate from the frame-pointer in
1263 that direction, so use the incoming args (maybe pretended) pointer. */
1265 ? gen_rtx_MEM (Pmode
, plus_constant (Pmode
, virtual_incoming_args_rtx
, -4))
1269 /* Accessor used in cris.md:return because cfun->machine isn't available
1273 cris_return_address_on_stack (void)
1275 return df_regs_ever_live_p (CRIS_SRP_REGNUM
)
1276 || cfun
->machine
->needs_return_address_on_stack
;
1279 /* Accessor used in cris.md:return because cfun->machine isn't available
1283 cris_return_address_on_stack_for_return (void)
1285 return cfun
->machine
->return_type
== CRIS_RETINSN_RET
? false
1286 : cris_return_address_on_stack ();
1289 /* This used to be the INITIAL_FRAME_POINTER_OFFSET worker; now only
1290 handles FP -> SP elimination offset. */
1293 cris_initial_frame_pointer_offset (void)
1297 /* Initial offset is 0 if we don't have a frame pointer. */
1299 bool got_really_used
= false;
1301 if (crtl
->uses_pic_offset_table
)
1303 push_topmost_sequence ();
1305 = reg_used_between_p (pic_offset_table_rtx
, get_insns (),
1307 pop_topmost_sequence ();
1310 /* And 4 for each register pushed. */
1311 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
1312 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
1315 /* And then, last, we add the locals allocated. */
1316 offs
+= get_frame_size ();
1318 /* And more; the accumulated args size. */
1319 offs
+= crtl
->outgoing_args_size
;
1321 /* Then round it off, in case we use aligned stack. */
1322 if (TARGET_STACK_ALIGN
)
1323 offs
= TARGET_ALIGN_BY_32
? (offs
+ 3) & ~3 : (offs
+ 1) & ~1;
1328 /* The INITIAL_ELIMINATION_OFFSET worker.
1329 Calculate the difference between imaginary registers such as frame
1330 pointer and the stack pointer. Used to eliminate the frame pointer
1331 and imaginary arg pointer. */
1334 cris_initial_elimination_offset (int fromreg
, int toreg
)
1337 = cris_initial_frame_pointer_offset ();
1339 /* We should be able to use regs_ever_live and related prologue
1340 information here, or alpha should not as well. */
1341 bool return_address_on_stack
= cris_return_address_on_stack ();
1343 /* Here we act as if the frame-pointer were needed. */
1344 int ap_fp_offset
= 4 + (return_address_on_stack
? 4 : 0);
1346 if (fromreg
== ARG_POINTER_REGNUM
1347 && toreg
== FRAME_POINTER_REGNUM
)
1348 return ap_fp_offset
;
1350 /* Between the frame pointer and the stack are only "normal" stack
1351 variables and saved registers. */
1352 if (fromreg
== FRAME_POINTER_REGNUM
1353 && toreg
== STACK_POINTER_REGNUM
)
1354 return fp_sp_offset
;
1356 /* We need to balance out the frame pointer here. */
1357 if (fromreg
== ARG_POINTER_REGNUM
1358 && toreg
== STACK_POINTER_REGNUM
)
1359 return ap_fp_offset
+ fp_sp_offset
- 4;
1364 /* Nonzero if X is a hard reg that can be used as an index. */
1366 reg_ok_for_base_p (const_rtx x
, bool strict
)
1368 return ((! strict
&& ! HARD_REGISTER_P (x
))
1369 || REGNO_OK_FOR_BASE_P (REGNO (x
)));
1372 /* Nonzero if X is a hard reg that can be used as an index. */
1374 reg_ok_for_index_p (const_rtx x
, bool strict
)
1376 return reg_ok_for_base_p (x
, strict
);
1379 /* No symbol can be used as an index (or more correct, as a base) together
1380 with a register with PIC; the PIC register must be there. */
1383 cris_constant_index_p (const_rtx x
)
1385 return (CRIS_CONSTANT_P (x
) && (!flag_pic
|| cris_valid_pic_const (x
, true)));
1388 /* True if X is a valid base register. */
1391 cris_base_p (const_rtx x
, bool strict
)
1393 return (REG_P (x
) && reg_ok_for_base_p (x
, strict
));
1396 /* True if X is a valid index register. */
1399 cris_index_p (const_rtx x
, bool strict
)
1401 return (REG_P (x
) && reg_ok_for_index_p (x
, strict
));
1404 /* True if X is a valid base register with or without autoincrement. */
1407 cris_base_or_autoincr_p (const_rtx x
, bool strict
)
1409 return (cris_base_p (x
, strict
)
1410 || (GET_CODE (x
) == POST_INC
1411 && cris_base_p (XEXP (x
, 0), strict
)
1412 && REGNO (XEXP (x
, 0)) != CRIS_ACR_REGNUM
));
1415 /* True if X is a valid (register) index for BDAP, i.e. [Rs].S or [Rs+].S. */
1418 cris_bdap_index_p (const_rtx x
, bool strict
)
1421 && GET_MODE (x
) == SImode
1422 && cris_base_or_autoincr_p (XEXP (x
, 0), strict
))
1423 || (GET_CODE (x
) == SIGN_EXTEND
1424 && MEM_P (XEXP (x
, 0))
1425 && (GET_MODE (XEXP (x
, 0)) == HImode
1426 || GET_MODE (XEXP (x
, 0)) == QImode
)
1427 && cris_base_or_autoincr_p (XEXP (XEXP (x
, 0), 0), strict
)));
1430 /* True if X is a valid (register) index for BIAP, i.e. Rd.m. */
1433 cris_biap_index_p (const_rtx x
, bool strict
)
1435 return (cris_index_p (x
, strict
)
1436 || (GET_CODE (x
) == MULT
1437 && cris_index_p (XEXP (x
, 0), strict
)
1438 && cris_scale_int_operand (XEXP (x
, 1), VOIDmode
)));
1441 /* Worker function for TARGET_LEGITIMATE_ADDRESS_P.
1443 A PIC operand looks like a normal symbol here. At output we dress it
1444 in "[rPIC+symbol:GOT]" (global symbol) or "rPIC+symbol:GOTOFF" (local
1445 symbol) so we exclude all addressing modes where we can't replace a
1446 plain "symbol" with that. A global PIC symbol does not fit anywhere
1447 here (but is thankfully a general_operand in itself). A local PIC
1448 symbol is valid for the plain "symbol + offset" case. */
1451 cris_legitimate_address_p (enum machine_mode mode
, rtx x
, bool strict
)
1455 if (cris_base_or_autoincr_p (x
, strict
))
1457 else if (TARGET_V32
)
1458 /* Nothing else is valid then. */
1460 else if (cris_constant_index_p (x
))
1463 else if (GET_CODE (x
) == PLUS
)
1468 if ((cris_base_p (x1
, strict
) && cris_constant_index_p (x2
))
1469 || (cris_base_p (x2
, strict
) && cris_constant_index_p (x1
))
1470 /* BDAP Rs[+], Rd. */
1471 || (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
1472 && ((cris_base_p (x1
, strict
)
1473 && cris_bdap_index_p (x2
, strict
))
1474 || (cris_base_p (x2
, strict
)
1475 && cris_bdap_index_p (x1
, strict
))
1477 || (cris_base_p (x1
, strict
)
1478 && cris_biap_index_p (x2
, strict
))
1479 || (cris_base_p (x2
, strict
)
1480 && cris_biap_index_p (x1
, strict
)))))
1485 /* DIP (Rs). Reject [[reg+]] and [[reg]] for DImode (long long). */
1486 if (GET_MODE_SIZE (mode
) <= UNITS_PER_WORD
1487 && cris_base_or_autoincr_p (XEXP (x
, 0), strict
))
1494 /* Worker function for TARGET_LEGITIMATE_CONSTANT_P. We have to handle
1495 PIC constants that aren't legitimized. FIXME: there used to be a
1496 guarantee that the target LEGITIMATE_CONSTANT_P didn't have to handle
1497 PIC constants, but no more (4.7 era); testcase: glibc init-first.c.
1498 While that may be seen as a bug, that guarantee seems a wart by design,
1499 so don't bother; fix the documentation instead. */
1502 cris_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1504 enum cris_symbol_type t
;
1507 return LEGITIMATE_PIC_OPERAND_P (x
);
1509 t
= cris_symbol_type_of (x
);
1513 || t
== cris_offsettable_symbol
1514 || t
== cris_unspec
;
1517 /* Worker function for LEGITIMIZE_RELOAD_ADDRESS. */
1520 cris_reload_address_legitimized (rtx x
,
1521 enum machine_mode mode ATTRIBUTE_UNUSED
,
1522 int opnum ATTRIBUTE_UNUSED
,
1524 int ind_levels ATTRIBUTE_UNUSED
)
1526 enum reload_type type
= (enum reload_type
) itype
;
1530 if (GET_CODE (x
) != PLUS
)
1538 op1p
= &XEXP (x
, 1);
1543 if (GET_CODE (op0
) == SIGN_EXTEND
&& MEM_P (XEXP (op0
, 0)))
1545 rtx op00
= XEXP (op0
, 0);
1546 rtx op000
= XEXP (op00
, 0);
1547 rtx
*op000p
= &XEXP (op00
, 0);
1549 if ((GET_MODE (op00
) == HImode
|| GET_MODE (op00
) == QImode
)
1551 || (GET_CODE (op000
) == POST_INC
&& REG_P (XEXP (op000
, 0)))))
1553 bool something_reloaded
= false;
1555 if (GET_CODE (op000
) == POST_INC
1556 && REG_P (XEXP (op000
, 0))
1557 && REGNO (XEXP (op000
, 0)) > CRIS_LAST_GENERAL_REGISTER
)
1558 /* No, this gets too complicated and is too rare to care
1559 about trying to improve on the general code Here.
1560 As the return-value is an all-or-nothing indicator, we
1561 punt on the other register too. */
1565 && REGNO (op000
) > CRIS_LAST_GENERAL_REGISTER
))
1567 /* The address of the inner mem is a pseudo or wrong
1568 reg: reload that. */
1569 push_reload (op000
, NULL_RTX
, op000p
, NULL
, GENERAL_REGS
,
1570 GET_MODE (x
), VOIDmode
, 0, 0, opnum
, type
);
1571 something_reloaded
= true;
1574 if (REGNO (op1
) > CRIS_LAST_GENERAL_REGISTER
)
1576 /* Base register is a pseudo or wrong reg: reload it. */
1577 push_reload (op1
, NULL_RTX
, op1p
, NULL
, GENERAL_REGS
,
1578 GET_MODE (x
), VOIDmode
, 0, 0,
1580 something_reloaded
= true;
1583 gcc_assert (something_reloaded
);
1593 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS.
1595 It seems like gcc (2.7.2 and 2.9x of 2000-03-22) may send "NO_REGS" as
1596 the class for a constant (testcase: __Mul in arit.c). To avoid forcing
1597 out a constant into the constant pool, we will trap this case and
1598 return something a bit more sane. FIXME: Check if this is a bug.
1599 Beware that we must not "override" classes that can be specified as
1600 constraint letters, or else asm operands using them will fail when
1601 they need to be reloaded. FIXME: Investigate whether that constitutes
1605 cris_preferred_reload_class (rtx x ATTRIBUTE_UNUSED
, reg_class_t rclass
)
1607 if (rclass
!= ACR_REGS
1608 && rclass
!= MOF_REGS
1609 && rclass
!= MOF_SRP_REGS
1610 && rclass
!= SRP_REGS
1611 && rclass
!= CC0_REGS
1612 && rclass
!= SPECIAL_REGS
)
1613 return GENERAL_REGS
;
1618 /* Worker function for TARGET_REGISTER_MOVE_COST. */
1621 cris_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED
,
1622 reg_class_t from
, reg_class_t to
)
1624 /* Can't move to and from a SPECIAL_REGS register, so we have to say
1625 their move cost within that class is higher. How about 7? That's 3
1626 for a move to a GENERAL_REGS register, 3 for the move from the
1627 GENERAL_REGS register, and 1 for the increased register pressure.
1628 Also, it's higher than the memory move cost, as it should.
1629 We also do this for ALL_REGS, since we don't want that class to be
1630 preferred (even to memory) at all where GENERAL_REGS doesn't fit.
1631 Whenever it's about to be used, it's for SPECIAL_REGS. If we don't
1632 present a higher cost for ALL_REGS than memory, a SPECIAL_REGS may be
1633 used when a GENERAL_REGS should be used, even if there are call-saved
1634 GENERAL_REGS left to allocate. This is because the fall-back when
1635 the most preferred register class isn't available, isn't the next
1636 (or next good) wider register class, but the *most widest* register
1637 class. FIXME: pre-IRA comment, perhaps obsolete now. */
1639 if ((reg_classes_intersect_p (from
, SPECIAL_REGS
)
1640 && reg_classes_intersect_p (to
, SPECIAL_REGS
))
1641 || from
== ALL_REGS
|| to
== ALL_REGS
)
1644 /* Make moves to/from SPECIAL_REGS slightly more expensive, as we
1645 generally prefer GENERAL_REGS. */
1646 if (reg_classes_intersect_p (from
, SPECIAL_REGS
)
1647 || reg_classes_intersect_p (to
, SPECIAL_REGS
))
1653 /* Worker function for TARGET_MEMORY_MOVE_COST.
1655 This isn't strictly correct for v0..3 in buswidth-8bit mode, but should
1659 cris_memory_move_cost (enum machine_mode mode
,
1660 reg_class_t rclass ATTRIBUTE_UNUSED
,
1661 bool in ATTRIBUTE_UNUSED
)
1670 /* Worker for cris_notice_update_cc; handles the "normal" cases.
1671 FIXME: this code is historical; its functionality should be
1672 refactored to look at insn attributes and moved to
1673 cris_notice_update_cc. Except, we better lose cc0 entirely. */
1676 cris_normal_notice_update_cc (rtx exp
, rtx insn
)
1678 /* "Normal" means, for:
1683 CC is (reg) and (...) - unless (...) is 0 or reg is a special
1684 register or (v32 and (...) is -32..-1), then CC does not change.
1685 CC_NO_OVERFLOW unless (...) is reg or mem.
1694 (set (reg1) (mem (bdap/biap)))
1695 (set (reg2) (bdap/biap))):
1696 CC is (reg1) and (mem (reg2))
1699 (set (mem (bdap/biap)) (reg1)) [or 0]
1700 (set (reg2) (bdap/biap))):
1703 (where reg and mem includes strict_low_parts variants thereof)
1705 For all others, assume CC is clobbered.
1706 Note that we do not have to care about setting CC_NO_OVERFLOW,
1707 since the overflow flag is set to 0 (i.e. right) for
1708 instructions where it does not have any sane sense, but where
1709 other flags have meanings. (This includes shifts; the carry is
1712 Note that there are other parallel constructs we could match,
1713 but we don't do that yet. */
1715 if (GET_CODE (exp
) == SET
)
1717 /* FIXME: Check when this happens. It looks like we should
1718 actually do a CC_STATUS_INIT here to be safe. */
1719 if (SET_DEST (exp
) == pc_rtx
)
1722 /* Record CC0 changes, so we do not have to output multiple
1724 if (SET_DEST (exp
) == cc0_rtx
)
1728 if (GET_CODE (SET_SRC (exp
)) == COMPARE
1729 && XEXP (SET_SRC (exp
), 1) == const0_rtx
)
1730 cc_status
.value1
= XEXP (SET_SRC (exp
), 0);
1732 cc_status
.value1
= SET_SRC (exp
);
1734 /* Handle flags for the special btstq on one bit. */
1735 if (GET_CODE (cc_status
.value1
) == ZERO_EXTRACT
1736 && XEXP (cc_status
.value1
, 1) == const1_rtx
)
1738 if (CONST_INT_P (XEXP (cc_status
.value1
, 0)))
1740 cc_status
.flags
= CC_INVERTED
;
1742 /* A one-bit btstq. */
1743 cc_status
.flags
= CC_Z_IN_NOT_N
;
1746 else if (GET_CODE (SET_SRC (exp
)) == COMPARE
)
1748 if (!REG_P (XEXP (SET_SRC (exp
), 0))
1749 && XEXP (SET_SRC (exp
), 1) != const0_rtx
)
1750 /* For some reason gcc will not canonicalize compare
1751 operations, reversing the sign by itself if
1752 operands are in wrong order. */
1753 /* (But NOT inverted; eq is still eq.) */
1754 cc_status
.flags
= CC_REVERSED
;
1756 /* This seems to be overlooked by gcc. FIXME: Check again.
1757 FIXME: Is it really safe? */
1759 = gen_rtx_MINUS (GET_MODE (SET_SRC (exp
)),
1760 XEXP (SET_SRC (exp
), 0),
1761 XEXP (SET_SRC (exp
), 1));
1765 else if (REG_P (SET_DEST (exp
))
1766 || (GET_CODE (SET_DEST (exp
)) == STRICT_LOW_PART
1767 && REG_P (XEXP (SET_DEST (exp
), 0))))
1769 /* A register is set; normally CC is set to show that no
1770 test insn is needed. Catch the exceptions. */
1772 /* If not to cc0, then no "set"s in non-natural mode give
1774 if (GET_MODE_SIZE (GET_MODE (SET_DEST (exp
))) > UNITS_PER_WORD
1775 || GET_MODE_CLASS (GET_MODE (SET_DEST (exp
))) == MODE_FLOAT
)
1777 /* ... except add:s and sub:s in DImode. */
1778 if (GET_MODE (SET_DEST (exp
)) == DImode
1779 && (GET_CODE (SET_SRC (exp
)) == PLUS
1780 || GET_CODE (SET_SRC (exp
)) == MINUS
))
1783 cc_status
.value1
= SET_DEST (exp
);
1784 cc_status
.value2
= SET_SRC (exp
);
1786 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1788 cc_status
.value2
= 0;
1790 /* Add and sub may set V, which gets us
1791 unoptimizable results in "gt" and "le" condition
1793 cc_status
.flags
|= CC_NO_OVERFLOW
;
1798 else if (SET_SRC (exp
) == const0_rtx
1799 || (REG_P (SET_SRC (exp
))
1800 && (REGNO (SET_SRC (exp
))
1801 > CRIS_LAST_GENERAL_REGISTER
))
1803 && REG_P (SET_DEST (exp
))
1804 && satisfies_constraint_I (SET_SRC (exp
))))
1806 /* There's no CC0 change for this case. Just check
1808 if (cc_status
.value1
1809 && modified_in_p (cc_status
.value1
, insn
))
1810 cc_status
.value1
= 0;
1812 if (cc_status
.value2
1813 && modified_in_p (cc_status
.value2
, insn
))
1814 cc_status
.value2
= 0;
1821 cc_status
.value1
= SET_DEST (exp
);
1822 cc_status
.value2
= SET_SRC (exp
);
1824 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1826 cc_status
.value2
= 0;
1828 /* Some operations may set V, which gets us
1829 unoptimizable results in "gt" and "le" condition
1831 if (GET_CODE (SET_SRC (exp
)) == PLUS
1832 || GET_CODE (SET_SRC (exp
)) == MINUS
1833 || GET_CODE (SET_SRC (exp
)) == NEG
)
1834 cc_status
.flags
|= CC_NO_OVERFLOW
;
1836 /* For V32, nothing with a register destination sets
1837 C and V usefully. */
1839 cc_status
.flags
|= CC_NO_OVERFLOW
;
1844 else if (MEM_P (SET_DEST (exp
))
1845 || (GET_CODE (SET_DEST (exp
)) == STRICT_LOW_PART
1846 && MEM_P (XEXP (SET_DEST (exp
), 0))))
1848 /* When SET to MEM, then CC is not changed (except for
1850 if (cc_status
.value1
1851 && modified_in_p (cc_status
.value1
, insn
))
1852 cc_status
.value1
= 0;
1854 if (cc_status
.value2
1855 && modified_in_p (cc_status
.value2
, insn
))
1856 cc_status
.value2
= 0;
1861 else if (GET_CODE (exp
) == PARALLEL
)
1863 if (GET_CODE (XVECEXP (exp
, 0, 0)) == SET
1864 && GET_CODE (XVECEXP (exp
, 0, 1)) == SET
1865 && REG_P (XEXP (XVECEXP (exp
, 0, 1), 0)))
1867 if (REG_P (XEXP (XVECEXP (exp
, 0, 0), 0))
1868 && MEM_P (XEXP (XVECEXP (exp
, 0, 0), 1)))
1872 /* For "move.S [rx=ry+o],rz", say CC reflects
1873 value1=rz and value2=[rx] */
1874 cc_status
.value1
= XEXP (XVECEXP (exp
, 0, 0), 0);
1876 = replace_equiv_address (XEXP (XVECEXP (exp
, 0, 0), 1),
1877 XEXP (XVECEXP (exp
, 0, 1), 0));
1879 /* Huh? A side-effect cannot change the destination
1881 if (cris_reg_overlap_mentioned_p (cc_status
.value1
,
1883 internal_error ("internal error: sideeffect-insn affecting main effect");
1885 /* For V32, moves to registers don't set C and V. */
1887 cc_status
.flags
|= CC_NO_OVERFLOW
;
1890 else if ((REG_P (XEXP (XVECEXP (exp
, 0, 0), 1))
1891 || XEXP (XVECEXP (exp
, 0, 0), 1) == const0_rtx
)
1892 && MEM_P (XEXP (XVECEXP (exp
, 0, 0), 0)))
1894 /* For "move.S rz,[rx=ry+o]" and "clear.S [rx=ry+o]",
1895 say flags are not changed, except for overlap. */
1896 if (cc_status
.value1
1897 && modified_in_p (cc_status
.value1
, insn
))
1898 cc_status
.value1
= 0;
1900 if (cc_status
.value2
1901 && modified_in_p (cc_status
.value2
, insn
))
1902 cc_status
.value2
= 0;
1909 /* If we got here, the case wasn't covered by the code above. */
1913 /* This function looks into the pattern to see how this insn affects
1916 Used when to eliminate test insns before a condition-code user,
1917 such as a "scc" insn or a conditional branch. This includes
1918 checking if the entities that cc was updated by, are changed by the
1921 Currently a jumble of the old peek-inside-the-insn and the newer
1922 check-cc-attribute methods. */
1925 cris_notice_update_cc (rtx exp
, rtx insn
)
1927 enum attr_cc attrval
= get_attr_cc (insn
);
1929 /* Check if user specified "-mcc-init" as a bug-workaround. Remember
1930 to still set CC_REVERSED as below, since that's required by some
1931 compare insn alternatives. (FIXME: GCC should do this virtual
1932 operand swap by itself.) A test-case that may otherwise fail is
1933 gcc.c-torture/execute/20000217-1.c -O0 and -O1. */
1938 if (attrval
== CC_REV
)
1939 cc_status
.flags
= CC_REVERSED
;
1943 /* Slowly, we're converting to using attributes to control the setting
1944 of condition-code status. */
1948 /* Even if it is "none", a setting may clobber a previous
1949 cc-value, so check. */
1950 if (GET_CODE (exp
) == SET
)
1952 if (cc_status
.value1
1953 && modified_in_p (cc_status
.value1
, insn
))
1954 cc_status
.value1
= 0;
1956 if (cc_status
.value2
1957 && modified_in_p (cc_status
.value2
, insn
))
1958 cc_status
.value2
= 0;
1969 cris_normal_notice_update_cc (exp
, insn
);
1971 /* The "test" insn doesn't clear (carry and) overflow on V32. We
1972 can change bge => bpl and blt => bmi by passing on to the cc0
1973 user that V should not be considered; bgt and ble are taken
1974 care of by other methods (see {tst,cmp}{si,hi,qi}). */
1975 if (attrval
== CC_NOOV32
&& TARGET_V32
)
1976 cc_status
.flags
|= CC_NO_OVERFLOW
;
1980 internal_error ("unknown cc_attr value");
1986 /* Return != 0 if the return sequence for the current function is short,
1987 like "ret" or "jump [sp+]". Prior to reloading, we can't tell if
1988 registers must be saved, so return 0 then. */
1991 cris_simple_epilogue (void)
1994 unsigned int reglimit
= STACK_POINTER_REGNUM
;
1995 bool got_really_used
= false;
1997 if (! reload_completed
1998 || frame_pointer_needed
1999 || get_frame_size () != 0
2000 || crtl
->args
.pretend_args_size
2002 || crtl
->outgoing_args_size
2003 || crtl
->calls_eh_return
2005 /* If we're not supposed to emit prologue and epilogue, we must
2006 not emit return-type instructions. */
2007 || !TARGET_PROLOGUE_EPILOGUE
)
2010 /* Can't return from stacked return address with v32. */
2011 if (TARGET_V32
&& cris_return_address_on_stack ())
2014 if (crtl
->uses_pic_offset_table
)
2016 push_topmost_sequence ();
2018 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL
);
2019 pop_topmost_sequence ();
2022 /* No simple epilogue if there are saved registers. */
2023 for (regno
= 0; regno
< reglimit
; regno
++)
2024 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
2030 /* Emit checking that MEM is aligned for an access in MODE, failing
2031 that, executing a "break 8" (or call to abort, if "break 8" is
2035 cris_emit_trap_for_misalignment (rtx mem
)
2037 rtx addr
, reg
, ok_label
, andop
;
2039 int natural_alignment
;
2040 gcc_assert (MEM_P (mem
));
2042 natural_alignment
= GET_MODE_SIZE (GET_MODE (mem
));
2043 addr
= XEXP (mem
, 0);
2044 reg
= force_reg (Pmode
, addr
);
2045 ok_label
= gen_label_rtx ();
2047 /* This will yield a btstq without a separate register used, usually -
2048 with the exception for PRE hoisting the "and" but not the branch
2049 around the trap: see testsuite/gcc.target/cris/sync-3s.c. */
2050 andop
= gen_rtx_AND (Pmode
, reg
, GEN_INT (natural_alignment
- 1));
2051 emit_cmp_and_jump_insns (force_reg (SImode
, andop
), const0_rtx
, EQ
,
2052 NULL_RTX
, Pmode
, 1, ok_label
);
2053 jmp
= get_last_insn ();
2054 gcc_assert (JUMP_P (jmp
));
2056 predict_insn_def (jmp
, PRED_NORETURN
, TAKEN
);
2057 expand_builtin_trap ();
2058 emit_label (ok_label
);
2061 /* Expand a return insn (just one insn) marked as using SRP or stack
2062 slot depending on parameter ON_STACK. */
2065 cris_expand_return (bool on_stack
)
2067 /* FIXME: emit a parallel with a USE for SRP or the stack-slot, to
2068 tell "ret" from "jump [sp+]". Some, but not all, other parts of
2069 GCC expect just (return) to do the right thing when optimizing, so
2070 we do that until they're fixed. Currently, all return insns in a
2071 function must be the same (not really a limiting factor) so we need
2072 to check that it doesn't change half-way through. */
2073 emit_jump_insn (ret_rtx
);
2075 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_RET
|| !on_stack
);
2076 CRIS_ASSERT (cfun
->machine
->return_type
!= CRIS_RETINSN_JUMP
|| on_stack
);
2078 cfun
->machine
->return_type
2079 = on_stack
? CRIS_RETINSN_JUMP
: CRIS_RETINSN_RET
;
2082 /* Compute a (partial) cost for rtx X. Return true if the complete
2083 cost has been computed, and false if subexpressions should be
2084 scanned. In either case, *TOTAL contains the cost result. */
2087 cris_rtx_costs (rtx x
, int code
, int outer_code
, int opno
, int *total
,
2094 HOST_WIDE_INT val
= INTVAL (x
);
2097 else if (val
< 32 && val
>= -32)
2099 /* Eight or 16 bits are a word and cycle more expensive. */
2100 else if (val
<= 32767 && val
>= -32768)
2102 /* A 32-bit constant (or very seldom, unsigned 16 bits) costs
2103 another word. FIXME: This isn't linear to 16 bits. */
2119 if (x
!= CONST0_RTX (GET_MODE (x
) == VOIDmode
? DImode
: GET_MODE (x
)))
2122 /* Make 0.0 cheap, else test-insns will not be used. */
2127 /* If we have one arm of an ADDI, make sure it gets the cost of
2128 one insn, i.e. zero cost for this operand, and just the cost
2129 of the PLUS, as the insn is created by combine from a PLUS
2130 and an ASHIFT, and the MULT cost below would make the
2131 combined value be larger than the separate insns. The insn
2132 validity is checked elsewhere by combine.
2134 FIXME: this case is a stop-gap for 4.3 and 4.4, this whole
2135 function should be rewritten. */
2136 if (outer_code
== PLUS
&& cris_biap_index_p (x
, false))
2142 /* Identify values that are no powers of two. Powers of 2 are
2143 taken care of already and those values should not be changed. */
2144 if (!CONST_INT_P (XEXP (x
, 1))
2145 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
2147 /* If we have a multiply insn, then the cost is between
2148 1 and 2 "fast" instructions. */
2149 if (TARGET_HAS_MUL_INSNS
)
2151 *total
= COSTS_N_INSNS (1) + COSTS_N_INSNS (1) / 2;
2155 /* Estimate as 4 + 4 * #ofbits. */
2156 *total
= COSTS_N_INSNS (132);
2165 if (!CONST_INT_P (XEXP (x
, 1))
2166 || exact_log2 (INTVAL (XEXP (x
, 1)) < 0))
2168 /* Estimate this as 4 + 8 * #of bits. */
2169 *total
= COSTS_N_INSNS (260);
2175 if (CONST_INT_P (XEXP (x
, 1))
2176 /* Two constants may actually happen before optimization. */
2177 && !CONST_INT_P (XEXP (x
, 0))
2178 && !satisfies_constraint_I (XEXP (x
, 1)))
2181 = (rtx_cost (XEXP (x
, 0), (enum rtx_code
) outer_code
,
2183 + 2 * GET_MODE_NUNITS (GET_MODE (XEXP (x
, 0))));
2189 if (outer_code
!= COMPARE
)
2193 case ZERO_EXTEND
: case SIGN_EXTEND
:
2194 *total
= rtx_cost (XEXP (x
, 0), (enum rtx_code
) outer_code
, opno
, speed
);
2202 /* The ADDRESS_COST worker. */
2205 cris_address_cost (rtx x
, enum machine_mode mode ATTRIBUTE_UNUSED
,
2206 addr_space_t as ATTRIBUTE_UNUSED
,
2207 bool speed ATTRIBUTE_UNUSED
)
2209 /* The metric to use for the cost-macros is unclear.
2210 The metric used here is (the number of cycles needed) / 2,
2211 where we consider equal a cycle for a word of code and a cycle to
2212 read memory. FIXME: Adding "+ 1" to all values would avoid
2213 returning 0, as tree-ssa-loop-ivopts.c as of r128272 "normalizes"
2214 0 to 1, thereby giving equal costs to [rN + rM] and [rN].
2215 Unfortunately(?) such a hack would expose other pessimizations,
2216 at least with g++.dg/tree-ssa/ivopts-1.C, adding insns to the
2217 loop there, without apparent reason. */
2219 /* The cheapest addressing modes get 0, since nothing extra is needed. */
2220 if (cris_base_or_autoincr_p (x
, false))
2223 /* An indirect mem must be a DIP. This means two bytes extra for code,
2224 and 4 bytes extra for memory read, i.e. (2 + 4) / 2. */
2228 /* Assume (2 + 4) / 2 for a single constant; a dword, since it needs
2229 an extra DIP prefix and 4 bytes of constant in most cases. */
2233 /* Handle BIAP and BDAP prefixes. */
2234 if (GET_CODE (x
) == PLUS
)
2236 rtx tem1
= XEXP (x
, 0);
2237 rtx tem2
= XEXP (x
, 1);
2239 /* Local extended canonicalization rule: the first operand must
2240 be REG, unless it's an operation (MULT). */
2241 if (!REG_P (tem1
) && GET_CODE (tem1
) != MULT
)
2242 tem1
= tem2
, tem2
= XEXP (x
, 0);
2244 /* We'll "assume" we have canonical RTX now. */
2245 gcc_assert (REG_P (tem1
) || GET_CODE (tem1
) == MULT
);
2247 /* A BIAP is 2 extra bytes for the prefix insn, nothing more. We
2248 recognize the typical MULT which is always in tem1 because of
2249 insn canonicalization. */
2250 if ((GET_CODE (tem1
) == MULT
&& cris_biap_index_p (tem1
, false))
2254 /* A BDAP (quick) is 2 extra bytes. Any constant operand to the
2255 PLUS is always found in tem2. */
2256 if (CONST_INT_P (tem2
) && INTVAL (tem2
) < 128 && INTVAL (tem2
) >= -128)
2259 /* A BDAP -32768 .. 32767 is like BDAP quick, but with 2 extra
2261 if (satisfies_constraint_L (tem2
))
2264 /* A BDAP with some other constant is 2 bytes extra. */
2265 if (CRIS_CONSTANT_P (tem2
))
2266 return (2 + 2 + 2) / 2;
2268 /* BDAP with something indirect should have a higher cost than
2269 BIAP with register. FIXME: Should it cost like a MEM or more? */
2270 return (2 + 2 + 2) / 2;
2273 /* What else? Return a high cost. It matters only for valid
2274 addressing modes. */
2278 /* Check various objections to the side-effect. Used in the test-part
2279 of an anonymous insn describing an insn with a possible side-effect.
2280 Returns nonzero if the implied side-effect is ok.
2283 ops : An array of rtx:es. lreg, rreg, rval,
2284 The variables multop and other_op are indexes into this,
2285 or -1 if they are not applicable.
2286 lreg : The register that gets assigned in the side-effect.
2287 rreg : One register in the side-effect expression
2288 rval : The other register, or an int.
2289 multop : An integer to multiply rval with.
2290 other_op : One of the entities of the main effect,
2291 whose mode we must consider. */
2294 cris_side_effect_mode_ok (enum rtx_code code
, rtx
*ops
,
2295 int lreg
, int rreg
, int rval
,
2296 int multop
, int other_op
)
2298 /* Find what value to multiply with, for rx =ry + rz * n. */
2299 int mult
= multop
< 0 ? 1 : INTVAL (ops
[multop
]);
2301 rtx reg_rtx
= ops
[rreg
];
2302 rtx val_rtx
= ops
[rval
];
2304 /* The operands may be swapped. Canonicalize them in reg_rtx and
2305 val_rtx, where reg_rtx always is a reg (for this constraint to
2307 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2308 reg_rtx
= val_rtx
, val_rtx
= ops
[rreg
];
2310 /* Don't forget to check that reg_rtx really is a reg. If it isn't,
2311 we have no business. */
2312 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2315 /* Don't do this when -mno-split. */
2316 if (!TARGET_SIDE_EFFECT_PREFIXES
)
2319 /* The mult expression may be hidden in lreg. FIXME: Add more
2320 commentary about that. */
2321 if (GET_CODE (val_rtx
) == MULT
)
2323 mult
= INTVAL (XEXP (val_rtx
, 1));
2324 val_rtx
= XEXP (val_rtx
, 0);
2328 /* First check the "other operand". */
2331 if (GET_MODE_SIZE (GET_MODE (ops
[other_op
])) > UNITS_PER_WORD
)
2334 /* Check if the lvalue register is the same as the "other
2335 operand". If so, the result is undefined and we shouldn't do
2336 this. FIXME: Check again. */
2337 if ((cris_base_p (ops
[lreg
], reload_in_progress
|| reload_completed
)
2338 && cris_base_p (ops
[other_op
],
2339 reload_in_progress
|| reload_completed
)
2340 && REGNO (ops
[lreg
]) == REGNO (ops
[other_op
]))
2341 || rtx_equal_p (ops
[other_op
], ops
[lreg
]))
2345 /* Do not accept frame_pointer_rtx as any operand. */
2346 if (ops
[lreg
] == frame_pointer_rtx
|| ops
[rreg
] == frame_pointer_rtx
2347 || ops
[rval
] == frame_pointer_rtx
2348 || (other_op
>= 0 && ops
[other_op
] == frame_pointer_rtx
))
2352 && ! cris_base_p (val_rtx
, reload_in_progress
|| reload_completed
))
2355 /* Do not allow rx = rx + n if a normal add or sub with same size
2357 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
2358 && CONST_INT_P (val_rtx
)
2359 && (INTVAL (val_rtx
) <= 63 && INTVAL (val_rtx
) >= -63))
2362 /* Check allowed cases, like [r(+)?].[bwd] and const. */
2363 if (CRIS_CONSTANT_P (val_rtx
))
2367 && cris_base_or_autoincr_p (XEXP (val_rtx
, 0),
2368 reload_in_progress
|| reload_completed
))
2371 if (GET_CODE (val_rtx
) == SIGN_EXTEND
2372 && MEM_P (XEXP (val_rtx
, 0))
2373 && cris_base_or_autoincr_p (XEXP (XEXP (val_rtx
, 0), 0),
2374 reload_in_progress
|| reload_completed
))
2377 /* If we got here, it's not a valid addressing mode. */
2380 else if (code
== MULT
2382 && cris_base_p (val_rtx
,
2383 reload_in_progress
|| reload_completed
)))
2385 /* Do not allow rx = rx + ry.S, since it doesn't give better code. */
2386 if (rtx_equal_p (ops
[lreg
], reg_rtx
)
2387 || (mult
== 1 && rtx_equal_p (ops
[lreg
], val_rtx
)))
2390 /* Do not allow bad multiply-values. */
2391 if (mult
!= 1 && mult
!= 2 && mult
!= 4)
2394 /* Only allow r + ... */
2395 if (! cris_base_p (reg_rtx
, reload_in_progress
|| reload_completed
))
2398 /* If we got here, all seems ok.
2399 (All checks need to be done above). */
2403 /* If we get here, the caller got its initial tests wrong. */
2404 internal_error ("internal error: cris_side_effect_mode_ok with bad operands");
2407 /* Whether next_cc0_user of insn is LE or GT or requires a real compare
2408 insn for other reasons. */
2411 cris_cc0_user_requires_cmp (rtx insn
)
2413 rtx_insn
*cc0_user
= NULL
;
2417 gcc_assert (insn
!= NULL
);
2422 cc0_user
= next_cc0_user (insn
);
2423 if (cc0_user
== NULL
)
2426 body
= PATTERN (cc0_user
);
2427 set
= single_set (cc0_user
);
2429 /* Users can be sCC and bCC. */
2430 if (JUMP_P (cc0_user
)
2431 && GET_CODE (body
) == SET
2432 && SET_DEST (body
) == pc_rtx
2433 && GET_CODE (SET_SRC (body
)) == IF_THEN_ELSE
2434 && XEXP (XEXP (SET_SRC (body
), 0), 0) == cc0_rtx
)
2437 GET_CODE (XEXP (SET_SRC (body
), 0)) == GT
2438 || GET_CODE (XEXP (SET_SRC (body
), 0)) == LE
;
2443 GET_CODE (SET_SRC (body
)) == GT
2444 || GET_CODE (SET_SRC (body
)) == LE
;
2450 /* The function reg_overlap_mentioned_p in CVS (still as of 2001-05-16)
2451 does not handle the case where the IN operand is strict_low_part; it
2452 does handle it for X. Test-case in Axis-20010516. This function takes
2453 care of that for THIS port. FIXME: strict_low_part is going away
2457 cris_reg_overlap_mentioned_p (rtx x
, rtx in
)
2459 /* The function reg_overlap_mentioned now handles when X is
2460 strict_low_part, but not when IN is a STRICT_LOW_PART. */
2461 if (GET_CODE (in
) == STRICT_LOW_PART
)
2464 return reg_overlap_mentioned_p (x
, in
);
2467 /* Return TRUE iff X is a CONST valid for e.g. indexing.
2468 ANY_OPERAND is 0 if X is in a CALL_P insn or movsi, 1
2472 cris_valid_pic_const (const_rtx x
, bool any_operand
)
2474 gcc_assert (flag_pic
);
2476 switch (GET_CODE (x
))
2485 if (GET_CODE (x
) != CONST
)
2490 /* Handle (const (plus (unspec .. UNSPEC_GOTREL) (const_int ...))). */
2491 if (GET_CODE (x
) == PLUS
2492 && GET_CODE (XEXP (x
, 0)) == UNSPEC
2493 && (XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_GOTREL
2494 || XINT (XEXP (x
, 0), 1) == CRIS_UNSPEC_PCREL
)
2495 && CONST_INT_P (XEXP (x
, 1)))
2498 if (GET_CODE (x
) == UNSPEC
)
2499 switch (XINT (x
, 1))
2501 /* A PCREL operand is only valid for call and movsi. */
2502 case CRIS_UNSPEC_PLT_PCREL
:
2503 case CRIS_UNSPEC_PCREL
:
2504 return !any_operand
;
2506 case CRIS_UNSPEC_PLT_GOTREL
:
2507 case CRIS_UNSPEC_PLTGOTREAD
:
2508 case CRIS_UNSPEC_GOTREAD
:
2509 case CRIS_UNSPEC_GOTREL
:
2515 return cris_symbol_type_of (x
) == cris_no_symbol
;
2518 /* Helper function to find the right symbol-type to generate,
2519 given the original (non-PIC) representation. */
2521 enum cris_symbol_type
2522 cris_symbol_type_of (const_rtx x
)
2524 switch (GET_CODE (x
))
2528 ? (SYMBOL_REF_LOCAL_P (x
)
2529 ? cris_rel_symbol
: cris_got_symbol
)
2530 : cris_offsettable_symbol
;
2533 return flag_pic
? cris_rel_symbol
: cris_offsettable_symbol
;
2536 return cris_symbol_type_of (XEXP (x
, 0));
2541 enum cris_symbol_type t1
= cris_symbol_type_of (XEXP (x
, 0));
2542 enum cris_symbol_type t2
= cris_symbol_type_of (XEXP (x
, 1));
2544 gcc_assert (t1
== cris_no_symbol
|| t2
== cris_no_symbol
);
2546 if (t1
== cris_got_symbol
|| t2
== cris_got_symbol
)
2547 return cris_got_symbol_needing_fixup
;
2549 return t1
!= cris_no_symbol
? t1
: t2
;
2554 return cris_no_symbol
;
2560 fatal_insn ("unrecognized supposed constant", x
);
2566 /* The LEGITIMATE_PIC_OPERAND_P worker. */
2569 cris_legitimate_pic_operand (rtx x
)
2571 /* Symbols are not valid PIC operands as-is; just constants. */
2572 return cris_valid_pic_const (x
, true);
2575 /* Queue an .ident string in the queue of top-level asm statements.
2576 If the front-end is done, we must be being called from toplev.c.
2577 In that case, do nothing. */
2579 cris_asm_output_ident (const char *string
)
2581 if (symtab
->state
!= PARSING
)
2584 default_asm_output_ident_directive (string
);
2587 /* The ASM_OUTPUT_CASE_END worker. */
2590 cris_asm_output_case_end (FILE *stream
, int num
, rtx table
)
2592 /* Step back, over the label for the table, to the actual casejump and
2593 assert that we find only what's expected. */
2594 rtx whole_jump_insn
= prev_nonnote_nondebug_insn (table
);
2595 gcc_assert (whole_jump_insn
!= NULL_RTX
&& LABEL_P (whole_jump_insn
));
2596 whole_jump_insn
= prev_nonnote_nondebug_insn (whole_jump_insn
);
2597 gcc_assert (whole_jump_insn
!= NULL_RTX
2598 && (JUMP_P (whole_jump_insn
)
2599 || (TARGET_V32
&& INSN_P (whole_jump_insn
)
2600 && GET_CODE (PATTERN (whole_jump_insn
)) == SEQUENCE
)));
2601 /* Get the pattern of the casejump, so we can extract the default label. */
2602 whole_jump_insn
= PATTERN (whole_jump_insn
);
2606 /* This can be a SEQUENCE, meaning the delay-slot of the jump is
2607 filled. We also output the offset word a little differently. */
2609 = (GET_CODE (whole_jump_insn
) == SEQUENCE
2610 ? PATTERN (XVECEXP (whole_jump_insn
, 0, 0)) : whole_jump_insn
);
2612 asm_fprintf (stream
,
2613 "\t.word %LL%d-.%s\n",
2614 CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (XVECEXP
2615 (parallel_jump
, 0, 0),
2617 (TARGET_PDEBUG
? "; default" : ""));
2621 asm_fprintf (stream
,
2622 "\t.word %LL%d-%LL%d%s\n",
2623 CODE_LABEL_NUMBER (XEXP
2625 (XEXP (XVECEXP (whole_jump_insn
, 0, 0), 1),
2628 (TARGET_PDEBUG
? "; default" : ""));
2631 /* The TARGET_OPTION_OVERRIDE worker.
2632 As is the norm, this also parses -mfoo=bar type parameters. */
2635 cris_option_override (void)
2637 if (cris_max_stackframe_str
)
2639 cris_max_stackframe
= atoi (cris_max_stackframe_str
);
2641 /* Do some sanity checking. */
2642 if (cris_max_stackframe
< 0 || cris_max_stackframe
> 0x20000000)
2643 internal_error ("-max-stackframe=%d is not usable, not between 0 and %d",
2644 cris_max_stackframe
, 0x20000000);
2647 /* Let "-metrax4" and "-metrax100" change the cpu version. */
2648 if (TARGET_SVINTO
&& cris_cpu_version
< CRIS_CPU_SVINTO
)
2649 cris_cpu_version
= CRIS_CPU_SVINTO
;
2650 else if (TARGET_ETRAX4_ADD
&& cris_cpu_version
< CRIS_CPU_ETRAX4
)
2651 cris_cpu_version
= CRIS_CPU_ETRAX4
;
2653 /* Parse -march=... and its synonym, the deprecated -mcpu=... */
2657 = (*cris_cpu_str
== 'v' ? atoi (cris_cpu_str
+ 1) : -1);
2659 if (strcmp ("etrax4", cris_cpu_str
) == 0)
2660 cris_cpu_version
= 3;
2662 if (strcmp ("svinto", cris_cpu_str
) == 0
2663 || strcmp ("etrax100", cris_cpu_str
) == 0)
2664 cris_cpu_version
= 8;
2666 if (strcmp ("ng", cris_cpu_str
) == 0
2667 || strcmp ("etrax100lx", cris_cpu_str
) == 0)
2668 cris_cpu_version
= 10;
2670 if (cris_cpu_version
< 0 || cris_cpu_version
> 32)
2671 error ("unknown CRIS version specification in -march= or -mcpu= : %s",
2674 /* Set the target flags. */
2675 if (cris_cpu_version
>= CRIS_CPU_ETRAX4
)
2676 target_flags
|= MASK_ETRAX4_ADD
;
2678 /* If this is Svinto or higher, align for 32 bit accesses. */
2679 if (cris_cpu_version
>= CRIS_CPU_SVINTO
)
2681 |= (MASK_SVINTO
| MASK_ALIGN_BY_32
2682 | MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2685 /* Note that we do not add new flags when it can be completely
2686 described with a macro that uses -mcpu=X. So
2687 TARGET_HAS_MUL_INSNS is (cris_cpu_version >= CRIS_CPU_NG). */
2693 = (*cris_tune_str
== 'v' ? atoi (cris_tune_str
+ 1) : -1);
2695 if (strcmp ("etrax4", cris_tune_str
) == 0)
2698 if (strcmp ("svinto", cris_tune_str
) == 0
2699 || strcmp ("etrax100", cris_tune_str
) == 0)
2702 if (strcmp ("ng", cris_tune_str
) == 0
2703 || strcmp ("etrax100lx", cris_tune_str
) == 0)
2706 if (cris_tune
< 0 || cris_tune
> 32)
2707 error ("unknown CRIS cpu version specification in -mtune= : %s",
2710 if (cris_tune
>= CRIS_CPU_SVINTO
)
2711 /* We have currently nothing more to tune than alignment for
2714 |= (MASK_STACK_ALIGN
| MASK_CONST_ALIGN
2715 | MASK_DATA_ALIGN
| MASK_ALIGN_BY_32
);
2718 if (cris_cpu_version
>= CRIS_CPU_V32
)
2719 target_flags
&= ~(MASK_SIDE_EFFECT_PREFIXES
|MASK_MUL_BUG
);
2723 /* Use error rather than warning, so invalid use is easily
2724 detectable. Still change to the values we expect, to avoid
2728 error ("-fPIC and -fpic are not supported in this configuration");
2732 /* Turn off function CSE. We need to have the addresses reach the
2733 call expanders to get PLT-marked, as they could otherwise be
2734 compared against zero directly or indirectly. After visiting the
2735 call expanders they will then be cse:ed, as the call expanders
2736 force_reg the addresses, effectively forcing flag_no_function_cse
2738 flag_no_function_cse
= 1;
2741 /* Set the per-function-data initializer. */
2742 init_machine_status
= cris_init_machine_status
;
2745 /* The TARGET_ASM_OUTPUT_MI_THUNK worker. */
2748 cris_asm_output_mi_thunk (FILE *stream
,
2749 tree thunkdecl ATTRIBUTE_UNUSED
,
2750 HOST_WIDE_INT delta
,
2751 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
2754 /* Make sure unwind info is emitted for the thunk if needed. */
2755 final_start_function (emit_barrier (), stream
, 1);
2758 fprintf (stream
, "\tadd%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2759 ADDITIVE_SIZE_MODIFIER (delta
), delta
,
2760 reg_names
[CRIS_FIRST_ARG_REG
]);
2762 fprintf (stream
, "\tsub%s " HOST_WIDE_INT_PRINT_DEC
",$%s\n",
2763 ADDITIVE_SIZE_MODIFIER (-delta
), -delta
,
2764 reg_names
[CRIS_FIRST_ARG_REG
]);
2768 const char *name
= XSTR (XEXP (DECL_RTL (funcdecl
), 0), 0);
2770 name
= (* targetm
.strip_name_encoding
) (name
);
2774 fprintf (stream
, "\tba ");
2775 assemble_name (stream
, name
);
2776 fprintf (stream
, "%s\n", CRIS_PLT_PCOFFSET_SUFFIX
);
2780 fprintf (stream
, "add.d ");
2781 assemble_name (stream
, name
);
2782 fprintf (stream
, "%s,$pc\n", CRIS_PLT_PCOFFSET_SUFFIX
);
2787 fprintf (stream
, "jump ");
2788 assemble_name (stream
, XSTR (XEXP (DECL_RTL (funcdecl
), 0), 0));
2789 fprintf (stream
, "\n");
2792 fprintf (stream
, "\tnop\n");
2795 final_end_function ();
2798 /* Boilerplate emitted at start of file.
2800 NO_APP *only at file start* means faster assembly. It also means
2801 comments are not allowed. In some cases comments will be output
2802 for debugging purposes. Make sure they are allowed then. */
2804 cris_file_start (void)
2806 /* These expressions can vary at run time, so we cannot put
2807 them into TARGET_INITIALIZER. */
2808 targetm
.asm_file_start_app_off
= !(TARGET_PDEBUG
|| flag_print_asm_name
);
2810 default_file_start ();
2813 /* Output that goes at the end of the file, similarly. */
2816 cris_file_end (void)
2818 /* For CRIS, the default is to assume *no* executable stack, so output
2819 an executable-stack-note only when needed. */
2820 if (TARGET_LINUX
&& trampolines_created
)
2821 file_end_indicate_exec_stack ();
2824 /* Rename the function calls for integer multiply and divide. */
2826 cris_init_libfuncs (void)
2828 set_optab_libfunc (smul_optab
, SImode
, "__Mul");
2829 set_optab_libfunc (sdiv_optab
, SImode
, "__Div");
2830 set_optab_libfunc (udiv_optab
, SImode
, "__Udiv");
2831 set_optab_libfunc (smod_optab
, SImode
, "__Mod");
2832 set_optab_libfunc (umod_optab
, SImode
, "__Umod");
2834 /* Atomic data being unaligned is unfortunately a reality.
2836 if (TARGET_ATOMICS_MAY_CALL_LIBFUNCS
)
2838 set_optab_libfunc (sync_compare_and_swap_optab
, SImode
,
2839 "__cris_atcmpxchgr32");
2840 set_optab_libfunc (sync_compare_and_swap_optab
, HImode
,
2841 "__cris_atcmpxchgr16");
2845 /* The INIT_EXPANDERS worker sets the per-function-data initializer and
2849 cris_init_expanders (void)
2851 /* Nothing here at the moment. */
2854 /* Zero initialization is OK for all current fields. */
2856 static struct machine_function
*
2857 cris_init_machine_status (void)
2859 return ggc_cleared_alloc
<machine_function
> ();
2862 /* Split a 2 word move (DI or presumably DF) into component parts.
2863 Originally a copy of gen_split_move_double in m32r.c. */
2866 cris_split_movdx (rtx
*operands
)
2868 enum machine_mode mode
= GET_MODE (operands
[0]);
2869 rtx dest
= operands
[0];
2870 rtx src
= operands
[1];
2873 /* We used to have to handle (SUBREG (MEM)) here, but that should no
2874 longer happen; after reload there are no SUBREGs any more, and we're
2875 only called after reload. */
2876 CRIS_ASSERT (GET_CODE (dest
) != SUBREG
&& GET_CODE (src
) != SUBREG
);
2881 int dregno
= REGNO (dest
);
2883 /* Reg-to-reg copy. */
2886 int sregno
= REGNO (src
);
2888 int reverse
= (dregno
== sregno
+ 1);
2890 /* We normally copy the low-numbered register first. However, if
2891 the first register operand 0 is the same as the second register of
2892 operand 1, we must copy in the opposite order. */
2893 emit_insn (gen_rtx_SET (VOIDmode
,
2894 operand_subword (dest
, reverse
, TRUE
, mode
),
2895 operand_subword (src
, reverse
, TRUE
, mode
)));
2897 emit_insn (gen_rtx_SET (VOIDmode
,
2898 operand_subword (dest
, !reverse
, TRUE
, mode
),
2899 operand_subword (src
, !reverse
, TRUE
, mode
)));
2901 /* Constant-to-reg copy. */
2902 else if (CONST_INT_P (src
) || GET_CODE (src
) == CONST_DOUBLE
)
2905 split_double (src
, &words
[0], &words
[1]);
2906 emit_insn (gen_rtx_SET (VOIDmode
,
2907 operand_subword (dest
, 0, TRUE
, mode
),
2910 emit_insn (gen_rtx_SET (VOIDmode
,
2911 operand_subword (dest
, 1, TRUE
, mode
),
2914 /* Mem-to-reg copy. */
2915 else if (MEM_P (src
))
2917 /* If the high-address word is used in the address, we must load it
2918 last. Otherwise, load it first. */
2919 rtx addr
= XEXP (src
, 0);
2921 = (refers_to_regno_p (dregno
, dregno
+ 1, addr
, NULL
) != 0);
2923 /* The original code implies that we can't do
2924 move.x [rN+],rM move.x [rN],rM+1
2925 when rN is dead, because of REG_NOTES damage. That is
2926 consistent with what I've seen, so don't try it.
2928 We have two different cases here; if the addr is POST_INC,
2929 just pass it through, otherwise add constants. */
2931 if (GET_CODE (addr
) == POST_INC
)
2936 /* Whenever we emit insns with post-incremented
2937 addresses ourselves, we must add a post-inc note
2939 mem
= change_address (src
, SImode
, addr
);
2941 = gen_rtx_SET (VOIDmode
,
2942 operand_subword (dest
, 0, TRUE
, mode
), mem
);
2943 insn
= emit_insn (insn
);
2944 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2946 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2949 mem
= copy_rtx (mem
);
2951 = gen_rtx_SET (VOIDmode
,
2952 operand_subword (dest
, 1, TRUE
, mode
), mem
);
2953 insn
= emit_insn (insn
);
2954 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
2956 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
2961 /* Make sure we don't get any other addresses with
2962 embedded postincrements. They should be stopped in
2963 GO_IF_LEGITIMATE_ADDRESS, but we're here for your
2965 if (side_effects_p (addr
))
2966 fatal_insn ("unexpected side-effects in address", addr
);
2968 emit_insn (gen_rtx_SET
2970 operand_subword (dest
, reverse
, TRUE
, mode
),
2973 plus_constant (Pmode
, addr
,
2974 reverse
* UNITS_PER_WORD
))));
2975 emit_insn (gen_rtx_SET
2977 operand_subword (dest
, ! reverse
, TRUE
, mode
),
2980 plus_constant (Pmode
, addr
,
2986 internal_error ("unknown src");
2988 /* Reg-to-mem copy or clear mem. */
2989 else if (MEM_P (dest
)
2991 || src
== const0_rtx
2992 || src
== CONST0_RTX (DFmode
)))
2994 rtx addr
= XEXP (dest
, 0);
2996 if (GET_CODE (addr
) == POST_INC
)
3001 /* Whenever we emit insns with post-incremented addresses
3002 ourselves, we must add a post-inc note manually. */
3003 mem
= change_address (dest
, SImode
, addr
);
3005 = gen_rtx_SET (VOIDmode
,
3006 mem
, operand_subword (src
, 0, TRUE
, mode
));
3007 insn
= emit_insn (insn
);
3008 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
3010 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
3013 mem
= copy_rtx (mem
);
3015 = gen_rtx_SET (VOIDmode
,
3017 operand_subword (src
, 1, TRUE
, mode
));
3018 insn
= emit_insn (insn
);
3019 if (GET_CODE (XEXP (mem
, 0)) == POST_INC
)
3021 = alloc_EXPR_LIST (REG_INC
, XEXP (XEXP (mem
, 0), 0),
3026 /* Make sure we don't get any other addresses with embedded
3027 postincrements. They should be stopped in
3028 GO_IF_LEGITIMATE_ADDRESS, but we're here for your safety. */
3029 if (side_effects_p (addr
))
3030 fatal_insn ("unexpected side-effects in address", addr
);
3032 emit_insn (gen_rtx_SET
3034 change_address (dest
, SImode
, addr
),
3035 operand_subword (src
, 0, TRUE
, mode
)));
3037 emit_insn (gen_rtx_SET
3039 change_address (dest
, SImode
,
3040 plus_constant (Pmode
, addr
,
3042 operand_subword (src
, 1, TRUE
, mode
)));
3047 internal_error ("unknown dest");
3054 /* The expander for the prologue pattern name. */
3057 cris_expand_prologue (void)
3060 int size
= get_frame_size ();
3061 /* Shorten the used name for readability. */
3062 int cfoa_size
= crtl
->outgoing_args_size
;
3063 int last_movem_reg
= -1;
3066 int return_address_on_stack
= cris_return_address_on_stack ();
3067 int got_really_used
= false;
3068 int n_movem_regs
= 0;
3069 int pretend
= crtl
->args
.pretend_args_size
;
3071 /* Don't do anything if no prologues or epilogues are wanted. */
3072 if (!TARGET_PROLOGUE_EPILOGUE
)
3075 CRIS_ASSERT (size
>= 0);
3077 if (crtl
->uses_pic_offset_table
)
3079 /* A reference may have been optimized out (like the abort () in
3080 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3082 push_topmost_sequence ();
3084 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL
);
3085 pop_topmost_sequence ();
3088 /* Align the size to what's best for the CPU model. */
3089 if (TARGET_STACK_ALIGN
)
3090 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
3094 /* See also cris_setup_incoming_varargs where
3095 cfun->machine->stdarg_regs is set. There are other setters of
3096 crtl->args.pretend_args_size than stdarg handling, like
3097 for an argument passed with parts in R13 and stack. We must
3098 not store R13 into the pretend-area for that case, as GCC does
3099 that itself. "Our" store would be marked as redundant and GCC
3100 will attempt to remove it, which will then be flagged as an
3101 internal error; trying to remove a frame-related insn. */
3102 int stdarg_regs
= cfun
->machine
->stdarg_regs
;
3104 framesize
+= pretend
;
3106 for (regno
= CRIS_FIRST_ARG_REG
+ CRIS_MAX_ARGS_IN_REGS
- 1;
3108 regno
--, pretend
-= 4, stdarg_regs
--)
3110 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3112 plus_constant (Pmode
,
3115 /* FIXME: When dwarf2 frame output and unless asynchronous
3116 exceptions, make dwarf2 bundle together all stack
3117 adjustments like it does for registers between stack
3119 RTX_FRAME_RELATED_P (insn
) = 1;
3121 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3122 set_mem_alias_set (mem
, get_varargs_alias_set ());
3123 insn
= emit_move_insn (mem
, gen_rtx_raw_REG (SImode
, regno
));
3125 /* Note the absence of RTX_FRAME_RELATED_P on the above insn:
3126 the value isn't restored, so we don't want to tell dwarf2
3127 that it's been stored to stack, else EH handling info would
3131 /* For other setters of crtl->args.pretend_args_size, we
3132 just adjust the stack by leaving the remaining size in
3133 "pretend", handled below. */
3136 /* Save SRP if not a leaf function. */
3137 if (return_address_on_stack
)
3139 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3141 plus_constant (Pmode
, stack_pointer_rtx
,
3144 RTX_FRAME_RELATED_P (insn
) = 1;
3146 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3147 set_mem_alias_set (mem
, get_frame_alias_set ());
3148 insn
= emit_move_insn (mem
, gen_rtx_raw_REG (SImode
, CRIS_SRP_REGNUM
));
3149 RTX_FRAME_RELATED_P (insn
) = 1;
3153 /* Set up the frame pointer, if needed. */
3154 if (frame_pointer_needed
)
3156 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3158 plus_constant (Pmode
, stack_pointer_rtx
,
3161 RTX_FRAME_RELATED_P (insn
) = 1;
3163 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3164 set_mem_alias_set (mem
, get_frame_alias_set ());
3165 insn
= emit_move_insn (mem
, frame_pointer_rtx
);
3166 RTX_FRAME_RELATED_P (insn
) = 1;
3168 insn
= emit_move_insn (frame_pointer_rtx
, stack_pointer_rtx
);
3169 RTX_FRAME_RELATED_P (insn
) = 1;
3174 /* Between frame-pointer and saved registers lie the area for local
3175 variables. If we get here with "pretended" size remaining, count
3176 it into the general stack size. */
3179 /* Get a contiguous sequence of registers, starting with R0, that need
3181 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
3183 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3187 /* Check if movem may be used for registers so far. */
3188 if (regno
== last_movem_reg
+ 1)
3189 /* Yes, update next expected register. */
3190 last_movem_reg
= regno
;
3193 /* We cannot use movem for all registers. We have to flush
3194 any movem:ed registers we got so far. */
3195 if (last_movem_reg
!= -1)
3198 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
3200 /* It is a win to use a side-effect assignment for
3201 64 <= size <= 128. But side-effect on movem was
3202 not usable for CRIS v0..3. Also only do it if
3203 side-effects insns are allowed. */
3204 if ((last_movem_reg
+ 1) * 4 + size
>= 64
3205 && (last_movem_reg
+ 1) * 4 + size
<= 128
3206 && (cris_cpu_version
>= CRIS_CPU_SVINTO
|| n_saved
== 1)
3207 && TARGET_SIDE_EFFECT_PREFIXES
)
3210 = gen_rtx_MEM (SImode
,
3211 plus_constant (Pmode
, stack_pointer_rtx
,
3212 -(n_saved
* 4 + size
)));
3213 set_mem_alias_set (mem
, get_frame_alias_set ());
3215 = cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3216 -(n_saved
* 4 + size
),
3222 = gen_rtx_SET (VOIDmode
,
3224 plus_constant (Pmode
, stack_pointer_rtx
,
3225 -(n_saved
* 4 + size
)));
3226 insn
= emit_insn (insn
);
3227 RTX_FRAME_RELATED_P (insn
) = 1;
3229 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3230 set_mem_alias_set (mem
, get_frame_alias_set ());
3231 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3235 framesize
+= n_saved
* 4 + size
;
3236 last_movem_reg
= -1;
3240 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3242 plus_constant (Pmode
,
3245 RTX_FRAME_RELATED_P (insn
) = 1;
3247 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3248 set_mem_alias_set (mem
, get_frame_alias_set ());
3249 insn
= emit_move_insn (mem
, gen_rtx_raw_REG (SImode
, regno
));
3250 RTX_FRAME_RELATED_P (insn
) = 1;
3252 framesize
+= 4 + size
;
3258 /* Check after, if we could movem all registers. This is the normal case. */
3259 if (last_movem_reg
!= -1)
3262 = (n_movem_regs
== 1) ? 1 : last_movem_reg
+ 1;
3264 /* Side-effect on movem was not usable for CRIS v0..3. Also only
3265 do it if side-effects insns are allowed. */
3266 if ((last_movem_reg
+ 1) * 4 + size
>= 64
3267 && (last_movem_reg
+ 1) * 4 + size
<= 128
3268 && (cris_cpu_version
>= CRIS_CPU_SVINTO
|| n_saved
== 1)
3269 && TARGET_SIDE_EFFECT_PREFIXES
)
3272 = gen_rtx_MEM (SImode
,
3273 plus_constant (Pmode
, stack_pointer_rtx
,
3274 -(n_saved
* 4 + size
)));
3275 set_mem_alias_set (mem
, get_frame_alias_set ());
3276 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
),
3277 -(n_saved
* 4 + size
), true);
3282 = gen_rtx_SET (VOIDmode
,
3284 plus_constant (Pmode
, stack_pointer_rtx
,
3285 -(n_saved
* 4 + size
)));
3286 insn
= emit_insn (insn
);
3287 RTX_FRAME_RELATED_P (insn
) = 1;
3289 mem
= gen_rtx_MEM (SImode
, stack_pointer_rtx
);
3290 set_mem_alias_set (mem
, get_frame_alias_set ());
3291 insn
= cris_emit_movem_store (mem
, GEN_INT (n_saved
), 0, true);
3294 framesize
+= n_saved
* 4 + size
;
3295 /* We have to put outgoing argument space after regs. */
3298 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3300 plus_constant (Pmode
,
3303 RTX_FRAME_RELATED_P (insn
) = 1;
3304 framesize
+= cfoa_size
;
3307 else if ((size
+ cfoa_size
) > 0)
3309 insn
= emit_insn (gen_rtx_SET (VOIDmode
,
3311 plus_constant (Pmode
,
3313 -(cfoa_size
+ size
))));
3314 RTX_FRAME_RELATED_P (insn
) = 1;
3315 framesize
+= size
+ cfoa_size
;
3318 /* Set up the PIC register, if it is used. */
3319 if (got_really_used
)
3322 = gen_rtx_UNSPEC (SImode
, gen_rtvec (1, const0_rtx
), CRIS_UNSPEC_GOT
);
3323 emit_move_insn (pic_offset_table_rtx
, got
);
3325 /* FIXME: This is a cover-up for flow2 messing up; it doesn't
3326 follow exceptional paths and tries to delete the GOT load as
3327 unused, if it isn't used on the non-exceptional paths. Other
3328 ports have similar or other cover-ups, or plain bugs marking
3329 the GOT register load as maybe-dead. To see this, remove the
3330 line below and try libsupc++/vec.cc or a trivial
3331 "static void y (); void x () {try {y ();} catch (...) {}}". */
3332 emit_use (pic_offset_table_rtx
);
3335 if (cris_max_stackframe
&& framesize
> cris_max_stackframe
)
3336 warning (0, "stackframe too big: %d bytes", framesize
);
3339 /* The expander for the epilogue pattern. */
3342 cris_expand_epilogue (void)
3345 int size
= get_frame_size ();
3346 int last_movem_reg
= -1;
3347 int argspace_offset
= crtl
->outgoing_args_size
;
3348 int pretend
= crtl
->args
.pretend_args_size
;
3350 bool return_address_on_stack
= cris_return_address_on_stack ();
3351 /* A reference may have been optimized out
3352 (like the abort () in fde_split in unwind-dw2-fde.c, at least 3.2.1)
3353 so check that it's still used. */
3354 int got_really_used
= false;
3355 int n_movem_regs
= 0;
3357 if (!TARGET_PROLOGUE_EPILOGUE
)
3360 if (crtl
->uses_pic_offset_table
)
3362 /* A reference may have been optimized out (like the abort () in
3363 fde_split in unwind-dw2-fde.c, at least 3.2.1) so check that
3365 push_topmost_sequence ();
3367 = reg_used_between_p (pic_offset_table_rtx
, get_insns (), NULL
);
3368 pop_topmost_sequence ();
3371 /* Align byte count of stack frame. */
3372 if (TARGET_STACK_ALIGN
)
3373 size
= TARGET_ALIGN_BY_32
? (size
+ 3) & ~3 : (size
+ 1) & ~1;
3375 /* Check how many saved regs we can movem. They start at r0 and must
3378 regno
< FIRST_PSEUDO_REGISTER
;
3380 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3384 if (regno
== last_movem_reg
+ 1)
3385 last_movem_reg
= regno
;
3390 /* If there was only one register that really needed to be saved
3391 through movem, don't use movem. */
3392 if (n_movem_regs
== 1)
3393 last_movem_reg
= -1;
3395 /* Now emit "normal" move insns for all regs higher than the movem
3397 for (regno
= FIRST_PSEUDO_REGISTER
- 1;
3398 regno
> last_movem_reg
;
3400 if (cris_reg_saved_in_regsave_area (regno
, got_really_used
))
3404 if (argspace_offset
)
3406 /* There is an area for outgoing parameters located before
3407 the saved registers. We have to adjust for that. */
3408 emit_insn (gen_rtx_SET (VOIDmode
,
3410 plus_constant (Pmode
, stack_pointer_rtx
,
3412 /* Make sure we only do this once. */
3413 argspace_offset
= 0;
3416 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
3417 stack_pointer_rtx
));
3418 set_mem_alias_set (mem
, get_frame_alias_set ());
3419 insn
= emit_move_insn (gen_rtx_raw_REG (SImode
, regno
), mem
);
3421 /* Whenever we emit insns with post-incremented addresses
3422 ourselves, we must add a post-inc note manually. */
3424 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3427 /* If we have any movem-restore, do it now. */
3428 if (last_movem_reg
!= -1)
3432 if (argspace_offset
)
3434 emit_insn (gen_rtx_SET (VOIDmode
,
3436 plus_constant (Pmode
, stack_pointer_rtx
,
3438 argspace_offset
= 0;
3441 mem
= gen_rtx_MEM (SImode
,
3442 gen_rtx_POST_INC (SImode
, stack_pointer_rtx
));
3443 set_mem_alias_set (mem
, get_frame_alias_set ());
3445 = emit_insn (cris_gen_movem_load (mem
,
3446 GEN_INT (last_movem_reg
+ 1), 0));
3447 /* Whenever we emit insns with post-incremented addresses
3448 ourselves, we must add a post-inc note manually. */
3449 if (side_effects_p (PATTERN (insn
)))
3451 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3454 /* If we don't clobber all of the allocated stack area (we've already
3455 deallocated saved registers), GCC might want to schedule loads from
3456 the stack to *after* the stack-pointer restore, which introduces an
3457 interrupt race condition. This happened for the initial-value
3458 SRP-restore for g++.dg/eh/registers1.C (noticed by inspection of
3459 other failure for that test). It also happened for the stack slot
3460 for the return value in (one version of)
3461 linux/fs/dcache.c:__d_lookup, at least with "-O2
3462 -fno-omit-frame-pointer". */
3464 /* Restore frame pointer if necessary. */
3465 if (frame_pointer_needed
)
3469 emit_insn (gen_cris_frame_deallocated_barrier ());
3471 emit_move_insn (stack_pointer_rtx
, frame_pointer_rtx
);
3472 mem
= gen_rtx_MEM (SImode
, gen_rtx_POST_INC (SImode
,
3473 stack_pointer_rtx
));
3474 set_mem_alias_set (mem
, get_frame_alias_set ());
3475 insn
= emit_move_insn (frame_pointer_rtx
, mem
);
3477 /* Whenever we emit insns with post-incremented addresses
3478 ourselves, we must add a post-inc note manually. */
3480 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3482 else if ((size
+ argspace_offset
) != 0)
3484 emit_insn (gen_cris_frame_deallocated_barrier ());
3486 /* If there was no frame-pointer to restore sp from, we must
3487 explicitly deallocate local variables. */
3489 /* Handle space for outgoing parameters that hasn't been handled
3491 size
+= argspace_offset
;
3493 emit_insn (gen_rtx_SET (VOIDmode
,
3495 plus_constant (Pmode
, stack_pointer_rtx
, size
)));
3498 /* If this function has no pushed register parameters
3499 (stdargs/varargs), and if it is not a leaf function, then we have
3500 the return address on the stack. */
3501 if (return_address_on_stack
&& pretend
== 0)
3503 if (TARGET_V32
|| crtl
->calls_eh_return
)
3507 rtx srpreg
= gen_rtx_raw_REG (SImode
, CRIS_SRP_REGNUM
);
3508 mem
= gen_rtx_MEM (SImode
,
3509 gen_rtx_POST_INC (SImode
,
3510 stack_pointer_rtx
));
3511 set_mem_alias_set (mem
, get_frame_alias_set ());
3512 insn
= emit_move_insn (srpreg
, mem
);
3514 /* Whenever we emit insns with post-incremented addresses
3515 ourselves, we must add a post-inc note manually. */
3517 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3519 if (crtl
->calls_eh_return
)
3520 emit_insn (gen_addsi3 (stack_pointer_rtx
,
3522 gen_rtx_raw_REG (SImode
,
3523 CRIS_STACKADJ_REG
)));
3524 cris_expand_return (false);
3527 cris_expand_return (true);
3532 /* If we pushed some register parameters, then adjust the stack for
3536 /* If SRP is stored on the way, we need to restore it first. */
3537 if (return_address_on_stack
)
3540 rtx srpreg
= gen_rtx_raw_REG (SImode
, CRIS_SRP_REGNUM
);
3543 mem
= gen_rtx_MEM (SImode
,
3544 gen_rtx_POST_INC (SImode
,
3545 stack_pointer_rtx
));
3546 set_mem_alias_set (mem
, get_frame_alias_set ());
3547 insn
= emit_move_insn (srpreg
, mem
);
3549 /* Whenever we emit insns with post-incremented addresses
3550 ourselves, we must add a post-inc note manually. */
3552 = alloc_EXPR_LIST (REG_INC
, stack_pointer_rtx
, REG_NOTES (insn
));
3555 emit_insn (gen_rtx_SET (VOIDmode
,
3557 plus_constant (Pmode
, stack_pointer_rtx
,
3561 /* Perform the "physical" unwinding that the EH machinery calculated. */
3562 if (crtl
->calls_eh_return
)
3563 emit_insn (gen_addsi3 (stack_pointer_rtx
,
3565 gen_rtx_raw_REG (SImode
,
3566 CRIS_STACKADJ_REG
)));
3567 cris_expand_return (false);
3570 /* Worker function for generating movem from mem for load_multiple. */
3573 cris_gen_movem_load (rtx src
, rtx nregs_rtx
, int nprefix
)
3575 int nregs
= INTVAL (nregs_rtx
);
3579 rtx srcreg
= XEXP (src
, 0);
3580 unsigned int regno
= nregs
- 1;
3589 if (GET_CODE (srcreg
) == POST_INC
)
3590 srcreg
= XEXP (srcreg
, 0);
3592 CRIS_ASSERT (REG_P (srcreg
));
3594 /* Don't use movem for just one insn. The insns are equivalent except
3595 for the pipeline hazard (on v32); movem does not forward the loaded
3596 registers so there's a three cycles penalty for their use. */
3598 return gen_movsi (gen_rtx_REG (SImode
, 0), src
);
3600 vec
= rtvec_alloc (nprefix
+ nregs
3601 + (GET_CODE (XEXP (src
, 0)) == POST_INC
));
3603 if (GET_CODE (XEXP (src
, 0)) == POST_INC
)
3605 RTVEC_ELT (vec
, nprefix
+ 1)
3606 = gen_rtx_SET (VOIDmode
, srcreg
,
3607 plus_constant (Pmode
, srcreg
, nregs
* 4));
3611 src
= replace_equiv_address (src
, srcreg
);
3612 RTVEC_ELT (vec
, nprefix
)
3613 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, regno
), src
);
3616 for (i
= 1; i
< nregs
; i
++, eltno
++)
3618 RTVEC_ELT (vec
, nprefix
+ eltno
)
3619 = gen_rtx_SET (VOIDmode
, gen_rtx_REG (SImode
, regno
),
3620 adjust_address_nv (src
, SImode
, i
* 4));
3624 return gen_rtx_PARALLEL (VOIDmode
, vec
);
3627 /* Worker function for generating movem to mem. If FRAME_RELATED, notes
3628 are added that the dwarf2 machinery understands. */
3631 cris_emit_movem_store (rtx dest
, rtx nregs_rtx
, int increment
,
3634 int nregs
= INTVAL (nregs_rtx
);
3639 rtx destreg
= XEXP (dest
, 0);
3640 unsigned int regno
= nregs
- 1;
3649 if (GET_CODE (destreg
) == POST_INC
)
3650 increment
+= nregs
* 4;
3652 if (GET_CODE (destreg
) == POST_INC
|| GET_CODE (destreg
) == PLUS
)
3653 destreg
= XEXP (destreg
, 0);
3655 CRIS_ASSERT (REG_P (destreg
));
3657 /* Don't use movem for just one insn. The insns are equivalent except
3658 for the pipeline hazard (on v32); movem does not forward the loaded
3659 registers so there's a three cycles penalty for use. */
3662 rtx mov
= gen_rtx_SET (VOIDmode
, dest
, gen_rtx_REG (SImode
, 0));
3666 insn
= emit_insn (mov
);
3668 RTX_FRAME_RELATED_P (insn
) = 1;
3672 /* If there was a request for a side-effect, create the ordinary
3674 vec
= rtvec_alloc (2);
3676 RTVEC_ELT (vec
, 0) = mov
;
3677 RTVEC_ELT (vec
, 1) = gen_rtx_SET (VOIDmode
, destreg
,
3678 plus_constant (Pmode
, destreg
,
3682 RTX_FRAME_RELATED_P (mov
) = 1;
3683 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3688 vec
= rtvec_alloc (nregs
+ (increment
!= 0 ? 1 : 0));
3690 = gen_rtx_SET (VOIDmode
,
3691 replace_equiv_address (dest
,
3692 plus_constant (Pmode
, destreg
,
3694 gen_rtx_REG (SImode
, regno
));
3697 /* The dwarf2 info wants this mark on each component in a parallel
3698 that's part of the prologue (though it's optional on the first
3701 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 0)) = 1;
3706 = gen_rtx_SET (VOIDmode
, destreg
,
3707 plus_constant (Pmode
, destreg
,
3709 ? increment
: nregs
* 4));
3713 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, 1)) = 1;
3715 /* Don't call adjust_address_nv on a post-incremented address if
3717 if (GET_CODE (XEXP (dest
, 0)) == POST_INC
)
3718 dest
= replace_equiv_address (dest
, destreg
);
3721 for (i
= 1; i
< nregs
; i
++, eltno
++)
3723 RTVEC_ELT (vec
, eltno
)
3724 = gen_rtx_SET (VOIDmode
, adjust_address_nv (dest
, SImode
, i
* 4),
3725 gen_rtx_REG (SImode
, regno
));
3727 RTX_FRAME_RELATED_P (RTVEC_ELT (vec
, eltno
)) = 1;
3732 insn
= emit_insn (gen_rtx_PARALLEL (VOIDmode
, vec
));
3734 /* Because dwarf2out.c handles the insns in a parallel as a sequence,
3735 we need to keep the stack adjustment separate, after the
3736 MEM-setters. Else the stack-adjustment in the second component of
3737 the parallel would be mishandled; the offsets for the SETs that
3738 follow it would be wrong. We prepare for this by adding a
3739 REG_FRAME_RELATED_EXPR with the MEM-setting parts in a SEQUENCE
3740 followed by the increment. Note that we have FRAME_RELATED_P on
3741 all the SETs, including the original stack adjustment SET in the
3747 rtx seq
= gen_rtx_SEQUENCE (VOIDmode
, rtvec_alloc (nregs
+ 1));
3748 XVECEXP (seq
, 0, 0) = copy_rtx (XVECEXP (PATTERN (insn
), 0, 0));
3749 for (i
= 1; i
< nregs
; i
++)
3751 = copy_rtx (XVECEXP (PATTERN (insn
), 0, i
+ 1));
3752 XVECEXP (seq
, 0, nregs
) = copy_rtx (XVECEXP (PATTERN (insn
), 0, 1));
3753 add_reg_note (insn
, REG_FRAME_RELATED_EXPR
, seq
);
3756 RTX_FRAME_RELATED_P (insn
) = 1;
3762 /* Worker function for expanding the address for PIC function calls. */
3765 cris_expand_pic_call_address (rtx
*opp
, rtx
*markerp
)
3769 gcc_assert (flag_pic
&& MEM_P (op
));
3772 /* It might be that code can be generated that jumps to 0 (or to a
3773 specific address). Don't die on that. (There is a
3775 if (CONSTANT_P (op
) && !CONST_INT_P (op
))
3777 enum cris_symbol_type t
= cris_symbol_type_of (op
);
3779 CRIS_ASSERT (can_create_pseudo_p ());
3781 /* For local symbols (non-PLT), just get the plain symbol
3782 reference into a register. For symbols that can be PLT, make
3784 if (t
== cris_rel_symbol
)
3786 /* For v32, we're fine as-is; just PICify the symbol. Forcing
3787 into a register caused performance regression for 3.2.1,
3788 observable in __floatdidf and elsewhere in libgcc. */
3791 rtx sym
= GET_CODE (op
) != CONST
? op
: get_related_value (op
);
3792 HOST_WIDE_INT offs
= get_integer_term (op
);
3794 /* We can't get calls to sym+N, N integer, can we? */
3795 gcc_assert (offs
== 0);
3797 op
= gen_rtx_CONST (Pmode
,
3798 gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, sym
),
3799 CRIS_UNSPEC_PCREL
));
3802 op
= force_reg (Pmode
, op
);
3805 *markerp
= const0_rtx
;
3807 else if (t
== cris_got_symbol
)
3809 if (TARGET_AVOID_GOTPLT
)
3811 /* Change a "jsr sym" into (allocate register rM, rO)
3812 "move.d (const (unspec [sym] CRIS_UNSPEC_PLT_GOTREL)),rM"
3813 "add.d rPIC,rM,rO", "jsr rO" for pre-v32 and
3814 "jsr (const (unspec [sym] CRIS_UNSPEC_PLT_PCREL))"
3818 crtl
->uses_pic_offset_table
= 1;
3819 tem
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
),
3821 ? CRIS_UNSPEC_PLT_PCREL
3822 : CRIS_UNSPEC_PLT_GOTREL
);
3823 tem
= gen_rtx_CONST (Pmode
, tem
);
3828 rm
= gen_reg_rtx (Pmode
);
3829 emit_move_insn (rm
, tem
);
3830 ro
= gen_reg_rtx (Pmode
);
3831 if (expand_binop (Pmode
, add_optab
, rm
,
3832 pic_offset_table_rtx
,
3833 ro
, 0, OPTAB_LIB_WIDEN
) != ro
)
3834 internal_error ("expand_binop failed in movsi got");
3840 /* Change a "jsr sym" into (allocate register rM, rO)
3841 "move.d (const (unspec [sym] CRIS_UNSPEC_PLTGOTREAD)),rM"
3842 "add.d rPIC,rM,rO" "jsr [rO]" with the memory access
3843 marked as not trapping and not aliasing. No "move.d
3844 [rO],rP" as that would invite to re-use of a value
3845 that should not be reused. FIXME: Need a peephole2
3846 for cases when this is cse:d from the call, to change
3847 back to just get the PLT entry address, so we don't
3848 resolve the same symbol over and over (the memory
3849 access of the PLTGOT isn't constant). */
3850 rtx tem
, mem
, rm
, ro
;
3852 gcc_assert (can_create_pseudo_p ());
3853 crtl
->uses_pic_offset_table
= 1;
3854 tem
= gen_rtx_UNSPEC (Pmode
, gen_rtvec (1, op
),
3855 CRIS_UNSPEC_PLTGOTREAD
);
3856 rm
= gen_reg_rtx (Pmode
);
3857 emit_move_insn (rm
, gen_rtx_CONST (Pmode
, tem
));
3858 ro
= gen_reg_rtx (Pmode
);
3859 if (expand_binop (Pmode
, add_optab
, rm
,
3860 pic_offset_table_rtx
,
3861 ro
, 0, OPTAB_LIB_WIDEN
) != ro
)
3862 internal_error ("expand_binop failed in movsi got");
3863 mem
= gen_rtx_MEM (Pmode
, ro
);
3865 /* This MEM doesn't alias anything. Whether it aliases
3866 other same symbols is unimportant. */
3867 set_mem_alias_set (mem
, new_alias_set ());
3868 MEM_NOTRAP_P (mem
) = 1;
3872 /* We need to prepare this call to go through the PLT; we
3873 need to make GOT available. */
3874 *markerp
= pic_offset_table_rtx
;
3877 /* Can't possibly get anything else for a function-call, right? */
3878 fatal_insn ("unidentifiable call op", op
);
3880 /* If the validizing variant is called, it will try to validize
3881 the address as a valid any-operand constant, but as it's only
3882 valid for calls and moves, it will fail and always be forced
3884 *opp
= replace_equiv_address_nv (*opp
, op
);
3887 /* Can't tell what locality a call to a non-constant address has;
3888 better make the GOT register alive at it.
3889 FIXME: Can we see whether the register has known constant
3891 *markerp
= pic_offset_table_rtx
;
3894 /* Make sure operands are in the right order for an addsi3 insn as
3895 generated by a define_split. Nothing but REG_P as the first
3896 operand is recognized by addsi3 after reload. OPERANDS contains
3897 the operands, with the first at OPERANDS[N] and the second at
3901 cris_order_for_addsi3 (rtx
*operands
, int n
)
3903 if (!REG_P (operands
[n
]))
3905 rtx tem
= operands
[n
];
3906 operands
[n
] = operands
[n
+ 1];
3907 operands
[n
+ 1] = tem
;
3911 /* Use from within code, from e.g. PRINT_OPERAND and
3912 PRINT_OPERAND_ADDRESS. Macros used in output_addr_const need to emit
3913 different things depending on whether code operand or constant is
3917 cris_output_addr_const (FILE *file
, rtx x
)
3920 output_addr_const (file
, x
);
3924 /* Worker function for ASM_OUTPUT_SYMBOL_REF. */
3927 cris_asm_output_symbol_ref (FILE *file
, rtx x
)
3929 gcc_assert (GET_CODE (x
) == SYMBOL_REF
);
3931 if (flag_pic
&& in_code
> 0)
3933 const char *origstr
= XSTR (x
, 0);
3935 str
= (* targetm
.strip_name_encoding
) (origstr
);
3936 assemble_name (file
, str
);
3939 if (!TARGET_V32
&& !crtl
->uses_pic_offset_table
)
3940 output_operand_lossage ("PIC register isn't set up");
3943 assemble_name (file
, XSTR (x
, 0));
3946 /* Worker function for ASM_OUTPUT_LABEL_REF. */
3949 cris_asm_output_label_ref (FILE *file
, char *buf
)
3951 if (flag_pic
&& in_code
> 0)
3953 assemble_name (file
, buf
);
3956 if (!TARGET_V32
&& !crtl
->uses_pic_offset_table
)
3957 internal_error ("emitting PIC operand, but PIC register "
3961 assemble_name (file
, buf
);
3964 /* Worker function for TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
3967 cris_output_addr_const_extra (FILE *file
, rtx xconst
)
3969 switch (GET_CODE (xconst
))
3974 x
= XVECEXP (xconst
, 0, 0);
3975 CRIS_ASSERT (GET_CODE (x
) == SYMBOL_REF
3976 || GET_CODE (x
) == LABEL_REF
3977 || GET_CODE (x
) == CONST
);
3978 output_addr_const (file
, x
);
3979 switch (XINT (xconst
, 1))
3981 case CRIS_UNSPEC_PCREL
:
3982 /* We only get this with -fpic/PIC to tell it apart from an
3983 invalid symbol. We can't tell here, but it should only
3984 be the operand of a call or movsi. */
3985 gcc_assert (TARGET_V32
&& flag_pic
);
3988 case CRIS_UNSPEC_PLT_PCREL
:
3989 gcc_assert (TARGET_V32
);
3990 fprintf (file
, ":PLT");
3993 case CRIS_UNSPEC_PLT_GOTREL
:
3994 gcc_assert (!TARGET_V32
);
3995 fprintf (file
, ":PLTG");
3998 case CRIS_UNSPEC_GOTREL
:
3999 gcc_assert (!TARGET_V32
);
4000 fprintf (file
, ":GOTOFF");
4003 case CRIS_UNSPEC_GOTREAD
:
4005 fprintf (file
, ":GOT16");
4007 fprintf (file
, ":GOT");
4010 case CRIS_UNSPEC_PLTGOTREAD
:
4012 fprintf (file
, CRIS_GOTPLT_SUFFIX
"16");
4014 fprintf (file
, CRIS_GOTPLT_SUFFIX
);
4027 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
4030 cris_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
4031 int incoming ATTRIBUTE_UNUSED
)
4033 return gen_rtx_REG (Pmode
, CRIS_STRUCT_VALUE_REGNUM
);
4036 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
4039 cris_setup_incoming_varargs (cumulative_args_t ca_v
,
4040 enum machine_mode mode ATTRIBUTE_UNUSED
,
4041 tree type ATTRIBUTE_UNUSED
,
4042 int *pretend_arg_size
,
4045 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
4047 if (ca
->regs
< CRIS_MAX_ARGS_IN_REGS
)
4049 int stdarg_regs
= CRIS_MAX_ARGS_IN_REGS
- ca
->regs
;
4050 cfun
->machine
->stdarg_regs
= stdarg_regs
;
4051 *pretend_arg_size
= stdarg_regs
* 4;
4055 fprintf (asm_out_file
,
4056 "\n; VA:: ANSI: %d args before, anon @ #%d, %dtime\n",
4057 ca
->regs
, *pretend_arg_size
, second_time
);
4060 /* Return true if TYPE must be passed by invisible reference.
4061 For cris, we pass <= 8 bytes by value, others by reference. */
4064 cris_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED
,
4065 enum machine_mode mode
, const_tree type
,
4066 bool named ATTRIBUTE_UNUSED
)
4068 return (targetm
.calls
.must_pass_in_stack (mode
, type
)
4069 || CRIS_FUNCTION_ARG_SIZE (mode
, type
) > 8);
4072 /* A combination of defining TARGET_PROMOTE_FUNCTION_MODE, promoting arguments
4073 and *not* defining TARGET_PROMOTE_PROTOTYPES or PROMOTE_MODE gives the
4074 best code size and speed for gcc, ipps and products in gcc-2.7.2. */
4077 cris_promote_function_mode (const_tree type ATTRIBUTE_UNUSED
,
4078 enum machine_mode mode
,
4079 int *punsignedp ATTRIBUTE_UNUSED
,
4080 const_tree fntype ATTRIBUTE_UNUSED
,
4083 /* Defining PROMOTE_FUNCTION_RETURN in gcc-2.7.2 uncovered bug 981110 (even
4084 when modifying TARGET_FUNCTION_VALUE to return the promoted mode).
4085 Maybe pointless as of now, but let's keep the old behavior. */
4086 if (for_return
== 1)
4088 return CRIS_PROMOTED_MODE (mode
, *punsignedp
, type
);
4091 /* Atomic types require alignment to be at least their "natural" size. */
4094 cris_atomic_align_for_mode (enum machine_mode mode
)
4096 return GET_MODE_BITSIZE (mode
);
4099 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4103 cris_function_value(const_tree type
,
4104 const_tree func ATTRIBUTE_UNUSED
,
4105 bool outgoing ATTRIBUTE_UNUSED
)
4107 return gen_rtx_REG (TYPE_MODE (type
), CRIS_FIRST_ARG_REG
);
4110 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4114 cris_libcall_value (enum machine_mode mode
,
4115 const_rtx fun ATTRIBUTE_UNUSED
)
4117 return gen_rtx_REG (mode
, CRIS_FIRST_ARG_REG
);
4120 /* Let's assume all functions return in r[CRIS_FIRST_ARG_REG] for the
4124 cris_function_value_regno_p (const unsigned int regno
)
4126 return (regno
== CRIS_FIRST_ARG_REG
);
4130 cris_arg_partial_bytes (cumulative_args_t ca
, enum machine_mode mode
,
4131 tree type
, bool named ATTRIBUTE_UNUSED
)
4133 if (get_cumulative_args (ca
)->regs
== CRIS_MAX_ARGS_IN_REGS
- 1
4134 && !targetm
.calls
.must_pass_in_stack (mode
, type
)
4135 && CRIS_FUNCTION_ARG_SIZE (mode
, type
) > 4
4136 && CRIS_FUNCTION_ARG_SIZE (mode
, type
) <= 8)
4137 return UNITS_PER_WORD
;
4143 cris_function_arg_1 (cumulative_args_t ca_v
,
4144 enum machine_mode mode ATTRIBUTE_UNUSED
,
4145 const_tree type ATTRIBUTE_UNUSED
,
4146 bool named
, bool incoming
)
4148 const CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
4150 if ((!incoming
|| named
) && ca
->regs
< CRIS_MAX_ARGS_IN_REGS
)
4151 return gen_rtx_REG (mode
, CRIS_FIRST_ARG_REG
+ ca
->regs
);
4156 /* Worker function for TARGET_FUNCTION_ARG.
4157 The void_type_node is sent as a "closing" call. */
4160 cris_function_arg (cumulative_args_t ca
, enum machine_mode mode
,
4161 const_tree type
, bool named
)
4163 return cris_function_arg_1 (ca
, mode
, type
, named
, false);
4166 /* Worker function for TARGET_FUNCTION_INCOMING_ARG.
4168 The differences between this and the previous, is that this one checks
4169 that an argument is named, since incoming stdarg/varargs arguments are
4170 pushed onto the stack, and we don't have to check against the "closing"
4171 void_type_node TYPE parameter. */
4174 cris_function_incoming_arg (cumulative_args_t ca
, enum machine_mode mode
,
4175 const_tree type
, bool named
)
4177 return cris_function_arg_1 (ca
, mode
, type
, named
, true);
4180 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE. */
4183 cris_function_arg_advance (cumulative_args_t ca_v
, enum machine_mode mode
,
4184 const_tree type
, bool named ATTRIBUTE_UNUSED
)
4186 CUMULATIVE_ARGS
*ca
= get_cumulative_args (ca_v
);
4188 ca
->regs
+= (3 + CRIS_FUNCTION_ARG_SIZE (mode
, type
)) / 4;
4191 /* Worker function for TARGET_MD_ASM_CLOBBERS. */
4194 cris_md_asm_clobbers (tree outputs
, tree inputs
, tree in_clobbers
)
4196 HARD_REG_SET mof_set
;
4200 CLEAR_HARD_REG_SET (mof_set
);
4201 SET_HARD_REG_BIT (mof_set
, CRIS_MOF_REGNUM
);
4203 /* For the time being, all asms clobber condition codes. Revisit when
4204 there's a reasonable use for inputs/outputs that mention condition
4207 = tree_cons (NULL_TREE
,
4208 build_string (strlen (reg_names
[CRIS_CC0_REGNUM
]),
4209 reg_names
[CRIS_CC0_REGNUM
]),
4212 for (t
= outputs
; t
!= NULL
; t
= TREE_CHAIN (t
))
4214 tree val
= TREE_VALUE (t
);
4216 /* The constraint letter for the singleton register class of MOF
4217 is 'h'. If it's mentioned in the constraints, the asm is
4218 MOF-aware and adding it to the clobbers would cause it to have
4219 impossible constraints. */
4220 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t
))),
4222 || tree_overlaps_hard_reg_set (val
, &mof_set
) != NULL_TREE
)
4226 for (t
= inputs
; t
!= NULL
; t
= TREE_CHAIN (t
))
4228 tree val
= TREE_VALUE (t
);
4230 if (strchr (TREE_STRING_POINTER (TREE_VALUE (TREE_PURPOSE (t
))),
4232 || tree_overlaps_hard_reg_set (val
, &mof_set
) != NULL_TREE
)
4236 return tree_cons (NULL_TREE
,
4237 build_string (strlen (reg_names
[CRIS_MOF_REGNUM
]),
4238 reg_names
[CRIS_MOF_REGNUM
]),
4242 /* Implement TARGET_FRAME_POINTER_REQUIRED.
4244 Really only needed if the stack frame has variable length (alloca
4245 or variable sized local arguments (GNU C extension). See PR39499 and
4246 PR38609 for the reason this isn't just 0. */
4249 cris_frame_pointer_required (void)
4251 return !crtl
->sp_is_unchanging
;
4254 /* Implement TARGET_ASM_TRAMPOLINE_TEMPLATE.
4256 This looks too complicated, and it is. I assigned r7 to be the
4257 static chain register, but it is call-saved, so we have to save it,
4258 and come back to restore it after the call, so we have to save srp...
4259 Anyway, trampolines are rare enough that we can cope with this
4260 somewhat lack of elegance.
4261 (Do not be tempted to "straighten up" whitespace in the asms; the
4262 assembler #NO_APP state mandates strict spacing). */
4263 /* ??? See the i386 regparm=3 implementation that pushes the static
4264 chain value to the stack in the trampoline, and uses a call-saved
4265 register when called directly. */
4268 cris_asm_trampoline_template (FILE *f
)
4272 /* This normally-unused nop insn acts as an instruction to
4273 the simulator to flush its instruction cache. None of
4274 the other instructions in the trampoline template suits
4275 as a trigger for V32. The pc-relative addressing mode
4276 works nicely as a trigger for V10.
4277 FIXME: Have specific V32 template (possibly avoiding the
4278 use of a special instruction). */
4279 fprintf (f
, "\tclearf x\n");
4280 /* We have to use a register as an intermediate, choosing
4281 semi-randomly R1 (which has to not be the STATIC_CHAIN_REGNUM),
4282 so we can use it for address indirection and jsr target. */
4283 fprintf (f
, "\tmove $r1,$mof\n");
4285 fprintf (f
, "\tmove.d 0,$r1\n");
4286 fprintf (f
, "\tmove.d $%s,[$r1]\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4287 fprintf (f
, "\taddq 6,$r1\n");
4288 fprintf (f
, "\tmove $mof,[$r1]\n");
4289 fprintf (f
, "\taddq 6,$r1\n");
4290 fprintf (f
, "\tmove $srp,[$r1]\n");
4292 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4294 fprintf (f
, "\tmove.d 0,$r1\n");
4295 fprintf (f
, "\tjsr $r1\n");
4296 fprintf (f
, "\tsetf\n");
4298 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4300 fprintf (f
, "\tmove.d 0,$r1\n");
4302 fprintf (f
, "\tmove.d 0,$r9\n");
4303 fprintf (f
, "\tjump $r9\n");
4304 fprintf (f
, "\tsetf\n");
4308 fprintf (f
, "\tmove.d $%s,[$pc+20]\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4309 fprintf (f
, "\tmove $srp,[$pc+22]\n");
4310 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4311 fprintf (f
, "\tjsr 0\n");
4312 fprintf (f
, "\tmove.d 0,$%s\n", reg_names
[STATIC_CHAIN_REGNUM
]);
4313 fprintf (f
, "\tjump 0\n");
4317 /* Implement TARGET_TRAMPOLINE_INIT. */
4320 cris_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
4322 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
4323 rtx tramp
= XEXP (m_tramp
, 0);
4326 emit_block_move (m_tramp
, assemble_trampoline_template (),
4327 GEN_INT (TRAMPOLINE_SIZE
), BLOCK_OP_NORMAL
);
4331 mem
= adjust_address (m_tramp
, SImode
, 6);
4332 emit_move_insn (mem
, plus_constant (Pmode
, tramp
, 38));
4333 mem
= adjust_address (m_tramp
, SImode
, 22);
4334 emit_move_insn (mem
, chain_value
);
4335 mem
= adjust_address (m_tramp
, SImode
, 28);
4336 emit_move_insn (mem
, fnaddr
);
4340 mem
= adjust_address (m_tramp
, SImode
, 10);
4341 emit_move_insn (mem
, chain_value
);
4342 mem
= adjust_address (m_tramp
, SImode
, 16);
4343 emit_move_insn (mem
, fnaddr
);
4346 /* Note that there is no need to do anything with the cache for
4347 sake of a trampoline. */
4352 /* Various small functions to replace macros. Only called from a
4353 debugger. They might collide with gcc functions or system functions,
4354 so only emit them when '#if 1' above. */
4356 enum rtx_code
Get_code (rtx
);
4361 return GET_CODE (x
);
4364 const char *Get_mode (rtx
);
4369 return GET_MODE_NAME (GET_MODE (x
));
4372 rtx
Xexp (rtx
, int);
4380 rtx
Xvecexp (rtx
, int, int);
4383 Xvecexp (rtx x
, int n
, int m
)
4385 return XVECEXP (x
, n
, m
);
4388 int Get_rtx_len (rtx
);
4393 return GET_RTX_LENGTH (GET_CODE (x
));
4396 /* Use upper-case to distinguish from local variables that are sometimes
4397 called next_insn and prev_insn. */
4399 rtx
Next_insn (rtx
);
4402 Next_insn (rtx insn
)
4404 return NEXT_INSN (insn
);
4407 rtx
Prev_insn (rtx
);
4410 Prev_insn (rtx insn
)
4412 return PREV_INSN (insn
);
4416 #include "gt-cris.h"
4420 * eval: (c-set-style "gnu")
4421 * indent-tabs-mode: t