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* config/arm/arm.c (TARGET_SETUP_INCOMING_VARARGS): New.
[official-gcc.git] / gcc / config / c4x / c4x.h
blobaa80ffbd17075572fb492d6d42426ee14dac5282
1 /* Definitions of target machine for GNU compiler. TMS320C[34]x
2 Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003 Free Software Foundation, Inc.
4
5 Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
6 and Herman Ten Brugge (Haj.Ten.Brugge@net.HCC.nl).
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
24
25 /* RUN-TIME TARGET SPECIFICATION. */
26
27 #define C4x 1
28
29 #define TARGET_CPU_CPP_BUILTINS() \
30 do \
31 { \
32 /* ??? HACK. We shouldn't have flag_inline_trees at all. */ \
33 extern int flag_inline_trees; \
34 if (!TARGET_SMALL) \
35 builtin_define ("_BIGMODEL"); \
36 if (!TARGET_MEMPARM) \
37 builtin_define ("_REGPARM"); \
38 if (flag_inline_functions \
39 || flag_inline_trees) \
40 builtin_define ("_INLINE"); \
41 if (TARGET_C3X) \
42 { \
43 builtin_define ("_TMS320C3x"); \
44 builtin_define ("_C3x"); \
45 if (TARGET_C30) \
46 { \
47 builtin_define ("_TMS320C30"); \
48 builtin_define ("_C30"); \
49 } \
50 else if (TARGET_C31) \
51 { \
52 builtin_define ("_TMS320C31"); \
53 builtin_define ("_C31"); \
54 } \
55 else if (TARGET_C32) \
56 { \
57 builtin_define ("_TMS320C32"); \
58 builtin_define ("_C32"); \
59 } \
60 else if (TARGET_C33) \
61 { \
62 builtin_define ("_TMS320C33"); \
63 builtin_define ("_C33"); \
64 } \
65 } \
66 else \
67 { \
68 builtin_define ("_TMS320C4x"); \
69 builtin_define ("_C4x"); \
70 if (TARGET_C40) \
71 { \
72 builtin_define ("_TMS320C40"); \
73 builtin_define ("_C40"); \
74 } \
75 else if (TARGET_C44) \
76 { \
77 builtin_define ("_TMS320C44"); \
78 builtin_define ("_C44"); \
79 } \
80 } \
81 } \
82 while (0)
83
84 /* Name of the c4x assembler. */
85
86 #define ASM_PROG "c4x-as"
87
88 /* Name of the c4x linker. */
89
90 #define LD_PROG "c4x-ld"
91
92 /* Define assembler options. */
93
94 #define ASM_SPEC "\
95 %{!mcpu=30:%{!mcpu=31:%{!mcpu=32:%{!mcpu=33:%{!mcpu=40:%{!mcpu=44:\
96 %{!m30:%{!m31:%{!m32:%{!m33:%{!m40:%{!m44:-m40}}}}}}}}}}}} \
97 %{mcpu=30} \
98 %{mcpu=31} \
99 %{mcpu=32} \
100 %{mcpu=33} \
101 %{mcpu=40} \
102 %{mcpu=44} \
103 %{m30} \
104 %{m31} \
105 %{m32} \
106 %{m33} \
107 %{m40} \
108 %{m44} \
109 %{mmemparm} %{mregparm} %{!mmemparm:%{!mregparm:-mregparm}} \
110 %{mbig} %{msmall} %{!msmall:%{!mbig:-mbig}}"
111
112 /* Define linker options. */
113
114 #define LINK_SPEC "\
115 %{m30:--architecture c3x} \
116 %{m31:--architecture c3x} \
117 %{m32:--architecture c3x} \
118 %{m33:--architecture c3x} \
119 %{mcpu=30:--architecture c3x} \
120 %{mcpu=31:--architecture c3x} \
121 %{mcpu=32:--architecture c3x} \
122 %{mcpu=33:--architecture c3x}"
123
124 /* Specify the end file to link with. */
125
126 #define ENDFILE_SPEC ""
127
128 /* Target compilation option flags. */
129
130 #define SMALL_MEMORY_FLAG 0x0000001 /* Small memory model. */
131 #define MPYI_FLAG 0x0000002 /* Use 24-bit MPYI for C3x. */
132 #define FAST_FIX_FLAG 0x0000004 /* Fast fixing of floats. */
133 #define RPTS_FLAG 0x0000008 /* Allow use of RPTS. */
134 #define C3X_FLAG 0x0000010 /* Emit C3x code. */
135 #define TI_FLAG 0x0000020 /* Be compatible with TI assembler. */
136 #define PARANOID_FLAG 0x0000040 /* Be paranoid about DP reg. in ISRs. */
137 #define MEMPARM_FLAG 0x0000080 /* Pass arguments on stack. */
138 #define DEVEL_FLAG 0x0000100 /* Enable features under development. */
139 #define RPTB_FLAG 0x0000200 /* Enable repeat block. */
140 #define BK_FLAG 0x0000400 /* Use BK as general register. */
141 #define DB_FLAG 0x0000800 /* Use decrement and branch for C3x. */
142 #define DEBUG_FLAG 0x0001000 /* Enable debugging of GCC. */
143 #define HOIST_FLAG 0x0002000 /* Force constants into registers. */
144 #define LOOP_UNSIGNED_FLAG 0x0004000 /* Allow unsigned loop counters. */
145 #define FORCE_FLAG 0x0008000 /* Force op0 and op1 to be same. */
146 #define PRESERVE_FLOAT_FLAG 0x0010000 /* Save all 40 bits for floats. */
147 #define PARALLEL_INSN_FLAG 0x0020000 /* Allow parallel insns. */
148 #define PARALLEL_MPY_FLAG 0x0040000 /* Allow MPY||ADD, MPY||SUB insns. */
149 #define ALIASES_FLAG 0x0080000 /* Assume mem refs possibly aliased. */
150
151 #define C30_FLAG 0x0100000 /* Emit C30 code. */
152 #define C31_FLAG 0x0200000 /* Emit C31 code. */
153 #define C32_FLAG 0x0400000 /* Emit C32 code. */
154 #define C33_FLAG 0x0800000 /* Emit C33 code. */
155 #define C40_FLAG 0x1000000 /* Emit C40 code. */
156 #define C44_FLAG 0x2000000 /* Emit C44 code. */
157
158 /* Run-time compilation parameters selecting different hardware subsets.
159
160 Macro to define tables used to set the flags.
161 This is a list in braces of triplets in braces,
162 each pair being { "NAME", VALUE, "DESCRIPTION" }
163 where VALUE is the bits to set or minus the bits to clear.
164 An empty string NAME is used to identify the default VALUE. */
165
166 #define TARGET_SWITCHES \
167 { { "small", SMALL_MEMORY_FLAG, \
168 N_("Small memory model") }, \
169 { "big", -SMALL_MEMORY_FLAG, \
170 N_("Big memory model") }, \
171 { "mpyi", MPYI_FLAG, \
172 N_("Use MPYI instruction for C3x") }, \
173 { "no-mpyi", -MPYI_FLAG, \
174 N_("Do not use MPYI instruction for C3x") }, \
175 { "fast-fix", FAST_FIX_FLAG, \
176 N_("Use fast but approximate float to integer conversion") }, \
177 { "no-fast-fix", -FAST_FIX_FLAG, \
178 N_("Use slow but accurate float to integer conversion") }, \
179 { "rpts", RPTS_FLAG, \
180 N_("Enable use of RTPS instruction") }, \
181 { "no-rpts", -RPTS_FLAG, \
182 N_("Disable use of RTPS instruction") }, \
183 { "rptb", RPTB_FLAG, \
184 N_("Enable use of RTPB instruction") }, \
185 { "no-rptb", -RPTB_FLAG, \
186 N_("Disable use of RTPB instruction") }, \
187 { "30", C30_FLAG, \
188 N_("Generate code for C30 CPU")}, \
189 { "31", C31_FLAG, \
190 N_("Generate code for C31 CPU")}, \
191 { "32", C32_FLAG, \
192 N_("Generate code for C32 CPU")}, \
193 { "33", C33_FLAG, \
194 N_("Generate code for C33 CPU")}, \
195 { "40", C40_FLAG, \
196 N_("Generate code for C40 CPU")}, \
197 { "44", C44_FLAG, \
198 N_("Generate code for C44 CPU")}, \
199 { "ti", TI_FLAG, \
200 N_("Emit code compatible with TI tools")}, \
201 { "no-ti", -TI_FLAG, \
202 N_("Emit code to use GAS extensions")}, \
203 { "paranoid", PARANOID_FLAG, \
204 N_("Save DP across ISR in small memory model") }, \
205 { "no-paranoid", -PARANOID_FLAG, \
206 N_("Don't save DP across ISR in small memory model") }, \
207 { "isr-dp-reload", PARANOID_FLAG, \
208 N_("Save DP across ISR in small memory model") }, \
209 { "no-isr-dp-reload", -PARANOID_FLAG, \
210 N_("Don't save DP across ISR in small memory model") }, \
211 { "memparm", MEMPARM_FLAG, \
212 N_("Pass arguments on the stack") }, \
213 { "regparm", -MEMPARM_FLAG, \
214 N_("Pass arguments in registers") }, \
215 { "devel", DEVEL_FLAG, \
216 N_("Enable new features under development") }, \
217 { "no-devel", -DEVEL_FLAG, \
218 N_("Disable new features under development") }, \
219 { "bk", BK_FLAG, \
220 N_("Use the BK register as a general purpose register") }, \
221 { "no-bk", -BK_FLAG, \
222 N_("Do not allocate BK register") }, \
223 { "db", DB_FLAG, \
224 N_("Enable use of DB instruction") }, \
225 { "no-db", -DB_FLAG, \
226 N_("Disable use of DB instruction") }, \
227 { "debug", DEBUG_FLAG, \
228 N_("Enable debugging") }, \
229 { "no-debug", -DEBUG_FLAG, \
230 N_("Disable debugging") }, \
231 { "hoist", HOIST_FLAG, \
232 N_("Force constants into registers to improve hoisting") }, \
233 { "no-hoist", -HOIST_FLAG, \
234 N_("Don't force constants into registers") }, \
235 { "force", FORCE_FLAG, \
236 N_("Force RTL generation to emit valid 3 operand insns") }, \
237 { "no-force", -FORCE_FLAG, \
238 N_("Allow RTL generation to emit invalid 3 operand insns") }, \
239 { "loop-unsigned", LOOP_UNSIGNED_FLAG, \
240 N_("Allow unsigned iteration counts for RPTB/DB") }, \
241 { "no-loop-unsigned", -LOOP_UNSIGNED_FLAG, \
242 N_("Disallow unsigned iteration counts for RPTB/DB") }, \
243 { "preserve-float", PRESERVE_FLOAT_FLAG, \
244 N_("Preserve all 40 bits of FP reg across call") }, \
245 { "no-preserve-float", -PRESERVE_FLOAT_FLAG, \
246 N_("Only preserve 32 bits of FP reg across call") }, \
247 { "parallel-insns", PARALLEL_INSN_FLAG, \
248 N_("Enable parallel instructions") }, \
249 { "no-parallel-insns", -PARALLEL_INSN_FLAG, \
250 N_("Disable parallel instructions") }, \
251 { "parallel-mpy", PARALLEL_MPY_FLAG, \
252 N_("Enable MPY||ADD and MPY||SUB instructions") }, \
253 { "no-parallel-mpy", -PARALLEL_MPY_FLAG, \
254 N_("Disable MPY||ADD and MPY||SUB instructions") }, \
255 { "aliases", ALIASES_FLAG, \
256 N_("Assume that pointers may be aliased") }, \
257 { "no-aliases", -ALIASES_FLAG, \
258 N_("Assume that pointers not aliased") }, \
259 { "", TARGET_DEFAULT, ""} }
260
261 /* Default target switches. */
262
263 /* Play safe, not the fastest code. */
264 #define TARGET_DEFAULT ALIASES_FLAG | PARALLEL_INSN_FLAG \
265 | PARALLEL_MPY_FLAG | RPTB_FLAG
266
267 /* Caveats:
268 Max iteration count for RPTB/RPTS is 2^31 + 1.
269 Max iteration count for DB is 2^31 + 1 for C40, but 2^23 + 1 for C30.
270 RPTS blocks interrupts. */
271
272
273 extern int target_flags;
274
275 #define TARGET_INLINE (! optimize_size) /* Inline MPYI. */
276 #define TARGET_SMALL_REG_CLASS 0
277
278 #define TARGET_SMALL (target_flags & SMALL_MEMORY_FLAG)
279 #define TARGET_MPYI (!TARGET_C3X || (target_flags & MPYI_FLAG))
280 #define TARGET_FAST_FIX (target_flags & FAST_FIX_FLAG)
281 #define TARGET_RPTS (target_flags & RPTS_FLAG)
282 #define TARGET_TI (target_flags & TI_FLAG)
283 #define TARGET_PARANOID (target_flags & PARANOID_FLAG)
284 #define TARGET_MEMPARM (target_flags & MEMPARM_FLAG)
285 #define TARGET_DEVEL (target_flags & DEVEL_FLAG)
286 #define TARGET_RPTB (target_flags & RPTB_FLAG \
287 && optimize >= 2)
288 #define TARGET_BK (target_flags & BK_FLAG)
289 #define TARGET_DB (! TARGET_C3X || (target_flags & DB_FLAG))
290 #define TARGET_DEBUG (target_flags & DEBUG_FLAG)
291 #define TARGET_HOIST (target_flags & HOIST_FLAG)
292 #define TARGET_LOOP_UNSIGNED (target_flags & LOOP_UNSIGNED_FLAG)
293 #define TARGET_FORCE (target_flags & FORCE_FLAG)
294 #define TARGET_PRESERVE_FLOAT (target_flags & PRESERVE_FLOAT_FLAG)
295 #define TARGET_PARALLEL ((target_flags & PARALLEL_INSN_FLAG) \
296 && optimize >= 2)
297 #define TARGET_PARALLEL_MPY (TARGET_PARALLEL \
298 && (target_flags & PARALLEL_MPY_FLAG))
299 #define TARGET_ALIASES (target_flags & ALIASES_FLAG)
300
301 #define TARGET_C3X (target_flags & C3X_FLAG)
302 #define TARGET_C30 (target_flags & C30_FLAG)
303 #define TARGET_C31 (target_flags & C31_FLAG)
304 #define TARGET_C32 (target_flags & C32_FLAG)
305 #define TARGET_C33 (target_flags & C33_FLAG)
306 #define TARGET_C40 (target_flags & C40_FLAG)
307 #define TARGET_C44 (target_flags & C44_FLAG)
308
309 /* Nonzero to use load_immed_addr pattern rather than forcing memory
310 addresses into memory. */
311 #define TARGET_LOAD_ADDRESS (1 || (! TARGET_C3X && ! TARGET_SMALL))
312
313 /* Nonzero to convert direct memory references into HIGH/LO_SUM pairs
314 during RTL generation. */
315 #define TARGET_EXPOSE_LDP 0
316
317 /* Nonzero to force loading of direct memory references into a register. */
318 #define TARGET_LOAD_DIRECT_MEMS 0
319
320 /* -mrpts allows the use of the RPTS instruction irregardless.
321 -mrpts=max-cycles will use RPTS if the number of cycles is constant
322 and less than max-cycles. */
323
324 #define TARGET_RPTS_CYCLES(CYCLES) (TARGET_RPTS || (CYCLES) < c4x_rpts_cycles)
325
326 /* -mcpu=XX with XX = target DSP version number. */
327
328 extern const char *c4x_rpts_cycles_string, *c4x_cpu_version_string;
329
330 #define TARGET_OPTIONS \
331 { {"rpts=", &c4x_rpts_cycles_string, \
332 N_("Specify maximum number of iterations for RPTS"), 0}, \
333 {"cpu=", &c4x_cpu_version_string, \
334 N_("Select CPU to generate code for"), 0} }
335
336 /* Sometimes certain combinations of command options do not make sense
337 on a particular target machine. You can define a macro
338 `OVERRIDE_OPTIONS' to take account of this. This macro, if
339 defined, is executed once just after all the command options have
340 been parsed. */
341
342 #define OVERRIDE_OPTIONS c4x_override_options ()
343
344 /* Define this to change the optimizations performed by default. */
345
346 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) c4x_optimization_options(LEVEL, SIZE)
347
348 /* Run Time Target Specification. */
349
350 #define TARGET_VERSION fprintf (stderr, " (TMS320C[34]x, TI syntax)");
351
352 /* Storage Layout. */
353
354 #define BITS_BIG_ENDIAN 0
355 #define BYTES_BIG_ENDIAN 0
356 #define WORDS_BIG_ENDIAN 0
357
358 /* Technically, we are little endian, but we put the floats out as
359 whole longs and this makes GCC put them out in the right order. */
360
361 #define FLOAT_WORDS_BIG_ENDIAN 1
362
363 /* Note the ANSI C standard requires sizeof(char) = 1. On the C[34]x
364 all integral and floating point data types are stored in memory as
365 32-bits (floating point types can be stored as 40-bits in the
366 extended precision registers), so sizeof(char) = sizeof(short) =
367 sizeof(int) = sizeof(long) = sizeof(float) = sizeof(double) = 1. */
368
369 #define BITS_PER_UNIT 32
370 #define UNITS_PER_WORD 1
371 #define PARM_BOUNDARY 32
372 #define STACK_BOUNDARY 32
373 #define FUNCTION_BOUNDARY 32
374 #define BIGGEST_ALIGNMENT 32
375 #define EMPTY_FIELD_BOUNDARY 32
376 #define STRICT_ALIGNMENT 0
377 #define TARGET_FLOAT_FORMAT C4X_FLOAT_FORMAT
378 #define MAX_FIXED_MODE_SIZE 64 /* HImode. */
379
380 /* If a structure has a floating point field then force structure
381 to have BLKMODE, unless it is the only field. */
382 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \
383 (TREE_CODE (TREE_TYPE (FIELD)) == REAL_TYPE && (MODE) == VOIDmode)
384
385 /* Number of bits in the high and low parts of a two stage
386 load of an immediate constant. */
387 #define BITS_PER_HIGH 16
388 #define BITS_PER_LO_SUM 16
389
390 /* Define register numbers. */
391
392 /* Extended-precision registers. */
393
394 #define R0_REGNO 0
395 #define R1_REGNO 1
396 #define R2_REGNO 2
397 #define R3_REGNO 3
398 #define R4_REGNO 4
399 #define R5_REGNO 5
400 #define R6_REGNO 6
401 #define R7_REGNO 7
402
403 /* Auxiliary (address) registers. */
404
405 #define AR0_REGNO 8
406 #define AR1_REGNO 9
407 #define AR2_REGNO 10
408 #define AR3_REGNO 11
409 #define AR4_REGNO 12
410 #define AR5_REGNO 13
411 #define AR6_REGNO 14
412 #define AR7_REGNO 15
413
414 /* Data page register. */
415
416 #define DP_REGNO 16
417
418 /* Index registers. */
419
420 #define IR0_REGNO 17
421 #define IR1_REGNO 18
422
423 /* Block size register. */
424
425 #define BK_REGNO 19
426
427 /* Stack pointer. */
428
429 #define SP_REGNO 20
430
431 /* Status register. */
432
433 #define ST_REGNO 21
434
435 /* Misc. interrupt registers. */
436
437 #define DIE_REGNO 22 /* C4x only. */
438 #define IE_REGNO 22 /* C3x only. */
439 #define IIE_REGNO 23 /* C4x only. */
440 #define IF_REGNO 23 /* C3x only. */
441 #define IIF_REGNO 24 /* C4x only. */
442 #define IOF_REGNO 24 /* C3x only. */
443
444 /* Repeat block registers. */
445
446 #define RS_REGNO 25
447 #define RE_REGNO 26
448 #define RC_REGNO 27
449
450 /* Additional extended-precision registers. */
451
452 #define R8_REGNO 28 /* C4x only. */
453 #define R9_REGNO 29 /* C4x only. */
454 #define R10_REGNO 30 /* C4x only. */
455 #define R11_REGNO 31 /* C4x only. */
456
457 #define FIRST_PSEUDO_REGISTER 32
458
459 /* Extended precision registers (low set). */
460
461 #define IS_R0R1_REGNO(r) \
462 ((unsigned int)((r) - R0_REGNO) <= (R1_REGNO - R0_REGNO))
463 #define IS_R2R3_REGNO(r) \
464 ((unsigned int)((r) - R2_REGNO) <= (R3_REGNO - R2_REGNO))
465 #define IS_EXT_LOW_REGNO(r) \
466 ((unsigned int)((r) - R0_REGNO) <= (R7_REGNO - R0_REGNO))
467
468 /* Extended precision registers (high set). */
469
470 #define IS_EXT_HIGH_REGNO(r) \
471 (! TARGET_C3X \
472 && ((unsigned int) ((r) - R8_REGNO) <= (R11_REGNO - R8_REGNO)))
473
474 /* Address registers. */
475
476 #define IS_AUX_REGNO(r) \
477 ((unsigned int)((r) - AR0_REGNO) <= (AR7_REGNO - AR0_REGNO))
478 #define IS_ADDR_REGNO(r) IS_AUX_REGNO(r)
479 #define IS_DP_REGNO(r) ((r) == DP_REGNO)
480 #define IS_INDEX_REGNO(r) (((r) == IR0_REGNO) || ((r) == IR1_REGNO))
481 #define IS_SP_REGNO(r) ((r) == SP_REGNO)
482 #define IS_BK_REGNO(r) (TARGET_BK && (r) == BK_REGNO)
483
484 /* Misc registers. */
485
486 #define IS_ST_REGNO(r) ((r) == ST_REGNO)
487 #define IS_RC_REGNO(r) ((r) == RC_REGNO)
488 #define IS_REPEAT_REGNO(r) (((r) >= RS_REGNO) && ((r) <= RC_REGNO))
489
490 /* Composite register sets. */
491
492 #define IS_ADDR_OR_INDEX_REGNO(r) (IS_ADDR_REGNO(r) || IS_INDEX_REGNO(r))
493 #define IS_EXT_REGNO(r) (IS_EXT_LOW_REGNO(r) || IS_EXT_HIGH_REGNO(r))
494 #define IS_STD_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) \
495 || IS_REPEAT_REGNO(r) \
496 || IS_SP_REGNO(r) \
497 || IS_BK_REGNO(r))
498 #define IS_INT_REGNO(r) (IS_EXT_REGNO(r) || IS_STD_REGNO(r))
499 #define IS_GROUP1_REGNO(r) (IS_ADDR_OR_INDEX_REGNO(r) || IS_BK_REGNO(r))
500 #define IS_INT_CALL_SAVED_REGNO(r) (((r) == R4_REGNO) || ((r) == R5_REGNO) \
501 || ((r) == R8_REGNO))
502 #define IS_FLOAT_CALL_SAVED_REGNO(r) (((r) == R6_REGNO) || ((r) == R7_REGNO))
503
504 #define IS_PSEUDO_REGNO(r) ((r) >= FIRST_PSEUDO_REGISTER)
505 #define IS_R0R1_OR_PSEUDO_REGNO(r) (IS_R0R1_REGNO(r) || IS_PSEUDO_REGNO(r))
506 #define IS_R2R3_OR_PSEUDO_REGNO(r) (IS_R2R3_REGNO(r) || IS_PSEUDO_REGNO(r))
507 #define IS_EXT_OR_PSEUDO_REGNO(r) (IS_EXT_REGNO(r) || IS_PSEUDO_REGNO(r))
508 #define IS_STD_OR_PSEUDO_REGNO(r) (IS_STD_REGNO(r) || IS_PSEUDO_REGNO(r))
509 #define IS_INT_OR_PSEUDO_REGNO(r) (IS_INT_REGNO(r) || IS_PSEUDO_REGNO(r))
510 #define IS_ADDR_OR_PSEUDO_REGNO(r) (IS_ADDR_REGNO(r) || IS_PSEUDO_REGNO(r))
511 #define IS_INDEX_OR_PSEUDO_REGNO(r) (IS_INDEX_REGNO(r) || IS_PSEUDO_REGNO(r))
512 #define IS_EXT_LOW_OR_PSEUDO_REGNO(r) (IS_EXT_LOW_REGNO(r) \
513 || IS_PSEUDO_REGNO(r))
514 #define IS_DP_OR_PSEUDO_REGNO(r) (IS_DP_REGNO(r) || IS_PSEUDO_REGNO(r))
515 #define IS_SP_OR_PSEUDO_REGNO(r) (IS_SP_REGNO(r) || IS_PSEUDO_REGNO(r))
516 #define IS_ST_OR_PSEUDO_REGNO(r) (IS_ST_REGNO(r) || IS_PSEUDO_REGNO(r))
517 #define IS_RC_OR_PSEUDO_REGNO(r) (IS_RC_REGNO(r) || IS_PSEUDO_REGNO(r))
518
519 #define IS_PSEUDO_REG(op) (IS_PSEUDO_REGNO(REGNO(op)))
520 #define IS_ADDR_REG(op) (IS_ADDR_REGNO(REGNO(op)))
521 #define IS_INDEX_REG(op) (IS_INDEX_REGNO(REGNO(op)))
522 #define IS_GROUP1_REG(r) (IS_GROUP1_REGNO(REGNO(op)))
523 #define IS_SP_REG(op) (IS_SP_REGNO(REGNO(op)))
524 #define IS_STD_REG(op) (IS_STD_REGNO(REGNO(op)))
525 #define IS_EXT_REG(op) (IS_EXT_REGNO(REGNO(op)))
526
527 #define IS_R0R1_OR_PSEUDO_REG(op) (IS_R0R1_OR_PSEUDO_REGNO(REGNO(op)))
528 #define IS_R2R3_OR_PSEUDO_REG(op) (IS_R2R3_OR_PSEUDO_REGNO(REGNO(op)))
529 #define IS_EXT_OR_PSEUDO_REG(op) (IS_EXT_OR_PSEUDO_REGNO(REGNO(op)))
530 #define IS_STD_OR_PSEUDO_REG(op) (IS_STD_OR_PSEUDO_REGNO(REGNO(op)))
531 #define IS_EXT_LOW_OR_PSEUDO_REG(op) (IS_EXT_LOW_OR_PSEUDO_REGNO(REGNO(op)))
532 #define IS_INT_OR_PSEUDO_REG(op) (IS_INT_OR_PSEUDO_REGNO(REGNO(op)))
533
534 #define IS_ADDR_OR_PSEUDO_REG(op) (IS_ADDR_OR_PSEUDO_REGNO(REGNO(op)))
535 #define IS_INDEX_OR_PSEUDO_REG(op) (IS_INDEX_OR_PSEUDO_REGNO(REGNO(op)))
536 #define IS_DP_OR_PSEUDO_REG(op) (IS_DP_OR_PSEUDO_REGNO(REGNO(op)))
537 #define IS_SP_OR_PSEUDO_REG(op) (IS_SP_OR_PSEUDO_REGNO(REGNO(op)))
538 #define IS_ST_OR_PSEUDO_REG(op) (IS_ST_OR_PSEUDO_REGNO(REGNO(op)))
539 #define IS_RC_OR_PSEUDO_REG(op) (IS_RC_OR_PSEUDO_REGNO(REGNO(op)))
540
541 /* 1 for registers that have pervasive standard uses
542 and are not available for the register allocator. */
543
544 #define FIXED_REGISTERS \
545 { \
546 /* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7. */ \
547 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
548 /* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11. */ \
549 1, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0 \
550 }
551
552 /* 1 for registers not available across function calls.
553 These must include the FIXED_REGISTERS and also any
554 registers that can be used without being saved.
555 The latter must include the registers where values are returned
556 and the register where structure-value addresses are passed.
557 Aside from that, you can include as many other registers as you like.
558
559 Note that the extended precision registers are only saved in some
560 modes. The macro HARD_REGNO_CALL_CLOBBERED specifies which modes
561 get clobbered for a given regno. */
562
563 #define CALL_USED_REGISTERS \
564 { \
565 /* R0 R1 R2 R3 R4 R5 R6 R7 AR0 AR1 AR2 AR3 AR4 AR5 AR6 AR7. */ \
566 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, \
567 /* DP IR0 IR1 BK SP ST DIE IIE IIF RS RE RC R8 R9 R10 R11. */ \
568 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1 \
569 }
570
571 /* Macro to conditionally modify fixed_regs/call_used_regs. */
572
573 #define CONDITIONAL_REGISTER_USAGE \
574 { \
575 if (! TARGET_BK) \
576 { \
577 fixed_regs[BK_REGNO] = 1; \
578 call_used_regs[BK_REGNO] = 1; \
579 c4x_regclass_map[BK_REGNO] = NO_REGS; \
580 } \
581 if (TARGET_C3X) \
582 { \
583 int i; \
584 \
585 reg_names[DIE_REGNO] = "ie"; /* Clobber die. */ \
586 reg_names[IF_REGNO] = "if"; /* Clobber iie. */ \
587 reg_names[IOF_REGNO] = "iof"; /* Clobber iif. */ \
588 \
589 for (i = R8_REGNO; i <= R11_REGNO; i++) \
590 { \
591 fixed_regs[i] = call_used_regs[i] = 1; \
592 c4x_regclass_map[i] = NO_REGS; \
593 } \
594 } \
595 if (TARGET_PRESERVE_FLOAT) \
596 { \
597 c4x_caller_save_map[R6_REGNO] = HFmode; \
598 c4x_caller_save_map[R7_REGNO] = HFmode; \
599 } \
600 }
601
602 /* Order of Allocation of Registers. */
603
604 /* List the order in which to allocate registers. Each register must be
605 listed once, even those in FIXED_REGISTERS.
606
607 First allocate registers that don't need preservation across calls,
608 except index and address registers. Then allocate data registers
609 that require preservation across calls (even though this invokes an
610 extra overhead of having to save/restore these registers). Next
611 allocate the address and index registers, since using these
612 registers for arithmetic can cause pipeline stalls. Finally
613 allocated the fixed registers which won't be allocated anyhow. */
614
615 #define REG_ALLOC_ORDER \
616 {R0_REGNO, R1_REGNO, R2_REGNO, R3_REGNO, \
617 R9_REGNO, R10_REGNO, R11_REGNO, \
618 RS_REGNO, RE_REGNO, RC_REGNO, BK_REGNO, \
619 R4_REGNO, R5_REGNO, R6_REGNO, R7_REGNO, R8_REGNO, \
620 AR0_REGNO, AR1_REGNO, AR2_REGNO, AR3_REGNO, \
621 AR4_REGNO, AR5_REGNO, AR6_REGNO, AR7_REGNO, \
622 IR0_REGNO, IR1_REGNO, \
623 SP_REGNO, DP_REGNO, ST_REGNO, IE_REGNO, IF_REGNO, IOF_REGNO}
624
625 /* A C expression that is nonzero if hard register number REGNO2 can be
626 considered for use as a rename register for REGNO1 */
627
628 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \
629 c4x_hard_regno_rename_ok((REGNO1), (REGNO2))
630
631 /* Determine which register classes are very likely used by spill registers.
632 local-alloc.c won't allocate pseudos that have these classes as their
633 preferred class unless they are "preferred or nothing". */
634
635 #define CLASS_LIKELY_SPILLED_P(CLASS) ((CLASS) == INDEX_REGS)
636
637 /* CCmode is wrongly defined in machmode.def. It should have a size
638 of UNITS_PER_WORD. HFmode is 40-bits and thus fits within a single
639 extended precision register. Similarly, HCmode fits within two
640 extended precision registers. */
641
642 #define HARD_REGNO_NREGS(REGNO, MODE) \
643 (((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : \
644 ((MODE) == HFmode) ? 1 : \
645 ((MODE) == HCmode) ? 2 : \
646 ((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
647
648
649 /* A C expression that is nonzero if the hard register REGNO is preserved
650 across a call in mode MODE. This does not have to include the call used
651 registers. */
652
653 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
654 ((IS_FLOAT_CALL_SAVED_REGNO (REGNO) && ! ((MODE) == QFmode)) \
655 || (IS_INT_CALL_SAVED_REGNO (REGNO) \
656 && ! ((MODE) == QImode || (MODE) == HImode || (MODE) == Pmode)))
657
658 /* Specify the modes required to caller save a given hard regno. */
659
660 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) (c4x_caller_save_map[REGNO])
661
662 #define HARD_REGNO_MODE_OK(REGNO, MODE) c4x_hard_regno_mode_ok(REGNO, MODE)
663
664 /* A C expression that is nonzero if it is desirable to choose
665 register allocation so as to avoid move instructions between a
666 value of mode MODE1 and a value of mode MODE2.
667
668 Value is 1 if it is a good idea to tie two pseudo registers
669 when one has mode MODE1 and one has mode MODE2.
670 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
671 for any hard reg, then this must be 0 for correct output. */
672
673 #define MODES_TIEABLE_P(MODE1, MODE2) 0
674
675
676 /* Define the classes of registers for register constraints in the
677 machine description. Also define ranges of constants.
678
679 One of the classes must always be named ALL_REGS and include all hard regs.
680 If there is more than one class, another class must be named NO_REGS
681 and contain no registers.
682
683 The name GENERAL_REGS must be the name of a class (or an alias for
684 another name such as ALL_REGS). This is the class of registers
685 that is allowed by "g" or "r" in a register constraint.
686 Also, registers outside this class are allocated only when
687 instructions express preferences for them.
688
689 The classes must be numbered in nondecreasing order; that is,
690 a larger-numbered class must never be contained completely
691 in a smaller-numbered class.
692
693 For any two classes, it is very desirable that there be another
694 class that represents their union. */
695
696 enum reg_class
697 {
698 NO_REGS,
699 R0R1_REGS, /* 't'. */
700 R2R3_REGS, /* 'u'. */
701 EXT_LOW_REGS, /* 'q'. */
702 EXT_REGS, /* 'f'. */
703 ADDR_REGS, /* 'a'. */
704 INDEX_REGS, /* 'x'. */
705 BK_REG, /* 'k'. */
706 SP_REG, /* 'b'. */
707 RC_REG, /* 'v'. */
708 COUNTER_REGS, /* */
709 INT_REGS, /* 'c'. */
710 GENERAL_REGS, /* 'r'. */
711 DP_REG, /* 'z'. */
712 ST_REG, /* 'y'. */
713 ALL_REGS,
714 LIM_REG_CLASSES
715 };
716
717 #define N_REG_CLASSES (int) LIM_REG_CLASSES
718
719 #define REG_CLASS_NAMES \
720 { \
721 "NO_REGS", \
722 "R0R1_REGS", \
723 "R2R3_REGS", \
724 "EXT_LOW_REGS", \
725 "EXT_REGS", \
726 "ADDR_REGS", \
727 "INDEX_REGS", \
728 "BK_REG", \
729 "SP_REG", \
730 "RC_REG", \
731 "COUNTER_REGS", \
732 "INT_REGS", \
733 "GENERAL_REGS", \
734 "DP_REG", \
735 "ST_REG", \
736 "ALL_REGS" \
737 }
738
739 /* Define which registers fit in which classes.
740 This is an initializer for a vector of HARD_REG_SET
741 of length N_REG_CLASSES. RC is not included in GENERAL_REGS
742 since the register allocator will often choose a general register
743 in preference to RC for the decrement_and_branch_on_count pattern. */
744
745 #define REG_CLASS_CONTENTS \
746 { \
747 {0x00000000}, /* No registers. */ \
748 {0x00000003}, /* 't' R0-R1 . */ \
749 {0x0000000c}, /* 'u' R2-R3 . */ \
750 {0x000000ff}, /* 'q' R0-R7 . */ \
751 {0xf00000ff}, /* 'f' R0-R11 */ \
752 {0x0000ff00}, /* 'a' AR0-AR7. */ \
753 {0x00060000}, /* 'x' IR0-IR1. */ \
754 {0x00080000}, /* 'k' BK. */ \
755 {0x00100000}, /* 'b' SP. */ \
756 {0x08000000}, /* 'v' RC. */ \
757 {0x0800ff00}, /* RC,AR0-AR7. */ \
758 {0x0e1eff00}, /* 'c' AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC. */ \
759 {0xfe1effff}, /* 'r' R0-R11, AR0-AR7, IR0-IR1, BK, SP, RS, RE, RC. */\
760 {0x00010000}, /* 'z' DP. */ \
761 {0x00200000}, /* 'y' ST. */ \
762 {0xffffffff}, /* All registers. */ \
763 }
764
765 /* The same information, inverted:
766 Return the class number of the smallest class containing
767 reg number REGNO. This could be a conditional expression
768 or could index an array. */
769
770 #define REGNO_REG_CLASS(REGNO) (c4x_regclass_map[REGNO])
771
772 /* When SMALL_REGISTER_CLASSES is defined, the lifetime of registers
773 explicitly used in the rtl is kept as short as possible.
774
775 We only need to define SMALL_REGISTER_CLASSES if TARGET_PARALLEL_MPY
776 is defined since the MPY|ADD insns require the classes R0R1_REGS and
777 R2R3_REGS which are used by the function return registers (R0,R1) and
778 the register arguments (R2,R3), respectively. I'm reluctant to define
779 this macro since it stomps on many potential optimizations. Ideally
780 it should have a register class argument so that not all the register
781 classes gets penalized for the sake of a naughty few... For long
782 double arithmetic we need two additional registers that we can use as
783 spill registers. */
784
785 #define SMALL_REGISTER_CLASSES (TARGET_SMALL_REG_CLASS && TARGET_PARALLEL_MPY)
786
787 #define BASE_REG_CLASS ADDR_REGS
788 #define INDEX_REG_CLASS INDEX_REGS
789
790 /*
791 Register constraints for the C4x
792
793 a - address reg (ar0-ar7)
794 b - stack reg (sp)
795 c - other gp int-only reg
796 d - data/int reg (equiv. to f)
797 f - data/float reg
798 h - data/long double reg (equiv. to f)
799 k - block count (bk)
800 q - r0-r7
801 t - r0-r1
802 u - r2-r3
803 v - repeat count (rc)
804 x - index register (ir0-ir1)
805 y - status register (st)
806 z - dp reg (dp)
807
808 Memory/constant constraints for the C4x
809
810 G - short float 16-bit
811 I - signed 16-bit constant (sign extended)
812 J - signed 8-bit constant (sign extended) (C4x only)
813 K - signed 5-bit constant (sign extended) (C4x only for stik)
814 L - unsigned 16-bit constant
815 M - unsigned 8-bit constant (C4x only)
816 N - ones complement of unsigned 16-bit constant
817 Q - indirect arx + 9-bit signed displacement
818 (a *-arx(n) or *+arx(n) is used to account for the sign bit)
819 R - indirect arx + 5-bit unsigned displacement (C4x only)
820 S - indirect arx + 0, 1, or irn displacement
821 T - direct symbol ref
822 > - indirect with autoincrement
823 < - indirect with autodecrement
824 } - indirect with post-modify
825 { - indirect with pre-modify
826 */
827
828 #define REG_CLASS_FROM_LETTER(CC) \
829 ( ((CC) == 'a') ? ADDR_REGS \
830 : ((CC) == 'b') ? SP_REG \
831 : ((CC) == 'c') ? INT_REGS \
832 : ((CC) == 'd') ? EXT_REGS \
833 : ((CC) == 'f') ? EXT_REGS \
834 : ((CC) == 'h') ? EXT_REGS \
835 : ((CC) == 'k') ? BK_REG \
836 : ((CC) == 'q') ? EXT_LOW_REGS \
837 : ((CC) == 't') ? R0R1_REGS \
838 : ((CC) == 'u') ? R2R3_REGS \
839 : ((CC) == 'v') ? RC_REG \
840 : ((CC) == 'x') ? INDEX_REGS \
841 : ((CC) == 'y') ? ST_REG \
842 : ((CC) == 'z') ? DP_REG \
843 : NO_REGS )
844
845 /* These assume that REGNO is a hard or pseudo reg number.
846 They give nonzero only if REGNO is a hard reg of the suitable class
847 or a pseudo reg currently allocated to a suitable hard reg.
848 Since they use reg_renumber, they are safe only once reg_renumber
849 has been allocated, which happens in local-alloc.c. */
850
851 #define REGNO_OK_FOR_BASE_P(REGNO) \
852 (IS_ADDR_REGNO(REGNO) || IS_ADDR_REGNO((unsigned)reg_renumber[REGNO]))
853
854 #define REGNO_OK_FOR_INDEX_P(REGNO) \
855 (IS_INDEX_REGNO(REGNO) || IS_INDEX_REGNO((unsigned)reg_renumber[REGNO]))
856
857 /* If we have to generate framepointer + constant prefer an ADDR_REGS
858 register. This avoids using EXT_REGS in addqi3_noclobber_reload. */
859
860 #define PREFERRED_RELOAD_CLASS(X, CLASS) \
861 (GET_CODE (X) == PLUS \
862 && GET_MODE (X) == Pmode \
863 && GET_CODE (XEXP ((X), 0)) == REG \
864 && GET_MODE (XEXP ((X), 0)) == Pmode \
865 && REGNO (XEXP ((X), 0)) == FRAME_POINTER_REGNUM \
866 && GET_CODE (XEXP ((X), 1)) == CONST_INT \
867 ? ADDR_REGS : (CLASS))
868
869 #define LIMIT_RELOAD_CLASS(X, CLASS) (CLASS)
870
871 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) 0
872
873 #define CLASS_MAX_NREGS(CLASS, MODE) \
874 (((MODE) == CCmode || (MODE) == CC_NOOVmode) ? 1 : ((MODE) == HFmode) ? 1 : \
875 ((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
876
877 #define IS_INT5_CONST(VAL) (((VAL) <= 15) && ((VAL) >= -16)) /* 'K'. */
878
879 #define IS_UINT5_CONST(VAL) (((VAL) <= 31) && ((VAL) >= 0)) /* 'R'. */
880
881 #define IS_INT8_CONST(VAL) (((VAL) <= 127) && ((VAL) >= -128)) /* 'J'. */
882
883 #define IS_UINT8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= 0)) /* 'M'. */
884
885 #define IS_INT16_CONST(VAL) (((VAL) <= 32767) && ((VAL) >= -32768)) /* 'I'. */
886
887 #define IS_UINT16_CONST(VAL) (((VAL) <= 65535) && ((VAL) >= 0)) /* 'L'. */
888
889 #define IS_NOT_UINT16_CONST(VAL) IS_UINT16_CONST(~(VAL)) /* 'N'. */
890
891 #define IS_HIGH_CONST(VAL) \
892 (! TARGET_C3X && (((VAL) & 0xffff) == 0)) /* 'O'. */
893
894
895 #define IS_DISP1_CONST(VAL) (((VAL) <= 1) && ((VAL) >= -1)) /* 'S'. */
896
897 #define IS_DISP8_CONST(VAL) (((VAL) <= 255) && ((VAL) >= -255)) /* 'Q'. */
898
899 #define IS_DISP1_OFF_CONST(VAL) (IS_DISP1_CONST (VAL) \
900 && IS_DISP1_CONST (VAL + 1))
901
902 #define IS_DISP8_OFF_CONST(VAL) (IS_DISP8_CONST (VAL) \
903 && IS_DISP8_CONST (VAL + 1))
904
905 #define CONST_OK_FOR_LETTER_P(VAL, C) \
906 ( ((C) == 'I') ? (IS_INT16_CONST (VAL)) \
907 : ((C) == 'J') ? (! TARGET_C3X && IS_INT8_CONST (VAL)) \
908 : ((C) == 'K') ? (! TARGET_C3X && IS_INT5_CONST (VAL)) \
909 : ((C) == 'L') ? (IS_UINT16_CONST (VAL)) \
910 : ((C) == 'M') ? (! TARGET_C3X && IS_UINT8_CONST (VAL)) \
911 : ((C) == 'N') ? (IS_NOT_UINT16_CONST (VAL)) \
912 : ((C) == 'O') ? (IS_HIGH_CONST (VAL)) \
913 : 0 )
914
915 #define CONST_DOUBLE_OK_FOR_LETTER_P(OP, C) \
916 ( ((C) == 'G') ? (fp_zero_operand (OP, QFmode)) \
917 : ((C) == 'H') ? (c4x_H_constant (OP)) \
918 : 0 )
919
920 #define EXTRA_CONSTRAINT(OP, C) \
921 ( ((C) == 'Q') ? (c4x_Q_constraint (OP)) \
922 : ((C) == 'R') ? (c4x_R_constraint (OP)) \
923 : ((C) == 'S') ? (c4x_S_constraint (OP)) \
924 : ((C) == 'T') ? (c4x_T_constraint (OP)) \
925 : ((C) == 'U') ? (c4x_U_constraint (OP)) \
926 : 0 )
927
928 #define SMALL_CONST(VAL, insn) \
929 ( ((insn == NULL_RTX) || (get_attr_data (insn) == DATA_INT16)) \
930 ? IS_INT16_CONST (VAL) \
931 : ( (get_attr_data (insn) == DATA_NOT_UINT16) \
932 ? IS_NOT_UINT16_CONST (VAL) \
933 : ( (get_attr_data (insn) == DATA_HIGH_16) \
934 ? IS_HIGH_CONST (VAL) \
935 : IS_UINT16_CONST (VAL) \
936 ) \
937 ) \
938 )
939
940 /*
941 I. Routine calling with arguments in registers
942 ----------------------------------------------
943
944 The TI C3x compiler has a rather unusual register passing algorithm.
945 Data is passed in the following registers (in order):
946
947 AR2, R2, R3, RC, RS, RE
948
949 However, the first and second floating point values are always in R2
950 and R3 (and all other floats are on the stack). Structs are always
951 passed on the stack. If the last argument is an ellipsis, the
952 previous argument is passed on the stack so that its address can be
953 taken for the stdargs macros.
954
955 Because of this, we have to pre-scan the list of arguments to figure
956 out what goes where in the list.
957
958 II. Routine calling with arguments on stack
959 -------------------------------------------
960
961 Let the subroutine declared as "foo(arg0, arg1, arg2);" have local
962 variables loc0, loc1, and loc2. After the function prologue has
963 been executed, the stack frame will look like:
964
965 [stack grows towards increasing addresses]
966 I-------------I
967 5 I saved reg1 I <= SP points here
968 I-------------I
969 4 I saved reg0 I
970 I-------------I
971 3 I loc2 I
972 I-------------I
973 2 I loc1 I
974 I-------------I
975 1 I loc0 I
976 I-------------I
977 0 I old FP I <= FP (AR3) points here
978 I-------------I
979 -1 I return PC I
980 I-------------I
981 -2 I arg0 I
982 I-------------I
983 -3 I arg1 I
984 I-------------I
985 -4 I arg2 I
986 I-------------I
987
988 All local variables (locn) are accessible by means of +FP(n+1)
989 addressing, where n is the local variable number.
990
991 All stack arguments (argn) are accessible by means of -FP(n-2).
992
993 The stack pointer (SP) points to the last register saved in the
994 prologue (regn).
995
996 Note that a push instruction performs a preincrement of the stack
997 pointer. (STACK_PUSH_CODE == PRE_INC)
998
999 III. Registers used in function calling convention
1000 --------------------------------------------------
1001
1002 Preserved across calls: R4...R5 (only by PUSH, i.e. lower 32 bits)
1003 R6...R7 (only by PUSHF, i.e. upper 32 bits)
1004 AR3...AR7
1005
1006 (Because of this model, we only assign FP values in R6, R7 and
1007 only assign integer values in R4, R5.)
1008
1009 These registers are saved at each function entry and restored at
1010 the exit. Also it is expected any of these not affected by any
1011 call to user-defined (not service) functions.
1012
1013 Not preserved across calls: R0...R3
1014 R4...R5 (upper 8 bits)
1015 R6...R7 (lower 8 bits)
1016 AR0...AR2, IR0, IR1, BK, ST, RS, RE, RC
1017
1018 These registers are used arbitrary in a function without being preserved.
1019 It is also expected that any of these can be clobbered by any call.
1020
1021 Not used by GCC (except for in user "asm" statements):
1022 IE (DIE), IF (IIE), IOF (IIF)
1023
1024 These registers are never used by GCC for any data, but can be used
1025 with "asm" statements. */
1026
1027 #define C4X_ARG0 -2
1028 #define C4X_LOC0 1
1029
1030 /* Basic Stack Layout. */
1031
1032 /* The stack grows upward, stack frame grows upward, and args grow
1033 downward. */
1034
1035 #define STARTING_FRAME_OFFSET C4X_LOC0
1036 #define FIRST_PARM_OFFSET(FNDECL) (C4X_ARG0 + 1)
1037 #define ARGS_GROW_DOWNWARD
1038 #define STACK_POINTER_OFFSET 1
1039
1040 /* Define this if pushing a word on the stack
1041 makes the stack pointer a smaller address. */
1042
1043 /* #define STACK_GROWS_DOWNWARD. */
1044 /* Like the dsp16xx, i370, i960, and we32k ports. */
1045
1046 /* Define this if the nominal address of the stack frame
1047 is at the high-address end of the local variables;
1048 that is, each additional local variable allocated
1049 goes at a more negative offset in the frame. */
1050
1051 /* #define FRAME_GROWS_DOWNWARD. */
1052
1053
1054 /* Registers That Address the Stack Frame. */
1055
1056 #define STACK_POINTER_REGNUM SP_REGNO /* SP. */
1057 #define FRAME_POINTER_REGNUM AR3_REGNO /* AR3. */
1058 #define ARG_POINTER_REGNUM AR3_REGNO /* AR3. */
1059 #define STATIC_CHAIN_REGNUM AR0_REGNO /* AR0. */
1060
1061 /* Eliminating Frame Pointer and Arg Pointer. */
1062
1063 #define FRAME_POINTER_REQUIRED 0
1064
1065 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
1066 { \
1067 int regno; \
1068 int offset = 0; \
1069 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
1070 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1071 offset += TARGET_PRESERVE_FLOAT \
1072 && IS_FLOAT_CALL_SAVED_REGNO (regno) ? 2 : 1; \
1073 (DEPTH) = -(offset + get_frame_size ()); \
1074 }
1075
1076 /* This is a hack... We need to specify a register. */
1077 #define ELIMINABLE_REGS \
1078 {{ FRAME_POINTER_REGNUM, FRAME_POINTER_REGNUM }}
1079
1080 #define CAN_ELIMINATE(FROM, TO) \
1081 (! (((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \
1082 || ((FROM) == FRAME_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM)))
1083
1084 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
1085 { \
1086 int regno; \
1087 int offset = 0; \
1088 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \
1089 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
1090 offset += TARGET_PRESERVE_FLOAT \
1091 && IS_FLOAT_CALL_SAVED_REGNO (regno) ? 2 : 1; \
1092 (OFFSET) = -(offset + get_frame_size ()); \
1093 }
1094
1095
1096 /* Passing Function Arguments on the Stack. */
1097
1098 #define PUSH_ARGS 1
1099 #define PUSH_ROUNDING(BYTES) (BYTES)
1100 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
1101
1102 /* The following structure is used by calls.c, function.c, c4x.c. */
1103
1104 typedef struct c4x_args
1105 {
1106 int floats;
1107 int ints;
1108 int maxfloats;
1109 int maxints;
1110 int init;
1111 int var;
1112 int prototype;
1113 int args;
1114 }
1115 CUMULATIVE_ARGS;
1116
1117 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
1118 (c4x_init_cumulative_args (&CUM, FNTYPE, LIBNAME))
1119
1120 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1121 (c4x_function_arg_advance (&CUM, MODE, TYPE, NAMED))
1122
1123 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1124 (c4x_function_arg(&CUM, MODE, TYPE, NAMED))
1125
1126 /* Define the profitability of saving registers around calls.
1127 We disable caller save to avoid a bug in flow.c (this also affects
1128 other targets such as m68k). Since we must use stf/sti,
1129 the profitability is marginal anyway. */
1130
1131 #define CALLER_SAVE_PROFITABLE(REFS,CALLS) 0
1132
1133 /* Never pass data by reference. */
1134
1135 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) 0
1136
1137 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
1138
1139 /* 1 if N is a possible register number for function argument passing. */
1140
1141 #define FUNCTION_ARG_REGNO_P(REGNO) \
1142 ( ( ((REGNO) == AR2_REGNO) /* AR2. */ \
1143 || ((REGNO) == R2_REGNO) /* R2. */ \
1144 || ((REGNO) == R3_REGNO) /* R3. */ \
1145 || ((REGNO) == RC_REGNO) /* RC. */ \
1146 || ((REGNO) == RS_REGNO) /* RS. */ \
1147 || ((REGNO) == RE_REGNO)) /* RE. */ \
1148 ? 1 \
1149 : 0)
1150
1151 /* How Scalar Function Values Are Returned. */
1152
1153 #define FUNCTION_VALUE(VALTYPE, FUNC) \
1154 gen_rtx(REG, TYPE_MODE(VALTYPE), R0_REGNO) /* Return in R0. */
1155
1156 #define LIBCALL_VALUE(MODE) \
1157 gen_rtx(REG, MODE, R0_REGNO) /* Return in R0. */
1158
1159 #define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == R0_REGNO)
1160
1161 /* How Large Values Are Returned. */
1162
1163 #define DEFAULT_PCC_STRUCT_RETURN 0
1164 #define STRUCT_VALUE_REGNUM AR0_REGNO /* AR0. */
1165
1166 /* Varargs handling. */
1167
1168 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1169 c4x_va_arg (valist, type)
1170
1171 /* Generating Code for Profiling. */
1172
1173 /* Note that the generated assembly uses the ^ operator to load the 16
1174 MSBs of the address. This is not supported by the TI assembler.
1175 The FUNCTION profiler needs a function mcount which gets passed
1176 a pointer to the LABELNO. */
1177
1178 #define FUNCTION_PROFILER(FILE, LABELNO) \
1179 if (! TARGET_C3X) \
1180 { \
1181 fprintf (FILE, "\tpush\tar2\n"); \
1182 fprintf (FILE, "\tldhi\t^LP%d,ar2\n", (LABELNO)); \
1183 fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
1184 fprintf (FILE, "\tcall\tmcount\n"); \
1185 fprintf (FILE, "\tpop\tar2\n"); \
1186 } \
1187 else \
1188 { \
1189 fprintf (FILE, "\tpush\tar2\n"); \
1190 fprintf (FILE, "\tldiu\t^LP%d,ar2\n", (LABELNO)); \
1191 fprintf (FILE, "\tlsh\t16,ar2\n"); \
1192 fprintf (FILE, "\tor\t#LP%d,ar2\n", (LABELNO)); \
1193 fprintf (FILE, "\tcall\tmcount\n"); \
1194 fprintf (FILE, "\tpop\tar2\n"); \
1195 }
1196
1197 /* Implicit Calls to Library Routines. */
1198
1199 #define TARGET_MEM_FUNCTIONS
1200
1201 /* CC_NOOVmode should be used when the first operand is a PLUS, MINUS, NEG
1202 or MULT.
1203 CCmode should be used when no special processing is needed. */
1204 #define SELECT_CC_MODE(OP,X,Y) \
1205 ((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
1206 || GET_CODE (X) == NEG || GET_CODE (X) == MULT \
1207 || GET_MODE (X) == ABS \
1208 || GET_CODE (Y) == PLUS || GET_CODE (Y) == MINUS \
1209 || GET_CODE (Y) == NEG || GET_CODE (Y) == MULT \
1210 || GET_MODE (Y) == ABS) \
1211 ? CC_NOOVmode : CCmode)
1212
1213 /* Addressing Modes. */
1214
1215 #define HAVE_POST_INCREMENT 1
1216 #define HAVE_PRE_INCREMENT 1
1217 #define HAVE_POST_DECREMENT 1
1218 #define HAVE_PRE_DECREMENT 1
1219 #define HAVE_PRE_MODIFY_REG 1
1220 #define HAVE_POST_MODIFY_REG 1
1221 #define HAVE_PRE_MODIFY_DISP 1
1222 #define HAVE_POST_MODIFY_DISP 1
1223
1224 /* The number of insns that can be packed into a single opcode. */
1225 #define PACK_INSNS 2
1226
1227 /* Recognize any constant value that is a valid address.
1228 We could allow arbitrary constant addresses in the large memory
1229 model but for the small memory model we can only accept addresses
1230 within the data page. I suppose we could also allow
1231 CONST PLUS SYMBOL_REF. */
1232 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == SYMBOL_REF)
1233
1234 /* Maximum number of registers that can appear in a valid memory
1235 address. */
1236 #define MAX_REGS_PER_ADDRESS 2
1237
1238 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1239 and check its validity for a certain class.
1240 We have two alternate definitions for each of them.
1241 The usual definition accepts all pseudo regs; the other rejects
1242 them unless they have been allocated suitable hard regs.
1243 The symbol REG_OK_STRICT causes the latter definition to be used.
1244
1245 Most source files want to accept pseudo regs in the hope that
1246 they will get allocated to the class that the insn wants them to be in.
1247 Source files for reload pass need to be strict.
1248 After reload, it makes no difference, since pseudo regs have
1249 been eliminated by then. */
1250
1251 #ifndef REG_OK_STRICT
1252
1253 /* Nonzero if X is a hard or pseudo reg that can be used as a base. */
1254
1255 #define REG_OK_FOR_BASE_P(X) IS_ADDR_OR_PSEUDO_REG(X)
1256
1257 /* Nonzero if X is a hard or pseudo reg that can be used as an index. */
1258
1259 #define REG_OK_FOR_INDEX_P(X) IS_INDEX_OR_PSEUDO_REG(X)
1260
1261 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1262 { \
1263 if (c4x_legitimate_address_p (MODE, X, 0)) \
1264 goto ADDR; \
1265 }
1266
1267 #else
1268
1269 /* Nonzero if X is a hard reg that can be used as an index. */
1270
1271 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1272
1273 /* Nonzero if X is a hard reg that can be used as a base reg. */
1274
1275 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1276
1277 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1278 { \
1279 if (c4x_legitimate_address_p (MODE, X, 1)) \
1280 goto ADDR; \
1281 }
1282
1283 #endif
1284
1285 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1286 { \
1287 rtx new; \
1288 \
1289 new = c4x_legitimize_address (X, MODE); \
1290 if (new != NULL_RTX) \
1291 { \
1292 (X) = new; \
1293 goto WIN; \
1294 } \
1295 }
1296
1297 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \
1298 { \
1299 if (MODE != HImode \
1300 && MODE != HFmode \
1301 && GET_MODE (X) != HImode \
1302 && GET_MODE (X) != HFmode \
1303 && (GET_CODE (X) == CONST \
1304 || GET_CODE (X) == SYMBOL_REF \
1305 || GET_CODE (X) == LABEL_REF)) \
1306 { \
1307 if (! TARGET_SMALL) \
1308 { \
1309 int i; \
1310 (X) = gen_rtx_LO_SUM (GET_MODE (X), \
1311 gen_rtx_HIGH (GET_MODE (X), X), X); \
1312 i = push_reload (XEXP (X, 0), NULL_RTX, \
1313 &XEXP (X, 0), NULL, \
1314 DP_REG, GET_MODE (X), VOIDmode, 0, 0, \
1315 OPNUM, TYPE); \
1316 /* The only valid reg is DP. This is a fixed reg and will \
1317 normally not be used so force it. */ \
1318 rld[i].reg_rtx = gen_rtx_REG (Pmode, DP_REGNO); \
1319 rld[i].nocombine = 1; \
1320 } \
1321 else \
1322 { \
1323 /* make_memloc in reload will substitute invalid memory \
1324 references. We need to fix them up. */ \
1325 (X) = gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, DP_REGNO), (X)); \
1326 } \
1327 goto WIN; \
1328 } \
1329 else if (MODE != HImode \
1330 && MODE != HFmode \
1331 && GET_MODE (X) != HImode \
1332 && GET_MODE (X) != HFmode \
1333 && GET_CODE (X) == LO_SUM \
1334 && GET_CODE (XEXP (X,0)) == HIGH \
1335 && (GET_CODE (XEXP (XEXP (X,0),0)) == CONST \
1336 || GET_CODE (XEXP (XEXP (X,0),0)) == SYMBOL_REF \
1337 || GET_CODE (XEXP (XEXP (X,0),0)) == LABEL_REF)) \
1338 { \
1339 if (! TARGET_SMALL) \
1340 { \
1341 int i = push_reload (XEXP (X, 0), NULL_RTX, \
1342 &XEXP (X, 0), NULL, \
1343 DP_REG, GET_MODE (X), VOIDmode, 0, 0, \
1344 OPNUM, TYPE); \
1345 /* The only valid reg is DP. This is a fixed reg and will \
1346 normally not be used so force it. */ \
1347 rld[i].reg_rtx = gen_rtx_REG (Pmode, DP_REGNO); \
1348 rld[i].nocombine = 1; \
1349 } \
1350 goto WIN; \
1351 } \
1352 }
1353
1354 /* No mode-dependent addresses on the C4x are autoincrements. */
1355
1356 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
1357 if (GET_CODE (ADDR) == PRE_DEC \
1358 || GET_CODE (ADDR) == POST_DEC \
1359 || GET_CODE (ADDR) == PRE_INC \
1360 || GET_CODE (ADDR) == POST_INC \
1361 || GET_CODE (ADDR) == POST_MODIFY \
1362 || GET_CODE (ADDR) == PRE_MODIFY) \
1363 goto LABEL
1364
1365
1366 /* Nonzero if the constant value X is a legitimate general operand.
1367 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1368
1369 The C4x can only load 16-bit immediate values, so we only allow a
1370 restricted subset of CONST_INT and CONST_DOUBLE. Disallow
1371 LABEL_REF and SYMBOL_REF (except on the C40 with the big memory
1372 model) so that the symbols will be forced into the constant pool.
1373 On second thoughts, let's do this with the move expanders since
1374 the alias analysis has trouble if we force constant addresses
1375 into memory.
1376 */
1377
1378 #define LEGITIMATE_CONSTANT_P(X) \
1379 ((GET_CODE (X) == CONST_DOUBLE && c4x_H_constant (X)) \
1380 || (GET_CODE (X) == CONST_INT) \
1381 || (GET_CODE (X) == SYMBOL_REF) \
1382 || (GET_CODE (X) == LABEL_REF) \
1383 || (GET_CODE (X) == CONST) \
1384 || (GET_CODE (X) == HIGH && ! TARGET_C3X) \
1385 || (GET_CODE (X) == LO_SUM && ! TARGET_C3X))
1386
1387 #define LEGITIMATE_DISPLACEMENT_P(X) IS_DISP8_CONST (INTVAL (X))
1388
1389 /* Descripting Relative Cost of Operations. */
1390
1391 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \
1392 if (REG_P (OP1) && ! REG_P (OP0)) \
1393 { \
1394 rtx tmp = OP0; OP0 = OP1 ; OP1 = tmp; \
1395 CODE = swap_condition (CODE); \
1396 }
1397
1398 #define EXT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, EXT_REGS))
1399 #define ADDR_CLASS_P(CLASS) (reg_class_subset_p (CLASS, ADDR_REGS))
1400 #define INDEX_CLASS_P(CLASS) (reg_class_subset_p (CLASS, INDEX_REGS))
1401 #define EXPENSIVE_CLASS_P(CLASS) (ADDR_CLASS_P(CLASS) \
1402 || INDEX_CLASS_P(CLASS) || (CLASS) == SP_REG)
1403
1404 /* Compute extra cost of moving data between one register class
1405 and another. */
1406
1407 #define REGISTER_MOVE_COST(MODE, FROM, TO) 2
1408
1409 /* Memory move cost is same as fast register move. Maybe this should
1410 be bumped up?. */
1411
1412 #define MEMORY_MOVE_COST(M,C,I) 4
1413
1414 /* Branches are kind of expensive (even with delayed branching) so
1415 make their cost higher. */
1416
1417 #define BRANCH_COST 8
1418
1419 #define WORD_REGISTER_OPERATIONS
1420
1421 /* Dividing the Output into Sections. */
1422
1423 #define TEXT_SECTION_ASM_OP "\t.text"
1424
1425 #define DATA_SECTION_ASM_OP "\t.data"
1426
1427 #define READONLY_DATA_SECTION_ASM_OP "\t.sect\t\".const\""
1428
1429 /* Do not use .init section so __main will be called on startup. This will
1430 call __do_global_ctors and prepare for __do_global_dtors on exit. */
1431
1432 #if 0
1433 #define INIT_SECTION_ASM_OP "\t.sect\t\".init\""
1434 #endif
1435
1436 #define FINI_SECTION_ASM_OP "\t.sect\t\".fini\""
1437
1438 #undef EXTRA_SECTIONS
1439 #define EXTRA_SECTIONS in_init, in_fini
1440
1441 #undef EXTRA_SECTION_FUNCTIONS
1442 #define EXTRA_SECTION_FUNCTIONS \
1443 INIT_SECTION_FUNCTION \
1444 FINI_SECTION_FUNCTION
1445
1446 #define INIT_SECTION_FUNCTION \
1447 extern void init_section (void); \
1448 void \
1449 init_section (void) \
1450 { \
1451 if (in_section != in_init) \
1452 { \
1453 fprintf (asm_out_file, ";\t.init\n"); \
1454 in_section = in_init; \
1455 } \
1456 }
1457
1458 #define FINI_SECTION_FUNCTION \
1459 void \
1460 fini_section () \
1461 { \
1462 if (in_section != in_fini) \
1463 { \
1464 fprintf (asm_out_file, "%s\n", FINI_SECTION_ASM_OP); \
1465 in_section = in_fini; \
1466 } \
1467 }
1468
1469 #define ASM_STABS_OP "\t.stabs\t"
1470
1471 /* Switch into a generic section. */
1472 #define TARGET_ASM_NAMED_SECTION c4x_asm_named_section
1473
1474
1475 /* Overall Framework of an Assembler File. */
1476
1477 #define ASM_COMMENT_START ";"
1478
1479 #define ASM_APP_ON ""
1480 #define ASM_APP_OFF ""
1481
1482 #define ASM_OUTPUT_ASCII(FILE, PTR, LEN) c4x_output_ascii (FILE, PTR, LEN)
1483
1484 /* Output and Generation of Labels. */
1485
1486 #define NO_DOT_IN_LABEL /* Only required for TI format. */
1487
1488 /* Globalizing directive for a label. */
1489 #define GLOBAL_ASM_OP "\t.global\t"
1490
1491 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \
1492 c4x_external_ref (NAME)
1493
1494 /* A C statement to output on FILE an assembler pseudo-op to
1495 declare a library function named external.
1496 (Only needed to keep asm30 happy for ___divqf3 etc.) */
1497
1498 #define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, FUN) \
1499 c4x_external_ref (XSTR (FUN, 0))
1500
1501 /* The prefix to add to user-visible assembler symbols. */
1502
1503 #define USER_LABEL_PREFIX "_"
1504
1505 /* This is how to store into the string LABEL
1506 the symbol_ref name of an internal numbered label where
1507 PREFIX is the class of label and NUM is the number within the class.
1508 This is suitable for output with `assemble_name'. */
1509
1510 #define ASM_GENERATE_INTERNAL_LABEL(BUFFER, PREFIX, NUM) \
1511 sprintf (BUFFER, "*%s%lu", PREFIX, (unsigned long)(NUM))
1512
1513 /* A C statement to output to the stdio stream STREAM assembler code which
1514 defines (equates) the symbol NAME to have the value VALUE. */
1515
1516 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \
1517 do { \
1518 assemble_name (STREAM, NAME); \
1519 fprintf (STREAM, "\t.set\t%s\n", VALUE); \
1520 } while (0)
1521
1522 /* Output of Dispatch Tables. */
1523
1524 /* This is how to output an element of a case-vector that is absolute. */
1525
1526 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1527 fprintf (FILE, "\t.long\tL%d\n", VALUE);
1528
1529 /* This is how to output an element of a case-vector that is relative. */
1530
1531 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1532 fprintf (FILE, "\t.long\tL%d-L%d\n", VALUE, REL);
1533
1534 #undef SIZE_TYPE
1535 #define SIZE_TYPE "unsigned int"
1536
1537 #undef PTRDIFF_TYPE
1538 #define PTRDIFF_TYPE "int"
1539
1540 #undef WCHAR_TYPE
1541 #define WCHAR_TYPE "long int"
1542
1543 #undef WCHAR_TYPE_SIZE
1544 #define WCHAR_TYPE_SIZE 32
1545
1546 #define INT_TYPE_SIZE 32
1547 #define LONG_LONG_TYPE_SIZE 64
1548 #define FLOAT_TYPE_SIZE 32
1549 #define DOUBLE_TYPE_SIZE 32
1550 #define LONG_DOUBLE_TYPE_SIZE 64 /* Actually only 40. */
1551
1552 /* Output #ident as a .ident. */
1553
1554 #define ASM_OUTPUT_IDENT(FILE, NAME) \
1555 fprintf (FILE, "\t.ident \"%s\"\n", NAME);
1556
1557 /* Output of Uninitialized Variables. */
1558
1559 /* This says how to output an assembler line to define a local
1560 uninitialized variable. */
1561
1562 #undef ASM_OUTPUT_LOCAL
1563 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1564 ( fputs ("\t.bss\t", FILE), \
1565 assemble_name (FILE, (NAME)), \
1566 fprintf (FILE, ",%u\n", (int)(ROUNDED)))
1567
1568 /* This says how to output an assembler line to define a global
1569 uninitialized variable. */
1570
1571 #undef ASM_OUTPUT_COMMON
1572 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1573 ( fputs ("\t.globl\t", FILE), \
1574 assemble_name (FILE, (NAME)), \
1575 fputs ("\n\t.bss\t", FILE), \
1576 assemble_name (FILE, (NAME)), \
1577 fprintf (FILE, ",%u\n", (int)(ROUNDED)))
1578
1579 #undef ASM_OUTPUT_BSS
1580 #define ASM_OUTPUT_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1581 ( fputs ("\t.globl\t", FILE), \
1582 assemble_name (FILE, (NAME)), \
1583 fputs ("\n\t.bss\t", FILE), \
1584 assemble_name (FILE, (NAME)), \
1585 fprintf (FILE, ",%u\n", (int)(SIZE)))
1586
1587 /* Macros Controlling Initialization Routines. */
1588
1589 #define OBJECT_FORMAT_COFF
1590 #define REAL_NM_FILE_NAME "c4x-nm"
1591
1592 /* Output of Assembler Instructions. */
1593
1594 /* Register names when used for integer modes. */
1595
1596 #define REGISTER_NAMES \
1597 { \
1598 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
1599 "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
1600 "dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
1601 "iif", "rs", "re", "rc", "r8", "r9", "r10", "r11" \
1602 }
1603
1604 /* Alternate register names when used for floating point modes. */
1605
1606 #define FLOAT_REGISTER_NAMES \
1607 { \
1608 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \
1609 "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7", \
1610 "dp", "ir0", "ir1", "bk", "sp", "st", "die", "iie", \
1611 "iif", "rs", "re", "rc", "f8", "f9", "f10", "f11" \
1612 }
1613
1614 #define PRINT_OPERAND(FILE, X, CODE) c4x_print_operand(FILE, X, CODE)
1615
1616 /* Determine which codes are valid without a following integer. These must
1617 not be alphabetic. */
1618
1619 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) ((CODE) == '#')
1620
1621 #define PRINT_OPERAND_ADDRESS(FILE, X) c4x_print_operand_address(FILE, X)
1622
1623 /* C4x specific pragmas. */
1624 #define REGISTER_TARGET_PRAGMAS() do { \
1625 c_register_pragma (0, "CODE_SECTION", c4x_pr_CODE_SECTION); \
1626 c_register_pragma (0, "DATA_SECTION", c4x_pr_DATA_SECTION); \
1627 c_register_pragma (0, "FUNC_CANNOT_INLINE", c4x_pr_ignored); \
1628 c_register_pragma (0, "FUNC_EXT_CALLED", c4x_pr_ignored); \
1629 c_register_pragma (0, "FUNC_IS_PURE", c4x_pr_FUNC_IS_PURE); \
1630 c_register_pragma (0, "FUNC_IS_SYSTEM", c4x_pr_ignored); \
1631 c_register_pragma (0, "FUNC_NEVER_RETURNS", c4x_pr_FUNC_NEVER_RETURNS); \
1632 c_register_pragma (0, "FUNC_NO_GLOBAL_ASG", c4x_pr_ignored); \
1633 c_register_pragma (0, "FUNC_NO_IND_ASG", c4x_pr_ignored); \
1634 c_register_pragma (0, "INTERRUPT", c4x_pr_INTERRUPT); \
1635 } while (0)
1636
1637 /* Assembler Commands for Alignment. */
1638
1639 #define ASM_OUTPUT_SKIP(FILE, SIZE) \
1640 { int c = SIZE; \
1641 for (; c > 0; --c) \
1642 fprintf (FILE,"\t.word\t0\n"); \
1643 }
1644
1645 #define ASM_NO_SKIP_IN_TEXT 1
1646
1647 /* I'm not sure about this one. FIXME. */
1648
1649 #define ASM_OUTPUT_ALIGN(FILE, LOG) \
1650 if ((LOG) != 0) \
1651 fprintf (FILE, "\t.align\t%d\n", (1 << (LOG)))
1652
1653
1654 /* Macros for SDB and DWARF Output (use .sdef instead of .def
1655 to avoid conflict with TI's use of .def). */
1656
1657 #define SDB_DELIM "\n"
1658 #define SDB_DEBUGGING_INFO 1
1659
1660 /* Don't use octal since this can confuse gas for the c4x. */
1661 #define PUT_SDB_TYPE(a) fprintf(asm_out_file, "\t.type\t0x%x%s", a, SDB_DELIM)
1662
1663 #define PUT_SDB_DEF(A) \
1664 do { fprintf (asm_out_file, "\t.sdef\t"); \
1665 ASM_OUTPUT_LABELREF (asm_out_file, A); \
1666 fprintf (asm_out_file, SDB_DELIM); } while (0)
1667
1668 #define PUT_SDB_PLAIN_DEF(A) \
1669 fprintf (asm_out_file,"\t.sdef\t.%s%s", A, SDB_DELIM)
1670
1671 #define PUT_SDB_BLOCK_START(LINE) \
1672 fprintf (asm_out_file, \
1673 "\t.sdef\t.bb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
1674 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
1675
1676 #define PUT_SDB_BLOCK_END(LINE) \
1677 fprintf (asm_out_file, \
1678 "\t.sdef\t.eb%s\t.val\t.%s\t.scl\t100%s\t.line\t%d%s\t.endef\n", \
1679 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
1680
1681 #define PUT_SDB_FUNCTION_START(LINE) \
1682 fprintf (asm_out_file, \
1683 "\t.sdef\t.bf%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
1684 SDB_DELIM, SDB_DELIM, SDB_DELIM, (LINE), SDB_DELIM)
1685
1686 /* Note we output relative line numbers for .ef which gas converts
1687 to absolute line numbers. The TI compiler outputs absolute line numbers
1688 in the .sym directive which gas does not support. */
1689 #define PUT_SDB_FUNCTION_END(LINE) \
1690 fprintf (asm_out_file, \
1691 "\t.sdef\t.ef%s\t.val\t.%s\t.scl\t101%s\t.line\t%d%s\t.endef\n", \
1692 SDB_DELIM, SDB_DELIM, SDB_DELIM, \
1693 (LINE), SDB_DELIM)
1694
1695 #define PUT_SDB_EPILOGUE_END(NAME) \
1696 do { fprintf (asm_out_file, "\t.sdef\t"); \
1697 ASM_OUTPUT_LABELREF (asm_out_file, NAME); \
1698 fprintf (asm_out_file, \
1699 "%s\t.val\t.%s\t.scl\t-1%s\t.endef\n", \
1700 SDB_DELIM, SDB_DELIM, SDB_DELIM); } while (0)
1701
1702 /* Define this as 1 if `char' should by default be signed; else as 0. */
1703
1704 #define DEFAULT_SIGNED_CHAR 1
1705
1706 /* A function address in a call instruction is a byte address (for
1707 indexing purposes) so give the MEM rtx a byte's mode. */
1708
1709 #define FUNCTION_MODE QImode
1710
1711 #define SLOW_BYTE_ACCESS 0
1712
1713 /* Specify the machine mode that pointers have. After generation of
1714 RTL, the compiler makes no further distinction between pointers and
1715 any other objects of this machine mode. */
1716
1717 #define Pmode QImode
1718
1719 /* On the C4x we can write the following code. We have to clear the cache
1720 every time we execute it because the data in the stack could change.
1721
1722 laj $+4
1723 addi3 4,r11,ar0
1724 lda *ar0,ar1
1725 lda *+ar0(1),ar0
1726 bud ar1
1727 nop
1728 nop
1729 or 1000h,st
1730 .word FNADDR
1731 .word CXT
1732
1733 On the c3x this is a bit more difficult. We have to write self
1734 modifying code here. So we have to clear the cache every time
1735 we execute it because the data in the stack could change.
1736
1737 ldiu TOP_OF_FUNCTION,ar1
1738 lsh 16,ar1
1739 or BOTTOM_OF_FUNCTION,ar1
1740 ldiu TOP_OF_STATIC,ar0
1741 bud ar1
1742 lsh 16,ar0
1743 or BOTTOM_OF_STATIC,ar0
1744 or 1000h,st
1745
1746 */
1747
1748 #define TRAMPOLINE_SIZE (TARGET_C3X ? 8 : 10)
1749
1750 #define TRAMPOLINE_TEMPLATE(FILE) \
1751 { \
1752 if (TARGET_C3X) \
1753 { \
1754 fprintf (FILE, "\tldiu\t0,ar1\n"); \
1755 fprintf (FILE, "\tlsh\t16,ar1\n"); \
1756 fprintf (FILE, "\tor\t0,ar1\n"); \
1757 fprintf (FILE, "\tldiu\t0,ar0\n"); \
1758 fprintf (FILE, "\tbud\tar1\n"); \
1759 fprintf (FILE, "\tlsh\t16,ar0\n"); \
1760 fprintf (FILE, "\tor\t0,ar0\n"); \
1761 fprintf (FILE, "\tor\t1000h,st\n"); \
1762 } \
1763 else \
1764 { \
1765 fprintf (FILE, "\tlaj\t$+4\n"); \
1766 fprintf (FILE, "\taddi3\t4,r11,ar0\n"); \
1767 fprintf (FILE, "\tlda\t*ar0,ar1\n"); \
1768 fprintf (FILE, "\tlda\t*+ar0(1),ar0\n"); \
1769 fprintf (FILE, "\tbud\tar1\n"); \
1770 fprintf (FILE, "\tnop\n"); \
1771 fprintf (FILE, "\tnop\n"); \
1772 fprintf (FILE, "\tor\t1000h,st\n"); \
1773 fprintf (FILE, "\t.word\t0\n"); \
1774 fprintf (FILE, "\t.word\t0\n"); \
1775 } \
1776 }
1777
1778 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1779 { \
1780 if (TARGET_C3X) \
1781 { \
1782 rtx tmp1, tmp2; \
1783 tmp1 = expand_shift (RSHIFT_EXPR, QImode, FNADDR, \
1784 size_int (16), 0, 1); \
1785 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
1786 GEN_INT (0x5069), size_int (16), 0, 1); \
1787 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
1788 emit_move_insn (gen_rtx (MEM, QImode, \
1789 plus_constant (tramp, 0)), tmp1); \
1790 tmp1 = expand_and (QImode, FNADDR, GEN_INT (0xffff), 0); \
1791 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
1792 GEN_INT (0x1069), size_int (16), 0, 1); \
1793 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
1794 emit_move_insn (gen_rtx (MEM, QImode, \
1795 plus_constant (tramp, 2)), tmp1); \
1796 tmp1 = expand_shift (RSHIFT_EXPR, QImode, CXT, \
1797 size_int (16), 0, 1); \
1798 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
1799 GEN_INT (0x5068), size_int (16), 0, 1); \
1800 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
1801 emit_move_insn (gen_rtx (MEM, QImode, \
1802 plus_constant (tramp, 3)), tmp1); \
1803 tmp1 = expand_and (QImode, CXT, GEN_INT (0xffff), 0); \
1804 tmp2 = expand_shift (LSHIFT_EXPR, QImode, \
1805 GEN_INT (0x1068), size_int (16), 0, 1); \
1806 emit_insn (gen_iorqi3 (tmp1, tmp1, tmp2)); \
1807 emit_move_insn (gen_rtx (MEM, QImode, \
1808 plus_constant (tramp, 6)), tmp1); \
1809 } \
1810 else \
1811 { \
1812 emit_move_insn (gen_rtx (MEM, QImode, \
1813 plus_constant (TRAMP, 8)), FNADDR); \
1814 emit_move_insn (gen_rtx (MEM, QImode, \
1815 plus_constant (TRAMP, 9)), CXT); \
1816 } \
1817 }
1818
1819 /* Specify the machine mode that this machine uses for the index in
1820 the tablejump instruction. */
1821
1822 #define CASE_VECTOR_MODE Pmode
1823
1824 /* Max number of (32-bit) bytes we can move from memory to memory
1825 in one reasonably fast instruction. */
1826
1827 #define MOVE_MAX 1
1828
1829 /* MOVE_RATIO is the number of move instructions that is better than a
1830 block move. */
1831
1832 #define MOVE_RATIO 3
1833
1834 #define BSS_SECTION_ASM_OP "\t.bss"
1835
1836 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
1837 fprintf (FILE, "\tpush\t%s\n", reg_names[REGNO])
1838
1839 /* This is how to output an insn to pop a register from the stack.
1840 It need not be very fast code. */
1841
1842 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \
1843 fprintf (FILE, "\tpop\t%s\n", reg_names[REGNO])
1844
1845 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1846 is done just by pretending it is already truncated. */
1847
1848 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1849
1850 #define DBR_OUTPUT_SEQEND(FILE) \
1851 if (final_sequence != NULL_RTX) \
1852 { \
1853 int count; \
1854 rtx insn = XVECEXP (final_sequence, 0, 0); \
1855 int laj = GET_CODE (insn) == CALL_INSN \
1856 || (GET_CODE (insn) == INSN \
1857 && GET_CODE (PATTERN (insn)) == TRAP_IF);\
1858 \
1859 count = dbr_sequence_length(); \
1860 while (count < (laj ? 2 : 3)) \
1861 { \
1862 fputs("\tnop\n", FILE); \
1863 count++; \
1864 } \
1865 if (laj) \
1866 fputs("\tpush\tr11\n", FILE); \
1867 }
1868
1869 #define NO_FUNCTION_CSE
1870
1871 /* We don't want a leading tab. */
1872
1873 #define ASM_OUTPUT_ASM(FILE, STRING) fprintf (FILE, "%s\n", STRING)
1874
1875 /* Define the codes that are matched by predicates in c4x.c. */
1876
1877 #define PREDICATE_CODES \
1878 {"fp_zero_operand", {CONST_DOUBLE}}, \
1879 {"const_operand", {CONST_INT, CONST_DOUBLE}}, \
1880 {"stik_const_operand", {CONST_INT}}, \
1881 {"not_const_operand", {CONST_INT}}, \
1882 {"reg_operand", {REG, SUBREG}}, \
1883 {"reg_or_const_operand", {REG, SUBREG, CONST_INT, CONST_DOUBLE}},\
1884 {"r0r1_reg_operand", {REG, SUBREG}}, \
1885 {"r2r3_reg_operand", {REG, SUBREG}}, \
1886 {"ext_low_reg_operand", {REG, SUBREG}}, \
1887 {"ext_reg_operand", {REG, SUBREG}}, \
1888 {"std_reg_operand", {REG, SUBREG}}, \
1889 {"std_or_reg_operand", {REG, SUBREG}}, \
1890 {"addr_reg_operand", {REG, SUBREG}}, \
1891 {"index_reg_operand", {REG, SUBREG}}, \
1892 {"dp_reg_operand", {REG}}, \
1893 {"sp_reg_operand", {REG}}, \
1894 {"st_reg_operand", {REG}}, \
1895 {"rc_reg_operand", {REG}}, \
1896 {"call_address_operand", {REG, SYMBOL_REF, LABEL_REF, CONST}}, \
1897 {"dst_operand", {SUBREG, REG, MEM}}, \
1898 {"src_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
1899 {"src_hi_operand", {SUBREG, REG, MEM, CONST_DOUBLE}}, \
1900 {"lsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
1901 {"tsrc_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
1902 {"nonimmediate_src_operand", {SUBREG, REG, MEM}}, \
1903 {"nonimmediate_lsrc_operand", {SUBREG, REG, MEM}}, \
1904 {"any_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE}}, \
1905 {"par_ind_operand", {MEM}}, \
1906 {"parallel_operand", {SUBREG, REG, MEM}}, \
1907 {"symbolic_address_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
1908 {"mem_operand", {MEM}},
1909
1910
1911 /* Define the intrinsic functions for the c3x/c4x. */
1912
1913 enum c4x_builtins
1914 {
1915 /* intrinsic name */
1916 C4X_BUILTIN_FIX, /* fast_ftoi */
1917 C4X_BUILTIN_FIX_ANSI, /* ansi_ftoi */
1918 C4X_BUILTIN_MPYI, /* fast_imult (only C3x) */
1919 C4X_BUILTIN_TOIEEE, /* toieee (only C4x) */
1920 C4X_BUILTIN_FRIEEE, /* frieee (only C4x) */
1921 C4X_BUILTIN_RCPF /* fast_invf (only C4x) */
1922 };
1923
1924
1925 /* Hack to overcome use of libgcc2.c using auto-host.h to determine
1926 HAVE_GAS_HIDDEN. */
1927 #undef HAVE_GAS_HIDDEN
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