| blob | d9f9e09e8087db83c9b2fc9f207e54b04e40413a |
1 ;; Machine description for DEC Alpha for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 ;; 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
5 ;;
6 ;; This file is part of GCC.
7 ;;
8 ;; GCC is free software; you can redistribute it and/or modify
9 ;; it under the terms of the GNU General Public License as published by
10 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; any later version.
12 ;;
13 ;; GCC is distributed in the hope that it will be useful,
14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ;; GNU General Public License for more details.
17 ;;
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING. If not, write to
20 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 ;; Boston, MA 02110-1301, USA.
23 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
25 ;; Uses of UNSPEC in this file:
27 (define_constants
28 [(UNSPEC_ARG_HOME 0)
29 (UNSPEC_INSXH 2)
30 (UNSPEC_MSKXH 3)
31 (UNSPEC_CVTQL 4)
32 (UNSPEC_CVTLQ 5)
33 (UNSPEC_UMK_LAUM 6)
34 (UNSPEC_UMK_LALM 7)
35 (UNSPEC_UMK_LAL 8)
36 (UNSPEC_UMK_LOAD_CIW 9)
37 (UNSPEC_LDGP2 10)
38 (UNSPEC_LITERAL 11)
39 (UNSPEC_LITUSE 12)
40 (UNSPEC_SIBCALL 13)
41 (UNSPEC_SYMBOL 14)
43 ;; TLS Support
44 (UNSPEC_TLSGD_CALL 15)
45 (UNSPEC_TLSLDM_CALL 16)
46 (UNSPEC_TLSGD 17)
47 (UNSPEC_TLSLDM 18)
48 (UNSPEC_DTPREL 19)
49 (UNSPEC_TPREL 20)
50 (UNSPEC_TP 21)
52 ;; Builtins
53 (UNSPEC_CMPBGE 22)
54 (UNSPEC_ZAP 23)
55 (UNSPEC_AMASK 24)
56 (UNSPEC_IMPLVER 25)
57 (UNSPEC_PERR 26)
58 (UNSPEC_COPYSIGN 27)
60 ;; Atomic operations
61 (UNSPEC_MB 28)
62 (UNSPEC_ATOMIC 31)
63 (UNSPEC_CMPXCHG 32)
64 (UNSPEC_XCHG 33)
65 ])
67 ;; UNSPEC_VOLATILE:
69 (define_constants
70 [(UNSPECV_IMB 0)
71 (UNSPECV_BLOCKAGE 1)
72 (UNSPECV_SETJMPR 2) ; builtin_setjmp_receiver
73 (UNSPECV_LONGJMP 3) ; builtin_longjmp
74 (UNSPECV_TRAPB 4)
75 (UNSPECV_PSPL 5) ; prologue_stack_probe_loop
76 (UNSPECV_REALIGN 6)
77 (UNSPECV_EHR 7) ; exception_receiver
78 (UNSPECV_MCOUNT 8)
79 (UNSPECV_FORCE_MOV 9)
80 (UNSPECV_LDGP1 10)
81 (UNSPECV_PLDGP2 11) ; prologue ldgp
82 (UNSPECV_SET_TP 12)
83 (UNSPECV_RPCC 13)
84 (UNSPECV_SETJMPR_ER 14) ; builtin_setjmp_receiver fragment
85 (UNSPECV_LL 15) ; load-locked
86 (UNSPECV_SC 16) ; store-conditional
87 ])
89 ;; Where necessary, the suffixes _le and _be are used to distinguish between
90 ;; little-endian and big-endian patterns.
91 ;;
92 ;; Note that the Unicos/Mk assembler does not support the following
93 ;; opcodes: mov, fmov, nop, fnop, unop.
94 \f
95 ;; Processor type -- this attribute must exactly match the processor_type
96 ;; enumeration in alpha.h.
98 (define_attr "tune" "ev4,ev5,ev6"
99 (const (symbol_ref "alpha_tune")))
101 ;; Define an insn type attribute. This is used in function unit delay
102 ;; computations, among other purposes. For the most part, we use the names
103 ;; defined in the EV4 documentation, but add a few that we have to know about
104 ;; separately.
106 (define_attr "type"
107 "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov,
108 icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,mb,ld_l,st_c,
109 multi,none"
110 (const_string "iadd"))
112 ;; Describe a user's asm statement.
113 (define_asm_attributes
114 [(set_attr "type" "multi")])
116 ;; Define the operand size an insn operates on. Used primarily by mul
117 ;; and div operations that have size dependent timings.
119 (define_attr "opsize" "si,di,udi"
120 (const_string "di"))
122 ;; The TRAP attribute marks instructions that may generate traps
123 ;; (which are imprecise and may need a trapb if software completion
124 ;; is desired).
126 (define_attr "trap" "no,yes"
127 (const_string "no"))
129 ;; The ROUND_SUFFIX attribute marks which instructions require a
130 ;; rounding-mode suffix. The value NONE indicates no suffix,
131 ;; the value NORMAL indicates a suffix controlled by alpha_fprm.
133 (define_attr "round_suffix" "none,normal,c"
134 (const_string "none"))
136 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix:
137 ;; NONE no suffix
138 ;; SU accepts only /su (cmpt et al)
139 ;; SUI accepts only /sui (cvtqt and cvtqs)
140 ;; V_SV accepts /v and /sv (cvtql only)
141 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only)
142 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions)
143 ;;
144 ;; The actual suffix emitted is controlled by alpha_fptm.
146 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui"
147 (const_string "none"))
149 ;; The length of an instruction sequence in bytes.
151 (define_attr "length" ""
152 (const_int 4))
154 ;; The USEGP attribute marks instructions that have relocations that use
155 ;; the GP.
157 (define_attr "usegp" "no,yes"
158 (cond [(eq_attr "type" "ldsym,jsr")
159 (const_string "yes")
160 (eq_attr "type" "ild,fld,ist,fst")
161 (symbol_ref "alpha_find_lo_sum_using_gp(insn)")
162 ]
163 (const_string "no")))
165 ;; The CANNOT_COPY attribute marks instructions with relocations that
166 ;; cannot easily be duplicated. This includes insns with gpdisp relocs
167 ;; since they have to stay in 1-1 correspondence with one another. This
168 ;; also includes jsr insns, since they must stay in correspondence with
169 ;; the immediately following gpdisp instructions.
171 (define_attr "cannot_copy" "false,true"
172 (const_string "false"))
173 \f
174 ;; Include scheduling descriptions.
176 (include "ev4.md")
177 (include "ev5.md")
178 (include "ev6.md")
180 \f
181 ;; Include predicate definitions
183 (include "predicates.md")
185 \f
186 ;; First define the arithmetic insns. Note that the 32-bit forms also
187 ;; sign-extend.
189 ;; Handle 32-64 bit extension from memory to a floating point register
190 ;; specially, since this occurs frequently in int->double conversions.
191 ;;
192 ;; Note that while we must retain the =f case in the insn for reload's
193 ;; benefit, it should be eliminated after reload, so we should never emit
194 ;; code for that case. But we don't reject the possibility.
196 (define_expand "extendsidi2"
197 [(set (match_operand:DI 0 "register_operand" "")
198 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
199 ""
200 "")
202 (define_insn "*cvtlq"
203 [(set (match_operand:DI 0 "register_operand" "=f")
204 (unspec:DI [(match_operand:SF 1 "reg_or_0_operand" "fG")]
205 UNSPEC_CVTLQ))]
206 ""
207 "cvtlq %1,%0"
208 [(set_attr "type" "fadd")])
210 (define_insn "*extendsidi2_1"
211 [(set (match_operand:DI 0 "register_operand" "=r,r,!*f")
212 (sign_extend:DI
213 (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))]
214 ""
215 "@
216 addl $31,%1,%0
217 ldl %0,%1
218 lds %0,%1\;cvtlq %0,%0"
219 [(set_attr "type" "iadd,ild,fld")
220 (set_attr "length" "*,*,8")])
222 (define_split
223 [(set (match_operand:DI 0 "hard_fp_register_operand" "")
224 (sign_extend:DI (match_operand:SI 1 "memory_operand" "")))]
225 "reload_completed"
226 [(set (match_dup 2) (match_dup 1))
227 (set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))]
228 {
229 operands[1] = adjust_address (operands[1], SFmode, 0);
230 operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0]));
231 })
233 ;; Optimize sign-extension of SImode loads. This shows up in the wake of
234 ;; reload when converting fp->int.
236 (define_peephole2
237 [(set (match_operand:SI 0 "hard_int_register_operand" "")
238 (match_operand:SI 1 "memory_operand" ""))
239 (set (match_operand:DI 2 "hard_int_register_operand" "")
240 (sign_extend:DI (match_dup 0)))]
241 "true_regnum (operands[0]) == true_regnum (operands[2])
242 || peep2_reg_dead_p (2, operands[0])"
243 [(set (match_dup 2)
244 (sign_extend:DI (match_dup 1)))]
245 "")
247 ;; Don't say we have addsi3 if optimizing. This generates better code. We
248 ;; have the anonymous addsi3 pattern below in case combine wants to make it.
249 (define_expand "addsi3"
250 [(set (match_operand:SI 0 "register_operand" "")
251 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "")
252 (match_operand:SI 2 "add_operand" "")))]
253 "! optimize"
254 "")
256 (define_insn "*addsi_internal"
257 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
258 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ")
259 (match_operand:SI 2 "add_operand" "rI,O,K,L")))]
260 ""
261 "@
262 addl %r1,%2,%0
263 subl %r1,%n2,%0
264 lda %0,%2(%r1)
265 ldah %0,%h2(%r1)")
267 (define_split
268 [(set (match_operand:SI 0 "register_operand" "")
269 (plus:SI (match_operand:SI 1 "register_operand" "")
270 (match_operand:SI 2 "const_int_operand" "")))]
271 "! add_operand (operands[2], SImode)"
272 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
273 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
274 {
275 HOST_WIDE_INT val = INTVAL (operands[2]);
276 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
277 HOST_WIDE_INT rest = val - low;
279 operands[3] = GEN_INT (rest);
280 operands[4] = GEN_INT (low);
281 })
283 (define_insn "*addsi_se"
284 [(set (match_operand:DI 0 "register_operand" "=r,r")
285 (sign_extend:DI
286 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
287 (match_operand:SI 2 "sext_add_operand" "rI,O"))))]
288 ""
289 "@
290 addl %r1,%2,%0
291 subl %r1,%n2,%0")
293 (define_insn "*addsi_se2"
294 [(set (match_operand:DI 0 "register_operand" "=r,r")
295 (sign_extend:DI
296 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
297 (match_operand:DI 2 "sext_add_operand" "rI,O"))
298 0)))]
299 ""
300 "@
301 addl %r1,%2,%0
302 subl %r1,%n2,%0")
304 (define_split
305 [(set (match_operand:DI 0 "register_operand" "")
306 (sign_extend:DI
307 (plus:SI (match_operand:SI 1 "reg_not_elim_operand" "")
308 (match_operand:SI 2 "const_int_operand" ""))))
309 (clobber (match_operand:SI 3 "reg_not_elim_operand" ""))]
310 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0
311 && INTVAL (operands[2]) % 4 == 0"
312 [(set (match_dup 3) (match_dup 4))
313 (set (match_dup 0) (sign_extend:DI (plus:SI (mult:SI (match_dup 3)
314 (match_dup 5))
315 (match_dup 1))))]
316 {
317 HOST_WIDE_INT val = INTVAL (operands[2]) / 4;
318 int mult = 4;
320 if (val % 2 == 0)
321 val /= 2, mult = 8;
323 operands[4] = GEN_INT (val);
324 operands[5] = GEN_INT (mult);
325 })
327 (define_split
328 [(set (match_operand:DI 0 "register_operand" "")
329 (sign_extend:DI
330 (plus:SI (match_operator:SI 1 "comparison_operator"
331 [(match_operand 2 "" "")
332 (match_operand 3 "" "")])
333 (match_operand:SI 4 "add_operand" ""))))
334 (clobber (match_operand:DI 5 "register_operand" ""))]
335 ""
336 [(set (match_dup 5) (match_dup 6))
337 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))]
338 {
339 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
340 operands[2], operands[3]);
341 operands[7] = gen_lowpart (SImode, operands[5]);
342 })
344 (define_insn "addvsi3"
345 [(set (match_operand:SI 0 "register_operand" "=r,r")
346 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
347 (match_operand:SI 2 "sext_add_operand" "rI,O")))
348 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
349 (sign_extend:DI (match_dup 2)))
350 (sign_extend:DI (plus:SI (match_dup 1)
351 (match_dup 2))))
352 (const_int 0))]
353 ""
354 "@
355 addlv %r1,%2,%0
356 sublv %r1,%n2,%0")
358 (define_expand "adddi3"
359 [(set (match_operand:DI 0 "register_operand" "")
360 (plus:DI (match_operand:DI 1 "register_operand" "")
361 (match_operand:DI 2 "add_operand" "")))]
362 ""
363 "")
365 (define_insn "*adddi_er_lo16_dtp"
366 [(set (match_operand:DI 0 "register_operand" "=r")
367 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
368 (match_operand:DI 2 "dtp16_symbolic_operand" "")))]
369 "HAVE_AS_TLS"
370 "lda %0,%2(%1)\t\t!dtprel")
372 (define_insn "*adddi_er_hi32_dtp"
373 [(set (match_operand:DI 0 "register_operand" "=r")
374 (plus:DI (match_operand:DI 1 "register_operand" "r")
375 (high:DI (match_operand:DI 2 "dtp32_symbolic_operand" ""))))]
376 "HAVE_AS_TLS"
377 "ldah %0,%2(%1)\t\t!dtprelhi")
379 (define_insn "*adddi_er_lo32_dtp"
380 [(set (match_operand:DI 0 "register_operand" "=r")
381 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
382 (match_operand:DI 2 "dtp32_symbolic_operand" "")))]
383 "HAVE_AS_TLS"
384 "lda %0,%2(%1)\t\t!dtprello")
386 (define_insn "*adddi_er_lo16_tp"
387 [(set (match_operand:DI 0 "register_operand" "=r")
388 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
389 (match_operand:DI 2 "tp16_symbolic_operand" "")))]
390 "HAVE_AS_TLS"
391 "lda %0,%2(%1)\t\t!tprel")
393 (define_insn "*adddi_er_hi32_tp"
394 [(set (match_operand:DI 0 "register_operand" "=r")
395 (plus:DI (match_operand:DI 1 "register_operand" "r")
396 (high:DI (match_operand:DI 2 "tp32_symbolic_operand" ""))))]
397 "HAVE_AS_TLS"
398 "ldah %0,%2(%1)\t\t!tprelhi")
400 (define_insn "*adddi_er_lo32_tp"
401 [(set (match_operand:DI 0 "register_operand" "=r")
402 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
403 (match_operand:DI 2 "tp32_symbolic_operand" "")))]
404 "HAVE_AS_TLS"
405 "lda %0,%2(%1)\t\t!tprello")
407 (define_insn "*adddi_er_high_l"
408 [(set (match_operand:DI 0 "register_operand" "=r")
409 (plus:DI (match_operand:DI 1 "register_operand" "r")
410 (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))]
411 "TARGET_EXPLICIT_RELOCS && reload_completed"
412 "ldah %0,%2(%1)\t\t!gprelhigh"
413 [(set_attr "usegp" "yes")])
415 (define_split
416 [(set (match_operand:DI 0 "register_operand" "")
417 (high:DI (match_operand:DI 1 "local_symbolic_operand" "")))]
418 "TARGET_EXPLICIT_RELOCS && reload_completed"
419 [(set (match_dup 0)
420 (plus:DI (match_dup 2) (high:DI (match_dup 1))))]
421 "operands[2] = pic_offset_table_rtx;")
423 ;; We used to expend quite a lot of effort choosing addq/subq/lda.
424 ;; With complications like
425 ;;
426 ;; The NT stack unwind code can't handle a subq to adjust the stack
427 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3,
428 ;; the exception handling code will loop if a subq is used and an
429 ;; exception occurs.
430 ;;
431 ;; The 19980616 change to emit prologues as RTL also confused some
432 ;; versions of GDB, which also interprets prologues. This has been
433 ;; fixed as of GDB 4.18, but it does not harm to unconditionally
434 ;; use lda here.
435 ;;
436 ;; and the fact that the three insns schedule exactly the same, it's
437 ;; just not worth the effort.
439 (define_insn "*adddi_internal"
440 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
441 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r")
442 (match_operand:DI 2 "add_operand" "r,K,L")))]
443 ""
444 "@
445 addq %1,%2,%0
446 lda %0,%2(%1)
447 ldah %0,%h2(%1)")
449 ;; ??? Allow large constants when basing off the frame pointer or some
450 ;; virtual register that may eliminate to the frame pointer. This is
451 ;; done because register elimination offsets will change the hi/lo split,
452 ;; and if we split before reload, we will require additional instructions.
454 (define_insn "*adddi_fp_hack"
455 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
456 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r,r,r")
457 (match_operand:DI 2 "const_int_operand" "K,L,n")))]
458 "NONSTRICT_REG_OK_FP_BASE_P (operands[1])
459 && INTVAL (operands[2]) >= 0
460 /* This is the largest constant an lda+ldah pair can add, minus
461 an upper bound on the displacement between SP and AP during
462 register elimination. See INITIAL_ELIMINATION_OFFSET. */
463 && INTVAL (operands[2])
464 < (0x7fff8000
465 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD
466 - ALPHA_ROUND(current_function_outgoing_args_size)
467 - (ALPHA_ROUND (get_frame_size ()
468 + max_reg_num () * UNITS_PER_WORD
469 + current_function_pretend_args_size)
470 - current_function_pretend_args_size))"
471 "@
472 lda %0,%2(%1)
473 ldah %0,%h2(%1)
474 #")
476 ;; Don't do this if we are adjusting SP since we don't want to do it
477 ;; in two steps. Don't split FP sources for the reason listed above.
478 (define_split
479 [(set (match_operand:DI 0 "register_operand" "")
480 (plus:DI (match_operand:DI 1 "register_operand" "")
481 (match_operand:DI 2 "const_int_operand" "")))]
482 "! add_operand (operands[2], DImode)
483 && operands[0] != stack_pointer_rtx
484 && operands[1] != frame_pointer_rtx
485 && operands[1] != arg_pointer_rtx"
486 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3)))
487 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))]
488 {
489 HOST_WIDE_INT val = INTVAL (operands[2]);
490 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000);
491 HOST_WIDE_INT rest = val - low;
493 operands[4] = GEN_INT (low);
494 if (CONST_OK_FOR_LETTER_P (rest, 'L'))
495 operands[3] = GEN_INT (rest);
496 else if (! no_new_pseudos)
497 {
498 operands[3] = gen_reg_rtx (DImode);
499 emit_move_insn (operands[3], operands[2]);
500 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3]));
501 DONE;
502 }
503 else
504 FAIL;
505 })
507 (define_insn "*saddl"
508 [(set (match_operand:SI 0 "register_operand" "=r,r")
509 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
510 (match_operand:SI 2 "const48_operand" "I,I"))
511 (match_operand:SI 3 "sext_add_operand" "rI,O")))]
512 ""
513 "@
514 s%2addl %1,%3,%0
515 s%2subl %1,%n3,%0")
517 (define_insn "*saddl_se"
518 [(set (match_operand:DI 0 "register_operand" "=r,r")
519 (sign_extend:DI
520 (plus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r")
521 (match_operand:SI 2 "const48_operand" "I,I"))
522 (match_operand:SI 3 "sext_add_operand" "rI,O"))))]
523 ""
524 "@
525 s%2addl %1,%3,%0
526 s%2subl %1,%n3,%0")
528 (define_split
529 [(set (match_operand:DI 0 "register_operand" "")
530 (sign_extend:DI
531 (plus:SI (mult:SI (match_operator:SI 1 "comparison_operator"
532 [(match_operand 2 "" "")
533 (match_operand 3 "" "")])
534 (match_operand:SI 4 "const48_operand" ""))
535 (match_operand:SI 5 "sext_add_operand" ""))))
536 (clobber (match_operand:DI 6 "reg_not_elim_operand" ""))]
537 ""
538 [(set (match_dup 6) (match_dup 7))
539 (set (match_dup 0)
540 (sign_extend:DI (plus:SI (mult:SI (match_dup 8) (match_dup 4))
541 (match_dup 5))))]
542 {
543 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode,
544 operands[2], operands[3]);
545 operands[8] = gen_lowpart (SImode, operands[6]);
546 })
548 (define_insn "*saddq"
549 [(set (match_operand:DI 0 "register_operand" "=r,r")
550 (plus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r,r")
551 (match_operand:DI 2 "const48_operand" "I,I"))
552 (match_operand:DI 3 "sext_add_operand" "rI,O")))]
553 ""
554 "@
555 s%2addq %1,%3,%0
556 s%2subq %1,%n3,%0")
558 (define_insn "addvdi3"
559 [(set (match_operand:DI 0 "register_operand" "=r,r")
560 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
561 (match_operand:DI 2 "sext_add_operand" "rI,O")))
562 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
563 (sign_extend:TI (match_dup 2)))
564 (sign_extend:TI (plus:DI (match_dup 1)
565 (match_dup 2))))
566 (const_int 0))]
567 ""
568 "@
569 addqv %r1,%2,%0
570 subqv %r1,%n2,%0")
572 (define_insn "negsi2"
573 [(set (match_operand:SI 0 "register_operand" "=r")
574 (neg:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
575 ""
576 "subl $31,%1,%0")
578 (define_insn "*negsi_se"
579 [(set (match_operand:DI 0 "register_operand" "=r")
580 (sign_extend:DI (neg:SI
581 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))]
582 ""
583 "subl $31,%1,%0")
585 (define_insn "negvsi2"
586 [(set (match_operand:SI 0 "register_operand" "=r")
587 (neg:SI (match_operand:SI 1 "register_operand" "r")))
588 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
589 (sign_extend:DI (neg:SI (match_dup 1))))
590 (const_int 0))]
591 ""
592 "sublv $31,%1,%0")
594 (define_insn "negdi2"
595 [(set (match_operand:DI 0 "register_operand" "=r")
596 (neg:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
597 ""
598 "subq $31,%1,%0")
600 (define_insn "negvdi2"
601 [(set (match_operand:DI 0 "register_operand" "=r")
602 (neg:DI (match_operand:DI 1 "register_operand" "r")))
603 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
604 (sign_extend:TI (neg:DI (match_dup 1))))
605 (const_int 0))]
606 ""
607 "subqv $31,%1,%0")
609 (define_expand "subsi3"
610 [(set (match_operand:SI 0 "register_operand" "")
611 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "")
612 (match_operand:SI 2 "reg_or_8bit_operand" "")))]
613 "! optimize"
614 "")
616 (define_insn "*subsi_internal"
617 [(set (match_operand:SI 0 "register_operand" "=r")
618 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
619 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
620 ""
621 "subl %r1,%2,%0")
623 (define_insn "*subsi_se"
624 [(set (match_operand:DI 0 "register_operand" "=r")
625 (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
626 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
627 ""
628 "subl %r1,%2,%0")
630 (define_insn "*subsi_se2"
631 [(set (match_operand:DI 0 "register_operand" "=r")
632 (sign_extend:DI
633 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
634 (match_operand:DI 2 "reg_or_8bit_operand" "rI"))
635 0)))]
636 ""
637 "subl %r1,%2,%0")
639 (define_insn "subvsi3"
640 [(set (match_operand:SI 0 "register_operand" "=r")
641 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ")
642 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
643 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
644 (sign_extend:DI (match_dup 2)))
645 (sign_extend:DI (minus:SI (match_dup 1)
646 (match_dup 2))))
647 (const_int 0))]
648 ""
649 "sublv %r1,%2,%0")
651 (define_insn "subdi3"
652 [(set (match_operand:DI 0 "register_operand" "=r")
653 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
654 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
655 ""
656 "subq %r1,%2,%0")
658 (define_insn "*ssubl"
659 [(set (match_operand:SI 0 "register_operand" "=r")
660 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
661 (match_operand:SI 2 "const48_operand" "I"))
662 (match_operand:SI 3 "reg_or_8bit_operand" "rI")))]
663 ""
664 "s%2subl %1,%3,%0")
666 (define_insn "*ssubl_se"
667 [(set (match_operand:DI 0 "register_operand" "=r")
668 (sign_extend:DI
669 (minus:SI (mult:SI (match_operand:SI 1 "reg_not_elim_operand" "r")
670 (match_operand:SI 2 "const48_operand" "I"))
671 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))]
672 ""
673 "s%2subl %1,%3,%0")
675 (define_insn "*ssubq"
676 [(set (match_operand:DI 0 "register_operand" "=r")
677 (minus:DI (mult:DI (match_operand:DI 1 "reg_not_elim_operand" "r")
678 (match_operand:DI 2 "const48_operand" "I"))
679 (match_operand:DI 3 "reg_or_8bit_operand" "rI")))]
680 ""
681 "s%2subq %1,%3,%0")
683 (define_insn "subvdi3"
684 [(set (match_operand:DI 0 "register_operand" "=r")
685 (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
686 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
687 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
688 (sign_extend:TI (match_dup 2)))
689 (sign_extend:TI (minus:DI (match_dup 1)
690 (match_dup 2))))
691 (const_int 0))]
692 ""
693 "subqv %r1,%2,%0")
695 ;; The Unicos/Mk assembler doesn't support mull.
697 (define_insn "mulsi3"
698 [(set (match_operand:SI 0 "register_operand" "=r")
699 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
700 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))]
701 "!TARGET_ABI_UNICOSMK"
702 "mull %r1,%2,%0"
703 [(set_attr "type" "imul")
704 (set_attr "opsize" "si")])
706 (define_insn "*mulsi_se"
707 [(set (match_operand:DI 0 "register_operand" "=r")
708 (sign_extend:DI
709 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
710 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))]
711 "!TARGET_ABI_UNICOSMK"
712 "mull %r1,%2,%0"
713 [(set_attr "type" "imul")
714 (set_attr "opsize" "si")])
716 (define_insn "mulvsi3"
717 [(set (match_operand:SI 0 "register_operand" "=r")
718 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ")
719 (match_operand:SI 2 "reg_or_8bit_operand" "rI")))
720 (trap_if (ne (mult:DI (sign_extend:DI (match_dup 1))
721 (sign_extend:DI (match_dup 2)))
722 (sign_extend:DI (mult:SI (match_dup 1)
723 (match_dup 2))))
724 (const_int 0))]
725 "!TARGET_ABI_UNICOSMK"
726 "mullv %r1,%2,%0"
727 [(set_attr "type" "imul")
728 (set_attr "opsize" "si")])
730 (define_insn "muldi3"
731 [(set (match_operand:DI 0 "register_operand" "=r")
732 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
733 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))]
734 ""
735 "mulq %r1,%2,%0"
736 [(set_attr "type" "imul")])
738 (define_insn "mulvdi3"
739 [(set (match_operand:DI 0 "register_operand" "=r")
740 (mult:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ")
741 (match_operand:DI 2 "reg_or_8bit_operand" "rI")))
742 (trap_if (ne (mult:TI (sign_extend:TI (match_dup 1))
743 (sign_extend:TI (match_dup 2)))
744 (sign_extend:TI (mult:DI (match_dup 1)
745 (match_dup 2))))
746 (const_int 0))]
747 ""
748 "mulqv %r1,%2,%0"
749 [(set_attr "type" "imul")])
751 (define_expand "umuldi3_highpart"
752 [(set (match_operand:DI 0 "register_operand" "")
753 (truncate:DI
754 (lshiftrt:TI
755 (mult:TI (zero_extend:TI
756 (match_operand:DI 1 "register_operand" ""))
757 (match_operand:DI 2 "reg_or_8bit_operand" ""))
758 (const_int 64))))]
759 ""
760 {
761 if (REG_P (operands[2]))
762 operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]);
763 })
765 (define_insn "*umuldi3_highpart_reg"
766 [(set (match_operand:DI 0 "register_operand" "=r")
767 (truncate:DI
768 (lshiftrt:TI
769 (mult:TI (zero_extend:TI
770 (match_operand:DI 1 "register_operand" "r"))
771 (zero_extend:TI
772 (match_operand:DI 2 "register_operand" "r")))
773 (const_int 64))))]
774 ""
775 "umulh %1,%2,%0"
776 [(set_attr "type" "imul")
777 (set_attr "opsize" "udi")])
779 (define_insn "*umuldi3_highpart_const"
780 [(set (match_operand:DI 0 "register_operand" "=r")
781 (truncate:DI
782 (lshiftrt:TI
783 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r"))
784 (match_operand:TI 2 "cint8_operand" "I"))
785 (const_int 64))))]
786 ""
787 "umulh %1,%2,%0"
788 [(set_attr "type" "imul")
789 (set_attr "opsize" "udi")])
790 \f
791 ;; The divide and remainder operations take their inputs from r24 and
792 ;; r25, put their output in r27, and clobber r23 and r28 on all
793 ;; systems except Unicos/Mk. On Unicos, the standard library provides
794 ;; subroutines which use the standard calling convention and work on
795 ;; DImode operands.
797 ;; ??? Force sign-extension here because some versions of OSF/1 and
798 ;; Interix/NT don't do the right thing if the inputs are not properly
799 ;; sign-extended. But Linux, for instance, does not have this
800 ;; problem. Is it worth the complication here to eliminate the sign
801 ;; extension?
803 (define_expand "divsi3"
804 [(set (match_dup 3)
805 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
806 (set (match_dup 4)
807 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
808 (parallel [(set (match_dup 5)
809 (sign_extend:DI (div:SI (match_dup 3) (match_dup 4))))
810 (clobber (reg:DI 23))
811 (clobber (reg:DI 28))])
812 (set (match_operand:SI 0 "nonimmediate_operand" "")
813 (subreg:SI (match_dup 5) 0))]
814 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
815 {
816 operands[3] = gen_reg_rtx (DImode);
817 operands[4] = gen_reg_rtx (DImode);
818 operands[5] = gen_reg_rtx (DImode);
819 })
821 (define_expand "udivsi3"
822 [(set (match_dup 3)
823 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
824 (set (match_dup 4)
825 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
826 (parallel [(set (match_dup 5)
827 (sign_extend:DI (udiv:SI (match_dup 3) (match_dup 4))))
828 (clobber (reg:DI 23))
829 (clobber (reg:DI 28))])
830 (set (match_operand:SI 0 "nonimmediate_operand" "")
831 (subreg:SI (match_dup 5) 0))]
832 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
833 {
834 operands[3] = gen_reg_rtx (DImode);
835 operands[4] = gen_reg_rtx (DImode);
836 operands[5] = gen_reg_rtx (DImode);
837 })
839 (define_expand "modsi3"
840 [(set (match_dup 3)
841 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
842 (set (match_dup 4)
843 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
844 (parallel [(set (match_dup 5)
845 (sign_extend:DI (mod:SI (match_dup 3) (match_dup 4))))
846 (clobber (reg:DI 23))
847 (clobber (reg:DI 28))])
848 (set (match_operand:SI 0 "nonimmediate_operand" "")
849 (subreg:SI (match_dup 5) 0))]
850 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
851 {
852 operands[3] = gen_reg_rtx (DImode);
853 operands[4] = gen_reg_rtx (DImode);
854 operands[5] = gen_reg_rtx (DImode);
855 })
857 (define_expand "umodsi3"
858 [(set (match_dup 3)
859 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))
860 (set (match_dup 4)
861 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "")))
862 (parallel [(set (match_dup 5)
863 (sign_extend:DI (umod:SI (match_dup 3) (match_dup 4))))
864 (clobber (reg:DI 23))
865 (clobber (reg:DI 28))])
866 (set (match_operand:SI 0 "nonimmediate_operand" "")
867 (subreg:SI (match_dup 5) 0))]
868 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
869 {
870 operands[3] = gen_reg_rtx (DImode);
871 operands[4] = gen_reg_rtx (DImode);
872 operands[5] = gen_reg_rtx (DImode);
873 })
875 (define_expand "divdi3"
876 [(parallel [(set (match_operand:DI 0 "register_operand" "")
877 (div:DI (match_operand:DI 1 "register_operand" "")
878 (match_operand:DI 2 "register_operand" "")))
879 (clobber (reg:DI 23))
880 (clobber (reg:DI 28))])]
881 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
882 "")
884 (define_expand "udivdi3"
885 [(parallel [(set (match_operand:DI 0 "register_operand" "")
886 (udiv:DI (match_operand:DI 1 "register_operand" "")
887 (match_operand:DI 2 "register_operand" "")))
888 (clobber (reg:DI 23))
889 (clobber (reg:DI 28))])]
890 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
891 "")
893 (define_expand "moddi3"
894 [(use (match_operand:DI 0 "register_operand" ""))
895 (use (match_operand:DI 1 "register_operand" ""))
896 (use (match_operand:DI 2 "register_operand" ""))]
897 "!TARGET_ABI_OPEN_VMS"
898 {
899 if (TARGET_ABI_UNICOSMK)
900 emit_insn (gen_moddi3_umk (operands[0], operands[1], operands[2]));
901 else
902 emit_insn (gen_moddi3_dft (operands[0], operands[1], operands[2]));
903 DONE;
904 })
906 (define_expand "moddi3_dft"
907 [(parallel [(set (match_operand:DI 0 "register_operand" "")
908 (mod:DI (match_operand:DI 1 "register_operand" "")
909 (match_operand:DI 2 "register_operand" "")))
910 (clobber (reg:DI 23))
911 (clobber (reg:DI 28))])]
912 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
913 "")
915 ;; On Unicos/Mk, we do as the system's C compiler does:
916 ;; compute the quotient, multiply and subtract.
918 (define_expand "moddi3_umk"
919 [(use (match_operand:DI 0 "register_operand" ""))
920 (use (match_operand:DI 1 "register_operand" ""))
921 (use (match_operand:DI 2 "register_operand" ""))]
922 "TARGET_ABI_UNICOSMK"
923 {
924 rtx div, mul = gen_reg_rtx (DImode);
926 div = expand_binop (DImode, sdiv_optab, operands[1], operands[2],
927 NULL_RTX, 0, OPTAB_LIB);
928 div = force_reg (DImode, div);
929 emit_insn (gen_muldi3 (mul, operands[2], div));
930 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
931 DONE;
932 })
934 (define_expand "umoddi3"
935 [(use (match_operand:DI 0 "register_operand" ""))
936 (use (match_operand:DI 1 "register_operand" ""))
937 (use (match_operand:DI 2 "register_operand" ""))]
938 "! TARGET_ABI_OPEN_VMS"
939 {
940 if (TARGET_ABI_UNICOSMK)
941 emit_insn (gen_umoddi3_umk (operands[0], operands[1], operands[2]));
942 else
943 emit_insn (gen_umoddi3_dft (operands[0], operands[1], operands[2]));
944 DONE;
945 })
947 (define_expand "umoddi3_dft"
948 [(parallel [(set (match_operand:DI 0 "register_operand" "")
949 (umod:DI (match_operand:DI 1 "register_operand" "")
950 (match_operand:DI 2 "register_operand" "")))
951 (clobber (reg:DI 23))
952 (clobber (reg:DI 28))])]
953 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
954 "")
956 (define_expand "umoddi3_umk"
957 [(use (match_operand:DI 0 "register_operand" ""))
958 (use (match_operand:DI 1 "register_operand" ""))
959 (use (match_operand:DI 2 "register_operand" ""))]
960 "TARGET_ABI_UNICOSMK"
961 {
962 rtx div, mul = gen_reg_rtx (DImode);
964 div = expand_binop (DImode, udiv_optab, operands[1], operands[2],
965 NULL_RTX, 1, OPTAB_LIB);
966 div = force_reg (DImode, div);
967 emit_insn (gen_muldi3 (mul, operands[2], div));
968 emit_insn (gen_subdi3 (operands[0], operands[1], mul));
969 DONE;
970 })
972 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as
973 ;; expanded by the assembler.
975 (define_insn_and_split "*divmodsi_internal_er"
976 [(set (match_operand:DI 0 "register_operand" "=c")
977 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
978 [(match_operand:DI 1 "register_operand" "a")
979 (match_operand:DI 2 "register_operand" "b")])))
980 (clobber (reg:DI 23))
981 (clobber (reg:DI 28))]
982 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
983 "#"
984 "&& reload_completed"
985 [(parallel [(set (match_dup 0)
986 (sign_extend:DI (match_dup 3)))
987 (use (match_dup 0))
988 (use (match_dup 4))
989 (clobber (reg:DI 23))
990 (clobber (reg:DI 28))])]
991 {
992 const char *str;
993 switch (GET_CODE (operands[3]))
994 {
995 case DIV:
996 str = "__divl";
997 break;
998 case UDIV:
999 str = "__divlu";
1000 break;
1001 case MOD:
1002 str = "__reml";
1003 break;
1004 case UMOD:
1005 str = "__remlu";
1006 break;
1007 default:
1008 gcc_unreachable ();
1009 }
1010 operands[4] = GEN_INT (alpha_next_sequence_number++);
1011 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1012 gen_rtx_SYMBOL_REF (DImode, str),
1013 operands[4]));
1014 }
1015 [(set_attr "type" "jsr")
1016 (set_attr "length" "8")])
1018 (define_insn "*divmodsi_internal_er_1"
1019 [(set (match_operand:DI 0 "register_operand" "=c")
1020 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1021 [(match_operand:DI 1 "register_operand" "a")
1022 (match_operand:DI 2 "register_operand" "b")])))
1023 (use (match_operand:DI 4 "register_operand" "c"))
1024 (use (match_operand 5 "const_int_operand" ""))
1025 (clobber (reg:DI 23))
1026 (clobber (reg:DI 28))]
1027 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1028 "jsr $23,($27),__%E3%j5"
1029 [(set_attr "type" "jsr")
1030 (set_attr "length" "4")])
1032 (define_insn "*divmodsi_internal"
1033 [(set (match_operand:DI 0 "register_operand" "=c")
1034 (sign_extend:DI (match_operator:SI 3 "divmod_operator"
1035 [(match_operand:DI 1 "register_operand" "a")
1036 (match_operand:DI 2 "register_operand" "b")])))
1037 (clobber (reg:DI 23))
1038 (clobber (reg:DI 28))]
1039 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1040 "%E3 %1,%2,%0"
1041 [(set_attr "type" "jsr")
1042 (set_attr "length" "8")])
1044 (define_insn_and_split "*divmoddi_internal_er"
1045 [(set (match_operand:DI 0 "register_operand" "=c")
1046 (match_operator:DI 3 "divmod_operator"
1047 [(match_operand:DI 1 "register_operand" "a")
1048 (match_operand:DI 2 "register_operand" "b")]))
1049 (clobber (reg:DI 23))
1050 (clobber (reg:DI 28))]
1051 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1052 "#"
1053 "&& reload_completed"
1054 [(parallel [(set (match_dup 0) (match_dup 3))
1055 (use (match_dup 0))
1056 (use (match_dup 4))
1057 (clobber (reg:DI 23))
1058 (clobber (reg:DI 28))])]
1059 {
1060 const char *str;
1061 switch (GET_CODE (operands[3]))
1062 {
1063 case DIV:
1064 str = "__divq";
1065 break;
1066 case UDIV:
1067 str = "__divqu";
1068 break;
1069 case MOD:
1070 str = "__remq";
1071 break;
1072 case UMOD:
1073 str = "__remqu";
1074 break;
1075 default:
1076 gcc_unreachable ();
1077 }
1078 operands[4] = GEN_INT (alpha_next_sequence_number++);
1079 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx,
1080 gen_rtx_SYMBOL_REF (DImode, str),
1081 operands[4]));
1082 }
1083 [(set_attr "type" "jsr")
1084 (set_attr "length" "8")])
1086 (define_insn "*divmoddi_internal_er_1"
1087 [(set (match_operand:DI 0 "register_operand" "=c")
1088 (match_operator:DI 3 "divmod_operator"
1089 [(match_operand:DI 1 "register_operand" "a")
1090 (match_operand:DI 2 "register_operand" "b")]))
1091 (use (match_operand:DI 4 "register_operand" "c"))
1092 (use (match_operand 5 "const_int_operand" ""))
1093 (clobber (reg:DI 23))
1094 (clobber (reg:DI 28))]
1095 "TARGET_EXPLICIT_RELOCS && ! TARGET_ABI_OPEN_VMS"
1096 "jsr $23,($27),__%E3%j5"
1097 [(set_attr "type" "jsr")
1098 (set_attr "length" "4")])
1100 (define_insn "*divmoddi_internal"
1101 [(set (match_operand:DI 0 "register_operand" "=c")
1102 (match_operator:DI 3 "divmod_operator"
1103 [(match_operand:DI 1 "register_operand" "a")
1104 (match_operand:DI 2 "register_operand" "b")]))
1105 (clobber (reg:DI 23))
1106 (clobber (reg:DI 28))]
1107 "! TARGET_ABI_OPEN_VMS && ! TARGET_ABI_UNICOSMK"
1108 "%E3 %1,%2,%0"
1109 [(set_attr "type" "jsr")
1110 (set_attr "length" "8")])
1111 \f
1112 ;; Next are the basic logical operations. We only expose the DImode operations
1113 ;; to the rtl expanders, but SImode versions exist for combine as well as for
1114 ;; the atomic operation splitters.
1116 (define_insn "*andsi_internal"
1117 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1118 (and:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1119 (match_operand:SI 2 "and_operand" "rI,N,MH")))]
1120 ""
1121 "@
1122 and %r1,%2,%0
1123 bic %r1,%N2,%0
1124 zapnot %r1,%m2,%0"
1125 [(set_attr "type" "ilog,ilog,shift")])
1127 (define_insn "anddi3"
1128 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1129 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ")
1130 (match_operand:DI 2 "and_operand" "rI,N,MH")))]
1131 ""
1132 "@
1133 and %r1,%2,%0
1134 bic %r1,%N2,%0
1135 zapnot %r1,%m2,%0"
1136 [(set_attr "type" "ilog,ilog,shift")])
1138 ;; There are times when we can split an AND into two AND insns. This occurs
1139 ;; when we can first clear any bytes and then clear anything else. For
1140 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07".
1141 ;; Only do this when running on 64-bit host since the computations are
1142 ;; too messy otherwise.
1144 (define_split
1145 [(set (match_operand:DI 0 "register_operand" "")
1146 (and:DI (match_operand:DI 1 "register_operand" "")
1147 (match_operand:DI 2 "const_int_operand" "")))]
1148 "HOST_BITS_PER_WIDE_INT == 64 && ! and_operand (operands[2], DImode)"
1149 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3)))
1150 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))]
1151 {
1152 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]);
1153 unsigned HOST_WIDE_INT mask2 = mask1;
1154 int i;
1156 /* For each byte that isn't all zeros, make it all ones. */
1157 for (i = 0; i < 64; i += 8)
1158 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0)
1159 mask1 |= (HOST_WIDE_INT) 0xff << i;
1161 /* Now turn on any bits we've just turned off. */
1162 mask2 |= ~ mask1;
1164 operands[3] = GEN_INT (mask1);
1165 operands[4] = GEN_INT (mask2);
1166 })
1168 (define_expand "zero_extendqihi2"
1169 [(set (match_operand:HI 0 "register_operand" "")
1170 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
1171 ""
1172 {
1173 if (! TARGET_BWX)
1174 operands[1] = force_reg (QImode, operands[1]);
1175 })
1177 (define_insn "*zero_extendqihi2_bwx"
1178 [(set (match_operand:HI 0 "register_operand" "=r,r")
1179 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1180 "TARGET_BWX"
1181 "@
1182 and %1,0xff,%0
1183 ldbu %0,%1"
1184 [(set_attr "type" "ilog,ild")])
1186 (define_insn "*zero_extendqihi2_nobwx"
1187 [(set (match_operand:HI 0 "register_operand" "=r")
1188 (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1189 "! TARGET_BWX"
1190 "and %1,0xff,%0"
1191 [(set_attr "type" "ilog")])
1193 (define_expand "zero_extendqisi2"
1194 [(set (match_operand:SI 0 "register_operand" "")
1195 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1196 ""
1197 {
1198 if (! TARGET_BWX)
1199 operands[1] = force_reg (QImode, operands[1]);
1200 })
1202 (define_insn "*zero_extendqisi2_bwx"
1203 [(set (match_operand:SI 0 "register_operand" "=r,r")
1204 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1205 "TARGET_BWX"
1206 "@
1207 and %1,0xff,%0
1208 ldbu %0,%1"
1209 [(set_attr "type" "ilog,ild")])
1211 (define_insn "*zero_extendqisi2_nobwx"
1212 [(set (match_operand:SI 0 "register_operand" "=r")
1213 (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1214 "! TARGET_BWX"
1215 "and %1,0xff,%0"
1216 [(set_attr "type" "ilog")])
1218 (define_expand "zero_extendqidi2"
1219 [(set (match_operand:DI 0 "register_operand" "")
1220 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
1221 ""
1222 {
1223 if (! TARGET_BWX)
1224 operands[1] = force_reg (QImode, operands[1]);
1225 })
1227 (define_insn "*zero_extendqidi2_bwx"
1228 [(set (match_operand:DI 0 "register_operand" "=r,r")
1229 (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,m")))]
1230 "TARGET_BWX"
1231 "@
1232 and %1,0xff,%0
1233 ldbu %0,%1"
1234 [(set_attr "type" "ilog,ild")])
1236 (define_insn "*zero_extendqidi2_nobwx"
1237 [(set (match_operand:DI 0 "register_operand" "=r")
1238 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1239 "! TARGET_BWX"
1240 "and %1,0xff,%0"
1241 [(set_attr "type" "ilog")])
1243 (define_expand "zero_extendhisi2"
1244 [(set (match_operand:SI 0 "register_operand" "")
1245 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
1246 ""
1247 {
1248 if (! TARGET_BWX)
1249 operands[1] = force_reg (HImode, operands[1]);
1250 })
1252 (define_insn "*zero_extendhisi2_bwx"
1253 [(set (match_operand:SI 0 "register_operand" "=r,r")
1254 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1255 "TARGET_BWX"
1256 "@
1257 zapnot %1,3,%0
1258 ldwu %0,%1"
1259 [(set_attr "type" "shift,ild")])
1261 (define_insn "*zero_extendhisi2_nobwx"
1262 [(set (match_operand:SI 0 "register_operand" "=r")
1263 (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1264 "! TARGET_BWX"
1265 "zapnot %1,3,%0"
1266 [(set_attr "type" "shift")])
1268 (define_expand "zero_extendhidi2"
1269 [(set (match_operand:DI 0 "register_operand" "")
1270 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
1271 ""
1272 {
1273 if (! TARGET_BWX)
1274 operands[1] = force_reg (HImode, operands[1]);
1275 })
1277 (define_insn "*zero_extendhidi2_bwx"
1278 [(set (match_operand:DI 0 "register_operand" "=r,r")
1279 (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1280 "TARGET_BWX"
1281 "@
1282 zapnot %1,3,%0
1283 ldwu %0,%1"
1284 [(set_attr "type" "shift,ild")])
1286 (define_insn "*zero_extendhidi2_nobwx"
1287 [(set (match_operand:DI 0 "register_operand" "=r")
1288 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1289 ""
1290 "zapnot %1,3,%0"
1291 [(set_attr "type" "shift")])
1293 (define_insn "zero_extendsidi2"
1294 [(set (match_operand:DI 0 "register_operand" "=r")
1295 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
1296 ""
1297 "zapnot %1,15,%0"
1298 [(set_attr "type" "shift")])
1300 (define_insn "*andnotsi3"
1301 [(set (match_operand:SI 0 "register_operand" "=r")
1302 (and:SI (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI"))
1303 (match_operand:SI 2 "reg_or_0_operand" "rJ")))]
1304 ""
1305 "bic %r2,%1,%0"
1306 [(set_attr "type" "ilog")])
1308 (define_insn "andnotdi3"
1309 [(set (match_operand:DI 0 "register_operand" "=r")
1310 (and:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1311 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1312 ""
1313 "bic %r2,%1,%0"
1314 [(set_attr "type" "ilog")])
1316 (define_insn "*iorsi_internal"
1317 [(set (match_operand:SI 0 "register_operand" "=r,r")
1318 (ior:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
1319 (match_operand:SI 2 "or_operand" "rI,N")))]
1320 ""
1321 "@
1322 bis %r1,%2,%0
1323 ornot %r1,%N2,%0"
1324 [(set_attr "type" "ilog")])
1326 (define_insn "iordi3"
1327 [(set (match_operand:DI 0 "register_operand" "=r,r")
1328 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1329 (match_operand:DI 2 "or_operand" "rI,N")))]
1330 ""
1331 "@
1332 bis %r1,%2,%0
1333 ornot %r1,%N2,%0"
1334 [(set_attr "type" "ilog")])
1336 (define_insn "*one_cmplsi_internal"
1337 [(set (match_operand:SI 0 "register_operand" "=r")
1338 (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))]
1339 ""
1340 "ornot $31,%1,%0"
1341 [(set_attr "type" "ilog")])
1343 (define_insn "one_cmpldi2"
1344 [(set (match_operand:DI 0 "register_operand" "=r")
1345 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))]
1346 ""
1347 "ornot $31,%1,%0"
1348 [(set_attr "type" "ilog")])
1350 (define_insn "*iornotsi3"
1351 [(set (match_operand:SI 0 "register_operand" "=r")
1352 (ior:SI (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI"))
1353 (match_operand:SI 2 "reg_or_0_operand" "rJ")))]
1354 ""
1355 "ornot %r2,%1,%0"
1356 [(set_attr "type" "ilog")])
1358 (define_insn "*iornotdi3"
1359 [(set (match_operand:DI 0 "register_operand" "=r")
1360 (ior:DI (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI"))
1361 (match_operand:DI 2 "reg_or_0_operand" "rJ")))]
1362 ""
1363 "ornot %r2,%1,%0"
1364 [(set_attr "type" "ilog")])
1366 (define_insn "*xorsi_internal"
1367 [(set (match_operand:SI 0 "register_operand" "=r,r")
1368 (xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ")
1369 (match_operand:SI 2 "or_operand" "rI,N")))]
1370 ""
1371 "@
1372 xor %r1,%2,%0
1373 eqv %r1,%N2,%0"
1374 [(set_attr "type" "ilog")])
1376 (define_insn "xordi3"
1377 [(set (match_operand:DI 0 "register_operand" "=r,r")
1378 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ")
1379 (match_operand:DI 2 "or_operand" "rI,N")))]
1380 ""
1381 "@
1382 xor %r1,%2,%0
1383 eqv %r1,%N2,%0"
1384 [(set_attr "type" "ilog")])
1386 (define_insn "*xornotsi3"
1387 [(set (match_operand:SI 0 "register_operand" "=r")
1388 (not:SI (xor:SI (match_operand:SI 1 "register_operand" "%rJ")
1389 (match_operand:SI 2 "register_operand" "rI"))))]
1390 ""
1391 "eqv %r1,%2,%0"
1392 [(set_attr "type" "ilog")])
1394 (define_insn "*xornotdi3"
1395 [(set (match_operand:DI 0 "register_operand" "=r")
1396 (not:DI (xor:DI (match_operand:DI 1 "register_operand" "%rJ")
1397 (match_operand:DI 2 "register_operand" "rI"))))]
1398 ""
1399 "eqv %r1,%2,%0"
1400 [(set_attr "type" "ilog")])
1401 \f
1402 ;; Handle FFS and related insns iff we support CIX.
1404 (define_expand "ffsdi2"
1405 [(set (match_dup 2)
1406 (ctz:DI (match_operand:DI 1 "register_operand" "")))
1407 (set (match_dup 3)
1408 (plus:DI (match_dup 2) (const_int 1)))
1409 (set (match_operand:DI 0 "register_operand" "")
1410 (if_then_else:DI (eq (match_dup 1) (const_int 0))
1411 (const_int 0) (match_dup 3)))]
1412 "TARGET_CIX"
1413 {
1414 operands[2] = gen_reg_rtx (DImode);
1415 operands[3] = gen_reg_rtx (DImode);
1416 })
1418 (define_insn "clzdi2"
1419 [(set (match_operand:DI 0 "register_operand" "=r")
1420 (clz:DI (match_operand:DI 1 "register_operand" "r")))]
1421 "TARGET_CIX"
1422 "ctlz %1,%0"
1423 [(set_attr "type" "mvi")])
1425 (define_insn "ctzdi2"
1426 [(set (match_operand:DI 0 "register_operand" "=r")
1427 (ctz:DI (match_operand:DI 1 "register_operand" "r")))]
1428 "TARGET_CIX"
1429 "cttz %1,%0"
1430 [(set_attr "type" "mvi")])
1432 (define_insn "popcountdi2"
1433 [(set (match_operand:DI 0 "register_operand" "=r")
1434 (popcount:DI (match_operand:DI 1 "register_operand" "r")))]
1435 "TARGET_CIX"
1436 "ctpop %1,%0"
1437 [(set_attr "type" "mvi")])
1438 \f
1439 ;; Next come the shifts and the various extract and insert operations.
1441 (define_insn "ashldi3"
1442 [(set (match_operand:DI 0 "register_operand" "=r,r")
1443 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ")
1444 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))]
1445 ""
1446 {
1447 switch (which_alternative)
1448 {
1449 case 0:
1450 if (operands[2] == const1_rtx)
1451 return "addq %r1,%r1,%0";
1452 else
1453 return "s%P2addq %r1,0,%0";
1454 case 1:
1455 return "sll %r1,%2,%0";
1456 default:
1457 gcc_unreachable ();
1458 }
1459 }
1460 [(set_attr "type" "iadd,shift")])
1462 (define_insn "*ashldi_se"
1463 [(set (match_operand:DI 0 "register_operand" "=r")
1464 (sign_extend:DI
1465 (subreg:SI (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1466 (match_operand:DI 2 "const_int_operand" "P"))
1467 0)))]
1468 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3"
1469 {
1470 if (operands[2] == const1_rtx)
1471 return "addl %r1,%r1,%0";
1472 else
1473 return "s%P2addl %r1,0,%0";
1474 }
1475 [(set_attr "type" "iadd")])
1477 (define_insn "lshrdi3"
1478 [(set (match_operand:DI 0 "register_operand" "=r")
1479 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1480 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1481 ""
1482 "srl %r1,%2,%0"
1483 [(set_attr "type" "shift")])
1485 (define_insn "ashrdi3"
1486 [(set (match_operand:DI 0 "register_operand" "=r")
1487 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1488 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))]
1489 ""
1490 "sra %r1,%2,%0"
1491 [(set_attr "type" "shift")])
1493 (define_expand "extendqihi2"
1494 [(set (match_dup 2)
1495 (ashift:DI (match_operand:QI 1 "some_operand" "")
1496 (const_int 56)))
1497 (set (match_operand:HI 0 "register_operand" "")
1498 (ashiftrt:DI (match_dup 2)
1499 (const_int 56)))]
1500 ""
1501 {
1502 if (TARGET_BWX)
1503 {
1504 emit_insn (gen_extendqihi2x (operands[0],
1505 force_reg (QImode, operands[1])));
1506 DONE;
1507 }
1509 /* If we have an unaligned MEM, extend to DImode (which we do
1510 specially) and then copy to the result. */
1511 if (unaligned_memory_operand (operands[1], HImode))
1512 {
1513 rtx temp = gen_reg_rtx (DImode);
1515 emit_insn (gen_extendqidi2 (temp, operands[1]));
1516 emit_move_insn (operands[0], gen_lowpart (HImode, temp));
1517 DONE;
1518 }
1520 operands[0] = gen_lowpart (DImode, operands[0]);
1521 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1522 operands[2] = gen_reg_rtx (DImode);
1523 })
1525 (define_insn "extendqidi2x"
1526 [(set (match_operand:DI 0 "register_operand" "=r")
1527 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
1528 "TARGET_BWX"
1529 "sextb %1,%0"
1530 [(set_attr "type" "shift")])
1532 (define_insn "extendhidi2x"
1533 [(set (match_operand:DI 0 "register_operand" "=r")
1534 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
1535 "TARGET_BWX"
1536 "sextw %1,%0"
1537 [(set_attr "type" "shift")])
1539 (define_insn "extendqisi2x"
1540 [(set (match_operand:SI 0 "register_operand" "=r")
1541 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1542 "TARGET_BWX"
1543 "sextb %1,%0"
1544 [(set_attr "type" "shift")])
1546 (define_insn "extendhisi2x"
1547 [(set (match_operand:SI 0 "register_operand" "=r")
1548 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1549 "TARGET_BWX"
1550 "sextw %1,%0"
1551 [(set_attr "type" "shift")])
1553 (define_insn "extendqihi2x"
1554 [(set (match_operand:HI 0 "register_operand" "=r")
1555 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1556 "TARGET_BWX"
1557 "sextb %1,%0"
1558 [(set_attr "type" "shift")])
1560 (define_expand "extendqisi2"
1561 [(set (match_dup 2)
1562 (ashift:DI (match_operand:QI 1 "some_operand" "")
1563 (const_int 56)))
1564 (set (match_operand:SI 0 "register_operand" "")
1565 (ashiftrt:DI (match_dup 2)
1566 (const_int 56)))]
1567 ""
1568 {
1569 if (TARGET_BWX)
1570 {
1571 emit_insn (gen_extendqisi2x (operands[0],
1572 force_reg (QImode, operands[1])));
1573 DONE;
1574 }
1576 /* If we have an unaligned MEM, extend to a DImode form of
1577 the result (which we do specially). */
1578 if (unaligned_memory_operand (operands[1], QImode))
1579 {
1580 rtx temp = gen_reg_rtx (DImode);
1582 emit_insn (gen_extendqidi2 (temp, operands[1]));
1583 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1584 DONE;
1585 }
1587 operands[0] = gen_lowpart (DImode, operands[0]);
1588 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1589 operands[2] = gen_reg_rtx (DImode);
1590 })
1592 (define_expand "extendqidi2"
1593 [(set (match_dup 2)
1594 (ashift:DI (match_operand:QI 1 "some_operand" "")
1595 (const_int 56)))
1596 (set (match_operand:DI 0 "register_operand" "")
1597 (ashiftrt:DI (match_dup 2)
1598 (const_int 56)))]
1599 ""
1600 {
1601 if (TARGET_BWX)
1602 {
1603 emit_insn (gen_extendqidi2x (operands[0],
1604 force_reg (QImode, operands[1])));
1605 DONE;
1606 }
1608 if (unaligned_memory_operand (operands[1], QImode))
1609 {
1610 rtx seq
1611 = gen_unaligned_extendqidi (operands[0],
1612 get_unaligned_address (operands[1], 1));
1614 alpha_set_memflags (seq, operands[1]);
1615 emit_insn (seq);
1616 DONE;
1617 }
1619 operands[1] = gen_lowpart (DImode, force_reg (QImode, operands[1]));
1620 operands[2] = gen_reg_rtx (DImode);
1621 })
1623 (define_expand "extendhisi2"
1624 [(set (match_dup 2)
1625 (ashift:DI (match_operand:HI 1 "some_operand" "")
1626 (const_int 48)))
1627 (set (match_operand:SI 0 "register_operand" "")
1628 (ashiftrt:DI (match_dup 2)
1629 (const_int 48)))]
1630 ""
1631 {
1632 if (TARGET_BWX)
1633 {
1634 emit_insn (gen_extendhisi2x (operands[0],
1635 force_reg (HImode, operands[1])));
1636 DONE;
1637 }
1639 /* If we have an unaligned MEM, extend to a DImode form of
1640 the result (which we do specially). */
1641 if (unaligned_memory_operand (operands[1], HImode))
1642 {
1643 rtx temp = gen_reg_rtx (DImode);
1645 emit_insn (gen_extendhidi2 (temp, operands[1]));
1646 emit_move_insn (operands[0], gen_lowpart (SImode, temp));
1647 DONE;
1648 }
1650 operands[0] = gen_lowpart (DImode, operands[0]);
1651 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1652 operands[2] = gen_reg_rtx (DImode);
1653 })
1655 (define_expand "extendhidi2"
1656 [(set (match_dup 2)
1657 (ashift:DI (match_operand:HI 1 "some_operand" "")
1658 (const_int 48)))
1659 (set (match_operand:DI 0 "register_operand" "")
1660 (ashiftrt:DI (match_dup 2)
1661 (const_int 48)))]
1662 ""
1663 {
1664 if (TARGET_BWX)
1665 {
1666 emit_insn (gen_extendhidi2x (operands[0],
1667 force_reg (HImode, operands[1])));
1668 DONE;
1669 }
1671 if (unaligned_memory_operand (operands[1], HImode))
1672 {
1673 rtx seq
1674 = gen_unaligned_extendhidi (operands[0],
1675 get_unaligned_address (operands[1], 2));
1677 alpha_set_memflags (seq, operands[1]);
1678 emit_insn (seq);
1679 DONE;
1680 }
1682 operands[1] = gen_lowpart (DImode, force_reg (HImode, operands[1]));
1683 operands[2] = gen_reg_rtx (DImode);
1684 })
1686 ;; Here's how we sign extend an unaligned byte and halfword. Doing this
1687 ;; as a pattern saves one instruction. The code is similar to that for
1688 ;; the unaligned loads (see below).
1689 ;;
1690 ;; Operand 1 is the address + 1 (+2 for HI), operand 0 is the result.
1691 (define_expand "unaligned_extendqidi"
1692 [(use (match_operand:QI 0 "register_operand" ""))
1693 (use (match_operand:DI 1 "address_operand" ""))]
1694 ""
1695 {
1696 if (WORDS_BIG_ENDIAN)
1697 emit_insn (gen_unaligned_extendqidi_be (operands[0], operands[1]));
1698 else
1699 emit_insn (gen_unaligned_extendqidi_le (operands[0], operands[1]));
1700 DONE;
1701 })
1703 (define_expand "unaligned_extendqidi_le"
1704 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1705 (set (match_dup 3)
1706 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -1))
1707 (const_int -8))))
1708 (set (match_dup 4)
1709 (ashift:DI (match_dup 3)
1710 (minus:DI (const_int 64)
1711 (ashift:DI
1712 (and:DI (match_dup 2) (const_int 7))
1713 (const_int 3)))))
1714 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1715 (ashiftrt:DI (match_dup 4) (const_int 56)))]
1716 "! WORDS_BIG_ENDIAN"
1717 {
1718 operands[2] = gen_reg_rtx (DImode);
1719 operands[3] = gen_reg_rtx (DImode);
1720 operands[4] = gen_reg_rtx (DImode);
1721 })
1723 (define_expand "unaligned_extendqidi_be"
1724 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1725 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -1)))
1726 (set (match_dup 4)
1727 (mem:DI (and:DI (match_dup 3)
1728 (const_int -8))))
1729 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -2)))
1730 (set (match_dup 6)
1731 (ashift:DI (match_dup 4)
1732 (ashift:DI
1733 (and:DI
1734 (plus:DI (match_dup 5) (const_int 1))
1735 (const_int 7))
1736 (const_int 3))))
1737 (set (subreg:DI (match_operand:QI 0 "register_operand" "") 0)
1738 (ashiftrt:DI (match_dup 6) (const_int 56)))]
1739 "WORDS_BIG_ENDIAN"
1740 {
1741 operands[2] = gen_reg_rtx (DImode);
1742 operands[3] = gen_reg_rtx (DImode);
1743 operands[4] = gen_reg_rtx (DImode);
1744 operands[5] = gen_reg_rtx (DImode);
1745 operands[6] = gen_reg_rtx (DImode);
1746 })
1748 (define_expand "unaligned_extendhidi"
1749 [(use (match_operand:QI 0 "register_operand" ""))
1750 (use (match_operand:DI 1 "address_operand" ""))]
1751 ""
1752 {
1753 operands[0] = gen_lowpart (DImode, operands[0]);
1754 emit_insn ((WORDS_BIG_ENDIAN
1755 ? gen_unaligned_extendhidi_be
1756 : gen_unaligned_extendhidi_le) (operands[0], operands[1]));
1757 DONE;
1758 })
1760 (define_expand "unaligned_extendhidi_le"
1761 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1762 (set (match_dup 3)
1763 (mem:DI (and:DI (plus:DI (match_dup 2) (const_int -2))
1764 (const_int -8))))
1765 (set (match_dup 4)
1766 (ashift:DI (match_dup 3)
1767 (minus:DI (const_int 64)
1768 (ashift:DI
1769 (and:DI (match_dup 2) (const_int 7))
1770 (const_int 3)))))
1771 (set (match_operand:DI 0 "register_operand" "")
1772 (ashiftrt:DI (match_dup 4) (const_int 48)))]
1773 "! WORDS_BIG_ENDIAN"
1774 {
1775 operands[2] = gen_reg_rtx (DImode);
1776 operands[3] = gen_reg_rtx (DImode);
1777 operands[4] = gen_reg_rtx (DImode);
1778 })
1780 (define_expand "unaligned_extendhidi_be"
1781 [(set (match_dup 2) (match_operand:DI 1 "address_operand" ""))
1782 (set (match_dup 3) (plus:DI (match_dup 2) (const_int -2)))
1783 (set (match_dup 4)
1784 (mem:DI (and:DI (match_dup 3)
1785 (const_int -8))))
1786 (set (match_dup 5) (plus:DI (match_dup 2) (const_int -3)))
1787 (set (match_dup 6)
1788 (ashift:DI (match_dup 4)
1789 (ashift:DI
1790 (and:DI
1791 (plus:DI (match_dup 5) (const_int 1))
1792 (const_int 7))
1793 (const_int 3))))
1794 (set (match_operand:DI 0 "register_operand" "")
1795 (ashiftrt:DI (match_dup 6) (const_int 48)))]
1796 "WORDS_BIG_ENDIAN"
1797 {
1798 operands[2] = gen_reg_rtx (DImode);
1799 operands[3] = gen_reg_rtx (DImode);
1800 operands[4] = gen_reg_rtx (DImode);
1801 operands[5] = gen_reg_rtx (DImode);
1802 operands[6] = gen_reg_rtx (DImode);
1803 })
1805 (define_insn "*extxl_const"
1806 [(set (match_operand:DI 0 "register_operand" "=r")
1807 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1808 (match_operand:DI 2 "mode_width_operand" "n")
1809 (match_operand:DI 3 "mul8_operand" "I")))]
1810 ""
1811 "ext%M2l %r1,%s3,%0"
1812 [(set_attr "type" "shift")])
1814 (define_insn "extxl_le"
1815 [(set (match_operand:DI 0 "register_operand" "=r")
1816 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1817 (match_operand:DI 2 "mode_width_operand" "n")
1818 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1819 (const_int 3))))]
1820 "! WORDS_BIG_ENDIAN"
1821 "ext%M2l %r1,%3,%0"
1822 [(set_attr "type" "shift")])
1824 (define_insn "extxl_be"
1825 [(set (match_operand:DI 0 "register_operand" "=r")
1826 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1827 (match_operand:DI 2 "mode_width_operand" "n")
1828 (minus:DI
1829 (const_int 56)
1830 (ashift:DI
1831 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
1832 (const_int 3)))))]
1833 "WORDS_BIG_ENDIAN"
1834 "ext%M2l %r1,%3,%0"
1835 [(set_attr "type" "shift")])
1837 ;; Combine has some strange notion of preserving existing undefined behavior
1838 ;; in shifts larger than a word size. So capture these patterns that it
1839 ;; should have turned into zero_extracts.
1841 (define_insn "*extxl_1_le"
1842 [(set (match_operand:DI 0 "register_operand" "=r")
1843 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1844 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1845 (const_int 3)))
1846 (match_operand:DI 3 "mode_mask_operand" "n")))]
1847 "! WORDS_BIG_ENDIAN"
1848 "ext%U3l %1,%2,%0"
1849 [(set_attr "type" "shift")])
1851 (define_insn "*extxl_1_be"
1852 [(set (match_operand:DI 0 "register_operand" "=r")
1853 (and:DI (lshiftrt:DI
1854 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1855 (minus:DI (const_int 56)
1856 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1857 (const_int 3))))
1858 (match_operand:DI 3 "mode_mask_operand" "n")))]
1859 "WORDS_BIG_ENDIAN"
1860 "ext%U3l %1,%2,%0"
1861 [(set_attr "type" "shift")])
1863 (define_insn "*extql_2_le"
1864 [(set (match_operand:DI 0 "register_operand" "=r")
1865 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1866 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1867 (const_int 3))))]
1868 "! WORDS_BIG_ENDIAN"
1869 "extql %1,%2,%0"
1870 [(set_attr "type" "shift")])
1872 (define_insn "*extql_2_be"
1873 [(set (match_operand:DI 0 "register_operand" "=r")
1874 (lshiftrt:DI
1875 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1876 (minus:DI (const_int 56)
1877 (ashift:DI
1878 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1879 (const_int 3)))))]
1880 "WORDS_BIG_ENDIAN"
1881 "extql %1,%2,%0"
1882 [(set_attr "type" "shift")])
1884 (define_insn "extqh_le"
1885 [(set (match_operand:DI 0 "register_operand" "=r")
1886 (ashift:DI
1887 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1888 (minus:DI (const_int 64)
1889 (ashift:DI
1890 (and:DI
1891 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1892 (const_int 7))
1893 (const_int 3)))))]
1894 "! WORDS_BIG_ENDIAN"
1895 "extqh %r1,%2,%0"
1896 [(set_attr "type" "shift")])
1898 (define_insn "extqh_be"
1899 [(set (match_operand:DI 0 "register_operand" "=r")
1900 (ashift:DI
1901 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1902 (ashift:DI
1903 (and:DI
1904 (plus:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1905 (const_int 1))
1906 (const_int 7))
1907 (const_int 3))))]
1908 "WORDS_BIG_ENDIAN"
1909 "extqh %r1,%2,%0"
1910 [(set_attr "type" "shift")])
1912 (define_insn "extlh_le"
1913 [(set (match_operand:DI 0 "register_operand" "=r")
1914 (ashift:DI
1915 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1916 (const_int 2147483647))
1917 (minus:DI (const_int 64)
1918 (ashift:DI
1919 (and:DI
1920 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1921 (const_int 7))
1922 (const_int 3)))))]
1923 "! WORDS_BIG_ENDIAN"
1924 "extlh %r1,%2,%0"
1925 [(set_attr "type" "shift")])
1927 (define_insn "extlh_be"
1928 [(set (match_operand:DI 0 "register_operand" "=r")
1929 (and:DI
1930 (ashift:DI
1931 (match_operand:DI 1 "reg_or_0_operand" "rJ")
1932 (ashift:DI
1933 (and:DI
1934 (plus:DI
1935 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1936 (const_int 1))
1937 (const_int 7))
1938 (const_int 3)))
1939 (const_int 2147483647)))]
1940 "WORDS_BIG_ENDIAN"
1941 "extlh %r1,%2,%0"
1942 [(set_attr "type" "shift")])
1944 (define_insn "extwh_le"
1945 [(set (match_operand:DI 0 "register_operand" "=r")
1946 (ashift:DI
1947 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1948 (const_int 65535))
1949 (minus:DI (const_int 64)
1950 (ashift:DI
1951 (and:DI
1952 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1953 (const_int 7))
1954 (const_int 3)))))]
1955 "! WORDS_BIG_ENDIAN"
1956 "extwh %r1,%2,%0"
1957 [(set_attr "type" "shift")])
1959 (define_insn "extwh_be"
1960 [(set (match_operand:DI 0 "register_operand" "=r")
1961 (and:DI
1962 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
1963 (ashift:DI
1964 (and:DI
1965 (plus:DI
1966 (match_operand:DI 2 "reg_or_8bit_operand" "rI")
1967 (const_int 1))
1968 (const_int 7))
1969 (const_int 3)))
1970 (const_int 65535)))]
1971 "WORDS_BIG_ENDIAN"
1972 "extwh %r1,%2,%0"
1973 [(set_attr "type" "shift")])
1975 ;; This converts an extXl into an extXh with an appropriate adjustment
1976 ;; to the address calculation.
1978 ;;(define_split
1979 ;; [(set (match_operand:DI 0 "register_operand" "")
1980 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand" "")
1981 ;; (match_operand:DI 2 "mode_width_operand" "")
1982 ;; (ashift:DI (match_operand:DI 3 "" "")
1983 ;; (const_int 3)))
1984 ;; (match_operand:DI 4 "const_int_operand" "")))
1985 ;; (clobber (match_operand:DI 5 "register_operand" ""))]
1986 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])"
1987 ;; [(set (match_dup 5) (match_dup 6))
1988 ;; (set (match_dup 0)
1989 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2)
1990 ;; (ashift:DI (plus:DI (match_dup 5)
1991 ;; (match_dup 7))
1992 ;; (const_int 3)))
1993 ;; (match_dup 4)))]
1994 ;; "
1995 ;;{
1996 ;; operands[6] = plus_constant (operands[3],
1997 ;; INTVAL (operands[2]) / BITS_PER_UNIT);
1998 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT);
1999 ;;}")
2001 (define_insn "*insbl_const"
2002 [(set (match_operand:DI 0 "register_operand" "=r")
2003 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2004 (match_operand:DI 2 "mul8_operand" "I")))]
2005 ""
2006 "insbl %1,%s2,%0"
2007 [(set_attr "type" "shift")])
2009 (define_insn "*inswl_const"
2010 [(set (match_operand:DI 0 "register_operand" "=r")
2011 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2012 (match_operand:DI 2 "mul8_operand" "I")))]
2013 ""
2014 "inswl %1,%s2,%0"
2015 [(set_attr "type" "shift")])
2017 (define_insn "*insll_const"
2018 [(set (match_operand:DI 0 "register_operand" "=r")
2019 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2020 (match_operand:DI 2 "mul8_operand" "I")))]
2021 ""
2022 "insll %1,%s2,%0"
2023 [(set_attr "type" "shift")])
2025 (define_insn "insbl_le"
2026 [(set (match_operand:DI 0 "register_operand" "=r")
2027 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2028 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2029 (const_int 3))))]
2030 "! WORDS_BIG_ENDIAN"
2031 "insbl %1,%2,%0"
2032 [(set_attr "type" "shift")])
2034 (define_insn "insbl_be"
2035 [(set (match_operand:DI 0 "register_operand" "=r")
2036 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" "r"))
2037 (minus:DI (const_int 56)
2038 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2039 (const_int 3)))))]
2040 "WORDS_BIG_ENDIAN"
2041 "insbl %1,%2,%0"
2042 [(set_attr "type" "shift")])
2044 (define_insn "inswl_le"
2045 [(set (match_operand:DI 0 "register_operand" "=r")
2046 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2047 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2048 (const_int 3))))]
2049 "! WORDS_BIG_ENDIAN"
2050 "inswl %1,%2,%0"
2051 [(set_attr "type" "shift")])
2053 (define_insn "inswl_be"
2054 [(set (match_operand:DI 0 "register_operand" "=r")
2055 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" "r"))
2056 (minus:DI (const_int 56)
2057 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2058 (const_int 3)))))]
2059 "WORDS_BIG_ENDIAN"
2060 "inswl %1,%2,%0"
2061 [(set_attr "type" "shift")])
2063 (define_insn "insll_le"
2064 [(set (match_operand:DI 0 "register_operand" "=r")
2065 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2066 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2067 (const_int 3))))]
2068 "! WORDS_BIG_ENDIAN"
2069 "insll %1,%2,%0"
2070 [(set_attr "type" "shift")])
2072 (define_insn "insll_be"
2073 [(set (match_operand:DI 0 "register_operand" "=r")
2074 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
2075 (minus:DI (const_int 56)
2076 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2077 (const_int 3)))))]
2078 "WORDS_BIG_ENDIAN"
2079 "insll %1,%2,%0"
2080 [(set_attr "type" "shift")])
2082 (define_insn "insql_le"
2083 [(set (match_operand:DI 0 "register_operand" "=r")
2084 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2085 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2086 (const_int 3))))]
2087 "! WORDS_BIG_ENDIAN"
2088 "insql %1,%2,%0"
2089 [(set_attr "type" "shift")])
2091 (define_insn "insql_be"
2092 [(set (match_operand:DI 0 "register_operand" "=r")
2093 (ashift:DI (match_operand:DI 1 "register_operand" "r")
2094 (minus:DI (const_int 56)
2095 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI")
2096 (const_int 3)))))]
2097 "WORDS_BIG_ENDIAN"
2098 "insql %1,%2,%0"
2099 [(set_attr "type" "shift")])
2101 ;; Combine has this sometimes habit of moving the and outside of the
2102 ;; shift, making life more interesting.
2104 (define_insn "*insxl"
2105 [(set (match_operand:DI 0 "register_operand" "=r")
2106 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r")
2107 (match_operand:DI 2 "mul8_operand" "I"))
2108 (match_operand:DI 3 "immediate_operand" "i")))]
2109 "HOST_BITS_PER_WIDE_INT == 64
2110 && GET_CODE (operands[3]) == CONST_INT
2111 && (((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2112 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2113 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2114 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2115 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2116 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])))"
2117 {
2118 #if HOST_BITS_PER_WIDE_INT == 64
2119 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2])
2120 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2121 return "insbl %1,%s2,%0";
2122 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2])
2123 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2124 return "inswl %1,%s2,%0";
2125 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2])
2126 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))
2127 return "insll %1,%s2,%0";
2128 #endif
2129 gcc_unreachable ();
2130 }
2131 [(set_attr "type" "shift")])
2133 ;; We do not include the insXh insns because they are complex to express
2134 ;; and it does not appear that we would ever want to generate them.
2135 ;;
2136 ;; Since we need them for block moves, though, cop out and use unspec.
2138 (define_insn "insxh"
2139 [(set (match_operand:DI 0 "register_operand" "=r")
2140 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2141 (match_operand:DI 2 "mode_width_operand" "n")
2142 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2143 UNSPEC_INSXH))]
2144 ""
2145 "ins%M2h %1,%3,%0"
2146 [(set_attr "type" "shift")])
2148 (define_insn "mskxl_le"
2149 [(set (match_operand:DI 0 "register_operand" "=r")
2150 (and:DI (not:DI (ashift:DI
2151 (match_operand:DI 2 "mode_mask_operand" "n")
2152 (ashift:DI
2153 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2154 (const_int 3))))
2155 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2156 "! WORDS_BIG_ENDIAN"
2157 "msk%U2l %r1,%3,%0"
2158 [(set_attr "type" "shift")])
2160 (define_insn "mskxl_be"
2161 [(set (match_operand:DI 0 "register_operand" "=r")
2162 (and:DI (not:DI (ashift:DI
2163 (match_operand:DI 2 "mode_mask_operand" "n")
2164 (minus:DI (const_int 56)
2165 (ashift:DI
2166 (match_operand:DI 3 "reg_or_8bit_operand" "rI")
2167 (const_int 3)))))
2168 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
2169 "WORDS_BIG_ENDIAN"
2170 "msk%U2l %r1,%3,%0"
2171 [(set_attr "type" "shift")])
2173 ;; We do not include the mskXh insns because it does not appear we would
2174 ;; ever generate one.
2175 ;;
2176 ;; Again, we do for block moves and we use unspec again.
2178 (define_insn "mskxh"
2179 [(set (match_operand:DI 0 "register_operand" "=r")
2180 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
2181 (match_operand:DI 2 "mode_width_operand" "n")
2182 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]
2183 UNSPEC_MSKXH))]
2184 ""
2185 "msk%M2h %1,%3,%0"
2186 [(set_attr "type" "shift")])
2188 ;; Prefer AND + NE over LSHIFTRT + AND.
2190 (define_insn_and_split "*ze_and_ne"
2191 [(set (match_operand:DI 0 "register_operand" "=r")
2192 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
2193 (const_int 1)
2194 (match_operand 2 "const_int_operand" "I")))]
2195 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2196 "#"
2197 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8"
2198 [(set (match_dup 0)
2199 (and:DI (match_dup 1) (match_dup 3)))
2200 (set (match_dup 0)
2201 (ne:DI (match_dup 0) (const_int 0)))]
2202 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));")
2203 \f
2204 ;; Floating-point operations. All the double-precision insns can extend
2205 ;; from single, so indicate that. The exception are the ones that simply
2206 ;; play with the sign bits; it's not clear what to do there.
2208 (define_insn "abssf2"
2209 [(set (match_operand:SF 0 "register_operand" "=f")
2210 (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2211 "TARGET_FP"
2212 "cpys $f31,%R1,%0"
2213 [(set_attr "type" "fcpys")])
2215 (define_insn "*nabssf2"
2216 [(set (match_operand:SF 0 "register_operand" "=f")
2217 (neg:SF (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG"))))]
2218 "TARGET_FP"
2219 "cpysn $f31,%R1,%0"
2220 [(set_attr "type" "fadd")])
2222 (define_insn "absdf2"
2223 [(set (match_operand:DF 0 "register_operand" "=f")
2224 (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2225 "TARGET_FP"
2226 "cpys $f31,%R1,%0"
2227 [(set_attr "type" "fcpys")])
2229 (define_insn "*nabsdf2"
2230 [(set (match_operand:DF 0 "register_operand" "=f")
2231 (neg:DF (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG"))))]
2232 "TARGET_FP"
2233 "cpysn $f31,%R1,%0"
2234 [(set_attr "type" "fadd")])
2236 (define_expand "abstf2"
2237 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2238 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2239 (use (match_dup 2))])]
2240 "TARGET_HAS_XFLOATING_LIBS"
2241 {
2242 #if HOST_BITS_PER_WIDE_INT >= 64
2243 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2244 #else
2245 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2246 #endif
2247 })
2249 (define_insn_and_split "*abstf_internal"
2250 [(set (match_operand:TF 0 "register_operand" "=r")
2251 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2252 (use (match_operand:DI 2 "register_operand" "r"))]
2253 "TARGET_HAS_XFLOATING_LIBS"
2254 "#"
2255 "&& reload_completed"
2256 [(const_int 0)]
2257 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;")
2259 (define_insn "negsf2"
2260 [(set (match_operand:SF 0 "register_operand" "=f")
2261 (neg:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
2262 "TARGET_FP"
2263 "cpysn %R1,%R1,%0"
2264 [(set_attr "type" "fadd")])
2266 (define_insn "negdf2"
2267 [(set (match_operand:DF 0 "register_operand" "=f")
2268 (neg:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2269 "TARGET_FP"
2270 "cpysn %R1,%R1,%0"
2271 [(set_attr "type" "fadd")])
2273 (define_expand "negtf2"
2274 [(parallel [(set (match_operand:TF 0 "register_operand" "")
2275 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "")))
2276 (use (match_dup 2))])]
2277 "TARGET_HAS_XFLOATING_LIBS"
2278 {
2279 #if HOST_BITS_PER_WIDE_INT >= 64
2280 operands[2] = force_reg (DImode, GEN_INT ((HOST_WIDE_INT) 1 << 63));
2281 #else
2282 operands[2] = force_reg (DImode, immed_double_const (0, 0x80000000, DImode));
2283 #endif
2284 })
2286 (define_insn_and_split "*negtf_internal"
2287 [(set (match_operand:TF 0 "register_operand" "=r")
2288 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG")))
2289 (use (match_operand:DI 2 "register_operand" "r"))]
2290 "TARGET_HAS_XFLOATING_LIBS"
2291 "#"
2292 "&& reload_completed"
2293 [(const_int 0)]
2294 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;")
2296 (define_insn "copysignsf3"
2297 [(set (match_operand:SF 0 "register_operand" "=f")
2298 (unspec:SF [(match_operand:SF 1 "reg_or_0_operand" "fG")
2299 (match_operand:SF 2 "reg_or_0_operand" "fG")]
2300 UNSPEC_COPYSIGN))]
2301 "TARGET_FP"
2302 "cpys %R2,%R1,%0"
2303 [(set_attr "type" "fadd")])
2305 (define_insn "*ncopysignsf3"
2306 [(set (match_operand:SF 0 "register_operand" "=f")
2307 (neg:SF (unspec:SF [(match_operand:SF 1 "reg_or_0_operand" "fG")
2308 (match_operand:SF 2 "reg_or_0_operand" "fG")]
2309 UNSPEC_COPYSIGN)))]
2310 "TARGET_FP"
2311 "cpysn %R2,%R1,%0"
2312 [(set_attr "type" "fadd")])
2314 (define_insn "copysigndf3"
2315 [(set (match_operand:DF 0 "register_operand" "=f")
2316 (unspec:DF [(match_operand:DF 1 "reg_or_0_operand" "fG")
2317 (match_operand:DF 2 "reg_or_0_operand" "fG")]
2318 UNSPEC_COPYSIGN))]
2319 "TARGET_FP"
2320 "cpys %R2,%R1,%0"
2321 [(set_attr "type" "fadd")])
2323 (define_insn "*ncopysigndf3"
2324 [(set (match_operand:DF 0 "register_operand" "=f")
2325 (neg:DF (unspec:DF [(match_operand:DF 1 "reg_or_0_operand" "fG")
2326 (match_operand:DF 2 "reg_or_0_operand" "fG")]
2327 UNSPEC_COPYSIGN)))]
2328 "TARGET_FP"
2329 "cpysn %R2,%R1,%0"
2330 [(set_attr "type" "fadd")])
2332 (define_insn "*addsf_ieee"
2333 [(set (match_operand:SF 0 "register_operand" "=&f")
2334 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2335 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2336 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2337 "add%,%/ %R1,%R2,%0"
2338 [(set_attr "type" "fadd")
2339 (set_attr "trap" "yes")
2340 (set_attr "round_suffix" "normal")
2341 (set_attr "trap_suffix" "u_su_sui")])
2343 (define_insn "addsf3"
2344 [(set (match_operand:SF 0 "register_operand" "=f")
2345 (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2346 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2347 "TARGET_FP"
2348 "add%,%/ %R1,%R2,%0"
2349 [(set_attr "type" "fadd")
2350 (set_attr "trap" "yes")
2351 (set_attr "round_suffix" "normal")
2352 (set_attr "trap_suffix" "u_su_sui")])
2354 (define_insn "*adddf_ieee"
2355 [(set (match_operand:DF 0 "register_operand" "=&f")
2356 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2357 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2358 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2359 "add%-%/ %R1,%R2,%0"
2360 [(set_attr "type" "fadd")
2361 (set_attr "trap" "yes")
2362 (set_attr "round_suffix" "normal")
2363 (set_attr "trap_suffix" "u_su_sui")])
2365 (define_insn "adddf3"
2366 [(set (match_operand:DF 0 "register_operand" "=f")
2367 (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2368 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2369 "TARGET_FP"
2370 "add%-%/ %R1,%R2,%0"
2371 [(set_attr "type" "fadd")
2372 (set_attr "trap" "yes")
2373 (set_attr "round_suffix" "normal")
2374 (set_attr "trap_suffix" "u_su_sui")])
2376 (define_insn "*adddf_ext1"
2377 [(set (match_operand:DF 0 "register_operand" "=f")
2378 (plus:DF (float_extend:DF
2379 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2380 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2381 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2382 "add%-%/ %R1,%R2,%0"
2383 [(set_attr "type" "fadd")
2384 (set_attr "trap" "yes")
2385 (set_attr "round_suffix" "normal")
2386 (set_attr "trap_suffix" "u_su_sui")])
2388 (define_insn "*adddf_ext2"
2389 [(set (match_operand:DF 0 "register_operand" "=f")
2390 (plus:DF (float_extend:DF
2391 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2392 (float_extend:DF
2393 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2394 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2395 "add%-%/ %R1,%R2,%0"
2396 [(set_attr "type" "fadd")
2397 (set_attr "trap" "yes")
2398 (set_attr "round_suffix" "normal")
2399 (set_attr "trap_suffix" "u_su_sui")])
2401 (define_expand "addtf3"
2402 [(use (match_operand 0 "register_operand" ""))
2403 (use (match_operand 1 "general_operand" ""))
2404 (use (match_operand 2 "general_operand" ""))]
2405 "TARGET_HAS_XFLOATING_LIBS"
2406 "alpha_emit_xfloating_arith (PLUS, operands); DONE;")
2408 ;; Define conversion operators between DFmode and SImode, using the cvtql
2409 ;; instruction. To allow combine et al to do useful things, we keep the
2410 ;; operation as a unit until after reload, at which point we split the
2411 ;; instructions.
2412 ;;
2413 ;; Note that we (attempt to) only consider this optimization when the
2414 ;; ultimate destination is memory. If we will be doing further integer
2415 ;; processing, it is cheaper to do the truncation in the int regs.
2417 (define_insn "*cvtql"
2418 [(set (match_operand:SF 0 "register_operand" "=f")
2419 (unspec:SF [(match_operand:DI 1 "reg_or_0_operand" "fG")]
2420 UNSPEC_CVTQL))]
2421 "TARGET_FP"
2422 "cvtql%/ %R1,%0"
2423 [(set_attr "type" "fadd")
2424 (set_attr "trap" "yes")
2425 (set_attr "trap_suffix" "v_sv")])
2427 (define_insn_and_split "*fix_truncdfsi_ieee"
2428 [(set (match_operand:SI 0 "memory_operand" "=m")
2429 (subreg:SI
2430 (match_operator:DI 4 "fix_operator"
2431 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
2432 (clobber (match_scratch:DI 2 "=&f"))
2433 (clobber (match_scratch:SF 3 "=&f"))]
2434 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2435 "#"
2436 "&& reload_completed"
2437 [(set (match_dup 2) (match_op_dup 4 [(match_dup 1)]))
2438 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2439 (set (match_dup 5) (match_dup 3))]
2440 {
2441 operands[5] = adjust_address (operands[0], SFmode, 0);
2442 }
2443 [(set_attr "type" "fadd")
2444 (set_attr "trap" "yes")])
2446 (define_insn_and_split "*fix_truncdfsi_internal"
2447 [(set (match_operand:SI 0 "memory_operand" "=m")
2448 (subreg:SI
2449 (match_operator:DI 3 "fix_operator"
2450 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0))
2451 (clobber (match_scratch:DI 2 "=f"))]
2452 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2453 "#"
2454 "&& reload_completed"
2455 [(set (match_dup 2) (match_op_dup 3 [(match_dup 1)]))
2456 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2457 (set (match_dup 5) (match_dup 4))]
2458 {
2459 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
2460 operands[5] = adjust_address (operands[0], SFmode, 0);
2461 }
2462 [(set_attr "type" "fadd")
2463 (set_attr "trap" "yes")])
2465 (define_insn "*fix_truncdfdi_ieee"
2466 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2467 (match_operator:DI 2 "fix_operator"
2468 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
2469 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2470 "cvt%-q%/ %R1,%0"
2471 [(set_attr "type" "fadd")
2472 (set_attr "trap" "yes")
2473 (set_attr "round_suffix" "c")
2474 (set_attr "trap_suffix" "v_sv_svi")])
2476 (define_insn "*fix_truncdfdi2"
2477 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2478 (match_operator:DI 2 "fix_operator"
2479 [(match_operand:DF 1 "reg_or_0_operand" "fG")]))]
2480 "TARGET_FP"
2481 "cvt%-q%/ %R1,%0"
2482 [(set_attr "type" "fadd")
2483 (set_attr "trap" "yes")
2484 (set_attr "round_suffix" "c")
2485 (set_attr "trap_suffix" "v_sv_svi")])
2487 (define_expand "fix_truncdfdi2"
2488 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2489 (fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
2490 "TARGET_FP"
2491 "")
2493 (define_expand "fixuns_truncdfdi2"
2494 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2495 (unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand" "")))]
2496 "TARGET_FP"
2497 "")
2499 ;; Likewise between SFmode and SImode.
2501 (define_insn_and_split "*fix_truncsfsi_ieee"
2502 [(set (match_operand:SI 0 "memory_operand" "=m")
2503 (subreg:SI
2504 (match_operator:DI 4 "fix_operator"
2505 [(float_extend:DF
2506 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
2507 (clobber (match_scratch:DI 2 "=&f"))
2508 (clobber (match_scratch:SF 3 "=&f"))]
2509 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2510 "#"
2511 "&& reload_completed"
2512 [(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))]))
2513 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2514 (set (match_dup 5) (match_dup 3))]
2515 {
2516 operands[5] = adjust_address (operands[0], SFmode, 0);
2517 }
2518 [(set_attr "type" "fadd")
2519 (set_attr "trap" "yes")])
2521 (define_insn_and_split "*fix_truncsfsi_internal"
2522 [(set (match_operand:SI 0 "memory_operand" "=m")
2523 (subreg:SI
2524 (match_operator:DI 3 "fix_operator"
2525 [(float_extend:DF
2526 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0))
2527 (clobber (match_scratch:DI 2 "=f"))]
2528 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2529 "#"
2530 "&& reload_completed"
2531 [(set (match_dup 2) (match_op_dup 3 [(float_extend:DF (match_dup 1))]))
2532 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL))
2533 (set (match_dup 5) (match_dup 4))]
2534 {
2535 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2]));
2536 operands[5] = adjust_address (operands[0], SFmode, 0);
2537 }
2538 [(set_attr "type" "fadd")
2539 (set_attr "trap" "yes")])
2541 (define_insn "*fix_truncsfdi_ieee"
2542 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f")
2543 (match_operator:DI 2 "fix_operator"
2544 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
2545 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2546 "cvt%-q%/ %R1,%0"
2547 [(set_attr "type" "fadd")
2548 (set_attr "trap" "yes")
2549 (set_attr "round_suffix" "c")
2550 (set_attr "trap_suffix" "v_sv_svi")])
2552 (define_insn "*fix_truncsfdi2"
2553 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f")
2554 (match_operator:DI 2 "fix_operator"
2555 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))]))]
2556 "TARGET_FP"
2557 "cvt%-q%/ %R1,%0"
2558 [(set_attr "type" "fadd")
2559 (set_attr "trap" "yes")
2560 (set_attr "round_suffix" "c")
2561 (set_attr "trap_suffix" "v_sv_svi")])
2563 (define_expand "fix_truncsfdi2"
2564 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2565 (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
2566 "TARGET_FP"
2567 "")
2569 (define_expand "fixuns_truncsfdi2"
2570 [(set (match_operand:DI 0 "reg_no_subreg_operand" "")
2571 (unsigned_fix:DI
2572 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))))]
2573 "TARGET_FP"
2574 "")
2576 (define_expand "fix_trunctfdi2"
2577 [(use (match_operand:DI 0 "register_operand" ""))
2578 (use (match_operand:TF 1 "general_operand" ""))]
2579 "TARGET_HAS_XFLOATING_LIBS"
2580 "alpha_emit_xfloating_cvt (FIX, operands); DONE;")
2582 (define_expand "fixuns_trunctfdi2"
2583 [(use (match_operand:DI 0 "register_operand" ""))
2584 (use (match_operand:TF 1 "general_operand" ""))]
2585 "TARGET_HAS_XFLOATING_LIBS"
2586 "alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;")
2588 (define_insn "*floatdisf_ieee"
2589 [(set (match_operand:SF 0 "register_operand" "=&f")
2590 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2591 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2592 "cvtq%,%/ %1,%0"
2593 [(set_attr "type" "fadd")
2594 (set_attr "trap" "yes")
2595 (set_attr "round_suffix" "normal")
2596 (set_attr "trap_suffix" "sui")])
2598 (define_insn "floatdisf2"
2599 [(set (match_operand:SF 0 "register_operand" "=f")
2600 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2601 "TARGET_FP"
2602 "cvtq%,%/ %1,%0"
2603 [(set_attr "type" "fadd")
2604 (set_attr "trap" "yes")
2605 (set_attr "round_suffix" "normal")
2606 (set_attr "trap_suffix" "sui")])
2608 (define_insn_and_split "*floatsisf2_ieee"
2609 [(set (match_operand:SF 0 "register_operand" "=&f")
2610 (float:SF (match_operand:SI 1 "memory_operand" "m")))
2611 (clobber (match_scratch:DI 2 "=&f"))
2612 (clobber (match_scratch:SF 3 "=&f"))]
2613 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2614 "#"
2615 "&& reload_completed"
2616 [(set (match_dup 3) (match_dup 1))
2617 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2618 (set (match_dup 0) (float:SF (match_dup 2)))]
2619 {
2620 operands[1] = adjust_address (operands[1], SFmode, 0);
2621 })
2623 (define_insn_and_split "*floatsisf2"
2624 [(set (match_operand:SF 0 "register_operand" "=f")
2625 (float:SF (match_operand:SI 1 "memory_operand" "m")))]
2626 "TARGET_FP"
2627 "#"
2628 "&& reload_completed"
2629 [(set (match_dup 0) (match_dup 1))
2630 (set (match_dup 2) (unspec:DI [(match_dup 0)] UNSPEC_CVTLQ))
2631 (set (match_dup 0) (float:SF (match_dup 2)))]
2632 {
2633 operands[1] = adjust_address (operands[1], SFmode, 0);
2634 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
2635 })
2637 (define_insn "*floatdidf_ieee"
2638 [(set (match_operand:DF 0 "register_operand" "=&f")
2639 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2640 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2641 "cvtq%-%/ %1,%0"
2642 [(set_attr "type" "fadd")
2643 (set_attr "trap" "yes")
2644 (set_attr "round_suffix" "normal")
2645 (set_attr "trap_suffix" "sui")])
2647 (define_insn "floatdidf2"
2648 [(set (match_operand:DF 0 "register_operand" "=f")
2649 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f")))]
2650 "TARGET_FP"
2651 "cvtq%-%/ %1,%0"
2652 [(set_attr "type" "fadd")
2653 (set_attr "trap" "yes")
2654 (set_attr "round_suffix" "normal")
2655 (set_attr "trap_suffix" "sui")])
2657 (define_insn_and_split "*floatsidf2_ieee"
2658 [(set (match_operand:DF 0 "register_operand" "=&f")
2659 (float:DF (match_operand:SI 1 "memory_operand" "m")))
2660 (clobber (match_scratch:DI 2 "=&f"))
2661 (clobber (match_scratch:SF 3 "=&f"))]
2662 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2663 "#"
2664 "&& reload_completed"
2665 [(set (match_dup 3) (match_dup 1))
2666 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2667 (set (match_dup 0) (float:DF (match_dup 2)))]
2668 {
2669 operands[1] = adjust_address (operands[1], SFmode, 0);
2670 })
2672 (define_insn_and_split "*floatsidf2"
2673 [(set (match_operand:DF 0 "register_operand" "=f")
2674 (float:DF (match_operand:SI 1 "memory_operand" "m")))]
2675 "TARGET_FP"
2676 "#"
2677 "&& reload_completed"
2678 [(set (match_dup 3) (match_dup 1))
2679 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ))
2680 (set (match_dup 0) (float:DF (match_dup 2)))]
2681 {
2682 operands[1] = adjust_address (operands[1], SFmode, 0);
2683 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0]));
2684 operands[3] = gen_rtx_REG (SFmode, REGNO (operands[0]));
2685 })
2687 (define_expand "floatditf2"
2688 [(use (match_operand:TF 0 "register_operand" ""))
2689 (use (match_operand:DI 1 "general_operand" ""))]
2690 "TARGET_HAS_XFLOATING_LIBS"
2691 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;")
2693 (define_expand "floatunsdisf2"
2694 [(use (match_operand:SF 0 "register_operand" ""))
2695 (use (match_operand:DI 1 "register_operand" ""))]
2696 "TARGET_FP"
2697 "alpha_emit_floatuns (operands); DONE;")
2699 (define_expand "floatunsdidf2"
2700 [(use (match_operand:DF 0 "register_operand" ""))
2701 (use (match_operand:DI 1 "register_operand" ""))]
2702 "TARGET_FP"
2703 "alpha_emit_floatuns (operands); DONE;")
2705 (define_expand "floatunsditf2"
2706 [(use (match_operand:TF 0 "register_operand" ""))
2707 (use (match_operand:DI 1 "general_operand" ""))]
2708 "TARGET_HAS_XFLOATING_LIBS"
2709 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;")
2711 (define_expand "extendsfdf2"
2712 [(set (match_operand:DF 0 "register_operand" "")
2713 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "")))]
2714 "TARGET_FP"
2715 {
2716 if (alpha_fptm >= ALPHA_FPTM_SU)
2717 operands[1] = force_reg (SFmode, operands[1]);
2718 })
2720 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already
2721 ;; asserted that alpha_fptm == ALPHA_FPTM_N.
2723 (define_insn "*extendsfdf2_ieee"
2724 [(set (match_operand:DF 0 "register_operand" "=&f")
2725 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2726 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2727 "cvtsts %1,%0"
2728 [(set_attr "type" "fadd")
2729 (set_attr "trap" "yes")])
2731 (define_insn "*extendsfdf2_internal"
2732 [(set (match_operand:DF 0 "register_operand" "=f,f,m")
2733 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))]
2734 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2735 "@
2736 cpys %1,%1,%0
2737 ld%, %0,%1
2738 st%- %1,%0"
2739 [(set_attr "type" "fcpys,fld,fst")])
2741 ;; Use register_operand for operand 1 to prevent compress_float_constant
2742 ;; from doing something silly. When optimizing we'll put things back
2743 ;; together anyway.
2744 (define_expand "extendsftf2"
2745 [(use (match_operand:TF 0 "register_operand" ""))
2746 (use (match_operand:SF 1 "register_operand" ""))]
2747 "TARGET_HAS_XFLOATING_LIBS"
2748 {
2749 rtx tmp = gen_reg_rtx (DFmode);
2750 emit_insn (gen_extendsfdf2 (tmp, operands[1]));
2751 emit_insn (gen_extenddftf2 (operands[0], tmp));
2752 DONE;
2753 })
2755 (define_expand "extenddftf2"
2756 [(use (match_operand:TF 0 "register_operand" ""))
2757 (use (match_operand:DF 1 "register_operand" ""))]
2758 "TARGET_HAS_XFLOATING_LIBS"
2759 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;")
2761 (define_insn "*truncdfsf2_ieee"
2762 [(set (match_operand:SF 0 "register_operand" "=&f")
2763 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2764 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2765 "cvt%-%,%/ %R1,%0"
2766 [(set_attr "type" "fadd")
2767 (set_attr "trap" "yes")
2768 (set_attr "round_suffix" "normal")
2769 (set_attr "trap_suffix" "u_su_sui")])
2771 (define_insn "truncdfsf2"
2772 [(set (match_operand:SF 0 "register_operand" "=f")
2773 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
2774 "TARGET_FP"
2775 "cvt%-%,%/ %R1,%0"
2776 [(set_attr "type" "fadd")
2777 (set_attr "trap" "yes")
2778 (set_attr "round_suffix" "normal")
2779 (set_attr "trap_suffix" "u_su_sui")])
2781 (define_expand "trunctfdf2"
2782 [(use (match_operand:DF 0 "register_operand" ""))
2783 (use (match_operand:TF 1 "general_operand" ""))]
2784 "TARGET_HAS_XFLOATING_LIBS"
2785 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;")
2787 (define_expand "trunctfsf2"
2788 [(use (match_operand:SF 0 "register_operand" ""))
2789 (use (match_operand:TF 1 "general_operand" ""))]
2790 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS"
2791 {
2792 rtx tmpf, sticky, arg, lo, hi;
2794 tmpf = gen_reg_rtx (DFmode);
2795 sticky = gen_reg_rtx (DImode);
2796 arg = copy_to_mode_reg (TFmode, operands[1]);
2797 lo = gen_lowpart (DImode, arg);
2798 hi = gen_highpart (DImode, arg);
2800 /* Convert the low word of the TFmode value into a sticky rounding bit,
2801 then or it into the low bit of the high word. This leaves the sticky
2802 bit at bit 48 of the fraction, which is representable in DFmode,
2803 which prevents rounding error in the final conversion to SFmode. */
2805 emit_insn (gen_rtx_SET (VOIDmode, sticky,
2806 gen_rtx_NE (DImode, lo, const0_rtx)));
2807 emit_insn (gen_iordi3 (hi, hi, sticky));
2808 emit_insn (gen_trunctfdf2 (tmpf, arg));
2809 emit_insn (gen_truncdfsf2 (operands[0], tmpf));
2810 DONE;
2811 })
2813 (define_insn "*divsf3_ieee"
2814 [(set (match_operand:SF 0 "register_operand" "=&f")
2815 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2816 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2817 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2818 "div%,%/ %R1,%R2,%0"
2819 [(set_attr "type" "fdiv")
2820 (set_attr "opsize" "si")
2821 (set_attr "trap" "yes")
2822 (set_attr "round_suffix" "normal")
2823 (set_attr "trap_suffix" "u_su_sui")])
2825 (define_insn "divsf3"
2826 [(set (match_operand:SF 0 "register_operand" "=f")
2827 (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2828 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2829 "TARGET_FP"
2830 "div%,%/ %R1,%R2,%0"
2831 [(set_attr "type" "fdiv")
2832 (set_attr "opsize" "si")
2833 (set_attr "trap" "yes")
2834 (set_attr "round_suffix" "normal")
2835 (set_attr "trap_suffix" "u_su_sui")])
2837 (define_insn "*divdf3_ieee"
2838 [(set (match_operand:DF 0 "register_operand" "=&f")
2839 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2840 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2841 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2842 "div%-%/ %R1,%R2,%0"
2843 [(set_attr "type" "fdiv")
2844 (set_attr "trap" "yes")
2845 (set_attr "round_suffix" "normal")
2846 (set_attr "trap_suffix" "u_su_sui")])
2848 (define_insn "divdf3"
2849 [(set (match_operand:DF 0 "register_operand" "=f")
2850 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2851 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2852 "TARGET_FP"
2853 "div%-%/ %R1,%R2,%0"
2854 [(set_attr "type" "fdiv")
2855 (set_attr "trap" "yes")
2856 (set_attr "round_suffix" "normal")
2857 (set_attr "trap_suffix" "u_su_sui")])
2859 (define_insn "*divdf_ext1"
2860 [(set (match_operand:DF 0 "register_operand" "=f")
2861 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2862 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2863 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2864 "div%-%/ %R1,%R2,%0"
2865 [(set_attr "type" "fdiv")
2866 (set_attr "trap" "yes")
2867 (set_attr "round_suffix" "normal")
2868 (set_attr "trap_suffix" "u_su_sui")])
2870 (define_insn "*divdf_ext2"
2871 [(set (match_operand:DF 0 "register_operand" "=f")
2872 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
2873 (float_extend:DF
2874 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2875 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2876 "div%-%/ %R1,%R2,%0"
2877 [(set_attr "type" "fdiv")
2878 (set_attr "trap" "yes")
2879 (set_attr "round_suffix" "normal")
2880 (set_attr "trap_suffix" "u_su_sui")])
2882 (define_insn "*divdf_ext3"
2883 [(set (match_operand:DF 0 "register_operand" "=f")
2884 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG"))
2885 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2886 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2887 "div%-%/ %R1,%R2,%0"
2888 [(set_attr "type" "fdiv")
2889 (set_attr "trap" "yes")
2890 (set_attr "round_suffix" "normal")
2891 (set_attr "trap_suffix" "u_su_sui")])
2893 (define_expand "divtf3"
2894 [(use (match_operand 0 "register_operand" ""))
2895 (use (match_operand 1 "general_operand" ""))
2896 (use (match_operand 2 "general_operand" ""))]
2897 "TARGET_HAS_XFLOATING_LIBS"
2898 "alpha_emit_xfloating_arith (DIV, operands); DONE;")
2900 (define_insn "*mulsf3_ieee"
2901 [(set (match_operand:SF 0 "register_operand" "=&f")
2902 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2903 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2904 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2905 "mul%,%/ %R1,%R2,%0"
2906 [(set_attr "type" "fmul")
2907 (set_attr "trap" "yes")
2908 (set_attr "round_suffix" "normal")
2909 (set_attr "trap_suffix" "u_su_sui")])
2911 (define_insn "mulsf3"
2912 [(set (match_operand:SF 0 "register_operand" "=f")
2913 (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG")
2914 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2915 "TARGET_FP"
2916 "mul%,%/ %R1,%R2,%0"
2917 [(set_attr "type" "fmul")
2918 (set_attr "trap" "yes")
2919 (set_attr "round_suffix" "normal")
2920 (set_attr "trap_suffix" "u_su_sui")])
2922 (define_insn "*muldf3_ieee"
2923 [(set (match_operand:DF 0 "register_operand" "=&f")
2924 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2925 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2926 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2927 "mul%-%/ %R1,%R2,%0"
2928 [(set_attr "type" "fmul")
2929 (set_attr "trap" "yes")
2930 (set_attr "round_suffix" "normal")
2931 (set_attr "trap_suffix" "u_su_sui")])
2933 (define_insn "muldf3"
2934 [(set (match_operand:DF 0 "register_operand" "=f")
2935 (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG")
2936 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2937 "TARGET_FP"
2938 "mul%-%/ %R1,%R2,%0"
2939 [(set_attr "type" "fmul")
2940 (set_attr "trap" "yes")
2941 (set_attr "round_suffix" "normal")
2942 (set_attr "trap_suffix" "u_su_sui")])
2944 (define_insn "*muldf_ext1"
2945 [(set (match_operand:DF 0 "register_operand" "=f")
2946 (mult:DF (float_extend:DF
2947 (match_operand:SF 1 "reg_or_0_operand" "fG"))
2948 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
2949 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2950 "mul%-%/ %R1,%R2,%0"
2951 [(set_attr "type" "fmul")
2952 (set_attr "trap" "yes")
2953 (set_attr "round_suffix" "normal")
2954 (set_attr "trap_suffix" "u_su_sui")])
2956 (define_insn "*muldf_ext2"
2957 [(set (match_operand:DF 0 "register_operand" "=f")
2958 (mult:DF (float_extend:DF
2959 (match_operand:SF 1 "reg_or_0_operand" "%fG"))
2960 (float_extend:DF
2961 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
2962 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
2963 "mul%-%/ %R1,%R2,%0"
2964 [(set_attr "type" "fmul")
2965 (set_attr "trap" "yes")
2966 (set_attr "round_suffix" "normal")
2967 (set_attr "trap_suffix" "u_su_sui")])
2969 (define_expand "multf3"
2970 [(use (match_operand 0 "register_operand" ""))
2971 (use (match_operand 1 "general_operand" ""))
2972 (use (match_operand 2 "general_operand" ""))]
2973 "TARGET_HAS_XFLOATING_LIBS"
2974 "alpha_emit_xfloating_arith (MULT, operands); DONE;")
2976 (define_insn "*subsf3_ieee"
2977 [(set (match_operand:SF 0 "register_operand" "=&f")
2978 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2979 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2980 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
2981 "sub%,%/ %R1,%R2,%0"
2982 [(set_attr "type" "fadd")
2983 (set_attr "trap" "yes")
2984 (set_attr "round_suffix" "normal")
2985 (set_attr "trap_suffix" "u_su_sui")])
2987 (define_insn "subsf3"
2988 [(set (match_operand:SF 0 "register_operand" "=f")
2989 (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG")
2990 (match_operand:SF 2 "reg_or_0_operand" "fG")))]
2991 "TARGET_FP"
2992 "sub%,%/ %R1,%R2,%0"
2993 [(set_attr "type" "fadd")
2994 (set_attr "trap" "yes")
2995 (set_attr "round_suffix" "normal")
2996 (set_attr "trap_suffix" "u_su_sui")])
2998 (define_insn "*subdf3_ieee"
2999 [(set (match_operand:DF 0 "register_operand" "=&f")
3000 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
3001 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
3002 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3003 "sub%-%/ %R1,%R2,%0"
3004 [(set_attr "type" "fadd")
3005 (set_attr "trap" "yes")
3006 (set_attr "round_suffix" "normal")
3007 (set_attr "trap_suffix" "u_su_sui")])
3009 (define_insn "subdf3"
3010 [(set (match_operand:DF 0 "register_operand" "=f")
3011 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
3012 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
3013 "TARGET_FP"
3014 "sub%-%/ %R1,%R2,%0"
3015 [(set_attr "type" "fadd")
3016 (set_attr "trap" "yes")
3017 (set_attr "round_suffix" "normal")
3018 (set_attr "trap_suffix" "u_su_sui")])
3020 (define_insn "*subdf_ext1"
3021 [(set (match_operand:DF 0 "register_operand" "=f")
3022 (minus:DF (float_extend:DF
3023 (match_operand:SF 1 "reg_or_0_operand" "fG"))
3024 (match_operand:DF 2 "reg_or_0_operand" "fG")))]
3025 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3026 "sub%-%/ %R1,%R2,%0"
3027 [(set_attr "type" "fadd")
3028 (set_attr "trap" "yes")
3029 (set_attr "round_suffix" "normal")
3030 (set_attr "trap_suffix" "u_su_sui")])
3032 (define_insn "*subdf_ext2"
3033 [(set (match_operand:DF 0 "register_operand" "=f")
3034 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG")
3035 (float_extend:DF
3036 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
3037 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3038 "sub%-%/ %R1,%R2,%0"
3039 [(set_attr "type" "fadd")
3040 (set_attr "trap" "yes")
3041 (set_attr "round_suffix" "normal")
3042 (set_attr "trap_suffix" "u_su_sui")])
3044 (define_insn "*subdf_ext3"
3045 [(set (match_operand:DF 0 "register_operand" "=f")
3046 (minus:DF (float_extend:DF
3047 (match_operand:SF 1 "reg_or_0_operand" "fG"))
3048 (float_extend:DF
3049 (match_operand:SF 2 "reg_or_0_operand" "fG"))))]
3050 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3051 "sub%-%/ %R1,%R2,%0"
3052 [(set_attr "type" "fadd")
3053 (set_attr "trap" "yes")
3054 (set_attr "round_suffix" "normal")
3055 (set_attr "trap_suffix" "u_su_sui")])
3057 (define_expand "subtf3"
3058 [(use (match_operand 0 "register_operand" ""))
3059 (use (match_operand 1 "general_operand" ""))
3060 (use (match_operand 2 "general_operand" ""))]
3061 "TARGET_HAS_XFLOATING_LIBS"
3062 "alpha_emit_xfloating_arith (MINUS, operands); DONE;")
3064 (define_insn "*sqrtsf2_ieee"
3065 [(set (match_operand:SF 0 "register_operand" "=&f")
3066 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
3067 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3068 "sqrt%,%/ %R1,%0"
3069 [(set_attr "type" "fsqrt")
3070 (set_attr "opsize" "si")
3071 (set_attr "trap" "yes")
3072 (set_attr "round_suffix" "normal")
3073 (set_attr "trap_suffix" "u_su_sui")])
3075 (define_insn "sqrtsf2"
3076 [(set (match_operand:SF 0 "register_operand" "=f")
3077 (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))]
3078 "TARGET_FP && TARGET_FIX"
3079 "sqrt%,%/ %R1,%0"
3080 [(set_attr "type" "fsqrt")
3081 (set_attr "opsize" "si")
3082 (set_attr "trap" "yes")
3083 (set_attr "round_suffix" "normal")
3084 (set_attr "trap_suffix" "u_su_sui")])
3086 (define_insn "*sqrtdf2_ieee"
3087 [(set (match_operand:DF 0 "register_operand" "=&f")
3088 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
3089 "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU"
3090 "sqrt%-%/ %R1,%0"
3091 [(set_attr "type" "fsqrt")
3092 (set_attr "trap" "yes")
3093 (set_attr "round_suffix" "normal")
3094 (set_attr "trap_suffix" "u_su_sui")])
3096 (define_insn "sqrtdf2"
3097 [(set (match_operand:DF 0 "register_operand" "=f")
3098 (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))]
3099 "TARGET_FP && TARGET_FIX"
3100 "sqrt%-%/ %R1,%0"
3101 [(set_attr "type" "fsqrt")
3102 (set_attr "trap" "yes")
3103 (set_attr "round_suffix" "normal")
3104 (set_attr "trap_suffix" "u_su_sui")])
3105 \f
3106 ;; Next are all the integer comparisons, and conditional moves and branches
3107 ;; and some of the related define_expand's and define_split's.
3109 (define_insn "*setcc_internal"
3110 [(set (match_operand 0 "register_operand" "=r")
3111 (match_operator 1 "alpha_comparison_operator"
3112 [(match_operand:DI 2 "register_operand" "r")
3113 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))]
3114 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3115 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3116 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3117 "cmp%C1 %2,%3,%0"
3118 [(set_attr "type" "icmp")])
3120 ;; Yes, we can technically support reg_or_8bit_operand in operand 2,
3121 ;; but that's non-canonical rtl and allowing that causes inefficiencies
3122 ;; from cse on.
3123 (define_insn "*setcc_swapped_internal"
3124 [(set (match_operand 0 "register_operand" "=r")
3125 (match_operator 1 "alpha_swapped_comparison_operator"
3126 [(match_operand:DI 2 "register_operand" "r")
3127 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))]
3128 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3129 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3130 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3131 "cmp%c1 %r3,%2,%0"
3132 [(set_attr "type" "icmp")])
3134 ;; Use match_operator rather than ne directly so that we can match
3135 ;; multiple integer modes.
3136 (define_insn "*setne_internal"
3137 [(set (match_operand 0 "register_operand" "=r")
3138 (match_operator 1 "signed_comparison_operator"
3139 [(match_operand:DI 2 "register_operand" "r")
3140 (const_int 0)]))]
3141 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT
3142 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8
3143 && GET_CODE (operands[1]) == NE
3144 && GET_MODE (operands[0]) == GET_MODE (operands[1])"
3145 "cmpult $31,%2,%0"
3146 [(set_attr "type" "icmp")])
3148 ;; The mode folding trick can't be used with const_int operands, since
3149 ;; reload needs to know the proper mode.
3150 ;;
3151 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand
3152 ;; in order to create more pairs of constants. As long as we're allowing
3153 ;; two constants at the same time, and will have to reload one of them...
3155 (define_insn "*movqicc_internal"
3156 [(set (match_operand:QI 0 "register_operand" "=r,r,r,r")
3157 (if_then_else:QI
3158 (match_operator 2 "signed_comparison_operator"
3159 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3160 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3161 (match_operand:QI 1 "add_operand" "rI,0,rI,0")
3162 (match_operand:QI 5 "add_operand" "0,rI,0,rI")))]
3163 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3164 "@
3165 cmov%C2 %r3,%1,%0
3166 cmov%D2 %r3,%5,%0
3167 cmov%c2 %r4,%1,%0
3168 cmov%d2 %r4,%5,%0"
3169 [(set_attr "type" "icmov")])
3171 (define_insn "*movhicc_internal"
3172 [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
3173 (if_then_else:HI
3174 (match_operator 2 "signed_comparison_operator"
3175 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3176 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3177 (match_operand:HI 1 "add_operand" "rI,0,rI,0")
3178 (match_operand:HI 5 "add_operand" "0,rI,0,rI")))]
3179 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3180 "@
3181 cmov%C2 %r3,%1,%0
3182 cmov%D2 %r3,%5,%0
3183 cmov%c2 %r4,%1,%0
3184 cmov%d2 %r4,%5,%0"
3185 [(set_attr "type" "icmov")])
3187 (define_insn "*movsicc_internal"
3188 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
3189 (if_then_else:SI
3190 (match_operator 2 "signed_comparison_operator"
3191 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3192 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3193 (match_operand:SI 1 "add_operand" "rI,0,rI,0")
3194 (match_operand:SI 5 "add_operand" "0,rI,0,rI")))]
3195 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3196 "@
3197 cmov%C2 %r3,%1,%0
3198 cmov%D2 %r3,%5,%0
3199 cmov%c2 %r4,%1,%0
3200 cmov%d2 %r4,%5,%0"
3201 [(set_attr "type" "icmov")])
3203 (define_insn "*movdicc_internal"
3204 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
3205 (if_then_else:DI
3206 (match_operator 2 "signed_comparison_operator"
3207 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J")
3208 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")])
3209 (match_operand:DI 1 "add_operand" "rI,0,rI,0")
3210 (match_operand:DI 5 "add_operand" "0,rI,0,rI")))]
3211 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)"
3212 "@
3213 cmov%C2 %r3,%1,%0
3214 cmov%D2 %r3,%5,%0
3215 cmov%c2 %r4,%1,%0
3216 cmov%d2 %r4,%5,%0"
3217 [(set_attr "type" "icmov")])
3219 (define_insn "*movqicc_lbc"
3220 [(set (match_operand:QI 0 "register_operand" "=r,r")
3221 (if_then_else:QI
3222 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3223 (const_int 1)
3224 (const_int 0))
3225 (const_int 0))
3226 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3227 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3228 ""
3229 "@
3230 cmovlbc %r2,%1,%0
3231 cmovlbs %r2,%3,%0"
3232 [(set_attr "type" "icmov")])
3234 (define_insn "*movhicc_lbc"
3235 [(set (match_operand:HI 0 "register_operand" "=r,r")
3236 (if_then_else:HI
3237 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3238 (const_int 1)
3239 (const_int 0))
3240 (const_int 0))
3241 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3242 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3243 ""
3244 "@
3245 cmovlbc %r2,%1,%0
3246 cmovlbs %r2,%3,%0"
3247 [(set_attr "type" "icmov")])
3249 (define_insn "*movsicc_lbc"
3250 [(set (match_operand:SI 0 "register_operand" "=r,r")
3251 (if_then_else:SI
3252 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3253 (const_int 1)
3254 (const_int 0))
3255 (const_int 0))
3256 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3257 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3258 ""
3259 "@
3260 cmovlbc %r2,%1,%0
3261 cmovlbs %r2,%3,%0"
3262 [(set_attr "type" "icmov")])
3264 (define_insn "*movdicc_lbc"
3265 [(set (match_operand:DI 0 "register_operand" "=r,r")
3266 (if_then_else:DI
3267 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3268 (const_int 1)
3269 (const_int 0))
3270 (const_int 0))
3271 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3272 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3273 ""
3274 "@
3275 cmovlbc %r2,%1,%0
3276 cmovlbs %r2,%3,%0"
3277 [(set_attr "type" "icmov")])
3279 (define_insn "*movqicc_lbs"
3280 [(set (match_operand:QI 0 "register_operand" "=r,r")
3281 (if_then_else:QI
3282 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3283 (const_int 1)
3284 (const_int 0))
3285 (const_int 0))
3286 (match_operand:QI 1 "reg_or_8bit_operand" "rI,0")
3287 (match_operand:QI 3 "reg_or_8bit_operand" "0,rI")))]
3288 ""
3289 "@
3290 cmovlbs %r2,%1,%0
3291 cmovlbc %r2,%3,%0"
3292 [(set_attr "type" "icmov")])
3294 (define_insn "*movhicc_lbs"
3295 [(set (match_operand:HI 0 "register_operand" "=r,r")
3296 (if_then_else:HI
3297 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3298 (const_int 1)
3299 (const_int 0))
3300 (const_int 0))
3301 (match_operand:HI 1 "reg_or_8bit_operand" "rI,0")
3302 (match_operand:HI 3 "reg_or_8bit_operand" "0,rI")))]
3303 ""
3304 "@
3305 cmovlbs %r2,%1,%0
3306 cmovlbc %r2,%3,%0"
3307 [(set_attr "type" "icmov")])
3309 (define_insn "*movsicc_lbs"
3310 [(set (match_operand:SI 0 "register_operand" "=r,r")
3311 (if_then_else:SI
3312 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3313 (const_int 1)
3314 (const_int 0))
3315 (const_int 0))
3316 (match_operand:SI 1 "reg_or_8bit_operand" "rI,0")
3317 (match_operand:SI 3 "reg_or_8bit_operand" "0,rI")))]
3318 ""
3319 "@
3320 cmovlbs %r2,%1,%0
3321 cmovlbc %r2,%3,%0"
3322 [(set_attr "type" "icmov")])
3324 (define_insn "*movdicc_lbs"
3325 [(set (match_operand:DI 0 "register_operand" "=r,r")
3326 (if_then_else:DI
3327 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ")
3328 (const_int 1)
3329 (const_int 0))
3330 (const_int 0))
3331 (match_operand:DI 1 "reg_or_8bit_operand" "rI,0")
3332 (match_operand:DI 3 "reg_or_8bit_operand" "0,rI")))]
3333 ""
3334 "@
3335 cmovlbs %r2,%1,%0
3336 cmovlbc %r2,%3,%0"
3337 [(set_attr "type" "icmov")])
3339 ;; For ABS, we have two choices, depending on whether the input and output
3340 ;; registers are the same or not.
3341 (define_expand "absdi2"
3342 [(set (match_operand:DI 0 "register_operand" "")
3343 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3344 ""
3345 {
3346 if (rtx_equal_p (operands[0], operands[1]))
3347 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode)));
3348 else
3349 emit_insn (gen_absdi2_diff (operands[0], operands[1]));
3350 DONE;
3351 })
3353 (define_expand "absdi2_same"
3354 [(set (match_operand:DI 1 "register_operand" "")
3355 (neg:DI (match_operand:DI 0 "register_operand" "")))
3356 (set (match_dup 0)
3357 (if_then_else:DI (ge (match_dup 0) (const_int 0))
3358 (match_dup 0)
3359 (match_dup 1)))]
3360 ""
3361 "")
3363 (define_expand "absdi2_diff"
3364 [(set (match_operand:DI 0 "register_operand" "")
3365 (neg:DI (match_operand:DI 1 "register_operand" "")))
3366 (set (match_dup 0)
3367 (if_then_else:DI (lt (match_dup 1) (const_int 0))
3368 (match_dup 0)
3369 (match_dup 1)))]
3370 ""
3371 "")
3373 (define_split
3374 [(set (match_operand:DI 0 "register_operand" "")
3375 (abs:DI (match_dup 0)))
3376 (clobber (match_operand:DI 1 "register_operand" ""))]
3377 ""
3378 [(set (match_dup 1) (neg:DI (match_dup 0)))
3379 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0))
3380 (match_dup 0) (match_dup 1)))]
3381 "")
3383 (define_split
3384 [(set (match_operand:DI 0 "register_operand" "")
3385 (abs:DI (match_operand:DI 1 "register_operand" "")))]
3386 "! rtx_equal_p (operands[0], operands[1])"
3387 [(set (match_dup 0) (neg:DI (match_dup 1)))
3388 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0))
3389 (match_dup 0) (match_dup 1)))]
3390 "")
3392 (define_split
3393 [(set (match_operand:DI 0 "register_operand" "")
3394 (neg:DI (abs:DI (match_dup 0))))
3395 (clobber (match_operand:DI 1 "register_operand" ""))]
3396 ""
3397 [(set (match_dup 1) (neg:DI (match_dup 0)))
3398 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0))
3399 (match_dup 0) (match_dup 1)))]
3400 "")
3402 (define_split
3403 [(set (match_operand:DI 0 "register_operand" "")
3404 (neg:DI (abs:DI (match_operand:DI 1 "register_operand" ""))))]
3405 "! rtx_equal_p (operands[0], operands[1])"
3406 [(set (match_dup 0) (neg:DI (match_dup 1)))
3407 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0))
3408 (match_dup 0) (match_dup 1)))]
3409 "")
3411 (define_insn "sminqi3"
3412 [(set (match_operand:QI 0 "register_operand" "=r")
3413 (smin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3414 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3415 "TARGET_MAX"
3416 "minsb8 %r1,%2,%0"
3417 [(set_attr "type" "mvi")])
3419 (define_insn "uminqi3"
3420 [(set (match_operand:QI 0 "register_operand" "=r")
3421 (umin:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3422 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3423 "TARGET_MAX"
3424 "minub8 %r1,%2,%0"
3425 [(set_attr "type" "mvi")])
3427 (define_insn "smaxqi3"
3428 [(set (match_operand:QI 0 "register_operand" "=r")
3429 (smax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3430 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3431 "TARGET_MAX"
3432 "maxsb8 %r1,%2,%0"
3433 [(set_attr "type" "mvi")])
3435 (define_insn "umaxqi3"
3436 [(set (match_operand:QI 0 "register_operand" "=r")
3437 (umax:QI (match_operand:QI 1 "reg_or_0_operand" "%rJ")
3438 (match_operand:QI 2 "reg_or_8bit_operand" "rI")))]
3439 "TARGET_MAX"
3440 "maxub8 %r1,%2,%0"
3441 [(set_attr "type" "mvi")])
3443 (define_insn "sminhi3"
3444 [(set (match_operand:HI 0 "register_operand" "=r")
3445 (smin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3446 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3447 "TARGET_MAX"
3448 "minsw4 %r1,%2,%0"
3449 [(set_attr "type" "mvi")])
3451 (define_insn "uminhi3"
3452 [(set (match_operand:HI 0 "register_operand" "=r")
3453 (umin:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3454 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3455 "TARGET_MAX"
3456 "minuw4 %r1,%2,%0"
3457 [(set_attr "type" "mvi")])
3459 (define_insn "smaxhi3"
3460 [(set (match_operand:HI 0 "register_operand" "=r")
3461 (smax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3462 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3463 "TARGET_MAX"
3464 "maxsw4 %r1,%2,%0"
3465 [(set_attr "type" "mvi")])
3467 (define_insn "umaxhi3"
3468 [(set (match_operand:HI 0 "register_operand" "=r")
3469 (umax:HI (match_operand:HI 1 "reg_or_0_operand" "%rJ")
3470 (match_operand:HI 2 "reg_or_8bit_operand" "rI")))]
3471 "TARGET_MAX"
3472 "maxuw4 %r1,%2,%0"
3473 [(set_attr "type" "mvi")])
3475 (define_expand "smaxdi3"
3476 [(set (match_dup 3)
3477 (le:DI (match_operand:DI 1 "reg_or_0_operand" "")
3478 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3479 (set (match_operand:DI 0 "register_operand" "")
3480 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3481 (match_dup 1) (match_dup 2)))]
3482 ""
3483 { operands[3] = gen_reg_rtx (DImode); })
3485 (define_split
3486 [(set (match_operand:DI 0 "register_operand" "")
3487 (smax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3488 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3489 (clobber (match_operand:DI 3 "register_operand" ""))]
3490 "operands[2] != const0_rtx"
3491 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2)))
3492 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3493 (match_dup 1) (match_dup 2)))]
3494 "")
3496 (define_insn "*smax_const0"
3497 [(set (match_operand:DI 0 "register_operand" "=r")
3498 (smax:DI (match_operand:DI 1 "register_operand" "0")
3499 (const_int 0)))]
3500 ""
3501 "cmovlt %0,0,%0"
3502 [(set_attr "type" "icmov")])
3504 (define_expand "smindi3"
3505 [(set (match_dup 3)
3506 (lt:DI (match_operand:DI 1 "reg_or_0_operand" "")
3507 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3508 (set (match_operand:DI 0 "register_operand" "")
3509 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3510 (match_dup 1) (match_dup 2)))]
3511 ""
3512 { operands[3] = gen_reg_rtx (DImode); })
3514 (define_split
3515 [(set (match_operand:DI 0 "register_operand" "")
3516 (smin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3517 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3518 (clobber (match_operand:DI 3 "register_operand" ""))]
3519 "operands[2] != const0_rtx"
3520 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2)))
3521 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3522 (match_dup 1) (match_dup 2)))]
3523 "")
3525 (define_insn "*smin_const0"
3526 [(set (match_operand:DI 0 "register_operand" "=r")
3527 (smin:DI (match_operand:DI 1 "register_operand" "0")
3528 (const_int 0)))]
3529 ""
3530 "cmovgt %0,0,%0"
3531 [(set_attr "type" "icmov")])
3533 (define_expand "umaxdi3"
3534 [(set (match_dup 3)
3535 (leu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3536 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3537 (set (match_operand:DI 0 "register_operand" "")
3538 (if_then_else:DI (eq (match_dup 3) (const_int 0))
3539 (match_dup 1) (match_dup 2)))]
3540 ""
3541 "operands[3] = gen_reg_rtx (DImode);")
3543 (define_split
3544 [(set (match_operand:DI 0 "register_operand" "")
3545 (umax:DI (match_operand:DI 1 "reg_or_0_operand" "")
3546 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3547 (clobber (match_operand:DI 3 "register_operand" ""))]
3548 "operands[2] != const0_rtx"
3549 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2)))
3550 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0))
3551 (match_dup 1) (match_dup 2)))]
3552 "")
3554 (define_expand "umindi3"
3555 [(set (match_dup 3)
3556 (ltu:DI (match_operand:DI 1 "reg_or_0_operand" "")
3557 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3558 (set (match_operand:DI 0 "register_operand" "")
3559 (if_then_else:DI (ne (match_dup 3) (const_int 0))
3560 (match_dup 1) (match_dup 2)))]
3561 ""
3562 "operands[3] = gen_reg_rtx (DImode);")
3564 (define_split
3565 [(set (match_operand:DI 0 "register_operand" "")
3566 (umin:DI (match_operand:DI 1 "reg_or_0_operand" "")
3567 (match_operand:DI 2 "reg_or_8bit_operand" "")))
3568 (clobber (match_operand:DI 3 "register_operand" ""))]
3569 "operands[2] != const0_rtx"
3570 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2)))
3571 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0))
3572 (match_dup 1) (match_dup 2)))]
3573 "")
3575 (define_insn "*bcc_normal"
3576 [(set (pc)
3577 (if_then_else
3578 (match_operator 1 "signed_comparison_operator"
3579 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
3580 (const_int 0)])
3581 (label_ref (match_operand 0 "" ""))
3582 (pc)))]
3583 ""
3584 "b%C1 %r2,%0"
3585 [(set_attr "type" "ibr")])
3587 (define_insn "*bcc_reverse"
3588 [(set (pc)
3589 (if_then_else
3590 (match_operator 1 "signed_comparison_operator"
3591 [(match_operand:DI 2 "register_operand" "r")
3592 (const_int 0)])
3594 (pc)
3595 (label_ref (match_operand 0 "" ""))))]
3596 ""
3597 "b%c1 %2,%0"
3598 [(set_attr "type" "ibr")])
3600 (define_insn "*blbs_normal"
3601 [(set (pc)
3602 (if_then_else
3603 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3604 (const_int 1)
3605 (const_int 0))
3606 (const_int 0))
3607 (label_ref (match_operand 0 "" ""))
3608 (pc)))]
3609 ""
3610 "blbs %r1,%0"
3611 [(set_attr "type" "ibr")])
3613 (define_insn "*blbc_normal"
3614 [(set (pc)
3615 (if_then_else
3616 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ")
3617 (const_int 1)
3618 (const_int 0))
3619 (const_int 0))
3620 (label_ref (match_operand 0 "" ""))
3621 (pc)))]
3622 ""
3623 "blbc %r1,%0"
3624 [(set_attr "type" "ibr")])
3626 (define_split
3627 [(parallel
3628 [(set (pc)
3629 (if_then_else
3630 (match_operator 1 "comparison_operator"
3631 [(zero_extract:DI (match_operand:DI 2 "register_operand" "")
3632 (const_int 1)
3633 (match_operand:DI 3 "const_int_operand" ""))
3634 (const_int 0)])
3635 (label_ref (match_operand 0 "" ""))
3636 (pc)))
3637 (clobber (match_operand:DI 4 "register_operand" ""))])]
3638 "INTVAL (operands[3]) != 0"
3639 [(set (match_dup 4)
3640 (lshiftrt:DI (match_dup 2) (match_dup 3)))
3641 (set (pc)
3642 (if_then_else (match_op_dup 1
3643 [(zero_extract:DI (match_dup 4)
3644 (const_int 1)
3645 (const_int 0))
3646 (const_int 0)])
3647 (label_ref (match_dup 0))
3648 (pc)))]
3649 "")
3650 \f
3651 ;; The following are the corresponding floating-point insns. Recall
3652 ;; we need to have variants that expand the arguments from SFmode
3653 ;; to DFmode.
3655 (define_insn "*cmpdf_ieee"
3656 [(set (match_operand:DF 0 "register_operand" "=&f")
3657 (match_operator:DF 1 "alpha_fp_comparison_operator"
3658 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3659 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3660 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3661 "cmp%-%C1%/ %R2,%R3,%0"
3662 [(set_attr "type" "fadd")
3663 (set_attr "trap" "yes")
3664 (set_attr "trap_suffix" "su")])
3666 (define_insn "*cmpdf_internal"
3667 [(set (match_operand:DF 0 "register_operand" "=f")
3668 (match_operator:DF 1 "alpha_fp_comparison_operator"
3669 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3670 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3671 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3672 "cmp%-%C1%/ %R2,%R3,%0"
3673 [(set_attr "type" "fadd")
3674 (set_attr "trap" "yes")
3675 (set_attr "trap_suffix" "su")])
3677 (define_insn "*cmpdf_ieee_ext1"
3678 [(set (match_operand:DF 0 "register_operand" "=&f")
3679 (match_operator:DF 1 "alpha_fp_comparison_operator"
3680 [(float_extend:DF
3681 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3682 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3683 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3684 "cmp%-%C1%/ %R2,%R3,%0"
3685 [(set_attr "type" "fadd")
3686 (set_attr "trap" "yes")
3687 (set_attr "trap_suffix" "su")])
3689 (define_insn "*cmpdf_ext1"
3690 [(set (match_operand:DF 0 "register_operand" "=f")
3691 (match_operator:DF 1 "alpha_fp_comparison_operator"
3692 [(float_extend:DF
3693 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3694 (match_operand:DF 3 "reg_or_0_operand" "fG")]))]
3695 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3696 "cmp%-%C1%/ %R2,%R3,%0"
3697 [(set_attr "type" "fadd")
3698 (set_attr "trap" "yes")
3699 (set_attr "trap_suffix" "su")])
3701 (define_insn "*cmpdf_ieee_ext2"
3702 [(set (match_operand:DF 0 "register_operand" "=&f")
3703 (match_operator:DF 1 "alpha_fp_comparison_operator"
3704 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3705 (float_extend:DF
3706 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3707 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3708 "cmp%-%C1%/ %R2,%R3,%0"
3709 [(set_attr "type" "fadd")
3710 (set_attr "trap" "yes")
3711 (set_attr "trap_suffix" "su")])
3713 (define_insn "*cmpdf_ext2"
3714 [(set (match_operand:DF 0 "register_operand" "=f")
3715 (match_operator:DF 1 "alpha_fp_comparison_operator"
3716 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3717 (float_extend:DF
3718 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3719 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3720 "cmp%-%C1%/ %R2,%R3,%0"
3721 [(set_attr "type" "fadd")
3722 (set_attr "trap" "yes")
3723 (set_attr "trap_suffix" "su")])
3725 (define_insn "*cmpdf_ieee_ext3"
3726 [(set (match_operand:DF 0 "register_operand" "=&f")
3727 (match_operator:DF 1 "alpha_fp_comparison_operator"
3728 [(float_extend:DF
3729 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3730 (float_extend:DF
3731 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3732 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU"
3733 "cmp%-%C1%/ %R2,%R3,%0"
3734 [(set_attr "type" "fadd")
3735 (set_attr "trap" "yes")
3736 (set_attr "trap_suffix" "su")])
3738 (define_insn "*cmpdf_ext3"
3739 [(set (match_operand:DF 0 "register_operand" "=f")
3740 (match_operator:DF 1 "alpha_fp_comparison_operator"
3741 [(float_extend:DF
3742 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3743 (float_extend:DF
3744 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))]
3745 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU"
3746 "cmp%-%C1%/ %R2,%R3,%0"
3747 [(set_attr "type" "fadd")
3748 (set_attr "trap" "yes")
3749 (set_attr "trap_suffix" "su")])
3751 (define_insn "*movdfcc_internal"
3752 [(set (match_operand:DF 0 "register_operand" "=f,f")
3753 (if_then_else:DF
3754 (match_operator 3 "signed_comparison_operator"
3755 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3756 (match_operand:DF 2 "const0_operand" "G,G")])
3757 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3758 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3759 "TARGET_FP"
3760 "@
3761 fcmov%C3 %R4,%R1,%0
3762 fcmov%D3 %R4,%R5,%0"
3763 [(set_attr "type" "fcmov")])
3765 (define_insn "*movsfcc_internal"
3766 [(set (match_operand:SF 0 "register_operand" "=f,f")
3767 (if_then_else:SF
3768 (match_operator 3 "signed_comparison_operator"
3769 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3770 (match_operand:DF 2 "const0_operand" "G,G")])
3771 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3772 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3773 "TARGET_FP"
3774 "@
3775 fcmov%C3 %R4,%R1,%0
3776 fcmov%D3 %R4,%R5,%0"
3777 [(set_attr "type" "fcmov")])
3779 (define_insn "*movdfcc_ext1"
3780 [(set (match_operand:DF 0 "register_operand" "=f,f")
3781 (if_then_else:DF
3782 (match_operator 3 "signed_comparison_operator"
3783 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG")
3784 (match_operand:DF 2 "const0_operand" "G,G")])
3785 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3786 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3787 "TARGET_FP"
3788 "@
3789 fcmov%C3 %R4,%R1,%0
3790 fcmov%D3 %R4,%R5,%0"
3791 [(set_attr "type" "fcmov")])
3793 (define_insn "*movdfcc_ext2"
3794 [(set (match_operand:DF 0 "register_operand" "=f,f")
3795 (if_then_else:DF
3796 (match_operator 3 "signed_comparison_operator"
3797 [(float_extend:DF
3798 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3799 (match_operand:DF 2 "const0_operand" "G,G")])
3800 (match_operand:DF 1 "reg_or_0_operand" "fG,0")
3801 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3802 "TARGET_FP"
3803 "@
3804 fcmov%C3 %R4,%R1,%0
3805 fcmov%D3 %R4,%R5,%0"
3806 [(set_attr "type" "fcmov")])
3808 (define_insn "*movdfcc_ext3"
3809 [(set (match_operand:SF 0 "register_operand" "=f,f")
3810 (if_then_else:SF
3811 (match_operator 3 "signed_comparison_operator"
3812 [(float_extend:DF
3813 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3814 (match_operand:DF 2 "const0_operand" "G,G")])
3815 (match_operand:SF 1 "reg_or_0_operand" "fG,0")
3816 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))]
3817 "TARGET_FP"
3818 "@
3819 fcmov%C3 %R4,%R1,%0
3820 fcmov%D3 %R4,%R5,%0"
3821 [(set_attr "type" "fcmov")])
3823 (define_insn "*movdfcc_ext4"
3824 [(set (match_operand:DF 0 "register_operand" "=f,f")
3825 (if_then_else:DF
3826 (match_operator 3 "signed_comparison_operator"
3827 [(float_extend:DF
3828 (match_operand:SF 4 "reg_or_0_operand" "fG,fG"))
3829 (match_operand:DF 2 "const0_operand" "G,G")])
3830 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0"))
3831 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))]
3832 "TARGET_FP"
3833 "@
3834 fcmov%C3 %R4,%R1,%0
3835 fcmov%D3 %R4,%R5,%0"
3836 [(set_attr "type" "fcmov")])
3838 (define_expand "smaxdf3"
3839 [(set (match_dup 3)
3840 (le:DF (match_operand:DF 1 "reg_or_0_operand" "")
3841 (match_operand:DF 2 "reg_or_0_operand" "")))
3842 (set (match_operand:DF 0 "register_operand" "")
3843 (if_then_else:DF (eq (match_dup 3) (match_dup 4))
3844 (match_dup 1) (match_dup 2)))]
3845 "TARGET_FP"
3846 {
3847 operands[3] = gen_reg_rtx (DFmode);
3848 operands[4] = CONST0_RTX (DFmode);
3849 })
3851 (define_expand "smindf3"
3852 [(set (match_dup 3)
3853 (lt:DF (match_operand:DF 1 "reg_or_0_operand" "")
3854 (match_operand:DF 2 "reg_or_0_operand" "")))
3855 (set (match_operand:DF 0 "register_operand" "")
3856 (if_then_else:DF (ne (match_dup 3) (match_dup 4))
3857 (match_dup 1) (match_dup 2)))]
3858 "TARGET_FP"
3859 {
3860 operands[3] = gen_reg_rtx (DFmode);
3861 operands[4] = CONST0_RTX (DFmode);
3862 })
3864 (define_expand "smaxsf3"
3865 [(set (match_dup 3)
3866 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3867 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3868 (set (match_operand:SF 0 "register_operand" "")
3869 (if_then_else:SF (eq (match_dup 3) (match_dup 4))
3870 (match_dup 1) (match_dup 2)))]
3871 "TARGET_FP"
3872 {
3873 operands[3] = gen_reg_rtx (DFmode);
3874 operands[4] = CONST0_RTX (DFmode);
3875 })
3877 (define_expand "sminsf3"
3878 [(set (match_dup 3)
3879 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" ""))
3880 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" ""))))
3881 (set (match_operand:SF 0 "register_operand" "")
3882 (if_then_else:SF (ne (match_dup 3) (match_dup 4))
3883 (match_dup 1) (match_dup 2)))]
3884 "TARGET_FP"
3885 {
3886 operands[3] = gen_reg_rtx (DFmode);
3887 operands[4] = CONST0_RTX (DFmode);
3888 })
3890 (define_insn "*fbcc_normal"
3891 [(set (pc)
3892 (if_then_else
3893 (match_operator 1 "signed_comparison_operator"
3894 [(match_operand:DF 2 "reg_or_0_operand" "fG")
3895 (match_operand:DF 3 "const0_operand" "G")])
3896 (label_ref (match_operand 0 "" ""))
3897 (pc)))]
3898 "TARGET_FP"
3899 "fb%C1 %R2,%0"
3900 [(set_attr "type" "fbr")])
3902 (define_insn "*fbcc_ext_normal"
3903 [(set (pc)
3904 (if_then_else
3905 (match_operator 1 "signed_comparison_operator"
3906 [(float_extend:DF
3907 (match_operand:SF 2 "reg_or_0_operand" "fG"))
3908 (match_operand:DF 3 "const0_operand" "G")])
3909 (label_ref (match_operand 0 "" ""))
3910 (pc)))]
3911 "TARGET_FP"
3912 "fb%C1 %R2,%0"
3913 [(set_attr "type" "fbr")])
3914 \f
3915 ;; These are the main define_expand's used to make conditional branches
3916 ;; and compares.
3918 (define_expand "cmpdf"
3919 [(set (cc0) (compare (match_operand:DF 0 "reg_or_0_operand" "")
3920 (match_operand:DF 1 "reg_or_0_operand" "")))]
3921 "TARGET_FP"
3922 {
3923 alpha_compare.op0 = operands[0];
3924 alpha_compare.op1 = operands[1];
3925 alpha_compare.fp_p = 1;
3926 DONE;
3927 })
3929 (define_expand "cmptf"
3930 [(set (cc0) (compare (match_operand:TF 0 "general_operand" "")
3931 (match_operand:TF 1 "general_operand" "")))]
3932 "TARGET_HAS_XFLOATING_LIBS"
3933 {
3934 alpha_compare.op0 = operands[0];
3935 alpha_compare.op1 = operands[1];
3936 alpha_compare.fp_p = 1;
3937 DONE;
3938 })
3940 (define_expand "cmpdi"
3941 [(set (cc0) (compare (match_operand:DI 0 "some_operand" "")
3942 (match_operand:DI 1 "some_operand" "")))]
3943 ""
3944 {
3945 alpha_compare.op0 = operands[0];
3946 alpha_compare.op1 = operands[1];
3947 alpha_compare.fp_p = 0;
3948 DONE;
3949 })
3951 (define_expand "beq"
3952 [(set (pc)
3953 (if_then_else (match_dup 1)
3954 (label_ref (match_operand 0 "" ""))
3955 (pc)))]
3956 ""
3957 "{ operands[1] = alpha_emit_conditional_branch (EQ); }")
3959 (define_expand "bne"
3960 [(set (pc)
3961 (if_then_else (match_dup 1)
3962 (label_ref (match_operand 0 "" ""))
3963 (pc)))]
3964 ""
3965 "{ operands[1] = alpha_emit_conditional_branch (NE); }")
3967 (define_expand "blt"
3968 [(set (pc)
3969 (if_then_else (match_dup 1)
3970 (label_ref (match_operand 0 "" ""))
3971 (pc)))]
3972 ""
3973 "{ operands[1] = alpha_emit_conditional_branch (LT); }")
3975 (define_expand "ble"
3976 [(set (pc)
3977 (if_then_else (match_dup 1)
3978 (label_ref (match_operand 0 "" ""))
3979 (pc)))]
3980 ""
3981 "{ operands[1] = alpha_emit_conditional_branch (LE); }")
3983 (define_expand "bgt"
3984 [(set (pc)
3985 (if_then_else (match_dup 1)
3986 (label_ref (match_operand 0 "" ""))
3987 (pc)))]
3988 ""
3989 "{ operands[1] = alpha_emit_conditional_branch (GT); }")
3991 (define_expand "bge"
3992 [(set (pc)
3993 (if_then_else (match_dup 1)
3994 (label_ref (match_operand 0 "" ""))
3995 (pc)))]
3996 ""
3997 "{ operands[1] = alpha_emit_conditional_branch (GE); }")
3999 (define_expand "bltu"
4000 [(set (pc)
4001 (if_then_else (match_dup 1)
4002 (label_ref (match_operand 0 "" ""))
4003 (pc)))]
4004 ""
4005 "{ operands[1] = alpha_emit_conditional_branch (LTU); }")
4007 (define_expand "bleu"
4008 [(set (pc)
4009 (if_then_else (match_dup 1)
4010 (label_ref (match_operand 0 "" ""))
4011 (pc)))]
4012 ""
4013 "{ operands[1] = alpha_emit_conditional_branch (LEU); }")
4015 (define_expand "bgtu"
4016 [(set (pc)
4017 (if_then_else (match_dup 1)
4018 (label_ref (match_operand 0 "" ""))
4019 (pc)))]
4020 ""
4021 "{ operands[1] = alpha_emit_conditional_branch (GTU); }")
4023 (define_expand "bgeu"
4024 [(set (pc)
4025 (if_then_else (match_dup 1)
4026 (label_ref (match_operand 0 "" ""))
4027 (pc)))]
4028 ""
4029 "{ operands[1] = alpha_emit_conditional_branch (GEU); }")
4031 (define_expand "bunordered"
4032 [(set (pc)
4033 (if_then_else (match_dup 1)
4034 (label_ref (match_operand 0 "" ""))
4035 (pc)))]
4036 ""
4037 "{ operands[1] = alpha_emit_conditional_branch (UNORDERED); }")
4039 (define_expand "bordered"
4040 [(set (pc)
4041 (if_then_else (match_dup 1)
4042 (label_ref (match_operand 0 "" ""))
4043 (pc)))]
4044 ""
4045 "{ operands[1] = alpha_emit_conditional_branch (ORDERED); }")
4047 (define_expand "seq"
4048 [(set (match_operand:DI 0 "register_operand" "")
4049 (match_dup 1))]
4050 ""
4051 "{ if ((operands[1] = alpha_emit_setcc (EQ)) == NULL_RTX) FAIL; }")
4053 (define_expand "sne"
4054 [(set (match_operand:DI 0 "register_operand" "")
4055 (match_dup 1))]
4056 ""
4057 "{ if ((operands[1] = alpha_emit_setcc (NE)) == NULL_RTX) FAIL; }")
4059 (define_expand "slt"
4060 [(set (match_operand:DI 0 "register_operand" "")
4061 (match_dup 1))]
4062 ""
4063 "{ if ((operands[1] = alpha_emit_setcc (LT)) == NULL_RTX) FAIL; }")
4065 (define_expand "sle"
4066 [(set (match_operand:DI 0 "register_operand" "")
4067 (match_dup 1))]
4068 ""
4069 "{ if ((operands[1] = alpha_emit_setcc (LE)) == NULL_RTX) FAIL; }")
4071 (define_expand "sgt"
4072 [(set (match_operand:DI 0 "register_operand" "")
4073 (match_dup 1))]
4074 ""
4075 "{ if ((operands[1] = alpha_emit_setcc (GT)) == NULL_RTX) FAIL; }")
4077 (define_expand "sge"
4078 [(set (match_operand:DI 0 "register_operand" "")
4079 (match_dup 1))]
4080 ""
4081 "{ if ((operands[1] = alpha_emit_setcc (GE)) == NULL_RTX) FAIL; }")
4083 (define_expand "sltu"
4084 [(set (match_operand:DI 0 "register_operand" "")
4085 (match_dup 1))]
4086 ""
4087 "{ if ((operands[1] = alpha_emit_setcc (LTU)) == NULL_RTX) FAIL; }")
4089 (define_expand "sleu"
4090 [(set (match_operand:DI 0 "register_operand" "")
4091 (match_dup 1))]
4092 ""
4093 "{ if ((operands[1] = alpha_emit_setcc (LEU)) == NULL_RTX) FAIL; }")
4095 (define_expand "sgtu"
4096 [(set (match_operand:DI 0 "register_operand" "")
4097 (match_dup 1))]
4098 ""
4099 "{ if ((operands[1] = alpha_emit_setcc (GTU)) == NULL_RTX) FAIL; }")
4101 (define_expand "sgeu"
4102 [(set (match_operand:DI 0 "register_operand" "")
4103 (match_dup 1))]
4104 ""
4105 "{ if ((operands[1] = alpha_emit_setcc (GEU)) == NULL_RTX) FAIL; }")
4107 (define_expand "sunordered"
4108 [(set (match_operand:DI 0 "register_operand" "")
4109 (match_dup 1))]
4110 ""
4111 "{ if ((operands[1] = alpha_emit_setcc (UNORDERED)) == NULL_RTX) FAIL; }")
4113 (define_expand "sordered"
4114 [(set (match_operand:DI 0 "register_operand" "")
4115 (match_dup 1))]
4116 ""
4117 "{ if ((operands[1] = alpha_emit_setcc (ORDERED)) == NULL_RTX) FAIL; }")
4118 \f
4119 ;; These are the main define_expand's used to make conditional moves.
4121 (define_expand "movsicc"
4122 [(set (match_operand:SI 0 "register_operand" "")
4123 (if_then_else:SI (match_operand 1 "comparison_operator" "")
4124 (match_operand:SI 2 "reg_or_8bit_operand" "")
4125 (match_operand:SI 3 "reg_or_8bit_operand" "")))]
4126 ""
4127 {
4128 if ((operands[1] = alpha_emit_conditional_move (operands[1], SImode)) == 0)
4129 FAIL;
4130 })
4132 (define_expand "movdicc"
4133 [(set (match_operand:DI 0 "register_operand" "")
4134 (if_then_else:DI (match_operand 1 "comparison_operator" "")
4135 (match_operand:DI 2 "reg_or_8bit_operand" "")
4136 (match_operand:DI 3 "reg_or_8bit_operand" "")))]
4137 ""
4138 {
4139 if ((operands[1] = alpha_emit_conditional_move (operands[1], DImode)) == 0)
4140 FAIL;
4141 })
4143 (define_expand "movsfcc"
4144 [(set (match_operand:SF 0 "register_operand" "")
4145 (if_then_else:SF (match_operand 1 "comparison_operator" "")
4146 (match_operand:SF 2 "reg_or_8bit_operand" "")
4147 (match_operand:SF 3 "reg_or_8bit_operand" "")))]
4148 ""
4149 {
4150 if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0)
4151 FAIL;
4152 })
4154 (define_expand "movdfcc"
4155 [(set (match_operand:DF 0 "register_operand" "")
4156 (if_then_else:DF (match_operand 1 "comparison_operator" "")
4157 (match_operand:DF 2 "reg_or_8bit_operand" "")
4158 (match_operand:DF 3 "reg_or_8bit_operand" "")))]
4159 ""
4160 {
4161 if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0)
4162 FAIL;
4163 })
4164 \f
4165 ;; These define_split definitions are used in cases when comparisons have
4166 ;; not be stated in the correct way and we need to reverse the second
4167 ;; comparison. For example, x >= 7 has to be done as x < 6 with the
4168 ;; comparison that tests the result being reversed. We have one define_split
4169 ;; for each use of a comparison. They do not match valid insns and need
4170 ;; not generate valid insns.
4171 ;;
4172 ;; We can also handle equality comparisons (and inequality comparisons in
4173 ;; cases where the resulting add cannot overflow) by doing an add followed by
4174 ;; a comparison with zero. This is faster since the addition takes one
4175 ;; less cycle than a compare when feeding into a conditional move.
4176 ;; For this case, we also have an SImode pattern since we can merge the add
4177 ;; and sign extend and the order doesn't matter.
4178 ;;
4179 ;; We do not do this for floating-point, since it isn't clear how the "wrong"
4180 ;; operation could have been generated.
4182 (define_split
4183 [(set (match_operand:DI 0 "register_operand" "")
4184 (if_then_else:DI
4185 (match_operator 1 "comparison_operator"
4186 [(match_operand:DI 2 "reg_or_0_operand" "")
4187 (match_operand:DI 3 "reg_or_cint_operand" "")])
4188 (match_operand:DI 4 "reg_or_cint_operand" "")
4189 (match_operand:DI 5 "reg_or_cint_operand" "")))
4190 (clobber (match_operand:DI 6 "register_operand" ""))]
4191 "operands[3] != const0_rtx"
4192 [(set (match_dup 6) (match_dup 7))
4193 (set (match_dup 0)
4194 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4195 {
4196 enum rtx_code code = GET_CODE (operands[1]);
4197 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4199 /* If we are comparing for equality with a constant and that constant
4200 appears in the arm when the register equals the constant, use the
4201 register since that is more likely to match (and to produce better code
4202 if both would). */
4204 if (code == EQ && GET_CODE (operands[3]) == CONST_INT
4205 && rtx_equal_p (operands[4], operands[3]))
4206 operands[4] = operands[2];
4208 else if (code == NE && GET_CODE (operands[3]) == CONST_INT
4209 && rtx_equal_p (operands[5], operands[3]))
4210 operands[5] = operands[2];
4212 if (code == NE || code == EQ
4213 || (extended_count (operands[2], DImode, unsignedp) >= 1
4214 && extended_count (operands[3], DImode, unsignedp) >= 1))
4215 {
4216 if (GET_CODE (operands[3]) == CONST_INT)
4217 operands[7] = gen_rtx_PLUS (DImode, operands[2],
4218 GEN_INT (- INTVAL (operands[3])));
4219 else
4220 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]);
4222 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx);
4223 }
4225 else if (code == EQ || code == LE || code == LT
4226 || code == LEU || code == LTU)
4227 {
4228 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]);
4229 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx);
4230 }
4231 else
4232 {
4233 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode,
4234 operands[2], operands[3]);
4235 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx);
4236 }
4237 })
4239 (define_split
4240 [(set (match_operand:DI 0 "register_operand" "")
4241 (if_then_else:DI
4242 (match_operator 1 "comparison_operator"
4243 [(match_operand:SI 2 "reg_or_0_operand" "")
4244 (match_operand:SI 3 "reg_or_cint_operand" "")])
4245 (match_operand:DI 4 "reg_or_8bit_operand" "")
4246 (match_operand:DI 5 "reg_or_8bit_operand" "")))
4247 (clobber (match_operand:DI 6 "register_operand" ""))]
4248 "operands[3] != const0_rtx
4249 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)"
4250 [(set (match_dup 6) (match_dup 7))
4251 (set (match_dup 0)
4252 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))]
4253 {
4254 enum rtx_code code = GET_CODE (operands[1]);
4255 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU);
4256 rtx tem;
4258 if ((code != NE && code != EQ
4259 && ! (extended_count (operands[2], DImode, unsignedp) >= 1
4260 && extended_count (operands[3], DImode, unsignedp) >= 1)))
4261 FAIL;
4263 if (GET_CODE (operands[3]) == CONST_INT)
4264 tem = gen_rtx_PLUS (SImode, operands[2],
4265 GEN_INT (- INTVAL (operands[3])));
4266 else
4267 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]);
4269 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem);
4270 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode,
4271 operands[6], const0_rtx);
4272 })
4274 ;; Prefer to use cmp and arithmetic when possible instead of a cmove.
4276 (define_split
4277 [(set (match_operand 0 "register_operand" "")
4278 (if_then_else (match_operator 1 "signed_comparison_operator"
4279 [(match_operand:DI 2 "reg_or_0_operand" "")
4280 (const_int 0)])
4281 (match_operand 3 "const_int_operand" "")
4282 (match_operand 4 "const_int_operand" "")))]
4283 ""
4284 [(const_int 0)]
4285 {
4286 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0],
4287 operands[2], operands[3], operands[4]))
4288 DONE;
4289 else
4290 FAIL;
4291 })
4293 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know.
4294 ;; Oh well, we match it in movcc, so it must be partially our fault.
4295 (define_split
4296 [(set (match_operand 0 "register_operand" "")
4297 (if_then_else (match_operator 1 "signed_comparison_operator"
4298 [(const_int 0)
4299 (match_operand:DI 2 "reg_or_0_operand" "")])
4300 (match_operand 3 "const_int_operand" "")
4301 (match_operand 4 "const_int_operand" "")))]
4302 ""
4303 [(const_int 0)]
4304 {
4305 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])),
4306 operands[0], operands[2], operands[3],
4307 operands[4]))
4308 DONE;
4309 else
4310 FAIL;
4311 })
4313 (define_insn_and_split "*cmp_sadd_di"
4314 [(set (match_operand:DI 0 "register_operand" "=r")
4315 (plus:DI (if_then_else:DI
4316 (match_operator 1 "alpha_zero_comparison_operator"
4317 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4318 (const_int 0)])
4319 (match_operand:DI 3 "const48_operand" "I")
4320 (const_int 0))
4321 (match_operand:DI 4 "sext_add_operand" "rIO")))
4322 (clobber (match_scratch:DI 5 "=r"))]
4323 ""
4324 "#"
4325 "! no_new_pseudos || reload_completed"
4326 [(set (match_dup 5)
4327 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4328 (set (match_dup 0)
4329 (plus:DI (mult:DI (match_dup 5) (match_dup 3))
4330 (match_dup 4)))]
4331 {
4332 if (! no_new_pseudos)
4333 operands[5] = gen_reg_rtx (DImode);
4334 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4335 operands[5] = operands[0];
4336 })
4338 (define_insn_and_split "*cmp_sadd_si"
4339 [(set (match_operand:SI 0 "register_operand" "=r")
4340 (plus:SI (if_then_else:SI
4341 (match_operator 1 "alpha_zero_comparison_operator"
4342 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4343 (const_int 0)])
4344 (match_operand:SI 3 "const48_operand" "I")
4345 (const_int 0))
4346 (match_operand:SI 4 "sext_add_operand" "rIO")))
4347 (clobber (match_scratch:SI 5 "=r"))]
4348 ""
4349 "#"
4350 "! no_new_pseudos || reload_completed"
4351 [(set (match_dup 5)
4352 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4353 (set (match_dup 0)
4354 (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4355 (match_dup 4)))]
4356 {
4357 if (! no_new_pseudos)
4358 operands[5] = gen_reg_rtx (DImode);
4359 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4360 operands[5] = operands[0];
4361 })
4363 (define_insn_and_split "*cmp_sadd_sidi"
4364 [(set (match_operand:DI 0 "register_operand" "=r")
4365 (sign_extend:DI
4366 (plus:SI (if_then_else:SI
4367 (match_operator 1 "alpha_zero_comparison_operator"
4368 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4369 (const_int 0)])
4370 (match_operand:SI 3 "const48_operand" "I")
4371 (const_int 0))
4372 (match_operand:SI 4 "sext_add_operand" "rIO"))))
4373 (clobber (match_scratch:SI 5 "=r"))]
4374 ""
4375 "#"
4376 "! no_new_pseudos || reload_completed"
4377 [(set (match_dup 5)
4378 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4379 (set (match_dup 0)
4380 (sign_extend:DI (plus:SI (mult:SI (match_dup 5) (match_dup 3))
4381 (match_dup 4))))]
4382 {
4383 if (! no_new_pseudos)
4384 operands[5] = gen_reg_rtx (DImode);
4385 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4386 operands[5] = operands[0];
4387 })
4389 (define_insn_and_split "*cmp_ssub_di"
4390 [(set (match_operand:DI 0 "register_operand" "=r")
4391 (minus:DI (if_then_else:DI
4392 (match_operator 1 "alpha_zero_comparison_operator"
4393 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4394 (const_int 0)])
4395 (match_operand:DI 3 "const48_operand" "I")
4396 (const_int 0))
4397 (match_operand:DI 4 "reg_or_8bit_operand" "rI")))
4398 (clobber (match_scratch:DI 5 "=r"))]
4399 ""
4400 "#"
4401 "! no_new_pseudos || reload_completed"
4402 [(set (match_dup 5)
4403 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)]))
4404 (set (match_dup 0)
4405 (minus:DI (mult:DI (match_dup 5) (match_dup 3))
4406 (match_dup 4)))]
4407 {
4408 if (! no_new_pseudos)
4409 operands[5] = gen_reg_rtx (DImode);
4410 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4411 operands[5] = operands[0];
4412 })
4414 (define_insn_and_split "*cmp_ssub_si"
4415 [(set (match_operand:SI 0 "register_operand" "=r")
4416 (minus:SI (if_then_else:SI
4417 (match_operator 1 "alpha_zero_comparison_operator"
4418 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4419 (const_int 0)])
4420 (match_operand:SI 3 "const48_operand" "I")
4421 (const_int 0))
4422 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))
4423 (clobber (match_scratch:SI 5 "=r"))]
4424 ""
4425 "#"
4426 "! no_new_pseudos || reload_completed"
4427 [(set (match_dup 5)
4428 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4429 (set (match_dup 0)
4430 (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4431 (match_dup 4)))]
4432 {
4433 if (! no_new_pseudos)
4434 operands[5] = gen_reg_rtx (DImode);
4435 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4436 operands[5] = operands[0];
4437 })
4439 (define_insn_and_split "*cmp_ssub_sidi"
4440 [(set (match_operand:DI 0 "register_operand" "=r")
4441 (sign_extend:DI
4442 (minus:SI (if_then_else:SI
4443 (match_operator 1 "alpha_zero_comparison_operator"
4444 [(match_operand:DI 2 "reg_or_0_operand" "rJ")
4445 (const_int 0)])
4446 (match_operand:SI 3 "const48_operand" "I")
4447 (const_int 0))
4448 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))))
4449 (clobber (match_scratch:SI 5 "=r"))]
4450 ""
4451 "#"
4452 "! no_new_pseudos || reload_completed"
4453 [(set (match_dup 5)
4454 (match_op_dup:SI 1 [(match_dup 2) (const_int 0)]))
4455 (set (match_dup 0)
4456 (sign_extend:DI (minus:SI (mult:SI (match_dup 5) (match_dup 3))
4457 (match_dup 4))))]
4458 {
4459 if (! no_new_pseudos)
4460 operands[5] = gen_reg_rtx (DImode);
4461 else if (reg_overlap_mentioned_p (operands[5], operands[4]))
4462 operands[5] = operands[0];
4463 })
4464 \f
4465 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF
4466 ;; work differently, so we have different patterns for each.
4468 ;; On Unicos/Mk a call information word (CIW) must be generated for each
4469 ;; call. The CIW contains information about arguments passed in registers
4470 ;; and is stored in the caller's SSIB. Its offset relative to the beginning
4471 ;; of the SSIB is passed in $25. Handling this properly is quite complicated
4472 ;; in the presence of inlining since the CIWs for calls performed by the
4473 ;; inlined function must be stored in the SSIB of the function it is inlined
4474 ;; into as well. We encode the CIW in an unspec and append it to the list
4475 ;; of the CIWs for the current function only when the instruction for loading
4476 ;; $25 is generated.
4478 (define_expand "call"
4479 [(use (match_operand:DI 0 "" ""))
4480 (use (match_operand 1 "" ""))
4481 (use (match_operand 2 "" ""))
4482 (use (match_operand 3 "" ""))]
4483 ""
4484 {
4485 if (TARGET_ABI_WINDOWS_NT)
4486 emit_call_insn (gen_call_nt (operands[0], operands[1]));
4487 else if (TARGET_ABI_OPEN_VMS)
4488 emit_call_insn (gen_call_vms (operands[0], operands[2]));
4489 else if (TARGET_ABI_UNICOSMK)
4490 emit_call_insn (gen_call_umk (operands[0], operands[2]));
4491 else
4492 emit_call_insn (gen_call_osf (operands[0], operands[1]));
4493 DONE;
4494 })
4496 (define_expand "sibcall"
4497 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4498 (match_operand 1 "" ""))
4499 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4500 "TARGET_ABI_OSF"
4501 {
4502 gcc_assert (GET_CODE (operands[0]) == MEM);
4503 operands[0] = XEXP (operands[0], 0);
4504 })
4506 (define_expand "call_osf"
4507 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4508 (match_operand 1 "" ""))
4509 (use (reg:DI 29))
4510 (clobber (reg:DI 26))])]
4511 ""
4512 {
4513 gcc_assert (GET_CODE (operands[0]) == MEM);
4515 operands[0] = XEXP (operands[0], 0);
4516 if (! call_operand (operands[0], Pmode))
4517 operands[0] = copy_to_mode_reg (Pmode, operands[0]);
4518 })
4520 (define_expand "call_nt"
4521 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4522 (match_operand 1 "" ""))
4523 (clobber (reg:DI 26))])]
4524 ""
4525 {
4526 gcc_assert (GET_CODE (operands[0]) == MEM);
4528 operands[0] = XEXP (operands[0], 0);
4529 if (GET_CODE (operands[0]) != SYMBOL_REF && GET_CODE (operands[0]) != REG)
4530 operands[0] = force_reg (DImode, operands[0]);
4531 })
4533 ;; Calls on Unicos/Mk are always indirect.
4534 ;; op 0: symbol ref for called function
4535 ;; op 1: CIW for $25 represented by an unspec
4537 (define_expand "call_umk"
4538 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4539 (match_operand 1 "" ""))
4540 (use (reg:DI 25))
4541 (clobber (reg:DI 26))])]
4542 ""
4543 {
4544 gcc_assert (GET_CODE (operands[0]) == MEM);
4546 /* Always load the address of the called function into a register;
4547 load the CIW in $25. */
4549 operands[0] = XEXP (operands[0], 0);
4550 if (GET_CODE (operands[0]) != REG)
4551 operands[0] = force_reg (DImode, operands[0]);
4553 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4554 })
4556 ;;
4557 ;; call openvms/alpha
4558 ;; op 0: symbol ref for called function
4559 ;; op 1: next_arg_reg (argument information value for R25)
4560 ;;
4561 (define_expand "call_vms"
4562 [(parallel [(call (mem:DI (match_operand 0 "" ""))
4563 (match_operand 1 "" ""))
4564 (use (match_dup 2))
4565 (use (reg:DI 25))
4566 (use (reg:DI 26))
4567 (clobber (reg:DI 27))])]
4568 ""
4569 {
4570 gcc_assert (GET_CODE (operands[0]) == MEM);
4572 operands[0] = XEXP (operands[0], 0);
4574 /* Always load AI with argument information, then handle symbolic and
4575 indirect call differently. Load RA and set operands[2] to PV in
4576 both cases. */
4578 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
4579 if (GET_CODE (operands[0]) == SYMBOL_REF)
4580 {
4581 alpha_need_linkage (XSTR (operands[0], 0), 0);
4583 operands[2] = const0_rtx;
4584 }
4585 else
4586 {
4587 emit_move_insn (gen_rtx_REG (Pmode, 26),
4588 gen_rtx_MEM (Pmode, plus_constant (operands[0], 8)));
4589 operands[2] = operands[0];
4590 }
4592 })
4594 (define_expand "call_value"
4595 [(use (match_operand 0 "" ""))
4596 (use (match_operand:DI 1 "" ""))
4597 (use (match_operand 2 "" ""))
4598 (use (match_operand 3 "" ""))
4599 (use (match_operand 4 "" ""))]
4600 ""
4601 {
4602 if (TARGET_ABI_WINDOWS_NT)
4603 emit_call_insn (gen_call_value_nt (operands[0], operands[1], operands[2]));
4604 else if (TARGET_ABI_OPEN_VMS)
4605 emit_call_insn (gen_call_value_vms (operands[0], operands[1],
4606 operands[3]));
4607 else if (TARGET_ABI_UNICOSMK)
4608 emit_call_insn (gen_call_value_umk (operands[0], operands[1],
4609 operands[3]));
4610 else
4611 emit_call_insn (gen_call_value_osf (operands[0], operands[1],
4612 operands[2]));
4613 DONE;
4614 })
4616 (define_expand "sibcall_value"
4617 [(parallel [(set (match_operand 0 "" "")
4618 (call (mem:DI (match_operand 1 "" ""))
4619 (match_operand 2 "" "")))
4620 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])]
4621 "TARGET_ABI_OSF"
4622 {
4623 gcc_assert (GET_CODE (operands[1]) == MEM);
4624 operands[1] = XEXP (operands[1], 0);
4625 })
4627 (define_expand "call_value_osf"
4628 [(parallel [(set (match_operand 0 "" "")
4629 (call (mem:DI (match_operand 1 "" ""))
4630 (match_operand 2 "" "")))
4631 (use (reg:DI 29))
4632 (clobber (reg:DI 26))])]
4633 ""
4634 {
4635 gcc_assert (GET_CODE (operands[1]) == MEM);
4637 operands[1] = XEXP (operands[1], 0);
4638 if (! call_operand (operands[1], Pmode))
4639 operands[1] = copy_to_mode_reg (Pmode, operands[1]);
4640 })
4642 (define_expand "call_value_nt"
4643 [(parallel [(set (match_operand 0 "" "")
4644 (call (mem:DI (match_operand 1 "" ""))
4645 (match_operand 2 "" "")))
4646 (clobber (reg:DI 26))])]
4647 ""
4648 {
4649 gcc_assert (GET_CODE (operands[1]) == MEM);
4651 operands[1] = XEXP (operands[1], 0);
4652 if (GET_CODE (operands[1]) != SYMBOL_REF && GET_CODE (operands[1]) != REG)
4653 operands[1] = force_reg (DImode, operands[1]);
4654 })
4656 (define_expand "call_value_vms"
4657 [(parallel [(set (match_operand 0 "" "")
4658 (call (mem:DI (match_operand:DI 1 "" ""))
4659 (match_operand 2 "" "")))
4660 (use (match_dup 3))
4661 (use (reg:DI 25))
4662 (use (reg:DI 26))
4663 (clobber (reg:DI 27))])]
4664 ""
4665 {
4666 gcc_assert (GET_CODE (operands[1]) == MEM);
4668 operands[1] = XEXP (operands[1], 0);
4670 /* Always load AI with argument information, then handle symbolic and
4671 indirect call differently. Load RA and set operands[3] to PV in
4672 both cases. */
4674 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4675 if (GET_CODE (operands[1]) == SYMBOL_REF)
4676 {
4677 alpha_need_linkage (XSTR (operands[1], 0), 0);
4679 operands[3] = const0_rtx;
4680 }
4681 else
4682 {
4683 emit_move_insn (gen_rtx_REG (Pmode, 26),
4684 gen_rtx_MEM (Pmode, plus_constant (operands[1], 8)));
4685 operands[3] = operands[1];
4686 }
4687 })
4689 (define_expand "call_value_umk"
4690 [(parallel [(set (match_operand 0 "" "")
4691 (call (mem:DI (match_operand 1 "" ""))
4692 (match_operand 2 "" "")))
4693 (use (reg:DI 25))
4694 (clobber (reg:DI 26))])]
4695 ""
4696 {
4697 gcc_assert (GET_CODE (operands[1]) == MEM);
4699 operands[1] = XEXP (operands[1], 0);
4700 if (GET_CODE (operands[1]) != REG)
4701 operands[1] = force_reg (DImode, operands[1]);
4703 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
4704 })
4706 (define_insn "*call_osf_1_er"
4707 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4708 (match_operand 1 "" ""))
4709 (use (reg:DI 29))
4710 (clobber (reg:DI 26))]
4711 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4712 "@
4713 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
4714 bsr $26,%0\t\t!samegp
4715 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
4716 [(set_attr "type" "jsr")
4717 (set_attr "length" "12,*,16")])
4719 ;; We must use peep2 instead of a split because we need accurate life
4720 ;; information for $gp. Consider the case of { bar(); while (1); }.
4721 (define_peephole2
4722 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4723 (match_operand 1 "" ""))
4724 (use (reg:DI 29))
4725 (clobber (reg:DI 26))])]
4726 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4727 && ! samegp_function_operand (operands[0], Pmode)
4728 && (peep2_regno_dead_p (1, 29)
4729 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
4730 [(parallel [(call (mem:DI (match_dup 2))
4731 (match_dup 1))
4732 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4733 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4734 (use (match_dup 0))
4735 (use (match_dup 3))])]
4736 {
4737 if (CONSTANT_P (operands[0]))
4738 {
4739 operands[2] = gen_rtx_REG (Pmode, 27);
4740 operands[3] = GEN_INT (alpha_next_sequence_number++);
4741 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4742 operands[0], operands[3]));
4743 }
4744 else
4745 {
4746 operands[2] = operands[0];
4747 operands[0] = const0_rtx;
4748 operands[3] = const0_rtx;
4749 }
4750 })
4752 (define_peephole2
4753 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand" ""))
4754 (match_operand 1 "" ""))
4755 (use (reg:DI 29))
4756 (clobber (reg:DI 26))])]
4757 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
4758 && ! samegp_function_operand (operands[0], Pmode)
4759 && ! (peep2_regno_dead_p (1, 29)
4760 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
4761 [(parallel [(call (mem:DI (match_dup 2))
4762 (match_dup 1))
4763 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4764 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4765 (use (match_dup 0))
4766 (use (match_dup 4))])
4767 (set (reg:DI 29)
4768 (unspec_volatile:DI [(reg:DI 26) (match_dup 3)] UNSPECV_LDGP1))
4769 (set (reg:DI 29)
4770 (unspec:DI [(reg:DI 29) (match_dup 3)] UNSPEC_LDGP2))]
4771 {
4772 if (CONSTANT_P (operands[0]))
4773 {
4774 operands[2] = gen_rtx_REG (Pmode, 27);
4775 operands[4] = GEN_INT (alpha_next_sequence_number++);
4776 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx,
4777 operands[0], operands[4]));
4778 }
4779 else
4780 {
4781 operands[2] = operands[0];
4782 operands[0] = const0_rtx;
4783 operands[4] = const0_rtx;
4784 }
4785 operands[3] = GEN_INT (alpha_next_sequence_number++);
4786 })
4788 ;; We add a blockage unspec_volatile to prevent insns from moving down
4789 ;; from above the call to in between the call and the ldah gpdisp.
4791 (define_insn "*call_osf_2_er"
4792 [(call (mem:DI (match_operand:DI 0 "register_operand" "c"))
4793 (match_operand 1 "" ""))
4794 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
4795 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
4796 (use (match_operand 2 "" ""))
4797 (use (match_operand 3 "const_int_operand" ""))]
4798 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4799 "jsr $26,(%0),%2%J3"
4800 [(set_attr "type" "jsr")
4801 (set_attr "cannot_copy" "true")])
4803 ;; We output a nop after noreturn calls at the very end of the function to
4804 ;; ensure that the return address always remains in the caller's code range,
4805 ;; as not doing so might confuse unwinding engines.
4806 ;;
4807 ;; The potential change in insn length is not reflected in the length
4808 ;; attributes at this stage. Since the extra space is only actually added at
4809 ;; the very end of the compilation process (via final/print_operand), it
4810 ;; really seems harmless and not worth the trouble of some extra computation
4811 ;; cost and complexity.
4813 (define_insn "*call_osf_1_noreturn"
4814 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4815 (match_operand 1 "" ""))
4816 (use (reg:DI 29))
4817 (clobber (reg:DI 26))]
4818 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
4819 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
4820 "@
4821 jsr $26,($27),0%+
4822 bsr $26,$%0..ng%+
4823 jsr $26,%0%+"
4824 [(set_attr "type" "jsr")
4825 (set_attr "length" "*,*,8")])
4827 (define_insn "*call_osf_1"
4828 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s"))
4829 (match_operand 1 "" ""))
4830 (use (reg:DI 29))
4831 (clobber (reg:DI 26))]
4832 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4833 "@
4834 jsr $26,($27),0\;ldgp $29,0($26)
4835 bsr $26,$%0..ng
4836 jsr $26,%0\;ldgp $29,0($26)"
4837 [(set_attr "type" "jsr")
4838 (set_attr "length" "12,*,16")])
4840 ;; Note that the DEC assembler expands "jmp foo" with $at, which
4841 ;; doesn't do what we want.
4842 (define_insn "*sibcall_osf_1_er"
4843 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4844 (match_operand 1 "" ""))
4845 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4846 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4847 "@
4848 br $31,%0\t\t!samegp
4849 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#"
4850 [(set_attr "type" "jsr")
4851 (set_attr "length" "*,8")])
4853 (define_insn "*sibcall_osf_1"
4854 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s"))
4855 (match_operand 1 "" ""))
4856 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
4857 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
4858 "@
4859 br $31,$%0..ng
4860 lda $27,%0\;jmp $31,($27),%0"
4861 [(set_attr "type" "jsr")
4862 (set_attr "length" "*,8")])
4864 (define_insn "*call_nt_1"
4865 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,R,s"))
4866 (match_operand 1 "" ""))
4867 (clobber (reg:DI 26))]
4868 "TARGET_ABI_WINDOWS_NT"
4869 "@
4870 jsr $26,(%0)
4871 bsr $26,%0
4872 jsr $26,%0"
4873 [(set_attr "type" "jsr")
4874 (set_attr "length" "*,*,12")])
4876 ; GAS relies on the order and position of instructions output below in order
4877 ; to generate relocs for VMS link to potentially optimize the call.
4878 ; Please do not molest.
4879 (define_insn "*call_vms_1"
4880 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s"))
4881 (match_operand 1 "" ""))
4882 (use (match_operand:DI 2 "nonmemory_operand" "r,n"))
4883 (use (reg:DI 25))
4884 (use (reg:DI 26))
4885 (clobber (reg:DI 27))]
4886 "TARGET_ABI_OPEN_VMS"
4887 {
4888 switch (which_alternative)
4889 {
4890 case 0:
4891 return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)";
4892 case 1:
4893 operands [2] = alpha_use_linkage (operands [0], cfun->decl, 1, 0);
4894 operands [3] = alpha_use_linkage (operands [0], cfun->decl, 0, 0);
4895 return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)";
4896 default:
4897 gcc_unreachable ();
4898 }
4899 }
4900 [(set_attr "type" "jsr")
4901 (set_attr "length" "12,16")])
4903 (define_insn "*call_umk_1"
4904 [(call (mem:DI (match_operand:DI 0 "call_operand" "r"))
4905 (match_operand 1 "" ""))
4906 (use (reg:DI 25))
4907 (clobber (reg:DI 26))]
4908 "TARGET_ABI_UNICOSMK"
4909 "jsr $26,(%0)"
4910 [(set_attr "type" "jsr")])
4912 ;; Call subroutine returning any type.
4914 (define_expand "untyped_call"
4915 [(parallel [(call (match_operand 0 "" "")
4916 (const_int 0))
4917 (match_operand 1 "" "")
4918 (match_operand 2 "" "")])]
4919 ""
4920 {
4921 int i;
4923 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
4925 for (i = 0; i < XVECLEN (operands[2], 0); i++)
4926 {
4927 rtx set = XVECEXP (operands[2], 0, i);
4928 emit_move_insn (SET_DEST (set), SET_SRC (set));
4929 }
4931 /* The optimizer does not know that the call sets the function value
4932 registers we stored in the result block. We avoid problems by
4933 claiming that all hard registers are used and clobbered at this
4934 point. */
4935 emit_insn (gen_blockage ());
4937 DONE;
4938 })
4940 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
4941 ;; all of memory. This blocks insns from being moved across this point.
4943 (define_insn "blockage"
4944 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
4945 ""
4946 ""
4947 [(set_attr "length" "0")
4948 (set_attr "type" "none")])
4950 (define_insn "jump"
4951 [(set (pc)
4952 (label_ref (match_operand 0 "" "")))]
4953 ""
4954 "br $31,%l0"
4955 [(set_attr "type" "ibr")])
4957 (define_expand "return"
4958 [(return)]
4959 "direct_return ()"
4960 "")
4962 (define_insn "*return_internal"
4963 [(return)]
4964 "reload_completed"
4965 "ret $31,($26),1"
4966 [(set_attr "type" "ibr")])
4968 (define_insn "indirect_jump"
4969 [(set (pc) (match_operand:DI 0 "register_operand" "r"))]
4970 ""
4971 "jmp $31,(%0),0"
4972 [(set_attr "type" "ibr")])
4974 (define_expand "tablejump"
4975 [(parallel [(set (pc)
4976 (match_operand 0 "register_operand" ""))
4977 (use (label_ref:DI (match_operand 1 "" "")))])]
4978 ""
4979 {
4980 if (TARGET_ABI_WINDOWS_NT)
4981 {
4982 rtx dest = gen_reg_rtx (DImode);
4983 emit_insn (gen_extendsidi2 (dest, operands[0]));
4984 operands[0] = dest;
4985 }
4986 else if (TARGET_ABI_OSF)
4987 {
4988 rtx dest = gen_reg_rtx (DImode);
4989 emit_insn (gen_extendsidi2 (dest, operands[0]));
4990 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest));
4991 operands[0] = dest;
4992 }
4993 })
4995 (define_insn "*tablejump_osf_nt_internal"
4996 [(set (pc)
4997 (match_operand:DI 0 "register_operand" "r"))
4998 (use (label_ref:DI (match_operand 1 "" "")))]
4999 "(TARGET_ABI_OSF || TARGET_ABI_WINDOWS_NT)
5000 && alpha_tablejump_addr_vec (insn)"
5001 {
5002 operands[2] = alpha_tablejump_best_label (insn);
5003 return "jmp $31,(%0),%2";
5004 }
5005 [(set_attr "type" "ibr")])
5007 (define_insn "*tablejump_internal"
5008 [(set (pc)
5009 (match_operand:DI 0 "register_operand" "r"))
5010 (use (label_ref (match_operand 1 "" "")))]
5011 ""
5012 "jmp $31,(%0),0"
5013 [(set_attr "type" "ibr")])
5015 ;; Cache flush. Used by INITIALIZE_TRAMPOLINE. 0x86 is PAL_imb, but we don't
5016 ;; want to have to include pal.h in our .s file.
5017 ;;
5018 ;; Technically the type for call_pal is jsr, but we use that for determining
5019 ;; if we need a GP. Use ibr instead since it has the same EV5 scheduling
5020 ;; characteristics.
5021 (define_insn "imb"
5022 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)]
5023 ""
5024 "call_pal 0x86"
5025 [(set_attr "type" "callpal")])
5027 ;; BUGCHK is documented common to OSF/1 and VMS PALcode.
5028 ;; NT does not document anything at 0x81 -- presumably it would generate
5029 ;; the equivalent of SIGILL, but this isn't that important.
5030 ;; ??? Presuming unicosmk uses either OSF/1 or VMS PALcode.
5031 (define_insn "trap"
5032 [(trap_if (const_int 1) (const_int 0))]
5033 "!TARGET_ABI_WINDOWS_NT"
5034 "call_pal 0x81"
5035 [(set_attr "type" "callpal")])
5037 ;; For userland, we load the thread pointer from the TCB.
5038 ;; For the kernel, we load the per-cpu private value.
5040 (define_insn "load_tp"
5041 [(set (match_operand:DI 0 "register_operand" "=v")
5042 (unspec:DI [(const_int 0)] UNSPEC_TP))]
5043 "TARGET_ABI_OSF"
5044 {
5045 if (TARGET_TLS_KERNEL)
5046 return "call_pal 0x32";
5047 else
5048 return "call_pal 0x9e";
5049 }
5050 [(set_attr "type" "callpal")])
5052 ;; For completeness, and possibly a __builtin function, here's how to
5053 ;; set the thread pointer. Since we don't describe enough of this
5054 ;; quantity for CSE, we have to use a volatile unspec, and then there's
5055 ;; not much point in creating an R16_REG register class.
5057 (define_expand "set_tp"
5058 [(set (reg:DI 16) (match_operand:DI 0 "input_operand" ""))
5059 (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
5060 "TARGET_ABI_OSF"
5061 "")
5063 (define_insn "*set_tp"
5064 [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)]
5065 "TARGET_ABI_OSF"
5066 {
5067 if (TARGET_TLS_KERNEL)
5068 return "call_pal 0x31";
5069 else
5070 return "call_pal 0x9f";
5071 }
5072 [(set_attr "type" "callpal")])
5073 \f
5074 ;; Finally, we have the basic data motion insns. The byte and word insns
5075 ;; are done via define_expand. Start with the floating-point insns, since
5076 ;; they are simpler.
5078 (define_insn "*movsf_nofix"
5079 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5080 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5081 "TARGET_FPREGS && ! TARGET_FIX
5082 && (register_operand (operands[0], SFmode)
5083 || reg_or_0_operand (operands[1], SFmode))"
5084 "@
5085 cpys %R1,%R1,%0
5086 ld%, %0,%1
5087 bis $31,%r1,%0
5088 ldl %0,%1
5089 st%, %R1,%0
5090 stl %r1,%0"
5091 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5093 (define_insn "*movsf_fix"
5094 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5095 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5096 "TARGET_FPREGS && TARGET_FIX
5097 && (register_operand (operands[0], SFmode)
5098 || reg_or_0_operand (operands[1], SFmode))"
5099 "@
5100 cpys %R1,%R1,%0
5101 ld%, %0,%1
5102 bis $31,%r1,%0
5103 ldl %0,%1
5104 st%, %R1,%0
5105 stl %r1,%0
5106 itofs %1,%0
5107 ftois %1,%0"
5108 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5110 (define_insn "*movsf_nofp"
5111 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
5112 (match_operand:SF 1 "input_operand" "rG,m,r"))]
5113 "! TARGET_FPREGS
5114 && (register_operand (operands[0], SFmode)
5115 || reg_or_0_operand (operands[1], SFmode))"
5116 "@
5117 bis $31,%r1,%0
5118 ldl %0,%1
5119 stl %r1,%0"
5120 [(set_attr "type" "ilog,ild,ist")])
5122 (define_insn "*movdf_nofix"
5123 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m")
5124 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))]
5125 "TARGET_FPREGS && ! TARGET_FIX
5126 && (register_operand (operands[0], DFmode)
5127 || reg_or_0_operand (operands[1], DFmode))"
5128 "@
5129 cpys %R1,%R1,%0
5130 ld%- %0,%1
5131 bis $31,%r1,%0
5132 ldq %0,%1
5133 st%- %R1,%0
5134 stq %r1,%0"
5135 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist")])
5137 (define_insn "*movdf_fix"
5138 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r")
5139 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))]
5140 "TARGET_FPREGS && TARGET_FIX
5141 && (register_operand (operands[0], DFmode)
5142 || reg_or_0_operand (operands[1], DFmode))"
5143 "@
5144 cpys %R1,%R1,%0
5145 ld%- %0,%1
5146 bis $31,%r1,%0
5147 ldq %0,%1
5148 st%- %R1,%0
5149 stq %r1,%0
5150 itoft %1,%0
5151 ftoit %1,%0"
5152 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi")])
5154 (define_insn "*movdf_nofp"
5155 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
5156 (match_operand:DF 1 "input_operand" "rG,m,r"))]
5157 "! TARGET_FPREGS
5158 && (register_operand (operands[0], DFmode)
5159 || reg_or_0_operand (operands[1], DFmode))"
5160 "@
5161 bis $31,%r1,%0
5162 ldq %0,%1
5163 stq %r1,%0"
5164 [(set_attr "type" "ilog,ild,ist")])
5166 ;; Subregs suck for register allocation. Pretend we can move TFmode
5167 ;; data between general registers until after reload.
5169 (define_insn_and_split "*movtf_internal"
5170 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o")
5171 (match_operand:TF 1 "input_operand" "roG,rG"))]
5172 "register_operand (operands[0], TFmode)
5173 || reg_or_0_operand (operands[1], TFmode)"
5174 "#"
5175 "reload_completed"
5176 [(set (match_dup 0) (match_dup 2))
5177 (set (match_dup 1) (match_dup 3))]
5178 {
5179 alpha_split_tfmode_pair (operands);
5180 if (reg_overlap_mentioned_p (operands[0], operands[3]))
5181 {
5182 rtx tmp;
5183 tmp = operands[0], operands[0] = operands[1], operands[1] = tmp;
5184 tmp = operands[2], operands[2] = operands[3], operands[3] = tmp;
5185 }
5186 })
5188 (define_expand "movsf"
5189 [(set (match_operand:SF 0 "nonimmediate_operand" "")
5190 (match_operand:SF 1 "general_operand" ""))]
5191 ""
5192 {
5193 if (GET_CODE (operands[0]) == MEM
5194 && ! reg_or_0_operand (operands[1], SFmode))
5195 operands[1] = force_reg (SFmode, operands[1]);
5196 })
5198 (define_expand "movdf"
5199 [(set (match_operand:DF 0 "nonimmediate_operand" "")
5200 (match_operand:DF 1 "general_operand" ""))]
5201 ""
5202 {
5203 if (GET_CODE (operands[0]) == MEM
5204 && ! reg_or_0_operand (operands[1], DFmode))
5205 operands[1] = force_reg (DFmode, operands[1]);
5206 })
5208 (define_expand "movtf"
5209 [(set (match_operand:TF 0 "nonimmediate_operand" "")
5210 (match_operand:TF 1 "general_operand" ""))]
5211 ""
5212 {
5213 if (GET_CODE (operands[0]) == MEM
5214 && ! reg_or_0_operand (operands[1], TFmode))
5215 operands[1] = force_reg (TFmode, operands[1]);
5216 })
5218 (define_insn "*movsi"
5219 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m")
5220 (match_operand:SI 1 "input_operand" "rJ,K,L,n,m,rJ"))]
5221 "(TARGET_ABI_OSF || TARGET_ABI_UNICOSMK)
5222 && (register_operand (operands[0], SImode)
5223 || reg_or_0_operand (operands[1], SImode))"
5224 "@
5225 bis $31,%r1,%0
5226 lda %0,%1($31)
5227 ldah %0,%h1($31)
5228 #
5229 ldl %0,%1
5230 stl %r1,%0"
5231 [(set_attr "type" "ilog,iadd,iadd,multi,ild,ist")])
5233 (define_insn "*movsi_nt_vms"
5234 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m")
5235 (match_operand:SI 1 "input_operand" "rJ,K,L,s,n,m,rJ"))]
5236 "(TARGET_ABI_WINDOWS_NT || TARGET_ABI_OPEN_VMS)
5237 && (register_operand (operands[0], SImode)
5238 || reg_or_0_operand (operands[1], SImode))"
5239 "@
5240 bis $31,%1,%0
5241 lda %0,%1
5242 ldah %0,%h1
5243 lda %0,%1
5244 #
5245 ldl %0,%1
5246 stl %r1,%0"
5247 [(set_attr "type" "ilog,iadd,iadd,ldsym,multi,ild,ist")])
5249 (define_insn "*movhi_nobwx"
5250 [(set (match_operand:HI 0 "register_operand" "=r,r")
5251 (match_operand:HI 1 "input_operand" "rJ,n"))]
5252 "! TARGET_BWX
5253 && (register_operand (operands[0], HImode)
5254 || register_operand (operands[1], HImode))"
5255 "@
5256 bis $31,%r1,%0
5257 lda %0,%L1($31)"
5258 [(set_attr "type" "ilog,iadd")])
5260 (define_insn "*movhi_bwx"
5261 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
5262 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))]
5263 "TARGET_BWX
5264 && (register_operand (operands[0], HImode)
5265 || reg_or_0_operand (operands[1], HImode))"
5266 "@
5267 bis $31,%r1,%0
5268 lda %0,%L1($31)
5269 ldwu %0,%1
5270 stw %r1,%0"
5271 [(set_attr "type" "ilog,iadd,ild,ist")])
5273 (define_insn "*movqi_nobwx"
5274 [(set (match_operand:QI 0 "register_operand" "=r,r")
5275 (match_operand:QI 1 "input_operand" "rJ,n"))]
5276 "! TARGET_BWX
5277 && (register_operand (operands[0], QImode)
5278 || register_operand (operands[1], QImode))"
5279 "@
5280 bis $31,%r1,%0
5281 lda %0,%L1($31)"
5282 [(set_attr "type" "ilog,iadd")])
5284 (define_insn "*movqi_bwx"
5285 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m")
5286 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))]
5287 "TARGET_BWX
5288 && (register_operand (operands[0], QImode)
5289 || reg_or_0_operand (operands[1], QImode))"
5290 "@
5291 bis $31,%r1,%0
5292 lda %0,%L1($31)
5293 ldbu %0,%1
5294 stb %r1,%0"
5295 [(set_attr "type" "ilog,iadd,ild,ist")])
5297 ;; We do two major things here: handle mem->mem and construct long
5298 ;; constants.
5300 (define_expand "movsi"
5301 [(set (match_operand:SI 0 "nonimmediate_operand" "")
5302 (match_operand:SI 1 "general_operand" ""))]
5303 ""
5304 {
5305 if (alpha_expand_mov (SImode, operands))
5306 DONE;
5307 })
5309 ;; Split a load of a large constant into the appropriate two-insn
5310 ;; sequence.
5312 (define_split
5313 [(set (match_operand:SI 0 "register_operand" "")
5314 (match_operand:SI 1 "non_add_const_operand" ""))]
5315 ""
5316 [(const_int 0)]
5317 {
5318 if (alpha_split_const_mov (SImode, operands))
5319 DONE;
5320 else
5321 FAIL;
5322 })
5324 ;; Split the load of an address into a four-insn sequence on Unicos/Mk.
5325 ;; Always generate a REG_EQUAL note for the last instruction to facilitate
5326 ;; optimizations. If the symbolic operand is a label_ref, generate REG_LABEL
5327 ;; notes and update LABEL_NUSES because this is not done automatically.
5328 ;; Labels may be incorrectly deleted if we don't do this.
5329 ;;
5330 ;; Describing what the individual instructions do correctly is too complicated
5331 ;; so use UNSPECs for each of the three parts of an address.
5333 (define_split
5334 [(set (match_operand:DI 0 "register_operand" "")
5335 (match_operand:DI 1 "symbolic_operand" ""))]
5336 "TARGET_ABI_UNICOSMK && reload_completed"
5337 [(const_int 0)]
5338 {
5339 rtx insn1, insn2, insn3;
5341 insn1 = emit_insn (gen_umk_laum (operands[0], operands[1]));
5342 emit_insn (gen_ashldi3 (operands[0], operands[0], GEN_INT (32)));
5343 insn2 = emit_insn (gen_umk_lalm (operands[0], operands[0], operands[1]));
5344 insn3 = emit_insn (gen_umk_lal (operands[0], operands[0], operands[1]));
5345 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_EQUAL, operands[1],
5346 REG_NOTES (insn3));
5347 if (GET_CODE (operands[1]) == LABEL_REF)
5348 {
5349 rtx label;
5351 label = XEXP (operands[1], 0);
5352 REG_NOTES (insn1) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5353 REG_NOTES (insn1));
5354 REG_NOTES (insn2) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5355 REG_NOTES (insn2));
5356 REG_NOTES (insn3) = gen_rtx_EXPR_LIST (REG_LABEL, label,
5357 REG_NOTES (insn3));
5358 LABEL_NUSES (label) += 3;
5359 }
5360 DONE;
5361 })
5363 ;; Instructions for loading the three parts of an address on Unicos/Mk.
5365 (define_insn "umk_laum"
5366 [(set (match_operand:DI 0 "register_operand" "=r")
5367 (unspec:DI [(match_operand:DI 1 "symbolic_operand" "")]
5368 UNSPEC_UMK_LAUM))]
5369 "TARGET_ABI_UNICOSMK"
5370 "laum %r0,%t1($31)"
5371 [(set_attr "type" "iadd")])
5373 (define_insn "umk_lalm"
5374 [(set (match_operand:DI 0 "register_operand" "=r")
5375 (plus:DI (match_operand:DI 1 "register_operand" "r")
5376 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5377 UNSPEC_UMK_LALM)))]
5378 "TARGET_ABI_UNICOSMK"
5379 "lalm %r0,%t2(%r1)"
5380 [(set_attr "type" "iadd")])
5382 (define_insn "umk_lal"
5383 [(set (match_operand:DI 0 "register_operand" "=r")
5384 (plus:DI (match_operand:DI 1 "register_operand" "r")
5385 (unspec:DI [(match_operand:DI 2 "symbolic_operand" "")]
5386 UNSPEC_UMK_LAL)))]
5387 "TARGET_ABI_UNICOSMK"
5388 "lal %r0,%t2(%r1)"
5389 [(set_attr "type" "iadd")])
5391 ;; Add a new call information word to the current function's list of CIWs
5392 ;; and load its index into $25. Doing it here ensures that the CIW will be
5393 ;; associated with the correct function even in the presence of inlining.
5395 (define_insn "*umk_load_ciw"
5396 [(set (reg:DI 25)
5397 (unspec:DI [(match_operand 0 "" "")] UNSPEC_UMK_LOAD_CIW))]
5398 "TARGET_ABI_UNICOSMK"
5399 {
5400 operands[0] = unicosmk_add_call_info_word (operands[0]);
5401 return "lda $25,%0";
5402 }
5403 [(set_attr "type" "iadd")])
5405 (define_insn "*movdi_er_low_l"
5406 [(set (match_operand:DI 0 "register_operand" "=r")
5407 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
5408 (match_operand:DI 2 "local_symbolic_operand" "")))]
5409 "TARGET_EXPLICIT_RELOCS"
5410 {
5411 if (true_regnum (operands[1]) == 29)
5412 return "lda %0,%2(%1)\t\t!gprel";
5413 else
5414 return "lda %0,%2(%1)\t\t!gprellow";
5415 }
5416 [(set_attr "usegp" "yes")])
5418 (define_split
5419 [(set (match_operand:DI 0 "register_operand" "")
5420 (match_operand:DI 1 "small_symbolic_operand" ""))]
5421 "TARGET_EXPLICIT_RELOCS && reload_completed"
5422 [(set (match_dup 0)
5423 (lo_sum:DI (match_dup 2) (match_dup 1)))]
5424 "operands[2] = pic_offset_table_rtx;")
5426 (define_split
5427 [(set (match_operand:DI 0 "register_operand" "")
5428 (match_operand:DI 1 "local_symbolic_operand" ""))]
5429 "TARGET_EXPLICIT_RELOCS && reload_completed"
5430 [(set (match_dup 0)
5431 (plus:DI (match_dup 2) (high:DI (match_dup 1))))
5432 (set (match_dup 0)
5433 (lo_sum:DI (match_dup 0) (match_dup 1)))]
5434 "operands[2] = pic_offset_table_rtx;")
5436 (define_split
5437 [(match_operand 0 "some_small_symbolic_operand" "")]
5438 ""
5439 [(match_dup 0)]
5440 "operands[0] = split_small_symbolic_operand (operands[0]);")
5442 ;; Accepts any symbolic, not just global, since function calls that
5443 ;; don't go via bsr still use !literal in hopes of linker relaxation.
5444 (define_insn "movdi_er_high_g"
5445 [(set (match_operand:DI 0 "register_operand" "=r")
5446 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5447 (match_operand:DI 2 "symbolic_operand" "")
5448 (match_operand 3 "const_int_operand" "")]
5449 UNSPEC_LITERAL))]
5450 "TARGET_EXPLICIT_RELOCS"
5451 {
5452 if (INTVAL (operands[3]) == 0)
5453 return "ldq %0,%2(%1)\t\t!literal";
5454 else
5455 return "ldq %0,%2(%1)\t\t!literal!%3";
5456 }
5457 [(set_attr "type" "ldsym")])
5459 (define_split
5460 [(set (match_operand:DI 0 "register_operand" "")
5461 (match_operand:DI 1 "global_symbolic_operand" ""))]
5462 "TARGET_EXPLICIT_RELOCS && reload_completed"
5463 [(set (match_dup 0)
5464 (unspec:DI [(match_dup 2)
5465 (match_dup 1)
5466 (const_int 0)] UNSPEC_LITERAL))]
5467 "operands[2] = pic_offset_table_rtx;")
5469 (define_insn "movdi_er_tlsgd"
5470 [(set (match_operand:DI 0 "register_operand" "=r")
5471 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5472 (match_operand:DI 2 "symbolic_operand" "")
5473 (match_operand 3 "const_int_operand" "")]
5474 UNSPEC_TLSGD))]
5475 "HAVE_AS_TLS"
5476 {
5477 if (INTVAL (operands[3]) == 0)
5478 return "lda %0,%2(%1)\t\t!tlsgd";
5479 else
5480 return "lda %0,%2(%1)\t\t!tlsgd!%3";
5481 })
5483 (define_insn "movdi_er_tlsldm"
5484 [(set (match_operand:DI 0 "register_operand" "=r")
5485 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5486 (match_operand 2 "const_int_operand" "")]
5487 UNSPEC_TLSLDM))]
5488 "HAVE_AS_TLS"
5489 {
5490 if (INTVAL (operands[2]) == 0)
5491 return "lda %0,%&(%1)\t\t!tlsldm";
5492 else
5493 return "lda %0,%&(%1)\t\t!tlsldm!%2";
5494 })
5496 (define_insn "*movdi_er_gotdtp"
5497 [(set (match_operand:DI 0 "register_operand" "=r")
5498 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5499 (match_operand:DI 2 "symbolic_operand" "")]
5500 UNSPEC_DTPREL))]
5501 "HAVE_AS_TLS"
5502 "ldq %0,%2(%1)\t\t!gotdtprel"
5503 [(set_attr "type" "ild")
5504 (set_attr "usegp" "yes")])
5506 (define_split
5507 [(set (match_operand:DI 0 "register_operand" "")
5508 (match_operand:DI 1 "gotdtp_symbolic_operand" ""))]
5509 "HAVE_AS_TLS && reload_completed"
5510 [(set (match_dup 0)
5511 (unspec:DI [(match_dup 2)
5512 (match_dup 1)] UNSPEC_DTPREL))]
5513 {
5514 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5515 operands[2] = pic_offset_table_rtx;
5516 })
5518 (define_insn "*movdi_er_gottp"
5519 [(set (match_operand:DI 0 "register_operand" "=r")
5520 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
5521 (match_operand:DI 2 "symbolic_operand" "")]
5522 UNSPEC_TPREL))]
5523 "HAVE_AS_TLS"
5524 "ldq %0,%2(%1)\t\t!gottprel"
5525 [(set_attr "type" "ild")
5526 (set_attr "usegp" "yes")])
5528 (define_split
5529 [(set (match_operand:DI 0 "register_operand" "")
5530 (match_operand:DI 1 "gottp_symbolic_operand" ""))]
5531 "HAVE_AS_TLS && reload_completed"
5532 [(set (match_dup 0)
5533 (unspec:DI [(match_dup 2)
5534 (match_dup 1)] UNSPEC_TPREL))]
5535 {
5536 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0);
5537 operands[2] = pic_offset_table_rtx;
5538 })
5540 (define_insn "*movdi_er_nofix"
5541 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,*f,*f,Q")
5542 (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,n,m,rJ,*fJ,Q,*f"))]
5543 "TARGET_EXPLICIT_RELOCS && ! TARGET_FIX
5544 && (register_operand (operands[0], DImode)
5545 || reg_or_0_operand (operands[1], DImode))"
5546 "@
5547 mov %r1,%0
5548 lda %0,%1($31)
5549 ldah %0,%h1($31)
5550 #
5551 #
5552 #
5553 ldq%A1 %0,%1
5554 stq%A0 %r1,%0
5555 fmov %R1,%0
5556 ldt %0,%1
5557 stt %R1,%0"
5558 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst")
5559 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*")])
5561 ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should
5562 ;; have been split up by the rules above but we shouldn't reject the
5563 ;; possibility of them getting through.
5565 (define_insn "*movdi_nofix"
5566 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,r,m,*f,*f,Q")
5567 (match_operand:DI 1 "input_operand" "rJ,K,L,U,s,n,m,rJ,*fJ,Q,*f"))]
5568 "! TARGET_FIX
5569 && (register_operand (operands[0], DImode)
5570 || reg_or_0_operand (operands[1], DImode))"
5571 "@
5572 bis $31,%r1,%0
5573 lda %0,%1($31)
5574 ldah %0,%h1($31)
5575 laum %0,%t1($31)\;sll %0,32,%0\;lalm %0,%t1(%0)\;lal %0,%t1(%0)
5576 lda %0,%1
5577 #
5578 ldq%A1 %0,%1
5579 stq%A0 %r1,%0
5580 cpys %R1,%R1,%0
5581 ldt %0,%1
5582 stt %R1,%0"
5583 [(set_attr "type" "ilog,iadd,iadd,ldsym,ldsym,multi,ild,ist,fcpys,fld,fst")
5584 (set_attr "length" "*,*,*,16,*,*,*,*,*,*,*")])
5586 (define_insn "*movdi_er_fix"
5587 [(set (match_operand:DI 0 "nonimmediate_operand"
5588 "=r,r,r,r,r,r,r, m, *f,*f, Q, r,*f")
5589 (match_operand:DI 1 "input_operand"
5590 "rJ,K,L,T,s,n,m,rJ,*fJ, Q,*f,*f, r"))]
5591 "TARGET_EXPLICIT_RELOCS && TARGET_FIX
5592 && (register_operand (operands[0], DImode)
5593 || reg_or_0_operand (operands[1], DImode))"
5594 "@
5595 mov %r1,%0
5596 lda %0,%1($31)
5597 ldah %0,%h1($31)
5598 #
5599 #
5600 #
5601 ldq%A1 %0,%1
5602 stq%A0 %r1,%0
5603 fmov %R1,%0
5604 ldt %0,%1
5605 stt %R1,%0
5606 ftoit %1,%0
5607 itoft %1,%0"
5608 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst,ftoi,itof")
5609 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*,*")])
5611 (define_insn "*movdi_fix"
5612 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q,r,*f")
5613 (match_operand:DI 1 "input_operand" "rJ,K,L,s,n,m,rJ,*fJ,Q,*f,*f,r"))]
5614 "! TARGET_EXPLICIT_RELOCS && TARGET_FIX
5615 && (register_operand (operands[0], DImode)
5616 || reg_or_0_operand (operands[1], DImode))"
5617 "@
5618 bis $31,%r1,%0
5619 lda %0,%1($31)
5620 ldah %0,%h1($31)
5621 lda %0,%1
5622 #
5623 ldq%A1 %0,%1
5624 stq%A0 %r1,%0
5625 cpys %R1,%R1,%0
5626 ldt %0,%1
5627 stt %R1,%0
5628 ftoit %1,%0
5629 itoft %1,%0"
5630 [(set_attr "type" "ilog,iadd,iadd,ldsym,multi,ild,ist,fcpys,fld,fst,ftoi,itof")])
5632 ;; VMS needs to set up "vms_base_regno" for unwinding. This move
5633 ;; often appears dead to the life analysis code, at which point we
5634 ;; die for emitting dead prologue instructions. Force this live.
5636 (define_insn "force_movdi"
5637 [(set (match_operand:DI 0 "register_operand" "=r")
5638 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")]
5639 UNSPECV_FORCE_MOV))]
5640 ""
5641 "mov %1,%0"
5642 [(set_attr "type" "ilog")])
5644 ;; We do three major things here: handle mem->mem, put 64-bit constants in
5645 ;; memory, and construct long 32-bit constants.
5647 (define_expand "movdi"
5648 [(set (match_operand:DI 0 "nonimmediate_operand" "")
5649 (match_operand:DI 1 "general_operand" ""))]
5650 ""
5651 {
5652 if (alpha_expand_mov (DImode, operands))
5653 DONE;
5654 })
5656 ;; Split a load of a large constant into the appropriate two-insn
5657 ;; sequence.
5659 (define_split
5660 [(set (match_operand:DI 0 "register_operand" "")
5661 (match_operand:DI 1 "non_add_const_operand" ""))]
5662 ""
5663 [(const_int 0)]
5664 {
5665 if (alpha_split_const_mov (DImode, operands))
5666 DONE;
5667 else
5668 FAIL;
5669 })
5671 ;; These are the partial-word cases.
5672 ;;
5673 ;; First we have the code to load an aligned word. Operand 0 is the register
5674 ;; in which to place the result. It's mode is QImode or HImode. Operand 1
5675 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the
5676 ;; number of bits within the word that the value is. Operand 3 is an SImode
5677 ;; scratch register. If operand 0 is a hard register, operand 3 may be the
5678 ;; same register. It is allowed to conflict with operand 1 as well.
5680 (define_expand "aligned_loadqi"
5681 [(set (match_operand:SI 3 "register_operand" "")
5682 (match_operand:SI 1 "memory_operand" ""))
5683 (set (match_operand:DI 0 "register_operand" "")
5684 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5685 (const_int 8)
5686 (match_operand:DI 2 "const_int_operand" "")))]
5688 ""
5689 "")
5691 (define_expand "aligned_loadhi"
5692 [(set (match_operand:SI 3 "register_operand" "")
5693 (match_operand:SI 1 "memory_operand" ""))
5694 (set (match_operand:DI 0 "register_operand" "")
5695 (zero_extract:DI (subreg:DI (match_dup 3) 0)
5696 (const_int 16)
5697 (match_operand:DI 2 "const_int_operand" "")))]
5699 ""
5700 "")
5702 ;; Similar for unaligned loads, where we use the sequence from the
5703 ;; Alpha Architecture manual. We have to distinguish between little-endian
5704 ;; and big-endian systems as the sequences are different.
5705 ;;
5706 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where
5707 ;; operand 3 can overlap the input and output registers.
5709 (define_expand "unaligned_loadqi"
5710 [(use (match_operand:DI 0 "register_operand" ""))
5711 (use (match_operand:DI 1 "address_operand" ""))
5712 (use (match_operand:DI 2 "register_operand" ""))
5713 (use (match_operand:DI 3 "register_operand" ""))]
5714 ""
5715 {
5716 if (WORDS_BIG_ENDIAN)
5717 emit_insn (gen_unaligned_loadqi_be (operands[0], operands[1],
5718 operands[2], operands[3]));
5719 else
5720 emit_insn (gen_unaligned_loadqi_le (operands[0], operands[1],
5721 operands[2], operands[3]));
5722 DONE;
5723 })
5725 (define_expand "unaligned_loadqi_le"
5726 [(set (match_operand:DI 2 "register_operand" "")
5727 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5728 (const_int -8))))
5729 (set (match_operand:DI 3 "register_operand" "")
5730 (match_dup 1))
5731 (set (match_operand:DI 0 "register_operand" "")
5732 (zero_extract:DI (match_dup 2)
5733 (const_int 8)
5734 (ashift:DI (match_dup 3) (const_int 3))))]
5735 "! WORDS_BIG_ENDIAN"
5736 "")
5738 (define_expand "unaligned_loadqi_be"
5739 [(set (match_operand:DI 2 "register_operand" "")
5740 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5741 (const_int -8))))
5742 (set (match_operand:DI 3 "register_operand" "")
5743 (match_dup 1))
5744 (set (match_operand:DI 0 "register_operand" "")
5745 (zero_extract:DI (match_dup 2)
5746 (const_int 8)
5747 (minus:DI
5748 (const_int 56)
5749 (ashift:DI (match_dup 3) (const_int 3)))))]
5750 "WORDS_BIG_ENDIAN"
5751 "")
5753 (define_expand "unaligned_loadhi"
5754 [(use (match_operand:DI 0 "register_operand" ""))
5755 (use (match_operand:DI 1 "address_operand" ""))
5756 (use (match_operand:DI 2 "register_operand" ""))
5757 (use (match_operand:DI 3 "register_operand" ""))]
5758 ""
5759 {
5760 if (WORDS_BIG_ENDIAN)
5761 emit_insn (gen_unaligned_loadhi_be (operands[0], operands[1],
5762 operands[2], operands[3]));
5763 else
5764 emit_insn (gen_unaligned_loadhi_le (operands[0], operands[1],
5765 operands[2], operands[3]));
5766 DONE;
5767 })
5769 (define_expand "unaligned_loadhi_le"
5770 [(set (match_operand:DI 2 "register_operand" "")
5771 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5772 (const_int -8))))
5773 (set (match_operand:DI 3 "register_operand" "")
5774 (match_dup 1))
5775 (set (match_operand:DI 0 "register_operand" "")
5776 (zero_extract:DI (match_dup 2)
5777 (const_int 16)
5778 (ashift:DI (match_dup 3) (const_int 3))))]
5779 "! WORDS_BIG_ENDIAN"
5780 "")
5782 (define_expand "unaligned_loadhi_be"
5783 [(set (match_operand:DI 2 "register_operand" "")
5784 (mem:DI (and:DI (match_operand:DI 1 "address_operand" "")
5785 (const_int -8))))
5786 (set (match_operand:DI 3 "register_operand" "")
5787 (plus:DI (match_dup 1) (const_int 1)))
5788 (set (match_operand:DI 0 "register_operand" "")
5789 (zero_extract:DI (match_dup 2)
5790 (const_int 16)
5791 (minus:DI
5792 (const_int 56)
5793 (ashift:DI (match_dup 3) (const_int 3)))))]
5794 "WORDS_BIG_ENDIAN"
5795 "")
5797 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the
5798 ;; aligned SImode MEM. Operand 1 is the register containing the
5799 ;; byte or word to store. Operand 2 is the number of bits within the word that
5800 ;; the value should be placed. Operands 3 and 4 are SImode temporaries.
5802 (define_expand "aligned_store"
5803 [(set (match_operand:SI 3 "register_operand" "")
5804 (match_operand:SI 0 "memory_operand" ""))
5805 (set (subreg:DI (match_dup 3) 0)
5806 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5)))
5807 (set (subreg:DI (match_operand:SI 4 "register_operand" "") 0)
5808 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand" ""))
5809 (match_operand:DI 2 "const_int_operand" "")))
5810 (set (subreg:DI (match_dup 4) 0)
5811 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0)))
5812 (set (match_dup 0) (match_dup 4))]
5813 ""
5814 {
5815 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1]))
5816 << INTVAL (operands[2])));
5817 })
5819 ;; For the unaligned byte and halfword cases, we use code similar to that
5820 ;; in the ;; Architecture book, but reordered to lower the number of registers
5821 ;; required. Operand 0 is the address. Operand 1 is the data to store.
5822 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may
5823 ;; be the same temporary, if desired. If the address is in a register,
5824 ;; operand 2 can be that register.
5826 (define_expand "unaligned_storeqi"
5827 [(use (match_operand:DI 0 "address_operand" ""))
5828 (use (match_operand:QI 1 "register_operand" ""))
5829 (use (match_operand:DI 2 "register_operand" ""))
5830 (use (match_operand:DI 3 "register_operand" ""))
5831 (use (match_operand:DI 4 "register_operand" ""))]
5832 ""
5833 {
5834 if (WORDS_BIG_ENDIAN)
5835 emit_insn (gen_unaligned_storeqi_be (operands[0], operands[1],
5836 operands[2], operands[3],
5837 operands[4]));
5838 else
5839 emit_insn (gen_unaligned_storeqi_le (operands[0], operands[1],
5840 operands[2], operands[3],
5841 operands[4]));
5842 DONE;
5843 })
5845 (define_expand "unaligned_storeqi_le"
5846 [(set (match_operand:DI 3 "register_operand" "")
5847 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5848 (const_int -8))))
5849 (set (match_operand:DI 2 "register_operand" "")
5850 (match_dup 0))
5851 (set (match_dup 3)
5852 (and:DI (not:DI (ashift:DI (const_int 255)
5853 (ashift:DI (match_dup 2) (const_int 3))))
5854 (match_dup 3)))
5855 (set (match_operand:DI 4 "register_operand" "")
5856 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5857 (ashift:DI (match_dup 2) (const_int 3))))
5858 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5859 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5860 (match_dup 4))]
5861 "! WORDS_BIG_ENDIAN"
5862 "")
5864 (define_expand "unaligned_storeqi_be"
5865 [(set (match_operand:DI 3 "register_operand" "")
5866 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5867 (const_int -8))))
5868 (set (match_operand:DI 2 "register_operand" "")
5869 (match_dup 0))
5870 (set (match_dup 3)
5871 (and:DI (not:DI (ashift:DI (const_int 255)
5872 (minus:DI (const_int 56)
5873 (ashift:DI (match_dup 2) (const_int 3)))))
5874 (match_dup 3)))
5875 (set (match_operand:DI 4 "register_operand" "")
5876 (ashift:DI (zero_extend:DI (match_operand:QI 1 "register_operand" ""))
5877 (minus:DI (const_int 56)
5878 (ashift:DI (match_dup 2) (const_int 3)))))
5879 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5880 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5881 (match_dup 4))]
5882 "WORDS_BIG_ENDIAN"
5883 "")
5885 (define_expand "unaligned_storehi"
5886 [(use (match_operand:DI 0 "address_operand" ""))
5887 (use (match_operand:HI 1 "register_operand" ""))
5888 (use (match_operand:DI 2 "register_operand" ""))
5889 (use (match_operand:DI 3 "register_operand" ""))
5890 (use (match_operand:DI 4 "register_operand" ""))]
5891 ""
5892 {
5893 if (WORDS_BIG_ENDIAN)
5894 emit_insn (gen_unaligned_storehi_be (operands[0], operands[1],
5895 operands[2], operands[3],
5896 operands[4]));
5897 else
5898 emit_insn (gen_unaligned_storehi_le (operands[0], operands[1],
5899 operands[2], operands[3],
5900 operands[4]));
5901 DONE;
5902 })
5904 (define_expand "unaligned_storehi_le"
5905 [(set (match_operand:DI 3 "register_operand" "")
5906 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5907 (const_int -8))))
5908 (set (match_operand:DI 2 "register_operand" "")
5909 (match_dup 0))
5910 (set (match_dup 3)
5911 (and:DI (not:DI (ashift:DI (const_int 65535)
5912 (ashift:DI (match_dup 2) (const_int 3))))
5913 (match_dup 3)))
5914 (set (match_operand:DI 4 "register_operand" "")
5915 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5916 (ashift:DI (match_dup 2) (const_int 3))))
5917 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5918 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5919 (match_dup 4))]
5920 "! WORDS_BIG_ENDIAN"
5921 "")
5923 (define_expand "unaligned_storehi_be"
5924 [(set (match_operand:DI 3 "register_operand" "")
5925 (mem:DI (and:DI (match_operand:DI 0 "address_operand" "")
5926 (const_int -8))))
5927 (set (match_operand:DI 2 "register_operand" "")
5928 (plus:DI (match_dup 0) (const_int 1)))
5929 (set (match_dup 3)
5930 (and:DI (not:DI (ashift:DI
5931 (const_int 65535)
5932 (minus:DI (const_int 56)
5933 (ashift:DI (match_dup 2) (const_int 3)))))
5934 (match_dup 3)))
5935 (set (match_operand:DI 4 "register_operand" "")
5936 (ashift:DI (zero_extend:DI (match_operand:HI 1 "register_operand" ""))
5937 (minus:DI (const_int 56)
5938 (ashift:DI (match_dup 2) (const_int 3)))))
5939 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3)))
5940 (set (mem:DI (and:DI (match_dup 0) (const_int -8)))
5941 (match_dup 4))]
5942 "WORDS_BIG_ENDIAN"
5943 "")
5944 \f
5945 ;; Here are the define_expand's for QI and HI moves that use the above
5946 ;; patterns. We have the normal sets, plus the ones that need scratch
5947 ;; registers for reload.
5949 (define_expand "movqi"
5950 [(set (match_operand:QI 0 "nonimmediate_operand" "")
5951 (match_operand:QI 1 "general_operand" ""))]
5952 ""
5953 {
5954 if (TARGET_BWX
5955 ? alpha_expand_mov (QImode, operands)
5956 : alpha_expand_mov_nobwx (QImode, operands))
5957 DONE;
5958 })
5960 (define_expand "movhi"
5961 [(set (match_operand:HI 0 "nonimmediate_operand" "")
5962 (match_operand:HI 1 "general_operand" ""))]
5963 ""
5964 {
5965 if (TARGET_BWX
5966 ? alpha_expand_mov (HImode, operands)
5967 : alpha_expand_mov_nobwx (HImode, operands))
5968 DONE;
5969 })
5971 ;; Here are the versions for reload. Note that in the unaligned cases
5972 ;; we know that the operand must not be a pseudo-register because stack
5973 ;; slots are always aligned references.
5975 (define_expand "reload_inqi"
5976 [(parallel [(match_operand:QI 0 "register_operand" "=r")
5977 (match_operand:QI 1 "any_memory_operand" "m")
5978 (match_operand:TI 2 "register_operand" "=&r")])]
5979 "! TARGET_BWX"
5980 {
5981 rtx scratch, seq;
5983 if (aligned_memory_operand (operands[1], QImode))
5984 {
5985 seq = gen_reload_inqi_help (operands[0], operands[1],
5986 gen_rtx_REG (SImode, REGNO (operands[2])));
5987 }
5988 else
5989 {
5990 rtx addr;
5992 /* It is possible that one of the registers we got for operands[2]
5993 might coincide with that of operands[0] (which is why we made
5994 it TImode). Pick the other one to use as our scratch. */
5995 if (REGNO (operands[0]) == REGNO (operands[2]))
5996 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
5997 else
5998 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
6000 addr = get_unaligned_address (operands[1], 0);
6001 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
6002 seq = gen_unaligned_loadqi (operands[0], addr, scratch, operands[0]);
6003 alpha_set_memflags (seq, operands[1]);
6004 }
6005 emit_insn (seq);
6006 DONE;
6007 })
6009 (define_expand "reload_inhi"
6010 [(parallel [(match_operand:HI 0 "register_operand" "=r")
6011 (match_operand:HI 1 "any_memory_operand" "m")
6012 (match_operand:TI 2 "register_operand" "=&r")])]
6013 "! TARGET_BWX"
6014 {
6015 rtx scratch, seq;
6017 if (aligned_memory_operand (operands[1], HImode))
6018 {
6019 seq = gen_reload_inhi_help (operands[0], operands[1],
6020 gen_rtx_REG (SImode, REGNO (operands[2])));
6021 }
6022 else
6023 {
6024 rtx addr;
6026 /* It is possible that one of the registers we got for operands[2]
6027 might coincide with that of operands[0] (which is why we made
6028 it TImode). Pick the other one to use as our scratch. */
6029 if (REGNO (operands[0]) == REGNO (operands[2]))
6030 scratch = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6031 else
6032 scratch = gen_rtx_REG (DImode, REGNO (operands[2]));
6034 addr = get_unaligned_address (operands[1], 0);
6035 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0]));
6036 seq = gen_unaligned_loadhi (operands[0], addr, scratch, operands[0]);
6037 alpha_set_memflags (seq, operands[1]);
6038 }
6039 emit_insn (seq);
6040 DONE;
6041 })
6043 (define_expand "reload_outqi"
6044 [(parallel [(match_operand:QI 0 "any_memory_operand" "=m")
6045 (match_operand:QI 1 "register_operand" "r")
6046 (match_operand:TI 2 "register_operand" "=&r")])]
6047 "! TARGET_BWX"
6048 {
6049 if (aligned_memory_operand (operands[0], QImode))
6050 {
6051 emit_insn (gen_reload_outqi_help
6052 (operands[0], operands[1],
6053 gen_rtx_REG (SImode, REGNO (operands[2])),
6054 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6055 }
6056 else
6057 {
6058 rtx addr = get_unaligned_address (operands[0], 0);
6059 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6060 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6061 rtx scratch3 = scratch1;
6062 rtx seq;
6064 if (GET_CODE (addr) == REG)
6065 scratch1 = addr;
6067 seq = gen_unaligned_storeqi (addr, operands[1], scratch1,
6068 scratch2, scratch3);
6069 alpha_set_memflags (seq, operands[0]);
6070 emit_insn (seq);
6071 }
6072 DONE;
6073 })
6075 (define_expand "reload_outhi"
6076 [(parallel [(match_operand:HI 0 "any_memory_operand" "=m")
6077 (match_operand:HI 1 "register_operand" "r")
6078 (match_operand:TI 2 "register_operand" "=&r")])]
6079 "! TARGET_BWX"
6080 {
6081 if (aligned_memory_operand (operands[0], HImode))
6082 {
6083 emit_insn (gen_reload_outhi_help
6084 (operands[0], operands[1],
6085 gen_rtx_REG (SImode, REGNO (operands[2])),
6086 gen_rtx_REG (SImode, REGNO (operands[2]) + 1)));
6087 }
6088 else
6089 {
6090 rtx addr = get_unaligned_address (operands[0], 0);
6091 rtx scratch1 = gen_rtx_REG (DImode, REGNO (operands[2]));
6092 rtx scratch2 = gen_rtx_REG (DImode, REGNO (operands[2]) + 1);
6093 rtx scratch3 = scratch1;
6094 rtx seq;
6096 if (GET_CODE (addr) == REG)
6097 scratch1 = addr;
6099 seq = gen_unaligned_storehi (addr, operands[1], scratch1,
6100 scratch2, scratch3);
6101 alpha_set_memflags (seq, operands[0]);
6102 emit_insn (seq);
6103 }
6104 DONE;
6105 })
6107 ;; Helpers for the above. The way reload is structured, we can't
6108 ;; always get a proper address for a stack slot during reload_foo
6109 ;; expansion, so we must delay our address manipulations until after.
6111 (define_insn_and_split "reload_inqi_help"
6112 [(set (match_operand:QI 0 "register_operand" "=r")
6113 (match_operand:QI 1 "memory_operand" "m"))
6114 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6115 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6116 "#"
6117 "! TARGET_BWX && reload_completed"
6118 [(const_int 0)]
6119 {
6120 rtx aligned_mem, bitnum;
6121 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6122 operands[0] = gen_lowpart (DImode, operands[0]);
6123 emit_insn (gen_aligned_loadqi (operands[0], aligned_mem, bitnum,
6124 operands[2]));
6125 DONE;
6126 })
6128 (define_insn_and_split "reload_inhi_help"
6129 [(set (match_operand:HI 0 "register_operand" "=r")
6130 (match_operand:HI 1 "memory_operand" "m"))
6131 (clobber (match_operand:SI 2 "register_operand" "=r"))]
6132 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6133 "#"
6134 "! TARGET_BWX && reload_completed"
6135 [(const_int 0)]
6136 {
6137 rtx aligned_mem, bitnum;
6138 get_aligned_mem (operands[1], &aligned_mem, &bitnum);
6139 operands[0] = gen_lowpart (DImode, operands[0]);
6140 emit_insn (gen_aligned_loadhi (operands[0], aligned_mem, bitnum,
6141 operands[2]));
6142 DONE;
6143 })
6145 (define_insn_and_split "reload_outqi_help"
6146 [(set (match_operand:QI 0 "memory_operand" "=m")
6147 (match_operand:QI 1 "register_operand" "r"))
6148 (clobber (match_operand:SI 2 "register_operand" "=r"))
6149 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6150 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6151 "#"
6152 "! TARGET_BWX && reload_completed"
6153 [(const_int 0)]
6154 {
6155 rtx aligned_mem, bitnum;
6156 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6157 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6158 operands[2], operands[3]));
6159 DONE;
6160 })
6162 (define_insn_and_split "reload_outhi_help"
6163 [(set (match_operand:HI 0 "memory_operand" "=m")
6164 (match_operand:HI 1 "register_operand" "r"))
6165 (clobber (match_operand:SI 2 "register_operand" "=r"))
6166 (clobber (match_operand:SI 3 "register_operand" "=r"))]
6167 "! TARGET_BWX && (reload_in_progress || reload_completed)"
6168 "#"
6169 "! TARGET_BWX && reload_completed"
6170 [(const_int 0)]
6171 {
6172 rtx aligned_mem, bitnum;
6173 get_aligned_mem (operands[0], &aligned_mem, &bitnum);
6174 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum,
6175 operands[2], operands[3]));
6176 DONE;
6177 })
6178 \f
6179 ;; Vector operations
6181 (define_mode_macro VEC [V8QI V4HI V2SI])
6183 (define_expand "mov<mode>"
6184 [(set (match_operand:VEC 0 "nonimmediate_operand" "")
6185 (match_operand:VEC 1 "general_operand" ""))]
6186 ""
6187 {
6188 if (alpha_expand_mov (<MODE>mode, operands))
6189 DONE;
6190 })
6192 (define_split
6193 [(set (match_operand:VEC 0 "register_operand" "")
6194 (match_operand:VEC 1 "non_zero_const_operand" ""))]
6195 ""
6196 [(const_int 0)]
6197 {
6198 if (alpha_split_const_mov (<MODE>mode, operands))
6199 DONE;
6200 else
6201 FAIL;
6202 })
6205 (define_expand "movmisalign<mode>"
6206 [(set (match_operand:VEC 0 "nonimmediate_operand" "")
6207 (match_operand:VEC 1 "general_operand" ""))]
6208 ""
6209 {
6210 alpha_expand_movmisalign (<MODE>mode, operands);
6211 DONE;
6212 })
6214 (define_insn "*mov<mode>_fix"
6215 [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m,r,*f")
6216 (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f,*f,r"))]
6217 "TARGET_FIX
6218 && (register_operand (operands[0], <MODE>mode)
6219 || reg_or_0_operand (operands[1], <MODE>mode))"
6220 "@
6221 bis $31,%r1,%0
6222 #
6223 ldq %0,%1
6224 stq %r1,%0
6225 cpys %R1,%R1,%0
6226 ldt %0,%1
6227 stt %R1,%0
6228 ftoit %1,%0
6229 itoft %1,%0"
6230 [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof")])
6232 (define_insn "*mov<mode>_nofix"
6233 [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m")
6234 (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f"))]
6235 "! TARGET_FIX
6236 && (register_operand (operands[0], <MODE>mode)
6237 || reg_or_0_operand (operands[1], <MODE>mode))"
6238 "@
6239 bis $31,%r1,%0
6240 #
6241 ldq %0,%1
6242 stq %r1,%0
6243 cpys %R1,%R1,%0
6244 ldt %0,%1
6245 stt %R1,%0"
6246 [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst")])
6248 (define_insn "uminv8qi3"
6249 [(set (match_operand:V8QI 0 "register_operand" "=r")
6250 (umin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6251 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6252 "TARGET_MAX"
6253 "minub8 %r1,%r2,%0"
6254 [(set_attr "type" "mvi")])
6256 (define_insn "sminv8qi3"
6257 [(set (match_operand:V8QI 0 "register_operand" "=r")
6258 (smin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6259 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6260 "TARGET_MAX"
6261 "minsb8 %r1,%r2,%0"
6262 [(set_attr "type" "mvi")])
6264 (define_insn "uminv4hi3"
6265 [(set (match_operand:V4HI 0 "register_operand" "=r")
6266 (umin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6267 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6268 "TARGET_MAX"
6269 "minuw4 %r1,%r2,%0"
6270 [(set_attr "type" "mvi")])
6272 (define_insn "sminv4hi3"
6273 [(set (match_operand:V4HI 0 "register_operand" "=r")
6274 (smin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6275 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6276 "TARGET_MAX"
6277 "minsw4 %r1,%r2,%0"
6278 [(set_attr "type" "mvi")])
6280 (define_insn "umaxv8qi3"
6281 [(set (match_operand:V8QI 0 "register_operand" "=r")
6282 (umax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6283 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6284 "TARGET_MAX"
6285 "maxub8 %r1,%r2,%0"
6286 [(set_attr "type" "mvi")])
6288 (define_insn "smaxv8qi3"
6289 [(set (match_operand:V8QI 0 "register_operand" "=r")
6290 (smax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
6291 (match_operand:V8QI 2 "reg_or_0_operand" "rW")))]
6292 "TARGET_MAX"
6293 "maxsb8 %r1,%r2,%0"
6294 [(set_attr "type" "mvi")])
6296 (define_insn "umaxv4hi3"
6297 [(set (match_operand:V4HI 0 "register_operand" "=r")
6298 (umax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6299 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6300 "TARGET_MAX"
6301 "maxuw4 %r1,%r2,%0"
6302 [(set_attr "type" "mvi")])
6304 (define_insn "smaxv4hi3"
6305 [(set (match_operand:V4HI 0 "register_operand" "=r")
6306 (smax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW")
6307 (match_operand:V4HI 2 "reg_or_0_operand" "rW")))]
6308 "TARGET_MAX"
6309 "maxsw4 %r1,%r2,%0"
6310 [(set_attr "type" "mvi")])
6312 (define_insn "one_cmpl<mode>2"
6313 [(set (match_operand:VEC 0 "register_operand" "=r")
6314 (not:VEC (match_operand:VEC 1 "register_operand" "r")))]
6315 ""
6316 "ornot $31,%1,%0"
6317 [(set_attr "type" "ilog")])
6319 (define_insn "and<mode>3"
6320 [(set (match_operand:VEC 0 "register_operand" "=r")
6321 (and:VEC (match_operand:VEC 1 "register_operand" "r")
6322 (match_operand:VEC 2 "register_operand" "r")))]
6323 ""
6324 "and %1,%2,%0"
6325 [(set_attr "type" "ilog")])
6327 (define_insn "*andnot<mode>3"
6328 [(set (match_operand:VEC 0 "register_operand" "=r")
6329 (and:VEC (not:VEC (match_operand:VEC 1 "register_operand" "r"))
6330 (match_operand:VEC 2 "register_operand" "r")))]
6331 ""
6332 "bic %2,%1,%0"
6333 [(set_attr "type" "ilog")])
6335 (define_insn "ior<mode>3"
6336 [(set (match_operand:VEC 0 "register_operand" "=r")
6337 (ior:VEC (match_operand:VEC 1 "register_operand" "r")
6338 (match_operand:VEC 2 "register_operand" "r")))]
6339 ""
6340 "bis %1,%2,%0"
6341 [(set_attr "type" "ilog")])
6343 (define_insn "*iornot<mode>3"
6344 [(set (match_operand:VEC 0 "register_operand" "=r")
6345 (ior:VEC (not:DI (match_operand:VEC 1 "register_operand" "r"))
6346 (match_operand:VEC 2 "register_operand" "r")))]
6347 ""
6348 "ornot %2,%1,%0"
6349 [(set_attr "type" "ilog")])
6351 (define_insn "xor<mode>3"
6352 [(set (match_operand:VEC 0 "register_operand" "=r")
6353 (xor:VEC (match_operand:VEC 1 "register_operand" "r")
6354 (match_operand:VEC 2 "register_operand" "r")))]
6355 ""
6356 "xor %1,%2,%0"
6357 [(set_attr "type" "ilog")])
6359 (define_insn "*xornot<mode>3"
6360 [(set (match_operand:VEC 0 "register_operand" "=r")
6361 (not:VEC (xor:VEC (match_operand:VEC 1 "register_operand" "r")
6362 (match_operand:VEC 2 "register_operand" "r"))))]
6363 ""
6364 "eqv %1,%2,%0"
6365 [(set_attr "type" "ilog")])
6367 (define_expand "vec_shl_<mode>"
6368 [(set (match_operand:VEC 0 "register_operand" "")
6369 (ashift:DI (match_operand:VEC 1 "register_operand" "")
6370 (match_operand:DI 2 "reg_or_6bit_operand" "")))]
6371 ""
6372 {
6373 operands[0] = gen_lowpart (DImode, operands[0]);
6374 operands[1] = gen_lowpart (DImode, operands[1]);
6375 })
6377 (define_expand "vec_shr_<mode>"
6378 [(set (match_operand:VEC 0 "register_operand" "")
6379 (lshiftrt:DI (match_operand:VEC 1 "register_operand" "")
6380 (match_operand:DI 2 "reg_or_6bit_operand" "")))]
6381 ""
6382 {
6383 operands[0] = gen_lowpart (DImode, operands[0]);
6384 operands[1] = gen_lowpart (DImode, operands[1]);
6385 })
6386 \f
6387 ;; Bit field extract patterns which use ext[wlq][lh]
6389 (define_expand "extv"
6390 [(set (match_operand:DI 0 "register_operand" "")
6391 (sign_extract:DI (match_operand:QI 1 "memory_operand" "")
6392 (match_operand:DI 2 "immediate_operand" "")
6393 (match_operand:DI 3 "immediate_operand" "")))]
6394 ""
6395 {
6396 int ofs;
6398 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6399 if (INTVAL (operands[3]) % 8 != 0
6400 || (INTVAL (operands[2]) != 16
6401 && INTVAL (operands[2]) != 32
6402 && INTVAL (operands[2]) != 64))
6403 FAIL;
6405 /* From mips.md: extract_bit_field doesn't verify that our source
6406 matches the predicate, so we force it to be a MEM here. */
6407 if (GET_CODE (operands[1]) != MEM)
6408 FAIL;
6410 /* The bit number is relative to the mode of operand 1 which is
6411 usually QImode (this might actually be a bug in expmed.c). Note
6412 that the bit number is negative in big-endian mode in this case.
6413 We have to convert that to the offset. */
6414 if (WORDS_BIG_ENDIAN)
6415 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6416 - INTVAL (operands[2]) - INTVAL (operands[3]);
6417 else
6418 ofs = INTVAL (operands[3]);
6420 ofs = ofs / 8;
6422 alpha_expand_unaligned_load (operands[0], operands[1],
6423 INTVAL (operands[2]) / 8,
6424 ofs, 1);
6425 DONE;
6426 })
6428 (define_expand "extzv"
6429 [(set (match_operand:DI 0 "register_operand" "")
6430 (zero_extract:DI (match_operand:DI 1 "nonimmediate_operand" "")
6431 (match_operand:DI 2 "immediate_operand" "")
6432 (match_operand:DI 3 "immediate_operand" "")))]
6433 ""
6434 {
6435 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6436 if (INTVAL (operands[3]) % 8 != 0
6437 || (INTVAL (operands[2]) != 8
6438 && INTVAL (operands[2]) != 16
6439 && INTVAL (operands[2]) != 32
6440 && INTVAL (operands[2]) != 64))
6441 FAIL;
6443 if (GET_CODE (operands[1]) == MEM)
6444 {
6445 int ofs;
6447 /* Fail 8 bit fields, falling back on a simple byte load. */
6448 if (INTVAL (operands[2]) == 8)
6449 FAIL;
6451 /* The bit number is relative to the mode of operand 1 which is
6452 usually QImode (this might actually be a bug in expmed.c). Note
6453 that the bit number is negative in big-endian mode in this case.
6454 We have to convert that to the offset. */
6455 if (WORDS_BIG_ENDIAN)
6456 ofs = GET_MODE_BITSIZE (GET_MODE (operands[1]))
6457 - INTVAL (operands[2]) - INTVAL (operands[3]);
6458 else
6459 ofs = INTVAL (operands[3]);
6461 ofs = ofs / 8;
6463 alpha_expand_unaligned_load (operands[0], operands[1],
6464 INTVAL (operands[2]) / 8,
6465 ofs, 0);
6466 DONE;
6467 }
6468 })
6470 (define_expand "insv"
6471 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "")
6472 (match_operand:DI 1 "immediate_operand" "")
6473 (match_operand:DI 2 "immediate_operand" ""))
6474 (match_operand:DI 3 "register_operand" ""))]
6475 ""
6476 {
6477 int ofs;
6479 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */
6480 if (INTVAL (operands[2]) % 8 != 0
6481 || (INTVAL (operands[1]) != 16
6482 && INTVAL (operands[1]) != 32
6483 && INTVAL (operands[1]) != 64))
6484 FAIL;
6486 /* From mips.md: store_bit_field doesn't verify that our source
6487 matches the predicate, so we force it to be a MEM here. */
6488 if (GET_CODE (operands[0]) != MEM)
6489 FAIL;
6491 /* The bit number is relative to the mode of operand 1 which is
6492 usually QImode (this might actually be a bug in expmed.c). Note
6493 that the bit number is negative in big-endian mode in this case.
6494 We have to convert that to the offset. */
6495 if (WORDS_BIG_ENDIAN)
6496 ofs = GET_MODE_BITSIZE (GET_MODE (operands[0]))
6497 - INTVAL (operands[1]) - INTVAL (operands[2]);
6498 else
6499 ofs = INTVAL (operands[2]);
6501 ofs = ofs / 8;
6503 alpha_expand_unaligned_store (operands[0], operands[3],
6504 INTVAL (operands[1]) / 8, ofs);
6505 DONE;
6506 })
6508 ;; Block move/clear, see alpha.c for more details.
6509 ;; Argument 0 is the destination
6510 ;; Argument 1 is the source
6511 ;; Argument 2 is the length
6512 ;; Argument 3 is the alignment
6514 (define_expand "movmemqi"
6515 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6516 (match_operand:BLK 1 "memory_operand" ""))
6517 (use (match_operand:DI 2 "immediate_operand" ""))
6518 (use (match_operand:DI 3 "immediate_operand" ""))])]
6519 ""
6520 {
6521 if (alpha_expand_block_move (operands))
6522 DONE;
6523 else
6524 FAIL;
6525 })
6527 (define_expand "movmemdi"
6528 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6529 (match_operand:BLK 1 "memory_operand" ""))
6530 (use (match_operand:DI 2 "immediate_operand" ""))
6531 (use (match_operand:DI 3 "immediate_operand" ""))
6532 (use (match_dup 4))
6533 (clobber (reg:DI 25))
6534 (clobber (reg:DI 16))
6535 (clobber (reg:DI 17))
6536 (clobber (reg:DI 18))
6537 (clobber (reg:DI 19))
6538 (clobber (reg:DI 20))
6539 (clobber (reg:DI 26))
6540 (clobber (reg:DI 27))])]
6541 "TARGET_ABI_OPEN_VMS"
6542 {
6543 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$MOVE");
6544 alpha_need_linkage (XSTR (operands[4], 0), 0);
6545 })
6547 (define_insn "*movmemdi_1"
6548 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6549 (match_operand:BLK 1 "memory_operand" "m,m"))
6550 (use (match_operand:DI 2 "nonmemory_operand" "r,i"))
6551 (use (match_operand:DI 3 "immediate_operand" ""))
6552 (use (match_operand:DI 4 "call_operand" "i,i"))
6553 (clobber (reg:DI 25))
6554 (clobber (reg:DI 16))
6555 (clobber (reg:DI 17))
6556 (clobber (reg:DI 18))
6557 (clobber (reg:DI 19))
6558 (clobber (reg:DI 20))
6559 (clobber (reg:DI 26))
6560 (clobber (reg:DI 27))]
6561 "TARGET_ABI_OPEN_VMS"
6562 {
6563 operands [5] = alpha_use_linkage (operands [4], cfun->decl, 0, 1);
6564 switch (which_alternative)
6565 {
6566 case 0:
6567 return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6568 case 1:
6569 return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)";
6570 default:
6571 gcc_unreachable ();
6572 }
6573 }
6574 [(set_attr "type" "multi")
6575 (set_attr "length" "28")])
6577 (define_expand "setmemqi"
6578 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6579 (match_operand 2 "const_int_operand" ""))
6580 (use (match_operand:DI 1 "immediate_operand" ""))
6581 (use (match_operand:DI 3 "immediate_operand" ""))])]
6582 ""
6583 {
6584 /* If value to set is not zero, use the library routine. */
6585 if (operands[2] != const0_rtx)
6586 FAIL;
6588 if (alpha_expand_block_clear (operands))
6589 DONE;
6590 else
6591 FAIL;
6592 })
6594 (define_expand "setmemdi"
6595 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
6596 (match_operand 2 "const_int_operand" ""))
6597 (use (match_operand:DI 1 "immediate_operand" ""))
6598 (use (match_operand:DI 3 "immediate_operand" ""))
6599 (use (match_dup 4))
6600 (clobber (reg:DI 25))
6601 (clobber (reg:DI 16))
6602 (clobber (reg:DI 17))
6603 (clobber (reg:DI 26))
6604 (clobber (reg:DI 27))])]
6605 "TARGET_ABI_OPEN_VMS"
6606 {
6607 /* If value to set is not zero, use the library routine. */
6608 if (operands[2] != const0_rtx)
6609 FAIL;
6611 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO");
6612 alpha_need_linkage (XSTR (operands[4], 0), 0);
6613 })
6615 (define_insn "*clrmemdi_1"
6616 [(set (match_operand:BLK 0 "memory_operand" "=m,=m")
6617 (const_int 0))
6618 (use (match_operand:DI 1 "nonmemory_operand" "r,i"))
6619 (use (match_operand:DI 2 "immediate_operand" ""))
6620 (use (match_operand:DI 3 "call_operand" "i,i"))
6621 (clobber (reg:DI 25))
6622 (clobber (reg:DI 16))
6623 (clobber (reg:DI 17))
6624 (clobber (reg:DI 26))
6625 (clobber (reg:DI 27))]
6626 "TARGET_ABI_OPEN_VMS"
6627 {
6628 operands [4] = alpha_use_linkage (operands [3], cfun->decl, 0, 1);
6629 switch (which_alternative)
6630 {
6631 case 0:
6632 return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6633 case 1:
6634 return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)";
6635 default:
6636 gcc_unreachable ();
6637 }
6638 }
6639 [(set_attr "type" "multi")
6640 (set_attr "length" "24")])
6642 \f
6643 ;; Subroutine of stack space allocation. Perform a stack probe.
6644 (define_expand "probe_stack"
6645 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand" ""))]
6646 ""
6647 {
6648 operands[1] = gen_rtx_MEM (DImode, plus_constant (stack_pointer_rtx,
6649 INTVAL (operands[0])));
6650 MEM_VOLATILE_P (operands[1]) = 1;
6652 operands[0] = const0_rtx;
6653 })
6655 ;; This is how we allocate stack space. If we are allocating a
6656 ;; constant amount of space and we know it is less than 4096
6657 ;; bytes, we need do nothing.
6658 ;;
6659 ;; If it is more than 4096 bytes, we need to probe the stack
6660 ;; periodically.
6661 (define_expand "allocate_stack"
6662 [(set (reg:DI 30)
6663 (plus:DI (reg:DI 30)
6664 (match_operand:DI 1 "reg_or_cint_operand" "")))
6665 (set (match_operand:DI 0 "register_operand" "=r")
6666 (match_dup 2))]
6667 ""
6668 {
6669 if (GET_CODE (operands[1]) == CONST_INT
6670 && INTVAL (operands[1]) < 32768)
6671 {
6672 if (INTVAL (operands[1]) >= 4096)
6673 {
6674 /* We do this the same way as in the prologue and generate explicit
6675 probes. Then we update the stack by the constant. */
6677 int probed = 4096;
6679 emit_insn (gen_probe_stack (GEN_INT (- probed)));
6680 while (probed + 8192 < INTVAL (operands[1]))
6681 emit_insn (gen_probe_stack (GEN_INT (- (probed += 8192))));
6683 if (probed + 4096 < INTVAL (operands[1]))
6684 emit_insn (gen_probe_stack (GEN_INT (- INTVAL(operands[1]))));
6685 }
6687 operands[1] = GEN_INT (- INTVAL (operands[1]));
6688 operands[2] = virtual_stack_dynamic_rtx;
6689 }
6690 else
6691 {
6692 rtx out_label = 0;
6693 rtx loop_label = gen_label_rtx ();
6694 rtx want = gen_reg_rtx (Pmode);
6695 rtx tmp = gen_reg_rtx (Pmode);
6696 rtx memref;
6698 emit_insn (gen_subdi3 (want, stack_pointer_rtx,
6699 force_reg (Pmode, operands[1])));
6700 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096)));
6702 if (GET_CODE (operands[1]) != CONST_INT)
6703 {
6704 out_label = gen_label_rtx ();
6705 emit_insn (gen_cmpdi (want, tmp));
6706 emit_jump_insn (gen_bgeu (out_label));
6707 }
6709 emit_label (loop_label);
6710 memref = gen_rtx_MEM (DImode, tmp);
6711 MEM_VOLATILE_P (memref) = 1;
6712 emit_move_insn (memref, const0_rtx);
6713 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192)));
6714 emit_insn (gen_cmpdi (tmp, want));
6715 emit_jump_insn (gen_bgtu (loop_label));
6717 memref = gen_rtx_MEM (DImode, want);
6718 MEM_VOLATILE_P (memref) = 1;
6719 emit_move_insn (memref, const0_rtx);
6721 if (out_label)
6722 emit_label (out_label);
6724 emit_move_insn (stack_pointer_rtx, want);
6725 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
6726 DONE;
6727 }
6728 })
6730 ;; This is used by alpha_expand_prolog to do the same thing as above,
6731 ;; except we cannot at that time generate new basic blocks, so we hide
6732 ;; the loop in this one insn.
6734 (define_insn "prologue_stack_probe_loop"
6735 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r")
6736 (match_operand:DI 1 "register_operand" "r")]
6737 UNSPECV_PSPL)]
6738 ""
6739 {
6740 operands[2] = gen_label_rtx ();
6741 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6742 CODE_LABEL_NUMBER (operands[2]));
6744 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2";
6745 }
6746 [(set_attr "length" "16")
6747 (set_attr "type" "multi")])
6749 (define_expand "prologue"
6750 [(clobber (const_int 0))]
6751 ""
6752 {
6753 alpha_expand_prologue ();
6754 DONE;
6755 })
6757 ;; These take care of emitting the ldgp insn in the prologue. This will be
6758 ;; an lda/ldah pair and we want to align them properly. So we have two
6759 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro
6760 ;; and the second of which emits nothing. However, both are marked as type
6761 ;; IADD (the default) so the alignment code in alpha.c does the right thing
6762 ;; with them.
6764 (define_expand "prologue_ldgp"
6765 [(set (match_dup 0)
6766 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6767 (set (match_dup 0)
6768 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))]
6769 ""
6770 {
6771 operands[0] = pic_offset_table_rtx;
6772 operands[1] = gen_rtx_REG (Pmode, 27);
6773 operands[2] = (TARGET_EXPLICIT_RELOCS
6774 ? GEN_INT (alpha_next_sequence_number++)
6775 : const0_rtx);
6776 })
6778 (define_insn "*ldgp_er_1"
6779 [(set (match_operand:DI 0 "register_operand" "=r")
6780 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6781 (match_operand 2 "const_int_operand" "")]
6782 UNSPECV_LDGP1))]
6783 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6784 "ldah %0,0(%1)\t\t!gpdisp!%2"
6785 [(set_attr "cannot_copy" "true")])
6787 (define_insn "*ldgp_er_2"
6788 [(set (match_operand:DI 0 "register_operand" "=r")
6789 (unspec:DI [(match_operand:DI 1 "register_operand" "r")
6790 (match_operand 2 "const_int_operand" "")]
6791 UNSPEC_LDGP2))]
6792 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6793 "lda %0,0(%1)\t\t!gpdisp!%2"
6794 [(set_attr "cannot_copy" "true")])
6796 (define_insn "*prologue_ldgp_er_2"
6797 [(set (match_operand:DI 0 "register_operand" "=r")
6798 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6799 (match_operand 2 "const_int_operand" "")]
6800 UNSPECV_PLDGP2))]
6801 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
6802 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:"
6803 [(set_attr "cannot_copy" "true")])
6805 (define_insn "*prologue_ldgp_1"
6806 [(set (match_operand:DI 0 "register_operand" "=r")
6807 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6808 (match_operand 2 "const_int_operand" "")]
6809 UNSPECV_LDGP1))]
6810 ""
6811 "ldgp %0,0(%1)\n$%~..ng:"
6812 [(set_attr "cannot_copy" "true")])
6814 (define_insn "*prologue_ldgp_2"
6815 [(set (match_operand:DI 0 "register_operand" "=r")
6816 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")
6817 (match_operand 2 "const_int_operand" "")]
6818 UNSPECV_PLDGP2))]
6819 ""
6820 "")
6822 ;; The _mcount profiling hook has special calling conventions, and
6823 ;; does not clobber all the registers that a normal call would. So
6824 ;; hide the fact this is a call at all.
6826 (define_insn "prologue_mcount"
6827 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)]
6828 ""
6829 {
6830 if (TARGET_EXPLICIT_RELOCS)
6831 /* Note that we cannot use a lituse_jsr reloc, since _mcount
6832 cannot be called via the PLT. */
6833 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount";
6834 else
6835 return "lda $28,_mcount\;jsr $28,($28),_mcount";
6836 }
6837 [(set_attr "type" "multi")
6838 (set_attr "length" "8")])
6840 (define_insn "init_fp"
6841 [(set (match_operand:DI 0 "register_operand" "=r")
6842 (match_operand:DI 1 "register_operand" "r"))
6843 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))]
6844 ""
6845 "bis $31,%1,%0")
6847 (define_expand "epilogue"
6848 [(return)]
6849 ""
6850 {
6851 alpha_expand_epilogue ();
6852 })
6854 (define_expand "sibcall_epilogue"
6855 [(return)]
6856 "TARGET_ABI_OSF"
6857 {
6858 alpha_expand_epilogue ();
6859 DONE;
6860 })
6862 (define_expand "builtin_longjmp"
6863 [(use (match_operand:DI 0 "register_operand" "r"))]
6864 "TARGET_ABI_OSF"
6865 {
6866 /* The elements of the buffer are, in order: */
6867 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6868 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 8));
6869 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 16));
6870 rtx pv = gen_rtx_REG (Pmode, 27);
6872 /* This bit is the same as expand_builtin_longjmp. */
6873 emit_move_insn (hard_frame_pointer_rtx, fp);
6874 emit_move_insn (pv, lab);
6875 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6876 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6877 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6879 /* Load the label we are jumping through into $27 so that we know
6880 where to look for it when we get back to setjmp's function for
6881 restoring the gp. */
6882 emit_jump_insn (gen_builtin_longjmp_internal (pv));
6883 emit_barrier ();
6884 DONE;
6885 })
6887 ;; This is effectively a copy of indirect_jump, but constrained such
6888 ;; that register renaming cannot foil our cunning plan with $27.
6889 (define_insn "builtin_longjmp_internal"
6890 [(set (pc)
6891 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")]
6892 UNSPECV_LONGJMP))]
6893 ""
6894 "jmp $31,(%0),0"
6895 [(set_attr "type" "ibr")])
6897 (define_expand "builtin_setjmp_receiver"
6898 [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)]
6899 "TARGET_ABI_OSF"
6900 "")
6902 (define_insn_and_split "*builtin_setjmp_receiver_1"
6903 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR)]
6904 "TARGET_ABI_OSF"
6905 {
6906 if (TARGET_EXPLICIT_RELOCS)
6907 return "#";
6908 else
6909 return "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)";
6910 }
6911 "&& TARGET_EXPLICIT_RELOCS && reload_completed"
6912 [(set (match_dup 1)
6913 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1))
6914 (set (match_dup 1)
6915 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))]
6916 {
6917 if (prev_nonnote_insn (curr_insn) != XEXP (operands[0], 0))
6918 emit_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, operands[0]),
6919 UNSPECV_SETJMPR_ER));
6920 operands[1] = pic_offset_table_rtx;
6921 operands[2] = gen_rtx_REG (Pmode, 27);
6922 operands[3] = GEN_INT (alpha_next_sequence_number++);
6923 }
6924 [(set_attr "length" "12")
6925 (set_attr "type" "multi")])
6927 (define_insn "*builtin_setjmp_receiver_er_sl_1"
6928 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR_ER)]
6929 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS && TARGET_AS_CAN_SUBTRACT_LABELS"
6930 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:")
6932 (define_insn "*builtin_setjmp_receiver_er_1"
6933 [(unspec_volatile [(match_operand 0 "" "")] UNSPECV_SETJMPR_ER)]
6934 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS"
6935 "br $27,$LSJ%=\n$LSJ%=:"
6936 [(set_attr "type" "ibr")])
6938 (define_expand "exception_receiver"
6939 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)]
6940 "TARGET_ABI_OSF"
6941 {
6942 if (TARGET_LD_BUGGY_LDGP)
6943 operands[0] = alpha_gp_save_rtx ();
6944 else
6945 operands[0] = const0_rtx;
6946 })
6948 (define_insn "*exception_receiver_2"
6949 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)]
6950 "TARGET_ABI_OSF && TARGET_LD_BUGGY_LDGP"
6951 "ldq $29,%0"
6952 [(set_attr "type" "ild")])
6954 (define_insn_and_split "*exception_receiver_1"
6955 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)]
6956 "TARGET_ABI_OSF"
6957 {
6958 if (TARGET_EXPLICIT_RELOCS)
6959 return "ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*";
6960 else
6961 return "ldgp $29,0($26)";
6962 }
6963 "&& TARGET_EXPLICIT_RELOCS && reload_completed"
6964 [(set (match_dup 0)
6965 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1))
6966 (set (match_dup 0)
6967 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))]
6968 {
6969 operands[0] = pic_offset_table_rtx;
6970 operands[1] = gen_rtx_REG (Pmode, 26);
6971 operands[2] = GEN_INT (alpha_next_sequence_number++);
6972 }
6973 [(set_attr "length" "8")
6974 (set_attr "type" "multi")])
6976 (define_expand "nonlocal_goto_receiver"
6977 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6978 (set (reg:DI 27) (mem:DI (reg:DI 29)))
6979 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)
6980 (use (reg:DI 27))]
6981 "TARGET_ABI_OPEN_VMS"
6982 "")
6984 (define_insn "arg_home"
6985 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
6986 (use (reg:DI 1))
6987 (use (reg:DI 25))
6988 (use (reg:DI 16))
6989 (use (reg:DI 17))
6990 (use (reg:DI 18))
6991 (use (reg:DI 19))
6992 (use (reg:DI 20))
6993 (use (reg:DI 21))
6994 (use (reg:DI 48))
6995 (use (reg:DI 49))
6996 (use (reg:DI 50))
6997 (use (reg:DI 51))
6998 (use (reg:DI 52))
6999 (use (reg:DI 53))
7000 (clobber (mem:BLK (const_int 0)))
7001 (clobber (reg:DI 24))
7002 (clobber (reg:DI 25))
7003 (clobber (reg:DI 0))]
7004 "TARGET_ABI_OPEN_VMS"
7005 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS"
7006 [(set_attr "length" "16")
7007 (set_attr "type" "multi")])
7009 ;; Load the CIW into r2 for calling __T3E_MISMATCH
7011 (define_expand "umk_mismatch_args"
7012 [(set:DI (match_dup 1) (mem:DI (plus:DI (reg:DI 15) (const_int -16))))
7013 (set:DI (match_dup 2) (mem:DI (plus:DI (match_dup 1) (const_int -32))))
7014 (set:DI (reg:DI 1) (match_operand:DI 0 "const_int_operand" ""))
7015 (set:DI (match_dup 3) (plus:DI (mult:DI (reg:DI 25)
7016 (const_int 8))
7017 (match_dup 2)))
7018 (set:DI (reg:DI 2) (mem:DI (match_dup 3)))]
7019 "TARGET_ABI_UNICOSMK"
7020 {
7021 operands[1] = gen_reg_rtx (DImode);
7022 operands[2] = gen_reg_rtx (DImode);
7023 operands[3] = gen_reg_rtx (DImode);
7024 })
7026 (define_insn "arg_home_umk"
7027 [(unspec [(const_int 0)] UNSPEC_ARG_HOME)
7028 (use (reg:DI 1))
7029 (use (reg:DI 2))
7030 (use (reg:DI 16))
7031 (use (reg:DI 17))
7032 (use (reg:DI 18))
7033 (use (reg:DI 19))
7034 (use (reg:DI 20))
7035 (use (reg:DI 21))
7036 (use (reg:DI 48))
7037 (use (reg:DI 49))
7038 (use (reg:DI 50))
7039 (use (reg:DI 51))
7040 (use (reg:DI 52))
7041 (use (reg:DI 53))
7042 (clobber (mem:BLK (const_int 0)))
7043 (parallel [
7044 (clobber (reg:DI 22))
7045 (clobber (reg:DI 23))
7046 (clobber (reg:DI 24))
7047 (clobber (reg:DI 0))
7048 (clobber (reg:DI 1))
7049 (clobber (reg:DI 2))
7050 (clobber (reg:DI 3))
7051 (clobber (reg:DI 4))
7052 (clobber (reg:DI 5))
7053 (clobber (reg:DI 6))
7054 (clobber (reg:DI 7))
7055 (clobber (reg:DI 8))])]
7056 "TARGET_ABI_UNICOSMK"
7057 "laum $4,__T3E_MISMATCH($31)\;sll $4,32,$4\;lalm $4,__T3E_MISMATCH($4)\;lal $4,__T3E_MISMATCH($4)\;jsr $3,($4)"
7058 [(set_attr "length" "16")
7059 (set_attr "type" "multi")])
7061 ;; Prefetch data.
7062 ;;
7063 ;; On EV4, these instructions are nops -- no load occurs.
7064 ;;
7065 ;; On EV5, these instructions act as a normal load, and thus can trap
7066 ;; if the address is invalid. The OS may (or may not) handle this in
7067 ;; the entMM fault handler and suppress the fault. If so, then this
7068 ;; has the effect of a read prefetch instruction.
7069 ;;
7070 ;; On EV6, these become official prefetch instructions.
7072 (define_insn "prefetch"
7073 [(prefetch (match_operand:DI 0 "address_operand" "p")
7074 (match_operand:DI 1 "const_int_operand" "n")
7075 (match_operand:DI 2 "const_int_operand" "n"))]
7076 "TARGET_FIXUP_EV5_PREFETCH || alpha_cpu == PROCESSOR_EV6"
7077 {
7078 /* Interpret "no temporal locality" as this data should be evicted once
7079 it is used. The "evict next" alternatives load the data into the cache
7080 and leave the LRU eviction counter pointing to that block. */
7081 static const char * const alt[2][2] = {
7082 {
7083 "ldq $31,%a0", /* read, evict next */
7084 "ldl $31,%a0", /* read, evict last */
7085 },
7086 {
7087 "ldt $f31,%a0", /* write, evict next */
7088 "lds $f31,%a0", /* write, evict last */
7089 }
7090 };
7092 bool write = INTVAL (operands[1]) != 0;
7093 bool lru = INTVAL (operands[2]) != 0;
7095 return alt[write][lru];
7096 }
7097 [(set_attr "type" "ild")])
7099 ;; Close the trap shadow of preceding instructions. This is generated
7100 ;; by alpha_reorg.
7102 (define_insn "trapb"
7103 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)]
7104 ""
7105 "trapb"
7106 [(set_attr "type" "misc")])
7108 ;; No-op instructions used by machine-dependent reorg to preserve
7109 ;; alignment for instruction issue.
7110 ;; The Unicos/Mk assembler does not support these opcodes.
7112 (define_insn "nop"
7113 [(const_int 0)]
7114 ""
7115 "bis $31,$31,$31"
7116 [(set_attr "type" "ilog")])
7118 (define_insn "fnop"
7119 [(const_int 1)]
7120 "TARGET_FP"
7121 "cpys $f31,$f31,$f31"
7122 [(set_attr "type" "fcpys")])
7124 (define_insn "unop"
7125 [(const_int 2)]
7126 ""
7127 "ldq_u $31,0($30)")
7129 ;; On Unicos/Mk we use a macro for aligning code.
7131 (define_insn "realign"
7132 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")]
7133 UNSPECV_REALIGN)]
7134 ""
7135 {
7136 if (TARGET_ABI_UNICOSMK)
7137 return "gcc@code@align %0";
7138 else
7139 return ".align %0 #realign";
7140 })
7141 \f
7142 ;; Instructions to be emitted from __builtins.
7144 (define_insn "builtin_cmpbge"
7145 [(set (match_operand:DI 0 "register_operand" "=r")
7146 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ")
7147 (match_operand:DI 2 "reg_or_8bit_operand" "rI")]
7148 UNSPEC_CMPBGE))]
7149 ""
7150 "cmpbge %r1,%2,%0"
7151 ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't
7152 ;; actually differentiate between ILOG and ICMP in the schedule.
7153 [(set_attr "type" "icmp")])
7155 (define_expand "builtin_extbl"
7156 [(match_operand:DI 0 "register_operand" "")
7157 (match_operand:DI 1 "reg_or_0_operand" "")
7158 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7159 ""
7160 {
7161 rtx (*gen) (rtx, rtx, rtx, rtx);
7162 if (WORDS_BIG_ENDIAN)
7163 gen = gen_extxl_be;
7164 else
7165 gen = gen_extxl_le;
7166 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (8), operands[2]));
7167 DONE;
7168 })
7170 (define_expand "builtin_extwl"
7171 [(match_operand:DI 0 "register_operand" "")
7172 (match_operand:DI 1 "reg_or_0_operand" "")
7173 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7174 ""
7175 {
7176 rtx (*gen) (rtx, rtx, rtx, rtx);
7177 if (WORDS_BIG_ENDIAN)
7178 gen = gen_extxl_be;
7179 else
7180 gen = gen_extxl_le;
7181 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (16), operands[2]));
7182 DONE;
7183 })
7185 (define_expand "builtin_extll"
7186 [(match_operand:DI 0 "register_operand" "")
7187 (match_operand:DI 1 "reg_or_0_operand" "")
7188 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7189 ""
7190 {
7191 rtx (*gen) (rtx, rtx, rtx, rtx);
7192 if (WORDS_BIG_ENDIAN)
7193 gen = gen_extxl_be;
7194 else
7195 gen = gen_extxl_le;
7196 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (32), operands[2]));
7197 DONE;
7198 })
7200 (define_expand "builtin_extql"
7201 [(match_operand:DI 0 "register_operand" "")
7202 (match_operand:DI 1 "reg_or_0_operand" "")
7203 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7204 ""
7205 {
7206 rtx (*gen) (rtx, rtx, rtx, rtx);
7207 if (WORDS_BIG_ENDIAN)
7208 gen = gen_extxl_be;
7209 else
7210 gen = gen_extxl_le;
7211 emit_insn ((*gen) (operands[0], operands[1], GEN_INT (64), operands[2]));
7212 DONE;
7213 })
7215 (define_expand "builtin_extwh"
7216 [(match_operand:DI 0 "register_operand" "")
7217 (match_operand:DI 1 "reg_or_0_operand" "")
7218 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7219 ""
7220 {
7221 rtx (*gen) (rtx, rtx, rtx);
7222 if (WORDS_BIG_ENDIAN)
7223 gen = gen_extwh_be;
7224 else
7225 gen = gen_extwh_le;
7226 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7227 DONE;
7228 })
7230 (define_expand "builtin_extlh"
7231 [(match_operand:DI 0 "register_operand" "")
7232 (match_operand:DI 1 "reg_or_0_operand" "")
7233 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7234 ""
7235 {
7236 rtx (*gen) (rtx, rtx, rtx);
7237 if (WORDS_BIG_ENDIAN)
7238 gen = gen_extlh_be;
7239 else
7240 gen = gen_extlh_le;
7241 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7242 DONE;
7243 })
7245 (define_expand "builtin_extqh"
7246 [(match_operand:DI 0 "register_operand" "")
7247 (match_operand:DI 1 "reg_or_0_operand" "")
7248 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7249 ""
7250 {
7251 rtx (*gen) (rtx, rtx, rtx);
7252 if (WORDS_BIG_ENDIAN)
7253 gen = gen_extqh_be;
7254 else
7255 gen = gen_extqh_le;
7256 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7257 DONE;
7258 })
7260 (define_expand "builtin_insbl"
7261 [(match_operand:DI 0 "register_operand" "")
7262 (match_operand:DI 1 "register_operand" "")
7263 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7264 ""
7265 {
7266 rtx (*gen) (rtx, rtx, rtx);
7267 if (WORDS_BIG_ENDIAN)
7268 gen = gen_insbl_be;
7269 else
7270 gen = gen_insbl_le;
7271 operands[1] = gen_lowpart (QImode, operands[1]);
7272 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7273 DONE;
7274 })
7276 (define_expand "builtin_inswl"
7277 [(match_operand:DI 0 "register_operand" "")
7278 (match_operand:DI 1 "register_operand" "")
7279 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7280 ""
7281 {
7282 rtx (*gen) (rtx, rtx, rtx);
7283 if (WORDS_BIG_ENDIAN)
7284 gen = gen_inswl_be;
7285 else
7286 gen = gen_inswl_le;
7287 operands[1] = gen_lowpart (HImode, operands[1]);
7288 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7289 DONE;
7290 })
7292 (define_expand "builtin_insll"
7293 [(match_operand:DI 0 "register_operand" "")
7294 (match_operand:DI 1 "register_operand" "")
7295 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7296 ""
7297 {
7298 rtx (*gen) (rtx, rtx, rtx);
7299 if (WORDS_BIG_ENDIAN)
7300 gen = gen_insll_be;
7301 else
7302 gen = gen_insll_le;
7303 operands[1] = gen_lowpart (SImode, operands[1]);
7304 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7305 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7306 DONE;
7307 })
7309 (define_expand "builtin_insql"
7310 [(match_operand:DI 0 "register_operand" "")
7311 (match_operand:DI 1 "reg_or_0_operand" "")
7312 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7313 ""
7314 {
7315 rtx (*gen) (rtx, rtx, rtx);
7316 if (WORDS_BIG_ENDIAN)
7317 gen = gen_insql_be;
7318 else
7319 gen = gen_insql_le;
7320 emit_insn ((*gen) (operands[0], operands[1], operands[2]));
7321 DONE;
7322 })
7324 (define_expand "builtin_inswh"
7325 [(match_operand:DI 0 "register_operand" "")
7326 (match_operand:DI 1 "register_operand" "")
7327 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7328 ""
7329 {
7330 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7331 DONE;
7332 })
7334 (define_expand "builtin_inslh"
7335 [(match_operand:DI 0 "register_operand" "")
7336 (match_operand:DI 1 "register_operand" "")
7337 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7338 ""
7339 {
7340 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7341 DONE;
7342 })
7344 (define_expand "builtin_insqh"
7345 [(match_operand:DI 0 "register_operand" "")
7346 (match_operand:DI 1 "register_operand" "")
7347 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7348 ""
7349 {
7350 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7351 DONE;
7352 })
7354 (define_expand "builtin_mskbl"
7355 [(match_operand:DI 0 "register_operand" "")
7356 (match_operand:DI 1 "reg_or_0_operand" "")
7357 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7358 ""
7359 {
7360 rtx (*gen) (rtx, rtx, rtx, rtx);
7361 rtx mask;
7362 if (WORDS_BIG_ENDIAN)
7363 gen = gen_mskxl_be;
7364 else
7365 gen = gen_mskxl_le;
7366 mask = GEN_INT (0xff);
7367 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7368 DONE;
7369 })
7371 (define_expand "builtin_mskwl"
7372 [(match_operand:DI 0 "register_operand" "")
7373 (match_operand:DI 1 "reg_or_0_operand" "")
7374 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7375 ""
7376 {
7377 rtx (*gen) (rtx, rtx, rtx, rtx);
7378 rtx mask;
7379 if (WORDS_BIG_ENDIAN)
7380 gen = gen_mskxl_be;
7381 else
7382 gen = gen_mskxl_le;
7383 mask = GEN_INT (0xffff);
7384 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7385 DONE;
7386 })
7388 (define_expand "builtin_mskll"
7389 [(match_operand:DI 0 "register_operand" "")
7390 (match_operand:DI 1 "reg_or_0_operand" "")
7391 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7392 ""
7393 {
7394 rtx (*gen) (rtx, rtx, rtx, rtx);
7395 rtx mask;
7396 if (WORDS_BIG_ENDIAN)
7397 gen = gen_mskxl_be;
7398 else
7399 gen = gen_mskxl_le;
7400 mask = immed_double_const (0xffffffff, 0, DImode);
7401 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7402 DONE;
7403 })
7405 (define_expand "builtin_mskql"
7406 [(match_operand:DI 0 "register_operand" "")
7407 (match_operand:DI 1 "reg_or_0_operand" "")
7408 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7409 ""
7410 {
7411 rtx (*gen) (rtx, rtx, rtx, rtx);
7412 rtx mask;
7413 if (WORDS_BIG_ENDIAN)
7414 gen = gen_mskxl_be;
7415 else
7416 gen = gen_mskxl_le;
7417 mask = constm1_rtx;
7418 emit_insn ((*gen) (operands[0], operands[1], mask, operands[2]));
7419 DONE;
7420 })
7422 (define_expand "builtin_mskwh"
7423 [(match_operand:DI 0 "register_operand" "")
7424 (match_operand:DI 1 "register_operand" "")
7425 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7426 ""
7427 {
7428 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2]));
7429 DONE;
7430 })
7432 (define_expand "builtin_msklh"
7433 [(match_operand:DI 0 "register_operand" "")
7434 (match_operand:DI 1 "register_operand" "")
7435 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7436 ""
7437 {
7438 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2]));
7439 DONE;
7440 })
7442 (define_expand "builtin_mskqh"
7443 [(match_operand:DI 0 "register_operand" "")
7444 (match_operand:DI 1 "register_operand" "")
7445 (match_operand:DI 2 "reg_or_8bit_operand" "")]
7446 ""
7447 {
7448 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2]));
7449 DONE;
7450 })
7452 (define_expand "builtin_zap"
7453 [(set (match_operand:DI 0 "register_operand" "")
7454 (and:DI (unspec:DI
7455 [(match_operand:DI 2 "reg_or_cint_operand" "")]
7456 UNSPEC_ZAP)
7457 (match_operand:DI 1 "reg_or_cint_operand" "")))]
7458 ""
7459 {
7460 if (GET_CODE (operands[2]) == CONST_INT)
7461 {
7462 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7464 if (mask == const0_rtx)
7465 {
7466 emit_move_insn (operands[0], const0_rtx);
7467 DONE;
7468 }
7469 if (mask == constm1_rtx)
7470 {
7471 emit_move_insn (operands[0], operands[1]);
7472 DONE;
7473 }
7475 operands[1] = force_reg (DImode, operands[1]);
7476 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7477 DONE;
7478 }
7480 operands[1] = force_reg (DImode, operands[1]);
7481 operands[2] = gen_lowpart (QImode, operands[2]);
7482 })
7484 (define_insn "*builtin_zap_1"
7485 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r")
7486 (and:DI (unspec:DI
7487 [(match_operand:QI 2 "reg_or_cint_operand" "n,n,r,r")]
7488 UNSPEC_ZAP)
7489 (match_operand:DI 1 "reg_or_cint_operand" "n,r,J,r")))]
7490 ""
7491 "@
7492 #
7493 #
7494 bis $31,$31,%0
7495 zap %r1,%2,%0"
7496 [(set_attr "type" "shift,shift,ilog,shift")])
7498 (define_split
7499 [(set (match_operand:DI 0 "register_operand" "")
7500 (and:DI (unspec:DI
7501 [(match_operand:QI 2 "const_int_operand" "")]
7502 UNSPEC_ZAP)
7503 (match_operand:DI 1 "const_int_operand" "")))]
7504 ""
7505 [(const_int 0)]
7506 {
7507 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2]));
7508 if (HOST_BITS_PER_WIDE_INT >= 64 || GET_CODE (mask) == CONST_INT)
7509 operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode);
7510 else
7511 {
7512 HOST_WIDE_INT c_lo = INTVAL (operands[1]);
7513 HOST_WIDE_INT c_hi = (c_lo < 0 ? -1 : 0);
7514 operands[1] = immed_double_const (c_lo & CONST_DOUBLE_LOW (mask),
7515 c_hi & CONST_DOUBLE_HIGH (mask),
7516 DImode);
7517 }
7518 emit_move_insn (operands[0], operands[1]);
7519 DONE;
7520 })
7522 (define_split
7523 [(set (match_operand:DI 0 "register_operand" "")
7524 (and:DI (unspec:DI
7525 [(match_operand:QI 2 "const_int_operand" "")]
7526 UNSPEC_ZAP)
7527 (match_operand:DI 1 "register_operand" "")))]
7528 ""
7529 [(set (match_dup 0)
7530 (and:DI (match_dup 1) (match_dup 2)))]
7531 {
7532 operands[2] = alpha_expand_zap_mask (INTVAL (operands[2]));
7533 if (operands[2] == const0_rtx)
7534 {
7535 emit_move_insn (operands[0], const0_rtx);
7536 DONE;
7537 }
7538 if (operands[2] == constm1_rtx)
7539 {
7540 emit_move_insn (operands[0], operands[1]);
7541 DONE;
7542 }
7543 })
7545 (define_expand "builtin_zapnot"
7546 [(set (match_operand:DI 0 "register_operand" "")
7547 (and:DI (unspec:DI
7548 [(not:QI (match_operand:DI 2 "reg_or_cint_operand" ""))]
7549 UNSPEC_ZAP)
7550 (match_operand:DI 1 "reg_or_cint_operand" "")))]
7551 ""
7552 {
7553 if (GET_CODE (operands[2]) == CONST_INT)
7554 {
7555 rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2]));
7557 if (mask == const0_rtx)
7558 {
7559 emit_move_insn (operands[0], const0_rtx);
7560 DONE;
7561 }
7562 if (mask == constm1_rtx)
7563 {
7564 emit_move_insn (operands[0], operands[1]);
7565 DONE;
7566 }
7568 operands[1] = force_reg (DImode, operands[1]);
7569 emit_insn (gen_anddi3 (operands[0], operands[1], mask));
7570 DONE;
7571 }
7573 operands[1] = force_reg (DImode, operands[1]);
7574 operands[2] = gen_lowpart (QImode, operands[2]);
7575 })
7577 (define_insn "*builtin_zapnot_1"
7578 [(set (match_operand:DI 0 "register_operand" "=r")
7579 (and:DI (unspec:DI
7580 [(not:QI (match_operand:QI 2 "register_operand" "r"))]
7581 UNSPEC_ZAP)
7582 (match_operand:DI 1 "reg_or_0_operand" "rJ")))]
7583 ""
7584 "zapnot %r1,%2,%0"
7585 [(set_attr "type" "shift")])
7587 (define_insn "builtin_amask"
7588 [(set (match_operand:DI 0 "register_operand" "=r")
7589 (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")]
7590 UNSPEC_AMASK))]
7591 ""
7592 "amask %1,%0"
7593 [(set_attr "type" "ilog")])
7595 (define_insn "builtin_implver"
7596 [(set (match_operand:DI 0 "register_operand" "=r")
7597 (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))]
7598 ""
7599 "implver %0"
7600 [(set_attr "type" "ilog")])
7602 (define_insn "builtin_rpcc"
7603 [(set (match_operand:DI 0 "register_operand" "=r")
7604 (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))]
7605 ""
7606 "rpcc %0"
7607 [(set_attr "type" "ilog")])
7609 (define_expand "builtin_minub8"
7610 [(match_operand:DI 0 "register_operand" "")
7611 (match_operand:DI 1 "reg_or_0_operand" "")
7612 (match_operand:DI 2 "reg_or_0_operand" "")]
7613 "TARGET_MAX"
7614 {
7615 alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0],
7616 operands[1], operands[2]);
7617 DONE;
7618 })
7620 (define_expand "builtin_minsb8"
7621 [(match_operand:DI 0 "register_operand" "")
7622 (match_operand:DI 1 "reg_or_0_operand" "")
7623 (match_operand:DI 2 "reg_or_0_operand" "")]
7624 "TARGET_MAX"
7625 {
7626 alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0],
7627 operands[1], operands[2]);
7628 DONE;
7629 })
7631 (define_expand "builtin_minuw4"
7632 [(match_operand:DI 0 "register_operand" "")
7633 (match_operand:DI 1 "reg_or_0_operand" "")
7634 (match_operand:DI 2 "reg_or_0_operand" "")]
7635 "TARGET_MAX"
7636 {
7637 alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0],
7638 operands[1], operands[2]);
7639 DONE;
7640 })
7642 (define_expand "builtin_minsw4"
7643 [(match_operand:DI 0 "register_operand" "")
7644 (match_operand:DI 1 "reg_or_0_operand" "")
7645 (match_operand:DI 2 "reg_or_0_operand" "")]
7646 "TARGET_MAX"
7647 {
7648 alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0],
7649 operands[1], operands[2]);
7650 DONE;
7651 })
7653 (define_expand "builtin_maxub8"
7654 [(match_operand:DI 0 "register_operand" "")
7655 (match_operand:DI 1 "reg_or_0_operand" "")
7656 (match_operand:DI 2 "reg_or_0_operand" "")]
7657 "TARGET_MAX"
7658 {
7659 alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0],
7660 operands[1], operands[2]);
7661 DONE;
7662 })
7664 (define_expand "builtin_maxsb8"
7665 [(match_operand:DI 0 "register_operand" "")
7666 (match_operand:DI 1 "reg_or_0_operand" "")
7667 (match_operand:DI 2 "reg_or_0_operand" "")]
7668 "TARGET_MAX"
7669 {
7670 alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0],
7671 operands[1], operands[2]);
7672 DONE;
7673 })
7675 (define_expand "builtin_maxuw4"
7676 [(match_operand:DI 0 "register_operand" "")
7677 (match_operand:DI 1 "reg_or_0_operand" "")
7678 (match_operand:DI 2 "reg_or_0_operand" "")]
7679 "TARGET_MAX"
7680 {
7681 alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0],
7682 operands[1], operands[2]);
7683 DONE;
7684 })
7686 (define_expand "builtin_maxsw4"
7687 [(match_operand:DI 0 "register_operand" "")
7688 (match_operand:DI 1 "reg_or_0_operand" "")
7689 (match_operand:DI 2 "reg_or_0_operand" "")]
7690 "TARGET_MAX"
7691 {
7692 alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0],
7693 operands[1], operands[2]);
7694 DONE;
7695 })
7697 (define_insn "builtin_perr"
7698 [(set (match_operand:DI 0 "register_operand" "=r")
7699 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ")
7700 (match_operand:DI 2 "reg_or_8bit_operand" "rJ")]
7701 UNSPEC_PERR))]
7702 "TARGET_MAX"
7703 "perr %r1,%r2,%0"
7704 [(set_attr "type" "mvi")])
7706 (define_expand "builtin_pklb"
7707 [(set (match_operand:DI 0 "register_operand" "")
7708 (vec_concat:V8QI
7709 (vec_concat:V4QI
7710 (truncate:V2QI (match_operand:DI 1 "register_operand" ""))
7711 (match_dup 2))
7712 (match_dup 3)))]
7713 "TARGET_MAX"
7714 {
7715 operands[0] = gen_lowpart (V8QImode, operands[0]);
7716 operands[1] = gen_lowpart (V2SImode, operands[1]);
7717 operands[2] = CONST0_RTX (V2QImode);
7718 operands[3] = CONST0_RTX (V4QImode);
7719 })
7721 (define_insn "*pklb"
7722 [(set (match_operand:V8QI 0 "register_operand" "=r")
7723 (vec_concat:V8QI
7724 (vec_concat:V4QI
7725 (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r"))
7726 (match_operand:V2QI 2 "const0_operand" ""))
7727 (match_operand:V4QI 3 "const0_operand" "")))]
7728 "TARGET_MAX"
7729 "pklb %r1,%0"
7730 [(set_attr "type" "mvi")])
7732 (define_expand "builtin_pkwb"
7733 [(set (match_operand:DI 0 "register_operand" "")
7734 (vec_concat:V8QI
7735 (truncate:V4QI (match_operand:DI 1 "register_operand" ""))
7736 (match_dup 2)))]
7737 "TARGET_MAX"
7738 {
7739 operands[0] = gen_lowpart (V8QImode, operands[0]);
7740 operands[1] = gen_lowpart (V4HImode, operands[1]);
7741 operands[2] = CONST0_RTX (V4QImode);
7742 })
7744 (define_insn "*pkwb"
7745 [(set (match_operand:V8QI 0 "register_operand" "=r")
7746 (vec_concat:V8QI
7747 (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r"))
7748 (match_operand:V4QI 2 "const0_operand" "")))]
7749 "TARGET_MAX"
7750 "pkwb %r1,%0"
7751 [(set_attr "type" "mvi")])
7753 (define_expand "builtin_unpkbl"
7754 [(set (match_operand:DI 0 "register_operand" "")
7755 (zero_extend:V2SI
7756 (vec_select:V2QI (match_operand:DI 1 "register_operand" "")
7757 (parallel [(const_int 0) (const_int 1)]))))]
7758 "TARGET_MAX"
7759 {
7760 operands[0] = gen_lowpart (V2SImode, operands[0]);
7761 operands[1] = gen_lowpart (V8QImode, operands[1]);
7762 })
7764 (define_insn "*unpkbl"
7765 [(set (match_operand:V2SI 0 "register_operand" "=r")
7766 (zero_extend:V2SI
7767 (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7768 (parallel [(const_int 0) (const_int 1)]))))]
7769 "TARGET_MAX"
7770 "unpkbl %r1,%0"
7771 [(set_attr "type" "mvi")])
7773 (define_expand "builtin_unpkbw"
7774 [(set (match_operand:DI 0 "register_operand" "")
7775 (zero_extend:V4HI
7776 (vec_select:V4QI (match_operand:DI 1 "register_operand" "")
7777 (parallel [(const_int 0)
7778 (const_int 1)
7779 (const_int 2)
7780 (const_int 3)]))))]
7781 "TARGET_MAX"
7782 {
7783 operands[0] = gen_lowpart (V4HImode, operands[0]);
7784 operands[1] = gen_lowpart (V8QImode, operands[1]);
7785 })
7787 (define_insn "*unpkbw"
7788 [(set (match_operand:V4HI 0 "register_operand" "=r")
7789 (zero_extend:V4HI
7790 (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW")
7791 (parallel [(const_int 0)
7792 (const_int 1)
7793 (const_int 2)
7794 (const_int 3)]))))]
7795 "TARGET_MAX"
7796 "unpkbw %r1,%0"
7797 [(set_attr "type" "mvi")])
7798 \f
7799 (include "sync.md")
7800 \f
7801 ;; The call patterns are at the end of the file because their
7802 ;; wildcard operand0 interferes with nice recognition.
7804 (define_insn "*call_value_osf_1_er"
7805 [(set (match_operand 0 "" "")
7806 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7807 (match_operand 2 "" "")))
7808 (use (reg:DI 29))
7809 (clobber (reg:DI 26))]
7810 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7811 "@
7812 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*
7813 bsr $26,%1\t\t!samegp
7814 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*"
7815 [(set_attr "type" "jsr")
7816 (set_attr "length" "12,*,16")])
7818 ;; We must use peep2 instead of a split because we need accurate life
7819 ;; information for $gp. Consider the case of { bar(); while (1); }.
7820 (define_peephole2
7821 [(parallel [(set (match_operand 0 "" "")
7822 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7823 (match_operand 2 "" "")))
7824 (use (reg:DI 29))
7825 (clobber (reg:DI 26))])]
7826 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7827 && ! samegp_function_operand (operands[1], Pmode)
7828 && (peep2_regno_dead_p (1, 29)
7829 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
7830 [(parallel [(set (match_dup 0)
7831 (call (mem:DI (match_dup 3))
7832 (match_dup 2)))
7833 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7834 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7835 (use (match_dup 1))
7836 (use (match_dup 4))])]
7837 {
7838 if (CONSTANT_P (operands[1]))
7839 {
7840 operands[3] = gen_rtx_REG (Pmode, 27);
7841 operands[4] = GEN_INT (alpha_next_sequence_number++);
7842 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7843 operands[1], operands[4]));
7844 }
7845 else
7846 {
7847 operands[3] = operands[1];
7848 operands[1] = const0_rtx;
7849 operands[4] = const0_rtx;
7850 }
7851 })
7853 (define_peephole2
7854 [(parallel [(set (match_operand 0 "" "")
7855 (call (mem:DI (match_operand:DI 1 "call_operand" ""))
7856 (match_operand 2 "" "")))
7857 (use (reg:DI 29))
7858 (clobber (reg:DI 26))])]
7859 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed
7860 && ! samegp_function_operand (operands[1], Pmode)
7861 && ! (peep2_regno_dead_p (1, 29)
7862 || find_reg_note (insn, REG_NORETURN, NULL_RTX))"
7863 [(parallel [(set (match_dup 0)
7864 (call (mem:DI (match_dup 3))
7865 (match_dup 2)))
7866 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7867 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7868 (use (match_dup 1))
7869 (use (match_dup 5))])
7870 (set (reg:DI 29)
7871 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7872 (set (reg:DI 29)
7873 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
7874 {
7875 if (CONSTANT_P (operands[1]))
7876 {
7877 operands[3] = gen_rtx_REG (Pmode, 27);
7878 operands[5] = GEN_INT (alpha_next_sequence_number++);
7879 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx,
7880 operands[1], operands[5]));
7881 }
7882 else
7883 {
7884 operands[3] = operands[1];
7885 operands[1] = const0_rtx;
7886 operands[5] = const0_rtx;
7887 }
7888 operands[4] = GEN_INT (alpha_next_sequence_number++);
7889 })
7891 ;; We add a blockage unspec_volatile to prevent insns from moving down
7892 ;; from above the call to in between the call and the ldah gpdisp.
7893 (define_insn "*call_value_osf_2_er"
7894 [(set (match_operand 0 "" "")
7895 (call (mem:DI (match_operand:DI 1 "register_operand" "c"))
7896 (match_operand 2 "" "")))
7897 (set (reg:DI 26)
7898 (plus:DI (pc) (const_int 4)))
7899 (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE)
7900 (use (match_operand 3 "" ""))
7901 (use (match_operand 4 "" ""))]
7902 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7903 "jsr $26,(%1),%3%J4"
7904 [(set_attr "type" "jsr")
7905 (set_attr "cannot_copy" "true")])
7907 (define_insn "*call_value_osf_1_noreturn"
7908 [(set (match_operand 0 "" "")
7909 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7910 (match_operand 2 "" "")))
7911 (use (reg:DI 29))
7912 (clobber (reg:DI 26))]
7913 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF
7914 && find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7915 "@
7916 jsr $26,($27),0%+
7917 bsr $26,$%1..ng%+
7918 jsr $26,%1%+"
7919 [(set_attr "type" "jsr")
7920 (set_attr "length" "*,*,8")])
7922 (define_insn_and_split "call_value_osf_tlsgd"
7923 [(set (match_operand 0 "" "")
7924 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
7925 (const_int 0)))
7926 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSGD_CALL)
7927 (use (reg:DI 29))
7928 (clobber (reg:DI 26))]
7929 "HAVE_AS_TLS"
7930 "#"
7931 "&& reload_completed"
7932 [(set (match_dup 3)
7933 (unspec:DI [(match_dup 5)
7934 (match_dup 1)
7935 (match_dup 2)] UNSPEC_LITERAL))
7936 (parallel [(set (match_dup 0)
7937 (call (mem:DI (match_dup 3))
7938 (const_int 0)))
7939 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7940 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
7941 (use (match_dup 1))
7942 (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL))])
7943 (set (match_dup 5)
7944 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7945 (set (match_dup 5)
7946 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))]
7947 {
7948 operands[3] = gen_rtx_REG (Pmode, 27);
7949 operands[4] = GEN_INT (alpha_next_sequence_number++);
7950 operands[5] = pic_offset_table_rtx;
7951 }
7952 [(set_attr "type" "multi")])
7954 (define_insn_and_split "call_value_osf_tlsldm"
7955 [(set (match_operand 0 "" "")
7956 (call (mem:DI (match_operand:DI 1 "symbolic_operand" ""))
7957 (const_int 0)))
7958 (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSLDM_CALL)
7959 (use (reg:DI 29))
7960 (clobber (reg:DI 26))]
7961 "HAVE_AS_TLS"
7962 "#"
7963 "&& reload_completed"
7964 [(set (match_dup 3)
7965 (unspec:DI [(match_dup 5)
7966 (match_dup 1)
7967 (match_dup 2)] UNSPEC_LITERAL))
7968 (parallel [(set (match_dup 0)
7969 (call (mem:DI (match_dup 3))
7970 (const_int 0)))
7971 (set (reg:DI 26) (plus:DI (pc) (const_int 4)))
7972 (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE)
7973 (use (match_dup 1))
7974 (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL))])
7975 (set (reg:DI 29)
7976 (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1))
7977 (set (reg:DI 29)
7978 (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))]
7979 {
7980 operands[3] = gen_rtx_REG (Pmode, 27);
7981 operands[4] = GEN_INT (alpha_next_sequence_number++);
7982 operands[5] = pic_offset_table_rtx;
7983 }
7984 [(set_attr "type" "multi")])
7986 (define_insn "*call_value_osf_1"
7987 [(set (match_operand 0 "" "")
7988 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s"))
7989 (match_operand 2 "" "")))
7990 (use (reg:DI 29))
7991 (clobber (reg:DI 26))]
7992 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
7993 "@
7994 jsr $26,($27),0\;ldgp $29,0($26)
7995 bsr $26,$%1..ng
7996 jsr $26,%1\;ldgp $29,0($26)"
7997 [(set_attr "type" "jsr")
7998 (set_attr "length" "12,*,16")])
8000 (define_insn "*sibcall_value_osf_1_er"
8001 [(set (match_operand 0 "" "")
8002 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
8003 (match_operand 2 "" "")))
8004 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
8005 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8006 "@
8007 br $31,%1\t\t!samegp
8008 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#"
8009 [(set_attr "type" "jsr")
8010 (set_attr "length" "*,8")])
8012 (define_insn "*sibcall_value_osf_1"
8013 [(set (match_operand 0 "" "")
8014 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s"))
8015 (match_operand 2 "" "")))
8016 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)]
8017 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF"
8018 "@
8019 br $31,$%1..ng
8020 lda $27,%1\;jmp $31,($27),%1"
8021 [(set_attr "type" "jsr")
8022 (set_attr "length" "*,8")])
8024 (define_insn "*call_value_nt_1"
8025 [(set (match_operand 0 "" "")
8026 (call (mem:DI (match_operand:DI 1 "call_operand" "r,R,s"))
8027 (match_operand 2 "" "")))
8028 (clobber (reg:DI 26))]
8029 "TARGET_ABI_WINDOWS_NT"
8030 "@
8031 jsr $26,(%1)
8032 bsr $26,%1
8033 jsr $26,%1"
8034 [(set_attr "type" "jsr")
8035 (set_attr "length" "*,*,12")])
8037 ; GAS relies on the order and position of instructions output below in order
8038 ; to generate relocs for VMS link to potentially optimize the call.
8039 ; Please do not molest.
8040 (define_insn "*call_value_vms_1"
8041 [(set (match_operand 0 "" "")
8042 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s"))
8043 (match_operand 2 "" "")))
8044 (use (match_operand:DI 3 "nonmemory_operand" "r,n"))
8045 (use (reg:DI 25))
8046 (use (reg:DI 26))
8047 (clobber (reg:DI 27))]
8048 "TARGET_ABI_OPEN_VMS"
8049 {
8050 switch (which_alternative)
8051 {
8052 case 0:
8053 return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)";
8054 case 1:
8055 operands [3] = alpha_use_linkage (operands [1], cfun->decl, 1, 0);
8056 operands [4] = alpha_use_linkage (operands [1], cfun->decl, 0, 0);
8057 return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)";
8058 default:
8059 gcc_unreachable ();
8060 }
8061 }
8062 [(set_attr "type" "jsr")
8063 (set_attr "length" "12,16")])
8065 (define_insn "*call_value_umk"
8066 [(set (match_operand 0 "" "")
8067 (call (mem:DI (match_operand:DI 1 "call_operand" "r"))
8068 (match_operand 2 "" "")))
8069 (use (reg:DI 25))
8070 (clobber (reg:DI 26))]
8071 "TARGET_ABI_UNICOSMK"
8072 "jsr $26,(%1)"
8073 [(set_attr "type" "jsr")])