gcc/config/i386/driver-i386.c

   1 /* Subroutines for the gcc driver.
   2    Copyright (C) 2006, 2007, 2008, 2010, 2011, 2012
   3    Free Software Foundation, Inc.
   4
   5 This file is part of GCC.
   6
   7 GCC is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3, or (at your option)
  10 any later version.
  11
  12 GCC is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with GCC; see the file COPYING3.  If not see
  19 <http://www.gnu.org/licenses/>.  */
  20
  21 #include "config.h"
  22 #include "system.h"
  23 #include "coretypes.h"
  24 #include "tm.h"
  25
  26 const char *host_detect_local_cpu (int argc, const char **argv);
  27
  28 #ifdef __GNUC__
  29 #include "cpuid.h"
  30
  31 struct cache_desc
  32 {
  33   unsigned sizekb;
  34   unsigned assoc;
  35   unsigned line;
  36 };
  37
  38 /* Returns command line parameters that describe size and
  39    cache line size of the processor caches.  */
  40
  41 static char *
  42 describe_cache (struct cache_desc level1, struct cache_desc level2)
  43 {
  44   char size[100], line[100], size2[100];
  45
  46   /* At the moment, gcc does not use the information
  47      about the associativity of the cache.  */
  48
  49   snprintf (size, sizeof (size),
  50             "--param l1-cache-size=%u ", level1.sizekb);
  51   snprintf (line, sizeof (line),
  52             "--param l1-cache-line-size=%u ", level1.line);
  53
  54   snprintf (size2, sizeof (size2),
  55             "--param l2-cache-size=%u ", level2.sizekb);
  56
  57   return concat (size, line, size2, NULL);
  58 }
  59
  60 /* Detect L2 cache parameters using CPUID extended function 0x80000006.  */
  61
  62 static void
  63 detect_l2_cache (struct cache_desc *level2)
  64 {
  65   unsigned eax, ebx, ecx, edx;
  66   unsigned assoc;
  67
  68   __cpuid (0x80000006, eax, ebx, ecx, edx);
  69
  70   level2->sizekb = (ecx >> 16) & 0xffff;
  71   level2->line = ecx & 0xff;
  72
  73   assoc = (ecx >> 12) & 0xf;
  74   if (assoc == 6)
  75     assoc = 8;
  76   else if (assoc == 8)
  77     assoc = 16;
  78   else if (assoc >= 0xa && assoc <= 0xc)
  79     assoc = 32 + (assoc - 0xa) * 16;
  80   else if (assoc >= 0xd && assoc <= 0xe)
  81     assoc = 96 + (assoc - 0xd) * 32;
  82
  83   level2->assoc = assoc;
  84 }
  85
  86 /* Returns the description of caches for an AMD processor.  */
  87
  88 static const char *
  89 detect_caches_amd (unsigned max_ext_level)
  90 {
  91   unsigned eax, ebx, ecx, edx;
  92
  93   struct cache_desc level1, level2 = {0, 0, 0};
  94
  95   if (max_ext_level < 0x80000005)
  96     return "";
  97
  98   __cpuid (0x80000005, eax, ebx, ecx, edx);
  99
 100   level1.sizekb = (ecx >> 24) & 0xff;
 101   level1.assoc = (ecx >> 16) & 0xff;
 102   level1.line = ecx & 0xff;
 103
 104   if (max_ext_level >= 0x80000006)
 105     detect_l2_cache (&level2);
 106
 107   return describe_cache (level1, level2);
 108 }
 109
 110 /* Decodes the size, the associativity and the cache line size of
 111    L1/L2 caches of an Intel processor.  Values are based on
 112    "Intel Processor Identification and the CPUID Instruction"
 113    [Application Note 485], revision -032, December 2007.  */
 114
 115 static void
 116 decode_caches_intel (unsigned reg, bool xeon_mp,
 117                      struct cache_desc *level1, struct cache_desc *level2)
 118 {
 119   int i;
 120
 121   for (i = 24; i >= 0; i -= 8)
 122     switch ((reg >> i) & 0xff)
 123       {
 124       case 0x0a:
 125         level1->sizekb = 8; level1->assoc = 2; level1->line = 32;
 126         break;
 127       case 0x0c:
 128         level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
 129         break;
 130       case 0x2c:
 131         level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
 132         break;
 133       case 0x39:
 134         level2->sizekb = 128; level2->assoc = 4; level2->line = 64;
 135         break;
 136       case 0x3a:
 137         level2->sizekb = 192; level2->assoc = 6; level2->line = 64;
 138         break;
 139       case 0x3b:
 140         level2->sizekb = 128; level2->assoc = 2; level2->line = 64;
 141         break;
 142       case 0x3c:
 143         level2->sizekb = 256; level2->assoc = 4; level2->line = 64;
 144         break;
 145       case 0x3d:
 146         level2->sizekb = 384; level2->assoc = 6; level2->line = 64;
 147         break;
 148       case 0x3e:
 149         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 150         break;
 151       case 0x41:
 152         level2->sizekb = 128; level2->assoc = 4; level2->line = 32;
 153         break;
 154       case 0x42:
 155         level2->sizekb = 256; level2->assoc = 4; level2->line = 32;
 156         break;
 157       case 0x43:
 158         level2->sizekb = 512; level2->assoc = 4; level2->line = 32;
 159         break;
 160       case 0x44:
 161         level2->sizekb = 1024; level2->assoc = 4; level2->line = 32;
 162         break;
 163       case 0x45:
 164         level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
 165         break;
 166       case 0x49:
 167         if (xeon_mp)
 168           break;
 169         level2->sizekb = 4096; level2->assoc = 16; level2->line = 64;
 170         break;
 171       case 0x4e:
 172         level2->sizekb = 6144; level2->assoc = 24; level2->line = 64;
 173         break;
 174       case 0x60:
 175         level1->sizekb = 16; level1->assoc = 8; level1->line = 64;
 176         break;
 177       case 0x66:
 178         level1->sizekb = 8; level1->assoc = 4; level1->line = 64;
 179         break;
 180       case 0x67:
 181         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 182         break;
 183       case 0x68:
 184         level1->sizekb = 32; level1->assoc = 4; level1->line = 64;
 185         break;
 186       case 0x78:
 187         level2->sizekb = 1024; level2->assoc = 4; level2->line = 64;
 188         break;
 189       case 0x79:
 190         level2->sizekb = 128; level2->assoc = 8; level2->line = 64;
 191         break;
 192       case 0x7a:
 193         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 194         break;
 195       case 0x7b:
 196         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 197         break;
 198       case 0x7c:
 199         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 200         break;
 201       case 0x7d:
 202         level2->sizekb = 2048; level2->assoc = 8; level2->line = 64;
 203         break;
 204       case 0x7f:
 205         level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
 206         break;
 207       case 0x82:
 208         level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
 209         break;
 210       case 0x83:
 211         level2->sizekb = 512; level2->assoc = 8; level2->line = 32;
 212         break;
 213       case 0x84:
 214         level2->sizekb = 1024; level2->assoc = 8; level2->line = 32;
 215         break;
 216       case 0x85:
 217         level2->sizekb = 2048; level2->assoc = 8; level2->line = 32;
 218         break;
 219       case 0x86:
 220         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 221         break;
 222       case 0x87:
 223         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 224
 225       default:
 226         break;
 227       }
 228 }
 229
 230 /* Detect cache parameters using CPUID function 2.  */
 231
 232 static void
 233 detect_caches_cpuid2 (bool xeon_mp,
 234                       struct cache_desc *level1, struct cache_desc *level2)
 235 {
 236   unsigned regs[4];
 237   int nreps, i;
 238
 239   __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 240
 241   nreps = regs[0] & 0x0f;
 242   regs[0] &= ~0x0f;
 243
 244   while (--nreps >= 0)
 245     {
 246       for (i = 0; i < 4; i++)
 247         if (regs[i] && !((regs[i] >> 31) & 1))
 248           decode_caches_intel (regs[i], xeon_mp, level1, level2);
 249
 250       if (nreps)
 251         __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 252     }
 253 }
 254
 255 /* Detect cache parameters using CPUID function 4. This
 256    method doesn't require hardcoded tables.  */
 257
 258 enum cache_type
 259 {
 260   CACHE_END = 0,
 261   CACHE_DATA = 1,
 262   CACHE_INST = 2,
 263   CACHE_UNIFIED = 3
 264 };
 265
 266 static void
 267 detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2,
 268                       struct cache_desc *level3)
 269 {
 270   struct cache_desc *cache;
 271
 272   unsigned eax, ebx, ecx, edx;
 273   int count;
 274
 275   for (count = 0;; count++)
 276     {
 277       __cpuid_count(4, count, eax, ebx, ecx, edx);
 278       switch (eax & 0x1f)
 279         {
 280         case CACHE_END:
 281           return;
 282         case CACHE_DATA:
 283         case CACHE_UNIFIED:
 284           {
 285             switch ((eax >> 5) & 0x07)
 286               {
 287               case 1:
 288                 cache = level1;
 289                 break;
 290               case 2:
 291                 cache = level2;
 292                 break;
 293               case 3:
 294                 cache = level3;
 295                 break;
 296               default:
 297                 cache = NULL;
 298               }
 299
 300             if (cache)
 301               {
 302                 unsigned sets = ecx + 1;
 303                 unsigned part = ((ebx >> 12) & 0x03ff) + 1;
 304
 305                 cache->assoc = ((ebx >> 22) & 0x03ff) + 1;
 306                 cache->line = (ebx & 0x0fff) + 1;
 307
 308                 cache->sizekb = (cache->assoc * part
 309                                  * cache->line * sets) / 1024;
 310               }
 311           }
 312         default:
 313           break;
 314         }
 315     }
 316 }
 317
 318 /* Returns the description of caches for an Intel processor.  */
 319
 320 static const char *
 321 detect_caches_intel (bool xeon_mp, unsigned max_level,
 322                      unsigned max_ext_level, unsigned *l2sizekb)
 323 {
 324   struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0};
 325
 326   if (max_level >= 4)
 327     detect_caches_cpuid4 (&level1, &level2, &level3);
 328   else if (max_level >= 2)
 329     detect_caches_cpuid2 (xeon_mp, &level1, &level2);
 330   else
 331     return "";
 332
 333   if (level1.sizekb == 0)
 334     return "";
 335
 336   /* Let the L3 replace the L2. This assumes inclusive caches
 337      and single threaded program for now. */
 338   if (level3.sizekb)
 339     level2 = level3;
 340
 341   /* Intel CPUs are equipped with AMD style L2 cache info.  Try this
 342      method if other methods fail to provide L2 cache parameters.  */
 343   if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
 344     detect_l2_cache (&level2);
 345
 346   *l2sizekb = level2.sizekb;
 347
 348   return describe_cache (level1, level2);
 349 }
 350
 351 /* This will be called by the spec parser in gcc.c when it sees
 352    a %:local_cpu_detect(args) construct.  Currently it will be called
 353    with either "arch" or "tune" as argument depending on if -march=native
 354    or -mtune=native is to be substituted.
 355
 356    It returns a string containing new command line parameters to be
 357    put at the place of the above two options, depending on what CPU
 358    this is executed.  E.g. "-march=k8" on an AMD64 machine
 359    for -march=native.
 360
 361    ARGC and ARGV are set depending on the actual arguments given
 362    in the spec.  */
 363
 364 const char *host_detect_local_cpu (int argc, const char **argv)
 365 {
 366   enum processor_type processor = PROCESSOR_I386;
 367   const char *cpu = "i386";
 368
 369   const char *cache = "";
 370   const char *options = "";
 371
 372   unsigned int eax, ebx, ecx, edx;
 373
 374   unsigned int max_level, ext_level;
 375
 376   unsigned int vendor;
 377   unsigned int model, family;
 378
 379   unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
 380   unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;
 381
 382   /* Extended features */
 383   unsigned int has_lahf_lm = 0, has_sse4a = 0;
 384   unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
 385   unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
 386   unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0, has_avx2 = 0;
 387   unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
 388   unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0;
 389   unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
 390   unsigned int has_hle = 0, has_rtm = 0;
 391   unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
 392   unsigned int has_rdseed = 0, has_prfchw = 0, has_adx = 0;
 393
 394   bool arch;
 395
 396   unsigned int l2sizekb = 0;
 397
 398   if (argc < 1)
 399     return NULL;
 400
 401   arch = !strcmp (argv[0], "arch");
 402
 403   if (!arch && strcmp (argv[0], "tune"))
 404     return NULL;
 405
 406   max_level = __get_cpuid_max (0, &vendor);
 407   if (max_level < 1)
 408     goto done;
 409
 410   __cpuid (1, eax, ebx, ecx, edx);
 411
 412   model = (eax >> 4) & 0x0f;
 413   family = (eax >> 8) & 0x0f;
 414   if (vendor == signature_INTEL_ebx)
 415     {
 416       unsigned int extended_model, extended_family;
 417
 418       extended_model = (eax >> 12) & 0xf0;
 419       extended_family = (eax >> 20) & 0xff;
 420       if (family == 0x0f)
 421         {
 422           family += extended_family;
 423           model += extended_model;
 424         }
 425       else if (family == 0x06)
 426         model += extended_model;
 427     }
 428
 429   has_sse3 = ecx & bit_SSE3;
 430   has_ssse3 = ecx & bit_SSSE3;
 431   has_sse4_1 = ecx & bit_SSE4_1;
 432   has_sse4_2 = ecx & bit_SSE4_2;
 433   has_avx = ecx & bit_AVX;
 434   has_cmpxchg16b = ecx & bit_CMPXCHG16B;
 435   has_movbe = ecx & bit_MOVBE;
 436   has_popcnt = ecx & bit_POPCNT;
 437   has_aes = ecx & bit_AES;
 438   has_pclmul = ecx & bit_PCLMUL;
 439   has_fma = ecx & bit_FMA;
 440   has_f16c = ecx & bit_F16C;
 441   has_rdrnd = ecx & bit_RDRND;
 442
 443   has_cmpxchg8b = edx & bit_CMPXCHG8B;
 444   has_cmov = edx & bit_CMOV;
 445   has_mmx = edx & bit_MMX;
 446   has_sse = edx & bit_SSE;
 447   has_sse2 = edx & bit_SSE2;
 448
 449   if (max_level >= 7)
 450     {
 451       __cpuid_count (7, 0, eax, ebx, ecx, edx);
 452
 453       has_bmi = ebx & bit_BMI;
 454       has_hle = ebx & bit_HLE;
 455       has_rtm = ebx & bit_RTM;
 456       has_avx2 = ebx & bit_AVX2;
 457       has_bmi2 = ebx & bit_BMI2;
 458       has_fsgsbase = ebx & bit_FSGSBASE;
 459       has_rdseed = ebx & bit_RDSEED;
 460       has_adx = ebx & bit_ADX;
 461     }
 462
 463   /* Check cpuid level of extended features.  */
 464   __cpuid (0x80000000, ext_level, ebx, ecx, edx);
 465
 466   if (ext_level > 0x80000000)
 467     {
 468       __cpuid (0x80000001, eax, ebx, ecx, edx);
 469
 470       has_lahf_lm = ecx & bit_LAHF_LM;
 471       has_sse4a = ecx & bit_SSE4a;
 472       has_abm = ecx & bit_ABM;
 473       has_lwp = ecx & bit_LWP;
 474       has_fma4 = ecx & bit_FMA4;
 475       has_xop = ecx & bit_XOP;
 476       has_tbm = ecx & bit_TBM;
 477       has_lzcnt = ecx & bit_LZCNT;
 478       has_prfchw = ecx & bit_PRFCHW;
 479
 480       has_longmode = edx & bit_LM;
 481       has_3dnowp = edx & bit_3DNOWP;
 482       has_3dnow = edx & bit_3DNOW;
 483     }
 484
 485   if (!arch)
 486     {
 487       if (vendor == signature_AMD_ebx)
 488         cache = detect_caches_amd (ext_level);
 489       else if (vendor == signature_INTEL_ebx)
 490         {
 491           bool xeon_mp = (family == 15 && model == 6);
 492           cache = detect_caches_intel (xeon_mp, max_level,
 493                                        ext_level, &l2sizekb);
 494         }
 495     }
 496
 497   if (vendor == signature_AMD_ebx)
 498     {
 499       unsigned int name;
 500
 501       /* Detect geode processor by its processor signature.  */
 502       if (ext_level > 0x80000001)
 503         __cpuid (0x80000002, name, ebx, ecx, edx);
 504       else
 505         name = 0;
 506
 507       if (name == signature_NSC_ebx)
 508         processor = PROCESSOR_GEODE;
 509       else if (has_movbe)
 510         processor = PROCESSOR_BTVER2;
 511       else if (has_bmi)
 512         processor = PROCESSOR_BDVER2;
 513       else if (has_xop)
 514         processor = PROCESSOR_BDVER1;
 515       else if (has_sse4a && has_ssse3)
 516         processor = PROCESSOR_BTVER1;
 517       else if (has_sse4a)
 518         processor = PROCESSOR_AMDFAM10;
 519       else if (has_sse2 || has_longmode)
 520         processor = PROCESSOR_K8;
 521       else if (has_3dnowp && family == 6)
 522         processor = PROCESSOR_ATHLON;
 523       else if (has_mmx)
 524         processor = PROCESSOR_K6;
 525       else
 526         processor = PROCESSOR_PENTIUM;
 527     }
 528   else
 529     {
 530       switch (family)
 531         {
 532         case 4:
 533           processor = PROCESSOR_I486;
 534           break;
 535         case 5:
 536           processor = PROCESSOR_PENTIUM;
 537           break;
 538         case 6:
 539           processor = PROCESSOR_PENTIUMPRO;
 540           break;
 541         case 15:
 542           processor = PROCESSOR_PENTIUM4;
 543           break;
 544         default:
 545           /* We have no idea.  */
 546           processor = PROCESSOR_GENERIC32;
 547         }
 548     }
 549
 550   switch (processor)
 551     {
 552     case PROCESSOR_I386:
 553       /* Default.  */
 554       break;
 555     case PROCESSOR_I486:
 556       cpu = "i486";
 557       break;
 558     case PROCESSOR_PENTIUM:
 559       if (arch && has_mmx)
 560         cpu = "pentium-mmx";
 561       else
 562         cpu = "pentium";
 563       break;
 564     case PROCESSOR_PENTIUMPRO:
 565       switch (model)
 566         {
 567         case 0x1c:
 568         case 0x26:
 569           /* Atom.  */
 570           cpu = "atom";
 571           break;
 572         case 0x1a:
 573         case 0x1e:
 574         case 0x1f:
 575         case 0x2e:
 576           /* Nehalem.  */
 577           cpu = "corei7";
 578           break;
 579         case 0x25:
 580         case 0x2c:
 581         case 0x2f:
 582           /* Westmere.  */
 583           cpu = "corei7";
 584           break;
 585         case 0x2a:
 586         case 0x2d:
 587           /* Sandy Bridge.  */
 588           cpu = "corei7-avx";
 589           break;
 590         case 0x17:
 591         case 0x1d:
 592           /* Penryn.  */
 593           cpu = "core2";
 594           break;
 595         case 0x0f:
 596           /* Merom.  */
 597           cpu = "core2";
 598           break;
 599         default:
 600           if (arch)
 601             {
 602               /* This is unknown family 0x6 CPU.  */
 603               if (has_avx)
 604                 /* Assume Sandy Bridge.  */
 605                 cpu = "corei7-avx";
 606               else if (has_sse4_2)
 607                 /* Assume Core i7.  */
 608                 cpu = "corei7";
 609               else if (has_ssse3)
 610                 {
 611                   if (has_movbe)
 612                     /* Assume Atom.  */
 613                     cpu = "atom";
 614                   else
 615                     /* Assume Core 2.  */
 616                     cpu = "core2";
 617                 }
 618               else if (has_sse3)
 619                 /* It is Core Duo.  */
 620                 cpu = "pentium-m";
 621               else if (has_sse2)
 622                 /* It is Pentium M.  */
 623                 cpu = "pentium-m";
 624               else if (has_sse)
 625                 /* It is Pentium III.  */
 626                 cpu = "pentium3";
 627               else if (has_mmx)
 628                 /* It is Pentium II.  */
 629                 cpu = "pentium2";
 630               else
 631                 /* Default to Pentium Pro.  */
 632                 cpu = "pentiumpro";
 633             }
 634           else
 635             /* For -mtune, we default to -mtune=generic.  */
 636             cpu = "generic";
 637           break;
 638         }
 639       break;
 640     case PROCESSOR_PENTIUM4:
 641       if (has_sse3)
 642         {
 643           if (has_longmode)
 644             cpu = "nocona";
 645           else
 646             cpu = "prescott";
 647         }
 648       else
 649         cpu = "pentium4";
 650       break;
 651     case PROCESSOR_GEODE:
 652       cpu = "geode";
 653       break;
 654     case PROCESSOR_K6:
 655       if (arch && has_3dnow)
 656         cpu = "k6-3";
 657       else
 658         cpu = "k6";
 659       break;
 660     case PROCESSOR_ATHLON:
 661       if (arch && has_sse)
 662         cpu = "athlon-4";
 663       else
 664         cpu = "athlon";
 665       break;
 666     case PROCESSOR_K8:
 667       if (arch && has_sse3)
 668         cpu = "k8-sse3";
 669       else
 670         cpu = "k8";
 671       break;
 672     case PROCESSOR_AMDFAM10:
 673       cpu = "amdfam10";
 674       break;
 675     case PROCESSOR_BDVER1:
 676       cpu = "bdver1";
 677       break;
 678     case PROCESSOR_BDVER2:
 679       cpu = "bdver2";
 680       break;
 681     case PROCESSOR_BTVER1:
 682       cpu = "btver1";
 683       break;
 684     case PROCESSOR_BTVER2:
 685       cpu = "btver2";
 686       break;
 687
 688     default:
 689       /* Use something reasonable.  */
 690       if (arch)
 691         {
 692           if (has_ssse3)
 693             cpu = "core2";
 694           else if (has_sse3)
 695             {
 696               if (has_longmode)
 697                 cpu = "nocona";
 698               else
 699                 cpu = "prescott";
 700             }
 701           else if (has_sse2)
 702             cpu = "pentium4";
 703           else if (has_cmov)
 704             cpu = "pentiumpro";
 705           else if (has_mmx)
 706             cpu = "pentium-mmx";
 707           else if (has_cmpxchg8b)
 708             cpu = "pentium";
 709         }
 710       else
 711         cpu = "generic";
 712     }
 713
 714   if (arch)
 715     {
 716       const char *cx16 = has_cmpxchg16b ? " -mcx16" : " -mno-cx16";
 717       const char *sahf = has_lahf_lm ? " -msahf" : " -mno-sahf";
 718       const char *movbe = has_movbe ? " -mmovbe" : " -mno-movbe";
 719       const char *ase = has_aes ? " -maes" : " -mno-aes";
 720       const char *pclmul = has_pclmul ? " -mpclmul" : " -mno-pclmul";
 721       const char *popcnt = has_popcnt ? " -mpopcnt" : " -mno-popcnt";
 722       const char *abm = has_abm ? " -mabm" : " -mno-abm";
 723       const char *lwp = has_lwp ? " -mlwp" : " -mno-lwp";
 724       const char *fma = has_fma ? " -mfma" : " -mno-fma";
 725       const char *fma4 = has_fma4 ? " -mfma4" : " -mno-fma4";
 726       const char *xop = has_xop ? " -mxop" : " -mno-xop";
 727       const char *bmi = has_bmi ? " -mbmi" : " -mno-bmi";
 728       const char *bmi2 = has_bmi2 ? " -mbmi2" : " -mno-bmi2";
 729       const char *tbm = has_tbm ? " -mtbm" : " -mno-tbm";
 730       const char *avx = has_avx ? " -mavx" : " -mno-avx";
 731       const char *avx2 = has_avx2 ? " -mavx2" : " -mno-avx2";
 732       const char *sse4_2 = has_sse4_2 ? " -msse4.2" : " -mno-sse4.2";
 733       const char *sse4_1 = has_sse4_1 ? " -msse4.1" : " -mno-sse4.1";
 734       const char *lzcnt = has_lzcnt ? " -mlzcnt" : " -mno-lzcnt";
 735       const char *hle = has_hle ? " -mhle" : " -mno-hle";
 736       const char *rtm = has_rtm ? " -mrtm" : " -mno-rtm";
 737       const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd";
 738       const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c";
 739       const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase";
 740       const char *rdseed = has_rdseed ? " -mrdseed" : " -mno-rdseed";
 741       const char *prfchw = has_prfchw ? " -mprfchw" : " -mno-prfchw";
 742       const char *adx = has_adx ? " -madx" : " -mno-adx";
 743
 744       options = concat (options, cx16, sahf, movbe, ase, pclmul,
 745                         popcnt, abm, lwp, fma, fma4, xop, bmi, bmi2,
 746                         tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm,
 747                         hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx, NULL);
 748     }
 749
 750 done:
 751   return concat (cache, "-m", argv[0], "=", cpu, options, NULL);
 752 }
 753 #else
 754
 755 /* If we aren't compiling with GCC then the driver will just ignore
 756    -march and -mtune "native" target and will leave to the newly
 757    built compiler to generate code for its default target.  */
 758
 759 const char *host_detect_local_cpu (int argc ATTRIBUTE_UNUSED,
 760                                    const char **argv ATTRIBUTE_UNUSED)
 761 {
 762   return NULL;
 763 }
 764 #endif /* __GNUC__ */