| blob | 81117914ff530d6bf200e31f3ab7d1608b4d37b1 |
1 ;; Patterns for the Intel Wireless MMX technology architecture.
2 ;; Copyright (C) 2003, 2004, 2005, 2007, 2008, 2010, 2012
3 ;; Free Software Foundation, Inc.
4 ;; Contributed by Red Hat.
6 ;; This file is part of GCC.
8 ;; GCC is free software; you can redistribute it and/or modify it under
9 ;; the terms of the GNU General Public License as published by the Free
10 ;; Software Foundation; either version 3, or (at your option) any later
11 ;; version.
13 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
14 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 ;; License for more details.
18 ;; You should have received a copy of the GNU General Public License
19 ;; along with GCC; see the file COPYING3. If not see
20 ;; <http://www.gnu.org/licenses/>.
22 ;; Register numbers
23 (define_constants
24 [(WCGR0 43)
25 (WCGR1 44)
26 (WCGR2 45)
27 (WCGR3 46)
28 ]
29 )
31 (define_insn "tbcstv8qi"
32 [(set (match_operand:V8QI 0 "register_operand" "=y")
33 (vec_duplicate:V8QI (match_operand:QI 1 "s_register_operand" "r")))]
34 "TARGET_REALLY_IWMMXT"
35 "tbcstb%?\\t%0, %1"
36 [(set_attr "predicable" "yes")
37 (set_attr "wtype" "tbcst")]
38 )
40 (define_insn "tbcstv4hi"
41 [(set (match_operand:V4HI 0 "register_operand" "=y")
42 (vec_duplicate:V4HI (match_operand:HI 1 "s_register_operand" "r")))]
43 "TARGET_REALLY_IWMMXT"
44 "tbcsth%?\\t%0, %1"
45 [(set_attr "predicable" "yes")
46 (set_attr "wtype" "tbcst")]
47 )
49 (define_insn "tbcstv2si"
50 [(set (match_operand:V2SI 0 "register_operand" "=y")
51 (vec_duplicate:V2SI (match_operand:SI 1 "s_register_operand" "r")))]
52 "TARGET_REALLY_IWMMXT"
53 "tbcstw%?\\t%0, %1"
54 [(set_attr "predicable" "yes")
55 (set_attr "wtype" "tbcst")]
56 )
58 (define_insn "iwmmxt_iordi3"
59 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r")
60 (ior:DI (match_operand:DI 1 "register_operand" "%y,0,r")
61 (match_operand:DI 2 "register_operand" "y,r,r")))]
62 "TARGET_REALLY_IWMMXT"
63 "@
64 wor%?\\t%0, %1, %2
65 #
66 #"
67 [(set_attr "predicable" "yes")
68 (set_attr "length" "4,8,8")
69 (set_attr "wtype" "wor,none,none")]
70 )
72 (define_insn "iwmmxt_xordi3"
73 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r")
74 (xor:DI (match_operand:DI 1 "register_operand" "%y,0,r")
75 (match_operand:DI 2 "register_operand" "y,r,r")))]
76 "TARGET_REALLY_IWMMXT"
77 "@
78 wxor%?\\t%0, %1, %2
79 #
80 #"
81 [(set_attr "predicable" "yes")
82 (set_attr "length" "4,8,8")
83 (set_attr "wtype" "wxor,none,none")]
84 )
86 (define_insn "iwmmxt_anddi3"
87 [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r")
88 (and:DI (match_operand:DI 1 "register_operand" "%y,0,r")
89 (match_operand:DI 2 "register_operand" "y,r,r")))]
90 "TARGET_REALLY_IWMMXT"
91 "@
92 wand%?\\t%0, %1, %2
93 #
94 #"
95 [(set_attr "predicable" "yes")
96 (set_attr "length" "4,8,8")
97 (set_attr "wtype" "wand,none,none")]
98 )
100 (define_insn "iwmmxt_nanddi3"
101 [(set (match_operand:DI 0 "register_operand" "=y")
102 (and:DI (match_operand:DI 1 "register_operand" "y")
103 (not:DI (match_operand:DI 2 "register_operand" "y"))))]
104 "TARGET_REALLY_IWMMXT"
105 "wandn%?\\t%0, %1, %2"
106 [(set_attr "predicable" "yes")
107 (set_attr "wtype" "wandn")]
108 )
110 (define_insn "*iwmmxt_arm_movdi"
111 [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, r, r, m,y,y,yr,y,yrUy,*w, r,*w,*w, *Uv")
112 (match_operand:DI 1 "di_operand" "rDa,Db,Dc,mi,r,y,yr,y,yrUy,y, r,*w,*w,*Uvi,*w"))]
113 "TARGET_REALLY_IWMMXT
114 && ( register_operand (operands[0], DImode)
115 || register_operand (operands[1], DImode))"
116 "*
117 switch (which_alternative)
118 {
119 case 0:
120 case 1:
121 case 2:
122 return \"#\";
123 case 3: case 4:
124 return output_move_double (operands, true, NULL);
125 case 5:
126 return \"wmov%?\\t%0,%1\";
127 case 6:
128 return \"tmcrr%?\\t%0,%Q1,%R1\";
129 case 7:
130 return \"tmrrc%?\\t%Q0,%R0,%1\";
131 case 8:
132 return \"wldrd%?\\t%0,%1\";
133 case 9:
134 return \"wstrd%?\\t%1,%0\";
135 case 10:
136 return \"fmdrr%?\\t%P0, %Q1, %R1\\t%@ int\";
137 case 11:
138 return \"fmrrd%?\\t%Q0, %R0, %P1\\t%@ int\";
139 case 12:
140 if (TARGET_VFP_SINGLE)
141 return \"fcpys%?\\t%0, %1\\t%@ int\;fcpys%?\\t%p0, %p1\\t%@ int\";
142 else
143 return \"fcpyd%?\\t%P0, %P1\\t%@ int\";
144 case 13: case 14:
145 return output_move_vfp (operands);
146 default:
147 gcc_unreachable ();
148 }
149 "
150 [(set (attr "length") (cond [(eq_attr "alternative" "0,3,4") (const_int 8)
151 (eq_attr "alternative" "1") (const_int 12)
152 (eq_attr "alternative" "2") (const_int 16)
153 (eq_attr "alternative" "12")
154 (if_then_else
155 (eq (symbol_ref "TARGET_VFP_SINGLE") (const_int 1))
156 (const_int 8)
157 (const_int 4))]
158 (const_int 4)))
159 (set_attr "type" "*,*,*,load2,store2,*,*,*,*,*,r_2_f,f_2_r,ffarithd,f_loadd,f_stored")
160 (set_attr "arm_pool_range" "*,*,*,1020,*,*,*,*,*,*,*,*,*,1020,*")
161 (set_attr "arm_neg_pool_range" "*,*,*,1008,*,*,*,*,*,*,*,*,*,1008,*")
162 (set_attr "wtype" "*,*,*,*,*,wmov,tmcrr,tmrrc,wldr,wstr,*,*,*,*,*")]
163 )
165 (define_insn "*iwmmxt_movsi_insn"
166 [(set (match_operand:SI 0 "nonimmediate_operand" "=rk,r,r,r,rk, m,z,r,?z,?Uy,*t, r,*t,*t ,*Uv")
167 (match_operand:SI 1 "general_operand" " rk,I,K,j,mi,rk,r,z,Uy, z, r,*t,*t,*Uvi, *t"))]
168 "TARGET_REALLY_IWMMXT
169 && ( register_operand (operands[0], SImode)
170 || register_operand (operands[1], SImode))"
171 "*
172 switch (which_alternative)
173 {
174 case 0: return \"mov\\t%0, %1\";
175 case 1: return \"mov\\t%0, %1\";
176 case 2: return \"mvn\\t%0, #%B1\";
177 case 3: return \"movw\\t%0, %1\";
178 case 4: return \"ldr\\t%0, %1\";
179 case 5: return \"str\\t%1, %0\";
180 case 6: return \"tmcr\\t%0, %1\";
181 case 7: return \"tmrc\\t%0, %1\";
182 case 8: return arm_output_load_gr (operands);
183 case 9: return \"wstrw\\t%1, %0\";
184 case 10:return \"fmsr\\t%0, %1\";
185 case 11:return \"fmrs\\t%0, %1\";
186 case 12:return \"fcpys\\t%0, %1\\t%@ int\";
187 case 13: case 14:
188 return output_move_vfp (operands);
189 default:
190 gcc_unreachable ();
191 }"
192 [(set_attr "type" "*,*,*,*,load1,store1,*,*,*,*,r_2_f,f_2_r,fcpys,f_loads,f_stores")
193 (set_attr "length" "*,*,*,*,*, *,*,*, 16, *,*,*,*,*,*")
194 (set_attr "pool_range" "*,*,*,*,4096, *,*,*,1024, *,*,*,*,1020,*")
195 (set_attr "neg_pool_range" "*,*,*,*,4084, *,*,*, *, 1012,*,*,*,1008,*")
196 ;; Note - the "predicable" attribute is not allowed to have alternatives.
197 ;; Since the wSTRw wCx instruction is not predicable, we cannot support
198 ;; predicating any of the alternatives in this template. Instead,
199 ;; we do the predication ourselves, in cond_iwmmxt_movsi_insn.
200 (set_attr "predicable" "no")
201 ;; Also - we have to pretend that these insns clobber the condition code
202 ;; bits as otherwise arm_final_prescan_insn() will try to conditionalize
203 ;; them.
204 (set_attr "conds" "clob")
205 (set_attr "wtype" "*,*,*,*,*,*,tmcr,tmrc,wldr,wstr,*,*,*,*,*")]
206 )
208 ;; Because iwmmxt_movsi_insn is not predicable, we provide the
209 ;; cond_exec version explicitly, with appropriate constraints.
211 (define_insn "*cond_iwmmxt_movsi_insn"
212 [(cond_exec
213 (match_operator 2 "arm_comparison_operator"
214 [(match_operand 3 "cc_register" "")
215 (const_int 0)])
216 (set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r")
217 (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,z")))]
218 "TARGET_REALLY_IWMMXT
219 && ( register_operand (operands[0], SImode)
220 || register_operand (operands[1], SImode))"
221 "*
222 switch (which_alternative)
223 {
224 case 0: return \"mov%?\\t%0, %1\";
225 case 1: return \"mvn%?\\t%0, #%B1\";
226 case 2: return \"ldr%?\\t%0, %1\";
227 case 3: return \"str%?\\t%1, %0\";
228 case 4: return \"tmcr%?\\t%0, %1\";
229 default: return \"tmrc%?\\t%0, %1\";
230 }"
231 [(set_attr "type" "*,*,load1,store1,*,*")
232 (set_attr "pool_range" "*,*,4096, *,*,*")
233 (set_attr "neg_pool_range" "*,*,4084, *,*,*")]
234 )
236 (define_insn "mov<mode>_internal"
237 [(set (match_operand:VMMX 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r,?r,?m")
238 (match_operand:VMMX 1 "general_operand" "y,y,mi,y,r,r,mi,r"))]
239 "TARGET_REALLY_IWMMXT"
240 "*
241 switch (which_alternative)
242 {
243 case 0: return \"wmov%?\\t%0, %1\";
244 case 1: return \"wstrd%?\\t%1, %0\";
245 case 2: return \"wldrd%?\\t%0, %1\";
246 case 3: return \"tmrrc%?\\t%Q0, %R0, %1\";
247 case 4: return \"tmcrr%?\\t%0, %Q1, %R1\";
248 case 5: return \"#\";
249 default: return output_move_double (operands, true, NULL);
250 }"
251 [(set_attr "predicable" "yes")
252 (set_attr "length" "4, 4, 4,4,4,8, 8,8")
253 (set_attr "type" "*,*,*,*,*,*,load1,store1")
254 (set_attr "pool_range" "*, *, 256,*,*,*, 256,*")
255 (set_attr "neg_pool_range" "*, *, 244,*,*,*, 244,*")
256 (set_attr "wtype" "wmov,wstr,wldr,tmrrc,tmcrr,*,*,*")]
257 )
259 (define_expand "iwmmxt_setwcgr0"
260 [(set (reg:SI WCGR0)
261 (match_operand:SI 0 "register_operand" ""))]
262 "TARGET_REALLY_IWMMXT"
263 {}
264 )
266 (define_expand "iwmmxt_setwcgr1"
267 [(set (reg:SI WCGR1)
268 (match_operand:SI 0 "register_operand" ""))]
269 "TARGET_REALLY_IWMMXT"
270 {}
271 )
273 (define_expand "iwmmxt_setwcgr2"
274 [(set (reg:SI WCGR2)
275 (match_operand:SI 0 "register_operand" ""))]
276 "TARGET_REALLY_IWMMXT"
277 {}
278 )
280 (define_expand "iwmmxt_setwcgr3"
281 [(set (reg:SI WCGR3)
282 (match_operand:SI 0 "register_operand" ""))]
283 "TARGET_REALLY_IWMMXT"
284 {}
285 )
287 (define_expand "iwmmxt_getwcgr0"
288 [(set (match_operand:SI 0 "register_operand" "")
289 (reg:SI WCGR0))]
290 "TARGET_REALLY_IWMMXT"
291 {}
292 )
294 (define_expand "iwmmxt_getwcgr1"
295 [(set (match_operand:SI 0 "register_operand" "")
296 (reg:SI WCGR1))]
297 "TARGET_REALLY_IWMMXT"
298 {}
299 )
301 (define_expand "iwmmxt_getwcgr2"
302 [(set (match_operand:SI 0 "register_operand" "")
303 (reg:SI WCGR2))]
304 "TARGET_REALLY_IWMMXT"
305 {}
306 )
308 (define_expand "iwmmxt_getwcgr3"
309 [(set (match_operand:SI 0 "register_operand" "")
310 (reg:SI WCGR3))]
311 "TARGET_REALLY_IWMMXT"
312 {}
313 )
315 (define_insn "*and<mode>3_iwmmxt"
316 [(set (match_operand:VMMX 0 "register_operand" "=y")
317 (and:VMMX (match_operand:VMMX 1 "register_operand" "y")
318 (match_operand:VMMX 2 "register_operand" "y")))]
319 "TARGET_REALLY_IWMMXT"
320 "wand\\t%0, %1, %2"
321 [(set_attr "predicable" "yes")
322 (set_attr "wtype" "wand")]
323 )
325 (define_insn "*ior<mode>3_iwmmxt"
326 [(set (match_operand:VMMX 0 "register_operand" "=y")
327 (ior:VMMX (match_operand:VMMX 1 "register_operand" "y")
328 (match_operand:VMMX 2 "register_operand" "y")))]
329 "TARGET_REALLY_IWMMXT"
330 "wor\\t%0, %1, %2"
331 [(set_attr "predicable" "yes")
332 (set_attr "wtype" "wor")]
333 )
335 (define_insn "*xor<mode>3_iwmmxt"
336 [(set (match_operand:VMMX 0 "register_operand" "=y")
337 (xor:VMMX (match_operand:VMMX 1 "register_operand" "y")
338 (match_operand:VMMX 2 "register_operand" "y")))]
339 "TARGET_REALLY_IWMMXT"
340 "wxor\\t%0, %1, %2"
341 [(set_attr "predicable" "yes")
342 (set_attr "wtype" "wxor")]
343 )
346 ;; Vector add/subtract
348 (define_insn "*add<mode>3_iwmmxt"
349 [(set (match_operand:VMMX 0 "register_operand" "=y")
350 (plus:VMMX (match_operand:VMMX 1 "register_operand" "y")
351 (match_operand:VMMX 2 "register_operand" "y")))]
352 "TARGET_REALLY_IWMMXT"
353 "wadd<MMX_char>%?\\t%0, %1, %2"
354 [(set_attr "predicable" "yes")
355 (set_attr "wtype" "wadd")]
356 )
358 (define_insn "ssaddv8qi3"
359 [(set (match_operand:V8QI 0 "register_operand" "=y")
360 (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "y")
361 (match_operand:V8QI 2 "register_operand" "y")))]
362 "TARGET_REALLY_IWMMXT"
363 "waddbss%?\\t%0, %1, %2"
364 [(set_attr "predicable" "yes")
365 (set_attr "wtype" "wadd")]
366 )
368 (define_insn "ssaddv4hi3"
369 [(set (match_operand:V4HI 0 "register_operand" "=y")
370 (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "y")
371 (match_operand:V4HI 2 "register_operand" "y")))]
372 "TARGET_REALLY_IWMMXT"
373 "waddhss%?\\t%0, %1, %2"
374 [(set_attr "predicable" "yes")
375 (set_attr "wtype" "wadd")]
376 )
378 (define_insn "ssaddv2si3"
379 [(set (match_operand:V2SI 0 "register_operand" "=y")
380 (ss_plus:V2SI (match_operand:V2SI 1 "register_operand" "y")
381 (match_operand:V2SI 2 "register_operand" "y")))]
382 "TARGET_REALLY_IWMMXT"
383 "waddwss%?\\t%0, %1, %2"
384 [(set_attr "predicable" "yes")
385 (set_attr "wtype" "wadd")]
386 )
388 (define_insn "usaddv8qi3"
389 [(set (match_operand:V8QI 0 "register_operand" "=y")
390 (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "y")
391 (match_operand:V8QI 2 "register_operand" "y")))]
392 "TARGET_REALLY_IWMMXT"
393 "waddbus%?\\t%0, %1, %2"
394 [(set_attr "predicable" "yes")
395 (set_attr "wtype" "wadd")]
396 )
398 (define_insn "usaddv4hi3"
399 [(set (match_operand:V4HI 0 "register_operand" "=y")
400 (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "y")
401 (match_operand:V4HI 2 "register_operand" "y")))]
402 "TARGET_REALLY_IWMMXT"
403 "waddhus%?\\t%0, %1, %2"
404 [(set_attr "predicable" "yes")
405 (set_attr "wtype" "wadd")]
406 )
408 (define_insn "usaddv2si3"
409 [(set (match_operand:V2SI 0 "register_operand" "=y")
410 (us_plus:V2SI (match_operand:V2SI 1 "register_operand" "y")
411 (match_operand:V2SI 2 "register_operand" "y")))]
412 "TARGET_REALLY_IWMMXT"
413 "waddwus%?\\t%0, %1, %2"
414 [(set_attr "predicable" "yes")
415 (set_attr "wtype" "wadd")]
416 )
418 (define_insn "*sub<mode>3_iwmmxt"
419 [(set (match_operand:VMMX 0 "register_operand" "=y")
420 (minus:VMMX (match_operand:VMMX 1 "register_operand" "y")
421 (match_operand:VMMX 2 "register_operand" "y")))]
422 "TARGET_REALLY_IWMMXT"
423 "wsub<MMX_char>%?\\t%0, %1, %2"
424 [(set_attr "predicable" "yes")
425 (set_attr "wtype" "wsub")]
426 )
428 (define_insn "sssubv8qi3"
429 [(set (match_operand:V8QI 0 "register_operand" "=y")
430 (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
431 (match_operand:V8QI 2 "register_operand" "y")))]
432 "TARGET_REALLY_IWMMXT"
433 "wsubbss%?\\t%0, %1, %2"
434 [(set_attr "predicable" "yes")
435 (set_attr "wtype" "wsub")]
436 )
438 (define_insn "sssubv4hi3"
439 [(set (match_operand:V4HI 0 "register_operand" "=y")
440 (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
441 (match_operand:V4HI 2 "register_operand" "y")))]
442 "TARGET_REALLY_IWMMXT"
443 "wsubhss%?\\t%0, %1, %2"
444 [(set_attr "predicable" "yes")
445 (set_attr "wtype" "wsub")]
446 )
448 (define_insn "sssubv2si3"
449 [(set (match_operand:V2SI 0 "register_operand" "=y")
450 (ss_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
451 (match_operand:V2SI 2 "register_operand" "y")))]
452 "TARGET_REALLY_IWMMXT"
453 "wsubwss%?\\t%0, %1, %2"
454 [(set_attr "predicable" "yes")
455 (set_attr "wtype" "wsub")]
456 )
458 (define_insn "ussubv8qi3"
459 [(set (match_operand:V8QI 0 "register_operand" "=y")
460 (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "y")
461 (match_operand:V8QI 2 "register_operand" "y")))]
462 "TARGET_REALLY_IWMMXT"
463 "wsubbus%?\\t%0, %1, %2"
464 [(set_attr "predicable" "yes")
465 (set_attr "wtype" "wsub")]
466 )
468 (define_insn "ussubv4hi3"
469 [(set (match_operand:V4HI 0 "register_operand" "=y")
470 (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "y")
471 (match_operand:V4HI 2 "register_operand" "y")))]
472 "TARGET_REALLY_IWMMXT"
473 "wsubhus%?\\t%0, %1, %2"
474 [(set_attr "predicable" "yes")
475 (set_attr "wtype" "wsub")]
476 )
478 (define_insn "ussubv2si3"
479 [(set (match_operand:V2SI 0 "register_operand" "=y")
480 (us_minus:V2SI (match_operand:V2SI 1 "register_operand" "y")
481 (match_operand:V2SI 2 "register_operand" "y")))]
482 "TARGET_REALLY_IWMMXT"
483 "wsubwus%?\\t%0, %1, %2"
484 [(set_attr "predicable" "yes")
485 (set_attr "wtype" "wsub")]
486 )
488 (define_insn "*mulv4hi3_iwmmxt"
489 [(set (match_operand:V4HI 0 "register_operand" "=y")
490 (mult:V4HI (match_operand:V4HI 1 "register_operand" "y")
491 (match_operand:V4HI 2 "register_operand" "y")))]
492 "TARGET_REALLY_IWMMXT"
493 "wmulul%?\\t%0, %1, %2"
494 [(set_attr "predicable" "yes")
495 (set_attr "wtype" "wmul")]
496 )
498 (define_insn "smulv4hi3_highpart"
499 [(set (match_operand:V4HI 0 "register_operand" "=y")
500 (truncate:V4HI
501 (lshiftrt:V4SI
502 (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
503 (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
504 (const_int 16))))]
505 "TARGET_REALLY_IWMMXT"
506 "wmulsm%?\\t%0, %1, %2"
507 [(set_attr "predicable" "yes")
508 (set_attr "wtype" "wmul")]
509 )
511 (define_insn "umulv4hi3_highpart"
512 [(set (match_operand:V4HI 0 "register_operand" "=y")
513 (truncate:V4HI
514 (lshiftrt:V4SI
515 (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
516 (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
517 (const_int 16))))]
518 "TARGET_REALLY_IWMMXT"
519 "wmulum%?\\t%0, %1, %2"
520 [(set_attr "predicable" "yes")
521 (set_attr "wtype" "wmul")]
522 )
524 (define_insn "iwmmxt_wmacs"
525 [(set (match_operand:DI 0 "register_operand" "=y")
526 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
527 (match_operand:V4HI 2 "register_operand" "y")
528 (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACS))]
529 "TARGET_REALLY_IWMMXT"
530 "wmacs%?\\t%0, %2, %3"
531 [(set_attr "predicable" "yes")
532 (set_attr "wtype" "wmac")]
533 )
535 (define_insn "iwmmxt_wmacsz"
536 [(set (match_operand:DI 0 "register_operand" "=y")
537 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
538 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACSZ))]
539 "TARGET_REALLY_IWMMXT"
540 "wmacsz%?\\t%0, %1, %2"
541 [(set_attr "predicable" "yes")
542 (set_attr "wtype" "wmac")]
543 )
545 (define_insn "iwmmxt_wmacu"
546 [(set (match_operand:DI 0 "register_operand" "=y")
547 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
548 (match_operand:V4HI 2 "register_operand" "y")
549 (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACU))]
550 "TARGET_REALLY_IWMMXT"
551 "wmacu%?\\t%0, %2, %3"
552 [(set_attr "predicable" "yes")
553 (set_attr "wtype" "wmac")]
554 )
556 (define_insn "iwmmxt_wmacuz"
557 [(set (match_operand:DI 0 "register_operand" "=y")
558 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")
559 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACUZ))]
560 "TARGET_REALLY_IWMMXT"
561 "wmacuz%?\\t%0, %1, %2"
562 [(set_attr "predicable" "yes")
563 (set_attr "wtype" "wmac")]
564 )
566 ;; Same as xordi3, but don't show input operands so that we don't think
567 ;; they are live.
568 (define_insn "iwmmxt_clrdi"
569 [(set (match_operand:DI 0 "register_operand" "=y")
570 (unspec:DI [(const_int 0)] UNSPEC_CLRDI))]
571 "TARGET_REALLY_IWMMXT"
572 "wxor%?\\t%0, %0, %0"
573 [(set_attr "predicable" "yes")
574 (set_attr "wtype" "wxor")]
575 )
577 ;; Seems like cse likes to generate these, so we have to support them.
579 (define_insn "iwmmxt_clrv8qi"
580 [(set (match_operand:V8QI 0 "s_register_operand" "=y")
581 (const_vector:V8QI [(const_int 0) (const_int 0)
582 (const_int 0) (const_int 0)
583 (const_int 0) (const_int 0)
584 (const_int 0) (const_int 0)]))]
585 "TARGET_REALLY_IWMMXT"
586 "wxor%?\\t%0, %0, %0"
587 [(set_attr "predicable" "yes")
588 (set_attr "wtype" "wxor")]
589 )
591 (define_insn "iwmmxt_clrv4hi"
592 [(set (match_operand:V4HI 0 "s_register_operand" "=y")
593 (const_vector:V4HI [(const_int 0) (const_int 0)
594 (const_int 0) (const_int 0)]))]
595 "TARGET_REALLY_IWMMXT"
596 "wxor%?\\t%0, %0, %0"
597 [(set_attr "predicable" "yes")
598 (set_attr "wtype" "wxor")]
599 )
601 (define_insn "iwmmxt_clrv2si"
602 [(set (match_operand:V2SI 0 "register_operand" "=y")
603 (const_vector:V2SI [(const_int 0) (const_int 0)]))]
604 "TARGET_REALLY_IWMMXT"
605 "wxor%?\\t%0, %0, %0"
606 [(set_attr "predicable" "yes")
607 (set_attr "wtype" "wxor")]
608 )
610 ;; Unsigned averages/sum of absolute differences
612 (define_insn "iwmmxt_uavgrndv8qi3"
613 [(set (match_operand:V8QI 0 "register_operand" "=y")
614 (truncate:V8QI
615 (lshiftrt:V8HI
616 (plus:V8HI
617 (plus:V8HI (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
618 (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y")))
619 (const_vector:V8HI [(const_int 1)
620 (const_int 1)
621 (const_int 1)
622 (const_int 1)
623 (const_int 1)
624 (const_int 1)
625 (const_int 1)
626 (const_int 1)]))
627 (const_int 1))))]
628 "TARGET_REALLY_IWMMXT"
629 "wavg2br%?\\t%0, %1, %2"
630 [(set_attr "predicable" "yes")
631 (set_attr "wtype" "wavg2")]
632 )
634 (define_insn "iwmmxt_uavgrndv4hi3"
635 [(set (match_operand:V4HI 0 "register_operand" "=y")
636 (truncate:V4HI
637 (lshiftrt:V4SI
638 (plus:V4SI
639 (plus:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
640 (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
641 (const_vector:V4SI [(const_int 1)
642 (const_int 1)
643 (const_int 1)
644 (const_int 1)]))
645 (const_int 1))))]
646 "TARGET_REALLY_IWMMXT"
647 "wavg2hr%?\\t%0, %1, %2"
648 [(set_attr "predicable" "yes")
649 (set_attr "wtype" "wavg2")]
650 )
652 (define_insn "iwmmxt_uavgv8qi3"
653 [(set (match_operand:V8QI 0 "register_operand" "=y")
654 (truncate:V8QI
655 (lshiftrt:V8HI
656 (plus:V8HI (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
657 (zero_extend:V8HI (match_operand:V8QI 2 "register_operand" "y")))
658 (const_int 1))))]
659 "TARGET_REALLY_IWMMXT"
660 "wavg2b%?\\t%0, %1, %2"
661 [(set_attr "predicable" "yes")
662 (set_attr "wtype" "wavg2")]
663 )
665 (define_insn "iwmmxt_uavgv4hi3"
666 [(set (match_operand:V4HI 0 "register_operand" "=y")
667 (truncate:V4HI
668 (lshiftrt:V4SI
669 (plus:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
670 (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y")))
671 (const_int 1))))]
672 "TARGET_REALLY_IWMMXT"
673 "wavg2h%?\\t%0, %1, %2"
674 [(set_attr "predicable" "yes")
675 (set_attr "wtype" "wavg2")]
676 )
678 ;; Insert/extract/shuffle
680 (define_insn "iwmmxt_tinsrb"
681 [(set (match_operand:V8QI 0 "register_operand" "=y")
682 (vec_merge:V8QI
683 (vec_duplicate:V8QI
684 (truncate:QI (match_operand:SI 2 "nonimmediate_operand" "r")))
685 (match_operand:V8QI 1 "register_operand" "0")
686 (match_operand:SI 3 "immediate_operand" "i")))]
687 "TARGET_REALLY_IWMMXT"
688 "*
689 {
690 return arm_output_iwmmxt_tinsr (operands);
691 }
692 "
693 [(set_attr "predicable" "yes")
694 (set_attr "wtype" "tinsr")]
695 )
697 (define_insn "iwmmxt_tinsrh"
698 [(set (match_operand:V4HI 0 "register_operand" "=y")
699 (vec_merge:V4HI
700 (vec_duplicate:V4HI
701 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "r")))
702 (match_operand:V4HI 1 "register_operand" "0")
703 (match_operand:SI 3 "immediate_operand" "i")))]
704 "TARGET_REALLY_IWMMXT"
705 "*
706 {
707 return arm_output_iwmmxt_tinsr (operands);
708 }
709 "
710 [(set_attr "predicable" "yes")
711 (set_attr "wtype" "tinsr")]
712 )
714 (define_insn "iwmmxt_tinsrw"
715 [(set (match_operand:V2SI 0 "register_operand" "=y")
716 (vec_merge:V2SI
717 (vec_duplicate:V2SI
718 (match_operand:SI 2 "nonimmediate_operand" "r"))
719 (match_operand:V2SI 1 "register_operand" "0")
720 (match_operand:SI 3 "immediate_operand" "i")))]
721 "TARGET_REALLY_IWMMXT"
722 "*
723 {
724 return arm_output_iwmmxt_tinsr (operands);
725 }
726 "
727 [(set_attr "predicable" "yes")
728 (set_attr "wtype" "tinsr")]
729 )
731 (define_insn "iwmmxt_textrmub"
732 [(set (match_operand:SI 0 "register_operand" "=r")
733 (zero_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
734 (parallel
735 [(match_operand:SI 2 "immediate_operand" "i")]))))]
736 "TARGET_REALLY_IWMMXT"
737 "textrmub%?\\t%0, %1, %2"
738 [(set_attr "predicable" "yes")
739 (set_attr "wtype" "textrm")]
740 )
742 (define_insn "iwmmxt_textrmsb"
743 [(set (match_operand:SI 0 "register_operand" "=r")
744 (sign_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y")
745 (parallel
746 [(match_operand:SI 2 "immediate_operand" "i")]))))]
747 "TARGET_REALLY_IWMMXT"
748 "textrmsb%?\\t%0, %1, %2"
749 [(set_attr "predicable" "yes")
750 (set_attr "wtype" "textrm")]
751 )
753 (define_insn "iwmmxt_textrmuh"
754 [(set (match_operand:SI 0 "register_operand" "=r")
755 (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
756 (parallel
757 [(match_operand:SI 2 "immediate_operand" "i")]))))]
758 "TARGET_REALLY_IWMMXT"
759 "textrmuh%?\\t%0, %1, %2"
760 [(set_attr "predicable" "yes")
761 (set_attr "wtype" "textrm")]
762 )
764 (define_insn "iwmmxt_textrmsh"
765 [(set (match_operand:SI 0 "register_operand" "=r")
766 (sign_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y")
767 (parallel
768 [(match_operand:SI 2 "immediate_operand" "i")]))))]
769 "TARGET_REALLY_IWMMXT"
770 "textrmsh%?\\t%0, %1, %2"
771 [(set_attr "predicable" "yes")
772 (set_attr "wtype" "textrm")]
773 )
775 ;; There are signed/unsigned variants of this instruction, but they are
776 ;; pointless.
777 (define_insn "iwmmxt_textrmw"
778 [(set (match_operand:SI 0 "register_operand" "=r")
779 (vec_select:SI (match_operand:V2SI 1 "register_operand" "y")
780 (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
781 "TARGET_REALLY_IWMMXT"
782 "textrmsw%?\\t%0, %1, %2"
783 [(set_attr "predicable" "yes")
784 (set_attr "wtype" "textrm")]
785 )
787 (define_insn "iwmmxt_wshufh"
788 [(set (match_operand:V4HI 0 "register_operand" "=y")
789 (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y")
790 (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_WSHUFH))]
791 "TARGET_REALLY_IWMMXT"
792 "wshufh%?\\t%0, %1, %2"
793 [(set_attr "predicable" "yes")
794 (set_attr "wtype" "wshufh")]
795 )
797 ;; Mask-generating comparisons
798 ;;
799 ;; Note - you cannot use patterns like these here:
800 ;;
801 ;; (set (match:<vector>) (<comparator>:<vector> (match:<vector>) (match:<vector>)))
802 ;;
803 ;; Because GCC will assume that the truth value (1 or 0) is installed
804 ;; into the entire destination vector, (with the '1' going into the least
805 ;; significant element of the vector). This is not how these instructions
806 ;; behave.
808 (define_insn "eqv8qi3"
809 [(set (match_operand:V8QI 0 "register_operand" "=y")
810 (unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand" "y")
811 (match_operand:V8QI 2 "register_operand" "y")]
812 VUNSPEC_WCMP_EQ))]
813 "TARGET_REALLY_IWMMXT"
814 "wcmpeqb%?\\t%0, %1, %2"
815 [(set_attr "predicable" "yes")
816 (set_attr "wtype" "wcmpeq")]
817 )
819 (define_insn "eqv4hi3"
820 [(set (match_operand:V4HI 0 "register_operand" "=y")
821 (unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand" "y")
822 (match_operand:V4HI 2 "register_operand" "y")]
823 VUNSPEC_WCMP_EQ))]
824 "TARGET_REALLY_IWMMXT"
825 "wcmpeqh%?\\t%0, %1, %2"
826 [(set_attr "predicable" "yes")
827 (set_attr "wtype" "wcmpeq")]
828 )
830 (define_insn "eqv2si3"
831 [(set (match_operand:V2SI 0 "register_operand" "=y")
832 (unspec_volatile:V2SI
833 [(match_operand:V2SI 1 "register_operand" "y")
834 (match_operand:V2SI 2 "register_operand" "y")]
835 VUNSPEC_WCMP_EQ))]
836 "TARGET_REALLY_IWMMXT"
837 "wcmpeqw%?\\t%0, %1, %2"
838 [(set_attr "predicable" "yes")
839 (set_attr "wtype" "wcmpeq")]
840 )
842 (define_insn "gtuv8qi3"
843 [(set (match_operand:V8QI 0 "register_operand" "=y")
844 (unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand" "y")
845 (match_operand:V8QI 2 "register_operand" "y")]
846 VUNSPEC_WCMP_GTU))]
847 "TARGET_REALLY_IWMMXT"
848 "wcmpgtub%?\\t%0, %1, %2"
849 [(set_attr "predicable" "yes")
850 (set_attr "wtype" "wcmpgt")]
851 )
853 (define_insn "gtuv4hi3"
854 [(set (match_operand:V4HI 0 "register_operand" "=y")
855 (unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand" "y")
856 (match_operand:V4HI 2 "register_operand" "y")]
857 VUNSPEC_WCMP_GTU))]
858 "TARGET_REALLY_IWMMXT"
859 "wcmpgtuh%?\\t%0, %1, %2"
860 [(set_attr "predicable" "yes")
861 (set_attr "wtype" "wcmpgt")]
862 )
864 (define_insn "gtuv2si3"
865 [(set (match_operand:V2SI 0 "register_operand" "=y")
866 (unspec_volatile:V2SI [(match_operand:V2SI 1 "register_operand" "y")
867 (match_operand:V2SI 2 "register_operand" "y")]
868 VUNSPEC_WCMP_GTU))]
869 "TARGET_REALLY_IWMMXT"
870 "wcmpgtuw%?\\t%0, %1, %2"
871 [(set_attr "predicable" "yes")
872 (set_attr "wtype" "wcmpgt")]
873 )
875 (define_insn "gtv8qi3"
876 [(set (match_operand:V8QI 0 "register_operand" "=y")
877 (unspec_volatile:V8QI [(match_operand:V8QI 1 "register_operand" "y")
878 (match_operand:V8QI 2 "register_operand" "y")]
879 VUNSPEC_WCMP_GT))]
880 "TARGET_REALLY_IWMMXT"
881 "wcmpgtsb%?\\t%0, %1, %2"
882 [(set_attr "predicable" "yes")
883 (set_attr "wtype" "wcmpgt")]
884 )
886 (define_insn "gtv4hi3"
887 [(set (match_operand:V4HI 0 "register_operand" "=y")
888 (unspec_volatile:V4HI [(match_operand:V4HI 1 "register_operand" "y")
889 (match_operand:V4HI 2 "register_operand" "y")]
890 VUNSPEC_WCMP_GT))]
891 "TARGET_REALLY_IWMMXT"
892 "wcmpgtsh%?\\t%0, %1, %2"
893 [(set_attr "predicable" "yes")
894 (set_attr "wtype" "wcmpgt")]
895 )
897 (define_insn "gtv2si3"
898 [(set (match_operand:V2SI 0 "register_operand" "=y")
899 (unspec_volatile:V2SI [(match_operand:V2SI 1 "register_operand" "y")
900 (match_operand:V2SI 2 "register_operand" "y")]
901 VUNSPEC_WCMP_GT))]
902 "TARGET_REALLY_IWMMXT"
903 "wcmpgtsw%?\\t%0, %1, %2"
904 [(set_attr "predicable" "yes")
905 (set_attr "wtype" "wcmpgt")]
906 )
908 ;; Max/min insns
910 (define_insn "*smax<mode>3_iwmmxt"
911 [(set (match_operand:VMMX 0 "register_operand" "=y")
912 (smax:VMMX (match_operand:VMMX 1 "register_operand" "y")
913 (match_operand:VMMX 2 "register_operand" "y")))]
914 "TARGET_REALLY_IWMMXT"
915 "wmaxs<MMX_char>%?\\t%0, %1, %2"
916 [(set_attr "predicable" "yes")
917 (set_attr "wtype" "wmax")]
918 )
920 (define_insn "*umax<mode>3_iwmmxt"
921 [(set (match_operand:VMMX 0 "register_operand" "=y")
922 (umax:VMMX (match_operand:VMMX 1 "register_operand" "y")
923 (match_operand:VMMX 2 "register_operand" "y")))]
924 "TARGET_REALLY_IWMMXT"
925 "wmaxu<MMX_char>%?\\t%0, %1, %2"
926 [(set_attr "predicable" "yes")
927 (set_attr "wtype" "wmax")]
928 )
930 (define_insn "*smin<mode>3_iwmmxt"
931 [(set (match_operand:VMMX 0 "register_operand" "=y")
932 (smin:VMMX (match_operand:VMMX 1 "register_operand" "y")
933 (match_operand:VMMX 2 "register_operand" "y")))]
934 "TARGET_REALLY_IWMMXT"
935 "wmins<MMX_char>%?\\t%0, %1, %2"
936 [(set_attr "predicable" "yes")
937 (set_attr "wtype" "wmin")]
938 )
940 (define_insn "*umin<mode>3_iwmmxt"
941 [(set (match_operand:VMMX 0 "register_operand" "=y")
942 (umin:VMMX (match_operand:VMMX 1 "register_operand" "y")
943 (match_operand:VMMX 2 "register_operand" "y")))]
944 "TARGET_REALLY_IWMMXT"
945 "wminu<MMX_char>%?\\t%0, %1, %2"
946 [(set_attr "predicable" "yes")
947 (set_attr "wtype" "wmin")]
948 )
950 ;; Pack/unpack insns.
952 (define_insn "iwmmxt_wpackhss"
953 [(set (match_operand:V8QI 0 "register_operand" "=y")
954 (vec_concat:V8QI
955 (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
956 (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
957 "TARGET_REALLY_IWMMXT"
958 "wpackhss%?\\t%0, %1, %2"
959 [(set_attr "predicable" "yes")
960 (set_attr "wtype" "wpack")]
961 )
963 (define_insn "iwmmxt_wpackwss"
964 [(set (match_operand:V4HI 0 "register_operand" "=y")
965 (vec_concat:V4HI
966 (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
967 (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
968 "TARGET_REALLY_IWMMXT"
969 "wpackwss%?\\t%0, %1, %2"
970 [(set_attr "predicable" "yes")
971 (set_attr "wtype" "wpack")]
972 )
974 (define_insn "iwmmxt_wpackdss"
975 [(set (match_operand:V2SI 0 "register_operand" "=y")
976 (vec_concat:V2SI
977 (ss_truncate:SI (match_operand:DI 1 "register_operand" "y"))
978 (ss_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
979 "TARGET_REALLY_IWMMXT"
980 "wpackdss%?\\t%0, %1, %2"
981 [(set_attr "predicable" "yes")
982 (set_attr "wtype" "wpack")]
983 )
985 (define_insn "iwmmxt_wpackhus"
986 [(set (match_operand:V8QI 0 "register_operand" "=y")
987 (vec_concat:V8QI
988 (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y"))
989 (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))]
990 "TARGET_REALLY_IWMMXT"
991 "wpackhus%?\\t%0, %1, %2"
992 [(set_attr "predicable" "yes")
993 (set_attr "wtype" "wpack")]
994 )
996 (define_insn "iwmmxt_wpackwus"
997 [(set (match_operand:V4HI 0 "register_operand" "=y")
998 (vec_concat:V4HI
999 (us_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y"))
1000 (us_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))]
1001 "TARGET_REALLY_IWMMXT"
1002 "wpackwus%?\\t%0, %1, %2"
1003 [(set_attr "predicable" "yes")
1004 (set_attr "wtype" "wpack")]
1005 )
1007 (define_insn "iwmmxt_wpackdus"
1008 [(set (match_operand:V2SI 0 "register_operand" "=y")
1009 (vec_concat:V2SI
1010 (us_truncate:SI (match_operand:DI 1 "register_operand" "y"))
1011 (us_truncate:SI (match_operand:DI 2 "register_operand" "y"))))]
1012 "TARGET_REALLY_IWMMXT"
1013 "wpackdus%?\\t%0, %1, %2"
1014 [(set_attr "predicable" "yes")
1015 (set_attr "wtype" "wpack")]
1016 )
1018 (define_insn "iwmmxt_wunpckihb"
1019 [(set (match_operand:V8QI 0 "register_operand" "=y")
1020 (vec_merge:V8QI
1021 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
1022 (parallel [(const_int 4)
1023 (const_int 0)
1024 (const_int 5)
1025 (const_int 1)
1026 (const_int 6)
1027 (const_int 2)
1028 (const_int 7)
1029 (const_int 3)]))
1030 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
1031 (parallel [(const_int 0)
1032 (const_int 4)
1033 (const_int 1)
1034 (const_int 5)
1035 (const_int 2)
1036 (const_int 6)
1037 (const_int 3)
1038 (const_int 7)]))
1039 (const_int 85)))]
1040 "TARGET_REALLY_IWMMXT"
1041 "wunpckihb%?\\t%0, %1, %2"
1042 [(set_attr "predicable" "yes")
1043 (set_attr "wtype" "wunpckih")]
1044 )
1046 (define_insn "iwmmxt_wunpckihh"
1047 [(set (match_operand:V4HI 0 "register_operand" "=y")
1048 (vec_merge:V4HI
1049 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
1050 (parallel [(const_int 2)
1051 (const_int 0)
1052 (const_int 3)
1053 (const_int 1)]))
1054 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
1055 (parallel [(const_int 0)
1056 (const_int 2)
1057 (const_int 1)
1058 (const_int 3)]))
1059 (const_int 5)))]
1060 "TARGET_REALLY_IWMMXT"
1061 "wunpckihh%?\\t%0, %1, %2"
1062 [(set_attr "predicable" "yes")
1063 (set_attr "wtype" "wunpckih")]
1064 )
1066 (define_insn "iwmmxt_wunpckihw"
1067 [(set (match_operand:V2SI 0 "register_operand" "=y")
1068 (vec_merge:V2SI
1069 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
1070 (parallel [(const_int 1)
1071 (const_int 0)]))
1072 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
1073 (parallel [(const_int 0)
1074 (const_int 1)]))
1075 (const_int 1)))]
1076 "TARGET_REALLY_IWMMXT"
1077 "wunpckihw%?\\t%0, %1, %2"
1078 [(set_attr "predicable" "yes")
1079 (set_attr "wtype" "wunpckih")]
1080 )
1082 (define_insn "iwmmxt_wunpckilb"
1083 [(set (match_operand:V8QI 0 "register_operand" "=y")
1084 (vec_merge:V8QI
1085 (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y")
1086 (parallel [(const_int 0)
1087 (const_int 4)
1088 (const_int 1)
1089 (const_int 5)
1090 (const_int 2)
1091 (const_int 6)
1092 (const_int 3)
1093 (const_int 7)]))
1094 (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y")
1095 (parallel [(const_int 4)
1096 (const_int 0)
1097 (const_int 5)
1098 (const_int 1)
1099 (const_int 6)
1100 (const_int 2)
1101 (const_int 7)
1102 (const_int 3)]))
1103 (const_int 85)))]
1104 "TARGET_REALLY_IWMMXT"
1105 "wunpckilb%?\\t%0, %1, %2"
1106 [(set_attr "predicable" "yes")
1107 (set_attr "wtype" "wunpckil")]
1108 )
1110 (define_insn "iwmmxt_wunpckilh"
1111 [(set (match_operand:V4HI 0 "register_operand" "=y")
1112 (vec_merge:V4HI
1113 (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y")
1114 (parallel [(const_int 0)
1115 (const_int 2)
1116 (const_int 1)
1117 (const_int 3)]))
1118 (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y")
1119 (parallel [(const_int 2)
1120 (const_int 0)
1121 (const_int 3)
1122 (const_int 1)]))
1123 (const_int 5)))]
1124 "TARGET_REALLY_IWMMXT"
1125 "wunpckilh%?\\t%0, %1, %2"
1126 [(set_attr "predicable" "yes")
1127 (set_attr "wtype" "wunpckil")]
1128 )
1130 (define_insn "iwmmxt_wunpckilw"
1131 [(set (match_operand:V2SI 0 "register_operand" "=y")
1132 (vec_merge:V2SI
1133 (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y")
1134 (parallel [(const_int 0)
1135 (const_int 1)]))
1136 (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y")
1137 (parallel [(const_int 1)
1138 (const_int 0)]))
1139 (const_int 1)))]
1140 "TARGET_REALLY_IWMMXT"
1141 "wunpckilw%?\\t%0, %1, %2"
1142 [(set_attr "predicable" "yes")
1143 (set_attr "wtype" "wunpckil")]
1144 )
1146 (define_insn "iwmmxt_wunpckehub"
1147 [(set (match_operand:V4HI 0 "register_operand" "=y")
1148 (vec_select:V4HI
1149 (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
1150 (parallel [(const_int 4) (const_int 5)
1151 (const_int 6) (const_int 7)])))]
1152 "TARGET_REALLY_IWMMXT"
1153 "wunpckehub%?\\t%0, %1"
1154 [(set_attr "predicable" "yes")
1155 (set_attr "wtype" "wunpckeh")]
1156 )
1158 (define_insn "iwmmxt_wunpckehuh"
1159 [(set (match_operand:V2SI 0 "register_operand" "=y")
1160 (vec_select:V2SI
1161 (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
1162 (parallel [(const_int 2) (const_int 3)])))]
1163 "TARGET_REALLY_IWMMXT"
1164 "wunpckehuh%?\\t%0, %1"
1165 [(set_attr "predicable" "yes")
1166 (set_attr "wtype" "wunpckeh")]
1167 )
1169 (define_insn "iwmmxt_wunpckehuw"
1170 [(set (match_operand:DI 0 "register_operand" "=y")
1171 (vec_select:DI
1172 (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
1173 (parallel [(const_int 1)])))]
1174 "TARGET_REALLY_IWMMXT"
1175 "wunpckehuw%?\\t%0, %1"
1176 [(set_attr "predicable" "yes")
1177 (set_attr "wtype" "wunpckeh")]
1178 )
1180 (define_insn "iwmmxt_wunpckehsb"
1181 [(set (match_operand:V4HI 0 "register_operand" "=y")
1182 (vec_select:V4HI
1183 (sign_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
1184 (parallel [(const_int 4) (const_int 5)
1185 (const_int 6) (const_int 7)])))]
1186 "TARGET_REALLY_IWMMXT"
1187 "wunpckehsb%?\\t%0, %1"
1188 [(set_attr "predicable" "yes")
1189 (set_attr "wtype" "wunpckeh")]
1190 )
1192 (define_insn "iwmmxt_wunpckehsh"
1193 [(set (match_operand:V2SI 0 "register_operand" "=y")
1194 (vec_select:V2SI
1195 (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
1196 (parallel [(const_int 2) (const_int 3)])))]
1197 "TARGET_REALLY_IWMMXT"
1198 "wunpckehsh%?\\t%0, %1"
1199 [(set_attr "predicable" "yes")
1200 (set_attr "wtype" "wunpckeh")]
1201 )
1203 (define_insn "iwmmxt_wunpckehsw"
1204 [(set (match_operand:DI 0 "register_operand" "=y")
1205 (vec_select:DI
1206 (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
1207 (parallel [(const_int 1)])))]
1208 "TARGET_REALLY_IWMMXT"
1209 "wunpckehsw%?\\t%0, %1"
1210 [(set_attr "predicable" "yes")
1211 (set_attr "wtype" "wunpckeh")]
1212 )
1214 (define_insn "iwmmxt_wunpckelub"
1215 [(set (match_operand:V4HI 0 "register_operand" "=y")
1216 (vec_select:V4HI
1217 (zero_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
1218 (parallel [(const_int 0) (const_int 1)
1219 (const_int 2) (const_int 3)])))]
1220 "TARGET_REALLY_IWMMXT"
1221 "wunpckelub%?\\t%0, %1"
1222 [(set_attr "predicable" "yes")
1223 (set_attr "wtype" "wunpckel")]
1224 )
1226 (define_insn "iwmmxt_wunpckeluh"
1227 [(set (match_operand:V2SI 0 "register_operand" "=y")
1228 (vec_select:V2SI
1229 (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
1230 (parallel [(const_int 0) (const_int 1)])))]
1231 "TARGET_REALLY_IWMMXT"
1232 "wunpckeluh%?\\t%0, %1"
1233 [(set_attr "predicable" "yes")
1234 (set_attr "wtype" "wunpckel")]
1235 )
1237 (define_insn "iwmmxt_wunpckeluw"
1238 [(set (match_operand:DI 0 "register_operand" "=y")
1239 (vec_select:DI
1240 (zero_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
1241 (parallel [(const_int 0)])))]
1242 "TARGET_REALLY_IWMMXT"
1243 "wunpckeluw%?\\t%0, %1"
1244 [(set_attr "predicable" "yes")
1245 (set_attr "wtype" "wunpckel")]
1246 )
1248 (define_insn "iwmmxt_wunpckelsb"
1249 [(set (match_operand:V4HI 0 "register_operand" "=y")
1250 (vec_select:V4HI
1251 (sign_extend:V8HI (match_operand:V8QI 1 "register_operand" "y"))
1252 (parallel [(const_int 0) (const_int 1)
1253 (const_int 2) (const_int 3)])))]
1254 "TARGET_REALLY_IWMMXT"
1255 "wunpckelsb%?\\t%0, %1"
1256 [(set_attr "predicable" "yes")
1257 (set_attr "wtype" "wunpckel")]
1258 )
1260 (define_insn "iwmmxt_wunpckelsh"
1261 [(set (match_operand:V2SI 0 "register_operand" "=y")
1262 (vec_select:V2SI
1263 (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
1264 (parallel [(const_int 0) (const_int 1)])))]
1265 "TARGET_REALLY_IWMMXT"
1266 "wunpckelsh%?\\t%0, %1"
1267 [(set_attr "predicable" "yes")
1268 (set_attr "wtype" "wunpckel")]
1269 )
1271 (define_insn "iwmmxt_wunpckelsw"
1272 [(set (match_operand:DI 0 "register_operand" "=y")
1273 (vec_select:DI
1274 (sign_extend:V2DI (match_operand:V2SI 1 "register_operand" "y"))
1275 (parallel [(const_int 0)])))]
1276 "TARGET_REALLY_IWMMXT"
1277 "wunpckelsw%?\\t%0, %1"
1278 [(set_attr "predicable" "yes")
1279 (set_attr "wtype" "wunpckel")]
1280 )
1282 ;; Shifts
1284 (define_insn "ror<mode>3"
1285 [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
1286 (rotatert:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1287 (match_operand:SI 2 "imm_or_reg_operand" "z,i")))]
1288 "TARGET_REALLY_IWMMXT"
1289 "*
1290 switch (which_alternative)
1291 {
1292 case 0:
1293 return \"wror<MMX_char>g%?\\t%0, %1, %2\";
1294 case 1:
1295 return arm_output_iwmmxt_shift_immediate (\"wror<MMX_char>\", operands, true);
1296 default:
1297 gcc_unreachable ();
1298 }
1299 "
1300 [(set_attr "predicable" "yes")
1301 (set_attr "arch" "*, iwmmxt2")
1302 (set_attr "wtype" "wror, wror")]
1303 )
1305 (define_insn "ashr<mode>3_iwmmxt"
1306 [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
1307 (ashiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1308 (match_operand:SI 2 "imm_or_reg_operand" "z,i")))]
1309 "TARGET_REALLY_IWMMXT"
1310 "*
1311 switch (which_alternative)
1312 {
1313 case 0:
1314 return \"wsra<MMX_char>g%?\\t%0, %1, %2\";
1315 case 1:
1316 return arm_output_iwmmxt_shift_immediate (\"wsra<MMX_char>\", operands, true);
1317 default:
1318 gcc_unreachable ();
1319 }
1320 "
1321 [(set_attr "predicable" "yes")
1322 (set_attr "arch" "*, iwmmxt2")
1323 (set_attr "wtype" "wsra, wsra")]
1324 )
1326 (define_insn "lshr<mode>3_iwmmxt"
1327 [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
1328 (lshiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1329 (match_operand:SI 2 "imm_or_reg_operand" "z,i")))]
1330 "TARGET_REALLY_IWMMXT"
1331 "*
1332 switch (which_alternative)
1333 {
1334 case 0:
1335 return \"wsrl<MMX_char>g%?\\t%0, %1, %2\";
1336 case 1:
1337 return arm_output_iwmmxt_shift_immediate (\"wsrl<MMX_char>\", operands, false);
1338 default:
1339 gcc_unreachable ();
1340 }
1341 "
1342 [(set_attr "predicable" "yes")
1343 (set_attr "arch" "*, iwmmxt2")
1344 (set_attr "wtype" "wsrl, wsrl")]
1345 )
1347 (define_insn "ashl<mode>3_iwmmxt"
1348 [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
1349 (ashift:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1350 (match_operand:SI 2 "imm_or_reg_operand" "z,i")))]
1351 "TARGET_REALLY_IWMMXT"
1352 "*
1353 switch (which_alternative)
1354 {
1355 case 0:
1356 return \"wsll<MMX_char>g%?\\t%0, %1, %2\";
1357 case 1:
1358 return arm_output_iwmmxt_shift_immediate (\"wsll<MMX_char>\", operands, false);
1359 default:
1360 gcc_unreachable ();
1361 }
1362 "
1363 [(set_attr "predicable" "yes")
1364 (set_attr "arch" "*, iwmmxt2")
1365 (set_attr "wtype" "wsll, wsll")]
1366 )
1368 (define_insn "ror<mode>3_di"
1369 [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
1370 (rotatert:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1371 (match_operand:DI 2 "imm_or_reg_operand" "y,i")))]
1372 "TARGET_REALLY_IWMMXT"
1373 "*
1374 switch (which_alternative)
1375 {
1376 case 0:
1377 return \"wror<MMX_char>%?\\t%0, %1, %2\";
1378 case 1:
1379 return arm_output_iwmmxt_shift_immediate (\"wror<MMX_char>\", operands, true);
1380 default:
1381 gcc_unreachable ();
1382 }
1383 "
1384 [(set_attr "predicable" "yes")
1385 (set_attr "arch" "*, iwmmxt2")
1386 (set_attr "wtype" "wror, wror")]
1387 )
1389 (define_insn "ashr<mode>3_di"
1390 [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
1391 (ashiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1392 (match_operand:DI 2 "imm_or_reg_operand" "y,i")))]
1393 "TARGET_REALLY_IWMMXT"
1394 "*
1395 switch (which_alternative)
1396 {
1397 case 0:
1398 return \"wsra<MMX_char>%?\\t%0, %1, %2\";
1399 case 1:
1400 return arm_output_iwmmxt_shift_immediate (\"wsra<MMX_char>\", operands, true);
1401 default:
1402 gcc_unreachable ();
1403 }
1404 "
1405 [(set_attr "predicable" "yes")
1406 (set_attr "arch" "*, iwmmxt2")
1407 (set_attr "wtype" "wsra, wsra")]
1408 )
1410 (define_insn "lshr<mode>3_di"
1411 [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
1412 (lshiftrt:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1413 (match_operand:DI 2 "register_operand" "y,i")))]
1414 "TARGET_REALLY_IWMMXT"
1415 "*
1416 switch (which_alternative)
1417 {
1418 case 0:
1419 return \"wsrl<MMX_char>%?\\t%0, %1, %2\";
1420 case 1:
1421 return arm_output_iwmmxt_shift_immediate (\"wsrl<MMX_char>\", operands, false);
1422 default:
1423 gcc_unreachable ();
1424 }
1425 "
1426 [(set_attr "predicable" "yes")
1427 (set_attr "arch" "*, iwmmxt2")
1428 (set_attr "wtype" "wsrl, wsrl")]
1429 )
1431 (define_insn "ashl<mode>3_di"
1432 [(set (match_operand:VSHFT 0 "register_operand" "=y,y")
1433 (ashift:VSHFT (match_operand:VSHFT 1 "register_operand" "y,y")
1434 (match_operand:DI 2 "imm_or_reg_operand" "y,i")))]
1435 "TARGET_REALLY_IWMMXT"
1436 "*
1437 switch (which_alternative)
1438 {
1439 case 0:
1440 return \"wsll<MMX_char>%?\\t%0, %1, %2\";
1441 case 1:
1442 return arm_output_iwmmxt_shift_immediate (\"wsll<MMX_char>\", operands, false);
1443 default:
1444 gcc_unreachable ();
1445 }
1446 "
1447 [(set_attr "predicable" "yes")
1448 (set_attr "arch" "*, iwmmxt2")
1449 (set_attr "wtype" "wsll, wsll")]
1450 )
1452 (define_insn "iwmmxt_wmadds"
1453 [(set (match_operand:V2SI 0 "register_operand" "=y")
1454 (plus:V2SI
1455 (mult:V2SI
1456 (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
1457 (parallel [(const_int 1) (const_int 3)]))
1458 (vec_select:V2SI (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))
1459 (parallel [(const_int 1) (const_int 3)])))
1460 (mult:V2SI
1461 (vec_select:V2SI (sign_extend:V4SI (match_dup 1))
1462 (parallel [(const_int 0) (const_int 2)]))
1463 (vec_select:V2SI (sign_extend:V4SI (match_dup 2))
1464 (parallel [(const_int 0) (const_int 2)])))))]
1465 "TARGET_REALLY_IWMMXT"
1466 "wmadds%?\\t%0, %1, %2"
1467 [(set_attr "predicable" "yes")
1468 (set_attr "wtype" "wmadd")]
1469 )
1471 (define_insn "iwmmxt_wmaddu"
1472 [(set (match_operand:V2SI 0 "register_operand" "=y")
1473 (plus:V2SI
1474 (mult:V2SI
1475 (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y"))
1476 (parallel [(const_int 1) (const_int 3)]))
1477 (vec_select:V2SI (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))
1478 (parallel [(const_int 1) (const_int 3)])))
1479 (mult:V2SI
1480 (vec_select:V2SI (zero_extend:V4SI (match_dup 1))
1481 (parallel [(const_int 0) (const_int 2)]))
1482 (vec_select:V2SI (zero_extend:V4SI (match_dup 2))
1483 (parallel [(const_int 0) (const_int 2)])))))]
1484 "TARGET_REALLY_IWMMXT"
1485 "wmaddu%?\\t%0, %1, %2"
1486 [(set_attr "predicable" "yes")
1487 (set_attr "wtype" "wmadd")]
1488 )
1490 (define_insn "iwmmxt_tmia"
1491 [(set (match_operand:DI 0 "register_operand" "=y")
1492 (plus:DI (match_operand:DI 1 "register_operand" "0")
1493 (mult:DI (sign_extend:DI
1494 (match_operand:SI 2 "register_operand" "r"))
1495 (sign_extend:DI
1496 (match_operand:SI 3 "register_operand" "r")))))]
1497 "TARGET_REALLY_IWMMXT"
1498 "tmia%?\\t%0, %2, %3"
1499 [(set_attr "predicable" "yes")
1500 (set_attr "wtype" "tmia")]
1501 )
1503 (define_insn "iwmmxt_tmiaph"
1504 [(set (match_operand:DI 0 "register_operand" "=y")
1505 (plus:DI (match_operand:DI 1 "register_operand" "0")
1506 (plus:DI
1507 (mult:DI (sign_extend:DI
1508 (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1509 (sign_extend:DI
1510 (truncate:HI (match_operand:SI 3 "register_operand" "r"))))
1511 (mult:DI (sign_extend:DI
1512 (truncate:HI (ashiftrt:SI (match_dup 2) (const_int 16))))
1513 (sign_extend:DI
1514 (truncate:HI (ashiftrt:SI (match_dup 3) (const_int 16))))))))]
1515 "TARGET_REALLY_IWMMXT"
1516 "tmiaph%?\\t%0, %2, %3"
1517 [(set_attr "predicable" "yes")
1518 (set_attr "wtype" "tmiaph")]
1519 )
1521 (define_insn "iwmmxt_tmiabb"
1522 [(set (match_operand:DI 0 "register_operand" "=y")
1523 (plus:DI (match_operand:DI 1 "register_operand" "0")
1524 (mult:DI (sign_extend:DI
1525 (truncate:HI (match_operand:SI 2 "register_operand" "r")))
1526 (sign_extend:DI
1527 (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))]
1528 "TARGET_REALLY_IWMMXT"
1529 "tmiabb%?\\t%0, %2, %3"
1530 [(set_attr "predicable" "yes")
1531 (set_attr "wtype" "tmiaxy")]
1532 )
1534 (define_insn "iwmmxt_tmiatb"
1535 [(set (match_operand:DI 0 "register_operand" "=y")
1536 (plus:DI (match_operand:DI 1 "register_operand" "0")
1537 (mult:DI (sign_extend:DI
1538 (truncate:HI
1539 (ashiftrt:SI
1540 (match_operand:SI 2 "register_operand" "r")
1541 (const_int 16))))
1542 (sign_extend:DI
1543 (truncate:HI
1544 (match_operand:SI 3 "register_operand" "r"))))))]
1545 "TARGET_REALLY_IWMMXT"
1546 "tmiatb%?\\t%0, %2, %3"
1547 [(set_attr "predicable" "yes")
1548 (set_attr "wtype" "tmiaxy")]
1549 )
1551 (define_insn "iwmmxt_tmiabt"
1552 [(set (match_operand:DI 0 "register_operand" "=y")
1553 (plus:DI (match_operand:DI 1 "register_operand" "0")
1554 (mult:DI (sign_extend:DI
1555 (truncate:HI
1556 (match_operand:SI 2 "register_operand" "r")))
1557 (sign_extend:DI
1558 (truncate:HI
1559 (ashiftrt:SI
1560 (match_operand:SI 3 "register_operand" "r")
1561 (const_int 16)))))))]
1562 "TARGET_REALLY_IWMMXT"
1563 "tmiabt%?\\t%0, %2, %3"
1564 [(set_attr "predicable" "yes")
1565 (set_attr "wtype" "tmiaxy")]
1566 )
1568 (define_insn "iwmmxt_tmiatt"
1569 [(set (match_operand:DI 0 "register_operand" "=y")
1570 (plus:DI (match_operand:DI 1 "register_operand" "0")
1571 (mult:DI (sign_extend:DI
1572 (truncate:HI
1573 (ashiftrt:SI
1574 (match_operand:SI 2 "register_operand" "r")
1575 (const_int 16))))
1576 (sign_extend:DI
1577 (truncate:HI
1578 (ashiftrt:SI
1579 (match_operand:SI 3 "register_operand" "r")
1580 (const_int 16)))))))]
1581 "TARGET_REALLY_IWMMXT"
1582 "tmiatt%?\\t%0, %2, %3"
1583 [(set_attr "predicable" "yes")
1584 (set_attr "wtype" "tmiaxy")]
1585 )
1587 (define_insn "iwmmxt_tmovmskb"
1588 [(set (match_operand:SI 0 "register_operand" "=r")
1589 (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1590 "TARGET_REALLY_IWMMXT"
1591 "tmovmskb%?\\t%0, %1"
1592 [(set_attr "predicable" "yes")
1593 (set_attr "wtype" "tmovmsk")]
1594 )
1596 (define_insn "iwmmxt_tmovmskh"
1597 [(set (match_operand:SI 0 "register_operand" "=r")
1598 (unspec:SI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1599 "TARGET_REALLY_IWMMXT"
1600 "tmovmskh%?\\t%0, %1"
1601 [(set_attr "predicable" "yes")
1602 (set_attr "wtype" "tmovmsk")]
1603 )
1605 (define_insn "iwmmxt_tmovmskw"
1606 [(set (match_operand:SI 0 "register_operand" "=r")
1607 (unspec:SI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_TMOVMSK))]
1608 "TARGET_REALLY_IWMMXT"
1609 "tmovmskw%?\\t%0, %1"
1610 [(set_attr "predicable" "yes")
1611 (set_attr "wtype" "tmovmsk")]
1612 )
1614 (define_insn "iwmmxt_waccb"
1615 [(set (match_operand:DI 0 "register_operand" "=y")
1616 (unspec:DI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_WACC))]
1617 "TARGET_REALLY_IWMMXT"
1618 "waccb%?\\t%0, %1"
1619 [(set_attr "predicable" "yes")
1620 (set_attr "wtype" "wacc")]
1621 )
1623 (define_insn "iwmmxt_wacch"
1624 [(set (match_operand:DI 0 "register_operand" "=y")
1625 (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_WACC))]
1626 "TARGET_REALLY_IWMMXT"
1627 "wacch%?\\t%0, %1"
1628 [(set_attr "predicable" "yes")
1629 (set_attr "wtype" "wacc")]
1630 )
1632 (define_insn "iwmmxt_waccw"
1633 [(set (match_operand:DI 0 "register_operand" "=y")
1634 (unspec:DI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_WACC))]
1635 "TARGET_REALLY_IWMMXT"
1636 "waccw%?\\t%0, %1"
1637 [(set_attr "predicable" "yes")
1638 (set_attr "wtype" "wacc")]
1639 )
1641 ;; use unspec here to prevent 8 * imm to be optimized by cse
1642 (define_insn "iwmmxt_waligni"
1643 [(set (match_operand:V8QI 0 "register_operand" "=y")
1644 (unspec:V8QI [(subreg:V8QI
1645 (ashiftrt:TI
1646 (subreg:TI (vec_concat:V16QI
1647 (match_operand:V8QI 1 "register_operand" "y")
1648 (match_operand:V8QI 2 "register_operand" "y")) 0)
1649 (mult:SI
1650 (match_operand:SI 3 "immediate_operand" "i")
1651 (const_int 8))) 0)] UNSPEC_WALIGNI))]
1652 "TARGET_REALLY_IWMMXT"
1653 "waligni%?\\t%0, %1, %2, %3"
1654 [(set_attr "predicable" "yes")
1655 (set_attr "wtype" "waligni")]
1656 )
1658 (define_insn "iwmmxt_walignr"
1659 [(set (match_operand:V8QI 0 "register_operand" "=y")
1660 (subreg:V8QI (ashiftrt:TI
1661 (subreg:TI (vec_concat:V16QI
1662 (match_operand:V8QI 1 "register_operand" "y")
1663 (match_operand:V8QI 2 "register_operand" "y")) 0)
1664 (mult:SI
1665 (zero_extract:SI (match_operand:SI 3 "register_operand" "z") (const_int 3) (const_int 0))
1666 (const_int 8))) 0))]
1667 "TARGET_REALLY_IWMMXT"
1668 "walignr%U3%?\\t%0, %1, %2"
1669 [(set_attr "predicable" "yes")
1670 (set_attr "wtype" "walignr")]
1671 )
1673 (define_insn "iwmmxt_walignr0"
1674 [(set (match_operand:V8QI 0 "register_operand" "=y")
1675 (subreg:V8QI (ashiftrt:TI
1676 (subreg:TI (vec_concat:V16QI
1677 (match_operand:V8QI 1 "register_operand" "y")
1678 (match_operand:V8QI 2 "register_operand" "y")) 0)
1679 (mult:SI
1680 (zero_extract:SI (reg:SI WCGR0) (const_int 3) (const_int 0))
1681 (const_int 8))) 0))]
1682 "TARGET_REALLY_IWMMXT"
1683 "walignr0%?\\t%0, %1, %2"
1684 [(set_attr "predicable" "yes")
1685 (set_attr "wtype" "walignr")]
1686 )
1688 (define_insn "iwmmxt_walignr1"
1689 [(set (match_operand:V8QI 0 "register_operand" "=y")
1690 (subreg:V8QI (ashiftrt:TI
1691 (subreg:TI (vec_concat:V16QI
1692 (match_operand:V8QI 1 "register_operand" "y")
1693 (match_operand:V8QI 2 "register_operand" "y")) 0)
1694 (mult:SI
1695 (zero_extract:SI (reg:SI WCGR1) (const_int 3) (const_int 0))
1696 (const_int 8))) 0))]
1697 "TARGET_REALLY_IWMMXT"
1698 "walignr1%?\\t%0, %1, %2"
1699 [(set_attr "predicable" "yes")
1700 (set_attr "wtype" "walignr")]
1701 )
1703 (define_insn "iwmmxt_walignr2"
1704 [(set (match_operand:V8QI 0 "register_operand" "=y")
1705 (subreg:V8QI (ashiftrt:TI
1706 (subreg:TI (vec_concat:V16QI
1707 (match_operand:V8QI 1 "register_operand" "y")
1708 (match_operand:V8QI 2 "register_operand" "y")) 0)
1709 (mult:SI
1710 (zero_extract:SI (reg:SI WCGR2) (const_int 3) (const_int 0))
1711 (const_int 8))) 0))]
1712 "TARGET_REALLY_IWMMXT"
1713 "walignr2%?\\t%0, %1, %2"
1714 [(set_attr "predicable" "yes")
1715 (set_attr "wtype" "walignr")]
1716 )
1718 (define_insn "iwmmxt_walignr3"
1719 [(set (match_operand:V8QI 0 "register_operand" "=y")
1720 (subreg:V8QI (ashiftrt:TI
1721 (subreg:TI (vec_concat:V16QI
1722 (match_operand:V8QI 1 "register_operand" "y")
1723 (match_operand:V8QI 2 "register_operand" "y")) 0)
1724 (mult:SI
1725 (zero_extract:SI (reg:SI WCGR3) (const_int 3) (const_int 0))
1726 (const_int 8))) 0))]
1727 "TARGET_REALLY_IWMMXT"
1728 "walignr3%?\\t%0, %1, %2"
1729 [(set_attr "predicable" "yes")
1730 (set_attr "wtype" "walignr")]
1731 )
1733 (define_insn "iwmmxt_wsadb"
1734 [(set (match_operand:V2SI 0 "register_operand" "=y")
1735 (unspec:V2SI [
1736 (match_operand:V2SI 1 "register_operand" "0")
1737 (match_operand:V8QI 2 "register_operand" "y")
1738 (match_operand:V8QI 3 "register_operand" "y")] UNSPEC_WSAD))]
1739 "TARGET_REALLY_IWMMXT"
1740 "wsadb%?\\t%0, %2, %3"
1741 [(set_attr "predicable" "yes")
1742 (set_attr "wtype" "wsad")]
1743 )
1745 (define_insn "iwmmxt_wsadh"
1746 [(set (match_operand:V2SI 0 "register_operand" "=y")
1747 (unspec:V2SI [
1748 (match_operand:V2SI 1 "register_operand" "0")
1749 (match_operand:V4HI 2 "register_operand" "y")
1750 (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WSAD))]
1751 "TARGET_REALLY_IWMMXT"
1752 "wsadh%?\\t%0, %2, %3"
1753 [(set_attr "predicable" "yes")
1754 (set_attr "wtype" "wsad")]
1755 )
1757 (define_insn "iwmmxt_wsadbz"
1758 [(set (match_operand:V2SI 0 "register_operand" "=y")
1759 (unspec:V2SI [(match_operand:V8QI 1 "register_operand" "y")
1760 (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1761 "TARGET_REALLY_IWMMXT"
1762 "wsadbz%?\\t%0, %1, %2"
1763 [(set_attr "predicable" "yes")
1764 (set_attr "wtype" "wsad")]
1765 )
1767 (define_insn "iwmmxt_wsadhz"
1768 [(set (match_operand:V2SI 0 "register_operand" "=y")
1769 (unspec:V2SI [(match_operand:V4HI 1 "register_operand" "y")
1770 (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSADZ))]
1771 "TARGET_REALLY_IWMMXT"
1772 "wsadhz%?\\t%0, %1, %2"
1773 [(set_attr "predicable" "yes")
1774 (set_attr "wtype" "wsad")]
1775 )
1777 (include "iwmmxt2.md")