gcc/config/i386/ia32intrin.h

   1 /* Copyright (C) 2009-2017 Free Software Foundation, Inc.
   2
   3    This file is part of GCC.
   4
   5    GCC is free software; you can redistribute it and/or modify
   6    it under the terms of the GNU General Public License as published by
   7    the Free Software Foundation; either version 3, or (at your option)
   8    any later version.
   9
  10    GCC is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13    GNU General Public License for more details.
  14
  15    Under Section 7 of GPL version 3, you are granted additional
  16    permissions described in the GCC Runtime Library Exception, version
  17    3.1, as published by the Free Software Foundation.
  18
  19    You should have received a copy of the GNU General Public License and
  20    a copy of the GCC Runtime Library Exception along with this program;
  21    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
  22    <http://www.gnu.org/licenses/>.  */
  23
  24 #ifndef _X86INTRIN_H_INCLUDED
  25 # error "Never use <ia32intrin.h> directly; include <x86intrin.h> instead."
  26 #endif
  27
  28 /* 32bit bsf */
  29 extern __inline int
  30 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
  31 __bsfd (int __X)
  32 {
  33   return __builtin_ctz (__X);
  34 }
  35
  36 /* 32bit bsr */
  37 extern __inline int
  38 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
  39 __bsrd (int __X)
  40 {
  41   return __builtin_ia32_bsrsi (__X);
  42 }
  43
  44 /* 32bit bswap */
  45 extern __inline int
  46 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
  47 __bswapd (int __X)
  48 {
  49   return __builtin_bswap32 (__X);
  50 }
  51
  52 #ifndef __iamcu__
  53
  54 #ifndef __SSE4_2__
  55 #pragma GCC push_options
  56 #pragma GCC target("sse4.2")
  57 #define __DISABLE_SSE4_2__
  58 #endif /* __SSE4_2__ */
  59
  60 /* 32bit accumulate CRC32 (polynomial 0x11EDC6F41) value.  */
  61 extern __inline unsigned int
  62 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
  63 __crc32b (unsigned int __C, unsigned char __V)
  64 {
  65   return __builtin_ia32_crc32qi (__C, __V);
  66 }
  67
  68 extern __inline unsigned int
  69 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
  70 __crc32w (unsigned int __C, unsigned short __V)
  71 {
  72   return __builtin_ia32_crc32hi (__C, __V);
  73 }
  74
  75 extern __inline unsigned int
  76 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
  77 __crc32d (unsigned int __C, unsigned int __V)
  78 {
  79   return __builtin_ia32_crc32si (__C, __V);
  80 }
  81
  82 #ifdef __DISABLE_SSE4_2__
  83 #undef __DISABLE_SSE4_2__
  84 #pragma GCC pop_options
  85 #endif /* __DISABLE_SSE4_2__ */
  86
  87 #endif /* __iamcu__ */
  88
  89 /* 32bit popcnt */
  90 extern __inline int
  91 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
  92 __popcntd (unsigned int __X)
  93 {
  94   return __builtin_popcount (__X);
  95 }
  96
  97 #ifndef __iamcu__
  98
  99 /* rdpmc */
 100 extern __inline unsigned long long
 101 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 102 __rdpmc (int __S)
 103 {
 104   return __builtin_ia32_rdpmc (__S);
 105 }
 106
 107 #endif /* __iamcu__ */
 108
 109 /* rdtsc */
 110 extern __inline unsigned long long
 111 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 112 __rdtsc (void)
 113 {
 114   return __builtin_ia32_rdtsc ();
 115 }
 116
 117 #ifndef __iamcu__
 118
 119 /* rdtscp */
 120 extern __inline unsigned long long
 121 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 122 __rdtscp (unsigned int *__A)
 123 {
 124   return __builtin_ia32_rdtscp (__A);
 125 }
 126
 127 #endif /* __iamcu__ */
 128
 129 /* 8bit rol */
 130 extern __inline unsigned char
 131 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 132 __rolb (unsigned char __X, int __C)
 133 {
 134   return __builtin_ia32_rolqi (__X, __C);
 135 }
 136
 137 /* 16bit rol */
 138 extern __inline unsigned short
 139 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 140 __rolw (unsigned short __X, int __C)
 141 {
 142   return __builtin_ia32_rolhi (__X, __C);
 143 }
 144
 145 /* 32bit rol */
 146 extern __inline unsigned int
 147 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 148 __rold (unsigned int __X, int __C)
 149 {
 150   return (__X << __C) | (__X >> (32 - __C));
 151 }
 152
 153 /* 8bit ror */
 154 extern __inline unsigned char
 155 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 156 __rorb (unsigned char __X, int __C)
 157 {
 158   return __builtin_ia32_rorqi (__X, __C);
 159 }
 160
 161 /* 16bit ror */
 162 extern __inline unsigned short
 163 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 164 __rorw (unsigned short __X, int __C)
 165 {
 166   return __builtin_ia32_rorhi (__X, __C);
 167 }
 168
 169 /* 32bit ror */
 170 extern __inline unsigned int
 171 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 172 __rord (unsigned int __X, int __C)
 173 {
 174   return (__X >> __C) | (__X << (32 - __C));
 175 }
 176
 177 /* Pause */
 178 extern __inline void
 179 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 180 __pause (void)
 181 {
 182   __builtin_ia32_pause ();
 183 }
 184
 185 #ifdef __x86_64__
 186 /* 64bit bsf */
 187 extern __inline int
 188 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 189 __bsfq (long long __X)
 190 {
 191   return __builtin_ctzll (__X);
 192 }
 193
 194 /* 64bit bsr */
 195 extern __inline int
 196 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 197 __bsrq (long long __X)
 198 {
 199   return __builtin_ia32_bsrdi (__X);
 200 }
 201
 202 /* 64bit bswap */
 203 extern __inline long long
 204 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 205 __bswapq (long long __X)
 206 {
 207   return __builtin_bswap64 (__X);
 208 }
 209
 210 #ifndef __SSE4_2__
 211 #pragma GCC push_options
 212 #pragma GCC target("sse4.2")
 213 #define __DISABLE_SSE4_2__
 214 #endif /* __SSE4_2__ */
 215
 216 /* 64bit accumulate CRC32 (polynomial 0x11EDC6F41) value.  */
 217 extern __inline unsigned long long
 218 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 219 __crc32q (unsigned long long __C, unsigned long long __V)
 220 {
 221   return __builtin_ia32_crc32di (__C, __V);
 222 }
 223
 224 #ifdef __DISABLE_SSE4_2__
 225 #undef __DISABLE_SSE4_2__
 226 #pragma GCC pop_options
 227 #endif /* __DISABLE_SSE4_2__ */
 228
 229 /* 64bit popcnt */
 230 extern __inline long long
 231 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 232 __popcntq (unsigned long long __X)
 233 {
 234   return __builtin_popcountll (__X);
 235 }
 236
 237 /* 64bit rol */
 238 extern __inline unsigned long long
 239 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 240 __rolq (unsigned long long __X, int __C)
 241 {
 242   return (__X << __C) | (__X >> (64 - __C));
 243 }
 244
 245 /* 64bit ror */
 246 extern __inline unsigned long long
 247 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 248 __rorq (unsigned long long __X, int __C)
 249 {
 250   return (__X >> __C) | (__X << (64 - __C));
 251 }
 252
 253 /* Read flags register */
 254 extern __inline unsigned long long
 255 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 256 __readeflags (void)
 257 {
 258   return __builtin_ia32_readeflags_u64 ();
 259 }
 260
 261 /* Write flags register */
 262 extern __inline void
 263 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 264 __writeeflags (unsigned long long __X)
 265 {
 266   __builtin_ia32_writeeflags_u64 (__X);
 267 }
 268
 269 #define _bswap64(a)             __bswapq(a)
 270 #define _popcnt64(a)            __popcntq(a)
 271 #else
 272
 273 /* Read flags register */
 274 extern __inline unsigned int
 275 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 276 __readeflags (void)
 277 {
 278   return __builtin_ia32_readeflags_u32 ();
 279 }
 280
 281 /* Write flags register */
 282 extern __inline void
 283 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
 284 __writeeflags (unsigned int __X)
 285 {
 286   __builtin_ia32_writeeflags_u32 (__X);
 287 }
 288
 289 #endif
 290
 291 /* On LP64 systems, longs are 64-bit.  Use the appropriate rotate
 292  * function.  */
 293 #ifdef __LP64__
 294 #define _lrotl(a,b)             __rolq((a), (b))
 295 #define _lrotr(a,b)             __rorq((a), (b))
 296 #else
 297 #define _lrotl(a,b)             __rold((a), (b))
 298 #define _lrotr(a,b)             __rord((a), (b))
 299 #endif
 300
 301 #define _bit_scan_forward(a)    __bsfd(a)
 302 #define _bit_scan_reverse(a)    __bsrd(a)
 303 #define _bswap(a)               __bswapd(a)
 304 #define _popcnt32(a)            __popcntd(a)
 305 #ifndef __iamcu__
 306 #define _rdpmc(a)               __rdpmc(a)
 307 #define _rdtscp(a)              __rdtscp(a)
 308 #endif /* __iamcu__ */
 309 #define _rdtsc()                __rdtsc()
 310 #define _rotwl(a,b)             __rolw((a), (b))
 311 #define _rotwr(a,b)             __rorw((a), (b))
 312 #define _rotl(a,b)              __rold((a), (b))
 313 #define _rotr(a,b)              __rord((a), (b))