gcc/config/i386/driver-i386.c

   1 /* Subroutines for the gcc driver.
   2    Copyright (C) 2006-2017 Free Software Foundation, Inc.
   3
   4 This file is part of GCC.
   5
   6 GCC is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 3, or (at your option)
   9 any later version.
  10
  11 GCC is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with GCC; see the file COPYING3.  If not see
  18 <http://www.gnu.org/licenses/>.  */
  19
  20 #include "config.h"
  21 #include "system.h"
  22 #include "coretypes.h"
  23 #include "tm.h"
  24
  25 const char *host_detect_local_cpu (int argc, const char **argv);
  26
  27 #if defined(__GNUC__) && (__GNUC__ >= 5 || !defined(__PIC__))
  28 #include "cpuid.h"
  29
  30 struct cache_desc
  31 {
  32   unsigned sizekb;
  33   unsigned assoc;
  34   unsigned line;
  35 };
  36
  37 /* Returns command line parameters that describe size and
  38    cache line size of the processor caches.  */
  39
  40 static char *
  41 describe_cache (struct cache_desc level1, struct cache_desc level2)
  42 {
  43   char size[100], line[100], size2[100];
  44
  45   /* At the moment, gcc does not use the information
  46      about the associativity of the cache.  */
  47
  48   snprintf (size, sizeof (size),
  49             "--param l1-cache-size=%u ", level1.sizekb);
  50   snprintf (line, sizeof (line),
  51             "--param l1-cache-line-size=%u ", level1.line);
  52
  53   snprintf (size2, sizeof (size2),
  54             "--param l2-cache-size=%u ", level2.sizekb);
  55
  56   return concat (size, line, size2, NULL);
  57 }
  58
  59 /* Detect L2 cache parameters using CPUID extended function 0x80000006.  */
  60
  61 static void
  62 detect_l2_cache (struct cache_desc *level2)
  63 {
  64   unsigned eax, ebx, ecx, edx;
  65   unsigned assoc;
  66
  67   __cpuid (0x80000006, eax, ebx, ecx, edx);
  68
  69   level2->sizekb = (ecx >> 16) & 0xffff;
  70   level2->line = ecx & 0xff;
  71
  72   assoc = (ecx >> 12) & 0xf;
  73   if (assoc == 6)
  74     assoc = 8;
  75   else if (assoc == 8)
  76     assoc = 16;
  77   else if (assoc >= 0xa && assoc <= 0xc)
  78     assoc = 32 + (assoc - 0xa) * 16;
  79   else if (assoc >= 0xd && assoc <= 0xe)
  80     assoc = 96 + (assoc - 0xd) * 32;
  81
  82   level2->assoc = assoc;
  83 }
  84
  85 /* Returns the description of caches for an AMD processor.  */
  86
  87 static const char *
  88 detect_caches_amd (unsigned max_ext_level)
  89 {
  90   unsigned eax, ebx, ecx, edx;
  91
  92   struct cache_desc level1, level2 = {0, 0, 0};
  93
  94   if (max_ext_level < 0x80000005)
  95     return "";
  96
  97   __cpuid (0x80000005, eax, ebx, ecx, edx);
  98
  99   level1.sizekb = (ecx >> 24) & 0xff;
 100   level1.assoc = (ecx >> 16) & 0xff;
 101   level1.line = ecx & 0xff;
 102
 103   if (max_ext_level >= 0x80000006)
 104     detect_l2_cache (&level2);
 105
 106   return describe_cache (level1, level2);
 107 }
 108
 109 /* Decodes the size, the associativity and the cache line size of
 110    L1/L2 caches of an Intel processor.  Values are based on
 111    "Intel Processor Identification and the CPUID Instruction"
 112    [Application Note 485], revision -032, December 2007.  */
 113
 114 static void
 115 decode_caches_intel (unsigned reg, bool xeon_mp,
 116                      struct cache_desc *level1, struct cache_desc *level2)
 117 {
 118   int i;
 119
 120   for (i = 24; i >= 0; i -= 8)
 121     switch ((reg >> i) & 0xff)
 122       {
 123       case 0x0a:
 124         level1->sizekb = 8; level1->assoc = 2; level1->line = 32;
 125         break;
 126       case 0x0c:
 127         level1->sizekb = 16; level1->assoc = 4; level1->line = 32;
 128         break;
 129       case 0x0d:
 130         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 131         break;
 132       case 0x0e:
 133         level1->sizekb = 24; level1->assoc = 6; level1->line = 64;
 134         break;
 135       case 0x21:
 136         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 137         break;
 138       case 0x24:
 139         level2->sizekb = 1024; level2->assoc = 16; level2->line = 64;
 140         break;
 141       case 0x2c:
 142         level1->sizekb = 32; level1->assoc = 8; level1->line = 64;
 143         break;
 144       case 0x39:
 145         level2->sizekb = 128; level2->assoc = 4; level2->line = 64;
 146         break;
 147       case 0x3a:
 148         level2->sizekb = 192; level2->assoc = 6; level2->line = 64;
 149         break;
 150       case 0x3b:
 151         level2->sizekb = 128; level2->assoc = 2; level2->line = 64;
 152         break;
 153       case 0x3c:
 154         level2->sizekb = 256; level2->assoc = 4; level2->line = 64;
 155         break;
 156       case 0x3d:
 157         level2->sizekb = 384; level2->assoc = 6; level2->line = 64;
 158         break;
 159       case 0x3e:
 160         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 161         break;
 162       case 0x41:
 163         level2->sizekb = 128; level2->assoc = 4; level2->line = 32;
 164         break;
 165       case 0x42:
 166         level2->sizekb = 256; level2->assoc = 4; level2->line = 32;
 167         break;
 168       case 0x43:
 169         level2->sizekb = 512; level2->assoc = 4; level2->line = 32;
 170         break;
 171       case 0x44:
 172         level2->sizekb = 1024; level2->assoc = 4; level2->line = 32;
 173         break;
 174       case 0x45:
 175         level2->sizekb = 2048; level2->assoc = 4; level2->line = 32;
 176         break;
 177       case 0x48:
 178         level2->sizekb = 3072; level2->assoc = 12; level2->line = 64;
 179         break;
 180       case 0x49:
 181         if (xeon_mp)
 182           break;
 183         level2->sizekb = 4096; level2->assoc = 16; level2->line = 64;
 184         break;
 185       case 0x4e:
 186         level2->sizekb = 6144; level2->assoc = 24; level2->line = 64;
 187         break;
 188       case 0x60:
 189         level1->sizekb = 16; level1->assoc = 8; level1->line = 64;
 190         break;
 191       case 0x66:
 192         level1->sizekb = 8; level1->assoc = 4; level1->line = 64;
 193         break;
 194       case 0x67:
 195         level1->sizekb = 16; level1->assoc = 4; level1->line = 64;
 196         break;
 197       case 0x68:
 198         level1->sizekb = 32; level1->assoc = 4; level1->line = 64;
 199         break;
 200       case 0x78:
 201         level2->sizekb = 1024; level2->assoc = 4; level2->line = 64;
 202         break;
 203       case 0x79:
 204         level2->sizekb = 128; level2->assoc = 8; level2->line = 64;
 205         break;
 206       case 0x7a:
 207         level2->sizekb = 256; level2->assoc = 8; level2->line = 64;
 208         break;
 209       case 0x7b:
 210         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 211         break;
 212       case 0x7c:
 213         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 214         break;
 215       case 0x7d:
 216         level2->sizekb = 2048; level2->assoc = 8; level2->line = 64;
 217         break;
 218       case 0x7f:
 219         level2->sizekb = 512; level2->assoc = 2; level2->line = 64;
 220         break;
 221       case 0x80:
 222         level2->sizekb = 512; level2->assoc = 8; level2->line = 64;
 223         break;
 224       case 0x82:
 225         level2->sizekb = 256; level2->assoc = 8; level2->line = 32;
 226         break;
 227       case 0x83:
 228         level2->sizekb = 512; level2->assoc = 8; level2->line = 32;
 229         break;
 230       case 0x84:
 231         level2->sizekb = 1024; level2->assoc = 8; level2->line = 32;
 232         break;
 233       case 0x85:
 234         level2->sizekb = 2048; level2->assoc = 8; level2->line = 32;
 235         break;
 236       case 0x86:
 237         level2->sizekb = 512; level2->assoc = 4; level2->line = 64;
 238         break;
 239       case 0x87:
 240         level2->sizekb = 1024; level2->assoc = 8; level2->line = 64;
 241
 242       default:
 243         break;
 244       }
 245 }
 246
 247 /* Detect cache parameters using CPUID function 2.  */
 248
 249 static void
 250 detect_caches_cpuid2 (bool xeon_mp,
 251                       struct cache_desc *level1, struct cache_desc *level2)
 252 {
 253   unsigned regs[4];
 254   int nreps, i;
 255
 256   __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 257
 258   nreps = regs[0] & 0x0f;
 259   regs[0] &= ~0x0f;
 260
 261   while (--nreps >= 0)
 262     {
 263       for (i = 0; i < 4; i++)
 264         if (regs[i] && !((regs[i] >> 31) & 1))
 265           decode_caches_intel (regs[i], xeon_mp, level1, level2);
 266
 267       if (nreps)
 268         __cpuid (2, regs[0], regs[1], regs[2], regs[3]);
 269     }
 270 }
 271
 272 /* Detect cache parameters using CPUID function 4. This
 273    method doesn't require hardcoded tables.  */
 274
 275 enum cache_type
 276 {
 277   CACHE_END = 0,
 278   CACHE_DATA = 1,
 279   CACHE_INST = 2,
 280   CACHE_UNIFIED = 3
 281 };
 282
 283 static void
 284 detect_caches_cpuid4 (struct cache_desc *level1, struct cache_desc *level2,
 285                       struct cache_desc *level3)
 286 {
 287   struct cache_desc *cache;
 288
 289   unsigned eax, ebx, ecx, edx;
 290   int count;
 291
 292   for (count = 0;; count++)
 293     {
 294       __cpuid_count(4, count, eax, ebx, ecx, edx);
 295       switch (eax & 0x1f)
 296         {
 297         case CACHE_END:
 298           return;
 299         case CACHE_DATA:
 300         case CACHE_UNIFIED:
 301           {
 302             switch ((eax >> 5) & 0x07)
 303               {
 304               case 1:
 305                 cache = level1;
 306                 break;
 307               case 2:
 308                 cache = level2;
 309                 break;
 310               case 3:
 311                 cache = level3;
 312                 break;
 313               default:
 314                 cache = NULL;
 315               }
 316
 317             if (cache)
 318               {
 319                 unsigned sets = ecx + 1;
 320                 unsigned part = ((ebx >> 12) & 0x03ff) + 1;
 321
 322                 cache->assoc = ((ebx >> 22) & 0x03ff) + 1;
 323                 cache->line = (ebx & 0x0fff) + 1;
 324
 325                 cache->sizekb = (cache->assoc * part
 326                                  * cache->line * sets) / 1024;
 327               }
 328           }
 329         default:
 330           break;
 331         }
 332     }
 333 }
 334
 335 /* Returns the description of caches for an Intel processor.  */
 336
 337 static const char *
 338 detect_caches_intel (bool xeon_mp, unsigned max_level,
 339                      unsigned max_ext_level, unsigned *l2sizekb)
 340 {
 341   struct cache_desc level1 = {0, 0, 0}, level2 = {0, 0, 0}, level3 = {0, 0, 0};
 342
 343   if (max_level >= 4)
 344     detect_caches_cpuid4 (&level1, &level2, &level3);
 345   else if (max_level >= 2)
 346     detect_caches_cpuid2 (xeon_mp, &level1, &level2);
 347   else
 348     return "";
 349
 350   if (level1.sizekb == 0)
 351     return "";
 352
 353   /* Let the L3 replace the L2. This assumes inclusive caches
 354      and single threaded program for now. */
 355   if (level3.sizekb)
 356     level2 = level3;
 357
 358   /* Intel CPUs are equipped with AMD style L2 cache info.  Try this
 359      method if other methods fail to provide L2 cache parameters.  */
 360   if (level2.sizekb == 0 && max_ext_level >= 0x80000006)
 361     detect_l2_cache (&level2);
 362
 363   *l2sizekb = level2.sizekb;
 364
 365   return describe_cache (level1, level2);
 366 }
 367
 368 /* This will be called by the spec parser in gcc.c when it sees
 369    a %:local_cpu_detect(args) construct.  Currently it will be called
 370    with either "arch" or "tune" as argument depending on if -march=native
 371    or -mtune=native is to be substituted.
 372
 373    It returns a string containing new command line parameters to be
 374    put at the place of the above two options, depending on what CPU
 375    this is executed.  E.g. "-march=k8" on an AMD64 machine
 376    for -march=native.
 377
 378    ARGC and ARGV are set depending on the actual arguments given
 379    in the spec.  */
 380
 381 const char *host_detect_local_cpu (int argc, const char **argv)
 382 {
 383   enum processor_type processor = PROCESSOR_I386;
 384   const char *cpu = "i386";
 385
 386   const char *cache = "";
 387   const char *options = "";
 388
 389   unsigned int eax, ebx, ecx, edx;
 390
 391   unsigned int max_level, ext_level;
 392
 393   unsigned int vendor;
 394   unsigned int model, family;
 395
 396   unsigned int has_sse3, has_ssse3, has_cmpxchg16b;
 397   unsigned int has_cmpxchg8b, has_cmov, has_mmx, has_sse, has_sse2;
 398
 399   /* Extended features */
 400   unsigned int has_lahf_lm = 0, has_sse4a = 0;
 401   unsigned int has_longmode = 0, has_3dnowp = 0, has_3dnow = 0;
 402   unsigned int has_movbe = 0, has_sse4_1 = 0, has_sse4_2 = 0;
 403   unsigned int has_popcnt = 0, has_aes = 0, has_avx = 0, has_avx2 = 0;
 404   unsigned int has_pclmul = 0, has_abm = 0, has_lwp = 0;
 405   unsigned int has_fma = 0, has_fma4 = 0, has_xop = 0;
 406   unsigned int has_bmi = 0, has_bmi2 = 0, has_tbm = 0, has_lzcnt = 0;
 407   unsigned int has_hle = 0, has_rtm = 0, has_sgx = 0;
 408   unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0;
 409   unsigned int has_rdseed = 0, has_prfchw = 0, has_adx = 0;
 410   unsigned int has_osxsave = 0, has_fxsr = 0, has_xsave = 0, has_xsaveopt = 0;
 411   unsigned int has_avx512er = 0, has_avx512pf = 0, has_avx512cd = 0;
 412   unsigned int has_avx512f = 0, has_sha = 0, has_prefetchwt1 = 0;
 413   unsigned int has_clflushopt = 0, has_xsavec = 0, has_xsaves = 0;
 414   unsigned int has_avx512dq = 0, has_avx512bw = 0, has_avx512vl = 0;
 415   unsigned int has_avx512vbmi = 0, has_avx512ifma = 0, has_clwb = 0;
 416   unsigned int has_mwaitx = 0, has_clzero = 0, has_pku = 0, has_rdpid = 0;
 417   unsigned int has_avx5124fmaps = 0, has_avx5124vnniw = 0;
 418
 419   bool arch;
 420
 421   unsigned int l2sizekb = 0;
 422
 423   if (argc < 1)
 424     return NULL;
 425
 426   arch = !strcmp (argv[0], "arch");
 427
 428   if (!arch && strcmp (argv[0], "tune"))
 429     return NULL;
 430
 431   max_level = __get_cpuid_max (0, &vendor);
 432   if (max_level < 1)
 433     goto done;
 434
 435   __cpuid (1, eax, ebx, ecx, edx);
 436
 437   model = (eax >> 4) & 0x0f;
 438   family = (eax >> 8) & 0x0f;
 439   if (vendor == signature_INTEL_ebx
 440       || vendor == signature_AMD_ebx)
 441     {
 442       unsigned int extended_model, extended_family;
 443
 444       extended_model = (eax >> 12) & 0xf0;
 445       extended_family = (eax >> 20) & 0xff;
 446       if (family == 0x0f)
 447         {
 448           family += extended_family;
 449           model += extended_model;
 450         }
 451       else if (family == 0x06)
 452         model += extended_model;
 453     }
 454
 455   has_sse3 = ecx & bit_SSE3;
 456   has_ssse3 = ecx & bit_SSSE3;
 457   has_sse4_1 = ecx & bit_SSE4_1;
 458   has_sse4_2 = ecx & bit_SSE4_2;
 459   has_avx = ecx & bit_AVX;
 460   has_osxsave = ecx & bit_OSXSAVE;
 461   has_cmpxchg16b = ecx & bit_CMPXCHG16B;
 462   has_movbe = ecx & bit_MOVBE;
 463   has_popcnt = ecx & bit_POPCNT;
 464   has_aes = ecx & bit_AES;
 465   has_pclmul = ecx & bit_PCLMUL;
 466   has_fma = ecx & bit_FMA;
 467   has_f16c = ecx & bit_F16C;
 468   has_rdrnd = ecx & bit_RDRND;
 469   has_xsave = ecx & bit_XSAVE;
 470
 471   has_cmpxchg8b = edx & bit_CMPXCHG8B;
 472   has_cmov = edx & bit_CMOV;
 473   has_mmx = edx & bit_MMX;
 474   has_fxsr = edx & bit_FXSAVE;
 475   has_sse = edx & bit_SSE;
 476   has_sse2 = edx & bit_SSE2;
 477
 478   if (max_level >= 7)
 479     {
 480       __cpuid_count (7, 0, eax, ebx, ecx, edx);
 481
 482       has_bmi = ebx & bit_BMI;
 483       has_sgx = ebx & bit_SGX;
 484       has_hle = ebx & bit_HLE;
 485       has_rtm = ebx & bit_RTM;
 486       has_avx2 = ebx & bit_AVX2;
 487       has_bmi2 = ebx & bit_BMI2;
 488       has_fsgsbase = ebx & bit_FSGSBASE;
 489       has_rdseed = ebx & bit_RDSEED;
 490       has_adx = ebx & bit_ADX;
 491       has_avx512f = ebx & bit_AVX512F;
 492       has_avx512er = ebx & bit_AVX512ER;
 493       has_avx512pf = ebx & bit_AVX512PF;
 494       has_avx512cd = ebx & bit_AVX512CD;
 495       has_sha = ebx & bit_SHA;
 496       has_clflushopt = ebx & bit_CLFLUSHOPT;
 497       has_clwb = ebx & bit_CLWB;
 498       has_avx512dq = ebx & bit_AVX512DQ;
 499       has_avx512bw = ebx & bit_AVX512BW;
 500       has_avx512vl = ebx & bit_AVX512VL;
 501       has_avx512ifma = ebx & bit_AVX512IFMA;
 502
 503       has_prefetchwt1 = ecx & bit_PREFETCHWT1;
 504       has_avx512vbmi = ecx & bit_AVX512VBMI;
 505       has_pku = ecx & bit_OSPKE;
 506       has_rdpid = ecx & bit_RDPID;
 507
 508       has_avx5124vnniw = edx & bit_AVX5124VNNIW;
 509       has_avx5124fmaps = edx & bit_AVX5124FMAPS;
 510     }
 511
 512   if (max_level >= 13)
 513     {
 514       __cpuid_count (13, 1, eax, ebx, ecx, edx);
 515
 516       has_xsaveopt = eax & bit_XSAVEOPT;
 517       has_xsavec = eax & bit_XSAVEC;
 518       has_xsaves = eax & bit_XSAVES;
 519     }
 520
 521   /* Check cpuid level of extended features.  */
 522   __cpuid (0x80000000, ext_level, ebx, ecx, edx);
 523
 524   if (ext_level >= 0x80000001)
 525     {
 526       __cpuid (0x80000001, eax, ebx, ecx, edx);
 527
 528       has_lahf_lm = ecx & bit_LAHF_LM;
 529       has_sse4a = ecx & bit_SSE4a;
 530       has_abm = ecx & bit_ABM;
 531       has_lwp = ecx & bit_LWP;
 532       has_fma4 = ecx & bit_FMA4;
 533       has_xop = ecx & bit_XOP;
 534       has_tbm = ecx & bit_TBM;
 535       has_lzcnt = ecx & bit_LZCNT;
 536       has_prfchw = ecx & bit_PRFCHW;
 537
 538       has_longmode = edx & bit_LM;
 539       has_3dnowp = edx & bit_3DNOWP;
 540       has_3dnow = edx & bit_3DNOW;
 541       has_mwaitx = ecx & bit_MWAITX;
 542     }
 543
 544   if (ext_level >= 0x80000008)
 545     {
 546       __cpuid (0x80000008, eax, ebx, ecx, edx);
 547       has_clzero = ebx & bit_CLZERO;
 548     }
 549
 550   /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv.  */
 551 #define XCR_XFEATURE_ENABLED_MASK       0x0
 552 #define XSTATE_FP                       0x1
 553 #define XSTATE_SSE                      0x2
 554 #define XSTATE_YMM                      0x4
 555 #define XSTATE_OPMASK                   0x20
 556 #define XSTATE_ZMM                      0x40
 557 #define XSTATE_HI_ZMM                   0x80
 558
 559 #define XCR_AVX_ENABLED_MASK \
 560   (XSTATE_SSE | XSTATE_YMM)
 561 #define XCR_AVX512F_ENABLED_MASK \
 562   (XSTATE_SSE | XSTATE_YMM | XSTATE_OPMASK | XSTATE_ZMM | XSTATE_HI_ZMM)
 563
 564   if (has_osxsave)
 565     asm (".byte 0x0f; .byte 0x01; .byte 0xd0"
 566          : "=a" (eax), "=d" (edx)
 567          : "c" (XCR_XFEATURE_ENABLED_MASK));
 568   else
 569     eax = 0;
 570
 571   /* Check if AVX registers are supported.  */
 572   if ((eax & XCR_AVX_ENABLED_MASK) != XCR_AVX_ENABLED_MASK)
 573     {
 574       has_avx = 0;
 575       has_avx2 = 0;
 576       has_fma = 0;
 577       has_fma4 = 0;
 578       has_f16c = 0;
 579       has_xop = 0;
 580       has_xsave = 0;
 581       has_xsaveopt = 0;
 582       has_xsaves = 0;
 583       has_xsavec = 0;
 584     }
 585
 586   /* Check if AVX512F registers are supported.  */
 587   if ((eax & XCR_AVX512F_ENABLED_MASK) != XCR_AVX512F_ENABLED_MASK)
 588     {
 589       has_avx512f = 0;
 590       has_avx512er = 0;
 591       has_avx512pf = 0;
 592       has_avx512cd = 0;
 593       has_avx512dq = 0;
 594       has_avx512bw = 0;
 595       has_avx512vl = 0;
 596     }
 597
 598   if (!arch)
 599     {
 600       if (vendor == signature_AMD_ebx
 601           || vendor == signature_CENTAUR_ebx
 602           || vendor == signature_CYRIX_ebx
 603           || vendor == signature_NSC_ebx)
 604         cache = detect_caches_amd (ext_level);
 605       else if (vendor == signature_INTEL_ebx)
 606         {
 607           bool xeon_mp = (family == 15 && model == 6);
 608           cache = detect_caches_intel (xeon_mp, max_level,
 609                                        ext_level, &l2sizekb);
 610         }
 611     }
 612
 613   if (vendor == signature_AMD_ebx)
 614     {
 615       unsigned int name;
 616
 617       /* Detect geode processor by its processor signature.  */
 618       if (ext_level >= 0x80000002)
 619         __cpuid (0x80000002, name, ebx, ecx, edx);
 620       else
 621         name = 0;
 622
 623       if (name == signature_NSC_ebx)
 624         processor = PROCESSOR_GEODE;
 625       else if (has_movbe && family == 22)
 626         processor = PROCESSOR_BTVER2;
 627       else if (has_clzero)
 628         processor = PROCESSOR_ZNVER1;
 629       else if (has_avx2)
 630         processor = PROCESSOR_BDVER4;
 631       else if (has_xsaveopt)
 632         processor = PROCESSOR_BDVER3;
 633       else if (has_bmi)
 634         processor = PROCESSOR_BDVER2;
 635       else if (has_xop)
 636         processor = PROCESSOR_BDVER1;
 637       else if (has_sse4a && has_ssse3)
 638         processor = PROCESSOR_BTVER1;
 639       else if (has_sse4a)
 640         processor = PROCESSOR_AMDFAM10;
 641       else if (has_sse2 || has_longmode)
 642         processor = PROCESSOR_K8;
 643       else if (has_3dnowp && family == 6)
 644         processor = PROCESSOR_ATHLON;
 645       else if (has_mmx)
 646         processor = PROCESSOR_K6;
 647       else
 648         processor = PROCESSOR_PENTIUM;
 649     }
 650   else if (vendor == signature_CENTAUR_ebx)
 651     {
 652       processor = PROCESSOR_GENERIC;
 653
 654       switch (family)
 655         {
 656         default:
 657           /* We have no idea.  */
 658           break;
 659
 660         case 5:
 661           if (has_3dnow || has_mmx)
 662             processor = PROCESSOR_I486;
 663           break;
 664
 665         case 6:
 666           if (has_longmode)
 667             processor = PROCESSOR_K8;
 668           else if (model >= 9)
 669             processor = PROCESSOR_PENTIUMPRO;
 670           else if (model >= 6)
 671             processor = PROCESSOR_I486;
 672         }
 673     }
 674   else
 675     {
 676       switch (family)
 677         {
 678         case 4:
 679           processor = PROCESSOR_I486;
 680           break;
 681         case 5:
 682           processor = PROCESSOR_PENTIUM;
 683           break;
 684         case 6:
 685           processor = PROCESSOR_PENTIUMPRO;
 686           break;
 687         case 15:
 688           processor = PROCESSOR_PENTIUM4;
 689           break;
 690         default:
 691           /* We have no idea.  */
 692           processor = PROCESSOR_GENERIC;
 693         }
 694     }
 695
 696   switch (processor)
 697     {
 698     case PROCESSOR_I386:
 699       /* Default.  */
 700       break;
 701     case PROCESSOR_I486:
 702       if (arch && vendor == signature_CENTAUR_ebx)
 703         {
 704           if (model >= 6)
 705             cpu = "c3";
 706           else if (has_3dnow)
 707             cpu = "winchip2";
 708           else
 709             /* Assume WinChip C6.  */
 710             cpu = "winchip-c6";
 711         }
 712       else
 713         cpu = "i486";
 714       break;
 715     case PROCESSOR_PENTIUM:
 716       if (arch && has_mmx)
 717         cpu = "pentium-mmx";
 718       else
 719         cpu = "pentium";
 720       break;
 721     case PROCESSOR_PENTIUMPRO:
 722       switch (model)
 723         {
 724         case 0x1c:
 725         case 0x26:
 726           /* Bonnell.  */
 727           cpu = "bonnell";
 728           break;
 729         case 0x37:
 730         case 0x4a:
 731         case 0x4d:
 732         case 0x5a:
 733         case 0x5d:
 734           /* Silvermont.  */
 735           cpu = "silvermont";
 736           break;
 737         case 0x0f:
 738           /* Merom.  */
 739         case 0x17:
 740         case 0x1d:
 741           /* Penryn.  */
 742           cpu = "core2";
 743           break;
 744         case 0x1a:
 745         case 0x1e:
 746         case 0x1f:
 747         case 0x2e:
 748           /* Nehalem.  */
 749           cpu = "nehalem";
 750           break;
 751         case 0x25:
 752         case 0x2c:
 753         case 0x2f:
 754           /* Westmere.  */
 755           cpu = "westmere";
 756           break;
 757         case 0x2a:
 758         case 0x2d:
 759           /* Sandy Bridge.  */
 760           cpu = "sandybridge";
 761           break;
 762         case 0x3a:
 763         case 0x3e:
 764           /* Ivy Bridge.  */
 765           cpu = "ivybridge";
 766           break;
 767         case 0x3c:
 768         case 0x3f:
 769         case 0x45:
 770         case 0x46:
 771           /* Haswell.  */
 772           cpu = "haswell";
 773           break;
 774         case 0x3d:
 775         case 0x47:
 776         case 0x4f:
 777         case 0x56:
 778           /* Broadwell.  */
 779           cpu = "broadwell";
 780           break;
 781         case 0x4e:
 782         case 0x5e:
 783           /* Skylake.  */
 784         case 0x8e:
 785         case 0x9e:
 786           /* Kaby Lake.  */
 787           cpu = "skylake";
 788           break;
 789         case 0x57:
 790           /* Knights Landing.  */
 791           cpu = "knl";
 792           break;
 793         case 0x85:
 794           /* Knights Mill. */
 795           cpu = "knm";
 796           break;
 797         default:
 798           if (arch)
 799             {
 800               /* This is unknown family 0x6 CPU.  */
 801               /* Assume Knights Landing.  */
 802               if (has_avx512f)
 803                 cpu = "knl";
 804               /* Assume Knights Mill */
 805               else if (has_avx5124vnniw)
 806                 cpu = "knm";
 807               /* Assume Skylake.  */
 808               else if (has_clflushopt)
 809                 cpu = "skylake";
 810               /* Assume Broadwell.  */
 811               else if (has_adx)
 812                 cpu = "broadwell";
 813               else if (has_avx2)
 814                 /* Assume Haswell.  */
 815                 cpu = "haswell";
 816               else if (has_avx)
 817                 /* Assume Sandy Bridge.  */
 818                 cpu = "sandybridge";
 819               else if (has_sse4_2)
 820                 {
 821                   if (has_movbe)
 822                     /* Assume Silvermont.  */
 823                     cpu = "silvermont";
 824                   else
 825                     /* Assume Nehalem.  */
 826                     cpu = "nehalem";
 827                 }
 828               else if (has_ssse3)
 829                 {
 830                   if (has_movbe)
 831                     /* Assume Bonnell.  */
 832                     cpu = "bonnell";
 833                   else
 834                     /* Assume Core 2.  */
 835                     cpu = "core2";
 836                 }
 837               else if (has_longmode)
 838                 /* Perhaps some emulator?  Assume x86-64, otherwise gcc
 839                    -march=native would be unusable for 64-bit compilations,
 840                    as all the CPUs below are 32-bit only.  */
 841                 cpu = "x86-64";
 842               else if (has_sse3)
 843                 {
 844                   if (vendor == signature_CENTAUR_ebx)
 845                     /* C7 / Eden "Esther" */
 846                     cpu = "c7";
 847                   else
 848                     /* It is Core Duo.  */
 849                     cpu = "pentium-m";
 850                 }
 851               else if (has_sse2)
 852                 /* It is Pentium M.  */
 853                 cpu = "pentium-m";
 854               else if (has_sse)
 855                 {
 856                   if (vendor == signature_CENTAUR_ebx)
 857                     {
 858                       if (model >= 9)
 859                         /* Eden "Nehemiah" */
 860                         cpu = "nehemiah";
 861                       else
 862                         cpu = "c3-2";
 863                     }
 864                   else
 865                     /* It is Pentium III.  */
 866                     cpu = "pentium3";
 867                 }
 868               else if (has_mmx)
 869                 /* It is Pentium II.  */
 870                 cpu = "pentium2";
 871               else
 872                 /* Default to Pentium Pro.  */
 873                 cpu = "pentiumpro";
 874             }
 875           else
 876             /* For -mtune, we default to -mtune=generic.  */
 877             cpu = "generic";
 878           break;
 879         }
 880       break;
 881     case PROCESSOR_PENTIUM4:
 882       if (has_sse3)
 883         {
 884           if (has_longmode)
 885             cpu = "nocona";
 886           else
 887             cpu = "prescott";
 888         }
 889       else
 890         cpu = "pentium4";
 891       break;
 892     case PROCESSOR_GEODE:
 893       cpu = "geode";
 894       break;
 895     case PROCESSOR_K6:
 896       if (arch && has_3dnow)
 897         cpu = "k6-3";
 898       else
 899         cpu = "k6";
 900       break;
 901     case PROCESSOR_ATHLON:
 902       if (arch && has_sse)
 903         cpu = "athlon-4";
 904       else
 905         cpu = "athlon";
 906       break;
 907     case PROCESSOR_K8:
 908       if (arch)
 909         {
 910           if (vendor == signature_CENTAUR_ebx)
 911             {
 912               if (has_sse4_1)
 913                 /* Nano 3000 | Nano dual / quad core | Eden X4 */
 914                 cpu = "nano-3000";
 915               else if (has_ssse3)
 916                 /* Nano 1000 | Nano 2000 */
 917                 cpu = "nano";
 918               else if (has_sse3)
 919                 /* Eden X2 */
 920                 cpu = "eden-x2";
 921               else
 922                 /* Default to k8 */
 923                 cpu = "k8";
 924             }
 925           else if (has_sse3)
 926             cpu = "k8-sse3";
 927           else
 928             cpu = "k8";
 929         }
 930       else
 931         /* For -mtune, we default to -mtune=k8 */
 932         cpu = "k8";
 933       break;
 934     case PROCESSOR_AMDFAM10:
 935       cpu = "amdfam10";
 936       break;
 937     case PROCESSOR_BDVER1:
 938       cpu = "bdver1";
 939       break;
 940     case PROCESSOR_BDVER2:
 941       cpu = "bdver2";
 942       break;
 943     case PROCESSOR_BDVER3:
 944       cpu = "bdver3";
 945       break;
 946     case PROCESSOR_BDVER4:
 947       cpu = "bdver4";
 948       break;
 949     case PROCESSOR_ZNVER1:
 950       cpu = "znver1";
 951       break;
 952     case PROCESSOR_BTVER1:
 953       cpu = "btver1";
 954       break;
 955     case PROCESSOR_BTVER2:
 956       cpu = "btver2";
 957       break;
 958
 959     default:
 960       /* Use something reasonable.  */
 961       if (arch)
 962         {
 963           if (has_ssse3)
 964             cpu = "core2";
 965           else if (has_sse3)
 966             {
 967               if (has_longmode)
 968                 cpu = "nocona";
 969               else
 970                 cpu = "prescott";
 971             }
 972           else if (has_longmode)
 973             /* Perhaps some emulator?  Assume x86-64, otherwise gcc
 974                -march=native would be unusable for 64-bit compilations,
 975                as all the CPUs below are 32-bit only.  */
 976             cpu = "x86-64";
 977           else if (has_sse2)
 978             cpu = "pentium4";
 979           else if (has_cmov)
 980             cpu = "pentiumpro";
 981           else if (has_mmx)
 982             cpu = "pentium-mmx";
 983           else if (has_cmpxchg8b)
 984             cpu = "pentium";
 985         }
 986       else
 987         cpu = "generic";
 988     }
 989
 990   if (arch)
 991     {
 992       const char *mmx = has_mmx ? " -mmmx" : " -mno-mmx";
 993       const char *mmx3dnow = has_3dnow ? " -m3dnow" : " -mno-3dnow";
 994       const char *sse = has_sse ? " -msse" : " -mno-sse";
 995       const char *sse2 = has_sse2 ? " -msse2" : " -mno-sse2";
 996       const char *sse3 = has_sse3 ? " -msse3" : " -mno-sse3";
 997       const char *ssse3 = has_ssse3 ? " -mssse3" : " -mno-ssse3";
 998       const char *sse4a = has_sse4a ? " -msse4a" : " -mno-sse4a";
 999       const char *cx16 = has_cmpxchg16b ? " -mcx16" : " -mno-cx16";
1000       const char *sahf = has_lahf_lm ? " -msahf" : " -mno-sahf";
1001       const char *movbe = has_movbe ? " -mmovbe" : " -mno-movbe";
1002       const char *aes = has_aes ? " -maes" : " -mno-aes";
1003       const char *sha = has_sha ? " -msha" : " -mno-sha";
1004       const char *pclmul = has_pclmul ? " -mpclmul" : " -mno-pclmul";
1005       const char *popcnt = has_popcnt ? " -mpopcnt" : " -mno-popcnt";
1006       const char *abm = has_abm ? " -mabm" : " -mno-abm";
1007       const char *lwp = has_lwp ? " -mlwp" : " -mno-lwp";
1008       const char *fma = has_fma ? " -mfma" : " -mno-fma";
1009       const char *fma4 = has_fma4 ? " -mfma4" : " -mno-fma4";
1010       const char *xop = has_xop ? " -mxop" : " -mno-xop";
1011       const char *bmi = has_bmi ? " -mbmi" : " -mno-bmi";
1012       const char *sgx = has_sgx ? " -msgx" : " -mno-sgx";
1013       const char *bmi2 = has_bmi2 ? " -mbmi2" : " -mno-bmi2";
1014       const char *tbm = has_tbm ? " -mtbm" : " -mno-tbm";
1015       const char *avx = has_avx ? " -mavx" : " -mno-avx";
1016       const char *avx2 = has_avx2 ? " -mavx2" : " -mno-avx2";
1017       const char *sse4_2 = has_sse4_2 ? " -msse4.2" : " -mno-sse4.2";
1018       const char *sse4_1 = has_sse4_1 ? " -msse4.1" : " -mno-sse4.1";
1019       const char *lzcnt = has_lzcnt ? " -mlzcnt" : " -mno-lzcnt";
1020       const char *hle = has_hle ? " -mhle" : " -mno-hle";
1021       const char *rtm = has_rtm ? " -mrtm" : " -mno-rtm";
1022       const char *rdrnd = has_rdrnd ? " -mrdrnd" : " -mno-rdrnd";
1023       const char *f16c = has_f16c ? " -mf16c" : " -mno-f16c";
1024       const char *fsgsbase = has_fsgsbase ? " -mfsgsbase" : " -mno-fsgsbase";
1025       const char *rdseed = has_rdseed ? " -mrdseed" : " -mno-rdseed";
1026       const char *prfchw = has_prfchw ? " -mprfchw" : " -mno-prfchw";
1027       const char *adx = has_adx ? " -madx" : " -mno-adx";
1028       const char *fxsr = has_fxsr ? " -mfxsr" : " -mno-fxsr";
1029       const char *xsave = has_xsave ? " -mxsave" : " -mno-xsave";
1030       const char *xsaveopt = has_xsaveopt ? " -mxsaveopt" : " -mno-xsaveopt";
1031       const char *avx512f = has_avx512f ? " -mavx512f" : " -mno-avx512f";
1032       const char *avx512er = has_avx512er ? " -mavx512er" : " -mno-avx512er";
1033       const char *avx512cd = has_avx512cd ? " -mavx512cd" : " -mno-avx512cd";
1034       const char *avx512pf = has_avx512pf ? " -mavx512pf" : " -mno-avx512pf";
1035       const char *prefetchwt1 = has_prefetchwt1 ? " -mprefetchwt1" : " -mno-prefetchwt1";
1036       const char *clflushopt = has_clflushopt ? " -mclflushopt" : " -mno-clflushopt";
1037       const char *xsavec = has_xsavec ? " -mxsavec" : " -mno-xsavec";
1038       const char *xsaves = has_xsaves ? " -mxsaves" : " -mno-xsaves";
1039       const char *avx512dq = has_avx512dq ? " -mavx512dq" : " -mno-avx512dq";
1040       const char *avx512bw = has_avx512bw ? " -mavx512bw" : " -mno-avx512bw";
1041       const char *avx512vl = has_avx512vl ? " -mavx512vl" : " -mno-avx512vl";
1042       const char *avx512ifma = has_avx512ifma ? " -mavx512ifma" : " -mno-avx512ifma";
1043       const char *avx512vbmi = has_avx512vbmi ? " -mavx512vbmi" : " -mno-avx512vbmi";
1044       const char *avx5124vnniw = has_avx5124vnniw ? " -mavx5124vnniw" : " -mno-avx5124vnniw";
1045       const char *avx5124fmaps = has_avx5124fmaps ? " -mavx5124fmaps" : " -mno-avx5124fmaps";
1046       const char *clwb = has_clwb ? " -mclwb" : " -mno-clwb";
1047       const char *mwaitx  = has_mwaitx  ? " -mmwaitx"  : " -mno-mwaitx";
1048       const char *clzero  = has_clzero  ? " -mclzero"  : " -mno-clzero";
1049       const char *pku = has_pku ? " -mpku" : " -mno-pku";
1050       const char *rdpid = has_rdpid ? " -mrdpid" : " -mno-rdpid";
1051       options = concat (options, mmx, mmx3dnow, sse, sse2, sse3, ssse3,
1052                         sse4a, cx16, sahf, movbe, aes, sha, pclmul,
1053                         popcnt, abm, lwp, fma, fma4, xop, bmi, sgx, bmi2,
1054                         tbm, avx, avx2, sse4_2, sse4_1, lzcnt, rtm,
1055                         hle, rdrnd, f16c, fsgsbase, rdseed, prfchw, adx,
1056                         fxsr, xsave, xsaveopt, avx512f, avx512er,
1057                         avx512cd, avx512pf, prefetchwt1, clflushopt,
1058                         xsavec, xsaves, avx512dq, avx512bw, avx512vl,
1059                         avx512ifma, avx512vbmi, avx5124fmaps, avx5124vnniw,
1060                         clwb, mwaitx, clzero, pku, rdpid, NULL);
1061     }
1062
1063 done:
1064   return concat (cache, "-m", argv[0], "=", cpu, options, NULL);
1065 }
1066 #else
1067
1068 /* If we are compiling with GCC where %EBX register is fixed, then the
1069    driver will just ignore -march and -mtune "native" target and will leave
1070    to the newly built compiler to generate code for its default target.  */
1071
1072 const char *host_detect_local_cpu (int, const char **)
1073 {
1074   return NULL;
1075 }
1076 #endif /* __GNUC__ */