gcc/config/riscv/riscv-c.c

   1 /* RISC-V-specific code for C family languages.
   2    Copyright (C) 2011-2018 Free Software Foundation, Inc.
   3    Contributed by Andrew Waterman (andrew@sifive.com).
   4
   5 This file is part of GCC.
   6
   7 GCC is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 3, or (at your option)
  10 any later version.
  11
  12 GCC is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with GCC; see the file COPYING3.  If not see
  19 <http://www.gnu.org/licenses/>.  */
  20
  21 #define IN_TARGET_CODE 1
  22
  23 #include "config.h"
  24 #include "system.h"
  25 #include "coretypes.h"
  26 #include "tm.h"
  27 #include "c-family/c-common.h"
  28 #include "cpplib.h"
  29
  30 #define builtin_define(TXT) cpp_define (pfile, TXT)
  31
  32 /* Implement TARGET_CPU_CPP_BUILTINS.  */
  33
  34 void
  35 riscv_cpu_cpp_builtins (cpp_reader *pfile)
  36 {
  37   builtin_define ("__riscv");
  38
  39   if (TARGET_RVC)
  40     builtin_define ("__riscv_compressed");
  41
  42   if (TARGET_RVE)
  43     builtin_define ("__riscv_32e");
  44
  45   if (TARGET_ATOMIC)
  46     builtin_define ("__riscv_atomic");
  47
  48   if (TARGET_MUL)
  49     builtin_define ("__riscv_mul");
  50   if (TARGET_DIV)
  51     builtin_define ("__riscv_div");
  52   if (TARGET_DIV && TARGET_MUL)
  53     builtin_define ("__riscv_muldiv");
  54
  55   builtin_define_with_int_value ("__riscv_xlen", UNITS_PER_WORD * 8);
  56   if (TARGET_HARD_FLOAT)
  57     builtin_define_with_int_value ("__riscv_flen", UNITS_PER_FP_REG * 8);
  58
  59   if (TARGET_HARD_FLOAT && TARGET_FDIV)
  60     {
  61       builtin_define ("__riscv_fdiv");
  62       builtin_define ("__riscv_fsqrt");
  63     }
  64
  65   switch (riscv_abi)
  66     {
  67     case ABI_ILP32:
  68     case ABI_ILP32E:
  69     case ABI_LP64:
  70       builtin_define ("__riscv_float_abi_soft");
  71       break;
  72
  73     case ABI_ILP32F:
  74     case ABI_LP64F:
  75       builtin_define ("__riscv_float_abi_single");
  76       break;
  77
  78     case ABI_ILP32D:
  79     case ABI_LP64D:
  80       builtin_define ("__riscv_float_abi_double");
  81       break;
  82     }
  83
  84   switch (riscv_cmodel)
  85     {
  86     case CM_MEDLOW:
  87       builtin_define ("__riscv_cmodel_medlow");
  88       break;
  89
  90     case CM_MEDANY:
  91       builtin_define ("__riscv_cmodel_medany");
  92       break;
  93
  94     case CM_PIC:
  95       builtin_define ("__riscv_cmodel_pic");
  96       break;
  97     }
  98 }