gcc/config/aarch64/aarch64-protos.h

   1 /* Machine description for AArch64 architecture.
   2    Copyright (C) 2009-2018 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but
  13    WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15    General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21
  22 #ifndef GCC_AARCH64_PROTOS_H
  23 #define GCC_AARCH64_PROTOS_H
  24
  25 #include "input.h"
  26
  27 /* SYMBOL_SMALL_ABSOLUTE: Generate symbol accesses through
  28    high and lo relocs that calculate the base address using a PC
  29    relative reloc.
  30    So to get the address of foo, we generate
  31    adrp x0, foo
  32    add  x0, x0, :lo12:foo
  33
  34    To load or store something to foo, we could use the corresponding
  35    load store variants that generate an
  36    ldr x0, [x0,:lo12:foo]
  37    or
  38    str x1, [x0, :lo12:foo]
  39
  40    This corresponds to the small code model of the compiler.
  41
  42    SYMBOL_SMALL_GOT_4G: Similar to the one above but this
  43    gives us the GOT entry of the symbol being referred to :
  44    Thus calculating the GOT entry for foo is done using the
  45    following sequence of instructions.  The ADRP instruction
  46    gets us to the page containing the GOT entry of the symbol
  47    and the got_lo12 gets us the actual offset in it, together
  48    the base and offset, we can address 4G size GOT table.
  49
  50    adrp  x0, :got:foo
  51    ldr   x0, [x0, :gotoff_lo12:foo]
  52
  53    This corresponds to the small PIC model of the compiler.
  54
  55    SYMBOL_SMALL_GOT_28K: Similar to SYMBOL_SMALL_GOT_4G, but used for symbol
  56    restricted within 28K GOT table size.
  57
  58    ldr reg, [gp, #:gotpage_lo15:sym]
  59
  60    This corresponds to -fpic model for small memory model of the compiler.
  61
  62    SYMBOL_SMALL_TLSGD
  63    SYMBOL_SMALL_TLSDESC
  64    SYMBOL_SMALL_TLSIE
  65    SYMBOL_TINY_TLSIE
  66    SYMBOL_TLSLE12
  67    SYMBOL_TLSLE24
  68    SYMBOL_TLSLE32
  69    SYMBOL_TLSLE48
  70    Each of these represents a thread-local symbol, and corresponds to the
  71    thread local storage relocation operator for the symbol being referred to.
  72
  73    SYMBOL_TINY_ABSOLUTE
  74
  75    Generate symbol accesses as a PC relative address using a single
  76    instruction.  To compute the address of symbol foo, we generate:
  77
  78    ADR x0, foo
  79
  80    SYMBOL_TINY_GOT
  81
  82    Generate symbol accesses via the GOT using a single PC relative
  83    instruction.  To compute the address of symbol foo, we generate:
  84
  85    ldr t0, :got:foo
  86
  87    The value of foo can subsequently read using:
  88
  89    ldrb    t0, [t0]
  90
  91    SYMBOL_FORCE_TO_MEM : Global variables are addressed using
  92    constant pool.  All variable addresses are spilled into constant
  93    pools.  The constant pools themselves are addressed using PC
  94    relative accesses.  This only works for the large code model.
  95  */
  96 enum aarch64_symbol_type
  97 {
  98   SYMBOL_SMALL_ABSOLUTE,
  99   SYMBOL_SMALL_GOT_28K,
 100   SYMBOL_SMALL_GOT_4G,
 101   SYMBOL_SMALL_TLSGD,
 102   SYMBOL_SMALL_TLSDESC,
 103   SYMBOL_SMALL_TLSIE,
 104   SYMBOL_TINY_ABSOLUTE,
 105   SYMBOL_TINY_GOT,
 106   SYMBOL_TINY_TLSIE,
 107   SYMBOL_TLSLE12,
 108   SYMBOL_TLSLE24,
 109   SYMBOL_TLSLE32,
 110   SYMBOL_TLSLE48,
 111   SYMBOL_FORCE_TO_MEM
 112 };
 113
 114 /* Classifies the type of an address query.
 115
 116    ADDR_QUERY_M
 117       Query what is valid for an "m" constraint and a memory_operand
 118       (the rules are the same for both).
 119
 120    ADDR_QUERY_LDP_STP
 121       Query what is valid for a load/store pair.
 122
 123    ADDR_QUERY_LDP_STP_N
 124       Query what is valid for a load/store pair, but narrow the incoming mode
 125       for address checking.  This is used for the store_pair_lanes patterns.
 126
 127    ADDR_QUERY_ANY
 128       Query what is valid for at least one memory constraint, which may
 129       allow things that "m" doesn't.  For example, the SVE LDR and STR
 130       addressing modes allow a wider range of immediate offsets than "m"
 131       does.  */
 132 enum aarch64_addr_query_type {
 133   ADDR_QUERY_M,
 134   ADDR_QUERY_LDP_STP,
 135   ADDR_QUERY_LDP_STP_N,
 136   ADDR_QUERY_ANY
 137 };
 138
 139 /* A set of tuning parameters contains references to size and time
 140    cost models and vectors for address cost calculations, register
 141    move costs and memory move costs.  */
 142
 143 /* Scaled addressing modes can vary cost depending on the mode of the
 144    value to be loaded/stored.  QImode values cannot use scaled
 145    addressing modes.  */
 146
 147 struct scale_addr_mode_cost
 148 {
 149   const int hi;
 150   const int si;
 151   const int di;
 152   const int ti;
 153 };
 154
 155 /* Additional cost for addresses.  */
 156 struct cpu_addrcost_table
 157 {
 158   const struct scale_addr_mode_cost addr_scale_costs;
 159   const int pre_modify;
 160   const int post_modify;
 161   const int register_offset;
 162   const int register_sextend;
 163   const int register_zextend;
 164   const int imm_offset;
 165 };
 166
 167 /* Additional costs for register copies.  Cost is for one register.  */
 168 struct cpu_regmove_cost
 169 {
 170   const int GP2GP;
 171   const int GP2FP;
 172   const int FP2GP;
 173   const int FP2FP;
 174 };
 175
 176 /* Cost for vector insn classes.  */
 177 struct cpu_vector_cost
 178 {
 179   const int scalar_int_stmt_cost;        /* Cost of any int scalar operation,
 180                                             excluding load and store.  */
 181   const int scalar_fp_stmt_cost;         /* Cost of any fp scalar operation,
 182                                             excluding load and store.  */
 183   const int scalar_load_cost;            /* Cost of scalar load.  */
 184   const int scalar_store_cost;           /* Cost of scalar store.  */
 185   const int vec_int_stmt_cost;           /* Cost of any int vector operation,
 186                                             excluding load, store, permute,
 187                                             vector-to-scalar and
 188                                             scalar-to-vector operation.  */
 189   const int vec_fp_stmt_cost;            /* Cost of any fp vector operation,
 190                                             excluding load, store, permute,
 191                                             vector-to-scalar and
 192                                             scalar-to-vector operation.  */
 193   const int vec_permute_cost;            /* Cost of permute operation.  */
 194   const int vec_to_scalar_cost;          /* Cost of vec-to-scalar operation.  */
 195   const int scalar_to_vec_cost;          /* Cost of scalar-to-vector
 196                                             operation.  */
 197   const int vec_align_load_cost;         /* Cost of aligned vector load.  */
 198   const int vec_unalign_load_cost;       /* Cost of unaligned vector load.  */
 199   const int vec_unalign_store_cost;      /* Cost of unaligned vector store.  */
 200   const int vec_store_cost;              /* Cost of vector store.  */
 201   const int cond_taken_branch_cost;      /* Cost of taken branch.  */
 202   const int cond_not_taken_branch_cost;  /* Cost of not taken branch.  */
 203 };
 204
 205 /* Branch costs.  */
 206 struct cpu_branch_cost
 207 {
 208   const int predictable;    /* Predictable branch or optimizing for size.  */
 209   const int unpredictable;  /* Unpredictable branch or optimizing for speed.  */
 210 };
 211
 212 /* Control approximate alternatives to certain FP operators.  */
 213 #define AARCH64_APPROX_MODE(MODE) \
 214   ((MIN_MODE_FLOAT <= (MODE) && (MODE) <= MAX_MODE_FLOAT) \
 215    ? (1 << ((MODE) - MIN_MODE_FLOAT)) \
 216    : (MIN_MODE_VECTOR_FLOAT <= (MODE) && (MODE) <= MAX_MODE_VECTOR_FLOAT) \
 217      ? (1 << ((MODE) - MIN_MODE_VECTOR_FLOAT \
 218               + MAX_MODE_FLOAT - MIN_MODE_FLOAT + 1)) \
 219      : (0))
 220 #define AARCH64_APPROX_NONE (0)
 221 #define AARCH64_APPROX_ALL (-1)
 222
 223 /* Allowed modes for approximations.  */
 224 struct cpu_approx_modes
 225 {
 226   const unsigned int division;          /* Division.  */
 227   const unsigned int sqrt;              /* Square root.  */
 228   const unsigned int recip_sqrt;        /* Reciprocal square root.  */
 229 };
 230
 231 /* Cache prefetch settings for prefetch-loop-arrays.  */
 232 struct cpu_prefetch_tune
 233 {
 234   const int num_slots;
 235   const int l1_cache_size;
 236   const int l1_cache_line_size;
 237   const int l2_cache_size;
 238   /* Whether software prefetch hints should be issued for non-constant
 239      strides.  */
 240   const bool prefetch_dynamic_strides;
 241   /* The minimum constant stride beyond which we should use prefetch
 242      hints for.  */
 243   const int minimum_stride;
 244   const int default_opt_level;
 245 };
 246
 247 struct tune_params
 248 {
 249   const struct cpu_cost_table *insn_extra_cost;
 250   const struct cpu_addrcost_table *addr_cost;
 251   const struct cpu_regmove_cost *regmove_cost;
 252   const struct cpu_vector_cost *vec_costs;
 253   const struct cpu_branch_cost *branch_costs;
 254   const struct cpu_approx_modes *approx_modes;
 255   int memmov_cost;
 256   int issue_rate;
 257   unsigned int fusible_ops;
 258   const char *function_align;
 259   const char *jump_align;
 260   const char *loop_align;
 261   int int_reassoc_width;
 262   int fp_reassoc_width;
 263   int vec_reassoc_width;
 264   int min_div_recip_mul_sf;
 265   int min_div_recip_mul_df;
 266   /* Value for aarch64_case_values_threshold; or 0 for the default.  */
 267   unsigned int max_case_values;
 268 /* An enum specifying how to take into account CPU autoprefetch capabilities
 269    during instruction scheduling:
 270    - AUTOPREFETCHER_OFF: Do not take autoprefetch capabilities into account.
 271    - AUTOPREFETCHER_WEAK: Attempt to sort sequences of loads/store in order of
 272    offsets but allow the pipeline hazard recognizer to alter that order to
 273    maximize multi-issue opportunities.
 274    - AUTOPREFETCHER_STRONG: Attempt to sort sequences of loads/store in order of
 275    offsets and prefer this even if it restricts multi-issue opportunities.  */
 276
 277   enum aarch64_autoprefetch_model
 278   {
 279     AUTOPREFETCHER_OFF,
 280     AUTOPREFETCHER_WEAK,
 281     AUTOPREFETCHER_STRONG
 282   } autoprefetcher_model;
 283
 284   unsigned int extra_tuning_flags;
 285
 286   /* Place prefetch struct pointer at the end to enable type checking
 287      errors when tune_params misses elements (e.g., from erroneous merges).  */
 288   const struct cpu_prefetch_tune *prefetch;
 289 };
 290
 291 /* Classifies an address.
 292
 293    ADDRESS_REG_IMM
 294        A simple base register plus immediate offset.
 295
 296    ADDRESS_REG_WB
 297        A base register indexed by immediate offset with writeback.
 298
 299    ADDRESS_REG_REG
 300        A base register indexed by (optionally scaled) register.
 301
 302    ADDRESS_REG_UXTW
 303        A base register indexed by (optionally scaled) zero-extended register.
 304
 305    ADDRESS_REG_SXTW
 306        A base register indexed by (optionally scaled) sign-extended register.
 307
 308    ADDRESS_LO_SUM
 309        A LO_SUM rtx with a base register and "LO12" symbol relocation.
 310
 311    ADDRESS_SYMBOLIC:
 312        A constant symbolic address, in pc-relative literal pool.  */
 313
 314 enum aarch64_address_type {
 315   ADDRESS_REG_IMM,
 316   ADDRESS_REG_WB,
 317   ADDRESS_REG_REG,
 318   ADDRESS_REG_UXTW,
 319   ADDRESS_REG_SXTW,
 320   ADDRESS_LO_SUM,
 321   ADDRESS_SYMBOLIC
 322 };
 323
 324 /* Address information.  */
 325 struct aarch64_address_info {
 326   enum aarch64_address_type type;
 327   rtx base;
 328   rtx offset;
 329   poly_int64 const_offset;
 330   int shift;
 331   enum aarch64_symbol_type symbol_type;
 332 };
 333
 334 #define AARCH64_FUSION_PAIR(x, name) \
 335   AARCH64_FUSE_##name##_index,
 336 /* Supported fusion operations.  */
 337 enum aarch64_fusion_pairs_index
 338 {
 339 #include "aarch64-fusion-pairs.def"
 340   AARCH64_FUSE_index_END
 341 };
 342
 343 #define AARCH64_FUSION_PAIR(x, name) \
 344   AARCH64_FUSE_##name = (1u << AARCH64_FUSE_##name##_index),
 345 /* Supported fusion operations.  */
 346 enum aarch64_fusion_pairs
 347 {
 348   AARCH64_FUSE_NOTHING = 0,
 349 #include "aarch64-fusion-pairs.def"
 350   AARCH64_FUSE_ALL = (1u << AARCH64_FUSE_index_END) - 1
 351 };
 352
 353 #define AARCH64_EXTRA_TUNING_OPTION(x, name) \
 354   AARCH64_EXTRA_TUNE_##name##_index,
 355 /* Supported tuning flags indexes.  */
 356 enum aarch64_extra_tuning_flags_index
 357 {
 358 #include "aarch64-tuning-flags.def"
 359   AARCH64_EXTRA_TUNE_index_END
 360 };
 361
 362
 363 #define AARCH64_EXTRA_TUNING_OPTION(x, name) \
 364   AARCH64_EXTRA_TUNE_##name = (1u << AARCH64_EXTRA_TUNE_##name##_index),
 365 /* Supported tuning flags.  */
 366 enum aarch64_extra_tuning_flags
 367 {
 368   AARCH64_EXTRA_TUNE_NONE = 0,
 369 #include "aarch64-tuning-flags.def"
 370   AARCH64_EXTRA_TUNE_ALL = (1u << AARCH64_EXTRA_TUNE_index_END) - 1
 371 };
 372
 373 /* Enum describing the various ways that the
 374    aarch64_parse_{arch,tune,cpu,extension} functions can fail.
 375    This way their callers can choose what kind of error to give.  */
 376
 377 enum aarch64_parse_opt_result
 378 {
 379   AARCH64_PARSE_OK,                     /* Parsing was successful.  */
 380   AARCH64_PARSE_MISSING_ARG,            /* Missing argument.  */
 381   AARCH64_PARSE_INVALID_FEATURE,        /* Invalid feature modifier.  */
 382   AARCH64_PARSE_INVALID_ARG             /* Invalid arch, tune, cpu arg.  */
 383 };
 384
 385 /* Enum to distinguish which type of check is to be done in
 386    aarch64_simd_valid_immediate.  This is used as a bitmask where
 387    AARCH64_CHECK_MOV has both bits set.  Thus AARCH64_CHECK_MOV will
 388    perform all checks.  Adding new types would require changes accordingly.  */
 389 enum simd_immediate_check {
 390   AARCH64_CHECK_ORR  = 1 << 0,
 391   AARCH64_CHECK_BIC  = 1 << 1,
 392   AARCH64_CHECK_MOV  = AARCH64_CHECK_ORR | AARCH64_CHECK_BIC
 393 };
 394
 395 extern struct tune_params aarch64_tune_params;
 396
 397 poly_int64 aarch64_initial_elimination_offset (unsigned, unsigned);
 398 int aarch64_get_condition_code (rtx);
 399 bool aarch64_address_valid_for_prefetch_p (rtx, bool);
 400 bool aarch64_bitmask_imm (HOST_WIDE_INT val, machine_mode);
 401 unsigned HOST_WIDE_INT aarch64_and_split_imm1 (HOST_WIDE_INT val_in);
 402 unsigned HOST_WIDE_INT aarch64_and_split_imm2 (HOST_WIDE_INT val_in);
 403 bool aarch64_and_bitmask_imm (unsigned HOST_WIDE_INT val_in, machine_mode mode);
 404 int aarch64_branch_cost (bool, bool);
 405 enum aarch64_symbol_type aarch64_classify_symbolic_expression (rtx);
 406 bool aarch64_can_const_movi_rtx_p (rtx x, machine_mode mode);
 407 bool aarch64_const_vec_all_same_int_p (rtx, HOST_WIDE_INT);
 408 bool aarch64_const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT,
 409                                             HOST_WIDE_INT);
 410 bool aarch64_constant_address_p (rtx);
 411 bool aarch64_emit_approx_div (rtx, rtx, rtx);
 412 bool aarch64_emit_approx_sqrt (rtx, rtx, bool);
 413 void aarch64_expand_call (rtx, rtx, bool);
 414 bool aarch64_expand_movmem (rtx *);
 415 bool aarch64_float_const_zero_rtx_p (rtx);
 416 bool aarch64_float_const_rtx_p (rtx);
 417 bool aarch64_function_arg_regno_p (unsigned);
 418 bool aarch64_fusion_enabled_p (enum aarch64_fusion_pairs);
 419 bool aarch64_gen_movmemqi (rtx *);
 420 bool aarch64_gimple_fold_builtin (gimple_stmt_iterator *);
 421 bool aarch64_is_extend_from_extract (scalar_int_mode, rtx, rtx);
 422 bool aarch64_is_long_call_p (rtx);
 423 bool aarch64_is_noplt_call_p (rtx);
 424 bool aarch64_label_mentioned_p (rtx);
 425 void aarch64_declare_function_name (FILE *, const char*, tree);
 426 bool aarch64_legitimate_pic_operand_p (rtx);
 427 bool aarch64_mask_and_shift_for_ubfiz_p (scalar_int_mode, rtx, rtx);
 428 bool aarch64_zero_extend_const_eq (machine_mode, rtx, machine_mode, rtx);
 429 bool aarch64_move_imm (HOST_WIDE_INT, machine_mode);
 430 opt_machine_mode aarch64_sve_pred_mode (unsigned int);
 431 bool aarch64_sve_cnt_immediate_p (rtx);
 432 bool aarch64_sve_addvl_addpl_immediate_p (rtx);
 433 bool aarch64_sve_inc_dec_immediate_p (rtx);
 434 int aarch64_add_offset_temporaries (rtx);
 435 void aarch64_split_add_offset (scalar_int_mode, rtx, rtx, rtx, rtx, rtx);
 436 bool aarch64_mov_operand_p (rtx, machine_mode);
 437 rtx aarch64_reverse_mask (machine_mode, unsigned int);
 438 bool aarch64_offset_7bit_signed_scaled_p (machine_mode, poly_int64);
 439 char *aarch64_output_sve_cnt_immediate (const char *, const char *, rtx);
 440 char *aarch64_output_sve_addvl_addpl (rtx, rtx, rtx);
 441 char *aarch64_output_sve_inc_dec_immediate (const char *, rtx);
 442 char *aarch64_output_scalar_simd_mov_immediate (rtx, scalar_int_mode);
 443 char *aarch64_output_simd_mov_immediate (rtx, unsigned,
 444                         enum simd_immediate_check w = AARCH64_CHECK_MOV);
 445 char *aarch64_output_sve_mov_immediate (rtx);
 446 char *aarch64_output_ptrue (machine_mode, char);
 447 bool aarch64_pad_reg_upward (machine_mode, const_tree, bool);
 448 bool aarch64_regno_ok_for_base_p (int, bool);
 449 bool aarch64_regno_ok_for_index_p (int, bool);
 450 bool aarch64_reinterpret_float_as_int (rtx value, unsigned HOST_WIDE_INT *fail);
 451 bool aarch64_simd_check_vect_par_cnst_half (rtx op, machine_mode mode,
 452                                             bool high);
 453 bool aarch64_simd_scalar_immediate_valid_for_move (rtx, scalar_int_mode);
 454 bool aarch64_simd_shift_imm_p (rtx, machine_mode, bool);
 455 bool aarch64_simd_valid_immediate (rtx, struct simd_immediate_info *,
 456                         enum simd_immediate_check w = AARCH64_CHECK_MOV);
 457 rtx aarch64_check_zero_based_sve_index_immediate (rtx);
 458 bool aarch64_sve_index_immediate_p (rtx);
 459 bool aarch64_sve_arith_immediate_p (rtx, bool);
 460 bool aarch64_sve_bitmask_immediate_p (rtx);
 461 bool aarch64_sve_dup_immediate_p (rtx);
 462 bool aarch64_sve_cmp_immediate_p (rtx, bool);
 463 bool aarch64_sve_float_arith_immediate_p (rtx, bool);
 464 bool aarch64_sve_float_mul_immediate_p (rtx);
 465 bool aarch64_split_dimode_const_store (rtx, rtx);
 466 bool aarch64_symbolic_address_p (rtx);
 467 bool aarch64_uimm12_shift (HOST_WIDE_INT);
 468 bool aarch64_use_return_insn_p (void);
 469 const char *aarch64_mangle_builtin_type (const_tree);
 470 const char *aarch64_output_casesi (rtx *);
 471
 472 enum aarch64_symbol_type aarch64_classify_symbol (rtx, HOST_WIDE_INT);
 473 enum aarch64_symbol_type aarch64_classify_tls_symbol (rtx);
 474 enum reg_class aarch64_regno_regclass (unsigned);
 475 int aarch64_asm_preferred_eh_data_format (int, int);
 476 int aarch64_fpconst_pow_of_2 (rtx);
 477 machine_mode aarch64_hard_regno_caller_save_mode (unsigned, unsigned,
 478                                                        machine_mode);
 479 int aarch64_uxt_size (int, HOST_WIDE_INT);
 480 int aarch64_vec_fpconst_pow_of_2 (rtx);
 481 rtx aarch64_eh_return_handler_rtx (void);
 482 rtx aarch64_mask_from_zextract_ops (rtx, rtx);
 483 const char *aarch64_output_move_struct (rtx *operands);
 484 rtx aarch64_return_addr (int, rtx);
 485 rtx aarch64_simd_gen_const_vector_dup (machine_mode, HOST_WIDE_INT);
 486 bool aarch64_simd_mem_operand_p (rtx);
 487 bool aarch64_sve_ld1r_operand_p (rtx);
 488 bool aarch64_sve_ldr_operand_p (rtx);
 489 bool aarch64_sve_struct_memory_operand_p (rtx);
 490 rtx aarch64_simd_vect_par_cnst_half (machine_mode, int, bool);
 491 rtx aarch64_tls_get_addr (void);
 492 tree aarch64_fold_builtin (tree, int, tree *, bool);
 493 unsigned aarch64_dbx_register_number (unsigned);
 494 unsigned aarch64_trampoline_size (void);
 495 void aarch64_asm_output_labelref (FILE *, const char *);
 496 void aarch64_cpu_cpp_builtins (cpp_reader *);
 497 const char * aarch64_gen_far_branch (rtx *, int, const char *, const char *);
 498 const char * aarch64_output_probe_stack_range (rtx, rtx);
 499 void aarch64_err_no_fpadvsimd (machine_mode);
 500 void aarch64_expand_epilogue (bool);
 501 void aarch64_expand_mov_immediate (rtx, rtx, rtx (*) (rtx, rtx) = 0);
 502 void aarch64_emit_sve_pred_move (rtx, rtx, rtx);
 503 void aarch64_expand_sve_mem_move (rtx, rtx, machine_mode);
 504 bool aarch64_maybe_expand_sve_subreg_move (rtx, rtx);
 505 void aarch64_split_sve_subreg_move (rtx, rtx, rtx);
 506 void aarch64_expand_prologue (void);
 507 void aarch64_expand_vector_init (rtx, rtx);
 508 void aarch64_init_cumulative_args (CUMULATIVE_ARGS *, const_tree, rtx,
 509                                    const_tree, unsigned);
 510 void aarch64_init_expanders (void);
 511 void aarch64_init_simd_builtins (void);
 512 void aarch64_emit_call_insn (rtx);
 513 void aarch64_register_pragmas (void);
 514 void aarch64_relayout_simd_types (void);
 515 void aarch64_reset_previous_fndecl (void);
 516 bool aarch64_return_address_signing_enabled (void);
 517 void aarch64_save_restore_target_globals (tree);
 518 void aarch64_addti_scratch_regs (rtx, rtx, rtx *,
 519                                  rtx *, rtx *,
 520                                  rtx *, rtx *,
 521                                  rtx *);
 522 void aarch64_subvti_scratch_regs (rtx, rtx, rtx *,
 523                                   rtx *, rtx *,
 524                                   rtx *, rtx *, rtx *);
 525 void aarch64_expand_subvti (rtx, rtx, rtx,
 526                             rtx, rtx, rtx, rtx);
 527
 528
 529 /* Initialize builtins for SIMD intrinsics.  */
 530 void init_aarch64_simd_builtins (void);
 531
 532 void aarch64_simd_emit_reg_reg_move (rtx *, machine_mode, unsigned int);
 533
 534 /* Expand builtins for SIMD intrinsics.  */
 535 rtx aarch64_simd_expand_builtin (int, tree, rtx);
 536
 537 void aarch64_simd_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT, const_tree);
 538 rtx aarch64_endian_lane_rtx (machine_mode, unsigned int);
 539
 540 void aarch64_split_128bit_move (rtx, rtx);
 541
 542 bool aarch64_split_128bit_move_p (rtx, rtx);
 543
 544 bool aarch64_mov128_immediate (rtx);
 545
 546 void aarch64_split_simd_combine (rtx, rtx, rtx);
 547
 548 void aarch64_split_simd_move (rtx, rtx);
 549
 550 /* Check for a legitimate floating point constant for FMOV.  */
 551 bool aarch64_float_const_representable_p (rtx);
 552
 553 #if defined (RTX_CODE)
 554 void aarch64_gen_unlikely_cbranch (enum rtx_code, machine_mode cc_mode,
 555                                    rtx label_ref);
 556 bool aarch64_legitimate_address_p (machine_mode, rtx, bool,
 557                                    aarch64_addr_query_type = ADDR_QUERY_M);
 558 machine_mode aarch64_select_cc_mode (RTX_CODE, rtx, rtx);
 559 rtx aarch64_gen_compare_reg (RTX_CODE, rtx, rtx);
 560 rtx aarch64_load_tp (rtx);
 561
 562 void aarch64_expand_compare_and_swap (rtx op[]);
 563 void aarch64_split_compare_and_swap (rtx op[]);
 564 void aarch64_gen_atomic_cas (rtx, rtx, rtx, rtx, rtx);
 565
 566 bool aarch64_atomic_ldop_supported_p (enum rtx_code);
 567 void aarch64_gen_atomic_ldop (enum rtx_code, rtx, rtx, rtx, rtx, rtx);
 568 void aarch64_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx);
 569
 570 bool aarch64_gen_adjusted_ldpstp (rtx *, bool, scalar_mode, RTX_CODE);
 571
 572 void aarch64_expand_sve_vec_cmp_int (rtx, rtx_code, rtx, rtx);
 573 bool aarch64_expand_sve_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool);
 574 void aarch64_expand_sve_vcond (machine_mode, machine_mode, rtx *);
 575 #endif /* RTX_CODE */
 576
 577 void aarch64_init_builtins (void);
 578
 579 bool aarch64_process_target_attr (tree);
 580 void aarch64_override_options_internal (struct gcc_options *);
 581
 582 rtx aarch64_expand_builtin (tree exp,
 583                             rtx target,
 584                             rtx subtarget ATTRIBUTE_UNUSED,
 585                             machine_mode mode ATTRIBUTE_UNUSED,
 586                             int ignore ATTRIBUTE_UNUSED);
 587 tree aarch64_builtin_decl (unsigned, bool ATTRIBUTE_UNUSED);
 588 tree aarch64_builtin_rsqrt (unsigned int);
 589 tree aarch64_builtin_vectorized_function (unsigned int, tree, tree);
 590
 591 extern void aarch64_split_combinev16qi (rtx operands[3]);
 592 extern void aarch64_expand_vec_perm (rtx, rtx, rtx, rtx, unsigned int);
 593 extern void aarch64_expand_sve_vec_perm (rtx, rtx, rtx, rtx);
 594 extern bool aarch64_madd_needs_nop (rtx_insn *);
 595 extern void aarch64_final_prescan_insn (rtx_insn *);
 596 void aarch64_atomic_assign_expand_fenv (tree *, tree *, tree *);
 597 int aarch64_ccmp_mode_to_code (machine_mode mode);
 598
 599 bool extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset);
 600 bool aarch64_operands_ok_for_ldpstp (rtx *, bool, machine_mode);
 601 bool aarch64_operands_adjust_ok_for_ldpstp (rtx *, bool, scalar_mode);
 602 void aarch64_swap_ldrstr_operands (rtx *, bool);
 603
 604 extern void aarch64_asm_output_pool_epilogue (FILE *, const char *,
 605                                               tree, HOST_WIDE_INT);
 606
 607
 608 extern bool aarch64_classify_address (struct aarch64_address_info *, rtx,
 609                                       machine_mode, bool,
 610                                       aarch64_addr_query_type = ADDR_QUERY_M);
 611
 612 /* Defined in common/config/aarch64-common.c.  */
 613 bool aarch64_handle_option (struct gcc_options *, struct gcc_options *,
 614                              const struct cl_decoded_option *, location_t);
 615 const char *aarch64_rewrite_selected_cpu (const char *name);
 616 enum aarch64_parse_opt_result aarch64_parse_extension (const char *,
 617                                                        unsigned long *);
 618 std::string aarch64_get_extension_string_for_isa_flags (unsigned long,
 619                                                         unsigned long);
 620
 621 rtl_opt_pass *make_pass_fma_steering (gcc::context *);
 622 rtl_opt_pass *make_pass_track_speculation (gcc::context *);
 623 rtl_opt_pass *make_pass_tag_collision_avoidance (gcc::context *);
 624
 625 poly_uint64 aarch64_regmode_natural_size (machine_mode);
 626
 627 bool aarch64_high_bits_all_ones_p (HOST_WIDE_INT);
 628
 629 #endif /* GCC_AARCH64_PROTOS_H */