1 /* Subroutines for gcc2 for pdp11.
2 Copyright (C) 1994-2015 Free Software Foundation, Inc.
3 Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 GCC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
27 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
32 #include "insn-attr.h"
37 #include "stor-layout.h"
47 #include "diagnostic-core.h"
50 #include "dominance.h"
56 #include "cfgcleanup.h"
58 #include "basic-block.h"
64 #include "target-def.h"
66 /* this is the current value returned by the macro FIRST_PARM_OFFSET
68 int current_first_parm_offset
;
70 /* Routines to encode/decode pdp11 floats */
71 static void encode_pdp11_f (const struct real_format
*fmt
,
72 long *, const REAL_VALUE_TYPE
*);
73 static void decode_pdp11_f (const struct real_format
*,
74 REAL_VALUE_TYPE
*, const long *);
75 static void encode_pdp11_d (const struct real_format
*fmt
,
76 long *, const REAL_VALUE_TYPE
*);
77 static void decode_pdp11_d (const struct real_format
*,
78 REAL_VALUE_TYPE
*, const long *);
80 /* These two are taken from the corresponding vax descriptors
81 in real.c, changing only the encode/decode routine pointers. */
82 const struct real_format pdp11_f_format
=
104 const struct real_format pdp11_d_format
=
127 encode_pdp11_f (const struct real_format
*fmt ATTRIBUTE_UNUSED
, long *buf
,
128 const REAL_VALUE_TYPE
*r
)
130 (*vax_f_format
.encode
) (fmt
, buf
, r
);
131 buf
[0] = ((buf
[0] >> 16) & 0xffff) | ((buf
[0] & 0xffff) << 16);
135 decode_pdp11_f (const struct real_format
*fmt ATTRIBUTE_UNUSED
,
136 REAL_VALUE_TYPE
*r
, const long *buf
)
139 tbuf
= ((buf
[0] >> 16) & 0xffff) | ((buf
[0] & 0xffff) << 16);
140 (*vax_f_format
.decode
) (fmt
, r
, &tbuf
);
144 encode_pdp11_d (const struct real_format
*fmt ATTRIBUTE_UNUSED
, long *buf
,
145 const REAL_VALUE_TYPE
*r
)
147 (*vax_d_format
.encode
) (fmt
, buf
, r
);
148 buf
[0] = ((buf
[0] >> 16) & 0xffff) | ((buf
[0] & 0xffff) << 16);
149 buf
[1] = ((buf
[1] >> 16) & 0xffff) | ((buf
[1] & 0xffff) << 16);
153 decode_pdp11_d (const struct real_format
*fmt ATTRIBUTE_UNUSED
,
154 REAL_VALUE_TYPE
*r
, const long *buf
)
157 tbuf
[0] = ((buf
[0] >> 16) & 0xffff) | ((buf
[0] & 0xffff) << 16);
158 tbuf
[1] = ((buf
[1] >> 16) & 0xffff) | ((buf
[1] & 0xffff) << 16);
159 (*vax_d_format
.decode
) (fmt
, r
, tbuf
);
162 /* This is where the condition code register lives. */
163 /* rtx cc0_reg_rtx; - no longer needed? */
165 static const char *singlemove_string (rtx
*);
166 static bool pdp11_assemble_integer (rtx
, unsigned int, int);
167 static bool pdp11_rtx_costs (rtx
, int, int, int, int *, bool);
168 static bool pdp11_return_in_memory (const_tree
, const_tree
);
169 static rtx
pdp11_function_value (const_tree
, const_tree
, bool);
170 static rtx
pdp11_libcall_value (machine_mode
, const_rtx
);
171 static bool pdp11_function_value_regno_p (const unsigned int);
172 static void pdp11_trampoline_init (rtx
, tree
, rtx
);
173 static rtx
pdp11_function_arg (cumulative_args_t
, machine_mode
,
175 static void pdp11_function_arg_advance (cumulative_args_t
,
176 machine_mode
, const_tree
, bool);
177 static void pdp11_conditional_register_usage (void);
178 static bool pdp11_legitimate_constant_p (machine_mode
, rtx
);
180 static bool pdp11_scalar_mode_supported_p (machine_mode
);
182 /* Initialize the GCC target structure. */
183 #undef TARGET_ASM_BYTE_OP
184 #define TARGET_ASM_BYTE_OP NULL
185 #undef TARGET_ASM_ALIGNED_HI_OP
186 #define TARGET_ASM_ALIGNED_HI_OP NULL
187 #undef TARGET_ASM_ALIGNED_SI_OP
188 #define TARGET_ASM_ALIGNED_SI_OP NULL
189 #undef TARGET_ASM_INTEGER
190 #define TARGET_ASM_INTEGER pdp11_assemble_integer
192 #undef TARGET_ASM_OPEN_PAREN
193 #define TARGET_ASM_OPEN_PAREN "["
194 #undef TARGET_ASM_CLOSE_PAREN
195 #define TARGET_ASM_CLOSE_PAREN "]"
197 #undef TARGET_RTX_COSTS
198 #define TARGET_RTX_COSTS pdp11_rtx_costs
200 #undef TARGET_FUNCTION_ARG
201 #define TARGET_FUNCTION_ARG pdp11_function_arg
202 #undef TARGET_FUNCTION_ARG_ADVANCE
203 #define TARGET_FUNCTION_ARG_ADVANCE pdp11_function_arg_advance
205 #undef TARGET_RETURN_IN_MEMORY
206 #define TARGET_RETURN_IN_MEMORY pdp11_return_in_memory
208 #undef TARGET_FUNCTION_VALUE
209 #define TARGET_FUNCTION_VALUE pdp11_function_value
210 #undef TARGET_LIBCALL_VALUE
211 #define TARGET_LIBCALL_VALUE pdp11_libcall_value
212 #undef TARGET_FUNCTION_VALUE_REGNO_P
213 #define TARGET_FUNCTION_VALUE_REGNO_P pdp11_function_value_regno_p
215 #undef TARGET_TRAMPOLINE_INIT
216 #define TARGET_TRAMPOLINE_INIT pdp11_trampoline_init
218 #undef TARGET_SECONDARY_RELOAD
219 #define TARGET_SECONDARY_RELOAD pdp11_secondary_reload
221 #undef TARGET_REGISTER_MOVE_COST
222 #define TARGET_REGISTER_MOVE_COST pdp11_register_move_cost
224 #undef TARGET_PREFERRED_RELOAD_CLASS
225 #define TARGET_PREFERRED_RELOAD_CLASS pdp11_preferred_reload_class
227 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
228 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS pdp11_preferred_output_reload_class
230 #undef TARGET_LEGITIMATE_ADDRESS_P
231 #define TARGET_LEGITIMATE_ADDRESS_P pdp11_legitimate_address_p
233 #undef TARGET_CONDITIONAL_REGISTER_USAGE
234 #define TARGET_CONDITIONAL_REGISTER_USAGE pdp11_conditional_register_usage
236 #undef TARGET_ASM_FUNCTION_SECTION
237 #define TARGET_ASM_FUNCTION_SECTION pdp11_function_section
239 #undef TARGET_PRINT_OPERAND
240 #define TARGET_PRINT_OPERAND pdp11_asm_print_operand
242 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
243 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P pdp11_asm_print_operand_punct_valid_p
245 #undef TARGET_LEGITIMATE_CONSTANT_P
246 #define TARGET_LEGITIMATE_CONSTANT_P pdp11_legitimate_constant_p
248 #undef TARGET_SCALAR_MODE_SUPPORTED_P
249 #define TARGET_SCALAR_MODE_SUPPORTED_P pdp11_scalar_mode_supported_p
251 /* A helper function to determine if REGNO should be saved in the
252 current function's stack frame. */
255 pdp11_saved_regno (unsigned regno
)
257 return !call_used_regs
[regno
] && df_regs_ever_live_p (regno
);
260 /* Expand the function prologue. */
263 pdp11_expand_prologue (void)
265 HOST_WIDE_INT fsize
= get_frame_size ();
267 rtx x
, via_ac
= NULL
;
269 /* If we are outputting code for main, the switch FPU to the
270 right mode if TARGET_FPU. */
271 if (MAIN_NAME_P (DECL_NAME (current_function_decl
)) && TARGET_FPU
)
273 emit_insn (gen_setd ());
274 emit_insn (gen_seti ());
277 if (frame_pointer_needed
)
279 x
= gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
);
280 x
= gen_frame_mem (Pmode
, x
);
281 emit_move_insn (x
, hard_frame_pointer_rtx
);
283 emit_move_insn (hard_frame_pointer_rtx
, stack_pointer_rtx
);
289 emit_insn (gen_addhi3 (stack_pointer_rtx
, stack_pointer_rtx
,
292 /* Prevent frame references via the frame pointer from being
293 scheduled before the frame is allocated. */
294 if (frame_pointer_needed
)
295 emit_insn (gen_blockage ());
298 /* Save CPU registers. */
299 for (regno
= R0_REGNUM
; regno
<= PC_REGNUM
; regno
++)
300 if (pdp11_saved_regno (regno
)
301 && (regno
!= HARD_FRAME_POINTER_REGNUM
|| !frame_pointer_needed
))
303 x
= gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
);
304 x
= gen_frame_mem (Pmode
, x
);
305 emit_move_insn (x
, gen_rtx_REG (Pmode
, regno
));
308 /* Save FPU registers. */
309 for (regno
= AC0_REGNUM
; regno
<= AC3_REGNUM
; regno
++)
310 if (pdp11_saved_regno (regno
))
312 x
= gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
);
313 x
= gen_frame_mem (DFmode
, x
);
314 via_ac
= gen_rtx_REG (DFmode
, regno
);
315 emit_move_insn (x
, via_ac
);
318 /* ??? Maybe make ac4, ac5 call used regs?? */
319 for (regno
= AC4_REGNUM
; regno
<= AC5_REGNUM
; regno
++)
320 if (pdp11_saved_regno (regno
))
322 gcc_assert (via_ac
!= NULL
);
323 emit_move_insn (via_ac
, gen_rtx_REG (DFmode
, regno
));
325 x
= gen_rtx_PRE_DEC (Pmode
, stack_pointer_rtx
);
326 x
= gen_frame_mem (DFmode
, x
);
327 emit_move_insn (x
, via_ac
);
331 /* The function epilogue should not depend on the current stack pointer!
332 It should use the frame pointer only. This is mandatory because
333 of alloca; we also take advantage of it to omit stack adjustments
336 /* Maybe we can make leaf functions faster by switching to the
337 second register file - this way we don't have to save regs!
338 leaf functions are ~ 50% of all functions (dynamically!)
340 set/clear bit 11 (dec. 2048) of status word for switching register files -
341 but how can we do this? the pdp11/45 manual says bit may only
342 be set (p.24), but not cleared!
344 switching to kernel is probably more expensive, so we'll leave it
345 like this and not use the second set of registers...
347 maybe as option if you want to generate code for kernel mode? */
350 pdp11_expand_epilogue (void)
352 HOST_WIDE_INT fsize
= get_frame_size ();
354 rtx x
, reg
, via_ac
= NULL
;
356 if (pdp11_saved_regno (AC4_REGNUM
) || pdp11_saved_regno (AC5_REGNUM
))
358 /* Find a temporary with which to restore AC4/5. */
359 for (regno
= AC0_REGNUM
; regno
<= AC3_REGNUM
; regno
++)
360 if (pdp11_saved_regno (regno
))
362 via_ac
= gen_rtx_REG (DFmode
, regno
);
367 /* If possible, restore registers via pops. */
368 if (!frame_pointer_needed
|| crtl
->sp_is_unchanging
)
370 /* Restore registers via pops. */
372 for (regno
= AC5_REGNUM
; regno
>= AC0_REGNUM
; regno
--)
373 if (pdp11_saved_regno (regno
))
375 x
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
376 x
= gen_frame_mem (DFmode
, x
);
377 reg
= gen_rtx_REG (DFmode
, regno
);
379 if (LOAD_FPU_REG_P (regno
))
380 emit_move_insn (reg
, x
);
383 emit_move_insn (via_ac
, x
);
384 emit_move_insn (reg
, via_ac
);
388 for (regno
= PC_REGNUM
; regno
>= R0_REGNUM
+ 2; regno
--)
389 if (pdp11_saved_regno (regno
)
390 && (regno
!= HARD_FRAME_POINTER_REGNUM
|| !frame_pointer_needed
))
392 x
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
393 x
= gen_frame_mem (Pmode
, x
);
394 emit_move_insn (gen_rtx_REG (Pmode
, regno
), x
);
399 /* Restore registers via moves. */
400 /* ??? If more than a few registers need to be restored, it's smaller
401 to generate a pointer through which we can emit pops. Consider
402 that moves cost 2*NREG words and pops cost NREG+3 words. This
403 means that the crossover is NREG=3.
405 Possible registers to use are:
406 (1) The first call-saved general register. This register will
407 be restored with the last pop.
408 (2) R1, if it's not used as a return register.
409 (3) FP itself. This option may result in +4 words, since we
410 may need two add imm,rn instructions instead of just one.
411 This also has the downside that we're not representing
412 the unwind info in any way, so during the epilogue the
413 debugger may get lost. */
415 HOST_WIDE_INT ofs
= -pdp11_sp_frame_offset ();
417 for (regno
= AC5_REGNUM
; regno
>= AC0_REGNUM
; regno
--)
418 if (pdp11_saved_regno (regno
))
420 x
= plus_constant (Pmode
, hard_frame_pointer_rtx
, ofs
);
421 x
= gen_frame_mem (DFmode
, x
);
422 reg
= gen_rtx_REG (DFmode
, regno
);
424 if (LOAD_FPU_REG_P (regno
))
425 emit_move_insn (reg
, x
);
428 emit_move_insn (via_ac
, x
);
429 emit_move_insn (reg
, via_ac
);
434 for (regno
= PC_REGNUM
; regno
>= R0_REGNUM
+ 2; regno
--)
435 if (pdp11_saved_regno (regno
)
436 && (regno
!= HARD_FRAME_POINTER_REGNUM
|| !frame_pointer_needed
))
438 x
= plus_constant (Pmode
, hard_frame_pointer_rtx
, ofs
);
439 x
= gen_frame_mem (Pmode
, x
);
440 emit_move_insn (gen_rtx_REG (Pmode
, regno
), x
);
445 /* Deallocate the stack frame. */
448 /* Prevent frame references via any pointer from being
449 scheduled after the frame is deallocated. */
450 emit_insn (gen_blockage ());
452 if (frame_pointer_needed
)
454 /* We can deallocate the frame with a single move. */
455 emit_move_insn (stack_pointer_rtx
, hard_frame_pointer_rtx
);
458 emit_insn (gen_addhi3 (stack_pointer_rtx
, stack_pointer_rtx
,
462 if (frame_pointer_needed
)
464 x
= gen_rtx_POST_INC (Pmode
, stack_pointer_rtx
);
465 x
= gen_frame_mem (Pmode
, x
);
466 emit_move_insn (hard_frame_pointer_rtx
, x
);
469 emit_jump_insn (gen_return ());
472 /* Return the best assembler insn template
473 for moving operands[1] into operands[0] as a fullword. */
475 singlemove_string (rtx
*operands
)
477 if (operands
[1] != const0_rtx
)
484 /* Expand multi-word operands (SImode or DImode) into the 2 or 4
485 corresponding HImode operands. The number of operands is given
486 as the third argument, and the required order of the parts as
487 the fourth argument. */
489 pdp11_expand_operands (rtx
*operands
, rtx exops
[][2], int opcount
,
490 pdp11_action
*action
, pdp11_partorder order
)
492 int words
, op
, w
, i
, sh
;
493 pdp11_partorder useorder
;
494 bool sameoff
= false;
495 enum { REGOP
, OFFSOP
, MEMOP
, PUSHOP
, POPOP
, CNSTOP
, RNDOP
} optype
;
499 words
= GET_MODE_BITSIZE (GET_MODE (operands
[0])) / 16;
501 /* If either piece order is accepted and one is pre-decrement
502 while the other is post-increment, set order to be high order
503 word first. That will force the pre-decrement to be turned
504 into a pointer adjust, then offset addressing.
505 Otherwise, if either operand uses pre-decrement, that means
506 the order is low order first.
507 Otherwise, if both operands are registers and destination is
508 higher than source and they overlap, do low order word (highest
509 register number) first. */
513 if (!REG_P (operands
[0]) && !REG_P (operands
[1]) &&
514 !(CONSTANT_P (operands
[1]) ||
515 GET_CODE (operands
[1]) == CONST_DOUBLE
) &&
516 ((GET_CODE (XEXP (operands
[0], 0)) == POST_INC
&&
517 GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
) ||
518 (GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
&&
519 GET_CODE (XEXP (operands
[1], 0)) == POST_INC
)))
521 else if ((!REG_P (operands
[0]) &&
522 GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
) ||
523 (!REG_P (operands
[1]) &&
524 !(CONSTANT_P (operands
[1]) ||
525 GET_CODE (operands
[1]) == CONST_DOUBLE
) &&
526 GET_CODE (XEXP (operands
[1], 0)) == PRE_DEC
))
528 else if (REG_P (operands
[0]) && REG_P (operands
[1]) &&
529 REGNO (operands
[0]) > REGNO (operands
[1]) &&
530 REGNO (operands
[0]) < REGNO (operands
[1]) + words
)
533 /* Check for source == offset from register and dest == push of
534 the same register. In that case, we have to use the same
535 offset (the one for the low order word) for all words, because
536 the push increases the offset to each source word.
537 In theory there are other cases like this, for example dest == pop,
538 but those don't occur in real life so ignore those. */
539 if (GET_CODE (operands
[0]) == MEM
540 && GET_CODE (XEXP (operands
[0], 0)) == PRE_DEC
541 && REGNO (XEXP (XEXP (operands
[0], 0), 0)) == STACK_POINTER_REGNUM
542 && reg_overlap_mentioned_p (stack_pointer_rtx
, operands
[1]))
546 /* If the caller didn't specify order, use the one we computed,
547 or high word first if we don't care either. If the caller did
548 specify, verify we don't have a problem with that order.
549 (If it matters to the caller, constraints need to be used to
550 ensure this case doesn't occur). */
552 order
= (useorder
== either
) ? big
: useorder
;
554 gcc_assert (useorder
== either
|| useorder
== order
);
557 for (op
= 0; op
< opcount
; op
++)
559 /* First classify the operand. */
560 if (REG_P (operands
[op
]))
562 else if (CONSTANT_P (operands
[op
])
563 || GET_CODE (operands
[op
]) == CONST_DOUBLE
)
565 else if (GET_CODE (XEXP (operands
[op
], 0)) == POST_INC
)
567 else if (GET_CODE (XEXP (operands
[op
], 0)) == PRE_DEC
)
569 else if (!reload_in_progress
|| offsettable_memref_p (operands
[op
]))
571 else if (GET_CODE (operands
[op
]) == MEM
)
576 /* Check for the cases that the operand constraints are not
577 supposed to allow to happen. Return failure for such cases. */
582 action
[op
] = no_action
;
584 /* If the operand uses pre-decrement addressing but we
585 want to get the parts high order first,
586 decrement the former register explicitly
587 and change the operand into ordinary indexing. */
588 if (optype
== PUSHOP
&& order
== big
)
590 gcc_assert (action
!= NULL
);
591 action
[op
] = dec_before
;
592 operands
[op
] = gen_rtx_MEM (GET_MODE (operands
[op
]),
593 XEXP (XEXP (operands
[op
], 0), 0));
596 /* If the operand uses post-increment mode but we want
597 to get the parts low order first, change the operand
598 into ordinary indexing and remember to increment
599 the register explicitly when we're done. */
600 else if (optype
== POPOP
&& order
== little
)
602 gcc_assert (action
!= NULL
);
603 action
[op
] = inc_after
;
604 operands
[op
] = gen_rtx_MEM (GET_MODE (operands
[op
]),
605 XEXP (XEXP (operands
[op
], 0), 0));
609 if (GET_CODE (operands
[op
]) == CONST_DOUBLE
)
611 REAL_VALUE_FROM_CONST_DOUBLE (r
, operands
[op
]);
612 REAL_VALUE_TO_TARGET_DOUBLE (r
, sval
);
615 for (i
= 0; i
< words
; i
++)
624 /* Set the output operand to be word "w" of the input. */
626 exops
[i
][op
] = gen_rtx_REG (HImode
, REGNO (operands
[op
]) + w
);
627 else if (optype
== OFFSOP
)
628 exops
[i
][op
] = adjust_address (operands
[op
], HImode
, w
* 2);
629 else if (optype
== CNSTOP
)
631 if (GET_CODE (operands
[op
]) == CONST_DOUBLE
)
633 sh
= 16 - (w
& 1) * 16;
634 exops
[i
][op
] = gen_rtx_CONST_INT (HImode
, (sval
[w
/ 2] >> sh
) & 0xffff);
638 sh
= ((words
- 1 - w
) * 16);
639 exops
[i
][op
] = gen_rtx_CONST_INT (HImode
, trunc_int_for_mode (INTVAL(operands
[op
]) >> sh
, HImode
));
643 exops
[i
][op
] = operands
[op
];
649 /* Output assembler code to perform a multiple-word move insn
650 with operands OPERANDS. This moves 2 or 4 words depending
651 on the machine mode of the operands. */
654 output_move_multiple (rtx
*operands
)
657 pdp11_action action
[2];
660 words
= GET_MODE_BITSIZE (GET_MODE (operands
[0])) / 16;
662 pdp11_expand_operands (operands
, exops
, 2, action
, either
);
664 /* Check for explicit decrement before. */
665 if (action
[0] == dec_before
)
667 operands
[0] = XEXP (operands
[0], 0);
668 output_asm_insn ("sub $4,%0", operands
);
670 if (action
[1] == dec_before
)
672 operands
[1] = XEXP (operands
[1], 0);
673 output_asm_insn ("sub $4,%1", operands
);
677 for (i
= 0; i
< words
; i
++)
678 output_asm_insn (singlemove_string (exops
[i
]), exops
[i
]);
680 /* Check for increment after. */
681 if (action
[0] == inc_after
)
683 operands
[0] = XEXP (operands
[0], 0);
684 output_asm_insn ("add $4,%0", operands
);
686 if (action
[1] == inc_after
)
688 operands
[1] = XEXP (operands
[1], 0);
689 output_asm_insn ("add $4,%1", operands
);
695 /* Output an ascii string. */
697 output_ascii (FILE *file
, const char *p
, int size
)
701 /* This used to output .byte "string", which doesn't work with the UNIX
702 assembler and I think not with DEC ones either. */
703 fprintf (file
, "\t.byte ");
705 for (i
= 0; i
< size
; i
++)
707 register int c
= p
[i
];
710 fprintf (file
, "%#o", c
);
719 pdp11_asm_output_var (FILE *file
, const char *name
, int size
,
720 int align
, bool global
)
723 fprintf (file
, "\n\t.even\n");
726 fprintf (file
, ".globl ");
727 assemble_name (file
, name
);
729 fprintf (file
, "\n");
730 assemble_name (file
, name
);
731 fprintf (file
, ": .=.+ %#ho\n", (unsigned short)size
);
735 pdp11_asm_print_operand (FILE *file
, rtx x
, int code
)
742 else if (code
== '@')
749 else if (GET_CODE (x
) == REG
)
750 fprintf (file
, "%s", reg_names
[REGNO (x
)]);
751 else if (GET_CODE (x
) == MEM
)
752 output_address (XEXP (x
, 0));
753 else if (GET_CODE (x
) == CONST_DOUBLE
&& GET_MODE (x
) != SImode
)
755 REAL_VALUE_FROM_CONST_DOUBLE (r
, x
);
756 REAL_VALUE_TO_TARGET_DOUBLE (r
, sval
);
757 fprintf (file
, "$%#lo", sval
[0] >> 16);
762 output_addr_const_pdp11 (file
, x
);
767 pdp11_asm_print_operand_punct_valid_p (unsigned char c
)
769 return (c
== '#' || c
== '@');
773 print_operand_address (FILE *file
, register rtx addr
)
781 switch (GET_CODE (addr
))
788 addr
= XEXP (addr
, 0);
793 fprintf (file
, "(%s)", reg_names
[REGNO (addr
)]);
798 fprintf (file
, "-(%s)", reg_names
[REGNO (XEXP (addr
, 0))]);
803 fprintf (file
, "(%s)+", reg_names
[REGNO (XEXP (addr
, 0))]);
809 if (CONSTANT_ADDRESS_P (XEXP (addr
, 0))
810 || GET_CODE (XEXP (addr
, 0)) == MEM
)
812 offset
= XEXP (addr
, 0);
813 addr
= XEXP (addr
, 1);
815 else if (CONSTANT_ADDRESS_P (XEXP (addr
, 1))
816 || GET_CODE (XEXP (addr
, 1)) == MEM
)
818 offset
= XEXP (addr
, 1);
819 addr
= XEXP (addr
, 0);
821 if (GET_CODE (addr
) != PLUS
)
823 else if (GET_CODE (XEXP (addr
, 0)) == REG
)
825 breg
= XEXP (addr
, 0);
826 addr
= XEXP (addr
, 1);
828 else if (GET_CODE (XEXP (addr
, 1)) == REG
)
830 breg
= XEXP (addr
, 1);
831 addr
= XEXP (addr
, 0);
833 if (GET_CODE (addr
) == REG
)
835 gcc_assert (breg
== 0);
841 gcc_assert (addr
== 0);
845 output_addr_const_pdp11 (file
, addr
);
848 gcc_assert (GET_CODE (breg
) == REG
);
849 fprintf (file
, "(%s)", reg_names
[REGNO (breg
)]);
854 if (!again
&& GET_CODE (addr
) == CONST_INT
)
856 /* Absolute (integer number) address. */
857 if (!TARGET_UNIX_ASM
)
858 fprintf (file
, "@$");
860 output_addr_const_pdp11 (file
, addr
);
864 /* Target hook to assemble integer objects. We need to use the
865 pdp-specific version of output_addr_const. */
868 pdp11_assemble_integer (rtx x
, unsigned int size
, int aligned_p
)
874 fprintf (asm_out_file
, "\t.byte\t");
875 output_addr_const_pdp11 (asm_out_file
, GEN_INT (INTVAL (x
) & 0xff));
877 fprintf (asm_out_file
, " /* char */\n");
881 fprintf (asm_out_file
, TARGET_UNIX_ASM
? "\t" : "\t.word\t");
882 output_addr_const_pdp11 (asm_out_file
, x
);
883 fprintf (asm_out_file
, " /* short */\n");
886 return default_assemble_integer (x
, size
, aligned_p
);
890 /* register move costs, indexed by regs */
892 static const int move_costs
[N_REG_CLASSES
][N_REG_CLASSES
] =
894 /* NO MUL GEN LFPU NLFPU FPU ALL */
896 /* NO */ { 0, 0, 0, 0, 0, 0, 0},
897 /* MUL */ { 0, 2, 2, 22, 22, 22, 22},
898 /* GEN */ { 0, 2, 2, 22, 22, 22, 22},
899 /* LFPU */ { 0, 22, 22, 2, 2, 2, 22},
900 /* NLFPU */ { 0, 22, 22, 2, 10, 10, 22},
901 /* FPU */ { 0, 22, 22, 2, 10, 10, 22},
902 /* ALL */ { 0, 22, 22, 22, 22, 22, 22}
906 /* -- note that some moves are tremendously expensive,
907 because they require lots of tricks! do we have to
908 charge the costs incurred by secondary reload class
909 -- as we do here with 10 -- or not ? */
912 pdp11_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
913 reg_class_t c1
, reg_class_t c2
)
915 return move_costs
[(int)c1
][(int)c2
];
919 pdp11_rtx_costs (rtx x
, int code
, int outer_code ATTRIBUTE_UNUSED
,
920 int opno ATTRIBUTE_UNUSED
, int *total
,
921 bool speed ATTRIBUTE_UNUSED
)
926 if (INTVAL (x
) == 0 || INTVAL (x
) == -1 || INTVAL (x
) == 1)
936 /* Twice as expensive as REG. */
941 /* Twice (or 4 times) as expensive as 16 bit. */
946 /* ??? There is something wrong in MULT because MULT is not
947 as cheap as total = 2 even if we can shift! */
948 /* If optimizing for size make mult etc cheap, but not 1, so when
949 in doubt the faster insn is chosen. */
951 *total
= COSTS_N_INSNS (2);
953 *total
= COSTS_N_INSNS (11);
958 *total
= COSTS_N_INSNS (2);
960 *total
= COSTS_N_INSNS (25);
965 *total
= COSTS_N_INSNS (2);
967 *total
= COSTS_N_INSNS (26);
971 /* Equivalent to length, so same for optimize_size. */
972 *total
= COSTS_N_INSNS (3);
976 /* Only used for qi->hi. */
977 *total
= COSTS_N_INSNS (1);
981 if (GET_MODE (x
) == HImode
)
982 *total
= COSTS_N_INSNS (1);
983 else if (GET_MODE (x
) == SImode
)
984 *total
= COSTS_N_INSNS (6);
986 *total
= COSTS_N_INSNS (2);
993 *total
= COSTS_N_INSNS (1);
994 else if (GET_MODE (x
) == QImode
)
996 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
)
997 *total
= COSTS_N_INSNS (8); /* worst case */
999 *total
= COSTS_N_INSNS (INTVAL (XEXP (x
, 1)));
1001 else if (GET_MODE (x
) == HImode
)
1003 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1005 if (abs (INTVAL (XEXP (x
, 1))) == 1)
1006 *total
= COSTS_N_INSNS (1);
1008 *total
= COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x
, 1)));
1011 *total
= COSTS_N_INSNS (10); /* worst case */
1013 else if (GET_MODE (x
) == SImode
)
1015 if (GET_CODE (XEXP (x
, 1)) == CONST_INT
)
1016 *total
= COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x
, 1)));
1017 else /* worst case */
1018 *total
= COSTS_N_INSNS (18);
1028 output_jump (enum rtx_code code
, int inv
, int length
)
1032 static char buf
[1000];
1033 const char *pos
, *neg
;
1035 if (cc_prev_status
.flags
& CC_NO_OVERFLOW
)
1039 case GTU
: code
= GT
; break;
1040 case LTU
: code
= LT
; break;
1041 case GEU
: code
= GE
; break;
1042 case LEU
: code
= LE
; break;
1048 case EQ
: pos
= "beq", neg
= "bne"; break;
1049 case NE
: pos
= "bne", neg
= "beq"; break;
1050 case GT
: pos
= "bgt", neg
= "ble"; break;
1051 case GTU
: pos
= "bhi", neg
= "blos"; break;
1052 case LT
: pos
= "blt", neg
= "bge"; break;
1053 case LTU
: pos
= "blo", neg
= "bhis"; break;
1054 case GE
: pos
= "bge", neg
= "blt"; break;
1055 case GEU
: pos
= "bhis", neg
= "blo"; break;
1056 case LE
: pos
= "ble", neg
= "bgt"; break;
1057 case LEU
: pos
= "blos", neg
= "bhi"; break;
1058 default: gcc_unreachable ();
1062 /* currently we don't need this, because the tstdf and cmpdf
1063 copy the condition code immediately, and other float operations are not
1064 yet recognized as changing the FCC - if so, then the length-cost of all
1065 jump insns increases by one, because we have to potentially copy the
1067 if (cc_status
.flags
& CC_IN_FPU
)
1068 output_asm_insn("cfcc", NULL
);
1075 sprintf(buf
, "%s %%l1", inv
? neg
: pos
);
1081 sprintf(buf
, "%s JMP_%d\n\tjmp %%l1\nJMP_%d:", inv
? pos
: neg
, x
, x
);
1095 notice_update_cc_on_set(rtx exp
, rtx insn ATTRIBUTE_UNUSED
)
1097 if (GET_CODE (SET_DEST (exp
)) == CC0
)
1099 cc_status
.flags
= 0;
1100 cc_status
.value1
= SET_DEST (exp
);
1101 cc_status
.value2
= SET_SRC (exp
);
1103 else if (GET_CODE (SET_SRC (exp
)) == CALL
)
1107 else if (SET_DEST(exp
) == pc_rtx
)
1111 else if (GET_MODE (SET_DEST(exp
)) == HImode
1112 || GET_MODE (SET_DEST(exp
)) == QImode
)
1114 cc_status
.flags
= GET_CODE (SET_SRC(exp
)) == MINUS
? 0 : CC_NO_OVERFLOW
;
1115 cc_status
.value1
= SET_SRC (exp
);
1116 cc_status
.value2
= SET_DEST (exp
);
1118 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == REG
1120 && reg_overlap_mentioned_p (cc_status
.value1
, cc_status
.value2
))
1121 cc_status
.value2
= 0;
1122 if (cc_status
.value1
&& GET_CODE (cc_status
.value1
) == MEM
1124 && GET_CODE (cc_status
.value2
) == MEM
)
1125 cc_status
.value2
= 0;
1135 simple_memory_operand(rtx op
, machine_mode mode ATTRIBUTE_UNUSED
)
1139 /* Eliminate non-memory operations */
1140 if (GET_CODE (op
) != MEM
)
1144 /* dword operations really put out 2 instructions, so eliminate them. */
1145 if (GET_MODE_SIZE (GET_MODE (op
)) > (HAVE_64BIT_P () ? 8 : 4))
1149 /* Decode the address now. */
1153 addr
= XEXP (op
, 0);
1155 switch (GET_CODE (addr
))
1158 /* (R0) - no extra cost */
1163 /* -(R0), (R0)+ - cheap! */
1167 /* cheap - is encoded in addressing mode info!
1169 -- except for @(R0), which has to be @0(R0) !!! */
1171 if (GET_CODE (XEXP (addr
, 0)) == REG
)
1181 /* @#address - extra cost */
1185 /* X(R0) - extra cost */
1197 * output a block move:
1199 * operands[0] ... to
1200 * operands[1] ... from
1201 * operands[2] ... length
1202 * operands[3] ... alignment
1203 * operands[4] ... scratch register
1208 output_block_move(rtx
*operands
)
1210 static int count
= 0;
1215 /* Move of zero bytes is a NOP. */
1216 if (operands
[2] == const0_rtx
)
1219 /* Look for moves by small constant byte counts, those we'll
1220 expand to straight line code. */
1221 if (CONSTANT_P (operands
[2]))
1223 if (INTVAL (operands
[2]) < 16
1224 && (!optimize_size
|| INTVAL (operands
[2]) < 5)
1225 && INTVAL (operands
[3]) == 1)
1229 for (i
= 1; i
<= INTVAL (operands
[2]); i
++)
1230 output_asm_insn("movb (%1)+, (%0)+", operands
);
1234 else if (INTVAL(operands
[2]) < 32
1235 && (!optimize_size
|| INTVAL (operands
[2]) < 9)
1236 && INTVAL (operands
[3]) >= 2)
1240 for (i
= 1; i
<= INTVAL (operands
[2]) / 2; i
++)
1241 output_asm_insn ("mov (%1)+, (%0)+", operands
);
1242 if (INTVAL (operands
[2]) & 1)
1243 output_asm_insn ("movb (%1), (%0)", operands
);
1249 /* Ideally we'd look for moves that are multiples of 4 or 8
1250 bytes and handle those by unrolling the move loop. That
1251 makes for a lot of code if done at run time, but it's ok
1252 for constant counts. Also, for variable counts we have
1253 to worry about odd byte count with even aligned pointers.
1254 On 11/40 and up we handle that case; on older machines
1255 we don't and just use byte-wise moves all the time. */
1257 if (CONSTANT_P (operands
[2]) )
1259 if (INTVAL (operands
[3]) < 2)
1263 lastbyte
= INTVAL (operands
[2]) & 1;
1265 if (optimize_size
|| INTVAL (operands
[2]) & 2)
1267 else if (INTVAL (operands
[2]) & 4)
1273 /* Loop count is byte count scaled by unroll. */
1274 operands
[2] = GEN_INT (INTVAL (operands
[2]) >> unroll
);
1275 output_asm_insn ("mov %2, %4", operands
);
1279 /* Variable byte count; use the input register
1281 operands
[4] = operands
[2];
1283 /* Decide whether to move by words, and check
1284 the byte count for zero. */
1285 if (TARGET_40_PLUS
&& INTVAL (operands
[3]) > 1)
1288 output_asm_insn ("asr %4", operands
);
1293 output_asm_insn ("tst %4", operands
);
1295 sprintf (buf
, "beq movestrhi%d", count
+ 1);
1296 output_asm_insn (buf
, NULL
);
1299 /* Output the loop label. */
1300 sprintf (buf
, "\nmovestrhi%d:", count
);
1301 output_asm_insn (buf
, NULL
);
1303 /* Output the appropriate move instructions. */
1307 output_asm_insn ("movb (%1)+, (%0)+", operands
);
1311 output_asm_insn ("mov (%1)+, (%0)+", operands
);
1315 output_asm_insn ("mov (%1)+, (%0)+", operands
);
1316 output_asm_insn ("mov (%1)+, (%0)+", operands
);
1320 output_asm_insn ("mov (%1)+, (%0)+", operands
);
1321 output_asm_insn ("mov (%1)+, (%0)+", operands
);
1322 output_asm_insn ("mov (%1)+, (%0)+", operands
);
1323 output_asm_insn ("mov (%1)+, (%0)+", operands
);
1327 /* Output the decrement and test. */
1330 sprintf (buf
, "sob %%4, movestrhi%d", count
);
1331 output_asm_insn (buf
, operands
);
1335 output_asm_insn ("dec %4", operands
);
1336 sprintf (buf
, "bgt movestrhi%d", count
);
1337 output_asm_insn (buf
, NULL
);
1341 /* If constant odd byte count, move the last byte. */
1343 output_asm_insn ("movb (%1), (%0)", operands
);
1344 else if (!CONSTANT_P (operands
[2]))
1346 /* Output the destination label for the zero byte count check. */
1347 sprintf (buf
, "\nmovestrhi%d:", count
);
1348 output_asm_insn (buf
, NULL
);
1351 /* If we did word moves, check for trailing last byte. */
1354 sprintf (buf
, "bcc movestrhi%d", count
);
1355 output_asm_insn (buf
, NULL
);
1356 output_asm_insn ("movb (%1), (%0)", operands
);
1357 sprintf (buf
, "\nmovestrhi%d:", count
);
1358 output_asm_insn (buf
, NULL
);
1366 /* This function checks whether a real value can be encoded as
1367 a literal, i.e., addressing mode 27. In that mode, real values
1368 are one word values, so the remaining 48 bits have to be zero. */
1370 legitimate_const_double_p (rtx address
)
1374 REAL_VALUE_FROM_CONST_DOUBLE (r
, address
);
1375 REAL_VALUE_TO_TARGET_DOUBLE (r
, sval
);
1376 if ((sval
[0] & 0xffff) == 0 && sval
[1] == 0)
1381 /* Implement CANNOT_CHANGE_MODE_CLASS. */
1383 pdp11_cannot_change_mode_class (machine_mode from
,
1385 enum reg_class rclass
)
1387 /* Also, FPU registers contain a whole float value and the parts of
1388 it are not separately accessible.
1390 So we disallow all mode changes involving FPRs. */
1391 if (FLOAT_MODE_P (from
) != FLOAT_MODE_P (to
))
1394 return reg_classes_intersect_p (FPU_REGS
, rclass
);
1397 /* TARGET_PREFERRED_RELOAD_CLASS
1399 Given an rtx X being reloaded into a reg required to be
1400 in class CLASS, return the class of reg to actually use.
1401 In general this is just CLASS; but on some machines
1402 in some cases it is preferable to use a more restrictive class.
1404 loading is easier into LOAD_FPU_REGS than FPU_REGS! */
1407 pdp11_preferred_reload_class (rtx x
, reg_class_t rclass
)
1409 if (rclass
== FPU_REGS
)
1410 return LOAD_FPU_REGS
;
1411 if (rclass
== ALL_REGS
)
1413 if (FLOAT_MODE_P (GET_MODE (x
)))
1414 return LOAD_FPU_REGS
;
1416 return GENERAL_REGS
;
1421 /* TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
1423 Given an rtx X being reloaded into a reg required to be
1424 in class CLASS, return the class of reg to actually use.
1425 In general this is just CLASS; but on some machines
1426 in some cases it is preferable to use a more restrictive class.
1428 loading is easier into LOAD_FPU_REGS than FPU_REGS! */
1431 pdp11_preferred_output_reload_class (rtx x
, reg_class_t rclass
)
1433 if (rclass
== FPU_REGS
)
1434 return LOAD_FPU_REGS
;
1435 if (rclass
== ALL_REGS
)
1437 if (FLOAT_MODE_P (GET_MODE (x
)))
1438 return LOAD_FPU_REGS
;
1440 return GENERAL_REGS
;
1446 /* TARGET_SECONDARY_RELOAD.
1448 FPU registers AC4 and AC5 (class NO_LOAD_FPU_REGS) require an
1449 intermediate register (AC0-AC3: LOAD_FPU_REGS). Everything else
1450 can be loade/stored directly. */
1452 pdp11_secondary_reload (bool in_p ATTRIBUTE_UNUSED
,
1454 reg_class_t reload_class
,
1455 machine_mode reload_mode ATTRIBUTE_UNUSED
,
1456 secondary_reload_info
*sri ATTRIBUTE_UNUSED
)
1458 if (reload_class
!= NO_LOAD_FPU_REGS
|| GET_CODE (x
) != REG
||
1459 REGNO_REG_CLASS (REGNO (x
)) == LOAD_FPU_REGS
)
1462 return LOAD_FPU_REGS
;
1465 /* Target routine to check if register to register move requires memory.
1467 The answer is yes if we're going between general register and FPU
1468 registers. The mode doesn't matter in making this check.
1471 pdp11_secondary_memory_needed (reg_class_t c1
, reg_class_t c2
,
1472 machine_mode mode ATTRIBUTE_UNUSED
)
1474 int fromfloat
= (c1
== LOAD_FPU_REGS
|| c1
== NO_LOAD_FPU_REGS
||
1476 int tofloat
= (c2
== LOAD_FPU_REGS
|| c2
== NO_LOAD_FPU_REGS
||
1479 return (fromfloat
!= tofloat
);
1482 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression
1483 that is a valid memory address for an instruction.
1484 The MODE argument is the machine mode for the MEM expression
1485 that wants to use this address.
1490 pdp11_legitimate_address_p (machine_mode mode
,
1491 rtx operand
, bool strict
)
1495 /* accept @#address */
1496 if (CONSTANT_ADDRESS_P (operand
))
1499 switch (GET_CODE (operand
))
1503 return !strict
|| REGNO_OK_FOR_BASE_P (REGNO (operand
));
1507 return GET_CODE (XEXP (operand
, 0)) == REG
1508 && (!strict
|| REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand
, 0))))
1509 && CONSTANT_ADDRESS_P (XEXP (operand
, 1));
1513 return GET_CODE (XEXP (operand
, 0)) == REG
1514 && (!strict
|| REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand
, 0))));
1518 return GET_CODE (XEXP (operand
, 0)) == REG
1519 && (!strict
|| REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand
, 0))));
1522 /* accept -(SP) -- which uses PRE_MODIFY for byte mode */
1523 return GET_CODE (XEXP (operand
, 0)) == REG
1524 && REGNO (XEXP (operand
, 0)) == STACK_POINTER_REGNUM
1525 && GET_CODE ((xfoob
= XEXP (operand
, 1))) == PLUS
1526 && GET_CODE (XEXP (xfoob
, 0)) == REG
1527 && REGNO (XEXP (xfoob
, 0)) == STACK_POINTER_REGNUM
1528 && CONSTANT_P (XEXP (xfoob
, 1))
1529 && INTVAL (XEXP (xfoob
,1)) == -2;
1532 /* accept (SP)+ -- which uses POST_MODIFY for byte mode */
1533 return GET_CODE (XEXP (operand
, 0)) == REG
1534 && REGNO (XEXP (operand
, 0)) == STACK_POINTER_REGNUM
1535 && GET_CODE ((xfoob
= XEXP (operand
, 1))) == PLUS
1536 && GET_CODE (XEXP (xfoob
, 0)) == REG
1537 && REGNO (XEXP (xfoob
, 0)) == STACK_POINTER_REGNUM
1538 && CONSTANT_P (XEXP (xfoob
, 1))
1539 && INTVAL (XEXP (xfoob
,1)) == 2;
1542 /* handle another level of indirection ! */
1543 xfoob
= XEXP (operand
, 0);
1545 /* (MEM:xx (MEM:xx ())) is not valid for SI, DI and currently
1546 also forbidden for float, because we have to handle this
1547 in output_move_double and/or output_move_quad() - we could
1548 do it, but currently it's not worth it!!!
1549 now that DFmode cannot go into CPU register file,
1550 maybe I should allow float ...
1551 but then I have to handle memory-to-memory moves in movdf ?? */
1552 if (GET_MODE_BITSIZE(mode
) > 16)
1555 /* accept @address */
1556 if (CONSTANT_ADDRESS_P (xfoob
))
1559 switch (GET_CODE (xfoob
))
1562 /* accept @(R0) - which is @0(R0) */
1563 return !strict
|| REGNO_OK_FOR_BASE_P(REGNO (xfoob
));
1567 return GET_CODE (XEXP (xfoob
, 0)) == REG
1568 && (!strict
|| REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob
, 0))))
1569 && CONSTANT_ADDRESS_P (XEXP (xfoob
, 1));
1573 return GET_CODE (XEXP (xfoob
, 0)) == REG
1574 && (!strict
|| REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob
, 0))));
1578 return GET_CODE (XEXP (xfoob
, 0)) == REG
1579 && (!strict
|| REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob
, 0))));
1582 /* anything else is invalid */
1587 /* anything else is invalid */
1592 /* Return the class number of the smallest class containing
1593 reg number REGNO. */
1595 pdp11_regno_reg_class (int regno
)
1597 if (regno
== FRAME_POINTER_REGNUM
|| regno
== ARG_POINTER_REGNUM
)
1598 return GENERAL_REGS
;
1599 else if (regno
> AC3_REGNUM
)
1600 return NO_LOAD_FPU_REGS
;
1601 else if (regno
>= AC0_REGNUM
)
1602 return LOAD_FPU_REGS
;
1606 return GENERAL_REGS
;
1611 pdp11_sp_frame_offset (void)
1613 int offset
= 0, regno
;
1614 offset
= get_frame_size();
1615 for (regno
= 0; regno
<= PC_REGNUM
; regno
++)
1616 if (pdp11_saved_regno (regno
))
1618 for (regno
= AC0_REGNUM
; regno
<= AC5_REGNUM
; regno
++)
1619 if (pdp11_saved_regno (regno
))
1625 /* Return the offset between two registers, one to be eliminated, and the other
1626 its replacement, at the start of a routine. */
1629 pdp11_initial_elimination_offset (int from
, int to
)
1633 if (from
== ARG_POINTER_REGNUM
&& to
== HARD_FRAME_POINTER_REGNUM
)
1635 else if (from
== FRAME_POINTER_REGNUM
1636 && to
== HARD_FRAME_POINTER_REGNUM
)
1640 gcc_assert (to
== STACK_POINTER_REGNUM
);
1642 /* Get the size of the register save area. */
1643 spoff
= pdp11_sp_frame_offset ();
1644 if (from
== FRAME_POINTER_REGNUM
)
1647 gcc_assert (from
== ARG_POINTER_REGNUM
);
1649 /* If there is a frame pointer, that is saved too. */
1650 if (frame_pointer_needed
)
1653 /* Account for the saved PC in the function call. */
1658 /* A copy of output_addr_const modified for pdp11 expression syntax.
1659 output_addr_const also gets called for %cDIGIT and %nDIGIT, which we don't
1660 use, and for debugging output, which we don't support with this port either.
1661 So this copy should get called whenever needed.
1664 output_addr_const_pdp11 (FILE *file
, rtx x
)
1670 switch (GET_CODE (x
))
1673 gcc_assert (flag_pic
);
1678 assemble_name (file
, XSTR (x
, 0));
1682 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (XEXP (x
, 0)));
1683 assemble_name (file
, buf
);
1687 ASM_GENERATE_INTERNAL_LABEL (buf
, "L", CODE_LABEL_NUMBER (x
));
1688 assemble_name (file
, buf
);
1696 fprintf (file
, "-");
1698 fprintf (file
, "%#o", i
& 0xffff);
1702 /* This used to output parentheses around the expression,
1703 but that does not work on the 386 (either ATT or BSD assembler). */
1704 output_addr_const_pdp11 (file
, XEXP (x
, 0));
1708 if (GET_MODE (x
) == VOIDmode
)
1710 /* We can use %o if the number is one word and positive. */
1711 gcc_assert (!CONST_DOUBLE_HIGH (x
));
1712 fprintf (file
, "%#ho", (unsigned short) CONST_DOUBLE_LOW (x
));
1715 /* We can't handle floating point constants;
1716 PRINT_OPERAND must handle them. */
1717 output_operand_lossage ("floating constant misused");
1721 /* Some assemblers need integer constants to appear last (e.g. masm). */
1722 if (GET_CODE (XEXP (x
, 0)) == CONST_INT
)
1724 output_addr_const_pdp11 (file
, XEXP (x
, 1));
1725 if (INTVAL (XEXP (x
, 0)) >= 0)
1726 fprintf (file
, "+");
1727 output_addr_const_pdp11 (file
, XEXP (x
, 0));
1731 output_addr_const_pdp11 (file
, XEXP (x
, 0));
1732 if (INTVAL (XEXP (x
, 1)) >= 0)
1733 fprintf (file
, "+");
1734 output_addr_const_pdp11 (file
, XEXP (x
, 1));
1739 /* Avoid outputting things like x-x or x+5-x,
1740 since some assemblers can't handle that. */
1741 x
= simplify_subtraction (x
);
1742 if (GET_CODE (x
) != MINUS
)
1745 output_addr_const_pdp11 (file
, XEXP (x
, 0));
1746 if (GET_CODE (XEXP (x
, 1)) != CONST_INT
1747 || INTVAL (XEXP (x
, 1)) >= 0)
1748 fprintf (file
, "-");
1749 output_addr_const_pdp11 (file
, XEXP (x
, 1));
1754 output_addr_const_pdp11 (file
, XEXP (x
, 0));
1758 output_operand_lossage ("invalid expression as operand");
1762 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1765 pdp11_return_in_memory (const_tree type
, const_tree fntype ATTRIBUTE_UNUSED
)
1767 /* Integers 32 bits and under, and scalar floats (if FPU), are returned
1768 in registers. The rest go into memory. */
1769 return (TYPE_MODE (type
) == DImode
1770 || (FLOAT_MODE_P (TYPE_MODE (type
)) && ! TARGET_AC0
)
1771 || TREE_CODE (type
) == VECTOR_TYPE
1772 || COMPLEX_MODE_P (TYPE_MODE (type
)));
1775 /* Worker function for TARGET_FUNCTION_VALUE.
1777 On the pdp11 the value is found in R0 (or ac0??? not without FPU!!!! ) */
1780 pdp11_function_value (const_tree valtype
,
1781 const_tree fntype_or_decl ATTRIBUTE_UNUSED
,
1782 bool outgoing ATTRIBUTE_UNUSED
)
1784 return gen_rtx_REG (TYPE_MODE (valtype
),
1785 BASE_RETURN_VALUE_REG(TYPE_MODE(valtype
)));
1788 /* Worker function for TARGET_LIBCALL_VALUE. */
1791 pdp11_libcall_value (machine_mode mode
,
1792 const_rtx fun ATTRIBUTE_UNUSED
)
1794 return gen_rtx_REG (mode
, BASE_RETURN_VALUE_REG(mode
));
1797 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P.
1799 On the pdp, the first "output" reg is the only register thus used.
1801 maybe ac0 ? - as option someday! */
1804 pdp11_function_value_regno_p (const unsigned int regno
)
1806 return (regno
== RETVAL_REGNUM
) || (TARGET_AC0
&& (regno
== AC0_REGNUM
));
1809 /* Worker function for TARGET_TRAMPOLINE_INIT.
1811 trampoline - how should i do it in separate i+d ?
1812 have some allocate_trampoline magic???
1814 the following should work for shared I/D:
1816 MOV #STATIC, $4 01270Y 0x0000 <- STATIC; Y = STATIC_CHAIN_REGNUM
1817 JMP @#FUNCTION 000137 0x0000 <- FUNCTION
1821 pdp11_trampoline_init (rtx m_tramp
, tree fndecl
, rtx chain_value
)
1823 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
1826 gcc_assert (!TARGET_SPLIT
);
1828 mem
= adjust_address (m_tramp
, HImode
, 0);
1829 emit_move_insn (mem
, GEN_INT (012700+STATIC_CHAIN_REGNUM
));
1830 mem
= adjust_address (m_tramp
, HImode
, 2);
1831 emit_move_insn (mem
, chain_value
);
1832 mem
= adjust_address (m_tramp
, HImode
, 4);
1833 emit_move_insn (mem
, GEN_INT (000137));
1834 emit_move_insn (mem
, fnaddr
);
1837 /* Worker function for TARGET_FUNCTION_ARG.
1839 Determine where to put an argument to a function.
1840 Value is zero to push the argument on the stack,
1841 or a hard register in which to store the argument.
1843 MODE is the argument's machine mode.
1844 TYPE is the data type of the argument (as a tree).
1845 This is null for libcalls where that information may
1847 CUM is a variable of type CUMULATIVE_ARGS which gives info about
1848 the preceding args and about the function being called.
1849 NAMED is nonzero if this argument is a named parameter
1850 (otherwise it is an extra parameter matching an ellipsis). */
1853 pdp11_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED
,
1854 machine_mode mode ATTRIBUTE_UNUSED
,
1855 const_tree type ATTRIBUTE_UNUSED
,
1856 bool named ATTRIBUTE_UNUSED
)
1861 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE.
1863 Update the data in CUM to advance over an argument of mode MODE and
1864 data type TYPE. (TYPE is null for libcalls where that information
1865 may not be available.) */
1868 pdp11_function_arg_advance (cumulative_args_t cum_v
, machine_mode mode
,
1869 const_tree type
, bool named ATTRIBUTE_UNUSED
)
1871 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
1873 *cum
+= (mode
!= BLKmode
1874 ? GET_MODE_SIZE (mode
)
1875 : int_size_in_bytes (type
));
1878 /* Make sure everything's fine if we *don't* have an FPU.
1879 This assumes that putting a register in fixed_regs will keep the
1880 compiler's mitts completely off it. We don't bother to zero it out
1881 of register classes. Also fix incompatible register naming with
1882 the UNIX assembler. */
1885 pdp11_conditional_register_usage (void)
1891 COPY_HARD_REG_SET (x
, reg_class_contents
[(int)FPU_REGS
]);
1892 for (i
= 0; i
< FIRST_PSEUDO_REGISTER
; i
++ )
1893 if (TEST_HARD_REG_BIT (x
, i
))
1894 fixed_regs
[i
] = call_used_regs
[i
] = 1;
1898 call_used_regs
[AC0_REGNUM
] = 1;
1899 if (TARGET_UNIX_ASM
)
1901 /* Change names of FPU registers for the UNIX assembler. */
1902 reg_names
[8] = "fr0";
1903 reg_names
[9] = "fr1";
1904 reg_names
[10] = "fr2";
1905 reg_names
[11] = "fr3";
1906 reg_names
[12] = "fr4";
1907 reg_names
[13] = "fr5";
1912 pdp11_function_section (tree decl ATTRIBUTE_UNUSED
,
1913 enum node_frequency freq ATTRIBUTE_UNUSED
,
1914 bool startup ATTRIBUTE_UNUSED
,
1915 bool exit ATTRIBUTE_UNUSED
)
1920 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */
1923 pdp11_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED
, rtx x
)
1925 return GET_CODE (x
) != CONST_DOUBLE
|| legitimate_const_double_p (x
);
1928 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
1931 pdp11_scalar_mode_supported_p (machine_mode mode
)
1933 /* Support SFmode even with -mfloat64. */
1936 return default_scalar_mode_supported_p (mode
);
1939 struct gcc_target targetm
= TARGET_INITIALIZER
;