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1 /* Subroutines used for code generation on IA-32.
2 Copyright (C) 1988-2015 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
109 #ifndef CHECK_STACK_LIMIT
110 #define CHECK_STACK_LIMIT (-1)
111 #endif
113 /* Return index of given mode in mult and division cost tables. */
114 #define MODE_INDEX(mode) \
115 ((mode) == QImode ? 0 \
116 : (mode) == HImode ? 1 \
117 : (mode) == SImode ? 2 \
118 : (mode) == DImode ? 3 \
119 : 4)
121 /* Processor costs (relative to an add) */
122 /* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */
123 #define COSTS_N_BYTES(N) ((N) * 2)
125 #define DUMMY_STRINGOP_ALGS {libcall, {{-1, libcall, false}}}
134 const
157 in QImode, HImode and SImode.
158 Relative to reg-reg move (2). */
162 in SFmode, DFmode and XFmode */
164 in SFmode, DFmode and XFmode */
167 in SImode and DImode */
169 in SImode and DImode */
172 in SImode, DImode and TImode */
174 in SImode, DImode and TImode */
187 ix86_size_memcpy,
188 ix86_size_memset,
200 };
202 /* Processor costs (relative to an add) */
205 DUMMY_STRINGOP_ALGS};
208 DUMMY_STRINGOP_ALGS};
210 static const
233 in QImode, HImode and SImode.
234 Relative to reg-reg move (2). */
238 in SFmode, DFmode and XFmode */
240 in SFmode, DFmode and XFmode */
243 in SImode and DImode */
245 in SImode and DImode */
248 in SImode, DImode and TImode */
250 in SImode, DImode and TImode */
263 i386_memcpy,
264 i386_memset,
276 };
280 DUMMY_STRINGOP_ALGS};
283 DUMMY_STRINGOP_ALGS};
285 static const
308 in QImode, HImode and SImode.
309 Relative to reg-reg move (2). */
313 in SFmode, DFmode and XFmode */
315 in SFmode, DFmode and XFmode */
318 in SImode and DImode */
320 in SImode and DImode */
323 in SImode, DImode and TImode */
325 in SImode, DImode and TImode */
328 shared for code and data, so 4kB is
329 not really precise. */
340 i486_memcpy,
341 i486_memset,
353 };
357 DUMMY_STRINGOP_ALGS};
360 DUMMY_STRINGOP_ALGS};
362 static const
385 in QImode, HImode and SImode.
386 Relative to reg-reg move (2). */
390 in SFmode, DFmode and XFmode */
392 in SFmode, DFmode and XFmode */
395 in SImode and DImode */
397 in SImode and DImode */
400 in SImode, DImode and TImode */
402 in SImode, DImode and TImode */
415 pentium_memcpy,
416 pentium_memset,
428 };
430 /* PentiumPro has optimized rep instructions for blocks aligned by 8 bytes
431 (we ensure the alignment). For small blocks inline loop is still a
432 noticeable win, for bigger blocks either rep movsl or rep movsb is
433 way to go. Rep movsb has apparently more expensive startup time in CPU,
434 but after 4K the difference is down in the noise. */
439 DUMMY_STRINGOP_ALGS};
444 DUMMY_STRINGOP_ALGS};
445 static const
468 in QImode, HImode and SImode.
469 Relative to reg-reg move (2). */
473 in SFmode, DFmode and XFmode */
475 in SFmode, DFmode and XFmode */
478 in SImode and DImode */
480 in SImode and DImode */
483 in SImode, DImode and TImode */
485 in SImode, DImode and TImode */
498 pentiumpro_memcpy,
499 pentiumpro_memset,
511 };
515 DUMMY_STRINGOP_ALGS};
518 DUMMY_STRINGOP_ALGS};
519 static const
542 in QImode, HImode and SImode.
543 Relative to reg-reg move (2). */
547 in SFmode, DFmode and XFmode */
549 in SFmode, DFmode and XFmode */
553 in SImode and DImode */
555 in SImode and DImode */
558 in SImode, DImode and TImode */
560 in SImode, DImode and TImode */
573 geode_memcpy,
574 geode_memset,
586 };
590 DUMMY_STRINGOP_ALGS};
593 DUMMY_STRINGOP_ALGS};
594 static const
617 in QImode, HImode and SImode.
618 Relative to reg-reg move (2). */
622 in SFmode, DFmode and XFmode */
624 in SFmode, DFmode and XFmode */
627 in SImode and DImode */
629 in SImode and DImode */
632 in SImode, DImode and TImode */
634 in SImode, DImode and TImode */
638 have integrated l2 cache, but
639 optimizing for k6 is not important
640 enough to worry about that. */
650 k6_memcpy,
651 k6_memset,
663 };
665 /* For some reason, Athlon deals better with REP prefix (relative to loops)
666 compared to K8. Alignment becomes important after 8 bytes for memcpy and
667 128 bytes for memset. */
670 DUMMY_STRINGOP_ALGS};
673 DUMMY_STRINGOP_ALGS};
674 static const
697 in QImode, HImode and SImode.
698 Relative to reg-reg move (2). */
702 in SFmode, DFmode and XFmode */
704 in SFmode, DFmode and XFmode */
707 in SImode and DImode */
709 in SImode and DImode */
712 in SImode, DImode and TImode */
714 in SImode, DImode and TImode */
727 athlon_memcpy,
728 athlon_memset,
740 };
742 /* K8 has optimized REP instruction for medium sized blocks, but for very
743 small blocks it is better to use loop. For large blocks, libcall can
744 do nontemporary accesses and beat inline considerably. */
755 static const
778 in QImode, HImode and SImode.
779 Relative to reg-reg move (2). */
783 in SFmode, DFmode and XFmode */
785 in SFmode, DFmode and XFmode */
788 in SImode and DImode */
790 in SImode and DImode */
793 in SImode, DImode and TImode */
795 in SImode, DImode and TImode */
800 /* New AMD processors never drop prefetches; if they cannot be performed
801 immediately, they are queued. We set number of simultaneous prefetches
802 to a large constant to reflect this (it probably is not a good idea not
803 to limit number of prefetches at all, as their execution also takes some
804 time). */
814 k8_memcpy,
815 k8_memset,
827 };
829 /* AMDFAM10 has optimized REP instruction for medium sized blocks, but for
830 very small blocks it is better to use loop. For large blocks, libcall can
831 do nontemporary accesses and beat inline considerably. */
864 in QImode, HImode and SImode.
865 Relative to reg-reg move (2). */
869 in SFmode, DFmode and XFmode */
871 in SFmode, DFmode and XFmode */
874 in SImode and DImode */
876 in SImode and DImode */
879 in SImode, DImode and TImode */
881 in SImode, DImode and TImode */
883 /* On K8:
884 MOVD reg64, xmmreg Double FSTORE 4
885 MOVD reg32, xmmreg Double FSTORE 4
886 On AMDFAM10:
887 MOVD reg64, xmmreg Double FADD 3
888 1/1 1/1
889 MOVD reg32, xmmreg Double FADD 3
890 1/1 1/1 */
894 /* New AMD processors never drop prefetches; if they cannot be performed
895 immediately, they are queued. We set number of simultaneous prefetches
896 to a large constant to reflect this (it probably is not a good idea not
897 to limit number of prefetches at all, as their execution also takes some
898 time). */
908 amdfam10_memcpy,
909 amdfam10_memset,
921 };
923 /* BDVER1 has optimized REP instruction for medium sized blocks, but for
924 very small blocks it is better to use loop. For large blocks, libcall
925 can do nontemporary accesses and beat inline considerably. */
959 in QImode, HImode and SImode.
960 Relative to reg-reg move (2). */
964 in SFmode, DFmode and XFmode */
966 in SFmode, DFmode and XFmode */
969 in SImode and DImode */
971 in SImode and DImode */
974 in SImode, DImode and TImode */
976 in SImode, DImode and TImode */
978 /* On K8:
979 MOVD reg64, xmmreg Double FSTORE 4
980 MOVD reg32, xmmreg Double FSTORE 4
981 On AMDFAM10:
982 MOVD reg64, xmmreg Double FADD 3
983 1/1 1/1
984 MOVD reg32, xmmreg Double FADD 3
985 1/1 1/1 */
989 /* New AMD processors never drop prefetches; if they cannot be performed
990 immediately, they are queued. We set number of simultaneous prefetches
991 to a large constant to reflect this (it probably is not a good idea not
992 to limit number of prefetches at all, as their execution also takes some
993 time). */
1003 bdver1_memcpy,
1004 bdver1_memset,
1016 };
1018 /* BDVER2 has optimized REP instruction for medium sized blocks, but for
1019 very small blocks it is better to use loop. For large blocks, libcall
1020 can do nontemporary accesses and beat inline considerably. */
1055 in QImode, HImode and SImode.
1056 Relative to reg-reg move (2). */
1060 in SFmode, DFmode and XFmode */
1062 in SFmode, DFmode and XFmode */
1065 in SImode and DImode */
1067 in SImode and DImode */
1070 in SImode, DImode and TImode */
1072 in SImode, DImode and TImode */
1074 /* On K8:
1075 MOVD reg64, xmmreg Double FSTORE 4
1076 MOVD reg32, xmmreg Double FSTORE 4
1077 On AMDFAM10:
1078 MOVD reg64, xmmreg Double FADD 3
1079 1/1 1/1
1080 MOVD reg32, xmmreg Double FADD 3
1081 1/1 1/1 */
1085 /* New AMD processors never drop prefetches; if they cannot be performed
1086 immediately, they are queued. We set number of simultaneous prefetches
1087 to a large constant to reflect this (it probably is not a good idea not
1088 to limit number of prefetches at all, as their execution also takes some
1089 time). */
1099 bdver2_memcpy,
1100 bdver2_memset,
1112 };
1115 /* BDVER3 has optimized REP instruction for medium sized blocks, but for
1116 very small blocks it is better to use loop. For large blocks, libcall
1117 can do nontemporary accesses and beat inline considerably. */
1150 in QImode, HImode and SImode.
1151 Relative to reg-reg move (2). */
1155 in SFmode, DFmode and XFmode */
1157 in SFmode, DFmode and XFmode */
1160 in SImode and DImode */
1162 in SImode and DImode */
1165 in SImode, DImode and TImode */
1167 in SImode, DImode and TImode */
1172 /* New AMD processors never drop prefetches; if they cannot be performed
1173 immediately, they are queued. We set number of simultaneous prefetches
1174 to a large constant to reflect this (it probably is not a good idea not
1175 to limit number of prefetches at all, as their execution also takes some
1176 time). */
1186 bdver3_memcpy,
1187 bdver3_memset,
1199 };
1201 /* BDVER4 has optimized REP instruction for medium sized blocks, but for
1202 very small blocks it is better to use loop. For large blocks, libcall
1203 can do nontemporary accesses and beat inline considerably. */
1236 in QImode, HImode and SImode.
1237 Relative to reg-reg move (2). */
1241 in SFmode, DFmode and XFmode */
1243 in SFmode, DFmode and XFmode */
1246 in SImode and DImode */
1248 in SImode and DImode */
1251 in SImode, DImode and TImode */
1253 in SImode, DImode and TImode */
1258 /* New AMD processors never drop prefetches; if they cannot be performed
1259 immediately, they are queued. We set number of simultaneous prefetches
1260 to a large constant to reflect this (it probably is not a good idea not
1261 to limit number of prefetches at all, as their execution also takes some
1262 time). */
1272 bdver4_memcpy,
1273 bdver4_memset,
1285 };
1287 /* BTVER1 has optimized REP instruction for medium sized blocks, but for
1288 very small blocks it is better to use loop. For large blocks, libcall can
1289 do nontemporary accesses and beat inline considerably. */
1322 in QImode, HImode and SImode.
1323 Relative to reg-reg move (2). */
1327 in SFmode, DFmode and XFmode */
1329 in SFmode, DFmode and XFmode */
1332 in SImode and DImode */
1334 in SImode and DImode */
1337 in SImode, DImode and TImode */
1339 in SImode, DImode and TImode */
1341 /* On K8:
1342 MOVD reg64, xmmreg Double FSTORE 4
1343 MOVD reg32, xmmreg Double FSTORE 4
1344 On AMDFAM10:
1345 MOVD reg64, xmmreg Double FADD 3
1346 1/1 1/1
1347 MOVD reg32, xmmreg Double FADD 3
1348 1/1 1/1 */
1361 btver1_memcpy,
1362 btver1_memset,
1374 };
1408 in QImode, HImode and SImode.
1409 Relative to reg-reg move (2). */
1413 in SFmode, DFmode and XFmode */
1415 in SFmode, DFmode and XFmode */
1418 in SImode and DImode */
1420 in SImode and DImode */
1423 in SImode, DImode and TImode */
1425 in SImode, DImode and TImode */
1427 /* On K8:
1428 MOVD reg64, xmmreg Double FSTORE 4
1429 MOVD reg32, xmmreg Double FSTORE 4
1430 On AMDFAM10:
1431 MOVD reg64, xmmreg Double FADD 3
1432 1/1 1/1
1433 MOVD reg32, xmmreg Double FADD 3
1434 1/1 1/1 */
1446 btver2_memcpy,
1447 btver2_memset,
1459 };
1463 DUMMY_STRINGOP_ALGS};
1467 DUMMY_STRINGOP_ALGS};
1469 static const
1492 in QImode, HImode and SImode.
1493 Relative to reg-reg move (2). */
1497 in SFmode, DFmode and XFmode */
1499 in SFmode, DFmode and XFmode */
1502 in SImode and DImode */
1504 in SImode and DImode */
1507 in SImode, DImode and TImode */
1509 in SImode, DImode and TImode */
1522 pentium4_memcpy,
1523 pentium4_memset,
1535 };
1548 static const
1571 in QImode, HImode and SImode.
1572 Relative to reg-reg move (2). */
1576 in SFmode, DFmode and XFmode */
1578 in SFmode, DFmode and XFmode */
1581 in SImode and DImode */
1583 in SImode and DImode */
1586 in SImode, DImode and TImode */
1588 in SImode, DImode and TImode */
1601 nocona_memcpy,
1602 nocona_memset,
1614 };
1625 static const
1648 in QImode, HImode and SImode.
1649 Relative to reg-reg move (2). */
1653 in SFmode, DFmode and XFmode */
1655 in SFmode, DFmode and XFmode */
1658 in SImode and DImode */
1660 in SImode and DImode */
1663 in SImode, DImode and TImode */
1665 in SImode, DImode and TImode */
1678 atom_memcpy,
1679 atom_memset,
1691 };
1702 static const
1725 in QImode, HImode and SImode.
1726 Relative to reg-reg move (2). */
1730 in SFmode, DFmode and XFmode */
1732 in SFmode, DFmode and XFmode */
1735 in SImode and DImode */
1737 in SImode and DImode */
1740 in SImode, DImode and TImode */
1742 in SImode, DImode and TImode */
1755 slm_memcpy,
1756 slm_memset,
1768 };
1779 static const
1802 in QImode, HImode and SImode.
1803 Relative to reg-reg move (2). */
1807 in SFmode, DFmode and XFmode */
1809 in SFmode, DFmode and XFmode */
1812 in SImode and DImode */
1814 in SImode and DImode */
1817 in SImode, DImode and TImode */
1819 in SImode, DImode and TImode */
1832 intel_memcpy,
1833 intel_memset,
1845 };
1847 /* Generic should produce code tuned for Core-i7 (and newer chips)
1848 and btver1 (and newer chips). */
1860 static const
1863 /* On all chips taken into consideration lea is 2 cycles and more. With
1864 this cost however our current implementation of synth_mult results in
1865 use of unnecessary temporary registers causing regression on several
1866 SPECfp benchmarks. */
1887 in QImode, HImode and SImode.
1888 Relative to reg-reg move (2). */
1892 in SFmode, DFmode and XFmode */
1894 in SFmode, DFmode and XFmode */
1897 in SImode and DImode */
1899 in SImode and DImode */
1902 in SImode, DImode and TImode */
1904 in SImode, DImode and TImode */
1910 /* Benchmarks shows large regressions on K8 sixtrack benchmark when this
1911 value is increased to perhaps more appropriate value of 5. */
1919 generic_memcpy,
1920 generic_memset,
1932 };
1934 /* core_cost should produce code tuned for Core familly of CPUs. */
1947 static const
1950 /* On all chips taken into consideration lea is 2 cycles and more. With
1951 this cost however our current implementation of synth_mult results in
1952 use of unnecessary temporary registers causing regression on several
1953 SPECfp benchmarks. */
1974 in QImode, HImode and SImode.
1975 Relative to reg-reg move (2). */
1979 in SFmode, DFmode and XFmode */
1981 in SFmode, DFmode and XFmode */
1984 in SImode and DImode */
1986 in SImode and DImode */
1989 in SImode, DImode and TImode */
1991 in SImode, DImode and TImode */
1997 /* FIXME perhaps more appropriate value is 5. */
2005 core_memcpy,
2006 core_memset,
2018 };
2021 /* Set by -mtune. */
2024 /* Set by -mtune or -Os. */
2027 /* Processor feature/optimization bitmasks. */
2028 #define m_386 (1<<PROCESSOR_I386)
2029 #define m_486 (1<<PROCESSOR_I486)
2030 #define m_PENT (1<<PROCESSOR_PENTIUM)
2031 #define m_PPRO (1<<PROCESSOR_PENTIUMPRO)
2032 #define m_PENT4 (1<<PROCESSOR_PENTIUM4)
2033 #define m_NOCONA (1<<PROCESSOR_NOCONA)
2034 #define m_P4_NOCONA (m_PENT4 | m_NOCONA)
2035 #define m_CORE2 (1<<PROCESSOR_CORE2)
2036 #define m_NEHALEM (1<<PROCESSOR_NEHALEM)
2037 #define m_SANDYBRIDGE (1<<PROCESSOR_SANDYBRIDGE)
2038 #define m_HASWELL (1<<PROCESSOR_HASWELL)
2039 #define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_HASWELL)
2040 #define m_BONNELL (1<<PROCESSOR_BONNELL)
2041 #define m_SILVERMONT (1<<PROCESSOR_SILVERMONT)
2042 #define m_KNL (1<<PROCESSOR_KNL)
2043 #define m_INTEL (1<<PROCESSOR_INTEL)
2045 #define m_GEODE (1<<PROCESSOR_GEODE)
2046 #define m_K6 (1<<PROCESSOR_K6)
2047 #define m_K6_GEODE (m_K6 | m_GEODE)
2048 #define m_K8 (1<<PROCESSOR_K8)
2049 #define m_ATHLON (1<<PROCESSOR_ATHLON)
2050 #define m_ATHLON_K8 (m_K8 | m_ATHLON)
2051 #define m_AMDFAM10 (1<<PROCESSOR_AMDFAM10)
2052 #define m_BDVER1 (1<<PROCESSOR_BDVER1)
2053 #define m_BDVER2 (1<<PROCESSOR_BDVER2)
2054 #define m_BDVER3 (1<<PROCESSOR_BDVER3)
2055 #define m_BDVER4 (1<<PROCESSOR_BDVER4)
2056 #define m_BTVER1 (1<<PROCESSOR_BTVER1)
2057 #define m_BTVER2 (1<<PROCESSOR_BTVER2)
2058 #define m_BDVER (m_BDVER1 | m_BDVER2 | m_BDVER3 | m_BDVER4)
2059 #define m_BTVER (m_BTVER1 | m_BTVER2)
2060 #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
2062 #define m_GENERIC (1<<PROCESSOR_GENERIC)
2065 #undef DEF_TUNE
2066 #define DEF_TUNE(tune, name, selector) name,
2068 #undef DEF_TUNE
2069 };
2071 /* Feature tests against the various tunings. */
2074 /* Feature tests against the various tunings used to create ix86_tune_features
2075 based on the processor mask. */
2077 #undef DEF_TUNE
2078 #define DEF_TUNE(tune, name, selector) selector,
2080 #undef DEF_TUNE
2081 };
2083 /* Feature tests against the various architecture variations. */
2086 /* Feature tests against the various architecture variations, used to create
2087 ix86_arch_features based on the processor mask. */
2089 /* X86_ARCH_CMOV: Conditional move was added for pentiumpro. */
2092 /* X86_ARCH_CMPXCHG: Compare and exchange was added for 80486. */
2095 /* X86_ARCH_CMPXCHG8B: Compare and exchange 8 bytes was added for pentium. */
2098 /* X86_ARCH_XADD: Exchange and add was added for 80486. */
2101 /* X86_ARCH_BSWAP: Byteswap was added for 80486. */
2103 };
2105 /* In case the average insn count for single function invocation is
2106 lower than this constant, emit fast (but longer) prologue and
2107 epilogue code. */
2108 #define FAST_PROLOGUE_INSN_COUNT 20
2110 /* Names for 8 (low), 8 (high), and 16-bit registers, respectively. */
2115 /* Array of the smallest class containing reg number REGNO, indexed by
2116 REGNO. Used by REGNO_REG_CLASS in i386.h. */
2119 {
2120 /* ax, dx, cx, bx */
2122 /* si, di, bp, sp */
2124 /* FP registers */
2127 /* arg pointer */
2128 NON_Q_REGS,
2129 /* flags, fpsr, fpcr, frame */
2131 /* SSE registers */
2134 /* MMX registers */
2137 /* REX registers */
2140 /* SSE REX registers */
2143 /* AVX-512 SSE registers */
2148 /* Mask registers. */
2151 /* MPX bound registers */
2153 };
2155 /* The "default" register map used in 32bit mode. */
2158 {
2170 };
2172 /* The "default" register map used in 64bit mode. */
2175 {
2187 };
2189 /* Define the register numbers to be used in Dwarf debugging information.
2190 The SVR4 reference port C compiler uses the following register numbers
2191 in its Dwarf output code:
2192 0 for %eax (gcc regno = 0)
2193 1 for %ecx (gcc regno = 2)
2194 2 for %edx (gcc regno = 1)
2195 3 for %ebx (gcc regno = 3)
2196 4 for %esp (gcc regno = 7)
2197 5 for %ebp (gcc regno = 6)
2198 6 for %esi (gcc regno = 4)
2199 7 for %edi (gcc regno = 5)
2200 The following three DWARF register numbers are never generated by
2201 the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4
2202 believes these numbers have these meanings.
2203 8 for %eip (no gcc equivalent)
2204 9 for %eflags (gcc regno = 17)
2205 10 for %trapno (no gcc equivalent)
2206 It is not at all clear how we should number the FP stack registers
2207 for the x86 architecture. If the version of SDB on x86/svr4 were
2208 a bit less brain dead with respect to floating-point then we would
2209 have a precedent to follow with respect to DWARF register numbers
2210 for x86 FP registers, but the SDB on x86/svr4 is so completely
2211 broken with respect to FP registers that it is hardly worth thinking
2212 of it as something to strive for compatibility with.
2213 The version of x86/svr4 SDB I have at the moment does (partially)
2214 seem to believe that DWARF register number 11 is associated with
2215 the x86 register %st(0), but that's about all. Higher DWARF
2216 register numbers don't seem to be associated with anything in
2217 particular, and even for DWARF regno 11, SDB only seems to under-
2218 stand that it should say that a variable lives in %st(0) (when
2219 asked via an `=' command) if we said it was in DWARF regno 11,
2220 but SDB still prints garbage when asked for the value of the
2221 variable in question (via a `/' command).
2222 (Also note that the labels SDB prints for various FP stack regs
2223 when doing an `x' command are all wrong.)
2224 Note that these problems generally don't affect the native SVR4
2225 C compiler because it doesn't allow the use of -O with -g and
2226 because when it is *not* optimizing, it allocates a memory
2227 location for each floating-point variable, and the memory
2228 location is what gets described in the DWARF AT_location
2229 attribute for the variable in question.
2230 Regardless of the severe mental illness of the x86/svr4 SDB, we
2231 do something sensible here and we use the following DWARF
2232 register numbers. Note that these are all stack-top-relative
2233 numbers.
2234 11 for %st(0) (gcc regno = 8)
2235 12 for %st(1) (gcc regno = 9)
2236 13 for %st(2) (gcc regno = 10)
2237 14 for %st(3) (gcc regno = 11)
2238 15 for %st(4) (gcc regno = 12)
2239 16 for %st(5) (gcc regno = 13)
2240 17 for %st(6) (gcc regno = 14)
2241 18 for %st(7) (gcc regno = 15)
2242 */
2244 {
2256 };
2258 /* Define parameter passing and return registers. */
2261 {
2263 };
2266 {
2268 };
2271 {
2273 };
2275 /* Additional registers that are clobbered by SYSV calls. */
2278 {
2283 };
2285 /* Define the structure for the machine field in struct function. */
2290 rtx rtl;
2292 };
2294 /* Structure describing stack frame layout.
2295 Stack grows downward:
2297 [arguments]
2298 <- ARG_POINTER
2299 saved pc
2301 saved static chain if ix86_static_chain_on_stack
2303 saved frame pointer if frame_pointer_needed
2304 <- HARD_FRAME_POINTER
2305 [saved regs]
2306 <- regs_save_offset
2307 [padding0]
2309 [saved SSE regs]
2310 <- sse_regs_save_offset
2311 [padding1] |
2312 | <- FRAME_POINTER
2313 [va_arg registers] |
2314 |
2315 [frame] |
2316 |
2317 [padding2] | = to_allocate
2318 <- STACK_POINTER
2319 */
2320 struct ix86_frame
2321 {
2328 /* The offsets relative to ARG_POINTER. */
2329 HOST_WIDE_INT frame_pointer_offset;
2330 HOST_WIDE_INT hard_frame_pointer_offset;
2331 HOST_WIDE_INT stack_pointer_offset;
2332 HOST_WIDE_INT hfp_save_offset;
2333 HOST_WIDE_INT reg_save_offset;
2334 HOST_WIDE_INT sse_reg_save_offset;
2336 /* When save_regs_using_mov is set, emit prologue using
2337 move instead of push instructions. */
2339 };
2341 /* Which cpu are we scheduling for. */
2344 /* Which cpu are we optimizing for. */
2347 /* Which instruction set architecture to use. */
2350 /* True if processor has SSE prefetch instruction. */
2353 /* -mstackrealign option */
2371 /* Preferred alignment for stack boundary in bits. */
2374 /* Alignment for incoming stack boundary in bits specified at
2375 command line. */
2378 /* Default alignment for incoming stack boundary in bits. */
2381 /* Alignment for incoming stack boundary in bits. */
2384 /* Calling abi specific va_list type nodes. */
2388 /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */
2392 /* Fence to use after loop using movnt. */
2393 tree x86_mfence;
2395 /* Register class used for passing given 64bit part of the argument.
2396 These represent classes as documented by the PS ABI, with the exception
2397 of SSESF, SSEDF classes, that are basically SSE class, just gcc will
2398 use SF or DFmode move instead of DImode to avoid reformatting penalties.
2400 Similarly we play games with INTEGERSI_CLASS to use cheaper SImode moves
2401 whenever possible (upper half does contain padding). */
2402 enum x86_64_reg_class
2403 {
2404 X86_64_NO_CLASS,
2405 X86_64_INTEGER_CLASS,
2406 X86_64_INTEGERSI_CLASS,
2407 X86_64_SSE_CLASS,
2408 X86_64_SSESF_CLASS,
2409 X86_64_SSEDF_CLASS,
2410 X86_64_SSEUP_CLASS,
2411 X86_64_X87_CLASS,
2412 X86_64_X87UP_CLASS,
2413 X86_64_COMPLEX_X87_CLASS,
2414 X86_64_MEMORY_CLASS
2415 };
2417 #define MAX_CLASSES 8
2419 /* Table of constants used by fldpi, fldln2, etc.... */
2423 \f
2428 const_tree);
2440 enum ix86_function_specific_strings
2441 {
2442 IX86_FUNCTION_SPECIFIC_ARCH,
2443 IX86_FUNCTION_SPECIFIC_TUNE,
2444 IX86_FUNCTION_SPECIFIC_MAX
2445 };
2467 \f
2468 #ifndef SUBTARGET32_DEFAULT_CPU
2470 #endif
2472 /* Whether -mtune= or -march= were specified */
2476 /* Vectorization library interface and handlers. */
2482 /* Processor target table, indexed by processor number */
2483 struct ptt
2484 {
2492 };
2494 /* This table must be in sync with enum processor_type in i386.h. */
2496 {
2523 };
2524 \f
2525 static unsigned int
2527 {
2530 /* vzeroupper instructions are inserted immediately after reload to
2531 account for possible spills from 256bit registers. The pass
2532 reuses mode switching infrastructure by re-running mode insertion
2533 pass, so disable entities that have already been processed. */
2539 /* Call optimize_mode_switching. */
2542 }
2547 {
2557 };
2560 {
2564 {}
2566 /* opt_pass methods: */
2568 {
2572 }
2575 {
2577 }
2583 rtl_opt_pass *
2585 {
2587 }
2589 /* Return true if a red-zone is in use. */
2593 {
2595 }
2596 \f
2597 /* Return a string that documents the current -m options. The caller is
2598 responsible for freeing the string. */
2604 {
2605 struct ix86_target_opts
2606 {
2609 };
2611 /* This table is ordered so that options like -msse4.2 that imply
2612 preceding options while match those first. */
2614 {
2668 };
2670 /* Flag options. */
2672 {
2701 };
2718 /* Add -march= option. */
2720 {
2723 }
2725 /* Add -mtune= option. */
2727 {
2730 }
2732 /* Add -m32/-m64/-mx32. */
2734 {
2737 else
2739 isa &= ~ (OPTION_MASK_ISA_64BIT
2740 | OPTION_MASK_ABI_64
2742 }
2743 else
2747 /* Pick out the options in isa options. */
2749 {
2751 {
2754 }
2755 }
2758 {
2761 isa);
2762 }
2764 /* Add flag options. */
2766 {
2768 {
2771 }
2772 }
2775 {
2778 }
2780 /* Add -fpmath= option. */
2782 {
2785 {
2800 }
2801 }
2803 /* Any options? */
2809 /* Size the string. */
2813 {
2818 }
2820 /* Build the string. */
2825 {
2832 {
2834 line_len++;
2837 {
2841 }
2842 }
2846 {
2850 }
2851 }
2857 }
2859 /* Return true, if profiling code should be emitted before
2860 prologue. Otherwise it returns false.
2861 Note: For x86 with "hotfix" it is sorried. */
2862 static bool
2864 {
2866 }
2868 /* Function that is callable from the debugger to print the current
2869 options. */
2870 void ATTRIBUTE_UNUSED
2872 {
2878 {
2881 }
2882 else
2886 }
2889 #define DEF_ENUM
2890 #define DEF_ALG(alg, name) #name,
2892 #undef DEF_ENUM
2893 #undef DEF_ALG
2894 };
2896 /* Parse parameter string passed to -mmemcpy-strategy= or -mmemset-strategy=.
2897 The string is of the following form (or comma separated list of it):
2899 strategy_alg:max_size:[align|noalign]
2901 where the full size range for the strategy is either [0, max_size] or
2902 [min_size, max_size], in which min_size is the max_size + 1 of the
2903 preceding range. The last size range must have max_size == -1.
2905 Examples:
2907 1.
2908 -mmemcpy-strategy=libcall:-1:noalign
2910 this is equivalent to (for known size memcpy) -mstringop-strategy=libcall
2913 2.
2914 -mmemset-strategy=rep_8byte:16:noalign,vector_loop:2048:align,libcall:-1:noalign
2916 This is to tell the compiler to use the following strategy for memset
2917 1) when the expected size is between [1, 16], use rep_8byte strategy;
2918 2) when the size is between [17, 2048], use vector_loop;
2919 3) when the size is > 2048, use libcall. */
2921 struct stringop_size_range
2922 {
2924 stringop_alg alg;
2926 };
2928 static void
2930 {
2938 else
2943 do
2944 {
2954 {
2958 }
2961 {
2965 }
2972 {
2974 alg_name,
2977 }
2981 {
2982 /* rep; movq isn't available in 32-bit code. */
2985 alg_name,
2988 }
2996 else
2997 {
3001 }
3002 n++;
3004 }
3008 {
3013 }
3016 {
3020 }
3022 /* Now override the default algs array. */
3024 {
3030 }
3031 }
3033 \f
3034 /* parse -mtune-ctrl= option. When DUMP is true,
3035 print the features that are explicitly set. */
3037 static void
3039 {
3047 do
3048 {
3055 {
3056 curr_feature_string++;
3058 }
3060 {
3062 {
3068 }
3069 }
3074 }
3077 }
3079 /* Helper function to set ix86_tune_features. IX86_TUNE is the
3080 processor type. */
3082 static void
3084 {
3089 {
3092 else
3094 }
3097 {
3102 }
3105 }
3108 /* Default align_* from the processor table. */
3110 static void
3112 {
3114 {
3117 }
3119 {
3122 }
3124 {
3126 }
3127 }
3129 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE hook. */
3131 static void
3133 {
3135 }
3137 /* Override various settings based on options. If MAIN_ARGS_P, the
3138 options are from the command line, otherwise they are from
3139 attributes. */
3141 static void
3145 {
3153 #define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
3154 #define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
3155 #define PTA_64BIT (HOST_WIDE_INT_1 << 2)
3156 #define PTA_ABM (HOST_WIDE_INT_1 << 3)
3157 #define PTA_AES (HOST_WIDE_INT_1 << 4)
3158 #define PTA_AVX (HOST_WIDE_INT_1 << 5)
3159 #define PTA_BMI (HOST_WIDE_INT_1 << 6)
3160 #define PTA_CX16 (HOST_WIDE_INT_1 << 7)
3161 #define PTA_F16C (HOST_WIDE_INT_1 << 8)
3162 #define PTA_FMA (HOST_WIDE_INT_1 << 9)
3163 #define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
3164 #define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
3165 #define PTA_LWP (HOST_WIDE_INT_1 << 12)
3166 #define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
3167 #define PTA_MMX (HOST_WIDE_INT_1 << 14)
3168 #define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
3169 #define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
3170 #define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
3171 #define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
3172 #define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
3173 #define PTA_RDRND (HOST_WIDE_INT_1 << 20)
3174 #define PTA_SSE (HOST_WIDE_INT_1 << 21)
3175 #define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
3176 #define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
3177 #define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
3178 #define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
3179 #define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
3180 #define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
3181 #define PTA_TBM (HOST_WIDE_INT_1 << 28)
3182 #define PTA_XOP (HOST_WIDE_INT_1 << 29)
3183 #define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
3184 #define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
3185 #define PTA_RTM (HOST_WIDE_INT_1 << 32)
3186 #define PTA_HLE (HOST_WIDE_INT_1 << 33)
3187 #define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
3188 #define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
3189 #define PTA_ADX (HOST_WIDE_INT_1 << 36)
3190 #define PTA_FXSR (HOST_WIDE_INT_1 << 37)
3191 #define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
3192 #define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
3193 #define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
3194 #define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
3195 #define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
3196 #define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
3197 #define PTA_MPX (HOST_WIDE_INT_1 << 44)
3198 #define PTA_SHA (HOST_WIDE_INT_1 << 45)
3199 #define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
3200 #define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
3201 #define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
3202 #define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
3203 #define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
3204 #define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
3205 #define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
3206 #define PTA_AVX512IFMA (HOST_WIDE_INT_1 << 53)
3207 #define PTA_AVX512VBMI (HOST_WIDE_INT_1 << 54)
3208 #define PTA_CLWB (HOST_WIDE_INT_1 << 55)
3209 #define PTA_PCOMMIT (HOST_WIDE_INT_1 << 56)
3210 #define PTA_MWAITX (HOST_WIDE_INT_1 << 57)
3212 #define PTA_CORE2 \
3213 (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
3214 | PTA_CX16 | PTA_FXSR)
3215 #define PTA_NEHALEM \
3216 (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
3217 #define PTA_WESTMERE \
3218 (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
3219 #define PTA_SANDYBRIDGE \
3220 (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
3221 #define PTA_IVYBRIDGE \
3222 (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
3223 #define PTA_HASWELL \
3224 (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
3225 | PTA_FMA | PTA_MOVBE | PTA_HLE)
3226 #define PTA_BROADWELL \
3227 (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
3228 #define PTA_KNL \
3229 (PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
3230 #define PTA_BONNELL \
3231 (PTA_CORE2 | PTA_MOVBE)
3232 #define PTA_SILVERMONT \
3233 (PTA_WESTMERE | PTA_MOVBE)
3235 /* if this reaches 64, need to widen struct pta flags below */
3237 static struct pta
3238 {
3243 }
3245 {
3279 PTA_SANDYBRIDGE},
3281 PTA_SANDYBRIDGE},
3283 PTA_IVYBRIDGE},
3285 PTA_IVYBRIDGE},
3377 PTA_64BIT
3379 };
3381 /* -mrecip options. */
3382 static struct
3383 {
3386 }
3388 {
3395 };
3399 /* Set up prefix/suffix so the error messages refer to either the command
3400 line argument, or the attribute(target). */
3402 {
3406 }
3407 else
3408 {
3412 }
3414 /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if
3415 TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */
3418 #ifdef TARGET_BI_ARCH
3419 else
3420 {
3421 #if TARGET_BI_ARCH == 1
3422 /* When TARGET_BI_ARCH == 1, by default, OPTION_MASK_ABI_64
3423 is on and OPTION_MASK_ABI_X32 is off. We turn off
3424 OPTION_MASK_ABI_64 if OPTION_MASK_ABI_X32 is turned on by
3425 -mx32. */
3428 #else
3429 /* When TARGET_BI_ARCH == 2, by default, OPTION_MASK_ABI_X32 is
3430 on and OPTION_MASK_ABI_64 is off. We turn off
3431 OPTION_MASK_ABI_X32 if OPTION_MASK_ABI_64 is turned on by
3432 -m64 or OPTION_MASK_CODE16 is turned on by -m16. */
3436 #endif
3437 }
3438 #endif
3441 {
3442 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3443 OPTION_MASK_ABI_64 for TARGET_X32. */
3446 }
3449 | OPTION_MASK_ABI_X32
3452 {
3453 /* Always turn on OPTION_MASK_ISA_64BIT and turn off
3454 OPTION_MASK_ABI_X32 for TARGET_LP64. */
3457 }
3459 #ifdef SUBTARGET_OVERRIDE_OPTIONS
3460 SUBTARGET_OVERRIDE_OPTIONS;
3461 #endif
3463 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
3464 SUBSUBTARGET_OVERRIDE_OPTIONS;
3465 #endif
3467 /* -fPIC is the default for x86_64. */
3471 /* Need to check -mtune=generic first. */
3473 {
3474 /* As special support for cross compilers we read -mtune=native
3475 as -mtune=generic. With native compilers we won't see the
3476 -mtune=native, as it was changed by the driver. */
3478 {
3480 }
3485 }
3486 else
3487 {
3491 {
3492 opts->x_ix86_tune_string
3495 }
3497 /* opts->x_ix86_tune_string is set to opts->x_ix86_arch_string
3498 or defaulted. We need to use a sensible tune option. */
3500 {
3502 }
3503 }
3507 {
3508 /* rep; movq isn't available in 32-bit code. */
3511 }
3514 opts->x_ix86_arch_string
3517 else
3521 {
3529 }
3530 else
3537 /* For targets using ms ABI enable ms-extensions, if not
3538 explicit turned off. For non-ms ABI we turn off this
3539 option. */
3544 {
3546 {
3590 {
3593 }
3601 }
3602 }
3603 else
3604 {
3605 /* For TARGET_64BIT and MS_ABI, force pic on, in order to enable the
3606 use of rip-relative addressing. This eliminates fixups that
3607 would otherwise be needed if this object is to be placed in a
3608 DLL, and is essentially just as efficient as direct addressing. */
3614 else
3616 }
3618 {
3621 }
3629 {
3632 /* Default cpu tuning to the architecture. */
3813 }
3837 {
3841 {
3843 {
3845 {
3853 }
3854 else
3857 }
3858 }
3859 /* Intel CPUs have always interpreted SSE prefetch instructions as
3860 NOPs; so, we can enable SSE prefetch instructions even when
3861 -mtune (rather than -march) points us to a processor that has them.
3862 However, the VIA C3 gives a SIGILL, so we only do that for i686 and
3863 higher processors. */
3868 }
3876 #ifndef USE_IX86_FRAME_POINTER
3877 #define USE_IX86_FRAME_POINTER 0
3878 #endif
3880 #ifndef USE_X86_64_FRAME_POINTER
3881 #define USE_X86_64_FRAME_POINTER 0
3882 #endif
3884 /* Set the default values for switches whose default depends on TARGET_64BIT
3885 in case they weren't overwritten by command line options. */
3887 {
3895 opts->x_flag_unwind_tables
3899 }
3900 else
3901 {
3903 opts->x_flag_omit_frame_pointer
3909 }
3912 /* TODO: ix86_cost should be chosen at instruction or function granuality
3913 so for cold code we use size_cost even in !optimize_size compilation. */
3916 else
3919 /* Arrange to set up i386_stack_locals for all functions. */
3922 /* Validate -mregparm= value. */
3924 {
3928 {
3932 }
3933 }
3937 /* Default align_* from the processor table. */
3940 /* Provide default for -mbranch-cost= value. */
3945 {
3946 opts->x_target_flags
3949 /* Enable by default the SSE and MMX builtins. Do allow the user to
3950 explicitly disable any of these. In particular, disabling SSE and
3951 MMX for kernel code is extremely useful. */
3953 opts->x_ix86_isa_flags
3960 }
3961 else
3962 {
3963 opts->x_target_flags
3967 opts->x_ix86_isa_flags
3970 /* i386 ABI does not specify red zone. It still makes sense to use it
3971 when programmer takes care to stack from being destroyed. */
3974 }
3976 /* Keep nonleaf frame pointers. */
3982 /* If we're doing fast math, we don't care about comparison order
3983 wrt NaNs. This lets us use a shorter comparison sequence. */
3987 /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387,
3988 since the insns won't need emulation. */
3992 /* Likewise, if the target doesn't have a 387, or we've specified
3993 software floating point, don't use 387 inline intrinsics. */
3997 /* Turn on MMX builtins for -msse. */
3999 opts->x_ix86_isa_flags
4002 /* Enable SSE prefetch. */
4007 /* Enable prefetch{,w} instructions for -m3dnow and -mprefetchwt1. */
4010 opts->x_ix86_isa_flags
4013 /* Enable popcnt instruction for -msse4.2 or -mabm. */
4016 opts->x_ix86_isa_flags
4019 /* Enable lzcnt instruction for -mabm. */
4021 opts->x_ix86_isa_flags
4024 /* Validate -mpreferred-stack-boundary= value or default it to
4025 PREFERRED_STACK_BOUNDARY_DEFAULT. */
4028 {
4035 {
4039 else
4042 }
4043 else
4044 ix86_preferred_stack_boundary
4046 }
4048 /* Set the default value for -mstackrealign. */
4054 /* Validate -mincoming-stack-boundary= value or default it to
4055 MIN_STACK_BOUNDARY/PREFERRED_STACK_BOUNDARY. */
4058 {
4065 else
4066 {
4067 ix86_user_incoming_stack_boundary
4069 ix86_incoming_stack_boundary
4071 }
4072 }
4074 #ifndef NO_PROFILE_COUNTERS
4077 #endif
4081 /* Accept -msseregparm only if at least SSE support is enabled. */
4087 {
4089 {
4091 {
4094 }
4097 {
4100 }
4101 }
4102 }
4103 /* For all chips supporting SSE2, -mfpmath=sse performs better than
4104 fpmath=387. The second is however default at many targets since the
4105 extra 80bit precision of temporaries is considered to be part of ABI.
4106 Overwrite the default at least for -ffast-math.
4107 TODO: -mfpmath=both seems to produce same performing code with bit
4108 smaller binaries. It is however not clear if register allocation is
4109 ready for this setting.
4110 Also -mfpmath=387 is overall a lot more compact (bout 4-5%) than SSE
4111 codegen. We may switch to 387 with -ffast-math for size optimized
4112 functions. */
4116 else
4119 /* If the i387 is disabled, then do not return values in it. */
4123 /* Use external vectorized library in vectorizing intrinsics. */
4126 {
4137 }
4143 /* If stack probes are required, the space used for large function
4144 arguments on the stack must also be probed, so enable
4145 -maccumulate-outgoing-args so this happens in the prologue. */
4148 {
4153 }
4155 /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */
4156 {
4162 }
4164 /* When scheduling description is not available, disable scheduler pass
4165 so it won't slow down the compilation and make x87 code slower. */
4186 /* Enable sw prefetching at -O3 for CPUS that prefetching is helpful. */
4188 && HAVE_prefetch
4194 /* If using typedef char *va_list, signal that __builtin_va_start (&ap, 0)
4195 can be opts->x_optimized to ap = __builtin_next_arg (0). */
4200 {
4203 {
4205 ix86_gen_tls_local_dynamic_base_64
4207 }
4208 else
4209 {
4211 ix86_gen_tls_local_dynamic_base_64
4213 }
4214 }
4215 else
4219 {
4230 }
4231 else
4232 {
4243 }
4245 #ifdef USE_IX86_CLD
4246 /* Use -mcld by default for 32-bit code if configured with --enable-cld. */
4249 #endif
4252 {
4257 }
4259 {
4263 }
4265 {
4266 #if defined(PROFILE_BEFORE_PROLOGUE)
4268 #else
4270 #endif
4271 }
4281 /* Enable 128-bit AVX instruction generation
4282 for the auto-vectorizer. */
4288 {
4295 {
4298 {
4300 q++;
4301 }
4302 else
4307 else
4308 {
4311 {
4314 }
4317 {
4321 }
4322 }
4327 else
4329 }
4330 }
4337 /* Default long double to 64-bit for 32-bit Bionic and to __float128
4338 for 64-bit Bionic. */
4343 ? MASK_LONG_DOUBLE_128
4346 /* Only one of them can be active. */
4350 /* Save the initial options in case the user does function specific
4351 options. */
4353 target_option_default_node = target_option_current_node
4356 /* Handle stack protector */
4358 opts->x_ix86_stack_protector_guard
4361 /* Handle -mmemcpy-strategy= and -mmemset-strategy= */
4363 {
4367 }
4370 {
4374 }
4375 }
4377 /* Implement the TARGET_OPTION_OVERRIDE hook. */
4379 static void
4381 {
4383 struct register_pass_info insert_vzeroupper_info
4386 };
4391 /* This needs to be done at start up. It's convenient to do it here. */
4393 }
4395 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
4398 {
4402 }
4404 /* Update register usage after having seen the compiler flags. */
4406 static void
4408 {
4411 /* For 32-bit targets, squash the REX registers. */
4413 {
4420 }
4422 /* See the definition of CALL_USED_REGISTERS in i386.h. */
4430 {
4431 /* Set/reset conditionally defined registers from
4432 CALL_USED_REGISTERS initializer. */
4436 /* Calculate registers of CLOBBERED_REGS register set
4437 as call used registers from GENERAL_REGS register set. */
4441 }
4443 /* If MMX is disabled, squash the registers. */
4449 /* If SSE is disabled, squash the registers. */
4455 /* If the FPU is disabled, squash the registers. */
4461 /* If AVX512F is disabled, squash the registers. */
4463 {
4469 }
4471 /* If MPX is disabled, squash the registers. */
4475 }
4477 \f
4478 /* Save the current options */
4480 static void
4483 {
4519 /* The fields are char but the variables are not; make sure the
4520 values fit in the fields. */
4525 }
4527 /* Restore the current options */
4529 static void
4532 {
4538 /* We don't change -fPIC. */
4576 /* TODO: ix86_cost should be chosen at instruction or function granuality
4577 so for cold code we use size_cost even in !optimize_size compilation. */
4580 else
4583 /* Recreate the arch feature tests if the arch changed */
4585 {
4590 }
4592 /* Recreate the tune optimization tests */
4595 }
4597 /* Adjust target options after streaming them in. This is mainly about
4598 reconciling them with global options. */
4600 static void
4602 {
4603 /* flag_pic is a global option, but ix86_cmodel is target saved option
4604 partly computed from flag_pic. If flag_pic is on, adjust x_ix86_cmodel
4605 for PIC, or error out. */
4608 {
4627 }
4628 else
4630 {
4645 }
4646 }
4648 /* Print the current options */
4650 static void
4653 {
4671 {
4674 }
4675 }
4677 \f
4678 /* Inner function to process the attribute((target(...))), take an argument and
4679 set the current options from the argument. If we have a list, recursively go
4680 over the list. */
4682 static bool
4687 {
4691 #define IX86_ATTR_ISA(S,O) { S, sizeof (S)-1, ix86_opt_isa, O, 0 }
4692 #define IX86_ATTR_STR(S,O) { S, sizeof (S)-1, ix86_opt_str, O, 0 }
4693 #define IX86_ATTR_ENUM(S,O) { S, sizeof (S)-1, ix86_opt_enum, O, 0 }
4694 #define IX86_ATTR_YES(S,O,M) { S, sizeof (S)-1, ix86_opt_yes, O, M }
4695 #define IX86_ATTR_NO(S,O,M) { S, sizeof (S)-1, ix86_opt_no, O, M }
4697 enum ix86_opt_type
4698 {
4699 ix86_opt_unknown,
4700 ix86_opt_yes,
4701 ix86_opt_no,
4702 ix86_opt_str,
4703 ix86_opt_enum,
4704 ix86_opt_isa
4705 };
4707 static const struct
4708 {
4715 /* isa options */
4769 /* enum options */
4772 /* string options */
4776 /* flag options */
4778 OPT_mcld,
4779 MASK_CLD),
4782 OPT_mfancy_math_387,
4783 MASK_NO_FANCY_MATH_387),
4786 OPT_mieee_fp,
4787 MASK_IEEE_FP),
4790 OPT_minline_all_stringops,
4791 MASK_INLINE_ALL_STRINGOPS),
4794 OPT_minline_stringops_dynamically,
4795 MASK_INLINE_STRINGOPS_DYNAMICALLY),
4798 OPT_mno_align_stringops,
4799 MASK_NO_ALIGN_STRINGOPS),
4802 OPT_mrecip,
4803 MASK_RECIP),
4805 };
4807 /* If this is a list, recurse to get the options. */
4809 {
4816 enum_opts_set))
4820 }
4823 {
4826 }
4828 /* Handle multiple arguments separated by commas. */
4832 {
4846 {
4850 }
4851 else
4852 {
4855 }
4857 /* Recognize no-xxx. */
4859 {
4863 }
4864 else
4867 /* Find the option. */
4871 {
4879 {
4884 }
4885 }
4887 /* Process the option. */
4889 {
4892 }
4895 {
4901 }
4904 {
4910 else
4912 }
4915 {
4917 {
4920 }
4921 else
4923 }
4926 {
4934 global_dc);
4935 else
4936 {
4939 }
4940 }
4942 else
4944 }
4947 }
4949 /* Return a TARGET_OPTION_NODE tree of the target options listed or NULL. */
4951 tree
4955 {
4970 /* Process each of the options on the chain. */
4975 /* If the changed options are different from the default, rerun
4976 ix86_option_override_internal, and then save the options away.
4977 The string options are are attribute options, and will be undone
4978 when we copy the save structure. */
4984 {
4985 /* If we are using the default tune= or arch=, undo the string assigned,
4986 and use the default. */
4997 /* If fpmath= is not set, and we now have sse2 on 32-bit, use it. */
5002 {
5005 }
5007 /* Do any overrides, such as arch=xxx, or tune=xxx support. */
5010 /* Add any builtin functions with the new isa if any. */
5013 /* Save the current options unless we are validating options for
5014 #pragma. */
5021 /* Free up memory allocated to hold the strings */
5024 }
5027 }
5029 /* Hook to validate attribute((target("string"))). */
5031 static bool
5034 tree args,
5036 {
5041 /* attribute((target("default"))) does nothing, beyond
5042 affecting multi-versioning. */
5051 /* Get the optimization options of the current function. */
5057 /* Init func_options. */
5065 /* Initialize func_options to the default before its target options can
5066 be set. */
5079 {
5084 }
5087 }
5089 \f
5090 /* Hook to determine if one function can safely inline another. */
5092 static bool
5094 {
5099 /* If callee has no option attributes, then it is ok to inline. */
5103 /* If caller has no option attributes, but callee does then it is not ok to
5104 inline. */
5108 else
5109 {
5113 /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
5114 can inline a SSE2 function but a SSE2 function can't inline a SSE4
5115 function. */
5120 /* See if we have the same non-isa options. */
5124 /* See if arch, tune, etc. are the same. */
5137 else
5139 }
5142 }
5144 \f
5145 /* Remember the last target of ix86_set_current_function. */
5148 /* Set targets globals to the default (or current #pragma GCC target
5149 if active). Invalidate ix86_previous_fndecl cache. */
5151 void
5153 {
5160 else
5163 }
5165 /* Establish appropriate back-end context for processing the function
5166 FNDECL. The argument might be NULL to indicate processing at top
5167 level, outside of any function scope. */
5168 static void
5170 {
5171 /* Only change the context if the function changes. This hook is called
5172 several times in the course of compiling a function, and we don't want to
5173 slow things down too much or call target_reinit when it isn't safe. */
5177 tree old_tree;
5182 else
5186 {
5190 }
5197 {
5203 else
5205 }
5207 }
5209 \f
5210 /* Return true if this goes in large data/bss. */
5212 static bool
5214 {
5218 /* Functions are never large data. */
5222 /* Automatic variables are never large data. */
5227 {
5233 }
5234 else
5235 {
5238 /* If this is an incomplete type with size 0, then we can't put it
5239 in data because it might be too big when completed. Also,
5240 int_size_in_bytes returns -1 if size can vary or is larger than
5241 an integer in which case also it is safer to assume that it goes in
5242 large data. */
5245 }
5248 }
5250 /* Switch to the appropriate section for output of DECL.
5251 DECL is either a `VAR_DECL' node or a constant of some sort.
5252 RELOC indicates whether forming the initial value of DECL requires
5253 link-time relocations. */
5258 {
5260 {
5264 {
5298 /* We don't split these for medium model. Place them into
5299 default sections and hope for best. */
5301 }
5303 {
5304 /* We might get called with string constants, but get_named_section
5305 doesn't like them as they are not DECLs. Also, we need to set
5306 flags in that case. */
5310 }
5311 }
5313 }
5315 /* Select a set of attributes for section NAME based on the properties
5316 of DECL and whether or not RELOC indicates that DECL's initializer
5317 might contain runtime relocations. */
5319 static unsigned int ATTRIBUTE_UNUSED
5321 {
5335 }
5337 /* Build up a unique section name, expressed as a
5338 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
5339 RELOC indicates whether the initial value of EXP requires
5340 link-time relocations. */
5342 static void ATTRIBUTE_UNUSED
5344 {
5346 {
5348 /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */
5352 {
5376 /* We don't split these for medium model. Place them into
5377 default sections and hope for best. */
5379 }
5381 {
5388 /* If we're using one_only, then there needs to be a .gnu.linkonce
5389 prefix to the section name. */
5396 }
5397 }
5399 }
5401 #ifdef COMMON_ASM_OP
5402 /* This says how to output assembler code to declare an
5403 uninitialized external linkage data object.
5405 For medium model x86-64 we need to use .largecomm opcode for
5406 large objects. */
5407 void
5411 {
5415 else
5420 }
5421 #endif
5423 /* Utility function for targets to use in implementing
5424 ASM_OUTPUT_ALIGNED_BSS. */
5426 void
5429 {
5433 else
5436 #ifdef ASM_DECLARE_OBJECT_NAME
5439 #else
5440 /* Standard thing is just output label for the object. */
5444 }
5445 \f
5446 /* Decide whether we must probe the stack before any space allocation
5447 on this target. It's essentially TARGET_STACK_PROBE except when
5448 -fstack-check causes the stack to be already probed differently. */
5450 bool
5452 {
5453 /* Do not probe the stack twice if static stack checking is enabled. */
5458 }
5459 \f
5460 /* Decide whether we can make a sibling call to a function. DECL is the
5461 declaration of the function being targeted by the call and EXP is the
5462 CALL_EXPR representing the call. */
5464 static bool
5466 {
5470 /* If we are generating position-independent code, we cannot sibcall
5471 optimize direct calls to global functions, as the PLT requires
5472 %ebx be live. (Darwin does not have a PLT.) */
5474 && !TARGET_64BIT
5475 && flag_pic
5476 && flag_plt
5480 /* If we need to align the outgoing stack, then sibcalling would
5481 unalign the stack, which may break the called function. */
5487 {
5490 }
5491 else
5492 {
5493 /* We're looking at the CALL_EXPR, we need the type of the function. */
5498 }
5500 /* Check that the return value locations are the same. Like
5501 if we are returning floats on the 80387 register stack, we cannot
5502 make a sibcall from a function that doesn't return a float to a
5503 function that does or, conversely, from a function that does return
5504 a float to a function that doesn't; the necessary stack adjustment
5505 would not be executed. This is also the place we notice
5506 differences in the return value ABI. Note that it is ok for one
5507 of the functions to have void return type as long as the return
5508 value of the other is passed in a register. */
5513 {
5516 }
5518 ;
5523 {
5524 /* The SYSV ABI has more call-clobbered registers;
5525 disallow sibcalls from MS to SYSV. */
5529 }
5530 else
5531 {
5532 /* If this call is indirect, we'll need to be able to use a
5533 call-clobbered register for the address of the target function.
5534 Make sure that all such registers are not used for passing
5535 parameters. Note that DLLIMPORT functions are indirect. */
5538 {
5540 {
5541 /* ??? Need to count the actual number of registers to be used,
5542 not the possible number of registers. Fix later. */
5544 }
5545 }
5546 }
5548 /* Otherwise okay. That also includes certain types of indirect calls. */
5550 }
5552 /* Handle "cdecl", "stdcall", "fastcall", "regparm", "thiscall",
5553 and "sseregparm" calling convention attributes;
5554 arguments as in struct attribute_spec.handler. */
5556 static tree
5558 tree args,
5561 {
5566 {
5568 name);
5571 }
5573 /* Can combine regparm with all attributes but fastcall, and thiscall. */
5575 {
5576 tree cst;
5579 {
5581 }
5584 {
5586 }
5590 {
5593 name);
5595 }
5597 {
5601 }
5604 }
5607 {
5608 /* Do not warn when emulating the MS ABI. */
5613 name);
5616 }
5618 /* Can combine fastcall with stdcall (redundant) and sseregparm. */
5620 {
5622 {
5624 }
5626 {
5628 }
5630 {
5632 }
5634 {
5636 }
5637 }
5639 /* Can combine stdcall with fastcall (redundant), regparm and
5640 sseregparm. */
5642 {
5644 {
5646 }
5648 {
5650 }
5652 {
5654 }
5655 }
5657 /* Can combine cdecl with regparm and sseregparm. */
5659 {
5661 {
5663 }
5665 {
5667 }
5669 {
5671 }
5672 }
5674 {
5677 name);
5679 {
5681 }
5683 {
5685 }
5687 {
5689 }
5690 }
5692 /* Can combine sseregparm with all attributes. */
5695 }
5697 /* The transactional memory builtins are implicitly regparm or fastcall
5698 depending on the ABI. Override the generic do-nothing attribute that
5699 these builtins were declared with, and replace it with one of the two
5700 attributes that we expect elsewhere. */
5702 static tree
5705 {
5706 tree alt;
5708 /* In no case do we want to add the placeholder attribute. */
5711 /* The 64-bit ABI is unchanged for transactional memory. */
5715 /* ??? Is there a better way to validate 32-bit windows? We have
5716 cfun->machine->call_abi, but that seems to be set only for 64-bit. */
5719 else
5720 {
5723 }
5727 }
5729 /* This function determines from TYPE the calling-convention. */
5731 unsigned int
5733 {
5736 tree attrs;
5743 {
5753 /* Regparam isn't allowed for thiscall and fastcall. */
5755 {
5760 }
5764 }
5771 || is_stdarg
5777 }
5779 /* Return 0 if the attributes for two types are incompatible, 1 if they
5780 are compatible, and 2 if they are nearly compatible (which causes a
5781 warning to be generated). */
5783 static int
5785 {
5801 }
5802 \f
5803 /* Return the regparm value for a function with the indicated TYPE and DECL.
5804 DECL may be NULL when calling function indirectly
5805 or considering a libcall. */
5807 static int
5809 {
5810 tree attr;
5821 {
5824 {
5827 }
5828 }
5834 /* Use register calling convention for local functions when possible. */
5837 {
5842 /* Caller and callee must agree on the calling convention, so
5843 checking here just optimize means that with
5844 __attribute__((optimize (...))) caller could use regparm convention
5845 and callee not, or vice versa. Instead look at whether the callee
5846 is optimized or not. */
5849 {
5852 {
5855 /* Make sure no regparm register is taken by a
5856 fixed register variable. */
5858 local_regparm++)
5862 /* We don't want to use regparm(3) for nested functions as
5863 these use a static chain pointer in the third argument. */
5867 /* Save a register for the split stack. */
5871 /* Each fixed register usage increases register pressure,
5872 so less registers should be used for argument passing.
5873 This functionality can be overriden by an explicit
5874 regparm value. */
5877 globals++;
5879 local_regparm
5884 }
5885 }
5886 }
5889 }
5891 /* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and
5892 DFmode (2) arguments in SSE registers for a function with the
5893 indicated TYPE and DECL. DECL may be NULL when calling function
5894 indirectly or considering a libcall. Return -1 if any FP parameter
5895 should be rejected by error. This is used in siutation we imply SSE
5896 calling convetion but the function is called from another function with
5897 SSE disabled. Otherwise return 0. */
5899 static int
5901 {
5904 /* Use SSE registers to pass SFmode and DFmode arguments if requested
5905 by the sseregparm attribute. */
5908 {
5910 {
5912 {
5916 else
5919 }
5921 }
5924 }
5933 /* For local functions, pass up to SSE_REGPARM_MAX SFmode
5934 (and DFmode for SSE2) arguments in SSE registers. */
5936 /* TARGET_SSE_MATH */
5940 {
5943 {
5944 /* Refuse to produce wrong code when local function with SSE enabled
5945 is called from SSE disabled function.
5946 FIXME: We need a way to detect these cases cross-ltrans partition
5947 and avoid using SSE calling conventions on local functions called
5948 from function with SSE disabled. For now at least delay the
5949 warning until we know we are going to produce wrong code.
5950 See PR66047 */
5955 }
5956 }
5959 }
5961 /* Return true if EAX is live at the start of the function. Used by
5962 ix86_expand_prologue to determine if we need special help before
5963 calling allocate_stack_worker. */
5965 static bool
5967 {
5968 /* Cheat. Don't bother working forward from ix86_function_regparm
5969 to the function type to whether an actual argument is located in
5970 eax. Instead just look at cfg info, which is still close enough
5971 to correct at this point. This gives false positives for broken
5972 functions that might use uninitialized data that happens to be
5973 allocated in eax, but who cares? */
5975 }
5977 static bool
5979 {
5980 tree attr;
5983 {
5989 /* For 32-bit MS-ABI the default is to keep aggregate
5990 return pointer. */
5993 }
5995 }
5997 /* Value is the number of bytes of arguments automatically
5998 popped when returning from a subroutine call.
5999 FUNDECL is the declaration node of the function (as a tree),
6000 FUNTYPE is the data type of the function (as a tree),
6001 or for a library call it is an identifier node for the subroutine name.
6002 SIZE is the number of bytes of arguments passed on the stack.
6004 On the 80386, the RTD insn may be used to pop them if the number
6005 of args is fixed, but if the number is variable then the caller
6006 must pop them all. RTD can't be used for library calls now
6007 because the library is compiled with the Unix compiler.
6008 Use of RTD is a selectable option, since it is incompatible with
6009 standard Unix calling sequences. If the option is not selected,
6010 the caller must always pop the args.
6012 The attribute stdcall is equivalent to RTD on a per module basis. */
6014 static int
6016 {
6019 /* None of the 64-bit ABIs pop arguments. */
6030 /* Lose any fake structure return argument if it is passed on the stack. */
6033 {
6037 }
6040 }
6042 /* Implement the TARGET_LEGITIMATE_COMBINED_INSN hook. */
6044 static bool
6046 {
6047 /* Check operand constraints in case hard registers were propagated
6048 into insn pattern. This check prevents combine pass from
6049 generating insn patterns with invalid hard register operands.
6050 These invalid insns can eventually confuse reload to error out
6051 with a spill failure. See also PRs 46829 and 46843. */
6053 {
6062 {
6070 /* For pre-AVX disallow unaligned loads/stores where the
6071 instructions don't support it. */
6075 {
6079 }
6081 /* A unary operator may be accepted by the predicate, but it
6082 is irrelevant for matching constraints. */
6087 {
6095 }
6102 /* Operand has no constraints, anything is OK. */
6107 {
6112 && operands_match_p
6116 {
6119 }
6120 }
6124 }
6125 }
6128 }
6129 \f
6130 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
6132 static unsigned HOST_WIDE_INT
6134 {
6138 }
6139 \f
6140 /* Argument support functions. */
6142 /* Return true when register may be used to pass function parameters. */
6143 bool
6145 {
6154 {
6158 else
6164 }
6170 /* TODO: The function should depend on current function ABI but
6171 builtins.c would need updating then. Therefore we use the
6172 default ABI. */
6175 /* RAX is used as hidden argument to va_arg functions. */
6181 else
6189 }
6191 /* Return if we do not know how to pass TYPE solely in registers. */
6193 static bool
6195 {
6199 /* For 32-bit, we want TImode aggregates to go on the stack. But watch out!
6200 The layout_type routine is crafty and tries to trick us into passing
6201 currently unsupported vector types on the stack by using TImode. */
6204 }
6206 /* It returns the size, in bytes, of the area reserved for arguments passed
6207 in registers for the function represented by fndecl dependent to the used
6208 abi format. */
6209 int
6211 {
6215 else
6220 }
6222 /* Returns value SYSV_ABI, MS_ABI dependent on fntype, specifying the
6223 call abi used. */
6224 enum calling_abi
6226 {
6228 {
6231 {
6233 {
6235 {
6238 {
6241 }
6242 }
6244 }
6245 }
6249 }
6251 }
6253 /* We add this as a workaround in order to use libc_has_function
6254 hook in i386.md. */
6255 bool
6257 {
6259 }
6261 static bool
6263 {
6265 {
6269 else
6271 }
6273 }
6275 static enum calling_abi
6277 {
6281 }
6283 /* Returns value SYSV_ABI, MS_ABI dependent on cfun, specifying the
6284 call abi used. */
6285 enum calling_abi
6287 {
6291 }
6293 /* Write the extra assembler code needed to declare a function properly. */
6295 void
6297 tree decl)
6298 {
6302 {
6308 }
6310 #ifdef SUBTARGET_ASM_UNWIND_INIT
6312 #endif
6316 /* Output magic byte marker, if hot-patch attribute is set. */
6318 {
6320 {
6321 /* leaq [%rsp + 0], %rsp */
6324 }
6325 else
6326 {
6327 /* movl.s %edi, %edi
6328 push %ebp
6329 movl.s %esp, %ebp */
6332 }
6333 }
6334 }
6336 /* regclass.c */
6339 /* Implementation of call abi switching target hook. Specific to FNDECL
6340 the specific call register sets are set. See also
6341 ix86_conditional_register_usage for more details. */
6342 void
6344 {
6347 else
6349 }
6351 /* 64-bit MS and SYSV ABI have different set of call used registers. Avoid
6352 expensive re-initialization of init_regs each time we switch function context
6353 since this is needed only during RTL expansion. */
6354 static void
6356 {
6360 }
6362 /* Return 1 if pseudo register should be created and used to hold
6363 GOT address for PIC code. */
6364 bool
6366 {
6373 }
6375 /* Initialize large model PIC register. */
6377 static void
6379 {
6381 rtx tmp_reg;
6390 label));
6394 }
6396 /* Create and initialize PIC register if required. */
6397 static void
6399 {
6400 edge entry_edge;
6409 {
6412 else
6414 }
6415 else
6416 {
6417 /* If there is future mcount call in the function it is more profitable
6418 to emit SET_GOT into ABI defined REAL_PIC_OFFSET_TABLE_REGNUM. */
6427 }
6435 }
6437 /* Initialize a variable CUM of type CUMULATIVE_ARGS
6438 for a call to a function whose data type is FNTYPE.
6439 For a library call, FNTYPE is 0. */
6441 void
6445 tree fndecl,
6447 {
6454 {
6457 {
6461 }
6462 else
6464 }
6465 else
6470 /* Set up the number of registers to use for passing arguments. */
6473 {
6475 ? X86_64_REGPARM_MAX
6477 }
6479 {
6482 {
6484 ? X86_64_SSE_REGPARM_MAX
6486 }
6487 }
6495 /* Because type might mismatch in between caller and callee, we need to
6496 use actual type of function for local calls.
6497 FIXME: cgraph_analyze can be told to actually record if function uses
6498 va_start so for local functions maybe_vaarg can be made aggressive
6499 helping K&R code.
6500 FIXME: once typesytem is fixed, we won't need this code anymore. */
6514 {
6515 /* If there are variable arguments, then we won't pass anything
6516 in registers in 32-bit mode. */
6518 {
6527 }
6529 /* Use ecx and edx registers if function has fastcall attribute,
6530 else look for regparm information. */
6532 {
6535 {
6538 }
6540 {
6543 }
6544 else
6546 }
6548 /* Set up the number of SSE registers used for passing SFmode
6549 and DFmode arguments. Warn for mismatching ABI. */
6551 }
6552 }
6554 /* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE.
6555 But in the case of vector types, it is some vector mode.
6557 When we have only some of our vector isa extensions enabled, then there
6558 are some modes for which vector_mode_supported_p is false. For these
6559 modes, the generic vector support in gcc will choose some non-vector mode
6560 in order to implement the type. By computing the natural mode, we'll
6561 select the proper ABI location for the operand and not depend on whatever
6562 the middle-end decides to do with these vector types.
6564 The midde-end can't deal with the vector types > 16 bytes. In this
6565 case, we return the original mode and warn ABI change if CUM isn't
6566 NULL.
6568 If INT_RETURN is true, warn ABI change if the vector mode isn't
6569 available for function return value. */
6571 static machine_mode
6574 {
6578 {
6581 /* ??? Generic code allows us to create width 1 vectors. Ignore. */
6583 {
6588 else
6591 /* Get the mode which has this inner mode and number of units. */
6595 {
6597 {
6602 {
6606 }
6608 {
6612 }
6615 }
6617 {
6622 {
6626 }
6628 {
6632 }
6635 }
6638 {
6643 {
6647 }
6649 {
6653 }
6654 }
6656 {
6661 {
6665 }
6667 {
6671 }
6672 }
6674 }
6677 }
6678 }
6681 }
6683 /* We want to pass a value in REGNO whose "natural" mode is MODE. However,
6684 this may not agree with the mode that the type system has chosen for the
6685 register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can
6686 go ahead and use it. Otherwise we have to build a PARALLEL instead. */
6688 static rtx
6691 {
6692 rtx tmp;
6696 else
6697 {
6701 }
6704 }
6706 /* x86-64 register passing implementation. See x86-64 ABI for details. Goal
6707 of this code is to classify each 8bytes of incoming argument by the register
6708 class and assign registers accordingly. */
6710 /* Return the union class of CLASS1 and CLASS2.
6711 See the x86-64 PS ABI for details. */
6713 static enum x86_64_reg_class
6715 {
6716 /* Rule #1: If both classes are equal, this is the resulting class. */
6720 /* Rule #2: If one of the classes is NO_CLASS, the resulting class is
6721 the other class. */
6727 /* Rule #3: If one of the classes is MEMORY, the result is MEMORY. */
6731 /* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
6739 /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class,
6740 MEMORY is used. */
6749 /* Rule #6: Otherwise class SSE is used. */
6751 }
6753 /* Classify the argument of type TYPE and mode MODE.
6754 CLASSES will be filled by the register class used to pass each word
6755 of the operand. The number of words is returned. In case the parameter
6756 should be passed in memory, 0 is returned. As a special case for zero
6757 sized containers, classes[0] will be NO_CLASS and 1 is returned.
6759 BIT_OFFSET is used internally for handling records and specifies offset
6760 of the offset in bits modulo 512 to avoid overflow cases.
6762 See the x86-64 PS ABI for details.
6763 */
6765 static int
6768 {
6769 HOST_WIDE_INT bytes =
6771 int words
6774 /* Variable sized entities are always passed/returned in memory. */
6783 {
6785 tree field;
6788 /* On x86-64 we pass structures larger than 64 bytes on the stack. */
6795 /* Zero sized arrays or structures are NO_CLASS. We return 0 to
6796 signalize memory class, so handle it as special case. */
6798 {
6801 }
6803 /* Classify each field of record and merge classes. */
6805 {
6807 /* And now merge the fields of structure. */
6809 {
6811 {
6817 /* Bitfields are always classified as integer. Handle them
6818 early, since later code would consider them to be
6819 misaligned integers. */
6821 {
6830 }
6831 else
6832 {
6837 /* Flexible array member is ignored. */
6844 {
6848 {
6851 "the ABI of passing struct with"
6852 " a flexible array member has"
6854 }
6856 }
6858 subclasses,
6868 }
6869 }
6870 }
6874 /* Arrays are handled as small records. */
6875 {
6882 /* The partial classes are now full classes. */
6893 }
6896 /* Unions are similar to RECORD_TYPE but offset is always 0.
6897 */
6899 {
6901 {
6909 bit_offset);
6914 }
6915 }
6920 }
6923 {
6924 /* When size > 16 bytes, if the first one isn't
6925 X86_64_SSE_CLASS or any other ones aren't
6926 X86_64_SSEUP_CLASS, everything should be passed in
6927 memory. */
6934 }
6936 /* Final merger cleanup. */
6938 {
6939 /* If one class is MEMORY, everything should be passed in
6940 memory. */
6944 /* The X86_64_SSEUP_CLASS should be always preceded by
6945 X86_64_SSE_CLASS or X86_64_SSEUP_CLASS. */
6949 {
6950 /* The first one should never be X86_64_SSEUP_CLASS. */
6953 }
6955 /* If X86_64_X87UP_CLASS isn't preceded by X86_64_X87_CLASS,
6956 everything should be passed in memory. */
6959 {
6962 /* The first one should never be X86_64_X87UP_CLASS. */
6965 {
6968 "the ABI of passing union with long double"
6970 }
6972 }
6973 }
6975 }
6977 /* Compute alignment needed. We align all types to natural boundaries with
6978 exception of XFmode that is aligned to 64bits. */
6980 {
6989 /* Misaligned fields are always returned in memory. */
6992 }
6994 /* for V1xx modes, just use the base mode */
6999 /* Classification of atomic types. */
7001 {
7017 {
7020 /* Analyze last 128 bits only. */
7024 {
7027 }
7029 {
7032 }
7034 {
7038 }
7040 {
7043 }
7044 else
7046 }
7053 /* OImode shouldn't be used directly. */
7060 else
7078 else
7079 {
7083 {
7086 "the ABI of passing structure with complex float"
7088 }
7091 }
7100 /* This modes is larger than 16 bytes. */
7158 else
7162 }
7163 }
7165 /* Examine the argument and return set number of register required in each
7166 class. Return true iff parameter should be passed in memory. */
7168 static bool
7171 {
7182 {
7203 }
7206 }
7208 /* Construct container for the argument used by GCC interface. See
7209 FUNCTION_ARG for the detailed description. */
7211 static rtx
7215 {
7216 /* The following variables hold the static issued_error state. */
7221 machine_mode tmpmode;
7230 rtx ret;
7241 /* We allowed the user to turn off SSE for kernel mode. Don't crash if
7242 some less clueful developer tries to use floating-point anyway. */
7244 {
7246 {
7248 {
7251 }
7252 }
7254 {
7257 }
7259 }
7261 /* Likewise, error if the ABI requires us to return values in the
7262 x87 registers and the user specified -mno-80387. */
7268 {
7270 {
7273 }
7275 }
7277 /* First construct simple cases. Avoid SCmode, since we want to use
7278 single register to pass this type. */
7281 {
7296 /* Zero sized array, struct or class. */
7300 }
7339 /* Otherwise figure out the entries of the PARALLEL. */
7341 {
7345 {
7350 /* Merge TImodes on aligned occasions here too. */
7352 tmpmode
7356 else
7358 /* We've requested 24 bytes we
7359 don't have mode for. Use DImode. */
7366 intreg++;
7374 sse_regno++;
7382 sse_regno++;
7387 {
7393 {
7395 i++;
7396 }
7397 else
7422 }
7428 sse_regno++;
7432 }
7433 }
7435 /* Empty aligned struct, union or class. */
7443 }
7445 /* Update the data in CUM to advance over an argument of mode MODE
7446 and data type TYPE. (TYPE is null for libcalls where that information
7447 may not be available.)
7449 Return a number of integer regsiters advanced over. */
7451 static int
7454 HOST_WIDE_INT words)
7455 {
7460 {
7467 /* FALLTHRU */
7479 {
7482 }
7486 /* OImode shouldn't be used directly. */
7499 /* FALLTHRU */
7521 {
7526 {
7529 }
7530 }
7540 {
7545 {
7548 }
7549 }
7551 }
7553 {
7559 }
7562 }
7564 static int
7567 {
7570 /* Unnamed 512 and 256bit vector mode parameters are passed on stack. */
7577 {
7583 }
7584 else
7585 {
7590 }
7591 }
7593 static int
7595 HOST_WIDE_INT words)
7596 {
7597 /* Otherwise, this should be passed indirect. */
7602 {
7606 }
7608 }
7610 /* Update the data in CUM to advance over an argument of mode MODE and
7611 data type TYPE. (TYPE is null for libcalls where that information
7612 may not be available.) */
7614 static void
7617 {
7624 else
7633 {
7634 /* If we pass bounds in BT then just update remained bounds count. */
7636 {
7639 }
7641 /* Update remained number of bounds to force. */
7648 }
7650 /* The first arg not going to Bounds Tables resets this counter. */
7652 /* For unnamed args we always pass bounds to avoid bounds mess when
7653 passed and received types do not match. If bounds do not follow
7654 unnamed arg, still pretend required number of bounds were passed. */
7656 {
7659 }
7662 {
7667 else
7669 }
7670 else
7673 /* For stdarg we expect bounds to be passed for each value passed
7674 in register. */
7677 /* For pointers passed in memory we expect bounds passed in Bounds
7678 Table. */
7681 }
7683 /* Define where to put the arguments to a function.
7684 Value is zero to push the argument on the stack,
7685 or a hard register in which to store the argument.
7687 MODE is the argument's machine mode.
7688 TYPE is the data type of the argument (as a tree).
7689 This is null for libcalls where that information may
7690 not be available.
7691 CUM is a variable of type CUMULATIVE_ARGS which gives info about
7692 the preceding args and about the function being called.
7693 NAMED is nonzero if this argument is a named parameter
7694 (otherwise it is an extra parameter matching an ellipsis). */
7696 static rtx
7700 {
7702 /* Avoid the AL settings for the Unix64 ABI. */
7707 {
7714 /* FALLTHRU */
7720 {
7723 /* Fastcall allocates the first two DWORD (SImode) or
7724 smaller arguments to ECX and EDX if it isn't an
7725 aggregate type . */
7727 {
7733 /* ECX not EAX is the first allocated register. */
7736 }
7738 }
7751 /* FALLTHRU */
7753 /* In 32bit, we pass TImode in xmm registers. */
7761 {
7765 }
7770 /* OImode and XImode shouldn't be used directly. */
7786 {
7790 }
7800 {
7804 }
7806 }
7808 {
7814 }
7817 }
7819 static rtx
7822 {
7823 /* Handle a hidden AL argument containing number of registers
7824 for varargs x86-64 functions. */
7828 ? X86_64_SSE_REGPARM_MAX
7833 {
7849 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
7853 }
7859 }
7861 static rtx
7864 HOST_WIDE_INT bytes)
7865 {
7868 /* We need to add clobber for MS_ABI->SYSV ABI calls in expand_call.
7869 We use value of -2 to specify that current function call is MSABI. */
7873 /* If we've run out of registers, it goes on the stack. */
7879 /* Only floating point modes are passed in anything but integer regs. */
7881 {
7884 else
7885 {
7888 /* Unnamed floating parameters are passed in both the
7889 SSE and integer registers. */
7895 }
7896 }
7897 /* Handle aggregated types passed in register. */
7899 {
7904 }
7907 }
7909 /* Return where to put the arguments to a function.
7910 Return zero to push the argument on the stack, or a hard register in which to store the argument.
7912 MODE is the argument's machine mode. TYPE is the data type of the
7913 argument. It is null for libcalls where that information may not be
7914 available. CUM gives information about the preceding args and about
7915 the function being called. NAMED is nonzero if this argument is a
7916 named parameter (otherwise it is an extra parameter matching an
7917 ellipsis). */
7919 static rtx
7922 {
7926 rtx arg;
7928 /* All pointer bounds argumntas are handled separately here. */
7931 {
7932 /* Return NULL if bounds are forced to go in Bounds Table. */
7935 /* Return the next available bound reg if any. */
7938 /* Return the next special slot number otherwise. */
7939 else
7943 }
7947 else
7951 /* To simplify the code below, represent vector types with a vector mode
7952 even if MMX/SSE are not active. */
7957 {
7962 else
7964 }
7965 else
7969 }
7971 /* A C expression that indicates when an argument must be passed by
7972 reference. If nonzero for an argument, a copy of that argument is
7973 made in memory and a pointer to the argument is passed instead of
7974 the argument itself. The pointer is passed in whatever way is
7975 appropriate for passing a pointer to that type. */
7977 static bool
7980 {
7983 /* Bounds are never passed by reference. */
7989 {
7992 /* See Windows x64 Software Convention. */
7994 {
7998 {
7999 /* Arrays are passed by reference. */
8004 {
8005 /* Structs/unions of sizes other than 8, 16, 32, or 64 bits
8006 are passed by reference. */
8008 }
8009 }
8011 /* __m128 is passed by reference. */
8013 }
8016 }
8019 }
8021 /* Return true when TYPE should be 128bit aligned for 32bit argument
8022 passing ABI. XXX: This function is obsolete and is only used for
8023 checking psABI compatibility with previous versions of GCC. */
8025 static bool
8027 {
8039 {
8040 /* Walk the aggregates recursively. */
8042 {
8046 {
8047 tree field;
8049 /* Walk all the structure fields. */
8051 {
8055 }
8057 }
8060 /* Just for use if some languages passes arrays by value. */
8067 }
8068 }
8070 }
8072 /* Return the alignment boundary for MODE and TYPE with alignment ALIGN.
8073 XXX: This function is obsolete and is only used for checking psABI
8074 compatibility with previous versions of GCC. */
8076 static unsigned int
8079 {
8080 /* In 32bit, only _Decimal128 and __float128 are aligned to their
8081 natural boundaries. */
8083 {
8084 /* i386 ABI defines all arguments to be 4 byte aligned. We have to
8085 make an exception for SSE modes since these require 128bit
8086 alignment.
8088 The handling here differs from field_alignment. ICC aligns MMX
8089 arguments to 4 byte boundaries, while structure fields are aligned
8090 to 8 byte boundaries. */
8092 {
8095 }
8096 else
8097 {
8100 }
8101 }
8105 }
8107 /* Return true when TYPE should be 128bit aligned for 32bit argument
8108 passing ABI. */
8110 static bool
8112 {
8122 {
8123 /* Walk the aggregates recursively. */
8125 {
8129 {
8130 tree field;
8132 /* Walk all the structure fields. */
8134 field;
8136 {
8140 }
8142 }
8145 /* Just for use if some languages passes arrays by value. */
8152 }
8153 }
8154 else
8158 }
8160 /* Gives the alignment boundary, in bits, of an argument with the
8161 specified mode and type. */
8163 static unsigned int
8165 {
8168 {
8169 /* Since the main variant type is used for call, we convert it to
8170 the main variant type. */
8173 }
8174 else
8178 else
8179 {
8184 {
8185 /* i386 ABI defines XFmode arguments to be 4 byte aligned. */
8187 {
8190 }
8196 }
8199 && !warned
8201 saved_align))
8202 {
8205 "The ABI for passing parameters with %d-byte"
8208 }
8209 }
8212 }
8214 /* Return true if N is a possible register number of function value. */
8216 static bool
8218 {
8220 {
8233 /* Complex values are returned in %st(0)/%st(1) pair. */
8236 /* TODO: The function should depend on current function ABI but
8237 builtins.c would need updating then. Therefore we use the
8238 default ABI. */
8243 /* Complex values are returned in %xmm0/%xmm1 pair. */
8252 }
8255 }
8257 /* Define how to find the value returned by a function.
8258 VALTYPE is the data type of the value (as a tree).
8259 If the precise function being called is known, FUNC is its FUNCTION_DECL;
8260 otherwise, FUNC is 0. */
8262 static rtx
8265 {
8268 /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where
8269 we normally prevent this case when mmx is not available. However
8270 some ABIs may require the result to be returned like DImode. */
8274 /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where
8275 we prevent this case when sse is not available. However some ABIs
8276 may require the result to be returned like integer TImode. */
8281 /* 32-byte vector modes in %ymm0. */
8285 /* 64-byte vector modes in %zmm0. */
8289 /* Floating point return values in %st(0) (unless -mno-fp-ret-in-387). */
8292 else
8293 /* Most things go in %eax. */
8296 /* Override FP return register with %xmm0 for local functions when
8297 SSE math is enabled or for functions with sseregparm attribute. */
8299 {
8302 {
8307 }
8311 }
8313 /* OImode shouldn't be used directly. */
8317 }
8319 static rtx
8321 const_tree valtype)
8322 {
8323 rtx ret;
8325 /* Handle libcalls, which don't provide a type node. */
8327 {
8331 {
8350 }
8353 }
8355 {
8356 /* Pointers are always returned in word_mode. */
8358 }
8364 /* For zero sized structures, construct_container returns NULL, but we
8365 need to keep rest of compiler happy by returning meaningful value. */
8370 }
8372 static rtx
8374 const_tree valtype)
8375 {
8379 {
8381 {
8400 }
8401 }
8403 }
8405 static rtx
8408 {
8423 else
8425 }
8427 static rtx
8429 {
8435 }
8437 /* Return an RTX representing a place where a function returns
8438 or recieves pointer bounds or NULL if no bounds are returned.
8440 VALTYPE is a data type of a value returned by the function.
8442 FN_DECL_OR_TYPE is a tree node representing FUNCTION_DECL
8443 or FUNCTION_TYPE of the function.
8445 If OUTGOING is false, return a place in which the caller will
8446 see the return value. Otherwise, return a place where a
8447 function returns a value. */
8449 static rtx
8451 const_tree fntype_or_decl ATTRIBUTE_UNUSED,
8453 {
8459 {
8460 bitmap slots;
8462 bitmap_iterator bi;
8470 {
8475 }
8481 }
8482 else
8486 }
8488 /* Pointer function arguments and return values are promoted to
8489 word_mode. */
8491 static machine_mode
8495 {
8497 {
8500 }
8502 for_return);
8503 }
8505 /* Return true if a structure, union or array with MODE containing FIELD
8506 should be accessed using BLKmode. */
8508 static bool
8510 {
8511 /* Union with XFmode must be in BLKmode. */
8515 }
8517 rtx
8519 {
8521 }
8523 /* Return true iff type is returned in memory. */
8525 static bool
8527 {
8528 #ifdef SUBTARGET_RETURN_IN_MEMORY
8530 #else
8532 HOST_WIDE_INT size;
8538 {
8540 {
8543 /* __m128 is returned in xmm0. */
8552 /* Otherwise, the size must be exactly in [1248]. */
8554 }
8555 else
8556 {
8561 }
8562 }
8563 else
8564 {
8574 {
8575 /* User-created vectors small enough to fit in EAX. */
8579 /* Unless ABI prescibes otherwise,
8580 MMX/3dNow values are returned in MM0 if available. */
8585 /* SSE values are returned in XMM0 if available. */
8589 /* AVX values are returned in YMM0 if available. */
8593 /* AVX512F values are returned in ZMM0 if available. */
8596 }
8604 /* OImode shouldn't be used directly. */
8608 }
8609 #endif
8610 }
8612 \f
8613 /* Create the va_list data type. */
8615 /* Returns the calling convention specific va_list date type.
8616 The argument ABI can be DEFAULT_ABI, MS_ABI, or SYSV_ABI. */
8618 static tree
8620 {
8623 /* For i386 we use plain pointer to argument area. */
8633 unsigned_type_node);
8636 unsigned_type_node);
8639 ptr_type_node);
8642 ptr_type_node);
8661 /* The correct type is an array type of one element. */
8663 }
8665 /* Setup the builtin va_list data type and for 64-bit the additional
8666 calling convention specific va_list data types. */
8668 static tree
8670 {
8673 /* Initialize abi specific va_list builtin types. */
8675 {
8676 tree t;
8678 {
8683 }
8684 else
8685 {
8690 }
8692 {
8697 }
8698 else
8699 {
8704 }
8705 }
8708 }
8710 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
8712 static void
8714 {
8716 alias_set_type set;
8719 /* GPR size of varargs save area. */
8722 else
8725 /* FPR size of varargs save area. We don't need it if we don't pass
8726 anything in SSE registers. */
8729 else
8743 {
8751 }
8754 {
8755 machine_mode smode;
8757 rtx test;
8759 /* Now emit code to save SSE registers. The AX parameter contains number
8760 of SSE parameter registers used to call this function, though all we
8761 actually check here is the zero/non-zero status. */
8766 label));
8768 /* ??? If !TARGET_SSE_TYPELESS_STORES, would we perform better if
8769 we used movdqa (i.e. TImode) instead? Perhaps even better would
8770 be if we could determine the real mode of the data, via a hook
8771 into pass_stdarg. Ignore all that for now. */
8781 {
8790 }
8793 }
8794 }
8796 static void
8798 {
8802 /* Reset to zero, as there might be a sysv vaarg used
8803 before. */
8808 {
8819 }
8820 }
8822 static void
8825 {
8827 CUMULATIVE_ARGS next_cum;
8828 tree fntype;
8830 /* This argument doesn't appear to be used anymore. Which is good,
8831 because the old code here didn't suppress rtl generation. */
8839 /* For varargs, we do not want to skip the dummy va_dcl argument.
8840 For stdargs, we do want to skip the last named argument. */
8848 else
8850 }
8852 static void
8855 tree type,
8858 {
8860 CUMULATIVE_ARGS next_cum;
8861 tree fntype;
8862 rtx save_area;
8867 /* Do nothing if we use plain pointer to argument area. */
8873 /* For varargs, we do not want to skip the dummy va_dcl argument.
8874 For stdargs, we do want to skip the last named argument. */
8888 {
8893 rtx bounds;
8897 else
8898 {
8899 rtx ldx_addr =
8906 }
8912 bnd_reg++;
8913 }
8914 }
8917 /* Checks if TYPE is of kind va_list char *. */
8919 static bool
8921 {
8922 tree canonic;
8924 /* For 32-bit it is always true. */
8930 }
8932 /* Implement va_start. */
8934 static void
8936 {
8940 tree type;
8941 rtx ovf_rtx;
8945 {
8948 /* When we are splitting the stack, we can't refer to the stack
8949 arguments using internal_arg_pointer, because they may be on
8950 the old stack. The split stack prologue will arrange to
8951 leave a pointer to the old stack arguments in a scratch
8952 register, which we here copy to a pseudo-register. The split
8953 stack prologue can't set the pseudo-register directly because
8954 it (the prologue) runs before any registers have been saved. */
8958 {
8959 rtx reg;
8973 }
8974 }
8976 /* Only 64bit target needs something special. */
8978 {
8981 else
8982 {
8992 /* Store zero bounds for va_list. */
8996 next));
8998 }
9000 }
9009 /* The following should be folded into the MEM_REF offset. */
9019 /* Count number of gp and fp argument registers used. */
9025 {
9031 }
9034 {
9040 }
9042 /* Find the overflow area. */
9046 else
9052 /* Store zero bounds for overflow area pointer. */
9061 {
9062 /* Find the register save area.
9063 Prologue of the function save it right above stack frame. */
9069 /* Store zero bounds for save area pointer. */
9076 }
9077 }
9079 /* Implement va_arg. */
9081 static tree
9084 {
9091 rtx container;
9093 tree ptrtype;
9094 machine_mode nat_mode;
9097 /* Only 64bit target needs something special. */
9121 {
9134 /* Unnamed 256 and 512bit vector mode parameters are passed on stack. */
9136 {
9139 }
9147 }
9149 /* Pull the value out of the saved registers. */
9154 {
9168 /* In case we are passing structure, verify that it is consecutive block
9169 on the register save area. If not we need to do moves. */
9171 {
9172 /* Verify that all registers are strictly consecutive */
9174 {
9178 {
9183 }
9184 }
9185 else
9186 {
9190 {
9195 }
9196 }
9197 }
9199 {
9202 }
9203 else
9204 {
9207 }
9209 /* First ensure that we fit completely in registers. */
9211 {
9218 }
9220 {
9228 }
9230 /* Compute index to start of area used for integer regs. */
9232 {
9233 /* int_addr = gpr + sav; */
9236 }
9238 {
9239 /* sse_addr = fpr + sav; */
9242 }
9244 {
9248 /* addr = &temp; */
9253 {
9257 tree piece_type;
9258 tree addr_type;
9259 tree daddr_type;
9268 {
9273 }
9277 else
9284 {
9287 }
9288 else
9289 {
9292 }
9299 {
9304 }
9305 else
9306 {
9307 tree copy
9312 }
9314 }
9315 }
9318 {
9322 }
9325 {
9329 }
9334 }
9336 /* ... otherwise out of the overflow area. */
9338 /* When we align parameter on stack for caller, if the parameter
9339 alignment is beyond MAX_SUPPORTED_STACK_ALIGNMENT, it will be
9340 aligned at MAX_SUPPORTED_STACK_ALIGNMENT. We will match callee
9341 here with caller. */
9346 /* Care for on-stack alignment if needed. */
9349 else
9350 {
9355 }
9372 }
9373 \f
9374 /* Return true if OPNUM's MEM should be matched
9375 in movabs* patterns. */
9377 bool
9379 {
9391 }
9392 \f
9393 /* Initialize the table of extra 80387 mathematical constants. */
9395 static void
9397 {
9399 {
9405 };
9409 {
9411 /* Ensure each constant is rounded to XFmode precision. */
9414 }
9417 }
9419 /* Return non-zero if the constant is something that
9420 can be loaded with a special instruction. */
9422 int
9424 {
9427 REAL_VALUE_TYPE r;
9439 /* For XFmode constants, try to find a special 80387 instruction when
9440 optimizing for size or on those CPUs that benefit from them. */
9443 {
9452 }
9454 /* Load of the constant -0.0 or -1.0 will be split as
9455 fldz;fchs or fld1;fchs sequence. */
9462 }
9464 /* Return the opcode of the special instruction to be used to load
9465 the constant X. */
9469 {
9471 {
9491 }
9492 }
9494 /* Return the CONST_DOUBLE representing the 80387 constant that is
9495 loaded by the specified special instruction. The argument IDX
9496 matches the return value from standard_80387_constant_p. */
9498 rtx
9500 {
9507 {
9518 }
9521 XFmode);
9522 }
9524 /* Return 1 if X is all 0s and 2 if x is all 1s
9525 in supported SSE/AVX vector mode. */
9527 int
9529 {
9530 machine_mode mode;
9541 {
9562 }
9565 }
9567 /* Return the opcode of the special instruction to be used to load
9568 the constant X. */
9572 {
9574 {
9577 {
9604 }
9614 else
9619 }
9621 }
9623 /* Returns true if OP contains a symbol reference */
9625 bool
9627 {
9636 {
9638 {
9644 }
9648 }
9651 }
9653 /* Return true if it is appropriate to emit `ret' instructions in the
9654 body of a function. Do this only if the epilogue is simple, needing a
9655 couple of insns. Prior to reloading, we can't tell how many registers
9656 must be saved, so return false then. Return false if there is no frame
9657 marker to de-allocate. */
9659 bool
9661 {
9667 /* Don't allow more than 32k pop, since that's all we can do
9668 with one instruction. */
9675 }
9676 \f
9677 /* Value should be nonzero if functions must have frame pointers.
9678 Zero means the frame pointer need not be set up (and parms may
9679 be accessed via the stack pointer) in functions that seem suitable. */
9681 static bool
9683 {
9684 /* If we accessed previous frames, then the generated code expects
9685 to be able to access the saved ebp value in our frame. */
9689 /* Several x86 os'es need a frame pointer for other reasons,
9690 usually pertaining to setjmp. */
9694 /* For older 32-bit runtimes setjmp requires valid frame-pointer. */
9698 /* Win64 SEH, very large frames need a frame-pointer as maximum stack
9699 allocation is 4GB. */
9703 /* In ix86_option_override_internal, TARGET_OMIT_LEAF_FRAME_POINTER
9704 turns off the frame pointer by default. Turn it back on now if
9705 we've not got a leaf function. */
9715 }
9717 /* Record that the current function accesses previous call frames. */
9719 void
9721 {
9723 }
9724 \f
9725 #ifndef USE_HIDDEN_LINKONCE
9726 # if defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)
9727 # define USE_HIDDEN_LINKONCE 1
9728 # else
9729 # define USE_HIDDEN_LINKONCE 0
9730 # endif
9731 #endif
9735 /* Fills in the label name that should be used for a pc thunk for
9736 the given register. */
9738 static void
9740 {
9745 else
9747 }
9750 /* This function generates code for -fpic that loads %ebx with
9751 the return address of the caller and then returns. */
9753 static void
9755 {
9760 {
9762 tree decl;
9778 #if TARGET_MACHO
9780 {
9789 }
9790 else
9791 #endif
9793 {
9804 }
9805 else
9806 {
9809 }
9815 /* Make sure unwind info is emitted for the thunk if needed. */
9818 /* Pad stack IP move with 4 instructions (two NOPs count
9819 as one instruction). */
9821 {
9826 }
9837 }
9841 }
9843 /* Emit code for the SET_GOT patterns. */
9847 {
9853 {
9854 /* Load (*VXWORKS_GOTT_BASE) into the PIC register. */
9859 /* Load (*VXWORKS_GOTT_BASE)[VXWORKS_GOTT_INDEX] into the PIC register.
9860 Use %P and a local symbol in order to print VXWORKS_GOTT_INDEX as
9861 an unadorned address. */
9866 }
9871 {
9873 /* We don't need a pic base, we're not producing pic. */
9880 }
9881 else
9882 {
9891 #if TARGET_MACHO
9892 /* Output the Mach-O "canonical" pic base label name ("Lxx$pb") here.
9893 This is what will be referenced by the Mach-O PIC subsystem. */
9897 /* When we are restoring the pic base at the site of a nonlocal label,
9898 and we decided to emit the pic base above, we will still output a
9899 local label used for calculating the correction offset (even though
9900 the offset will be 0 in that case). */
9904 #endif
9905 }
9911 }
9913 /* Generate an "push" pattern for input ARG. */
9915 static rtx
9917 {
9929 stack_pointer_rtx)),
9930 arg);
9931 }
9933 /* Generate an "pop" pattern for input ARG. */
9935 static rtx
9937 {
9944 stack_pointer_rtx)));
9945 }
9947 /* Return >= 0 if there is an unused call-clobbered register available
9948 for the entire function. */
9950 static unsigned int
9952 {
9959 {
9961 /* Can't use the same register for both PIC and DRAP. */
9964 else
9969 }
9972 }
9974 /* Return TRUE if we need to save REGNO. */
9976 static bool
9978 {
9981 {
9983 {
9984 /* REAL_PIC_OFFSET_TABLE_REGNUM used by call to
9985 _mcount in prologue. */
9988 }
9995 }
9998 {
10001 {
10007 }
10008 }
10019 }
10021 /* Return number of saved general prupose registers. */
10023 static int
10025 {
10031 nregs ++;
10033 }
10035 /* Return number of saved SSE registrers. */
10037 static int
10039 {
10047 nregs ++;
10049 }
10051 /* Given FROM and TO register numbers, say whether this elimination is
10052 allowed. If stack alignment is needed, we can only replace argument
10053 pointer with hard frame pointer, or replace frame pointer with stack
10054 pointer. Otherwise, frame pointer elimination is automatically
10055 handled and all other eliminations are valid. */
10057 static bool
10059 {
10065 else
10067 }
10069 /* Return the offset between two registers, one to be eliminated, and the other
10070 its replacement, at the start of a routine. */
10072 HOST_WIDE_INT
10074 {
10083 else
10084 {
10092 }
10093 }
10095 /* In a dynamically-aligned function, we can't know the offset from
10096 stack pointer to frame pointer, so we must ensure that setjmp
10097 eliminates fp against the hard fp (%ebp) rather than trying to
10098 index from %esp up to the top of the frame across a gap that is
10099 of unknown (at compile-time) size. */
10100 static rtx
10102 {
10104 }
10106 /* When using -fsplit-stack, the allocation routines set a field in
10107 the TCB to the bottom of the stack plus this much space, measured
10108 in bytes. */
10110 #define SPLIT_STACK_AVAILABLE 256
10112 /* Fill structure ix86_frame about frame of currently computed function. */
10114 static void
10116 {
10118 HOST_WIDE_INT offset;
10121 HOST_WIDE_INT to_allocate;
10126 /* 64-bit MS ABI seem to require stack alignment to be always 16 except for
10127 function prologues and leaf. */
10131 {
10134 }
10135 /* preferred_stack_boundary is never updated for call
10136 expanded from tls descriptor. Update it here. We don't update it in
10137 expand stage because according to the comments before
10138 ix86_current_function_calls_tls_descriptor, tls calls may be optimized
10139 away. */
10142 {
10146 }
10155 /* For SEH we have to limit the amount of code movement into the prologue.
10156 At present we do this via a BLOCKAGE, at which point there's very little
10157 scheduling that can be done, which means that there's very little point
10158 in doing anything except PUSHs. */
10162 /* During reload iteration the amount of registers saved can change.
10163 Recompute the value as needed. Do not recompute when amount of registers
10164 didn't change as reload does multiple calls to the function and does not
10165 expect the decision to change within single iteration. */
10168 {
10174 /* The fast prologue uses move instead of push to save registers. This
10175 is significantly longer, but also executes faster as modern hardware
10176 can execute the moves in parallel, but can't do that for push/pop.
10178 Be careful about choosing what prologue to emit: When function takes
10179 many instructions to execute we may use slow version as well as in
10180 case function is known to be outside hot spot (this is known with
10181 feedback only). Weight the size of function by number of registers
10182 to save as it is cheap to use one or two push instructions but very
10183 slow to use many of them. */
10187 || (flag_branch_probabilities
10190 else
10193 }
10195 frame->save_regs_using_mov
10197 /* If static stack checking is enabled and done with probes,
10198 the registers need to be saved before allocating the frame. */
10201 /* Skip return address. */
10204 /* Skip pushed static chain. */
10208 /* Skip saved base pointer. */
10213 /* The traditional frame pointer location is at the top of the frame. */
10216 /* Register save area */
10220 /* On SEH target, registers are pushed just before the frame pointer
10221 location. */
10225 /* Align and set SSE register save area. */
10227 {
10228 /* The only ABI that has saved SSE registers (Win64) also has a
10229 16-byte aligned default stack, and thus we don't need to be
10230 within the re-aligned local stack frame to save them. */
10234 }
10237 /* The re-aligned stack starts here. Values before this point are not
10238 directly comparable with values below this point. In order to make
10239 sure that no value happens to be the same before and after, force
10240 the alignment computation below to add a non-zero value. */
10244 /* Va-arg area */
10248 /* Align start of frame for local function. */
10257 /* Frame pointer points here. */
10262 /* Add outgoing arguments area. Can be skipped if we eliminated
10263 all the function calls as dead code.
10264 Skipping is however impossible when function calls alloca. Alloca
10265 expander assumes that last crtl->outgoing_args_size
10266 of stack frame are unused. */
10270 {
10273 }
10274 else
10277 /* Align stack boundary. Only needed if we're calling another function
10278 or using alloca. */
10283 /* We've reached end of stack frame. */
10286 /* Size prologue needs to allocate. */
10297 {
10303 }
10304 else
10308 /* The SEH frame pointer location is near the bottom of the frame.
10309 This is enforced by the fact that the difference between the
10310 stack pointer and the frame pointer is limited to 240 bytes in
10311 the unwind data structure. */
10313 {
10314 HOST_WIDE_INT diff;
10316 /* If we can leave the frame pointer where it is, do so. Also, returns
10317 the establisher frame for __builtin_frame_address (0). */
10322 {
10323 /* Ideally we'd determine what portion of the local stack frame
10324 (within the constraint of the lowest 240) is most heavily used.
10325 But without that complication, simply bias the frame pointer
10326 by 128 bytes so as to maximize the amount of the local stack
10327 frame that is addressable with 8-bit offsets. */
10329 }
10330 }
10331 }
10333 /* This is semi-inlined memory_address_length, but simplified
10334 since we know that we're always dealing with reg+offset, and
10335 to avoid having to create and discard all that rtl. */
10339 {
10343 {
10344 /* EBP and R13 cannot be encoded without an offset. */
10346 }
10350 /* ESP and R12 must be encoded with a SIB byte. */
10352 len++;
10355 }
10357 /* Return an RTX that points to CFA_OFFSET within the stack frame.
10358 The valid base registers are taken from CFUN->MACHINE->FS. */
10360 static rtx
10362 {
10368 {
10369 /* Choose the base register most likely to allow the most scheduling
10370 opportunities. Generally FP is valid throughout the function,
10371 while DRAP must be reloaded within the epilogue. But choose either
10372 over the SP due to increased encoding size. */
10375 {
10378 }
10380 {
10383 }
10385 {
10388 }
10389 }
10390 else
10391 {
10392 HOST_WIDE_INT toffset;
10395 /* Choose the base register with the smallest address encoding.
10396 With a tie, choose FP > DRAP > SP. */
10398 {
10402 }
10404 {
10408 {
10412 }
10413 }
10415 {
10419 {
10423 }
10424 }
10425 }
10429 }
10431 /* Emit code to save registers in the prologue. */
10433 static void
10435 {
10441 {
10444 }
10445 }
10447 /* Emit a single register save at CFA - CFA_OFFSET. */
10449 static void
10451 HOST_WIDE_INT cfa_offset)
10452 {
10460 /* For SSE saves, we need to indicate the 128-bit alignment. */
10471 /* When saving registers into a re-aligned local stack frame, avoid
10472 any tricky guessing by dwarf2out. */
10474 {
10478 {
10479 /* A bit of a hack. We force the DRAP register to be saved in
10480 the re-aligned stack frame, which provides us with a copy
10481 of the CFA that will last past the prologue. Install it. */
10487 }
10488 else
10489 {
10490 /* The frame pointer is a stable reference within the
10491 aligned frame. Use it. */
10497 }
10498 }
10500 /* The memory may not be relative to the current CFA register,
10501 which means that we may need to generate a new pattern for
10502 use by the unwind info. */
10504 {
10509 }
10510 }
10512 /* Emit code to save registers using MOV insns.
10513 First register is stored at CFA - CFA_OFFSET. */
10514 static void
10516 {
10521 {
10524 }
10525 }
10527 /* Emit code to save SSE registers using MOV insns.
10528 First register is stored at CFA - CFA_OFFSET. */
10529 static void
10531 {
10536 {
10539 }
10540 }
10544 /* Add a REG_CFA_RESTORE REG note to INSN or queue them until next stack
10545 manipulation insn. The value is on the stack at CFA - CFA_OFFSET.
10546 Don't add the note if the previously saved value will be left untouched
10547 within stack red-zone till return, as unwinders can find the same value
10548 in the register and on the stack. */
10550 static void
10552 {
10558 {
10561 }
10562 else
10563 queued_cfa_restores
10565 }
10567 /* Add queued REG_CFA_RESTORE notes if any to INSN. */
10569 static void
10571 {
10572 rtx last;
10576 ;
10581 }
10583 /* Expand prologue or epilogue stack adjustment.
10584 The pattern exist to put a dependency on all ebp-based memory accesses.
10585 STYLE should be negative if instructions should be marked as frame related,
10586 zero if %r11 register is live and cannot be freely used and positive
10587 otherwise. */
10589 static void
10592 {
10594 rtx insn;
10601 else
10602 {
10603 rtx tmp;
10604 /* r11 is used by indirect sibcall return as well, set before the
10605 epilogue and used after the epilogue. */
10608 else
10609 {
10613 }
10619 }
10626 {
10627 rtx r;
10637 }
10639 {
10642 {
10646 }
10647 }
10650 {
10655 {
10658 }
10660 {
10663 }
10664 else
10665 {
10666 /* Else there are two possibilities: SP itself, which we set
10667 up as the default above. Or EH_RETURN_STACKADJ_RTX, which is
10668 taken care of this by hand along the eh_return path. */
10671 }
10675 }
10676 }
10678 /* Find an available register to be used as dynamic realign argument
10679 pointer regsiter. Such a register will be written in prologue and
10680 used in begin of body, so it must not be
10681 1. parameter passing register.
10682 2. GOT pointer.
10683 We reuse static-chain register if it is available. Otherwise, we
10684 use DI for i386 and R13 for x86-64. We chose R13 since it has
10685 shorter encoding.
10687 Return: the regno of chosen register. */
10689 static unsigned int
10691 {
10695 {
10696 /* Use R13 for nested function or function need static chain.
10697 Since function with tail call may use any caller-saved
10698 registers in epilogue, DRAP must not use caller-saved
10699 register in such case. */
10704 }
10705 else
10706 {
10707 /* Use DI for nested function or function need static chain.
10708 Since function with tail call may use any caller-saved
10709 registers in epilogue, DRAP must not use caller-saved
10710 register in such case. */
10714 /* Reuse static chain register if it isn't used for parameter
10715 passing. */
10717 {
10721 }
10723 }
10724 }
10726 /* Return minimum incoming stack alignment. */
10728 static unsigned int
10730 {
10733 /* Prefer the one specified at command line. */
10736 /* In 32bit, use MIN_STACK_BOUNDARY for incoming stack boundary
10737 if -mstackrealign is used, it isn't used for sibcall check and
10738 estimated stack alignment is 128bit. */
10740 && !TARGET_64BIT
10741 && ix86_force_align_arg_pointer
10744 else
10747 /* Incoming stack alignment can be changed on individual functions
10748 via force_align_arg_pointer attribute. We use the smallest
10749 incoming stack boundary. */
10755 /* The incoming stack frame has to be aligned at least at
10756 parm_stack_boundary. */
10760 /* Stack at entrance of main is aligned by runtime. We use the
10761 smallest incoming stack boundary. */
10769 }
10771 /* Update incoming stack boundary and estimated stack alignment. */
10773 static void
10775 {
10776 ix86_incoming_stack_boundary
10779 /* x86_64 vararg needs 16byte stack alignment for register save
10780 area. */
10785 }
10787 /* Handle the TARGET_GET_DRAP_RTX hook. Return NULL if no DRAP is
10788 needed or an rtx for DRAP otherwise. */
10790 static rtx
10792 {
10797 {
10798 /* Assign DRAP to vDRAP and returns vDRAP */
10800 rtx drap_vreg;
10801 rtx arg_ptr;
10814 {
10817 }
10819 }
10820 else
10822 }
10824 /* Handle the TARGET_INTERNAL_ARG_POINTER hook. */
10826 static rtx
10828 {
10830 }
10833 rtx reg;
10835 };
10837 /* Return a short-lived scratch register for use on function entry.
10838 In 32-bit mode, it is valid only after the registers are saved
10839 in the prologue. This register must be released by means of
10840 release_scratch_register_on_entry once it is dead. */
10842 static void
10844 {
10850 {
10851 /* We always use R11 in 64-bit mode. */
10853 }
10854 else
10855 {
10857 bool fastcall_p
10859 bool thiscall_p
10863 int drap_regno
10866 /* 'fastcall' sets regparm to 2, uses ecx/edx for arguments and eax
10867 for the static chain register. */
10871 /* 'thiscall' sets regparm to 1, uses ecx for arguments and edx
10872 for the static chain register. */
10877 /* ecx is the static chain register. */
10879 && !static_chain_p
10884 /* esi is the static chain register. */
10890 else
10891 {
10894 }
10895 }
10899 {
10902 }
10903 }
10905 /* Release a scratch register obtained from the preceding function. */
10907 static void
10909 {
10911 {
10915 /* The RTX_FRAME_RELATED_P mechanism doesn't know about pop. */
10921 }
10922 }
10924 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
10926 /* Emit code to adjust the stack pointer by SIZE bytes while probing it. */
10928 static void
10930 {
10931 /* We skip the probe for the first interval + a small dope of 4 words and
10932 probe that many bytes past the specified size to maintain a protection
10933 area at the botton of the stack. */
10937 /* See if we have a constant small number of probes to generate. If so,
10938 that's the easy case. The run-time loop is made up of 11 insns in the
10939 generic case while the compile-time loop is made up of 3+2*(n-1) insns
10940 for n # of intervals. */
10942 {
10946 /* Adjust SP and probe at PROBE_INTERVAL + N * PROBE_INTERVAL for
10947 values of N from 1 until it exceeds SIZE. If only one probe is
10948 needed, this will not generate any code. Then adjust and probe
10949 to PROBE_INTERVAL + SIZE. */
10951 {
10953 {
10956 }
10957 else
10964 }
10968 else
10976 /* Adjust back to account for the additional first interval. */
10980 }
10982 /* Otherwise, do the same as above, but in a loop. Note that we must be
10983 extra careful with variables wrapping around because we might be at
10984 the very top (or the very bottom) of the address space and we have
10985 to be able to handle this case properly; in particular, we use an
10986 equality test for the loop condition. */
10987 else
10988 {
10989 HOST_WIDE_INT rounded_size;
10995 /* Step 1: round SIZE to the previous multiple of the interval. */
11000 /* Step 2: compute initial and final value of the loop counter. */
11002 /* SP = SP_0 + PROBE_INTERVAL. */
11007 /* LAST_ADDR = SP_0 + PROBE_INTERVAL + ROUNDED_SIZE. */
11011 stack_pointer_rtx)));
11014 /* Step 3: the loop
11016 while (SP != LAST_ADDR)
11017 {
11018 SP = SP + PROBE_INTERVAL
11019 probe at SP
11020 }
11022 adjusts SP and probes to PROBE_INTERVAL + N * PROBE_INTERVAL for
11023 values of N from 1 until it is equal to ROUNDED_SIZE. */
11028 /* Step 4: adjust SP and probe at PROBE_INTERVAL + SIZE if we cannot
11029 assert at compile-time that SIZE is equal to ROUNDED_SIZE. */
11032 {
11037 }
11039 /* Adjust back to account for the additional first interval. */
11045 }
11049 /* Even if the stack pointer isn't the CFA register, we need to correctly
11050 describe the adjustments made to it, in particular differentiate the
11051 frame-related ones from the frame-unrelated ones. */
11053 {
11066 }
11068 /* Make sure nothing is scheduled before we are done. */
11070 }
11072 /* Adjust the stack pointer up to REG while probing it. */
11076 {
11086 /* Jump to END_LAB if SP == LAST_ADDR. */
11094 /* SP = SP + PROBE_INTERVAL. */
11098 /* Probe at SP. */
11109 }
11111 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE,
11112 inclusive. These are offsets from the current stack pointer. */
11114 static void
11116 {
11117 /* See if we have a constant small number of probes to generate. If so,
11118 that's the easy case. The run-time loop is made up of 7 insns in the
11119 generic case while the compile-time loop is made up of n insns for n #
11120 of intervals. */
11122 {
11123 HOST_WIDE_INT i;
11125 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 1 until
11126 it exceeds SIZE. If only one probe is needed, this will not
11127 generate any code. Then probe at FIRST + SIZE. */
11134 }
11136 /* Otherwise, do the same as above, but in a loop. Note that we must be
11137 extra careful with variables wrapping around because we might be at
11138 the very top (or the very bottom) of the address space and we have
11139 to be able to handle this case properly; in particular, we use an
11140 equality test for the loop condition. */
11141 else
11142 {
11149 /* Step 1: round SIZE to the previous multiple of the interval. */
11154 /* Step 2: compute initial and final value of the loop counter. */
11156 /* TEST_OFFSET = FIRST. */
11159 /* LAST_OFFSET = FIRST + ROUNDED_SIZE. */
11163 /* Step 3: the loop
11165 while (TEST_ADDR != LAST_ADDR)
11166 {
11167 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
11168 probe at TEST_ADDR
11169 }
11171 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
11172 until it is equal to ROUNDED_SIZE. */
11177 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
11178 that SIZE is equal to ROUNDED_SIZE. */
11183 stack_pointer_rtx,
11188 }
11190 /* Make sure nothing is scheduled before we are done. */
11192 }
11194 /* Probe a range of stack addresses from REG to END, inclusive. These are
11195 offsets from the current stack pointer. */
11199 {
11209 /* Jump to END_LAB if TEST_ADDR == LAST_ADDR. */
11217 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
11221 /* Probe at TEST_ADDR. */
11234 }
11236 /* Finalize stack_realign_needed flag, which will guide prologue/epilogue
11237 to be generated in correct form. */
11238 static void
11240 {
11241 /* Check if stack realign is really needed after reload, and
11242 stores result in cfun */
11243 unsigned int incoming_stack_boundary
11252 {
11253 /* After stack_realign_needed is finalized, we can't no longer
11254 change it. */
11257 }
11259 /* If the only reason for frame_pointer_needed is that we conservatively
11260 assumed stack realignment might be needed, but in the end nothing that
11261 needed the stack alignment had been spilled, clear frame_pointer_needed
11262 and say we don't need stack realignment. */
11264 && frame_pointer_needed
11266 && flag_omit_frame_pointer
11268 && !ix86_current_function_calls_tls_descriptor
11277 {
11279 basic_block bb;
11286 HARD_FRAME_POINTER_REGNUM);
11288 {
11293 set_up_by_prologue))
11294 {
11298 }
11299 }
11301 /* If drap has been set, but it actually isn't live at the start
11302 of the function, there is no reason to set it up. */
11304 {
11307 {
11310 }
11311 }
11312 else
11327 }
11331 }
11333 /* Delete SET_GOT right after entry block if it is allocated to reg. */
11335 static void
11337 {
11343 {
11346 {
11352 }
11353 }
11354 }
11356 /* Expand the prologue into a bunch of separate insns. */
11358 void
11360 {
11364 HOST_WIDE_INT allocate;
11370 /* DRAP should not coexist with stack_realign_fp */
11375 /* Initialize CFA state for before the prologue. */
11379 /* Track SP offset to the CFA. We continue tracking this after we've
11380 swapped the CFA register away from SP. In the case of re-alignment
11381 this is fudged; we're interested to offsets within the local frame. */
11388 {
11389 /* We should have already generated an error for any use of
11390 ms_hook on a nested function. */
11393 /* Check if profiling is active and we shall use profiling before
11394 prologue variant. If so sorry. */
11399 /* In ix86_asm_output_function_label we emitted:
11400 8b ff movl.s %edi,%edi
11401 55 push %ebp
11402 8b ec movl.s %esp,%ebp
11404 This matches the hookable function prologue in Win32 API
11405 functions in Microsoft Windows XP Service Pack 2 and newer.
11406 Wine uses this to enable Windows apps to hook the Win32 API
11407 functions provided by Wine.
11409 What that means is that we've already set up the frame pointer. */
11413 {
11416 /* We've decided to use the frame pointer already set up.
11417 Describe this to the unwinder by pretending that both
11418 push and mov insns happen right here.
11420 Putting the unwind info here at the end of the ms_hook
11421 is done so that we can make absolutely certain we get
11422 the required byte sequence at the start of the function,
11423 rather than relying on an assembler that can produce
11424 the exact encoding required.
11426 However it does mean (in the unpatched case) that we have
11427 a 1 insn window where the asynchronous unwind info is
11428 incorrect. However, if we placed the unwind info at
11429 its correct location we would have incorrect unwind info
11430 in the patched case. Which is probably all moot since
11431 I don't expect Wine generates dwarf2 unwind info for the
11432 system libraries that use this feature. */
11438 stack_pointer_rtx);
11446 /* Note that gen_push incremented m->fs.cfa_offset, even
11447 though we didn't emit the push insn here. */
11451 }
11452 else
11453 {
11454 /* The frame pointer is not needed so pop %ebp again.
11455 This leaves us with a pristine state. */
11457 }
11458 }
11460 /* The first insn of a function that accepts its static chain on the
11461 stack is to push the register that would be filled in by a direct
11462 call. This insn will be skipped by the trampoline. */
11464 {
11468 /* We don't want to interpret this push insn as a register save,
11469 only as a stack adjustment. The real copy of the register as
11470 a save will be done later, if needed. */
11475 }
11477 /* Emit prologue code to adjust stack alignment and setup DRAP, in case
11478 of DRAP is needed and stack realignment is really needed after reload */
11480 {
11483 /* Only need to push parameter pointer reg if it is caller saved. */
11485 {
11486 /* Push arg pointer reg */
11489 }
11491 /* Grab the argument pointer. */
11498 /* Align the stack. */
11500 stack_pointer_rtx,
11504 /* Replicate the return address on the stack so that return
11505 address can be reached via (argp - 1) slot. This is needed
11506 to implement macro RETURN_ADDR_RTX and intrinsic function
11507 expand_builtin_return_addr etc. */
11513 /* For the purposes of frame and register save area addressing,
11514 we've started over with a new frame. */
11517 }
11523 {
11524 /* Note: AT&T enter does NOT have reversed args. Enter is probably
11525 slower on all targets. Also sdb doesn't like it. */
11529 /* Push registers now, before setting the frame pointer
11530 on SEH target. */
11532 && TARGET_SEH
11534 {
11538 }
11541 {
11549 }
11550 }
11553 {
11554 /* If saving registers via PUSH, do so now. */
11556 {
11560 }
11562 /* When using red zone we may start register saving before allocating
11563 the stack frame saving one cycle of the prologue. However, avoid
11564 doing this if we have to probe the stack; at least on x86_64 the
11565 stack probe can turn into a call that clobbers a red zone location. */
11567 && (! TARGET_STACK_PROBE
11569 {
11572 }
11573 }
11576 {
11580 /* The computation of the size of the re-aligned stack frame means
11581 that we must allocate the size of the register save area before
11582 performing the actual alignment. Otherwise we cannot guarantee
11583 that there's enough storage above the realignment point. */
11590 /* Align the stack. */
11592 stack_pointer_rtx,
11595 /* For the purposes of register save area addressing, the stack
11596 pointer is no longer valid. As for the value of sp_offset,
11597 see ix86_compute_frame_layout, which we need to match in order
11598 to pass verification of stack_pointer_offset at the end. */
11601 }
11606 {
11607 /* We start to count from ARG_POINTER. */
11610 /* If it was realigned, take into account the fake frame. */
11612 {
11619 /* This over-estimates by 1 minimal-stack-alignment-unit but
11620 mitigates that by counting in the new return address slot. */
11621 current_function_dynamic_stack_size
11623 }
11626 }
11628 /* On SEH target with very large frame size, allocate an area to save
11629 SSE registers (as the very large allocation won't be described). */
11633 {
11634 HOST_WIDE_INT sse_size =
11639 /* No need to do stack checking as the area will be immediately
11640 written. */
11647 }
11649 /* The stack has already been decremented by the instruction calling us
11650 so probe if the size is non-negative to preserve the protection area. */
11652 {
11653 /* We expect the registers to be saved when probes are used. */
11657 {
11660 {
11663 }
11664 }
11665 else
11666 {
11673 {
11675 {
11678 }
11679 else
11681 }
11682 else
11683 {
11685 {
11689 }
11690 else
11692 }
11693 }
11694 }
11697 ;
11700 {
11704 }
11705 else
11706 {
11718 {
11721 /* Note that SEH directives need to continue tracking the stack
11722 pointer even after the frame pointer has been set up. */
11724 {
11732 }
11733 }
11736 {
11741 {
11749 }
11750 }
11755 /* Use the fact that AX still contains ALLOCATE. */
11757 ? gen_pro_epilogue_adjust_stack_di_sub
11764 {
11772 }
11775 /* Use stack_pointer_rtx for relative addressing so that code
11776 works for realigned stack, too. */
11778 {
11785 }
11787 {
11792 }
11793 }
11796 /* If we havn't already set up the frame pointer, do so now. */
11798 {
11810 }
11817 /* For the mcount profiling on 32 bit PIC mode we need to emit SET_GOT
11818 in PROLOGUE. */
11820 {
11826 /* Deleting already emmitted SET_GOT if exist and allocated to
11827 REAL_PIC_OFFSET_TABLE_REGNUM. */
11829 }
11832 {
11833 /* vDRAP is setup but after reload it turns out stack realign
11834 isn't necessary, here we will emit prologue to setup DRAP
11835 without stack realign adjustment */
11838 }
11840 /* Prevent instructions from being scheduled into register save push
11841 sequence when access to the redzone area is done through frame pointer.
11842 The offset between the frame pointer and the stack pointer is calculated
11843 relative to the value of the stack pointer at the end of the function
11844 prologue, and moving instructions that access redzone area via frame
11845 pointer inside push sequence violates this assumption. */
11849 /* Emit cld instruction if stringops are used in the function. */
11853 /* SEH requires that the prologue end within 256 bytes of the start of
11854 the function. Prevent instruction schedules that would extend that.
11855 Further, prevent alloca modifications to the stack pointer from being
11856 combined with prologue modifications. */
11859 }
11861 /* Emit code to restore REG using a POP insn. */
11863 static void
11865 {
11874 {
11875 /* Previously we'd represented the CFA as an expression
11876 like *(%ebp - 8). We've just popped that value from
11877 the stack, which means we need to reset the CFA to
11878 the drap register. This will remain until we restore
11879 the stack pointer. */
11883 /* This means that the DRAP register is valid for addressing too. */
11886 }
11889 {
11896 }
11898 /* When the frame pointer is the CFA, and we pop it, we are
11899 swapping back to the stack pointer as the CFA. This happens
11900 for stack frames that don't allocate other data, so we assume
11901 the stack pointer is now pointing at the return address, i.e.
11902 the function entry state, which makes the offset be 1 word. */
11904 {
11907 {
11915 }
11916 }
11917 }
11919 /* Emit code to restore saved registers using POP insns. */
11921 static void
11923 {
11929 }
11931 /* Emit code and notes for the LEAVE instruction. */
11933 static void
11935 {
11947 {
11955 }
11958 }
11960 /* Emit code to restore saved registers using MOV insns.
11961 First register is restored from CFA - CFA_OFFSET. */
11962 static void
11965 {
11971 {
11973 rtx mem;
11981 {
11982 /* Previously we'd represented the CFA as an expression
11983 like *(%ebp - 8). We've just popped that value from
11984 the stack, which means we need to reset the CFA to
11985 the drap register. This will remain until we restore
11986 the stack pointer. */
11990 /* This means that the DRAP register is valid for addressing. */
11992 }
11993 else
11997 }
11998 }
12000 /* Emit code to restore saved registers using MOV insns.
12001 First register is restored from CFA - CFA_OFFSET. */
12002 static void
12005 {
12010 {
12012 rtx mem;
12022 }
12023 }
12025 /* Restore function stack, frame, and registers. */
12027 void
12029 {
12045 /* The FP must be valid if the frame pointer is present. */
12050 /* We must have *some* valid pointer to the stack frame. */
12053 /* The DRAP is never valid at this point. */
12056 /* See the comment about red zone and frame
12057 pointer usage in ix86_expand_prologue. */
12064 /* Determine the CFA offset of the end of the red-zone. */
12067 {
12068 /* The red-zone begins below the return address. */
12071 /* When the register save area is in the aligned portion of
12072 the stack, determine the maximum runtime displacement that
12073 matches up with the aligned frame. */
12077 }
12079 /* Special care must be taken for the normal return case of a function
12080 using eh_return: the eax and edx registers are marked as saved, but
12081 not restored along this path. Adjust the save location to match. */
12085 /* EH_RETURN requires the use of moves to function properly. */
12088 /* SEH requires the use of pops to identify the epilogue. */
12091 /* If we're only restoring one register and sp is not valid then
12092 using a move instruction to restore the register since it's
12093 less work than reloading sp and popping the register. */
12106 && TARGET_USE_LEAVE
12110 else
12114 {
12115 /* Ensure that the entire register save area is addressable via
12116 the stack pointer, if we will restore via sp. */
12121 {
12125 style,
12127 }
12128 }
12130 /* If there are any SSE registers to restore, then we have to do it
12131 via moves, since there's obviously no pop for SSE regs. */
12137 {
12138 rtx t;
12143 /* eh_return epilogues need %ecx added to the stack pointer. */
12145 {
12149 /* Stack align doesn't work with eh_return. */
12151 /* Neither does regparm nested functions. */
12155 {
12163 /* Note that we use SA as a temporary CFA, as the return
12164 address is at the proper place relative to it. We
12165 pretend this happens at the FP restore insn because
12166 prior to this insn the FP would be stored at the wrong
12167 offset relative to SA, and after this insn we have no
12168 other reasonable register to use for the CFA. We don't
12169 bother resetting the CFA to the SP for the duration of
12170 the return insn. */
12183 }
12184 else
12185 {
12193 {
12197 UNITS_PER_WORD));
12199 }
12200 }
12203 }
12204 }
12205 else
12206 {
12207 /* SEH requires that the function end with (1) a stack adjustment
12208 if necessary, (2) a sequence of pops, and (3) a return or
12209 jump instruction. Prevent insns from the function body from
12210 being scheduled into this sequence. */
12212 {
12213 /* Prevent a catch region from being adjacent to the standard
12214 epilogue sequence. Unfortuantely crtl->uses_eh_lsda nor
12215 several other flags that would be interesting to test are
12216 not yet set up. */
12219 else
12221 }
12223 /* First step is to deallocate the stack frame so that we can
12224 pop the registers. Also do it on SEH target for very large
12225 frame as the emitted instructions aren't allowed by the ABI in
12226 epilogues. */
12228 || (TARGET_SEH
12231 {
12236 }
12238 {
12242 style,
12244 }
12247 }
12249 /* If we used a stack pointer and haven't already got rid of it,
12250 then do so now. */
12252 {
12253 /* If the stack pointer is valid and pointing at the frame
12254 pointer store address, then we only need a pop. */
12257 /* Leave results in shorter dependency chains on CPUs that are
12258 able to grok it fast. */
12263 else
12264 {
12266 hard_frame_pointer_rtx,
12269 }
12270 }
12273 {
12301 }
12303 /* At this point the stack pointer must be valid, and we must have
12304 restored all of the registers. We may not have deallocated the
12305 entire stack frame. We've delayed this until now because it may
12306 be possible to merge the local stack deallocation with the
12307 deallocation forced by ix86_static_chain_on_stack. */
12312 {
12316 }
12317 else
12320 /* Sibcall epilogues don't want a return instruction. */
12322 {
12325 }
12328 {
12331 /* i386 can only pop 64K bytes. If asked to pop more, pop return
12332 address, do explicit add, and jump indirectly to the caller. */
12335 {
12339 /* There is no "pascal" calling convention in any 64bit ABI. */
12355 }
12356 else
12358 }
12359 else
12362 /* Restore the state back to the state from the prologue,
12363 so that it's correct for the next epilogue. */
12365 }
12367 /* Reset from the function's potential modifications. */
12369 static void
12371 {
12375 #if TARGET_MACHO
12376 /* Mach-O doesn't support labels at the end of objects, so if
12377 it looks like we might want one, insert a NOP. */
12378 {
12384 {
12385 /* Don't insert a nop for NOTE_INSN_DELETED_DEBUG_LABEL
12386 notes only, instead set their CODE_LABEL_NUMBER to -1,
12387 otherwise there would be code generation differences
12388 in between -g and -g0. */
12392 }
12402 }
12403 #endif
12405 }
12407 /* Return a scratch register to use in the split stack prologue. The
12408 split stack prologue is used for -fsplit-stack. It is the first
12409 instructions in the function, even before the regular prologue.
12410 The scratch register can be any caller-saved register which is not
12411 used for parameters or for the static chain. */
12413 static unsigned int
12415 {
12418 else
12419 {
12432 {
12434 {
12438 }
12440 }
12442 {
12446 }
12448 {
12451 else
12452 {
12454 {
12458 }
12460 }
12461 }
12462 else
12463 {
12464 /* FIXME: We could make this work by pushing a register
12465 around the addition and comparison. */
12468 }
12469 }
12470 }
12472 /* A SYMBOL_REF for the function which allocates new stackspace for
12473 -fsplit-stack. */
12477 /* A SYMBOL_REF for the more stack function when using the large
12478 model. */
12482 /* Handle -fsplit-stack. These are the first instructions in the
12483 function, even before the regular prologue. */
12485 void
12487 {
12489 HOST_WIDE_INT allocate;
12495 rtx fn;
12503 /* This is the label we will branch to if we have enough stack
12504 space. We expect the basic block reordering pass to reverse this
12505 branch if optimizing, so that we branch in the unlikely case. */
12508 /* We need to compare the stack pointer minus the frame size with
12509 the stack boundary in the TCB. The stack boundary always gives
12510 us SPLIT_STACK_AVAILABLE bytes, so if we need less than that we
12511 can compare directly. Otherwise we need to do an addition. */
12514 UNSPEC_STACK_CHECK);
12519 else
12520 {
12522 rtx offset;
12524 /* We need a scratch register to hold the stack pointer minus
12525 the required frame size. Since this is the very start of the
12526 function, the scratch register can be any caller-saved
12527 register which is not used for parameters. */
12534 {
12535 /* We don't use ix86_gen_add3 in this case because it will
12536 want to split to lea, but when not optimizing the insn
12537 will not be split after this point. */
12540 offset)));
12541 }
12542 else
12543 {
12546 stack_pointer_rtx));
12547 }
12549 }
12555 /* Mark the jump as very likely to be taken. */
12560 {
12563 }
12566 /* Get more stack space. We pass in the desired stack space and the
12567 size of the arguments to copy to the new stack. In 32-bit mode
12568 we push the parameters; __morestack will return on a new stack
12569 anyhow. In 64-bit mode we pass the parameters in r10 and
12570 r11. */
12575 {
12581 /* If this function uses a static chain, it will be in %r10.
12582 Preserve it across the call to __morestack. */
12584 {
12585 rtx rax;
12590 }
12594 {
12595 HOST_WIDE_INT argval;
12598 /* When using the large model we need to load the address
12599 into a register, and we've run out of registers. So we
12600 switch to a different calling convention, and we call a
12601 different function: __morestack_large. We pass the
12602 argument size in the upper 32 bits of r10 and pass the
12603 frame size in the lower 32 bits. */
12608 {
12609 split_stack_fn_large =
12612 }
12614 {
12616 rtx x;
12625 UNSPEC_GOT);
12631 }
12632 else
12639 }
12640 else
12641 {
12645 }
12648 }
12649 else
12650 {
12653 }
12659 /* In order to make call/return prediction work right, we now need
12660 to execute a return instruction. See
12661 libgcc/config/i386/morestack.S for the details on how this works.
12663 For flow purposes gcc must not see this as a return
12664 instruction--we need control flow to continue at the subsequent
12665 label. Therefore, we use an unspec. */
12669 /* If we are in 64-bit mode and this function uses a static chain,
12670 we saved %r10 in %rax before calling _morestack. */
12675 /* If this function calls va_start, we need to store a pointer to
12676 the arguments on the old stack, because they may not have been
12677 all copied to the new stack. At this point the old stack can be
12678 found at the frame pointer value used by __morestack, because
12679 __morestack has set that up before calling back to us. Here we
12680 store that pointer in a scratch register, and in
12681 ix86_expand_prologue we store the scratch register in a stack
12682 slot. */
12684 {
12686 rtx frame_reg;
12693 /* 64-bit:
12694 fp -> old fp value
12695 return address within this function
12696 return address of caller of this function
12697 stack arguments
12698 So we add three words to get to the stack arguments.
12700 32-bit:
12701 fp -> old fp value
12702 return address within this function
12703 first argument to __morestack
12704 second argument to __morestack
12705 return address of caller of this function
12706 stack arguments
12707 So we add five words to get to the stack arguments.
12708 */
12719 }
12724 /* If this function calls va_start, we now have to set the scratch
12725 register for the case where we do not call __morestack. In this
12726 case we need to set it based on the stack pointer. */
12728 {
12735 }
12736 }
12738 /* We may have to tell the dataflow pass that the split stack prologue
12739 is initializing a scratch register. */
12741 static void
12743 {
12745 {
12748 }
12749 }
12750 \f
12751 /* Extract the parts of an RTL expression that is a valid memory address
12752 for an instruction. Return 0 if the structure of the address is
12753 grossly off. Return -1 if the address contains ASHIFT, so it is not
12754 strictly valid, but still used for computing length of lea instruction. */
12756 int
12758 {
12763 rtx tmp;
12767 /* Allow zero-extended SImode addresses,
12768 they will be emitted with addr32 prefix. */
12770 {
12773 {
12777 }
12780 {
12787 }
12788 }
12790 /* Allow SImode subregs of DImode addresses,
12791 they will be emitted with addr32 prefix. */
12793 {
12796 {
12800 }
12801 }
12806 {
12809 else
12811 }
12813 {
12818 do
12819 {
12824 }
12831 {
12834 {
12859 /* FALLTHRU */
12863 && TARGET_TLS_DIRECT_SEG_REFS
12866 else
12873 /* FALLTHRU */
12880 else
12895 }
12896 }
12897 }
12899 {
12902 }
12904 {
12905 /* We're called for lea too, which implements ashift on occasion. */
12915 }
12916 else
12920 {
12922 ;
12925 ;
12926 else
12928 }
12930 /* Extract the integral value of scale. */
12932 {
12936 }
12941 /* Avoid useless 0 displacement. */
12945 /* Allow arg pointer and stack pointer as index if there is not scaling. */
12950 {
12953 }
12955 /* Special case: %ebp cannot be encoded as a base without a displacement.
12956 Similarly %r13. */
12958 && base_reg
12967 /* Special case: on K6, [%esi] makes the instruction vector decoded.
12968 Avoid this by transforming to [%esi+0].
12969 Reload calls address legitimization without cfun defined, so we need
12970 to test cfun for being non-NULL. */
12976 /* Special case: encode reg+reg instead of reg*2. */
12980 /* Special case: scaling cannot be encoded without base or displacement. */
12991 }
12992 \f
12993 /* Return cost of the memory address x.
12994 For i386, it is better to use a complex address than let gcc copy
12995 the address into a reg and make a new pseudo. But not if the address
12996 requires to two regs - that would mean more pseudos with longer
12997 lifetimes. */
12998 static int
13000 {
13012 /* Attempt to minimize number of registers in the address by increasing
13013 address cost for each used register. We don't increase address cost
13014 for "pic_offset_table_rtx". When a memopt with "pic_offset_table_rtx"
13015 is not invariant itself it most likely means that base or index is not
13016 invariant. Therefore only "pic_offset_table_rtx" could be hoisted out,
13017 which is not profitable for x86. */
13021 || !pic_offset_table_rtx
13024 cost++;
13029 || !pic_offset_table_rtx
13032 cost++;
13034 /* AMD-K6 don't like addresses with ModR/M set to 00_xxx_100b,
13035 since it's predecode logic can't detect the length of instructions
13036 and it degenerates to vector decoded. Increase cost of such
13037 addresses here. The penalty is minimally 2 cycles. It may be worthwhile
13038 to split such addresses or even refuse such addresses at all.
13040 Following addressing modes are affected:
13041 [base+scale*index]
13042 [scale*index+disp]
13043 [base+index]
13045 The first and last case may be avoidable by explicitly coding the zero in
13046 memory address, but I don't have AMD-K6 machine handy to check this
13047 theory. */
13056 }
13057 \f
13058 /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as
13059 this is used for to form addresses to local data when -fPIC is in
13060 use. */
13062 static bool
13064 {
13067 }
13069 /* Determine if a given RTX is a valid constant. We already know this
13070 satisfies CONSTANT_P. */
13072 static bool
13074 {
13075 /* Pointer bounds constants are not valid. */
13080 {
13085 {
13089 }
13094 /* Only some unspecs are valid as "constants". */
13097 {
13113 }
13115 /* We must have drilled down to a symbol. */
13120 /* FALLTHRU */
13123 /* TLS symbols are never valid. */
13127 /* DLLIMPORT symbols are never valid. */
13132 #if TARGET_MACHO
13133 /* mdynamic-no-pic */
13136 #endif
13150 }
13152 /* Otherwise we handle everything else in the move patterns. */
13154 }
13156 /* Determine if it's legal to put X into the constant pool. This
13157 is not possible for the address of thread-local symbols, which
13158 is checked above. */
13160 static bool
13162 {
13163 /* We can always put integral constants and vectors in memory. */
13165 {
13174 }
13176 }
13178 /* Nonzero if the symbol is marked as dllimport, or as stub-variable,
13179 otherwise zero. */
13181 static bool
13183 {
13189 }
13192 /* Nonzero if the constant value X is a legitimate general operand
13193 when generating PIC code. It is given that flag_pic is on and
13194 that X satisfies CONSTANT_P. */
13196 bool
13198 {
13199 rtx inner;
13202 {
13209 /* Only some unspecs are valid as "constants". */
13212 {
13225 }
13226 /* FALLTHRU */
13234 }
13235 }
13237 /* Determine if a given CONST RTX is a valid memory displacement
13238 in PIC mode. */
13240 bool
13242 {
13245 /* In 64bit mode we can allow direct addresses of symbols and labels
13246 when they are not dynamic symbols. */
13248 {
13252 {
13276 /* FALLTHRU */
13279 /* TLS references should always be enclosed in UNSPEC.
13280 The dllimported symbol needs always to be resolved. */
13286 {
13294 /* Function-symbols need to be resolved only for
13295 large-model.
13296 For the small-model we don't need to resolve anything
13297 here. */
13302 /* Non-external symbols don't need to be resolved for
13303 large, and medium-model. */
13308 }
13311 || (HAVE_LD_PIE_COPYRELOC
13312 && flag_pie
13321 }
13322 }
13328 {
13329 /* We are unsafe to allow PLUS expressions. This limit allowed distance
13330 of GOT tables. We should not need these anyway. */
13342 }
13346 {
13351 }
13360 {
13364 /* We need to check for both symbols and labels because VxWorks loads
13365 text labels with @GOT rather than @GOTOFF. See gotoff_operand for
13366 details. */
13370 /* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
13371 While ABI specify also 32bit relocation but we don't produce it in
13372 small PIC model at all. */
13394 }
13397 }
13399 /* Determine if op is suitable RTX for an address register.
13400 Return naked register if a register or a register subreg is
13401 found, otherwise return NULL_RTX. */
13403 static rtx
13405 {
13408 /* Only SImode or DImode registers can form the address. */
13415 {
13423 /* Don't allow SUBREGs that span more than a word. It can
13424 lead to spill failures when the register is one word out
13425 of a two word structure. */
13429 /* Allow only SUBREGs of non-eliminable hard registers. */
13432 }
13434 /* Op is not a register. */
13436 }
13438 /* Recognizes RTL expressions that are valid memory addresses for an
13439 instruction. The MODE argument is the machine mode for the MEM
13440 expression that wants to use this address.
13442 It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should
13443 convert common non-canonical forms to canonical form so that they will
13444 be recognized. */
13446 static bool
13448 {
13451 HOST_WIDE_INT scale;
13455 /* Decomposition failed. */
13464 /* Validate base register. */
13466 {
13474 /* Base is not valid. */
13476 }
13478 /* Validate index register. */
13480 {
13488 /* Index is not valid. */
13490 }
13492 /* Index and base should have the same mode. */
13497 /* Address override works only on the (%reg) part of %fs:(%reg). */
13503 /* Validate scale factor. */
13505 {
13507 /* Scale without index. */
13511 /* Scale is not a valid multiplier. */
13513 }
13515 /* Validate displacement. */
13517 {
13522 {
13523 /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when
13524 used. While ABI specify also 32bit relocations, we don't produce
13525 them at all and use IP relative instead. */
13532 /* 64bit address unspec. */
13552 /* Invalid address unspec. */
13554 }
13557 && (flag_pic
13558 || (TARGET_MACHO
13559 #if TARGET_MACHO
13560 && MACHOPIC_INDIRECT
13562 #endif
13563 )))
13564 {
13566 is_legitimate_pic:
13568 {
13569 /* foo@dtpoff(%rX) is ok. */
13576 /* Non-constant pic memory reference. */
13578 }
13581 /* Displacement is an invalid pic construct. */
13583 #if TARGET_MACHO
13586 /* displacment must be referenced via non_lazy_pointer */
13588 #endif
13590 /* This code used to verify that a symbolic pic displacement
13591 includes the pic_offset_table_rtx register.
13593 While this is good idea, unfortunately these constructs may
13594 be created by "adds using lea" optimization for incorrect
13595 code like:
13597 int a;
13598 int foo(int i)
13599 {
13600 return *(&a+i);
13601 }
13603 This code is nonsensical, but results in addressing
13604 GOT table with pic_offset_table_rtx base. We can't
13605 just refuse it easily, since it gets matched by
13606 "addsi3" pattern, that later gets split to lea in the
13607 case output register differs from input. While this
13608 can be handled by separate addsi pattern for this case
13609 that never results in lea, this seems to be easier and
13610 correct fix for crash to disable this test. */
13611 }
13618 /* Displacement is not constant. */
13622 /* Displacement is out of range. */
13624 /* In x32 mode, constant addresses are sign extended to 64bit, so
13625 we have to prevent addresses from 0x80000000 to 0xffffffff. */
13630 }
13632 /* Everything looks valid. */
13634 }
13636 /* Determine if a given RTX is a valid constant address. */
13638 bool
13640 {
13642 }
13643 \f
13644 /* Return a unique alias set for the GOT. */
13646 static alias_set_type
13648 {
13653 }
13655 /* Return a legitimate reference for ORIG (an address) using the
13656 register REG. If REG is 0, a new pseudo is generated.
13658 There are two types of references that must be handled:
13660 1. Global data references must load the address from the GOT, via
13661 the PIC reg. An insn is emitted to do this load, and the reg is
13662 returned.
13664 2. Static data references, constant pool addresses, and code labels
13665 compute the address as an offset from the GOT, whose base is in
13666 the PIC reg. Static data objects have SYMBOL_FLAG_LOCAL set to
13667 differentiate them from global data objects. The returned
13668 address is the PIC reg + an unspec constant.
13670 TARGET_LEGITIMATE_ADDRESS_P rejects symbolic references unless the PIC
13671 reg also appears in the address. */
13673 static rtx
13675 {
13679 #if TARGET_MACHO
13681 {
13684 /* Use the generic Mach-O PIC machinery. */
13686 }
13687 #endif
13690 {
13694 }
13700 {
13701 rtx tmpreg;
13702 /* This symbol may be referenced via a displacement from the PIC
13703 base address (@GOTOFF). */
13708 {
13710 UNSPEC_GOTOFF);
13712 }
13713 else
13718 else
13723 {
13727 }
13728 else
13730 }
13732 {
13733 /* This symbol may be referenced via a displacement from the PIC
13734 base address (@GOTOFF). */
13739 {
13741 UNSPEC_GOTOFF);
13743 }
13744 else
13750 {
13753 }
13754 }
13756 /* We can't use @GOTOFF for text labels on VxWorks;
13757 see gotoff_operand. */
13759 {
13764 /* For x64 PE-COFF there is no GOT table. So we use address
13765 directly. */
13767 {
13775 }
13777 {
13785 /* Use directly gen_movsi, otherwise the address is loaded
13786 into register for CSE. We don't want to CSE this addresses,
13787 instead we CSE addresses from the GOT table, so skip this. */
13790 }
13791 else
13792 {
13793 /* This symbol must be referenced via a load from the
13794 Global Offset Table (@GOT). */
13808 }
13809 }
13810 else
13811 {
13814 {
13816 {
13819 }
13820 else
13822 }
13824 {
13827 /* We must match stuff we generate before. Assume the only
13828 unspecs that can get here are ours. Not that we could do
13829 anything with them anyway.... */
13835 }
13837 {
13840 /* Check first to see if this is a constant offset from a @GOTOFF
13841 symbol reference. */
13844 {
13846 {
13848 UNSPEC_GOTOFF);
13854 {
13857 }
13858 }
13859 else
13860 {
13863 {
13867 }
13868 }
13869 }
13870 else
13871 {
13874 new_rtx
13878 {
13881 {
13884 new_rtx
13886 }
13887 else
13889 }
13890 else
13891 {
13892 /* For %rip addressing, we have to use just disp32, not
13893 base nor index. */
13900 {
13903 }
13905 }
13906 }
13907 }
13908 }
13910 }
13911 \f
13912 /* Load the thread pointer. If TO_REG is true, force it into a register. */
13914 static rtx
13916 {
13920 {
13925 }
13931 }
13933 /* Construct the SYMBOL_REF for the tls_get_addr function. */
13937 static rtx
13939 {
13941 {
13947 }
13950 {
13952 UNSPEC_PLTOFF);
13955 }
13958 }
13960 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */
13964 rtx
13966 {
13968 {
13969 ix86_tls_module_base_symbol
13974 }
13977 }
13979 /* A subroutine of ix86_legitimize_address and ix86_expand_move. FOR_MOV is
13980 false if we expect this to be used for a memory address and true if
13981 we expect to load the address into a register. */
13983 static rtx
13985 {
13991 /* Fall back to global dynamic model if tool chain cannot support local
13992 dynamic. */
13999 {
14004 {
14007 else
14008 {
14011 }
14012 }
14015 {
14018 else
14028 }
14029 else
14030 {
14034 {
14039 emit_call_insn
14049 }
14050 else
14052 }
14059 {
14062 else
14063 {
14066 }
14067 }
14070 {
14075 else
14081 }
14082 else
14083 {
14087 {
14090 rtx eqv;
14093 emit_call_insn
14098 /* Attach a unique REG_EQUAL, to allow the RTL optimizers to
14099 share the LD_BASE result with other LD model accesses. */
14101 UNSPEC_TLS_LD_BASE);
14105 }
14106 else
14108 }
14116 {
14123 }
14128 {
14130 {
14131 /* The Sun linker took the AMD64 TLS spec literally
14132 and can only handle %rax as destination of the
14133 initial executable code sequence. */
14138 }
14140 /* Generate DImode references to avoid %fs:(%reg32)
14141 problems and linker IE->LE relaxation bug. */
14145 }
14147 {
14150 }
14152 {
14156 }
14157 else
14158 {
14161 }
14171 {
14176 }
14177 else
14178 {
14182 }
14192 {
14196 }
14197 else
14198 {
14202 }
14207 }
14210 }
14212 /* Create or return the unique __imp_DECL dllimport symbol corresponding
14213 to symbol DECL if BEIMPORT is true. Otherwise create or return the
14214 unique refptr-DECL symbol corresponding to symbol DECL. */
14217 {
14221 {
14223 }
14225 static int
14227 {
14229 }
14230 };
14234 static tree
14236 {
14242 tree to;
14243 rtx rtl;
14270 else
14283 {
14285 #ifdef SUB_TARGET_RECORD_STUB
14287 #endif
14288 }
14297 }
14299 /* Expand SYMBOL into its corresponding far-addresse symbol.
14300 WANT_REG is true if we require the result be a register. */
14302 static rtx
14304 {
14305 tree imp_decl;
14306 rtx x;
14315 }
14317 /* Expand SYMBOL into its corresponding dllimport symbol. WANT_REG is
14318 true if we require the result be a register. */
14320 static rtx
14322 {
14323 tree imp_decl;
14324 rtx x;
14333 }
14335 /* Expand SYMBOL into its corresponding dllimport or refptr symbol. WANT_REG
14336 is true if we require the result be a register. */
14338 static rtx
14340 {
14345 {
14352 {
14355 }
14356 }
14372 {
14375 }
14377 }
14379 /* Try machine-dependent ways of modifying an illegitimate address
14380 to be legitimate. If we find one, return the new, valid address.
14381 This macro is used in only one place: `memory_address' in explow.c.
14383 OLDX is the address as it was before break_out_memory_refs was called.
14384 In some cases it is useful to look at this to decide what needs to be done.
14386 It is always safe for this macro to do nothing. It exists to recognize
14387 opportunities to optimize the output.
14389 For the 80386, we handle X+REG by loading X into a register R and
14390 using R+REG. R will go in a general reg and indexing will be used.
14391 However, if REG is a broken-out memory address or multiplication,
14392 nothing needs to be done because REG can certainly go in a general reg.
14394 When -fpic is used, special handling is needed for symbolic references.
14395 See comments by legitimize_pic_address in i386.c for details. */
14397 static rtx
14399 {
14410 {
14414 }
14417 {
14421 }
14426 #if TARGET_MACHO
14429 #endif
14431 /* Canonicalize shifts by 0, 1, 2, 3 into multiply */
14435 {
14440 }
14443 {
14444 /* Canonicalize shifts by 0, 1, 2, 3 into multiply. */
14449 {
14455 }
14460 {
14466 }
14468 /* Put multiply first if it isn't already. */
14470 {
14473 }
14475 /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const)))
14476 into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be
14477 created by virtual register instantiation, register elimination, and
14478 similar optimizations. */
14480 {
14486 }
14488 /* Canonicalize
14489 (plus (plus (mult (reg) (const)) (plus (reg) (const))) const)
14490 into (plus (plus (mult (reg) (const)) (reg)) (const)). */
14495 {
14496 rtx constant;
14500 {
14503 }
14505 {
14508 }
14509 else
14513 {
14520 }
14521 }
14527 {
14530 }
14533 {
14536 }
14544 {
14547 }
14553 {
14557 {
14560 }
14564 }
14567 {
14571 {
14574 }
14578 }
14579 }
14582 }
14583 \f
14584 /* Print an integer constant expression in assembler syntax. Addition
14585 and subtraction are the only arithmetic that may appear in these
14586 expressions. FILE is the stdio stream to write to, X is the rtx, and
14587 CODE is the operand print code from the output string. */
14589 static void
14591 {
14595 {
14604 else
14605 {
14608 /* Mark the decl as referenced so that cgraph will
14609 output the function. */
14613 #if TARGET_MACHO
14617 #endif
14619 }
14627 /* FALLTHRU */
14638 /* This used to output parentheses around the expression,
14639 but that does not work on the 386 (either ATT or BSD assembler). */
14644 /* We can't handle floating point constants;
14645 TARGET_PRINT_OPERAND must handle them. */
14650 /* Some assemblers need integer constants to appear first. */
14652 {
14656 }
14657 else
14658 {
14663 }
14678 {
14682 }
14687 {
14706 /* FIXME: This might be @TPOFF in Sun ld too. */
14715 else
14725 else
14731 #if TARGET_MACHO
14736 #endif
14740 }
14745 }
14746 }
14748 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
14749 We need to emit DTP-relative relocations. */
14751 static void ATTRIBUTE_UNUSED
14753 {
14758 {
14766 }
14767 }
14769 /* Return true if X is a representation of the PIC register. This copes
14770 with calls from ix86_find_base_term, where the register might have
14771 been replaced by a cselib value. */
14773 static bool
14775 {
14782 {
14790 }
14791 else
14793 }
14795 /* Helper function for ix86_delegitimize_address.
14796 Attempt to delegitimize TLS local-exec accesses. */
14798 static rtx
14800 {
14825 {
14830 }
14836 }
14838 /* In the name of slightly smaller debug output, and to cater to
14839 general assembler lossage, recognize PIC+GOTOFF and turn it back
14840 into a direct symbol reference.
14842 On Darwin, this is necessary to avoid a crash, because Darwin
14843 has a different PIC label for each routine but the DWARF debugging
14844 information is not associated with any particular routine, so it's
14845 necessary to remove references to the PIC label from RTL stored by
14846 the DWARF output code. */
14848 static rtx
14850 {
14852 /* addend is NULL or some rtx if x is something+GOTOFF where
14853 something doesn't include the PIC register. */
14855 /* reg_addend is NULL or a multiple of some register. */
14857 /* const_addend is NULL or a const_int. */
14859 /* This is the result, or NULL. */
14868 {
14875 {
14881 }
14888 {
14891 {
14896 }
14898 }
14903 /* Fall thru into the code shared with -m32 for -mcmodel=large -fpic
14904 and -mcmodel=medium -fpic. */
14905 }
14912 /* %ebx + GOT/GOTOFF */
14913 ;
14915 {
14916 /* %ebx + %reg * scale + GOT/GOTOFF */
14922 else
14923 {
14926 }
14927 }
14928 else
14934 {
14937 }
14958 {
14959 /* If the rest of original X doesn't involve the PIC register, add
14960 addend and subtract pic_offset_table_rtx. This can happen e.g.
14961 for code like:
14962 leal (%ebx, %ecx, 4), %ecx
14963 ...
14964 movl foo@GOTOFF(%ecx), %edx
14965 in which case we return (%ecx - %ebx) + foo
14966 or (%ecx - _GLOBAL_OFFSET_TABLE_) + foo if pseudo_pic_reg
14967 and reload has completed. */
14971 pic_offset_table_rtx),
14972 result);
14974 {
14978 }
14979 else
14981 }
14983 {
14987 }
14989 }
14991 /* If X is a machine specific address (i.e. a symbol or label being
14992 referenced as a displacement from the GOT implemented using an
14993 UNSPEC), then return the base term. Otherwise return X. */
14995 rtx
14997 {
14998 rtx term;
15001 {
15014 }
15017 }
15018 \f
15019 static void
15022 {
15026 {
15029 }
15034 {
15037 {
15056 }
15060 {
15079 }
15086 /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers.
15087 Those same assemblers have the same but opposite lossage on cmov. */
15090 else
15095 {
15108 }
15115 else
15120 {
15133 }
15140 else
15150 else
15161 }
15163 }
15165 /* Print the name of register X to FILE based on its machine mode and number.
15166 If CODE is 'w', pretend the mode is HImode.
15167 If CODE is 'b', pretend the mode is QImode.
15168 If CODE is 'k', pretend the mode is SImode.
15169 If CODE is 'q', pretend the mode is DImode.
15170 If CODE is 'x', pretend the mode is V4SFmode.
15171 If CODE is 't', pretend the mode is V8SFmode.
15172 If CODE is 'g', pretend the mode is V16SFmode.
15173 If CODE is 'h', pretend the reg is the 'high' byte register.
15174 If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
15175 If CODE is 'd', duplicate the operand for AVX instruction.
15176 */
15178 void
15180 {
15190 {
15194 }
15197 {
15200 }
15218 else
15232 {
15240 normal:
15256 {
15261 }
15265 }
15269 /* Irritatingly, AMD extended registers use
15270 different naming convention: "r%d[bwd]" */
15272 {
15275 {
15289 /* no suffix */
15294 }
15296 }
15299 {
15302 else
15304 }
15305 }
15307 /* Meaning of CODE:
15308 L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
15309 C -- print opcode suffix for set/cmov insn.
15310 c -- like C, but print reversed condition
15311 F,f -- likewise, but for floating-point.
15312 O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
15313 otherwise nothing
15314 R -- print embeded rounding and sae.
15315 r -- print only sae.
15316 z -- print the opcode suffix for the size of the current operand.
15317 Z -- likewise, with special suffixes for x87 instructions.
15318 * -- print a star (in certain assembler syntax)
15319 A -- print an absolute memory reference.
15320 E -- print address with DImode register names if TARGET_64BIT.
15321 w -- print the operand as if it's a "word" (HImode) even if it isn't.
15322 s -- print a shift double count, followed by the assemblers argument
15323 delimiter.
15324 b -- print the QImode name of the register for the indicated operand.
15325 %b0 would print %al if operands[0] is reg 0.
15326 w -- likewise, print the HImode name of the register.
15327 k -- likewise, print the SImode name of the register.
15328 q -- likewise, print the DImode name of the register.
15329 x -- likewise, print the V4SFmode name of the register.
15330 t -- likewise, print the V8SFmode name of the register.
15331 g -- likewise, print the V16SFmode name of the register.
15332 h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
15333 y -- print "st(0)" instead of "st" as a register.
15334 d -- print duplicated register operand for AVX instruction.
15335 D -- print condition for SSE cmp instruction.
15336 P -- if PIC, print an @PLT suffix.
15337 p -- print raw symbol name.
15338 X -- don't print any sort of PIC '@' suffix for a symbol.
15339 & -- print some in-use local-dynamic symbol name.
15340 H -- print a memory address offset by 8; used for sse high-parts
15341 Y -- print condition for XOP pcom* instruction.
15342 + -- print a branch hint as 'cs' or 'ds' prefix
15343 ; -- print a semicolon (after prefixes due to bug in older gas).
15344 ~ -- print "i" if TARGET_AVX2, "f" otherwise.
15345 @ -- print a segment register of thread base pointer load
15346 ^ -- print addr32 prefix if TARGET_64BIT and Pmode != word_mode
15347 ! -- print MPX prefix for jxx/call/ret instructions if required.
15348 */
15350 void
15352 {
15354 {
15356 {
15359 {
15365 /* Intel syntax. For absolute addresses, registers should not
15366 be surrounded by braces. */
15368 {
15373 }
15378 }
15384 /* Wrap address in an UNSPEC to declare special handling. */
15422 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15427 {
15441 output_operand_lossage
15444 }
15447 #endif
15452 {
15453 /* Opcodes don't get size suffixes if using Intel opcodes. */
15458 {
15476 output_operand_lossage
15479 }
15480 }
15483 warning
15485 /* FALLTHRU */
15488 /* 387 opcodes don't get size suffixes if using Intel opcodes. */
15493 {
15495 {
15497 #ifdef HAVE_AS_IX86_FILDS
15499 #endif
15507 #ifdef HAVE_AS_IX86_FILDQ
15509 #else
15511 #endif
15516 }
15517 }
15519 {
15520 /* 387 opcodes don't get size suffixes
15521 if the operands are registers. */
15526 {
15542 }
15543 }
15544 else
15545 {
15546 output_operand_lossage
15549 }
15551 output_operand_lossage
15572 {
15575 }
15580 {
15631 }
15635 /* Little bit of braindamage here. The SSE compare instructions
15636 does use completely different names for the comparisons that the
15637 fp conditional moves. */
15639 {
15642 {
15645 }
15651 {
15654 }
15660 {
15663 }
15672 {
15675 }
15681 {
15684 }
15690 {
15693 }
15704 }
15709 #ifdef HAVE_AS_IX86_CMOV_SUN_SYNTAX
15712 #endif
15717 {
15721 }
15725 file);
15730 {
15734 }
15735 /* It doesn't actually matter what mode we use here, as we're
15736 only going to use this for printing. */
15738 /* Output 'qword ptr' for intel assembler dialect. */
15747 #ifdef HAVE_AS_IX86_HLE
15749 #else
15751 #endif
15753 #ifdef HAVE_AS_IX86_HLE
15755 #else
15757 #endif
15758 /* We do not want to print value of the operand. */
15787 {
15802 }
15815 {
15820 else
15823 }
15826 {
15827 rtx x;
15836 {
15841 {
15843 bool cputaken
15846 /* Emit hints only in the case default branch prediction
15847 heuristics would fail. */
15849 {
15850 /* We use 3e (DS) prefix for taken branches and
15851 2e (CS) prefix for not taken branches. */
15854 else
15856 }
15857 }
15858 }
15860 }
15863 #ifndef HAVE_AS_IX86_REP_LOCK_PREFIX
15865 #endif
15872 /* The kernel uses a different segment register for performance
15873 reasons; a system call would not have to trash the userspace
15874 segment register, which would be expensive. */
15877 else
15897 }
15898 }
15904 {
15905 /* No `byte ptr' prefix for call instructions or BLKmode operands. */
15908 {
15911 {
15920 else
15927 }
15929 /* Check for explicit size override (codes 'b', 'w', 'k',
15930 'q' and 'x') */
15944 }
15947 /* Avoid (%rip) for call operands. */
15953 else
15955 }
15958 {
15959 REAL_VALUE_TYPE r;
15967 /* Sign extend 32bit SFmode immediate to 8 bytes. */
15971 else
15973 }
15976 {
15977 REAL_VALUE_TYPE r;
15986 }
15988 /* These float cases don't actually occur as immediate operands. */
15990 {
15995 }
15997 else
15998 {
15999 /* We have patterns that allow zero sets of memory, for instance.
16000 In 64-bit mode, we should probably support all 8-byte vectors,
16001 since we can in fact encode that into an immediate. */
16003 {
16006 }
16009 {
16011 {
16014 }
16017 {
16020 else
16022 }
16023 }
16028 else
16030 }
16031 }
16033 static bool
16035 {
16038 }
16039 \f
16040 /* Print a memory operand whose address is ADDR. */
16042 static void
16044 {
16053 {
16060 }
16062 {
16066 }
16068 {
16072 {
16075 }
16078 }
16080 {
16085 }
16086 else
16097 {
16108 }
16110 /* Use one byte shorter RIP relative addressing for 64bit mode. */
16112 {
16124 }
16126 {
16127 /* Displacement only requires special attention. */
16130 {
16134 }
16137 else
16139 }
16140 else
16141 {
16142 /* Print SImode register names to force addr32 prefix. */
16144 {
16145 #ifdef ENABLE_CHECKING
16148 {
16159 }
16160 #endif
16163 }
16165 && TARGET_X32
16166 && disp
16169 {
16170 /* X32 runs in 64-bit mode, where displacement, DISP, in
16171 address DISP(%r64), is encoded as 32-bit immediate sign-
16172 extended from 32-bit to 64-bit. For -0x40000300(%r64),
16173 address is %r64 + 0xffffffffbffffd00. When %r64 <
16174 0x40000300, like 0x37ffe064, address is 0xfffffffff7ffdd64,
16175 which is invalid for x32. The correct address is %r64
16176 - 0x40000300 == 0xf7ffdd64. To properly encode
16177 -0x40000300(%r64) for x32, we zero-extend negative
16178 displacement by forcing addr32 prefix which truncates
16179 0xfffffffff7ffdd64 to 0xf7ffdd64. In theory, we should
16180 zero-extend all negative displacements, including -1(%rsp).
16181 However, for small negative displacements, sign-extension
16182 won't cause overflow. We only zero-extend negative
16183 displacements if they < -16*1024*1024, which is also used
16184 to check legitimate address displacements for PIC. */
16186 }
16189 {
16191 {
16196 else
16198 }
16204 {
16209 }
16211 }
16212 else
16213 {
16217 {
16218 /* Pull out the offset of a symbol; print any symbol itself. */
16222 {
16226 }
16234 else
16236 }
16240 {
16243 {
16247 }
16248 }
16251 else
16255 {
16260 }
16262 }
16263 }
16264 }
16266 /* Implementation of TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
16268 static bool
16270 {
16271 rtx op;
16278 {
16281 /* FIXME: This might be @TPOFF in Sun ld. */
16292 else
16304 else
16311 #if TARGET_MACHO
16317 #endif
16320 {
16325 #ifdef TARGET_THREAD_SPLIT_STACK_OFFSET
16327 #else
16329 #endif
16332 }
16337 }
16340 }
16341 \f
16342 /* Split one or more double-mode RTL references into pairs of half-mode
16343 references. The RTL can be REG, offsettable MEM, integer constant, or
16344 CONST_DOUBLE. "operands" is a pointer to an array of double-mode RTLs to
16345 split and "num" is its length. lo_half and hi_half are output arrays
16346 that parallel "operands". */
16348 void
16351 {
16352 machine_mode half_mode;
16356 {
16365 }
16370 {
16373 /* simplify_subreg refuse to split volatile memory addresses,
16374 but we still have to handle it. */
16376 {
16379 }
16380 else
16381 {
16388 }
16389 }
16390 }
16391 \f
16392 /* Output code to perform a 387 binary operation in INSN, one of PLUS,
16393 MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3]
16394 is the expression of the binary operation. The output may either be
16395 emitted here, or returned to the caller, like all output_* functions.
16397 There is no guarantee that the operands are the same mode, as they
16398 might be within FLOAT or FLOAT_EXTEND expressions. */
16400 #ifndef SYSV386_COMPAT
16401 /* Set to 1 for compatibility with brain-damaged assemblers. No-one
16402 wants to fix the assemblers because that causes incompatibility
16403 with gcc. No-one wants to fix gcc because that causes
16404 incompatibility with assemblers... You can use the option of
16405 -DSYSV386_COMPAT=0 if you recompile both gcc and gas this way. */
16406 #define SYSV386_COMPAT 1
16407 #endif
16411 {
16417 #ifdef ENABLE_CHECKING
16418 /* Even if we do not want to check the inputs, this documents input
16419 constraints. Which helps in understanding the following code. */
16429 else
16431 #endif
16434 {
16439 else
16448 else
16457 else
16466 else
16473 }
16476 {
16478 {
16482 else
16484 }
16485 else
16486 {
16490 else
16492 }
16494 }
16498 {
16504 /* know operands[0] == operands[1]. */
16507 {
16510 }
16513 {
16515 /* How is it that we are storing to a dead operand[2]?
16516 Well, presumably operands[1] is dead too. We can't
16517 store the result to st(0) as st(0) gets popped on this
16518 instruction. Instead store to operands[2] (which I
16519 think has to be st(1)). st(1) will be popped later.
16520 gcc <= 2.8.1 didn't have this check and generated
16521 assembly code that the Unixware assembler rejected. */
16523 else
16526 }
16530 else
16537 {
16540 }
16543 {
16546 }
16549 {
16550 #if SYSV386_COMPAT
16551 /* The SystemV/386 SVR3.2 assembler, and probably all AT&T
16552 derived assemblers, confusingly reverse the direction of
16553 the operation for fsub{r} and fdiv{r} when the
16554 destination register is not st(0). The Intel assembler
16555 doesn't have this brain damage. Read !SYSV386_COMPAT to
16556 figure out what the hardware really does. */
16559 else
16561 #else
16563 /* As above for fmul/fadd, we can't store to st(0). */
16565 else
16567 #endif
16569 }
16572 {
16573 #if SYSV386_COMPAT
16576 else
16578 #else
16581 else
16583 #endif
16585 }
16588 {
16591 else
16594 }
16596 {
16597 #if SYSV386_COMPAT
16599 #else
16601 #endif
16602 }
16603 else
16604 {
16605 #if SYSV386_COMPAT
16607 #else
16609 #endif
16610 }
16615 }
16619 }
16621 /* Check if a 256bit AVX register is referenced inside of EXP. */
16623 static bool
16625 {
16631 }
16633 /* Return needed mode for entity in optimize_mode_switching pass. */
16635 static int
16637 {
16639 {
16640 rtx link;
16642 /* Needed mode is set to AVX_U128_CLEAN if there are
16643 no 256bit modes used in function arguments. */
16645 link;
16647 {
16649 {
16654 }
16655 }
16658 }
16660 /* Require DIRTY mode if a 256bit AVX register is referenced. Hardware
16661 changes state only when a 256bit register is written to, but we need
16662 to prevent the compiler from moving optimal insertion point above
16663 eventual read from 256bit register. */
16670 }
16672 /* Return mode that i387 must be switched into
16673 prior to the execution of insn. */
16675 static int
16677 {
16680 /* The mode UNINITIALIZED is used to store control word after a
16681 function call or ASM pattern. The mode ANY specify that function
16682 has no requirements on the control word and make no changes in the
16683 bits we are interested in. */
16697 {
16720 }
16723 }
16725 /* Return mode that entity must be switched into
16726 prior to the execution of insn. */
16728 static int
16730 {
16732 {
16742 }
16744 }
16746 /* Check if a 256bit AVX register is referenced in stores. */
16748 static void
16750 {
16752 {
16755 }
16756 }
16758 /* Calculate mode of upper 128bit AVX registers after the insn. */
16760 static int
16762 {
16769 /* We know that state is clean after CALL insn if there are no
16770 256bit registers used in the function return register. */
16772 {
16777 }
16779 /* Otherwise, return current mode. Remember that if insn
16780 references AVX 256bit registers, the mode was already changed
16781 to DIRTY from MODE_NEEDED. */
16783 }
16785 /* Return the mode that an insn results in. */
16787 static int
16789 {
16791 {
16801 }
16802 }
16804 static int
16806 {
16807 tree arg;
16809 /* Entry mode is set to AVX_U128_DIRTY if there are
16810 256bit modes used in function arguments. */
16813 {
16818 }
16821 }
16823 /* Return a mode that ENTITY is assumed to be
16824 switched to at function entry. */
16826 static int
16828 {
16830 {
16840 }
16841 }
16843 static int
16845 {
16848 /* Exit mode is set to AVX_U128_DIRTY if there are
16849 256bit modes used in the function return register. */
16854 }
16856 /* Return a mode that ENTITY is assumed to be
16857 switched to at function exit. */
16859 static int
16861 {
16863 {
16873 }
16874 }
16876 static int
16878 {
16880 }
16882 /* Output code to initialize control word copies used by trunc?f?i and
16883 rounding patterns. CURRENT_MODE is set to current control word,
16884 while NEW_MODE is set to new control word. */
16886 static void
16888 {
16890 rtx new_mode;
16901 {
16903 {
16905 /* round toward zero (truncate) */
16911 /* round down toward -oo */
16918 /* round up toward +oo */
16925 /* mask precision exception for nearbyint() */
16932 }
16933 }
16934 else
16935 {
16937 {
16939 /* round toward zero (truncate) */
16945 /* round down toward -oo */
16951 /* round up toward +oo */
16957 /* mask precision exception for nearbyint() */
16964 }
16965 }
16971 }
16973 /* Emit vzeroupper. */
16975 void
16977 {
16980 /* Cancel automatic vzeroupper insertion if there are
16981 live call-saved SSE registers at the insertion point. */
16993 }
16995 /* Generate one or more insns to set ENTITY to MODE. */
16997 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE
16998 is the set of hard registers live at the point where the insn(s)
16999 are to be inserted. */
17001 static void
17003 HARD_REG_SET regs_live)
17004 {
17006 {
17021 }
17022 }
17024 /* Output code for INSN to convert a float to a signed int. OPERANDS
17025 are the insn operands. The output may be [HSD]Imode and the input
17026 operand may be [SDX]Fmode. */
17030 {
17035 /* Jump through a hoop or two for DImode, since the hardware has no
17036 non-popping instruction. We used to do this a different way, but
17037 that was somewhat fragile and broke with post-reload splitters. */
17047 else
17048 {
17053 else
17057 }
17060 }
17062 /* Output code for x87 ffreep insn. The OPNO argument, which may only
17063 have the values zero or one, indicates the ffreep insn's operand
17064 from the OPERANDS array. */
17068 {
17070 #ifdef HAVE_AS_IX86_FFREEP
17072 #else
17073 {
17083 }
17084 #endif
17087 }
17090 /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi
17091 should be used. UNORDERED_P is true when fucom should be used. */
17095 {
17101 {
17104 }
17105 else
17106 {
17109 }
17112 {
17116 else
17118 else
17121 else
17123 }
17130 {
17132 {
17135 }
17136 else
17138 }
17141 && stack_top_dies
17144 {
17145 /* If both the top of the 387 stack dies, and the other operand
17146 is also a stack register that dies, then this must be a
17147 `fcompp' float compare */
17150 {
17151 /* There is no double popping fcomi variant. Fortunately,
17152 eflags is immune from the fstp's cc clobbering. */
17155 else
17158 }
17159 else
17160 {
17163 else
17165 }
17166 }
17167 else
17168 {
17169 /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */
17172 {
17180 NULL,
17181 NULL,
17188 NULL,
17189 NULL,
17190 NULL,
17191 NULL
17192 };
17207 }
17208 }
17210 void
17212 {
17215 #ifdef ASM_QUAD
17218 #else
17220 #endif
17223 }
17225 void
17227 {
17230 #ifdef ASM_QUAD
17233 #else
17235 #endif
17236 /* We can't use @GOTOFF for text labels on VxWorks; see gotoff_operand. */
17242 #if TARGET_MACHO
17244 {
17248 }
17249 #endif
17250 else
17253 }
17254 \f
17255 /* Generate either "mov $0, reg" or "xor reg, reg", as appropriate
17256 for the target. */
17258 void
17260 {
17261 rtx tmp;
17263 /* We play register width games, which are only valid after reload. */
17266 /* Avoid HImode and its attendant prefix byte. */
17272 {
17275 }
17278 }
17280 /* X is an unchanging MEM. If it is a constant pool reference, return
17281 the constant pool rtx, else NULL. */
17283 rtx
17285 {
17292 }
17294 void
17296 {
17304 {
17305 rtx tmp;
17309 {
17315 }
17318 }
17322 {
17325 rtx tmp;
17330 else
17334 {
17341 }
17342 }
17346 {
17348 {
17349 #if TARGET_MACHO
17350 /* dynamic-no-pic */
17352 {
17359 }
17361 {
17365 }
17368 else
17369 {
17377 }
17378 /* dynamic-no-pic */
17379 #endif
17380 }
17381 else
17382 {
17386 {
17392 }
17393 }
17394 }
17395 else
17396 {
17407 /* Force large constants in 64bit compilation into register
17408 to get them CSEed. */
17419 {
17420 /* If we are loading a floating point constant to a register,
17421 force the value to memory now, since we'll get better code
17422 out the back end. */
17426 {
17431 }
17432 }
17433 }
17436 }
17438 void
17440 {
17447 /* Force constants other than zero into memory. We do not know how
17448 the instructions used to build constants modify the upper 64 bits
17449 of the register, once we have that information we may be able
17450 to handle some of them more efficiently. */
17459 /* We need to check memory alignment for SSE mode since attribute
17460 can make operands unaligned. */
17465 {
17468 /* ix86_expand_vector_move_misalign() does not like constants ... */
17474 /* ... nor both arguments in memory. */
17482 }
17484 /* Make operand1 a register if it isn't already. */
17488 {
17491 }
17494 }
17496 /* Split 32-byte AVX unaligned load and store if needed. */
17498 static void
17500 {
17501 rtx m;
17505 machine_mode mode;
17508 {
17529 }
17532 {
17535 {
17542 }
17543 /* Normal *mov<mode>_internal pattern will handle
17544 unaligned loads just fine if misaligned_operand
17545 is true, and without the UNSPEC it can be combined
17546 with arithmetic instructions. */
17549 else
17551 }
17553 {
17556 {
17561 }
17562 else
17564 }
17565 else
17567 }
17569 /* Implement the movmisalign patterns for SSE. Non-SSE modes go
17570 straight to ix86_expand_vector_move. */
17571 /* Code generation for scalar reg-reg moves of single and double precision data:
17572 if (x86_sse_partial_reg_dependency == true | x86_sse_split_regs == true)
17573 movaps reg, reg
17574 else
17575 movss reg, reg
17576 if (x86_sse_partial_reg_dependency == true)
17577 movapd reg, reg
17578 else
17579 movsd reg, reg
17581 Code generation for scalar loads of double precision data:
17582 if (x86_sse_split_regs == true)
17583 movlpd mem, reg (gas syntax)
17584 else
17585 movsd mem, reg
17587 Code generation for unaligned packed loads of single precision data
17588 (x86_sse_unaligned_move_optimal overrides x86_sse_partial_reg_dependency):
17589 if (x86_sse_unaligned_move_optimal)
17590 movups mem, reg
17592 if (x86_sse_partial_reg_dependency == true)
17593 {
17594 xorps reg, reg
17595 movlps mem, reg
17596 movhps mem+8, reg
17597 }
17598 else
17599 {
17600 movlps mem, reg
17601 movhps mem+8, reg
17602 }
17604 Code generation for unaligned packed loads of double precision data
17605 (x86_sse_unaligned_move_optimal overrides x86_sse_split_regs):
17606 if (x86_sse_unaligned_move_optimal)
17607 movupd mem, reg
17609 if (x86_sse_split_regs == true)
17610 {
17611 movlpd mem, reg
17612 movhpd mem+8, reg
17613 }
17614 else
17615 {
17616 movsd mem, reg
17617 movhpd mem+8, reg
17618 }
17619 */
17621 void
17623 {
17632 {
17634 {
17638 {
17640 {
17643 }
17644 else
17646 }
17648 /* FALLTHRU */
17652 {
17667 }
17673 else
17681 }
17684 }
17688 {
17690 {
17694 {
17696 {
17699 }
17700 else
17702 }
17704 /* FALLTHRU */
17714 }
17717 }
17720 {
17721 /* Normal *mov<mode>_internal pattern will handle
17722 unaligned loads just fine if misaligned_operand
17723 is true, and without the UNSPEC it can be combined
17724 with arithmetic instructions. */
17730 /* ??? If we have typed data, then it would appear that using
17731 movdqu is the only way to get unaligned data loaded with
17732 integer type. */
17734 {
17736 {
17739 }
17741 /* We will eventually emit movups based on insn attributes. */
17745 }
17747 {
17748 rtx zero;
17751 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17752 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17754 {
17755 /* We will eventually emit movups based on insn attributes. */
17758 }
17760 /* When SSE registers are split into halves, we can avoid
17761 writing to the top half twice. */
17763 {
17766 }
17767 else
17768 {
17769 /* ??? Not sure about the best option for the Intel chips.
17770 The following would seem to satisfy; the register is
17771 entirely cleared, breaking the dependency chain. We
17772 then store to the upper half, with a dependency depth
17773 of one. A rumor has it that Intel recommends two movsd
17774 followed by an unpacklpd, but this is unconfirmed. And
17775 given that the dependency depth of the unpacklpd would
17776 still be one, I'm not sure why this would be better. */
17778 }
17784 }
17785 else
17786 {
17787 rtx t;
17790 || TARGET_SSE_UNALIGNED_LOAD_OPTIMAL
17791 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17793 {
17795 {
17798 }
17805 }
17809 else
17814 else
17823 }
17824 }
17826 {
17828 {
17831 /* We will eventually emit movups based on insn attributes. */
17833 }
17835 {
17837 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17838 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17840 /* We will eventually emit movups based on insn attributes. */
17842 else
17843 {
17848 }
17849 }
17850 else
17851 {
17856 || TARGET_SSE_UNALIGNED_STORE_OPTIMAL
17857 || TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
17859 {
17862 }
17863 else
17864 {
17869 }
17870 }
17871 }
17872 else
17874 }
17876 /* Helper function of ix86_fixup_binary_operands to canonicalize
17877 operand order. Returns true if the operands should be swapped. */
17879 static bool
17881 rtx operands[])
17882 {
17887 /* If the operation is not commutative, we can't do anything. */
17891 /* Highest priority is that src1 should match dst. */
17897 /* Next highest priority is that immediate constants come second. */
17903 /* Lowest priority is that memory references should come second. */
17910 }
17913 /* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the
17914 destination to use for the operation. If different from the true
17915 destination in operands[0], a copy operation will be required. */
17917 rtx
17919 rtx operands[])
17920 {
17925 /* Canonicalize operand order. */
17927 {
17928 /* It is invalid to swap operands of different modes. */
17932 }
17934 /* Both source operands cannot be in memory. */
17936 {
17937 /* Optimization: Only read from memory once. */
17939 {
17942 }
17945 else
17947 }
17949 /* If the destination is memory, and we do not have matching source
17950 operands, do things in registers. */
17954 /* Source 1 cannot be a constant. */
17958 /* Source 1 cannot be a non-matching memory. */
17962 /* Improve address combine. */
17971 }
17973 /* Similarly, but assume that the destination has already been
17974 set up properly. */
17976 void
17979 {
17982 }
17984 /* Attempt to expand a binary operator. Make the expansion closer to the
17985 actual machine, then just general_operand, which will allow 3 separate
17986 memory references (one output, two input) in a single insn. */
17988 void
17990 rtx operands[])
17991 {
17998 /* Emit the instruction. */
18005 {
18006 /* This is going to be an LEA; avoid splitting it later. */
18008 }
18009 else
18010 {
18013 }
18015 /* Fix up the destination if needed. */
18018 }
18020 /* Expand vector logical operation CODE (AND, IOR, XOR) in MODE with
18021 the given OPERANDS. */
18023 void
18025 rtx operands[])
18026 {
18029 {
18032 }
18034 {
18037 }
18038 /* Optimize (__m128i) d | (__m128i) e and similar code
18039 when d and e are float vectors into float vector logical
18040 insn. In C/C++ without using intrinsics there is no other way
18041 to express vector logical operation on float vectors than
18042 to cast them temporarily to integer vectors. */
18044 && !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
18053 {
18054 rtx dst;
18056 {
18065 {
18068 }
18069 else
18070 {
18075 }
18086 }
18087 }
18096 }
18098 /* Return TRUE or FALSE depending on whether the binary operator meets the
18099 appropriate constraints. */
18101 bool
18104 {
18109 /* Both source operands cannot be in memory. */
18113 /* Canonicalize operand order for commutative operators. */
18117 /* If the destination is memory, we must have a matching source operand. */
18121 /* Source 1 cannot be a constant. */
18125 /* Source 1 cannot be a non-matching memory. */
18127 /* Support "andhi/andsi/anddi" as a zero-extending move. */
18135 }
18137 /* Attempt to expand a unary operator. Make the expansion closer to the
18138 actual machine, then just general_operand, which will allow 2 separate
18139 memory references (one output, one input) in a single insn. */
18141 void
18143 rtx operands[])
18144 {
18151 /* If the destination is memory, and we do not have matching source
18152 operands, do things in registers. */
18154 {
18157 else
18159 }
18161 /* When source operand is memory, destination must match. */
18165 /* Emit the instruction. */
18171 else
18172 {
18175 }
18177 /* Fix up the destination if needed. */
18180 }
18182 /* Split 32bit/64bit divmod with 8bit unsigned divmod if dividend and
18183 divisor are within the range [0-255]. */
18185 void
18188 {
18197 {
18210 }
18217 /* Use 8bit unsigned divimod if dividend and divisor are within
18218 the range [0-255]. */
18227 pc_rtx);
18232 /* Generate original signed/unsigned divimod. */
18237 /* Branch to the end. */
18241 /* Generate 8bit unsigned divide. */
18243 /* Don't use operands[0] for result of 8bit divide since not all
18244 registers support QImode ZERO_EXTRACT. */
18251 {
18254 }
18255 else
18256 {
18259 }
18261 /* Extract remainder from AH. */
18265 else
18266 {
18267 /* Need a new scratch register since the old one has result
18268 of 8bit divide. */
18272 }
18275 /* Zero extend quotient from AL. */
18281 }
18283 #define LEA_MAX_STALL (3)
18284 #define LEA_SEARCH_THRESHOLD (LEA_MAX_STALL << 1)
18286 /* Increase given DISTANCE in half-cycles according to
18287 dependencies between PREV and NEXT instructions.
18288 Add 1 half-cycle if there is no dependency and
18289 go to next cycle if there is some dependecy. */
18291 static unsigned int
18293 {
18309 }
18311 /* Function checks if instruction INSN defines register number
18312 REGNO1 or REGNO2. */
18314 static bool
18317 {
18318 df_ref def;
18328 }
18330 /* Function checks if instruction INSN uses register number
18331 REGNO as a part of address expression. */
18333 static bool
18335 {
18336 df_ref use;
18343 }
18345 /* Search backward for non-agu definition of register number REGNO1
18346 or register number REGNO2 in basic block starting from instruction
18347 START up to head of basic block or instruction INSN.
18349 Function puts true value into *FOUND var if definition was found
18350 and false otherwise.
18352 Distance in half-cycles between START and found instruction or head
18353 of BB is added to DISTANCE and returned. */
18355 static int
18359 {
18369 {
18371 {
18374 {
18377 {
18380 }
18381 }
18384 }
18389 }
18392 }
18394 /* Search backward for non-agu definition of register number REGNO1
18395 or register number REGNO2 in INSN's basic block until
18396 1. Pass LEA_SEARCH_THRESHOLD instructions, or
18397 2. Reach neighbour BBs boundary, or
18398 3. Reach agu definition.
18399 Returns the distance between the non-agu definition point and INSN.
18400 If no definition point, returns -1. */
18402 static int
18405 {
18416 {
18417 edge e;
18418 edge_iterator ei;
18423 {
18426 }
18432 else
18433 {
18438 {
18439 int bb_dist
18445 {
18452 }
18453 }
18456 }
18457 }
18459 /* get_attr_type may modify recog data. We want to make sure
18460 that recog data is valid for instruction INSN, on which
18461 distance_non_agu_define is called. INSN is unchanged here. */
18468 }
18470 /* Return the distance in half-cycles between INSN and the next
18471 insn that uses register number REGNO in memory address added
18472 to DISTANCE. Return -1 if REGNO0 is set.
18474 Put true value into *FOUND if register usage was found and
18475 false otherwise.
18476 Put true value into *REDEFINED if register redefinition was
18477 found and false otherwise. */
18479 static int
18483 {
18492 {
18495 /* If insn and start belong to the same bb, set prev to insn,
18496 so the call to increase_distance will increase the distance
18497 between insns by 1. */
18499 }
18504 {
18506 {
18509 {
18510 /* Return DISTANCE if OP0 is used in memory
18511 address in NEXT. */
18514 }
18517 {
18518 /* Return -1 if OP0 is set in NEXT. */
18521 }
18524 }
18530 }
18533 }
18535 /* Return the distance between INSN and the next insn that uses
18536 register number REGNO0 in memory address. Return -1 if no such
18537 a use is found within LEA_SEARCH_THRESHOLD or REGNO0 is set. */
18539 static int
18541 {
18553 {
18554 edge e;
18555 edge_iterator ei;
18560 {
18563 }
18569 else
18570 {
18576 {
18577 int bb_dist
18582 {
18589 }
18590 }
18593 }
18594 }
18600 }
18602 /* Define this macro to tune LEA priority vs ADD, it take effect when
18603 there is a dilemma of choicing LEA or ADD
18604 Negative value: ADD is more preferred than LEA
18605 Zero: Netrual
18606 Positive value: LEA is more preferred than ADD*/
18607 #define IX86_LEA_PRIORITY 0
18609 /* Return true if usage of lea INSN has performance advantage
18610 over a sequence of instructions. Instructions sequence has
18611 SPLIT_COST cycles higher latency than lea latency. */
18613 static bool
18616 {
18619 /* For Silvermont if using a 2-source or 3-source LEA for
18620 non-destructive destination purposes, or due to wanting
18621 ability to use SCALE, the use of LEA is justified. */
18623 {
18631 }
18637 {
18638 /* If there is no non AGU operand definition, no AGU
18639 operand usage and split cost is 0 then both lea
18640 and non lea variants have same priority. Currently
18641 we prefer lea for 64 bit code and non lea on 32 bit
18642 code. */
18645 else
18647 }
18649 /* With longer definitions distance lea is more preferable.
18650 Here we change it to take into account splitting cost and
18651 lea priority. */
18654 /* If there is no use in memory addess then we just check
18655 that split cost exceeds AGU stall. */
18659 /* If this insn has both backward non-agu dependence and forward
18660 agu dependence, the one with short distance takes effect. */
18662 }
18664 /* Return true if it is legal to clobber flags by INSN and
18665 false otherwise. */
18667 static bool
18669 {
18671 df_ref use;
18672 bitmap live;
18675 {
18677 {
18684 }
18690 }
18694 }
18696 /* Return true if we need to split op0 = op1 + op2 into a sequence of
18697 move and add to avoid AGU stalls. */
18699 bool
18701 {
18704 /* Check if we need to optimize. */
18708 /* Check it is correct to split here. */
18716 /* We need to split only adds with non destructive
18717 destination operand. */
18720 else
18722 }
18724 /* Return true if we should emit lea instruction instead of mov
18725 instruction. */
18727 bool
18729 {
18732 /* Check if we need to optimize. */
18736 /* Use lea for reg to reg moves only. */
18744 }
18746 /* Return true if we need to split lea into a sequence of
18747 instructions to avoid AGU stalls. */
18749 bool
18751 {
18757 /* Check we need to optimize. */
18761 /* The "at least two components" test below might not catch simple
18762 move or zero extension insns if parts.base is non-NULL and parts.disp
18763 is const0_rtx as the only components in the address, e.g. if the
18764 register is %rbp or %r13. As this test is much cheaper and moves or
18765 zero extensions are the common case, do this check first. */
18771 /* Check if it is OK to split here. */
18778 /* There should be at least two components in the address. */
18783 /* We should not split into add if non legitimate pic
18784 operand is used as displacement. */
18799 /* Compute how many cycles we will add to execution time
18800 if split lea into a sequence of instructions. */
18802 {
18803 /* Have to use mov instruction if non desctructive
18804 destination form is used. */
18808 /* Have to add index to base if both exist. */
18812 /* Have to use shift and adds if scale is 2 or greater. */
18814 {
18819 else
18821 }
18823 /* Have to use add instruction with immediate if
18824 disp is non zero. */
18828 /* Subtract the price of lea. */
18830 }
18834 }
18836 /* Emit x86 binary operand CODE in mode MODE, where the first operand
18837 matches destination. RTX includes clobber of FLAGS_REG. */
18839 static void
18842 {
18849 }
18851 /* Return true if regno1 def is nearest to the insn. */
18853 static bool
18855 {
18862 {
18864 {
18867 }
18873 }
18875 /* None of the regs is defined in the bb. */
18877 }
18879 /* Split lea instructions into a sequence of instructions
18880 which are executed on ALU to avoid AGU stalls.
18881 It is assumed that it is allowed to clobber flags register
18882 at lea position. */
18884 void
18886 {
18902 {
18905 }
18908 {
18911 }
18917 {
18918 /* Case r1 = r1 + ... */
18920 {
18921 /* If we have a case r1 = r1 + C * r2 then we
18922 should use multiplication which is very
18923 expensive. Assume cost model is wrong if we
18924 have such case here. */
18929 }
18930 else
18931 {
18932 /* r1 = r2 + r3 * C case. Need to move r3 into r1. */
18936 /* Use shift for scaling. */
18945 }
18946 }
18948 {
18951 }
18952 else
18953 {
18955 {
18958 }
18960 {
18963 }
18964 else
18965 {
18970 else
18971 {
18972 rtx tmp1;
18974 /* Find better operand for SET instruction, depending
18975 on which definition is farther from the insn. */
18978 else
18988 }
18991 }
18995 }
18996 }
18998 /* Return true if it is ok to optimize an ADD operation to LEA
18999 operation to avoid flag register consumation. For most processors,
19000 ADD is faster than LEA. For the processors like BONNELL, if the
19001 destination register of LEA holds an actual address which will be
19002 used soon, LEA is better and otherwise ADD is better. */
19004 bool
19006 {
19011 /* If a = b + c, (a!=b && a!=c), must use lea form. */
19019 }
19021 /* Return true if destination reg of SET_BODY is shift count of
19022 USE_BODY. */
19024 static bool
19026 {
19027 rtx set_dest;
19028 rtx shift_rtx;
19031 /* Retrieve destination of SET_BODY. */
19033 {
19042 use_body))
19047 }
19049 /* Retrieve shift count of USE_BODY. */
19051 {
19063 }
19071 {
19074 /* Return true if shift count is dest of SET_BODY. */
19076 {
19077 /* Add check since it can be invoked before register
19078 allocation in pre-reload schedule. */
19084 }
19085 }
19088 }
19090 /* Return true if destination reg of SET_INSN is shift count of
19091 USE_INSN. */
19093 bool
19095 {
19098 }
19100 /* Return TRUE or FALSE depending on whether the unary operator meets the
19101 appropriate constraints. */
19103 bool
19105 machine_mode,
19107 {
19108 /* If one of operands is memory, source and destination must match. */
19114 }
19116 /* Return TRUE if the operands to a vec_interleave_{high,low}v2df
19117 are ok, keeping in mind the possible movddup alternative. */
19119 bool
19121 {
19127 }
19129 /* Post-reload splitter for converting an SF or DFmode value in an
19130 SSE register into an unsigned SImode. */
19132 void
19134 {
19135 machine_mode vecmode;
19145 /* Load up the value into the low element. We must ensure that the other
19146 elements are valid floats -- zero is the easiest such value. */
19148 {
19151 else
19153 }
19154 else
19155 {
19160 else
19162 }
19182 else
19187 }
19189 /* Convert an unsigned DImode value into a DFmode, using only SSE.
19190 Expects the 64-bit DImode to be supplied in a pair of integral
19191 registers. Requires SSE2; will use SSE3 if available. For x86_32,
19192 -mfpmath=sse, !optimize_size only. */
19194 void
19196 {
19200 rtx x;
19206 {
19209 }
19210 else
19211 {
19215 }
19223 /* int_xmm = {0x45300000UL, fp_xmm/hi, 0x43300000, fp_xmm/lo } */
19226 /* Concatenating (juxtaposing) (0x43300000UL ## fp_value_low_xmm)
19227 yields a valid DF value equal to (0x1.0p52 + double(fp_value_lo_xmm)).
19228 Similarly (0x45300000UL ## fp_value_hi_xmm) yields
19229 (0x1.0p84 + double(fp_value_hi_xmm)).
19230 Note these exponents differ by 32. */
19234 /* Subtract off those 0x1.0p52 and 0x1.0p84 biases, to produce values
19235 in [0,2**32-1] and [0]+[2**32,2**64-1] respectively. */
19244 /* Add the upper and lower DFmode values together. */
19247 else
19248 {
19252 }
19255 }
19257 /* Not used, but eases macroization of patterns. */
19258 void
19260 {
19262 }
19264 /* Convert an unsigned SImode value into a DFmode. Only currently used
19265 for SSE, but applicable anywhere. */
19267 void
19269 {
19270 REAL_VALUE_TYPE TWO31r;
19285 }
19287 /* Convert a signed DImode value into a DFmode. Only used for SSE in
19288 32-bit mode; otherwise we have a direct convert instruction. */
19290 void
19292 {
19293 REAL_VALUE_TYPE TWO32r;
19311 }
19313 /* Convert an unsigned SImode value into a SFmode, using only SSE.
19314 For x86_32, -mfpmath=sse, !optimize_size only. */
19315 void
19317 {
19318 REAL_VALUE_TYPE ONE16r;
19337 }
19339 /* floatunsv{4,8}siv{4,8}sf2 expander. Expand code to convert
19340 a vector of unsigned ints VAL to vector of floats TARGET. */
19342 void
19344 {
19346 REAL_VALUE_TYPE TWO16r;
19353 else
19358 OPTAB_DIRECT);
19369 OPTAB_DIRECT);
19371 OPTAB_DIRECT);
19374 }
19376 /* Adjust a V*SFmode/V*DFmode value VAL so that *sfix_trunc* resp. fix_trunc*
19377 pattern can be used on it instead of *ufix_trunc* resp. fixuns_trunc*.
19378 This is done by doing just signed conversion if < 0x1p31, and otherwise by
19379 subtracting 0x1p31 first and xoring in 0x80000000 from *XORP afterwards. */
19381 rtx
19383 {
19384 REAL_VALUE_TYPE TWO31r;
19399 {
19405 }
19414 OPTAB_DIRECT);
19415 else
19416 {
19422 OPTAB_DIRECT);
19423 }
19426 }
19428 /* A subroutine of ix86_build_signbit_mask. If VECT is true,
19429 then replicate the value for all elements of the vector
19430 register. */
19432 rtx
19434 {
19436 rtvec v;
19437 machine_mode scalar_mode;
19440 {
19473 }
19474 }
19476 /* A subroutine of ix86_expand_fp_absneg_operator, copysign expanders
19477 and ix86_expand_int_vcond. Create a mask for the sign bit in MODE
19478 for an SSE register. If VECT is true, then replicate the mask for
19479 all elements of the vector register. If INVERT is true, then create
19480 a mask excluding the sign bit. */
19482 rtx
19484 {
19486 wide_int w;
19490 {
19521 }
19528 /* Force this value into the low part of a fp vector constant. */
19537 }
19539 /* Generate code for floating point ABS or NEG. */
19541 void
19543 rtx operands[])
19544 {
19555 {
19561 }
19563 /* NEG and ABS performed with SSE use bitwise mask operations.
19564 Create the appropriate mask now. */
19567 else
19577 {
19579 rtvec par;
19584 else
19585 {
19588 }
19590 }
19591 else
19593 }
19595 /* Expand a copysign operation. Special case operand 0 being a constant. */
19597 void
19599 {
19613 else
19617 {
19624 {
19627 else
19628 {
19632 }
19633 }
19643 else
19647 }
19648 else
19649 {
19659 else
19663 }
19664 }
19666 /* Deconstruct a copysign operation into bit masks. Operand 0 is known to
19667 be a constant, and so has already been expanded into a vector constant. */
19669 void
19671 {
19687 {
19690 }
19691 }
19693 /* Deconstruct a copysign operation into bit masks. Operand 0 is variable,
19694 so we have to do two masks. */
19696 void
19698 {
19713 {
19714 /* Shouldn't happen often (it's useless, obviously), but when it does
19715 we'd generate incorrect code if we continue below. */
19718 }
19721 {
19732 }
19733 else
19734 {
19736 {
19738 }
19740 {
19744 }
19748 {
19751 }
19753 {
19758 }
19760 }
19764 }
19766 /* Return TRUE or FALSE depending on whether the first SET in INSN
19767 has source and destination with matching CC modes, and that the
19768 CC mode is at least as constrained as REQ_MODE. */
19770 bool
19772 {
19773 rtx set;
19774 machine_mode set_mode;
19784 {
19794 /* FALLTHRU */
19798 /* FALLTHRU */
19802 /* FALLTHRU */
19817 }
19820 }
19822 /* Generate insn patterns to do an integer compare of OPERANDS. */
19824 static rtx
19826 {
19827 machine_mode cmpmode;
19833 /* This is very simple, but making the interface the same as in the
19834 FP case makes the rest of the code easier. */
19838 /* Return the test that should be put into the flags user, i.e.
19839 the bcc, scc, or cmov instruction. */
19841 }
19843 /* Figure out whether to use ordered or unordered fp comparisons.
19844 Return the appropriate mode to use. */
19846 machine_mode
19848 {
19849 /* ??? In order to make all comparisons reversible, we do all comparisons
19850 non-trapping when compiling for IEEE. Once gcc is able to distinguish
19851 all forms trapping and nontrapping comparisons, we can make inequality
19852 comparisons trapping again, since it results in better code when using
19853 FCOM based compares. */
19855 }
19857 machine_mode
19859 {
19863 {
19866 }
19869 {
19870 /* Only zero flag is needed. */
19874 /* Codes needing carry flag. */
19877 /* Detect overflow checks. They need just the carry flag. */
19881 else
19886 /* Codes possibly doable only with sign flag when
19887 comparing against zero. */
19892 else
19893 /* For other cases Carry flag is not required. */
19895 /* Codes doable only with sign flag when comparing
19896 against zero, but we miss jump instruction for it
19897 so we need to use relational tests against overflow
19898 that thus needs to be zero. */
19903 else
19905 /* strcmp pattern do (use flags) and combine may ask us for proper
19906 mode. */
19911 }
19912 }
19914 /* Return the fixed registers used for condition codes. */
19916 static bool
19918 {
19922 }
19924 /* If two condition code modes are compatible, return a condition code
19925 mode which is compatible with both. Otherwise, return
19926 VOIDmode. */
19928 static machine_mode
19930 {
19947 {
19962 {
19977 }
19981 /* These are only compatible with themselves, which we already
19982 checked above. */
19984 }
19985 }
19988 /* Return a comparison we can do and that it is equivalent to
19989 swap_condition (code) apart possibly from orderedness.
19990 But, never change orderedness if TARGET_IEEE_FP, returning
19991 UNKNOWN in that case if necessary. */
19993 static enum rtx_code
19995 {
19997 {
20008 }
20009 }
20011 /* Return cost of comparison CODE using the best strategy for performance.
20012 All following functions do use number of instructions as a cost metrics.
20013 In future this should be tweaked to compute bytes for optimize_size and
20014 take into account performance of various instructions on various CPUs. */
20016 static int
20018 {
20021 /* The cost of code using bit-twiddling on %ah. */
20023 {
20046 }
20049 {
20056 }
20057 }
20059 /* Return strategy to use for floating-point. We assume that fcomi is always
20060 preferrable where available, since that is also true when looking at size
20061 (2 bytes, vs. 3 for fnstsw+sahf and at least 5 for fnstsw+test). */
20063 enum ix86_fpcmp_strategy
20065 {
20066 /* Do fcomi/sahf based test when profitable. */
20075 }
20077 /* Swap, force into registers, or otherwise massage the two operands
20078 to a fp comparison. The operands are updated in place; the new
20079 comparison code is returned. */
20081 static enum rtx_code
20083 {
20089 /* All of the unordered compare instructions only work on registers.
20090 The same is true of the fcomi compare instructions. The XFmode
20091 compare instructions require registers except when comparing
20092 against zero or when converting operand 1 from fixed point to
20093 floating point. */
20102 {
20105 }
20106 else
20107 {
20108 /* %%% We only allow op1 in memory; op0 must be st(0). So swap
20109 things around if they appear profitable, otherwise force op0
20110 into a register. */
20116 {
20119 {
20122 }
20123 }
20129 {
20134 {
20137 }
20138 else
20140 }
20141 }
20143 /* Try to rearrange the comparison to make it cheaper. */
20147 {
20152 }
20157 }
20159 /* Convert comparison codes we use to represent FP comparison to integer
20160 code that will result in proper branch. Return UNKNOWN if no such code
20161 is available. */
20163 enum rtx_code
20165 {
20167 {
20190 }
20191 }
20193 /* Generate insn patterns to do a floating point compare of OPERANDS. */
20195 static rtx
20197 {
20204 /* Do fcomi/sahf based test when profitable. */
20206 {
20226 /* Sadness wrt reg-stack pops killing fpsr -- gotta get fnstsw first. */
20233 /* In the unordered case, we have to check C2 for NaN's, which
20234 doesn't happen to work out to anything nice combination-wise.
20235 So do some bit twiddling on the value we've got in AH to come
20236 up with an appropriate set of condition codes. */
20240 {
20244 {
20247 }
20248 else
20249 {
20255 }
20260 {
20265 }
20266 else
20267 {
20270 }
20275 {
20278 }
20279 else
20280 {
20284 }
20289 {
20295 }
20296 else
20297 {
20300 }
20305 {
20310 }
20311 else
20312 {
20315 }
20320 {
20325 }
20326 else
20327 {
20330 }
20344 }
20349 }
20351 /* Return the test that should be put into the flags user, i.e.
20352 the bcc, scc, or cmov instruction. */
20355 const0_rtx);
20356 }
20358 static rtx
20360 {
20361 rtx ret;
20367 {
20370 }
20371 else
20375 }
20377 void
20379 {
20381 rtx tmp;
20384 {
20391 simple:
20395 pc_rtx);
20403 /* Expand DImode branch into multiple compare+branch. */
20404 {
20408 machine_mode submode;
20411 {
20414 }
20421 /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to
20422 avoid two branches. This costs one extra insn, so disable when
20423 optimizing for size. */
20428 {
20446 }
20448 /* Otherwise, if we are doing less-than or greater-or-equal-than,
20449 op1 is a constant and the low word is zero, then we can just
20450 examine the high word. Similarly for low word -1 and
20451 less-or-equal-than or greater-than. */
20455 {
20458 {
20461 }
20465 {
20468 }
20472 }
20474 /* Otherwise, we need two or three jumps. */
20483 {
20497 }
20499 /*
20500 * a < b =>
20501 * if (hi(a) < hi(b)) goto true;
20502 * if (hi(a) > hi(b)) goto false;
20503 * if (lo(a) < lo(b)) goto true;
20504 * false:
20505 */
20517 }
20522 }
20523 }
20525 /* Split branch based on floating point condition. */
20526 void
20529 {
20530 rtx condition;
20531 rtx i;
20534 {
20537 }
20540 tmp);
20548 }
20550 void
20552 {
20553 rtx ret;
20560 }
20562 /* Expand comparison setting or clearing carry flag. Return true when
20563 successful and set pop for the operation. */
20564 static bool
20566 {
20567 machine_mode mode =
20570 /* Do not handle double-mode compares that go through special path. */
20575 {
20576 rtx compare_op;
20581 /* Shortcut: following common codes never translate
20582 into carry flag compares. */
20587 /* These comparisons require zero flag; swap operands so they won't. */
20590 {
20593 }
20595 /* Try to expand the comparison and verify that we end up with
20596 carry flag based comparison. This fails to be true only when
20597 we decide to expand comparison using arithmetic that is not
20598 too common scenario. */
20607 else
20616 }
20622 {
20627 /* Convert a==0 into (unsigned)a<1. */
20636 /* Convert a>b into b<a or a>=b-1. */
20640 {
20642 /* Bail out on overflow. We still can swap operands but that
20643 would force loading of the constant into register. */
20648 }
20649 else
20650 {
20653 }
20656 /* Convert a>=0 into (unsigned)a<0x80000000. */
20674 }
20675 /* Swapping operands may cause constant to appear as first operand. */
20677 {
20681 }
20685 }
20687 bool
20689 {
20692 rtx compare_op;
20714 /* Don't attempt mode expansion here -- if we had to expand 5 or 6
20715 HImode insns, we'd be swallowed in word prefix ops. */
20721 {
20725 HOST_WIDE_INT diff;
20728 /* Sign bit compares are better done using shifts than we do by using
20729 sbb. */
20732 {
20733 /* Detect overlap between destination and compare sources. */
20737 {
20738 rtx flags;
20747 {
20749 compare_code
20751 }
20753 /* To simplify rest of code, restrict to the GEU case. */
20755 {
20759 }
20760 else
20761 {
20764 reverse_condition_maybe_unordered
20766 else
20769 }
20778 else
20781 }
20782 else
20783 {
20786 else
20787 {
20790 }
20792 }
20795 {
20796 /*
20797 * cmpl op0,op1
20798 * sbbl dest,dest
20799 * [addl dest, ct]
20800 *
20801 * Size 5 - 8.
20802 */
20807 }
20809 {
20810 /*
20811 * cmpl op0,op1
20812 * sbbl dest,dest
20813 * orl $ct, dest
20814 *
20815 * Size 8.
20816 */
20820 }
20822 {
20823 /*
20824 * cmpl op0,op1
20825 * sbbl dest,dest
20826 * notl dest
20827 * [addl dest, cf]
20828 *
20829 * Size 8 - 11.
20830 */
20836 }
20837 else
20838 {
20839 /*
20840 * cmpl op0,op1
20841 * sbbl dest,dest
20842 * [notl dest]
20843 * andl cf - ct, dest
20844 * [addl dest, ct]
20845 *
20846 * Size 8 - 11.
20847 */
20850 {
20854 }
20864 }
20870 }
20873 {
20878 {
20881 /* We may be reversing unordered compare to normal compare, that
20882 is not valid in general (we may convert non-trapping condition
20883 to trapping one), however on i386 we currently emit all
20884 comparisons unordered. */
20886 }
20887 else
20890 {
20894 }
20895 }
20900 {
20905 {
20910 }
20911 }
20913 /* Optimize dest = (op0 < 0) ? -1 : cf. */
20917 {
20918 /* If lea code below could be used, only optimize
20919 if it results in a 2 insn sequence. */
20925 {
20926 /*
20927 * notl op1 (if necessary)
20928 * sarl $31, op1
20929 * orl cf, op1
20930 */
20932 {
20936 }
20947 }
20948 }
20956 {
20957 /*
20958 * xorl dest,dest
20959 * cmpl op1,op2
20960 * setcc dest
20961 * lea cf(dest*(ct-cf)),dest
20962 *
20963 * Size 14.
20964 *
20965 * This also catches the degenerate setcc-only case.
20966 */
20968 rtx tmp;
20974 /* On x86_64 the lea instruction operates on Pmode, so we need
20975 to get arithmetics done in proper mode to match. */
20978 else
20979 {
20980 rtx out1;
20983 nops++;
20985 {
20987 nops++;
20988 }
20989 }
20991 {
20993 nops++;
20994 }
20996 {
20999 else
21001 }
21006 }
21008 /*
21009 * General case: Jumpful:
21010 * xorl dest,dest cmpl op1, op2
21011 * cmpl op1, op2 movl ct, dest
21012 * setcc dest jcc 1f
21013 * decl dest movl cf, dest
21014 * andl (cf-ct),dest 1:
21015 * addl ct,dest
21016 *
21017 * Size 20. Size 14.
21018 *
21019 * This is reasonably steep, but branch mispredict costs are
21020 * high on modern cpus, so consider failing only if optimizing
21021 * for space.
21022 */
21027 {
21029 {
21034 {
21037 /* We may be reversing unordered compare to normal compare,
21038 that is not valid in general (we may convert non-trapping
21039 condition to trapping one), however on i386 we currently
21040 emit all comparisons unordered. */
21042 }
21043 else
21044 {
21048 }
21051 {
21055 }
21056 }
21059 {
21060 /* notl op1 (if needed)
21061 sarl $31, op1
21062 andl (cf-ct), op1
21063 addl ct, op1
21065 For x < 0 (resp. x <= -1) there will be no notl,
21066 so if possible swap the constants to get rid of the
21067 complement.
21068 True/false will be -1/0 while code below (store flag
21069 followed by decrement) is 0/-1, so the constants need
21070 to be exchanged once more. */
21073 {
21076 }
21077 else
21081 }
21082 else
21083 {
21087 constm1_rtx,
21089 }
21101 }
21102 }
21105 {
21106 /* Try a few things more with specific constants and a variable. */
21108 optab op;
21114 /* If one of the two operands is an interesting constant, load a
21115 constant with the above and mask it in with a logical operation. */
21118 {
21124 else
21126 }
21128 {
21134 else
21136 }
21137 else
21144 /* Recurse to get the constant loaded. */
21148 /* Mask in the interesting variable. */
21150 OPTAB_WIDEN);
21155 }
21157 /*
21158 * For comparison with above,
21159 *
21160 * movl cf,dest
21161 * movl ct,tmp
21162 * cmpl op1,op2
21163 * cmovcc tmp,dest
21164 *
21165 * Size 15.
21166 */
21188 }
21190 /* Swap, force into registers, or otherwise massage the two operands
21191 to an sse comparison with a mask result. Thus we differ a bit from
21192 ix86_prepare_fp_compare_args which expects to produce a flags result.
21194 The DEST operand exists to help determine whether to commute commutative
21195 operators. The POP0/POP1 operands are updated in place. The new
21196 comparison code is returned, or UNKNOWN if not implementable. */
21198 static enum rtx_code
21201 {
21203 {
21206 /* AVX supports all the needed comparisons. */
21209 /* We have no LTGT as an operator. We could implement it with
21210 NE & ORDERED, but this requires an extra temporary. It's
21211 not clear that it's worth it. */
21218 /* These are supported directly. */
21225 /* AVX has 3 operand comparisons, no need to swap anything. */
21228 /* For commutative operators, try to canonicalize the destination
21229 operand to be first in the comparison - this helps reload to
21230 avoid extra moves. */
21233 /* FALLTHRU */
21239 /* These are not supported directly before AVX, and furthermore
21240 ix86_expand_sse_fp_minmax only optimizes LT/UNGE. Swap the
21241 comparison operands to transform into something that is
21242 supported. */
21249 }
21252 }
21254 /* Detect conditional moves that exactly match min/max operational
21255 semantics. Note that this is IEEE safe, as long as we don't
21256 interchange the operands.
21258 Returns FALSE if this conditional move doesn't match a MIN/MAX,
21259 and TRUE if the operation is successful and instructions are emitted. */
21261 static bool
21264 {
21265 machine_mode mode;
21267 rtx tmp;
21270 ;
21273 else
21280 else
21285 /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here,
21286 but MODE may be a vector mode and thus not appropriate. */
21288 {
21290 rtvec v;
21295 }
21296 else
21297 {
21300 }
21304 }
21306 /* Expand an sse vector comparison. Return the register with the result. */
21308 static rtx
21311 {
21315 /* In general case result of comparison can differ from operands' type. */
21316 machine_mode cmp_mode;
21318 /* In AVX512F the result of comparison is an integer mask. */
21320 rtx x;
21323 {
21328 }
21329 else
21342 /* Compare patterns for int modes are unspec in AVX512F only. */
21344 {
21348 {
21365 }
21368 {
21371 }
21372 }
21376 {
21379 }
21380 else
21384 }
21386 /* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical
21387 operations. This is used for both scalar and vector conditional moves. */
21389 static void
21391 {
21395 /* In AVX512F the result of comparison is an integer mask. */
21403 {
21405 }
21408 {
21412 }
21415 {
21420 }
21423 {
21427 }
21430 {
21437 op_true,
21438 op_false)));
21439 }
21440 else
21441 {
21451 {
21465 {
21472 }
21487 {
21494 }
21518 }
21521 {
21525 }
21526 else
21527 {
21533 else
21545 }
21546 }
21547 }
21549 /* Expand a floating-point conditional move. Return true if successful. */
21551 bool
21553 {
21561 {
21562 machine_mode cmode;
21564 /* Since we've no cmove for sse registers, don't force bad register
21565 allocation just to gain access to it. Deny movcc when the
21566 comparison mode doesn't match the move mode. */
21585 }
21592 /* The floating point conditional move instructions don't directly
21593 support conditions resulting from a signed integer comparison. */
21597 {
21602 }
21609 }
21611 /* Expand a floating-point vector conditional move; a vcond operation
21612 rather than a movcc operation. */
21614 bool
21616 {
21618 rtx cmp;
21623 {
21624 rtx temp;
21626 {
21643 }
21645 OPTAB_DIRECT);
21648 }
21658 }
21660 /* Expand a signed/unsigned integral vector conditional move. */
21662 bool
21664 {
21674 /* Try to optimize x < 0 ? -1 : 0 into (signed) x >> 31
21675 and x < 0 ? 1 : 0 into (unsigned) x >> 31. */
21684 {
21688 {
21694 }
21697 {
21703 }
21704 }
21713 /* XOP supports all of the comparisons on all 128-bit vector int types. */
21717 ;
21718 else
21719 {
21720 /* Canonicalize the comparison to EQ, GT, GTU. */
21722 {
21739 /* FALLTHRU */
21749 }
21751 /* Only SSE4.1/SSE4.2 supports V2DImode. */
21753 {
21755 {
21757 /* SSE4.1 supports EQ. */
21764 /* SSE4.2 supports GT/GTU. */
21771 }
21772 }
21774 /* Unsigned parallel compare is not supported by the hardware.
21775 Play some tricks to turn this into a signed comparison
21776 against 0. */
21778 {
21782 {
21789 {
21794 {
21803 }
21804 /* Subtract (-(INT MAX) - 1) from both operands to make
21805 them signed. */
21816 }
21825 /* Perform a parallel unsigned saturating subtraction. */
21837 }
21838 }
21839 }
21841 /* Allow the comparison to be done in one mode, but the movcc to
21842 happen in another mode. */
21844 {
21847 }
21848 else
21849 {
21855 }
21860 }
21862 /* AVX512F does support 64-byte integer vector operations,
21863 thus the longest vector we are faced with is V64QImode. */
21864 #define MAX_VECT_LEN 64
21866 struct expand_vec_perm_d
21867 {
21870 machine_mode vmode;
21874 };
21876 static bool
21879 {
21880 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
21881 expander, so args are either in d, or in op0, op1 etc. */
21887 {
21918 {
21921 }
21925 {
21928 }
21932 {
21935 }
21951 {
21954 }
21958 {
21961 }
21965 {
21968 }
21972 }
21977 /* ix86_expand_vec_perm_vpermi2 is called from both const and non-const
21978 expander, so args are either in d, or in op0, op1 etc. */
21980 {
21988 }
21992 }
21994 /* Expand a variable vector permutation. */
21996 void
21998 {
22009 /* Number of elements in the vector. */
22018 {
22020 {
22021 /* Unfortunately, the VPERMQ and VPERMPD instructions only support
22022 an constant shuffle operand. With a tiny bit of effort we can
22023 use VPERMD instead. A re-interpretation stall for V4DFmode is
22024 unfortunate but there's no avoiding it.
22025 Similarly for V16HImode we don't have instructions for variable
22026 shuffling, while for V32QImode we can use after preparing suitable
22027 masks vpshufb; vpshufb; vpermq; vpor. */
22030 {
22034 }
22035 else
22036 {
22040 }
22043 /* Replicate the low bits of the V4DImode mask into V8SImode:
22044 mask = { A B C D }
22045 t1 = { A A B B C C D D }. */
22053 else
22056 /* Multiply the shuffle indicies by two. */
22058 OPTAB_DIRECT);
22060 /* Add one to the odd shuffle indicies:
22061 t1 = { A*2, A*2+1, B*2, B*2+1, ... }. */
22063 {
22066 }
22070 OPTAB_DIRECT);
22072 /* Continue as if V8SImode (resp. V32QImode) was used initially. */
22077 }
22080 {
22082 /* The VPERMD and VPERMPS instructions already properly ignore
22083 the high bits of the shuffle elements. No need for us to
22084 perform an AND ourselves. */
22086 {
22091 }
22092 else
22093 {
22099 }
22106 else
22107 {
22113 }
22117 /* By combining the two 128-bit input vectors into one 256-bit
22118 input vector, we can use VPERMD and VPERMPS for the full
22119 two-operand shuffle. */
22151 /* From mask create two adjusted masks, which contain the same
22152 bits as mask in the low 7 bits of each vector element.
22153 The first mask will have the most significant bit clear
22154 if it requests element from the same 128-bit lane
22155 and MSB set if it requests element from the other 128-bit lane.
22156 The second mask will have the opposite values of the MSB,
22157 and additionally will have its 128-bit lanes swapped.
22158 E.g. { 07 12 1e 09 ... | 17 19 05 1f ... } mask vector will have
22159 t1 { 07 92 9e 09 ... | 17 19 85 1f ... } and
22160 t3 { 97 99 05 9f ... | 87 12 1e 89 ... } where each ...
22161 stands for other 12 bytes. */
22162 /* The bit whether element is from the same lane or the other
22163 lane is bit 4, so shift it up by 3 to the MSB position. */
22167 /* Clear MSB bits from the mask just in case it had them set. */
22169 /* After this t1 will have MSB set for elements from other lane. */
22171 /* Clear bits other than MSB. */
22173 /* Or in the lower bits from mask into t3. */
22175 /* And invert MSB bits in t1, so MSB is set for elements from the same
22176 lane. */
22178 /* Swap 128-bit lanes in t3. */
22183 /* And or in the lower bits from mask into t1. */
22186 {
22187 /* Each of these shuffles will put 0s in places where
22188 element from the other 128-bit lane is needed, otherwise
22189 will shuffle in the requested value. */
22193 /* For t3 the 128-bit lanes are swapped again. */
22198 /* And oring both together leads to the result. */
22205 }
22208 /* Similarly to the above one_operand_shuffle code,
22209 just for repeated twice for each operand. merge_two:
22210 code will merge the two results together. */
22234 }
22235 }
22238 {
22239 /* The XOP VPPERM insn supports three inputs. By ignoring the
22240 one_operand_shuffle special case, we avoid creating another
22241 set of constant vectors in memory. */
22244 /* mask = mask & {2*w-1, ...} */
22246 }
22247 else
22248 {
22249 /* mask = mask & {w-1, ...} */
22251 }
22259 /* For non-QImode operations, convert the word permutation control
22260 into a byte permutation control. */
22262 {
22267 /* Convert mask to vector of chars. */
22270 /* Replicate each of the input bytes into byte positions:
22271 (v2di) --> {0,0,0,0,0,0,0,0, 8,8,8,8,8,8,8,8}
22272 (v4si) --> {0,0,0,0, 4,4,4,4, 8,8,8,8, 12,12,12,12}
22273 (v8hi) --> {0,0, 2,2, 4,4, 6,6, ...}. */
22280 else
22283 /* Convert it into the byte positions by doing
22284 mask = mask + {0,1,..,16/w, 0,1,..,16/w, ...} */
22290 }
22292 /* The actual shuffle operations all operate on V16QImode. */
22297 {
22304 }
22306 {
22313 }
22314 else
22315 {
22319 /* Shuffle the two input vectors independently. */
22325 merge_two:
22326 /* Then merge them together. The key is whether any given control
22327 element contained a bit set that indicates the second word. */
22331 {
22332 /* Without SSE4.1, we don't have V2DImode EQ. Perform one
22333 more shuffle to convert the V2DI input mask into a V4SI
22334 input mask. At which point the masking that expand_int_vcond
22335 will work as desired. */
22343 }
22365 }
22366 }
22368 /* Unpack OP[1] into the next wider integer vector type. UNSIGNED_P is
22369 true if we should do zero extension, else sign extension. HIGH_P is
22370 true if we want the N/2 high elements, else the low elements. */
22372 void
22374 {
22376 rtx tmp;
22379 {
22385 {
22389 else
22392 extract
22398 else
22401 extract
22407 else
22410 extract
22416 else
22419 extract
22425 else
22428 extract
22434 else
22437 extract
22443 else
22449 else
22455 else
22460 }
22463 {
22466 }
22468 {
22469 /* Shift higher 8 bytes to lower 8 bytes. */
22474 }
22475 else
22479 }
22480 else
22481 {
22485 {
22489 else
22495 else
22501 else
22506 }
22510 else
22517 }
22518 }
22520 /* Expand conditional increment or decrement using adb/sbb instructions.
22521 The default case using setcc followed by the conditional move can be
22522 done by generic code. */
22523 bool
22525 {
22527 rtx flags;
22529 rtx compare_op;
22532 machine_mode mode;
22547 {
22550 }
22553 {
22557 reverse_condition_maybe_unordered
22559 else
22561 }
22565 /* Construct either adc or sbb insn. */
22567 {
22569 {
22584 }
22585 }
22586 else
22587 {
22589 {
22604 }
22605 }
22609 }
22612 /* Split operands 0 and 1 into half-mode parts. Similar to split_double_mode,
22613 but works for floating pointer parameters and nonoffsetable memories.
22614 For pushes, it returns just stack offsets; the values will be saved
22615 in the right order. Maximally three parts are generated. */
22617 static int
22619 {
22624 else
22630 /* Optimize constant pool reference to immediates. This is used by fp
22631 moves, that force all constants to memory to allow combining. */
22633 {
22637 }
22640 {
22641 /* The only non-offsetable memories we handle are pushes. */
22650 }
22653 {
22655 /* Caution: if we looked through a constant pool memory above,
22656 the operand may actually have a different mode now. That's
22657 ok, since we want to pun this all the way back to an integer. */
22661 }
22664 {
22667 else
22668 {
22672 {
22676 }
22678 {
22683 }
22685 {
22686 REAL_VALUE_TYPE r;
22691 {
22698 /* We can't use REAL_VALUE_TO_TARGET_LONG_DOUBLE since
22699 long double may not be 80-bit. */
22708 }
22711 }
22712 else
22714 }
22715 }
22716 else
22717 {
22721 {
22724 {
22728 }
22730 {
22734 }
22736 {
22737 REAL_VALUE_TYPE r;
22743 /* real_to_target puts 32-bit pieces in each long. */
22745 gen_int_mode
22748 DImode);
22752 else
22754 gen_int_mode
22757 DImode);
22758 }
22759 else
22761 }
22762 }
22765 }
22767 /* Emit insns to perform a move or push of DI, DF, XF, and TF values.
22768 Return false when normal moves are needed; true when all required
22769 insns have been emitted. Operands 2-4 contain the input values
22770 int the correct order; operands 5-7 contain the output values. */
22772 void
22774 {
22782 /* The DFmode expanders may ask us to move double.
22783 For 64bit target this is single move. By hiding the fact
22784 here we simplify i386.md splitters. */
22786 {
22787 /* Optimize constant pool reference to immediates. This is used by
22788 fp moves, that force all constants to memory to allow combining. */
22795 {
22798 }
22799 else
22804 }
22806 /* The only non-offsettable memory we handle is push. */
22809 else
22816 /* When emitting push, take care for source operands on the stack. */
22819 {
22822 /* Compensate for the stack decrement by 4. */
22827 /* src_base refers to the stack pointer and is
22828 automatically decreased by emitted push. */
22832 }
22834 /* We need to do copy in the right order in case an address register
22835 of the source overlaps the destination. */
22837 {
22838 rtx tmp;
22841 {
22845 collisions++;
22846 }
22848 /* Collision in the middle part can be handled by reordering. */
22850 {
22853 }
22857 {
22859 {
22862 }
22863 else
22864 {
22867 }
22868 }
22870 /* If there are more collisions, we can't handle it by reordering.
22871 Do an lea to the last part and use only one colliding move. */
22873 {
22880 /* Handle the case when the last part isn't valid for lea.
22881 Happens in 64-bit mode storing the 12-byte XFmode. */
22887 {
22892 {
22893 /* It is not valid to use %gs: or %fs: in
22894 lea though, so we need to remove it from the
22895 address used for lea and add it to each individual
22896 memory loads instead. */
22900 {
22902 {
22908 {
22912 }
22913 }
22917 }
22919 }
22920 }
22926 {
22931 }
22932 }
22933 }
22936 {
22938 {
22940 {
22945 }
22947 {
22950 }
22951 }
22952 else
22953 {
22954 /* In 64bit mode we don't have 32bit push available. In case this is
22955 register, it is OK - we will just use larger counterpart. We also
22956 retype memory - these comes from attempt to avoid REX prefix on
22957 moving of second half of TFmode value. */
22959 {
22961 {
22972 }
22976 }
22977 }
22981 }
22983 /* Choose correct order to not overwrite the source before it is copied. */
22993 {
22995 {
22998 }
22999 }
23000 else
23001 {
23003 {
23006 }
23007 }
23009 /* If optimizing for size, attempt to locally unCSE nonzero constants. */
23011 {
23020 }
23026 }
23028 /* Helper function of ix86_split_ashl used to generate an SImode/DImode
23029 left shift by a constant, either using a single shift or
23030 a sequence of add instructions. */
23032 static void
23034 {
23040 {
23044 }
23045 else
23046 {
23049 }
23050 }
23052 void
23054 {
23063 {
23068 {
23074 }
23075 else
23076 {
23084 }
23086 }
23093 {
23094 /* Assuming we've chosen a QImode capable registers, then 1 << N
23095 can be done with two 32/64-bit shifts, no branches, no cmoves. */
23097 {
23113 }
23115 /* Otherwise, we can get the same results by manually performing
23116 a bit extract operation on bit 5/6, and then performing the two
23117 shifts. The two methods of getting 0/1 into low/high are exactly
23118 the same size. Avoiding the shift in the bit extract case helps
23119 pentium4 a bit; no one else seems to care much either way. */
23120 else
23121 {
23122 machine_mode half_mode;
23126 HOST_WIDE_INT bits;
23127 rtx x;
23130 {
23136 }
23137 else
23138 {
23144 }
23148 else
23156 }
23161 }
23164 {
23165 /* For -1 << N, we can avoid the shld instruction, because we
23166 know that we're shifting 0...31/63 ones into a -1. */
23170 else
23172 }
23173 else
23174 {
23182 }
23187 {
23193 }
23194 else
23195 {
23200 }
23201 }
23203 void
23205 {
23215 {
23220 {
23226 }
23228 {
23237 }
23238 else
23239 {
23247 }
23248 }
23249 else
23250 {
23262 {
23270 scratch));
23271 }
23272 else
23273 {
23278 }
23279 }
23280 }
23282 void
23284 {
23294 {
23299 {
23306 }
23307 else
23308 {
23316 }
23317 }
23318 else
23319 {
23331 {
23337 scratch));
23338 }
23339 else
23340 {
23345 }
23346 }
23347 }
23349 /* Predict just emitted jump instruction to be taken with probability PROB. */
23350 static void
23352 {
23356 }
23358 /* Helper function for the string operations below. Dest VARIABLE whether
23359 it is aligned to VALUE bytes. If true, jump to the label. */
23362 {
23367 else
23373 else
23376 }
23378 /* Adjust COUNTER by the VALUE. */
23379 static void
23381 {
23386 }
23388 /* Zero extend possibly SImode EXP to Pmode register. */
23389 rtx
23391 {
23393 }
23395 /* Divide COUNTREG by SCALE. */
23396 static rtx
23398 {
23399 rtx sc;
23411 }
23413 /* Return mode for the memcpy/memset loop counter. Prefer SImode over
23414 DImode for constant loop counts. */
23416 static machine_mode
23418 {
23426 }
23428 /* Copy the address to a Pmode register. This is used for x32 to
23429 truncate DImode TLS address to a SImode register. */
23431 static rtx
23433 {
23434 rtx reg;
23436 {
23440 }
23441 else
23442 {
23447 }
23448 }
23450 /* When ISSETMEM is FALSE, output simple loop to move memory pointer to SRCPTR
23451 to DESTPTR via chunks of MODE unrolled UNROLL times, overall size is COUNT
23452 specified in bytes. When ISSETMEM is TRUE, output the equivalent loop to set
23453 memory by VALUE (supposed to be in MODE).
23455 The size is rounded down to whole number of chunk size moved at once.
23456 SRCMEM and DESTMEM provide MEMrtx to feed proper aliasing info. */
23459 static void
23464 {
23471 rtx size;
23480 /* Those two should combine. */
23482 {
23486 }
23493 /* This assert could be relaxed - in this case we'll need to compute
23494 smallest power of two, containing in PIECE_SIZE_N and pass it to
23495 offset_address. */
23501 {
23505 /* When unrolling for chips that reorder memory reads and writes,
23506 we can save registers by using single temporary.
23507 Also using 4 temporaries is overkill in 32bit mode. */
23509 {
23511 {
23513 {
23514 destmem =
23516 srcmem =
23518 }
23520 }
23521 }
23522 else
23523 {
23527 {
23530 {
23531 srcmem =
23533 }
23535 }
23537 {
23539 {
23540 destmem =
23542 }
23544 }
23545 }
23546 }
23547 else
23549 {
23551 destmem =
23554 }
23564 {
23570 else
23572 }
23573 else
23581 {
23586 }
23588 }
23590 /* Output "rep; mov" or "rep; stos" instruction depending on ISSETMEM argument.
23591 When ISSETMEM is true, arguments SRCMEM and SRCPTR are ignored.
23592 When ISSETMEM is false, arguments VALUE and ORIG_VALUE are ignored.
23593 For setmem case, VALUE is a promoted to a wider size ORIG_VALUE.
23594 ORIG_VALUE is the original value passed to memset to fill the memory with.
23595 Other arguments have same meaning as for previous function. */
23597 static void
23600 rtx count,
23602 {
23603 rtx destexp;
23604 rtx srcexp;
23605 rtx countreg;
23606 HOST_WIDE_INT rounded_count;
23608 /* If possible, it is shorter to use rep movs.
23609 TODO: Maybe it is better to move this logic to decide_alg. */
23620 {
23624 }
23625 else
23628 {
23633 }
23638 {
23641 }
23642 else
23643 {
23647 {
23651 }
23652 else
23655 {
23660 }
23661 else
23662 {
23665 }
23668 }
23669 }
23671 /* This function emits moves to copy SIZE_TO_MOVE bytes from SRCMEM to
23672 DESTMEM.
23673 SRC is passed by pointer to be updated on return.
23674 Return value is updated DST. */
23675 static rtx
23677 HOST_WIDE_INT size_to_move)
23678 {
23681 machine_mode move_mode;
23684 /* Find the widest mode in which we could perform moves.
23685 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23686 it until move of such size is supported. */
23691 {
23695 }
23697 /* Find the corresponding vector mode with the same size as MOVE_MODE.
23698 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
23700 {
23705 {
23709 }
23710 }
23716 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23720 {
23721 /* We move from memory to memory, so we'll need to do it via
23722 a temporary register. */
23733 piece_size);
23735 piece_size);
23736 }
23738 /* Update DST and SRC rtx. */
23741 }
23743 /* Output code to copy at most count & (max_size - 1) bytes from SRC to DEST. */
23744 static void
23747 {
23750 {
23755 /* For now MAX_SIZE should be a power of 2. This assert could be
23756 relaxed, but it'll require a bit more complicated epilogue
23757 expanding. */
23760 {
23763 }
23765 }
23767 {
23773 }
23775 /* When there are stringops, we can cheaply increase dest and src pointers.
23776 Otherwise we save code size by maintaining offset (zero is readily
23777 available from preceding rep operation) and using x86 addressing modes.
23778 */
23780 {
23782 {
23789 }
23791 {
23798 }
23800 {
23807 }
23808 }
23809 else
23810 {
23812 rtx tmp;
23815 {
23826 }
23828 {
23841 }
23843 {
23852 }
23853 }
23854 }
23856 /* This function emits moves to fill SIZE_TO_MOVE bytes starting from DESTMEM
23857 with value PROMOTED_VAL.
23858 SRC is passed by pointer to be updated on return.
23859 Return value is updated DST. */
23860 static rtx
23862 HOST_WIDE_INT size_to_move)
23863 {
23866 machine_mode move_mode;
23869 /* Find the widest mode in which we could perform moves.
23870 Start with the biggest power of 2 less than SIZE_TO_MOVE and half
23871 it until move of such size is supported. */
23876 {
23879 }
23886 /* Emit moves. We'll need SIZE_TO_MOVE/PIECE_SIZES moves. */
23890 {
23892 {
23895 piece_size);
23897 }
23905 piece_size);
23906 }
23908 /* Update DST rtx. */
23910 }
23911 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23912 static void
23915 {
23916 count =
23922 }
23924 /* Output code to set at most count & (max_size - 1) bytes starting by DEST. */
23925 static void
23928 {
23929 rtx dest;
23932 {
23937 /* For now MAX_SIZE should be a power of 2. This assert could be
23938 relaxed, but it'll require a bit more complicated epilogue
23939 expanding. */
23942 {
23944 {
23947 else
23949 }
23950 }
23952 }
23954 {
23957 }
23959 {
23962 {
23967 }
23968 else
23969 {
23978 }
23981 }
23983 {
23986 {
23989 }
23990 else
23991 {
23996 }
23999 }
24001 {
24007 }
24009 {
24015 }
24017 {
24023 }
24024 }
24026 /* Depending on ISSETMEM, copy enough from SRCMEM to DESTMEM or set enough to
24027 DESTMEM to align it to DESIRED_ALIGNMENT. Original alignment is ALIGN.
24028 Depending on ISSETMEM, either arguments SRCMEM/SRCPTR or VALUE/VEC_VALUE are
24029 ignored.
24030 Return value is updated DESTMEM. */
24031 static rtx
24036 {
24039 {
24041 {
24044 {
24047 else
24049 }
24050 else
24056 }
24057 }
24059 }
24061 /* Test if COUNT&SIZE is nonzero and if so, expand movme
24062 or setmem sequence that is valid for SIZE..2*SIZE-1 bytes
24063 and jump to DONE_LABEL. */
24064 static void
24070 {
24073 rtx modesize;
24076 /* If we do not have vector value to copy, we must reduce size. */
24078 {
24080 {
24085 }
24086 else
24088 }
24089 else
24090 {
24091 /* Choose appropriate vector mode. */
24097 }
24102 {
24105 else
24106 {
24109 }
24111 }
24117 {
24121 }
24123 {
24126 else
24127 {
24130 }
24132 }
24138 }
24140 /* Handle small memcpy (up to SIZE that is supposed to be small power of 2.
24141 and get ready for the main memcpy loop by copying iniital DESIRED_ALIGN-ALIGN
24142 bytes and last SIZE bytes adjusitng DESTPTR/SRCPTR/COUNT in a way we can
24143 proceed with an loop copying SIZE bytes at once. Do moves in MODE.
24144 DONE_LABEL is a label after the whole copying sequence. The label is created
24145 on demand if *DONE_LABEL is NULL.
24146 MIN_SIZE is minimal size of block copied. This value gets adjusted for new
24147 bounds after the initial copies.
24149 DESTMEM/SRCMEM are memory expressions pointing to the copies block,
24150 DESTPTR/SRCPTR are pointers to the block. DYNAMIC_CHECK indicate whether
24151 we will dispatch to a library call for large blocks.
24153 In pseudocode we do:
24155 if (COUNT < SIZE)
24156 {
24157 Assume that SIZE is 4. Bigger sizes are handled analogously
24158 if (COUNT & 4)
24159 {
24160 copy 4 bytes from SRCPTR to DESTPTR
24161 copy 4 bytes from SRCPTR + COUNT - 4 to DESTPTR + COUNT - 4
24162 goto done_label
24163 }
24164 if (!COUNT)
24165 goto done_label;
24166 copy 1 byte from SRCPTR to DESTPTR
24167 if (COUNT & 2)
24168 {
24169 copy 2 bytes from SRCPTR to DESTPTR
24170 copy 2 bytes from SRCPTR + COUNT - 2 to DESTPTR + COUNT - 2
24171 }
24172 }
24173 else
24174 {
24175 copy at least DESIRED_ALIGN-ALIGN bytes from SRCPTR to DESTPTR
24176 copy SIZE bytes from SRCPTR + COUNT - SIZE to DESTPTR + COUNT -SIZE
24178 OLD_DESPTR = DESTPTR;
24179 Align DESTPTR up to DESIRED_ALIGN
24180 SRCPTR += DESTPTR - OLD_DESTPTR
24181 COUNT -= DEST_PTR - OLD_DESTPTR
24182 if (DYNAMIC_CHECK)
24183 Round COUNT down to multiple of SIZE
24184 << optional caller supplied zero size guard is here >>
24185 << optional caller suppplied dynamic check is here >>
24186 << caller supplied main copy loop is here >>
24187 }
24188 done_label:
24189 */
24190 static void
24193 machine_mode mode,
24203 {
24206 rtx modesize;
24208 rtx mode_value;
24210 /* Chose proper value to copy. */
24213 else
24217 /* See if block is big or small, handle small blocks. */
24219 {
24230 /* Handle sizes > 3. */
24237 /* Nothing to copy? Jump to DONE_LABEL if so */
24241 /* Do a byte copy. */
24245 else
24246 {
24249 }
24251 /* Handle sizes 2 and 3. */
24258 else
24259 {
24264 }
24270 }
24271 else
24275 /* Start memcpy for COUNT >= SIZE. */
24277 {
24280 }
24282 /* Copy first desired_align bytes. */
24288 {
24291 else
24292 {
24295 }
24298 }
24301 /* Copy last SIZE bytes. */
24308 else
24309 {
24315 }
24317 {
24321 else
24322 {
24325 }
24326 }
24328 /* Align destination. */
24330 {
24334 /* Align destptr up, place it to new register. */
24343 /* See how many bytes we skipped. */
24347 /* Adjust srcptr and count. */
24353 /* We copied at most size + prolog_size. */
24356 else
24359 /* Our loops always round down the bock size, but for dispatch to library
24360 we need precise value. */
24364 }
24365 else
24366 {
24368 /* Decrease count, so we won't end up copying last word twice. */
24372 else
24376 }
24377 }
24380 /* This function is like the previous one, except here we know how many bytes
24381 need to be copied. That allows us to update alignment not only of DST, which
24382 is returned, but also of SRC, which is passed as a pointer for that
24383 reason. */
24384 static rtx
24389 {
24397 {
24401 }
24406 {
24408 {
24410 {
24413 else
24415 }
24416 else
24419 }
24420 }
24427 {
24433 {
24436 {
24440 }
24445 }
24449 }
24452 }
24454 /* Return true if ALG can be used in current context.
24455 Assume we expand memset if MEMSET is true. */
24456 static bool
24458 {
24463 /* Algorithms using the rep prefix want at least edi and ecx;
24464 additionally, memset wants eax and memcpy wants esi. Don't
24465 consider such algorithms if the user has appropriated those
24466 registers for their own purposes. */
24473 }
24475 /* Given COUNT and EXPECTED_SIZE, decide on codegen of string operation. */
24476 static enum stringop_alg
24480 {
24491 /* Even if the string operation call is cold, we still might spend a lot
24492 of time processing large blocks. */
24498 else
24504 else
24507 /* See maximal size for user defined algorithm. */
24509 {
24516 }
24518 /* If expected size is not known but max size is small enough
24519 so inline version is a win, set expected size into
24520 the range. */
24525 /* If user specified the algorithm, honnor it if possible. */
24529 /* rep; movq or rep; movl is the smallest variant. */
24531 {
24536 else
24539 }
24540 /* Very tiny blocks are best handled via the loop, REP is expensive to
24541 setup. */
24545 {
24549 {
24550 /* We get here if the algorithms that were not libcall-based
24551 were rep-prefix based and we are unable to use rep prefixes
24552 based on global register usage. Break out of the loop and
24553 use the heuristic below. */
24557 {
24561 {
24564 }
24565 /* Honor TARGET_INLINE_ALL_STRINGOPS by picking
24566 last non-libcall inline algorithm. */
24568 {
24569 /* When the current size is best to be copied by a libcall,
24570 but we are still forced to inline, run the heuristic below
24571 that will pick code for medium sized blocks. */
24573 {
24576 }
24579 }
24581 {
24584 }
24585 }
24586 }
24587 }
24588 /* When asked to inline the call anyway, try to pick meaningful choice.
24589 We look for maximal size of block that is faster to copy by hand and
24590 take blocks of at most of that size guessing that average size will
24591 be roughly half of the block.
24593 If this turns out to be bad, we might simply specify the preferred
24594 choice in ix86_costs. */
24598 {
24601 /* If there aren't any usable algorithms, then recursing on
24602 smaller sizes isn't going to find anything. Just return the
24603 simple byte-at-a-time copy loop. */
24605 {
24606 /* Pick something reasonable. */
24610 }
24618 else
24621 }
24624 }
24626 /* Decide on alignment. We know that the operand is already aligned to ALIGN
24627 (ALIGN can be based on profile feedback and thus it is not 100% guaranteed). */
24628 static int
24632 machine_mode move_mode)
24633 {
24644 /* PentiumPro has special logic triggering for 8 byte aligned blocks.
24645 copying whole cacheline at once. */
24658 }
24661 /* Helper function for memcpy. For QImode value 0xXY produce
24662 0xXYXYXYXY of wide specified by MODE. This is essentially
24663 a * 0x10101010, but we can do slightly better than
24664 synth_mult by unwinding the sequence by hand on CPUs with
24665 slow multiply. */
24666 static rtx
24668 {
24670 rtx tmp;
24677 {
24685 }
24694 nops--;
24699 {
24703 OPTAB_DIRECT);
24704 }
24705 else
24706 {
24712 else
24714 else
24715 {
24718 reg =
24720 }
24730 }
24731 }
24733 /* Duplicate value VAL using promote_duplicated_reg into maximal size that will
24734 be needed by main loop copying SIZE_NEEDED chunks and prologue getting
24735 alignment from ALIGN to DESIRED_ALIGN. */
24736 static rtx
24739 {
24740 rtx promoted_val;
24749 else
24753 }
24755 /* Expand string move (memcpy) ot store (memset) operation. Use i386 string
24756 operations when profitable. The code depends upon architecture, block size
24757 and alignment, but always has one of the following overall structures:
24759 Aligned move sequence:
24761 1) Prologue guard: Conditional that jumps up to epilogues for small
24762 blocks that can be handled by epilogue alone. This is faster
24763 but also needed for correctness, since prologue assume the block
24764 is larger than the desired alignment.
24766 Optional dynamic check for size and libcall for large
24767 blocks is emitted here too, with -minline-stringops-dynamically.
24769 2) Prologue: copy first few bytes in order to get destination
24770 aligned to DESIRED_ALIGN. It is emitted only when ALIGN is less
24771 than DESIRED_ALIGN and up to DESIRED_ALIGN - ALIGN bytes can be
24772 copied. We emit either a jump tree on power of two sized
24773 blocks, or a byte loop.
24775 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24776 with specified algorithm.
24778 4) Epilogue: code copying tail of the block that is too small to be
24779 handled by main body (or up to size guarded by prologue guard).
24781 Misaligned move sequence
24783 1) missaligned move prologue/epilogue containing:
24784 a) Prologue handling small memory blocks and jumping to done_label
24785 (skipped if blocks are known to be large enough)
24786 b) Signle move copying first DESIRED_ALIGN-ALIGN bytes if alignment is
24787 needed by single possibly misaligned move
24788 (skipped if alignment is not needed)
24789 c) Copy of last SIZE_NEEDED bytes by possibly misaligned moves
24791 2) Zero size guard dispatching to done_label, if needed
24793 3) dispatch to library call, if needed,
24795 3) Main body: the copying loop itself, copying in SIZE_NEEDED chunks
24796 with specified algorithm. */
24797 bool
24803 {
24804 rtx destreg;
24807 rtx tmp;
24823 /* TODO: Once value ranges are available, fill in proper data. */
24831 /* i386 can do misaligned access on reasonably increased cost. */
24835 /* ALIGN is the minimum of destination and source alignment, but we care here
24836 just about destination alignment. */
24842 {
24845 /* When COUNT is 0, there is nothing to do. */
24848 }
24849 else
24850 {
24859 }
24861 /* Make sure we don't need to care about overflow later on. */
24865 /* Step 0: Decide on preferred algorithm, desired alignment and
24866 size of chunks to be copied by main loop. */
24868 issetmem,
24875 /* For now vector-version of memset is generated only for memory zeroing, as
24876 creating of promoted vector value is very cheap in this case. */
24889 {
24908 /* Find the widest supported mode. */
24914 /* Find the corresponding vector mode with the same size as MOVE_MODE.
24915 MOVE_MODE is an integer mode at the moment (SI, DI, TI, etc.). */
24917 {
24922 }
24934 }
24942 /* Step 1: Prologue guard. */
24944 /* Alignment code needs count to be in register. */
24946 {
24949 {
24950 align_bytes
24954 else
24956 }
24959 }
24962 /* Misaligned move sequences handle both prologue and epilogue at once.
24963 Default code generation results in a smaller code for large alignments
24964 and also avoids redundant job when sizes are known precisely. */
24965 misaligned_prologue_used
24966 = (TARGET_MISALIGNED_MOVE_STRING_PRO_EPILOGUES
24972 /* Do the cheap promotion to allow better CSE across the
24973 main loop and epilogue (ie one load of the big constant in the
24974 front of all code.
24975 For now the misaligned move sequences do not have fast path
24976 without broadcasting. */
24978 {
24980 {
24986 }
24987 else
24988 {
24991 }
24992 }
24993 /* Misaligned move sequences handles both prologues and epilogues at once.
24994 Default code generation results in smaller code for large alignments and
24995 also avoids redundant job when sizes are known precisely. */
24997 {
24998 /* Misaligned move prologue handled small blocks by itself. */
24999 expand_set_or_movmem_prologue_epilogue_by_misaligned_moves
25004 desired_align < align
25013 {
25014 /* It is possible that we copied enough so the main loop will not
25015 execute. */
25025 else
25027 }
25028 }
25029 /* Ensure that alignment prologue won't copy past end of block. */
25031 {
25033 /* Epilogue always copies COUNT_EXP & EPILOGUE_SIZE_NEEDED bytes.
25034 Make sure it is power of 2. */
25037 /* To improve performance of small blocks, we jump around the VAL
25038 promoting mode. This mean that if the promoted VAL is not constant,
25039 we might not use it in the epilogue and have to use byte
25040 loop variant. */
25045 {
25046 /* If main algorithm works on QImode, no epilogue is needed.
25047 For small sizes just don't align anything. */
25050 else
25052 }
25055 {
25062 else
25064 }
25065 }
25067 /* Emit code to decide on runtime whether library call or inline should be
25068 used. */
25070 {
25072 {
25074 {
25078 }
25079 }
25080 else
25081 {
25091 else
25095 }
25096 }
25098 /* Step 2: Alignment prologue. */
25099 /* Do the expensive promotion once we branched off the small blocks. */
25105 {
25107 {
25108 /* Except for the first move in prologue, we no longer know
25109 constant offset in aliasing info. It don't seems to worth
25110 the pain to maintain it for the first move, so throw away
25111 the info early. */
25118 issetmem);
25119 /* At most desired_align - align bytes are copied. */
25122 else
25124 }
25125 else
25126 {
25127 /* If we know how many bytes need to be stored before dst is
25128 sufficiently aligned, maintain aliasing info accurately. */
25130 srcreg,
25131 promoted_val,
25132 vec_promoted_val,
25133 desired_align,
25134 align_bytes,
25135 issetmem);
25142 }
25144 && !min_size
25149 {
25150 /* It is possible that we copied enough so the main loop will not
25151 execute. */
25161 else
25163 }
25164 }
25166 {
25173 }
25177 /* Step 3: Main loop. */
25180 {
25203 }
25204 /* Adjust properly the offset of src and dest memory for aliasing. */
25206 {
25212 }
25213 else
25214 {
25218 }
25220 /* Step 4: Epilogue to copy the remaining bytes. */
25221 epilogue:
25223 {
25224 /* When the main loop is done, COUNT_EXP might hold original count,
25225 while we want to copy only COUNT_EXP & SIZE_NEEDED bytes.
25226 Epilogue code will actually copy COUNT_EXP & EPILOGUE_SIZE_NEEDED
25227 bytes. Compensate if needed. */
25230 {
25231 tmp =
25234 OPTAB_DIRECT);
25237 }
25240 }
25243 {
25246 epilogue_size_needed);
25247 else
25248 {
25252 epilogue_size_needed);
25253 else
25255 epilogue_size_needed);
25256 }
25257 }
25261 }
25264 /* Expand the appropriate insns for doing strlen if not just doing
25265 repnz; scasb
25267 out = result, initialized with the start address
25268 align_rtx = alignment of the address.
25269 scratch = scratch register, initialized with the startaddress when
25270 not aligned, otherwise undefined
25272 This is just the body. It needs the initializations mentioned above and
25273 some address computing at the end. These things are done in i386.md. */
25275 static void
25277 {
25279 rtx tmp;
25284 rtx mem;
25287 rtx cmp;
25293 /* Loop to check 1..3 bytes for null to get an aligned pointer. */
25295 /* Is there a known alignment and is it less than 4? */
25297 {
25300 /* Is there a known alignment and is it not 2? */
25302 {
25306 /* Leave just the 3 lower bits. */
25316 }
25317 else
25318 {
25319 /* Since the alignment is 2, we have to check 2 or 0 bytes;
25320 check if is aligned to 4 - byte. */
25327 }
25331 /* Now compare the bytes. */
25333 /* Compare the first n unaligned byte on a byte per byte basis. */
25337 /* Increment the address. */
25340 /* Not needed with an alignment of 2 */
25342 {
25346 end_0_label);
25351 }
25354 end_0_label);
25357 }
25359 /* Generate loop to check 4 bytes at a time. It is not a good idea to
25360 align this loop. It gives only huge programs, but does not help to
25361 speed up. */
25368 /* This formula yields a nonzero result iff one of the bytes is zero.
25369 This saves three branches inside loop and many cycles. */
25377 align_4_label);
25380 {
25386 /* If zero is not in the first two bytes, move two bytes forward. */
25392 reg,
25393 tmpreg)));
25394 /* Emit lea manually to avoid clobbering of flags. */
25401 reg2,
25402 out)));
25403 }
25404 else
25405 {
25407 /* Is zero in the first two bytes? */
25414 pc_rtx);
25418 /* Not in the first two. Move two bytes forward. */
25424 }
25426 /* Avoid branch in fixing the byte. */
25434 }
25436 /* Expand strlen. */
25438 bool
25440 {
25443 /* The generic case of strlen expander is long. Avoid it's
25444 expanding unless TARGET_INLINE_ALL_STRINGOPS. */
25447 && !TARGET_INLINE_ALL_STRINGOPS
25457 {
25458 /* Well it seems that some optimizer does not combine a call like
25459 foo(strlen(bar), strlen(bar));
25460 when the move and the subtraction is done here. It does calculate
25461 the length just once when these instructions are done inside of
25462 output_strlen_unroll(). But I think since &bar[strlen(bar)] is
25463 often used and I use one fewer register for the lifetime of
25464 output_strlen_unroll() this is better. */
25470 /* strlensi_unroll_1 returns the address of the zero at the end of
25471 the string, like memchr(), so compute the length by subtracting
25472 the start address. */
25474 }
25475 else
25476 {
25477 rtx unspec;
25479 /* Can't use this if the user has appropriated eax, ecx, or edi. */
25492 /* If .md starts supporting :P, this can be done in .md. */
25498 }
25500 }
25502 /* For given symbol (function) construct code to compute address of it's PLT
25503 entry in large x86-64 PIC model. */
25504 static rtx
25506 {
25519 }
25521 rtx
25523 rtx callarg2,
25525 {
25535 {
25536 #if TARGET_MACHO
25539 #endif
25540 }
25541 else
25542 {
25543 /* Static functions and indirect calls don't need the pic register. Also,
25544 check if PLT was explicitly avoided via no-plt or "noplt" attribute, making
25545 it an indirect call. */
25547 && (!TARGET_64BIT
25552 && flag_plt
25556 {
25560 pic_offset_table_rtx);
25561 }
25562 }
25564 /* Skip setting up RAX register for -mskip-rax-setup when there are no
25565 parameters passed in vector registers. */
25570 {
25574 }
25577 && !TARGET_PECOFF
25585 {
25588 }
25593 {
25594 /* We should add bounds as destination register in case
25595 pointer with bounds may be returned. */
25597 {
25601 {
25606 }
25607 else
25608 {
25612 }
25613 }
25616 }
25620 {
25624 }
25628 {
25629 int const cregs_size
25634 {
25639 }
25640 }
25649 }
25651 /* Return true if the function being called was marked with attribute "noplt"
25652 or using -fno-plt and we are compiling for non-PIC and x86_64. We need to
25653 handle the non-PIC case in the backend because there is no easy interface
25654 for the front-end to force non-PLT calls to use the GOT. This is currently
25655 used only with 64-bit ELF targets to call the function marked "noplt"
25656 indirectly. */
25658 static bool
25660 {
25674 }
25676 /* Output the assembly for a call instruction. */
25680 {
25686 {
25691 /* SEH epilogue detection requires the indirect branch case
25692 to include REX.W. */
25695 else
25700 }
25702 /* SEH unwinding can require an extra nop to be emitted in several
25703 circumstances. Determine if we have one of those. */
25705 {
25709 {
25710 /* If we get to another real insn, we don't need the nop. */
25714 /* If we get to the epilogue note, prevent a catch region from
25715 being adjacent to the standard epilogue sequence. If non-
25716 call-exceptions, we'll have done this during epilogue emission. */
25718 && !flag_non_call_exceptions
25720 {
25723 }
25724 }
25726 /* If we didn't find a real insn following the call, prevent the
25727 unwinder from looking into the next function. */
25730 }
25736 else
25745 }
25746 \f
25747 /* Clear stack slot assignments remembered from previous functions.
25748 This is called from INIT_EXPANDERS once before RTL is emitted for each
25749 function. */
25753 {
25761 }
25763 /* Return a MEM corresponding to a stack slot with mode MODE.
25764 Allocate a new slot if necessary.
25766 The RTL for a function can have several slots available: N is
25767 which slot to use. */
25769 rtx
25771 {
25788 }
25790 static void
25792 {
25798 }
25799 \f
25800 /* Check whether x86 address PARTS is a pc-relative address. */
25802 static bool
25804 {
25812 {
25814 {
25831 }
25832 }
25834 }
25836 /* Calculate the length of the memory address in the instruction encoding.
25837 Includes addr32 prefix, does not include the one-byte modrm, opcode,
25838 or other prefixes. We never generate addr32 prefix for LEA insn. */
25840 int
25842 {
25859 /* If this is not LEA instruction, add the length of addr32 prefix. */
25864 len++;
25878 /* Rule of thumb:
25879 - esp as the base always wants an index,
25880 - ebp as the base always wants a displacement,
25881 - r12 as the base always wants an index,
25882 - r13 as the base always wants a displacement. */
25884 /* Register Indirect. */
25886 {
25887 /* esp (for its index) and ebp (for its displacement) need
25888 the two-byte modrm form. Similarly for r12 and r13 in 64-bit
25889 code. */
25896 len++;
25897 }
25899 /* Direct Addressing. In 64-bit mode mod 00 r/m 5
25900 is not disp32, but disp32(%rip), so for disp32
25901 SIB byte is needed, unless print_operand_address
25902 optimizes it into disp32(%rip) or (%rip) is implied
25903 by UNSPEC. */
25905 {
25908 len++;
25909 }
25910 else
25911 {
25912 /* Find the length of the displacement constant. */
25914 {
25917 else
25919 }
25920 /* ebp always wants a displacement. Similarly r13. */
25922 len++;
25924 /* An index requires the two-byte modrm form.... */
25926 /* ...like esp (or r12), which always wants an index. */
25930 len++;
25931 }
25934 }
25936 /* Compute default value for "length_immediate" attribute. When SHORTFORM
25937 is set, expect that insn have 8bit immediate alternative. */
25938 int
25940 {
25946 {
25951 {
25954 {
25966 }
25968 {
25971 }
25972 }
25974 {
25984 /* Immediates for DImode instructions are encoded
25985 as 32bit sign extended values. */
25991 }
25992 }
25994 }
25996 /* Compute default value for "length_address" attribute. */
25997 int
25999 {
26003 {
26014 }
26019 {
26022 {
26027 constraints++;
26030 ;
26031 /* Skip ignored operands. */
26034 }
26036 }
26038 }
26040 /* Compute default value for "length_vex" attribute. It includes
26041 2 or 3 byte VEX prefix and 1 opcode byte. */
26043 int
26046 {
26049 /* Only 0f opcode can use 2 byte VEX prefix and VEX W bit uses 3
26050 byte VEX prefix. */
26054 /* We can always use 2 byte VEX prefix in 32bit. */
26062 {
26063 /* REX.W bit uses 3 byte VEX prefix. */
26067 }
26068 else
26069 {
26070 /* REX.X or REX.B bits use 3 byte VEX prefix. */
26074 }
26077 }
26078 \f
26079 /* Return the maximum number of instructions a cpu can issue. */
26081 static int
26083 {
26085 {
26117 }
26118 }
26120 /* A subroutine of ix86_adjust_cost -- return TRUE iff INSN reads flags set
26121 by DEP_INSN and nothing set by DEP_INSN. */
26123 static bool
26125 {
26128 /* Simplify the test for uninteresting insns. */
26136 {
26139 }
26144 {
26147 }
26148 else
26154 /* This test is true if the dependent insn reads the flags but
26155 not any other potentially set register. */
26163 }
26165 /* Return true iff USE_INSN has a memory address with operands set by
26166 SET_INSN. */
26168 bool
26170 {
26175 {
26178 }
26180 }
26182 /* Helper function for exact_store_load_dependency.
26183 Return true if addr is found in insn. */
26184 static bool
26186 {
26193 {
26199 CASE_CONST_ANY:
26208 }
26212 {
26214 {
26224 }
26225 }
26227 }
26229 /* Return true if there exists exact dependency for store & load, i.e.
26230 the same memory address is used in them. */
26231 static bool
26233 {
26247 }
26249 static int
26251 {
26257 /* Anti and output dependencies have zero cost on all CPUs. */
26263 /* If we can't recognize the insns, we can't really do anything. */
26271 {
26273 /* Address Generation Interlock adds a cycle of latency. */
26275 {
26286 }
26290 /* ??? Compares pair with jump/setcc. */
26294 /* Floating point stores require value to be ready one cycle earlier. */
26302 /* INT->FP conversion is expensive. */
26306 /* There is one cycle extra latency between an FP op and a store. */
26316 /* Show ability of reorder buffer to hide latency of load by executing
26317 in parallel with previous instruction in case
26318 previous instruction is not needed to compute the address. */
26321 {
26322 /* Claim moves to take one cycle, as core can issue one load
26323 at time and the next load can start cycle later. */
26328 cost--;
26329 }
26333 /* The esp dependency is resolved before
26334 the instruction is really finished. */
26339 /* INT->FP conversion is expensive. */
26345 /* Show ability of reorder buffer to hide latency of load by executing
26346 in parallel with previous instruction in case
26347 previous instruction is not needed to compute the address. */
26350 {
26351 /* Claim moves to take one cycle, as core can issue one load
26352 at time and the next load can start cycle later. */
26358 else
26360 }
26371 /* Stack engine allows to execute push&pop instructions in parall. */
26375 /* FALLTHRU */
26381 /* Show ability of reorder buffer to hide latency of load by executing
26382 in parallel with previous instruction in case
26383 previous instruction is not needed to compute the address. */
26386 {
26390 /* Because of the difference between the length of integer and
26391 floating unit pipeline preparation stages, the memory operands
26392 for floating point are cheaper.
26394 ??? For Athlon it the difference is most probably 2. */
26397 else
26402 else
26404 }
26411 /* Stack engine allows to execute push&pop instructions in parall. */
26418 /* Show ability of reorder buffer to hide latency of load by executing
26419 in parallel with previous instruction in case
26420 previous instruction is not needed to compute the address. */
26423 {
26426 else
26428 }
26437 /* Increase cost of integer loads. */
26440 {
26443 {
26446 else
26447 {
26448 /* Increase cost of ld/st for short int types only
26449 because of store forwarding issue. */
26453 {
26454 /* Increase cost of store/load insn if exact
26455 dependence exists and it is load insn. */
26460 }
26461 }
26462 }
26463 }
26467 }
26470 }
26472 /* How many alternative schedules to try. This should be as wide as the
26473 scheduling freedom in the DFA, but no wider. Making this value too
26474 large results extra work for the scheduler. */
26476 static int
26478 {
26480 {
26492 /* We use lookahead value 4 for BD both before and after reload
26493 schedules. Plan is to have value 8 included for O3. */
26504 /* Generally, we want haifa-sched:max_issue() to look ahead as far
26505 as many instructions can be executed on a cycle, i.e.,
26506 issue_rate. I wonder why tuning for many CPUs does not do this. */
26509 /* Don't use lookahead for pre-reload schedule to save compile time. */
26514 }
26515 }
26517 /* Return true if target platform supports macro-fusion. */
26519 static bool
26521 {
26523 }
26525 /* Check whether current microarchitecture support macro fusion
26526 for insn pair "CONDGEN + CONDJMP". Refer to
26527 "Intel Architectures Optimization Reference Manual". */
26529 static bool
26531 {
26552 {
26557 {
26561 else
26563 }
26564 }
26571 /* Macro-fusion for cmp/test MEM-IMM + conditional jmp is not
26572 supported. */
26579 /* No fusion for RIP-relative address. */
26586 ix86_address parts;
26592 }
26597 /* Check whether conditional jump use Sign or Overflow Flags. */
26605 /* Return true for TYPE_TEST and TYPE_ICMP. */
26610 /* The following is the case that macro-fusion for alu + jmp. */
26614 /* No fusion for alu op with memory destination operand. */
26619 /* Macro-fusion for inc/dec + unsigned conditional jump is not
26620 supported. */
26629 }
26631 /* Try to reorder ready list to take advantage of Atom pipelined IMUL
26632 execution. It is applied if
26633 (1) IMUL instruction is on the top of list;
26634 (2) There exists the only producer of independent IMUL instruction in
26635 ready list.
26636 Return index of IMUL producer if it was found and -1 otherwise. */
26637 static int
26639 {
26642 sd_iterator_def sd_it;
26643 dep_t dep;
26650 /* Check that IMUL instruction is on the top of ready list. */
26659 /* Search for producer of independent IMUL instruction. */
26661 {
26665 /* Skip IMUL instruction. */
26675 {
26676 rtx con;
26687 {
26688 sd_iterator_def sd_it1;
26689 dep_t dep1;
26690 /* Check if there is no other dependee for IMUL. */
26693 {
26694 rtx pro;
26700 }
26703 }
26704 }
26707 }
26709 }
26711 /* Try to find the best candidate on the top of ready list if two insns
26712 have the same priority - candidate is best if its dependees were
26713 scheduled earlier. Applied for Silvermont only.
26714 Return true if top 2 insns must be interchanged. */
26715 static bool
26717 {
26720 rtx set;
26721 sd_iterator_def sd_it;
26722 dep_t dep;
26725 #define INSN_TICK(INSN) (HID (INSN)->tick)
26746 {
26749 /* Determine winner more precise. */
26751 {
26752 rtx pro;
26758 }
26760 {
26761 rtx pro;
26767 }
26770 {
26771 /* Determine winner - load must win. */
26777 }
26779 }
26781 #undef INSN_TICK
26782 }
26784 /* Perform possible reodering of ready list for Atom/Silvermont only.
26785 Return issue rate. */
26786 static int
26789 {
26796 /* Set up issue rate. */
26799 /* Do reodering for BONNELL/SILVERMONT only. */
26803 /* Nothing to do if ready list contains only 1 instruction. */
26807 /* Do reodering for post-reload scheduler only. */
26812 {
26817 /* Put IMUL producer (ready[index]) at the top of ready list. */
26823 }
26825 /* Skip selective scheduling since HID is not populated in it. */
26829 {
26833 /* Swap 2 top elements of ready list. */
26837 }
26839 }
26841 static bool
26844 /* Returns true if lhs of insn is HW function argument register and set up
26845 is_spilled to true if it is likely spilled HW register. */
26846 static bool
26848 {
26849 rtx dst;
26853 /* Call instructions are not movable, ignore it. */
26864 {
26865 /* Is it likely spilled HW register? */
26870 }
26872 }
26874 /* Add output dependencies for chain of function adjacent arguments if only
26875 there is a move to likely spilled HW register. Return first argument
26876 if at least one dependence was added or NULL otherwise. */
26879 {
26887 /* Find nearest to call argument passing instruction. */
26889 {
26898 }
26902 {
26909 {
26912 }
26914 {
26915 /* Add output depdendence between two function arguments if chain
26916 of output arguments contains likely spilled HW registers. */
26920 }
26921 else
26923 }
26927 }
26929 /* Add output or anti dependency from insn to first_arg to restrict its code
26930 motion. */
26931 static void
26933 {
26934 rtx set;
26935 rtx tmp;
26937 /* Add anti dependencies for bounds stores. */
26942 {
26945 }
26952 {
26953 /* Add output dependency to the first function argument. */
26956 }
26957 /* Add anti dependency. */
26959 }
26961 /* Avoid cross block motion of function argument through adding dependency
26962 from the first non-jump instruction in bb. */
26963 static void
26965 {
26969 {
26971 {
26974 {
26977 }
26978 }
26982 }
26983 }
26985 /* Hook for pre-reload schedule - avoid motion of function arguments
26986 passed in likely spilled HW registers. */
26987 static void
26989 {
26998 {
27001 {
27002 /* Add dependee for first argument to predecessors if only
27003 region contains more than one block. */
27007 /* Skip trivial regions and region head blocks that can have
27008 predecessors outside of region. */
27010 {
27011 edge e;
27012 edge_iterator ei;
27014 /* Regions are SCCs with the exception of selective
27015 scheduling with pipelining of outer blocks enabled.
27016 So also check that immediate predecessors of a non-head
27017 block are in the same region. */
27019 {
27020 /* Avoid creating of loop-carried dependencies through
27021 using topological ordering in the region. */
27025 }
27026 }
27030 }
27031 }
27034 }
27036 /* Hook for pre-reload schedule - set priority of moves from likely spilled
27037 HW registers to maximum, to schedule them at soon as possible. These are
27038 moves from function argument registers at the top of the function entry
27039 and moves from function return value registers after call. */
27040 static int
27042 {
27043 rtx set;
27053 {
27060 }
27063 }
27065 /* Model decoder of Core 2/i7.
27066 Below hooks for multipass scheduling (see haifa-sched.c:max_issue)
27067 track the instruction fetch block boundaries and make sure that long
27068 (9+ bytes) instructions are assigned to D0. */
27070 /* Maximum length of an insn that can be handled by
27071 a secondary decoder unit. '8' for Core 2/i7. */
27074 /* Ifetch block size, i.e., number of bytes decoder reads per cycle.
27075 '16' for Core 2/i7. */
27078 /* Maximum number of instructions decoder can handle per cycle.
27079 '6' for Core 2/i7. */
27083 ix86_first_cycle_multipass_data_t;
27085 const_ix86_first_cycle_multipass_data_t;
27087 /* A variable to store target state across calls to max_issue within
27088 one cycle. */
27092 /* Initialize DATA. */
27093 static void
27095 {
27096 ix86_first_cycle_multipass_data_t data
27103 }
27105 /* Advancing the cycle; reset ifetch block counts. */
27106 static void
27108 {
27115 }
27119 /* Filter out insns from ready_try that the core will not be able to issue
27120 on current cycle due to decoder. */
27121 static void
27122 core2i7_first_cycle_multipass_filter_ready_try
27125 {
27127 {
27138 (!first_cycle_insn_p
27140 /* ... or it would not fit into the ifetch block ... */
27142 /* ... or the decoder is full already ... */
27144 /* ... mask the insn out. */
27145 {
27150 }
27151 }
27152 }
27154 /* Prepare for a new round of multipass lookahead scheduling. */
27155 static void
27159 {
27160 ix86_first_cycle_multipass_data_t data
27162 const_ix86_first_cycle_multipass_data_t prev_data
27165 /* Restore the state from the end of the previous round. */
27169 /* Filter instructions that cannot be issued on current cycle due to
27170 decoder restrictions. */
27172 first_cycle_insn_p);
27173 }
27175 /* INSN is being issued in current solution. Account for its impact on
27176 the decoder model. */
27177 static void
27181 {
27182 ix86_first_cycle_multipass_data_t data
27184 const_ix86_first_cycle_multipass_data_t prev_data
27194 /* Allocate or resize the bitmap for storing INSN's effect on ready_try. */
27196 {
27199 }
27201 {
27205 }
27208 /* Filter out insns from ready_try that the core will not be able to issue
27209 on current cycle due to decoder. */
27212 }
27214 /* Revert the effect on ready_try. */
27215 static void
27219 {
27220 const_ix86_first_cycle_multipass_data_t data
27223 sbitmap_iterator sbi;
27227 {
27229 }
27230 }
27232 /* Save the result of multipass lookahead scheduling for the next round. */
27233 static void
27235 {
27236 const_ix86_first_cycle_multipass_data_t data
27238 ix86_first_cycle_multipass_data_t next_data
27242 {
27245 }
27246 }
27248 /* Deallocate target data. */
27249 static void
27251 {
27252 ix86_first_cycle_multipass_data_t data
27256 {
27260 }
27261 }
27263 /* Prepare for scheduling pass. */
27264 static void
27266 {
27267 /* Install scheduling hooks for current CPU. Some of these hooks are used
27268 in time-critical parts of the scheduler, so we only set them up when
27269 they are actually used. */
27271 {
27276 /* Do not perform multipass scheduling for pre-reload schedule
27277 to save compile time. */
27279 {
27295 /* Set decoder parameters. */
27300 }
27301 /* ... Fall through ... */
27311 }
27312 }
27314 \f
27315 /* Compute the alignment given to a constant that is being placed in memory.
27316 EXP is the constant and ALIGN is the alignment that the object would
27317 ordinarily have.
27318 The value of this function is used instead of that alignment to align
27319 the object. */
27321 int
27323 {
27326 {
27331 }
27337 }
27339 /* Compute the alignment for a static variable.
27340 TYPE is the data type, and ALIGN is the alignment that
27341 the object would ordinarily have. The value of this function is used
27342 instead of that alignment to align the object. */
27344 int
27346 {
27347 /* GCC 4.8 and earlier used to incorrectly assume this alignment even
27348 for symbols from other compilation units or symbols that don't need
27349 to bind locally. In order to preserve some ABI compatibility with
27350 those compilers, ensure we don't decrease alignment from what we
27351 used to assume. */
27355 /* A data structure, equal or greater than the size of a cache line
27356 (64 bytes in the Pentium 4 and other recent Intel processors, including
27357 processors based on Intel Core microarchitecture) should be aligned
27358 so that its base address is a multiple of a cache line size. */
27360 int max_align
27367 {
27371 }
27377 {
27384 }
27386 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27387 to 16byte boundary. */
27389 {
27396 }
27402 {
27407 }
27409 {
27416 }
27421 {
27426 }
27429 {
27434 }
27437 }
27439 /* Compute the alignment for a local variable or a stack slot. EXP is
27440 the data type or decl itself, MODE is the widest mode available and
27441 ALIGN is the alignment that the object would ordinarily have. The
27442 value of this macro is used instead of that alignment to align the
27443 object. */
27445 unsigned int
27448 {
27452 {
27455 }
27456 else
27457 {
27460 }
27462 /* Don't do dynamic stack realignment for long long objects with
27463 -mpreferred-stack-boundary=2. */
27472 /* If TYPE is NULL, we are allocating a stack slot for caller-save
27473 register in MODE. We will return the largest alignment of XF
27474 and DF. */
27476 {
27480 }
27482 /* x86-64 ABI requires arrays greater than 16 bytes to be aligned
27483 to 16byte boundary. Exact wording is:
27485 An array uses the same alignment as its elements, except that a local or
27486 global array variable of length at least 16 bytes or
27487 a C99 variable-length array variable always has alignment of at least 16 bytes.
27489 This was added to allow use of aligned SSE instructions at arrays. This
27490 rule is meant for static storage (where compiler can not do the analysis
27491 by itself). We follow it for automatic variables only when convenient.
27492 We fully control everything in the function compiled and functions from
27493 other unit can not rely on the alignment.
27495 Exclude va_list type. It is the common case of local array where
27496 we can not benefit from the alignment.
27498 TODO: Probably one should optimize for size only when var is not escaping. */
27501 {
27511 }
27513 {
27518 }
27520 {
27526 }
27531 {
27536 }
27539 {
27545 }
27547 }
27549 /* Compute the minimum required alignment for dynamic stack realignment
27550 purposes for a local variable, parameter or a stack slot. EXP is
27551 the data type or decl itself, MODE is its mode and ALIGN is the
27552 alignment that the object would ordinarily have. */
27554 unsigned int
27557 {
27561 {
27564 }
27565 else
27566 {
27569 }
27574 /* Don't do dynamic stack realignment for long long objects with
27575 -mpreferred-stack-boundary=2. */
27582 }
27583 \f
27584 /* Find a location for the static chain incoming to a nested function.
27585 This is a register, unless all free registers are used by arguments. */
27587 static rtx
27589 {
27592 /* While this function won't be called by the middle-end when a static
27593 chain isn't needed, it's also used throughout the backend so it's
27594 easiest to keep this check centralized. */
27599 {
27600 /* We always use R10 in 64-bit mode. */
27602 }
27603 else
27604 {
27608 /* By default in 32-bit mode we use ECX to pass the static chain. */
27612 {
27615 }
27616 else
27617 {
27620 }
27624 {
27625 /* Fastcall functions use ecx/edx for arguments, which leaves
27626 us with EAX for the static chain.
27627 Thiscall functions use ecx for arguments, which also
27628 leaves us with EAX for the static chain. */
27630 }
27632 {
27633 /* Thiscall functions use ecx for arguments, which leaves
27634 us with EAX and EDX for the static chain.
27635 We are using for abi-compatibility EAX. */
27637 }
27639 {
27640 /* For regparm 3, we have no free call-clobbered registers in
27641 which to store the static chain. In order to implement this,
27642 we have the trampoline push the static chain to the stack.
27643 However, we can't push a value below the return address when
27644 we call the nested function directly, so we have to use an
27645 alternate entry point. For this we use ESI, and have the
27646 alternate entry point push ESI, so that things appear the
27647 same once we're executing the nested function. */
27649 {
27655 }
27657 }
27658 }
27661 }
27663 /* Emit RTL insns to initialize the variable parts of a trampoline.
27664 FNDECL is the decl of the target address; M_TRAMP is a MEM for
27665 the trampoline, and CHAIN_VALUE is an RTX for the static chain
27666 to be passed to the target function. */
27668 static void
27670 {
27678 {
27681 /* Load the function address to r11. Try to load address using
27682 the shorter movl instead of movabs. We may want to support
27683 movq for kernel mode, but kernel does not use trampolines at
27684 the moment. FNADDR is a 32bit address and may not be in
27685 DImode when ptr_mode == SImode. Always use movl in this
27686 case. */
27689 {
27698 }
27699 else
27700 {
27707 }
27709 /* Load static chain using movabs to r10. Use the shorter movl
27710 instead of movabs when ptr_mode == SImode. */
27712 {
27715 }
27716 else
27717 {
27720 }
27729 /* Jump to r11; the last (unused) byte is a nop, only there to
27730 pad the write out to a single 32-bit store. */
27734 }
27735 else
27736 {
27739 /* Depending on the static chain location, either load a register
27740 with a constant, or push the constant to the stack. All of the
27741 instructions are the same size. */
27744 {
27746 {
27753 }
27754 }
27755 else
27770 /* Compute offset from the end of the jmp to the target function.
27771 In the case in which the trampoline stores the static chain on
27772 the stack, we need to skip the first insn which pushes the
27773 (call-saved) register static chain; this push is 1 byte. */
27780 }
27784 #ifdef HAVE_ENABLE_EXECUTE_STACK
27785 #ifdef CHECK_EXECUTE_STACK_ENABLED
27787 #endif
27790 #endif
27791 }
27792 \f
27793 /* The following file contains several enumerations and data structures
27794 built from the definitions in i386-builtin-types.def. */
27798 /* Table for the ix86 builtin non-function types. */
27801 /* Retrieve an element from the above table, building some of
27802 the types lazily. */
27804 static tree
27806 {
27818 {
27819 machine_mode mode;
27826 }
27827 else
27828 {
27834 else
27842 }
27846 }
27848 /* Table for the ix86 builtin function types. */
27851 /* Retrieve an element from the above table, building some of
27852 the types lazily. */
27854 static tree
27856 {
27857 tree type;
27866 {
27874 {
27877 }
27880 }
27881 else
27882 {
27888 }
27892 }
27895 /* Codes for all the SSE/MMX builtins. */
27896 enum ix86_builtins
27897 {
27898 IX86_BUILTIN_ADDPS,
27899 IX86_BUILTIN_ADDSS,
27900 IX86_BUILTIN_DIVPS,
27901 IX86_BUILTIN_DIVSS,
27902 IX86_BUILTIN_MULPS,
27903 IX86_BUILTIN_MULSS,
27904 IX86_BUILTIN_SUBPS,
27905 IX86_BUILTIN_SUBSS,
27907 IX86_BUILTIN_CMPEQPS,
27908 IX86_BUILTIN_CMPLTPS,
27909 IX86_BUILTIN_CMPLEPS,
27910 IX86_BUILTIN_CMPGTPS,
27911 IX86_BUILTIN_CMPGEPS,
27912 IX86_BUILTIN_CMPNEQPS,
27913 IX86_BUILTIN_CMPNLTPS,
27914 IX86_BUILTIN_CMPNLEPS,
27915 IX86_BUILTIN_CMPNGTPS,
27916 IX86_BUILTIN_CMPNGEPS,
27917 IX86_BUILTIN_CMPORDPS,
27918 IX86_BUILTIN_CMPUNORDPS,
27919 IX86_BUILTIN_CMPEQSS,
27920 IX86_BUILTIN_CMPLTSS,
27921 IX86_BUILTIN_CMPLESS,
27922 IX86_BUILTIN_CMPNEQSS,
27923 IX86_BUILTIN_CMPNLTSS,
27924 IX86_BUILTIN_CMPNLESS,
27925 IX86_BUILTIN_CMPORDSS,
27926 IX86_BUILTIN_CMPUNORDSS,
27928 IX86_BUILTIN_COMIEQSS,
27929 IX86_BUILTIN_COMILTSS,
27930 IX86_BUILTIN_COMILESS,
27931 IX86_BUILTIN_COMIGTSS,
27932 IX86_BUILTIN_COMIGESS,
27933 IX86_BUILTIN_COMINEQSS,
27934 IX86_BUILTIN_UCOMIEQSS,
27935 IX86_BUILTIN_UCOMILTSS,
27936 IX86_BUILTIN_UCOMILESS,
27937 IX86_BUILTIN_UCOMIGTSS,
27938 IX86_BUILTIN_UCOMIGESS,
27939 IX86_BUILTIN_UCOMINEQSS,
27941 IX86_BUILTIN_CVTPI2PS,
27942 IX86_BUILTIN_CVTPS2PI,
27943 IX86_BUILTIN_CVTSI2SS,
27944 IX86_BUILTIN_CVTSI642SS,
27945 IX86_BUILTIN_CVTSS2SI,
27946 IX86_BUILTIN_CVTSS2SI64,
27947 IX86_BUILTIN_CVTTPS2PI,
27948 IX86_BUILTIN_CVTTSS2SI,
27949 IX86_BUILTIN_CVTTSS2SI64,
27951 IX86_BUILTIN_MAXPS,
27952 IX86_BUILTIN_MAXSS,
27953 IX86_BUILTIN_MINPS,
27954 IX86_BUILTIN_MINSS,
27956 IX86_BUILTIN_LOADUPS,
27957 IX86_BUILTIN_STOREUPS,
27958 IX86_BUILTIN_MOVSS,
27960 IX86_BUILTIN_MOVHLPS,
27961 IX86_BUILTIN_MOVLHPS,
27962 IX86_BUILTIN_LOADHPS,
27963 IX86_BUILTIN_LOADLPS,
27964 IX86_BUILTIN_STOREHPS,
27965 IX86_BUILTIN_STORELPS,
27967 IX86_BUILTIN_MASKMOVQ,
27968 IX86_BUILTIN_MOVMSKPS,
27969 IX86_BUILTIN_PMOVMSKB,
27971 IX86_BUILTIN_MOVNTPS,
27972 IX86_BUILTIN_MOVNTQ,
27974 IX86_BUILTIN_LOADDQU,
27975 IX86_BUILTIN_STOREDQU,
27977 IX86_BUILTIN_PACKSSWB,
27978 IX86_BUILTIN_PACKSSDW,
27979 IX86_BUILTIN_PACKUSWB,
27981 IX86_BUILTIN_PADDB,
27982 IX86_BUILTIN_PADDW,
27983 IX86_BUILTIN_PADDD,
27984 IX86_BUILTIN_PADDQ,
27985 IX86_BUILTIN_PADDSB,
27986 IX86_BUILTIN_PADDSW,
27987 IX86_BUILTIN_PADDUSB,
27988 IX86_BUILTIN_PADDUSW,
27989 IX86_BUILTIN_PSUBB,
27990 IX86_BUILTIN_PSUBW,
27991 IX86_BUILTIN_PSUBD,
27992 IX86_BUILTIN_PSUBQ,
27993 IX86_BUILTIN_PSUBSB,
27994 IX86_BUILTIN_PSUBSW,
27995 IX86_BUILTIN_PSUBUSB,
27996 IX86_BUILTIN_PSUBUSW,
27998 IX86_BUILTIN_PAND,
27999 IX86_BUILTIN_PANDN,
28000 IX86_BUILTIN_POR,
28001 IX86_BUILTIN_PXOR,
28003 IX86_BUILTIN_PAVGB,
28004 IX86_BUILTIN_PAVGW,
28006 IX86_BUILTIN_PCMPEQB,
28007 IX86_BUILTIN_PCMPEQW,
28008 IX86_BUILTIN_PCMPEQD,
28009 IX86_BUILTIN_PCMPGTB,
28010 IX86_BUILTIN_PCMPGTW,
28011 IX86_BUILTIN_PCMPGTD,
28013 IX86_BUILTIN_PMADDWD,
28015 IX86_BUILTIN_PMAXSW,
28016 IX86_BUILTIN_PMAXUB,
28017 IX86_BUILTIN_PMINSW,
28018 IX86_BUILTIN_PMINUB,
28020 IX86_BUILTIN_PMULHUW,
28021 IX86_BUILTIN_PMULHW,
28022 IX86_BUILTIN_PMULLW,
28024 IX86_BUILTIN_PSADBW,
28025 IX86_BUILTIN_PSHUFW,
28027 IX86_BUILTIN_PSLLW,
28028 IX86_BUILTIN_PSLLD,
28029 IX86_BUILTIN_PSLLQ,
28030 IX86_BUILTIN_PSRAW,
28031 IX86_BUILTIN_PSRAD,
28032 IX86_BUILTIN_PSRLW,
28033 IX86_BUILTIN_PSRLD,
28034 IX86_BUILTIN_PSRLQ,
28035 IX86_BUILTIN_PSLLWI,
28036 IX86_BUILTIN_PSLLDI,
28037 IX86_BUILTIN_PSLLQI,
28038 IX86_BUILTIN_PSRAWI,
28039 IX86_BUILTIN_PSRADI,
28040 IX86_BUILTIN_PSRLWI,
28041 IX86_BUILTIN_PSRLDI,
28042 IX86_BUILTIN_PSRLQI,
28044 IX86_BUILTIN_PUNPCKHBW,
28045 IX86_BUILTIN_PUNPCKHWD,
28046 IX86_BUILTIN_PUNPCKHDQ,
28047 IX86_BUILTIN_PUNPCKLBW,
28048 IX86_BUILTIN_PUNPCKLWD,
28049 IX86_BUILTIN_PUNPCKLDQ,
28051 IX86_BUILTIN_SHUFPS,
28053 IX86_BUILTIN_RCPPS,
28054 IX86_BUILTIN_RCPSS,
28055 IX86_BUILTIN_RSQRTPS,
28056 IX86_BUILTIN_RSQRTPS_NR,
28057 IX86_BUILTIN_RSQRTSS,
28058 IX86_BUILTIN_RSQRTF,
28059 IX86_BUILTIN_SQRTPS,
28060 IX86_BUILTIN_SQRTPS_NR,
28061 IX86_BUILTIN_SQRTSS,
28063 IX86_BUILTIN_UNPCKHPS,
28064 IX86_BUILTIN_UNPCKLPS,
28066 IX86_BUILTIN_ANDPS,
28067 IX86_BUILTIN_ANDNPS,
28068 IX86_BUILTIN_ORPS,
28069 IX86_BUILTIN_XORPS,
28071 IX86_BUILTIN_EMMS,
28072 IX86_BUILTIN_LDMXCSR,
28073 IX86_BUILTIN_STMXCSR,
28074 IX86_BUILTIN_SFENCE,
28076 IX86_BUILTIN_FXSAVE,
28077 IX86_BUILTIN_FXRSTOR,
28078 IX86_BUILTIN_FXSAVE64,
28079 IX86_BUILTIN_FXRSTOR64,
28081 IX86_BUILTIN_XSAVE,
28082 IX86_BUILTIN_XRSTOR,
28083 IX86_BUILTIN_XSAVE64,
28084 IX86_BUILTIN_XRSTOR64,
28086 IX86_BUILTIN_XSAVEOPT,
28087 IX86_BUILTIN_XSAVEOPT64,
28089 IX86_BUILTIN_XSAVEC,
28090 IX86_BUILTIN_XSAVEC64,
28092 IX86_BUILTIN_XSAVES,
28093 IX86_BUILTIN_XRSTORS,
28094 IX86_BUILTIN_XSAVES64,
28095 IX86_BUILTIN_XRSTORS64,
28097 /* 3DNow! Original */
28098 IX86_BUILTIN_FEMMS,
28099 IX86_BUILTIN_PAVGUSB,
28100 IX86_BUILTIN_PF2ID,
28101 IX86_BUILTIN_PFACC,
28102 IX86_BUILTIN_PFADD,
28103 IX86_BUILTIN_PFCMPEQ,
28104 IX86_BUILTIN_PFCMPGE,
28105 IX86_BUILTIN_PFCMPGT,
28106 IX86_BUILTIN_PFMAX,
28107 IX86_BUILTIN_PFMIN,
28108 IX86_BUILTIN_PFMUL,
28109 IX86_BUILTIN_PFRCP,
28110 IX86_BUILTIN_PFRCPIT1,
28111 IX86_BUILTIN_PFRCPIT2,
28112 IX86_BUILTIN_PFRSQIT1,
28113 IX86_BUILTIN_PFRSQRT,
28114 IX86_BUILTIN_PFSUB,
28115 IX86_BUILTIN_PFSUBR,
28116 IX86_BUILTIN_PI2FD,
28117 IX86_BUILTIN_PMULHRW,
28119 /* 3DNow! Athlon Extensions */
28120 IX86_BUILTIN_PF2IW,
28121 IX86_BUILTIN_PFNACC,
28122 IX86_BUILTIN_PFPNACC,
28123 IX86_BUILTIN_PI2FW,
28124 IX86_BUILTIN_PSWAPDSI,
28125 IX86_BUILTIN_PSWAPDSF,
28127 /* SSE2 */
28128 IX86_BUILTIN_ADDPD,
28129 IX86_BUILTIN_ADDSD,
28130 IX86_BUILTIN_DIVPD,
28131 IX86_BUILTIN_DIVSD,
28132 IX86_BUILTIN_MULPD,
28133 IX86_BUILTIN_MULSD,
28134 IX86_BUILTIN_SUBPD,
28135 IX86_BUILTIN_SUBSD,
28137 IX86_BUILTIN_CMPEQPD,
28138 IX86_BUILTIN_CMPLTPD,
28139 IX86_BUILTIN_CMPLEPD,
28140 IX86_BUILTIN_CMPGTPD,
28141 IX86_BUILTIN_CMPGEPD,
28142 IX86_BUILTIN_CMPNEQPD,
28143 IX86_BUILTIN_CMPNLTPD,
28144 IX86_BUILTIN_CMPNLEPD,
28145 IX86_BUILTIN_CMPNGTPD,
28146 IX86_BUILTIN_CMPNGEPD,
28147 IX86_BUILTIN_CMPORDPD,
28148 IX86_BUILTIN_CMPUNORDPD,
28149 IX86_BUILTIN_CMPEQSD,
28150 IX86_BUILTIN_CMPLTSD,
28151 IX86_BUILTIN_CMPLESD,
28152 IX86_BUILTIN_CMPNEQSD,
28153 IX86_BUILTIN_CMPNLTSD,
28154 IX86_BUILTIN_CMPNLESD,
28155 IX86_BUILTIN_CMPORDSD,
28156 IX86_BUILTIN_CMPUNORDSD,
28158 IX86_BUILTIN_COMIEQSD,
28159 IX86_BUILTIN_COMILTSD,
28160 IX86_BUILTIN_COMILESD,
28161 IX86_BUILTIN_COMIGTSD,
28162 IX86_BUILTIN_COMIGESD,
28163 IX86_BUILTIN_COMINEQSD,
28164 IX86_BUILTIN_UCOMIEQSD,
28165 IX86_BUILTIN_UCOMILTSD,
28166 IX86_BUILTIN_UCOMILESD,
28167 IX86_BUILTIN_UCOMIGTSD,
28168 IX86_BUILTIN_UCOMIGESD,
28169 IX86_BUILTIN_UCOMINEQSD,
28171 IX86_BUILTIN_MAXPD,
28172 IX86_BUILTIN_MAXSD,
28173 IX86_BUILTIN_MINPD,
28174 IX86_BUILTIN_MINSD,
28176 IX86_BUILTIN_ANDPD,
28177 IX86_BUILTIN_ANDNPD,
28178 IX86_BUILTIN_ORPD,
28179 IX86_BUILTIN_XORPD,
28181 IX86_BUILTIN_SQRTPD,
28182 IX86_BUILTIN_SQRTSD,
28184 IX86_BUILTIN_UNPCKHPD,
28185 IX86_BUILTIN_UNPCKLPD,
28187 IX86_BUILTIN_SHUFPD,
28189 IX86_BUILTIN_LOADUPD,
28190 IX86_BUILTIN_STOREUPD,
28191 IX86_BUILTIN_MOVSD,
28193 IX86_BUILTIN_LOADHPD,
28194 IX86_BUILTIN_LOADLPD,
28196 IX86_BUILTIN_CVTDQ2PD,
28197 IX86_BUILTIN_CVTDQ2PS,
28199 IX86_BUILTIN_CVTPD2DQ,
28200 IX86_BUILTIN_CVTPD2PI,
28201 IX86_BUILTIN_CVTPD2PS,
28202 IX86_BUILTIN_CVTTPD2DQ,
28203 IX86_BUILTIN_CVTTPD2PI,
28205 IX86_BUILTIN_CVTPI2PD,
28206 IX86_BUILTIN_CVTSI2SD,
28207 IX86_BUILTIN_CVTSI642SD,
28209 IX86_BUILTIN_CVTSD2SI,
28210 IX86_BUILTIN_CVTSD2SI64,
28211 IX86_BUILTIN_CVTSD2SS,
28212 IX86_BUILTIN_CVTSS2SD,
28213 IX86_BUILTIN_CVTTSD2SI,
28214 IX86_BUILTIN_CVTTSD2SI64,
28216 IX86_BUILTIN_CVTPS2DQ,
28217 IX86_BUILTIN_CVTPS2PD,
28218 IX86_BUILTIN_CVTTPS2DQ,
28220 IX86_BUILTIN_MOVNTI,
28221 IX86_BUILTIN_MOVNTI64,
28222 IX86_BUILTIN_MOVNTPD,
28223 IX86_BUILTIN_MOVNTDQ,
28225 IX86_BUILTIN_MOVQ128,
28227 /* SSE2 MMX */
28228 IX86_BUILTIN_MASKMOVDQU,
28229 IX86_BUILTIN_MOVMSKPD,
28230 IX86_BUILTIN_PMOVMSKB128,
28232 IX86_BUILTIN_PACKSSWB128,
28233 IX86_BUILTIN_PACKSSDW128,
28234 IX86_BUILTIN_PACKUSWB128,
28236 IX86_BUILTIN_PADDB128,
28237 IX86_BUILTIN_PADDW128,
28238 IX86_BUILTIN_PADDD128,
28239 IX86_BUILTIN_PADDQ128,
28240 IX86_BUILTIN_PADDSB128,
28241 IX86_BUILTIN_PADDSW128,
28242 IX86_BUILTIN_PADDUSB128,
28243 IX86_BUILTIN_PADDUSW128,
28244 IX86_BUILTIN_PSUBB128,
28245 IX86_BUILTIN_PSUBW128,
28246 IX86_BUILTIN_PSUBD128,
28247 IX86_BUILTIN_PSUBQ128,
28248 IX86_BUILTIN_PSUBSB128,
28249 IX86_BUILTIN_PSUBSW128,
28250 IX86_BUILTIN_PSUBUSB128,
28251 IX86_BUILTIN_PSUBUSW128,
28253 IX86_BUILTIN_PAND128,
28254 IX86_BUILTIN_PANDN128,
28255 IX86_BUILTIN_POR128,
28256 IX86_BUILTIN_PXOR128,
28258 IX86_BUILTIN_PAVGB128,
28259 IX86_BUILTIN_PAVGW128,
28261 IX86_BUILTIN_PCMPEQB128,
28262 IX86_BUILTIN_PCMPEQW128,
28263 IX86_BUILTIN_PCMPEQD128,
28264 IX86_BUILTIN_PCMPGTB128,
28265 IX86_BUILTIN_PCMPGTW128,
28266 IX86_BUILTIN_PCMPGTD128,
28268 IX86_BUILTIN_PMADDWD128,
28270 IX86_BUILTIN_PMAXSW128,
28271 IX86_BUILTIN_PMAXUB128,
28272 IX86_BUILTIN_PMINSW128,
28273 IX86_BUILTIN_PMINUB128,
28275 IX86_BUILTIN_PMULUDQ,
28276 IX86_BUILTIN_PMULUDQ128,
28277 IX86_BUILTIN_PMULHUW128,
28278 IX86_BUILTIN_PMULHW128,
28279 IX86_BUILTIN_PMULLW128,
28281 IX86_BUILTIN_PSADBW128,
28282 IX86_BUILTIN_PSHUFHW,
28283 IX86_BUILTIN_PSHUFLW,
28284 IX86_BUILTIN_PSHUFD,
28286 IX86_BUILTIN_PSLLDQI128,
28287 IX86_BUILTIN_PSLLWI128,
28288 IX86_BUILTIN_PSLLDI128,
28289 IX86_BUILTIN_PSLLQI128,
28290 IX86_BUILTIN_PSRAWI128,
28291 IX86_BUILTIN_PSRADI128,
28292 IX86_BUILTIN_PSRLDQI128,
28293 IX86_BUILTIN_PSRLWI128,
28294 IX86_BUILTIN_PSRLDI128,
28295 IX86_BUILTIN_PSRLQI128,
28297 IX86_BUILTIN_PSLLDQ128,
28298 IX86_BUILTIN_PSLLW128,
28299 IX86_BUILTIN_PSLLD128,
28300 IX86_BUILTIN_PSLLQ128,
28301 IX86_BUILTIN_PSRAW128,
28302 IX86_BUILTIN_PSRAD128,
28303 IX86_BUILTIN_PSRLW128,
28304 IX86_BUILTIN_PSRLD128,
28305 IX86_BUILTIN_PSRLQ128,
28307 IX86_BUILTIN_PUNPCKHBW128,
28308 IX86_BUILTIN_PUNPCKHWD128,
28309 IX86_BUILTIN_PUNPCKHDQ128,
28310 IX86_BUILTIN_PUNPCKHQDQ128,
28311 IX86_BUILTIN_PUNPCKLBW128,
28312 IX86_BUILTIN_PUNPCKLWD128,
28313 IX86_BUILTIN_PUNPCKLDQ128,
28314 IX86_BUILTIN_PUNPCKLQDQ128,
28316 IX86_BUILTIN_CLFLUSH,
28317 IX86_BUILTIN_MFENCE,
28318 IX86_BUILTIN_LFENCE,
28319 IX86_BUILTIN_PAUSE,
28321 IX86_BUILTIN_FNSTENV,
28322 IX86_BUILTIN_FLDENV,
28323 IX86_BUILTIN_FNSTSW,
28324 IX86_BUILTIN_FNCLEX,
28326 IX86_BUILTIN_BSRSI,
28327 IX86_BUILTIN_BSRDI,
28328 IX86_BUILTIN_RDPMC,
28329 IX86_BUILTIN_RDTSC,
28330 IX86_BUILTIN_RDTSCP,
28331 IX86_BUILTIN_ROLQI,
28332 IX86_BUILTIN_ROLHI,
28333 IX86_BUILTIN_RORQI,
28334 IX86_BUILTIN_RORHI,
28336 /* SSE3. */
28337 IX86_BUILTIN_ADDSUBPS,
28338 IX86_BUILTIN_HADDPS,
28339 IX86_BUILTIN_HSUBPS,
28340 IX86_BUILTIN_MOVSHDUP,
28341 IX86_BUILTIN_MOVSLDUP,
28342 IX86_BUILTIN_ADDSUBPD,
28343 IX86_BUILTIN_HADDPD,
28344 IX86_BUILTIN_HSUBPD,
28345 IX86_BUILTIN_LDDQU,
28347 IX86_BUILTIN_MONITOR,
28348 IX86_BUILTIN_MWAIT,
28350 /* SSSE3. */
28351 IX86_BUILTIN_PHADDW,
28352 IX86_BUILTIN_PHADDD,
28353 IX86_BUILTIN_PHADDSW,
28354 IX86_BUILTIN_PHSUBW,
28355 IX86_BUILTIN_PHSUBD,
28356 IX86_BUILTIN_PHSUBSW,
28357 IX86_BUILTIN_PMADDUBSW,
28358 IX86_BUILTIN_PMULHRSW,
28359 IX86_BUILTIN_PSHUFB,
28360 IX86_BUILTIN_PSIGNB,
28361 IX86_BUILTIN_PSIGNW,
28362 IX86_BUILTIN_PSIGND,
28363 IX86_BUILTIN_PALIGNR,
28364 IX86_BUILTIN_PABSB,
28365 IX86_BUILTIN_PABSW,
28366 IX86_BUILTIN_PABSD,
28368 IX86_BUILTIN_PHADDW128,
28369 IX86_BUILTIN_PHADDD128,
28370 IX86_BUILTIN_PHADDSW128,
28371 IX86_BUILTIN_PHSUBW128,
28372 IX86_BUILTIN_PHSUBD128,
28373 IX86_BUILTIN_PHSUBSW128,
28374 IX86_BUILTIN_PMADDUBSW128,
28375 IX86_BUILTIN_PMULHRSW128,
28376 IX86_BUILTIN_PSHUFB128,
28377 IX86_BUILTIN_PSIGNB128,
28378 IX86_BUILTIN_PSIGNW128,
28379 IX86_BUILTIN_PSIGND128,
28380 IX86_BUILTIN_PALIGNR128,
28381 IX86_BUILTIN_PABSB128,
28382 IX86_BUILTIN_PABSW128,
28383 IX86_BUILTIN_PABSD128,
28385 /* AMDFAM10 - SSE4A New Instructions. */
28386 IX86_BUILTIN_MOVNTSD,
28387 IX86_BUILTIN_MOVNTSS,
28388 IX86_BUILTIN_EXTRQI,
28389 IX86_BUILTIN_EXTRQ,
28390 IX86_BUILTIN_INSERTQI,
28391 IX86_BUILTIN_INSERTQ,
28393 /* SSE4.1. */
28394 IX86_BUILTIN_BLENDPD,
28395 IX86_BUILTIN_BLENDPS,
28396 IX86_BUILTIN_BLENDVPD,
28397 IX86_BUILTIN_BLENDVPS,
28398 IX86_BUILTIN_PBLENDVB128,
28399 IX86_BUILTIN_PBLENDW128,
28401 IX86_BUILTIN_DPPD,
28402 IX86_BUILTIN_DPPS,
28404 IX86_BUILTIN_INSERTPS128,
28406 IX86_BUILTIN_MOVNTDQA,
28407 IX86_BUILTIN_MPSADBW128,
28408 IX86_BUILTIN_PACKUSDW128,
28409 IX86_BUILTIN_PCMPEQQ,
28410 IX86_BUILTIN_PHMINPOSUW128,
28412 IX86_BUILTIN_PMAXSB128,
28413 IX86_BUILTIN_PMAXSD128,
28414 IX86_BUILTIN_PMAXUD128,
28415 IX86_BUILTIN_PMAXUW128,
28417 IX86_BUILTIN_PMINSB128,
28418 IX86_BUILTIN_PMINSD128,
28419 IX86_BUILTIN_PMINUD128,
28420 IX86_BUILTIN_PMINUW128,
28422 IX86_BUILTIN_PMOVSXBW128,
28423 IX86_BUILTIN_PMOVSXBD128,
28424 IX86_BUILTIN_PMOVSXBQ128,
28425 IX86_BUILTIN_PMOVSXWD128,
28426 IX86_BUILTIN_PMOVSXWQ128,
28427 IX86_BUILTIN_PMOVSXDQ128,
28429 IX86_BUILTIN_PMOVZXBW128,
28430 IX86_BUILTIN_PMOVZXBD128,
28431 IX86_BUILTIN_PMOVZXBQ128,
28432 IX86_BUILTIN_PMOVZXWD128,
28433 IX86_BUILTIN_PMOVZXWQ128,
28434 IX86_BUILTIN_PMOVZXDQ128,
28436 IX86_BUILTIN_PMULDQ128,
28437 IX86_BUILTIN_PMULLD128,
28439 IX86_BUILTIN_ROUNDSD,
28440 IX86_BUILTIN_ROUNDSS,
28442 IX86_BUILTIN_ROUNDPD,
28443 IX86_BUILTIN_ROUNDPS,
28445 IX86_BUILTIN_FLOORPD,
28446 IX86_BUILTIN_CEILPD,
28447 IX86_BUILTIN_TRUNCPD,
28448 IX86_BUILTIN_RINTPD,
28449 IX86_BUILTIN_ROUNDPD_AZ,
28451 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX,
28452 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX,
28453 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX,
28455 IX86_BUILTIN_FLOORPS,
28456 IX86_BUILTIN_CEILPS,
28457 IX86_BUILTIN_TRUNCPS,
28458 IX86_BUILTIN_RINTPS,
28459 IX86_BUILTIN_ROUNDPS_AZ,
28461 IX86_BUILTIN_FLOORPS_SFIX,
28462 IX86_BUILTIN_CEILPS_SFIX,
28463 IX86_BUILTIN_ROUNDPS_AZ_SFIX,
28465 IX86_BUILTIN_PTESTZ,
28466 IX86_BUILTIN_PTESTC,
28467 IX86_BUILTIN_PTESTNZC,
28469 IX86_BUILTIN_VEC_INIT_V2SI,
28470 IX86_BUILTIN_VEC_INIT_V4HI,
28471 IX86_BUILTIN_VEC_INIT_V8QI,
28472 IX86_BUILTIN_VEC_EXT_V2DF,
28473 IX86_BUILTIN_VEC_EXT_V2DI,
28474 IX86_BUILTIN_VEC_EXT_V4SF,
28475 IX86_BUILTIN_VEC_EXT_V4SI,
28476 IX86_BUILTIN_VEC_EXT_V8HI,
28477 IX86_BUILTIN_VEC_EXT_V2SI,
28478 IX86_BUILTIN_VEC_EXT_V4HI,
28479 IX86_BUILTIN_VEC_EXT_V16QI,
28480 IX86_BUILTIN_VEC_SET_V2DI,
28481 IX86_BUILTIN_VEC_SET_V4SF,
28482 IX86_BUILTIN_VEC_SET_V4SI,
28483 IX86_BUILTIN_VEC_SET_V8HI,
28484 IX86_BUILTIN_VEC_SET_V4HI,
28485 IX86_BUILTIN_VEC_SET_V16QI,
28487 IX86_BUILTIN_VEC_PACK_SFIX,
28488 IX86_BUILTIN_VEC_PACK_SFIX256,
28490 /* SSE4.2. */
28491 IX86_BUILTIN_CRC32QI,
28492 IX86_BUILTIN_CRC32HI,
28493 IX86_BUILTIN_CRC32SI,
28494 IX86_BUILTIN_CRC32DI,
28496 IX86_BUILTIN_PCMPESTRI128,
28497 IX86_BUILTIN_PCMPESTRM128,
28498 IX86_BUILTIN_PCMPESTRA128,
28499 IX86_BUILTIN_PCMPESTRC128,
28500 IX86_BUILTIN_PCMPESTRO128,
28501 IX86_BUILTIN_PCMPESTRS128,
28502 IX86_BUILTIN_PCMPESTRZ128,
28503 IX86_BUILTIN_PCMPISTRI128,
28504 IX86_BUILTIN_PCMPISTRM128,
28505 IX86_BUILTIN_PCMPISTRA128,
28506 IX86_BUILTIN_PCMPISTRC128,
28507 IX86_BUILTIN_PCMPISTRO128,
28508 IX86_BUILTIN_PCMPISTRS128,
28509 IX86_BUILTIN_PCMPISTRZ128,
28511 IX86_BUILTIN_PCMPGTQ,
28513 /* AES instructions */
28514 IX86_BUILTIN_AESENC128,
28515 IX86_BUILTIN_AESENCLAST128,
28516 IX86_BUILTIN_AESDEC128,
28517 IX86_BUILTIN_AESDECLAST128,
28518 IX86_BUILTIN_AESIMC128,
28519 IX86_BUILTIN_AESKEYGENASSIST128,
28521 /* PCLMUL instruction */
28522 IX86_BUILTIN_PCLMULQDQ128,
28524 /* AVX */
28525 IX86_BUILTIN_ADDPD256,
28526 IX86_BUILTIN_ADDPS256,
28527 IX86_BUILTIN_ADDSUBPD256,
28528 IX86_BUILTIN_ADDSUBPS256,
28529 IX86_BUILTIN_ANDPD256,
28530 IX86_BUILTIN_ANDPS256,
28531 IX86_BUILTIN_ANDNPD256,
28532 IX86_BUILTIN_ANDNPS256,
28533 IX86_BUILTIN_BLENDPD256,
28534 IX86_BUILTIN_BLENDPS256,
28535 IX86_BUILTIN_BLENDVPD256,
28536 IX86_BUILTIN_BLENDVPS256,
28537 IX86_BUILTIN_DIVPD256,
28538 IX86_BUILTIN_DIVPS256,
28539 IX86_BUILTIN_DPPS256,
28540 IX86_BUILTIN_HADDPD256,
28541 IX86_BUILTIN_HADDPS256,
28542 IX86_BUILTIN_HSUBPD256,
28543 IX86_BUILTIN_HSUBPS256,
28544 IX86_BUILTIN_MAXPD256,
28545 IX86_BUILTIN_MAXPS256,
28546 IX86_BUILTIN_MINPD256,
28547 IX86_BUILTIN_MINPS256,
28548 IX86_BUILTIN_MULPD256,
28549 IX86_BUILTIN_MULPS256,
28550 IX86_BUILTIN_ORPD256,
28551 IX86_BUILTIN_ORPS256,
28552 IX86_BUILTIN_SHUFPD256,
28553 IX86_BUILTIN_SHUFPS256,
28554 IX86_BUILTIN_SUBPD256,
28555 IX86_BUILTIN_SUBPS256,
28556 IX86_BUILTIN_XORPD256,
28557 IX86_BUILTIN_XORPS256,
28558 IX86_BUILTIN_CMPSD,
28559 IX86_BUILTIN_CMPSS,
28560 IX86_BUILTIN_CMPPD,
28561 IX86_BUILTIN_CMPPS,
28562 IX86_BUILTIN_CMPPD256,
28563 IX86_BUILTIN_CMPPS256,
28564 IX86_BUILTIN_CVTDQ2PD256,
28565 IX86_BUILTIN_CVTDQ2PS256,
28566 IX86_BUILTIN_CVTPD2PS256,
28567 IX86_BUILTIN_CVTPS2DQ256,
28568 IX86_BUILTIN_CVTPS2PD256,
28569 IX86_BUILTIN_CVTTPD2DQ256,
28570 IX86_BUILTIN_CVTPD2DQ256,
28571 IX86_BUILTIN_CVTTPS2DQ256,
28572 IX86_BUILTIN_EXTRACTF128PD256,
28573 IX86_BUILTIN_EXTRACTF128PS256,
28574 IX86_BUILTIN_EXTRACTF128SI256,
28575 IX86_BUILTIN_VZEROALL,
28576 IX86_BUILTIN_VZEROUPPER,
28577 IX86_BUILTIN_VPERMILVARPD,
28578 IX86_BUILTIN_VPERMILVARPS,
28579 IX86_BUILTIN_VPERMILVARPD256,
28580 IX86_BUILTIN_VPERMILVARPS256,
28581 IX86_BUILTIN_VPERMILPD,
28582 IX86_BUILTIN_VPERMILPS,
28583 IX86_BUILTIN_VPERMILPD256,
28584 IX86_BUILTIN_VPERMILPS256,
28585 IX86_BUILTIN_VPERMIL2PD,
28586 IX86_BUILTIN_VPERMIL2PS,
28587 IX86_BUILTIN_VPERMIL2PD256,
28588 IX86_BUILTIN_VPERMIL2PS256,
28589 IX86_BUILTIN_VPERM2F128PD256,
28590 IX86_BUILTIN_VPERM2F128PS256,
28591 IX86_BUILTIN_VPERM2F128SI256,
28592 IX86_BUILTIN_VBROADCASTSS,
28593 IX86_BUILTIN_VBROADCASTSD256,
28594 IX86_BUILTIN_VBROADCASTSS256,
28595 IX86_BUILTIN_VBROADCASTPD256,
28596 IX86_BUILTIN_VBROADCASTPS256,
28597 IX86_BUILTIN_VINSERTF128PD256,
28598 IX86_BUILTIN_VINSERTF128PS256,
28599 IX86_BUILTIN_VINSERTF128SI256,
28600 IX86_BUILTIN_LOADUPD256,
28601 IX86_BUILTIN_LOADUPS256,
28602 IX86_BUILTIN_STOREUPD256,
28603 IX86_BUILTIN_STOREUPS256,
28604 IX86_BUILTIN_LDDQU256,
28605 IX86_BUILTIN_MOVNTDQ256,
28606 IX86_BUILTIN_MOVNTPD256,
28607 IX86_BUILTIN_MOVNTPS256,
28608 IX86_BUILTIN_LOADDQU256,
28609 IX86_BUILTIN_STOREDQU256,
28610 IX86_BUILTIN_MASKLOADPD,
28611 IX86_BUILTIN_MASKLOADPS,
28612 IX86_BUILTIN_MASKSTOREPD,
28613 IX86_BUILTIN_MASKSTOREPS,
28614 IX86_BUILTIN_MASKLOADPD256,
28615 IX86_BUILTIN_MASKLOADPS256,
28616 IX86_BUILTIN_MASKSTOREPD256,
28617 IX86_BUILTIN_MASKSTOREPS256,
28618 IX86_BUILTIN_MOVSHDUP256,
28619 IX86_BUILTIN_MOVSLDUP256,
28620 IX86_BUILTIN_MOVDDUP256,
28622 IX86_BUILTIN_SQRTPD256,
28623 IX86_BUILTIN_SQRTPS256,
28624 IX86_BUILTIN_SQRTPS_NR256,
28625 IX86_BUILTIN_RSQRTPS256,
28626 IX86_BUILTIN_RSQRTPS_NR256,
28628 IX86_BUILTIN_RCPPS256,
28630 IX86_BUILTIN_ROUNDPD256,
28631 IX86_BUILTIN_ROUNDPS256,
28633 IX86_BUILTIN_FLOORPD256,
28634 IX86_BUILTIN_CEILPD256,
28635 IX86_BUILTIN_TRUNCPD256,
28636 IX86_BUILTIN_RINTPD256,
28637 IX86_BUILTIN_ROUNDPD_AZ256,
28639 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256,
28640 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256,
28641 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256,
28643 IX86_BUILTIN_FLOORPS256,
28644 IX86_BUILTIN_CEILPS256,
28645 IX86_BUILTIN_TRUNCPS256,
28646 IX86_BUILTIN_RINTPS256,
28647 IX86_BUILTIN_ROUNDPS_AZ256,
28649 IX86_BUILTIN_FLOORPS_SFIX256,
28650 IX86_BUILTIN_CEILPS_SFIX256,
28651 IX86_BUILTIN_ROUNDPS_AZ_SFIX256,
28653 IX86_BUILTIN_UNPCKHPD256,
28654 IX86_BUILTIN_UNPCKLPD256,
28655 IX86_BUILTIN_UNPCKHPS256,
28656 IX86_BUILTIN_UNPCKLPS256,
28658 IX86_BUILTIN_SI256_SI,
28659 IX86_BUILTIN_PS256_PS,
28660 IX86_BUILTIN_PD256_PD,
28661 IX86_BUILTIN_SI_SI256,
28662 IX86_BUILTIN_PS_PS256,
28663 IX86_BUILTIN_PD_PD256,
28665 IX86_BUILTIN_VTESTZPD,
28666 IX86_BUILTIN_VTESTCPD,
28667 IX86_BUILTIN_VTESTNZCPD,
28668 IX86_BUILTIN_VTESTZPS,
28669 IX86_BUILTIN_VTESTCPS,
28670 IX86_BUILTIN_VTESTNZCPS,
28671 IX86_BUILTIN_VTESTZPD256,
28672 IX86_BUILTIN_VTESTCPD256,
28673 IX86_BUILTIN_VTESTNZCPD256,
28674 IX86_BUILTIN_VTESTZPS256,
28675 IX86_BUILTIN_VTESTCPS256,
28676 IX86_BUILTIN_VTESTNZCPS256,
28677 IX86_BUILTIN_PTESTZ256,
28678 IX86_BUILTIN_PTESTC256,
28679 IX86_BUILTIN_PTESTNZC256,
28681 IX86_BUILTIN_MOVMSKPD256,
28682 IX86_BUILTIN_MOVMSKPS256,
28684 /* AVX2 */
28685 IX86_BUILTIN_MPSADBW256,
28686 IX86_BUILTIN_PABSB256,
28687 IX86_BUILTIN_PABSW256,
28688 IX86_BUILTIN_PABSD256,
28689 IX86_BUILTIN_PACKSSDW256,
28690 IX86_BUILTIN_PACKSSWB256,
28691 IX86_BUILTIN_PACKUSDW256,
28692 IX86_BUILTIN_PACKUSWB256,
28693 IX86_BUILTIN_PADDB256,
28694 IX86_BUILTIN_PADDW256,
28695 IX86_BUILTIN_PADDD256,
28696 IX86_BUILTIN_PADDQ256,
28697 IX86_BUILTIN_PADDSB256,
28698 IX86_BUILTIN_PADDSW256,
28699 IX86_BUILTIN_PADDUSB256,
28700 IX86_BUILTIN_PADDUSW256,
28701 IX86_BUILTIN_PALIGNR256,
28702 IX86_BUILTIN_AND256I,
28703 IX86_BUILTIN_ANDNOT256I,
28704 IX86_BUILTIN_PAVGB256,
28705 IX86_BUILTIN_PAVGW256,
28706 IX86_BUILTIN_PBLENDVB256,
28707 IX86_BUILTIN_PBLENDVW256,
28708 IX86_BUILTIN_PCMPEQB256,
28709 IX86_BUILTIN_PCMPEQW256,
28710 IX86_BUILTIN_PCMPEQD256,
28711 IX86_BUILTIN_PCMPEQQ256,
28712 IX86_BUILTIN_PCMPGTB256,
28713 IX86_BUILTIN_PCMPGTW256,
28714 IX86_BUILTIN_PCMPGTD256,
28715 IX86_BUILTIN_PCMPGTQ256,
28716 IX86_BUILTIN_PHADDW256,
28717 IX86_BUILTIN_PHADDD256,
28718 IX86_BUILTIN_PHADDSW256,
28719 IX86_BUILTIN_PHSUBW256,
28720 IX86_BUILTIN_PHSUBD256,
28721 IX86_BUILTIN_PHSUBSW256,
28722 IX86_BUILTIN_PMADDUBSW256,
28723 IX86_BUILTIN_PMADDWD256,
28724 IX86_BUILTIN_PMAXSB256,
28725 IX86_BUILTIN_PMAXSW256,
28726 IX86_BUILTIN_PMAXSD256,
28727 IX86_BUILTIN_PMAXUB256,
28728 IX86_BUILTIN_PMAXUW256,
28729 IX86_BUILTIN_PMAXUD256,
28730 IX86_BUILTIN_PMINSB256,
28731 IX86_BUILTIN_PMINSW256,
28732 IX86_BUILTIN_PMINSD256,
28733 IX86_BUILTIN_PMINUB256,
28734 IX86_BUILTIN_PMINUW256,
28735 IX86_BUILTIN_PMINUD256,
28736 IX86_BUILTIN_PMOVMSKB256,
28737 IX86_BUILTIN_PMOVSXBW256,
28738 IX86_BUILTIN_PMOVSXBD256,
28739 IX86_BUILTIN_PMOVSXBQ256,
28740 IX86_BUILTIN_PMOVSXWD256,
28741 IX86_BUILTIN_PMOVSXWQ256,
28742 IX86_BUILTIN_PMOVSXDQ256,
28743 IX86_BUILTIN_PMOVZXBW256,
28744 IX86_BUILTIN_PMOVZXBD256,
28745 IX86_BUILTIN_PMOVZXBQ256,
28746 IX86_BUILTIN_PMOVZXWD256,
28747 IX86_BUILTIN_PMOVZXWQ256,
28748 IX86_BUILTIN_PMOVZXDQ256,
28749 IX86_BUILTIN_PMULDQ256,
28750 IX86_BUILTIN_PMULHRSW256,
28751 IX86_BUILTIN_PMULHUW256,
28752 IX86_BUILTIN_PMULHW256,
28753 IX86_BUILTIN_PMULLW256,
28754 IX86_BUILTIN_PMULLD256,
28755 IX86_BUILTIN_PMULUDQ256,
28756 IX86_BUILTIN_POR256,
28757 IX86_BUILTIN_PSADBW256,
28758 IX86_BUILTIN_PSHUFB256,
28759 IX86_BUILTIN_PSHUFD256,
28760 IX86_BUILTIN_PSHUFHW256,
28761 IX86_BUILTIN_PSHUFLW256,
28762 IX86_BUILTIN_PSIGNB256,
28763 IX86_BUILTIN_PSIGNW256,
28764 IX86_BUILTIN_PSIGND256,
28765 IX86_BUILTIN_PSLLDQI256,
28766 IX86_BUILTIN_PSLLWI256,
28767 IX86_BUILTIN_PSLLW256,
28768 IX86_BUILTIN_PSLLDI256,
28769 IX86_BUILTIN_PSLLD256,
28770 IX86_BUILTIN_PSLLQI256,
28771 IX86_BUILTIN_PSLLQ256,
28772 IX86_BUILTIN_PSRAWI256,
28773 IX86_BUILTIN_PSRAW256,
28774 IX86_BUILTIN_PSRADI256,
28775 IX86_BUILTIN_PSRAD256,
28776 IX86_BUILTIN_PSRLDQI256,
28777 IX86_BUILTIN_PSRLWI256,
28778 IX86_BUILTIN_PSRLW256,
28779 IX86_BUILTIN_PSRLDI256,
28780 IX86_BUILTIN_PSRLD256,
28781 IX86_BUILTIN_PSRLQI256,
28782 IX86_BUILTIN_PSRLQ256,
28783 IX86_BUILTIN_PSUBB256,
28784 IX86_BUILTIN_PSUBW256,
28785 IX86_BUILTIN_PSUBD256,
28786 IX86_BUILTIN_PSUBQ256,
28787 IX86_BUILTIN_PSUBSB256,
28788 IX86_BUILTIN_PSUBSW256,
28789 IX86_BUILTIN_PSUBUSB256,
28790 IX86_BUILTIN_PSUBUSW256,
28791 IX86_BUILTIN_PUNPCKHBW256,
28792 IX86_BUILTIN_PUNPCKHWD256,
28793 IX86_BUILTIN_PUNPCKHDQ256,
28794 IX86_BUILTIN_PUNPCKHQDQ256,
28795 IX86_BUILTIN_PUNPCKLBW256,
28796 IX86_BUILTIN_PUNPCKLWD256,
28797 IX86_BUILTIN_PUNPCKLDQ256,
28798 IX86_BUILTIN_PUNPCKLQDQ256,
28799 IX86_BUILTIN_PXOR256,
28800 IX86_BUILTIN_MOVNTDQA256,
28801 IX86_BUILTIN_VBROADCASTSS_PS,
28802 IX86_BUILTIN_VBROADCASTSS_PS256,
28803 IX86_BUILTIN_VBROADCASTSD_PD256,
28804 IX86_BUILTIN_VBROADCASTSI256,
28805 IX86_BUILTIN_PBLENDD256,
28806 IX86_BUILTIN_PBLENDD128,
28807 IX86_BUILTIN_PBROADCASTB256,
28808 IX86_BUILTIN_PBROADCASTW256,
28809 IX86_BUILTIN_PBROADCASTD256,
28810 IX86_BUILTIN_PBROADCASTQ256,
28811 IX86_BUILTIN_PBROADCASTB128,
28812 IX86_BUILTIN_PBROADCASTW128,
28813 IX86_BUILTIN_PBROADCASTD128,
28814 IX86_BUILTIN_PBROADCASTQ128,
28815 IX86_BUILTIN_VPERMVARSI256,
28816 IX86_BUILTIN_VPERMDF256,
28817 IX86_BUILTIN_VPERMVARSF256,
28818 IX86_BUILTIN_VPERMDI256,
28819 IX86_BUILTIN_VPERMTI256,
28820 IX86_BUILTIN_VEXTRACT128I256,
28821 IX86_BUILTIN_VINSERT128I256,
28822 IX86_BUILTIN_MASKLOADD,
28823 IX86_BUILTIN_MASKLOADQ,
28824 IX86_BUILTIN_MASKLOADD256,
28825 IX86_BUILTIN_MASKLOADQ256,
28826 IX86_BUILTIN_MASKSTORED,
28827 IX86_BUILTIN_MASKSTOREQ,
28828 IX86_BUILTIN_MASKSTORED256,
28829 IX86_BUILTIN_MASKSTOREQ256,
28830 IX86_BUILTIN_PSLLVV4DI,
28831 IX86_BUILTIN_PSLLVV2DI,
28832 IX86_BUILTIN_PSLLVV8SI,
28833 IX86_BUILTIN_PSLLVV4SI,
28834 IX86_BUILTIN_PSRAVV8SI,
28835 IX86_BUILTIN_PSRAVV4SI,
28836 IX86_BUILTIN_PSRLVV4DI,
28837 IX86_BUILTIN_PSRLVV2DI,
28838 IX86_BUILTIN_PSRLVV8SI,
28839 IX86_BUILTIN_PSRLVV4SI,
28841 IX86_BUILTIN_GATHERSIV2DF,
28842 IX86_BUILTIN_GATHERSIV4DF,
28843 IX86_BUILTIN_GATHERDIV2DF,
28844 IX86_BUILTIN_GATHERDIV4DF,
28845 IX86_BUILTIN_GATHERSIV4SF,
28846 IX86_BUILTIN_GATHERSIV8SF,
28847 IX86_BUILTIN_GATHERDIV4SF,
28848 IX86_BUILTIN_GATHERDIV8SF,
28849 IX86_BUILTIN_GATHERSIV2DI,
28850 IX86_BUILTIN_GATHERSIV4DI,
28851 IX86_BUILTIN_GATHERDIV2DI,
28852 IX86_BUILTIN_GATHERDIV4DI,
28853 IX86_BUILTIN_GATHERSIV4SI,
28854 IX86_BUILTIN_GATHERSIV8SI,
28855 IX86_BUILTIN_GATHERDIV4SI,
28856 IX86_BUILTIN_GATHERDIV8SI,
28858 /* AVX512F */
28859 IX86_BUILTIN_SI512_SI256,
28860 IX86_BUILTIN_PD512_PD256,
28861 IX86_BUILTIN_PS512_PS256,
28862 IX86_BUILTIN_SI512_SI,
28863 IX86_BUILTIN_PD512_PD,
28864 IX86_BUILTIN_PS512_PS,
28865 IX86_BUILTIN_ADDPD512,
28866 IX86_BUILTIN_ADDPS512,
28867 IX86_BUILTIN_ADDSD_ROUND,
28868 IX86_BUILTIN_ADDSS_ROUND,
28869 IX86_BUILTIN_ALIGND512,
28870 IX86_BUILTIN_ALIGNQ512,
28871 IX86_BUILTIN_BLENDMD512,
28872 IX86_BUILTIN_BLENDMPD512,
28873 IX86_BUILTIN_BLENDMPS512,
28874 IX86_BUILTIN_BLENDMQ512,
28875 IX86_BUILTIN_BROADCASTF32X4_512,
28876 IX86_BUILTIN_BROADCASTF64X4_512,
28877 IX86_BUILTIN_BROADCASTI32X4_512,
28878 IX86_BUILTIN_BROADCASTI64X4_512,
28879 IX86_BUILTIN_BROADCASTSD512,
28880 IX86_BUILTIN_BROADCASTSS512,
28881 IX86_BUILTIN_CMPD512,
28882 IX86_BUILTIN_CMPPD512,
28883 IX86_BUILTIN_CMPPS512,
28884 IX86_BUILTIN_CMPQ512,
28885 IX86_BUILTIN_CMPSD_MASK,
28886 IX86_BUILTIN_CMPSS_MASK,
28887 IX86_BUILTIN_COMIDF,
28888 IX86_BUILTIN_COMISF,
28889 IX86_BUILTIN_COMPRESSPD512,
28890 IX86_BUILTIN_COMPRESSPDSTORE512,
28891 IX86_BUILTIN_COMPRESSPS512,
28892 IX86_BUILTIN_COMPRESSPSSTORE512,
28893 IX86_BUILTIN_CVTDQ2PD512,
28894 IX86_BUILTIN_CVTDQ2PS512,
28895 IX86_BUILTIN_CVTPD2DQ512,
28896 IX86_BUILTIN_CVTPD2PS512,
28897 IX86_BUILTIN_CVTPD2UDQ512,
28898 IX86_BUILTIN_CVTPH2PS512,
28899 IX86_BUILTIN_CVTPS2DQ512,
28900 IX86_BUILTIN_CVTPS2PD512,
28901 IX86_BUILTIN_CVTPS2PH512,
28902 IX86_BUILTIN_CVTPS2UDQ512,
28903 IX86_BUILTIN_CVTSD2SS_ROUND,
28904 IX86_BUILTIN_CVTSI2SD64,
28905 IX86_BUILTIN_CVTSI2SS32,
28906 IX86_BUILTIN_CVTSI2SS64,
28907 IX86_BUILTIN_CVTSS2SD_ROUND,
28908 IX86_BUILTIN_CVTTPD2DQ512,
28909 IX86_BUILTIN_CVTTPD2UDQ512,
28910 IX86_BUILTIN_CVTTPS2DQ512,
28911 IX86_BUILTIN_CVTTPS2UDQ512,
28912 IX86_BUILTIN_CVTUDQ2PD512,
28913 IX86_BUILTIN_CVTUDQ2PS512,
28914 IX86_BUILTIN_CVTUSI2SD32,
28915 IX86_BUILTIN_CVTUSI2SD64,
28916 IX86_BUILTIN_CVTUSI2SS32,
28917 IX86_BUILTIN_CVTUSI2SS64,
28918 IX86_BUILTIN_DIVPD512,
28919 IX86_BUILTIN_DIVPS512,
28920 IX86_BUILTIN_DIVSD_ROUND,
28921 IX86_BUILTIN_DIVSS_ROUND,
28922 IX86_BUILTIN_EXPANDPD512,
28923 IX86_BUILTIN_EXPANDPD512Z,
28924 IX86_BUILTIN_EXPANDPDLOAD512,
28925 IX86_BUILTIN_EXPANDPDLOAD512Z,
28926 IX86_BUILTIN_EXPANDPS512,
28927 IX86_BUILTIN_EXPANDPS512Z,
28928 IX86_BUILTIN_EXPANDPSLOAD512,
28929 IX86_BUILTIN_EXPANDPSLOAD512Z,
28930 IX86_BUILTIN_EXTRACTF32X4,
28931 IX86_BUILTIN_EXTRACTF64X4,
28932 IX86_BUILTIN_EXTRACTI32X4,
28933 IX86_BUILTIN_EXTRACTI64X4,
28934 IX86_BUILTIN_FIXUPIMMPD512_MASK,
28935 IX86_BUILTIN_FIXUPIMMPD512_MASKZ,
28936 IX86_BUILTIN_FIXUPIMMPS512_MASK,
28937 IX86_BUILTIN_FIXUPIMMPS512_MASKZ,
28938 IX86_BUILTIN_FIXUPIMMSD128_MASK,
28939 IX86_BUILTIN_FIXUPIMMSD128_MASKZ,
28940 IX86_BUILTIN_FIXUPIMMSS128_MASK,
28941 IX86_BUILTIN_FIXUPIMMSS128_MASKZ,
28942 IX86_BUILTIN_GETEXPPD512,
28943 IX86_BUILTIN_GETEXPPS512,
28944 IX86_BUILTIN_GETEXPSD128,
28945 IX86_BUILTIN_GETEXPSS128,
28946 IX86_BUILTIN_GETMANTPD512,
28947 IX86_BUILTIN_GETMANTPS512,
28948 IX86_BUILTIN_GETMANTSD128,
28949 IX86_BUILTIN_GETMANTSS128,
28950 IX86_BUILTIN_INSERTF32X4,
28951 IX86_BUILTIN_INSERTF64X4,
28952 IX86_BUILTIN_INSERTI32X4,
28953 IX86_BUILTIN_INSERTI64X4,
28954 IX86_BUILTIN_LOADAPD512,
28955 IX86_BUILTIN_LOADAPS512,
28956 IX86_BUILTIN_LOADDQUDI512,
28957 IX86_BUILTIN_LOADDQUSI512,
28958 IX86_BUILTIN_LOADUPD512,
28959 IX86_BUILTIN_LOADUPS512,
28960 IX86_BUILTIN_MAXPD512,
28961 IX86_BUILTIN_MAXPS512,
28962 IX86_BUILTIN_MAXSD_ROUND,
28963 IX86_BUILTIN_MAXSS_ROUND,
28964 IX86_BUILTIN_MINPD512,
28965 IX86_BUILTIN_MINPS512,
28966 IX86_BUILTIN_MINSD_ROUND,
28967 IX86_BUILTIN_MINSS_ROUND,
28968 IX86_BUILTIN_MOVAPD512,
28969 IX86_BUILTIN_MOVAPS512,
28970 IX86_BUILTIN_MOVDDUP512,
28971 IX86_BUILTIN_MOVDQA32LOAD512,
28972 IX86_BUILTIN_MOVDQA32STORE512,
28973 IX86_BUILTIN_MOVDQA32_512,
28974 IX86_BUILTIN_MOVDQA64LOAD512,
28975 IX86_BUILTIN_MOVDQA64STORE512,
28976 IX86_BUILTIN_MOVDQA64_512,
28977 IX86_BUILTIN_MOVNTDQ512,
28978 IX86_BUILTIN_MOVNTDQA512,
28979 IX86_BUILTIN_MOVNTPD512,
28980 IX86_BUILTIN_MOVNTPS512,
28981 IX86_BUILTIN_MOVSHDUP512,
28982 IX86_BUILTIN_MOVSLDUP512,
28983 IX86_BUILTIN_MULPD512,
28984 IX86_BUILTIN_MULPS512,
28985 IX86_BUILTIN_MULSD_ROUND,
28986 IX86_BUILTIN_MULSS_ROUND,
28987 IX86_BUILTIN_PABSD512,
28988 IX86_BUILTIN_PABSQ512,
28989 IX86_BUILTIN_PADDD512,
28990 IX86_BUILTIN_PADDQ512,
28991 IX86_BUILTIN_PANDD512,
28992 IX86_BUILTIN_PANDND512,
28993 IX86_BUILTIN_PANDNQ512,
28994 IX86_BUILTIN_PANDQ512,
28995 IX86_BUILTIN_PBROADCASTD512,
28996 IX86_BUILTIN_PBROADCASTD512_GPR,
28997 IX86_BUILTIN_PBROADCASTMB512,
28998 IX86_BUILTIN_PBROADCASTMW512,
28999 IX86_BUILTIN_PBROADCASTQ512,
29000 IX86_BUILTIN_PBROADCASTQ512_GPR,
29001 IX86_BUILTIN_PCMPEQD512_MASK,
29002 IX86_BUILTIN_PCMPEQQ512_MASK,
29003 IX86_BUILTIN_PCMPGTD512_MASK,
29004 IX86_BUILTIN_PCMPGTQ512_MASK,
29005 IX86_BUILTIN_PCOMPRESSD512,
29006 IX86_BUILTIN_PCOMPRESSDSTORE512,
29007 IX86_BUILTIN_PCOMPRESSQ512,
29008 IX86_BUILTIN_PCOMPRESSQSTORE512,
29009 IX86_BUILTIN_PEXPANDD512,
29010 IX86_BUILTIN_PEXPANDD512Z,
29011 IX86_BUILTIN_PEXPANDDLOAD512,
29012 IX86_BUILTIN_PEXPANDDLOAD512Z,
29013 IX86_BUILTIN_PEXPANDQ512,
29014 IX86_BUILTIN_PEXPANDQ512Z,
29015 IX86_BUILTIN_PEXPANDQLOAD512,
29016 IX86_BUILTIN_PEXPANDQLOAD512Z,
29017 IX86_BUILTIN_PMAXSD512,
29018 IX86_BUILTIN_PMAXSQ512,
29019 IX86_BUILTIN_PMAXUD512,
29020 IX86_BUILTIN_PMAXUQ512,
29021 IX86_BUILTIN_PMINSD512,
29022 IX86_BUILTIN_PMINSQ512,
29023 IX86_BUILTIN_PMINUD512,
29024 IX86_BUILTIN_PMINUQ512,
29025 IX86_BUILTIN_PMOVDB512,
29026 IX86_BUILTIN_PMOVDB512_MEM,
29027 IX86_BUILTIN_PMOVDW512,
29028 IX86_BUILTIN_PMOVDW512_MEM,
29029 IX86_BUILTIN_PMOVQB512,
29030 IX86_BUILTIN_PMOVQB512_MEM,
29031 IX86_BUILTIN_PMOVQD512,
29032 IX86_BUILTIN_PMOVQD512_MEM,
29033 IX86_BUILTIN_PMOVQW512,
29034 IX86_BUILTIN_PMOVQW512_MEM,
29035 IX86_BUILTIN_PMOVSDB512,
29036 IX86_BUILTIN_PMOVSDB512_MEM,
29037 IX86_BUILTIN_PMOVSDW512,
29038 IX86_BUILTIN_PMOVSDW512_MEM,
29039 IX86_BUILTIN_PMOVSQB512,
29040 IX86_BUILTIN_PMOVSQB512_MEM,
29041 IX86_BUILTIN_PMOVSQD512,
29042 IX86_BUILTIN_PMOVSQD512_MEM,
29043 IX86_BUILTIN_PMOVSQW512,
29044 IX86_BUILTIN_PMOVSQW512_MEM,
29045 IX86_BUILTIN_PMOVSXBD512,
29046 IX86_BUILTIN_PMOVSXBQ512,
29047 IX86_BUILTIN_PMOVSXDQ512,
29048 IX86_BUILTIN_PMOVSXWD512,
29049 IX86_BUILTIN_PMOVSXWQ512,
29050 IX86_BUILTIN_PMOVUSDB512,
29051 IX86_BUILTIN_PMOVUSDB512_MEM,
29052 IX86_BUILTIN_PMOVUSDW512,
29053 IX86_BUILTIN_PMOVUSDW512_MEM,
29054 IX86_BUILTIN_PMOVUSQB512,
29055 IX86_BUILTIN_PMOVUSQB512_MEM,
29056 IX86_BUILTIN_PMOVUSQD512,
29057 IX86_BUILTIN_PMOVUSQD512_MEM,
29058 IX86_BUILTIN_PMOVUSQW512,
29059 IX86_BUILTIN_PMOVUSQW512_MEM,
29060 IX86_BUILTIN_PMOVZXBD512,
29061 IX86_BUILTIN_PMOVZXBQ512,
29062 IX86_BUILTIN_PMOVZXDQ512,
29063 IX86_BUILTIN_PMOVZXWD512,
29064 IX86_BUILTIN_PMOVZXWQ512,
29065 IX86_BUILTIN_PMULDQ512,
29066 IX86_BUILTIN_PMULLD512,
29067 IX86_BUILTIN_PMULUDQ512,
29068 IX86_BUILTIN_PORD512,
29069 IX86_BUILTIN_PORQ512,
29070 IX86_BUILTIN_PROLD512,
29071 IX86_BUILTIN_PROLQ512,
29072 IX86_BUILTIN_PROLVD512,
29073 IX86_BUILTIN_PROLVQ512,
29074 IX86_BUILTIN_PRORD512,
29075 IX86_BUILTIN_PRORQ512,
29076 IX86_BUILTIN_PRORVD512,
29077 IX86_BUILTIN_PRORVQ512,
29078 IX86_BUILTIN_PSHUFD512,
29079 IX86_BUILTIN_PSLLD512,
29080 IX86_BUILTIN_PSLLDI512,
29081 IX86_BUILTIN_PSLLQ512,
29082 IX86_BUILTIN_PSLLQI512,
29083 IX86_BUILTIN_PSLLVV16SI,
29084 IX86_BUILTIN_PSLLVV8DI,
29085 IX86_BUILTIN_PSRAD512,
29086 IX86_BUILTIN_PSRADI512,
29087 IX86_BUILTIN_PSRAQ512,
29088 IX86_BUILTIN_PSRAQI512,
29089 IX86_BUILTIN_PSRAVV16SI,
29090 IX86_BUILTIN_PSRAVV8DI,
29091 IX86_BUILTIN_PSRLD512,
29092 IX86_BUILTIN_PSRLDI512,
29093 IX86_BUILTIN_PSRLQ512,
29094 IX86_BUILTIN_PSRLQI512,
29095 IX86_BUILTIN_PSRLVV16SI,
29096 IX86_BUILTIN_PSRLVV8DI,
29097 IX86_BUILTIN_PSUBD512,
29098 IX86_BUILTIN_PSUBQ512,
29099 IX86_BUILTIN_PTESTMD512,
29100 IX86_BUILTIN_PTESTMQ512,
29101 IX86_BUILTIN_PTESTNMD512,
29102 IX86_BUILTIN_PTESTNMQ512,
29103 IX86_BUILTIN_PUNPCKHDQ512,
29104 IX86_BUILTIN_PUNPCKHQDQ512,
29105 IX86_BUILTIN_PUNPCKLDQ512,
29106 IX86_BUILTIN_PUNPCKLQDQ512,
29107 IX86_BUILTIN_PXORD512,
29108 IX86_BUILTIN_PXORQ512,
29109 IX86_BUILTIN_RCP14PD512,
29110 IX86_BUILTIN_RCP14PS512,
29111 IX86_BUILTIN_RCP14SD,
29112 IX86_BUILTIN_RCP14SS,
29113 IX86_BUILTIN_RNDSCALEPD,
29114 IX86_BUILTIN_RNDSCALEPS,
29115 IX86_BUILTIN_RNDSCALESD,
29116 IX86_BUILTIN_RNDSCALESS,
29117 IX86_BUILTIN_RSQRT14PD512,
29118 IX86_BUILTIN_RSQRT14PS512,
29119 IX86_BUILTIN_RSQRT14SD,
29120 IX86_BUILTIN_RSQRT14SS,
29121 IX86_BUILTIN_SCALEFPD512,
29122 IX86_BUILTIN_SCALEFPS512,
29123 IX86_BUILTIN_SCALEFSD,
29124 IX86_BUILTIN_SCALEFSS,
29125 IX86_BUILTIN_SHUFPD512,
29126 IX86_BUILTIN_SHUFPS512,
29127 IX86_BUILTIN_SHUF_F32x4,
29128 IX86_BUILTIN_SHUF_F64x2,
29129 IX86_BUILTIN_SHUF_I32x4,
29130 IX86_BUILTIN_SHUF_I64x2,
29131 IX86_BUILTIN_SQRTPD512,
29132 IX86_BUILTIN_SQRTPD512_MASK,
29133 IX86_BUILTIN_SQRTPS512_MASK,
29134 IX86_BUILTIN_SQRTPS_NR512,
29135 IX86_BUILTIN_SQRTSD_ROUND,
29136 IX86_BUILTIN_SQRTSS_ROUND,
29137 IX86_BUILTIN_STOREAPD512,
29138 IX86_BUILTIN_STOREAPS512,
29139 IX86_BUILTIN_STOREDQUDI512,
29140 IX86_BUILTIN_STOREDQUSI512,
29141 IX86_BUILTIN_STOREUPD512,
29142 IX86_BUILTIN_STOREUPS512,
29143 IX86_BUILTIN_SUBPD512,
29144 IX86_BUILTIN_SUBPS512,
29145 IX86_BUILTIN_SUBSD_ROUND,
29146 IX86_BUILTIN_SUBSS_ROUND,
29147 IX86_BUILTIN_UCMPD512,
29148 IX86_BUILTIN_UCMPQ512,
29149 IX86_BUILTIN_UNPCKHPD512,
29150 IX86_BUILTIN_UNPCKHPS512,
29151 IX86_BUILTIN_UNPCKLPD512,
29152 IX86_BUILTIN_UNPCKLPS512,
29153 IX86_BUILTIN_VCVTSD2SI32,
29154 IX86_BUILTIN_VCVTSD2SI64,
29155 IX86_BUILTIN_VCVTSD2USI32,
29156 IX86_BUILTIN_VCVTSD2USI64,
29157 IX86_BUILTIN_VCVTSS2SI32,
29158 IX86_BUILTIN_VCVTSS2SI64,
29159 IX86_BUILTIN_VCVTSS2USI32,
29160 IX86_BUILTIN_VCVTSS2USI64,
29161 IX86_BUILTIN_VCVTTSD2SI32,
29162 IX86_BUILTIN_VCVTTSD2SI64,
29163 IX86_BUILTIN_VCVTTSD2USI32,
29164 IX86_BUILTIN_VCVTTSD2USI64,
29165 IX86_BUILTIN_VCVTTSS2SI32,
29166 IX86_BUILTIN_VCVTTSS2SI64,
29167 IX86_BUILTIN_VCVTTSS2USI32,
29168 IX86_BUILTIN_VCVTTSS2USI64,
29169 IX86_BUILTIN_VFMADDPD512_MASK,
29170 IX86_BUILTIN_VFMADDPD512_MASK3,
29171 IX86_BUILTIN_VFMADDPD512_MASKZ,
29172 IX86_BUILTIN_VFMADDPS512_MASK,
29173 IX86_BUILTIN_VFMADDPS512_MASK3,
29174 IX86_BUILTIN_VFMADDPS512_MASKZ,
29175 IX86_BUILTIN_VFMADDSD3_ROUND,
29176 IX86_BUILTIN_VFMADDSS3_ROUND,
29177 IX86_BUILTIN_VFMADDSUBPD512_MASK,
29178 IX86_BUILTIN_VFMADDSUBPD512_MASK3,
29179 IX86_BUILTIN_VFMADDSUBPD512_MASKZ,
29180 IX86_BUILTIN_VFMADDSUBPS512_MASK,
29181 IX86_BUILTIN_VFMADDSUBPS512_MASK3,
29182 IX86_BUILTIN_VFMADDSUBPS512_MASKZ,
29183 IX86_BUILTIN_VFMSUBADDPD512_MASK3,
29184 IX86_BUILTIN_VFMSUBADDPS512_MASK3,
29185 IX86_BUILTIN_VFMSUBPD512_MASK3,
29186 IX86_BUILTIN_VFMSUBPS512_MASK3,
29187 IX86_BUILTIN_VFMSUBSD3_MASK3,
29188 IX86_BUILTIN_VFMSUBSS3_MASK3,
29189 IX86_BUILTIN_VFNMADDPD512_MASK,
29190 IX86_BUILTIN_VFNMADDPS512_MASK,
29191 IX86_BUILTIN_VFNMSUBPD512_MASK,
29192 IX86_BUILTIN_VFNMSUBPD512_MASK3,
29193 IX86_BUILTIN_VFNMSUBPS512_MASK,
29194 IX86_BUILTIN_VFNMSUBPS512_MASK3,
29195 IX86_BUILTIN_VPCLZCNTD512,
29196 IX86_BUILTIN_VPCLZCNTQ512,
29197 IX86_BUILTIN_VPCONFLICTD512,
29198 IX86_BUILTIN_VPCONFLICTQ512,
29199 IX86_BUILTIN_VPERMDF512,
29200 IX86_BUILTIN_VPERMDI512,
29201 IX86_BUILTIN_VPERMI2VARD512,
29202 IX86_BUILTIN_VPERMI2VARPD512,
29203 IX86_BUILTIN_VPERMI2VARPS512,
29204 IX86_BUILTIN_VPERMI2VARQ512,
29205 IX86_BUILTIN_VPERMILPD512,
29206 IX86_BUILTIN_VPERMILPS512,
29207 IX86_BUILTIN_VPERMILVARPD512,
29208 IX86_BUILTIN_VPERMILVARPS512,
29209 IX86_BUILTIN_VPERMT2VARD512,
29210 IX86_BUILTIN_VPERMT2VARD512_MASKZ,
29211 IX86_BUILTIN_VPERMT2VARPD512,
29212 IX86_BUILTIN_VPERMT2VARPD512_MASKZ,
29213 IX86_BUILTIN_VPERMT2VARPS512,
29214 IX86_BUILTIN_VPERMT2VARPS512_MASKZ,
29215 IX86_BUILTIN_VPERMT2VARQ512,
29216 IX86_BUILTIN_VPERMT2VARQ512_MASKZ,
29217 IX86_BUILTIN_VPERMVARDF512,
29218 IX86_BUILTIN_VPERMVARDI512,
29219 IX86_BUILTIN_VPERMVARSF512,
29220 IX86_BUILTIN_VPERMVARSI512,
29221 IX86_BUILTIN_VTERNLOGD512_MASK,
29222 IX86_BUILTIN_VTERNLOGD512_MASKZ,
29223 IX86_BUILTIN_VTERNLOGQ512_MASK,
29224 IX86_BUILTIN_VTERNLOGQ512_MASKZ,
29226 /* Mask arithmetic operations */
29227 IX86_BUILTIN_KAND16,
29228 IX86_BUILTIN_KANDN16,
29229 IX86_BUILTIN_KNOT16,
29230 IX86_BUILTIN_KOR16,
29231 IX86_BUILTIN_KORTESTC16,
29232 IX86_BUILTIN_KORTESTZ16,
29233 IX86_BUILTIN_KUNPCKBW,
29234 IX86_BUILTIN_KXNOR16,
29235 IX86_BUILTIN_KXOR16,
29236 IX86_BUILTIN_KMOV16,
29238 /* AVX512VL. */
29239 IX86_BUILTIN_PMOVUSQD256_MEM,
29240 IX86_BUILTIN_PMOVUSQD128_MEM,
29241 IX86_BUILTIN_PMOVSQD256_MEM,
29242 IX86_BUILTIN_PMOVSQD128_MEM,
29243 IX86_BUILTIN_PMOVQD256_MEM,
29244 IX86_BUILTIN_PMOVQD128_MEM,
29245 IX86_BUILTIN_PMOVUSQW256_MEM,
29246 IX86_BUILTIN_PMOVUSQW128_MEM,
29247 IX86_BUILTIN_PMOVSQW256_MEM,
29248 IX86_BUILTIN_PMOVSQW128_MEM,
29249 IX86_BUILTIN_PMOVQW256_MEM,
29250 IX86_BUILTIN_PMOVQW128_MEM,
29251 IX86_BUILTIN_PMOVUSQB256_MEM,
29252 IX86_BUILTIN_PMOVUSQB128_MEM,
29253 IX86_BUILTIN_PMOVSQB256_MEM,
29254 IX86_BUILTIN_PMOVSQB128_MEM,
29255 IX86_BUILTIN_PMOVQB256_MEM,
29256 IX86_BUILTIN_PMOVQB128_MEM,
29257 IX86_BUILTIN_PMOVUSDW256_MEM,
29258 IX86_BUILTIN_PMOVUSDW128_MEM,
29259 IX86_BUILTIN_PMOVSDW256_MEM,
29260 IX86_BUILTIN_PMOVSDW128_MEM,
29261 IX86_BUILTIN_PMOVDW256_MEM,
29262 IX86_BUILTIN_PMOVDW128_MEM,
29263 IX86_BUILTIN_PMOVUSDB256_MEM,
29264 IX86_BUILTIN_PMOVUSDB128_MEM,
29265 IX86_BUILTIN_PMOVSDB256_MEM,
29266 IX86_BUILTIN_PMOVSDB128_MEM,
29267 IX86_BUILTIN_PMOVDB256_MEM,
29268 IX86_BUILTIN_PMOVDB128_MEM,
29269 IX86_BUILTIN_MOVDQA64LOAD256_MASK,
29270 IX86_BUILTIN_MOVDQA64LOAD128_MASK,
29271 IX86_BUILTIN_MOVDQA32LOAD256_MASK,
29272 IX86_BUILTIN_MOVDQA32LOAD128_MASK,
29273 IX86_BUILTIN_MOVDQA64STORE256_MASK,
29274 IX86_BUILTIN_MOVDQA64STORE128_MASK,
29275 IX86_BUILTIN_MOVDQA32STORE256_MASK,
29276 IX86_BUILTIN_MOVDQA32STORE128_MASK,
29277 IX86_BUILTIN_LOADAPD256_MASK,
29278 IX86_BUILTIN_LOADAPD128_MASK,
29279 IX86_BUILTIN_LOADAPS256_MASK,
29280 IX86_BUILTIN_LOADAPS128_MASK,
29281 IX86_BUILTIN_STOREAPD256_MASK,
29282 IX86_BUILTIN_STOREAPD128_MASK,
29283 IX86_BUILTIN_STOREAPS256_MASK,
29284 IX86_BUILTIN_STOREAPS128_MASK,
29285 IX86_BUILTIN_LOADUPD256_MASK,
29286 IX86_BUILTIN_LOADUPD128_MASK,
29287 IX86_BUILTIN_LOADUPS256_MASK,
29288 IX86_BUILTIN_LOADUPS128_MASK,
29289 IX86_BUILTIN_STOREUPD256_MASK,
29290 IX86_BUILTIN_STOREUPD128_MASK,
29291 IX86_BUILTIN_STOREUPS256_MASK,
29292 IX86_BUILTIN_STOREUPS128_MASK,
29293 IX86_BUILTIN_LOADDQUDI256_MASK,
29294 IX86_BUILTIN_LOADDQUDI128_MASK,
29295 IX86_BUILTIN_LOADDQUSI256_MASK,
29296 IX86_BUILTIN_LOADDQUSI128_MASK,
29297 IX86_BUILTIN_LOADDQUHI256_MASK,
29298 IX86_BUILTIN_LOADDQUHI128_MASK,
29299 IX86_BUILTIN_LOADDQUQI256_MASK,
29300 IX86_BUILTIN_LOADDQUQI128_MASK,
29301 IX86_BUILTIN_STOREDQUDI256_MASK,
29302 IX86_BUILTIN_STOREDQUDI128_MASK,
29303 IX86_BUILTIN_STOREDQUSI256_MASK,
29304 IX86_BUILTIN_STOREDQUSI128_MASK,
29305 IX86_BUILTIN_STOREDQUHI256_MASK,
29306 IX86_BUILTIN_STOREDQUHI128_MASK,
29307 IX86_BUILTIN_STOREDQUQI256_MASK,
29308 IX86_BUILTIN_STOREDQUQI128_MASK,
29309 IX86_BUILTIN_COMPRESSPDSTORE256,
29310 IX86_BUILTIN_COMPRESSPDSTORE128,
29311 IX86_BUILTIN_COMPRESSPSSTORE256,
29312 IX86_BUILTIN_COMPRESSPSSTORE128,
29313 IX86_BUILTIN_PCOMPRESSQSTORE256,
29314 IX86_BUILTIN_PCOMPRESSQSTORE128,
29315 IX86_BUILTIN_PCOMPRESSDSTORE256,
29316 IX86_BUILTIN_PCOMPRESSDSTORE128,
29317 IX86_BUILTIN_EXPANDPDLOAD256,
29318 IX86_BUILTIN_EXPANDPDLOAD128,
29319 IX86_BUILTIN_EXPANDPSLOAD256,
29320 IX86_BUILTIN_EXPANDPSLOAD128,
29321 IX86_BUILTIN_PEXPANDQLOAD256,
29322 IX86_BUILTIN_PEXPANDQLOAD128,
29323 IX86_BUILTIN_PEXPANDDLOAD256,
29324 IX86_BUILTIN_PEXPANDDLOAD128,
29325 IX86_BUILTIN_EXPANDPDLOAD256Z,
29326 IX86_BUILTIN_EXPANDPDLOAD128Z,
29327 IX86_BUILTIN_EXPANDPSLOAD256Z,
29328 IX86_BUILTIN_EXPANDPSLOAD128Z,
29329 IX86_BUILTIN_PEXPANDQLOAD256Z,
29330 IX86_BUILTIN_PEXPANDQLOAD128Z,
29331 IX86_BUILTIN_PEXPANDDLOAD256Z,
29332 IX86_BUILTIN_PEXPANDDLOAD128Z,
29333 IX86_BUILTIN_PALIGNR256_MASK,
29334 IX86_BUILTIN_PALIGNR128_MASK,
29335 IX86_BUILTIN_MOVDQA64_256_MASK,
29336 IX86_BUILTIN_MOVDQA64_128_MASK,
29337 IX86_BUILTIN_MOVDQA32_256_MASK,
29338 IX86_BUILTIN_MOVDQA32_128_MASK,
29339 IX86_BUILTIN_MOVAPD256_MASK,
29340 IX86_BUILTIN_MOVAPD128_MASK,
29341 IX86_BUILTIN_MOVAPS256_MASK,
29342 IX86_BUILTIN_MOVAPS128_MASK,
29343 IX86_BUILTIN_MOVDQUHI256_MASK,
29344 IX86_BUILTIN_MOVDQUHI128_MASK,
29345 IX86_BUILTIN_MOVDQUQI256_MASK,
29346 IX86_BUILTIN_MOVDQUQI128_MASK,
29347 IX86_BUILTIN_MINPS128_MASK,
29348 IX86_BUILTIN_MAXPS128_MASK,
29349 IX86_BUILTIN_MINPD128_MASK,
29350 IX86_BUILTIN_MAXPD128_MASK,
29351 IX86_BUILTIN_MAXPD256_MASK,
29352 IX86_BUILTIN_MAXPS256_MASK,
29353 IX86_BUILTIN_MINPD256_MASK,
29354 IX86_BUILTIN_MINPS256_MASK,
29355 IX86_BUILTIN_MULPS128_MASK,
29356 IX86_BUILTIN_DIVPS128_MASK,
29357 IX86_BUILTIN_MULPD128_MASK,
29358 IX86_BUILTIN_DIVPD128_MASK,
29359 IX86_BUILTIN_DIVPD256_MASK,
29360 IX86_BUILTIN_DIVPS256_MASK,
29361 IX86_BUILTIN_MULPD256_MASK,
29362 IX86_BUILTIN_MULPS256_MASK,
29363 IX86_BUILTIN_ADDPD128_MASK,
29364 IX86_BUILTIN_ADDPD256_MASK,
29365 IX86_BUILTIN_ADDPS128_MASK,
29366 IX86_BUILTIN_ADDPS256_MASK,
29367 IX86_BUILTIN_SUBPD128_MASK,
29368 IX86_BUILTIN_SUBPD256_MASK,
29369 IX86_BUILTIN_SUBPS128_MASK,
29370 IX86_BUILTIN_SUBPS256_MASK,
29371 IX86_BUILTIN_XORPD256_MASK,
29372 IX86_BUILTIN_XORPD128_MASK,
29373 IX86_BUILTIN_XORPS256_MASK,
29374 IX86_BUILTIN_XORPS128_MASK,
29375 IX86_BUILTIN_ORPD256_MASK,
29376 IX86_BUILTIN_ORPD128_MASK,
29377 IX86_BUILTIN_ORPS256_MASK,
29378 IX86_BUILTIN_ORPS128_MASK,
29379 IX86_BUILTIN_BROADCASTF32x2_256,
29380 IX86_BUILTIN_BROADCASTI32x2_256,
29381 IX86_BUILTIN_BROADCASTI32x2_128,
29382 IX86_BUILTIN_BROADCASTF64X2_256,
29383 IX86_BUILTIN_BROADCASTI64X2_256,
29384 IX86_BUILTIN_BROADCASTF32X4_256,
29385 IX86_BUILTIN_BROADCASTI32X4_256,
29386 IX86_BUILTIN_EXTRACTF32X4_256,
29387 IX86_BUILTIN_EXTRACTI32X4_256,
29388 IX86_BUILTIN_DBPSADBW256,
29389 IX86_BUILTIN_DBPSADBW128,
29390 IX86_BUILTIN_CVTTPD2QQ256,
29391 IX86_BUILTIN_CVTTPD2QQ128,
29392 IX86_BUILTIN_CVTTPD2UQQ256,
29393 IX86_BUILTIN_CVTTPD2UQQ128,
29394 IX86_BUILTIN_CVTPD2QQ256,
29395 IX86_BUILTIN_CVTPD2QQ128,
29396 IX86_BUILTIN_CVTPD2UQQ256,
29397 IX86_BUILTIN_CVTPD2UQQ128,
29398 IX86_BUILTIN_CVTPD2UDQ256_MASK,
29399 IX86_BUILTIN_CVTPD2UDQ128_MASK,
29400 IX86_BUILTIN_CVTTPS2QQ256,
29401 IX86_BUILTIN_CVTTPS2QQ128,
29402 IX86_BUILTIN_CVTTPS2UQQ256,
29403 IX86_BUILTIN_CVTTPS2UQQ128,
29404 IX86_BUILTIN_CVTTPS2DQ256_MASK,
29405 IX86_BUILTIN_CVTTPS2DQ128_MASK,
29406 IX86_BUILTIN_CVTTPS2UDQ256,
29407 IX86_BUILTIN_CVTTPS2UDQ128,
29408 IX86_BUILTIN_CVTTPD2DQ256_MASK,
29409 IX86_BUILTIN_CVTTPD2DQ128_MASK,
29410 IX86_BUILTIN_CVTTPD2UDQ256_MASK,
29411 IX86_BUILTIN_CVTTPD2UDQ128_MASK,
29412 IX86_BUILTIN_CVTPD2DQ256_MASK,
29413 IX86_BUILTIN_CVTPD2DQ128_MASK,
29414 IX86_BUILTIN_CVTDQ2PD256_MASK,
29415 IX86_BUILTIN_CVTDQ2PD128_MASK,
29416 IX86_BUILTIN_CVTUDQ2PD256_MASK,
29417 IX86_BUILTIN_CVTUDQ2PD128_MASK,
29418 IX86_BUILTIN_CVTDQ2PS256_MASK,
29419 IX86_BUILTIN_CVTDQ2PS128_MASK,
29420 IX86_BUILTIN_CVTUDQ2PS256_MASK,
29421 IX86_BUILTIN_CVTUDQ2PS128_MASK,
29422 IX86_BUILTIN_CVTPS2PD256_MASK,
29423 IX86_BUILTIN_CVTPS2PD128_MASK,
29424 IX86_BUILTIN_PBROADCASTB256_MASK,
29425 IX86_BUILTIN_PBROADCASTB256_GPR_MASK,
29426 IX86_BUILTIN_PBROADCASTB128_MASK,
29427 IX86_BUILTIN_PBROADCASTB128_GPR_MASK,
29428 IX86_BUILTIN_PBROADCASTW256_MASK,
29429 IX86_BUILTIN_PBROADCASTW256_GPR_MASK,
29430 IX86_BUILTIN_PBROADCASTW128_MASK,
29431 IX86_BUILTIN_PBROADCASTW128_GPR_MASK,
29432 IX86_BUILTIN_PBROADCASTD256_MASK,
29433 IX86_BUILTIN_PBROADCASTD256_GPR_MASK,
29434 IX86_BUILTIN_PBROADCASTD128_MASK,
29435 IX86_BUILTIN_PBROADCASTD128_GPR_MASK,
29436 IX86_BUILTIN_PBROADCASTQ256_MASK,
29437 IX86_BUILTIN_PBROADCASTQ256_GPR_MASK,
29438 IX86_BUILTIN_PBROADCASTQ128_MASK,
29439 IX86_BUILTIN_PBROADCASTQ128_GPR_MASK,
29440 IX86_BUILTIN_BROADCASTSS256,
29441 IX86_BUILTIN_BROADCASTSS128,
29442 IX86_BUILTIN_BROADCASTSD256,
29443 IX86_BUILTIN_EXTRACTF64X2_256,
29444 IX86_BUILTIN_EXTRACTI64X2_256,
29445 IX86_BUILTIN_INSERTF32X4_256,
29446 IX86_BUILTIN_INSERTI32X4_256,
29447 IX86_BUILTIN_PMOVSXBW256_MASK,
29448 IX86_BUILTIN_PMOVSXBW128_MASK,
29449 IX86_BUILTIN_PMOVSXBD256_MASK,
29450 IX86_BUILTIN_PMOVSXBD128_MASK,
29451 IX86_BUILTIN_PMOVSXBQ256_MASK,
29452 IX86_BUILTIN_PMOVSXBQ128_MASK,
29453 IX86_BUILTIN_PMOVSXWD256_MASK,
29454 IX86_BUILTIN_PMOVSXWD128_MASK,
29455 IX86_BUILTIN_PMOVSXWQ256_MASK,
29456 IX86_BUILTIN_PMOVSXWQ128_MASK,
29457 IX86_BUILTIN_PMOVSXDQ256_MASK,
29458 IX86_BUILTIN_PMOVSXDQ128_MASK,
29459 IX86_BUILTIN_PMOVZXBW256_MASK,
29460 IX86_BUILTIN_PMOVZXBW128_MASK,
29461 IX86_BUILTIN_PMOVZXBD256_MASK,
29462 IX86_BUILTIN_PMOVZXBD128_MASK,
29463 IX86_BUILTIN_PMOVZXBQ256_MASK,
29464 IX86_BUILTIN_PMOVZXBQ128_MASK,
29465 IX86_BUILTIN_PMOVZXWD256_MASK,
29466 IX86_BUILTIN_PMOVZXWD128_MASK,
29467 IX86_BUILTIN_PMOVZXWQ256_MASK,
29468 IX86_BUILTIN_PMOVZXWQ128_MASK,
29469 IX86_BUILTIN_PMOVZXDQ256_MASK,
29470 IX86_BUILTIN_PMOVZXDQ128_MASK,
29471 IX86_BUILTIN_REDUCEPD256_MASK,
29472 IX86_BUILTIN_REDUCEPD128_MASK,
29473 IX86_BUILTIN_REDUCEPS256_MASK,
29474 IX86_BUILTIN_REDUCEPS128_MASK,
29475 IX86_BUILTIN_REDUCESD_MASK,
29476 IX86_BUILTIN_REDUCESS_MASK,
29477 IX86_BUILTIN_VPERMVARHI256_MASK,
29478 IX86_BUILTIN_VPERMVARHI128_MASK,
29479 IX86_BUILTIN_VPERMT2VARHI256,
29480 IX86_BUILTIN_VPERMT2VARHI256_MASKZ,
29481 IX86_BUILTIN_VPERMT2VARHI128,
29482 IX86_BUILTIN_VPERMT2VARHI128_MASKZ,
29483 IX86_BUILTIN_VPERMI2VARHI256,
29484 IX86_BUILTIN_VPERMI2VARHI128,
29485 IX86_BUILTIN_RCP14PD256,
29486 IX86_BUILTIN_RCP14PD128,
29487 IX86_BUILTIN_RCP14PS256,
29488 IX86_BUILTIN_RCP14PS128,
29489 IX86_BUILTIN_RSQRT14PD256_MASK,
29490 IX86_BUILTIN_RSQRT14PD128_MASK,
29491 IX86_BUILTIN_RSQRT14PS256_MASK,
29492 IX86_BUILTIN_RSQRT14PS128_MASK,
29493 IX86_BUILTIN_SQRTPD256_MASK,
29494 IX86_BUILTIN_SQRTPD128_MASK,
29495 IX86_BUILTIN_SQRTPS256_MASK,
29496 IX86_BUILTIN_SQRTPS128_MASK,
29497 IX86_BUILTIN_PADDB128_MASK,
29498 IX86_BUILTIN_PADDW128_MASK,
29499 IX86_BUILTIN_PADDD128_MASK,
29500 IX86_BUILTIN_PADDQ128_MASK,
29501 IX86_BUILTIN_PSUBB128_MASK,
29502 IX86_BUILTIN_PSUBW128_MASK,
29503 IX86_BUILTIN_PSUBD128_MASK,
29504 IX86_BUILTIN_PSUBQ128_MASK,
29505 IX86_BUILTIN_PADDSB128_MASK,
29506 IX86_BUILTIN_PADDSW128_MASK,
29507 IX86_BUILTIN_PSUBSB128_MASK,
29508 IX86_BUILTIN_PSUBSW128_MASK,
29509 IX86_BUILTIN_PADDUSB128_MASK,
29510 IX86_BUILTIN_PADDUSW128_MASK,
29511 IX86_BUILTIN_PSUBUSB128_MASK,
29512 IX86_BUILTIN_PSUBUSW128_MASK,
29513 IX86_BUILTIN_PADDB256_MASK,
29514 IX86_BUILTIN_PADDW256_MASK,
29515 IX86_BUILTIN_PADDD256_MASK,
29516 IX86_BUILTIN_PADDQ256_MASK,
29517 IX86_BUILTIN_PADDSB256_MASK,
29518 IX86_BUILTIN_PADDSW256_MASK,
29519 IX86_BUILTIN_PADDUSB256_MASK,
29520 IX86_BUILTIN_PADDUSW256_MASK,
29521 IX86_BUILTIN_PSUBB256_MASK,
29522 IX86_BUILTIN_PSUBW256_MASK,
29523 IX86_BUILTIN_PSUBD256_MASK,
29524 IX86_BUILTIN_PSUBQ256_MASK,
29525 IX86_BUILTIN_PSUBSB256_MASK,
29526 IX86_BUILTIN_PSUBSW256_MASK,
29527 IX86_BUILTIN_PSUBUSB256_MASK,
29528 IX86_BUILTIN_PSUBUSW256_MASK,
29529 IX86_BUILTIN_SHUF_F64x2_256,
29530 IX86_BUILTIN_SHUF_I64x2_256,
29531 IX86_BUILTIN_SHUF_I32x4_256,
29532 IX86_BUILTIN_SHUF_F32x4_256,
29533 IX86_BUILTIN_PMOVWB128,
29534 IX86_BUILTIN_PMOVWB256,
29535 IX86_BUILTIN_PMOVSWB128,
29536 IX86_BUILTIN_PMOVSWB256,
29537 IX86_BUILTIN_PMOVUSWB128,
29538 IX86_BUILTIN_PMOVUSWB256,
29539 IX86_BUILTIN_PMOVDB128,
29540 IX86_BUILTIN_PMOVDB256,
29541 IX86_BUILTIN_PMOVSDB128,
29542 IX86_BUILTIN_PMOVSDB256,
29543 IX86_BUILTIN_PMOVUSDB128,
29544 IX86_BUILTIN_PMOVUSDB256,
29545 IX86_BUILTIN_PMOVDW128,
29546 IX86_BUILTIN_PMOVDW256,
29547 IX86_BUILTIN_PMOVSDW128,
29548 IX86_BUILTIN_PMOVSDW256,
29549 IX86_BUILTIN_PMOVUSDW128,
29550 IX86_BUILTIN_PMOVUSDW256,
29551 IX86_BUILTIN_PMOVQB128,
29552 IX86_BUILTIN_PMOVQB256,
29553 IX86_BUILTIN_PMOVSQB128,
29554 IX86_BUILTIN_PMOVSQB256,
29555 IX86_BUILTIN_PMOVUSQB128,
29556 IX86_BUILTIN_PMOVUSQB256,
29557 IX86_BUILTIN_PMOVQW128,
29558 IX86_BUILTIN_PMOVQW256,
29559 IX86_BUILTIN_PMOVSQW128,
29560 IX86_BUILTIN_PMOVSQW256,
29561 IX86_BUILTIN_PMOVUSQW128,
29562 IX86_BUILTIN_PMOVUSQW256,
29563 IX86_BUILTIN_PMOVQD128,
29564 IX86_BUILTIN_PMOVQD256,
29565 IX86_BUILTIN_PMOVSQD128,
29566 IX86_BUILTIN_PMOVSQD256,
29567 IX86_BUILTIN_PMOVUSQD128,
29568 IX86_BUILTIN_PMOVUSQD256,
29569 IX86_BUILTIN_RANGEPD256,
29570 IX86_BUILTIN_RANGEPD128,
29571 IX86_BUILTIN_RANGEPS256,
29572 IX86_BUILTIN_RANGEPS128,
29573 IX86_BUILTIN_GETEXPPS256,
29574 IX86_BUILTIN_GETEXPPD256,
29575 IX86_BUILTIN_GETEXPPS128,
29576 IX86_BUILTIN_GETEXPPD128,
29577 IX86_BUILTIN_FIXUPIMMPD256_MASK,
29578 IX86_BUILTIN_FIXUPIMMPD256_MASKZ,
29579 IX86_BUILTIN_FIXUPIMMPS256_MASK,
29580 IX86_BUILTIN_FIXUPIMMPS256_MASKZ,
29581 IX86_BUILTIN_FIXUPIMMPD128_MASK,
29582 IX86_BUILTIN_FIXUPIMMPD128_MASKZ,
29583 IX86_BUILTIN_FIXUPIMMPS128_MASK,
29584 IX86_BUILTIN_FIXUPIMMPS128_MASKZ,
29585 IX86_BUILTIN_PABSQ256,
29586 IX86_BUILTIN_PABSQ128,
29587 IX86_BUILTIN_PABSD256_MASK,
29588 IX86_BUILTIN_PABSD128_MASK,
29589 IX86_BUILTIN_PMULHRSW256_MASK,
29590 IX86_BUILTIN_PMULHRSW128_MASK,
29591 IX86_BUILTIN_PMULHUW128_MASK,
29592 IX86_BUILTIN_PMULHUW256_MASK,
29593 IX86_BUILTIN_PMULHW256_MASK,
29594 IX86_BUILTIN_PMULHW128_MASK,
29595 IX86_BUILTIN_PMULLW256_MASK,
29596 IX86_BUILTIN_PMULLW128_MASK,
29597 IX86_BUILTIN_PMULLQ256,
29598 IX86_BUILTIN_PMULLQ128,
29599 IX86_BUILTIN_ANDPD256_MASK,
29600 IX86_BUILTIN_ANDPD128_MASK,
29601 IX86_BUILTIN_ANDPS256_MASK,
29602 IX86_BUILTIN_ANDPS128_MASK,
29603 IX86_BUILTIN_ANDNPD256_MASK,
29604 IX86_BUILTIN_ANDNPD128_MASK,
29605 IX86_BUILTIN_ANDNPS256_MASK,
29606 IX86_BUILTIN_ANDNPS128_MASK,
29607 IX86_BUILTIN_PSLLWI128_MASK,
29608 IX86_BUILTIN_PSLLDI128_MASK,
29609 IX86_BUILTIN_PSLLQI128_MASK,
29610 IX86_BUILTIN_PSLLW128_MASK,
29611 IX86_BUILTIN_PSLLD128_MASK,
29612 IX86_BUILTIN_PSLLQ128_MASK,
29613 IX86_BUILTIN_PSLLWI256_MASK ,
29614 IX86_BUILTIN_PSLLW256_MASK,
29615 IX86_BUILTIN_PSLLDI256_MASK,
29616 IX86_BUILTIN_PSLLD256_MASK,
29617 IX86_BUILTIN_PSLLQI256_MASK,
29618 IX86_BUILTIN_PSLLQ256_MASK,
29619 IX86_BUILTIN_PSRADI128_MASK,
29620 IX86_BUILTIN_PSRAD128_MASK,
29621 IX86_BUILTIN_PSRADI256_MASK,
29622 IX86_BUILTIN_PSRAD256_MASK,
29623 IX86_BUILTIN_PSRAQI128_MASK,
29624 IX86_BUILTIN_PSRAQ128_MASK,
29625 IX86_BUILTIN_PSRAQI256_MASK,
29626 IX86_BUILTIN_PSRAQ256_MASK,
29627 IX86_BUILTIN_PANDD256,
29628 IX86_BUILTIN_PANDD128,
29629 IX86_BUILTIN_PSRLDI128_MASK,
29630 IX86_BUILTIN_PSRLD128_MASK,
29631 IX86_BUILTIN_PSRLDI256_MASK,
29632 IX86_BUILTIN_PSRLD256_MASK,
29633 IX86_BUILTIN_PSRLQI128_MASK,
29634 IX86_BUILTIN_PSRLQ128_MASK,
29635 IX86_BUILTIN_PSRLQI256_MASK,
29636 IX86_BUILTIN_PSRLQ256_MASK,
29637 IX86_BUILTIN_PANDQ256,
29638 IX86_BUILTIN_PANDQ128,
29639 IX86_BUILTIN_PANDND256,
29640 IX86_BUILTIN_PANDND128,
29641 IX86_BUILTIN_PANDNQ256,
29642 IX86_BUILTIN_PANDNQ128,
29643 IX86_BUILTIN_PORD256,
29644 IX86_BUILTIN_PORD128,
29645 IX86_BUILTIN_PORQ256,
29646 IX86_BUILTIN_PORQ128,
29647 IX86_BUILTIN_PXORD256,
29648 IX86_BUILTIN_PXORD128,
29649 IX86_BUILTIN_PXORQ256,
29650 IX86_BUILTIN_PXORQ128,
29651 IX86_BUILTIN_PACKSSWB256_MASK,
29652 IX86_BUILTIN_PACKSSWB128_MASK,
29653 IX86_BUILTIN_PACKUSWB256_MASK,
29654 IX86_BUILTIN_PACKUSWB128_MASK,
29655 IX86_BUILTIN_RNDSCALEPS256,
29656 IX86_BUILTIN_RNDSCALEPD256,
29657 IX86_BUILTIN_RNDSCALEPS128,
29658 IX86_BUILTIN_RNDSCALEPD128,
29659 IX86_BUILTIN_VTERNLOGQ256_MASK,
29660 IX86_BUILTIN_VTERNLOGQ256_MASKZ,
29661 IX86_BUILTIN_VTERNLOGD256_MASK,
29662 IX86_BUILTIN_VTERNLOGD256_MASKZ,
29663 IX86_BUILTIN_VTERNLOGQ128_MASK,
29664 IX86_BUILTIN_VTERNLOGQ128_MASKZ,
29665 IX86_BUILTIN_VTERNLOGD128_MASK,
29666 IX86_BUILTIN_VTERNLOGD128_MASKZ,
29667 IX86_BUILTIN_SCALEFPD256,
29668 IX86_BUILTIN_SCALEFPS256,
29669 IX86_BUILTIN_SCALEFPD128,
29670 IX86_BUILTIN_SCALEFPS128,
29671 IX86_BUILTIN_VFMADDPD256_MASK,
29672 IX86_BUILTIN_VFMADDPD256_MASK3,
29673 IX86_BUILTIN_VFMADDPD256_MASKZ,
29674 IX86_BUILTIN_VFMADDPD128_MASK,
29675 IX86_BUILTIN_VFMADDPD128_MASK3,
29676 IX86_BUILTIN_VFMADDPD128_MASKZ,
29677 IX86_BUILTIN_VFMADDPS256_MASK,
29678 IX86_BUILTIN_VFMADDPS256_MASK3,
29679 IX86_BUILTIN_VFMADDPS256_MASKZ,
29680 IX86_BUILTIN_VFMADDPS128_MASK,
29681 IX86_BUILTIN_VFMADDPS128_MASK3,
29682 IX86_BUILTIN_VFMADDPS128_MASKZ,
29683 IX86_BUILTIN_VFMSUBPD256_MASK3,
29684 IX86_BUILTIN_VFMSUBPD128_MASK3,
29685 IX86_BUILTIN_VFMSUBPS256_MASK3,
29686 IX86_BUILTIN_VFMSUBPS128_MASK3,
29687 IX86_BUILTIN_VFNMADDPD256_MASK,
29688 IX86_BUILTIN_VFNMADDPD128_MASK,
29689 IX86_BUILTIN_VFNMADDPS256_MASK,
29690 IX86_BUILTIN_VFNMADDPS128_MASK,
29691 IX86_BUILTIN_VFNMSUBPD256_MASK,
29692 IX86_BUILTIN_VFNMSUBPD256_MASK3,
29693 IX86_BUILTIN_VFNMSUBPD128_MASK,
29694 IX86_BUILTIN_VFNMSUBPD128_MASK3,
29695 IX86_BUILTIN_VFNMSUBPS256_MASK,
29696 IX86_BUILTIN_VFNMSUBPS256_MASK3,
29697 IX86_BUILTIN_VFNMSUBPS128_MASK,
29698 IX86_BUILTIN_VFNMSUBPS128_MASK3,
29699 IX86_BUILTIN_VFMADDSUBPD256_MASK,
29700 IX86_BUILTIN_VFMADDSUBPD256_MASK3,
29701 IX86_BUILTIN_VFMADDSUBPD256_MASKZ,
29702 IX86_BUILTIN_VFMADDSUBPD128_MASK,
29703 IX86_BUILTIN_VFMADDSUBPD128_MASK3,
29704 IX86_BUILTIN_VFMADDSUBPD128_MASKZ,
29705 IX86_BUILTIN_VFMADDSUBPS256_MASK,
29706 IX86_BUILTIN_VFMADDSUBPS256_MASK3,
29707 IX86_BUILTIN_VFMADDSUBPS256_MASKZ,
29708 IX86_BUILTIN_VFMADDSUBPS128_MASK,
29709 IX86_BUILTIN_VFMADDSUBPS128_MASK3,
29710 IX86_BUILTIN_VFMADDSUBPS128_MASKZ,
29711 IX86_BUILTIN_VFMSUBADDPD256_MASK3,
29712 IX86_BUILTIN_VFMSUBADDPD128_MASK3,
29713 IX86_BUILTIN_VFMSUBADDPS256_MASK3,
29714 IX86_BUILTIN_VFMSUBADDPS128_MASK3,
29715 IX86_BUILTIN_INSERTF64X2_256,
29716 IX86_BUILTIN_INSERTI64X2_256,
29717 IX86_BUILTIN_PSRAVV16HI,
29718 IX86_BUILTIN_PSRAVV8HI,
29719 IX86_BUILTIN_PMADDUBSW256_MASK,
29720 IX86_BUILTIN_PMADDUBSW128_MASK,
29721 IX86_BUILTIN_PMADDWD256_MASK,
29722 IX86_BUILTIN_PMADDWD128_MASK,
29723 IX86_BUILTIN_PSRLVV16HI,
29724 IX86_BUILTIN_PSRLVV8HI,
29725 IX86_BUILTIN_CVTPS2DQ256_MASK,
29726 IX86_BUILTIN_CVTPS2DQ128_MASK,
29727 IX86_BUILTIN_CVTPS2UDQ256,
29728 IX86_BUILTIN_CVTPS2UDQ128,
29729 IX86_BUILTIN_CVTPS2QQ256,
29730 IX86_BUILTIN_CVTPS2QQ128,
29731 IX86_BUILTIN_CVTPS2UQQ256,
29732 IX86_BUILTIN_CVTPS2UQQ128,
29733 IX86_BUILTIN_GETMANTPS256,
29734 IX86_BUILTIN_GETMANTPS128,
29735 IX86_BUILTIN_GETMANTPD256,
29736 IX86_BUILTIN_GETMANTPD128,
29737 IX86_BUILTIN_MOVDDUP256_MASK,
29738 IX86_BUILTIN_MOVDDUP128_MASK,
29739 IX86_BUILTIN_MOVSHDUP256_MASK,
29740 IX86_BUILTIN_MOVSHDUP128_MASK,
29741 IX86_BUILTIN_MOVSLDUP256_MASK,
29742 IX86_BUILTIN_MOVSLDUP128_MASK,
29743 IX86_BUILTIN_CVTQQ2PS256,
29744 IX86_BUILTIN_CVTQQ2PS128,
29745 IX86_BUILTIN_CVTUQQ2PS256,
29746 IX86_BUILTIN_CVTUQQ2PS128,
29747 IX86_BUILTIN_CVTQQ2PD256,
29748 IX86_BUILTIN_CVTQQ2PD128,
29749 IX86_BUILTIN_CVTUQQ2PD256,
29750 IX86_BUILTIN_CVTUQQ2PD128,
29751 IX86_BUILTIN_VPERMT2VARQ256,
29752 IX86_BUILTIN_VPERMT2VARQ256_MASKZ,
29753 IX86_BUILTIN_VPERMT2VARD256,
29754 IX86_BUILTIN_VPERMT2VARD256_MASKZ,
29755 IX86_BUILTIN_VPERMI2VARQ256,
29756 IX86_BUILTIN_VPERMI2VARD256,
29757 IX86_BUILTIN_VPERMT2VARPD256,
29758 IX86_BUILTIN_VPERMT2VARPD256_MASKZ,
29759 IX86_BUILTIN_VPERMT2VARPS256,
29760 IX86_BUILTIN_VPERMT2VARPS256_MASKZ,
29761 IX86_BUILTIN_VPERMI2VARPD256,
29762 IX86_BUILTIN_VPERMI2VARPS256,
29763 IX86_BUILTIN_VPERMT2VARQ128,
29764 IX86_BUILTIN_VPERMT2VARQ128_MASKZ,
29765 IX86_BUILTIN_VPERMT2VARD128,
29766 IX86_BUILTIN_VPERMT2VARD128_MASKZ,
29767 IX86_BUILTIN_VPERMI2VARQ128,
29768 IX86_BUILTIN_VPERMI2VARD128,
29769 IX86_BUILTIN_VPERMT2VARPD128,
29770 IX86_BUILTIN_VPERMT2VARPD128_MASKZ,
29771 IX86_BUILTIN_VPERMT2VARPS128,
29772 IX86_BUILTIN_VPERMT2VARPS128_MASKZ,
29773 IX86_BUILTIN_VPERMI2VARPD128,
29774 IX86_BUILTIN_VPERMI2VARPS128,
29775 IX86_BUILTIN_PSHUFB256_MASK,
29776 IX86_BUILTIN_PSHUFB128_MASK,
29777 IX86_BUILTIN_PSHUFHW256_MASK,
29778 IX86_BUILTIN_PSHUFHW128_MASK,
29779 IX86_BUILTIN_PSHUFLW256_MASK,
29780 IX86_BUILTIN_PSHUFLW128_MASK,
29781 IX86_BUILTIN_PSHUFD256_MASK,
29782 IX86_BUILTIN_PSHUFD128_MASK,
29783 IX86_BUILTIN_SHUFPD256_MASK,
29784 IX86_BUILTIN_SHUFPD128_MASK,
29785 IX86_BUILTIN_SHUFPS256_MASK,
29786 IX86_BUILTIN_SHUFPS128_MASK,
29787 IX86_BUILTIN_PROLVQ256,
29788 IX86_BUILTIN_PROLVQ128,
29789 IX86_BUILTIN_PROLQ256,
29790 IX86_BUILTIN_PROLQ128,
29791 IX86_BUILTIN_PRORVQ256,
29792 IX86_BUILTIN_PRORVQ128,
29793 IX86_BUILTIN_PRORQ256,
29794 IX86_BUILTIN_PRORQ128,
29795 IX86_BUILTIN_PSRAVQ128,
29796 IX86_BUILTIN_PSRAVQ256,
29797 IX86_BUILTIN_PSLLVV4DI_MASK,
29798 IX86_BUILTIN_PSLLVV2DI_MASK,
29799 IX86_BUILTIN_PSLLVV8SI_MASK,
29800 IX86_BUILTIN_PSLLVV4SI_MASK,
29801 IX86_BUILTIN_PSRAVV8SI_MASK,
29802 IX86_BUILTIN_PSRAVV4SI_MASK,
29803 IX86_BUILTIN_PSRLVV4DI_MASK,
29804 IX86_BUILTIN_PSRLVV2DI_MASK,
29805 IX86_BUILTIN_PSRLVV8SI_MASK,
29806 IX86_BUILTIN_PSRLVV4SI_MASK,
29807 IX86_BUILTIN_PSRAWI256_MASK,
29808 IX86_BUILTIN_PSRAW256_MASK,
29809 IX86_BUILTIN_PSRAWI128_MASK,
29810 IX86_BUILTIN_PSRAW128_MASK,
29811 IX86_BUILTIN_PSRLWI256_MASK,
29812 IX86_BUILTIN_PSRLW256_MASK,
29813 IX86_BUILTIN_PSRLWI128_MASK,
29814 IX86_BUILTIN_PSRLW128_MASK,
29815 IX86_BUILTIN_PRORVD256,
29816 IX86_BUILTIN_PROLVD256,
29817 IX86_BUILTIN_PRORD256,
29818 IX86_BUILTIN_PROLD256,
29819 IX86_BUILTIN_PRORVD128,
29820 IX86_BUILTIN_PROLVD128,
29821 IX86_BUILTIN_PRORD128,
29822 IX86_BUILTIN_PROLD128,
29823 IX86_BUILTIN_FPCLASSPD256,
29824 IX86_BUILTIN_FPCLASSPD128,
29825 IX86_BUILTIN_FPCLASSSD,
29826 IX86_BUILTIN_FPCLASSPS256,
29827 IX86_BUILTIN_FPCLASSPS128,
29828 IX86_BUILTIN_FPCLASSSS,
29829 IX86_BUILTIN_CVTB2MASK128,
29830 IX86_BUILTIN_CVTB2MASK256,
29831 IX86_BUILTIN_CVTW2MASK128,
29832 IX86_BUILTIN_CVTW2MASK256,
29833 IX86_BUILTIN_CVTD2MASK128,
29834 IX86_BUILTIN_CVTD2MASK256,
29835 IX86_BUILTIN_CVTQ2MASK128,
29836 IX86_BUILTIN_CVTQ2MASK256,
29837 IX86_BUILTIN_CVTMASK2B128,
29838 IX86_BUILTIN_CVTMASK2B256,
29839 IX86_BUILTIN_CVTMASK2W128,
29840 IX86_BUILTIN_CVTMASK2W256,
29841 IX86_BUILTIN_CVTMASK2D128,
29842 IX86_BUILTIN_CVTMASK2D256,
29843 IX86_BUILTIN_CVTMASK2Q128,
29844 IX86_BUILTIN_CVTMASK2Q256,
29845 IX86_BUILTIN_PCMPEQB128_MASK,
29846 IX86_BUILTIN_PCMPEQB256_MASK,
29847 IX86_BUILTIN_PCMPEQW128_MASK,
29848 IX86_BUILTIN_PCMPEQW256_MASK,
29849 IX86_BUILTIN_PCMPEQD128_MASK,
29850 IX86_BUILTIN_PCMPEQD256_MASK,
29851 IX86_BUILTIN_PCMPEQQ128_MASK,
29852 IX86_BUILTIN_PCMPEQQ256_MASK,
29853 IX86_BUILTIN_PCMPGTB128_MASK,
29854 IX86_BUILTIN_PCMPGTB256_MASK,
29855 IX86_BUILTIN_PCMPGTW128_MASK,
29856 IX86_BUILTIN_PCMPGTW256_MASK,
29857 IX86_BUILTIN_PCMPGTD128_MASK,
29858 IX86_BUILTIN_PCMPGTD256_MASK,
29859 IX86_BUILTIN_PCMPGTQ128_MASK,
29860 IX86_BUILTIN_PCMPGTQ256_MASK,
29861 IX86_BUILTIN_PTESTMB128,
29862 IX86_BUILTIN_PTESTMB256,
29863 IX86_BUILTIN_PTESTMW128,
29864 IX86_BUILTIN_PTESTMW256,
29865 IX86_BUILTIN_PTESTMD128,
29866 IX86_BUILTIN_PTESTMD256,
29867 IX86_BUILTIN_PTESTMQ128,
29868 IX86_BUILTIN_PTESTMQ256,
29869 IX86_BUILTIN_PTESTNMB128,
29870 IX86_BUILTIN_PTESTNMB256,
29871 IX86_BUILTIN_PTESTNMW128,
29872 IX86_BUILTIN_PTESTNMW256,
29873 IX86_BUILTIN_PTESTNMD128,
29874 IX86_BUILTIN_PTESTNMD256,
29875 IX86_BUILTIN_PTESTNMQ128,
29876 IX86_BUILTIN_PTESTNMQ256,
29877 IX86_BUILTIN_PBROADCASTMB128,
29878 IX86_BUILTIN_PBROADCASTMB256,
29879 IX86_BUILTIN_PBROADCASTMW128,
29880 IX86_BUILTIN_PBROADCASTMW256,
29881 IX86_BUILTIN_COMPRESSPD256,
29882 IX86_BUILTIN_COMPRESSPD128,
29883 IX86_BUILTIN_COMPRESSPS256,
29884 IX86_BUILTIN_COMPRESSPS128,
29885 IX86_BUILTIN_PCOMPRESSQ256,
29886 IX86_BUILTIN_PCOMPRESSQ128,
29887 IX86_BUILTIN_PCOMPRESSD256,
29888 IX86_BUILTIN_PCOMPRESSD128,
29889 IX86_BUILTIN_EXPANDPD256,
29890 IX86_BUILTIN_EXPANDPD128,
29891 IX86_BUILTIN_EXPANDPS256,
29892 IX86_BUILTIN_EXPANDPS128,
29893 IX86_BUILTIN_PEXPANDQ256,
29894 IX86_BUILTIN_PEXPANDQ128,
29895 IX86_BUILTIN_PEXPANDD256,
29896 IX86_BUILTIN_PEXPANDD128,
29897 IX86_BUILTIN_EXPANDPD256Z,
29898 IX86_BUILTIN_EXPANDPD128Z,
29899 IX86_BUILTIN_EXPANDPS256Z,
29900 IX86_BUILTIN_EXPANDPS128Z,
29901 IX86_BUILTIN_PEXPANDQ256Z,
29902 IX86_BUILTIN_PEXPANDQ128Z,
29903 IX86_BUILTIN_PEXPANDD256Z,
29904 IX86_BUILTIN_PEXPANDD128Z,
29905 IX86_BUILTIN_PMAXSD256_MASK,
29906 IX86_BUILTIN_PMINSD256_MASK,
29907 IX86_BUILTIN_PMAXUD256_MASK,
29908 IX86_BUILTIN_PMINUD256_MASK,
29909 IX86_BUILTIN_PMAXSD128_MASK,
29910 IX86_BUILTIN_PMINSD128_MASK,
29911 IX86_BUILTIN_PMAXUD128_MASK,
29912 IX86_BUILTIN_PMINUD128_MASK,
29913 IX86_BUILTIN_PMAXSQ256_MASK,
29914 IX86_BUILTIN_PMINSQ256_MASK,
29915 IX86_BUILTIN_PMAXUQ256_MASK,
29916 IX86_BUILTIN_PMINUQ256_MASK,
29917 IX86_BUILTIN_PMAXSQ128_MASK,
29918 IX86_BUILTIN_PMINSQ128_MASK,
29919 IX86_BUILTIN_PMAXUQ128_MASK,
29920 IX86_BUILTIN_PMINUQ128_MASK,
29921 IX86_BUILTIN_PMINSB256_MASK,
29922 IX86_BUILTIN_PMINUB256_MASK,
29923 IX86_BUILTIN_PMAXSB256_MASK,
29924 IX86_BUILTIN_PMAXUB256_MASK,
29925 IX86_BUILTIN_PMINSB128_MASK,
29926 IX86_BUILTIN_PMINUB128_MASK,
29927 IX86_BUILTIN_PMAXSB128_MASK,
29928 IX86_BUILTIN_PMAXUB128_MASK,
29929 IX86_BUILTIN_PMINSW256_MASK,
29930 IX86_BUILTIN_PMINUW256_MASK,
29931 IX86_BUILTIN_PMAXSW256_MASK,
29932 IX86_BUILTIN_PMAXUW256_MASK,
29933 IX86_BUILTIN_PMINSW128_MASK,
29934 IX86_BUILTIN_PMINUW128_MASK,
29935 IX86_BUILTIN_PMAXSW128_MASK,
29936 IX86_BUILTIN_PMAXUW128_MASK,
29937 IX86_BUILTIN_VPCONFLICTQ256,
29938 IX86_BUILTIN_VPCONFLICTD256,
29939 IX86_BUILTIN_VPCLZCNTQ256,
29940 IX86_BUILTIN_VPCLZCNTD256,
29941 IX86_BUILTIN_UNPCKHPD256_MASK,
29942 IX86_BUILTIN_UNPCKHPD128_MASK,
29943 IX86_BUILTIN_UNPCKHPS256_MASK,
29944 IX86_BUILTIN_UNPCKHPS128_MASK,
29945 IX86_BUILTIN_UNPCKLPD256_MASK,
29946 IX86_BUILTIN_UNPCKLPD128_MASK,
29947 IX86_BUILTIN_UNPCKLPS256_MASK,
29948 IX86_BUILTIN_VPCONFLICTQ128,
29949 IX86_BUILTIN_VPCONFLICTD128,
29950 IX86_BUILTIN_VPCLZCNTQ128,
29951 IX86_BUILTIN_VPCLZCNTD128,
29952 IX86_BUILTIN_UNPCKLPS128_MASK,
29953 IX86_BUILTIN_ALIGND256,
29954 IX86_BUILTIN_ALIGNQ256,
29955 IX86_BUILTIN_ALIGND128,
29956 IX86_BUILTIN_ALIGNQ128,
29957 IX86_BUILTIN_CVTPS2PH256_MASK,
29958 IX86_BUILTIN_CVTPS2PH_MASK,
29959 IX86_BUILTIN_CVTPH2PS_MASK,
29960 IX86_BUILTIN_CVTPH2PS256_MASK,
29961 IX86_BUILTIN_PUNPCKHDQ128_MASK,
29962 IX86_BUILTIN_PUNPCKHDQ256_MASK,
29963 IX86_BUILTIN_PUNPCKHQDQ128_MASK,
29964 IX86_BUILTIN_PUNPCKHQDQ256_MASK,
29965 IX86_BUILTIN_PUNPCKLDQ128_MASK,
29966 IX86_BUILTIN_PUNPCKLDQ256_MASK,
29967 IX86_BUILTIN_PUNPCKLQDQ128_MASK,
29968 IX86_BUILTIN_PUNPCKLQDQ256_MASK,
29969 IX86_BUILTIN_PUNPCKHBW128_MASK,
29970 IX86_BUILTIN_PUNPCKHBW256_MASK,
29971 IX86_BUILTIN_PUNPCKHWD128_MASK,
29972 IX86_BUILTIN_PUNPCKHWD256_MASK,
29973 IX86_BUILTIN_PUNPCKLBW128_MASK,
29974 IX86_BUILTIN_PUNPCKLBW256_MASK,
29975 IX86_BUILTIN_PUNPCKLWD128_MASK,
29976 IX86_BUILTIN_PUNPCKLWD256_MASK,
29977 IX86_BUILTIN_PSLLVV16HI,
29978 IX86_BUILTIN_PSLLVV8HI,
29979 IX86_BUILTIN_PACKSSDW256_MASK,
29980 IX86_BUILTIN_PACKSSDW128_MASK,
29981 IX86_BUILTIN_PACKUSDW256_MASK,
29982 IX86_BUILTIN_PACKUSDW128_MASK,
29983 IX86_BUILTIN_PAVGB256_MASK,
29984 IX86_BUILTIN_PAVGW256_MASK,
29985 IX86_BUILTIN_PAVGB128_MASK,
29986 IX86_BUILTIN_PAVGW128_MASK,
29987 IX86_BUILTIN_VPERMVARSF256_MASK,
29988 IX86_BUILTIN_VPERMVARDF256_MASK,
29989 IX86_BUILTIN_VPERMDF256_MASK,
29990 IX86_BUILTIN_PABSB256_MASK,
29991 IX86_BUILTIN_PABSB128_MASK,
29992 IX86_BUILTIN_PABSW256_MASK,
29993 IX86_BUILTIN_PABSW128_MASK,
29994 IX86_BUILTIN_VPERMILVARPD_MASK,
29995 IX86_BUILTIN_VPERMILVARPS_MASK,
29996 IX86_BUILTIN_VPERMILVARPD256_MASK,
29997 IX86_BUILTIN_VPERMILVARPS256_MASK,
29998 IX86_BUILTIN_VPERMILPD_MASK,
29999 IX86_BUILTIN_VPERMILPS_MASK,
30000 IX86_BUILTIN_VPERMILPD256_MASK,
30001 IX86_BUILTIN_VPERMILPS256_MASK,
30002 IX86_BUILTIN_BLENDMQ256,
30003 IX86_BUILTIN_BLENDMD256,
30004 IX86_BUILTIN_BLENDMPD256,
30005 IX86_BUILTIN_BLENDMPS256,
30006 IX86_BUILTIN_BLENDMQ128,
30007 IX86_BUILTIN_BLENDMD128,
30008 IX86_BUILTIN_BLENDMPD128,
30009 IX86_BUILTIN_BLENDMPS128,
30010 IX86_BUILTIN_BLENDMW256,
30011 IX86_BUILTIN_BLENDMB256,
30012 IX86_BUILTIN_BLENDMW128,
30013 IX86_BUILTIN_BLENDMB128,
30014 IX86_BUILTIN_PMULLD256_MASK,
30015 IX86_BUILTIN_PMULLD128_MASK,
30016 IX86_BUILTIN_PMULUDQ256_MASK,
30017 IX86_BUILTIN_PMULDQ256_MASK,
30018 IX86_BUILTIN_PMULDQ128_MASK,
30019 IX86_BUILTIN_PMULUDQ128_MASK,
30020 IX86_BUILTIN_CVTPD2PS256_MASK,
30021 IX86_BUILTIN_CVTPD2PS_MASK,
30022 IX86_BUILTIN_VPERMVARSI256_MASK,
30023 IX86_BUILTIN_VPERMVARDI256_MASK,
30024 IX86_BUILTIN_VPERMDI256_MASK,
30025 IX86_BUILTIN_CMPQ256,
30026 IX86_BUILTIN_CMPD256,
30027 IX86_BUILTIN_UCMPQ256,
30028 IX86_BUILTIN_UCMPD256,
30029 IX86_BUILTIN_CMPB256,
30030 IX86_BUILTIN_CMPW256,
30031 IX86_BUILTIN_UCMPB256,
30032 IX86_BUILTIN_UCMPW256,
30033 IX86_BUILTIN_CMPPD256_MASK,
30034 IX86_BUILTIN_CMPPS256_MASK,
30035 IX86_BUILTIN_CMPQ128,
30036 IX86_BUILTIN_CMPD128,
30037 IX86_BUILTIN_UCMPQ128,
30038 IX86_BUILTIN_UCMPD128,
30039 IX86_BUILTIN_CMPB128,
30040 IX86_BUILTIN_CMPW128,
30041 IX86_BUILTIN_UCMPB128,
30042 IX86_BUILTIN_UCMPW128,
30043 IX86_BUILTIN_CMPPD128_MASK,
30044 IX86_BUILTIN_CMPPS128_MASK,
30046 IX86_BUILTIN_GATHER3SIV8SF,
30047 IX86_BUILTIN_GATHER3SIV4SF,
30048 IX86_BUILTIN_GATHER3SIV4DF,
30049 IX86_BUILTIN_GATHER3SIV2DF,
30050 IX86_BUILTIN_GATHER3DIV8SF,
30051 IX86_BUILTIN_GATHER3DIV4SF,
30052 IX86_BUILTIN_GATHER3DIV4DF,
30053 IX86_BUILTIN_GATHER3DIV2DF,
30054 IX86_BUILTIN_GATHER3SIV8SI,
30055 IX86_BUILTIN_GATHER3SIV4SI,
30056 IX86_BUILTIN_GATHER3SIV4DI,
30057 IX86_BUILTIN_GATHER3SIV2DI,
30058 IX86_BUILTIN_GATHER3DIV8SI,
30059 IX86_BUILTIN_GATHER3DIV4SI,
30060 IX86_BUILTIN_GATHER3DIV4DI,
30061 IX86_BUILTIN_GATHER3DIV2DI,
30062 IX86_BUILTIN_SCATTERSIV8SF,
30063 IX86_BUILTIN_SCATTERSIV4SF,
30064 IX86_BUILTIN_SCATTERSIV4DF,
30065 IX86_BUILTIN_SCATTERSIV2DF,
30066 IX86_BUILTIN_SCATTERDIV8SF,
30067 IX86_BUILTIN_SCATTERDIV4SF,
30068 IX86_BUILTIN_SCATTERDIV4DF,
30069 IX86_BUILTIN_SCATTERDIV2DF,
30070 IX86_BUILTIN_SCATTERSIV8SI,
30071 IX86_BUILTIN_SCATTERSIV4SI,
30072 IX86_BUILTIN_SCATTERSIV4DI,
30073 IX86_BUILTIN_SCATTERSIV2DI,
30074 IX86_BUILTIN_SCATTERDIV8SI,
30075 IX86_BUILTIN_SCATTERDIV4SI,
30076 IX86_BUILTIN_SCATTERDIV4DI,
30077 IX86_BUILTIN_SCATTERDIV2DI,
30079 /* AVX512DQ. */
30080 IX86_BUILTIN_RANGESD128,
30081 IX86_BUILTIN_RANGESS128,
30082 IX86_BUILTIN_KUNPCKWD,
30083 IX86_BUILTIN_KUNPCKDQ,
30084 IX86_BUILTIN_BROADCASTF32x2_512,
30085 IX86_BUILTIN_BROADCASTI32x2_512,
30086 IX86_BUILTIN_BROADCASTF64X2_512,
30087 IX86_BUILTIN_BROADCASTI64X2_512,
30088 IX86_BUILTIN_BROADCASTF32X8_512,
30089 IX86_BUILTIN_BROADCASTI32X8_512,
30090 IX86_BUILTIN_EXTRACTF64X2_512,
30091 IX86_BUILTIN_EXTRACTF32X8,
30092 IX86_BUILTIN_EXTRACTI64X2_512,
30093 IX86_BUILTIN_EXTRACTI32X8,
30094 IX86_BUILTIN_REDUCEPD512_MASK,
30095 IX86_BUILTIN_REDUCEPS512_MASK,
30096 IX86_BUILTIN_PMULLQ512,
30097 IX86_BUILTIN_XORPD512,
30098 IX86_BUILTIN_XORPS512,
30099 IX86_BUILTIN_ORPD512,
30100 IX86_BUILTIN_ORPS512,
30101 IX86_BUILTIN_ANDPD512,
30102 IX86_BUILTIN_ANDPS512,
30103 IX86_BUILTIN_ANDNPD512,
30104 IX86_BUILTIN_ANDNPS512,
30105 IX86_BUILTIN_INSERTF32X8,
30106 IX86_BUILTIN_INSERTI32X8,
30107 IX86_BUILTIN_INSERTF64X2_512,
30108 IX86_BUILTIN_INSERTI64X2_512,
30109 IX86_BUILTIN_FPCLASSPD512,
30110 IX86_BUILTIN_FPCLASSPS512,
30111 IX86_BUILTIN_CVTD2MASK512,
30112 IX86_BUILTIN_CVTQ2MASK512,
30113 IX86_BUILTIN_CVTMASK2D512,
30114 IX86_BUILTIN_CVTMASK2Q512,
30115 IX86_BUILTIN_CVTPD2QQ512,
30116 IX86_BUILTIN_CVTPS2QQ512,
30117 IX86_BUILTIN_CVTPD2UQQ512,
30118 IX86_BUILTIN_CVTPS2UQQ512,
30119 IX86_BUILTIN_CVTQQ2PS512,
30120 IX86_BUILTIN_CVTUQQ2PS512,
30121 IX86_BUILTIN_CVTQQ2PD512,
30122 IX86_BUILTIN_CVTUQQ2PD512,
30123 IX86_BUILTIN_CVTTPS2QQ512,
30124 IX86_BUILTIN_CVTTPS2UQQ512,
30125 IX86_BUILTIN_CVTTPD2QQ512,
30126 IX86_BUILTIN_CVTTPD2UQQ512,
30127 IX86_BUILTIN_RANGEPS512,
30128 IX86_BUILTIN_RANGEPD512,
30130 /* AVX512BW. */
30131 IX86_BUILTIN_PACKUSDW512,
30132 IX86_BUILTIN_PACKSSDW512,
30133 IX86_BUILTIN_LOADDQUHI512_MASK,
30134 IX86_BUILTIN_LOADDQUQI512_MASK,
30135 IX86_BUILTIN_PSLLDQ512,
30136 IX86_BUILTIN_PSRLDQ512,
30137 IX86_BUILTIN_STOREDQUHI512_MASK,
30138 IX86_BUILTIN_STOREDQUQI512_MASK,
30139 IX86_BUILTIN_PALIGNR512,
30140 IX86_BUILTIN_PALIGNR512_MASK,
30141 IX86_BUILTIN_MOVDQUHI512_MASK,
30142 IX86_BUILTIN_MOVDQUQI512_MASK,
30143 IX86_BUILTIN_PSADBW512,
30144 IX86_BUILTIN_DBPSADBW512,
30145 IX86_BUILTIN_PBROADCASTB512,
30146 IX86_BUILTIN_PBROADCASTB512_GPR,
30147 IX86_BUILTIN_PBROADCASTW512,
30148 IX86_BUILTIN_PBROADCASTW512_GPR,
30149 IX86_BUILTIN_PMOVSXBW512_MASK,
30150 IX86_BUILTIN_PMOVZXBW512_MASK,
30151 IX86_BUILTIN_VPERMVARHI512_MASK,
30152 IX86_BUILTIN_VPERMT2VARHI512,
30153 IX86_BUILTIN_VPERMT2VARHI512_MASKZ,
30154 IX86_BUILTIN_VPERMI2VARHI512,
30155 IX86_BUILTIN_PAVGB512,
30156 IX86_BUILTIN_PAVGW512,
30157 IX86_BUILTIN_PADDB512,
30158 IX86_BUILTIN_PSUBB512,
30159 IX86_BUILTIN_PSUBSB512,
30160 IX86_BUILTIN_PADDSB512,
30161 IX86_BUILTIN_PSUBUSB512,
30162 IX86_BUILTIN_PADDUSB512,
30163 IX86_BUILTIN_PSUBW512,
30164 IX86_BUILTIN_PADDW512,
30165 IX86_BUILTIN_PSUBSW512,
30166 IX86_BUILTIN_PADDSW512,
30167 IX86_BUILTIN_PSUBUSW512,
30168 IX86_BUILTIN_PADDUSW512,
30169 IX86_BUILTIN_PMAXUW512,
30170 IX86_BUILTIN_PMAXSW512,
30171 IX86_BUILTIN_PMINUW512,
30172 IX86_BUILTIN_PMINSW512,
30173 IX86_BUILTIN_PMAXUB512,
30174 IX86_BUILTIN_PMAXSB512,
30175 IX86_BUILTIN_PMINUB512,
30176 IX86_BUILTIN_PMINSB512,
30177 IX86_BUILTIN_PMOVWB512,
30178 IX86_BUILTIN_PMOVSWB512,
30179 IX86_BUILTIN_PMOVUSWB512,
30180 IX86_BUILTIN_PMULHRSW512_MASK,
30181 IX86_BUILTIN_PMULHUW512_MASK,
30182 IX86_BUILTIN_PMULHW512_MASK,
30183 IX86_BUILTIN_PMULLW512_MASK,
30184 IX86_BUILTIN_PSLLWI512_MASK,
30185 IX86_BUILTIN_PSLLW512_MASK,
30186 IX86_BUILTIN_PACKSSWB512,
30187 IX86_BUILTIN_PACKUSWB512,
30188 IX86_BUILTIN_PSRAVV32HI,
30189 IX86_BUILTIN_PMADDUBSW512_MASK,
30190 IX86_BUILTIN_PMADDWD512_MASK,
30191 IX86_BUILTIN_PSRLVV32HI,
30192 IX86_BUILTIN_PUNPCKHBW512,
30193 IX86_BUILTIN_PUNPCKHWD512,
30194 IX86_BUILTIN_PUNPCKLBW512,
30195 IX86_BUILTIN_PUNPCKLWD512,
30196 IX86_BUILTIN_PSHUFB512,
30197 IX86_BUILTIN_PSHUFHW512,
30198 IX86_BUILTIN_PSHUFLW512,
30199 IX86_BUILTIN_PSRAWI512,
30200 IX86_BUILTIN_PSRAW512,
30201 IX86_BUILTIN_PSRLWI512,
30202 IX86_BUILTIN_PSRLW512,
30203 IX86_BUILTIN_CVTB2MASK512,
30204 IX86_BUILTIN_CVTW2MASK512,
30205 IX86_BUILTIN_CVTMASK2B512,
30206 IX86_BUILTIN_CVTMASK2W512,
30207 IX86_BUILTIN_PCMPEQB512_MASK,
30208 IX86_BUILTIN_PCMPEQW512_MASK,
30209 IX86_BUILTIN_PCMPGTB512_MASK,
30210 IX86_BUILTIN_PCMPGTW512_MASK,
30211 IX86_BUILTIN_PTESTMB512,
30212 IX86_BUILTIN_PTESTMW512,
30213 IX86_BUILTIN_PTESTNMB512,
30214 IX86_BUILTIN_PTESTNMW512,
30215 IX86_BUILTIN_PSLLVV32HI,
30216 IX86_BUILTIN_PABSB512,
30217 IX86_BUILTIN_PABSW512,
30218 IX86_BUILTIN_BLENDMW512,
30219 IX86_BUILTIN_BLENDMB512,
30220 IX86_BUILTIN_CMPB512,
30221 IX86_BUILTIN_CMPW512,
30222 IX86_BUILTIN_UCMPB512,
30223 IX86_BUILTIN_UCMPW512,
30225 /* Alternate 4 and 8 element gather/scatter for the vectorizer
30226 where all operands are 32-byte or 64-byte wide respectively. */
30227 IX86_BUILTIN_GATHERALTSIV4DF,
30228 IX86_BUILTIN_GATHERALTDIV8SF,
30229 IX86_BUILTIN_GATHERALTSIV4DI,
30230 IX86_BUILTIN_GATHERALTDIV8SI,
30231 IX86_BUILTIN_GATHER3ALTDIV16SF,
30232 IX86_BUILTIN_GATHER3ALTDIV16SI,
30233 IX86_BUILTIN_GATHER3ALTSIV4DF,
30234 IX86_BUILTIN_GATHER3ALTDIV8SF,
30235 IX86_BUILTIN_GATHER3ALTSIV4DI,
30236 IX86_BUILTIN_GATHER3ALTDIV8SI,
30237 IX86_BUILTIN_GATHER3ALTSIV8DF,
30238 IX86_BUILTIN_GATHER3ALTSIV8DI,
30239 IX86_BUILTIN_GATHER3DIV16SF,
30240 IX86_BUILTIN_GATHER3DIV16SI,
30241 IX86_BUILTIN_GATHER3DIV8DF,
30242 IX86_BUILTIN_GATHER3DIV8DI,
30243 IX86_BUILTIN_GATHER3SIV16SF,
30244 IX86_BUILTIN_GATHER3SIV16SI,
30245 IX86_BUILTIN_GATHER3SIV8DF,
30246 IX86_BUILTIN_GATHER3SIV8DI,
30247 IX86_BUILTIN_SCATTERDIV16SF,
30248 IX86_BUILTIN_SCATTERDIV16SI,
30249 IX86_BUILTIN_SCATTERDIV8DF,
30250 IX86_BUILTIN_SCATTERDIV8DI,
30251 IX86_BUILTIN_SCATTERSIV16SF,
30252 IX86_BUILTIN_SCATTERSIV16SI,
30253 IX86_BUILTIN_SCATTERSIV8DF,
30254 IX86_BUILTIN_SCATTERSIV8DI,
30256 /* AVX512PF */
30257 IX86_BUILTIN_GATHERPFQPD,
30258 IX86_BUILTIN_GATHERPFDPS,
30259 IX86_BUILTIN_GATHERPFDPD,
30260 IX86_BUILTIN_GATHERPFQPS,
30261 IX86_BUILTIN_SCATTERPFDPD,
30262 IX86_BUILTIN_SCATTERPFDPS,
30263 IX86_BUILTIN_SCATTERPFQPD,
30264 IX86_BUILTIN_SCATTERPFQPS,
30266 /* AVX-512ER */
30267 IX86_BUILTIN_EXP2PD_MASK,
30268 IX86_BUILTIN_EXP2PS_MASK,
30269 IX86_BUILTIN_EXP2PS,
30270 IX86_BUILTIN_RCP28PD,
30271 IX86_BUILTIN_RCP28PS,
30272 IX86_BUILTIN_RCP28SD,
30273 IX86_BUILTIN_RCP28SS,
30274 IX86_BUILTIN_RSQRT28PD,
30275 IX86_BUILTIN_RSQRT28PS,
30276 IX86_BUILTIN_RSQRT28SD,
30277 IX86_BUILTIN_RSQRT28SS,
30279 /* AVX-512IFMA */
30280 IX86_BUILTIN_VPMADD52LUQ512,
30281 IX86_BUILTIN_VPMADD52HUQ512,
30282 IX86_BUILTIN_VPMADD52LUQ256,
30283 IX86_BUILTIN_VPMADD52HUQ256,
30284 IX86_BUILTIN_VPMADD52LUQ128,
30285 IX86_BUILTIN_VPMADD52HUQ128,
30286 IX86_BUILTIN_VPMADD52LUQ512_MASKZ,
30287 IX86_BUILTIN_VPMADD52HUQ512_MASKZ,
30288 IX86_BUILTIN_VPMADD52LUQ256_MASKZ,
30289 IX86_BUILTIN_VPMADD52HUQ256_MASKZ,
30290 IX86_BUILTIN_VPMADD52LUQ128_MASKZ,
30291 IX86_BUILTIN_VPMADD52HUQ128_MASKZ,
30293 /* AVX-512VBMI */
30294 IX86_BUILTIN_VPMULTISHIFTQB512,
30295 IX86_BUILTIN_VPMULTISHIFTQB256,
30296 IX86_BUILTIN_VPMULTISHIFTQB128,
30297 IX86_BUILTIN_VPERMVARQI512_MASK,
30298 IX86_BUILTIN_VPERMT2VARQI512,
30299 IX86_BUILTIN_VPERMT2VARQI512_MASKZ,
30300 IX86_BUILTIN_VPERMI2VARQI512,
30301 IX86_BUILTIN_VPERMVARQI256_MASK,
30302 IX86_BUILTIN_VPERMVARQI128_MASK,
30303 IX86_BUILTIN_VPERMT2VARQI256,
30304 IX86_BUILTIN_VPERMT2VARQI256_MASKZ,
30305 IX86_BUILTIN_VPERMT2VARQI128,
30306 IX86_BUILTIN_VPERMT2VARQI128_MASKZ,
30307 IX86_BUILTIN_VPERMI2VARQI256,
30308 IX86_BUILTIN_VPERMI2VARQI128,
30310 /* SHA builtins. */
30311 IX86_BUILTIN_SHA1MSG1,
30312 IX86_BUILTIN_SHA1MSG2,
30313 IX86_BUILTIN_SHA1NEXTE,
30314 IX86_BUILTIN_SHA1RNDS4,
30315 IX86_BUILTIN_SHA256MSG1,
30316 IX86_BUILTIN_SHA256MSG2,
30317 IX86_BUILTIN_SHA256RNDS2,
30319 /* CLWB instructions. */
30320 IX86_BUILTIN_CLWB,
30322 /* PCOMMIT instructions. */
30323 IX86_BUILTIN_PCOMMIT,
30325 /* CLFLUSHOPT instructions. */
30326 IX86_BUILTIN_CLFLUSHOPT,
30328 /* TFmode support builtins. */
30329 IX86_BUILTIN_INFQ,
30330 IX86_BUILTIN_HUGE_VALQ,
30331 IX86_BUILTIN_FABSQ,
30332 IX86_BUILTIN_COPYSIGNQ,
30334 /* Vectorizer support builtins. */
30335 IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512,
30336 IX86_BUILTIN_CPYSGNPS,
30337 IX86_BUILTIN_CPYSGNPD,
30338 IX86_BUILTIN_CPYSGNPS256,
30339 IX86_BUILTIN_CPYSGNPS512,
30340 IX86_BUILTIN_CPYSGNPD256,
30341 IX86_BUILTIN_CPYSGNPD512,
30342 IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512,
30343 IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512,
30346 /* FMA4 instructions. */
30347 IX86_BUILTIN_VFMADDSS,
30348 IX86_BUILTIN_VFMADDSD,
30349 IX86_BUILTIN_VFMADDPS,
30350 IX86_BUILTIN_VFMADDPD,
30351 IX86_BUILTIN_VFMADDPS256,
30352 IX86_BUILTIN_VFMADDPD256,
30353 IX86_BUILTIN_VFMADDSUBPS,
30354 IX86_BUILTIN_VFMADDSUBPD,
30355 IX86_BUILTIN_VFMADDSUBPS256,
30356 IX86_BUILTIN_VFMADDSUBPD256,
30358 /* FMA3 instructions. */
30359 IX86_BUILTIN_VFMADDSS3,
30360 IX86_BUILTIN_VFMADDSD3,
30362 /* XOP instructions. */
30363 IX86_BUILTIN_VPCMOV,
30364 IX86_BUILTIN_VPCMOV_V2DI,
30365 IX86_BUILTIN_VPCMOV_V4SI,
30366 IX86_BUILTIN_VPCMOV_V8HI,
30367 IX86_BUILTIN_VPCMOV_V16QI,
30368 IX86_BUILTIN_VPCMOV_V4SF,
30369 IX86_BUILTIN_VPCMOV_V2DF,
30370 IX86_BUILTIN_VPCMOV256,
30371 IX86_BUILTIN_VPCMOV_V4DI256,
30372 IX86_BUILTIN_VPCMOV_V8SI256,
30373 IX86_BUILTIN_VPCMOV_V16HI256,
30374 IX86_BUILTIN_VPCMOV_V32QI256,
30375 IX86_BUILTIN_VPCMOV_V8SF256,
30376 IX86_BUILTIN_VPCMOV_V4DF256,
30378 IX86_BUILTIN_VPPERM,
30380 IX86_BUILTIN_VPMACSSWW,
30381 IX86_BUILTIN_VPMACSWW,
30382 IX86_BUILTIN_VPMACSSWD,
30383 IX86_BUILTIN_VPMACSWD,
30384 IX86_BUILTIN_VPMACSSDD,
30385 IX86_BUILTIN_VPMACSDD,
30386 IX86_BUILTIN_VPMACSSDQL,
30387 IX86_BUILTIN_VPMACSSDQH,
30388 IX86_BUILTIN_VPMACSDQL,
30389 IX86_BUILTIN_VPMACSDQH,
30390 IX86_BUILTIN_VPMADCSSWD,
30391 IX86_BUILTIN_VPMADCSWD,
30393 IX86_BUILTIN_VPHADDBW,
30394 IX86_BUILTIN_VPHADDBD,
30395 IX86_BUILTIN_VPHADDBQ,
30396 IX86_BUILTIN_VPHADDWD,
30397 IX86_BUILTIN_VPHADDWQ,
30398 IX86_BUILTIN_VPHADDDQ,
30399 IX86_BUILTIN_VPHADDUBW,
30400 IX86_BUILTIN_VPHADDUBD,
30401 IX86_BUILTIN_VPHADDUBQ,
30402 IX86_BUILTIN_VPHADDUWD,
30403 IX86_BUILTIN_VPHADDUWQ,
30404 IX86_BUILTIN_VPHADDUDQ,
30405 IX86_BUILTIN_VPHSUBBW,
30406 IX86_BUILTIN_VPHSUBWD,
30407 IX86_BUILTIN_VPHSUBDQ,
30409 IX86_BUILTIN_VPROTB,
30410 IX86_BUILTIN_VPROTW,
30411 IX86_BUILTIN_VPROTD,
30412 IX86_BUILTIN_VPROTQ,
30413 IX86_BUILTIN_VPROTB_IMM,
30414 IX86_BUILTIN_VPROTW_IMM,
30415 IX86_BUILTIN_VPROTD_IMM,
30416 IX86_BUILTIN_VPROTQ_IMM,
30418 IX86_BUILTIN_VPSHLB,
30419 IX86_BUILTIN_VPSHLW,
30420 IX86_BUILTIN_VPSHLD,
30421 IX86_BUILTIN_VPSHLQ,
30422 IX86_BUILTIN_VPSHAB,
30423 IX86_BUILTIN_VPSHAW,
30424 IX86_BUILTIN_VPSHAD,
30425 IX86_BUILTIN_VPSHAQ,
30427 IX86_BUILTIN_VFRCZSS,
30428 IX86_BUILTIN_VFRCZSD,
30429 IX86_BUILTIN_VFRCZPS,
30430 IX86_BUILTIN_VFRCZPD,
30431 IX86_BUILTIN_VFRCZPS256,
30432 IX86_BUILTIN_VFRCZPD256,
30434 IX86_BUILTIN_VPCOMEQUB,
30435 IX86_BUILTIN_VPCOMNEUB,
30436 IX86_BUILTIN_VPCOMLTUB,
30437 IX86_BUILTIN_VPCOMLEUB,
30438 IX86_BUILTIN_VPCOMGTUB,
30439 IX86_BUILTIN_VPCOMGEUB,
30440 IX86_BUILTIN_VPCOMFALSEUB,
30441 IX86_BUILTIN_VPCOMTRUEUB,
30443 IX86_BUILTIN_VPCOMEQUW,
30444 IX86_BUILTIN_VPCOMNEUW,
30445 IX86_BUILTIN_VPCOMLTUW,
30446 IX86_BUILTIN_VPCOMLEUW,
30447 IX86_BUILTIN_VPCOMGTUW,
30448 IX86_BUILTIN_VPCOMGEUW,
30449 IX86_BUILTIN_VPCOMFALSEUW,
30450 IX86_BUILTIN_VPCOMTRUEUW,
30452 IX86_BUILTIN_VPCOMEQUD,
30453 IX86_BUILTIN_VPCOMNEUD,
30454 IX86_BUILTIN_VPCOMLTUD,
30455 IX86_BUILTIN_VPCOMLEUD,
30456 IX86_BUILTIN_VPCOMGTUD,
30457 IX86_BUILTIN_VPCOMGEUD,
30458 IX86_BUILTIN_VPCOMFALSEUD,
30459 IX86_BUILTIN_VPCOMTRUEUD,
30461 IX86_BUILTIN_VPCOMEQUQ,
30462 IX86_BUILTIN_VPCOMNEUQ,
30463 IX86_BUILTIN_VPCOMLTUQ,
30464 IX86_BUILTIN_VPCOMLEUQ,
30465 IX86_BUILTIN_VPCOMGTUQ,
30466 IX86_BUILTIN_VPCOMGEUQ,
30467 IX86_BUILTIN_VPCOMFALSEUQ,
30468 IX86_BUILTIN_VPCOMTRUEUQ,
30470 IX86_BUILTIN_VPCOMEQB,
30471 IX86_BUILTIN_VPCOMNEB,
30472 IX86_BUILTIN_VPCOMLTB,
30473 IX86_BUILTIN_VPCOMLEB,
30474 IX86_BUILTIN_VPCOMGTB,
30475 IX86_BUILTIN_VPCOMGEB,
30476 IX86_BUILTIN_VPCOMFALSEB,
30477 IX86_BUILTIN_VPCOMTRUEB,
30479 IX86_BUILTIN_VPCOMEQW,
30480 IX86_BUILTIN_VPCOMNEW,
30481 IX86_BUILTIN_VPCOMLTW,
30482 IX86_BUILTIN_VPCOMLEW,
30483 IX86_BUILTIN_VPCOMGTW,
30484 IX86_BUILTIN_VPCOMGEW,
30485 IX86_BUILTIN_VPCOMFALSEW,
30486 IX86_BUILTIN_VPCOMTRUEW,
30488 IX86_BUILTIN_VPCOMEQD,
30489 IX86_BUILTIN_VPCOMNED,
30490 IX86_BUILTIN_VPCOMLTD,
30491 IX86_BUILTIN_VPCOMLED,
30492 IX86_BUILTIN_VPCOMGTD,
30493 IX86_BUILTIN_VPCOMGED,
30494 IX86_BUILTIN_VPCOMFALSED,
30495 IX86_BUILTIN_VPCOMTRUED,
30497 IX86_BUILTIN_VPCOMEQQ,
30498 IX86_BUILTIN_VPCOMNEQ,
30499 IX86_BUILTIN_VPCOMLTQ,
30500 IX86_BUILTIN_VPCOMLEQ,
30501 IX86_BUILTIN_VPCOMGTQ,
30502 IX86_BUILTIN_VPCOMGEQ,
30503 IX86_BUILTIN_VPCOMFALSEQ,
30504 IX86_BUILTIN_VPCOMTRUEQ,
30506 /* LWP instructions. */
30507 IX86_BUILTIN_LLWPCB,
30508 IX86_BUILTIN_SLWPCB,
30509 IX86_BUILTIN_LWPVAL32,
30510 IX86_BUILTIN_LWPVAL64,
30511 IX86_BUILTIN_LWPINS32,
30512 IX86_BUILTIN_LWPINS64,
30514 IX86_BUILTIN_CLZS,
30516 /* RTM */
30517 IX86_BUILTIN_XBEGIN,
30518 IX86_BUILTIN_XEND,
30519 IX86_BUILTIN_XABORT,
30520 IX86_BUILTIN_XTEST,
30522 /* MPX */
30523 IX86_BUILTIN_BNDMK,
30524 IX86_BUILTIN_BNDSTX,
30525 IX86_BUILTIN_BNDLDX,
30526 IX86_BUILTIN_BNDCL,
30527 IX86_BUILTIN_BNDCU,
30528 IX86_BUILTIN_BNDRET,
30529 IX86_BUILTIN_BNDNARROW,
30530 IX86_BUILTIN_BNDINT,
30531 IX86_BUILTIN_SIZEOF,
30532 IX86_BUILTIN_BNDLOWER,
30533 IX86_BUILTIN_BNDUPPER,
30535 /* BMI instructions. */
30536 IX86_BUILTIN_BEXTR32,
30537 IX86_BUILTIN_BEXTR64,
30538 IX86_BUILTIN_CTZS,
30540 /* TBM instructions. */
30541 IX86_BUILTIN_BEXTRI32,
30542 IX86_BUILTIN_BEXTRI64,
30544 /* BMI2 instructions. */
30545 IX86_BUILTIN_BZHI32,
30546 IX86_BUILTIN_BZHI64,
30547 IX86_BUILTIN_PDEP32,
30548 IX86_BUILTIN_PDEP64,
30549 IX86_BUILTIN_PEXT32,
30550 IX86_BUILTIN_PEXT64,
30552 /* ADX instructions. */
30553 IX86_BUILTIN_ADDCARRYX32,
30554 IX86_BUILTIN_ADDCARRYX64,
30556 /* SBB instructions. */
30557 IX86_BUILTIN_SBB32,
30558 IX86_BUILTIN_SBB64,
30560 /* FSGSBASE instructions. */
30561 IX86_BUILTIN_RDFSBASE32,
30562 IX86_BUILTIN_RDFSBASE64,
30563 IX86_BUILTIN_RDGSBASE32,
30564 IX86_BUILTIN_RDGSBASE64,
30565 IX86_BUILTIN_WRFSBASE32,
30566 IX86_BUILTIN_WRFSBASE64,
30567 IX86_BUILTIN_WRGSBASE32,
30568 IX86_BUILTIN_WRGSBASE64,
30570 /* RDRND instructions. */
30571 IX86_BUILTIN_RDRAND16_STEP,
30572 IX86_BUILTIN_RDRAND32_STEP,
30573 IX86_BUILTIN_RDRAND64_STEP,
30575 /* RDSEED instructions. */
30576 IX86_BUILTIN_RDSEED16_STEP,
30577 IX86_BUILTIN_RDSEED32_STEP,
30578 IX86_BUILTIN_RDSEED64_STEP,
30580 /* F16C instructions. */
30581 IX86_BUILTIN_CVTPH2PS,
30582 IX86_BUILTIN_CVTPH2PS256,
30583 IX86_BUILTIN_CVTPS2PH,
30584 IX86_BUILTIN_CVTPS2PH256,
30586 /* MONITORX and MWAITX instrucions. */
30587 IX86_BUILTIN_MONITORX,
30588 IX86_BUILTIN_MWAITX,
30590 /* CFString built-in for darwin */
30591 IX86_BUILTIN_CFSTRING,
30593 /* Builtins to get CPU type and supported features. */
30594 IX86_BUILTIN_CPU_INIT,
30595 IX86_BUILTIN_CPU_IS,
30596 IX86_BUILTIN_CPU_SUPPORTS,
30598 /* Read/write FLAGS register built-ins. */
30599 IX86_BUILTIN_READ_FLAGS,
30600 IX86_BUILTIN_WRITE_FLAGS,
30602 IX86_BUILTIN_MAX
30603 };
30605 /* Table for the ix86 builtin decls. */
30608 /* Table of all of the builtin functions that are possible with different ISA's
30609 but are waiting to be built until a function is declared to use that
30610 ISA. */
30619 };
30623 /* Bits that can still enable any inclusion of a builtin. */
30626 /* Add an ix86 target builtin function with CODE, NAME and TYPE. Save the MASK
30627 of which isa_flags to use in the ix86_builtins_isa array. Stores the
30628 function decl in the ix86_builtins array. Returns the function decl or
30629 NULL_TREE, if the builtin was not added.
30631 If the front end has a special hook for builtin functions, delay adding
30632 builtin functions that aren't in the current ISA until the ISA is changed
30633 with function specific optimization. Doing so, can save about 300K for the
30634 default compiler. When the builtin is expanded, check at that time whether
30635 it is valid.
30637 If the front end doesn't have a special hook, record all builtins, even if
30638 it isn't an instruction set in the current ISA in case the user uses
30639 function specific options for a different ISA, so that we don't get scope
30640 errors if a builtin is added in the middle of a function scope. */
30646 {
30650 {
30659 {
30665 }
30666 else
30667 {
30668 /* Just a MASK where set_and_not_built_p == true can potentially
30669 include a builtin. */
30678 }
30679 }
30682 }
30684 /* Like def_builtin, but also marks the function decl "const". */
30689 {
30693 else
30697 }
30699 /* Add any new builtin functions for a given ISA that may not have been
30700 declared. This saves a bit of space compared to adding all of the
30701 declarations to the tree, even if we didn't use them. */
30703 static void
30705 {
30709 /* Bits in ISA value can be removed from potential isa values. */
30717 {
30720 {
30723 /* Don't define the builtin again. */
30729 NULL_TREE);
30736 NULL_TREE);
30739 }
30740 }
30743 }
30745 /* Bits for builtin_description.flag. */
30747 /* Set when we don't support the comparison natively, and should
30748 swap_comparison in order to support it. */
30749 #define BUILTIN_DESC_SWAP_OPERANDS 1
30751 struct builtin_description
30752 {
30759 };
30762 {
30763 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comieq", IX86_BUILTIN_COMIEQSS, UNEQ, 0 },
30764 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comilt", IX86_BUILTIN_COMILTSS, UNLT, 0 },
30765 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comile", IX86_BUILTIN_COMILESS, UNLE, 0 },
30766 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comigt", IX86_BUILTIN_COMIGTSS, GT, 0 },
30767 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comige", IX86_BUILTIN_COMIGESS, GE, 0 },
30768 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_comi, "__builtin_ia32_comineq", IX86_BUILTIN_COMINEQSS, LTGT, 0 },
30769 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomieq", IX86_BUILTIN_UCOMIEQSS, UNEQ, 0 },
30770 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomilt", IX86_BUILTIN_UCOMILTSS, UNLT, 0 },
30771 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomile", IX86_BUILTIN_UCOMILESS, UNLE, 0 },
30772 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomigt", IX86_BUILTIN_UCOMIGTSS, GT, 0 },
30773 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomige", IX86_BUILTIN_UCOMIGESS, GE, 0 },
30774 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_ucomi, "__builtin_ia32_ucomineq", IX86_BUILTIN_UCOMINEQSS, LTGT, 0 },
30775 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdeq", IX86_BUILTIN_COMIEQSD, UNEQ, 0 },
30776 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdlt", IX86_BUILTIN_COMILTSD, UNLT, 0 },
30777 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdle", IX86_BUILTIN_COMILESD, UNLE, 0 },
30778 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdgt", IX86_BUILTIN_COMIGTSD, GT, 0 },
30779 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdge", IX86_BUILTIN_COMIGESD, GE, 0 },
30780 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_comi, "__builtin_ia32_comisdneq", IX86_BUILTIN_COMINEQSD, LTGT, 0 },
30781 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdeq", IX86_BUILTIN_UCOMIEQSD, UNEQ, 0 },
30782 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdlt", IX86_BUILTIN_UCOMILTSD, UNLT, 0 },
30783 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdle", IX86_BUILTIN_UCOMILESD, UNLE, 0 },
30784 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdgt", IX86_BUILTIN_UCOMIGTSD, GT, 0 },
30785 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdge", IX86_BUILTIN_UCOMIGESD, GE, 0 },
30786 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ucomi, "__builtin_ia32_ucomisdneq", IX86_BUILTIN_UCOMINEQSD, LTGT, 0 },
30787 };
30790 {
30791 /* SSE4.2 */
30792 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestri128", IX86_BUILTIN_PCMPESTRI128, UNKNOWN, 0 },
30793 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrm128", IX86_BUILTIN_PCMPESTRM128, UNKNOWN, 0 },
30794 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestria128", IX86_BUILTIN_PCMPESTRA128, UNKNOWN, (int) CCAmode },
30795 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestric128", IX86_BUILTIN_PCMPESTRC128, UNKNOWN, (int) CCCmode },
30796 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestrio128", IX86_BUILTIN_PCMPESTRO128, UNKNOWN, (int) CCOmode },
30797 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestris128", IX86_BUILTIN_PCMPESTRS128, UNKNOWN, (int) CCSmode },
30798 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpestr, "__builtin_ia32_pcmpestriz128", IX86_BUILTIN_PCMPESTRZ128, UNKNOWN, (int) CCZmode },
30799 };
30802 {
30803 /* SSE4.2 */
30804 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistri128", IX86_BUILTIN_PCMPISTRI128, UNKNOWN, 0 },
30805 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrm128", IX86_BUILTIN_PCMPISTRM128, UNKNOWN, 0 },
30806 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistria128", IX86_BUILTIN_PCMPISTRA128, UNKNOWN, (int) CCAmode },
30807 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistric128", IX86_BUILTIN_PCMPISTRC128, UNKNOWN, (int) CCCmode },
30808 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistrio128", IX86_BUILTIN_PCMPISTRO128, UNKNOWN, (int) CCOmode },
30809 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistris128", IX86_BUILTIN_PCMPISTRS128, UNKNOWN, (int) CCSmode },
30810 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_pcmpistr, "__builtin_ia32_pcmpistriz128", IX86_BUILTIN_PCMPISTRZ128, UNKNOWN, (int) CCZmode },
30811 };
30813 /* Special builtins with variable number of arguments. */
30815 {
30816 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
30817 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
30818 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
30820 /* 80387 (for use internally for atomic compound assignment). */
30821 { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
30822 { 0, CODE_FOR_fldenv, "__builtin_ia32_fldenv", IX86_BUILTIN_FLDENV, UNKNOWN, (int) VOID_FTYPE_PCVOID },
30823 { 0, CODE_FOR_fnstsw, "__builtin_ia32_fnstsw", IX86_BUILTIN_FNSTSW, UNKNOWN, (int) USHORT_FTYPE_VOID },
30824 { 0, CODE_FOR_fnclex, "__builtin_ia32_fnclex", IX86_BUILTIN_FNCLEX, UNKNOWN, (int) VOID_FTYPE_VOID },
30826 /* MMX */
30827 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_emms, "__builtin_ia32_emms", IX86_BUILTIN_EMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30829 /* 3DNow! */
30830 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_femms, "__builtin_ia32_femms", IX86_BUILTIN_FEMMS, UNKNOWN, (int) VOID_FTYPE_VOID },
30832 /* FXSR, XSAVE, XSAVEOPT, XSAVEC and XSAVES. */
30833 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxsave", IX86_BUILTIN_FXSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID },
30834 { OPTION_MASK_ISA_FXSR, CODE_FOR_nothing, "__builtin_ia32_fxrstor", IX86_BUILTIN_FXRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID },
30835 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xsave", IX86_BUILTIN_XSAVE, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30836 { OPTION_MASK_ISA_XSAVE, CODE_FOR_nothing, "__builtin_ia32_xrstor", IX86_BUILTIN_XRSTOR, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30837 { OPTION_MASK_ISA_XSAVEOPT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt", IX86_BUILTIN_XSAVEOPT, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30838 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xsaves", IX86_BUILTIN_XSAVES, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30839 { OPTION_MASK_ISA_XSAVES, CODE_FOR_nothing, "__builtin_ia32_xrstors", IX86_BUILTIN_XRSTORS, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30840 { OPTION_MASK_ISA_XSAVEC, CODE_FOR_nothing, "__builtin_ia32_xsavec", IX86_BUILTIN_XSAVEC, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30842 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxsave64", IX86_BUILTIN_FXSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30843 { OPTION_MASK_ISA_FXSR | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_fxrstor64", IX86_BUILTIN_FXRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID },
30844 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsave64", IX86_BUILTIN_XSAVE64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30845 { OPTION_MASK_ISA_XSAVE | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstor64", IX86_BUILTIN_XRSTOR64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30846 { OPTION_MASK_ISA_XSAVEOPT | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaveopt64", IX86_BUILTIN_XSAVEOPT64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30847 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsaves64", IX86_BUILTIN_XSAVES64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30848 { OPTION_MASK_ISA_XSAVES | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xrstors64", IX86_BUILTIN_XRSTORS64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30849 { OPTION_MASK_ISA_XSAVEC | OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_xsavec64", IX86_BUILTIN_XSAVEC64, UNKNOWN, (int) VOID_FTYPE_PVOID_INT64 },
30851 /* SSE */
30852 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storeups, "__builtin_ia32_storeups", IX86_BUILTIN_STOREUPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30853 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movntv4sf, "__builtin_ia32_movntps", IX86_BUILTIN_MOVNTPS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30854 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadups, "__builtin_ia32_loadups", IX86_BUILTIN_LOADUPS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30856 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadhps_exp, "__builtin_ia32_loadhps", IX86_BUILTIN_LOADHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30857 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_loadlps_exp, "__builtin_ia32_loadlps", IX86_BUILTIN_LOADLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_PCV2SF },
30858 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storehps, "__builtin_ia32_storehps", IX86_BUILTIN_STOREHPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30859 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_storelps, "__builtin_ia32_storelps", IX86_BUILTIN_STORELPS, UNKNOWN, (int) VOID_FTYPE_PV2SF_V4SF },
30861 /* SSE or 3DNow!A */
30862 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_sfence, "__builtin_ia32_sfence", IX86_BUILTIN_SFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30863 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_sse_movntq, "__builtin_ia32_movntq", IX86_BUILTIN_MOVNTQ, UNKNOWN, (int) VOID_FTYPE_PULONGLONG_ULONGLONG },
30865 /* SSE2 */
30866 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lfence, "__builtin_ia32_lfence", IX86_BUILTIN_LFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30867 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_mfence, 0, IX86_BUILTIN_MFENCE, UNKNOWN, (int) VOID_FTYPE_VOID },
30868 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storeupd, "__builtin_ia32_storeupd", IX86_BUILTIN_STOREUPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30869 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_storedquv16qi, "__builtin_ia32_storedqu", IX86_BUILTIN_STOREDQU, UNKNOWN, (int) VOID_FTYPE_PCHAR_V16QI },
30870 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2df, "__builtin_ia32_movntpd", IX86_BUILTIN_MOVNTPD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30871 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntv2di, "__builtin_ia32_movntdq", IX86_BUILTIN_MOVNTDQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI },
30872 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movntisi, "__builtin_ia32_movnti", IX86_BUILTIN_MOVNTI, UNKNOWN, (int) VOID_FTYPE_PINT_INT },
30873 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_movntidi, "__builtin_ia32_movnti64", IX86_BUILTIN_MOVNTI64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG },
30874 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadupd, "__builtin_ia32_loadupd", IX86_BUILTIN_LOADUPD, UNKNOWN, (int) V2DF_FTYPE_PCDOUBLE },
30875 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loaddquv16qi, "__builtin_ia32_loaddqu", IX86_BUILTIN_LOADDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30877 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadhpd_exp, "__builtin_ia32_loadhpd", IX86_BUILTIN_LOADHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30878 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_loadlpd_exp, "__builtin_ia32_loadlpd", IX86_BUILTIN_LOADLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_PCDOUBLE },
30880 /* SSE3 */
30881 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_lddqu, "__builtin_ia32_lddqu", IX86_BUILTIN_LDDQU, UNKNOWN, (int) V16QI_FTYPE_PCCHAR },
30883 /* SSE4.1 */
30884 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_movntdqa, "__builtin_ia32_movntdqa", IX86_BUILTIN_MOVNTDQA, UNKNOWN, (int) V2DI_FTYPE_PV2DI },
30886 /* SSE4A */
30887 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv2df, "__builtin_ia32_movntsd", IX86_BUILTIN_MOVNTSD, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V2DF },
30888 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_vmmovntv4sf, "__builtin_ia32_movntss", IX86_BUILTIN_MOVNTSS, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V4SF },
30890 /* AVX */
30891 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroall, "__builtin_ia32_vzeroall", IX86_BUILTIN_VZEROALL, UNKNOWN, (int) VOID_FTYPE_VOID },
30892 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vzeroupper, "__builtin_ia32_vzeroupper", IX86_BUILTIN_VZEROUPPER, UNKNOWN, (int) VOID_FTYPE_VOID },
30894 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4sf, "__builtin_ia32_vbroadcastss", IX86_BUILTIN_VBROADCASTSS, UNKNOWN, (int) V4SF_FTYPE_PCFLOAT },
30895 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv4df, "__builtin_ia32_vbroadcastsd256", IX86_BUILTIN_VBROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30896 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_dupv8sf, "__builtin_ia32_vbroadcastss256", IX86_BUILTIN_VBROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30897 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v4df, "__builtin_ia32_vbroadcastf128_pd256", IX86_BUILTIN_VBROADCASTPD256, UNKNOWN, (int) V4DF_FTYPE_PCV2DF },
30898 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vbroadcastf128_v8sf, "__builtin_ia32_vbroadcastf128_ps256", IX86_BUILTIN_VBROADCASTPS256, UNKNOWN, (int) V8SF_FTYPE_PCV4SF },
30900 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadupd256, "__builtin_ia32_loadupd256", IX86_BUILTIN_LOADUPD256, UNKNOWN, (int) V4DF_FTYPE_PCDOUBLE },
30901 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loadups256, "__builtin_ia32_loadups256", IX86_BUILTIN_LOADUPS256, UNKNOWN, (int) V8SF_FTYPE_PCFLOAT },
30902 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeupd256, "__builtin_ia32_storeupd256", IX86_BUILTIN_STOREUPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30903 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storeups256, "__builtin_ia32_storeups256", IX86_BUILTIN_STOREUPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30904 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_loaddquv32qi, "__builtin_ia32_loaddqu256", IX86_BUILTIN_LOADDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30905 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_storedquv32qi, "__builtin_ia32_storedqu256", IX86_BUILTIN_STOREDQU256, UNKNOWN, (int) VOID_FTYPE_PCHAR_V32QI },
30906 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_lddqu256, "__builtin_ia32_lddqu256", IX86_BUILTIN_LDDQU256, UNKNOWN, (int) V32QI_FTYPE_PCCHAR },
30908 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4di, "__builtin_ia32_movntdq256", IX86_BUILTIN_MOVNTDQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI },
30909 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv4df, "__builtin_ia32_movntpd256", IX86_BUILTIN_MOVNTPD256, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V4DF },
30910 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movntv8sf, "__builtin_ia32_movntps256", IX86_BUILTIN_MOVNTPS256, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V8SF },
30912 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd, "__builtin_ia32_maskloadpd", IX86_BUILTIN_MASKLOADPD, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DI },
30913 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps, "__builtin_ia32_maskloadps", IX86_BUILTIN_MASKLOADPS, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SI },
30914 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadpd256, "__builtin_ia32_maskloadpd256", IX86_BUILTIN_MASKLOADPD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DI },
30915 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskloadps256, "__builtin_ia32_maskloadps256", IX86_BUILTIN_MASKLOADPS256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SI },
30916 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd, "__builtin_ia32_maskstorepd", IX86_BUILTIN_MASKSTOREPD, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DI_V2DF },
30917 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps, "__builtin_ia32_maskstoreps", IX86_BUILTIN_MASKSTOREPS, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SI_V4SF },
30918 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstorepd256, "__builtin_ia32_maskstorepd256", IX86_BUILTIN_MASKSTOREPD256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DI_V4DF },
30919 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_maskstoreps256, "__builtin_ia32_maskstoreps256", IX86_BUILTIN_MASKSTOREPS256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SI_V8SF },
30921 /* AVX2 */
30922 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_movntdqa, "__builtin_ia32_movntdqa256", IX86_BUILTIN_MOVNTDQA256, UNKNOWN, (int) V4DI_FTYPE_PV4DI },
30923 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd, "__builtin_ia32_maskloadd", IX86_BUILTIN_MASKLOADD, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI },
30924 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq, "__builtin_ia32_maskloadq", IX86_BUILTIN_MASKLOADQ, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI },
30925 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadd256, "__builtin_ia32_maskloadd256", IX86_BUILTIN_MASKLOADD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI },
30926 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskloadq256, "__builtin_ia32_maskloadq256", IX86_BUILTIN_MASKLOADQ256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI },
30927 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored, "__builtin_ia32_maskstored", IX86_BUILTIN_MASKSTORED, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_V4SI },
30928 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq, "__builtin_ia32_maskstoreq", IX86_BUILTIN_MASKSTOREQ, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_V2DI },
30929 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstored256, "__builtin_ia32_maskstored256", IX86_BUILTIN_MASKSTORED256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_V8SI },
30930 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_maskstoreq256, "__builtin_ia32_maskstoreq256", IX86_BUILTIN_MASKSTOREQ256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_V4DI },
30932 /* AVX512F */
30933 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16sf_mask, "__builtin_ia32_compressstoresf512_mask", IX86_BUILTIN_COMPRESSPSSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30934 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev16si_mask, "__builtin_ia32_compressstoresi512_mask", IX86_BUILTIN_PCOMPRESSDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30935 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8df_mask, "__builtin_ia32_compressstoredf512_mask", IX86_BUILTIN_COMPRESSPDSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30936 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressstorev8di_mask, "__builtin_ia32_compressstoredi512_mask", IX86_BUILTIN_PCOMPRESSQSTORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30937 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandloadsf512_mask", IX86_BUILTIN_EXPANDPSLOAD512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30938 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandloadsf512_maskz", IX86_BUILTIN_EXPANDPSLOAD512Z, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30939 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandloadsi512_mask", IX86_BUILTIN_PEXPANDDLOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30940 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandloadsi512_maskz", IX86_BUILTIN_PEXPANDDLOAD512Z, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30941 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expandloaddf512_mask", IX86_BUILTIN_EXPANDPDLOAD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30942 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expandloaddf512_maskz", IX86_BUILTIN_EXPANDPDLOAD512Z, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30943 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expandloaddi512_mask", IX86_BUILTIN_PEXPANDQLOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30944 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expandloaddi512_maskz", IX86_BUILTIN_PEXPANDQLOAD512Z, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30945 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv16si_mask, "__builtin_ia32_loaddqusi512_mask", IX86_BUILTIN_LOADDQUSI512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30946 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loaddquv8di_mask, "__builtin_ia32_loaddqudi512_mask", IX86_BUILTIN_LOADDQUDI512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30947 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadupd512_mask, "__builtin_ia32_loadupd512_mask", IX86_BUILTIN_LOADUPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30948 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadups512_mask, "__builtin_ia32_loadups512_mask", IX86_BUILTIN_LOADUPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30949 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_loadaps512_mask", IX86_BUILTIN_LOADAPS512, UNKNOWN, (int) V16SF_FTYPE_PCV16SF_V16SF_HI },
30950 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32load512_mask", IX86_BUILTIN_MOVDQA32LOAD512, UNKNOWN, (int) V16SI_FTYPE_PCV16SI_V16SI_HI },
30951 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_loadapd512_mask", IX86_BUILTIN_LOADAPD512, UNKNOWN, (int) V8DF_FTYPE_PCV8DF_V8DF_QI },
30952 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64load512_mask", IX86_BUILTIN_MOVDQA64LOAD512, UNKNOWN, (int) V8DI_FTYPE_PCV8DI_V8DI_QI },
30953 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv16sf, "__builtin_ia32_movntps512", IX86_BUILTIN_MOVNTPS512, UNKNOWN, (int) VOID_FTYPE_PFLOAT_V16SF },
30954 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8df, "__builtin_ia32_movntpd512", IX86_BUILTIN_MOVNTPD512, UNKNOWN, (int) VOID_FTYPE_PDOUBLE_V8DF },
30955 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntv8di, "__builtin_ia32_movntdq512", IX86_BUILTIN_MOVNTDQ512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI },
30956 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movntdqa, "__builtin_ia32_movntdqa512", IX86_BUILTIN_MOVNTDQA512, UNKNOWN, (int) V8DI_FTYPE_PV8DI },
30957 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv16si_mask, "__builtin_ia32_storedqusi512_mask", IX86_BUILTIN_STOREDQUSI512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30958 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storedquv8di_mask, "__builtin_ia32_storedqudi512_mask", IX86_BUILTIN_STOREDQUDI512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30959 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeupd512_mask, "__builtin_ia32_storeupd512_mask", IX86_BUILTIN_STOREUPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30960 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask_store, "__builtin_ia32_pmovusqd512mem_mask", IX86_BUILTIN_PMOVUSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30961 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask_store, "__builtin_ia32_pmovsqd512mem_mask", IX86_BUILTIN_PMOVSQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30962 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask_store, "__builtin_ia32_pmovqd512mem_mask", IX86_BUILTIN_PMOVQD512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8DI_QI },
30963 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovusqw512mem_mask", IX86_BUILTIN_PMOVUSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30964 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovsqw512mem_mask", IX86_BUILTIN_PMOVSQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30965 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask_store, "__builtin_ia32_pmovqw512mem_mask", IX86_BUILTIN_PMOVQW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8DI_QI },
30966 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovusdw512mem_mask", IX86_BUILTIN_PMOVUSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30967 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovsdw512mem_mask", IX86_BUILTIN_PMOVSDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30968 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask_store, "__builtin_ia32_pmovdw512mem_mask", IX86_BUILTIN_PMOVDW512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16SI_HI },
30969 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovqb512mem_mask", IX86_BUILTIN_PMOVQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30970 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovusqb512mem_mask", IX86_BUILTIN_PMOVUSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30971 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask_store, "__builtin_ia32_pmovsqb512mem_mask", IX86_BUILTIN_PMOVSQB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8DI_QI },
30972 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovusdb512mem_mask", IX86_BUILTIN_PMOVUSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30973 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovsdb512mem_mask", IX86_BUILTIN_PMOVSDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30974 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask_store, "__builtin_ia32_pmovdb512mem_mask", IX86_BUILTIN_PMOVDB512_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16SI_HI },
30975 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storeups512_mask, "__builtin_ia32_storeups512_mask", IX86_BUILTIN_STOREUPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30976 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16sf_mask, "__builtin_ia32_storeaps512_mask", IX86_BUILTIN_STOREAPS512, UNKNOWN, (int) VOID_FTYPE_PV16SF_V16SF_HI },
30977 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev16si_mask, "__builtin_ia32_movdqa32store512_mask", IX86_BUILTIN_MOVDQA32STORE512, UNKNOWN, (int) VOID_FTYPE_PV16SI_V16SI_HI },
30978 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8df_mask, "__builtin_ia32_storeapd512_mask", IX86_BUILTIN_STOREAPD512, UNKNOWN, (int) VOID_FTYPE_PV8DF_V8DF_QI },
30979 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_storev8di_mask, "__builtin_ia32_movdqa64store512_mask", IX86_BUILTIN_MOVDQA64STORE512, UNKNOWN, (int) VOID_FTYPE_PV8DI_V8DI_QI },
30981 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_llwpcb, "__builtin_ia32_llwpcb", IX86_BUILTIN_LLWPCB, UNKNOWN, (int) VOID_FTYPE_PVOID },
30982 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_slwpcb, "__builtin_ia32_slwpcb", IX86_BUILTIN_SLWPCB, UNKNOWN, (int) PVOID_FTYPE_VOID },
30983 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvalsi3, "__builtin_ia32_lwpval32", IX86_BUILTIN_LWPVAL32, UNKNOWN, (int) VOID_FTYPE_UINT_UINT_UINT },
30984 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpvaldi3, "__builtin_ia32_lwpval64", IX86_BUILTIN_LWPVAL64, UNKNOWN, (int) VOID_FTYPE_UINT64_UINT_UINT },
30985 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinssi3, "__builtin_ia32_lwpins32", IX86_BUILTIN_LWPINS32, UNKNOWN, (int) UCHAR_FTYPE_UINT_UINT_UINT },
30986 { OPTION_MASK_ISA_LWP, CODE_FOR_lwp_lwpinsdi3, "__builtin_ia32_lwpins64", IX86_BUILTIN_LWPINS64, UNKNOWN, (int) UCHAR_FTYPE_UINT64_UINT_UINT },
30988 /* FSGSBASE */
30989 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasesi, "__builtin_ia32_rdfsbase32", IX86_BUILTIN_RDFSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30990 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdfsbasedi, "__builtin_ia32_rdfsbase64", IX86_BUILTIN_RDFSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30991 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasesi, "__builtin_ia32_rdgsbase32", IX86_BUILTIN_RDGSBASE32, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
30992 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_rdgsbasedi, "__builtin_ia32_rdgsbase64", IX86_BUILTIN_RDGSBASE64, UNKNOWN, (int) UINT64_FTYPE_VOID },
30993 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasesi, "__builtin_ia32_wrfsbase32", IX86_BUILTIN_WRFSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30994 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrfsbasedi, "__builtin_ia32_wrfsbase64", IX86_BUILTIN_WRFSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30995 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasesi, "__builtin_ia32_wrgsbase32", IX86_BUILTIN_WRGSBASE32, UNKNOWN, (int) VOID_FTYPE_UNSIGNED },
30996 { OPTION_MASK_ISA_FSGSBASE | OPTION_MASK_ISA_64BIT, CODE_FOR_wrgsbasedi, "__builtin_ia32_wrgsbase64", IX86_BUILTIN_WRGSBASE64, UNKNOWN, (int) VOID_FTYPE_UINT64 },
30998 /* RTM */
30999 { OPTION_MASK_ISA_RTM, CODE_FOR_xbegin, "__builtin_ia32_xbegin", IX86_BUILTIN_XBEGIN, UNKNOWN, (int) UNSIGNED_FTYPE_VOID },
31000 { OPTION_MASK_ISA_RTM, CODE_FOR_xend, "__builtin_ia32_xend", IX86_BUILTIN_XEND, UNKNOWN, (int) VOID_FTYPE_VOID },
31001 { OPTION_MASK_ISA_RTM, CODE_FOR_xtest, "__builtin_ia32_xtest", IX86_BUILTIN_XTEST, UNKNOWN, (int) INT_FTYPE_VOID },
31003 /* AVX512BW */
31004 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_loaddquhi512_mask", IX86_BUILTIN_LOADDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_PCV32HI_V32HI_SI },
31005 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_loaddquqi512_mask", IX86_BUILTIN_LOADDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_PCV64QI_V64QI_DI },
31006 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv32hi_mask, "__builtin_ia32_storedquhi512_mask", IX86_BUILTIN_STOREDQUHI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV32HI_V32HI_SI },
31007 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_storedquv64qi_mask, "__builtin_ia32_storedquqi512_mask", IX86_BUILTIN_STOREDQUQI512_MASK, UNKNOWN, (int) VOID_FTYPE_PV64QI_V64QI_DI },
31009 /* AVX512VL */
31010 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_loaddquhi256_mask", IX86_BUILTIN_LOADDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_PCV16HI_V16HI_HI },
31011 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_loaddquhi128_mask", IX86_BUILTIN_LOADDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_PCV8HI_V8HI_QI },
31012 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_loaddquqi256_mask", IX86_BUILTIN_LOADDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_PCV32QI_V32QI_SI },
31013 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_loaddquqi128_mask", IX86_BUILTIN_LOADDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_PCV16QI_V16QI_HI },
31014 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64load256_mask", IX86_BUILTIN_MOVDQA64LOAD256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31015 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64load128_mask", IX86_BUILTIN_MOVDQA64LOAD128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31016 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32load256_mask", IX86_BUILTIN_MOVDQA32LOAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31017 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32load128_mask", IX86_BUILTIN_MOVDQA32LOAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31018 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4di_mask, "__builtin_ia32_movdqa64store256_mask", IX86_BUILTIN_MOVDQA64STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
31019 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2di_mask, "__builtin_ia32_movdqa64store128_mask", IX86_BUILTIN_MOVDQA64STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
31020 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8si_mask, "__builtin_ia32_movdqa32store256_mask", IX86_BUILTIN_MOVDQA32STORE256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
31021 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4si_mask, "__builtin_ia32_movdqa32store128_mask", IX86_BUILTIN_MOVDQA32STORE128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
31022 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_loadapd256_mask", IX86_BUILTIN_LOADAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31023 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_loadapd128_mask", IX86_BUILTIN_LOADAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31024 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_loadaps256_mask", IX86_BUILTIN_LOADAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31025 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_loadaps128_mask", IX86_BUILTIN_LOADAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31026 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4df_mask, "__builtin_ia32_storeapd256_mask", IX86_BUILTIN_STOREAPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
31027 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev2df_mask, "__builtin_ia32_storeapd128_mask", IX86_BUILTIN_STOREAPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
31028 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev8sf_mask, "__builtin_ia32_storeaps256_mask", IX86_BUILTIN_STOREAPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
31029 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storev4sf_mask, "__builtin_ia32_storeaps128_mask", IX86_BUILTIN_STOREAPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
31030 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadupd256_mask, "__builtin_ia32_loadupd256_mask", IX86_BUILTIN_LOADUPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31031 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loadupd_mask, "__builtin_ia32_loadupd128_mask", IX86_BUILTIN_LOADUPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31032 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loadups256_mask, "__builtin_ia32_loadups256_mask", IX86_BUILTIN_LOADUPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31033 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_loadups_mask, "__builtin_ia32_loadups128_mask", IX86_BUILTIN_LOADUPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31034 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd256_mask, "__builtin_ia32_storeupd256_mask", IX86_BUILTIN_STOREUPD256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
31035 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeupd_mask, "__builtin_ia32_storeupd128_mask", IX86_BUILTIN_STOREUPD128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
31036 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups256_mask, "__builtin_ia32_storeups256_mask", IX86_BUILTIN_STOREUPS256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
31037 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storeups_mask, "__builtin_ia32_storeups128_mask", IX86_BUILTIN_STOREUPS128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
31038 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv4di_mask, "__builtin_ia32_loaddqudi256_mask", IX86_BUILTIN_LOADDQUDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31039 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv2di_mask, "__builtin_ia32_loaddqudi128_mask", IX86_BUILTIN_LOADDQUDI128_MASK, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31040 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv8si_mask, "__builtin_ia32_loaddqusi256_mask", IX86_BUILTIN_LOADDQUSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31041 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv4si_mask, "__builtin_ia32_loaddqusi128_mask", IX86_BUILTIN_LOADDQUSI128_MASK, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31042 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4di_mask, "__builtin_ia32_storedqudi256_mask", IX86_BUILTIN_STOREDQUDI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
31043 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv2di_mask, "__builtin_ia32_storedqudi128_mask", IX86_BUILTIN_STOREDQUDI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
31044 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8si_mask, "__builtin_ia32_storedqusi256_mask", IX86_BUILTIN_STOREDQUSI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
31045 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv4si_mask, "__builtin_ia32_storedqusi128_mask", IX86_BUILTIN_STOREDQUSI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
31046 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16hi_mask, "__builtin_ia32_storedquhi256_mask", IX86_BUILTIN_STOREDQUHI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV16HI_V16HI_HI },
31047 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv8hi_mask, "__builtin_ia32_storedquhi128_mask", IX86_BUILTIN_STOREDQUHI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8HI_QI },
31048 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv32qi_mask, "__builtin_ia32_storedquqi256_mask", IX86_BUILTIN_STOREDQUQI256_MASK, UNKNOWN, (int) VOID_FTYPE_PV32QI_V32QI_SI },
31049 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_storedquv16qi_mask, "__builtin_ia32_storedquqi128_mask", IX86_BUILTIN_STOREDQUQI128_MASK, UNKNOWN, (int) VOID_FTYPE_PV16QI_V16QI_HI },
31050 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4df_mask, "__builtin_ia32_compressstoredf256_mask", IX86_BUILTIN_COMPRESSPDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DF_V4DF_QI },
31051 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2df_mask, "__builtin_ia32_compressstoredf128_mask", IX86_BUILTIN_COMPRESSPDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DF_V2DF_QI },
31052 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8sf_mask, "__builtin_ia32_compressstoresf256_mask", IX86_BUILTIN_COMPRESSPSSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SF_V8SF_QI },
31053 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4sf_mask, "__builtin_ia32_compressstoresf128_mask", IX86_BUILTIN_COMPRESSPSSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SF_V4SF_QI },
31054 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4di_mask, "__builtin_ia32_compressstoredi256_mask", IX86_BUILTIN_PCOMPRESSQSTORE256, UNKNOWN, (int) VOID_FTYPE_PV4DI_V4DI_QI },
31055 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev2di_mask, "__builtin_ia32_compressstoredi128_mask", IX86_BUILTIN_PCOMPRESSQSTORE128, UNKNOWN, (int) VOID_FTYPE_PV2DI_V2DI_QI },
31056 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev8si_mask, "__builtin_ia32_compressstoresi256_mask", IX86_BUILTIN_PCOMPRESSDSTORE256, UNKNOWN, (int) VOID_FTYPE_PV8SI_V8SI_QI },
31057 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressstorev4si_mask, "__builtin_ia32_compressstoresi128_mask", IX86_BUILTIN_PCOMPRESSDSTORE128, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4SI_QI },
31058 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expandloaddf256_mask", IX86_BUILTIN_EXPANDPDLOAD256, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31059 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expandloaddf128_mask", IX86_BUILTIN_EXPANDPDLOAD128, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31060 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandloadsf256_mask", IX86_BUILTIN_EXPANDPSLOAD256, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31061 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandloadsf128_mask", IX86_BUILTIN_EXPANDPSLOAD128, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31062 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expandloaddi256_mask", IX86_BUILTIN_PEXPANDQLOAD256, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31063 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expandloaddi128_mask", IX86_BUILTIN_PEXPANDQLOAD128, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31064 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandloadsi256_mask", IX86_BUILTIN_PEXPANDDLOAD256, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31065 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandloadsi128_mask", IX86_BUILTIN_PEXPANDDLOAD128, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31066 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expandloaddf256_maskz", IX86_BUILTIN_EXPANDPDLOAD256Z, UNKNOWN, (int) V4DF_FTYPE_PCV4DF_V4DF_QI },
31067 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expandloaddf128_maskz", IX86_BUILTIN_EXPANDPDLOAD128Z, UNKNOWN, (int) V2DF_FTYPE_PCV2DF_V2DF_QI },
31068 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandloadsf256_maskz", IX86_BUILTIN_EXPANDPSLOAD256Z, UNKNOWN, (int) V8SF_FTYPE_PCV8SF_V8SF_QI },
31069 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandloadsf128_maskz", IX86_BUILTIN_EXPANDPSLOAD128Z, UNKNOWN, (int) V4SF_FTYPE_PCV4SF_V4SF_QI },
31070 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expandloaddi256_maskz", IX86_BUILTIN_PEXPANDQLOAD256Z, UNKNOWN, (int) V4DI_FTYPE_PCV4DI_V4DI_QI },
31071 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expandloaddi128_maskz", IX86_BUILTIN_PEXPANDQLOAD128Z, UNKNOWN, (int) V2DI_FTYPE_PCV2DI_V2DI_QI },
31072 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandloadsi256_maskz", IX86_BUILTIN_PEXPANDDLOAD256Z, UNKNOWN, (int) V8SI_FTYPE_PCV8SI_V8SI_QI },
31073 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandloadsi128_maskz", IX86_BUILTIN_PEXPANDDLOAD128Z, UNKNOWN, (int) V4SI_FTYPE_PCV4SI_V4SI_QI },
31074 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask_store, "__builtin_ia32_pmovqd256mem_mask", IX86_BUILTIN_PMOVQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
31075 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask_store, "__builtin_ia32_pmovqd128mem_mask", IX86_BUILTIN_PMOVQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
31076 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask_store, "__builtin_ia32_pmovsqd256mem_mask", IX86_BUILTIN_PMOVSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
31077 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask_store, "__builtin_ia32_pmovsqd128mem_mask", IX86_BUILTIN_PMOVSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
31078 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask_store, "__builtin_ia32_pmovusqd256mem_mask", IX86_BUILTIN_PMOVUSQD256_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V4DI_QI },
31079 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask_store, "__builtin_ia32_pmovusqd128mem_mask", IX86_BUILTIN_PMOVUSQD128_MEM, UNKNOWN, (int) VOID_FTYPE_PV4SI_V2DI_QI },
31080 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovqw256mem_mask", IX86_BUILTIN_PMOVQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
31081 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovqw128mem_mask", IX86_BUILTIN_PMOVQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
31082 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovsqw256mem_mask", IX86_BUILTIN_PMOVSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
31083 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovsqw128mem_mask", IX86_BUILTIN_PMOVSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
31084 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask_store, "__builtin_ia32_pmovusqw256mem_mask", IX86_BUILTIN_PMOVUSQW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4DI_QI },
31085 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask_store, "__builtin_ia32_pmovusqw128mem_mask", IX86_BUILTIN_PMOVUSQW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V2DI_QI },
31086 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovqb256mem_mask", IX86_BUILTIN_PMOVQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
31087 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovqb128mem_mask", IX86_BUILTIN_PMOVQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
31088 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovsqb256mem_mask", IX86_BUILTIN_PMOVSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
31089 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovsqb128mem_mask", IX86_BUILTIN_PMOVSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
31090 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask_store, "__builtin_ia32_pmovusqb256mem_mask", IX86_BUILTIN_PMOVUSQB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4DI_QI },
31091 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask_store, "__builtin_ia32_pmovusqb128mem_mask", IX86_BUILTIN_PMOVUSQB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V2DI_QI },
31092 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovdb256mem_mask", IX86_BUILTIN_PMOVDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
31093 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovdb128mem_mask", IX86_BUILTIN_PMOVDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
31094 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovsdb256mem_mask", IX86_BUILTIN_PMOVSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
31095 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovsdb128mem_mask", IX86_BUILTIN_PMOVSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
31096 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask_store, "__builtin_ia32_pmovusdb256mem_mask", IX86_BUILTIN_PMOVUSDB256_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V8SI_QI },
31097 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask_store, "__builtin_ia32_pmovusdb128mem_mask", IX86_BUILTIN_PMOVUSDB128_MEM, UNKNOWN, (int) VOID_FTYPE_PV16QI_V4SI_QI },
31098 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovdw256mem_mask", IX86_BUILTIN_PMOVDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
31099 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovdw128mem_mask", IX86_BUILTIN_PMOVDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
31100 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovsdw256mem_mask", IX86_BUILTIN_PMOVSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
31101 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovsdw128mem_mask", IX86_BUILTIN_PMOVSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
31102 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask_store, "__builtin_ia32_pmovusdw256mem_mask", IX86_BUILTIN_PMOVUSDW256_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V8SI_QI },
31103 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask_store, "__builtin_ia32_pmovusdw128mem_mask", IX86_BUILTIN_PMOVUSDW128_MEM, UNKNOWN, (int) VOID_FTYPE_PV8HI_V4SI_QI },
31105 /* PCOMMIT. */
31106 { OPTION_MASK_ISA_PCOMMIT, CODE_FOR_pcommit, "__builtin_ia32_pcommit", IX86_BUILTIN_PCOMMIT, UNKNOWN, (int) VOID_FTYPE_VOID },
31107 };
31109 /* Builtins with variable number of arguments. */
31111 {
31112 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
31113 { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
31114 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
31115 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
31116 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
31117 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
31118 { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
31120 /* MMX */
31121 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31122 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31123 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31124 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31125 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31126 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31128 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31129 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31130 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31131 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31132 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31133 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31134 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31135 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31137 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31138 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31140 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31141 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_andnotv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31142 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31143 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31145 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31146 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31147 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31148 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31149 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31150 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31152 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31153 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31154 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckhdq, "__builtin_ia32_punpckhdq", IX86_BUILTIN_PUNPCKHDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31155 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklbw, "__builtin_ia32_punpcklbw", IX86_BUILTIN_PUNPCKLBW, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31156 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpcklwd, "__builtin_ia32_punpcklwd", IX86_BUILTIN_PUNPCKLWD, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI},
31157 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_punpckldq, "__builtin_ia32_punpckldq", IX86_BUILTIN_PUNPCKLDQ, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI},
31159 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packsswb, "__builtin_ia32_packsswb", IX86_BUILTIN_PACKSSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
31160 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packssdw, "__builtin_ia32_packssdw", IX86_BUILTIN_PACKSSDW, UNKNOWN, (int) V4HI_FTYPE_V2SI_V2SI },
31161 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_packuswb, "__builtin_ia32_packuswb", IX86_BUILTIN_PACKUSWB, UNKNOWN, (int) V8QI_FTYPE_V4HI_V4HI },
31163 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_pmaddwd, "__builtin_ia32_pmaddwd", IX86_BUILTIN_PMADDWD, UNKNOWN, (int) V2SI_FTYPE_V4HI_V4HI },
31165 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllwi", IX86_BUILTIN_PSLLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31166 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslldi", IX86_BUILTIN_PSLLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31167 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllqi", IX86_BUILTIN_PSLLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31168 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv4hi3, "__builtin_ia32_psllw", IX86_BUILTIN_PSLLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31169 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv2si3, "__builtin_ia32_pslld", IX86_BUILTIN_PSLLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31170 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashlv1di3, "__builtin_ia32_psllq", IX86_BUILTIN_PSLLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31172 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlwi", IX86_BUILTIN_PSRLWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31173 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrldi", IX86_BUILTIN_PSRLDI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31174 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlqi", IX86_BUILTIN_PSRLQI, UNKNOWN, (int) V1DI_FTYPE_V1DI_SI_COUNT },
31175 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv4hi3, "__builtin_ia32_psrlw", IX86_BUILTIN_PSRLW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31176 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv2si3, "__builtin_ia32_psrld", IX86_BUILTIN_PSRLD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31177 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_lshrv1di3, "__builtin_ia32_psrlq", IX86_BUILTIN_PSRLQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_COUNT },
31179 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psrawi", IX86_BUILTIN_PSRAWI, UNKNOWN, (int) V4HI_FTYPE_V4HI_SI_COUNT },
31180 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psradi", IX86_BUILTIN_PSRADI, UNKNOWN, (int) V2SI_FTYPE_V2SI_SI_COUNT },
31181 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv4hi3, "__builtin_ia32_psraw", IX86_BUILTIN_PSRAW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI_COUNT },
31182 { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_ashrv2si3, "__builtin_ia32_psrad", IX86_BUILTIN_PSRAD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI_COUNT },
31184 /* 3DNow! */
31185 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pf2id, "__builtin_ia32_pf2id", IX86_BUILTIN_PF2ID, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31186 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_floatv2si2, "__builtin_ia32_pi2fd", IX86_BUILTIN_PI2FD, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31187 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpv2sf2, "__builtin_ia32_pfrcp", IX86_BUILTIN_PFRCP, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31188 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqrtv2sf2, "__builtin_ia32_pfrsqrt", IX86_BUILTIN_PFRSQRT, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31190 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgusb", IX86_BUILTIN_PAVGUSB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31191 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_haddv2sf3, "__builtin_ia32_pfacc", IX86_BUILTIN_PFACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31192 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_addv2sf3, "__builtin_ia32_pfadd", IX86_BUILTIN_PFADD, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31193 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_eqv2sf3, "__builtin_ia32_pfcmpeq", IX86_BUILTIN_PFCMPEQ, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31194 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gev2sf3, "__builtin_ia32_pfcmpge", IX86_BUILTIN_PFCMPGE, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31195 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_gtv2sf3, "__builtin_ia32_pfcmpgt", IX86_BUILTIN_PFCMPGT, UNKNOWN, (int) V2SI_FTYPE_V2SF_V2SF },
31196 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_smaxv2sf3, "__builtin_ia32_pfmax", IX86_BUILTIN_PFMAX, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31197 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_sminv2sf3, "__builtin_ia32_pfmin", IX86_BUILTIN_PFMIN, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31198 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_mulv2sf3, "__builtin_ia32_pfmul", IX86_BUILTIN_PFMUL, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31199 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit1v2sf3, "__builtin_ia32_pfrcpit1", IX86_BUILTIN_PFRCPIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31200 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rcpit2v2sf3, "__builtin_ia32_pfrcpit2", IX86_BUILTIN_PFRCPIT2, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31201 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_rsqit1v2sf3, "__builtin_ia32_pfrsqit1", IX86_BUILTIN_PFRSQIT1, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31202 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subv2sf3, "__builtin_ia32_pfsub", IX86_BUILTIN_PFSUB, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31203 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_subrv2sf3, "__builtin_ia32_pfsubr", IX86_BUILTIN_PFSUBR, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31204 { OPTION_MASK_ISA_3DNOW, CODE_FOR_mmx_pmulhrwv4hi3, "__builtin_ia32_pmulhrw", IX86_BUILTIN_PMULHRW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31206 /* 3DNow!A */
31207 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pf2iw, "__builtin_ia32_pf2iw", IX86_BUILTIN_PF2IW, UNKNOWN, (int) V2SI_FTYPE_V2SF },
31208 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pi2fw, "__builtin_ia32_pi2fw", IX86_BUILTIN_PI2FW, UNKNOWN, (int) V2SF_FTYPE_V2SI },
31209 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2si2, "__builtin_ia32_pswapdsi", IX86_BUILTIN_PSWAPDSI, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31210 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pswapdv2sf2, "__builtin_ia32_pswapdsf", IX86_BUILTIN_PSWAPDSF, UNKNOWN, (int) V2SF_FTYPE_V2SF },
31211 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_hsubv2sf3, "__builtin_ia32_pfnacc", IX86_BUILTIN_PFNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31212 { OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_addsubv2sf3, "__builtin_ia32_pfpnacc", IX86_BUILTIN_PFPNACC, UNKNOWN, (int) V2SF_FTYPE_V2SF_V2SF },
31214 /* SSE */
31215 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movmskps, "__builtin_ia32_movmskps", IX86_BUILTIN_MOVMSKPS, UNKNOWN, (int) INT_FTYPE_V4SF },
31216 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_sqrtv4sf2, "__builtin_ia32_sqrtps", IX86_BUILTIN_SQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31217 { OPTION_MASK_ISA_SSE, CODE_FOR_sqrtv4sf2, "__builtin_ia32_sqrtps_nr", IX86_BUILTIN_SQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31218 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rsqrtv4sf2, "__builtin_ia32_rsqrtps", IX86_BUILTIN_RSQRTPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31219 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtv4sf2, "__builtin_ia32_rsqrtps_nr", IX86_BUILTIN_RSQRTPS_NR, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31220 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_rcpv4sf2, "__builtin_ia32_rcpps", IX86_BUILTIN_RCPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31221 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtps2pi, "__builtin_ia32_cvtps2pi", IX86_BUILTIN_CVTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31222 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtss2si, "__builtin_ia32_cvtss2si", IX86_BUILTIN_CVTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31223 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq, "__builtin_ia32_cvtss2si64", IX86_BUILTIN_CVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31224 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttps2pi, "__builtin_ia32_cvttps2pi", IX86_BUILTIN_CVTTPS2PI, UNKNOWN, (int) V2SI_FTYPE_V4SF },
31225 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvttss2si, "__builtin_ia32_cvttss2si", IX86_BUILTIN_CVTTSS2SI, UNKNOWN, (int) INT_FTYPE_V4SF },
31226 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq, "__builtin_ia32_cvttss2si64", IX86_BUILTIN_CVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF },
31228 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_shufps, "__builtin_ia32_shufps", IX86_BUILTIN_SHUFPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31230 { OPTION_MASK_ISA_SSE, CODE_FOR_addv4sf3, "__builtin_ia32_addps", IX86_BUILTIN_ADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31231 { OPTION_MASK_ISA_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31232 { OPTION_MASK_ISA_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31233 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31234 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31235 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31236 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31237 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31239 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31240 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31241 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31242 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31243 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31244 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31245 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31246 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31247 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31248 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF_SWAP },
31249 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF_SWAP},
31250 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31251 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, (int) V4SF_FTYPE_V4SF_V4SF },
31252 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, (int) V4SF_FTYPE_V4SF_V4SF },
31253 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, (int) V4SF_FTYPE_V4SF_V4SF },
31254 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31255 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, (int) V4SF_FTYPE_V4SF_V4SF },
31256 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, (int) V4SF_FTYPE_V4SF_V4SF },
31257 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, (int) V4SF_FTYPE_V4SF_V4SF },
31258 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, (int) V4SF_FTYPE_V4SF_V4SF },
31260 { OPTION_MASK_ISA_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31261 { OPTION_MASK_ISA_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31262 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31263 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31265 { OPTION_MASK_ISA_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31266 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_andnotv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31267 { OPTION_MASK_ISA_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31268 { OPTION_MASK_ISA_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31270 { OPTION_MASK_ISA_SSE, CODE_FOR_copysignv4sf3, "__builtin_ia32_copysignps", IX86_BUILTIN_CPYSGNPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31272 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31273 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movhlps_exp, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31274 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_movlhps_exp, "__builtin_ia32_movlhps", IX86_BUILTIN_MOVLHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31275 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_highv4sf, "__builtin_ia32_unpckhps", IX86_BUILTIN_UNPCKHPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31276 { OPTION_MASK_ISA_SSE, CODE_FOR_vec_interleave_lowv4sf, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31278 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtpi2ps, "__builtin_ia32_cvtpi2ps", IX86_BUILTIN_CVTPI2PS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2SI },
31279 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_cvtsi2ss, "__builtin_ia32_cvtsi2ss", IX86_BUILTIN_CVTSI2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_SI },
31280 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq, "__builtin_ia32_cvtsi642ss", IX86_BUILTIN_CVTSI642SS, UNKNOWN, V4SF_FTYPE_V4SF_DI },
31282 { OPTION_MASK_ISA_SSE, CODE_FOR_rsqrtsf2, "__builtin_ia32_rsqrtf", IX86_BUILTIN_RSQRTF, UNKNOWN, (int) FLOAT_FTYPE_FLOAT },
31284 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmsqrtv4sf2, "__builtin_ia32_sqrtss", IX86_BUILTIN_SQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31285 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrsqrtv4sf2, "__builtin_ia32_rsqrtss", IX86_BUILTIN_RSQRTSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31286 { OPTION_MASK_ISA_SSE, CODE_FOR_sse_vmrcpv4sf2, "__builtin_ia32_rcpss", IX86_BUILTIN_RCPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_VEC_MERGE },
31288 { OPTION_MASK_ISA_SSE, CODE_FOR_abstf2, 0, IX86_BUILTIN_FABSQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128 },
31289 { OPTION_MASK_ISA_SSE, CODE_FOR_copysigntf3, 0, IX86_BUILTIN_COPYSIGNQ, UNKNOWN, (int) FLOAT128_FTYPE_FLOAT128_FLOAT128 },
31291 /* SSE MMX or 3Dnow!A */
31292 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31293 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31294 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31296 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31297 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31298 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31299 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31301 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_psadbw, "__builtin_ia32_psadbw", IX86_BUILTIN_PSADBW, UNKNOWN, (int) V1DI_FTYPE_V8QI_V8QI },
31302 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pmovmskb, "__builtin_ia32_pmovmskb", IX86_BUILTIN_PMOVMSKB, UNKNOWN, (int) INT_FTYPE_V8QI },
31304 { OPTION_MASK_ISA_SSE | OPTION_MASK_ISA_3DNOW_A, CODE_FOR_mmx_pshufw, "__builtin_ia32_pshufw", IX86_BUILTIN_PSHUFW, UNKNOWN, (int) V4HI_FTYPE_V4HI_INT },
31306 /* SSE2 */
31307 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_shufpd, "__builtin_ia32_shufpd", IX86_BUILTIN_SHUFPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31309 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movmskpd, "__builtin_ia32_movmskpd", IX86_BUILTIN_MOVMSKPD, UNKNOWN, (int) INT_FTYPE_V2DF },
31310 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmovmskb, "__builtin_ia32_pmovmskb128", IX86_BUILTIN_PMOVMSKB128, UNKNOWN, (int) INT_FTYPE_V16QI },
31311 { OPTION_MASK_ISA_SSE2, CODE_FOR_sqrtv2df2, "__builtin_ia32_sqrtpd", IX86_BUILTIN_SQRTPD, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31312 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtdq2pd, "__builtin_ia32_cvtdq2pd", IX86_BUILTIN_CVTDQ2PD, UNKNOWN, (int) V2DF_FTYPE_V4SI },
31313 { OPTION_MASK_ISA_SSE2, CODE_FOR_floatv4siv4sf2, "__builtin_ia32_cvtdq2ps", IX86_BUILTIN_CVTDQ2PS, UNKNOWN, (int) V4SF_FTYPE_V4SI },
31315 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2dq, "__builtin_ia32_cvtpd2dq", IX86_BUILTIN_CVTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31316 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2pi, "__builtin_ia32_cvtpd2pi", IX86_BUILTIN_CVTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31317 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpd2ps, "__builtin_ia32_cvtpd2ps", IX86_BUILTIN_CVTPD2PS, UNKNOWN, (int) V4SF_FTYPE_V2DF },
31318 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2dq, "__builtin_ia32_cvttpd2dq", IX86_BUILTIN_CVTTPD2DQ, UNKNOWN, (int) V4SI_FTYPE_V2DF },
31319 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttpd2pi, "__builtin_ia32_cvttpd2pi", IX86_BUILTIN_CVTTPD2PI, UNKNOWN, (int) V2SI_FTYPE_V2DF },
31321 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtpi2pd, "__builtin_ia32_cvtpi2pd", IX86_BUILTIN_CVTPI2PD, UNKNOWN, (int) V2DF_FTYPE_V2SI },
31323 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2si, "__builtin_ia32_cvtsd2si", IX86_BUILTIN_CVTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31324 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvttsd2si, "__builtin_ia32_cvttsd2si", IX86_BUILTIN_CVTTSD2SI, UNKNOWN, (int) INT_FTYPE_V2DF },
31325 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq, "__builtin_ia32_cvtsd2si64", IX86_BUILTIN_CVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31326 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq, "__builtin_ia32_cvttsd2si64", IX86_BUILTIN_CVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF },
31328 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_fix_notruncv4sfv4si, "__builtin_ia32_cvtps2dq", IX86_BUILTIN_CVTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31329 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtps2pd, "__builtin_ia32_cvtps2pd", IX86_BUILTIN_CVTPS2PD, UNKNOWN, (int) V2DF_FTYPE_V4SF },
31330 { OPTION_MASK_ISA_SSE2, CODE_FOR_fix_truncv4sfv4si2, "__builtin_ia32_cvttps2dq", IX86_BUILTIN_CVTTPS2DQ, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31332 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2df3, "__builtin_ia32_addpd", IX86_BUILTIN_ADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31333 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31334 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31335 { OPTION_MASK_ISA_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31336 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31337 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31338 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31339 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31341 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31342 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31343 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31344 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31345 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP},
31346 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31347 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31348 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31349 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31350 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31351 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF_SWAP },
31352 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31353 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, (int) V2DF_FTYPE_V2DF_V2DF },
31354 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, (int) V2DF_FTYPE_V2DF_V2DF },
31355 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, (int) V2DF_FTYPE_V2DF_V2DF },
31356 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31357 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, (int) V2DF_FTYPE_V2DF_V2DF },
31358 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, (int) V2DF_FTYPE_V2DF_V2DF },
31359 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, (int) V2DF_FTYPE_V2DF_V2DF },
31360 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, (int) V2DF_FTYPE_V2DF_V2DF },
31362 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31363 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31364 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31365 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31367 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31368 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31369 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31370 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31372 { OPTION_MASK_ISA_SSE2, CODE_FOR_copysignv2df3, "__builtin_ia32_copysignpd", IX86_BUILTIN_CPYSGNPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31374 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31375 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2df, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31376 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2df, "__builtin_ia32_unpcklpd", IX86_BUILTIN_UNPCKLPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31378 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_pack_sfix_v2df, "__builtin_ia32_vec_pack_sfix", IX86_BUILTIN_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31380 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv16qi3, "__builtin_ia32_paddb128", IX86_BUILTIN_PADDB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31381 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv8hi3, "__builtin_ia32_paddw128", IX86_BUILTIN_PADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31382 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv4si3, "__builtin_ia32_paddd128", IX86_BUILTIN_PADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31383 { OPTION_MASK_ISA_SSE2, CODE_FOR_addv2di3, "__builtin_ia32_paddq128", IX86_BUILTIN_PADDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31384 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv16qi3, "__builtin_ia32_psubb128", IX86_BUILTIN_PSUBB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31385 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv8hi3, "__builtin_ia32_psubw128", IX86_BUILTIN_PSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31386 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31387 { OPTION_MASK_ISA_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31389 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31390 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31391 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31392 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31393 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31394 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31395 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31396 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31398 { OPTION_MASK_ISA_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31399 { OPTION_MASK_ISA_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI },
31401 { OPTION_MASK_ISA_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31402 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_andnotv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31403 { OPTION_MASK_ISA_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31404 { OPTION_MASK_ISA_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31406 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31407 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31409 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31410 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31411 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31412 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31413 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31414 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31416 { OPTION_MASK_ISA_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31417 { OPTION_MASK_ISA_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31418 { OPTION_MASK_ISA_SSE2, CODE_FOR_uminv16qi3, "__builtin_ia32_pminub128", IX86_BUILTIN_PMINUB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31419 { OPTION_MASK_ISA_SSE2, CODE_FOR_sminv8hi3, "__builtin_ia32_pminsw128", IX86_BUILTIN_PMINSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31421 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv16qi, "__builtin_ia32_punpckhbw128", IX86_BUILTIN_PUNPCKHBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31422 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv8hi, "__builtin_ia32_punpckhwd128", IX86_BUILTIN_PUNPCKHWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31423 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv4si, "__builtin_ia32_punpckhdq128", IX86_BUILTIN_PUNPCKHDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31424 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_highv2di, "__builtin_ia32_punpckhqdq128", IX86_BUILTIN_PUNPCKHQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31425 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv16qi, "__builtin_ia32_punpcklbw128", IX86_BUILTIN_PUNPCKLBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31426 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv8hi, "__builtin_ia32_punpcklwd128", IX86_BUILTIN_PUNPCKLWD128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31427 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv4si, "__builtin_ia32_punpckldq128", IX86_BUILTIN_PUNPCKLDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31428 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_interleave_lowv2di, "__builtin_ia32_punpcklqdq128", IX86_BUILTIN_PUNPCKLQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31430 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packsswb, "__builtin_ia32_packsswb128", IX86_BUILTIN_PACKSSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31431 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31432 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI },
31434 { OPTION_MASK_ISA_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31435 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_psadbw, "__builtin_ia32_psadbw128", IX86_BUILTIN_PSADBW128, UNKNOWN, (int) V2DI_FTYPE_V16QI_V16QI },
31437 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_umulv1siv1di3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, UNKNOWN, (int) V1DI_FTYPE_V2SI_V2SI },
31438 { OPTION_MASK_ISA_SSE2, CODE_FOR_vec_widen_umult_even_v4si, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31440 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pmaddwd, "__builtin_ia32_pmaddwd128", IX86_BUILTIN_PMADDWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI },
31442 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsi2sd, "__builtin_ia32_cvtsi2sd", IX86_BUILTIN_CVTSI2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_SI },
31443 { OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq, "__builtin_ia32_cvtsi642sd", IX86_BUILTIN_CVTSI642SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_DI },
31444 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtsd2ss, "__builtin_ia32_cvtsd2ss", IX86_BUILTIN_CVTSD2SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF },
31445 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_cvtss2sd, "__builtin_ia32_cvtss2sd", IX86_BUILTIN_CVTSS2SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF },
31447 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_ashlv1ti3, "__builtin_ia32_pslldqi128", IX86_BUILTIN_PSLLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31448 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllwi128", IX86_BUILTIN_PSLLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31449 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslldi128", IX86_BUILTIN_PSLLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31450 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllqi128", IX86_BUILTIN_PSLLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31451 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv8hi3, "__builtin_ia32_psllw128", IX86_BUILTIN_PSLLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31452 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv4si3, "__builtin_ia32_pslld128", IX86_BUILTIN_PSLLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31453 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashlv2di3, "__builtin_ia32_psllq128", IX86_BUILTIN_PSLLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31455 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_lshrv1ti3, "__builtin_ia32_psrldqi128", IX86_BUILTIN_PSRLDQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_CONVERT },
31456 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlwi128", IX86_BUILTIN_PSRLWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31457 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrldi128", IX86_BUILTIN_PSRLDI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31458 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlqi128", IX86_BUILTIN_PSRLQI128, UNKNOWN, (int) V2DI_FTYPE_V2DI_SI_COUNT },
31459 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv8hi3, "__builtin_ia32_psrlw128", IX86_BUILTIN_PSRLW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31460 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv4si3, "__builtin_ia32_psrld128", IX86_BUILTIN_PSRLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31461 { OPTION_MASK_ISA_SSE2, CODE_FOR_lshrv2di3, "__builtin_ia32_psrlq128", IX86_BUILTIN_PSRLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_COUNT },
31463 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psrawi128", IX86_BUILTIN_PSRAWI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_SI_COUNT },
31464 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psradi128", IX86_BUILTIN_PSRADI128, UNKNOWN, (int) V4SI_FTYPE_V4SI_SI_COUNT },
31465 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv8hi3, "__builtin_ia32_psraw128", IX86_BUILTIN_PSRAW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_COUNT },
31466 { OPTION_MASK_ISA_SSE2, CODE_FOR_ashrv4si3, "__builtin_ia32_psrad128", IX86_BUILTIN_PSRAD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_COUNT },
31468 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufd, "__builtin_ia32_pshufd", IX86_BUILTIN_PSHUFD, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT },
31469 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshuflw, "__builtin_ia32_pshuflw", IX86_BUILTIN_PSHUFLW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31470 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_pshufhw, "__builtin_ia32_pshufhw", IX86_BUILTIN_PSHUFHW, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT },
31472 { OPTION_MASK_ISA_SSE2, CODE_FOR_sse2_vmsqrtv2df2, "__builtin_ia32_sqrtsd", IX86_BUILTIN_SQRTSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_VEC_MERGE },
31474 { OPTION_MASK_ISA_SSE, CODE_FOR_sse2_movq128, "__builtin_ia32_movq128", IX86_BUILTIN_MOVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31476 /* SSE2 MMX */
31477 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_addv1di3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31478 { OPTION_MASK_ISA_SSE2, CODE_FOR_mmx_subv1di3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI },
31480 /* SSE3 */
31481 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movshdup, "__builtin_ia32_movshdup", IX86_BUILTIN_MOVSHDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF},
31482 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_movsldup, "__builtin_ia32_movsldup", IX86_BUILTIN_MOVSLDUP, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31484 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31485 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31486 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31487 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31488 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
31489 { OPTION_MASK_ISA_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
31491 /* SSSE3 */
31492 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv16qi2, "__builtin_ia32_pabsb128", IX86_BUILTIN_PABSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31493 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8qi2, "__builtin_ia32_pabsb", IX86_BUILTIN_PABSB, UNKNOWN, (int) V8QI_FTYPE_V8QI },
31494 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv8hi2, "__builtin_ia32_pabsw128", IX86_BUILTIN_PABSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31495 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4hi2, "__builtin_ia32_pabsw", IX86_BUILTIN_PABSW, UNKNOWN, (int) V4HI_FTYPE_V4HI },
31496 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv4si2, "__builtin_ia32_pabsd128", IX86_BUILTIN_PABSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31497 { OPTION_MASK_ISA_SSSE3, CODE_FOR_absv2si2, "__builtin_ia32_pabsd", IX86_BUILTIN_PABSD, UNKNOWN, (int) V2SI_FTYPE_V2SI },
31499 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv8hi3, "__builtin_ia32_phaddw128", IX86_BUILTIN_PHADDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31500 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddwv4hi3, "__builtin_ia32_phaddw", IX86_BUILTIN_PHADDW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31501 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv4si3, "__builtin_ia32_phaddd128", IX86_BUILTIN_PHADDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31502 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phadddv2si3, "__builtin_ia32_phaddd", IX86_BUILTIN_PHADDD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31503 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv8hi3, "__builtin_ia32_phaddsw128", IX86_BUILTIN_PHADDSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31504 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phaddswv4hi3, "__builtin_ia32_phaddsw", IX86_BUILTIN_PHADDSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31505 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv8hi3, "__builtin_ia32_phsubw128", IX86_BUILTIN_PHSUBW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31506 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubwv4hi3, "__builtin_ia32_phsubw", IX86_BUILTIN_PHSUBW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31507 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv4si3, "__builtin_ia32_phsubd128", IX86_BUILTIN_PHSUBD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31508 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubdv2si3, "__builtin_ia32_phsubd", IX86_BUILTIN_PHSUBD, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31509 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv8hi3, "__builtin_ia32_phsubsw128", IX86_BUILTIN_PHSUBSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31510 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_phsubswv4hi3, "__builtin_ia32_phsubsw", IX86_BUILTIN_PHSUBSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31511 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw128, "__builtin_ia32_pmaddubsw128", IX86_BUILTIN_PMADDUBSW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI },
31512 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmaddubsw, "__builtin_ia32_pmaddubsw", IX86_BUILTIN_PMADDUBSW, UNKNOWN, (int) V4HI_FTYPE_V8QI_V8QI },
31513 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv8hi3, "__builtin_ia32_pmulhrsw128", IX86_BUILTIN_PMULHRSW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31514 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pmulhrswv4hi3, "__builtin_ia32_pmulhrsw", IX86_BUILTIN_PMULHRSW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31515 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv16qi3, "__builtin_ia32_pshufb128", IX86_BUILTIN_PSHUFB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31516 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_pshufbv8qi3, "__builtin_ia32_pshufb", IX86_BUILTIN_PSHUFB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31517 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv16qi3, "__builtin_ia32_psignb128", IX86_BUILTIN_PSIGNB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31518 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8qi3, "__builtin_ia32_psignb", IX86_BUILTIN_PSIGNB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
31519 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv8hi3, "__builtin_ia32_psignw128", IX86_BUILTIN_PSIGNW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31520 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4hi3, "__builtin_ia32_psignw", IX86_BUILTIN_PSIGNW, UNKNOWN, (int) V4HI_FTYPE_V4HI_V4HI },
31521 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv4si3, "__builtin_ia32_psignd128", IX86_BUILTIN_PSIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31522 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_psignv2si3, "__builtin_ia32_psignd", IX86_BUILTIN_PSIGND, UNKNOWN, (int) V2SI_FTYPE_V2SI_V2SI },
31524 /* SSSE3. */
31525 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrti, "__builtin_ia32_palignr128", IX86_BUILTIN_PALIGNR128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_CONVERT },
31526 { OPTION_MASK_ISA_SSSE3, CODE_FOR_ssse3_palignrdi, "__builtin_ia32_palignr", IX86_BUILTIN_PALIGNR, UNKNOWN, (int) V1DI_FTYPE_V1DI_V1DI_INT_CONVERT },
31528 /* SSE4.1 */
31529 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendpd, "__builtin_ia32_blendpd", IX86_BUILTIN_BLENDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31530 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendps, "__builtin_ia32_blendps", IX86_BUILTIN_BLENDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31531 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvpd, "__builtin_ia32_blendvpd", IX86_BUILTIN_BLENDVPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF },
31532 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_blendvps, "__builtin_ia32_blendvps", IX86_BUILTIN_BLENDVPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF },
31533 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dppd, "__builtin_ia32_dppd", IX86_BUILTIN_DPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31534 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_dpps, "__builtin_ia32_dpps", IX86_BUILTIN_DPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31535 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_insertps, "__builtin_ia32_insertps128", IX86_BUILTIN_INSERTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31536 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mpsadbw, "__builtin_ia32_mpsadbw128", IX86_BUILTIN_MPSADBW128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_INT },
31537 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendvb, "__builtin_ia32_pblendvb128", IX86_BUILTIN_PBLENDVB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI },
31538 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_pblendw, "__builtin_ia32_pblendw128", IX86_BUILTIN_PBLENDW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_INT },
31540 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv8qiv8hi2, "__builtin_ia32_pmovsxbw128", IX86_BUILTIN_PMOVSXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31541 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4qiv4si2, "__builtin_ia32_pmovsxbd128", IX86_BUILTIN_PMOVSXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31542 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2qiv2di2, "__builtin_ia32_pmovsxbq128", IX86_BUILTIN_PMOVSXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31543 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv4hiv4si2, "__builtin_ia32_pmovsxwd128", IX86_BUILTIN_PMOVSXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31544 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2hiv2di2, "__builtin_ia32_pmovsxwq128", IX86_BUILTIN_PMOVSXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31545 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_sign_extendv2siv2di2, "__builtin_ia32_pmovsxdq128", IX86_BUILTIN_PMOVSXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31546 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv8qiv8hi2, "__builtin_ia32_pmovzxbw128", IX86_BUILTIN_PMOVZXBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI },
31547 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4qiv4si2, "__builtin_ia32_pmovzxbd128", IX86_BUILTIN_PMOVZXBD128, UNKNOWN, (int) V4SI_FTYPE_V16QI },
31548 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2qiv2di2, "__builtin_ia32_pmovzxbq128", IX86_BUILTIN_PMOVZXBQ128, UNKNOWN, (int) V2DI_FTYPE_V16QI },
31549 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv4hiv4si2, "__builtin_ia32_pmovzxwd128", IX86_BUILTIN_PMOVZXWD128, UNKNOWN, (int) V4SI_FTYPE_V8HI },
31550 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2hiv2di2, "__builtin_ia32_pmovzxwq128", IX86_BUILTIN_PMOVZXWQ128, UNKNOWN, (int) V2DI_FTYPE_V8HI },
31551 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_zero_extendv2siv2di2, "__builtin_ia32_pmovzxdq128", IX86_BUILTIN_PMOVZXDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI },
31552 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_phminposuw, "__builtin_ia32_phminposuw128", IX86_BUILTIN_PHMINPOSUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31554 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_packusdw, "__builtin_ia32_packusdw128", IX86_BUILTIN_PACKUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI },
31555 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_eqv2di3, "__builtin_ia32_pcmpeqq", IX86_BUILTIN_PCMPEQQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31556 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv16qi3, "__builtin_ia32_pmaxsb128", IX86_BUILTIN_PMAXSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31557 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_smaxv4si3, "__builtin_ia32_pmaxsd128", IX86_BUILTIN_PMAXSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31558 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv4si3, "__builtin_ia32_pmaxud128", IX86_BUILTIN_PMAXUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31559 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_umaxv8hi3, "__builtin_ia32_pmaxuw128", IX86_BUILTIN_PMAXUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31560 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv16qi3, "__builtin_ia32_pminsb128", IX86_BUILTIN_PMINSB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI },
31561 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sminv4si3, "__builtin_ia32_pminsd128", IX86_BUILTIN_PMINSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31562 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv4si3, "__builtin_ia32_pminud128", IX86_BUILTIN_PMINUD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31563 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_uminv8hi3, "__builtin_ia32_pminuw128", IX86_BUILTIN_PMINUW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI },
31564 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
31565 { OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31567 /* SSE4.1 */
31568 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31569 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31570 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31571 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundss, "__builtin_ia32_roundss", IX86_BUILTIN_ROUNDSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31573 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_floorpd", IX86_BUILTIN_FLOORPD, (enum rtx_code) ROUND_FLOOR, (int) V2DF_FTYPE_V2DF_ROUND },
31574 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_ceilpd", IX86_BUILTIN_CEILPD, (enum rtx_code) ROUND_CEIL, (int) V2DF_FTYPE_V2DF_ROUND },
31575 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_truncpd", IX86_BUILTIN_TRUNCPD, (enum rtx_code) ROUND_TRUNC, (int) V2DF_FTYPE_V2DF_ROUND },
31576 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_rintpd", IX86_BUILTIN_RINTPD, (enum rtx_code) ROUND_MXCSR, (int) V2DF_FTYPE_V2DF_ROUND },
31578 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_floorpd_vec_pack_sfix", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31579 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd_vec_pack_sfix, "__builtin_ia32_ceilpd_vec_pack_sfix", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V2DF_V2DF_ROUND },
31581 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2, "__builtin_ia32_roundpd_az", IX86_BUILTIN_ROUNDPD_AZ, UNKNOWN, (int) V2DF_FTYPE_V2DF },
31582 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv2df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX, UNKNOWN, (int) V4SI_FTYPE_V2DF_V2DF },
31584 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_floorps", IX86_BUILTIN_FLOORPS, (enum rtx_code) ROUND_FLOOR, (int) V4SF_FTYPE_V4SF_ROUND },
31585 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_ceilps", IX86_BUILTIN_CEILPS, (enum rtx_code) ROUND_CEIL, (int) V4SF_FTYPE_V4SF_ROUND },
31586 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_truncps", IX86_BUILTIN_TRUNCPS, (enum rtx_code) ROUND_TRUNC, (int) V4SF_FTYPE_V4SF_ROUND },
31587 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_rintps", IX86_BUILTIN_RINTPS, (enum rtx_code) ROUND_MXCSR, (int) V4SF_FTYPE_V4SF_ROUND },
31589 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_floorps_sfix", IX86_BUILTIN_FLOORPS_SFIX, (enum rtx_code) ROUND_FLOOR, (int) V4SI_FTYPE_V4SF_ROUND },
31590 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps_sfix, "__builtin_ia32_ceilps_sfix", IX86_BUILTIN_CEILPS_SFIX, (enum rtx_code) ROUND_CEIL, (int) V4SI_FTYPE_V4SF_ROUND },
31592 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2, "__builtin_ia32_roundps_az", IX86_BUILTIN_ROUNDPS_AZ, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31593 { OPTION_MASK_ISA_ROUND, CODE_FOR_roundv4sf2_sfix, "__builtin_ia32_roundps_az_sfix", IX86_BUILTIN_ROUNDPS_AZ_SFIX, UNKNOWN, (int) V4SI_FTYPE_V4SF },
31595 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestz128", IX86_BUILTIN_PTESTZ, EQ, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31596 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestc128", IX86_BUILTIN_PTESTC, LTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31597 { OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_ptest, "__builtin_ia32_ptestnzc128", IX86_BUILTIN_PTESTNZC, GTU, (int) INT_FTYPE_V2DI_V2DI_PTEST },
31599 /* SSE4.2 */
31600 { OPTION_MASK_ISA_SSE4_2, CODE_FOR_sse4_2_gtv2di3, "__builtin_ia32_pcmpgtq", IX86_BUILTIN_PCMPGTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31601 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32qi, "__builtin_ia32_crc32qi", IX86_BUILTIN_CRC32QI, UNKNOWN, (int) UINT_FTYPE_UINT_UCHAR },
31602 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32hi, "__builtin_ia32_crc32hi", IX86_BUILTIN_CRC32HI, UNKNOWN, (int) UINT_FTYPE_UINT_USHORT },
31603 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32, CODE_FOR_sse4_2_crc32si, "__builtin_ia32_crc32si", IX86_BUILTIN_CRC32SI, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31604 { OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_CRC32 | OPTION_MASK_ISA_64BIT, CODE_FOR_sse4_2_crc32di, "__builtin_ia32_crc32di", IX86_BUILTIN_CRC32DI, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31606 /* SSE4A */
31607 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrqi, "__builtin_ia32_extrqi", IX86_BUILTIN_EXTRQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_UINT_UINT },
31608 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_extrq, "__builtin_ia32_extrq", IX86_BUILTIN_EXTRQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V16QI },
31609 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertqi, "__builtin_ia32_insertqi", IX86_BUILTIN_INSERTQI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_UINT_UINT },
31610 { OPTION_MASK_ISA_SSE4A, CODE_FOR_sse4a_insertq, "__builtin_ia32_insertq", IX86_BUILTIN_INSERTQ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31612 /* AES */
31613 { OPTION_MASK_ISA_SSE2, CODE_FOR_aeskeygenassist, 0, IX86_BUILTIN_AESKEYGENASSIST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT },
31614 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesimc, 0, IX86_BUILTIN_AESIMC128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31616 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenc, 0, IX86_BUILTIN_AESENC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31617 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesenclast, 0, IX86_BUILTIN_AESENCLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31618 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdec, 0, IX86_BUILTIN_AESDEC128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31619 { OPTION_MASK_ISA_SSE2, CODE_FOR_aesdeclast, 0, IX86_BUILTIN_AESDECLAST128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31621 /* PCLMUL */
31622 { OPTION_MASK_ISA_SSE2, CODE_FOR_pclmulqdq, 0, IX86_BUILTIN_PCLMULQDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT },
31624 /* AVX */
31625 { OPTION_MASK_ISA_AVX, CODE_FOR_addv4df3, "__builtin_ia32_addpd256", IX86_BUILTIN_ADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31626 { OPTION_MASK_ISA_AVX, CODE_FOR_addv8sf3, "__builtin_ia32_addps256", IX86_BUILTIN_ADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31627 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv4df3, "__builtin_ia32_addsubpd256", IX86_BUILTIN_ADDSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31628 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_addsubv8sf3, "__builtin_ia32_addsubps256", IX86_BUILTIN_ADDSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31629 { OPTION_MASK_ISA_AVX, CODE_FOR_andv4df3, "__builtin_ia32_andpd256", IX86_BUILTIN_ANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31630 { OPTION_MASK_ISA_AVX, CODE_FOR_andv8sf3, "__builtin_ia32_andps256", IX86_BUILTIN_ANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31631 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv4df3, "__builtin_ia32_andnpd256", IX86_BUILTIN_ANDNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31632 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_andnotv8sf3, "__builtin_ia32_andnps256", IX86_BUILTIN_ANDNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31633 { OPTION_MASK_ISA_AVX, CODE_FOR_divv4df3, "__builtin_ia32_divpd256", IX86_BUILTIN_DIVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31634 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_divv8sf3, "__builtin_ia32_divps256", IX86_BUILTIN_DIVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31635 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv4df3, "__builtin_ia32_haddpd256", IX86_BUILTIN_HADDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31636 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv8sf3, "__builtin_ia32_hsubps256", IX86_BUILTIN_HSUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31637 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_hsubv4df3, "__builtin_ia32_hsubpd256", IX86_BUILTIN_HSUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31638 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_haddv8sf3, "__builtin_ia32_haddps256", IX86_BUILTIN_HADDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31639 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv4df3, "__builtin_ia32_maxpd256", IX86_BUILTIN_MAXPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31640 { OPTION_MASK_ISA_AVX, CODE_FOR_smaxv8sf3, "__builtin_ia32_maxps256", IX86_BUILTIN_MAXPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31641 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv4df3, "__builtin_ia32_minpd256", IX86_BUILTIN_MINPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31642 { OPTION_MASK_ISA_AVX, CODE_FOR_sminv8sf3, "__builtin_ia32_minps256", IX86_BUILTIN_MINPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31643 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv4df3, "__builtin_ia32_mulpd256", IX86_BUILTIN_MULPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31644 { OPTION_MASK_ISA_AVX, CODE_FOR_mulv8sf3, "__builtin_ia32_mulps256", IX86_BUILTIN_MULPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31645 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv4df3, "__builtin_ia32_orpd256", IX86_BUILTIN_ORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31646 { OPTION_MASK_ISA_AVX, CODE_FOR_iorv8sf3, "__builtin_ia32_orps256", IX86_BUILTIN_ORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31647 { OPTION_MASK_ISA_AVX, CODE_FOR_subv4df3, "__builtin_ia32_subpd256", IX86_BUILTIN_SUBPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31648 { OPTION_MASK_ISA_AVX, CODE_FOR_subv8sf3, "__builtin_ia32_subps256", IX86_BUILTIN_SUBPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31649 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv4df3, "__builtin_ia32_xorpd256", IX86_BUILTIN_XORPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31650 { OPTION_MASK_ISA_AVX, CODE_FOR_xorv8sf3, "__builtin_ia32_xorps256", IX86_BUILTIN_XORPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31652 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv2df3, "__builtin_ia32_vpermilvarpd", IX86_BUILTIN_VPERMILVARPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI },
31653 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4sf3, "__builtin_ia32_vpermilvarps", IX86_BUILTIN_VPERMILVARPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI },
31654 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv4df3, "__builtin_ia32_vpermilvarpd256", IX86_BUILTIN_VPERMILVARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI },
31655 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilvarv8sf3, "__builtin_ia32_vpermilvarps256", IX86_BUILTIN_VPERMILVARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31657 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendpd256, "__builtin_ia32_blendpd256", IX86_BUILTIN_BLENDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31658 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendps256, "__builtin_ia32_blendps256", IX86_BUILTIN_BLENDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31659 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvpd256, "__builtin_ia32_blendvpd256", IX86_BUILTIN_BLENDVPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF },
31660 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_blendvps256, "__builtin_ia32_blendvps256", IX86_BUILTIN_BLENDVPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF },
31661 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_dpps256, "__builtin_ia32_dpps256", IX86_BUILTIN_DPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31662 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufpd256, "__builtin_ia32_shufpd256", IX86_BUILTIN_SHUFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31663 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_shufps256, "__builtin_ia32_shufps256", IX86_BUILTIN_SHUFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31664 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv2df3, "__builtin_ia32_cmpsd", IX86_BUILTIN_CMPSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31665 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vmcmpv4sf3, "__builtin_ia32_cmpss", IX86_BUILTIN_CMPSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31666 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv2df3, "__builtin_ia32_cmppd", IX86_BUILTIN_CMPPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
31667 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4sf3, "__builtin_ia32_cmpps", IX86_BUILTIN_CMPPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
31668 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv4df3, "__builtin_ia32_cmppd256", IX86_BUILTIN_CMPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31669 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cmpv8sf3, "__builtin_ia32_cmpps256", IX86_BUILTIN_CMPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31670 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v4df, "__builtin_ia32_vextractf128_pd256", IX86_BUILTIN_EXTRACTF128PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT },
31671 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8sf, "__builtin_ia32_vextractf128_ps256", IX86_BUILTIN_EXTRACTF128PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT },
31672 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vextractf128v8si, "__builtin_ia32_vextractf128_si256", IX86_BUILTIN_EXTRACTF128SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT },
31673 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv4siv4df2, "__builtin_ia32_cvtdq2pd256", IX86_BUILTIN_CVTDQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SI },
31674 { OPTION_MASK_ISA_AVX, CODE_FOR_floatv8siv8sf2, "__builtin_ia32_cvtdq2ps256", IX86_BUILTIN_CVTDQ2PS256, UNKNOWN, (int) V8SF_FTYPE_V8SI },
31675 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2ps256, "__builtin_ia32_cvtpd2ps256", IX86_BUILTIN_CVTPD2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DF },
31676 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_fix_notruncv8sfv8si, "__builtin_ia32_cvtps2dq256", IX86_BUILTIN_CVTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31677 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtps2pd256, "__builtin_ia32_cvtps2pd256", IX86_BUILTIN_CVTPS2PD256, UNKNOWN, (int) V4DF_FTYPE_V4SF },
31678 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv4dfv4si2, "__builtin_ia32_cvttpd2dq256", IX86_BUILTIN_CVTTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31679 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_cvtpd2dq256, "__builtin_ia32_cvtpd2dq256", IX86_BUILTIN_CVTPD2DQ256, UNKNOWN, (int) V4SI_FTYPE_V4DF },
31680 { OPTION_MASK_ISA_AVX, CODE_FOR_fix_truncv8sfv8si2, "__builtin_ia32_cvttps2dq256", IX86_BUILTIN_CVTTPS2DQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31681 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v4df3, "__builtin_ia32_vperm2f128_pd256", IX86_BUILTIN_VPERM2F128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT },
31682 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8sf3, "__builtin_ia32_vperm2f128_ps256", IX86_BUILTIN_VPERM2F128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT },
31683 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vperm2f128v8si3, "__builtin_ia32_vperm2f128_si256", IX86_BUILTIN_VPERM2F128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31684 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv2df, "__builtin_ia32_vpermilpd", IX86_BUILTIN_VPERMILPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
31685 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4sf, "__builtin_ia32_vpermilps", IX86_BUILTIN_VPERMILPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
31686 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv4df, "__builtin_ia32_vpermilpd256", IX86_BUILTIN_VPERMILPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31687 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vpermilv8sf, "__builtin_ia32_vpermilps256", IX86_BUILTIN_VPERMILPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31688 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v4df, "__builtin_ia32_vinsertf128_pd256", IX86_BUILTIN_VINSERTF128PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT },
31689 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8sf, "__builtin_ia32_vinsertf128_ps256", IX86_BUILTIN_VINSERTF128PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT },
31690 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vinsertf128v8si, "__builtin_ia32_vinsertf128_si256", IX86_BUILTIN_VINSERTF128SI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT },
31692 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movshdup256, "__builtin_ia32_movshdup256", IX86_BUILTIN_MOVSHDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31693 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movsldup256, "__builtin_ia32_movsldup256", IX86_BUILTIN_MOVSLDUP256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31694 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movddup256, "__builtin_ia32_movddup256", IX86_BUILTIN_MOVDDUP256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31696 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv4df2, "__builtin_ia32_sqrtpd256", IX86_BUILTIN_SQRTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31697 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_sqrtv8sf2, "__builtin_ia32_sqrtps256", IX86_BUILTIN_SQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31698 { OPTION_MASK_ISA_AVX, CODE_FOR_sqrtv8sf2, "__builtin_ia32_sqrtps_nr256", IX86_BUILTIN_SQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31699 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rsqrtv8sf2, "__builtin_ia32_rsqrtps256", IX86_BUILTIN_RSQRTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31700 { OPTION_MASK_ISA_AVX, CODE_FOR_rsqrtv8sf2, "__builtin_ia32_rsqrtps_nr256", IX86_BUILTIN_RSQRTPS_NR256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31702 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_rcpv8sf2, "__builtin_ia32_rcpps256", IX86_BUILTIN_RCPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31704 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_roundpd256", IX86_BUILTIN_ROUNDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31705 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_roundps256", IX86_BUILTIN_ROUNDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT },
31707 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_floorpd256", IX86_BUILTIN_FLOORPD256, (enum rtx_code) ROUND_FLOOR, (int) V4DF_FTYPE_V4DF_ROUND },
31708 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_ceilpd256", IX86_BUILTIN_CEILPD256, (enum rtx_code) ROUND_CEIL, (int) V4DF_FTYPE_V4DF_ROUND },
31709 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_truncpd256", IX86_BUILTIN_TRUNCPD256, (enum rtx_code) ROUND_TRUNC, (int) V4DF_FTYPE_V4DF_ROUND },
31710 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd256, "__builtin_ia32_rintpd256", IX86_BUILTIN_RINTPD256, (enum rtx_code) ROUND_MXCSR, (int) V4DF_FTYPE_V4DF_ROUND },
31712 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2, "__builtin_ia32_roundpd_az256", IX86_BUILTIN_ROUNDPD_AZ256, UNKNOWN, (int) V4DF_FTYPE_V4DF },
31713 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv4df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix256", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31715 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_floorpd_vec_pack_sfix256", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31716 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundpd_vec_pack_sfix256, "__builtin_ia32_ceilpd_vec_pack_sfix256", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V4DF_V4DF_ROUND },
31718 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_floorps256", IX86_BUILTIN_FLOORPS256, (enum rtx_code) ROUND_FLOOR, (int) V8SF_FTYPE_V8SF_ROUND },
31719 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_ceilps256", IX86_BUILTIN_CEILPS256, (enum rtx_code) ROUND_CEIL, (int) V8SF_FTYPE_V8SF_ROUND },
31720 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_truncps256", IX86_BUILTIN_TRUNCPS256, (enum rtx_code) ROUND_TRUNC, (int) V8SF_FTYPE_V8SF_ROUND },
31721 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps256, "__builtin_ia32_rintps256", IX86_BUILTIN_RINTPS256, (enum rtx_code) ROUND_MXCSR, (int) V8SF_FTYPE_V8SF_ROUND },
31723 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_floorps_sfix256", IX86_BUILTIN_FLOORPS_SFIX256, (enum rtx_code) ROUND_FLOOR, (int) V8SI_FTYPE_V8SF_ROUND },
31724 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_roundps_sfix256, "__builtin_ia32_ceilps_sfix256", IX86_BUILTIN_CEILPS_SFIX256, (enum rtx_code) ROUND_CEIL, (int) V8SI_FTYPE_V8SF_ROUND },
31726 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2, "__builtin_ia32_roundps_az256", IX86_BUILTIN_ROUNDPS_AZ256, UNKNOWN, (int) V8SF_FTYPE_V8SF },
31727 { OPTION_MASK_ISA_AVX, CODE_FOR_roundv8sf2_sfix, "__builtin_ia32_roundps_az_sfix256", IX86_BUILTIN_ROUNDPS_AZ_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V8SF },
31729 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhpd256, "__builtin_ia32_unpckhpd256", IX86_BUILTIN_UNPCKHPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31730 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklpd256, "__builtin_ia32_unpcklpd256", IX86_BUILTIN_UNPCKLPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31731 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpckhps256, "__builtin_ia32_unpckhps256", IX86_BUILTIN_UNPCKHPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31732 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_unpcklps256, "__builtin_ia32_unpcklps256", IX86_BUILTIN_UNPCKLPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31734 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_si256_si, "__builtin_ia32_si256_si", IX86_BUILTIN_SI256_SI, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31735 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ps256_ps, "__builtin_ia32_ps256_ps", IX86_BUILTIN_PS256_PS, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31736 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_pd256_pd, "__builtin_ia32_pd256_pd", IX86_BUILTIN_PD256_PD, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31737 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8si, "__builtin_ia32_si_si256", IX86_BUILTIN_SI_SI256, UNKNOWN, (int) V4SI_FTYPE_V8SI },
31738 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v8sf, "__builtin_ia32_ps_ps256", IX86_BUILTIN_PS_PS256, UNKNOWN, (int) V4SF_FTYPE_V8SF },
31739 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_extract_lo_v4df, "__builtin_ia32_pd_pd256", IX86_BUILTIN_PD_PD256, UNKNOWN, (int) V2DF_FTYPE_V4DF },
31741 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestzpd", IX86_BUILTIN_VTESTZPD, EQ, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31742 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestcpd", IX86_BUILTIN_VTESTCPD, LTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31743 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd, "__builtin_ia32_vtestnzcpd", IX86_BUILTIN_VTESTNZCPD, GTU, (int) INT_FTYPE_V2DF_V2DF_PTEST },
31744 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestzps", IX86_BUILTIN_VTESTZPS, EQ, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31745 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestcps", IX86_BUILTIN_VTESTCPS, LTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31746 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps, "__builtin_ia32_vtestnzcps", IX86_BUILTIN_VTESTNZCPS, GTU, (int) INT_FTYPE_V4SF_V4SF_PTEST },
31747 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestzpd256", IX86_BUILTIN_VTESTZPD256, EQ, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31748 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestcpd256", IX86_BUILTIN_VTESTCPD256, LTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31749 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestpd256, "__builtin_ia32_vtestnzcpd256", IX86_BUILTIN_VTESTNZCPD256, GTU, (int) INT_FTYPE_V4DF_V4DF_PTEST },
31750 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestzps256", IX86_BUILTIN_VTESTZPS256, EQ, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31751 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestcps256", IX86_BUILTIN_VTESTCPS256, LTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31752 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_vtestps256, "__builtin_ia32_vtestnzcps256", IX86_BUILTIN_VTESTNZCPS256, GTU, (int) INT_FTYPE_V8SF_V8SF_PTEST },
31753 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestz256", IX86_BUILTIN_PTESTZ256, EQ, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31754 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestc256", IX86_BUILTIN_PTESTC256, LTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31755 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_ptest256, "__builtin_ia32_ptestnzc256", IX86_BUILTIN_PTESTNZC256, GTU, (int) INT_FTYPE_V4DI_V4DI_PTEST },
31757 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskpd256, "__builtin_ia32_movmskpd256", IX86_BUILTIN_MOVMSKPD256, UNKNOWN, (int) INT_FTYPE_V4DF },
31758 { OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
31760 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv8sf3, "__builtin_ia32_copysignps256", IX86_BUILTIN_CPYSGNPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF },
31761 { OPTION_MASK_ISA_AVX, CODE_FOR_copysignv4df3, "__builtin_ia32_copysignpd256", IX86_BUILTIN_CPYSGNPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF },
31763 { OPTION_MASK_ISA_AVX, CODE_FOR_vec_pack_sfix_v4df, "__builtin_ia32_vec_pack_sfix256 ", IX86_BUILTIN_VEC_PACK_SFIX256, UNKNOWN, (int) V8SI_FTYPE_V4DF_V4DF },
31765 /* AVX2 */
31766 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_mpsadbw, "__builtin_ia32_mpsadbw256", IX86_BUILTIN_MPSADBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_INT },
31767 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv32qi2, "__builtin_ia32_pabsb256", IX86_BUILTIN_PABSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI },
31768 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv16hi2, "__builtin_ia32_pabsw256", IX86_BUILTIN_PABSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI },
31769 { OPTION_MASK_ISA_AVX2, CODE_FOR_absv8si2, "__builtin_ia32_pabsd256", IX86_BUILTIN_PABSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI },
31770 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packssdw, "__builtin_ia32_packssdw256", IX86_BUILTIN_PACKSSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31771 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packsswb, "__builtin_ia32_packsswb256", IX86_BUILTIN_PACKSSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31772 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packusdw, "__builtin_ia32_packusdw256", IX86_BUILTIN_PACKUSDW256, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI },
31773 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_packuswb, "__builtin_ia32_packuswb256", IX86_BUILTIN_PACKUSWB256, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI },
31774 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv32qi3, "__builtin_ia32_paddb256", IX86_BUILTIN_PADDB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31775 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv16hi3, "__builtin_ia32_paddw256", IX86_BUILTIN_PADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31776 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv8si3, "__builtin_ia32_paddd256", IX86_BUILTIN_PADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31777 { OPTION_MASK_ISA_AVX2, CODE_FOR_addv4di3, "__builtin_ia32_paddq256", IX86_BUILTIN_PADDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31778 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv32qi3, "__builtin_ia32_paddsb256", IX86_BUILTIN_PADDSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31779 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ssaddv16hi3, "__builtin_ia32_paddsw256", IX86_BUILTIN_PADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31780 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv32qi3, "__builtin_ia32_paddusb256", IX86_BUILTIN_PADDUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31781 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_usaddv16hi3, "__builtin_ia32_paddusw256", IX86_BUILTIN_PADDUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31782 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_palignrv2ti, "__builtin_ia32_palignr256", IX86_BUILTIN_PALIGNR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_CONVERT },
31783 { OPTION_MASK_ISA_AVX2, CODE_FOR_andv4di3, "__builtin_ia32_andsi256", IX86_BUILTIN_AND256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31784 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_andnotv4di3, "__builtin_ia32_andnotsi256", IX86_BUILTIN_ANDNOT256I, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31785 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv32qi3, "__builtin_ia32_pavgb256", IX86_BUILTIN_PAVGB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31786 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_uavgv16hi3, "__builtin_ia32_pavgw256", IX86_BUILTIN_PAVGW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31787 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendvb, "__builtin_ia32_pblendvb256", IX86_BUILTIN_PBLENDVB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI },
31788 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblendw, "__builtin_ia32_pblendw256", IX86_BUILTIN_PBLENDVW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_INT },
31789 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv32qi3, "__builtin_ia32_pcmpeqb256", IX86_BUILTIN_PCMPEQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31790 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv16hi3, "__builtin_ia32_pcmpeqw256", IX86_BUILTIN_PCMPEQW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31791 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv8si3, "__builtin_ia32_pcmpeqd256", IX86_BUILTIN_PCMPEQD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31792 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_eqv4di3, "__builtin_ia32_pcmpeqq256", IX86_BUILTIN_PCMPEQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31793 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv32qi3, "__builtin_ia32_pcmpgtb256", IX86_BUILTIN_PCMPGTB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31794 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv16hi3, "__builtin_ia32_pcmpgtw256", IX86_BUILTIN_PCMPGTW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31795 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv8si3, "__builtin_ia32_pcmpgtd256", IX86_BUILTIN_PCMPGTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31796 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_gtv4di3, "__builtin_ia32_pcmpgtq256", IX86_BUILTIN_PCMPGTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31797 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddwv16hi3, "__builtin_ia32_phaddw256", IX86_BUILTIN_PHADDW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31798 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phadddv8si3, "__builtin_ia32_phaddd256", IX86_BUILTIN_PHADDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31799 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phaddswv16hi3, "__builtin_ia32_phaddsw256", IX86_BUILTIN_PHADDSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31800 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubwv16hi3, "__builtin_ia32_phsubw256", IX86_BUILTIN_PHSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31801 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubdv8si3, "__builtin_ia32_phsubd256", IX86_BUILTIN_PHSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31802 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_phsubswv16hi3, "__builtin_ia32_phsubsw256", IX86_BUILTIN_PHSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31803 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddubsw256, "__builtin_ia32_pmaddubsw256", IX86_BUILTIN_PMADDUBSW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31804 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmaddwd, "__builtin_ia32_pmaddwd256", IX86_BUILTIN_PMADDWD256, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI },
31805 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv32qi3, "__builtin_ia32_pmaxsb256", IX86_BUILTIN_PMAXSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31806 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv16hi3, "__builtin_ia32_pmaxsw256", IX86_BUILTIN_PMAXSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31807 { OPTION_MASK_ISA_AVX2, CODE_FOR_smaxv8si3 , "__builtin_ia32_pmaxsd256", IX86_BUILTIN_PMAXSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31808 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv32qi3, "__builtin_ia32_pmaxub256", IX86_BUILTIN_PMAXUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31809 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv16hi3, "__builtin_ia32_pmaxuw256", IX86_BUILTIN_PMAXUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31810 { OPTION_MASK_ISA_AVX2, CODE_FOR_umaxv8si3 , "__builtin_ia32_pmaxud256", IX86_BUILTIN_PMAXUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31811 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv32qi3, "__builtin_ia32_pminsb256", IX86_BUILTIN_PMINSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31812 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv16hi3, "__builtin_ia32_pminsw256", IX86_BUILTIN_PMINSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31813 { OPTION_MASK_ISA_AVX2, CODE_FOR_sminv8si3 , "__builtin_ia32_pminsd256", IX86_BUILTIN_PMINSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31814 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv32qi3, "__builtin_ia32_pminub256", IX86_BUILTIN_PMINUB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31815 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv16hi3, "__builtin_ia32_pminuw256", IX86_BUILTIN_PMINUW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31816 { OPTION_MASK_ISA_AVX2, CODE_FOR_uminv8si3 , "__builtin_ia32_pminud256", IX86_BUILTIN_PMINUD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31817 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmovmskb, "__builtin_ia32_pmovmskb256", IX86_BUILTIN_PMOVMSKB256, UNKNOWN, (int) INT_FTYPE_V32QI },
31818 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv16qiv16hi2, "__builtin_ia32_pmovsxbw256", IX86_BUILTIN_PMOVSXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31819 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8qiv8si2 , "__builtin_ia32_pmovsxbd256", IX86_BUILTIN_PMOVSXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31820 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4qiv4di2 , "__builtin_ia32_pmovsxbq256", IX86_BUILTIN_PMOVSXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31821 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv8hiv8si2 , "__builtin_ia32_pmovsxwd256", IX86_BUILTIN_PMOVSXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31822 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4hiv4di2 , "__builtin_ia32_pmovsxwq256", IX86_BUILTIN_PMOVSXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31823 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sign_extendv4siv4di2 , "__builtin_ia32_pmovsxdq256", IX86_BUILTIN_PMOVSXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31824 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv16qiv16hi2, "__builtin_ia32_pmovzxbw256", IX86_BUILTIN_PMOVZXBW256, UNKNOWN, (int) V16HI_FTYPE_V16QI },
31825 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8qiv8si2 , "__builtin_ia32_pmovzxbd256", IX86_BUILTIN_PMOVZXBD256, UNKNOWN, (int) V8SI_FTYPE_V16QI },
31826 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4qiv4di2 , "__builtin_ia32_pmovzxbq256", IX86_BUILTIN_PMOVZXBQ256, UNKNOWN, (int) V4DI_FTYPE_V16QI },
31827 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv8hiv8si2 , "__builtin_ia32_pmovzxwd256", IX86_BUILTIN_PMOVZXWD256, UNKNOWN, (int) V8SI_FTYPE_V8HI },
31828 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4hiv4di2 , "__builtin_ia32_pmovzxwq256", IX86_BUILTIN_PMOVZXWQ256, UNKNOWN, (int) V4DI_FTYPE_V8HI },
31829 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_zero_extendv4siv4di2 , "__builtin_ia32_pmovzxdq256", IX86_BUILTIN_PMOVZXDQ256, UNKNOWN, (int) V4DI_FTYPE_V4SI },
31830 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_smult_even_v8si, "__builtin_ia32_pmuldq256", IX86_BUILTIN_PMULDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31831 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pmulhrswv16hi3 , "__builtin_ia32_pmulhrsw256", IX86_BUILTIN_PMULHRSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31832 { OPTION_MASK_ISA_AVX2, CODE_FOR_umulv16hi3_highpart, "__builtin_ia32_pmulhuw256" , IX86_BUILTIN_PMULHUW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31833 { OPTION_MASK_ISA_AVX2, CODE_FOR_smulv16hi3_highpart, "__builtin_ia32_pmulhw256" , IX86_BUILTIN_PMULHW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31834 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv16hi3, "__builtin_ia32_pmullw256" , IX86_BUILTIN_PMULLW256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31835 { OPTION_MASK_ISA_AVX2, CODE_FOR_mulv8si3, "__builtin_ia32_pmulld256" , IX86_BUILTIN_PMULLD256 , UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31836 { OPTION_MASK_ISA_AVX2, CODE_FOR_vec_widen_umult_even_v8si, "__builtin_ia32_pmuludq256", IX86_BUILTIN_PMULUDQ256, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI },
31837 { OPTION_MASK_ISA_AVX2, CODE_FOR_iorv4di3, "__builtin_ia32_por256", IX86_BUILTIN_POR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31838 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psadbw, "__builtin_ia32_psadbw256", IX86_BUILTIN_PSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI },
31839 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufbv32qi3, "__builtin_ia32_pshufb256", IX86_BUILTIN_PSHUFB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31840 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufdv3, "__builtin_ia32_pshufd256", IX86_BUILTIN_PSHUFD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT },
31841 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshufhwv3, "__builtin_ia32_pshufhw256", IX86_BUILTIN_PSHUFHW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31842 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pshuflwv3, "__builtin_ia32_pshuflw256", IX86_BUILTIN_PSHUFLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT },
31843 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv32qi3, "__builtin_ia32_psignb256", IX86_BUILTIN_PSIGNB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31844 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv16hi3, "__builtin_ia32_psignw256", IX86_BUILTIN_PSIGNW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31845 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_psignv8si3 , "__builtin_ia32_psignd256", IX86_BUILTIN_PSIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31846 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlv2ti3, "__builtin_ia32_pslldqi256", IX86_BUILTIN_PSLLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31847 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllwi256", IX86_BUILTIN_PSLLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31848 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv16hi3, "__builtin_ia32_psllw256", IX86_BUILTIN_PSLLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31849 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslldi256", IX86_BUILTIN_PSLLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31850 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv8si3, "__builtin_ia32_pslld256", IX86_BUILTIN_PSLLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31851 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllqi256", IX86_BUILTIN_PSLLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31852 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashlv4di3, "__builtin_ia32_psllq256", IX86_BUILTIN_PSLLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31853 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psrawi256", IX86_BUILTIN_PSRAWI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31854 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv16hi3, "__builtin_ia32_psraw256", IX86_BUILTIN_PSRAW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31855 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psradi256", IX86_BUILTIN_PSRADI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31856 { OPTION_MASK_ISA_AVX2, CODE_FOR_ashrv8si3, "__builtin_ia32_psrad256", IX86_BUILTIN_PSRAD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31857 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrv2ti3, "__builtin_ia32_psrldqi256", IX86_BUILTIN_PSRLDQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_CONVERT },
31858 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlwi256", IX86_BUILTIN_PSRLWI256 , UNKNOWN, (int) V16HI_FTYPE_V16HI_SI_COUNT },
31859 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv16hi3, "__builtin_ia32_psrlw256", IX86_BUILTIN_PSRLW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_COUNT },
31860 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrldi256", IX86_BUILTIN_PSRLDI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_SI_COUNT },
31861 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv8si3, "__builtin_ia32_psrld256", IX86_BUILTIN_PSRLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_COUNT },
31862 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlqi256", IX86_BUILTIN_PSRLQI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_COUNT },
31863 { OPTION_MASK_ISA_AVX2, CODE_FOR_lshrv4di3, "__builtin_ia32_psrlq256", IX86_BUILTIN_PSRLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_COUNT },
31864 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv32qi3, "__builtin_ia32_psubb256", IX86_BUILTIN_PSUBB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31865 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv16hi3, "__builtin_ia32_psubw256", IX86_BUILTIN_PSUBW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31866 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv8si3, "__builtin_ia32_psubd256", IX86_BUILTIN_PSUBD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31867 { OPTION_MASK_ISA_AVX2, CODE_FOR_subv4di3, "__builtin_ia32_psubq256", IX86_BUILTIN_PSUBQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31868 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv32qi3, "__builtin_ia32_psubsb256", IX86_BUILTIN_PSUBSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31869 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_sssubv16hi3, "__builtin_ia32_psubsw256", IX86_BUILTIN_PSUBSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31870 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv32qi3, "__builtin_ia32_psubusb256", IX86_BUILTIN_PSUBUSB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31871 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ussubv16hi3, "__builtin_ia32_psubusw256", IX86_BUILTIN_PSUBUSW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31872 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv32qi, "__builtin_ia32_punpckhbw256", IX86_BUILTIN_PUNPCKHBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31873 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv16hi, "__builtin_ia32_punpckhwd256", IX86_BUILTIN_PUNPCKHWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31874 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv8si, "__builtin_ia32_punpckhdq256", IX86_BUILTIN_PUNPCKHDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31875 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_highv4di, "__builtin_ia32_punpckhqdq256", IX86_BUILTIN_PUNPCKHQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31876 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv32qi, "__builtin_ia32_punpcklbw256", IX86_BUILTIN_PUNPCKLBW256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI },
31877 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv16hi, "__builtin_ia32_punpcklwd256", IX86_BUILTIN_PUNPCKLWD256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI },
31878 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv8si, "__builtin_ia32_punpckldq256", IX86_BUILTIN_PUNPCKLDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31879 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_interleave_lowv4di, "__builtin_ia32_punpcklqdq256", IX86_BUILTIN_PUNPCKLQDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31880 { OPTION_MASK_ISA_AVX2, CODE_FOR_xorv4di3, "__builtin_ia32_pxor256", IX86_BUILTIN_PXOR256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31881 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4sf, "__builtin_ia32_vbroadcastss_ps", IX86_BUILTIN_VBROADCASTSS_PS, UNKNOWN, (int) V4SF_FTYPE_V4SF },
31882 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv8sf, "__builtin_ia32_vbroadcastss_ps256", IX86_BUILTIN_VBROADCASTSS_PS256, UNKNOWN, (int) V8SF_FTYPE_V4SF },
31883 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vec_dupv4df, "__builtin_ia32_vbroadcastsd_pd256", IX86_BUILTIN_VBROADCASTSD_PD256, UNKNOWN, (int) V4DF_FTYPE_V2DF },
31884 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_vbroadcasti128_v4di, "__builtin_ia32_vbroadcastsi256", IX86_BUILTIN_VBROADCASTSI256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31885 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv4si, "__builtin_ia32_pblendd128", IX86_BUILTIN_PBLENDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
31886 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pblenddv8si, "__builtin_ia32_pblendd256", IX86_BUILTIN_PBLENDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT },
31887 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv32qi, "__builtin_ia32_pbroadcastb256", IX86_BUILTIN_PBROADCASTB256, UNKNOWN, (int) V32QI_FTYPE_V16QI },
31888 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16hi, "__builtin_ia32_pbroadcastw256", IX86_BUILTIN_PBROADCASTW256, UNKNOWN, (int) V16HI_FTYPE_V8HI },
31889 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8si, "__builtin_ia32_pbroadcastd256", IX86_BUILTIN_PBROADCASTD256, UNKNOWN, (int) V8SI_FTYPE_V4SI },
31890 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4di, "__builtin_ia32_pbroadcastq256", IX86_BUILTIN_PBROADCASTQ256, UNKNOWN, (int) V4DI_FTYPE_V2DI },
31891 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv16qi, "__builtin_ia32_pbroadcastb128", IX86_BUILTIN_PBROADCASTB128, UNKNOWN, (int) V16QI_FTYPE_V16QI },
31892 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv8hi, "__builtin_ia32_pbroadcastw128", IX86_BUILTIN_PBROADCASTW128, UNKNOWN, (int) V8HI_FTYPE_V8HI },
31893 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv4si, "__builtin_ia32_pbroadcastd128", IX86_BUILTIN_PBROADCASTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI },
31894 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_pbroadcastv2di, "__builtin_ia32_pbroadcastq128", IX86_BUILTIN_PBROADCASTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI },
31895 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8si, "__builtin_ia32_permvarsi256", IX86_BUILTIN_VPERMVARSI256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31896 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permvarv8sf, "__builtin_ia32_permvarsf256", IX86_BUILTIN_VPERMVARSF256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI },
31897 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4df, "__builtin_ia32_permdf256", IX86_BUILTIN_VPERMDF256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT },
31898 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv4di, "__builtin_ia32_permdi256", IX86_BUILTIN_VPERMDI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT },
31899 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_permv2ti, "__builtin_ia32_permti256", IX86_BUILTIN_VPERMTI256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT },
31900 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vextractf128v4di, "__builtin_ia32_extract128i256", IX86_BUILTIN_VEXTRACT128I256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT },
31901 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx_vinsertf128v4di, "__builtin_ia32_insert128i256", IX86_BUILTIN_VINSERT128I256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT },
31902 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4di, "__builtin_ia32_psllv4di", IX86_BUILTIN_PSLLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31903 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv2di, "__builtin_ia32_psllv2di", IX86_BUILTIN_PSLLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31904 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv8si, "__builtin_ia32_psllv8si", IX86_BUILTIN_PSLLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31905 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashlvv4si, "__builtin_ia32_psllv4si", IX86_BUILTIN_PSLLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31906 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv8si, "__builtin_ia32_psrav8si", IX86_BUILTIN_PSRAVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31907 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_ashrvv4si, "__builtin_ia32_psrav4si", IX86_BUILTIN_PSRAVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31908 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4di, "__builtin_ia32_psrlv4di", IX86_BUILTIN_PSRLVV4DI, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI },
31909 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv2di, "__builtin_ia32_psrlv2di", IX86_BUILTIN_PSRLVV2DI, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI },
31910 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv8si, "__builtin_ia32_psrlv8si", IX86_BUILTIN_PSRLVV8SI, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI },
31911 { OPTION_MASK_ISA_AVX2, CODE_FOR_avx2_lshrvv4si, "__builtin_ia32_psrlv4si", IX86_BUILTIN_PSRLVV4SI, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
31913 { OPTION_MASK_ISA_LZCNT, CODE_FOR_clzhi2_lzcnt, "__builtin_clzs", IX86_BUILTIN_CLZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31915 /* BMI */
31916 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_si, "__builtin_ia32_bextr_u32", IX86_BUILTIN_BEXTR32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31917 { OPTION_MASK_ISA_BMI, CODE_FOR_bmi_bextr_di, "__builtin_ia32_bextr_u64", IX86_BUILTIN_BEXTR64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31918 { OPTION_MASK_ISA_BMI, CODE_FOR_ctzhi2, "__builtin_ctzs", IX86_BUILTIN_CTZS, UNKNOWN, (int) UINT16_FTYPE_UINT16 },
31920 /* TBM */
31921 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31922 { OPTION_MASK_ISA_TBM, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31924 /* F16C */
31925 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI },
31926 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtph2ps256, "__builtin_ia32_vcvtph2ps256", IX86_BUILTIN_CVTPH2PS256, UNKNOWN, (int) V8SF_FTYPE_V8HI },
31927 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph, "__builtin_ia32_vcvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT },
31928 { OPTION_MASK_ISA_F16C, CODE_FOR_vcvtps2ph256, "__builtin_ia32_vcvtps2ph256", IX86_BUILTIN_CVTPS2PH256, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT },
31930 /* BMI2 */
31931 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_si3, "__builtin_ia32_bzhi_si", IX86_BUILTIN_BZHI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31932 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_bzhi_di3, "__builtin_ia32_bzhi_di", IX86_BUILTIN_BZHI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31933 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_si3, "__builtin_ia32_pdep_si", IX86_BUILTIN_PDEP32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31934 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pdep_di3, "__builtin_ia32_pdep_di", IX86_BUILTIN_PDEP64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31935 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_si3, "__builtin_ia32_pext_si", IX86_BUILTIN_PEXT32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT },
31936 { OPTION_MASK_ISA_BMI2, CODE_FOR_bmi2_pext_di3, "__builtin_ia32_pext_di", IX86_BUILTIN_PEXT64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64 },
31938 /* AVX512F */
31939 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_256si, "__builtin_ia32_si512_256si", IX86_BUILTIN_SI512_SI256, UNKNOWN, (int) V16SI_FTYPE_V8SI },
31940 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_256ps, "__builtin_ia32_ps512_256ps", IX86_BUILTIN_PS512_PS256, UNKNOWN, (int) V16SF_FTYPE_V8SF },
31941 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_256pd, "__builtin_ia32_pd512_256pd", IX86_BUILTIN_PD512_PD256, UNKNOWN, (int) V8DF_FTYPE_V4DF },
31942 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_si512_si, "__builtin_ia32_si512_si", IX86_BUILTIN_SI512_SI, UNKNOWN, (int) V16SI_FTYPE_V4SI },
31943 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ps512_ps, "__builtin_ia32_ps512_ps", IX86_BUILTIN_PS512_PS, UNKNOWN, (int) V16SF_FTYPE_V4SF },
31944 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pd512_pd, "__builtin_ia32_pd512_pd", IX86_BUILTIN_PD512_PD, UNKNOWN, (int) V8DF_FTYPE_V2DF },
31945 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv16si_mask, "__builtin_ia32_alignd512_mask", IX86_BUILTIN_ALIGND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
31946 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_alignv8di_mask, "__builtin_ia32_alignq512_mask", IX86_BUILTIN_ALIGNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
31947 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16si, "__builtin_ia32_blendmd_512_mask", IX86_BUILTIN_BLENDMD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31948 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8df, "__builtin_ia32_blendmpd_512_mask", IX86_BUILTIN_BLENDMPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31949 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv16sf, "__builtin_ia32_blendmps_512_mask", IX86_BUILTIN_BLENDMPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31950 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_blendmv8di, "__builtin_ia32_blendmq_512_mask", IX86_BUILTIN_BLENDMQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31951 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x4_512", IX86_BUILTIN_BROADCASTF32X4_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31952 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8df_mask, "__builtin_ia32_broadcastf64x4_512", IX86_BUILTIN_BROADCASTF64X4_512, UNKNOWN, (int) V8DF_FTYPE_V4DF_V8DF_QI },
31953 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv16si_mask, "__builtin_ia32_broadcasti32x4_512", IX86_BUILTIN_BROADCASTI32X4_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31954 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_broadcastv8di_mask, "__builtin_ia32_broadcasti64x4_512", IX86_BUILTIN_BROADCASTI64X4_512, UNKNOWN, (int) V8DI_FTYPE_V4DI_V8DI_QI },
31955 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8df_mask, "__builtin_ia32_broadcastsd512", IX86_BUILTIN_BROADCASTSD512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
31956 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16sf_mask, "__builtin_ia32_broadcastss512", IX86_BUILTIN_BROADCASTSS512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
31957 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16si3_mask, "__builtin_ia32_cmpd512_mask", IX86_BUILTIN_CMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
31958 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8di3_mask, "__builtin_ia32_cmpq512_mask", IX86_BUILTIN_CMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
31959 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8df_mask, "__builtin_ia32_compressdf512_mask", IX86_BUILTIN_COMPRESSPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31960 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16sf_mask, "__builtin_ia32_compresssf512_mask", IX86_BUILTIN_COMPRESSPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31961 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv8siv8df2_mask, "__builtin_ia32_cvtdq2pd512_mask", IX86_BUILTIN_CVTDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31962 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtps2ph512_mask, "__builtin_ia32_vcvtps2ph512_mask", IX86_BUILTIN_CVTPS2PH512, UNKNOWN, (int) V16HI_FTYPE_V16SF_INT_V16HI_HI },
31963 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv8siv8df2_mask, "__builtin_ia32_cvtudq2pd512_mask", IX86_BUILTIN_CVTUDQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SI_V8DF_QI },
31964 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2sd32, "__builtin_ia32_cvtusi2sd32", IX86_BUILTIN_CVTUSI2SD32, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT },
31965 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_mask, "__builtin_ia32_expanddf512_mask", IX86_BUILTIN_EXPANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31966 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8df_maskz, "__builtin_ia32_expanddf512_maskz", IX86_BUILTIN_EXPANDPD512Z, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31967 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_mask, "__builtin_ia32_expandsf512_mask", IX86_BUILTIN_EXPANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31968 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16sf_maskz, "__builtin_ia32_expandsf512_maskz", IX86_BUILTIN_EXPANDPS512Z, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31969 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf32x4_mask, "__builtin_ia32_extractf32x4_mask", IX86_BUILTIN_EXTRACTF32X4, UNKNOWN, (int) V4SF_FTYPE_V16SF_INT_V4SF_QI },
31970 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextractf64x4_mask, "__builtin_ia32_extractf64x4_mask", IX86_BUILTIN_EXTRACTF64X4, UNKNOWN, (int) V4DF_FTYPE_V8DF_INT_V4DF_QI },
31971 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti32x4_mask, "__builtin_ia32_extracti32x4_mask", IX86_BUILTIN_EXTRACTI32X4, UNKNOWN, (int) V4SI_FTYPE_V16SI_INT_V4SI_QI },
31972 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vextracti64x4_mask, "__builtin_ia32_extracti64x4_mask", IX86_BUILTIN_EXTRACTI64X4, UNKNOWN, (int) V4DI_FTYPE_V8DI_INT_V4DI_QI },
31973 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf32x4_mask, "__builtin_ia32_insertf32x4_mask", IX86_BUILTIN_INSERTF32X4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V4SF_INT_V16SF_HI },
31974 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinsertf64x4_mask, "__builtin_ia32_insertf64x4_mask", IX86_BUILTIN_INSERTF64X4, UNKNOWN, (int) V8DF_FTYPE_V8DF_V4DF_INT_V8DF_QI },
31975 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti32x4_mask, "__builtin_ia32_inserti32x4_mask", IX86_BUILTIN_INSERTI32X4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_INT_V16SI_HI },
31976 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vinserti64x4_mask, "__builtin_ia32_inserti64x4_mask", IX86_BUILTIN_INSERTI64X4, UNKNOWN, (int) V8DI_FTYPE_V8DI_V4DI_INT_V8DI_QI },
31977 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8df_mask, "__builtin_ia32_movapd512_mask", IX86_BUILTIN_MOVAPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31978 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16sf_mask, "__builtin_ia32_movaps512_mask", IX86_BUILTIN_MOVAPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31979 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movddup512_mask, "__builtin_ia32_movddup512_mask", IX86_BUILTIN_MOVDDUP512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
31980 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv16si_mask, "__builtin_ia32_movdqa32_512_mask", IX86_BUILTIN_MOVDQA32_512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31981 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_loadv8di_mask, "__builtin_ia32_movdqa64_512_mask", IX86_BUILTIN_MOVDQA64_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31982 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movshdup512_mask, "__builtin_ia32_movshdup512_mask", IX86_BUILTIN_MOVSHDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31983 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_movsldup512_mask, "__builtin_ia32_movsldup512_mask", IX86_BUILTIN_MOVSLDUP512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
31984 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv16si2_mask, "__builtin_ia32_pabsd512_mask", IX86_BUILTIN_PABSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
31985 { OPTION_MASK_ISA_AVX512F, CODE_FOR_absv8di2_mask, "__builtin_ia32_pabsq512_mask", IX86_BUILTIN_PABSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
31986 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16si3_mask, "__builtin_ia32_paddd512_mask", IX86_BUILTIN_PADDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31987 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8di3_mask, "__builtin_ia32_paddq512_mask", IX86_BUILTIN_PADDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31988 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv16si3_mask, "__builtin_ia32_pandd512_mask", IX86_BUILTIN_PANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31989 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv16si3_mask, "__builtin_ia32_pandnd512_mask", IX86_BUILTIN_PANDND512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
31990 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_andnotv8di3_mask, "__builtin_ia32_pandnq512_mask", IX86_BUILTIN_PANDNQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31991 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andv8di3_mask, "__builtin_ia32_pandq512_mask", IX86_BUILTIN_PANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
31992 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv16si_mask, "__builtin_ia32_pbroadcastd512", IX86_BUILTIN_PBROADCASTD512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
31993 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv16si_mask, "__builtin_ia32_pbroadcastd512_gpr_mask", IX86_BUILTIN_PBROADCASTD512_GPR, UNKNOWN, (int) V16SI_FTYPE_SI_V16SI_HI },
31994 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv8di, "__builtin_ia32_broadcastmb512", IX86_BUILTIN_PBROADCASTMB512, UNKNOWN, (int) V8DI_FTYPE_QI },
31995 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv16si, "__builtin_ia32_broadcastmw512", IX86_BUILTIN_PBROADCASTMW512, UNKNOWN, (int) V16SI_FTYPE_HI },
31996 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dupv8di_mask, "__builtin_ia32_pbroadcastq512", IX86_BUILTIN_PBROADCASTQ512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
31997 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vec_dup_gprv8di_mask, "__builtin_ia32_pbroadcastq512_gpr_mask", IX86_BUILTIN_PBROADCASTQ512_GPR, UNKNOWN, (int) V8DI_FTYPE_DI_V8DI_QI },
31998 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv16si3_mask, "__builtin_ia32_pcmpeqd512_mask", IX86_BUILTIN_PCMPEQD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
31999 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_eqv8di3_mask, "__builtin_ia32_pcmpeqq512_mask", IX86_BUILTIN_PCMPEQQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
32000 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv16si3_mask, "__builtin_ia32_pcmpgtd512_mask", IX86_BUILTIN_PCMPGTD512_MASK, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
32001 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_gtv8di3_mask, "__builtin_ia32_pcmpgtq512_mask", IX86_BUILTIN_PCMPGTQ512_MASK, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
32002 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv16si_mask, "__builtin_ia32_compresssi512_mask", IX86_BUILTIN_PCOMPRESSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32003 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_compressv8di_mask, "__builtin_ia32_compressdi512_mask", IX86_BUILTIN_PCOMPRESSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32004 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_mask, "__builtin_ia32_expandsi512_mask", IX86_BUILTIN_PEXPANDD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32005 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv16si_maskz, "__builtin_ia32_expandsi512_maskz", IX86_BUILTIN_PEXPANDD512Z, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32006 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_mask, "__builtin_ia32_expanddi512_mask", IX86_BUILTIN_PEXPANDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32007 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_expandv8di_maskz, "__builtin_ia32_expanddi512_maskz", IX86_BUILTIN_PEXPANDQ512Z, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32008 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16si3_mask, "__builtin_ia32_pmaxsd512_mask", IX86_BUILTIN_PMAXSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32009 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8di3_mask, "__builtin_ia32_pmaxsq512_mask", IX86_BUILTIN_PMAXSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32010 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv16si3_mask, "__builtin_ia32_pmaxud512_mask", IX86_BUILTIN_PMAXUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32011 { OPTION_MASK_ISA_AVX512F, CODE_FOR_umaxv8di3_mask, "__builtin_ia32_pmaxuq512_mask", IX86_BUILTIN_PMAXUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32012 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16si3_mask, "__builtin_ia32_pminsd512_mask", IX86_BUILTIN_PMINSD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32013 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8di3_mask, "__builtin_ia32_pminsq512_mask", IX86_BUILTIN_PMINSQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32014 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv16si3_mask, "__builtin_ia32_pminud512_mask", IX86_BUILTIN_PMINUD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32015 { OPTION_MASK_ISA_AVX512F, CODE_FOR_uminv8di3_mask, "__builtin_ia32_pminuq512_mask", IX86_BUILTIN_PMINUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32016 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16qi2_mask, "__builtin_ia32_pmovdb512_mask", IX86_BUILTIN_PMOVDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
32017 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev16siv16hi2_mask, "__builtin_ia32_pmovdw512_mask", IX86_BUILTIN_PMOVDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
32018 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div16qi2_mask, "__builtin_ia32_pmovqb512_mask", IX86_BUILTIN_PMOVQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
32019 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8si2_mask, "__builtin_ia32_pmovqd512_mask", IX86_BUILTIN_PMOVQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
32020 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_truncatev8div8hi2_mask, "__builtin_ia32_pmovqw512_mask", IX86_BUILTIN_PMOVQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
32021 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16qi2_mask, "__builtin_ia32_pmovsdb512_mask", IX86_BUILTIN_PMOVSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
32022 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev16siv16hi2_mask, "__builtin_ia32_pmovsdw512_mask", IX86_BUILTIN_PMOVSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
32023 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div16qi2_mask, "__builtin_ia32_pmovsqb512_mask", IX86_BUILTIN_PMOVSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
32024 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8si2_mask, "__builtin_ia32_pmovsqd512_mask", IX86_BUILTIN_PMOVSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
32025 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ss_truncatev8div8hi2_mask, "__builtin_ia32_pmovsqw512_mask", IX86_BUILTIN_PMOVSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
32026 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16qiv16si2_mask, "__builtin_ia32_pmovsxbd512_mask", IX86_BUILTIN_PMOVSXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
32027 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8qiv8di2_mask, "__builtin_ia32_pmovsxbq512_mask", IX86_BUILTIN_PMOVSXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
32028 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8siv8di2_mask, "__builtin_ia32_pmovsxdq512_mask", IX86_BUILTIN_PMOVSXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
32029 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv16hiv16si2_mask, "__builtin_ia32_pmovsxwd512_mask", IX86_BUILTIN_PMOVSXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
32030 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sign_extendv8hiv8di2_mask, "__builtin_ia32_pmovsxwq512_mask", IX86_BUILTIN_PMOVSXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
32031 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16qi2_mask, "__builtin_ia32_pmovusdb512_mask", IX86_BUILTIN_PMOVUSDB512, UNKNOWN, (int) V16QI_FTYPE_V16SI_V16QI_HI },
32032 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev16siv16hi2_mask, "__builtin_ia32_pmovusdw512_mask", IX86_BUILTIN_PMOVUSDW512, UNKNOWN, (int) V16HI_FTYPE_V16SI_V16HI_HI },
32033 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div16qi2_mask, "__builtin_ia32_pmovusqb512_mask", IX86_BUILTIN_PMOVUSQB512, UNKNOWN, (int) V16QI_FTYPE_V8DI_V16QI_QI },
32034 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8si2_mask, "__builtin_ia32_pmovusqd512_mask", IX86_BUILTIN_PMOVUSQD512, UNKNOWN, (int) V8SI_FTYPE_V8DI_V8SI_QI },
32035 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_us_truncatev8div8hi2_mask, "__builtin_ia32_pmovusqw512_mask", IX86_BUILTIN_PMOVUSQW512, UNKNOWN, (int) V8HI_FTYPE_V8DI_V8HI_QI },
32036 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16qiv16si2_mask, "__builtin_ia32_pmovzxbd512_mask", IX86_BUILTIN_PMOVZXBD512, UNKNOWN, (int) V16SI_FTYPE_V16QI_V16SI_HI },
32037 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8qiv8di2_mask, "__builtin_ia32_pmovzxbq512_mask", IX86_BUILTIN_PMOVZXBQ512, UNKNOWN, (int) V8DI_FTYPE_V16QI_V8DI_QI },
32038 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8siv8di2_mask, "__builtin_ia32_pmovzxdq512_mask", IX86_BUILTIN_PMOVZXDQ512, UNKNOWN, (int) V8DI_FTYPE_V8SI_V8DI_QI },
32039 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv16hiv16si2_mask, "__builtin_ia32_pmovzxwd512_mask", IX86_BUILTIN_PMOVZXWD512, UNKNOWN, (int) V16SI_FTYPE_V16HI_V16SI_HI },
32040 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_zero_extendv8hiv8di2_mask, "__builtin_ia32_pmovzxwq512_mask", IX86_BUILTIN_PMOVZXWQ512, UNKNOWN, (int) V8DI_FTYPE_V8HI_V8DI_QI },
32041 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_smult_even_v16si_mask, "__builtin_ia32_pmuldq512_mask", IX86_BUILTIN_PMULDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
32042 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16si3_mask, "__builtin_ia32_pmulld512_mask" , IX86_BUILTIN_PMULLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32043 { OPTION_MASK_ISA_AVX512F, CODE_FOR_vec_widen_umult_even_v16si_mask, "__builtin_ia32_pmuludq512_mask", IX86_BUILTIN_PMULUDQ512, UNKNOWN, (int) V8DI_FTYPE_V16SI_V16SI_V8DI_QI },
32044 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv16si3_mask, "__builtin_ia32_pord512_mask", IX86_BUILTIN_PORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32045 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorv8di3_mask, "__builtin_ia32_porq512_mask", IX86_BUILTIN_PORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32046 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv16si_mask, "__builtin_ia32_prold512_mask", IX86_BUILTIN_PROLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32047 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolv8di_mask, "__builtin_ia32_prolq512_mask", IX86_BUILTIN_PROLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32048 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv16si_mask, "__builtin_ia32_prolvd512_mask", IX86_BUILTIN_PROLVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32049 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rolvv8di_mask, "__builtin_ia32_prolvq512_mask", IX86_BUILTIN_PROLVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32050 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv16si_mask, "__builtin_ia32_prord512_mask", IX86_BUILTIN_PRORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32051 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorv8di_mask, "__builtin_ia32_prorq512_mask", IX86_BUILTIN_PRORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32052 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv16si_mask, "__builtin_ia32_prorvd512_mask", IX86_BUILTIN_PRORVD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32053 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rorvv8di_mask, "__builtin_ia32_prorvq512_mask", IX86_BUILTIN_PRORVQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32054 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_pshufdv3_mask, "__builtin_ia32_pshufd512_mask", IX86_BUILTIN_PSHUFD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32055 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslld512_mask", IX86_BUILTIN_PSLLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
32056 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv16si3_mask, "__builtin_ia32_pslldi512_mask", IX86_BUILTIN_PSLLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32057 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllq512_mask", IX86_BUILTIN_PSLLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
32058 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashlv8di3_mask, "__builtin_ia32_psllqi512_mask", IX86_BUILTIN_PSLLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32059 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv16si_mask, "__builtin_ia32_psllv16si_mask", IX86_BUILTIN_PSLLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32060 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashlvv8di_mask, "__builtin_ia32_psllv8di_mask", IX86_BUILTIN_PSLLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32061 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psrad512_mask", IX86_BUILTIN_PSRAD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
32062 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv16si3_mask, "__builtin_ia32_psradi512_mask", IX86_BUILTIN_PSRADI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32063 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraq512_mask", IX86_BUILTIN_PSRAQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
32064 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ashrv8di3_mask, "__builtin_ia32_psraqi512_mask", IX86_BUILTIN_PSRAQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32065 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv16si_mask, "__builtin_ia32_psrav16si_mask", IX86_BUILTIN_PSRAVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32066 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ashrvv8di_mask, "__builtin_ia32_psrav8di_mask", IX86_BUILTIN_PSRAVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32067 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrld512_mask", IX86_BUILTIN_PSRLD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V4SI_V16SI_HI },
32068 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv16si3_mask, "__builtin_ia32_psrldi512_mask", IX86_BUILTIN_PSRLDI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_INT_V16SI_HI },
32069 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlq512_mask", IX86_BUILTIN_PSRLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_V8DI_QI },
32070 { OPTION_MASK_ISA_AVX512F, CODE_FOR_lshrv8di3_mask, "__builtin_ia32_psrlqi512_mask", IX86_BUILTIN_PSRLQI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32071 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv16si_mask, "__builtin_ia32_psrlv16si_mask", IX86_BUILTIN_PSRLVV16SI, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32072 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_lshrvv8di_mask, "__builtin_ia32_psrlv8di_mask", IX86_BUILTIN_PSRLVV8DI, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32073 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16si3_mask, "__builtin_ia32_psubd512_mask", IX86_BUILTIN_PSUBD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32074 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8di3_mask, "__builtin_ia32_psubq512_mask", IX86_BUILTIN_PSUBQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32075 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv16si3_mask, "__builtin_ia32_ptestmd512", IX86_BUILTIN_PTESTMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
32076 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testmv8di3_mask, "__builtin_ia32_ptestmq512", IX86_BUILTIN_PTESTMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
32077 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv16si3_mask, "__builtin_ia32_ptestnmd512", IX86_BUILTIN_PTESTNMD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_HI },
32078 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_testnmv8di3_mask, "__builtin_ia32_ptestnmq512", IX86_BUILTIN_PTESTNMQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_QI },
32079 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv16si_mask, "__builtin_ia32_punpckhdq512_mask", IX86_BUILTIN_PUNPCKHDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32080 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_highv8di_mask, "__builtin_ia32_punpckhqdq512_mask", IX86_BUILTIN_PUNPCKHQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32081 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv16si_mask, "__builtin_ia32_punpckldq512_mask", IX86_BUILTIN_PUNPCKLDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32082 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_interleave_lowv8di_mask, "__builtin_ia32_punpcklqdq512_mask", IX86_BUILTIN_PUNPCKLQDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32083 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv16si3_mask, "__builtin_ia32_pxord512_mask", IX86_BUILTIN_PXORD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32084 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorv8di3_mask, "__builtin_ia32_pxorq512_mask", IX86_BUILTIN_PXORQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32085 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v8df_mask, "__builtin_ia32_rcp14pd512_mask", IX86_BUILTIN_RCP14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32086 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rcp14v16sf_mask, "__builtin_ia32_rcp14ps512_mask", IX86_BUILTIN_RCP14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32087 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v2df, "__builtin_ia32_rcp14sd", IX86_BUILTIN_RCP14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
32088 { OPTION_MASK_ISA_AVX512F, CODE_FOR_srcp14v4sf, "__builtin_ia32_rcp14ss", IX86_BUILTIN_RCP14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
32089 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v8df_mask, "__builtin_ia32_rsqrt14pd512_mask", IX86_BUILTIN_RSQRT14PD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI },
32090 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v16sf_mask, "__builtin_ia32_rsqrt14ps512_mask", IX86_BUILTIN_RSQRT14PS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI },
32091 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v2df, "__builtin_ia32_rsqrt14sd", IX86_BUILTIN_RSQRT14SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF },
32092 { OPTION_MASK_ISA_AVX512F, CODE_FOR_rsqrt14v4sf, "__builtin_ia32_rsqrt14ss", IX86_BUILTIN_RSQRT14SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF },
32093 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufpd512_mask, "__builtin_ia32_shufpd512_mask", IX86_BUILTIN_SHUFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
32094 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shufps512_mask, "__builtin_ia32_shufps512_mask", IX86_BUILTIN_SHUFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
32095 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_mask", IX86_BUILTIN_SHUF_F32x4, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI },
32096 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_mask", IX86_BUILTIN_SHUF_F64x2, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI },
32097 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_mask", IX86_BUILTIN_SHUF_I32x4, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_INT_V16SI_HI },
32098 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_mask", IX86_BUILTIN_SHUF_I64x2, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_QI },
32099 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv16si3_mask, "__builtin_ia32_ucmpd512_mask", IX86_BUILTIN_UCMPD512, UNKNOWN, (int) HI_FTYPE_V16SI_V16SI_INT_HI },
32100 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ucmpv8di3_mask, "__builtin_ia32_ucmpq512_mask", IX86_BUILTIN_UCMPQ512, UNKNOWN, (int) QI_FTYPE_V8DI_V8DI_INT_QI },
32101 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhpd512_mask, "__builtin_ia32_unpckhpd512_mask", IX86_BUILTIN_UNPCKHPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32102 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpckhps512_mask, "__builtin_ia32_unpckhps512_mask", IX86_BUILTIN_UNPCKHPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklpd512_mask, "__builtin_ia32_unpcklpd512_mask", IX86_BUILTIN_UNPCKLPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32104 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_unpcklps512_mask, "__builtin_ia32_unpcklps512_mask", IX86_BUILTIN_UNPCKLPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32105 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv16si2_mask, "__builtin_ia32_vplzcntd_512_mask", IX86_BUILTIN_VPCLZCNTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32106 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_clzv8di2_mask, "__builtin_ia32_vplzcntq_512_mask", IX86_BUILTIN_VPCLZCNTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32107 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv16si_mask, "__builtin_ia32_vpconflictsi_512_mask", IX86_BUILTIN_VPCONFLICTD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_HI },
32108 { OPTION_MASK_ISA_AVX512CD, CODE_FOR_conflictv8di_mask, "__builtin_ia32_vpconflictdi_512_mask", IX86_BUILTIN_VPCONFLICTQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_QI },
32109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8df_mask, "__builtin_ia32_permdf512_mask", IX86_BUILTIN_VPERMDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permv8di_mask, "__builtin_ia32_permdi512_mask", IX86_BUILTIN_VPERMDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_V8DI_QI },
32111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16si3_mask, "__builtin_ia32_vpermi2vard512_mask", IX86_BUILTIN_VPERMI2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32112 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8df3_mask, "__builtin_ia32_vpermi2varpd512_mask", IX86_BUILTIN_VPERMI2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
32113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv16sf3_mask, "__builtin_ia32_vpermi2varps512_mask", IX86_BUILTIN_VPERMI2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermi2varv8di3_mask, "__builtin_ia32_vpermi2varq512_mask", IX86_BUILTIN_VPERMI2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv8df_mask, "__builtin_ia32_vpermilpd512_mask", IX86_BUILTIN_VPERMILPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilv16sf_mask, "__builtin_ia32_vpermilps512_mask", IX86_BUILTIN_VPERMILPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
32117 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv8df3_mask, "__builtin_ia32_vpermilvarpd512_mask", IX86_BUILTIN_VPERMILVARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
32118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermilvarv16sf3_mask, "__builtin_ia32_vpermilvarps512_mask", IX86_BUILTIN_VPERMILVARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32119 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_mask, "__builtin_ia32_vpermt2vard512_mask", IX86_BUILTIN_VPERMT2VARD512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32120 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16si3_maskz, "__builtin_ia32_vpermt2vard512_maskz", IX86_BUILTIN_VPERMT2VARD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32121 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_mask, "__builtin_ia32_vpermt2varpd512_mask", IX86_BUILTIN_VPERMT2VARPD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
32122 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8df3_maskz, "__builtin_ia32_vpermt2varpd512_maskz", IX86_BUILTIN_VPERMT2VARPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_V8DF_QI },
32123 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_mask, "__builtin_ia32_vpermt2varps512_mask", IX86_BUILTIN_VPERMT2VARPS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
32124 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv16sf3_maskz, "__builtin_ia32_vpermt2varps512_maskz", IX86_BUILTIN_VPERMT2VARPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_V16SF_HI },
32125 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_mask, "__builtin_ia32_vpermt2varq512_mask", IX86_BUILTIN_VPERMT2VARQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32126 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vpermt2varv8di3_maskz, "__builtin_ia32_vpermt2varq512_maskz", IX86_BUILTIN_VPERMT2VARQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32127 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8df_mask, "__builtin_ia32_permvardf512_mask", IX86_BUILTIN_VPERMVARDF512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DI_V8DF_QI },
32128 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv8di_mask, "__builtin_ia32_permvardi512_mask", IX86_BUILTIN_VPERMVARDI512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32129 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16sf_mask, "__builtin_ia32_permvarsf512_mask", IX86_BUILTIN_VPERMVARSF512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SI_V16SF_HI },
32130 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_permvarv16si_mask, "__builtin_ia32_permvarsi512_mask", IX86_BUILTIN_VPERMVARSI512, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_HI },
32131 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_mask, "__builtin_ia32_pternlogd512_mask", IX86_BUILTIN_VTERNLOGD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
32132 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv16si_maskz, "__builtin_ia32_pternlogd512_maskz", IX86_BUILTIN_VTERNLOGD512_MASKZ, UNKNOWN, (int) V16SI_FTYPE_V16SI_V16SI_V16SI_INT_HI },
32133 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_mask, "__builtin_ia32_pternlogq512_mask", IX86_BUILTIN_VTERNLOGQ512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
32134 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vternlogv8di_maskz, "__builtin_ia32_pternlogq512_maskz", IX86_BUILTIN_VTERNLOGQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_INT_QI },
32136 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv16sf3, "__builtin_ia32_copysignps512", IX86_BUILTIN_CPYSGNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF },
32137 { OPTION_MASK_ISA_AVX512F, CODE_FOR_copysignv8df3, "__builtin_ia32_copysignpd512", IX86_BUILTIN_CPYSGNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF },
32138 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2, "__builtin_ia32_sqrtpd512", IX86_BUILTIN_SQRTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF },
32139 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sqrtv16sf2, "__builtin_ia32_sqrtps512", IX86_BUILTIN_SQRTPS_NR512, UNKNOWN, (int) V16SF_FTYPE_V16SF },
32140 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf, "__builtin_ia32_exp2ps", IX86_BUILTIN_EXP2PS, UNKNOWN, (int) V16SF_FTYPE_V16SF },
32141 { OPTION_MASK_ISA_AVX512F, CODE_FOR_roundv8df2_vec_pack_sfix, "__builtin_ia32_roundpd_az_vec_pack_sfix512", IX86_BUILTIN_ROUNDPD_AZ_VEC_PACK_SFIX512, UNKNOWN, (int) V16SI_FTYPE_V8DF_V8DF },
32142 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_floorpd_vec_pack_sfix512", IX86_BUILTIN_FLOORPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_FLOOR, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
32143 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_roundpd_vec_pack_sfix512, "__builtin_ia32_ceilpd_vec_pack_sfix512", IX86_BUILTIN_CEILPD_VEC_PACK_SFIX512, (enum rtx_code) ROUND_CEIL, (int) V16SI_FTYPE_V8DF_V8DF_ROUND },
32145 /* Mask arithmetic operations */
32146 { OPTION_MASK_ISA_AVX512F, CODE_FOR_andhi3, "__builtin_ia32_kandhi", IX86_BUILTIN_KAND16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32147 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kandnhi, "__builtin_ia32_kandnhi", IX86_BUILTIN_KANDN16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32148 { OPTION_MASK_ISA_AVX512F, CODE_FOR_one_cmplhi2, "__builtin_ia32_knothi", IX86_BUILTIN_KNOT16, UNKNOWN, (int) HI_FTYPE_HI },
32149 { OPTION_MASK_ISA_AVX512F, CODE_FOR_iorhi3, "__builtin_ia32_korhi", IX86_BUILTIN_KOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32150 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestchi, "__builtin_ia32_kortestchi", IX86_BUILTIN_KORTESTC16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32151 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kortestzhi, "__builtin_ia32_kortestzhi", IX86_BUILTIN_KORTESTZ16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32152 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kunpckhi, "__builtin_ia32_kunpckhi", IX86_BUILTIN_KUNPCKBW, UNKNOWN, (int) HI_FTYPE_HI_HI },
32153 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kxnorhi, "__builtin_ia32_kxnorhi", IX86_BUILTIN_KXNOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32154 { OPTION_MASK_ISA_AVX512F, CODE_FOR_xorhi3, "__builtin_ia32_kxorhi", IX86_BUILTIN_KXOR16, UNKNOWN, (int) HI_FTYPE_HI_HI },
32155 { OPTION_MASK_ISA_AVX512F, CODE_FOR_kmovw, "__builtin_ia32_kmov16", IX86_BUILTIN_KMOV16, UNKNOWN, (int) HI_FTYPE_HI },
32157 /* SHA */
32158 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg1, 0, IX86_BUILTIN_SHA1MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32159 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1msg2, 0, IX86_BUILTIN_SHA1MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32160 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1nexte, 0, IX86_BUILTIN_SHA1NEXTE, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32161 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha1rnds4, 0, IX86_BUILTIN_SHA1RNDS4, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT },
32162 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg1, 0, IX86_BUILTIN_SHA256MSG1, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32163 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256msg2, 0, IX86_BUILTIN_SHA256MSG2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
32164 { OPTION_MASK_ISA_SSE2, CODE_FOR_sha256rnds2, 0, IX86_BUILTIN_SHA256RNDS2, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI },
32166 /* AVX512VL. */
32167 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_palignrv32qi_mask, "__builtin_ia32_palignr256_mask", IX86_BUILTIN_PALIGNR256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_SI_CONVERT },
32168 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_palignrv16qi_mask, "__builtin_ia32_palignr128_mask", IX86_BUILTIN_PALIGNR128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_HI_CONVERT },
32169 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4di_mask, "__builtin_ia32_movdqa64_256_mask", IX86_BUILTIN_MOVDQA64_256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32170 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2di_mask, "__builtin_ia32_movdqa64_128_mask", IX86_BUILTIN_MOVDQA64_128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32171 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8si_mask, "__builtin_ia32_movdqa32_256_mask", IX86_BUILTIN_MOVDQA32_256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32172 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4si_mask, "__builtin_ia32_movdqa32_128_mask", IX86_BUILTIN_MOVDQA32_128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32173 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4df_mask, "__builtin_ia32_movapd256_mask", IX86_BUILTIN_MOVAPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32174 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv2df_mask, "__builtin_ia32_movapd128_mask", IX86_BUILTIN_MOVAPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32175 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv8sf_mask, "__builtin_ia32_movaps256_mask", IX86_BUILTIN_MOVAPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32176 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loadv4sf_mask, "__builtin_ia32_movaps128_mask", IX86_BUILTIN_MOVAPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32177 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv16hi_mask, "__builtin_ia32_movdquhi256_mask", IX86_BUILTIN_MOVDQUHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32178 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_loaddquv8hi_mask, "__builtin_ia32_movdquhi128_mask", IX86_BUILTIN_MOVDQUHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32179 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_loaddquv32qi_mask, "__builtin_ia32_movdquqi256_mask", IX86_BUILTIN_MOVDQUQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32180 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_loaddquv16qi_mask, "__builtin_ia32_movdquqi128_mask", IX86_BUILTIN_MOVDQUQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32181 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4sf3_mask, "__builtin_ia32_minps_mask", IX86_BUILTIN_MINPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32182 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4sf3_mask, "__builtin_ia32_maxps_mask", IX86_BUILTIN_MAXPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32183 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2df3_mask, "__builtin_ia32_minpd_mask", IX86_BUILTIN_MINPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32184 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2df3_mask, "__builtin_ia32_maxpd_mask", IX86_BUILTIN_MAXPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32185 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4df3_mask, "__builtin_ia32_maxpd256_mask", IX86_BUILTIN_MAXPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32186 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8sf3_mask, "__builtin_ia32_maxps256_mask", IX86_BUILTIN_MAXPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32187 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4df3_mask, "__builtin_ia32_minpd256_mask", IX86_BUILTIN_MINPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32188 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8sf3_mask, "__builtin_ia32_minps256_mask", IX86_BUILTIN_MINPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32189 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4sf3_mask, "__builtin_ia32_mulps_mask", IX86_BUILTIN_MULPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32190 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_divv4sf3_mask, "__builtin_ia32_divps_mask", IX86_BUILTIN_DIVPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32191 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv2df3_mask, "__builtin_ia32_mulpd_mask", IX86_BUILTIN_MULPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32192 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_divv2df3_mask, "__builtin_ia32_divpd_mask", IX86_BUILTIN_DIVPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32193 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv4df3_mask, "__builtin_ia32_divpd256_mask", IX86_BUILTIN_DIVPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32194 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_divv8sf3_mask, "__builtin_ia32_divps256_mask", IX86_BUILTIN_DIVPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32195 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4df3_mask, "__builtin_ia32_mulpd256_mask", IX86_BUILTIN_MULPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32196 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8sf3_mask, "__builtin_ia32_mulps256_mask", IX86_BUILTIN_MULPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32197 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2df3_mask, "__builtin_ia32_addpd128_mask", IX86_BUILTIN_ADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32198 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4df3_mask, "__builtin_ia32_addpd256_mask", IX86_BUILTIN_ADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32199 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4sf3_mask, "__builtin_ia32_addps128_mask", IX86_BUILTIN_ADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32200 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8sf3_mask, "__builtin_ia32_addps256_mask", IX86_BUILTIN_ADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32201 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2df3_mask, "__builtin_ia32_subpd128_mask", IX86_BUILTIN_SUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32202 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4df3_mask, "__builtin_ia32_subpd256_mask", IX86_BUILTIN_SUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32203 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4sf3_mask, "__builtin_ia32_subps128_mask", IX86_BUILTIN_SUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32204 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8sf3_mask, "__builtin_ia32_subps256_mask", IX86_BUILTIN_SUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32205 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4df3_mask, "__builtin_ia32_xorpd256_mask", IX86_BUILTIN_XORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32206 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2df3_mask, "__builtin_ia32_xorpd128_mask", IX86_BUILTIN_XORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32207 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8sf3_mask, "__builtin_ia32_xorps256_mask", IX86_BUILTIN_XORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32208 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4sf3_mask, "__builtin_ia32_xorps128_mask", IX86_BUILTIN_XORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32209 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4df3_mask, "__builtin_ia32_orpd256_mask", IX86_BUILTIN_ORPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32210 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2df3_mask, "__builtin_ia32_orpd128_mask", IX86_BUILTIN_ORPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32211 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8sf3_mask, "__builtin_ia32_orps256_mask", IX86_BUILTIN_ORPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32212 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4sf3_mask, "__builtin_ia32_orps128_mask", IX86_BUILTIN_ORPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32213 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8sf_mask, "__builtin_ia32_broadcastf32x2_256_mask", IX86_BUILTIN_BROADCASTF32x2_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32214 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv8si_mask, "__builtin_ia32_broadcasti32x2_256_mask", IX86_BUILTIN_BROADCASTI32x2_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32215 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4si_mask, "__builtin_ia32_broadcasti32x2_128_mask", IX86_BUILTIN_BROADCASTI32x2_128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32216 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4df_mask_1, "__builtin_ia32_broadcastf64x2_256_mask", IX86_BUILTIN_BROADCASTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32217 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_broadcastv4di_mask_1, "__builtin_ia32_broadcasti64x2_256_mask", IX86_BUILTIN_BROADCASTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32218 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8sf_mask_1, "__builtin_ia32_broadcastf32x4_256_mask", IX86_BUILTIN_BROADCASTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32219 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_broadcastv8si_mask_1, "__builtin_ia32_broadcasti32x4_256_mask", IX86_BUILTIN_BROADCASTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32220 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8sf, "__builtin_ia32_extractf32x4_256_mask", IX86_BUILTIN_EXTRACTF32X4_256, UNKNOWN, (int) V4SF_FTYPE_V8SF_INT_V4SF_QI },
32221 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v8si, "__builtin_ia32_extracti32x4_256_mask", IX86_BUILTIN_EXTRACTI32X4_256, UNKNOWN, (int) V4SI_FTYPE_V8SI_INT_V4SI_QI },
32222 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv16hi_mask, "__builtin_ia32_dbpsadbw256_mask", IX86_BUILTIN_DBPSADBW256, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_INT_V16HI_HI },
32223 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_dbpsadbwv8hi_mask, "__builtin_ia32_dbpsadbw128_mask", IX86_BUILTIN_DBPSADBW128, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_INT_V8HI_QI },
32224 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2qq256_mask", IX86_BUILTIN_CVTTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32225 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2qq128_mask", IX86_BUILTIN_CVTTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32226 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4di2_mask, "__builtin_ia32_cvttpd2uqq256_mask", IX86_BUILTIN_CVTTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32227 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2di2_mask, "__builtin_ia32_cvttpd2uqq128_mask", IX86_BUILTIN_CVTTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32228 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2qq256_mask", IX86_BUILTIN_CVTPD2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32229 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2qq128_mask", IX86_BUILTIN_CVTPD2QQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32230 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4di2_mask, "__builtin_ia32_cvtpd2uqq256_mask", IX86_BUILTIN_CVTPD2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4DF_V4DI_QI },
32231 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2di2_mask, "__builtin_ia32_cvtpd2uqq128_mask", IX86_BUILTIN_CVTPD2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V2DF_V2DI_QI },
32232 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv4dfv4si2_mask, "__builtin_ia32_cvtpd2udq256_mask", IX86_BUILTIN_CVTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32233 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_notruncv2dfv2si2_mask, "__builtin_ia32_cvtpd2udq128_mask", IX86_BUILTIN_CVTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32234 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2qq256_mask", IX86_BUILTIN_CVTTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32235 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2qq128_mask", IX86_BUILTIN_CVTTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32236 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4di2_mask, "__builtin_ia32_cvttps2uqq256_mask", IX86_BUILTIN_CVTTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32237 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2sfv2di2_mask, "__builtin_ia32_cvttps2uqq128_mask", IX86_BUILTIN_CVTTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32238 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2dq256_mask", IX86_BUILTIN_CVTTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32239 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2dq128_mask", IX86_BUILTIN_CVTTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32240 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv8sfv8si2_mask, "__builtin_ia32_cvttps2udq256_mask", IX86_BUILTIN_CVTTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32241 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4sfv4si2_mask, "__builtin_ia32_cvttps2udq128_mask", IX86_BUILTIN_CVTTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32242 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_fix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2dq256_mask", IX86_BUILTIN_CVTTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32243 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvttpd2dq_mask, "__builtin_ia32_cvttpd2dq128_mask", IX86_BUILTIN_CVTTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32244 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv4dfv4si2_mask, "__builtin_ia32_cvttpd2udq256_mask", IX86_BUILTIN_CVTTPD2UDQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32245 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufix_truncv2dfv2si2_mask, "__builtin_ia32_cvttpd2udq128_mask", IX86_BUILTIN_CVTTPD2UDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32246 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2dq256_mask, "__builtin_ia32_cvtpd2dq256_mask", IX86_BUILTIN_CVTPD2DQ256_MASK, UNKNOWN, (int) V4SI_FTYPE_V4DF_V4SI_QI },
32247 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2dq_mask, "__builtin_ia32_cvtpd2dq128_mask", IX86_BUILTIN_CVTPD2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V2DF_V4SI_QI },
32248 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4df2_mask, "__builtin_ia32_cvtdq2pd256_mask", IX86_BUILTIN_CVTDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32249 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtdq2pd_mask, "__builtin_ia32_cvtdq2pd128_mask", IX86_BUILTIN_CVTDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32250 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4df2_mask, "__builtin_ia32_cvtudq2pd256_mask", IX86_BUILTIN_CVTUDQ2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SI_V4DF_QI },
32251 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2siv2df2_mask, "__builtin_ia32_cvtudq2pd128_mask", IX86_BUILTIN_CVTUDQ2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SI_V2DF_QI },
32252 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv8siv8sf2_mask, "__builtin_ia32_cvtdq2ps256_mask", IX86_BUILTIN_CVTDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32253 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4siv4sf2_mask, "__builtin_ia32_cvtdq2ps128_mask", IX86_BUILTIN_CVTDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32254 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv8siv8sf2_mask, "__builtin_ia32_cvtudq2ps256_mask", IX86_BUILTIN_CVTUDQ2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_QI },
32255 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4siv4sf2_mask, "__builtin_ia32_cvtudq2ps128_mask", IX86_BUILTIN_CVTUDQ2PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_QI },
32256 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtps2pd256_mask, "__builtin_ia32_cvtps2pd256_mask", IX86_BUILTIN_CVTPS2PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4SF_V4DF_QI },
32257 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtps2pd_mask, "__builtin_ia32_cvtps2pd128_mask", IX86_BUILTIN_CVTPS2PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V4SF_V2DF_QI },
32258 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv32qi_mask, "__builtin_ia32_pbroadcastb256_mask", IX86_BUILTIN_PBROADCASTB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16QI_V32QI_SI },
32259 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv32qi_mask, "__builtin_ia32_pbroadcastb256_gpr_mask", IX86_BUILTIN_PBROADCASTB256_GPR_MASK, UNKNOWN, (int) V32QI_FTYPE_QI_V32QI_SI },
32260 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16qi_mask, "__builtin_ia32_pbroadcastb128_mask", IX86_BUILTIN_PBROADCASTB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32261 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16qi_mask, "__builtin_ia32_pbroadcastb128_gpr_mask", IX86_BUILTIN_PBROADCASTB128_GPR_MASK, UNKNOWN, (int) V16QI_FTYPE_QI_V16QI_HI },
32262 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv16hi_mask, "__builtin_ia32_pbroadcastw256_mask", IX86_BUILTIN_PBROADCASTW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8HI_V16HI_HI },
32263 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv16hi_mask, "__builtin_ia32_pbroadcastw256_gpr_mask", IX86_BUILTIN_PBROADCASTW256_GPR_MASK, UNKNOWN, (int) V16HI_FTYPE_HI_V16HI_HI },
32264 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8hi_mask, "__builtin_ia32_pbroadcastw128_mask", IX86_BUILTIN_PBROADCASTW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32265 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8hi_mask, "__builtin_ia32_pbroadcastw128_gpr_mask", IX86_BUILTIN_PBROADCASTW128_GPR_MASK, UNKNOWN, (int) V8HI_FTYPE_HI_V8HI_QI },
32266 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8si_mask, "__builtin_ia32_pbroadcastd256_mask", IX86_BUILTIN_PBROADCASTD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V4SI_V8SI_QI },
32267 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv8si_mask, "__builtin_ia32_pbroadcastd256_gpr_mask", IX86_BUILTIN_PBROADCASTD256_GPR_MASK, UNKNOWN, (int) V8SI_FTYPE_SI_V8SI_QI },
32268 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4si_mask, "__builtin_ia32_pbroadcastd128_mask", IX86_BUILTIN_PBROADCASTD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32269 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4si_mask, "__builtin_ia32_pbroadcastd128_gpr_mask", IX86_BUILTIN_PBROADCASTD128_GPR_MASK, UNKNOWN, (int) V4SI_FTYPE_SI_V4SI_QI },
32270 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4di_mask, "__builtin_ia32_pbroadcastq256_mask", IX86_BUILTIN_PBROADCASTQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V2DI_V4DI_QI },
32271 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv4di_mask, "__builtin_ia32_pbroadcastq256_gpr_mask", IX86_BUILTIN_PBROADCASTQ256_GPR_MASK, UNKNOWN, (int) V4DI_FTYPE_DI_V4DI_QI },
32272 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv2di_mask, "__builtin_ia32_pbroadcastq128_mask", IX86_BUILTIN_PBROADCASTQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32273 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dup_gprv2di_mask, "__builtin_ia32_pbroadcastq128_gpr_mask", IX86_BUILTIN_PBROADCASTQ128_GPR_MASK, UNKNOWN, (int) V2DI_FTYPE_DI_V2DI_QI },
32274 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv8sf_mask, "__builtin_ia32_broadcastss256_mask", IX86_BUILTIN_BROADCASTSS256, UNKNOWN, (int) V8SF_FTYPE_V4SF_V8SF_QI },
32275 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4sf_mask, "__builtin_ia32_broadcastss128_mask", IX86_BUILTIN_BROADCASTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32276 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vec_dupv4df_mask, "__builtin_ia32_broadcastsd256_mask", IX86_BUILTIN_BROADCASTSD256, UNKNOWN, (int) V4DF_FTYPE_V2DF_V4DF_QI },
32277 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4df, "__builtin_ia32_extractf64x2_256_mask", IX86_BUILTIN_EXTRACTF64X2_256, UNKNOWN, (int) V2DF_FTYPE_V4DF_INT_V2DF_QI },
32278 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vextractf128v4di, "__builtin_ia32_extracti64x2_256_mask", IX86_BUILTIN_EXTRACTI64X2_256, UNKNOWN, (int) V2DI_FTYPE_V4DI_INT_V2DI_QI },
32279 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8sf, "__builtin_ia32_insertf32x4_256_mask", IX86_BUILTIN_INSERTF32X4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V4SF_INT_V8SF_QI },
32280 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv8si, "__builtin_ia32_inserti32x4_256_mask", IX86_BUILTIN_INSERTI32X4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_INT_V8SI_QI },
32281 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv16qiv16hi2_mask, "__builtin_ia32_pmovsxbw256_mask", IX86_BUILTIN_PMOVSXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32282 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv8qiv8hi2_mask, "__builtin_ia32_pmovsxbw128_mask", IX86_BUILTIN_PMOVSXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32283 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8qiv8si2_mask, "__builtin_ia32_pmovsxbd256_mask", IX86_BUILTIN_PMOVSXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32284 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4qiv4si2_mask, "__builtin_ia32_pmovsxbd128_mask", IX86_BUILTIN_PMOVSXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32285 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4qiv4di2_mask, "__builtin_ia32_pmovsxbq256_mask", IX86_BUILTIN_PMOVSXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32286 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2qiv2di2_mask, "__builtin_ia32_pmovsxbq128_mask", IX86_BUILTIN_PMOVSXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32287 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv8hiv8si2_mask, "__builtin_ia32_pmovsxwd256_mask", IX86_BUILTIN_PMOVSXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32288 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv4hiv4si2_mask, "__builtin_ia32_pmovsxwd128_mask", IX86_BUILTIN_PMOVSXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32289 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4hiv4di2_mask, "__builtin_ia32_pmovsxwq256_mask", IX86_BUILTIN_PMOVSXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32290 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2hiv2di2_mask, "__builtin_ia32_pmovsxwq128_mask", IX86_BUILTIN_PMOVSXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32291 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sign_extendv4siv4di2_mask, "__builtin_ia32_pmovsxdq256_mask", IX86_BUILTIN_PMOVSXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32292 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_sign_extendv2siv2di2_mask, "__builtin_ia32_pmovsxdq128_mask", IX86_BUILTIN_PMOVSXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32293 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv16qiv16hi2_mask, "__builtin_ia32_pmovzxbw256_mask", IX86_BUILTIN_PMOVZXBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16QI_V16HI_HI },
32294 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv8qiv8hi2_mask, "__builtin_ia32_pmovzxbw128_mask", IX86_BUILTIN_PMOVZXBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V8HI_QI },
32295 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8qiv8si2_mask, "__builtin_ia32_pmovzxbd256_mask", IX86_BUILTIN_PMOVZXBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16QI_V8SI_QI },
32296 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4qiv4si2_mask, "__builtin_ia32_pmovzxbd128_mask", IX86_BUILTIN_PMOVZXBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V16QI_V4SI_QI },
32297 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4qiv4di2_mask, "__builtin_ia32_pmovzxbq256_mask", IX86_BUILTIN_PMOVZXBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V16QI_V4DI_QI },
32298 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2qiv2di2_mask, "__builtin_ia32_pmovzxbq128_mask", IX86_BUILTIN_PMOVZXBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V16QI_V2DI_QI },
32299 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv8hiv8si2_mask, "__builtin_ia32_pmovzxwd256_mask", IX86_BUILTIN_PMOVZXWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8HI_V8SI_QI },
32300 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv4hiv4si2_mask, "__builtin_ia32_pmovzxwd128_mask", IX86_BUILTIN_PMOVZXWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V4SI_QI },
32301 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4hiv4di2_mask, "__builtin_ia32_pmovzxwq256_mask", IX86_BUILTIN_PMOVZXWQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8HI_V4DI_QI },
32302 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2hiv2di2_mask, "__builtin_ia32_pmovzxwq128_mask", IX86_BUILTIN_PMOVZXWQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V8HI_V2DI_QI },
32303 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_zero_extendv4siv4di2_mask, "__builtin_ia32_pmovzxdq256_mask", IX86_BUILTIN_PMOVZXDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4SI_V4DI_QI },
32304 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_zero_extendv2siv2di2_mask, "__builtin_ia32_pmovzxdq128_mask", IX86_BUILTIN_PMOVZXDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V2DI_QI },
32305 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4df_mask, "__builtin_ia32_reducepd256_mask", IX86_BUILTIN_REDUCEPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32306 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv2df_mask, "__builtin_ia32_reducepd128_mask", IX86_BUILTIN_REDUCEPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32307 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv8sf_mask, "__builtin_ia32_reduceps256_mask", IX86_BUILTIN_REDUCEPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32308 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_reducepv4sf_mask, "__builtin_ia32_reduceps128_mask", IX86_BUILTIN_REDUCEPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32309 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv2df, "__builtin_ia32_reducesd", IX86_BUILTIN_REDUCESD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
32310 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducesv4sf, "__builtin_ia32_reducess", IX86_BUILTIN_REDUCESS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
32311 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16hi_mask, "__builtin_ia32_permvarhi256_mask", IX86_BUILTIN_VPERMVARHI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32312 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv8hi_mask, "__builtin_ia32_permvarhi128_mask", IX86_BUILTIN_VPERMVARHI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32313 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_mask, "__builtin_ia32_vpermt2varhi256_mask", IX86_BUILTIN_VPERMT2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32314 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16hi3_maskz, "__builtin_ia32_vpermt2varhi256_maskz", IX86_BUILTIN_VPERMT2VARHI256_MASKZ, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32315 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_mask, "__builtin_ia32_vpermt2varhi128_mask", IX86_BUILTIN_VPERMT2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32316 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8hi3_maskz, "__builtin_ia32_vpermt2varhi128_maskz", IX86_BUILTIN_VPERMT2VARHI128_MASKZ, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32317 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16hi3_mask, "__builtin_ia32_vpermi2varhi256_mask", IX86_BUILTIN_VPERMI2VARHI256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32318 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8hi3_mask, "__builtin_ia32_vpermi2varhi128_mask", IX86_BUILTIN_VPERMI2VARHI128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32319 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4df_mask, "__builtin_ia32_rcp14pd256_mask", IX86_BUILTIN_RCP14PD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32320 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v2df_mask, "__builtin_ia32_rcp14pd128_mask", IX86_BUILTIN_RCP14PD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32321 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v8sf_mask, "__builtin_ia32_rcp14ps256_mask", IX86_BUILTIN_RCP14PS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32322 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rcp14v4sf_mask, "__builtin_ia32_rcp14ps128_mask", IX86_BUILTIN_RCP14PS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32323 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4df_mask, "__builtin_ia32_rsqrt14pd256_mask", IX86_BUILTIN_RSQRT14PD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32324 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v2df_mask, "__builtin_ia32_rsqrt14pd128_mask", IX86_BUILTIN_RSQRT14PD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32325 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v8sf_mask, "__builtin_ia32_rsqrt14ps256_mask", IX86_BUILTIN_RSQRT14PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32326 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_rsqrt14v4sf_mask, "__builtin_ia32_rsqrt14ps128_mask", IX86_BUILTIN_RSQRT14PS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32327 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv4df2_mask, "__builtin_ia32_sqrtpd256_mask", IX86_BUILTIN_SQRTPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32328 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sqrtv2df2_mask, "__builtin_ia32_sqrtpd128_mask", IX86_BUILTIN_SQRTPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32329 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_sqrtv8sf2_mask, "__builtin_ia32_sqrtps256_mask", IX86_BUILTIN_SQRTPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32330 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_sqrtv4sf2_mask, "__builtin_ia32_sqrtps128_mask", IX86_BUILTIN_SQRTPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32331 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16qi3_mask, "__builtin_ia32_paddb128_mask", IX86_BUILTIN_PADDB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32332 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8hi3_mask, "__builtin_ia32_paddw128_mask", IX86_BUILTIN_PADDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32333 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4si3_mask, "__builtin_ia32_paddd128_mask", IX86_BUILTIN_PADDD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32334 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv2di3_mask, "__builtin_ia32_paddq128_mask", IX86_BUILTIN_PADDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32335 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16qi3_mask, "__builtin_ia32_psubb128_mask", IX86_BUILTIN_PSUBB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32336 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8hi3_mask, "__builtin_ia32_psubw128_mask", IX86_BUILTIN_PSUBW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32337 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4si3_mask, "__builtin_ia32_psubd128_mask", IX86_BUILTIN_PSUBD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32338 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv2di3_mask, "__builtin_ia32_psubq128_mask", IX86_BUILTIN_PSUBQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32339 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv16qi3_mask, "__builtin_ia32_paddsb128_mask", IX86_BUILTIN_PADDSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32340 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ssaddv8hi3_mask, "__builtin_ia32_paddsw128_mask", IX86_BUILTIN_PADDSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32341 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv16qi3_mask, "__builtin_ia32_psubsb128_mask", IX86_BUILTIN_PSUBSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32342 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_sssubv8hi3_mask, "__builtin_ia32_psubsw128_mask", IX86_BUILTIN_PSUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32343 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv16qi3_mask, "__builtin_ia32_paddusb128_mask", IX86_BUILTIN_PADDUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32344 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_usaddv8hi3_mask, "__builtin_ia32_paddusw128_mask", IX86_BUILTIN_PADDUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32345 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv16qi3_mask, "__builtin_ia32_psubusb128_mask", IX86_BUILTIN_PSUBUSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32346 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_ussubv8hi3_mask, "__builtin_ia32_psubusw128_mask", IX86_BUILTIN_PSUBUSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32347 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv32qi3_mask, "__builtin_ia32_paddb256_mask", IX86_BUILTIN_PADDB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32348 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv16hi3_mask, "__builtin_ia32_paddw256_mask", IX86_BUILTIN_PADDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32349 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv8si3_mask, "__builtin_ia32_paddd256_mask", IX86_BUILTIN_PADDD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32350 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_addv4di3_mask, "__builtin_ia32_paddq256_mask", IX86_BUILTIN_PADDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32351 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv32qi3_mask, "__builtin_ia32_paddsb256_mask", IX86_BUILTIN_PADDSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32352 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ssaddv16hi3_mask, "__builtin_ia32_paddsw256_mask", IX86_BUILTIN_PADDSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32353 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv32qi3_mask, "__builtin_ia32_paddusb256_mask", IX86_BUILTIN_PADDUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32354 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_usaddv16hi3_mask, "__builtin_ia32_paddusw256_mask", IX86_BUILTIN_PADDUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32355 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv32qi3_mask, "__builtin_ia32_psubb256_mask", IX86_BUILTIN_PSUBB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32356 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv16hi3_mask, "__builtin_ia32_psubw256_mask", IX86_BUILTIN_PSUBW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32357 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv8si3_mask, "__builtin_ia32_psubd256_mask", IX86_BUILTIN_PSUBD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32358 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_subv4di3_mask, "__builtin_ia32_psubq256_mask", IX86_BUILTIN_PSUBQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32359 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv32qi3_mask, "__builtin_ia32_psubsb256_mask", IX86_BUILTIN_PSUBSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32360 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_sssubv16hi3_mask, "__builtin_ia32_psubsw256_mask", IX86_BUILTIN_PSUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32361 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv32qi3_mask, "__builtin_ia32_psubusb256_mask", IX86_BUILTIN_PSUBUSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32362 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ussubv16hi3_mask, "__builtin_ia32_psubusw256_mask", IX86_BUILTIN_PSUBUSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32363 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_f64x2_mask, "__builtin_ia32_shuf_f64x2_256_mask", IX86_BUILTIN_SHUF_F64x2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32364 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_shuf_i64x2_mask, "__builtin_ia32_shuf_i64x2_256_mask", IX86_BUILTIN_SHUF_I64x2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32365 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_i32x4_mask, "__builtin_ia32_shuf_i32x4_256_mask", IX86_BUILTIN_SHUF_I32x4_256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32366 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_shuf_f32x4_mask, "__builtin_ia32_shuf_f32x4_256_mask", IX86_BUILTIN_SHUF_F32x4_256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32367 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovwb128_mask", IX86_BUILTIN_PMOVWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32368 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovwb256_mask", IX86_BUILTIN_PMOVWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32369 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovswb128_mask", IX86_BUILTIN_PMOVSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32370 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovswb256_mask", IX86_BUILTIN_PMOVSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32371 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8hiv8qi2_mask, "__builtin_ia32_pmovuswb128_mask", IX86_BUILTIN_PMOVUSWB128, UNKNOWN, (int) V16QI_FTYPE_V8HI_V16QI_QI },
32372 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev16hiv16qi2_mask, "__builtin_ia32_pmovuswb256_mask", IX86_BUILTIN_PMOVUSWB256, UNKNOWN, (int) V16QI_FTYPE_V16HI_V16QI_HI },
32373 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4qi2_mask, "__builtin_ia32_pmovdb128_mask", IX86_BUILTIN_PMOVDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32374 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8qi2_mask, "__builtin_ia32_pmovdb256_mask", IX86_BUILTIN_PMOVDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32375 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4qi2_mask, "__builtin_ia32_pmovsdb128_mask", IX86_BUILTIN_PMOVSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32376 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8qi2_mask, "__builtin_ia32_pmovsdb256_mask", IX86_BUILTIN_PMOVSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32377 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4qi2_mask, "__builtin_ia32_pmovusdb128_mask", IX86_BUILTIN_PMOVUSDB128, UNKNOWN, (int) V16QI_FTYPE_V4SI_V16QI_QI },
32378 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8qi2_mask, "__builtin_ia32_pmovusdb256_mask", IX86_BUILTIN_PMOVUSDB256, UNKNOWN, (int) V16QI_FTYPE_V8SI_V16QI_QI },
32379 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4siv4hi2_mask, "__builtin_ia32_pmovdw128_mask", IX86_BUILTIN_PMOVDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32380 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev8siv8hi2_mask, "__builtin_ia32_pmovdw256_mask", IX86_BUILTIN_PMOVDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32381 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4siv4hi2_mask, "__builtin_ia32_pmovsdw128_mask", IX86_BUILTIN_PMOVSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32382 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev8siv8hi2_mask, "__builtin_ia32_pmovsdw256_mask", IX86_BUILTIN_PMOVSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32383 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4siv4hi2_mask, "__builtin_ia32_pmovusdw128_mask", IX86_BUILTIN_PMOVUSDW128, UNKNOWN, (int) V8HI_FTYPE_V4SI_V8HI_QI },
32384 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev8siv8hi2_mask, "__builtin_ia32_pmovusdw256_mask", IX86_BUILTIN_PMOVUSDW256, UNKNOWN, (int) V8HI_FTYPE_V8SI_V8HI_QI },
32385 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2qi2_mask, "__builtin_ia32_pmovqb128_mask", IX86_BUILTIN_PMOVQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32386 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4qi2_mask, "__builtin_ia32_pmovqb256_mask", IX86_BUILTIN_PMOVQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32387 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2qi2_mask, "__builtin_ia32_pmovsqb128_mask", IX86_BUILTIN_PMOVSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32388 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4qi2_mask, "__builtin_ia32_pmovsqb256_mask", IX86_BUILTIN_PMOVSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32389 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2qi2_mask, "__builtin_ia32_pmovusqb128_mask", IX86_BUILTIN_PMOVUSQB128, UNKNOWN, (int) V16QI_FTYPE_V2DI_V16QI_QI },
32390 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4qi2_mask, "__builtin_ia32_pmovusqb256_mask", IX86_BUILTIN_PMOVUSQB256, UNKNOWN, (int) V16QI_FTYPE_V4DI_V16QI_QI },
32391 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2hi2_mask, "__builtin_ia32_pmovqw128_mask", IX86_BUILTIN_PMOVQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32392 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4hi2_mask, "__builtin_ia32_pmovqw256_mask", IX86_BUILTIN_PMOVQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32393 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2hi2_mask, "__builtin_ia32_pmovsqw128_mask", IX86_BUILTIN_PMOVSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32394 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4hi2_mask, "__builtin_ia32_pmovsqw256_mask", IX86_BUILTIN_PMOVSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32395 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2hi2_mask, "__builtin_ia32_pmovusqw128_mask", IX86_BUILTIN_PMOVUSQW128, UNKNOWN, (int) V8HI_FTYPE_V2DI_V8HI_QI },
32396 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4hi2_mask, "__builtin_ia32_pmovusqw256_mask", IX86_BUILTIN_PMOVUSQW256, UNKNOWN, (int) V8HI_FTYPE_V4DI_V8HI_QI },
32397 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev2div2si2_mask, "__builtin_ia32_pmovqd128_mask", IX86_BUILTIN_PMOVQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32398 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_truncatev4div4si2_mask, "__builtin_ia32_pmovqd256_mask", IX86_BUILTIN_PMOVQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32399 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev2div2si2_mask, "__builtin_ia32_pmovsqd128_mask", IX86_BUILTIN_PMOVSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32400 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ss_truncatev4div4si2_mask, "__builtin_ia32_pmovsqd256_mask", IX86_BUILTIN_PMOVSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32401 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev2div2si2_mask, "__builtin_ia32_pmovusqd128_mask", IX86_BUILTIN_PMOVUSQD128, UNKNOWN, (int) V4SI_FTYPE_V2DI_V4SI_QI },
32402 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_us_truncatev4div4si2_mask, "__builtin_ia32_pmovusqd256_mask", IX86_BUILTIN_PMOVUSQD256, UNKNOWN, (int) V4SI_FTYPE_V4DI_V4SI_QI },
32403 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4df_mask, "__builtin_ia32_rangepd256_mask", IX86_BUILTIN_RANGEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32404 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv2df_mask, "__builtin_ia32_rangepd128_mask", IX86_BUILTIN_RANGEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32405 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv8sf_mask, "__builtin_ia32_rangeps256_mask", IX86_BUILTIN_RANGEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32406 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_rangepv4sf_mask, "__builtin_ia32_rangeps128_mask", IX86_BUILTIN_RANGEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32407 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv8sf_mask, "__builtin_ia32_getexpps256_mask", IX86_BUILTIN_GETEXPPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32408 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4df_mask, "__builtin_ia32_getexppd256_mask", IX86_BUILTIN_GETEXPPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32409 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv4sf_mask, "__builtin_ia32_getexpps128_mask", IX86_BUILTIN_GETEXPPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32410 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getexpv2df_mask, "__builtin_ia32_getexppd128_mask", IX86_BUILTIN_GETEXPPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32411 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_mask, "__builtin_ia32_fixupimmpd256_mask", IX86_BUILTIN_FIXUPIMMPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32412 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4df_maskz, "__builtin_ia32_fixupimmpd256_maskz", IX86_BUILTIN_FIXUPIMMPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DI_INT_QI },
32413 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_mask, "__builtin_ia32_fixupimmps256_mask", IX86_BUILTIN_FIXUPIMMPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32414 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv8sf_maskz, "__builtin_ia32_fixupimmps256_maskz", IX86_BUILTIN_FIXUPIMMPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SI_INT_QI },
32415 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_mask, "__builtin_ia32_fixupimmpd128_mask", IX86_BUILTIN_FIXUPIMMPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32416 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv2df_maskz, "__builtin_ia32_fixupimmpd128_maskz", IX86_BUILTIN_FIXUPIMMPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI },
32417 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_mask, "__builtin_ia32_fixupimmps128_mask", IX86_BUILTIN_FIXUPIMMPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32418 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fixupimmv4sf_maskz, "__builtin_ia32_fixupimmps128_maskz", IX86_BUILTIN_FIXUPIMMPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI },
32419 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4di2_mask, "__builtin_ia32_pabsq256_mask", IX86_BUILTIN_PABSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32420 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv2di2_mask, "__builtin_ia32_pabsq128_mask", IX86_BUILTIN_PABSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32421 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8si2_mask, "__builtin_ia32_pabsd256_mask", IX86_BUILTIN_PABSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32422 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv4si2_mask, "__builtin_ia32_pabsd128_mask", IX86_BUILTIN_PABSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32423 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pmulhrswv16hi3_mask , "__builtin_ia32_pmulhrsw256_mask", IX86_BUILTIN_PMULHRSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32424 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pmulhrswv8hi3_mask, "__builtin_ia32_pmulhrsw128_mask", IX86_BUILTIN_PMULHRSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32425 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv8hi3_highpart_mask, "__builtin_ia32_pmulhuw128_mask", IX86_BUILTIN_PMULHUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32426 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umulv16hi3_highpart_mask, "__builtin_ia32_pmulhuw256_mask" , IX86_BUILTIN_PMULHUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32427 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv16hi3_highpart_mask, "__builtin_ia32_pmulhw256_mask" , IX86_BUILTIN_PMULHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32428 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smulv8hi3_highpart_mask, "__builtin_ia32_pmulhw128_mask", IX86_BUILTIN_PMULHW128_MASK, UNKNOWN,(int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32429 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv16hi3_mask, "__builtin_ia32_pmullw256_mask" , IX86_BUILTIN_PMULLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32430 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8hi3_mask, "__builtin_ia32_pmullw128_mask", IX86_BUILTIN_PMULLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32431 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv4di3_mask, "__builtin_ia32_pmullq256_mask", IX86_BUILTIN_PMULLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32432 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_mulv2di3_mask, "__builtin_ia32_pmullq128_mask", IX86_BUILTIN_PMULLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32433 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4df3_mask, "__builtin_ia32_andpd256_mask", IX86_BUILTIN_ANDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32434 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2df3_mask, "__builtin_ia32_andpd128_mask", IX86_BUILTIN_ANDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32435 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8sf3_mask, "__builtin_ia32_andps256_mask", IX86_BUILTIN_ANDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32436 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4sf3_mask, "__builtin_ia32_andps128_mask", IX86_BUILTIN_ANDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32437 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv4df3_mask, "__builtin_ia32_andnpd256_mask", IX86_BUILTIN_ANDNPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32438 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2df3_mask, "__builtin_ia32_andnpd128_mask", IX86_BUILTIN_ANDNPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32439 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_andnotv8sf3_mask, "__builtin_ia32_andnps256_mask", IX86_BUILTIN_ANDNPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32440 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_andnotv4sf3_mask, "__builtin_ia32_andnps128_mask", IX86_BUILTIN_ANDNPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32441 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllwi128_mask", IX86_BUILTIN_PSLLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32442 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslldi128_mask", IX86_BUILTIN_PSLLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32443 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllqi128_mask", IX86_BUILTIN_PSLLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32444 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8hi3_mask, "__builtin_ia32_psllw128_mask", IX86_BUILTIN_PSLLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32445 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4si3_mask, "__builtin_ia32_pslld128_mask", IX86_BUILTIN_PSLLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32446 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv2di3_mask, "__builtin_ia32_psllq128_mask", IX86_BUILTIN_PSLLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32447 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllwi256_mask", IX86_BUILTIN_PSLLWI256_MASK , UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32448 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv16hi3_mask, "__builtin_ia32_psllw256_mask", IX86_BUILTIN_PSLLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32449 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslldi256_mask", IX86_BUILTIN_PSLLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32450 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv8si3_mask, "__builtin_ia32_pslld256_mask", IX86_BUILTIN_PSLLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32451 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllqi256_mask", IX86_BUILTIN_PSLLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32452 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashlv4di3_mask, "__builtin_ia32_psllq256_mask", IX86_BUILTIN_PSLLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32453 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psradi128_mask", IX86_BUILTIN_PSRADI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32454 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4si3_mask, "__builtin_ia32_psrad128_mask", IX86_BUILTIN_PSRAD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32455 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psradi256_mask", IX86_BUILTIN_PSRADI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32456 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8si3_mask, "__builtin_ia32_psrad256_mask", IX86_BUILTIN_PSRAD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32457 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraqi128_mask", IX86_BUILTIN_PSRAQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32458 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv2di3_mask, "__builtin_ia32_psraq128_mask", IX86_BUILTIN_PSRAQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32459 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraqi256_mask", IX86_BUILTIN_PSRAQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32460 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv4di3_mask, "__builtin_ia32_psraq256_mask", IX86_BUILTIN_PSRAQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32461 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv8si3_mask, "__builtin_ia32_pandd256_mask", IX86_BUILTIN_PANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32462 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4si3_mask, "__builtin_ia32_pandd128_mask", IX86_BUILTIN_PANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32463 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrldi128_mask", IX86_BUILTIN_PSRLDI128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32464 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4si3_mask, "__builtin_ia32_psrld128_mask", IX86_BUILTIN_PSRLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32465 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrldi256_mask", IX86_BUILTIN_PSRLDI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32466 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8si3_mask, "__builtin_ia32_psrld256_mask", IX86_BUILTIN_PSRLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V4SI_V8SI_QI },
32467 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlqi128_mask", IX86_BUILTIN_PSRLQI128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32468 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv2di3_mask, "__builtin_ia32_psrlq128_mask", IX86_BUILTIN_PSRLQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32469 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlqi256_mask", IX86_BUILTIN_PSRLQI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32470 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv4di3_mask, "__builtin_ia32_psrlq256_mask", IX86_BUILTIN_PSRLQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_V4DI_QI },
32471 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv4di3_mask, "__builtin_ia32_pandq256_mask", IX86_BUILTIN_PANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32472 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_andv2di3_mask, "__builtin_ia32_pandq128_mask", IX86_BUILTIN_PANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32473 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv8si3_mask, "__builtin_ia32_pandnd256_mask", IX86_BUILTIN_PANDND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32474 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv4si3_mask, "__builtin_ia32_pandnd128_mask", IX86_BUILTIN_PANDND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32475 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_andnotv4di3_mask, "__builtin_ia32_pandnq256_mask", IX86_BUILTIN_PANDNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32476 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_andnotv2di3_mask, "__builtin_ia32_pandnq128_mask", IX86_BUILTIN_PANDNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32477 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv8si3_mask, "__builtin_ia32_pord256_mask", IX86_BUILTIN_PORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32478 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4si3_mask, "__builtin_ia32_pord128_mask", IX86_BUILTIN_PORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32479 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv4di3_mask, "__builtin_ia32_porq256_mask", IX86_BUILTIN_PORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32480 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_iorv2di3_mask, "__builtin_ia32_porq128_mask", IX86_BUILTIN_PORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32481 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv8si3_mask, "__builtin_ia32_pxord256_mask", IX86_BUILTIN_PXORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32482 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4si3_mask, "__builtin_ia32_pxord128_mask", IX86_BUILTIN_PXORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32483 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv4di3_mask, "__builtin_ia32_pxorq256_mask", IX86_BUILTIN_PXORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32484 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_xorv2di3_mask, "__builtin_ia32_pxorq128_mask", IX86_BUILTIN_PXORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32485 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packsswb_mask, "__builtin_ia32_packsswb256_mask", IX86_BUILTIN_PACKSSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32486 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packsswb_mask, "__builtin_ia32_packsswb128_mask", IX86_BUILTIN_PACKSSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32487 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packuswb_mask, "__builtin_ia32_packuswb256_mask", IX86_BUILTIN_PACKUSWB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V16HI_V16HI_V32QI_SI },
32488 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packuswb_mask, "__builtin_ia32_packuswb128_mask", IX86_BUILTIN_PACKUSWB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V8HI_V8HI_V16QI_HI },
32489 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev8sf_mask, "__builtin_ia32_rndscaleps_256_mask", IX86_BUILTIN_RNDSCALEPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32490 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4df_mask, "__builtin_ia32_rndscalepd_256_mask", IX86_BUILTIN_RNDSCALEPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32491 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev4sf_mask, "__builtin_ia32_rndscaleps_128_mask", IX86_BUILTIN_RNDSCALEPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32492 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rndscalev2df_mask, "__builtin_ia32_rndscalepd_128_mask", IX86_BUILTIN_RNDSCALEPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32493 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_mask, "__builtin_ia32_pternlogq256_mask", IX86_BUILTIN_VTERNLOGQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32494 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4di_maskz, "__builtin_ia32_pternlogq256_maskz", IX86_BUILTIN_VTERNLOGQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_INT_QI },
32495 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_mask, "__builtin_ia32_pternlogd256_mask", IX86_BUILTIN_VTERNLOGD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32496 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv8si_maskz, "__builtin_ia32_pternlogd256_maskz", IX86_BUILTIN_VTERNLOGD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_INT_QI },
32497 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_mask, "__builtin_ia32_pternlogq128_mask", IX86_BUILTIN_VTERNLOGQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32498 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv2di_maskz, "__builtin_ia32_pternlogq128_maskz", IX86_BUILTIN_VTERNLOGQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_INT_QI },
32499 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_mask, "__builtin_ia32_pternlogd128_mask", IX86_BUILTIN_VTERNLOGD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32500 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vternlogv4si_maskz, "__builtin_ia32_pternlogd128_maskz", IX86_BUILTIN_VTERNLOGD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_INT_QI },
32501 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4df_mask, "__builtin_ia32_scalefpd256_mask", IX86_BUILTIN_SCALEFPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32502 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv8sf_mask, "__builtin_ia32_scalefps256_mask", IX86_BUILTIN_SCALEFPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32503 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv2df_mask, "__builtin_ia32_scalefpd128_mask", IX86_BUILTIN_SCALEFPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32504 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_scalefv4sf_mask, "__builtin_ia32_scalefps128_mask", IX86_BUILTIN_SCALEFPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32505 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask, "__builtin_ia32_vfmaddpd256_mask", IX86_BUILTIN_VFMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32506 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_mask3, "__builtin_ia32_vfmaddpd256_mask3", IX86_BUILTIN_VFMADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32507 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4df_maskz, "__builtin_ia32_vfmaddpd256_maskz", IX86_BUILTIN_VFMADDPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32508 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask, "__builtin_ia32_vfmaddpd128_mask", IX86_BUILTIN_VFMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32509 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_mask3, "__builtin_ia32_vfmaddpd128_mask3", IX86_BUILTIN_VFMADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32510 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v2df_maskz, "__builtin_ia32_vfmaddpd128_maskz", IX86_BUILTIN_VFMADDPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32511 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask, "__builtin_ia32_vfmaddps256_mask", IX86_BUILTIN_VFMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32512 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_mask3, "__builtin_ia32_vfmaddps256_mask3", IX86_BUILTIN_VFMADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32513 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v8sf_maskz, "__builtin_ia32_vfmaddps256_maskz", IX86_BUILTIN_VFMADDPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32514 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask, "__builtin_ia32_vfmaddps128_mask", IX86_BUILTIN_VFMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32515 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_mask3, "__builtin_ia32_vfmaddps128_mask3", IX86_BUILTIN_VFMADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32516 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmadd_v4sf_maskz, "__builtin_ia32_vfmaddps128_maskz", IX86_BUILTIN_VFMADDPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32517 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4df_mask3, "__builtin_ia32_vfmsubpd256_mask3", IX86_BUILTIN_VFMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32518 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v2df_mask3, "__builtin_ia32_vfmsubpd128_mask3", IX86_BUILTIN_VFMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32519 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v8sf_mask3, "__builtin_ia32_vfmsubps256_mask3", IX86_BUILTIN_VFMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32520 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsub_v4sf_mask3, "__builtin_ia32_vfmsubps128_mask3", IX86_BUILTIN_VFMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32521 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4df_mask, "__builtin_ia32_vfnmaddpd256_mask", IX86_BUILTIN_VFNMADDPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32522 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v2df_mask, "__builtin_ia32_vfnmaddpd128_mask", IX86_BUILTIN_VFNMADDPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32523 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v8sf_mask, "__builtin_ia32_vfnmaddps256_mask", IX86_BUILTIN_VFNMADDPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32524 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmadd_v4sf_mask, "__builtin_ia32_vfnmaddps128_mask", IX86_BUILTIN_VFNMADDPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32525 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask, "__builtin_ia32_vfnmsubpd256_mask", IX86_BUILTIN_VFNMSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32526 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4df_mask3, "__builtin_ia32_vfnmsubpd256_mask3", IX86_BUILTIN_VFNMSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32527 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask, "__builtin_ia32_vfnmsubpd128_mask", IX86_BUILTIN_VFNMSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32528 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v2df_mask3, "__builtin_ia32_vfnmsubpd128_mask3", IX86_BUILTIN_VFNMSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32529 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask, "__builtin_ia32_vfnmsubps256_mask", IX86_BUILTIN_VFNMSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32530 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v8sf_mask3, "__builtin_ia32_vfnmsubps256_mask3", IX86_BUILTIN_VFNMSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32531 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask, "__builtin_ia32_vfnmsubps128_mask", IX86_BUILTIN_VFNMSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32532 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fnmsub_v4sf_mask3, "__builtin_ia32_vfnmsubps128_mask3", IX86_BUILTIN_VFNMSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32533 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask, "__builtin_ia32_vfmaddsubpd256_mask", IX86_BUILTIN_VFMADDSUBPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32534 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_mask3, "__builtin_ia32_vfmaddsubpd256_mask3", IX86_BUILTIN_VFMADDSUBPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32535 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4df_maskz, "__builtin_ia32_vfmaddsubpd256_maskz", IX86_BUILTIN_VFMADDSUBPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32536 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask, "__builtin_ia32_vfmaddsubpd128_mask", IX86_BUILTIN_VFMADDSUBPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32537 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_mask3, "__builtin_ia32_vfmaddsubpd128_mask3", IX86_BUILTIN_VFMADDSUBPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32538 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v2df_maskz, "__builtin_ia32_vfmaddsubpd128_maskz", IX86_BUILTIN_VFMADDSUBPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32539 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask, "__builtin_ia32_vfmaddsubps256_mask", IX86_BUILTIN_VFMADDSUBPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32540 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_mask3, "__builtin_ia32_vfmaddsubps256_mask3", IX86_BUILTIN_VFMADDSUBPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32541 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v8sf_maskz, "__builtin_ia32_vfmaddsubps256_maskz", IX86_BUILTIN_VFMADDSUBPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32542 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask, "__builtin_ia32_vfmaddsubps128_mask", IX86_BUILTIN_VFMADDSUBPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32543 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_mask3, "__builtin_ia32_vfmaddsubps128_mask3", IX86_BUILTIN_VFMADDSUBPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32544 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmaddsub_v4sf_maskz, "__builtin_ia32_vfmaddsubps128_maskz", IX86_BUILTIN_VFMADDSUBPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32545 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4df_mask3, "__builtin_ia32_vfmsubaddpd256_mask3", IX86_BUILTIN_VFMSUBADDPD256_MASK3, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32546 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v2df_mask3, "__builtin_ia32_vfmsubaddpd128_mask3", IX86_BUILTIN_VFMSUBADDPD128_MASK3, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32547 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v8sf_mask3, "__builtin_ia32_vfmsubaddps256_mask3", IX86_BUILTIN_VFMSUBADDPS256_MASK3, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32548 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_fmsubadd_v4sf_mask3, "__builtin_ia32_vfmsubaddps128_mask3", IX86_BUILTIN_VFMSUBADDPS128_MASK3, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32549 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4df, "__builtin_ia32_insertf64x2_256_mask", IX86_BUILTIN_INSERTF64X2_256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V2DF_INT_V4DF_QI },
32550 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vinsertv4di, "__builtin_ia32_inserti64x2_256_mask", IX86_BUILTIN_INSERTI64X2_256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V2DI_INT_V4DI_QI },
32551 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv16hi_mask, "__builtin_ia32_psrav16hi_mask", IX86_BUILTIN_PSRAVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32552 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashrvv8hi_mask, "__builtin_ia32_psrav8hi_mask", IX86_BUILTIN_PSRAVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32553 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v16hi_mask, "__builtin_ia32_pmaddubsw256_mask", IX86_BUILTIN_PMADDUBSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V32QI_V32QI_V16HI_HI },
32554 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddubsw512v8hi_mask, "__builtin_ia32_pmaddubsw128_mask", IX86_BUILTIN_PMADDUBSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V16QI_V16QI_V8HI_QI },
32555 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v16hi_mask, "__builtin_ia32_pmaddwd256_mask", IX86_BUILTIN_PMADDWD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V16HI_V16HI_V8SI_QI },
32556 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512bw_pmaddwd512v8hi_mask, "__builtin_ia32_pmaddwd128_mask", IX86_BUILTIN_PMADDWD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V8HI_V8HI_V4SI_QI },
32557 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv16hi_mask, "__builtin_ia32_psrlv16hi_mask", IX86_BUILTIN_PSRLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32558 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_lshrvv8hi_mask, "__builtin_ia32_psrlv8hi_mask", IX86_BUILTIN_PSRLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32559 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_fix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2dq256_mask", IX86_BUILTIN_CVTPS2DQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32560 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_fix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2dq128_mask", IX86_BUILTIN_CVTPS2DQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32561 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv8sfv8si_mask, "__builtin_ia32_cvtps2udq256_mask", IX86_BUILTIN_CVTPS2UDQ256, UNKNOWN, (int) V8SI_FTYPE_V8SF_V8SI_QI },
32562 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ufix_notruncv4sfv4si_mask, "__builtin_ia32_cvtps2udq128_mask", IX86_BUILTIN_CVTPS2UDQ128, UNKNOWN, (int) V4SI_FTYPE_V4SF_V4SI_QI },
32563 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv4di_mask, "__builtin_ia32_cvtps2qq256_mask", IX86_BUILTIN_CVTPS2QQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32564 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2qqv2di_mask, "__builtin_ia32_cvtps2qq128_mask", IX86_BUILTIN_CVTPS2QQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32565 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv4di_mask, "__builtin_ia32_cvtps2uqq256_mask", IX86_BUILTIN_CVTPS2UQQ256, UNKNOWN, (int) V4DI_FTYPE_V4SF_V4DI_QI },
32566 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_cvtps2uqqv2di_mask, "__builtin_ia32_cvtps2uqq128_mask", IX86_BUILTIN_CVTPS2UQQ128, UNKNOWN, (int) V2DI_FTYPE_V4SF_V2DI_QI },
32567 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv8sf_mask, "__builtin_ia32_getmantps256_mask", IX86_BUILTIN_GETMANTPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32568 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4sf_mask, "__builtin_ia32_getmantps128_mask", IX86_BUILTIN_GETMANTPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32569 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv4df_mask, "__builtin_ia32_getmantpd256_mask", IX86_BUILTIN_GETMANTPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32570 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_getmantv2df_mask, "__builtin_ia32_getmantpd128_mask", IX86_BUILTIN_GETMANTPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32571 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movddup256_mask, "__builtin_ia32_movddup256_mask", IX86_BUILTIN_MOVDDUP256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32572 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_dupv2df_mask, "__builtin_ia32_movddup128_mask", IX86_BUILTIN_MOVDDUP128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32573 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movshdup256_mask, "__builtin_ia32_movshdup256_mask", IX86_BUILTIN_MOVSHDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32574 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movshdup_mask, "__builtin_ia32_movshdup128_mask", IX86_BUILTIN_MOVSHDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32575 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_movsldup256_mask, "__builtin_ia32_movsldup256_mask", IX86_BUILTIN_MOVSLDUP256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32576 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse3_movsldup_mask, "__builtin_ia32_movsldup128_mask", IX86_BUILTIN_MOVSLDUP128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32577 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4sf2_mask, "__builtin_ia32_cvtqq2ps256_mask", IX86_BUILTIN_CVTQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32578 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2sf2_mask, "__builtin_ia32_cvtqq2ps128_mask", IX86_BUILTIN_CVTQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32579 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4sf2_mask, "__builtin_ia32_cvtuqq2ps256_mask", IX86_BUILTIN_CVTUQQ2PS256, UNKNOWN, (int) V4SF_FTYPE_V4DI_V4SF_QI },
32580 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2sf2_mask, "__builtin_ia32_cvtuqq2ps128_mask", IX86_BUILTIN_CVTUQQ2PS128, UNKNOWN, (int) V4SF_FTYPE_V2DI_V4SF_QI },
32581 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv4div4df2_mask, "__builtin_ia32_cvtqq2pd256_mask", IX86_BUILTIN_CVTQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32582 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_floatv2div2df2_mask, "__builtin_ia32_cvtqq2pd128_mask", IX86_BUILTIN_CVTQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32583 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv4div4df2_mask, "__builtin_ia32_cvtuqq2pd256_mask", IX86_BUILTIN_CVTUQQ2PD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_QI },
32584 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ufloatv2div2df2_mask, "__builtin_ia32_cvtuqq2pd128_mask", IX86_BUILTIN_CVTUQQ2PD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_QI },
32585 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_mask, "__builtin_ia32_vpermt2varq256_mask", IX86_BUILTIN_VPERMT2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32586 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4di3_maskz, "__builtin_ia32_vpermt2varq256_maskz", IX86_BUILTIN_VPERMT2VARQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32587 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_mask, "__builtin_ia32_vpermt2vard256_mask", IX86_BUILTIN_VPERMT2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32588 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8si3_maskz, "__builtin_ia32_vpermt2vard256_maskz", IX86_BUILTIN_VPERMT2VARD256_MASKZ, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32589 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4di3_mask, "__builtin_ia32_vpermi2varq256_mask", IX86_BUILTIN_VPERMI2VARQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32590 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8si3_mask, "__builtin_ia32_vpermi2vard256_mask", IX86_BUILTIN_VPERMI2VARD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32591 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_mask, "__builtin_ia32_vpermt2varpd256_mask", IX86_BUILTIN_VPERMT2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32592 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4df3_maskz, "__builtin_ia32_vpermt2varpd256_maskz", IX86_BUILTIN_VPERMT2VARPD256_MASKZ, UNKNOWN, (int) V4DF_FTYPE_V4DI_V4DF_V4DF_QI },
32593 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_mask, "__builtin_ia32_vpermt2varps256_mask", IX86_BUILTIN_VPERMT2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32594 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv8sf3_maskz, "__builtin_ia32_vpermt2varps256_maskz", IX86_BUILTIN_VPERMT2VARPS256_MASKZ, UNKNOWN, (int) V8SF_FTYPE_V8SI_V8SF_V8SF_QI },
32595 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4df3_mask, "__builtin_ia32_vpermi2varpd256_mask", IX86_BUILTIN_VPERMI2VARPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32596 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv8sf3_mask, "__builtin_ia32_vpermi2varps256_mask", IX86_BUILTIN_VPERMI2VARPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32597 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_mask, "__builtin_ia32_vpermt2varq128_mask", IX86_BUILTIN_VPERMT2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32598 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2di3_maskz, "__builtin_ia32_vpermt2varq128_maskz", IX86_BUILTIN_VPERMT2VARQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32599 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_mask, "__builtin_ia32_vpermt2vard128_mask", IX86_BUILTIN_VPERMT2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32600 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4si3_maskz, "__builtin_ia32_vpermt2vard128_maskz", IX86_BUILTIN_VPERMT2VARD128_MASKZ, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32601 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2di3_mask, "__builtin_ia32_vpermi2varq128_mask", IX86_BUILTIN_VPERMI2VARQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32602 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4si3_mask, "__builtin_ia32_vpermi2vard128_mask", IX86_BUILTIN_VPERMI2VARD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32603 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_mask, "__builtin_ia32_vpermt2varpd128_mask", IX86_BUILTIN_VPERMT2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32604 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv2df3_maskz, "__builtin_ia32_vpermt2varpd128_maskz", IX86_BUILTIN_VPERMT2VARPD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DI_V2DF_V2DF_QI },
32605 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_mask, "__builtin_ia32_vpermt2varps128_mask", IX86_BUILTIN_VPERMT2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32606 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv4sf3_maskz, "__builtin_ia32_vpermt2varps128_maskz", IX86_BUILTIN_VPERMT2VARPS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SI_V4SF_V4SF_QI },
32607 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv2df3_mask, "__builtin_ia32_vpermi2varpd128_mask", IX86_BUILTIN_VPERMI2VARPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32608 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv4sf3_mask, "__builtin_ia32_vpermi2varps128_mask", IX86_BUILTIN_VPERMI2VARPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32609 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_pshufbv32qi3_mask, "__builtin_ia32_pshufb256_mask", IX86_BUILTIN_PSHUFB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32610 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ssse3_pshufbv16qi3_mask, "__builtin_ia32_pshufb128_mask", IX86_BUILTIN_PSHUFB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32611 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhwv3_mask, "__builtin_ia32_pshufhw256_mask", IX86_BUILTIN_PSHUFHW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32612 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufhw_mask, "__builtin_ia32_pshufhw128_mask", IX86_BUILTIN_PSHUFHW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32613 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflwv3_mask, "__builtin_ia32_pshuflw256_mask", IX86_BUILTIN_PSHUFLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32614 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshuflw_mask, "__builtin_ia32_pshuflw128_mask", IX86_BUILTIN_PSHUFLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32615 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufdv3_mask, "__builtin_ia32_pshufd256_mask", IX86_BUILTIN_PSHUFD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32616 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_pshufd_mask, "__builtin_ia32_pshufd128_mask", IX86_BUILTIN_PSHUFD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32617 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufpd256_mask, "__builtin_ia32_shufpd256_mask", IX86_BUILTIN_SHUFPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_INT_V4DF_QI },
32618 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_shufpd_mask, "__builtin_ia32_shufpd128_mask", IX86_BUILTIN_SHUFPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_V2DF_QI },
32619 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_shufps256_mask, "__builtin_ia32_shufps256_mask", IX86_BUILTIN_SHUFPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_INT_V8SF_QI },
32620 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse_shufps_mask, "__builtin_ia32_shufps128_mask", IX86_BUILTIN_SHUFPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_V4SF_QI },
32621 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4di_mask, "__builtin_ia32_prolvq256_mask", IX86_BUILTIN_PROLVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32622 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv2di_mask, "__builtin_ia32_prolvq128_mask", IX86_BUILTIN_PROLVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32623 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4di_mask, "__builtin_ia32_prolq256_mask", IX86_BUILTIN_PROLQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32624 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv2di_mask, "__builtin_ia32_prolq128_mask", IX86_BUILTIN_PROLQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32625 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4di_mask, "__builtin_ia32_prorvq256_mask", IX86_BUILTIN_PRORVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32626 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv2di_mask, "__builtin_ia32_prorvq128_mask", IX86_BUILTIN_PRORVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32627 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4di_mask, "__builtin_ia32_prorq256_mask", IX86_BUILTIN_PRORQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32628 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv2di_mask, "__builtin_ia32_prorq128_mask", IX86_BUILTIN_PRORQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_INT_V2DI_QI },
32629 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv2di_mask, "__builtin_ia32_psravq128_mask", IX86_BUILTIN_PSRAVQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32630 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4di_mask, "__builtin_ia32_psravq256_mask", IX86_BUILTIN_PSRAVQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32631 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4di_mask, "__builtin_ia32_psllv4di_mask", IX86_BUILTIN_PSLLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32632 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv2di_mask, "__builtin_ia32_psllv2di_mask", IX86_BUILTIN_PSLLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32633 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv8si_mask, "__builtin_ia32_psllv8si_mask", IX86_BUILTIN_PSLLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32634 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashlvv4si_mask, "__builtin_ia32_psllv4si_mask", IX86_BUILTIN_PSLLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32635 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv8si_mask, "__builtin_ia32_psrav8si_mask", IX86_BUILTIN_PSRAVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32636 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_ashrvv4si_mask, "__builtin_ia32_psrav4si_mask", IX86_BUILTIN_PSRAVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32637 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4di_mask, "__builtin_ia32_psrlv4di_mask", IX86_BUILTIN_PSRLVV4DI_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32638 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv2di_mask, "__builtin_ia32_psrlv2di_mask", IX86_BUILTIN_PSRLVV2DI_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32639 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv8si_mask, "__builtin_ia32_psrlv8si_mask", IX86_BUILTIN_PSRLVV8SI_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32640 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_lshrvv4si_mask, "__builtin_ia32_psrlv4si_mask", IX86_BUILTIN_PSRLVV4SI_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32641 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psrawi256_mask", IX86_BUILTIN_PSRAWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32642 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv16hi3_mask, "__builtin_ia32_psraw256_mask", IX86_BUILTIN_PSRAW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32643 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psrawi128_mask", IX86_BUILTIN_PSRAWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32644 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_ashrv8hi3_mask, "__builtin_ia32_psraw128_mask", IX86_BUILTIN_PSRAW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32645 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlwi256_mask", IX86_BUILTIN_PSRLWI256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_INT_V16HI_HI },
32646 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv16hi3_mask, "__builtin_ia32_psrlw256_mask", IX86_BUILTIN_PSRLW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V8HI_V16HI_HI },
32647 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlwi128_mask", IX86_BUILTIN_PSRLWI128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_INT_V8HI_QI },
32648 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_lshrv8hi3_mask, "__builtin_ia32_psrlw128_mask", IX86_BUILTIN_PSRLW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32649 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv8si_mask, "__builtin_ia32_prorvd256_mask", IX86_BUILTIN_PRORVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32650 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv8si_mask, "__builtin_ia32_prolvd256_mask", IX86_BUILTIN_PROLVD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32651 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv8si_mask, "__builtin_ia32_prord256_mask", IX86_BUILTIN_PRORD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32652 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv8si_mask, "__builtin_ia32_prold256_mask", IX86_BUILTIN_PROLD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_INT_V8SI_QI },
32653 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorvv4si_mask, "__builtin_ia32_prorvd128_mask", IX86_BUILTIN_PRORVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32654 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolvv4si_mask, "__builtin_ia32_prolvd128_mask", IX86_BUILTIN_PROLVD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32655 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rorv4si_mask, "__builtin_ia32_prord128_mask", IX86_BUILTIN_PRORD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32656 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_rolv4si_mask, "__builtin_ia32_prold128_mask", IX86_BUILTIN_PROLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_INT_V4SI_QI },
32657 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4df_mask, "__builtin_ia32_fpclasspd256_mask", IX86_BUILTIN_FPCLASSPD256, UNKNOWN, (int) QI_FTYPE_V4DF_INT_QI },
32658 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv2df_mask, "__builtin_ia32_fpclasspd128_mask", IX86_BUILTIN_FPCLASSPD128, UNKNOWN, (int) QI_FTYPE_V2DF_INT_QI },
32659 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv2df, "__builtin_ia32_fpclasssd", IX86_BUILTIN_FPCLASSSD, UNKNOWN, (int) QI_FTYPE_V2DF_INT },
32660 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv8sf_mask, "__builtin_ia32_fpclassps256_mask", IX86_BUILTIN_FPCLASSPS256, UNKNOWN, (int) QI_FTYPE_V8SF_INT_QI },
32661 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512dq_fpclassv4sf_mask, "__builtin_ia32_fpclassps128_mask", IX86_BUILTIN_FPCLASSPS128, UNKNOWN, (int) QI_FTYPE_V4SF_INT_QI },
32662 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vmfpclassv4sf, "__builtin_ia32_fpclassss", IX86_BUILTIN_FPCLASSSS, UNKNOWN, (int) QI_FTYPE_V4SF_INT },
32663 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv16qi, "__builtin_ia32_cvtb2mask128", IX86_BUILTIN_CVTB2MASK128, UNKNOWN, (int) HI_FTYPE_V16QI },
32664 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtb2maskv32qi, "__builtin_ia32_cvtb2mask256", IX86_BUILTIN_CVTB2MASK256, UNKNOWN, (int) SI_FTYPE_V32QI },
32665 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv8hi, "__builtin_ia32_cvtw2mask128", IX86_BUILTIN_CVTW2MASK128, UNKNOWN, (int) QI_FTYPE_V8HI },
32666 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtw2maskv16hi, "__builtin_ia32_cvtw2mask256", IX86_BUILTIN_CVTW2MASK256, UNKNOWN, (int) HI_FTYPE_V16HI },
32667 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv4si, "__builtin_ia32_cvtd2mask128", IX86_BUILTIN_CVTD2MASK128, UNKNOWN, (int) QI_FTYPE_V4SI },
32668 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtd2maskv8si, "__builtin_ia32_cvtd2mask256", IX86_BUILTIN_CVTD2MASK256, UNKNOWN, (int) QI_FTYPE_V8SI },
32669 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv2di, "__builtin_ia32_cvtq2mask128", IX86_BUILTIN_CVTQ2MASK128, UNKNOWN, (int) QI_FTYPE_V2DI },
32670 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtq2maskv4di, "__builtin_ia32_cvtq2mask256", IX86_BUILTIN_CVTQ2MASK256, UNKNOWN, (int) QI_FTYPE_V4DI },
32671 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv16qi, "__builtin_ia32_cvtmask2b128", IX86_BUILTIN_CVTMASK2B128, UNKNOWN, (int) V16QI_FTYPE_HI },
32672 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2bv32qi, "__builtin_ia32_cvtmask2b256", IX86_BUILTIN_CVTMASK2B256, UNKNOWN, (int) V32QI_FTYPE_SI },
32673 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv8hi, "__builtin_ia32_cvtmask2w128", IX86_BUILTIN_CVTMASK2W128, UNKNOWN, (int) V8HI_FTYPE_QI },
32674 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2wv16hi, "__builtin_ia32_cvtmask2w256", IX86_BUILTIN_CVTMASK2W256, UNKNOWN, (int) V16HI_FTYPE_HI },
32675 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv4si, "__builtin_ia32_cvtmask2d128", IX86_BUILTIN_CVTMASK2D128, UNKNOWN, (int) V4SI_FTYPE_QI },
32676 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2dv8si, "__builtin_ia32_cvtmask2d256", IX86_BUILTIN_CVTMASK2D256, UNKNOWN, (int) V8SI_FTYPE_QI },
32677 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv2di, "__builtin_ia32_cvtmask2q128", IX86_BUILTIN_CVTMASK2Q128, UNKNOWN, (int) V2DI_FTYPE_QI },
32678 { OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cvtmask2qv4di, "__builtin_ia32_cvtmask2q256", IX86_BUILTIN_CVTMASK2Q256, UNKNOWN, (int) V4DI_FTYPE_QI },
32679 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16qi3_mask, "__builtin_ia32_pcmpeqb128_mask", IX86_BUILTIN_PCMPEQB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32680 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv32qi3_mask, "__builtin_ia32_pcmpeqb256_mask", IX86_BUILTIN_PCMPEQB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32681 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8hi3_mask, "__builtin_ia32_pcmpeqw128_mask", IX86_BUILTIN_PCMPEQW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32682 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv16hi3_mask, "__builtin_ia32_pcmpeqw256_mask", IX86_BUILTIN_PCMPEQW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32683 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4si3_mask, "__builtin_ia32_pcmpeqd128_mask", IX86_BUILTIN_PCMPEQD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32684 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv8si3_mask, "__builtin_ia32_pcmpeqd256_mask", IX86_BUILTIN_PCMPEQD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32685 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv2di3_mask, "__builtin_ia32_pcmpeqq128_mask", IX86_BUILTIN_PCMPEQQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32686 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_eqv4di3_mask, "__builtin_ia32_pcmpeqq256_mask", IX86_BUILTIN_PCMPEQQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32687 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16qi3_mask, "__builtin_ia32_pcmpgtb128_mask", IX86_BUILTIN_PCMPGTB128_MASK, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32688 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv32qi3_mask, "__builtin_ia32_pcmpgtb256_mask", IX86_BUILTIN_PCMPGTB256_MASK, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32689 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8hi3_mask, "__builtin_ia32_pcmpgtw128_mask", IX86_BUILTIN_PCMPGTW128_MASK, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32690 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv16hi3_mask, "__builtin_ia32_pcmpgtw256_mask", IX86_BUILTIN_PCMPGTW256_MASK, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32691 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4si3_mask, "__builtin_ia32_pcmpgtd128_mask", IX86_BUILTIN_PCMPGTD128_MASK, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32692 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv8si3_mask, "__builtin_ia32_pcmpgtd256_mask", IX86_BUILTIN_PCMPGTD256_MASK, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32693 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv2di3_mask, "__builtin_ia32_pcmpgtq128_mask", IX86_BUILTIN_PCMPGTQ128_MASK, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32694 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_gtv4di3_mask, "__builtin_ia32_pcmpgtq256_mask", IX86_BUILTIN_PCMPGTQ256_MASK, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32695 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16qi3_mask, "__builtin_ia32_ptestmb128", IX86_BUILTIN_PTESTMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32696 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv32qi3_mask, "__builtin_ia32_ptestmb256", IX86_BUILTIN_PTESTMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32697 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8hi3_mask, "__builtin_ia32_ptestmw128", IX86_BUILTIN_PTESTMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32698 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv16hi3_mask, "__builtin_ia32_ptestmw256", IX86_BUILTIN_PTESTMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32699 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4si3_mask, "__builtin_ia32_ptestmd128", IX86_BUILTIN_PTESTMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32700 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv8si3_mask, "__builtin_ia32_ptestmd256", IX86_BUILTIN_PTESTMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32701 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv2di3_mask, "__builtin_ia32_ptestmq128", IX86_BUILTIN_PTESTMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32702 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testmv4di3_mask, "__builtin_ia32_ptestmq256", IX86_BUILTIN_PTESTMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32703 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16qi3_mask, "__builtin_ia32_ptestnmb128", IX86_BUILTIN_PTESTNMB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_HI },
32704 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv32qi3_mask, "__builtin_ia32_ptestnmb256", IX86_BUILTIN_PTESTNMB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_SI },
32705 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8hi3_mask, "__builtin_ia32_ptestnmw128", IX86_BUILTIN_PTESTNMW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_QI },
32706 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv16hi3_mask, "__builtin_ia32_ptestnmw256", IX86_BUILTIN_PTESTNMW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_HI },
32707 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4si3_mask, "__builtin_ia32_ptestnmd128", IX86_BUILTIN_PTESTNMD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_QI },
32708 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv8si3_mask, "__builtin_ia32_ptestnmd256", IX86_BUILTIN_PTESTNMD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_QI },
32709 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv2di3_mask, "__builtin_ia32_ptestnmq128", IX86_BUILTIN_PTESTNMQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_QI },
32710 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_testnmv4di3_mask, "__builtin_ia32_ptestnmq256", IX86_BUILTIN_PTESTNMQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_QI },
32711 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv2di, "__builtin_ia32_broadcastmb128", IX86_BUILTIN_PBROADCASTMB128, UNKNOWN, (int) V2DI_FTYPE_QI },
32712 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskb_vec_dupv4di, "__builtin_ia32_broadcastmb256", IX86_BUILTIN_PBROADCASTMB256, UNKNOWN, (int) V4DI_FTYPE_QI },
32713 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv4si, "__builtin_ia32_broadcastmw128", IX86_BUILTIN_PBROADCASTMW128, UNKNOWN, (int) V4SI_FTYPE_HI },
32714 { OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512CD, CODE_FOR_avx512cd_maskw_vec_dupv8si, "__builtin_ia32_broadcastmw256", IX86_BUILTIN_PBROADCASTMW256, UNKNOWN, (int) V8SI_FTYPE_HI },
32715 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4df_mask, "__builtin_ia32_compressdf256_mask", IX86_BUILTIN_COMPRESSPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32716 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2df_mask, "__builtin_ia32_compressdf128_mask", IX86_BUILTIN_COMPRESSPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32717 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8sf_mask, "__builtin_ia32_compresssf256_mask", IX86_BUILTIN_COMPRESSPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32718 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4sf_mask, "__builtin_ia32_compresssf128_mask", IX86_BUILTIN_COMPRESSPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32719 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4di_mask, "__builtin_ia32_compressdi256_mask", IX86_BUILTIN_PCOMPRESSQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32720 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv2di_mask, "__builtin_ia32_compressdi128_mask", IX86_BUILTIN_PCOMPRESSQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32721 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv8si_mask, "__builtin_ia32_compresssi256_mask", IX86_BUILTIN_PCOMPRESSD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32722 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_compressv4si_mask, "__builtin_ia32_compresssi128_mask", IX86_BUILTIN_PCOMPRESSD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32723 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_mask, "__builtin_ia32_expanddf256_mask", IX86_BUILTIN_EXPANDPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32724 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_mask, "__builtin_ia32_expanddf128_mask", IX86_BUILTIN_EXPANDPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32725 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_mask, "__builtin_ia32_expandsf256_mask", IX86_BUILTIN_EXPANDPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32726 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_mask, "__builtin_ia32_expandsf128_mask", IX86_BUILTIN_EXPANDPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32727 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_mask, "__builtin_ia32_expanddi256_mask", IX86_BUILTIN_PEXPANDQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32728 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_mask, "__builtin_ia32_expanddi128_mask", IX86_BUILTIN_PEXPANDQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32729 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_mask, "__builtin_ia32_expandsi256_mask", IX86_BUILTIN_PEXPANDD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32730 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_mask, "__builtin_ia32_expandsi128_mask", IX86_BUILTIN_PEXPANDD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32731 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4df_maskz, "__builtin_ia32_expanddf256_maskz", IX86_BUILTIN_EXPANDPD256Z, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32732 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2df_maskz, "__builtin_ia32_expanddf128_maskz", IX86_BUILTIN_EXPANDPD128Z, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32733 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8sf_maskz, "__builtin_ia32_expandsf256_maskz", IX86_BUILTIN_EXPANDPS256Z, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32734 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4sf_maskz, "__builtin_ia32_expandsf128_maskz", IX86_BUILTIN_EXPANDPS128Z, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32735 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4di_maskz, "__builtin_ia32_expanddi256_maskz", IX86_BUILTIN_PEXPANDQ256Z, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32736 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv2di_maskz, "__builtin_ia32_expanddi128_maskz", IX86_BUILTIN_PEXPANDQ128Z, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32737 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv8si_maskz, "__builtin_ia32_expandsi256_maskz", IX86_BUILTIN_PEXPANDD256Z, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32738 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_expandv4si_maskz, "__builtin_ia32_expandsi128_maskz", IX86_BUILTIN_PEXPANDD128Z, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32739 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8si3_mask, "__builtin_ia32_pmaxsd256_mask", IX86_BUILTIN_PMAXSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32740 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8si3_mask, "__builtin_ia32_pminsd256_mask", IX86_BUILTIN_PMINSD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32741 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8si3_mask, "__builtin_ia32_pmaxud256_mask", IX86_BUILTIN_PMAXUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32742 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8si3_mask, "__builtin_ia32_pminud256_mask", IX86_BUILTIN_PMINUD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32743 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4si3_mask, "__builtin_ia32_pmaxsd128_mask", IX86_BUILTIN_PMAXSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32744 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4si3_mask, "__builtin_ia32_pminsd128_mask", IX86_BUILTIN_PMINSD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32745 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4si3_mask, "__builtin_ia32_pmaxud128_mask", IX86_BUILTIN_PMAXUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32746 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4si3_mask, "__builtin_ia32_pminud128_mask", IX86_BUILTIN_PMINUD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32747 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv4di3_mask, "__builtin_ia32_pmaxsq256_mask", IX86_BUILTIN_PMAXSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32748 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv4di3_mask, "__builtin_ia32_pminsq256_mask", IX86_BUILTIN_PMINSQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32749 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv4di3_mask, "__builtin_ia32_pmaxuq256_mask", IX86_BUILTIN_PMAXUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32750 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv4di3_mask, "__builtin_ia32_pminuq256_mask", IX86_BUILTIN_PMINUQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32751 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv2di3_mask, "__builtin_ia32_pmaxsq128_mask", IX86_BUILTIN_PMAXSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32752 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv2di3_mask, "__builtin_ia32_pminsq128_mask", IX86_BUILTIN_PMINSQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32753 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv2di3_mask, "__builtin_ia32_pmaxuq128_mask", IX86_BUILTIN_PMAXUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32754 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv2di3_mask, "__builtin_ia32_pminuq128_mask", IX86_BUILTIN_PMINUQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32755 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv32qi3_mask, "__builtin_ia32_pminsb256_mask", IX86_BUILTIN_PMINSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32756 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv32qi3_mask, "__builtin_ia32_pminub256_mask", IX86_BUILTIN_PMINUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32757 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv32qi3_mask, "__builtin_ia32_pmaxsb256_mask", IX86_BUILTIN_PMAXSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32758 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv32qi3_mask, "__builtin_ia32_pmaxub256_mask", IX86_BUILTIN_PMAXUB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32759 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16qi3_mask, "__builtin_ia32_pminsb128_mask", IX86_BUILTIN_PMINSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32760 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16qi3_mask, "__builtin_ia32_pminub128_mask", IX86_BUILTIN_PMINUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32761 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16qi3_mask, "__builtin_ia32_pmaxsb128_mask", IX86_BUILTIN_PMAXSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32762 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16qi3_mask, "__builtin_ia32_pmaxub128_mask", IX86_BUILTIN_PMAXUB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32763 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv16hi3_mask, "__builtin_ia32_pminsw256_mask", IX86_BUILTIN_PMINSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32764 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv16hi3_mask, "__builtin_ia32_pminuw256_mask", IX86_BUILTIN_PMINUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32765 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv16hi3_mask, "__builtin_ia32_pmaxsw256_mask", IX86_BUILTIN_PMAXSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32766 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv16hi3_mask, "__builtin_ia32_pmaxuw256_mask", IX86_BUILTIN_PMAXUW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32767 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sminv8hi3_mask, "__builtin_ia32_pminsw128_mask", IX86_BUILTIN_PMINSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32768 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_uminv8hi3_mask, "__builtin_ia32_pminuw128_mask", IX86_BUILTIN_PMINUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32769 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_smaxv8hi3_mask, "__builtin_ia32_pmaxsw128_mask", IX86_BUILTIN_PMAXSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32770 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_umaxv8hi3_mask, "__builtin_ia32_pmaxuw128_mask", IX86_BUILTIN_PMAXUW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32771 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4di_mask, "__builtin_ia32_vpconflictdi_256_mask", IX86_BUILTIN_VPCONFLICTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32772 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv8si_mask, "__builtin_ia32_vpconflictsi_256_mask", IX86_BUILTIN_VPCONFLICTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32773 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4di2_mask, "__builtin_ia32_vplzcntq_256_mask", IX86_BUILTIN_VPCLZCNTQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32774 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv8si2_mask, "__builtin_ia32_vplzcntd_256_mask", IX86_BUILTIN_VPCLZCNTD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32775 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhpd256_mask, "__builtin_ia32_unpckhpd256_mask", IX86_BUILTIN_UNPCKHPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32776 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpckhpd128_mask, "__builtin_ia32_unpckhpd128_mask", IX86_BUILTIN_UNPCKHPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32777 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpckhps256_mask, "__builtin_ia32_unpckhps256_mask", IX86_BUILTIN_UNPCKHPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32778 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4sf_mask, "__builtin_ia32_unpckhps128_mask", IX86_BUILTIN_UNPCKHPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32779 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklpd256_mask, "__builtin_ia32_unpcklpd256_mask", IX86_BUILTIN_UNPCKLPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_V4DF_QI },
32780 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_unpcklpd128_mask, "__builtin_ia32_unpcklpd128_mask", IX86_BUILTIN_UNPCKLPD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_QI },
32781 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_unpcklps256_mask, "__builtin_ia32_unpcklps256_mask", IX86_BUILTIN_UNPCKLPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_V8SF_QI },
32782 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv2di_mask, "__builtin_ia32_vpconflictdi_128_mask", IX86_BUILTIN_VPCONFLICTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32783 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_conflictv4si_mask, "__builtin_ia32_vpconflictsi_128_mask", IX86_BUILTIN_VPCONFLICTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32784 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv2di2_mask, "__builtin_ia32_vplzcntq_128_mask", IX86_BUILTIN_VPCLZCNTQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32785 { OPTION_MASK_ISA_AVX512CD | OPTION_MASK_ISA_AVX512VL, CODE_FOR_clzv4si2_mask, "__builtin_ia32_vplzcntd_128_mask", IX86_BUILTIN_VPCLZCNTD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32786 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_unpcklps128_mask, "__builtin_ia32_unpcklps128_mask", IX86_BUILTIN_UNPCKLPS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_QI },
32787 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv8si_mask, "__builtin_ia32_alignd256_mask", IX86_BUILTIN_ALIGND256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_INT_V8SI_QI },
32788 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4di_mask, "__builtin_ia32_alignq256_mask", IX86_BUILTIN_ALIGNQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_INT_V4DI_QI },
32789 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv4si_mask, "__builtin_ia32_alignd128_mask", IX86_BUILTIN_ALIGND128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_INT_V4SI_QI },
32790 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_alignv2di_mask, "__builtin_ia32_alignq128_mask", IX86_BUILTIN_ALIGNQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_INT_V2DI_QI },
32791 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph256_mask, "__builtin_ia32_vcvtps2ph256_mask", IX86_BUILTIN_CVTPS2PH256_MASK, UNKNOWN, (int) V8HI_FTYPE_V8SF_INT_V8HI_QI },
32792 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtps2ph_mask, "__builtin_ia32_vcvtps2ph_mask", IX86_BUILTIN_CVTPS2PH_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SF_INT_V8HI_QI },
32793 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps_mask, "__builtin_ia32_vcvtph2ps_mask", IX86_BUILTIN_CVTPH2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V8HI_V4SF_QI },
32794 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vcvtph2ps256_mask, "__builtin_ia32_vcvtph2ps256_mask", IX86_BUILTIN_CVTPH2PS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8HI_V8SF_QI },
32795 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv4si_mask, "__builtin_ia32_punpckhdq128_mask", IX86_BUILTIN_PUNPCKHDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32796 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv8si_mask, "__builtin_ia32_punpckhdq256_mask", IX86_BUILTIN_PUNPCKHDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32797 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv2di_mask, "__builtin_ia32_punpckhqdq128_mask", IX86_BUILTIN_PUNPCKHQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32798 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv4di_mask, "__builtin_ia32_punpckhqdq256_mask", IX86_BUILTIN_PUNPCKHQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32799 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv4si_mask, "__builtin_ia32_punpckldq128_mask", IX86_BUILTIN_PUNPCKLDQ128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32800 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv8si_mask, "__builtin_ia32_punpckldq256_mask", IX86_BUILTIN_PUNPCKLDQ256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32801 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv2di_mask, "__builtin_ia32_punpcklqdq128_mask", IX86_BUILTIN_PUNPCKLQDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
32802 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv4di_mask, "__builtin_ia32_punpcklqdq256_mask", IX86_BUILTIN_PUNPCKLQDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32803 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv16qi_mask, "__builtin_ia32_punpckhbw128_mask", IX86_BUILTIN_PUNPCKHBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32804 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv32qi_mask, "__builtin_ia32_punpckhbw256_mask", IX86_BUILTIN_PUNPCKHBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32805 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_highv8hi_mask, "__builtin_ia32_punpckhwd128_mask", IX86_BUILTIN_PUNPCKHWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32806 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_highv16hi_mask, "__builtin_ia32_punpckhwd256_mask", IX86_BUILTIN_PUNPCKHWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32807 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv16qi_mask, "__builtin_ia32_punpcklbw128_mask", IX86_BUILTIN_PUNPCKLBW128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32808 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv32qi_mask, "__builtin_ia32_punpcklbw256_mask", IX86_BUILTIN_PUNPCKLBW256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32809 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_interleave_lowv8hi_mask, "__builtin_ia32_punpcklwd128_mask", IX86_BUILTIN_PUNPCKLWD128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32810 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_interleave_lowv16hi_mask, "__builtin_ia32_punpcklwd256_mask", IX86_BUILTIN_PUNPCKLWD256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32811 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv16hi_mask, "__builtin_ia32_psllv16hi_mask", IX86_BUILTIN_PSLLVV16HI, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32812 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ashlvv8hi_mask, "__builtin_ia32_psllv8hi_mask", IX86_BUILTIN_PSLLVV8HI, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32813 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packssdw_mask, "__builtin_ia32_packssdw256_mask", IX86_BUILTIN_PACKSSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32814 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_packssdw_mask, "__builtin_ia32_packssdw128_mask", IX86_BUILTIN_PACKSSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32815 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_packusdw_mask, "__builtin_ia32_packusdw256_mask", IX86_BUILTIN_PACKUSDW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V8SI_V8SI_V16HI_HI },
32816 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_packusdw_mask, "__builtin_ia32_packusdw128_mask", IX86_BUILTIN_PACKUSDW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V4SI_V4SI_V8HI_QI },
32817 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv32qi3_mask, "__builtin_ia32_pavgb256_mask", IX86_BUILTIN_PAVGB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
32818 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_uavgv16hi3_mask, "__builtin_ia32_pavgw256_mask", IX86_BUILTIN_PAVGW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_V16HI_HI },
32819 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv16qi3_mask, "__builtin_ia32_pavgb128_mask", IX86_BUILTIN_PAVGB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
32820 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_uavgv8hi3_mask, "__builtin_ia32_pavgw128_mask", IX86_BUILTIN_PAVGW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_V8HI_QI },
32821 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8sf_mask, "__builtin_ia32_permvarsf256_mask", IX86_BUILTIN_VPERMVARSF256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32822 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4df_mask, "__builtin_ia32_permvardf256_mask", IX86_BUILTIN_VPERMVARDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32823 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4df_mask, "__builtin_ia32_permdf256_mask", IX86_BUILTIN_VPERMDF256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32824 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv32qi2_mask, "__builtin_ia32_pabsb256_mask", IX86_BUILTIN_PABSB256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32825 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16qi2_mask, "__builtin_ia32_pabsb128_mask", IX86_BUILTIN_PABSB128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32826 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv16hi2_mask, "__builtin_ia32_pabsw256_mask", IX86_BUILTIN_PABSW256_MASK, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32827 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_absv8hi2_mask, "__builtin_ia32_pabsw128_mask", IX86_BUILTIN_PABSW128_MASK, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32828 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv2df3_mask, "__builtin_ia32_vpermilvarpd_mask", IX86_BUILTIN_VPERMILVARPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DI_V2DF_QI },
32829 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4sf3_mask, "__builtin_ia32_vpermilvarps_mask", IX86_BUILTIN_VPERMILVARPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SI_V4SF_QI },
32830 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv4df3_mask, "__builtin_ia32_vpermilvarpd256_mask", IX86_BUILTIN_VPERMILVARPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DI_V4DF_QI },
32831 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilvarv8sf3_mask, "__builtin_ia32_vpermilvarps256_mask", IX86_BUILTIN_VPERMILVARPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SI_V8SF_QI },
32832 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv2df_mask, "__builtin_ia32_vpermilpd_mask", IX86_BUILTIN_VPERMILPD_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT_V2DF_QI },
32833 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4sf_mask, "__builtin_ia32_vpermilps_mask", IX86_BUILTIN_VPERMILPS_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_V4SF_QI },
32834 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv4df_mask, "__builtin_ia32_vpermilpd256_mask", IX86_BUILTIN_VPERMILPD256_MASK, UNKNOWN, (int) V4DF_FTYPE_V4DF_INT_V4DF_QI },
32835 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_vpermilv8sf_mask, "__builtin_ia32_vpermilps256_mask", IX86_BUILTIN_VPERMILPS256_MASK, UNKNOWN, (int) V8SF_FTYPE_V8SF_INT_V8SF_QI },
32836 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4di, "__builtin_ia32_blendmq_256_mask", IX86_BUILTIN_BLENDMQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_QI },
32837 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8si, "__builtin_ia32_blendmd_256_mask", IX86_BUILTIN_BLENDMD256, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_QI },
32838 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4df, "__builtin_ia32_blendmpd_256_mask", IX86_BUILTIN_BLENDMPD256, UNKNOWN, (int) V4DF_FTYPE_V4DF_V4DF_QI },
32839 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8sf, "__builtin_ia32_blendmps_256_mask", IX86_BUILTIN_BLENDMPS256, UNKNOWN, (int) V8SF_FTYPE_V8SF_V8SF_QI },
32840 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2di, "__builtin_ia32_blendmq_128_mask", IX86_BUILTIN_BLENDMQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_QI },
32841 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4si, "__builtin_ia32_blendmd_128_mask", IX86_BUILTIN_BLENDMD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_QI },
32842 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv2df, "__builtin_ia32_blendmpd_128_mask", IX86_BUILTIN_BLENDMPD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_QI },
32843 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv4sf, "__builtin_ia32_blendmps_128_mask", IX86_BUILTIN_BLENDMPS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_QI },
32844 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16hi, "__builtin_ia32_blendmw_256_mask", IX86_BUILTIN_BLENDMW256, UNKNOWN, (int) V16HI_FTYPE_V16HI_V16HI_HI },
32845 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv32qi, "__builtin_ia32_blendmb_256_mask", IX86_BUILTIN_BLENDMB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_SI },
32846 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv8hi, "__builtin_ia32_blendmw_128_mask", IX86_BUILTIN_BLENDMW128, UNKNOWN, (int) V8HI_FTYPE_V8HI_V8HI_QI },
32847 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_blendmv16qi, "__builtin_ia32_blendmb_128_mask", IX86_BUILTIN_BLENDMB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_HI },
32848 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv8si3_mask, "__builtin_ia32_pmulld256_mask", IX86_BUILTIN_PMULLD256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32849 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_mulv4si3_mask, "__builtin_ia32_pmulld128_mask", IX86_BUILTIN_PMULLD128_MASK, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI_V4SI_QI },
32850 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v8si_mask, "__builtin_ia32_pmuludq256_mask", IX86_BUILTIN_PMULUDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32851 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_smult_even_v8si_mask, "__builtin_ia32_pmuldq256_mask", IX86_BUILTIN_PMULDQ256_MASK, UNKNOWN, (int) V4DI_FTYPE_V8SI_V8SI_V4DI_QI },
32852 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse4_1_mulv2siv2di3_mask, "__builtin_ia32_pmuldq128_mask", IX86_BUILTIN_PMULDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32853 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_vec_widen_umult_even_v4si_mask, "__builtin_ia32_pmuludq128_mask", IX86_BUILTIN_PMULUDQ128_MASK, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI_V2DI_QI },
32854 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx_cvtpd2ps256_mask, "__builtin_ia32_cvtpd2ps256_mask", IX86_BUILTIN_CVTPD2PS256_MASK, UNKNOWN, (int) V4SF_FTYPE_V4DF_V4SF_QI },
32855 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_sse2_cvtpd2ps_mask, "__builtin_ia32_cvtpd2ps_mask", IX86_BUILTIN_CVTPD2PS_MASK, UNKNOWN, (int) V4SF_FTYPE_V2DF_V4SF_QI },
32856 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv8si_mask, "__builtin_ia32_permvarsi256_mask", IX86_BUILTIN_VPERMVARSI256_MASK, UNKNOWN, (int) V8SI_FTYPE_V8SI_V8SI_V8SI_QI },
32857 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx2_permvarv4di_mask, "__builtin_ia32_permvardi256_mask", IX86_BUILTIN_VPERMVARDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
32858 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permv4di_mask, "__builtin_ia32_permdi256_mask", IX86_BUILTIN_VPERMDI256_MASK, UNKNOWN, (int) V4DI_FTYPE_V4DI_INT_V4DI_QI },
32859 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4di3_mask, "__builtin_ia32_cmpq256_mask", IX86_BUILTIN_CMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32860 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8si3_mask, "__builtin_ia32_cmpd256_mask", IX86_BUILTIN_CMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32861 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4di3_mask, "__builtin_ia32_ucmpq256_mask", IX86_BUILTIN_UCMPQ256, UNKNOWN, (int) QI_FTYPE_V4DI_V4DI_INT_QI },
32862 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8si3_mask, "__builtin_ia32_ucmpd256_mask", IX86_BUILTIN_UCMPD256, UNKNOWN, (int) QI_FTYPE_V8SI_V8SI_INT_QI },
32863 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv32qi3_mask, "__builtin_ia32_cmpb256_mask", IX86_BUILTIN_CMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32864 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16hi3_mask, "__builtin_ia32_cmpw256_mask", IX86_BUILTIN_CMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32865 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv32qi3_mask, "__builtin_ia32_ucmpb256_mask", IX86_BUILTIN_UCMPB256, UNKNOWN, (int) SI_FTYPE_V32QI_V32QI_INT_SI },
32866 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16hi3_mask, "__builtin_ia32_ucmpw256_mask", IX86_BUILTIN_UCMPW256, UNKNOWN, (int) HI_FTYPE_V16HI_V16HI_INT_HI },
32867 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4df3_mask, "__builtin_ia32_cmppd256_mask", IX86_BUILTIN_CMPPD256_MASK, UNKNOWN, (int) QI_FTYPE_V4DF_V4DF_INT_QI },
32868 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8sf3_mask, "__builtin_ia32_cmpps256_mask", IX86_BUILTIN_CMPPS256_MASK, UNKNOWN, (int) QI_FTYPE_V8SF_V8SF_INT_QI },
32869 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2di3_mask, "__builtin_ia32_cmpq128_mask", IX86_BUILTIN_CMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32870 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4si3_mask, "__builtin_ia32_cmpd128_mask", IX86_BUILTIN_CMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32871 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv2di3_mask, "__builtin_ia32_ucmpq128_mask", IX86_BUILTIN_UCMPQ128, UNKNOWN, (int) QI_FTYPE_V2DI_V2DI_INT_QI },
32872 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv4si3_mask, "__builtin_ia32_ucmpd128_mask", IX86_BUILTIN_UCMPD128, UNKNOWN, (int) QI_FTYPE_V4SI_V4SI_INT_QI },
32873 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv16qi3_mask, "__builtin_ia32_cmpb128_mask", IX86_BUILTIN_CMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32874 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv8hi3_mask, "__builtin_ia32_cmpw128_mask", IX86_BUILTIN_CMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32875 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv16qi3_mask, "__builtin_ia32_ucmpb128_mask", IX86_BUILTIN_UCMPB128, UNKNOWN, (int) HI_FTYPE_V16QI_V16QI_INT_HI },
32876 { OPTION_MASK_ISA_AVX512BW | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_ucmpv8hi3_mask, "__builtin_ia32_ucmpw128_mask", IX86_BUILTIN_UCMPW128, UNKNOWN, (int) QI_FTYPE_V8HI_V8HI_INT_QI },
32877 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv2df3_mask, "__builtin_ia32_cmppd128_mask", IX86_BUILTIN_CMPPD128_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI },
32878 { OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_cmpv4sf3_mask, "__builtin_ia32_cmpps128_mask", IX86_BUILTIN_CMPPS128_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI },
32880 /* AVX512DQ. */
32881 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask, "__builtin_ia32_broadcastf32x2_512_mask", IX86_BUILTIN_BROADCASTF32x2_512, UNKNOWN, (int) V16SF_FTYPE_V4SF_V16SF_HI },
32882 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask, "__builtin_ia32_broadcasti32x2_512_mask", IX86_BUILTIN_BROADCASTI32x2_512, UNKNOWN, (int) V16SI_FTYPE_V4SI_V16SI_HI },
32883 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8df_mask_1, "__builtin_ia32_broadcastf64x2_512_mask", IX86_BUILTIN_BROADCASTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V2DF_V8DF_QI },
32884 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv8di_mask_1, "__builtin_ia32_broadcasti64x2_512_mask", IX86_BUILTIN_BROADCASTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V2DI_V8DI_QI },
32885 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16sf_mask_1, "__builtin_ia32_broadcastf32x8_512_mask", IX86_BUILTIN_BROADCASTF32X8_512, UNKNOWN, (int) V16SF_FTYPE_V8SF_V16SF_HI },
32886 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_broadcastv16si_mask_1, "__builtin_ia32_broadcasti32x8_512_mask", IX86_BUILTIN_BROADCASTI32X8_512, UNKNOWN, (int) V16SI_FTYPE_V8SI_V16SI_HI },
32887 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf64x2_mask, "__builtin_ia32_extractf64x2_512_mask", IX86_BUILTIN_EXTRACTF64X2_512, UNKNOWN, (int) V2DF_FTYPE_V8DF_INT_V2DF_QI },
32888 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextractf32x8_mask, "__builtin_ia32_extractf32x8_mask", IX86_BUILTIN_EXTRACTF32X8, UNKNOWN, (int) V8SF_FTYPE_V16SF_INT_V8SF_QI },
32889 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti64x2_mask, "__builtin_ia32_extracti64x2_512_mask", IX86_BUILTIN_EXTRACTI64X2_512, UNKNOWN, (int) V2DI_FTYPE_V8DI_INT_V2DI_QI },
32890 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vextracti32x8_mask, "__builtin_ia32_extracti32x8_mask", IX86_BUILTIN_EXTRACTI32X8, UNKNOWN, (int) V8SI_FTYPE_V16SI_INT_V8SI_QI },
32891 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv8df_mask, "__builtin_ia32_reducepd512_mask", IX86_BUILTIN_REDUCEPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI },
32892 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_reducepv16sf_mask, "__builtin_ia32_reduceps512_mask", IX86_BUILTIN_REDUCEPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI },
32893 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_mulv8di3_mask, "__builtin_ia32_pmullq512_mask", IX86_BUILTIN_PMULLQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
32894 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv8df3_mask, "__builtin_ia32_xorpd512_mask", IX86_BUILTIN_XORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32895 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_xorv16sf3_mask, "__builtin_ia32_xorps512_mask", IX86_BUILTIN_XORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32896 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv8df3_mask, "__builtin_ia32_orpd512_mask", IX86_BUILTIN_ORPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32897 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_iorv16sf3_mask, "__builtin_ia32_orps512_mask", IX86_BUILTIN_ORPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32898 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv8df3_mask, "__builtin_ia32_andpd512_mask", IX86_BUILTIN_ANDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI },
32899 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_andv16sf3_mask, "__builtin_ia32_andps512_mask", IX86_BUILTIN_ANDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32900 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv8df3_mask, "__builtin_ia32_andnpd512_mask", IX86_BUILTIN_ANDNPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI},
32901 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_andnotv16sf3_mask, "__builtin_ia32_andnps512_mask", IX86_BUILTIN_ANDNPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI },
32902 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf32x8_mask, "__builtin_ia32_insertf32x8_mask", IX86_BUILTIN_INSERTF32X8, UNKNOWN, (int) V16SF_FTYPE_V16SF_V8SF_INT_V16SF_HI },
32903 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti32x8_mask, "__builtin_ia32_inserti32x8_mask", IX86_BUILTIN_INSERTI32X8, UNKNOWN, (int) V16SI_FTYPE_V16SI_V8SI_INT_V16SI_HI },
32904 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinsertf64x2_mask, "__builtin_ia32_insertf64x2_512_mask", IX86_BUILTIN_INSERTF64X2_512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V2DF_INT_V8DF_QI },
32905 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_vinserti64x2_mask, "__builtin_ia32_inserti64x2_512_mask", IX86_BUILTIN_INSERTI64X2_512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V2DI_INT_V8DI_QI },
32906 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv8df_mask, "__builtin_ia32_fpclasspd512_mask", IX86_BUILTIN_FPCLASSPD512, UNKNOWN, (int) QI_FTYPE_V8DF_INT_QI },
32907 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_fpclassv16sf_mask, "__builtin_ia32_fpclassps512_mask", IX86_BUILTIN_FPCLASSPS512, UNKNOWN, (int) HI_FTYPE_V16SF_INT_HI },
32908 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtd2maskv16si, "__builtin_ia32_cvtd2mask512", IX86_BUILTIN_CVTD2MASK512, UNKNOWN, (int) HI_FTYPE_V16SI },
32909 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtq2maskv8di, "__builtin_ia32_cvtq2mask512", IX86_BUILTIN_CVTQ2MASK512, UNKNOWN, (int) QI_FTYPE_V8DI },
32910 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2dv16si, "__builtin_ia32_cvtmask2d512", IX86_BUILTIN_CVTMASK2D512, UNKNOWN, (int) V16SI_FTYPE_HI },
32911 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512f_cvtmask2qv8di, "__builtin_ia32_cvtmask2q512", IX86_BUILTIN_CVTMASK2Q512, UNKNOWN, (int) V8DI_FTYPE_QI },
32913 /* AVX512BW. */
32914 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpcksi, "__builtin_ia32_kunpcksi", IX86_BUILTIN_KUNPCKWD, UNKNOWN, (int) SI_FTYPE_SI_SI },
32915 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_kunpckdi, "__builtin_ia32_kunpckdi", IX86_BUILTIN_KUNPCKDQ, UNKNOWN, (int) DI_FTYPE_DI_DI },
32916 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packusdw_mask, "__builtin_ia32_packusdw512_mask", IX86_BUILTIN_PACKUSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32917 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlv4ti3, "__builtin_ia32_pslldq512", IX86_BUILTIN_PSLLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32918 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrv4ti3, "__builtin_ia32_psrldq512", IX86_BUILTIN_PSRLDQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_INT_CONVERT },
32919 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packssdw_mask, "__builtin_ia32_packssdw512_mask", IX86_BUILTIN_PACKSSDW512, UNKNOWN, (int) V32HI_FTYPE_V16SI_V16SI_V32HI_SI },
32920 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv4ti, "__builtin_ia32_palignr512", IX86_BUILTIN_PALIGNR512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_CONVERT },
32921 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_palignrv64qi_mask, "__builtin_ia32_palignr512_mask", IX86_BUILTIN_PALIGNR512_MASK, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_INT_V8DI_DI_CONVERT },
32922 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_loaddquv32hi_mask, "__builtin_ia32_movdquhi512_mask", IX86_BUILTIN_MOVDQUHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32923 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_loaddquv64qi_mask, "__builtin_ia32_movdquqi512_mask", IX86_BUILTIN_MOVDQUQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32924 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512f_psadbw, "__builtin_ia32_psadbw512", IX86_BUILTIN_PSADBW512, UNKNOWN, (int) V8DI_FTYPE_V64QI_V64QI },
32925 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_dbpsadbwv32hi_mask, "__builtin_ia32_dbpsadbw512_mask", IX86_BUILTIN_DBPSADBW512, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_INT_V32HI_SI },
32926 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv64qi_mask, "__builtin_ia32_pbroadcastb512_mask", IX86_BUILTIN_PBROADCASTB512, UNKNOWN, (int) V64QI_FTYPE_V16QI_V64QI_DI },
32927 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv64qi_mask, "__builtin_ia32_pbroadcastb512_gpr_mask", IX86_BUILTIN_PBROADCASTB512_GPR, UNKNOWN, (int) V64QI_FTYPE_QI_V64QI_DI },
32928 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dupv32hi_mask, "__builtin_ia32_pbroadcastw512_mask", IX86_BUILTIN_PBROADCASTW512, UNKNOWN, (int) V32HI_FTYPE_V8HI_V32HI_SI },
32929 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vec_dup_gprv32hi_mask, "__builtin_ia32_pbroadcastw512_gpr_mask", IX86_BUILTIN_PBROADCASTW512_GPR, UNKNOWN, (int) V32HI_FTYPE_HI_V32HI_SI },
32930 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sign_extendv32qiv32hi2_mask, "__builtin_ia32_pmovsxbw512_mask", IX86_BUILTIN_PMOVSXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32931 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_zero_extendv32qiv32hi2_mask, "__builtin_ia32_pmovzxbw512_mask", IX86_BUILTIN_PMOVZXBW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32QI_V32HI_SI },
32932 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_permvarv32hi_mask, "__builtin_ia32_permvarhi512_mask", IX86_BUILTIN_VPERMVARHI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32933 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_mask, "__builtin_ia32_vpermt2varhi512_mask", IX86_BUILTIN_VPERMT2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32934 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermt2varv32hi3_maskz, "__builtin_ia32_vpermt2varhi512_maskz", IX86_BUILTIN_VPERMT2VARHI512_MASKZ, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32935 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_vpermi2varv32hi3_mask, "__builtin_ia32_vpermi2varhi512_mask", IX86_BUILTIN_VPERMI2VARHI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32936 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv64qi3_mask, "__builtin_ia32_pavgb512_mask", IX86_BUILTIN_PAVGB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32937 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_uavgv32hi3_mask, "__builtin_ia32_pavgw512_mask", IX86_BUILTIN_PAVGW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32938 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv64qi3_mask, "__builtin_ia32_paddb512_mask", IX86_BUILTIN_PADDB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32939 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv64qi3_mask, "__builtin_ia32_psubb512_mask", IX86_BUILTIN_PSUBB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32940 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv64qi3_mask, "__builtin_ia32_psubsb512_mask", IX86_BUILTIN_PSUBSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32941 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv64qi3_mask, "__builtin_ia32_paddsb512_mask", IX86_BUILTIN_PADDSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32942 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv64qi3_mask, "__builtin_ia32_psubusb512_mask", IX86_BUILTIN_PSUBUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32943 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv64qi3_mask, "__builtin_ia32_paddusb512_mask", IX86_BUILTIN_PADDUSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32944 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_subv32hi3_mask, "__builtin_ia32_psubw512_mask", IX86_BUILTIN_PSUBW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32945 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_addv32hi3_mask, "__builtin_ia32_paddw512_mask", IX86_BUILTIN_PADDW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32946 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_sssubv32hi3_mask, "__builtin_ia32_psubsw512_mask", IX86_BUILTIN_PSUBSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32947 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ssaddv32hi3_mask, "__builtin_ia32_paddsw512_mask", IX86_BUILTIN_PADDSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32948 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ussubv32hi3_mask, "__builtin_ia32_psubusw512_mask", IX86_BUILTIN_PSUBUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32949 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_usaddv32hi3_mask, "__builtin_ia32_paddusw512_mask", IX86_BUILTIN_PADDUSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32950 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv32hi3_mask, "__builtin_ia32_pmaxuw512_mask", IX86_BUILTIN_PMAXUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32951 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv32hi3_mask, "__builtin_ia32_pmaxsw512_mask", IX86_BUILTIN_PMAXSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32952 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv32hi3_mask, "__builtin_ia32_pminuw512_mask", IX86_BUILTIN_PMINUW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32953 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv32hi3_mask, "__builtin_ia32_pminsw512_mask", IX86_BUILTIN_PMINSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32954 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umaxv64qi3_mask, "__builtin_ia32_pmaxub512_mask", IX86_BUILTIN_PMAXUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32955 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smaxv64qi3_mask, "__builtin_ia32_pmaxsb512_mask", IX86_BUILTIN_PMAXSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32956 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_uminv64qi3_mask, "__builtin_ia32_pminub512_mask", IX86_BUILTIN_PMINUB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32957 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_sminv64qi3_mask, "__builtin_ia32_pminsb512_mask", IX86_BUILTIN_PMINSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32958 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovwb512_mask", IX86_BUILTIN_PMOVWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32959 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ss_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovswb512_mask", IX86_BUILTIN_PMOVSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32960 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_us_truncatev32hiv32qi2_mask, "__builtin_ia32_pmovuswb512_mask", IX86_BUILTIN_PMOVUSWB512, UNKNOWN, (int) V32QI_FTYPE_V32HI_V32QI_SI },
32961 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_umulhrswv32hi3_mask, "__builtin_ia32_pmulhrsw512_mask", IX86_BUILTIN_PMULHRSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32962 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_umulv32hi3_highpart_mask, "__builtin_ia32_pmulhuw512_mask" , IX86_BUILTIN_PMULHUW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32963 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_smulv32hi3_highpart_mask, "__builtin_ia32_pmulhw512_mask" , IX86_BUILTIN_PMULHW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32964 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_mulv32hi3_mask, "__builtin_ia32_pmullw512_mask", IX86_BUILTIN_PMULLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32965 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllwi512_mask", IX86_BUILTIN_PSLLWI512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32966 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashlv32hi3_mask, "__builtin_ia32_psllw512_mask", IX86_BUILTIN_PSLLW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32967 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packsswb_mask, "__builtin_ia32_packsswb512_mask", IX86_BUILTIN_PACKSSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32968 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_packuswb_mask, "__builtin_ia32_packuswb512_mask", IX86_BUILTIN_PACKUSWB512, UNKNOWN, (int) V64QI_FTYPE_V32HI_V32HI_V64QI_DI },
32969 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashrvv32hi_mask, "__builtin_ia32_psrav32hi_mask", IX86_BUILTIN_PSRAVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32970 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddubsw512v32hi_mask, "__builtin_ia32_pmaddubsw512_mask", IX86_BUILTIN_PMADDUBSW512_MASK, UNKNOWN, (int) V32HI_FTYPE_V64QI_V64QI_V32HI_SI },
32971 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pmaddwd512v32hi_mask, "__builtin_ia32_pmaddwd512_mask", IX86_BUILTIN_PMADDWD512_MASK, UNKNOWN, (int) V16SI_FTYPE_V32HI_V32HI_V16SI_HI },
32972 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_lshrvv32hi_mask, "__builtin_ia32_psrlv32hi_mask", IX86_BUILTIN_PSRLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32973 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv64qi_mask, "__builtin_ia32_punpckhbw512_mask", IX86_BUILTIN_PUNPCKHBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32974 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_highv32hi_mask, "__builtin_ia32_punpckhwd512_mask", IX86_BUILTIN_PUNPCKHWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32975 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv64qi_mask, "__builtin_ia32_punpcklbw512_mask", IX86_BUILTIN_PUNPCKLBW512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32976 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_interleave_lowv32hi_mask, "__builtin_ia32_punpcklwd512_mask", IX86_BUILTIN_PUNPCKLWD512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32977 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufbv64qi3_mask, "__builtin_ia32_pshufb512_mask", IX86_BUILTIN_PSHUFB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
32978 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshufhwv32hi_mask, "__builtin_ia32_pshufhw512_mask", IX86_BUILTIN_PSHUFHW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32979 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_pshuflwv32hi_mask, "__builtin_ia32_pshuflw512_mask", IX86_BUILTIN_PSHUFLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32980 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psrawi512_mask", IX86_BUILTIN_PSRAWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32981 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_ashrv32hi3_mask, "__builtin_ia32_psraw512_mask", IX86_BUILTIN_PSRAW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32982 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlwi512_mask", IX86_BUILTIN_PSRLWI512, UNKNOWN, (int) V32HI_FTYPE_V32HI_INT_V32HI_SI },
32983 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_lshrv32hi3_mask, "__builtin_ia32_psrlw512_mask", IX86_BUILTIN_PSRLW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V8HI_V32HI_SI },
32984 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtb2maskv64qi, "__builtin_ia32_cvtb2mask512", IX86_BUILTIN_CVTB2MASK512, UNKNOWN, (int) DI_FTYPE_V64QI },
32985 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtw2maskv32hi, "__builtin_ia32_cvtw2mask512", IX86_BUILTIN_CVTW2MASK512, UNKNOWN, (int) SI_FTYPE_V32HI },
32986 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2bv64qi, "__builtin_ia32_cvtmask2b512", IX86_BUILTIN_CVTMASK2B512, UNKNOWN, (int) V64QI_FTYPE_DI },
32987 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cvtmask2wv32hi, "__builtin_ia32_cvtmask2w512", IX86_BUILTIN_CVTMASK2W512, UNKNOWN, (int) V32HI_FTYPE_SI },
32988 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv64qi3_mask, "__builtin_ia32_pcmpeqb512_mask", IX86_BUILTIN_PCMPEQB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32989 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_eqv32hi3_mask, "__builtin_ia32_pcmpeqw512_mask", IX86_BUILTIN_PCMPEQW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32990 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv64qi3_mask, "__builtin_ia32_pcmpgtb512_mask", IX86_BUILTIN_PCMPGTB512_MASK, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32991 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_gtv32hi3_mask, "__builtin_ia32_pcmpgtw512_mask", IX86_BUILTIN_PCMPGTW512_MASK, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32992 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv64qi3_mask, "__builtin_ia32_ptestmb512", IX86_BUILTIN_PTESTMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32993 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testmv32hi3_mask, "__builtin_ia32_ptestmw512", IX86_BUILTIN_PTESTMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32994 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv64qi3_mask, "__builtin_ia32_ptestnmb512", IX86_BUILTIN_PTESTNMB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_DI },
32995 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_testnmv32hi3_mask, "__builtin_ia32_ptestnmw512", IX86_BUILTIN_PTESTNMW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_SI },
32996 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ashlvv32hi_mask, "__builtin_ia32_psllv32hi_mask", IX86_BUILTIN_PSLLVV32HI, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_V32HI_SI },
32997 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv64qi2_mask, "__builtin_ia32_pabsb512_mask", IX86_BUILTIN_PABSB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
32998 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_absv32hi2_mask, "__builtin_ia32_pabsw512_mask", IX86_BUILTIN_PABSW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
32999 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv32hi, "__builtin_ia32_blendmw_512_mask", IX86_BUILTIN_BLENDMW512, UNKNOWN, (int) V32HI_FTYPE_V32HI_V32HI_SI },
33000 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_blendmv64qi, "__builtin_ia32_blendmb_512_mask", IX86_BUILTIN_BLENDMB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_DI },
33001 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv64qi3_mask, "__builtin_ia32_cmpb512_mask", IX86_BUILTIN_CMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
33002 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_cmpv32hi3_mask, "__builtin_ia32_cmpw512_mask", IX86_BUILTIN_CMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
33003 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv64qi3_mask, "__builtin_ia32_ucmpb512_mask", IX86_BUILTIN_UCMPB512, UNKNOWN, (int) DI_FTYPE_V64QI_V64QI_INT_DI },
33004 { OPTION_MASK_ISA_AVX512BW, CODE_FOR_avx512bw_ucmpv32hi3_mask, "__builtin_ia32_ucmpw512_mask", IX86_BUILTIN_UCMPW512, UNKNOWN, (int) SI_FTYPE_V32HI_V32HI_INT_SI },
33006 /* AVX512IFMA */
33007 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_mask, "__builtin_ia32_vpmadd52luq512_mask", IX86_BUILTIN_VPMADD52LUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33008 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52luqv8di_maskz, "__builtin_ia32_vpmadd52luq512_maskz", IX86_BUILTIN_VPMADD52LUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33009 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_mask, "__builtin_ia32_vpmadd52huq512_mask", IX86_BUILTIN_VPMADD52HUQ512, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33010 { OPTION_MASK_ISA_AVX512IFMA, CODE_FOR_vpamdd52huqv8di_maskz, "__builtin_ia32_vpmadd52huq512_maskz", IX86_BUILTIN_VPMADD52HUQ512_MASKZ, UNKNOWN, (int) V8DI_FTYPE_V8DI_V8DI_V8DI_QI },
33011 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_mask, "__builtin_ia32_vpmadd52luq256_mask", IX86_BUILTIN_VPMADD52LUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33012 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv4di_maskz, "__builtin_ia32_vpmadd52luq256_maskz", IX86_BUILTIN_VPMADD52LUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33013 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_mask, "__builtin_ia32_vpmadd52huq256_mask", IX86_BUILTIN_VPMADD52HUQ256, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33014 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv4di_maskz, "__builtin_ia32_vpmadd52huq256_maskz", IX86_BUILTIN_VPMADD52HUQ256_MASKZ, UNKNOWN, (int) V4DI_FTYPE_V4DI_V4DI_V4DI_QI },
33015 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_mask, "__builtin_ia32_vpmadd52luq128_mask", IX86_BUILTIN_VPMADD52LUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
33016 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52luqv2di_maskz, "__builtin_ia32_vpmadd52luq128_maskz", IX86_BUILTIN_VPMADD52LUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
33017 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_mask, "__builtin_ia32_vpmadd52huq128_mask", IX86_BUILTIN_VPMADD52HUQ128, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
33018 { OPTION_MASK_ISA_AVX512IFMA | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpamdd52huqv2di_maskz, "__builtin_ia32_vpmadd52huq128_maskz", IX86_BUILTIN_VPMADD52HUQ128_MASKZ, UNKNOWN, (int) V2DI_FTYPE_V2DI_V2DI_V2DI_QI },
33020 /* AVX512VBMI */
33021 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_vpmultishiftqbv64qi_mask, "__builtin_ia32_vpmultishiftqb512_mask", IX86_BUILTIN_VPMULTISHIFTQB512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33022 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv32qi_mask, "__builtin_ia32_vpmultishiftqb256_mask", IX86_BUILTIN_VPMULTISHIFTQB256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33023 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_vpmultishiftqbv16qi_mask, "__builtin_ia32_vpmultishiftqb128_mask", IX86_BUILTIN_VPMULTISHIFTQB128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33024 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_permvarv64qi_mask, "__builtin_ia32_permvarqi512_mask", IX86_BUILTIN_VPERMVARQI512_MASK, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33025 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_mask, "__builtin_ia32_vpermt2varqi512_mask", IX86_BUILTIN_VPERMT2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33026 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermt2varv64qi3_maskz, "__builtin_ia32_vpermt2varqi512_maskz", IX86_BUILTIN_VPERMT2VARQI512_MASKZ, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33027 { OPTION_MASK_ISA_AVX512VBMI, CODE_FOR_avx512bw_vpermi2varv64qi3_mask, "__builtin_ia32_vpermi2varqi512_mask", IX86_BUILTIN_VPERMI2VARQI512, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI_V64QI_DI },
33028 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv32qi_mask, "__builtin_ia32_permvarqi256_mask", IX86_BUILTIN_VPERMVARQI256_MASK, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33029 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_permvarv16qi_mask, "__builtin_ia32_permvarqi128_mask", IX86_BUILTIN_VPERMVARQI128_MASK, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33030 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_mask, "__builtin_ia32_vpermt2varqi256_mask", IX86_BUILTIN_VPERMT2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33031 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv32qi3_maskz, "__builtin_ia32_vpermt2varqi256_maskz", IX86_BUILTIN_VPERMT2VARQI256_MASKZ, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33032 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_mask, "__builtin_ia32_vpermt2varqi128_mask", IX86_BUILTIN_VPERMT2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33033 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermt2varv16qi3_maskz, "__builtin_ia32_vpermt2varqi128_maskz", IX86_BUILTIN_VPERMT2VARQI128_MASKZ, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33034 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv32qi3_mask, "__builtin_ia32_vpermi2varqi256_mask", IX86_BUILTIN_VPERMI2VARQI256, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI_V32QI_SI },
33035 { OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VL, CODE_FOR_avx512vl_vpermi2varv16qi3_mask, "__builtin_ia32_vpermi2varqi128_mask", IX86_BUILTIN_VPERMI2VARQI128, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI_V16QI_HI },
33036 };
33038 /* Builtins with rounding support. */
33040 {
33041 /* AVX512F */
33042 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv8df3_mask_round, "__builtin_ia32_addpd512_mask", IX86_BUILTIN_ADDPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33043 { OPTION_MASK_ISA_AVX512F, CODE_FOR_addv16sf3_mask_round, "__builtin_ia32_addps512_mask", IX86_BUILTIN_ADDPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33044 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmaddv2df3_round, "__builtin_ia32_addsd_round", IX86_BUILTIN_ADDSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33045 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmaddv4sf3_round, "__builtin_ia32_addss_round", IX86_BUILTIN_ADDSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33046 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv8df3_mask_round, "__builtin_ia32_cmppd512_mask", IX86_BUILTIN_CMPPD512, UNKNOWN, (int) QI_FTYPE_V8DF_V8DF_INT_QI_INT },
33047 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cmpv16sf3_mask_round, "__builtin_ia32_cmpps512_mask", IX86_BUILTIN_CMPPS512, UNKNOWN, (int) HI_FTYPE_V16SF_V16SF_INT_HI_INT },
33048 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv2df3_mask_round, "__builtin_ia32_cmpsd_mask", IX86_BUILTIN_CMPSD_MASK, UNKNOWN, (int) QI_FTYPE_V2DF_V2DF_INT_QI_INT },
33049 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmcmpv4sf3_mask_round, "__builtin_ia32_cmpss_mask", IX86_BUILTIN_CMPSS_MASK, UNKNOWN, (int) QI_FTYPE_V4SF_V4SF_INT_QI_INT },
33050 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_comi_round, "__builtin_ia32_vcomisd", IX86_BUILTIN_COMIDF, UNKNOWN, (int) INT_FTYPE_V2DF_V2DF_INT_INT },
33051 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_comi_round, "__builtin_ia32_vcomiss", IX86_BUILTIN_COMISF, UNKNOWN, (int) INT_FTYPE_V4SF_V4SF_INT_INT },
33052 { OPTION_MASK_ISA_AVX512F, CODE_FOR_floatv16siv16sf2_mask_round, "__builtin_ia32_cvtdq2ps512_mask", IX86_BUILTIN_CVTDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
33053 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2dq512_mask_round, "__builtin_ia32_cvtpd2dq512_mask", IX86_BUILTIN_CVTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33054 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtpd2ps512_mask_round, "__builtin_ia32_cvtpd2ps512_mask", IX86_BUILTIN_CVTPD2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DF_V8SF_QI_INT },
33055 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_notruncv8dfv8si2_mask_round, "__builtin_ia32_cvtpd2udq512_mask", IX86_BUILTIN_CVTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33056 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtph2ps512_mask_round, "__builtin_ia32_vcvtph2ps512_mask", IX86_BUILTIN_CVTPH2PS512, UNKNOWN, (int) V16SF_FTYPE_V16HI_V16SF_HI_INT },
33057 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2dq512_mask", IX86_BUILTIN_CVTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33058 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_cvtps2pd512_mask_round, "__builtin_ia32_cvtps2pd512_mask", IX86_BUILTIN_CVTPS2PD512, UNKNOWN, (int) V8DF_FTYPE_V8SF_V8DF_QI_INT },
33059 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_ufix_notruncv16sfv16si_mask_round, "__builtin_ia32_cvtps2udq512_mask", IX86_BUILTIN_CVTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33060 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2ss_round, "__builtin_ia32_cvtsd2ss_round", IX86_BUILTIN_CVTSD2SS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V2DF_INT },
33061 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsi2sdq_round, "__builtin_ia32_cvtsi2sd64", IX86_BUILTIN_CVTSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT64_INT },
33062 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtsi2ss_round, "__builtin_ia32_cvtsi2ss32", IX86_BUILTIN_CVTSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT_INT },
33063 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtsi2ssq_round, "__builtin_ia32_cvtsi2ss64", IX86_BUILTIN_CVTSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT64_INT },
33064 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtss2sd_round, "__builtin_ia32_cvtss2sd_round", IX86_BUILTIN_CVTSS2SD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V4SF_INT },
33065 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2dq512_mask", IX86_BUILTIN_CVTTPD2DQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33066 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv8dfv8si2_mask_round, "__builtin_ia32_cvttpd2udq512_mask", IX86_BUILTIN_CVTTPD2UDQ512, UNKNOWN, (int) V8SI_FTYPE_V8DF_V8SI_QI_INT },
33067 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2dq512_mask", IX86_BUILTIN_CVTTPS2DQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33068 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufix_truncv16sfv16si2_mask_round, "__builtin_ia32_cvttps2udq512_mask", IX86_BUILTIN_CVTTPS2UDQ512, UNKNOWN, (int) V16SI_FTYPE_V16SF_V16SI_HI_INT },
33069 { OPTION_MASK_ISA_AVX512F, CODE_FOR_ufloatv16siv16sf2_mask_round, "__builtin_ia32_cvtudq2ps512_mask", IX86_BUILTIN_CVTUDQ2PS512, UNKNOWN, (int) V16SF_FTYPE_V16SI_V16SF_HI_INT },
33070 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2sd64_round, "__builtin_ia32_cvtusi2sd64", IX86_BUILTIN_CVTUSI2SD64, UNKNOWN, (int) V2DF_FTYPE_V2DF_UINT64_INT },
33071 { OPTION_MASK_ISA_AVX512F, CODE_FOR_cvtusi2ss32_round, "__builtin_ia32_cvtusi2ss32", IX86_BUILTIN_CVTUSI2SS32, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT_INT },
33072 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_cvtusi2ss64_round, "__builtin_ia32_cvtusi2ss64", IX86_BUILTIN_CVTUSI2SS64, UNKNOWN, (int) V4SF_FTYPE_V4SF_UINT64_INT },
33073 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv8df3_mask_round, "__builtin_ia32_divpd512_mask", IX86_BUILTIN_DIVPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33074 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_divv16sf3_mask_round, "__builtin_ia32_divps512_mask", IX86_BUILTIN_DIVPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33075 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmdivv2df3_round, "__builtin_ia32_divsd_round", IX86_BUILTIN_DIVSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33076 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmdivv4sf3_round, "__builtin_ia32_divss_round", IX86_BUILTIN_DIVSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33077 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_mask_round, "__builtin_ia32_fixupimmpd512_mask", IX86_BUILTIN_FIXUPIMMPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
33078 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv8df_maskz_round, "__builtin_ia32_fixupimmpd512_maskz", IX86_BUILTIN_FIXUPIMMPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DI_INT_QI_INT },
33079 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_mask_round, "__builtin_ia32_fixupimmps512_mask", IX86_BUILTIN_FIXUPIMMPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
33080 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fixupimmv16sf_maskz_round, "__builtin_ia32_fixupimmps512_maskz", IX86_BUILTIN_FIXUPIMMPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SI_INT_HI_INT },
33081 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_mask_round, "__builtin_ia32_fixupimmsd_mask", IX86_BUILTIN_FIXUPIMMSD128_MASK, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
33082 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv2df_maskz_round, "__builtin_ia32_fixupimmsd_maskz", IX86_BUILTIN_FIXUPIMMSD128_MASKZ, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DI_INT_QI_INT },
33083 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_mask_round, "__builtin_ia32_fixupimmss_mask", IX86_BUILTIN_FIXUPIMMSS128_MASK, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
33084 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sfixupimmv4sf_maskz_round, "__builtin_ia32_fixupimmss_maskz", IX86_BUILTIN_FIXUPIMMSS128_MASKZ, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SI_INT_QI_INT },
33085 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv8df_mask_round, "__builtin_ia32_getexppd512_mask", IX86_BUILTIN_GETEXPPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33086 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getexpv16sf_mask_round, "__builtin_ia32_getexpps512_mask", IX86_BUILTIN_GETEXPPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33087 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv2df_round, "__builtin_ia32_getexpsd128_round", IX86_BUILTIN_GETEXPSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33088 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33089 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
33090 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
33091 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33092 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33093 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33094 { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33095 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33096 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsmaxv4sf3_round, "__builtin_ia32_maxss_round", IX86_BUILTIN_MAXSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33097 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv8df3_mask_round, "__builtin_ia32_minpd512_mask", IX86_BUILTIN_MINPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33098 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sminv16sf3_mask_round, "__builtin_ia32_minps512_mask", IX86_BUILTIN_MINPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33099 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsminv2df3_round, "__builtin_ia32_minsd_round", IX86_BUILTIN_MINSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33100 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsminv4sf3_round, "__builtin_ia32_minss_round", IX86_BUILTIN_MINSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33101 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv8df3_mask_round, "__builtin_ia32_mulpd512_mask", IX86_BUILTIN_MULPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33102 { OPTION_MASK_ISA_AVX512F, CODE_FOR_mulv16sf3_mask_round, "__builtin_ia32_mulps512_mask", IX86_BUILTIN_MULPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33103 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmmulv2df3_round, "__builtin_ia32_mulsd_round", IX86_BUILTIN_MULSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33104 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmmulv4sf3_round, "__builtin_ia32_mulss_round", IX86_BUILTIN_MULSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33105 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev8df_mask_round, "__builtin_ia32_rndscalepd_mask", IX86_BUILTIN_RNDSCALEPD, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT },
33106 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev16sf_mask_round, "__builtin_ia32_rndscaleps_mask", IX86_BUILTIN_RNDSCALEPS, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT },
33107 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev2df_round, "__builtin_ia32_rndscalesd_round", IX86_BUILTIN_RNDSCALESD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33108 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_rndscalev4sf_round, "__builtin_ia32_rndscaless_round", IX86_BUILTIN_RNDSCALESS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33109 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv8df_mask_round, "__builtin_ia32_scalefpd512_mask", IX86_BUILTIN_SCALEFPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33110 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_scalefv16sf_mask_round, "__builtin_ia32_scalefps512_mask", IX86_BUILTIN_SCALEFPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33111 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv2df_round, "__builtin_ia32_scalefsd_round", IX86_BUILTIN_SCALEFSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33112 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vmscalefv4sf_round, "__builtin_ia32_scalefss_round", IX86_BUILTIN_SCALEFSS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33113 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv8df2_mask_round, "__builtin_ia32_sqrtpd512_mask", IX86_BUILTIN_SQRTPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33114 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sqrtv16sf2_mask_round, "__builtin_ia32_sqrtps512_mask", IX86_BUILTIN_SQRTPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33115 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsqrtv2df2_round, "__builtin_ia32_sqrtsd_round", IX86_BUILTIN_SQRTSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33116 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsqrtv4sf2_round, "__builtin_ia32_sqrtss_round", IX86_BUILTIN_SQRTSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33117 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv8df3_mask_round, "__builtin_ia32_subpd512_mask", IX86_BUILTIN_SUBPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33118 { OPTION_MASK_ISA_AVX512F, CODE_FOR_subv16sf3_mask_round, "__builtin_ia32_subps512_mask", IX86_BUILTIN_SUBPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33119 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsubv2df3_round, "__builtin_ia32_subsd_round", IX86_BUILTIN_SUBSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33120 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_vmsubv4sf3_round, "__builtin_ia32_subss_round", IX86_BUILTIN_SUBSS_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33121 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvtsd2si_round, "__builtin_ia32_vcvtsd2si32", IX86_BUILTIN_VCVTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
33122 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvtsd2siq_round, "__builtin_ia32_vcvtsd2si64", IX86_BUILTIN_VCVTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
33123 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtsd2usi_round, "__builtin_ia32_vcvtsd2usi32", IX86_BUILTIN_VCVTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
33124 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtsd2usiq_round, "__builtin_ia32_vcvtsd2usi64", IX86_BUILTIN_VCVTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
33125 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvtss2si_round, "__builtin_ia32_vcvtss2si32", IX86_BUILTIN_VCVTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
33126 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvtss2siq_round, "__builtin_ia32_vcvtss2si64", IX86_BUILTIN_VCVTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
33127 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvtss2usi_round, "__builtin_ia32_vcvtss2usi32", IX86_BUILTIN_VCVTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
33128 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvtss2usiq_round, "__builtin_ia32_vcvtss2usi64", IX86_BUILTIN_VCVTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
33129 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_cvttsd2si_round, "__builtin_ia32_vcvttsd2si32", IX86_BUILTIN_VCVTTSD2SI32, UNKNOWN, (int) INT_FTYPE_V2DF_INT },
33130 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse2_cvttsd2siq_round, "__builtin_ia32_vcvttsd2si64", IX86_BUILTIN_VCVTTSD2SI64, UNKNOWN, (int) INT64_FTYPE_V2DF_INT },
33131 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttsd2usi_round, "__builtin_ia32_vcvttsd2usi32", IX86_BUILTIN_VCVTTSD2USI32, UNKNOWN, (int) UINT_FTYPE_V2DF_INT },
33132 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttsd2usiq_round, "__builtin_ia32_vcvttsd2usi64", IX86_BUILTIN_VCVTTSD2USI64, UNKNOWN, (int) UINT64_FTYPE_V2DF_INT },
33133 { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse_cvttss2si_round, "__builtin_ia32_vcvttss2si32", IX86_BUILTIN_VCVTTSS2SI32, UNKNOWN, (int) INT_FTYPE_V4SF_INT },
33134 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_sse_cvttss2siq_round, "__builtin_ia32_vcvttss2si64", IX86_BUILTIN_VCVTTSS2SI64, UNKNOWN, (int) INT64_FTYPE_V4SF_INT },
33135 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vcvttss2usi_round, "__builtin_ia32_vcvttss2usi32", IX86_BUILTIN_VCVTTSS2USI32, UNKNOWN, (int) UINT_FTYPE_V4SF_INT },
33136 { OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_64BIT, CODE_FOR_avx512f_vcvttss2usiq_round, "__builtin_ia32_vcvttss2usi64", IX86_BUILTIN_VCVTTSS2USI64, UNKNOWN, (int) UINT64_FTYPE_V4SF_INT },
33137 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask_round, "__builtin_ia32_vfmaddpd512_mask", IX86_BUILTIN_VFMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33138 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_mask3_round, "__builtin_ia32_vfmaddpd512_mask3", IX86_BUILTIN_VFMADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33139 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v8df_maskz_round, "__builtin_ia32_vfmaddpd512_maskz", IX86_BUILTIN_VFMADDPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33140 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask_round, "__builtin_ia32_vfmaddps512_mask", IX86_BUILTIN_VFMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33141 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_mask3_round, "__builtin_ia32_vfmaddps512_mask3", IX86_BUILTIN_VFMADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33142 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmadd_v16sf_maskz_round, "__builtin_ia32_vfmaddps512_maskz", IX86_BUILTIN_VFMADDPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33143 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v2df_round, "__builtin_ia32_vfmaddsd3_round", IX86_BUILTIN_VFMADDSD3_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_V2DF_INT },
33144 { OPTION_MASK_ISA_AVX512F, CODE_FOR_fmai_vmfmadd_v4sf_round, "__builtin_ia32_vfmaddss3_round", IX86_BUILTIN_VFMADDSS3_ROUND, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_V4SF_INT },
33145 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask_round, "__builtin_ia32_vfmaddsubpd512_mask", IX86_BUILTIN_VFMADDSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33146 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_mask3_round, "__builtin_ia32_vfmaddsubpd512_mask3", IX86_BUILTIN_VFMADDSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33147 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v8df_maskz_round, "__builtin_ia32_vfmaddsubpd512_maskz", IX86_BUILTIN_VFMADDSUBPD512_MASKZ, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33148 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask_round, "__builtin_ia32_vfmaddsubps512_mask", IX86_BUILTIN_VFMADDSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33149 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_mask3_round, "__builtin_ia32_vfmaddsubps512_mask3", IX86_BUILTIN_VFMADDSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33150 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmaddsub_v16sf_maskz_round, "__builtin_ia32_vfmaddsubps512_maskz", IX86_BUILTIN_VFMADDSUBPS512_MASKZ, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33151 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v8df_mask3_round, "__builtin_ia32_vfmsubaddpd512_mask3", IX86_BUILTIN_VFMSUBADDPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33152 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsubadd_v16sf_mask3_round, "__builtin_ia32_vfmsubaddps512_mask3", IX86_BUILTIN_VFMSUBADDPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33153 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v8df_mask3_round, "__builtin_ia32_vfmsubpd512_mask3", IX86_BUILTIN_VFMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33154 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fmsub_v16sf_mask3_round, "__builtin_ia32_vfmsubps512_mask3", IX86_BUILTIN_VFMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33155 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v8df_mask_round, "__builtin_ia32_vfnmaddpd512_mask", IX86_BUILTIN_VFNMADDPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33156 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmadd_v16sf_mask_round, "__builtin_ia32_vfnmaddps512_mask", IX86_BUILTIN_VFNMADDPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33157 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask_round, "__builtin_ia32_vfnmsubpd512_mask", IX86_BUILTIN_VFNMSUBPD512_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33158 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v8df_mask3_round, "__builtin_ia32_vfnmsubpd512_mask3", IX86_BUILTIN_VFNMSUBPD512_MASK3, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT },
33159 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask_round, "__builtin_ia32_vfnmsubps512_mask", IX86_BUILTIN_VFNMSUBPS512_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33160 { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_fnmsub_v16sf_mask3_round, "__builtin_ia32_vfnmsubps512_mask3", IX86_BUILTIN_VFNMSUBPS512_MASK3, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT },
33162 /* AVX512ER */
33163 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v8df_mask_round, "__builtin_ia32_exp2pd_mask", IX86_BUILTIN_EXP2PD_MASK, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33164 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_exp2v16sf_mask_round, "__builtin_ia32_exp2ps_mask", IX86_BUILTIN_EXP2PS_MASK, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33165 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v8df_mask_round, "__builtin_ia32_rcp28pd_mask", IX86_BUILTIN_RCP28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33166 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rcp28v16sf_mask_round, "__builtin_ia32_rcp28ps_mask", IX86_BUILTIN_RCP28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33167 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v2df_round, "__builtin_ia32_rcp28sd_round", IX86_BUILTIN_RCP28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33168 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrcp28v4sf_round, "__builtin_ia32_rcp28ss_round", IX86_BUILTIN_RCP28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33169 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v8df_mask_round, "__builtin_ia32_rsqrt28pd_mask", IX86_BUILTIN_RSQRT28PD, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_QI_INT },
33170 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_rsqrt28v16sf_mask_round, "__builtin_ia32_rsqrt28ps_mask", IX86_BUILTIN_RSQRT28PS, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_HI_INT },
33171 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v2df_round, "__builtin_ia32_rsqrt28sd_round", IX86_BUILTIN_RSQRT28SD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
33172 { OPTION_MASK_ISA_AVX512ER, CODE_FOR_avx512er_vmrsqrt28v4sf_round, "__builtin_ia32_rsqrt28ss_round", IX86_BUILTIN_RSQRT28SS, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT },
33174 /* AVX512DQ. */
33175 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv2df_round, "__builtin_ia32_rangesd128_round", IX86_BUILTIN_RANGESD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT },
33176 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangesv4sf_round, "__builtin_ia32_rangess128_round", IX86_BUILTIN_RANGESS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT },
33177 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2qq512_mask", IX86_BUILTIN_CVTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33178 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2qqv8di_mask_round, "__builtin_ia32_cvtps2qq512_mask", IX86_BUILTIN_CVTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33179 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_notruncv8dfv8di2_mask_round, "__builtin_ia32_cvtpd2uqq512_mask", IX86_BUILTIN_CVTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33180 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_cvtps2uqqv8di_mask_round, "__builtin_ia32_cvtps2uqq512_mask", IX86_BUILTIN_CVTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33181 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8sf2_mask_round, "__builtin_ia32_cvtqq2ps512_mask", IX86_BUILTIN_CVTQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33182 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8sf2_mask_round, "__builtin_ia32_cvtuqq2ps512_mask", IX86_BUILTIN_CVTUQQ2PS512, UNKNOWN, (int) V8SF_FTYPE_V8DI_V8SF_QI_INT },
33183 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_floatv8div8df2_mask_round, "__builtin_ia32_cvtqq2pd512_mask", IX86_BUILTIN_CVTQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33184 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufloatv8div8df2_mask_round, "__builtin_ia32_cvtuqq2pd512_mask", IX86_BUILTIN_CVTUQQ2PD512, UNKNOWN, (int) V8DF_FTYPE_V8DI_V8DF_QI_INT },
33185 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2qq512_mask", IX86_BUILTIN_CVTTPS2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33186 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8sfv8di2_mask_round, "__builtin_ia32_cvttps2uqq512_mask", IX86_BUILTIN_CVTTPS2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8SF_V8DI_QI_INT },
33187 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_fix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2qq512_mask", IX86_BUILTIN_CVTTPD2QQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33188 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_ufix_truncv8dfv8di2_mask_round, "__builtin_ia32_cvttpd2uqq512_mask", IX86_BUILTIN_CVTTPD2UQQ512, UNKNOWN, (int) V8DI_FTYPE_V8DF_V8DI_QI_INT },
33189 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv16sf_mask_round, "__builtin_ia32_rangeps512_mask", IX86_BUILTIN_RANGEPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_INT_V16SF_HI_INT },
33190 { OPTION_MASK_ISA_AVX512DQ, CODE_FOR_avx512dq_rangepv8df_mask_round, "__builtin_ia32_rangepd512_mask", IX86_BUILTIN_RANGEPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_INT_V8DF_QI_INT },
33191 };
33193 /* Bultins for MPX. */
33195 {
33196 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndstx", IX86_BUILTIN_BNDSTX, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND_PCVOID },
33197 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcl", IX86_BUILTIN_BNDCL, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33198 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndcu", IX86_BUILTIN_BNDCU, UNKNOWN, (int) VOID_FTYPE_PCVOID_BND },
33199 };
33201 /* Const builtins for MPX. */
33203 {
33204 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndmk", IX86_BUILTIN_BNDMK, UNKNOWN, (int) BND_FTYPE_PCVOID_ULONG },
33205 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndldx", IX86_BUILTIN_BNDLDX, UNKNOWN, (int) BND_FTYPE_PCVOID_PCVOID },
33206 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_narrow_bounds", IX86_BUILTIN_BNDNARROW, UNKNOWN, (int) PVOID_FTYPE_PCVOID_BND_ULONG },
33207 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndint", IX86_BUILTIN_BNDINT, UNKNOWN, (int) BND_FTYPE_BND_BND },
33208 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_sizeof", IX86_BUILTIN_SIZEOF, UNKNOWN, (int) ULONG_FTYPE_VOID },
33209 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndlower", IX86_BUILTIN_BNDLOWER, UNKNOWN, (int) PVOID_FTYPE_BND },
33210 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndupper", IX86_BUILTIN_BNDUPPER, UNKNOWN, (int) PVOID_FTYPE_BND },
33211 { OPTION_MASK_ISA_MPX, (enum insn_code)0, "__builtin_ia32_bndret", IX86_BUILTIN_BNDRET, UNKNOWN, (int) BND_FTYPE_PCVOID },
33212 };
33214 /* FMA4 and XOP. */
33215 #define MULTI_ARG_4_DF2_DI_I V2DF_FTYPE_V2DF_V2DF_V2DI_INT
33216 #define MULTI_ARG_4_DF2_DI_I1 V4DF_FTYPE_V4DF_V4DF_V4DI_INT
33217 #define MULTI_ARG_4_SF2_SI_I V4SF_FTYPE_V4SF_V4SF_V4SI_INT
33218 #define MULTI_ARG_4_SF2_SI_I1 V8SF_FTYPE_V8SF_V8SF_V8SI_INT
33219 #define MULTI_ARG_3_SF V4SF_FTYPE_V4SF_V4SF_V4SF
33220 #define MULTI_ARG_3_DF V2DF_FTYPE_V2DF_V2DF_V2DF
33221 #define MULTI_ARG_3_SF2 V8SF_FTYPE_V8SF_V8SF_V8SF
33222 #define MULTI_ARG_3_DF2 V4DF_FTYPE_V4DF_V4DF_V4DF
33223 #define MULTI_ARG_3_DI V2DI_FTYPE_V2DI_V2DI_V2DI
33224 #define MULTI_ARG_3_SI V4SI_FTYPE_V4SI_V4SI_V4SI
33225 #define MULTI_ARG_3_SI_DI V4SI_FTYPE_V4SI_V4SI_V2DI
33226 #define MULTI_ARG_3_HI V8HI_FTYPE_V8HI_V8HI_V8HI
33227 #define MULTI_ARG_3_HI_SI V8HI_FTYPE_V8HI_V8HI_V4SI
33228 #define MULTI_ARG_3_QI V16QI_FTYPE_V16QI_V16QI_V16QI
33229 #define MULTI_ARG_3_DI2 V4DI_FTYPE_V4DI_V4DI_V4DI
33230 #define MULTI_ARG_3_SI2 V8SI_FTYPE_V8SI_V8SI_V8SI
33231 #define MULTI_ARG_3_HI2 V16HI_FTYPE_V16HI_V16HI_V16HI
33232 #define MULTI_ARG_3_QI2 V32QI_FTYPE_V32QI_V32QI_V32QI
33233 #define MULTI_ARG_2_SF V4SF_FTYPE_V4SF_V4SF
33234 #define MULTI_ARG_2_DF V2DF_FTYPE_V2DF_V2DF
33235 #define MULTI_ARG_2_DI V2DI_FTYPE_V2DI_V2DI
33236 #define MULTI_ARG_2_SI V4SI_FTYPE_V4SI_V4SI
33237 #define MULTI_ARG_2_HI V8HI_FTYPE_V8HI_V8HI
33238 #define MULTI_ARG_2_QI V16QI_FTYPE_V16QI_V16QI
33239 #define MULTI_ARG_2_DI_IMM V2DI_FTYPE_V2DI_SI
33240 #define MULTI_ARG_2_SI_IMM V4SI_FTYPE_V4SI_SI
33241 #define MULTI_ARG_2_HI_IMM V8HI_FTYPE_V8HI_SI
33242 #define MULTI_ARG_2_QI_IMM V16QI_FTYPE_V16QI_SI
33243 #define MULTI_ARG_2_DI_CMP V2DI_FTYPE_V2DI_V2DI_CMP
33244 #define MULTI_ARG_2_SI_CMP V4SI_FTYPE_V4SI_V4SI_CMP
33245 #define MULTI_ARG_2_HI_CMP V8HI_FTYPE_V8HI_V8HI_CMP
33246 #define MULTI_ARG_2_QI_CMP V16QI_FTYPE_V16QI_V16QI_CMP
33247 #define MULTI_ARG_2_SF_TF V4SF_FTYPE_V4SF_V4SF_TF
33248 #define MULTI_ARG_2_DF_TF V2DF_FTYPE_V2DF_V2DF_TF
33249 #define MULTI_ARG_2_DI_TF V2DI_FTYPE_V2DI_V2DI_TF
33250 #define MULTI_ARG_2_SI_TF V4SI_FTYPE_V4SI_V4SI_TF
33251 #define MULTI_ARG_2_HI_TF V8HI_FTYPE_V8HI_V8HI_TF
33252 #define MULTI_ARG_2_QI_TF V16QI_FTYPE_V16QI_V16QI_TF
33253 #define MULTI_ARG_1_SF V4SF_FTYPE_V4SF
33254 #define MULTI_ARG_1_DF V2DF_FTYPE_V2DF
33255 #define MULTI_ARG_1_SF2 V8SF_FTYPE_V8SF
33256 #define MULTI_ARG_1_DF2 V4DF_FTYPE_V4DF
33257 #define MULTI_ARG_1_DI V2DI_FTYPE_V2DI
33258 #define MULTI_ARG_1_SI V4SI_FTYPE_V4SI
33259 #define MULTI_ARG_1_HI V8HI_FTYPE_V8HI
33260 #define MULTI_ARG_1_QI V16QI_FTYPE_V16QI
33261 #define MULTI_ARG_1_SI_DI V2DI_FTYPE_V4SI
33262 #define MULTI_ARG_1_HI_DI V2DI_FTYPE_V8HI
33263 #define MULTI_ARG_1_HI_SI V4SI_FTYPE_V8HI
33264 #define MULTI_ARG_1_QI_DI V2DI_FTYPE_V16QI
33265 #define MULTI_ARG_1_QI_SI V4SI_FTYPE_V16QI
33266 #define MULTI_ARG_1_QI_HI V8HI_FTYPE_V16QI
33269 {
33310 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov", IX86_BUILTIN_VPCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
33311 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2di, "__builtin_ia32_vpcmov_v2di", IX86_BUILTIN_VPCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
33312 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4si, "__builtin_ia32_vpcmov_v4si", IX86_BUILTIN_VPCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
33313 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8hi, "__builtin_ia32_vpcmov_v8hi", IX86_BUILTIN_VPCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
33314 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16qi, "__builtin_ia32_vpcmov_v16qi",IX86_BUILTIN_VPCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
33315 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v2df, "__builtin_ia32_vpcmov_v2df", IX86_BUILTIN_VPCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
33316 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4sf, "__builtin_ia32_vpcmov_v4sf", IX86_BUILTIN_VPCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
33318 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov256", IX86_BUILTIN_VPCMOV256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33319 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4di256, "__builtin_ia32_vpcmov_v4di256", IX86_BUILTIN_VPCMOV_V4DI256, UNKNOWN, (int)MULTI_ARG_3_DI2 },
33320 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8si256, "__builtin_ia32_vpcmov_v8si256", IX86_BUILTIN_VPCMOV_V8SI256, UNKNOWN, (int)MULTI_ARG_3_SI2 },
33321 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v16hi256, "__builtin_ia32_vpcmov_v16hi256", IX86_BUILTIN_VPCMOV_V16HI256, UNKNOWN, (int)MULTI_ARG_3_HI2 },
33322 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v32qi256, "__builtin_ia32_vpcmov_v32qi256", IX86_BUILTIN_VPCMOV_V32QI256, UNKNOWN, (int)MULTI_ARG_3_QI2 },
33323 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v4df256, "__builtin_ia32_vpcmov_v4df256", IX86_BUILTIN_VPCMOV_V4DF256, UNKNOWN, (int)MULTI_ARG_3_DF2 },
33324 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcmov_v8sf256, "__builtin_ia32_vpcmov_v8sf256", IX86_BUILTIN_VPCMOV_V8SF256, UNKNOWN, (int)MULTI_ARG_3_SF2 },
33326 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pperm, "__builtin_ia32_vpperm", IX86_BUILTIN_VPPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
33328 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssww, "__builtin_ia32_vpmacssww", IX86_BUILTIN_VPMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33329 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsww, "__builtin_ia32_vpmacsww", IX86_BUILTIN_VPMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
33330 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsswd, "__builtin_ia32_vpmacsswd", IX86_BUILTIN_VPMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33331 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacswd, "__builtin_ia32_vpmacswd", IX86_BUILTIN_VPMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33332 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdd, "__builtin_ia32_vpmacssdd", IX86_BUILTIN_VPMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33333 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdd, "__builtin_ia32_vpmacsdd", IX86_BUILTIN_VPMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
33334 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdql, "__builtin_ia32_vpmacssdql", IX86_BUILTIN_VPMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33335 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacssdqh, "__builtin_ia32_vpmacssdqh", IX86_BUILTIN_VPMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33336 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdql, "__builtin_ia32_vpmacsdql", IX86_BUILTIN_VPMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33337 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmacsdqh, "__builtin_ia32_vpmacsdqh", IX86_BUILTIN_VPMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
33338 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcsswd, "__builtin_ia32_vpmadcsswd", IX86_BUILTIN_VPMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33339 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pmadcswd, "__builtin_ia32_vpmadcswd", IX86_BUILTIN_VPMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
33341 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv2di3, "__builtin_ia32_vprotq", IX86_BUILTIN_VPROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33342 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv4si3, "__builtin_ia32_vprotd", IX86_BUILTIN_VPROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
33343 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv8hi3, "__builtin_ia32_vprotw", IX86_BUILTIN_VPROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
33344 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vrotlv16qi3, "__builtin_ia32_vprotb", IX86_BUILTIN_VPROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
33345 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv2di3, "__builtin_ia32_vprotqi", IX86_BUILTIN_VPROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
33346 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv4si3, "__builtin_ia32_vprotdi", IX86_BUILTIN_VPROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
33347 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv8hi3, "__builtin_ia32_vprotwi", IX86_BUILTIN_VPROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
33348 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_rotlv16qi3, "__builtin_ia32_vprotbi", IX86_BUILTIN_VPROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
33349 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav2di3, "__builtin_ia32_vpshaq", IX86_BUILTIN_VPSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33350 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav4si3, "__builtin_ia32_vpshad", IX86_BUILTIN_VPSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
33351 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav8hi3, "__builtin_ia32_vpshaw", IX86_BUILTIN_VPSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
33352 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shav16qi3, "__builtin_ia32_vpshab", IX86_BUILTIN_VPSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
33353 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv2di3, "__builtin_ia32_vpshlq", IX86_BUILTIN_VPSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
33354 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv4si3, "__builtin_ia32_vpshld", IX86_BUILTIN_VPSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
33355 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv8hi3, "__builtin_ia32_vpshlw", IX86_BUILTIN_VPSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
33356 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_shlv16qi3, "__builtin_ia32_vpshlb", IX86_BUILTIN_VPSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
33358 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv4sf2, "__builtin_ia32_vfrczss", IX86_BUILTIN_VFRCZSS, UNKNOWN, (int)MULTI_ARG_1_SF },
33359 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vmfrczv2df2, "__builtin_ia32_vfrczsd", IX86_BUILTIN_VFRCZSD, UNKNOWN, (int)MULTI_ARG_1_DF },
33360 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4sf2, "__builtin_ia32_vfrczps", IX86_BUILTIN_VFRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
33361 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv2df2, "__builtin_ia32_vfrczpd", IX86_BUILTIN_VFRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
33362 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv8sf2, "__builtin_ia32_vfrczps256", IX86_BUILTIN_VFRCZPS256, UNKNOWN, (int)MULTI_ARG_1_SF2 },
33363 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_frczv4df2, "__builtin_ia32_vfrczpd256", IX86_BUILTIN_VFRCZPD256, UNKNOWN, (int)MULTI_ARG_1_DF2 },
33365 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbw, "__builtin_ia32_vphaddbw", IX86_BUILTIN_VPHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33366 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbd, "__builtin_ia32_vphaddbd", IX86_BUILTIN_VPHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33367 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddbq, "__builtin_ia32_vphaddbq", IX86_BUILTIN_VPHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33368 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwd, "__builtin_ia32_vphaddwd", IX86_BUILTIN_VPHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33369 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddwq, "__builtin_ia32_vphaddwq", IX86_BUILTIN_VPHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33370 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadddq, "__builtin_ia32_vphadddq", IX86_BUILTIN_VPHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33371 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubw, "__builtin_ia32_vphaddubw", IX86_BUILTIN_VPHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33372 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubd, "__builtin_ia32_vphaddubd", IX86_BUILTIN_VPHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
33373 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddubq, "__builtin_ia32_vphaddubq", IX86_BUILTIN_VPHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
33374 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwd, "__builtin_ia32_vphadduwd", IX86_BUILTIN_VPHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33375 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phadduwq, "__builtin_ia32_vphadduwq", IX86_BUILTIN_VPHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
33376 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phaddudq, "__builtin_ia32_vphaddudq", IX86_BUILTIN_VPHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33377 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubbw, "__builtin_ia32_vphsubbw", IX86_BUILTIN_VPHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
33378 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubwd, "__builtin_ia32_vphsubwd", IX86_BUILTIN_VPHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
33379 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_phsubdq, "__builtin_ia32_vphsubdq", IX86_BUILTIN_VPHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
33381 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomeqb", IX86_BUILTIN_VPCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
33382 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33383 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomneqb", IX86_BUILTIN_VPCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
33384 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomltb", IX86_BUILTIN_VPCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
33385 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomleb", IX86_BUILTIN_VPCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
33386 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgtb", IX86_BUILTIN_VPCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
33387 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv16qi3, "__builtin_ia32_vpcomgeb", IX86_BUILTIN_VPCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
33389 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomeqw", IX86_BUILTIN_VPCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
33390 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomnew", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33391 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomneqw", IX86_BUILTIN_VPCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
33392 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomltw", IX86_BUILTIN_VPCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
33393 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomlew", IX86_BUILTIN_VPCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
33394 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgtw", IX86_BUILTIN_VPCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
33395 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv8hi3, "__builtin_ia32_vpcomgew", IX86_BUILTIN_VPCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
33397 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomeqd", IX86_BUILTIN_VPCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
33398 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomned", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33399 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomneqd", IX86_BUILTIN_VPCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
33400 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomltd", IX86_BUILTIN_VPCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
33401 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomled", IX86_BUILTIN_VPCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
33402 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomgtd", IX86_BUILTIN_VPCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
33403 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv4si3, "__builtin_ia32_vpcomged", IX86_BUILTIN_VPCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
33405 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomeqq", IX86_BUILTIN_VPCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33406 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33407 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomneqq", IX86_BUILTIN_VPCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
33408 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomltq", IX86_BUILTIN_VPCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
33409 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomleq", IX86_BUILTIN_VPCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
33410 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgtq", IX86_BUILTIN_VPCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
33411 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmpv2di3, "__builtin_ia32_vpcomgeq", IX86_BUILTIN_VPCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
33413 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomequb", IX86_BUILTIN_VPCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
33414 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomneub", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33415 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v16qi3,"__builtin_ia32_vpcomnequb", IX86_BUILTIN_VPCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
33416 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomltub", IX86_BUILTIN_VPCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
33417 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomleub", IX86_BUILTIN_VPCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
33418 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgtub", IX86_BUILTIN_VPCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
33419 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv16qi3, "__builtin_ia32_vpcomgeub", IX86_BUILTIN_VPCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
33421 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomequw", IX86_BUILTIN_VPCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
33422 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomneuw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33423 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v8hi3, "__builtin_ia32_vpcomnequw", IX86_BUILTIN_VPCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
33424 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomltuw", IX86_BUILTIN_VPCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
33425 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomleuw", IX86_BUILTIN_VPCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
33426 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgtuw", IX86_BUILTIN_VPCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
33427 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv8hi3, "__builtin_ia32_vpcomgeuw", IX86_BUILTIN_VPCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
33429 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomequd", IX86_BUILTIN_VPCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
33430 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomneud", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33431 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v4si3, "__builtin_ia32_vpcomnequd", IX86_BUILTIN_VPCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
33432 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomltud", IX86_BUILTIN_VPCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
33433 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomleud", IX86_BUILTIN_VPCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
33434 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgtud", IX86_BUILTIN_VPCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
33435 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv4si3, "__builtin_ia32_vpcomgeud", IX86_BUILTIN_VPCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
33437 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomequq", IX86_BUILTIN_VPCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
33438 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomneuq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33439 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_uns2v2di3, "__builtin_ia32_vpcomnequq", IX86_BUILTIN_VPCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
33440 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomltuq", IX86_BUILTIN_VPCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
33441 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomleuq", IX86_BUILTIN_VPCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
33442 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgtuq", IX86_BUILTIN_VPCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
33443 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_maskcmp_unsv2di3, "__builtin_ia32_vpcomgeuq", IX86_BUILTIN_VPCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
33445 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseb", IX86_BUILTIN_VPCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33446 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalsew", IX86_BUILTIN_VPCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33447 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalsed", IX86_BUILTIN_VPCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33448 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseq", IX86_BUILTIN_VPCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33449 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomfalseub",IX86_BUILTIN_VPCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
33450 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomfalseuw",IX86_BUILTIN_VPCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
33451 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomfalseud",IX86_BUILTIN_VPCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
33452 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomfalseuq",IX86_BUILTIN_VPCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
33454 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueb", IX86_BUILTIN_VPCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33455 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtruew", IX86_BUILTIN_VPCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33456 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrued", IX86_BUILTIN_VPCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33457 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueq", IX86_BUILTIN_VPCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33458 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv16qi3, "__builtin_ia32_vpcomtrueub", IX86_BUILTIN_VPCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
33459 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv8hi3, "__builtin_ia32_vpcomtrueuw", IX86_BUILTIN_VPCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
33460 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv4si3, "__builtin_ia32_vpcomtrueud", IX86_BUILTIN_VPCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
33461 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_pcom_tfv2di3, "__builtin_ia32_vpcomtrueuq", IX86_BUILTIN_VPCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
33463 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v2df3, "__builtin_ia32_vpermil2pd", IX86_BUILTIN_VPERMIL2PD, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I },
33464 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4sf3, "__builtin_ia32_vpermil2ps", IX86_BUILTIN_VPERMIL2PS, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I },
33465 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v4df3, "__builtin_ia32_vpermil2pd256", IX86_BUILTIN_VPERMIL2PD256, UNKNOWN, (int)MULTI_ARG_4_DF2_DI_I1 },
33466 { OPTION_MASK_ISA_XOP, CODE_FOR_xop_vpermil2v8sf3, "__builtin_ia32_vpermil2ps256", IX86_BUILTIN_VPERMIL2PS256, UNKNOWN, (int)MULTI_ARG_4_SF2_SI_I1 },
33468 };
33469 \f
33470 /* TM vector builtins. */
33472 /* Reuse the existing x86-specific `struct builtin_description' cause
33473 we're lazy. Add casts to make them fit. */
33475 {
33476 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33477 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33478 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
33479 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33480 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33481 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33482 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
33484 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33485 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33486 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_WaWM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
33487 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33488 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaRM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33489 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RaWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33490 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_RfWM128", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M128, UNKNOWN, V4SF_FTYPE_PCV4SF },
33492 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WM256", (enum ix86_builtins) BUILT_IN_TM_STORE_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33493 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaRM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33494 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_WaWM256", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M256, UNKNOWN, VOID_FTYPE_PV8SF_V8SF },
33495 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33496 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaRM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33497 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33498 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
33500 { OPTION_MASK_ISA_MMX, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
33501 { OPTION_MASK_ISA_SSE, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
33502 { OPTION_MASK_ISA_AVX, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
33503 };
33505 /* TM callbacks. */
33507 /* Return the builtin decl needed to load a vector of TYPE. */
33509 static tree
33511 {
33513 {
33515 {
33522 }
33523 }
33525 }
33527 /* Return the builtin decl needed to store a vector of TYPE. */
33529 static tree
33531 {
33533 {
33535 {
33542 }
33543 }
33545 }
33546 \f
33547 /* Initialize the transactional memory vector load/store builtins. */
33549 static void
33551 {
33555 tree decl;
33562 /* If there are no builtins defined, we must be compiling in a
33563 language without trans-mem support. */
33567 /* Use whatever attributes a normal TM load has. */
33571 /* Use whatever attributes a normal TM store has. */
33575 /* Use whatever attributes a normal TM log has. */
33583 {
33587 {
33595 {
33598 }
33600 {
33603 }
33604 else
33605 {
33608 }
33610 /* The builtin without the prefix for
33611 calling it directly. */
33613 attrs);
33614 /* add_builtin_function() will set the DECL_ATTRIBUTES, now
33615 set the TYPE_ATTRIBUTES. */
33619 }
33620 }
33621 }
33623 /* Set up all the MMX/SSE builtins, even builtins for instructions that are not
33624 in the current target ISA to allow the user to compile particular modules
33625 with different target specific options that differ from the command line
33626 options. */
33627 static void
33629 {
33634 /* Add all special builtins with variable number of operands. */
33638 {
33644 }
33646 /* Add all builtins with variable number of operands. */
33650 {
33656 }
33658 /* Add all builtins with rounding. */
33662 {
33668 }
33670 /* pcmpestr[im] insns. */
33674 {
33677 else
33680 }
33682 /* pcmpistr[im] insns. */
33686 {
33689 else
33692 }
33694 /* comi/ucomi insns. */
33696 {
33699 else
33702 }
33704 /* SSE */
33710 /* SSE or 3DNow!A */
33713 IX86_BUILTIN_MASKMOVQ);
33715 /* SSE2 */
33724 /* SSE3. */
33730 /* AES */
33744 /* PCLMUL */
33748 /* RDRND */
33755 IX86_BUILTIN_RDRAND64_STEP);
33757 /* AVX2 */
33759 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_V2DF_INT,
33760 IX86_BUILTIN_GATHERSIV2DF);
33763 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_V4DF_INT,
33764 IX86_BUILTIN_GATHERSIV4DF);
33767 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_V2DF_INT,
33768 IX86_BUILTIN_GATHERDIV2DF);
33771 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_V4DF_INT,
33772 IX86_BUILTIN_GATHERDIV4DF);
33775 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_V4SF_INT,
33776 IX86_BUILTIN_GATHERSIV4SF);
33779 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_V8SF_INT,
33780 IX86_BUILTIN_GATHERSIV8SF);
33783 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_V4SF_INT,
33784 IX86_BUILTIN_GATHERDIV4SF);
33787 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_V4SF_INT,
33788 IX86_BUILTIN_GATHERDIV8SF);
33791 V2DI_FTYPE_V2DI_PCINT64_V4SI_V2DI_INT,
33792 IX86_BUILTIN_GATHERSIV2DI);
33795 V4DI_FTYPE_V4DI_PCINT64_V4SI_V4DI_INT,
33796 IX86_BUILTIN_GATHERSIV4DI);
33799 V2DI_FTYPE_V2DI_PCINT64_V2DI_V2DI_INT,
33800 IX86_BUILTIN_GATHERDIV2DI);
33803 V4DI_FTYPE_V4DI_PCINT64_V4DI_V4DI_INT,
33804 IX86_BUILTIN_GATHERDIV4DI);
33807 V4SI_FTYPE_V4SI_PCINT_V4SI_V4SI_INT,
33808 IX86_BUILTIN_GATHERSIV4SI);
33811 V8SI_FTYPE_V8SI_PCINT_V8SI_V8SI_INT,
33812 IX86_BUILTIN_GATHERSIV8SI);
33815 V4SI_FTYPE_V4SI_PCINT_V2DI_V4SI_INT,
33816 IX86_BUILTIN_GATHERDIV4SI);
33819 V4SI_FTYPE_V4SI_PCINT_V4DI_V4SI_INT,
33820 IX86_BUILTIN_GATHERDIV8SI);
33823 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_V4DF_INT,
33824 IX86_BUILTIN_GATHERALTSIV4DF);
33827 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_V8SF_INT,
33828 IX86_BUILTIN_GATHERALTDIV8SF);
33831 V4DI_FTYPE_V4DI_PCINT64_V8SI_V4DI_INT,
33832 IX86_BUILTIN_GATHERALTSIV4DI);
33835 V8SI_FTYPE_V8SI_PCINT_V4DI_V8SI_INT,
33836 IX86_BUILTIN_GATHERALTDIV8SI);
33838 /* AVX512F */
33840 V16SF_FTYPE_V16SF_PCFLOAT_V16SI_HI_INT,
33841 IX86_BUILTIN_GATHER3SIV16SF);
33844 V8DF_FTYPE_V8DF_PCDOUBLE_V8SI_QI_INT,
33845 IX86_BUILTIN_GATHER3SIV8DF);
33848 V8SF_FTYPE_V8SF_PCFLOAT_V8DI_QI_INT,
33849 IX86_BUILTIN_GATHER3DIV16SF);
33852 V8DF_FTYPE_V8DF_PCDOUBLE_V8DI_QI_INT,
33853 IX86_BUILTIN_GATHER3DIV8DF);
33856 V16SI_FTYPE_V16SI_PCINT_V16SI_HI_INT,
33857 IX86_BUILTIN_GATHER3SIV16SI);
33860 V8DI_FTYPE_V8DI_PCINT64_V8SI_QI_INT,
33861 IX86_BUILTIN_GATHER3SIV8DI);
33864 V8SI_FTYPE_V8SI_PCINT_V8DI_QI_INT,
33865 IX86_BUILTIN_GATHER3DIV16SI);
33868 V8DI_FTYPE_V8DI_PCINT64_V8DI_QI_INT,
33869 IX86_BUILTIN_GATHER3DIV8DI);
33872 V8DF_FTYPE_V8DF_PCDOUBLE_V16SI_QI_INT,
33873 IX86_BUILTIN_GATHER3ALTSIV8DF);
33876 V16SF_FTYPE_V16SF_PCFLOAT_V8DI_HI_INT,
33877 IX86_BUILTIN_GATHER3ALTDIV16SF);
33880 V8DI_FTYPE_V8DI_PCINT64_V16SI_QI_INT,
33881 IX86_BUILTIN_GATHER3ALTSIV8DI);
33884 V16SI_FTYPE_V16SI_PCINT_V8DI_HI_INT,
33885 IX86_BUILTIN_GATHER3ALTDIV16SI);
33888 VOID_FTYPE_PFLOAT_HI_V16SI_V16SF_INT,
33889 IX86_BUILTIN_SCATTERSIV16SF);
33892 VOID_FTYPE_PDOUBLE_QI_V8SI_V8DF_INT,
33893 IX86_BUILTIN_SCATTERSIV8DF);
33896 VOID_FTYPE_PFLOAT_QI_V8DI_V8SF_INT,
33897 IX86_BUILTIN_SCATTERDIV16SF);
33900 VOID_FTYPE_PDOUBLE_QI_V8DI_V8DF_INT,
33901 IX86_BUILTIN_SCATTERDIV8DF);
33904 VOID_FTYPE_PINT_HI_V16SI_V16SI_INT,
33905 IX86_BUILTIN_SCATTERSIV16SI);
33908 VOID_FTYPE_PLONGLONG_QI_V8SI_V8DI_INT,
33909 IX86_BUILTIN_SCATTERSIV8DI);
33912 VOID_FTYPE_PINT_QI_V8DI_V8SI_INT,
33913 IX86_BUILTIN_SCATTERDIV16SI);
33916 VOID_FTYPE_PLONGLONG_QI_V8DI_V8DI_INT,
33917 IX86_BUILTIN_SCATTERDIV8DI);
33919 /* AVX512VL */
33921 V2DF_FTYPE_V2DF_PCDOUBLE_V4SI_QI_INT,
33922 IX86_BUILTIN_GATHER3SIV2DF);
33925 V4DF_FTYPE_V4DF_PCDOUBLE_V4SI_QI_INT,
33926 IX86_BUILTIN_GATHER3SIV4DF);
33929 V2DF_FTYPE_V2DF_PCDOUBLE_V2DI_QI_INT,
33930 IX86_BUILTIN_GATHER3DIV2DF);
33933 V4DF_FTYPE_V4DF_PCDOUBLE_V4DI_QI_INT,
33934 IX86_BUILTIN_GATHER3DIV4DF);
33937 V4SF_FTYPE_V4SF_PCFLOAT_V4SI_QI_INT,
33938 IX86_BUILTIN_GATHER3SIV4SF);
33941 V8SF_FTYPE_V8SF_PCFLOAT_V8SI_QI_INT,
33942 IX86_BUILTIN_GATHER3SIV8SF);
33945 V4SF_FTYPE_V4SF_PCFLOAT_V2DI_QI_INT,
33946 IX86_BUILTIN_GATHER3DIV4SF);
33949 V4SF_FTYPE_V4SF_PCFLOAT_V4DI_QI_INT,
33950 IX86_BUILTIN_GATHER3DIV8SF);
33953 V2DI_FTYPE_V2DI_PCINT64_V4SI_QI_INT,
33954 IX86_BUILTIN_GATHER3SIV2DI);
33957 V4DI_FTYPE_V4DI_PCINT64_V4SI_QI_INT,
33958 IX86_BUILTIN_GATHER3SIV4DI);
33961 V2DI_FTYPE_V2DI_PCINT64_V2DI_QI_INT,
33962 IX86_BUILTIN_GATHER3DIV2DI);
33965 V4DI_FTYPE_V4DI_PCINT64_V4DI_QI_INT,
33966 IX86_BUILTIN_GATHER3DIV4DI);
33969 V4SI_FTYPE_V4SI_PCINT_V4SI_QI_INT,
33970 IX86_BUILTIN_GATHER3SIV4SI);
33973 V8SI_FTYPE_V8SI_PCINT_V8SI_QI_INT,
33974 IX86_BUILTIN_GATHER3SIV8SI);
33977 V4SI_FTYPE_V4SI_PCINT_V2DI_QI_INT,
33978 IX86_BUILTIN_GATHER3DIV4SI);
33981 V4SI_FTYPE_V4SI_PCINT_V4DI_QI_INT,
33982 IX86_BUILTIN_GATHER3DIV8SI);
33985 V4DF_FTYPE_V4DF_PCDOUBLE_V8SI_QI_INT,
33986 IX86_BUILTIN_GATHER3ALTSIV4DF);
33989 V8SF_FTYPE_V8SF_PCFLOAT_V4DI_QI_INT,
33990 IX86_BUILTIN_GATHER3ALTDIV8SF);
33993 V4DI_FTYPE_V4DI_PCINT64_V8SI_QI_INT,
33994 IX86_BUILTIN_GATHER3ALTSIV4DI);
33997 V8SI_FTYPE_V8SI_PCINT_V4DI_QI_INT,
33998 IX86_BUILTIN_GATHER3ALTDIV8SI);
34001 VOID_FTYPE_PFLOAT_QI_V8SI_V8SF_INT,
34002 IX86_BUILTIN_SCATTERSIV8SF);
34005 VOID_FTYPE_PFLOAT_QI_V4SI_V4SF_INT,
34006 IX86_BUILTIN_SCATTERSIV4SF);
34009 VOID_FTYPE_PDOUBLE_QI_V4SI_V4DF_INT,
34010 IX86_BUILTIN_SCATTERSIV4DF);
34013 VOID_FTYPE_PDOUBLE_QI_V4SI_V2DF_INT,
34014 IX86_BUILTIN_SCATTERSIV2DF);
34017 VOID_FTYPE_PFLOAT_QI_V4DI_V4SF_INT,
34018 IX86_BUILTIN_SCATTERDIV8SF);
34021 VOID_FTYPE_PFLOAT_QI_V2DI_V4SF_INT,
34022 IX86_BUILTIN_SCATTERDIV4SF);
34025 VOID_FTYPE_PDOUBLE_QI_V4DI_V4DF_INT,
34026 IX86_BUILTIN_SCATTERDIV4DF);
34029 VOID_FTYPE_PDOUBLE_QI_V2DI_V2DF_INT,
34030 IX86_BUILTIN_SCATTERDIV2DF);
34033 VOID_FTYPE_PINT_QI_V8SI_V8SI_INT,
34034 IX86_BUILTIN_SCATTERSIV8SI);
34037 VOID_FTYPE_PINT_QI_V4SI_V4SI_INT,
34038 IX86_BUILTIN_SCATTERSIV4SI);
34041 VOID_FTYPE_PLONGLONG_QI_V4SI_V4DI_INT,
34042 IX86_BUILTIN_SCATTERSIV4DI);
34045 VOID_FTYPE_PLONGLONG_QI_V4SI_V2DI_INT,
34046 IX86_BUILTIN_SCATTERSIV2DI);
34049 VOID_FTYPE_PINT_QI_V4DI_V4SI_INT,
34050 IX86_BUILTIN_SCATTERDIV8SI);
34053 VOID_FTYPE_PINT_QI_V2DI_V4SI_INT,
34054 IX86_BUILTIN_SCATTERDIV4SI);
34057 VOID_FTYPE_PLONGLONG_QI_V4DI_V4DI_INT,
34058 IX86_BUILTIN_SCATTERDIV4DI);
34061 VOID_FTYPE_PLONGLONG_QI_V2DI_V2DI_INT,
34062 IX86_BUILTIN_SCATTERDIV2DI);
34064 /* AVX512PF */
34066 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
34067 IX86_BUILTIN_GATHERPFDPD);
34069 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
34070 IX86_BUILTIN_GATHERPFDPS);
34072 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
34073 IX86_BUILTIN_GATHERPFQPD);
34075 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
34076 IX86_BUILTIN_GATHERPFQPS);
34078 VOID_FTYPE_QI_V8SI_PCINT64_INT_INT,
34079 IX86_BUILTIN_SCATTERPFDPD);
34081 VOID_FTYPE_HI_V16SI_PCINT_INT_INT,
34082 IX86_BUILTIN_SCATTERPFDPS);
34084 VOID_FTYPE_QI_V8DI_PCINT64_INT_INT,
34085 IX86_BUILTIN_SCATTERPFQPD);
34087 VOID_FTYPE_QI_V8DI_PCINT_INT_INT,
34088 IX86_BUILTIN_SCATTERPFQPS);
34090 /* SHA */
34106 /* RTM. */
34110 /* MMX access to the vec_init patterns. */
34115 V4HI_FTYPE_HI_HI_HI_HI,
34116 IX86_BUILTIN_VEC_INIT_V4HI);
34119 V8QI_FTYPE_QI_QI_QI_QI_QI_QI_QI_QI,
34120 IX86_BUILTIN_VEC_INIT_V8QI);
34122 /* Access to the vec_extract patterns. */
34144 /* Access to the vec_set patterns. */
34165 /* RDSEED */
34174 /* ADCX */
34179 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34180 IX86_BUILTIN_ADDCARRYX64);
34182 /* SBB */
34187 UCHAR_FTYPE_UCHAR_ULONGLONG_ULONGLONG_PULONGLONG,
34188 IX86_BUILTIN_SBB64);
34190 /* Read/write FLAGS. */
34200 /* CLFLUSHOPT. */
34204 /* CLWB. */
34208 /* MONITORX and MWAITX. */
34214 /* Add FMA4 multi-arg argument instructions */
34216 {
34222 }
34223 }
34225 static void
34227 {
34230 tree decl;
34236 {
34243 /* With no leaf and nothrow flags for MPX builtins
34244 abnormal edges may follow its call when setjmp
34245 presents in the function. Since we may have a lot
34246 of MPX builtins calls it causes lots of useless
34247 edges and enormous PHI nodes. To avoid this we mark
34248 MPX builtins as leaf and nothrow. */
34250 {
34252 NULL_TREE);
34254 }
34255 else
34256 {
34259 }
34260 }
34265 {
34273 {
34275 NULL_TREE);
34277 }
34278 else
34279 {
34282 }
34283 }
34284 }
34286 /* This adds a condition to the basic_block NEW_BB in function FUNCTION_DECL
34287 to return a pointer to VERSION_DECL if the outcome of the expression
34288 formed by PREDICATE_CHAIN is true. This function will be called during
34289 version dispatch to decide which function version to execute. It returns
34290 the basic block at the end, to which more conditions can be added. */
34292 static basic_block
34295 {
34296 gimple return_stmt;
34298 gimple convert_stmt;
34299 gimple call_cond_stmt;
34300 gimple if_else_stmt;
34306 gimple_seq gseq;
34323 {
34331 }
34334 {
34349 else
34350 {
34351 gimple assign_stmt;
34352 /* Use MIN_EXPR to check if any integer is zero?.
34353 and_expr_var = min_expr <cond_var, and_expr_var> */
34361 }
34362 }
34365 integer_zero_node,
34395 }
34397 /* This parses the attribute arguments to target in DECL and determines
34398 the right builtin to use to match the platform specification.
34399 It returns the priority value for this version decl. If PREDICATE_LIST
34400 is not NULL, it stores the list of cpu features that need to be checked
34401 before dispatching this function. */
34403 static unsigned int
34405 {
34406 tree attrs;
34408 tree target_node;
34415 /* Priority of i386 features, greater value is higher priority. This is
34416 used to decide the order in which function dispatch must happen. For
34417 instance, a version specialized for SSE4.2 should be checked for dispatch
34418 before a version for SSE3, as SSE4.2 implies SSE3. */
34419 enum feature_priority
34420 {
34422 P_MMX,
34423 P_SSE,
34424 P_SSE2,
34425 P_SSE3,
34426 P_SSSE3,
34427 P_PROC_SSSE3,
34428 P_SSE4_A,
34429 P_PROC_SSE4_A,
34430 P_SSE4_1,
34431 P_SSE4_2,
34432 P_PROC_SSE4_2,
34433 P_POPCNT,
34434 P_AVX,
34435 P_PROC_AVX,
34436 P_BMI,
34437 P_PROC_BMI,
34438 P_FMA4,
34439 P_XOP,
34440 P_PROC_XOP,
34441 P_FMA,
34442 P_PROC_FMA,
34443 P_BMI2,
34444 P_AVX2,
34445 P_PROC_AVX2,
34446 P_AVX512F,
34447 P_PROC_AVX512F
34448 };
34452 /* These are the target attribute strings for which a dispatcher is
34453 available, from fold_builtin_cpu. */
34455 static struct _feature_list
34456 {
34459 }
34461 {
34479 };
34482 static unsigned int NUM_FEATURES
34498 /* Return priority zero for default function. */
34502 /* Handle arch= if specified. For priority, set it to be 1 more than
34503 the best instruction set the processor can handle. For instance, if
34504 there is a version for atom and a version for ssse3 (the highest ISA
34505 priority for atom), the atom version must be checked for dispatch
34506 before the ssse3 version. */
34508 {
34518 {
34520 {
34528 else
34529 /* We translate "arch=corei7" and "arch=nehalem" to
34530 "corei7" so that it will be mapped to M_INTEL_COREI7
34531 as cpu type to cover all M_INTEL_COREI7_XXXs. */
34538 else
34545 else
34589 }
34590 }
34595 {
34599 }
34602 {
34604 /* For a C string literal the length includes the trailing NULL. */
34607 predicate_chain);
34608 }
34609 }
34611 /* Process feature name. */
34618 {
34619 /* Do not process "arch=" */
34621 {
34624 }
34626 {
34628 {
34630 {
34635 predicate_chain);
34636 }
34637 /* Find the maximum priority feature. */
34642 }
34643 }
34645 {
34649 }
34651 }
34655 {
34658 attrs_str);
34660 }
34662 {
34665 }
34668 }
34670 /* This compares the priority of target features in function DECL1
34671 and DECL2. It returns positive value if DECL1 is higher priority,
34672 negative value if DECL2 is higher priority and 0 if they are the
34673 same. */
34675 static int
34677 {
34682 }
34684 /* V1 and V2 point to function versions with different priorities
34685 based on the target ISA. This function compares their priorities. */
34687 static int
34689 {
34691 {
34692 tree version_decl;
34693 tree predicate_chain;
34700 }
34702 /* This function generates the dispatch function for
34703 multi-versioned functions. DISPATCH_DECL is the function which will
34704 contain the dispatch logic. FNDECLS are the function choices for
34705 dispatch, and is a tree chain. EMPTY_BB is the basic block pointer
34706 in DISPATCH_DECL in which the dispatch code is generated. */
34708 static int
34712 {
34713 tree default_decl;
34714 gimple ifunc_cpu_init_stmt;
34715 gimple_seq gseq;
34717 tree ele;
34723 struct _function_version_info
34724 {
34725 tree version_decl;
34726 tree predicate_chain;
34734 /*fndecls_p is actually a vector. */
34737 /* At least one more version other than the default. */
34744 /* The first version in the vector is the default decl. */
34750 /* Function version dispatch is via IFUNC. IFUNC resolvers fire before
34751 constructors, so explicity call __builtin_cpu_init here. */
34762 {
34766 /* Get attribute string, parse it and find the right predicate decl.
34767 The predicate function could be a lengthy combination of many
34768 features, like arch-type and various isa-variants. */
34779 actual_versions++;
34780 }
34782 /* Sort the versions according to descending order of dispatch priority. The
34783 priority is based on the ISA. This is not a perfect solution. There
34784 could still be ambiguity. If more than one function version is suitable
34785 to execute, which one should be dispatched? In future, allow the user
34786 to specify a dispatch priority next to the version. */
34796 /* dispatch default version at the end. */
34802 }
34804 /* Comparator function to be used in qsort routine to sort attribute
34805 specification strings to "target". */
34807 static int
34809 {
34813 }
34815 /* ARGLIST is the argument to target attribute. This function tokenizes
34816 the comma separated arguments, sorts them and returns a string which
34817 is a unique identifier for the comma separated arguments. It also
34818 replaces non-identifier characters "=,-" with "_". */
34822 {
34823 tree arg;
34832 {
34837 argnum++;
34840 argnum++;
34841 }
34846 {
34852 }
34854 /* Replace "=,-" with "_". */
34867 {
34869 i++;
34871 }
34878 {
34883 }
34888 }
34890 /* This function changes the assembler name for functions that are
34891 versions. If DECL is a function version and has a "target"
34892 attribute, it appends the attribute string to its assembler name. */
34894 static tree
34896 {
34897 tree version_attr;
34905 "Function versions cannot be marked as gnu_inline,"
34914 /* target attribute string cannot be NULL. */
34918 version_string
34929 /* Allow assembler name to be modified if already set. */
34937 }
34939 /* This function returns true if FN1 and FN2 are versions of the same function,
34940 that is, the target strings of the function decls are different. This assumes
34941 that FN1 and FN2 have the same signature. */
34943 static bool
34945 {
34957 /* At least one function decl should have the target attribute specified. */
34961 /* Diagnose missing target attribute if one of the decls is already
34962 multi-versioned. */
34964 {
34966 {
34968 {
34971 }
34974 fn2);
34977 /* Prevent diagnosing of the same error multiple times. */
34982 }
34984 }
34989 /* The sorted target strings must be different for fn1 and fn2
34990 to be versions. */
34993 else
35000 }
35002 static tree
35004 {
35005 /* For function version, add the target suffix to the assembler name. */
35009 #ifdef SUBTARGET_MANGLE_DECL_ASSEMBLER_NAME
35011 #endif
35014 }
35016 /* Return a new name by appending SUFFIX to the DECL name. If make_unique
35017 is true, append the full path name of the source file. */
35021 {
35029 /* Get a unique name that can be used globally without any chances
35030 of collision at link time. */
35040 /* Use '.' to concatenate names as it is demangler friendly. */
35043 suffix);
35044 else
35048 }
35050 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
35052 /* Make a dispatcher declaration for the multi-versioned function DECL.
35053 Calls to DECL function will be replaced with calls to the dispatcher
35054 by the front-end. Return the decl created. */
35056 static tree
35058 {
35059 tree func_decl;
35079 /* Mark this func as external, the resolver will flip it again if
35080 it gets generated. */
35082 /* This will be of type IFUNCs have to be externally visible. */
35086 }
35088 #endif
35090 /* Returns true if decl is multi-versioned and DECL is the default function,
35091 that is it is not tagged with target specific optimization. */
35093 static bool
35095 {
35104 }
35106 /* Make a dispatcher declaration for the multi-versioned function DECL.
35107 Calls to DECL function will be replaced with calls to the dispatcher
35108 by the front-end. Returns the decl of the dispatcher function. */
35110 static tree
35112 {
35134 /* Find the default version and make it the first node. */
35136 /* Go to the beginning of the chain. */
35141 {
35146 }
35148 /* If there is no default node, just return NULL. */
35152 /* Make default info the first node. */
35154 {
35161 }
35165 #if defined (ASM_OUTPUT_TYPE_DIRECTIVE)
35167 {
35172 /* Right now, the dispatching is done via ifunc. */
35178 dispatcher_version_info
35183 /* Set the dispatcher for all the versions. */
35186 {
35189 }
35190 }
35191 else
35192 #endif
35193 {
35195 "multiversioning needs ifunc which is not supported "
35197 }
35200 }
35202 /* Makes a function attribute of the form NAME(ARG_NAME) and chains
35203 it to CHAIN. */
35205 static tree
35207 {
35208 tree attr_name;
35209 tree attr_arg_name;
35210 tree attr_args;
35211 tree attr;
35218 }
35220 /* Make the resolver function decl to dispatch the versions of
35221 a multi-versioned function, DEFAULT_DECL. Create an
35222 empty basic block in the resolver and store the pointer in
35223 EMPTY_BB. Return the decl of the resolver function. */
35225 static tree
35229 {
35234 /* IFUNC's have to be globally visible. So, if the default_decl is
35235 not, then the name of the IFUNC should be made unique. */
35239 /* Append the filename to the resolver function if the versions are
35240 not externally visible. This is because the resolver function has
35241 to be externally visible for the loader to find it. So, appending
35242 the filename will prevent conflicts with a resolver function from
35243 another module which is based on the same version name. */
35246 /* The resolver function should return a (void *). */
35257 /* IFUNC resolvers have to be externally visible. */
35261 /* Resolver is not external, body is generated. */
35271 {
35272 /* In this case, each translation unit with a call to this
35273 versioned function will put out a resolver. Ensure it
35274 is comdat to keep just one copy. */
35277 }
35278 /* Build result decl and add to function_decl. */
35294 /* Mark dispatch_decl as "ifunc" with resolver as resolver_name. */
35298 /* Create the alias for dispatch to resolver here. */
35299 /*cgraph_create_function_alias (dispatch_decl, decl);*/
35303 }
35305 /* Generate the dispatching code body to dispatch multi-versioned function
35306 DECL. The target hook is called to process the "target" attributes and
35307 provide the code to dispatch the right function at run-time. NODE points
35308 to the dispatcher decl whose body will be created. */
35310 static tree
35312 {
35313 tree resolver_decl;
35314 basic_block empty_bb;
35315 tree default_ver_decl;
35331 /* The first version in the chain corresponds to the default version. */
35334 /* node is going to be an alias, so remove the finalized bit. */
35348 {
35350 /* Check for virtual functions here again, as by this time it should
35351 have been determined if this function needs a vtable index or
35352 not. This happens for methods in derived classes that override
35353 virtual methods in base classes but are not explicitly marked as
35354 virtual. */
35359 }
35365 }
35366 /* This builds the processor_model struct type defined in
35367 libgcc/config/i386/cpuinfo.c */
35369 static tree
35371 {
35378 /* The first 3 fields are unsigned int. */
35380 {
35386 }
35388 /* The last field is an array of unsigned integers of size one. */
35399 }
35401 /* Returns a extern, comdat VAR_DECL of type TYPE and name NAME. */
35403 static tree
35405 {
35406 tree new_decl;
35409 VAR_DECL,
35411 type);
35424 }
35426 /* FNDECL is a __builtin_cpu_is or a __builtin_cpu_supports call that is folded
35427 into an integer defined in libgcc/config/i386/cpuinfo.c */
35429 static tree
35431 {
35437 /* This is the order of bit-fields in __processor_features in cpuinfo.c */
35438 enum processor_features
35439 {
35441 F_MMX,
35442 F_POPCNT,
35443 F_SSE,
35444 F_SSE2,
35445 F_SSE3,
35446 F_SSSE3,
35447 F_SSE4_1,
35448 F_SSE4_2,
35449 F_AVX,
35450 F_AVX2,
35451 F_SSE4_A,
35452 F_FMA4,
35453 F_XOP,
35454 F_FMA,
35455 F_AVX512F,
35456 F_BMI,
35457 F_BMI2,
35458 F_MAX
35459 };
35461 /* These are the values for vendor types and cpu types and subtypes
35462 in cpuinfo.c. Cpu types and subtypes should be subtracted by
35463 the corresponding start value. */
35464 enum processor_model
35465 {
35467 M_AMD,
35468 M_CPU_TYPE_START,
35469 M_INTEL_BONNELL,
35470 M_INTEL_CORE2,
35471 M_INTEL_COREI7,
35472 M_AMDFAM10H,
35473 M_AMDFAM15H,
35474 M_INTEL_SILVERMONT,
35475 M_INTEL_KNL,
35476 M_AMD_BTVER1,
35477 M_AMD_BTVER2,
35478 M_CPU_SUBTYPE_START,
35479 M_INTEL_COREI7_NEHALEM,
35480 M_INTEL_COREI7_WESTMERE,
35481 M_INTEL_COREI7_SANDYBRIDGE,
35482 M_AMDFAM10H_BARCELONA,
35483 M_AMDFAM10H_SHANGHAI,
35484 M_AMDFAM10H_ISTANBUL,
35485 M_AMDFAM15H_BDVER1,
35486 M_AMDFAM15H_BDVER2,
35487 M_AMDFAM15H_BDVER3,
35488 M_AMDFAM15H_BDVER4,
35489 M_INTEL_COREI7_IVYBRIDGE,
35490 M_INTEL_COREI7_HASWELL,
35491 M_INTEL_COREI7_BROADWELL
35492 };
35494 static struct _arch_names_table
35495 {
35498 }
35500 {
35527 };
35529 static struct _isa_names_table
35530 {
35533 }
35535 {
35554 };
35568 {
35569 /* *args must be a expr that can contain other EXPRS leading to a
35570 STRING_CST. */
35572 {
35575 }
35577 }
35582 {
35583 tree ref;
35584 tree field;
35585 tree final;
35588 unsigned int NUM_ARCH_NAMES
35597 {
35601 }
35606 /* CPU types are stored in the next field. */
35609 {
35612 }
35614 /* CPU subtypes are stored in the next field. */
35616 {
35619 }
35621 /* Get the appropriate field in __cpu_model. */
35625 /* Check the value. */
35629 }
35631 {
35632 tree ref;
35633 tree array_elt;
35634 tree field;
35635 tree final;
35638 unsigned int NUM_ISA_NAMES
35647 {
35651 }
35654 /* Get the last field, which is __cpu_features. */
35658 /* Get the appropriate field: __cpu_model.__cpu_features */
35662 /* Access the 0th element of __cpu_features array. */
35667 /* Return __cpu_model.__cpu_features[0] & field_val */
35671 }
35673 }
35675 static tree
35678 {
35680 {
35685 {
35688 }
35689 }
35691 #ifdef SUBTARGET_FOLD_BUILTIN
35693 #endif
35696 }
35698 /* Make builtins to detect cpu type and features supported. NAME is
35699 the builtin name, CODE is the builtin code, and FTYPE is the function
35700 type of the builtin. */
35702 static void
35705 {
35706 tree decl;
35707 tree type;
35715 }
35717 /* Make builtins to get CPU type and features supported. The created
35718 builtins are :
35720 __builtin_cpu_init (), to detect cpu type and features,
35721 __builtin_cpu_is ("<CPUNAME>"), to check if cpu is of type <CPUNAME>,
35722 __builtin_cpu_supports ("<FEATURE>"), to check if cpu supports <FEATURE>
35723 */
35725 static void
35727 {
35734 }
35736 /* Internal method for ix86_init_builtins. */
35738 static void
35740 {
35752 sysv_va_ref =
35755 fnvoid_va_end_ms =
35757 fnvoid_va_start_ms =
35759 fnvoid_va_end_sysv =
35761 fnvoid_va_start_sysv =
35763 NULL_TREE);
35764 fnvoid_va_copy_ms =
35766 NULL_TREE);
35767 fnvoid_va_copy_sysv =
35783 }
35785 static void
35787 {
35790 /* The __float80 type. */
35793 {
35794 /* The __float80 type. */
35799 }
35802 /* The __float128 type. */
35808 /* This macro is built by i386-builtin-types.awk. */
35809 DEFINE_BUILTIN_PRIMITIVE_TYPES;
35810 }
35812 static void
35814 {
35815 tree t;
35819 /* Builtins to get CPU type and features. */
35822 /* TFmode support builtins. */
35828 /* We will expand them to normal call if SSE isn't available since
35829 they are used by libgcc. */
35849 #ifdef SUBTARGET_INIT_BUILTINS
35850 SUBTARGET_INIT_BUILTINS;
35851 #endif
35852 }
35854 /* Return the ix86 builtin for CODE. */
35856 static tree
35858 {
35863 }
35865 /* Errors in the source file can cause expand_expr to return const0_rtx
35866 where we expect a vector. To avoid crashing, use one of the vector
35867 clear instructions. */
35868 static rtx
35870 {
35874 }
35876 /* Fixup modeless constants to fit required mode. */
35877 static rtx
35879 {
35883 }
35885 /* Subroutine of ix86_expand_builtin to take care of binop insns. */
35887 static rtx
35889 {
35890 rtx pat;
35910 {
35914 }
35928 }
35930 /* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
35932 static rtx
35936 {
35937 rtx pat;
35945 rtx op;
35946 machine_mode mode;
35952 {
36032 }
36042 {
36049 {
36051 {
36054 {
36072 xop_rotl:
36074 {
36077 gcc_checking_assert
36079 }
36080 else
36081 {
36082 gcc_checking_assert
36093 }
36097 }
36098 }
36099 }
36100 else
36101 {
36102 non_constant:
36106 /* If we aren't optimizing, only allow one memory operand to be
36107 generated. */
36109 num_memory++;
36117 }
36121 }
36124 {
36135 else
36136 {
36142 }
36155 }
36162 }
36164 /* Subroutine of ix86_expand_args_builtin to take care of scalar unop
36165 insns with vec_merge. */
36167 static rtx
36169 rtx target)
36170 {
36171 rtx pat;
36198 }
36200 /* Subroutine of ix86_expand_builtin to take care of comparison insns. */
36202 static rtx
36205 {
36206 rtx pat;
36211 rtx op2;
36222 /* Swap operands if we have a comparison that isn't available in
36223 hardware. */
36245 }
36247 /* Subroutine of ix86_expand_builtin to take care of comi insns. */
36249 static rtx
36251 rtx target)
36252 {
36253 rtx pat;
36267 /* Swap operands if we have a comparison that isn't available in
36268 hardware. */
36290 const0_rtx)));
36293 }
36295 /* Subroutines of ix86_expand_args_builtin to take care of round insns. */
36297 static rtx
36299 rtx target)
36300 {
36301 rtx pat;
36326 }
36328 static rtx
36331 {
36332 rtx pat;
36337 rtx op2;
36364 }
36366 /* Subroutine of ix86_expand_builtin to take care of ptest insns. */
36368 static rtx
36370 rtx target)
36371 {
36372 rtx pat;
36404 const0_rtx)));
36407 }
36409 /* Subroutine of ix86_expand_builtin to take care of pcmpestr[im] insns. */
36411 static rtx
36414 {
36415 rtx pat;
36453 {
36456 }
36459 {
36468 }
36470 {
36479 }
36480 else
36481 {
36488 }
36496 {
36501 emit_insn
36505 FLAGS_REG),
36506 const0_rtx)));
36508 }
36509 else
36511 }
36514 /* Subroutine of ix86_expand_builtin to take care of pcmpistr[im] insns. */
36516 static rtx
36519 {
36520 rtx pat;
36548 {
36551 }
36554 {
36563 }
36565 {
36574 }
36575 else
36576 {
36583 }
36591 {
36596 emit_insn
36600 FLAGS_REG),
36601 const0_rtx)));
36603 }
36604 else
36606 }
36608 /* Subroutine of ix86_expand_builtin to take care of insns with
36609 variable number of operands. */
36611 static rtx
36614 {
36620 struct
36621 {
36622 rtx op;
36623 machine_mode mode;
36634 {
37344 }
37349 {
37352 }
37355 {
37362 }
37363 else
37364 {
37367 }
37370 {
37377 {
37378 /* SIMD shift insns take either an 8-bit immediate or
37379 register as count. But builtin functions take int as
37380 count. If count doesn't match, we put it in register. */
37382 {
37386 }
37387 }
37390 {
37393 {
37502 {
37506 {
37509 }
37515 }
37517 }
37518 }
37519 else
37520 {
37524 /* If we aren't optimizing, only allow one memory operand to
37525 be generated. */
37527 num_memory++;
37532 {
37535 }
37536 else
37537 {
37540 }
37541 }
37545 }
37548 {
37573 }
37580 }
37582 /* Transform pattern of following layout:
37583 (parallel [
37584 set (A B)
37585 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)])
37586 ])
37587 into:
37588 (set (A B))
37590 Or:
37591 (parallel [ A B
37592 ...
37593 (unspec [C] UNSPEC_EMBEDDED_ROUNDING)
37594 ...
37595 ])
37596 into:
37597 (parallel [ A B ... ]) */
37599 static rtx
37601 {
37608 {
37617 }
37618 else
37619 {
37625 {
37630 }
37632 /* No more than 1 occurence was removed. */
37636 }
37637 }
37639 /* Subroutine of ix86_expand_round_builtin to take care of comi insns
37640 with rounding. */
37641 static rtx
37644 {
37661 /* See avxintrin.h for values. */
37663 {
37667 };
37669 {
37674 };
37677 {
37680 }
37682 {
37685 }
37688 {
37691 }
37714 ? CODE_FOR_sse_ucomi_round
37721 /* Rounding operand can be either NO_ROUND or ROUND_SAE at this point. */
37723 {
37729 }
37730 else
37731 {
37734 }
37739 set_dst,
37740 const0_rtx)));
37743 }
37745 static rtx
37748 {
37749 rtx pat;
37751 struct
37752 {
37753 rtx op;
37754 machine_mode mode;
37763 {
37846 }
37856 {
37863 {
37865 {
37867 {
37883 }
37884 }
37885 }
37887 {
37889 {
37892 }
37894 /* If there is no rounding use normal version of the pattern. */
37897 }
37898 else
37899 {
37906 {
37909 }
37910 else
37911 {
37914 }
37915 }
37919 }
37922 {
37947 }
37957 }
37959 /* Subroutine of ix86_expand_builtin to take care of special insns
37960 with variable number of operands. */
37962 static rtx
37965 {
37966 tree arg;
37970 struct
37971 {
37972 rtx op;
37973 machine_mode mode;
37982 {
38022 {
38030 }
38049 /* Reserve memory operand for target. */
38052 {
38053 /* These builtins and instructions require the memory
38054 to be properly aligned. */
38073 }
38102 {
38103 /* These builtins and instructions require the memory
38104 to be properly aligned. */
38121 }
38122 /* FALLTHRU */
38160 /* Reserve memory operand for target. */
38187 {
38188 /* These builtins and instructions require the memory
38189 to be properly aligned. */
38212 }
38225 }
38230 {
38235 {
38238 /* target at this point has just BITS_PER_UNIT MEM_ALIGN
38239 on it. Try to improve it using get_pointer_alignment,
38240 and if the special builtin is one that requires strict
38241 mode alignment, also from it's GET_MODE_ALIGNMENT.
38242 Failure to do so could lead to ix86_legitimate_combined_insn
38243 rejecting all changes to such insns. */
38249 }
38250 else
38253 }
38254 else
38255 {
38262 }
38265 {
38274 {
38276 {
38282 else
38285 }
38286 }
38287 else
38288 {
38290 {
38291 /* This must be the memory operand. */
38294 /* op at this point has just BITS_PER_UNIT MEM_ALIGN
38295 on it. Try to improve it using get_pointer_alignment,
38296 and if the special builtin is one that requires strict
38297 mode alignment, also from it's GET_MODE_ALIGNMENT.
38298 Failure to do so could lead to ix86_legitimate_combined_insn
38299 rejecting all changes to such insns. */
38305 }
38306 else
38307 {
38308 /* This must be register. */
38316 else
38317 {
38320 }
38321 }
38322 }
38326 }
38329 {
38344 }
38350 }
38352 /* Return the integer constant in ARG. Constrain it to be in the range
38353 of the subparts of VEC_TYPE; issue an error if not. */
38355 static int
38357 {
38362 {
38365 }
38368 }
38370 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38371 ix86_expand_vector_init. We DO have language-level syntax for this, in
38372 the form of (type){ init-list }. Except that since we can't place emms
38373 instructions from inside the compiler, we can't allow the use of MMX
38374 registers unless the user explicitly asks for it. So we do *not* define
38375 vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead
38376 we have builtins invoked by mmintrin.h that gives us license to emit
38377 these sorts of instructions. */
38379 static rtx
38381 {
38391 {
38394 }
38401 }
38403 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38404 ix86_expand_vector_extract. They would be redundant (for non-MMX) if we
38405 had a language-level syntax for referencing vector elements. */
38407 static rtx
38409 {
38413 rtx op0;
38433 }
38435 /* A subroutine of ix86_expand_builtin. These builtins are a wrapper around
38436 ix86_expand_vector_set. They would be redundant (for non-MMX) if we had
38437 a language-level syntax for referencing vector elements. */
38439 static rtx
38441 {
38465 /* OP0 is the source of these builtin functions and shouldn't be
38466 modified. Create a copy, use it and return it as target. */
38472 }
38474 /* Emit conditional move of SRC to DST with condition
38475 OP1 CODE OP2. */
38476 static void
38478 {
38479 rtx t;
38482 {
38486 }
38487 else
38488 {
38494 }
38495 }
38497 /* Choose max of DST and SRC and put it to DST. */
38498 static void
38500 {
38502 }
38504 /* Expand an expression EXP that calls a built-in function,
38505 with result going to TARGET if that's convenient
38506 (and in mode MODE if that's convenient).
38507 SUBTARGET may be used as the target for computing one of EXP's operands.
38508 IGNORE is nonzero if the value is to be ignored. */
38510 static rtx
38513 {
38523 /* For CPU builtins that can be folded, fold first and expand the fold. */
38525 {
38527 {
38528 /* Make it call __cpu_indicator_init in libgcc. */
38534 }
38537 {
38542 }
38543 }
38545 /* Determine whether the builtin function is available under the current ISA.
38546 Originally the builtin was not created if it wasn't applicable to the
38547 current ISA based on the command line switches. With function specific
38548 options, we need to check in the context of the function making the call
38549 whether it is supported. */
38552 {
38558 else
38559 {
38563 }
38565 }
38568 {
38586 /* Builtin arg1 is size of block but instruction op1 should
38587 be (size - 1). */
38678 /* If no bounds were specified for returned value,
38679 then use INIT bounds. It usually happens when
38680 some built-in function is expanded. */
38682 {
38691 }
38697 {
38700 /* Return value and lb. */
38702 /* Bounds. */
38704 /* Size. */
38711 /* Size was passed but we need to use (size - 1) as for bndmk. */
38715 /* Add LB to size and inverse to get UB. */
38725 /* We need to move bounds to memory before any computations. */
38728 else
38729 {
38732 }
38734 /* Generate mem expression to be used for access to LB and UB. */
38740 /* Compute LB. */
38745 /* Compute UB. UB is stored in 1's complement form. Therefore
38746 we also use max here. */
38755 }
38758 {
38776 /* Put first bounds to temporaries. */
38780 {
38784 }
38785 else
38786 {
38790 }
38792 /* Put second bounds to temporaries. */
38796 {
38800 }
38801 else
38802 {
38806 }
38808 /* Compute LB. */
38812 /* Compute UB. UB is stored in 1's complement form. Therefore
38813 we also use max here. */
38820 }
38823 {
38824 tree name;
38825 rtx symbol;
38843 }
38846 {
38857 /* We need to move bounds to memory first. */
38860 else
38861 {
38864 }
38866 /* Generate mem expression to access LB and load it. */
38871 }
38874 {
38885 /* We need to move bounds to memory first. */
38888 else
38889 {
38892 }
38894 /* Generate mem expression to access UB. */
38897 /* We need to inverse all bits of UB. */
38904 }
38909 ? CODE_FOR_mmx_maskmovq
38911 /* Note the arg order is different from the operand order. */
39052 {
39053 REAL_VALUE_TYPE inf;
39054 rtx tmp;
39066 }
39076 {
39082 insn = (TARGET_64BIT
39086 }
39088 {
39089 insn = (TARGET_64BIT
39093 }
39094 else
39095 {
39098 insn = (TARGET_64BIT
39106 {
39109 }
39111 }
39114 {
39115 /* mode is VOIDmode if __builtin_rd* has been called
39116 without lhs. */
39120 }
39123 {
39128 }
39141 {
39162 }
39168 {
39171 }
39197 {
39200 }
39206 {
39210 {
39249 }
39254 }
39255 else
39256 {
39258 {
39279 }
39281 }
39311 ? CODE_FOR_tbm_bextri_si
39314 {
39317 }
39318 else
39319 {
39328 }
39344 rdrand_step:
39351 {
39354 }
39360 /* Emit SImode conditional move. */
39362 {
39365 }
39368 else
39376 const0_rtx);
39395 rdseed_step:
39402 {
39405 }
39411 const0_rtx);
39440 addcarryx:
39448 /* Generate CF from input operand. */
39453 /* Gen ADCX instruction to compute X+Y+CF. */
39468 /* Store the result. */
39471 {
39474 }
39477 /* Return current CF value. */
39519 kortest:
39533 /* Emit kortest. */
39535 /* And use setcc to return result from flags. */
39793 gather_gen:
39794 rtx half;
39807 /* Note the arg order is different from the operand order. */
39818 else
39822 {
39846 else
39853 {
39858 }
39867 else
39874 {
39879 }
39883 }
39885 /* Force memory operand only with base register here. But we
39886 don't want to do it on memory operand for other builtin
39887 functions. */
39900 {
39903 }
39904 else
39905 {
39908 }
39910 {
39913 }
39915 /* Optimize. If mask is known to have all high bits set,
39916 replace op0 with pc_rtx to signal that the instruction
39917 overwrites the whole destination and doesn't use its
39918 previous contents. */
39920 {
39922 {
39925 }
39927 {
39930 {
39934 negative++;
39937 negative++;
39938 }
39941 }
39944 {
39945 /* Recognize also when mask is like:
39946 __v2df src = _mm_setzero_pd ();
39947 __v2df mask = _mm_cmpeq_pd (src, src);
39948 or
39949 __v8sf src = _mm256_setzero_ps ();
39950 __v8sf mask = _mm256_cmp_ps (src, src, _CMP_EQ_OQ);
39951 as that is a cheaper way to load all ones into
39952 a register than having to load a constant from
39953 memory. */
39956 {
39961 {
39968 /* FALLTHRU */
39978 }
39979 }
39980 }
39981 }
39989 {
40015 }
40018 scatter_gen:
40034 /* Force memory operand only with base register here. But we
40035 don't want to do it on memory operand for other builtin
40036 functions. */
40045 {
40048 }
40049 else
40050 {
40053 }
40062 {
40065 }
40074 vec_prefetch_gen:
40094 {
40097 }
40099 {
40102 }
40107 /* Force memory operand only with base register here. But we
40108 don't want to do it on memory operand for other builtin
40109 functions. */
40116 {
40119 }
40122 {
40125 }
40141 {
40144 }
40150 }
40163 {
40167 /* Emit a normal call if SSE isn't available. */
40171 }
40200 }
40202 /* This returns the target-specific builtin with code CODE if
40203 current_function_decl has visibility on this builtin, which is checked
40204 using isa flags. Returns NULL_TREE otherwise. */
40207 {
40211 /* Determine the isa flags of current_function_decl. */
40223 else
40225 }
40227 /* Return function decl for target specific builtin
40228 for given MPX builtin passed i FCODE. */
40229 static tree
40231 {
40233 {
40269 }
40272 }
40274 /* Helper function for ix86_load_bounds and ix86_store_bounds.
40276 Return an address to be used to load/store bounds for pointer
40277 passed in SLOT.
40279 SLOT_NO is an integer constant holding number of a target
40280 dependent special slot to be used in case SLOT is not a memory.
40282 SPECIAL_BASE is a pointer to be used as a base of fake address
40283 to access special slots in Bounds Table. SPECIAL_BASE[-1],
40284 SPECIAL_BASE[-2] etc. will be used as fake pointer locations. */
40286 static rtx
40288 {
40291 /* NULL slot means we pass bounds for pointer not passed to the
40292 function at all. Register slot means we pass pointer in a
40293 register. In both these cases bounds are passed via Bounds
40294 Table. Since we do not have actual pointer stored in memory,
40295 we have to use fake addresses to access Bounds Table. We
40296 start with (special_base - sizeof (void*)) and decrease this
40297 address by pointer size to get addresses for other slots. */
40299 {
40303 }
40304 /* If pointer is passed in a memory then its address is used to
40305 access Bounds Table. */
40307 {
40311 }
40312 else
40316 }
40318 /* Expand pass uses this hook to load bounds for function parameter
40319 PTR passed in SLOT in case its bounds are not passed in a register.
40321 If SLOT is a memory, then bounds are loaded as for regular pointer
40322 loaded from memory. PTR may be NULL in case SLOT is a memory.
40323 In such case value of PTR (if required) may be loaded from SLOT.
40325 If SLOT is NULL or a register then SLOT_NO is an integer constant
40326 holding number of the target dependent special slot which should be
40327 used to obtain bounds.
40329 Return loaded bounds. */
40331 static rtx
40333 {
40335 rtx addr;
40337 /* Get address to be used to access Bounds Table. Special slots start
40338 at the location of return address of the current function. */
40341 /* Load pointer value from a memory if we don't have it. */
40343 {
40346 }
40353 }
40355 /* Expand pass uses this hook to store BOUNDS for call argument PTR
40356 passed in SLOT in case BOUNDS are not passed in a register.
40358 If SLOT is a memory, then BOUNDS are stored as for regular pointer
40359 stored in memory. PTR may be NULL in case SLOT is a memory.
40360 In such case value of PTR (if required) may be loaded from SLOT.
40362 If SLOT is NULL or a register then SLOT_NO is an integer constant
40363 holding number of the target dependent special slot which should be
40364 used to store BOUNDS. */
40366 static void
40368 {
40369 rtx addr;
40371 /* Get address to be used to access Bounds Table. Special slots start
40372 at the location of return address of a called function. */
40375 /* Load pointer value from a memory if we don't have it. */
40377 {
40380 }
40389 }
40391 /* Load and return bounds returned by function in SLOT. */
40393 static rtx
40395 {
40396 rtx res;
40403 }
40405 /* Store BOUNDS returned by function into SLOT. */
40407 static void
40409 {
40412 }
40414 /* Returns a function decl for a vectorized version of the builtin function
40415 with builtin function code FN and the result vector type TYPE, or NULL_TREE
40416 if it is not available. */
40418 static tree
40420 tree type_in)
40421 {
40437 {
40440 {
40447 }
40452 {
40455 }
40460 {
40467 }
40473 /* The round insn does not trap on denormals. */
40478 {
40485 }
40491 /* The round insn does not trap on denormals. */
40496 {
40501 }
40507 /* The round insn does not trap on denormals. */
40512 {
40519 }
40525 /* The round insn does not trap on denormals. */
40530 {
40535 }
40542 {
40547 }
40554 {
40559 }
40565 /* The round insn does not trap on denormals. */
40570 {
40577 }
40583 /* The round insn does not trap on denormals. */
40588 {
40593 }
40598 {
40605 }
40610 {
40617 }
40621 /* The round insn does not trap on denormals. */
40626 {
40631 }
40635 /* The round insn does not trap on denormals. */
40640 {
40645 }
40649 /* The round insn does not trap on denormals. */
40654 {
40659 }
40663 /* The round insn does not trap on denormals. */
40668 {
40673 }
40677 /* The round insn does not trap on denormals. */
40682 {
40687 }
40691 /* The round insn does not trap on denormals. */
40696 {
40701 }
40705 /* The round insn does not trap on denormals. */
40710 {
40715 }
40719 /* The round insn does not trap on denormals. */
40724 {
40729 }
40733 /* The round insn does not trap on denormals. */
40738 {
40743 }
40747 /* The round insn does not trap on denormals. */
40752 {
40757 }
40762 {
40767 }
40772 {
40777 }
40782 }
40784 /* Dispatch to a handler for a vectorization library. */
40787 type_in);
40790 }
40792 /* Handler for an SVML-style interface to
40793 a library with vectorized intrinsics. */
40795 static tree
40797 {
40805 /* The SVML is suitable for unsafe math only. */
40818 {
40865 }
40874 {
40877 }
40878 else
40881 /* Convert to uppercase. */
40886 args;
40888 arity++;
40892 else
40895 /* Build a function declaration for the vectorized function. */
40904 }
40906 /* Handler for an ACML-style interface to
40907 a library with vectorized intrinsics. */
40909 static tree
40911 {
40919 /* The ACML is 64bits only and suitable for unsafe math only as
40920 it does not correctly support parts of IEEE with the required
40921 precision such as denormals. */
40935 {
40965 }
40972 args;
40974 arity++;
40978 else
40981 /* Build a function declaration for the vectorized function. */
40990 }
40992 /* Returns a decl of a function that implements gather load with
40993 memory type MEM_VECTYPE and index type INDEX_VECTYPE and SCALE.
40994 Return NULL_TREE if it is not available. */
40996 static tree
40999 {
41015 /* v*gather* insn sign extends index to pointer mode. */
41027 {
41031 else
41037 else
41043 else
41049 else
41055 else
41061 else
41067 else
41073 else
41079 else
41085 else
41091 else
41097 else
41102 }
41105 }
41107 /* Returns a code for a target-specific builtin that implements
41108 reciprocal of the function, or NULL_TREE if not available. */
41110 static tree
41112 {
41119 /* Machine dependent builtins. */
41121 {
41122 /* Vectorized version of sqrt to rsqrt conversion. */
41131 }
41132 else
41133 /* Normal builtins. */
41135 {
41136 /* Sqrt to rsqrt conversion. */
41142 }
41143 }
41144 \f
41145 /* Helper for avx_vpermilps256_operand et al. This is also used by
41146 the expansion functions to turn the parallel back into a mask.
41147 The return value is 0 for no match and the imm8+1 for a match. */
41149 int
41151 {
41159 /* Validate that all of the elements are constants, and not totally
41160 out of range. Copy the data into an integral array to make the
41161 subsequent checks easier. */
41163 {
41173 }
41176 {
41178 /* In the 512-bit DFmode case, we can only move elements within
41179 a 128-bit lane. First fill the second part of the mask,
41180 then fallthru. */
41182 {
41186 }
41188 {
41192 }
41193 /* FALLTHRU */
41196 /* In the 256-bit DFmode case, we can only move elements within
41197 a 128-bit lane. */
41199 {
41203 }
41205 {
41209 }
41213 /* In 512 bit SFmode case, permutation in the upper 256 bits
41214 must mirror the permutation in the lower 256-bits. */
41218 /* FALLTHRU */
41221 /* In 256 bit SFmode case, we have full freedom of
41222 movement within the low 128-bit lane, but the high 128-bit
41223 lane must mirror the exact same pattern. */
41228 /* FALLTHRU */
41232 /* In the 128-bit case, we've full freedom in the placement of
41233 the elements from the source operand. */
41240 }
41242 /* Make sure success has a non-zero value by adding one. */
41244 }
41246 /* Helper for avx_vperm2f128_v4df_operand et al. This is also used by
41247 the expansion functions to turn the parallel back into a mask.
41248 The return value is 0 for no match and the imm8+1 for a match. */
41250 int
41252 {
41260 /* Validate that all of the elements are constants, and not totally
41261 out of range. Copy the data into an integral array to make the
41262 subsequent checks easier. */
41264 {
41274 }
41276 /* Validate that the halves of the permute are halves. */
41284 /* Reconstruct the mask. */
41286 {
41292 }
41294 /* Make sure success has a non-zero value by adding one. */
41296 }
41297 \f
41298 /* Return a register priority for hard reg REGNO. */
41299 static int
41301 {
41302 /* ebp and r13 as the base always wants a displacement, r12 as the
41303 base always wants an index. So discourage their usage in an
41304 address. */
41309 /* New x86-64 int registers result in bigger code size. Discourage
41310 them. */
41313 /* New x86-64 SSE registers result in bigger code size. Discourage
41314 them. */
41317 /* Usage of AX register results in smaller code. Prefer it. */
41321 }
41323 /* Implement TARGET_PREFERRED_RELOAD_CLASS.
41325 Put float CONST_DOUBLE in the constant pool instead of fp regs.
41326 QImode must go into class Q_REGS.
41327 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and
41328 movdf to do mem-to-mem moves through integer regs. */
41330 static reg_class_t
41332 {
41335 /* We're only allowed to return a subclass of CLASS. Many of the
41336 following checks fail for NO_REGS, so eliminate that early. */
41340 /* All classes can load zeros. */
41344 /* Force constants into memory if we are loading a (nonzero) constant into
41345 an MMX, SSE or MASK register. This is because there are no MMX/SSE/MASK
41346 instructions to load from a constant. */
41353 /* Prefer SSE regs only, if we can use them for math. */
41357 /* Floating-point constants need more complex checks. */
41359 {
41360 /* General regs can load everything. */
41364 /* Floats can load 0 and 1 plus some others. Note that we eliminated
41365 zero above. We only want to wind up preferring 80387 registers if
41366 we plan on doing computation with them. */
41369 {
41370 /* Limit class to non-sse. */
41379 }
41382 }
41384 /* Generally when we see PLUS here, it's the function invariant
41385 (plus soft-fp const_int). Which can only be computed into general
41386 regs. */
41390 /* QImode constants are easy to load, but non-constant QImode data
41391 must go into Q_REGS. */
41393 {
41399 }
41402 }
41404 /* Discourage putting floating-point values in SSE registers unless
41405 SSE math is being used, and likewise for the 387 registers. */
41406 static reg_class_t
41408 {
41411 /* Restrict the output reload class to the register bank that we are doing
41412 math on. If we would like not to return a subset of CLASS, reject this
41413 alternative: if reload cannot do this, it will still use its choice. */
41419 {
41424 else
41426 }
41429 }
41431 static reg_class_t
41434 {
41435 /* Double-word spills from general registers to non-offsettable memory
41436 references (zero-extended addresses) require special handling. */
41442 {
41444 ? CODE_FOR_reload_noff_load
41446 /* Add the cost of moving address to a temporary. */
41450 }
41452 /* QImode spills from non-QI registers require
41453 intermediate register on 32bit targets. */
41459 {
41464 else
41470 /* Return Q_REGS if the operand is in memory. */
41473 }
41475 /* This condition handles corner case where an expression involving
41476 pointers gets vectorized. We're trying to use the address of a
41477 stack slot as a vector initializer.
41479 (set (reg:V2DI 74 [ vect_cst_.2 ])
41480 (vec_duplicate:V2DI (reg/f:DI 20 frame)))
41482 Eventually frame gets turned into sp+offset like this:
41484 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41485 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41486 (const_int 392 [0x188]))))
41488 That later gets turned into:
41490 (set (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41491 (vec_duplicate:V2DI (plus:DI (reg/f:DI 7 sp)
41492 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))))
41494 We'll have the following reload recorded:
41496 Reload 0: reload_in (DI) =
41497 (plus:DI (reg/f:DI 7 sp)
41498 (mem/u/c/i:DI (symbol_ref/u:DI ("*.LC0") [flags 0x2]) [0 S8 A64]))
41499 reload_out (V2DI) = (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41500 SSE_REGS, RELOAD_OTHER (opnum = 0), can't combine
41501 reload_in_reg: (plus:DI (reg/f:DI 7 sp) (const_int 392 [0x188]))
41502 reload_out_reg: (reg:V2DI 21 xmm0 [orig:74 vect_cst_.2 ] [74])
41503 reload_reg_rtx: (reg:V2DI 22 xmm1)
41505 Which isn't going to work since SSE instructions can't handle scalar
41506 additions. Returning GENERAL_REGS forces the addition into integer
41507 register and reload can handle subsequent reloads without problems. */
41515 }
41517 /* Implement TARGET_CLASS_LIKELY_SPILLED_P. */
41519 static bool
41521 {
41523 {
41539 }
41542 }
41544 /* If we are copying between general and FP registers, we need a memory
41545 location. The same is true for SSE and MMX registers.
41547 To optimize register_move_cost performance, allow inline variant.
41549 The macro can't work reliably when one of the CLASSES is class containing
41550 registers from multiple units (SSE, MMX, integer). We avoid this by never
41551 combining those units in single alternative in the machine description.
41552 Ensure that this constraint holds to avoid unexpected surprises.
41554 When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not
41555 enforce these sanity checks. */
41560 {
41569 {
41572 }
41577 /* Between mask and general, we have moves no larger than word size. */
41582 /* ??? This is a lie. We do have moves between mmx/general, and for
41583 mmx/sse2. But by saying we need secondary memory we discourage the
41584 register allocator from using the mmx registers unless needed. */
41589 {
41590 /* SSE1 doesn't have any direct moves from other classes. */
41594 /* If the target says that inter-unit moves are more expensive
41595 than moving through memory, then don't generate them. */
41600 /* Between SSE and general, we have moves no larger than word size. */
41603 }
41606 }
41608 bool
41611 {
41613 }
41615 /* Implement the TARGET_CLASS_MAX_NREGS hook.
41617 On the 80386, this is the size of MODE in words,
41618 except in the FP regs, where a single reg is always enough. */
41620 static unsigned char
41622 {
41624 {
41629 else
41631 }
41632 else
41633 {
41636 else
41638 }
41639 }
41641 /* Return true if the registers in CLASS cannot represent the change from
41642 modes FROM to TO. */
41644 bool
41647 {
41651 /* x87 registers can't do subreg at all, as all values are reformatted
41652 to extended precision. */
41657 {
41658 /* Vector registers do not support QI or HImode loads. If we don't
41659 disallow a change to these modes, reload will assume it's ok to
41660 drop the subreg from (subreg:SI (reg:HI 100) 0). This affects
41661 the vec_dupv4hi pattern. */
41664 }
41667 }
41669 /* Return the cost of moving data of mode M between a
41670 register and memory. A value of 2 is the default; this cost is
41671 relative to those in `REGISTER_MOVE_COST'.
41673 This function is used extensively by register_move_cost that is used to
41674 build tables at startup. Make it inline in this case.
41675 When IN is 2, return maximum of in and out move cost.
41677 If moving between registers and memory is more expensive than
41678 between two registers, you should define this macro to express the
41679 relative cost.
41681 Model also increased moving costs of QImode registers in non
41682 Q_REGS classes.
41683 */
41687 {
41690 {
41693 {
41705 }
41709 }
41711 {
41714 {
41726 }
41730 }
41732 {
41735 {
41744 }
41748 }
41750 {
41753 {
41759 else
41764 }
41765 else
41766 {
41771 else
41773 }
41780 /* Compute number of 32bit moves needed. TFmode is moved as XFmode. */
41787 else
41791 }
41792 }
41794 static int
41797 {
41799 }
41802 /* Return the cost of moving data from a register in class CLASS1 to
41803 one in class CLASS2.
41805 It is not required that the cost always equal 2 when FROM is the same as TO;
41806 on some machines it is expensive to move between registers if they are not
41807 general registers. */
41809 static int
41811 reg_class_t class2_i)
41812 {
41816 /* In case we require secondary memory, compute cost of the store followed
41817 by load. In order to avoid bad register allocation choices, we need
41818 for this to be *at least* as high as the symmetric MEMORY_MOVE_COST. */
41821 {
41827 /* In case of copying from general_purpose_register we may emit multiple
41828 stores followed by single load causing memory size mismatch stall.
41829 Count this as arbitrarily high cost of 20. */
41834 /* In the case of FP/MMX moves, the registers actually overlap, and we
41835 have to switch modes in order to treat them differently. */
41841 }
41843 /* Moves between SSE/MMX and integer unit are expensive. */
41847 /* ??? By keeping returned value relatively high, we limit the number
41848 of moves between integer and MMX/SSE registers for all targets.
41849 Additionally, high value prevents problem with x86_modes_tieable_p(),
41850 where integer modes in MMX/SSE registers are not tieable
41851 because of missing QImode and HImode moves to, from or between
41852 MMX/SSE registers. */
41862 }
41864 /* Return TRUE if hard register REGNO can hold a value of machine-mode
41865 MODE. */
41867 bool
41869 {
41870 /* Flags and only flags can only hold CCmode values. */
41881 || (TARGET_AVX512BW
41886 {
41887 /* We implement the move patterns for all vector modes into and
41888 out of SSE registers, even when no operation instructions
41889 are available. */
41891 /* For AVX-512 we allow, regardless of regno:
41892 - XI mode
41893 - any of 512-bit wide vector mode
41894 - any scalar mode. */
41901 /* TODO check for QI/HI scalars. */
41902 /* AVX512VL allows sse regs16+ for 128/256 bit modes. */
41910 /* xmm16-xmm31 are only available for AVX-512. */
41914 /* OImode and AVX modes are available only when AVX is enabled. */
41921 }
41923 {
41924 /* We implement the move patterns for 3DNOW modes even in MMX mode,
41925 so if the register is available at all, then we can move data of
41926 the given mode into or out of it. */
41929 }
41932 {
41933 /* Take care for QImode values - they can be in non-QI regs,
41934 but then they do cause partial register stalls. */
41939 /* LRA checks if the hard register is OK for the given mode.
41940 QImode values can live in non-QI regs, so we allow all
41941 registers here. */
41945 }
41946 /* We handle both integer and floats in the general purpose registers. */
41953 /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go
41954 on to use that value in smaller contexts, this can easily force a
41955 pseudo to be allocated to GENERAL_REGS. Since this is no worse than
41956 supporting DImode, allow it. */
41961 }
41963 /* A subroutine of ix86_modes_tieable_p. Return true if MODE is a
41964 tieable integer mode. */
41966 static bool
41968 {
41970 {
41983 }
41984 }
41986 /* Return true if MODE1 is accessible in a register that can hold MODE2
41987 without copying. That is, all register classes that can hold MODE2
41988 can also hold MODE1. */
41990 bool
41992 {
42000 /* MODE2 being XFmode implies fp stack or general regs, which means we
42001 can tie any smaller floating point modes to it. Note that we do not
42002 tie this with TFmode. */
42006 /* MODE2 being DFmode implies fp stack, general or sse regs, which means
42007 that we can tie it with SFmode. */
42011 /* If MODE2 is only appropriate for an SSE register, then tie with
42012 any other mode acceptable to SSE registers. */
42022 /* If MODE2 is appropriate for an MMX register, then tie
42023 with any other mode acceptable to MMX registers. */
42030 }
42032 /* Return the cost of moving between two registers of mode MODE. */
42034 static int
42036 {
42040 {
42072 }
42074 /* Return the cost of moving between two registers of mode MODE,
42075 assuming that the move will be in pieces of at most UNITS bytes. */
42077 }
42079 /* Compute a (partial) cost for rtx X. Return true if the complete
42080 cost has been computed, and false if subexpressions should be
42081 scanned. In either case, *TOTAL contains the cost result. */
42083 static bool
42086 {
42087 rtx mask;
42094 {
42098 {
42101 }
42113 && !(TARGET_64BIT
42117 /* Use 0 cost for CONST to improve its propagation. */
42120 else
42130 {
42140 }
42142 {
42145 {
42154 }
42155 }
42156 /* Fall back to (MEM (SYMBOL_REF)), since that's where
42157 it'll probably end up. Add a penalty for size. */
42164 /* The zero extensions is often completely free on x86_64, so make
42165 it as cheap as possible. */
42171 else
42183 {
42186 {
42189 }
42192 {
42195 }
42196 }
42197 /* FALLTHRU */
42204 {
42205 /* ??? Should be SSE vector operation cost. */
42206 /* At least for published AMD latencies, this really is the same
42207 as the latency for a simple fpu operation like fabs. */
42208 /* V*QImode is emulated with 1-11 insns. */
42210 {
42213 {
42214 /* For XOP we use vpshab, which requires a broadcast of the
42215 value to the variable shift insn. For constants this
42216 means a V16Q const in mem; even when we can perform the
42217 shift with one insn set the cost to prefer paddb. */
42219 {
42224 }
42226 }
42230 }
42231 else
42233 }
42235 {
42237 {
42240 else
42242 }
42243 else
42244 {
42247 else
42249 }
42250 }
42251 else
42252 {
42257 {
42258 /* Return the cost after shift-and truncation. */
42261 }
42262 else
42264 }
42268 {
42269 rtx sub;
42274 /* ??? SSE scalar/vector cost should be used here. */
42275 /* ??? Bald assumption that fma has the same cost as fmul. */
42279 /* Negate in op0 or op2 is free: FMS, FNMA, FNMS. */
42290 }
42294 {
42295 /* ??? SSE scalar cost should be used here. */
42298 }
42300 {
42303 }
42305 {
42306 /* ??? SSE vector cost should be used here. */
42309 }
42311 {
42312 /* V*QImode is emulated with 7-13 insns. */
42314 {
42321 }
42322 /* V*DImode is emulated with 5-8 insns. */
42324 {
42327 else
42329 }
42330 /* Without sse4.1, we don't have PMULLD; it's emulated with 7
42331 insns, including two PMULUDQ. */
42334 else
42337 }
42338 else
42339 {
42344 {
42347 nbits++;
42348 }
42349 else
42350 /* This is arbitrary. */
42353 /* Compute costs correctly for widening multiplication. */
42357 {
42364 {
42368 else
42370 }
42374 }
42382 }
42389 /* ??? SSE cost should be used here. */
42394 /* ??? SSE vector cost should be used here. */
42396 else
42403 {
42408 {
42411 {
42419 }
42420 }
42423 {
42426 {
42432 }
42433 }
42435 {
42443 }
42444 }
42445 /* FALLTHRU */
42449 {
42450 /* ??? SSE cost should be used here. */
42453 }
42455 {
42458 }
42460 {
42461 /* ??? SSE vector cost should be used here. */
42464 }
42465 /* FALLTHRU */
42472 {
42479 }
42480 /* FALLTHRU */
42484 {
42485 /* ??? SSE cost should be used here. */
42488 }
42490 {
42493 }
42495 {
42496 /* ??? SSE vector cost should be used here. */
42499 }
42500 /* FALLTHRU */
42504 {
42505 /* ??? Should be SSE vector operation cost. */
42506 /* At least for published AMD latencies, this really is the same
42507 as the latency for a simple fpu operation like fabs. */
42509 }
42512 else
42521 {
42522 /* This kind of construct is implemented using test[bwl].
42523 Treat it as if we had an AND. */
42528 }
42530 /* The embedded comparison operand is completely free. */
42544 /* ??? SSE cost should be used here. */
42549 /* ??? SSE vector cost should be used here. */
42555 /* ??? SSE cost should be used here. */
42560 /* ??? SSE vector cost should be used here. */
42572 /* ??? Assume all of these vector manipulation patterns are
42573 recognizable. In which case they all pretty much have the
42574 same cost. */
42579 /* This is masked instruction, assume the same cost,
42580 as nonmasked variant. */
42583 else
42589 }
42590 }
42592 #if TARGET_MACHO
42596 /* Given a symbol name and its associated stub, write out the
42597 definition of the stub. */
42599 void
42601 {
42606 /* For 64-bit we shouldn't get here. */
42609 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
42626 else
42633 {
42635 }
42637 {
42638 /* PIC stub. */
42639 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42645 }
42646 else
42649 /* The AT&T-style ("self-modifying") stub is not lazily bound, thus
42650 it needs no stub-binding-helper. */
42657 {
42660 }
42661 else
42666 /* N.B. Keep the correspondence of these
42667 'symbol_ptr/symbol_ptr2/symbol_ptr3' sections consistent with the
42668 old-pic/new-pic/non-pic stubs; altering this will break
42669 compatibility with existing dylibs. */
42671 {
42672 /* 25-byte PIC stub using "CALL get_pc_thunk". */
42674 }
42675 else
42676 /* 16-byte -mdynamic-no-pic stub. */
42682 }
42685 /* Order the registers for register allocator. */
42687 void
42689 {
42693 /* First allocate the local general purpose registers. */
42698 /* Global general purpose registers. */
42703 /* x87 registers come first in case we are doing FP math
42704 using them. */
42709 /* SSE registers. */
42715 /* Extended REX SSE registers. */
42719 /* Mask register. */
42723 /* MPX bound registers. */
42727 /* x87 registers. */
42735 /* Initialize the rest of array as we do not allocate some registers
42736 at all. */
42739 }
42741 /* Handle a "callee_pop_aggregate_return" attribute; arguments as
42742 in struct attribute_spec handler. */
42743 static tree
42745 tree args,
42748 {
42753 {
42755 name);
42758 }
42760 {
42762 name);
42765 }
42767 {
42768 tree cst;
42772 {
42775 name);
42777 }
42780 {
42783 name);
42785 }
42788 }
42791 }
42793 /* Handle a "ms_abi" or "sysv" attribute; arguments as in
42794 struct attribute_spec.handler. */
42795 static tree
42798 {
42803 {
42805 name);
42808 }
42810 /* Can combine regparm with all attributes but fastcall. */
42812 {
42814 {
42816 }
42819 }
42821 {
42823 {
42825 }
42828 }
42831 }
42833 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
42834 struct attribute_spec.handler. */
42835 static tree
42838 {
42841 {
42844 }
42845 else
42849 {
42851 name);
42853 }
42859 {
42861 name);
42863 }
42866 }
42868 static tree
42871 {
42873 {
42875 name);
42877 }
42879 }
42881 static bool
42883 {
42887 }
42889 /* Returns an expression indicating where the this parameter is
42890 located on entry to the FUNCTION. */
42892 static rtx
42894 {
42900 {
42905 else
42908 }
42913 {
42920 {
42925 }
42926 else
42927 {
42930 {
42936 }
42937 }
42939 }
42943 }
42945 /* Determine whether x86_output_mi_thunk can succeed. */
42947 static bool
42949 const_tree function)
42950 {
42951 /* 64-bit can handle anything. */
42955 /* For 32-bit, everything's fine if we have one free register. */
42959 /* Need a free register for vcall_offset. */
42963 /* Need a free register for GOT references. */
42967 /* Otherwise ok. */
42969 }
42971 /* Output the assembler code for a thunk function. THUNK_DECL is the
42972 declaration for the thunk function itself, FUNCTION is the decl for
42973 the target function. DELTA is an immediate constant offset to be
42974 added to THIS. If VCALL_OFFSET is nonzero, the word at
42975 *(*this + vcall_offset) should be added to THIS. */
42977 static void
42980 {
42988 else
42989 {
42995 else
42997 }
43001 /* If VCALL_OFFSET, we'll need THIS in a register. Might as well
43002 pull it in now and let DELTA benefit. */
43006 {
43007 /* Put the this parameter into %eax. */
43010 }
43011 else
43014 /* Adjust the this parameter by a fixed constant. */
43016 {
43021 {
43023 {
43027 }
43028 }
43031 }
43033 /* Adjust the this parameter by a value stored in the vtable. */
43035 {
43045 /* Adjust the this parameter. */
43049 {
43053 }
43060 vcall_mem));
43061 else
43063 }
43065 /* If necessary, drop THIS back to its stack slot. */
43071 {
43074 ;
43075 else
43076 {
43080 }
43081 }
43082 else
43083 {
43085 ;
43086 #if TARGET_MACHO
43088 {
43091 }
43093 else
43094 {
43102 }
43103 }
43105 /* Our sibling call patterns do not allow memories, because we have no
43106 predicate that can distinguish between frame and non-frame memory.
43107 For our purposes here, we can get away with (ab)using a jump pattern,
43108 because we're going to do no optimization. */
43110 {
43112 {
43118 }
43119 else
43121 }
43122 else
43123 {
43125 {
43126 // CM_LARGE_PIC always uses pseudo PIC register which is
43127 // uninitialized. Since FUNCTION is local and calling it
43128 // doesn't go through PLT, we use scratch register %r11 as
43129 // PIC register and initialize it here.
43134 }
43137 {
43143 }
43149 }
43152 /* Emit just enough of rest_of_compilation to get the insns emitted.
43153 Note that use_thunk calls assemble_start_function et al. */
43159 }
43161 static void
43163 {
43167 #if TARGET_MACHO
43169 #endif
43176 }
43178 int
43180 {
43181 machine_mode mode;
43192 }
43194 /* Print call to TARGET to FILE. */
43196 static void
43198 {
43201 else
43203 }
43205 /* Output assembler code to FILE to increment profiler label # LABELNO
43206 for profiling a function entry. */
43207 void
43209 {
43213 {
43214 #ifndef NO_PROFILE_COUNTERS
43216 #endif
43220 else
43222 }
43224 {
43225 #ifndef NO_PROFILE_COUNTERS
43228 #endif
43230 }
43231 else
43232 {
43233 #ifndef NO_PROFILE_COUNTERS
43236 #endif
43238 }
43241 {
43245 }
43246 }
43248 /* We don't have exact information about the insn sizes, but we may assume
43249 quite safely that we are informed about all 1 byte insns and memory
43250 address sizes. This is enough to eliminate unnecessary padding in
43251 99% of cases. */
43253 static int
43255 {
43261 /* Discard alignments we've emit and jump instructions. */
43266 /* Important case - calls are always 5 bytes.
43267 It is common to have many calls in the row. */
43276 /* For normal instructions we rely on get_attr_length being exact,
43277 with a few exceptions. */
43279 {
43283 {
43293 /* Otherwise trust get_attr_length. */
43295 }
43300 }
43303 else
43305 }
43307 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43309 /* AMD K8 core mispredicts jumps when there are more than 3 jumps in 16 byte
43310 window. */
43312 static void
43314 {
43319 /* Look for all minimal intervals of instructions containing 4 jumps.
43320 The intervals are bounded by START and INSN. NBYTES is the total
43321 size of instructions in the interval including INSN and not including
43322 START. When the NBYTES is smaller than 16 bytes, it is possible
43323 that the end of START and INSN ends up in the same 16byte page.
43325 The smallest offset in the page INSN can start is the case where START
43326 ends on the offset 0. Offset of INSN is then NBYTES - sizeof (INSN).
43327 We add p2align to 16byte window with maxskip 15 - NBYTES + sizeof (INSN).
43329 Don't consider asm goto as jump, while it can contain a jump, it doesn't
43330 have to, control transfer to label(s) can be performed through other
43331 means, and also we estimate minimum length of all asm stmts as 0. */
43333 {
43337 {
43343 /* If align > 3, only up to 16 - max_skip - 1 bytes can be
43344 already in the current 16 byte page, because otherwise
43345 ASM_OUTPUT_MAX_SKIP_ALIGN could skip max_skip or fewer
43346 bytes to reach 16 byte boundary. */
43354 {
43356 {
43361 else
43364 }
43365 }
43367 }
43376 njumps++;
43377 else
43381 {
43386 else
43389 }
43396 {
43403 }
43404 }
43405 }
43406 #endif
43408 /* AMD Athlon works faster
43409 when RET is not destination of conditional jump or directly preceded
43410 by other jump instruction. We avoid the penalty by inserting NOP just
43411 before the RET instructions in such cases. */
43412 static void
43414 {
43415 edge e;
43416 edge_iterator ei;
43419 {
43432 {
43433 edge e;
43434 edge_iterator ei;
43439 {
43442 }
43443 }
43445 {
43451 /* Empty functions get branch mispredict even when
43452 the jump destination is not visible to us. */
43455 }
43457 {
43460 }
43461 }
43462 }
43464 /* Count the minimum number of instructions in BB. Return 4 if the
43465 number of instructions >= 4. */
43467 static int
43469 {
43473 /* Count number of instructions in this block. Return 4 if the number
43474 of instructions >= 4. */
43476 {
43477 /* Only happen in exit blocks. */
43485 {
43486 insn_count++;
43489 }
43490 }
43493 }
43496 /* Count the minimum number of instructions in code path in BB.
43497 Return 4 if the number of instructions >= 4. */
43499 static int
43501 {
43502 edge e;
43503 edge_iterator ei;
43506 /* Only bother counting instructions along paths with no
43507 more than 2 basic blocks between entry and exit. Given
43508 that BB has an edge to exit, determine if a predecessor
43509 of BB has an edge from entry. If so, compute the number
43510 of instructions in the predecessor block. If there
43511 happen to be multiple such blocks, compute the minimum. */
43514 {
43515 edge prev_e;
43516 edge_iterator prev_ei;
43519 {
43522 }
43524 {
43526 {
43531 }
43532 }
43533 }
43539 }
43541 /* Pad short function to 4 instructions. */
43543 static void
43545 {
43546 edge e;
43547 edge_iterator ei;
43550 {
43553 {
43556 /* Pad short function. */
43558 {
43561 /* Find epilogue. */
43570 /* Two NOPs count as one instruction. */
43573 }
43574 }
43575 }
43576 }
43578 /* Fix up a Windows system unwinder issue. If an EH region falls through into
43579 the epilogue, the Windows system unwinder will apply epilogue logic and
43580 produce incorrect offsets. This can be avoided by adding a nop between
43581 the last insn that can throw and the first insn of the epilogue. */
43583 static void
43585 {
43586 edge e;
43587 edge_iterator ei;
43590 {
43593 /* Find the beginning of the epilogue. */
43600 /* We only care about preceding insns that can throw. */
43605 /* Do not separate calls from their debug information. */
43611 else
43615 }
43616 }
43618 /* Implement machine specific optimizations. We implement padding of returns
43619 for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */
43620 static void
43622 {
43623 /* We are freeing block_for_insn in the toplev to keep compatibility
43624 with old MDEP_REORGS that are not CFG based. Recompute it now. */
43631 {
43636 #ifdef ASM_OUTPUT_MAX_SKIP_PAD
43639 #endif
43640 }
43641 }
43643 /* Return nonzero when QImode register that must be represented via REX prefix
43644 is used. */
43645 bool
43647 {
43655 }
43657 /* Return true when INSN mentions register that must be encoded using REX
43658 prefix. */
43659 bool
43661 {
43664 {
43669 }
43671 }
43673 /* If profitable, negate (without causing overflow) integer constant
43674 of mode MODE at location LOC. Return true in this case. */
43675 bool
43677 {
43678 HOST_WIDE_INT val;
43684 {
43686 /* DImode x86_64 constants must fit in 32 bits. */
43699 }
43701 /* Avoid overflows. */
43707 /* Make things pretty and `subl $4,%eax' rather than `addl $-4,%eax'.
43708 Exceptions: -128 encodes smaller than 128, so swap sign and op. */
43711 {
43714 }
43717 }
43719 /* Generate an unsigned DImode/SImode to FP conversion. This is the same code
43720 optabs would emit if we didn't have TFmode patterns. */
43722 void
43724 {
43759 }
43760 \f
43766 /* Get a vector mode of the same size as the original but with elements
43767 twice as wide. This is only guaranteed to apply to integral vectors. */
43771 {
43772 /* ??? Rely on the ordering that genmodes.c gives to vectors. */
43777 }
43779 /* A subroutine of ix86_expand_vector_init_duplicate. Tries to
43780 fill target with val via vec_duplicate. */
43782 static bool
43784 {
43787 rtx dup;
43789 /* First attempt to recognize VAL as-is. */
43793 {
43795 /* If that fails, force VAL into a register. */
43806 }
43808 }
43810 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43811 with all elements equal to VAR. Return true if successful. */
43813 static bool
43816 {
43820 {
43825 /* FALLTHRU */
43845 {
43846 rtx x;
43853 }
43866 {
43870 permute:
43878 /* Extend to SImode using a paradoxical SUBREG. */
43882 /* Insert the SImode value as low element of a V4SImode vector. */
43891 }
43902 widen:
43903 /* Replicate the value once into the next wider mode and recurse. */
43904 {
43906 rtx x;
43923 }
43929 else
43930 {
43939 }
43946 else
43947 {
43956 }
43961 }
43962 }
43964 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
43965 whose ONE_VAR element is VAR, and other elements are zero. Return true
43966 if successful. */
43968 static bool
43971 {
43972 machine_mode vsimode;
43973 rtx new_target;
43978 {
43980 /* For SSE4.1, we normally use vector set. But if the second
43981 element is zero and inter-unit moves are OK, we use movq
43982 instead. */
43984 && !(TARGET_INTER_UNIT_MOVES_TO_VEC
44006 /* Use ix86_expand_vector_set in 64bit mode only. */
44011 }
44014 {
44019 }
44022 {
44027 /* FALLTHRU */
44042 else
44049 {
44050 /* We need to shuffle the value to the correct position, so
44051 create a new pseudo to store the intermediate result. */
44053 /* With SSE2, we can use the integer shuffle insns. */
44055 {
44057 const1_rtx,
44064 }
44066 /* Otherwise convert the intermediate result to V4SFmode and
44067 use the SSE1 shuffle instructions. */
44069 {
44072 }
44073 else
44077 const1_rtx,
44086 }
44101 widen:
44105 /* Zero extend the variable element to SImode and recurse. */
44118 }
44119 }
44121 /* A subroutine of ix86_expand_vector_init. Store into TARGET a vector
44122 consisting of the values in VALS. It is known that all elements
44123 except ONE_VAR are constants. Return true if successful. */
44125 static bool
44128 {
44130 machine_mode wmode;
44138 {
44143 /* For the two element vectors, it's just as easy to use
44144 the general case. */
44148 /* Use ix86_expand_vector_set in 64bit mode only. */
44170 widen:
44171 /* There's no way to set one QImode entry easily. Combine
44172 the variable value with its adjacent constant value, and
44173 promote to an HImode set. */
44176 {
44181 }
44182 else
44183 {
44186 }
44200 }
44205 }
44207 /* A subroutine of ix86_expand_vector_init_general. Use vector
44208 concatenate to handle the most general case: all values variable,
44209 and none identical. */
44211 static void
44214 {
44217 rtvec v;
44221 {
44224 {
44269 }
44281 {
44296 }
44301 {
44320 }
44325 {
44338 }
44341 half:
44342 /* FIXME: We process inputs backward to help RA. PR 36222. */
44346 {
44351 }
44355 {
44359 {
44363 }
44366 {
44370 }
44373 }
44375 {
44378 {
44382 }
44385 }
44386 else
44392 }
44393 }
44395 /* A subroutine of ix86_expand_vector_init_general. Use vector
44396 interleave to handle the most general case: all values variable,
44397 and none identical. */
44399 static void
44402 {
44411 {
44432 }
44435 {
44436 /* Extend the odd elment to SImode using a paradoxical SUBREG. */
44440 /* Insert the SImode value as low element of V4SImode vector. */
44444 op0),
44446 const1_rtx);
44449 /* Cast the V4SImode vector back to a vector in orignal mode. */
44453 /* Load even elements into the second position. */
44457 const1_rtx));
44459 /* Cast vector to FIRST_IMODE vector. */
44462 }
44464 /* Interleave low FIRST_IMODE vectors. */
44466 {
44470 /* Cast FIRST_IMODE vector to SECOND_IMODE vector. */
44473 }
44475 /* Interleave low SECOND_IMODE vectors. */
44477 {
44480 {
44485 /* Cast the SECOND_IMODE vector to the THIRD_IMODE
44486 vector. */
44489 }
44492 /* FALLTHRU */
44499 /* Cast the SECOND_IMODE vector back to a vector on original
44500 mode. */
44506 }
44507 }
44509 /* A subroutine of ix86_expand_vector_init. Handle the most general case:
44510 all values variable, and none identical. */
44512 static void
44515 {
44522 {
44527 /* FALLTHRU */
44555 half:
44578 quarter:
44604 /* FALLTHRU */
44610 /* Don't use ix86_expand_vector_init_interleave if we can't
44611 move from GPR to SSE register directly. */
44627 }
44629 {
44631 machine_mode inner_mode;
44641 {
44645 {
44651 else
44652 {
44657 }
44658 }
44661 }
44666 {
44672 }
44674 {
44680 }
44681 else
44683 }
44684 }
44686 /* Initialize vector TARGET via VALS. Suppress the use of MMX
44687 instructions unless MMX_OK is true. */
44689 void
44691 {
44698 rtx x;
44701 {
44711 }
44713 /* Constants are best loaded from the constant pool. */
44715 {
44718 }
44720 /* If all values are identical, broadcast the value. */
44726 /* Values where only one field is non-constant are best loaded from
44727 the pool and overwritten via move later. */
44729 {
44733 one_var))
44738 }
44741 }
44743 void
44745 {
44748 machine_mode half_mode;
44750 rtx tmp;
44752 = {
44759 };
44761 = {
44768 };
44774 {
44778 {
44783 else
44787 }
44799 else
44805 {
44808 /* For the two element vectors, we implement a VEC_CONCAT with
44809 the extraction of the other element. */
44816 else
44821 }
44830 {
44836 /* tmp = target = A B C D */
44838 /* target = A A B B */
44840 /* target = X A B B */
44842 /* target = A X C D */
44849 /* tmp = target = A B C D */
44851 /* tmp = X B C D */
44853 /* target = A B X D */
44860 /* tmp = target = A B C D */
44862 /* tmp = X B C D */
44864 /* target = A B X D */
44872 }
44880 /* Element 0 handled by vec_merge below. */
44882 {
44885 }
44888 {
44889 /* With SSE2, use integer shuffles to swap element 0 and ELT,
44890 store into element 0, then shuffle them back. */
44907 }
44908 else
44909 {
44910 /* For SSE1, we have to reuse the V4SF code. */
44914 }
44967 half:
44968 /* Compute offset. */
44974 /* Extract the half. */
44978 /* Put val in tmp at elt. */
44981 /* Put it back. */
44987 {
44990 }
44995 {
44998 }
45003 {
45006 }
45011 {
45014 }
45019 {
45022 }
45027 {
45030 }
45035 }
45038 {
45044 }
45046 {
45050 }
45051 else
45052 {
45061 }
45062 }
45064 void
45066 {
45070 rtx tmp;
45073 {
45078 /* FALLTHRU */
45091 {
45111 }
45123 {
45125 {
45145 }
45149 }
45150 else
45151 {
45152 /* For SSE1, we have to reuse the V4SF code. */
45156 }
45172 {
45176 else
45180 }
45185 {
45189 else
45193 }
45198 {
45202 else
45206 }
45211 {
45215 else
45219 }
45224 {
45228 else
45232 }
45237 {
45241 else
45245 }
45250 {
45254 else
45258 }
45263 {
45267 else
45271 }
45278 else
45287 else
45296 else
45305 else
45311 /* ??? Could extract the appropriate HImode element and shift. */
45314 }
45317 {
45321 /* Let the rtl optimizers know about the zero extension performed. */
45323 {
45326 }
45329 }
45330 else
45331 {
45338 }
45339 }
45341 /* Generate code to copy vector bits i / 2 ... i - 1 from vector SRC
45342 to bits 0 ... i / 2 - 1 of vector DEST, which has the same mode.
45343 The upper bits of DEST are undefined, though they shouldn't cause
45344 exceptions (some bits from src or all zeros are ok). */
45346 static void
45348 {
45351 {
45355 else
45373 else
45380 else
45388 {
45393 const1_rtx);
45394 }
45395 else
45396 {
45400 }
45422 else
45444 }
45448 }
45450 /* Expand a vector reduction. FN is the binary pattern to reduce;
45451 DEST is the destination; IN is the input vector. */
45453 void
45455 {
45460 /* SSE4 has a special instruction for V8HImode UMIN reduction. */
45464 {
45467 }
45472 {
45477 else
45481 }
45482 }
45483 \f
45484 /* Target hook for scalar_mode_supported_p. */
45485 static bool
45487 {
45492 else
45494 }
45496 /* Implements target hook vector_mode_supported_p. */
45497 static bool
45499 {
45513 }
45515 /* Implement target hook libgcc_floating_mode_supported_p. */
45516 static bool
45518 {
45520 {
45527 #ifdef IX86_NO_LIBGCC_TFMODE
45529 #elif defined IX86_MAYBE_NO_LIBGCC_TFMODE
45531 #else
45533 #endif
45537 }
45538 }
45540 /* Target hook for c_mode_for_suffix. */
45541 static machine_mode
45543 {
45550 }
45552 /* Worker function for TARGET_MD_ASM_ADJUST.
45554 We do this in the new i386 backend to maintain source compatibility
45555 with the old cc0-based compiler. */
45561 {
45569 }
45571 /* Implements target vector targetm.asm.encode_section_info. */
45573 static void ATTRIBUTE_UNUSED
45575 {
45580 }
45582 /* Worker function for REVERSE_CONDITION. */
45584 enum rtx_code
45586 {
45590 }
45592 /* Output code to perform an x87 FP register move, from OPERANDS[1]
45593 to OPERANDS[0]. */
45597 {
45599 {
45602 {
45606 }
45610 }
45612 {
45616 else
45617 {
45618 /* There is no non-popping store to memory for XFmode.
45619 So if we need one, follow the store with a load. */
45622 else
45624 }
45625 }
45626 else
45628 }
45630 /* Output code to perform a conditional jump to LABEL, if C2 flag in
45631 FP status register is set. */
45633 void
45635 {
45637 rtx temp;
45642 {
45647 }
45648 else
45649 {
45654 }
45658 pc_rtx);
45663 }
45665 /* Output code to perform a log1p XFmode calculation. */
45668 {
45674 rtx test;
45680 XFmode));
45694 }
45696 /* Emit code for round calculation. */
45698 {
45705 rtx insn;
45710 {
45722 }
45725 {
45746 }
45754 /* round(a) = sgn(a) * floor(fabs(a) + 0.5) */
45756 /* scratch = fxam(op1) */
45759 UNSPEC_FXAM)));
45760 /* e1 = fabs(op1) */
45763 /* e2 = e1 + 0.5 */
45767 /* res = floor(e2) */
45769 {
45773 }
45774 else
45778 {
45781 {
45788 UNSPEC_TRUNC_NOOP)));
45789 }
45805 }
45807 /* flags = signbit(a) */
45810 /* if (flags) then res = -res */
45814 pc_rtx);
45825 }
45827 /* Output code to perform a Newton-Rhapson approximation of a single precision
45828 floating point divide [http://en.wikipedia.org/wiki/N-th_root_algorithm]. */
45831 {
45839 /* a / b = a * ((rcp(b) + rcp(b)) - (b * rcp(b) * rcp (b))) */
45843 /* x0 = rcp(b) estimate */
45846 UNSPEC_RCP14)));
45847 else
45849 UNSPEC_RCP)));
45851 /* e0 = x0 * b */
45854 /* e0 = x0 * e0 */
45857 /* e1 = x0 + x0 */
45860 /* x1 = e1 - e0 */
45863 /* res = a * x1 */
45865 }
45867 /* Output code to perform a Newton-Rhapson approximation of a
45868 single precision floating point [reciprocal] square root. */
45872 {
45874 REAL_VALUE_TYPE r;
45891 {
45894 /* There is no 512-bit rsqrt. There is however rsqrt14. */
45897 }
45899 /* sqrt(a) = -0.5 * a * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0)
45900 rsqrt(a) = -0.5 * rsqrtss(a) * (a * rsqrtss(a) * rsqrtss(a) - 3.0) */
45904 /* x0 = rsqrt(a) estimate */
45906 unspec)));
45908 /* If (a == 0.0) Filter out infinity to prevent NaN for sqrt(0.0). */
45910 {
45918 /* Handle masked compare. */
45920 {
45922 /* Imm value 0x4 corresponds to not-equal comparison. */
45925 }
45926 else
45927 {
45931 }
45932 }
45934 /* e0 = x0 * a */
45936 /* e1 = e0 * x0 */
45939 /* e2 = e1 - 3. */
45945 /* e3 = -.5 * x0 */
45947 else
45948 /* e3 = -.5 * e0 */
45950 /* ret = e2 * e3 */
45952 }
45954 #ifdef TARGET_SOLARIS
45955 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */
45957 static void
45959 tree decl)
45960 {
45961 /* With Binutils 2.15, the "@unwind" marker must be specified on
45962 every occurrence of the ".eh_frame" section, not just the first
45963 one. */
45966 {
45970 }
45972 #ifndef USE_GAS
45974 {
45977 }
45978 #endif
45981 }
45984 /* Return the mangling of TYPE if it is an extended fundamental type. */
45988 {
45996 {
45998 /* __float128 is "g". */
46001 /* "long double" or __float80 is "e". */
46005 }
46006 }
46008 /* For 32-bit code we can save PIC register setup by using
46009 __stack_chk_fail_local hidden function instead of calling
46010 __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC
46011 register, so it is better to call __stack_chk_fail directly. */
46013 static tree ATTRIBUTE_UNUSED
46015 {
46016 return TARGET_64BIT
46019 }
46021 /* Select a format to encode pointers in exception handling data. CODE
46022 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is
46023 true if the symbol may be affected by dynamic relocations.
46025 ??? All x86 object file formats are capable of representing this.
46026 After all, the relocation needed is the same as for the call insn.
46027 Whether or not a particular assembler allows us to enter such, I
46028 guess we'll have to see. */
46029 int
46031 {
46033 {
46040 }
46045 }
46046 \f
46047 /* Expand copysign from SIGN to the positive value ABS_VALUE
46048 storing in RESULT. If MASK is non-null, it shall be a mask to mask out
46049 the sign-bit. */
46050 static void
46052 {
46056 {
46057 machine_mode vmode;
46063 else
46068 {
46069 /* We need to generate a scalar mode mask in this case. */
46074 }
46075 }
46076 else
46080 }
46082 /* Expand fabs (OP0) and return a new rtx that holds the result. The
46083 mask for masking out the sign-bit is stored in *SMASK, if that is
46084 non-null. */
46085 static rtx
46087 {
46096 else
46100 {
46101 /* We need to generate a scalar mode mask in this case. */
46106 }
46113 }
46115 /* Expands a comparison of OP0 with OP1 using comparison code CODE,
46116 swapping the operands if SWAP_OPERANDS is true. The expanded
46117 code is a forward jump to a newly created label in case the
46118 comparison is true. The generated label rtx is returned. */
46122 {
46125 rtx tmp;
46140 }
46142 /* Expand a mask generating SSE comparison instruction comparing OP0 with OP1
46143 using comparison code CODE. Operands are swapped for the comparison if
46144 SWAP_OPERANDS is true. Returns a rtx for the generated mask. */
46145 static rtx
46148 {
46161 }
46163 /* Generate and return a rtx of mode MODE for 2**n where n is the number
46164 of bits of the mantissa of MODE, which must be one of DFmode or SFmode. */
46165 static rtx
46167 {
46168 REAL_VALUE_TYPE TWO52r;
46169 rtx TWO52;
46176 }
46178 /* Expand SSE sequence for computing lround from OP1 storing
46179 into OP0. */
46180 void
46182 {
46183 /* C code for the stuff we're doing below:
46184 tmp = op1 + copysign (nextafter (0.5, 0.0), op1)
46185 return (long)tmp;
46186 */
46190 rtx adj;
46192 /* load nextafter (0.5, 0.0) */
46197 /* adj = copysign (0.5, op1) */
46201 /* adj = op1 + adj */
46204 /* op0 = (imode)adj */
46206 }
46208 /* Expand SSE2 sequence for computing lround from OPERAND1 storing
46209 into OPERAND0. */
46210 void
46212 {
46213 /* C code for the stuff we're doing below (for do_floor):
46214 xi = (long)op1;
46215 xi -= (double)xi > op1 ? 1 : 0;
46216 return xi;
46217 */
46223 /* reg = (long)op1 */
46227 /* freg = (double)reg */
46231 /* ireg = (freg > op1) ? ireg - 1 : ireg */
46242 }
46244 /* Expand rint (IEEE round to nearest) rounding OPERAND1 and storing the
46245 result in OPERAND0. */
46246 void
46248 {
46249 /* C code for the stuff we're doing below:
46250 xa = fabs (operand1);
46251 if (!isless (xa, 2**52))
46252 return operand1;
46253 xa = xa + 2**52 - 2**52;
46254 return copysign (xa, operand1);
46255 */
46263 /* xa = abs (operand1) */
46266 /* if (!isless (xa, TWO52)) goto label; */
46279 }
46281 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46282 into OPERAND0. */
46283 void
46285 {
46286 /* C code for the stuff we expand below.
46287 double xa = fabs (x), x2;
46288 if (!isless (xa, TWO52))
46289 return x;
46290 xa = xa + TWO52 - TWO52;
46291 x2 = copysign (xa, x);
46292 Compensate. Floor:
46293 if (x2 > x)
46294 x2 -= 1;
46295 Compensate. Ceil:
46296 if (x2 < x)
46297 x2 -= -1;
46298 return x2;
46299 */
46306 /* Temporary for holding the result, initialized to the input
46307 operand to ease control flow. */
46311 /* xa = abs (operand1) */
46314 /* if (!isless (xa, TWO52)) goto label; */
46317 /* xa = xa + TWO52 - TWO52; */
46321 /* xa = copysign (xa, operand1) */
46324 /* generate 1.0 or -1.0 */
46329 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46332 /* We always need to subtract here to preserve signed zero. */
46341 }
46343 /* Expand SSE2 sequence for computing floor or ceil from OPERAND1 storing
46344 into OPERAND0. */
46345 void
46347 {
46348 /* C code for the stuff we expand below.
46349 double xa = fabs (x), x2;
46350 if (!isless (xa, TWO52))
46351 return x;
46352 x2 = (double)(long)x;
46353 Compensate. Floor:
46354 if (x2 > x)
46355 x2 -= 1;
46356 Compensate. Ceil:
46357 if (x2 < x)
46358 x2 += 1;
46359 if (HONOR_SIGNED_ZEROS (mode))
46360 return copysign (x2, x);
46361 return x2;
46362 */
46369 /* Temporary for holding the result, initialized to the input
46370 operand to ease control flow. */
46374 /* xa = abs (operand1) */
46377 /* if (!isless (xa, TWO52)) goto label; */
46380 /* xa = (double)(long)x */
46385 /* generate 1.0 */
46388 /* Compensate: xa = xa - (xa > operand1 ? 1 : 0) */
46402 }
46404 /* Expand SSE sequence for computing round from OPERAND1 storing
46405 into OPERAND0. Sequence that works without relying on DImode truncation
46406 via cvttsd2siq that is only available on 64bit targets. */
46407 void
46409 {
46410 /* C code for the stuff we expand below.
46411 double xa = fabs (x), xa2, x2;
46412 if (!isless (xa, TWO52))
46413 return x;
46414 Using the absolute value and copying back sign makes
46415 -0.0 -> -0.0 correct.
46416 xa2 = xa + TWO52 - TWO52;
46417 Compensate.
46418 dxa = xa2 - xa;
46419 if (dxa <= -0.5)
46420 xa2 += 1;
46421 else if (dxa > 0.5)
46422 xa2 -= 1;
46423 x2 = copysign (xa2, x);
46424 return x2;
46425 */
46432 /* Temporary for holding the result, initialized to the input
46433 operand to ease control flow. */
46437 /* xa = abs (operand1) */
46440 /* if (!isless (xa, TWO52)) goto label; */
46443 /* xa2 = xa + TWO52 - TWO52; */
46447 /* dxa = xa2 - xa; */
46450 /* generate 0.5, 1.0 and -0.5 */
46456 /* Compensate. */
46458 /* xa2 = xa2 - (dxa > 0.5 ? 1 : 0) */
46462 /* xa2 = xa2 + (dxa <= -0.5 ? 1 : 0) */
46467 /* res = copysign (xa2, operand1) */
46474 }
46476 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46477 into OPERAND0. */
46478 void
46480 {
46481 /* C code for SSE variant we expand below.
46482 double xa = fabs (x), x2;
46483 if (!isless (xa, TWO52))
46484 return x;
46485 x2 = (double)(long)x;
46486 if (HONOR_SIGNED_ZEROS (mode))
46487 return copysign (x2, x);
46488 return x2;
46489 */
46496 /* Temporary for holding the result, initialized to the input
46497 operand to ease control flow. */
46501 /* xa = abs (operand1) */
46504 /* if (!isless (xa, TWO52)) goto label; */
46507 /* x = (double)(long)x */
46519 }
46521 /* Expand SSE sequence for computing trunc from OPERAND1 storing
46522 into OPERAND0. */
46523 void
46525 {
46530 /* C code for SSE variant we expand below.
46531 double xa = fabs (x), x2;
46532 if (!isless (xa, TWO52))
46533 return x;
46534 xa2 = xa + TWO52 - TWO52;
46535 Compensate:
46536 if (xa2 > xa)
46537 xa2 -= 1.0;
46538 x2 = copysign (xa2, x);
46539 return x2;
46540 */
46544 /* Temporary for holding the result, initialized to the input
46545 operand to ease control flow. */
46549 /* xa = abs (operand1) */
46552 /* if (!isless (xa, TWO52)) goto label; */
46555 /* res = xa + TWO52 - TWO52; */
46560 /* generate 1.0 */
46563 /* Compensate: res = xa2 - (res > xa ? 1 : 0) */
46570 /* res = copysign (res, operand1) */
46577 }
46579 /* Expand SSE sequence for computing round from OPERAND1 storing
46580 into OPERAND0. */
46581 void
46583 {
46584 /* C code for the stuff we're doing below:
46585 double xa = fabs (x);
46586 if (!isless (xa, TWO52))
46587 return x;
46588 xa = (double)(long)(xa + nextafter (0.5, 0.0));
46589 return copysign (xa, x);
46590 */
46597 /* Temporary for holding the result, initialized to the input
46598 operand to ease control flow. */
46606 /* load nextafter (0.5, 0.0) */
46611 /* xa = xa + 0.5 */
46615 /* xa = (double)(int64_t)xa */
46620 /* res = copysign (xa, operand1) */
46627 }
46629 /* Expand SSE sequence for computing round
46630 from OP1 storing into OP0 using sse4 round insn. */
46631 void
46633 {
46642 {
46653 }
46655 /* round (a) = trunc (a + copysign (0.5, a)) */
46657 /* load nextafter (0.5, 0.0) */
46663 /* e1 = copysign (0.5, op1) */
46667 /* e2 = op1 + e1 */
46670 /* res = trunc (e2) */
46675 }
46676 \f
46678 /* Table of valid machine attributes. */
46680 {
46681 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler,
46682 affects_type_identity } */
46683 /* Stdcall attribute says callee is responsible for popping arguments
46684 if they are not variable. */
46687 /* Fastcall attribute says callee is responsible for popping arguments
46688 if they are not variable. */
46691 /* Thiscall attribute says callee is responsible for popping arguments
46692 if they are not variable. */
46695 /* Cdecl attribute says the callee is a normal C declaration */
46698 /* Regparm attribute specifies how many integer arguments are to be
46699 passed in registers. */
46702 /* Sseregparm attribute says we are using x86_64 calling conventions
46703 for FP arguments. */
46706 /* The transactional memory builtins are implicitly regparm or fastcall
46707 depending on the ABI. Override the generic do-nothing attribute that
46708 these builtins were declared with. */
46711 /* force_align_arg_pointer says this function realigns the stack at entry. */
46714 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
46719 #endif
46724 #ifdef SUBTARGET_ATTRIBUTE_TABLE
46725 SUBTARGET_ATTRIBUTE_TABLE,
46726 #endif
46727 /* ms_abi and sysv_abi calling convention function attributes. */
46734 /* End element. */
46736 };
46738 /* Implement targetm.vectorize.builtin_vectorization_cost. */
46739 static int
46742 {
46746 {
46791 }
46792 }
46794 /* A cached (set (nil) (vselect (vconcat (nil) (nil)) (parallel [])))
46795 insn, so that expand_vselect{,_vconcat} doesn't have to create a fresh
46796 insn every time. */
46800 /* Initialize vselect_insn. */
46802 static void
46804 {
46806 rtx x;
46817 }
46819 /* Construct (set target (vec_select op0 (parallel perm))) and
46820 return true if that's a valid instruction in the active ISA. */
46822 static bool
46825 {
46851 }
46853 /* Similar, but generate a vec_concat from op0 and op1 as well. */
46855 static bool
46859 {
46860 machine_mode v2mode;
46861 rtx x;
46876 }
46878 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
46879 in terms of blendp[sd] / pblendw / pblendvb / vpblendd. */
46881 static bool
46883 {
46892 && (TARGET_AVX512BW
46894 ;
46896 ;
46898 ;
46900 ;
46901 else
46904 /* This is a blend, not a permute. Elements must stay in their
46905 respective lanes. */
46907 {
46911 }
46916 /* ??? Without SSE4.1, we could implement this with and/andn/or. This
46917 decision should be extracted elsewhere, so that we only try that
46918 sequence once all budget==3 options have been tried. */
46925 {
46955 /* See if bytes move in pairs so we can use pblendw with
46956 an immediate argument, rather than pblendvb with a vector
46957 argument. */
46960 {
46961 use_pblendvb:
46965 finish_pblendvb:
46971 else
46976 }
46981 /* FALLTHRU */
46983 do_subreg:
46990 /* See if bytes move in pairs. If not, vpblendvb must be used. */
46994 /* See if bytes move in quadruplets. If yes, vpblendd
46995 with immediate can be used. */
47000 {
47001 /* See if bytes move the same in both lanes. If yes,
47002 vpblendw with immediate can be used. */
47007 /* Use vpblendw. */
47012 }
47014 /* Use vpblendd. */
47021 /* See if words move in pairs. If yes, vpblendd can be used. */
47026 {
47027 /* See if words move the same in both lanes. If not,
47028 vpblendvb must be used. */
47031 {
47032 /* Use vpblendvb. */
47042 }
47044 /* Use vpblendw. */
47048 }
47050 /* Use vpblendd. */
47057 /* Use vpblendd. */
47065 }
47068 {
47085 }
47089 else
47092 /* This matches five different patterns with the different modes. */
47100 }
47102 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47103 in terms of the variable form of vpermilps.
47105 Note that we will have already failed the immediate input vpermilps,
47106 which requires that the high and low part shuffle be identical; the
47107 variable form doesn't require that. */
47109 static bool
47111 {
47118 /* We can only permute within the 128-bit lane. */
47120 {
47124 }
47130 {
47133 /* Within each 128-bit lane, the elements of op0 are numbered
47134 from 0 and the elements of op1 are numbered from 4. */
47141 }
47148 }
47150 /* Return true if permutation D can be performed as VMODE permutation
47151 instead. */
47153 static bool
47155 {
47170 else
47176 }
47178 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47179 in terms of pshufb, vpperm, vpermq, vpermd, vpermps or vperm2i128. */
47181 static bool
47183 {
47192 {
47194 {
47197 {
47201 /* Use vperm2i128 insn. The pattern uses
47202 V4DImode instead of V2TImode. */
47215 }
47217 }
47218 }
47219 else
47220 {
47222 {
47225 }
47227 {
47231 /* V4DImode should be already handled through
47232 expand_vselect by vpermq instruction. */
47239 {
47240 /* First see if vpermq can be used for
47241 V8SImode/V16HImode/V32QImode. */
47243 {
47251 {
47255 }
47257 }
47259 /* Next see if vpermd can be used. */
47262 }
47263 /* Or if vpermps can be used. */
47268 {
47269 /* vpshufb only works intra lanes, it is not
47270 possible to shuffle bytes in between the lanes. */
47274 }
47275 }
47277 {
47281 /* If vpermq didn't work, vpshufb won't work either. */
47289 {
47290 /* First see if vpermq can be used for
47291 V16SImode/V32HImode/V64QImode. */
47293 {
47301 {
47305 }
47307 }
47309 /* Next see if vpermd can be used. */
47312 }
47313 /* Or if vpermps can be used. */
47317 {
47318 /* vpshufb only works intra lanes, it is not
47319 possible to shuffle bytes in between the lanes. */
47323 }
47324 }
47325 else
47327 }
47338 else
47339 {
47347 else
47351 {
47355 }
47356 }
47367 {
47382 else
47384 }
47385 else
47386 {
47389 }
47394 }
47396 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to instantiate D
47397 in a single instruction. */
47399 static bool
47401 {
47405 /* Check plain VEC_SELECT first, because AVX has instructions that could
47406 match both SEL and SEL+CONCAT, but the plain SEL will allow a memory
47407 input where SEL+CONCAT may not. */
47409 {
47415 {
47421 }
47424 {
47428 }
47430 {
47431 /* Use vpbroadcast{b,w,d}. */
47434 {
47477 /* For other modes prefer other shuffles this function creates. */
47479 }
47481 {
47485 }
47486 }
47491 /* There are plenty of patterns in sse.md that are written for
47492 SEL+CONCAT and are not replicated for a single op. Perhaps
47493 that should be changed, to avoid the nastiness here. */
47495 /* Recognize interleave style patterns, which means incrementing
47496 every other permutation operand. */
47498 {
47501 }
47506 /* Recognize shufps, which means adding {0, 0, nelt, nelt}. */
47508 {
47510 {
47515 }
47520 }
47521 }
47523 /* Finally, try the fully general two operand permute. */
47528 /* Recognize interleave style patterns with reversed operands. */
47530 {
47532 {
47536 else
47539 }
47544 }
47546 /* Try the SSE4.1 blend variable merge instructions. */
47550 /* Try one of the AVX vpermil variable permutations. */
47554 /* Try the SSSE3 pshufb or XOP vpperm or AVX2 vperm2i128,
47555 vpshufb, vpermd, vpermps or vpermq variable permutation. */
47559 /* Try the AVX2 vpalignr instruction. */
47563 /* Try the AVX512F vpermi2 instructions. */
47568 }
47570 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement D
47571 in terms of a pair of pshuflw + pshufhw instructions. */
47573 static bool
47575 {
47583 /* The two permutations only operate in 64-bit lanes. */
47594 /* Emit the pshuflw. */
47601 /* Emit the pshufhw. */
47609 }
47611 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47612 the permutation using the SSSE3 palignr instruction. This succeeds
47613 when all of the elements in PERM fit within one vector and we merely
47614 need to shift them down so that a single vector permutation has a
47615 chance to succeed. If SINGLE_INSN_ONLY_P, succeed if only
47616 the vpalignr instruction itself can perform the requested permutation. */
47618 static bool
47620 {
47627 /* Even with AVX, palignr only operates on 128-bit vectors,
47628 in AVX2 palignr operates on both 128-bit lanes. */
47638 {
47642 {
47645 }
47654 }
47657 {
47666 }
47668 /* Given that we have SSSE3, we know we'll be able to implement the
47669 single operand permutation after the palignr with pshufb for
47670 128-bit vectors. If SINGLE_INSN_ONLY_P, in_order has to be computed
47671 first. */
47677 {
47682 }
47686 {
47692 else
47697 }
47703 /* For AVX2, test whether we can permute the result in one instruction. */
47705 {
47710 }
47714 {
47718 }
47719 else
47720 {
47725 shift));
47726 }
47730 /* Test for the degenerate case where the alignment by itself
47731 produces the desired permutation. */
47733 {
47736 }
47742 }
47744 /* A subroutine of ix86_expand_vec_perm_const_1. Try to simplify
47745 the permutation using the SSE4_1 pblendv instruction. Potentially
47746 reduces permutation from 2 pshufb and or to 1 pshufb and pblendv. */
47748 static bool
47750 {
47756 /* Use the same checks as in expand_vec_perm_blend. */
47760 ;
47762 ;
47764 ;
47765 else
47768 /* Figure out where permutation elements stay not in their
47769 respective lanes. */
47771 {
47775 }
47776 /* We can pblend the part where elements stay not in their
47777 respective lanes only when these elements are all in one
47778 half of a permutation.
47779 {0 1 8 3 4 5 9 7} is ok as 8, 9 are at not at their respective
47780 lanes, but both 8 and 9 >= 8
47781 {0 1 8 3 4 5 2 7} is not ok as 2 and 8 are not at their
47782 respective lanes and 8 >= 8, but 2 not. */
47788 /* First we apply one operand permutation to the part where
47789 elements stay not in their respective lanes. */
47793 else
47805 else
47810 /* Next we put permuted elements into their positions. */
47814 else
47824 }
47828 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
47829 a two vector permutation into a single vector permutation by using
47830 an interleave operation to merge the vectors. */
47832 static bool
47834 {
47843 {
47846 }
47848 {
47851 /* For 32-byte modes allow even d->one_operand_p.
47852 The lack of cross-lane shuffling in some instructions
47853 might prevent a single insn shuffle. */
47856 /* If expand_vec_perm_interleave3 can expand this into
47857 a 3 insn sequence, give up and let it be expanded as
47858 3 insn sequence. While that is one insn longer,
47859 it doesn't need a memory operand and in the common
47860 case that both interleave low and high permutations
47861 with the same operands are adjacent needs 4 insns
47862 for both after CSE. */
47865 }
47866 else
47869 /* Examine from whence the elements come. */
47878 {
47881 /* Split the two input vectors into 4 halves. */
47887 /* If the elements from the low halves use interleave low, and similarly
47888 for interleave high. If the elements are from mis-matched halves, we
47889 can use shufps for V4SF/V4SI or do a DImode shuffle. */
47891 {
47892 /* punpckl* */
47894 {
47899 }
47902 }
47904 {
47905 /* punpckh* */
47907 {
47912 }
47915 }
47917 {
47918 /* shufps */
47920 {
47925 }
47927 {
47928 /* shufpd */
47933 }
47934 }
47936 {
47937 /* shufps */
47939 {
47944 }
47946 {
47947 /* shufpd */
47952 }
47953 }
47954 else
47956 }
47957 else
47958 {
47963 /* Split the two input vectors into 8 quarters. */
47969 {
47972 }
47975 {
47979 }
47981 {
47984 }
47987 {
47989 {
47990 /* Attempt to increase the likelihood that dfinal
47991 shuffle will be intra-lane. */
47993 }
47995 /* vperm2f128 or vperm2i128. */
47997 {
48002 }
48007 {
48011 {
48014 }
48015 }
48016 }
48021 {
48022 /* vpunpckl* */
48024 {
48033 }
48034 }
48037 {
48038 /* vpunpckh* */
48040 {
48049 }
48050 }
48051 else
48053 }
48055 /* Use the remapping array set up above to move the elements from their
48056 swizzled locations into their final destinations. */
48059 {
48062 /* If same_halves is true, both halves of the remapped vector are the
48063 same. Avoid cross-lane accesses if possible. */
48065 {
48068 }
48069 else
48071 }
48073 {
48076 }
48080 /* Test if the final remap can be done with a single insn. For V4SFmode or
48081 V4SImode this *will* succeed. For V8HImode or V16QImode it may not. */
48094 {
48097 }
48104 }
48106 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48107 a single vector cross-lane permutation into vpermq followed
48108 by any of the single insn permutations. */
48110 static bool
48112 {
48126 {
48129 }
48132 {
48137 }
48150 {
48157 }
48164 {
48169 ;
48172 else
48174 }
48183 }
48185 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to expand
48186 a vector permutation using two instructions, vperm2f128 resp.
48187 vperm2i128 followed by any single in-lane permutation. */
48189 static bool
48191 {
48205 /* ((perm << 2)|perm) & 0x33 is the vperm2[fi]128
48206 immediate. For perm < 16 the second permutation uses
48207 d->op0 as first operand, for perm >= 16 it uses d->op1
48208 as first operand. The second operand is the result of
48209 vperm2[fi]128. */
48211 {
48212 /* Ignore permutations which do not move anything cross-lane. */
48214 {
48215 /* The second shuffle for e.g. V4DFmode has
48216 0123 and ABCD operands.
48217 Ignore AB23, as 23 is already in the second lane
48218 of the first operand. */
48220 /* And 01CD, as 01 is in the first lane of the first
48221 operand. */
48223 /* And 4567, as then the vperm2[fi]128 doesn't change
48224 anything on the original 4567 second operand. */
48226 }
48227 else
48228 {
48229 /* The second shuffle for e.g. V4DFmode has
48230 4567 and ABCD operands.
48231 Ignore AB67, as 67 is already in the second lane
48232 of the first operand. */
48234 /* And 45CD, as 45 is in the first lane of the first
48235 operand. */
48237 /* And 0123, as then the vperm2[fi]128 doesn't change
48238 anything on the original 0123 first operand. */
48240 }
48243 {
48249 else
48251 }
48254 {
48258 }
48259 else
48263 {
48267 /* Found a usable second shuffle. dfirst will be
48268 vperm2f128 on d->op0 and d->op1. */
48280 /* And dsecond is some single insn shuffle, taking
48281 d->op0 and result of vperm2f128 (if perm < 16) or
48282 d->op1 and result of vperm2f128 (otherwise). */
48291 }
48293 /* For one operand, the only useful vperm2f128 permutation is 0x01
48294 aka lanes swap. */
48297 }
48300 }
48302 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to simplify
48303 a two vector permutation using 2 intra-lane interleave insns
48304 and cross-lane shuffle for 32-byte vectors. */
48306 static bool
48308 {
48315 ;
48317 ;
48318 else
48333 {
48337 else
48343 else
48349 else
48355 else
48361 else
48367 else
48372 }
48376 }
48378 /* A subroutine of ix86_expand_vec_perm_builtin_1. Try to implement
48379 a single vector permutation using a single intra-lane vector
48380 permutation, vperm2f128 swapping the lanes and vblend* insn blending
48381 the non-swapped and swapped vectors together. */
48383 static bool
48385 {
48393 || TARGET_AVX2
48402 {
48409 }
48444 }
48446 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement a V4DF
48447 permutation using two vperm2f128, followed by a vshufpd insn blending
48448 the two vectors together. */
48450 static bool
48452 {
48495 }
48497 /* A subroutine of expand_vec_perm_even_odd_1. Implement the double-word
48498 permutation with two pshufb insns and an ior. We should have already
48499 failed all two instruction sequences. */
48501 static bool
48503 {
48517 /* Generate two permutation masks. If the required element is within
48518 the given vector it is shuffled into the proper lane. If the required
48519 element is in the other vector, force a zero into the lane by setting
48520 bit 7 in the permutation mask. */
48523 {
48530 {
48533 }
48534 }
48558 }
48560 /* Implement arbitrary permutation of one V32QImode and V16QImode operand
48561 with two vpshufb insns, vpermq and vpor. We should have already failed
48562 all two or three instruction sequences. */
48564 static bool
48566 {
48581 /* Generate two permutation masks. If the required element is within
48582 the same lane, it is shuffled in. If the required element from the
48583 other lane, force a zero by setting bit 7 in the permutation mask.
48584 In the other mask the mask has non-negative elements if element
48585 is requested from the other lane, but also moved to the other lane,
48586 so that the result of vpshufb can have the two V2TImode halves
48587 swapped. */
48590 {
48595 {
48598 }
48599 }
48608 /* Swap the 128-byte lanes of h into hp. */
48612 const1_rtx));
48629 }
48631 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48632 and extract-odd permutations of two V32QImode and V16QImode operand
48633 with two vpshufb insns, vpor and vpermq. We should have already
48634 failed all two or three instruction sequences. */
48636 static bool
48638 {
48657 /* Generate two permutation masks. In the first permutation mask
48658 the first quarter will contain indexes for the first half
48659 of the op0, the second quarter will contain bit 7 set, third quarter
48660 will contain indexes for the second half of the op0 and the
48661 last quarter bit 7 set. In the second permutation mask
48662 the first quarter will contain bit 7 set, the second quarter
48663 indexes for the first half of the op1, the third quarter bit 7 set
48664 and last quarter indexes for the second half of the op1.
48665 I.e. the first mask e.g. for V32QImode extract even will be:
48666 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128
48667 (all values masked with 0xf except for -128) and second mask
48668 for extract even will be
48669 -128, ..., -128, 0, 2, ..., 0xe, -128, ..., -128, 0, 2, ..., 0xe. */
48672 {
48678 {
48681 }
48682 }
48701 /* Permute the V4DImode quarters using { 0, 2, 1, 3 } permutation. */
48709 }
48711 /* A subroutine of expand_vec_perm_even_odd_1. Implement extract-even
48712 and extract-odd permutations of two V16QI, V8HI, V16HI or V32QI operands
48713 with two "and" and "pack" or two "shift" and "pack" insns. We should
48714 have already failed all two instruction sequences. */
48716 static bool
48718 {
48722 machine_mode half_mode;
48731 {
48733 /* Required for "pack". */
48744 /* No check as all instructions are SSE2. */
48775 /* Only V8HI, V16QI, V16HI and V32QI modes are more profitable than
48776 general shuffles. */
48778 }
48780 /* Check that permutation is even or odd. */
48795 {
48802 }
48803 else
48804 {
48811 }
48812 /* In AVX2 for 256 bit case we need to permute pack result. */
48814 {
48820 const0_rtx,
48821 const2_rtx,
48822 const1_rtx,
48825 }
48826 else
48830 }
48832 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement extract-even
48833 and extract-odd permutations. */
48835 static bool
48837 {
48841 {
48848 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
48852 /* Now an unpck[lh]pd will produce the result required. */
48855 else
48861 {
48870 /* Shuffle within the 128-bit lanes to produce:
48871 { 0 2 8 a 4 6 c e } | { 1 3 9 b 5 7 d f }. */
48875 /* Shuffle the lanes around to produce:
48876 { 4 6 c e 0 2 8 a } and { 5 7 d f 1 3 9 b }. */
48880 /* Shuffle within the 128-bit lanes to produce:
48881 { 0 2 4 6 4 6 0 2 } | { 1 3 5 7 5 7 1 3 }. */
48884 /* Shuffle within the 128-bit lanes to produce:
48885 { 8 a c e c e 8 a } | { 9 b d f d f 9 b }. */
48888 /* Shuffle the lanes around to produce:
48889 { 0 2 4 6 8 a c e } | { 1 3 5 7 9 b d f }. */
48892 }
48899 /* These are always directly implementable by expand_vec_perm_1. */
48907 else
48908 {
48911 /* We need 2*log2(N)-1 operations to achieve odd/even
48912 with interleave. */
48921 else
48924 }
48936 {
48941 else
48946 {
48951 }
48953 }
48961 /* Shuffle the lanes around into { 0 1 4 5 } and { 2 3 6 7 }. */
48965 /* Now an vpunpck[lh]qdq will produce the result required. */
48968 else
48975 {
48980 else
48985 {
48990 }
48992 }
49003 /* Shuffle the lanes around into
49004 { 0 1 2 3 8 9 a b } and { 4 5 6 7 c d e f }. */
49012 /* Swap the 2nd and 3rd position in each lane into
49013 { 0 2 1 3 8 a 9 b } and { 4 6 5 7 c e d f }. */
49019 /* Now an vpunpck[lh]qdq will produce
49020 { 0 2 4 6 8 a c e } resp. { 1 3 5 7 9 b d f }. */
49024 else
49033 }
49036 }
49038 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
49039 extract-even and extract-odd permutations. */
49041 static bool
49043 {
49055 }
49057 /* A subroutine of ix86_expand_vec_perm_builtin_1. Implement broadcast
49058 permutations. We assume that expand_vec_perm_1 has already failed. */
49060 static bool
49062 {
49070 {
49073 /* These are special-cased in sse.md so that we can optionally
49074 use the vbroadcast instruction. They expand to two insns
49075 if the input happens to be in a register. */
49082 /* These are always implementable using standard shuffle patterns. */
49087 /* These can be implemented via interleave. We save one insn by
49088 stopping once we have promoted to V4SImode and then use pshufd. */
49091 do
49092 {
49093 rtx dest;
49099 {
49103 }
49110 }
49126 /* For AVX2 broadcasts of the first element vpbroadcast* or
49127 vpermq should be used by expand_vec_perm_1. */
49133 }
49134 }
49136 /* A subroutine of ix86_expand_vec_perm_builtin_1. Pattern match
49137 broadcast permutations. */
49139 static bool
49141 {
49153 }
49155 /* Implement arbitrary permutations of two V64QImode operands
49156 will 2 vpermi2w, 2 vpshufb and one vpor instruction. */
49157 static bool
49159 {
49169 machine_mode vmode;
49175 {
49182 }
49184 /* Prepare permutations such that the first one takes care of
49185 putting the even bytes into the right positions or one higher
49186 positions (ds[0]) and the second one takes care of
49187 putting the odd bytes into the right positions or one below
49188 (ds[1]). */
49191 {
49194 {
49197 }
49198 else
49199 {
49202 }
49203 }
49225 }
49227 /* Implement arbitrary permutation of two V32QImode and V16QImode operands
49228 with 4 vpshufb insns, 2 vpermq and 3 vpor. We should have already failed
49229 all the shorter instruction sequences. */
49231 static bool
49233 {
49249 /* Generate 4 permutation masks. If the required element is within
49250 the same lane, it is shuffled in. If the required element from the
49251 other lane, force a zero by setting bit 7 in the permutation mask.
49252 In the other mask the mask has non-negative elements if element
49253 is requested from the other lane, but also moved to the other lane,
49254 so that the result of vpshufb can have the two V2TImode halves
49255 swapped. */
49258 {
49263 }
49269 {
49277 }
49280 {
49282 {
49285 }
49292 }
49294 /* Swap the 128-byte lanes of h[X]. */
49296 {
49302 const1_rtx));
49304 }
49307 {
49309 {
49312 }
49318 }
49321 {
49323 {
49327 }
49330 }
49340 }
49342 /* The guts of ix86_expand_vec_perm_const, also used by the ok hook.
49343 With all of the interface bits taken care of, perform the expansion
49344 in D and return true on success. */
49346 static bool
49348 {
49349 /* Try a single instruction expansion. */
49353 /* Try sequences of two instructions. */
49376 /* Try sequences of three instructions. */
49393 /* Try sequences of four instructions. */
49404 /* ??? Look for narrow permutations whose element orderings would
49405 allow the promotion to a wider mode. */
49407 /* ??? Look for sequences of interleave or a wider permute that place
49408 the data into the correct lanes for a half-vector shuffle like
49409 pshuf[lh]w or vpermilps. */
49411 /* ??? Look for sequences of interleave that produce the desired results.
49412 The combinatorics of punpck[lh] get pretty ugly... */
49417 /* Even longer sequences. */
49422 }
49424 /* If a permutation only uses one operand, make it clear. Returns true
49425 if the permutation references both operands. */
49427 static bool
49429 {
49437 {
49443 {
49446 }
49447 /* The elements of PERM do not suggest that only the first operand
49448 is used, but both operands are identical. Allow easier matching
49449 of the permutation by folding the permutation into the single
49450 input vector. */
49451 /* FALLTHRU */
49462 }
49465 }
49467 bool
49469 {
49474 rtx sel;
49491 {
49496 }
49503 /* If the selector says both arguments are needed, but the operands are the
49504 same, the above tried to expand with one_operand_p and flattened selector.
49505 If that didn't work, retry without one_operand_p; we succeeded with that
49506 during testing. */
49508 {
49512 }
49515 }
49517 /* Implement targetm.vectorize.vec_perm_const_ok. */
49519 static bool
49522 {
49531 /* Given sufficient ISA support we can just return true here
49532 for selected vector modes. */
49534 {
49540 /* All implementable with a single vpermi2 insn. */
49545 /* All implementable with a single vpermi2 insn. */
49550 /* Implementable with 2 vpermi2, 2 vpshufb and 1 or insn. */
49558 /* All implementable with a single vpermi2 insn. */
49563 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49568 /* Implementable with 4 vpshufb insns, 2 vpermq and 3 vpor insns. */
49575 /* All implementable with a single vpperm insn. */
49578 /* All implementable with 2 pshufb + 1 ior. */
49584 /* All implementable with shufpd or unpck[lh]pd. */
49588 }
49590 /* Extract the values from the vector CST into the permutation
49591 array in D. */
49594 {
49598 }
49600 /* For all elements from second vector, fold the elements to first. */
49605 /* Check whether the mask can be applied to the vector type. */
49608 /* Implementable with shufps or pshufd. */
49612 /* Otherwise we have to go through the motions and see if we can
49613 figure out how to generate the requested permutation. */
49624 }
49626 void
49628 {
49643 /* We'll either be able to implement the permutation directly... */
49647 /* ... or we use the special-case patterns. */
49649 }
49651 static void
49653 {
49668 {
49671 }
49673 /* Note that for AVX this isn't one instruction. */
49676 }
49679 /* Expand a vector operation CODE for a V*QImode in terms of the
49680 same operation on V*HImode. */
49682 void
49684 {
49686 machine_mode himode;
49696 {
49714 }
49718 {
49720 /* Unpack data such that we've got a source byte in each low byte of
49721 each word. We don't care what goes into the high byte of each word.
49722 Rather than trying to get zero in there, most convenient is to let
49723 it be a copy of the low byte. */
49728 /* FALLTHRU */
49740 /* FALLTHRU */
49750 }
49752 /* Perform the operation. */
49759 /* Merge the data back into the right place. */
49769 {
49770 /* For SSE2, we used an full interleave, so the desired
49771 results are in the even elements. */
49774 }
49775 else
49776 {
49777 /* For AVX, the interleave used above was not cross-lane. So the
49778 extraction is evens but with the second and third quarter swapped.
49779 Happily, that is even one insn shorter than even extraction. */
49782 }
49789 }
49791 /* Helper function of ix86_expand_mul_widen_evenodd. Return true
49792 if op is CONST_VECTOR with all odd elements equal to their
49793 preceding element. */
49795 static bool
49797 {
49807 }
49809 void
49812 {
49815 rtx x;
49823 /* We only play even/odd games with vectors of SImode. */
49826 /* If we're looking for the odd results, shift those members down to
49827 the even slots. For some cpus this is faster than a PSHUFD. */
49829 {
49830 /* For XOP use vpmacsdqh, but only for smult, as it is only
49831 signed. */
49833 {
49837 }
49848 }
49851 {
49854 else
49856 }
49858 {
49861 else
49863 }
49868 else
49869 {
49872 /* The easiest way to implement this without PMULDQ is to go through
49873 the motions as if we are performing a full 64-bit multiply. With
49874 the exception that we need to do less shuffling of the elements. */
49876 /* Compute the sign-extension, aka highparts, of the two operands. */
49882 /* Multiply LO(A) * HI(B), and vice-versa. */
49888 /* Multiply LO(A) * LO(B). */
49892 /* Combine and shift the highparts into place. */
49897 /* Combine high and low parts. */
49900 }
49902 }
49904 void
49907 {
49913 {
49918 {
49919 /* With XOP, we have pmacsdqh, aka mul_widen_odd. In this case,
49920 shuffle the elements once so that all elements are in the right
49921 place for immediate use: { A C B D }. */
49926 }
49927 else
49928 {
49929 /* Put the elements into place for the multiply. */
49933 }
49938 /* Shuffle the elements between the lanes. After this we
49939 have { A B E F | C D G H } for each operand. */
49949 /* Shuffle the elements within the lanes. After this we
49950 have { A A B B | C C D D } or { E E F F | G G H H }. */
49991 }
49992 }
49994 void
49996 {
50006 /* Move the results in element 2 down to element 1; we don't care
50007 what goes in elements 2 and 3. Then we can merge the parts
50008 back together with an interleave.
50010 Note that two other sequences were tried:
50011 (1) Use interleaves at the start instead of psrldq, which allows
50012 us to use a single shufps to merge things back at the end.
50013 (2) Use shufps here to combine the two vectors, then pshufd to
50014 put the elements in the correct order.
50015 In both cases the cost of the reformatting stall was too high
50016 and the overall sequence slower. */
50027 }
50029 void
50031 {
50042 {
50043 /* op1: A,B,C,D, op2: E,F,G,H */
50052 /* t1: B,A,D,C */
50059 /* t2: (B*E),(A*F),(D*G),(C*H) */
50062 /* t3: (B*E)+(A*F), (D*G)+(C*H) */
50065 /* t4: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
50068 /* Multiply lower parts and add all */
50075 }
50076 else
50077 {
50078 machine_mode nmode;
50082 {
50085 }
50087 {
50090 }
50092 {
50095 }
50096 else
50100 /* Multiply low parts. */
50104 /* Shift input vectors right 32 bits so we can multiply high parts. */
50109 /* Multiply high parts by low parts. */
50115 /* Combine and shift the highparts back. */
50119 /* Combine high and low parts. */
50121 }
50125 }
50127 /* Return 1 if control tansfer instruction INSN
50128 should be encoded with bnd prefix.
50129 If insn is NULL then return 1 when control
50130 transfer instructions should be prefixed with
50131 bnd by default for current function. */
50133 bool
50135 {
50136 /* For call insns check special flag. */
50138 {
50142 }
50144 /* All other insns are prefixed only if function is instrumented. */
50146 }
50148 /* Calculate integer abs() using only SSE2 instructions. */
50150 void
50152 {
50157 {
50158 /* For 32-bit signed integer X, the best way to calculate the absolute
50159 value of X is (((signed) X >> (W-1)) ^ X) - ((signed) X >> (W-1)). */
50171 /* For 16-bit signed integer X, the best way to calculate the absolute
50172 value of X is max (X, -X), as SSE2 provides the PMAXSW insn. */
50180 /* For 8-bit signed integer X, the best way to calculate the absolute
50181 value of X is min ((unsigned char) X, (unsigned char) (-X)),
50182 as SSE2 provides the PMINUB insn. */
50192 }
50196 }
50198 /* Expand an insert into a vector register through pinsr insn.
50199 Return true if successful. */
50201 bool
50203 {
50211 {
50214 }
50220 {
50225 {
50232 {
50264 }
50278 }
50282 }
50283 }
50284 \f
50285 /* This function returns the calling abi specific va_list type node.
50286 It returns the FNDECL specific va_list type. */
50288 static tree
50290 {
50297 else
50299 }
50301 /* Returns the canonical va_list type specified by TYPE. If there
50302 is no valid TYPE provided, it return NULL_TREE. */
50304 static tree
50306 {
50309 /* Resolve references and pointers to va_list type. */
50318 {
50323 {
50324 /* If va_list is an array type, the argument may have decayed
50325 to a pointer type, e.g. by being passed to another function.
50326 In that case, unwrap both types so that we can compare the
50327 underlying records. */
50330 {
50333 }
50334 }
50341 {
50342 /* If va_list is an array type, the argument may have decayed
50343 to a pointer type, e.g. by being passed to another function.
50344 In that case, unwrap both types so that we can compare the
50345 underlying records. */
50348 {
50351 }
50352 }
50359 {
50360 /* If va_list is an array type, the argument may have decayed
50361 to a pointer type, e.g. by being passed to another function.
50362 In that case, unwrap both types so that we can compare the
50363 underlying records. */
50366 {
50369 }
50370 }
50374 }
50376 }
50378 /* Iterate through the target-specific builtin types for va_list.
50379 IDX denotes the iterator, *PTREE is set to the result type of
50380 the va_list builtin, and *PNAME to its internal type.
50381 Returns zero if there is no element for this index, otherwise
50382 IDX should be increased upon the next call.
50383 Note, do not iterate a base builtin's name like __builtin_va_list.
50384 Used from c_common_nodes_and_builtins. */
50386 static int
50388 {
50390 {
50392 {
50405 }
50406 }
50409 }
50411 #undef TARGET_SCHED_DISPATCH
50412 #define TARGET_SCHED_DISPATCH has_dispatch
50413 #undef TARGET_SCHED_DISPATCH_DO
50414 #define TARGET_SCHED_DISPATCH_DO do_dispatch
50415 #undef TARGET_SCHED_REASSOCIATION_WIDTH
50416 #define TARGET_SCHED_REASSOCIATION_WIDTH ix86_reassociation_width
50417 #undef TARGET_SCHED_REORDER
50418 #define TARGET_SCHED_REORDER ix86_sched_reorder
50419 #undef TARGET_SCHED_ADJUST_PRIORITY
50420 #define TARGET_SCHED_ADJUST_PRIORITY ix86_adjust_priority
50421 #undef TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK
50422 #define TARGET_SCHED_DEPENDENCIES_EVALUATION_HOOK \
50423 ix86_dependencies_evaluation_hook
50425 /* The size of the dispatch window is the total number of bytes of
50426 object code allowed in a window. */
50427 #define DISPATCH_WINDOW_SIZE 16
50429 /* Number of dispatch windows considered for scheduling. */
50430 #define MAX_DISPATCH_WINDOWS 3
50432 /* Maximum number of instructions in a window. */
50433 #define MAX_INSN 4
50435 /* Maximum number of immediate operands in a window. */
50436 #define MAX_IMM 4
50438 /* Maximum number of immediate bits allowed in a window. */
50439 #define MAX_IMM_SIZE 128
50441 /* Maximum number of 32 bit immediates allowed in a window. */
50442 #define MAX_IMM_32 4
50444 /* Maximum number of 64 bit immediates allowed in a window. */
50445 #define MAX_IMM_64 2
50447 /* Maximum total of loads or prefetches allowed in a window. */
50448 #define MAX_LOAD 2
50450 /* Maximum total of stores allowed in a window. */
50451 #define MAX_STORE 1
50453 #undef BIG
50454 #define BIG 100
50457 /* Dispatch groups. Istructions that affect the mix in a dispatch window. */
50460 disp_load,
50461 disp_store,
50462 disp_load_store,
50463 disp_prefetch,
50464 disp_imm,
50465 disp_imm_32,
50466 disp_imm_64,
50467 disp_branch,
50468 disp_cmp,
50469 disp_jcc,
50470 disp_last
50471 };
50473 /* Number of allowable groups in a dispatch window. It is an array
50474 indexed by dispatch_group enum. 100 is used as a big number,
50475 because the number of these kind of operations does not have any
50476 effect in dispatch window, but we need them for other reasons in
50477 the table. */
50480 };
50486 };
50488 /* Instruction path. */
50494 last_path
50495 };
50497 /* sched_insn_info defines a window to the instructions scheduled in
50498 the basic block. It contains a pointer to the insn_info table and
50499 the instruction scheduled.
50501 Windows are allocated for each basic block and are linked
50502 together. */
50504 rtx insn;
50511 /* Linked list of dispatch windows. This is a two way list of
50512 dispatch windows of a basic block. It contains information about
50513 the number of uops in the window and the total number of
50514 instructions and of bytes in the object code for this dispatch
50515 window. */
50533 /* Immediate valuse used in an insn. */
50535 {
50544 /* Get dispatch group of insn. */
50546 static enum dispatch_group
50548 {
50564 }
50566 /* Return true if insn is a compare instruction. */
50568 static bool
50570 {
50578 }
50580 /* Return true if a dispatch violation encountered. */
50582 static bool
50584 {
50588 }
50590 /* Return true if insn is a branch instruction. */
50592 static bool
50594 {
50596 }
50598 /* Return true if insn is a prefetch instruction. */
50600 static bool
50602 {
50604 }
50606 /* This function initializes a dispatch window and the list container holding a
50607 pointer to the window. */
50609 static void
50611 {
50617 else
50635 {
50641 }
50643 }
50645 /* This function allocates and initializes a dispatch window and the
50646 list container holding a pointer to the window. */
50650 {
50655 }
50657 /* This routine initializes the dispatch scheduling information. It
50658 initiates building dispatch scheduler tables and constructs the
50659 first dispatch window. */
50661 static void
50663 {
50664 /* Allocate a dispatch list and a window. */
50669 }
50671 /* This function returns true if a branch is detected. End of a basic block
50672 does not have to be a branch, but here we assume only branches end a
50673 window. */
50675 static bool
50677 {
50679 }
50681 /* This function is called when the end of a window processing is reached. */
50683 static void
50685 {
50688 {
50693 }
50695 }
50697 /* Allocates a new dispatch window and adds it to WINDOW_LIST.
50698 WINDOW_NUM is either 0 or 1. A maximum of two windows are generated
50699 for 48 bytes of instructions. Note that these windows are not dispatch
50700 windows that their sizes are DISPATCH_WINDOW_SIZE. */
50704 {
50706 {
50711 }
50717 }
50719 /* Compute number of immediate operands of an instruction. */
50721 static void
50723 {
50730 {
50737 else
50749 {
50752 }
50757 }
50758 }
50760 /* Return total size of immediate operands of an instruction along with number
50761 of corresponding immediate-operands. It initializes its parameters to zero
50762 befor calling FIND_CONSTANT.
50763 INSN is the input instruction. IMM is the total of immediates.
50764 IMM32 is the number of 32 bit immediates. IMM64 is the number of 64
50765 bit immediates. */
50767 static int
50769 {
50777 }
50779 /* This function indicates if an operand of an instruction is an
50780 immediate. */
50782 static bool
50784 {
50793 }
50795 /* Return single or double path for instructions. */
50797 static enum insn_path
50799 {
50809 }
50811 /* Return insn dispatch group. */
50813 static enum dispatch_group
50815 {
50833 }
50835 /* Count number of GROUP restricted instructions in a dispatch
50836 window WINDOW_LIST. */
50838 static int
50840 {
50851 {
50870 }
50883 }
50885 /* This function returns true if insn satisfies dispatch rules on the
50886 last window scheduled. */
50888 static bool
50890 {
50898 /* Make disp_cmp and disp_jcc get scheduled at the latest. These
50899 instructions should be given the lowest priority in the
50900 scheduling process in Haifa scheduler to make sure they will be
50901 scheduled in the same dispatch window as the reference to them. */
50905 /* Check nonrestricted. */
50909 /* Get last dispatch window. */
50914 {
50919 /* Window 1 is full. Go for next window. */
50921 }
50928 /* See if it fits in the first window. */
50930 {
50931 /* The first widow should have only single and double path
50932 uops. */
50938 }
50940 }
50942 /* Add an instruction INSN with NUM_UOPS micro-operations to the
50943 dispatch window WINDOW_LIST. */
50945 static void
50947 {
50965 /* Initialize window with new instruction. */
50986 {
50989 }
50990 }
50992 /* Adds a scheduled instruction, INSN, to the current dispatch window.
50993 If the total bytes of instructions or the number of instructions in
50994 the window exceed allowable, it allocates a new window. */
50996 static void
50998 {
51021 /* Get the last dispatch window. */
51029 else
51032 /* If current window is full, get a new window.
51033 Window number zero is full, if MAX_INSN uops are scheduled in it.
51034 Window number one is full, if window zero's bytes plus window
51035 one's bytes is 32, or if the bytes of the new instruction added
51036 to the total makes it greater than 48, or it has already MAX_INSN
51037 instructions in it. */
51046 {
51049 }
51052 {
51056 {
51059 }
51060 }
51062 {
51067 {
51070 }
51073 }
51074 else
51078 {
51079 /* End of basic block is reached do end-basic-block process. */
51082 }
51083 }
51085 /* Print the dispatch window, WINDOW_NUM, to FILE. */
51087 DEBUG_FUNCTION static void
51089 {
51095 else
51109 {
51112 fprintf (file, " group[%d] = %s, insn[%d] = %p, path[%d] = %d byte_len[%d] = %d, imm_bytes[%d] = %d\n",
51118 }
51119 }
51121 /* Print to stdout a dispatch window. */
51123 DEBUG_FUNCTION void
51125 {
51127 }
51129 /* Print INSN dispatch information to FILE. */
51131 DEBUG_FUNCTION static void
51133 {
51156 }
51158 /* Print to STDERR the status of the ready list with respect to
51159 dispatch windows. */
51161 DEBUG_FUNCTION void
51163 {
51171 }
51173 /* This routine is the driver of the dispatch scheduler. */
51175 static void
51177 {
51182 }
51184 /* Return TRUE if Dispatch Scheduling is supported. */
51186 static bool
51188 {
51192 {
51208 }
51211 }
51213 /* Implementation of reassociation_width target hook used by
51214 reassoc phase to identify parallelism level in reassociated
51215 tree. Statements tree_code is passed in OPC. Arguments type
51216 is passed in MODE.
51218 Currently parallel reassociation is enabled for Atom
51219 processors only and we set reassociation width to be 2
51220 because Atom may issue up to 2 instructions per cycle.
51222 Return value should be fixed if parallel reassociation is
51223 enabled for other processors. */
51225 static int
51227 {
51228 /* Vector part. */
51230 {
51233 else
51235 }
51237 /* Scalar part. */
51242 else
51244 }
51246 /* ??? No autovectorization into MMX or 3DNOW until we can reliably
51247 place emms and femms instructions. */
51249 static machine_mode
51251 {
51256 {
51275 else
51287 /* FALLTHRU */
51291 }
51292 }
51294 /* If AVX is enabled then try vectorizing with both 256bit and 128bit
51295 vectors. If AVX512F is enabled then try vectorizing with 512bit,
51296 256bit and 128bit vectors. */
51298 static unsigned int
51300 {
51303 }
51305 \f
51307 /* Return class of registers which could be used for pseudo of MODE
51308 and of class RCLASS for spilling instead of memory. Return NO_REGS
51309 if it is not possible or non-profitable. */
51310 static reg_class_t
51312 {
51318 }
51320 /* Implement targetm.vectorize.init_cost. */
51324 {
51328 }
51330 /* Implement targetm.vectorize.add_stmt_cost. */
51332 static unsigned
51336 {
51343 /* Statements in an inner loop relative to the loop being
51344 vectorized are weighted more heavily. The value here is
51345 arbitrary and could potentially be improved with analysis. */
51351 /* We need to multiply all vector stmt cost by 1.7 (estimated cost)
51352 for Silvermont as it has out of order integer pipeline and can execute
51353 2 scalar instruction per tick, but has in order SIMD pipeline. */
51356 {
51360 }
51365 }
51367 /* Implement targetm.vectorize.finish_cost. */
51369 static void
51372 {
51377 }
51379 /* Implement targetm.vectorize.destroy_cost_data. */
51381 static void
51383 {
51385 }
51387 /* Validate target specific memory model bits in VAL. */
51389 static unsigned HOST_WIDE_INT
51391 {
51398 {
51402 }
51405 {
51409 }
51411 {
51415 }
51417 }
51419 /* Set CLONEI->vecsize_mangle, CLONEI->vecsize_int,
51420 CLONEI->vecsize_float and if CLONEI->simdlen is 0, also
51421 CLONEI->simdlen. Return 0 if SIMD clones shouldn't be emitted,
51422 or number of vecsize_mangle variants that should be emitted. */
51424 static int
51428 {
51435 {
51439 }
51444 {
51451 /* case SCmode: */
51452 /* case DCmode: */
51458 }
51460 tree t;
51464 /* FIXME: Shouldn't we allow such arguments if they are uniform? */
51466 {
51473 /* case SCmode: */
51474 /* case DCmode: */
51480 }
51483 {
51484 /* Parse here processor clause. If not present, default to 'b'. */
51486 }
51488 {
51489 /* If the function isn't exported, we can pick up just one ISA
51490 for the clones. */
51495 else
51498 }
51499 else
51500 {
51503 }
51505 {
51518 }
51520 {
51523 else
51528 }
51530 }
51532 /* Add target attribute to SIMD clone NODE if needed. */
51534 static void
51536 {
51540 {
51555 }
51565 }
51567 /* If SIMD clone NODE can't be used in a vectorized loop
51568 in current function, return -1, otherwise return a badness of using it
51569 (0 if it is most desirable from vecsize_mangle point of view, 1
51570 slightly less desirable, etc.). */
51572 static int
51574 {
51576 {
51594 }
51595 }
51597 /* This function adjusts the unroll factor based on
51598 the hardware capabilities. For ex, bdver3 has
51599 a loop buffer which makes unrolling of smaller
51600 loops less important. This function decides the
51601 unroll factor using number of memory references
51602 (value 32 is used) as a heuristic. */
51604 static unsigned
51606 {
51615 /* Count the number of memory references within the loop body.
51616 This value determines the unrolling factor for bdver3 and bdver4
51617 architectures. */
51626 {
51631 else
51633 }
51640 }
51643 /* Implement TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P. */
51645 static bool
51647 {
51648 /* For x87 floating point with standard excess precision handling,
51649 there is no adddf3 pattern (since x87 floating point only has
51650 XFmode operations) so the default hook implementation gets this
51651 wrong. */
51653 }
51655 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV. */
51657 static void
51659 {
51664 {
51679 hold_fnclex);
51692 }
51694 {
51703 mxcsr_orig_var,
51713 ldmxcsr_hold_call);
51716 else
51721 ldmxcsr_clear_call);
51722 else
51726 stxmcsr_update_call);
51728 {
51734 exceptions_assign);
51735 }
51736 else
51741 ldmxcsr_update_call);
51742 }
51743 tree atomic_feraiseexcept
51748 atomic_feraiseexcept_call);
51749 }
51751 /* Return mode to be used for bounds or VOIDmode
51752 if bounds are not supported. */
51754 static enum machine_mode
51756 {
51757 /* Do not support pointer checker if MPX
51758 is not enabled. */
51760 {
51765 }
51768 }
51770 /* Return constant used to statically initialize constant bounds.
51772 This function is used to create special bound values. For now
51773 only INIT bounds and NONE bounds are expected. More special
51774 values may be added later. */
51776 static tree
51778 {
51784 /* This function is supposed to be used to create INIT and
51785 NONE bounds only. */
51790 }
51792 /* Generate a list of statements STMTS to initialize pointer bounds
51793 variable VAR with bounds LB and UB. Return the number of generated
51794 statements. */
51796 static int
51798 {
51816 }
51818 #if !TARGET_MACHO && !TARGET_DLLIMPORT_DECL_ATTRIBUTES
51819 /* For i386, common symbol is local only for non-PIE binaries. For
51820 x86-64, common symbol is local only for non-PIE binaries or linker
51821 supports copy reloc in PIE binaries. */
51823 static bool
51825 {
51827 (!flag_pic
51828 || (TARGET_64BIT
51830 }
51831 #endif
51833 /* If MEM is in the form of [base+offset], extract the two parts
51834 of address and set to BASE and OFFSET, otherwise return false. */
51836 static bool
51838 {
51839 rtx addr;
51849 {
51853 }
51859 {
51863 }
51866 }
51868 /* Given OPERANDS of consecutive load/store, check if we can merge
51869 them into move multiple. LOAD is true if they are load instructions.
51870 MODE is the mode of memory operands. */
51872 bool
51875 {
51880 {
51885 }
51886 else
51887 {
51892 }
51899 /* Check if the addresses are in the form of [base+offset]. */
51905 /* Check if the bases are the same. */
51912 /* Check if mem_1 is adjacent to mem_2 and mem_1 has lower address. */
51917 }
51919 /* Initialize the GCC target structure. */
51920 #undef TARGET_RETURN_IN_MEMORY
51921 #define TARGET_RETURN_IN_MEMORY ix86_return_in_memory
51923 #undef TARGET_LEGITIMIZE_ADDRESS
51924 #define TARGET_LEGITIMIZE_ADDRESS ix86_legitimize_address
51926 #undef TARGET_ATTRIBUTE_TABLE
51927 #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table
51928 #undef TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P
51929 #define TARGET_FUNCTION_ATTRIBUTE_INLINABLE_P hook_bool_const_tree_true
51930 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
51931 # undef TARGET_MERGE_DECL_ATTRIBUTES
51932 # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes
51933 #endif
51935 #undef TARGET_COMP_TYPE_ATTRIBUTES
51936 #define TARGET_COMP_TYPE_ATTRIBUTES ix86_comp_type_attributes
51938 #undef TARGET_INIT_BUILTINS
51939 #define TARGET_INIT_BUILTINS ix86_init_builtins
51940 #undef TARGET_BUILTIN_DECL
51941 #define TARGET_BUILTIN_DECL ix86_builtin_decl
51942 #undef TARGET_EXPAND_BUILTIN
51943 #define TARGET_EXPAND_BUILTIN ix86_expand_builtin
51945 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
51946 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
51947 ix86_builtin_vectorized_function
51949 #undef TARGET_VECTORIZE_BUILTIN_TM_LOAD
51950 #define TARGET_VECTORIZE_BUILTIN_TM_LOAD ix86_builtin_tm_load
51952 #undef TARGET_VECTORIZE_BUILTIN_TM_STORE
51953 #define TARGET_VECTORIZE_BUILTIN_TM_STORE ix86_builtin_tm_store
51955 #undef TARGET_VECTORIZE_BUILTIN_GATHER
51956 #define TARGET_VECTORIZE_BUILTIN_GATHER ix86_vectorize_builtin_gather
51958 #undef TARGET_BUILTIN_RECIPROCAL
51959 #define TARGET_BUILTIN_RECIPROCAL ix86_builtin_reciprocal
51961 #undef TARGET_ASM_FUNCTION_EPILOGUE
51962 #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue
51964 #undef TARGET_ENCODE_SECTION_INFO
51965 #ifndef SUBTARGET_ENCODE_SECTION_INFO
51966 #define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info
51967 #else
51968 #define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO
51969 #endif
51971 #undef TARGET_ASM_OPEN_PAREN
51973 #undef TARGET_ASM_CLOSE_PAREN
51976 #undef TARGET_ASM_BYTE_OP
51977 #define TARGET_ASM_BYTE_OP ASM_BYTE
51979 #undef TARGET_ASM_ALIGNED_HI_OP
51980 #define TARGET_ASM_ALIGNED_HI_OP ASM_SHORT
51981 #undef TARGET_ASM_ALIGNED_SI_OP
51982 #define TARGET_ASM_ALIGNED_SI_OP ASM_LONG
51983 #ifdef ASM_QUAD
51984 #undef TARGET_ASM_ALIGNED_DI_OP
51985 #define TARGET_ASM_ALIGNED_DI_OP ASM_QUAD
51986 #endif
51988 #undef TARGET_PROFILE_BEFORE_PROLOGUE
51989 #define TARGET_PROFILE_BEFORE_PROLOGUE ix86_profile_before_prologue
51991 #undef TARGET_MANGLE_DECL_ASSEMBLER_NAME
51992 #define TARGET_MANGLE_DECL_ASSEMBLER_NAME ix86_mangle_decl_assembler_name
51994 #undef TARGET_ASM_UNALIGNED_HI_OP
51995 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
51996 #undef TARGET_ASM_UNALIGNED_SI_OP
51997 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
51998 #undef TARGET_ASM_UNALIGNED_DI_OP
51999 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
52001 #undef TARGET_PRINT_OPERAND
52002 #define TARGET_PRINT_OPERAND ix86_print_operand
52003 #undef TARGET_PRINT_OPERAND_ADDRESS
52004 #define TARGET_PRINT_OPERAND_ADDRESS ix86_print_operand_address
52005 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
52006 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P ix86_print_operand_punct_valid_p
52007 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
52008 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA i386_asm_output_addr_const_extra
52010 #undef TARGET_SCHED_INIT_GLOBAL
52011 #define TARGET_SCHED_INIT_GLOBAL ix86_sched_init_global
52012 #undef TARGET_SCHED_ADJUST_COST
52013 #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost
52014 #undef TARGET_SCHED_ISSUE_RATE
52015 #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate
52016 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
52017 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
52018 ia32_multipass_dfa_lookahead
52019 #undef TARGET_SCHED_MACRO_FUSION_P
52020 #define TARGET_SCHED_MACRO_FUSION_P ix86_macro_fusion_p
52021 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
52022 #define TARGET_SCHED_MACRO_FUSION_PAIR_P ix86_macro_fusion_pair_p
52024 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
52025 #define TARGET_FUNCTION_OK_FOR_SIBCALL ix86_function_ok_for_sibcall
52027 #undef TARGET_MEMMODEL_CHECK
52028 #define TARGET_MEMMODEL_CHECK ix86_memmodel_check
52030 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
52031 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV ix86_atomic_assign_expand_fenv
52033 #ifdef HAVE_AS_TLS
52034 #undef TARGET_HAVE_TLS
52035 #define TARGET_HAVE_TLS true
52036 #endif
52037 #undef TARGET_CANNOT_FORCE_CONST_MEM
52038 #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem
52039 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
52040 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true
52042 #undef TARGET_DELEGITIMIZE_ADDRESS
52043 #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address
52045 #undef TARGET_MS_BITFIELD_LAYOUT_P
52046 #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p
52048 #if TARGET_MACHO
52049 #undef TARGET_BINDS_LOCAL_P
52050 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
52051 #else
52052 #undef TARGET_BINDS_LOCAL_P
52053 #define TARGET_BINDS_LOCAL_P ix86_binds_local_p
52054 #endif
52055 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
52056 #undef TARGET_BINDS_LOCAL_P
52057 #define TARGET_BINDS_LOCAL_P i386_pe_binds_local_p
52058 #endif
52060 #undef TARGET_ASM_OUTPUT_MI_THUNK
52061 #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk
52062 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
52063 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK x86_can_output_mi_thunk
52065 #undef TARGET_ASM_FILE_START
52066 #define TARGET_ASM_FILE_START x86_file_start
52068 #undef TARGET_OPTION_OVERRIDE
52069 #define TARGET_OPTION_OVERRIDE ix86_option_override
52071 #undef TARGET_REGISTER_MOVE_COST
52072 #define TARGET_REGISTER_MOVE_COST ix86_register_move_cost
52073 #undef TARGET_MEMORY_MOVE_COST
52074 #define TARGET_MEMORY_MOVE_COST ix86_memory_move_cost
52075 #undef TARGET_RTX_COSTS
52076 #define TARGET_RTX_COSTS ix86_rtx_costs
52077 #undef TARGET_ADDRESS_COST
52078 #define TARGET_ADDRESS_COST ix86_address_cost
52080 #undef TARGET_FIXED_CONDITION_CODE_REGS
52081 #define TARGET_FIXED_CONDITION_CODE_REGS ix86_fixed_condition_code_regs
52082 #undef TARGET_CC_MODES_COMPATIBLE
52083 #define TARGET_CC_MODES_COMPATIBLE ix86_cc_modes_compatible
52085 #undef TARGET_MACHINE_DEPENDENT_REORG
52086 #define TARGET_MACHINE_DEPENDENT_REORG ix86_reorg
52088 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE
52089 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE ix86_builtin_setjmp_frame_value
52091 #undef TARGET_BUILD_BUILTIN_VA_LIST
52092 #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list
52094 #undef TARGET_FOLD_BUILTIN
52095 #define TARGET_FOLD_BUILTIN ix86_fold_builtin
52097 #undef TARGET_COMPARE_VERSION_PRIORITY
52098 #define TARGET_COMPARE_VERSION_PRIORITY ix86_compare_version_priority
52100 #undef TARGET_GENERATE_VERSION_DISPATCHER_BODY
52101 #define TARGET_GENERATE_VERSION_DISPATCHER_BODY \
52102 ix86_generate_version_dispatcher_body
52104 #undef TARGET_GET_FUNCTION_VERSIONS_DISPATCHER
52105 #define TARGET_GET_FUNCTION_VERSIONS_DISPATCHER \
52106 ix86_get_function_versions_dispatcher
52108 #undef TARGET_ENUM_VA_LIST_P
52109 #define TARGET_ENUM_VA_LIST_P ix86_enum_va_list
52111 #undef TARGET_FN_ABI_VA_LIST
52112 #define TARGET_FN_ABI_VA_LIST ix86_fn_abi_va_list
52114 #undef TARGET_CANONICAL_VA_LIST_TYPE
52115 #define TARGET_CANONICAL_VA_LIST_TYPE ix86_canonical_va_list_type
52117 #undef TARGET_EXPAND_BUILTIN_VA_START
52118 #define TARGET_EXPAND_BUILTIN_VA_START ix86_va_start
52120 #undef TARGET_MD_ASM_ADJUST
52121 #define TARGET_MD_ASM_ADJUST ix86_md_asm_adjust
52123 #undef TARGET_PROMOTE_PROTOTYPES
52124 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
52125 #undef TARGET_SETUP_INCOMING_VARARGS
52126 #define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs
52127 #undef TARGET_MUST_PASS_IN_STACK
52128 #define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack
52129 #undef TARGET_FUNCTION_ARG_ADVANCE
52130 #define TARGET_FUNCTION_ARG_ADVANCE ix86_function_arg_advance
52131 #undef TARGET_FUNCTION_ARG
52132 #define TARGET_FUNCTION_ARG ix86_function_arg
52133 #undef TARGET_INIT_PIC_REG
52134 #define TARGET_INIT_PIC_REG ix86_init_pic_reg
52135 #undef TARGET_USE_PSEUDO_PIC_REG
52136 #define TARGET_USE_PSEUDO_PIC_REG ix86_use_pseudo_pic_reg
52137 #undef TARGET_FUNCTION_ARG_BOUNDARY
52138 #define TARGET_FUNCTION_ARG_BOUNDARY ix86_function_arg_boundary
52139 #undef TARGET_PASS_BY_REFERENCE
52140 #define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference
52141 #undef TARGET_INTERNAL_ARG_POINTER
52142 #define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer
52143 #undef TARGET_UPDATE_STACK_BOUNDARY
52144 #define TARGET_UPDATE_STACK_BOUNDARY ix86_update_stack_boundary
52145 #undef TARGET_GET_DRAP_RTX
52146 #define TARGET_GET_DRAP_RTX ix86_get_drap_rtx
52147 #undef TARGET_STRICT_ARGUMENT_NAMING
52148 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
52149 #undef TARGET_STATIC_CHAIN
52150 #define TARGET_STATIC_CHAIN ix86_static_chain
52151 #undef TARGET_TRAMPOLINE_INIT
52152 #define TARGET_TRAMPOLINE_INIT ix86_trampoline_init
52153 #undef TARGET_RETURN_POPS_ARGS
52154 #define TARGET_RETURN_POPS_ARGS ix86_return_pops_args
52156 #undef TARGET_LEGITIMATE_COMBINED_INSN
52157 #define TARGET_LEGITIMATE_COMBINED_INSN ix86_legitimate_combined_insn
52159 #undef TARGET_ASAN_SHADOW_OFFSET
52160 #define TARGET_ASAN_SHADOW_OFFSET ix86_asan_shadow_offset
52162 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
52163 #define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg
52165 #undef TARGET_SCALAR_MODE_SUPPORTED_P
52166 #define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
52168 #undef TARGET_VECTOR_MODE_SUPPORTED_P
52169 #define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
52171 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
52172 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
52173 ix86_libgcc_floating_mode_supported_p
52175 #undef TARGET_C_MODE_FOR_SUFFIX
52176 #define TARGET_C_MODE_FOR_SUFFIX ix86_c_mode_for_suffix
52178 #ifdef HAVE_AS_TLS
52179 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
52180 #define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel
52181 #endif
52183 #ifdef SUBTARGET_INSERT_ATTRIBUTES
52184 #undef TARGET_INSERT_ATTRIBUTES
52185 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES
52186 #endif
52188 #undef TARGET_MANGLE_TYPE
52189 #define TARGET_MANGLE_TYPE ix86_mangle_type
52191 #if !TARGET_MACHO
52192 #undef TARGET_STACK_PROTECT_FAIL
52193 #define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail
52194 #endif
52196 #undef TARGET_FUNCTION_VALUE
52197 #define TARGET_FUNCTION_VALUE ix86_function_value
52199 #undef TARGET_FUNCTION_VALUE_REGNO_P
52200 #define TARGET_FUNCTION_VALUE_REGNO_P ix86_function_value_regno_p
52202 #undef TARGET_PROMOTE_FUNCTION_MODE
52203 #define TARGET_PROMOTE_FUNCTION_MODE ix86_promote_function_mode
52205 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
52206 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE ix86_override_options_after_change
52208 #undef TARGET_MEMBER_TYPE_FORCES_BLK
52209 #define TARGET_MEMBER_TYPE_FORCES_BLK ix86_member_type_forces_blk
52211 #undef TARGET_INSTANTIATE_DECLS
52212 #define TARGET_INSTANTIATE_DECLS ix86_instantiate_decls
52214 #undef TARGET_SECONDARY_RELOAD
52215 #define TARGET_SECONDARY_RELOAD ix86_secondary_reload
52217 #undef TARGET_CLASS_MAX_NREGS
52218 #define TARGET_CLASS_MAX_NREGS ix86_class_max_nregs
52220 #undef TARGET_PREFERRED_RELOAD_CLASS
52221 #define TARGET_PREFERRED_RELOAD_CLASS ix86_preferred_reload_class
52222 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS
52223 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS ix86_preferred_output_reload_class
52224 #undef TARGET_CLASS_LIKELY_SPILLED_P
52225 #define TARGET_CLASS_LIKELY_SPILLED_P ix86_class_likely_spilled_p
52227 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
52228 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
52229 ix86_builtin_vectorization_cost
52230 #undef TARGET_VECTORIZE_VEC_PERM_CONST_OK
52231 #define TARGET_VECTORIZE_VEC_PERM_CONST_OK \
52232 ix86_vectorize_vec_perm_const_ok
52233 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
52234 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE \
52235 ix86_preferred_simd_mode
52236 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES
52237 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_SIZES \
52238 ix86_autovectorize_vector_sizes
52239 #undef TARGET_VECTORIZE_INIT_COST
52240 #define TARGET_VECTORIZE_INIT_COST ix86_init_cost
52241 #undef TARGET_VECTORIZE_ADD_STMT_COST
52242 #define TARGET_VECTORIZE_ADD_STMT_COST ix86_add_stmt_cost
52243 #undef TARGET_VECTORIZE_FINISH_COST
52244 #define TARGET_VECTORIZE_FINISH_COST ix86_finish_cost
52245 #undef TARGET_VECTORIZE_DESTROY_COST_DATA
52246 #define TARGET_VECTORIZE_DESTROY_COST_DATA ix86_destroy_cost_data
52248 #undef TARGET_SET_CURRENT_FUNCTION
52249 #define TARGET_SET_CURRENT_FUNCTION ix86_set_current_function
52251 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
52252 #define TARGET_OPTION_VALID_ATTRIBUTE_P ix86_valid_target_attribute_p
52254 #undef TARGET_OPTION_SAVE
52255 #define TARGET_OPTION_SAVE ix86_function_specific_save
52257 #undef TARGET_OPTION_RESTORE
52258 #define TARGET_OPTION_RESTORE ix86_function_specific_restore
52260 #undef TARGET_OPTION_POST_STREAM_IN
52261 #define TARGET_OPTION_POST_STREAM_IN ix86_function_specific_post_stream_in
52263 #undef TARGET_OPTION_PRINT
52264 #define TARGET_OPTION_PRINT ix86_function_specific_print
52266 #undef TARGET_OPTION_FUNCTION_VERSIONS
52267 #define TARGET_OPTION_FUNCTION_VERSIONS ix86_function_versions
52269 #undef TARGET_CAN_INLINE_P
52270 #define TARGET_CAN_INLINE_P ix86_can_inline_p
52272 #undef TARGET_EXPAND_TO_RTL_HOOK
52273 #define TARGET_EXPAND_TO_RTL_HOOK ix86_maybe_switch_abi
52275 #undef TARGET_LEGITIMATE_ADDRESS_P
52276 #define TARGET_LEGITIMATE_ADDRESS_P ix86_legitimate_address_p
52278 #undef TARGET_LRA_P
52279 #define TARGET_LRA_P hook_bool_void_true
52281 #undef TARGET_REGISTER_PRIORITY
52282 #define TARGET_REGISTER_PRIORITY ix86_register_priority
52284 #undef TARGET_REGISTER_USAGE_LEVELING_P
52285 #define TARGET_REGISTER_USAGE_LEVELING_P hook_bool_void_true
52287 #undef TARGET_LEGITIMATE_CONSTANT_P
52288 #define TARGET_LEGITIMATE_CONSTANT_P ix86_legitimate_constant_p
52290 #undef TARGET_FRAME_POINTER_REQUIRED
52291 #define TARGET_FRAME_POINTER_REQUIRED ix86_frame_pointer_required
52293 #undef TARGET_CAN_ELIMINATE
52294 #define TARGET_CAN_ELIMINATE ix86_can_eliminate
52296 #undef TARGET_EXTRA_LIVE_ON_ENTRY
52297 #define TARGET_EXTRA_LIVE_ON_ENTRY ix86_live_on_entry
52299 #undef TARGET_ASM_CODE_END
52300 #define TARGET_ASM_CODE_END ix86_code_end
52302 #undef TARGET_CONDITIONAL_REGISTER_USAGE
52303 #define TARGET_CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage
52305 #if TARGET_MACHO
52306 #undef TARGET_INIT_LIBFUNCS
52307 #define TARGET_INIT_LIBFUNCS darwin_rename_builtins
52308 #endif
52310 #undef TARGET_LOOP_UNROLL_ADJUST
52311 #define TARGET_LOOP_UNROLL_ADJUST ix86_loop_unroll_adjust
52313 #undef TARGET_SPILL_CLASS
52314 #define TARGET_SPILL_CLASS ix86_spill_class
52316 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
52317 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
52318 ix86_simd_clone_compute_vecsize_and_simdlen
52320 #undef TARGET_SIMD_CLONE_ADJUST
52321 #define TARGET_SIMD_CLONE_ADJUST \
52322 ix86_simd_clone_adjust
52324 #undef TARGET_SIMD_CLONE_USABLE
52325 #define TARGET_SIMD_CLONE_USABLE \
52326 ix86_simd_clone_usable
52328 #undef TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P
52329 #define TARGET_FLOAT_EXCEPTIONS_ROUNDING_SUPPORTED_P \
52330 ix86_float_exceptions_rounding_supported_p
52332 #undef TARGET_MODE_EMIT
52333 #define TARGET_MODE_EMIT ix86_emit_mode_set
52335 #undef TARGET_MODE_NEEDED
52336 #define TARGET_MODE_NEEDED ix86_mode_needed
52338 #undef TARGET_MODE_AFTER
52339 #define TARGET_MODE_AFTER ix86_mode_after
52341 #undef TARGET_MODE_ENTRY
52342 #define TARGET_MODE_ENTRY ix86_mode_entry
52344 #undef TARGET_MODE_EXIT
52345 #define TARGET_MODE_EXIT ix86_mode_exit
52347 #undef TARGET_MODE_PRIORITY
52348 #define TARGET_MODE_PRIORITY ix86_mode_priority
52350 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
52351 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
52353 #undef TARGET_LOAD_BOUNDS_FOR_ARG
52354 #define TARGET_LOAD_BOUNDS_FOR_ARG ix86_load_bounds
52356 #undef TARGET_STORE_BOUNDS_FOR_ARG
52357 #define TARGET_STORE_BOUNDS_FOR_ARG ix86_store_bounds
52359 #undef TARGET_LOAD_RETURNED_BOUNDS
52360 #define TARGET_LOAD_RETURNED_BOUNDS ix86_load_returned_bounds
52362 #undef TARGET_STORE_RETURNED_BOUNDS
52363 #define TARGET_STORE_RETURNED_BOUNDS ix86_store_returned_bounds
52365 #undef TARGET_CHKP_BOUND_MODE
52366 #define TARGET_CHKP_BOUND_MODE ix86_mpx_bound_mode
52368 #undef TARGET_BUILTIN_CHKP_FUNCTION
52369 #define TARGET_BUILTIN_CHKP_FUNCTION ix86_builtin_mpx_function
52371 #undef TARGET_CHKP_FUNCTION_VALUE_BOUNDS
52372 #define TARGET_CHKP_FUNCTION_VALUE_BOUNDS ix86_function_value_bounds
52374 #undef TARGET_CHKP_MAKE_BOUNDS_CONSTANT
52375 #define TARGET_CHKP_MAKE_BOUNDS_CONSTANT ix86_make_bounds_constant
52377 #undef TARGET_CHKP_INITIALIZE_BOUNDS
52378 #define TARGET_CHKP_INITIALIZE_BOUNDS ix86_initialize_bounds
52380 #undef TARGET_SETUP_INCOMING_VARARG_BOUNDS
52381 #define TARGET_SETUP_INCOMING_VARARG_BOUNDS ix86_setup_incoming_vararg_bounds
52383 #undef TARGET_OFFLOAD_OPTIONS
52384 #define TARGET_OFFLOAD_OPTIONS \
52385 ix86_offload_options
52387 #undef TARGET_ABSOLUTE_BIGGEST_ALIGNMENT
52388 #define TARGET_ABSOLUTE_BIGGEST_ALIGNMENT 512
52391 \f