1 /* Copyright (C) 1997-2015 Free Software Foundation, Inc.
2 Contributed by Red Hat, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING3. If not see
18 <http://www.gnu.org/licenses/>. */
22 #include "coretypes.h"
27 #include "fold-const.h"
29 #include "stor-layout.h"
30 #include "stringpool.h"
32 #include "hard-reg-set.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "insn-flags.h"
38 #include "insn-attr.h"
52 #include "insn-codes.h"
54 #include "diagnostic-core.h"
56 #include "dominance.h"
62 #include "cfgcleanup.h"
63 #include "basic-block.h"
66 #include "targhooks.h"
67 #include "langhooks.h"
74 #include "target-def.h"
77 #define FRV_INLINE inline
80 /* The maximum number of distinct NOP patterns. There are three:
81 nop, fnop and mnop. */
82 #define NUM_NOP_PATTERNS 3
84 /* Classification of instructions and units: integer, floating-point/media,
85 branch and control. */
86 enum frv_insn_group
{ GROUP_I
, GROUP_FM
, GROUP_B
, GROUP_C
, NUM_GROUPS
};
88 /* The DFA names of the units, in packet order. */
89 static const char *const frv_unit_names
[] =
99 /* The classification of each unit in frv_unit_names[]. */
100 static const enum frv_insn_group frv_unit_groups
[ARRAY_SIZE (frv_unit_names
)] =
110 /* Return the DFA unit code associated with the Nth unit of integer
111 or floating-point group GROUP, */
112 #define NTH_UNIT(GROUP, N) frv_unit_codes[(GROUP) + (N) * 2 + 1]
114 /* Return the number of integer or floating-point unit UNIT
115 (1 for I1, 2 for F2, etc.). */
116 #define UNIT_NUMBER(UNIT) (((UNIT) - 1) / 2)
118 /* The DFA unit number for each unit in frv_unit_names[]. */
119 static int frv_unit_codes
[ARRAY_SIZE (frv_unit_names
)];
121 /* FRV_TYPE_TO_UNIT[T] is the last unit in frv_unit_names[] that can issue
122 an instruction of type T. The value is ARRAY_SIZE (frv_unit_names) if
123 no instruction of type T has been seen. */
124 static unsigned int frv_type_to_unit
[TYPE_UNKNOWN
+ 1];
126 /* An array of dummy nop INSNs, one for each type of nop that the
128 static GTY(()) rtx_insn
*frv_nops
[NUM_NOP_PATTERNS
];
130 /* The number of nop instructions in frv_nops[]. */
131 static unsigned int frv_num_nops
;
133 /* The type of access. FRV_IO_UNKNOWN means the access can be either
134 a read or a write. */
135 enum frv_io_type
{ FRV_IO_UNKNOWN
, FRV_IO_READ
, FRV_IO_WRITE
};
137 /* Information about one __builtin_read or __builtin_write access, or
138 the combination of several such accesses. The most general value
139 is all-zeros (an unknown access to an unknown address). */
141 enum frv_io_type type
;
143 /* The constant address being accessed, or zero if not known. */
144 HOST_WIDE_INT const_address
;
146 /* The run-time address, as used in operand 0 of the membar pattern. */
150 /* Return true if instruction INSN should be packed with the following
152 #define PACKING_FLAG_P(INSN) (GET_MODE (INSN) == TImode)
154 /* Set the value of PACKING_FLAG_P(INSN). */
155 #define SET_PACKING_FLAG(INSN) PUT_MODE (INSN, TImode)
156 #define CLEAR_PACKING_FLAG(INSN) PUT_MODE (INSN, VOIDmode)
158 /* Loop with REG set to each hard register in rtx X. */
159 #define FOR_EACH_REGNO(REG, X) \
160 for (REG = REGNO (X); \
161 REG < REGNO (X) + HARD_REGNO_NREGS (REGNO (X), GET_MODE (X)); \
164 /* This structure contains machine specific function data. */
165 struct GTY(()) machine_function
167 /* True if we have created an rtx that relies on the stack frame. */
170 /* True if this function contains at least one __builtin_{read,write}*. */
174 /* Temporary register allocation support structure. */
175 typedef struct frv_tmp_reg_struct
177 HARD_REG_SET regs
; /* possible registers to allocate */
178 int next_reg
[N_REG_CLASSES
]; /* next register to allocate per class */
182 /* Register state information for VLIW re-packing phase. */
183 #define REGSTATE_CC_MASK 0x07 /* Mask to isolate CCn for cond exec */
184 #define REGSTATE_MODIFIED 0x08 /* reg modified in current VLIW insn */
185 #define REGSTATE_IF_TRUE 0x10 /* reg modified in cond exec true */
186 #define REGSTATE_IF_FALSE 0x20 /* reg modified in cond exec false */
188 #define REGSTATE_IF_EITHER (REGSTATE_IF_TRUE | REGSTATE_IF_FALSE)
190 typedef unsigned char regstate_t
;
192 /* Used in frv_frame_accessor_t to indicate the direction of a register-to-
200 /* Information required by frv_frame_access. */
203 /* This field is FRV_LOAD if registers are to be loaded from the stack and
204 FRV_STORE if they should be stored onto the stack. FRV_STORE implies
205 the move is being done by the prologue code while FRV_LOAD implies it
206 is being done by the epilogue. */
207 enum frv_stack_op op
;
209 /* The base register to use when accessing the stack. This may be the
210 frame pointer, stack pointer, or a temporary. The choice of register
211 depends on which part of the frame is being accessed and how big the
215 /* The offset of BASE from the bottom of the current frame, in bytes. */
217 } frv_frame_accessor_t
;
219 /* Conditional execution support gathered together in one structure. */
222 /* Linked list of insns to add if the conditional execution conversion was
223 successful. Each link points to an EXPR_LIST which points to the pattern
224 of the insn to add, and the insn to be inserted before. */
225 rtx added_insns_list
;
227 /* Identify which registers are safe to allocate for if conversions to
228 conditional execution. We keep the last allocated register in the
229 register classes between COND_EXEC statements. This will mean we allocate
230 different registers for each different COND_EXEC group if we can. This
231 might allow the scheduler to intermix two different COND_EXEC sections. */
232 frv_tmp_reg_t tmp_reg
;
234 /* For nested IFs, identify which CC registers are used outside of setting
235 via a compare isnsn, and using via a check insn. This will allow us to
236 know if we can rewrite the register to use a different register that will
237 be paired with the CR register controlling the nested IF-THEN blocks. */
238 HARD_REG_SET nested_cc_ok_rewrite
;
240 /* Temporary registers allocated to hold constants during conditional
242 rtx scratch_regs
[FIRST_PSEUDO_REGISTER
];
244 /* Current number of temp registers available. */
245 int cur_scratch_regs
;
247 /* Number of nested conditional execution blocks. */
248 int num_nested_cond_exec
;
250 /* Map of insns that set up constants in scratch registers. */
251 bitmap scratch_insns_bitmap
;
253 /* Conditional execution test register (CC0..CC7). */
256 /* Conditional execution compare register that is paired with cr_reg, so that
257 nested compares can be done. The csubcc and caddcc instructions don't
258 have enough bits to specify both a CC register to be set and a CR register
259 to do the test on, so the same bit number is used for both. Needless to
260 say, this is rather inconvenient for GCC. */
263 /* Extra CR registers used for &&, ||. */
267 /* Previous CR used in nested if, to make sure we are dealing with the same
268 nested if as the previous statement. */
269 rtx last_nested_if_cr
;
273 static /* GTY(()) */ frv_ifcvt_t frv_ifcvt
;
275 /* Map register number to smallest register class. */
276 enum reg_class regno_reg_class
[FIRST_PSEUDO_REGISTER
];
278 /* Cached value of frv_stack_info. */
279 static frv_stack_t
*frv_stack_cache
= (frv_stack_t
*)0;
281 /* Forward references */
283 static void frv_option_override (void);
284 static bool frv_legitimate_address_p (machine_mode
, rtx
, bool);
285 static int frv_default_flags_for_cpu (void);
286 static int frv_string_begins_with (const char *, const char *);
287 static FRV_INLINE
bool frv_small_data_reloc_p (rtx
, int);
288 static void frv_print_operand (FILE *, rtx
, int);
289 static void frv_print_operand_address (FILE *, rtx
);
290 static bool frv_print_operand_punct_valid_p (unsigned char code
);
291 static void frv_print_operand_memory_reference_reg
293 static void frv_print_operand_memory_reference (FILE *, rtx
, int);
294 static int frv_print_operand_jump_hint (rtx_insn
*);
295 static const char *comparison_string (enum rtx_code
, rtx
);
296 static rtx
frv_function_value (const_tree
, const_tree
,
298 static rtx
frv_libcall_value (machine_mode
,
300 static FRV_INLINE
int frv_regno_ok_for_base_p (int, int);
301 static rtx
single_set_pattern (rtx
);
302 static int frv_function_contains_far_jump (void);
303 static rtx
frv_alloc_temp_reg (frv_tmp_reg_t
*,
307 static rtx
frv_frame_offset_rtx (int);
308 static rtx
frv_frame_mem (machine_mode
, rtx
, int);
309 static rtx
frv_dwarf_store (rtx
, int);
310 static void frv_frame_insn (rtx
, rtx
);
311 static void frv_frame_access (frv_frame_accessor_t
*,
313 static void frv_frame_access_multi (frv_frame_accessor_t
*,
315 static void frv_frame_access_standard_regs (enum frv_stack_op
,
317 static struct machine_function
*frv_init_machine_status (void);
318 static rtx
frv_int_to_acc (enum insn_code
, int, rtx
);
319 static machine_mode
frv_matching_accg_mode (machine_mode
);
320 static rtx
frv_read_argument (tree
, unsigned int);
321 static rtx
frv_read_iacc_argument (machine_mode
, tree
, unsigned int);
322 static int frv_check_constant_argument (enum insn_code
, int, rtx
);
323 static rtx
frv_legitimize_target (enum insn_code
, rtx
);
324 static rtx
frv_legitimize_argument (enum insn_code
, int, rtx
);
325 static rtx
frv_legitimize_tls_address (rtx
, enum tls_model
);
326 static rtx
frv_legitimize_address (rtx
, rtx
, machine_mode
);
327 static rtx
frv_expand_set_builtin (enum insn_code
, tree
, rtx
);
328 static rtx
frv_expand_unop_builtin (enum insn_code
, tree
, rtx
);
329 static rtx
frv_expand_binop_builtin (enum insn_code
, tree
, rtx
);
330 static rtx
frv_expand_cut_builtin (enum insn_code
, tree
, rtx
);
331 static rtx
frv_expand_binopimm_builtin (enum insn_code
, tree
, rtx
);
332 static rtx
frv_expand_voidbinop_builtin (enum insn_code
, tree
);
333 static rtx
frv_expand_int_void2arg (enum insn_code
, tree
);
334 static rtx
frv_expand_prefetches (enum insn_code
, tree
);
335 static rtx
frv_expand_voidtriop_builtin (enum insn_code
, tree
);
336 static rtx
frv_expand_voidaccop_builtin (enum insn_code
, tree
);
337 static rtx
frv_expand_mclracc_builtin (tree
);
338 static rtx
frv_expand_mrdacc_builtin (enum insn_code
, tree
);
339 static rtx
frv_expand_mwtacc_builtin (enum insn_code
, tree
);
340 static rtx
frv_expand_noargs_builtin (enum insn_code
);
341 static void frv_split_iacc_move (rtx
, rtx
);
342 static rtx
frv_emit_comparison (enum rtx_code
, rtx
, rtx
);
343 static void frv_ifcvt_add_insn (rtx
, rtx
, int);
344 static rtx
frv_ifcvt_rewrite_mem (rtx
, machine_mode
, rtx
);
345 static rtx
frv_ifcvt_load_value (rtx
, rtx
);
346 static unsigned int frv_insn_unit (rtx_insn
*);
347 static bool frv_issues_to_branch_unit_p (rtx_insn
*);
348 static int frv_cond_flags (rtx
);
349 static bool frv_regstate_conflict_p (regstate_t
, regstate_t
);
350 static bool frv_registers_conflict_p (rtx
);
351 static void frv_registers_update_1 (rtx
, const_rtx
, void *);
352 static void frv_registers_update (rtx
);
353 static void frv_start_packet (void);
354 static void frv_start_packet_block (void);
355 static void frv_finish_packet (void (*) (void));
356 static bool frv_pack_insn_p (rtx_insn
*);
357 static void frv_add_insn_to_packet (rtx_insn
*);
358 static void frv_insert_nop_in_packet (rtx_insn
*);
359 static bool frv_for_each_packet (void (*) (void));
360 static bool frv_sort_insn_group_1 (enum frv_insn_group
,
361 unsigned int, unsigned int,
362 unsigned int, unsigned int,
364 static int frv_compare_insns (const void *, const void *);
365 static void frv_sort_insn_group (enum frv_insn_group
);
366 static void frv_reorder_packet (void);
367 static void frv_fill_unused_units (enum frv_insn_group
);
368 static void frv_align_label (void);
369 static void frv_reorg_packet (void);
370 static void frv_register_nop (rtx
);
371 static void frv_reorg (void);
372 static void frv_pack_insns (void);
373 static void frv_function_prologue (FILE *, HOST_WIDE_INT
);
374 static void frv_function_epilogue (FILE *, HOST_WIDE_INT
);
375 static bool frv_assemble_integer (rtx
, unsigned, int);
376 static void frv_init_builtins (void);
377 static rtx
frv_expand_builtin (tree
, rtx
, rtx
, machine_mode
, int);
378 static void frv_init_libfuncs (void);
379 static bool frv_in_small_data_p (const_tree
);
380 static void frv_asm_output_mi_thunk
381 (FILE *, tree
, HOST_WIDE_INT
, HOST_WIDE_INT
, tree
);
382 static void frv_setup_incoming_varargs (cumulative_args_t
,
385 static rtx
frv_expand_builtin_saveregs (void);
386 static void frv_expand_builtin_va_start (tree
, rtx
);
387 static bool frv_rtx_costs (rtx
, int, int, int, int*,
389 static int frv_register_move_cost (machine_mode
,
390 reg_class_t
, reg_class_t
);
391 static int frv_memory_move_cost (machine_mode
,
393 static void frv_asm_out_constructor (rtx
, int);
394 static void frv_asm_out_destructor (rtx
, int);
395 static bool frv_function_symbol_referenced_p (rtx
);
396 static bool frv_legitimate_constant_p (machine_mode
, rtx
);
397 static bool frv_cannot_force_const_mem (machine_mode
, rtx
);
398 static const char *unspec_got_name (int);
399 static void frv_output_const_unspec (FILE *,
400 const struct frv_unspec
*);
401 static bool frv_function_ok_for_sibcall (tree
, tree
);
402 static rtx
frv_struct_value_rtx (tree
, int);
403 static bool frv_must_pass_in_stack (machine_mode mode
, const_tree type
);
404 static int frv_arg_partial_bytes (cumulative_args_t
, machine_mode
,
406 static rtx
frv_function_arg (cumulative_args_t
, machine_mode
,
408 static rtx
frv_function_incoming_arg (cumulative_args_t
, machine_mode
,
410 static void frv_function_arg_advance (cumulative_args_t
, machine_mode
,
412 static unsigned int frv_function_arg_boundary (machine_mode
,
414 static void frv_output_dwarf_dtprel (FILE *, int, rtx
)
416 static reg_class_t
frv_secondary_reload (bool, rtx
, reg_class_t
,
418 secondary_reload_info
*);
419 static bool frv_frame_pointer_required (void);
420 static bool frv_can_eliminate (const int, const int);
421 static void frv_conditional_register_usage (void);
422 static void frv_trampoline_init (rtx
, tree
, rtx
);
423 static bool frv_class_likely_spilled_p (reg_class_t
);
425 /* Initialize the GCC target structure. */
426 #undef TARGET_PRINT_OPERAND
427 #define TARGET_PRINT_OPERAND frv_print_operand
428 #undef TARGET_PRINT_OPERAND_ADDRESS
429 #define TARGET_PRINT_OPERAND_ADDRESS frv_print_operand_address
430 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
431 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P frv_print_operand_punct_valid_p
432 #undef TARGET_ASM_FUNCTION_PROLOGUE
433 #define TARGET_ASM_FUNCTION_PROLOGUE frv_function_prologue
434 #undef TARGET_ASM_FUNCTION_EPILOGUE
435 #define TARGET_ASM_FUNCTION_EPILOGUE frv_function_epilogue
436 #undef TARGET_ASM_INTEGER
437 #define TARGET_ASM_INTEGER frv_assemble_integer
438 #undef TARGET_OPTION_OVERRIDE
439 #define TARGET_OPTION_OVERRIDE frv_option_override
440 #undef TARGET_INIT_BUILTINS
441 #define TARGET_INIT_BUILTINS frv_init_builtins
442 #undef TARGET_EXPAND_BUILTIN
443 #define TARGET_EXPAND_BUILTIN frv_expand_builtin
444 #undef TARGET_INIT_LIBFUNCS
445 #define TARGET_INIT_LIBFUNCS frv_init_libfuncs
446 #undef TARGET_IN_SMALL_DATA_P
447 #define TARGET_IN_SMALL_DATA_P frv_in_small_data_p
448 #undef TARGET_REGISTER_MOVE_COST
449 #define TARGET_REGISTER_MOVE_COST frv_register_move_cost
450 #undef TARGET_MEMORY_MOVE_COST
451 #define TARGET_MEMORY_MOVE_COST frv_memory_move_cost
452 #undef TARGET_RTX_COSTS
453 #define TARGET_RTX_COSTS frv_rtx_costs
454 #undef TARGET_ASM_CONSTRUCTOR
455 #define TARGET_ASM_CONSTRUCTOR frv_asm_out_constructor
456 #undef TARGET_ASM_DESTRUCTOR
457 #define TARGET_ASM_DESTRUCTOR frv_asm_out_destructor
459 #undef TARGET_ASM_OUTPUT_MI_THUNK
460 #define TARGET_ASM_OUTPUT_MI_THUNK frv_asm_output_mi_thunk
461 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
462 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
464 #undef TARGET_SCHED_ISSUE_RATE
465 #define TARGET_SCHED_ISSUE_RATE frv_issue_rate
467 #undef TARGET_LEGITIMIZE_ADDRESS
468 #define TARGET_LEGITIMIZE_ADDRESS frv_legitimize_address
470 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
471 #define TARGET_FUNCTION_OK_FOR_SIBCALL frv_function_ok_for_sibcall
472 #undef TARGET_LEGITIMATE_CONSTANT_P
473 #define TARGET_LEGITIMATE_CONSTANT_P frv_legitimate_constant_p
474 #undef TARGET_CANNOT_FORCE_CONST_MEM
475 #define TARGET_CANNOT_FORCE_CONST_MEM frv_cannot_force_const_mem
477 #undef TARGET_HAVE_TLS
478 #define TARGET_HAVE_TLS HAVE_AS_TLS
480 #undef TARGET_STRUCT_VALUE_RTX
481 #define TARGET_STRUCT_VALUE_RTX frv_struct_value_rtx
482 #undef TARGET_MUST_PASS_IN_STACK
483 #define TARGET_MUST_PASS_IN_STACK frv_must_pass_in_stack
484 #undef TARGET_PASS_BY_REFERENCE
485 #define TARGET_PASS_BY_REFERENCE hook_pass_by_reference_must_pass_in_stack
486 #undef TARGET_ARG_PARTIAL_BYTES
487 #define TARGET_ARG_PARTIAL_BYTES frv_arg_partial_bytes
488 #undef TARGET_FUNCTION_ARG
489 #define TARGET_FUNCTION_ARG frv_function_arg
490 #undef TARGET_FUNCTION_INCOMING_ARG
491 #define TARGET_FUNCTION_INCOMING_ARG frv_function_incoming_arg
492 #undef TARGET_FUNCTION_ARG_ADVANCE
493 #define TARGET_FUNCTION_ARG_ADVANCE frv_function_arg_advance
494 #undef TARGET_FUNCTION_ARG_BOUNDARY
495 #define TARGET_FUNCTION_ARG_BOUNDARY frv_function_arg_boundary
497 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
498 #define TARGET_EXPAND_BUILTIN_SAVEREGS frv_expand_builtin_saveregs
499 #undef TARGET_SETUP_INCOMING_VARARGS
500 #define TARGET_SETUP_INCOMING_VARARGS frv_setup_incoming_varargs
501 #undef TARGET_MACHINE_DEPENDENT_REORG
502 #define TARGET_MACHINE_DEPENDENT_REORG frv_reorg
504 #undef TARGET_EXPAND_BUILTIN_VA_START
505 #define TARGET_EXPAND_BUILTIN_VA_START frv_expand_builtin_va_start
508 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
509 #define TARGET_ASM_OUTPUT_DWARF_DTPREL frv_output_dwarf_dtprel
512 #undef TARGET_CLASS_LIKELY_SPILLED_P
513 #define TARGET_CLASS_LIKELY_SPILLED_P frv_class_likely_spilled_p
515 #undef TARGET_SECONDARY_RELOAD
516 #define TARGET_SECONDARY_RELOAD frv_secondary_reload
518 #undef TARGET_LEGITIMATE_ADDRESS_P
519 #define TARGET_LEGITIMATE_ADDRESS_P frv_legitimate_address_p
521 #undef TARGET_FRAME_POINTER_REQUIRED
522 #define TARGET_FRAME_POINTER_REQUIRED frv_frame_pointer_required
524 #undef TARGET_CAN_ELIMINATE
525 #define TARGET_CAN_ELIMINATE frv_can_eliminate
527 #undef TARGET_CONDITIONAL_REGISTER_USAGE
528 #define TARGET_CONDITIONAL_REGISTER_USAGE frv_conditional_register_usage
530 #undef TARGET_TRAMPOLINE_INIT
531 #define TARGET_TRAMPOLINE_INIT frv_trampoline_init
533 #undef TARGET_FUNCTION_VALUE
534 #define TARGET_FUNCTION_VALUE frv_function_value
535 #undef TARGET_LIBCALL_VALUE
536 #define TARGET_LIBCALL_VALUE frv_libcall_value
538 struct gcc_target targetm
= TARGET_INITIALIZER
;
540 #define FRV_SYMBOL_REF_TLS_P(RTX) \
541 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
544 /* Any function call that satisfies the machine-independent
545 requirements is eligible on FR-V. */
548 frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED
,
549 tree exp ATTRIBUTE_UNUSED
)
554 /* Return true if SYMBOL is a small data symbol and relocation RELOC
555 can be used to access it directly in a load or store. */
557 static FRV_INLINE
bool
558 frv_small_data_reloc_p (rtx symbol
, int reloc
)
560 return (GET_CODE (symbol
) == SYMBOL_REF
561 && SYMBOL_REF_SMALL_P (symbol
)
562 && (!TARGET_FDPIC
|| flag_pic
== 1)
563 && (reloc
== R_FRV_GOTOFF12
|| reloc
== R_FRV_GPREL12
));
566 /* Return true if X is a valid relocation unspec. If it is, fill in UNSPEC
570 frv_const_unspec_p (rtx x
, struct frv_unspec
*unspec
)
572 if (GET_CODE (x
) == CONST
)
576 if (GET_CODE (x
) == PLUS
&& GET_CODE (XEXP (x
, 1)) == CONST_INT
)
578 unspec
->offset
+= INTVAL (XEXP (x
, 1));
581 if (GET_CODE (x
) == UNSPEC
&& XINT (x
, 1) == UNSPEC_GOT
)
583 unspec
->symbol
= XVECEXP (x
, 0, 0);
584 unspec
->reloc
= INTVAL (XVECEXP (x
, 0, 1));
586 if (unspec
->offset
== 0)
589 if (frv_small_data_reloc_p (unspec
->symbol
, unspec
->reloc
)
590 && unspec
->offset
> 0
591 && unspec
->offset
< g_switch_value
)
598 /* Decide whether we can force certain constants to memory. If we
599 decide we can't, the caller should be able to cope with it in
602 We never allow constants to be forced into memory for TARGET_FDPIC.
603 This is necessary for several reasons:
605 1. Since frv_legitimate_constant_p rejects constant pool addresses, the
606 target-independent code will try to force them into the constant
607 pool, thus leading to infinite recursion.
609 2. We can never introduce new constant pool references during reload.
610 Any such reference would require use of the pseudo FDPIC register.
612 3. We can't represent a constant added to a function pointer (which is
613 not the same as a pointer to a function+constant).
615 4. In many cases, it's more efficient to calculate the constant in-line. */
618 frv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED
,
619 rtx x ATTRIBUTE_UNUSED
)
625 frv_default_flags_for_cpu (void)
627 switch (frv_cpu_type
)
629 case FRV_CPU_GENERIC
:
630 return MASK_DEFAULT_FRV
;
633 return MASK_DEFAULT_FR550
;
637 return MASK_DEFAULT_FR500
;
640 return MASK_DEFAULT_FR450
;
644 return MASK_DEFAULT_FR400
;
648 return MASK_DEFAULT_SIMPLE
;
655 /* Implement TARGET_OPTION_OVERRIDE. */
658 frv_option_override (void)
663 target_flags
|= (frv_default_flags_for_cpu () & ~target_flags_explicit
);
665 /* -mlibrary-pic sets -fPIC and -G0 and also suppresses warnings from the
666 linker about linking pic and non-pic code. */
669 if (!flag_pic
) /* -fPIC */
672 if (!global_options_set
.x_g_switch_value
) /* -G0 */
678 /* A C expression whose value is a register class containing hard
679 register REGNO. In general there is more than one such class;
680 choose a class which is "minimal", meaning that no smaller class
681 also contains the register. */
683 for (regno
= 0; regno
< FIRST_PSEUDO_REGISTER
; regno
++)
685 enum reg_class rclass
;
689 int gpr_reg
= regno
- GPR_FIRST
;
691 if (gpr_reg
== GR8_REG
)
694 else if (gpr_reg
== GR9_REG
)
697 else if (gpr_reg
== GR14_REG
)
698 rclass
= FDPIC_FPTR_REGS
;
700 else if (gpr_reg
== FDPIC_REGNO
)
703 else if ((gpr_reg
& 3) == 0)
706 else if ((gpr_reg
& 1) == 0)
713 else if (FPR_P (regno
))
715 int fpr_reg
= regno
- GPR_FIRST
;
716 if ((fpr_reg
& 3) == 0)
717 rclass
= QUAD_FPR_REGS
;
719 else if ((fpr_reg
& 1) == 0)
726 else if (regno
== LR_REGNO
)
729 else if (regno
== LCR_REGNO
)
732 else if (ICC_P (regno
))
735 else if (FCC_P (regno
))
738 else if (ICR_P (regno
))
741 else if (FCR_P (regno
))
744 else if (ACC_P (regno
))
746 int r
= regno
- ACC_FIRST
;
748 rclass
= QUAD_ACC_REGS
;
749 else if ((r
& 1) == 0)
750 rclass
= EVEN_ACC_REGS
;
755 else if (ACCG_P (regno
))
761 regno_reg_class
[regno
] = rclass
;
764 /* Check for small data option */
765 if (!global_options_set
.x_g_switch_value
&& !TARGET_LIBPIC
)
766 g_switch_value
= SDATA_DEFAULT_SIZE
;
768 /* There is no single unaligned SI op for PIC code. Sometimes we
769 need to use ".4byte" and sometimes we need to use ".picptr".
770 See frv_assemble_integer for details. */
771 if (flag_pic
|| TARGET_FDPIC
)
772 targetm
.asm_out
.unaligned_op
.si
= 0;
774 if ((target_flags_explicit
& MASK_LINKED_FP
) == 0)
775 target_flags
|= MASK_LINKED_FP
;
777 if ((target_flags_explicit
& MASK_OPTIMIZE_MEMBAR
) == 0)
778 target_flags
|= MASK_OPTIMIZE_MEMBAR
;
780 for (i
= 0; i
< ARRAY_SIZE (frv_unit_names
); i
++)
781 frv_unit_codes
[i
] = get_cpu_unit_code (frv_unit_names
[i
]);
783 for (i
= 0; i
< ARRAY_SIZE (frv_type_to_unit
); i
++)
784 frv_type_to_unit
[i
] = ARRAY_SIZE (frv_unit_codes
);
786 init_machine_status
= frv_init_machine_status
;
790 /* Return true if NAME (a STRING_CST node) begins with PREFIX. */
793 frv_string_begins_with (const char *name
, const char *prefix
)
795 const int prefix_len
= strlen (prefix
);
797 /* Remember: NAME's length includes the null terminator. */
798 return (strncmp (name
, prefix
, prefix_len
) == 0);
801 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */
804 frv_conditional_register_usage (void)
808 for (i
= GPR_FIRST
+ NUM_GPRS
; i
<= GPR_LAST
; i
++)
809 fixed_regs
[i
] = call_used_regs
[i
] = 1;
811 for (i
= FPR_FIRST
+ NUM_FPRS
; i
<= FPR_LAST
; i
++)
812 fixed_regs
[i
] = call_used_regs
[i
] = 1;
814 /* Reserve the registers used for conditional execution. At present, we need
815 1 ICC and 1 ICR register. */
816 fixed_regs
[ICC_TEMP
] = call_used_regs
[ICC_TEMP
] = 1;
817 fixed_regs
[ICR_TEMP
] = call_used_regs
[ICR_TEMP
] = 1;
821 fixed_regs
[ICC_FIRST
] = call_used_regs
[ICC_FIRST
] = 1;
822 fixed_regs
[FCC_FIRST
] = call_used_regs
[FCC_FIRST
] = 1;
823 fixed_regs
[ICR_FIRST
] = call_used_regs
[ICR_FIRST
] = 1;
824 fixed_regs
[FCR_FIRST
] = call_used_regs
[FCR_FIRST
] = 1;
828 fixed_regs
[GPR_FIRST
+ 16] = fixed_regs
[GPR_FIRST
+ 17] =
829 call_used_regs
[GPR_FIRST
+ 16] = call_used_regs
[GPR_FIRST
+ 17] = 0;
832 /* If -fpic, SDA_BASE_REG is the PIC register. */
833 if (g_switch_value
== 0 && !flag_pic
)
834 fixed_regs
[SDA_BASE_REG
] = call_used_regs
[SDA_BASE_REG
] = 0;
837 fixed_regs
[PIC_REGNO
] = call_used_regs
[PIC_REGNO
] = 0;
843 * Compute the stack frame layout
846 * +---------------+-----------------------+-----------------------+
847 * |Register |type |caller-save/callee-save|
848 * +---------------+-----------------------+-----------------------+
849 * |GR0 |Zero register | - |
850 * |GR1 |Stack pointer(SP) | - |
851 * |GR2 |Frame pointer(FP) | - |
852 * |GR3 |Hidden parameter | caller save |
853 * |GR4-GR7 | - | caller save |
854 * |GR8-GR13 |Argument register | caller save |
855 * |GR14-GR15 | - | caller save |
856 * |GR16-GR31 | - | callee save |
857 * |GR32-GR47 | - | caller save |
858 * |GR48-GR63 | - | callee save |
859 * |FR0-FR15 | - | caller save |
860 * |FR16-FR31 | - | callee save |
861 * |FR32-FR47 | - | caller save |
862 * |FR48-FR63 | - | callee save |
863 * +---------------+-----------------------+-----------------------+
867 * SP-> |-----------------------------------|
869 * |-----------------------------------|
870 * | Register save area |
871 * |-----------------------------------|
872 * | Local variable save area |
873 * FP-> |-----------------------------------|
875 * |-----------------------------------|
876 * | Hidden parameter save area |
877 * |-----------------------------------|
878 * | Return address(LR) storage area |
879 * |-----------------------------------|
880 * | Padding for alignment |
881 * |-----------------------------------|
882 * | Register argument area |
883 * OLD SP-> |-----------------------------------|
885 * |-----------------------------------|
888 * Argument area/Parameter area:
890 * When a function is called, this area is used for argument transfer. When
891 * the argument is set up by the caller function, this area is referred to as
892 * the argument area. When the argument is referenced by the callee function,
893 * this area is referred to as the parameter area. The area is allocated when
894 * all arguments cannot be placed on the argument register at the time of
897 * Register save area:
899 * This is a register save area that must be guaranteed for the caller
900 * function. This area is not secured when the register save operation is not
903 * Local variable save area:
905 * This is the area for local variables and temporary variables.
909 * This area stores the FP value of the caller function.
911 * Hidden parameter save area:
913 * This area stores the start address of the return value storage
914 * area for a struct/union return function.
915 * When a struct/union is used as the return value, the caller
916 * function stores the return value storage area start address in
917 * register GR3 and passes it to the caller function.
918 * The callee function interprets the address stored in the GR3
919 * as the return value storage area start address.
920 * When register GR3 needs to be saved into memory, the callee
921 * function saves it in the hidden parameter save area. This
922 * area is not secured when the save operation is not needed.
924 * Return address(LR) storage area:
926 * This area saves the LR. The LR stores the address of a return to the caller
927 * function for the purpose of function calling.
929 * Argument register area:
931 * This area saves the argument register. This area is not secured when the
932 * save operation is not needed.
936 * Arguments, the count of which equals the count of argument registers (6
937 * words), are positioned in registers GR8 to GR13 and delivered to the callee
938 * function. When a struct/union return function is called, the return value
939 * area address is stored in register GR3. Arguments not placed in the
940 * argument registers will be stored in the stack argument area for transfer
941 * purposes. When an 8-byte type argument is to be delivered using registers,
942 * it is divided into two and placed in two registers for transfer. When
943 * argument registers must be saved to memory, the callee function secures an
944 * argument register save area in the stack. In this case, a continuous
945 * argument register save area must be established in the parameter area. The
946 * argument register save area must be allocated as needed to cover the size of
947 * the argument register to be saved. If the function has a variable count of
948 * arguments, it saves all argument registers in the argument register save
951 * Argument Extension Format:
953 * When an argument is to be stored in the stack, its type is converted to an
954 * extended type in accordance with the individual argument type. The argument
955 * is freed by the caller function after the return from the callee function is
958 * +-----------------------+---------------+------------------------+
959 * | Argument Type |Extended Type |Stack Storage Size(byte)|
960 * +-----------------------+---------------+------------------------+
962 * |signed char |int | 4 |
963 * |unsigned char |int | 4 |
964 * |[signed] short int |int | 4 |
965 * |unsigned short int |int | 4 |
966 * |[signed] int |No extension | 4 |
967 * |unsigned int |No extension | 4 |
968 * |[signed] long int |No extension | 4 |
969 * |unsigned long int |No extension | 4 |
970 * |[signed] long long int |No extension | 8 |
971 * |unsigned long long int |No extension | 8 |
972 * |float |double | 8 |
973 * |double |No extension | 8 |
974 * |long double |No extension | 8 |
975 * |pointer |No extension | 4 |
976 * |struct/union |- | 4 (*1) |
977 * +-----------------------+---------------+------------------------+
979 * When a struct/union is to be delivered as an argument, the caller copies it
980 * to the local variable area and delivers the address of that area.
984 * +-------------------------------+----------------------+
985 * |Return Value Type |Return Value Interface|
986 * +-------------------------------+----------------------+
988 * |[signed|unsigned] char |GR8 |
989 * |[signed|unsigned] short int |GR8 |
990 * |[signed|unsigned] int |GR8 |
991 * |[signed|unsigned] long int |GR8 |
993 * |[signed|unsigned] long long int|GR8 & GR9 |
995 * |double |GR8 & GR9 |
996 * |long double |GR8 & GR9 |
997 * |struct/union |(*1) |
998 * +-------------------------------+----------------------+
1000 * When a struct/union is used as the return value, the caller function stores
1001 * the start address of the return value storage area into GR3 and then passes
1002 * it to the callee function. The callee function interprets GR3 as the start
1003 * address of the return value storage area. When this address needs to be
1004 * saved in memory, the callee function secures the hidden parameter save area
1005 * and saves the address in that area.
1009 frv_stack_info (void)
1011 static frv_stack_t info
, zero_info
;
1012 frv_stack_t
*info_ptr
= &info
;
1013 tree fndecl
= current_function_decl
;
1021 /* If we've already calculated the values and reload is complete,
1023 if (frv_stack_cache
)
1024 return frv_stack_cache
;
1026 /* Zero all fields. */
1029 /* Set up the register range information. */
1030 info_ptr
->regs
[STACK_REGS_GPR
].name
= "gpr";
1031 info_ptr
->regs
[STACK_REGS_GPR
].first
= LAST_ARG_REGNUM
+ 1;
1032 info_ptr
->regs
[STACK_REGS_GPR
].last
= GPR_LAST
;
1033 info_ptr
->regs
[STACK_REGS_GPR
].dword_p
= TRUE
;
1035 info_ptr
->regs
[STACK_REGS_FPR
].name
= "fpr";
1036 info_ptr
->regs
[STACK_REGS_FPR
].first
= FPR_FIRST
;
1037 info_ptr
->regs
[STACK_REGS_FPR
].last
= FPR_LAST
;
1038 info_ptr
->regs
[STACK_REGS_FPR
].dword_p
= TRUE
;
1040 info_ptr
->regs
[STACK_REGS_LR
].name
= "lr";
1041 info_ptr
->regs
[STACK_REGS_LR
].first
= LR_REGNO
;
1042 info_ptr
->regs
[STACK_REGS_LR
].last
= LR_REGNO
;
1043 info_ptr
->regs
[STACK_REGS_LR
].special_p
= 1;
1045 info_ptr
->regs
[STACK_REGS_CC
].name
= "cc";
1046 info_ptr
->regs
[STACK_REGS_CC
].first
= CC_FIRST
;
1047 info_ptr
->regs
[STACK_REGS_CC
].last
= CC_LAST
;
1048 info_ptr
->regs
[STACK_REGS_CC
].field_p
= TRUE
;
1050 info_ptr
->regs
[STACK_REGS_LCR
].name
= "lcr";
1051 info_ptr
->regs
[STACK_REGS_LCR
].first
= LCR_REGNO
;
1052 info_ptr
->regs
[STACK_REGS_LCR
].last
= LCR_REGNO
;
1054 info_ptr
->regs
[STACK_REGS_STDARG
].name
= "stdarg";
1055 info_ptr
->regs
[STACK_REGS_STDARG
].first
= FIRST_ARG_REGNUM
;
1056 info_ptr
->regs
[STACK_REGS_STDARG
].last
= LAST_ARG_REGNUM
;
1057 info_ptr
->regs
[STACK_REGS_STDARG
].dword_p
= 1;
1058 info_ptr
->regs
[STACK_REGS_STDARG
].special_p
= 1;
1060 info_ptr
->regs
[STACK_REGS_STRUCT
].name
= "struct";
1061 info_ptr
->regs
[STACK_REGS_STRUCT
].first
= FRV_STRUCT_VALUE_REGNUM
;
1062 info_ptr
->regs
[STACK_REGS_STRUCT
].last
= FRV_STRUCT_VALUE_REGNUM
;
1063 info_ptr
->regs
[STACK_REGS_STRUCT
].special_p
= 1;
1065 info_ptr
->regs
[STACK_REGS_FP
].name
= "fp";
1066 info_ptr
->regs
[STACK_REGS_FP
].first
= FRAME_POINTER_REGNUM
;
1067 info_ptr
->regs
[STACK_REGS_FP
].last
= FRAME_POINTER_REGNUM
;
1068 info_ptr
->regs
[STACK_REGS_FP
].special_p
= 1;
1070 /* Determine if this is a stdarg function. If so, allocate space to store
1077 /* Find the last argument, and see if it is __builtin_va_alist. */
1078 for (cur_arg
= DECL_ARGUMENTS (fndecl
); cur_arg
!= (tree
)0; cur_arg
= next_arg
)
1080 next_arg
= DECL_CHAIN (cur_arg
);
1081 if (next_arg
== (tree
)0)
1083 if (DECL_NAME (cur_arg
)
1084 && !strcmp (IDENTIFIER_POINTER (DECL_NAME (cur_arg
)), "__builtin_va_alist"))
1092 /* Iterate over all of the register ranges. */
1093 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1095 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1096 int first
= reg_ptr
->first
;
1097 int last
= reg_ptr
->last
;
1099 int size_2words
= 0;
1102 /* Calculate which registers need to be saved & save area size. */
1106 for (regno
= first
; regno
<= last
; regno
++)
1108 if ((df_regs_ever_live_p (regno
) && !call_used_regs
[regno
])
1109 || (crtl
->calls_eh_return
1110 && (regno
>= FIRST_EH_REGNUM
&& regno
<= LAST_EH_REGNUM
))
1111 || (!TARGET_FDPIC
&& flag_pic
1112 && crtl
->uses_pic_offset_table
&& regno
== PIC_REGNO
))
1114 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
1115 size_1word
+= UNITS_PER_WORD
;
1120 /* Calculate whether we need to create a frame after everything else
1121 has been processed. */
1126 if (df_regs_ever_live_p (LR_REGNO
)
1128 /* This is set for __builtin_return_address, etc. */
1129 || cfun
->machine
->frame_needed
1130 || (TARGET_LINKED_FP
&& frame_pointer_needed
)
1131 || (!TARGET_FDPIC
&& flag_pic
1132 && crtl
->uses_pic_offset_table
))
1134 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1135 size_1word
+= UNITS_PER_WORD
;
1139 case STACK_REGS_STDARG
:
1142 /* If this is a stdarg function with a non varardic
1143 argument split between registers and the stack,
1144 adjust the saved registers downward. */
1145 last
-= (ADDR_ALIGN (crtl
->args
.pretend_args_size
, UNITS_PER_WORD
)
1148 for (regno
= first
; regno
<= last
; regno
++)
1150 info_ptr
->save_p
[regno
] = REG_SAVE_1WORD
;
1151 size_1word
+= UNITS_PER_WORD
;
1154 info_ptr
->stdarg_size
= size_1word
;
1158 case STACK_REGS_STRUCT
:
1159 if (cfun
->returns_struct
)
1161 info_ptr
->save_p
[FRV_STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1162 size_1word
+= UNITS_PER_WORD
;
1170 /* If this is a field, it only takes one word. */
1171 if (reg_ptr
->field_p
)
1172 size_1word
= UNITS_PER_WORD
;
1174 /* Determine which register pairs can be saved together. */
1175 else if (reg_ptr
->dword_p
&& TARGET_DWORD
)
1177 for (regno
= first
; regno
< last
; regno
+= 2)
1179 if (info_ptr
->save_p
[regno
] && info_ptr
->save_p
[regno
+1])
1181 size_2words
+= 2 * UNITS_PER_WORD
;
1182 size_1word
-= 2 * UNITS_PER_WORD
;
1183 info_ptr
->save_p
[regno
] = REG_SAVE_2WORDS
;
1184 info_ptr
->save_p
[regno
+1] = REG_SAVE_NO_SAVE
;
1189 reg_ptr
->size_1word
= size_1word
;
1190 reg_ptr
->size_2words
= size_2words
;
1192 if (! reg_ptr
->special_p
)
1194 info_ptr
->regs_size_1word
+= size_1word
;
1195 info_ptr
->regs_size_2words
+= size_2words
;
1200 /* Set up the sizes of each each field in the frame body, making the sizes
1201 of each be divisible by the size of a dword if dword operations might
1202 be used, or the size of a word otherwise. */
1203 alignment
= (TARGET_DWORD
? 2 * UNITS_PER_WORD
: UNITS_PER_WORD
);
1205 info_ptr
->parameter_size
= ADDR_ALIGN (crtl
->outgoing_args_size
, alignment
);
1206 info_ptr
->regs_size
= ADDR_ALIGN (info_ptr
->regs_size_2words
1207 + info_ptr
->regs_size_1word
,
1209 info_ptr
->vars_size
= ADDR_ALIGN (get_frame_size (), alignment
);
1211 info_ptr
->pretend_size
= crtl
->args
.pretend_args_size
;
1213 /* Work out the size of the frame, excluding the header. Both the frame
1214 body and register parameter area will be dword-aligned. */
1215 info_ptr
->total_size
1216 = (ADDR_ALIGN (info_ptr
->parameter_size
1217 + info_ptr
->regs_size
1218 + info_ptr
->vars_size
,
1220 + ADDR_ALIGN (info_ptr
->pretend_size
1221 + info_ptr
->stdarg_size
,
1222 2 * UNITS_PER_WORD
));
1224 /* See if we need to create a frame at all, if so add header area. */
1225 if (info_ptr
->total_size
> 0
1226 || frame_pointer_needed
1227 || info_ptr
->regs
[STACK_REGS_LR
].size_1word
> 0
1228 || info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
> 0)
1230 offset
= info_ptr
->parameter_size
;
1231 info_ptr
->header_size
= 4 * UNITS_PER_WORD
;
1232 info_ptr
->total_size
+= 4 * UNITS_PER_WORD
;
1234 /* Calculate the offsets to save normal register pairs. */
1235 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1237 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1238 if (! reg_ptr
->special_p
)
1240 int first
= reg_ptr
->first
;
1241 int last
= reg_ptr
->last
;
1244 for (regno
= first
; regno
<= last
; regno
++)
1245 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
1246 && regno
!= FRAME_POINTER_REGNUM
1247 && (regno
< FIRST_ARG_REGNUM
1248 || regno
> LAST_ARG_REGNUM
))
1250 info_ptr
->reg_offset
[regno
] = offset
;
1251 offset
+= 2 * UNITS_PER_WORD
;
1256 /* Calculate the offsets to save normal single registers. */
1257 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1259 frv_stack_regs_t
*reg_ptr
= &(info_ptr
->regs
[range
]);
1260 if (! reg_ptr
->special_p
)
1262 int first
= reg_ptr
->first
;
1263 int last
= reg_ptr
->last
;
1266 for (regno
= first
; regno
<= last
; regno
++)
1267 if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
1268 && regno
!= FRAME_POINTER_REGNUM
1269 && (regno
< FIRST_ARG_REGNUM
1270 || regno
> LAST_ARG_REGNUM
))
1272 info_ptr
->reg_offset
[regno
] = offset
;
1273 offset
+= UNITS_PER_WORD
;
1278 /* Calculate the offset to save the local variables at. */
1279 offset
= ADDR_ALIGN (offset
, alignment
);
1280 if (info_ptr
->vars_size
)
1282 info_ptr
->vars_offset
= offset
;
1283 offset
+= info_ptr
->vars_size
;
1286 /* Align header to a dword-boundary. */
1287 offset
= ADDR_ALIGN (offset
, 2 * UNITS_PER_WORD
);
1289 /* Calculate the offsets in the fixed frame. */
1290 info_ptr
->save_p
[FRAME_POINTER_REGNUM
] = REG_SAVE_1WORD
;
1291 info_ptr
->reg_offset
[FRAME_POINTER_REGNUM
] = offset
;
1292 info_ptr
->regs
[STACK_REGS_FP
].size_1word
= UNITS_PER_WORD
;
1294 info_ptr
->save_p
[LR_REGNO
] = REG_SAVE_1WORD
;
1295 info_ptr
->reg_offset
[LR_REGNO
] = offset
+ 2*UNITS_PER_WORD
;
1296 info_ptr
->regs
[STACK_REGS_LR
].size_1word
= UNITS_PER_WORD
;
1298 if (cfun
->returns_struct
)
1300 info_ptr
->save_p
[FRV_STRUCT_VALUE_REGNUM
] = REG_SAVE_1WORD
;
1301 info_ptr
->reg_offset
[FRV_STRUCT_VALUE_REGNUM
] = offset
+ UNITS_PER_WORD
;
1302 info_ptr
->regs
[STACK_REGS_STRUCT
].size_1word
= UNITS_PER_WORD
;
1305 /* Calculate the offsets to store the arguments passed in registers
1306 for stdarg functions. The register pairs are first and the single
1307 register if any is last. The register save area starts on a
1309 if (info_ptr
->stdarg_size
)
1311 int first
= info_ptr
->regs
[STACK_REGS_STDARG
].first
;
1312 int last
= info_ptr
->regs
[STACK_REGS_STDARG
].last
;
1315 /* Skip the header. */
1316 offset
+= 4 * UNITS_PER_WORD
;
1317 for (regno
= first
; regno
<= last
; regno
++)
1319 if (info_ptr
->save_p
[regno
] == REG_SAVE_2WORDS
)
1321 info_ptr
->reg_offset
[regno
] = offset
;
1322 offset
+= 2 * UNITS_PER_WORD
;
1324 else if (info_ptr
->save_p
[regno
] == REG_SAVE_1WORD
)
1326 info_ptr
->reg_offset
[regno
] = offset
;
1327 offset
+= UNITS_PER_WORD
;
1333 if (reload_completed
)
1334 frv_stack_cache
= info_ptr
;
1340 /* Print the information about the frv stack offsets, etc. when debugging. */
1343 frv_debug_stack (frv_stack_t
*info
)
1348 info
= frv_stack_info ();
1350 fprintf (stderr
, "\nStack information for function %s:\n",
1351 ((current_function_decl
&& DECL_NAME (current_function_decl
))
1352 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl
))
1355 fprintf (stderr
, "\ttotal_size\t= %6d\n", info
->total_size
);
1356 fprintf (stderr
, "\tvars_size\t= %6d\n", info
->vars_size
);
1357 fprintf (stderr
, "\tparam_size\t= %6d\n", info
->parameter_size
);
1358 fprintf (stderr
, "\tregs_size\t= %6d, 1w = %3d, 2w = %3d\n",
1359 info
->regs_size
, info
->regs_size_1word
, info
->regs_size_2words
);
1361 fprintf (stderr
, "\theader_size\t= %6d\n", info
->header_size
);
1362 fprintf (stderr
, "\tpretend_size\t= %6d\n", info
->pretend_size
);
1363 fprintf (stderr
, "\tvars_offset\t= %6d\n", info
->vars_offset
);
1364 fprintf (stderr
, "\tregs_offset\t= %6d\n", info
->regs_offset
);
1366 for (range
= 0; range
< STACK_REGS_MAX
; range
++)
1368 frv_stack_regs_t
*regs
= &(info
->regs
[range
]);
1369 if ((regs
->size_1word
+ regs
->size_2words
) > 0)
1371 int first
= regs
->first
;
1372 int last
= regs
->last
;
1375 fprintf (stderr
, "\t%s\tsize\t= %6d, 1w = %3d, 2w = %3d, save =",
1376 regs
->name
, regs
->size_1word
+ regs
->size_2words
,
1377 regs
->size_1word
, regs
->size_2words
);
1379 for (regno
= first
; regno
<= last
; regno
++)
1381 if (info
->save_p
[regno
] == REG_SAVE_1WORD
)
1382 fprintf (stderr
, " %s (%d)", reg_names
[regno
],
1383 info
->reg_offset
[regno
]);
1385 else if (info
->save_p
[regno
] == REG_SAVE_2WORDS
)
1386 fprintf (stderr
, " %s-%s (%d)", reg_names
[regno
],
1387 reg_names
[regno
+1], info
->reg_offset
[regno
]);
1390 fputc ('\n', stderr
);
1400 /* Used during final to control the packing of insns. The value is
1401 1 if the current instruction should be packed with the next one,
1402 0 if it shouldn't or -1 if packing is disabled altogether. */
1404 static int frv_insn_packing_flag
;
1406 /* True if the current function contains a far jump. */
1409 frv_function_contains_far_jump (void)
1411 rtx_insn
*insn
= get_insns ();
1414 && get_attr_far_jump (insn
) == FAR_JUMP_YES
))
1415 insn
= NEXT_INSN (insn
);
1416 return (insn
!= NULL
);
1419 /* For the FRV, this function makes sure that a function with far jumps
1420 will return correctly. It also does the VLIW packing. */
1423 frv_function_prologue (FILE *file
, HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1425 rtx_insn
*insn
, *next
, *last_call
;
1427 /* If no frame was created, check whether the function uses a call
1428 instruction to implement a far jump. If so, save the link in gr3 and
1429 replace all returns to LR with returns to GR3. GR3 is used because it
1430 is call-clobbered, because is not available to the register allocator,
1431 and because all functions that take a hidden argument pointer will have
1433 if (frv_stack_info ()->total_size
== 0 && frv_function_contains_far_jump ())
1437 /* Just to check that the above comment is true. */
1438 gcc_assert (!df_regs_ever_live_p (GPR_FIRST
+ 3));
1440 /* Generate the instruction that saves the link register. */
1441 fprintf (file
, "\tmovsg lr,gr3\n");
1443 /* Replace the LR with GR3 in *return_internal patterns. The insn
1444 will now return using jmpl @(gr3,0) rather than bralr. We cannot
1445 simply emit a different assembly directive because bralr and jmpl
1446 execute in different units. */
1447 for (insn
= get_insns(); insn
!= NULL
; insn
= NEXT_INSN (insn
))
1450 rtx pattern
= PATTERN (insn
);
1451 if (GET_CODE (pattern
) == PARALLEL
1452 && XVECLEN (pattern
, 0) >= 2
1453 && GET_CODE (XVECEXP (pattern
, 0, 0)) == RETURN
1454 && GET_CODE (XVECEXP (pattern
, 0, 1)) == USE
)
1456 rtx address
= XEXP (XVECEXP (pattern
, 0, 1), 0);
1457 if (GET_CODE (address
) == REG
&& REGNO (address
) == LR_REGNO
)
1458 SET_REGNO (address
, GPR_FIRST
+ 3);
1465 /* Allow the garbage collector to free the nops created by frv_reorg. */
1466 memset (frv_nops
, 0, sizeof (frv_nops
));
1468 /* Locate CALL_ARG_LOCATION notes that have been misplaced
1469 and move them back to where they should be located. */
1471 for (insn
= get_insns (); insn
; insn
= next
)
1473 next
= NEXT_INSN (insn
);
1475 || (INSN_P (insn
) && GET_CODE (PATTERN (insn
)) == SEQUENCE
1476 && CALL_P (XVECEXP (PATTERN (insn
), 0, 0))))
1479 if (!NOTE_P (insn
) || NOTE_KIND (insn
) != NOTE_INSN_CALL_ARG_LOCATION
)
1482 if (NEXT_INSN (last_call
) == insn
)
1485 SET_NEXT_INSN (PREV_INSN (insn
)) = NEXT_INSN (insn
);
1486 SET_PREV_INSN (NEXT_INSN (insn
)) = PREV_INSN (insn
);
1487 SET_PREV_INSN (insn
) = last_call
;
1488 SET_NEXT_INSN (insn
) = NEXT_INSN (last_call
);
1489 SET_PREV_INSN (NEXT_INSN (insn
)) = insn
;
1490 SET_NEXT_INSN (PREV_INSN (insn
)) = insn
;
1496 /* Return the next available temporary register in a given class. */
1499 frv_alloc_temp_reg (
1500 frv_tmp_reg_t
*info
, /* which registers are available */
1501 enum reg_class rclass
, /* register class desired */
1502 machine_mode mode
, /* mode to allocate register with */
1503 int mark_as_used
, /* register not available after allocation */
1504 int no_abort
) /* return NULL instead of aborting */
1506 int regno
= info
->next_reg
[ (int)rclass
];
1507 int orig_regno
= regno
;
1508 HARD_REG_SET
*reg_in_class
= ®_class_contents
[ (int)rclass
];
1513 if (TEST_HARD_REG_BIT (*reg_in_class
, regno
)
1514 && TEST_HARD_REG_BIT (info
->regs
, regno
))
1517 if (++regno
>= FIRST_PSEUDO_REGISTER
)
1519 if (regno
== orig_regno
)
1521 gcc_assert (no_abort
);
1526 nr
= HARD_REGNO_NREGS (regno
, mode
);
1527 info
->next_reg
[ (int)rclass
] = regno
+ nr
;
1530 for (i
= 0; i
< nr
; i
++)
1531 CLEAR_HARD_REG_BIT (info
->regs
, regno
+i
);
1533 return gen_rtx_REG (mode
, regno
);
1537 /* Return an rtx with the value OFFSET, which will either be a register or a
1538 signed 12-bit integer. It can be used as the second operand in an "add"
1539 instruction, or as the index in a load or store.
1541 The function returns a constant rtx if OFFSET is small enough, otherwise
1542 it loads the constant into register OFFSET_REGNO and returns that. */
1544 frv_frame_offset_rtx (int offset
)
1546 rtx offset_rtx
= GEN_INT (offset
);
1547 if (IN_RANGE (offset
, -2048, 2047))
1551 rtx reg_rtx
= gen_rtx_REG (SImode
, OFFSET_REGNO
);
1552 if (IN_RANGE (offset
, -32768, 32767))
1553 emit_insn (gen_movsi (reg_rtx
, offset_rtx
));
1556 emit_insn (gen_movsi_high (reg_rtx
, offset_rtx
));
1557 emit_insn (gen_movsi_lo_sum (reg_rtx
, offset_rtx
));
1563 /* Generate (mem:MODE (plus:Pmode BASE (frv_frame_offset OFFSET)))). The
1564 prologue and epilogue uses such expressions to access the stack. */
1566 frv_frame_mem (machine_mode mode
, rtx base
, int offset
)
1568 return gen_rtx_MEM (mode
, gen_rtx_PLUS (Pmode
,
1570 frv_frame_offset_rtx (offset
)));
1573 /* Generate a frame-related expression:
1575 (set REG (mem (plus (sp) (const_int OFFSET)))).
1577 Such expressions are used in FRAME_RELATED_EXPR notes for more complex
1578 instructions. Marking the expressions as frame-related is superfluous if
1579 the note contains just a single set. But if the note contains a PARALLEL
1580 or SEQUENCE that has several sets, each set must be individually marked
1581 as frame-related. */
1583 frv_dwarf_store (rtx reg
, int offset
)
1585 rtx set
= gen_rtx_SET (gen_rtx_MEM (GET_MODE (reg
),
1586 plus_constant (Pmode
, stack_pointer_rtx
,
1589 RTX_FRAME_RELATED_P (set
) = 1;
1593 /* Emit a frame-related instruction whose pattern is PATTERN. The
1594 instruction is the last in a sequence that cumulatively performs the
1595 operation described by DWARF_PATTERN. The instruction is marked as
1596 frame-related and has a REG_FRAME_RELATED_EXPR note containing
1599 frv_frame_insn (rtx pattern
, rtx dwarf_pattern
)
1601 rtx insn
= emit_insn (pattern
);
1602 RTX_FRAME_RELATED_P (insn
) = 1;
1603 REG_NOTES (insn
) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR
,
1608 /* Emit instructions that transfer REG to or from the memory location (sp +
1609 STACK_OFFSET). The register is stored in memory if ACCESSOR->OP is
1610 FRV_STORE and loaded if it is FRV_LOAD. Only the prologue uses this
1611 function to store registers and only the epilogue uses it to load them.
1613 The caller sets up ACCESSOR so that BASE is equal to (sp + BASE_OFFSET).
1614 The generated instruction will use BASE as its base register. BASE may
1615 simply be the stack pointer, but if several accesses are being made to a
1616 region far away from the stack pointer, it may be more efficient to set
1617 up a temporary instead.
1619 Store instructions will be frame-related and will be annotated with the
1620 overall effect of the store. Load instructions will be followed by a
1621 (use) to prevent later optimizations from zapping them.
1623 The function takes care of the moves to and from SPRs, using TEMP_REGNO
1624 as a temporary in such cases. */
1626 frv_frame_access (frv_frame_accessor_t
*accessor
, rtx reg
, int stack_offset
)
1628 machine_mode mode
= GET_MODE (reg
);
1629 rtx mem
= frv_frame_mem (mode
,
1631 stack_offset
- accessor
->base_offset
);
1633 if (accessor
->op
== FRV_LOAD
)
1635 if (SPR_P (REGNO (reg
)))
1637 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1638 emit_insn (gen_rtx_SET (temp
, mem
));
1639 emit_insn (gen_rtx_SET (reg
, temp
));
1643 /* We cannot use reg+reg addressing for DImode access. */
1645 && GET_CODE (XEXP (mem
, 0)) == PLUS
1646 && GET_CODE (XEXP (XEXP (mem
, 0), 0)) == REG
1647 && GET_CODE (XEXP (XEXP (mem
, 0), 1)) == REG
)
1649 rtx temp
= gen_rtx_REG (SImode
, TEMP_REGNO
);
1651 emit_move_insn (temp
,
1652 gen_rtx_PLUS (SImode
, XEXP (XEXP (mem
, 0), 0),
1653 XEXP (XEXP (mem
, 0), 1)));
1654 mem
= gen_rtx_MEM (DImode
, temp
);
1656 emit_insn (gen_rtx_SET (reg
, mem
));
1662 if (SPR_P (REGNO (reg
)))
1664 rtx temp
= gen_rtx_REG (mode
, TEMP_REGNO
);
1665 emit_insn (gen_rtx_SET (temp
, reg
));
1666 frv_frame_insn (gen_rtx_SET (mem
, temp
),
1667 frv_dwarf_store (reg
, stack_offset
));
1669 else if (mode
== DImode
)
1671 /* For DImode saves, the dwarf2 version needs to be a SEQUENCE
1672 with a separate save for each register. */
1673 rtx reg1
= gen_rtx_REG (SImode
, REGNO (reg
));
1674 rtx reg2
= gen_rtx_REG (SImode
, REGNO (reg
) + 1);
1675 rtx set1
= frv_dwarf_store (reg1
, stack_offset
);
1676 rtx set2
= frv_dwarf_store (reg2
, stack_offset
+ 4);
1678 /* Also we cannot use reg+reg addressing. */
1679 if (GET_CODE (XEXP (mem
, 0)) == PLUS
1680 && GET_CODE (XEXP (XEXP (mem
, 0), 0)) == REG
1681 && GET_CODE (XEXP (XEXP (mem
, 0), 1)) == REG
)
1683 rtx temp
= gen_rtx_REG (SImode
, TEMP_REGNO
);
1684 emit_move_insn (temp
,
1685 gen_rtx_PLUS (SImode
, XEXP (XEXP (mem
, 0), 0),
1686 XEXP (XEXP (mem
, 0), 1)));
1687 mem
= gen_rtx_MEM (DImode
, temp
);
1690 frv_frame_insn (gen_rtx_SET (mem
, reg
),
1691 gen_rtx_PARALLEL (VOIDmode
,
1692 gen_rtvec (2, set1
, set2
)));
1695 frv_frame_insn (gen_rtx_SET (mem
, reg
),
1696 frv_dwarf_store (reg
, stack_offset
));
1700 /* A function that uses frv_frame_access to transfer a group of registers to
1701 or from the stack. ACCESSOR is passed directly to frv_frame_access, INFO
1702 is the stack information generated by frv_stack_info, and REG_SET is the
1703 number of the register set to transfer. */
1705 frv_frame_access_multi (frv_frame_accessor_t
*accessor
,
1709 frv_stack_regs_t
*regs_info
;
1712 regs_info
= &info
->regs
[reg_set
];
1713 for (regno
= regs_info
->first
; regno
<= regs_info
->last
; regno
++)
1714 if (info
->save_p
[regno
])
1715 frv_frame_access (accessor
,
1716 info
->save_p
[regno
] == REG_SAVE_2WORDS
1717 ? gen_rtx_REG (DImode
, regno
)
1718 : gen_rtx_REG (SImode
, regno
),
1719 info
->reg_offset
[regno
]);
1722 /* Save or restore callee-saved registers that are kept outside the frame
1723 header. The function saves the registers if OP is FRV_STORE and restores
1724 them if OP is FRV_LOAD. INFO is the stack information generated by
1727 frv_frame_access_standard_regs (enum frv_stack_op op
, frv_stack_t
*info
)
1729 frv_frame_accessor_t accessor
;
1732 accessor
.base
= stack_pointer_rtx
;
1733 accessor
.base_offset
= 0;
1734 frv_frame_access_multi (&accessor
, info
, STACK_REGS_GPR
);
1735 frv_frame_access_multi (&accessor
, info
, STACK_REGS_FPR
);
1736 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LCR
);
1740 /* Called after register allocation to add any instructions needed for the
1741 prologue. Using a prologue insn is favored compared to putting all of the
1742 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1743 it allows the scheduler to intermix instructions with the saves of
1744 the caller saved registers. In some cases, it might be necessary
1745 to emit a barrier instruction as the last insn to prevent such
1748 Also any insns generated here should have RTX_FRAME_RELATED_P(insn) = 1
1749 so that the debug info generation code can handle them properly. */
1751 frv_expand_prologue (void)
1753 frv_stack_t
*info
= frv_stack_info ();
1754 rtx sp
= stack_pointer_rtx
;
1755 rtx fp
= frame_pointer_rtx
;
1756 frv_frame_accessor_t accessor
;
1758 if (TARGET_DEBUG_STACK
)
1759 frv_debug_stack (info
);
1761 if (flag_stack_usage_info
)
1762 current_function_static_stack_size
= info
->total_size
;
1764 if (info
->total_size
== 0)
1767 /* We're interested in three areas of the frame here:
1769 A: the register save area
1771 C: the header after B
1773 If the frame pointer isn't used, we'll have to set up A, B and C
1774 using the stack pointer. If the frame pointer is used, we'll access
1778 B: set up using sp or a temporary (see below)
1781 We set up B using the stack pointer if the frame is small enough.
1782 Otherwise, it's more efficient to copy the old stack pointer into a
1783 temporary and use that.
1785 Note that it's important to make sure the prologue and epilogue use the
1786 same registers to access A and C, since doing otherwise will confuse
1787 the aliasing code. */
1789 /* Set up ACCESSOR for accessing region B above. If the frame pointer
1790 isn't used, the same method will serve for C. */
1791 accessor
.op
= FRV_STORE
;
1792 if (frame_pointer_needed
&& info
->total_size
> 2048)
1794 accessor
.base
= gen_rtx_REG (Pmode
, OLD_SP_REGNO
);
1795 accessor
.base_offset
= info
->total_size
;
1796 emit_insn (gen_movsi (accessor
.base
, sp
));
1800 accessor
.base
= stack_pointer_rtx
;
1801 accessor
.base_offset
= 0;
1804 /* Allocate the stack space. */
1806 rtx asm_offset
= frv_frame_offset_rtx (-info
->total_size
);
1807 rtx dwarf_offset
= GEN_INT (-info
->total_size
);
1809 frv_frame_insn (gen_stack_adjust (sp
, sp
, asm_offset
),
1810 gen_rtx_SET (sp
, gen_rtx_PLUS (Pmode
, sp
, dwarf_offset
)));
1813 /* If the frame pointer is needed, store the old one at (sp + FP_OFFSET)
1814 and point the new one to that location. */
1815 if (frame_pointer_needed
)
1817 int fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1819 /* ASM_SRC and DWARF_SRC both point to the frame header. ASM_SRC is
1820 based on ACCESSOR.BASE but DWARF_SRC is always based on the stack
1822 rtx asm_src
= plus_constant (Pmode
, accessor
.base
,
1823 fp_offset
- accessor
.base_offset
);
1824 rtx dwarf_src
= plus_constant (Pmode
, sp
, fp_offset
);
1826 /* Store the old frame pointer at (sp + FP_OFFSET). */
1827 frv_frame_access (&accessor
, fp
, fp_offset
);
1829 /* Set up the new frame pointer. */
1830 frv_frame_insn (gen_rtx_SET (fp
, asm_src
),
1831 gen_rtx_SET (fp
, dwarf_src
));
1833 /* Access region C from the frame pointer. */
1835 accessor
.base_offset
= fp_offset
;
1838 /* Set up region C. */
1839 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STRUCT
);
1840 frv_frame_access_multi (&accessor
, info
, STACK_REGS_LR
);
1841 frv_frame_access_multi (&accessor
, info
, STACK_REGS_STDARG
);
1843 /* Set up region A. */
1844 frv_frame_access_standard_regs (FRV_STORE
, info
);
1846 /* If this is a varargs/stdarg function, issue a blockage to prevent the
1847 scheduler from moving loads before the stores saving the registers. */
1848 if (info
->stdarg_size
> 0)
1849 emit_insn (gen_blockage ());
1851 /* Set up pic register/small data register for this function. */
1852 if (!TARGET_FDPIC
&& flag_pic
&& crtl
->uses_pic_offset_table
)
1853 emit_insn (gen_pic_prologue (gen_rtx_REG (Pmode
, PIC_REGNO
),
1854 gen_rtx_REG (Pmode
, LR_REGNO
),
1855 gen_rtx_REG (SImode
, OFFSET_REGNO
)));
1859 /* Under frv, all of the work is done via frv_expand_epilogue, but
1860 this function provides a convenient place to do cleanup. */
1863 frv_function_epilogue (FILE *file ATTRIBUTE_UNUSED
,
1864 HOST_WIDE_INT size ATTRIBUTE_UNUSED
)
1866 frv_stack_cache
= (frv_stack_t
*)0;
1868 /* Zap last used registers for conditional execution. */
1869 memset (&frv_ifcvt
.tmp_reg
, 0, sizeof (frv_ifcvt
.tmp_reg
));
1871 /* Release the bitmap of created insns. */
1872 BITMAP_FREE (frv_ifcvt
.scratch_insns_bitmap
);
1876 /* Called after register allocation to add any instructions needed for the
1877 epilogue. Using an epilogue insn is favored compared to putting all of the
1878 instructions in the TARGET_ASM_FUNCTION_PROLOGUE target hook, since
1879 it allows the scheduler to intermix instructions with the saves of
1880 the caller saved registers. In some cases, it might be necessary
1881 to emit a barrier instruction as the last insn to prevent such
1885 frv_expand_epilogue (bool emit_return
)
1887 frv_stack_t
*info
= frv_stack_info ();
1888 rtx fp
= frame_pointer_rtx
;
1889 rtx sp
= stack_pointer_rtx
;
1893 fp_offset
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
1895 /* Restore the stack pointer to its original value if alloca or the like
1897 if (! crtl
->sp_is_unchanging
)
1898 emit_insn (gen_addsi3 (sp
, fp
, frv_frame_offset_rtx (-fp_offset
)));
1900 /* Restore the callee-saved registers that were used in this function. */
1901 frv_frame_access_standard_regs (FRV_LOAD
, info
);
1903 /* Set RETURN_ADDR to the address we should return to. Set it to NULL if
1904 no return instruction should be emitted. */
1905 if (info
->save_p
[LR_REGNO
])
1910 /* Use the same method to access the link register's slot as we did in
1911 the prologue. In other words, use the frame pointer if available,
1912 otherwise use the stack pointer.
1914 LR_OFFSET is the offset of the link register's slot from the start
1915 of the frame and MEM is a memory rtx for it. */
1916 lr_offset
= info
->reg_offset
[LR_REGNO
];
1917 if (frame_pointer_needed
)
1918 mem
= frv_frame_mem (Pmode
, fp
, lr_offset
- fp_offset
);
1920 mem
= frv_frame_mem (Pmode
, sp
, lr_offset
);
1922 /* Load the old link register into a GPR. */
1923 return_addr
= gen_rtx_REG (Pmode
, TEMP_REGNO
);
1924 emit_insn (gen_rtx_SET (return_addr
, mem
));
1927 return_addr
= gen_rtx_REG (Pmode
, LR_REGNO
);
1929 /* Restore the old frame pointer. Emit a USE afterwards to make sure
1930 the load is preserved. */
1931 if (frame_pointer_needed
)
1933 emit_insn (gen_rtx_SET (fp
, gen_rtx_MEM (Pmode
, fp
)));
1937 /* Deallocate the stack frame. */
1938 if (info
->total_size
!= 0)
1940 rtx offset
= frv_frame_offset_rtx (info
->total_size
);
1941 emit_insn (gen_stack_adjust (sp
, sp
, offset
));
1944 /* If this function uses eh_return, add the final stack adjustment now. */
1945 if (crtl
->calls_eh_return
)
1946 emit_insn (gen_stack_adjust (sp
, sp
, EH_RETURN_STACKADJ_RTX
));
1949 emit_jump_insn (gen_epilogue_return (return_addr
));
1952 rtx lr
= return_addr
;
1954 if (REGNO (return_addr
) != LR_REGNO
)
1956 lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
1957 emit_move_insn (lr
, return_addr
);
1965 /* Worker function for TARGET_ASM_OUTPUT_MI_THUNK. */
1968 frv_asm_output_mi_thunk (FILE *file
,
1969 tree thunk_fndecl ATTRIBUTE_UNUSED
,
1970 HOST_WIDE_INT delta
,
1971 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED
,
1974 const char *name_func
= XSTR (XEXP (DECL_RTL (function
), 0), 0);
1975 const char *name_arg0
= reg_names
[FIRST_ARG_REGNUM
];
1976 const char *name_jmp
= reg_names
[JUMP_REGNO
];
1977 const char *parallel
= (frv_issue_rate () > 1 ? ".p" : "");
1979 /* Do the add using an addi if possible. */
1980 if (IN_RANGE (delta
, -2048, 2047))
1981 fprintf (file
, "\taddi %s,#%d,%s\n", name_arg0
, (int) delta
, name_arg0
);
1984 const char *const name_add
= reg_names
[TEMP_REGNO
];
1985 fprintf (file
, "\tsethi%s #hi(" HOST_WIDE_INT_PRINT_DEC
"),%s\n",
1986 parallel
, delta
, name_add
);
1987 fprintf (file
, "\tsetlo #lo(" HOST_WIDE_INT_PRINT_DEC
"),%s\n",
1989 fprintf (file
, "\tadd %s,%s,%s\n", name_add
, name_arg0
, name_arg0
);
1994 const char *name_pic
= reg_names
[FDPIC_REGNO
];
1995 name_jmp
= reg_names
[FDPIC_FPTR_REGNO
];
1999 fprintf (file
, "\tsethi%s #gotofffuncdeschi(", parallel
);
2000 assemble_name (file
, name_func
);
2001 fprintf (file
, "),%s\n", name_jmp
);
2003 fprintf (file
, "\tsetlo #gotofffuncdesclo(");
2004 assemble_name (file
, name_func
);
2005 fprintf (file
, "),%s\n", name_jmp
);
2007 fprintf (file
, "\tldd @(%s,%s), %s\n", name_jmp
, name_pic
, name_jmp
);
2011 fprintf (file
, "\tlddo @(%s,#gotofffuncdesc12(", name_pic
);
2012 assemble_name (file
, name_func
);
2013 fprintf (file
, "\t)), %s\n", name_jmp
);
2018 fprintf (file
, "\tsethi%s #hi(", parallel
);
2019 assemble_name (file
, name_func
);
2020 fprintf (file
, "),%s\n", name_jmp
);
2022 fprintf (file
, "\tsetlo #lo(");
2023 assemble_name (file
, name_func
);
2024 fprintf (file
, "),%s\n", name_jmp
);
2028 /* Use JUMP_REGNO as a temporary PIC register. */
2029 const char *name_lr
= reg_names
[LR_REGNO
];
2030 const char *name_gppic
= name_jmp
;
2031 const char *name_tmp
= reg_names
[TEMP_REGNO
];
2033 fprintf (file
, "\tmovsg %s,%s\n", name_lr
, name_tmp
);
2034 fprintf (file
, "\tcall 1f\n");
2035 fprintf (file
, "1:\tmovsg %s,%s\n", name_lr
, name_gppic
);
2036 fprintf (file
, "\tmovgs %s,%s\n", name_tmp
, name_lr
);
2037 fprintf (file
, "\tsethi%s #gprelhi(1b),%s\n", parallel
, name_tmp
);
2038 fprintf (file
, "\tsetlo #gprello(1b),%s\n", name_tmp
);
2039 fprintf (file
, "\tsub %s,%s,%s\n", name_gppic
, name_tmp
, name_gppic
);
2041 fprintf (file
, "\tsethi%s #gprelhi(", parallel
);
2042 assemble_name (file
, name_func
);
2043 fprintf (file
, "),%s\n", name_tmp
);
2045 fprintf (file
, "\tsetlo #gprello(");
2046 assemble_name (file
, name_func
);
2047 fprintf (file
, "),%s\n", name_tmp
);
2049 fprintf (file
, "\tadd %s,%s,%s\n", name_gppic
, name_tmp
, name_jmp
);
2052 /* Jump to the function address. */
2053 fprintf (file
, "\tjmpl @(%s,%s)\n", name_jmp
, reg_names
[GPR_FIRST
+0]);
2058 /* On frv, create a frame whenever we need to create stack. */
2061 frv_frame_pointer_required (void)
2063 /* If we forgoing the usual linkage requirements, we only need
2064 a frame pointer if the stack pointer might change. */
2065 if (!TARGET_LINKED_FP
)
2066 return !crtl
->sp_is_unchanging
;
2068 if (! crtl
->is_leaf
)
2071 if (get_frame_size () != 0)
2077 if (!crtl
->sp_is_unchanging
)
2080 if (!TARGET_FDPIC
&& flag_pic
&& crtl
->uses_pic_offset_table
)
2086 if (cfun
->machine
->frame_needed
)
2093 /* Worker function for TARGET_CAN_ELIMINATE. */
2096 frv_can_eliminate (const int from
, const int to
)
2098 return (from
== ARG_POINTER_REGNUM
&& to
== STACK_POINTER_REGNUM
2099 ? ! frame_pointer_needed
2103 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It specifies the
2104 initial difference between the specified pair of registers. This macro must
2105 be defined if `ELIMINABLE_REGS' is defined. */
2107 /* See frv_stack_info for more details on the frv stack frame. */
2110 frv_initial_elimination_offset (int from
, int to
)
2112 frv_stack_t
*info
= frv_stack_info ();
2115 if (to
== STACK_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
2116 ret
= info
->total_size
- info
->pretend_size
;
2118 else if (to
== STACK_POINTER_REGNUM
&& from
== FRAME_POINTER_REGNUM
)
2119 ret
= info
->reg_offset
[FRAME_POINTER_REGNUM
];
2121 else if (to
== FRAME_POINTER_REGNUM
&& from
== ARG_POINTER_REGNUM
)
2122 ret
= (info
->total_size
2123 - info
->reg_offset
[FRAME_POINTER_REGNUM
]
2124 - info
->pretend_size
);
2129 if (TARGET_DEBUG_STACK
)
2130 fprintf (stderr
, "Eliminate %s to %s by adding %d\n",
2131 reg_names
[from
], reg_names
[to
], ret
);
2137 /* Worker function for TARGET_SETUP_INCOMING_VARARGS. */
2140 frv_setup_incoming_varargs (cumulative_args_t cum_v
,
2142 tree type ATTRIBUTE_UNUSED
,
2146 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
2148 if (TARGET_DEBUG_ARG
)
2150 "setup_vararg: words = %2d, mode = %4s, pretend_size = %d, second_time = %d\n",
2151 *cum
, GET_MODE_NAME (mode
), *pretend_size
, second_time
);
2155 /* Worker function for TARGET_EXPAND_BUILTIN_SAVEREGS. */
2158 frv_expand_builtin_saveregs (void)
2160 int offset
= UNITS_PER_WORD
* FRV_NUM_ARG_REGS
;
2162 if (TARGET_DEBUG_ARG
)
2163 fprintf (stderr
, "expand_builtin_saveregs: offset from ap = %d\n",
2166 return gen_rtx_PLUS (Pmode
, virtual_incoming_args_rtx
, GEN_INT (- offset
));
2170 /* Expand __builtin_va_start to do the va_start macro. */
2173 frv_expand_builtin_va_start (tree valist
, rtx nextarg
)
2176 int num
= crtl
->args
.info
- FIRST_ARG_REGNUM
- FRV_NUM_ARG_REGS
;
2178 nextarg
= gen_rtx_PLUS (Pmode
, virtual_incoming_args_rtx
,
2179 GEN_INT (UNITS_PER_WORD
* num
));
2181 if (TARGET_DEBUG_ARG
)
2183 fprintf (stderr
, "va_start: args_info = %d, num = %d\n",
2184 crtl
->args
.info
, num
);
2186 debug_rtx (nextarg
);
2189 t
= build2 (MODIFY_EXPR
, TREE_TYPE (valist
), valist
,
2190 fold_convert (TREE_TYPE (valist
),
2191 make_tree (sizetype
, nextarg
)));
2192 TREE_SIDE_EFFECTS (t
) = 1;
2194 expand_expr (t
, const0_rtx
, VOIDmode
, EXPAND_NORMAL
);
2198 /* Expand a block move operation, and return 1 if successful. Return 0
2199 if we should let the compiler generate normal code.
2201 operands[0] is the destination
2202 operands[1] is the source
2203 operands[2] is the length
2204 operands[3] is the alignment */
2206 /* Maximum number of loads to do before doing the stores */
2207 #ifndef MAX_MOVE_REG
2208 #define MAX_MOVE_REG 4
2211 /* Maximum number of total loads to do. */
2212 #ifndef TOTAL_MOVE_REG
2213 #define TOTAL_MOVE_REG 8
2217 frv_expand_block_move (rtx operands
[])
2219 rtx orig_dest
= operands
[0];
2220 rtx orig_src
= operands
[1];
2221 rtx bytes_rtx
= operands
[2];
2222 rtx align_rtx
= operands
[3];
2223 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2236 rtx stores
[MAX_MOVE_REG
];
2240 /* If this is not a fixed size move, just call memcpy. */
2244 /* This should be a fixed size alignment. */
2245 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
2247 align
= INTVAL (align_rtx
);
2249 /* Anything to move? */
2250 bytes
= INTVAL (bytes_rtx
);
2254 /* Don't support real large moves. */
2255 if (bytes
> TOTAL_MOVE_REG
*align
)
2258 /* Move the address into scratch registers. */
2259 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2260 src_reg
= copy_addr_to_reg (XEXP (orig_src
, 0));
2262 num_reg
= offset
= 0;
2263 for ( ; bytes
> 0; (bytes
-= move_bytes
), (offset
+= move_bytes
))
2265 /* Calculate the correct offset for src/dest. */
2269 dest_addr
= dest_reg
;
2273 src_addr
= plus_constant (Pmode
, src_reg
, offset
);
2274 dest_addr
= plus_constant (Pmode
, dest_reg
, offset
);
2277 /* Generate the appropriate load and store, saving the stores
2279 if (bytes
>= 4 && align
>= 4)
2281 else if (bytes
>= 2 && align
>= 2)
2286 move_bytes
= GET_MODE_SIZE (mode
);
2287 tmp_reg
= gen_reg_rtx (mode
);
2288 src_mem
= change_address (orig_src
, mode
, src_addr
);
2289 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2290 emit_insn (gen_rtx_SET (tmp_reg
, src_mem
));
2291 stores
[num_reg
++] = gen_rtx_SET (dest_mem
, tmp_reg
);
2293 if (num_reg
>= MAX_MOVE_REG
)
2295 for (i
= 0; i
< num_reg
; i
++)
2296 emit_insn (stores
[i
]);
2301 for (i
= 0; i
< num_reg
; i
++)
2302 emit_insn (stores
[i
]);
2308 /* Expand a block clear operation, and return 1 if successful. Return 0
2309 if we should let the compiler generate normal code.
2311 operands[0] is the destination
2312 operands[1] is the length
2313 operands[3] is the alignment */
2316 frv_expand_block_clear (rtx operands
[])
2318 rtx orig_dest
= operands
[0];
2319 rtx bytes_rtx
= operands
[1];
2320 rtx align_rtx
= operands
[3];
2321 int constp
= (GET_CODE (bytes_rtx
) == CONST_INT
);
2331 /* If this is not a fixed size move, just call memcpy. */
2335 /* This should be a fixed size alignment. */
2336 gcc_assert (GET_CODE (align_rtx
) == CONST_INT
);
2338 align
= INTVAL (align_rtx
);
2340 /* Anything to move? */
2341 bytes
= INTVAL (bytes_rtx
);
2345 /* Don't support real large clears. */
2346 if (bytes
> TOTAL_MOVE_REG
*align
)
2349 /* Move the address into a scratch register. */
2350 dest_reg
= copy_addr_to_reg (XEXP (orig_dest
, 0));
2353 for ( ; bytes
> 0; (bytes
-= clear_bytes
), (offset
+= clear_bytes
))
2355 /* Calculate the correct offset for src/dest. */
2356 dest_addr
= ((offset
== 0)
2358 : plus_constant (Pmode
, dest_reg
, offset
));
2360 /* Generate the appropriate store of gr0. */
2361 if (bytes
>= 4 && align
>= 4)
2363 else if (bytes
>= 2 && align
>= 2)
2368 clear_bytes
= GET_MODE_SIZE (mode
);
2369 dest_mem
= change_address (orig_dest
, mode
, dest_addr
);
2370 emit_insn (gen_rtx_SET (dest_mem
, const0_rtx
));
2377 /* The following variable is used to output modifiers of assembler
2378 code of the current output insn. */
2380 static rtx
*frv_insn_operands
;
2382 /* The following function is used to add assembler insn code suffix .p
2383 if it is necessary. */
2386 frv_asm_output_opcode (FILE *f
, const char *ptr
)
2390 if (frv_insn_packing_flag
<= 0)
2393 for (; *ptr
&& *ptr
!= ' ' && *ptr
!= '\t';)
2396 if (c
== '%' && ((*ptr
>= 'a' && *ptr
<= 'z')
2397 || (*ptr
>= 'A' && *ptr
<= 'Z')))
2399 int letter
= *ptr
++;
2402 frv_print_operand (f
, frv_insn_operands
[c
], letter
);
2403 while ((c
= *ptr
) >= '0' && c
<= '9')
2415 /* Set up the packing bit for the current output insn. Note that this
2416 function is not called for asm insns. */
2419 frv_final_prescan_insn (rtx_insn
*insn
, rtx
*opvec
,
2420 int noperands ATTRIBUTE_UNUSED
)
2424 if (frv_insn_packing_flag
>= 0)
2426 frv_insn_operands
= opvec
;
2427 frv_insn_packing_flag
= PACKING_FLAG_P (insn
);
2429 else if (recog_memoized (insn
) >= 0
2430 && get_attr_acc_group (insn
) == ACC_GROUP_ODD
)
2431 /* Packing optimizations have been disabled, but INSN can only
2432 be issued in M1. Insert an mnop in M0. */
2433 fprintf (asm_out_file
, "\tmnop.p\n");
2439 /* A C expression whose value is RTL representing the address in a stack frame
2440 where the pointer to the caller's frame is stored. Assume that FRAMEADDR is
2441 an RTL expression for the address of the stack frame itself.
2443 If you don't define this macro, the default is to return the value of
2444 FRAMEADDR--that is, the stack frame address is also the address of the stack
2445 word that points to the previous frame. */
2447 /* The default is correct, but we need to make sure the frame gets created. */
2449 frv_dynamic_chain_address (rtx frame
)
2451 cfun
->machine
->frame_needed
= 1;
2456 /* A C expression whose value is RTL representing the value of the return
2457 address for the frame COUNT steps up from the current frame, after the
2458 prologue. FRAMEADDR is the frame pointer of the COUNT frame, or the frame
2459 pointer of the COUNT - 1 frame if `RETURN_ADDR_IN_PREVIOUS_FRAME' is
2462 The value of the expression must always be the correct address when COUNT is
2463 zero, but may be `NULL_RTX' if there is not way to determine the return
2464 address of other frames. */
2467 frv_return_addr_rtx (int count
, rtx frame
)
2471 cfun
->machine
->frame_needed
= 1;
2472 return gen_rtx_MEM (Pmode
, plus_constant (Pmode
, frame
, 8));
2475 /* Given a memory reference MEMREF, interpret the referenced memory as
2476 an array of MODE values, and return a reference to the element
2477 specified by INDEX. Assume that any pre-modification implicit in
2478 MEMREF has already happened.
2480 MEMREF must be a legitimate operand for modes larger than SImode.
2481 frv_legitimate_address_p forbids register+register addresses, which
2482 this function cannot handle. */
2484 frv_index_memory (rtx memref
, machine_mode mode
, int index
)
2486 rtx base
= XEXP (memref
, 0);
2487 if (GET_CODE (base
) == PRE_MODIFY
)
2488 base
= XEXP (base
, 0);
2489 return change_address (memref
, mode
,
2490 plus_constant (Pmode
, base
,
2491 index
* GET_MODE_SIZE (mode
)));
2495 /* Print a memory address as an operand to reference that memory location. */
2497 frv_print_operand_address (FILE * stream
, rtx x
)
2499 if (GET_CODE (x
) == MEM
)
2502 switch (GET_CODE (x
))
2505 fputs (reg_names
[ REGNO (x
)], stream
);
2509 fprintf (stream
, "%ld", (long) INTVAL (x
));
2513 assemble_name (stream
, XSTR (x
, 0));
2518 output_addr_const (stream
, x
);
2522 /* Poorly constructed asm statements can trigger this alternative.
2523 See gcc/testsuite/gcc.dg/asm-4.c for an example. */
2524 frv_print_operand_memory_reference (stream
, x
, 0);
2531 fatal_insn ("bad insn to frv_print_operand_address:", x
);
2536 frv_print_operand_memory_reference_reg (FILE * stream
, rtx x
)
2538 int regno
= true_regnum (x
);
2540 fputs (reg_names
[regno
], stream
);
2542 fatal_insn ("bad register to frv_print_operand_memory_reference_reg:", x
);
2545 /* Print a memory reference suitable for the ld/st instructions. */
2548 frv_print_operand_memory_reference (FILE * stream
, rtx x
, int addr_offset
)
2550 struct frv_unspec unspec
;
2554 switch (GET_CODE (x
))
2561 case PRE_MODIFY
: /* (pre_modify (reg) (plus (reg) (reg))) */
2563 x1
= XEXP (XEXP (x
, 1), 1);
2573 if (GET_CODE (x0
) == CONST_INT
)
2581 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2590 else if (GET_CODE (x1
) != CONST_INT
)
2591 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2594 fputs ("@(", stream
);
2596 fputs (reg_names
[GPR_R0
], stream
);
2597 else if (GET_CODE (x0
) == REG
|| GET_CODE (x0
) == SUBREG
)
2598 frv_print_operand_memory_reference_reg (stream
, x0
);
2600 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2602 fputs (",", stream
);
2604 fputs (reg_names
[GPR_R0
], stream
);
2608 switch (GET_CODE (x1
))
2612 frv_print_operand_memory_reference_reg (stream
, x1
);
2616 fprintf (stream
, "%ld", (long) (INTVAL (x1
) + addr_offset
));
2620 if (!frv_const_unspec_p (x1
, &unspec
))
2621 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x1
);
2622 frv_output_const_unspec (stream
, &unspec
);
2626 fatal_insn ("bad insn to frv_print_operand_memory_reference:", x
);
2630 fputs (")", stream
);
2634 /* Return 2 for likely branches and 0 for non-likely branches */
2636 #define FRV_JUMP_LIKELY 2
2637 #define FRV_JUMP_NOT_LIKELY 0
2640 frv_print_operand_jump_hint (rtx_insn
*insn
)
2646 enum { UNKNOWN
, BACKWARD
, FORWARD
} jump_type
= UNKNOWN
;
2648 gcc_assert (JUMP_P (insn
));
2650 /* Assume any non-conditional jump is likely. */
2651 if (! any_condjump_p (insn
))
2652 ret
= FRV_JUMP_LIKELY
;
2656 labelref
= condjump_label (insn
);
2659 rtx label
= XEXP (labelref
, 0);
2660 jump_type
= (insn_current_address
> INSN_ADDRESSES (INSN_UID (label
))
2665 note
= find_reg_note (insn
, REG_BR_PROB
, 0);
2667 ret
= ((jump_type
== BACKWARD
) ? FRV_JUMP_LIKELY
: FRV_JUMP_NOT_LIKELY
);
2671 prob
= XINT (note
, 0);
2672 ret
= ((prob
>= (REG_BR_PROB_BASE
/ 2))
2674 : FRV_JUMP_NOT_LIKELY
);
2686 case UNKNOWN
: direction
= "unknown jump direction"; break;
2687 case BACKWARD
: direction
= "jump backward"; break;
2688 case FORWARD
: direction
= "jump forward"; break;
2692 "%s: uid %ld, %s, probability = %d, max prob. = %d, hint = %d\n",
2693 IDENTIFIER_POINTER (DECL_NAME (current_function_decl
)),
2694 (long)INSN_UID (insn
), direction
, prob
,
2695 REG_BR_PROB_BASE
, ret
);
2703 /* Return the comparison operator to use for CODE given that the ICC
2707 comparison_string (enum rtx_code code
, rtx op0
)
2709 bool is_nz_p
= GET_MODE (op0
) == CC_NZmode
;
2712 default: output_operand_lossage ("bad condition code");
2713 case EQ
: return "eq";
2714 case NE
: return "ne";
2715 case LT
: return is_nz_p
? "n" : "lt";
2716 case LE
: return "le";
2717 case GT
: return "gt";
2718 case GE
: return is_nz_p
? "p" : "ge";
2719 case LTU
: return is_nz_p
? "no" : "c";
2720 case LEU
: return is_nz_p
? "eq" : "ls";
2721 case GTU
: return is_nz_p
? "ne" : "hi";
2722 case GEU
: return is_nz_p
? "ra" : "nc";
2726 /* Print an operand to an assembler instruction.
2728 `%' followed by a letter and a digit says to output an operand in an
2729 alternate fashion. Four letters have standard, built-in meanings
2730 described below. The hook `TARGET_PRINT_OPERAND' can define
2731 additional letters with nonstandard meanings.
2733 `%cDIGIT' can be used to substitute an operand that is a constant value
2734 without the syntax that normally indicates an immediate operand.
2736 `%nDIGIT' is like `%cDIGIT' except that the value of the constant is negated
2739 `%aDIGIT' can be used to substitute an operand as if it were a memory
2740 reference, with the actual operand treated as the address. This may be
2741 useful when outputting a "load address" instruction, because often the
2742 assembler syntax for such an instruction requires you to write the operand
2743 as if it were a memory reference.
2745 `%lDIGIT' is used to substitute a `label_ref' into a jump instruction.
2747 `%=' outputs a number which is unique to each instruction in the entire
2748 compilation. This is useful for making local labels to be referred to more
2749 than once in a single template that generates multiple assembler
2752 `%' followed by a punctuation character specifies a substitution that
2753 does not use an operand. Only one case is standard: `%%' outputs a
2754 `%' into the assembler code. Other nonstandard cases can be defined
2755 in the `TARGET_PRINT_OPERAND' hook. You must also define which
2756 punctuation characters are valid with the
2757 `TARGET_PRINT_OPERAND_PUNCT_VALID_P' hook. */
2760 frv_print_operand (FILE * file
, rtx x
, int code
)
2762 struct frv_unspec unspec
;
2763 HOST_WIDE_INT value
;
2766 if (code
!= 0 && !ISALPHA (code
))
2769 else if (GET_CODE (x
) == CONST_INT
)
2772 else if (GET_CODE (x
) == CONST_DOUBLE
)
2774 if (GET_MODE (x
) == SFmode
)
2779 REAL_VALUE_FROM_CONST_DOUBLE (rv
, x
);
2780 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
2784 else if (GET_MODE (x
) == VOIDmode
)
2785 value
= CONST_DOUBLE_LOW (x
);
2788 fatal_insn ("bad insn in frv_print_operand, bad const_double", x
);
2799 fputs (reg_names
[GPR_R0
], file
);
2803 fprintf (file
, "%d", frv_print_operand_jump_hint (current_output_insn
));
2807 /* Output small data area base register (gr16). */
2808 fputs (reg_names
[SDA_BASE_REG
], file
);
2812 /* Output pic register (gr17). */
2813 fputs (reg_names
[PIC_REGNO
], file
);
2817 /* Output the temporary integer CCR register. */
2818 fputs (reg_names
[ICR_TEMP
], file
);
2822 /* Output the temporary integer CC register. */
2823 fputs (reg_names
[ICC_TEMP
], file
);
2826 /* case 'a': print an address. */
2829 /* Print appropriate test for integer branch false operation. */
2830 fputs (comparison_string (reverse_condition (GET_CODE (x
)),
2831 XEXP (x
, 0)), file
);
2835 /* Print appropriate test for integer branch true operation. */
2836 fputs (comparison_string (GET_CODE (x
), XEXP (x
, 0)), file
);
2840 /* Print 1 for a NE and 0 for an EQ to give the final argument
2841 for a conditional instruction. */
2842 if (GET_CODE (x
) == NE
)
2845 else if (GET_CODE (x
) == EQ
)
2849 fatal_insn ("bad insn to frv_print_operand, 'e' modifier:", x
);
2853 /* Print appropriate test for floating point branch false operation. */
2854 switch (GET_CODE (x
))
2857 fatal_insn ("bad insn to frv_print_operand, 'F' modifier:", x
);
2859 case EQ
: fputs ("ne", file
); break;
2860 case NE
: fputs ("eq", file
); break;
2861 case LT
: fputs ("uge", file
); break;
2862 case LE
: fputs ("ug", file
); break;
2863 case GT
: fputs ("ule", file
); break;
2864 case GE
: fputs ("ul", file
); break;
2869 /* Print appropriate test for floating point branch true operation. */
2870 switch (GET_CODE (x
))
2873 fatal_insn ("bad insn to frv_print_operand, 'f' modifier:", x
);
2875 case EQ
: fputs ("eq", file
); break;
2876 case NE
: fputs ("ne", file
); break;
2877 case LT
: fputs ("lt", file
); break;
2878 case LE
: fputs ("le", file
); break;
2879 case GT
: fputs ("gt", file
); break;
2880 case GE
: fputs ("ge", file
); break;
2885 /* Print appropriate GOT function. */
2886 if (GET_CODE (x
) != CONST_INT
)
2887 fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x
);
2888 fputs (unspec_got_name (INTVAL (x
)), file
);
2892 /* Print 'i' if the operand is a constant, or is a memory reference that
2894 if (GET_CODE (x
) == MEM
)
2895 x
= ((GET_CODE (XEXP (x
, 0)) == PLUS
)
2896 ? XEXP (XEXP (x
, 0), 1)
2898 else if (GET_CODE (x
) == PLUS
)
2901 switch (GET_CODE (x
))
2915 /* For jump instructions, print 'i' if the operand is a constant or
2916 is an expression that adds a constant. */
2917 if (GET_CODE (x
) == CONST_INT
)
2922 if (GET_CODE (x
) == CONST_INT
2923 || (GET_CODE (x
) == PLUS
2924 && (GET_CODE (XEXP (x
, 1)) == CONST_INT
2925 || GET_CODE (XEXP (x
, 0)) == CONST_INT
)))
2931 /* Print the lower register of a double word register pair */
2932 if (GET_CODE (x
) == REG
)
2933 fputs (reg_names
[ REGNO (x
)+1 ], file
);
2935 fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x
);
2938 /* case 'l': print a LABEL_REF. */
2942 /* Print a memory reference for ld/st/jmp, %N prints a memory reference
2943 for the second word of double memory operations. */
2944 offset
= (code
== 'M') ? 0 : UNITS_PER_WORD
;
2945 switch (GET_CODE (x
))
2948 fatal_insn ("bad insn to frv_print_operand, 'M/N' modifier:", x
);
2951 frv_print_operand_memory_reference (file
, XEXP (x
, 0), offset
);
2959 frv_print_operand_memory_reference (file
, x
, offset
);
2965 /* Print the opcode of a command. */
2966 switch (GET_CODE (x
))
2969 fatal_insn ("bad insn to frv_print_operand, 'O' modifier:", x
);
2971 case PLUS
: fputs ("add", file
); break;
2972 case MINUS
: fputs ("sub", file
); break;
2973 case AND
: fputs ("and", file
); break;
2974 case IOR
: fputs ("or", file
); break;
2975 case XOR
: fputs ("xor", file
); break;
2976 case ASHIFT
: fputs ("sll", file
); break;
2977 case ASHIFTRT
: fputs ("sra", file
); break;
2978 case LSHIFTRT
: fputs ("srl", file
); break;
2982 /* case 'n': negate and print a constant int. */
2985 /* Print PIC label using operand as the number. */
2986 if (GET_CODE (x
) != CONST_INT
)
2987 fatal_insn ("bad insn to frv_print_operand, P modifier:", x
);
2989 fprintf (file
, ".LCF%ld", (long)INTVAL (x
));
2993 /* Print 'u' if the operand is a update load/store. */
2994 if (GET_CODE (x
) == MEM
&& GET_CODE (XEXP (x
, 0)) == PRE_MODIFY
)
2999 /* If value is 0, print gr0, otherwise it must be a register. */
3000 if (GET_CODE (x
) == CONST_INT
&& INTVAL (x
) == 0)
3001 fputs (reg_names
[GPR_R0
], file
);
3003 else if (GET_CODE (x
) == REG
)
3004 fputs (reg_names
[REGNO (x
)], file
);
3007 fatal_insn ("bad insn in frv_print_operand, z case", x
);
3011 /* Print constant in hex. */
3012 if (GET_CODE (x
) == CONST_INT
|| GET_CODE (x
) == CONST_DOUBLE
)
3014 fprintf (file
, "%s0x%.4lx", IMMEDIATE_PREFIX
, (long) value
);
3021 if (GET_CODE (x
) == REG
)
3022 fputs (reg_names
[REGNO (x
)], file
);
3024 else if (GET_CODE (x
) == CONST_INT
3025 || GET_CODE (x
) == CONST_DOUBLE
)
3026 fprintf (file
, "%s%ld", IMMEDIATE_PREFIX
, (long) value
);
3028 else if (frv_const_unspec_p (x
, &unspec
))
3029 frv_output_const_unspec (file
, &unspec
);
3031 else if (GET_CODE (x
) == MEM
)
3032 frv_print_operand_address (file
, XEXP (x
, 0));
3034 else if (CONSTANT_ADDRESS_P (x
))
3035 frv_print_operand_address (file
, x
);
3038 fatal_insn ("bad insn in frv_print_operand, 0 case", x
);
3043 fatal_insn ("frv_print_operand: unknown code", x
);
3051 frv_print_operand_punct_valid_p (unsigned char code
)
3053 return (code
== '.' || code
== '#' || code
== '@' || code
== '~'
3054 || code
== '*' || code
== '&');
3058 /* A C statement (sans semicolon) for initializing the variable CUM for the
3059 state at the beginning of the argument list. The variable has type
3060 `CUMULATIVE_ARGS'. The value of FNTYPE is the tree node for the data type
3061 of the function which will receive the args, or 0 if the args are to a
3062 compiler support library function. The value of INDIRECT is nonzero when
3063 processing an indirect call, for example a call through a function pointer.
3064 The value of INDIRECT is zero for a call to an explicitly named function, a
3065 library function call, or when `INIT_CUMULATIVE_ARGS' is used to find
3066 arguments for the function being compiled.
3068 When processing a call to a compiler support library function, LIBNAME
3069 identifies which one. It is a `symbol_ref' rtx which contains the name of
3070 the function, as a string. LIBNAME is 0 when an ordinary C function call is
3071 being processed. Thus, each time this macro is called, either LIBNAME or
3072 FNTYPE is nonzero, but never both of them at once. */
3075 frv_init_cumulative_args (CUMULATIVE_ARGS
*cum
,
3081 *cum
= FIRST_ARG_REGNUM
;
3083 if (TARGET_DEBUG_ARG
)
3085 fprintf (stderr
, "\ninit_cumulative_args:");
3086 if (!fndecl
&& fntype
)
3087 fputs (" indirect", stderr
);
3090 fputs (" incoming", stderr
);
3094 tree ret_type
= TREE_TYPE (fntype
);
3095 fprintf (stderr
, " return=%s,",
3096 get_tree_code_name (TREE_CODE (ret_type
)));
3099 if (libname
&& GET_CODE (libname
) == SYMBOL_REF
)
3100 fprintf (stderr
, " libname=%s", XSTR (libname
, 0));
3102 if (cfun
->returns_struct
)
3103 fprintf (stderr
, " return-struct");
3105 putc ('\n', stderr
);
3110 /* Return true if we should pass an argument on the stack rather than
3114 frv_must_pass_in_stack (machine_mode mode
, const_tree type
)
3116 if (mode
== BLKmode
)
3120 return AGGREGATE_TYPE_P (type
);
3123 /* If defined, a C expression that gives the alignment boundary, in bits, of an
3124 argument with the specified mode and type. If it is not defined,
3125 `PARM_BOUNDARY' is used for all arguments. */
3128 frv_function_arg_boundary (machine_mode mode ATTRIBUTE_UNUSED
,
3129 const_tree type ATTRIBUTE_UNUSED
)
3131 return BITS_PER_WORD
;
3135 frv_function_arg_1 (cumulative_args_t cum_v
, machine_mode mode
,
3136 const_tree type ATTRIBUTE_UNUSED
, bool named
,
3137 bool incoming ATTRIBUTE_UNUSED
)
3139 const CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
3141 machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3146 /* Return a marker for use in the call instruction. */
3147 if (xmode
== VOIDmode
)
3153 else if (arg_num
<= LAST_ARG_REGNUM
)
3155 ret
= gen_rtx_REG (xmode
, arg_num
);
3156 debstr
= reg_names
[arg_num
];
3165 if (TARGET_DEBUG_ARG
)
3167 "function_arg: words = %2d, mode = %4s, named = %d, size = %3d, arg = %s\n",
3168 arg_num
, GET_MODE_NAME (mode
), named
, GET_MODE_SIZE (mode
), debstr
);
3174 frv_function_arg (cumulative_args_t cum
, machine_mode mode
,
3175 const_tree type
, bool named
)
3177 return frv_function_arg_1 (cum
, mode
, type
, named
, false);
3181 frv_function_incoming_arg (cumulative_args_t cum
, machine_mode mode
,
3182 const_tree type
, bool named
)
3184 return frv_function_arg_1 (cum
, mode
, type
, named
, true);
3188 /* A C statement (sans semicolon) to update the summarizer variable CUM to
3189 advance past an argument in the argument list. The values MODE, TYPE and
3190 NAMED describe that argument. Once this is done, the variable CUM is
3191 suitable for analyzing the *following* argument with `FUNCTION_ARG', etc.
3193 This macro need not do anything if the argument in question was passed on
3194 the stack. The compiler knows how to track the amount of stack space used
3195 for arguments without any special help. */
3198 frv_function_arg_advance (cumulative_args_t cum_v
,
3200 const_tree type ATTRIBUTE_UNUSED
,
3203 CUMULATIVE_ARGS
*cum
= get_cumulative_args (cum_v
);
3205 machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3206 int bytes
= GET_MODE_SIZE (xmode
);
3207 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3210 *cum
= arg_num
+ words
;
3212 if (TARGET_DEBUG_ARG
)
3214 "function_adv: words = %2d, mode = %4s, named = %d, size = %3d\n",
3215 arg_num
, GET_MODE_NAME (mode
), named
, words
* UNITS_PER_WORD
);
3219 /* A C expression for the number of words, at the beginning of an argument,
3220 must be put in registers. The value must be zero for arguments that are
3221 passed entirely in registers or that are entirely pushed on the stack.
3223 On some machines, certain arguments must be passed partially in registers
3224 and partially in memory. On these machines, typically the first N words of
3225 arguments are passed in registers, and the rest on the stack. If a
3226 multi-word argument (a `double' or a structure) crosses that boundary, its
3227 first few words must be passed in registers and the rest must be pushed.
3228 This macro tells the compiler when this occurs, and how many of the words
3229 should go in registers.
3231 `FUNCTION_ARG' for these arguments should return the first register to be
3232 used by the caller for this argument; likewise `FUNCTION_INCOMING_ARG', for
3233 the called function. */
3236 frv_arg_partial_bytes (cumulative_args_t cum
, machine_mode mode
,
3237 tree type ATTRIBUTE_UNUSED
, bool named ATTRIBUTE_UNUSED
)
3240 machine_mode xmode
= (mode
== BLKmode
) ? SImode
: mode
;
3241 int bytes
= GET_MODE_SIZE (xmode
);
3242 int words
= (bytes
+ UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
3243 int arg_num
= *get_cumulative_args (cum
);
3246 ret
= ((arg_num
<= LAST_ARG_REGNUM
&& arg_num
+ words
> LAST_ARG_REGNUM
+1)
3247 ? LAST_ARG_REGNUM
- arg_num
+ 1
3249 ret
*= UNITS_PER_WORD
;
3251 if (TARGET_DEBUG_ARG
&& ret
)
3252 fprintf (stderr
, "frv_arg_partial_bytes: %d\n", ret
);
3258 /* Implements TARGET_FUNCTION_VALUE. */
3261 frv_function_value (const_tree valtype
,
3262 const_tree fn_decl_or_type ATTRIBUTE_UNUSED
,
3263 bool outgoing ATTRIBUTE_UNUSED
)
3265 return gen_rtx_REG (TYPE_MODE (valtype
), RETURN_VALUE_REGNUM
);
3269 /* Implements TARGET_LIBCALL_VALUE. */
3272 frv_libcall_value (machine_mode mode
,
3273 const_rtx fun ATTRIBUTE_UNUSED
)
3275 return gen_rtx_REG (mode
, RETURN_VALUE_REGNUM
);
3279 /* Implements FUNCTION_VALUE_REGNO_P. */
3282 frv_function_value_regno_p (const unsigned int regno
)
3284 return (regno
== RETURN_VALUE_REGNUM
);
3287 /* Return true if a register is ok to use as a base or index register. */
3289 static FRV_INLINE
int
3290 frv_regno_ok_for_base_p (int regno
, int strict_p
)
3296 return (reg_renumber
[regno
] >= 0 && GPR_P (reg_renumber
[regno
]));
3298 if (regno
== ARG_POINTER_REGNUM
)
3301 return (regno
>= FIRST_PSEUDO_REGISTER
);
3305 /* A C compound statement with a conditional `goto LABEL;' executed if X (an
3306 RTX) is a legitimate memory address on the target machine for a memory
3307 operand of mode MODE.
3309 It usually pays to define several simpler macros to serve as subroutines for
3310 this one. Otherwise it may be too complicated to understand.
3312 This macro must exist in two variants: a strict variant and a non-strict
3313 one. The strict variant is used in the reload pass. It must be defined so
3314 that any pseudo-register that has not been allocated a hard register is
3315 considered a memory reference. In contexts where some kind of register is
3316 required, a pseudo-register with no hard register must be rejected.
3318 The non-strict variant is used in other passes. It must be defined to
3319 accept all pseudo-registers in every context where some kind of register is
3322 Compiler source files that want to use the strict variant of this macro
3323 define the macro `REG_OK_STRICT'. You should use an `#ifdef REG_OK_STRICT'
3324 conditional to define the strict variant in that case and the non-strict
3327 Normally, constant addresses which are the sum of a `symbol_ref' and an
3328 integer are stored inside a `const' RTX to mark them as constant.
3329 Therefore, there is no need to recognize such sums specifically as
3330 legitimate addresses. Normally you would simply recognize any `const' as
3333 Usually `TARGET_PRINT_OPERAND_ADDRESS' is not prepared to handle
3334 constant sums that are not marked with `const'. It assumes that a
3335 naked `plus' indicates indexing. If so, then you *must* reject such
3336 naked constant sums as illegitimate addresses, so that none of them
3337 will be given to `TARGET_PRINT_OPERAND_ADDRESS'. */
3340 frv_legitimate_address_p_1 (machine_mode mode
,
3344 int allow_double_reg_p
)
3348 HOST_WIDE_INT value
;
3351 if (FRV_SYMBOL_REF_TLS_P (x
))
3354 switch (GET_CODE (x
))
3361 if (GET_CODE (x
) != REG
)
3367 ret
= frv_regno_ok_for_base_p (REGNO (x
), strict_p
);
3373 if (GET_CODE (x0
) != REG
3374 || ! frv_regno_ok_for_base_p (REGNO (x0
), strict_p
)
3375 || GET_CODE (x1
) != PLUS
3376 || ! rtx_equal_p (x0
, XEXP (x1
, 0))
3377 || GET_CODE (XEXP (x1
, 1)) != REG
3378 || ! frv_regno_ok_for_base_p (REGNO (XEXP (x1
, 1)), strict_p
))
3385 /* 12-bit immediate */
3390 ret
= IN_RANGE (INTVAL (x
), -2048, 2047);
3392 /* If we can't use load/store double operations, make sure we can
3393 address the second word. */
3394 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3395 ret
= IN_RANGE (INTVAL (x
) + GET_MODE_SIZE (mode
) - 1,
3404 if (GET_CODE (x0
) == SUBREG
)
3405 x0
= SUBREG_REG (x0
);
3407 if (GET_CODE (x0
) != REG
)
3410 regno0
= REGNO (x0
);
3411 if (!frv_regno_ok_for_base_p (regno0
, strict_p
))
3414 switch (GET_CODE (x1
))
3420 x1
= SUBREG_REG (x1
);
3421 if (GET_CODE (x1
) != REG
)
3427 /* Do not allow reg+reg addressing for modes > 1 word if we
3428 can't depend on having move double instructions. */
3429 if (!allow_double_reg_p
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3432 ret
= frv_regno_ok_for_base_p (REGNO (x1
), strict_p
);
3436 /* 12-bit immediate */
3441 value
= INTVAL (x1
);
3442 ret
= IN_RANGE (value
, -2048, 2047);
3444 /* If we can't use load/store double operations, make sure we can
3445 address the second word. */
3446 if (ret
&& GET_MODE_SIZE (mode
) > UNITS_PER_WORD
)
3447 ret
= IN_RANGE (value
+ GET_MODE_SIZE (mode
) - 1, -2048, 2047);
3452 if (!condexec_p
&& got12_operand (x1
, VOIDmode
))
3460 if (TARGET_DEBUG_ADDR
)
3462 fprintf (stderr
, "\n========== legitimate_address_p, mode = %s, result = %d, addresses are %sstrict%s\n",
3463 GET_MODE_NAME (mode
), ret
, (strict_p
) ? "" : "not ",
3464 (condexec_p
) ? ", inside conditional code" : "");
3472 frv_legitimate_address_p (machine_mode mode
, rtx x
, bool strict_p
)
3474 return frv_legitimate_address_p_1 (mode
, x
, strict_p
, FALSE
, FALSE
);
3477 /* Given an ADDR, generate code to inline the PLT. */
3479 gen_inlined_tls_plt (rtx addr
)
3482 rtx picreg
= get_hard_reg_initial_val (Pmode
, FDPIC_REG
);
3485 dest
= gen_reg_rtx (DImode
);
3492 lddi.p @(gr15, #gottlsdesc12(ADDR)), gr8
3493 calll #gettlsoff(ADDR)@(gr8, gr0)
3495 emit_insn (gen_tls_lddi (dest
, addr
, picreg
));
3502 sethi.p #gottlsdeschi(ADDR), gr8
3503 setlo #gottlsdesclo(ADDR), gr8
3504 ldd #tlsdesc(ADDR)@(gr15, gr8), gr8
3505 calll #gettlsoff(ADDR)@(gr8, gr0)
3507 rtx reguse
= gen_reg_rtx (Pmode
);
3508 emit_insn (gen_tlsoff_hilo (reguse
, addr
, GEN_INT (R_FRV_GOTTLSDESCHI
)));
3509 emit_insn (gen_tls_tlsdesc_ldd (dest
, picreg
, reguse
, addr
));
3512 retval
= gen_reg_rtx (Pmode
);
3513 emit_insn (gen_tls_indirect_call (retval
, addr
, dest
, picreg
));
3517 /* Emit a TLSMOFF or TLSMOFF12 offset, depending on -mTLS. Returns
3518 the destination address. */
3520 gen_tlsmoff (rtx addr
, rtx reg
)
3522 rtx dest
= gen_reg_rtx (Pmode
);
3526 /* sethi.p #tlsmoffhi(x), grA
3527 setlo #tlsmofflo(x), grA
3529 dest
= gen_reg_rtx (Pmode
);
3530 emit_insn (gen_tlsoff_hilo (dest
, addr
,
3531 GEN_INT (R_FRV_TLSMOFFHI
)));
3532 dest
= gen_rtx_PLUS (Pmode
, dest
, reg
);
3536 /* addi grB, #tlsmoff12(x), grC
3538 ld/st @(grB, #tlsmoff12(x)), grC
3540 dest
= gen_reg_rtx (Pmode
);
3541 emit_insn (gen_symGOTOFF2reg_i (dest
, addr
, reg
,
3542 GEN_INT (R_FRV_TLSMOFF12
)));
3547 /* Generate code for a TLS address. */
3549 frv_legitimize_tls_address (rtx addr
, enum tls_model model
)
3551 rtx dest
, tp
= gen_rtx_REG (Pmode
, 29);
3552 rtx picreg
= get_hard_reg_initial_val (Pmode
, 15);
3556 case TLS_MODEL_INITIAL_EXEC
:
3560 ldi @(gr15, #gottlsoff12(x)), gr5
3562 dest
= gen_reg_rtx (Pmode
);
3563 emit_insn (gen_tls_load_gottlsoff12 (dest
, addr
, picreg
));
3564 dest
= gen_rtx_PLUS (Pmode
, tp
, dest
);
3568 /* -fPIC or anything else.
3570 sethi.p #gottlsoffhi(x), gr14
3571 setlo #gottlsofflo(x), gr14
3572 ld #tlsoff(x)@(gr15, gr14), gr9
3574 rtx tmp
= gen_reg_rtx (Pmode
);
3575 dest
= gen_reg_rtx (Pmode
);
3576 emit_insn (gen_tlsoff_hilo (tmp
, addr
,
3577 GEN_INT (R_FRV_GOTTLSOFF_HI
)));
3579 emit_insn (gen_tls_tlsoff_ld (dest
, picreg
, tmp
, addr
));
3580 dest
= gen_rtx_PLUS (Pmode
, tp
, dest
);
3583 case TLS_MODEL_LOCAL_DYNAMIC
:
3587 if (TARGET_INLINE_PLT
)
3588 retval
= gen_inlined_tls_plt (GEN_INT (0));
3591 /* call #gettlsoff(0) */
3592 retval
= gen_reg_rtx (Pmode
);
3593 emit_insn (gen_call_gettlsoff (retval
, GEN_INT (0), picreg
));
3596 reg
= gen_reg_rtx (Pmode
);
3597 emit_insn (gen_rtx_SET (reg
, gen_rtx_PLUS (Pmode
, retval
, tp
)));
3599 dest
= gen_tlsmoff (addr
, reg
);
3602 dest = gen_reg_rtx (Pmode);
3603 emit_insn (gen_tlsoff_hilo (dest, addr,
3604 GEN_INT (R_FRV_TLSMOFFHI)));
3605 dest = gen_rtx_PLUS (Pmode, dest, reg);
3609 case TLS_MODEL_LOCAL_EXEC
:
3610 dest
= gen_tlsmoff (addr
, gen_rtx_REG (Pmode
, 29));
3612 case TLS_MODEL_GLOBAL_DYNAMIC
:
3616 if (TARGET_INLINE_PLT
)
3617 retval
= gen_inlined_tls_plt (addr
);
3620 /* call #gettlsoff(x) */
3621 retval
= gen_reg_rtx (Pmode
);
3622 emit_insn (gen_call_gettlsoff (retval
, addr
, picreg
));
3624 dest
= gen_rtx_PLUS (Pmode
, retval
, tp
);
3635 frv_legitimize_address (rtx x
,
3636 rtx oldx ATTRIBUTE_UNUSED
,
3637 machine_mode mode ATTRIBUTE_UNUSED
)
3639 if (GET_CODE (x
) == SYMBOL_REF
)
3641 enum tls_model model
= SYMBOL_REF_TLS_MODEL (x
);
3643 return frv_legitimize_tls_address (x
, model
);
3649 /* Test whether a local function descriptor is canonical, i.e.,
3650 whether we can use FUNCDESC_GOTOFF to compute the address of the
3654 frv_local_funcdesc_p (rtx fnx
)
3657 enum symbol_visibility vis
;
3660 if (! SYMBOL_REF_LOCAL_P (fnx
))
3663 fn
= SYMBOL_REF_DECL (fnx
);
3668 vis
= DECL_VISIBILITY (fn
);
3670 if (vis
== VISIBILITY_PROTECTED
)
3671 /* Private function descriptors for protected functions are not
3672 canonical. Temporarily change the visibility to global. */
3673 vis
= VISIBILITY_DEFAULT
;
3674 else if (flag_shlib
)
3675 /* If we're already compiling for a shared library (that, unlike
3676 executables, can't assume that the existence of a definition
3677 implies local binding), we can skip the re-testing. */
3680 ret
= default_binds_local_p_1 (fn
, flag_pic
);
3682 DECL_VISIBILITY (fn
) = vis
;
3687 /* Load the _gp symbol into DEST. SRC is supposed to be the FDPIC
3691 frv_gen_GPsym2reg (rtx dest
, rtx src
)
3693 tree gp
= get_identifier ("_gp");
3694 rtx gp_sym
= gen_rtx_SYMBOL_REF (Pmode
, IDENTIFIER_POINTER (gp
));
3696 return gen_symGOT2reg (dest
, gp_sym
, src
, GEN_INT (R_FRV_GOT12
));
3700 unspec_got_name (int i
)
3704 case R_FRV_GOT12
: return "got12";
3705 case R_FRV_GOTHI
: return "gothi";
3706 case R_FRV_GOTLO
: return "gotlo";
3707 case R_FRV_FUNCDESC
: return "funcdesc";
3708 case R_FRV_FUNCDESC_GOT12
: return "gotfuncdesc12";
3709 case R_FRV_FUNCDESC_GOTHI
: return "gotfuncdeschi";
3710 case R_FRV_FUNCDESC_GOTLO
: return "gotfuncdesclo";
3711 case R_FRV_FUNCDESC_VALUE
: return "funcdescvalue";
3712 case R_FRV_FUNCDESC_GOTOFF12
: return "gotofffuncdesc12";
3713 case R_FRV_FUNCDESC_GOTOFFHI
: return "gotofffuncdeschi";
3714 case R_FRV_FUNCDESC_GOTOFFLO
: return "gotofffuncdesclo";
3715 case R_FRV_GOTOFF12
: return "gotoff12";
3716 case R_FRV_GOTOFFHI
: return "gotoffhi";
3717 case R_FRV_GOTOFFLO
: return "gotofflo";
3718 case R_FRV_GPREL12
: return "gprel12";
3719 case R_FRV_GPRELHI
: return "gprelhi";
3720 case R_FRV_GPRELLO
: return "gprello";
3721 case R_FRV_GOTTLSOFF_HI
: return "gottlsoffhi";
3722 case R_FRV_GOTTLSOFF_LO
: return "gottlsofflo";
3723 case R_FRV_TLSMOFFHI
: return "tlsmoffhi";
3724 case R_FRV_TLSMOFFLO
: return "tlsmofflo";
3725 case R_FRV_TLSMOFF12
: return "tlsmoff12";
3726 case R_FRV_TLSDESCHI
: return "tlsdeschi";
3727 case R_FRV_TLSDESCLO
: return "tlsdesclo";
3728 case R_FRV_GOTTLSDESCHI
: return "gottlsdeschi";
3729 case R_FRV_GOTTLSDESCLO
: return "gottlsdesclo";
3730 default: gcc_unreachable ();
3734 /* Write the assembler syntax for UNSPEC to STREAM. Note that any offset
3735 is added inside the relocation operator. */
3738 frv_output_const_unspec (FILE *stream
, const struct frv_unspec
*unspec
)
3740 fprintf (stream
, "#%s(", unspec_got_name (unspec
->reloc
));
3741 output_addr_const (stream
, plus_constant (Pmode
, unspec
->symbol
,
3743 fputs (")", stream
);
3746 /* Implement FIND_BASE_TERM. See whether ORIG_X represents #gprel12(foo)
3747 or #gotoff12(foo) for some small data symbol foo. If so, return foo,
3748 otherwise return ORIG_X. */
3751 frv_find_base_term (rtx x
)
3753 struct frv_unspec unspec
;
3755 if (frv_const_unspec_p (x
, &unspec
)
3756 && frv_small_data_reloc_p (unspec
.symbol
, unspec
.reloc
))
3757 return plus_constant (Pmode
, unspec
.symbol
, unspec
.offset
);
3762 /* Return 1 if operand is a valid FRV address. CONDEXEC_P is true if
3763 the operand is used by a predicated instruction. */
3766 frv_legitimate_memory_operand (rtx op
, machine_mode mode
, int condexec_p
)
3768 return ((GET_MODE (op
) == mode
|| mode
== VOIDmode
)
3769 && GET_CODE (op
) == MEM
3770 && frv_legitimate_address_p_1 (mode
, XEXP (op
, 0),
3771 reload_completed
, condexec_p
, FALSE
));
3775 frv_expand_fdpic_call (rtx
*operands
, bool ret_value
, bool sibcall
)
3777 rtx lr
= gen_rtx_REG (Pmode
, LR_REGNO
);
3778 rtx picreg
= get_hard_reg_initial_val (SImode
, FDPIC_REG
);
3784 rvrtx
= operands
[0];
3788 addr
= XEXP (operands
[0], 0);
3790 /* Inline PLTs if we're optimizing for speed. We'd like to inline
3791 any calls that would involve a PLT, but can't tell, since we
3792 don't know whether an extern function is going to be provided by
3793 a separate translation unit or imported from a separate module.
3794 When compiling for shared libraries, if the function has default
3795 visibility, we assume it's overridable, so we inline the PLT, but
3796 for executables, we don't really have a way to make a good
3797 decision: a function is as likely to be imported from a shared
3798 library as it is to be defined in the executable itself. We
3799 assume executables will get global functions defined locally,
3800 whereas shared libraries will have them potentially overridden,
3801 so we only inline PLTs when compiling for shared libraries.
3803 In order to mark a function as local to a shared library, any
3804 non-default visibility attribute suffices. Unfortunately,
3805 there's no simple way to tag a function declaration as ``in a
3806 different module'', which we could then use to trigger PLT
3807 inlining on executables. There's -minline-plt, but it affects
3808 all external functions, so one would have to also mark function
3809 declarations available in the same module with non-default
3810 visibility, which is advantageous in itself. */
3811 if (GET_CODE (addr
) == SYMBOL_REF
3812 && ((!SYMBOL_REF_LOCAL_P (addr
) && TARGET_INLINE_PLT
)
3816 dest
= gen_reg_rtx (SImode
);
3818 x
= gen_symGOTOFF2reg_hilo (dest
, addr
, OUR_FDPIC_REG
,
3819 GEN_INT (R_FRV_FUNCDESC_GOTOFF12
));
3821 x
= gen_symGOTOFF2reg (dest
, addr
, OUR_FDPIC_REG
,
3822 GEN_INT (R_FRV_FUNCDESC_GOTOFF12
));
3824 crtl
->uses_pic_offset_table
= TRUE
;
3827 else if (GET_CODE (addr
) == SYMBOL_REF
)
3829 /* These are always either local, or handled through a local
3832 c
= gen_call_value_fdpicsi (rvrtx
, addr
, operands
[1],
3833 operands
[2], picreg
, lr
);
3835 c
= gen_call_fdpicsi (addr
, operands
[1], operands
[2], picreg
, lr
);
3839 else if (! ldd_address_operand (addr
, Pmode
))
3840 addr
= force_reg (Pmode
, addr
);
3842 picreg
= gen_reg_rtx (DImode
);
3843 emit_insn (gen_movdi_ldd (picreg
, addr
));
3845 if (sibcall
&& ret_value
)
3846 c
= gen_sibcall_value_fdpicdi (rvrtx
, picreg
, const0_rtx
);
3848 c
= gen_sibcall_fdpicdi (picreg
, const0_rtx
);
3850 c
= gen_call_value_fdpicdi (rvrtx
, picreg
, const0_rtx
, lr
);
3852 c
= gen_call_fdpicdi (picreg
, const0_rtx
, lr
);
3856 /* Look for a SYMBOL_REF of a function in an rtx. We always want to
3857 process these separately from any offsets, such that we add any
3858 offsets to the function descriptor (the actual pointer), not to the
3859 function address. */
3862 frv_function_symbol_referenced_p (rtx x
)
3868 if (GET_CODE (x
) == SYMBOL_REF
)
3869 return SYMBOL_REF_FUNCTION_P (x
);
3871 length
= GET_RTX_LENGTH (GET_CODE (x
));
3872 format
= GET_RTX_FORMAT (GET_CODE (x
));
3874 for (j
= 0; j
< length
; ++j
)
3879 if (frv_function_symbol_referenced_p (XEXP (x
, j
)))
3885 if (XVEC (x
, j
) != 0)
3888 for (k
= 0; k
< XVECLEN (x
, j
); ++k
)
3889 if (frv_function_symbol_referenced_p (XVECEXP (x
, j
, k
)))
3895 /* Nothing to do. */
3903 /* Return true if the memory operand is one that can be conditionally
3907 condexec_memory_operand (rtx op
, machine_mode mode
)
3909 machine_mode op_mode
= GET_MODE (op
);
3912 if (mode
!= VOIDmode
&& op_mode
!= mode
)
3927 if (GET_CODE (op
) != MEM
)
3930 addr
= XEXP (op
, 0);
3931 return frv_legitimate_address_p_1 (mode
, addr
, reload_completed
, TRUE
, FALSE
);
3934 /* Return true if the bare return instruction can be used outside of the
3935 epilog code. For frv, we only do it if there was no stack allocation. */
3938 direct_return_p (void)
3942 if (!reload_completed
)
3945 info
= frv_stack_info ();
3946 return (info
->total_size
== 0);
3951 frv_emit_move (machine_mode mode
, rtx dest
, rtx src
)
3953 if (GET_CODE (src
) == SYMBOL_REF
)
3955 enum tls_model model
= SYMBOL_REF_TLS_MODEL (src
);
3957 src
= frv_legitimize_tls_address (src
, model
);
3963 if (frv_emit_movsi (dest
, src
))
3972 if (!reload_in_progress
3973 && !reload_completed
3974 && !register_operand (dest
, mode
)
3975 && !reg_or_0_operand (src
, mode
))
3976 src
= copy_to_mode_reg (mode
, src
);
3983 emit_insn (gen_rtx_SET (dest
, src
));
3986 /* Emit code to handle a MOVSI, adding in the small data register or pic
3987 register if needed to load up addresses. Return TRUE if the appropriate
3988 instructions are emitted. */
3991 frv_emit_movsi (rtx dest
, rtx src
)
3993 int base_regno
= -1;
3996 struct frv_unspec old_unspec
;
3998 if (!reload_in_progress
3999 && !reload_completed
4000 && !register_operand (dest
, SImode
)
4001 && (!reg_or_0_operand (src
, SImode
)
4002 /* Virtual registers will almost always be replaced by an
4003 add instruction, so expose this to CSE by copying to
4004 an intermediate register. */
4005 || (GET_CODE (src
) == REG
4006 && IN_RANGE (REGNO (src
),
4007 FIRST_VIRTUAL_REGISTER
,
4008 LAST_VIRTUAL_POINTER_REGISTER
))))
4010 emit_insn (gen_rtx_SET (dest
, copy_to_mode_reg (SImode
, src
)));
4014 /* Explicitly add in the PIC or small data register if needed. */
4015 switch (GET_CODE (src
))
4024 /* Using GPREL12, we use a single GOT entry for all symbols
4025 in read-only sections, but trade sequences such as:
4027 sethi #gothi(label), gr#
4028 setlo #gotlo(label), gr#
4033 ld @(gr15,#got12(_gp)), gr#
4034 sethi #gprelhi(label), gr##
4035 setlo #gprello(label), gr##
4038 We may often be able to share gr# for multiple
4039 computations of GPREL addresses, and we may often fold
4040 the final add into the pair of registers of a load or
4041 store instruction, so it's often profitable. Even when
4042 optimizing for size, we're trading a GOT entry for an
4043 additional instruction, which trades GOT space
4044 (read-write) for code size (read-only, shareable), as
4045 long as the symbol is not used in more than two different
4048 With -fpie/-fpic, we'd be trading a single load for a
4049 sequence of 4 instructions, because the offset of the
4050 label can't be assumed to be addressable with 12 bits, so
4051 we don't do this. */
4052 if (TARGET_GPREL_RO
)
4053 unspec
= R_FRV_GPREL12
;
4055 unspec
= R_FRV_GOT12
;
4058 base_regno
= PIC_REGNO
;
4063 if (frv_const_unspec_p (src
, &old_unspec
))
4066 if (TARGET_FDPIC
&& frv_function_symbol_referenced_p (XEXP (src
, 0)))
4069 src
= force_reg (GET_MODE (XEXP (src
, 0)), XEXP (src
, 0));
4070 emit_move_insn (dest
, src
);
4075 sym
= XEXP (sym
, 0);
4076 if (GET_CODE (sym
) == PLUS
4077 && GET_CODE (XEXP (sym
, 0)) == SYMBOL_REF
4078 && GET_CODE (XEXP (sym
, 1)) == CONST_INT
)
4079 sym
= XEXP (sym
, 0);
4080 if (GET_CODE (sym
) == SYMBOL_REF
)
4082 else if (GET_CODE (sym
) == LABEL_REF
)
4085 goto handle_whatever
;
4093 enum tls_model model
= SYMBOL_REF_TLS_MODEL (sym
);
4097 src
= frv_legitimize_tls_address (src
, model
);
4098 emit_move_insn (dest
, src
);
4102 if (SYMBOL_REF_FUNCTION_P (sym
))
4104 if (frv_local_funcdesc_p (sym
))
4105 unspec
= R_FRV_FUNCDESC_GOTOFF12
;
4107 unspec
= R_FRV_FUNCDESC_GOT12
;
4111 if (CONSTANT_POOL_ADDRESS_P (sym
))
4112 switch (GET_CODE (get_pool_constant (sym
)))
4119 unspec
= R_FRV_GOTOFF12
;
4124 if (TARGET_GPREL_RO
)
4125 unspec
= R_FRV_GPREL12
;
4127 unspec
= R_FRV_GOT12
;
4130 else if (SYMBOL_REF_LOCAL_P (sym
)
4131 && !SYMBOL_REF_EXTERNAL_P (sym
)
4132 && SYMBOL_REF_DECL (sym
)
4133 && (!DECL_P (SYMBOL_REF_DECL (sym
))
4134 || !DECL_COMMON (SYMBOL_REF_DECL (sym
))))
4136 tree decl
= SYMBOL_REF_DECL (sym
);
4137 tree init
= TREE_CODE (decl
) == VAR_DECL
4138 ? DECL_INITIAL (decl
)
4139 : TREE_CODE (decl
) == CONSTRUCTOR
4142 bool named_section
, readonly
;
4144 if (init
&& init
!= error_mark_node
)
4145 reloc
= compute_reloc_for_constant (init
);
4147 named_section
= TREE_CODE (decl
) == VAR_DECL
4148 && lookup_attribute ("section", DECL_ATTRIBUTES (decl
));
4149 readonly
= decl_readonly_section (decl
, reloc
);
4152 unspec
= R_FRV_GOT12
;
4154 unspec
= R_FRV_GOTOFF12
;
4155 else if (readonly
&& TARGET_GPREL_RO
)
4156 unspec
= R_FRV_GPREL12
;
4158 unspec
= R_FRV_GOT12
;
4161 unspec
= R_FRV_GOT12
;
4165 else if (SYMBOL_REF_SMALL_P (sym
))
4166 base_regno
= SDA_BASE_REG
;
4169 base_regno
= PIC_REGNO
;
4174 if (base_regno
>= 0)
4176 if (GET_CODE (sym
) == SYMBOL_REF
&& SYMBOL_REF_SMALL_P (sym
))
4177 emit_insn (gen_symGOTOFF2reg (dest
, src
,
4178 gen_rtx_REG (Pmode
, base_regno
),
4179 GEN_INT (R_FRV_GPREL12
)));
4181 emit_insn (gen_symGOTOFF2reg_hilo (dest
, src
,
4182 gen_rtx_REG (Pmode
, base_regno
),
4183 GEN_INT (R_FRV_GPREL12
)));
4184 if (base_regno
== PIC_REGNO
)
4185 crtl
->uses_pic_offset_table
= TRUE
;
4193 /* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
4194 new uses of it once reload has begun. */
4195 gcc_assert (!reload_in_progress
&& !reload_completed
);
4199 case R_FRV_GOTOFF12
:
4200 if (!frv_small_data_reloc_p (sym
, unspec
))
4201 x
= gen_symGOTOFF2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4204 x
= gen_symGOTOFF2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4207 if (!frv_small_data_reloc_p (sym
, unspec
))
4208 x
= gen_symGPREL2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4211 x
= gen_symGPREL2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4213 case R_FRV_FUNCDESC_GOTOFF12
:
4215 x
= gen_symGOTOFF2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4218 x
= gen_symGOTOFF2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4222 x
= gen_symGOT2reg_hilo (dest
, src
, OUR_FDPIC_REG
,
4225 x
= gen_symGOT2reg (dest
, src
, OUR_FDPIC_REG
, GEN_INT (unspec
));
4229 crtl
->uses_pic_offset_table
= TRUE
;
4238 /* Return a string to output a single word move. */
4241 output_move_single (rtx operands
[], rtx insn
)
4243 rtx dest
= operands
[0];
4244 rtx src
= operands
[1];
4246 if (GET_CODE (dest
) == REG
)
4248 int dest_regno
= REGNO (dest
);
4249 machine_mode mode
= GET_MODE (dest
);
4251 if (GPR_P (dest_regno
))
4253 if (GET_CODE (src
) == REG
)
4255 /* gpr <- some sort of register */
4256 int src_regno
= REGNO (src
);
4258 if (GPR_P (src_regno
))
4259 return "mov %1, %0";
4261 else if (FPR_P (src_regno
))
4262 return "movfg %1, %0";
4264 else if (SPR_P (src_regno
))
4265 return "movsg %1, %0";
4268 else if (GET_CODE (src
) == MEM
)
4277 return "ldsb%I1%U1 %M1,%0";
4280 return "ldsh%I1%U1 %M1,%0";
4284 return "ld%I1%U1 %M1, %0";
4288 else if (GET_CODE (src
) == CONST_INT
4289 || GET_CODE (src
) == CONST_DOUBLE
)
4291 /* gpr <- integer/floating constant */
4292 HOST_WIDE_INT value
;
4294 if (GET_CODE (src
) == CONST_INT
)
4295 value
= INTVAL (src
);
4297 else if (mode
== SFmode
)
4302 REAL_VALUE_FROM_CONST_DOUBLE (rv
, src
);
4303 REAL_VALUE_TO_TARGET_SINGLE (rv
, l
);
4308 value
= CONST_DOUBLE_LOW (src
);
4310 if (IN_RANGE (value
, -32768, 32767))
4311 return "setlos %1, %0";
4316 else if (GET_CODE (src
) == SYMBOL_REF
4317 || GET_CODE (src
) == LABEL_REF
4318 || GET_CODE (src
) == CONST
)
4324 else if (FPR_P (dest_regno
))
4326 if (GET_CODE (src
) == REG
)
4328 /* fpr <- some sort of register */
4329 int src_regno
= REGNO (src
);
4331 if (GPR_P (src_regno
))
4332 return "movgf %1, %0";
4334 else if (FPR_P (src_regno
))
4336 if (TARGET_HARD_FLOAT
)
4337 return "fmovs %1, %0";
4339 return "mor %1, %1, %0";
4343 else if (GET_CODE (src
) == MEM
)
4352 return "ldbf%I1%U1 %M1,%0";
4355 return "ldhf%I1%U1 %M1,%0";
4359 return "ldf%I1%U1 %M1, %0";
4363 else if (ZERO_P (src
))
4364 return "movgf %., %0";
4367 else if (SPR_P (dest_regno
))
4369 if (GET_CODE (src
) == REG
)
4371 /* spr <- some sort of register */
4372 int src_regno
= REGNO (src
);
4374 if (GPR_P (src_regno
))
4375 return "movgs %1, %0";
4377 else if (ZERO_P (src
))
4378 return "movgs %., %0";
4382 else if (GET_CODE (dest
) == MEM
)
4384 if (GET_CODE (src
) == REG
)
4386 int src_regno
= REGNO (src
);
4387 machine_mode mode
= GET_MODE (dest
);
4389 if (GPR_P (src_regno
))
4397 return "stb%I0%U0 %1, %M0";
4400 return "sth%I0%U0 %1, %M0";
4404 return "st%I0%U0 %1, %M0";
4408 else if (FPR_P (src_regno
))
4416 return "stbf%I0%U0 %1, %M0";
4419 return "sthf%I0%U0 %1, %M0";
4423 return "stf%I0%U0 %1, %M0";
4428 else if (ZERO_P (src
))
4430 switch (GET_MODE (dest
))
4436 return "stb%I0%U0 %., %M0";
4439 return "sth%I0%U0 %., %M0";
4443 return "st%I0%U0 %., %M0";
4448 fatal_insn ("bad output_move_single operand", insn
);
4453 /* Return a string to output a double word move. */
4456 output_move_double (rtx operands
[], rtx insn
)
4458 rtx dest
= operands
[0];
4459 rtx src
= operands
[1];
4460 machine_mode mode
= GET_MODE (dest
);
4462 if (GET_CODE (dest
) == REG
)
4464 int dest_regno
= REGNO (dest
);
4466 if (GPR_P (dest_regno
))
4468 if (GET_CODE (src
) == REG
)
4470 /* gpr <- some sort of register */
4471 int src_regno
= REGNO (src
);
4473 if (GPR_P (src_regno
))
4476 else if (FPR_P (src_regno
))
4478 if (((dest_regno
- GPR_FIRST
) & 1) == 0
4479 && ((src_regno
- FPR_FIRST
) & 1) == 0)
4480 return "movfgd %1, %0";
4486 else if (GET_CODE (src
) == MEM
)
4489 if (dbl_memory_one_insn_operand (src
, mode
))
4490 return "ldd%I1%U1 %M1, %0";
4495 else if (GET_CODE (src
) == CONST_INT
4496 || GET_CODE (src
) == CONST_DOUBLE
)
4500 else if (FPR_P (dest_regno
))
4502 if (GET_CODE (src
) == REG
)
4504 /* fpr <- some sort of register */
4505 int src_regno
= REGNO (src
);
4507 if (GPR_P (src_regno
))
4509 if (((dest_regno
- FPR_FIRST
) & 1) == 0
4510 && ((src_regno
- GPR_FIRST
) & 1) == 0)
4511 return "movgfd %1, %0";
4516 else if (FPR_P (src_regno
))
4519 && ((dest_regno
- FPR_FIRST
) & 1) == 0
4520 && ((src_regno
- FPR_FIRST
) & 1) == 0)
4521 return "fmovd %1, %0";
4527 else if (GET_CODE (src
) == MEM
)
4530 if (dbl_memory_one_insn_operand (src
, mode
))
4531 return "lddf%I1%U1 %M1, %0";
4536 else if (ZERO_P (src
))
4541 else if (GET_CODE (dest
) == MEM
)
4543 if (GET_CODE (src
) == REG
)
4545 int src_regno
= REGNO (src
);
4547 if (GPR_P (src_regno
))
4549 if (((src_regno
- GPR_FIRST
) & 1) == 0
4550 && dbl_memory_one_insn_operand (dest
, mode
))
4551 return "std%I0%U0 %1, %M0";
4556 if (FPR_P (src_regno
))
4558 if (((src_regno
- FPR_FIRST
) & 1) == 0
4559 && dbl_memory_one_insn_operand (dest
, mode
))
4560 return "stdf%I0%U0 %1, %M0";
4566 else if (ZERO_P (src
))
4568 if (dbl_memory_one_insn_operand (dest
, mode
))
4569 return "std%I0%U0 %., %M0";
4575 fatal_insn ("bad output_move_double operand", insn
);
4580 /* Return a string to output a single word conditional move.
4581 Operand0 -- EQ/NE of ccr register and 0
4582 Operand1 -- CCR register
4583 Operand2 -- destination
4584 Operand3 -- source */
4587 output_condmove_single (rtx operands
[], rtx insn
)
4589 rtx dest
= operands
[2];
4590 rtx src
= operands
[3];
4592 if (GET_CODE (dest
) == REG
)
4594 int dest_regno
= REGNO (dest
);
4595 machine_mode mode
= GET_MODE (dest
);
4597 if (GPR_P (dest_regno
))
4599 if (GET_CODE (src
) == REG
)
4601 /* gpr <- some sort of register */
4602 int src_regno
= REGNO (src
);
4604 if (GPR_P (src_regno
))
4605 return "cmov %z3, %2, %1, %e0";
4607 else if (FPR_P (src_regno
))
4608 return "cmovfg %3, %2, %1, %e0";
4611 else if (GET_CODE (src
) == MEM
)
4620 return "cldsb%I3%U3 %M3, %2, %1, %e0";
4623 return "cldsh%I3%U3 %M3, %2, %1, %e0";
4627 return "cld%I3%U3 %M3, %2, %1, %e0";
4631 else if (ZERO_P (src
))
4632 return "cmov %., %2, %1, %e0";
4635 else if (FPR_P (dest_regno
))
4637 if (GET_CODE (src
) == REG
)
4639 /* fpr <- some sort of register */
4640 int src_regno
= REGNO (src
);
4642 if (GPR_P (src_regno
))
4643 return "cmovgf %3, %2, %1, %e0";
4645 else if (FPR_P (src_regno
))
4647 if (TARGET_HARD_FLOAT
)
4648 return "cfmovs %3,%2,%1,%e0";
4650 return "cmor %3, %3, %2, %1, %e0";
4654 else if (GET_CODE (src
) == MEM
)
4657 if (mode
== SImode
|| mode
== SFmode
)
4658 return "cldf%I3%U3 %M3, %2, %1, %e0";
4661 else if (ZERO_P (src
))
4662 return "cmovgf %., %2, %1, %e0";
4666 else if (GET_CODE (dest
) == MEM
)
4668 if (GET_CODE (src
) == REG
)
4670 int src_regno
= REGNO (src
);
4671 machine_mode mode
= GET_MODE (dest
);
4673 if (GPR_P (src_regno
))
4681 return "cstb%I2%U2 %3, %M2, %1, %e0";
4684 return "csth%I2%U2 %3, %M2, %1, %e0";
4688 return "cst%I2%U2 %3, %M2, %1, %e0";
4692 else if (FPR_P (src_regno
) && (mode
== SImode
|| mode
== SFmode
))
4693 return "cstf%I2%U2 %3, %M2, %1, %e0";
4696 else if (ZERO_P (src
))
4698 machine_mode mode
= GET_MODE (dest
);
4705 return "cstb%I2%U2 %., %M2, %1, %e0";
4708 return "csth%I2%U2 %., %M2, %1, %e0";
4712 return "cst%I2%U2 %., %M2, %1, %e0";
4717 fatal_insn ("bad output_condmove_single operand", insn
);
4722 /* Emit the appropriate code to do a comparison, returning the register the
4723 comparison was done it. */
4726 frv_emit_comparison (enum rtx_code test
, rtx op0
, rtx op1
)
4728 machine_mode cc_mode
;
4731 /* Floating point doesn't have comparison against a constant. */
4732 if (GET_MODE (op0
) == CC_FPmode
&& GET_CODE (op1
) != REG
)
4733 op1
= force_reg (GET_MODE (op0
), op1
);
4735 /* Possibly disable using anything but a fixed register in order to work
4736 around cse moving comparisons past function calls. */
4737 cc_mode
= SELECT_CC_MODE (test
, op0
, op1
);
4738 cc_reg
= ((TARGET_ALLOC_CC
)
4739 ? gen_reg_rtx (cc_mode
)
4740 : gen_rtx_REG (cc_mode
,
4741 (cc_mode
== CC_FPmode
) ? FCC_FIRST
: ICC_FIRST
));
4743 emit_insn (gen_rtx_SET (cc_reg
, gen_rtx_COMPARE (cc_mode
, op0
, op1
)));
4749 /* Emit code for a conditional branch.
4750 XXX: I originally wanted to add a clobber of a CCR register to use in
4751 conditional execution, but that confuses the rest of the compiler. */
4754 frv_emit_cond_branch (rtx operands
[])
4759 enum rtx_code test
= GET_CODE (operands
[0]);
4760 rtx cc_reg
= frv_emit_comparison (test
, operands
[1], operands
[2]);
4761 machine_mode cc_mode
= GET_MODE (cc_reg
);
4763 /* Branches generate:
4765 (if_then_else (<test>, <cc_reg>, (const_int 0))
4766 (label_ref <branch_label>)
4768 label_ref
= gen_rtx_LABEL_REF (VOIDmode
, operands
[3]);
4769 test_rtx
= gen_rtx_fmt_ee (test
, cc_mode
, cc_reg
, const0_rtx
);
4770 if_else
= gen_rtx_IF_THEN_ELSE (cc_mode
, test_rtx
, label_ref
, pc_rtx
);
4771 emit_jump_insn (gen_rtx_SET (pc_rtx
, if_else
));
4776 /* Emit code to set a gpr to 1/0 based on a comparison. */
4779 frv_emit_scc (rtx operands
[])
4785 enum rtx_code test
= GET_CODE (operands
[1]);
4786 rtx cc_reg
= frv_emit_comparison (test
, operands
[2], operands
[3]);
4788 /* SCC instructions generate:
4789 (parallel [(set <target> (<test>, <cc_reg>, (const_int 0))
4790 (clobber (<ccr_reg>))]) */
4791 test_rtx
= gen_rtx_fmt_ee (test
, SImode
, cc_reg
, const0_rtx
);
4792 set
= gen_rtx_SET (operands
[0], test_rtx
);
4794 cr_reg
= ((TARGET_ALLOC_CC
)
4795 ? gen_reg_rtx (CC_CCRmode
)
4796 : gen_rtx_REG (CC_CCRmode
,
4797 ((GET_MODE (cc_reg
) == CC_FPmode
)
4801 clobber
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
4802 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber
)));
4807 /* Split a SCC instruction into component parts, returning a SEQUENCE to hold
4808 the separate insns. */
4811 frv_split_scc (rtx dest
, rtx test
, rtx cc_reg
, rtx cr_reg
, HOST_WIDE_INT value
)
4817 /* Set the appropriate CCR bit. */
4818 emit_insn (gen_rtx_SET (cr_reg
,
4819 gen_rtx_fmt_ee (GET_CODE (test
),
4824 /* Move the value into the destination. */
4825 emit_move_insn (dest
, GEN_INT (value
));
4827 /* Move 0 into the destination if the test failed */
4828 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4829 gen_rtx_EQ (GET_MODE (cr_reg
),
4832 gen_rtx_SET (dest
, const0_rtx
)));
4834 /* Finish up, return sequence. */
4841 /* Emit the code for a conditional move, return TRUE if we could do the
4845 frv_emit_cond_move (rtx dest
, rtx test_rtx
, rtx src1
, rtx src2
)
4852 enum rtx_code test
= GET_CODE (test_rtx
);
4853 rtx cc_reg
= frv_emit_comparison (test
,
4854 XEXP (test_rtx
, 0), XEXP (test_rtx
, 1));
4855 machine_mode cc_mode
= GET_MODE (cc_reg
);
4857 /* Conditional move instructions generate:
4858 (parallel [(set <target>
4859 (if_then_else (<test> <cc_reg> (const_int 0))
4862 (clobber (<ccr_reg>))]) */
4864 /* Handle various cases of conditional move involving two constants. */
4865 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
4867 HOST_WIDE_INT value1
= INTVAL (src1
);
4868 HOST_WIDE_INT value2
= INTVAL (src2
);
4870 /* Having 0 as one of the constants can be done by loading the other
4871 constant, and optionally moving in gr0. */
4872 if (value1
== 0 || value2
== 0)
4875 /* If the first value is within an addi range and also the difference
4876 between the two fits in an addi's range, load up the difference, then
4877 conditionally move in 0, and then unconditionally add the first
4879 else if (IN_RANGE (value1
, -2048, 2047)
4880 && IN_RANGE (value2
- value1
, -2048, 2047))
4883 /* If neither condition holds, just force the constant into a
4887 src1
= force_reg (GET_MODE (dest
), src1
);
4888 src2
= force_reg (GET_MODE (dest
), src2
);
4892 /* If one value is a register, insure the other value is either 0 or a
4896 if (GET_CODE (src1
) == CONST_INT
&& INTVAL (src1
) != 0)
4897 src1
= force_reg (GET_MODE (dest
), src1
);
4899 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
4900 src2
= force_reg (GET_MODE (dest
), src2
);
4903 test2
= gen_rtx_fmt_ee (test
, cc_mode
, cc_reg
, const0_rtx
);
4904 if_rtx
= gen_rtx_IF_THEN_ELSE (GET_MODE (dest
), test2
, src1
, src2
);
4906 set
= gen_rtx_SET (dest
, if_rtx
);
4908 cr_reg
= ((TARGET_ALLOC_CC
)
4909 ? gen_reg_rtx (CC_CCRmode
)
4910 : gen_rtx_REG (CC_CCRmode
,
4911 (cc_mode
== CC_FPmode
) ? FCR_FIRST
: ICR_FIRST
));
4913 clobber_cc
= gen_rtx_CLOBBER (VOIDmode
, cr_reg
);
4914 emit_insn (gen_rtx_PARALLEL (VOIDmode
, gen_rtvec (2, set
, clobber_cc
)));
4919 /* Split a conditional move into constituent parts, returning a SEQUENCE
4920 containing all of the insns. */
4923 frv_split_cond_move (rtx operands
[])
4925 rtx dest
= operands
[0];
4926 rtx test
= operands
[1];
4927 rtx cc_reg
= operands
[2];
4928 rtx src1
= operands
[3];
4929 rtx src2
= operands
[4];
4930 rtx cr_reg
= operands
[5];
4932 machine_mode cr_mode
= GET_MODE (cr_reg
);
4936 /* Set the appropriate CCR bit. */
4937 emit_insn (gen_rtx_SET (cr_reg
,
4938 gen_rtx_fmt_ee (GET_CODE (test
),
4943 /* Handle various cases of conditional move involving two constants. */
4944 if (GET_CODE (src1
) == CONST_INT
&& GET_CODE (src2
) == CONST_INT
)
4946 HOST_WIDE_INT value1
= INTVAL (src1
);
4947 HOST_WIDE_INT value2
= INTVAL (src2
);
4949 /* Having 0 as one of the constants can be done by loading the other
4950 constant, and optionally moving in gr0. */
4953 emit_move_insn (dest
, src2
);
4954 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4955 gen_rtx_NE (cr_mode
, cr_reg
,
4957 gen_rtx_SET (dest
, src1
)));
4960 else if (value2
== 0)
4962 emit_move_insn (dest
, src1
);
4963 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4964 gen_rtx_EQ (cr_mode
, cr_reg
,
4966 gen_rtx_SET (dest
, src2
)));
4969 /* If the first value is within an addi range and also the difference
4970 between the two fits in an addi's range, load up the difference, then
4971 conditionally move in 0, and then unconditionally add the first
4973 else if (IN_RANGE (value1
, -2048, 2047)
4974 && IN_RANGE (value2
- value1
, -2048, 2047))
4976 rtx dest_si
= ((GET_MODE (dest
) == SImode
)
4978 : gen_rtx_SUBREG (SImode
, dest
, 0));
4980 emit_move_insn (dest_si
, GEN_INT (value2
- value1
));
4981 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4982 gen_rtx_NE (cr_mode
, cr_reg
,
4984 gen_rtx_SET (dest_si
, const0_rtx
)));
4985 emit_insn (gen_addsi3 (dest_si
, dest_si
, src1
));
4993 /* Emit the conditional move for the test being true if needed. */
4994 if (! rtx_equal_p (dest
, src1
))
4995 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
4996 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
4997 gen_rtx_SET (dest
, src1
)));
4999 /* Emit the conditional move for the test being false if needed. */
5000 if (! rtx_equal_p (dest
, src2
))
5001 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5002 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
5003 gen_rtx_SET (dest
, src2
)));
5006 /* Finish up, return sequence. */
5013 /* Split (set DEST SOURCE), where DEST is a double register and SOURCE is a
5014 memory location that is not known to be dword-aligned. */
5016 frv_split_double_load (rtx dest
, rtx source
)
5018 int regno
= REGNO (dest
);
5019 rtx dest1
= gen_highpart (SImode
, dest
);
5020 rtx dest2
= gen_lowpart (SImode
, dest
);
5021 rtx address
= XEXP (source
, 0);
5023 /* If the address is pre-modified, load the lower-numbered register
5024 first, then load the other register using an integer offset from
5025 the modified base register. This order should always be safe,
5026 since the pre-modification cannot affect the same registers as the
5029 The situation for other loads is more complicated. Loading one
5030 of the registers could affect the value of ADDRESS, so we must
5031 be careful which order we do them in. */
5032 if (GET_CODE (address
) == PRE_MODIFY
5033 || ! refers_to_regno_p (regno
, address
))
5035 /* It is safe to load the lower-numbered register first. */
5036 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
5037 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
5041 /* ADDRESS is not pre-modified and the address depends on the
5042 lower-numbered register. Load the higher-numbered register
5044 emit_move_insn (dest2
, frv_index_memory (source
, SImode
, 1));
5045 emit_move_insn (dest1
, change_address (source
, SImode
, NULL
));
5049 /* Split (set DEST SOURCE), where DEST refers to a dword memory location
5050 and SOURCE is either a double register or the constant zero. */
5052 frv_split_double_store (rtx dest
, rtx source
)
5054 rtx dest1
= change_address (dest
, SImode
, NULL
);
5055 rtx dest2
= frv_index_memory (dest
, SImode
, 1);
5056 if (ZERO_P (source
))
5058 emit_move_insn (dest1
, CONST0_RTX (SImode
));
5059 emit_move_insn (dest2
, CONST0_RTX (SImode
));
5063 emit_move_insn (dest1
, gen_highpart (SImode
, source
));
5064 emit_move_insn (dest2
, gen_lowpart (SImode
, source
));
5069 /* Split a min/max operation returning a SEQUENCE containing all of the
5073 frv_split_minmax (rtx operands
[])
5075 rtx dest
= operands
[0];
5076 rtx minmax
= operands
[1];
5077 rtx src1
= operands
[2];
5078 rtx src2
= operands
[3];
5079 rtx cc_reg
= operands
[4];
5080 rtx cr_reg
= operands
[5];
5082 enum rtx_code test_code
;
5083 machine_mode cr_mode
= GET_MODE (cr_reg
);
5087 /* Figure out which test to use. */
5088 switch (GET_CODE (minmax
))
5093 case SMIN
: test_code
= LT
; break;
5094 case SMAX
: test_code
= GT
; break;
5095 case UMIN
: test_code
= LTU
; break;
5096 case UMAX
: test_code
= GTU
; break;
5099 /* Issue the compare instruction. */
5100 emit_insn (gen_rtx_SET (cc_reg
, gen_rtx_COMPARE (GET_MODE (cc_reg
),
5103 /* Set the appropriate CCR bit. */
5104 emit_insn (gen_rtx_SET (cr_reg
, gen_rtx_fmt_ee (test_code
,
5109 /* If are taking the min/max of a nonzero constant, load that first, and
5110 then do a conditional move of the other value. */
5111 if (GET_CODE (src2
) == CONST_INT
&& INTVAL (src2
) != 0)
5113 gcc_assert (!rtx_equal_p (dest
, src1
));
5115 emit_move_insn (dest
, src2
);
5116 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5117 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
5118 gen_rtx_SET (dest
, src1
)));
5121 /* Otherwise, do each half of the move. */
5124 /* Emit the conditional move for the test being true if needed. */
5125 if (! rtx_equal_p (dest
, src1
))
5126 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5127 gen_rtx_NE (cr_mode
, cr_reg
, const0_rtx
),
5128 gen_rtx_SET (dest
, src1
)));
5130 /* Emit the conditional move for the test being false if needed. */
5131 if (! rtx_equal_p (dest
, src2
))
5132 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5133 gen_rtx_EQ (cr_mode
, cr_reg
, const0_rtx
),
5134 gen_rtx_SET (dest
, src2
)));
5137 /* Finish up, return sequence. */
5144 /* Split an integer abs operation returning a SEQUENCE containing all of the
5148 frv_split_abs (rtx operands
[])
5150 rtx dest
= operands
[0];
5151 rtx src
= operands
[1];
5152 rtx cc_reg
= operands
[2];
5153 rtx cr_reg
= operands
[3];
5158 /* Issue the compare < 0 instruction. */
5159 emit_insn (gen_rtx_SET (cc_reg
, gen_rtx_COMPARE (CCmode
, src
, const0_rtx
)));
5161 /* Set the appropriate CCR bit. */
5162 emit_insn (gen_rtx_SET (cr_reg
, gen_rtx_fmt_ee (LT
, CC_CCRmode
,
5163 cc_reg
, const0_rtx
)));
5165 /* Emit the conditional negate if the value is negative. */
5166 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5167 gen_rtx_NE (CC_CCRmode
, cr_reg
, const0_rtx
),
5168 gen_negsi2 (dest
, src
)));
5170 /* Emit the conditional move for the test being false if needed. */
5171 if (! rtx_equal_p (dest
, src
))
5172 emit_insn (gen_rtx_COND_EXEC (VOIDmode
,
5173 gen_rtx_EQ (CC_CCRmode
, cr_reg
, const0_rtx
),
5174 gen_rtx_SET (dest
, src
)));
5176 /* Finish up, return sequence. */
5183 /* Initialize machine-specific if-conversion data.
5184 On the FR-V, we don't have any extra fields per se, but it is useful hook to
5185 initialize the static storage. */
5187 frv_ifcvt_machdep_init (void *ce_info ATTRIBUTE_UNUSED
)
5189 frv_ifcvt
.added_insns_list
= NULL_RTX
;
5190 frv_ifcvt
.cur_scratch_regs
= 0;
5191 frv_ifcvt
.num_nested_cond_exec
= 0;
5192 frv_ifcvt
.cr_reg
= NULL_RTX
;
5193 frv_ifcvt
.nested_cc_reg
= NULL_RTX
;
5194 frv_ifcvt
.extra_int_cr
= NULL_RTX
;
5195 frv_ifcvt
.extra_fp_cr
= NULL_RTX
;
5196 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
5200 /* Internal function to add a potential insn to the list of insns to be inserted
5201 if the conditional execution conversion is successful. */
5204 frv_ifcvt_add_insn (rtx pattern
, rtx insn
, int before_p
)
5206 rtx link
= alloc_EXPR_LIST (VOIDmode
, pattern
, insn
);
5208 link
->jump
= before_p
; /* Mark to add this before or after insn. */
5209 frv_ifcvt
.added_insns_list
= alloc_EXPR_LIST (VOIDmode
, link
,
5210 frv_ifcvt
.added_insns_list
);
5212 if (TARGET_DEBUG_COND_EXEC
)
5215 "\n:::::::::: frv_ifcvt_add_insn: add the following %s insn %d:\n",
5216 (before_p
) ? "before" : "after",
5217 (int)INSN_UID (insn
));
5219 debug_rtx (pattern
);
5224 /* A C expression to modify the code described by the conditional if
5225 information CE_INFO, possibly updating the tests in TRUE_EXPR, and
5226 FALSE_EXPR for converting if-then and if-then-else code to conditional
5227 instructions. Set either TRUE_EXPR or FALSE_EXPR to a null pointer if the
5228 tests cannot be converted. */
5231 frv_ifcvt_modify_tests (ce_if_block
*ce_info
, rtx
*p_true
, rtx
*p_false
)
5233 basic_block test_bb
= ce_info
->test_bb
; /* test basic block */
5234 basic_block then_bb
= ce_info
->then_bb
; /* THEN */
5235 basic_block else_bb
= ce_info
->else_bb
; /* ELSE or NULL */
5236 basic_block join_bb
= ce_info
->join_bb
; /* join block or NULL */
5237 rtx true_expr
= *p_true
;
5241 machine_mode mode
= GET_MODE (true_expr
);
5245 frv_tmp_reg_t
*tmp_reg
= &frv_ifcvt
.tmp_reg
;
5247 rtx sub_cond_exec_reg
;
5249 enum rtx_code code_true
;
5250 enum rtx_code code_false
;
5251 enum reg_class cc_class
;
5252 enum reg_class cr_class
;
5255 reg_set_iterator rsi
;
5257 /* Make sure we are only dealing with hard registers. Also honor the
5258 -mno-cond-exec switch, and -mno-nested-cond-exec switches if
5260 if (!reload_completed
|| !TARGET_COND_EXEC
5261 || (!TARGET_NESTED_CE
&& ce_info
->pass
> 1))
5264 /* Figure out which registers we can allocate for our own purposes. Only
5265 consider registers that are not preserved across function calls and are
5266 not fixed. However, allow the ICC/ICR temporary registers to be allocated
5267 if we did not need to use them in reloading other registers. */
5268 memset (&tmp_reg
->regs
, 0, sizeof (tmp_reg
->regs
));
5269 COPY_HARD_REG_SET (tmp_reg
->regs
, call_used_reg_set
);
5270 AND_COMPL_HARD_REG_SET (tmp_reg
->regs
, fixed_reg_set
);
5271 SET_HARD_REG_BIT (tmp_reg
->regs
, ICC_TEMP
);
5272 SET_HARD_REG_BIT (tmp_reg
->regs
, ICR_TEMP
);
5274 /* If this is a nested IF, we need to discover whether the CC registers that
5275 are set/used inside of the block are used anywhere else. If not, we can
5276 change them to be the CC register that is paired with the CR register that
5277 controls the outermost IF block. */
5278 if (ce_info
->pass
> 1)
5280 CLEAR_HARD_REG_SET (frv_ifcvt
.nested_cc_ok_rewrite
);
5281 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5282 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5284 if (REGNO_REG_SET_P (df_get_live_in (then_bb
), j
))
5288 && REGNO_REG_SET_P (df_get_live_in (else_bb
), j
))
5292 && REGNO_REG_SET_P (df_get_live_in (join_bb
), j
))
5295 SET_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
);
5299 for (j
= 0; j
< frv_ifcvt
.cur_scratch_regs
; j
++)
5300 frv_ifcvt
.scratch_regs
[j
] = NULL_RTX
;
5302 frv_ifcvt
.added_insns_list
= NULL_RTX
;
5303 frv_ifcvt
.cur_scratch_regs
= 0;
5305 bb
= (basic_block
*) alloca ((2 + ce_info
->num_multiple_test_blocks
)
5306 * sizeof (basic_block
));
5312 /* Remove anything live at the beginning of the join block from being
5313 available for allocation. */
5314 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (join_bb
), 0, regno
, rsi
)
5316 if (regno
< FIRST_PSEUDO_REGISTER
)
5317 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
5321 /* Add in all of the blocks in multiple &&/|| blocks to be scanned. */
5323 if (ce_info
->num_multiple_test_blocks
)
5325 basic_block multiple_test_bb
= ce_info
->last_test_bb
;
5327 while (multiple_test_bb
!= test_bb
)
5329 bb
[num_bb
++] = multiple_test_bb
;
5330 multiple_test_bb
= EDGE_PRED (multiple_test_bb
, 0)->src
;
5334 /* Add in the THEN and ELSE blocks to be scanned. */
5335 bb
[num_bb
++] = then_bb
;
5337 bb
[num_bb
++] = else_bb
;
5339 sub_cond_exec_reg
= NULL_RTX
;
5340 frv_ifcvt
.num_nested_cond_exec
= 0;
5342 /* Scan all of the blocks for registers that must not be allocated. */
5343 for (j
= 0; j
< num_bb
; j
++)
5345 rtx_insn
*last_insn
= BB_END (bb
[j
]);
5346 rtx_insn
*insn
= BB_HEAD (bb
[j
]);
5350 fprintf (dump_file
, "Scanning %s block %d, start %d, end %d\n",
5351 (bb
[j
] == else_bb
) ? "else" : ((bb
[j
] == then_bb
) ? "then" : "test"),
5353 (int) INSN_UID (BB_HEAD (bb
[j
])),
5354 (int) INSN_UID (BB_END (bb
[j
])));
5356 /* Anything live at the beginning of the block is obviously unavailable
5358 EXECUTE_IF_SET_IN_REG_SET (df_get_live_in (bb
[j
]), 0, regno
, rsi
)
5360 if (regno
< FIRST_PSEUDO_REGISTER
)
5361 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, regno
);
5364 /* Loop through the insns in the block. */
5367 /* Mark any new registers that are created as being unavailable for
5368 allocation. Also see if the CC register used in nested IFs can be
5374 int skip_nested_if
= FALSE
;
5375 HARD_REG_SET mentioned_regs
;
5377 CLEAR_HARD_REG_SET (mentioned_regs
);
5378 find_all_hard_regs (PATTERN (insn
), &mentioned_regs
);
5379 AND_COMPL_HARD_REG_SET (tmp_reg
->regs
, mentioned_regs
);
5381 pattern
= PATTERN (insn
);
5382 if (GET_CODE (pattern
) == COND_EXEC
)
5384 rtx reg
= XEXP (COND_EXEC_TEST (pattern
), 0);
5386 if (reg
!= sub_cond_exec_reg
)
5388 sub_cond_exec_reg
= reg
;
5389 frv_ifcvt
.num_nested_cond_exec
++;
5393 set
= single_set_pattern (pattern
);
5396 rtx dest
= SET_DEST (set
);
5397 rtx src
= SET_SRC (set
);
5399 if (GET_CODE (dest
) == REG
)
5401 int regno
= REGNO (dest
);
5402 enum rtx_code src_code
= GET_CODE (src
);
5404 if (CC_P (regno
) && src_code
== COMPARE
)
5405 skip_nested_if
= TRUE
;
5407 else if (CR_P (regno
)
5408 && (src_code
== IF_THEN_ELSE
5409 || COMPARISON_P (src
)))
5410 skip_nested_if
= TRUE
;
5414 if (! skip_nested_if
)
5415 AND_COMPL_HARD_REG_SET (frv_ifcvt
.nested_cc_ok_rewrite
,
5419 if (insn
== last_insn
)
5422 insn
= NEXT_INSN (insn
);
5426 /* If this is a nested if, rewrite the CC registers that are available to
5427 include the ones that can be rewritten, to increase the chance of being
5428 able to allocate a paired CC/CR register combination. */
5429 if (ce_info
->pass
> 1)
5431 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5432 if (TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, j
))
5433 SET_HARD_REG_BIT (tmp_reg
->regs
, j
);
5435 CLEAR_HARD_REG_BIT (tmp_reg
->regs
, j
);
5441 fprintf (dump_file
, "Available GPRs: ");
5443 for (j
= GPR_FIRST
; j
<= GPR_LAST
; j
++)
5444 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5446 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5447 if (++num_gprs
> GPR_TEMP_NUM
+2)
5451 fprintf (dump_file
, "%s\nAvailable CRs: ",
5452 (num_gprs
> GPR_TEMP_NUM
+2) ? " ..." : "");
5454 for (j
= CR_FIRST
; j
<= CR_LAST
; j
++)
5455 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5456 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5458 fputs ("\n", dump_file
);
5460 if (ce_info
->pass
> 1)
5462 fprintf (dump_file
, "Modifiable CCs: ");
5463 for (j
= CC_FIRST
; j
<= CC_LAST
; j
++)
5464 if (TEST_HARD_REG_BIT (tmp_reg
->regs
, j
))
5465 fprintf (dump_file
, " %d [%s]", j
, reg_names
[j
]);
5467 fprintf (dump_file
, "\n%d nested COND_EXEC statements\n",
5468 frv_ifcvt
.num_nested_cond_exec
);
5472 /* Allocate the appropriate temporary condition code register. Try to
5473 allocate the ICR/FCR register that corresponds to the ICC/FCC register so
5474 that conditional cmp's can be done. */
5475 if (mode
== CCmode
|| mode
== CC_UNSmode
|| mode
== CC_NZmode
)
5477 cr_class
= ICR_REGS
;
5478 cc_class
= ICC_REGS
;
5479 cc_first
= ICC_FIRST
;
5482 else if (mode
== CC_FPmode
)
5484 cr_class
= FCR_REGS
;
5485 cc_class
= FCC_REGS
;
5486 cc_first
= FCC_FIRST
;
5491 cc_first
= cc_last
= 0;
5492 cr_class
= cc_class
= NO_REGS
;
5495 cc
= XEXP (true_expr
, 0);
5496 nested_cc
= cr
= NULL_RTX
;
5497 if (cc_class
!= NO_REGS
)
5499 /* For nested IFs and &&/||, see if we can find a CC and CR register pair
5500 so we can execute a csubcc/caddcc/cfcmps instruction. */
5503 for (cc_regno
= cc_first
; cc_regno
<= cc_last
; cc_regno
++)
5505 int cr_regno
= cc_regno
- CC_FIRST
+ CR_FIRST
;
5507 if (TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cc_regno
)
5508 && TEST_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, cr_regno
))
5510 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cr_class
] = cr_regno
;
5511 cr
= frv_alloc_temp_reg (tmp_reg
, cr_class
, CC_CCRmode
, TRUE
,
5514 frv_ifcvt
.tmp_reg
.next_reg
[ (int)cc_class
] = cc_regno
;
5515 nested_cc
= frv_alloc_temp_reg (tmp_reg
, cc_class
, CCmode
,
5525 fprintf (dump_file
, "Could not allocate a CR temporary register\n");
5532 "Will use %s for conditional execution, %s for nested comparisons\n",
5533 reg_names
[ REGNO (cr
)],
5534 (nested_cc
) ? reg_names
[ REGNO (nested_cc
) ] : "<none>");
5536 /* Set the CCR bit. Note for integer tests, we reverse the condition so that
5537 in an IF-THEN-ELSE sequence, we are testing the TRUE case against the CCR
5538 bit being true. We don't do this for floating point, because of NaNs. */
5539 code
= GET_CODE (true_expr
);
5540 if (GET_MODE (cc
) != CC_FPmode
)
5542 code
= reverse_condition (code
);
5552 check_insn
= gen_rtx_SET (cr
, gen_rtx_fmt_ee (code
, CC_CCRmode
,
5555 /* Record the check insn to be inserted later. */
5556 frv_ifcvt_add_insn (check_insn
, BB_END (test_bb
), TRUE
);
5558 /* Update the tests. */
5559 frv_ifcvt
.cr_reg
= cr
;
5560 frv_ifcvt
.nested_cc_reg
= nested_cc
;
5561 *p_true
= gen_rtx_fmt_ee (code_true
, CC_CCRmode
, cr
, const0_rtx
);
5562 *p_false
= gen_rtx_fmt_ee (code_false
, CC_CCRmode
, cr
, const0_rtx
);
5565 /* Fail, don't do this conditional execution. */
5568 *p_false
= NULL_RTX
;
5570 fprintf (dump_file
, "Disabling this conditional execution.\n");
5576 /* A C expression to modify the code described by the conditional if
5577 information CE_INFO, for the basic block BB, possibly updating the tests in
5578 TRUE_EXPR, and FALSE_EXPR for converting the && and || parts of if-then or
5579 if-then-else code to conditional instructions. Set either TRUE_EXPR or
5580 FALSE_EXPR to a null pointer if the tests cannot be converted. */
5582 /* p_true and p_false are given expressions of the form:
5584 (and (eq:CC_CCR (reg:CC_CCR)
5590 frv_ifcvt_modify_multiple_tests (ce_if_block
*ce_info
,
5595 rtx old_true
= XEXP (*p_true
, 0);
5596 rtx old_false
= XEXP (*p_false
, 0);
5597 rtx true_expr
= XEXP (*p_true
, 1);
5598 rtx false_expr
= XEXP (*p_false
, 1);
5601 rtx cr
= XEXP (old_true
, 0);
5603 rtx new_cr
= NULL_RTX
;
5604 rtx
*p_new_cr
= (rtx
*)0;
5608 enum reg_class cr_class
;
5609 machine_mode mode
= GET_MODE (true_expr
);
5610 rtx (*logical_func
)(rtx
, rtx
, rtx
);
5612 if (TARGET_DEBUG_COND_EXEC
)
5615 "\n:::::::::: frv_ifcvt_modify_multiple_tests, before modification for %s\ntrue insn:\n",
5616 ce_info
->and_and_p
? "&&" : "||");
5618 debug_rtx (*p_true
);
5620 fputs ("\nfalse insn:\n", stderr
);
5621 debug_rtx (*p_false
);
5624 if (!TARGET_MULTI_CE
)
5627 if (GET_CODE (cr
) != REG
)
5630 if (mode
== CCmode
|| mode
== CC_UNSmode
|| mode
== CC_NZmode
)
5632 cr_class
= ICR_REGS
;
5633 p_new_cr
= &frv_ifcvt
.extra_int_cr
;
5635 else if (mode
== CC_FPmode
)
5637 cr_class
= FCR_REGS
;
5638 p_new_cr
= &frv_ifcvt
.extra_fp_cr
;
5643 /* Allocate a temp CR, reusing a previously allocated temp CR if we have 3 or
5644 more &&/|| tests. */
5648 new_cr
= *p_new_cr
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, cr_class
,
5649 CC_CCRmode
, TRUE
, TRUE
);
5654 if (ce_info
->and_and_p
)
5656 old_test
= old_false
;
5657 test_expr
= true_expr
;
5658 logical_func
= (GET_CODE (old_true
) == EQ
) ? gen_andcr
: gen_andncr
;
5659 *p_true
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
5660 *p_false
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
5664 old_test
= old_false
;
5665 test_expr
= false_expr
;
5666 logical_func
= (GET_CODE (old_false
) == EQ
) ? gen_orcr
: gen_orncr
;
5667 *p_true
= gen_rtx_EQ (CC_CCRmode
, cr
, const0_rtx
);
5668 *p_false
= gen_rtx_NE (CC_CCRmode
, cr
, const0_rtx
);
5671 /* First add the andcr/andncr/orcr/orncr, which will be added after the
5672 conditional check instruction, due to frv_ifcvt_add_insn being a LIFO
5674 frv_ifcvt_add_insn ((*logical_func
) (cr
, cr
, new_cr
), BB_END (bb
), TRUE
);
5676 /* Now add the conditional check insn. */
5677 cc
= XEXP (test_expr
, 0);
5678 compare
= gen_rtx_fmt_ee (GET_CODE (test_expr
), CC_CCRmode
, cc
, const0_rtx
);
5679 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, old_test
, compare
, const0_rtx
);
5681 check_insn
= gen_rtx_SET (new_cr
, if_else
);
5683 /* Add the new check insn to the list of check insns that need to be
5685 frv_ifcvt_add_insn (check_insn
, BB_END (bb
), TRUE
);
5687 if (TARGET_DEBUG_COND_EXEC
)
5689 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, after modification\ntrue insn:\n",
5692 debug_rtx (*p_true
);
5694 fputs ("\nfalse insn:\n", stderr
);
5695 debug_rtx (*p_false
);
5701 *p_true
= *p_false
= NULL_RTX
;
5703 /* If we allocated a CR register, release it. */
5706 CLEAR_HARD_REG_BIT (frv_ifcvt
.tmp_reg
.regs
, REGNO (new_cr
));
5707 *p_new_cr
= NULL_RTX
;
5710 if (TARGET_DEBUG_COND_EXEC
)
5711 fputs ("\n:::::::::: frv_ifcvt_modify_multiple_tests, failed.\n", stderr
);
5717 /* Return a register which will be loaded with a value if an IF block is
5718 converted to conditional execution. This is used to rewrite instructions
5719 that use constants to ones that just use registers. */
5722 frv_ifcvt_load_value (rtx value
, rtx insn ATTRIBUTE_UNUSED
)
5724 int num_alloc
= frv_ifcvt
.cur_scratch_regs
;
5728 /* We know gr0 == 0, so replace any errant uses. */
5729 if (value
== const0_rtx
)
5730 return gen_rtx_REG (SImode
, GPR_FIRST
);
5732 /* First search all registers currently loaded to see if we have an
5733 applicable constant. */
5734 if (CONSTANT_P (value
)
5735 || (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
))
5737 for (i
= 0; i
< num_alloc
; i
++)
5739 if (rtx_equal_p (SET_SRC (frv_ifcvt
.scratch_regs
[i
]), value
))
5740 return SET_DEST (frv_ifcvt
.scratch_regs
[i
]);
5744 /* Have we exhausted the number of registers available? */
5745 if (num_alloc
>= GPR_TEMP_NUM
)
5748 fprintf (dump_file
, "Too many temporary registers allocated\n");
5753 /* Allocate the new register. */
5754 reg
= frv_alloc_temp_reg (&frv_ifcvt
.tmp_reg
, GPR_REGS
, SImode
, TRUE
, TRUE
);
5758 fputs ("Could not find a scratch register\n", dump_file
);
5763 frv_ifcvt
.cur_scratch_regs
++;
5764 frv_ifcvt
.scratch_regs
[num_alloc
] = gen_rtx_SET (reg
, value
);
5768 if (GET_CODE (value
) == CONST_INT
)
5769 fprintf (dump_file
, "Register %s will hold %ld\n",
5770 reg_names
[ REGNO (reg
)], (long)INTVAL (value
));
5772 else if (GET_CODE (value
) == REG
&& REGNO (value
) == LR_REGNO
)
5773 fprintf (dump_file
, "Register %s will hold LR\n",
5774 reg_names
[ REGNO (reg
)]);
5777 fprintf (dump_file
, "Register %s will hold a saved value\n",
5778 reg_names
[ REGNO (reg
)]);
5785 /* Update a MEM used in conditional code that might contain an offset to put
5786 the offset into a scratch register, so that the conditional load/store
5787 operations can be used. This function returns the original pointer if the
5788 MEM is valid to use in conditional code, NULL if we can't load up the offset
5789 into a temporary register, or the new MEM if we were successful. */
5792 frv_ifcvt_rewrite_mem (rtx mem
, machine_mode mode
, rtx insn
)
5794 rtx addr
= XEXP (mem
, 0);
5796 if (!frv_legitimate_address_p_1 (mode
, addr
, reload_completed
, TRUE
, FALSE
))
5798 if (GET_CODE (addr
) == PLUS
)
5800 rtx addr_op0
= XEXP (addr
, 0);
5801 rtx addr_op1
= XEXP (addr
, 1);
5803 if (GET_CODE (addr_op0
) == REG
&& CONSTANT_P (addr_op1
))
5805 rtx reg
= frv_ifcvt_load_value (addr_op1
, insn
);
5809 addr
= gen_rtx_PLUS (Pmode
, addr_op0
, reg
);
5816 else if (CONSTANT_P (addr
))
5817 addr
= frv_ifcvt_load_value (addr
, insn
);
5822 if (addr
== NULL_RTX
)
5825 else if (XEXP (mem
, 0) != addr
)
5826 return change_address (mem
, mode
, addr
);
5833 /* Given a PATTERN, return a SET expression if this PATTERN has only a single
5834 SET, possibly conditionally executed. It may also have CLOBBERs, USEs. */
5837 single_set_pattern (rtx pattern
)
5842 if (GET_CODE (pattern
) == COND_EXEC
)
5843 pattern
= COND_EXEC_CODE (pattern
);
5845 if (GET_CODE (pattern
) == SET
)
5848 else if (GET_CODE (pattern
) == PARALLEL
)
5850 for (i
= 0, set
= 0; i
< XVECLEN (pattern
, 0); i
++)
5852 rtx sub
= XVECEXP (pattern
, 0, i
);
5854 switch (GET_CODE (sub
))
5878 /* A C expression to modify the code described by the conditional if
5879 information CE_INFO with the new PATTERN in INSN. If PATTERN is a null
5880 pointer after the IFCVT_MODIFY_INSN macro executes, it is assumed that that
5881 insn cannot be converted to be executed conditionally. */
5884 frv_ifcvt_modify_insn (ce_if_block
*ce_info
,
5888 rtx orig_ce_pattern
= pattern
;
5894 gcc_assert (GET_CODE (pattern
) == COND_EXEC
);
5896 test
= COND_EXEC_TEST (pattern
);
5897 if (GET_CODE (test
) == AND
)
5899 rtx cr
= frv_ifcvt
.cr_reg
;
5902 op0
= XEXP (test
, 0);
5903 if (! rtx_equal_p (cr
, XEXP (op0
, 0)))
5906 op1
= XEXP (test
, 1);
5907 test_reg
= XEXP (op1
, 0);
5908 if (GET_CODE (test_reg
) != REG
)
5911 /* Is this the first nested if block in this sequence? If so, generate
5912 an andcr or andncr. */
5913 if (! frv_ifcvt
.last_nested_if_cr
)
5917 frv_ifcvt
.last_nested_if_cr
= test_reg
;
5918 if (GET_CODE (op0
) == NE
)
5919 and_op
= gen_andcr (test_reg
, cr
, test_reg
);
5921 and_op
= gen_andncr (test_reg
, cr
, test_reg
);
5923 frv_ifcvt_add_insn (and_op
, insn
, TRUE
);
5926 /* If this isn't the first statement in the nested if sequence, see if we
5927 are dealing with the same register. */
5928 else if (! rtx_equal_p (test_reg
, frv_ifcvt
.last_nested_if_cr
))
5931 COND_EXEC_TEST (pattern
) = test
= op1
;
5934 /* If this isn't a nested if, reset state variables. */
5937 frv_ifcvt
.last_nested_if_cr
= NULL_RTX
;
5940 set
= single_set_pattern (pattern
);
5943 rtx dest
= SET_DEST (set
);
5944 rtx src
= SET_SRC (set
);
5945 machine_mode mode
= GET_MODE (dest
);
5947 /* Check for normal binary operators. */
5948 if (mode
== SImode
&& ARITHMETIC_P (src
))
5950 op0
= XEXP (src
, 0);
5951 op1
= XEXP (src
, 1);
5953 if (integer_register_operand (op0
, SImode
) && CONSTANT_P (op1
))
5955 op1
= frv_ifcvt_load_value (op1
, insn
);
5957 COND_EXEC_CODE (pattern
)
5958 = gen_rtx_SET (dest
, gen_rtx_fmt_ee (GET_CODE (src
),
5966 /* For multiply by a constant, we need to handle the sign extending
5967 correctly. Add a USE of the value after the multiply to prevent flow
5968 from cratering because only one register out of the two were used. */
5969 else if (mode
== DImode
&& GET_CODE (src
) == MULT
)
5971 op0
= XEXP (src
, 0);
5972 op1
= XEXP (src
, 1);
5973 if (GET_CODE (op0
) == SIGN_EXTEND
&& GET_CODE (op1
) == CONST_INT
)
5975 op1
= frv_ifcvt_load_value (op1
, insn
);
5978 op1
= gen_rtx_SIGN_EXTEND (DImode
, op1
);
5979 COND_EXEC_CODE (pattern
)
5980 = gen_rtx_SET (dest
, gen_rtx_MULT (DImode
, op0
, op1
));
5986 frv_ifcvt_add_insn (gen_use (dest
), insn
, FALSE
);
5989 /* If we are just loading a constant created for a nested conditional
5990 execution statement, just load the constant without any conditional
5991 execution, since we know that the constant will not interfere with any
5993 else if (frv_ifcvt
.scratch_insns_bitmap
5994 && bitmap_bit_p (frv_ifcvt
.scratch_insns_bitmap
,
5996 && REG_P (SET_DEST (set
))
5997 /* We must not unconditionally set a scratch reg chosen
5998 for a nested if-converted block if its incoming
5999 value from the TEST block (or the result of the THEN
6000 branch) could/should propagate to the JOIN block.
6001 It suffices to test whether the register is live at
6002 the JOIN point: if it's live there, we can infer
6003 that we set it in the former JOIN block of the
6004 nested if-converted block (otherwise it wouldn't
6005 have been available as a scratch register), and it
6006 is either propagated through or set in the other
6007 conditional block. It's probably not worth trying
6008 to catch the latter case, and it could actually
6009 limit scheduling of the combined block quite
6012 && ! (REGNO_REG_SET_P (df_get_live_in (ce_info
->join_bb
),
6013 REGNO (SET_DEST (set
))))
6014 /* Similarly, we must not unconditionally set a reg
6015 used as scratch in the THEN branch if the same reg
6016 is live in the ELSE branch. */
6017 && (! ce_info
->else_bb
6018 || BLOCK_FOR_INSN (insn
) == ce_info
->else_bb
6019 || ! (REGNO_REG_SET_P (df_get_live_in (ce_info
->else_bb
),
6020 REGNO (SET_DEST (set
))))))
6023 else if (mode
== QImode
|| mode
== HImode
|| mode
== SImode
6026 int changed_p
= FALSE
;
6028 /* Check for just loading up a constant */
6029 if (CONSTANT_P (src
) && integer_register_operand (dest
, mode
))
6031 src
= frv_ifcvt_load_value (src
, insn
);
6038 /* See if we need to fix up stores */
6039 if (GET_CODE (dest
) == MEM
)
6041 rtx new_mem
= frv_ifcvt_rewrite_mem (dest
, mode
, insn
);
6046 else if (new_mem
!= dest
)
6053 /* See if we need to fix up loads */
6054 if (GET_CODE (src
) == MEM
)
6056 rtx new_mem
= frv_ifcvt_rewrite_mem (src
, mode
, insn
);
6061 else if (new_mem
!= src
)
6068 /* If either src or destination changed, redo SET. */
6070 COND_EXEC_CODE (pattern
) = gen_rtx_SET (dest
, src
);
6073 /* Rewrite a nested set cccr in terms of IF_THEN_ELSE. Also deal with
6074 rewriting the CC register to be the same as the paired CC/CR register
6076 else if (mode
== CC_CCRmode
&& COMPARISON_P (src
))
6078 int regno
= REGNO (XEXP (src
, 0));
6081 if (ce_info
->pass
> 1
6082 && regno
!= (int)REGNO (frv_ifcvt
.nested_cc_reg
)
6083 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
, regno
))
6085 src
= gen_rtx_fmt_ee (GET_CODE (src
),
6087 frv_ifcvt
.nested_cc_reg
,
6091 if_else
= gen_rtx_IF_THEN_ELSE (CC_CCRmode
, test
, src
, const0_rtx
);
6092 pattern
= gen_rtx_SET (dest
, if_else
);
6095 /* Remap a nested compare instruction to use the paired CC/CR reg. */
6096 else if (ce_info
->pass
> 1
6097 && GET_CODE (dest
) == REG
6098 && CC_P (REGNO (dest
))
6099 && REGNO (dest
) != REGNO (frv_ifcvt
.nested_cc_reg
)
6100 && TEST_HARD_REG_BIT (frv_ifcvt
.nested_cc_ok_rewrite
,
6102 && GET_CODE (src
) == COMPARE
)
6104 PUT_MODE (frv_ifcvt
.nested_cc_reg
, GET_MODE (dest
));
6105 COND_EXEC_CODE (pattern
)
6106 = gen_rtx_SET (frv_ifcvt
.nested_cc_reg
, copy_rtx (src
));
6110 if (TARGET_DEBUG_COND_EXEC
)
6112 rtx orig_pattern
= PATTERN (insn
);
6114 PATTERN (insn
) = pattern
;
6116 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn after modification:\n",
6120 PATTERN (insn
) = orig_pattern
;
6126 if (TARGET_DEBUG_COND_EXEC
)
6128 rtx orig_pattern
= PATTERN (insn
);
6130 PATTERN (insn
) = orig_ce_pattern
;
6132 "\n:::::::::: frv_ifcvt_modify_insn: pass = %d, insn could not be modified:\n",
6136 PATTERN (insn
) = orig_pattern
;
6143 /* A C expression to perform any final machine dependent modifications in
6144 converting code to conditional execution in the code described by the
6145 conditional if information CE_INFO. */
6148 frv_ifcvt_modify_final (ce_if_block
*ce_info ATTRIBUTE_UNUSED
)
6152 rtx p
= frv_ifcvt
.added_insns_list
;
6155 /* Loop inserting the check insns. The last check insn is the first test,
6156 and is the appropriate place to insert constants. */
6161 rtx check_and_insert_insns
= XEXP (p
, 0);
6164 check_insn
= XEXP (check_and_insert_insns
, 0);
6165 existing_insn
= XEXP (check_and_insert_insns
, 1);
6168 /* The jump bit is used to say that the new insn is to be inserted BEFORE
6169 the existing insn, otherwise it is to be inserted AFTER. */
6170 if (check_and_insert_insns
->jump
)
6172 emit_insn_before (check_insn
, existing_insn
);
6173 check_and_insert_insns
->jump
= 0;
6176 emit_insn_after (check_insn
, existing_insn
);
6178 free_EXPR_LIST_node (check_and_insert_insns
);
6179 free_EXPR_LIST_node (old_p
);
6181 while (p
!= NULL_RTX
);
6183 /* Load up any constants needed into temp gprs */
6184 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
6186 rtx insn
= emit_insn_before (frv_ifcvt
.scratch_regs
[i
], existing_insn
);
6187 if (! frv_ifcvt
.scratch_insns_bitmap
)
6188 frv_ifcvt
.scratch_insns_bitmap
= BITMAP_ALLOC (NULL
);
6189 bitmap_set_bit (frv_ifcvt
.scratch_insns_bitmap
, INSN_UID (insn
));
6190 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
6193 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6194 frv_ifcvt
.cur_scratch_regs
= 0;
6198 /* A C expression to cancel any machine dependent modifications in converting
6199 code to conditional execution in the code described by the conditional if
6200 information CE_INFO. */
6203 frv_ifcvt_modify_cancel (ce_if_block
*ce_info ATTRIBUTE_UNUSED
)
6206 rtx p
= frv_ifcvt
.added_insns_list
;
6208 /* Loop freeing up the EXPR_LIST's allocated. */
6209 while (p
!= NULL_RTX
)
6211 rtx check_and_jump
= XEXP (p
, 0);
6215 free_EXPR_LIST_node (check_and_jump
);
6216 free_EXPR_LIST_node (old_p
);
6219 /* Release any temporary gprs allocated. */
6220 for (i
= 0; i
< frv_ifcvt
.cur_scratch_regs
; i
++)
6221 frv_ifcvt
.scratch_regs
[i
] = NULL_RTX
;
6223 frv_ifcvt
.added_insns_list
= NULL_RTX
;
6224 frv_ifcvt
.cur_scratch_regs
= 0;
6228 /* A C expression for the size in bytes of the trampoline, as an integer.
6232 setlo #0, <static_chain>
6234 sethi #0, <static_chain>
6235 jmpl @(gr0,<jmp_reg>) */
6238 frv_trampoline_size (void)
6241 /* Allocate room for the function descriptor and the lddi
6244 return 5 /* instructions */ * 4 /* instruction size. */;
6248 /* A C statement to initialize the variable parts of a trampoline. ADDR is an
6249 RTX for the address of the trampoline; FNADDR is an RTX for the address of
6250 the nested function; STATIC_CHAIN is an RTX for the static chain value that
6251 should be passed to the function when it is called.
6256 setlo #0, <static_chain>
6258 sethi #0, <static_chain>
6259 jmpl @(gr0,<jmp_reg>) */
6262 frv_trampoline_init (rtx m_tramp
, tree fndecl
, rtx static_chain
)
6264 rtx addr
= XEXP (m_tramp
, 0);
6265 rtx fnaddr
= XEXP (DECL_RTL (fndecl
), 0);
6266 rtx sc_reg
= force_reg (Pmode
, static_chain
);
6268 emit_library_call (gen_rtx_SYMBOL_REF (SImode
, "__trampoline_setup"),
6269 LCT_NORMAL
, VOIDmode
, 4,
6271 GEN_INT (frv_trampoline_size ()), SImode
,
6277 /* Many machines have some registers that cannot be copied directly to or from
6278 memory or even from other types of registers. An example is the `MQ'
6279 register, which on most machines, can only be copied to or from general
6280 registers, but not memory. Some machines allow copying all registers to and
6281 from memory, but require a scratch register for stores to some memory
6282 locations (e.g., those with symbolic address on the RT, and those with
6283 certain symbolic address on the SPARC when compiling PIC). In some cases,
6284 both an intermediate and a scratch register are required.
6286 You should define these macros to indicate to the reload phase that it may
6287 need to allocate at least one register for a reload in addition to the
6288 register to contain the data. Specifically, if copying X to a register
6289 RCLASS in MODE requires an intermediate register, you should define
6290 `SECONDARY_INPUT_RELOAD_CLASS' to return the largest register class all of
6291 whose registers can be used as intermediate registers or scratch registers.
6293 If copying a register RCLASS in MODE to X requires an intermediate or scratch
6294 register, `SECONDARY_OUTPUT_RELOAD_CLASS' should be defined to return the
6295 largest register class required. If the requirements for input and output
6296 reloads are the same, the macro `SECONDARY_RELOAD_CLASS' should be used
6297 instead of defining both macros identically.
6299 The values returned by these macros are often `GENERAL_REGS'. Return
6300 `NO_REGS' if no spare register is needed; i.e., if X can be directly copied
6301 to or from a register of RCLASS in MODE without requiring a scratch register.
6302 Do not define this macro if it would always return `NO_REGS'.
6304 If a scratch register is required (either with or without an intermediate
6305 register), you should define patterns for `reload_inM' or `reload_outM', as
6306 required.. These patterns, which will normally be implemented with a
6307 `define_expand', should be similar to the `movM' patterns, except that
6308 operand 2 is the scratch register.
6310 Define constraints for the reload register and scratch register that contain
6311 a single register class. If the original reload register (whose class is
6312 RCLASS) can meet the constraint given in the pattern, the value returned by
6313 these macros is used for the class of the scratch register. Otherwise, two
6314 additional reload registers are required. Their classes are obtained from
6315 the constraints in the insn pattern.
6317 X might be a pseudo-register or a `subreg' of a pseudo-register, which could
6318 either be in a hard register or in memory. Use `true_regnum' to find out;
6319 it will return -1 if the pseudo is in memory and the hard register number if
6320 it is in a register.
6322 These macros should not be used in the case where a particular class of
6323 registers can only be copied to memory and not to another class of
6324 registers. In that case, secondary reload registers are not needed and
6325 would not be helpful. Instead, a stack location must be used to perform the
6326 copy and the `movM' pattern should use memory as an intermediate storage.
6327 This case often occurs between floating-point and general registers. */
6330 frv_secondary_reload_class (enum reg_class rclass
,
6331 machine_mode mode ATTRIBUTE_UNUSED
,
6342 /* Accumulators/Accumulator guard registers need to go through floating
6347 if (x
&& GET_CODE (x
) == REG
)
6349 int regno
= REGNO (x
);
6351 if (ACC_P (regno
) || ACCG_P (regno
))
6356 /* Nonzero constants should be loaded into an FPR through a GPR. */
6358 if (x
&& CONSTANT_P (x
) && !ZERO_P (x
))
6364 /* All of these types need gpr registers. */
6376 /* The accumulators need fpr registers. */
6386 /* This hook exists to catch the case where secondary_reload_class() is
6387 called from init_reg_autoinc() in regclass.c - before the reload optabs
6388 have been initialised. */
6391 frv_secondary_reload (bool in_p
, rtx x
, reg_class_t reload_class_i
,
6392 machine_mode reload_mode
,
6393 secondary_reload_info
* sri
)
6395 enum reg_class rclass
= NO_REGS
;
6396 enum reg_class reload_class
= (enum reg_class
) reload_class_i
;
6398 if (sri
->prev_sri
&& sri
->prev_sri
->t_icode
!= CODE_FOR_nothing
)
6400 sri
->icode
= sri
->prev_sri
->t_icode
;
6404 rclass
= frv_secondary_reload_class (reload_class
, reload_mode
, x
);
6406 if (rclass
!= NO_REGS
)
6408 enum insn_code icode
6409 = direct_optab_handler (in_p
? reload_in_optab
: reload_out_optab
,
6413 /* This happens when then the reload_[in|out]_optabs have
6414 not been initialised. */
6415 sri
->t_icode
= CODE_FOR_nothing
;
6420 /* Fall back to the default secondary reload handler. */
6421 return default_secondary_reload (in_p
, x
, reload_class
, reload_mode
, sri
);
6425 /* Worker function for TARGET_CLASS_LIKELY_SPILLED_P. */
6428 frv_class_likely_spilled_p (reg_class_t rclass
)
6438 case FDPIC_FPTR_REGS
:
6458 /* An expression for the alignment of a structure field FIELD if the
6459 alignment computed in the usual way is COMPUTED. GCC uses this
6460 value instead of the value in `BIGGEST_ALIGNMENT' or
6461 `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */
6463 /* The definition type of the bit field data is either char, short, long or
6464 long long. The maximum bit size is the number of bits of its own type.
6466 The bit field data is assigned to a storage unit that has an adequate size
6467 for bit field data retention and is located at the smallest address.
6469 Consecutive bit field data are packed at consecutive bits having the same
6470 storage unit, with regard to the type, beginning with the MSB and continuing
6473 If a field to be assigned lies over a bit field type boundary, its
6474 assignment is completed by aligning it with a boundary suitable for the
6477 When a bit field having a bit length of 0 is declared, it is forcibly
6478 assigned to the next storage unit.
6491 &x 00000000 00000000 00000000 00000000
6494 &x+4 00000000 00000000 00000000 00000000
6497 &x+8 00000000 00000000 00000000 00000000
6500 &x+12 00000000 00000000 00000000 00000000
6506 frv_adjust_field_align (tree field
, int computed
)
6508 /* Make sure that the bitfield is not wider than the type. */
6509 if (DECL_BIT_FIELD (field
)
6510 && !DECL_ARTIFICIAL (field
))
6512 tree parent
= DECL_CONTEXT (field
);
6513 tree prev
= NULL_TREE
;
6516 for (cur
= TYPE_FIELDS (parent
); cur
&& cur
!= field
; cur
= DECL_CHAIN (cur
))
6518 if (TREE_CODE (cur
) != FIELD_DECL
)
6526 /* If this isn't a :0 field and if the previous element is a bitfield
6527 also, see if the type is different, if so, we will need to align the
6528 bit-field to the next boundary. */
6530 && ! DECL_PACKED (field
)
6531 && ! integer_zerop (DECL_SIZE (field
))
6532 && DECL_BIT_FIELD_TYPE (field
) != DECL_BIT_FIELD_TYPE (prev
))
6534 int prev_align
= TYPE_ALIGN (TREE_TYPE (prev
));
6535 int cur_align
= TYPE_ALIGN (TREE_TYPE (field
));
6536 computed
= (prev_align
> cur_align
) ? prev_align
: cur_align
;
6544 /* A C expression that is nonzero if it is permissible to store a value of mode
6545 MODE in hard register number REGNO (or in several registers starting with
6546 that one). For a machine where all registers are equivalent, a suitable
6549 #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
6551 It is not necessary for this macro to check for the numbers of fixed
6552 registers, because the allocation mechanism considers them to be always
6555 On some machines, double-precision values must be kept in even/odd register
6556 pairs. The way to implement that is to define this macro to reject odd
6557 register numbers for such modes.
6559 The minimum requirement for a mode to be OK in a register is that the
6560 `movMODE' instruction pattern support moves between the register and any
6561 other hard register for which the mode is OK; and that moving a value into
6562 the register and back out not alter it.
6564 Since the same instruction used to move `SImode' will work for all narrower
6565 integer modes, it is not necessary on any machine for `HARD_REGNO_MODE_OK'
6566 to distinguish between these modes, provided you define patterns `movhi',
6567 etc., to take advantage of this. This is useful because of the interaction
6568 between `HARD_REGNO_MODE_OK' and `MODES_TIEABLE_P'; it is very desirable for
6569 all integer modes to be tieable.
6571 Many machines have special registers for floating point arithmetic. Often
6572 people assume that floating point machine modes are allowed only in floating
6573 point registers. This is not true. Any registers that can hold integers
6574 can safely *hold* a floating point machine mode, whether or not floating
6575 arithmetic can be done on it in those registers. Integer move instructions
6576 can be used to move the values.
6578 On some machines, though, the converse is true: fixed-point machine modes
6579 may not go in floating registers. This is true if the floating registers
6580 normalize any value stored in them, because storing a non-floating value
6581 there would garble it. In this case, `HARD_REGNO_MODE_OK' should reject
6582 fixed-point machine modes in floating registers. But if the floating
6583 registers do not automatically normalize, if you can store any bit pattern
6584 in one and retrieve it unchanged without a trap, then any machine mode may
6585 go in a floating register, so you can define this macro to say so.
6587 The primary significance of special floating registers is rather that they
6588 are the registers acceptable in floating point arithmetic instructions.
6589 However, this is of no concern to `HARD_REGNO_MODE_OK'. You handle it by
6590 writing the proper constraints for those instructions.
6592 On some machines, the floating registers are especially slow to access, so
6593 that it is better to store a value in a stack frame than in such a register
6594 if floating point arithmetic is not being done. As long as the floating
6595 registers are not in class `GENERAL_REGS', they will not be used unless some
6596 pattern's constraint asks for one. */
6599 frv_hard_regno_mode_ok (int regno
, machine_mode mode
)
6609 return ICC_P (regno
) || GPR_P (regno
);
6612 return CR_P (regno
) || GPR_P (regno
);
6615 return FCC_P (regno
) || GPR_P (regno
);
6621 /* Set BASE to the first register in REGNO's class. Set MASK to the
6622 bits that must be clear in (REGNO - BASE) for the register to be
6624 if (INTEGRAL_MODE_P (mode
) || FLOAT_MODE_P (mode
) || VECTOR_MODE_P (mode
))
6628 /* ACCGs store one byte. Two-byte quantities must start in
6629 even-numbered registers, four-byte ones in registers whose
6630 numbers are divisible by four, and so on. */
6632 mask
= GET_MODE_SIZE (mode
) - 1;
6636 /* The other registers store one word. */
6637 if (GPR_P (regno
) || regno
== AP_FIRST
)
6640 else if (FPR_P (regno
))
6643 else if (ACC_P (regno
))
6646 else if (SPR_P (regno
))
6647 return mode
== SImode
;
6649 /* Fill in the table. */
6653 /* Anything smaller than an SI is OK in any word-sized register. */
6654 if (GET_MODE_SIZE (mode
) < 4)
6657 mask
= (GET_MODE_SIZE (mode
) / 4) - 1;
6659 return (((regno
- base
) & mask
) == 0);
6666 /* A C expression for the number of consecutive hard registers, starting at
6667 register number REGNO, required to hold a value of mode MODE.
6669 On a machine where all registers are exactly one word, a suitable definition
6672 #define HARD_REGNO_NREGS(REGNO, MODE) \
6673 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
6674 / UNITS_PER_WORD)) */
6676 /* On the FRV, make the CC_FP mode take 3 words in the integer registers, so
6677 that we can build the appropriate instructions to properly reload the
6678 values. Also, make the byte-sized accumulator guards use one guard
6682 frv_hard_regno_nregs (int regno
, machine_mode mode
)
6685 return GET_MODE_SIZE (mode
);
6687 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6691 /* A C expression for the maximum number of consecutive registers of
6692 class RCLASS needed to hold a value of mode MODE.
6694 This is closely related to the macro `HARD_REGNO_NREGS'. In fact, the value
6695 of the macro `CLASS_MAX_NREGS (RCLASS, MODE)' should be the maximum value of
6696 `HARD_REGNO_NREGS (REGNO, MODE)' for all REGNO values in the class RCLASS.
6698 This macro helps control the handling of multiple-word values in
6701 This declaration is required. */
6704 frv_class_max_nregs (enum reg_class rclass
, machine_mode mode
)
6706 if (rclass
== ACCG_REGS
)
6707 /* An N-byte value requires N accumulator guards. */
6708 return GET_MODE_SIZE (mode
);
6710 return (GET_MODE_SIZE (mode
) + UNITS_PER_WORD
- 1) / UNITS_PER_WORD
;
6714 /* A C expression that is nonzero if X is a legitimate constant for an
6715 immediate operand on the target machine. You can assume that X satisfies
6716 `CONSTANT_P', so you need not check this. In fact, `1' is a suitable
6717 definition for this macro on machines where anything `CONSTANT_P' is valid. */
6720 frv_legitimate_constant_p (machine_mode mode
, rtx x
)
6722 /* frv_cannot_force_const_mem always returns true for FDPIC. This
6723 means that the move expanders will be expected to deal with most
6724 kinds of constant, regardless of what we return here.
6726 However, among its other duties, frv_legitimate_constant_p decides whether
6727 a constant can be entered into reg_equiv_constant[]. If we return true,
6728 reload can create new instances of the constant whenever it likes.
6730 The idea is therefore to accept as many constants as possible (to give
6731 reload more freedom) while rejecting constants that can only be created
6732 at certain times. In particular, anything with a symbolic component will
6733 require use of the pseudo FDPIC register, which is only available before
6736 return LEGITIMATE_PIC_OPERAND_P (x
);
6738 /* All of the integer constants are ok. */
6739 if (GET_CODE (x
) != CONST_DOUBLE
)
6742 /* double integer constants are ok. */
6743 if (GET_MODE (x
) == VOIDmode
|| mode
== DImode
)
6746 /* 0 is always ok. */
6747 if (x
== CONST0_RTX (mode
))
6750 /* If floating point is just emulated, allow any constant, since it will be
6751 constructed in the GPRs. */
6752 if (!TARGET_HAS_FPRS
)
6755 if (mode
== DFmode
&& !TARGET_DOUBLE
)
6758 /* Otherwise store the constant away and do a load. */
6762 /* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
6763 CC_NZ for comparisons against zero in which a single Z or N flag test
6764 is enough, CC_UNS for other unsigned comparisons, and CC for other
6765 signed comparisons. */
6768 frv_select_cc_mode (enum rtx_code code
, rtx x
, rtx y
)
6770 if (GET_MODE_CLASS (GET_MODE (x
)) == MODE_FLOAT
)
6779 return y
== const0_rtx
? CC_NZmode
: CCmode
;
6785 return y
== const0_rtx
? CC_NZmode
: CC_UNSmode
;
6793 /* Worker function for TARGET_REGISTER_MOVE_COST. */
6795 #define HIGH_COST 40
6796 #define MEDIUM_COST 3
6800 frv_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
6801 reg_class_t from
, reg_class_t to
)
6814 case FDPIC_FPTR_REGS
:
6815 case FDPIC_CALL_REGS
:
6828 case FDPIC_FPTR_REGS
:
6829 case FDPIC_CALL_REGS
:
6854 case FDPIC_FPTR_REGS
:
6855 case FDPIC_CALL_REGS
:
6879 case FDPIC_FPTR_REGS
:
6880 case FDPIC_CALL_REGS
:
6901 /* Worker function for TARGET_MEMORY_MOVE_COST. */
6904 frv_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED
,
6905 reg_class_t rclass ATTRIBUTE_UNUSED
,
6906 bool in ATTRIBUTE_UNUSED
)
6912 /* Implementation of TARGET_ASM_INTEGER. In the FRV case we need to
6913 use ".picptr" to generate safe relocations for PIC code. We also
6914 need a fixup entry for aligned (non-debugging) code. */
6917 frv_assemble_integer (rtx value
, unsigned int size
, int aligned_p
)
6919 if ((flag_pic
|| TARGET_FDPIC
) && size
== UNITS_PER_WORD
)
6921 if (GET_CODE (value
) == CONST
6922 || GET_CODE (value
) == SYMBOL_REF
6923 || GET_CODE (value
) == LABEL_REF
)
6925 if (TARGET_FDPIC
&& GET_CODE (value
) == SYMBOL_REF
6926 && SYMBOL_REF_FUNCTION_P (value
))
6928 fputs ("\t.picptr\tfuncdesc(", asm_out_file
);
6929 output_addr_const (asm_out_file
, value
);
6930 fputs (")\n", asm_out_file
);
6933 else if (TARGET_FDPIC
&& GET_CODE (value
) == CONST
6934 && frv_function_symbol_referenced_p (value
))
6936 if (aligned_p
&& !TARGET_FDPIC
)
6938 static int label_num
= 0;
6942 ASM_GENERATE_INTERNAL_LABEL (buf
, "LCP", label_num
++);
6943 p
= (* targetm
.strip_name_encoding
) (buf
);
6945 fprintf (asm_out_file
, "%s:\n", p
);
6946 fprintf (asm_out_file
, "%s\n", FIXUP_SECTION_ASM_OP
);
6947 fprintf (asm_out_file
, "\t.picptr\t%s\n", p
);
6948 fprintf (asm_out_file
, "\t.previous\n");
6950 assemble_integer_with_op ("\t.picptr\t", value
);
6955 /* We've set the unaligned SI op to NULL, so we always have to
6956 handle the unaligned case here. */
6957 assemble_integer_with_op ("\t.4byte\t", value
);
6961 return default_assemble_integer (value
, size
, aligned_p
);
6964 /* Function to set up the backend function structure. */
6966 static struct machine_function
*
6967 frv_init_machine_status (void)
6969 return ggc_cleared_alloc
<machine_function
> ();
6972 /* Implement TARGET_SCHED_ISSUE_RATE. */
6975 frv_issue_rate (void)
6980 switch (frv_cpu_type
)
6984 case FRV_CPU_SIMPLE
:
6992 case FRV_CPU_GENERIC
:
6994 case FRV_CPU_TOMCAT
:
7002 /* Return the value of INSN's acc_group attribute. */
7005 frv_acc_group (rtx insn
)
7007 /* This distinction only applies to the FR550 packing constraints. */
7008 if (frv_cpu_type
== FRV_CPU_FR550
)
7010 subrtx_iterator::array_type array
;
7011 FOR_EACH_SUBRTX (iter
, array
, PATTERN (insn
), NONCONST
)
7014 unsigned int regno
= REGNO (*iter
);
7015 /* If REGNO refers to an accumulator, return ACC_GROUP_ODD if
7016 the bit 2 of the register number is set and ACC_GROUP_EVEN if
7019 return (regno
- ACC_FIRST
) & 4 ? ACC_GROUP_ODD
: ACC_GROUP_EVEN
;
7021 return (regno
- ACCG_FIRST
) & 4 ? ACC_GROUP_ODD
: ACC_GROUP_EVEN
;
7024 return ACC_GROUP_NONE
;
7027 /* Return the index of the DFA unit in FRV_UNIT_NAMES[] that instruction
7028 INSN will try to claim first. Since this value depends only on the
7029 type attribute, we can cache the results in FRV_TYPE_TO_UNIT[]. */
7032 frv_insn_unit (rtx_insn
*insn
)
7034 enum attr_type type
;
7036 type
= get_attr_type (insn
);
7037 if (frv_type_to_unit
[type
] == ARRAY_SIZE (frv_unit_codes
))
7039 /* We haven't seen this type of instruction before. */
7043 /* Issue the instruction on its own to see which unit it prefers. */
7044 state
= alloca (state_size ());
7045 state_reset (state
);
7046 state_transition (state
, insn
);
7048 /* Find out which unit was taken. */
7049 for (unit
= 0; unit
< ARRAY_SIZE (frv_unit_codes
); unit
++)
7050 if (cpu_unit_reservation_p (state
, frv_unit_codes
[unit
]))
7053 gcc_assert (unit
!= ARRAY_SIZE (frv_unit_codes
));
7055 frv_type_to_unit
[type
] = unit
;
7057 return frv_type_to_unit
[type
];
7060 /* Return true if INSN issues to a branch unit. */
7063 frv_issues_to_branch_unit_p (rtx_insn
*insn
)
7065 return frv_unit_groups
[frv_insn_unit (insn
)] == GROUP_B
;
7068 /* The instructions in the packet, partitioned into groups. */
7069 struct frv_packet_group
{
7070 /* How many instructions in the packet belong to this group. */
7071 unsigned int num_insns
;
7073 /* A list of the instructions that belong to this group, in the order
7074 they appear in the rtl stream. */
7075 rtx_insn
*insns
[ARRAY_SIZE (frv_unit_codes
)];
7077 /* The contents of INSNS after they have been sorted into the correct
7078 assembly-language order. Element X issues to unit X. The list may
7079 contain extra nops. */
7080 rtx_insn
*sorted
[ARRAY_SIZE (frv_unit_codes
)];
7082 /* The member of frv_nops[] to use in sorted[]. */
7086 /* The current state of the packing pass, implemented by frv_pack_insns. */
7088 /* The state of the pipeline DFA. */
7091 /* Which hardware registers are set within the current packet,
7092 and the conditions under which they are set. */
7093 regstate_t regstate
[FIRST_PSEUDO_REGISTER
];
7095 /* The memory locations that have been modified so far in this
7096 packet. MEM is the memref and COND is the regstate_t condition
7097 under which it is set. */
7103 /* The number of valid entries in MEMS. The value is larger than
7104 ARRAY_SIZE (mems) if there were too many mems to record. */
7105 unsigned int num_mems
;
7107 /* The maximum number of instructions that can be packed together. */
7108 unsigned int issue_rate
;
7110 /* The instructions in the packet, partitioned into groups. */
7111 struct frv_packet_group groups
[NUM_GROUPS
];
7113 /* The instructions that make up the current packet. */
7114 rtx_insn
*insns
[ARRAY_SIZE (frv_unit_codes
)];
7115 unsigned int num_insns
;
7118 /* Return the regstate_t flags for the given COND_EXEC condition.
7119 Abort if the condition isn't in the right form. */
7122 frv_cond_flags (rtx cond
)
7124 gcc_assert ((GET_CODE (cond
) == EQ
|| GET_CODE (cond
) == NE
)
7125 && GET_CODE (XEXP (cond
, 0)) == REG
7126 && CR_P (REGNO (XEXP (cond
, 0)))
7127 && XEXP (cond
, 1) == const0_rtx
);
7128 return ((REGNO (XEXP (cond
, 0)) - CR_FIRST
)
7129 | (GET_CODE (cond
) == NE
7131 : REGSTATE_IF_FALSE
));
7135 /* Return true if something accessed under condition COND2 can
7136 conflict with something written under condition COND1. */
7139 frv_regstate_conflict_p (regstate_t cond1
, regstate_t cond2
)
7141 /* If either reference was unconditional, we have a conflict. */
7142 if ((cond1
& REGSTATE_IF_EITHER
) == 0
7143 || (cond2
& REGSTATE_IF_EITHER
) == 0)
7146 /* The references might conflict if they were controlled by
7148 if ((cond1
& REGSTATE_CC_MASK
) != (cond2
& REGSTATE_CC_MASK
))
7151 /* They definitely conflict if they are controlled by the
7153 if ((cond1
& cond2
& REGSTATE_IF_EITHER
) != 0)
7160 /* Return true if an instruction with pattern PAT depends on an
7161 instruction in the current packet. COND describes the condition
7162 under which PAT might be set or used. */
7165 frv_registers_conflict_p_1 (rtx pat
, regstate_t cond
)
7167 subrtx_var_iterator::array_type array
;
7168 FOR_EACH_SUBRTX_VAR (iter
, array
, pat
, NONCONST
)
7171 if (GET_CODE (x
) == REG
)
7174 FOR_EACH_REGNO (regno
, x
)
7175 if ((frv_packet
.regstate
[regno
] & REGSTATE_MODIFIED
) != 0)
7176 if (frv_regstate_conflict_p (frv_packet
.regstate
[regno
], cond
))
7179 else if (GET_CODE (x
) == MEM
)
7181 /* If we ran out of memory slots, assume a conflict. */
7182 if (frv_packet
.num_mems
> ARRAY_SIZE (frv_packet
.mems
))
7185 /* Check for output or true dependencies with earlier MEMs. */
7186 for (unsigned int i
= 0; i
< frv_packet
.num_mems
; i
++)
7187 if (frv_regstate_conflict_p (frv_packet
.mems
[i
].cond
, cond
))
7189 if (true_dependence (frv_packet
.mems
[i
].mem
, VOIDmode
, x
))
7192 if (output_dependence (frv_packet
.mems
[i
].mem
, x
))
7197 /* The return values of calls aren't significant: they describe
7198 the effect of the call as a whole, not of the insn itself. */
7199 else if (GET_CODE (x
) == SET
&& GET_CODE (SET_SRC (x
)) == CALL
)
7200 iter
.substitute (SET_SRC (x
));
7206 /* Return true if something in X might depend on an instruction
7207 in the current packet. */
7210 frv_registers_conflict_p (rtx x
)
7215 if (GET_CODE (x
) == COND_EXEC
)
7217 if (frv_registers_conflict_p_1 (XEXP (x
, 0), flags
))
7220 flags
|= frv_cond_flags (XEXP (x
, 0));
7223 return frv_registers_conflict_p_1 (x
, flags
);
7227 /* A note_stores callback. DATA points to the regstate_t condition
7228 under which X is modified. Update FRV_PACKET accordingly. */
7231 frv_registers_update_1 (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
7235 if (GET_CODE (x
) == REG
)
7236 FOR_EACH_REGNO (regno
, x
)
7237 frv_packet
.regstate
[regno
] |= *(regstate_t
*) data
;
7239 if (GET_CODE (x
) == MEM
)
7241 if (frv_packet
.num_mems
< ARRAY_SIZE (frv_packet
.mems
))
7243 frv_packet
.mems
[frv_packet
.num_mems
].mem
= x
;
7244 frv_packet
.mems
[frv_packet
.num_mems
].cond
= *(regstate_t
*) data
;
7246 frv_packet
.num_mems
++;
7251 /* Update the register state information for an instruction whose
7255 frv_registers_update (rtx x
)
7259 flags
= REGSTATE_MODIFIED
;
7260 if (GET_CODE (x
) == COND_EXEC
)
7262 flags
|= frv_cond_flags (XEXP (x
, 0));
7265 note_stores (x
, frv_registers_update_1
, &flags
);
7269 /* Initialize frv_packet for the start of a new packet. */
7272 frv_start_packet (void)
7274 enum frv_insn_group group
;
7276 memset (frv_packet
.regstate
, 0, sizeof (frv_packet
.regstate
));
7277 frv_packet
.num_mems
= 0;
7278 frv_packet
.num_insns
= 0;
7279 for (group
= GROUP_I
; group
< NUM_GROUPS
;
7280 group
= (enum frv_insn_group
) (group
+ 1))
7281 frv_packet
.groups
[group
].num_insns
= 0;
7285 /* Likewise for the start of a new basic block. */
7288 frv_start_packet_block (void)
7290 state_reset (frv_packet
.dfa_state
);
7291 frv_start_packet ();
7295 /* Finish the current packet, if any, and start a new one. Call
7296 HANDLE_PACKET with FRV_PACKET describing the completed packet. */
7299 frv_finish_packet (void (*handle_packet
) (void))
7301 if (frv_packet
.num_insns
> 0)
7304 state_transition (frv_packet
.dfa_state
, 0);
7305 frv_start_packet ();
7310 /* Return true if INSN can be added to the current packet. Update
7311 the DFA state on success. */
7314 frv_pack_insn_p (rtx_insn
*insn
)
7316 /* See if the packet is already as long as it can be. */
7317 if (frv_packet
.num_insns
== frv_packet
.issue_rate
)
7320 /* If the scheduler thought that an instruction should start a packet,
7321 it's usually a good idea to believe it. It knows much more about
7322 the latencies than we do.
7324 There are some exceptions though:
7326 - Conditional instructions are scheduled on the assumption that
7327 they will be executed. This is usually a good thing, since it
7328 tends to avoid unnecessary stalls in the conditional code.
7329 But we want to pack conditional instructions as tightly as
7330 possible, in order to optimize the case where they aren't
7333 - The scheduler will always put branches on their own, even
7334 if there's no real dependency.
7336 - There's no point putting a call in its own packet unless
7338 if (frv_packet
.num_insns
> 0
7339 && NONJUMP_INSN_P (insn
)
7340 && GET_MODE (insn
) == TImode
7341 && GET_CODE (PATTERN (insn
)) != COND_EXEC
)
7344 /* Check for register conflicts. Don't do this for setlo since any
7345 conflict will be with the partnering sethi, with which it can
7347 if (get_attr_type (insn
) != TYPE_SETLO
)
7348 if (frv_registers_conflict_p (PATTERN (insn
)))
7351 return state_transition (frv_packet
.dfa_state
, insn
) < 0;
7355 /* Add instruction INSN to the current packet. */
7358 frv_add_insn_to_packet (rtx_insn
*insn
)
7360 struct frv_packet_group
*packet_group
;
7362 packet_group
= &frv_packet
.groups
[frv_unit_groups
[frv_insn_unit (insn
)]];
7363 packet_group
->insns
[packet_group
->num_insns
++] = insn
;
7364 frv_packet
.insns
[frv_packet
.num_insns
++] = insn
;
7366 frv_registers_update (PATTERN (insn
));
7370 /* Insert INSN (a member of frv_nops[]) into the current packet. If the
7371 packet ends in a branch or call, insert the nop before it, otherwise
7375 frv_insert_nop_in_packet (rtx_insn
*insn
)
7377 struct frv_packet_group
*packet_group
;
7380 packet_group
= &frv_packet
.groups
[frv_unit_groups
[frv_insn_unit (insn
)]];
7381 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
7382 if (! NONJUMP_INSN_P (last
))
7384 insn
= emit_insn_before (PATTERN (insn
), last
);
7385 frv_packet
.insns
[frv_packet
.num_insns
- 1] = insn
;
7386 frv_packet
.insns
[frv_packet
.num_insns
++] = last
;
7390 insn
= emit_insn_after (PATTERN (insn
), last
);
7391 frv_packet
.insns
[frv_packet
.num_insns
++] = insn
;
7393 packet_group
->insns
[packet_group
->num_insns
++] = insn
;
7397 /* If packing is enabled, divide the instructions into packets and
7398 return true. Call HANDLE_PACKET for each complete packet. */
7401 frv_for_each_packet (void (*handle_packet
) (void))
7403 rtx_insn
*insn
, *next_insn
;
7405 frv_packet
.issue_rate
= frv_issue_rate ();
7407 /* Early exit if we don't want to pack insns. */
7409 || !flag_schedule_insns_after_reload
7410 || !TARGET_VLIW_BRANCH
7411 || frv_packet
.issue_rate
== 1)
7414 /* Set up the initial packing state. */
7416 frv_packet
.dfa_state
= alloca (state_size ());
7418 frv_start_packet_block ();
7419 for (insn
= get_insns (); insn
!= 0; insn
= next_insn
)
7424 code
= GET_CODE (insn
);
7425 next_insn
= NEXT_INSN (insn
);
7427 if (code
== CODE_LABEL
)
7429 frv_finish_packet (handle_packet
);
7430 frv_start_packet_block ();
7434 switch (GET_CODE (PATTERN (insn
)))
7441 /* Calls mustn't be packed on a TOMCAT. */
7442 if (CALL_P (insn
) && frv_cpu_type
== FRV_CPU_TOMCAT
)
7443 frv_finish_packet (handle_packet
);
7445 /* Since the last instruction in a packet determines the EH
7446 region, any exception-throwing instruction must come at
7447 the end of reordered packet. Insns that issue to a
7448 branch unit are bound to come last; for others it's
7449 too hard to predict. */
7450 eh_insn_p
= (find_reg_note (insn
, REG_EH_REGION
, NULL
) != NULL
);
7451 if (eh_insn_p
&& !frv_issues_to_branch_unit_p (insn
))
7452 frv_finish_packet (handle_packet
);
7454 /* Finish the current packet if we can't add INSN to it.
7455 Simulate cycles until INSN is ready to issue. */
7456 if (!frv_pack_insn_p (insn
))
7458 frv_finish_packet (handle_packet
);
7459 while (!frv_pack_insn_p (insn
))
7460 state_transition (frv_packet
.dfa_state
, 0);
7463 /* Add the instruction to the packet. */
7464 frv_add_insn_to_packet (insn
);
7466 /* Calls and jumps end a packet, as do insns that throw
7468 if (code
== CALL_INSN
|| code
== JUMP_INSN
|| eh_insn_p
)
7469 frv_finish_packet (handle_packet
);
7473 frv_finish_packet (handle_packet
);
7478 /* Subroutine of frv_sort_insn_group. We are trying to sort
7479 frv_packet.groups[GROUP].sorted[0...NUM_INSNS-1] into assembly
7480 language order. We have already picked a new position for
7481 frv_packet.groups[GROUP].sorted[X] if bit X of ISSUED is set.
7482 These instructions will occupy elements [0, LOWER_SLOT) and
7483 [UPPER_SLOT, NUM_INSNS) of the final (sorted) array. STATE is
7484 the DFA state after issuing these instructions.
7486 Try filling elements [LOWER_SLOT, UPPER_SLOT) with every permutation
7487 of the unused instructions. Return true if one such permutation gives
7488 a valid ordering, leaving the successful permutation in sorted[].
7489 Do not modify sorted[] until a valid permutation is found. */
7492 frv_sort_insn_group_1 (enum frv_insn_group group
,
7493 unsigned int lower_slot
, unsigned int upper_slot
,
7494 unsigned int issued
, unsigned int num_insns
,
7497 struct frv_packet_group
*packet_group
;
7503 /* Early success if we've filled all the slots. */
7504 if (lower_slot
== upper_slot
)
7507 packet_group
= &frv_packet
.groups
[group
];
7508 dfa_size
= state_size ();
7509 test_state
= alloca (dfa_size
);
7511 /* Try issuing each unused instruction. */
7512 for (i
= num_insns
- 1; i
+ 1 != 0; i
--)
7513 if (~issued
& (1 << i
))
7515 insn
= packet_group
->sorted
[i
];
7516 memcpy (test_state
, state
, dfa_size
);
7517 if (state_transition (test_state
, insn
) < 0
7518 && cpu_unit_reservation_p (test_state
,
7519 NTH_UNIT (group
, upper_slot
- 1))
7520 && frv_sort_insn_group_1 (group
, lower_slot
, upper_slot
- 1,
7521 issued
| (1 << i
), num_insns
,
7524 packet_group
->sorted
[upper_slot
- 1] = insn
;
7532 /* Compare two instructions by their frv_insn_unit. */
7535 frv_compare_insns (const void *first
, const void *second
)
7537 rtx_insn
* const *insn1
= (rtx_insn
* const *) first
;
7538 rtx_insn
* const *insn2
= (rtx_insn
* const *) second
;
7539 return frv_insn_unit (*insn1
) - frv_insn_unit (*insn2
);
7542 /* Copy frv_packet.groups[GROUP].insns[] to frv_packet.groups[GROUP].sorted[]
7543 and sort it into assembly language order. See frv.md for a description of
7547 frv_sort_insn_group (enum frv_insn_group group
)
7549 struct frv_packet_group
*packet_group
;
7550 unsigned int first
, i
, nop
, max_unit
, num_slots
;
7551 state_t state
, test_state
;
7554 packet_group
= &frv_packet
.groups
[group
];
7556 /* Assume no nop is needed. */
7557 packet_group
->nop
= 0;
7559 if (packet_group
->num_insns
== 0)
7562 /* Copy insns[] to sorted[]. */
7563 memcpy (packet_group
->sorted
, packet_group
->insns
,
7564 sizeof (rtx
) * packet_group
->num_insns
);
7566 /* Sort sorted[] by the unit that each insn tries to take first. */
7567 if (packet_group
->num_insns
> 1)
7568 qsort (packet_group
->sorted
, packet_group
->num_insns
,
7569 sizeof (rtx
), frv_compare_insns
);
7571 /* That's always enough for branch and control insns. */
7572 if (group
== GROUP_B
|| group
== GROUP_C
)
7575 dfa_size
= state_size ();
7576 state
= alloca (dfa_size
);
7577 test_state
= alloca (dfa_size
);
7579 /* Find the highest FIRST such that sorted[0...FIRST-1] can issue
7580 consecutively and such that the DFA takes unit X when sorted[X]
7581 is added. Set STATE to the new DFA state. */
7582 state_reset (test_state
);
7583 for (first
= 0; first
< packet_group
->num_insns
; first
++)
7585 memcpy (state
, test_state
, dfa_size
);
7586 if (state_transition (test_state
, packet_group
->sorted
[first
]) >= 0
7587 || !cpu_unit_reservation_p (test_state
, NTH_UNIT (group
, first
)))
7591 /* If all the instructions issued in ascending order, we're done. */
7592 if (first
== packet_group
->num_insns
)
7595 /* Add nops to the end of sorted[] and try each permutation until
7596 we find one that works. */
7597 for (nop
= 0; nop
< frv_num_nops
; nop
++)
7599 max_unit
= frv_insn_unit (frv_nops
[nop
]);
7600 if (frv_unit_groups
[max_unit
] == group
)
7602 packet_group
->nop
= frv_nops
[nop
];
7603 num_slots
= UNIT_NUMBER (max_unit
) + 1;
7604 for (i
= packet_group
->num_insns
; i
< num_slots
; i
++)
7605 packet_group
->sorted
[i
] = frv_nops
[nop
];
7606 if (frv_sort_insn_group_1 (group
, first
, num_slots
,
7607 (1 << first
) - 1, num_slots
, state
))
7614 /* Sort the current packet into assembly-language order. Set packing
7615 flags as appropriate. */
7618 frv_reorder_packet (void)
7620 unsigned int cursor
[NUM_GROUPS
];
7621 rtx insns
[ARRAY_SIZE (frv_unit_groups
)];
7622 unsigned int unit
, to
, from
;
7623 enum frv_insn_group group
;
7624 struct frv_packet_group
*packet_group
;
7626 /* First sort each group individually. */
7627 for (group
= GROUP_I
; group
< NUM_GROUPS
;
7628 group
= (enum frv_insn_group
) (group
+ 1))
7631 frv_sort_insn_group (group
);
7634 /* Go through the unit template and try add an instruction from
7635 that unit's group. */
7637 for (unit
= 0; unit
< ARRAY_SIZE (frv_unit_groups
); unit
++)
7639 group
= frv_unit_groups
[unit
];
7640 packet_group
= &frv_packet
.groups
[group
];
7641 if (cursor
[group
] < packet_group
->num_insns
)
7643 /* frv_reorg should have added nops for us. */
7644 gcc_assert (packet_group
->sorted
[cursor
[group
]]
7645 != packet_group
->nop
);
7646 insns
[to
++] = packet_group
->sorted
[cursor
[group
]++];
7650 gcc_assert (to
== frv_packet
.num_insns
);
7652 /* Clear the last instruction's packing flag, thus marking the end of
7653 a packet. Reorder the other instructions relative to it. */
7654 CLEAR_PACKING_FLAG (insns
[to
- 1]);
7655 for (from
= 0; from
< to
- 1; from
++)
7657 remove_insn (insns
[from
]);
7658 add_insn_before (insns
[from
], insns
[to
- 1], NULL
);
7659 SET_PACKING_FLAG (insns
[from
]);
7664 /* Divide instructions into packets. Reorder the contents of each
7665 packet so that they are in the correct assembly-language order.
7667 Since this pass can change the raw meaning of the rtl stream, it must
7668 only be called at the last minute, just before the instructions are
7672 frv_pack_insns (void)
7674 if (frv_for_each_packet (frv_reorder_packet
))
7675 frv_insn_packing_flag
= 0;
7677 frv_insn_packing_flag
= -1;
7680 /* See whether we need to add nops to group GROUP in order to
7681 make a valid packet. */
7684 frv_fill_unused_units (enum frv_insn_group group
)
7686 unsigned int non_nops
, nops
, i
;
7687 struct frv_packet_group
*packet_group
;
7689 packet_group
= &frv_packet
.groups
[group
];
7691 /* Sort the instructions into assembly-language order.
7692 Use nops to fill slots that are otherwise unused. */
7693 frv_sort_insn_group (group
);
7695 /* See how many nops are needed before the final useful instruction. */
7697 for (non_nops
= 0; non_nops
< packet_group
->num_insns
; non_nops
++)
7698 while (packet_group
->sorted
[i
++] == packet_group
->nop
)
7701 /* Insert that many nops into the instruction stream. */
7703 frv_insert_nop_in_packet (packet_group
->nop
);
7706 /* Return true if accesses IO1 and IO2 refer to the same doubleword. */
7709 frv_same_doubleword_p (const struct frv_io
*io1
, const struct frv_io
*io2
)
7711 if (io1
->const_address
!= 0 && io2
->const_address
!= 0)
7712 return io1
->const_address
== io2
->const_address
;
7714 if (io1
->var_address
!= 0 && io2
->var_address
!= 0)
7715 return rtx_equal_p (io1
->var_address
, io2
->var_address
);
7720 /* Return true if operations IO1 and IO2 are guaranteed to complete
7724 frv_io_fixed_order_p (const struct frv_io
*io1
, const struct frv_io
*io2
)
7726 /* The order of writes is always preserved. */
7727 if (io1
->type
== FRV_IO_WRITE
&& io2
->type
== FRV_IO_WRITE
)
7730 /* The order of reads isn't preserved. */
7731 if (io1
->type
!= FRV_IO_WRITE
&& io2
->type
!= FRV_IO_WRITE
)
7734 /* One operation is a write and the other is (or could be) a read.
7735 The order is only guaranteed if the accesses are to the same
7737 return frv_same_doubleword_p (io1
, io2
);
7740 /* Generalize I/O operation X so that it covers both X and Y. */
7743 frv_io_union (struct frv_io
*x
, const struct frv_io
*y
)
7745 if (x
->type
!= y
->type
)
7746 x
->type
= FRV_IO_UNKNOWN
;
7747 if (!frv_same_doubleword_p (x
, y
))
7749 x
->const_address
= 0;
7754 /* Fill IO with information about the load or store associated with
7755 membar instruction INSN. */
7758 frv_extract_membar (struct frv_io
*io
, rtx_insn
*insn
)
7760 extract_insn (insn
);
7761 io
->type
= (enum frv_io_type
) INTVAL (recog_data
.operand
[2]);
7762 io
->const_address
= INTVAL (recog_data
.operand
[1]);
7763 io
->var_address
= XEXP (recog_data
.operand
[0], 0);
7766 /* A note_stores callback for which DATA points to an rtx. Nullify *DATA
7767 if X is a register and *DATA depends on X. */
7770 frv_io_check_address (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
7772 rtx
*other
= (rtx
*) data
;
7774 if (REG_P (x
) && *other
!= 0 && reg_overlap_mentioned_p (x
, *other
))
7778 /* A note_stores callback for which DATA points to a HARD_REG_SET.
7779 Remove every modified register from the set. */
7782 frv_io_handle_set (rtx x
, const_rtx pat ATTRIBUTE_UNUSED
, void *data
)
7784 HARD_REG_SET
*set
= (HARD_REG_SET
*) data
;
7788 FOR_EACH_REGNO (regno
, x
)
7789 CLEAR_HARD_REG_BIT (*set
, regno
);
7792 /* A note_uses callback that adds all registers in *X to hard register
7796 frv_io_handle_use (rtx
*x
, void *data
)
7798 find_all_hard_regs (*x
, (HARD_REG_SET
*) data
);
7801 /* Go through block BB looking for membars to remove. There are two
7802 cases where intra-block analysis is enough:
7804 - a membar is redundant if it occurs between two consecutive I/O
7805 operations and if those operations are guaranteed to complete
7808 - a membar for a __builtin_read is redundant if the result is
7809 used before the next I/O operation is issued.
7811 If the last membar in the block could not be removed, and there
7812 are guaranteed to be no I/O operations between that membar and
7813 the end of the block, store the membar in *LAST_MEMBAR, otherwise
7816 Describe the block's first I/O operation in *NEXT_IO. Describe
7817 an unknown operation if the block doesn't do any I/O. */
7820 frv_optimize_membar_local (basic_block bb
, struct frv_io
*next_io
,
7821 rtx_insn
**last_membar
)
7823 HARD_REG_SET used_regs
;
7824 rtx next_membar
, set
;
7828 /* NEXT_IO is the next I/O operation to be performed after the current
7829 instruction. It starts off as being an unknown operation. */
7830 memset (next_io
, 0, sizeof (*next_io
));
7832 /* NEXT_IS_END_P is true if NEXT_IO describes the end of the block. */
7833 next_is_end_p
= true;
7835 /* If the current instruction is a __builtin_read or __builtin_write,
7836 NEXT_MEMBAR is the membar instruction associated with it. NEXT_MEMBAR
7837 is null if the membar has already been deleted.
7839 Note that the initialization here should only be needed to
7840 suppress warnings. */
7843 /* USED_REGS is the set of registers that are used before the
7844 next I/O instruction. */
7845 CLEAR_HARD_REG_SET (used_regs
);
7847 for (insn
= BB_END (bb
); insn
!= BB_HEAD (bb
); insn
= PREV_INSN (insn
))
7850 /* We can't predict what a call will do to volatile memory. */
7851 memset (next_io
, 0, sizeof (struct frv_io
));
7852 next_is_end_p
= false;
7853 CLEAR_HARD_REG_SET (used_regs
);
7855 else if (INSN_P (insn
))
7856 switch (recog_memoized (insn
))
7858 case CODE_FOR_optional_membar_qi
:
7859 case CODE_FOR_optional_membar_hi
:
7860 case CODE_FOR_optional_membar_si
:
7861 case CODE_FOR_optional_membar_di
:
7865 /* Local information isn't enough to decide whether this
7866 membar is needed. Stash it away for later. */
7867 *last_membar
= insn
;
7868 frv_extract_membar (next_io
, insn
);
7869 next_is_end_p
= false;
7873 /* Check whether the I/O operation before INSN could be
7874 reordered with one described by NEXT_IO. If it can't,
7875 INSN will not be needed. */
7876 struct frv_io prev_io
;
7878 frv_extract_membar (&prev_io
, insn
);
7879 if (frv_io_fixed_order_p (&prev_io
, next_io
))
7883 ";; [Local] Removing membar %d since order"
7884 " of accesses is guaranteed\n",
7885 INSN_UID (next_membar
));
7887 insn
= NEXT_INSN (insn
);
7888 delete_insn (next_membar
);
7896 /* Invalidate NEXT_IO's address if it depends on something that
7897 is clobbered by INSN. */
7898 if (next_io
->var_address
)
7899 note_stores (PATTERN (insn
), frv_io_check_address
,
7900 &next_io
->var_address
);
7902 /* If the next membar is associated with a __builtin_read,
7903 see if INSN reads from that address. If it does, and if
7904 the destination register is used before the next I/O access,
7905 there is no need for the membar. */
7906 set
= PATTERN (insn
);
7907 if (next_io
->type
== FRV_IO_READ
7908 && next_io
->var_address
!= 0
7910 && GET_CODE (set
) == SET
7911 && GET_CODE (SET_DEST (set
)) == REG
7912 && TEST_HARD_REG_BIT (used_regs
, REGNO (SET_DEST (set
))))
7916 src
= SET_SRC (set
);
7917 if (GET_CODE (src
) == ZERO_EXTEND
)
7918 src
= XEXP (src
, 0);
7920 if (GET_CODE (src
) == MEM
7921 && rtx_equal_p (XEXP (src
, 0), next_io
->var_address
))
7925 ";; [Local] Removing membar %d since the target"
7926 " of %d is used before the I/O operation\n",
7927 INSN_UID (next_membar
), INSN_UID (insn
));
7929 if (next_membar
== *last_membar
)
7932 delete_insn (next_membar
);
7937 /* If INSN has volatile references, forget about any registers
7938 that are used after it. Otherwise forget about uses that
7939 are (or might be) defined by INSN. */
7940 if (volatile_refs_p (PATTERN (insn
)))
7941 CLEAR_HARD_REG_SET (used_regs
);
7943 note_stores (PATTERN (insn
), frv_io_handle_set
, &used_regs
);
7945 note_uses (&PATTERN (insn
), frv_io_handle_use
, &used_regs
);
7950 /* See if MEMBAR, the last membar instruction in BB, can be removed.
7951 FIRST_IO[X] describes the first operation performed by basic block X. */
7954 frv_optimize_membar_global (basic_block bb
, struct frv_io
*first_io
,
7957 struct frv_io this_io
, next_io
;
7961 /* We need to keep the membar if there is an edge to the exit block. */
7962 FOR_EACH_EDGE (succ
, ei
, bb
->succs
)
7963 /* for (succ = bb->succ; succ != 0; succ = succ->succ_next) */
7964 if (succ
->dest
== EXIT_BLOCK_PTR_FOR_FN (cfun
))
7967 /* Work out the union of all successor blocks. */
7968 ei
= ei_start (bb
->succs
);
7969 ei_cond (ei
, &succ
);
7970 /* next_io = first_io[bb->succ->dest->index]; */
7971 next_io
= first_io
[succ
->dest
->index
];
7972 ei
= ei_start (bb
->succs
);
7973 if (ei_cond (ei
, &succ
))
7975 for (ei_next (&ei
); ei_cond (ei
, &succ
); ei_next (&ei
))
7976 /*for (succ = bb->succ->succ_next; succ != 0; succ = succ->succ_next)*/
7977 frv_io_union (&next_io
, &first_io
[succ
->dest
->index
]);
7982 frv_extract_membar (&this_io
, membar
);
7983 if (frv_io_fixed_order_p (&this_io
, &next_io
))
7987 ";; [Global] Removing membar %d since order of accesses"
7988 " is guaranteed\n", INSN_UID (membar
));
7990 delete_insn (membar
);
7994 /* Remove redundant membars from the current function. */
7997 frv_optimize_membar (void)
8000 struct frv_io
*first_io
;
8001 rtx_insn
**last_membar
;
8003 compute_bb_for_insn ();
8004 first_io
= XCNEWVEC (struct frv_io
, last_basic_block_for_fn (cfun
));
8005 last_membar
= XCNEWVEC (rtx_insn
*, last_basic_block_for_fn (cfun
));
8007 FOR_EACH_BB_FN (bb
, cfun
)
8008 frv_optimize_membar_local (bb
, &first_io
[bb
->index
],
8009 &last_membar
[bb
->index
]);
8011 FOR_EACH_BB_FN (bb
, cfun
)
8012 if (last_membar
[bb
->index
] != 0)
8013 frv_optimize_membar_global (bb
, first_io
, last_membar
[bb
->index
]);
8019 /* Used by frv_reorg to keep track of the current packet's address. */
8020 static unsigned int frv_packet_address
;
8022 /* If the current packet falls through to a label, try to pad the packet
8023 with nops in order to fit the label's alignment requirements. */
8026 frv_align_label (void)
8028 unsigned int alignment
, target
, nop
;
8029 rtx_insn
*x
, *last
, *barrier
, *label
;
8031 /* Walk forward to the start of the next packet. Set ALIGNMENT to the
8032 maximum alignment of that packet, LABEL to the last label between
8033 the packets, and BARRIER to the last barrier. */
8034 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
8035 label
= barrier
= 0;
8037 for (x
= NEXT_INSN (last
); x
!= 0 && !INSN_P (x
); x
= NEXT_INSN (x
))
8041 unsigned int subalign
= 1 << label_to_alignment (x
);
8042 alignment
= MAX (alignment
, subalign
);
8049 /* If -malign-labels, and the packet falls through to an unaligned
8050 label, try introducing a nop to align that label to 8 bytes. */
8051 if (TARGET_ALIGN_LABELS
8054 && frv_packet
.num_insns
< frv_packet
.issue_rate
)
8055 alignment
= MAX (alignment
, 8);
8057 /* Advance the address to the end of the current packet. */
8058 frv_packet_address
+= frv_packet
.num_insns
* 4;
8060 /* Work out the target address, after alignment. */
8061 target
= (frv_packet_address
+ alignment
- 1) & -alignment
;
8063 /* If the packet falls through to the label, try to find an efficient
8064 padding sequence. */
8067 /* First try adding nops to the current packet. */
8068 for (nop
= 0; nop
< frv_num_nops
; nop
++)
8069 while (frv_packet_address
< target
&& frv_pack_insn_p (frv_nops
[nop
]))
8071 frv_insert_nop_in_packet (frv_nops
[nop
]);
8072 frv_packet_address
+= 4;
8075 /* If we still haven't reached the target, add some new packets that
8076 contain only nops. If there are two types of nop, insert an
8077 alternating sequence of frv_nops[0] and frv_nops[1], which will
8078 lead to packets like:
8085 etc. Just emit frv_nops[0] if that's the only nop we have. */
8086 last
= frv_packet
.insns
[frv_packet
.num_insns
- 1];
8088 while (frv_packet_address
< target
)
8090 last
= emit_insn_after (PATTERN (frv_nops
[nop
]), last
);
8091 frv_packet_address
+= 4;
8092 if (frv_num_nops
> 1)
8097 frv_packet_address
= target
;
8100 /* Subroutine of frv_reorg, called after each packet has been constructed
8104 frv_reorg_packet (void)
8106 frv_fill_unused_units (GROUP_I
);
8107 frv_fill_unused_units (GROUP_FM
);
8111 /* Add an instruction with pattern NOP to frv_nops[]. */
8114 frv_register_nop (rtx nop
)
8116 rtx_insn
*nop_insn
= make_insn_raw (nop
);
8117 SET_NEXT_INSN (nop_insn
) = 0;
8118 SET_PREV_INSN (nop_insn
) = 0;
8119 frv_nops
[frv_num_nops
++] = nop_insn
;
8122 /* Implement TARGET_MACHINE_DEPENDENT_REORG. Divide the instructions
8123 into packets and check whether we need to insert nops in order to
8124 fulfill the processor's issue requirements. Also, if the user has
8125 requested a certain alignment for a label, try to meet that alignment
8126 by inserting nops in the previous packet. */
8131 if (optimize
> 0 && TARGET_OPTIMIZE_MEMBAR
&& cfun
->machine
->has_membar_p
)
8132 frv_optimize_membar ();
8135 frv_register_nop (gen_nop ());
8137 frv_register_nop (gen_mnop ());
8138 if (TARGET_HARD_FLOAT
)
8139 frv_register_nop (gen_fnop ());
8141 /* Estimate the length of each branch. Although this may change after
8142 we've inserted nops, it will only do so in big functions. */
8143 shorten_branches (get_insns ());
8145 frv_packet_address
= 0;
8146 frv_for_each_packet (frv_reorg_packet
);
8149 #define def_builtin(name, type, code) \
8150 add_builtin_function ((name), (type), (code), BUILT_IN_MD, NULL, NULL)
8152 struct builtin_description
8154 enum insn_code icode
;
8156 enum frv_builtins code
;
8157 enum rtx_code comparison
;
8161 /* Media intrinsics that take a single, constant argument. */
8163 static struct builtin_description bdesc_set
[] =
8165 { CODE_FOR_mhdsets
, "__MHDSETS", FRV_BUILTIN_MHDSETS
, UNKNOWN
, 0 }
8168 /* Media intrinsics that take just one argument. */
8170 static struct builtin_description bdesc_1arg
[] =
8172 { CODE_FOR_mnot
, "__MNOT", FRV_BUILTIN_MNOT
, UNKNOWN
, 0 },
8173 { CODE_FOR_munpackh
, "__MUNPACKH", FRV_BUILTIN_MUNPACKH
, UNKNOWN
, 0 },
8174 { CODE_FOR_mbtoh
, "__MBTOH", FRV_BUILTIN_MBTOH
, UNKNOWN
, 0 },
8175 { CODE_FOR_mhtob
, "__MHTOB", FRV_BUILTIN_MHTOB
, UNKNOWN
, 0},
8176 { CODE_FOR_mabshs
, "__MABSHS", FRV_BUILTIN_MABSHS
, UNKNOWN
, 0 },
8177 { CODE_FOR_scutss
, "__SCUTSS", FRV_BUILTIN_SCUTSS
, UNKNOWN
, 0 }
8180 /* Media intrinsics that take two arguments. */
8182 static struct builtin_description bdesc_2arg
[] =
8184 { CODE_FOR_mand
, "__MAND", FRV_BUILTIN_MAND
, UNKNOWN
, 0},
8185 { CODE_FOR_mor
, "__MOR", FRV_BUILTIN_MOR
, UNKNOWN
, 0},
8186 { CODE_FOR_mxor
, "__MXOR", FRV_BUILTIN_MXOR
, UNKNOWN
, 0},
8187 { CODE_FOR_maveh
, "__MAVEH", FRV_BUILTIN_MAVEH
, UNKNOWN
, 0},
8188 { CODE_FOR_msaths
, "__MSATHS", FRV_BUILTIN_MSATHS
, UNKNOWN
, 0},
8189 { CODE_FOR_msathu
, "__MSATHU", FRV_BUILTIN_MSATHU
, UNKNOWN
, 0},
8190 { CODE_FOR_maddhss
, "__MADDHSS", FRV_BUILTIN_MADDHSS
, UNKNOWN
, 0},
8191 { CODE_FOR_maddhus
, "__MADDHUS", FRV_BUILTIN_MADDHUS
, UNKNOWN
, 0},
8192 { CODE_FOR_msubhss
, "__MSUBHSS", FRV_BUILTIN_MSUBHSS
, UNKNOWN
, 0},
8193 { CODE_FOR_msubhus
, "__MSUBHUS", FRV_BUILTIN_MSUBHUS
, UNKNOWN
, 0},
8194 { CODE_FOR_mqaddhss
, "__MQADDHSS", FRV_BUILTIN_MQADDHSS
, UNKNOWN
, 0},
8195 { CODE_FOR_mqaddhus
, "__MQADDHUS", FRV_BUILTIN_MQADDHUS
, UNKNOWN
, 0},
8196 { CODE_FOR_mqsubhss
, "__MQSUBHSS", FRV_BUILTIN_MQSUBHSS
, UNKNOWN
, 0},
8197 { CODE_FOR_mqsubhus
, "__MQSUBHUS", FRV_BUILTIN_MQSUBHUS
, UNKNOWN
, 0},
8198 { CODE_FOR_mpackh
, "__MPACKH", FRV_BUILTIN_MPACKH
, UNKNOWN
, 0},
8199 { CODE_FOR_mcop1
, "__Mcop1", FRV_BUILTIN_MCOP1
, UNKNOWN
, 0},
8200 { CODE_FOR_mcop2
, "__Mcop2", FRV_BUILTIN_MCOP2
, UNKNOWN
, 0},
8201 { CODE_FOR_mwcut
, "__MWCUT", FRV_BUILTIN_MWCUT
, UNKNOWN
, 0},
8202 { CODE_FOR_mqsaths
, "__MQSATHS", FRV_BUILTIN_MQSATHS
, UNKNOWN
, 0},
8203 { CODE_FOR_mqlclrhs
, "__MQLCLRHS", FRV_BUILTIN_MQLCLRHS
, UNKNOWN
, 0},
8204 { CODE_FOR_mqlmths
, "__MQLMTHS", FRV_BUILTIN_MQLMTHS
, UNKNOWN
, 0},
8205 { CODE_FOR_smul
, "__SMUL", FRV_BUILTIN_SMUL
, UNKNOWN
, 0},
8206 { CODE_FOR_umul
, "__UMUL", FRV_BUILTIN_UMUL
, UNKNOWN
, 0},
8207 { CODE_FOR_addss
, "__ADDSS", FRV_BUILTIN_ADDSS
, UNKNOWN
, 0},
8208 { CODE_FOR_subss
, "__SUBSS", FRV_BUILTIN_SUBSS
, UNKNOWN
, 0},
8209 { CODE_FOR_slass
, "__SLASS", FRV_BUILTIN_SLASS
, UNKNOWN
, 0},
8210 { CODE_FOR_scan
, "__SCAN", FRV_BUILTIN_SCAN
, UNKNOWN
, 0}
8213 /* Integer intrinsics that take two arguments and have no return value. */
8215 static struct builtin_description bdesc_int_void2arg
[] =
8217 { CODE_FOR_smass
, "__SMASS", FRV_BUILTIN_SMASS
, UNKNOWN
, 0},
8218 { CODE_FOR_smsss
, "__SMSSS", FRV_BUILTIN_SMSSS
, UNKNOWN
, 0},
8219 { CODE_FOR_smu
, "__SMU", FRV_BUILTIN_SMU
, UNKNOWN
, 0}
8222 static struct builtin_description bdesc_prefetches
[] =
8224 { CODE_FOR_frv_prefetch0
, "__data_prefetch0", FRV_BUILTIN_PREFETCH0
, UNKNOWN
,
8226 { CODE_FOR_frv_prefetch
, "__data_prefetch", FRV_BUILTIN_PREFETCH
, UNKNOWN
, 0}
8229 /* Media intrinsics that take two arguments, the first being an ACC number. */
8231 static struct builtin_description bdesc_cut
[] =
8233 { CODE_FOR_mcut
, "__MCUT", FRV_BUILTIN_MCUT
, UNKNOWN
, 0},
8234 { CODE_FOR_mcutss
, "__MCUTSS", FRV_BUILTIN_MCUTSS
, UNKNOWN
, 0},
8235 { CODE_FOR_mdcutssi
, "__MDCUTSSI", FRV_BUILTIN_MDCUTSSI
, UNKNOWN
, 0}
8238 /* Two-argument media intrinsics with an immediate second argument. */
8240 static struct builtin_description bdesc_2argimm
[] =
8242 { CODE_FOR_mrotli
, "__MROTLI", FRV_BUILTIN_MROTLI
, UNKNOWN
, 0},
8243 { CODE_FOR_mrotri
, "__MROTRI", FRV_BUILTIN_MROTRI
, UNKNOWN
, 0},
8244 { CODE_FOR_msllhi
, "__MSLLHI", FRV_BUILTIN_MSLLHI
, UNKNOWN
, 0},
8245 { CODE_FOR_msrlhi
, "__MSRLHI", FRV_BUILTIN_MSRLHI
, UNKNOWN
, 0},
8246 { CODE_FOR_msrahi
, "__MSRAHI", FRV_BUILTIN_MSRAHI
, UNKNOWN
, 0},
8247 { CODE_FOR_mexpdhw
, "__MEXPDHW", FRV_BUILTIN_MEXPDHW
, UNKNOWN
, 0},
8248 { CODE_FOR_mexpdhd
, "__MEXPDHD", FRV_BUILTIN_MEXPDHD
, UNKNOWN
, 0},
8249 { CODE_FOR_mdrotli
, "__MDROTLI", FRV_BUILTIN_MDROTLI
, UNKNOWN
, 0},
8250 { CODE_FOR_mcplhi
, "__MCPLHI", FRV_BUILTIN_MCPLHI
, UNKNOWN
, 0},
8251 { CODE_FOR_mcpli
, "__MCPLI", FRV_BUILTIN_MCPLI
, UNKNOWN
, 0},
8252 { CODE_FOR_mhsetlos
, "__MHSETLOS", FRV_BUILTIN_MHSETLOS
, UNKNOWN
, 0},
8253 { CODE_FOR_mhsetloh
, "__MHSETLOH", FRV_BUILTIN_MHSETLOH
, UNKNOWN
, 0},
8254 { CODE_FOR_mhsethis
, "__MHSETHIS", FRV_BUILTIN_MHSETHIS
, UNKNOWN
, 0},
8255 { CODE_FOR_mhsethih
, "__MHSETHIH", FRV_BUILTIN_MHSETHIH
, UNKNOWN
, 0},
8256 { CODE_FOR_mhdseth
, "__MHDSETH", FRV_BUILTIN_MHDSETH
, UNKNOWN
, 0},
8257 { CODE_FOR_mqsllhi
, "__MQSLLHI", FRV_BUILTIN_MQSLLHI
, UNKNOWN
, 0},
8258 { CODE_FOR_mqsrahi
, "__MQSRAHI", FRV_BUILTIN_MQSRAHI
, UNKNOWN
, 0}
8261 /* Media intrinsics that take two arguments and return void, the first argument
8262 being a pointer to 4 words in memory. */
8264 static struct builtin_description bdesc_void2arg
[] =
8266 { CODE_FOR_mdunpackh
, "__MDUNPACKH", FRV_BUILTIN_MDUNPACKH
, UNKNOWN
, 0},
8267 { CODE_FOR_mbtohe
, "__MBTOHE", FRV_BUILTIN_MBTOHE
, UNKNOWN
, 0},
8270 /* Media intrinsics that take three arguments, the first being a const_int that
8271 denotes an accumulator, and that return void. */
8273 static struct builtin_description bdesc_void3arg
[] =
8275 { CODE_FOR_mcpxrs
, "__MCPXRS", FRV_BUILTIN_MCPXRS
, UNKNOWN
, 0},
8276 { CODE_FOR_mcpxru
, "__MCPXRU", FRV_BUILTIN_MCPXRU
, UNKNOWN
, 0},
8277 { CODE_FOR_mcpxis
, "__MCPXIS", FRV_BUILTIN_MCPXIS
, UNKNOWN
, 0},
8278 { CODE_FOR_mcpxiu
, "__MCPXIU", FRV_BUILTIN_MCPXIU
, UNKNOWN
, 0},
8279 { CODE_FOR_mmulhs
, "__MMULHS", FRV_BUILTIN_MMULHS
, UNKNOWN
, 0},
8280 { CODE_FOR_mmulhu
, "__MMULHU", FRV_BUILTIN_MMULHU
, UNKNOWN
, 0},
8281 { CODE_FOR_mmulxhs
, "__MMULXHS", FRV_BUILTIN_MMULXHS
, UNKNOWN
, 0},
8282 { CODE_FOR_mmulxhu
, "__MMULXHU", FRV_BUILTIN_MMULXHU
, UNKNOWN
, 0},
8283 { CODE_FOR_mmachs
, "__MMACHS", FRV_BUILTIN_MMACHS
, UNKNOWN
, 0},
8284 { CODE_FOR_mmachu
, "__MMACHU", FRV_BUILTIN_MMACHU
, UNKNOWN
, 0},
8285 { CODE_FOR_mmrdhs
, "__MMRDHS", FRV_BUILTIN_MMRDHS
, UNKNOWN
, 0},
8286 { CODE_FOR_mmrdhu
, "__MMRDHU", FRV_BUILTIN_MMRDHU
, UNKNOWN
, 0},
8287 { CODE_FOR_mqcpxrs
, "__MQCPXRS", FRV_BUILTIN_MQCPXRS
, UNKNOWN
, 0},
8288 { CODE_FOR_mqcpxru
, "__MQCPXRU", FRV_BUILTIN_MQCPXRU
, UNKNOWN
, 0},
8289 { CODE_FOR_mqcpxis
, "__MQCPXIS", FRV_BUILTIN_MQCPXIS
, UNKNOWN
, 0},
8290 { CODE_FOR_mqcpxiu
, "__MQCPXIU", FRV_BUILTIN_MQCPXIU
, UNKNOWN
, 0},
8291 { CODE_FOR_mqmulhs
, "__MQMULHS", FRV_BUILTIN_MQMULHS
, UNKNOWN
, 0},
8292 { CODE_FOR_mqmulhu
, "__MQMULHU", FRV_BUILTIN_MQMULHU
, UNKNOWN
, 0},
8293 { CODE_FOR_mqmulxhs
, "__MQMULXHS", FRV_BUILTIN_MQMULXHS
, UNKNOWN
, 0},
8294 { CODE_FOR_mqmulxhu
, "__MQMULXHU", FRV_BUILTIN_MQMULXHU
, UNKNOWN
, 0},
8295 { CODE_FOR_mqmachs
, "__MQMACHS", FRV_BUILTIN_MQMACHS
, UNKNOWN
, 0},
8296 { CODE_FOR_mqmachu
, "__MQMACHU", FRV_BUILTIN_MQMACHU
, UNKNOWN
, 0},
8297 { CODE_FOR_mqxmachs
, "__MQXMACHS", FRV_BUILTIN_MQXMACHS
, UNKNOWN
, 0},
8298 { CODE_FOR_mqxmacxhs
, "__MQXMACXHS", FRV_BUILTIN_MQXMACXHS
, UNKNOWN
, 0},
8299 { CODE_FOR_mqmacxhs
, "__MQMACXHS", FRV_BUILTIN_MQMACXHS
, UNKNOWN
, 0}
8302 /* Media intrinsics that take two accumulator numbers as argument and
8305 static struct builtin_description bdesc_voidacc
[] =
8307 { CODE_FOR_maddaccs
, "__MADDACCS", FRV_BUILTIN_MADDACCS
, UNKNOWN
, 0},
8308 { CODE_FOR_msubaccs
, "__MSUBACCS", FRV_BUILTIN_MSUBACCS
, UNKNOWN
, 0},
8309 { CODE_FOR_masaccs
, "__MASACCS", FRV_BUILTIN_MASACCS
, UNKNOWN
, 0},
8310 { CODE_FOR_mdaddaccs
, "__MDADDACCS", FRV_BUILTIN_MDADDACCS
, UNKNOWN
, 0},
8311 { CODE_FOR_mdsubaccs
, "__MDSUBACCS", FRV_BUILTIN_MDSUBACCS
, UNKNOWN
, 0},
8312 { CODE_FOR_mdasaccs
, "__MDASACCS", FRV_BUILTIN_MDASACCS
, UNKNOWN
, 0}
8315 /* Intrinsics that load a value and then issue a MEMBAR. The load is
8316 a normal move and the ICODE is for the membar. */
8318 static struct builtin_description bdesc_loads
[] =
8320 { CODE_FOR_optional_membar_qi
, "__builtin_read8",
8321 FRV_BUILTIN_READ8
, UNKNOWN
, 0},
8322 { CODE_FOR_optional_membar_hi
, "__builtin_read16",
8323 FRV_BUILTIN_READ16
, UNKNOWN
, 0},
8324 { CODE_FOR_optional_membar_si
, "__builtin_read32",
8325 FRV_BUILTIN_READ32
, UNKNOWN
, 0},
8326 { CODE_FOR_optional_membar_di
, "__builtin_read64",
8327 FRV_BUILTIN_READ64
, UNKNOWN
, 0}
8330 /* Likewise stores. */
8332 static struct builtin_description bdesc_stores
[] =
8334 { CODE_FOR_optional_membar_qi
, "__builtin_write8",
8335 FRV_BUILTIN_WRITE8
, UNKNOWN
, 0},
8336 { CODE_FOR_optional_membar_hi
, "__builtin_write16",
8337 FRV_BUILTIN_WRITE16
, UNKNOWN
, 0},
8338 { CODE_FOR_optional_membar_si
, "__builtin_write32",
8339 FRV_BUILTIN_WRITE32
, UNKNOWN
, 0},
8340 { CODE_FOR_optional_membar_di
, "__builtin_write64",
8341 FRV_BUILTIN_WRITE64
, UNKNOWN
, 0},
8344 /* Initialize media builtins. */
8347 frv_init_builtins (void)
8349 tree accumulator
= integer_type_node
;
8350 tree integer
= integer_type_node
;
8351 tree voidt
= void_type_node
;
8352 tree uhalf
= short_unsigned_type_node
;
8353 tree sword1
= long_integer_type_node
;
8354 tree uword1
= long_unsigned_type_node
;
8355 tree sword2
= long_long_integer_type_node
;
8356 tree uword2
= long_long_unsigned_type_node
;
8357 tree uword4
= build_pointer_type (uword1
);
8358 tree vptr
= build_pointer_type (build_type_variant (void_type_node
, 0, 1));
8359 tree ubyte
= unsigned_char_type_node
;
8360 tree iacc
= integer_type_node
;
8362 #define UNARY(RET, T1) \
8363 build_function_type_list (RET, T1, NULL_TREE)
8365 #define BINARY(RET, T1, T2) \
8366 build_function_type_list (RET, T1, T2, NULL_TREE)
8368 #define TRINARY(RET, T1, T2, T3) \
8369 build_function_type_list (RET, T1, T2, T3, NULL_TREE)
8371 #define QUAD(RET, T1, T2, T3, T4) \
8372 build_function_type_list (RET, T1, T2, T3, T4, NULL_TREE)
8374 tree void_ftype_void
= build_function_type_list (voidt
, NULL_TREE
);
8376 tree void_ftype_acc
= UNARY (voidt
, accumulator
);
8377 tree void_ftype_uw4_uw1
= BINARY (voidt
, uword4
, uword1
);
8378 tree void_ftype_uw4_uw2
= BINARY (voidt
, uword4
, uword2
);
8379 tree void_ftype_acc_uw1
= BINARY (voidt
, accumulator
, uword1
);
8380 tree void_ftype_acc_acc
= BINARY (voidt
, accumulator
, accumulator
);
8381 tree void_ftype_acc_uw1_uw1
= TRINARY (voidt
, accumulator
, uword1
, uword1
);
8382 tree void_ftype_acc_sw1_sw1
= TRINARY (voidt
, accumulator
, sword1
, sword1
);
8383 tree void_ftype_acc_uw2_uw2
= TRINARY (voidt
, accumulator
, uword2
, uword2
);
8384 tree void_ftype_acc_sw2_sw2
= TRINARY (voidt
, accumulator
, sword2
, sword2
);
8386 tree uw1_ftype_uw1
= UNARY (uword1
, uword1
);
8387 tree uw1_ftype_sw1
= UNARY (uword1
, sword1
);
8388 tree uw1_ftype_uw2
= UNARY (uword1
, uword2
);
8389 tree uw1_ftype_acc
= UNARY (uword1
, accumulator
);
8390 tree uw1_ftype_uh_uh
= BINARY (uword1
, uhalf
, uhalf
);
8391 tree uw1_ftype_uw1_uw1
= BINARY (uword1
, uword1
, uword1
);
8392 tree uw1_ftype_uw1_int
= BINARY (uword1
, uword1
, integer
);
8393 tree uw1_ftype_acc_uw1
= BINARY (uword1
, accumulator
, uword1
);
8394 tree uw1_ftype_acc_sw1
= BINARY (uword1
, accumulator
, sword1
);
8395 tree uw1_ftype_uw2_uw1
= BINARY (uword1
, uword2
, uword1
);
8396 tree uw1_ftype_uw2_int
= BINARY (uword1
, uword2
, integer
);
8398 tree sw1_ftype_int
= UNARY (sword1
, integer
);
8399 tree sw1_ftype_sw1_sw1
= BINARY (sword1
, sword1
, sword1
);
8400 tree sw1_ftype_sw1_int
= BINARY (sword1
, sword1
, integer
);
8402 tree uw2_ftype_uw1
= UNARY (uword2
, uword1
);
8403 tree uw2_ftype_uw1_int
= BINARY (uword2
, uword1
, integer
);
8404 tree uw2_ftype_uw2_uw2
= BINARY (uword2
, uword2
, uword2
);
8405 tree uw2_ftype_uw2_int
= BINARY (uword2
, uword2
, integer
);
8406 tree uw2_ftype_acc_int
= BINARY (uword2
, accumulator
, integer
);
8407 tree uw2_ftype_uh_uh_uh_uh
= QUAD (uword2
, uhalf
, uhalf
, uhalf
, uhalf
);
8409 tree sw2_ftype_sw2_sw2
= BINARY (sword2
, sword2
, sword2
);
8410 tree sw2_ftype_sw2_int
= BINARY (sword2
, sword2
, integer
);
8411 tree uw2_ftype_uw1_uw1
= BINARY (uword2
, uword1
, uword1
);
8412 tree sw2_ftype_sw1_sw1
= BINARY (sword2
, sword1
, sword1
);
8413 tree void_ftype_sw1_sw1
= BINARY (voidt
, sword1
, sword1
);
8414 tree void_ftype_iacc_sw2
= BINARY (voidt
, iacc
, sword2
);
8415 tree void_ftype_iacc_sw1
= BINARY (voidt
, iacc
, sword1
);
8416 tree sw1_ftype_sw1
= UNARY (sword1
, sword1
);
8417 tree sw2_ftype_iacc
= UNARY (sword2
, iacc
);
8418 tree sw1_ftype_iacc
= UNARY (sword1
, iacc
);
8419 tree void_ftype_ptr
= UNARY (voidt
, const_ptr_type_node
);
8420 tree uw1_ftype_vptr
= UNARY (uword1
, vptr
);
8421 tree uw2_ftype_vptr
= UNARY (uword2
, vptr
);
8422 tree void_ftype_vptr_ub
= BINARY (voidt
, vptr
, ubyte
);
8423 tree void_ftype_vptr_uh
= BINARY (voidt
, vptr
, uhalf
);
8424 tree void_ftype_vptr_uw1
= BINARY (voidt
, vptr
, uword1
);
8425 tree void_ftype_vptr_uw2
= BINARY (voidt
, vptr
, uword2
);
8427 def_builtin ("__MAND", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAND
);
8428 def_builtin ("__MOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MOR
);
8429 def_builtin ("__MXOR", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MXOR
);
8430 def_builtin ("__MNOT", uw1_ftype_uw1
, FRV_BUILTIN_MNOT
);
8431 def_builtin ("__MROTLI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTLI
);
8432 def_builtin ("__MROTRI", uw1_ftype_uw1_int
, FRV_BUILTIN_MROTRI
);
8433 def_builtin ("__MWCUT", uw1_ftype_uw2_uw1
, FRV_BUILTIN_MWCUT
);
8434 def_builtin ("__MAVEH", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MAVEH
);
8435 def_builtin ("__MSLLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSLLHI
);
8436 def_builtin ("__MSRLHI", uw1_ftype_uw1_int
, FRV_BUILTIN_MSRLHI
);
8437 def_builtin ("__MSRAHI", sw1_ftype_sw1_int
, FRV_BUILTIN_MSRAHI
);
8438 def_builtin ("__MSATHS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSATHS
);
8439 def_builtin ("__MSATHU", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSATHU
);
8440 def_builtin ("__MADDHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MADDHSS
);
8441 def_builtin ("__MADDHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MADDHUS
);
8442 def_builtin ("__MSUBHSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_MSUBHSS
);
8443 def_builtin ("__MSUBHUS", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MSUBHUS
);
8444 def_builtin ("__MMULHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULHS
);
8445 def_builtin ("__MMULHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULHU
);
8446 def_builtin ("__MMULXHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMULXHS
);
8447 def_builtin ("__MMULXHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMULXHU
);
8448 def_builtin ("__MMACHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMACHS
);
8449 def_builtin ("__MMACHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMACHU
);
8450 def_builtin ("__MMRDHS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MMRDHS
);
8451 def_builtin ("__MMRDHU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MMRDHU
);
8452 def_builtin ("__MQADDHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQADDHSS
);
8453 def_builtin ("__MQADDHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQADDHUS
);
8454 def_builtin ("__MQSUBHSS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSUBHSS
);
8455 def_builtin ("__MQSUBHUS", uw2_ftype_uw2_uw2
, FRV_BUILTIN_MQSUBHUS
);
8456 def_builtin ("__MQMULHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULHS
);
8457 def_builtin ("__MQMULHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULHU
);
8458 def_builtin ("__MQMULXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMULXHS
);
8459 def_builtin ("__MQMULXHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMULXHU
);
8460 def_builtin ("__MQMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACHS
);
8461 def_builtin ("__MQMACHU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQMACHU
);
8462 def_builtin ("__MCPXRS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXRS
);
8463 def_builtin ("__MCPXRU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXRU
);
8464 def_builtin ("__MCPXIS", void_ftype_acc_sw1_sw1
, FRV_BUILTIN_MCPXIS
);
8465 def_builtin ("__MCPXIU", void_ftype_acc_uw1_uw1
, FRV_BUILTIN_MCPXIU
);
8466 def_builtin ("__MQCPXRS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXRS
);
8467 def_builtin ("__MQCPXRU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXRU
);
8468 def_builtin ("__MQCPXIS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQCPXIS
);
8469 def_builtin ("__MQCPXIU", void_ftype_acc_uw2_uw2
, FRV_BUILTIN_MQCPXIU
);
8470 def_builtin ("__MCUT", uw1_ftype_acc_uw1
, FRV_BUILTIN_MCUT
);
8471 def_builtin ("__MCUTSS", uw1_ftype_acc_sw1
, FRV_BUILTIN_MCUTSS
);
8472 def_builtin ("__MEXPDHW", uw1_ftype_uw1_int
, FRV_BUILTIN_MEXPDHW
);
8473 def_builtin ("__MEXPDHD", uw2_ftype_uw1_int
, FRV_BUILTIN_MEXPDHD
);
8474 def_builtin ("__MPACKH", uw1_ftype_uh_uh
, FRV_BUILTIN_MPACKH
);
8475 def_builtin ("__MUNPACKH", uw2_ftype_uw1
, FRV_BUILTIN_MUNPACKH
);
8476 def_builtin ("__MDPACKH", uw2_ftype_uh_uh_uh_uh
, FRV_BUILTIN_MDPACKH
);
8477 def_builtin ("__MDUNPACKH", void_ftype_uw4_uw2
, FRV_BUILTIN_MDUNPACKH
);
8478 def_builtin ("__MBTOH", uw2_ftype_uw1
, FRV_BUILTIN_MBTOH
);
8479 def_builtin ("__MHTOB", uw1_ftype_uw2
, FRV_BUILTIN_MHTOB
);
8480 def_builtin ("__MBTOHE", void_ftype_uw4_uw1
, FRV_BUILTIN_MBTOHE
);
8481 def_builtin ("__MCLRACC", void_ftype_acc
, FRV_BUILTIN_MCLRACC
);
8482 def_builtin ("__MCLRACCA", void_ftype_void
, FRV_BUILTIN_MCLRACCA
);
8483 def_builtin ("__MRDACC", uw1_ftype_acc
, FRV_BUILTIN_MRDACC
);
8484 def_builtin ("__MRDACCG", uw1_ftype_acc
, FRV_BUILTIN_MRDACCG
);
8485 def_builtin ("__MWTACC", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACC
);
8486 def_builtin ("__MWTACCG", void_ftype_acc_uw1
, FRV_BUILTIN_MWTACCG
);
8487 def_builtin ("__Mcop1", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP1
);
8488 def_builtin ("__Mcop2", uw1_ftype_uw1_uw1
, FRV_BUILTIN_MCOP2
);
8489 def_builtin ("__MTRAP", void_ftype_void
, FRV_BUILTIN_MTRAP
);
8490 def_builtin ("__MQXMACHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACHS
);
8491 def_builtin ("__MQXMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQXMACXHS
);
8492 def_builtin ("__MQMACXHS", void_ftype_acc_sw2_sw2
, FRV_BUILTIN_MQMACXHS
);
8493 def_builtin ("__MADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MADDACCS
);
8494 def_builtin ("__MSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MSUBACCS
);
8495 def_builtin ("__MASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MASACCS
);
8496 def_builtin ("__MDADDACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDADDACCS
);
8497 def_builtin ("__MDSUBACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDSUBACCS
);
8498 def_builtin ("__MDASACCS", void_ftype_acc_acc
, FRV_BUILTIN_MDASACCS
);
8499 def_builtin ("__MABSHS", uw1_ftype_sw1
, FRV_BUILTIN_MABSHS
);
8500 def_builtin ("__MDROTLI", uw2_ftype_uw2_int
, FRV_BUILTIN_MDROTLI
);
8501 def_builtin ("__MCPLHI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLHI
);
8502 def_builtin ("__MCPLI", uw1_ftype_uw2_int
, FRV_BUILTIN_MCPLI
);
8503 def_builtin ("__MDCUTSSI", uw2_ftype_acc_int
, FRV_BUILTIN_MDCUTSSI
);
8504 def_builtin ("__MQSATHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQSATHS
);
8505 def_builtin ("__MHSETLOS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETLOS
);
8506 def_builtin ("__MHSETHIS", sw1_ftype_sw1_int
, FRV_BUILTIN_MHSETHIS
);
8507 def_builtin ("__MHDSETS", sw1_ftype_int
, FRV_BUILTIN_MHDSETS
);
8508 def_builtin ("__MHSETLOH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETLOH
);
8509 def_builtin ("__MHSETHIH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHSETHIH
);
8510 def_builtin ("__MHDSETH", uw1_ftype_uw1_int
, FRV_BUILTIN_MHDSETH
);
8511 def_builtin ("__MQLCLRHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQLCLRHS
);
8512 def_builtin ("__MQLMTHS", sw2_ftype_sw2_sw2
, FRV_BUILTIN_MQLMTHS
);
8513 def_builtin ("__MQSLLHI", uw2_ftype_uw2_int
, FRV_BUILTIN_MQSLLHI
);
8514 def_builtin ("__MQSRAHI", sw2_ftype_sw2_int
, FRV_BUILTIN_MQSRAHI
);
8515 def_builtin ("__SMUL", sw2_ftype_sw1_sw1
, FRV_BUILTIN_SMUL
);
8516 def_builtin ("__UMUL", uw2_ftype_uw1_uw1
, FRV_BUILTIN_UMUL
);
8517 def_builtin ("__SMASS", void_ftype_sw1_sw1
, FRV_BUILTIN_SMASS
);
8518 def_builtin ("__SMSSS", void_ftype_sw1_sw1
, FRV_BUILTIN_SMSSS
);
8519 def_builtin ("__SMU", void_ftype_sw1_sw1
, FRV_BUILTIN_SMU
);
8520 def_builtin ("__ADDSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_ADDSS
);
8521 def_builtin ("__SUBSS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SUBSS
);
8522 def_builtin ("__SLASS", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SLASS
);
8523 def_builtin ("__SCAN", sw1_ftype_sw1_sw1
, FRV_BUILTIN_SCAN
);
8524 def_builtin ("__SCUTSS", sw1_ftype_sw1
, FRV_BUILTIN_SCUTSS
);
8525 def_builtin ("__IACCreadll", sw2_ftype_iacc
, FRV_BUILTIN_IACCreadll
);
8526 def_builtin ("__IACCreadl", sw1_ftype_iacc
, FRV_BUILTIN_IACCreadl
);
8527 def_builtin ("__IACCsetll", void_ftype_iacc_sw2
, FRV_BUILTIN_IACCsetll
);
8528 def_builtin ("__IACCsetl", void_ftype_iacc_sw1
, FRV_BUILTIN_IACCsetl
);
8529 def_builtin ("__data_prefetch0", void_ftype_ptr
, FRV_BUILTIN_PREFETCH0
);
8530 def_builtin ("__data_prefetch", void_ftype_ptr
, FRV_BUILTIN_PREFETCH
);
8531 def_builtin ("__builtin_read8", uw1_ftype_vptr
, FRV_BUILTIN_READ8
);
8532 def_builtin ("__builtin_read16", uw1_ftype_vptr
, FRV_BUILTIN_READ16
);
8533 def_builtin ("__builtin_read32", uw1_ftype_vptr
, FRV_BUILTIN_READ32
);
8534 def_builtin ("__builtin_read64", uw2_ftype_vptr
, FRV_BUILTIN_READ64
);
8536 def_builtin ("__builtin_write8", void_ftype_vptr_ub
, FRV_BUILTIN_WRITE8
);
8537 def_builtin ("__builtin_write16", void_ftype_vptr_uh
, FRV_BUILTIN_WRITE16
);
8538 def_builtin ("__builtin_write32", void_ftype_vptr_uw1
, FRV_BUILTIN_WRITE32
);
8539 def_builtin ("__builtin_write64", void_ftype_vptr_uw2
, FRV_BUILTIN_WRITE64
);
8547 /* Set the names for various arithmetic operations according to the
8550 frv_init_libfuncs (void)
8552 set_optab_libfunc (smod_optab
, SImode
, "__modi");
8553 set_optab_libfunc (umod_optab
, SImode
, "__umodi");
8555 set_optab_libfunc (add_optab
, DImode
, "__addll");
8556 set_optab_libfunc (sub_optab
, DImode
, "__subll");
8557 set_optab_libfunc (smul_optab
, DImode
, "__mulll");
8558 set_optab_libfunc (sdiv_optab
, DImode
, "__divll");
8559 set_optab_libfunc (smod_optab
, DImode
, "__modll");
8560 set_optab_libfunc (umod_optab
, DImode
, "__umodll");
8561 set_optab_libfunc (and_optab
, DImode
, "__andll");
8562 set_optab_libfunc (ior_optab
, DImode
, "__orll");
8563 set_optab_libfunc (xor_optab
, DImode
, "__xorll");
8564 set_optab_libfunc (one_cmpl_optab
, DImode
, "__notll");
8566 set_optab_libfunc (add_optab
, SFmode
, "__addf");
8567 set_optab_libfunc (sub_optab
, SFmode
, "__subf");
8568 set_optab_libfunc (smul_optab
, SFmode
, "__mulf");
8569 set_optab_libfunc (sdiv_optab
, SFmode
, "__divf");
8571 set_optab_libfunc (add_optab
, DFmode
, "__addd");
8572 set_optab_libfunc (sub_optab
, DFmode
, "__subd");
8573 set_optab_libfunc (smul_optab
, DFmode
, "__muld");
8574 set_optab_libfunc (sdiv_optab
, DFmode
, "__divd");
8576 set_conv_libfunc (sext_optab
, DFmode
, SFmode
, "__ftod");
8577 set_conv_libfunc (trunc_optab
, SFmode
, DFmode
, "__dtof");
8579 set_conv_libfunc (sfix_optab
, SImode
, SFmode
, "__ftoi");
8580 set_conv_libfunc (sfix_optab
, DImode
, SFmode
, "__ftoll");
8581 set_conv_libfunc (sfix_optab
, SImode
, DFmode
, "__dtoi");
8582 set_conv_libfunc (sfix_optab
, DImode
, DFmode
, "__dtoll");
8584 set_conv_libfunc (ufix_optab
, SImode
, SFmode
, "__ftoui");
8585 set_conv_libfunc (ufix_optab
, DImode
, SFmode
, "__ftoull");
8586 set_conv_libfunc (ufix_optab
, SImode
, DFmode
, "__dtoui");
8587 set_conv_libfunc (ufix_optab
, DImode
, DFmode
, "__dtoull");
8589 set_conv_libfunc (sfloat_optab
, SFmode
, SImode
, "__itof");
8590 set_conv_libfunc (sfloat_optab
, SFmode
, DImode
, "__lltof");
8591 set_conv_libfunc (sfloat_optab
, DFmode
, SImode
, "__itod");
8592 set_conv_libfunc (sfloat_optab
, DFmode
, DImode
, "__lltod");
8595 /* Convert an integer constant to an accumulator register. ICODE is the
8596 code of the target instruction, OPNUM is the number of the
8597 accumulator operand and OPVAL is the constant integer. Try both
8598 ACC and ACCG registers; only report an error if neither fit the
8602 frv_int_to_acc (enum insn_code icode
, int opnum
, rtx opval
)
8607 /* ACCs and ACCGs are implicit global registers if media intrinsics
8608 are being used. We set up this lazily to avoid creating lots of
8609 unnecessary call_insn rtl in non-media code. */
8610 for (i
= 0; i
<= ACC_MASK
; i
++)
8611 if ((i
& ACC_MASK
) == i
)
8612 global_regs
[i
+ ACC_FIRST
] = global_regs
[i
+ ACCG_FIRST
] = 1;
8614 if (GET_CODE (opval
) != CONST_INT
)
8616 error ("accumulator is not a constant integer");
8619 if ((INTVAL (opval
) & ~ACC_MASK
) != 0)
8621 error ("accumulator number is out of bounds");
8625 reg
= gen_rtx_REG (insn_data
[icode
].operand
[opnum
].mode
,
8626 ACC_FIRST
+ INTVAL (opval
));
8627 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
8628 SET_REGNO (reg
, ACCG_FIRST
+ INTVAL (opval
));
8630 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (reg
, VOIDmode
))
8632 error ("inappropriate accumulator for %qs", insn_data
[icode
].name
);
8638 /* If an ACC rtx has mode MODE, return the mode that the matching ACCG
8642 frv_matching_accg_mode (machine_mode mode
)
8660 /* Given that a __builtin_read or __builtin_write function is accessing
8661 address ADDRESS, return the value that should be used as operand 1
8665 frv_io_address_cookie (rtx address
)
8667 return (GET_CODE (address
) == CONST_INT
8668 ? GEN_INT (INTVAL (address
) / 8 * 8)
8672 /* Return the accumulator guard that should be paired with accumulator
8673 register ACC. The mode of the returned register is in the same
8674 class as ACC, but is four times smaller. */
8677 frv_matching_accg_for_acc (rtx acc
)
8679 return gen_rtx_REG (frv_matching_accg_mode (GET_MODE (acc
)),
8680 REGNO (acc
) - ACC_FIRST
+ ACCG_FIRST
);
8683 /* Read the requested argument from the call EXP given by INDEX.
8684 Return the value as an rtx. */
8687 frv_read_argument (tree exp
, unsigned int index
)
8689 return expand_normal (CALL_EXPR_ARG (exp
, index
));
8692 /* Like frv_read_argument, but interpret the argument as the number
8693 of an IACC register and return a (reg:MODE ...) rtx for it. */
8696 frv_read_iacc_argument (machine_mode mode
, tree call
,
8702 op
= frv_read_argument (call
, index
);
8703 if (GET_CODE (op
) != CONST_INT
8705 || INTVAL (op
) > IACC_LAST
- IACC_FIRST
8706 || ((INTVAL (op
) * 4) & (GET_MODE_SIZE (mode
) - 1)) != 0)
8708 error ("invalid IACC argument");
8712 /* IACCs are implicit global registers. We set up this lazily to
8713 avoid creating lots of unnecessary call_insn rtl when IACCs aren't
8715 regno
= INTVAL (op
) + IACC_FIRST
;
8716 for (i
= 0; i
< HARD_REGNO_NREGS (regno
, mode
); i
++)
8717 global_regs
[regno
+ i
] = 1;
8719 return gen_rtx_REG (mode
, regno
);
8722 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE.
8723 The instruction should require a constant operand of some sort. The
8724 function prints an error if OPVAL is not valid. */
8727 frv_check_constant_argument (enum insn_code icode
, int opnum
, rtx opval
)
8729 if (GET_CODE (opval
) != CONST_INT
)
8731 error ("%qs expects a constant argument", insn_data
[icode
].name
);
8734 if (! (*insn_data
[icode
].operand
[opnum
].predicate
) (opval
, VOIDmode
))
8736 error ("constant argument out of range for %qs", insn_data
[icode
].name
);
8742 /* Return a legitimate rtx for instruction ICODE's return value. Use TARGET
8743 if it's not null, has the right mode, and satisfies operand 0's
8747 frv_legitimize_target (enum insn_code icode
, rtx target
)
8749 machine_mode mode
= insn_data
[icode
].operand
[0].mode
;
8752 || GET_MODE (target
) != mode
8753 || ! (*insn_data
[icode
].operand
[0].predicate
) (target
, mode
))
8754 return gen_reg_rtx (mode
);
8759 /* Given that ARG is being passed as operand OPNUM to instruction ICODE,
8760 check whether ARG satisfies the operand's constraints. If it doesn't,
8761 copy ARG to a temporary register and return that. Otherwise return ARG
8765 frv_legitimize_argument (enum insn_code icode
, int opnum
, rtx arg
)
8767 machine_mode mode
= insn_data
[icode
].operand
[opnum
].mode
;
8769 if ((*insn_data
[icode
].operand
[opnum
].predicate
) (arg
, mode
))
8772 return copy_to_mode_reg (mode
, arg
);
8775 /* Return a volatile memory reference of mode MODE whose address is ARG. */
8778 frv_volatile_memref (machine_mode mode
, rtx arg
)
8782 mem
= gen_rtx_MEM (mode
, memory_address (mode
, arg
));
8783 MEM_VOLATILE_P (mem
) = 1;
8787 /* Expand builtins that take a single, constant argument. At the moment,
8788 only MHDSETS falls into this category. */
8791 frv_expand_set_builtin (enum insn_code icode
, tree call
, rtx target
)
8794 rtx op0
= frv_read_argument (call
, 0);
8796 if (! frv_check_constant_argument (icode
, 1, op0
))
8799 target
= frv_legitimize_target (icode
, target
);
8800 pat
= GEN_FCN (icode
) (target
, op0
);
8808 /* Expand builtins that take one operand. */
8811 frv_expand_unop_builtin (enum insn_code icode
, tree call
, rtx target
)
8814 rtx op0
= frv_read_argument (call
, 0);
8816 target
= frv_legitimize_target (icode
, target
);
8817 op0
= frv_legitimize_argument (icode
, 1, op0
);
8818 pat
= GEN_FCN (icode
) (target
, op0
);
8826 /* Expand builtins that take two operands. */
8829 frv_expand_binop_builtin (enum insn_code icode
, tree call
, rtx target
)
8832 rtx op0
= frv_read_argument (call
, 0);
8833 rtx op1
= frv_read_argument (call
, 1);
8835 target
= frv_legitimize_target (icode
, target
);
8836 op0
= frv_legitimize_argument (icode
, 1, op0
);
8837 op1
= frv_legitimize_argument (icode
, 2, op1
);
8838 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
8846 /* Expand cut-style builtins, which take two operands and an implicit ACCG
8850 frv_expand_cut_builtin (enum insn_code icode
, tree call
, rtx target
)
8853 rtx op0
= frv_read_argument (call
, 0);
8854 rtx op1
= frv_read_argument (call
, 1);
8857 target
= frv_legitimize_target (icode
, target
);
8858 op0
= frv_int_to_acc (icode
, 1, op0
);
8862 if (icode
== CODE_FOR_mdcutssi
|| GET_CODE (op1
) == CONST_INT
)
8864 if (! frv_check_constant_argument (icode
, 2, op1
))
8868 op1
= frv_legitimize_argument (icode
, 2, op1
);
8870 op2
= frv_matching_accg_for_acc (op0
);
8871 pat
= GEN_FCN (icode
) (target
, op0
, op1
, op2
);
8879 /* Expand builtins that take two operands and the second is immediate. */
8882 frv_expand_binopimm_builtin (enum insn_code icode
, tree call
, rtx target
)
8885 rtx op0
= frv_read_argument (call
, 0);
8886 rtx op1
= frv_read_argument (call
, 1);
8888 if (! frv_check_constant_argument (icode
, 2, op1
))
8891 target
= frv_legitimize_target (icode
, target
);
8892 op0
= frv_legitimize_argument (icode
, 1, op0
);
8893 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
8901 /* Expand builtins that take two operands, the first operand being a pointer to
8902 ints and return void. */
8905 frv_expand_voidbinop_builtin (enum insn_code icode
, tree call
)
8908 rtx op0
= frv_read_argument (call
, 0);
8909 rtx op1
= frv_read_argument (call
, 1);
8910 machine_mode mode0
= insn_data
[icode
].operand
[0].mode
;
8913 if (GET_CODE (op0
) != MEM
)
8917 if (! offsettable_address_p (0, mode0
, op0
))
8919 reg
= gen_reg_rtx (Pmode
);
8920 emit_insn (gen_rtx_SET (reg
, op0
));
8923 op0
= gen_rtx_MEM (SImode
, reg
);
8926 addr
= XEXP (op0
, 0);
8927 if (! offsettable_address_p (0, mode0
, addr
))
8928 addr
= copy_to_mode_reg (Pmode
, op0
);
8930 op0
= change_address (op0
, V4SImode
, addr
);
8931 op1
= frv_legitimize_argument (icode
, 1, op1
);
8932 pat
= GEN_FCN (icode
) (op0
, op1
);
8940 /* Expand builtins that take two long operands and return void. */
8943 frv_expand_int_void2arg (enum insn_code icode
, tree call
)
8946 rtx op0
= frv_read_argument (call
, 0);
8947 rtx op1
= frv_read_argument (call
, 1);
8949 op0
= frv_legitimize_argument (icode
, 1, op0
);
8950 op1
= frv_legitimize_argument (icode
, 1, op1
);
8951 pat
= GEN_FCN (icode
) (op0
, op1
);
8959 /* Expand prefetch builtins. These take a single address as argument. */
8962 frv_expand_prefetches (enum insn_code icode
, tree call
)
8965 rtx op0
= frv_read_argument (call
, 0);
8967 pat
= GEN_FCN (icode
) (force_reg (Pmode
, op0
));
8975 /* Expand builtins that take three operands and return void. The first
8976 argument must be a constant that describes a pair or quad accumulators. A
8977 fourth argument is created that is the accumulator guard register that
8978 corresponds to the accumulator. */
8981 frv_expand_voidtriop_builtin (enum insn_code icode
, tree call
)
8984 rtx op0
= frv_read_argument (call
, 0);
8985 rtx op1
= frv_read_argument (call
, 1);
8986 rtx op2
= frv_read_argument (call
, 2);
8989 op0
= frv_int_to_acc (icode
, 0, op0
);
8993 op1
= frv_legitimize_argument (icode
, 1, op1
);
8994 op2
= frv_legitimize_argument (icode
, 2, op2
);
8995 op3
= frv_matching_accg_for_acc (op0
);
8996 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
9004 /* Expand builtins that perform accumulator-to-accumulator operations.
9005 These builtins take two accumulator numbers as argument and return
9009 frv_expand_voidaccop_builtin (enum insn_code icode
, tree call
)
9012 rtx op0
= frv_read_argument (call
, 0);
9013 rtx op1
= frv_read_argument (call
, 1);
9017 op0
= frv_int_to_acc (icode
, 0, op0
);
9021 op1
= frv_int_to_acc (icode
, 1, op1
);
9025 op2
= frv_matching_accg_for_acc (op0
);
9026 op3
= frv_matching_accg_for_acc (op1
);
9027 pat
= GEN_FCN (icode
) (op0
, op1
, op2
, op3
);
9035 /* Expand a __builtin_read* function. ICODE is the instruction code for the
9036 membar and TARGET_MODE is the mode that the loaded value should have. */
9039 frv_expand_load_builtin (enum insn_code icode
, machine_mode target_mode
,
9040 tree call
, rtx target
)
9042 rtx op0
= frv_read_argument (call
, 0);
9043 rtx cookie
= frv_io_address_cookie (op0
);
9045 if (target
== 0 || !REG_P (target
))
9046 target
= gen_reg_rtx (target_mode
);
9047 op0
= frv_volatile_memref (insn_data
[icode
].operand
[0].mode
, op0
);
9048 convert_move (target
, op0
, 1);
9049 emit_insn (GEN_FCN (icode
) (copy_rtx (op0
), cookie
, GEN_INT (FRV_IO_READ
)));
9050 cfun
->machine
->has_membar_p
= 1;
9054 /* Likewise __builtin_write* functions. */
9057 frv_expand_store_builtin (enum insn_code icode
, tree call
)
9059 rtx op0
= frv_read_argument (call
, 0);
9060 rtx op1
= frv_read_argument (call
, 1);
9061 rtx cookie
= frv_io_address_cookie (op0
);
9063 op0
= frv_volatile_memref (insn_data
[icode
].operand
[0].mode
, op0
);
9064 convert_move (op0
, force_reg (insn_data
[icode
].operand
[0].mode
, op1
), 1);
9065 emit_insn (GEN_FCN (icode
) (copy_rtx (op0
), cookie
, GEN_INT (FRV_IO_WRITE
)));
9066 cfun
->machine
->has_membar_p
= 1;
9070 /* Expand the MDPACKH builtin. It takes four unsigned short arguments and
9071 each argument forms one word of the two double-word input registers.
9072 CALL is the tree for the call and TARGET, if nonnull, suggests a good place
9073 to put the return value. */
9076 frv_expand_mdpackh_builtin (tree call
, rtx target
)
9078 enum insn_code icode
= CODE_FOR_mdpackh
;
9080 rtx arg1
= frv_read_argument (call
, 0);
9081 rtx arg2
= frv_read_argument (call
, 1);
9082 rtx arg3
= frv_read_argument (call
, 2);
9083 rtx arg4
= frv_read_argument (call
, 3);
9085 target
= frv_legitimize_target (icode
, target
);
9086 op0
= gen_reg_rtx (DImode
);
9087 op1
= gen_reg_rtx (DImode
);
9089 /* The high half of each word is not explicitly initialized, so indicate
9090 that the input operands are not live before this point. */
9094 /* Move each argument into the low half of its associated input word. */
9095 emit_move_insn (simplify_gen_subreg (HImode
, op0
, DImode
, 2), arg1
);
9096 emit_move_insn (simplify_gen_subreg (HImode
, op0
, DImode
, 6), arg2
);
9097 emit_move_insn (simplify_gen_subreg (HImode
, op1
, DImode
, 2), arg3
);
9098 emit_move_insn (simplify_gen_subreg (HImode
, op1
, DImode
, 6), arg4
);
9100 pat
= GEN_FCN (icode
) (target
, op0
, op1
);
9108 /* Expand the MCLRACC builtin. This builtin takes a single accumulator
9109 number as argument. */
9112 frv_expand_mclracc_builtin (tree call
)
9114 enum insn_code icode
= CODE_FOR_mclracc
;
9116 rtx op0
= frv_read_argument (call
, 0);
9118 op0
= frv_int_to_acc (icode
, 0, op0
);
9122 pat
= GEN_FCN (icode
) (op0
);
9129 /* Expand builtins that take no arguments. */
9132 frv_expand_noargs_builtin (enum insn_code icode
)
9134 rtx pat
= GEN_FCN (icode
) (const0_rtx
);
9141 /* Expand MRDACC and MRDACCG. These builtins take a single accumulator
9142 number or accumulator guard number as argument and return an SI integer. */
9145 frv_expand_mrdacc_builtin (enum insn_code icode
, tree call
)
9148 rtx target
= gen_reg_rtx (SImode
);
9149 rtx op0
= frv_read_argument (call
, 0);
9151 op0
= frv_int_to_acc (icode
, 1, op0
);
9155 pat
= GEN_FCN (icode
) (target
, op0
);
9163 /* Expand MWTACC and MWTACCG. These builtins take an accumulator or
9164 accumulator guard as their first argument and an SImode value as their
9168 frv_expand_mwtacc_builtin (enum insn_code icode
, tree call
)
9171 rtx op0
= frv_read_argument (call
, 0);
9172 rtx op1
= frv_read_argument (call
, 1);
9174 op0
= frv_int_to_acc (icode
, 0, op0
);
9178 op1
= frv_legitimize_argument (icode
, 1, op1
);
9179 pat
= GEN_FCN (icode
) (op0
, op1
);
9186 /* Emit a move from SRC to DEST in SImode chunks. This can be used
9187 to move DImode values into and out of IACC0. */
9190 frv_split_iacc_move (rtx dest
, rtx src
)
9195 inner
= GET_MODE (dest
);
9196 for (i
= 0; i
< GET_MODE_SIZE (inner
); i
+= GET_MODE_SIZE (SImode
))
9197 emit_move_insn (simplify_gen_subreg (SImode
, dest
, inner
, i
),
9198 simplify_gen_subreg (SImode
, src
, inner
, i
));
9201 /* Expand builtins. */
9204 frv_expand_builtin (tree exp
,
9206 rtx subtarget ATTRIBUTE_UNUSED
,
9207 machine_mode mode ATTRIBUTE_UNUSED
,
9208 int ignore ATTRIBUTE_UNUSED
)
9210 tree fndecl
= TREE_OPERAND (CALL_EXPR_FN (exp
), 0);
9211 unsigned fcode
= (unsigned)DECL_FUNCTION_CODE (fndecl
);
9213 struct builtin_description
*d
;
9215 if (fcode
< FRV_BUILTIN_FIRST_NONMEDIA
&& !TARGET_MEDIA
)
9217 error ("media functions are not available unless -mmedia is used");
9223 case FRV_BUILTIN_MCOP1
:
9224 case FRV_BUILTIN_MCOP2
:
9225 case FRV_BUILTIN_MDUNPACKH
:
9226 case FRV_BUILTIN_MBTOHE
:
9227 if (! TARGET_MEDIA_REV1
)
9229 error ("this media function is only available on the fr500");
9234 case FRV_BUILTIN_MQXMACHS
:
9235 case FRV_BUILTIN_MQXMACXHS
:
9236 case FRV_BUILTIN_MQMACXHS
:
9237 case FRV_BUILTIN_MADDACCS
:
9238 case FRV_BUILTIN_MSUBACCS
:
9239 case FRV_BUILTIN_MASACCS
:
9240 case FRV_BUILTIN_MDADDACCS
:
9241 case FRV_BUILTIN_MDSUBACCS
:
9242 case FRV_BUILTIN_MDASACCS
:
9243 case FRV_BUILTIN_MABSHS
:
9244 case FRV_BUILTIN_MDROTLI
:
9245 case FRV_BUILTIN_MCPLHI
:
9246 case FRV_BUILTIN_MCPLI
:
9247 case FRV_BUILTIN_MDCUTSSI
:
9248 case FRV_BUILTIN_MQSATHS
:
9249 case FRV_BUILTIN_MHSETLOS
:
9250 case FRV_BUILTIN_MHSETLOH
:
9251 case FRV_BUILTIN_MHSETHIS
:
9252 case FRV_BUILTIN_MHSETHIH
:
9253 case FRV_BUILTIN_MHDSETS
:
9254 case FRV_BUILTIN_MHDSETH
:
9255 if (! TARGET_MEDIA_REV2
)
9257 error ("this media function is only available on the fr400"
9263 case FRV_BUILTIN_SMASS
:
9264 case FRV_BUILTIN_SMSSS
:
9265 case FRV_BUILTIN_SMU
:
9266 case FRV_BUILTIN_ADDSS
:
9267 case FRV_BUILTIN_SUBSS
:
9268 case FRV_BUILTIN_SLASS
:
9269 case FRV_BUILTIN_SCUTSS
:
9270 case FRV_BUILTIN_IACCreadll
:
9271 case FRV_BUILTIN_IACCreadl
:
9272 case FRV_BUILTIN_IACCsetll
:
9273 case FRV_BUILTIN_IACCsetl
:
9274 if (!TARGET_FR405_BUILTINS
)
9276 error ("this builtin function is only available"
9277 " on the fr405 and fr450");
9282 case FRV_BUILTIN_PREFETCH
:
9283 if (!TARGET_FR500_FR550_BUILTINS
)
9285 error ("this builtin function is only available on the fr500"
9291 case FRV_BUILTIN_MQLCLRHS
:
9292 case FRV_BUILTIN_MQLMTHS
:
9293 case FRV_BUILTIN_MQSLLHI
:
9294 case FRV_BUILTIN_MQSRAHI
:
9295 if (!TARGET_MEDIA_FR450
)
9297 error ("this builtin function is only available on the fr450");
9306 /* Expand unique builtins. */
9310 case FRV_BUILTIN_MTRAP
:
9311 return frv_expand_noargs_builtin (CODE_FOR_mtrap
);
9313 case FRV_BUILTIN_MCLRACC
:
9314 return frv_expand_mclracc_builtin (exp
);
9316 case FRV_BUILTIN_MCLRACCA
:
9318 return frv_expand_noargs_builtin (CODE_FOR_mclracca8
);
9320 return frv_expand_noargs_builtin (CODE_FOR_mclracca4
);
9322 case FRV_BUILTIN_MRDACC
:
9323 return frv_expand_mrdacc_builtin (CODE_FOR_mrdacc
, exp
);
9325 case FRV_BUILTIN_MRDACCG
:
9326 return frv_expand_mrdacc_builtin (CODE_FOR_mrdaccg
, exp
);
9328 case FRV_BUILTIN_MWTACC
:
9329 return frv_expand_mwtacc_builtin (CODE_FOR_mwtacc
, exp
);
9331 case FRV_BUILTIN_MWTACCG
:
9332 return frv_expand_mwtacc_builtin (CODE_FOR_mwtaccg
, exp
);
9334 case FRV_BUILTIN_MDPACKH
:
9335 return frv_expand_mdpackh_builtin (exp
, target
);
9337 case FRV_BUILTIN_IACCreadll
:
9339 rtx src
= frv_read_iacc_argument (DImode
, exp
, 0);
9340 if (target
== 0 || !REG_P (target
))
9341 target
= gen_reg_rtx (DImode
);
9342 frv_split_iacc_move (target
, src
);
9346 case FRV_BUILTIN_IACCreadl
:
9347 return frv_read_iacc_argument (SImode
, exp
, 0);
9349 case FRV_BUILTIN_IACCsetll
:
9351 rtx dest
= frv_read_iacc_argument (DImode
, exp
, 0);
9352 rtx src
= frv_read_argument (exp
, 1);
9353 frv_split_iacc_move (dest
, force_reg (DImode
, src
));
9357 case FRV_BUILTIN_IACCsetl
:
9359 rtx dest
= frv_read_iacc_argument (SImode
, exp
, 0);
9360 rtx src
= frv_read_argument (exp
, 1);
9361 emit_move_insn (dest
, force_reg (SImode
, src
));
9369 /* Expand groups of builtins. */
9371 for (i
= 0, d
= bdesc_set
; i
< ARRAY_SIZE (bdesc_set
); i
++, d
++)
9372 if (d
->code
== fcode
)
9373 return frv_expand_set_builtin (d
->icode
, exp
, target
);
9375 for (i
= 0, d
= bdesc_1arg
; i
< ARRAY_SIZE (bdesc_1arg
); i
++, d
++)
9376 if (d
->code
== fcode
)
9377 return frv_expand_unop_builtin (d
->icode
, exp
, target
);
9379 for (i
= 0, d
= bdesc_2arg
; i
< ARRAY_SIZE (bdesc_2arg
); i
++, d
++)
9380 if (d
->code
== fcode
)
9381 return frv_expand_binop_builtin (d
->icode
, exp
, target
);
9383 for (i
= 0, d
= bdesc_cut
; i
< ARRAY_SIZE (bdesc_cut
); i
++, d
++)
9384 if (d
->code
== fcode
)
9385 return frv_expand_cut_builtin (d
->icode
, exp
, target
);
9387 for (i
= 0, d
= bdesc_2argimm
; i
< ARRAY_SIZE (bdesc_2argimm
); i
++, d
++)
9388 if (d
->code
== fcode
)
9389 return frv_expand_binopimm_builtin (d
->icode
, exp
, target
);
9391 for (i
= 0, d
= bdesc_void2arg
; i
< ARRAY_SIZE (bdesc_void2arg
); i
++, d
++)
9392 if (d
->code
== fcode
)
9393 return frv_expand_voidbinop_builtin (d
->icode
, exp
);
9395 for (i
= 0, d
= bdesc_void3arg
; i
< ARRAY_SIZE (bdesc_void3arg
); i
++, d
++)
9396 if (d
->code
== fcode
)
9397 return frv_expand_voidtriop_builtin (d
->icode
, exp
);
9399 for (i
= 0, d
= bdesc_voidacc
; i
< ARRAY_SIZE (bdesc_voidacc
); i
++, d
++)
9400 if (d
->code
== fcode
)
9401 return frv_expand_voidaccop_builtin (d
->icode
, exp
);
9403 for (i
= 0, d
= bdesc_int_void2arg
;
9404 i
< ARRAY_SIZE (bdesc_int_void2arg
); i
++, d
++)
9405 if (d
->code
== fcode
)
9406 return frv_expand_int_void2arg (d
->icode
, exp
);
9408 for (i
= 0, d
= bdesc_prefetches
;
9409 i
< ARRAY_SIZE (bdesc_prefetches
); i
++, d
++)
9410 if (d
->code
== fcode
)
9411 return frv_expand_prefetches (d
->icode
, exp
);
9413 for (i
= 0, d
= bdesc_loads
; i
< ARRAY_SIZE (bdesc_loads
); i
++, d
++)
9414 if (d
->code
== fcode
)
9415 return frv_expand_load_builtin (d
->icode
, TYPE_MODE (TREE_TYPE (exp
)),
9418 for (i
= 0, d
= bdesc_stores
; i
< ARRAY_SIZE (bdesc_stores
); i
++, d
++)
9419 if (d
->code
== fcode
)
9420 return frv_expand_store_builtin (d
->icode
, exp
);
9426 frv_in_small_data_p (const_tree decl
)
9429 const char *section_name
;
9431 /* Don't apply the -G flag to internal compiler structures. We
9432 should leave such structures in the main data section, partly
9433 for efficiency and partly because the size of some of them
9434 (such as C++ typeinfos) is not known until later. */
9435 if (TREE_CODE (decl
) != VAR_DECL
|| DECL_ARTIFICIAL (decl
))
9438 /* If we already know which section the decl should be in, see if
9439 it's a small data section. */
9440 section_name
= DECL_SECTION_NAME (decl
);
9443 if (frv_string_begins_with (section_name
, ".sdata"))
9445 if (frv_string_begins_with (section_name
, ".sbss"))
9450 size
= int_size_in_bytes (TREE_TYPE (decl
));
9451 if (size
> 0 && size
<= g_switch_value
)
9458 frv_rtx_costs (rtx x
,
9459 int code ATTRIBUTE_UNUSED
,
9460 int outer_code ATTRIBUTE_UNUSED
,
9461 int opno ATTRIBUTE_UNUSED
,
9463 bool speed ATTRIBUTE_UNUSED
)
9465 if (outer_code
== MEM
)
9467 /* Don't differentiate between memory addresses. All the ones
9468 we accept have equal cost. */
9469 *total
= COSTS_N_INSNS (0);
9476 /* Make 12-bit integers really cheap. */
9477 if (IN_RANGE (INTVAL (x
), -2048, 2047))
9488 *total
= COSTS_N_INSNS (2);
9502 if (GET_MODE (x
) == SImode
)
9503 *total
= COSTS_N_INSNS (1);
9504 else if (GET_MODE (x
) == DImode
)
9505 *total
= COSTS_N_INSNS (2);
9507 *total
= COSTS_N_INSNS (3);
9511 if (GET_MODE (x
) == SImode
)
9512 *total
= COSTS_N_INSNS (2);
9514 *total
= COSTS_N_INSNS (6); /* guess */
9521 *total
= COSTS_N_INSNS (18);
9525 *total
= COSTS_N_INSNS (3);
9534 frv_asm_out_constructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9536 switch_to_section (ctors_section
);
9537 assemble_align (POINTER_SIZE
);
9540 int ok
= frv_assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, 1);
9545 assemble_integer_with_op ("\t.picptr\t", symbol
);
9549 frv_asm_out_destructor (rtx symbol
, int priority ATTRIBUTE_UNUSED
)
9551 switch_to_section (dtors_section
);
9552 assemble_align (POINTER_SIZE
);
9555 int ok
= frv_assemble_integer (symbol
, POINTER_SIZE
/ BITS_PER_UNIT
, 1);
9560 assemble_integer_with_op ("\t.picptr\t", symbol
);
9563 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9566 frv_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED
,
9567 int incoming ATTRIBUTE_UNUSED
)
9569 return gen_rtx_REG (Pmode
, FRV_STRUCT_VALUE_REGNUM
);
9572 #define TLS_BIAS (2048 - 16)
9574 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
9575 We need to emit DTP-relative relocations. */
9578 frv_output_dwarf_dtprel (FILE *file
, int size
, rtx x
)
9580 gcc_assert (size
== 4);
9581 fputs ("\t.picptr\ttlsmoff(", file
);
9582 /* We want the unbiased TLS offset, so add the bias to the
9583 expression, such that the implicit biasing cancels out. */
9584 output_addr_const (file
, plus_constant (Pmode
, x
, TLS_BIAS
));