1 /* Medium-level subroutines: convert bit-field store and extract
2 and shifts, multiplies and divides to rtl instructions.
3 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
4 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
31 #include "insn-config.h"
37 static void store_fixed_bit_field
PARAMS ((rtx
, unsigned HOST_WIDE_INT
,
38 unsigned HOST_WIDE_INT
,
39 unsigned HOST_WIDE_INT
, rtx
));
40 static void store_split_bit_field
PARAMS ((rtx
, unsigned HOST_WIDE_INT
,
41 unsigned HOST_WIDE_INT
, rtx
));
42 static rtx extract_fixed_bit_field
PARAMS ((enum machine_mode
, rtx
,
43 unsigned HOST_WIDE_INT
,
44 unsigned HOST_WIDE_INT
,
45 unsigned HOST_WIDE_INT
,
47 static rtx mask_rtx
PARAMS ((enum machine_mode
, int,
49 static rtx lshift_value
PARAMS ((enum machine_mode
, rtx
,
51 static rtx extract_split_bit_field
PARAMS ((rtx
, unsigned HOST_WIDE_INT
,
52 unsigned HOST_WIDE_INT
, int));
53 static void do_cmp_and_jump
PARAMS ((rtx
, rtx
, enum rtx_code
,
54 enum machine_mode
, rtx
));
56 /* Non-zero means divides or modulus operations are relatively cheap for
57 powers of two, so don't use branches; emit the operation instead.
58 Usually, this will mean that the MD file will emit non-branch
61 static int sdiv_pow2_cheap
, smod_pow2_cheap
;
63 #ifndef SLOW_UNALIGNED_ACCESS
64 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) STRICT_ALIGNMENT
67 /* For compilers that support multiple targets with different word sizes,
68 MAX_BITS_PER_WORD contains the biggest value of BITS_PER_WORD. An example
69 is the H8/300(H) compiler. */
71 #ifndef MAX_BITS_PER_WORD
72 #define MAX_BITS_PER_WORD BITS_PER_WORD
75 /* Reduce conditional compilation elsewhere. */
78 #define CODE_FOR_insv CODE_FOR_nothing
79 #define gen_insv(a,b,c,d) NULL_RTX
83 #define CODE_FOR_extv CODE_FOR_nothing
84 #define gen_extv(a,b,c,d) NULL_RTX
88 #define CODE_FOR_extzv CODE_FOR_nothing
89 #define gen_extzv(a,b,c,d) NULL_RTX
92 /* Cost of various pieces of RTL. Note that some of these are indexed by
93 shift count and some by mode. */
94 static int add_cost
, negate_cost
, zero_cost
;
95 static int shift_cost
[MAX_BITS_PER_WORD
];
96 static int shiftadd_cost
[MAX_BITS_PER_WORD
];
97 static int shiftsub_cost
[MAX_BITS_PER_WORD
];
98 static int mul_cost
[NUM_MACHINE_MODES
];
99 static int div_cost
[NUM_MACHINE_MODES
];
100 static int mul_widen_cost
[NUM_MACHINE_MODES
];
101 static int mul_highpart_cost
[NUM_MACHINE_MODES
];
106 /* This is "some random pseudo register" for purposes of calling recog
107 to see what insns exist. */
108 rtx reg
= gen_rtx_REG (word_mode
, 10000);
109 rtx shift_insn
, shiftadd_insn
, shiftsub_insn
;
112 enum machine_mode mode
, wider_mode
;
116 reg
= gen_rtx_REG (word_mode
, 10000);
118 zero_cost
= rtx_cost (const0_rtx
, 0);
119 add_cost
= rtx_cost (gen_rtx_PLUS (word_mode
, reg
, reg
), SET
);
121 shift_insn
= emit_insn (gen_rtx_SET (VOIDmode
, reg
,
122 gen_rtx_ASHIFT (word_mode
, reg
,
126 = emit_insn (gen_rtx_SET (VOIDmode
, reg
,
127 gen_rtx_PLUS (word_mode
,
128 gen_rtx_MULT (word_mode
,
133 = emit_insn (gen_rtx_SET (VOIDmode
, reg
,
134 gen_rtx_MINUS (word_mode
,
135 gen_rtx_MULT (word_mode
,
142 shiftadd_cost
[0] = shiftsub_cost
[0] = add_cost
;
144 for (m
= 1; m
< MAX_BITS_PER_WORD
; m
++)
146 shift_cost
[m
] = shiftadd_cost
[m
] = shiftsub_cost
[m
] = 32000;
148 XEXP (SET_SRC (PATTERN (shift_insn
)), 1) = GEN_INT (m
);
149 if (recog (PATTERN (shift_insn
), shift_insn
, &dummy
) >= 0)
150 shift_cost
[m
] = rtx_cost (SET_SRC (PATTERN (shift_insn
)), SET
);
152 XEXP (XEXP (SET_SRC (PATTERN (shiftadd_insn
)), 0), 1)
153 = GEN_INT ((HOST_WIDE_INT
) 1 << m
);
154 if (recog (PATTERN (shiftadd_insn
), shiftadd_insn
, &dummy
) >= 0)
155 shiftadd_cost
[m
] = rtx_cost (SET_SRC (PATTERN (shiftadd_insn
)), SET
);
157 XEXP (XEXP (SET_SRC (PATTERN (shiftsub_insn
)), 0), 1)
158 = GEN_INT ((HOST_WIDE_INT
) 1 << m
);
159 if (recog (PATTERN (shiftsub_insn
), shiftsub_insn
, &dummy
) >= 0)
160 shiftsub_cost
[m
] = rtx_cost (SET_SRC (PATTERN (shiftsub_insn
)), SET
);
163 negate_cost
= rtx_cost (gen_rtx_NEG (word_mode
, reg
), SET
);
166 = (rtx_cost (gen_rtx_DIV (word_mode
, reg
, GEN_INT (32)), SET
)
169 = (rtx_cost (gen_rtx_MOD (word_mode
, reg
, GEN_INT (32)), SET
)
172 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
);
174 mode
= GET_MODE_WIDER_MODE (mode
))
176 reg
= gen_rtx_REG (mode
, 10000);
177 div_cost
[(int) mode
] = rtx_cost (gen_rtx_UDIV (mode
, reg
, reg
), SET
);
178 mul_cost
[(int) mode
] = rtx_cost (gen_rtx_MULT (mode
, reg
, reg
), SET
);
179 wider_mode
= GET_MODE_WIDER_MODE (mode
);
180 if (wider_mode
!= VOIDmode
)
182 mul_widen_cost
[(int) wider_mode
]
183 = rtx_cost (gen_rtx_MULT (wider_mode
,
184 gen_rtx_ZERO_EXTEND (wider_mode
, reg
),
185 gen_rtx_ZERO_EXTEND (wider_mode
, reg
)),
187 mul_highpart_cost
[(int) mode
]
188 = rtx_cost (gen_rtx_TRUNCATE
190 gen_rtx_LSHIFTRT (wider_mode
,
191 gen_rtx_MULT (wider_mode
,
196 GEN_INT (GET_MODE_BITSIZE (mode
)))),
204 /* Return an rtx representing minus the value of X.
205 MODE is the intended mode of the result,
206 useful if X is a CONST_INT. */
210 enum machine_mode mode
;
213 rtx result
= simplify_unary_operation (NEG
, mode
, x
, mode
);
216 result
= expand_unop (mode
, neg_optab
, x
, NULL_RTX
, 0);
221 /* Report on the availability of insv/extv/extzv and the desired mode
222 of each of their operands. Returns MAX_MACHINE_MODE if HAVE_foo
223 is false; else the mode of the specified operand. If OPNO is -1,
224 all the caller cares about is whether the insn is available. */
226 mode_for_extraction (pattern
, opno
)
227 enum extraction_pattern pattern
;
230 const struct insn_data
*data
;
237 data
= &insn_data
[CODE_FOR_insv
];
240 return MAX_MACHINE_MODE
;
245 data
= &insn_data
[CODE_FOR_extv
];
248 return MAX_MACHINE_MODE
;
253 data
= &insn_data
[CODE_FOR_extzv
];
256 return MAX_MACHINE_MODE
;
265 /* Everyone who uses this function used to follow it with
266 if (result == VOIDmode) result = word_mode; */
267 if (data
->operand
[opno
].mode
== VOIDmode
)
269 return data
->operand
[opno
].mode
;
273 /* Generate code to store value from rtx VALUE
274 into a bit-field within structure STR_RTX
275 containing BITSIZE bits starting at bit BITNUM.
276 FIELDMODE is the machine-mode of the FIELD_DECL node for this field.
277 ALIGN is the alignment that STR_RTX is known to have.
278 TOTAL_SIZE is the size of the structure in bytes, or -1 if varying. */
280 /* ??? Note that there are two different ideas here for how
281 to determine the size to count bits within, for a register.
282 One is BITS_PER_WORD, and the other is the size of operand 3
285 If operand 3 of the insv pattern is VOIDmode, then we will use BITS_PER_WORD
286 else, we use the mode of operand 3. */
289 store_bit_field (str_rtx
, bitsize
, bitnum
, fieldmode
, value
, total_size
)
291 unsigned HOST_WIDE_INT bitsize
;
292 unsigned HOST_WIDE_INT bitnum
;
293 enum machine_mode fieldmode
;
295 HOST_WIDE_INT total_size
;
298 = (GET_CODE (str_rtx
) == MEM
) ? BITS_PER_UNIT
: BITS_PER_WORD
;
299 unsigned HOST_WIDE_INT offset
= bitnum
/ unit
;
300 unsigned HOST_WIDE_INT bitpos
= bitnum
% unit
;
303 enum machine_mode op_mode
= mode_for_extraction (EP_insv
, 3);
305 /* Discount the part of the structure before the desired byte.
306 We need to know how many bytes are safe to reference after it. */
308 total_size
-= (bitpos
/ BIGGEST_ALIGNMENT
309 * (BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
));
311 while (GET_CODE (op0
) == SUBREG
)
313 /* The following line once was done only if WORDS_BIG_ENDIAN,
314 but I think that is a mistake. WORDS_BIG_ENDIAN is
315 meaningful at a much higher level; when structures are copied
316 between memory and regs, the higher-numbered regs
317 always get higher addresses. */
318 offset
+= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
);
319 /* We used to adjust BITPOS here, but now we do the whole adjustment
320 right after the loop. */
321 op0
= SUBREG_REG (op0
);
324 value
= protect_from_queue (value
, 0);
327 value
= force_not_mem (value
);
329 /* If the target is a register, overwriting the entire object, or storing
330 a full-word or multi-word field can be done with just a SUBREG.
332 If the target is memory, storing any naturally aligned field can be
333 done with a simple store. For targets that support fast unaligned
334 memory, any naturally sized, unit aligned field can be done directly. */
337 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
338 && (GET_CODE (op0
) != MEM
339 ? (GET_MODE_SIZE (fieldmode
) >= UNITS_PER_WORD
340 || GET_MODE_SIZE (GET_MODE (op0
)) == GET_MODE_SIZE (fieldmode
))
341 : (! SLOW_UNALIGNED_ACCESS (fieldmode
, MEM_ALIGN (op0
))
342 || (offset
* BITS_PER_UNIT
% bitsize
== 0
343 && MEM_ALIGN (op0
) % GET_MODE_BITSIZE (fieldmode
) == 0))))
345 if (GET_MODE (op0
) != fieldmode
)
347 if (GET_CODE (op0
) == SUBREG
)
349 if (GET_MODE (SUBREG_REG (op0
)) == fieldmode
350 || GET_MODE_CLASS (fieldmode
) == MODE_INT
351 || GET_MODE_CLASS (fieldmode
) == MODE_PARTIAL_INT
)
352 op0
= SUBREG_REG (op0
);
354 /* Else we've got some float mode source being extracted into
355 a different float mode destination -- this combination of
356 subregs results in Severe Tire Damage. */
359 if (GET_CODE (op0
) == REG
)
360 op0
= gen_rtx_SUBREG (fieldmode
, op0
,
361 (bitnum
% BITS_PER_WORD
) / BITS_PER_UNIT
362 + (offset
* UNITS_PER_WORD
));
364 op0
= adjust_address (op0
, fieldmode
, offset
);
366 emit_move_insn (op0
, value
);
370 /* Make sure we are playing with integral modes. Pun with subregs
371 if we aren't. This must come after the entire register case above,
372 since that case is valid for any mode. The following cases are only
373 valid for integral modes. */
375 enum machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
376 if (imode
!= GET_MODE (op0
))
378 if (GET_CODE (op0
) == MEM
)
379 op0
= adjust_address (op0
, imode
, 0);
380 else if (imode
!= BLKmode
)
381 op0
= gen_lowpart (imode
, op0
);
387 /* If OP0 is a register, BITPOS must count within a word.
388 But as we have it, it counts within whatever size OP0 now has.
389 On a bigendian machine, these are not the same, so convert. */
391 && GET_CODE (op0
) != MEM
392 && unit
> GET_MODE_BITSIZE (GET_MODE (op0
)))
393 bitpos
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
395 /* Storing an lsb-aligned field in a register
396 can be done with a movestrict instruction. */
398 if (GET_CODE (op0
) != MEM
399 && (BYTES_BIG_ENDIAN
? bitpos
+ bitsize
== unit
: bitpos
== 0)
400 && bitsize
== GET_MODE_BITSIZE (fieldmode
)
401 && (movstrict_optab
->handlers
[(int) fieldmode
].insn_code
402 != CODE_FOR_nothing
))
404 int icode
= movstrict_optab
->handlers
[(int) fieldmode
].insn_code
;
406 /* Get appropriate low part of the value being stored. */
407 if (GET_CODE (value
) == CONST_INT
|| GET_CODE (value
) == REG
)
408 value
= gen_lowpart (fieldmode
, value
);
409 else if (!(GET_CODE (value
) == SYMBOL_REF
410 || GET_CODE (value
) == LABEL_REF
411 || GET_CODE (value
) == CONST
))
412 value
= convert_to_mode (fieldmode
, value
, 0);
414 if (! (*insn_data
[icode
].operand
[1].predicate
) (value
, fieldmode
))
415 value
= copy_to_mode_reg (fieldmode
, value
);
417 if (GET_CODE (op0
) == SUBREG
)
419 if (GET_MODE (SUBREG_REG (op0
)) == fieldmode
420 || GET_MODE_CLASS (fieldmode
) == MODE_INT
421 || GET_MODE_CLASS (fieldmode
) == MODE_PARTIAL_INT
)
422 op0
= SUBREG_REG (op0
);
424 /* Else we've got some float mode source being extracted into
425 a different float mode destination -- this combination of
426 subregs results in Severe Tire Damage. */
430 emit_insn (GEN_FCN (icode
)
431 (gen_rtx_SUBREG (fieldmode
, op0
,
432 (bitnum
% BITS_PER_WORD
) / BITS_PER_UNIT
433 + (offset
* UNITS_PER_WORD
)),
439 /* Handle fields bigger than a word. */
441 if (bitsize
> BITS_PER_WORD
)
443 /* Here we transfer the words of the field
444 in the order least significant first.
445 This is because the most significant word is the one which may
447 However, only do that if the value is not BLKmode. */
449 unsigned int backwards
= WORDS_BIG_ENDIAN
&& fieldmode
!= BLKmode
;
450 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
453 /* This is the mode we must force value to, so that there will be enough
454 subwords to extract. Note that fieldmode will often (always?) be
455 VOIDmode, because that is what store_field uses to indicate that this
456 is a bit field, but passing VOIDmode to operand_subword_force will
457 result in an abort. */
458 fieldmode
= smallest_mode_for_size (nwords
* BITS_PER_WORD
, MODE_INT
);
460 for (i
= 0; i
< nwords
; i
++)
462 /* If I is 0, use the low-order word in both field and target;
463 if I is 1, use the next to lowest word; and so on. */
464 unsigned int wordnum
= (backwards
? nwords
- i
- 1 : i
);
465 unsigned int bit_offset
= (backwards
466 ? MAX ((int) bitsize
- ((int) i
+ 1)
469 : (int) i
* BITS_PER_WORD
);
471 store_bit_field (op0
, MIN (BITS_PER_WORD
,
472 bitsize
- i
* BITS_PER_WORD
),
473 bitnum
+ bit_offset
, word_mode
,
474 operand_subword_force (value
, wordnum
,
475 (GET_MODE (value
) == VOIDmode
477 : GET_MODE (value
))),
483 /* From here on we can assume that the field to be stored in is
484 a full-word (whatever type that is), since it is shorter than a word. */
486 /* OFFSET is the number of words or bytes (UNIT says which)
487 from STR_RTX to the first word or byte containing part of the field. */
489 if (GET_CODE (op0
) != MEM
)
492 || GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
494 if (GET_CODE (op0
) != REG
)
496 /* Since this is a destination (lvalue), we can't copy it to a
497 pseudo. We can trivially remove a SUBREG that does not
498 change the size of the operand. Such a SUBREG may have been
499 added above. Otherwise, abort. */
500 if (GET_CODE (op0
) == SUBREG
501 && (GET_MODE_SIZE (GET_MODE (op0
))
502 == GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0
)))))
503 op0
= SUBREG_REG (op0
);
507 op0
= gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD
, MODE_INT
, 0),
508 op0
, (offset
* UNITS_PER_WORD
));
513 op0
= protect_from_queue (op0
, 1);
515 /* If VALUE is a floating-point mode, access it as an integer of the
516 corresponding size. This can occur on a machine with 64 bit registers
517 that uses SFmode for float. This can also occur for unaligned float
519 if (GET_MODE_CLASS (GET_MODE (value
)) == MODE_FLOAT
)
521 if (GET_CODE (value
) != REG
)
522 value
= copy_to_reg (value
);
523 value
= gen_rtx_SUBREG (word_mode
, value
, 0);
526 /* Now OFFSET is nonzero only if OP0 is memory
527 and is therefore always measured in bytes. */
530 && GET_MODE (value
) != BLKmode
531 && !(bitsize
== 1 && GET_CODE (value
) == CONST_INT
)
532 /* Ensure insv's size is wide enough for this field. */
533 && (GET_MODE_BITSIZE (op_mode
) >= bitsize
)
534 && ! ((GET_CODE (op0
) == REG
|| GET_CODE (op0
) == SUBREG
)
535 && (bitsize
+ bitpos
> GET_MODE_BITSIZE (op_mode
))))
537 int xbitpos
= bitpos
;
540 rtx last
= get_last_insn ();
542 enum machine_mode maxmode
= mode_for_extraction (EP_insv
, 3);
543 int save_volatile_ok
= volatile_ok
;
547 /* If this machine's insv can only insert into a register, copy OP0
548 into a register and save it back later. */
549 /* This used to check flag_force_mem, but that was a serious
550 de-optimization now that flag_force_mem is enabled by -O2. */
551 if (GET_CODE (op0
) == MEM
552 && ! ((*insn_data
[(int) CODE_FOR_insv
].operand
[0].predicate
)
556 enum machine_mode bestmode
;
558 /* Get the mode to use for inserting into this field. If OP0 is
559 BLKmode, get the smallest mode consistent with the alignment. If
560 OP0 is a non-BLKmode object that is no wider than MAXMODE, use its
561 mode. Otherwise, use the smallest mode containing the field. */
563 if (GET_MODE (op0
) == BLKmode
564 || GET_MODE_SIZE (GET_MODE (op0
)) > GET_MODE_SIZE (maxmode
))
566 = get_best_mode (bitsize
, bitnum
, MEM_ALIGN (op0
), maxmode
,
567 MEM_VOLATILE_P (op0
));
569 bestmode
= GET_MODE (op0
);
571 if (bestmode
== VOIDmode
572 || (SLOW_UNALIGNED_ACCESS (bestmode
, MEM_ALIGN (op0
))
573 && GET_MODE_BITSIZE (bestmode
) > MEM_ALIGN (op0
)))
576 /* Adjust address to point to the containing unit of that mode.
577 Compute offset as multiple of this unit, counting in bytes. */
578 unit
= GET_MODE_BITSIZE (bestmode
);
579 offset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
580 bitpos
= bitnum
% unit
;
581 op0
= adjust_address (op0
, bestmode
, offset
);
583 /* Fetch that unit, store the bitfield in it, then store
585 tempreg
= copy_to_reg (op0
);
586 store_bit_field (tempreg
, bitsize
, bitpos
, fieldmode
, value
,
588 emit_move_insn (op0
, tempreg
);
591 volatile_ok
= save_volatile_ok
;
593 /* Add OFFSET into OP0's address. */
594 if (GET_CODE (xop0
) == MEM
)
595 xop0
= adjust_address (xop0
, byte_mode
, offset
);
597 /* If xop0 is a register, we need it in MAXMODE
598 to make it acceptable to the format of insv. */
599 if (GET_CODE (xop0
) == SUBREG
)
600 /* We can't just change the mode, because this might clobber op0,
601 and we will need the original value of op0 if insv fails. */
602 xop0
= gen_rtx_SUBREG (maxmode
, SUBREG_REG (xop0
), SUBREG_BYTE (xop0
));
603 if (GET_CODE (xop0
) == REG
&& GET_MODE (xop0
) != maxmode
)
604 xop0
= gen_rtx_SUBREG (maxmode
, xop0
, 0);
606 /* On big-endian machines, we count bits from the most significant.
607 If the bit field insn does not, we must invert. */
609 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
610 xbitpos
= unit
- bitsize
- xbitpos
;
612 /* We have been counting XBITPOS within UNIT.
613 Count instead within the size of the register. */
614 if (BITS_BIG_ENDIAN
&& GET_CODE (xop0
) != MEM
)
615 xbitpos
+= GET_MODE_BITSIZE (maxmode
) - unit
;
617 unit
= GET_MODE_BITSIZE (maxmode
);
619 /* Convert VALUE to maxmode (which insv insn wants) in VALUE1. */
621 if (GET_MODE (value
) != maxmode
)
623 if (GET_MODE_BITSIZE (GET_MODE (value
)) >= bitsize
)
625 /* Optimization: Don't bother really extending VALUE
626 if it has all the bits we will actually use. However,
627 if we must narrow it, be sure we do it correctly. */
629 if (GET_MODE_SIZE (GET_MODE (value
)) < GET_MODE_SIZE (maxmode
))
630 value1
= simplify_gen_subreg (maxmode
, value1
,
631 GET_MODE (value1
), 0);
633 value1
= gen_lowpart (maxmode
, value1
);
635 else if (GET_CODE (value
) == CONST_INT
)
636 value1
= GEN_INT (trunc_int_for_mode (INTVAL (value
), maxmode
));
637 else if (!CONSTANT_P (value
))
638 /* Parse phase is supposed to make VALUE's data type
639 match that of the component reference, which is a type
640 at least as wide as the field; so VALUE should have
641 a mode that corresponds to that type. */
645 /* If this machine's insv insists on a register,
646 get VALUE1 into a register. */
647 if (! ((*insn_data
[(int) CODE_FOR_insv
].operand
[3].predicate
)
649 value1
= force_reg (maxmode
, value1
);
651 pat
= gen_insv (xop0
, GEN_INT (bitsize
), GEN_INT (xbitpos
), value1
);
656 delete_insns_since (last
);
657 store_fixed_bit_field (op0
, offset
, bitsize
, bitpos
, value
);
662 /* Insv is not available; store using shifts and boolean ops. */
663 store_fixed_bit_field (op0
, offset
, bitsize
, bitpos
, value
);
667 /* Use shifts and boolean operations to store VALUE
668 into a bit field of width BITSIZE
669 in a memory location specified by OP0 except offset by OFFSET bytes.
670 (OFFSET must be 0 if OP0 is a register.)
671 The field starts at position BITPOS within the byte.
672 (If OP0 is a register, it may be a full word or a narrower mode,
673 but BITPOS still counts within a full word,
674 which is significant on bigendian machines.)
676 Note that protect_from_queue has already been done on OP0 and VALUE. */
679 store_fixed_bit_field (op0
, offset
, bitsize
, bitpos
, value
)
681 unsigned HOST_WIDE_INT offset
, bitsize
, bitpos
;
684 enum machine_mode mode
;
685 unsigned int total_bits
= BITS_PER_WORD
;
690 /* There is a case not handled here:
691 a structure with a known alignment of just a halfword
692 and a field split across two aligned halfwords within the structure.
693 Or likewise a structure with a known alignment of just a byte
694 and a field split across two bytes.
695 Such cases are not supposed to be able to occur. */
697 if (GET_CODE (op0
) == REG
|| GET_CODE (op0
) == SUBREG
)
701 /* Special treatment for a bit field split across two registers. */
702 if (bitsize
+ bitpos
> BITS_PER_WORD
)
704 store_split_bit_field (op0
, bitsize
, bitpos
, value
);
710 /* Get the proper mode to use for this field. We want a mode that
711 includes the entire field. If such a mode would be larger than
712 a word, we won't be doing the extraction the normal way.
713 We don't want a mode bigger than the destination. */
715 mode
= GET_MODE (op0
);
716 if (GET_MODE_BITSIZE (mode
) == 0
717 || GET_MODE_BITSIZE (mode
) > GET_MODE_BITSIZE (word_mode
))
719 mode
= get_best_mode (bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
720 MEM_ALIGN (op0
), mode
, MEM_VOLATILE_P (op0
));
722 if (mode
== VOIDmode
)
724 /* The only way this should occur is if the field spans word
726 store_split_bit_field (op0
, bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
731 total_bits
= GET_MODE_BITSIZE (mode
);
733 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
734 be in the range 0 to total_bits-1, and put any excess bytes in
736 if (bitpos
>= total_bits
)
738 offset
+= (bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
);
739 bitpos
-= ((bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
)
743 /* Get ref to an aligned byte, halfword, or word containing the field.
744 Adjust BITPOS to be position within a word,
745 and OFFSET to be the offset of that word.
746 Then alter OP0 to refer to that word. */
747 bitpos
+= (offset
% (total_bits
/ BITS_PER_UNIT
)) * BITS_PER_UNIT
;
748 offset
-= (offset
% (total_bits
/ BITS_PER_UNIT
));
749 op0
= adjust_address (op0
, mode
, offset
);
752 mode
= GET_MODE (op0
);
754 /* Now MODE is either some integral mode for a MEM as OP0,
755 or is a full-word for a REG as OP0. TOTAL_BITS corresponds.
756 The bit field is contained entirely within OP0.
757 BITPOS is the starting bit number within OP0.
758 (OP0's mode may actually be narrower than MODE.) */
760 if (BYTES_BIG_ENDIAN
)
761 /* BITPOS is the distance between our msb
762 and that of the containing datum.
763 Convert it to the distance from the lsb. */
764 bitpos
= total_bits
- bitsize
- bitpos
;
766 /* Now BITPOS is always the distance between our lsb
769 /* Shift VALUE left by BITPOS bits. If VALUE is not constant,
770 we must first convert its mode to MODE. */
772 if (GET_CODE (value
) == CONST_INT
)
774 HOST_WIDE_INT v
= INTVAL (value
);
776 if (bitsize
< HOST_BITS_PER_WIDE_INT
)
777 v
&= ((HOST_WIDE_INT
) 1 << bitsize
) - 1;
781 else if ((bitsize
< HOST_BITS_PER_WIDE_INT
782 && v
== ((HOST_WIDE_INT
) 1 << bitsize
) - 1)
783 || (bitsize
== HOST_BITS_PER_WIDE_INT
&& v
== -1))
786 value
= lshift_value (mode
, value
, bitpos
, bitsize
);
790 int must_and
= (GET_MODE_BITSIZE (GET_MODE (value
)) != bitsize
791 && bitpos
+ bitsize
!= GET_MODE_BITSIZE (mode
));
793 if (GET_MODE (value
) != mode
)
795 if ((GET_CODE (value
) == REG
|| GET_CODE (value
) == SUBREG
)
796 && GET_MODE_SIZE (mode
) < GET_MODE_SIZE (GET_MODE (value
)))
797 value
= gen_lowpart (mode
, value
);
799 value
= convert_to_mode (mode
, value
, 1);
803 value
= expand_binop (mode
, and_optab
, value
,
804 mask_rtx (mode
, 0, bitsize
, 0),
805 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
807 value
= expand_shift (LSHIFT_EXPR
, mode
, value
,
808 build_int_2 (bitpos
, 0), NULL_RTX
, 1);
811 /* Now clear the chosen bits in OP0,
812 except that if VALUE is -1 we need not bother. */
814 subtarget
= (GET_CODE (op0
) == REG
|| ! flag_force_mem
) ? op0
: 0;
818 temp
= expand_binop (mode
, and_optab
, op0
,
819 mask_rtx (mode
, bitpos
, bitsize
, 1),
820 subtarget
, 1, OPTAB_LIB_WIDEN
);
826 /* Now logical-or VALUE into OP0, unless it is zero. */
829 temp
= expand_binop (mode
, ior_optab
, temp
, value
,
830 subtarget
, 1, OPTAB_LIB_WIDEN
);
832 emit_move_insn (op0
, temp
);
835 /* Store a bit field that is split across multiple accessible memory objects.
837 OP0 is the REG, SUBREG or MEM rtx for the first of the objects.
838 BITSIZE is the field width; BITPOS the position of its first bit
840 VALUE is the value to store.
842 This does not yet handle fields wider than BITS_PER_WORD. */
845 store_split_bit_field (op0
, bitsize
, bitpos
, value
)
847 unsigned HOST_WIDE_INT bitsize
, bitpos
;
851 unsigned int bitsdone
= 0;
853 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
855 if (GET_CODE (op0
) == REG
|| GET_CODE (op0
) == SUBREG
)
856 unit
= BITS_PER_WORD
;
858 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
860 /* If VALUE is a constant other than a CONST_INT, get it into a register in
861 WORD_MODE. If we can do this using gen_lowpart_common, do so. Note
862 that VALUE might be a floating-point constant. */
863 if (CONSTANT_P (value
) && GET_CODE (value
) != CONST_INT
)
865 rtx word
= gen_lowpart_common (word_mode
, value
);
867 if (word
&& (value
!= word
))
870 value
= gen_lowpart_common (word_mode
,
871 force_reg (GET_MODE (value
) != VOIDmode
873 : word_mode
, value
));
875 else if (GET_CODE (value
) == ADDRESSOF
)
876 value
= copy_to_reg (value
);
878 while (bitsdone
< bitsize
)
880 unsigned HOST_WIDE_INT thissize
;
882 unsigned HOST_WIDE_INT thispos
;
883 unsigned HOST_WIDE_INT offset
;
885 offset
= (bitpos
+ bitsdone
) / unit
;
886 thispos
= (bitpos
+ bitsdone
) % unit
;
888 /* THISSIZE must not overrun a word boundary. Otherwise,
889 store_fixed_bit_field will call us again, and we will mutually
891 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
892 thissize
= MIN (thissize
, unit
- thispos
);
894 if (BYTES_BIG_ENDIAN
)
898 /* We must do an endian conversion exactly the same way as it is
899 done in extract_bit_field, so that the two calls to
900 extract_fixed_bit_field will have comparable arguments. */
901 if (GET_CODE (value
) != MEM
|| GET_MODE (value
) == BLKmode
)
902 total_bits
= BITS_PER_WORD
;
904 total_bits
= GET_MODE_BITSIZE (GET_MODE (value
));
906 /* Fetch successively less significant portions. */
907 if (GET_CODE (value
) == CONST_INT
)
908 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
909 >> (bitsize
- bitsdone
- thissize
))
910 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
912 /* The args are chosen so that the last part includes the
913 lsb. Give extract_bit_field the value it needs (with
914 endianness compensation) to fetch the piece we want. */
915 part
= extract_fixed_bit_field (word_mode
, value
, 0, thissize
,
916 total_bits
- bitsize
+ bitsdone
,
921 /* Fetch successively more significant portions. */
922 if (GET_CODE (value
) == CONST_INT
)
923 part
= GEN_INT (((unsigned HOST_WIDE_INT
) (INTVAL (value
))
925 & (((HOST_WIDE_INT
) 1 << thissize
) - 1));
927 part
= extract_fixed_bit_field (word_mode
, value
, 0, thissize
,
928 bitsdone
, NULL_RTX
, 1);
931 /* If OP0 is a register, then handle OFFSET here.
933 When handling multiword bitfields, extract_bit_field may pass
934 down a word_mode SUBREG of a larger REG for a bitfield that actually
935 crosses a word boundary. Thus, for a SUBREG, we must find
936 the current word starting from the base register. */
937 if (GET_CODE (op0
) == SUBREG
)
939 int word_offset
= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
) + offset
;
940 word
= operand_subword_force (SUBREG_REG (op0
), word_offset
,
941 GET_MODE (SUBREG_REG (op0
)));
944 else if (GET_CODE (op0
) == REG
)
946 word
= operand_subword_force (op0
, offset
, GET_MODE (op0
));
952 /* OFFSET is in UNITs, and UNIT is in bits.
953 store_fixed_bit_field wants offset in bytes. */
954 store_fixed_bit_field (word
, offset
* unit
/ BITS_PER_UNIT
, thissize
,
956 bitsdone
+= thissize
;
960 /* Generate code to extract a byte-field from STR_RTX
961 containing BITSIZE bits, starting at BITNUM,
962 and put it in TARGET if possible (if TARGET is nonzero).
963 Regardless of TARGET, we return the rtx for where the value is placed.
966 STR_RTX is the structure containing the byte (a REG or MEM).
967 UNSIGNEDP is nonzero if this is an unsigned bit field.
968 MODE is the natural mode of the field value once extracted.
969 TMODE is the mode the caller would like the value to have;
970 but the value may be returned with type MODE instead.
972 TOTAL_SIZE is the size in bytes of the containing structure,
975 If a TARGET is specified and we can store in it at no extra cost,
976 we do so, and return TARGET.
977 Otherwise, we return a REG of mode TMODE or MODE, with TMODE preferred
978 if they are equally easy. */
981 extract_bit_field (str_rtx
, bitsize
, bitnum
, unsignedp
,
982 target
, mode
, tmode
, total_size
)
984 unsigned HOST_WIDE_INT bitsize
;
985 unsigned HOST_WIDE_INT bitnum
;
988 enum machine_mode mode
, tmode
;
989 HOST_WIDE_INT total_size
;
992 = (GET_CODE (str_rtx
) == MEM
) ? BITS_PER_UNIT
: BITS_PER_WORD
;
993 unsigned HOST_WIDE_INT offset
= bitnum
/ unit
;
994 unsigned HOST_WIDE_INT bitpos
= bitnum
% unit
;
996 rtx spec_target
= target
;
997 rtx spec_target_subreg
= 0;
998 enum machine_mode int_mode
;
999 enum machine_mode extv_mode
= mode_for_extraction (EP_extv
, 0);
1000 enum machine_mode extzv_mode
= mode_for_extraction (EP_extzv
, 0);
1001 enum machine_mode mode1
;
1004 /* Discount the part of the structure before the desired byte.
1005 We need to know how many bytes are safe to reference after it. */
1006 if (total_size
>= 0)
1007 total_size
-= (bitpos
/ BIGGEST_ALIGNMENT
1008 * (BIGGEST_ALIGNMENT
/ BITS_PER_UNIT
));
1010 if (tmode
== VOIDmode
)
1012 while (GET_CODE (op0
) == SUBREG
)
1014 int outer_size
= GET_MODE_BITSIZE (GET_MODE (op0
));
1015 int inner_size
= GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0
)));
1017 offset
+= SUBREG_BYTE (op0
) / UNITS_PER_WORD
;
1019 inner_size
= MIN (inner_size
, BITS_PER_WORD
);
1021 if (BYTES_BIG_ENDIAN
&& (outer_size
< inner_size
))
1023 bitpos
+= inner_size
- outer_size
;
1026 offset
+= (bitpos
/ unit
);
1031 op0
= SUBREG_REG (op0
);
1034 if (GET_CODE (op0
) == REG
1035 && mode
== GET_MODE (op0
)
1037 && bitsize
== GET_MODE_BITSIZE (GET_MODE (op0
)))
1039 /* We're trying to extract a full register from itself. */
1043 /* Make sure we are playing with integral modes. Pun with subregs
1046 enum machine_mode imode
= int_mode_for_mode (GET_MODE (op0
));
1047 if (imode
!= GET_MODE (op0
))
1049 if (GET_CODE (op0
) == MEM
)
1050 op0
= adjust_address (op0
, imode
, 0);
1051 else if (imode
!= BLKmode
)
1052 op0
= gen_lowpart (imode
, op0
);
1058 /* ??? We currently assume TARGET is at least as big as BITSIZE.
1059 If that's wrong, the solution is to test for it and set TARGET to 0
1062 /* If OP0 is a register, BITPOS must count within a word.
1063 But as we have it, it counts within whatever size OP0 now has.
1064 On a bigendian machine, these are not the same, so convert. */
1065 if (BYTES_BIG_ENDIAN
1066 && GET_CODE (op0
) != MEM
1067 && unit
> GET_MODE_BITSIZE (GET_MODE (op0
)))
1068 bitpos
+= unit
- GET_MODE_BITSIZE (GET_MODE (op0
));
1070 /* Extracting a full-word or multi-word value
1071 from a structure in a register or aligned memory.
1072 This can be done with just SUBREG.
1073 So too extracting a subword value in
1074 the least significant part of the register. */
1076 byte_offset
= (bitnum
% BITS_PER_WORD
) / BITS_PER_UNIT
1077 + (offset
* UNITS_PER_WORD
);
1079 mode1
= (VECTOR_MODE_P (tmode
)
1081 : mode_for_size (bitsize
, GET_MODE_CLASS (tmode
), 0));
1083 if (((GET_CODE (op0
) != MEM
1084 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode
),
1085 GET_MODE_BITSIZE (GET_MODE (op0
)))
1086 && GET_MODE_SIZE (mode1
) != 0
1087 && byte_offset
% GET_MODE_SIZE (mode1
) == 0)
1088 || (GET_CODE (op0
) == MEM
1089 && (! SLOW_UNALIGNED_ACCESS (mode
, MEM_ALIGN (op0
))
1090 || (offset
* BITS_PER_UNIT
% bitsize
== 0
1091 && MEM_ALIGN (op0
) % bitsize
== 0))))
1092 && ((bitsize
>= BITS_PER_WORD
&& bitsize
== GET_MODE_BITSIZE (mode
)
1093 && bitpos
% BITS_PER_WORD
== 0)
1094 || (mode_for_size (bitsize
, GET_MODE_CLASS (tmode
), 0) != BLKmode
1095 /* ??? The big endian test here is wrong. This is correct
1096 if the value is in a register, and if mode_for_size is not
1097 the same mode as op0. This causes us to get unnecessarily
1098 inefficient code from the Thumb port when -mbig-endian. */
1099 && (BYTES_BIG_ENDIAN
1100 ? bitpos
+ bitsize
== BITS_PER_WORD
1103 if (mode1
!= GET_MODE (op0
))
1105 if (GET_CODE (op0
) == SUBREG
)
1107 if (GET_MODE (SUBREG_REG (op0
)) == mode1
1108 || GET_MODE_CLASS (mode1
) == MODE_INT
1109 || GET_MODE_CLASS (mode1
) == MODE_PARTIAL_INT
)
1110 op0
= SUBREG_REG (op0
);
1112 /* Else we've got some float mode source being extracted into
1113 a different float mode destination -- this combination of
1114 subregs results in Severe Tire Damage. */
1117 if (GET_CODE (op0
) == REG
)
1118 op0
= gen_rtx_SUBREG (mode1
, op0
, byte_offset
);
1120 op0
= adjust_address (op0
, mode1
, offset
);
1123 return convert_to_mode (tmode
, op0
, unsignedp
);
1127 /* Handle fields bigger than a word. */
1129 if (bitsize
> BITS_PER_WORD
)
1131 /* Here we transfer the words of the field
1132 in the order least significant first.
1133 This is because the most significant word is the one which may
1134 be less than full. */
1136 unsigned int nwords
= (bitsize
+ (BITS_PER_WORD
- 1)) / BITS_PER_WORD
;
1139 if (target
== 0 || GET_CODE (target
) != REG
)
1140 target
= gen_reg_rtx (mode
);
1142 /* Indicate for flow that the entire target reg is being set. */
1143 emit_insn (gen_rtx_CLOBBER (VOIDmode
, target
));
1145 for (i
= 0; i
< nwords
; i
++)
1147 /* If I is 0, use the low-order word in both field and target;
1148 if I is 1, use the next to lowest word; and so on. */
1149 /* Word number in TARGET to use. */
1150 unsigned int wordnum
1152 ? GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
- i
- 1
1154 /* Offset from start of field in OP0. */
1155 unsigned int bit_offset
= (WORDS_BIG_ENDIAN
1156 ? MAX (0, ((int) bitsize
- ((int) i
+ 1)
1157 * (int) BITS_PER_WORD
))
1158 : (int) i
* BITS_PER_WORD
);
1159 rtx target_part
= operand_subword (target
, wordnum
, 1, VOIDmode
);
1161 = extract_bit_field (op0
, MIN (BITS_PER_WORD
,
1162 bitsize
- i
* BITS_PER_WORD
),
1163 bitnum
+ bit_offset
, 1, target_part
, mode
,
1164 word_mode
, total_size
);
1166 if (target_part
== 0)
1169 if (result_part
!= target_part
)
1170 emit_move_insn (target_part
, result_part
);
1175 /* Unless we've filled TARGET, the upper regs in a multi-reg value
1176 need to be zero'd out. */
1177 if (GET_MODE_SIZE (GET_MODE (target
)) > nwords
* UNITS_PER_WORD
)
1179 unsigned int i
, total_words
;
1181 total_words
= GET_MODE_SIZE (GET_MODE (target
)) / UNITS_PER_WORD
;
1182 for (i
= nwords
; i
< total_words
; i
++)
1184 (operand_subword (target
,
1185 WORDS_BIG_ENDIAN
? total_words
- i
- 1 : i
,
1192 /* Signed bit field: sign-extend with two arithmetic shifts. */
1193 target
= expand_shift (LSHIFT_EXPR
, mode
, target
,
1194 build_int_2 (GET_MODE_BITSIZE (mode
) - bitsize
, 0),
1196 return expand_shift (RSHIFT_EXPR
, mode
, target
,
1197 build_int_2 (GET_MODE_BITSIZE (mode
) - bitsize
, 0),
1201 /* From here on we know the desired field is smaller than a word. */
1203 /* Check if there is a correspondingly-sized integer field, so we can
1204 safely extract it as one size of integer, if necessary; then
1205 truncate or extend to the size that is wanted; then use SUBREGs or
1206 convert_to_mode to get one of the modes we really wanted. */
1208 int_mode
= int_mode_for_mode (tmode
);
1209 if (int_mode
== BLKmode
)
1210 int_mode
= int_mode_for_mode (mode
);
1211 if (int_mode
== BLKmode
)
1212 abort (); /* Should probably push op0 out to memory and then
1215 /* OFFSET is the number of words or bytes (UNIT says which)
1216 from STR_RTX to the first word or byte containing part of the field. */
1218 if (GET_CODE (op0
) != MEM
)
1221 || GET_MODE_SIZE (GET_MODE (op0
)) > UNITS_PER_WORD
)
1223 if (GET_CODE (op0
) != REG
)
1224 op0
= copy_to_reg (op0
);
1225 op0
= gen_rtx_SUBREG (mode_for_size (BITS_PER_WORD
, MODE_INT
, 0),
1226 op0
, (offset
* UNITS_PER_WORD
));
1231 op0
= protect_from_queue (str_rtx
, 1);
1233 /* Now OFFSET is nonzero only for memory operands. */
1238 && (GET_MODE_BITSIZE (extzv_mode
) >= bitsize
)
1239 && ! ((GET_CODE (op0
) == REG
|| GET_CODE (op0
) == SUBREG
)
1240 && (bitsize
+ bitpos
> GET_MODE_BITSIZE (extzv_mode
))))
1242 unsigned HOST_WIDE_INT xbitpos
= bitpos
, xoffset
= offset
;
1243 rtx bitsize_rtx
, bitpos_rtx
;
1244 rtx last
= get_last_insn ();
1246 rtx xtarget
= target
;
1247 rtx xspec_target
= spec_target
;
1248 rtx xspec_target_subreg
= spec_target_subreg
;
1250 enum machine_mode maxmode
= mode_for_extraction (EP_extzv
, 0);
1252 if (GET_CODE (xop0
) == MEM
)
1254 int save_volatile_ok
= volatile_ok
;
1257 /* Is the memory operand acceptable? */
1258 if (! ((*insn_data
[(int) CODE_FOR_extzv
].operand
[1].predicate
)
1259 (xop0
, GET_MODE (xop0
))))
1261 /* No, load into a reg and extract from there. */
1262 enum machine_mode bestmode
;
1264 /* Get the mode to use for inserting into this field. If
1265 OP0 is BLKmode, get the smallest mode consistent with the
1266 alignment. If OP0 is a non-BLKmode object that is no
1267 wider than MAXMODE, use its mode. Otherwise, use the
1268 smallest mode containing the field. */
1270 if (GET_MODE (xop0
) == BLKmode
1271 || (GET_MODE_SIZE (GET_MODE (op0
))
1272 > GET_MODE_SIZE (maxmode
)))
1273 bestmode
= get_best_mode (bitsize
, bitnum
,
1274 MEM_ALIGN (xop0
), maxmode
,
1275 MEM_VOLATILE_P (xop0
));
1277 bestmode
= GET_MODE (xop0
);
1279 if (bestmode
== VOIDmode
1280 || (SLOW_UNALIGNED_ACCESS (bestmode
, MEM_ALIGN (xop0
))
1281 && GET_MODE_BITSIZE (bestmode
) > MEM_ALIGN (xop0
)))
1284 /* Compute offset as multiple of this unit,
1285 counting in bytes. */
1286 unit
= GET_MODE_BITSIZE (bestmode
);
1287 xoffset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
1288 xbitpos
= bitnum
% unit
;
1289 xop0
= adjust_address (xop0
, bestmode
, xoffset
);
1291 /* Fetch it to a register in that size. */
1292 xop0
= force_reg (bestmode
, xop0
);
1294 /* XBITPOS counts within UNIT, which is what is expected. */
1297 /* Get ref to first byte containing part of the field. */
1298 xop0
= adjust_address (xop0
, byte_mode
, xoffset
);
1300 volatile_ok
= save_volatile_ok
;
1303 /* If op0 is a register, we need it in MAXMODE (which is usually
1304 SImode). to make it acceptable to the format of extzv. */
1305 if (GET_CODE (xop0
) == SUBREG
&& GET_MODE (xop0
) != maxmode
)
1307 if (GET_CODE (xop0
) == REG
&& GET_MODE (xop0
) != maxmode
)
1308 xop0
= gen_rtx_SUBREG (maxmode
, xop0
, 0);
1310 /* On big-endian machines, we count bits from the most significant.
1311 If the bit field insn does not, we must invert. */
1312 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
1313 xbitpos
= unit
- bitsize
- xbitpos
;
1315 /* Now convert from counting within UNIT to counting in MAXMODE. */
1316 if (BITS_BIG_ENDIAN
&& GET_CODE (xop0
) != MEM
)
1317 xbitpos
+= GET_MODE_BITSIZE (maxmode
) - unit
;
1319 unit
= GET_MODE_BITSIZE (maxmode
);
1322 || (flag_force_mem
&& GET_CODE (xtarget
) == MEM
))
1323 xtarget
= xspec_target
= gen_reg_rtx (tmode
);
1325 if (GET_MODE (xtarget
) != maxmode
)
1327 if (GET_CODE (xtarget
) == REG
)
1329 int wider
= (GET_MODE_SIZE (maxmode
)
1330 > GET_MODE_SIZE (GET_MODE (xtarget
)));
1331 xtarget
= gen_lowpart (maxmode
, xtarget
);
1333 xspec_target_subreg
= xtarget
;
1336 xtarget
= gen_reg_rtx (maxmode
);
1339 /* If this machine's extzv insists on a register target,
1340 make sure we have one. */
1341 if (! ((*insn_data
[(int) CODE_FOR_extzv
].operand
[0].predicate
)
1342 (xtarget
, maxmode
)))
1343 xtarget
= gen_reg_rtx (maxmode
);
1345 bitsize_rtx
= GEN_INT (bitsize
);
1346 bitpos_rtx
= GEN_INT (xbitpos
);
1348 pat
= gen_extzv (protect_from_queue (xtarget
, 1),
1349 xop0
, bitsize_rtx
, bitpos_rtx
);
1354 spec_target
= xspec_target
;
1355 spec_target_subreg
= xspec_target_subreg
;
1359 delete_insns_since (last
);
1360 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1366 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1372 && (GET_MODE_BITSIZE (extv_mode
) >= bitsize
)
1373 && ! ((GET_CODE (op0
) == REG
|| GET_CODE (op0
) == SUBREG
)
1374 && (bitsize
+ bitpos
> GET_MODE_BITSIZE (extv_mode
))))
1376 int xbitpos
= bitpos
, xoffset
= offset
;
1377 rtx bitsize_rtx
, bitpos_rtx
;
1378 rtx last
= get_last_insn ();
1379 rtx xop0
= op0
, xtarget
= target
;
1380 rtx xspec_target
= spec_target
;
1381 rtx xspec_target_subreg
= spec_target_subreg
;
1383 enum machine_mode maxmode
= mode_for_extraction (EP_extv
, 0);
1385 if (GET_CODE (xop0
) == MEM
)
1387 /* Is the memory operand acceptable? */
1388 if (! ((*insn_data
[(int) CODE_FOR_extv
].operand
[1].predicate
)
1389 (xop0
, GET_MODE (xop0
))))
1391 /* No, load into a reg and extract from there. */
1392 enum machine_mode bestmode
;
1394 /* Get the mode to use for inserting into this field. If
1395 OP0 is BLKmode, get the smallest mode consistent with the
1396 alignment. If OP0 is a non-BLKmode object that is no
1397 wider than MAXMODE, use its mode. Otherwise, use the
1398 smallest mode containing the field. */
1400 if (GET_MODE (xop0
) == BLKmode
1401 || (GET_MODE_SIZE (GET_MODE (op0
))
1402 > GET_MODE_SIZE (maxmode
)))
1403 bestmode
= get_best_mode (bitsize
, bitnum
,
1404 MEM_ALIGN (xop0
), maxmode
,
1405 MEM_VOLATILE_P (xop0
));
1407 bestmode
= GET_MODE (xop0
);
1409 if (bestmode
== VOIDmode
1410 || (SLOW_UNALIGNED_ACCESS (bestmode
, MEM_ALIGN (xop0
))
1411 && GET_MODE_BITSIZE (bestmode
) > MEM_ALIGN (xop0
)))
1414 /* Compute offset as multiple of this unit,
1415 counting in bytes. */
1416 unit
= GET_MODE_BITSIZE (bestmode
);
1417 xoffset
= (bitnum
/ unit
) * GET_MODE_SIZE (bestmode
);
1418 xbitpos
= bitnum
% unit
;
1419 xop0
= adjust_address (xop0
, bestmode
, xoffset
);
1421 /* Fetch it to a register in that size. */
1422 xop0
= force_reg (bestmode
, xop0
);
1424 /* XBITPOS counts within UNIT, which is what is expected. */
1427 /* Get ref to first byte containing part of the field. */
1428 xop0
= adjust_address (xop0
, byte_mode
, xoffset
);
1431 /* If op0 is a register, we need it in MAXMODE (which is usually
1432 SImode) to make it acceptable to the format of extv. */
1433 if (GET_CODE (xop0
) == SUBREG
&& GET_MODE (xop0
) != maxmode
)
1435 if (GET_CODE (xop0
) == REG
&& GET_MODE (xop0
) != maxmode
)
1436 xop0
= gen_rtx_SUBREG (maxmode
, xop0
, 0);
1438 /* On big-endian machines, we count bits from the most significant.
1439 If the bit field insn does not, we must invert. */
1440 if (BITS_BIG_ENDIAN
!= BYTES_BIG_ENDIAN
)
1441 xbitpos
= unit
- bitsize
- xbitpos
;
1443 /* XBITPOS counts within a size of UNIT.
1444 Adjust to count within a size of MAXMODE. */
1445 if (BITS_BIG_ENDIAN
&& GET_CODE (xop0
) != MEM
)
1446 xbitpos
+= (GET_MODE_BITSIZE (maxmode
) - unit
);
1448 unit
= GET_MODE_BITSIZE (maxmode
);
1451 || (flag_force_mem
&& GET_CODE (xtarget
) == MEM
))
1452 xtarget
= xspec_target
= gen_reg_rtx (tmode
);
1454 if (GET_MODE (xtarget
) != maxmode
)
1456 if (GET_CODE (xtarget
) == REG
)
1458 int wider
= (GET_MODE_SIZE (maxmode
)
1459 > GET_MODE_SIZE (GET_MODE (xtarget
)));
1460 xtarget
= gen_lowpart (maxmode
, xtarget
);
1462 xspec_target_subreg
= xtarget
;
1465 xtarget
= gen_reg_rtx (maxmode
);
1468 /* If this machine's extv insists on a register target,
1469 make sure we have one. */
1470 if (! ((*insn_data
[(int) CODE_FOR_extv
].operand
[0].predicate
)
1471 (xtarget
, maxmode
)))
1472 xtarget
= gen_reg_rtx (maxmode
);
1474 bitsize_rtx
= GEN_INT (bitsize
);
1475 bitpos_rtx
= GEN_INT (xbitpos
);
1477 pat
= gen_extv (protect_from_queue (xtarget
, 1),
1478 xop0
, bitsize_rtx
, bitpos_rtx
);
1483 spec_target
= xspec_target
;
1484 spec_target_subreg
= xspec_target_subreg
;
1488 delete_insns_since (last
);
1489 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1495 target
= extract_fixed_bit_field (int_mode
, op0
, offset
, bitsize
,
1498 if (target
== spec_target
)
1500 if (target
== spec_target_subreg
)
1502 if (GET_MODE (target
) != tmode
&& GET_MODE (target
) != mode
)
1504 /* If the target mode is floating-point, first convert to the
1505 integer mode of that size and then access it as a floating-point
1506 value via a SUBREG. */
1507 if (GET_MODE_CLASS (tmode
) == MODE_FLOAT
)
1509 target
= convert_to_mode (mode_for_size (GET_MODE_BITSIZE (tmode
),
1512 if (GET_CODE (target
) != REG
)
1513 target
= copy_to_reg (target
);
1514 return gen_rtx_SUBREG (tmode
, target
, 0);
1517 return convert_to_mode (tmode
, target
, unsignedp
);
1522 /* Extract a bit field using shifts and boolean operations
1523 Returns an rtx to represent the value.
1524 OP0 addresses a register (word) or memory (byte).
1525 BITPOS says which bit within the word or byte the bit field starts in.
1526 OFFSET says how many bytes farther the bit field starts;
1527 it is 0 if OP0 is a register.
1528 BITSIZE says how many bits long the bit field is.
1529 (If OP0 is a register, it may be narrower than a full word,
1530 but BITPOS still counts within a full word,
1531 which is significant on bigendian machines.)
1533 UNSIGNEDP is nonzero for an unsigned bit field (don't sign-extend value).
1534 If TARGET is nonzero, attempts to store the value there
1535 and return TARGET, but this is not guaranteed.
1536 If TARGET is not used, create a pseudo-reg of mode TMODE for the value. */
1539 extract_fixed_bit_field (tmode
, op0
, offset
, bitsize
, bitpos
,
1541 enum machine_mode tmode
;
1543 unsigned HOST_WIDE_INT offset
, bitsize
, bitpos
;
1546 unsigned int total_bits
= BITS_PER_WORD
;
1547 enum machine_mode mode
;
1549 if (GET_CODE (op0
) == SUBREG
|| GET_CODE (op0
) == REG
)
1551 /* Special treatment for a bit field split across two registers. */
1552 if (bitsize
+ bitpos
> BITS_PER_WORD
)
1553 return extract_split_bit_field (op0
, bitsize
, bitpos
, unsignedp
);
1557 /* Get the proper mode to use for this field. We want a mode that
1558 includes the entire field. If such a mode would be larger than
1559 a word, we won't be doing the extraction the normal way. */
1561 mode
= get_best_mode (bitsize
, bitpos
+ offset
* BITS_PER_UNIT
,
1562 MEM_ALIGN (op0
), word_mode
, MEM_VOLATILE_P (op0
));
1564 if (mode
== VOIDmode
)
1565 /* The only way this should occur is if the field spans word
1567 return extract_split_bit_field (op0
, bitsize
,
1568 bitpos
+ offset
* BITS_PER_UNIT
,
1571 total_bits
= GET_MODE_BITSIZE (mode
);
1573 /* Make sure bitpos is valid for the chosen mode. Adjust BITPOS to
1574 be in the range 0 to total_bits-1, and put any excess bytes in
1576 if (bitpos
>= total_bits
)
1578 offset
+= (bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
);
1579 bitpos
-= ((bitpos
/ total_bits
) * (total_bits
/ BITS_PER_UNIT
)
1583 /* Get ref to an aligned byte, halfword, or word containing the field.
1584 Adjust BITPOS to be position within a word,
1585 and OFFSET to be the offset of that word.
1586 Then alter OP0 to refer to that word. */
1587 bitpos
+= (offset
% (total_bits
/ BITS_PER_UNIT
)) * BITS_PER_UNIT
;
1588 offset
-= (offset
% (total_bits
/ BITS_PER_UNIT
));
1589 op0
= adjust_address (op0
, mode
, offset
);
1592 mode
= GET_MODE (op0
);
1594 if (BYTES_BIG_ENDIAN
)
1595 /* BITPOS is the distance between our msb and that of OP0.
1596 Convert it to the distance from the lsb. */
1597 bitpos
= total_bits
- bitsize
- bitpos
;
1599 /* Now BITPOS is always the distance between the field's lsb and that of OP0.
1600 We have reduced the big-endian case to the little-endian case. */
1606 /* If the field does not already start at the lsb,
1607 shift it so it does. */
1608 tree amount
= build_int_2 (bitpos
, 0);
1609 /* Maybe propagate the target for the shift. */
1610 /* But not if we will return it--could confuse integrate.c. */
1611 rtx subtarget
= (target
!= 0 && GET_CODE (target
) == REG
1612 && !REG_FUNCTION_VALUE_P (target
)
1614 if (tmode
!= mode
) subtarget
= 0;
1615 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
1617 /* Convert the value to the desired mode. */
1619 op0
= convert_to_mode (tmode
, op0
, 1);
1621 /* Unless the msb of the field used to be the msb when we shifted,
1622 mask out the upper bits. */
1624 if (GET_MODE_BITSIZE (mode
) != bitpos
+ bitsize
)
1625 return expand_binop (GET_MODE (op0
), and_optab
, op0
,
1626 mask_rtx (GET_MODE (op0
), 0, bitsize
, 0),
1627 target
, 1, OPTAB_LIB_WIDEN
);
1631 /* To extract a signed bit-field, first shift its msb to the msb of the word,
1632 then arithmetic-shift its lsb to the lsb of the word. */
1633 op0
= force_reg (mode
, op0
);
1637 /* Find the narrowest integer mode that contains the field. */
1639 for (mode
= GET_CLASS_NARROWEST_MODE (MODE_INT
); mode
!= VOIDmode
;
1640 mode
= GET_MODE_WIDER_MODE (mode
))
1641 if (GET_MODE_BITSIZE (mode
) >= bitsize
+ bitpos
)
1643 op0
= convert_to_mode (mode
, op0
, 0);
1647 if (GET_MODE_BITSIZE (mode
) != (bitsize
+ bitpos
))
1650 = build_int_2 (GET_MODE_BITSIZE (mode
) - (bitsize
+ bitpos
), 0);
1651 /* Maybe propagate the target for the shift. */
1652 /* But not if we will return the result--could confuse integrate.c. */
1653 rtx subtarget
= (target
!= 0 && GET_CODE (target
) == REG
1654 && ! REG_FUNCTION_VALUE_P (target
)
1656 op0
= expand_shift (LSHIFT_EXPR
, mode
, op0
, amount
, subtarget
, 1);
1659 return expand_shift (RSHIFT_EXPR
, mode
, op0
,
1660 build_int_2 (GET_MODE_BITSIZE (mode
) - bitsize
, 0),
1664 /* Return a constant integer (CONST_INT or CONST_DOUBLE) mask value
1665 of mode MODE with BITSIZE ones followed by BITPOS zeros, or the
1666 complement of that if COMPLEMENT. The mask is truncated if
1667 necessary to the width of mode MODE. The mask is zero-extended if
1668 BITSIZE+BITPOS is too small for MODE. */
1671 mask_rtx (mode
, bitpos
, bitsize
, complement
)
1672 enum machine_mode mode
;
1673 int bitpos
, bitsize
, complement
;
1675 HOST_WIDE_INT masklow
, maskhigh
;
1677 if (bitpos
< HOST_BITS_PER_WIDE_INT
)
1678 masklow
= (HOST_WIDE_INT
) -1 << bitpos
;
1682 if (bitpos
+ bitsize
< HOST_BITS_PER_WIDE_INT
)
1683 masklow
&= ((unsigned HOST_WIDE_INT
) -1
1684 >> (HOST_BITS_PER_WIDE_INT
- bitpos
- bitsize
));
1686 if (bitpos
<= HOST_BITS_PER_WIDE_INT
)
1689 maskhigh
= (HOST_WIDE_INT
) -1 << (bitpos
- HOST_BITS_PER_WIDE_INT
);
1691 if (bitpos
+ bitsize
> HOST_BITS_PER_WIDE_INT
)
1692 maskhigh
&= ((unsigned HOST_WIDE_INT
) -1
1693 >> (2 * HOST_BITS_PER_WIDE_INT
- bitpos
- bitsize
));
1699 maskhigh
= ~maskhigh
;
1703 return immed_double_const (masklow
, maskhigh
, mode
);
1706 /* Return a constant integer (CONST_INT or CONST_DOUBLE) rtx with the value
1707 VALUE truncated to BITSIZE bits and then shifted left BITPOS bits. */
1710 lshift_value (mode
, value
, bitpos
, bitsize
)
1711 enum machine_mode mode
;
1713 int bitpos
, bitsize
;
1715 unsigned HOST_WIDE_INT v
= INTVAL (value
);
1716 HOST_WIDE_INT low
, high
;
1718 if (bitsize
< HOST_BITS_PER_WIDE_INT
)
1719 v
&= ~((HOST_WIDE_INT
) -1 << bitsize
);
1721 if (bitpos
< HOST_BITS_PER_WIDE_INT
)
1724 high
= (bitpos
> 0 ? (v
>> (HOST_BITS_PER_WIDE_INT
- bitpos
)) : 0);
1729 high
= v
<< (bitpos
- HOST_BITS_PER_WIDE_INT
);
1732 return immed_double_const (low
, high
, mode
);
1735 /* Extract a bit field that is split across two words
1736 and return an RTX for the result.
1738 OP0 is the REG, SUBREG or MEM rtx for the first of the two words.
1739 BITSIZE is the field width; BITPOS, position of its first bit, in the word.
1740 UNSIGNEDP is 1 if should zero-extend the contents; else sign-extend. */
1743 extract_split_bit_field (op0
, bitsize
, bitpos
, unsignedp
)
1745 unsigned HOST_WIDE_INT bitsize
, bitpos
;
1749 unsigned int bitsdone
= 0;
1750 rtx result
= NULL_RTX
;
1753 /* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
1755 if (GET_CODE (op0
) == REG
|| GET_CODE (op0
) == SUBREG
)
1756 unit
= BITS_PER_WORD
;
1758 unit
= MIN (MEM_ALIGN (op0
), BITS_PER_WORD
);
1760 while (bitsdone
< bitsize
)
1762 unsigned HOST_WIDE_INT thissize
;
1764 unsigned HOST_WIDE_INT thispos
;
1765 unsigned HOST_WIDE_INT offset
;
1767 offset
= (bitpos
+ bitsdone
) / unit
;
1768 thispos
= (bitpos
+ bitsdone
) % unit
;
1770 /* THISSIZE must not overrun a word boundary. Otherwise,
1771 extract_fixed_bit_field will call us again, and we will mutually
1773 thissize
= MIN (bitsize
- bitsdone
, BITS_PER_WORD
);
1774 thissize
= MIN (thissize
, unit
- thispos
);
1776 /* If OP0 is a register, then handle OFFSET here.
1778 When handling multiword bitfields, extract_bit_field may pass
1779 down a word_mode SUBREG of a larger REG for a bitfield that actually
1780 crosses a word boundary. Thus, for a SUBREG, we must find
1781 the current word starting from the base register. */
1782 if (GET_CODE (op0
) == SUBREG
)
1784 int word_offset
= (SUBREG_BYTE (op0
) / UNITS_PER_WORD
) + offset
;
1785 word
= operand_subword_force (SUBREG_REG (op0
), word_offset
,
1786 GET_MODE (SUBREG_REG (op0
)));
1789 else if (GET_CODE (op0
) == REG
)
1791 word
= operand_subword_force (op0
, offset
, GET_MODE (op0
));
1797 /* Extract the parts in bit-counting order,
1798 whose meaning is determined by BYTES_PER_UNIT.
1799 OFFSET is in UNITs, and UNIT is in bits.
1800 extract_fixed_bit_field wants offset in bytes. */
1801 part
= extract_fixed_bit_field (word_mode
, word
,
1802 offset
* unit
/ BITS_PER_UNIT
,
1803 thissize
, thispos
, 0, 1);
1804 bitsdone
+= thissize
;
1806 /* Shift this part into place for the result. */
1807 if (BYTES_BIG_ENDIAN
)
1809 if (bitsize
!= bitsdone
)
1810 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
1811 build_int_2 (bitsize
- bitsdone
, 0), 0, 1);
1815 if (bitsdone
!= thissize
)
1816 part
= expand_shift (LSHIFT_EXPR
, word_mode
, part
,
1817 build_int_2 (bitsdone
- thissize
, 0), 0, 1);
1823 /* Combine the parts with bitwise or. This works
1824 because we extracted each part as an unsigned bit field. */
1825 result
= expand_binop (word_mode
, ior_optab
, part
, result
, NULL_RTX
, 1,
1831 /* Unsigned bit field: we are done. */
1834 /* Signed bit field: sign-extend with two arithmetic shifts. */
1835 result
= expand_shift (LSHIFT_EXPR
, word_mode
, result
,
1836 build_int_2 (BITS_PER_WORD
- bitsize
, 0),
1838 return expand_shift (RSHIFT_EXPR
, word_mode
, result
,
1839 build_int_2 (BITS_PER_WORD
- bitsize
, 0), NULL_RTX
, 0);
1842 /* Add INC into TARGET. */
1845 expand_inc (target
, inc
)
1848 rtx value
= expand_binop (GET_MODE (target
), add_optab
,
1850 target
, 0, OPTAB_LIB_WIDEN
);
1851 if (value
!= target
)
1852 emit_move_insn (target
, value
);
1855 /* Subtract DEC from TARGET. */
1858 expand_dec (target
, dec
)
1861 rtx value
= expand_binop (GET_MODE (target
), sub_optab
,
1863 target
, 0, OPTAB_LIB_WIDEN
);
1864 if (value
!= target
)
1865 emit_move_insn (target
, value
);
1868 /* Output a shift instruction for expression code CODE,
1869 with SHIFTED being the rtx for the value to shift,
1870 and AMOUNT the tree for the amount to shift by.
1871 Store the result in the rtx TARGET, if that is convenient.
1872 If UNSIGNEDP is nonzero, do a logical shift; otherwise, arithmetic.
1873 Return the rtx for where the value is. */
1876 expand_shift (code
, mode
, shifted
, amount
, target
, unsignedp
)
1877 enum tree_code code
;
1878 enum machine_mode mode
;
1885 int left
= (code
== LSHIFT_EXPR
|| code
== LROTATE_EXPR
);
1886 int rotate
= (code
== LROTATE_EXPR
|| code
== RROTATE_EXPR
);
1889 /* Previously detected shift-counts computed by NEGATE_EXPR
1890 and shifted in the other direction; but that does not work
1893 op1
= expand_expr (amount
, NULL_RTX
, VOIDmode
, 0);
1895 #ifdef SHIFT_COUNT_TRUNCATED
1896 if (SHIFT_COUNT_TRUNCATED
)
1898 if (GET_CODE (op1
) == CONST_INT
1899 && ((unsigned HOST_WIDE_INT
) INTVAL (op1
) >=
1900 (unsigned HOST_WIDE_INT
) GET_MODE_BITSIZE (mode
)))
1901 op1
= GEN_INT ((unsigned HOST_WIDE_INT
) INTVAL (op1
)
1902 % GET_MODE_BITSIZE (mode
));
1903 else if (GET_CODE (op1
) == SUBREG
1904 && SUBREG_BYTE (op1
) == 0)
1905 op1
= SUBREG_REG (op1
);
1909 if (op1
== const0_rtx
)
1912 for (try = 0; temp
== 0 && try < 3; try++)
1914 enum optab_methods methods
;
1917 methods
= OPTAB_DIRECT
;
1919 methods
= OPTAB_WIDEN
;
1921 methods
= OPTAB_LIB_WIDEN
;
1925 /* Widening does not work for rotation. */
1926 if (methods
== OPTAB_WIDEN
)
1928 else if (methods
== OPTAB_LIB_WIDEN
)
1930 /* If we have been unable to open-code this by a rotation,
1931 do it as the IOR of two shifts. I.e., to rotate A
1932 by N bits, compute (A << N) | ((unsigned) A >> (C - N))
1933 where C is the bitsize of A.
1935 It is theoretically possible that the target machine might
1936 not be able to perform either shift and hence we would
1937 be making two libcalls rather than just the one for the
1938 shift (similarly if IOR could not be done). We will allow
1939 this extremely unlikely lossage to avoid complicating the
1942 rtx subtarget
= target
== shifted
? 0 : target
;
1944 tree type
= TREE_TYPE (amount
);
1945 tree new_amount
= make_tree (type
, op1
);
1947 = fold (build (MINUS_EXPR
, type
,
1949 build_int_2 (GET_MODE_BITSIZE (mode
),
1953 shifted
= force_reg (mode
, shifted
);
1955 temp
= expand_shift (left
? LSHIFT_EXPR
: RSHIFT_EXPR
,
1956 mode
, shifted
, new_amount
, subtarget
, 1);
1957 temp1
= expand_shift (left
? RSHIFT_EXPR
: LSHIFT_EXPR
,
1958 mode
, shifted
, other_amount
, 0, 1);
1959 return expand_binop (mode
, ior_optab
, temp
, temp1
, target
,
1960 unsignedp
, methods
);
1963 temp
= expand_binop (mode
,
1964 left
? rotl_optab
: rotr_optab
,
1965 shifted
, op1
, target
, unsignedp
, methods
);
1967 /* If we don't have the rotate, but we are rotating by a constant
1968 that is in range, try a rotate in the opposite direction. */
1970 if (temp
== 0 && GET_CODE (op1
) == CONST_INT
1972 && (unsigned int) INTVAL (op1
) < GET_MODE_BITSIZE (mode
))
1973 temp
= expand_binop (mode
,
1974 left
? rotr_optab
: rotl_optab
,
1976 GEN_INT (GET_MODE_BITSIZE (mode
)
1978 target
, unsignedp
, methods
);
1981 temp
= expand_binop (mode
,
1982 left
? ashl_optab
: lshr_optab
,
1983 shifted
, op1
, target
, unsignedp
, methods
);
1985 /* Do arithmetic shifts.
1986 Also, if we are going to widen the operand, we can just as well
1987 use an arithmetic right-shift instead of a logical one. */
1988 if (temp
== 0 && ! rotate
1989 && (! unsignedp
|| (! left
&& methods
== OPTAB_WIDEN
)))
1991 enum optab_methods methods1
= methods
;
1993 /* If trying to widen a log shift to an arithmetic shift,
1994 don't accept an arithmetic shift of the same size. */
1996 methods1
= OPTAB_MUST_WIDEN
;
1998 /* Arithmetic shift */
2000 temp
= expand_binop (mode
,
2001 left
? ashl_optab
: ashr_optab
,
2002 shifted
, op1
, target
, unsignedp
, methods1
);
2005 /* We used to try extzv here for logical right shifts, but that was
2006 only useful for one machine, the VAX, and caused poor code
2007 generation there for lshrdi3, so the code was deleted and a
2008 define_expand for lshrsi3 was added to vax.md. */
2016 enum alg_code
{ alg_zero
, alg_m
, alg_shift
,
2017 alg_add_t_m2
, alg_sub_t_m2
,
2018 alg_add_factor
, alg_sub_factor
,
2019 alg_add_t2_m
, alg_sub_t2_m
,
2020 alg_add
, alg_subtract
, alg_factor
, alg_shiftop
};
2022 /* This structure records a sequence of operations.
2023 `ops' is the number of operations recorded.
2024 `cost' is their total cost.
2025 The operations are stored in `op' and the corresponding
2026 logarithms of the integer coefficients in `log'.
2028 These are the operations:
2029 alg_zero total := 0;
2030 alg_m total := multiplicand;
2031 alg_shift total := total * coeff
2032 alg_add_t_m2 total := total + multiplicand * coeff;
2033 alg_sub_t_m2 total := total - multiplicand * coeff;
2034 alg_add_factor total := total * coeff + total;
2035 alg_sub_factor total := total * coeff - total;
2036 alg_add_t2_m total := total * coeff + multiplicand;
2037 alg_sub_t2_m total := total * coeff - multiplicand;
2039 The first operand must be either alg_zero or alg_m. */
2045 /* The size of the OP and LOG fields are not directly related to the
2046 word size, but the worst-case algorithms will be if we have few
2047 consecutive ones or zeros, i.e., a multiplicand like 10101010101...
2048 In that case we will generate shift-by-2, add, shift-by-2, add,...,
2049 in total wordsize operations. */
2050 enum alg_code op
[MAX_BITS_PER_WORD
];
2051 char log
[MAX_BITS_PER_WORD
];
2054 static void synth_mult
PARAMS ((struct algorithm
*,
2055 unsigned HOST_WIDE_INT
,
2057 static unsigned HOST_WIDE_INT choose_multiplier
PARAMS ((unsigned HOST_WIDE_INT
,
2059 unsigned HOST_WIDE_INT
*,
2061 static unsigned HOST_WIDE_INT invert_mod2n
PARAMS ((unsigned HOST_WIDE_INT
,
2063 /* Compute and return the best algorithm for multiplying by T.
2064 The algorithm must cost less than cost_limit
2065 If retval.cost >= COST_LIMIT, no algorithm was found and all
2066 other field of the returned struct are undefined. */
2069 synth_mult (alg_out
, t
, cost_limit
)
2070 struct algorithm
*alg_out
;
2071 unsigned HOST_WIDE_INT t
;
2075 struct algorithm
*alg_in
, *best_alg
;
2077 unsigned HOST_WIDE_INT q
;
2079 /* Indicate that no algorithm is yet found. If no algorithm
2080 is found, this value will be returned and indicate failure. */
2081 alg_out
->cost
= cost_limit
;
2083 if (cost_limit
<= 0)
2086 /* t == 1 can be done in zero cost. */
2091 alg_out
->op
[0] = alg_m
;
2095 /* t == 0 sometimes has a cost. If it does and it exceeds our limit,
2099 if (zero_cost
>= cost_limit
)
2104 alg_out
->cost
= zero_cost
;
2105 alg_out
->op
[0] = alg_zero
;
2110 /* We'll be needing a couple extra algorithm structures now. */
2112 alg_in
= (struct algorithm
*)alloca (sizeof (struct algorithm
));
2113 best_alg
= (struct algorithm
*)alloca (sizeof (struct algorithm
));
2115 /* If we have a group of zero bits at the low-order part of T, try
2116 multiplying by the remaining bits and then doing a shift. */
2120 m
= floor_log2 (t
& -t
); /* m = number of low zero bits */
2121 if (m
< BITS_PER_WORD
)
2124 cost
= shift_cost
[m
];
2125 synth_mult (alg_in
, q
, cost_limit
- cost
);
2127 cost
+= alg_in
->cost
;
2128 if (cost
< cost_limit
)
2130 struct algorithm
*x
;
2131 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2132 best_alg
->log
[best_alg
->ops
] = m
;
2133 best_alg
->op
[best_alg
->ops
] = alg_shift
;
2139 /* If we have an odd number, add or subtract one. */
2142 unsigned HOST_WIDE_INT w
;
2144 for (w
= 1; (w
& t
) != 0; w
<<= 1)
2146 /* If T was -1, then W will be zero after the loop. This is another
2147 case where T ends with ...111. Handling this with (T + 1) and
2148 subtract 1 produces slightly better code and results in algorithm
2149 selection much faster than treating it like the ...0111 case
2153 /* Reject the case where t is 3.
2154 Thus we prefer addition in that case. */
2157 /* T ends with ...111. Multiply by (T + 1) and subtract 1. */
2160 synth_mult (alg_in
, t
+ 1, cost_limit
- cost
);
2162 cost
+= alg_in
->cost
;
2163 if (cost
< cost_limit
)
2165 struct algorithm
*x
;
2166 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2167 best_alg
->log
[best_alg
->ops
] = 0;
2168 best_alg
->op
[best_alg
->ops
] = alg_sub_t_m2
;
2174 /* T ends with ...01 or ...011. Multiply by (T - 1) and add 1. */
2177 synth_mult (alg_in
, t
- 1, cost_limit
- cost
);
2179 cost
+= alg_in
->cost
;
2180 if (cost
< cost_limit
)
2182 struct algorithm
*x
;
2183 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2184 best_alg
->log
[best_alg
->ops
] = 0;
2185 best_alg
->op
[best_alg
->ops
] = alg_add_t_m2
;
2191 /* Look for factors of t of the form
2192 t = q(2**m +- 1), 2 <= m <= floor(log2(t - 1)).
2193 If we find such a factor, we can multiply by t using an algorithm that
2194 multiplies by q, shift the result by m and add/subtract it to itself.
2196 We search for large factors first and loop down, even if large factors
2197 are less probable than small; if we find a large factor we will find a
2198 good sequence quickly, and therefore be able to prune (by decreasing
2199 COST_LIMIT) the search. */
2201 for (m
= floor_log2 (t
- 1); m
>= 2; m
--)
2203 unsigned HOST_WIDE_INT d
;
2205 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) + 1;
2206 if (t
% d
== 0 && t
> d
&& m
< BITS_PER_WORD
)
2208 cost
= MIN (shiftadd_cost
[m
], add_cost
+ shift_cost
[m
]);
2209 synth_mult (alg_in
, t
/ d
, cost_limit
- cost
);
2211 cost
+= alg_in
->cost
;
2212 if (cost
< cost_limit
)
2214 struct algorithm
*x
;
2215 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2216 best_alg
->log
[best_alg
->ops
] = m
;
2217 best_alg
->op
[best_alg
->ops
] = alg_add_factor
;
2220 /* Other factors will have been taken care of in the recursion. */
2224 d
= ((unsigned HOST_WIDE_INT
) 1 << m
) - 1;
2225 if (t
% d
== 0 && t
> d
&& m
< BITS_PER_WORD
)
2227 cost
= MIN (shiftsub_cost
[m
], add_cost
+ shift_cost
[m
]);
2228 synth_mult (alg_in
, t
/ d
, cost_limit
- cost
);
2230 cost
+= alg_in
->cost
;
2231 if (cost
< cost_limit
)
2233 struct algorithm
*x
;
2234 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2235 best_alg
->log
[best_alg
->ops
] = m
;
2236 best_alg
->op
[best_alg
->ops
] = alg_sub_factor
;
2243 /* Try shift-and-add (load effective address) instructions,
2244 i.e. do a*3, a*5, a*9. */
2250 if (m
>= 0 && m
< BITS_PER_WORD
)
2252 cost
= shiftadd_cost
[m
];
2253 synth_mult (alg_in
, (t
- 1) >> m
, cost_limit
- cost
);
2255 cost
+= alg_in
->cost
;
2256 if (cost
< cost_limit
)
2258 struct algorithm
*x
;
2259 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2260 best_alg
->log
[best_alg
->ops
] = m
;
2261 best_alg
->op
[best_alg
->ops
] = alg_add_t2_m
;
2269 if (m
>= 0 && m
< BITS_PER_WORD
)
2271 cost
= shiftsub_cost
[m
];
2272 synth_mult (alg_in
, (t
+ 1) >> m
, cost_limit
- cost
);
2274 cost
+= alg_in
->cost
;
2275 if (cost
< cost_limit
)
2277 struct algorithm
*x
;
2278 x
= alg_in
, alg_in
= best_alg
, best_alg
= x
;
2279 best_alg
->log
[best_alg
->ops
] = m
;
2280 best_alg
->op
[best_alg
->ops
] = alg_sub_t2_m
;
2286 /* If cost_limit has not decreased since we stored it in alg_out->cost,
2287 we have not found any algorithm. */
2288 if (cost_limit
== alg_out
->cost
)
2291 /* If we are getting a too long sequence for `struct algorithm'
2292 to record, make this search fail. */
2293 if (best_alg
->ops
== MAX_BITS_PER_WORD
)
2296 /* Copy the algorithm from temporary space to the space at alg_out.
2297 We avoid using structure assignment because the majority of
2298 best_alg is normally undefined, and this is a critical function. */
2299 alg_out
->ops
= best_alg
->ops
+ 1;
2300 alg_out
->cost
= cost_limit
;
2301 memcpy (alg_out
->op
, best_alg
->op
,
2302 alg_out
->ops
* sizeof *alg_out
->op
);
2303 memcpy (alg_out
->log
, best_alg
->log
,
2304 alg_out
->ops
* sizeof *alg_out
->log
);
2307 /* Perform a multiplication and return an rtx for the result.
2308 MODE is mode of value; OP0 and OP1 are what to multiply (rtx's);
2309 TARGET is a suggestion for where to store the result (an rtx).
2311 We check specially for a constant integer as OP1.
2312 If you want this check for OP0 as well, then before calling
2313 you should swap the two operands if OP0 would be constant. */
2316 expand_mult (mode
, op0
, op1
, target
, unsignedp
)
2317 enum machine_mode mode
;
2318 rtx op0
, op1
, target
;
2321 rtx const_op1
= op1
;
2323 /* synth_mult does an `unsigned int' multiply. As long as the mode is
2324 less than or equal in size to `unsigned int' this doesn't matter.
2325 If the mode is larger than `unsigned int', then synth_mult works only
2326 if the constant value exactly fits in an `unsigned int' without any
2327 truncation. This means that multiplying by negative values does
2328 not work; results are off by 2^32 on a 32 bit machine. */
2330 /* If we are multiplying in DImode, it may still be a win
2331 to try to work with shifts and adds. */
2332 if (GET_CODE (op1
) == CONST_DOUBLE
2333 && GET_MODE_CLASS (GET_MODE (op1
)) == MODE_INT
2334 && HOST_BITS_PER_INT
>= BITS_PER_WORD
2335 && CONST_DOUBLE_HIGH (op1
) == 0)
2336 const_op1
= GEN_INT (CONST_DOUBLE_LOW (op1
));
2337 else if (HOST_BITS_PER_INT
< GET_MODE_BITSIZE (mode
)
2338 && GET_CODE (op1
) == CONST_INT
2339 && INTVAL (op1
) < 0)
2342 /* We used to test optimize here, on the grounds that it's better to
2343 produce a smaller program when -O is not used.
2344 But this causes such a terrible slowdown sometimes
2345 that it seems better to use synth_mult always. */
2347 if (const_op1
&& GET_CODE (const_op1
) == CONST_INT
2348 && (unsignedp
|| ! flag_trapv
))
2350 struct algorithm alg
;
2351 struct algorithm alg2
;
2352 HOST_WIDE_INT val
= INTVAL (op1
);
2353 HOST_WIDE_INT val_so_far
;
2356 enum {basic_variant
, negate_variant
, add_variant
} variant
= basic_variant
;
2358 /* op0 must be register to make mult_cost match the precomputed
2359 shiftadd_cost array. */
2360 op0
= force_reg (mode
, op0
);
2362 /* Try to do the computation three ways: multiply by the negative of OP1
2363 and then negate, do the multiplication directly, or do multiplication
2366 mult_cost
= rtx_cost (gen_rtx_MULT (mode
, op0
, op1
), SET
);
2367 mult_cost
= MIN (12 * add_cost
, mult_cost
);
2369 synth_mult (&alg
, val
, mult_cost
);
2371 /* This works only if the inverted value actually fits in an
2373 if (HOST_BITS_PER_INT
>= GET_MODE_BITSIZE (mode
))
2375 synth_mult (&alg2
, - val
,
2376 (alg
.cost
< mult_cost
? alg
.cost
: mult_cost
) - negate_cost
);
2377 if (alg2
.cost
+ negate_cost
< alg
.cost
)
2378 alg
= alg2
, variant
= negate_variant
;
2381 /* This proves very useful for division-by-constant. */
2382 synth_mult (&alg2
, val
- 1,
2383 (alg
.cost
< mult_cost
? alg
.cost
: mult_cost
) - add_cost
);
2384 if (alg2
.cost
+ add_cost
< alg
.cost
)
2385 alg
= alg2
, variant
= add_variant
;
2387 if (alg
.cost
< mult_cost
)
2389 /* We found something cheaper than a multiply insn. */
2392 enum machine_mode nmode
;
2394 op0
= protect_from_queue (op0
, 0);
2396 /* Avoid referencing memory over and over.
2397 For speed, but also for correctness when mem is volatile. */
2398 if (GET_CODE (op0
) == MEM
)
2399 op0
= force_reg (mode
, op0
);
2401 /* ACCUM starts out either as OP0 or as a zero, depending on
2402 the first operation. */
2404 if (alg
.op
[0] == alg_zero
)
2406 accum
= copy_to_mode_reg (mode
, const0_rtx
);
2409 else if (alg
.op
[0] == alg_m
)
2411 accum
= copy_to_mode_reg (mode
, op0
);
2417 for (opno
= 1; opno
< alg
.ops
; opno
++)
2419 int log
= alg
.log
[opno
];
2420 int preserve
= preserve_subexpressions_p ();
2421 rtx shift_subtarget
= preserve
? 0 : accum
;
2423 = (opno
== alg
.ops
- 1 && target
!= 0 && variant
!= add_variant
2426 rtx accum_target
= preserve
? 0 : accum
;
2428 switch (alg
.op
[opno
])
2431 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2432 build_int_2 (log
, 0), NULL_RTX
, 0);
2437 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
,
2438 build_int_2 (log
, 0), NULL_RTX
, 0);
2439 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
2441 ? add_target
: accum_target
);
2442 val_so_far
+= (HOST_WIDE_INT
) 1 << log
;
2446 tem
= expand_shift (LSHIFT_EXPR
, mode
, op0
,
2447 build_int_2 (log
, 0), NULL_RTX
, 0);
2448 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, tem
),
2450 ? add_target
: accum_target
);
2451 val_so_far
-= (HOST_WIDE_INT
) 1 << log
;
2455 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2456 build_int_2 (log
, 0), shift_subtarget
,
2458 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
),
2460 ? add_target
: accum_target
);
2461 val_so_far
= (val_so_far
<< log
) + 1;
2465 accum
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2466 build_int_2 (log
, 0), shift_subtarget
,
2468 accum
= force_operand (gen_rtx_MINUS (mode
, accum
, op0
),
2470 ? add_target
: accum_target
);
2471 val_so_far
= (val_so_far
<< log
) - 1;
2474 case alg_add_factor
:
2475 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2476 build_int_2 (log
, 0), NULL_RTX
, 0);
2477 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, tem
),
2479 ? add_target
: accum_target
);
2480 val_so_far
+= val_so_far
<< log
;
2483 case alg_sub_factor
:
2484 tem
= expand_shift (LSHIFT_EXPR
, mode
, accum
,
2485 build_int_2 (log
, 0), NULL_RTX
, 0);
2486 accum
= force_operand (gen_rtx_MINUS (mode
, tem
, accum
),
2487 (add_target
? add_target
2488 : preserve
? 0 : tem
));
2489 val_so_far
= (val_so_far
<< log
) - val_so_far
;
2496 /* Write a REG_EQUAL note on the last insn so that we can cse
2497 multiplication sequences. Note that if ACCUM is a SUBREG,
2498 we've set the inner register and must properly indicate
2501 tem
= op0
, nmode
= mode
;
2502 if (GET_CODE (accum
) == SUBREG
)
2504 nmode
= GET_MODE (SUBREG_REG (accum
));
2505 tem
= gen_lowpart (nmode
, op0
);
2508 insn
= get_last_insn ();
2509 set_unique_reg_note (insn
,
2511 gen_rtx_MULT (nmode
, tem
,
2512 GEN_INT (val_so_far
)));
2515 if (variant
== negate_variant
)
2517 val_so_far
= - val_so_far
;
2518 accum
= expand_unop (mode
, neg_optab
, accum
, target
, 0);
2520 else if (variant
== add_variant
)
2522 val_so_far
= val_so_far
+ 1;
2523 accum
= force_operand (gen_rtx_PLUS (mode
, accum
, op0
), target
);
2526 if (val
!= val_so_far
)
2533 /* This used to use umul_optab if unsigned, but for non-widening multiply
2534 there is no difference between signed and unsigned. */
2535 op0
= expand_binop (mode
,
2537 && flag_trapv
&& (GET_MODE_CLASS(mode
) == MODE_INT
)
2538 ? smulv_optab
: smul_optab
,
2539 op0
, op1
, target
, unsignedp
, OPTAB_LIB_WIDEN
);
2545 /* Return the smallest n such that 2**n >= X. */
2549 unsigned HOST_WIDE_INT x
;
2551 return floor_log2 (x
- 1) + 1;
2554 /* Choose a minimal N + 1 bit approximation to 1/D that can be used to
2555 replace division by D, and put the least significant N bits of the result
2556 in *MULTIPLIER_PTR and return the most significant bit.
2558 The width of operations is N (should be <= HOST_BITS_PER_WIDE_INT), the
2559 needed precision is in PRECISION (should be <= N).
2561 PRECISION should be as small as possible so this function can choose
2562 multiplier more freely.
2564 The rounded-up logarithm of D is placed in *lgup_ptr. A shift count that
2565 is to be used for a final right shift is placed in *POST_SHIFT_PTR.
2567 Using this function, x/D will be equal to (x * m) >> (*POST_SHIFT_PTR),
2568 where m is the full HOST_BITS_PER_WIDE_INT + 1 bit multiplier. */
2571 unsigned HOST_WIDE_INT
2572 choose_multiplier (d
, n
, precision
, multiplier_ptr
, post_shift_ptr
, lgup_ptr
)
2573 unsigned HOST_WIDE_INT d
;
2576 unsigned HOST_WIDE_INT
*multiplier_ptr
;
2577 int *post_shift_ptr
;
2580 HOST_WIDE_INT mhigh_hi
, mlow_hi
;
2581 unsigned HOST_WIDE_INT mhigh_lo
, mlow_lo
;
2582 int lgup
, post_shift
;
2584 unsigned HOST_WIDE_INT nl
, dummy1
;
2585 HOST_WIDE_INT nh
, dummy2
;
2587 /* lgup = ceil(log2(divisor)); */
2588 lgup
= ceil_log2 (d
);
2594 pow2
= n
+ lgup
- precision
;
2596 if (pow
== 2 * HOST_BITS_PER_WIDE_INT
)
2598 /* We could handle this with some effort, but this case is much better
2599 handled directly with a scc insn, so rely on caller using that. */
2603 /* mlow = 2^(N + lgup)/d */
2604 if (pow
>= HOST_BITS_PER_WIDE_INT
)
2606 nh
= (HOST_WIDE_INT
) 1 << (pow
- HOST_BITS_PER_WIDE_INT
);
2612 nl
= (unsigned HOST_WIDE_INT
) 1 << pow
;
2614 div_and_round_double (TRUNC_DIV_EXPR
, 1, nl
, nh
, d
, (HOST_WIDE_INT
) 0,
2615 &mlow_lo
, &mlow_hi
, &dummy1
, &dummy2
);
2617 /* mhigh = (2^(N + lgup) + 2^N + lgup - precision)/d */
2618 if (pow2
>= HOST_BITS_PER_WIDE_INT
)
2619 nh
|= (HOST_WIDE_INT
) 1 << (pow2
- HOST_BITS_PER_WIDE_INT
);
2621 nl
|= (unsigned HOST_WIDE_INT
) 1 << pow2
;
2622 div_and_round_double (TRUNC_DIV_EXPR
, 1, nl
, nh
, d
, (HOST_WIDE_INT
) 0,
2623 &mhigh_lo
, &mhigh_hi
, &dummy1
, &dummy2
);
2625 if (mhigh_hi
&& nh
- d
>= d
)
2627 if (mhigh_hi
> 1 || mlow_hi
> 1)
2629 /* assert that mlow < mhigh. */
2630 if (! (mlow_hi
< mhigh_hi
|| (mlow_hi
== mhigh_hi
&& mlow_lo
< mhigh_lo
)))
2633 /* If precision == N, then mlow, mhigh exceed 2^N
2634 (but they do not exceed 2^(N+1)). */
2636 /* Reduce to lowest terms */
2637 for (post_shift
= lgup
; post_shift
> 0; post_shift
--)
2639 unsigned HOST_WIDE_INT ml_lo
= (mlow_hi
<< (HOST_BITS_PER_WIDE_INT
- 1)) | (mlow_lo
>> 1);
2640 unsigned HOST_WIDE_INT mh_lo
= (mhigh_hi
<< (HOST_BITS_PER_WIDE_INT
- 1)) | (mhigh_lo
>> 1);
2650 *post_shift_ptr
= post_shift
;
2652 if (n
< HOST_BITS_PER_WIDE_INT
)
2654 unsigned HOST_WIDE_INT mask
= ((unsigned HOST_WIDE_INT
) 1 << n
) - 1;
2655 *multiplier_ptr
= mhigh_lo
& mask
;
2656 return mhigh_lo
>= mask
;
2660 *multiplier_ptr
= mhigh_lo
;
2665 /* Compute the inverse of X mod 2**n, i.e., find Y such that X * Y is
2666 congruent to 1 (mod 2**N). */
2668 static unsigned HOST_WIDE_INT
2670 unsigned HOST_WIDE_INT x
;
2673 /* Solve x*y == 1 (mod 2^n), where x is odd. Return y. */
2675 /* The algorithm notes that the choice y = x satisfies
2676 x*y == 1 mod 2^3, since x is assumed odd.
2677 Each iteration doubles the number of bits of significance in y. */
2679 unsigned HOST_WIDE_INT mask
;
2680 unsigned HOST_WIDE_INT y
= x
;
2683 mask
= (n
== HOST_BITS_PER_WIDE_INT
2684 ? ~(unsigned HOST_WIDE_INT
) 0
2685 : ((unsigned HOST_WIDE_INT
) 1 << n
) - 1);
2689 y
= y
* (2 - x
*y
) & mask
; /* Modulo 2^N */
2695 /* Emit code to adjust ADJ_OPERAND after multiplication of wrong signedness
2696 flavor of OP0 and OP1. ADJ_OPERAND is already the high half of the
2697 product OP0 x OP1. If UNSIGNEDP is nonzero, adjust the signed product
2698 to become unsigned, if UNSIGNEDP is zero, adjust the unsigned product to
2701 The result is put in TARGET if that is convenient.
2703 MODE is the mode of operation. */
2706 expand_mult_highpart_adjust (mode
, adj_operand
, op0
, op1
, target
, unsignedp
)
2707 enum machine_mode mode
;
2708 rtx adj_operand
, op0
, op1
, target
;
2712 enum rtx_code adj_code
= unsignedp
? PLUS
: MINUS
;
2714 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
2715 build_int_2 (GET_MODE_BITSIZE (mode
) - 1, 0),
2717 tem
= expand_and (tem
, op1
, NULL_RTX
);
2719 = force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
2722 tem
= expand_shift (RSHIFT_EXPR
, mode
, op1
,
2723 build_int_2 (GET_MODE_BITSIZE (mode
) - 1, 0),
2725 tem
= expand_and (tem
, op0
, NULL_RTX
);
2726 target
= force_operand (gen_rtx_fmt_ee (adj_code
, mode
, adj_operand
, tem
),
2732 /* Emit code to multiply OP0 and CNST1, putting the high half of the result
2733 in TARGET if that is convenient, and return where the result is. If the
2734 operation can not be performed, 0 is returned.
2736 MODE is the mode of operation and result.
2738 UNSIGNEDP nonzero means unsigned multiply.
2740 MAX_COST is the total allowed cost for the expanded RTL. */
2743 expand_mult_highpart (mode
, op0
, cnst1
, target
, unsignedp
, max_cost
)
2744 enum machine_mode mode
;
2746 unsigned HOST_WIDE_INT cnst1
;
2750 enum machine_mode wider_mode
= GET_MODE_WIDER_MODE (mode
);
2751 optab mul_highpart_optab
;
2754 int size
= GET_MODE_BITSIZE (mode
);
2757 /* We can't support modes wider than HOST_BITS_PER_INT. */
2758 if (size
> HOST_BITS_PER_WIDE_INT
)
2761 op1
= GEN_INT (trunc_int_for_mode (cnst1
, mode
));
2764 = immed_double_const (cnst1
,
2767 : -(cnst1
>> (HOST_BITS_PER_WIDE_INT
- 1))),
2770 /* expand_mult handles constant multiplication of word_mode
2771 or narrower. It does a poor job for large modes. */
2772 if (size
< BITS_PER_WORD
2773 && mul_cost
[(int) wider_mode
] + shift_cost
[size
-1] < max_cost
)
2775 /* We have to do this, since expand_binop doesn't do conversion for
2776 multiply. Maybe change expand_binop to handle widening multiply? */
2777 op0
= convert_to_mode (wider_mode
, op0
, unsignedp
);
2779 /* We know that this can't have signed overflow, so pretend this is
2780 an unsigned multiply. */
2781 tem
= expand_mult (wider_mode
, op0
, wide_op1
, NULL_RTX
, 0);
2782 tem
= expand_shift (RSHIFT_EXPR
, wider_mode
, tem
,
2783 build_int_2 (size
, 0), NULL_RTX
, 1);
2784 return convert_modes (mode
, wider_mode
, tem
, unsignedp
);
2788 target
= gen_reg_rtx (mode
);
2790 /* Firstly, try using a multiplication insn that only generates the needed
2791 high part of the product, and in the sign flavor of unsignedp. */
2792 if (mul_highpart_cost
[(int) mode
] < max_cost
)
2794 mul_highpart_optab
= unsignedp
? umul_highpart_optab
: smul_highpart_optab
;
2795 target
= expand_binop (mode
, mul_highpart_optab
,
2796 op0
, op1
, target
, unsignedp
, OPTAB_DIRECT
);
2801 /* Secondly, same as above, but use sign flavor opposite of unsignedp.
2802 Need to adjust the result after the multiplication. */
2803 if (size
- 1 < BITS_PER_WORD
2804 && (mul_highpart_cost
[(int) mode
] + 2 * shift_cost
[size
-1] + 4 * add_cost
2807 mul_highpart_optab
= unsignedp
? smul_highpart_optab
: umul_highpart_optab
;
2808 target
= expand_binop (mode
, mul_highpart_optab
,
2809 op0
, op1
, target
, unsignedp
, OPTAB_DIRECT
);
2811 /* We used the wrong signedness. Adjust the result. */
2812 return expand_mult_highpart_adjust (mode
, target
, op0
,
2813 op1
, target
, unsignedp
);
2816 /* Try widening multiplication. */
2817 moptab
= unsignedp
? umul_widen_optab
: smul_widen_optab
;
2818 if (moptab
->handlers
[(int) wider_mode
].insn_code
!= CODE_FOR_nothing
2819 && mul_widen_cost
[(int) wider_mode
] < max_cost
)
2821 op1
= force_reg (mode
, op1
);
2825 /* Try widening the mode and perform a non-widening multiplication. */
2826 moptab
= smul_optab
;
2827 if (smul_optab
->handlers
[(int) wider_mode
].insn_code
!= CODE_FOR_nothing
2828 && size
- 1 < BITS_PER_WORD
2829 && mul_cost
[(int) wider_mode
] + shift_cost
[size
-1] < max_cost
)
2835 /* Try widening multiplication of opposite signedness, and adjust. */
2836 moptab
= unsignedp
? smul_widen_optab
: umul_widen_optab
;
2837 if (moptab
->handlers
[(int) wider_mode
].insn_code
!= CODE_FOR_nothing
2838 && size
- 1 < BITS_PER_WORD
2839 && (mul_widen_cost
[(int) wider_mode
]
2840 + 2 * shift_cost
[size
-1] + 4 * add_cost
< max_cost
))
2842 rtx regop1
= force_reg (mode
, op1
);
2843 tem
= expand_binop (wider_mode
, moptab
, op0
, regop1
,
2844 NULL_RTX
, ! unsignedp
, OPTAB_WIDEN
);
2847 /* Extract the high half of the just generated product. */
2848 tem
= expand_shift (RSHIFT_EXPR
, wider_mode
, tem
,
2849 build_int_2 (size
, 0), NULL_RTX
, 1);
2850 tem
= convert_modes (mode
, wider_mode
, tem
, unsignedp
);
2851 /* We used the wrong signedness. Adjust the result. */
2852 return expand_mult_highpart_adjust (mode
, tem
, op0
, op1
,
2860 /* Pass NULL_RTX as target since TARGET has wrong mode. */
2861 tem
= expand_binop (wider_mode
, moptab
, op0
, op1
,
2862 NULL_RTX
, unsignedp
, OPTAB_WIDEN
);
2866 /* Extract the high half of the just generated product. */
2867 if (mode
== word_mode
)
2869 return gen_highpart (mode
, tem
);
2873 tem
= expand_shift (RSHIFT_EXPR
, wider_mode
, tem
,
2874 build_int_2 (size
, 0), NULL_RTX
, 1);
2875 return convert_modes (mode
, wider_mode
, tem
, unsignedp
);
2879 /* Emit the code to divide OP0 by OP1, putting the result in TARGET
2880 if that is convenient, and returning where the result is.
2881 You may request either the quotient or the remainder as the result;
2882 specify REM_FLAG nonzero to get the remainder.
2884 CODE is the expression code for which kind of division this is;
2885 it controls how rounding is done. MODE is the machine mode to use.
2886 UNSIGNEDP nonzero means do unsigned division. */
2888 /* ??? For CEIL_MOD_EXPR, can compute incorrect remainder with ANDI
2889 and then correct it by or'ing in missing high bits
2890 if result of ANDI is nonzero.
2891 For ROUND_MOD_EXPR, can use ANDI and then sign-extend the result.
2892 This could optimize to a bfexts instruction.
2893 But C doesn't use these operations, so their optimizations are
2895 /* ??? For modulo, we don't actually need the highpart of the first product,
2896 the low part will do nicely. And for small divisors, the second multiply
2897 can also be a low-part only multiply or even be completely left out.
2898 E.g. to calculate the remainder of a division by 3 with a 32 bit
2899 multiply, multiply with 0x55555556 and extract the upper two bits;
2900 the result is exact for inputs up to 0x1fffffff.
2901 The input range can be reduced by using cross-sum rules.
2902 For odd divisors >= 3, the following table gives right shift counts
2903 so that if an number is shifted by an integer multiple of the given
2904 amount, the remainder stays the same:
2905 2, 4, 3, 6, 10, 12, 4, 8, 18, 6, 11, 20, 18, 0, 5, 10, 12, 0, 12, 20,
2906 14, 12, 23, 21, 8, 0, 20, 18, 0, 0, 6, 12, 0, 22, 0, 18, 20, 30, 0, 0,
2907 0, 8, 0, 11, 12, 10, 36, 0, 30, 0, 0, 12, 0, 0, 0, 0, 44, 12, 24, 0,
2908 20, 0, 7, 14, 0, 18, 36, 0, 0, 46, 60, 0, 42, 0, 15, 24, 20, 0, 0, 33,
2909 0, 20, 0, 0, 18, 0, 60, 0, 0, 0, 0, 0, 40, 18, 0, 0, 12
2911 Cross-sum rules for even numbers can be derived by leaving as many bits
2912 to the right alone as the divisor has zeros to the right.
2913 E.g. if x is an unsigned 32 bit number:
2914 (x mod 12) == (((x & 1023) + ((x >> 8) & ~3)) * 0x15555558 >> 2 * 3) >> 28
2917 #define EXACT_POWER_OF_2_OR_ZERO_P(x) (((x) & ((x) - 1)) == 0)
2920 expand_divmod (rem_flag
, code
, mode
, op0
, op1
, target
, unsignedp
)
2922 enum tree_code code
;
2923 enum machine_mode mode
;
2924 rtx op0
, op1
, target
;
2927 enum machine_mode compute_mode
;
2929 rtx quotient
= 0, remainder
= 0;
2933 optab optab1
, optab2
;
2934 int op1_is_constant
, op1_is_pow2
;
2935 int max_cost
, extra_cost
;
2936 static HOST_WIDE_INT last_div_const
= 0;
2938 op1_is_constant
= GET_CODE (op1
) == CONST_INT
;
2939 op1_is_pow2
= (op1_is_constant
2940 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
2941 || (! unsignedp
&& EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1
))))));
2944 This is the structure of expand_divmod:
2946 First comes code to fix up the operands so we can perform the operations
2947 correctly and efficiently.
2949 Second comes a switch statement with code specific for each rounding mode.
2950 For some special operands this code emits all RTL for the desired
2951 operation, for other cases, it generates only a quotient and stores it in
2952 QUOTIENT. The case for trunc division/remainder might leave quotient = 0,
2953 to indicate that it has not done anything.
2955 Last comes code that finishes the operation. If QUOTIENT is set and
2956 REM_FLAG is set, the remainder is computed as OP0 - QUOTIENT * OP1. If
2957 QUOTIENT is not set, it is computed using trunc rounding.
2959 We try to generate special code for division and remainder when OP1 is a
2960 constant. If |OP1| = 2**n we can use shifts and some other fast
2961 operations. For other values of OP1, we compute a carefully selected
2962 fixed-point approximation m = 1/OP1, and generate code that multiplies OP0
2965 In all cases but EXACT_DIV_EXPR, this multiplication requires the upper
2966 half of the product. Different strategies for generating the product are
2967 implemented in expand_mult_highpart.
2969 If what we actually want is the remainder, we generate that by another
2970 by-constant multiplication and a subtraction. */
2972 /* We shouldn't be called with OP1 == const1_rtx, but some of the
2973 code below will malfunction if we are, so check here and handle
2974 the special case if so. */
2975 if (op1
== const1_rtx
)
2976 return rem_flag
? const0_rtx
: op0
;
2978 /* When dividing by -1, we could get an overflow.
2979 negv_optab can handle overflows. */
2980 if (! unsignedp
&& op1
== constm1_rtx
)
2984 return expand_unop (mode
, flag_trapv
&& GET_MODE_CLASS(mode
) == MODE_INT
2985 ? negv_optab
: neg_optab
, op0
, target
, 0);
2989 /* Don't use the function value register as a target
2990 since we have to read it as well as write it,
2991 and function-inlining gets confused by this. */
2992 && ((REG_P (target
) && REG_FUNCTION_VALUE_P (target
))
2993 /* Don't clobber an operand while doing a multi-step calculation. */
2994 || ((rem_flag
|| op1_is_constant
)
2995 && (reg_mentioned_p (target
, op0
)
2996 || (GET_CODE (op0
) == MEM
&& GET_CODE (target
) == MEM
)))
2997 || reg_mentioned_p (target
, op1
)
2998 || (GET_CODE (op1
) == MEM
&& GET_CODE (target
) == MEM
)))
3001 /* Get the mode in which to perform this computation. Normally it will
3002 be MODE, but sometimes we can't do the desired operation in MODE.
3003 If so, pick a wider mode in which we can do the operation. Convert
3004 to that mode at the start to avoid repeated conversions.
3006 First see what operations we need. These depend on the expression
3007 we are evaluating. (We assume that divxx3 insns exist under the
3008 same conditions that modxx3 insns and that these insns don't normally
3009 fail. If these assumptions are not correct, we may generate less
3010 efficient code in some cases.)
3012 Then see if we find a mode in which we can open-code that operation
3013 (either a division, modulus, or shift). Finally, check for the smallest
3014 mode for which we can do the operation with a library call. */
3016 /* We might want to refine this now that we have division-by-constant
3017 optimization. Since expand_mult_highpart tries so many variants, it is
3018 not straightforward to generalize this. Maybe we should make an array
3019 of possible modes in init_expmed? Save this for GCC 2.7. */
3021 optab1
= (op1_is_pow2
? (unsignedp
? lshr_optab
: ashr_optab
)
3022 : (unsignedp
? udiv_optab
: sdiv_optab
));
3023 optab2
= (op1_is_pow2
? optab1
: (unsignedp
? udivmod_optab
: sdivmod_optab
));
3025 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
3026 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
3027 if (optab1
->handlers
[(int) compute_mode
].insn_code
!= CODE_FOR_nothing
3028 || optab2
->handlers
[(int) compute_mode
].insn_code
!= CODE_FOR_nothing
)
3031 if (compute_mode
== VOIDmode
)
3032 for (compute_mode
= mode
; compute_mode
!= VOIDmode
;
3033 compute_mode
= GET_MODE_WIDER_MODE (compute_mode
))
3034 if (optab1
->handlers
[(int) compute_mode
].libfunc
3035 || optab2
->handlers
[(int) compute_mode
].libfunc
)
3038 /* If we still couldn't find a mode, use MODE, but we'll probably abort
3040 if (compute_mode
== VOIDmode
)
3041 compute_mode
= mode
;
3043 if (target
&& GET_MODE (target
) == compute_mode
)
3046 tquotient
= gen_reg_rtx (compute_mode
);
3048 size
= GET_MODE_BITSIZE (compute_mode
);
3050 /* It should be possible to restrict the precision to GET_MODE_BITSIZE
3051 (mode), and thereby get better code when OP1 is a constant. Do that
3052 later. It will require going over all usages of SIZE below. */
3053 size
= GET_MODE_BITSIZE (mode
);
3056 /* Only deduct something for a REM if the last divide done was
3057 for a different constant. Then set the constant of the last
3059 max_cost
= div_cost
[(int) compute_mode
]
3060 - (rem_flag
&& ! (last_div_const
!= 0 && op1_is_constant
3061 && INTVAL (op1
) == last_div_const
)
3062 ? mul_cost
[(int) compute_mode
] + add_cost
: 0);
3064 last_div_const
= ! rem_flag
&& op1_is_constant
? INTVAL (op1
) : 0;
3066 /* Now convert to the best mode to use. */
3067 if (compute_mode
!= mode
)
3069 op0
= convert_modes (compute_mode
, mode
, op0
, unsignedp
);
3070 op1
= convert_modes (compute_mode
, mode
, op1
, unsignedp
);
3072 /* convert_modes may have placed op1 into a register, so we
3073 must recompute the following. */
3074 op1_is_constant
= GET_CODE (op1
) == CONST_INT
;
3075 op1_is_pow2
= (op1_is_constant
3076 && ((EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
3078 && EXACT_POWER_OF_2_OR_ZERO_P (-INTVAL (op1
)))))) ;
3081 /* If one of the operands is a volatile MEM, copy it into a register. */
3083 if (GET_CODE (op0
) == MEM
&& MEM_VOLATILE_P (op0
))
3084 op0
= force_reg (compute_mode
, op0
);
3085 if (GET_CODE (op1
) == MEM
&& MEM_VOLATILE_P (op1
))
3086 op1
= force_reg (compute_mode
, op1
);
3088 /* If we need the remainder or if OP1 is constant, we need to
3089 put OP0 in a register in case it has any queued subexpressions. */
3090 if (rem_flag
|| op1_is_constant
)
3091 op0
= force_reg (compute_mode
, op0
);
3093 last
= get_last_insn ();
3095 /* Promote floor rounding to trunc rounding for unsigned operations. */
3098 if (code
== FLOOR_DIV_EXPR
)
3099 code
= TRUNC_DIV_EXPR
;
3100 if (code
== FLOOR_MOD_EXPR
)
3101 code
= TRUNC_MOD_EXPR
;
3102 if (code
== EXACT_DIV_EXPR
&& op1_is_pow2
)
3103 code
= TRUNC_DIV_EXPR
;
3106 if (op1
!= const0_rtx
)
3109 case TRUNC_MOD_EXPR
:
3110 case TRUNC_DIV_EXPR
:
3111 if (op1_is_constant
)
3115 unsigned HOST_WIDE_INT mh
, ml
;
3116 int pre_shift
, post_shift
;
3118 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
3120 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
3122 pre_shift
= floor_log2 (d
);
3126 = expand_binop (compute_mode
, and_optab
, op0
,
3127 GEN_INT (((HOST_WIDE_INT
) 1 << pre_shift
) - 1),
3131 return gen_lowpart (mode
, remainder
);
3133 quotient
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3134 build_int_2 (pre_shift
, 0),
3137 else if (size
<= HOST_BITS_PER_WIDE_INT
)
3139 if (d
>= ((unsigned HOST_WIDE_INT
) 1 << (size
- 1)))
3141 /* Most significant bit of divisor is set; emit an scc
3143 quotient
= emit_store_flag (tquotient
, GEU
, op0
, op1
,
3144 compute_mode
, 1, 1);
3150 /* Find a suitable multiplier and right shift count
3151 instead of multiplying with D. */
3153 mh
= choose_multiplier (d
, size
, size
,
3154 &ml
, &post_shift
, &dummy
);
3156 /* If the suggested multiplier is more than SIZE bits,
3157 we can do better for even divisors, using an
3158 initial right shift. */
3159 if (mh
!= 0 && (d
& 1) == 0)
3161 pre_shift
= floor_log2 (d
& -d
);
3162 mh
= choose_multiplier (d
>> pre_shift
, size
,
3164 &ml
, &post_shift
, &dummy
);
3175 if (post_shift
- 1 >= BITS_PER_WORD
)
3178 extra_cost
= (shift_cost
[post_shift
- 1]
3179 + shift_cost
[1] + 2 * add_cost
);
3180 t1
= expand_mult_highpart (compute_mode
, op0
, ml
,
3182 max_cost
- extra_cost
);
3185 t2
= force_operand (gen_rtx_MINUS (compute_mode
,
3188 t3
= expand_shift (RSHIFT_EXPR
, compute_mode
, t2
,
3189 build_int_2 (1, 0), NULL_RTX
,1);
3190 t4
= force_operand (gen_rtx_PLUS (compute_mode
,
3194 = expand_shift (RSHIFT_EXPR
, compute_mode
, t4
,
3195 build_int_2 (post_shift
- 1, 0),
3202 if (pre_shift
>= BITS_PER_WORD
3203 || post_shift
>= BITS_PER_WORD
)
3206 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3207 build_int_2 (pre_shift
, 0),
3209 extra_cost
= (shift_cost
[pre_shift
]
3210 + shift_cost
[post_shift
]);
3211 t2
= expand_mult_highpart (compute_mode
, t1
, ml
,
3213 max_cost
- extra_cost
);
3217 = expand_shift (RSHIFT_EXPR
, compute_mode
, t2
,
3218 build_int_2 (post_shift
, 0),
3223 else /* Too wide mode to use tricky code */
3226 insn
= get_last_insn ();
3228 && (set
= single_set (insn
)) != 0
3229 && SET_DEST (set
) == quotient
)
3230 set_unique_reg_note (insn
,
3232 gen_rtx_UDIV (compute_mode
, op0
, op1
));
3234 else /* TRUNC_DIV, signed */
3236 unsigned HOST_WIDE_INT ml
;
3237 int lgup
, post_shift
;
3238 HOST_WIDE_INT d
= INTVAL (op1
);
3239 unsigned HOST_WIDE_INT abs_d
= d
>= 0 ? d
: -d
;
3241 /* n rem d = n rem -d */
3242 if (rem_flag
&& d
< 0)
3245 op1
= GEN_INT (trunc_int_for_mode (abs_d
, compute_mode
));
3251 quotient
= expand_unop (compute_mode
, neg_optab
, op0
,
3253 else if (abs_d
== (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
3255 /* This case is not handled correctly below. */
3256 quotient
= emit_store_flag (tquotient
, EQ
, op0
, op1
,
3257 compute_mode
, 1, 1);
3261 else if (EXACT_POWER_OF_2_OR_ZERO_P (d
)
3262 && (rem_flag
? smod_pow2_cheap
: sdiv_pow2_cheap
)
3263 /* ??? The cheap metric is computed only for
3264 word_mode. If this operation is wider, this may
3265 not be so. Assume true if the optab has an
3266 expander for this mode. */
3267 && (((rem_flag
? smod_optab
: sdiv_optab
)
3268 ->handlers
[(int) compute_mode
].insn_code
3269 != CODE_FOR_nothing
)
3270 || (sdivmod_optab
->handlers
[(int) compute_mode
]
3271 .insn_code
!= CODE_FOR_nothing
)))
3273 else if (EXACT_POWER_OF_2_OR_ZERO_P (abs_d
))
3275 lgup
= floor_log2 (abs_d
);
3276 if (BRANCH_COST
< 1 || (abs_d
!= 2 && BRANCH_COST
< 3))
3278 rtx label
= gen_label_rtx ();
3281 t1
= copy_to_mode_reg (compute_mode
, op0
);
3282 do_cmp_and_jump (t1
, const0_rtx
, GE
,
3283 compute_mode
, label
);
3284 expand_inc (t1
, GEN_INT (trunc_int_for_mode
3285 (abs_d
- 1, compute_mode
)));
3287 quotient
= expand_shift (RSHIFT_EXPR
, compute_mode
, t1
,
3288 build_int_2 (lgup
, 0),
3294 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3295 build_int_2 (size
- 1, 0),
3297 t2
= expand_shift (RSHIFT_EXPR
, compute_mode
, t1
,
3298 build_int_2 (size
- lgup
, 0),
3300 t3
= force_operand (gen_rtx_PLUS (compute_mode
,
3303 quotient
= expand_shift (RSHIFT_EXPR
, compute_mode
, t3
,
3304 build_int_2 (lgup
, 0),
3308 /* We have computed OP0 / abs(OP1). If OP1 is negative, negate
3312 insn
= get_last_insn ();
3314 && (set
= single_set (insn
)) != 0
3315 && SET_DEST (set
) == quotient
3316 && abs_d
< ((unsigned HOST_WIDE_INT
) 1
3317 << (HOST_BITS_PER_WIDE_INT
- 1)))
3318 set_unique_reg_note (insn
,
3320 gen_rtx_DIV (compute_mode
,
3327 quotient
= expand_unop (compute_mode
, neg_optab
,
3328 quotient
, quotient
, 0);
3331 else if (size
<= HOST_BITS_PER_WIDE_INT
)
3333 choose_multiplier (abs_d
, size
, size
- 1,
3334 &ml
, &post_shift
, &lgup
);
3335 if (ml
< (unsigned HOST_WIDE_INT
) 1 << (size
- 1))
3339 if (post_shift
>= BITS_PER_WORD
3340 || size
- 1 >= BITS_PER_WORD
)
3343 extra_cost
= (shift_cost
[post_shift
]
3344 + shift_cost
[size
- 1] + add_cost
);
3345 t1
= expand_mult_highpart (compute_mode
, op0
, ml
,
3347 max_cost
- extra_cost
);
3350 t2
= expand_shift (RSHIFT_EXPR
, compute_mode
, t1
,
3351 build_int_2 (post_shift
, 0), NULL_RTX
, 0);
3352 t3
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3353 build_int_2 (size
- 1, 0), NULL_RTX
, 0);
3356 = force_operand (gen_rtx_MINUS (compute_mode
,
3361 = force_operand (gen_rtx_MINUS (compute_mode
,
3369 if (post_shift
>= BITS_PER_WORD
3370 || size
- 1 >= BITS_PER_WORD
)
3373 ml
|= (~(unsigned HOST_WIDE_INT
) 0) << (size
- 1);
3374 extra_cost
= (shift_cost
[post_shift
]
3375 + shift_cost
[size
- 1] + 2 * add_cost
);
3376 t1
= expand_mult_highpart (compute_mode
, op0
, ml
,
3378 max_cost
- extra_cost
);
3381 t2
= force_operand (gen_rtx_PLUS (compute_mode
,
3384 t3
= expand_shift (RSHIFT_EXPR
, compute_mode
, t2
,
3385 build_int_2 (post_shift
, 0),
3387 t4
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3388 build_int_2 (size
- 1, 0),
3392 = force_operand (gen_rtx_MINUS (compute_mode
,
3397 = force_operand (gen_rtx_MINUS (compute_mode
,
3402 else /* Too wide mode to use tricky code */
3405 insn
= get_last_insn ();
3407 && (set
= single_set (insn
)) != 0
3408 && SET_DEST (set
) == quotient
)
3409 set_unique_reg_note (insn
,
3411 gen_rtx_DIV (compute_mode
, op0
, op1
));
3416 delete_insns_since (last
);
3419 case FLOOR_DIV_EXPR
:
3420 case FLOOR_MOD_EXPR
:
3421 /* We will come here only for signed operations. */
3422 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
3424 unsigned HOST_WIDE_INT mh
, ml
;
3425 int pre_shift
, lgup
, post_shift
;
3426 HOST_WIDE_INT d
= INTVAL (op1
);
3430 /* We could just as easily deal with negative constants here,
3431 but it does not seem worth the trouble for GCC 2.6. */
3432 if (EXACT_POWER_OF_2_OR_ZERO_P (d
))
3434 pre_shift
= floor_log2 (d
);
3437 remainder
= expand_binop (compute_mode
, and_optab
, op0
,
3438 GEN_INT (((HOST_WIDE_INT
) 1 << pre_shift
) - 1),
3439 remainder
, 0, OPTAB_LIB_WIDEN
);
3441 return gen_lowpart (mode
, remainder
);
3443 quotient
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3444 build_int_2 (pre_shift
, 0),
3451 mh
= choose_multiplier (d
, size
, size
- 1,
3452 &ml
, &post_shift
, &lgup
);
3456 if (post_shift
< BITS_PER_WORD
3457 && size
- 1 < BITS_PER_WORD
)
3459 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3460 build_int_2 (size
- 1, 0),
3462 t2
= expand_binop (compute_mode
, xor_optab
, op0
, t1
,
3463 NULL_RTX
, 0, OPTAB_WIDEN
);
3464 extra_cost
= (shift_cost
[post_shift
]
3465 + shift_cost
[size
- 1] + 2 * add_cost
);
3466 t3
= expand_mult_highpart (compute_mode
, t2
, ml
,
3468 max_cost
- extra_cost
);
3471 t4
= expand_shift (RSHIFT_EXPR
, compute_mode
, t3
,
3472 build_int_2 (post_shift
, 0),
3474 quotient
= expand_binop (compute_mode
, xor_optab
,
3475 t4
, t1
, tquotient
, 0,
3483 rtx nsign
, t1
, t2
, t3
, t4
;
3484 t1
= force_operand (gen_rtx_PLUS (compute_mode
,
3485 op0
, constm1_rtx
), NULL_RTX
);
3486 t2
= expand_binop (compute_mode
, ior_optab
, op0
, t1
, NULL_RTX
,
3488 nsign
= expand_shift (RSHIFT_EXPR
, compute_mode
, t2
,
3489 build_int_2 (size
- 1, 0), NULL_RTX
, 0);
3490 t3
= force_operand (gen_rtx_MINUS (compute_mode
, t1
, nsign
),
3492 t4
= expand_divmod (0, TRUNC_DIV_EXPR
, compute_mode
, t3
, op1
,
3497 t5
= expand_unop (compute_mode
, one_cmpl_optab
, nsign
,
3499 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
3508 delete_insns_since (last
);
3510 /* Try using an instruction that produces both the quotient and
3511 remainder, using truncation. We can easily compensate the quotient
3512 or remainder to get floor rounding, once we have the remainder.
3513 Notice that we compute also the final remainder value here,
3514 and return the result right away. */
3515 if (target
== 0 || GET_MODE (target
) != compute_mode
)
3516 target
= gen_reg_rtx (compute_mode
);
3521 = GET_CODE (target
) == REG
? target
: gen_reg_rtx (compute_mode
);
3522 quotient
= gen_reg_rtx (compute_mode
);
3527 = GET_CODE (target
) == REG
? target
: gen_reg_rtx (compute_mode
);
3528 remainder
= gen_reg_rtx (compute_mode
);
3531 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
,
3532 quotient
, remainder
, 0))
3534 /* This could be computed with a branch-less sequence.
3535 Save that for later. */
3537 rtx label
= gen_label_rtx ();
3538 do_cmp_and_jump (remainder
, const0_rtx
, EQ
, compute_mode
, label
);
3539 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
3540 NULL_RTX
, 0, OPTAB_WIDEN
);
3541 do_cmp_and_jump (tem
, const0_rtx
, GE
, compute_mode
, label
);
3542 expand_dec (quotient
, const1_rtx
);
3543 expand_inc (remainder
, op1
);
3545 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
3548 /* No luck with division elimination or divmod. Have to do it
3549 by conditionally adjusting op0 *and* the result. */
3551 rtx label1
, label2
, label3
, label4
, label5
;
3555 quotient
= gen_reg_rtx (compute_mode
);
3556 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
3557 label1
= gen_label_rtx ();
3558 label2
= gen_label_rtx ();
3559 label3
= gen_label_rtx ();
3560 label4
= gen_label_rtx ();
3561 label5
= gen_label_rtx ();
3562 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
3563 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
, compute_mode
, label1
);
3564 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3565 quotient
, 0, OPTAB_LIB_WIDEN
);
3566 if (tem
!= quotient
)
3567 emit_move_insn (quotient
, tem
);
3568 emit_jump_insn (gen_jump (label5
));
3570 emit_label (label1
);
3571 expand_inc (adjusted_op0
, const1_rtx
);
3572 emit_jump_insn (gen_jump (label4
));
3574 emit_label (label2
);
3575 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
, compute_mode
, label3
);
3576 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3577 quotient
, 0, OPTAB_LIB_WIDEN
);
3578 if (tem
!= quotient
)
3579 emit_move_insn (quotient
, tem
);
3580 emit_jump_insn (gen_jump (label5
));
3582 emit_label (label3
);
3583 expand_dec (adjusted_op0
, const1_rtx
);
3584 emit_label (label4
);
3585 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3586 quotient
, 0, OPTAB_LIB_WIDEN
);
3587 if (tem
!= quotient
)
3588 emit_move_insn (quotient
, tem
);
3589 expand_dec (quotient
, const1_rtx
);
3590 emit_label (label5
);
3598 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
)))
3601 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
3602 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3603 build_int_2 (floor_log2 (d
), 0),
3605 t2
= expand_binop (compute_mode
, and_optab
, op0
,
3607 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3608 t3
= gen_reg_rtx (compute_mode
);
3609 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
3610 compute_mode
, 1, 1);
3614 lab
= gen_label_rtx ();
3615 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
3616 expand_inc (t1
, const1_rtx
);
3621 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
3627 /* Try using an instruction that produces both the quotient and
3628 remainder, using truncation. We can easily compensate the
3629 quotient or remainder to get ceiling rounding, once we have the
3630 remainder. Notice that we compute also the final remainder
3631 value here, and return the result right away. */
3632 if (target
== 0 || GET_MODE (target
) != compute_mode
)
3633 target
= gen_reg_rtx (compute_mode
);
3637 remainder
= (GET_CODE (target
) == REG
3638 ? target
: gen_reg_rtx (compute_mode
));
3639 quotient
= gen_reg_rtx (compute_mode
);
3643 quotient
= (GET_CODE (target
) == REG
3644 ? target
: gen_reg_rtx (compute_mode
));
3645 remainder
= gen_reg_rtx (compute_mode
);
3648 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
,
3651 /* This could be computed with a branch-less sequence.
3652 Save that for later. */
3653 rtx label
= gen_label_rtx ();
3654 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
3655 compute_mode
, label
);
3656 expand_inc (quotient
, const1_rtx
);
3657 expand_dec (remainder
, op1
);
3659 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
3662 /* No luck with division elimination or divmod. Have to do it
3663 by conditionally adjusting op0 *and* the result. */
3666 rtx adjusted_op0
, tem
;
3668 quotient
= gen_reg_rtx (compute_mode
);
3669 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
3670 label1
= gen_label_rtx ();
3671 label2
= gen_label_rtx ();
3672 do_cmp_and_jump (adjusted_op0
, const0_rtx
, NE
,
3673 compute_mode
, label1
);
3674 emit_move_insn (quotient
, const0_rtx
);
3675 emit_jump_insn (gen_jump (label2
));
3677 emit_label (label1
);
3678 expand_dec (adjusted_op0
, const1_rtx
);
3679 tem
= expand_binop (compute_mode
, udiv_optab
, adjusted_op0
, op1
,
3680 quotient
, 1, OPTAB_LIB_WIDEN
);
3681 if (tem
!= quotient
)
3682 emit_move_insn (quotient
, tem
);
3683 expand_inc (quotient
, const1_rtx
);
3684 emit_label (label2
);
3689 if (op1_is_constant
&& EXACT_POWER_OF_2_OR_ZERO_P (INTVAL (op1
))
3690 && INTVAL (op1
) >= 0)
3692 /* This is extremely similar to the code for the unsigned case
3693 above. For 2.7 we should merge these variants, but for
3694 2.6.1 I don't want to touch the code for unsigned since that
3695 get used in C. The signed case will only be used by other
3699 unsigned HOST_WIDE_INT d
= INTVAL (op1
);
3700 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3701 build_int_2 (floor_log2 (d
), 0),
3703 t2
= expand_binop (compute_mode
, and_optab
, op0
,
3705 NULL_RTX
, 1, OPTAB_LIB_WIDEN
);
3706 t3
= gen_reg_rtx (compute_mode
);
3707 t3
= emit_store_flag (t3
, NE
, t2
, const0_rtx
,
3708 compute_mode
, 1, 1);
3712 lab
= gen_label_rtx ();
3713 do_cmp_and_jump (t2
, const0_rtx
, EQ
, compute_mode
, lab
);
3714 expand_inc (t1
, const1_rtx
);
3719 quotient
= force_operand (gen_rtx_PLUS (compute_mode
,
3725 /* Try using an instruction that produces both the quotient and
3726 remainder, using truncation. We can easily compensate the
3727 quotient or remainder to get ceiling rounding, once we have the
3728 remainder. Notice that we compute also the final remainder
3729 value here, and return the result right away. */
3730 if (target
== 0 || GET_MODE (target
) != compute_mode
)
3731 target
= gen_reg_rtx (compute_mode
);
3734 remainder
= (GET_CODE (target
) == REG
3735 ? target
: gen_reg_rtx (compute_mode
));
3736 quotient
= gen_reg_rtx (compute_mode
);
3740 quotient
= (GET_CODE (target
) == REG
3741 ? target
: gen_reg_rtx (compute_mode
));
3742 remainder
= gen_reg_rtx (compute_mode
);
3745 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
,
3748 /* This could be computed with a branch-less sequence.
3749 Save that for later. */
3751 rtx label
= gen_label_rtx ();
3752 do_cmp_and_jump (remainder
, const0_rtx
, EQ
,
3753 compute_mode
, label
);
3754 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
3755 NULL_RTX
, 0, OPTAB_WIDEN
);
3756 do_cmp_and_jump (tem
, const0_rtx
, LT
, compute_mode
, label
);
3757 expand_inc (quotient
, const1_rtx
);
3758 expand_dec (remainder
, op1
);
3760 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
3763 /* No luck with division elimination or divmod. Have to do it
3764 by conditionally adjusting op0 *and* the result. */
3766 rtx label1
, label2
, label3
, label4
, label5
;
3770 quotient
= gen_reg_rtx (compute_mode
);
3771 adjusted_op0
= copy_to_mode_reg (compute_mode
, op0
);
3772 label1
= gen_label_rtx ();
3773 label2
= gen_label_rtx ();
3774 label3
= gen_label_rtx ();
3775 label4
= gen_label_rtx ();
3776 label5
= gen_label_rtx ();
3777 do_cmp_and_jump (op1
, const0_rtx
, LT
, compute_mode
, label2
);
3778 do_cmp_and_jump (adjusted_op0
, const0_rtx
, GT
,
3779 compute_mode
, label1
);
3780 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3781 quotient
, 0, OPTAB_LIB_WIDEN
);
3782 if (tem
!= quotient
)
3783 emit_move_insn (quotient
, tem
);
3784 emit_jump_insn (gen_jump (label5
));
3786 emit_label (label1
);
3787 expand_dec (adjusted_op0
, const1_rtx
);
3788 emit_jump_insn (gen_jump (label4
));
3790 emit_label (label2
);
3791 do_cmp_and_jump (adjusted_op0
, const0_rtx
, LT
,
3792 compute_mode
, label3
);
3793 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3794 quotient
, 0, OPTAB_LIB_WIDEN
);
3795 if (tem
!= quotient
)
3796 emit_move_insn (quotient
, tem
);
3797 emit_jump_insn (gen_jump (label5
));
3799 emit_label (label3
);
3800 expand_inc (adjusted_op0
, const1_rtx
);
3801 emit_label (label4
);
3802 tem
= expand_binop (compute_mode
, sdiv_optab
, adjusted_op0
, op1
,
3803 quotient
, 0, OPTAB_LIB_WIDEN
);
3804 if (tem
!= quotient
)
3805 emit_move_insn (quotient
, tem
);
3806 expand_inc (quotient
, const1_rtx
);
3807 emit_label (label5
);
3812 case EXACT_DIV_EXPR
:
3813 if (op1_is_constant
&& HOST_BITS_PER_WIDE_INT
>= size
)
3815 HOST_WIDE_INT d
= INTVAL (op1
);
3816 unsigned HOST_WIDE_INT ml
;
3820 pre_shift
= floor_log2 (d
& -d
);
3821 ml
= invert_mod2n (d
>> pre_shift
, size
);
3822 t1
= expand_shift (RSHIFT_EXPR
, compute_mode
, op0
,
3823 build_int_2 (pre_shift
, 0), NULL_RTX
, unsignedp
);
3824 quotient
= expand_mult (compute_mode
, t1
,
3825 GEN_INT (trunc_int_for_mode
3826 (ml
, compute_mode
)),
3829 insn
= get_last_insn ();
3830 set_unique_reg_note (insn
,
3832 gen_rtx_fmt_ee (unsignedp
? UDIV
: DIV
,
3838 case ROUND_DIV_EXPR
:
3839 case ROUND_MOD_EXPR
:
3844 label
= gen_label_rtx ();
3845 quotient
= gen_reg_rtx (compute_mode
);
3846 remainder
= gen_reg_rtx (compute_mode
);
3847 if (expand_twoval_binop (udivmod_optab
, op0
, op1
, quotient
, remainder
, 1) == 0)
3850 quotient
= expand_binop (compute_mode
, udiv_optab
, op0
, op1
,
3851 quotient
, 1, OPTAB_LIB_WIDEN
);
3852 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 1);
3853 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
3854 remainder
, 1, OPTAB_LIB_WIDEN
);
3856 tem
= plus_constant (op1
, -1);
3857 tem
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
,
3858 build_int_2 (1, 0), NULL_RTX
, 1);
3859 do_cmp_and_jump (remainder
, tem
, LEU
, compute_mode
, label
);
3860 expand_inc (quotient
, const1_rtx
);
3861 expand_dec (remainder
, op1
);
3866 rtx abs_rem
, abs_op1
, tem
, mask
;
3868 label
= gen_label_rtx ();
3869 quotient
= gen_reg_rtx (compute_mode
);
3870 remainder
= gen_reg_rtx (compute_mode
);
3871 if (expand_twoval_binop (sdivmod_optab
, op0
, op1
, quotient
, remainder
, 0) == 0)
3874 quotient
= expand_binop (compute_mode
, sdiv_optab
, op0
, op1
,
3875 quotient
, 0, OPTAB_LIB_WIDEN
);
3876 tem
= expand_mult (compute_mode
, quotient
, op1
, NULL_RTX
, 0);
3877 remainder
= expand_binop (compute_mode
, sub_optab
, op0
, tem
,
3878 remainder
, 0, OPTAB_LIB_WIDEN
);
3880 abs_rem
= expand_abs (compute_mode
, remainder
, NULL_RTX
, 1, 0);
3881 abs_op1
= expand_abs (compute_mode
, op1
, NULL_RTX
, 1, 0);
3882 tem
= expand_shift (LSHIFT_EXPR
, compute_mode
, abs_rem
,
3883 build_int_2 (1, 0), NULL_RTX
, 1);
3884 do_cmp_and_jump (tem
, abs_op1
, LTU
, compute_mode
, label
);
3885 tem
= expand_binop (compute_mode
, xor_optab
, op0
, op1
,
3886 NULL_RTX
, 0, OPTAB_WIDEN
);
3887 mask
= expand_shift (RSHIFT_EXPR
, compute_mode
, tem
,
3888 build_int_2 (size
- 1, 0), NULL_RTX
, 0);
3889 tem
= expand_binop (compute_mode
, xor_optab
, mask
, const1_rtx
,
3890 NULL_RTX
, 0, OPTAB_WIDEN
);
3891 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
3892 NULL_RTX
, 0, OPTAB_WIDEN
);
3893 expand_inc (quotient
, tem
);
3894 tem
= expand_binop (compute_mode
, xor_optab
, mask
, op1
,
3895 NULL_RTX
, 0, OPTAB_WIDEN
);
3896 tem
= expand_binop (compute_mode
, sub_optab
, tem
, mask
,
3897 NULL_RTX
, 0, OPTAB_WIDEN
);
3898 expand_dec (remainder
, tem
);
3901 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
3909 if (target
&& GET_MODE (target
) != compute_mode
)
3914 /* Try to produce the remainder without producing the quotient.
3915 If we seem to have a divmod pattern that does not require widening,
3916 don't try widening here. We should really have an WIDEN argument
3917 to expand_twoval_binop, since what we'd really like to do here is
3918 1) try a mod insn in compute_mode
3919 2) try a divmod insn in compute_mode
3920 3) try a div insn in compute_mode and multiply-subtract to get
3922 4) try the same things with widening allowed. */
3924 = sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
3927 ((optab2
->handlers
[(int) compute_mode
].insn_code
3928 != CODE_FOR_nothing
)
3929 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
3932 /* No luck there. Can we do remainder and divide at once
3933 without a library call? */
3934 remainder
= gen_reg_rtx (compute_mode
);
3935 if (! expand_twoval_binop ((unsignedp
3939 NULL_RTX
, remainder
, unsignedp
))
3944 return gen_lowpart (mode
, remainder
);
3947 /* Produce the quotient. Try a quotient insn, but not a library call.
3948 If we have a divmod in this mode, use it in preference to widening
3949 the div (for this test we assume it will not fail). Note that optab2
3950 is set to the one of the two optabs that the call below will use. */
3952 = sign_expand_binop (compute_mode
, udiv_optab
, sdiv_optab
,
3953 op0
, op1
, rem_flag
? NULL_RTX
: target
,
3955 ((optab2
->handlers
[(int) compute_mode
].insn_code
3956 != CODE_FOR_nothing
)
3957 ? OPTAB_DIRECT
: OPTAB_WIDEN
));
3961 /* No luck there. Try a quotient-and-remainder insn,
3962 keeping the quotient alone. */
3963 quotient
= gen_reg_rtx (compute_mode
);
3964 if (! expand_twoval_binop (unsignedp
? udivmod_optab
: sdivmod_optab
,
3966 quotient
, NULL_RTX
, unsignedp
))
3970 /* Still no luck. If we are not computing the remainder,
3971 use a library call for the quotient. */
3972 quotient
= sign_expand_binop (compute_mode
,
3973 udiv_optab
, sdiv_optab
,
3975 unsignedp
, OPTAB_LIB_WIDEN
);
3982 if (target
&& GET_MODE (target
) != compute_mode
)
3986 /* No divide instruction either. Use library for remainder. */
3987 remainder
= sign_expand_binop (compute_mode
, umod_optab
, smod_optab
,
3989 unsignedp
, OPTAB_LIB_WIDEN
);
3992 /* We divided. Now finish doing X - Y * (X / Y). */
3993 remainder
= expand_mult (compute_mode
, quotient
, op1
,
3994 NULL_RTX
, unsignedp
);
3995 remainder
= expand_binop (compute_mode
, sub_optab
, op0
,
3996 remainder
, target
, unsignedp
,
4001 return gen_lowpart (mode
, rem_flag
? remainder
: quotient
);
4004 /* Return a tree node with data type TYPE, describing the value of X.
4005 Usually this is an RTL_EXPR, if there is no obvious better choice.
4006 X may be an expression, however we only support those expressions
4007 generated by loop.c. */
4016 switch (GET_CODE (x
))
4019 t
= build_int_2 (INTVAL (x
),
4020 (TREE_UNSIGNED (type
)
4021 && (GET_MODE_BITSIZE (TYPE_MODE (type
)) < HOST_BITS_PER_WIDE_INT
))
4022 || INTVAL (x
) >= 0 ? 0 : -1);
4023 TREE_TYPE (t
) = type
;
4027 if (GET_MODE (x
) == VOIDmode
)
4029 t
= build_int_2 (CONST_DOUBLE_LOW (x
), CONST_DOUBLE_HIGH (x
));
4030 TREE_TYPE (t
) = type
;
4036 REAL_VALUE_FROM_CONST_DOUBLE (d
, x
);
4037 t
= build_real (type
, d
);
4048 units
= CONST_VECTOR_NUNITS (x
);
4050 /* Build a tree with vector elements. */
4051 for (i
= units
- 1; i
>= 0; --i
)
4053 elt
= CONST_VECTOR_ELT (x
, i
);
4054 t
= tree_cons (NULL_TREE
, make_tree (type
, elt
), t
);
4057 return build_vector (type
, t
);
4061 return fold (build (PLUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4062 make_tree (type
, XEXP (x
, 1))));
4065 return fold (build (MINUS_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4066 make_tree (type
, XEXP (x
, 1))));
4069 return fold (build1 (NEGATE_EXPR
, type
, make_tree (type
, XEXP (x
, 0))));
4072 return fold (build (MULT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4073 make_tree (type
, XEXP (x
, 1))));
4076 return fold (build (LSHIFT_EXPR
, type
, make_tree (type
, XEXP (x
, 0)),
4077 make_tree (type
, XEXP (x
, 1))));
4080 return fold (convert (type
,
4081 build (RSHIFT_EXPR
, unsigned_type (type
),
4082 make_tree (unsigned_type (type
),
4084 make_tree (type
, XEXP (x
, 1)))));
4087 return fold (convert (type
,
4088 build (RSHIFT_EXPR
, signed_type (type
),
4089 make_tree (signed_type (type
), XEXP (x
, 0)),
4090 make_tree (type
, XEXP (x
, 1)))));
4093 if (TREE_CODE (type
) != REAL_TYPE
)
4094 t
= signed_type (type
);
4098 return fold (convert (type
,
4099 build (TRUNC_DIV_EXPR
, t
,
4100 make_tree (t
, XEXP (x
, 0)),
4101 make_tree (t
, XEXP (x
, 1)))));
4103 t
= unsigned_type (type
);
4104 return fold (convert (type
,
4105 build (TRUNC_DIV_EXPR
, t
,
4106 make_tree (t
, XEXP (x
, 0)),
4107 make_tree (t
, XEXP (x
, 1)))));
4109 t
= make_node (RTL_EXPR
);
4110 TREE_TYPE (t
) = type
;
4112 #ifdef POINTERS_EXTEND_UNSIGNED
4113 /* If TYPE is a POINTER_TYPE, X might be Pmode with TYPE_MODE being
4114 ptr_mode. So convert. */
4115 if (POINTER_TYPE_P (type
) && GET_MODE (x
) != TYPE_MODE (type
))
4116 x
= convert_memory_address (TYPE_MODE (type
), x
);
4119 RTL_EXPR_RTL (t
) = x
;
4120 /* There are no insns to be output
4121 when this rtl_expr is used. */
4122 RTL_EXPR_SEQUENCE (t
) = 0;
4127 /* Return an rtx representing the value of X * MULT + ADD.
4128 TARGET is a suggestion for where to store the result (an rtx).
4129 MODE is the machine mode for the computation.
4130 X and MULT must have mode MODE. ADD may have a different mode.
4131 So can X (defaults to same as MODE).
4132 UNSIGNEDP is non-zero to do unsigned multiplication.
4133 This may emit insns. */
4136 expand_mult_add (x
, target
, mult
, add
, mode
, unsignedp
)
4137 rtx x
, target
, mult
, add
;
4138 enum machine_mode mode
;
4141 tree type
= type_for_mode (mode
, unsignedp
);
4142 tree add_type
= (GET_MODE (add
) == VOIDmode
4143 ? type
: type_for_mode (GET_MODE (add
), unsignedp
));
4144 tree result
= fold (build (PLUS_EXPR
, type
,
4145 fold (build (MULT_EXPR
, type
,
4146 make_tree (type
, x
),
4147 make_tree (type
, mult
))),
4148 make_tree (add_type
, add
)));
4150 return expand_expr (result
, target
, VOIDmode
, 0);
4153 /* Compute the logical-and of OP0 and OP1, storing it in TARGET
4154 and returning TARGET.
4156 If TARGET is 0, a pseudo-register or constant is returned. */
4159 expand_and (op0
, op1
, target
)
4160 rtx op0
, op1
, target
;
4162 enum machine_mode mode
= VOIDmode
;
4165 if (GET_MODE (op0
) != VOIDmode
)
4166 mode
= GET_MODE (op0
);
4167 else if (GET_MODE (op1
) != VOIDmode
)
4168 mode
= GET_MODE (op1
);
4170 if (mode
!= VOIDmode
)
4171 tem
= expand_binop (mode
, and_optab
, op0
, op1
, target
, 0, OPTAB_LIB_WIDEN
);
4172 else if (GET_CODE (op0
) == CONST_INT
&& GET_CODE (op1
) == CONST_INT
)
4173 tem
= GEN_INT (INTVAL (op0
) & INTVAL (op1
));
4179 else if (tem
!= target
)
4180 emit_move_insn (target
, tem
);
4184 /* Emit a store-flags instruction for comparison CODE on OP0 and OP1
4185 and storing in TARGET. Normally return TARGET.
4186 Return 0 if that cannot be done.
4188 MODE is the mode to use for OP0 and OP1 should they be CONST_INTs. If
4189 it is VOIDmode, they cannot both be CONST_INT.
4191 UNSIGNEDP is for the case where we have to widen the operands
4192 to perform the operation. It says to use zero-extension.
4194 NORMALIZEP is 1 if we should convert the result to be either zero
4195 or one. Normalize is -1 if we should convert the result to be
4196 either zero or -1. If NORMALIZEP is zero, the result will be left
4197 "raw" out of the scc insn. */
4200 emit_store_flag (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
)
4204 enum machine_mode mode
;
4209 enum insn_code icode
;
4210 enum machine_mode compare_mode
;
4211 enum machine_mode target_mode
= GET_MODE (target
);
4213 rtx last
= get_last_insn ();
4214 rtx pattern
, comparison
;
4216 /* ??? Ok to do this and then fail? */
4217 op0
= protect_from_queue (op0
, 0);
4218 op1
= protect_from_queue (op1
, 0);
4221 code
= unsigned_condition (code
);
4223 /* If one operand is constant, make it the second one. Only do this
4224 if the other operand is not constant as well. */
4226 if (swap_commutative_operands_p (op0
, op1
))
4231 code
= swap_condition (code
);
4234 if (mode
== VOIDmode
)
4235 mode
= GET_MODE (op0
);
4237 /* For some comparisons with 1 and -1, we can convert this to
4238 comparisons with zero. This will often produce more opportunities for
4239 store-flag insns. */
4244 if (op1
== const1_rtx
)
4245 op1
= const0_rtx
, code
= LE
;
4248 if (op1
== constm1_rtx
)
4249 op1
= const0_rtx
, code
= LT
;
4252 if (op1
== const1_rtx
)
4253 op1
= const0_rtx
, code
= GT
;
4256 if (op1
== constm1_rtx
)
4257 op1
= const0_rtx
, code
= GE
;
4260 if (op1
== const1_rtx
)
4261 op1
= const0_rtx
, code
= NE
;
4264 if (op1
== const1_rtx
)
4265 op1
= const0_rtx
, code
= EQ
;
4271 /* If we are comparing a double-word integer with zero, we can convert
4272 the comparison into one involving a single word. */
4273 if (GET_MODE_BITSIZE (mode
) == BITS_PER_WORD
* 2
4274 && GET_MODE_CLASS (mode
) == MODE_INT
4275 && op1
== const0_rtx
)
4277 if (code
== EQ
|| code
== NE
)
4279 /* Do a logical OR of the two words and compare the result. */
4280 rtx op0h
= gen_highpart (word_mode
, op0
);
4281 rtx op0l
= gen_lowpart (word_mode
, op0
);
4282 rtx op0both
= expand_binop (word_mode
, ior_optab
, op0h
, op0l
,
4283 NULL_RTX
, unsignedp
, OPTAB_DIRECT
);
4285 return emit_store_flag (target
, code
, op0both
, op1
, word_mode
,
4286 unsignedp
, normalizep
);
4288 else if (code
== LT
|| code
== GE
)
4289 /* If testing the sign bit, can just test on high word. */
4290 return emit_store_flag (target
, code
, gen_highpart (word_mode
, op0
),
4291 op1
, word_mode
, unsignedp
, normalizep
);
4294 /* From now on, we won't change CODE, so set ICODE now. */
4295 icode
= setcc_gen_code
[(int) code
];
4297 /* If this is A < 0 or A >= 0, we can do this by taking the ones
4298 complement of A (for GE) and shifting the sign bit to the low bit. */
4299 if (op1
== const0_rtx
&& (code
== LT
|| code
== GE
)
4300 && GET_MODE_CLASS (mode
) == MODE_INT
4301 && (normalizep
|| STORE_FLAG_VALUE
== 1
4302 || (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4303 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4304 == (HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1)))))
4308 /* If the result is to be wider than OP0, it is best to convert it
4309 first. If it is to be narrower, it is *incorrect* to convert it
4311 if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (mode
))
4313 op0
= protect_from_queue (op0
, 0);
4314 op0
= convert_modes (target_mode
, mode
, op0
, 0);
4318 if (target_mode
!= mode
)
4322 op0
= expand_unop (mode
, one_cmpl_optab
, op0
,
4323 ((STORE_FLAG_VALUE
== 1 || normalizep
)
4324 ? 0 : subtarget
), 0);
4326 if (STORE_FLAG_VALUE
== 1 || normalizep
)
4327 /* If we are supposed to produce a 0/1 value, we want to do
4328 a logical shift from the sign bit to the low-order bit; for
4329 a -1/0 value, we do an arithmetic shift. */
4330 op0
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
4331 size_int (GET_MODE_BITSIZE (mode
) - 1),
4332 subtarget
, normalizep
!= -1);
4334 if (mode
!= target_mode
)
4335 op0
= convert_modes (target_mode
, mode
, op0
, 0);
4340 if (icode
!= CODE_FOR_nothing
)
4342 insn_operand_predicate_fn pred
;
4344 /* We think we may be able to do this with a scc insn. Emit the
4345 comparison and then the scc insn.
4347 compare_from_rtx may call emit_queue, which would be deleted below
4348 if the scc insn fails. So call it ourselves before setting LAST.
4349 Likewise for do_pending_stack_adjust. */
4352 do_pending_stack_adjust ();
4353 last
= get_last_insn ();
4356 = compare_from_rtx (op0
, op1
, code
, unsignedp
, mode
, NULL_RTX
);
4357 if (GET_CODE (comparison
) == CONST_INT
)
4358 return (comparison
== const0_rtx
? const0_rtx
4359 : normalizep
== 1 ? const1_rtx
4360 : normalizep
== -1 ? constm1_rtx
4363 /* The code of COMPARISON may not match CODE if compare_from_rtx
4364 decided to swap its operands and reverse the original code.
4366 We know that compare_from_rtx returns either a CONST_INT or
4367 a new comparison code, so it is safe to just extract the
4368 code from COMPARISON. */
4369 code
= GET_CODE (comparison
);
4371 /* Get a reference to the target in the proper mode for this insn. */
4372 compare_mode
= insn_data
[(int) icode
].operand
[0].mode
;
4374 pred
= insn_data
[(int) icode
].operand
[0].predicate
;
4375 if (preserve_subexpressions_p ()
4376 || ! (*pred
) (subtarget
, compare_mode
))
4377 subtarget
= gen_reg_rtx (compare_mode
);
4379 pattern
= GEN_FCN (icode
) (subtarget
);
4382 emit_insn (pattern
);
4384 /* If we are converting to a wider mode, first convert to
4385 TARGET_MODE, then normalize. This produces better combining
4386 opportunities on machines that have a SIGN_EXTRACT when we are
4387 testing a single bit. This mostly benefits the 68k.
4389 If STORE_FLAG_VALUE does not have the sign bit set when
4390 interpreted in COMPARE_MODE, we can do this conversion as
4391 unsigned, which is usually more efficient. */
4392 if (GET_MODE_SIZE (target_mode
) > GET_MODE_SIZE (compare_mode
))
4394 convert_move (target
, subtarget
,
4395 (GET_MODE_BITSIZE (compare_mode
)
4396 <= HOST_BITS_PER_WIDE_INT
)
4397 && 0 == (STORE_FLAG_VALUE
4398 & ((HOST_WIDE_INT
) 1
4399 << (GET_MODE_BITSIZE (compare_mode
) -1))));
4401 compare_mode
= target_mode
;
4406 /* If we want to keep subexpressions around, don't reuse our
4409 if (preserve_subexpressions_p ())
4412 /* Now normalize to the proper value in COMPARE_MODE. Sometimes
4413 we don't have to do anything. */
4414 if (normalizep
== 0 || normalizep
== STORE_FLAG_VALUE
)
4416 /* STORE_FLAG_VALUE might be the most negative number, so write
4417 the comparison this way to avoid a compiler-time warning. */
4418 else if (- normalizep
== STORE_FLAG_VALUE
)
4419 op0
= expand_unop (compare_mode
, neg_optab
, op0
, subtarget
, 0);
4421 /* We don't want to use STORE_FLAG_VALUE < 0 below since this
4422 makes it hard to use a value of just the sign bit due to
4423 ANSI integer constant typing rules. */
4424 else if (GET_MODE_BITSIZE (compare_mode
) <= HOST_BITS_PER_WIDE_INT
4425 && (STORE_FLAG_VALUE
4426 & ((HOST_WIDE_INT
) 1
4427 << (GET_MODE_BITSIZE (compare_mode
) - 1))))
4428 op0
= expand_shift (RSHIFT_EXPR
, compare_mode
, op0
,
4429 size_int (GET_MODE_BITSIZE (compare_mode
) - 1),
4430 subtarget
, normalizep
== 1);
4431 else if (STORE_FLAG_VALUE
& 1)
4433 op0
= expand_and (op0
, const1_rtx
, subtarget
);
4434 if (normalizep
== -1)
4435 op0
= expand_unop (compare_mode
, neg_optab
, op0
, op0
, 0);
4440 /* If we were converting to a smaller mode, do the
4442 if (target_mode
!= compare_mode
)
4444 convert_move (target
, op0
, 0);
4452 delete_insns_since (last
);
4454 /* If expensive optimizations, use different pseudo registers for each
4455 insn, instead of reusing the same pseudo. This leads to better CSE,
4456 but slows down the compiler, since there are more pseudos */
4457 subtarget
= (!flag_expensive_optimizations
4458 && (target_mode
== mode
)) ? target
: NULL_RTX
;
4460 /* If we reached here, we can't do this with a scc insn. However, there
4461 are some comparisons that can be done directly. For example, if
4462 this is an equality comparison of integers, we can try to exclusive-or
4463 (or subtract) the two operands and use a recursive call to try the
4464 comparison with zero. Don't do any of these cases if branches are
4468 && GET_MODE_CLASS (mode
) == MODE_INT
&& (code
== EQ
|| code
== NE
)
4469 && op1
!= const0_rtx
)
4471 tem
= expand_binop (mode
, xor_optab
, op0
, op1
, subtarget
, 1,
4475 tem
= expand_binop (mode
, sub_optab
, op0
, op1
, subtarget
, 1,
4478 tem
= emit_store_flag (target
, code
, tem
, const0_rtx
,
4479 mode
, unsignedp
, normalizep
);
4481 delete_insns_since (last
);
4485 /* Some other cases we can do are EQ, NE, LE, and GT comparisons with
4486 the constant zero. Reject all other comparisons at this point. Only
4487 do LE and GT if branches are expensive since they are expensive on
4488 2-operand machines. */
4490 if (BRANCH_COST
== 0
4491 || GET_MODE_CLASS (mode
) != MODE_INT
|| op1
!= const0_rtx
4492 || (code
!= EQ
&& code
!= NE
4493 && (BRANCH_COST
<= 1 || (code
!= LE
&& code
!= GT
))))
4496 /* See what we need to return. We can only return a 1, -1, or the
4499 if (normalizep
== 0)
4501 if (STORE_FLAG_VALUE
== 1 || STORE_FLAG_VALUE
== -1)
4502 normalizep
= STORE_FLAG_VALUE
;
4504 else if (GET_MODE_BITSIZE (mode
) <= HOST_BITS_PER_WIDE_INT
4505 && ((STORE_FLAG_VALUE
& GET_MODE_MASK (mode
))
4506 == (unsigned HOST_WIDE_INT
) 1 << (GET_MODE_BITSIZE (mode
) - 1)))
4512 /* Try to put the result of the comparison in the sign bit. Assume we can't
4513 do the necessary operation below. */
4517 /* To see if A <= 0, compute (A | (A - 1)). A <= 0 iff that result has
4518 the sign bit set. */
4522 /* This is destructive, so SUBTARGET can't be OP0. */
4523 if (rtx_equal_p (subtarget
, op0
))
4526 tem
= expand_binop (mode
, sub_optab
, op0
, const1_rtx
, subtarget
, 0,
4529 tem
= expand_binop (mode
, ior_optab
, op0
, tem
, subtarget
, 0,
4533 /* To see if A > 0, compute (((signed) A) << BITS) - A, where BITS is the
4534 number of bits in the mode of OP0, minus one. */
4538 if (rtx_equal_p (subtarget
, op0
))
4541 tem
= expand_shift (RSHIFT_EXPR
, mode
, op0
,
4542 size_int (GET_MODE_BITSIZE (mode
) - 1),
4544 tem
= expand_binop (mode
, sub_optab
, tem
, op0
, subtarget
, 0,
4548 if (code
== EQ
|| code
== NE
)
4550 /* For EQ or NE, one way to do the comparison is to apply an operation
4551 that converts the operand into a positive number if it is non-zero
4552 or zero if it was originally zero. Then, for EQ, we subtract 1 and
4553 for NE we negate. This puts the result in the sign bit. Then we
4554 normalize with a shift, if needed.
4556 Two operations that can do the above actions are ABS and FFS, so try
4557 them. If that doesn't work, and MODE is smaller than a full word,
4558 we can use zero-extension to the wider mode (an unsigned conversion)
4559 as the operation. */
4561 /* Note that ABS doesn't yield a positive number for INT_MIN, but
4562 that is compensated by the subsequent overflow when subtracting
4565 if (abs_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
4566 tem
= expand_unop (mode
, abs_optab
, op0
, subtarget
, 1);
4567 else if (ffs_optab
->handlers
[(int) mode
].insn_code
!= CODE_FOR_nothing
)
4568 tem
= expand_unop (mode
, ffs_optab
, op0
, subtarget
, 1);
4569 else if (GET_MODE_SIZE (mode
) < UNITS_PER_WORD
)
4571 op0
= protect_from_queue (op0
, 0);
4572 tem
= convert_modes (word_mode
, mode
, op0
, 1);
4579 tem
= expand_binop (mode
, sub_optab
, tem
, const1_rtx
, subtarget
,
4582 tem
= expand_unop (mode
, neg_optab
, tem
, subtarget
, 0);
4585 /* If we couldn't do it that way, for NE we can "or" the two's complement
4586 of the value with itself. For EQ, we take the one's complement of
4587 that "or", which is an extra insn, so we only handle EQ if branches
4590 if (tem
== 0 && (code
== NE
|| BRANCH_COST
> 1))
4592 if (rtx_equal_p (subtarget
, op0
))
4595 tem
= expand_unop (mode
, neg_optab
, op0
, subtarget
, 0);
4596 tem
= expand_binop (mode
, ior_optab
, tem
, op0
, subtarget
, 0,
4599 if (tem
&& code
== EQ
)
4600 tem
= expand_unop (mode
, one_cmpl_optab
, tem
, subtarget
, 0);
4604 if (tem
&& normalizep
)
4605 tem
= expand_shift (RSHIFT_EXPR
, mode
, tem
,
4606 size_int (GET_MODE_BITSIZE (mode
) - 1),
4607 subtarget
, normalizep
== 1);
4611 if (GET_MODE (tem
) != target_mode
)
4613 convert_move (target
, tem
, 0);
4616 else if (!subtarget
)
4618 emit_move_insn (target
, tem
);
4623 delete_insns_since (last
);
4628 /* Like emit_store_flag, but always succeeds. */
4631 emit_store_flag_force (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
)
4635 enum machine_mode mode
;
4641 /* First see if emit_store_flag can do the job. */
4642 tem
= emit_store_flag (target
, code
, op0
, op1
, mode
, unsignedp
, normalizep
);
4646 if (normalizep
== 0)
4649 /* If this failed, we have to do this with set/compare/jump/set code. */
4651 if (GET_CODE (target
) != REG
4652 || reg_mentioned_p (target
, op0
) || reg_mentioned_p (target
, op1
))
4653 target
= gen_reg_rtx (GET_MODE (target
));
4655 emit_move_insn (target
, const1_rtx
);
4656 label
= gen_label_rtx ();
4657 do_compare_rtx_and_jump (op0
, op1
, code
, unsignedp
, mode
, NULL_RTX
,
4660 emit_move_insn (target
, const0_rtx
);
4666 /* Perform possibly multi-word comparison and conditional jump to LABEL
4667 if ARG1 OP ARG2 true where ARG1 and ARG2 are of mode MODE
4669 The algorithm is based on the code in expr.c:do_jump.
4671 Note that this does not perform a general comparison. Only variants
4672 generated within expmed.c are correctly handled, others abort (but could
4673 be handled if needed). */
4676 do_cmp_and_jump (arg1
, arg2
, op
, mode
, label
)
4677 rtx arg1
, arg2
, label
;
4679 enum machine_mode mode
;
4681 /* If this mode is an integer too wide to compare properly,
4682 compare word by word. Rely on cse to optimize constant cases. */
4684 if (GET_MODE_CLASS (mode
) == MODE_INT
4685 && ! can_compare_p (op
, mode
, ccp_jump
))
4687 rtx label2
= gen_label_rtx ();
4692 do_jump_by_parts_greater_rtx (mode
, 1, arg2
, arg1
, label2
, label
);
4696 do_jump_by_parts_greater_rtx (mode
, 1, arg1
, arg2
, label
, label2
);
4700 do_jump_by_parts_greater_rtx (mode
, 0, arg2
, arg1
, label2
, label
);
4704 do_jump_by_parts_greater_rtx (mode
, 0, arg1
, arg2
, label2
, label
);
4708 do_jump_by_parts_greater_rtx (mode
, 0, arg2
, arg1
, label
, label2
);
4711 /* do_jump_by_parts_equality_rtx compares with zero. Luckily
4712 that's the only equality operations we do */
4714 if (arg2
!= const0_rtx
|| mode
!= GET_MODE(arg1
))
4716 do_jump_by_parts_equality_rtx (arg1
, label2
, label
);
4720 if (arg2
!= const0_rtx
|| mode
!= GET_MODE(arg1
))
4722 do_jump_by_parts_equality_rtx (arg1
, label
, label2
);
4729 emit_label (label2
);
4732 emit_cmp_and_jump_insns (arg1
, arg2
, op
, NULL_RTX
, mode
, 0, label
);