| blob | 1ae9f0db094e38111d25a15fd68f4ddfe824c494 |
1 2024-03-25 Richard Biener <rguenther@suse.de>
3 * config.gcc (amdgcn): Add gfx1036 entries.
4 * config/gcn/gcn-hsa.h (NO_XNACK): Likewise.
5 (gcn_local_sym_hash): Likewise.
6 * config/gcn/gcn-opts.h (enum processor_type): Likewise.
7 (TARGET_GFX1036): New macro.
8 * config/gcn/gcn.cc (gcn_option_override): Handle gfx1036.
9 (gcn_omp_device_kind_arch_isa): Likewise.
10 (output_file_start): Likewise.
11 * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Add __gfx1036__.
12 (TARGET_CPU_CPP_BUILTINS): Rename __gfx1030 to __gfx1030__.
13 * config/gcn/gcn.opt: Add gfx1036.
14 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1036): New.
15 (main): Handle gfx1036.
16 * config/gcn/t-omp-device: Add gfx1036 isa.
17 * doc/install.texi (amdgcn): Add gfx1036.
18 * doc/invoke.texi (-march): Likewise.
20 2024-03-25 Pan Li <pan2.li@intel.com>
22 * config/riscv/riscv-c.cc (riscv_pragma_intrinsic): Remove error
23 when V is disabled and init the RVV types and intrinic APIs.
24 * config/riscv/riscv-vector-builtins.cc (expand_builtin): Report
25 error if V ext is disabled.
26 * config/riscv/riscv.cc (riscv_return_value_is_vector_type_p):
27 Ditto.
28 (riscv_arguments_is_vector_type_p): Ditto.
29 (riscv_vector_cc_function_p): Ditto.
30 * config/riscv/riscv_vector.h: Remove error if V is disable.
32 2024-03-23 John David Anglin <danglin@gcc.gnu.org>
34 * config/pa/pa.cc (pa_output_global_address): Handle
35 UNSPEC_DLTIND14R addresses.
36 * config/pa/pa.h (PRINT_OPERAND_ADDRESS): Output "RT'" for
37 UNSPEC_DLTIND14R address.
39 2024-03-23 Jakub Jelinek <jakub@redhat.com>
41 PR tree-optimization/114433
42 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): For
43 m_bitfld_load check save_first rather than m_first.
45 2024-03-23 Jakub Jelinek <jakub@redhat.com>
47 PR tree-optimization/114425
48 * gimple-lower-bitint.cc (build_bitint_stmt_ssa_conflicts): Handle
49 _Complex large/huge _BitInt types like the large/huge _BitInt types.
51 2024-03-23 Jakub Jelinek <jakub@redhat.com>
53 PR middle-end/111683
54 * tree-predcom.cc (pcom_worker::suitable_component_p): If has_write
55 and comp_step is RS_NONZERO, return false if any reference in the
56 component doesn't have DR_STEP a multiple of access size.
58 2024-03-23 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
60 * config/xtensa/xtensa.md: Add new split pattern described above.
62 2024-03-22 Georg-Johann Lay <avr@gjlay.de>
64 * config/avr/avr.cc (avr_set_current_function): Adjust diagnostic
65 for deprecated SIGNAL and INTERRUPT usage without respective header.
67 2024-03-22 Andrew Stubbs <ams@baylibre.com>
69 * config/gcn/gcn.md (*memory_barrier): Split into RDNA and !RDNA.
70 (atomic_load<mode>): Adjust RDNA cache settings.
71 (atomic_store<mode>): Likewise.
72 (atomic_exchange<mode>): Likewise.
74 2024-03-22 Andrew Stubbs <ams@baylibre.com>
76 * config/gcn/gcn.cc (gcn_vectorize_preferred_simd_mode): Prefer V32 on
77 RDNA devices.
79 2024-03-22 Andrew Stubbs <ams@baylibre.com>
81 * config.gcc (amdgcn): Add gfx1103 entries.
82 * config/gcn/gcn-hsa.h (NO_XNACK): Likewise.
83 (gcn_local_sym_hash): Likewise.
84 * config/gcn/gcn-opts.h (enum processor_type): Likewise.
85 (TARGET_GFX1103): New macro.
86 * config/gcn/gcn.cc (gcn_option_override): Handle gfx1103.
87 (gcn_omp_device_kind_arch_isa): Likewise.
88 (output_file_start): Likewise.
89 (gcn_hsa_declare_function_name): Use TARGET_RDNA3, not just gfx1100.
90 * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Add __gfx1103__.
91 * config/gcn/gcn.opt: Add gfx1103.
92 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1103): New.
93 (main): Handle gfx1103.
94 * config/gcn/t-omp-device: Add gfx1103 isa.
95 * doc/install.texi (amdgcn): Add gfx1103.
96 * doc/invoke.texi (-march): Likewise.
98 2024-03-22 Andrew Stubbs <ams@baylibre.com>
100 * dojump.cc (do_compare_rtx_and_jump): Clear excess bits in vector
101 bitmasks.
102 (do_compare_and_jump): Remove now-redundant similar code.
103 * internal-fn.cc (expand_fn_using_insn): Clear excess bits in vector
104 bitmasks.
105 (add_mask_and_len_args): Likewise.
107 2024-03-22 Pan Li <pan2.li@intel.com>
109 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Add pre-define
110 macro __riscv_v_fixed_vlen when zvl.
111 * config/riscv/riscv.cc (riscv_handle_rvv_vector_bits_attribute):
112 New static func to take care of the RVV types decorated by
113 the attributes.
115 2024-03-22 Andrew Pinski <quic_apinski@quicinc.com>
117 PR c/109619
118 * builtins.cc (fold_builtin_1): Use error_operand_p
119 instead of checking against ERROR_MARK.
120 (fold_builtin_2): Likewise.
121 (fold_builtin_3): Likewise.
123 2024-03-22 Jakub Jelinek <jakub@redhat.com>
125 PR sanitizer/111736
126 * ubsan.cc (ubsan_expand_null_ifn, instrument_mem_ref): Avoid
127 SANITIZE_NULL instrumentation for non-generic address spaces
128 for which targetm.addr_space.zero_address_valid (as) is true.
130 2024-03-22 Jakub Jelinek <jakub@redhat.com>
132 PR tree-optimization/114405
133 * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
134 Set rprec to limb_prec rather than 0 if tprec is divisible by
135 limb_prec. In the last bf_cur handling, set rprec to (tprec + bo_bit)
136 % limb_prec rather than tprec % limb_prec and use just rprec instead
137 of rprec + bo_bit. For build_bit_field_ref offset, divide
138 (tprec + bo_bit) by limb_prec rather than just tprec.
140 2024-03-22 Christoph Müllner <christoph.muellner@vrull.eu>
142 PR target/114194
143 * config/riscv/vector-iterators.md: Split VI into VI_FRAC and VI_NOFRAC.
144 Only include VI_NOFRAC in V_VLS without TARGET_XTHEADVECTOR.
146 2024-03-22 Jeff Law <jlaw@ventanamicro.com>
148 * config/riscv/riscv.cc (riscv_expand_prologue): Add missing stack
149 tie for scalable and final stack adjustment if needed.
150 Co-authored-by: Raphael Zinsly <rzinsly@ventanamicro.com>
152 2024-03-22 Pan Li <pan2.li@intel.com>
154 PR target/114352
155 * common/config/riscv/riscv-common.cc (struct riscv_func_target_info):
156 New struct for func decl and target name.
157 (struct riscv_func_target_hasher): New hasher for hash table mapping
158 from the fn_decl to fn_target_name.
159 (riscv_func_decl_hash): New func to compute the hash for fn_decl.
160 (riscv_func_target_hasher::hash): New func to impl hash interface.
161 (riscv_func_target_hasher::equal): New func to impl equal interface.
162 (riscv_cmdline_subset_list): New static var for cmdline subset list.
163 (riscv_func_target_table_lazy_init): New func to lazy init the func
164 target hash table.
165 (riscv_func_target_get): New func to get target name from hash table.
166 (riscv_func_target_put): New func to put target name into hash table.
167 (riscv_func_target_remove_and_destory): New func to remove target
168 info from the hash table and destory it.
169 (riscv_parse_arch_string): Set the static var cmdline_subset_list.
170 * config/riscv/riscv-subset.h (riscv_cmdline_subset_list): New static
171 var for cmdline subset list.
172 (riscv_func_target_get): New func decl.
173 (riscv_func_target_put): Ditto.
174 (riscv_func_target_remove_and_destory): Ditto.
175 * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
176 Take cmdline_subset_list instead of current_subset_list when clone.
177 (riscv_process_target_attr): Record the func target info to hash table.
178 (riscv_option_valid_attribute_p): Add new arg tree fndel.
179 * config/riscv/riscv.cc (riscv_declare_function_name): Consume the
180 func target info and print the arch message.
182 2024-03-22 Pan Li <pan2.li@intel.com>
184 PR target/114352
185 * common/config/riscv/riscv-common.cc (riscv_subset_list::parse):
186 Replace implied, combine and check to func finalize.
187 (riscv_subset_list::finalize): New func impl to take care of
188 implied, combine ext and related checks.
189 * config/riscv/riscv-subset.h: Add func decl for finalize.
190 * config/riscv/riscv-target-attr.cc (riscv_target_attr_parser::parse_arch):
191 Finalize the ext before return succeed.
192 * config/riscv/riscv.cc (riscv_set_current_function): Reinit the
193 machine mode before when set cur function.
195 2024-03-21 Andrew Stubbs <ams@baylibre.com>
197 * config/gcn/gcn.cc (gcn_expand_builtin_1): Comment correction.
199 2024-03-21 Andrew Stubbs <ams@baylibre.com>
201 * config/gcn/gcn-hsa.h (ASM_SPEC): Pass -mattr=+cumode.
203 2024-03-21 Andrew Stubbs <ams@baylibre.com>
205 * config/gcn/gcn-run.cc (main): Add an hsa_memory_free calls for each
206 device_malloc call.
208 2024-03-21 liuhongt <hongtao.liu@intel.com>
210 PR tree-optimization/114396
211 * tree-vect-loop.cc (vect_peel_nonlinear_iv_init): Pass utype
212 and true to wi::from_mpz.
214 2024-03-21 Richard Biener <rguenther@suse.de>
216 PR tree-optimization/111736
217 * asan.cc (instrument_derefs): Do not instrument accesses
218 to non-generic address-spaces.
220 2024-03-21 Richard Biener <rguenther@suse.de>
222 PR tree-optimization/113727
223 * tree-sra.cc (analyze_access_subtree): Do not allow
224 replacements in subtrees when grp_partial_lhs.
226 2024-03-21 liuhongt <hongtao.liu@intel.com>
228 PR middle-end/114347
229 * doc/invoke.texi: Document -fexcess-precision=16.
231 2024-03-20 Cupertino Miranda <cupertino.miranda@oracle.com>
233 * config/bpf/core-builtins.cc (bpf_core_get_index): Check if
234 field contains a DECL_NAME.
236 2024-03-20 Cupertino Miranda <cupertino.miranda@oracle.com>
238 * config/bpf/btfext-out.cc (cpf_core_reloc_add): Correct for new code.
239 Add assert to validate the string is set.
240 * config/bpf/core-builtins.cc (cr_final): Make string struct
241 field as const.
242 (process_enum_value): Correct for field type change.
243 (process_type): Set access string to "0".
245 2024-03-20 Cupertino Miranda <cupertino.miranda@oracle.com>
247 * config/bpf/core-builtins.cc (core_field_info): Add
248 support for POINTER_PLUS_EXPR in the root of the field expression.
249 (bpf_core_get_index): Likewise.
250 (pack_field_expr): Make the BTF type to point to the structure
251 related node, instead of its pointer type.
252 (make_core_safe_access_index): Correct to new code.
254 2024-03-20 Xi Ruoyao <xry111@xry111.site>
256 PR target/114407
257 * config/loongarch/loongarch-opts.cc (loongarch_config_target):
258 Fix typo in diagnostic message, enabing -> enabling.
260 2024-03-20 Jakub Jelinek <jakub@redhat.com>
262 PR target/114175
263 * config/visium/visium.cc (visium_setup_incoming_varargs): Only skip
264 TARGET_FUNCTION_ARG_ADVANCE for TYPE_NO_NAMED_ARGS_STDARG_P functions
265 if arg.type is NULL.
267 2024-03-20 Jakub Jelinek <jakub@redhat.com>
269 PR target/114175
270 * config/nios2/nios2.cc (nios2_setup_incoming_varargs): Only skip
271 nios2_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
272 if arg.type is NULL.
274 2024-03-20 Jakub Jelinek <jakub@redhat.com>
276 PR target/114175
277 * config/nds32/nds32.cc (nds32_setup_incoming_varargs): Only skip
278 function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
279 if arg.type is NULL.
281 2024-03-20 Jakub Jelinek <jakub@redhat.com>
283 PR target/114175
284 * config/m32r/m32r.cc (m32r_setup_incoming_varargs): Only skip
285 function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
286 if arg.type is NULL.
288 2024-03-20 Jakub Jelinek <jakub@redhat.com>
290 PR target/114175
291 * config/ft32/ft32.cc (ft32_setup_incoming_varargs): Only skip
292 function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
293 if arg.type is NULL.
295 2024-03-20 Jakub Jelinek <jakub@redhat.com>
297 PR target/114175
298 * config/epiphany/epiphany.cc (epiphany_setup_incoming_varargs): Only
299 skip function arg advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
300 if arg.type is NULL.
302 2024-03-20 Jakub Jelinek <jakub@redhat.com>
304 PR target/114175
305 * config/csky/csky.cc (csky_setup_incoming_varargs): Only skip
306 csky_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
307 if arg.type is NULL.
309 2024-03-20 Yury Khrustalev <yury.khrustalev@arm.com>
311 * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
313 2024-03-20 Jakub Jelinek <jakub@redhat.com>
315 PR tree-optimization/114365
316 * gimple-lower-bitint.cc (bitint_large_huge::handle_load): When adding
317 a PHI node, set iv2 to its result afterwards.
319 2024-03-20 Jakub Jelinek <jakub@redhat.com>
321 * tree-ssa-loop-ch.cc (update_profile_after_ch): Fix comment typo:
322 probabbility -> probability.
323 (ch_base::copy_headers): Fix comment typo: itrations -> iterations.
325 2024-03-20 Jakub Jelinek <jakub@redhat.com>
327 PR bootstrap/114369
328 * system.h (vec_step): Define to vec_step_ when compiling
329 with clang on PowerPC.
331 2024-03-20 demin.han <demin.han@starfivetech.com>
333 PR target/112651
334 * config/riscv/riscv-opts.h (enum riscv_autovec_lmul_enum): Rename
335 (enum rvv_max_lmul_enum): Ditto
336 (TARGET_MAX_LMUL): Ditto
337 * config/riscv/riscv-v.cc (preferred_simd_mode): Ditto
338 * config/riscv/riscv-vector-costs.cc (costs::record_potential_unexpected_spills): Ditto
339 (costs::better_main_loop_than_p): Ditto
340 * config/riscv/riscv.opt: Replace -param=riscv-autovec-lmul with -mrvv-max-lmul
342 2024-03-20 Richard Biener <rguenther@suse.de>
344 PR middle-end/113396
345 * tree-dfa.cc (get_ref_base_and_extent): Use index range
346 bounds only if they fit within the address-range constraints
347 of offset_int.
349 2024-03-20 Chenghui Pan <panchenghui@loongson.cn>
351 * config/loongarch/loongarch.cc
352 (loongarch_hard_regno_mode_ok_uncached): Combine UNITS_PER_FP_REG and
353 UNITS_PER_FPREG macros.
354 (loongarch_hard_regno_nregs): Ditto.
355 (loongarch_class_max_nregs): Ditto.
356 (loongarch_get_separate_components): Ditto.
357 (loongarch_process_components): Ditto.
358 * config/loongarch/loongarch.h (UNITS_PER_FPREG): Ditto.
359 (UNITS_PER_HWFPVALUE): Ditto.
360 (UNITS_PER_FPVALUE): Ditto.
362 2024-03-20 Chenghui Pan <panchenghui@loongson.cn>
364 * config/loongarch/lasx.md (vec_cmp<mode><mode256_i>): Remove checking
365 of loongarch_expand_vec_cmp()'s return value.
366 (vec_cmpu<ILASX:mode><mode256_i>): Ditto.
367 * config/loongarch/lsx.md (vec_cmp<mode><mode_i>): Ditto.
368 (vec_cmpu<ILSX:mode><mode_i>): Ditto.
369 * config/loongarch/loongarch-protos.h
370 (loongarch_expand_vec_cmp): Change loongarch_expand_vec_cmp()'s return
371 type from bool to void.
372 * config/loongarch/loongarch.cc (loongarch_expand_vec_cmp): Ditto.
374 2024-03-20 Chenghui Pan <panchenghui@loongson.cn>
376 * config/loongarch/loongarch-protos.h
377 (loongarch_cfun_has_cprestore_slot_p): Delete.
378 (loongarch_adjust_insn_length): Delete.
379 (current_section_name): Delete.
380 (loongarch_split_symbol_type): Delete.
381 * config/loongarch/loongarch.cc
382 (loongarch_case_values_threshold): Delete.
383 (loongarch_spill_class): Delete.
384 (TARGET_OPTAB_SUPPORTED_P): Delete.
385 (TARGET_CASE_VALUES_THRESHOLD): Delete.
386 (TARGET_SPILL_CLASS): Delete.
388 2024-03-20 Lewis Hyatt <lhyatt@gmail.com>
390 PR c++/111918
391 * diagnostic-core.h (enum diagnostic_t): Add DK_ANY special flag.
392 * diagnostic.cc (diagnostic_option_classifier::classify_diagnostic):
393 Make use of DK_ANY to indicate a diagnostic was initially enabled.
394 (diagnostic_context::diagnostic_enabled): Do not change the type of
395 a diagnostic if the saved classification is type DK_ANY.
397 2024-03-19 Martin Jambor <mjambor@suse.cz>
399 PR ipa/108802
400 PR ipa/114254
401 * ipa-prop.cc (ipa_get_stmt_member_ptr_load_param): Fix case looking
402 at COMPONENT_REFs directly from a PARM_DECL, also recognize loads from
403 a pointer parameter.
404 (ipa_analyze_indirect_call_uses): Also recognize loads from a pointer
405 parameter, also recognize the case when pfn pointer is loaded in its
406 own BB.
408 2024-03-19 Vladimir N. Makarov <vmakarov@redhat.com>
410 PR target/99829
411 * lra-constraints.cc (lra_constraints): Prevent removing insn
412 with reverse equivalence to memory if the memory was reloaded.
414 2024-03-19 David Malcolm <dmalcolm@redhat.com>
416 PR middle-end/114348
417 * diagnostic-format-json.cc
418 (json_stderr_output_format::machine_readable_stderr_p): New.
419 (json_file_output_format::machine_readable_stderr_p): New.
420 * diagnostic-format-sarif.cc
421 (sarif_stream_output_format::machine_readable_stderr_p): New.
422 (sarif_file_output_format::machine_readable_stderr_p): New.
423 * diagnostic.cc (diagnostic_context::action_after_output): Move
424 "fnotice" to before "finish" call, so that we still have the
425 diagnostic_context.
426 (fnotice): Bail out if the user requested one of the
427 machine-readable diagnostic output formats on stderr.
428 * diagnostic.h
429 (diagnostic_output_format::machine_readable_stderr_p): New pure
430 virtual function.
431 (diagnostic_text_output_format::machine_readable_stderr_p): New.
432 (diagnostic_context::get_output_format): New accessor.
434 2024-03-19 Edwin Lu <ewlu@rivosinc.com>
436 PR target/114175
437 * config/riscv/riscv.cc (riscv_setup_incoming_varargs): Only skip
438 riscv_funciton_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
439 if arg.type is NULL
441 2024-03-19 Jonathan Wakely <jwakely@redhat.com>
443 * doc/install.texi (Prerequisites): Document use of autogen for
444 libstdc++.
446 2024-03-19 Richard Biener <rguenther@suse.de>
448 PR tree-optimization/114151
449 PR tree-optimization/114269
450 PR tree-optimization/114322
451 PR tree-optimization/114074
452 * tree-chrec.cc (chrec_fold_multiply): Restrict the use of
453 unsigned arithmetic when actual overflow on constant operands
454 is observed.
456 2024-03-19 Jakub Jelinek <jakub@redhat.com>
458 PR target/114175
459 * config/arc/arc.cc (arc_setup_incoming_varargs): Only skip
460 arc_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
461 if arg.type is NULL.
463 2024-03-19 Xi Ruoyao <xry111@xry111.site>
465 PR target/114175
466 * config/loongarch/loongarch.cc
467 (loongarch_setup_incoming_varargs): Only skip
468 loongarch_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P
469 functions if arg.type is NULL.
471 2024-03-19 Christophe Lyon <christophe.lyon@linaro.org>
473 PR target/114323
474 * config/arm/arm-mve-builtins.cc
475 (function_instance::reads_global_state_p): Take CP_READ_MEMORY
476 into account.
478 2024-03-19 Jakub Jelinek <jakub@redhat.com>
480 PR target/114175
481 * config/alpha/alpha.cc (alpha_setup_incoming_varargs): Only skip
482 function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
483 if arg.type is NULL.
485 2024-03-19 Jakub Jelinek <jakub@redhat.com>
487 PR target/114175
488 * config/rs6000/rs6000-call.cc (setup_incoming_varargs): Only skip
489 rs6000_function_arg_advance_1 for TYPE_NO_NAMED_ARGS_STDARG_P functions
490 if arg.type is NULL.
492 2024-03-19 Richard Biener <rguenther@suse.de>
494 PR tree-optimization/114375
495 * tree-vect-slp.cc (vect_build_slp_tree_2): Compute the
496 load permutation for masked loads but reject it when any
497 such is necessary.
498 * tree-vect-stmts.cc (vectorizable_load): Reject masked
499 VMAT_ELEMENTWISE and VMAT_STRIDED_SLP as those are not
500 supported.
502 2024-03-19 Mary Bennett <mary.bennett@embecosm.com>
504 * common/config/riscv/riscv-common.cc: Create XCVbi extension
505 support.
506 * config/riscv/riscv.opt: Likewise.
507 * config/riscv/corev.md: Implement cv_branch<mode> pattern
508 for cv.beqimm and cv.bneimm.
509 * config/riscv/riscv.md: Add CORE-V branch immediate to RISC-V
510 branch instruction pattern.
511 * config/riscv/constraints.md: Implement constraints
512 cv_bi_s5 - signed 5-bit immediate.
513 * config/riscv/predicates.md: Implement predicate
514 const_int5s_operand - signed 5 bit immediate.
515 * doc/sourcebuild.texi: Add XCVbi documentation.
517 2024-03-19 Chen Jiawei <jiawei@iscas.ac.cn>
519 * config/riscv/riscv-cores.def (RISCV_TUNE): New def.
520 (RISCV_CORE): Ditto.
521 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): New
522 option.
523 * config/riscv/riscv.cc: New def.
524 * config/riscv/riscv.md: New include.
525 * config/riscv/xiangshan.md: New file.
527 2024-03-18 David Malcolm <dmalcolm@redhat.com>
529 PR analyzer/110902
530 PR analyzer/110928
531 PR analyzer/111305
532 PR analyzer/111441
533 * selftest.h (ASSERT_NE_AT): New macro.
535 2024-03-18 Uros Bizjak <ubizjak@gmail.com>
537 PR target/111822
538 * config/i386/i386-features.cc (smode_convert_cst): New function
539 to handle SImode, DImode and TImode immediates, generalized from
540 timode_convert_cst.
541 (timode_convert_cst): Remove.
542 (scalar_chain::convert_op): Unify from
543 general_scalar_chain::convert_op and timode_scalar_chain::convert_op.
544 (general_scalar_chain::convert_op): Remove.
545 (timode_scalar_chain::convert_op): Remove.
546 (timode_scalar_chain::convert_insn): Update the call to
547 renamed timode_convert_cst.
548 * config/i386/i386-features.h (class scalar_chain):
549 Redeclare convert_op as protected class member.
550 (class general_calar_chain): Remove convert_op.
551 (class timode_scalar_chain): Ditto.
553 2024-03-18 Jan Hubicka <jh@suse.cz>
555 * config/i386/zn4zn5.md: Add file missed in the previous commit.
557 2024-03-18 Jan Hubicka <jh@suse.cz>
558 Karthiban Anbazhagan <Karthiban.Anbazhagan@amd.com>
560 * common/config/i386/cpuinfo.h (get_amd_cpu): Recognize znver5.
561 * common/config/i386/i386-common.cc (processor_names): Add znver5.
562 (processor_alias_table): Likewise.
563 * common/config/i386/i386-cpuinfo.h (processor_types): Add new zen
564 family.
565 (processor_subtypes): Add znver5.
566 * config.gcc (x86_64-*-* |...): Likewise.
567 * config/i386/driver-i386.cc (host_detect_local_cpu): Let
568 march=native detect znver5 cpu's.
569 * config/i386/i386-c.cc (ix86_target_macros_internal): Add
570 znver5.
571 * config/i386/i386-options.cc (m_ZNVER5): New definition
572 (processor_cost_table): Add znver5.
573 * config/i386/i386.cc (ix86_reassociation_width): Likewise.
574 * config/i386/i386.h (processor_type): Add PROCESSOR_ZNVER5
575 (PTA_ZNVER5): New definition.
576 * config/i386/i386.md (define_attr "cpu"): Add znver5.
577 (Scheduling descriptions) Add znver5.md.
578 * config/i386/x86-tune-costs.h (znver5_cost): New definition.
579 * config/i386/x86-tune-sched.cc (ix86_issue_rate): Add znver5.
580 (ix86_adjust_cost): Likewise.
581 * config/i386/x86-tune.def (avx512_move_by_pieces): Add m_ZNVER5.
582 (avx512_store_by_pieces): Add m_ZNVER5.
583 * doc/extend.texi: Add znver5.
584 * doc/invoke.texi: Likewise.
585 * config/i386/znver4.md: Rename to zn4zn5.md; combine znver4 and znver5 Scheduler.
587 2024-03-18 Georg-Johann Lay <avr@gjlay.de>
589 * config/avr/constraints.md (CX2, CX3, CX4): New constraints.
590 * config/avr/avr-protos.h (avr_xor_noclobber_dconst): New proto.
591 * config/avr/avr.cc (avr_xor_noclobber_dconst): New function.
592 * config/avr/avr.md (xorhi3, *xorhi3): Add "d,0,CX2,X" alternative.
593 (xorpsi3, *xorpsi3): Add "d,0,CX3,X" alternative.
594 (xorsi3, *xorsi3): Add "d,0,CX4,X" alternative.
596 2024-03-18 liuhongt <hongtao.liu@intel.com>
598 PR target/114334
599 * config/i386/i386.md (mode): Add new number V8BF,V16BF,V32BF.
600 (MODEF248): New mode iterator.
601 (ssevecmodesuffix): Hanlde BF and HF.
602 * config/i386/sse.md (andnot<mode>3): Extend to HF/BF.
603 (<code><mode>3): Ditto.
605 2024-03-18 John David Anglin <danglin@gcc.gnu.org>
607 PR rtl-optimization/112415
608 * config/pa/pa.cc (pa_emit_move_sequence): Revise condition
609 for symbolic memory operands.
610 (pa_legitimate_address_p): Revise LO_SUM condition.
611 * config/pa/pa.h (INT14_OK_STRICT): Revise define. Move
612 comment about GNU linker to predicates.md.
613 * config/pa/predicates.md (floating_point_store_memory_operand):
614 Revise condition for symbolic memory operands. Update
615 comment.
617 2024-03-17 John David Anglin <danglin@gcc.gnu.org>
619 * config/pa/pa.cc (pa_delegitimize_address): Delegitimize UNSPEC_TP.
621 2024-03-16 Jakub Jelinek <jakub@redhat.com>
623 PR target/114175
624 * config/i386/i386.cc (ix86_setup_incoming_varargs): Only skip
625 ix86_function_arg_advance for TYPE_NO_NAMED_ARGS_STDARG_P functions
626 if arg.type is NULL.
628 2024-03-16 Jakub Jelinek <jakub@redhat.com>
630 PR tree-optimization/114329
631 * gimple-lower-bitint.cc (struct bitint_large_huge): Declare
632 build_bit_field_ref method.
633 (bitint_large_huge::build_bit_field_ref): New method.
634 (bitint_large_huge::lower_mergeable_stmt): Use it.
636 2024-03-15 YunQiang Su <syq@gcc.gnu.org>
638 * config/riscv/riscv.opt.urls: Regenerated.
639 * config/rs6000/sysv4.opt.urls: Likewise.
640 * config/xtensa/xtensa.opt.urls: Likewise.
642 2024-03-15 Jakub Jelinek <jakub@redhat.com>
644 * lower-subreg.cc (resolve_simple_move): Fix comment typo,
645 betwee -> between.
646 * edit-context.cc (class line_event): Fix comment typo,
647 betweeen -> between.
649 2024-03-15 Jakub Jelinek <jakub@redhat.com>
651 PR target/114339
652 * config/i386/i386-expand.cc (ix86_expand_int_sse_cmp) <case LE>: Fix
653 a pasto, compare code against LE rather than GE.
655 2024-03-15 Joe Ramsay <Joe.Ramsay@arm.com>
657 * match.pd: Fix truncation pattern for -fno-signed-zeroes
659 2024-03-15 Jakub Jelinek <jakub@redhat.com>
661 PR middle-end/114332
662 * expr.cc (expand_expr_real_1): EXTEND_BITINT also CALL_EXPR results.
664 2024-03-15 Jakub Jelinek <jakub@redhat.com>
666 PR tree-optimization/113466
667 * gimple-lower-bitint.cc (bitint_large_huge): Add m_returns_twice_calls
668 member.
669 (bitint_large_huge::bitint_large_huge): Initialize it.
670 (bitint_large_huge::~bitint_large_huge): Release it.
671 (bitint_large_huge::lower_call): Remember ECF_RETURNS_TWICE call stmts
672 before which at least one statement has been inserted.
673 (gimple_lower_bitint): Move argument loads before ECF_RETURNS_TWICE
674 calls to a different block and add corresponding PHIs.
676 2024-03-15 YunQiang Su <syq@gcc.gnu.org>
678 * config/mips/mips.opt: Support -mstrict-align, and use
679 TARGET_STRICT_ALIGN as the flag; keep -m(no-)unaligned-access
680 as alias.
681 * config/mips/mips.h: Use TARGET_STRICT_ALIGN.
682 * config/mips/mips.opt.urls: Regenerate.
683 * doc/invoke.texi: Document -m(no-)strict-algin for MIPSr6.
685 2024-03-15 Tejas Belagod <tejas.belagod@arm.com>
687 PR middle-end/114108
688 * tree-vect-patterns.cc (vect_recog_abd_pattern): Call
689 vect_convert_output with the correct vecitype.
691 2024-03-15 Chenghui Pan <panchenghui@loongson.cn>
693 * config/loongarch/lasx.md (lasx_xvpermi_q_<LASX:mode>):
694 Remove masking of operand 3.
696 2024-03-14 Jason Merrill <jason@redhat.com>
698 * tree-core.h (enum clobber_kind): Clarify CLOBBER_OBJECT_*
699 comments.
701 2024-03-14 John David Anglin <danglin@gcc.gnu.org>
703 PR target/114288
704 * config/pa/pa.cc (pa_legitimate_address_p): Don't allow
705 14-bit displacements before reload for modes that may use
706 a floating-point load or store.
708 2024-03-14 David Faust <david.faust@oracle.com>
710 * config/bpf/bpf.h (INT8_TYPE): Change to signed char.
712 2024-03-14 Max Filippov <jcmvbkbc@gmail.com>
714 * config/xtensa/xtensa.md (movsi_internal): Move l32i and s32i
715 patterns ahead of the l32i.n and s32i.n.
717 2024-03-14 Jakub Jelinek <jakub@redhat.com>
719 * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): Fix comment typo.
721 2024-03-14 Jakub Jelinek <jakub@redhat.com>
723 PR middle-end/113907
724 * ipa-icf.cc (sem_item_optimizer::merge_classes): Reset
725 SSA_NAME_RANGE_INFO and SSA_NAME_PTR_INFO on successfully ICF merged
726 functions.
728 2024-03-14 Xi Ruoyao <xry111@xry111.site>
730 * config/loongarch/loongarch.md (any_ge): Remove.
731 (sge<u>_<X:mode><GPR:mode>): Remove.
733 2024-03-14 Jakub Jelinek <jakub@redhat.com>
735 PR target/114310
736 * config/aarch64/aarch64.cc (aarch64_expand_compare_and_swap): For
737 TImode force newval into a register.
739 2024-03-14 Chung-Lin Tang <cltang@baylibre.com>
741 * tree.h (OMP_CLAUSE_MAP_READONLY): New macro.
742 (OMP_CLAUSE__CACHE__READONLY): New macro.
743 * tree-core.h (struct GTY(()) tree_base): Adjust comments for new
744 uses of readonly_flag bit in OMP_CLAUSE_MAP_READONLY and
745 OMP_CLAUSE__CACHE__READONLY.
746 * tree-pretty-print.cc (dump_omp_clause): Add support for printing
747 OMP_CLAUSE_MAP_READONLY and OMP_CLAUSE__CACHE__READONLY.
749 2024-03-14 Andreas Krebbel <krebbel@linux.ibm.com>
751 * config/s390/s390.cc (s390_encode_section_info): Adjust the check
752 for misaligned symbols.
753 * config/s390/s390.opt: Improve documentation.
755 2024-03-14 Jakub Jelinek <jakub@redhat.com>
757 * gimple-iterator.cc (edge_before_returns_twice_call): Copy all
758 flags and probability from ad_edge to e edge. If CDI_DOMINATORS
759 are computed, recompute immediate dominator of other_edge->src
760 and other_edge->dest.
761 (gsi_safe_insert_before, gsi_safe_insert_seq_before): Update *iter
762 for the returns_twice call case to the gsi_for_stmt (stmt) to deal
763 with update it for bb splitting.
765 2024-03-14 liuhongt <hongtao.liu@intel.com>
767 * config/i386/i386-features.cc
768 (general_scalar_chain::convert_op): Handle REG_EH_REGION note.
769 (convert_scalars_to_vector): Ditto.
770 * config/i386/i386-features.h (class scalar_chain): New
771 memeber control_flow_insns.
773 2024-03-13 Jakub Jelinek <jakub@redhat.com>
775 PR middle-end/114319
776 * gimple-ssa-store-merging.cc
777 (imm_store_chain_info::try_coalesce_bswap): For 32-bit targets
778 allow matching __builtin_bswap64 if there is bswapsi2 optab.
780 2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
782 * config/s390/s390.cc (s390_secondary_reload): Guard
783 SYMBOL_FLAG_NOTALIGN2_P.
785 2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
787 * config/s390/s390-builtin-types.def: Update to reflect latest
788 changes.
789 * config/s390/s390-builtins.def: Streamline vector builtins with
790 LLVM.
792 2024-03-13 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
794 * config/s390/s390-builtins.def (vec_permi): Deprecate.
795 (vec_ctd): Deprecate.
796 (vec_ctd_s64): Deprecate.
797 (vec_ctd_u64): Deprecate.
798 (vec_ctsl): Deprecate.
799 (vec_ctul): Deprecate.
800 (vec_ld2f): Deprecate.
801 (vec_st2f): Deprecate.
802 (vec_insert): Deprecate overloads with bool vectors.
804 2024-03-13 Jakub Jelinek <jakub@redhat.com>
806 PR middle-end/114313
807 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
808 TYPE_SIZE of TREE_TYPE (var) rather than TYPE_SIZE of type.
809 (bitint_large_huge::handle_load): Pass NULL_TREE rather than
810 rhs_type to limb_access for the bitfield load cases.
811 (bitint_large_huge::lower_mergeable_stmt): Pass NULL_TREE rather than
812 lhs_type to limb_access if nlhs is non-NULL.
814 2024-03-13 Jakub Jelinek <jakub@redhat.com>
816 PR sanitizer/112709
817 * asan.cc (maybe_create_ssa_name, maybe_cast_to_ptrmode,
818 build_check_stmt, maybe_instrument_call, asan_expand_mark_ifn): Use
819 gsi_safe_insert_before instead of gsi_insert_before.
821 2024-03-13 Jakub Jelinek <jakub@redhat.com>
823 PR sanitizer/112709
824 * gimple-iterator.h (gsi_safe_insert_before,
825 gsi_safe_insert_seq_before): Declare.
826 * gimple-iterator.cc: Include gimplify.h.
827 (edge_before_returns_twice_call, adjust_before_returns_twice_call,
828 gsi_safe_insert_before, gsi_safe_insert_seq_before): New functions.
829 * ubsan.cc (instrument_mem_ref, instrument_pointer_overflow,
830 instrument_nonnull_arg, instrument_nonnull_return): Use
831 gsi_safe_insert_before instead of gsi_insert_before.
832 (maybe_instrument_pointer_overflow): Use force_gimple_operand,
833 gimple_seq_add_seq_without_update and gsi_safe_insert_seq_before
834 instead of force_gimple_operand_gsi.
835 (instrument_object_size): Likewise. Use gsi_safe_insert_before
836 instead of gsi_insert_before.
838 2024-03-12 Richard Biener <rguenther@suse.de>
840 PR tree-optimization/114121
841 * tree-chrec.cc (chrec_fold_plus_1): Guard recursion with
842 converted operand properly.
843 (chrec_fold_multiply): Likewise. Handle missed recursion.
845 2024-03-12 Jakub Jelinek <jakub@redhat.com>
847 PR sanitizer/112709
848 * asan.cc (has_stmt_been_instrumented_p): Don't instrument call
849 stores on the caller side unless it is a call to a builtin or
850 internal function or function doesn't return by hidden reference.
851 (maybe_instrument_call): Likewise.
852 (instrument_derefs): Instrument stores to RESULT_DECL if
853 returning by hidden reference.
855 2024-03-12 Jakub Jelinek <jakub@redhat.com>
857 PR tree-optimization/114293
858 * tree-ssa-strlen.cc (strlen_pass::handle_builtin_strlen): If
859 max is smaller than min, set max to ~(size_t)0.
861 2024-03-12 Pan Li <pan2.li@intel.com>
863 * config/riscv/riscv-c.cc (riscv_ext_version_value): Fix
864 code style greater than 80 chars.
865 (riscv_cpu_cpp_builtins): Fix useless empty line, indent
866 with 3 space(s) and argument unalignment.
868 2024-03-12 Richard Biener <rguenther@suse.de>
870 PR tree-optimization/114297
871 * tree-vect-loop.cc (vectorizable_live_operation): Pass in the
872 live stmts SLP node to vect_create_epilog_for_reduction.
874 2024-03-12 Andrew Pinski <quic_apinski@quicinc.com>
876 PR driver/114314
877 * common.opt (fmultiflags): Add RejectNegative.
879 2024-03-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
881 * config/aarch64/aarch64.md: Rename aarch_ to aarch64_.
882 * config/aarch64/aarch64.opt: Likewise.
883 * config/aarch64/aarch64-c.cc (aarch64_update_cpp_builtins): Likewise.
884 * config/aarch64/aarch64.cc (aarch64_expand_prologue): Likewise.
885 (aarch64_expand_epilogue): Likewise.
886 (aarch64_post_cfi_startproc): Likewise.
887 (aarch64_handle_no_branch_protection): Copy and rename.
888 (aarch64_handle_standard_branch_protection): Likewise.
889 (aarch64_handle_pac_ret_protection): Likewise.
890 (aarch64_handle_pac_ret_leaf): Likewise.
891 (aarch64_handle_pac_ret_b_key): Likewise.
892 (aarch64_handle_bti_protection): Likewise.
893 (aarch64_override_options): Update branch protection validation.
894 (aarch64_handle_attr_branch_protection): Likewise.
895 * config/arm/aarch-common-protos.h (aarch_validate_mbranch_protection):
896 Pass branch protection type description as argument.
897 (struct aarch_branch_protect_type): Move from aarch-common.h.
898 * config/arm/aarch-common.cc (aarch_handle_no_branch_protection):
899 Remove.
900 (aarch_handle_standard_branch_protection): Remove.
901 (aarch_handle_pac_ret_protection): Remove.
902 (aarch_handle_pac_ret_leaf): Remove.
903 (aarch_handle_pac_ret_b_key): Remove.
904 (aarch_handle_bti_protection): Remove.
905 (aarch_validate_mbranch_protection): Pass branch protection type
906 description as argument.
907 * config/arm/aarch-common.h (enum aarch_key_type): Remove.
908 (struct aarch_branch_protect_type): Remove.
909 * config/arm/arm-c.cc (arm_cpu_builtins): Remove aarch_ra_sign_key.
910 * config/arm/arm.cc (arm_handle_no_branch_protection): Copy and rename.
911 (arm_handle_standard_branch_protection): Likewise.
912 (arm_handle_pac_ret_protection): Likewise.
913 (arm_handle_pac_ret_leaf): Likewise.
914 (arm_handle_bti_protection): Likewise.
915 (arm_configure_build_target): Update branch protection validation.
916 * config/arm/arm.opt: Remove aarch_ra_sign_key.
918 2024-03-11 Richard Biener <rguenther@suse.de>
920 PR middle-end/114299
921 * gimplify.cc (internal_get_tmp_var): When gimplification
922 of VAL failed, return a decl.
924 2024-03-11 Jakub Jelinek <jakub@redhat.com>
926 PR tree-optimization/114278
927 * tree-ssa.cc (maybe_optimize_var): If large/huge _BitInt vars are no
928 longer addressable, set DECL_NOT_GIMPLE_REG_P on them.
930 2024-03-11 Eric Botcazou <ebotcazou@adacore.com>
932 PR debug/113519
933 PR debug/113777
934 * dwarf2out.cc (gen_enumeration_type_die): In the reverse case,
935 generate the DIE with the same parent as in the regular case.
937 2024-03-11 Andrew Pinski <quic_apinski@quicinc.com>
939 PR middle-end/95351
940 * fold-const.cc (merge_truthop_with_opposite_arm): Use
941 the type of the operands of the comparison and not the type
942 of the comparison.
944 2024-03-10 jlaw <jeffreyalaw@gmail.com>
946 PR tree-optimization/110199
947 * tree-ssa-scopedtables.cc
948 (avail_exprs_stack::simplify_binary_operation): Generalize handling
949 of MIN_EXPR/MAX_EXPR to allow additional simplifications. Canonicalize
950 comparison operands for other cases.
952 2024-03-10 Pan Li <pan2.li@intel.com>
954 * tree-vect-stmts.cc (vectorizable_store): Enable the assert
955 during transform process.
956 (vectorizable_load): Ditto.
958 2024-03-10 jlaw <jeffreyalaw@gmail.com>
960 PR target/102250
961 * doc/install.texi: Document need for python when building
962 RISC-V compilers.
964 2024-03-10 jlaw <jeffreyalaw@gmail.com>
966 PR target/111362
967 * mode-switching.cc (optimize_mode_switching): Only process
968 NONDEBUG insns.
970 2024-03-09 Georg-Johann Lay <avr@gjlay.de>
972 * config/avr/avr.md: Fix typos in comment, indentation glitches
973 and some other nits.
975 2024-03-09 Jakub Jelinek <jakub@redhat.com>
977 PR target/114284
978 * fwprop.cc (try_fwprop_subst_pattern): Don't propagate
979 src containing MEMs unless prop.likely_profitable_p ().
981 2024-03-09 Xi Ruoyao <xry111@xry111.site>
983 * config/loongarch/loongarch.cc (loongarch_print_operand_reloc):
984 Support 'Q' for R_LARCH_RELAX for TLS IE.
985 (loongarch_output_move): Use 'Q' to print R_LARCH_RELAX for TLS
986 IE.
987 * config/loongarch/loongarch.md (ld_from_got<mode>): Likewise.
989 2024-03-09 Georg-Johann Lay <avr@gjlay.de>
991 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Determine cost for
992 usum_widenqihi and add_zero_extend1.
993 [MINUS]: Determine costs for udiff_widenqihi, sub+zero_extend,
994 sub+sign_extend.
995 * config/avr/avr.md (*addhi3.sign_extend1, *subhi3.sign_extend2):
996 Compute exact insn lengths.
997 (*usum_widenqihi3): Allow input operands to commute.
999 2024-03-09 Jakub Jelinek <jakub@redhat.com>
1001 * config/i386/i386.opt.urls: Regenerate.
1003 2024-03-09 Lulu Cheng <chenglulu@loongson.cn>
1005 * config/loongarch/sync.md (atomic_cas_value_strong<mode>):
1006 In loongarch64, a sign extension operation is added when
1007 operands[2] is a register operand and the mode is SImode.
1009 2024-03-08 Martin Jambor <mjambor@suse.cz>
1011 PR ipa/113757
1012 * tree-inline.cc (redirect_all_calls): Remove code adding SSAs to
1013 id->killed_new_ssa_names.
1015 2024-03-08 Vladimir N. Makarov <vmakarov@redhat.com>
1017 PR target/113790
1018 * lra-assigns.cc (assign_by_spills): Set up all_spilled_pseudos
1019 for non-reload pseudo too.
1021 2024-03-08 David Faust <david.faust@oracle.com>
1023 * config/bpf/bpf.cc (bpf_expand_cpymem, bpf_expand_setmem): Do
1024 not attempt inline expansion if size is above threshold.
1025 * config/bpf/bpf.opt (-minline-memops-threshold): New option.
1026 * doc/invoke.texi (eBPF Options) <-minline-memops-threshold>:
1027 Document.
1029 2024-03-08 Richard Biener <rguenther@suse.de>
1031 PR tree-optimization/114269
1032 PR tree-optimization/114074
1033 * tree-chrec.cc (chrec_fold_plus_1): Handle sign-conversions
1034 in the third CASE_CONVERT case as well.
1035 (chrec_fold_multiply): Handle sign-conversions from unsigned
1036 by performing the operation in the unsigned type.
1038 2024-03-08 Georg-Johann Lay <avr@gjlay.de>
1040 * config/avr/avr.md (*addhi3_zero_extend.ashift1): New pattern.
1041 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS]: Compute its cost.
1043 2024-03-08 Jakub Jelinek <jakub@redhat.com>
1045 * bb-reorder.cc (fix_up_fall_thru_edges): Fix up checking assert,
1046 asm_noperands < 0 means it is not asm goto too.
1048 2024-03-08 Jakub Jelinek <jakub@redhat.com>
1050 PR target/38534
1051 * config/i386/i386.opt (mnoreturn-no-callee-saved-registers): New
1052 option.
1053 * config/i386/i386-options.cc (ix86_set_func_type): Don't use
1054 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP unless
1055 ix86_noreturn_no_callee_saved_registers is enabled.
1056 * doc/invoke.texi (-mnoreturn-no-callee-saved-registers): Document.
1058 2024-03-08 Jakub Jelinek <jakub@redhat.com>
1060 PR debug/113918
1061 * dwarf2out.cc (gen_field_die): Emit DW_AT_export_symbols
1062 on anonymous unions or structs for -gdwarf-5 or -gno-strict-dwarf.
1064 2024-03-08 demin.han <demin.han@starfivetech.com>
1066 PR target/114264
1067 * config/riscv/riscv-vector-costs.cc: Fix ICE
1069 2024-03-08 Haochen Gui <guihaoc@gcc.gnu.org>
1071 * fwprop.cc (forward_propagate_into): Return false for volatile set
1072 source rtx.
1074 2024-03-07 Wilco Dijkstra <wilco.dijkstra@arm.com>
1076 PR target/113618
1077 * config/aarch64/aarch64.cc (aarch64_copy_one_block): Remove.
1078 (aarch64_expand_cpymem): Emit single load/store only.
1079 (aarch64_set_one_block): Emit single stores only.
1081 2024-03-07 Robin Dapp <rdapp@ventanamicro.com>
1083 PR middle-end/114196
1084 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p): Merge
1085 vectorization guards.
1087 2024-03-07 Jonathan Wakely <jwakely@redhat.com>
1089 * doc/cppopts.texi: Remove incorrect claim about -dD not
1090 outputting predefined macros.
1092 2024-03-07 Jeevitha Palanisamy <jeevitha@linux.ibm.com>
1094 PR target/113950
1095 * config/rs6000/vsx.md (vsx_splat_<mode>): Correct assignment to operand1
1096 and simplify else if with else.
1098 2024-03-07 Francois-Xavier Coudert <fxcoudert@gcc.gnu.org>
1100 * system.h: Include safe-ctype.h after C++ standard headers.
1102 2024-03-07 Jakub Jelinek <jakub@redhat.com>
1104 PR rtl-optimization/110079
1105 * bb-reorder.cc (fix_crossing_unconditional_branches): Don't adjust
1106 asm goto.
1108 2024-03-07 Jakub Jelinek <jakub@redhat.com>
1110 PR middle-end/105533
1111 * expmed.cc (choose_mult_variant): Only try the val - 1 variant
1112 if val is not HOST_WIDE_INT_MIN or if mode has exactly
1113 HOST_BITS_PER_WIDE_INT precision. Avoid triggering UB while computing
1114 val - 1.
1116 2024-03-07 Jakub Jelinek <jakub@redhat.com>
1118 PR middle-end/105533
1119 * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference) <case ARRAY_REF>:
1120 Multiple op->off by BITS_PER_UNIT instead of shifting it left by
1121 LOG2_BITS_PER_UNIT.
1123 2024-03-07 Yang Yujie <yangyujie@loongson.cn>
1125 * config.gcc: Add a case for loongarch*-*-linux-musl*.
1126 * config/loongarch/linux.h: Disable the multilib-compatible
1127 treatment for *musl* targets.
1128 * config/loongarch/musl.h: New file.
1130 2024-03-07 Jakub Jelinek <jakub@redhat.com>
1132 PR tree-optimization/114009
1133 * genmatch.cc (decision_tree::gen): Emit ARG_UNUSED for captures
1134 argument even for GENERIC, not just for GIMPLE.
1135 * match.pd (a * !a -> 0): New simplifications.
1137 2024-03-07 demin.han <demin.han@starfivetech.com>
1139 * config/riscv/riscv-protos.h (expand_vec_cmp): Change proto
1140 * config/riscv/riscv-v.cc (expand_vec_cmp): Use default arguments
1141 (expand_vec_cmp_float): Adapt arguments
1143 2024-03-06 Uros Bizjak <ubizjak@gmail.com>
1145 PR target/114232
1146 * config/i386/mmx.md (negv2qi2): Enable for optimize_size instead
1147 of optimize_function_for_size_p. Explictily enable for TARGET_SSE2.
1148 (negv2qi SSE reg splitter): Enable for TARGET_SSE2 only.
1149 (<plusminus:insn>v2qi3): Enable for optimize_size instead
1150 of optimize_function_for_size_p. Explictily enable for TARGET_SSE2.
1151 (<plusminus:insn>v2qi SSE reg splitter): Enable for TARGET_SSE2 only.
1152 (<any_shift:insn>v2qi3): Enable for optimize_size instead
1153 of optimize_function_for_size_p.
1155 2024-03-06 Robin Dapp <rdapp@ventanamicro.com>
1157 PR target/114200
1158 PR target/114202
1159 * config/riscv/vector.md: Use vmv[1248]r.v instead of vmv.v.v.
1161 2024-03-06 Robin Dapp <rdapp@ventanamicro.com>
1163 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Move...
1164 (costs::adjust_stmt_cost): ... to here and add vec_load/vec_store
1165 offset handling.
1166 (costs::add_stmt_cost): Also adjust cost for statements without
1167 stmt_info.
1168 * config/riscv/riscv-vector-costs.h: Define zero constant.
1170 2024-03-06 Wilco Dijkstra <wilco.dijkstra@arm.com>
1172 PR target/113915
1173 * config/arm/arm.md (NOCOND): Improve comment.
1174 (arm_rev*) Add predicable.
1175 * config/arm/arm.cc (arm_final_prescan_insn): Add check for
1176 PREDICABLE_YES.
1178 2024-03-06 Jeff Law <jlaw@ventanamicro.com>
1180 PR target/113001
1181 PR target/112871
1182 * config/riscv/riscv.cc (expand_conditional_move): Do not swap
1183 operands when the comparison operand is the same as the false
1184 arm for a NE test.
1186 2024-03-06 Uros Bizjak <ubizjak@gmail.com>
1188 * config/i386/i386-expand.cc (ix86_expand_move) [TARGET_MACHO]:
1189 Eliminate common code and use generic code instead.
1191 2024-03-06 Georg-Johann Lay <avr@gjlay.de>
1193 * config/avr/avr.cc (avr_rtx_costs_1) [PLUS+ZERO_EXTEND]: Adjust
1194 rtx cost.
1196 2024-03-06 Richard Biener <rguenther@suse.de>
1198 PR tree-optimization/114239
1199 * tree-vect-loop.cc (vect_get_vect_def): Remove.
1200 (vect_create_epilog_for_reduction): The passed in stmt_info
1201 should now be the live stmt that produces the scalar reduction
1202 result. Revert PR114192 fix. Base reduction info off
1203 info_for_reduction. Remove special handling of
1204 early-break/peeled, restore original vector def gathering.
1205 Make sure to pick the correct exit PHIs.
1206 (vectorizable_live_operation): Pass in the proper stmt_info
1207 for early break exits.
1209 2024-03-06 Richard Sandiford <richard.sandiford@arm.com>
1211 * config/aarch64/aarch64-feature-deps.h (feature_deps::info): Add
1212 out-of-class definitions of static constants.
1214 2024-03-06 Richard Biener <rguenther@suse.de>
1216 PR tree-optimization/114249
1217 * tree-vect-slp.cc (vect_build_slp_instance): Move making
1218 a BB reduction lane number even ...
1219 (vect_slp_check_for_roots): ... here to avoid leaking
1220 pattern defs.
1222 2024-03-06 Richard Biener <rguenther@suse.de>
1224 PR tree-optimization/114246
1225 * tree-ssa-dse.cc (increment_start_addr): Strip useless
1226 type conversions from the adjusted address.
1228 2024-03-06 Jakub Jelinek <jakub@redhat.com>
1230 PR rtl-optimization/114190
1231 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
1232 Call df_remove_problem for df_note before calling df_analyze.
1234 2024-03-05 Cupertino Miranda <cupertino.miranda@oracle.com>
1235 Indu Bhagat <indu.bhagat@oracle.com>
1237 PR debug/114186
1238 * dwarf2ctf.cc (gen_ctf_array_type): Invoke the ctf_add_array ()
1239 in the correct order of the dimensions.
1240 (gen_ctf_subrange_type): Refactor out handling of
1241 DW_TAG_subrange_type DIE to here.
1243 2024-03-05 Richard Sandiford <richard.sandiford@arm.com>
1245 PR sanitizer/97696
1246 * asan.cc (asan_expand_mark_ifn): Allow the length to be a poly_int.
1248 2024-03-05 Richard Sandiford <richard.sandiford@arm.com>
1250 * config/aarch64/aarch64.md (stride_type): Remove luti_consecutive
1251 and luti_strided.
1252 * config/aarch64/aarch64-sme.md
1253 (@aarch64_sme_lut<LUTI_BITS><mode>): Remove stride_type attribute.
1254 (@aarch64_sme_lut<LUTI_BITS><mode>_strided2): Delete.
1255 (@aarch64_sme_lut<LUTI_BITS><mode>_strided4): Likewise.
1256 * config/aarch64/aarch64-early-ra.cc (is_stride_candidate)
1257 (early_ra::maybe_convert_to_strided_access): Remove support for
1258 strided LUTI2 and LUTI4.
1260 2024-03-05 Richard Earnshaw <rearnsha@arm.com>
1262 PR target/113510
1263 * config/arm/thumb1.md (peephole2 to fuse mov imm/add SP): Use
1264 low_register_operand.
1266 2024-03-05 Georg-Johann Lay <avr@gjlay.de>
1268 * config/avr/avr.md: Add two RTL peepholes for PLUS, IOR and AND
1269 in HI, PSI, SI that swap operation order from "X = CST, X o= Y"
1270 to "X = Y, X o= CST".
1272 2024-03-05 Xi Ruoyao <xry111@xry111.site>
1274 * config/loongarch/loongarch.h (ADDITIONAL_REGISTER_NAMES): Add
1275 s9 as an alias of r22.
1277 2024-03-05 Roger Sayle <roger@nextmovesoftware.com>
1279 * config/avr/avr-protos.h (avr_out_insv): New proto.
1280 * config/avr/avr.cc (avr_out_insv): New function.
1281 (avr_adjust_insn_length) [ADJUST_LEN_INSV]: Handle case.
1282 (avr_cbranch_cost) [ZERO_EXTRACT]: Adjust rtx costs.
1283 * config/avr/avr.md (define_attr "adjust_len") Add insv.
1284 (andhi3, *andhi3, andpsi3, *andpsi3, andsi3, *andsi3):
1285 Add constraint alternative where the 3rd operand is a power
1286 of 2, and the source register may differ from the destination.
1287 (*insv.any_shift.<mode>_split): Call avr_out_insv to output
1288 instructions. Set attr "length" to "insv".
1289 * config/avr/constraints.md (Cb2, Cb3, Cb4): New constraints.
1291 2024-03-05 Richard Biener <rguenther@suse.de>
1293 PR tree-optimization/114231
1294 * tree-vect-slp.cc (vect_analyze_slp): Lookup patterns when
1295 processing a BB SLP root.
1297 2024-03-05 Jakub Jelinek <jakub@redhat.com>
1299 PR rtl-optimization/114211
1300 * lower-subreg.cc (resolve_simple_move): For double-word
1301 rotates by BITS_PER_WORD if there is overlap between source
1302 and destination use a temporary.
1304 2024-03-05 Jakub Jelinek <jakub@redhat.com>
1306 PR middle-end/114157
1307 * gimple-lower-bitint.cc: Include stor-layout.h.
1308 (mergeable_op): Return true for BIT_FIELD_REF.
1309 (struct bitint_large_huge): Declare handle_bit_field_ref method.
1310 (bitint_large_huge::handle_bit_field_ref): New method.
1311 (bitint_large_huge::handle_stmt): Use it for BIT_FIELD_REF.
1313 2024-03-05 Jakub Jelinek <jakub@redhat.com>
1315 PR target/114116
1316 * config/i386/i386.h (enum call_saved_registers_type): Add
1317 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP enumerator.
1318 * config/i386/i386-options.cc (ix86_set_func_type): Remove
1319 has_no_callee_saved_registers variable, add no_callee_saved_registers
1320 instead, initialize it depending on whether it is
1321 no_callee_saved_registers function or not. Don't set it if
1322 no_caller_saved_registers attribute is present. Adjust users.
1323 * config/i386/i386.cc (ix86_function_ok_for_sibcall): Handle
1324 TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP like
1325 TYPE_NO_CALLEE_SAVED_REGISTERS.
1326 (ix86_save_reg): Handle TYPE_NO_CALLEE_SAVED_REGISTERS_EXCEPT_BP.
1328 2024-03-05 Pan Li <pan2.li@intel.com>
1330 * config/riscv/riscv.cc (riscv_v_adjust_bytesize): Cleanup unused
1331 mode_size related code.
1333 2024-03-05 Patrick Palka <ppalka@redhat.com>
1335 * doc/invoke.texi (-Wno-global-module): Document.
1337 2024-03-04 David Faust <david.faust@oracle.com>
1339 * config/bpf/bpf-protos.h (bpf_expand_setmem): New prototype.
1340 * config/bpf/bpf.cc (bpf_expand_setmem): New.
1341 * config/bpf/bpf.md (setmemdi): New define_expand.
1343 2024-03-04 Jakub Jelinek <jakub@redhat.com>
1345 PR rtl-optimization/113010
1346 * combine.cc (simplify_comparison): Guard the
1347 WORD_REGISTER_OPERATIONS check on scalar_int_mode of SUBREG_REG
1348 and initialize inner_mode.
1350 2024-03-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
1352 * config/arm/iterators.md (supf): Remove VMLALDAVXQ_U, VMLALDAVXQ_P_U,
1353 VMLALDAVAXQ_U cases.
1354 (VMLALDAVXQ): Remove iterator.
1355 (VMLALDAVXQ_P): Likewise.
1356 (VMLALDAVAXQ): Likewise.
1357 * config/arm/mve.md (mve_vstrwq_p_fv4sf): Replace use of <MVE_VPRED>
1358 mode iterator attribute with V4BI mode.
1359 * config/arm/unspecs.md (VMLALDAVXQ_U, VMLALDAVXQ_P_U,
1360 VMLALDAVAXQ_U): Remove unused unspecs.
1362 2024-03-04 Andre Vieira <andre.simoesdiasvieira@arm.com>
1364 * config/arm/arm.md (mve_safe_imp_xlane_pred): New attribute.
1365 * config/arm/iterators.md (mve_vmaxmin_safe_imp): New iterator
1366 attribute.
1367 * config/arm/mve.md (vaddvq_s, vaddvq_u, vaddlvq_s, vaddlvq_u,
1368 vaddvaq_s, vaddvaq_u, vmaxavq_s, vmaxvq_u, vmladavq_s, vmladavq_u,
1369 vmladavxq_s, vmlsdavq_s, vmlsdavxq_s, vaddlvaq_s, vaddlvaq_u,
1370 vmlaldavq_u, vmlaldavq_s, vmlaldavq_u, vmlaldavxq_s, vmlsldavq_s,
1371 vmlsldavxq_s, vrmlaldavhq_u, vrmlaldavhq_s, vrmlaldavhxq_s,
1372 vrmlsldavhq_s, vrmlsldavhxq_s, vrmlaldavhaq_s, vrmlaldavhaq_u,
1373 vrmlaldavhaxq_s, vrmlsldavhaq_s, vrmlsldavhaxq_s, vabavq_s, vabavq_u,
1374 vmladavaq_u, vmladavaq_s, vmladavaxq_s, vmlsdavaq_s, vmlsdavaxq_s,
1375 vmlaldavaq_s, vmlaldavaq_u, vmlaldavaxq_s, vmlsldavaq_s,
1376 vmlsldavaxq_s): Added mve_safe_imp_xlane_pred.
1378 2024-03-04 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1380 * config/arm/arm.md (mve_unpredicated_insn): New attribute.
1381 * config/arm/arm.h (MVE_VPT_PREDICATED_INSN_P): New define.
1382 (MVE_VPT_UNPREDICATED_INSN_P): Likewise.
1383 (MVE_VPT_PREDICABLE_INSN_P): Likewise.
1384 * config/arm/vec-common.md (mve_vshlq_<supf><mode>): Add attribute.
1385 * config/arm/mve.md (arm_vcx1q<a>_p_v16qi): Add attribute.
1386 (arm_vcx1q<a>v16qi): Likewise.
1387 (arm_vcx1qav16qi): Likewise.
1388 (arm_vcx1qv16qi): Likewise.
1389 (arm_vcx2q<a>_p_v16qi): Likewise.
1390 (arm_vcx2q<a>v16qi): Likewise.
1391 (arm_vcx2qav16qi): Likewise.
1392 (arm_vcx2qv16qi): Likewise.
1393 (arm_vcx3q<a>_p_v16qi): Likewise.
1394 (arm_vcx3q<a>v16qi): Likewise.
1395 (arm_vcx3qav16qi): Likewise.
1396 (arm_vcx3qv16qi): Likewise.
1397 (@mve_<mve_insn>q_<supf><mode>): Likewise.
1398 (@mve_<mve_insn>q_int_<supf><mode>): Likewise.
1399 (@mve_<mve_insn>q_<supf>v4si): Likewise.
1400 (@mve_<mve_insn>q_n_<supf><mode>): Likewise.
1401 (@mve_<mve_insn>q_r_<supf><mode>): Likewise.
1402 (@mve_<mve_insn>q_f<mode>): Likewise.
1403 (@mve_<mve_insn>q_m_<supf><mode>): Likewise.
1404 (@mve_<mve_insn>q_m_n_<supf><mode>): Likewise.
1405 (@mve_<mve_insn>q_m_r_<supf><mode>): Likewise.
1406 (@mve_<mve_insn>q_m_f<mode>): Likewise.
1407 (@mve_<mve_insn>q_int_m_<supf><mode>): Likewise.
1408 (@mve_<mve_insn>q_p_<supf>v4si): Likewise.
1409 (@mve_<mve_insn>q_p_<supf><mode>): Likewise.
1410 (@mve_<mve_insn>q<mve_rot>_<supf><mode>): Likewise.
1411 (@mve_<mve_insn>q<mve_rot>_f<mode>): Likewise.
1412 (@mve_<mve_insn>q<mve_rot>_m_<supf><mode>): Likewise.
1413 (@mve_<mve_insn>q<mve_rot>_m_f<mode>): Likewise.
1414 (mve_v<absneg_str>q_f<mode>): Likewise.
1415 (mve_<mve_addsubmul>q<mode>): Likewise.
1416 (mve_<mve_addsubmul>q_f<mode>): Likewise.
1417 (mve_vadciq_<supf>v4si): Likewise.
1418 (mve_vadciq_m_<supf>v4si): Likewise.
1419 (mve_vadcq_<supf>v4si): Likewise.
1420 (mve_vadcq_m_<supf>v4si): Likewise.
1421 (mve_vandq_<supf><mode>): Likewise.
1422 (mve_vandq_f<mode>): Likewise.
1423 (mve_vandq_m_<supf><mode>): Likewise.
1424 (mve_vandq_m_f<mode>): Likewise.
1425 (mve_vandq_s<mode>): Likewise.
1426 (mve_vandq_u<mode>): Likewise.
1427 (mve_vbicq_<supf><mode>): Likewise.
1428 (mve_vbicq_f<mode>): Likewise.
1429 (mve_vbicq_m_<supf><mode>): Likewise.
1430 (mve_vbicq_m_f<mode>): Likewise.
1431 (mve_vbicq_m_n_<supf><mode>): Likewise.
1432 (mve_vbicq_n_<supf><mode>): Likewise.
1433 (mve_vbicq_s<mode>): Likewise.
1434 (mve_vbicq_u<mode>): Likewise.
1435 (@mve_vclzq_s<mode>): Likewise.
1436 (mve_vclzq_u<mode>): Likewise.
1437 (@mve_vcmp_<mve_cmp_op>q_<mode>): Likewise.
1438 (@mve_vcmp_<mve_cmp_op>q_n_<mode>): Likewise.
1439 (@mve_vcmp_<mve_cmp_op>q_f<mode>): Likewise.
1440 (@mve_vcmp_<mve_cmp_op>q_n_f<mode>): Likewise.
1441 (@mve_vcmp_<mve_cmp_op1>q_m_f<mode>): Likewise.
1442 (@mve_vcmp_<mve_cmp_op1>q_m_n_<supf><mode>): Likewise.
1443 (@mve_vcmp_<mve_cmp_op1>q_m_<supf><mode>): Likewise.
1444 (@mve_vcmp_<mve_cmp_op1>q_m_n_f<mode>): Likewise.
1445 (mve_vctp<MVE_vctp>q<MVE_vpred>): Likewise.
1446 (mve_vctp<MVE_vctp>q_m<MVE_vpred>): Likewise.
1447 (mve_vcvtaq_<supf><mode>): Likewise.
1448 (mve_vcvtaq_m_<supf><mode>): Likewise.
1449 (mve_vcvtbq_f16_f32v8hf): Likewise.
1450 (mve_vcvtbq_f32_f16v4sf): Likewise.
1451 (mve_vcvtbq_m_f16_f32v8hf): Likewise.
1452 (mve_vcvtbq_m_f32_f16v4sf): Likewise.
1453 (mve_vcvtmq_<supf><mode>): Likewise.
1454 (mve_vcvtmq_m_<supf><mode>): Likewise.
1455 (mve_vcvtnq_<supf><mode>): Likewise.
1456 (mve_vcvtnq_m_<supf><mode>): Likewise.
1457 (mve_vcvtpq_<supf><mode>): Likewise.
1458 (mve_vcvtpq_m_<supf><mode>): Likewise.
1459 (mve_vcvtq_from_f_<supf><mode>): Likewise.
1460 (mve_vcvtq_m_from_f_<supf><mode>): Likewise.
1461 (mve_vcvtq_m_n_from_f_<supf><mode>): Likewise.
1462 (mve_vcvtq_m_n_to_f_<supf><mode>): Likewise.
1463 (mve_vcvtq_m_to_f_<supf><mode>): Likewise.
1464 (mve_vcvtq_n_from_f_<supf><mode>): Likewise.
1465 (mve_vcvtq_n_to_f_<supf><mode>): Likewise.
1466 (mve_vcvtq_to_f_<supf><mode>): Likewise.
1467 (mve_vcvttq_f16_f32v8hf): Likewise.
1468 (mve_vcvttq_f32_f16v4sf): Likewise.
1469 (mve_vcvttq_m_f16_f32v8hf): Likewise.
1470 (mve_vcvttq_m_f32_f16v4sf): Likewise.
1471 (mve_vdwdupq_m_wb_u<mode>_insn): Likewise.
1472 (mve_vdwdupq_wb_u<mode>_insn): Likewise.
1473 (mve_veorq_s><mode>): Likewise.
1474 (mve_veorq_u><mode>): Likewise.
1475 (mve_veorq_f<mode>): Likewise.
1476 (mve_vidupq_m_wb_u<mode>_insn): Likewise.
1477 (mve_vidupq_u<mode>_insn): Likewise.
1478 (mve_viwdupq_m_wb_u<mode>_insn): Likewise.
1479 (mve_viwdupq_wb_u<mode>_insn): Likewise.
1480 (mve_vldrbq_<supf><mode>): Likewise.
1481 (mve_vldrbq_gather_offset_<supf><mode>): Likewise.
1482 (mve_vldrbq_gather_offset_z_<supf><mode>): Likewise.
1483 (mve_vldrbq_z_<supf><mode>): Likewise.
1484 (mve_vldrdq_gather_base_<supf>v2di): Likewise.
1485 (mve_vldrdq_gather_base_wb_<supf>v2di_insn): Likewise.
1486 (mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Likewise.
1487 (mve_vldrdq_gather_base_z_<supf>v2di): Likewise.
1488 (mve_vldrdq_gather_offset_<supf>v2di): Likewise.
1489 (mve_vldrdq_gather_offset_z_<supf>v2di): Likewise.
1490 (mve_vldrdq_gather_shifted_offset_<supf>v2di): Likewise.
1491 (mve_vldrdq_gather_shifted_offset_z_<supf>v2di): Likewise.
1492 (mve_vldrhq_<supf><mode>): Likewise.
1493 (mve_vldrhq_fv8hf): Likewise.
1494 (mve_vldrhq_gather_offset_<supf><mode>): Likewise.
1495 (mve_vldrhq_gather_offset_fv8hf): Likewise.
1496 (mve_vldrhq_gather_offset_z_<supf><mode>): Likewise.
1497 (mve_vldrhq_gather_offset_z_fv8hf): Likewise.
1498 (mve_vldrhq_gather_shifted_offset_<supf><mode>): Likewise.
1499 (mve_vldrhq_gather_shifted_offset_fv8hf): Likewise.
1500 (mve_vldrhq_gather_shifted_offset_z_<supf><mode>): Likewise.
1501 (mve_vldrhq_gather_shifted_offset_z_fv8hf): Likewise.
1502 (mve_vldrhq_z_<supf><mode>): Likewise.
1503 (mve_vldrhq_z_fv8hf): Likewise.
1504 (mve_vldrwq_<supf>v4si): Likewise.
1505 (mve_vldrwq_fv4sf): Likewise.
1506 (mve_vldrwq_gather_base_<supf>v4si): Likewise.
1507 (mve_vldrwq_gather_base_fv4sf): Likewise.
1508 (mve_vldrwq_gather_base_wb_<supf>v4si_insn): Likewise.
1509 (mve_vldrwq_gather_base_wb_fv4sf_insn): Likewise.
1510 (mve_vldrwq_gather_base_wb_z_<supf>v4si_insn): Likewise.
1511 (mve_vldrwq_gather_base_wb_z_fv4sf_insn): Likewise.
1512 (mve_vldrwq_gather_base_z_<supf>v4si): Likewise.
1513 (mve_vldrwq_gather_base_z_fv4sf): Likewise.
1514 (mve_vldrwq_gather_offset_<supf>v4si): Likewise.
1515 (mve_vldrwq_gather_offset_fv4sf): Likewise.
1516 (mve_vldrwq_gather_offset_z_<supf>v4si): Likewise.
1517 (mve_vldrwq_gather_offset_z_fv4sf): Likewise.
1518 (mve_vldrwq_gather_shifted_offset_<supf>v4si): Likewise.
1519 (mve_vldrwq_gather_shifted_offset_fv4sf): Likewise.
1520 (mve_vldrwq_gather_shifted_offset_z_<supf>v4si): Likewise.
1521 (mve_vldrwq_gather_shifted_offset_z_fv4sf): Likewise.
1522 (mve_vldrwq_z_<supf>v4si): Likewise.
1523 (mve_vldrwq_z_fv4sf): Likewise.
1524 (mve_vmvnq_s<mode>): Likewise.
1525 (mve_vmvnq_u<mode>): Likewise.
1526 (mve_vornq_<supf><mode>): Likewise.
1527 (mve_vornq_f<mode>): Likewise.
1528 (mve_vornq_m_<supf><mode>): Likewise.
1529 (mve_vornq_m_f<mode>): Likewise.
1530 (mve_vornq_s<mode>): Likewise.
1531 (mve_vornq_u<mode>): Likewise.
1532 (mve_vorrq_<supf><mode>): Likewise.
1533 (mve_vorrq_f<mode>): Likewise.
1534 (mve_vorrq_m_<supf><mode>): Likewise.
1535 (mve_vorrq_m_f<mode>): Likewise.
1536 (mve_vorrq_m_n_<supf><mode>): Likewise.
1537 (mve_vorrq_n_<supf><mode>): Likewise.
1538 (mve_vorrq_s<mode>): Likewise.
1539 (mve_vorrq_s<mode>): Likewise.
1540 (mve_vsbciq_<supf>v4si): Likewise.
1541 (mve_vsbciq_m_<supf>v4si): Likewise.
1542 (mve_vsbcq_<supf>v4si): Likewise.
1543 (mve_vsbcq_m_<supf>v4si): Likewise.
1544 (mve_vshlcq_<supf><mode>): Likewise.
1545 (mve_vshlcq_m_<supf><mode>): Likewise.
1546 (mve_vshrq_m_n_<supf><mode>): Likewise.
1547 (mve_vshrq_n_<supf><mode>): Likewise.
1548 (mve_vstrbq_<supf><mode>): Likewise.
1549 (mve_vstrbq_p_<supf><mode>): Likewise.
1550 (mve_vstrbq_scatter_offset_<supf><mode>_insn): Likewise.
1551 (mve_vstrbq_scatter_offset_p_<supf><mode>_insn): Likewise.
1552 (mve_vstrdq_scatter_base_<supf>v2di): Likewise.
1553 (mve_vstrdq_scatter_base_p_<supf>v2di): Likewise.
1554 (mve_vstrdq_scatter_base_wb_<supf>v2di): Likewise.
1555 (mve_vstrdq_scatter_base_wb_p_<supf>v2di): Likewise.
1556 (mve_vstrdq_scatter_offset_<supf>v2di_insn): Likewise.
1557 (mve_vstrdq_scatter_offset_p_<supf>v2di_insn): Likewise.
1558 (mve_vstrdq_scatter_shifted_offset_<supf>v2di_insn): Likewise.
1559 (mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn): Likewise.
1560 (mve_vstrhq_<supf><mode>): Likewise.
1561 (mve_vstrhq_fv8hf): Likewise.
1562 (mve_vstrhq_p_<supf><mode>): Likewise.
1563 (mve_vstrhq_p_fv8hf): Likewise.
1564 (mve_vstrhq_scatter_offset_<supf><mode>_insn): Likewise.
1565 (mve_vstrhq_scatter_offset_fv8hf_insn): Likewise.
1566 (mve_vstrhq_scatter_offset_p_<supf><mode>_insn): Likewise.
1567 (mve_vstrhq_scatter_offset_p_fv8hf_insn): Likewise.
1568 (mve_vstrhq_scatter_shifted_offset_<supf><mode>_insn): Likewise.
1569 (mve_vstrhq_scatter_shifted_offset_fv8hf_insn): Likewise.
1570 (mve_vstrhq_scatter_shifted_offset_p_<supf><mode>_insn): Likewise.
1571 (mve_vstrhq_scatter_shifted_offset_p_fv8hf_insn): Likewise.
1572 (mve_vstrwq_<supf>v4si): Likewise.
1573 (mve_vstrwq_fv4sf): Likewise.
1574 (mve_vstrwq_p_<supf>v4si): Likewise.
1575 (mve_vstrwq_p_fv4sf): Likewise.
1576 (mve_vstrwq_scatter_base_<supf>v4si): Likewise.
1577 (mve_vstrwq_scatter_base_fv4sf): Likewise.
1578 (mve_vstrwq_scatter_base_p_<supf>v4si): Likewise.
1579 (mve_vstrwq_scatter_base_p_fv4sf): Likewise.
1580 (mve_vstrwq_scatter_base_wb_<supf>v4si): Likewise.
1581 (mve_vstrwq_scatter_base_wb_fv4sf): Likewise.
1582 (mve_vstrwq_scatter_base_wb_p_<supf>v4si): Likewise.
1583 (mve_vstrwq_scatter_base_wb_p_fv4sf): Likewise.
1584 (mve_vstrwq_scatter_offset_<supf>v4si_insn): Likewise.
1585 (mve_vstrwq_scatter_offset_fv4sf_insn): Likewise.
1586 (mve_vstrwq_scatter_offset_p_<supf>v4si_insn): Likewise.
1587 (mve_vstrwq_scatter_offset_p_fv4sf_insn): Likewise.
1588 (mve_vstrwq_scatter_shifted_offset_<supf>v4si_insn): Likewise.
1589 (mve_vstrwq_scatter_shifted_offset_fv4sf_insn): Likewise.
1590 (mve_vstrwq_scatter_shifted_offset_p_<supf>v4si_insn): Likewise.
1591 (mve_vstrwq_scatter_shifted_offset_p_fv4sf_insn): Likewise.
1593 2024-03-04 Marek Polacek <polacek@redhat.com>
1595 * doc/extend.texi: Update [[gnu::no_dangling]].
1597 2024-03-04 Andrew Stubbs <ams@baylibre.com>
1599 * dojump.cc (do_compare_and_jump): Use full-width integers for shifts.
1600 * expr.cc (store_constructor): Likewise.
1601 (do_store_flag): Likewise.
1603 2024-03-04 Mark Wielaard <mark@klomp.org>
1605 * common.opt.urls: Regenerate.
1606 * config/avr/avr.opt.urls: Likewise.
1607 * config/i386/i386.opt.urls: Likewise.
1608 * config/pru/pru.opt.urls: Likewise.
1609 * config/riscv/riscv.opt.urls: Likewise.
1610 * config/rs6000/rs6000.opt.urls: Likewise.
1612 2024-03-04 Richard Biener <rguenther@suse.de>
1614 PR tree-optimization/114197
1615 * tree-if-conv.cc (bitfields_to_lower_p): Do not lower if
1616 there are volatile bitfield accesses.
1617 (pass_if_conversion::execute): Throw away result if the
1618 if-converted and original loops are not nested as expected.
1620 2024-03-04 Richard Biener <rguenther@suse.de>
1622 PR tree-optimization/114164
1623 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Fail if
1624 the code generated for mask argument setup is not supported.
1626 2024-03-04 Richard Biener <rguenther@suse.de>
1628 PR tree-optimization/114203
1629 * tree-ssa-loop-niter.cc (build_cltz_expr): Apply CTZ->CLZ
1630 adjustment before making the result defined at zero.
1632 2024-03-04 Richard Biener <rguenther@suse.de>
1634 PR tree-optimization/114192
1635 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Use the
1636 appropriate def for the live out stmt in case of an alternate
1637 exit.
1639 2024-03-04 Jakub Jelinek <jakub@redhat.com>
1641 PR middle-end/114209
1642 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Call
1643 unshare_expr when creating a MEM_REF from MEM_REF.
1644 (bitint_large_huge::lower_stmt): Call unshare_expr.
1646 2024-03-04 Jakub Jelinek <jakub@redhat.com>
1648 PR target/114184
1649 * config/i386/i386-expand.cc (ix86_expand_move): If XFmode op1
1650 is SUBREG of CONSTANT_P, force the SUBREG_REG into memory or
1651 register.
1653 2024-03-04 Roger Sayle <roger@nextmovesoftware.com>
1655 PR target/114187
1656 * simplify-rtx.cc (simplify_context::simplify_subreg): Call
1657 lowpart_subreg to perform type conversion, to avoid confusion
1658 over the offset to use in the call to simplify_reg_subreg.
1660 2024-03-03 Greg McGary <gkm@rivosinc.com>
1662 PR rtl-optimization/113010
1663 * combine.cc (simplify_comparison): Simplify a SUBREG on
1664 WORD_REGISTER_OPERATIONS targets only if it is a zero-extending
1665 MEM load.
1667 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
1669 * config/avr/avr.cc: Resolve ATTRIBUTE_UNUSED.
1670 Use bool in place of int for boolean logic (if possible).
1671 Move declarations to definitions (if possible).
1672 * config/avr/avr.md: Use C++ comments. Fix some indentation glitches.
1673 * config/avr/avr-dimode.md: Same.
1674 * config/avr/constraints.md: Same.
1675 * config/avr/predicates.md: Same.
1677 2024-03-03 Uros Bizjak <ubizjak@gmail.com>
1679 PR target/113720
1680 * config/alpha/alpha.md (umuldi3_highpart): Remove expander.
1681 (*umuldi3_highpart_reg): Rename to umuldi3_highpart and
1682 simplify insn RTX using UMUL_HIGHPART rtx_code.
1683 (*umuldi3_highpart_const): Remove.
1685 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
1687 PR target/114100
1688 * config/avr/avr-protos.h (_reg_unused_after): Remove proto.
1689 * config/avr/avr.cc (_reg_unused_after): Make static. And
1690 add 3rd argument to skip the current insn.
1691 (reg_unused_after): Adjust call of reg_unused_after.
1692 (avr_out_plus_1) [AVR_TINY && -mfuse-add >= 2]: Don't output
1693 unneeded frame pointer adjustments.
1695 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
1697 PR target/92729
1698 * config/avr/avr.md (define_attr "cc"): Remove.
1699 * config/avr/avr-protos.h (avr_out_plus): Remove pcc argument
1700 from prototype.
1701 * config/avr/avr.cc (avr_out_plus_1): Remove pcc argument and
1702 its uses. Add insn argument.
1703 (avr_out_plus_symbol): Remove pcc argument and its uses.
1704 (avr_out_plus): Remove pcc argument and its uses.
1705 Adjust calls of avr_out_plus_symbol and avr_out_plus_1.
1706 (avr_out_round): Adjust call of avr_out_plus.
1708 2024-03-03 Georg-Johann Lay <avr@gjlay.de>
1710 * config/avr/avr.cc (avr_init_cumulative_args): Fix a typo
1711 from r14-9273.
1713 2024-03-03 Oleg Endo <olegendo@gcc.gnu.org>
1715 PR target/101737
1716 * config/sh/sh.cc (sh_is_nott_insn): Handle case where the input
1717 is not an insn, but e.g. a code label.
1719 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
1721 * config/avr/avr.md (REG_0, ... REG_36): New define_constants.
1722 * config/avr/avr.cc: Use them instead of magic numbers when it
1723 means a register number.
1725 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
1727 * config/avr/avr.cc: Adjust some comments.
1729 2024-03-02 Georg-Johann Lay <avr@gjlay.de>
1731 PR target/114100
1732 * config/avr/avr.cc (avr_out_plus_1) [-mtiny-stack]: Only adjust
1733 the low part of the frame pointer with 8-bit stack pointer.
1735 2024-03-01 Patrick Palka <ppalka@redhat.com>
1737 PR c++/104919
1738 PR c++/106009
1739 * tree-inline.cc (remap_decl): Handle copy_decl returning the
1740 original decl.
1741 (remap_decls): Handle remap_decl returning the original decl.
1742 (copy_fn): Adjust copy_decl callback to skip TYPE_DECL and
1743 CONST_DECL.
1745 2024-03-01 Jeff Law <jlaw@ventanamicro.com>
1747 * config/riscv/riscv.md (zero_extendqi<SUPERQI:mode>2_internal): Fix
1748 type attribute.
1749 (extendsidi2_internal, movhf_hardfloat, movhf_softfloat): Likewise.
1750 (movdi_32bit, movdi_64bit, movsi_internal): Likewise.
1751 (movhi_internal, movqi_internal): Likewise.
1752 (movsf_softfloat, movsf_hardfloat): Likewise.
1753 (movdf_hardfloat_rv32, movdf_hardfloat_rv64): Likewise.
1754 (movdf_softfloat): Likewise.
1756 2024-03-01 Marek Polacek <polacek@redhat.com>
1758 PR c++/110358
1759 PR c++/109642
1760 * doc/extend.texi: Document gnu::no_dangling.
1761 * doc/invoke.texi: Mention that gnu::no_dangling disables
1762 -Wdangling-reference.
1764 2024-03-01 Georg-Johann Lay <avr@gjlay.de>
1766 * config/avr/avr.opt: Overhaul help screen.
1768 2024-03-01 Jakub Jelinek <jakub@redhat.com>
1769 Tobias Burnus <tburnus@baylibre.com>
1771 PR c++/110347
1772 * gimplify.cc (omp_notice_variable): Fix 'shared' arg to
1773 lang_hooks.decls.omp_disregard_value_expr for
1774 (first)private in target regions.
1776 2024-03-01 Jakub Jelinek <jakub@redhat.com>
1778 PR middle-end/114136
1779 * calls.cc (expand_call): For TYPE_NO_NAMED_ARGS_STDARG_P set
1780 n_named_args initially before INIT_CUMULATIVE_ARGS to
1781 structure_value_addr_parm rather than 0, after it don't modify
1782 it if strict_argument_naming and clear only if
1783 !pretend_outgoing_varargs_named.
1785 2024-03-01 Jakub Jelinek <jakub@redhat.com>
1787 PR debug/114015
1788 * dwarf2out.cc (should_move_die_to_comdat): Return false for
1789 aggregates without DW_AT_byte_size attribute or with non-constant
1790 DW_AT_byte_size.
1792 2024-03-01 Georg-Johann Lay <avr@gjlay.de>
1794 * doc/invoke.texi (AVR Options) <-mfuse-add=level>: Document
1795 valid values for level.
1797 2024-03-01 Richard Biener <rguenther@suse.de>
1799 PR middle-end/114070
1800 * match.pd ((c ? a : b) op d --> c ? (a op d) : (b op d)):
1801 Allow the folding if before lowering and the current IL
1802 isn't supported with vcond_mask.
1804 2024-03-01 xuli <xuli1@eswincomputing.com>
1806 * config/riscv/riscv.cc (TARGET_GNU_ATTRIBUTES): Add riscv_vector_cc
1807 attribute to riscv_attribute_table.
1808 (riscv_vector_cc_function_p): Return true if FUNC is a riscv_vector_cc function.
1809 (riscv_fntype_abi): Add riscv_vector_cc attribute check.
1810 * doc/extend.texi: Add riscv_vector_cc attribute description.
1812 2024-03-01 Pan Li <pan2.li@intel.com>
1814 PR target/112817
1815 * config/riscv/riscv-avlprop.cc (pass_avlprop::execute): Replace
1816 RVV_FIXED_VLMAX to RVV_VECTOR_BITS_ZVL.
1817 * config/riscv/riscv-opts.h (enum riscv_autovec_preference_enum): Remove.
1818 (enum rvv_vector_bits_enum): New enum for different RVV vector bits.
1819 * config/riscv/riscv-selftests.cc (riscv_run_selftests): Update
1820 comments for option replacement.
1821 * config/riscv/riscv-v.cc (autovec_use_vlmax_p): Replace enum of
1822 riscv_autovec_preference to rvv_vector_bits.
1823 (vls_mode_valid_p): Ditto.
1824 (estimated_poly_value): Ditto.
1825 * config/riscv/riscv.cc (riscv_convert_vector_chunks): Rename to
1826 vector chunks and honor new option mrvv-vector-bits.
1827 (riscv_override_options_internal): Update comments and rename the
1828 vector chunks.
1829 * config/riscv/riscv.opt: Add option mrvv-vector-bits and remove
1830 internal option param=riscv-autovec-preference.
1832 2024-03-01 Jakub Jelinek <jakub@redhat.com>
1834 * function.cc (assign_parms): Only call assign_parms_setup_varargs
1835 early for TYPE_NO_NAMED_ARGS_STDARG_P functions if fnargs is empty.
1837 2024-03-01 Jakub Jelinek <jakub@redhat.com>
1839 PR middle-end/114156
1840 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Allow
1841 rhs1 of a VCE to have no underlying variable if it is a load and
1842 handle that case.
1844 2024-02-29 David Malcolm <dmalcolm@redhat.com>
1846 PR analyzer/114159
1847 * function.cc (function_name): Make param const.
1848 * function.h (function_name): Likewise.
1850 2024-02-29 Georg-Johann Lay <avr@gjlay.de>
1852 PR target/114100
1853 * doc/invoke.texi (AVR Options) <-mfuse-add>: Document.
1854 * config/avr/avr.opt (-mfuse-add=): New target option.
1855 * common/config/avr/avr-common.cc (avr_option_optimization_table)
1856 [OPT_LEVELS_1_PLUS]: Set -mfuse-add=1.
1857 [OPT_LEVELS_2_PLUS]: Set -mfuse-add=2.
1858 * config/avr/avr-passes.def (avr_pass_fuse_add): Insert new pass.
1859 * config/avr/avr-protos.h (avr_split_tiny_move)
1860 (make_avr_pass_fuse_add): New protos.
1861 * config/avr/avr.md [AVR_TINY]: New post-reload splitter uses
1862 avr_split_tiny_move to split indirect memory accesses.
1863 (gen_move_clobbercc): New define_expand helper.
1864 * config/avr/avr.cc (avr_pass_data_fuse_add): New pass data.
1865 (avr_pass_fuse_add): New class from rtl_opt_pass.
1866 (make_avr_pass_fuse_add, avr_split_tiny_move): New functions.
1867 (reg_seen_between_p, emit_move_ccc, emit_move_ccc_after): New functions.
1868 (avr_legitimate_address_p) [AVR_TINY]: Don't restrict offsets
1869 of PLUS addressing for AVR_TINY.
1870 (avr_regno_mode_code_ok_for_base_p) [AVR_TINY]: Ignore -mstrict-X.
1871 (avr_out_plus_1) [AVR_TINY]: Tweak ++Y and --Y.
1872 (avr_mode_code_base_reg_class) [AVR_TINY]: Always return POINTER_REGS.
1874 2024-02-29 Georg-Johann Lay <avr@gjlay.de>
1876 PR target/114132
1877 * config/avr/avr.h (CUMULATIVE_ARGS) <has_stack_args>: New field.
1878 * config/avr/avr.cc (avr_init_cumulative_args): Initialize it.
1879 (avr_function_arg): Set it.
1880 (avr_frame_pointer_required_p): Use it instead of .nregs.
1882 2024-02-29 Andrew Pinski <quic_apinski@quicinc.com>
1884 PR target/108174
1885 * config/aarch64/aarch64-builtins.cc (aarch64_memtag_builtin_data): Make
1886 static and mark with GTY.
1888 2024-02-29 Xi Ruoyao <xry111@xry111.site>
1890 * config/loongarch/loongarch.md
1891 (loongarch_<crc>_w_<size>_w_extended): New define_insn.
1893 2024-02-29 Xi Ruoyao <xry111@xry111.site>
1895 * config/loongarch/loongarch.md (CRC): New define_int_iterator.
1896 (crc): New define_int_attr.
1897 (loongarch_crc_w_<size>_w, loongarch_crcc_w_<size>_w): Unify
1898 into ...
1899 (loongarch_<crc>_w_<size>_w): ... here.
1901 2024-02-29 Kito Cheng <kito.cheng@sifive.com>
1903 PR target/114130
1904 * config/riscv/sync.md (atomic_compare_and_swap<mode>): Sign
1905 extend the expected value if needed.
1907 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
1909 * config.gcc (target_gtfiles): Change coreout to btfext-out.
1910 (extra_objs): Change coreout to btfext-out.
1911 * config/bpf/coreout.cc: Rename to btfext-out.cc.
1912 * config/bpf/btfext-out.cc: Add.
1913 * config/bpf/coreout.h: Rename to btfext-out.h.
1914 * config/bpf/btfext-out.h: Add.
1915 * config/bpf/core-builtins.cc: Change include.
1916 * config/bpf/core-builtins.h: Change include.
1917 * config/bpf/t-bpf: Accomodate renamed files.
1919 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
1921 PR target/113453
1922 * config/bpf/bpf.cc (bpf_function_prologue): Define target
1923 hook.
1924 * config/bpf/coreout.cc (brf_ext_info_section)
1925 (btf_ext_info): Move from coreout.h
1926 (btf_ext_funcinfo, btf_ext_lineinfo): Add struct.
1927 (bpf_core_reloc): Rename to btf_ext_core_reloc.
1928 (btf_ext): Add static variable.
1929 (btfext_info_sec_find_or_add, SEARCH_NODE_AND_RETURN)
1930 (bpf_create_or_find_funcinfo, bpt_create_core_reloc)
1931 (btf_ext_add_string, btf_funcinfo_type_callback)
1932 (btf_add_func_info_for, btf_validate_funcinfo)
1933 (btf_ext_info_len, output_btfext_func_info): Add function.
1934 (output_btfext_header, bpf_core_reloc_add)
1935 (output_btfext_core_relocs, btf_ext_init, btf_ext_output):
1936 Change to support new structs.
1937 * config/bpf/coreout.h (btf_ext_funcinfo, btf_ext_lineinfo):
1938 Move and change in coreout.cc.
1939 (btf_add_func_info_for, btf_ext_add_string): Add prototypes.
1941 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
1943 * config/bpf/bpf.cc (bpf_option_override): Make .BTF.ext
1944 enabled by default for BPF.
1945 (bpf_file_end): Call BTF deallocation.
1946 (bpf_asm_init_sections): Correct condition.
1947 * dwarf2ctf.cc (ctf_debug_finalize): Conditionally execute BTF
1948 deallocation.
1949 (ctf_debuf_finish): Correct condition for calling
1950 ctf_debug_finalize.
1952 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
1954 * btfout.cc (output_btf_func_types): Use FOR_EACH_VEC_ELT.
1955 (traverse_btf_func_types): Define function.
1956 * ctfc.h (funcs_traverse_callback): Typedef for function
1957 prototype.
1958 (traverse_btf_func_types): Add prototype.
1960 2024-02-28 Cupertino Miranda <cupertino.miranda@oracle.com>
1962 * btfout.cc (btf_collect_dataset): Corrects BTF type id.
1964 2024-02-28 Richard Biener <rguenther@suse.de>
1966 PR tree-optimization/113831
1967 PR tree-optimization/108355
1968 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Revert
1969 PR113831 fix.
1971 2024-02-28 Richard Biener <rguenther@suse.de>
1973 PR tree-optimization/114121
1974 * tree-ssa-sccvn.h (vn_reference_s::offset,
1975 vn_reference_s::max_size): New fields.
1976 (vn_reference_insert_pieces): Adjust prototype.
1977 * tree-ssa-pre.cc (phi_translate_1): Preserve offset/max_size.
1978 * tree-ssa-sccvn.cc (vn_reference_eq): Compare offset and
1979 size, allow using "don't know" state.
1980 (vn_walk_cb_data::finish): Pass along offset/max_size.
1981 (vn_reference_lookup_or_insert_for_pieces): Take offset and
1982 max_size as argument and use it.
1983 (vn_reference_lookup_3): Properly adjust offset and max_size
1984 according to the adjusted ao_ref.
1985 (vn_reference_lookup_pieces): Initialize offset and max_size.
1986 (vn_reference_lookup): Likewise.
1987 (vn_reference_lookup_call): Likewise.
1988 (vn_reference_insert): Likewise.
1989 (visit_reference_op_call): Likewise.
1990 (vn_reference_insert_pieces): Take offset and max_size
1991 as argument and use it.
1993 2024-02-28 Juergen Christ <jchrist@linux.ibm.com>
1995 PR tree-optimization/114075
1996 * tree-vect-stmts.cc (vectorizable_operation): Don't emulate floating
1997 point vectors
1999 2024-02-28 Jakub Jelinek <jakub@redhat.com>
2001 PR tree-optimization/114041
2002 * graphite-sese-to-poly.cc (add_conditions_to_domain): Check for
2003 INTEGRAL_TYPE_P check rather than INTEGER_TYPE.
2005 2024-02-28 Jakub Jelinek <jakub@redhat.com>
2007 PR tree-optimization/113988
2008 * stor-layout.h (bitwise_mode_for_size): Declare.
2009 * stor-layout.cc (bitwise_mode_for_size): New function.
2010 * gimple-fold.cc (gimple_fold_builtin_memory_op): Use it.
2011 Use bitwise_type_for_mode instead of build_nonstandard_integer_type.
2012 Use BITS_PER_UNIT instead of 8.
2014 2024-02-27 Uros Bizjak <ubizjak@gmail.com>
2016 PR target/113871
2017 * config/i386/mmx.md (V248FI): Add V2BF mode.
2018 (V24FI_32): Ditto.
2020 2024-02-27 Eric Botcazou <ebotcazou@adacore.com>
2022 * tree-ssa-dse.cc (compute_trims): Fix description. Return early
2023 if either ref->offset is not byte aligned or ref->size is not known
2024 to be equal to ref->max_size.
2025 (maybe_trim_complex_store): Fix description.
2026 (maybe_trim_constructor_store): Likewise.
2027 (maybe_trim_partially_dead_store): Likewise.
2029 2024-02-27 Richard Earnshaw <rearnsha@arm.com>
2031 * config/arm/mmintrin.h: Warn if this header is included without
2032 defining __ENABLE_DEPRECATED_IWMMXT.
2034 2024-02-27 Richard Biener <rguenther@suse.de>
2036 PR tree-optimization/114074
2037 * tree-chrec.h (chrec_convert_rhs): Default at_stmt arg to NULL.
2038 * tree-chrec.cc (chrec_fold_multiply): Canonicalize inputs.
2039 Handle poly vs. non-poly multiplication correctly with respect
2040 to undefined behavior on overflow.
2042 2024-02-27 Jakub Jelinek <jakub@redhat.com>
2044 PR rtl-optimization/114044
2045 * internal-fn.def (CLRSB, CLZ, CTZ, FFS, PARITY): Use
2046 DEF_INTERNAL_INT_EXT_FN macro rather than DEF_INTERNAL_INT_FN.
2047 * internal-fn.h (expand_CLRSB, expand_CLZ, expand_CTZ, expand_FFS,
2048 expand_PARITY): Declare.
2049 * internal-fn.cc (expand_bitquery, expand_CLRSB, expand_CLZ,
2050 expand_CTZ, expand_FFS, expand_PARITY): New functions.
2051 (expand_POPCOUNT): Use expand_bitquery.
2053 2024-02-27 Richard Biener <rguenther@suse.de>
2055 PR tree-optimization/114081
2056 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2057 Perform manual dominator update for prologue peeling.
2058 (vect_do_peeling): Properly update dominators after adding the
2059 prologue-around guard.
2061 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
2063 * config/avr/avr.opt (mcall-prologues, mrelax, maccumulate-args)
2064 (mstrict-X): Tag as "Optimization".
2066 2024-02-26 Georg-Johann Lay <avr@gjlay.de>
2068 * config/avr/avr.cc (avr_out_compare) [AVR_TINY]: Remove code in
2069 an "if avr_adiw_reg_p()" block that's dead for AVR_TINY.
2071 2024-02-26 Jakub Jelinek <jakub@redhat.com>
2072 H.J. Lu <hjl.tools@gmail.com>
2074 PR rtl-optimization/113617
2075 * varasm.cc (default_elf_select_rtx_section): For
2076 references to private symbols in comdat sections
2077 use .data.relro.local.pool.<comdat>, .data.relro.pool.<comdat>
2078 or .rodata.<comdat> comdat sections.
2080 2024-02-26 Richard Biener <rguenther@suse.de>
2082 PR tree-optimization/114099
2083 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
2084 Create and fill in a needed virtual LC PHI for the alternate
2085 exits. Remove code dealing with that missing.
2087 2024-02-26 Richard Biener <rguenther@suse.de>
2089 PR tree-optimization/114068
2090 * tree-vect-loop-manip.cc (get_live_virtual_operand_on_edge):
2091 New function.
2092 (slpeel_tree_duplicate_loop_to_edge_cfg): Add a virtual LC PHI
2093 on the main exit if needed. Remove band-aid for the case
2094 it was missing.
2096 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
2098 PR target/114097
2099 * config/i386/i386-options.cc (ix86_set_func_type): Check
2100 interrupt instead of noreturn attribute.
2102 2024-02-26 Jakub Jelinek <jakub@redhat.com>
2104 * config/i386/i386.cc (ix86_bitint_type_info): Add support for
2105 !TARGET_64BIT.
2107 2024-02-26 Jakub Jelinek <jakub@redhat.com>
2109 PR tree-optimization/114090
2110 * match.pd ((x >= 0 ? x : 0) + (x <= 0 ? -x : 0) -> abs x):
2111 Restrict pattern to ANY_INTEGRAL_TYPE_P and TYPE_OVERFLOW_UNDEFINED
2112 types.
2113 ((x <= 0 ? -x : 0) -> max(-x, 0)): Likewise.
2115 2024-02-26 Jakub Jelinek <jakub@redhat.com>
2117 PR middle-end/114084
2118 * fold-const.cc (fold_binary_loc): Avoid the final associate_trees
2119 if all subtrees of var0 come from one of the op0 or op1 operands
2120 and all subtrees of con0 come from the other one. Don't clear
2121 variables which are never used afterwards.
2123 2024-02-26 Richard Biener <rguenther@suse.de>
2125 PR middle-end/114070
2126 * genmatch.cc (parser::parse_c_expr): Do not record operand
2127 lists but only mark operators used.
2128 * match.pd ((c ? a : b) op (c ? d : e) --> c ? (a op d) : (b op e)):
2129 Properly guard the case of tcc_comparison changing the VEC_COND
2130 value operand type.
2132 2024-02-26 Jakub Jelinek <jakub@redhat.com>
2134 PR target/114094
2135 * config/i386/i386.cc (x86_function_profiler): Add missing new-line
2136 to printed instruction.
2138 2024-02-26 H.J. Lu <hjl.tools@gmail.com>
2140 PR target/114098
2141 * config/i386/amxtileintrin.h (_tile_loadconfig): Use
2142 __builtin_ia32_ldtilecfg.
2143 (_tile_storeconfig): Use __builtin_ia32_sttilecfg.
2144 * config/i386/i386-builtin.def (BDESC): Add
2145 __builtin_ia32_ldtilecfg and __builtin_ia32_sttilecfg.
2146 * config/i386/i386-expand.cc (ix86_expand_builtin): Handle
2147 IX86_BUILTIN_LDTILECFG and IX86_BUILTIN_STTILECFG.
2148 * config/i386/i386.md (ldtilecfg): New pattern.
2149 (sttilecfg): Likewise.
2151 2024-02-24 Richard Sandiford <richard.sandiford@arm.com>
2153 PR tree-optimization/113205
2154 * tree-vect-slp.cc (vect_optimize_slp_pass::forward_cost): Reject
2155 the proposed layout if it does not allow a source partition with
2156 layout 2 to keep that layout.
2158 2024-02-24 Jakub Jelinek <jakub@redhat.com>
2160 * builtins.cc (fold_builtin_isascii): Use HOST_WIDE_INT_UC macro.
2161 * combine.cc (make_field_assignment): Use HOST_WIDE_INT_1U macro.
2162 * double-int.cc (double_int::mask): Use HOST_WIDE_INT_UC macros.
2163 * genattrtab.cc (attr_alt_complement): Use HOST_WIDE_INT_1 macro.
2164 (mk_attr_alt): Use HOST_WIDE_INT_0 macro.
2165 * genautomata.cc (bitmap_set_bit, CLEAR_BIT): Use HOST_WIDE_INT_1
2166 macros.
2167 * ipa-strub.cc (can_strub_internally_p): Use HOST_WIDE_INT_1 macro.
2168 * loop-iv.cc (implies_p): Use HOST_WIDE_INT_1U macro.
2169 * pretty-print.cc (test_pp_format): Use HOST_WIDE_INT_C and
2170 HOST_WIDE_INT_UC macros.
2171 * rtlanal.cc (nonzero_bits1): Use HOST_WIDE_INT_UC macro.
2172 * tree.cc (build_replicated_int_cst): Use HOST_WIDE_INT_1U macro.
2173 * tree.h (DECL_OFFSET_ALIGN): Use HOST_WIDE_INT_1U macro.
2174 * tree-ssa-structalias.cc (dump_varinfo): Use ~HOST_WIDE_INT_0U
2175 macros.
2176 * wide-int.cc (divmod_internal_2): Use HOST_WIDE_INT_1U macro.
2177 * config/i386/constraints.md (define_constraint "L"): Use
2178 HOST_WIDE_INT_C macro.
2179 * config/i386/i386.md (movabsq split peephole2): Use HOST_WIDE_INT_C
2180 macro.
2181 (movl + movb peephole2): Likewise.
2182 * config/i386/predicates.md (x86_64_zext_immediate_operand): Likewise.
2183 (const_32bit_mask): Likewise.
2185 2024-02-24 Jakub Jelinek <jakub@redhat.com>
2187 PR middle-end/114073
2188 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle
2189 VIEW_CONVERT_EXPRs between large/huge _BitInt and non-integer/pointer
2190 types like vector or complex types.
2191 (gimple_lower_bitint): Don't merge VIEW_CONVERT_EXPRs to non-integral
2192 types. Fix up VIEW_CONVERT_EXPR handling. Allow merging
2193 VIEW_CONVERT_EXPR from non-integral/pointer types with a store.
2195 2024-02-23 Robin Dapp <rdapp@ventanamicro.com>
2197 PR target/114028
2198 * config/riscv/riscv-v.cc (rvv_builder::can_duplicate_repeating_sequence_p):
2199 Return false if inner mode is already Pmode.
2200 (rvv_builder::is_all_same_sequence): New function.
2201 (expand_vec_init): Emit broadcast if sequence is all same.
2203 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
2205 PR target/113613
2206 * config/aarch64/aarch64-early-ra.cc
2207 (early_ra::m_current_region): New member variable.
2208 (early_ra::m_fpr_recency): Likewise.
2209 (early_ra::start_new_region): Bump m_current_region.
2210 (early_ra::allocate_colors): Prefer less recently used registers
2211 in the event of a tie. Add a comment to explain why we prefer(ed)
2212 higher-numbered registers.
2213 (early_ra::find_oldest_color): Prefer less recently used registers
2214 here too.
2215 (early_ra::finalize_allocation): Update recency information for
2216 allocated registers.
2217 (early_ra::process_blocks): Initialize m_current_region and
2218 m_fpr_recency.
2220 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
2222 PR target/113295
2223 * config/aarch64/aarch64-early-ra.cc
2224 (early_ra::test_strictness): New enum.
2225 (early_ra::is_chain_candidate): Add a strictness parameter to
2226 control whether only correctness matters, or whether both correctness
2227 and heuristics should be used. Handle multiple levels of equivalence.
2228 (early_ra::find_related_start): Update call accordingly.
2229 (early_ra::strided_polarity_pref): Likewise.
2230 (early_ra::form_chains): Likewise.
2231 (early_ra::try_to_chain_allocnos): Use is_chain_candidate in
2232 correctness mode rather than trying to inline the test.
2234 2024-02-23 Richard Sandiford <richard.sandiford@arm.com>
2236 PR target/113295
2237 * config/aarch64/aarch64-early-ra.cc
2238 (early_ra::find_related_start): Account for definitions by shared
2239 registers when testing for a single register definition.
2240 (early_ra::accumulate_defs): New function.
2241 (early_ra::record_copy): If A shares B's register, fold A's
2242 definition information into B's. Fold A's use information into B's.
2244 2024-02-23 H.J. Lu <hjl.tools@gmail.com>
2246 * configure.ac (HAVE_AS_R_X86_64_CODE_6_GOTTPOFF): Defined as 1
2247 if R_X86_64_CODE_6_GOTTPOFF is supported.
2248 * config.in: Regenerated.
2249 * configure: Likewise.
2250 * config/i386/predicates.md (apx_ndd_add_memory_operand): Allow
2251 UNSPEC_GOTNTPOFF if R_X86_64_CODE_6_GOTTPOFF is supported.
2253 2024-02-23 Richard Earnshaw <rearnsha@arm.com>
2255 PR target/108120
2256 * config/arm/neon.md (div<VCVTF:mode>3): Rename from div<mode>3.
2257 Gate with ARM_HAVE_NEON_<MODE>_ARITH.
2259 2024-02-23 Jakub Jelinek <jakub@redhat.com>
2261 PR rtl-optimization/114054
2262 * expr.cc (expand_expr_real_2) <case MULT_EXPR>: Use
2263 temp variable instead of target parameter for result.
2265 2024-02-23 Jakub Jelinek <jakub@redhat.com>
2267 PR tree-optimization/114040
2268 * gimple-lower-bitint.cc (bitint_large_huge::lower_addsub_overflow):
2269 Use EQ_EXPR rather than LT_EXPR for g2 condition and change its
2270 probability from likely to unlikely. When handling the true true
2271 store, first cast to limb_access_type and then to l's type.
2273 2024-02-23 Richard Biener <rguenther@suse.de>
2275 PR target/90785
2276 * config.gcc: Add ia64*-*-* to the list of obsoleted targets.
2278 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
2280 PR other/109668
2281 * config/riscv/arch-canonicalize: Move to python3
2282 * config/riscv/multilib-generator: Likewise
2284 2024-02-23 Palmer Dabbelt <palmer@rivosinc.com>
2286 * doc/invoke.texi: Document -mcpu.
2288 2024-02-23 Lulu Cheng <chenglulu@loongson.cn>
2290 * configure: Regenerate.
2291 * configure.ac: Add parameter "--fatal-warnings" to assemble
2292 when checking whether the assemble support conditional branch
2293 relaxation.
2295 2024-02-22 Jakub Jelinek <jakub@redhat.com>
2297 PR c/114007
2298 * doc/extend.texi: (__extension__): Remove comments about scope
2299 tokens vs. two colons.
2301 2024-02-22 Andrew Pinski <quic_apinski@quicinc.com>
2303 PR tree-optimization/109804
2304 * gimple-ssa-warn-access.cc (new_delete_mismatch_p): Handle
2305 DEMANGLE_COMPONENT_UNNAMED_TYPE.
2307 2024-02-22 Richard Biener <rguenther@suse.de>
2309 PR tree-optimization/114048
2310 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): MEM_REF
2311 can also produce -1 off.
2313 2024-02-22 Richard Biener <rguenther@suse.de>
2315 PR tree-optimization/114027
2316 * tree-vect-loop.cc (vecctorizable_reduction): Use optimized
2317 condition reduction classification only for single-element
2318 chains.
2320 2024-02-22 Jakub Jelinek <jakub@redhat.com>
2322 PR ipa/111960
2323 * profile-count.h (profile_count::dump): Remove overload with
2324 char * first argument.
2325 * profile-count.cc (profile_count::dump): Change overload with char *
2326 first argument which uses sprintf into the overfload with FILE *
2327 first argument and use fprintf instead. Remove overload which wrapped
2328 it.
2330 2024-02-22 Jakub Jelinek <jakub@redhat.com>
2332 PR tree-optimization/113993
2333 * tree-call-cdce.cc (get_no_error_domain): Handle
2334 BUILT_IN_{COSH,SINH,EXP{,M1,2}}{F32X,F64X}. Handle
2335 BUILT_IN_{COSH,SINH,EXP{,M1,2}}L for
2336 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
2337 the as the F128 suffixed cases, otherwise as non-suffixed ones.
2338 Handle BUILT_IN_{EXP,POW}10L for
2339 REAL_MODE_FORMAT (TYPE_MODE (long_double_type_node))->emax == 16384
2340 as (-inf, 4932).
2342 2024-02-22 Jakub Jelinek <jakub@redhat.com>
2344 PR tree-optimization/114038
2345 * gimple-lower-bitint.cc (bitint_large_huge::lower_mul_overflow): Fix
2346 loop exit condition if end is divisible by limb_prec.
2348 2024-02-22 YunQiang Su <syq@gcc.gnu.org>
2350 * doc/invoke.texi(MIPS Options): Fix skipping UrlSuffix
2351 problem of mabi=, mno-flush-func, mexplicit-relocs;
2352 add missing leading - of mbranch-cost option.
2353 * config/mips/mips.opt.urls: Regenerate.
2355 2024-02-22 Kewen Lin <linkw@linux.ibm.com>
2357 PR target/109987
2358 * config/rs6000/constraints.md (we): Update internal doc without
2359 referring to option -mpower9-vector.
2360 * config/rs6000/driver-rs6000.cc (asm_names): Remove mpower9-vector
2361 special handlings.
2362 * config/rs6000/rs6000-cpus.def (OTHER_P9_VECTOR_MASKS,
2363 OTHER_P8_VECTOR_MASKS): Merge to ...
2364 (OTHER_VSX_VECTOR_MASKS): ... here.
2365 * config/rs6000/rs6000.cc (rs6000_option_override_internal): Remove
2366 some error message handlings and explicit option mask adjustments on
2367 explicit option power{8,9}-vector conflicting with other options.
2368 (rs6000_print_isa_options): Update comments.
2369 (rs6000_disable_incompatible_switches): Remove power{8,9}-vector
2370 related array items and handlings.
2371 * config/rs6000/rs6000.h (ASM_CPU_SPEC): Remove mpower9-vector
2372 special handlings.
2373 * config/rs6000/rs6000.opt: Make option power{8,9}-vector as
2374 WarnRemoved.
2375 * doc/extend.texi: Remove documentation referring to option
2376 -mpower8-vector.
2377 * doc/invoke.texi: Remove documentation for option
2378 -mpower{8,9}-vector and adjust some documentation referring to them.
2379 * doc/md.texi: Update documentation for constraint we.
2380 * doc/sourcebuild.texi: Remove documentation for powerpc_p8vector_ok.
2382 2024-02-22 Pan Li <pan2.li@intel.com>
2384 PR target/114017
2385 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Upgrade
2386 the version to 0.12.
2388 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
2390 * config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert
2392 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
2393 Robin Dapp <rdapp.gcc@gmail.com>
2395 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
2396 (generic_ooo_vec_load): Ditto
2397 (generic_ooo_vec_store): Ditto
2398 (generic_ooo_vec_loadstore_seg): Ditto
2399 (generic_ooo_vec_alu): Ditto
2400 (generic_ooo_vec_fcmp): Ditto
2401 (generic_ooo_vec_imul): Ditto
2402 (generic_ooo_vec_fadd): Ditto
2403 (generic_ooo_vec_fmul): Ditto
2404 (generic_ooo_crypto): Ditto
2405 (generic_ooo_perm): Ditto
2406 (generic_ooo_vec_reduction): Ditto
2407 (generic_ooo_vec_ordered_reduction): Ditto
2408 (generic_ooo_vec_idiv): Ditto
2409 (generic_ooo_vec_float_divsqrt): Ditto
2410 (generic_ooo_vec_mask): Ditto
2411 (generic_ooo_vec_vesetvl): Ditto
2412 (generic_ooo_vec_setrm): Ditto
2413 (generic_ooo_vec_readlen): Ditto
2414 * config/riscv/riscv.md: Include generic-vector-ooo
2415 * config/riscv/generic-vector-ooo.md: New file. To here
2417 2024-02-21 Edwin Lu <ewlu@rivosinc.com>
2419 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
2420 (generic_ooo_branch): Ditto
2421 * config/riscv/generic.md (generic_sfb_alu): Ditto
2422 (generic_fmul_half): Ditto
2423 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
2424 * config/riscv/sifive-7.md (sifive_7_hfma): Add reservation
2425 (sifive_7_popcount): Ditto
2426 * config/riscv/sifive-p400.md (sifive_p400_clmul): Ditto
2427 * config/riscv/sifive-p600.md (sifive_p600_clmul): Ditto
2428 * config/riscv/vector.md: Change rdfrm to fmove
2429 * config/riscv/zc.md: Change pushpop to load/store
2431 2024-02-21 Jonathan Wakely <jwakely@redhat.com>
2433 * doc/invoke.texi (Warning Options): Fix typos.
2435 2024-02-21 David Faust <david.faust@oracle.com>
2437 * config/bpf/bpf-protos.h (bpf_expand_cpymem): New.
2438 * config/bpf/bpf.cc: (emit_move_loop, bpf_expand_cpymem): New.
2439 * config/bpf/bpf.md: (cpymemdi, movmemdi): New define_expands.
2441 2024-02-21 Martin Jambor <mjambor@suse.cz>
2443 PR ipa/113476
2444 * ipa-prop.h (ipa_node_params): Convert lattices to a vector, adjust
2445 initializers in the contructor.
2446 (ipa_node_params::~ipa_node_params): Release lattices as a vector.
2447 * ipa-cp.h: New file.
2448 * ipa-cp.cc: Include sreal.h and ipa-cp.h.
2449 (ipcp_value_source): Move to ipa-cp.h.
2450 (ipcp_value_base): Likewise.
2451 (ipcp_value): Likewise.
2452 (ipcp_lattice): Likewise.
2453 (ipcp_agg_lattice): Likewise.
2454 (ipcp_bits_lattice): Likewise.
2455 (ipcp_vr_lattice): Likewise.
2456 (ipcp_param_lattices): Likewise.
2457 (ipa_get_parm_lattices): Remove assert latticess is non-NULL.
2458 (ipa_value_from_jfunc): Adjust a check for empty lattices.
2459 (ipa_context_from_jfunc): Likewise.
2460 (ipa_agg_value_from_jfunc): Likewise.
2461 (merge_agg_lats_step): Do not memset new aggregate lattices to zero.
2462 (ipcp_propagate_stage): Allocate lattices in a vector as opposed to
2463 just in contiguous memory.
2464 (ipcp_store_vr_results): Adjust a check for empty lattices.
2465 * auto-profile.cc: Include sreal.h and ipa-cp.h.
2466 * cgraph.cc: Likewise.
2467 * cgraphclones.cc: Likewise.
2468 * cgraphunit.cc: Likewise.
2469 * config/aarch64/aarch64.cc: Likewise.
2470 * config/i386/i386-builtins.cc: Likewise.
2471 * config/i386/i386-expand.cc: Likewise.
2472 * config/i386/i386-features.cc: Likewise.
2473 * config/i386/i386-options.cc: Likewise.
2474 * config/i386/i386.cc: Likewise.
2475 * config/rs6000/rs6000.cc: Likewise.
2476 * config/s390/s390.cc: Likewise.
2477 * gengtype.cc (open_base_files): Added sreal.h and ipa-cp.h to the
2478 files to be included in gtype-desc.cc.
2479 * gimple-range-fold.cc: Include sreal.h and ipa-cp.h.
2480 * ipa-devirt.cc: Likewise.
2481 * ipa-fnsummary.cc: Likewise.
2482 * ipa-icf.cc: Likewise.
2483 * ipa-inline-analysis.cc: Likewise.
2484 * ipa-inline-transform.cc: Likewise.
2485 * ipa-inline.cc: Include ipa-cp.h, move inclusion of sreal.h higher.
2486 * ipa-modref.cc: Include sreal.h and ipa-cp.h.
2487 * ipa-param-manipulation.cc: Likewise.
2488 * ipa-predicate.cc: Likewise.
2489 * ipa-profile.cc: Likewise.
2490 * ipa-prop.cc: Likewise.
2491 (ipa_node_params_t::duplicate): Assert new lattices remain empty
2492 instead of setting them to NULL.
2493 * ipa-pure-const.cc: Include sreal.h and ipa-cp.h.
2494 * ipa-split.cc: Likewise.
2495 * ipa-sra.cc: Likewise.
2496 * ipa-strub.cc: Likewise.
2497 * ipa-utils.cc: Likewise.
2498 * ipa.cc: Likewise.
2499 * toplev.cc: Likewise.
2500 * tree-ssa-ccp.cc: Likewise.
2501 * tree-ssa-sccvn.cc: Likewise.
2502 * tree-vrp.cc: Likewise.
2504 2024-02-21 Tamar Christina <tamar.christina@arm.com>
2506 * config/aarch64/aarch64-arches.def (AARCH64_ARCH): Remove LS64 from
2507 Armv8.7-a.
2509 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2511 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
2512 Use aarch64_gen_compare_zero_and_branch rather than emitting
2513 a CBZ directly.
2515 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2517 * config/aarch64/aarch64.cc (aarch64_option_valid_attribute_p):
2518 Remove duplicated call.
2520 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2522 * config/aarch64/aarch64.cc (aarch64_function_ok_for_sibcall):
2523 Check that each individual piece of state is shared in the same
2524 way, rather than using an aggregate check for PSTATE.ZA.
2526 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2528 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
2529 In the code that commits a lazy save, only zero ZA if the function
2530 has ZA state. Similarly zero ZT0 if the function has ZT0 state.
2532 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2534 * config/aarch64/aarch64-sme.md (aarch64_commit_lazy_save): Remove,
2535 directly inserting the associated sequence
2536 * config/aarch64/aarch64.cc (aarch64_mode_emit_local_sme_state):
2537 ...here instead.
2539 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2541 PR target/113995
2542 * config/aarch64/aarch64.cc (aarch64_expand_prologue): Don't
2543 fold the SVE allocation into the initial allocation if the
2544 initial allocation includes a VG save.
2546 2024-02-21 Richard Sandiford <richard.sandiford@arm.com>
2548 PR target/113220
2549 * cfgrtl.cc (commit_one_edge_insertion): Handle sequences that
2550 contain jumps even if called after initial RTL expansion.
2551 * mode-switching.cc: Include cfgbuild.h.
2552 (optimize_mode_switching): Allow the sequence returned by the
2553 emit hook to contain internal jumps. Record which blocks
2554 contain such jumps and split the blocks at the end.
2555 * config/aarch64/aarch64.cc (aarch64_mode_emit): Check for
2556 non-debug insns when scanning the sequence.
2558 2024-02-21 Tobias Burnus <tburnus@baylibre.com>
2560 * config/nvptx/gen-omp-device-properties.sh: Add 'nvptx64' to arch.
2561 * config/nvptx/nvptx.cc (nvptx_omp_device_kind_arch_isa): Likewise.
2563 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
2565 * doc/invoke.texi (-mmcu): Add information about MCU specs.
2567 2024-02-21 Dimitar Dimitrov <dimitar@dinux.eu>
2569 * doc/invoke.texi (-minrt): Clarify that main
2570 must take no arguments.
2572 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
2574 * config/avr/builtins.def: Use function prototypes of given size
2575 and signedness.
2576 * config/avr/avr.cc (avr_init_builtins): Adjust types required
2577 by builtins.def.
2578 * doc/extend.texi (AVR Built-in Functions): Adjust accordingly.
2580 2024-02-20 Georg-Johann Lay <avr@gjlay.de>
2582 * doc/extend.texi (AVR Built-in Functions): Use @defbuiltin
2583 instead of @table.
2585 2024-02-20 Will Hawkins <hawkinsw@obs.cr>
2587 * config/bpf/bpf.opt: Add help information for -mcpu.
2589 2024-02-20 Richard Sandiford <richard.sandiford@arm.com>
2591 PR target/113805
2592 * config/aarch64/aarch64-passes.def (pass_late_track_speculation):
2593 New pass.
2594 * config/aarch64/aarch64-protos.h (make_pass_late_track_speculation):
2595 Declare.
2596 * config/aarch64/aarch64.md (is_call): New attribute.
2597 (*and<mode>3nr_compare0): Rename to...
2598 (@aarch64_and<mode>3nr_compare0): ...this.
2599 * config/aarch64/aarch64-sme.md (aarch64_get_sme_state)
2600 (aarch64_tpidr2_save, aarch64_tpidr2_restore): Add is_call attributes.
2601 * config/aarch64/aarch64-speculation.cc: Update file comment to
2602 describe the new late pass.
2603 (aarch64_do_track_speculation): Handle is_call insns like other calls.
2604 (pass_track_speculation): Add an is_late member variable.
2605 (pass_track_speculation::gate): Run the late pass for streaming-
2606 compatible functions and the early pass for other functions.
2607 (make_pass_track_speculation): Update accordingly.
2608 (make_pass_late_track_speculation): New function.
2609 * config/aarch64/aarch64.cc (aarch64_gen_test_and_branch): New
2610 function.
2611 (aarch64_guard_switch_pstate_sm): Use it.
2613 2024-02-19 Iain Sandoe <iain@sandoe.co.uk>
2615 * config/aarch64/aarch64-builtins.cc (aarch64_init_rng_builtins):
2616 Register these builtins with a pointer to uint64_t rather than unsigned
2617 DI mode.
2619 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
2621 PR target/113615
2622 * config/gcn/gcn-valu.md (define_expand "reduc_<fexpander>_scal_<mode>"):
2623 Conditionalize on '!TARGET_RDNA2_PLUS'.
2624 * config/gcn/gcn.cc (gcn_expand_dpp_shr_insn)
2625 (gcn_expand_reduc_scalar):
2626 'gcc_checking_assert (!TARGET_RDNA2_PLUS);'.
2628 2024-02-19 Thomas Schwinge <tschwinge@baylibre.com>
2630 * config/gcn/gcn.h (TARGET_CPU_CPP_BUILTINS): Restore lost
2631 '__gfx90a__' target CPU definition. Add some safeguards for the future.
2633 2024-02-19 Richard Biener <rguenther@suse.de>
2635 PR rtl-optimization/54052
2636 * rtl-ssa/blocks.cc (function_info::place_phis): Filter
2637 local defs by LR_OUT.
2639 2024-02-19 Jakub Jelinek <jakub@redhat.com>
2641 PR tree-optimization/113967
2642 * match.pd (bit_insert @0 (BIT_FIELD_REF @1 ..) ..): Require
2643 in condition that @rpos is multiple of vector element size.
2645 2024-02-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
2647 PR target/113696
2648 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info):
2649 Suppress vsetvl fusion.
2651 2024-02-18 H.J. Lu <hjl.tools@gmail.com>
2653 PR target/113912
2654 * config/i386/i386.cc (ix86_can_use_push2pop2): New.
2655 (ix86_pro_and_epilogue_can_use_push2pop2): Use it.
2656 (ix86_emit_save_regs): Don't generate push2 if
2657 ix86_can_use_push2pop2 return false.
2658 (ix86_expand_epilogue): Don't generate pop2 if
2659 ix86_can_use_push2pop2 return false.
2661 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
2663 * doc/invoke.texi (AVR Options) <-mmcu>: Remove "Atmel".
2664 Note on complete device support.
2666 2024-02-18 Georg-Johann Lay <avr@gjlay.de>
2668 * doc/extend.texi (AVR Function Attributes): Fuse description
2669 of "signal" and "interrupt" attribute. Link pseudo instruction.
2671 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
2673 * config/loongarch/larchintrin.h (__movgr2fcsr): Remove redundant
2674 symbol type conversions.
2675 (__cacop_d): Likewise.
2676 (__cpucfg): Likewise.
2677 (__asrtle_d): Likewise.
2678 (__asrtgt_d): Likewise.
2679 (__lddir_d): Likewise.
2680 (__ldpte_d): Likewise.
2681 (__crc_w_b_w): Likewise.
2682 (__crc_w_h_w): Likewise.
2683 (__crc_w_w_w): Likewise.
2684 (__crc_w_d_w): Likewise.
2685 (__crcc_w_b_w): Likewise.
2686 (__crcc_w_h_w): Likewise.
2687 (__crcc_w_w_w): Likewise.
2688 (__crcc_w_d_w): Likewise.
2689 (__csrrd_w): Likewise.
2690 (__csrwr_w): Likewise.
2691 (__csrxchg_w): Likewise.
2692 (__csrrd_d): Likewise.
2693 (__csrwr_d): Likewise.
2694 (__csrxchg_d): Likewise.
2695 (__iocsrrd_b): Likewise.
2696 (__iocsrrd_h): Likewise.
2697 (__iocsrrd_w): Likewise.
2698 (__iocsrrd_d): Likewise.
2699 (__iocsrwr_b): Likewise.
2700 (__iocsrwr_h): Likewise.
2701 (__iocsrwr_w): Likewise.
2702 (__iocsrwr_d): Likewise.
2703 (__frecipe_s): Likewise.
2704 (__frecipe_d): Likewise.
2705 (__frsqrte_s): Likewise.
2706 (__frsqrte_d): Likewise.
2708 2024-02-18 Lulu Cheng <chenglulu@loongson.cn>
2710 * config/loongarch/larchintrin.h (__iocsrrd_h): Modify the
2711 function return value type to unsigned short.
2713 2024-02-16 Edwin Lu <ewlu@rivosinc.com>
2715 * doc/sourcebuild.texi: add scan-assembler-bound
2717 2024-02-16 Jason Merrill <jason@redhat.com>
2719 * gdbhooks.py: Fix regex syntax.
2721 2024-02-16 Richard Biener <rguenther@suse.de>
2723 PR tree-optimization/113895
2724 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Disable
2725 consistency checking when there are out-of-bound array
2726 accesses. Allow -1 off when from an array reference with
2727 constant index.
2729 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
2731 PR target/106543
2732 * config/riscv/riscv.md (*sge<u>_<X:mode><GPR:mode>): Fix asm
2733 pattern.
2735 2024-02-16 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
2737 * doc/sourcebuild.texi (Effective-Target Keywords, Other
2738 attribugs): Document linker_plugin.
2739 (Require Support): Document dg-require-linker-plugin.
2741 2024-02-16 Kito Cheng <kito.cheng@sifive.com>
2743 PR target/109349
2744 * common/config/riscv/riscv-common.cc (riscv_arch_help): New.
2745 * config/riscv/riscv-protos.h (RISCV_MAJOR_VERSION_BASE): New.
2746 (RISCV_MINOR_VERSION_BASE): Ditto.
2747 (RISCV_REVISION_VERSION_BASE): Ditto.
2748 * config/riscv/riscv-c.cc (riscv_ext_version_value): Use enum
2749 rather than magic number.
2750 * config/riscv/riscv.h (riscv_arch_help): New.
2751 (EXTRA_SPEC_FUNCTIONS): Add riscv_arch_help.
2752 (DRIVER_SELF_SPECS): Handle -march=help, -print-supported-extensions and
2753 --print-supported-extensions.
2754 * config/riscv/riscv.opt (march=help): New.
2755 (print-supported-extensions): New.
2756 (-print-supported-extensions): New.
2757 * doc/invoke.texi (RISC-V Options): Document -march=help.
2759 2024-02-16 Tejas Belagod <tejas.belagod@arm.com>
2761 PR target/113780
2762 * config/arm/arm.cc (arm_function_ok_for_sibcall): Don't allow tailcalls
2763 for indirect calls with 4 or more arguments in pac-enabled functions.
2765 2024-02-15 David Faust <david.faust@oracle.com>
2767 * config/bpf/bpf.md (zero_extendqidi2): Correct asm template to
2768 use ldxb instead of ldxh.
2770 2024-02-15 Jakub Jelinek <jakub@redhat.com>
2772 PR middle-end/113921
2773 * cfgrtl.h (prepend_insn_to_edge): New declaration.
2774 * cfgrtl.cc (insert_insn_on_edge): Clarify behavior in function
2775 comment.
2776 (prepend_insn_to_edge): New function.
2777 * cfgexpand.cc (expand_asm_stmt): Use prepend_insn_to_edge instead of
2778 insert_insn_on_edge.
2780 2024-02-15 Richard Biener <rguenther@suse.de>
2782 PR tree-optimization/111156
2783 * tree-vect-loop.cc (vect_dissolve_slp_only_groups): Look
2784 at the pattern stmt if any.
2786 2024-02-15 Georg-Johann Lay <avr@gjlay.de>
2788 PR target/113927
2789 * config/avr/avr.h (AVR_HAVE_ADIW): New macro.
2790 * config/avr/avr-protos.h (avr_adiw_reg_p): New proto.
2791 * config/avr/avr.cc (avr_adiw_reg_p): New function.
2792 (avr_conditional_register_usage) [AVR_TINY]: Don't clear ADDW_REGS.
2793 Replace test_hard_reg_class (ADDW_REGS, ...) with calls to
2794 * config/avr/avr.md: Same.
2795 (attr "isa") <tiny, no_tiny>: Remove.
2796 <adiw, no_adiw>: Add.
2797 (define_insn, define_insn_and_split): When an alternative has
2798 constraint "w", then set attribute "isa" to "adiw".
2799 * config/avr/avr-c.cc (avr_cpu_cpp_builtins) [AVR_HAVE_ADIW]:
2800 Built-in define __AVR_HAVE_ADIW__.
2801 * doc/invoke.texi (AVR Options): Document it.
2803 2024-02-15 Andrew Stubbs <ams@baylibre.com>
2805 * config/gcn/gcn-valu.md
2806 (vec_extract<V_MOV:mode><V_MOV_ALT:mode>): Add conditions for RDNA.
2807 * config/gcn/gcn.cc (gcn_vectorize_vec_perm_const): Check permutation
2808 details are supported on RDNA devices.
2810 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
2812 PR middle-end/113508
2813 * doc/md.texi (sdot_prod@var{m}, udot_prod@var{m},
2814 usdot_prod@var{m}, ssad@var{m}, usad@var{m}, widen_usum@var{m}3,
2815 smulhs@var{m}3, umulhs@var{m}3, smulhrs@var{m}3, umulhrs@var{m}3):
2816 Add sentence about what the mode m is.
2818 2024-02-15 Andrew Pinski <quic_apinski@quicinc.com>
2820 * doc/md.texi (widen_ssum, widen_usum, smulhs, umulhs,
2821 smulhrs, umulhrs, sdiv_pow2): Move the 3 outside of the
2822 var.
2824 2024-02-15 Richard Biener <rguenther@suse.de>
2826 * tree-ssa-tail-merge.cc (same_succ_hash): Skip debug
2827 stmts.
2829 2024-02-15 Jakub Jelinek <jakub@redhat.com>
2831 PR tree-optimization/113567
2832 * gimple-lower-bitint.cc (gimple_lower_bitint): For large/huge
2833 _BitInt multiplication, division or modulo with
2834 SSA_NAME_OCCURS_IN_ABNORMAL_PHI lhs and at least one of rhs1 and rhs2
2835 force the affected inputs into a new SSA_NAME.
2837 2024-02-14 Uros Bizjak <ubizjak@gmail.com>
2839 PR target/113871
2840 * config/i386/mmx.md (V248FI): New mode iterator.
2841 (V24FI_32): DItto.
2842 (vec_shl_<V248FI:mode>): New expander.
2843 (vec_shl_<V24FI_32:mode>): Ditto.
2844 (vec_shr_<V248FI:mode>): Ditto.
2845 (vec_shr_<V24FI_32:mode>): Ditto.
2846 * config/i386/sse.md (vec_shl_<V_128:mode>): Simplify expander.
2847 (vec_shr_<V248FI:mode>): Ditto.
2849 2024-02-14 Jan Hubicka <jh@suse.cz>
2851 PR tree-optimization/111054
2852 * tree-ssa-loop-split.cc (split_loop): Check for profile being present.
2854 2024-02-14 Tamar Christina <tamar.christina@arm.com>
2856 * tree-cfg.cc (replace_loop_annotate): Inspect loop edges for annotations.
2858 2024-02-14 Richard Biener <rguenther@suse.de>
2860 PR tree-optimization/113910
2861 * bitmap.cc (bitmap_hash): Mix the full element "hash" to
2862 the hashval_t hash.
2864 2024-02-14 Jakub Jelinek <jakub@redhat.com>
2866 * pretty-print.cc (PTRDIFF_MAX): Define if not yet defined.
2867 (pp_integer_with_precision): For unsigned ptrdiff_t printing
2868 with u, o or x print ptrdiff_t argument converted to
2869 unsigned long long and masked with 2ULL * PTRDIFF_MAX + 1.
2871 2024-02-14 Richard Biener <rguenther@suse.de>
2873 PR middle-end/113576
2874 * expr.cc (do_store_flag): For vector bool compares of vectors
2875 with padding zero that.
2876 * dojump.cc (do_compare_and_jump): Likewise.
2878 2024-02-14 Gerald Pfeifer <gerald@pfeifer.com>
2880 * doc/install.texi (Prerequisites): Update gettext link.
2882 2024-02-13 H.J. Lu <hjl.tools@gmail.com>
2884 PR target/113876
2885 * config/i386/i386.cc (ix86_pro_and_epilogue_can_use_push2pop2):
2886 Return false if the incoming stack isn't 16-byte aligned.
2888 2024-02-13 Tobias Burnus <tburnus@baylibre.com>
2890 PR middle-end/113904
2891 * omp-general.cc (struct omp_ts_info): Update for splitting of
2892 OMP_TRAIT_PROPERTY_EXPR into OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
2893 * omp-selectors.h (enum omp_tp_type): Replace
2894 OMP_TRAIT_PROPERTY_EXPR by OMP_TRAIT_PROPERTY_{DEV_NUM,BOOL}_EXPR.
2896 2024-02-13 Monk Chiang <monk.chiang@sifive.com>
2898 PR target/113742
2899 * config/riscv/riscv.cc (riscv_macro_fusion_pair_p): Fix
2900 recognizes UNSPEC_AUIPC for RISCV_FUSE_LUI_ADDI.
2902 2024-02-13 Richard Biener <rguenther@suse.de>
2904 PR tree-optimization/113895
2905 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Track
2906 offset to discover constant array indices in bits, handle
2907 COMPONENT_REF to bitfields.
2909 2024-02-13 Richard Biener <rguenther@suse.de>
2911 PR tree-optimization/113831
2912 * tree-ssa-sccvn.cc (ao_ref_init_from_vn_reference): Fix
2913 typo in comment.
2915 2024-02-13 Richard Biener <rguenther@suse.de>
2917 PR tree-optimization/113902
2918 * tree-vect-loop.cc (move_early_exit_stmts): Track
2919 last_seen_vuse for VUSE updating.
2921 2024-02-13 Tamar Christina <tamar.christina@arm.com>
2923 PR tree-optimization/113734
2924 * tree-vect-loop.cc (vect_transform_loop): Treat the final iteration of
2925 an early break loop as partial.
2927 2024-02-13 Richard Biener <rguenther@suse.de>
2929 PR tree-optimization/113898
2930 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): Add
2931 missing accumulated off adjustment.
2933 2024-02-13 Jakub Jelinek <jakub@redhat.com>
2935 * hwint.h (GCC_PRISZ, fmt_size_t): Fix preprocessor conditions,
2936 instead of comparing SIZE_MAX against INT_MAX and LONG_MAX compare
2937 it against UINT_MAX and ULONG_MAX.
2939 2024-02-13 David Malcolm <dmalcolm@redhat.com>
2941 * diagnostic-core.h (emit_diagnostic_valist): Rename overload
2942 to...
2943 (emit_diagnostic_valist_meta): ...this.
2944 * diagnostic.cc (emit_diagnostic_valist): Likewise, to...
2945 (emit_diagnostic_valist_meta): ...this.
2947 2024-02-12 Jakub Jelinek <jakub@redhat.com>
2949 PR tree-optimization/113849
2950 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't use
2951 fast path for widening casts where !m_upwards_2limb and lhs_type
2952 has precision which is a multiple of limb_prec.
2954 2024-02-12 Jakub Jelinek <jakub@redhat.com>
2956 PR c++/113674
2957 * attribs.cc (extract_attribute_substring): Remove.
2958 (lookup_scoped_attribute_spec): Don't call it.
2960 2024-02-12 Jakub Jelinek <jakub@redhat.com>
2962 * gengtype.cc (adjust_field_rtx_def): Use HOST_SIZE_T_PRINT_UNSIGNED
2963 and cast to fmt_size_t instead of %lu and cast to unsigned long.
2965 2024-02-12 Christophe Lyon <christophe.lyon@linaro.org>
2967 * Makefile.in: Add no-info dependency.
2968 * configure.ac: Set BUILD_INFO=no-info if makeinfo is not
2969 available.
2970 * configure: Regenerate.
2972 2024-02-12 Iain Sandoe <iain@sandoe.co.uk>
2974 PR target/113855
2975 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): Moved to be
2976 available to all sub-targets.
2977 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): Delete.
2978 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): Delete.
2980 2024-02-12 Richard Biener <rguenther@suse.de>
2982 PR tree-optimization/113831
2983 PR tree-optimization/108355
2984 * tree-ssa-sccvn.cc (copy_reference_ops_from_ref): When
2985 we see variable array indices and get_ref_base_and_extent
2986 can resolve those to constants fix up the ops to constants
2987 as well.
2988 (ao_ref_init_from_vn_reference): Use 'off' member for
2989 ARRAY_REF and ARRAY_RANGE_REF instead of recomputing it.
2990 (valueize_refs_1): Also fixup 'off' of ARRAY_RANGE_REF.
2992 2024-02-12 Pan Li <pan2.li@intel.com>
2994 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin):
2995 Replace args to arguments for misspelled term.
2997 2024-02-12 Georg-Johann Lay <avr@gjlay.de>
2999 PR target/112944
3000 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) [have_flmap]:
3001 <*link_rodata_in_ram>: Spec undefs symbol __do_flmap_init
3002 when not linked with -mrodata-in-ram.
3004 2024-02-12 Richard Biener <rguenther@suse.de>
3006 PR tree-optimization/113863
3007 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
3008 Record crossed virtual PHIs.
3009 * tree-vect-loop.cc (move_early_exit_stmts): Elide crossed
3010 virtual PHIs.
3012 2024-02-10 Marek Polacek <polacek@redhat.com>
3014 DR 2237
3015 PR c++/107126
3016 PR c++/97202
3017 * doc/invoke.texi: Document -Wtemplate-id-cdtor.
3019 2024-02-10 Jakub Jelinek <jakub@redhat.com>
3021 * gimple-lower-bitint.cc (itint_large_huge::lower_addsub_overflow): Fix
3022 computation of idx for i == 4 of bitint_prec_huge.
3024 2024-02-10 Jakub Jelinek <jakub@redhat.com>
3026 PR middle-end/110754
3027 * gimple-low.cc (assumption_copy_decl): For TREE_THIS_VOLATILE
3028 decls create PARM_DECL with pointer to original type, set
3029 TREE_READONLY and keep TREE_THIS_VOLATILE, TREE_ADDRESSABLE,
3030 DECL_NOT_GIMPLE_REG_P and DECL_BY_REFERENCE cleared.
3031 (adjust_assumption_stmt_op): For remapped TREE_THIS_VOLATILE decls
3032 wrap PARM_DECL into a simple TREE_THIS_NO_TRAP MEM_REF.
3033 (lower_assumption): For TREE_THIS_VOLATILE vars pass ADDR_EXPR
3034 of the var as argument.
3036 2024-02-10 Jakub Jelinek <jakub@redhat.com>
3038 * pretty-print.cc (pp_integer_with_precision): Handle precision 3 for
3039 size_t and precision 4 for ptrdiff_t. Formatting fix.
3040 (pp_format): Document %{t,z}{d,i,u,o,x}. Implement t and z modifiers.
3041 Formatting fixes.
3042 (test_pp_format): Test t and z modifiers.
3043 * gcc.cc (read_specs): Use %td instead of %ld and casts to long.
3045 2024-02-10 Jakub Jelinek <jakub@redhat.com>
3047 * ipa-icf.cc (sem_item_optimizer::process_cong_reduction,
3048 sem_item_optimizer::dump_cong_classes): Use HOST_SIZE_T_PRINT_UNSIGNED
3049 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
3050 * tree.cc (print_debug_expr_statistics): Use HOST_SIZE_T_PRINT_DEC
3051 and casts to fmt_size_t instead of "%ld" and casts to long.
3052 (print_value_expr_statistics, print_type_hash_statistics): Likewise.
3053 * dwarf2out.cc (output_macinfo_op): Use HOST_WIDE_INT_PRINT_UNSIGNED
3054 instead of "%lu" and casts to unsigned long.
3055 * gcov-dump.cc (dump_gcov_file): Use %u instead of %lu and casts to
3056 unsigned long.
3057 * tree-ssa-dom.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
3058 and casts to fmt_size_t instead of "%ld" and casts to long.
3059 * cfgexpand.cc (dump_stack_var_partition): Use
3060 HOST_SIZE_T_PRINT_UNSIGNED and casts to fmt_size_t instead of "%lu"
3061 and casts to unsigned long.
3062 * gengtype.cc (adjust_field_rtx_def): Likewise.
3063 * tree-into-ssa.cc (htab_statistics): Use HOST_SIZE_T_PRINT_DEC
3064 and casts to fmt_size_t instead of "%ld" and casts to long.
3065 * postreload-gcse.cc (dump_hash_table): Likewise.
3066 * ggc-page.cc (alloc_page): Use HOST_SIZE_T_PRINT_UNSIGNED
3067 and casts to fmt_size_t instead of "%lu" and casts to unsigned long.
3068 (ggc_internal_alloc, ggc_free): Likewise.
3069 * genpreds.cc (write_lookup_constraint_1): Likewise.
3070 (write_insn_constraint_len): Likewise.
3071 * tree-dfa.cc (dump_dfa_stats): Use HOST_SIZE_T_PRINT_DEC
3072 and casts to fmt_size_t instead of "%ld" and casts to long.
3073 * varasm.cc (output_constant_pool_contents): Use
3074 HOST_WIDE_INT_PRINT_DEC instead of "%ld" and casts to long.
3075 * var-tracking.cc (dump_var): Likewise.
3077 2024-02-09 Jakub Jelinek <jakub@redhat.com>
3079 PR tree-optimization/113783
3080 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Look
3081 through VIEW_CONVERT_EXPR for final cast checks. Handle
3082 VIEW_CONVERT_EXPRs from large/huge _BitInt to > MAX_FIXED_MODE_SIZE
3083 INTEGER_TYPEs.
3084 (gimple_lower_bitint): Don't merge mergeable operations or other
3085 casts with VIEW_CONVERT_EXPRs to > MAX_FIXED_MODE_SIZE INTEGER_TYPEs.
3086 * expr.cc (expand_expr_real_1): Don't use convert_modes if either
3087 mode is BLKmode.
3089 2024-02-09 Jakub Jelinek <jakub@redhat.com>
3091 * hwint.h (GCC_PRISZ, fmt_size_t, HOST_SIZE_T_PRINT_DEC,
3092 HOST_SIZE_T_PRINT_UNSIGNED, HOST_SIZE_T_PRINT_HEX,
3093 HOST_SIZE_T_PRINT_HEX_PURE): Define.
3094 * ira-conflicts.cc (build_conflict_bit_table): Use it. Formatting
3095 fixes.
3097 2024-02-09 Jakub Jelinek <jakub@redhat.com>
3099 PR middle-end/113415
3100 * cfgexpand.cc (expand_asm_stmt): For asm goto, use
3101 duplicate_insn_chain to duplicate after_rtl_seq sequence instead
3102 of hand written loop with emit_insn of copy_insn and emit original
3103 after_rtl_seq on the last edge.
3105 2024-02-09 Jakub Jelinek <jakub@redhat.com>
3107 PR tree-optimization/113818
3108 * gimple-lower-bitint.cc (add_eh_edge): New function.
3109 (bitint_large_huge::handle_load,
3110 bitint_large_huge::lower_mergeable_stmt,
3111 bitint_large_huge::lower_muldiv_stmt): Use it.
3113 2024-02-09 Jakub Jelinek <jakub@redhat.com>
3115 PR tree-optimization/113774
3116 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast): Don't
3117 emit any comparison if m_first and low + 1 is equal to
3118 m_upwards_2limb, simplify condition for that. If not
3119 single_comparison, not m_first and we can prove that the idx <= low
3120 comparison will be always true, emit instead of idx <= low
3121 comparison low <= low such that cfg cleanup will optimize it at
3122 the end of the pass.
3124 2024-02-08 Aldy Hernandez <aldyh@redhat.com>
3126 PR tree-optimization/113735
3127 * value-relation.cc (equiv_oracle::add_equiv_to_block): Call
3128 limit_check().
3130 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
3132 * config/avr/gen-avr-mmcu-specs.cc (struct McuInfo): New.
3133 (main, print_mcu, diagnose_mrodata_in_ram): Pass it down.
3135 2024-02-08 H.J. Lu <hjl.tools@gmail.com>
3137 PR target/113711
3138 PR target/113733
3139 * config/i386/constraints.md: List all constraints with j prefix.
3140 (j>): Change auto-dec to auto-inc in documentation.
3141 (je): Changed to a memory constraint with APX NDD TLS operand
3142 check.
3143 (jM): New memory constraint for APX NDD instructions.
3144 (jO): Likewise.
3145 * config/i386/i386-protos.h (x86_poff_operand_p): Removed.
3146 * config/i386/i386.cc (x86_poff_operand_p): Likewise.
3147 * config/i386/i386.md (*add<dwi>3_doubleword): Use rjO.
3148 (*add<mode>_1[SWI48]): Use je and jM.
3149 (addsi_1_zext): Use jM.
3150 (*addv<dwi>4_doubleword_1[DWI]): Likewise.
3151 (*sub<mode>_1[SWI]): Use jM.
3152 (@add<mode>3_cc_overflow_1[SWI]): Likewise.
3153 (*add<dwi>3_doubleword_cc_overflow_1): Use rjO.
3154 (*and<dwi>3_doubleword): Likewise.
3155 (*anddi_1): Use jM.
3156 (*andsi_1_zext): Likewise.
3157 (*and<mode>_1[SWI24]): Likewise.
3158 (*<code><dwi>3_doubleword[any_or]): Use rjO
3159 (*code<mode>_1[any_or SWI248]): Use jM.
3160 (*<code>si_1_zext[zero_extend + any_or]): Likewise.
3161 * config/i386/predicates.md (apx_ndd_memory_operand): New.
3162 (apx_ndd_add_memory_operand): Likewise.
3164 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
3166 PR target/113824
3167 * config/avr/avr-mcus.def (ata5797): Move from avr5 to avr4.
3168 * doc/avr-mmcu.texi: Rebuild.
3170 2024-02-08 Tamar Christina <tamar.christina@arm.com>
3172 PR tree-optimization/113808
3173 * tree-vect-loop.cc (vectorizable_live_operation): Don't cache the
3174 value cross iterations.
3176 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
3178 * config/avr/gen-avr-mmcu-specs.cc (print_mcu) <*cpp_mcu>: Spec always
3179 defines __AVR_PM_BASE_ADDRESS__ if the core has it.
3181 2024-02-08 Richard Biener <rguenther@suse.de>
3183 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
3184 Revert last change to dr_may_alias_p.
3186 2024-02-08 Georg-Johann Lay <avr@gjlay.de>
3188 * config/avr/gen-avr-mmcu-specs.cc: Rename spec cc1_misc to
3189 cc1_rodata_in_ram. Rename spec link_misc to link_rodata_in_ram.
3190 Remove spec asm_misc.
3191 * config/avr/specs.h: Same.
3193 2024-02-08 Pan Li <pan2.li@intel.com>
3195 PR target/113766
3196 * config/riscv/riscv-vector-builtins-shapes.cc (struct alu_def): Make
3197 sure the c.arg_num is >= 2 before checking.
3198 (struct build_frm_base): Ditto.
3199 (struct narrow_alu_def): Ditto.
3201 2024-02-07 Richard Biener <rguenther@suse.de>
3203 PR tree-optimization/113796
3204 * tree-if-conv.cc (combine_blocks): Wipe range-info before
3205 replacing PHIs and inserting predicates.
3207 2024-02-07 Roger Sayle <roger@nextmovesoftware.com>
3208 Uros Bizjak <ubizjak@gmail.com>
3210 PR target/113690
3211 * config/i386/i386-features.cc (timode_convert_cst): New helper
3212 function to convert a TImode CONST_SCALAR_INT_P to a V1TImode
3213 CONST_VECTOR.
3214 (timode_scalar_chain::convert_op): Use timode_convert_cst.
3215 (timode_scalar_chain::convert_insn): Delete REG_EQUAL notes.
3216 Use timode_convert_cst.
3218 2024-02-07 Victor Do Nascimento <victor.donascimento@arm.com>
3220 * config/aarch64/aarch64-sys-regs.def: Copy from Binutils.
3221 * config/aarch64/aarch64.h (AARCH64_FL_AIE): New.
3222 (AARCH64_FL_DEBUGv8p9): Likewise.
3223 (AARCH64_FL_FGT2): Likewise.Likewise.
3224 (AARCH64_FL_ITE): Likewise.
3225 (AARCH64_FL_PFAR): Likewise.
3226 (AARCH64_FL_PMUv3_ICNTR): Likewise.
3227 (AARCH64_FL_PMUv3_SS): Likewise.
3228 (AARCH64_FL_PMUv3p9): Likewise.
3229 (AARCH64_FL_RASv2): Likewise.
3230 (AARCH64_FL_S1PIE): Likewise.
3231 (AARCH64_FL_S1POE): Likewise.
3232 (AARCH64_FL_S2PIE): Likewise.
3233 (AARCH64_FL_S2POE): Likewise.
3234 (AARCH64_FL_SCTLR2): Likewise.
3235 (AARCH64_FL_SEBEP): Likewise.
3236 (AARCH64_FL_SPE_FDS): Likewise.
3237 (AARCH64_FL_TCR2): Likewise.
3239 2024-02-07 Richard Biener <rguenther@suse.de>
3241 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences):
3242 Only check whether reads are in-bound in places that are not safe.
3243 Fix dependence check. Add missing newline. Clarify comments.
3245 2024-02-07 Tamar Christina <tamar.christina@arm.com>
3247 PR tree-optimization/113750
3248 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Check
3249 for single predecessor when doing early break vect.
3250 * tree-vect-loop.cc (move_early_exit_stmts): Get gsi at the start but
3251 after labels.
3253 2024-02-07 Tamar Christina <tamar.christina@arm.com>
3255 PR tree-optimization/113731
3256 * gimple-iterator.cc (gsi_move_before): Take new parameter for update
3257 method.
3258 * gimple-iterator.h (gsi_move_before): Default new param to
3259 GSI_SAME_STMT.
3260 * tree-vect-loop.cc (move_early_exit_stmts): Call gsi_move_before with
3261 GSI_NEW_STMT.
3263 2024-02-07 Jakub Jelinek <jakub@redhat.com>
3265 PR tree-optimization/113756
3266 * range-op.cc (update_known_bitmask): For GIMPLE_UNARY_RHS,
3267 use TYPE_SIGN (lh.type ()) instead of sign for widest_int::from
3268 of lh_bits value and mask.
3270 2024-02-07 Jakub Jelinek <jakub@redhat.com>
3272 PR tree-optimization/113753
3273 * wide-int.cc (wi::mul_internal): Unpack op1val and op2val with
3274 UNSIGNED rather than SIGNED. If high or needs_overflow and prec is
3275 not a multiple of HOST_BITS_PER_WIDE_INT, shift left bits above prec
3276 so that they start with r[half_blocks_needed] lowest bit. Fix up
3277 computation of top mask for SIGNED.
3279 2024-02-07 Pan Li <pan2.li@intel.com>
3281 PR target/113766
3282 * config/riscv/riscv-protos.h (resolve_overloaded_builtin): Adjust
3283 the signature of func.
3284 * config/riscv/riscv-c.cc (riscv_resolve_overloaded_builtin): Ditto.
3285 * config/riscv/riscv-vector-builtins.cc (resolve_overloaded_builtin): Make
3286 overloaded func with empty args error.
3288 2024-02-06 H.J. Lu <hjl.tools@gmail.com>
3290 PR target/113689
3291 * config/i386/i386.cc (x86_64_select_profile_regnum): Return
3292 R10_REG after sorry.
3294 2024-02-06 Andrew Carlotti <andrew.carlotti@arm.com>
3296 * config/aarch64/aarch64.cc (aarch64_mangle_decl_assembler_name):
3297 Move before new caller, and add ".default" suffix.
3298 (get_suffixed_assembler_name): New.
3299 (make_resolver_func): Use get_suffixed_assembler_name.
3300 (aarch64_generate_version_dispatcher_body): Redo name mangling.
3302 2024-02-06 Jakub Jelinek <jakub@redhat.com>
3304 PR target/113763
3305 * config/aarch64/aarch64.cc (aarch64_output_sme_zero_za): Change tiles
3306 element from std::pair<unsigned int, char> to an unnamed struct.
3307 Adjust uses of tile range variable.
3309 2024-02-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3311 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::emit_vsetvl): Fix inifinite compilation.
3312 (pre_vsetvl::remove_vsetvl_pre_insns): Ditto.
3314 2024-02-06 Jakub Jelinek <jakub@redhat.com>
3316 PR sanitizer/110676
3317 * gimple-fold.cc (gimple_fold_builtin_strlen): For -fsanitize=address
3318 reset maxlen to sizetype maximum.
3320 2024-02-06 Jakub Jelinek <jakub@redhat.com>
3322 PR tree-optimization/113736
3323 * gimple-lower-bitint.cc (bitint_large_huge::limb_access): Use
3324 var's address space for MEM_REF or VIEW_CONVERT_EXPRs.
3326 2024-02-06 Jakub Jelinek <jakub@redhat.com>
3328 PR tree-optimization/113759
3329 * tree-ssa-math-opts.cc (convert_mult_to_widen): If actual_precision
3330 or from_unsignedN differs from properties of typeN, update typeN
3331 to build_nonstandard_integer_type. If TREE_TYPE (rhsN) is not
3332 uselessly convertible to typeN, convert it using fold_convert or
3333 build_and_insert_cast depending on if rhsN is INTEGER_CST or not.
3334 (convert_plusminus_to_widen): Likewise.
3336 2024-02-06 Tejas Belagod <tejas.belagod@arm.com>
3338 PR target/112577
3339 * config/aarch64/aarch64.cc (aarch64_class_max_nregs): Handle 64-bit
3340 vector structure modes correctly.
3342 2024-02-05 Christoph Müllner <christoph.muellner@vrull.eu>
3344 * config/riscv/thead.cc (th_print_operand_address): Fix compiler
3345 warning.
3347 2024-02-05 H.J. Lu <hjl.tools@gmail.com>
3349 PR target/113689
3350 * config/i386/i386.cc (x86_64_select_profile_regnum): New.
3351 (x86_function_profiler): Call x86_64_select_profile_regnum to
3352 get a scratch register for large model profiling.
3354 2024-02-05 Richard Ball <richard.ball@arm.com>
3356 * config/arm/arm.cc (arm_output_mi_thunk): Emit
3357 insn for bti_c when bti is enabled.
3359 2024-02-05 Xi Ruoyao <xry111@xry111.site>
3361 * config/mips/mips-msa.md (neg<mode:MSA>2): Add missing mode for
3362 neg.
3364 2024-02-05 Xi Ruoyao <xry111@xry111.site>
3366 * config/mips/mips-msa.md (elmsgnbit): New define_mode_attr.
3367 (neg<mode>2): Change the mode iterator from MSA to IMSA because
3368 in FP arithmetic we cannot use (0 - x) for -x.
3369 (neg<mode>2): New define_insn to implement FP vector negation,
3370 using a bnegi instruction to negate the sign bit.
3372 2024-02-05 Richard Biener <rguenther@suse.de>
3374 PR tree-optimization/113707
3375 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): After
3376 checking the avail set treat out-of-region defines as
3377 available.
3379 2024-02-05 Richard Biener <rguenther@suse.de>
3381 * tree-vect-data-refs.cc (vect_create_data_ref_ptr): Use
3382 the default mode when building a pointer.
3384 2024-02-05 Jakub Jelinek <jakub@redhat.com>
3386 PR tree-optimization/113737
3387 * gimple-lower-bitint.cc (gimple_lower_bitint): If GIMPLE_SWITCH
3388 has just a single label, remove it and make single successor edge
3389 EDGE_FALLTHRU.
3391 2024-02-05 Jakub Jelinek <jakub@redhat.com>
3393 PR target/113059
3394 * config/i386/i386-features.cc (rest_of_handle_insert_vzeroupper):
3395 Remove REG_DEAD/REG_UNUSED notes at the end of the pass before
3396 df_analyze call.
3398 2024-02-05 Richard Biener <rguenther@suse.de>
3400 PR target/113255
3401 * config/i386/i386-expand.cc
3402 (expand_set_or_cpymem_prologue_epilogue_by_misaligned_moves):
3403 Use a new pseudo for the skipped number of bytes.
3405 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
3407 * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670.
3408 * doc/invoke.texi (RISC-V Options): Add sifive-p450,
3409 sifive-p670.
3411 2024-02-05 Monk Chiang <monk.chiang@sifive.com>
3413 * config/riscv/riscv.md: Include sifive-p400.md.
3414 * config/riscv/sifive-p400.md: New file.
3415 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
3416 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
3417 Add sifive_p400.
3418 * config/riscv/riscv.cc (sifive_p400_tune_info): New.
3419 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
3420 * doc/invoke.texi (RISC-V Options): Add sifive-p400-series
3422 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
3424 * config/xtensa/xtensa.md (*eqne_zero_masked_bits):
3425 Add missing ":SI" to the match_operator.
3427 2024-02-04 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
3429 * config/xtensa/xtensa.md (SHI): New mode iterator.
3430 (2 split patterns related to constsynth):
3431 Change to also accept HImode operands.
3433 2024-02-04 Jeff Law <jlaw@ventanamicro.com>
3435 * config/riscv/riscv.cc (riscv_rtx_costs): Handle SUBREG and REG
3436 similarly.
3438 2024-02-04 Xi Ruoyao <xry111@xry111.site>
3440 * config/loongarch/lsx.md (neg<mode:FLSX>2): Remove the
3441 incorrect expand.
3442 * config/loongarch/simd.md (simdfmt_as_i): New define_mode_attr.
3443 (elmsgnbit): Likewise.
3444 (neg<mode:FVEC>2): New define_insn.
3445 * config/loongarch/lasx.md (negv4df2, negv8sf2): Remove as they
3446 are now instantiated in simd.md.
3448 2024-02-04 Xi Ruoyao <xry111@xry111.site>
3450 * config/loongarch/loongarch.cc (loongarch_symbol_insns): Do not
3451 use LSX_SUPPORTED_MODE_P or LASX_SUPPORTED_MODE_P if mode is
3452 MAX_MACHINE_MODE.
3454 2024-02-04 Li Wei <liwei@loongson.cn>
3456 * config/loongarch/loongarch.cc (loongarch_expand_vselect): Adjust.
3457 (loongarch_expand_vselect_vconcat): Ditto.
3458 (loongarch_try_expand_lsx_vshuf_const): New, use vshuf to implement
3459 all 128-bit constant permutation situations.
3460 (loongarch_expand_lsx_shuffle): Adjust and rename function name.
3461 (loongarch_is_imm_set_shuffle): Renamed function name.
3462 (loongarch_expand_vec_perm_even_odd): Function forward declaration.
3463 (loongarch_expand_vec_perm_even_odd_1): Add implement for 128-bit
3464 extract-even and extract-odd permutations.
3465 (loongarch_is_odd_extraction): Delete.
3466 (loongarch_is_even_extraction): Ditto.
3467 (loongarch_expand_vec_perm_const): Adjust.
3469 2024-02-03 Jakub Jelinek <jakub@redhat.com>
3471 PR middle-end/113722
3472 * wide-int.cc (wi::bswap_large): Rename third argument from
3473 len to xlen and adjust use in safe_uhwi. Add len variable, set
3474 it to BLOCKS_NEEDED (precision) and use it for clearing of val
3475 and as canonize argument. Clear val using memset instead of
3476 a loop.
3478 2024-02-03 Jakub Jelinek <jakub@redhat.com>
3480 * ggc-common.cc (gt_pch_save): Allow addr to be equal to
3481 mmi.preferred_base + mmi.size - sizeof (void *).
3483 2024-02-03 Xi Ruoyao <xry111@xry111.site>
3485 * config/loongarch/loongarch-def.h (abi_minimal_isa): Declare.
3486 * config/loongarch/loongarch-opts.cc (abi_minimal_isa): Remove
3487 the ODR-violating locale declaration.
3489 2024-02-02 Tamar Christina <tamar.christina@arm.com>
3491 PR tree-optimization/113588
3492 PR tree-optimization/113467
3493 * tree-vect-data-refs.cc
3494 (vect_analyze_data_ref_dependence): Choose correct dest and fix checks.
3495 (vect_analyze_early_break_dependences): Update comments.
3497 2024-02-02 John David Anglin <danglin@gcc.gnu.org>
3499 PR target/59778
3500 * config/pa/pa.cc (enum pa_builtins): Add PA_BUILTIN_GET_FPSR
3501 and PA_BUILTIN_SET_FPSR builtins.
3502 * (pa_builtins_icode): Declare.
3503 * (def_builtin, pa_fpu_init_builtins): New.
3504 * (pa_init_builtins): Initialize FPU builtins.
3505 * (pa_builtin_decl, pa_expand_builtin_1): New.
3506 * (pa_expand_builtin): Handle PA_BUILTIN_GET_FPSR and
3507 PA_BUILTIN_SET_FPSR builtins.
3508 * (pa_atomic_assign_expand_fenv): New.
3509 * config/pa/pa.md (UNSPECV_GET_FPSR, UNSPECV_SET_FPSR): New
3510 UNSPECV constants.
3511 (get_fpsr, put_fpsr): New expanders.
3512 (get_fpsr_32, get_fpsr_64, set_fpsr_32, set_fpsr_64): New
3513 insn patterns.
3515 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3517 PR target/113697
3518 * config/riscv/riscv-v.cc (expand_reduction): Pass VLMAX avl to scalar move.
3520 2024-02-02 Jonathan Wakely <jwakely@redhat.com>
3522 * doc/extend.texi (Common Type Attributes): Fix typo in
3523 description of hardbool.
3525 2024-02-02 Jakub Jelinek <jakub@redhat.com>
3527 PR tree-optimization/113692
3528 * gimple-lower-bitint.cc (bitint_large_huge::lower_stmt): Handle casts
3529 from large/huge BITINT_TYPEs to POINTER_TYPE/REFERENCE_TYPE as
3530 final_cast_p.
3532 2024-02-02 Jakub Jelinek <jakub@redhat.com>
3534 PR middle-end/113699
3535 * gimple-lower-bitint.cc (bitint_large_huge::lower_asm): Handle
3536 uninitialized large/huge _BitInt SSA_NAME inputs.
3538 2024-02-02 Jakub Jelinek <jakub@redhat.com>
3540 PR middle-end/113705
3541 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use wide_int_from
3542 around wi::to_wide in order to compare value in prec precision.
3544 2024-02-02 Lehua Ding <lehua.ding@rivai.ai>
3546 Revert:
3547 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3549 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
3551 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3553 * config/riscv/riscv.cc (riscv_legitimize_move): Fix poly_int dest generation.
3555 2024-02-02 Pan Li <pan2.li@intel.com>
3557 * config/riscv/riscv.cc (riscv_get_arg_info): Cleanup comments.
3558 (riscv_pass_by_reference): Ditto.
3559 (riscv_fntype_abi): Ditto.
3561 2024-02-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3563 * config/riscv/riscv-vsetvl.cc (vsetvl_pre_insn_p): New function.
3564 (pre_vsetvl::cleaup): Remove vsetvl_pre.
3565 (pre_vsetvl::remove_vsetvl_pre_insns): New function.
3567 2024-02-02 Jiahao Xu <xujiahao@loongson.cn>
3569 * config/loongarch/larchintrin.h
3570 (__frecipe_s): Update function return type.
3571 (__frecipe_d): Ditto.
3572 (__frsqrte_s): Ditto.
3573 (__frsqrte_d): Ditto.
3575 2024-02-02 Li Wei <liwei@loongson.cn>
3577 * config/loongarch/loongarch.cc (loongarch_multiply_add_p): New.
3578 (loongarch_vector_costs::add_stmt_cost): Adjust.
3580 2024-02-02 Xi Ruoyao <xry111@xry111.site>
3582 * config/loongarch/loongarch.md (unspec): Add
3583 UNSPEC_LA_PCREL_64_PART1 and UNSPEC_LA_PCREL_64_PART2.
3584 (la_pcrel64_two_parts): New define_insn.
3585 * config/loongarch/loongarch.cc (loongarch_tls_symbol): Fix a
3586 typo in the comment.
3587 (loongarch_call_tls_get_addr): If -mcmodel=extreme
3588 -mexplicit-relocs={always,auto}, use la_pcrel64_two_parts for
3589 addressing the TLS symbol and __tls_get_addr. Emit an REG_EQUAL
3590 note to allow CSE addressing __tls_get_addr.
3591 (loongarch_legitimize_tls_address): If -mcmodel=extreme
3592 -mexplicit-relocs={always,auto}, address TLS IE symbols with
3593 la_pcrel64_two_parts.
3594 (loongarch_split_symbol): If -mcmodel=extreme
3595 -mexplicit-relocs={always,auto}, address symbols with
3596 la_pcrel64_two_parts.
3597 (loongarch_output_mi_thunk): Clean up unreachable code. If
3598 -mcmodel=extreme -mexplicit-relocs={always,auto}, address the MI
3599 thunks with la_pcrel64_two_parts.
3601 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3603 * config/loongarch/loongarch.cc (loongarch_call_tls_get_addr):
3604 Add support for call36.
3606 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3608 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
3609 When the code model of the symbol is extreme and -mexplicit-relocs=auto,
3610 the macro instruction loading symbol address is not applicable.
3611 (loongarch_call_tls_get_addr): Adjust code.
3612 (loongarch_legitimize_tls_address): Likewise.
3614 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3616 * config/loongarch/loongarch-protos.h (loongarch_symbol_extreme_p):
3617 Add function declaration.
3618 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
3619 For SYMBOL_PCREL64, non-zero addend of "la.local $rd,$rt,sym+addend"
3620 is not allowed
3621 (loongarch_load_tls): Added macro support in extreme mode.
3622 (loongarch_call_tls_get_addr): Likewise.
3623 (loongarch_legitimize_tls_address): Likewise.
3624 (loongarch_force_address): Likewise.
3625 (loongarch_legitimize_move): Likewise.
3626 (loongarch_output_mi_thunk): Likewise.
3627 (loongarch_option_override_internal): Remove the code that detects
3628 explicit relocs status.
3629 (loongarch_handle_model_attribute): Likewise.
3630 * config/loongarch/loongarch.md (movdi_symbolic_off64): New template.
3631 * config/loongarch/predicates.md (symbolic_off64_operand): New predicate.
3632 (symbolic_off64_or_reg_operand): Likewise.
3634 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3636 * config/loongarch/loongarch.cc (loongarch_load_tls):
3637 Load all types of tls symbols through one function.
3638 (loongarch_got_load_tls_gd): Delete.
3639 (loongarch_got_load_tls_ld): Delete.
3640 (loongarch_got_load_tls_ie): Delete.
3641 (loongarch_got_load_tls_le): Delete.
3642 (loongarch_call_tls_get_addr): Modify the called function name.
3643 (loongarch_legitimize_tls_address): Likewise.
3644 * config/loongarch/loongarch.md (@got_load_tls_gd<mode>): Delete.
3645 (@load_tls<mode>): New template.
3646 (@got_load_tls_ld<mode>): Delete.
3647 (@got_load_tls_le<mode>): Delete.
3648 (@got_load_tls_ie<mode>): Delete.
3650 2024-02-02 Lulu Cheng <chenglulu@loongson.cn>
3652 * config/loongarch/loongarch.cc (mem_shadd_or_shadd_rtx_p): New function.
3653 (loongarch_legitimize_address): Add logical transformation code.
3655 2024-02-01 Marek Polacek <polacek@redhat.com>
3657 * doc/invoke.texi: Update -Wdangling-reference documentation.
3659 2024-02-01 Uros Bizjak <ubizjak@gmail.com>
3661 PR target/113701
3662 * config/i386/i386.md (*cmp<dwi>_doubleword):
3663 Do not force SUBREG pieces to pseudos.
3665 2024-02-01 John David Anglin <danglin@gcc.gnu.org>
3667 * config/pa/pa.md (atomic_storedi_1): Fix bug in
3668 alternative 1.
3670 2024-02-01 Georg-Johann Lay <avr@gjlay.de>
3672 * config/avr/avr.cc: Tabify.
3674 2024-02-01 Richard Ball <richard.ball@arm.com>
3676 PR tree-optimization/111268
3677 * tree-vect-slp.cc (vectorizable_slp_permutation_1):
3678 Add variable-length check for vector input arguments
3679 to a function.
3681 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
3683 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Don't
3684 hard-code number of SGPR/VGPR/AVGPR registers.
3685 * config/gcn/gcn.h: Add a 'STATIC_ASSERT's for number of
3686 SGPR/VGPR/AVGPR registers.
3688 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
3690 * config/riscv/riscv.md: Add "fcvt_i2f", "fcvt_f2i" type
3691 attribute, and include sifive-p600.md.
3692 * config/riscv/generic-ooo.md: Update type attribute.
3693 * config/riscv/generic.md: Update type attribute.
3694 * config/riscv/sifive-7.md: Update type attribute.
3695 * config/riscv/sifive-p600.md: New file.
3696 * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter.
3697 * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type):
3698 Add sifive_p600.
3699 * config/riscv/riscv.cc (sifive_p600_tune_info): New.
3700 * config/riscv/riscv.h (TARGET_SFB_ALU): Update.
3701 * doc/invoke.texi (RISC-V Options): Add sifive-p600-series
3703 2024-02-01 Monk Chiang <monk.chiang@sifive.com>
3705 * common/config/riscv/riscv-common.cc: Add Za64rs, Za128rs,
3706 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b items.
3707 * config/riscv/riscv.opt: New macro for 7 new unprivileged
3708 extensions.
3709 * doc/invoke.texi (RISC-V Options): Add Za64rs, Za128rs,
3710 Ziccif, Ziccrse, Ziccamoa, Zicclsm, Zic64b extensions.
3712 2024-02-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
3714 * config/sol2.h (LIBASAN_EARLY_SPEC): Add -z now unless
3715 -static-libasan. Add missing whitespace.
3717 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
3719 * config/gcn/gcn.md (FIRST_SGPR_REG, LAST_SGPR_REG)
3720 (FIRST_VGPR_REG, LAST_VGPR_REG, FIRST_AVGPR_REG, LAST_AVGPR_REG):
3721 Don't 'define_constants'.
3723 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
3725 * config/gcn/gcn.h (SGPR_OR_VGPR_REGNO_P): Remove.
3727 2024-02-01 Thomas Schwinge <tschwinge@baylibre.com>
3729 * config/gcn/gcn.md (sync_compare_and_swap<mode>_lds_insn)
3730 [TARGET_RDNA3]: Adjust.
3732 2024-02-01 Richard Biener <rguenther@suse.de>
3734 PR tree-optimization/113693
3735 * tree-ssa-sccvn.cc (rpo_elim::eliminate_avail): Honor avail
3736 data when available.
3738 2024-02-01 Jakub Jelinek <jakub@redhat.com>
3739 Jason Merrill <jason@redhat.com>
3741 PR c++/113531
3742 * gimple-low.cc (lower_stmt): Remove .ASAN_MARK calls
3743 on variables which were promoted to TREE_STATIC.
3745 2024-02-01 Roger Sayle <roger@nextmovesoftware.com>
3746 Richard Biener <rguenther@suse.de>
3748 PR target/113560
3749 * tree-ssa-math-opts.cc (is_widening_mult_rhs_p): Use range
3750 information via tree_non_zero_bits to check if this operand
3751 is suitably extended for a widening (or highpart) multiplication.
3752 (convert_mult_to_widen): Insert explicit casts if the RHS or LHS
3753 isn't already of the claimed type.
3755 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3757 Revert:
3758 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3760 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
3761 (generic_ooo_branch): ditto
3762 * config/riscv/generic.md (generic_sfb_alu): ditto
3763 (generic_fmul_half): ditto
3764 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
3765 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
3766 (sifive_7_popcount): ditto
3767 * config/riscv/vector.md: change rdfrm to fmove
3768 * config/riscv/zc.md: change pushpop to load/store
3770 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3772 Revert:
3773 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3774 Robin Dapp <rdapp.gcc@gmail.com>
3776 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
3777 (generic_ooo_vec_load): ditto
3778 (generic_ooo_vec_store): ditto
3779 (generic_ooo_vec_loadstore_seg): ditto
3780 (generic_ooo_vec_alu): ditto
3781 (generic_ooo_vec_fcmp): ditto
3782 (generic_ooo_vec_imul): ditto
3783 (generic_ooo_vec_fadd): ditto
3784 (generic_ooo_vec_fmul): ditto
3785 (generic_ooo_crypto): ditto
3786 (generic_ooo_perm): ditto
3787 (generic_ooo_vec_reduction): ditto
3788 (generic_ooo_vec_ordered_reduction): ditto
3789 (generic_ooo_vec_idiv): ditto
3790 (generic_ooo_vec_float_divsqrt): ditto
3791 (generic_ooo_vec_mask): ditto
3792 (generic_ooo_vec_vesetvl): ditto
3793 (generic_ooo_vec_setrm): ditto
3794 (generic_ooo_vec_readlen): ditto
3795 * config/riscv/riscv.md: include generic-vector-ooo
3796 * config/riscv/generic-vector-ooo.md: New file. to here
3798 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3800 Revert:
3801 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3803 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
3805 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3807 * config/riscv/riscv.cc (riscv_sched_variable_issue): enable assert
3809 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3810 Robin Dapp <rdapp.gcc@gmail.com>
3812 * config/riscv/generic-ooo.md (generic_ooo): Move reservation
3813 (generic_ooo_vec_load): ditto
3814 (generic_ooo_vec_store): ditto
3815 (generic_ooo_vec_loadstore_seg): ditto
3816 (generic_ooo_vec_alu): ditto
3817 (generic_ooo_vec_fcmp): ditto
3818 (generic_ooo_vec_imul): ditto
3819 (generic_ooo_vec_fadd): ditto
3820 (generic_ooo_vec_fmul): ditto
3821 (generic_ooo_crypto): ditto
3822 (generic_ooo_perm): ditto
3823 (generic_ooo_vec_reduction): ditto
3824 (generic_ooo_vec_ordered_reduction): ditto
3825 (generic_ooo_vec_idiv): ditto
3826 (generic_ooo_vec_float_divsqrt): ditto
3827 (generic_ooo_vec_mask): ditto
3828 (generic_ooo_vec_vesetvl): ditto
3829 (generic_ooo_vec_setrm): ditto
3830 (generic_ooo_vec_readlen): ditto
3831 * config/riscv/riscv.md: include generic-vector-ooo
3832 * config/riscv/generic-vector-ooo.md: New file. to here
3834 2024-02-01 Edwin Lu <ewlu@rivosinc.com>
3836 * config/riscv/generic-ooo.md (generic_ooo_sfb_alu): Add reservation
3837 (generic_ooo_branch): ditto
3838 * config/riscv/generic.md (generic_sfb_alu): ditto
3839 (generic_fmul_half): ditto
3840 * config/riscv/riscv.md: Remove cbo, pushpop, and rdfrm types
3841 * config/riscv/sifive-7.md (sifive_7_hfma):Add reservation
3842 (sifive_7_popcount): ditto
3843 * config/riscv/vector.md: change rdfrm to fmove
3844 * config/riscv/zc.md: change pushpop to load/store
3846 2024-02-01 Andrew Pinski <quic_apinski@quicinc.com>
3848 PR target/113657
3849 * config/aarch64/aarch64-simd.md (split for movv8di):
3850 For strict aligned mode, use DImode instead of TImode.
3852 2024-01-31 Robin Dapp <rdapp@ventanamicro.com>
3854 PR middle-end/113607
3855 * match.pd: Make sure else values match when folding a
3856 vec_cond into a conditional operation.
3858 2024-01-31 Marek Polacek <polacek@redhat.com>
3860 * doc/invoke.texi: Mention that -fconcepts-ts was deprecated in GCC 14.
3862 2024-01-31 Tamar Christina <tamar.christina@arm.com>
3863 Matthew Malcomson <matthew.malcomson@arm.com>
3865 PR sanitizer/112644
3866 * asan.h (asan_intercepted_p): Incercept memset, memmove, memcpy and
3867 memcmp.
3868 * builtins.cc (expand_builtin): Include HWASAN when checking for
3869 builtin inlining.
3871 2024-01-31 Richard Biener <rguenther@suse.de>
3873 PR middle-end/110176
3874 * match.pd (zext (bool) <= (int) 4294967295u): Make sure
3875 to match INTEGER_CST only without outstanding conversion.
3877 2024-01-31 Alex Coplan <alex.coplan@arm.com>
3879 PR target/111677
3880 * config/aarch64/aarch64.cc (aarch64_reg_save_mode): Use
3881 V16QImode for the full 16-byte FPR saves in the vector PCS case.
3883 2024-01-31 Richard Biener <rguenther@suse.de>
3885 PR tree-optimization/111444
3886 * tree-ssa-sccvn.cc (vn_reference_lookup_3): Do not use
3887 vn_reference_lookup_2 when optimistically skipping may-defs.
3889 2024-01-31 Richard Biener <rguenther@suse.de>
3891 PR tree-optimization/113630
3892 * tree-ssa-pre.cc (compute_avail): Avoid registering a
3893 reference with a representation with not matching base
3894 access size.
3896 2024-01-31 Jakub Jelinek <jakub@redhat.com>
3898 PR rtl-optimization/113656
3899 * simplify-rtx.cc (simplify_context::simplify_unary_operation_1)
3900 <case FLOAT_TRUNCATE>: Fix up last argument to simplify_gen_unary.
3902 2024-01-31 Jakub Jelinek <jakub@redhat.com>
3904 PR debug/113637
3905 * dwarf2out.cc (loc_list_from_tree_1): Assume integral types
3906 with BLKmode are larger than DWARF2_ADDR_SIZE.
3908 2024-01-31 Jakub Jelinek <jakub@redhat.com>
3910 PR tree-optimization/113639
3911 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
3912 For VIEW_CONVERT_EXPR set rhs1 to its operand.
3914 2024-01-31 Richard Biener <rguenther@suse.de>
3916 PR tree-optimization/113670
3917 * tree-vect-data-refs.cc (vect_check_gather_scatter):
3918 Make sure we can take the address of the reference base.
3920 2024-01-31 Georg-Johann Lay <avr@gjlay.de>
3922 * config/avr/avr-mcus.def: Add AVR64DU28, AVR64DU32, ATA5787,
3923 ATA5835, ATtiny64AUTO, ATA5700M322.
3924 * doc/avr-mmcu.texi: Rebuild.
3926 2024-01-31 Alexandre Oliva <oliva@adacore.com>
3928 PR debug/113394
3929 * ipa-strub.cc (build_ref_type_for): Drop nonaliased. Adjust
3930 caller.
3932 2024-01-31 Alexandre Oliva <oliva@adacore.com>
3934 PR middle-end/112917
3935 PR middle-end/113100
3936 * builtins.cc (expand_builtin_stack_address): Use
3937 STACK_ADDRESS_OFFSET.
3938 * doc/extend.texi (__builtin_stack_address): Adjust.
3939 * config/sparc/sparc.h (STACK_ADDRESS_OFFSET): Define.
3940 * doc/tm.texi.in (STACK_ADDRESS_OFFSET): Document.
3941 * doc/tm.texi: Rebuilt.
3943 2024-01-31 Juzhe-Zhong <juzhe.zhong@rivai.ai>
3945 PR target/113495
3946 * config/riscv/riscv-vsetvl.cc (extract_single_source): Remove.
3947 (pre_vsetvl::compute_vsetvl_def_data): Fix compile time issue.
3948 (pre_vsetvl::compute_transparent): New function.
3949 (pre_vsetvl::compute_lcm_local_properties): Fix compile time time issue.
3951 2024-01-30 Fangrui Song <maskray@google.com>
3953 PR target/105576
3954 * config/i386/constraints.md: Define constraint "Ws".
3955 * doc/md.texi: Document it.
3957 2024-01-30 Marek Polacek <polacek@redhat.com>
3959 PR c++/110358
3960 PR c++/109640
3961 * doc/invoke.texi: Update -Wdangling-reference description.
3963 2024-01-30 Takayuki 'January June' Suwa <jjsuwa_sys3175@yahoo.co.jp>
3965 * config/xtensa/constraints.md (R, T, U):
3966 Change define_constraint to define_memory_constraint.
3967 * config/xtensa/predicates.md (move_operand): Don't check that a
3968 constant pool operand size is a multiple of UNITS_PER_WORD.
3969 * config/xtensa/xtensa.cc
3970 (xtensa_lra_p, TARGET_LRA_P): Remove.
3971 (xtensa_emit_move_sequence): Remove "if (reload_in_progress)"
3972 clause as it can no longer be true.
3973 (fixup_subreg_mem): Drop function.
3974 (xtensa_output_integer_literal_parts): Consider 16-bit wide
3975 constants.
3976 (xtensa_legitimate_constant_p): Add short-circuit path for
3977 integer load instructions. Don't check that mode size is
3978 at least UNITS_PER_WORD.
3979 * config/xtensa/xtensa.md (movsf): Use can_create_pseudo_p()
3980 rather reload_in_progress and reload_completed.
3981 (doloop_end): Drop operand 2.
3982 (movhi_internal): Add alternative loading constant from a
3983 literal pool.
3984 (define_split for DI register_operand): Don't limit to
3985 !TARGET_AUTO_LITPOOLS.
3986 * config/xtensa/xtensa.opt (mlra): Change to no effect.
3988 2024-01-30 Pan Li <pan2.li@intel.com>
3990 * config/riscv/riscv.cc (riscv_v_vls_mode_aggregate_gpr_count): New function to
3991 calculate the gpr count required by vls mode.
3992 (riscv_v_vls_to_gpr_mode): New function convert vls mode to gpr mode.
3993 (riscv_pass_vls_aggregate_in_gpr): New function to return the rtx of gpr
3994 for vls mode.
3995 (riscv_get_arg_info): Add vls mode handling.
3996 (riscv_pass_by_reference): Return false if arg info has no zero gpr count.
3998 2024-01-30 Richard Biener <rguenther@suse.de>
4000 PR tree-optimization/113659
4001 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4002 Handle main exit without virtual use.
4004 2024-01-30 Christoph Müllner <christoph.muellner@vrull.eu>
4006 * config/riscv/riscv.md: Move UNSPEC_XTHEADFMV* to unspec enum.
4008 2024-01-30 Iain Sandoe <iain@sandoe.co.uk>
4010 PR libgcc/113403
4011 * config/darwin.h (DARWIN_SHARED_WEAK_ADDS, DARWIN_WEAK_CRTS): New.
4012 (REAL_LIBGCC_SPEC): Move weak CRT handling to separate spec.
4013 * config/i386/darwin.h (DARWIN_HEAP_T_LIB): New.
4014 * config/i386/darwin32-biarch.h (DARWIN_HEAP_T_LIB): New.
4015 * config/i386/darwin64-biarch.h (DARWIN_HEAP_T_LIB): New.
4016 * config/rs6000/darwin.h (DARWIN_HEAP_T_LIB): New.
4018 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
4020 PR target/113623
4021 * config/aarch64/aarch64-early-ra.cc (early_ra::preprocess_insns):
4022 Mark all registers that occur in addresses as needing a GPR.
4024 2024-01-30 Richard Sandiford <richard.sandiford@arm.com>
4026 PR target/113636
4027 * config/aarch64/aarch64-early-ra.cc (early_ra::replace_regs): Take
4028 the containing insn as an extra parameter. Reset debug instructions
4029 if they reference a register that is no longer used by real insns.
4030 (early_ra::apply_allocation): Update calls accordingly.
4032 2024-01-30 Jakub Jelinek <jakub@redhat.com>
4034 PR tree-optimization/113603
4035 * tree-ssa-strlen.cc (strlen_pass::handle_store): After
4036 count_nonzero_bytes call refetch si using get_strinfo in case it
4037 has been unshared in the meantime.
4039 2024-01-30 Jakub Jelinek <jakub@redhat.com>
4041 PR middle-end/101195
4042 * except.cc (expand_builtin_eh_return_data_regno): If which doesn't
4043 fit into unsigned HOST_WIDE_INT, return constm1_rtx.
4045 2024-01-30 Jin Ma <jinma@linux.alibaba.com>
4047 * config/riscv/thead.cc (th_print_operand_address): Change %ld
4048 to %lld.
4050 2024-01-29 Manos Anagnostakis <manos.anagnostakis@vrull.eu>
4051 Manolis Tsamis <manolis.tsamis@vrull.eu>
4052 Philipp Tomsich <philipp.tomsich@vrull.eu>
4054 * config/aarch64/aarch64-ldpstp.md: Remove unused mode.
4055 * config/aarch64/aarch64-protos.h (aarch64_operands_ok_for_ldpstp):
4056 Likewise.
4057 * config/aarch64/aarch64.cc (aarch64_operands_ok_for_ldpstp):
4058 Call on framework moved later.
4060 2024-01-29 Jose E. Marchesi <jose.marchesi@oracle.com>
4062 * config/bpf/bpf.cc (bpf_expand_epilogue): Do not emit a return
4063 instruction in naked function epilogues.
4065 2024-01-29 YunQiang Su <syq@gcc.gnu.org>
4067 PR target/113655
4068 * configure.ac: Fix typo gcc_cv_as_mips_explicit should be
4069 gcc_cv_as_mips_explicit_relocs.
4070 * configure: Regnerated.
4072 2024-01-29 Matthieu Longo <matthieu.longo@arm.com>
4074 PR target/108933
4075 * config/arm/arm.md (arm_rev16si2): Convert to define_insn.
4076 Correct generated RTL.
4077 (arm_rev16si2_alt1): Correctly handle conditional execution.
4078 (arm_rev16si2_alt2): Likewise.
4080 2024-01-29 Richard Biener <rguenther@suse.de>
4082 PR middle-end/113622
4083 * expr.cc (expand_assignment): Spill hard registers if
4084 we index them with a variable offset.
4086 2024-01-29 Richard Biener <rguenther@suse.de>
4088 PR middle-end/113622
4089 * gimple-isel.cc (gimple_expand_vec_set_extract_expr):
4090 Also allow DECL_HARD_REGISTER variables.
4092 2024-01-29 Alex Coplan <alex.coplan@arm.com>
4094 PR target/113616
4095 * config/aarch64/aarch64-ldp-fusion.cc (fixup_debug_uses_trailing_add):
4096 Use iterate_safely when iterating over debug uses.
4097 (fixup_debug_uses): Likewise.
4098 (ldp_bb_info::cleanup_tombstones): Use iterate_safely to iterate
4099 over nondebug insns instead of manually maintaining the next insn.
4100 * iterator-utils.h (class safe_iterator): New.
4101 (iterate_safely): New.
4103 2024-01-29 H.J. Lu <hjl.tools@gmail.com>
4105 PR target/38534
4106 * config/i386/i386-options.cc (ix86_set_func_type): Save
4107 callee-saved registers in noreturn functions for -O0/-Og.
4109 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
4111 PR target/113615
4112 * config/gcn/gcn-valu.md (fold_left_plus_<mode>): Only
4113 define for !TARGET_RDNA2_PLUS.
4115 2024-01-29 Richard Sandiford <richard.sandiford@arm.com>
4117 PR target/113281
4118 * tree-vect-patterns.cc (vect_recog_over_widening_pattern): Remove
4119 workaround for right shifts.
4120 (vect_truncatable_operation_p): Handle NEGATE_EXPR and BIT_NOT_EXPR.
4121 (vect_determine_precisions_from_range): Be more selective about
4122 which codes can be narrowed based on their input and output ranges.
4123 For shifts, require at least one more bit of precision than the
4124 maximum shift amount.
4126 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
4128 * config/nvptx/nvptx.opt (march-map=): Add sm_89 and sm_90a.
4130 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
4132 * doc/install.texi (amdgcn): Recommend LLVM 15+ and newlib 4.4+,
4133 but keep requiring only newlib 4.3+ and, if gfx1100 is disabled,
4134 LLVM 13.0.1+.
4136 2024-01-29 Tobias Burnus <tburnus@baylibre.com>
4138 PR other/111966
4139 * config/gcn/mkoffload.cc (SET_XNACK_UNSET, TEST_SRAM_ECC_UNSET): New.
4140 (SET_SRAM_ECC_UNSUPPORTED): Renamed to ...
4141 (SET_SRAM_ECC_UNSET): ... this.
4142 (copy_early_debug_info): Remove gfx900 special case, now handled as
4143 part of the generic handling.
4144 (main): Update SRAM_ECC and XNACK for the -march as done in gcn-hsa.h.
4146 2024-01-29 Jakub Jelinek <jakub@redhat.com>
4148 PR tree-optimization/110603
4149 * tree-ssa-strlen.cc (get_range_strlen_dynamic): Remove incorrect
4150 setting of pdata->maxlen to vr.upper_bound (which is unconditionally
4151 overwritten anyway). Avoid creating invalid range with minlen
4152 larger than maxlen. Formatting fix.
4154 2024-01-29 Richard Biener <rguenther@suse.de>
4156 PR debug/103047
4157 * tree-inline.cc (initialize_inlined_parameters): Reverse
4158 the decl chain of inlined parameters.
4160 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
4162 * config/darwin.cc (darwin_build_constant_cfstring): Prevent over-
4163 alignment of CFString constants by setting DECL_USER_ALIGN.
4165 2024-01-28 Iain Sandoe <iain@sandoe.co.uk>
4166 Jakub Jelinek <jakub@redhat.com>
4168 PR libgcc/113402
4169 * builtins.cc (expand_builtin): Handle BUILT_IN_GCC_NESTED_PTR_CREATED
4170 and BUILT_IN_GCC_NESTED_PTR_DELETED.
4171 * builtins.def (BUILT_IN_GCC_NESTED_PTR_CREATED,
4172 BUILT_IN_GCC_NESTED_PTR_DELETED): Make these builtins LIB-EXT and
4173 rename the library fallbacks to __gcc_nested_func_ptr_created and
4174 __gcc_nested_func_ptr_deleted.
4175 * doc/invoke.texi: Rename these to __gcc_nested_func_ptr_created
4176 and __gcc_nested_func_ptr_deleted.
4177 * tree-nested.cc (finalize_nesting_tree_1): Use builtin_explicit for
4178 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED.
4179 * tree.cc (build_common_builtin_nodes): Build the
4180 BUILT_IN_GCC_NESTED_PTR_CREATED and BUILT_IN_GCC_NESTED_PTR_DELETED local
4181 builtins only for non-explicit.
4183 2024-01-28 YunQiang Su <syq@gcc.gnu.org>
4185 * doc/invoke.texi: Remove duplicate MIPS explicit-relocs option.
4187 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
4189 PR target/38534
4190 * config/i386/i386-options.cc (ix86_set_func_type): Don't
4191 save and restore callee saved registers for a noreturn function
4192 with nothrow or compiled with -fno-exceptions.
4194 2024-01-27 H.J. Lu <hjl.tools@gmail.com>
4196 PR target/103503
4197 PR target/113312
4198 * config/i386/i386-expand.cc (ix86_expand_call): Replace
4199 no_caller_saved_registers check with call_saved_registers check.
4200 Clobber all registers that are not used by the callee with
4201 no_callee_saved_registers attribute.
4202 * config/i386/i386-options.cc (ix86_set_func_type): Set
4203 call_saved_registers to TYPE_NO_CALLEE_SAVED_REGISTERS for
4204 noreturn function. Disallow no_callee_saved_registers with
4205 interrupt or no_caller_saved_registers attributes together.
4206 (ix86_set_current_function): Replace no_caller_saved_registers
4207 check with call_saved_registers check.
4208 (ix86_handle_no_caller_saved_registers_attribute): Renamed to ...
4209 (ix86_handle_call_saved_registers_attribute): This.
4210 (ix86_gnu_attributes): Add
4211 ix86_handle_call_saved_registers_attribute.
4212 * config/i386/i386.cc (ix86_conditional_register_usage): Replace
4213 no_caller_saved_registers check with call_saved_registers check.
4214 (ix86_function_ok_for_sibcall): Don't allow callee with
4215 no_callee_saved_registers attribute when the calling function
4216 has callee-saved registers.
4217 (ix86_comp_type_attributes): Also check
4218 no_callee_saved_registers.
4219 (ix86_epilogue_uses): Replace no_caller_saved_registers check
4220 with call_saved_registers check.
4221 (ix86_hard_regno_scratch_ok): Likewise.
4222 (ix86_save_reg): Replace no_caller_saved_registers check with
4223 call_saved_registers check. Don't save any registers for
4224 TYPE_NO_CALLEE_SAVED_REGISTERS. Save all registers with
4225 TYPE_DEFAULT_CALL_SAVED_REGISTERS if function with
4226 no_callee_saved_registers attribute is called.
4227 (find_drap_reg): Replace no_caller_saved_registers check with
4228 call_saved_registers check.
4229 * config/i386/i386.h (call_saved_registers_type): New enum.
4230 (machine_function): Replace no_caller_saved_registers with
4231 call_saved_registers.
4232 * doc/extend.texi: Document no_callee_saved_registers attribute.
4234 2024-01-27 Jakub Jelinek <jakub@redhat.com>
4236 PR tree-optimization/113614
4237 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't merge
4238 widening casts from signed to unsigned types with TRUNC_DIV_EXPR,
4239 TRUNC_MOD_EXPR or FLOAT_EXPR uses.
4241 2024-01-27 Jakub Jelinek <jakub@redhat.com>
4243 PR tree-optimization/113568
4244 * gimple-lower-bitint.cc (bitint_large_huge::lower_mergeable_stmt):
4245 For VIEW_CONVERT_EXPR use first operand of rhs1 instead of rhs1
4246 in the widening extension checks.
4248 2024-01-27 Jakub Jelinek <jakub@redhat.com>
4250 * gimple-lower-bitint.cc (gimple_lower_bitint): For
4251 TDF_DETAILS dump mapping of SSA_NAMEs to decls.
4253 2024-01-26 Hans-Peter Nilsson <hp@axis.com>
4255 * cgraphunit.cc (process_function_and_variable_attributes): Tweak
4256 the warning for an attribute-always_inline without inline declaration.
4258 2024-01-26 Robin Dapp <rdapp@ventanamicro.com>
4260 PR other/113575
4261 * genopinit.cc (main): Split init_all_optabs into functions
4262 of 1000 patterns each.
4264 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
4266 * config.gcc (amdgcn-*-*): Add gfx1030 and gfx1100 to
4267 TM_MULTILIB_CONFIG.
4268 * doc/install.texi (Configuration amdgcn-*-*): Mention gfx1030/gfx1100.
4269 * doc/invoke.texi (AMD GCN Options): Add gfx1030 and gfx1100 to
4270 -march/-mtune.
4272 2024-01-26 Andrew Stubbs <ams@baylibre.com>
4274 * config/gcn/gcn-opts.h (TARGET_PACKED_WORK_ITEMS): Add TARGET_RDNA3.
4275 * config/gcn/gcn-valu.md (all_convert): New iterator.
4276 (<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): New
4277 define_expand, and rename the old one to ...
4278 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): ... this.
4279 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>2<exec>): Likewise, to ...
4280 (extend<V_INT_1REG_ALT:mode><V_INT_1REG:mode>_sdwa<exec>): .. this.
4281 (*<convop><V_INT_1REG_ALT:mode><V_INT_1REG:mode>_shift<exec>): New.
4282 * config/gcn/gcn.cc (gcn_global_address_p): Use "offsetbits" correctly.
4283 (gcn_hsa_declare_function_name): Update the vgpr counting for gfx1100.
4284 * config/gcn/gcn.md (<u>mulhisi3): Disable on RDNA3.
4285 (<u>mulqihi3_scalar): Likewise.
4287 2024-01-26 Richard Biener <rguenther@suse.de>
4289 PR tree-optimization/113602
4290 * tree-data-ref.cc (dr_analyze_innermost): Fail when
4291 the base object isn't addressable.
4293 2024-01-26 Tobias Burnus <tburnus@baylibre.com>
4295 * config/gcn/gcn-hsa.h (ABI_VERSION_SPEC): New; creates the
4296 "--amdhsa-code-object-version=" argument.
4297 (ASM_SPEC): Use it; replace previous version of it.
4299 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4301 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Refine some codes.
4302 (pre_vsetvl::emit_vsetvl): Ditto.
4304 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
4306 * config/loongarch/lasx.md (vec_extract<mode>_0):
4307 New define_insn_and_split patten.
4309 2024-01-26 Jiahao Xu <xujiahao@loongson.cn>
4311 * config/loongarch/loongarch.h (LOGICAL_OP_NON_SHORT_CIRCUIT): Define.
4313 2024-01-26 Li Wei <liwei@loongson.cn>
4315 * config/loongarch/loongarch.cc (loongarch_emit_swdivsf): Adjust.
4317 2024-01-26 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4319 PR target/113469
4320 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_lcm_local_properties): Fix bug.
4322 2024-01-26 Andrew Pinski <quic_apinski@quicinc.com>
4324 PR target/100212
4325 * config/aarch64/aarch64.cc (aarch64_classify_index): Avoid
4326 undefined shift after the call to exact_log2.
4328 2024-01-25 Andrew Pinski <quic_apinski@quicinc.com>
4330 PR target/100204
4331 * config/aarch64/constraints.md (J): Cast to `unsigned HOST_WIDE_INT`
4332 before taking the negative of it.
4334 2024-01-25 Vladimir N. Makarov <vmakarov@redhat.com>
4336 PR target/113526
4337 * lra-constraints.cc (curr_insn_transform): Change class even for
4338 spilled pseudo successfully matched with with NO_REGS.
4340 2024-01-25 Georg-Johann Lay <avr@gjlay.de>
4342 PR target/113601
4343 * config/avr/avr-mcus.def (atmega3208, atmega3209): Fix data_section_start.
4345 2024-01-25 Szabolcs Nagy <szabolcs.nagy@arm.com>
4347 PR target/112987
4348 * config/aarch64/aarch64.cc (aarch64_gen_compare_zero_and_branch): New.
4349 (aarch64_expand_epilogue): Use the new function.
4350 (aarch64_split_compare_and_swap): Likewise.
4351 (aarch64_split_atomic_op): Likewise.
4353 2024-01-25 Robin Dapp <rdapp.gcc@gmail.com>
4355 PR middle-end/112971
4356 * fold-const.cc (simplify_const_binop): New function for binop
4357 simplification of two constant vectors when element-wise
4358 handling is not necessary.
4359 (const_binop): Call new function.
4361 2024-01-25 Mary Bennett <mary.bennett@embecosm.com>
4363 * common/config/riscv/riscv-common.cc: Add XCVbitmanip.
4364 * config/riscv/constraints.md: Likewise.
4365 * config/riscv/corev.def: Likewise.
4366 * config/riscv/corev.md: Likewise.
4367 * config/riscv/predicates.md: Likewise.
4368 * config/riscv/riscv-builtins.cc (AVAIL): Likewise.
4369 * config/riscv/riscv-ftypes.def: Likewise.
4370 * config/riscv/riscv.opt: Likewise.
4371 * config/riscv/riscv.cc (riscv_print_operand): Add new operand 'Y'.
4372 * doc/extend.texi: Add XCVbitmanip builtin documentation.
4373 * doc/sourcebuild.texi: Likewise.
4375 2024-01-25 Tobias Burnus <tburnus@baylibre.com>
4377 * config/gcn/gcn-hsa.h (ASM_SPEC): Add space after -mxnack= argument.
4379 2024-01-25 Yanzhang Wang <yanzhang.wang@intel.com>
4381 PR target/113538
4382 * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag.
4383 (riscv_fntype_abi): Ditto.
4384 * config/riscv/riscv.opt: Ditto.
4386 2024-01-25 Jakub Jelinek <jakub@redhat.com>
4388 PR middle-end/113574
4389 * convert.cc (convert_to_integer_1) <case LSHIFT_EXPR>: Compare shift
4390 count against TYPE_PRECISION rather than TYPE_SIZE.
4392 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
4394 PR target/113572
4395 * config/aarch64/aarch64-sve-builtins.cc (vector_cst_all_same):
4396 Check VECTOR_CST_ELT instead of VECTOR_CST_ENCODED_ELT
4398 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
4400 PR target/113550
4401 * config/aarch64/aarch64-simd.md: In the movv8di splitter, check
4402 whether each split instruction is a load that clobbers the source
4403 address. Emit that instruction last if so.
4405 2024-01-25 Richard Sandiford <richard.sandiford@arm.com>
4407 PR target/113485
4408 * config/aarch64/aarch64-simd.md (aarch64_zip1<mode>_low): New
4409 pattern.
4410 (<optab><Vnarrowq><mode>2): Use it instead of generating a
4411 paradoxical subreg for the input.
4413 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4415 * config/riscv/riscv-vsetvl.cc (get_all_predecessors): New function.
4416 (pre_vsetvl::pre_global_vsetvl_info): Add LCM delete block all
4417 predecessors dump information.
4419 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4421 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::compute_vsetvl_def_data): Remove
4422 redundant full available computation.
4423 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
4425 2024-01-25 Jakub Jelinek <jakub@redhat.com>
4427 * doc/generic.texi (VECTOR_CST): Fix typo - petterns -> patterns.
4428 * doc/rtl.texi (CONST_VECTOR): Likewise.
4430 2024-01-25 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4432 * config/riscv/riscv-opts.h (enum vsetvl_strategy_enum): Add optim-no-fusion option.
4433 * config/riscv/riscv-vsetvl.cc (pass_vsetvl::lazy_vsetvl): Ditto.
4434 (pass_vsetvl::execute): Ditto.
4435 * config/riscv/riscv.opt: Ditto.
4437 2024-01-25 Jiahao Xu <xujiahao@loongson.cn>
4439 * config/loongarch/lasx.md (@vec_concatz<mode>): Remove this define_insn pattern.
4440 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init): Use vec_concat<mode>.
4442 2024-01-25 Richard Biener <rguenther@suse.de>
4444 PR tree-optimization/113576
4445 * tree-vect-loop.cc (vec_init_loop_exit_info): Only allow
4446 exits with may_be_zero niters when its the last one.
4448 2024-01-25 Lulu Cheng <chenglulu@loongson.cn>
4450 * config/loongarch/loongarch.cc (loongarch_symbolic_constant_p):
4451 For symbols of type tls, non-zero Offset is not generated.
4453 2024-01-25 Haochen Gui <guihaoc@gcc.gnu.org>
4455 * config/rs6000/rs6000-string.cc (expand_block_compare): Enable
4456 P9 with m32 and mpowerpc64.
4458 2024-01-25 liuhongt <hongtao.liu@intel.com>
4460 * config/i386/i386-options.cc (ix86_option_override_internal):
4461 Enable -mlam=u57 by default when compiled with
4462 -fsanitize=hwaddress.
4464 2024-01-25 Palmer Dabbelt <palmer@rivosinc.com>
4466 * common/config/riscv/riscv-common.cc (riscv_implied_info):
4467 Remove {"ztso", "a"}.
4469 2024-01-24 Martin Jambor <mjambor@suse.cz>
4471 PR ipa/108007
4472 PR ipa/112616
4473 * cgraph.h (cgraph_edge): Add a parameter to
4474 redirect_call_stmt_to_callee.
4475 * ipa-param-manipulation.h (ipa_param_adjustments): Add a
4476 parameter to modify_call.
4477 (ipa_release_ssas_in_hash): Declare.
4478 * cgraph.cc (cgraph_edge::redirect_call_stmt_to_callee): New
4479 parameter killed_ssas, pass it to padjs->modify_call.
4480 * ipa-param-manipulation.cc (purge_all_uses): New function.
4481 (ipa_param_adjustments::modify_call): New parameter killed_ssas.
4482 Instead of substituting uses, invoke purge_all_uses. If
4483 hash of killed SSAs has not been provided, create a temporary one
4484 and release SSAs that have been added to it.
4485 (compare_ssa_versions): New function.
4486 (ipa_release_ssas_in_hash): Likewise.
4487 * tree-inline.cc (redirect_all_calls): Create
4488 id->killed_new_ssa_names earlier, pass it to edge redirection,
4489 adjust a comment.
4490 (copy_body): Release SSAs in id->killed_new_ssa_names.
4492 2024-01-24 Andrew Pinski <quic_apinski@quicinc.com>
4494 PR target/113486
4495 * config/aarch64/aarch64.cc (aarch64_get_reg_raw_mode): For
4496 TARGET_GENERAL_REGS_ONLY, return VOIDmode for non-GP_REGNUM_P regno.
4498 2024-01-24 Monk Chiang <monk.chiang@sifive.com>
4500 PR target/113095
4501 * config/riscv/sfb.md: New splitters to rewrite single bit
4502 sign extension as the condition to SFB instructions.
4504 2024-01-24 Jan Hubicka <jh@suse.cz>
4506 PR middle-end/88345
4507 * common.opt: (flimit-function-alignment): Reorder alphabeticaly
4508 (fmin-function-alignment): New parameter.
4509 * doc/invoke.texi: (-fmin-function-alignment): Document.
4510 (-falign-functions,-falign-loops,-falign-labels): Mention that
4511 aglinments are ignored in cold code.
4512 * varasm.cc (assemble_start_function): Handle min-function-alignment.
4514 2024-01-24 Tamar Christina <tamar.christina@arm.com>
4516 PR target/109636
4517 * config/aarch64/aarch64-simd.md (<su_optab>div<mode>3,
4518 mulv2di3): Remove.
4519 * config/aarch64/iterators.md (VQDIV): Remove.
4520 (SVE_FULL_SDI_SIMD, SVE_FULL_HSDI_SIMD_DI,
4521 SVE_I_SIMD_DI): New.
4522 (VPRED, sve_lane_con): Add V4SI and V2DI.
4523 * config/aarch64/aarch64-sve.md (<optab><mode>3,
4524 @aarch64_pred_<optab><mode>): Support Advanced SIMD types.
4525 (mul<mode>3): New, split from <optab><mode>3.
4526 (@aarch64_pred_<optab><mode>, *post_ra_<optab><mode>3): New.
4527 * config/aarch64/aarch64-sve2.md (@aarch64_mul_lane_<mode>,
4528 *aarch64_mul_unpredicated_<mode>): Change SVE_FULL_HSDI to
4529 SVE_FULL_HSDI_SIMD_DI.
4531 2024-01-24 Tamar Christina <tamar.christina@arm.com>
4533 PR tree-optimization/113552
4534 * config/aarch64/aarch64.cc
4535 (aarch64_simd_clone_compute_vecsize_and_simdlen): Block simdlen 1.
4537 2024-01-24 Martin Jambor <mjambor@suse.cz>
4539 PR ipa/113490
4540 * ipa-cp.cc (ipcp_lattice<valtype>::add_value): Bail out if value
4541 count is equal or greater than the limit. Use the limit from the
4542 callee.
4544 2024-01-24 YunQiang Su <syq@gcc.gnu.org>
4546 * configure.ac: Detect the explicit relocs support for
4547 mips, and define C macro MIPS_EXPLICIT_RELOCS.
4548 * config.in: Regenerated.
4549 * configure: Regenerated.
4550 * doc/invoke.texi(MIPS Options): Add -mexplicit-relocs.
4551 * config/mips/mips-opts.h: Define enum mips_explicit_relocs.
4552 * config/mips/mips.cc(mips_set_compression_mode): Sorry if
4553 !TARGET_EXPLICIT_RELOCS instead of just set it.
4554 * config/mips/mips.h: Define TARGET_EXPLICIT_RELOCS and
4555 TARGET_EXPLICIT_RELOCS_PCREL with mips_opt_explicit_relocs.
4556 * config/mips/mips.opt: Introduce -mexplicit-relocs= option
4557 and define -m(no-)explicit-relocs as aliases.
4559 2024-01-24 Alex Coplan <alex.coplan@arm.com>
4561 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
4562 to 1.
4563 (-mlate-ldp-fusion): Likewise.
4565 2024-01-24 Tamar Christina <tamar.christina@arm.com>
4567 * tree-vect-loop.cc (vect_get_vect_def,
4568 vect_create_epilog_for_reduction): Rename main_exit_p to
4569 last_val_reduc_p.
4571 2024-01-24 Tamar Christina <tamar.christina@arm.com>
4573 PR tree-optimization/113364
4574 * tree-vect-loop.cc (vect_create_epilog_for_reduction): If all exits all
4575 early exits then we must reduce from the first offset for all of them.
4577 2024-01-24 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4579 PR target/113495
4580 * config/riscv/riscv-vsetvl.cc (get_expr_id): Remove.
4581 (get_regno): Ditto.
4582 (get_bb_index): Ditto.
4583 (pre_vsetvl::compute_avl_def_data): Ditto.
4584 (pre_vsetvl::earliest_fuse_vsetvl_info): Fix large memory usage.
4585 (pre_vsetvl::pre_global_vsetvl_info): Ditto.
4587 2024-01-23 Andrew Pinski <quic_apinski@quicinc.com>
4588 Richard Sandiford <richard.sandiford@arm.com>
4590 PR target/100942
4591 * ccmp.cc (ccmp_candidate_p): Add outer argument.
4592 Allow if the outer is true and the lhs is used more
4593 than once.
4594 (expand_ccmp_expr): Update call to ccmp_candidate_p.
4595 * expr.h (expand_expr_real_gassign): Declare.
4596 * expr.cc (expand_expr_real_gassign): New function, split out from...
4597 (expand_expr_real_1): ...here.
4598 * cfgexpand.cc (expand_gimple_stmt_1): Use expand_expr_real_gassign.
4600 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4602 PR target/113089
4603 * config/aarch64/aarch64-ldp-fusion.cc (reset_debug_use): New.
4604 (fixup_debug_use): New.
4605 (fixup_debug_uses_trailing_add): New.
4606 (fixup_debug_uses): New. Use it ...
4607 (ldp_bb_info::fuse_pair): ... here.
4608 (try_promote_writeback): Call fixup_debug_uses_trailing_add to
4609 fix up debug uses of the base register that are affected by
4610 folding in the trailing add insn.
4612 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4614 PR target/113089
4615 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::fuse_pair):
4616 Update trailing nondebug uses of the base register in the case
4617 of cancelling writeback.
4619 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4621 PR target/113089
4622 * rtl-ssa/accesses.h (use_info::next_debug_insn_use): New.
4623 (debug_insn_use_iterator): New.
4624 (set_info::first_debug_insn_use): New.
4625 (set_info::debug_insn_uses): New.
4626 * rtl-ssa/member-fns.inl (use_info::next_debug_insn_use): New.
4627 (set_info::first_debug_insn_use): New.
4628 (set_info::debug_insn_uses): New.
4630 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4632 PR target/113356
4633 * config/aarch64/aarch64-ldp-fusion.cc (ldp_bb_info::try_fuse_pair):
4634 Don't record hazards against the opposite insn in the pair.
4636 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4638 PR target/113070
4639 * config/aarch64/aarch64-ldp-fusion.cc
4640 (struct stp_change_builder): New.
4641 (decide_stp_strategy): Reanme to ...
4642 (try_repurpose_store): ... this.
4643 (ldp_bb_info::fuse_pair): Refactor to use stp_change_builder to
4644 construct stp changes. Fix up uses when inserting new stp insns.
4646 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4648 PR target/113070
4649 * rtl-ssa.h: Include hash-set.h.
4650 * rtl-ssa/changes.cc (function_info::finalize_new_accesses): Add
4651 new_sets parameter and use it to keep track of new user-created sets.
4652 (function_info::apply_changes_to_insn): Also call add_def on new sets.
4653 (function_info::change_insns): Add hash_set to keep track of new
4654 user-created defs. Plumb it through.
4655 * rtl-ssa/functions.h: Add hash_set parameter to finalize_new_accesses and
4656 apply_changes_to_insn.
4658 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4660 PR target/113070
4661 * rtl-ssa/accesses.cc (function_info::create_use): New.
4662 * rtl-ssa/changes.cc (function_info::finalize_new_accesses):
4663 Ensure new uses end up referring to permanent defs.
4664 * rtl-ssa/functions.h (function_info::create_use): Declare.
4666 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4668 PR target/113070
4669 * rtl-ssa/changes.cc (function_info::change_insns): Split out the call
4670 to finalize_new_accesses from the backwards placement loop, run it
4671 forwards in a separate loop.
4673 2024-01-23 Richard Biener <rguenther@suse.de>
4675 PR tree-optimization/113552
4676 * tree-vect-stmts.cc (vectorizable_simd_clone_call): Use
4677 floor_log2 instead of exact_log2 on the number of calls.
4679 2024-01-23 Jeff Law <jlaw@ventanamicro.com>
4680 Jakub Jelinek <jakub@redhat.com>
4682 * config/ia64/ia64.cc (ia64_start_function): Add ATTRIBUTE_UNUSED to
4683 decl.
4685 2024-01-23 Richard Biener <rguenther@suse.de>
4687 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4688 Separate single and multi-exit case when creating PHIs between
4689 the main and epilogue.
4691 2024-01-23 Richard Sandiford <richard.sandiford@arm.com>
4693 PR target/112989
4694 * config/aarch64/aarch64-sve-builtins-shapes.cc (build_one): Skip
4695 MODE_single variants of functions that don't take tuple arguments.
4697 2024-01-23 Alex Coplan <alex.coplan@arm.com>
4699 PR target/113114
4700 * config/aarch64/aarch64-ldp-fusion.cc (try_promote_writeback):
4701 Don't assert recog success, just punt if the writeback pair
4702 isn't recognized.
4704 2024-01-23 Jakub Jelinek <jakub@redhat.com>
4706 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Add
4707 ATTRIBUTE_UNUSED to decl.
4709 2024-01-23 Richard Biener <rguenther@suse.de>
4711 PR debug/107058
4712 * dwarf2out.cc (dwarf2out_die_ref_for_decl): Gracefully
4713 handle unexpected but bogus DIE contexts when not checking
4714 enabled.
4716 2024-01-23 Jakub Jelinek <jakub@redhat.com>
4718 PR tree-optimization/113462
4719 * fold-const.cc (native_interpret_int): Don't punt if total_bytes
4720 is larger than HOST_BITS_PER_DOUBLE_INT / BITS_PER_UNIT.
4721 (fold_view_convert_expr): Use XALLOCAVEC buffers for types with
4722 sizes between 129 and 8192 bytes.
4724 2024-01-23 Xi Ruoyao <xry111@xry111.site>
4726 * config/loongarch/loongarch.cc (loongarch_explicit_relocs_p):
4727 If la_opt_explicit_relocs is EXPLICIT_RELOCS_AUTO, return false
4728 for SYMBOL_TLS_LDM and SYMBOL_TLS_GD.
4729 (loongarch_call_tls_get_addr): Do not split symbols of
4730 SYMBOL_TLS_LDM or SYMBOL_TLS_GD if la_opt_explicit_relocs is
4731 EXPLICIT_RELOCS_AUTO.
4733 2024-01-23 Richard Biener <rguenther@suse.de>
4735 * alias.cc (known_base_value_p): Remove.
4736 (find_base_value): Remove PLUS/MINUS handling
4737 when both operands are not CONST_INT_P.
4739 2024-01-23 Richard Biener <rguenther@suse.de>
4741 PR rtl-optimization/113255
4742 * alias.cc (find_base_term): Remove PLUS/MINUS handling
4743 when both operands are not CONST_INT_P.
4745 2024-01-23 Richard Biener <rguenther@suse.de>
4747 PR debug/112718
4748 * dwarf2out.cc (dwarf2out_finish): Reset all type units
4749 for the fat part of an LTO compile.
4751 2024-01-23 chenxiaolong <chenxiaolong@loongson.cn>
4753 * doc/sourcebuild.texi: Add attributes for keywords.
4755 2024-01-23 Sandra Loosemore <sandra@codesourcery.com>
4757 PR c++/90463
4758 * doc/invoke.texi (Warning Options): Correct lists of options
4759 enabled by -Wall and -Wextra by checking against common.opt
4760 and c-family/c.opt.
4762 2024-01-22 Andrew Pinski <quic_apinski@quicinc.com>
4764 PR target/113030
4765 * config/arm/parsecpu.awk (check_cpu): Use cpu_opt_alias
4766 instead of cpu_optaliases.
4767 (check_arch): Use arch_opt_alias instead of arch_optaliases.
4769 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4771 * config/riscv/riscv-protos.h (splat_to_scalar_move_p): New function.
4772 * config/riscv/riscv-v.cc (splat_to_scalar_move_p): Ditto.
4773 * config/riscv/vector.md: Simplify vmv.v.x. into vmv.s.x.
4775 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4777 PR target/109092
4778 * config/riscv/riscv.md: Use reg instead of subreg.
4780 2024-01-22 Tobias Burnus <tburnus@baylibre.com>
4782 PR other/111966
4783 * config/gcn/mkoffload.cc (elf_arch): Change default to gfx900
4784 to match the compiler default.
4785 (simple_object_copy_lto_debug_sections): Never unlink the outfile
4786 on error as the caller does so.
4787 (maybe_unlink, compile_native): Use %<...%> and %qs in fatal_error.
4788 (main): Likewise. Fix 'mkoffload.dbg.o' cleanup.
4790 2024-01-22 Richard Biener <rguenther@suse.de>
4792 PR tree-optimization/113373
4793 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4794 Create LC PHIs in the exit blocks where necessary.
4795 * tree-vect-loop.cc (vectorizable_live_operation): Do not try
4796 to handle missing LC PHIs.
4797 (find_connected_edge): Remove.
4798 (vect_create_epilog_for_reduction): Cleanup use of auto_vec.
4800 2024-01-22 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4802 * config/riscv/vector.md: Fix vfirst/vmsbf/vmsof ratio attributes.
4804 2024-01-22 xuli <xuli1@eswincomputing.com>
4806 PR target/113420
4807 * config/riscv/riscv-vector-builtins.cc (has_vxrm_or_frm_p):remove.
4808 (registered_function::overloaded_hash):refactor.
4809 (resolve_overloaded_builtin):avoid internal ICE.
4811 2024-01-21 Mikael Pettersson <mikpelinux@gmail.com>
4813 PR target/82420
4814 PR target/111279
4815 * calls.cc (emit_library_call_value_1): Pass valid TYPE
4816 to emit_push_insn.
4817 * expr.cc (emit_push_insn): Likewise.
4819 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
4821 * config/riscv/riscv.cc (riscv_init_cumulative_args): Install
4822 correcction version of last change.
4824 2024-01-21 Jeff Law <jlaw@ventanamicro.com>
4826 * config/riscv/riscv.cc (riscv_init_cumulative_args): Update and
4827 fix bugs in signature.
4829 2024-01-21 Roger Sayle <roger@nextmovesoftware.com>
4830 Richard Biener <rguenther@suse.de>
4832 PR rtl-optimization/111267
4833 * fwprop.cc (fwprop_propagation::profitabe_p): Rename
4834 profitable_p method to likely_profitable_p.
4835 (try_fwprop_subst_node): Update call to likely_profitable_p.
4836 Only bail-out early when !prop.likely_profitable_p for instructions
4837 that are not single sets. When comparing costs, bail-out if the
4838 cost is unchanged and !prop.likely_profitable_p.
4840 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
4842 PR c++/90464
4843 * doc/invoke.texi (Warning Options): Document that -Wunused-parameter
4844 isn't enabled by -Wunused unless -Wextra is provided, and that
4845 -Wunused does enable -Wunused-const-variable=1 for C. Clarify that
4846 -Wunused doesn't enable -Wunused-* options documented as behaving
4847 otherwise, and list them explicitly.
4849 2024-01-21 Sandra Loosemore <sandra@codesourcery.com>
4851 PR c/109708
4852 * doc/invoke.texi (Warning Options): Fix broken example and
4853 clean up/reorganize the others. Also describe what the short-form
4854 options mean.
4856 2024-01-20 Sandra Loosemore <sandra@codesourcery.com>
4858 PR c/102998
4859 * doc/invoke.texi (Option Summary): Add -Warray-parameter.
4860 (Warning Options): Correct/edit discussion of -Warray-parameter
4861 to make the first example less confusing, and fill in missing info.
4863 2024-01-20 Jakub Jelinek <jakub@redhat.com>
4865 PR tree-optimization/113462
4866 * gimple-lower-bitint.cc (bitint_large_huge::handle_cast):
4867 Handle rhs1 INTEGER_CST like SSA_NAME.
4869 2024-01-20 Jakub Jelinek <jakub@redhat.com>
4871 PR tree-optimization/113491
4872 * tree-switch-conversion.cc (switch_conversion::build_constructors):
4873 If elt.index has precision higher than sizetype, fold_convert it to
4874 sizetype.
4875 (switch_conversion::array_value_type): Return type if type is
4876 BITINT_TYPE with precision above MAX_FIXED_MODE_SIZE or with BLKmode.
4877 (switch_conversion::build_arrays): Use unsigned_type_for rather than
4878 lang_hooks.types.type_for_mode if utype is BITINT_TYPE with precision
4879 above MAX_FIXED_MODE_SIZE or with BLKmode. If utype has precision
4880 higher than sizetype, use sizetype as tidx type and fold_convert the
4881 subtraction to sizetype.
4883 2024-01-20 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4885 * config/riscv/riscv.cc (riscv_init_cumulative_args): Suppress warning.
4886 (riscv_vector_mode_supported_any_target_p): Ditto.
4888 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
4890 PR target/110934
4891 * config/m68k/m68k.cc (m68k_zero_call_used_regs): New function.
4892 (TARGET_ZERO_CALL_USED_REGS): Define.
4894 2024-01-19 Mikael Pettersson <mikpelinux@gmail.com>
4896 PR target/108640
4897 * config/m68k/m68k.cc (output_andsi3): Use QImode for
4898 address adjusted for 1-byte RMW access.
4899 (output_iorsi3): Likewise.
4900 (output_xorsi3): Likewise.
4902 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
4904 * doc/invoke.texi (RISC-V Options): Add list of supported
4905 extensions.
4907 2024-01-19 Juzhe-Zhong <juzhe.zhong@rivai.ai>
4909 PR target/113495
4910 * config/riscv/riscv-protos.h (RVV_VLMAX): Change to regno_reg_rtx[X0_REGNUM].
4911 (RVV_VUNDEF): Ditto.
4912 * config/riscv/riscv-vsetvl.cc: Add timevar.
4914 2024-01-19 Richard Biener <rguenther@suse.de>
4916 PR debug/113488
4917 * lto-streamer-in.cc (lto_read_tree_1): When there isn't
4918 an early DIE but there should be, do not pretend there is.
4920 2024-01-19 Richard Biener <rguenther@suse.de>
4922 PR tree-optimization/113494
4923 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
4924 Handle endless loop on exit. Handle re-allocated PHI.
4926 2024-01-19 Jakub Jelinek <jakub@redhat.com>
4928 PR tree-optimization/113464
4929 * gimple-lower-bitint.cc (gimple_lower_bitint): Don't try to
4930 optimize loads into GIMPLE_ASM stmts.
4932 2024-01-19 Jakub Jelinek <jakub@redhat.com>
4934 PR tree-optimization/113463
4935 * gimple-ssa-warn-restrict.cc (builtin_memref::extend_offset_range):
4936 Only look through NOP_EXPRs if rhs1 doesn't have wider type than
4937 lhs.
4939 2024-01-19 Jakub Jelinek <jakub@redhat.com>
4941 PR tree-optimization/113459
4942 * tree-ssa-sccvn.cc (vn_walk_cb_data::push_partial_def): Use
4943 TREE_INT_CST_LOW of TYPE_SIZE_UNIT rather than GET_MODE_SIZE
4944 of SCALAR_INT_TYPE_MODE if type has BLKmode.
4945 (vn_reference_lookup_3): Likewise. Formatting fix.
4947 2024-01-19 Jakub Jelinek <jakub@redhat.com>
4948 Richard Biener <rguenther@suse.de>
4950 * cfgexpand.cc (discover_nonconstant_array_refs_r): Force non-BLKmode
4951 VAR_DECLs referenced in BLKmode VIEW_CONVERT_EXPRs into memory.
4952 * expr.cc (expand_expr_real_1) <case VIEW_CONVERT_EXPR>: Do nothing
4953 but adjust_address also for BLKmode mode and MEM op0.
4955 2024-01-19 Palmer Dabbelt <palmer@rivosinc.com>
4957 * common/config/riscv/riscv-common.cc: Add Zihpm and Zicnttr
4958 extensions.
4960 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
4962 * doc/invoke.texi (RISC-V Options): Document the syntax of -march.
4964 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
4966 * common/config/riscv/riscv-common.cc
4967 (riscv_subset_list::parse_std_ext): Remove.
4968 (riscv_subset_list::parse_multiletter_ext): Remove.
4969 * config/riscv/riscv-subset.h
4970 (riscv_subset_list::parse_std_ext): Remove.
4971 (riscv_subset_list::parse_multiletter_ext): Remove.
4973 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
4975 * common/config/riscv/riscv-common.cc
4976 (riscv_subset_list::parse_single_std_ext): New parameter.
4977 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
4978 (riscv_subset_list::parse_single_ext): Ditto.
4979 (riscv_subset_list::parse): Relax the order for the input of ISA
4980 string.
4981 * config/riscv/riscv-subset.h
4982 (riscv_subset_list::parse_single_std_ext): New parameter.
4983 (riscv_subset_list::parse_single_multiletter_ext): Ditto.
4984 (riscv_subset_list::parse_single_ext): Ditto.
4986 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
4988 * common/config/riscv/riscv-common.cc
4989 (riscv_subset_list::parse_base_ext): New.
4990 (riscv_subset_list::parse): Extract part of logic into
4991 riscv_subset_list::parse_base_ext.
4992 * config/riscv/riscv-subset.h (riscv_subset_list::parse_base_ext):
4993 New.
4995 2024-01-19 Kito Cheng <kito.cheng@sifive.com>
4997 * config/riscv/riscv.cc (riscv_override_options_internal): Tweak
4998 sorry message.
5000 2024-01-19 Kuan-Lin Chen <rufus@andestech.com>
5002 * config/riscv/vector-crypto.md (UNSPEC_CLMUL): Rename to
5003 UNSPEC_CLMUL_VC.
5005 2024-01-19 Sandra Loosemore <sandra@codesourcery.com>
5007 PR c/110029
5008 * doc/extend.texi (Common Variable Attributes): Explain what
5009 happens when multiple variables with cleanups are in the same scope.
5011 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
5013 PR ipa/108470
5014 * doc/extend.texi (Common Function Attributes): Document that
5015 noinline also disables some interprocedural optimizations and
5016 improve flow to the part about using inline asm instead to
5017 disable calls from being optimized away completely. Remove the
5018 sentence that says noipa is mainly for internal compiler testing.
5020 2024-01-18 John David Anglin <danglin@gcc.gnu.org>
5022 PR tree-optimization/69807
5023 * config/pa/pa.cc (pa_option_override): Set flag_pie on TARGET_64BIT.
5025 2024-01-18 Brian Inglis <Brian.Inglis@Shaw.ca>
5027 PR target/108521
5028 * doc/invoke.texi (Option Summary): Remove -mcygwin and -mno-cygwin
5029 from x86 Windows Options.
5031 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
5033 PR c/107942
5034 * doc/extend.texi (C Extensions): Add new section to menu.
5035 (Function Attributes): Move dangling index entries to....
5036 (Const and Volatile Functions): New section.
5038 2024-01-18 David Malcolm <dmalcolm@redhat.com>
5040 PR middle-end/112684
5041 * toplev.cc (toplev::main): Don't ICE in
5042 -fdiagnostics-generate-patch when exiting after options,
5043 since no edit context will have been created.
5045 2024-01-18 Richard Biener <rguenther@suse.de>
5047 * tree-vect-stmts.cc (vectorizable_store): Do not pre-allocate
5048 operands vector.
5050 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
5052 * Makefile.in: Emit ENABLE_DARWIN_AT_RPATH into site.exp
5053 when ENABLE_DARWIN_AT_RPATH_TRUE is not '#'.
5055 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5056 Jin Ma <jinma@linux.alibaba.com>
5057 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5058 Christoph Müllner <christoph.muellner@vrull.eu>
5060 * config/riscv/thead.cc
5061 (th_asm_output_opcode): Rewrite some instructions.
5063 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5064 Jin Ma <jinma@linux.alibaba.com>
5065 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5066 Christoph Müllner <christoph.muellner@vrull.eu>
5068 * config/riscv/riscv.md (none,thv,rvv): New attribute.
5069 (no,yes): Add an attribute to disable alternative
5070 for xtheadvector or RVV1.0.
5071 * config/riscv/vector.md:
5072 Disable alternatives that destination register overlaps
5073 source register group for xtheadvector.
5075 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5076 Jin Ma <jinma@linux.alibaba.com>
5077 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5078 Christoph Müllner <christoph.muellner@vrull.eu>
5080 * config/riscv/riscv-vector-builtins-bases.cc
5081 (class th_loadstore_width): Define new builtin bases.
5082 (class th_extract): Define new builtin bases.
5083 (BASE): Define new builtin bases.
5084 * config/riscv/riscv-vector-builtins-bases.h:
5085 Define new builtin class.
5086 * config/riscv/riscv-vector-builtins-shapes.cc
5087 (struct th_loadstore_width_def): Define new builtin shapes.
5088 (struct th_indexed_loadstore_width_def):
5089 Define new builtin shapes.
5090 (struct th_extract_def): Define new builtin shapes.
5091 (SHAPE): Define new builtin shapes.
5092 * config/riscv/riscv-vector-builtins-shapes.h:
5093 Define new builtin shapes.
5094 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_FUNCTION):
5095 Redefine DEF_RVV_FUNCTION for XTheadVector special intrinsics.
5096 * config/riscv/riscv-vector-builtins.h
5097 (enum required_ext): Add new XTheadVector member.
5098 (struct function_group_info): Likewise.
5099 * config/riscv/t-riscv:
5100 Add thead-vector-builtins-functions.def
5101 * config/riscv/thead-vector.md
5102 (@pred_mov_width<vlmem_op_attr><mode>): Add new patterns.
5103 (*pred_mov_width<vlmem_op_attr><mode>): Likewise.
5104 (@pred_store_width<vlmem_op_attr><mode>): Likewise.
5105 (@pred_strided_load_width<vlmem_op_attr><mode>): Likewise.
5106 (@pred_strided_store_width<vlmem_op_attr><mode>): Likewise.
5107 (@pred_indexed_load_width<vlmem_op_attr><mode>): Likewise.
5108 (@pred_th_extract<mode>): Likewise.
5109 (*pred_th_extract<mode>): Likewise.
5110 * config/riscv/thead-vector-builtins-functions.def: New file.
5112 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5113 Jin Ma <jinma@linux.alibaba.com>
5114 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5115 Christoph Müllner <christoph.muellner@vrull.eu>
5117 * config.gcc: Add files for XTheadVector intrinsics.
5118 * config/riscv/autovec.md: Guard XTheadVector.
5119 * config/riscv/predicates.md: Disable immediate vl
5120 for XTheadVector.
5121 * config/riscv/riscv-c.cc (riscv_pragma_intrinsic):
5122 Add pragma for XTheadVector.
5123 * config/riscv/riscv-string.cc (riscv_expand_block_move):
5124 Guard XTheadVector.
5125 * config/riscv/riscv-v.cc (vls_mode_valid_p):
5126 Avoid autovec.
5127 * config/riscv/riscv-vector-builtins-bases.cc:
5128 Do not normalize vsetvl instructions for XTheadVector.
5129 * config/riscv/riscv-vector-builtins-shapes.cc (check_type):
5130 New check type function.
5131 (build_one): Adjust for XTheadVector.
5132 * config/riscv/riscv-vector-switch.def (ENTRY):
5133 Disable fractional mode for the XTheadVector extension.
5134 (TUPLE_ENTRY): Likewise.
5135 * config/riscv/riscv.cc (riscv_v_adjust_bytesize):
5136 Guard XTheadVector.
5137 (riscv_preferred_simd_mode): Likewsie.
5138 (riscv_autovectorize_vector_modes): Likewise.
5139 (riscv_vector_mode_supported_any_target_p): Likewise.
5140 (TARGET_VECTOR_MODE_SUPPORTED_ANY_TARGET_P): Likewise.
5141 * config/riscv/thead.cc (th_asm_output_opcode):
5142 Rewrite vsetvl instructions.
5143 * config/riscv/vector.md:
5144 Include thead-vector.md and change fractional LMUL
5145 into 1 for vbool.
5146 * config/riscv/riscv_th_vector.h: New file.
5147 * config/riscv/thead-vector.md: New file.
5149 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5150 Jin Ma <jinma@linux.alibaba.com>
5151 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5152 Christoph Müllner <christoph.muellner@vrull.eu>
5154 * config/riscv/riscv-protos.h (riscv_asm_output_opcode):
5155 Add new function to add assembler insn code prefix/suffix.
5156 (th_asm_output_opcode):
5157 Add Thead function to add assembler insn code prefix/suffix.
5158 * config/riscv/riscv.cc (riscv_asm_output_opcode):
5159 Implement function to add assembler insn code prefix/suffix.
5160 * config/riscv/riscv.h (ASM_OUTPUT_OPCODE):
5161 Add new function to add assembler insn code prefix/suffix.
5162 * config/riscv/thead.cc (th_asm_output_opcode):
5163 Implement Thead function to add assembler insn code
5164 prefix/suffix.
5166 2024-01-18 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
5167 Jin Ma <jinma@linux.alibaba.com>
5168 Xianmiao Qu <cooper.qu@linux.alibaba.com>
5169 Christoph Müllner <christoph.muellner@vrull.eu>
5171 * common/config/riscv/riscv-common.cc
5172 (riscv_subset_list::parse): Add new vendor extension.
5173 * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
5174 Add test marco.
5175 * config/riscv/riscv.opt: Add new mask.
5177 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
5179 * config/darwin.h (DARWIN_RPATH_SPEC): Arrange for the %P spec
5180 to be conditional on macosx-version-min.
5182 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
5184 * config/darwin.cc (darwin_objc1_section): Use the correct
5185 meta-data version for constant strings.
5186 (machopic_select_section): Assert if we fail to handle CFString
5187 sections as Obejctive-C meta-data or drectly.
5189 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
5191 * lto-section-names.h (OFFLOAD_SECTION_NAME_PREFIX,
5192 OFFLOAD_VAR_TABLE_SECTION_NAME, OFFLOAD_FUNC_TABLE_SECTION_NAME,
5193 OFFLOAD_IND_FUNC_TABLE_SECTION_NAME): Provide Mach-O syntax
5194 versions when the object format is Mach-O.
5196 2024-01-18 Iain Sandoe <iain@sandoe.co.uk>
5198 PR target/105522
5199 * config/darwin.cc (machopic_select_section): Handle C and C++
5200 CFStrings.
5201 (darwin_rename_builtins): Move this out of the CFString code.
5202 (darwin_libc_has_function): Likewise.
5203 (darwin_build_constant_cfstring): Create an anonymous var to
5204 hold each CFString.
5205 * config/darwin.h (ASM_OUTPUT_LABELREF): Handle constant
5206 CFstrings.
5208 2024-01-18 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
5210 PR bootstrap/113445
5211 * haifa-sched.cc (dep_list_size): Make global.
5212 * sched-deps.cc (find_inc): Use instead of sd_lists_size().
5213 * sched-int.h (dep_list_size): Declare.
5215 2024-01-18 Martin Jambor <mjambor@suse.cz>
5217 PR tree-optimization/110422
5218 * tree-sra.cc (scan_function): Disqualify bases of operands of asm
5219 gotos.
5221 2024-01-18 Richard Biener <rguenther@suse.de>
5223 PR tree-optimization/113475
5224 * gimple-range-phi.h (phi_analyzer::m_phi_groups): New.
5225 * gimple-range-phi.cc (phi_analyzer::phi_analyzer): Initialize.
5226 (phi_analyzer::~phi_analyzer): Deallocate and free collected
5227 phi_grous.
5228 (phi_analyzer::process_phi): Record allocated phi_groups.
5230 2024-01-18 Richard Biener <rguenther@suse.de>
5232 * tree-vect-stmts.cc (vectorizable_store): Do not allocate
5233 storage for gvec_oprnds elements.
5235 2024-01-18 Richard Biener <rguenther@suse.de>
5237 * tree-vect-loop.cc (vec_init_loop_exit_info): Adjust comment,
5238 prefer all later exits we can handle.
5239 (vect_analyze_loop_form): Free the allocated loop body.
5240 Adjust comments.
5242 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5244 * config/avr/avr-log.cc: Tabify.
5246 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5248 * config/riscv/autovec.md: Support vi variant.
5250 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5252 * config/avr/avr-devices.cc: Tabify.
5254 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5256 * config/avr/avr-c.cc: Tabify.
5258 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5260 * config/avr/driver-avr.cc: Tabify.
5262 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5264 * config/avr/gen-avr-mmcu-texi.cc: Tabify.
5266 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5268 * config/avr/gen-avr-mmcu-specs.cc: Tabify.
5270 2024-01-18 Jakub Jelinek <jakub@redhat.com>
5272 * config/riscv/riscv.opt (mshorten-memrefs, mrelax, mcsr-check,
5273 minline-strcmp, minline-strncmp, minline-strlen,
5274 -param=riscv-vector-abi): Remove Bool keywords.
5276 2024-01-18 Jakub Jelinek <jakub@redhat.com>
5278 PR target/113122
5279 * config/i386/i386.cc (x86_function_profiler): Add -masm=intel
5280 support. Add missing space after , in emitted assembly in some
5281 cases. Formatting fixes.
5283 2024-01-18 Xi Ruoyao <xry111@xry111.site>
5285 * config/loongarch/loongarch.md (movsi_internal): Remove
5286 constraint z.
5288 2024-01-18 Georg-Johann Lay <avr@gjlay.de>
5290 * config/avr/gen-avr-mmcu-specs.cc (diagnose_rodata_in_ram): Fix typo
5291 in the diagnostic, and capitalize the device name.
5292 (print_mcu): Generate specs such that:
5293 <*check_rodata_in_ram>: New.
5294 <*cc1_misc>: Use check_rodata_in_ram instead of cc1_rodata_in_ram.
5295 <*link_misc>: Use check_rodata_in_ram instead of link_rodata_in_ram.
5296 <*cc1_rodata_in_ram, *link_rodata_in_ram>: Remove.
5298 2024-01-18 Jakub Jelinek <jakub@redhat.com>
5300 PR other/113399
5301 * common.opt (ffold-mem-offsets): Remove Target and Bool keywords, add
5302 Common and Optimization.
5304 2024-01-18 Richard Biener <rguenther@suse.de>
5306 PR tree-optimization/113431
5307 * tree-vect-data-refs.cc (vect_preserves_scalar_order_p):
5308 When there is an invariant load we might not preserve
5309 scalar order.
5311 2024-01-18 Richard Biener <rguenther@suse.de>
5313 PR tree-optimization/113374
5314 * tree-ssa-operands.h (SET_PHI_ARG_DEF_ON_EDGE): New.
5315 * tree-vect-loop.cc (move_early_exit_stmts): Update
5316 virtual LC PHIs.
5317 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5318 Refactor. Preserve virtual LC PHIs on all exits.
5320 2024-01-18 Lulu Cheng <chenglulu@loongson.cn>
5322 * config/loongarch/loongarch.cc (loongarch_split_symbol):
5323 Assign the '/u' attribute to the mem.
5325 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
5327 PR middle-end/110847
5328 * doc/invoke.texi (Option Summary): Document negative forms of
5329 -Wtsan and -Wxor-used-as-pow.
5330 (Warning Options): Likewise.
5332 2024-01-18 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5334 PR target/113429
5335 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::earliest_fuse_vsetvl_info): Fix bug.
5337 2024-01-18 Sandra Loosemore <sandra@codesourcery.com>
5339 * doc/extend.texi (Common Function Attributes): Re-alphabetize
5340 the table.
5341 (Common Variable Attributes): Likewise.
5342 (Common Type Attributes): Likewise.
5344 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
5346 PR middle-end/111659
5347 * doc/extend.texi (Common Variable Attributes): Fix long lines
5348 in documentation of strict_flex_array + other minor copy-editing.
5349 Add a cross-reference to -Wstrict-flex-arrays.
5350 * doc/invoke.texi (Option Summary): Fix whitespace in tables
5351 before -fstrict-flex-arrays and -Wstrict-flex-arrays.
5352 (C Dialect Options): Combine the docs for the two
5353 -fstrict-flex-arrays forms into a single entry. Note this option
5354 is for C/C++ only. Add a cross-reference to -Wstrict-flex-arrays.
5355 (Warning Options): Note -Wstrict-flex-arrays is for C/C++ only.
5356 Minor copy-editing. Add cross references to the strict_flex_array
5357 attribute and -fstrict-flex-arrays option. Add note that this
5358 option depends on -ftree-vrp.
5360 2024-01-17 Andrew Pinski <quic_apinski@quicinc.com>
5362 PR target/113221
5363 * config/aarch64/predicates.md (aarch64_ldp_reg_operand): For subreg,
5364 only allow REG operands instead of allowing all.
5366 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
5368 * config/riscv/riscv-vsetvl.cc (earliest_fuse_vsetvl_info):
5369 Remove redundant checks in else condition for readablity.
5370 (earliest_fuse_vsetvl_info) Print iteration count in debug
5371 prints.
5372 (earliest_fuse_vsetvl_info) Fix misleading vsetvl info
5373 dump details in certain cases.
5375 2024-01-17 Vineet Gupta <vineetg@rivosinc.com>
5377 * config/riscv/riscv.opt: New -param=vsetvl-strategy.
5378 * config/riscv/riscv-opts.h: New enum vsetvl_strategy_enum.
5379 * config/riscv/riscv-vsetvl.cc
5380 (pre_vsetvl::pre_global_vsetvl_info): Use vsetvl_strategy.
5381 (pass_vsetvl::execute): Use vsetvl_strategy.
5383 2024-01-17 Jan Hubicka <jh@suse.cz>
5385 * ipa-polymorphic-call.cc (ipa_polymorphic_call_context::set_by_invariant): Remove
5386 accidental hack reseting offset.
5388 2024-01-17 Jan Hubicka <jh@suse.cz>
5390 * config/i386/i386-options.cc (ix86_option_override_internal): Fix
5391 handling of X86_TUNE_AVOID_512FMA_CHAINS.
5393 2024-01-17 Jan Hubicka <jh@suse.cz>
5394 Jakub Jelinek <jakub@redhat.com>
5396 PR tree-optimization/110852
5397 * predict.cc (expr_expected_value_1): Fix profile merging of PHI and
5398 binary operations
5399 (get_predictor_value): Handle PRED_COMBINED_VALUE_PREDICTIONS and
5400 PRED_COMBINED_VALUE_PREDICTIONS_PHI
5401 * predict.def (PRED_COMBINED_VALUE_PREDICTIONS): New predictor.
5402 (PRED_COMBINED_VALUE_PREDICTIONS_PHI): New predictor.
5404 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5406 PR tree-optimization/113421
5407 * gimple-lower-bitint.cc (stmt_needs_operand_addr): Adjust function
5408 comment.
5409 (bitint_dom_walker::before_dom_children): Add g temporary to simplify
5410 formatting. Start at vop rather than cvop even if stmt is a store
5411 and needs_operand_addr.
5413 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5415 PR middle-end/113410
5416 * gimple-ssa-warn-access.cc (pass_waccess::maybe_check_access_sizes):
5417 If access_nelts is integral with larger precision than sizetype,
5418 fold_convert it to sizetype.
5420 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5422 PR tree-optimization/113408
5423 * gimple-lower-bitint.cc (bitint_large_huge::handle_stmt): For
5424 VIEW_CONVERT_EXPR, pass TREE_OPERAND (rhs1, 0) rather than rhs1
5425 to handle_cast.
5427 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5429 PR middle-end/113406
5430 * ipa-strub.cc (pass_ipa_strub::execute): Check aggregate_value_p
5431 regardless of whether is_gimple_reg_type (restype) or not.
5433 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5435 * tree-into-ssa.cc (pass_build_ssa::gate): Fix comment typo,
5436 funcions -> functions, and use were instead of was.
5437 * gengtype.cc (dump_typekind): Fix comment typos, funcion -> function
5438 and guaranteee -> guarantee.
5439 * attribs.h (struct attr_access): Fix comment typo funcion -> function.
5441 2024-01-17 Jakub Jelinek <jakub@redhat.com>
5443 PR middle-end/113409
5444 * omp-general.cc (omp_adjust_for_condition): Handle BITINT_TYPE like
5445 INTEGER_TYPE.
5446 (omp_extract_for_data): Use build_bitint_type rather than
5447 build_nonstandard_integer_type if either iter_type or loop->v type
5448 is BITINT_TYPE.
5449 * omp-expand.cc (expand_omp_for_generic,
5450 expand_omp_taskloop_for_outer, expand_omp_taskloop_for_inner): Handle
5451 BITINT_TYPE like INTEGER_TYPE.
5453 2024-01-17 Richard Biener <rguenther@suse.de>
5455 PR tree-optimization/113371
5456 * tree-vect-data-refs.cc (vect_enhance_data_refs_alignment):
5457 Do not peel when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
5458 * tree-vect-loop-manip.cc (vect_do_peeling): Assert we do
5459 not perform prologue peeling when LOOP_VINFO_EARLY_BREAKS_VECT_PEELED.
5461 2024-01-17 Maxim Kuvyrkov <maxim.kuvyrkov@linaro.org>
5463 PR rtl-optimization/96388
5464 PR rtl-optimization/111554
5465 * sched-deps.cc (find_inc): Avoid exponential behavior.
5467 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
5469 PR c/111693
5470 * doc/invoke.texi (Option Summary): Move -Wuseless-cast
5471 from C++ Language Options to Warning Options. Add entry for
5472 -Wuse-after-free.
5473 (C++ Dialect Options): Move -Wuse-after-free and -Wuseless-cast
5474 from here....
5475 (Warning Options): ...to here. Minor copy-editing to fix typo
5476 and grammar.
5478 2024-01-17 YunQiang Su <syq@gcc.gnu.org>
5480 * config/mips/mips.cc (mips_compute_frame_info): If another
5481 register is used as global_pointer, mark $GP live false.
5483 2024-01-17 Sandra Loosemore <sandra@codesourcery.com>
5485 PR target/112973
5486 * doc/extend.texi (BPF Built-in Functions): Wrap long lines and
5487 give the section a light copy-editing pass.
5489 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
5491 * config/aarch64/aarch64-cores.def (AARCH64_CORE): Add 'cobalt-100' CPU.
5492 * config/aarch64/aarch64-tune.md: Regenerated.
5493 * doc/invoke.texi (-mcpu): Add cobalt-100 core.
5495 2024-01-16 Wilco Dijkstra <wilco.dijkstra@arm.com>
5497 PR target/112573
5498 * config/aarch64/aarch64.cc (aarch64_legitimize_address): Reassociate
5499 badly formed CONST expressions.
5501 2024-01-16 Daniel Cederman <cederman@gaisler.com>
5503 * config/sparc/sparc.cc (next_active_non_empty_insn): Length 0 treated as empty
5505 2024-01-16 Daniel Cederman <cederman@gaisler.com>
5507 * config/sparc/sparc.cc (atomic_insn_for_leon3_p): Treat membar_storeload as atomic
5508 * config/sparc/sync.md (membar_storeload): Turn into named insn
5509 and add GR712RC errata workaround.
5510 (membar_v8): Add GR712RC errata workaround.
5512 2024-01-16 Andreas Larsson <andreas@gaisler.com>
5514 * config/sparc/sync.md (*membar_storeload_leon3): Remove
5515 (*membar_storeload): Enable for LEON
5517 2024-01-16 Jakub Jelinek <jakub@redhat.com>
5519 PR tree-optimization/113372
5520 PR middle-end/90348
5521 PR middle-end/110115
5522 PR middle-end/111422
5523 * cfgexpand.cc (add_scope_conflicts_2): New function.
5524 (add_scope_conflicts_1): Use it.
5526 2024-01-16 Georg-Johann Lay <avr@gjlay.de>
5528 * config/avr/avr-mcus.def (avr16eb14, avr16eb20, avr16eb28, avr16eb32)
5529 (avr16ea28, avr16ea32, avr16ea48, avr32ea28, avr32ea32, avr32ea48): Add.
5530 * doc/avr-mmcu.texi: Regenerate.
5532 2024-01-16 Feng Xue <fxue@os.amperecomputing.com>
5534 PR tree-optimization/113091
5535 * tree-vect-slp.cc (vect_slp_has_scalar_use): New function.
5536 (vect_bb_slp_mark_live_stmts): New parameter scalar_use_map, check
5537 scalar use with new function.
5538 (vect_bb_slp_mark_live_stmts): New function as entry to existing
5539 overriden functions with same name.
5540 (vect_slp_analyze_operations): Call new entry function to mark
5541 live statements.
5543 2024-01-16 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5545 PR target/113404
5546 * config/riscv/riscv.cc (riscv_override_options_internal): Report sorry
5547 for RVV in big-endian mode.
5549 2024-01-16 Yanzhang Wang <yanzhang.wang@intel.com>
5551 * config/riscv/riscv.cc (riscv_arg_has_vector): Delete.
5552 (riscv_pass_in_vector_p): Delete.
5553 (riscv_init_cumulative_args): Delete the checking.
5554 (riscv_get_arg_info): Delete the checking.
5555 (riscv_function_value): Delete the checking.
5556 * config/riscv/riscv.h: Delete the member for checking.
5558 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
5560 * doc/invoke.texi (AVR Options) [-mskip-bug]: Add documentation.
5562 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
5564 * config.gcc: Include riscv_bitmanip.h.
5565 * config/riscv/bitmanip.md: Changed mode form X to GPR in orcb and clmul pattern.
5566 * config/riscv/crypto.md: Changed mode form X to GPR in brev8 pattern.
5567 * config/riscv/riscv-builtins.cc (AVAIL): Adding new bitmanip builtins.
5568 (RISCV_BUILTIN_NO_PREFIX): New helper macro.
5569 * config/riscv/riscv-cmo.def (RISCV_BUILTIN): Add '_32'/'_64' postfix to builtins.
5570 * config/riscv/riscv-ftypes.def (2): New ftypes.
5571 * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): New builtins.
5572 (RISCV_BUILTIN_NO_PREFIX): Likewise.
5573 * config/riscv/riscv_bitmanip.h: New file.
5575 2024-01-15 Liao Shihua <shihua@iscas.ac.cn>
5577 * config.gcc: Include riscv_crypto.h.
5578 * config/riscv/riscv_crypto.h: New file.
5580 2024-01-15 Vladimir N. Makarov <vmakarov@redhat.com>
5582 PR middle-end/113354
5583 * lra-constraints.cc (curr_insn_transform): Spill pseudo only used
5584 in the insn if the corresponding operand does not require hard
5585 register anymore.
5587 2024-01-15 Georg-Johann Lay <avr@gjlay.de>
5589 PR target/107201
5590 * config/avr/avr.h (EXTRA_SPEC_FUNCTIONS): Add no-devlib, avr_no_devlib.
5591 * config/avr/driver-avr.cc (avr_no_devlib): New function.
5592 (avr_devicespecs_file): Use it to remove -nodevicelib from the
5593 options for cores only.
5594 * config/avr/avr-arch.h (avr_get_parch): New prototype.
5595 * config/avr/avr-devices.cc (avr_get_parch): New function.
5597 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5599 PR target/113247
5600 * config/riscv/riscv-protos.h (struct regmove_vector_cost): Add vector to scalar regmove.
5601 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Ditto.
5602 * config/riscv/riscv.cc (riscv_builtin_vectorization_cost): Adjust vec_construct cost.
5604 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5606 PR target/113281
5607 * config/riscv/riscv-vector-costs.cc (costs::adjust_vect_cost_per_loop): New function.
5608 (costs::finish_cost): Adjust cost for LOOP LEN with NITERS < VF.
5609 * config/riscv/riscv-vector-costs.h: New function.
5611 2024-01-15 Richard Biener <rguenther@suse.de>
5613 PR tree-optimization/113385
5614 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5615 First redirect, then split the exit edge.
5617 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5619 * config/riscv/riscv-vector-costs.cc (costs::analyze_loop_vinfo):
5620 Remove m_num_vector_iterations.
5621 * config/riscv/riscv-vector-costs.h: Ditto.
5623 2024-01-15 Andrew Pinski <quic_apinski@quicinc.com>
5625 PR target/113156
5626 * config/avr/avr.opt (-mdouble, -mlong-double): Add "Save" flag.
5627 (-mbranch-cost): Set "Optimization" flag.
5629 2024-01-15 Jakub Jelinek <jakub@redhat.com>
5631 PR tree-optimization/113370
5632 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Only
5633 set rem to prec % (2 * limb_prec) if m_upwards_2limb, otherwise
5634 set it to just prec % limb_prec.
5636 2024-01-15 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5638 PR target/113393
5639 * config/riscv/vector.md: Fix ternary attributes.
5641 2024-01-14 Georg-Johann Lay <avr@gjlay.de>
5643 PR target/112944
5644 * configure.ac [target=avr]: Check availability of emulations
5645 avrxmega2_flmap and avrxmega4_flmap, resulting in new config vars
5646 HAVE_LD_AVR_AVRXMEGA2_FLMAP and HAVE_LD_AVR_AVRXMEGA4_FLMAP.
5647 * configure: Regenerate.
5648 * config.in: Regenerate.
5649 * doc/invoke.texi (AVR Options): Document -mflmap, -mrodata-in-ram,
5650 __AVR_HAVE_FLMAP__, __AVR_RODATA_IN_RAM__.
5651 * config/avr/avr.opt (-mflmap, -mrodata-in-ram): New options.
5652 * config/avr/avr-arch.h (enum avr_device_specific_features):
5653 Add AVR_ISA_FLMAP.
5654 * config/avr/avr-mcus.def (AVR_MCU) [avr64*, avr128*]: Set isa flag
5655 AVR_ISA_FLMAP.
5656 * config/avr/avr.cc (avr_arch_index, avr_has_rodata_p): New vars.
5657 (avr_set_core_architecture): Set avr_arch_index.
5658 (have_avrxmega2_flmap, have_avrxmega4_flmap)
5659 (have_avrxmega3_rodata_in_flash): Set new static const bool according
5660 to configure results.
5661 (avr_rodata_in_flash_p): New function using them.
5662 (avr_asm_init_sections): Let readonly_data_section->unnamed.callback
5663 track avr_need_copy_data_p only if not avr_rodata_in_flash_p().
5664 (avr_asm_named_section): Track avr_has_rodata_p.
5665 (avr_file_end): Emit __do_copy_data also when avr_has_rodata_p
5666 and not avr_rodata_in_flash_p ().
5667 * config/avr/specs.h (CC1_SPEC): Add %(cc1_rodata_in_ram).
5668 (LINK_SPEC): Add %(link_rodata_in_ram).
5669 (LINK_ARCH_SPEC): Remove.
5670 * config/avr/gen-avr-mmcu-specs.cc (have_avrxmega3_rodata_in_flash)
5671 (have_avrxmega2_flmap, have_avrxmega4_flmap): Set new static
5672 const bool according to configure results.
5673 (diagnose_mrodata_in_ram): New function.
5674 (print_mcu): Generate specs with the following changes:
5675 <*cc1_misc, *asm_misc, *link_misc>: New specs so that we don't
5676 need to extend avr/specs.h each time we add a new bell or whistle.
5677 <*cc1_rodata_in_ram, *link_rodata_in_ram>: New specs to diagnose
5678 -m[no-]rodata-in-ram.
5679 <*cpp_rodata_in_ram>: New. Does -D__AVR_RODATA_IN_RAM__=0/1.
5680 <*cpp_mcu>: Add -D__AVR_AVR_FLMAP__ if it applies.
5681 <*cpp>: Add %(cpp_rodata_in_ram).
5682 <*link_arch>: Use emulation avrxmega2_flmap, avrxmega4_flmap as
5683 requested.
5684 <*self_spec>: Add -mflmap or %<mflmap as needed.
5686 2024-01-14 Jeff Law <jlaw@ventanamicro.com>
5688 * config/mips/mips.md (ior<mode>3_mips16_asmacro): Use SImode,
5689 not the GPR iterator. Adjust pattern name and mode attribute
5690 accordingly.
5692 2024-01-13 Jakub Jelinek <jakub@redhat.com>
5694 PR tree-optimization/113361
5695 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand_addr):
5696 Fix up determination of the type for > limb_prec constants.
5698 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
5700 * doc/extend.texi (AVR Named Address Spaces, Limitations and Caveats):
5701 Add web-link to the avr-gcc wiki.
5703 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
5705 * doc/extend.texi (AVR Variable Attributes) [address]: Remove
5706 documentation for a version without argument, which is not supported.
5708 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5710 * config/arm/arm_neon.h
5711 (vld1_u8_x4, vld1_u16_x4, vld1_u32_x4, vld1_u64_x4): New.
5712 (vld1_s8_x4, vld1_s16_x4, vld1_s32_x4, vld1_s64_x4): New.
5713 (vld1_f16_x4, vld1_f32_x4): New.
5714 (vld1_p8_x4, vld1_p16_x4, vld1_p64_x4): New.
5715 (vld1_bf16_x4): New.
5716 (vld1q_types_x4): Updated to use vld1q_x4
5717 from arm_neon_builtins.def
5718 * config/arm/arm_neon_builtins.def
5719 (vld1_x4): Updated entries.
5720 (vld1q_x4): New entries, but comes from the old vld1_x4
5721 * config/arm/neon.md
5722 (neon_vld1q_x4<mode>): Updated from neon_vld1_x4<mode>.
5724 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5726 * config/arm/arm_neon.h
5727 (vld1_u8_x3, vld1_u16_x3, vld1_u32_x3, vld1_u64_x3): New.
5728 (vld1_s8_x3, vld1_s16_x3, vld1_s32_x3, vld1_s64_x3): New.
5729 (vld1_f16_x3, vld1_f32_x3): New.
5730 (vld1_p8_x3, vld1_p16_x3, vld1_p64_x3): New.
5731 (vld1_bf16_x3): New.
5732 (vld1q_types_x3): Updated to use vld1q_x3 from
5733 arm_neon_builtins.def
5734 * config/arm/arm_neon_builtins.def
5735 (vld1_x3): Updated entries.
5736 (vld1q_x3): New entries, but comes from the old vld1_x2
5737 * config/arm/neon.md
5738 (neon_vld1q_x3<mode>): Updated from neon_vld1_x3<mode>.
5740 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5742 * config/arm/arm_neon.h
5743 (vld1_u8_x2, vld1_u16_x2, vld1_u32_x2, vld1_u64_x2): New.
5744 (vld1_s8_x2, vld1_s16_x2, vld1_s32_x2, vld1_s64_x2): New.
5745 (vld1_f16_x2, vld1_f32_x2): New.
5746 (vld1_p8_x2, vld1_p16_x2, vld1_p64_x2): New.
5747 (vld1_bf16_x2): New.
5748 (vld1q_types_x2): Updated to use vld1q_x2 from
5749 arm_neon_builtins.def
5750 * config/arm/arm_neon_builtins.def
5751 (vld1_x2): Updated entries.
5752 (vld1q_x2): New entries, but comes from the old vld1_x2
5753 * config/arm/neon.md
5754 (neon_vld1<VMEMX2_q>_x2<VDQX:mode>): Updated from
5755 neon_vld1_x2<mode>.
5757 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5759 * config/arm/arm_neon.h
5760 (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New.
5761 (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New.
5762 (vst1q_f16_x4, vst1q_f32_x4): New.
5763 (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New.
5764 (vst1q_bf16_x4): New.
5765 * config/arm/arm_neon_builtins.def (vst1q_x4): New entries.
5766 * config/arm/neon.md
5767 (neon_vst1q_x4<mode>): New.
5768 (neon_vst1x4qa<mode>, neon_vst1x4qb<mode>): New.
5769 * config/arm/unspecs.md
5770 (UNSPEC_VST1X4A, UNSPEC_VST1X4B): New.
5772 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5774 * config/arm/arm_neon.h
5775 (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New.
5776 (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New.
5777 (vst1q_f16_x3, vst1q_f32_x3): New.
5778 (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New.
5779 (vst1q_bf16_x3): New.
5780 * config/arm/arm_neon_builtins.def (vst1q_x3): New entries.
5781 * config/arm/neon.md
5782 (neon_vst1q_x3<mode>): New.
5783 (neon_vld1x3qa<mode>, neon_vst1x3qb<mode>): New.
5784 * config/arm/unspecs.md
5785 (UNSPEC_VST1X3A, UNSPEC_VST1X3B): New.
5787 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5789 * config/arm/arm_neon.h
5790 (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x2): New.
5791 (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New.
5792 (vst1q_f16_x2, vst1q_f32_x2): New.
5793 (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New.
5794 (vst1q_bf16_x2): New.
5795 * config/arm/arm_neon_builtins.def (vst1<_x2): New entries.
5796 * config/arm/neon.md
5797 (neon_vst1<VMEMX2_q>_x2<VDQX:mode>): Updated from
5798 neon_vst1_x2<mode>.
5799 * config/arm/iterators.md
5800 (VMEMX2): New mode iterator.
5801 (VMEMX2_q): New mode attribute.
5803 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5805 * config/arm/arm_neon.h
5806 (vst1_u8_x4, vst1_u16_x4, vst1_u32_x4, vst1_u64_x4): New.
5807 (vst1_s8_x4, vst1_s16_x4, vst1_s32_x4, vst1_s64_x4): New.
5808 (vst1_f16_x4, vst1_f32_x4): New.
5809 (vst1_p8_x4, vst1_p16_x4, vst1_p64_x4): New.
5810 (vst1_bf16_x4): New.
5811 * config/arm/arm_neon_builtins.def (vst1_x4): New entries.
5812 * config/arm/neon.md (vst1_x4<mode>): New.
5814 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5816 * config/arm/arm_neon.h
5817 (vst1_u8_x3, vst1_u16_x3, vst1_u32_x3, vst1_u64_x3): New.
5818 (vst1_s8_x3, vst1_s16_x3, vst1_s32_x3, vst1_s64_x3): New.
5819 (vst1_f16_x3, vst1_f32_x3): New.
5820 (vst1_p8_x3, vst1_p16_x3, vst1_p64_x3): New.
5821 (vst1_bf16_x3): New.
5822 * config/arm/arm_neon_builtins.def (vst1_x3): New entries.
5823 * config/arm/neon.md (vst1_x3<mode>): New.
5825 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5827 * config/arm/arm_neon.h
5828 (vst1_u8_x2, vst1_u16_x2, vst1_u32_x2, vst1_u64_x2): New.
5829 (vst1_s8_x2, vst1_s16_x2, vst1_s32_x2, vst1_s64_x2): New.
5830 (vst1_f16_x2, vst1_f32_x2): New.
5831 (vst1_p8_x2, vst1_p16_x2, vst1_p64_x2): New.
5832 (vst1_bf16_x2): New.
5833 * config/arm/arm_neon_builtins.def (vst1_x2): New entries.
5834 * config/arm/neon.md (vst1_x2<mode>): New.
5836 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5838 * config/arm/arm_neon.h
5839 (vld1q_u8_x4, vld1q_u16_x4, vld1q_u32_x4, vld1q_u64_x4): New.
5840 (vld1q_s8_x4, vld1q_s16_x4, vld1q_s32_x4, vld1q_s64_x4): New.
5841 (vld1q_f16_x4, vld1q_f32_x4): New.
5842 (vld1q_p8_x4, vld1q_p16_x4, vld1q_p64_x4): New.
5843 (vld1q_bf16_x4): New.
5844 * config/arm/arm_neon_builtins.def (vld1_x4): New entries.
5845 * config/arm/neon.md
5846 (neon_vld1_x4<mode>): New.
5847 (neon_vld1x4qa<mode>, neon_vld1x4qb<mode>): New
5848 * config/arm/unspecs.md
5849 (UNSPEC_VLD1X4A, UNSPEC_VLD1X4B): New.
5851 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5853 * config/arm/arm_neon.h
5854 (vld1q_u8_x3, vld1q_u16_x3, vld1q_u32_x3, vld1q_u64_x3): New.
5855 (vld1q_s8_x3, vld1q_s16_x3, vld1q_s32_x3, vld1q_s64_x3): New.
5856 (vld1q_f16_x3, vld1q_f32_x3): New.
5857 (vld1q_p8_x3, vld1q_p16_x3, vld1q_p64_x3): New.
5858 (vld1q_bf16_x3): New.
5859 * config/arm/arm_neon_builtins.def (vld1_x3): New entries.
5860 * config/arm/neon.md
5861 (neon_vld1_x3<mode>): New.
5862 (neon_vld1x3qa<mode>, neon_vld1x3qb<mode>): New.
5863 * config/arm/unspecs.md
5864 (UNSPEC_VLD1X3A, UNSPEC_VLD1X3B): New.
5866 2024-01-12 Ezra Sitorus <ezra.sitorus@arm.com>
5868 * config/arm/arm_neon.h
5869 (vld1q_u8_x2, vld1q_u16_x2, vld1q_u32_x2, vld1q_u64_x2): New.
5870 (vld1q_s8_x2, vld1q_s16_x2, vld1q_s32_x2, vld1q_s64_x2): New.
5871 (vld1q_f16_x2, vld1q_f32_x2): New.
5872 (vld1q_p8_x2, vld1q_p16_x2, vld1q_p64_x2): New.
5873 (vld1q_bf16_x2): New.
5874 * config/arm/arm_neon_builtins.def (vld1_x2): New entries.
5875 * config/arm/neon.md (vld1_x2<mode>): New.
5877 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5879 PR tree-optimization/113287
5880 * doc/sourcebuild.texi (check_effective_target_bitint65535): New.
5882 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5884 * tree-vect-loop-manip.cc (vect_loop_versioning): Replace single_exit.
5885 * tree-vect-loop.cc (vect_transform_loop): Likewise.
5887 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5889 PR tree-optimization/113178
5890 * tree-vect-loop.cc (vect_create_epilog_for_reduction): Fill in all
5891 alternate exits.
5893 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5895 PR tree-optimization/113237
5896 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg): Use
5897 existing LCSSA variable for exit when all exits are early break.
5899 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5901 PR tree-optimization/113137
5902 PR tree-optimization/113136
5903 PR tree-optimization/113172
5904 PR tree-optimization/113178
5905 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
5906 Maintain PHIs on inverted loops.
5907 (vect_do_peeling): Maintain virtual PHIs on inverted loops.
5908 * tree-vect-loop.cc (vec_init_loop_exit_info): Pick exit closes to
5909 latch.
5910 (vect_create_loop_vinfo): Record all conds instead of only alt ones.
5912 2024-01-12 Tamar Christina <tamar.christina@arm.com>
5914 PR tree-optimization/113135
5915 * tree-vect-data-refs.cc (vect_analyze_early_break_dependences): Rework
5916 dependency analysis.
5918 2024-01-12 Iain Sandoe <iain@sandoe.co.uk>
5920 * config/rs6000/host-darwin.cc (segv_handler): Use the revised
5921 diagnostics class member name for abort of error.
5923 2024-01-12 Georg-Johann Lay <avr@gjlay.de>
5925 * config/avr/avr.cc (avr_handle_addr_attribute): Move "..." from
5926 format string to %s argument.
5928 2024-01-12 John David Anglin <danglin@gcc.gnu.org>
5929 Jakub Jelinek <jakub@redhat.com>
5931 PR middle-end/113182
5932 * varasm.cc (process_pending_assemble_externals,
5933 assemble_external_libcall): Use targetm.strip_name_encoding
5934 before calling get_identifier.
5936 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
5938 PR target/113196
5939 * config/aarch64/aarch64.h (machine_function::advsimd_zero_insn):
5940 New member variable.
5941 * config/aarch64/aarch64-protos.h (aarch64_split_simd_shift_p):
5942 Declare.
5943 * config/aarch64/iterators.md (Vnarrowq2): New mode attribute.
5944 * config/aarch64/aarch64-simd.md
5945 (vec_unpacku_hi_<mode>, vec_unpacks_hi_<mode>): Recombine into...
5946 (vec_unpack<su>_hi_<mode>): ...this. Move the generation of
5947 zip2 for zero-extends to...
5948 (aarch64_simd_vec_unpack<su>_hi_<mode>): ...a split of this
5949 instruction. Fix big-endian handling.
5950 (vec_unpacku_lo_<mode>, vec_unpacks_lo_<mode>): Recombine into...
5951 (vec_unpack<su>_lo_<mode>): ...this. Move the generation of
5952 zip1 for zero-extends to...
5953 (<optab><Vnarrowq><mode>2): ...a split of this instruction.
5954 Fix big-endian handling.
5955 (*aarch64_zip1_uxtl): New pattern.
5956 (aarch64_usubw<mode>_lo_zip, aarch64_uaddw<mode>_lo_zip): Delete
5957 (aarch64_usubw<mode>_hi_zip, aarch64_uaddw<mode>_hi_zip): Likewise.
5958 * config/aarch64/aarch64.cc (aarch64_get_shareable_reg): New function.
5959 (aarch64_gen_shareable_zero): Use it.
5960 (aarch64_split_simd_shift_p): New function.
5962 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
5964 * emit-rtl.h (rtl_data::x_function_beg_note): New member variable.
5965 (function_beg_insn): New macro.
5966 * function.cc (expand_function_start): Initialize function_beg_insn.
5968 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
5970 PR target/112989
5971 * config/aarch64/aarch64-sve-builtins.h
5972 (function_builder::m_overload_names): Replace with...
5973 * config/aarch64/aarch64-sve-builtins.cc (overload_names): ...this
5974 new global.
5975 (add_overloaded_function): Update accordingly, using get_identifier
5976 to get a GGC-friendly record of the name.
5978 2024-01-12 Richard Sandiford <richard.sandiford@arm.com>
5980 PR target/112989
5981 * config/aarch64/aarch64-sve-builtins.def: Don't include
5982 aarch64-sve-builtins-sme.def.
5983 (DEF_SME_ZA_FUNCTION_GS, DEF_SME_ZA_FUNCTION): Move to...
5984 * config/aarch64/aarch64-sve-builtins-sme.def: ...here.
5985 (DEF_SME_FUNCTION): New macro. Use it and DEF_SME_FUNCTION_GS
5986 instead of DEF_SVE_*. Add AARCH64_FL_SME to anything that
5987 requires AARCH64_FL_SME2.
5988 * config/aarch64/aarch64-sve-builtins-sve2.def: Make same
5989 AARCH64_FL_SME adjustment here.
5990 * config/aarch64/aarch64-sve-builtins.cc (function_groups): Don't
5991 include SME intrinsics.
5992 (sme_function_groups): New array.
5993 (handle_arm_sve_h): Remove check for AARCH64_FL_SME.
5994 (handle_arm_sme_h): Use sme_function_groups instead of function_groups.
5996 2024-01-12 Juzhe-Zhong <juzhe.zhong@rivai.ai>
5998 PR target/113281
5999 * config/riscv/riscv-protos.h (struct regmove_vector_cost): New struct.
6000 (struct cpu_vector_cost): Add regmove struct.
6001 (get_vector_costs): Export as global.
6002 * config/riscv/riscv-vector-costs.cc (adjust_stmt_cost): Adjust scalar_to_vec cost.
6003 (costs::add_stmt_cost): Ditto.
6004 * config/riscv/riscv.cc (get_common_costs): Export global function.
6006 2024-01-12 Jakub Jelinek <jakub@redhat.com>
6008 PR tree-optimization/113334
6009 * gimple-lower-bitint.cc (bitint_large_huge::handle_operand): Use
6010 wi::neg_p (wi::to_wide (op)) instead of tree_int_cst_sgn (op) < 0
6011 to determine if number should be extended by all ones rather than zero
6012 extended.
6014 2024-01-12 Jakub Jelinek <jakub@redhat.com>
6016 PR tree-optimization/113330
6017 * tree-sra.cc (create_access): Punt for BITINT_TYPE accesses with
6018 too large size.
6020 2024-01-12 Jakub Jelinek <jakub@redhat.com>
6022 PR tree-optimization/113323
6023 * gimple-lower-bitint.cc (bitint_dom_walker::before_dom_children): Fix
6024 check for lhs being large/huge _BitInt not in m_names.
6026 2024-01-12 Jakub Jelinek <jakub@redhat.com>
6028 PR tree-optimization/113316
6029 * gimple-lower-bitint.cc (bitint_large_huge::lower_call): Handle
6030 uninitialized large/huge _BitInt arguments to calls.
6032 2024-01-12 Jakub Jelinek <jakub@redhat.com>
6034 * gimple-lower-bitint.cc (mergeable_op): Instead of comparing
6035 TYPE_SIZE (t) of large/huge BITINT_TYPEs, compare
6036 CEIL (TYPE_PRECISION (t), limb_prec).
6037 (bitint_large_huge::handle_cast): Likewise.
6039 2024-01-12 Ilya Leoshkevich <iii@linux.ibm.com>
6041 PR sanitizer/113284
6042 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
6043 Use assemble_function_label_final () for Power ELF V1 ABI.
6044 * output.h (assemble_function_label_final): New function.
6045 * varasm.cc (assemble_function_label_raw): Use
6046 assemble_function_label_final ().
6047 (assemble_function_label_final): New function.
6049 2024-01-12 Richard Biener <rguenther@suse.de>
6051 PR middle-end/113344
6052 * match.pd ((double)float CMP (double)float -> float CMP float):
6053 Perform result type check only for vectors.
6054 * fold-const.cc (fold_binary_loc): Likewise.
6056 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
6058 * config/i386/sse.md (sdot_prod<mode>): Remove redundant SET.
6059 (usdot_prod<mode>): Ditto.
6060 (sdot_prod<mode>): Ditto.
6061 (udot_prod<mode>): Ditto.
6063 2024-01-12 Haochen Jiang <haochen.jiang@intel.com>
6065 PR target/113288
6066 * config/i386/i386-c.cc (ix86_target_macros_internal):
6067 Add __AVX10_1__, __AVX10_1_256__ and __AVX10_1_512__.
6069 2024-01-12 Richard Biener <rguenther@suse.de>
6071 PR target/112280
6072 * config/s390/s390.cc (expand_perm_as_a_vlbr_vstbr_candidate):
6073 Do not generate code when d.testing_p.
6075 2024-01-12 liuhongt <hongtao.liu@intel.com>
6077 PR target/113039
6078 * doc/invoke.texi (fcf-protection=): Update documents.
6080 2024-01-12 Pan Li <pan2.li@intel.com>
6082 * config/riscv/riscv.cc (riscv_v_ext_mode_p): Update the
6083 comments of predicate func riscv_v_ext_mode_p.
6085 2024-01-12 Feng Wang <wangfeng@eswincomputing.com>
6087 * config/riscv/riscv-vector-builtins.def (vfloat16m8_t):
6088 Modify ABI-name length of vfloat16m8_t
6090 2024-01-12 Li Wei <liwei@loongson.cn>
6092 * config/loongarch/loongarch.cc (loongarch_expand_conditional_move):
6093 Adjust.
6095 2024-01-12 Li Wei <liwei@loongson.cn>
6097 * config/loongarch/loongarch.md (add<mode>3): Removed.
6098 (*addsi3): New.
6099 (addsi3): Ditto.
6100 (adddi3): Ditto.
6101 (*addsi3_extended): Removed.
6102 (addsi3_extended): New.
6104 2024-01-11 Jin Ma <jinma@linux.alibaba.com>
6106 * config/riscv/thead.md: Add limits for splits.
6108 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
6110 PR middle-end/113322
6111 * expr.cc (do_store_flag): Don't try single bit tests with
6112 comparison on vector types.
6114 2024-01-11 Andrew Pinski <quic_apinski@quicinc.com>
6116 PR tree-optimization/113301
6117 * match.pd (`1/x`): Delay signed case until late.
6119 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
6121 * doc/invoke.texi (AVR Options): Move -mrmw, -mn-flash, -mshort-calls
6122 and -msp8 to...
6123 (AVR Internal Options): ...this new @subsubsection.
6125 2024-01-11 Vladimir N. Makarov <vmakarov@redhat.com>
6127 PR rtl-optimization/112918
6128 * lra-constraints.cc (SMALL_REGISTER_CLASS_P): Move before in_class_p.
6129 (in_class_p): Restrict condition for narrowing class in case of
6130 allow_all_reload_class_changes_p.
6131 (process_alt_operands): Try to match operand without and with
6132 narrowing reg class. Discourage narrowing the class. Finish insn
6133 matching only if there is no class narrowing.
6134 (curr_insn_transform): Pass true to in_class_p for reg operand win.
6136 2024-01-11 Richard Biener <rguenther@suse.de>
6138 PR tree-optimization/112505
6139 * tree-vect-loop.cc (vectorizable_induction): Reject
6140 bit-precision induction.
6142 2024-01-11 Richard Biener <rguenther@suse.de>
6144 PR tree-optimization/113126
6145 * match.pd ((double)float CMP (double)float -> float CMP float):
6146 Make sure the boolean type is the same.
6147 * fold-const.cc (fold_binary_loc): Likewise.
6149 2024-01-11 Richard Biener <rguenther@suse.de>
6151 PR tree-optimization/112636
6152 * tree-ssa-loop-ch.cc (ch_base::copy_headers): Call
6153 estimate_numbers_of_iterations before querying
6154 get_max_loop_iterations_int.
6155 (pass_ch::execute): Initialize SCEV and loops appropriately.
6157 2024-01-11 Georg-Johann Lay <avr@gjlay.de>
6159 * config/avr/avr-devices.cc (avr_texinfo): Adjust documentation for
6160 Reduced Tiny.
6161 * config/avr/gen-avr-mmcu-texi.cc (main): Add @anchor for each core.
6162 * doc/extend.texi (AVR Variable Attributes): Improve documentation
6163 of io, io_low and address attributes.
6164 * doc/invoke.texi (AVR Options): Add some anchors for external refs.
6165 * doc/avr-mmcu.texi: Rebuild.
6167 2024-01-11 Yang Yujie <yangyujie@loongson.cn>
6169 PR target/113233
6170 * config/loongarch/genopts/loongarch.opt.in: Mark options with
6171 the "Save" property.
6172 * config/loongarch/loongarch.opt: Same.
6173 * config/loongarch/loongarch-opts.cc: Refresh -mcmodel= state
6174 according to la_target.
6175 * config/loongarch/loongarch.cc: Implement TARGET_OPTION_{SAVE,
6176 RESTORE} for the la_target structure; Rename option conditions
6177 to have the same "la_" prefix.
6178 * config/loongarch/loongarch.h: Same.
6180 2024-01-11 Pan Li <pan2.li@intel.com>
6182 * loop-unroll.cc (insert_var_expansion_initialization): Leverage
6183 MODE_HAS_SIGNED_ZEROS for expansion variable initialization.
6185 2024-01-11 Alex Coplan <alex.coplan@arm.com>
6187 PR target/113077
6188 * config/aarch64/aarch64-ldp-fusion.cc (filter_notes): Add
6189 fr_expr param to extract REG_FRAME_RELATED_EXPR notes.
6190 (combine_reg_notes): Handle REG_FRAME_RELATED_EXPR notes, and
6191 synthesize these if needed. Update caller ...
6192 (ldp_bb_info::fuse_pair): ... here.
6193 (ldp_bb_info::try_fuse_pair): Punt if either insn has writeback
6194 and either insn is frame-related.
6195 (find_trailing_add): Punt on frame-related insns.
6196 * config/aarch64/aarch64.cc (aarch64_save_callee_saves): Use
6197 REG_FRAME_RELATED_EXPR instead of REG_CFA_OFFSET.
6199 2024-01-11 YunQiang Su <syq@gcc.gnu.org>
6201 * config/mips/mips.cc (mips_start_function_definition):
6202 Add ATTRIBUTE_UNUSED.
6204 2024-01-11 Richard Biener <rguenther@suse.de>
6206 PR middle-end/112740
6207 * expr.cc (store_constructor): Check the integer vector
6208 mask has a single bit per element before using sign-extension
6209 to expand an uniform vector.
6211 2024-01-11 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6213 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): VLA
6214 preempt VLS on unknown NITERS loop.
6216 2024-01-11 Haochen Jiang <haochen.jiang@intel.com>
6218 * doc/invoke.texi: Add -mevex512.
6220 2024-01-11 Lulu Cheng <chenglulu@loongson.cn>
6222 * config/loongarch/loongarch.md (one_cmpl<mode>2): Replace GPR with X.
6223 (*nor<mode>3): Likewise.
6224 (nor<mode>3): Likewise.
6225 (*negsi2_extended): New template.
6226 (*<optab>si3_internal): Likewise.
6227 (*one_cmplsi2_internal): Likewise.
6228 (*norsi3_internal): Likewise.
6229 (*<optab>nsi_internal): Likewise.
6230 (bytepick_w_<bytepick_imm>_extend): Modify this template according to the
6231 modified bit operation to make the optimization work.
6233 2024-01-11 liuhongt <hongtao.liu@intel.com>
6235 PR target/104401
6236 * match.pd (VEC_COND_EXPR: A < B ? A : B -> MIN_EXPR): New patten match.
6238 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6240 * config/riscv/riscv.cc (get_common_costs): Switch RVV cost model.
6241 (get_vector_costs): Ditto.
6242 (riscv_builtin_vectorization_cost): Ditto.
6244 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6246 * config/riscv/riscv-vector-costs.cc (costs::better_main_loop_than_p): Minior tweak.
6248 2024-01-10 Antoni Boucher <bouanto@zoho.com>
6250 PR jit/111396
6251 * ipa-fnsummary.cc (ipa_fnsummary_cc_finalize): Call
6252 ipa_free_size_summary.
6253 * ipa-icf.cc (ipa_icf_cc_finalize): New function.
6254 * ipa-profile.cc (ipa_profile_cc_finalize): New function.
6255 * ipa-prop.cc (ipa_prop_cc_finalize): New function.
6256 * ipa-prop.h (ipa_prop_cc_finalize): New function.
6257 * ipa-sra.cc (ipa_sra_cc_finalize): New function.
6258 * ipa-utils.h (ipa_profile_cc_finalize, ipa_icf_cc_finalize,
6259 ipa_sra_cc_finalize): New functions.
6260 * toplev.cc (toplev::finalize): Call ipa_icf_cc_finalize,
6261 ipa_prop_cc_finalize, ipa_profile_cc_finalize and
6262 ipa_sra_cc_finalize
6263 Include ipa-utils.h.
6265 2024-01-10 Jin Ma <jinma@linux.alibaba.com>
6267 * config/riscv/riscv-protos.h (th_int_get_mask): New prototype.
6268 (th_int_get_save_adjustment): Likewise.
6269 (th_int_adjust_cfi_prologue): Likewise.
6270 * config/riscv/riscv.cc (BITSET_P): Moved away from here.
6271 (TH_INT_INTERRUPT): New macro.
6272 (riscv_expand_prologue): Add the processing of XTheadInt.
6273 (riscv_expand_epilogue): Likewise.
6274 * config/riscv/riscv.h (BITSET_P): Moved to here.
6275 * config/riscv/riscv.md: New unspec.
6276 * config/riscv/thead.cc (th_int_get_mask): New function.
6277 (th_int_get_save_adjustment): Likewise.
6278 (th_int_adjust_cfi_prologue): Likewise.
6279 * config/riscv/thead.md (th_int_push): New pattern.
6280 (th_int_pop): new pattern.
6282 2024-01-10 Tamar Christina <tamar.christina@arm.com>
6284 PR tree-optimization/112468
6285 * doc/sourcebuild.texi: Document ifn_copysign.
6286 * match.pd: Only apply transformation if target supports the IFN.
6288 2024-01-10 Andrew Pinski <quic_apinski@quicinc.com>
6290 PR tree-optimization/112581
6291 * gimple-if-to-switch.cc (pass_if_to_switch::execute): Call
6292 mark_ssa_maybe_undefs.
6293 * tree-ssa-reassoc.cc (can_reassociate_op_p): Uninitialized
6294 variables can not be reassociated.
6295 (init_range_entry): Check for uninitialized variables too.
6296 (init_reassoc): Call mark_ssa_maybe_undefs.
6298 2024-01-10 Maciej W. Rozycki <macro@embecosm.com>
6300 * config/riscv/riscv.cc (riscv_noce_conversion_profitable_p):
6301 Also handle sign extension.
6303 2024-01-10 Alex Coplan <alex.coplan@arm.com>
6305 * config/aarch64/aarch64.opt (-mearly-ldp-fusion): Set default
6306 to 0.
6307 (-mlate-ldp-fusion): Likewise.
6309 2024-01-10 Tamar Christina <tamar.christina@arm.com>
6311 PR tree-optimization/113287
6312 * tree-vect-stmts.cc (vectorizable_early_exit): Check the flags on edge
6313 instead of using BRANCH_EDGE to determine true edge.
6315 2024-01-10 Richard Biener <rguenther@suse.de>
6317 PR tree-optimization/113078
6318 * tree-vect-loop.cc (check_reduction_path): Canonicalize
6319 .COND_SUB to .COND_ADD.
6321 2024-01-10 David Malcolm <dmalcolm@redhat.com>
6323 * gcc-urlifier.cc (gcc_urlifier::get_url_suffix_for_option):
6324 Handle prefix mappings before calling find_opt.
6325 (selftest::gcc_urlifier_cc_tests): Add example of urlifying a
6326 "-fno-"-prefixed command-line option.
6327 * opts-common.cc (get_option_prefix_remapping): New.
6328 * opts.h (get_option_prefix_remapping): New decl.
6330 2024-01-10 David Malcolm <dmalcolm@redhat.com>
6332 * diagnostic.cc (diagnostic_context::report_diagnostic): Pass
6333 m_urlifier to pp_output_formatted_text.
6334 * pretty-print.cc: Add #define of INCLUDE_VECTOR.
6335 (obstack_append_string): New overload, taking a length.
6336 (urlify_quoted_string): Pass in an obstack ptr, rather than using
6337 that of the pp's buffer. Generalize to handle trailing text in
6338 the buffer beyond the run of quoted text.
6339 (class quoting_info): New.
6340 (on_begin_quote): New.
6341 (on_end_quote): New.
6342 (pp_format): Refactor phase 1 and phase 2 quoting support, moving
6343 it to calls to on_begin_quote and on_end_quote.
6344 (struct auto_obstack): New.
6345 (quoting_info::handle_phase_3): New.
6346 (pp_output_formatted_text): Add urlifier param. Use it if there
6347 is deferred urlification. Delete m_quotes.
6348 (selftest::pp_printf_with_urlifier): Pass urlifier to
6349 pp_output_formatted_text.
6350 (selftest::test_urlification): Update results for the existing
6351 case of quoted text stradding chunks; add more such test cases.
6352 * pretty-print.h (class quoting_info): New forward decl.
6353 (chunk_info::m_quotes): New field.
6354 (pp_output_formatted_text): Add optional urlifier param.
6356 2024-01-10 David Malcolm <dmalcolm@redhat.com>
6358 * pretty-print.cc (selftest::test_pp_format): Add selftest
6359 coverage for numbered args.
6361 2024-01-10 Tamar Christina <tamar.christina@arm.com>
6363 PR tree-optimization/113144
6364 PR tree-optimization/113145
6365 * tree-vect-loop-manip.cc (slpeel_tree_duplicate_loop_to_edge_cfg):
6366 Update all BB that the original exits dominated.
6368 2024-01-10 Eric Botcazou <ebotcazou@adacore.com>
6370 * dwarf2out.cc (modified_type_die): Extend the support of reverse
6371 storage order to enumeration types if -gstrict-dwarf is not passed.
6372 (gen_enumeration_type_die): Add REVERSE parameter and generate the
6373 DIE immediately after the existing one if it is true.
6374 (gen_tagged_type_die): Add REVERSE parameter and pass it in the
6375 call to gen_enumeration_type_die.
6376 (gen_type_die_with_usage): Add REVERSE parameter and pass it in the
6377 first recursive call as well as the call to gen_tagged_type_die.
6378 (gen_type_die): Add REVERSE parameter and pass it in the call to
6379 gen_type_die_with_usage.
6381 2024-01-10 Jakub Jelinek <jakub@redhat.com>
6383 PR tree-optimization/113120
6384 * tree-sra.cc (analyze_access_subtree): For BITINT_TYPE
6385 with root->size TYPE_PRECISION don't build anything new.
6386 Otherwise, if root->type is a BITINT_TYPE, use build_bitint_type
6387 rather than build_nonstandard_integer_type.
6389 2024-01-10 Hongyu Wang <hongyu.wang@intel.com>
6391 * config/i386/i386.opt: Adjust document.
6392 * doc/invoke.texi: Add description for
6393 -mapx-inline-asm-use-gpr32.
6395 2024-01-10 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6397 * config/riscv/autovec.md (<u>avg<v_double_trunc>3_floor): Remove.
6398 (avg<v_double_trunc>3_floor): New pattern.
6399 (<u>avg<v_double_trunc>3_ceil): Remove.
6400 (avg<v_double_trunc>3_ceil): New pattern.
6401 (uavg<mode>3_floor): Ditto.
6402 (uavg<mode>3_ceil): Ditto.
6403 * config/riscv/riscv-protos.h (enum insn_flags): Add for average addition.
6404 (enum insn_type): Ditto.
6405 * config/riscv/riscv-v.cc: Ditto.
6406 * config/riscv/vector-iterators.md (ashiftrt): Remove.
6407 (ASHIFTRT): Ditto.
6408 * config/riscv/vector.md: Add VLS modes.
6410 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
6412 PR target/111480
6413 * config/rs6000/vsx.md (VCZLSBB): New int iterator.
6414 (vczlsbb_char): New int attribute.
6415 (vclzlsbb_<mode>, vctzlsbb_<mode>): Merge to ...
6416 (vc<vczlsbb_char>zlsbb_<mode>): ... this.
6417 (*vctzlsbb_zext_<mode>): Rename to ...
6418 (*vc<vczlsbb_char>zlsbb_zext_<mode>): ... this, and extend it to
6419 cover vclzlsbb.
6421 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
6423 PR target/112606
6424 * config/rs6000/rs6000.md (copysign<mode>3 IEEE128): Change predicate
6425 of the last argument from altivec_register_operand to any_operand. If
6426 operands[2] is CONST_DOUBLE, emit abs or neg abs depending on its sign
6427 otherwise if it doesn't satisfy altivec_register_operand, force it to
6428 REG using copy_to_mode_reg.
6430 2024-01-10 Kewen Lin <linkw@linux.ibm.com>
6432 PR middle-end/113100
6433 * builtins.cc (expand_builtin_stack_address): Guard stack point
6434 adjustment with SPARC_STACK_BOUNDARY_HACK.
6436 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
6438 * config/loongarch/genopts/loongarch-strings: Remove explicit-reloc
6439 argument string definitions.
6440 * config/loongarch/loongarch-str.h: Same.
6441 * config/loongarch/genopts/loongarch.opt.in: Mark -m[no-]explicit-relocs
6442 as aliases to -mexplicit-relocs={always,none}
6443 * config/loongarch/loongarch.opt: Regenerate.
6444 * config/loongarch/loongarch.cc: Same.
6446 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
6448 * config/loongarch/loongarch-def.h: Define constants with
6449 enums instead of Macros.
6451 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
6453 * config/loongarch/genopts/loongarch-strings: Rename.
6454 * config/loongarch/genopts/loongarch.opt.in: Same.
6455 * config/loongarch/loongarch-cpu.cc: Same.
6456 * config/loongarch/loongarch-def.cc: Same.
6457 * config/loongarch/loongarch-def.h: Same.
6458 * config/loongarch/loongarch-opts.cc: Same.
6459 * config/loongarch/loongarch-opts.h: Same.
6460 * config/loongarch/loongarch-str.h: Same.
6461 * config/loongarch/loongarch.opt: Same.
6463 2024-01-10 Yang Yujie <yangyujie@loongson.cn>
6465 * config/loongarch/genopts/genstr.sh: Prepend the isa_evolution
6466 variable with the common la_ prefix.
6467 * config/loongarch/genopts/loongarch.opt.in: Mark ISA evolution
6468 flags as saved using TargetVariable.
6469 * config/loongarch/loongarch.opt: Same.
6470 * config/loongarch/loongarch-def.h: Define evolution_set to
6471 mark changes to the -march default.
6472 * config/loongarch/loongarch-driver.cc: Same.
6473 * config/loongarch/loongarch-opts.cc: Same.
6474 * config/loongarch/loongarch-opts.h: Define and use ISA evolution
6475 conditions around the la_target structure.
6476 * config/loongarch/loongarch.cc: Same.
6477 * config/loongarch/loongarch.md: Same.
6478 * config/loongarch/loongarch-builtins.cc: Same.
6479 * config/loongarch/loongarch-c.cc: Same.
6480 * config/loongarch/lasx.md: Same.
6481 * config/loongarch/lsx.md: Same.
6482 * config/loongarch/sync.md: Same.
6484 2024-01-09 Jeff Law <jlaw@ventanamicro.com>
6486 * config/epiphany/constraints.md (Car): Allow -1024..1023, no more,
6487 no less.
6489 2024-01-09 Richard Sandiford <richard.sandiford@arm.com>
6491 * config/mn10300/mn10300.md (subdi3_degenerate): Add isa attribute.
6493 2024-01-09 Tamar Christina <tamar.christina@arm.com>
6495 * tree-vect-loop.cc (vectorizable_live_operation_1): Drop unused
6496 restart_loop.
6497 (vectorizable_live_operation): Likewise.
6499 2024-01-09 Tamar Christina <tamar.christina@arm.com>
6501 PR tree-optimization/113199
6502 * tree-vect-loop.cc (vectorizable_live_operation_1): Use
6503 BIT_FIELD_REF.
6505 2024-01-09 Jakub Jelinek <jakub@redhat.com>
6507 PR target/113270
6508 * config.gcc (aarch64*-*-*): Add aarch64-builtins.h to target_gtfiles.
6509 * config/aarch64/aarch64-builtins.cc (aarch64_simd_types): Add extern
6510 GTY(()) declaration before the definition, drop GTY(()) drom the
6511 definition.
6513 2024-01-09 Richard Biener <rguenther@suse.de>
6515 PR tree-optimization/113026
6516 * tree-vect-loop-manip.cc (vect_do_peeling): Remove
6517 redundant and wrong niter bound setting. Move niter
6518 bound adjustment down.
6520 2024-01-09 Tamar Christina <tamar.christina@arm.com>
6522 PR middle-end/113163
6523 * tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
6524 Reject non-linear inductions that aren't supported.
6526 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
6528 * config/arc/arc.cc (arc_shift_alg): New enumerated type for
6529 left shift implementation strategies.
6530 (arc_shift_info): Type for each entry of the shift strategy table.
6531 (arc_shift_context_idx): Return a integer value for each code
6532 generation context, used as an index
6533 (arc_ashl_alg): Table indexed by context and shifted bit count.
6534 (arc_split_ashl): Use the arc_ashl_alg table to select SImode
6535 left shift implementation.
6536 (arc_rtx_costs) <case ASHIFT>: Use the arc_ashl_alg table to
6537 provide accurate costs, when optimizing for speed or size.
6539 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6541 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): Fix loop invariant check.
6543 2024-01-09 Julian Brown <julian@codesourcery.com>
6545 * gimplify.cc (gimplify_expr): Ensure OMP_ARRAY_SECTION has been
6546 processed out before gimplification.
6547 * tree-pretty-print.cc (dump_generic_node): Support OMP_ARRAY_SECTION.
6548 * tree.def (OMP_ARRAY_SECTION): New tree code.
6550 2024-01-09 Jakub Jelinek <jakub@redhat.com>
6552 PR tree-optimization/113210
6553 * tree-vect-loop.cc (vect_get_loop_niters): If non-INTEGER_CST
6554 value in *number_of_iterationsm1 PLUS_EXPR 1 is folded into
6555 INTEGER_CST, recompute *number_of_iterationsm1 as the INTEGER_CST
6556 minus 1.
6558 2024-01-09 Eric Botcazou <ebotcazou@adacore.com>
6560 PR rtl-optimization/113140
6561 * reorg.cc (fill_slots_from_thread): If we are to branch after the
6562 last instruction of the function, create an end label.
6564 2024-01-09 Roger Sayle <roger@nextmovesoftware.com>
6565 Hongtao Liu <hongtao.liu@intel.com>
6567 PR target/112992
6568 * config/i386/i386-expand.cc
6569 (ix86_convert_const_wide_int_to_broadcast): Allow call to
6570 ix86_expand_vector_init_duplicate to fail, and return NULL_RTX.
6571 (ix86_broadcast_from_constant): Revert recent change; Return a
6572 suitable MEMREF independently of mode/target combinations.
6573 (ix86_expand_vector_move): Allow ix86_expand_vector_init_duplicate
6574 to decide whether expansion is possible/preferrable. Only try
6575 forcing DImode constants to memory (and trying again) if calling
6576 ix86_expand_vector_init_duplicate fails with an DImode immediate
6577 constant.
6578 (ix86_expand_vector_init_duplicate) <case E_V2DImode>: Try using
6579 V4SImode for suitable immediate constants.
6580 <case E_V4DImode>: Try using V8SImode for suitable constants.
6581 <case E_V4HImode>: Fail for CONST_INT_P, i.e. use constant pool.
6582 <case E_V2HImode>: Likewise.
6583 <case E_V8HImode>: For CONST_INT_P try using V4SImode via widen.
6584 <case E_V16QImode>: For CONT_INT_P try using V8HImode via widen.
6585 <label widen>: Handle CONT_INTs via simplify_binary_operation.
6586 Allow recursive calls to ix86_expand_vector_init_duplicate to fail.
6587 <case E_V16HImode>: For CONST_INT_P try V8SImode via widen.
6588 <case E_V32QImode>: For CONST_INT_P try V16HImode via widen.
6589 (ix86_expand_vector_init): Move try using a broadcast for all_same
6590 with ix86_expand_vector_init_duplicate before using constant pool.
6592 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
6594 * doc/invoke.texi (Arm Options): Document Cortex-M52 options.
6596 2024-01-09 Chung-Ju Wu <jasonwucj@gmail.com>
6598 * config/arm/arm-cpus.in (cortex-m52): New cpu.
6599 * config/arm/arm-tables.opt: Regenerate.
6600 * config/arm/arm-tune.md: Regenerate.
6602 2024-01-09 Jiahao Xu <xujiahao@loongson.cn>
6604 * config/loongarch/lasx.md (vec_initv32qiv16qi): Rename to ..
6605 (vec_init<mode><lasxhalf>): .. this, and extend to mode.
6606 (@vec_concatz<mode>): New insn pattern.
6607 * config/loongarch/loongarch.cc (loongarch_expand_vector_group_init):
6608 Handle VALS containing two vectors.
6610 2024-01-09 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6612 * config/riscv/riscv-vector-builtins-functions.def (vleff): Move comments.
6613 (vundefined): Ditto.
6615 2024-01-09 Feng Wang <wangfeng@eswincomputing.com>
6617 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
6618 Add new function_base for crypto vector.
6619 (class bitmanip): Ditto.
6620 (class b_reverse):Ditto.
6621 (class vwsll): Ditto.
6622 (class clmul): Ditto.
6623 (class vg_nhab): Ditto.
6624 (class crypto_vv):Ditto.
6625 (class crypto_vi):Ditto.
6626 (class vaeskf2_vsm3c):Ditto.
6627 (class vsm3me): Ditto.
6628 (BASE): Add BASE declaration for crypto vector.
6629 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
6630 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
6631 Add crypto vector intrinsic definition.
6632 (vbrev): Ditto.
6633 (vclz): Ditto.
6634 (vctz): Ditto.
6635 (vwsll): Ditto.
6636 (vandn): Ditto.
6637 (vbrev8): Ditto.
6638 (vrev8): Ditto.
6639 (vrol): Ditto.
6640 (vror): Ditto.
6641 (vclmul): Ditto.
6642 (vclmulh): Ditto.
6643 (vghsh): Ditto.
6644 (vgmul): Ditto.
6645 (vaesef): Ditto.
6646 (vaesem): Ditto.
6647 (vaesdf): Ditto.
6648 (vaesdm): Ditto.
6649 (vaesz): Ditto.
6650 (vaeskf1): Ditto.
6651 (vaeskf2): Ditto.
6652 (vsha2ms): Ditto.
6653 (vsha2ch): Ditto.
6654 (vsha2cl): Ditto.
6655 (vsm4k): Ditto.
6656 (vsm4r): Ditto.
6657 (vsm3me): Ditto.
6658 (vsm3c): Ditto.
6659 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
6660 Add new function_shape for crypto vector.
6661 (struct crypto_vi_def): Ditto.
6662 (struct crypto_vv_no_op_type_def): Ditto.
6663 (SHAPE): Add SHAPE declaration of crypto vector.
6664 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
6665 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
6666 Add new data type for crypto vector.
6667 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6668 (vuint32mf2_t): Ditto.
6669 (vuint32m1_t): Ditto.
6670 (vuint32m2_t): Ditto.
6671 (vuint32m4_t): Ditto.
6672 (vuint32m8_t): Ditto.
6673 (vuint64m1_t): Ditto.
6674 (vuint64m2_t): Ditto.
6675 (vuint64m4_t): Ditto.
6676 (vuint64m8_t): Ditto.
6677 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
6678 Add new data struct for crypto vector.
6679 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6680 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
6681 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
6683 2024-01-08 Ilya Leoshkevich <iii@linux.ibm.com>
6685 PR sanitizer/113251
6686 * varasm.cc (assemble_function_label_raw): Do not call
6687 asan_function_start () without the current function.
6689 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
6691 PR target/113225
6692 * btfout.cc (btf_collect_datasec): Skip creating BTF info for
6693 extern and kernel_helper attributed function decls.
6695 2024-01-08 Cupertino Miranda <cupertino.miranda@oracle.com>
6697 * btfout.cc (output_btf_strs): Changed.
6699 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
6701 * config/gcn/mkoffload.cc (main): Handle gfx1100
6702 when setting the default XNACK.
6704 2024-01-08 Tobias Burnus <tobias@codesourcery.com>
6706 * config.gcc (amdgcn-*-amdhsa): Accept --with-arch=gfx1100.
6707 * config/gcn/gcn-hsa.h (NO_XNACK): Add gfx1100:
6708 (ASM_SPEC): Handle gfx1100.
6709 * config/gcn/gcn-opts.h (enum processor_type): Add PROCESSOR_GFX1100.
6710 (enum gcn_isa): Add ISA_RDNA3.
6711 (TARGET_GFX1100, TARGET_RDNA2_PLUS, TARGET_RDNA3): Define.
6712 * config/gcn/gcn-valu.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
6713 * config/gcn/gcn.cc (gcn_option_override,
6714 gcn_omp_device_kind_arch_isa, output_file_start): Handle gfx1100.
6715 (gcn_global_address_p, gcn_addr_space_legitimate_address_p): Change
6716 TARGET_RDNA2 to TARGET_RDNA2_PLUS.
6717 (gcn_hsa_declare_function_name): Don't use '.amdhsa_reserve_flat_scratch'
6718 with gfx1100.
6719 * config/gcn/gcn.h (ASSEMBLER_DIALECT): Likewise.
6720 (TARGET_CPU_CPP_BUILTINS): Define __RDNA3__, __gfx1030__ and
6721 __gfx1100__.
6722 * config/gcn/gcn.md: Change TARGET_RDNA2 to TARGET_RDNA2_PLUS.
6723 * config/gcn/gcn.opt (Enum gpu_type): Add gfx1100.
6724 * config/gcn/mkoffload.cc (EF_AMDGPU_MACH_AMDGCN_GFX1100): Define.
6725 (isa_has_combined_avgprs, main): Handle gfx1100.
6726 * config/gcn/t-omp-device (isa): Add gfx1100.
6728 2024-01-08 Richard Biener <rguenther@suse.de>
6730 * doc/invoke.texi (-mmovbe): Clarify.
6732 2024-01-08 Richard Biener <rguenther@suse.de>
6734 PR tree-optimization/113026
6735 * tree-vect-loop.cc (vect_need_peeling_or_partial_vectors_p):
6736 Avoid an epilog in more cases.
6737 * tree-vect-loop-manip.cc (vect_do_peeling): Adjust the
6738 epilogues niter upper bounds and estimates.
6740 2024-01-08 Jakub Jelinek <jakub@redhat.com>
6742 PR tree-optimization/113228
6743 * gimplify.cc (recalculate_side_effects): Do nothing for SSA_NAMEs.
6745 2024-01-08 Jakub Jelinek <jakub@redhat.com>
6747 PR tree-optimization/113120
6748 * gimple-lower-bitint.cc (gimple_lower_bitint): Fix handling of very
6749 large _BitInt zero INTEGER_CST PHI argument.
6751 2024-01-08 Jakub Jelinek <jakub@redhat.com>
6753 PR tree-optimization/113119
6754 * gimple-lower-bitint.cc (optimizable_arith_overflow): Punt if
6755 both REALPART_EXPR and cast from IMAGPART_EXPR appear, but cast
6756 is before REALPART_EXPR.
6758 2024-01-08 Georg-Johann Lay <avr@gjlay.de>
6760 PR target/112952
6761 * config/avr/avr.cc (avr_handle_addr_attribute): Also print valid
6762 range when diagnosing attribute "io" and "io_low" are out of range.
6763 (avr_eval_addr_attrib): Don't ICE on empty address at that place.
6764 (avr_insert_attributes): Reject if attribute "address", "io" or "io_low"
6765 in contexts other than static storage.
6766 (avr_asm_output_aligned_decl_common): Move output of decls with
6767 attribute "address", "io", and "io_low" to...
6768 (avr_output_addr_attrib): ...this new function.
6769 (avr_asm_asm_output_aligned_bss): Remove output for decls with
6770 attribute "address", "io", and "io_low".
6771 (avr_encode_section_info): Rectify handling of decls with attribute
6772 "address", "io", and "io_low".
6774 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
6776 * config/gcn/mkoffload.cc (TEST_XNACK_UNSET): New.
6777 (elf_flags): Remove XNACK from the default value.
6778 (main): Set a default XNACK according to the arch.
6780 2024-01-08 Andrew Stubbs <ams@codesourcery.com>
6782 * config/gcn/mkoffload.cc (isa_has_combined_avgprs): Delete.
6783 (process_asm): Don't count avgprs.
6785 2024-01-08 Hongyu Wang <hongyu.wang@intel.com>
6787 * config/i386/i386.opt: Add supported sub-features.
6788 * doc/extend.texi: Add description for target attribute.
6790 2024-01-08 Feng Wang <wangfeng@eswincomputing.com>
6792 * config/riscv/vector.md: Modify avl_type operand index of zvbc ins.
6794 2024-01-07 Roger Sayle <roger@nextmovesoftware.com>
6795 Uros Bizjak <ubizjak@gmail.com>
6797 PR target/113231
6798 * config/i386/i386-features.cc (compute_convert_gain): Include
6799 the overhead of explicit load and store (movd) instructions when
6800 converting non-store scalar operations with memory destinations.
6801 Various indentation whitespace fixes.
6803 2024-01-07 Tamar Christina <tamar.christina@arm.com>
6805 * config/arm/neon.md (cbranch<mode>4): New.
6807 2024-01-07 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6809 * config/riscv/riscv-vsetvl.cc: replace std::max by MAX.
6811 2024-01-06 Jiahao Xu <xujiahao@loongson.cn>
6813 * config/loongarch/lasx.md: Set the unused bits in operand[3] to 0.
6815 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6817 PR target/113248
6818 * config/riscv/riscv-vsetvl.cc (pre_vsetvl::fuse_local_vsetvl_info):
6819 Update the MAX_SEW.
6821 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6823 * config/riscv/riscv-vector-costs.cc (loop_invariant_op_p): New function.
6824 (variable_vectorized_p): Teach loop invariant.
6825 (has_unexpected_spills_p): Ditto.
6827 2024-01-06 Juzhe-Zhong <juzhe.zhong@rivai.ai>
6829 * config/riscv/riscv-protos.h (whole_reg_to_reg_move_p): New function.
6830 * config/riscv/riscv-v.cc (whole_reg_to_reg_move_p): Ditto.
6831 * config/riscv/vector.md: Allow non-vlmax with len = NUNITS simplification.
6833 2024-01-05 Richard Sandiford <richard.sandiford@arm.com>
6835 PR target/113104
6836 * doc/invoke.texi (aarch64-sve-compare-costs): Replace with...
6837 (aarch64-vect-compare-costs): ...this.
6838 * config/aarch64/aarch64.opt (-param=aarch64-sve-compare-costs=):
6839 Replace with...
6840 (-param=aarch64-vect-compare-costs=): ...this new param.
6841 * config/aarch64/aarch64.cc (aarch64_override_options_internal):
6842 Don't disable it when vectorizing for Advanced SIMD only.
6843 (aarch64_autovectorize_vector_modes): Apply VECT_COMPARE_COSTS
6844 whenever aarch64_vect_compare_costs is true.
6846 2024-01-05 Lulu Cheng <chenglulu@loongson.cn>
6848 * config/loongarch/lasx.md (lasx_mxld_<lasxfmt_f>):
6849 Modify the method of determining the memory offset of [x]vld/[x]vst.
6850 (lasx_mxst_<lasxfmt_f>): Likewise.
6851 * config/loongarch/loongarch.cc (loongarch_valid_offset_p): Delete.
6852 (loongarch_address_insns): Likewise.
6853 * config/loongarch/lsx.md (lsx_ld_<lsxfmt_f>): Likewise.
6854 (lsx_st_<lsxfmt_f>): Likewise.
6855 * config/loongarch/predicates.md (aq10b_operand): Likewise.
6856 (aq10h_operand): Likewise.
6857 (aq10w_operand): Likewise.
6858 (aq10d_operand): Likewise.
6860 2024-01-05 Alex Coplan <alex.coplan@arm.com>
6862 PR target/113217
6863 * config/aarch64/aarch64-ldp-fusion.cc
6864 (ldp_bb_info::try_fuse_pair): If the second access can throw,
6865 narrow the move range to exactly that insn.
6867 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
6869 * asan.cc (asan_function_start): Drop switch_to_section ().
6870 (asan_emit_stack_protection): Set .LASANPC alignment.
6871 * config/i386/i386.cc: Use assemble_function_label_raw ()
6872 instead of ASM_OUTPUT_LABEL ().
6873 * config/s390/s390.cc (s390_asm_output_function_label):
6874 Likewise.
6875 * defaults.h (ASM_OUTPUT_FUNCTION_LABEL): Likewise.
6876 * final.cc (final_start_function_1): Drop
6877 asan_function_start ().
6878 * output.h (assemble_function_label_raw): New function.
6879 * varasm.cc (assemble_function_label_raw): Likewise.
6881 2024-01-05 Ilya Leoshkevich <iii@linux.ibm.com>
6883 * config/aarch64/aarch64.cc (aarch64_declare_function_name):
6884 Use ASM_OUTPUT_FUNCTION_LABEL ().
6885 * config/alpha/alpha.cc (alpha_start_function): Likewise.
6886 * config/arm/aout.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
6887 * config/arm/arm.cc (arm_asm_declare_function_name): Likewise.
6888 * config/bfin/bfin.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
6889 * config/c6x/c6x.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
6890 * config/gcn/gcn.cc (gcn_hsa_declare_function_name): Likewise.
6891 * config/h8300/h8300.h (ASM_DECLARE_FUNCTION_NAME): Likewise.
6892 * config/ia64/ia64.cc (ia64_start_function): Likewise.
6893 * config/mcore/mcore-elf.h (ASM_DECLARE_FUNCTION_NAME):
6894 Likewise.
6895 * config/microblaze/microblaze.cc (microblaze_function_prologue):
6896 Likewise.
6897 * config/mips/mips.cc (mips_start_unique_function): Return the
6898 tree.
6899 (mips_start_function_definition): Use
6900 ASM_OUTPUT_FUNCTION_LABEL ().
6901 (mips_finish_stub): Pass the tree to
6902 mips_start_function_definition ().
6903 (mips16_build_function_stub): Likewise.
6904 (mips16_build_call_stub): Likewise.
6905 (mips_output_function_prologue): Likewise.
6906 * config/pa/pa.cc (pa_output_function_label): Use
6907 ASM_OUTPUT_FUNCTION_LABEL ().
6908 * config/riscv/riscv.cc (riscv_declare_function_name): Likewise.
6909 * config/rs6000/rs6000.cc (rs6000_elf_declare_function_name):
6910 Likewise.
6911 (rs6000_xcoff_declare_function_name): Likewise.
6913 2024-01-05 Jakub Jelinek <jakub@redhat.com>
6915 PR tree-optimization/113201
6916 * tree-scalar-evolution.cc (final_value_replacement_loop): Don't call
6917 replace_uses_by on SSA_NAME_OCCURS_IN_ABNORMAL_PHI rslt.
6919 2024-01-05 Jakub Jelinek <jakub@redhat.com>
6921 PR tree-optimization/90693
6922 * tree-ssa-math-opts.cc (match_single_bit_test): If
6923 tree_expr_nonzero_p (arg), remember it in the second argument to
6924 IFN_POPCOUNT or lower it as arg & (arg - 1) == 0 rather than
6925 arg ^ (arg - 1) > arg - 1.
6926 * internal-fn.cc (expand_POPCOUNT): If second argument to
6927 IFN_POPCOUNT suggests arg is non-zero, try to expand it as
6928 arg & (arg - 1) == 0 rather than arg ^ (arg - 1) > arg - 1.
6930 2024-01-05 Kito Cheng <kito.cheng@sifive.com>
6932 * config/riscv/riscv-v.cc (expand_load_store):
6933 Remove `value`.
6934 (expand_cond_len_op): Ditto.
6935 (expand_gather_scatter): Ditto.
6936 (expand_lanes_load_store): Ditto.
6937 (expand_fold_extract_last): Ditto.
6939 2024-01-05 Pan Li <pan2.li@intel.com>
6941 Revert:
6942 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
6944 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
6945 Add new function_base for crypto vector.
6946 (class bitmanip): Ditto.
6947 (class b_reverse):Ditto.
6948 (class vwsll): Ditto.
6949 (class clmul): Ditto.
6950 (class vg_nhab): Ditto.
6951 (class crypto_vv):Ditto.
6952 (class crypto_vi):Ditto.
6953 (class vaeskf2_vsm3c):Ditto.
6954 (class vsm3me): Ditto.
6955 (BASE): Add BASE declaration for crypto vector.
6956 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
6957 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
6958 Add crypto vector intrinsic definition.
6959 (vbrev): Ditto.
6960 (vclz): Ditto.
6961 (vctz): Ditto.
6962 (vwsll): Ditto.
6963 (vandn): Ditto.
6964 (vbrev8): Ditto.
6965 (vrev8): Ditto.
6966 (vrol): Ditto.
6967 (vror): Ditto.
6968 (vclmul): Ditto.
6969 (vclmulh): Ditto.
6970 (vghsh): Ditto.
6971 (vgmul): Ditto.
6972 (vaesef): Ditto.
6973 (vaesem): Ditto.
6974 (vaesdf): Ditto.
6975 (vaesdm): Ditto.
6976 (vaesz): Ditto.
6977 (vaeskf1): Ditto.
6978 (vaeskf2): Ditto.
6979 (vsha2ms): Ditto.
6980 (vsha2ch): Ditto.
6981 (vsha2cl): Ditto.
6982 (vsm4k): Ditto.
6983 (vsm4r): Ditto.
6984 (vsm3me): Ditto.
6985 (vsm3c): Ditto.
6986 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
6987 Add new function_shape for crypto vector.
6988 (struct crypto_vi_def): Ditto.
6989 (struct crypto_vv_no_op_type_def): Ditto.
6990 (SHAPE): Add SHAPE declaration of crypto vector.
6991 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
6992 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
6993 Add new data type for crypto vector.
6994 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
6995 (vuint32mf2_t): Ditto.
6996 (vuint32m1_t): Ditto.
6997 (vuint32m2_t): Ditto.
6998 (vuint32m4_t): Ditto.
6999 (vuint32m8_t): Ditto.
7000 (vuint64m1_t): Ditto.
7001 (vuint64m2_t): Ditto.
7002 (vuint64m4_t): Ditto.
7003 (vuint64m8_t): Ditto.
7004 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
7005 Add new data struct for crypto vector.
7006 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
7007 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
7008 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
7010 2024-01-05 Feng Wang <wangfeng@eswincomputing.com>
7012 * config/riscv/riscv-vector-builtins-bases.cc (class vandn):
7013 Add new function_base for crypto vector.
7014 (class bitmanip): Ditto.
7015 (class b_reverse):Ditto.
7016 (class vwsll): Ditto.
7017 (class clmul): Ditto.
7018 (class vg_nhab): Ditto.
7019 (class crypto_vv):Ditto.
7020 (class crypto_vi):Ditto.
7021 (class vaeskf2_vsm3c):Ditto.
7022 (class vsm3me): Ditto.
7023 (BASE): Add BASE declaration for crypto vector.
7024 * config/riscv/riscv-vector-builtins-bases.h: Ditto.
7025 * config/riscv/riscv-vector-builtins-functions.def (REQUIRED_EXTENSIONS):
7026 Add crypto vector intrinsic definition.
7027 (vbrev): Ditto.
7028 (vclz): Ditto.
7029 (vctz): Ditto.
7030 (vwsll): Ditto.
7031 (vandn): Ditto.
7032 (vbrev8): Ditto.
7033 (vrev8): Ditto.
7034 (vrol): Ditto.
7035 (vror): Ditto.
7036 (vclmul): Ditto.
7037 (vclmulh): Ditto.
7038 (vghsh): Ditto.
7039 (vgmul): Ditto.
7040 (vaesef): Ditto.
7041 (vaesem): Ditto.
7042 (vaesdf): Ditto.
7043 (vaesdm): Ditto.
7044 (vaesz): Ditto.
7045 (vaeskf1): Ditto.
7046 (vaeskf2): Ditto.
7047 (vsha2ms): Ditto.
7048 (vsha2ch): Ditto.
7049 (vsha2cl): Ditto.
7050 (vsm4k): Ditto.
7051 (vsm4r): Ditto.
7052 (vsm3me): Ditto.
7053 (vsm3c): Ditto.
7054 * config/riscv/riscv-vector-builtins-shapes.cc (struct crypto_vv_def):
7055 Add new function_shape for crypto vector.
7056 (struct crypto_vi_def): Ditto.
7057 (struct crypto_vv_no_op_type_def): Ditto.
7058 (SHAPE): Add SHAPE declaration of crypto vector.
7059 * config/riscv/riscv-vector-builtins-shapes.h: Ditto.
7060 * config/riscv/riscv-vector-builtins-types.def (DEF_RVV_CRYPTO_SEW32_OPS):
7061 Add new data type for crypto vector.
7062 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
7063 (vuint32mf2_t): Ditto.
7064 (vuint32m1_t): Ditto.
7065 (vuint32m2_t): Ditto.
7066 (vuint32m4_t): Ditto.
7067 (vuint32m8_t): Ditto.
7068 (vuint64m1_t): Ditto.
7069 (vuint64m2_t): Ditto.
7070 (vuint64m4_t): Ditto.
7071 (vuint64m8_t): Ditto.
7072 * config/riscv/riscv-vector-builtins.cc (DEF_RVV_CRYPTO_SEW32_OPS):
7073 Add new data struct for crypto vector.
7074 (DEF_RVV_CRYPTO_SEW64_OPS): Ditto.
7075 (registered_function::overloaded_hash): Processing size_t uimm for C overloaded func.
7076 * config/riscv/riscv-vector-builtins.def (vi): Add vi OP_TYPE.
7078 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7080 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
7082 2024-01-04 Andrew Pinski <quic_apinski@quicinc.com>
7084 PR tree-optimization/113186
7085 * gimple-match-head.cc (gimple_bitwise_inverted_equal_p):
7086 Match `^` with the `==` for 1bit integral types.
7087 * match.pd (maybe_cmp): Allow for bit_xor for 1bit
7088 integral types.
7090 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7092 * toplev.cc (general_init): Pass lang_mask to urlifier.
7094 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7096 * diagnostic.h (diagnostic_make_option_url_cb): Add lang_mask
7097 param.
7098 (diagnostic_context::make_option_url): Update for lang_mask param.
7099 * gcc-urlifier.cc: Include "opts.h" and "options.h".
7100 (gcc_urlifier::gcc_urlifier): Add lang_mask param.
7101 (gcc_urlifier::m_lang_mask): New field.
7102 (doc_urls): Make static.
7103 (gcc_urlifier::get_url_for_quoted_text): Use label_text.
7104 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
7105 Look for an option by name before trying a binary search in
7106 doc_urls.
7107 (gcc_urlifier::get_url_suffix_for_quoted_text): Use label_text.
7108 (gcc_urlifier::get_url_suffix_for_option): New.
7109 (make_gcc_urlifier): Add lang_mask param.
7110 (selftest::gcc_urlifier_cc_tests): Update for above changes.
7111 Verify that a URL is found for "-fpack-struct".
7112 * gcc-urlifier.def: Drop options "--version" and "-fpack-struct".
7113 * gcc-urlifier.h (make_gcc_urlifier): Add lang_mask param.
7114 * gcc.cc (driver::global_initializations): Pass 0 for lang_mask
7115 to make_gcc_urlifier.
7116 * opts-diagnostic.h (get_option_url): Add lang_mask param.
7117 * opts.cc (get_option_html_page): Remove special-casing for
7118 analyzer and LTO.
7119 (get_option_url_suffix): New.
7120 (get_option_url): Reimplement.
7121 (selftest::test_get_option_html_page): Rename to...
7122 (selftest::test_get_option_url_suffix): ...this and update for
7123 above changes.
7124 (selftest::opts_cc_tests): Update for renaming.
7125 * opts.h: Include "rich-location.h".
7126 (get_option_url_suffix): New decl.
7128 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7130 * Makefile.in (ALL_OPT_URL_FILES): New.
7131 (GCC_OBJS): Add options-urls.o.
7132 (OBJS): Likewise.
7133 (OBJS-libcommon): Likewise.
7134 (s-options): Depend on $(ALL_OPT_URL_FILES), and add this to
7135 inputs to opt-gather.awk.
7136 (options-urls.cc): New Makefile target.
7137 * opt-functions.awk (url_suffix): New function.
7138 (lang_url_suffix): New function.
7139 * options-urls-cc-gen.awk: New file.
7140 * opts.h (get_opt_url_suffix): New decl.
7142 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7144 * params.opt.urls: New file, autogenerated by
7145 regenerate-opt-urls.py.
7147 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7149 * common.opt.urls: New file, autogenerated by
7150 regenerate-opt-urls.py.
7151 * config/aarch64/aarch64.opt.urls: Likewise.
7152 * config/alpha/alpha.opt.urls: Likewise.
7153 * config/alpha/elf.opt.urls: Likewise.
7154 * config/arc/arc-tables.opt.urls: Likewise.
7155 * config/arc/arc.opt.urls: Likewise.
7156 * config/arm/arm-tables.opt.urls: Likewise.
7157 * config/arm/arm.opt.urls: Likewise.
7158 * config/arm/vxworks.opt.urls: Likewise.
7159 * config/avr/avr.opt.urls: Likewise.
7160 * config/bpf/bpf.opt.urls: Likewise.
7161 * config/c6x/c6x-tables.opt.urls: Likewise.
7162 * config/c6x/c6x.opt.urls: Likewise.
7163 * config/cris/cris.opt.urls: Likewise.
7164 * config/cris/elf.opt.urls: Likewise.
7165 * config/csky/csky.opt.urls: Likewise.
7166 * config/csky/csky_tables.opt.urls: Likewise.
7167 * config/darwin.opt.urls: Likewise.
7168 * config/dragonfly.opt.urls: Likewise.
7169 * config/epiphany/epiphany.opt.urls: Likewise.
7170 * config/fr30/fr30.opt.urls: Likewise.
7171 * config/freebsd.opt.urls: Likewise.
7172 * config/frv/frv.opt.urls: Likewise.
7173 * config/ft32/ft32.opt.urls: Likewise.
7174 * config/fused-madd.opt.urls: Likewise.
7175 * config/g.opt.urls: Likewise.
7176 * config/gcn/gcn.opt.urls: Likewise.
7177 * config/gnu-user.opt.urls: Likewise.
7178 * config/h8300/h8300.opt.urls: Likewise.
7179 * config/hpux11.opt.urls: Likewise.
7180 * config/i386/cygming.opt.urls: Likewise.
7181 * config/i386/cygwin.opt.urls: Likewise.
7182 * config/i386/djgpp.opt.urls: Likewise.
7183 * config/i386/i386.opt.urls: Likewise.
7184 * config/i386/mingw-w64.opt.urls: Likewise.
7185 * config/i386/mingw.opt.urls: Likewise.
7186 * config/i386/nto.opt.urls: Likewise.
7187 * config/ia64/ia64.opt.urls: Likewise.
7188 * config/ia64/ilp32.opt.urls: Likewise.
7189 * config/ia64/vms.opt.urls: Likewise.
7190 * config/iq2000/iq2000.opt.urls: Likewise.
7191 * config/linux-android.opt.urls: Likewise.
7192 * config/linux.opt.urls: Likewise.
7193 * config/lm32/lm32.opt.urls: Likewise.
7194 * config/loongarch/loongarch.opt.urls: Likewise.
7195 * config/lynx.opt.urls: Likewise.
7196 * config/m32c/m32c.opt.urls: Likewise.
7197 * config/m32r/m32r.opt.urls: Likewise.
7198 * config/m68k/ieee.opt.urls: Likewise.
7199 * config/m68k/m68k-tables.opt.urls: Likewise.
7200 * config/m68k/m68k.opt.urls: Likewise.
7201 * config/m68k/uclinux.opt.urls: Likewise.
7202 * config/mcore/mcore.opt.urls: Likewise.
7203 * config/microblaze/microblaze.opt.urls: Likewise.
7204 * config/mips/mips-tables.opt.urls: Likewise.
7205 * config/mips/mips.opt.urls: Likewise.
7206 * config/mips/sde.opt.urls: Likewise.
7207 * config/mmix/mmix.opt.urls: Likewise.
7208 * config/mn10300/mn10300.opt.urls: Likewise.
7209 * config/moxie/moxie.opt.urls: Likewise.
7210 * config/msp430/msp430.opt.urls: Likewise.
7211 * config/nds32/nds32-elf.opt.urls: Likewise.
7212 * config/nds32/nds32-linux.opt.urls: Likewise.
7213 * config/nds32/nds32.opt.urls: Likewise.
7214 * config/netbsd-elf.opt.urls: Likewise.
7215 * config/netbsd.opt.urls: Likewise.
7216 * config/nios2/elf.opt.urls: Likewise.
7217 * config/nios2/nios2.opt.urls: Likewise.
7218 * config/nvptx/nvptx-gen.opt.urls: Likewise.
7219 * config/nvptx/nvptx.opt.urls: Likewise.
7220 * config/openbsd.opt.urls: Likewise.
7221 * config/or1k/elf.opt.urls: Likewise.
7222 * config/or1k/or1k.opt.urls: Likewise.
7223 * config/pa/pa-hpux.opt.urls: Likewise.
7224 * config/pa/pa-hpux1010.opt.urls: Likewise.
7225 * config/pa/pa-hpux1111.opt.urls: Likewise.
7226 * config/pa/pa-hpux1131.opt.urls: Likewise.
7227 * config/pa/pa.opt.urls: Likewise.
7228 * config/pa/pa64-hpux.opt.urls: Likewise.
7229 * config/pdp11/pdp11.opt.urls: Likewise.
7230 * config/pru/pru.opt.urls: Likewise.
7231 * config/riscv/riscv.opt.urls: Likewise.
7232 * config/rl78/rl78.opt.urls: Likewise.
7233 * config/rpath.opt.urls: Likewise.
7234 * config/rs6000/476.opt.urls: Likewise.
7235 * config/rs6000/aix64.opt.urls: Likewise.
7236 * config/rs6000/darwin.opt.urls: Likewise.
7237 * config/rs6000/linux64.opt.urls: Likewise.
7238 * config/rs6000/rs6000-tables.opt.urls: Likewise.
7239 * config/rs6000/rs6000.opt.urls: Likewise.
7240 * config/rs6000/sysv4.opt.urls: Likewise.
7241 * config/rtems.opt.urls: Likewise.
7242 * config/rx/elf.opt.urls: Likewise.
7243 * config/rx/rx.opt.urls: Likewise.
7244 * config/s390/s390.opt.urls: Likewise.
7245 * config/s390/tpf.opt.urls: Likewise.
7246 * config/sh/sh.opt.urls: Likewise.
7247 * config/sh/superh.opt.urls: Likewise.
7248 * config/sol2.opt.urls: Likewise.
7249 * config/sparc/long-double-switch.opt.urls: Likewise.
7250 * config/sparc/sparc.opt.urls: Likewise.
7251 * config/stormy16/stormy16.opt.urls: Likewise.
7252 * config/v850/v850.opt.urls: Likewise.
7253 * config/vax/elf.opt.urls: Likewise.
7254 * config/vax/vax.opt.urls: Likewise.
7255 * config/visium/visium.opt.urls: Likewise.
7256 * config/vms/vms.opt.urls: Likewise.
7257 * config/vxworks-smp.opt.urls: Likewise.
7258 * config/vxworks.opt.urls: Likewise.
7259 * config/xtensa/elf.opt.urls: Likewise.
7260 * config/xtensa/uclinux.opt.urls: Likewise.
7261 * config/xtensa/xtensa.opt.urls: Likewise.
7262 * config/bfin/bfin.opt.urls: New file.
7264 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7266 * Makefile.in (OPT_URLS_HTML_DEPS): New.
7267 (regenerate-opt-urls): New target.
7268 (regenerate-opt-urls-unit-test): New target.
7269 * doc/options.texi (Option properties): Add UrlSuffix and
7270 description of regenerate-opt-urls.py. Add LangUrlSuffix_*.
7271 * doc/sourcebuild.texi (Anatomy of a Language Front End): Add
7272 reference to regenerate-opt-urls.py's PER_LANGUAGE_OPTION_INDEXES
7273 and Makefile.in's OPT_URLS_HTML_DEPS.
7274 (Anatomy of a Target Back End): Add
7275 reference to regenerate-opt-urls.py's TARGET_SPECIFIC_PAGES.
7276 * regenerate-opt-urls.py: New file.
7278 2024-01-04 David Malcolm <dmalcolm@redhat.com>
7280 * diagnostic-format-sarif.cc
7281 (sarif_builder::make_logical_location_object): Convert to...
7282 (make_sarif_logical_location_object): ...this.
7283 (sarif_builder::set_any_logical_locs_arr): Update for above
7284 change.
7285 (sarif_builder::make_thread_flow_location_object): Call
7286 maybe_add_sarif_properties on each diagnostic_event.
7287 * diagnostic-format-sarif.h (class logical_location): New forward
7288 decl.
7289 (make_sarif_logical_location_object): New decl.
7290 * diagnostic-path.h (class sarif_object): New forward decl.
7291 (diagnostic_event::maybe_add_sarif_properties): New vfunc.
7293 2024-01-04 Kuan-Lin Chen <rufus@andestech.com>
7294 Patrick Lin <patrick@andestech.com>
7295 Rufus Chen <rufus@andestech.com>
7296 Monk Chiang <monk.chiang@sifive.com>
7298 * config/riscv/riscv.cc (riscv_legitimize_move): Expand movfh
7299 with Nan-boxing value.
7300 * config/riscv/riscv.md (*movhf_softfloat_unspec): New pattern.
7302 2024-01-04 Roger Sayle <roger@nextmovesoftware.com>
7303 Jeff Law <jlaw@ventanamicro.com>
7305 PR rtl-optimization/104914
7306 * expr.cc (expand_assignment): When target is SUBREG_PROMOTED_VAR_P
7307 a sign or zero extension is only required if the modified field
7308 overlaps the SUBREG's most significant bit. On MODE_REP_EXTENDED
7309 targets, don't refer to the temporarily incorrectly extended value
7310 using a SUBREG, but instead generate an explicit TRUNCATE rtx.
7312 2024-01-04 Pan Li <pan2.li@intel.com>
7314 Revert:
7315 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7317 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
7319 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7321 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): Teach vi variant.
7323 2024-01-04 Kito Cheng <kito.cheng@sifive.com>
7325 * config/riscv/riscv.cc (riscv_for_each_saved_reg): Adjust the
7326 offset of fcsr.
7328 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7330 * config/riscv/riscv-vector-costs.cc (variable_vectorized_p): New function.
7331 (compute_nregs_for_mode): Refine LMUL.
7332 (max_number_of_live_regs): Ditto.
7333 (compute_estimated_lmul): Ditto.
7334 (has_unexpected_spills_p): Ditto.
7336 2024-01-04 Li Wei <liwei@loongson.cn>
7338 * config/loongarch/loongarch.cc (loongarch_is_odd_extraction):
7339 Remove useless forward declaration.
7340 (loongarch_is_even_extraction): Remove useless forward declaration.
7341 (loongarch_try_expand_lsx_vshuf_const): Removed.
7342 (loongarch_expand_vec_perm_const_1): Merged.
7343 (loongarch_is_double_duplicate): Removed.
7344 (loongarch_is_center_extraction): Ditto.
7345 (loongarch_is_reversing_permutation): Ditto.
7346 (loongarch_is_di_misalign_extract): Ditto.
7347 (loongarch_is_si_misalign_extract): Ditto.
7348 (loongarch_is_lasx_lowpart_extract): Ditto.
7349 (loongarch_is_op_reverse_perm): Ditto.
7350 (loongarch_is_single_op_perm): Ditto.
7351 (loongarch_is_divisible_perm): Ditto.
7352 (loongarch_is_triple_stride_extract): Ditto.
7353 (loongarch_expand_vec_perm_const_2): Merged.
7354 (loongarch_expand_vec_perm_const): New.
7355 (loongarch_vectorize_vec_perm_const): Adjust.
7357 2024-01-04 Sandra Loosemore <sandra@codesourcery.com>
7359 * omp-general.cc: Fix comment typos and misplaced/confusing
7360 comments. Delete redundant include of omp-general.h.
7362 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
7364 PR rtl-optimization/104914
7365 * config/mips/mips.md (insqisi_extended): New patterns.
7366 (inshisi_extended): Ditto.
7368 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
7370 * config/mips/mips.cc (mips_insn_cost): New function.
7372 2024-01-04 YunQiang Su <syq@gcc.gnu.org>
7374 * config/mips/mips.md (perf_ratio): New attribute.
7376 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7378 PR target/113206
7379 PR target/113209
7380 * config/riscv/riscv-vsetvl.cc (invalid_opt_bb_p): New function.
7381 (pre_vsetvl::compute_lcm_local_properties): Disable earliest fusion on
7382 blocks belong to infinite loop.
7383 (pre_vsetvl::emit_vsetvl): Remove fake edges.
7384 * config/riscv/t-riscv: Add a new include file.
7386 2024-01-04 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7388 * config/riscv/vector.md: Fix indent.
7390 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
7392 * tree-core.h (enum omp_clause_code): Move OMP_CLAUSE_INDIRECT to before
7393 OMP_CLAUSE__SIMDUID_.
7394 * tree.cc (omp_clause_num_ops): Update position of entry for
7395 OMP_CLAUSE_INDIRECT to correspond with omp_clause_code.
7396 (omp_clause_code_name): Likewise.
7398 2024-01-03 Kwok Cheung Yeung <kcy@codesourcery.com>
7400 * config/nvptx/nvptx.cc (nvptx_record_offload_symbol): Restucture
7401 printing of FUNC_MAP/IND_FUNC_MAP labels.
7403 2024-01-03 Jakub Jelinek <jakub@redhat.com>
7405 * gcc.cc (process_command): Update copyright notice dates.
7406 * gcov-dump.cc (print_version): Ditto.
7407 * gcov.cc (print_version): Ditto.
7408 * gcov-tool.cc (print_version): Ditto.
7409 * gengtype.cc (create_file): Ditto.
7410 * doc/cpp.texi: Bump @copying's copyright year.
7411 * doc/cppinternals.texi: Ditto.
7412 * doc/gcc.texi: Ditto.
7413 * doc/gccint.texi: Ditto.
7414 * doc/gcov.texi: Ditto.
7415 * doc/install.texi: Ditto.
7416 * doc/invoke.texi: Ditto.
7418 2024-01-03 Xi Ruoyao <xry111@xry111.site>
7420 * config/loongarch/simd.md (fmax<mode>3): New define_insn.
7421 (fmin<mode>3): Likewise.
7422 (reduc_fmax_scal_<mode>3): New define_expand.
7423 (reduc_fmin_scal_<mode>3): Likewise.
7425 2024-01-03 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7427 PR target/113112
7428 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Add rgroup info.
7429 (max_number_of_live_regs): Ditto.
7430 (has_unexpected_spills_p): Ditto.
7432 2024-01-02 Jun Sha (Joshua) <cooper.joshua@linux.alibaba.com>
7433 Jin Ma <jinma@linux.alibaba.com>
7434 Xianmiao Qu <cooper.qu@linux.alibaba.com>
7435 Christoph Müllner <christoph.muellner@vrull.eu>
7437 * config/riscv/vector.md:
7438 Use vector_length_operand for vsetvl patterns.
7440 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7442 * config/riscv/riscv-v.cc (is_vlmax_len_p): Remove satisfies_constraint_K.
7443 (expand_cond_len_op): Add simplification of dummy len and dummy mask.
7445 2024-01-02 Di Zhao <dizhao@os.amperecomputing.com>
7447 * config/aarch64/aarch64-tuning-flags.def
7448 (AARCH64_EXTRA_TUNING_OPTION): New tuning option
7449 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA.
7450 * config/aarch64/aarch64.cc
7451 (aarch64_override_options_internal): Set
7452 param_fully_pipelined_fma according to tuning option.
7453 * config/aarch64/tuning_models/ampere1.h: Add
7454 AARCH64_EXTRA_TUNE_FULLY_PIPELINED_FMA to tune_flags.
7455 * config/aarch64/tuning_models/ampere1a.h: Likewise.
7456 * config/aarch64/tuning_models/ampere1b.h: Likewise.
7458 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
7460 * config/riscv/vector-crypto.md: Modify copyright year.
7462 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7464 * config/riscv/riscv-vector-costs.cc: Move STMT_VINFO_TYPE (...) to local.
7466 2024-01-02 Lulu Cheng <chenglulu@loongson.cn>
7468 * config.in: Regenerate.
7469 * config/loongarch/loongarch-opts.h (HAVE_AS_TLS_LE_RELAXATION): Define.
7470 * config/loongarch/loongarch.cc (loongarch_legitimize_tls_address):
7471 Added TLS Le Relax support.
7472 (loongarch_print_operand_reloc): Add the output string of TLS Le Relax.
7473 * config/loongarch/loongarch.md (@add_tls_le_relax<mode>): New template.
7474 * configure: Regenerate.
7475 * configure.ac: Check if binutils supports TLS le relax.
7477 2024-01-02 Feng Wang <wangfeng@eswincomputing.com>
7479 * config/riscv/iterators.md: Add rotate insn name.
7480 * config/riscv/riscv.md: Add new insns name for crypto vector.
7481 * config/riscv/vector-iterators.md: Add new iterators for crypto vector.
7482 * config/riscv/vector.md: Add the corresponding attr for crypto vector.
7483 * config/riscv/vector-crypto.md: New file.The machine descriptions for crypto vector.
7485 2024-01-02 Juzhe-Zhong <juzhe.zhong@rivai.ai>
7487 PR target/113112
7488 * config/riscv/riscv-vector-costs.cc (compute_nregs_for_mode): Fix
7489 pointer type liveness count.
7490 \f
7491 Copyright (C) 2024 Free Software Foundation, Inc.
7493 Copying and distribution of this file, with or without modification,
7494 are permitted in any medium without royalty provided the copyright
7495 notice and this notice are preserved.