gcc/combine.c

   1 /* Optimize by combining instructions for GNU compiler.
   2    Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
   3    1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
   4    2011, 2012 Free Software Foundation, Inc.
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify it under
   9 the terms of the GNU General Public License as published by the Free
  10 Software Foundation; either version 3, or (at your option) any later
  11 version.
  12
  13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16 for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 /* This module is essentially the "combiner" phase of the U. of Arizona
  23    Portable Optimizer, but redone to work on our list-structured
  24    representation for RTL instead of their string representation.
  25
  26    The LOG_LINKS of each insn identify the most recent assignment
  27    to each REG used in the insn.  It is a list of previous insns,
  28    each of which contains a SET for a REG that is used in this insn
  29    and not used or set in between.  LOG_LINKs never cross basic blocks.
  30    They were set up by the preceding pass (lifetime analysis).
  31
  32    We try to combine each pair of insns joined by a logical link.
  33    We also try to combine triples of insns A, B and C when
  34    C has a link back to B and B has a link back to A.
  35
  36    LOG_LINKS does not have links for use of the CC0.  They don't
  37    need to, because the insn that sets the CC0 is always immediately
  38    before the insn that tests it.  So we always regard a branch
  39    insn as having a logical link to the preceding insn.  The same is true
  40    for an insn explicitly using CC0.
  41
  42    We check (with use_crosses_set_p) to avoid combining in such a way
  43    as to move a computation to a place where its value would be different.
  44
  45    Combination is done by mathematically substituting the previous
  46    insn(s) values for the regs they set into the expressions in
  47    the later insns that refer to these regs.  If the result is a valid insn
  48    for our target machine, according to the machine description,
  49    we install it, delete the earlier insns, and update the data flow
  50    information (LOG_LINKS and REG_NOTES) for what we did.
  51
  52    There are a few exceptions where the dataflow information isn't
  53    completely updated (however this is only a local issue since it is
  54    regenerated before the next pass that uses it):
  55
  56    - reg_live_length is not updated
  57    - reg_n_refs is not adjusted in the rare case when a register is
  58      no longer required in a computation
  59    - there are extremely rare cases (see distribute_notes) when a
  60      REG_DEAD note is lost
  61    - a LOG_LINKS entry that refers to an insn with multiple SETs may be
  62      removed because there is no way to know which register it was
  63      linking
  64
  65    To simplify substitution, we combine only when the earlier insn(s)
  66    consist of only a single assignment.  To simplify updating afterward,
  67    we never combine when a subroutine call appears in the middle.
  68
  69    Since we do not represent assignments to CC0 explicitly except when that
  70    is all an insn does, there is no LOG_LINKS entry in an insn that uses
  71    the condition code for the insn that set the condition code.
  72    Fortunately, these two insns must be consecutive.
  73    Therefore, every JUMP_INSN is taken to have an implicit logical link
  74    to the preceding insn.  This is not quite right, since non-jumps can
  75    also use the condition code; but in practice such insns would not
  76    combine anyway.  */
  77
  78 #include "config.h"
  79 #include "system.h"
  80 #include "coretypes.h"
  81 #include "tm.h"
  82 #include "rtl.h"
  83 #include "tree.h"
  84 #include "tm_p.h"
  85 #include "flags.h"
  86 #include "regs.h"
  87 #include "hard-reg-set.h"
  88 #include "basic-block.h"
  89 #include "insn-config.h"
  90 #include "function.h"
  91 /* Include expr.h after insn-config.h so we get HAVE_conditional_move.  */
  92 #include "expr.h"
  93 #include "insn-attr.h"
  94 #include "recog.h"
  95 #include "diagnostic-core.h"
  96 #include "target.h"
  97 #include "optabs.h"
  98 #include "insn-codes.h"
  99 #include "rtlhooks-def.h"
 100 /* Include output.h for dump_file.  */
 101 #include "output.h"
 102 #include "params.h"
 103 #include "timevar.h"
 104 #include "tree-pass.h"
 105 #include "df.h"
 106 #include "cgraph.h"
 107 #include "obstack.h"
 108
 109 /* Number of attempts to combine instructions in this function.  */
 110
 111 static int combine_attempts;
 112
 113 /* Number of attempts that got as far as substitution in this function.  */
 114
 115 static int combine_merges;
 116
 117 /* Number of instructions combined with added SETs in this function.  */
 118
 119 static int combine_extras;
 120
 121 /* Number of instructions combined in this function.  */
 122
 123 static int combine_successes;
 124
 125 /* Totals over entire compilation.  */
 126
 127 static int total_attempts, total_merges, total_extras, total_successes;
 128
 129 /* combine_instructions may try to replace the right hand side of the
 130    second instruction with the value of an associated REG_EQUAL note
 131    before throwing it at try_combine.  That is problematic when there
 132    is a REG_DEAD note for a register used in the old right hand side
 133    and can cause distribute_notes to do wrong things.  This is the
 134    second instruction if it has been so modified, null otherwise.  */
 135
 136 static rtx i2mod;
 137
 138 /* When I2MOD is nonnull, this is a copy of the old right hand side.  */
 139
 140 static rtx i2mod_old_rhs;
 141
 142 /* When I2MOD is nonnull, this is a copy of the new right hand side.  */
 143
 144 static rtx i2mod_new_rhs;
 145 \f
 146 typedef struct reg_stat_struct {
 147   /* Record last point of death of (hard or pseudo) register n.  */
 148   rtx                           last_death;
 149
 150   /* Record last point of modification of (hard or pseudo) register n.  */
 151   rtx                           last_set;
 152
 153   /* The next group of fields allows the recording of the last value assigned
 154      to (hard or pseudo) register n.  We use this information to see if an
 155      operation being processed is redundant given a prior operation performed
 156      on the register.  For example, an `and' with a constant is redundant if
 157      all the zero bits are already known to be turned off.
 158
 159      We use an approach similar to that used by cse, but change it in the
 160      following ways:
 161
 162      (1) We do not want to reinitialize at each label.
 163      (2) It is useful, but not critical, to know the actual value assigned
 164          to a register.  Often just its form is helpful.
 165
 166      Therefore, we maintain the following fields:
 167
 168      last_set_value             the last value assigned
 169      last_set_label             records the value of label_tick when the
 170                                 register was assigned
 171      last_set_table_tick        records the value of label_tick when a
 172                                 value using the register is assigned
 173      last_set_invalid           set to nonzero when it is not valid
 174                                 to use the value of this register in some
 175                                 register's value
 176
 177      To understand the usage of these tables, it is important to understand
 178      the distinction between the value in last_set_value being valid and
 179      the register being validly contained in some other expression in the
 180      table.
 181
 182      (The next two parameters are out of date).
 183
 184      reg_stat[i].last_set_value is valid if it is nonzero, and either
 185      reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
 186
 187      Register I may validly appear in any expression returned for the value
 188      of another register if reg_n_sets[i] is 1.  It may also appear in the
 189      value for register J if reg_stat[j].last_set_invalid is zero, or
 190      reg_stat[i].last_set_label < reg_stat[j].last_set_label.
 191
 192      If an expression is found in the table containing a register which may
 193      not validly appear in an expression, the register is replaced by
 194      something that won't match, (clobber (const_int 0)).  */
 195
 196   /* Record last value assigned to (hard or pseudo) register n.  */
 197
 198   rtx                           last_set_value;
 199
 200   /* Record the value of label_tick when an expression involving register n
 201      is placed in last_set_value.  */
 202
 203   int                           last_set_table_tick;
 204
 205   /* Record the value of label_tick when the value for register n is placed in
 206      last_set_value.  */
 207
 208   int                           last_set_label;
 209
 210   /* These fields are maintained in parallel with last_set_value and are
 211      used to store the mode in which the register was last set, the bits
 212      that were known to be zero when it was last set, and the number of
 213      sign bits copies it was known to have when it was last set.  */
 214
 215   unsigned HOST_WIDE_INT        last_set_nonzero_bits;
 216   char                          last_set_sign_bit_copies;
 217   ENUM_BITFIELD(machine_mode)   last_set_mode : 8;
 218
 219   /* Set nonzero if references to register n in expressions should not be
 220      used.  last_set_invalid is set nonzero when this register is being
 221      assigned to and last_set_table_tick == label_tick.  */
 222
 223   char                          last_set_invalid;
 224
 225   /* Some registers that are set more than once and used in more than one
 226      basic block are nevertheless always set in similar ways.  For example,
 227      a QImode register may be loaded from memory in two places on a machine
 228      where byte loads zero extend.
 229
 230      We record in the following fields if a register has some leading bits
 231      that are always equal to the sign bit, and what we know about the
 232      nonzero bits of a register, specifically which bits are known to be
 233      zero.
 234
 235      If an entry is zero, it means that we don't know anything special.  */
 236
 237   unsigned char                 sign_bit_copies;
 238
 239   unsigned HOST_WIDE_INT        nonzero_bits;
 240
 241   /* Record the value of the label_tick when the last truncation
 242      happened.  The field truncated_to_mode is only valid if
 243      truncation_label == label_tick.  */
 244
 245   int                           truncation_label;
 246
 247   /* Record the last truncation seen for this register.  If truncation
 248      is not a nop to this mode we might be able to save an explicit
 249      truncation if we know that value already contains a truncated
 250      value.  */
 251
 252   ENUM_BITFIELD(machine_mode)   truncated_to_mode : 8;
 253 } reg_stat_type;
 254
 255 DEF_VEC_O(reg_stat_type);
 256 DEF_VEC_ALLOC_O(reg_stat_type,heap);
 257
 258 static VEC(reg_stat_type,heap) *reg_stat;
 259
 260 /* Record the luid of the last insn that invalidated memory
 261    (anything that writes memory, and subroutine calls, but not pushes).  */
 262
 263 static int mem_last_set;
 264
 265 /* Record the luid of the last CALL_INSN
 266    so we can tell whether a potential combination crosses any calls.  */
 267
 268 static int last_call_luid;
 269
 270 /* When `subst' is called, this is the insn that is being modified
 271    (by combining in a previous insn).  The PATTERN of this insn
 272    is still the old pattern partially modified and it should not be
 273    looked at, but this may be used to examine the successors of the insn
 274    to judge whether a simplification is valid.  */
 275
 276 static rtx subst_insn;
 277
 278 /* This is the lowest LUID that `subst' is currently dealing with.
 279    get_last_value will not return a value if the register was set at or
 280    after this LUID.  If not for this mechanism, we could get confused if
 281    I2 or I1 in try_combine were an insn that used the old value of a register
 282    to obtain a new value.  In that case, we might erroneously get the
 283    new value of the register when we wanted the old one.  */
 284
 285 static int subst_low_luid;
 286
 287 /* This contains any hard registers that are used in newpat; reg_dead_at_p
 288    must consider all these registers to be always live.  */
 289
 290 static HARD_REG_SET newpat_used_regs;
 291
 292 /* This is an insn to which a LOG_LINKS entry has been added.  If this
 293    insn is the earlier than I2 or I3, combine should rescan starting at
 294    that location.  */
 295
 296 static rtx added_links_insn;
 297
 298 /* Basic block in which we are performing combines.  */
 299 static basic_block this_basic_block;
 300 static bool optimize_this_for_speed_p;
 301
 302 \f
 303 /* Length of the currently allocated uid_insn_cost array.  */
 304
 305 static int max_uid_known;
 306
 307 /* The following array records the insn_rtx_cost for every insn
 308    in the instruction stream.  */
 309
 310 static int *uid_insn_cost;
 311
 312 /* The following array records the LOG_LINKS for every insn in the
 313    instruction stream as struct insn_link pointers.  */
 314
 315 struct insn_link {
 316   rtx insn;
 317   struct insn_link *next;
 318 };
 319
 320 static struct insn_link **uid_log_links;
 321
 322 #define INSN_COST(INSN)         (uid_insn_cost[INSN_UID (INSN)])
 323 #define LOG_LINKS(INSN)         (uid_log_links[INSN_UID (INSN)])
 324
 325 #define FOR_EACH_LOG_LINK(L, INSN)                              \
 326   for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
 327
 328 /* Links for LOG_LINKS are allocated from this obstack.  */
 329
 330 static struct obstack insn_link_obstack;
 331
 332 /* Allocate a link.  */
 333
 334 static inline struct insn_link *
 335 alloc_insn_link (rtx insn, struct insn_link *next)
 336 {
 337   struct insn_link *l
 338     = (struct insn_link *) obstack_alloc (&insn_link_obstack,
 339                                           sizeof (struct insn_link));
 340   l->insn = insn;
 341   l->next = next;
 342   return l;
 343 }
 344
 345 /* Incremented for each basic block.  */
 346
 347 static int label_tick;
 348
 349 /* Reset to label_tick for each extended basic block in scanning order.  */
 350
 351 static int label_tick_ebb_start;
 352
 353 /* Mode used to compute significance in reg_stat[].nonzero_bits.  It is the
 354    largest integer mode that can fit in HOST_BITS_PER_WIDE_INT.  */
 355
 356 static enum machine_mode nonzero_bits_mode;
 357
 358 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
 359    be safely used.  It is zero while computing them and after combine has
 360    completed.  This former test prevents propagating values based on
 361    previously set values, which can be incorrect if a variable is modified
 362    in a loop.  */
 363
 364 static int nonzero_sign_valid;
 365
 366 \f
 367 /* Record one modification to rtl structure
 368    to be undone by storing old_contents into *where.  */
 369
 370 enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
 371
 372 struct undo
 373 {
 374   struct undo *next;
 375   enum undo_kind kind;
 376   union { rtx r; int i; enum machine_mode m; struct insn_link *l; } old_contents;
 377   union { rtx *r; int *i; struct insn_link **l; } where;
 378 };
 379
 380 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
 381    num_undo says how many are currently recorded.
 382
 383    other_insn is nonzero if we have modified some other insn in the process
 384    of working on subst_insn.  It must be verified too.  */
 385
 386 struct undobuf
 387 {
 388   struct undo *undos;
 389   struct undo *frees;
 390   rtx other_insn;
 391 };
 392
 393 static struct undobuf undobuf;
 394
 395 /* Number of times the pseudo being substituted for
 396    was found and replaced.  */
 397
 398 static int n_occurrences;
 399
 400 static rtx reg_nonzero_bits_for_combine (const_rtx, enum machine_mode, const_rtx,
 401                                          enum machine_mode,
 402                                          unsigned HOST_WIDE_INT,
 403                                          unsigned HOST_WIDE_INT *);
 404 static rtx reg_num_sign_bit_copies_for_combine (const_rtx, enum machine_mode, const_rtx,
 405                                                 enum machine_mode,
 406                                                 unsigned int, unsigned int *);
 407 static void do_SUBST (rtx *, rtx);
 408 static void do_SUBST_INT (int *, int);
 409 static void init_reg_last (void);
 410 static void setup_incoming_promotions (rtx);
 411 static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
 412 static int cant_combine_insn_p (rtx);
 413 static int can_combine_p (rtx, rtx, rtx, rtx, rtx, rtx, rtx *, rtx *);
 414 static int combinable_i3pat (rtx, rtx *, rtx, rtx, rtx, int, int, rtx *);
 415 static int contains_muldiv (rtx);
 416 static rtx try_combine (rtx, rtx, rtx, rtx, int *, rtx);
 417 static void undo_all (void);
 418 static void undo_commit (void);
 419 static rtx *find_split_point (rtx *, rtx, bool);
 420 static rtx subst (rtx, rtx, rtx, int, int, int);
 421 static rtx combine_simplify_rtx (rtx, enum machine_mode, int, int);
 422 static rtx simplify_if_then_else (rtx);
 423 static rtx simplify_set (rtx);
 424 static rtx simplify_logical (rtx);
 425 static rtx expand_compound_operation (rtx);
 426 static const_rtx expand_field_assignment (const_rtx);
 427 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
 428                             rtx, unsigned HOST_WIDE_INT, int, int, int);
 429 static rtx extract_left_shift (rtx, int);
 430 static rtx make_compound_operation (rtx, enum rtx_code);
 431 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
 432                               unsigned HOST_WIDE_INT *);
 433 static rtx canon_reg_for_combine (rtx, rtx);
 434 static rtx force_to_mode (rtx, enum machine_mode,
 435                           unsigned HOST_WIDE_INT, int);
 436 static rtx if_then_else_cond (rtx, rtx *, rtx *);
 437 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
 438 static int rtx_equal_for_field_assignment_p (rtx, rtx);
 439 static rtx make_field_assignment (rtx);
 440 static rtx apply_distributive_law (rtx);
 441 static rtx distribute_and_simplify_rtx (rtx, int);
 442 static rtx simplify_and_const_int_1 (enum machine_mode, rtx,
 443                                      unsigned HOST_WIDE_INT);
 444 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
 445                                    unsigned HOST_WIDE_INT);
 446 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
 447                             HOST_WIDE_INT, enum machine_mode, int *);
 448 static rtx simplify_shift_const_1 (enum rtx_code, enum machine_mode, rtx, int);
 449 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
 450                                  int);
 451 static int recog_for_combine (rtx *, rtx, rtx *);
 452 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
 453 static enum rtx_code simplify_compare_const (enum rtx_code, rtx, rtx *);
 454 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
 455 static void update_table_tick (rtx);
 456 static void record_value_for_reg (rtx, rtx, rtx);
 457 static void check_promoted_subreg (rtx, rtx);
 458 static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
 459 static void record_dead_and_set_regs (rtx);
 460 static int get_last_value_validate (rtx *, rtx, int, int);
 461 static rtx get_last_value (const_rtx);
 462 static int use_crosses_set_p (const_rtx, int);
 463 static void reg_dead_at_p_1 (rtx, const_rtx, void *);
 464 static int reg_dead_at_p (rtx, rtx);
 465 static void move_deaths (rtx, rtx, int, rtx, rtx *);
 466 static int reg_bitfield_target_p (rtx, rtx);
 467 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx, rtx);
 468 static void distribute_links (struct insn_link *);
 469 static void mark_used_regs_combine (rtx);
 470 static void record_promoted_value (rtx, rtx);
 471 static int unmentioned_reg_p_1 (rtx *, void *);
 472 static bool unmentioned_reg_p (rtx, rtx);
 473 static int record_truncated_value (rtx *, void *);
 474 static void record_truncated_values (rtx *, void *);
 475 static bool reg_truncated_to_mode (enum machine_mode, const_rtx);
 476 static rtx gen_lowpart_or_truncate (enum machine_mode, rtx);
 477 \f
 478
 479 /* It is not safe to use ordinary gen_lowpart in combine.
 480    See comments in gen_lowpart_for_combine.  */
 481 #undef RTL_HOOKS_GEN_LOWPART
 482 #define RTL_HOOKS_GEN_LOWPART              gen_lowpart_for_combine
 483
 484 /* Our implementation of gen_lowpart never emits a new pseudo.  */
 485 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
 486 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT      gen_lowpart_for_combine
 487
 488 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
 489 #define RTL_HOOKS_REG_NONZERO_REG_BITS     reg_nonzero_bits_for_combine
 490
 491 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
 492 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES  reg_num_sign_bit_copies_for_combine
 493
 494 #undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
 495 #define RTL_HOOKS_REG_TRUNCATED_TO_MODE    reg_truncated_to_mode
 496
 497 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
 498
 499 \f
 500 /* Try to split PATTERN found in INSN.  This returns NULL_RTX if
 501    PATTERN can not be split.  Otherwise, it returns an insn sequence.
 502    This is a wrapper around split_insns which ensures that the
 503    reg_stat vector is made larger if the splitter creates a new
 504    register.  */
 505
 506 static rtx
 507 combine_split_insns (rtx pattern, rtx insn)
 508 {
 509   rtx ret;
 510   unsigned int nregs;
 511
 512   ret = split_insns (pattern, insn);
 513   nregs = max_reg_num ();
 514   if (nregs > VEC_length (reg_stat_type, reg_stat))
 515     VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
 516   return ret;
 517 }
 518
 519 /* This is used by find_single_use to locate an rtx in LOC that
 520    contains exactly one use of DEST, which is typically either a REG
 521    or CC0.  It returns a pointer to the innermost rtx expression
 522    containing DEST.  Appearances of DEST that are being used to
 523    totally replace it are not counted.  */
 524
 525 static rtx *
 526 find_single_use_1 (rtx dest, rtx *loc)
 527 {
 528   rtx x = *loc;
 529   enum rtx_code code = GET_CODE (x);
 530   rtx *result = NULL;
 531   rtx *this_result;
 532   int i;
 533   const char *fmt;
 534
 535   switch (code)
 536     {
 537     case CONST_INT:
 538     case CONST:
 539     case LABEL_REF:
 540     case SYMBOL_REF:
 541     case CONST_DOUBLE:
 542     case CONST_VECTOR:
 543     case CLOBBER:
 544       return 0;
 545
 546     case SET:
 547       /* If the destination is anything other than CC0, PC, a REG or a SUBREG
 548          of a REG that occupies all of the REG, the insn uses DEST if
 549          it is mentioned in the destination or the source.  Otherwise, we
 550          need just check the source.  */
 551       if (GET_CODE (SET_DEST (x)) != CC0
 552           && GET_CODE (SET_DEST (x)) != PC
 553           && !REG_P (SET_DEST (x))
 554           && ! (GET_CODE (SET_DEST (x)) == SUBREG
 555                 && REG_P (SUBREG_REG (SET_DEST (x)))
 556                 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
 557                       + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
 558                     == ((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
 559                          + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))))
 560         break;
 561
 562       return find_single_use_1 (dest, &SET_SRC (x));
 563
 564     case MEM:
 565     case SUBREG:
 566       return find_single_use_1 (dest, &XEXP (x, 0));
 567
 568     default:
 569       break;
 570     }
 571
 572   /* If it wasn't one of the common cases above, check each expression and
 573      vector of this code.  Look for a unique usage of DEST.  */
 574
 575   fmt = GET_RTX_FORMAT (code);
 576   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
 577     {
 578       if (fmt[i] == 'e')
 579         {
 580           if (dest == XEXP (x, i)
 581               || (REG_P (dest) && REG_P (XEXP (x, i))
 582                   && REGNO (dest) == REGNO (XEXP (x, i))))
 583             this_result = loc;
 584           else
 585             this_result = find_single_use_1 (dest, &XEXP (x, i));
 586
 587           if (result == NULL)
 588             result = this_result;
 589           else if (this_result)
 590             /* Duplicate usage.  */
 591             return NULL;
 592         }
 593       else if (fmt[i] == 'E')
 594         {
 595           int j;
 596
 597           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
 598             {
 599               if (XVECEXP (x, i, j) == dest
 600                   || (REG_P (dest)
 601                       && REG_P (XVECEXP (x, i, j))
 602                       && REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
 603                 this_result = loc;
 604               else
 605                 this_result = find_single_use_1 (dest, &XVECEXP (x, i, j));
 606
 607               if (result == NULL)
 608                 result = this_result;
 609               else if (this_result)
 610                 return NULL;
 611             }
 612         }
 613     }
 614
 615   return result;
 616 }
 617
 618
 619 /* See if DEST, produced in INSN, is used only a single time in the
 620    sequel.  If so, return a pointer to the innermost rtx expression in which
 621    it is used.
 622
 623    If PLOC is nonzero, *PLOC is set to the insn containing the single use.
 624
 625    If DEST is cc0_rtx, we look only at the next insn.  In that case, we don't
 626    care about REG_DEAD notes or LOG_LINKS.
 627
 628    Otherwise, we find the single use by finding an insn that has a
 629    LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST.  If DEST is
 630    only referenced once in that insn, we know that it must be the first
 631    and last insn referencing DEST.  */
 632
 633 static rtx *
 634 find_single_use (rtx dest, rtx insn, rtx *ploc)
 635 {
 636   basic_block bb;
 637   rtx next;
 638   rtx *result;
 639   struct insn_link *link;
 640
 641 #ifdef HAVE_cc0
 642   if (dest == cc0_rtx)
 643     {
 644       next = NEXT_INSN (insn);
 645       if (next == 0
 646           || (!NONJUMP_INSN_P (next) && !JUMP_P (next)))
 647         return 0;
 648
 649       result = find_single_use_1 (dest, &PATTERN (next));
 650       if (result && ploc)
 651         *ploc = next;
 652       return result;
 653     }
 654 #endif
 655
 656   if (!REG_P (dest))
 657     return 0;
 658
 659   bb = BLOCK_FOR_INSN (insn);
 660   for (next = NEXT_INSN (insn);
 661        next && BLOCK_FOR_INSN (next) == bb;
 662        next = NEXT_INSN (next))
 663     if (INSN_P (next) && dead_or_set_p (next, dest))
 664       {
 665         FOR_EACH_LOG_LINK (link, next)
 666           if (link->insn == insn)
 667             break;
 668
 669         if (link)
 670           {
 671             result = find_single_use_1 (dest, &PATTERN (next));
 672             if (ploc)
 673               *ploc = next;
 674             return result;
 675           }
 676       }
 677
 678   return 0;
 679 }
 680 \f
 681 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
 682    insn.  The substitution can be undone by undo_all.  If INTO is already
 683    set to NEWVAL, do not record this change.  Because computing NEWVAL might
 684    also call SUBST, we have to compute it before we put anything into
 685    the undo table.  */
 686
 687 static void
 688 do_SUBST (rtx *into, rtx newval)
 689 {
 690   struct undo *buf;
 691   rtx oldval = *into;
 692
 693   if (oldval == newval)
 694     return;
 695
 696   /* We'd like to catch as many invalid transformations here as
 697      possible.  Unfortunately, there are way too many mode changes
 698      that are perfectly valid, so we'd waste too much effort for
 699      little gain doing the checks here.  Focus on catching invalid
 700      transformations involving integer constants.  */
 701   if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
 702       && CONST_INT_P (newval))
 703     {
 704       /* Sanity check that we're replacing oldval with a CONST_INT
 705          that is a valid sign-extension for the original mode.  */
 706       gcc_assert (INTVAL (newval)
 707                   == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
 708
 709       /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
 710          CONST_INT is not valid, because after the replacement, the
 711          original mode would be gone.  Unfortunately, we can't tell
 712          when do_SUBST is called to replace the operand thereof, so we
 713          perform this test on oldval instead, checking whether an
 714          invalid replacement took place before we got here.  */
 715       gcc_assert (!(GET_CODE (oldval) == SUBREG
 716                     && CONST_INT_P (SUBREG_REG (oldval))));
 717       gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
 718                     && CONST_INT_P (XEXP (oldval, 0))));
 719     }
 720
 721   if (undobuf.frees)
 722     buf = undobuf.frees, undobuf.frees = buf->next;
 723   else
 724     buf = XNEW (struct undo);
 725
 726   buf->kind = UNDO_RTX;
 727   buf->where.r = into;
 728   buf->old_contents.r = oldval;
 729   *into = newval;
 730
 731   buf->next = undobuf.undos, undobuf.undos = buf;
 732 }
 733
 734 #define SUBST(INTO, NEWVAL)     do_SUBST(&(INTO), (NEWVAL))
 735
 736 /* Similar to SUBST, but NEWVAL is an int expression.  Note that substitution
 737    for the value of a HOST_WIDE_INT value (including CONST_INT) is
 738    not safe.  */
 739
 740 static void
 741 do_SUBST_INT (int *into, int newval)
 742 {
 743   struct undo *buf;
 744   int oldval = *into;
 745
 746   if (oldval == newval)
 747     return;
 748
 749   if (undobuf.frees)
 750     buf = undobuf.frees, undobuf.frees = buf->next;
 751   else
 752     buf = XNEW (struct undo);
 753
 754   buf->kind = UNDO_INT;
 755   buf->where.i = into;
 756   buf->old_contents.i = oldval;
 757   *into = newval;
 758
 759   buf->next = undobuf.undos, undobuf.undos = buf;
 760 }
 761
 762 #define SUBST_INT(INTO, NEWVAL)  do_SUBST_INT(&(INTO), (NEWVAL))
 763
 764 /* Similar to SUBST, but just substitute the mode.  This is used when
 765    changing the mode of a pseudo-register, so that any other
 766    references to the entry in the regno_reg_rtx array will change as
 767    well.  */
 768
 769 static void
 770 do_SUBST_MODE (rtx *into, enum machine_mode newval)
 771 {
 772   struct undo *buf;
 773   enum machine_mode oldval = GET_MODE (*into);
 774
 775   if (oldval == newval)
 776     return;
 777
 778   if (undobuf.frees)
 779     buf = undobuf.frees, undobuf.frees = buf->next;
 780   else
 781     buf = XNEW (struct undo);
 782
 783   buf->kind = UNDO_MODE;
 784   buf->where.r = into;
 785   buf->old_contents.m = oldval;
 786   adjust_reg_mode (*into, newval);
 787
 788   buf->next = undobuf.undos, undobuf.undos = buf;
 789 }
 790
 791 #define SUBST_MODE(INTO, NEWVAL)  do_SUBST_MODE(&(INTO), (NEWVAL))
 792
 793 /* Similar to SUBST, but NEWVAL is a LOG_LINKS expression.  */
 794
 795 static void
 796 do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
 797 {
 798   struct undo *buf;
 799   struct insn_link * oldval = *into;
 800
 801   if (oldval == newval)
 802     return;
 803
 804   if (undobuf.frees)
 805     buf = undobuf.frees, undobuf.frees = buf->next;
 806   else
 807     buf = XNEW (struct undo);
 808
 809   buf->kind = UNDO_LINKS;
 810   buf->where.l = into;
 811   buf->old_contents.l = oldval;
 812   *into = newval;
 813
 814   buf->next = undobuf.undos, undobuf.undos = buf;
 815 }
 816
 817 #define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
 818
 819 \f
 820 /* Subroutine of try_combine.  Determine whether the replacement patterns
 821    NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_rtx_cost
 822    than the original sequence I0, I1, I2, I3 and undobuf.other_insn.  Note
 823    that I0, I1 and/or NEWI2PAT may be NULL_RTX.  Similarly, NEWOTHERPAT and
 824    undobuf.other_insn may also both be NULL_RTX.  Return false if the cost
 825    of all the instructions can be estimated and the replacements are more
 826    expensive than the original sequence.  */
 827
 828 static bool
 829 combine_validate_cost (rtx i0, rtx i1, rtx i2, rtx i3, rtx newpat,
 830                        rtx newi2pat, rtx newotherpat)
 831 {
 832   int i0_cost, i1_cost, i2_cost, i3_cost;
 833   int new_i2_cost, new_i3_cost;
 834   int old_cost, new_cost;
 835
 836   /* Lookup the original insn_rtx_costs.  */
 837   i2_cost = INSN_COST (i2);
 838   i3_cost = INSN_COST (i3);
 839
 840   if (i1)
 841     {
 842       i1_cost = INSN_COST (i1);
 843       if (i0)
 844         {
 845           i0_cost = INSN_COST (i0);
 846           old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 847                       ? i0_cost + i1_cost + i2_cost + i3_cost : 0);
 848         }
 849       else
 850         {
 851           old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
 852                       ? i1_cost + i2_cost + i3_cost : 0);
 853           i0_cost = 0;
 854         }
 855     }
 856   else
 857     {
 858       old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
 859       i1_cost = i0_cost = 0;
 860     }
 861
 862   /* Calculate the replacement insn_rtx_costs.  */
 863   new_i3_cost = insn_rtx_cost (newpat, optimize_this_for_speed_p);
 864   if (newi2pat)
 865     {
 866       new_i2_cost = insn_rtx_cost (newi2pat, optimize_this_for_speed_p);
 867       new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
 868                  ? new_i2_cost + new_i3_cost : 0;
 869     }
 870   else
 871     {
 872       new_cost = new_i3_cost;
 873       new_i2_cost = 0;
 874     }
 875
 876   if (undobuf.other_insn)
 877     {
 878       int old_other_cost, new_other_cost;
 879
 880       old_other_cost = INSN_COST (undobuf.other_insn);
 881       new_other_cost = insn_rtx_cost (newotherpat, optimize_this_for_speed_p);
 882       if (old_other_cost > 0 && new_other_cost > 0)
 883         {
 884           old_cost += old_other_cost;
 885           new_cost += new_other_cost;
 886         }
 887       else
 888         old_cost = 0;
 889     }
 890
 891   /* Disallow this combination if both new_cost and old_cost are greater than
 892      zero, and new_cost is greater than old cost.  */
 893   if (old_cost > 0 && new_cost > old_cost)
 894     {
 895       if (dump_file)
 896         {
 897           if (i0)
 898             {
 899               fprintf (dump_file,
 900                        "rejecting combination of insns %d, %d, %d and %d\n",
 901                        INSN_UID (i0), INSN_UID (i1), INSN_UID (i2),
 902                        INSN_UID (i3));
 903               fprintf (dump_file, "original costs %d + %d + %d + %d = %d\n",
 904                        i0_cost, i1_cost, i2_cost, i3_cost, old_cost);
 905             }
 906           else if (i1)
 907             {
 908               fprintf (dump_file,
 909                        "rejecting combination of insns %d, %d and %d\n",
 910                        INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
 911               fprintf (dump_file, "original costs %d + %d + %d = %d\n",
 912                        i1_cost, i2_cost, i3_cost, old_cost);
 913             }
 914           else
 915             {
 916               fprintf (dump_file,
 917                        "rejecting combination of insns %d and %d\n",
 918                        INSN_UID (i2), INSN_UID (i3));
 919               fprintf (dump_file, "original costs %d + %d = %d\n",
 920                        i2_cost, i3_cost, old_cost);
 921             }
 922
 923           if (newi2pat)
 924             {
 925               fprintf (dump_file, "replacement costs %d + %d = %d\n",
 926                        new_i2_cost, new_i3_cost, new_cost);
 927             }
 928           else
 929             fprintf (dump_file, "replacement cost %d\n", new_cost);
 930         }
 931
 932       return false;
 933     }
 934
 935   /* Update the uid_insn_cost array with the replacement costs.  */
 936   INSN_COST (i2) = new_i2_cost;
 937   INSN_COST (i3) = new_i3_cost;
 938   if (i1)
 939     {
 940       INSN_COST (i1) = 0;
 941       if (i0)
 942         INSN_COST (i0) = 0;
 943     }
 944
 945   return true;
 946 }
 947
 948
 949 /* Delete any insns that copy a register to itself.  */
 950
 951 static void
 952 delete_noop_moves (void)
 953 {
 954   rtx insn, next;
 955   basic_block bb;
 956
 957   FOR_EACH_BB (bb)
 958     {
 959       for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
 960         {
 961           next = NEXT_INSN (insn);
 962           if (INSN_P (insn) && noop_move_p (insn))
 963             {
 964               if (dump_file)
 965                 fprintf (dump_file, "deleting noop move %d\n", INSN_UID (insn));
 966
 967               delete_insn_and_edges (insn);
 968             }
 969         }
 970     }
 971 }
 972
 973 \f
 974 /* Fill in log links field for all insns.  */
 975
 976 static void
 977 create_log_links (void)
 978 {
 979   basic_block bb;
 980   rtx *next_use, insn;
 981   df_ref *def_vec, *use_vec;
 982
 983   next_use = XCNEWVEC (rtx, max_reg_num ());
 984
 985   /* Pass through each block from the end, recording the uses of each
 986      register and establishing log links when def is encountered.
 987      Note that we do not clear next_use array in order to save time,
 988      so we have to test whether the use is in the same basic block as def.
 989
 990      There are a few cases below when we do not consider the definition or
 991      usage -- these are taken from original flow.c did. Don't ask me why it is
 992      done this way; I don't know and if it works, I don't want to know.  */
 993
 994   FOR_EACH_BB (bb)
 995     {
 996       FOR_BB_INSNS_REVERSE (bb, insn)
 997         {
 998           if (!NONDEBUG_INSN_P (insn))
 999             continue;
1000
1001           /* Log links are created only once.  */
1002           gcc_assert (!LOG_LINKS (insn));
1003
1004           for (def_vec = DF_INSN_DEFS (insn); *def_vec; def_vec++)
1005             {
1006               df_ref def = *def_vec;
1007               int regno = DF_REF_REGNO (def);
1008               rtx use_insn;
1009
1010               if (!next_use[regno])
1011                 continue;
1012
1013               /* Do not consider if it is pre/post modification in MEM.  */
1014               if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
1015                 continue;
1016
1017               /* Do not make the log link for frame pointer.  */
1018               if ((regno == FRAME_POINTER_REGNUM
1019                    && (! reload_completed || frame_pointer_needed))
1020 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1021                   || (regno == HARD_FRAME_POINTER_REGNUM
1022                       && (! reload_completed || frame_pointer_needed))
1023 #endif
1024 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1025                   || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
1026 #endif
1027                   )
1028                 continue;
1029
1030               use_insn = next_use[regno];
1031               if (BLOCK_FOR_INSN (use_insn) == bb)
1032                 {
1033                   /* flow.c claimed:
1034
1035                      We don't build a LOG_LINK for hard registers contained
1036                      in ASM_OPERANDs.  If these registers get replaced,
1037                      we might wind up changing the semantics of the insn,
1038                      even if reload can make what appear to be valid
1039                      assignments later.  */
1040                   if (regno >= FIRST_PSEUDO_REGISTER
1041                       || asm_noperands (PATTERN (use_insn)) < 0)
1042                     {
1043                       /* Don't add duplicate links between instructions.  */
1044                       struct insn_link *links;
1045                       FOR_EACH_LOG_LINK (links, use_insn)
1046                         if (insn == links->insn)
1047                           break;
1048
1049                       if (!links)
1050                         LOG_LINKS (use_insn)
1051                           = alloc_insn_link (insn, LOG_LINKS (use_insn));
1052                     }
1053                 }
1054               next_use[regno] = NULL_RTX;
1055             }
1056
1057           for (use_vec = DF_INSN_USES (insn); *use_vec; use_vec++)
1058             {
1059               df_ref use = *use_vec;
1060               int regno = DF_REF_REGNO (use);
1061
1062               /* Do not consider the usage of the stack pointer
1063                  by function call.  */
1064               if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1065                 continue;
1066
1067               next_use[regno] = insn;
1068             }
1069         }
1070     }
1071
1072   free (next_use);
1073 }
1074
1075 /* Walk the LOG_LINKS of insn B to see if we find a reference to A.  Return
1076    true if we found a LOG_LINK that proves that A feeds B.  This only works
1077    if there are no instructions between A and B which could have a link
1078    depending on A, since in that case we would not record a link for B.
1079    We also check the implicit dependency created by a cc0 setter/user
1080    pair.  */
1081
1082 static bool
1083 insn_a_feeds_b (rtx a, rtx b)
1084 {
1085   struct insn_link *links;
1086   FOR_EACH_LOG_LINK (links, b)
1087     if (links->insn == a)
1088       return true;
1089 #ifdef HAVE_cc0
1090   if (sets_cc0_p (a))
1091     return true;
1092 #endif
1093   return false;
1094 }
1095 \f
1096 /* Main entry point for combiner.  F is the first insn of the function.
1097    NREGS is the first unused pseudo-reg number.
1098
1099    Return nonzero if the combiner has turned an indirect jump
1100    instruction into a direct jump.  */
1101 static int
1102 combine_instructions (rtx f, unsigned int nregs)
1103 {
1104   rtx insn, next;
1105 #ifdef HAVE_cc0
1106   rtx prev;
1107 #endif
1108   struct insn_link *links, *nextlinks;
1109   rtx first;
1110   basic_block last_bb;
1111
1112   int new_direct_jump_p = 0;
1113
1114   for (first = f; first && !INSN_P (first); )
1115     first = NEXT_INSN (first);
1116   if (!first)
1117     return 0;
1118
1119   combine_attempts = 0;
1120   combine_merges = 0;
1121   combine_extras = 0;
1122   combine_successes = 0;
1123
1124   rtl_hooks = combine_rtl_hooks;
1125
1126   VEC_safe_grow_cleared (reg_stat_type, heap, reg_stat, nregs);
1127
1128   init_recog_no_volatile ();
1129
1130   /* Allocate array for insn info.  */
1131   max_uid_known = get_max_uid ();
1132   uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1133   uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1134   gcc_obstack_init (&insn_link_obstack);
1135
1136   nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
1137
1138   /* Don't use reg_stat[].nonzero_bits when computing it.  This can cause
1139      problems when, for example, we have j <<= 1 in a loop.  */
1140
1141   nonzero_sign_valid = 0;
1142   label_tick = label_tick_ebb_start = 1;
1143
1144   /* Scan all SETs and see if we can deduce anything about what
1145      bits are known to be zero for some registers and how many copies
1146      of the sign bit are known to exist for those registers.
1147
1148      Also set any known values so that we can use it while searching
1149      for what bits are known to be set.  */
1150
1151   setup_incoming_promotions (first);
1152   /* Allow the entry block and the first block to fall into the same EBB.
1153      Conceptually the incoming promotions are assigned to the entry block.  */
1154   last_bb = ENTRY_BLOCK_PTR;
1155
1156   create_log_links ();
1157   FOR_EACH_BB (this_basic_block)
1158     {
1159       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1160       last_call_luid = 0;
1161       mem_last_set = -1;
1162
1163       label_tick++;
1164       if (!single_pred_p (this_basic_block)
1165           || single_pred (this_basic_block) != last_bb)
1166         label_tick_ebb_start = label_tick;
1167       last_bb = this_basic_block;
1168
1169       FOR_BB_INSNS (this_basic_block, insn)
1170         if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1171           {
1172 #ifdef AUTO_INC_DEC
1173             rtx links;
1174 #endif
1175
1176             subst_low_luid = DF_INSN_LUID (insn);
1177             subst_insn = insn;
1178
1179             note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
1180                          insn);
1181             record_dead_and_set_regs (insn);
1182
1183 #ifdef AUTO_INC_DEC
1184             for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1185               if (REG_NOTE_KIND (links) == REG_INC)
1186                 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1187                                                   insn);
1188 #endif
1189
1190             /* Record the current insn_rtx_cost of this instruction.  */
1191             if (NONJUMP_INSN_P (insn))
1192               INSN_COST (insn) = insn_rtx_cost (PATTERN (insn),
1193                                                 optimize_this_for_speed_p);
1194             if (dump_file)
1195               fprintf(dump_file, "insn_cost %d: %d\n",
1196                     INSN_UID (insn), INSN_COST (insn));
1197           }
1198     }
1199
1200   nonzero_sign_valid = 1;
1201
1202   /* Now scan all the insns in forward order.  */
1203   label_tick = label_tick_ebb_start = 1;
1204   init_reg_last ();
1205   setup_incoming_promotions (first);
1206   last_bb = ENTRY_BLOCK_PTR;
1207
1208   FOR_EACH_BB (this_basic_block)
1209     {
1210       rtx last_combined_insn = NULL_RTX;
1211       optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1212       last_call_luid = 0;
1213       mem_last_set = -1;
1214
1215       label_tick++;
1216       if (!single_pred_p (this_basic_block)
1217           || single_pred (this_basic_block) != last_bb)
1218         label_tick_ebb_start = label_tick;
1219       last_bb = this_basic_block;
1220
1221       rtl_profile_for_bb (this_basic_block);
1222       for (insn = BB_HEAD (this_basic_block);
1223            insn != NEXT_INSN (BB_END (this_basic_block));
1224            insn = next ? next : NEXT_INSN (insn))
1225         {
1226           next = 0;
1227           if (NONDEBUG_INSN_P (insn))
1228             {
1229               while (last_combined_insn
1230                      && INSN_DELETED_P (last_combined_insn))
1231                 last_combined_insn = PREV_INSN (last_combined_insn);
1232               if (last_combined_insn == NULL_RTX
1233                   || BARRIER_P (last_combined_insn)
1234                   || BLOCK_FOR_INSN (last_combined_insn) != this_basic_block
1235                   || DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1236                 last_combined_insn = insn;
1237
1238               /* See if we know about function return values before this
1239                  insn based upon SUBREG flags.  */
1240               check_promoted_subreg (insn, PATTERN (insn));
1241
1242               /* See if we can find hardregs and subreg of pseudos in
1243                  narrower modes.  This could help turning TRUNCATEs
1244                  into SUBREGs.  */
1245               note_uses (&PATTERN (insn), record_truncated_values, NULL);
1246
1247               /* Try this insn with each insn it links back to.  */
1248
1249               FOR_EACH_LOG_LINK (links, insn)
1250                 if ((next = try_combine (insn, links->insn, NULL_RTX,
1251                                          NULL_RTX, &new_direct_jump_p,
1252                                          last_combined_insn)) != 0)
1253                   goto retry;
1254
1255               /* Try each sequence of three linked insns ending with this one.  */
1256
1257               FOR_EACH_LOG_LINK (links, insn)
1258                 {
1259                   rtx link = links->insn;
1260
1261                   /* If the linked insn has been replaced by a note, then there
1262                      is no point in pursuing this chain any further.  */
1263                   if (NOTE_P (link))
1264                     continue;
1265
1266                   FOR_EACH_LOG_LINK (nextlinks, link)
1267                     if ((next = try_combine (insn, link, nextlinks->insn,
1268                                              NULL_RTX, &new_direct_jump_p,
1269                                              last_combined_insn)) != 0)
1270                       goto retry;
1271                 }
1272
1273 #ifdef HAVE_cc0
1274               /* Try to combine a jump insn that uses CC0
1275                  with a preceding insn that sets CC0, and maybe with its
1276                  logical predecessor as well.
1277                  This is how we make decrement-and-branch insns.
1278                  We need this special code because data flow connections
1279                  via CC0 do not get entered in LOG_LINKS.  */
1280
1281               if (JUMP_P (insn)
1282                   && (prev = prev_nonnote_insn (insn)) != 0
1283                   && NONJUMP_INSN_P (prev)
1284                   && sets_cc0_p (PATTERN (prev)))
1285                 {
1286                   if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1287                                            &new_direct_jump_p,
1288                                            last_combined_insn)) != 0)
1289                     goto retry;
1290
1291                   FOR_EACH_LOG_LINK (nextlinks, prev)
1292                     if ((next = try_combine (insn, prev, nextlinks->insn,
1293                                              NULL_RTX, &new_direct_jump_p,
1294                                              last_combined_insn)) != 0)
1295                       goto retry;
1296                 }
1297
1298               /* Do the same for an insn that explicitly references CC0.  */
1299               if (NONJUMP_INSN_P (insn)
1300                   && (prev = prev_nonnote_insn (insn)) != 0
1301                   && NONJUMP_INSN_P (prev)
1302                   && sets_cc0_p (PATTERN (prev))
1303                   && GET_CODE (PATTERN (insn)) == SET
1304                   && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
1305                 {
1306                   if ((next = try_combine (insn, prev, NULL_RTX, NULL_RTX,
1307                                            &new_direct_jump_p,
1308                                            last_combined_insn)) != 0)
1309                     goto retry;
1310
1311                   FOR_EACH_LOG_LINK (nextlinks, prev)
1312                     if ((next = try_combine (insn, prev, nextlinks->insn,
1313                                              NULL_RTX, &new_direct_jump_p,
1314                                              last_combined_insn)) != 0)
1315                       goto retry;
1316                 }
1317
1318               /* Finally, see if any of the insns that this insn links to
1319                  explicitly references CC0.  If so, try this insn, that insn,
1320                  and its predecessor if it sets CC0.  */
1321               FOR_EACH_LOG_LINK (links, insn)
1322                 if (NONJUMP_INSN_P (links->insn)
1323                     && GET_CODE (PATTERN (links->insn)) == SET
1324                     && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (links->insn)))
1325                     && (prev = prev_nonnote_insn (links->insn)) != 0
1326                     && NONJUMP_INSN_P (prev)
1327                     && sets_cc0_p (PATTERN (prev))
1328                     && (next = try_combine (insn, links->insn,
1329                                             prev, NULL_RTX, &new_direct_jump_p,
1330                                             last_combined_insn)) != 0)
1331                   goto retry;
1332 #endif
1333
1334               /* Try combining an insn with two different insns whose results it
1335                  uses.  */
1336               FOR_EACH_LOG_LINK (links, insn)
1337                 for (nextlinks = links->next; nextlinks;
1338                      nextlinks = nextlinks->next)
1339                   if ((next = try_combine (insn, links->insn,
1340                                            nextlinks->insn, NULL_RTX,
1341                                            &new_direct_jump_p,
1342                                            last_combined_insn)) != 0)
1343                     goto retry;
1344
1345               /* Try four-instruction combinations.  */
1346               FOR_EACH_LOG_LINK (links, insn)
1347                 {
1348                   struct insn_link *next1;
1349                   rtx link = links->insn;
1350
1351                   /* If the linked insn has been replaced by a note, then there
1352                      is no point in pursuing this chain any further.  */
1353                   if (NOTE_P (link))
1354                     continue;
1355
1356                   FOR_EACH_LOG_LINK (next1, link)
1357                     {
1358                       rtx link1 = next1->insn;
1359                       if (NOTE_P (link1))
1360                         continue;
1361                       /* I0 -> I1 -> I2 -> I3.  */
1362                       FOR_EACH_LOG_LINK (nextlinks, link1)
1363                         if ((next = try_combine (insn, link, link1,
1364                                                  nextlinks->insn,
1365                                                  &new_direct_jump_p,
1366                                                  last_combined_insn)) != 0)
1367                           goto retry;
1368                       /* I0, I1 -> I2, I2 -> I3.  */
1369                       for (nextlinks = next1->next; nextlinks;
1370                            nextlinks = nextlinks->next)
1371                         if ((next = try_combine (insn, link, link1,
1372                                                  nextlinks->insn,
1373                                                  &new_direct_jump_p,
1374                                                  last_combined_insn)) != 0)
1375                           goto retry;
1376                     }
1377
1378                   for (next1 = links->next; next1; next1 = next1->next)
1379                     {
1380                       rtx link1 = next1->insn;
1381                       if (NOTE_P (link1))
1382                         continue;
1383                       /* I0 -> I2; I1, I2 -> I3.  */
1384                       FOR_EACH_LOG_LINK (nextlinks, link)
1385                         if ((next = try_combine (insn, link, link1,
1386                                                  nextlinks->insn,
1387                                                  &new_direct_jump_p,
1388                                                  last_combined_insn)) != 0)
1389                           goto retry;
1390                       /* I0 -> I1; I1, I2 -> I3.  */
1391                       FOR_EACH_LOG_LINK (nextlinks, link1)
1392                         if ((next = try_combine (insn, link, link1,
1393                                                  nextlinks->insn,
1394                                                  &new_direct_jump_p,
1395                                                  last_combined_insn)) != 0)
1396                           goto retry;
1397                     }
1398                 }
1399
1400               /* Try this insn with each REG_EQUAL note it links back to.  */
1401               FOR_EACH_LOG_LINK (links, insn)
1402                 {
1403                   rtx set, note;
1404                   rtx temp = links->insn;
1405                   if ((set = single_set (temp)) != 0
1406                       && (note = find_reg_equal_equiv_note (temp)) != 0
1407                       && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1408                       /* Avoid using a register that may already been marked
1409                          dead by an earlier instruction.  */
1410                       && ! unmentioned_reg_p (note, SET_SRC (set))
1411                       && (GET_MODE (note) == VOIDmode
1412                           ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1413                           : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
1414                     {
1415                       /* Temporarily replace the set's source with the
1416                          contents of the REG_EQUAL note.  The insn will
1417                          be deleted or recognized by try_combine.  */
1418                       rtx orig = SET_SRC (set);
1419                       SET_SRC (set) = note;
1420                       i2mod = temp;
1421                       i2mod_old_rhs = copy_rtx (orig);
1422                       i2mod_new_rhs = copy_rtx (note);
1423                       next = try_combine (insn, i2mod, NULL_RTX, NULL_RTX,
1424                                           &new_direct_jump_p,
1425                                           last_combined_insn);
1426                       i2mod = NULL_RTX;
1427                       if (next)
1428                         goto retry;
1429                       SET_SRC (set) = orig;
1430                     }
1431                 }
1432
1433               if (!NOTE_P (insn))
1434                 record_dead_and_set_regs (insn);
1435
1436             retry:
1437               ;
1438             }
1439         }
1440     }
1441
1442   default_rtl_profile ();
1443   clear_bb_flags ();
1444   new_direct_jump_p |= purge_all_dead_edges ();
1445   delete_noop_moves ();
1446
1447   /* Clean up.  */
1448   obstack_free (&insn_link_obstack, NULL);
1449   free (uid_log_links);
1450   free (uid_insn_cost);
1451   VEC_free (reg_stat_type, heap, reg_stat);
1452
1453   {
1454     struct undo *undo, *next;
1455     for (undo = undobuf.frees; undo; undo = next)
1456       {
1457         next = undo->next;
1458         free (undo);
1459       }
1460     undobuf.frees = 0;
1461   }
1462
1463   total_attempts += combine_attempts;
1464   total_merges += combine_merges;
1465   total_extras += combine_extras;
1466   total_successes += combine_successes;
1467
1468   nonzero_sign_valid = 0;
1469   rtl_hooks = general_rtl_hooks;
1470
1471   /* Make recognizer allow volatile MEMs again.  */
1472   init_recog ();
1473
1474   return new_direct_jump_p;
1475 }
1476
1477 /* Wipe the last_xxx fields of reg_stat in preparation for another pass.  */
1478
1479 static void
1480 init_reg_last (void)
1481 {
1482   unsigned int i;
1483   reg_stat_type *p;
1484
1485   FOR_EACH_VEC_ELT (reg_stat_type, reg_stat, i, p)
1486     memset (p, 0, offsetof (reg_stat_type, sign_bit_copies));
1487 }
1488 \f
1489 /* Set up any promoted values for incoming argument registers.  */
1490
1491 static void
1492 setup_incoming_promotions (rtx first)
1493 {
1494   tree arg;
1495   bool strictly_local = false;
1496
1497   for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1498        arg = DECL_CHAIN (arg))
1499     {
1500       rtx x, reg = DECL_INCOMING_RTL (arg);
1501       int uns1, uns3;
1502       enum machine_mode mode1, mode2, mode3, mode4;
1503
1504       /* Only continue if the incoming argument is in a register.  */
1505       if (!REG_P (reg))
1506         continue;
1507
1508       /* Determine, if possible, whether all call sites of the current
1509          function lie within the current compilation unit.  (This does
1510          take into account the exporting of a function via taking its
1511          address, and so forth.)  */
1512       strictly_local = cgraph_local_info (current_function_decl)->local;
1513
1514       /* The mode and signedness of the argument before any promotions happen
1515          (equal to the mode of the pseudo holding it at that stage).  */
1516       mode1 = TYPE_MODE (TREE_TYPE (arg));
1517       uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1518
1519       /* The mode and signedness of the argument after any source language and
1520          TARGET_PROMOTE_PROTOTYPES-driven promotions.  */
1521       mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1522       uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1523
1524       /* The mode and signedness of the argument as it is actually passed,
1525          after any TARGET_PROMOTE_FUNCTION_ARGS-driven ABI promotions.  */
1526       mode3 = promote_function_mode (DECL_ARG_TYPE (arg), mode2, &uns3,
1527                                      TREE_TYPE (cfun->decl), 0);
1528
1529       /* The mode of the register in which the argument is being passed.  */
1530       mode4 = GET_MODE (reg);
1531
1532       /* Eliminate sign extensions in the callee when:
1533          (a) A mode promotion has occurred;  */
1534       if (mode1 == mode3)
1535         continue;
1536       /* (b) The mode of the register is the same as the mode of
1537              the argument as it is passed; */
1538       if (mode3 != mode4)
1539         continue;
1540       /* (c) There's no language level extension;  */
1541       if (mode1 == mode2)
1542         ;
1543       /* (c.1) All callers are from the current compilation unit.  If that's
1544          the case we don't have to rely on an ABI, we only have to know
1545          what we're generating right now, and we know that we will do the
1546          mode1 to mode2 promotion with the given sign.  */
1547       else if (!strictly_local)
1548         continue;
1549       /* (c.2) The combination of the two promotions is useful.  This is
1550          true when the signs match, or if the first promotion is unsigned.
1551          In the later case, (sign_extend (zero_extend x)) is the same as
1552          (zero_extend (zero_extend x)), so make sure to force UNS3 true.  */
1553       else if (uns1)
1554         uns3 = true;
1555       else if (uns3)
1556         continue;
1557
1558       /* Record that the value was promoted from mode1 to mode3,
1559          so that any sign extension at the head of the current
1560          function may be eliminated.  */
1561       x = gen_rtx_CLOBBER (mode1, const0_rtx);
1562       x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1563       record_value_for_reg (reg, first, x);
1564     }
1565 }
1566
1567 /* Called via note_stores.  If X is a pseudo that is narrower than
1568    HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1569
1570    If we are setting only a portion of X and we can't figure out what
1571    portion, assume all bits will be used since we don't know what will
1572    be happening.
1573
1574    Similarly, set how many bits of X are known to be copies of the sign bit
1575    at all locations in the function.  This is the smallest number implied
1576    by any set of X.  */
1577
1578 static void
1579 set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1580 {
1581   rtx insn = (rtx) data;
1582   unsigned int num;
1583
1584   if (REG_P (x)
1585       && REGNO (x) >= FIRST_PSEUDO_REGISTER
1586       /* If this register is undefined at the start of the file, we can't
1587          say what its contents were.  */
1588       && ! REGNO_REG_SET_P
1589            (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x))
1590       && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
1591     {
1592       reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
1593
1594       if (set == 0 || GET_CODE (set) == CLOBBER)
1595         {
1596           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1597           rsp->sign_bit_copies = 1;
1598           return;
1599         }
1600
1601       /* If this register is being initialized using itself, and the
1602          register is uninitialized in this basic block, and there are
1603          no LOG_LINKS which set the register, then part of the
1604          register is uninitialized.  In that case we can't assume
1605          anything about the number of nonzero bits.
1606
1607          ??? We could do better if we checked this in
1608          reg_{nonzero_bits,num_sign_bit_copies}_for_combine.  Then we
1609          could avoid making assumptions about the insn which initially
1610          sets the register, while still using the information in other
1611          insns.  We would have to be careful to check every insn
1612          involved in the combination.  */
1613
1614       if (insn
1615           && reg_referenced_p (x, PATTERN (insn))
1616           && !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1617                                REGNO (x)))
1618         {
1619           struct insn_link *link;
1620
1621           FOR_EACH_LOG_LINK (link, insn)
1622             if (dead_or_set_p (link->insn, x))
1623               break;
1624           if (!link)
1625             {
1626               rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1627               rsp->sign_bit_copies = 1;
1628               return;
1629             }
1630         }
1631
1632       /* If this is a complex assignment, see if we can convert it into a
1633          simple assignment.  */
1634       set = expand_field_assignment (set);
1635
1636       /* If this is a simple assignment, or we have a paradoxical SUBREG,
1637          set what we know about X.  */
1638
1639       if (SET_DEST (set) == x
1640           || (paradoxical_subreg_p (SET_DEST (set))
1641               && SUBREG_REG (SET_DEST (set)) == x))
1642         {
1643           rtx src = SET_SRC (set);
1644
1645 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1646           /* If X is narrower than a word and SRC is a non-negative
1647              constant that would appear negative in the mode of X,
1648              sign-extend it for use in reg_stat[].nonzero_bits because some
1649              machines (maybe most) will actually do the sign-extension
1650              and this is the conservative approach.
1651
1652              ??? For 2.5, try to tighten up the MD files in this regard
1653              instead of this kludge.  */
1654
1655           if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD
1656               && CONST_INT_P (src)
1657               && INTVAL (src) > 0
1658               && val_signbit_known_set_p (GET_MODE (x), INTVAL (src)))
1659             src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (GET_MODE (x)));
1660 #endif
1661
1662           /* Don't call nonzero_bits if it cannot change anything.  */
1663           if (rsp->nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1664             rsp->nonzero_bits |= nonzero_bits (src, nonzero_bits_mode);
1665           num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1666           if (rsp->sign_bit_copies == 0
1667               || rsp->sign_bit_copies > num)
1668             rsp->sign_bit_copies = num;
1669         }
1670       else
1671         {
1672           rsp->nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1673           rsp->sign_bit_copies = 1;
1674         }
1675     }
1676 }
1677 \f
1678 /* See if INSN can be combined into I3.  PRED, PRED2, SUCC and SUCC2 are
1679    optionally insns that were previously combined into I3 or that will be
1680    combined into the merger of INSN and I3.  The order is PRED, PRED2,
1681    INSN, SUCC, SUCC2, I3.
1682
1683    Return 0 if the combination is not allowed for any reason.
1684
1685    If the combination is allowed, *PDEST will be set to the single
1686    destination of INSN and *PSRC to the single source, and this function
1687    will return 1.  */
1688
1689 static int
1690 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED,
1691                rtx pred2 ATTRIBUTE_UNUSED, rtx succ, rtx succ2,
1692                rtx *pdest, rtx *psrc)
1693 {
1694   int i;
1695   const_rtx set = 0;
1696   rtx src, dest;
1697   rtx p;
1698 #ifdef AUTO_INC_DEC
1699   rtx link;
1700 #endif
1701   bool all_adjacent = true;
1702
1703   if (succ)
1704     {
1705       if (succ2)
1706         {
1707           if (next_active_insn (succ2) != i3)
1708             all_adjacent = false;
1709           if (next_active_insn (succ) != succ2)
1710             all_adjacent = false;
1711         }
1712       else if (next_active_insn (succ) != i3)
1713         all_adjacent = false;
1714       if (next_active_insn (insn) != succ)
1715         all_adjacent = false;
1716     }
1717   else if (next_active_insn (insn) != i3)
1718     all_adjacent = false;
1719
1720   /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1721      or a PARALLEL consisting of such a SET and CLOBBERs.
1722
1723      If INSN has CLOBBER parallel parts, ignore them for our processing.
1724      By definition, these happen during the execution of the insn.  When it
1725      is merged with another insn, all bets are off.  If they are, in fact,
1726      needed and aren't also supplied in I3, they may be added by
1727      recog_for_combine.  Otherwise, it won't match.
1728
1729      We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1730      note.
1731
1732      Get the source and destination of INSN.  If more than one, can't
1733      combine.  */
1734
1735   if (GET_CODE (PATTERN (insn)) == SET)
1736     set = PATTERN (insn);
1737   else if (GET_CODE (PATTERN (insn)) == PARALLEL
1738            && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1739     {
1740       for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1741         {
1742           rtx elt = XVECEXP (PATTERN (insn), 0, i);
1743
1744           switch (GET_CODE (elt))
1745             {
1746             /* This is important to combine floating point insns
1747                for the SH4 port.  */
1748             case USE:
1749               /* Combining an isolated USE doesn't make sense.
1750                  We depend here on combinable_i3pat to reject them.  */
1751               /* The code below this loop only verifies that the inputs of
1752                  the SET in INSN do not change.  We call reg_set_between_p
1753                  to verify that the REG in the USE does not change between
1754                  I3 and INSN.
1755                  If the USE in INSN was for a pseudo register, the matching
1756                  insn pattern will likely match any register; combining this
1757                  with any other USE would only be safe if we knew that the
1758                  used registers have identical values, or if there was
1759                  something to tell them apart, e.g. different modes.  For
1760                  now, we forgo such complicated tests and simply disallow
1761                  combining of USES of pseudo registers with any other USE.  */
1762               if (REG_P (XEXP (elt, 0))
1763                   && GET_CODE (PATTERN (i3)) == PARALLEL)
1764                 {
1765                   rtx i3pat = PATTERN (i3);
1766                   int i = XVECLEN (i3pat, 0) - 1;
1767                   unsigned int regno = REGNO (XEXP (elt, 0));
1768
1769                   do
1770                     {
1771                       rtx i3elt = XVECEXP (i3pat, 0, i);
1772
1773                       if (GET_CODE (i3elt) == USE
1774                           && REG_P (XEXP (i3elt, 0))
1775                           && (REGNO (XEXP (i3elt, 0)) == regno
1776                               ? reg_set_between_p (XEXP (elt, 0),
1777                                                    PREV_INSN (insn), i3)
1778                               : regno >= FIRST_PSEUDO_REGISTER))
1779                         return 0;
1780                     }
1781                   while (--i >= 0);
1782                 }
1783               break;
1784
1785               /* We can ignore CLOBBERs.  */
1786             case CLOBBER:
1787               break;
1788
1789             case SET:
1790               /* Ignore SETs whose result isn't used but not those that
1791                  have side-effects.  */
1792               if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1793                   && insn_nothrow_p (insn)
1794                   && !side_effects_p (elt))
1795                 break;
1796
1797               /* If we have already found a SET, this is a second one and
1798                  so we cannot combine with this insn.  */
1799               if (set)
1800                 return 0;
1801
1802               set = elt;
1803               break;
1804
1805             default:
1806               /* Anything else means we can't combine.  */
1807               return 0;
1808             }
1809         }
1810
1811       if (set == 0
1812           /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1813              so don't do anything with it.  */
1814           || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1815         return 0;
1816     }
1817   else
1818     return 0;
1819
1820   if (set == 0)
1821     return 0;
1822
1823   set = expand_field_assignment (set);
1824   src = SET_SRC (set), dest = SET_DEST (set);
1825
1826   /* Don't eliminate a store in the stack pointer.  */
1827   if (dest == stack_pointer_rtx
1828       /* Don't combine with an insn that sets a register to itself if it has
1829          a REG_EQUAL note.  This may be part of a LIBCALL sequence.  */
1830       || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1831       /* Can't merge an ASM_OPERANDS.  */
1832       || GET_CODE (src) == ASM_OPERANDS
1833       /* Can't merge a function call.  */
1834       || GET_CODE (src) == CALL
1835       /* Don't eliminate a function call argument.  */
1836       || (CALL_P (i3)
1837           && (find_reg_fusage (i3, USE, dest)
1838               || (REG_P (dest)
1839                   && REGNO (dest) < FIRST_PSEUDO_REGISTER
1840                   && global_regs[REGNO (dest)])))
1841       /* Don't substitute into an incremented register.  */
1842       || FIND_REG_INC_NOTE (i3, dest)
1843       || (succ && FIND_REG_INC_NOTE (succ, dest))
1844       || (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1845       /* Don't substitute into a non-local goto, this confuses CFG.  */
1846       || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1847       /* Make sure that DEST is not used after SUCC but before I3.  */
1848       || (!all_adjacent
1849           && ((succ2
1850                && (reg_used_between_p (dest, succ2, i3)
1851                    || reg_used_between_p (dest, succ, succ2)))
1852               || (!succ2 && succ && reg_used_between_p (dest, succ, i3))))
1853       /* Make sure that the value that is to be substituted for the register
1854          does not use any registers whose values alter in between.  However,
1855          If the insns are adjacent, a use can't cross a set even though we
1856          think it might (this can happen for a sequence of insns each setting
1857          the same destination; last_set of that register might point to
1858          a NOTE).  If INSN has a REG_EQUIV note, the register is always
1859          equivalent to the memory so the substitution is valid even if there
1860          are intervening stores.  Also, don't move a volatile asm or
1861          UNSPEC_VOLATILE across any other insns.  */
1862       || (! all_adjacent
1863           && (((!MEM_P (src)
1864                 || ! find_reg_note (insn, REG_EQUIV, src))
1865                && use_crosses_set_p (src, DF_INSN_LUID (insn)))
1866               || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1867               || GET_CODE (src) == UNSPEC_VOLATILE))
1868       /* Don't combine across a CALL_INSN, because that would possibly
1869          change whether the life span of some REGs crosses calls or not,
1870          and it is a pain to update that information.
1871          Exception: if source is a constant, moving it later can't hurt.
1872          Accept that as a special case.  */
1873       || (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1874     return 0;
1875
1876   /* DEST must either be a REG or CC0.  */
1877   if (REG_P (dest))
1878     {
1879       /* If register alignment is being enforced for multi-word items in all
1880          cases except for parameters, it is possible to have a register copy
1881          insn referencing a hard register that is not allowed to contain the
1882          mode being copied and which would not be valid as an operand of most
1883          insns.  Eliminate this problem by not combining with such an insn.
1884
1885          Also, on some machines we don't want to extend the life of a hard
1886          register.  */
1887
1888       if (REG_P (src)
1889           && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1890                && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1891               /* Don't extend the life of a hard register unless it is
1892                  user variable (if we have few registers) or it can't
1893                  fit into the desired register (meaning something special
1894                  is going on).
1895                  Also avoid substituting a return register into I3, because
1896                  reload can't handle a conflict with constraints of other
1897                  inputs.  */
1898               || (REGNO (src) < FIRST_PSEUDO_REGISTER
1899                   && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1900         return 0;
1901     }
1902   else if (GET_CODE (dest) != CC0)
1903     return 0;
1904
1905
1906   if (GET_CODE (PATTERN (i3)) == PARALLEL)
1907     for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1908       if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1909         {
1910           /* Don't substitute for a register intended as a clobberable
1911              operand.  */
1912           rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1913           if (rtx_equal_p (reg, dest))
1914             return 0;
1915
1916           /* If the clobber represents an earlyclobber operand, we must not
1917              substitute an expression containing the clobbered register.
1918              As we do not analyze the constraint strings here, we have to
1919              make the conservative assumption.  However, if the register is
1920              a fixed hard reg, the clobber cannot represent any operand;
1921              we leave it up to the machine description to either accept or
1922              reject use-and-clobber patterns.  */
1923           if (!REG_P (reg)
1924               || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1925               || !fixed_regs[REGNO (reg)])
1926             if (reg_overlap_mentioned_p (reg, src))
1927               return 0;
1928         }
1929
1930   /* If INSN contains anything volatile, or is an `asm' (whether volatile
1931      or not), reject, unless nothing volatile comes between it and I3 */
1932
1933   if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1934     {
1935       /* Make sure neither succ nor succ2 contains a volatile reference.  */
1936       if (succ2 != 0 && volatile_refs_p (PATTERN (succ2)))
1937         return 0;
1938       if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1939         return 0;
1940       /* We'll check insns between INSN and I3 below.  */
1941     }
1942
1943   /* If INSN is an asm, and DEST is a hard register, reject, since it has
1944      to be an explicit register variable, and was chosen for a reason.  */
1945
1946   if (GET_CODE (src) == ASM_OPERANDS
1947       && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1948     return 0;
1949
1950   /* If there are any volatile insns between INSN and I3, reject, because
1951      they might affect machine state.  */
1952
1953   for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1954     if (INSN_P (p) && p != succ && p != succ2 && volatile_insn_p (PATTERN (p)))
1955       return 0;
1956
1957   /* If INSN contains an autoincrement or autodecrement, make sure that
1958      register is not used between there and I3, and not already used in
1959      I3 either.  Neither must it be used in PRED or SUCC, if they exist.
1960      Also insist that I3 not be a jump; if it were one
1961      and the incremented register were spilled, we would lose.  */
1962
1963 #ifdef AUTO_INC_DEC
1964   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1965     if (REG_NOTE_KIND (link) == REG_INC
1966         && (JUMP_P (i3)
1967             || reg_used_between_p (XEXP (link, 0), insn, i3)
1968             || (pred != NULL_RTX
1969                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1970             || (pred2 != NULL_RTX
1971                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred2)))
1972             || (succ != NULL_RTX
1973                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1974             || (succ2 != NULL_RTX
1975                 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ2)))
1976             || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1977       return 0;
1978 #endif
1979
1980 #ifdef HAVE_cc0
1981   /* Don't combine an insn that follows a CC0-setting insn.
1982      An insn that uses CC0 must not be separated from the one that sets it.
1983      We do, however, allow I2 to follow a CC0-setting insn if that insn
1984      is passed as I1; in that case it will be deleted also.
1985      We also allow combining in this case if all the insns are adjacent
1986      because that would leave the two CC0 insns adjacent as well.
1987      It would be more logical to test whether CC0 occurs inside I1 or I2,
1988      but that would be much slower, and this ought to be equivalent.  */
1989
1990   p = prev_nonnote_insn (insn);
1991   if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1992       && ! all_adjacent)
1993     return 0;
1994 #endif
1995
1996   /* If we get here, we have passed all the tests and the combination is
1997      to be allowed.  */
1998
1999   *pdest = dest;
2000   *psrc = src;
2001
2002   return 1;
2003 }
2004 \f
2005 /* LOC is the location within I3 that contains its pattern or the component
2006    of a PARALLEL of the pattern.  We validate that it is valid for combining.
2007
2008    One problem is if I3 modifies its output, as opposed to replacing it
2009    entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2010    doing so would produce an insn that is not equivalent to the original insns.
2011
2012    Consider:
2013
2014          (set (reg:DI 101) (reg:DI 100))
2015          (set (subreg:SI (reg:DI 101) 0) <foo>)
2016
2017    This is NOT equivalent to:
2018
2019          (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2020                     (set (reg:DI 101) (reg:DI 100))])
2021
2022    Not only does this modify 100 (in which case it might still be valid
2023    if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2024
2025    We can also run into a problem if I2 sets a register that I1
2026    uses and I1 gets directly substituted into I3 (not via I2).  In that
2027    case, we would be getting the wrong value of I2DEST into I3, so we
2028    must reject the combination.  This case occurs when I2 and I1 both
2029    feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2030    If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2031    of a SET must prevent combination from occurring.  The same situation
2032    can occur for I0, in which case I0_NOT_IN_SRC is set.
2033
2034    Before doing the above check, we first try to expand a field assignment
2035    into a set of logical operations.
2036
2037    If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2038    we place a register that is both set and used within I3.  If more than one
2039    such register is detected, we fail.
2040
2041    Return 1 if the combination is valid, zero otherwise.  */
2042
2043 static int
2044 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2045                   int i1_not_in_src, int i0_not_in_src, rtx *pi3dest_killed)
2046 {
2047   rtx x = *loc;
2048
2049   if (GET_CODE (x) == SET)
2050     {
2051       rtx set = x ;
2052       rtx dest = SET_DEST (set);
2053       rtx src = SET_SRC (set);
2054       rtx inner_dest = dest;
2055       rtx subdest;
2056
2057       while (GET_CODE (inner_dest) == STRICT_LOW_PART
2058              || GET_CODE (inner_dest) == SUBREG
2059              || GET_CODE (inner_dest) == ZERO_EXTRACT)
2060         inner_dest = XEXP (inner_dest, 0);
2061
2062       /* Check for the case where I3 modifies its output, as discussed
2063          above.  We don't want to prevent pseudos from being combined
2064          into the address of a MEM, so only prevent the combination if
2065          i1 or i2 set the same MEM.  */
2066       if ((inner_dest != dest &&
2067            (!MEM_P (inner_dest)
2068             || rtx_equal_p (i2dest, inner_dest)
2069             || (i1dest && rtx_equal_p (i1dest, inner_dest))
2070             || (i0dest && rtx_equal_p (i0dest, inner_dest)))
2071            && (reg_overlap_mentioned_p (i2dest, inner_dest)
2072                || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2073                || (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2074
2075           /* This is the same test done in can_combine_p except we can't test
2076              all_adjacent; we don't have to, since this instruction will stay
2077              in place, thus we are not considering increasing the lifetime of
2078              INNER_DEST.
2079
2080              Also, if this insn sets a function argument, combining it with
2081              something that might need a spill could clobber a previous
2082              function argument; the all_adjacent test in can_combine_p also
2083              checks this; here, we do a more specific test for this case.  */
2084
2085           || (REG_P (inner_dest)
2086               && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2087               && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
2088                                         GET_MODE (inner_dest))))
2089           || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2090           || (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2091         return 0;
2092
2093       /* If DEST is used in I3, it is being killed in this insn, so
2094          record that for later.  We have to consider paradoxical
2095          subregs here, since they kill the whole register, but we
2096          ignore partial subregs, STRICT_LOW_PART, etc.
2097          Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2098          STACK_POINTER_REGNUM, since these are always considered to be
2099          live.  Similarly for ARG_POINTER_REGNUM if it is fixed.  */
2100       subdest = dest;
2101       if (GET_CODE (subdest) == SUBREG
2102           && (GET_MODE_SIZE (GET_MODE (subdest))
2103               >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
2104         subdest = SUBREG_REG (subdest);
2105       if (pi3dest_killed
2106           && REG_P (subdest)
2107           && reg_referenced_p (subdest, PATTERN (i3))
2108           && REGNO (subdest) != FRAME_POINTER_REGNUM
2109 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
2110           && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
2111 #endif
2112 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
2113           && (REGNO (subdest) != ARG_POINTER_REGNUM
2114               || ! fixed_regs [REGNO (subdest)])
2115 #endif
2116           && REGNO (subdest) != STACK_POINTER_REGNUM)
2117         {
2118           if (*pi3dest_killed)
2119             return 0;
2120
2121           *pi3dest_killed = subdest;
2122         }
2123     }
2124
2125   else if (GET_CODE (x) == PARALLEL)
2126     {
2127       int i;
2128
2129       for (i = 0; i < XVECLEN (x, 0); i++)
2130         if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2131                                 i1_not_in_src, i0_not_in_src, pi3dest_killed))
2132           return 0;
2133     }
2134
2135   return 1;
2136 }
2137 \f
2138 /* Return 1 if X is an arithmetic expression that contains a multiplication
2139    and division.  We don't count multiplications by powers of two here.  */
2140
2141 static int
2142 contains_muldiv (rtx x)
2143 {
2144   switch (GET_CODE (x))
2145     {
2146     case MOD:  case DIV:  case UMOD:  case UDIV:
2147       return 1;
2148
2149     case MULT:
2150       return ! (CONST_INT_P (XEXP (x, 1))
2151                 && exact_log2 (UINTVAL (XEXP (x, 1))) >= 0);
2152     default:
2153       if (BINARY_P (x))
2154         return contains_muldiv (XEXP (x, 0))
2155             || contains_muldiv (XEXP (x, 1));
2156
2157       if (UNARY_P (x))
2158         return contains_muldiv (XEXP (x, 0));
2159
2160       return 0;
2161     }
2162 }
2163 \f
2164 /* Determine whether INSN can be used in a combination.  Return nonzero if
2165    not.  This is used in try_combine to detect early some cases where we
2166    can't perform combinations.  */
2167
2168 static int
2169 cant_combine_insn_p (rtx insn)
2170 {
2171   rtx set;
2172   rtx src, dest;
2173
2174   /* If this isn't really an insn, we can't do anything.
2175      This can occur when flow deletes an insn that it has merged into an
2176      auto-increment address.  */
2177   if (! INSN_P (insn))
2178     return 1;
2179
2180   /* Never combine loads and stores involving hard regs that are likely
2181      to be spilled.  The register allocator can usually handle such
2182      reg-reg moves by tying.  If we allow the combiner to make
2183      substitutions of likely-spilled regs, reload might die.
2184      As an exception, we allow combinations involving fixed regs; these are
2185      not available to the register allocator so there's no risk involved.  */
2186
2187   set = single_set (insn);
2188   if (! set)
2189     return 0;
2190   src = SET_SRC (set);
2191   dest = SET_DEST (set);
2192   if (GET_CODE (src) == SUBREG)
2193     src = SUBREG_REG (src);
2194   if (GET_CODE (dest) == SUBREG)
2195     dest = SUBREG_REG (dest);
2196   if (REG_P (src) && REG_P (dest)
2197       && ((HARD_REGISTER_P (src)
2198            && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2199            && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (src))))
2200           || (HARD_REGISTER_P (dest)
2201               && ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2202               && targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2203     return 1;
2204
2205   return 0;
2206 }
2207
2208 struct likely_spilled_retval_info
2209 {
2210   unsigned regno, nregs;
2211   unsigned mask;
2212 };
2213
2214 /* Called via note_stores by likely_spilled_retval_p.  Remove from info->mask
2215    hard registers that are known to be written to / clobbered in full.  */
2216 static void
2217 likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2218 {
2219   struct likely_spilled_retval_info *const info =
2220     (struct likely_spilled_retval_info *) data;
2221   unsigned regno, nregs;
2222   unsigned new_mask;
2223
2224   if (!REG_P (XEXP (set, 0)))
2225     return;
2226   regno = REGNO (x);
2227   if (regno >= info->regno + info->nregs)
2228     return;
2229   nregs = hard_regno_nregs[regno][GET_MODE (x)];
2230   if (regno + nregs <= info->regno)
2231     return;
2232   new_mask = (2U << (nregs - 1)) - 1;
2233   if (regno < info->regno)
2234     new_mask >>= info->regno - regno;
2235   else
2236     new_mask <<= regno - info->regno;
2237   info->mask &= ~new_mask;
2238 }
2239
2240 /* Return nonzero iff part of the return value is live during INSN, and
2241    it is likely spilled.  This can happen when more than one insn is needed
2242    to copy the return value, e.g. when we consider to combine into the
2243    second copy insn for a complex value.  */
2244
2245 static int
2246 likely_spilled_retval_p (rtx insn)
2247 {
2248   rtx use = BB_END (this_basic_block);
2249   rtx reg, p;
2250   unsigned regno, nregs;
2251   /* We assume here that no machine mode needs more than
2252      32 hard registers when the value overlaps with a register
2253      for which TARGET_FUNCTION_VALUE_REGNO_P is true.  */
2254   unsigned mask;
2255   struct likely_spilled_retval_info info;
2256
2257   if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2258     return 0;
2259   reg = XEXP (PATTERN (use), 0);
2260   if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2261     return 0;
2262   regno = REGNO (reg);
2263   nregs = hard_regno_nregs[regno][GET_MODE (reg)];
2264   if (nregs == 1)
2265     return 0;
2266   mask = (2U << (nregs - 1)) - 1;
2267
2268   /* Disregard parts of the return value that are set later.  */
2269   info.regno = regno;
2270   info.nregs = nregs;
2271   info.mask = mask;
2272   for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
2273     if (INSN_P (p))
2274       note_stores (PATTERN (p), likely_spilled_retval_1, &info);
2275   mask = info.mask;
2276
2277   /* Check if any of the (probably) live return value registers is
2278      likely spilled.  */
2279   nregs --;
2280   do
2281     {
2282       if ((mask & 1 << nregs)
2283           && targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2284         return 1;
2285     } while (nregs--);
2286   return 0;
2287 }
2288
2289 /* Adjust INSN after we made a change to its destination.
2290
2291    Changing the destination can invalidate notes that say something about
2292    the results of the insn and a LOG_LINK pointing to the insn.  */
2293
2294 static void
2295 adjust_for_new_dest (rtx insn)
2296 {
2297   /* For notes, be conservative and simply remove them.  */
2298   remove_reg_equal_equiv_notes (insn);
2299
2300   /* The new insn will have a destination that was previously the destination
2301      of an insn just above it.  Call distribute_links to make a LOG_LINK from
2302      the next use of that destination.  */
2303   distribute_links (alloc_insn_link (insn, NULL));
2304
2305   df_insn_rescan (insn);
2306 }
2307
2308 /* Return TRUE if combine can reuse reg X in mode MODE.
2309    ADDED_SETS is nonzero if the original set is still required.  */
2310 static bool
2311 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
2312 {
2313   unsigned int regno;
2314
2315   if (!REG_P(x))
2316     return false;
2317
2318   regno = REGNO (x);
2319   /* Allow hard registers if the new mode is legal, and occupies no more
2320      registers than the old mode.  */
2321   if (regno < FIRST_PSEUDO_REGISTER)
2322     return (HARD_REGNO_MODE_OK (regno, mode)
2323             && (hard_regno_nregs[regno][GET_MODE (x)]
2324                 >= hard_regno_nregs[regno][mode]));
2325
2326   /* Or a pseudo that is only used once.  */
2327   return (REG_N_SETS (regno) == 1 && !added_sets
2328           && !REG_USERVAR_P (x));
2329 }
2330
2331
2332 /* Check whether X, the destination of a set, refers to part of
2333    the register specified by REG.  */
2334
2335 static bool
2336 reg_subword_p (rtx x, rtx reg)
2337 {
2338   /* Check that reg is an integer mode register.  */
2339   if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2340     return false;
2341
2342   if (GET_CODE (x) == STRICT_LOW_PART
2343       || GET_CODE (x) == ZERO_EXTRACT)
2344     x = XEXP (x, 0);
2345
2346   return GET_CODE (x) == SUBREG
2347          && SUBREG_REG (x) == reg
2348          && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2349 }
2350
2351 #ifdef AUTO_INC_DEC
2352 /* Replace auto-increment addressing modes with explicit operations to access
2353    the same addresses without modifying the corresponding registers.  */
2354
2355 static rtx
2356 cleanup_auto_inc_dec (rtx src, enum machine_mode mem_mode)
2357 {
2358   rtx x = src;
2359   const RTX_CODE code = GET_CODE (x);
2360   int i;
2361   const char *fmt;
2362
2363   switch (code)
2364     {
2365     case REG:
2366     case CONST_INT:
2367     case CONST_DOUBLE:
2368     case CONST_FIXED:
2369     case CONST_VECTOR:
2370     case SYMBOL_REF:
2371     case CODE_LABEL:
2372     case PC:
2373     case CC0:
2374     case SCRATCH:
2375       /* SCRATCH must be shared because they represent distinct values.  */
2376       return x;
2377     case CLOBBER:
2378       if (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
2379         return x;
2380       break;
2381
2382     case CONST:
2383       if (shared_const_p (x))
2384         return x;
2385       break;
2386
2387     case MEM:
2388       mem_mode = GET_MODE (x);
2389       break;
2390
2391     case PRE_INC:
2392     case PRE_DEC:
2393       gcc_assert (mem_mode != VOIDmode && mem_mode != BLKmode);
2394       return gen_rtx_PLUS (GET_MODE (x),
2395                            cleanup_auto_inc_dec (XEXP (x, 0), mem_mode),
2396                            GEN_INT (code == PRE_INC
2397                                     ? GET_MODE_SIZE (mem_mode)
2398                                     : -GET_MODE_SIZE (mem_mode)));
2399
2400     case POST_INC:
2401     case POST_DEC:
2402     case PRE_MODIFY:
2403     case POST_MODIFY:
2404       return cleanup_auto_inc_dec (code == PRE_MODIFY
2405                                    ? XEXP (x, 1) : XEXP (x, 0),
2406                                    mem_mode);
2407
2408     default:
2409       break;
2410     }
2411
2412   /* Copy the various flags, fields, and other information.  We assume
2413      that all fields need copying, and then clear the fields that should
2414      not be copied.  That is the sensible default behavior, and forces
2415      us to explicitly document why we are *not* copying a flag.  */
2416   x = shallow_copy_rtx (x);
2417
2418   /* We do not copy the USED flag, which is used as a mark bit during
2419      walks over the RTL.  */
2420   RTX_FLAG (x, used) = 0;
2421
2422   /* We do not copy FRAME_RELATED for INSNs.  */
2423   if (INSN_P (x))
2424     RTX_FLAG (x, frame_related) = 0;
2425
2426   fmt = GET_RTX_FORMAT (code);
2427   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2428     if (fmt[i] == 'e')
2429       XEXP (x, i) = cleanup_auto_inc_dec (XEXP (x, i), mem_mode);
2430     else if (fmt[i] == 'E' || fmt[i] == 'V')
2431       {
2432         int j;
2433         XVEC (x, i) = rtvec_alloc (XVECLEN (x, i));
2434         for (j = 0; j < XVECLEN (x, i); j++)
2435           XVECEXP (x, i, j)
2436             = cleanup_auto_inc_dec (XVECEXP (src, i, j), mem_mode);
2437       }
2438
2439   return x;
2440 }
2441 #endif
2442
2443 /* Auxiliary data structure for propagate_for_debug_stmt.  */
2444
2445 struct rtx_subst_pair
2446 {
2447   rtx to;
2448   bool adjusted;
2449 };
2450
2451 /* DATA points to an rtx_subst_pair.  Return the value that should be
2452    substituted.  */
2453
2454 static rtx
2455 propagate_for_debug_subst (rtx from, const_rtx old_rtx, void *data)
2456 {
2457   struct rtx_subst_pair *pair = (struct rtx_subst_pair *)data;
2458
2459   if (!rtx_equal_p (from, old_rtx))
2460     return NULL_RTX;
2461   if (!pair->adjusted)
2462     {
2463       pair->adjusted = true;
2464 #ifdef AUTO_INC_DEC
2465       pair->to = cleanup_auto_inc_dec (pair->to, VOIDmode);
2466 #else
2467       pair->to = copy_rtx (pair->to);
2468 #endif
2469       pair->to = make_compound_operation (pair->to, SET);
2470       return pair->to;
2471     }
2472   return copy_rtx (pair->to);
2473 }
2474
2475 /* Replace all the occurrences of DEST with SRC in DEBUG_INSNs between INSN
2476    and LAST, not including INSN, but including LAST.  Also stop at the end
2477    of THIS_BASIC_BLOCK.  */
2478
2479 static void
2480 propagate_for_debug (rtx insn, rtx last, rtx dest, rtx src)
2481 {
2482   rtx next, loc, end = NEXT_INSN (BB_END (this_basic_block));
2483
2484   struct rtx_subst_pair p;
2485   p.to = src;
2486   p.adjusted = false;
2487
2488   next = NEXT_INSN (insn);
2489   last = NEXT_INSN (last);
2490   while (next != last && next != end)
2491     {
2492       insn = next;
2493       next = NEXT_INSN (insn);
2494       if (DEBUG_INSN_P (insn))
2495         {
2496           loc = simplify_replace_fn_rtx (INSN_VAR_LOCATION_LOC (insn),
2497                                          dest, propagate_for_debug_subst, &p);
2498           if (loc == INSN_VAR_LOCATION_LOC (insn))
2499             continue;
2500           INSN_VAR_LOCATION_LOC (insn) = loc;
2501           df_insn_rescan (insn);
2502         }
2503     }
2504 }
2505
2506 /* Delete the unconditional jump INSN and adjust the CFG correspondingly.
2507    Note that the INSN should be deleted *after* removing dead edges, so
2508    that the kept edge is the fallthrough edge for a (set (pc) (pc))
2509    but not for a (set (pc) (label_ref FOO)).  */
2510
2511 static void
2512 update_cfg_for_uncondjump (rtx insn)
2513 {
2514   basic_block bb = BLOCK_FOR_INSN (insn);
2515   gcc_assert (BB_END (bb) == insn);
2516
2517   purge_dead_edges (bb);
2518
2519   delete_insn (insn);
2520   if (EDGE_COUNT (bb->succs) == 1)
2521     {
2522       rtx insn;
2523
2524       single_succ_edge (bb)->flags |= EDGE_FALLTHRU;
2525
2526       /* Remove barriers from the footer if there are any.  */
2527       for (insn = bb->il.rtl->footer; insn; insn = NEXT_INSN (insn))
2528         if (BARRIER_P (insn))
2529           {
2530             if (PREV_INSN (insn))
2531               NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
2532             else
2533               bb->il.rtl->footer = NEXT_INSN (insn);
2534             if (NEXT_INSN (insn))
2535               PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
2536           }
2537         else if (LABEL_P (insn))
2538           break;
2539     }
2540 }
2541
2542 /* Try to combine the insns I0, I1 and I2 into I3.
2543    Here I0, I1 and I2 appear earlier than I3.
2544    I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2545    I3.
2546
2547    If we are combining more than two insns and the resulting insn is not
2548    recognized, try splitting it into two insns.  If that happens, I2 and I3
2549    are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2550    Otherwise, I0, I1 and I2 are pseudo-deleted.
2551
2552    Return 0 if the combination does not work.  Then nothing is changed.
2553    If we did the combination, return the insn at which combine should
2554    resume scanning.
2555
2556    Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
2557    new direct jump instruction.
2558
2559    LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2560    been I3 passed to an earlier try_combine within the same basic
2561    block.  */
2562
2563 static rtx
2564 try_combine (rtx i3, rtx i2, rtx i1, rtx i0, int *new_direct_jump_p,
2565              rtx last_combined_insn)
2566 {
2567   /* New patterns for I3 and I2, respectively.  */
2568   rtx newpat, newi2pat = 0;
2569   rtvec newpat_vec_with_clobbers = 0;
2570   int substed_i2 = 0, substed_i1 = 0, substed_i0 = 0;
2571   /* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2572      dead.  */
2573   int added_sets_0, added_sets_1, added_sets_2;
2574   /* Total number of SETs to put into I3.  */
2575   int total_sets;
2576   /* Nonzero if I2's or I1's body now appears in I3.  */
2577   int i2_is_used = 0, i1_is_used = 0;
2578   /* INSN_CODEs for new I3, new I2, and user of condition code.  */
2579   int insn_code_number, i2_code_number = 0, other_code_number = 0;
2580   /* Contains I3 if the destination of I3 is used in its source, which means
2581      that the old life of I3 is being killed.  If that usage is placed into
2582      I2 and not in I3, a REG_DEAD note must be made.  */
2583   rtx i3dest_killed = 0;
2584   /* SET_DEST and SET_SRC of I2, I1 and I0.  */
2585   rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2586   /* Copy of SET_SRC of I1, if needed.  */
2587   rtx i1src_copy = 0;
2588   /* Set if I2DEST was reused as a scratch register.  */
2589   bool i2scratch = false;
2590   /* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases.  */
2591   rtx i0pat = 0, i1pat = 0, i2pat = 0;
2592   /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC.  */
2593   int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
2594   int i0dest_in_i0src = 0, i1dest_in_i0src = 0, i2dest_in_i0src = 0;
2595   int i2dest_killed = 0, i1dest_killed = 0, i0dest_killed = 0;
2596   int i1_feeds_i2_n = 0, i0_feeds_i2_n = 0, i0_feeds_i1_n = 0;
2597   /* Notes that must be added to REG_NOTES in I3 and I2.  */
2598   rtx new_i3_notes, new_i2_notes;
2599   /* Notes that we substituted I3 into I2 instead of the normal case.  */
2600   int i3_subst_into_i2 = 0;
2601   /* Notes that I1, I2 or I3 is a MULT operation.  */
2602   int have_mult = 0;
2603   int swap_i2i3 = 0;
2604   int changed_i3_dest = 0;
2605
2606   int maxreg;
2607   rtx temp;
2608   struct insn_link *link;
2609   rtx other_pat = 0;
2610   rtx new_other_notes;
2611   int i;
2612
2613   /* Only try four-insn combinations when there's high likelihood of
2614      success.  Look for simple insns, such as loads of constants or
2615      binary operations involving a constant.  */
2616   if (i0)
2617     {
2618       int i;
2619       int ngood = 0;
2620       int nshift = 0;
2621
2622       if (!flag_expensive_optimizations)
2623         return 0;
2624
2625       for (i = 0; i < 4; i++)
2626         {
2627           rtx insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2628           rtx set = single_set (insn);
2629           rtx src;
2630           if (!set)
2631             continue;
2632           src = SET_SRC (set);
2633           if (CONSTANT_P (src))
2634             {
2635               ngood += 2;
2636               break;
2637             }
2638           else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2639             ngood++;
2640           else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2641                    || GET_CODE (src) == LSHIFTRT)
2642             nshift++;
2643         }
2644       if (ngood < 2 && nshift < 2)
2645         return 0;
2646     }
2647
2648   /* Exit early if one of the insns involved can't be used for
2649      combinations.  */
2650   if (cant_combine_insn_p (i3)
2651       || cant_combine_insn_p (i2)
2652       || (i1 && cant_combine_insn_p (i1))
2653       || (i0 && cant_combine_insn_p (i0))
2654       || likely_spilled_retval_p (i3))
2655     return 0;
2656
2657   combine_attempts++;
2658   undobuf.other_insn = 0;
2659
2660   /* Reset the hard register usage information.  */
2661   CLEAR_HARD_REG_SET (newpat_used_regs);
2662
2663   if (dump_file && (dump_flags & TDF_DETAILS))
2664     {
2665       if (i0)
2666         fprintf (dump_file, "\nTrying %d, %d, %d -> %d:\n",
2667                  INSN_UID (i0), INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2668       else if (i1)
2669         fprintf (dump_file, "\nTrying %d, %d -> %d:\n",
2670                  INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
2671       else
2672         fprintf (dump_file, "\nTrying %d -> %d:\n",
2673                  INSN_UID (i2), INSN_UID (i3));
2674     }
2675
2676   /* If multiple insns feed into one of I2 or I3, they can be in any
2677      order.  To simplify the code below, reorder them in sequence.  */
2678   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2679     temp = i2, i2 = i0, i0 = temp;
2680   if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2681     temp = i1, i1 = i0, i0 = temp;
2682   if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2683     temp = i1, i1 = i2, i2 = temp;
2684
2685   added_links_insn = 0;
2686
2687   /* First check for one important special case that the code below will
2688      not handle.  Namely, the case where I1 is zero, I2 is a PARALLEL
2689      and I3 is a SET whose SET_SRC is a SET_DEST in I2.  In that case,
2690      we may be able to replace that destination with the destination of I3.
2691      This occurs in the common code where we compute both a quotient and
2692      remainder into a structure, in which case we want to do the computation
2693      directly into the structure to avoid register-register copies.
2694
2695      Note that this case handles both multiple sets in I2 and also cases
2696      where I2 has a number of CLOBBERs inside the PARALLEL.
2697
2698      We make very conservative checks below and only try to handle the
2699      most common cases of this.  For example, we only handle the case
2700      where I2 and I3 are adjacent to avoid making difficult register
2701      usage tests.  */
2702
2703   if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2704       && REG_P (SET_SRC (PATTERN (i3)))
2705       && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2706       && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2707       && GET_CODE (PATTERN (i2)) == PARALLEL
2708       && ! side_effects_p (SET_DEST (PATTERN (i3)))
2709       /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2710          below would need to check what is inside (and reg_overlap_mentioned_p
2711          doesn't support those codes anyway).  Don't allow those destinations;
2712          the resulting insn isn't likely to be recognized anyway.  */
2713       && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2714       && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2715       && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2716                                     SET_DEST (PATTERN (i3)))
2717       && next_active_insn (i2) == i3)
2718     {
2719       rtx p2 = PATTERN (i2);
2720
2721       /* Make sure that the destination of I3,
2722          which we are going to substitute into one output of I2,
2723          is not used within another output of I2.  We must avoid making this:
2724          (parallel [(set (mem (reg 69)) ...)
2725                     (set (reg 69) ...)])
2726          which is not well-defined as to order of actions.
2727          (Besides, reload can't handle output reloads for this.)
2728
2729          The problem can also happen if the dest of I3 is a memory ref,
2730          if another dest in I2 is an indirect memory ref.  */
2731       for (i = 0; i < XVECLEN (p2, 0); i++)
2732         if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2733              || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2734             && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2735                                         SET_DEST (XVECEXP (p2, 0, i))))
2736           break;
2737
2738       if (i == XVECLEN (p2, 0))
2739         for (i = 0; i < XVECLEN (p2, 0); i++)
2740           if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2741               && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2742             {
2743               combine_merges++;
2744
2745               subst_insn = i3;
2746               subst_low_luid = DF_INSN_LUID (i2);
2747
2748               added_sets_2 = added_sets_1 = added_sets_0 = 0;
2749               i2src = SET_SRC (XVECEXP (p2, 0, i));
2750               i2dest = SET_DEST (XVECEXP (p2, 0, i));
2751               i2dest_killed = dead_or_set_p (i2, i2dest);
2752
2753               /* Replace the dest in I2 with our dest and make the resulting
2754                  insn the new pattern for I3.  Then skip to where we validate
2755                  the pattern.  Everything was set up above.  */
2756               SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2757               newpat = p2;
2758               i3_subst_into_i2 = 1;
2759               goto validate_replacement;
2760             }
2761     }
2762
2763   /* If I2 is setting a pseudo to a constant and I3 is setting some
2764      sub-part of it to another constant, merge them by making a new
2765      constant.  */
2766   if (i1 == 0
2767       && (temp = single_set (i2)) != 0
2768       && (CONST_INT_P (SET_SRC (temp))
2769           || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
2770       && GET_CODE (PATTERN (i3)) == SET
2771       && (CONST_INT_P (SET_SRC (PATTERN (i3)))
2772           || GET_CODE (SET_SRC (PATTERN (i3))) == CONST_DOUBLE)
2773       && reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp)))
2774     {
2775       rtx dest = SET_DEST (PATTERN (i3));
2776       int offset = -1;
2777       int width = 0;
2778
2779       if (GET_CODE (dest) == ZERO_EXTRACT)
2780         {
2781           if (CONST_INT_P (XEXP (dest, 1))
2782               && CONST_INT_P (XEXP (dest, 2)))
2783             {
2784               width = INTVAL (XEXP (dest, 1));
2785               offset = INTVAL (XEXP (dest, 2));
2786               dest = XEXP (dest, 0);
2787               if (BITS_BIG_ENDIAN)
2788                 offset = GET_MODE_PRECISION (GET_MODE (dest)) - width - offset;
2789             }
2790         }
2791       else
2792         {
2793           if (GET_CODE (dest) == STRICT_LOW_PART)
2794             dest = XEXP (dest, 0);
2795           width = GET_MODE_PRECISION (GET_MODE (dest));
2796           offset = 0;
2797         }
2798
2799       if (offset >= 0)
2800         {
2801           /* If this is the low part, we're done.  */
2802           if (subreg_lowpart_p (dest))
2803             ;
2804           /* Handle the case where inner is twice the size of outer.  */
2805           else if (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2806                    == 2 * GET_MODE_PRECISION (GET_MODE (dest)))
2807             offset += GET_MODE_PRECISION (GET_MODE (dest));
2808           /* Otherwise give up for now.  */
2809           else
2810             offset = -1;
2811         }
2812
2813       if (offset >= 0
2814           && (GET_MODE_PRECISION (GET_MODE (SET_DEST (temp)))
2815               <= HOST_BITS_PER_DOUBLE_INT))
2816         {
2817           double_int m, o, i;
2818           rtx inner = SET_SRC (PATTERN (i3));
2819           rtx outer = SET_SRC (temp);
2820
2821           o = rtx_to_double_int (outer);
2822           i = rtx_to_double_int (inner);
2823
2824           m = double_int_mask (width);
2825           i = double_int_and (i, m);
2826           m = double_int_lshift (m, offset, HOST_BITS_PER_DOUBLE_INT, false);
2827           i = double_int_lshift (i, offset, HOST_BITS_PER_DOUBLE_INT, false);
2828           o = double_int_ior (double_int_and_not (o, m), i);
2829
2830           combine_merges++;
2831           subst_insn = i3;
2832           subst_low_luid = DF_INSN_LUID (i2);
2833           added_sets_2 = added_sets_1 = added_sets_0 = 0;
2834           i2dest = SET_DEST (temp);
2835           i2dest_killed = dead_or_set_p (i2, i2dest);
2836
2837           /* Replace the source in I2 with the new constant and make the
2838              resulting insn the new pattern for I3.  Then skip to where we
2839              validate the pattern.  Everything was set up above.  */
2840           SUBST (SET_SRC (temp),
2841                  immed_double_int_const (o, GET_MODE (SET_DEST (temp))));
2842
2843           newpat = PATTERN (i2);
2844
2845           /* The dest of I3 has been replaced with the dest of I2.  */
2846           changed_i3_dest = 1;
2847           goto validate_replacement;
2848         }
2849     }
2850
2851 #ifndef HAVE_cc0
2852   /* If we have no I1 and I2 looks like:
2853         (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2854                    (set Y OP)])
2855      make up a dummy I1 that is
2856         (set Y OP)
2857      and change I2 to be
2858         (set (reg:CC X) (compare:CC Y (const_int 0)))
2859
2860      (We can ignore any trailing CLOBBERs.)
2861
2862      This undoes a previous combination and allows us to match a branch-and-
2863      decrement insn.  */
2864
2865   if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
2866       && XVECLEN (PATTERN (i2), 0) >= 2
2867       && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
2868       && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2869           == MODE_CC)
2870       && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2871       && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2872       && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
2873       && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
2874       && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2875                       SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
2876     {
2877       for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
2878         if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
2879           break;
2880
2881       if (i == 1)
2882         {
2883           /* We make I1 with the same INSN_UID as I2.  This gives it
2884              the same DF_INSN_LUID for value tracking.  Our fake I1 will
2885              never appear in the insn stream so giving it the same INSN_UID
2886              as I2 will not cause a problem.  */
2887
2888           i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
2889                              BLOCK_FOR_INSN (i2), XVECEXP (PATTERN (i2), 0, 1),
2890                              INSN_LOCATOR (i2), -1, NULL_RTX);
2891
2892           SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2893           SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2894                  SET_DEST (PATTERN (i1)));
2895           SUBST_LINK (LOG_LINKS (i2), alloc_insn_link (i1, LOG_LINKS (i2)));
2896         }
2897     }
2898 #endif
2899
2900   /* Verify that I2 and I1 are valid for combining.  */
2901   if (! can_combine_p (i2, i3, i0, i1, NULL_RTX, NULL_RTX, &i2dest, &i2src)
2902       || (i1 && ! can_combine_p (i1, i3, i0, NULL_RTX, i2, NULL_RTX,
2903                                  &i1dest, &i1src))
2904       || (i0 && ! can_combine_p (i0, i3, NULL_RTX, NULL_RTX, i1, i2,
2905                                  &i0dest, &i0src)))
2906     {
2907       undo_all ();
2908       return 0;
2909     }
2910
2911   /* Record whether I2DEST is used in I2SRC and similarly for the other
2912      cases.  Knowing this will help in register status updating below.  */
2913   i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2914   i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2915   i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2916   i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2917   i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2918   i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2919   i2dest_killed = dead_or_set_p (i2, i2dest);
2920   i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2921   i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2922
2923   /* For the earlier insns, determine which of the subsequent ones they
2924      feed.  */
2925   i1_feeds_i2_n = i1 && insn_a_feeds_b (i1, i2);
2926   i0_feeds_i1_n = i0 && insn_a_feeds_b (i0, i1);
2927   i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (i0, i2)
2928                           : (!reg_overlap_mentioned_p (i1dest, i0dest)
2929                              && reg_overlap_mentioned_p (i0dest, i2src))));
2930
2931   /* Ensure that I3's pattern can be the destination of combines.  */
2932   if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest, i0dest,
2933                           i1 && i2dest_in_i1src && !i1_feeds_i2_n,
2934                           i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
2935                                  || (i1dest_in_i0src && !i0_feeds_i1_n)),
2936                           &i3dest_killed))
2937     {
2938       undo_all ();
2939       return 0;
2940     }
2941
2942   /* See if any of the insns is a MULT operation.  Unless one is, we will
2943      reject a combination that is, since it must be slower.  Be conservative
2944      here.  */
2945   if (GET_CODE (i2src) == MULT
2946       || (i1 != 0 && GET_CODE (i1src) == MULT)
2947       || (i0 != 0 && GET_CODE (i0src) == MULT)
2948       || (GET_CODE (PATTERN (i3)) == SET
2949           && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2950     have_mult = 1;
2951
2952   /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2953      We used to do this EXCEPT in one case: I3 has a post-inc in an
2954      output operand.  However, that exception can give rise to insns like
2955         mov r3,(r3)+
2956      which is a famous insn on the PDP-11 where the value of r3 used as the
2957      source was model-dependent.  Avoid this sort of thing.  */
2958
2959 #if 0
2960   if (!(GET_CODE (PATTERN (i3)) == SET
2961         && REG_P (SET_SRC (PATTERN (i3)))
2962         && MEM_P (SET_DEST (PATTERN (i3)))
2963         && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2964             || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2965     /* It's not the exception.  */
2966 #endif
2967 #ifdef AUTO_INC_DEC
2968     {
2969       rtx link;
2970       for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2971         if (REG_NOTE_KIND (link) == REG_INC
2972             && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2973                 || (i1 != 0
2974                     && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2975           {
2976             undo_all ();
2977             return 0;
2978           }
2979     }
2980 #endif
2981
2982   /* See if the SETs in I1 or I2 need to be kept around in the merged
2983      instruction: whenever the value set there is still needed past I3.
2984      For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2985
2986      For the SET in I1, we have two cases:  If I1 and I2 independently
2987      feed into I3, the set in I1 needs to be kept around if I1DEST dies
2988      or is set in I3.  Otherwise (if I1 feeds I2 which feeds I3), the set
2989      in I1 needs to be kept around unless I1DEST dies or is set in either
2990      I2 or I3.  The same consideration applies to I0.  */
2991
2992   added_sets_2 = !dead_or_set_p (i3, i2dest);
2993
2994   if (i1)
2995     added_sets_1 = !(dead_or_set_p (i3, i1dest)
2996                      || (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
2997   else
2998     added_sets_1 = 0;
2999
3000   if (i0)
3001     added_sets_0 =  !(dead_or_set_p (i3, i0dest)
3002                       || (i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3003                       || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)));
3004   else
3005     added_sets_0 = 0;
3006
3007   /* We are about to copy insns for the case where they need to be kept
3008      around.  Check that they can be copied in the merged instruction.  */
3009
3010   if (targetm.cannot_copy_insn_p
3011       && ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
3012           || (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
3013           || (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
3014     {
3015       undo_all ();
3016       return 0;
3017     }
3018
3019   /* If the set in I2 needs to be kept around, we must make a copy of
3020      PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3021      PATTERN (I2), we are only substituting for the original I1DEST, not into
3022      an already-substituted copy.  This also prevents making self-referential
3023      rtx.  If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3024      I2DEST.  */
3025
3026   if (added_sets_2)
3027     {
3028       if (GET_CODE (PATTERN (i2)) == PARALLEL)
3029         i2pat = gen_rtx_SET (VOIDmode, i2dest, copy_rtx (i2src));
3030       else
3031         i2pat = copy_rtx (PATTERN (i2));
3032     }
3033
3034   if (added_sets_1)
3035     {
3036       if (GET_CODE (PATTERN (i1)) == PARALLEL)
3037         i1pat = gen_rtx_SET (VOIDmode, i1dest, copy_rtx (i1src));
3038       else
3039         i1pat = copy_rtx (PATTERN (i1));
3040     }
3041
3042   if (added_sets_0)
3043     {
3044       if (GET_CODE (PATTERN (i0)) == PARALLEL)
3045         i0pat = gen_rtx_SET (VOIDmode, i0dest, copy_rtx (i0src));
3046       else
3047         i0pat = copy_rtx (PATTERN (i0));
3048     }
3049
3050   combine_merges++;
3051
3052   /* Substitute in the latest insn for the regs set by the earlier ones.  */
3053
3054   maxreg = max_reg_num ();
3055
3056   subst_insn = i3;
3057
3058 #ifndef HAVE_cc0
3059   /* Many machines that don't use CC0 have insns that can both perform an
3060      arithmetic operation and set the condition code.  These operations will
3061      be represented as a PARALLEL with the first element of the vector
3062      being a COMPARE of an arithmetic operation with the constant zero.
3063      The second element of the vector will set some pseudo to the result
3064      of the same arithmetic operation.  If we simplify the COMPARE, we won't
3065      match such a pattern and so will generate an extra insn.   Here we test
3066      for this case, where both the comparison and the operation result are
3067      needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3068      I2SRC.  Later we will make the PARALLEL that contains I2.  */
3069
3070   if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
3071       && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
3072       && CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
3073       && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
3074     {
3075       rtx newpat_dest;
3076       rtx *cc_use_loc = NULL, cc_use_insn = NULL_RTX;
3077       rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
3078       enum machine_mode compare_mode, orig_compare_mode;
3079       enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
3080
3081       newpat = PATTERN (i3);
3082       newpat_dest = SET_DEST (newpat);
3083       compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
3084
3085       if (undobuf.other_insn == 0
3086           && (cc_use_loc = find_single_use (SET_DEST (newpat), i3,
3087                                             &cc_use_insn)))
3088         {
3089           compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
3090           compare_code = simplify_compare_const (compare_code,
3091                                                  op0, &op1);
3092 #ifdef CANONICALIZE_COMPARISON
3093           CANONICALIZE_COMPARISON (compare_code, op0, op1);
3094 #endif
3095         }
3096
3097       /* Do the rest only if op1 is const0_rtx, which may be the
3098          result of simplification.  */
3099       if (op1 == const0_rtx)
3100         {
3101           /* If a single use of the CC is found, prepare to modify it
3102              when SELECT_CC_MODE returns a new CC-class mode, or when
3103              the above simplify_compare_const() returned a new comparison
3104              operator.  undobuf.other_insn is assigned the CC use insn
3105              when modifying it.  */
3106           if (cc_use_loc)
3107             {
3108 #ifdef SELECT_CC_MODE
3109               enum machine_mode new_mode
3110                 = SELECT_CC_MODE (compare_code, op0, op1);
3111               if (new_mode != orig_compare_mode
3112                   && can_change_dest_mode (SET_DEST (newpat),
3113                                            added_sets_2, new_mode))
3114                 {
3115                   unsigned int regno = REGNO (newpat_dest);
3116                   compare_mode = new_mode;
3117                   if (regno < FIRST_PSEUDO_REGISTER)
3118                     newpat_dest = gen_rtx_REG (compare_mode, regno);
3119                   else
3120                     {
3121                       SUBST_MODE (regno_reg_rtx[regno], compare_mode);
3122                       newpat_dest = regno_reg_rtx[regno];
3123                     }
3124                 }
3125 #endif
3126               /* Cases for modifying the CC-using comparison.  */
3127               if (compare_code != orig_compare_code
3128                   /* ??? Do we need to verify the zero rtx?  */
3129                   && XEXP (*cc_use_loc, 1) == const0_rtx)
3130                 {
3131                   /* Replace cc_use_loc with entire new RTX.  */
3132                   SUBST (*cc_use_loc,
3133                          gen_rtx_fmt_ee (compare_code, compare_mode,
3134                                          newpat_dest, const0_rtx));
3135                   undobuf.other_insn = cc_use_insn;
3136                 }
3137               else if (compare_mode != orig_compare_mode)
3138                 {
3139                   /* Just replace the CC reg with a new mode.  */
3140                   SUBST (XEXP (*cc_use_loc, 0), newpat_dest);
3141                   undobuf.other_insn = cc_use_insn;
3142                 }
3143             }
3144
3145           /* Now we modify the current newpat:
3146              First, SET_DEST(newpat) is updated if the CC mode has been
3147              altered. For targets without SELECT_CC_MODE, this should be
3148              optimized away.  */
3149           if (compare_mode != orig_compare_mode)
3150             SUBST (SET_DEST (newpat), newpat_dest);
3151           /* This is always done to propagate i2src into newpat.  */
3152           SUBST (SET_SRC (newpat),
3153                  gen_rtx_COMPARE (compare_mode, op0, op1));
3154           /* Create new version of i2pat if needed; the below PARALLEL
3155              creation needs this to work correctly.  */
3156           if (! rtx_equal_p (i2src, op0))
3157             i2pat = gen_rtx_SET (VOIDmode, i2dest, op0);
3158           i2_is_used = 1;
3159         }
3160     }
3161 #endif
3162
3163   if (i2_is_used == 0)
3164     {
3165       /* It is possible that the source of I2 or I1 may be performing
3166          an unneeded operation, such as a ZERO_EXTEND of something
3167          that is known to have the high part zero.  Handle that case
3168          by letting subst look at the inner insns.
3169
3170          Another way to do this would be to have a function that tries
3171          to simplify a single insn instead of merging two or more
3172          insns.  We don't do this because of the potential of infinite
3173          loops and because of the potential extra memory required.
3174          However, doing it the way we are is a bit of a kludge and
3175          doesn't catch all cases.
3176
3177          But only do this if -fexpensive-optimizations since it slows
3178          things down and doesn't usually win.
3179
3180          This is not done in the COMPARE case above because the
3181          unmodified I2PAT is used in the PARALLEL and so a pattern
3182          with a modified I2SRC would not match.  */
3183
3184       if (flag_expensive_optimizations)
3185         {
3186           /* Pass pc_rtx so no substitutions are done, just
3187              simplifications.  */
3188           if (i1)
3189             {
3190               subst_low_luid = DF_INSN_LUID (i1);
3191               i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0, 0);
3192             }
3193
3194           subst_low_luid = DF_INSN_LUID (i2);
3195           i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0, 0);
3196         }
3197
3198       n_occurrences = 0;                /* `subst' counts here */
3199       subst_low_luid = DF_INSN_LUID (i2);
3200
3201       /* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3202          copy of I2SRC each time we substitute it, in order to avoid creating
3203          self-referential RTL when we will be substituting I1SRC for I1DEST
3204          later.  Likewise if I0 feeds into I2, either directly or indirectly
3205          through I1, and I0DEST is in I0SRC.  */
3206       newpat = subst (PATTERN (i3), i2dest, i2src, 0, 0,
3207                       (i1_feeds_i2_n && i1dest_in_i1src)
3208                       || ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3209                           && i0dest_in_i0src));
3210       substed_i2 = 1;
3211
3212       /* Record whether I2's body now appears within I3's body.  */
3213       i2_is_used = n_occurrences;
3214     }
3215
3216   /* If we already got a failure, don't try to do more.  Otherwise, try to
3217      substitute I1 if we have it.  */
3218
3219   if (i1 && GET_CODE (newpat) != CLOBBER)
3220     {
3221       /* Check that an autoincrement side-effect on I1 has not been lost.
3222          This happens if I1DEST is mentioned in I2 and dies there, and
3223          has disappeared from the new pattern.  */
3224       if ((FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3225            && i1_feeds_i2_n
3226            && dead_or_set_p (i2, i1dest)
3227            && !reg_overlap_mentioned_p (i1dest, newpat))
3228            /* Before we can do this substitution, we must redo the test done
3229               above (see detailed comments there) that ensures I1DEST isn't
3230               mentioned in any SETs in NEWPAT that are field assignments.  */
3231           || !combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX, NULL_RTX,
3232                                 0, 0, 0))
3233         {
3234           undo_all ();
3235           return 0;
3236         }
3237
3238       n_occurrences = 0;
3239       subst_low_luid = DF_INSN_LUID (i1);
3240
3241       /* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3242          copy of I1SRC each time we substitute it, in order to avoid creating
3243          self-referential RTL when we will be substituting I0SRC for I0DEST
3244          later.  */
3245       newpat = subst (newpat, i1dest, i1src, 0, 0,
3246                       i0_feeds_i1_n && i0dest_in_i0src);
3247       substed_i1 = 1;
3248
3249       /* Record whether I1's body now appears within I3's body.  */
3250       i1_is_used = n_occurrences;
3251     }
3252
3253   /* Likewise for I0 if we have it.  */
3254
3255   if (i0 && GET_CODE (newpat) != CLOBBER)
3256     {
3257       if ((FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3258            && ((i0_feeds_i2_n && dead_or_set_p (i2, i0dest))
3259                || (i0_feeds_i1_n && dead_or_set_p (i1, i0dest)))
3260            && !reg_overlap_mentioned_p (i0dest, newpat))
3261           || !combinable_i3pat (NULL_RTX, &newpat, i0dest, NULL_RTX, NULL_RTX,
3262                                 0, 0, 0))
3263         {
3264           undo_all ();
3265           return 0;
3266         }
3267
3268       /* If the following substitution will modify I1SRC, make a copy of it
3269          for the case where it is substituted for I1DEST in I2PAT later.  */
3270       if (i0_feeds_i1_n && added_sets_2 && i1_feeds_i2_n)
3271         i1src_copy = copy_rtx (i1src);
3272
3273       n_occurrences = 0;
3274       subst_low_luid = DF_INSN_LUID (i0);
3275       newpat = subst (newpat, i0dest, i0src, 0, 0, 0);
3276       substed_i0 = 1;
3277     }
3278
3279   /* Fail if an autoincrement side-effect has been duplicated.  Be careful
3280      to count all the ways that I2SRC and I1SRC can be used.  */
3281   if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3282        && i2_is_used + added_sets_2 > 1)
3283       || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3284           && (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n)
3285               > 1))
3286       || (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3287           && (n_occurrences + added_sets_0
3288               + (added_sets_1 && i0_feeds_i1_n)
3289               + (added_sets_2 && i0_feeds_i2_n)
3290               > 1))
3291       /* Fail if we tried to make a new register.  */
3292       || max_reg_num () != maxreg
3293       /* Fail if we couldn't do something and have a CLOBBER.  */
3294       || GET_CODE (newpat) == CLOBBER
3295       /* Fail if this new pattern is a MULT and we didn't have one before
3296          at the outer level.  */
3297       || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3298           && ! have_mult))
3299     {
3300       undo_all ();
3301       return 0;
3302     }
3303
3304   /* If the actions of the earlier insns must be kept
3305      in addition to substituting them into the latest one,
3306      we must make a new PARALLEL for the latest insn
3307      to hold additional the SETs.  */
3308
3309   if (added_sets_0 || added_sets_1 || added_sets_2)
3310     {
3311       int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3312       combine_extras++;
3313
3314       if (GET_CODE (newpat) == PARALLEL)
3315         {
3316           rtvec old = XVEC (newpat, 0);
3317           total_sets = XVECLEN (newpat, 0) + extra_sets;
3318           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3319           memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
3320                   sizeof (old->elem[0]) * old->num_elem);
3321         }
3322       else
3323         {
3324           rtx old = newpat;
3325           total_sets = 1 + extra_sets;
3326           newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3327           XVECEXP (newpat, 0, 0) = old;
3328         }
3329
3330       if (added_sets_0)
3331         XVECEXP (newpat, 0, --total_sets) = i0pat;
3332
3333       if (added_sets_1)
3334         {
3335           rtx t = i1pat;
3336           if (i0_feeds_i1_n)
3337             t = subst (t, i0dest, i0src, 0, 0, 0);
3338
3339           XVECEXP (newpat, 0, --total_sets) = t;
3340         }
3341       if (added_sets_2)
3342         {
3343           rtx t = i2pat;
3344           if (i1_feeds_i2_n)
3345             t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, 0, 0,
3346                        i0_feeds_i1_n && i0dest_in_i0src);
3347           if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3348             t = subst (t, i0dest, i0src, 0, 0, 0);
3349
3350           XVECEXP (newpat, 0, --total_sets) = t;
3351         }
3352     }
3353
3354  validate_replacement:
3355
3356   /* Note which hard regs this insn has as inputs.  */
3357   mark_used_regs_combine (newpat);
3358
3359   /* If recog_for_combine fails, it strips existing clobbers.  If we'll
3360      consider splitting this pattern, we might need these clobbers.  */
3361   if (i1 && GET_CODE (newpat) == PARALLEL
3362       && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3363     {
3364       int len = XVECLEN (newpat, 0);
3365
3366       newpat_vec_with_clobbers = rtvec_alloc (len);
3367       for (i = 0; i < len; i++)
3368         RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3369     }
3370
3371   /* Is the result of combination a valid instruction?  */
3372   insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3373
3374   /* If the result isn't valid, see if it is a PARALLEL of two SETs where
3375      the second SET's destination is a register that is unused and isn't
3376      marked as an instruction that might trap in an EH region.  In that case,
3377      we just need the first SET.   This can occur when simplifying a divmod
3378      insn.  We *must* test for this case here because the code below that
3379      splits two independent SETs doesn't handle this case correctly when it
3380      updates the register status.
3381
3382      It's pointless doing this if we originally had two sets, one from
3383      i3, and one from i2.  Combining then splitting the parallel results
3384      in the original i2 again plus an invalid insn (which we delete).
3385      The net effect is only to move instructions around, which makes
3386      debug info less accurate.
3387
3388      Also check the case where the first SET's destination is unused.
3389      That would not cause incorrect code, but does cause an unneeded
3390      insn to remain.  */
3391
3392   if (insn_code_number < 0
3393       && !(added_sets_2 && i1 == 0)
3394       && GET_CODE (newpat) == PARALLEL
3395       && XVECLEN (newpat, 0) == 2
3396       && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3397       && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3398       && asm_noperands (newpat) < 0)
3399     {
3400       rtx set0 = XVECEXP (newpat, 0, 0);
3401       rtx set1 = XVECEXP (newpat, 0, 1);
3402
3403       if (((REG_P (SET_DEST (set1))
3404             && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3405            || (GET_CODE (SET_DEST (set1)) == SUBREG
3406                && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3407           && insn_nothrow_p (i3)
3408           && !side_effects_p (SET_SRC (set1)))
3409         {
3410           newpat = set0;
3411           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3412         }
3413
3414       else if (((REG_P (SET_DEST (set0))
3415                  && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3416                 || (GET_CODE (SET_DEST (set0)) == SUBREG
3417                     && find_reg_note (i3, REG_UNUSED,
3418                                       SUBREG_REG (SET_DEST (set0)))))
3419                && insn_nothrow_p (i3)
3420                && !side_effects_p (SET_SRC (set0)))
3421         {
3422           newpat = set1;
3423           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3424
3425           if (insn_code_number >= 0)
3426             changed_i3_dest = 1;
3427         }
3428     }
3429
3430   /* If we were combining three insns and the result is a simple SET
3431      with no ASM_OPERANDS that wasn't recognized, try to split it into two
3432      insns.  There are two ways to do this.  It can be split using a
3433      machine-specific method (like when you have an addition of a large
3434      constant) or by combine in the function find_split_point.  */
3435
3436   if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3437       && asm_noperands (newpat) < 0)
3438     {
3439       rtx parallel, m_split, *split;
3440
3441       /* See if the MD file can split NEWPAT.  If it can't, see if letting it
3442          use I2DEST as a scratch register will help.  In the latter case,
3443          convert I2DEST to the mode of the source of NEWPAT if we can.  */
3444
3445       m_split = combine_split_insns (newpat, i3);
3446
3447       /* We can only use I2DEST as a scratch reg if it doesn't overlap any
3448          inputs of NEWPAT.  */
3449
3450       /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3451          possible to try that as a scratch reg.  This would require adding
3452          more code to make it work though.  */
3453
3454       if (m_split == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3455         {
3456           enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3457
3458           /* First try to split using the original register as a
3459              scratch register.  */
3460           parallel = gen_rtx_PARALLEL (VOIDmode,
3461                                        gen_rtvec (2, newpat,
3462                                                   gen_rtx_CLOBBER (VOIDmode,
3463                                                                    i2dest)));
3464           m_split = combine_split_insns (parallel, i3);
3465
3466           /* If that didn't work, try changing the mode of I2DEST if
3467              we can.  */
3468           if (m_split == 0
3469               && new_mode != GET_MODE (i2dest)
3470               && new_mode != VOIDmode
3471               && can_change_dest_mode (i2dest, added_sets_2, new_mode))
3472             {
3473               enum machine_mode old_mode = GET_MODE (i2dest);
3474               rtx ni2dest;
3475
3476               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3477                 ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3478               else
3479                 {
3480                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], new_mode);
3481                   ni2dest = regno_reg_rtx[REGNO (i2dest)];
3482                 }
3483
3484               parallel = (gen_rtx_PARALLEL
3485                           (VOIDmode,
3486                            gen_rtvec (2, newpat,
3487                                       gen_rtx_CLOBBER (VOIDmode,
3488                                                        ni2dest))));
3489               m_split = combine_split_insns (parallel, i3);
3490
3491               if (m_split == 0
3492                   && REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3493                 {
3494                   struct undo *buf;
3495
3496                   adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3497                   buf = undobuf.undos;
3498                   undobuf.undos = buf->next;
3499                   buf->next = undobuf.frees;
3500                   undobuf.frees = buf;
3501                 }
3502             }
3503
3504           i2scratch = m_split != 0;
3505         }
3506
3507       /* If recog_for_combine has discarded clobbers, try to use them
3508          again for the split.  */
3509       if (m_split == 0 && newpat_vec_with_clobbers)
3510         {
3511           parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3512           m_split = combine_split_insns (parallel, i3);
3513         }
3514
3515       if (m_split && NEXT_INSN (m_split) == NULL_RTX)
3516         {
3517           m_split = PATTERN (m_split);
3518           insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
3519           if (insn_code_number >= 0)
3520             newpat = m_split;
3521         }
3522       else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
3523                && (next_nonnote_nondebug_insn (i2) == i3
3524                    || ! use_crosses_set_p (PATTERN (m_split), DF_INSN_LUID (i2))))
3525         {
3526           rtx i2set, i3set;
3527           rtx newi3pat = PATTERN (NEXT_INSN (m_split));
3528           newi2pat = PATTERN (m_split);
3529
3530           i3set = single_set (NEXT_INSN (m_split));
3531           i2set = single_set (m_split);
3532
3533           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3534
3535           /* If I2 or I3 has multiple SETs, we won't know how to track
3536              register status, so don't use these insns.  If I2's destination
3537              is used between I2 and I3, we also can't use these insns.  */
3538
3539           if (i2_code_number >= 0 && i2set && i3set
3540               && (next_nonnote_nondebug_insn (i2) == i3
3541                   || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3542             insn_code_number = recog_for_combine (&newi3pat, i3,
3543                                                   &new_i3_notes);
3544           if (insn_code_number >= 0)
3545             newpat = newi3pat;
3546
3547           /* It is possible that both insns now set the destination of I3.
3548              If so, we must show an extra use of it.  */
3549
3550           if (insn_code_number >= 0)
3551             {
3552               rtx new_i3_dest = SET_DEST (i3set);
3553               rtx new_i2_dest = SET_DEST (i2set);
3554
3555               while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3556                      || GET_CODE (new_i3_dest) == STRICT_LOW_PART
3557                      || GET_CODE (new_i3_dest) == SUBREG)
3558                 new_i3_dest = XEXP (new_i3_dest, 0);
3559
3560               while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3561                      || GET_CODE (new_i2_dest) == STRICT_LOW_PART
3562                      || GET_CODE (new_i2_dest) == SUBREG)
3563                 new_i2_dest = XEXP (new_i2_dest, 0);
3564
3565               if (REG_P (new_i3_dest)
3566                   && REG_P (new_i2_dest)
3567                   && REGNO (new_i3_dest) == REGNO (new_i2_dest))
3568                 INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3569             }
3570         }
3571
3572       /* If we can split it and use I2DEST, go ahead and see if that
3573          helps things be recognized.  Verify that none of the registers
3574          are set between I2 and I3.  */
3575       if (insn_code_number < 0
3576           && (split = find_split_point (&newpat, i3, false)) != 0
3577 #ifdef HAVE_cc0
3578           && REG_P (i2dest)
3579 #endif
3580           /* We need I2DEST in the proper mode.  If it is a hard register
3581              or the only use of a pseudo, we can change its mode.
3582              Make sure we don't change a hard register to have a mode that
3583              isn't valid for it, or change the number of registers.  */
3584           && (GET_MODE (*split) == GET_MODE (i2dest)
3585               || GET_MODE (*split) == VOIDmode
3586               || can_change_dest_mode (i2dest, added_sets_2,
3587                                        GET_MODE (*split)))
3588           && (next_nonnote_nondebug_insn (i2) == i3
3589               || ! use_crosses_set_p (*split, DF_INSN_LUID (i2)))
3590           /* We can't overwrite I2DEST if its value is still used by
3591              NEWPAT.  */
3592           && ! reg_referenced_p (i2dest, newpat))
3593         {
3594           rtx newdest = i2dest;
3595           enum rtx_code split_code = GET_CODE (*split);
3596           enum machine_mode split_mode = GET_MODE (*split);
3597           bool subst_done = false;
3598           newi2pat = NULL_RTX;
3599
3600           i2scratch = true;
3601
3602           /* *SPLIT may be part of I2SRC, so make sure we have the
3603              original expression around for later debug processing.
3604              We should not need I2SRC any more in other cases.  */
3605           if (MAY_HAVE_DEBUG_INSNS)
3606             i2src = copy_rtx (i2src);
3607           else
3608             i2src = NULL;
3609
3610           /* Get NEWDEST as a register in the proper mode.  We have already
3611              validated that we can do this.  */
3612           if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3613             {
3614               if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3615                 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3616               else
3617                 {
3618                   SUBST_MODE (regno_reg_rtx[REGNO (i2dest)], split_mode);
3619                   newdest = regno_reg_rtx[REGNO (i2dest)];
3620                 }
3621             }
3622
3623           /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3624              an ASHIFT.  This can occur if it was inside a PLUS and hence
3625              appeared to be a memory address.  This is a kludge.  */
3626           if (split_code == MULT
3627               && CONST_INT_P (XEXP (*split, 1))
3628               && INTVAL (XEXP (*split, 1)) > 0
3629               && (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3630             {
3631               SUBST (*split, gen_rtx_ASHIFT (split_mode,
3632                                              XEXP (*split, 0), GEN_INT (i)));
3633               /* Update split_code because we may not have a multiply
3634                  anymore.  */
3635               split_code = GET_CODE (*split);
3636             }
3637
3638 #ifdef INSN_SCHEDULING
3639           /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3640              be written as a ZERO_EXTEND.  */
3641           if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3642             {
3643 #ifdef LOAD_EXTEND_OP
3644               /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3645                  what it really is.  */
3646               if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
3647                   == SIGN_EXTEND)
3648                 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3649                                                     SUBREG_REG (*split)));
3650               else
3651 #endif
3652                 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3653                                                     SUBREG_REG (*split)));
3654             }
3655 #endif
3656
3657           /* Attempt to split binary operators using arithmetic identities.  */
3658           if (BINARY_P (SET_SRC (newpat))
3659               && split_mode == GET_MODE (SET_SRC (newpat))
3660               && ! side_effects_p (SET_SRC (newpat)))
3661             {
3662               rtx setsrc = SET_SRC (newpat);
3663               enum machine_mode mode = GET_MODE (setsrc);
3664               enum rtx_code code = GET_CODE (setsrc);
3665               rtx src_op0 = XEXP (setsrc, 0);
3666               rtx src_op1 = XEXP (setsrc, 1);
3667
3668               /* Split "X = Y op Y" as "Z = Y; X = Z op Z".  */
3669               if (rtx_equal_p (src_op0, src_op1))
3670                 {
3671                   newi2pat = gen_rtx_SET (VOIDmode, newdest, src_op0);
3672                   SUBST (XEXP (setsrc, 0), newdest);
3673                   SUBST (XEXP (setsrc, 1), newdest);
3674                   subst_done = true;
3675                 }
3676               /* Split "((P op Q) op R) op S" where op is PLUS or MULT.  */
3677               else if ((code == PLUS || code == MULT)
3678                        && GET_CODE (src_op0) == code
3679                        && GET_CODE (XEXP (src_op0, 0)) == code
3680                        && (INTEGRAL_MODE_P (mode)
3681                            || (FLOAT_MODE_P (mode)
3682                                && flag_unsafe_math_optimizations)))
3683                 {
3684                   rtx p = XEXP (XEXP (src_op0, 0), 0);
3685                   rtx q = XEXP (XEXP (src_op0, 0), 1);
3686                   rtx r = XEXP (src_op0, 1);
3687                   rtx s = src_op1;
3688
3689                   /* Split both "((X op Y) op X) op Y" and
3690                      "((X op Y) op Y) op X" as "T op T" where T is
3691                      "X op Y".  */
3692                   if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3693                        || (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3694                     {
3695                       newi2pat = gen_rtx_SET (VOIDmode, newdest,
3696                                               XEXP (src_op0, 0));
3697                       SUBST (XEXP (setsrc, 0), newdest);
3698                       SUBST (XEXP (setsrc, 1), newdest);
3699                       subst_done = true;
3700                     }
3701                   /* Split "((X op X) op Y) op Y)" as "T op T" where
3702                      T is "X op Y".  */
3703                   else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3704                     {
3705                       rtx tmp = simplify_gen_binary (code, mode, p, r);
3706                       newi2pat = gen_rtx_SET (VOIDmode, newdest, tmp);
3707                       SUBST (XEXP (setsrc, 0), newdest);
3708                       SUBST (XEXP (setsrc, 1), newdest);
3709                       subst_done = true;
3710                     }
3711                 }
3712             }
3713
3714           if (!subst_done)
3715             {
3716               newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
3717               SUBST (*split, newdest);
3718             }
3719
3720           i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3721
3722           /* recog_for_combine might have added CLOBBERs to newi2pat.
3723              Make sure NEWPAT does not depend on the clobbered regs.  */
3724           if (GET_CODE (newi2pat) == PARALLEL)
3725             for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3726               if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3727                 {
3728                   rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3729                   if (reg_overlap_mentioned_p (reg, newpat))
3730                     {
3731                       undo_all ();
3732                       return 0;
3733                     }
3734                 }
3735
3736           /* If the split point was a MULT and we didn't have one before,
3737              don't use one now.  */
3738           if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3739             insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3740         }
3741     }
3742
3743   /* Check for a case where we loaded from memory in a narrow mode and
3744      then sign extended it, but we need both registers.  In that case,
3745      we have a PARALLEL with both loads from the same memory location.
3746      We can split this into a load from memory followed by a register-register
3747      copy.  This saves at least one insn, more if register allocation can
3748      eliminate the copy.
3749
3750      We cannot do this if the destination of the first assignment is a
3751      condition code register or cc0.  We eliminate this case by making sure
3752      the SET_DEST and SET_SRC have the same mode.
3753
3754      We cannot do this if the destination of the second assignment is
3755      a register that we have already assumed is zero-extended.  Similarly
3756      for a SUBREG of such a register.  */
3757
3758   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3759            && GET_CODE (newpat) == PARALLEL
3760            && XVECLEN (newpat, 0) == 2
3761            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3762            && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3763            && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3764                == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3765            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3766            && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3767                            XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3768            && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3769                                    DF_INSN_LUID (i2))
3770            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3771            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3772            && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
3773                  (REG_P (temp)
3774                   && VEC_index (reg_stat_type, reg_stat,
3775                                 REGNO (temp))->nonzero_bits != 0
3776                   && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3777                   && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3778                   && (VEC_index (reg_stat_type, reg_stat,
3779                                  REGNO (temp))->nonzero_bits
3780                       != GET_MODE_MASK (word_mode))))
3781            && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3782                  && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3783                      (REG_P (temp)
3784                       && VEC_index (reg_stat_type, reg_stat,
3785                                     REGNO (temp))->nonzero_bits != 0
3786                       && GET_MODE_PRECISION (GET_MODE (temp)) < BITS_PER_WORD
3787                       && GET_MODE_PRECISION (GET_MODE (temp)) < HOST_BITS_PER_INT
3788                       && (VEC_index (reg_stat_type, reg_stat,
3789                                      REGNO (temp))->nonzero_bits
3790                           != GET_MODE_MASK (word_mode)))))
3791            && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3792                                          SET_SRC (XVECEXP (newpat, 0, 1)))
3793            && ! find_reg_note (i3, REG_UNUSED,
3794                                SET_DEST (XVECEXP (newpat, 0, 0))))
3795     {
3796       rtx ni2dest;
3797
3798       newi2pat = XVECEXP (newpat, 0, 0);
3799       ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3800       newpat = XVECEXP (newpat, 0, 1);
3801       SUBST (SET_SRC (newpat),
3802              gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3803       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3804
3805       if (i2_code_number >= 0)
3806         insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3807
3808       if (insn_code_number >= 0)
3809         swap_i2i3 = 1;
3810     }
3811
3812   /* Similarly, check for a case where we have a PARALLEL of two independent
3813      SETs but we started with three insns.  In this case, we can do the sets
3814      as two separate insns.  This case occurs when some SET allows two
3815      other insns to combine, but the destination of that SET is still live.  */
3816
3817   else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3818            && GET_CODE (newpat) == PARALLEL
3819            && XVECLEN (newpat, 0) == 2
3820            && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3821            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3822            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3823            && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3824            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3825            && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3826            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3827                                   XVECEXP (newpat, 0, 0))
3828            && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3829                                   XVECEXP (newpat, 0, 1))
3830            && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3831                  && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3832     {
3833       /* Normally, it doesn't matter which of the two is done first,
3834          but the one that references cc0 can't be the second, and
3835          one which uses any regs/memory set in between i2 and i3 can't
3836          be first.  */
3837       if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3838                               DF_INSN_LUID (i2))
3839 #ifdef HAVE_cc0
3840           && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0))
3841 #endif
3842          )
3843         {
3844           newi2pat = XVECEXP (newpat, 0, 1);
3845           newpat = XVECEXP (newpat, 0, 0);
3846         }
3847       else if (!use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 0)),
3848                                    DF_INSN_LUID (i2))
3849 #ifdef HAVE_cc0
3850                && !reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 1))
3851 #endif
3852               )
3853         {
3854           newi2pat = XVECEXP (newpat, 0, 0);
3855           newpat = XVECEXP (newpat, 0, 1);
3856         }
3857       else
3858         {
3859           undo_all ();
3860           return 0;
3861         }
3862
3863       i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3864
3865       if (i2_code_number >= 0)
3866         {
3867           /* recog_for_combine might have added CLOBBERs to newi2pat.
3868              Make sure NEWPAT does not depend on the clobbered regs.  */
3869           if (GET_CODE (newi2pat) == PARALLEL)
3870             {
3871               for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3872                 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3873                   {
3874                     rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3875                     if (reg_overlap_mentioned_p (reg, newpat))
3876                       {
3877                         undo_all ();
3878                         return 0;
3879                       }
3880                   }
3881             }
3882
3883           insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3884         }
3885     }
3886
3887   /* If it still isn't recognized, fail and change things back the way they
3888      were.  */
3889   if ((insn_code_number < 0
3890        /* Is the result a reasonable ASM_OPERANDS?  */
3891        && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
3892     {
3893       undo_all ();
3894       return 0;
3895     }
3896
3897   /* If we had to change another insn, make sure it is valid also.  */
3898   if (undobuf.other_insn)
3899     {
3900       CLEAR_HARD_REG_SET (newpat_used_regs);
3901
3902       other_pat = PATTERN (undobuf.other_insn);
3903       other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
3904                                              &new_other_notes);
3905
3906       if (other_code_number < 0 && ! check_asm_operands (other_pat))
3907         {
3908           undo_all ();
3909           return 0;
3910         }
3911     }
3912
3913 #ifdef HAVE_cc0
3914   /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
3915      they are adjacent to each other or not.  */
3916   {
3917     rtx p = prev_nonnote_insn (i3);
3918     if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
3919         && sets_cc0_p (newi2pat))
3920       {
3921         undo_all ();
3922         return 0;
3923       }
3924   }
3925 #endif
3926
3927   /* Only allow this combination if insn_rtx_costs reports that the
3928      replacement instructions are cheaper than the originals.  */
3929   if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, other_pat))
3930     {
3931       undo_all ();
3932       return 0;
3933     }
3934
3935   if (MAY_HAVE_DEBUG_INSNS)
3936     {
3937       struct undo *undo;
3938
3939       for (undo = undobuf.undos; undo; undo = undo->next)
3940         if (undo->kind == UNDO_MODE)
3941           {
3942             rtx reg = *undo->where.r;
3943             enum machine_mode new_mode = GET_MODE (reg);
3944             enum machine_mode old_mode = undo->old_contents.m;
3945
3946             /* Temporarily revert mode back.  */
3947             adjust_reg_mode (reg, old_mode);
3948
3949             if (reg == i2dest && i2scratch)
3950               {
3951                 /* If we used i2dest as a scratch register with a
3952                    different mode, substitute it for the original
3953                    i2src while its original mode is temporarily
3954                    restored, and then clear i2scratch so that we don't
3955                    do it again later.  */
3956                 propagate_for_debug (i2, last_combined_insn, reg, i2src);
3957                 i2scratch = false;
3958                 /* Put back the new mode.  */
3959                 adjust_reg_mode (reg, new_mode);
3960               }
3961             else
3962               {
3963                 rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
3964                 rtx first, last;
3965
3966                 if (reg == i2dest)
3967                   {
3968                     first = i2;
3969                     last = last_combined_insn;
3970                   }
3971                 else
3972                   {
3973                     first = i3;
3974                     last = undobuf.other_insn;
3975                     gcc_assert (last);
3976                     if (DF_INSN_LUID (last)
3977                         < DF_INSN_LUID (last_combined_insn))
3978                       last = last_combined_insn;
3979                   }
3980
3981                 /* We're dealing with a reg that changed mode but not
3982                    meaning, so we want to turn it into a subreg for
3983                    the new mode.  However, because of REG sharing and
3984                    because its mode had already changed, we have to do
3985                    it in two steps.  First, replace any debug uses of
3986                    reg, with its original mode temporarily restored,
3987                    with this copy we have created; then, replace the
3988                    copy with the SUBREG of the original shared reg,
3989                    once again changed to the new mode.  */
3990                 propagate_for_debug (first, last, reg, tempreg);
3991                 adjust_reg_mode (reg, new_mode);
3992                 propagate_for_debug (first, last, tempreg,
3993                                      lowpart_subreg (old_mode, reg, new_mode));
3994               }
3995           }
3996     }
3997
3998   /* If we will be able to accept this, we have made a
3999      change to the destination of I3.  This requires us to
4000      do a few adjustments.  */
4001
4002   if (changed_i3_dest)
4003     {
4004       PATTERN (i3) = newpat;
4005       adjust_for_new_dest (i3);
4006     }
4007
4008   /* We now know that we can do this combination.  Merge the insns and
4009      update the status of registers and LOG_LINKS.  */
4010
4011   if (undobuf.other_insn)
4012     {
4013       rtx note, next;
4014
4015       PATTERN (undobuf.other_insn) = other_pat;
4016
4017       /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
4018          are still valid.  Then add any non-duplicate notes added by
4019          recog_for_combine.  */
4020       for (note = REG_NOTES (undobuf.other_insn); note; note = next)
4021         {
4022           next = XEXP (note, 1);
4023
4024           if (REG_NOTE_KIND (note) == REG_UNUSED
4025               && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
4026             remove_note (undobuf.other_insn, note);
4027         }
4028
4029       distribute_notes (new_other_notes, undobuf.other_insn,
4030                         undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX,
4031                         NULL_RTX);
4032     }
4033
4034   if (swap_i2i3)
4035     {
4036       rtx insn;
4037       struct insn_link *link;
4038       rtx ni2dest;
4039
4040       /* I3 now uses what used to be its destination and which is now
4041          I2's destination.  This requires us to do a few adjustments.  */
4042       PATTERN (i3) = newpat;
4043       adjust_for_new_dest (i3);
4044
4045       /* We need a LOG_LINK from I3 to I2.  But we used to have one,
4046          so we still will.
4047
4048          However, some later insn might be using I2's dest and have
4049          a LOG_LINK pointing at I3.  We must remove this link.
4050          The simplest way to remove the link is to point it at I1,
4051          which we know will be a NOTE.  */
4052
4053       /* newi2pat is usually a SET here; however, recog_for_combine might
4054          have added some clobbers.  */
4055       if (GET_CODE (newi2pat) == PARALLEL)
4056         ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
4057       else
4058         ni2dest = SET_DEST (newi2pat);
4059
4060       for (insn = NEXT_INSN (i3);
4061            insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4062                     || insn != BB_HEAD (this_basic_block->next_bb));
4063            insn = NEXT_INSN (insn))
4064         {
4065           if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
4066             {
4067               FOR_EACH_LOG_LINK (link, insn)
4068                 if (link->insn == i3)
4069                   link->insn = i1;
4070
4071               break;
4072             }
4073         }
4074     }
4075
4076   {
4077     rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
4078     struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
4079     rtx midnotes = 0;
4080     int from_luid;
4081     /* Compute which registers we expect to eliminate.  newi2pat may be setting
4082        either i3dest or i2dest, so we must check it.  Also, i1dest may be the
4083        same as i3dest, in which case newi2pat may be setting i1dest.  */
4084     rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
4085                    || i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
4086                    || !i2dest_killed
4087                    ? 0 : i2dest);
4088     rtx elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
4089                    || (newi2pat && reg_set_p (i1dest, newi2pat))
4090                    || !i1dest_killed
4091                    ? 0 : i1dest);
4092     rtx elim_i0 = (i0 == 0 || i0dest_in_i0src
4093                    || (newi2pat && reg_set_p (i0dest, newi2pat))
4094                    || !i0dest_killed
4095                    ? 0 : i0dest);
4096
4097     /* Get the old REG_NOTES and LOG_LINKS from all our insns and
4098        clear them.  */
4099     i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
4100     i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
4101     if (i1)
4102       i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
4103     if (i0)
4104       i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4105
4106     /* Ensure that we do not have something that should not be shared but
4107        occurs multiple times in the new insns.  Check this by first
4108        resetting all the `used' flags and then copying anything is shared.  */
4109
4110     reset_used_flags (i3notes);
4111     reset_used_flags (i2notes);
4112     reset_used_flags (i1notes);
4113     reset_used_flags (i0notes);
4114     reset_used_flags (newpat);
4115     reset_used_flags (newi2pat);
4116     if (undobuf.other_insn)
4117       reset_used_flags (PATTERN (undobuf.other_insn));
4118
4119     i3notes = copy_rtx_if_shared (i3notes);
4120     i2notes = copy_rtx_if_shared (i2notes);
4121     i1notes = copy_rtx_if_shared (i1notes);
4122     i0notes = copy_rtx_if_shared (i0notes);
4123     newpat = copy_rtx_if_shared (newpat);
4124     newi2pat = copy_rtx_if_shared (newi2pat);
4125     if (undobuf.other_insn)
4126       reset_used_flags (PATTERN (undobuf.other_insn));
4127
4128     INSN_CODE (i3) = insn_code_number;
4129     PATTERN (i3) = newpat;
4130
4131     if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4132       {
4133         rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
4134
4135         reset_used_flags (call_usage);
4136         call_usage = copy_rtx (call_usage);
4137
4138         if (substed_i2)
4139           {
4140             /* I2SRC must still be meaningful at this point.  Some splitting
4141                operations can invalidate I2SRC, but those operations do not
4142                apply to calls.  */
4143             gcc_assert (i2src);
4144             replace_rtx (call_usage, i2dest, i2src);
4145           }
4146
4147         if (substed_i1)
4148           replace_rtx (call_usage, i1dest, i1src);
4149         if (substed_i0)
4150           replace_rtx (call_usage, i0dest, i0src);
4151
4152         CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
4153       }
4154
4155     if (undobuf.other_insn)
4156       INSN_CODE (undobuf.other_insn) = other_code_number;
4157
4158     /* We had one special case above where I2 had more than one set and
4159        we replaced a destination of one of those sets with the destination
4160        of I3.  In that case, we have to update LOG_LINKS of insns later
4161        in this basic block.  Note that this (expensive) case is rare.
4162
4163        Also, in this case, we must pretend that all REG_NOTEs for I2
4164        actually came from I3, so that REG_UNUSED notes from I2 will be
4165        properly handled.  */
4166
4167     if (i3_subst_into_i2)
4168       {
4169         for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4170           if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4171                || GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4172               && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4173               && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4174               && ! find_reg_note (i2, REG_UNUSED,
4175                                   SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4176             for (temp = NEXT_INSN (i2);
4177                  temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
4178                           || BB_HEAD (this_basic_block) != temp);
4179                  temp = NEXT_INSN (temp))
4180               if (temp != i3 && INSN_P (temp))
4181                 FOR_EACH_LOG_LINK (link, temp)
4182                   if (link->insn == i2)
4183                     link->insn = i3;
4184
4185         if (i3notes)
4186           {
4187             rtx link = i3notes;
4188             while (XEXP (link, 1))
4189               link = XEXP (link, 1);
4190             XEXP (link, 1) = i2notes;
4191           }
4192         else
4193           i3notes = i2notes;
4194         i2notes = 0;
4195       }
4196
4197     LOG_LINKS (i3) = NULL;
4198     REG_NOTES (i3) = 0;
4199     LOG_LINKS (i2) = NULL;
4200     REG_NOTES (i2) = 0;
4201
4202     if (newi2pat)
4203       {
4204         if (MAY_HAVE_DEBUG_INSNS && i2scratch)
4205           propagate_for_debug (i2, last_combined_insn, i2dest, i2src);
4206         INSN_CODE (i2) = i2_code_number;
4207         PATTERN (i2) = newi2pat;
4208       }
4209     else
4210       {
4211         if (MAY_HAVE_DEBUG_INSNS && i2src)
4212           propagate_for_debug (i2, last_combined_insn, i2dest, i2src);
4213         SET_INSN_DELETED (i2);
4214       }
4215
4216     if (i1)
4217       {
4218         LOG_LINKS (i1) = NULL;
4219         REG_NOTES (i1) = 0;
4220         if (MAY_HAVE_DEBUG_INSNS)
4221           propagate_for_debug (i1, last_combined_insn, i1dest, i1src);
4222         SET_INSN_DELETED (i1);
4223       }
4224
4225     if (i0)
4226       {
4227         LOG_LINKS (i0) = NULL;
4228         REG_NOTES (i0) = 0;
4229         if (MAY_HAVE_DEBUG_INSNS)
4230           propagate_for_debug (i0, last_combined_insn, i0dest, i0src);
4231         SET_INSN_DELETED (i0);
4232       }
4233
4234     /* Get death notes for everything that is now used in either I3 or
4235        I2 and used to die in a previous insn.  If we built two new
4236        patterns, move from I1 to I2 then I2 to I3 so that we get the
4237        proper movement on registers that I2 modifies.  */
4238
4239     if (i0)
4240       from_luid = DF_INSN_LUID (i0);
4241     else if (i1)
4242       from_luid = DF_INSN_LUID (i1);
4243     else
4244       from_luid = DF_INSN_LUID (i2);
4245     if (newi2pat)
4246       move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4247     move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4248
4249     /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3.  */
4250     if (i3notes)
4251       distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
4252                         elim_i2, elim_i1, elim_i0);
4253     if (i2notes)
4254       distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
4255                         elim_i2, elim_i1, elim_i0);
4256     if (i1notes)
4257       distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
4258                         elim_i2, elim_i1, elim_i0);
4259     if (i0notes)
4260       distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL_RTX,
4261                         elim_i2, elim_i1, elim_i0);
4262     if (midnotes)
4263       distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4264                         elim_i2, elim_i1, elim_i0);
4265
4266     /* Distribute any notes added to I2 or I3 by recog_for_combine.  We
4267        know these are REG_UNUSED and want them to go to the desired insn,
4268        so we always pass it as i3.  */
4269
4270     if (newi2pat && new_i2_notes)
4271       distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX,
4272                         NULL_RTX);
4273
4274     if (new_i3_notes)
4275       distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX,
4276                         NULL_RTX);
4277
4278     /* If I3DEST was used in I3SRC, it really died in I3.  We may need to
4279        put a REG_DEAD note for it somewhere.  If NEWI2PAT exists and sets
4280        I3DEST, the death must be somewhere before I2, not I3.  If we passed I3
4281        in that case, it might delete I2.  Similarly for I2 and I1.
4282        Show an additional death due to the REG_DEAD note we make here.  If
4283        we discard it in distribute_notes, we will decrement it again.  */
4284
4285     if (i3dest_killed)
4286       {
4287         if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4288           distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4289                                             NULL_RTX),
4290                             NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1, elim_i0);
4291         else
4292           distribute_notes (alloc_reg_note (REG_DEAD, i3dest_killed,
4293                                             NULL_RTX),
4294                             NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4295                             elim_i2, elim_i1, elim_i0);
4296       }
4297
4298     if (i2dest_in_i2src)
4299       {
4300         rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4301         if (newi2pat && reg_set_p (i2dest, newi2pat))
4302           distribute_notes (new_note,  NULL_RTX, i2, NULL_RTX, NULL_RTX,
4303                             NULL_RTX, NULL_RTX);
4304         else
4305           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4306                             NULL_RTX, NULL_RTX, NULL_RTX);
4307       }
4308
4309     if (i1dest_in_i1src)
4310       {
4311         rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4312         if (newi2pat && reg_set_p (i1dest, newi2pat))
4313           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4314                             NULL_RTX, NULL_RTX);
4315         else
4316           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4317                             NULL_RTX, NULL_RTX, NULL_RTX);
4318       }
4319
4320     if (i0dest_in_i0src)
4321       {
4322         rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4323         if (newi2pat && reg_set_p (i0dest, newi2pat))
4324           distribute_notes (new_note, NULL_RTX, i2, NULL_RTX, NULL_RTX,
4325                             NULL_RTX, NULL_RTX);
4326         else
4327           distribute_notes (new_note, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
4328                             NULL_RTX, NULL_RTX, NULL_RTX);
4329       }
4330
4331     distribute_links (i3links);
4332     distribute_links (i2links);
4333     distribute_links (i1links);
4334     distribute_links (i0links);
4335
4336     if (REG_P (i2dest))
4337       {
4338         struct insn_link *link;
4339         rtx i2_insn = 0, i2_val = 0, set;
4340
4341         /* The insn that used to set this register doesn't exist, and
4342            this life of the register may not exist either.  See if one of
4343            I3's links points to an insn that sets I2DEST.  If it does,
4344            that is now the last known value for I2DEST. If we don't update
4345            this and I2 set the register to a value that depended on its old
4346            contents, we will get confused.  If this insn is used, thing
4347            will be set correctly in combine_instructions.  */
4348         FOR_EACH_LOG_LINK (link, i3)
4349           if ((set = single_set (link->insn)) != 0
4350               && rtx_equal_p (i2dest, SET_DEST (set)))
4351             i2_insn = link->insn, i2_val = SET_SRC (set);
4352
4353         record_value_for_reg (i2dest, i2_insn, i2_val);
4354
4355         /* If the reg formerly set in I2 died only once and that was in I3,
4356            zero its use count so it won't make `reload' do any work.  */
4357         if (! added_sets_2
4358             && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4359             && ! i2dest_in_i2src)
4360           INC_REG_N_SETS (REGNO (i2dest), -1);
4361       }
4362
4363     if (i1 && REG_P (i1dest))
4364       {
4365         struct insn_link *link;
4366         rtx i1_insn = 0, i1_val = 0, set;
4367
4368         FOR_EACH_LOG_LINK (link, i3)
4369           if ((set = single_set (link->insn)) != 0
4370               && rtx_equal_p (i1dest, SET_DEST (set)))
4371             i1_insn = link->insn, i1_val = SET_SRC (set);
4372
4373         record_value_for_reg (i1dest, i1_insn, i1_val);
4374
4375         if (! added_sets_1 && ! i1dest_in_i1src)
4376           INC_REG_N_SETS (REGNO (i1dest), -1);
4377       }
4378
4379     if (i0 && REG_P (i0dest))
4380       {
4381         struct insn_link *link;
4382         rtx i0_insn = 0, i0_val = 0, set;
4383
4384         FOR_EACH_LOG_LINK (link, i3)
4385           if ((set = single_set (link->insn)) != 0
4386               && rtx_equal_p (i0dest, SET_DEST (set)))
4387             i0_insn = link->insn, i0_val = SET_SRC (set);
4388
4389         record_value_for_reg (i0dest, i0_insn, i0_val);
4390
4391         if (! added_sets_0 && ! i0dest_in_i0src)
4392           INC_REG_N_SETS (REGNO (i0dest), -1);
4393       }
4394
4395     /* Update reg_stat[].nonzero_bits et al for any changes that may have
4396        been made to this insn.  The order of
4397        set_nonzero_bits_and_sign_copies() is important.  Because newi2pat
4398        can affect nonzero_bits of newpat */
4399     if (newi2pat)
4400       note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4401     note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4402   }
4403
4404   if (undobuf.other_insn != NULL_RTX)
4405     {
4406       if (dump_file)
4407         {
4408           fprintf (dump_file, "modifying other_insn ");
4409           dump_insn_slim (dump_file, undobuf.other_insn);
4410         }
4411       df_insn_rescan (undobuf.other_insn);
4412     }
4413
4414   if (i0 && !(NOTE_P(i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4415     {
4416       if (dump_file)
4417         {
4418           fprintf (dump_file, "modifying insn i1 ");
4419           dump_insn_slim (dump_file, i0);
4420         }
4421       df_insn_rescan (i0);
4422     }
4423
4424   if (i1 && !(NOTE_P(i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4425     {
4426       if (dump_file)
4427         {
4428           fprintf (dump_file, "modifying insn i1 ");
4429           dump_insn_slim (dump_file, i1);
4430         }
4431       df_insn_rescan (i1);
4432     }
4433
4434   if (i2 && !(NOTE_P(i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4435     {
4436       if (dump_file)
4437         {
4438           fprintf (dump_file, "modifying insn i2 ");
4439           dump_insn_slim (dump_file, i2);
4440         }
4441       df_insn_rescan (i2);
4442     }
4443
4444   if (i3 && !(NOTE_P(i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4445     {
4446       if (dump_file)
4447         {
4448           fprintf (dump_file, "modifying insn i3 ");
4449           dump_insn_slim (dump_file, i3);
4450         }
4451       df_insn_rescan (i3);
4452     }
4453
4454   /* Set new_direct_jump_p if a new return or simple jump instruction
4455      has been created.  Adjust the CFG accordingly.  */
4456
4457   if (returnjump_p (i3) || any_uncondjump_p (i3))
4458     {
4459       *new_direct_jump_p = 1;
4460       mark_jump_label (PATTERN (i3), i3, 0);
4461       update_cfg_for_uncondjump (i3);
4462     }
4463
4464   if (undobuf.other_insn != NULL_RTX
4465       && (returnjump_p (undobuf.other_insn)
4466           || any_uncondjump_p (undobuf.other_insn)))
4467     {
4468       *new_direct_jump_p = 1;
4469       update_cfg_for_uncondjump (undobuf.other_insn);
4470     }
4471
4472   /* A noop might also need cleaning up of CFG, if it comes from the
4473      simplification of a jump.  */
4474   if (JUMP_P (i3)
4475       && GET_CODE (newpat) == SET
4476       && SET_SRC (newpat) == pc_rtx
4477       && SET_DEST (newpat) == pc_rtx)
4478     {
4479       *new_direct_jump_p = 1;
4480       update_cfg_for_uncondjump (i3);
4481     }
4482
4483   if (undobuf.other_insn != NULL_RTX
4484       && JUMP_P (undobuf.other_insn)
4485       && GET_CODE (PATTERN (undobuf.other_insn)) == SET
4486       && SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4487       && SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4488     {
4489       *new_direct_jump_p = 1;
4490       update_cfg_for_uncondjump (undobuf.other_insn);
4491     }
4492
4493   combine_successes++;
4494   undo_commit ();
4495
4496   if (added_links_insn
4497       && (newi2pat == 0 || DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i2))
4498       && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (i3))
4499     return added_links_insn;
4500   else
4501     return newi2pat ? i2 : i3;
4502 }
4503 \f
4504 /* Undo all the modifications recorded in undobuf.  */
4505
4506 static void
4507 undo_all (void)
4508 {
4509   struct undo *undo, *next;
4510
4511   for (undo = undobuf.undos; undo; undo = next)
4512     {
4513       next = undo->next;
4514       switch (undo->kind)
4515         {
4516         case UNDO_RTX:
4517           *undo->where.r = undo->old_contents.r;
4518           break;
4519         case UNDO_INT:
4520           *undo->where.i = undo->old_contents.i;
4521           break;
4522         case UNDO_MODE:
4523           adjust_reg_mode (*undo->where.r, undo->old_contents.m);
4524           break;
4525         case UNDO_LINKS:
4526           *undo->where.l = undo->old_contents.l;
4527           break;
4528         default:
4529           gcc_unreachable ();
4530         }
4531
4532       undo->next = undobuf.frees;
4533       undobuf.frees = undo;
4534     }
4535
4536   undobuf.undos = 0;
4537 }
4538
4539 /* We've committed to accepting the changes we made.  Move all
4540    of the undos to the free list.  */
4541
4542 static void
4543 undo_commit (void)
4544 {
4545   struct undo *undo, *next;
4546
4547   for (undo = undobuf.undos; undo; undo = next)
4548     {
4549       next = undo->next;
4550       undo->next = undobuf.frees;
4551       undobuf.frees = undo;
4552     }
4553   undobuf.undos = 0;
4554 }
4555 \f
4556 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
4557    where we have an arithmetic expression and return that point.  LOC will
4558    be inside INSN.
4559
4560    try_combine will call this function to see if an insn can be split into
4561    two insns.  */
4562
4563 static rtx *
4564 find_split_point (rtx *loc, rtx insn, bool set_src)
4565 {
4566   rtx x = *loc;
4567   enum rtx_code code = GET_CODE (x);
4568   rtx *split;
4569   unsigned HOST_WIDE_INT len = 0;
4570   HOST_WIDE_INT pos = 0;
4571   int unsignedp = 0;
4572   rtx inner = NULL_RTX;
4573
4574   /* First special-case some codes.  */
4575   switch (code)
4576     {
4577     case SUBREG:
4578 #ifdef INSN_SCHEDULING
4579       /* If we are making a paradoxical SUBREG invalid, it becomes a split
4580          point.  */
4581       if (MEM_P (SUBREG_REG (x)))
4582         return loc;
4583 #endif
4584       return find_split_point (&SUBREG_REG (x), insn, false);
4585
4586     case MEM:
4587 #ifdef HAVE_lo_sum
4588       /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4589          using LO_SUM and HIGH.  */
4590       if (GET_CODE (XEXP (x, 0)) == CONST
4591           || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
4592         {
4593           enum machine_mode address_mode
4594             = targetm.addr_space.address_mode (MEM_ADDR_SPACE (x));
4595
4596           SUBST (XEXP (x, 0),
4597                  gen_rtx_LO_SUM (address_mode,
4598                                  gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4599                                  XEXP (x, 0)));
4600           return &XEXP (XEXP (x, 0), 0);
4601         }
4602 #endif
4603
4604       /* If we have a PLUS whose second operand is a constant and the
4605          address is not valid, perhaps will can split it up using
4606          the machine-specific way to split large constants.  We use
4607          the first pseudo-reg (one of the virtual regs) as a placeholder;
4608          it will not remain in the result.  */
4609       if (GET_CODE (XEXP (x, 0)) == PLUS
4610           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
4611           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4612                                             MEM_ADDR_SPACE (x)))
4613         {
4614           rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4615           rtx seq = combine_split_insns (gen_rtx_SET (VOIDmode, reg,
4616                                                       XEXP (x, 0)),
4617                                          subst_insn);
4618
4619           /* This should have produced two insns, each of which sets our
4620              placeholder.  If the source of the second is a valid address,
4621              we can make put both sources together and make a split point
4622              in the middle.  */
4623
4624           if (seq
4625               && NEXT_INSN (seq) != NULL_RTX
4626               && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
4627               && NONJUMP_INSN_P (seq)
4628               && GET_CODE (PATTERN (seq)) == SET
4629               && SET_DEST (PATTERN (seq)) == reg
4630               && ! reg_mentioned_p (reg,
4631                                     SET_SRC (PATTERN (seq)))
4632               && NONJUMP_INSN_P (NEXT_INSN (seq))
4633               && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4634               && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4635               && memory_address_addr_space_p
4636                    (GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4637                     MEM_ADDR_SPACE (x)))
4638             {
4639               rtx src1 = SET_SRC (PATTERN (seq));
4640               rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4641
4642               /* Replace the placeholder in SRC2 with SRC1.  If we can
4643                  find where in SRC2 it was placed, that can become our
4644                  split point and we can replace this address with SRC2.
4645                  Just try two obvious places.  */
4646
4647               src2 = replace_rtx (src2, reg, src1);
4648               split = 0;
4649               if (XEXP (src2, 0) == src1)
4650                 split = &XEXP (src2, 0);
4651               else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4652                        && XEXP (XEXP (src2, 0), 0) == src1)
4653                 split = &XEXP (XEXP (src2, 0), 0);
4654
4655               if (split)
4656                 {
4657                   SUBST (XEXP (x, 0), src2);
4658                   return split;
4659                 }
4660             }
4661
4662           /* If that didn't work, perhaps the first operand is complex and
4663              needs to be computed separately, so make a split point there.
4664              This will occur on machines that just support REG + CONST
4665              and have a constant moved through some previous computation.  */
4666
4667           else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4668                    && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4669                          && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4670             return &XEXP (XEXP (x, 0), 0);
4671         }
4672
4673       /* If we have a PLUS whose first operand is complex, try computing it
4674          separately by making a split there.  */
4675       if (GET_CODE (XEXP (x, 0)) == PLUS
4676           && ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4677                                             MEM_ADDR_SPACE (x))
4678           && ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4679           && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4680                 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4681         return &XEXP (XEXP (x, 0), 0);
4682       break;
4683
4684     case SET:
4685 #ifdef HAVE_cc0
4686       /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
4687          ZERO_EXTRACT, the most likely reason why this doesn't match is that
4688          we need to put the operand into a register.  So split at that
4689          point.  */
4690
4691       if (SET_DEST (x) == cc0_rtx
4692           && GET_CODE (SET_SRC (x)) != COMPARE
4693           && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
4694           && !OBJECT_P (SET_SRC (x))
4695           && ! (GET_CODE (SET_SRC (x)) == SUBREG
4696                 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
4697         return &SET_SRC (x);
4698 #endif
4699
4700       /* See if we can split SET_SRC as it stands.  */
4701       split = find_split_point (&SET_SRC (x), insn, true);
4702       if (split && split != &SET_SRC (x))
4703         return split;
4704
4705       /* See if we can split SET_DEST as it stands.  */
4706       split = find_split_point (&SET_DEST (x), insn, false);
4707       if (split && split != &SET_DEST (x))
4708         return split;
4709
4710       /* See if this is a bitfield assignment with everything constant.  If
4711          so, this is an IOR of an AND, so split it into that.  */
4712       if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
4713           && HWI_COMPUTABLE_MODE_P (GET_MODE (XEXP (SET_DEST (x), 0)))
4714           && CONST_INT_P (XEXP (SET_DEST (x), 1))
4715           && CONST_INT_P (XEXP (SET_DEST (x), 2))
4716           && CONST_INT_P (SET_SRC (x))
4717           && ((INTVAL (XEXP (SET_DEST (x), 1))
4718                + INTVAL (XEXP (SET_DEST (x), 2)))
4719               <= GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0))))
4720           && ! side_effects_p (XEXP (SET_DEST (x), 0)))
4721         {
4722           HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
4723           unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
4724           unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
4725           rtx dest = XEXP (SET_DEST (x), 0);
4726           enum machine_mode mode = GET_MODE (dest);
4727           unsigned HOST_WIDE_INT mask
4728             = ((unsigned HOST_WIDE_INT) 1 << len) - 1;
4729           rtx or_mask;
4730
4731           if (BITS_BIG_ENDIAN)
4732             pos = GET_MODE_PRECISION (mode) - len - pos;
4733
4734           or_mask = gen_int_mode (src << pos, mode);
4735           if (src == mask)
4736             SUBST (SET_SRC (x),
4737                    simplify_gen_binary (IOR, mode, dest, or_mask));
4738           else
4739             {
4740               rtx negmask = gen_int_mode (~(mask << pos), mode);
4741               SUBST (SET_SRC (x),
4742                      simplify_gen_binary (IOR, mode,
4743                                           simplify_gen_binary (AND, mode,
4744                                                                dest, negmask),
4745                                           or_mask));
4746             }
4747
4748           SUBST (SET_DEST (x), dest);
4749
4750           split = find_split_point (&SET_SRC (x), insn, true);
4751           if (split && split != &SET_SRC (x))
4752             return split;
4753         }
4754
4755       /* Otherwise, see if this is an operation that we can split into two.
4756          If so, try to split that.  */
4757       code = GET_CODE (SET_SRC (x));
4758
4759       switch (code)
4760         {
4761         case AND:
4762           /* If we are AND'ing with a large constant that is only a single
4763              bit and the result is only being used in a context where we
4764              need to know if it is zero or nonzero, replace it with a bit
4765              extraction.  This will avoid the large constant, which might
4766              have taken more than one insn to make.  If the constant were
4767              not a valid argument to the AND but took only one insn to make,
4768              this is no worse, but if it took more than one insn, it will
4769              be better.  */
4770
4771           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4772               && REG_P (XEXP (SET_SRC (x), 0))
4773               && (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
4774               && REG_P (SET_DEST (x))
4775               && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
4776               && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
4777               && XEXP (*split, 0) == SET_DEST (x)
4778               && XEXP (*split, 1) == const0_rtx)
4779             {
4780               rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
4781                                                 XEXP (SET_SRC (x), 0),
4782                                                 pos, NULL_RTX, 1, 1, 0, 0);
4783               if (extraction != 0)
4784                 {
4785                   SUBST (SET_SRC (x), extraction);
4786                   return find_split_point (loc, insn, false);
4787                 }
4788             }
4789           break;
4790
4791         case NE:
4792           /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
4793              is known to be on, this can be converted into a NEG of a shift.  */
4794           if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
4795               && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
4796               && 1 <= (pos = exact_log2
4797                        (nonzero_bits (XEXP (SET_SRC (x), 0),
4798                                       GET_MODE (XEXP (SET_SRC (x), 0))))))
4799             {
4800               enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
4801
4802               SUBST (SET_SRC (x),
4803                      gen_rtx_NEG (mode,
4804                                   gen_rtx_LSHIFTRT (mode,
4805                                                     XEXP (SET_SRC (x), 0),
4806                                                     GEN_INT (pos))));
4807
4808               split = find_split_point (&SET_SRC (x), insn, true);
4809               if (split && split != &SET_SRC (x))
4810                 return split;
4811             }
4812           break;
4813
4814         case SIGN_EXTEND:
4815           inner = XEXP (SET_SRC (x), 0);
4816
4817           /* We can't optimize if either mode is a partial integer
4818              mode as we don't know how many bits are significant
4819              in those modes.  */
4820           if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
4821               || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
4822             break;
4823
4824           pos = 0;
4825           len = GET_MODE_PRECISION (GET_MODE (inner));
4826           unsignedp = 0;
4827           break;
4828
4829         case SIGN_EXTRACT:
4830         case ZERO_EXTRACT:
4831           if (CONST_INT_P (XEXP (SET_SRC (x), 1))
4832               && CONST_INT_P (XEXP (SET_SRC (x), 2)))
4833             {
4834               inner = XEXP (SET_SRC (x), 0);
4835               len = INTVAL (XEXP (SET_SRC (x), 1));
4836               pos = INTVAL (XEXP (SET_SRC (x), 2));
4837
4838               if (BITS_BIG_ENDIAN)
4839                 pos = GET_MODE_PRECISION (GET_MODE (inner)) - len - pos;
4840               unsignedp = (code == ZERO_EXTRACT);
4841             }
4842           break;
4843
4844         default:
4845           break;
4846         }
4847
4848       if (len && pos >= 0
4849           && pos + len <= GET_MODE_PRECISION (GET_MODE (inner)))
4850         {
4851           enum machine_mode mode = GET_MODE (SET_SRC (x));
4852
4853           /* For unsigned, we have a choice of a shift followed by an
4854              AND or two shifts.  Use two shifts for field sizes where the
4855              constant might be too large.  We assume here that we can
4856              always at least get 8-bit constants in an AND insn, which is
4857              true for every current RISC.  */
4858
4859           if (unsignedp && len <= 8)
4860             {
4861               SUBST (SET_SRC (x),
4862                      gen_rtx_AND (mode,
4863                                   gen_rtx_LSHIFTRT
4864                                   (mode, gen_lowpart (mode, inner),
4865                                    GEN_INT (pos)),
4866                                   GEN_INT (((unsigned HOST_WIDE_INT) 1 << len)
4867                                            - 1)));
4868
4869               split = find_split_point (&SET_SRC (x), insn, true);
4870               if (split && split != &SET_SRC (x))
4871                 return split;
4872             }
4873           else
4874             {
4875               SUBST (SET_SRC (x),
4876                      gen_rtx_fmt_ee
4877                      (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
4878                       gen_rtx_ASHIFT (mode,
4879                                       gen_lowpart (mode, inner),
4880                                       GEN_INT (GET_MODE_PRECISION (mode)
4881                                                - len - pos)),
4882                       GEN_INT (GET_MODE_PRECISION (mode) - len)));
4883
4884               split = find_split_point (&SET_SRC (x), insn, true);
4885               if (split && split != &SET_SRC (x))
4886                 return split;
4887             }
4888         }
4889
4890       /* See if this is a simple operation with a constant as the second
4891          operand.  It might be that this constant is out of range and hence
4892          could be used as a split point.  */
4893       if (BINARY_P (SET_SRC (x))
4894           && CONSTANT_P (XEXP (SET_SRC (x), 1))
4895           && (OBJECT_P (XEXP (SET_SRC (x), 0))
4896               || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
4897                   && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
4898         return &XEXP (SET_SRC (x), 1);
4899
4900       /* Finally, see if this is a simple operation with its first operand
4901          not in a register.  The operation might require this operand in a
4902          register, so return it as a split point.  We can always do this
4903          because if the first operand were another operation, we would have
4904          already found it as a split point.  */
4905       if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
4906           && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
4907         return &XEXP (SET_SRC (x), 0);
4908
4909       return 0;
4910
4911     case AND:
4912     case IOR:
4913       /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
4914          it is better to write this as (not (ior A B)) so we can split it.
4915          Similarly for IOR.  */
4916       if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
4917         {
4918           SUBST (*loc,
4919                  gen_rtx_NOT (GET_MODE (x),
4920                               gen_rtx_fmt_ee (code == IOR ? AND : IOR,
4921                                               GET_MODE (x),
4922                                               XEXP (XEXP (x, 0), 0),
4923                                               XEXP (XEXP (x, 1), 0))));
4924           return find_split_point (loc, insn, set_src);
4925         }
4926
4927       /* Many RISC machines have a large set of logical insns.  If the
4928          second operand is a NOT, put it first so we will try to split the
4929          other operand first.  */
4930       if (GET_CODE (XEXP (x, 1)) == NOT)
4931         {
4932           rtx tem = XEXP (x, 0);
4933           SUBST (XEXP (x, 0), XEXP (x, 1));
4934           SUBST (XEXP (x, 1), tem);
4935         }
4936       break;
4937
4938     case PLUS:
4939     case MINUS:
4940       /* Canonicalization can produce (minus A (mult B C)), where C is a
4941          constant.  It may be better to try splitting (plus (mult B -C) A)
4942          instead if this isn't a multiply by a power of two.  */
4943       if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
4944           && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4945           && exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1))) < 0)
4946         {
4947           enum machine_mode mode = GET_MODE (x);
4948           unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
4949           HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
4950           SUBST (*loc, gen_rtx_PLUS (mode, gen_rtx_MULT (mode,
4951                                                          XEXP (XEXP (x, 1), 0),
4952                                                          GEN_INT (other_int)),
4953                                      XEXP (x, 0)));
4954           return find_split_point (loc, insn, set_src);
4955         }
4956
4957       /* Split at a multiply-accumulate instruction.  However if this is
4958          the SET_SRC, we likely do not have such an instruction and it's
4959          worthless to try this split.  */
4960       if (!set_src && GET_CODE (XEXP (x, 0)) == MULT)
4961         return loc;
4962
4963     default:
4964       break;
4965     }
4966
4967   /* Otherwise, select our actions depending on our rtx class.  */
4968   switch (GET_RTX_CLASS (code))
4969     {
4970     case RTX_BITFIELD_OPS:              /* This is ZERO_EXTRACT and SIGN_EXTRACT.  */
4971     case RTX_TERNARY:
4972       split = find_split_point (&XEXP (x, 2), insn, false);
4973       if (split)
4974         return split;
4975       /* ... fall through ...  */
4976     case RTX_BIN_ARITH:
4977     case RTX_COMM_ARITH:
4978     case RTX_COMPARE:
4979     case RTX_COMM_COMPARE:
4980       split = find_split_point (&XEXP (x, 1), insn, false);
4981       if (split)
4982         return split;
4983       /* ... fall through ...  */
4984     case RTX_UNARY:
4985       /* Some machines have (and (shift ...) ...) insns.  If X is not
4986          an AND, but XEXP (X, 0) is, use it as our split point.  */
4987       if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
4988         return &XEXP (x, 0);
4989
4990       split = find_split_point (&XEXP (x, 0), insn, false);
4991       if (split)
4992         return split;
4993       return loc;
4994
4995     default:
4996       /* Otherwise, we don't have a split point.  */
4997       return 0;
4998     }
4999 }
5000 \f
5001 /* Throughout X, replace FROM with TO, and return the result.
5002    The result is TO if X is FROM;
5003    otherwise the result is X, but its contents may have been modified.
5004    If they were modified, a record was made in undobuf so that
5005    undo_all will (among other things) return X to its original state.
5006
5007    If the number of changes necessary is too much to record to undo,
5008    the excess changes are not made, so the result is invalid.
5009    The changes already made can still be undone.
5010    undobuf.num_undo is incremented for such changes, so by testing that
5011    the caller can tell whether the result is valid.
5012
5013    `n_occurrences' is incremented each time FROM is replaced.
5014
5015    IN_DEST is nonzero if we are processing the SET_DEST of a SET.
5016
5017    IN_COND is nonzero if we are at the top level of a condition.
5018
5019    UNIQUE_COPY is nonzero if each substitution must be unique.  We do this
5020    by copying if `n_occurrences' is nonzero.  */
5021
5022 static rtx
5023 subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
5024 {
5025   enum rtx_code code = GET_CODE (x);
5026   enum machine_mode op0_mode = VOIDmode;
5027   const char *fmt;
5028   int len, i;
5029   rtx new_rtx;
5030
5031 /* Two expressions are equal if they are identical copies of a shared
5032    RTX or if they are both registers with the same register number
5033    and mode.  */
5034
5035 #define COMBINE_RTX_EQUAL_P(X,Y)                        \
5036   ((X) == (Y)                                           \
5037    || (REG_P (X) && REG_P (Y)   \
5038        && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5039
5040   if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
5041     {
5042       n_occurrences++;
5043       return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
5044     }
5045
5046   /* If X and FROM are the same register but different modes, they
5047      will not have been seen as equal above.  However, the log links code
5048      will make a LOG_LINKS entry for that case.  If we do nothing, we
5049      will try to rerecognize our original insn and, when it succeeds,
5050      we will delete the feeding insn, which is incorrect.
5051
5052      So force this insn not to match in this (rare) case.  */
5053   if (! in_dest && code == REG && REG_P (from)
5054       && reg_overlap_mentioned_p (x, from))
5055     return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
5056
5057   /* If this is an object, we are done unless it is a MEM or LO_SUM, both
5058      of which may contain things that can be combined.  */
5059   if (code != MEM && code != LO_SUM && OBJECT_P (x))
5060     return x;
5061
5062   /* It is possible to have a subexpression appear twice in the insn.
5063      Suppose that FROM is a register that appears within TO.
5064      Then, after that subexpression has been scanned once by `subst',
5065      the second time it is scanned, TO may be found.  If we were
5066      to scan TO here, we would find FROM within it and create a
5067      self-referent rtl structure which is completely wrong.  */
5068   if (COMBINE_RTX_EQUAL_P (x, to))
5069     return to;
5070
5071   /* Parallel asm_operands need special attention because all of the
5072      inputs are shared across the arms.  Furthermore, unsharing the
5073      rtl results in recognition failures.  Failure to handle this case
5074      specially can result in circular rtl.
5075
5076      Solve this by doing a normal pass across the first entry of the
5077      parallel, and only processing the SET_DESTs of the subsequent
5078      entries.  Ug.  */
5079
5080   if (code == PARALLEL
5081       && GET_CODE (XVECEXP (x, 0, 0)) == SET
5082       && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
5083     {
5084       new_rtx = subst (XVECEXP (x, 0, 0), from, to, 0, 0, unique_copy);
5085
5086       /* If this substitution failed, this whole thing fails.  */
5087       if (GET_CODE (new_rtx) == CLOBBER
5088           && XEXP (new_rtx, 0) == const0_rtx)
5089         return new_rtx;
5090
5091       SUBST (XVECEXP (x, 0, 0), new_rtx);
5092
5093       for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
5094         {
5095           rtx dest = SET_DEST (XVECEXP (x, 0, i));
5096
5097           if (!REG_P (dest)
5098               && GET_CODE (dest) != CC0
5099               && GET_CODE (dest) != PC)
5100             {
5101               new_rtx = subst (dest, from, to, 0, 0, unique_copy);
5102
5103               /* If this substitution failed, this whole thing fails.  */
5104               if (GET_CODE (new_rtx) == CLOBBER
5105                   && XEXP (new_rtx, 0) == const0_rtx)
5106                 return new_rtx;
5107
5108               SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
5109             }
5110         }
5111     }
5112   else
5113     {
5114       len = GET_RTX_LENGTH (code);
5115       fmt = GET_RTX_FORMAT (code);
5116
5117       /* We don't need to process a SET_DEST that is a register, CC0,
5118          or PC, so set up to skip this common case.  All other cases
5119          where we want to suppress replacing something inside a
5120          SET_SRC are handled via the IN_DEST operand.  */
5121       if (code == SET
5122           && (REG_P (SET_DEST (x))
5123               || GET_CODE (SET_DEST (x)) == CC0
5124               || GET_CODE (SET_DEST (x)) == PC))
5125         fmt = "ie";
5126
5127       /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5128          constant.  */
5129       if (fmt[0] == 'e')
5130         op0_mode = GET_MODE (XEXP (x, 0));
5131
5132       for (i = 0; i < len; i++)
5133         {
5134           if (fmt[i] == 'E')
5135             {
5136               int j;
5137               for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5138                 {
5139                   if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5140                     {
5141                       new_rtx = (unique_copy && n_occurrences
5142                              ? copy_rtx (to) : to);
5143                       n_occurrences++;
5144                     }
5145                   else
5146                     {
5147                       new_rtx = subst (XVECEXP (x, i, j), from, to, 0, 0,
5148                                        unique_copy);
5149
5150                       /* If this substitution failed, this whole thing
5151                          fails.  */
5152                       if (GET_CODE (new_rtx) == CLOBBER
5153                           && XEXP (new_rtx, 0) == const0_rtx)
5154                         return new_rtx;
5155                     }
5156
5157                   SUBST (XVECEXP (x, i, j), new_rtx);
5158                 }
5159             }
5160           else if (fmt[i] == 'e')
5161             {
5162               /* If this is a register being set, ignore it.  */
5163               new_rtx = XEXP (x, i);
5164               if (in_dest
5165                   && i == 0
5166                   && (((code == SUBREG || code == ZERO_EXTRACT)
5167                        && REG_P (new_rtx))
5168                       || code == STRICT_LOW_PART))
5169                 ;
5170
5171               else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5172                 {
5173                   /* In general, don't install a subreg involving two
5174                      modes not tieable.  It can worsen register
5175                      allocation, and can even make invalid reload
5176                      insns, since the reg inside may need to be copied
5177                      from in the outside mode, and that may be invalid
5178                      if it is an fp reg copied in integer mode.
5179
5180                      We allow two exceptions to this: It is valid if
5181                      it is inside another SUBREG and the mode of that
5182                      SUBREG and the mode of the inside of TO is
5183                      tieable and it is valid if X is a SET that copies
5184                      FROM to CC0.  */
5185
5186                   if (GET_CODE (to) == SUBREG
5187                       && ! MODES_TIEABLE_P (GET_MODE (to),
5188                                             GET_MODE (SUBREG_REG (to)))
5189                       && ! (code == SUBREG
5190                             && MODES_TIEABLE_P (GET_MODE (x),
5191                                                 GET_MODE (SUBREG_REG (to))))
5192 #ifdef HAVE_cc0
5193                       && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
5194 #endif
5195                       )
5196                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5197
5198 #ifdef CANNOT_CHANGE_MODE_CLASS
5199                   if (code == SUBREG
5200                       && REG_P (to)
5201                       && REGNO (to) < FIRST_PSEUDO_REGISTER
5202                       && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
5203                                                    GET_MODE (to),
5204                                                    GET_MODE (x)))
5205                     return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5206 #endif
5207
5208                   new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5209                   n_occurrences++;
5210                 }
5211               else
5212                 /* If we are in a SET_DEST, suppress most cases unless we
5213                    have gone inside a MEM, in which case we want to
5214                    simplify the address.  We assume here that things that
5215                    are actually part of the destination have their inner
5216                    parts in the first expression.  This is true for SUBREG,
5217                    STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5218                    things aside from REG and MEM that should appear in a
5219                    SET_DEST.  */
5220                 new_rtx = subst (XEXP (x, i), from, to,
5221                              (((in_dest
5222                                 && (code == SUBREG || code == STRICT_LOW_PART
5223                                     || code == ZERO_EXTRACT))
5224                                || code == SET)
5225                               && i == 0),
5226                                  code == IF_THEN_ELSE && i == 0,
5227                                  unique_copy);
5228
5229               /* If we found that we will have to reject this combination,
5230                  indicate that by returning the CLOBBER ourselves, rather than
5231                  an expression containing it.  This will speed things up as
5232                  well as prevent accidents where two CLOBBERs are considered
5233                  to be equal, thus producing an incorrect simplification.  */
5234
5235               if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5236                 return new_rtx;
5237
5238               if (GET_CODE (x) == SUBREG
5239                   && (CONST_INT_P (new_rtx)
5240                       || GET_CODE (new_rtx) == CONST_DOUBLE))
5241                 {
5242                   enum machine_mode mode = GET_MODE (x);
5243
5244                   x = simplify_subreg (GET_MODE (x), new_rtx,
5245                                        GET_MODE (SUBREG_REG (x)),
5246                                        SUBREG_BYTE (x));
5247                   if (! x)
5248                     x = gen_rtx_CLOBBER (mode, const0_rtx);
5249                 }
5250               else if (CONST_INT_P (new_rtx)
5251                        && GET_CODE (x) == ZERO_EXTEND)
5252                 {
5253                   x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
5254                                                 new_rtx, GET_MODE (XEXP (x, 0)));
5255                   gcc_assert (x);
5256                 }
5257               else
5258                 SUBST (XEXP (x, i), new_rtx);
5259             }
5260         }
5261     }
5262
5263   /* Check if we are loading something from the constant pool via float
5264      extension; in this case we would undo compress_float_constant
5265      optimization and degenerate constant load to an immediate value.  */
5266   if (GET_CODE (x) == FLOAT_EXTEND
5267       && MEM_P (XEXP (x, 0))
5268       && MEM_READONLY_P (XEXP (x, 0)))
5269     {
5270       rtx tmp = avoid_constant_pool_reference (x);
5271       if (x != tmp)
5272         return x;
5273     }
5274
5275   /* Try to simplify X.  If the simplification changed the code, it is likely
5276      that further simplification will help, so loop, but limit the number
5277      of repetitions that will be performed.  */
5278
5279   for (i = 0; i < 4; i++)
5280     {
5281       /* If X is sufficiently simple, don't bother trying to do anything
5282          with it.  */
5283       if (code != CONST_INT && code != REG && code != CLOBBER)
5284         x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5285
5286       if (GET_CODE (x) == code)
5287         break;
5288
5289       code = GET_CODE (x);
5290
5291       /* We no longer know the original mode of operand 0 since we
5292          have changed the form of X)  */
5293       op0_mode = VOIDmode;
5294     }
5295
5296   return x;
5297 }
5298 \f
5299 /* Simplify X, a piece of RTL.  We just operate on the expression at the
5300    outer level; call `subst' to simplify recursively.  Return the new
5301    expression.
5302
5303    OP0_MODE is the original mode of XEXP (x, 0).  IN_DEST is nonzero
5304    if we are inside a SET_DEST.  IN_COND is nonzero if we are at the top level
5305    of a condition.  */
5306
5307 static rtx
5308 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest,
5309                       int in_cond)
5310 {
5311   enum rtx_code code = GET_CODE (x);
5312   enum machine_mode mode = GET_MODE (x);
5313   rtx temp;
5314   int i;
5315
5316   /* If this is a commutative operation, put a constant last and a complex
5317      expression first.  We don't need to do this for comparisons here.  */
5318   if (COMMUTATIVE_ARITH_P (x)
5319       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5320     {
5321       temp = XEXP (x, 0);
5322       SUBST (XEXP (x, 0), XEXP (x, 1));
5323       SUBST (XEXP (x, 1), temp);
5324     }
5325
5326   /* If this is a simple operation applied to an IF_THEN_ELSE, try
5327      applying it to the arms of the IF_THEN_ELSE.  This often simplifies
5328      things.  Check for cases where both arms are testing the same
5329      condition.
5330
5331      Don't do anything if all operands are very simple.  */
5332
5333   if ((BINARY_P (x)
5334        && ((!OBJECT_P (XEXP (x, 0))
5335             && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5336                   && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5337            || (!OBJECT_P (XEXP (x, 1))
5338                && ! (GET_CODE (XEXP (x, 1)) == SUBREG
5339                      && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5340       || (UNARY_P (x)
5341           && (!OBJECT_P (XEXP (x, 0))
5342                && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5343                      && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5344     {
5345       rtx cond, true_rtx, false_rtx;
5346
5347       cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5348       if (cond != 0
5349           /* If everything is a comparison, what we have is highly unlikely
5350              to be simpler, so don't use it.  */
5351           && ! (COMPARISON_P (x)
5352                 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
5353         {
5354           rtx cop1 = const0_rtx;
5355           enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5356
5357           if (cond_code == NE && COMPARISON_P (cond))
5358             return x;
5359
5360           /* Simplify the alternative arms; this may collapse the true and
5361              false arms to store-flag values.  Be careful to use copy_rtx
5362              here since true_rtx or false_rtx might share RTL with x as a
5363              result of the if_then_else_cond call above.  */
5364           true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5365           false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0, 0);
5366
5367           /* If true_rtx and false_rtx are not general_operands, an if_then_else
5368              is unlikely to be simpler.  */
5369           if (general_operand (true_rtx, VOIDmode)
5370               && general_operand (false_rtx, VOIDmode))
5371             {
5372               enum rtx_code reversed;
5373
5374               /* Restarting if we generate a store-flag expression will cause
5375                  us to loop.  Just drop through in this case.  */
5376
5377               /* If the result values are STORE_FLAG_VALUE and zero, we can
5378                  just make the comparison operation.  */
5379               if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5380                 x = simplify_gen_relational (cond_code, mode, VOIDmode,
5381                                              cond, cop1);
5382               else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5383                        && ((reversed = reversed_comparison_code_parts
5384                                         (cond_code, cond, cop1, NULL))
5385                            != UNKNOWN))
5386                 x = simplify_gen_relational (reversed, mode, VOIDmode,
5387                                              cond, cop1);
5388
5389               /* Likewise, we can make the negate of a comparison operation
5390                  if the result values are - STORE_FLAG_VALUE and zero.  */
5391               else if (CONST_INT_P (true_rtx)
5392                        && INTVAL (true_rtx) == - STORE_FLAG_VALUE
5393                        && false_rtx == const0_rtx)
5394                 x = simplify_gen_unary (NEG, mode,
5395                                         simplify_gen_relational (cond_code,
5396                                                                  mode, VOIDmode,
5397                                                                  cond, cop1),
5398                                         mode);
5399               else if (CONST_INT_P (false_rtx)
5400                        && INTVAL (false_rtx) == - STORE_FLAG_VALUE
5401                        && true_rtx == const0_rtx
5402                        && ((reversed = reversed_comparison_code_parts
5403                                         (cond_code, cond, cop1, NULL))
5404                            != UNKNOWN))
5405                 x = simplify_gen_unary (NEG, mode,
5406                                         simplify_gen_relational (reversed,
5407                                                                  mode, VOIDmode,
5408                                                                  cond, cop1),
5409                                         mode);
5410               else
5411                 return gen_rtx_IF_THEN_ELSE (mode,
5412                                              simplify_gen_relational (cond_code,
5413                                                                       mode,
5414                                                                       VOIDmode,
5415                                                                       cond,
5416                                                                       cop1),
5417                                              true_rtx, false_rtx);
5418
5419               code = GET_CODE (x);
5420               op0_mode = VOIDmode;
5421             }
5422         }
5423     }
5424
5425   /* Try to fold this expression in case we have constants that weren't
5426      present before.  */
5427   temp = 0;
5428   switch (GET_RTX_CLASS (code))
5429     {
5430     case RTX_UNARY:
5431       if (op0_mode == VOIDmode)
5432         op0_mode = GET_MODE (XEXP (x, 0));
5433       temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
5434       break;
5435     case RTX_COMPARE:
5436     case RTX_COMM_COMPARE:
5437       {
5438         enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5439         if (cmp_mode == VOIDmode)
5440           {
5441             cmp_mode = GET_MODE (XEXP (x, 1));
5442             if (cmp_mode == VOIDmode)
5443               cmp_mode = op0_mode;
5444           }
5445         temp = simplify_relational_operation (code, mode, cmp_mode,
5446                                               XEXP (x, 0), XEXP (x, 1));
5447       }
5448       break;
5449     case RTX_COMM_ARITH:
5450     case RTX_BIN_ARITH:
5451       temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5452       break;
5453     case RTX_BITFIELD_OPS:
5454     case RTX_TERNARY:
5455       temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5456                                          XEXP (x, 1), XEXP (x, 2));
5457       break;
5458     default:
5459       break;
5460     }
5461
5462   if (temp)
5463     {
5464       x = temp;
5465       code = GET_CODE (temp);
5466       op0_mode = VOIDmode;
5467       mode = GET_MODE (temp);
5468     }
5469
5470   /* First see if we can apply the inverse distributive law.  */
5471   if (code == PLUS || code == MINUS
5472       || code == AND || code == IOR || code == XOR)
5473     {
5474       x = apply_distributive_law (x);
5475       code = GET_CODE (x);
5476       op0_mode = VOIDmode;
5477     }
5478
5479   /* If CODE is an associative operation not otherwise handled, see if we
5480      can associate some operands.  This can win if they are constants or
5481      if they are logically related (i.e. (a & b) & a).  */
5482   if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5483        || code == AND || code == IOR || code == XOR
5484        || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5485       && ((INTEGRAL_MODE_P (mode) && code != DIV)
5486           || (flag_associative_math && FLOAT_MODE_P (mode))))
5487     {
5488       if (GET_CODE (XEXP (x, 0)) == code)
5489         {
5490           rtx other = XEXP (XEXP (x, 0), 0);
5491           rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5492           rtx inner_op1 = XEXP (x, 1);
5493           rtx inner;
5494
5495           /* Make sure we pass the constant operand if any as the second
5496              one if this is a commutative operation.  */
5497           if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5498             {
5499               rtx tem = inner_op0;
5500               inner_op0 = inner_op1;
5501               inner_op1 = tem;
5502             }
5503           inner = simplify_binary_operation (code == MINUS ? PLUS
5504                                              : code == DIV ? MULT
5505                                              : code,
5506                                              mode, inner_op0, inner_op1);
5507
5508           /* For commutative operations, try the other pair if that one
5509              didn't simplify.  */
5510           if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5511             {
5512               other = XEXP (XEXP (x, 0), 1);
5513               inner = simplify_binary_operation (code, mode,
5514                                                  XEXP (XEXP (x, 0), 0),
5515                                                  XEXP (x, 1));
5516             }
5517
5518           if (inner)
5519             return simplify_gen_binary (code, mode, other, inner);
5520         }
5521     }
5522
5523   /* A little bit of algebraic simplification here.  */
5524   switch (code)
5525     {
5526     case MEM:
5527       /* Ensure that our address has any ASHIFTs converted to MULT in case
5528          address-recognizing predicates are called later.  */
5529       temp = make_compound_operation (XEXP (x, 0), MEM);
5530       SUBST (XEXP (x, 0), temp);
5531       break;
5532
5533     case SUBREG:
5534       if (op0_mode == VOIDmode)
5535         op0_mode = GET_MODE (SUBREG_REG (x));
5536
5537       /* See if this can be moved to simplify_subreg.  */
5538       if (CONSTANT_P (SUBREG_REG (x))
5539           && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
5540              /* Don't call gen_lowpart if the inner mode
5541                 is VOIDmode and we cannot simplify it, as SUBREG without
5542                 inner mode is invalid.  */
5543           && (GET_MODE (SUBREG_REG (x)) != VOIDmode
5544               || gen_lowpart_common (mode, SUBREG_REG (x))))
5545         return gen_lowpart (mode, SUBREG_REG (x));
5546
5547       if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5548         break;
5549       {
5550         rtx temp;
5551         temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
5552                                 SUBREG_BYTE (x));
5553         if (temp)
5554           return temp;
5555       }
5556
5557       /* Don't change the mode of the MEM if that would change the meaning
5558          of the address.  */
5559       if (MEM_P (SUBREG_REG (x))
5560           && (MEM_VOLATILE_P (SUBREG_REG (x))
5561               || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
5562         return gen_rtx_CLOBBER (mode, const0_rtx);
5563
5564       /* Note that we cannot do any narrowing for non-constants since
5565          we might have been counting on using the fact that some bits were
5566          zero.  We now do this in the SET.  */
5567
5568       break;
5569
5570     case NEG:
5571       temp = expand_compound_operation (XEXP (x, 0));
5572
5573       /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5574          replaced by (lshiftrt X C).  This will convert
5575          (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y).  */
5576
5577       if (GET_CODE (temp) == ASHIFTRT
5578           && CONST_INT_P (XEXP (temp, 1))
5579           && INTVAL (XEXP (temp, 1)) == GET_MODE_PRECISION (mode) - 1)
5580         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5581                                      INTVAL (XEXP (temp, 1)));
5582
5583       /* If X has only a single bit that might be nonzero, say, bit I, convert
5584          (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5585          MODE minus 1.  This will convert (neg (zero_extract X 1 Y)) to
5586          (sign_extract X 1 Y).  But only do this if TEMP isn't a register
5587          or a SUBREG of one since we'd be making the expression more
5588          complex if it was just a register.  */
5589
5590       if (!REG_P (temp)
5591           && ! (GET_CODE (temp) == SUBREG
5592                 && REG_P (SUBREG_REG (temp)))
5593           && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
5594         {
5595           rtx temp1 = simplify_shift_const
5596             (NULL_RTX, ASHIFTRT, mode,
5597              simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
5598                                    GET_MODE_PRECISION (mode) - 1 - i),
5599              GET_MODE_PRECISION (mode) - 1 - i);
5600
5601           /* If all we did was surround TEMP with the two shifts, we
5602              haven't improved anything, so don't use it.  Otherwise,
5603              we are better off with TEMP1.  */
5604           if (GET_CODE (temp1) != ASHIFTRT
5605               || GET_CODE (XEXP (temp1, 0)) != ASHIFT
5606               || XEXP (XEXP (temp1, 0), 0) != temp)
5607             return temp1;
5608         }
5609       break;
5610
5611     case TRUNCATE:
5612       /* We can't handle truncation to a partial integer mode here
5613          because we don't know the real bitsize of the partial
5614          integer mode.  */
5615       if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5616         break;
5617
5618       if (HWI_COMPUTABLE_MODE_P (mode))
5619         SUBST (XEXP (x, 0),
5620                force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5621                               GET_MODE_MASK (mode), 0));
5622
5623       /* We can truncate a constant value and return it.  */
5624       if (CONST_INT_P (XEXP (x, 0)))
5625         return gen_int_mode (INTVAL (XEXP (x, 0)), mode);
5626
5627       /* Similarly to what we do in simplify-rtx.c, a truncate of a register
5628          whose value is a comparison can be replaced with a subreg if
5629          STORE_FLAG_VALUE permits.  */
5630       if (HWI_COMPUTABLE_MODE_P (mode)
5631           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
5632           && (temp = get_last_value (XEXP (x, 0)))
5633           && COMPARISON_P (temp))
5634         return gen_lowpart (mode, XEXP (x, 0));
5635       break;
5636
5637     case CONST:
5638       /* (const (const X)) can become (const X).  Do it this way rather than
5639          returning the inner CONST since CONST can be shared with a
5640          REG_EQUAL note.  */
5641       if (GET_CODE (XEXP (x, 0)) == CONST)
5642         SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
5643       break;
5644
5645 #ifdef HAVE_lo_sum
5646     case LO_SUM:
5647       /* Convert (lo_sum (high FOO) FOO) to FOO.  This is necessary so we
5648          can add in an offset.  find_split_point will split this address up
5649          again if it doesn't match.  */
5650       if (GET_CODE (XEXP (x, 0)) == HIGH
5651           && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
5652         return XEXP (x, 1);
5653       break;
5654 #endif
5655
5656     case PLUS:
5657       /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
5658          when c is (const_int (pow2 + 1) / 2) is a sign extension of a
5659          bit-field and can be replaced by either a sign_extend or a
5660          sign_extract.  The `and' may be a zero_extend and the two
5661          <c>, -<c> constants may be reversed.  */
5662       if (GET_CODE (XEXP (x, 0)) == XOR
5663           && CONST_INT_P (XEXP (x, 1))
5664           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
5665           && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
5666           && ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
5667               || (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
5668           && HWI_COMPUTABLE_MODE_P (mode)
5669           && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
5670                && CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
5671                && (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
5672                    == ((unsigned HOST_WIDE_INT) 1 << (i + 1)) - 1))
5673               || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
5674                   && (GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
5675                       == (unsigned int) i + 1))))
5676         return simplify_shift_const
5677           (NULL_RTX, ASHIFTRT, mode,
5678            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5679                                  XEXP (XEXP (XEXP (x, 0), 0), 0),
5680                                  GET_MODE_PRECISION (mode) - (i + 1)),
5681            GET_MODE_PRECISION (mode) - (i + 1));
5682
5683       /* If only the low-order bit of X is possibly nonzero, (plus x -1)
5684          can become (ashiftrt (ashift (xor x 1) C) C) where C is
5685          the bitsize of the mode - 1.  This allows simplification of
5686          "a = (b & 8) == 0;"  */
5687       if (XEXP (x, 1) == constm1_rtx
5688           && !REG_P (XEXP (x, 0))
5689           && ! (GET_CODE (XEXP (x, 0)) == SUBREG
5690                 && REG_P (SUBREG_REG (XEXP (x, 0))))
5691           && nonzero_bits (XEXP (x, 0), mode) == 1)
5692         return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
5693            simplify_shift_const (NULL_RTX, ASHIFT, mode,
5694                                  gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
5695                                  GET_MODE_PRECISION (mode) - 1),
5696            GET_MODE_PRECISION (mode) - 1);
5697
5698       /* If we are adding two things that have no bits in common, convert
5699          the addition into an IOR.  This will often be further simplified,
5700          for example in cases like ((a & 1) + (a & 2)), which can
5701          become a & 3.  */
5702
5703       if (HWI_COMPUTABLE_MODE_P (mode)
5704           && (nonzero_bits (XEXP (x, 0), mode)
5705               & nonzero_bits (XEXP (x, 1), mode)) == 0)
5706         {
5707           /* Try to simplify the expression further.  */
5708           rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
5709           temp = combine_simplify_rtx (tor, VOIDmode, in_dest, 0);
5710
5711           /* If we could, great.  If not, do not go ahead with the IOR
5712              replacement, since PLUS appears in many special purpose
5713              address arithmetic instructions.  */
5714           if (GET_CODE (temp) != CLOBBER
5715               && (GET_CODE (temp) != IOR
5716                   || ((XEXP (temp, 0) != XEXP (x, 0)
5717                        || XEXP (temp, 1) != XEXP (x, 1))
5718                       && (XEXP (temp, 0) != XEXP (x, 1)
5719                           || XEXP (temp, 1) != XEXP (x, 0)))))
5720             return temp;
5721         }
5722       break;
5723
5724     case MINUS:
5725       /* (minus <foo> (and <foo> (const_int -pow2))) becomes
5726          (and <foo> (const_int pow2-1))  */
5727       if (GET_CODE (XEXP (x, 1)) == AND
5728           && CONST_INT_P (XEXP (XEXP (x, 1), 1))
5729           && exact_log2 (-UINTVAL (XEXP (XEXP (x, 1), 1))) >= 0
5730           && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
5731         return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
5732                                        -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
5733       break;
5734
5735     case MULT:
5736       /* If we have (mult (plus A B) C), apply the distributive law and then
5737          the inverse distributive law to see if things simplify.  This
5738          occurs mostly in addresses, often when unrolling loops.  */
5739
5740       if (GET_CODE (XEXP (x, 0)) == PLUS)
5741         {
5742           rtx result = distribute_and_simplify_rtx (x, 0);
5743           if (result)
5744             return result;
5745         }
5746
5747       /* Try simplify a*(b/c) as (a*b)/c.  */
5748       if (FLOAT_MODE_P (mode) && flag_associative_math
5749           && GET_CODE (XEXP (x, 0)) == DIV)
5750         {
5751           rtx tem = simplify_binary_operation (MULT, mode,
5752                                                XEXP (XEXP (x, 0), 0),
5753                                                XEXP (x, 1));
5754           if (tem)
5755             return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
5756         }
5757       break;
5758
5759     case UDIV:
5760       /* If this is a divide by a power of two, treat it as a shift if
5761          its first operand is a shift.  */
5762       if (CONST_INT_P (XEXP (x, 1))
5763           && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
5764           && (GET_CODE (XEXP (x, 0)) == ASHIFT
5765               || GET_CODE (XEXP (x, 0)) == LSHIFTRT
5766               || GET_CODE (XEXP (x, 0)) == ASHIFTRT
5767               || GET_CODE (XEXP (x, 0)) == ROTATE
5768               || GET_CODE (XEXP (x, 0)) == ROTATERT))
5769         return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
5770       break;
5771
5772     case EQ:  case NE:
5773     case GT:  case GTU:  case GE:  case GEU:
5774     case LT:  case LTU:  case LE:  case LEU:
5775     case UNEQ:  case LTGT:
5776     case UNGT:  case UNGE:
5777     case UNLT:  case UNLE:
5778     case UNORDERED: case ORDERED:
5779       /* If the first operand is a condition code, we can't do anything
5780          with it.  */
5781       if (GET_CODE (XEXP (x, 0)) == COMPARE
5782           || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
5783               && ! CC0_P (XEXP (x, 0))))
5784         {
5785           rtx op0 = XEXP (x, 0);
5786           rtx op1 = XEXP (x, 1);
5787           enum rtx_code new_code;
5788
5789           if (GET_CODE (op0) == COMPARE)
5790             op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
5791
5792           /* Simplify our comparison, if possible.  */
5793           new_code = simplify_comparison (code, &op0, &op1);
5794
5795           /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
5796              if only the low-order bit is possibly nonzero in X (such as when
5797              X is a ZERO_EXTRACT of one bit).  Similarly, we can convert EQ to
5798              (xor X 1) or (minus 1 X); we use the former.  Finally, if X is
5799              known to be either 0 or -1, NE becomes a NEG and EQ becomes
5800              (plus X 1).
5801
5802              Remove any ZERO_EXTRACT we made when thinking this was a
5803              comparison.  It may now be simpler to use, e.g., an AND.  If a
5804              ZERO_EXTRACT is indeed appropriate, it will be placed back by
5805              the call to make_compound_operation in the SET case.
5806
5807              Don't apply these optimizations if the caller would
5808              prefer a comparison rather than a value.
5809              E.g., for the condition in an IF_THEN_ELSE most targets need
5810              an explicit comparison.  */
5811
5812           if (in_cond)
5813             ;
5814
5815           else if (STORE_FLAG_VALUE == 1
5816               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5817               && op1 == const0_rtx
5818               && mode == GET_MODE (op0)
5819               && nonzero_bits (op0, mode) == 1)
5820             return gen_lowpart (mode,
5821                                 expand_compound_operation (op0));
5822
5823           else if (STORE_FLAG_VALUE == 1
5824                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5825                    && op1 == const0_rtx
5826                    && mode == GET_MODE (op0)
5827                    && (num_sign_bit_copies (op0, mode)
5828                        == GET_MODE_PRECISION (mode)))
5829             {
5830               op0 = expand_compound_operation (op0);
5831               return simplify_gen_unary (NEG, mode,
5832                                          gen_lowpart (mode, op0),
5833                                          mode);
5834             }
5835
5836           else if (STORE_FLAG_VALUE == 1
5837                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5838                    && op1 == const0_rtx
5839                    && mode == GET_MODE (op0)
5840                    && nonzero_bits (op0, mode) == 1)
5841             {
5842               op0 = expand_compound_operation (op0);
5843               return simplify_gen_binary (XOR, mode,
5844                                           gen_lowpart (mode, op0),
5845                                           const1_rtx);
5846             }
5847
5848           else if (STORE_FLAG_VALUE == 1
5849                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5850                    && op1 == const0_rtx
5851                    && mode == GET_MODE (op0)
5852                    && (num_sign_bit_copies (op0, mode)
5853                        == GET_MODE_PRECISION (mode)))
5854             {
5855               op0 = expand_compound_operation (op0);
5856               return plus_constant (gen_lowpart (mode, op0), 1);
5857             }
5858
5859           /* If STORE_FLAG_VALUE is -1, we have cases similar to
5860              those above.  */
5861           if (in_cond)
5862             ;
5863
5864           else if (STORE_FLAG_VALUE == -1
5865               && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5866               && op1 == const0_rtx
5867               && (num_sign_bit_copies (op0, mode)
5868                   == GET_MODE_PRECISION (mode)))
5869             return gen_lowpart (mode,
5870                                 expand_compound_operation (op0));
5871
5872           else if (STORE_FLAG_VALUE == -1
5873                    && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5874                    && op1 == const0_rtx
5875                    && mode == GET_MODE (op0)
5876                    && nonzero_bits (op0, mode) == 1)
5877             {
5878               op0 = expand_compound_operation (op0);
5879               return simplify_gen_unary (NEG, mode,
5880                                          gen_lowpart (mode, op0),
5881                                          mode);
5882             }
5883
5884           else if (STORE_FLAG_VALUE == -1
5885                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5886                    && op1 == const0_rtx
5887                    && mode == GET_MODE (op0)
5888                    && (num_sign_bit_copies (op0, mode)
5889                        == GET_MODE_PRECISION (mode)))
5890             {
5891               op0 = expand_compound_operation (op0);
5892               return simplify_gen_unary (NOT, mode,
5893                                          gen_lowpart (mode, op0),
5894                                          mode);
5895             }
5896
5897           /* If X is 0/1, (eq X 0) is X-1.  */
5898           else if (STORE_FLAG_VALUE == -1
5899                    && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
5900                    && op1 == const0_rtx
5901                    && mode == GET_MODE (op0)
5902                    && nonzero_bits (op0, mode) == 1)
5903             {
5904               op0 = expand_compound_operation (op0);
5905               return plus_constant (gen_lowpart (mode, op0), -1);
5906             }
5907
5908           /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
5909              one bit that might be nonzero, we can convert (ne x 0) to
5910              (ashift x c) where C puts the bit in the sign bit.  Remove any
5911              AND with STORE_FLAG_VALUE when we are done, since we are only
5912              going to test the sign bit.  */
5913           if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
5914               && HWI_COMPUTABLE_MODE_P (mode)
5915               && val_signbit_p (mode, STORE_FLAG_VALUE)
5916               && op1 == const0_rtx
5917               && mode == GET_MODE (op0)
5918               && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
5919             {
5920               x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
5921                                         expand_compound_operation (op0),
5922                                         GET_MODE_PRECISION (mode) - 1 - i);
5923               if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
5924                 return XEXP (x, 0);
5925               else
5926                 return x;
5927             }
5928
5929           /* If the code changed, return a whole new comparison.  */
5930           if (new_code != code)
5931             return gen_rtx_fmt_ee (new_code, mode, op0, op1);
5932
5933           /* Otherwise, keep this operation, but maybe change its operands.
5934              This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR).  */
5935           SUBST (XEXP (x, 0), op0);
5936           SUBST (XEXP (x, 1), op1);
5937         }
5938       break;
5939
5940     case IF_THEN_ELSE:
5941       return simplify_if_then_else (x);
5942
5943     case ZERO_EXTRACT:
5944     case SIGN_EXTRACT:
5945     case ZERO_EXTEND:
5946     case SIGN_EXTEND:
5947       /* If we are processing SET_DEST, we are done.  */
5948       if (in_dest)
5949         return x;
5950
5951       return expand_compound_operation (x);
5952
5953     case SET:
5954       return simplify_set (x);
5955
5956     case AND:
5957     case IOR:
5958       return simplify_logical (x);
5959
5960     case ASHIFT:
5961     case LSHIFTRT:
5962     case ASHIFTRT:
5963     case ROTATE:
5964     case ROTATERT:
5965       /* If this is a shift by a constant amount, simplify it.  */
5966       if (CONST_INT_P (XEXP (x, 1)))
5967         return simplify_shift_const (x, code, mode, XEXP (x, 0),
5968                                      INTVAL (XEXP (x, 1)));
5969
5970       else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
5971         SUBST (XEXP (x, 1),
5972                force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
5973                               ((unsigned HOST_WIDE_INT) 1
5974                                << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
5975                               - 1,
5976                               0));
5977       break;
5978
5979     default:
5980       break;
5981     }
5982
5983   return x;
5984 }
5985 \f
5986 /* Simplify X, an IF_THEN_ELSE expression.  Return the new expression.  */
5987
5988 static rtx
5989 simplify_if_then_else (rtx x)
5990 {
5991   enum machine_mode mode = GET_MODE (x);
5992   rtx cond = XEXP (x, 0);
5993   rtx true_rtx = XEXP (x, 1);
5994   rtx false_rtx = XEXP (x, 2);
5995   enum rtx_code true_code = GET_CODE (cond);
5996   int comparison_p = COMPARISON_P (cond);
5997   rtx temp;
5998   int i;
5999   enum rtx_code false_code;
6000   rtx reversed;
6001
6002   /* Simplify storing of the truth value.  */
6003   if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
6004     return simplify_gen_relational (true_code, mode, VOIDmode,
6005                                     XEXP (cond, 0), XEXP (cond, 1));
6006
6007   /* Also when the truth value has to be reversed.  */
6008   if (comparison_p
6009       && true_rtx == const0_rtx && false_rtx == const_true_rtx
6010       && (reversed = reversed_comparison (cond, mode)))
6011     return reversed;
6012
6013   /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6014      in it is being compared against certain values.  Get the true and false
6015      comparisons and see if that says anything about the value of each arm.  */
6016
6017   if (comparison_p
6018       && ((false_code = reversed_comparison_code (cond, NULL))
6019           != UNKNOWN)
6020       && REG_P (XEXP (cond, 0)))
6021     {
6022       HOST_WIDE_INT nzb;
6023       rtx from = XEXP (cond, 0);
6024       rtx true_val = XEXP (cond, 1);
6025       rtx false_val = true_val;
6026       int swapped = 0;
6027
6028       /* If FALSE_CODE is EQ, swap the codes and arms.  */
6029
6030       if (false_code == EQ)
6031         {
6032           swapped = 1, true_code = EQ, false_code = NE;
6033           temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
6034         }
6035
6036       /* If we are comparing against zero and the expression being tested has
6037          only a single bit that might be nonzero, that is its value when it is
6038          not equal to zero.  Similarly if it is known to be -1 or 0.  */
6039
6040       if (true_code == EQ && true_val == const0_rtx
6041           && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
6042         {
6043           false_code = EQ;
6044           false_val = gen_int_mode (nzb, GET_MODE (from));
6045         }
6046       else if (true_code == EQ && true_val == const0_rtx
6047                && (num_sign_bit_copies (from, GET_MODE (from))
6048                    == GET_MODE_PRECISION (GET_MODE (from))))
6049         {
6050           false_code = EQ;
6051           false_val = constm1_rtx;
6052         }
6053
6054       /* Now simplify an arm if we know the value of the register in the
6055          branch and it is used in the arm.  Be careful due to the potential
6056          of locally-shared RTL.  */
6057
6058       if (reg_mentioned_p (from, true_rtx))
6059         true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
6060                                       from, true_val),
6061                           pc_rtx, pc_rtx, 0, 0, 0);
6062       if (reg_mentioned_p (from, false_rtx))
6063         false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
6064                                    from, false_val),
6065                            pc_rtx, pc_rtx, 0, 0, 0);
6066
6067       SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
6068       SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
6069
6070       true_rtx = XEXP (x, 1);
6071       false_rtx = XEXP (x, 2);
6072       true_code = GET_CODE (cond);
6073     }
6074
6075   /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6076      reversed, do so to avoid needing two sets of patterns for
6077      subtract-and-branch insns.  Similarly if we have a constant in the true
6078      arm, the false arm is the same as the first operand of the comparison, or
6079      the false arm is more complicated than the true arm.  */
6080
6081   if (comparison_p
6082       && reversed_comparison_code (cond, NULL) != UNKNOWN
6083       && (true_rtx == pc_rtx
6084           || (CONSTANT_P (true_rtx)
6085               && !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
6086           || true_rtx == const0_rtx
6087           || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
6088           || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
6089               && !OBJECT_P (false_rtx))
6090           || reg_mentioned_p (true_rtx, false_rtx)
6091           || rtx_equal_p (false_rtx, XEXP (cond, 0))))
6092     {
6093       true_code = reversed_comparison_code (cond, NULL);
6094       SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
6095       SUBST (XEXP (x, 1), false_rtx);
6096       SUBST (XEXP (x, 2), true_rtx);
6097
6098       temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
6099       cond = XEXP (x, 0);
6100
6101       /* It is possible that the conditional has been simplified out.  */
6102       true_code = GET_CODE (cond);
6103       comparison_p = COMPARISON_P (cond);
6104     }
6105
6106   /* If the two arms are identical, we don't need the comparison.  */
6107
6108   if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6109     return true_rtx;
6110
6111   /* Convert a == b ? b : a to "a".  */
6112   if (true_code == EQ && ! side_effects_p (cond)
6113       && !HONOR_NANS (mode)
6114       && rtx_equal_p (XEXP (cond, 0), false_rtx)
6115       && rtx_equal_p (XEXP (cond, 1), true_rtx))
6116     return false_rtx;
6117   else if (true_code == NE && ! side_effects_p (cond)
6118            && !HONOR_NANS (mode)
6119            && rtx_equal_p (XEXP (cond, 0), true_rtx)
6120            && rtx_equal_p (XEXP (cond, 1), false_rtx))
6121     return true_rtx;
6122
6123   /* Look for cases where we have (abs x) or (neg (abs X)).  */
6124
6125   if (GET_MODE_CLASS (mode) == MODE_INT
6126       && comparison_p
6127       && XEXP (cond, 1) == const0_rtx
6128       && GET_CODE (false_rtx) == NEG
6129       && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6130       && rtx_equal_p (true_rtx, XEXP (cond, 0))
6131       && ! side_effects_p (true_rtx))
6132     switch (true_code)
6133       {
6134       case GT:
6135       case GE:
6136         return simplify_gen_unary (ABS, mode, true_rtx, mode);
6137       case LT:
6138       case LE:
6139         return
6140           simplify_gen_unary (NEG, mode,
6141                               simplify_gen_unary (ABS, mode, true_rtx, mode),
6142                               mode);
6143       default:
6144         break;
6145       }
6146
6147   /* Look for MIN or MAX.  */
6148
6149   if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
6150       && comparison_p
6151       && rtx_equal_p (XEXP (cond, 0), true_rtx)
6152       && rtx_equal_p (XEXP (cond, 1), false_rtx)
6153       && ! side_effects_p (cond))
6154     switch (true_code)
6155       {
6156       case GE:
6157       case GT:
6158         return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
6159       case LE:
6160       case LT:
6161         return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
6162       case GEU:
6163       case GTU:
6164         return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
6165       case LEU:
6166       case LTU:
6167         return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
6168       default:
6169         break;
6170       }
6171
6172   /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6173      second operand is zero, this can be done as (OP Z (mult COND C2)) where
6174      C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6175      SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6176      We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6177      neither 1 or -1, but it isn't worth checking for.  */
6178
6179   if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6180       && comparison_p
6181       && GET_MODE_CLASS (mode) == MODE_INT
6182       && ! side_effects_p (x))
6183     {
6184       rtx t = make_compound_operation (true_rtx, SET);
6185       rtx f = make_compound_operation (false_rtx, SET);
6186       rtx cond_op0 = XEXP (cond, 0);
6187       rtx cond_op1 = XEXP (cond, 1);
6188       enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6189       enum machine_mode m = mode;
6190       rtx z = 0, c1 = NULL_RTX;
6191
6192       if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6193            || GET_CODE (t) == IOR || GET_CODE (t) == XOR
6194            || GET_CODE (t) == ASHIFT
6195            || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6196           && rtx_equal_p (XEXP (t, 0), f))
6197         c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6198
6199       /* If an identity-zero op is commutative, check whether there
6200          would be a match if we swapped the operands.  */
6201       else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6202                 || GET_CODE (t) == XOR)
6203                && rtx_equal_p (XEXP (t, 1), f))
6204         c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6205       else if (GET_CODE (t) == SIGN_EXTEND
6206                && (GET_CODE (XEXP (t, 0)) == PLUS
6207                    || GET_CODE (XEXP (t, 0)) == MINUS
6208                    || GET_CODE (XEXP (t, 0)) == IOR
6209                    || GET_CODE (XEXP (t, 0)) == XOR
6210                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6211                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6212                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6213                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6214                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6215                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6216                && (num_sign_bit_copies (f, GET_MODE (f))
6217                    > (unsigned int)
6218                      (GET_MODE_PRECISION (mode)
6219                       - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 0))))))
6220         {
6221           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6222           extend_op = SIGN_EXTEND;
6223           m = GET_MODE (XEXP (t, 0));
6224         }
6225       else if (GET_CODE (t) == SIGN_EXTEND
6226                && (GET_CODE (XEXP (t, 0)) == PLUS
6227                    || GET_CODE (XEXP (t, 0)) == IOR
6228                    || GET_CODE (XEXP (t, 0)) == XOR)
6229                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6230                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6231                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6232                && (num_sign_bit_copies (f, GET_MODE (f))
6233                    > (unsigned int)
6234                      (GET_MODE_PRECISION (mode)
6235                       - GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (t, 0), 1))))))
6236         {
6237           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6238           extend_op = SIGN_EXTEND;
6239           m = GET_MODE (XEXP (t, 0));
6240         }
6241       else if (GET_CODE (t) == ZERO_EXTEND
6242                && (GET_CODE (XEXP (t, 0)) == PLUS
6243                    || GET_CODE (XEXP (t, 0)) == MINUS
6244                    || GET_CODE (XEXP (t, 0)) == IOR
6245                    || GET_CODE (XEXP (t, 0)) == XOR
6246                    || GET_CODE (XEXP (t, 0)) == ASHIFT
6247                    || GET_CODE (XEXP (t, 0)) == LSHIFTRT
6248                    || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6249                && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6250                && HWI_COMPUTABLE_MODE_P (mode)
6251                && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6252                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6253                && ((nonzero_bits (f, GET_MODE (f))
6254                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
6255                    == 0))
6256         {
6257           c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6258           extend_op = ZERO_EXTEND;
6259           m = GET_MODE (XEXP (t, 0));
6260         }
6261       else if (GET_CODE (t) == ZERO_EXTEND
6262                && (GET_CODE (XEXP (t, 0)) == PLUS
6263                    || GET_CODE (XEXP (t, 0)) == IOR
6264                    || GET_CODE (XEXP (t, 0)) == XOR)
6265                && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6266                && HWI_COMPUTABLE_MODE_P (mode)
6267                && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6268                && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6269                && ((nonzero_bits (f, GET_MODE (f))
6270                     & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
6271                    == 0))
6272         {
6273           c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6274           extend_op = ZERO_EXTEND;
6275           m = GET_MODE (XEXP (t, 0));
6276         }
6277
6278       if (z)
6279         {
6280           temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
6281                                                  cond_op0, cond_op1),
6282                         pc_rtx, pc_rtx, 0, 0, 0);
6283           temp = simplify_gen_binary (MULT, m, temp,
6284                                       simplify_gen_binary (MULT, m, c1,
6285                                                            const_true_rtx));
6286           temp = subst (temp, pc_rtx, pc_rtx, 0, 0, 0);
6287           temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
6288
6289           if (extend_op != UNKNOWN)
6290             temp = simplify_gen_unary (extend_op, mode, temp, m);
6291
6292           return temp;
6293         }
6294     }
6295
6296   /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6297      1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6298      negation of a single bit, we can convert this operation to a shift.  We
6299      can actually do this more generally, but it doesn't seem worth it.  */
6300
6301   if (true_code == NE && XEXP (cond, 1) == const0_rtx
6302       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6303       && ((1 == nonzero_bits (XEXP (cond, 0), mode)
6304            && (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6305           || ((num_sign_bit_copies (XEXP (cond, 0), mode)
6306                == GET_MODE_PRECISION (mode))
6307               && (i = exact_log2 (-UINTVAL (true_rtx))) >= 0)))
6308     return
6309       simplify_shift_const (NULL_RTX, ASHIFT, mode,
6310                             gen_lowpart (mode, XEXP (cond, 0)), i);
6311
6312   /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8.  */
6313   if (true_code == NE && XEXP (cond, 1) == const0_rtx
6314       && false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6315       && GET_MODE (XEXP (cond, 0)) == mode
6316       && (UINTVAL (true_rtx) & GET_MODE_MASK (mode))
6317           == nonzero_bits (XEXP (cond, 0), mode)
6318       && (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
6319     return XEXP (cond, 0);
6320
6321   return x;
6322 }
6323 \f
6324 /* Simplify X, a SET expression.  Return the new expression.  */
6325
6326 static rtx
6327 simplify_set (rtx x)
6328 {
6329   rtx src = SET_SRC (x);
6330   rtx dest = SET_DEST (x);
6331   enum machine_mode mode
6332     = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6333   rtx other_insn;
6334   rtx *cc_use;
6335
6336   /* (set (pc) (return)) gets written as (return).  */
6337   if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6338     return src;
6339
6340   /* Now that we know for sure which bits of SRC we are using, see if we can
6341      simplify the expression for the object knowing that we only need the
6342      low-order bits.  */
6343
6344   if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6345     {
6346       src = force_to_mode (src, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
6347       SUBST (SET_SRC (x), src);
6348     }
6349
6350   /* If we are setting CC0 or if the source is a COMPARE, look for the use of
6351      the comparison result and try to simplify it unless we already have used
6352      undobuf.other_insn.  */
6353   if ((GET_MODE_CLASS (mode) == MODE_CC
6354        || GET_CODE (src) == COMPARE
6355        || CC0_P (dest))
6356       && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
6357       && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6358       && COMPARISON_P (*cc_use)
6359       && rtx_equal_p (XEXP (*cc_use, 0), dest))
6360     {
6361       enum rtx_code old_code = GET_CODE (*cc_use);
6362       enum rtx_code new_code;
6363       rtx op0, op1, tmp;
6364       int other_changed = 0;
6365       rtx inner_compare = NULL_RTX;
6366       enum machine_mode compare_mode = GET_MODE (dest);
6367
6368       if (GET_CODE (src) == COMPARE)
6369         {
6370           op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6371           if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6372             {
6373               inner_compare = op0;
6374               op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6375             }
6376         }
6377       else
6378         op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6379
6380       tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
6381                                            op0, op1);
6382       if (!tmp)
6383         new_code = old_code;
6384       else if (!CONSTANT_P (tmp))
6385         {
6386           new_code = GET_CODE (tmp);
6387           op0 = XEXP (tmp, 0);
6388           op1 = XEXP (tmp, 1);
6389         }
6390       else
6391         {
6392           rtx pat = PATTERN (other_insn);
6393           undobuf.other_insn = other_insn;
6394           SUBST (*cc_use, tmp);
6395
6396           /* Attempt to simplify CC user.  */
6397           if (GET_CODE (pat) == SET)
6398             {
6399               rtx new_rtx = simplify_rtx (SET_SRC (pat));
6400               if (new_rtx != NULL_RTX)
6401                 SUBST (SET_SRC (pat), new_rtx);
6402             }
6403
6404           /* Convert X into a no-op move.  */
6405           SUBST (SET_DEST (x), pc_rtx);
6406           SUBST (SET_SRC (x), pc_rtx);
6407           return x;
6408         }
6409
6410       /* Simplify our comparison, if possible.  */
6411       new_code = simplify_comparison (new_code, &op0, &op1);
6412
6413 #ifdef SELECT_CC_MODE
6414       /* If this machine has CC modes other than CCmode, check to see if we
6415          need to use a different CC mode here.  */
6416       if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6417         compare_mode = GET_MODE (op0);
6418       else if (inner_compare
6419                && GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6420                && new_code == old_code
6421                && op0 == XEXP (inner_compare, 0)
6422                && op1 == XEXP (inner_compare, 1))
6423         compare_mode = GET_MODE (inner_compare);
6424       else
6425         compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6426
6427 #ifndef HAVE_cc0
6428       /* If the mode changed, we have to change SET_DEST, the mode in the
6429          compare, and the mode in the place SET_DEST is used.  If SET_DEST is
6430          a hard register, just build new versions with the proper mode.  If it
6431          is a pseudo, we lose unless it is only time we set the pseudo, in
6432          which case we can safely change its mode.  */
6433       if (compare_mode != GET_MODE (dest))
6434         {
6435           if (can_change_dest_mode (dest, 0, compare_mode))
6436             {
6437               unsigned int regno = REGNO (dest);
6438               rtx new_dest;
6439
6440               if (regno < FIRST_PSEUDO_REGISTER)
6441                 new_dest = gen_rtx_REG (compare_mode, regno);
6442               else
6443                 {
6444                   SUBST_MODE (regno_reg_rtx[regno], compare_mode);
6445                   new_dest = regno_reg_rtx[regno];
6446                 }
6447
6448               SUBST (SET_DEST (x), new_dest);
6449               SUBST (XEXP (*cc_use, 0), new_dest);
6450               other_changed = 1;
6451
6452               dest = new_dest;
6453             }
6454         }
6455 #endif  /* cc0 */
6456 #endif  /* SELECT_CC_MODE */
6457
6458       /* If the code changed, we have to build a new comparison in
6459          undobuf.other_insn.  */
6460       if (new_code != old_code)
6461         {
6462           int other_changed_previously = other_changed;
6463           unsigned HOST_WIDE_INT mask;
6464           rtx old_cc_use = *cc_use;
6465
6466           SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6467                                           dest, const0_rtx));
6468           other_changed = 1;
6469
6470           /* If the only change we made was to change an EQ into an NE or
6471              vice versa, OP0 has only one bit that might be nonzero, and OP1
6472              is zero, check if changing the user of the condition code will
6473              produce a valid insn.  If it won't, we can keep the original code
6474              in that insn by surrounding our operation with an XOR.  */
6475
6476           if (((old_code == NE && new_code == EQ)
6477                || (old_code == EQ && new_code == NE))
6478               && ! other_changed_previously && op1 == const0_rtx
6479               && HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
6480               && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
6481             {
6482               rtx pat = PATTERN (other_insn), note = 0;
6483
6484               if ((recog_for_combine (&pat, other_insn, &note) < 0
6485                    && ! check_asm_operands (pat)))
6486                 {
6487                   *cc_use = old_cc_use;
6488                   other_changed = 0;
6489
6490                   op0 = simplify_gen_binary (XOR, GET_MODE (op0),
6491                                              op0, GEN_INT (mask));
6492                 }
6493             }
6494         }
6495
6496       if (other_changed)
6497         undobuf.other_insn = other_insn;
6498
6499       /* Otherwise, if we didn't previously have a COMPARE in the
6500          correct mode, we need one.  */
6501       if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
6502         {
6503           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6504           src = SET_SRC (x);
6505         }
6506       else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6507         {
6508           SUBST (SET_SRC (x), op0);
6509           src = SET_SRC (x);
6510         }
6511       /* Otherwise, update the COMPARE if needed.  */
6512       else if (XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6513         {
6514           SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6515           src = SET_SRC (x);
6516         }
6517     }
6518   else
6519     {
6520       /* Get SET_SRC in a form where we have placed back any
6521          compound expressions.  Then do the checks below.  */
6522       src = make_compound_operation (src, SET);
6523       SUBST (SET_SRC (x), src);
6524     }
6525
6526   /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6527      and X being a REG or (subreg (reg)), we may be able to convert this to
6528      (set (subreg:m2 x) (op)).
6529
6530      We can always do this if M1 is narrower than M2 because that means that
6531      we only care about the low bits of the result.
6532
6533      However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6534      perform a narrower operation than requested since the high-order bits will
6535      be undefined.  On machine where it is defined, this transformation is safe
6536      as long as M1 and M2 have the same number of words.  */
6537
6538   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6539       && !OBJECT_P (SUBREG_REG (src))
6540       && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
6541            / UNITS_PER_WORD)
6542           == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
6543                + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
6544 #ifndef WORD_REGISTER_OPERATIONS
6545       && (GET_MODE_SIZE (GET_MODE (src))
6546         < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
6547 #endif
6548 #ifdef CANNOT_CHANGE_MODE_CLASS
6549       && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6550             && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
6551                                          GET_MODE (SUBREG_REG (src)),
6552                                          GET_MODE (src)))
6553 #endif
6554       && (REG_P (dest)
6555           || (GET_CODE (dest) == SUBREG
6556               && REG_P (SUBREG_REG (dest)))))
6557     {
6558       SUBST (SET_DEST (x),
6559              gen_lowpart (GET_MODE (SUBREG_REG (src)),
6560                                       dest));
6561       SUBST (SET_SRC (x), SUBREG_REG (src));
6562
6563       src = SET_SRC (x), dest = SET_DEST (x);
6564     }
6565
6566 #ifdef HAVE_cc0
6567   /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
6568      in SRC.  */
6569   if (dest == cc0_rtx
6570       && GET_CODE (src) == SUBREG
6571       && subreg_lowpart_p (src)
6572       && (GET_MODE_PRECISION (GET_MODE (src))
6573           < GET_MODE_PRECISION (GET_MODE (SUBREG_REG (src)))))
6574     {
6575       rtx inner = SUBREG_REG (src);
6576       enum machine_mode inner_mode = GET_MODE (inner);
6577
6578       /* Here we make sure that we don't have a sign bit on.  */
6579       if (val_signbit_known_clear_p (GET_MODE (src),
6580                                      nonzero_bits (inner, inner_mode)))
6581         {
6582           SUBST (SET_SRC (x), inner);
6583           src = SET_SRC (x);
6584         }
6585     }
6586 #endif
6587
6588 #ifdef LOAD_EXTEND_OP
6589   /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6590      would require a paradoxical subreg.  Replace the subreg with a
6591      zero_extend to avoid the reload that would otherwise be required.  */
6592
6593   if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6594       && INTEGRAL_MODE_P (GET_MODE (SUBREG_REG (src)))
6595       && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
6596       && SUBREG_BYTE (src) == 0
6597       && paradoxical_subreg_p (src)
6598       && MEM_P (SUBREG_REG (src)))
6599     {
6600       SUBST (SET_SRC (x),
6601              gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
6602                             GET_MODE (src), SUBREG_REG (src)));
6603
6604       src = SET_SRC (x);
6605     }
6606 #endif
6607
6608   /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
6609      are comparing an item known to be 0 or -1 against 0, use a logical
6610      operation instead. Check for one of the arms being an IOR of the other
6611      arm with some value.  We compute three terms to be IOR'ed together.  In
6612      practice, at most two will be nonzero.  Then we do the IOR's.  */
6613
6614   if (GET_CODE (dest) != PC
6615       && GET_CODE (src) == IF_THEN_ELSE
6616       && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
6617       && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
6618       && XEXP (XEXP (src, 0), 1) == const0_rtx
6619       && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
6620 #ifdef HAVE_conditional_move
6621       && ! can_conditionally_move_p (GET_MODE (src))
6622 #endif
6623       && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
6624                                GET_MODE (XEXP (XEXP (src, 0), 0)))
6625           == GET_MODE_PRECISION (GET_MODE (XEXP (XEXP (src, 0), 0))))
6626       && ! side_effects_p (src))
6627     {
6628       rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
6629                       ? XEXP (src, 1) : XEXP (src, 2));
6630       rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
6631                    ? XEXP (src, 2) : XEXP (src, 1));
6632       rtx term1 = const0_rtx, term2, term3;
6633
6634       if (GET_CODE (true_rtx) == IOR
6635           && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
6636         term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
6637       else if (GET_CODE (true_rtx) == IOR
6638                && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
6639         term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
6640       else if (GET_CODE (false_rtx) == IOR
6641                && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
6642         term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
6643       else if (GET_CODE (false_rtx) == IOR
6644                && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
6645         term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
6646
6647       term2 = simplify_gen_binary (AND, GET_MODE (src),
6648                                    XEXP (XEXP (src, 0), 0), true_rtx);
6649       term3 = simplify_gen_binary (AND, GET_MODE (src),
6650                                    simplify_gen_unary (NOT, GET_MODE (src),
6651                                                        XEXP (XEXP (src, 0), 0),
6652                                                        GET_MODE (src)),
6653                                    false_rtx);
6654
6655       SUBST (SET_SRC (x),
6656              simplify_gen_binary (IOR, GET_MODE (src),
6657                                   simplify_gen_binary (IOR, GET_MODE (src),
6658                                                        term1, term2),
6659                                   term3));
6660
6661       src = SET_SRC (x);
6662     }
6663
6664   /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
6665      whole thing fail.  */
6666   if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
6667     return src;
6668   else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
6669     return dest;
6670   else
6671     /* Convert this into a field assignment operation, if possible.  */
6672     return make_field_assignment (x);
6673 }
6674 \f
6675 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
6676    result.  */
6677
6678 static rtx
6679 simplify_logical (rtx x)
6680 {
6681   enum machine_mode mode = GET_MODE (x);
6682   rtx op0 = XEXP (x, 0);
6683   rtx op1 = XEXP (x, 1);
6684
6685   switch (GET_CODE (x))
6686     {
6687     case AND:
6688       /* We can call simplify_and_const_int only if we don't lose
6689          any (sign) bits when converting INTVAL (op1) to
6690          "unsigned HOST_WIDE_INT".  */
6691       if (CONST_INT_P (op1)
6692           && (HWI_COMPUTABLE_MODE_P (mode)
6693               || INTVAL (op1) > 0))
6694         {
6695           x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
6696           if (GET_CODE (x) != AND)
6697             return x;
6698
6699           op0 = XEXP (x, 0);
6700           op1 = XEXP (x, 1);
6701         }
6702
6703       /* If we have any of (and (ior A B) C) or (and (xor A B) C),
6704          apply the distributive law and then the inverse distributive
6705          law to see if things simplify.  */
6706       if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
6707         {
6708           rtx result = distribute_and_simplify_rtx (x, 0);
6709           if (result)
6710             return result;
6711         }
6712       if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
6713         {
6714           rtx result = distribute_and_simplify_rtx (x, 1);
6715           if (result)
6716             return result;
6717         }
6718       break;
6719
6720     case IOR:
6721       /* If we have (ior (and A B) C), apply the distributive law and then
6722          the inverse distributive law to see if things simplify.  */
6723
6724       if (GET_CODE (op0) == AND)
6725         {
6726           rtx result = distribute_and_simplify_rtx (x, 0);
6727           if (result)
6728             return result;
6729         }
6730
6731       if (GET_CODE (op1) == AND)
6732         {
6733           rtx result = distribute_and_simplify_rtx (x, 1);
6734           if (result)
6735             return result;
6736         }
6737       break;
6738
6739     default:
6740       gcc_unreachable ();
6741     }
6742
6743   return x;
6744 }
6745 \f
6746 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
6747    operations" because they can be replaced with two more basic operations.
6748    ZERO_EXTEND is also considered "compound" because it can be replaced with
6749    an AND operation, which is simpler, though only one operation.
6750
6751    The function expand_compound_operation is called with an rtx expression
6752    and will convert it to the appropriate shifts and AND operations,
6753    simplifying at each stage.
6754
6755    The function make_compound_operation is called to convert an expression
6756    consisting of shifts and ANDs into the equivalent compound expression.
6757    It is the inverse of this function, loosely speaking.  */
6758
6759 static rtx
6760 expand_compound_operation (rtx x)
6761 {
6762   unsigned HOST_WIDE_INT pos = 0, len;
6763   int unsignedp = 0;
6764   unsigned int modewidth;
6765   rtx tem;
6766
6767   switch (GET_CODE (x))
6768     {
6769     case ZERO_EXTEND:
6770       unsignedp = 1;
6771     case SIGN_EXTEND:
6772       /* We can't necessarily use a const_int for a multiword mode;
6773          it depends on implicitly extending the value.
6774          Since we don't know the right way to extend it,
6775          we can't tell whether the implicit way is right.
6776
6777          Even for a mode that is no wider than a const_int,
6778          we can't win, because we need to sign extend one of its bits through
6779          the rest of it, and we don't know which bit.  */
6780       if (CONST_INT_P (XEXP (x, 0)))
6781         return x;
6782
6783       /* Return if (subreg:MODE FROM 0) is not a safe replacement for
6784          (zero_extend:MODE FROM) or (sign_extend:MODE FROM).  It is for any MEM
6785          because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
6786          reloaded. If not for that, MEM's would very rarely be safe.
6787
6788          Reject MODEs bigger than a word, because we might not be able
6789          to reference a two-register group starting with an arbitrary register
6790          (and currently gen_lowpart might crash for a SUBREG).  */
6791
6792       if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
6793         return x;
6794
6795       /* Reject MODEs that aren't scalar integers because turning vector
6796          or complex modes into shifts causes problems.  */
6797
6798       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6799         return x;
6800
6801       len = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)));
6802       /* If the inner object has VOIDmode (the only way this can happen
6803          is if it is an ASM_OPERANDS), we can't do anything since we don't
6804          know how much masking to do.  */
6805       if (len == 0)
6806         return x;
6807
6808       break;
6809
6810     case ZERO_EXTRACT:
6811       unsignedp = 1;
6812
6813       /* ... fall through ...  */
6814
6815     case SIGN_EXTRACT:
6816       /* If the operand is a CLOBBER, just return it.  */
6817       if (GET_CODE (XEXP (x, 0)) == CLOBBER)
6818         return XEXP (x, 0);
6819
6820       if (!CONST_INT_P (XEXP (x, 1))
6821           || !CONST_INT_P (XEXP (x, 2))
6822           || GET_MODE (XEXP (x, 0)) == VOIDmode)
6823         return x;
6824
6825       /* Reject MODEs that aren't scalar integers because turning vector
6826          or complex modes into shifts causes problems.  */
6827
6828       if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
6829         return x;
6830
6831       len = INTVAL (XEXP (x, 1));
6832       pos = INTVAL (XEXP (x, 2));
6833
6834       /* This should stay within the object being extracted, fail otherwise.  */
6835       if (len + pos > GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))))
6836         return x;
6837
6838       if (BITS_BIG_ENDIAN)
6839         pos = GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) - len - pos;
6840
6841       break;
6842
6843     default:
6844       return x;
6845     }
6846   /* Convert sign extension to zero extension, if we know that the high
6847      bit is not set, as this is easier to optimize.  It will be converted
6848      back to cheaper alternative in make_extraction.  */
6849   if (GET_CODE (x) == SIGN_EXTEND
6850       && (HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6851           && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6852                 & ~(((unsigned HOST_WIDE_INT)
6853                       GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
6854                      >> 1))
6855                == 0)))
6856     {
6857       rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
6858       rtx temp2 = expand_compound_operation (temp);
6859
6860       /* Make sure this is a profitable operation.  */
6861       if (set_src_cost (x, optimize_this_for_speed_p)
6862           > set_src_cost (temp2, optimize_this_for_speed_p))
6863        return temp2;
6864       else if (set_src_cost (x, optimize_this_for_speed_p)
6865                > set_src_cost (temp, optimize_this_for_speed_p))
6866        return temp;
6867       else
6868        return x;
6869     }
6870
6871   /* We can optimize some special cases of ZERO_EXTEND.  */
6872   if (GET_CODE (x) == ZERO_EXTEND)
6873     {
6874       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
6875          know that the last value didn't have any inappropriate bits
6876          set.  */
6877       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6878           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6879           && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6880           && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
6881               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6882         return XEXP (XEXP (x, 0), 0);
6883
6884       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6885       if (GET_CODE (XEXP (x, 0)) == SUBREG
6886           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6887           && subreg_lowpart_p (XEXP (x, 0))
6888           && HWI_COMPUTABLE_MODE_P (GET_MODE (x))
6889           && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
6890               & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6891         return SUBREG_REG (XEXP (x, 0));
6892
6893       /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
6894          is a comparison and STORE_FLAG_VALUE permits.  This is like
6895          the first case, but it works even when GET_MODE (x) is larger
6896          than HOST_WIDE_INT.  */
6897       if (GET_CODE (XEXP (x, 0)) == TRUNCATE
6898           && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
6899           && COMPARISON_P (XEXP (XEXP (x, 0), 0))
6900           && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6901               <= HOST_BITS_PER_WIDE_INT)
6902           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6903         return XEXP (XEXP (x, 0), 0);
6904
6905       /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)).  */
6906       if (GET_CODE (XEXP (x, 0)) == SUBREG
6907           && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
6908           && subreg_lowpart_p (XEXP (x, 0))
6909           && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
6910           && (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0)))
6911               <= HOST_BITS_PER_WIDE_INT)
6912           && (STORE_FLAG_VALUE & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6913         return SUBREG_REG (XEXP (x, 0));
6914
6915     }
6916
6917   /* If we reach here, we want to return a pair of shifts.  The inner
6918      shift is a left shift of BITSIZE - POS - LEN bits.  The outer
6919      shift is a right shift of BITSIZE - LEN bits.  It is arithmetic or
6920      logical depending on the value of UNSIGNEDP.
6921
6922      If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
6923      converted into an AND of a shift.
6924
6925      We must check for the case where the left shift would have a negative
6926      count.  This can happen in a case like (x >> 31) & 255 on machines
6927      that can't shift by a constant.  On those machines, we would first
6928      combine the shift with the AND to produce a variable-position
6929      extraction.  Then the constant of 31 would be substituted in
6930      to produce such a position.  */
6931
6932   modewidth = GET_MODE_PRECISION (GET_MODE (x));
6933   if (modewidth >= pos + len)
6934     {
6935       enum machine_mode mode = GET_MODE (x);
6936       tem = gen_lowpart (mode, XEXP (x, 0));
6937       if (!tem || GET_CODE (tem) == CLOBBER)
6938         return x;
6939       tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
6940                                   tem, modewidth - pos - len);
6941       tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
6942                                   mode, tem, modewidth - len);
6943     }
6944   else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
6945     tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
6946                                   simplify_shift_const (NULL_RTX, LSHIFTRT,
6947                                                         GET_MODE (x),
6948                                                         XEXP (x, 0), pos),
6949                                   ((unsigned HOST_WIDE_INT) 1 << len) - 1);
6950   else
6951     /* Any other cases we can't handle.  */
6952     return x;
6953
6954   /* If we couldn't do this for some reason, return the original
6955      expression.  */
6956   if (GET_CODE (tem) == CLOBBER)
6957     return x;
6958
6959   return tem;
6960 }
6961 \f
6962 /* X is a SET which contains an assignment of one object into
6963    a part of another (such as a bit-field assignment, STRICT_LOW_PART,
6964    or certain SUBREGS). If possible, convert it into a series of
6965    logical operations.
6966
6967    We half-heartedly support variable positions, but do not at all
6968    support variable lengths.  */
6969
6970 static const_rtx
6971 expand_field_assignment (const_rtx x)
6972 {
6973   rtx inner;
6974   rtx pos;                      /* Always counts from low bit.  */
6975   int len;
6976   rtx mask, cleared, masked;
6977   enum machine_mode compute_mode;
6978
6979   /* Loop until we find something we can't simplify.  */
6980   while (1)
6981     {
6982       if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
6983           && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
6984         {
6985           inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
6986           len = GET_MODE_PRECISION (GET_MODE (XEXP (SET_DEST (x), 0)));
6987           pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
6988         }
6989       else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
6990                && CONST_INT_P (XEXP (SET_DEST (x), 1)))
6991         {
6992           inner = XEXP (SET_DEST (x), 0);
6993           len = INTVAL (XEXP (SET_DEST (x), 1));
6994           pos = XEXP (SET_DEST (x), 2);
6995
6996           /* A constant position should stay within the width of INNER.  */
6997           if (CONST_INT_P (pos)
6998               && INTVAL (pos) + len > GET_MODE_PRECISION (GET_MODE (inner)))
6999             break;
7000
7001           if (BITS_BIG_ENDIAN)
7002             {
7003               if (CONST_INT_P (pos))
7004                 pos = GEN_INT (GET_MODE_PRECISION (GET_MODE (inner)) - len
7005                                - INTVAL (pos));
7006               else if (GET_CODE (pos) == MINUS
7007                        && CONST_INT_P (XEXP (pos, 1))
7008                        && (INTVAL (XEXP (pos, 1))
7009                            == GET_MODE_PRECISION (GET_MODE (inner)) - len))
7010                 /* If position is ADJUST - X, new position is X.  */
7011                 pos = XEXP (pos, 0);
7012               else
7013                 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
7014                                            GEN_INT (GET_MODE_PRECISION (
7015                                                     GET_MODE (inner))
7016                                                     - len),
7017                                            pos);
7018             }
7019         }
7020
7021       /* A SUBREG between two modes that occupy the same numbers of words
7022          can be done by moving the SUBREG to the source.  */
7023       else if (GET_CODE (SET_DEST (x)) == SUBREG
7024                /* We need SUBREGs to compute nonzero_bits properly.  */
7025                && nonzero_sign_valid
7026                && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
7027                      + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
7028                    == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
7029                         + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
7030         {
7031           x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
7032                            gen_lowpart
7033                            (GET_MODE (SUBREG_REG (SET_DEST (x))),
7034                             SET_SRC (x)));
7035           continue;
7036         }
7037       else
7038         break;
7039
7040       while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7041         inner = SUBREG_REG (inner);
7042
7043       compute_mode = GET_MODE (inner);
7044
7045       /* Don't attempt bitwise arithmetic on non scalar integer modes.  */
7046       if (! SCALAR_INT_MODE_P (compute_mode))
7047         {
7048           enum machine_mode imode;
7049
7050           /* Don't do anything for vector or complex integral types.  */
7051           if (! FLOAT_MODE_P (compute_mode))
7052             break;
7053
7054           /* Try to find an integral mode to pun with.  */
7055           imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
7056           if (imode == BLKmode)
7057             break;
7058
7059           compute_mode = imode;
7060           inner = gen_lowpart (imode, inner);
7061         }
7062
7063       /* Compute a mask of LEN bits, if we can do this on the host machine.  */
7064       if (len >= HOST_BITS_PER_WIDE_INT)
7065         break;
7066
7067       /* Now compute the equivalent expression.  Make a copy of INNER
7068          for the SET_DEST in case it is a MEM into which we will substitute;
7069          we don't want shared RTL in that case.  */
7070       mask = GEN_INT (((unsigned HOST_WIDE_INT) 1 << len) - 1);
7071       cleared = simplify_gen_binary (AND, compute_mode,
7072                                      simplify_gen_unary (NOT, compute_mode,
7073                                        simplify_gen_binary (ASHIFT,
7074                                                             compute_mode,
7075                                                             mask, pos),
7076                                        compute_mode),
7077                                      inner);
7078       masked = simplify_gen_binary (ASHIFT, compute_mode,
7079                                     simplify_gen_binary (
7080                                       AND, compute_mode,
7081                                       gen_lowpart (compute_mode, SET_SRC (x)),
7082                                       mask),
7083                                     pos);
7084
7085       x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
7086                        simplify_gen_binary (IOR, compute_mode,
7087                                             cleared, masked));
7088     }
7089
7090   return x;
7091 }
7092 \f
7093 /* Return an RTX for a reference to LEN bits of INNER.  If POS_RTX is nonzero,
7094    it is an RTX that represents a variable starting position; otherwise,
7095    POS is the (constant) starting bit position (counted from the LSB).
7096
7097    UNSIGNEDP is nonzero for an unsigned reference and zero for a
7098    signed reference.
7099
7100    IN_DEST is nonzero if this is a reference in the destination of a
7101    SET.  This is used when a ZERO_ or SIGN_EXTRACT isn't needed.  If nonzero,
7102    a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7103    be used.
7104
7105    IN_COMPARE is nonzero if we are in a COMPARE.  This means that a
7106    ZERO_EXTRACT should be built even for bits starting at bit 0.
7107
7108    MODE is the desired mode of the result (if IN_DEST == 0).
7109
7110    The result is an RTX for the extraction or NULL_RTX if the target
7111    can't handle it.  */
7112
7113 static rtx
7114 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7115                  rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
7116                  int in_dest, int in_compare)
7117 {
7118   /* This mode describes the size of the storage area
7119      to fetch the overall value from.  Within that, we
7120      ignore the POS lowest bits, etc.  */
7121   enum machine_mode is_mode = GET_MODE (inner);
7122   enum machine_mode inner_mode;
7123   enum machine_mode wanted_inner_mode;
7124   enum machine_mode wanted_inner_reg_mode = word_mode;
7125   enum machine_mode pos_mode = word_mode;
7126   enum machine_mode extraction_mode = word_mode;
7127   enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
7128   rtx new_rtx = 0;
7129   rtx orig_pos_rtx = pos_rtx;
7130   HOST_WIDE_INT orig_pos;
7131
7132   if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7133     {
7134       /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7135          consider just the QI as the memory to extract from.
7136          The subreg adds or removes high bits; its mode is
7137          irrelevant to the meaning of this extraction,
7138          since POS and LEN count from the lsb.  */
7139       if (MEM_P (SUBREG_REG (inner)))
7140         is_mode = GET_MODE (SUBREG_REG (inner));
7141       inner = SUBREG_REG (inner);
7142     }
7143   else if (GET_CODE (inner) == ASHIFT
7144            && CONST_INT_P (XEXP (inner, 1))
7145            && pos_rtx == 0 && pos == 0
7146            && len > UINTVAL (XEXP (inner, 1)))
7147     {
7148       /* We're extracting the least significant bits of an rtx
7149          (ashift X (const_int C)), where LEN > C.  Extract the
7150          least significant (LEN - C) bits of X, giving an rtx
7151          whose mode is MODE, then shift it left C times.  */
7152       new_rtx = make_extraction (mode, XEXP (inner, 0),
7153                              0, 0, len - INTVAL (XEXP (inner, 1)),
7154                              unsignedp, in_dest, in_compare);
7155       if (new_rtx != 0)
7156         return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7157     }
7158
7159   inner_mode = GET_MODE (inner);
7160
7161   if (pos_rtx && CONST_INT_P (pos_rtx))
7162     pos = INTVAL (pos_rtx), pos_rtx = 0;
7163
7164   /* See if this can be done without an extraction.  We never can if the
7165      width of the field is not the same as that of some integer mode. For
7166      registers, we can only avoid the extraction if the position is at the
7167      low-order bit and this is either not in the destination or we have the
7168      appropriate STRICT_LOW_PART operation available.
7169
7170      For MEM, we can avoid an extract if the field starts on an appropriate
7171      boundary and we can change the mode of the memory reference.  */
7172
7173   if (tmode != BLKmode
7174       && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7175            && !MEM_P (inner)
7176            && (inner_mode == tmode
7177                || !REG_P (inner)
7178                || TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7179                || reg_truncated_to_mode (tmode, inner))
7180            && (! in_dest
7181                || (REG_P (inner)
7182                    && have_insn_for (STRICT_LOW_PART, tmode))))
7183           || (MEM_P (inner) && pos_rtx == 0
7184               && (pos
7185                   % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7186                      : BITS_PER_UNIT)) == 0
7187               /* We can't do this if we are widening INNER_MODE (it
7188                  may not be aligned, for one thing).  */
7189               && GET_MODE_PRECISION (inner_mode) >= GET_MODE_PRECISION (tmode)
7190               && (inner_mode == tmode
7191                   || (! mode_dependent_address_p (XEXP (inner, 0))
7192                       && ! MEM_VOLATILE_P (inner))))))
7193     {
7194       /* If INNER is a MEM, make a new MEM that encompasses just the desired
7195          field.  If the original and current mode are the same, we need not
7196          adjust the offset.  Otherwise, we do if bytes big endian.
7197
7198          If INNER is not a MEM, get a piece consisting of just the field
7199          of interest (in this case POS % BITS_PER_WORD must be 0).  */
7200
7201       if (MEM_P (inner))
7202         {
7203           HOST_WIDE_INT offset;
7204
7205           /* POS counts from lsb, but make OFFSET count in memory order.  */
7206           if (BYTES_BIG_ENDIAN)
7207             offset = (GET_MODE_PRECISION (is_mode) - len - pos) / BITS_PER_UNIT;
7208           else
7209             offset = pos / BITS_PER_UNIT;
7210
7211           new_rtx = adjust_address_nv (inner, tmode, offset);
7212         }
7213       else if (REG_P (inner))
7214         {
7215           if (tmode != inner_mode)
7216             {
7217               /* We can't call gen_lowpart in a DEST since we
7218                  always want a SUBREG (see below) and it would sometimes
7219                  return a new hard register.  */
7220               if (pos || in_dest)
7221                 {
7222                   HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
7223
7224                   if (WORDS_BIG_ENDIAN
7225                       && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
7226                     final_word = ((GET_MODE_SIZE (inner_mode)
7227                                    - GET_MODE_SIZE (tmode))
7228                                   / UNITS_PER_WORD) - final_word;
7229
7230                   final_word *= UNITS_PER_WORD;
7231                   if (BYTES_BIG_ENDIAN &&
7232                       GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
7233                     final_word += (GET_MODE_SIZE (inner_mode)
7234                                    - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
7235
7236                   /* Avoid creating invalid subregs, for example when
7237                      simplifying (x>>32)&255.  */
7238                   if (!validate_subreg (tmode, inner_mode, inner, final_word))
7239                     return NULL_RTX;
7240
7241                   new_rtx = gen_rtx_SUBREG (tmode, inner, final_word);
7242                 }
7243               else
7244                 new_rtx = gen_lowpart (tmode, inner);
7245             }
7246           else
7247             new_rtx = inner;
7248         }
7249       else
7250         new_rtx = force_to_mode (inner, tmode,
7251                              len >= HOST_BITS_PER_WIDE_INT
7252                              ? ~(unsigned HOST_WIDE_INT) 0
7253                              : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7254                              0);
7255
7256       /* If this extraction is going into the destination of a SET,
7257          make a STRICT_LOW_PART unless we made a MEM.  */
7258
7259       if (in_dest)
7260         return (MEM_P (new_rtx) ? new_rtx
7261                 : (GET_CODE (new_rtx) != SUBREG
7262                    ? gen_rtx_CLOBBER (tmode, const0_rtx)
7263                    : gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7264
7265       if (mode == tmode)
7266         return new_rtx;
7267
7268       if (CONST_INT_P (new_rtx)
7269           || GET_CODE (new_rtx) == CONST_DOUBLE)
7270         return simplify_unary_operation (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7271                                          mode, new_rtx, tmode);
7272
7273       /* If we know that no extraneous bits are set, and that the high
7274          bit is not set, convert the extraction to the cheaper of
7275          sign and zero extension, that are equivalent in these cases.  */
7276       if (flag_expensive_optimizations
7277           && (HWI_COMPUTABLE_MODE_P (tmode)
7278               && ((nonzero_bits (new_rtx, tmode)
7279                    & ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7280                   == 0)))
7281         {
7282           rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7283           rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7284
7285           /* Prefer ZERO_EXTENSION, since it gives more information to
7286              backends.  */
7287           if (set_src_cost (temp, optimize_this_for_speed_p)
7288               <= set_src_cost (temp1, optimize_this_for_speed_p))
7289             return temp;
7290           return temp1;
7291         }
7292
7293       /* Otherwise, sign- or zero-extend unless we already are in the
7294          proper mode.  */
7295
7296       return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7297                              mode, new_rtx));
7298     }
7299
7300   /* Unless this is a COMPARE or we have a funny memory reference,
7301      don't do anything with zero-extending field extracts starting at
7302      the low-order bit since they are simple AND operations.  */
7303   if (pos_rtx == 0 && pos == 0 && ! in_dest
7304       && ! in_compare && unsignedp)
7305     return 0;
7306
7307   /* Unless INNER is not MEM, reject this if we would be spanning bytes or
7308      if the position is not a constant and the length is not 1.  In all
7309      other cases, we would only be going outside our object in cases when
7310      an original shift would have been undefined.  */
7311   if (MEM_P (inner)
7312       && ((pos_rtx == 0 && pos + len > GET_MODE_PRECISION (is_mode))
7313           || (pos_rtx != 0 && len != 1)))
7314     return 0;
7315
7316   /* Get the mode to use should INNER not be a MEM, the mode for the position,
7317      and the mode for the result.  */
7318   if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
7319     {
7320       wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
7321       pos_mode = mode_for_extraction (EP_insv, 2);
7322       extraction_mode = mode_for_extraction (EP_insv, 3);
7323     }
7324
7325   if (! in_dest && unsignedp
7326       && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
7327     {
7328       wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
7329       pos_mode = mode_for_extraction (EP_extzv, 3);
7330       extraction_mode = mode_for_extraction (EP_extzv, 0);
7331     }
7332
7333   if (! in_dest && ! unsignedp
7334       && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
7335     {
7336       wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
7337       pos_mode = mode_for_extraction (EP_extv, 3);
7338       extraction_mode = mode_for_extraction (EP_extv, 0);
7339     }
7340
7341   /* Never narrow an object, since that might not be safe.  */
7342
7343   if (mode != VOIDmode
7344       && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
7345     extraction_mode = mode;
7346
7347   if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
7348       && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7349     pos_mode = GET_MODE (pos_rtx);
7350
7351   /* If this is not from memory, the desired mode is the preferred mode
7352      for an extraction pattern's first input operand, or word_mode if there
7353      is none.  */
7354   if (!MEM_P (inner))
7355     wanted_inner_mode = wanted_inner_reg_mode;
7356   else
7357     {
7358       /* Be careful not to go beyond the extracted object and maintain the
7359          natural alignment of the memory.  */
7360       wanted_inner_mode = smallest_mode_for_size (len, MODE_INT);
7361       while (pos % GET_MODE_BITSIZE (wanted_inner_mode) + len
7362              > GET_MODE_BITSIZE (wanted_inner_mode))
7363         {
7364           wanted_inner_mode = GET_MODE_WIDER_MODE (wanted_inner_mode);
7365           gcc_assert (wanted_inner_mode != VOIDmode);
7366         }
7367
7368       /* If we have to change the mode of memory and cannot, the desired mode
7369          is EXTRACTION_MODE.  */
7370       if (inner_mode != wanted_inner_mode
7371           && (mode_dependent_address_p (XEXP (inner, 0))
7372               || MEM_VOLATILE_P (inner)
7373               || pos_rtx))
7374         wanted_inner_mode = extraction_mode;
7375     }
7376
7377   orig_pos = pos;
7378
7379   if (BITS_BIG_ENDIAN)
7380     {
7381       /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7382          BITS_BIG_ENDIAN style.  If position is constant, compute new
7383          position.  Otherwise, build subtraction.
7384          Note that POS is relative to the mode of the original argument.
7385          If it's a MEM we need to recompute POS relative to that.
7386          However, if we're extracting from (or inserting into) a register,
7387          we want to recompute POS relative to wanted_inner_mode.  */
7388       int width = (MEM_P (inner)
7389                    ? GET_MODE_BITSIZE (is_mode)
7390                    : GET_MODE_BITSIZE (wanted_inner_mode));
7391
7392       if (pos_rtx == 0)
7393         pos = width - len - pos;
7394       else
7395         pos_rtx
7396           = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
7397       /* POS may be less than 0 now, but we check for that below.
7398          Note that it can only be less than 0 if !MEM_P (inner).  */
7399     }
7400
7401   /* If INNER has a wider mode, and this is a constant extraction, try to
7402      make it smaller and adjust the byte to point to the byte containing
7403      the value.  */
7404   if (wanted_inner_mode != VOIDmode
7405       && inner_mode != wanted_inner_mode
7406       && ! pos_rtx
7407       && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
7408       && MEM_P (inner)
7409       && ! mode_dependent_address_p (XEXP (inner, 0))
7410       && ! MEM_VOLATILE_P (inner))
7411     {
7412       int offset = 0;
7413
7414       /* The computations below will be correct if the machine is big
7415          endian in both bits and bytes or little endian in bits and bytes.
7416          If it is mixed, we must adjust.  */
7417
7418       /* If bytes are big endian and we had a paradoxical SUBREG, we must
7419          adjust OFFSET to compensate.  */
7420       if (BYTES_BIG_ENDIAN
7421           && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
7422         offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
7423
7424       /* We can now move to the desired byte.  */
7425       offset += (pos / GET_MODE_BITSIZE (wanted_inner_mode))
7426                 * GET_MODE_SIZE (wanted_inner_mode);
7427       pos %= GET_MODE_BITSIZE (wanted_inner_mode);
7428
7429       if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7430           && is_mode != wanted_inner_mode)
7431         offset = (GET_MODE_SIZE (is_mode)
7432                   - GET_MODE_SIZE (wanted_inner_mode) - offset);
7433
7434       inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7435     }
7436
7437   /* If INNER is not memory, get it into the proper mode.  If we are changing
7438      its mode, POS must be a constant and smaller than the size of the new
7439      mode.  */
7440   else if (!MEM_P (inner))
7441     {
7442       /* On the LHS, don't create paradoxical subregs implicitely truncating
7443          the register unless TRULY_NOOP_TRUNCATION.  */
7444       if (in_dest
7445           && !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7446                                              wanted_inner_mode))
7447         return NULL_RTX;
7448
7449       if (GET_MODE (inner) != wanted_inner_mode
7450           && (pos_rtx != 0
7451               || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
7452         return NULL_RTX;
7453
7454       if (orig_pos < 0)
7455         return NULL_RTX;
7456
7457       inner = force_to_mode (inner, wanted_inner_mode,
7458                              pos_rtx
7459                              || len + orig_pos >= HOST_BITS_PER_WIDE_INT
7460                              ? ~(unsigned HOST_WIDE_INT) 0
7461                              : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
7462                                 << orig_pos),
7463                              0);
7464     }
7465
7466   /* Adjust mode of POS_RTX, if needed.  If we want a wider mode, we
7467      have to zero extend.  Otherwise, we can just use a SUBREG.  */
7468   if (pos_rtx != 0
7469       && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
7470     {
7471       rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
7472
7473       /* If we know that no extraneous bits are set, and that the high
7474          bit is not set, convert extraction to cheaper one - either
7475          SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7476          cases.  */
7477       if (flag_expensive_optimizations
7478           && (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7479               && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7480                    & ~(((unsigned HOST_WIDE_INT)
7481                         GET_MODE_MASK (GET_MODE (pos_rtx)))
7482                        >> 1))
7483                   == 0)))
7484         {
7485           rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
7486
7487           /* Prefer ZERO_EXTENSION, since it gives more information to
7488              backends.  */
7489           if (set_src_cost (temp1, optimize_this_for_speed_p)
7490               < set_src_cost (temp, optimize_this_for_speed_p))
7491             temp = temp1;
7492         }
7493       pos_rtx = temp;
7494     }
7495   else if (pos_rtx != 0
7496            && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
7497     pos_rtx = gen_lowpart (pos_mode, pos_rtx);
7498
7499   /* Make POS_RTX unless we already have it and it is correct.  If we don't
7500      have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7501      be a CONST_INT.  */
7502   if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7503     pos_rtx = orig_pos_rtx;
7504
7505   else if (pos_rtx == 0)
7506     pos_rtx = GEN_INT (pos);
7507
7508   /* Make the required operation.  See if we can use existing rtx.  */
7509   new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7510                          extraction_mode, inner, GEN_INT (len), pos_rtx);
7511   if (! in_dest)
7512     new_rtx = gen_lowpart (mode, new_rtx);
7513
7514   return new_rtx;
7515 }
7516 \f
7517 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
7518    with any other operations in X.  Return X without that shift if so.  */
7519
7520 static rtx
7521 extract_left_shift (rtx x, int count)
7522 {
7523   enum rtx_code code = GET_CODE (x);
7524   enum machine_mode mode = GET_MODE (x);
7525   rtx tem;
7526
7527   switch (code)
7528     {
7529     case ASHIFT:
7530       /* This is the shift itself.  If it is wide enough, we will return
7531          either the value being shifted if the shift count is equal to
7532          COUNT or a shift for the difference.  */
7533       if (CONST_INT_P (XEXP (x, 1))
7534           && INTVAL (XEXP (x, 1)) >= count)
7535         return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7536                                      INTVAL (XEXP (x, 1)) - count);
7537       break;
7538
7539     case NEG:  case NOT:
7540       if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7541         return simplify_gen_unary (code, mode, tem, mode);
7542
7543       break;
7544
7545     case PLUS:  case IOR:  case XOR:  case AND:
7546       /* If we can safely shift this constant and we find the inner shift,
7547          make a new operation.  */
7548       if (CONST_INT_P (XEXP (x, 1))
7549           && (UINTVAL (XEXP (x, 1))
7550               & ((((unsigned HOST_WIDE_INT) 1 << count)) - 1)) == 0
7551           && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
7552         return simplify_gen_binary (code, mode, tem,
7553                                     GEN_INT (INTVAL (XEXP (x, 1)) >> count));
7554
7555       break;
7556
7557     default:
7558       break;
7559     }
7560
7561   return 0;
7562 }
7563 \f
7564 /* Look at the expression rooted at X.  Look for expressions
7565    equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
7566    Form these expressions.
7567
7568    Return the new rtx, usually just X.
7569
7570    Also, for machines like the VAX that don't have logical shift insns,
7571    try to convert logical to arithmetic shift operations in cases where
7572    they are equivalent.  This undoes the canonicalizations to logical
7573    shifts done elsewhere.
7574
7575    We try, as much as possible, to re-use rtl expressions to save memory.
7576
7577    IN_CODE says what kind of expression we are processing.  Normally, it is
7578    SET.  In a memory address (inside a MEM, PLUS or minus, the latter two
7579    being kludges), it is MEM.  When processing the arguments of a comparison
7580    or a COMPARE against zero, it is COMPARE.  */
7581
7582 static rtx
7583 make_compound_operation (rtx x, enum rtx_code in_code)
7584 {
7585   enum rtx_code code = GET_CODE (x);
7586   enum machine_mode mode = GET_MODE (x);
7587   int mode_width = GET_MODE_PRECISION (mode);
7588   rtx rhs, lhs;
7589   enum rtx_code next_code;
7590   int i, j;
7591   rtx new_rtx = 0;
7592   rtx tem;
7593   const char *fmt;
7594
7595   /* Select the code to be used in recursive calls.  Once we are inside an
7596      address, we stay there.  If we have a comparison, set to COMPARE,
7597      but once inside, go back to our default of SET.  */
7598
7599   next_code = (code == MEM ? MEM
7600                : ((code == PLUS || code == MINUS)
7601                   && SCALAR_INT_MODE_P (mode)) ? MEM
7602                : ((code == COMPARE || COMPARISON_P (x))
7603                   && XEXP (x, 1) == const0_rtx) ? COMPARE
7604                : in_code == COMPARE ? SET : in_code);
7605
7606   /* Process depending on the code of this operation.  If NEW is set
7607      nonzero, it will be returned.  */
7608
7609   switch (code)
7610     {
7611     case ASHIFT:
7612       /* Convert shifts by constants into multiplications if inside
7613          an address.  */
7614       if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
7615           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
7616           && INTVAL (XEXP (x, 1)) >= 0
7617           && SCALAR_INT_MODE_P (mode))
7618         {
7619           HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
7620           HOST_WIDE_INT multval = (HOST_WIDE_INT) 1 << count;
7621
7622           new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7623           if (GET_CODE (new_rtx) == NEG)
7624             {
7625               new_rtx = XEXP (new_rtx, 0);
7626               multval = -multval;
7627             }
7628           multval = trunc_int_for_mode (multval, mode);
7629           new_rtx = gen_rtx_MULT (mode, new_rtx, GEN_INT (multval));
7630         }
7631       break;
7632
7633     case PLUS:
7634       lhs = XEXP (x, 0);
7635       rhs = XEXP (x, 1);
7636       lhs = make_compound_operation (lhs, next_code);
7637       rhs = make_compound_operation (rhs, next_code);
7638       if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG
7639           && SCALAR_INT_MODE_P (mode))
7640         {
7641           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (lhs, 0), 0),
7642                                      XEXP (lhs, 1));
7643           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7644         }
7645       else if (GET_CODE (lhs) == MULT
7646                && (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
7647         {
7648           tem = simplify_gen_binary (MULT, mode, XEXP (lhs, 0),
7649                                      simplify_gen_unary (NEG, mode,
7650                                                          XEXP (lhs, 1),
7651                                                          mode));
7652           new_rtx = simplify_gen_binary (MINUS, mode, rhs, tem);
7653         }
7654       else
7655         {
7656           SUBST (XEXP (x, 0), lhs);
7657           SUBST (XEXP (x, 1), rhs);
7658           goto maybe_swap;
7659         }
7660       x = gen_lowpart (mode, new_rtx);
7661       goto maybe_swap;
7662
7663     case MINUS:
7664       lhs = XEXP (x, 0);
7665       rhs = XEXP (x, 1);
7666       lhs = make_compound_operation (lhs, next_code);
7667       rhs = make_compound_operation (rhs, next_code);
7668       if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG
7669           && SCALAR_INT_MODE_P (mode))
7670         {
7671           tem = simplify_gen_binary (MULT, mode, XEXP (XEXP (rhs, 0), 0),
7672                                      XEXP (rhs, 1));
7673           new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7674         }
7675       else if (GET_CODE (rhs) == MULT
7676                && (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
7677         {
7678           tem = simplify_gen_binary (MULT, mode, XEXP (rhs, 0),
7679                                      simplify_gen_unary (NEG, mode,
7680                                                          XEXP (rhs, 1),
7681                                                          mode));
7682           new_rtx = simplify_gen_binary (PLUS, mode, tem, lhs);
7683         }
7684       else
7685         {
7686           SUBST (XEXP (x, 0), lhs);
7687           SUBST (XEXP (x, 1), rhs);
7688           return x;
7689         }
7690       return gen_lowpart (mode, new_rtx);
7691
7692     case AND:
7693       /* If the second operand is not a constant, we can't do anything
7694          with it.  */
7695       if (!CONST_INT_P (XEXP (x, 1)))
7696         break;
7697
7698       /* If the constant is a power of two minus one and the first operand
7699          is a logical right shift, make an extraction.  */
7700       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7701           && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7702         {
7703           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7704           new_rtx = make_extraction (mode, new_rtx, 0, XEXP (XEXP (x, 0), 1), i, 1,
7705                                  0, in_code == COMPARE);
7706         }
7707
7708       /* Same as previous, but for (subreg (lshiftrt ...)) in first op.  */
7709       else if (GET_CODE (XEXP (x, 0)) == SUBREG
7710                && subreg_lowpart_p (XEXP (x, 0))
7711                && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
7712                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7713         {
7714           new_rtx = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
7715                                          next_code);
7716           new_rtx = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new_rtx, 0,
7717                                  XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
7718                                  0, in_code == COMPARE);
7719         }
7720       /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)).  */
7721       else if ((GET_CODE (XEXP (x, 0)) == XOR
7722                 || GET_CODE (XEXP (x, 0)) == IOR)
7723                && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
7724                && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
7725                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7726         {
7727           /* Apply the distributive law, and then try to make extractions.  */
7728           new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
7729                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
7730                                              XEXP (x, 1)),
7731                                 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
7732                                              XEXP (x, 1)));
7733           new_rtx = make_compound_operation (new_rtx, in_code);
7734         }
7735
7736       /* If we are have (and (rotate X C) M) and C is larger than the number
7737          of bits in M, this is an extraction.  */
7738
7739       else if (GET_CODE (XEXP (x, 0)) == ROTATE
7740                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7741                && (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
7742                && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
7743         {
7744           new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
7745           new_rtx = make_extraction (mode, new_rtx,
7746                                  (GET_MODE_PRECISION (mode)
7747                                   - INTVAL (XEXP (XEXP (x, 0), 1))),
7748                                  NULL_RTX, i, 1, 0, in_code == COMPARE);
7749         }
7750
7751       /* On machines without logical shifts, if the operand of the AND is
7752          a logical shift and our mask turns off all the propagated sign
7753          bits, we can replace the logical shift with an arithmetic shift.  */
7754       else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7755                && !have_insn_for (LSHIFTRT, mode)
7756                && have_insn_for (ASHIFTRT, mode)
7757                && CONST_INT_P (XEXP (XEXP (x, 0), 1))
7758                && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7759                && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
7760                && mode_width <= HOST_BITS_PER_WIDE_INT)
7761         {
7762           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
7763
7764           mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
7765           if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
7766             SUBST (XEXP (x, 0),
7767                    gen_rtx_ASHIFTRT (mode,
7768                                      make_compound_operation
7769                                      (XEXP (XEXP (x, 0), 0), next_code),
7770                                      XEXP (XEXP (x, 0), 1)));
7771         }
7772
7773       /* If the constant is one less than a power of two, this might be
7774          representable by an extraction even if no shift is present.
7775          If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
7776          we are in a COMPARE.  */
7777       else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
7778         new_rtx = make_extraction (mode,
7779                                make_compound_operation (XEXP (x, 0),
7780                                                         next_code),
7781                                0, NULL_RTX, i, 1, 0, in_code == COMPARE);
7782
7783       /* If we are in a comparison and this is an AND with a power of two,
7784          convert this into the appropriate bit extract.  */
7785       else if (in_code == COMPARE
7786                && (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
7787         new_rtx = make_extraction (mode,
7788                                make_compound_operation (XEXP (x, 0),
7789                                                         next_code),
7790                                i, NULL_RTX, 1, 1, 0, 1);
7791
7792       break;
7793
7794     case LSHIFTRT:
7795       /* If the sign bit is known to be zero, replace this with an
7796          arithmetic shift.  */
7797       if (have_insn_for (ASHIFTRT, mode)
7798           && ! have_insn_for (LSHIFTRT, mode)
7799           && mode_width <= HOST_BITS_PER_WIDE_INT
7800           && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
7801         {
7802           new_rtx = gen_rtx_ASHIFTRT (mode,
7803                                   make_compound_operation (XEXP (x, 0),
7804                                                            next_code),
7805                                   XEXP (x, 1));
7806           break;
7807         }
7808
7809       /* ... fall through ...  */
7810
7811     case ASHIFTRT:
7812       lhs = XEXP (x, 0);
7813       rhs = XEXP (x, 1);
7814
7815       /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
7816          this is a SIGN_EXTRACT.  */
7817       if (CONST_INT_P (rhs)
7818           && GET_CODE (lhs) == ASHIFT
7819           && CONST_INT_P (XEXP (lhs, 1))
7820           && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
7821           && INTVAL (XEXP (lhs, 1)) >= 0
7822           && INTVAL (rhs) < mode_width)
7823         {
7824           new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
7825           new_rtx = make_extraction (mode, new_rtx,
7826                                  INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
7827                                  NULL_RTX, mode_width - INTVAL (rhs),
7828                                  code == LSHIFTRT, 0, in_code == COMPARE);
7829           break;
7830         }
7831
7832       /* See if we have operations between an ASHIFTRT and an ASHIFT.
7833          If so, try to merge the shifts into a SIGN_EXTEND.  We could
7834          also do this for some cases of SIGN_EXTRACT, but it doesn't
7835          seem worth the effort; the case checked for occurs on Alpha.  */
7836
7837       if (!OBJECT_P (lhs)
7838           && ! (GET_CODE (lhs) == SUBREG
7839                 && (OBJECT_P (SUBREG_REG (lhs))))
7840           && CONST_INT_P (rhs)
7841           && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
7842           && INTVAL (rhs) < mode_width
7843           && (new_rtx = extract_left_shift (lhs, INTVAL (rhs))) != 0)
7844         new_rtx = make_extraction (mode, make_compound_operation (new_rtx, next_code),
7845                                0, NULL_RTX, mode_width - INTVAL (rhs),
7846                                code == LSHIFTRT, 0, in_code == COMPARE);
7847
7848       break;
7849
7850     case SUBREG:
7851       /* Call ourselves recursively on the inner expression.  If we are
7852          narrowing the object and it has a different RTL code from
7853          what it originally did, do this SUBREG as a force_to_mode.  */
7854       {
7855         rtx inner = SUBREG_REG (x), simplified;
7856
7857         tem = make_compound_operation (inner, in_code);
7858
7859         simplified
7860           = simplify_subreg (mode, tem, GET_MODE (inner), SUBREG_BYTE (x));
7861         if (simplified)
7862           tem = simplified;
7863
7864         if (GET_CODE (tem) != GET_CODE (inner)
7865             && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (inner))
7866             && subreg_lowpart_p (x))
7867           {
7868             rtx newer
7869               = force_to_mode (tem, mode, ~(unsigned HOST_WIDE_INT) 0, 0);
7870
7871             /* If we have something other than a SUBREG, we might have
7872                done an expansion, so rerun ourselves.  */
7873             if (GET_CODE (newer) != SUBREG)
7874               newer = make_compound_operation (newer, in_code);
7875
7876             /* force_to_mode can expand compounds.  If it just re-expanded the
7877                compound, use gen_lowpart to convert to the desired mode.  */
7878             if (rtx_equal_p (newer, x)
7879                 /* Likewise if it re-expanded the compound only partially.
7880                    This happens for SUBREG of ZERO_EXTRACT if they extract
7881                    the same number of bits.  */
7882                 || (GET_CODE (newer) == SUBREG
7883                     && (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
7884                         || GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
7885                     && GET_CODE (inner) == AND
7886                     && rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
7887               return gen_lowpart (GET_MODE (x), tem);
7888
7889             return newer;
7890           }
7891
7892         if (simplified)
7893           return tem;
7894       }
7895       break;
7896
7897     default:
7898       break;
7899     }
7900
7901   if (new_rtx)
7902     {
7903       x = gen_lowpart (mode, new_rtx);
7904       code = GET_CODE (x);
7905     }
7906
7907   /* Now recursively process each operand of this operation.  We need to
7908      handle ZERO_EXTEND specially so that we don't lose track of the
7909      inner mode.  */
7910   if (GET_CODE (x) == ZERO_EXTEND)
7911     {
7912       new_rtx = make_compound_operation (XEXP (x, 0), next_code);
7913       tem = simplify_const_unary_operation (ZERO_EXTEND, GET_MODE (x),
7914                                             new_rtx, GET_MODE (XEXP (x, 0)));
7915       if (tem)
7916         return tem;
7917       SUBST (XEXP (x, 0), new_rtx);
7918       return x;
7919     }
7920
7921   fmt = GET_RTX_FORMAT (code);
7922   for (i = 0; i < GET_RTX_LENGTH (code); i++)
7923     if (fmt[i] == 'e')
7924       {
7925         new_rtx = make_compound_operation (XEXP (x, i), next_code);
7926         SUBST (XEXP (x, i), new_rtx);
7927       }
7928     else if (fmt[i] == 'E')
7929       for (j = 0; j < XVECLEN (x, i); j++)
7930         {
7931           new_rtx = make_compound_operation (XVECEXP (x, i, j), next_code);
7932           SUBST (XVECEXP (x, i, j), new_rtx);
7933         }
7934
7935  maybe_swap:
7936   /* If this is a commutative operation, the changes to the operands
7937      may have made it noncanonical.  */
7938   if (COMMUTATIVE_ARITH_P (x)
7939       && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
7940     {
7941       tem = XEXP (x, 0);
7942       SUBST (XEXP (x, 0), XEXP (x, 1));
7943       SUBST (XEXP (x, 1), tem);
7944     }
7945
7946   return x;
7947 }
7948 \f
7949 /* Given M see if it is a value that would select a field of bits
7950    within an item, but not the entire word.  Return -1 if not.
7951    Otherwise, return the starting position of the field, where 0 is the
7952    low-order bit.
7953
7954    *PLEN is set to the length of the field.  */
7955
7956 static int
7957 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
7958 {
7959   /* Get the bit number of the first 1 bit from the right, -1 if none.  */
7960   int pos = m ? ctz_hwi (m) : -1;
7961   int len = 0;
7962
7963   if (pos >= 0)
7964     /* Now shift off the low-order zero bits and see if we have a
7965        power of two minus 1.  */
7966     len = exact_log2 ((m >> pos) + 1);
7967
7968   if (len <= 0)
7969     pos = -1;
7970
7971   *plen = len;
7972   return pos;
7973 }
7974 \f
7975 /* If X refers to a register that equals REG in value, replace these
7976    references with REG.  */
7977 static rtx
7978 canon_reg_for_combine (rtx x, rtx reg)
7979 {
7980   rtx op0, op1, op2;
7981   const char *fmt;
7982   int i;
7983   bool copied;
7984
7985   enum rtx_code code = GET_CODE (x);
7986   switch (GET_RTX_CLASS (code))
7987     {
7988     case RTX_UNARY:
7989       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7990       if (op0 != XEXP (x, 0))
7991         return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
7992                                    GET_MODE (reg));
7993       break;
7994
7995     case RTX_BIN_ARITH:
7996     case RTX_COMM_ARITH:
7997       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
7998       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
7999       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8000         return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
8001       break;
8002
8003     case RTX_COMPARE:
8004     case RTX_COMM_COMPARE:
8005       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8006       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8007       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8008         return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
8009                                         GET_MODE (op0), op0, op1);
8010       break;
8011
8012     case RTX_TERNARY:
8013     case RTX_BITFIELD_OPS:
8014       op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8015       op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8016       op2 = canon_reg_for_combine (XEXP (x, 2), reg);
8017       if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
8018         return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
8019                                      GET_MODE (op0), op0, op1, op2);
8020
8021     case RTX_OBJ:
8022       if (REG_P (x))
8023         {
8024           if (rtx_equal_p (get_last_value (reg), x)
8025               || rtx_equal_p (reg, get_last_value (x)))
8026             return reg;
8027           else
8028             break;
8029         }
8030
8031       /* fall through */
8032
8033     default:
8034       fmt = GET_RTX_FORMAT (code);
8035       copied = false;
8036       for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8037         if (fmt[i] == 'e')
8038           {
8039             rtx op = canon_reg_for_combine (XEXP (x, i), reg);
8040             if (op != XEXP (x, i))
8041               {
8042                 if (!copied)
8043                   {
8044                     copied = true;
8045                     x = copy_rtx (x);
8046                   }
8047                 XEXP (x, i) = op;
8048               }
8049           }
8050         else if (fmt[i] == 'E')
8051           {
8052             int j;
8053             for (j = 0; j < XVECLEN (x, i); j++)
8054               {
8055                 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
8056                 if (op != XVECEXP (x, i, j))
8057                   {
8058                     if (!copied)
8059                       {
8060                         copied = true;
8061                         x = copy_rtx (x);
8062                       }
8063                     XVECEXP (x, i, j) = op;
8064                   }
8065               }
8066           }
8067
8068       break;
8069     }
8070
8071   return x;
8072 }
8073
8074 /* Return X converted to MODE.  If the value is already truncated to
8075    MODE we can just return a subreg even though in the general case we
8076    would need an explicit truncation.  */
8077
8078 static rtx
8079 gen_lowpart_or_truncate (enum machine_mode mode, rtx x)
8080 {
8081   if (!CONST_INT_P (x)
8082       && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (x))
8083       && !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
8084       && !(REG_P (x) && reg_truncated_to_mode (mode, x)))
8085     {
8086       /* Bit-cast X into an integer mode.  */
8087       if (!SCALAR_INT_MODE_P (GET_MODE (x)))
8088         x = gen_lowpart (int_mode_for_mode (GET_MODE (x)), x);
8089       x = simplify_gen_unary (TRUNCATE, int_mode_for_mode (mode),
8090                               x, GET_MODE (x));
8091     }
8092
8093   return gen_lowpart (mode, x);
8094 }
8095
8096 /* See if X can be simplified knowing that we will only refer to it in
8097    MODE and will only refer to those bits that are nonzero in MASK.
8098    If other bits are being computed or if masking operations are done
8099    that select a superset of the bits in MASK, they can sometimes be
8100    ignored.
8101
8102    Return a possibly simplified expression, but always convert X to
8103    MODE.  If X is a CONST_INT, AND the CONST_INT with MASK.
8104
8105    If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
8106    are all off in X.  This is used when X will be complemented, by either
8107    NOT, NEG, or XOR.  */
8108
8109 static rtx
8110 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
8111                int just_select)
8112 {
8113   enum rtx_code code = GET_CODE (x);
8114   int next_select = just_select || code == XOR || code == NOT || code == NEG;
8115   enum machine_mode op_mode;
8116   unsigned HOST_WIDE_INT fuller_mask, nonzero;
8117   rtx op0, op1, temp;
8118
8119   /* If this is a CALL or ASM_OPERANDS, don't do anything.  Some of the
8120      code below will do the wrong thing since the mode of such an
8121      expression is VOIDmode.
8122
8123      Also do nothing if X is a CLOBBER; this can happen if X was
8124      the return value from a call to gen_lowpart.  */
8125   if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8126     return x;
8127
8128   /* We want to perform the operation is its present mode unless we know
8129      that the operation is valid in MODE, in which case we do the operation
8130      in MODE.  */
8131   op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8132               && have_insn_for (code, mode))
8133              ? mode : GET_MODE (x));
8134
8135   /* It is not valid to do a right-shift in a narrower mode
8136      than the one it came in with.  */
8137   if ((code == LSHIFTRT || code == ASHIFTRT)
8138       && GET_MODE_PRECISION (mode) < GET_MODE_PRECISION (GET_MODE (x)))
8139     op_mode = GET_MODE (x);
8140
8141   /* Truncate MASK to fit OP_MODE.  */
8142   if (op_mode)
8143     mask &= GET_MODE_MASK (op_mode);
8144
8145   /* When we have an arithmetic operation, or a shift whose count we
8146      do not know, we need to assume that all bits up to the highest-order
8147      bit in MASK will be needed.  This is how we form such a mask.  */
8148   if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
8149     fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
8150   else
8151     fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
8152                    - 1);
8153
8154   /* Determine what bits of X are guaranteed to be (non)zero.  */
8155   nonzero = nonzero_bits (x, mode);
8156
8157   /* If none of the bits in X are needed, return a zero.  */
8158   if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8159     x = const0_rtx;
8160
8161   /* If X is a CONST_INT, return a new one.  Do this here since the
8162      test below will fail.  */
8163   if (CONST_INT_P (x))
8164     {
8165       if (SCALAR_INT_MODE_P (mode))
8166         return gen_int_mode (INTVAL (x) & mask, mode);
8167       else
8168         {
8169           x = GEN_INT (INTVAL (x) & mask);
8170           return gen_lowpart_common (mode, x);
8171         }
8172     }
8173
8174   /* If X is narrower than MODE and we want all the bits in X's mode, just
8175      get X in the proper mode.  */
8176   if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
8177       && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8178     return gen_lowpart (mode, x);
8179
8180   /* We can ignore the effect of a SUBREG if it narrows the mode or
8181      if the constant masks to zero all the bits the mode doesn't have.  */
8182   if (GET_CODE (x) == SUBREG
8183       && subreg_lowpart_p (x)
8184       && ((GET_MODE_SIZE (GET_MODE (x))
8185            < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
8186           || (0 == (mask
8187                     & GET_MODE_MASK (GET_MODE (x))
8188                     & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
8189     return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
8190
8191   /* The arithmetic simplifications here only work for scalar integer modes.  */
8192   if (!SCALAR_INT_MODE_P (mode) || !SCALAR_INT_MODE_P (GET_MODE (x)))
8193     return gen_lowpart_or_truncate (mode, x);
8194
8195   switch (code)
8196     {
8197     case CLOBBER:
8198       /* If X is a (clobber (const_int)), return it since we know we are
8199          generating something that won't match.  */
8200       return x;
8201
8202     case SIGN_EXTEND:
8203     case ZERO_EXTEND:
8204     case ZERO_EXTRACT:
8205     case SIGN_EXTRACT:
8206       x = expand_compound_operation (x);
8207       if (GET_CODE (x) != code)
8208         return force_to_mode (x, mode, mask, next_select);
8209       break;
8210
8211     case TRUNCATE:
8212       /* Similarly for a truncate.  */
8213       return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8214
8215     case AND:
8216       /* If this is an AND with a constant, convert it into an AND
8217          whose constant is the AND of that constant with MASK.  If it
8218          remains an AND of MASK, delete it since it is redundant.  */
8219
8220       if (CONST_INT_P (XEXP (x, 1)))
8221         {
8222           x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8223                                       mask & INTVAL (XEXP (x, 1)));
8224
8225           /* If X is still an AND, see if it is an AND with a mask that
8226              is just some low-order bits.  If so, and it is MASK, we don't
8227              need it.  */
8228
8229           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8230               && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
8231                   == mask))
8232             x = XEXP (x, 0);
8233
8234           /* If it remains an AND, try making another AND with the bits
8235              in the mode mask that aren't in MASK turned on.  If the
8236              constant in the AND is wide enough, this might make a
8237              cheaper constant.  */
8238
8239           if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8240               && GET_MODE_MASK (GET_MODE (x)) != mask
8241               && HWI_COMPUTABLE_MODE_P (GET_MODE (x)))
8242             {
8243               unsigned HOST_WIDE_INT cval
8244                 = UINTVAL (XEXP (x, 1))
8245                   | (GET_MODE_MASK (GET_MODE (x)) & ~mask);
8246               int width = GET_MODE_PRECISION (GET_MODE (x));
8247               rtx y;
8248
8249               /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
8250                  number, sign extend it.  */
8251               if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8252                   && (cval & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8253                 cval |= (unsigned HOST_WIDE_INT) -1 << width;
8254
8255               y = simplify_gen_binary (AND, GET_MODE (x),
8256                                        XEXP (x, 0), GEN_INT (cval));
8257               if (set_src_cost (y, optimize_this_for_speed_p)
8258                   < set_src_cost (x, optimize_this_for_speed_p))
8259                 x = y;
8260             }
8261
8262           break;
8263         }
8264
8265       goto binop;
8266
8267     case PLUS:
8268       /* In (and (plus FOO C1) M), if M is a mask that just turns off
8269          low-order bits (as in an alignment operation) and FOO is already
8270          aligned to that boundary, mask C1 to that boundary as well.
8271          This may eliminate that PLUS and, later, the AND.  */
8272
8273       {
8274         unsigned int width = GET_MODE_PRECISION (mode);
8275         unsigned HOST_WIDE_INT smask = mask;
8276
8277         /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8278            number, sign extend it.  */
8279
8280         if (width < HOST_BITS_PER_WIDE_INT
8281             && (smask & ((unsigned HOST_WIDE_INT) 1 << (width - 1))) != 0)
8282           smask |= (unsigned HOST_WIDE_INT) (-1) << width;
8283
8284         if (CONST_INT_P (XEXP (x, 1))
8285             && exact_log2 (- smask) >= 0
8286             && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8287             && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8288           return force_to_mode (plus_constant (XEXP (x, 0),
8289                                                (INTVAL (XEXP (x, 1)) & smask)),
8290                                 mode, smask, next_select);
8291       }
8292
8293       /* ... fall through ...  */
8294
8295     case MULT:
8296       /* For PLUS, MINUS and MULT, we need any bits less significant than the
8297          most significant bit in MASK since carries from those bits will
8298          affect the bits we are interested in.  */
8299       mask = fuller_mask;
8300       goto binop;
8301
8302     case MINUS:
8303       /* If X is (minus C Y) where C's least set bit is larger than any bit
8304          in the mask, then we may replace with (neg Y).  */
8305       if (CONST_INT_P (XEXP (x, 0))
8306           && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
8307                                         & -INTVAL (XEXP (x, 0))))
8308               > mask))
8309         {
8310           x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
8311                                   GET_MODE (x));
8312           return force_to_mode (x, mode, mask, next_select);
8313         }
8314
8315       /* Similarly, if C contains every bit in the fuller_mask, then we may
8316          replace with (not Y).  */
8317       if (CONST_INT_P (XEXP (x, 0))
8318           && ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8319         {
8320           x = simplify_gen_unary (NOT, GET_MODE (x),
8321                                   XEXP (x, 1), GET_MODE (x));
8322           return force_to_mode (x, mode, mask, next_select);
8323         }
8324
8325       mask = fuller_mask;
8326       goto binop;
8327
8328     case IOR:
8329     case XOR:
8330       /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8331          LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8332          operation which may be a bitfield extraction.  Ensure that the
8333          constant we form is not wider than the mode of X.  */
8334
8335       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8336           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8337           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8338           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8339           && CONST_INT_P (XEXP (x, 1))
8340           && ((INTVAL (XEXP (XEXP (x, 0), 1))
8341                + floor_log2 (INTVAL (XEXP (x, 1))))
8342               < GET_MODE_PRECISION (GET_MODE (x)))
8343           && (UINTVAL (XEXP (x, 1))
8344               & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
8345         {
8346           temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
8347                           << INTVAL (XEXP (XEXP (x, 0), 1)));
8348           temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
8349                                       XEXP (XEXP (x, 0), 0), temp);
8350           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
8351                                    XEXP (XEXP (x, 0), 1));
8352           return force_to_mode (x, mode, mask, next_select);
8353         }
8354
8355     binop:
8356       /* For most binary operations, just propagate into the operation and
8357          change the mode if we have an operation of that mode.  */
8358
8359       op0 = force_to_mode (XEXP (x, 0), mode, mask, next_select);
8360       op1 = force_to_mode (XEXP (x, 1), mode, mask, next_select);
8361
8362       /* If we ended up truncating both operands, truncate the result of the
8363          operation instead.  */
8364       if (GET_CODE (op0) == TRUNCATE
8365           && GET_CODE (op1) == TRUNCATE)
8366         {
8367           op0 = XEXP (op0, 0);
8368           op1 = XEXP (op1, 0);
8369         }
8370
8371       op0 = gen_lowpart_or_truncate (op_mode, op0);
8372       op1 = gen_lowpart_or_truncate (op_mode, op1);
8373
8374       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8375         x = simplify_gen_binary (code, op_mode, op0, op1);
8376       break;
8377
8378     case ASHIFT:
8379       /* For left shifts, do the same, but just for the first operand.
8380          However, we cannot do anything with shifts where we cannot
8381          guarantee that the counts are smaller than the size of the mode
8382          because such a count will have a different meaning in a
8383          wider mode.  */
8384
8385       if (! (CONST_INT_P (XEXP (x, 1))
8386              && INTVAL (XEXP (x, 1)) >= 0
8387              && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
8388           && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8389                 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8390                     < (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
8391         break;
8392
8393       /* If the shift count is a constant and we can do arithmetic in
8394          the mode of the shift, refine which bits we need.  Otherwise, use the
8395          conservative form of the mask.  */
8396       if (CONST_INT_P (XEXP (x, 1))
8397           && INTVAL (XEXP (x, 1)) >= 0
8398           && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (op_mode)
8399           && HWI_COMPUTABLE_MODE_P (op_mode))
8400         mask >>= INTVAL (XEXP (x, 1));
8401       else
8402         mask = fuller_mask;
8403
8404       op0 = gen_lowpart_or_truncate (op_mode,
8405                                      force_to_mode (XEXP (x, 0), op_mode,
8406                                                     mask, next_select));
8407
8408       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8409         x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
8410       break;
8411
8412     case LSHIFTRT:
8413       /* Here we can only do something if the shift count is a constant,
8414          this shift constant is valid for the host, and we can do arithmetic
8415          in OP_MODE.  */
8416
8417       if (CONST_INT_P (XEXP (x, 1))
8418           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8419           && HWI_COMPUTABLE_MODE_P (op_mode))
8420         {
8421           rtx inner = XEXP (x, 0);
8422           unsigned HOST_WIDE_INT inner_mask;
8423
8424           /* Select the mask of the bits we need for the shift operand.  */
8425           inner_mask = mask << INTVAL (XEXP (x, 1));
8426
8427           /* We can only change the mode of the shift if we can do arithmetic
8428              in the mode of the shift and INNER_MASK is no wider than the
8429              width of X's mode.  */
8430           if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
8431             op_mode = GET_MODE (x);
8432
8433           inner = force_to_mode (inner, op_mode, inner_mask, next_select);
8434
8435           if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
8436             x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
8437         }
8438
8439       /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
8440          shift and AND produces only copies of the sign bit (C2 is one less
8441          than a power of two), we can do this with just a shift.  */
8442
8443       if (GET_CODE (x) == LSHIFTRT
8444           && CONST_INT_P (XEXP (x, 1))
8445           /* The shift puts one of the sign bit copies in the least significant
8446              bit.  */
8447           && ((INTVAL (XEXP (x, 1))
8448                + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
8449               >= GET_MODE_PRECISION (GET_MODE (x)))
8450           && exact_log2 (mask + 1) >= 0
8451           /* Number of bits left after the shift must be more than the mask
8452              needs.  */
8453           && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
8454               <= GET_MODE_PRECISION (GET_MODE (x)))
8455           /* Must be more sign bit copies than the mask needs.  */
8456           && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
8457               >= exact_log2 (mask + 1)))
8458         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8459                                  GEN_INT (GET_MODE_PRECISION (GET_MODE (x))
8460                                           - exact_log2 (mask + 1)));
8461
8462       goto shiftrt;
8463
8464     case ASHIFTRT:
8465       /* If we are just looking for the sign bit, we don't need this shift at
8466          all, even if it has a variable count.  */
8467       if (val_signbit_p (GET_MODE (x), mask))
8468         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8469
8470       /* If this is a shift by a constant, get a mask that contains those bits
8471          that are not copies of the sign bit.  We then have two cases:  If
8472          MASK only includes those bits, this can be a logical shift, which may
8473          allow simplifications.  If MASK is a single-bit field not within
8474          those bits, we are requesting a copy of the sign bit and hence can
8475          shift the sign bit to the appropriate location.  */
8476
8477       if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
8478           && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
8479         {
8480           int i;
8481
8482           /* If the considered data is wider than HOST_WIDE_INT, we can't
8483              represent a mask for all its bits in a single scalar.
8484              But we only care about the lower bits, so calculate these.  */
8485
8486           if (GET_MODE_PRECISION (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
8487             {
8488               nonzero = ~(unsigned HOST_WIDE_INT) 0;
8489
8490               /* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8491                  is the number of bits a full-width mask would have set.
8492                  We need only shift if these are fewer than nonzero can
8493                  hold.  If not, we must keep all bits set in nonzero.  */
8494
8495               if (GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
8496                   < HOST_BITS_PER_WIDE_INT)
8497                 nonzero >>= INTVAL (XEXP (x, 1))
8498                             + HOST_BITS_PER_WIDE_INT
8499                             - GET_MODE_PRECISION (GET_MODE (x)) ;
8500             }
8501           else
8502             {
8503               nonzero = GET_MODE_MASK (GET_MODE (x));
8504               nonzero >>= INTVAL (XEXP (x, 1));
8505             }
8506
8507           if ((mask & ~nonzero) == 0)
8508             {
8509               x = simplify_shift_const (NULL_RTX, LSHIFTRT, GET_MODE (x),
8510                                         XEXP (x, 0), INTVAL (XEXP (x, 1)));
8511               if (GET_CODE (x) != ASHIFTRT)
8512                 return force_to_mode (x, mode, mask, next_select);
8513             }
8514
8515           else if ((i = exact_log2 (mask)) >= 0)
8516             {
8517               x = simplify_shift_const
8518                   (NULL_RTX, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
8519                    GET_MODE_PRECISION (GET_MODE (x)) - 1 - i);
8520
8521               if (GET_CODE (x) != ASHIFTRT)
8522                 return force_to_mode (x, mode, mask, next_select);
8523             }
8524         }
8525
8526       /* If MASK is 1, convert this to an LSHIFTRT.  This can be done
8527          even if the shift count isn't a constant.  */
8528       if (mask == 1)
8529         x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8530                                  XEXP (x, 0), XEXP (x, 1));
8531
8532     shiftrt:
8533
8534       /* If this is a zero- or sign-extension operation that just affects bits
8535          we don't care about, remove it.  Be sure the call above returned
8536          something that is still a shift.  */
8537
8538       if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
8539           && CONST_INT_P (XEXP (x, 1))
8540           && INTVAL (XEXP (x, 1)) >= 0
8541           && (INTVAL (XEXP (x, 1))
8542               <= GET_MODE_PRECISION (GET_MODE (x)) - (floor_log2 (mask) + 1))
8543           && GET_CODE (XEXP (x, 0)) == ASHIFT
8544           && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
8545         return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
8546                               next_select);
8547
8548       break;
8549
8550     case ROTATE:
8551     case ROTATERT:
8552       /* If the shift count is constant and we can do computations
8553          in the mode of X, compute where the bits we care about are.
8554          Otherwise, we can't do anything.  Don't change the mode of
8555          the shift or propagate MODE into the shift, though.  */
8556       if (CONST_INT_P (XEXP (x, 1))
8557           && INTVAL (XEXP (x, 1)) >= 0)
8558         {
8559           temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
8560                                             GET_MODE (x), GEN_INT (mask),
8561                                             XEXP (x, 1));
8562           if (temp && CONST_INT_P (temp))
8563             SUBST (XEXP (x, 0),
8564                    force_to_mode (XEXP (x, 0), GET_MODE (x),
8565                                   INTVAL (temp), next_select));
8566         }
8567       break;
8568
8569     case NEG:
8570       /* If we just want the low-order bit, the NEG isn't needed since it
8571          won't change the low-order bit.  */
8572       if (mask == 1)
8573         return force_to_mode (XEXP (x, 0), mode, mask, just_select);
8574
8575       /* We need any bits less significant than the most significant bit in
8576          MASK since carries from those bits will affect the bits we are
8577          interested in.  */
8578       mask = fuller_mask;
8579       goto unop;
8580
8581     case NOT:
8582       /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
8583          same as the XOR case above.  Ensure that the constant we form is not
8584          wider than the mode of X.  */
8585
8586       if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8587           && CONST_INT_P (XEXP (XEXP (x, 0), 1))
8588           && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8589           && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
8590               < GET_MODE_PRECISION (GET_MODE (x)))
8591           && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
8592         {
8593           temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
8594                                GET_MODE (x));
8595           temp = simplify_gen_binary (XOR, GET_MODE (x),
8596                                       XEXP (XEXP (x, 0), 0), temp);
8597           x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
8598                                    temp, XEXP (XEXP (x, 0), 1));
8599
8600           return force_to_mode (x, mode, mask, next_select);
8601         }
8602
8603       /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
8604          use the full mask inside the NOT.  */
8605       mask = fuller_mask;
8606
8607     unop:
8608       op0 = gen_lowpart_or_truncate (op_mode,
8609                                      force_to_mode (XEXP (x, 0), mode, mask,
8610                                                     next_select));
8611       if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
8612         x = simplify_gen_unary (code, op_mode, op0, op_mode);
8613       break;
8614
8615     case NE:
8616       /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
8617          in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
8618          which is equal to STORE_FLAG_VALUE.  */
8619       if ((mask & ~STORE_FLAG_VALUE) == 0
8620           && XEXP (x, 1) == const0_rtx
8621           && GET_MODE (XEXP (x, 0)) == mode
8622           && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
8623           && (nonzero_bits (XEXP (x, 0), mode)
8624               == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
8625         return force_to_mode (XEXP (x, 0), mode, mask, next_select);
8626
8627       break;
8628
8629     case IF_THEN_ELSE:
8630       /* We have no way of knowing if the IF_THEN_ELSE can itself be
8631          written in a narrower mode.  We play it safe and do not do so.  */
8632
8633       SUBST (XEXP (x, 1),
8634              gen_lowpart_or_truncate (GET_MODE (x),
8635                                       force_to_mode (XEXP (x, 1), mode,
8636                                                      mask, next_select)));
8637       SUBST (XEXP (x, 2),
8638              gen_lowpart_or_truncate (GET_MODE (x),
8639                                       force_to_mode (XEXP (x, 2), mode,
8640                                                      mask, next_select)));
8641       break;
8642
8643     default:
8644       break;
8645     }
8646
8647   /* Ensure we return a value of the proper mode.  */
8648   return gen_lowpart_or_truncate (mode, x);
8649 }
8650 \f
8651 /* Return nonzero if X is an expression that has one of two values depending on
8652    whether some other value is zero or nonzero.  In that case, we return the
8653    value that is being tested, *PTRUE is set to the value if the rtx being
8654    returned has a nonzero value, and *PFALSE is set to the other alternative.
8655
8656    If we return zero, we set *PTRUE and *PFALSE to X.  */
8657
8658 static rtx
8659 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
8660 {
8661   enum machine_mode mode = GET_MODE (x);
8662   enum rtx_code code = GET_CODE (x);
8663   rtx cond0, cond1, true0, true1, false0, false1;
8664   unsigned HOST_WIDE_INT nz;
8665
8666   /* If we are comparing a value against zero, we are done.  */
8667   if ((code == NE || code == EQ)
8668       && XEXP (x, 1) == const0_rtx)
8669     {
8670       *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
8671       *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
8672       return XEXP (x, 0);
8673     }
8674
8675   /* If this is a unary operation whose operand has one of two values, apply
8676      our opcode to compute those values.  */
8677   else if (UNARY_P (x)
8678            && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
8679     {
8680       *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
8681       *pfalse = simplify_gen_unary (code, mode, false0,
8682                                     GET_MODE (XEXP (x, 0)));
8683       return cond0;
8684     }
8685
8686   /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
8687      make can't possibly match and would suppress other optimizations.  */
8688   else if (code == COMPARE)
8689     ;
8690
8691   /* If this is a binary operation, see if either side has only one of two
8692      values.  If either one does or if both do and they are conditional on
8693      the same value, compute the new true and false values.  */
8694   else if (BINARY_P (x))
8695     {
8696       cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
8697       cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
8698
8699       if ((cond0 != 0 || cond1 != 0)
8700           && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
8701         {
8702           /* If if_then_else_cond returned zero, then true/false are the
8703              same rtl.  We must copy one of them to prevent invalid rtl
8704              sharing.  */
8705           if (cond0 == 0)
8706             true0 = copy_rtx (true0);
8707           else if (cond1 == 0)
8708             true1 = copy_rtx (true1);
8709
8710           if (COMPARISON_P (x))
8711             {
8712               *ptrue = simplify_gen_relational (code, mode, VOIDmode,
8713                                                 true0, true1);
8714               *pfalse = simplify_gen_relational (code, mode, VOIDmode,
8715                                                  false0, false1);
8716              }
8717           else
8718             {
8719               *ptrue = simplify_gen_binary (code, mode, true0, true1);
8720               *pfalse = simplify_gen_binary (code, mode, false0, false1);
8721             }
8722
8723           return cond0 ? cond0 : cond1;
8724         }
8725
8726       /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
8727          operands is zero when the other is nonzero, and vice-versa,
8728          and STORE_FLAG_VALUE is 1 or -1.  */
8729
8730       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8731           && (code == PLUS || code == IOR || code == XOR || code == MINUS
8732               || code == UMAX)
8733           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8734         {
8735           rtx op0 = XEXP (XEXP (x, 0), 1);
8736           rtx op1 = XEXP (XEXP (x, 1), 1);
8737
8738           cond0 = XEXP (XEXP (x, 0), 0);
8739           cond1 = XEXP (XEXP (x, 1), 0);
8740
8741           if (COMPARISON_P (cond0)
8742               && COMPARISON_P (cond1)
8743               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8744                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8745                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8746                   || ((swap_condition (GET_CODE (cond0))
8747                        == reversed_comparison_code (cond1, NULL))
8748                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8749                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8750               && ! side_effects_p (x))
8751             {
8752               *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
8753               *pfalse = simplify_gen_binary (MULT, mode,
8754                                              (code == MINUS
8755                                               ? simplify_gen_unary (NEG, mode,
8756                                                                     op1, mode)
8757                                               : op1),
8758                                               const_true_rtx);
8759               return cond0;
8760             }
8761         }
8762
8763       /* Similarly for MULT, AND and UMIN, except that for these the result
8764          is always zero.  */
8765       if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8766           && (code == MULT || code == AND || code == UMIN)
8767           && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
8768         {
8769           cond0 = XEXP (XEXP (x, 0), 0);
8770           cond1 = XEXP (XEXP (x, 1), 0);
8771
8772           if (COMPARISON_P (cond0)
8773               && COMPARISON_P (cond1)
8774               && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
8775                    && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
8776                    && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
8777                   || ((swap_condition (GET_CODE (cond0))
8778                        == reversed_comparison_code (cond1, NULL))
8779                       && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
8780                       && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
8781               && ! side_effects_p (x))
8782             {
8783               *ptrue = *pfalse = const0_rtx;
8784               return cond0;
8785             }
8786         }
8787     }
8788
8789   else if (code == IF_THEN_ELSE)
8790     {
8791       /* If we have IF_THEN_ELSE already, extract the condition and
8792          canonicalize it if it is NE or EQ.  */
8793       cond0 = XEXP (x, 0);
8794       *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
8795       if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
8796         return XEXP (cond0, 0);
8797       else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
8798         {
8799           *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
8800           return XEXP (cond0, 0);
8801         }
8802       else
8803         return cond0;
8804     }
8805
8806   /* If X is a SUBREG, we can narrow both the true and false values
8807      if the inner expression, if there is a condition.  */
8808   else if (code == SUBREG
8809            && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
8810                                                &true0, &false0)))
8811     {
8812       true0 = simplify_gen_subreg (mode, true0,
8813                                    GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8814       false0 = simplify_gen_subreg (mode, false0,
8815                                     GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
8816       if (true0 && false0)
8817         {
8818           *ptrue = true0;
8819           *pfalse = false0;
8820           return cond0;
8821         }
8822     }
8823
8824   /* If X is a constant, this isn't special and will cause confusions
8825      if we treat it as such.  Likewise if it is equivalent to a constant.  */
8826   else if (CONSTANT_P (x)
8827            || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
8828     ;
8829
8830   /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
8831      will be least confusing to the rest of the compiler.  */
8832   else if (mode == BImode)
8833     {
8834       *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
8835       return x;
8836     }
8837
8838   /* If X is known to be either 0 or -1, those are the true and
8839      false values when testing X.  */
8840   else if (x == constm1_rtx || x == const0_rtx
8841            || (mode != VOIDmode
8842                && num_sign_bit_copies (x, mode) == GET_MODE_PRECISION (mode)))
8843     {
8844       *ptrue = constm1_rtx, *pfalse = const0_rtx;
8845       return x;
8846     }
8847
8848   /* Likewise for 0 or a single bit.  */
8849   else if (HWI_COMPUTABLE_MODE_P (mode)
8850            && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
8851     {
8852       *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
8853       return x;
8854     }
8855
8856   /* Otherwise fail; show no condition with true and false values the same.  */
8857   *ptrue = *pfalse = x;
8858   return 0;
8859 }
8860 \f
8861 /* Return the value of expression X given the fact that condition COND
8862    is known to be true when applied to REG as its first operand and VAL
8863    as its second.  X is known to not be shared and so can be modified in
8864    place.
8865
8866    We only handle the simplest cases, and specifically those cases that
8867    arise with IF_THEN_ELSE expressions.  */
8868
8869 static rtx
8870 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
8871 {
8872   enum rtx_code code = GET_CODE (x);
8873   rtx temp;
8874   const char *fmt;
8875   int i, j;
8876
8877   if (side_effects_p (x))
8878     return x;
8879
8880   /* If either operand of the condition is a floating point value,
8881      then we have to avoid collapsing an EQ comparison.  */
8882   if (cond == EQ
8883       && rtx_equal_p (x, reg)
8884       && ! FLOAT_MODE_P (GET_MODE (x))
8885       && ! FLOAT_MODE_P (GET_MODE (val)))
8886     return val;
8887
8888   if (cond == UNEQ && rtx_equal_p (x, reg))
8889     return val;
8890
8891   /* If X is (abs REG) and we know something about REG's relationship
8892      with zero, we may be able to simplify this.  */
8893
8894   if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
8895     switch (cond)
8896       {
8897       case GE:  case GT:  case EQ:
8898         return XEXP (x, 0);
8899       case LT:  case LE:
8900         return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
8901                                    XEXP (x, 0),
8902                                    GET_MODE (XEXP (x, 0)));
8903       default:
8904         break;
8905       }
8906
8907   /* The only other cases we handle are MIN, MAX, and comparisons if the
8908      operands are the same as REG and VAL.  */
8909
8910   else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
8911     {
8912       if (rtx_equal_p (XEXP (x, 0), val))
8913         cond = swap_condition (cond), temp = val, val = reg, reg = temp;
8914
8915       if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
8916         {
8917           if (COMPARISON_P (x))
8918             {
8919               if (comparison_dominates_p (cond, code))
8920                 return const_true_rtx;
8921
8922               code = reversed_comparison_code (x, NULL);
8923               if (code != UNKNOWN
8924                   && comparison_dominates_p (cond, code))
8925                 return const0_rtx;
8926               else
8927                 return x;
8928             }
8929           else if (code == SMAX || code == SMIN
8930                    || code == UMIN || code == UMAX)
8931             {
8932               int unsignedp = (code == UMIN || code == UMAX);
8933
8934               /* Do not reverse the condition when it is NE or EQ.
8935                  This is because we cannot conclude anything about
8936                  the value of 'SMAX (x, y)' when x is not equal to y,
8937                  but we can when x equals y.  */
8938               if ((code == SMAX || code == UMAX)
8939                   && ! (cond == EQ || cond == NE))
8940                 cond = reverse_condition (cond);
8941
8942               switch (cond)
8943                 {
8944                 case GE:   case GT:
8945                   return unsignedp ? x : XEXP (x, 1);
8946                 case LE:   case LT:
8947                   return unsignedp ? x : XEXP (x, 0);
8948                 case GEU:  case GTU:
8949                   return unsignedp ? XEXP (x, 1) : x;
8950                 case LEU:  case LTU:
8951                   return unsignedp ? XEXP (x, 0) : x;
8952                 default:
8953                   break;
8954                 }
8955             }
8956         }
8957     }
8958   else if (code == SUBREG)
8959     {
8960       enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
8961       rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
8962
8963       if (SUBREG_REG (x) != r)
8964         {
8965           /* We must simplify subreg here, before we lose track of the
8966              original inner_mode.  */
8967           new_rtx = simplify_subreg (GET_MODE (x), r,
8968                                  inner_mode, SUBREG_BYTE (x));
8969           if (new_rtx)
8970             return new_rtx;
8971           else
8972             SUBST (SUBREG_REG (x), r);
8973         }
8974
8975       return x;
8976     }
8977   /* We don't have to handle SIGN_EXTEND here, because even in the
8978      case of replacing something with a modeless CONST_INT, a
8979      CONST_INT is already (supposed to be) a valid sign extension for
8980      its narrower mode, which implies it's already properly
8981      sign-extended for the wider mode.  Now, for ZERO_EXTEND, the
8982      story is different.  */
8983   else if (code == ZERO_EXTEND)
8984     {
8985       enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
8986       rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
8987
8988       if (XEXP (x, 0) != r)
8989         {
8990           /* We must simplify the zero_extend here, before we lose
8991              track of the original inner_mode.  */
8992           new_rtx = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
8993                                           r, inner_mode);
8994           if (new_rtx)
8995             return new_rtx;
8996           else
8997             SUBST (XEXP (x, 0), r);
8998         }
8999
9000       return x;
9001     }
9002
9003   fmt = GET_RTX_FORMAT (code);
9004   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9005     {
9006       if (fmt[i] == 'e')
9007         SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
9008       else if (fmt[i] == 'E')
9009         for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9010           SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
9011                                                 cond, reg, val));
9012     }
9013
9014   return x;
9015 }
9016 \f
9017 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
9018    assignment as a field assignment.  */
9019
9020 static int
9021 rtx_equal_for_field_assignment_p (rtx x, rtx y)
9022 {
9023   if (x == y || rtx_equal_p (x, y))
9024     return 1;
9025
9026   if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
9027     return 0;
9028
9029   /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9030      Note that all SUBREGs of MEM are paradoxical; otherwise they
9031      would have been rewritten.  */
9032   if (MEM_P (x) && GET_CODE (y) == SUBREG
9033       && MEM_P (SUBREG_REG (y))
9034       && rtx_equal_p (SUBREG_REG (y),
9035                       gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
9036     return 1;
9037
9038   if (MEM_P (y) && GET_CODE (x) == SUBREG
9039       && MEM_P (SUBREG_REG (x))
9040       && rtx_equal_p (SUBREG_REG (x),
9041                       gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
9042     return 1;
9043
9044   /* We used to see if get_last_value of X and Y were the same but that's
9045      not correct.  In one direction, we'll cause the assignment to have
9046      the wrong destination and in the case, we'll import a register into this
9047      insn that might have already have been dead.   So fail if none of the
9048      above cases are true.  */
9049   return 0;
9050 }
9051 \f
9052 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
9053    Return that assignment if so.
9054
9055    We only handle the most common cases.  */
9056
9057 static rtx
9058 make_field_assignment (rtx x)
9059 {
9060   rtx dest = SET_DEST (x);
9061   rtx src = SET_SRC (x);
9062   rtx assign;
9063   rtx rhs, lhs;
9064   HOST_WIDE_INT c1;
9065   HOST_WIDE_INT pos;
9066   unsigned HOST_WIDE_INT len;
9067   rtx other;
9068   enum machine_mode mode;
9069
9070   /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9071      a clear of a one-bit field.  We will have changed it to
9072      (and (rotate (const_int -2) POS) DEST), so check for that.  Also check
9073      for a SUBREG.  */
9074
9075   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
9076       && CONST_INT_P (XEXP (XEXP (src, 0), 0))
9077       && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
9078       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9079     {
9080       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9081                                 1, 1, 1, 0);
9082       if (assign != 0)
9083         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9084       return x;
9085     }
9086
9087   if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
9088       && subreg_lowpart_p (XEXP (src, 0))
9089       && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
9090           < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
9091       && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
9092       && CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
9093       && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
9094       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9095     {
9096       assign = make_extraction (VOIDmode, dest, 0,
9097                                 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
9098                                 1, 1, 1, 0);
9099       if (assign != 0)
9100         return gen_rtx_SET (VOIDmode, assign, const0_rtx);
9101       return x;
9102     }
9103
9104   /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9105      one-bit field.  */
9106   if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9107       && XEXP (XEXP (src, 0), 0) == const1_rtx
9108       && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
9109     {
9110       assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
9111                                 1, 1, 1, 0);
9112       if (assign != 0)
9113         return gen_rtx_SET (VOIDmode, assign, const1_rtx);
9114       return x;
9115     }
9116
9117   /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9118      SRC is an AND with all bits of that field set, then we can discard
9119      the AND.  */
9120   if (GET_CODE (dest) == ZERO_EXTRACT
9121       && CONST_INT_P (XEXP (dest, 1))
9122       && GET_CODE (src) == AND
9123       && CONST_INT_P (XEXP (src, 1)))
9124     {
9125       HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9126       unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9127       unsigned HOST_WIDE_INT ze_mask;
9128
9129       if (width >= HOST_BITS_PER_WIDE_INT)
9130         ze_mask = -1;
9131       else
9132         ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9133
9134       /* Complete overlap.  We can remove the source AND.  */
9135       if ((and_mask & ze_mask) == ze_mask)
9136         return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
9137
9138       /* Partial overlap.  We can reduce the source AND.  */
9139       if ((and_mask & ze_mask) != and_mask)
9140         {
9141           mode = GET_MODE (src);
9142           src = gen_rtx_AND (mode, XEXP (src, 0),
9143                              gen_int_mode (and_mask & ze_mask, mode));
9144           return gen_rtx_SET (VOIDmode, dest, src);
9145         }
9146     }
9147
9148   /* The other case we handle is assignments into a constant-position
9149      field.  They look like (ior/xor (and DEST C1) OTHER).  If C1 represents
9150      a mask that has all one bits except for a group of zero bits and
9151      OTHER is known to have zeros where C1 has ones, this is such an
9152      assignment.  Compute the position and length from C1.  Shift OTHER
9153      to the appropriate position, force it to the required mode, and
9154      make the extraction.  Check for the AND in both operands.  */
9155
9156   if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9157     return x;
9158
9159   rhs = expand_compound_operation (XEXP (src, 0));
9160   lhs = expand_compound_operation (XEXP (src, 1));
9161
9162   if (GET_CODE (rhs) == AND
9163       && CONST_INT_P (XEXP (rhs, 1))
9164       && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
9165     c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9166   else if (GET_CODE (lhs) == AND
9167            && CONST_INT_P (XEXP (lhs, 1))
9168            && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
9169     c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9170   else
9171     return x;
9172
9173   pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
9174   if (pos < 0 || pos + len > GET_MODE_PRECISION (GET_MODE (dest))
9175       || GET_MODE_PRECISION (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
9176       || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
9177     return x;
9178
9179   assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
9180   if (assign == 0)
9181     return x;
9182
9183   /* The mode to use for the source is the mode of the assignment, or of
9184      what is inside a possible STRICT_LOW_PART.  */
9185   mode = (GET_CODE (assign) == STRICT_LOW_PART
9186           ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9187
9188   /* Shift OTHER right POS places and make it the source, restricting it
9189      to the proper length and mode.  */
9190
9191   src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
9192                                                      GET_MODE (src),
9193                                                      other, pos),
9194                                dest);
9195   src = force_to_mode (src, mode,
9196                        GET_MODE_PRECISION (mode) >= HOST_BITS_PER_WIDE_INT
9197                        ? ~(unsigned HOST_WIDE_INT) 0
9198                        : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
9199                        0);
9200
9201   /* If SRC is masked by an AND that does not make a difference in
9202      the value being stored, strip it.  */
9203   if (GET_CODE (assign) == ZERO_EXTRACT
9204       && CONST_INT_P (XEXP (assign, 1))
9205       && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9206       && GET_CODE (src) == AND
9207       && CONST_INT_P (XEXP (src, 1))
9208       && UINTVAL (XEXP (src, 1))
9209          == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1)
9210     src = XEXP (src, 0);
9211
9212   return gen_rtx_SET (VOIDmode, assign, src);
9213 }
9214 \f
9215 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9216    if so.  */
9217
9218 static rtx
9219 apply_distributive_law (rtx x)
9220 {
9221   enum rtx_code code = GET_CODE (x);
9222   enum rtx_code inner_code;
9223   rtx lhs, rhs, other;
9224   rtx tem;
9225
9226   /* Distributivity is not true for floating point as it can change the
9227      value.  So we don't do it unless -funsafe-math-optimizations.  */
9228   if (FLOAT_MODE_P (GET_MODE (x))
9229       && ! flag_unsafe_math_optimizations)
9230     return x;
9231
9232   /* The outer operation can only be one of the following:  */
9233   if (code != IOR && code != AND && code != XOR
9234       && code != PLUS && code != MINUS)
9235     return x;
9236
9237   lhs = XEXP (x, 0);
9238   rhs = XEXP (x, 1);
9239
9240   /* If either operand is a primitive we can't do anything, so get out
9241      fast.  */
9242   if (OBJECT_P (lhs) || OBJECT_P (rhs))
9243     return x;
9244
9245   lhs = expand_compound_operation (lhs);
9246   rhs = expand_compound_operation (rhs);
9247   inner_code = GET_CODE (lhs);
9248   if (inner_code != GET_CODE (rhs))
9249     return x;
9250
9251   /* See if the inner and outer operations distribute.  */
9252   switch (inner_code)
9253     {
9254     case LSHIFTRT:
9255     case ASHIFTRT:
9256     case AND:
9257     case IOR:
9258       /* These all distribute except over PLUS.  */
9259       if (code == PLUS || code == MINUS)
9260         return x;
9261       break;
9262
9263     case MULT:
9264       if (code != PLUS && code != MINUS)
9265         return x;
9266       break;
9267
9268     case ASHIFT:
9269       /* This is also a multiply, so it distributes over everything.  */
9270       break;
9271
9272     case SUBREG:
9273       /* Non-paradoxical SUBREGs distributes over all operations,
9274          provided the inner modes and byte offsets are the same, this
9275          is an extraction of a low-order part, we don't convert an fp
9276          operation to int or vice versa, this is not a vector mode,
9277          and we would not be converting a single-word operation into a
9278          multi-word operation.  The latter test is not required, but
9279          it prevents generating unneeded multi-word operations.  Some
9280          of the previous tests are redundant given the latter test,
9281          but are retained because they are required for correctness.
9282
9283          We produce the result slightly differently in this case.  */
9284
9285       if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
9286           || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
9287           || ! subreg_lowpart_p (lhs)
9288           || (GET_MODE_CLASS (GET_MODE (lhs))
9289               != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
9290           || paradoxical_subreg_p (lhs)
9291           || VECTOR_MODE_P (GET_MODE (lhs))
9292           || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD
9293           /* Result might need to be truncated.  Don't change mode if
9294              explicit truncation is needed.  */
9295           || !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (x),
9296                                              GET_MODE (SUBREG_REG (lhs))))
9297         return x;
9298
9299       tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
9300                                  SUBREG_REG (lhs), SUBREG_REG (rhs));
9301       return gen_lowpart (GET_MODE (x), tem);
9302
9303     default:
9304       return x;
9305     }
9306
9307   /* Set LHS and RHS to the inner operands (A and B in the example
9308      above) and set OTHER to the common operand (C in the example).
9309      There is only one way to do this unless the inner operation is
9310      commutative.  */
9311   if (COMMUTATIVE_ARITH_P (lhs)
9312       && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9313     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9314   else if (COMMUTATIVE_ARITH_P (lhs)
9315            && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9316     other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9317   else if (COMMUTATIVE_ARITH_P (lhs)
9318            && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9319     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9320   else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9321     other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9322   else
9323     return x;
9324
9325   /* Form the new inner operation, seeing if it simplifies first.  */
9326   tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
9327
9328   /* There is one exception to the general way of distributing:
9329      (a | c) ^ (b | c) -> (a ^ b) & ~c  */
9330   if (code == XOR && inner_code == IOR)
9331     {
9332       inner_code = AND;
9333       other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
9334     }
9335
9336   /* We may be able to continuing distributing the result, so call
9337      ourselves recursively on the inner operation before forming the
9338      outer operation, which we return.  */
9339   return simplify_gen_binary (inner_code, GET_MODE (x),
9340                               apply_distributive_law (tem), other);
9341 }
9342
9343 /* See if X is of the form (* (+ A B) C), and if so convert to
9344    (+ (* A C) (* B C)) and try to simplify.
9345
9346    Most of the time, this results in no change.  However, if some of
9347    the operands are the same or inverses of each other, simplifications
9348    will result.
9349
9350    For example, (and (ior A B) (not B)) can occur as the result of
9351    expanding a bit field assignment.  When we apply the distributive
9352    law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9353    which then simplifies to (and (A (not B))).
9354
9355    Note that no checks happen on the validity of applying the inverse
9356    distributive law.  This is pointless since we can do it in the
9357    few places where this routine is called.
9358
9359    N is the index of the term that is decomposed (the arithmetic operation,
9360    i.e. (+ A B) in the first example above).  !N is the index of the term that
9361    is distributed, i.e. of C in the first example above.  */
9362 static rtx
9363 distribute_and_simplify_rtx (rtx x, int n)
9364 {
9365   enum machine_mode mode;
9366   enum rtx_code outer_code, inner_code;
9367   rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9368
9369   /* Distributivity is not true for floating point as it can change the
9370      value.  So we don't do it unless -funsafe-math-optimizations.  */
9371   if (FLOAT_MODE_P (GET_MODE (x))
9372       && ! flag_unsafe_math_optimizations)
9373     return NULL_RTX;
9374
9375   decomposed = XEXP (x, n);
9376   if (!ARITHMETIC_P (decomposed))
9377     return NULL_RTX;
9378
9379   mode = GET_MODE (x);
9380   outer_code = GET_CODE (x);
9381   distributed = XEXP (x, !n);
9382
9383   inner_code = GET_CODE (decomposed);
9384   inner_op0 = XEXP (decomposed, 0);
9385   inner_op1 = XEXP (decomposed, 1);
9386
9387   /* Special case (and (xor B C) (not A)), which is equivalent to
9388      (xor (ior A B) (ior A C))  */
9389   if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
9390     {
9391       distributed = XEXP (distributed, 0);
9392       outer_code = IOR;
9393     }
9394
9395   if (n == 0)
9396     {
9397       /* Distribute the second term.  */
9398       new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
9399       new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
9400     }
9401   else
9402     {
9403       /* Distribute the first term.  */
9404       new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
9405       new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
9406     }
9407
9408   tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
9409                                                      new_op0, new_op1));
9410   if (GET_CODE (tmp) != outer_code
9411       && (set_src_cost (tmp, optimize_this_for_speed_p)
9412           < set_src_cost (x, optimize_this_for_speed_p)))
9413     return tmp;
9414
9415   return NULL_RTX;
9416 }
9417 \f
9418 /* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
9419    in MODE.  Return an equivalent form, if different from (and VAROP
9420    (const_int CONSTOP)).  Otherwise, return NULL_RTX.  */
9421
9422 static rtx
9423 simplify_and_const_int_1 (enum machine_mode mode, rtx varop,
9424                           unsigned HOST_WIDE_INT constop)
9425 {
9426   unsigned HOST_WIDE_INT nonzero;
9427   unsigned HOST_WIDE_INT orig_constop;
9428   rtx orig_varop;
9429   int i;
9430
9431   orig_varop = varop;
9432   orig_constop = constop;
9433   if (GET_CODE (varop) == CLOBBER)
9434     return NULL_RTX;
9435
9436   /* Simplify VAROP knowing that we will be only looking at some of the
9437      bits in it.
9438
9439      Note by passing in CONSTOP, we guarantee that the bits not set in
9440      CONSTOP are not significant and will never be examined.  We must
9441      ensure that is the case by explicitly masking out those bits
9442      before returning.  */
9443   varop = force_to_mode (varop, mode, constop, 0);
9444
9445   /* If VAROP is a CLOBBER, we will fail so return it.  */
9446   if (GET_CODE (varop) == CLOBBER)
9447     return varop;
9448
9449   /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
9450      to VAROP and return the new constant.  */
9451   if (CONST_INT_P (varop))
9452     return gen_int_mode (INTVAL (varop) & constop, mode);
9453
9454   /* See what bits may be nonzero in VAROP.  Unlike the general case of
9455      a call to nonzero_bits, here we don't care about bits outside
9456      MODE.  */
9457
9458   nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
9459
9460   /* Turn off all bits in the constant that are known to already be zero.
9461      Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
9462      which is tested below.  */
9463
9464   constop &= nonzero;
9465
9466   /* If we don't have any bits left, return zero.  */
9467   if (constop == 0)
9468     return const0_rtx;
9469
9470   /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
9471      a power of two, we can replace this with an ASHIFT.  */
9472   if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
9473       && (i = exact_log2 (constop)) >= 0)
9474     return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
9475
9476   /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
9477      or XOR, then try to apply the distributive law.  This may eliminate
9478      operations if either branch can be simplified because of the AND.
9479      It may also make some cases more complex, but those cases probably
9480      won't match a pattern either with or without this.  */
9481
9482   if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
9483     return
9484       gen_lowpart
9485         (mode,
9486          apply_distributive_law
9487          (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
9488                                simplify_and_const_int (NULL_RTX,
9489                                                        GET_MODE (varop),
9490                                                        XEXP (varop, 0),
9491                                                        constop),
9492                                simplify_and_const_int (NULL_RTX,
9493                                                        GET_MODE (varop),
9494                                                        XEXP (varop, 1),
9495                                                        constop))));
9496
9497   /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
9498      the AND and see if one of the operands simplifies to zero.  If so, we
9499      may eliminate it.  */
9500
9501   if (GET_CODE (varop) == PLUS
9502       && exact_log2 (constop + 1) >= 0)
9503     {
9504       rtx o0, o1;
9505
9506       o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
9507       o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
9508       if (o0 == const0_rtx)
9509         return o1;
9510       if (o1 == const0_rtx)
9511         return o0;
9512     }
9513
9514   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
9515   varop = gen_lowpart (mode, varop);
9516   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
9517     return NULL_RTX;
9518
9519   /* If we are only masking insignificant bits, return VAROP.  */
9520   if (constop == nonzero)
9521     return varop;
9522
9523   if (varop == orig_varop && constop == orig_constop)
9524     return NULL_RTX;
9525
9526   /* Otherwise, return an AND.  */
9527   return simplify_gen_binary (AND, mode, varop, gen_int_mode (constop, mode));
9528 }
9529
9530
9531 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
9532    in MODE.
9533
9534    Return an equivalent form, if different from X.  Otherwise, return X.  If
9535    X is zero, we are to always construct the equivalent form.  */
9536
9537 static rtx
9538 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
9539                         unsigned HOST_WIDE_INT constop)
9540 {
9541   rtx tem = simplify_and_const_int_1 (mode, varop, constop);
9542   if (tem)
9543     return tem;
9544
9545   if (!x)
9546     x = simplify_gen_binary (AND, GET_MODE (varop), varop,
9547                              gen_int_mode (constop, mode));
9548   if (GET_MODE (x) != mode)
9549     x = gen_lowpart (mode, x);
9550   return x;
9551 }
9552 \f
9553 /* Given a REG, X, compute which bits in X can be nonzero.
9554    We don't care about bits outside of those defined in MODE.
9555
9556    For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
9557    a shift, AND, or zero_extract, we can do better.  */
9558
9559 static rtx
9560 reg_nonzero_bits_for_combine (const_rtx x, enum machine_mode mode,
9561                               const_rtx known_x ATTRIBUTE_UNUSED,
9562                               enum machine_mode known_mode ATTRIBUTE_UNUSED,
9563                               unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
9564                               unsigned HOST_WIDE_INT *nonzero)
9565 {
9566   rtx tem;
9567   reg_stat_type *rsp;
9568
9569   /* If X is a register whose nonzero bits value is current, use it.
9570      Otherwise, if X is a register whose value we can find, use that
9571      value.  Otherwise, use the previously-computed global nonzero bits
9572      for this register.  */
9573
9574   rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9575   if (rsp->last_set_value != 0
9576       && (rsp->last_set_mode == mode
9577           || (GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
9578               && GET_MODE_CLASS (mode) == MODE_INT))
9579       && ((rsp->last_set_label >= label_tick_ebb_start
9580            && rsp->last_set_label < label_tick)
9581           || (rsp->last_set_label == label_tick
9582               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9583           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9584               && REG_N_SETS (REGNO (x)) == 1
9585               && !REGNO_REG_SET_P
9586                   (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9587     {
9588       *nonzero &= rsp->last_set_nonzero_bits;
9589       return NULL;
9590     }
9591
9592   tem = get_last_value (x);
9593
9594   if (tem)
9595     {
9596 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
9597       /* If X is narrower than MODE and TEM is a non-negative
9598          constant that would appear negative in the mode of X,
9599          sign-extend it for use in reg_nonzero_bits because some
9600          machines (maybe most) will actually do the sign-extension
9601          and this is the conservative approach.
9602
9603          ??? For 2.5, try to tighten up the MD files in this regard
9604          instead of this kludge.  */
9605
9606       if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode)
9607           && CONST_INT_P (tem)
9608           && INTVAL (tem) > 0
9609           && val_signbit_known_set_p (GET_MODE (x), INTVAL (tem)))
9610         tem = GEN_INT (INTVAL (tem) | ~GET_MODE_MASK (GET_MODE (x)));
9611 #endif
9612       return tem;
9613     }
9614   else if (nonzero_sign_valid && rsp->nonzero_bits)
9615     {
9616       unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
9617
9618       if (GET_MODE_PRECISION (GET_MODE (x)) < GET_MODE_PRECISION (mode))
9619         /* We don't know anything about the upper bits.  */
9620         mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
9621       *nonzero &= mask;
9622     }
9623
9624   return NULL;
9625 }
9626
9627 /* Return the number of bits at the high-order end of X that are known to
9628    be equal to the sign bit.  X will be used in mode MODE; if MODE is
9629    VOIDmode, X will be used in its own mode.  The returned value  will always
9630    be between 1 and the number of bits in MODE.  */
9631
9632 static rtx
9633 reg_num_sign_bit_copies_for_combine (const_rtx x, enum machine_mode mode,
9634                                      const_rtx known_x ATTRIBUTE_UNUSED,
9635                                      enum machine_mode known_mode
9636                                      ATTRIBUTE_UNUSED,
9637                                      unsigned int known_ret ATTRIBUTE_UNUSED,
9638                                      unsigned int *result)
9639 {
9640   rtx tem;
9641   reg_stat_type *rsp;
9642
9643   rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
9644   if (rsp->last_set_value != 0
9645       && rsp->last_set_mode == mode
9646       && ((rsp->last_set_label >= label_tick_ebb_start
9647            && rsp->last_set_label < label_tick)
9648           || (rsp->last_set_label == label_tick
9649               && DF_INSN_LUID (rsp->last_set) < subst_low_luid)
9650           || (REGNO (x) >= FIRST_PSEUDO_REGISTER
9651               && REG_N_SETS (REGNO (x)) == 1
9652               && !REGNO_REG_SET_P
9653                   (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), REGNO (x)))))
9654     {
9655       *result = rsp->last_set_sign_bit_copies;
9656       return NULL;
9657     }
9658
9659   tem = get_last_value (x);
9660   if (tem != 0)
9661     return tem;
9662
9663   if (nonzero_sign_valid && rsp->sign_bit_copies != 0
9664       && GET_MODE_PRECISION (GET_MODE (x)) == GET_MODE_PRECISION (mode))
9665     *result = rsp->sign_bit_copies;
9666
9667   return NULL;
9668 }
9669 \f
9670 /* Return the number of "extended" bits there are in X, when interpreted
9671    as a quantity in MODE whose signedness is indicated by UNSIGNEDP.  For
9672    unsigned quantities, this is the number of high-order zero bits.
9673    For signed quantities, this is the number of copies of the sign bit
9674    minus 1.  In both case, this function returns the number of "spare"
9675    bits.  For example, if two quantities for which this function returns
9676    at least 1 are added, the addition is known not to overflow.
9677
9678    This function will always return 0 unless called during combine, which
9679    implies that it must be called from a define_split.  */
9680
9681 unsigned int
9682 extended_count (const_rtx x, enum machine_mode mode, int unsignedp)
9683 {
9684   if (nonzero_sign_valid == 0)
9685     return 0;
9686
9687   return (unsignedp
9688           ? (HWI_COMPUTABLE_MODE_P (mode)
9689              ? (unsigned int) (GET_MODE_PRECISION (mode) - 1
9690                                - floor_log2 (nonzero_bits (x, mode)))
9691              : 0)
9692           : num_sign_bit_copies (x, mode) - 1);
9693 }
9694 \f
9695 /* This function is called from `simplify_shift_const' to merge two
9696    outer operations.  Specifically, we have already found that we need
9697    to perform operation *POP0 with constant *PCONST0 at the outermost
9698    position.  We would now like to also perform OP1 with constant CONST1
9699    (with *POP0 being done last).
9700
9701    Return 1 if we can do the operation and update *POP0 and *PCONST0 with
9702    the resulting operation.  *PCOMP_P is set to 1 if we would need to
9703    complement the innermost operand, otherwise it is unchanged.
9704
9705    MODE is the mode in which the operation will be done.  No bits outside
9706    the width of this mode matter.  It is assumed that the width of this mode
9707    is smaller than or equal to HOST_BITS_PER_WIDE_INT.
9708
9709    If *POP0 or OP1 are UNKNOWN, it means no operation is required.  Only NEG, PLUS,
9710    IOR, XOR, and AND are supported.  We may set *POP0 to SET if the proper
9711    result is simply *PCONST0.
9712
9713    If the resulting operation cannot be expressed as one operation, we
9714    return 0 and do not change *POP0, *PCONST0, and *PCOMP_P.  */
9715
9716 static int
9717 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
9718 {
9719   enum rtx_code op0 = *pop0;
9720   HOST_WIDE_INT const0 = *pconst0;
9721
9722   const0 &= GET_MODE_MASK (mode);
9723   const1 &= GET_MODE_MASK (mode);
9724
9725   /* If OP0 is an AND, clear unimportant bits in CONST1.  */
9726   if (op0 == AND)
9727     const1 &= const0;
9728
9729   /* If OP0 or OP1 is UNKNOWN, this is easy.  Similarly if they are the same or
9730      if OP0 is SET.  */
9731
9732   if (op1 == UNKNOWN || op0 == SET)
9733     return 1;
9734
9735   else if (op0 == UNKNOWN)
9736     op0 = op1, const0 = const1;
9737
9738   else if (op0 == op1)
9739     {
9740       switch (op0)
9741         {
9742         case AND:
9743           const0 &= const1;
9744           break;
9745         case IOR:
9746           const0 |= const1;
9747           break;
9748         case XOR:
9749           const0 ^= const1;
9750           break;
9751         case PLUS:
9752           const0 += const1;
9753           break;
9754         case NEG:
9755           op0 = UNKNOWN;
9756           break;
9757         default:
9758           break;
9759         }
9760     }
9761
9762   /* Otherwise, if either is a PLUS or NEG, we can't do anything.  */
9763   else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
9764     return 0;
9765
9766   /* If the two constants aren't the same, we can't do anything.  The
9767      remaining six cases can all be done.  */
9768   else if (const0 != const1)
9769     return 0;
9770
9771   else
9772     switch (op0)
9773       {
9774       case IOR:
9775         if (op1 == AND)
9776           /* (a & b) | b == b */
9777           op0 = SET;
9778         else /* op1 == XOR */
9779           /* (a ^ b) | b == a | b */
9780           {;}
9781         break;
9782
9783       case XOR:
9784         if (op1 == AND)
9785           /* (a & b) ^ b == (~a) & b */
9786           op0 = AND, *pcomp_p = 1;
9787         else /* op1 == IOR */
9788           /* (a | b) ^ b == a & ~b */
9789           op0 = AND, const0 = ~const0;
9790         break;
9791
9792       case AND:
9793         if (op1 == IOR)
9794           /* (a | b) & b == b */
9795         op0 = SET;
9796         else /* op1 == XOR */
9797           /* (a ^ b) & b) == (~a) & b */
9798           *pcomp_p = 1;
9799         break;
9800       default:
9801         break;
9802       }
9803
9804   /* Check for NO-OP cases.  */
9805   const0 &= GET_MODE_MASK (mode);
9806   if (const0 == 0
9807       && (op0 == IOR || op0 == XOR || op0 == PLUS))
9808     op0 = UNKNOWN;
9809   else if (const0 == 0 && op0 == AND)
9810     op0 = SET;
9811   else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
9812            && op0 == AND)
9813     op0 = UNKNOWN;
9814
9815   *pop0 = op0;
9816
9817   /* ??? Slightly redundant with the above mask, but not entirely.
9818      Moving this above means we'd have to sign-extend the mode mask
9819      for the final test.  */
9820   if (op0 != UNKNOWN && op0 != NEG)
9821     *pconst0 = trunc_int_for_mode (const0, mode);
9822
9823   return 1;
9824 }
9825 \f
9826 /* A helper to simplify_shift_const_1 to determine the mode we can perform
9827    the shift in.  The original shift operation CODE is performed on OP in
9828    ORIG_MODE.  Return the wider mode MODE if we can perform the operation
9829    in that mode.  Return ORIG_MODE otherwise.  We can also assume that the
9830    result of the shift is subject to operation OUTER_CODE with operand
9831    OUTER_CONST.  */
9832
9833 static enum machine_mode
9834 try_widen_shift_mode (enum rtx_code code, rtx op, int count,
9835                       enum machine_mode orig_mode, enum machine_mode mode,
9836                       enum rtx_code outer_code, HOST_WIDE_INT outer_const)
9837 {
9838   if (orig_mode == mode)
9839     return mode;
9840   gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
9841
9842   /* In general we can't perform in wider mode for right shift and rotate.  */
9843   switch (code)
9844     {
9845     case ASHIFTRT:
9846       /* We can still widen if the bits brought in from the left are identical
9847          to the sign bit of ORIG_MODE.  */
9848       if (num_sign_bit_copies (op, mode)
9849           > (unsigned) (GET_MODE_PRECISION (mode)
9850                         - GET_MODE_PRECISION (orig_mode)))
9851         return mode;
9852       return orig_mode;
9853
9854     case LSHIFTRT:
9855       /* Similarly here but with zero bits.  */
9856       if (HWI_COMPUTABLE_MODE_P (mode)
9857           && (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
9858         return mode;
9859
9860       /* We can also widen if the bits brought in will be masked off.  This
9861          operation is performed in ORIG_MODE.  */
9862       if (outer_code == AND)
9863         {
9864           int care_bits = low_bitmask_len (orig_mode, outer_const);
9865
9866           if (care_bits >= 0
9867               && GET_MODE_PRECISION (orig_mode) - care_bits >= count)
9868             return mode;
9869         }
9870       /* fall through */
9871
9872     case ROTATE:
9873       return orig_mode;
9874
9875     case ROTATERT:
9876       gcc_unreachable ();
9877
9878     default:
9879       return mode;
9880     }
9881 }
9882
9883 /* Simplify a shift of VAROP by ORIG_COUNT bits.  CODE says what kind
9884    of shift.  The result of the shift is RESULT_MODE.  Return NULL_RTX
9885    if we cannot simplify it.  Otherwise, return a simplified value.
9886
9887    The shift is normally computed in the widest mode we find in VAROP, as
9888    long as it isn't a different number of words than RESULT_MODE.  Exceptions
9889    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
9890
9891 static rtx
9892 simplify_shift_const_1 (enum rtx_code code, enum machine_mode result_mode,
9893                         rtx varop, int orig_count)
9894 {
9895   enum rtx_code orig_code = code;
9896   rtx orig_varop = varop;
9897   int count;
9898   enum machine_mode mode = result_mode;
9899   enum machine_mode shift_mode, tmode;
9900   unsigned int mode_words
9901     = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
9902   /* We form (outer_op (code varop count) (outer_const)).  */
9903   enum rtx_code outer_op = UNKNOWN;
9904   HOST_WIDE_INT outer_const = 0;
9905   int complement_p = 0;
9906   rtx new_rtx, x;
9907
9908   /* Make sure and truncate the "natural" shift on the way in.  We don't
9909      want to do this inside the loop as it makes it more difficult to
9910      combine shifts.  */
9911   if (SHIFT_COUNT_TRUNCATED)
9912     orig_count &= GET_MODE_BITSIZE (mode) - 1;
9913
9914   /* If we were given an invalid count, don't do anything except exactly
9915      what was requested.  */
9916
9917   if (orig_count < 0 || orig_count >= (int) GET_MODE_PRECISION (mode))
9918     return NULL_RTX;
9919
9920   count = orig_count;
9921
9922   /* Unless one of the branches of the `if' in this loop does a `continue',
9923      we will `break' the loop after the `if'.  */
9924
9925   while (count != 0)
9926     {
9927       /* If we have an operand of (clobber (const_int 0)), fail.  */
9928       if (GET_CODE (varop) == CLOBBER)
9929         return NULL_RTX;
9930
9931       /* Convert ROTATERT to ROTATE.  */
9932       if (code == ROTATERT)
9933         {
9934           unsigned int bitsize = GET_MODE_PRECISION (result_mode);
9935           code = ROTATE;
9936           if (VECTOR_MODE_P (result_mode))
9937             count = bitsize / GET_MODE_NUNITS (result_mode) - count;
9938           else
9939             count = bitsize - count;
9940         }
9941
9942       shift_mode = try_widen_shift_mode (code, varop, count, result_mode,
9943                                          mode, outer_op, outer_const);
9944
9945       /* Handle cases where the count is greater than the size of the mode
9946          minus 1.  For ASHIFT, use the size minus one as the count (this can
9947          occur when simplifying (lshiftrt (ashiftrt ..))).  For rotates,
9948          take the count modulo the size.  For other shifts, the result is
9949          zero.
9950
9951          Since these shifts are being produced by the compiler by combining
9952          multiple operations, each of which are defined, we know what the
9953          result is supposed to be.  */
9954
9955       if (count > (GET_MODE_PRECISION (shift_mode) - 1))
9956         {
9957           if (code == ASHIFTRT)
9958             count = GET_MODE_PRECISION (shift_mode) - 1;
9959           else if (code == ROTATE || code == ROTATERT)
9960             count %= GET_MODE_PRECISION (shift_mode);
9961           else
9962             {
9963               /* We can't simply return zero because there may be an
9964                  outer op.  */
9965               varop = const0_rtx;
9966               count = 0;
9967               break;
9968             }
9969         }
9970
9971       /* If we discovered we had to complement VAROP, leave.  Making a NOT
9972          here would cause an infinite loop.  */
9973       if (complement_p)
9974         break;
9975
9976       /* An arithmetic right shift of a quantity known to be -1 or 0
9977          is a no-op.  */
9978       if (code == ASHIFTRT
9979           && (num_sign_bit_copies (varop, shift_mode)
9980               == GET_MODE_PRECISION (shift_mode)))
9981         {
9982           count = 0;
9983           break;
9984         }
9985
9986       /* If we are doing an arithmetic right shift and discarding all but
9987          the sign bit copies, this is equivalent to doing a shift by the
9988          bitsize minus one.  Convert it into that shift because it will often
9989          allow other simplifications.  */
9990
9991       if (code == ASHIFTRT
9992           && (count + num_sign_bit_copies (varop, shift_mode)
9993               >= GET_MODE_PRECISION (shift_mode)))
9994         count = GET_MODE_PRECISION (shift_mode) - 1;
9995
9996       /* We simplify the tests below and elsewhere by converting
9997          ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
9998          `make_compound_operation' will convert it to an ASHIFTRT for
9999          those machines (such as VAX) that don't have an LSHIFTRT.  */
10000       if (code == ASHIFTRT
10001           && val_signbit_known_clear_p (shift_mode,
10002                                         nonzero_bits (varop, shift_mode)))
10003         code = LSHIFTRT;
10004
10005       if (((code == LSHIFTRT
10006             && HWI_COMPUTABLE_MODE_P (shift_mode)
10007             && !(nonzero_bits (varop, shift_mode) >> count))
10008            || (code == ASHIFT
10009                && HWI_COMPUTABLE_MODE_P (shift_mode)
10010                && !((nonzero_bits (varop, shift_mode) << count)
10011                     & GET_MODE_MASK (shift_mode))))
10012           && !side_effects_p (varop))
10013         varop = const0_rtx;
10014
10015       switch (GET_CODE (varop))
10016         {
10017         case SIGN_EXTEND:
10018         case ZERO_EXTEND:
10019         case SIGN_EXTRACT:
10020         case ZERO_EXTRACT:
10021           new_rtx = expand_compound_operation (varop);
10022           if (new_rtx != varop)
10023             {
10024               varop = new_rtx;
10025               continue;
10026             }
10027           break;
10028
10029         case MEM:
10030           /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10031              minus the width of a smaller mode, we can do this with a
10032              SIGN_EXTEND or ZERO_EXTEND from the narrower memory location.  */
10033           if ((code == ASHIFTRT || code == LSHIFTRT)
10034               && ! mode_dependent_address_p (XEXP (varop, 0))
10035               && ! MEM_VOLATILE_P (varop)
10036               && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
10037                                          MODE_INT, 1)) != BLKmode)
10038             {
10039               new_rtx = adjust_address_nv (varop, tmode,
10040                                        BYTES_BIG_ENDIAN ? 0
10041                                        : count / BITS_PER_UNIT);
10042
10043               varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
10044                                      : ZERO_EXTEND, mode, new_rtx);
10045               count = 0;
10046               continue;
10047             }
10048           break;
10049
10050         case SUBREG:
10051           /* If VAROP is a SUBREG, strip it as long as the inner operand has
10052              the same number of words as what we've seen so far.  Then store
10053              the widest mode in MODE.  */
10054           if (subreg_lowpart_p (varop)
10055               && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
10056                   > GET_MODE_SIZE (GET_MODE (varop)))
10057               && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
10058                                   + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
10059                  == mode_words
10060               && GET_MODE_CLASS (GET_MODE (varop)) == MODE_INT
10061               && GET_MODE_CLASS (GET_MODE (SUBREG_REG (varop))) == MODE_INT)
10062             {
10063               varop = SUBREG_REG (varop);
10064               if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
10065                 mode = GET_MODE (varop);
10066               continue;
10067             }
10068           break;
10069
10070         case MULT:
10071           /* Some machines use MULT instead of ASHIFT because MULT
10072              is cheaper.  But it is still better on those machines to
10073              merge two shifts into one.  */
10074           if (CONST_INT_P (XEXP (varop, 1))
10075               && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10076             {
10077               varop
10078                 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
10079                                        XEXP (varop, 0),
10080                                        GEN_INT (exact_log2 (
10081                                                 UINTVAL (XEXP (varop, 1)))));
10082               continue;
10083             }
10084           break;
10085
10086         case UDIV:
10087           /* Similar, for when divides are cheaper.  */
10088           if (CONST_INT_P (XEXP (varop, 1))
10089               && exact_log2 (UINTVAL (XEXP (varop, 1))) >= 0)
10090             {
10091               varop
10092                 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
10093                                        XEXP (varop, 0),
10094                                        GEN_INT (exact_log2 (
10095                                                 UINTVAL (XEXP (varop, 1)))));
10096               continue;
10097             }
10098           break;
10099
10100         case ASHIFTRT:
10101           /* If we are extracting just the sign bit of an arithmetic
10102              right shift, that shift is not needed.  However, the sign
10103              bit of a wider mode may be different from what would be
10104              interpreted as the sign bit in a narrower mode, so, if
10105              the result is narrower, don't discard the shift.  */
10106           if (code == LSHIFTRT
10107               && count == (GET_MODE_BITSIZE (result_mode) - 1)
10108               && (GET_MODE_BITSIZE (result_mode)
10109                   >= GET_MODE_BITSIZE (GET_MODE (varop))))
10110             {
10111               varop = XEXP (varop, 0);
10112               continue;
10113             }
10114
10115           /* ... fall through ...  */
10116
10117         case LSHIFTRT:
10118         case ASHIFT:
10119         case ROTATE:
10120           /* Here we have two nested shifts.  The result is usually the
10121              AND of a new shift with a mask.  We compute the result below.  */
10122           if (CONST_INT_P (XEXP (varop, 1))
10123               && INTVAL (XEXP (varop, 1)) >= 0
10124               && INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (GET_MODE (varop))
10125               && HWI_COMPUTABLE_MODE_P (result_mode)
10126               && HWI_COMPUTABLE_MODE_P (mode)
10127               && !VECTOR_MODE_P (result_mode))
10128             {
10129               enum rtx_code first_code = GET_CODE (varop);
10130               unsigned int first_count = INTVAL (XEXP (varop, 1));
10131               unsigned HOST_WIDE_INT mask;
10132               rtx mask_rtx;
10133
10134               /* We have one common special case.  We can't do any merging if
10135                  the inner code is an ASHIFTRT of a smaller mode.  However, if
10136                  we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10137                  with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10138                  we can convert it to
10139                  (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10140                  This simplifies certain SIGN_EXTEND operations.  */
10141               if (code == ASHIFT && first_code == ASHIFTRT
10142                   && count == (GET_MODE_PRECISION (result_mode)
10143                                - GET_MODE_PRECISION (GET_MODE (varop))))
10144                 {
10145                   /* C3 has the low-order C1 bits zero.  */
10146
10147                   mask = GET_MODE_MASK (mode)
10148                          & ~(((unsigned HOST_WIDE_INT) 1 << first_count) - 1);
10149
10150                   varop = simplify_and_const_int (NULL_RTX, result_mode,
10151                                                   XEXP (varop, 0), mask);
10152                   varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
10153                                                 varop, count);
10154                   count = first_count;
10155                   code = ASHIFTRT;
10156                   continue;
10157                 }
10158
10159               /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10160                  than C1 high-order bits equal to the sign bit, we can convert
10161                  this to either an ASHIFT or an ASHIFTRT depending on the
10162                  two counts.
10163
10164                  We cannot do this if VAROP's mode is not SHIFT_MODE.  */
10165
10166               if (code == ASHIFTRT && first_code == ASHIFT
10167                   && GET_MODE (varop) == shift_mode
10168                   && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
10169                       > first_count))
10170                 {
10171                   varop = XEXP (varop, 0);
10172                   count -= first_count;
10173                   if (count < 0)
10174                     {
10175                       count = -count;
10176                       code = ASHIFT;
10177                     }
10178
10179                   continue;
10180                 }
10181
10182               /* There are some cases we can't do.  If CODE is ASHIFTRT,
10183                  we can only do this if FIRST_CODE is also ASHIFTRT.
10184
10185                  We can't do the case when CODE is ROTATE and FIRST_CODE is
10186                  ASHIFTRT.
10187
10188                  If the mode of this shift is not the mode of the outer shift,
10189                  we can't do this if either shift is a right shift or ROTATE.
10190
10191                  Finally, we can't do any of these if the mode is too wide
10192                  unless the codes are the same.
10193
10194                  Handle the case where the shift codes are the same
10195                  first.  */
10196
10197               if (code == first_code)
10198                 {
10199                   if (GET_MODE (varop) != result_mode
10200                       && (code == ASHIFTRT || code == LSHIFTRT
10201                           || code == ROTATE))
10202                     break;
10203
10204                   count += first_count;
10205                   varop = XEXP (varop, 0);
10206                   continue;
10207                 }
10208
10209               if (code == ASHIFTRT
10210                   || (code == ROTATE && first_code == ASHIFTRT)
10211                   || GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
10212                   || (GET_MODE (varop) != result_mode
10213                       && (first_code == ASHIFTRT || first_code == LSHIFTRT
10214                           || first_code == ROTATE
10215                           || code == ROTATE)))
10216                 break;
10217
10218               /* To compute the mask to apply after the shift, shift the
10219                  nonzero bits of the inner shift the same way the
10220                  outer shift will.  */
10221
10222               mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
10223
10224               mask_rtx
10225                 = simplify_const_binary_operation (code, result_mode, mask_rtx,
10226                                                    GEN_INT (count));
10227
10228               /* Give up if we can't compute an outer operation to use.  */
10229               if (mask_rtx == 0
10230                   || !CONST_INT_P (mask_rtx)
10231                   || ! merge_outer_ops (&outer_op, &outer_const, AND,
10232                                         INTVAL (mask_rtx),
10233                                         result_mode, &complement_p))
10234                 break;
10235
10236               /* If the shifts are in the same direction, we add the
10237                  counts.  Otherwise, we subtract them.  */
10238               if ((code == ASHIFTRT || code == LSHIFTRT)
10239                   == (first_code == ASHIFTRT || first_code == LSHIFTRT))
10240                 count += first_count;
10241               else
10242                 count -= first_count;
10243
10244               /* If COUNT is positive, the new shift is usually CODE,
10245                  except for the two exceptions below, in which case it is
10246                  FIRST_CODE.  If the count is negative, FIRST_CODE should
10247                  always be used  */
10248               if (count > 0
10249                   && ((first_code == ROTATE && code == ASHIFT)
10250                       || (first_code == ASHIFTRT && code == LSHIFTRT)))
10251                 code = first_code;
10252               else if (count < 0)
10253                 code = first_code, count = -count;
10254
10255               varop = XEXP (varop, 0);
10256               continue;
10257             }
10258
10259           /* If we have (A << B << C) for any shift, we can convert this to
10260              (A << C << B).  This wins if A is a constant.  Only try this if
10261              B is not a constant.  */
10262
10263           else if (GET_CODE (varop) == code
10264                    && CONST_INT_P (XEXP (varop, 0))
10265                    && !CONST_INT_P (XEXP (varop, 1)))
10266             {
10267               rtx new_rtx = simplify_const_binary_operation (code, mode,
10268                                                          XEXP (varop, 0),
10269                                                          GEN_INT (count));
10270               varop = gen_rtx_fmt_ee (code, mode, new_rtx, XEXP (varop, 1));
10271               count = 0;
10272               continue;
10273             }
10274           break;
10275
10276         case NOT:
10277           if (VECTOR_MODE_P (mode))
10278             break;
10279
10280           /* Make this fit the case below.  */
10281           varop = gen_rtx_XOR (mode, XEXP (varop, 0),
10282                                GEN_INT (GET_MODE_MASK (mode)));
10283           continue;
10284
10285         case IOR:
10286         case AND:
10287         case XOR:
10288           /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10289              with C the size of VAROP - 1 and the shift is logical if
10290              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10291              we have an (le X 0) operation.   If we have an arithmetic shift
10292              and STORE_FLAG_VALUE is 1 or we have a logical shift with
10293              STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation.  */
10294
10295           if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10296               && XEXP (XEXP (varop, 0), 1) == constm1_rtx
10297               && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10298               && (code == LSHIFTRT || code == ASHIFTRT)
10299               && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10300               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10301             {
10302               count = 0;
10303               varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
10304                                   const0_rtx);
10305
10306               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10307                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10308
10309               continue;
10310             }
10311
10312           /* If we have (shift (logical)), move the logical to the outside
10313              to allow it to possibly combine with another logical and the
10314              shift to combine with another shift.  This also canonicalizes to
10315              what a ZERO_EXTRACT looks like.  Also, some machines have
10316              (and (shift)) insns.  */
10317
10318           if (CONST_INT_P (XEXP (varop, 1))
10319               /* We can't do this if we have (ashiftrt (xor))  and the
10320                  constant has its sign bit set in shift_mode.  */
10321               && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10322                    && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10323                                               shift_mode))
10324               && (new_rtx = simplify_const_binary_operation (code, result_mode,
10325                                                          XEXP (varop, 1),
10326                                                          GEN_INT (count))) != 0
10327               && CONST_INT_P (new_rtx)
10328               && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
10329                                   INTVAL (new_rtx), result_mode, &complement_p))
10330             {
10331               varop = XEXP (varop, 0);
10332               continue;
10333             }
10334
10335           /* If we can't do that, try to simplify the shift in each arm of the
10336              logical expression, make a new logical expression, and apply
10337              the inverse distributive law.  This also can't be done
10338              for some (ashiftrt (xor)).  */
10339           if (CONST_INT_P (XEXP (varop, 1))
10340              && !(code == ASHIFTRT && GET_CODE (varop) == XOR
10341                   && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
10342                                              shift_mode)))
10343             {
10344               rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10345                                               XEXP (varop, 0), count);
10346               rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
10347                                               XEXP (varop, 1), count);
10348
10349               varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
10350                                            lhs, rhs);
10351               varop = apply_distributive_law (varop);
10352
10353               count = 0;
10354               continue;
10355             }
10356           break;
10357
10358         case EQ:
10359           /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
10360              says that the sign bit can be tested, FOO has mode MODE, C is
10361              GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
10362              that may be nonzero.  */
10363           if (code == LSHIFTRT
10364               && XEXP (varop, 1) == const0_rtx
10365               && GET_MODE (XEXP (varop, 0)) == result_mode
10366               && count == (GET_MODE_PRECISION (result_mode) - 1)
10367               && HWI_COMPUTABLE_MODE_P (result_mode)
10368               && STORE_FLAG_VALUE == -1
10369               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10370               && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10371                                   &complement_p))
10372             {
10373               varop = XEXP (varop, 0);
10374               count = 0;
10375               continue;
10376             }
10377           break;
10378
10379         case NEG:
10380           /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
10381              than the number of bits in the mode is equivalent to A.  */
10382           if (code == LSHIFTRT
10383               && count == (GET_MODE_PRECISION (result_mode) - 1)
10384               && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
10385             {
10386               varop = XEXP (varop, 0);
10387               count = 0;
10388               continue;
10389             }
10390
10391           /* NEG commutes with ASHIFT since it is multiplication.  Move the
10392              NEG outside to allow shifts to combine.  */
10393           if (code == ASHIFT
10394               && merge_outer_ops (&outer_op, &outer_const, NEG, 0, result_mode,
10395                                   &complement_p))
10396             {
10397               varop = XEXP (varop, 0);
10398               continue;
10399             }
10400           break;
10401
10402         case PLUS:
10403           /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
10404              is one less than the number of bits in the mode is
10405              equivalent to (xor A 1).  */
10406           if (code == LSHIFTRT
10407               && count == (GET_MODE_PRECISION (result_mode) - 1)
10408               && XEXP (varop, 1) == constm1_rtx
10409               && nonzero_bits (XEXP (varop, 0), result_mode) == 1
10410               && merge_outer_ops (&outer_op, &outer_const, XOR, 1, result_mode,
10411                                   &complement_p))
10412             {
10413               count = 0;
10414               varop = XEXP (varop, 0);
10415               continue;
10416             }
10417
10418           /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
10419              that might be nonzero in BAR are those being shifted out and those
10420              bits are known zero in FOO, we can replace the PLUS with FOO.
10421              Similarly in the other operand order.  This code occurs when
10422              we are computing the size of a variable-size array.  */
10423
10424           if ((code == ASHIFTRT || code == LSHIFTRT)
10425               && count < HOST_BITS_PER_WIDE_INT
10426               && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
10427               && (nonzero_bits (XEXP (varop, 1), result_mode)
10428                   & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
10429             {
10430               varop = XEXP (varop, 0);
10431               continue;
10432             }
10433           else if ((code == ASHIFTRT || code == LSHIFTRT)
10434                    && count < HOST_BITS_PER_WIDE_INT
10435                    && HWI_COMPUTABLE_MODE_P (result_mode)
10436                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10437                             >> count)
10438                    && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
10439                             & nonzero_bits (XEXP (varop, 1),
10440                                                  result_mode)))
10441             {
10442               varop = XEXP (varop, 1);
10443               continue;
10444             }
10445
10446           /* (ashift (plus foo C) N) is (plus (ashift foo N) C').  */
10447           if (code == ASHIFT
10448               && CONST_INT_P (XEXP (varop, 1))
10449               && (new_rtx = simplify_const_binary_operation (ASHIFT, result_mode,
10450                                                          XEXP (varop, 1),
10451                                                          GEN_INT (count))) != 0
10452               && CONST_INT_P (new_rtx)
10453               && merge_outer_ops (&outer_op, &outer_const, PLUS,
10454                                   INTVAL (new_rtx), result_mode, &complement_p))
10455             {
10456               varop = XEXP (varop, 0);
10457               continue;
10458             }
10459
10460           /* Check for 'PLUS signbit', which is the canonical form of 'XOR
10461              signbit', and attempt to change the PLUS to an XOR and move it to
10462              the outer operation as is done above in the AND/IOR/XOR case
10463              leg for shift(logical). See details in logical handling above
10464              for reasoning in doing so.  */
10465           if (code == LSHIFTRT
10466               && CONST_INT_P (XEXP (varop, 1))
10467               && mode_signbit_p (result_mode, XEXP (varop, 1))
10468               && (new_rtx = simplify_const_binary_operation (code, result_mode,
10469                                                          XEXP (varop, 1),
10470                                                          GEN_INT (count))) != 0
10471               && CONST_INT_P (new_rtx)
10472               && merge_outer_ops (&outer_op, &outer_const, XOR,
10473                                   INTVAL (new_rtx), result_mode, &complement_p))
10474             {
10475               varop = XEXP (varop, 0);
10476               continue;
10477             }
10478
10479           break;
10480
10481         case MINUS:
10482           /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
10483              with C the size of VAROP - 1 and the shift is logical if
10484              STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10485              we have a (gt X 0) operation.  If the shift is arithmetic with
10486              STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
10487              we have a (neg (gt X 0)) operation.  */
10488
10489           if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10490               && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
10491               && count == (GET_MODE_PRECISION (GET_MODE (varop)) - 1)
10492               && (code == LSHIFTRT || code == ASHIFTRT)
10493               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10494               && INTVAL (XEXP (XEXP (varop, 0), 1)) == count
10495               && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10496             {
10497               count = 0;
10498               varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
10499                                   const0_rtx);
10500
10501               if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10502                 varop = gen_rtx_NEG (GET_MODE (varop), varop);
10503
10504               continue;
10505             }
10506           break;
10507
10508         case TRUNCATE:
10509           /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
10510              if the truncate does not affect the value.  */
10511           if (code == LSHIFTRT
10512               && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
10513               && CONST_INT_P (XEXP (XEXP (varop, 0), 1))
10514               && (INTVAL (XEXP (XEXP (varop, 0), 1))
10515                   >= (GET_MODE_PRECISION (GET_MODE (XEXP (varop, 0)))
10516                       - GET_MODE_PRECISION (GET_MODE (varop)))))
10517             {
10518               rtx varop_inner = XEXP (varop, 0);
10519
10520               varop_inner
10521                 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
10522                                     XEXP (varop_inner, 0),
10523                                     GEN_INT
10524                                     (count + INTVAL (XEXP (varop_inner, 1))));
10525               varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
10526               count = 0;
10527               continue;
10528             }
10529           break;
10530
10531         default:
10532           break;
10533         }
10534
10535       break;
10536     }
10537
10538   shift_mode = try_widen_shift_mode (code, varop, count, result_mode, mode,
10539                                      outer_op, outer_const);
10540
10541   /* We have now finished analyzing the shift.  The result should be
10542      a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places.  If
10543      OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
10544      to the result of the shift.  OUTER_CONST is the relevant constant,
10545      but we must turn off all bits turned off in the shift.  */
10546
10547   if (outer_op == UNKNOWN
10548       && orig_code == code && orig_count == count
10549       && varop == orig_varop
10550       && shift_mode == GET_MODE (varop))
10551     return NULL_RTX;
10552
10553   /* Make a SUBREG if necessary.  If we can't make it, fail.  */
10554   varop = gen_lowpart (shift_mode, varop);
10555   if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10556     return NULL_RTX;
10557
10558   /* If we have an outer operation and we just made a shift, it is
10559      possible that we could have simplified the shift were it not
10560      for the outer operation.  So try to do the simplification
10561      recursively.  */
10562
10563   if (outer_op != UNKNOWN)
10564     x = simplify_shift_const_1 (code, shift_mode, varop, count);
10565   else
10566     x = NULL_RTX;
10567
10568   if (x == NULL_RTX)
10569     x = simplify_gen_binary (code, shift_mode, varop, GEN_INT (count));
10570
10571   /* If we were doing an LSHIFTRT in a wider mode than it was originally,
10572      turn off all the bits that the shift would have turned off.  */
10573   if (orig_code == LSHIFTRT && result_mode != shift_mode)
10574     x = simplify_and_const_int (NULL_RTX, shift_mode, x,
10575                                 GET_MODE_MASK (result_mode) >> orig_count);
10576
10577   /* Do the remainder of the processing in RESULT_MODE.  */
10578   x = gen_lowpart_or_truncate (result_mode, x);
10579
10580   /* If COMPLEMENT_P is set, we have to complement X before doing the outer
10581      operation.  */
10582   if (complement_p)
10583     x = simplify_gen_unary (NOT, result_mode, x, result_mode);
10584
10585   if (outer_op != UNKNOWN)
10586     {
10587       if (GET_RTX_CLASS (outer_op) != RTX_UNARY
10588           && GET_MODE_PRECISION (result_mode) < HOST_BITS_PER_WIDE_INT)
10589         outer_const = trunc_int_for_mode (outer_const, result_mode);
10590
10591       if (outer_op == AND)
10592         x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
10593       else if (outer_op == SET)
10594         {
10595           /* This means that we have determined that the result is
10596              equivalent to a constant.  This should be rare.  */
10597           if (!side_effects_p (x))
10598             x = GEN_INT (outer_const);
10599         }
10600       else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
10601         x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
10602       else
10603         x = simplify_gen_binary (outer_op, result_mode, x,
10604                                  GEN_INT (outer_const));
10605     }
10606
10607   return x;
10608 }
10609
10610 /* Simplify a shift of VAROP by COUNT bits.  CODE says what kind of shift.
10611    The result of the shift is RESULT_MODE.  If we cannot simplify it,
10612    return X or, if it is NULL, synthesize the expression with
10613    simplify_gen_binary.  Otherwise, return a simplified value.
10614
10615    The shift is normally computed in the widest mode we find in VAROP, as
10616    long as it isn't a different number of words than RESULT_MODE.  Exceptions
10617    are ASHIFTRT and ROTATE, which are always done in their original mode.  */
10618
10619 static rtx
10620 simplify_shift_const (rtx x, enum rtx_code code, enum machine_mode result_mode,
10621                       rtx varop, int count)
10622 {
10623   rtx tem = simplify_shift_const_1 (code, result_mode, varop, count);
10624   if (tem)
10625     return tem;
10626
10627   if (!x)
10628     x = simplify_gen_binary (code, GET_MODE (varop), varop, GEN_INT (count));
10629   if (GET_MODE (x) != result_mode)
10630     x = gen_lowpart (result_mode, x);
10631   return x;
10632 }
10633
10634 \f
10635 /* Like recog, but we receive the address of a pointer to a new pattern.
10636    We try to match the rtx that the pointer points to.
10637    If that fails, we may try to modify or replace the pattern,
10638    storing the replacement into the same pointer object.
10639
10640    Modifications include deletion or addition of CLOBBERs.
10641
10642    PNOTES is a pointer to a location where any REG_UNUSED notes added for
10643    the CLOBBERs are placed.
10644
10645    The value is the final insn code from the pattern ultimately matched,
10646    or -1.  */
10647
10648 static int
10649 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
10650 {
10651   rtx pat = *pnewpat;
10652   int insn_code_number;
10653   int num_clobbers_to_add = 0;
10654   int i;
10655   rtx notes = 0;
10656   rtx old_notes, old_pat;
10657
10658   /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
10659      we use to indicate that something didn't match.  If we find such a
10660      thing, force rejection.  */
10661   if (GET_CODE (pat) == PARALLEL)
10662     for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
10663       if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
10664           && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
10665         return -1;
10666
10667   old_pat = PATTERN (insn);
10668   old_notes = REG_NOTES (insn);
10669   PATTERN (insn) = pat;
10670   REG_NOTES (insn) = 0;
10671
10672   insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10673   if (dump_file && (dump_flags & TDF_DETAILS))
10674     {
10675       if (insn_code_number < 0)
10676         fputs ("Failed to match this instruction:\n", dump_file);
10677       else
10678         fputs ("Successfully matched this instruction:\n", dump_file);
10679       print_rtl_single (dump_file, pat);
10680     }
10681
10682   /* If it isn't, there is the possibility that we previously had an insn
10683      that clobbered some register as a side effect, but the combined
10684      insn doesn't need to do that.  So try once more without the clobbers
10685      unless this represents an ASM insn.  */
10686
10687   if (insn_code_number < 0 && ! check_asm_operands (pat)
10688       && GET_CODE (pat) == PARALLEL)
10689     {
10690       int pos;
10691
10692       for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
10693         if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
10694           {
10695             if (i != pos)
10696               SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
10697             pos++;
10698           }
10699
10700       SUBST_INT (XVECLEN (pat, 0), pos);
10701
10702       if (pos == 1)
10703         pat = XVECEXP (pat, 0, 0);
10704
10705       PATTERN (insn) = pat;
10706       insn_code_number = recog (pat, insn, &num_clobbers_to_add);
10707       if (dump_file && (dump_flags & TDF_DETAILS))
10708         {
10709           if (insn_code_number < 0)
10710             fputs ("Failed to match this instruction:\n", dump_file);
10711           else
10712             fputs ("Successfully matched this instruction:\n", dump_file);
10713           print_rtl_single (dump_file, pat);
10714         }
10715     }
10716   PATTERN (insn) = old_pat;
10717   REG_NOTES (insn) = old_notes;
10718
10719   /* Recognize all noop sets, these will be killed by followup pass.  */
10720   if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
10721     insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
10722
10723   /* If we had any clobbers to add, make a new pattern than contains
10724      them.  Then check to make sure that all of them are dead.  */
10725   if (num_clobbers_to_add)
10726     {
10727       rtx newpat = gen_rtx_PARALLEL (VOIDmode,
10728                                      rtvec_alloc (GET_CODE (pat) == PARALLEL
10729                                                   ? (XVECLEN (pat, 0)
10730                                                      + num_clobbers_to_add)
10731                                                   : num_clobbers_to_add + 1));
10732
10733       if (GET_CODE (pat) == PARALLEL)
10734         for (i = 0; i < XVECLEN (pat, 0); i++)
10735           XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
10736       else
10737         XVECEXP (newpat, 0, 0) = pat;
10738
10739       add_clobbers (newpat, insn_code_number);
10740
10741       for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
10742            i < XVECLEN (newpat, 0); i++)
10743         {
10744           if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
10745               && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
10746             return -1;
10747           if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
10748             {
10749               gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
10750               notes = alloc_reg_note (REG_UNUSED,
10751                                       XEXP (XVECEXP (newpat, 0, i), 0), notes);
10752             }
10753         }
10754       pat = newpat;
10755     }
10756
10757   *pnewpat = pat;
10758   *pnotes = notes;
10759
10760   return insn_code_number;
10761 }
10762 \f
10763 /* Like gen_lowpart_general but for use by combine.  In combine it
10764    is not possible to create any new pseudoregs.  However, it is
10765    safe to create invalid memory addresses, because combine will
10766    try to recognize them and all they will do is make the combine
10767    attempt fail.
10768
10769    If for some reason this cannot do its job, an rtx
10770    (clobber (const_int 0)) is returned.
10771    An insn containing that will not be recognized.  */
10772
10773 static rtx
10774 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
10775 {
10776   enum machine_mode imode = GET_MODE (x);
10777   unsigned int osize = GET_MODE_SIZE (omode);
10778   unsigned int isize = GET_MODE_SIZE (imode);
10779   rtx result;
10780
10781   if (omode == imode)
10782     return x;
10783
10784   /* Return identity if this is a CONST or symbolic reference.  */
10785   if (omode == Pmode
10786       && (GET_CODE (x) == CONST
10787           || GET_CODE (x) == SYMBOL_REF
10788           || GET_CODE (x) == LABEL_REF))
10789     return x;
10790
10791   /* We can only support MODE being wider than a word if X is a
10792      constant integer or has a mode the same size.  */
10793   if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
10794       && ! ((imode == VOIDmode
10795              && (CONST_INT_P (x)
10796                  || GET_CODE (x) == CONST_DOUBLE))
10797             || isize == osize))
10798     goto fail;
10799
10800   /* X might be a paradoxical (subreg (mem)).  In that case, gen_lowpart
10801      won't know what to do.  So we will strip off the SUBREG here and
10802      process normally.  */
10803   if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
10804     {
10805       x = SUBREG_REG (x);
10806
10807       /* For use in case we fall down into the address adjustments
10808          further below, we need to adjust the known mode and size of
10809          x; imode and isize, since we just adjusted x.  */
10810       imode = GET_MODE (x);
10811
10812       if (imode == omode)
10813         return x;
10814
10815       isize = GET_MODE_SIZE (imode);
10816     }
10817
10818   result = gen_lowpart_common (omode, x);
10819
10820   if (result)
10821     return result;
10822
10823   if (MEM_P (x))
10824     {
10825       int offset = 0;
10826
10827       /* Refuse to work on a volatile memory ref or one with a mode-dependent
10828          address.  */
10829       if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
10830         goto fail;
10831
10832       /* If we want to refer to something bigger than the original memref,
10833          generate a paradoxical subreg instead.  That will force a reload
10834          of the original memref X.  */
10835       if (isize < osize)
10836         return gen_rtx_SUBREG (omode, x, 0);
10837
10838       if (WORDS_BIG_ENDIAN)
10839         offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
10840
10841       /* Adjust the address so that the address-after-the-data is
10842          unchanged.  */
10843       if (BYTES_BIG_ENDIAN)
10844         offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
10845
10846       return adjust_address_nv (x, omode, offset);
10847     }
10848
10849   /* If X is a comparison operator, rewrite it in a new mode.  This
10850      probably won't match, but may allow further simplifications.  */
10851   else if (COMPARISON_P (x))
10852     return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
10853
10854   /* If we couldn't simplify X any other way, just enclose it in a
10855      SUBREG.  Normally, this SUBREG won't match, but some patterns may
10856      include an explicit SUBREG or we may simplify it further in combine.  */
10857   else
10858     {
10859       int offset = 0;
10860       rtx res;
10861
10862       offset = subreg_lowpart_offset (omode, imode);
10863       if (imode == VOIDmode)
10864         {
10865           imode = int_mode_for_mode (omode);
10866           x = gen_lowpart_common (imode, x);
10867           if (x == NULL)
10868             goto fail;
10869         }
10870       res = simplify_gen_subreg (omode, x, imode, offset);
10871       if (res)
10872         return res;
10873     }
10874
10875  fail:
10876   return gen_rtx_CLOBBER (omode, const0_rtx);
10877 }
10878 \f
10879 /* Try to simplify a comparison between OP0 and a constant OP1,
10880    where CODE is the comparison code that will be tested, into a
10881    (CODE OP0 const0_rtx) form.
10882
10883    The result is a possibly different comparison code to use.
10884    *POP1 may be updated.  */
10885
10886 static enum rtx_code
10887 simplify_compare_const (enum rtx_code code, rtx op0, rtx *pop1)
10888 {
10889   enum machine_mode mode = GET_MODE (op0);
10890   unsigned int mode_width = GET_MODE_PRECISION (mode);
10891   HOST_WIDE_INT const_op = INTVAL (*pop1);
10892
10893   /* Get the constant we are comparing against and turn off all bits
10894      not on in our mode.  */
10895   if (mode != VOIDmode)
10896     const_op = trunc_int_for_mode (const_op, mode);
10897
10898   /* If we are comparing against a constant power of two and the value
10899      being compared can only have that single bit nonzero (e.g., it was
10900      `and'ed with that bit), we can replace this with a comparison
10901      with zero.  */
10902   if (const_op
10903       && (code == EQ || code == NE || code == GE || code == GEU
10904           || code == LT || code == LTU)
10905       && mode_width <= HOST_BITS_PER_WIDE_INT
10906       && exact_log2 (const_op) >= 0
10907       && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
10908     {
10909       code = (code == EQ || code == GE || code == GEU ? NE : EQ);
10910       const_op = 0;
10911     }
10912
10913   /* Similarly, if we are comparing a value known to be either -1 or
10914      0 with -1, change it to the opposite comparison against zero.  */
10915   if (const_op == -1
10916       && (code == EQ || code == NE || code == GT || code == LE
10917           || code == GEU || code == LTU)
10918       && num_sign_bit_copies (op0, mode) == mode_width)
10919     {
10920       code = (code == EQ || code == LE || code == GEU ? NE : EQ);
10921       const_op = 0;
10922     }
10923
10924   /* Do some canonicalizations based on the comparison code.  We prefer
10925      comparisons against zero and then prefer equality comparisons.
10926      If we can reduce the size of a constant, we will do that too.  */
10927   switch (code)
10928     {
10929     case LT:
10930       /* < C is equivalent to <= (C - 1) */
10931       if (const_op > 0)
10932         {
10933           const_op -= 1;
10934           code = LE;
10935           /* ... fall through to LE case below.  */
10936         }
10937       else
10938         break;
10939
10940     case LE:
10941       /* <= C is equivalent to < (C + 1); we do this for C < 0  */
10942       if (const_op < 0)
10943         {
10944           const_op += 1;
10945           code = LT;
10946         }
10947
10948       /* If we are doing a <= 0 comparison on a value known to have
10949          a zero sign bit, we can replace this with == 0.  */
10950       else if (const_op == 0
10951                && mode_width <= HOST_BITS_PER_WIDE_INT
10952                && (nonzero_bits (op0, mode)
10953                    & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10954                == 0)
10955         code = EQ;
10956       break;
10957
10958     case GE:
10959       /* >= C is equivalent to > (C - 1).  */
10960       if (const_op > 0)
10961         {
10962           const_op -= 1;
10963           code = GT;
10964           /* ... fall through to GT below.  */
10965         }
10966       else
10967         break;
10968
10969     case GT:
10970       /* > C is equivalent to >= (C + 1); we do this for C < 0.  */
10971       if (const_op < 0)
10972         {
10973           const_op += 1;
10974           code = GE;
10975         }
10976
10977       /* If we are doing a > 0 comparison on a value known to have
10978          a zero sign bit, we can replace this with != 0.  */
10979       else if (const_op == 0
10980                && mode_width <= HOST_BITS_PER_WIDE_INT
10981                && (nonzero_bits (op0, mode)
10982                    & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10983                == 0)
10984         code = NE;
10985       break;
10986
10987     case LTU:
10988       /* < C is equivalent to <= (C - 1).  */
10989       if (const_op > 0)
10990         {
10991           const_op -= 1;
10992           code = LEU;
10993           /* ... fall through ...  */
10994         }
10995       /* (unsigned) < 0x80000000 is equivalent to >= 0.  */
10996       else if (mode_width <= HOST_BITS_PER_WIDE_INT
10997                && (unsigned HOST_WIDE_INT) const_op
10998                == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
10999         {
11000           const_op = 0;
11001           code = GE;
11002           break;
11003         }
11004       else
11005         break;
11006
11007     case LEU:
11008       /* unsigned <= 0 is equivalent to == 0 */
11009       if (const_op == 0)
11010         code = EQ;
11011       /* (unsigned) <= 0x7fffffff is equivalent to >= 0.  */
11012       else if (mode_width <= HOST_BITS_PER_WIDE_INT
11013                && (unsigned HOST_WIDE_INT) const_op
11014                == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11015         {
11016           const_op = 0;
11017           code = GE;
11018         }
11019       break;
11020
11021     case GEU:
11022       /* >= C is equivalent to > (C - 1).  */
11023       if (const_op > 1)
11024         {
11025           const_op -= 1;
11026           code = GTU;
11027           /* ... fall through ...  */
11028         }
11029
11030       /* (unsigned) >= 0x80000000 is equivalent to < 0.  */
11031       else if (mode_width <= HOST_BITS_PER_WIDE_INT
11032                && (unsigned HOST_WIDE_INT) const_op
11033                == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1))
11034         {
11035           const_op = 0;
11036           code = LT;
11037           break;
11038         }
11039       else
11040         break;
11041
11042     case GTU:
11043       /* unsigned > 0 is equivalent to != 0 */
11044       if (const_op == 0)
11045         code = NE;
11046       /* (unsigned) > 0x7fffffff is equivalent to < 0.  */
11047       else if (mode_width <= HOST_BITS_PER_WIDE_INT
11048                && (unsigned HOST_WIDE_INT) const_op
11049                == ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)) - 1)
11050         {
11051           const_op = 0;
11052           code = LT;
11053         }
11054       break;
11055
11056     default:
11057       break;
11058     }
11059
11060   *pop1 = GEN_INT (const_op);
11061   return code;
11062 }
11063 \f
11064 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
11065    comparison code that will be tested.
11066
11067    The result is a possibly different comparison code to use.  *POP0 and
11068    *POP1 may be updated.
11069
11070    It is possible that we might detect that a comparison is either always
11071    true or always false.  However, we do not perform general constant
11072    folding in combine, so this knowledge isn't useful.  Such tautologies
11073    should have been detected earlier.  Hence we ignore all such cases.  */
11074
11075 static enum rtx_code
11076 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
11077 {
11078   rtx op0 = *pop0;
11079   rtx op1 = *pop1;
11080   rtx tem, tem1;
11081   int i;
11082   enum machine_mode mode, tmode;
11083
11084   /* Try a few ways of applying the same transformation to both operands.  */
11085   while (1)
11086     {
11087 #ifndef WORD_REGISTER_OPERATIONS
11088       /* The test below this one won't handle SIGN_EXTENDs on these machines,
11089          so check specially.  */
11090       if (code != GTU && code != GEU && code != LTU && code != LEU
11091           && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
11092           && GET_CODE (XEXP (op0, 0)) == ASHIFT
11093           && GET_CODE (XEXP (op1, 0)) == ASHIFT
11094           && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
11095           && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
11096           && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
11097               == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
11098           && CONST_INT_P (XEXP (op0, 1))
11099           && XEXP (op0, 1) == XEXP (op1, 1)
11100           && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11101           && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
11102           && (INTVAL (XEXP (op0, 1))
11103               == (GET_MODE_PRECISION (GET_MODE (op0))
11104                   - (GET_MODE_PRECISION
11105                      (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
11106         {
11107           op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
11108           op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
11109         }
11110 #endif
11111
11112       /* If both operands are the same constant shift, see if we can ignore the
11113          shift.  We can if the shift is a rotate or if the bits shifted out of
11114          this shift are known to be zero for both inputs and if the type of
11115          comparison is compatible with the shift.  */
11116       if (GET_CODE (op0) == GET_CODE (op1)
11117           && HWI_COMPUTABLE_MODE_P (GET_MODE(op0))
11118           && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
11119               || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
11120                   && (code != GT && code != LT && code != GE && code != LE))
11121               || (GET_CODE (op0) == ASHIFTRT
11122                   && (code != GTU && code != LTU
11123                       && code != GEU && code != LEU)))
11124           && CONST_INT_P (XEXP (op0, 1))
11125           && INTVAL (XEXP (op0, 1)) >= 0
11126           && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11127           && XEXP (op0, 1) == XEXP (op1, 1))
11128         {
11129           enum machine_mode mode = GET_MODE (op0);
11130           unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11131           int shift_count = INTVAL (XEXP (op0, 1));
11132
11133           if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
11134             mask &= (mask >> shift_count) << shift_count;
11135           else if (GET_CODE (op0) == ASHIFT)
11136             mask = (mask & (mask << shift_count)) >> shift_count;
11137
11138           if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
11139               && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
11140             op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
11141           else
11142             break;
11143         }
11144
11145       /* If both operands are AND's of a paradoxical SUBREG by constant, the
11146          SUBREGs are of the same mode, and, in both cases, the AND would
11147          be redundant if the comparison was done in the narrower mode,
11148          do the comparison in the narrower mode (e.g., we are AND'ing with 1
11149          and the operand's possibly nonzero bits are 0xffffff01; in that case
11150          if we only care about QImode, we don't need the AND).  This case
11151          occurs if the output mode of an scc insn is not SImode and
11152          STORE_FLAG_VALUE == 1 (e.g., the 386).
11153
11154          Similarly, check for a case where the AND's are ZERO_EXTEND
11155          operations from some narrower mode even though a SUBREG is not
11156          present.  */
11157
11158       else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
11159                && CONST_INT_P (XEXP (op0, 1))
11160                && CONST_INT_P (XEXP (op1, 1)))
11161         {
11162           rtx inner_op0 = XEXP (op0, 0);
11163           rtx inner_op1 = XEXP (op1, 0);
11164           HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
11165           HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
11166           int changed = 0;
11167
11168           if (paradoxical_subreg_p (inner_op0)
11169               && GET_CODE (inner_op1) == SUBREG
11170               && (GET_MODE (SUBREG_REG (inner_op0))
11171                   == GET_MODE (SUBREG_REG (inner_op1)))
11172               && (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (inner_op0)))
11173                   <= HOST_BITS_PER_WIDE_INT)
11174               && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
11175                                              GET_MODE (SUBREG_REG (inner_op0)))))
11176               && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
11177                                              GET_MODE (SUBREG_REG (inner_op1))))))
11178             {
11179               op0 = SUBREG_REG (inner_op0);
11180               op1 = SUBREG_REG (inner_op1);
11181
11182               /* The resulting comparison is always unsigned since we masked
11183                  off the original sign bit.  */
11184               code = unsigned_condition (code);
11185
11186               changed = 1;
11187             }
11188
11189           else if (c0 == c1)
11190             for (tmode = GET_CLASS_NARROWEST_MODE
11191                  (GET_MODE_CLASS (GET_MODE (op0)));
11192                  tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
11193               if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
11194                 {
11195                   op0 = gen_lowpart (tmode, inner_op0);
11196                   op1 = gen_lowpart (tmode, inner_op1);
11197                   code = unsigned_condition (code);
11198                   changed = 1;
11199                   break;
11200                 }
11201
11202           if (! changed)
11203             break;
11204         }
11205
11206       /* If both operands are NOT, we can strip off the outer operation
11207          and adjust the comparison code for swapped operands; similarly for
11208          NEG, except that this must be an equality comparison.  */
11209       else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
11210                || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
11211                    && (code == EQ || code == NE)))
11212         op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
11213
11214       else
11215         break;
11216     }
11217
11218   /* If the first operand is a constant, swap the operands and adjust the
11219      comparison code appropriately, but don't do this if the second operand
11220      is already a constant integer.  */
11221   if (swap_commutative_operands_p (op0, op1))
11222     {
11223       tem = op0, op0 = op1, op1 = tem;
11224       code = swap_condition (code);
11225     }
11226
11227   /* We now enter a loop during which we will try to simplify the comparison.
11228      For the most part, we only are concerned with comparisons with zero,
11229      but some things may really be comparisons with zero but not start
11230      out looking that way.  */
11231
11232   while (CONST_INT_P (op1))
11233     {
11234       enum machine_mode mode = GET_MODE (op0);
11235       unsigned int mode_width = GET_MODE_PRECISION (mode);
11236       unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
11237       int equality_comparison_p;
11238       int sign_bit_comparison_p;
11239       int unsigned_comparison_p;
11240       HOST_WIDE_INT const_op;
11241
11242       /* We only want to handle integral modes.  This catches VOIDmode,
11243          CCmode, and the floating-point modes.  An exception is that we
11244          can handle VOIDmode if OP0 is a COMPARE or a comparison
11245          operation.  */
11246
11247       if (GET_MODE_CLASS (mode) != MODE_INT
11248           && ! (mode == VOIDmode
11249                 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
11250         break;
11251
11252       /* Try to simplify the compare to constant, possibly changing the
11253          comparison op, and/or changing op1 to zero.  */
11254       code = simplify_compare_const (code, op0, &op1);
11255       const_op = INTVAL (op1);
11256
11257       /* Compute some predicates to simplify code below.  */
11258
11259       equality_comparison_p = (code == EQ || code == NE);
11260       sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
11261       unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
11262                                || code == GEU);
11263
11264       /* If this is a sign bit comparison and we can do arithmetic in
11265          MODE, say that we will only be needing the sign bit of OP0.  */
11266       if (sign_bit_comparison_p && HWI_COMPUTABLE_MODE_P (mode))
11267         op0 = force_to_mode (op0, mode,
11268                              (unsigned HOST_WIDE_INT) 1
11269                              << (GET_MODE_PRECISION (mode) - 1),
11270                              0);
11271
11272       /* Now try cases based on the opcode of OP0.  If none of the cases
11273          does a "continue", we exit this loop immediately after the
11274          switch.  */
11275
11276       switch (GET_CODE (op0))
11277         {
11278         case ZERO_EXTRACT:
11279           /* If we are extracting a single bit from a variable position in
11280              a constant that has only a single bit set and are comparing it
11281              with zero, we can convert this into an equality comparison
11282              between the position and the location of the single bit.  */
11283           /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
11284              have already reduced the shift count modulo the word size.  */
11285           if (!SHIFT_COUNT_TRUNCATED
11286               && CONST_INT_P (XEXP (op0, 0))
11287               && XEXP (op0, 1) == const1_rtx
11288               && equality_comparison_p && const_op == 0
11289               && (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
11290             {
11291               if (BITS_BIG_ENDIAN)
11292                 {
11293                   enum machine_mode new_mode
11294                     = mode_for_extraction (EP_extzv, 1);
11295                   if (new_mode == MAX_MACHINE_MODE)
11296                     i = BITS_PER_WORD - 1 - i;
11297                   else
11298                     {
11299                       mode = new_mode;
11300                       i = (GET_MODE_PRECISION (mode) - 1 - i);
11301                     }
11302                 }
11303
11304               op0 = XEXP (op0, 2);
11305               op1 = GEN_INT (i);
11306               const_op = i;
11307
11308               /* Result is nonzero iff shift count is equal to I.  */
11309               code = reverse_condition (code);
11310               continue;
11311             }
11312
11313           /* ... fall through ...  */
11314
11315         case SIGN_EXTRACT:
11316           tem = expand_compound_operation (op0);
11317           if (tem != op0)
11318             {
11319               op0 = tem;
11320               continue;
11321             }
11322           break;
11323
11324         case NOT:
11325           /* If testing for equality, we can take the NOT of the constant.  */
11326           if (equality_comparison_p
11327               && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
11328             {
11329               op0 = XEXP (op0, 0);
11330               op1 = tem;
11331               continue;
11332             }
11333
11334           /* If just looking at the sign bit, reverse the sense of the
11335              comparison.  */
11336           if (sign_bit_comparison_p)
11337             {
11338               op0 = XEXP (op0, 0);
11339               code = (code == GE ? LT : GE);
11340               continue;
11341             }
11342           break;
11343
11344         case NEG:
11345           /* If testing for equality, we can take the NEG of the constant.  */
11346           if (equality_comparison_p
11347               && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
11348             {
11349               op0 = XEXP (op0, 0);
11350               op1 = tem;
11351               continue;
11352             }
11353
11354           /* The remaining cases only apply to comparisons with zero.  */
11355           if (const_op != 0)
11356             break;
11357
11358           /* When X is ABS or is known positive,
11359              (neg X) is < 0 if and only if X != 0.  */
11360
11361           if (sign_bit_comparison_p
11362               && (GET_CODE (XEXP (op0, 0)) == ABS
11363                   || (mode_width <= HOST_BITS_PER_WIDE_INT
11364                       && (nonzero_bits (XEXP (op0, 0), mode)
11365                           & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11366                          == 0)))
11367             {
11368               op0 = XEXP (op0, 0);
11369               code = (code == LT ? NE : EQ);
11370               continue;
11371             }
11372
11373           /* If we have NEG of something whose two high-order bits are the
11374              same, we know that "(-a) < 0" is equivalent to "a > 0".  */
11375           if (num_sign_bit_copies (op0, mode) >= 2)
11376             {
11377               op0 = XEXP (op0, 0);
11378               code = swap_condition (code);
11379               continue;
11380             }
11381           break;
11382
11383         case ROTATE:
11384           /* If we are testing equality and our count is a constant, we
11385              can perform the inverse operation on our RHS.  */
11386           if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
11387               && (tem = simplify_binary_operation (ROTATERT, mode,
11388                                                    op1, XEXP (op0, 1))) != 0)
11389             {
11390               op0 = XEXP (op0, 0);
11391               op1 = tem;
11392               continue;
11393             }
11394
11395           /* If we are doing a < 0 or >= 0 comparison, it means we are testing
11396              a particular bit.  Convert it to an AND of a constant of that
11397              bit.  This will be converted into a ZERO_EXTRACT.  */
11398           if (const_op == 0 && sign_bit_comparison_p
11399               && CONST_INT_P (XEXP (op0, 1))
11400               && mode_width <= HOST_BITS_PER_WIDE_INT)
11401             {
11402               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11403                                             ((unsigned HOST_WIDE_INT) 1
11404                                              << (mode_width - 1
11405                                                  - INTVAL (XEXP (op0, 1)))));
11406               code = (code == LT ? NE : EQ);
11407               continue;
11408             }
11409
11410           /* Fall through.  */
11411
11412         case ABS:
11413           /* ABS is ignorable inside an equality comparison with zero.  */
11414           if (const_op == 0 && equality_comparison_p)
11415             {
11416               op0 = XEXP (op0, 0);
11417               continue;
11418             }
11419           break;
11420
11421         case SIGN_EXTEND:
11422           /* Can simplify (compare (zero/sign_extend FOO) CONST) to
11423              (compare FOO CONST) if CONST fits in FOO's mode and we
11424              are either testing inequality or have an unsigned
11425              comparison with ZERO_EXTEND or a signed comparison with
11426              SIGN_EXTEND.  But don't do it if we don't have a compare
11427              insn of the given mode, since we'd have to revert it
11428              later on, and then we wouldn't know whether to sign- or
11429              zero-extend.  */
11430           mode = GET_MODE (XEXP (op0, 0));
11431           if (GET_MODE_CLASS (mode) == MODE_INT
11432               && ! unsigned_comparison_p
11433               && HWI_COMPUTABLE_MODE_P (mode)
11434               && trunc_int_for_mode (const_op, mode) == const_op
11435               && have_insn_for (COMPARE, mode))
11436             {
11437               op0 = XEXP (op0, 0);
11438               continue;
11439             }
11440           break;
11441
11442         case SUBREG:
11443           /* Check for the case where we are comparing A - C1 with C2, that is
11444
11445                (subreg:MODE (plus (A) (-C1))) op (C2)
11446
11447              with C1 a constant, and try to lift the SUBREG, i.e. to do the
11448              comparison in the wider mode.  One of the following two conditions
11449              must be true in order for this to be valid:
11450
11451                1. The mode extension results in the same bit pattern being added
11452                   on both sides and the comparison is equality or unsigned.  As
11453                   C2 has been truncated to fit in MODE, the pattern can only be
11454                   all 0s or all 1s.
11455
11456                2. The mode extension results in the sign bit being copied on
11457                   each side.
11458
11459              The difficulty here is that we have predicates for A but not for
11460              (A - C1) so we need to check that C1 is within proper bounds so
11461              as to perturbate A as little as possible.  */
11462
11463           if (mode_width <= HOST_BITS_PER_WIDE_INT
11464               && subreg_lowpart_p (op0)
11465               && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) > mode_width
11466               && GET_CODE (SUBREG_REG (op0)) == PLUS
11467               && CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
11468             {
11469               enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
11470               rtx a = XEXP (SUBREG_REG (op0), 0);
11471               HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
11472
11473               if ((c1 > 0
11474                    && (unsigned HOST_WIDE_INT) c1
11475                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
11476                    && (equality_comparison_p || unsigned_comparison_p)
11477                    /* (A - C1) zero-extends if it is positive and sign-extends
11478                       if it is negative, C2 both zero- and sign-extends.  */
11479                    && ((0 == (nonzero_bits (a, inner_mode)
11480                               & ~GET_MODE_MASK (mode))
11481                         && const_op >= 0)
11482                        /* (A - C1) sign-extends if it is positive and 1-extends
11483                           if it is negative, C2 both sign- and 1-extends.  */
11484                        || (num_sign_bit_copies (a, inner_mode)
11485                            > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11486                                              - mode_width)
11487                            && const_op < 0)))
11488                   || ((unsigned HOST_WIDE_INT) c1
11489                        < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
11490                       /* (A - C1) always sign-extends, like C2.  */
11491                       && num_sign_bit_copies (a, inner_mode)
11492                          > (unsigned int) (GET_MODE_PRECISION (inner_mode)
11493                                            - (mode_width - 1))))
11494                 {
11495                   op0 = SUBREG_REG (op0);
11496                   continue;
11497                 }
11498             }
11499
11500           /* If the inner mode is narrower and we are extracting the low part,
11501              we can treat the SUBREG as if it were a ZERO_EXTEND.  */
11502           if (subreg_lowpart_p (op0)
11503               && GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0))) < mode_width)
11504             /* Fall through */ ;
11505           else
11506             break;
11507
11508           /* ... fall through ...  */
11509
11510         case ZERO_EXTEND:
11511           mode = GET_MODE (XEXP (op0, 0));
11512           if (GET_MODE_CLASS (mode) == MODE_INT
11513               && (unsigned_comparison_p || equality_comparison_p)
11514               && HWI_COMPUTABLE_MODE_P (mode)
11515               && (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
11516               && const_op >= 0
11517               && have_insn_for (COMPARE, mode))
11518             {
11519               op0 = XEXP (op0, 0);
11520               continue;
11521             }
11522           break;
11523
11524         case PLUS:
11525           /* (eq (plus X A) B) -> (eq X (minus B A)).  We can only do
11526              this for equality comparisons due to pathological cases involving
11527              overflows.  */
11528           if (equality_comparison_p
11529               && 0 != (tem = simplify_binary_operation (MINUS, mode,
11530                                                         op1, XEXP (op0, 1))))
11531             {
11532               op0 = XEXP (op0, 0);
11533               op1 = tem;
11534               continue;
11535             }
11536
11537           /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0.  */
11538           if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
11539               && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
11540             {
11541               op0 = XEXP (XEXP (op0, 0), 0);
11542               code = (code == LT ? EQ : NE);
11543               continue;
11544             }
11545           break;
11546
11547         case MINUS:
11548           /* We used to optimize signed comparisons against zero, but that
11549              was incorrect.  Unsigned comparisons against zero (GTU, LEU)
11550              arrive here as equality comparisons, or (GEU, LTU) are
11551              optimized away.  No need to special-case them.  */
11552
11553           /* (eq (minus A B) C) -> (eq A (plus B C)) or
11554              (eq B (minus A C)), whichever simplifies.  We can only do
11555              this for equality comparisons due to pathological cases involving
11556              overflows.  */
11557           if (equality_comparison_p
11558               && 0 != (tem = simplify_binary_operation (PLUS, mode,
11559                                                         XEXP (op0, 1), op1)))
11560             {
11561               op0 = XEXP (op0, 0);
11562               op1 = tem;
11563               continue;
11564             }
11565
11566           if (equality_comparison_p
11567               && 0 != (tem = simplify_binary_operation (MINUS, mode,
11568                                                         XEXP (op0, 0), op1)))
11569             {
11570               op0 = XEXP (op0, 1);
11571               op1 = tem;
11572               continue;
11573             }
11574
11575           /* The sign bit of (minus (ashiftrt X C) X), where C is the number
11576              of bits in X minus 1, is one iff X > 0.  */
11577           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
11578               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11579               && UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
11580               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11581             {
11582               op0 = XEXP (op0, 1);
11583               code = (code == GE ? LE : GT);
11584               continue;
11585             }
11586           break;
11587
11588         case XOR:
11589           /* (eq (xor A B) C) -> (eq A (xor B C)).  This is a simplification
11590              if C is zero or B is a constant.  */
11591           if (equality_comparison_p
11592               && 0 != (tem = simplify_binary_operation (XOR, mode,
11593                                                         XEXP (op0, 1), op1)))
11594             {
11595               op0 = XEXP (op0, 0);
11596               op1 = tem;
11597               continue;
11598             }
11599           break;
11600
11601         case EQ:  case NE:
11602         case UNEQ:  case LTGT:
11603         case LT:  case LTU:  case UNLT:  case LE:  case LEU:  case UNLE:
11604         case GT:  case GTU:  case UNGT:  case GE:  case GEU:  case UNGE:
11605         case UNORDERED: case ORDERED:
11606           /* We can't do anything if OP0 is a condition code value, rather
11607              than an actual data value.  */
11608           if (const_op != 0
11609               || CC0_P (XEXP (op0, 0))
11610               || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
11611             break;
11612
11613           /* Get the two operands being compared.  */
11614           if (GET_CODE (XEXP (op0, 0)) == COMPARE)
11615             tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
11616           else
11617             tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
11618
11619           /* Check for the cases where we simply want the result of the
11620              earlier test or the opposite of that result.  */
11621           if (code == NE || code == EQ
11622               || (val_signbit_known_set_p (GET_MODE (op0), STORE_FLAG_VALUE)
11623                   && (code == LT || code == GE)))
11624             {
11625               enum rtx_code new_code;
11626               if (code == LT || code == NE)
11627                 new_code = GET_CODE (op0);
11628               else
11629                 new_code = reversed_comparison_code (op0, NULL);
11630
11631               if (new_code != UNKNOWN)
11632                 {
11633                   code = new_code;
11634                   op0 = tem;
11635                   op1 = tem1;
11636                   continue;
11637                 }
11638             }
11639           break;
11640
11641         case IOR:
11642           /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
11643              iff X <= 0.  */
11644           if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
11645               && XEXP (XEXP (op0, 0), 1) == constm1_rtx
11646               && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
11647             {
11648               op0 = XEXP (op0, 1);
11649               code = (code == GE ? GT : LE);
11650               continue;
11651             }
11652           break;
11653
11654         case AND:
11655           /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1).  This
11656              will be converted to a ZERO_EXTRACT later.  */
11657           if (const_op == 0 && equality_comparison_p
11658               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11659               && XEXP (XEXP (op0, 0), 0) == const1_rtx)
11660             {
11661               op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
11662                                       XEXP (XEXP (op0, 0), 1));
11663               op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11664               continue;
11665             }
11666
11667           /* If we are comparing (and (lshiftrt X C1) C2) for equality with
11668              zero and X is a comparison and C1 and C2 describe only bits set
11669              in STORE_FLAG_VALUE, we can compare with X.  */
11670           if (const_op == 0 && equality_comparison_p
11671               && mode_width <= HOST_BITS_PER_WIDE_INT
11672               && CONST_INT_P (XEXP (op0, 1))
11673               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
11674               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11675               && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
11676               && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
11677             {
11678               mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11679                       << INTVAL (XEXP (XEXP (op0, 0), 1)));
11680               if ((~STORE_FLAG_VALUE & mask) == 0
11681                   && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
11682                       || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
11683                           && COMPARISON_P (tem))))
11684                 {
11685                   op0 = XEXP (XEXP (op0, 0), 0);
11686                   continue;
11687                 }
11688             }
11689
11690           /* If we are doing an equality comparison of an AND of a bit equal
11691              to the sign bit, replace this with a LT or GE comparison of
11692              the underlying value.  */
11693           if (equality_comparison_p
11694               && const_op == 0
11695               && CONST_INT_P (XEXP (op0, 1))
11696               && mode_width <= HOST_BITS_PER_WIDE_INT
11697               && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
11698                   == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
11699             {
11700               op0 = XEXP (op0, 0);
11701               code = (code == EQ ? GE : LT);
11702               continue;
11703             }
11704
11705           /* If this AND operation is really a ZERO_EXTEND from a narrower
11706              mode, the constant fits within that mode, and this is either an
11707              equality or unsigned comparison, try to do this comparison in
11708              the narrower mode.
11709
11710              Note that in:
11711
11712              (ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
11713              -> (ne:DI (reg:SI 4) (const_int 0))
11714
11715              unless TRULY_NOOP_TRUNCATION allows it or the register is
11716              known to hold a value of the required mode the
11717              transformation is invalid.  */
11718           if ((equality_comparison_p || unsigned_comparison_p)
11719               && CONST_INT_P (XEXP (op0, 1))
11720               && (i = exact_log2 ((UINTVAL (XEXP (op0, 1))
11721                                    & GET_MODE_MASK (mode))
11722                                   + 1)) >= 0
11723               && const_op >> i == 0
11724               && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode
11725               && (TRULY_NOOP_TRUNCATION_MODES_P (tmode, GET_MODE (op0))
11726                   || (REG_P (XEXP (op0, 0))
11727                       && reg_truncated_to_mode (tmode, XEXP (op0, 0)))))
11728             {
11729               op0 = gen_lowpart (tmode, XEXP (op0, 0));
11730               continue;
11731             }
11732
11733           /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
11734              fits in both M1 and M2 and the SUBREG is either paradoxical
11735              or represents the low part, permute the SUBREG and the AND
11736              and try again.  */
11737           if (GET_CODE (XEXP (op0, 0)) == SUBREG)
11738             {
11739               unsigned HOST_WIDE_INT c1;
11740               tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
11741               /* Require an integral mode, to avoid creating something like
11742                  (AND:SF ...).  */
11743               if (SCALAR_INT_MODE_P (tmode)
11744                   /* It is unsafe to commute the AND into the SUBREG if the
11745                      SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
11746                      not defined.  As originally written the upper bits
11747                      have a defined value due to the AND operation.
11748                      However, if we commute the AND inside the SUBREG then
11749                      they no longer have defined values and the meaning of
11750                      the code has been changed.  */
11751                   && (0
11752 #ifdef WORD_REGISTER_OPERATIONS
11753                       || (mode_width > GET_MODE_PRECISION (tmode)
11754                           && mode_width <= BITS_PER_WORD)
11755 #endif
11756                       || (mode_width <= GET_MODE_PRECISION (tmode)
11757                           && subreg_lowpart_p (XEXP (op0, 0))))
11758                   && CONST_INT_P (XEXP (op0, 1))
11759                   && mode_width <= HOST_BITS_PER_WIDE_INT
11760                   && HWI_COMPUTABLE_MODE_P (tmode)
11761                   && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
11762                   && (c1 & ~GET_MODE_MASK (tmode)) == 0
11763                   && c1 != mask
11764                   && c1 != GET_MODE_MASK (tmode))
11765                 {
11766                   op0 = simplify_gen_binary (AND, tmode,
11767                                              SUBREG_REG (XEXP (op0, 0)),
11768                                              gen_int_mode (c1, tmode));
11769                   op0 = gen_lowpart (mode, op0);
11770                   continue;
11771                 }
11772             }
11773
11774           /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0).  */
11775           if (const_op == 0 && equality_comparison_p
11776               && XEXP (op0, 1) == const1_rtx
11777               && GET_CODE (XEXP (op0, 0)) == NOT)
11778             {
11779               op0 = simplify_and_const_int (NULL_RTX, mode,
11780                                             XEXP (XEXP (op0, 0), 0), 1);
11781               code = (code == NE ? EQ : NE);
11782               continue;
11783             }
11784
11785           /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
11786              (eq (and (lshiftrt X) 1) 0).
11787              Also handle the case where (not X) is expressed using xor.  */
11788           if (const_op == 0 && equality_comparison_p
11789               && XEXP (op0, 1) == const1_rtx
11790               && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
11791             {
11792               rtx shift_op = XEXP (XEXP (op0, 0), 0);
11793               rtx shift_count = XEXP (XEXP (op0, 0), 1);
11794
11795               if (GET_CODE (shift_op) == NOT
11796                   || (GET_CODE (shift_op) == XOR
11797                       && CONST_INT_P (XEXP (shift_op, 1))
11798                       && CONST_INT_P (shift_count)
11799                       && HWI_COMPUTABLE_MODE_P (mode)
11800                       && (UINTVAL (XEXP (shift_op, 1))
11801                           == (unsigned HOST_WIDE_INT) 1
11802                                << INTVAL (shift_count))))
11803                 {
11804                   op0
11805                     = gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
11806                   op0 = simplify_and_const_int (NULL_RTX, mode, op0, 1);
11807                   code = (code == NE ? EQ : NE);
11808                   continue;
11809                 }
11810             }
11811           break;
11812
11813         case ASHIFT:
11814           /* If we have (compare (ashift FOO N) (const_int C)) and
11815              the high order N bits of FOO (N+1 if an inequality comparison)
11816              are known to be zero, we can do this by comparing FOO with C
11817              shifted right N bits so long as the low-order N bits of C are
11818              zero.  */
11819           if (CONST_INT_P (XEXP (op0, 1))
11820               && INTVAL (XEXP (op0, 1)) >= 0
11821               && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
11822                   < HOST_BITS_PER_WIDE_INT)
11823               && (((unsigned HOST_WIDE_INT) const_op
11824                    & (((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1)))
11825                       - 1)) == 0)
11826               && mode_width <= HOST_BITS_PER_WIDE_INT
11827               && (nonzero_bits (XEXP (op0, 0), mode)
11828                   & ~(mask >> (INTVAL (XEXP (op0, 1))
11829                                + ! equality_comparison_p))) == 0)
11830             {
11831               /* We must perform a logical shift, not an arithmetic one,
11832                  as we want the top N bits of C to be zero.  */
11833               unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
11834
11835               temp >>= INTVAL (XEXP (op0, 1));
11836               op1 = gen_int_mode (temp, mode);
11837               op0 = XEXP (op0, 0);
11838               continue;
11839             }
11840
11841           /* If we are doing a sign bit comparison, it means we are testing
11842              a particular bit.  Convert it to the appropriate AND.  */
11843           if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
11844               && mode_width <= HOST_BITS_PER_WIDE_INT)
11845             {
11846               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
11847                                             ((unsigned HOST_WIDE_INT) 1
11848                                              << (mode_width - 1
11849                                                  - INTVAL (XEXP (op0, 1)))));
11850               code = (code == LT ? NE : EQ);
11851               continue;
11852             }
11853
11854           /* If this an equality comparison with zero and we are shifting
11855              the low bit to the sign bit, we can convert this to an AND of the
11856              low-order bit.  */
11857           if (const_op == 0 && equality_comparison_p
11858               && CONST_INT_P (XEXP (op0, 1))
11859               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11860             {
11861               op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), 1);
11862               continue;
11863             }
11864           break;
11865
11866         case ASHIFTRT:
11867           /* If this is an equality comparison with zero, we can do this
11868              as a logical shift, which might be much simpler.  */
11869           if (equality_comparison_p && const_op == 0
11870               && CONST_INT_P (XEXP (op0, 1)))
11871             {
11872               op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
11873                                           XEXP (op0, 0),
11874                                           INTVAL (XEXP (op0, 1)));
11875               continue;
11876             }
11877
11878           /* If OP0 is a sign extension and CODE is not an unsigned comparison,
11879              do the comparison in a narrower mode.  */
11880           if (! unsigned_comparison_p
11881               && CONST_INT_P (XEXP (op0, 1))
11882               && GET_CODE (XEXP (op0, 0)) == ASHIFT
11883               && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
11884               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11885                                          MODE_INT, 1)) != BLKmode
11886               && (((unsigned HOST_WIDE_INT) const_op
11887                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11888                   <= GET_MODE_MASK (tmode)))
11889             {
11890               op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
11891               continue;
11892             }
11893
11894           /* Likewise if OP0 is a PLUS of a sign extension with a
11895              constant, which is usually represented with the PLUS
11896              between the shifts.  */
11897           if (! unsigned_comparison_p
11898               && CONST_INT_P (XEXP (op0, 1))
11899               && GET_CODE (XEXP (op0, 0)) == PLUS
11900               && CONST_INT_P (XEXP (XEXP (op0, 0), 1))
11901               && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
11902               && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
11903               && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
11904                                          MODE_INT, 1)) != BLKmode
11905               && (((unsigned HOST_WIDE_INT) const_op
11906                    + (GET_MODE_MASK (tmode) >> 1) + 1)
11907                   <= GET_MODE_MASK (tmode)))
11908             {
11909               rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
11910               rtx add_const = XEXP (XEXP (op0, 0), 1);
11911               rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
11912                                                    add_const, XEXP (op0, 1));
11913
11914               op0 = simplify_gen_binary (PLUS, tmode,
11915                                          gen_lowpart (tmode, inner),
11916                                          new_const);
11917               continue;
11918             }
11919
11920           /* ... fall through ...  */
11921         case LSHIFTRT:
11922           /* If we have (compare (xshiftrt FOO N) (const_int C)) and
11923              the low order N bits of FOO are known to be zero, we can do this
11924              by comparing FOO with C shifted left N bits so long as no
11925              overflow occurs.  Even if the low order N bits of FOO aren't known
11926              to be zero, if the comparison is >= or < we can use the same
11927              optimization and for > or <= by setting all the low
11928              order N bits in the comparison constant.  */
11929           if (CONST_INT_P (XEXP (op0, 1))
11930               && INTVAL (XEXP (op0, 1)) > 0
11931               && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
11932               && mode_width <= HOST_BITS_PER_WIDE_INT
11933               && (((unsigned HOST_WIDE_INT) const_op
11934                    + (GET_CODE (op0) != LSHIFTRT
11935                       ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
11936                          + 1)
11937                       : 0))
11938                   <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
11939             {
11940               unsigned HOST_WIDE_INT low_bits
11941                 = (nonzero_bits (XEXP (op0, 0), mode)
11942                    & (((unsigned HOST_WIDE_INT) 1
11943                        << INTVAL (XEXP (op0, 1))) - 1));
11944               if (low_bits == 0 || !equality_comparison_p)
11945                 {
11946                   /* If the shift was logical, then we must make the condition
11947                      unsigned.  */
11948                   if (GET_CODE (op0) == LSHIFTRT)
11949                     code = unsigned_condition (code);
11950
11951                   const_op <<= INTVAL (XEXP (op0, 1));
11952                   if (low_bits != 0
11953                       && (code == GT || code == GTU
11954                           || code == LE || code == LEU))
11955                     const_op
11956                       |= (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1);
11957                   op1 = GEN_INT (const_op);
11958                   op0 = XEXP (op0, 0);
11959                   continue;
11960                 }
11961             }
11962
11963           /* If we are using this shift to extract just the sign bit, we
11964              can replace this with an LT or GE comparison.  */
11965           if (const_op == 0
11966               && (equality_comparison_p || sign_bit_comparison_p)
11967               && CONST_INT_P (XEXP (op0, 1))
11968               && UINTVAL (XEXP (op0, 1)) == mode_width - 1)
11969             {
11970               op0 = XEXP (op0, 0);
11971               code = (code == NE || code == GT ? LT : GE);
11972               continue;
11973             }
11974           break;
11975
11976         default:
11977           break;
11978         }
11979
11980       break;
11981     }
11982
11983   /* Now make any compound operations involved in this comparison.  Then,
11984      check for an outmost SUBREG on OP0 that is not doing anything or is
11985      paradoxical.  The latter transformation must only be performed when
11986      it is known that the "extra" bits will be the same in op0 and op1 or
11987      that they don't matter.  There are three cases to consider:
11988
11989      1. SUBREG_REG (op0) is a register.  In this case the bits are don't
11990      care bits and we can assume they have any convenient value.  So
11991      making the transformation is safe.
11992
11993      2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
11994      In this case the upper bits of op0 are undefined.  We should not make
11995      the simplification in that case as we do not know the contents of
11996      those bits.
11997
11998      3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
11999      UNKNOWN.  In that case we know those bits are zeros or ones.  We must
12000      also be sure that they are the same as the upper bits of op1.
12001
12002      We can never remove a SUBREG for a non-equality comparison because
12003      the sign bit is in a different place in the underlying object.  */
12004
12005   op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
12006   op1 = make_compound_operation (op1, SET);
12007
12008   if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
12009       && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
12010       && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
12011       && (code == NE || code == EQ))
12012     {
12013       if (paradoxical_subreg_p (op0))
12014         {
12015           /* For paradoxical subregs, allow case 1 as above.  Case 3 isn't
12016              implemented.  */
12017           if (REG_P (SUBREG_REG (op0)))
12018             {
12019               op0 = SUBREG_REG (op0);
12020               op1 = gen_lowpart (GET_MODE (op0), op1);
12021             }
12022         }
12023       else if ((GET_MODE_PRECISION (GET_MODE (SUBREG_REG (op0)))
12024                 <= HOST_BITS_PER_WIDE_INT)
12025                && (nonzero_bits (SUBREG_REG (op0),
12026                                  GET_MODE (SUBREG_REG (op0)))
12027                    & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
12028         {
12029           tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
12030
12031           if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
12032                & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
12033             op0 = SUBREG_REG (op0), op1 = tem;
12034         }
12035     }
12036
12037   /* We now do the opposite procedure: Some machines don't have compare
12038      insns in all modes.  If OP0's mode is an integer mode smaller than a
12039      word and we can't do a compare in that mode, see if there is a larger
12040      mode for which we can do the compare.  There are a number of cases in
12041      which we can use the wider mode.  */
12042
12043   mode = GET_MODE (op0);
12044   if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
12045       && GET_MODE_SIZE (mode) < UNITS_PER_WORD
12046       && ! have_insn_for (COMPARE, mode))
12047     for (tmode = GET_MODE_WIDER_MODE (mode);
12048          (tmode != VOIDmode && HWI_COMPUTABLE_MODE_P (tmode));
12049          tmode = GET_MODE_WIDER_MODE (tmode))
12050       if (have_insn_for (COMPARE, tmode))
12051         {
12052           int zero_extended;
12053
12054           /* If this is a test for negative, we can make an explicit
12055              test of the sign bit.  Test this first so we can use
12056              a paradoxical subreg to extend OP0.  */
12057
12058           if (op1 == const0_rtx && (code == LT || code == GE)
12059               && HWI_COMPUTABLE_MODE_P (mode))
12060             {
12061               op0 = simplify_gen_binary (AND, tmode,
12062                                          gen_lowpart (tmode, op0),
12063                                          GEN_INT ((unsigned HOST_WIDE_INT) 1
12064                                                   << (GET_MODE_BITSIZE (mode)
12065                                                       - 1)));
12066               code = (code == LT) ? NE : EQ;
12067               break;
12068             }
12069
12070           /* If the only nonzero bits in OP0 and OP1 are those in the
12071              narrower mode and this is an equality or unsigned comparison,
12072              we can use the wider mode.  Similarly for sign-extended
12073              values, in which case it is true for all comparisons.  */
12074           zero_extended = ((code == EQ || code == NE
12075                             || code == GEU || code == GTU
12076                             || code == LEU || code == LTU)
12077                            && (nonzero_bits (op0, tmode)
12078                                & ~GET_MODE_MASK (mode)) == 0
12079                            && ((CONST_INT_P (op1)
12080                                 || (nonzero_bits (op1, tmode)
12081                                     & ~GET_MODE_MASK (mode)) == 0)));
12082
12083           if (zero_extended
12084               || ((num_sign_bit_copies (op0, tmode)
12085                    > (unsigned int) (GET_MODE_PRECISION (tmode)
12086                                      - GET_MODE_PRECISION (mode)))
12087                   && (num_sign_bit_copies (op1, tmode)
12088                       > (unsigned int) (GET_MODE_PRECISION (tmode)
12089                                         - GET_MODE_PRECISION (mode)))))
12090             {
12091               /* If OP0 is an AND and we don't have an AND in MODE either,
12092                  make a new AND in the proper mode.  */
12093               if (GET_CODE (op0) == AND
12094                   && !have_insn_for (AND, mode))
12095                 op0 = simplify_gen_binary (AND, tmode,
12096                                            gen_lowpart (tmode,
12097                                                         XEXP (op0, 0)),
12098                                            gen_lowpart (tmode,
12099                                                         XEXP (op0, 1)));
12100               else
12101                 {
12102                   if (zero_extended)
12103                     {
12104                       op0 = simplify_gen_unary (ZERO_EXTEND, tmode, op0, mode);
12105                       op1 = simplify_gen_unary (ZERO_EXTEND, tmode, op1, mode);
12106                     }
12107                   else
12108                     {
12109                       op0 = simplify_gen_unary (SIGN_EXTEND, tmode, op0, mode);
12110                       op1 = simplify_gen_unary (SIGN_EXTEND, tmode, op1, mode);
12111                     }
12112                   break;
12113                 }
12114             }
12115         }
12116
12117 #ifdef CANONICALIZE_COMPARISON
12118   /* If this machine only supports a subset of valid comparisons, see if we
12119      can convert an unsupported one into a supported one.  */
12120   CANONICALIZE_COMPARISON (code, op0, op1);
12121 #endif
12122
12123   *pop0 = op0;
12124   *pop1 = op1;
12125
12126   return code;
12127 }
12128 \f
12129 /* Utility function for record_value_for_reg.  Count number of
12130    rtxs in X.  */
12131 static int
12132 count_rtxs (rtx x)
12133 {
12134   enum rtx_code code = GET_CODE (x);
12135   const char *fmt;
12136   int i, j, ret = 1;
12137
12138   if (GET_RTX_CLASS (code) == '2'
12139       || GET_RTX_CLASS (code) == 'c')
12140     {
12141       rtx x0 = XEXP (x, 0);
12142       rtx x1 = XEXP (x, 1);
12143
12144       if (x0 == x1)
12145         return 1 + 2 * count_rtxs (x0);
12146
12147       if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
12148            || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
12149           && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12150         return 2 + 2 * count_rtxs (x0)
12151                + count_rtxs (x == XEXP (x1, 0)
12152                              ? XEXP (x1, 1) : XEXP (x1, 0));
12153
12154       if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
12155            || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
12156           && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12157         return 2 + 2 * count_rtxs (x1)
12158                + count_rtxs (x == XEXP (x0, 0)
12159                              ? XEXP (x0, 1) : XEXP (x0, 0));
12160     }
12161
12162   fmt = GET_RTX_FORMAT (code);
12163   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12164     if (fmt[i] == 'e')
12165       ret += count_rtxs (XEXP (x, i));
12166     else if (fmt[i] == 'E')
12167       for (j = 0; j < XVECLEN (x, i); j++)
12168         ret += count_rtxs (XVECEXP (x, i, j));
12169
12170   return ret;
12171 }
12172 \f
12173 /* Utility function for following routine.  Called when X is part of a value
12174    being stored into last_set_value.  Sets last_set_table_tick
12175    for each register mentioned.  Similar to mention_regs in cse.c  */
12176
12177 static void
12178 update_table_tick (rtx x)
12179 {
12180   enum rtx_code code = GET_CODE (x);
12181   const char *fmt = GET_RTX_FORMAT (code);
12182   int i, j;
12183
12184   if (code == REG)
12185     {
12186       unsigned int regno = REGNO (x);
12187       unsigned int endregno = END_REGNO (x);
12188       unsigned int r;
12189
12190       for (r = regno; r < endregno; r++)
12191         {
12192           reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, r);
12193           rsp->last_set_table_tick = label_tick;
12194         }
12195
12196       return;
12197     }
12198
12199   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12200     if (fmt[i] == 'e')
12201       {
12202         /* Check for identical subexpressions.  If x contains
12203            identical subexpression we only have to traverse one of
12204            them.  */
12205         if (i == 0 && ARITHMETIC_P (x))
12206           {
12207             /* Note that at this point x1 has already been
12208                processed.  */
12209             rtx x0 = XEXP (x, 0);
12210             rtx x1 = XEXP (x, 1);
12211
12212             /* If x0 and x1 are identical then there is no need to
12213                process x0.  */
12214             if (x0 == x1)
12215               break;
12216
12217             /* If x0 is identical to a subexpression of x1 then while
12218                processing x1, x0 has already been processed.  Thus we
12219                are done with x.  */
12220             if (ARITHMETIC_P (x1)
12221                 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12222               break;
12223
12224             /* If x1 is identical to a subexpression of x0 then we
12225                still have to process the rest of x0.  */
12226             if (ARITHMETIC_P (x0)
12227                 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12228               {
12229                 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
12230                 break;
12231               }
12232           }
12233
12234         update_table_tick (XEXP (x, i));
12235       }
12236     else if (fmt[i] == 'E')
12237       for (j = 0; j < XVECLEN (x, i); j++)
12238         update_table_tick (XVECEXP (x, i, j));
12239 }
12240
12241 /* Record that REG is set to VALUE in insn INSN.  If VALUE is zero, we
12242    are saying that the register is clobbered and we no longer know its
12243    value.  If INSN is zero, don't update reg_stat[].last_set; this is
12244    only permitted with VALUE also zero and is used to invalidate the
12245    register.  */
12246
12247 static void
12248 record_value_for_reg (rtx reg, rtx insn, rtx value)
12249 {
12250   unsigned int regno = REGNO (reg);
12251   unsigned int endregno = END_REGNO (reg);
12252   unsigned int i;
12253   reg_stat_type *rsp;
12254
12255   /* If VALUE contains REG and we have a previous value for REG, substitute
12256      the previous value.  */
12257   if (value && insn && reg_overlap_mentioned_p (reg, value))
12258     {
12259       rtx tem;
12260
12261       /* Set things up so get_last_value is allowed to see anything set up to
12262          our insn.  */
12263       subst_low_luid = DF_INSN_LUID (insn);
12264       tem = get_last_value (reg);
12265
12266       /* If TEM is simply a binary operation with two CLOBBERs as operands,
12267          it isn't going to be useful and will take a lot of time to process,
12268          so just use the CLOBBER.  */
12269
12270       if (tem)
12271         {
12272           if (ARITHMETIC_P (tem)
12273               && GET_CODE (XEXP (tem, 0)) == CLOBBER
12274               && GET_CODE (XEXP (tem, 1)) == CLOBBER)
12275             tem = XEXP (tem, 0);
12276           else if (count_occurrences (value, reg, 1) >= 2)
12277             {
12278               /* If there are two or more occurrences of REG in VALUE,
12279                  prevent the value from growing too much.  */
12280               if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
12281                 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
12282             }
12283
12284           value = replace_rtx (copy_rtx (value), reg, tem);
12285         }
12286     }
12287
12288   /* For each register modified, show we don't know its value, that
12289      we don't know about its bitwise content, that its value has been
12290      updated, and that we don't know the location of the death of the
12291      register.  */
12292   for (i = regno; i < endregno; i++)
12293     {
12294       rsp = VEC_index (reg_stat_type, reg_stat, i);
12295
12296       if (insn)
12297         rsp->last_set = insn;
12298
12299       rsp->last_set_value = 0;
12300       rsp->last_set_mode = VOIDmode;
12301       rsp->last_set_nonzero_bits = 0;
12302       rsp->last_set_sign_bit_copies = 0;
12303       rsp->last_death = 0;
12304       rsp->truncated_to_mode = VOIDmode;
12305     }
12306
12307   /* Mark registers that are being referenced in this value.  */
12308   if (value)
12309     update_table_tick (value);
12310
12311   /* Now update the status of each register being set.
12312      If someone is using this register in this block, set this register
12313      to invalid since we will get confused between the two lives in this
12314      basic block.  This makes using this register always invalid.  In cse, we
12315      scan the table to invalidate all entries using this register, but this
12316      is too much work for us.  */
12317
12318   for (i = regno; i < endregno; i++)
12319     {
12320       rsp = VEC_index (reg_stat_type, reg_stat, i);
12321       rsp->last_set_label = label_tick;
12322       if (!insn
12323           || (value && rsp->last_set_table_tick >= label_tick_ebb_start))
12324         rsp->last_set_invalid = 1;
12325       else
12326         rsp->last_set_invalid = 0;
12327     }
12328
12329   /* The value being assigned might refer to X (like in "x++;").  In that
12330      case, we must replace it with (clobber (const_int 0)) to prevent
12331      infinite loops.  */
12332   rsp = VEC_index (reg_stat_type, reg_stat, regno);
12333   if (value && !get_last_value_validate (&value, insn, label_tick, 0))
12334     {
12335       value = copy_rtx (value);
12336       if (!get_last_value_validate (&value, insn, label_tick, 1))
12337         value = 0;
12338     }
12339
12340   /* For the main register being modified, update the value, the mode, the
12341      nonzero bits, and the number of sign bit copies.  */
12342
12343   rsp->last_set_value = value;
12344
12345   if (value)
12346     {
12347       enum machine_mode mode = GET_MODE (reg);
12348       subst_low_luid = DF_INSN_LUID (insn);
12349       rsp->last_set_mode = mode;
12350       if (GET_MODE_CLASS (mode) == MODE_INT
12351           && HWI_COMPUTABLE_MODE_P (mode))
12352         mode = nonzero_bits_mode;
12353       rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
12354       rsp->last_set_sign_bit_copies
12355         = num_sign_bit_copies (value, GET_MODE (reg));
12356     }
12357 }
12358
12359 /* Called via note_stores from record_dead_and_set_regs to handle one
12360    SET or CLOBBER in an insn.  DATA is the instruction in which the
12361    set is occurring.  */
12362
12363 static void
12364 record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
12365 {
12366   rtx record_dead_insn = (rtx) data;
12367
12368   if (GET_CODE (dest) == SUBREG)
12369     dest = SUBREG_REG (dest);
12370
12371   if (!record_dead_insn)
12372     {
12373       if (REG_P (dest))
12374         record_value_for_reg (dest, NULL_RTX, NULL_RTX);
12375       return;
12376     }
12377
12378   if (REG_P (dest))
12379     {
12380       /* If we are setting the whole register, we know its value.  Otherwise
12381          show that we don't know the value.  We can handle SUBREG in
12382          some cases.  */
12383       if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
12384         record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
12385       else if (GET_CODE (setter) == SET
12386                && GET_CODE (SET_DEST (setter)) == SUBREG
12387                && SUBREG_REG (SET_DEST (setter)) == dest
12388                && GET_MODE_PRECISION (GET_MODE (dest)) <= BITS_PER_WORD
12389                && subreg_lowpart_p (SET_DEST (setter)))
12390         record_value_for_reg (dest, record_dead_insn,
12391                               gen_lowpart (GET_MODE (dest),
12392                                                        SET_SRC (setter)));
12393       else
12394         record_value_for_reg (dest, record_dead_insn, NULL_RTX);
12395     }
12396   else if (MEM_P (dest)
12397            /* Ignore pushes, they clobber nothing.  */
12398            && ! push_operand (dest, GET_MODE (dest)))
12399     mem_last_set = DF_INSN_LUID (record_dead_insn);
12400 }
12401
12402 /* Update the records of when each REG was most recently set or killed
12403    for the things done by INSN.  This is the last thing done in processing
12404    INSN in the combiner loop.
12405
12406    We update reg_stat[], in particular fields last_set, last_set_value,
12407    last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
12408    last_death, and also the similar information mem_last_set (which insn
12409    most recently modified memory) and last_call_luid (which insn was the
12410    most recent subroutine call).  */
12411
12412 static void
12413 record_dead_and_set_regs (rtx insn)
12414 {
12415   rtx link;
12416   unsigned int i;
12417
12418   for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
12419     {
12420       if (REG_NOTE_KIND (link) == REG_DEAD
12421           && REG_P (XEXP (link, 0)))
12422         {
12423           unsigned int regno = REGNO (XEXP (link, 0));
12424           unsigned int endregno = END_REGNO (XEXP (link, 0));
12425
12426           for (i = regno; i < endregno; i++)
12427             {
12428               reg_stat_type *rsp;
12429
12430               rsp = VEC_index (reg_stat_type, reg_stat, i);
12431               rsp->last_death = insn;
12432             }
12433         }
12434       else if (REG_NOTE_KIND (link) == REG_INC)
12435         record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
12436     }
12437
12438   if (CALL_P (insn))
12439     {
12440       for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
12441         if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
12442           {
12443             reg_stat_type *rsp;
12444
12445             rsp = VEC_index (reg_stat_type, reg_stat, i);
12446             rsp->last_set_invalid = 1;
12447             rsp->last_set = insn;
12448             rsp->last_set_value = 0;
12449             rsp->last_set_mode = VOIDmode;
12450             rsp->last_set_nonzero_bits = 0;
12451             rsp->last_set_sign_bit_copies = 0;
12452             rsp->last_death = 0;
12453             rsp->truncated_to_mode = VOIDmode;
12454           }
12455
12456       last_call_luid = mem_last_set = DF_INSN_LUID (insn);
12457
12458       /* We can't combine into a call pattern.  Remember, though, that
12459          the return value register is set at this LUID.  We could
12460          still replace a register with the return value from the
12461          wrong subroutine call!  */
12462       note_stores (PATTERN (insn), record_dead_and_set_regs_1, NULL_RTX);
12463     }
12464   else
12465     note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
12466 }
12467
12468 /* If a SUBREG has the promoted bit set, it is in fact a property of the
12469    register present in the SUBREG, so for each such SUBREG go back and
12470    adjust nonzero and sign bit information of the registers that are
12471    known to have some zero/sign bits set.
12472
12473    This is needed because when combine blows the SUBREGs away, the
12474    information on zero/sign bits is lost and further combines can be
12475    missed because of that.  */
12476
12477 static void
12478 record_promoted_value (rtx insn, rtx subreg)
12479 {
12480   struct insn_link *links;
12481   rtx set;
12482   unsigned int regno = REGNO (SUBREG_REG (subreg));
12483   enum machine_mode mode = GET_MODE (subreg);
12484
12485   if (GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT)
12486     return;
12487
12488   for (links = LOG_LINKS (insn); links;)
12489     {
12490       reg_stat_type *rsp;
12491
12492       insn = links->insn;
12493       set = single_set (insn);
12494
12495       if (! set || !REG_P (SET_DEST (set))
12496           || REGNO (SET_DEST (set)) != regno
12497           || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
12498         {
12499           links = links->next;
12500           continue;
12501         }
12502
12503       rsp = VEC_index (reg_stat_type, reg_stat, regno);
12504       if (rsp->last_set == insn)
12505         {
12506           if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
12507             rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
12508         }
12509
12510       if (REG_P (SET_SRC (set)))
12511         {
12512           regno = REGNO (SET_SRC (set));
12513           links = LOG_LINKS (insn);
12514         }
12515       else
12516         break;
12517     }
12518 }
12519
12520 /* Check if X, a register, is known to contain a value already
12521    truncated to MODE.  In this case we can use a subreg to refer to
12522    the truncated value even though in the generic case we would need
12523    an explicit truncation.  */
12524
12525 static bool
12526 reg_truncated_to_mode (enum machine_mode mode, const_rtx x)
12527 {
12528   reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12529   enum machine_mode truncated = rsp->truncated_to_mode;
12530
12531   if (truncated == 0
12532       || rsp->truncation_label < label_tick_ebb_start)
12533     return false;
12534   if (GET_MODE_SIZE (truncated) <= GET_MODE_SIZE (mode))
12535     return true;
12536   if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
12537     return true;
12538   return false;
12539 }
12540
12541 /* Callback for for_each_rtx.  If *P is a hard reg or a subreg record the mode
12542    that the register is accessed in.  For non-TRULY_NOOP_TRUNCATION targets we
12543    might be able to turn a truncate into a subreg using this information.
12544    Return -1 if traversing *P is complete or 0 otherwise.  */
12545
12546 static int
12547 record_truncated_value (rtx *p, void *data ATTRIBUTE_UNUSED)
12548 {
12549   rtx x = *p;
12550   enum machine_mode truncated_mode;
12551   reg_stat_type *rsp;
12552
12553   if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
12554     {
12555       enum machine_mode original_mode = GET_MODE (SUBREG_REG (x));
12556       truncated_mode = GET_MODE (x);
12557
12558       if (GET_MODE_SIZE (original_mode) <= GET_MODE_SIZE (truncated_mode))
12559         return -1;
12560
12561       if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
12562         return -1;
12563
12564       x = SUBREG_REG (x);
12565     }
12566   /* ??? For hard-regs we now record everything.  We might be able to
12567      optimize this using last_set_mode.  */
12568   else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
12569     truncated_mode = GET_MODE (x);
12570   else
12571     return 0;
12572
12573   rsp = VEC_index (reg_stat_type, reg_stat, REGNO (x));
12574   if (rsp->truncated_to_mode == 0
12575       || rsp->truncation_label < label_tick_ebb_start
12576       || (GET_MODE_SIZE (truncated_mode)
12577           < GET_MODE_SIZE (rsp->truncated_to_mode)))
12578     {
12579       rsp->truncated_to_mode = truncated_mode;
12580       rsp->truncation_label = label_tick;
12581     }
12582
12583   return -1;
12584 }
12585
12586 /* Callback for note_uses.  Find hardregs and subregs of pseudos and
12587    the modes they are used in.  This can help truning TRUNCATEs into
12588    SUBREGs.  */
12589
12590 static void
12591 record_truncated_values (rtx *x, void *data ATTRIBUTE_UNUSED)
12592 {
12593   for_each_rtx (x, record_truncated_value, NULL);
12594 }
12595
12596 /* Scan X for promoted SUBREGs.  For each one found,
12597    note what it implies to the registers used in it.  */
12598
12599 static void
12600 check_promoted_subreg (rtx insn, rtx x)
12601 {
12602   if (GET_CODE (x) == SUBREG
12603       && SUBREG_PROMOTED_VAR_P (x)
12604       && REG_P (SUBREG_REG (x)))
12605     record_promoted_value (insn, x);
12606   else
12607     {
12608       const char *format = GET_RTX_FORMAT (GET_CODE (x));
12609       int i, j;
12610
12611       for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
12612         switch (format[i])
12613           {
12614           case 'e':
12615             check_promoted_subreg (insn, XEXP (x, i));
12616             break;
12617           case 'V':
12618           case 'E':
12619             if (XVEC (x, i) != 0)
12620               for (j = 0; j < XVECLEN (x, i); j++)
12621                 check_promoted_subreg (insn, XVECEXP (x, i, j));
12622             break;
12623           }
12624     }
12625 }
12626 \f
12627 /* Verify that all the registers and memory references mentioned in *LOC are
12628    still valid.  *LOC was part of a value set in INSN when label_tick was
12629    equal to TICK.  Return 0 if some are not.  If REPLACE is nonzero, replace
12630    the invalid references with (clobber (const_int 0)) and return 1.  This
12631    replacement is useful because we often can get useful information about
12632    the form of a value (e.g., if it was produced by a shift that always
12633    produces -1 or 0) even though we don't know exactly what registers it
12634    was produced from.  */
12635
12636 static int
12637 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
12638 {
12639   rtx x = *loc;
12640   const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
12641   int len = GET_RTX_LENGTH (GET_CODE (x));
12642   int i, j;
12643
12644   if (REG_P (x))
12645     {
12646       unsigned int regno = REGNO (x);
12647       unsigned int endregno = END_REGNO (x);
12648       unsigned int j;
12649
12650       for (j = regno; j < endregno; j++)
12651         {
12652           reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, j);
12653           if (rsp->last_set_invalid
12654               /* If this is a pseudo-register that was only set once and not
12655                  live at the beginning of the function, it is always valid.  */
12656               || (! (regno >= FIRST_PSEUDO_REGISTER
12657                      && REG_N_SETS (regno) == 1
12658                      && (!REGNO_REG_SET_P
12659                          (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno)))
12660                   && rsp->last_set_label > tick))
12661           {
12662             if (replace)
12663               *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12664             return replace;
12665           }
12666         }
12667
12668       return 1;
12669     }
12670   /* If this is a memory reference, make sure that there were no stores after
12671      it that might have clobbered the value.  We don't have alias info, so we
12672      assume any store invalidates it.  Moreover, we only have local UIDs, so
12673      we also assume that there were stores in the intervening basic blocks.  */
12674   else if (MEM_P (x) && !MEM_READONLY_P (x)
12675            && (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
12676     {
12677       if (replace)
12678         *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
12679       return replace;
12680     }
12681
12682   for (i = 0; i < len; i++)
12683     {
12684       if (fmt[i] == 'e')
12685         {
12686           /* Check for identical subexpressions.  If x contains
12687              identical subexpression we only have to traverse one of
12688              them.  */
12689           if (i == 1 && ARITHMETIC_P (x))
12690             {
12691               /* Note that at this point x0 has already been checked
12692                  and found valid.  */
12693               rtx x0 = XEXP (x, 0);
12694               rtx x1 = XEXP (x, 1);
12695
12696               /* If x0 and x1 are identical then x is also valid.  */
12697               if (x0 == x1)
12698                 return 1;
12699
12700               /* If x1 is identical to a subexpression of x0 then
12701                  while checking x0, x1 has already been checked.  Thus
12702                  it is valid and so as x.  */
12703               if (ARITHMETIC_P (x0)
12704                   && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
12705                 return 1;
12706
12707               /* If x0 is identical to a subexpression of x1 then x is
12708                  valid iff the rest of x1 is valid.  */
12709               if (ARITHMETIC_P (x1)
12710                   && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
12711                 return
12712                   get_last_value_validate (&XEXP (x1,
12713                                                   x0 == XEXP (x1, 0) ? 1 : 0),
12714                                            insn, tick, replace);
12715             }
12716
12717           if (get_last_value_validate (&XEXP (x, i), insn, tick,
12718                                        replace) == 0)
12719             return 0;
12720         }
12721       else if (fmt[i] == 'E')
12722         for (j = 0; j < XVECLEN (x, i); j++)
12723           if (get_last_value_validate (&XVECEXP (x, i, j),
12724                                        insn, tick, replace) == 0)
12725             return 0;
12726     }
12727
12728   /* If we haven't found a reason for it to be invalid, it is valid.  */
12729   return 1;
12730 }
12731
12732 /* Get the last value assigned to X, if known.  Some registers
12733    in the value may be replaced with (clobber (const_int 0)) if their value
12734    is known longer known reliably.  */
12735
12736 static rtx
12737 get_last_value (const_rtx x)
12738 {
12739   unsigned int regno;
12740   rtx value;
12741   reg_stat_type *rsp;
12742
12743   /* If this is a non-paradoxical SUBREG, get the value of its operand and
12744      then convert it to the desired mode.  If this is a paradoxical SUBREG,
12745      we cannot predict what values the "extra" bits might have.  */
12746   if (GET_CODE (x) == SUBREG
12747       && subreg_lowpart_p (x)
12748       && !paradoxical_subreg_p (x)
12749       && (value = get_last_value (SUBREG_REG (x))) != 0)
12750     return gen_lowpart (GET_MODE (x), value);
12751
12752   if (!REG_P (x))
12753     return 0;
12754
12755   regno = REGNO (x);
12756   rsp = VEC_index (reg_stat_type, reg_stat, regno);
12757   value = rsp->last_set_value;
12758
12759   /* If we don't have a value, or if it isn't for this basic block and
12760      it's either a hard register, set more than once, or it's a live
12761      at the beginning of the function, return 0.
12762
12763      Because if it's not live at the beginning of the function then the reg
12764      is always set before being used (is never used without being set).
12765      And, if it's set only once, and it's always set before use, then all
12766      uses must have the same last value, even if it's not from this basic
12767      block.  */
12768
12769   if (value == 0
12770       || (rsp->last_set_label < label_tick_ebb_start
12771           && (regno < FIRST_PSEUDO_REGISTER
12772               || REG_N_SETS (regno) != 1
12773               || REGNO_REG_SET_P
12774                  (DF_LR_IN (ENTRY_BLOCK_PTR->next_bb), regno))))
12775     return 0;
12776
12777   /* If the value was set in a later insn than the ones we are processing,
12778      we can't use it even if the register was only set once.  */
12779   if (rsp->last_set_label == label_tick
12780       && DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
12781     return 0;
12782
12783   /* If the value has all its registers valid, return it.  */
12784   if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 0))
12785     return value;
12786
12787   /* Otherwise, make a copy and replace any invalid register with
12788      (clobber (const_int 0)).  If that fails for some reason, return 0.  */
12789
12790   value = copy_rtx (value);
12791   if (get_last_value_validate (&value, rsp->last_set, rsp->last_set_label, 1))
12792     return value;
12793
12794   return 0;
12795 }
12796 \f
12797 /* Return nonzero if expression X refers to a REG or to memory
12798    that is set in an instruction more recent than FROM_LUID.  */
12799
12800 static int
12801 use_crosses_set_p (const_rtx x, int from_luid)
12802 {
12803   const char *fmt;
12804   int i;
12805   enum rtx_code code = GET_CODE (x);
12806
12807   if (code == REG)
12808     {
12809       unsigned int regno = REGNO (x);
12810       unsigned endreg = END_REGNO (x);
12811
12812 #ifdef PUSH_ROUNDING
12813       /* Don't allow uses of the stack pointer to be moved,
12814          because we don't know whether the move crosses a push insn.  */
12815       if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
12816         return 1;
12817 #endif
12818       for (; regno < endreg; regno++)
12819         {
12820           reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
12821           if (rsp->last_set
12822               && rsp->last_set_label == label_tick
12823               && DF_INSN_LUID (rsp->last_set) > from_luid)
12824             return 1;
12825         }
12826       return 0;
12827     }
12828
12829   if (code == MEM && mem_last_set > from_luid)
12830     return 1;
12831
12832   fmt = GET_RTX_FORMAT (code);
12833
12834   for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
12835     {
12836       if (fmt[i] == 'E')
12837         {
12838           int j;
12839           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
12840             if (use_crosses_set_p (XVECEXP (x, i, j), from_luid))
12841               return 1;
12842         }
12843       else if (fmt[i] == 'e'
12844                && use_crosses_set_p (XEXP (x, i), from_luid))
12845         return 1;
12846     }
12847   return 0;
12848 }
12849 \f
12850 /* Define three variables used for communication between the following
12851    routines.  */
12852
12853 static unsigned int reg_dead_regno, reg_dead_endregno;
12854 static int reg_dead_flag;
12855
12856 /* Function called via note_stores from reg_dead_at_p.
12857
12858    If DEST is within [reg_dead_regno, reg_dead_endregno), set
12859    reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET.  */
12860
12861 static void
12862 reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
12863 {
12864   unsigned int regno, endregno;
12865
12866   if (!REG_P (dest))
12867     return;
12868
12869   regno = REGNO (dest);
12870   endregno = END_REGNO (dest);
12871   if (reg_dead_endregno > regno && reg_dead_regno < endregno)
12872     reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
12873 }
12874
12875 /* Return nonzero if REG is known to be dead at INSN.
12876
12877    We scan backwards from INSN.  If we hit a REG_DEAD note or a CLOBBER
12878    referencing REG, it is dead.  If we hit a SET referencing REG, it is
12879    live.  Otherwise, see if it is live or dead at the start of the basic
12880    block we are in.  Hard regs marked as being live in NEWPAT_USED_REGS
12881    must be assumed to be always live.  */
12882
12883 static int
12884 reg_dead_at_p (rtx reg, rtx insn)
12885 {
12886   basic_block block;
12887   unsigned int i;
12888
12889   /* Set variables for reg_dead_at_p_1.  */
12890   reg_dead_regno = REGNO (reg);
12891   reg_dead_endregno = END_REGNO (reg);
12892
12893   reg_dead_flag = 0;
12894
12895   /* Check that reg isn't mentioned in NEWPAT_USED_REGS.  For fixed registers
12896      we allow the machine description to decide whether use-and-clobber
12897      patterns are OK.  */
12898   if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
12899     {
12900       for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12901         if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
12902           return 0;
12903     }
12904
12905   /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
12906      beginning of basic block.  */
12907   block = BLOCK_FOR_INSN (insn);
12908   for (;;)
12909     {
12910       if (INSN_P (insn))
12911         {
12912           note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
12913           if (reg_dead_flag)
12914             return reg_dead_flag == 1 ? 1 : 0;
12915
12916           if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
12917             return 1;
12918         }
12919
12920       if (insn == BB_HEAD (block))
12921         break;
12922
12923       insn = PREV_INSN (insn);
12924     }
12925
12926   /* Look at live-in sets for the basic block that we were in.  */
12927   for (i = reg_dead_regno; i < reg_dead_endregno; i++)
12928     if (REGNO_REG_SET_P (df_get_live_in (block), i))
12929       return 0;
12930
12931   return 1;
12932 }
12933 \f
12934 /* Note hard registers in X that are used.  */
12935
12936 static void
12937 mark_used_regs_combine (rtx x)
12938 {
12939   RTX_CODE code = GET_CODE (x);
12940   unsigned int regno;
12941   int i;
12942
12943   switch (code)
12944     {
12945     case LABEL_REF:
12946     case SYMBOL_REF:
12947     case CONST_INT:
12948     case CONST:
12949     case CONST_DOUBLE:
12950     case CONST_VECTOR:
12951     case PC:
12952     case ADDR_VEC:
12953     case ADDR_DIFF_VEC:
12954     case ASM_INPUT:
12955 #ifdef HAVE_cc0
12956     /* CC0 must die in the insn after it is set, so we don't need to take
12957        special note of it here.  */
12958     case CC0:
12959 #endif
12960       return;
12961
12962     case CLOBBER:
12963       /* If we are clobbering a MEM, mark any hard registers inside the
12964          address as used.  */
12965       if (MEM_P (XEXP (x, 0)))
12966         mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
12967       return;
12968
12969     case REG:
12970       regno = REGNO (x);
12971       /* A hard reg in a wide mode may really be multiple registers.
12972          If so, mark all of them just like the first.  */
12973       if (regno < FIRST_PSEUDO_REGISTER)
12974         {
12975           /* None of this applies to the stack, frame or arg pointers.  */
12976           if (regno == STACK_POINTER_REGNUM
12977 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
12978               || regno == HARD_FRAME_POINTER_REGNUM
12979 #endif
12980 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
12981               || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
12982 #endif
12983               || regno == FRAME_POINTER_REGNUM)
12984             return;
12985
12986           add_to_hard_reg_set (&newpat_used_regs, GET_MODE (x), regno);
12987         }
12988       return;
12989
12990     case SET:
12991       {
12992         /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
12993            the address.  */
12994         rtx testreg = SET_DEST (x);
12995
12996         while (GET_CODE (testreg) == SUBREG
12997                || GET_CODE (testreg) == ZERO_EXTRACT
12998                || GET_CODE (testreg) == STRICT_LOW_PART)
12999           testreg = XEXP (testreg, 0);
13000
13001         if (MEM_P (testreg))
13002           mark_used_regs_combine (XEXP (testreg, 0));
13003
13004         mark_used_regs_combine (SET_SRC (x));
13005       }
13006       return;
13007
13008     default:
13009       break;
13010     }
13011
13012   /* Recursively scan the operands of this expression.  */
13013
13014   {
13015     const char *fmt = GET_RTX_FORMAT (code);
13016
13017     for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13018       {
13019         if (fmt[i] == 'e')
13020           mark_used_regs_combine (XEXP (x, i));
13021         else if (fmt[i] == 'E')
13022           {
13023             int j;
13024
13025             for (j = 0; j < XVECLEN (x, i); j++)
13026               mark_used_regs_combine (XVECEXP (x, i, j));
13027           }
13028       }
13029   }
13030 }
13031 \f
13032 /* Remove register number REGNO from the dead registers list of INSN.
13033
13034    Return the note used to record the death, if there was one.  */
13035
13036 rtx
13037 remove_death (unsigned int regno, rtx insn)
13038 {
13039   rtx note = find_regno_note (insn, REG_DEAD, regno);
13040
13041   if (note)
13042     remove_note (insn, note);
13043
13044   return note;
13045 }
13046
13047 /* For each register (hardware or pseudo) used within expression X, if its
13048    death is in an instruction with luid between FROM_LUID (inclusive) and
13049    TO_INSN (exclusive), put a REG_DEAD note for that register in the
13050    list headed by PNOTES.
13051
13052    That said, don't move registers killed by maybe_kill_insn.
13053
13054    This is done when X is being merged by combination into TO_INSN.  These
13055    notes will then be distributed as needed.  */
13056
13057 static void
13058 move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx to_insn,
13059              rtx *pnotes)
13060 {
13061   const char *fmt;
13062   int len, i;
13063   enum rtx_code code = GET_CODE (x);
13064
13065   if (code == REG)
13066     {
13067       unsigned int regno = REGNO (x);
13068       rtx where_dead = VEC_index (reg_stat_type, reg_stat, regno)->last_death;
13069
13070       /* Don't move the register if it gets killed in between from and to.  */
13071       if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
13072           && ! reg_referenced_p (x, maybe_kill_insn))
13073         return;
13074
13075       if (where_dead
13076           && BLOCK_FOR_INSN (where_dead) == BLOCK_FOR_INSN (to_insn)
13077           && DF_INSN_LUID (where_dead) >= from_luid
13078           && DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
13079         {
13080           rtx note = remove_death (regno, where_dead);
13081
13082           /* It is possible for the call above to return 0.  This can occur
13083              when last_death points to I2 or I1 that we combined with.
13084              In that case make a new note.
13085
13086              We must also check for the case where X is a hard register
13087              and NOTE is a death note for a range of hard registers
13088              including X.  In that case, we must put REG_DEAD notes for
13089              the remaining registers in place of NOTE.  */
13090
13091           if (note != 0 && regno < FIRST_PSEUDO_REGISTER
13092               && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13093                   > GET_MODE_SIZE (GET_MODE (x))))
13094             {
13095               unsigned int deadregno = REGNO (XEXP (note, 0));
13096               unsigned int deadend = END_HARD_REGNO (XEXP (note, 0));
13097               unsigned int ourend = END_HARD_REGNO (x);
13098               unsigned int i;
13099
13100               for (i = deadregno; i < deadend; i++)
13101                 if (i < regno || i >= ourend)
13102                   add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
13103             }
13104
13105           /* If we didn't find any note, or if we found a REG_DEAD note that
13106              covers only part of the given reg, and we have a multi-reg hard
13107              register, then to be safe we must check for REG_DEAD notes
13108              for each register other than the first.  They could have
13109              their own REG_DEAD notes lying around.  */
13110           else if ((note == 0
13111                     || (note != 0
13112                         && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
13113                             < GET_MODE_SIZE (GET_MODE (x)))))
13114                    && regno < FIRST_PSEUDO_REGISTER
13115                    && hard_regno_nregs[regno][GET_MODE (x)] > 1)
13116             {
13117               unsigned int ourend = END_HARD_REGNO (x);
13118               unsigned int i, offset;
13119               rtx oldnotes = 0;
13120
13121               if (note)
13122                 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
13123               else
13124                 offset = 1;
13125
13126               for (i = regno + offset; i < ourend; i++)
13127                 move_deaths (regno_reg_rtx[i],
13128                              maybe_kill_insn, from_luid, to_insn, &oldnotes);
13129             }
13130
13131           if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
13132             {
13133               XEXP (note, 1) = *pnotes;
13134               *pnotes = note;
13135             }
13136           else
13137             *pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
13138         }
13139
13140       return;
13141     }
13142
13143   else if (GET_CODE (x) == SET)
13144     {
13145       rtx dest = SET_DEST (x);
13146
13147       move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
13148
13149       /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
13150          that accesses one word of a multi-word item, some
13151          piece of everything register in the expression is used by
13152          this insn, so remove any old death.  */
13153       /* ??? So why do we test for equality of the sizes?  */
13154
13155       if (GET_CODE (dest) == ZERO_EXTRACT
13156           || GET_CODE (dest) == STRICT_LOW_PART
13157           || (GET_CODE (dest) == SUBREG
13158               && (((GET_MODE_SIZE (GET_MODE (dest))
13159                     + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
13160                   == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
13161                        + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
13162         {
13163           move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
13164           return;
13165         }
13166
13167       /* If this is some other SUBREG, we know it replaces the entire
13168          value, so use that as the destination.  */
13169       if (GET_CODE (dest) == SUBREG)
13170         dest = SUBREG_REG (dest);
13171
13172       /* If this is a MEM, adjust deaths of anything used in the address.
13173          For a REG (the only other possibility), the entire value is
13174          being replaced so the old value is not used in this insn.  */
13175
13176       if (MEM_P (dest))
13177         move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
13178                      to_insn, pnotes);
13179       return;
13180     }
13181
13182   else if (GET_CODE (x) == CLOBBER)
13183     return;
13184
13185   len = GET_RTX_LENGTH (code);
13186   fmt = GET_RTX_FORMAT (code);
13187
13188   for (i = 0; i < len; i++)
13189     {
13190       if (fmt[i] == 'E')
13191         {
13192           int j;
13193           for (j = XVECLEN (x, i) - 1; j >= 0; j--)
13194             move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
13195                          to_insn, pnotes);
13196         }
13197       else if (fmt[i] == 'e')
13198         move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
13199     }
13200 }
13201 \f
13202 /* Return 1 if X is the target of a bit-field assignment in BODY, the
13203    pattern of an insn.  X must be a REG.  */
13204
13205 static int
13206 reg_bitfield_target_p (rtx x, rtx body)
13207 {
13208   int i;
13209
13210   if (GET_CODE (body) == SET)
13211     {
13212       rtx dest = SET_DEST (body);
13213       rtx target;
13214       unsigned int regno, tregno, endregno, endtregno;
13215
13216       if (GET_CODE (dest) == ZERO_EXTRACT)
13217         target = XEXP (dest, 0);
13218       else if (GET_CODE (dest) == STRICT_LOW_PART)
13219         target = SUBREG_REG (XEXP (dest, 0));
13220       else
13221         return 0;
13222
13223       if (GET_CODE (target) == SUBREG)
13224         target = SUBREG_REG (target);
13225
13226       if (!REG_P (target))
13227         return 0;
13228
13229       tregno = REGNO (target), regno = REGNO (x);
13230       if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
13231         return target == x;
13232
13233       endtregno = end_hard_regno (GET_MODE (target), tregno);
13234       endregno = end_hard_regno (GET_MODE (x), regno);
13235
13236       return endregno > tregno && regno < endtregno;
13237     }
13238
13239   else if (GET_CODE (body) == PARALLEL)
13240     for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
13241       if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
13242         return 1;
13243
13244   return 0;
13245 }
13246 \f
13247 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
13248    as appropriate.  I3 and I2 are the insns resulting from the combination
13249    insns including FROM (I2 may be zero).
13250
13251    ELIM_I2 and ELIM_I1 are either zero or registers that we know will
13252    not need REG_DEAD notes because they are being substituted for.  This
13253    saves searching in the most common cases.
13254
13255    Each note in the list is either ignored or placed on some insns, depending
13256    on the type of note.  */
13257
13258 static void
13259 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
13260                   rtx elim_i1, rtx elim_i0)
13261 {
13262   rtx note, next_note;
13263   rtx tem;
13264
13265   for (note = notes; note; note = next_note)
13266     {
13267       rtx place = 0, place2 = 0;
13268
13269       next_note = XEXP (note, 1);
13270       switch (REG_NOTE_KIND (note))
13271         {
13272         case REG_BR_PROB:
13273         case REG_BR_PRED:
13274           /* Doesn't matter much where we put this, as long as it's somewhere.
13275              It is preferable to keep these notes on branches, which is most
13276              likely to be i3.  */
13277           place = i3;
13278           break;
13279
13280         case REG_NON_LOCAL_GOTO:
13281           if (JUMP_P (i3))
13282             place = i3;
13283           else
13284             {
13285               gcc_assert (i2 && JUMP_P (i2));
13286               place = i2;
13287             }
13288           break;
13289
13290         case REG_EH_REGION:
13291           /* These notes must remain with the call or trapping instruction.  */
13292           if (CALL_P (i3))
13293             place = i3;
13294           else if (i2 && CALL_P (i2))
13295             place = i2;
13296           else
13297             {
13298               gcc_assert (cfun->can_throw_non_call_exceptions);
13299               if (may_trap_p (i3))
13300                 place = i3;
13301               else if (i2 && may_trap_p (i2))
13302                 place = i2;
13303               /* ??? Otherwise assume we've combined things such that we
13304                  can now prove that the instructions can't trap.  Drop the
13305                  note in this case.  */
13306             }
13307           break;
13308
13309         case REG_ARGS_SIZE:
13310           /* ??? How to distribute between i3-i1.  Assume i3 contains the
13311              entire adjustment.  Assert i3 contains at least some adjust.  */
13312           if (!noop_move_p (i3))
13313             {
13314               int old_size, args_size = INTVAL (XEXP (note, 0));
13315               /* fixup_args_size_notes looks at REG_NORETURN note,
13316                  so ensure the note is placed there first.  */
13317               if (CALL_P (i3))
13318                 {
13319                   rtx *np;
13320                   for (np = &next_note; *np; np = &XEXP (*np, 1))
13321                     if (REG_NOTE_KIND (*np) == REG_NORETURN)
13322                       {
13323                         rtx n = *np;
13324                         *np = XEXP (n, 1);
13325                         XEXP (n, 1) = REG_NOTES (i3);
13326                         REG_NOTES (i3) = n;
13327                         break;
13328                       }
13329                 }
13330               old_size = fixup_args_size_notes (PREV_INSN (i3), i3, args_size);
13331               /* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
13332                  REG_ARGS_SIZE note to all noreturn calls, allow that here.  */
13333               gcc_assert (old_size != args_size
13334                           || (CALL_P (i3)
13335                               && !ACCUMULATE_OUTGOING_ARGS
13336                               && find_reg_note (i3, REG_NORETURN, NULL_RTX)));
13337             }
13338           break;
13339
13340         case REG_NORETURN:
13341         case REG_SETJMP:
13342         case REG_TM:
13343           /* These notes must remain with the call.  It should not be
13344              possible for both I2 and I3 to be a call.  */
13345           if (CALL_P (i3))
13346             place = i3;
13347           else
13348             {
13349               gcc_assert (i2 && CALL_P (i2));
13350               place = i2;
13351             }
13352           break;
13353
13354         case REG_UNUSED:
13355           /* Any clobbers for i3 may still exist, and so we must process
13356              REG_UNUSED notes from that insn.
13357
13358              Any clobbers from i2 or i1 can only exist if they were added by
13359              recog_for_combine.  In that case, recog_for_combine created the
13360              necessary REG_UNUSED notes.  Trying to keep any original
13361              REG_UNUSED notes from these insns can cause incorrect output
13362              if it is for the same register as the original i3 dest.
13363              In that case, we will notice that the register is set in i3,
13364              and then add a REG_UNUSED note for the destination of i3, which
13365              is wrong.  However, it is possible to have REG_UNUSED notes from
13366              i2 or i1 for register which were both used and clobbered, so
13367              we keep notes from i2 or i1 if they will turn into REG_DEAD
13368              notes.  */
13369
13370           /* If this register is set or clobbered in I3, put the note there
13371              unless there is one already.  */
13372           if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
13373             {
13374               if (from_insn != i3)
13375                 break;
13376
13377               if (! (REG_P (XEXP (note, 0))
13378                      ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
13379                      : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
13380                 place = i3;
13381             }
13382           /* Otherwise, if this register is used by I3, then this register
13383              now dies here, so we must put a REG_DEAD note here unless there
13384              is one already.  */
13385           else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
13386                    && ! (REG_P (XEXP (note, 0))
13387                          ? find_regno_note (i3, REG_DEAD,
13388                                             REGNO (XEXP (note, 0)))
13389                          : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
13390             {
13391               PUT_REG_NOTE_KIND (note, REG_DEAD);
13392               place = i3;
13393             }
13394           break;
13395
13396         case REG_EQUAL:
13397         case REG_EQUIV:
13398         case REG_NOALIAS:
13399           /* These notes say something about results of an insn.  We can
13400              only support them if they used to be on I3 in which case they
13401              remain on I3.  Otherwise they are ignored.
13402
13403              If the note refers to an expression that is not a constant, we
13404              must also ignore the note since we cannot tell whether the
13405              equivalence is still true.  It might be possible to do
13406              slightly better than this (we only have a problem if I2DEST
13407              or I1DEST is present in the expression), but it doesn't
13408              seem worth the trouble.  */
13409
13410           if (from_insn == i3
13411               && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
13412             place = i3;
13413           break;
13414
13415         case REG_INC:
13416           /* These notes say something about how a register is used.  They must
13417              be present on any use of the register in I2 or I3.  */
13418           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
13419             place = i3;
13420
13421           if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
13422             {
13423               if (place)
13424                 place2 = i2;
13425               else
13426                 place = i2;
13427             }
13428           break;
13429
13430         case REG_LABEL_TARGET:
13431         case REG_LABEL_OPERAND:
13432           /* This can show up in several ways -- either directly in the
13433              pattern, or hidden off in the constant pool with (or without?)
13434              a REG_EQUAL note.  */
13435           /* ??? Ignore the without-reg_equal-note problem for now.  */
13436           if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
13437               || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
13438                   && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13439                   && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
13440             place = i3;
13441
13442           if (i2
13443               && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
13444                   || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
13445                       && GET_CODE (XEXP (tem, 0)) == LABEL_REF
13446                       && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
13447             {
13448               if (place)
13449                 place2 = i2;
13450               else
13451                 place = i2;
13452             }
13453
13454           /* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
13455              as a JUMP_LABEL or decrement LABEL_NUSES if it's already
13456              there.  */
13457           if (place && JUMP_P (place)
13458               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13459               && (JUMP_LABEL (place) == NULL
13460                   || JUMP_LABEL (place) == XEXP (note, 0)))
13461             {
13462               rtx label = JUMP_LABEL (place);
13463
13464               if (!label)
13465                 JUMP_LABEL (place) = XEXP (note, 0);
13466               else if (LABEL_P (label))
13467                 LABEL_NUSES (label)--;
13468             }
13469
13470           if (place2 && JUMP_P (place2)
13471               && REG_NOTE_KIND (note) == REG_LABEL_TARGET
13472               && (JUMP_LABEL (place2) == NULL
13473                   || JUMP_LABEL (place2) == XEXP (note, 0)))
13474             {
13475               rtx label = JUMP_LABEL (place2);
13476
13477               if (!label)
13478                 JUMP_LABEL (place2) = XEXP (note, 0);
13479               else if (LABEL_P (label))
13480                 LABEL_NUSES (label)--;
13481               place2 = 0;
13482             }
13483           break;
13484
13485         case REG_NONNEG:
13486           /* This note says something about the value of a register prior
13487              to the execution of an insn.  It is too much trouble to see
13488              if the note is still correct in all situations.  It is better
13489              to simply delete it.  */
13490           break;
13491
13492         case REG_DEAD:
13493           /* If we replaced the right hand side of FROM_INSN with a
13494              REG_EQUAL note, the original use of the dying register
13495              will not have been combined into I3 and I2.  In such cases,
13496              FROM_INSN is guaranteed to be the first of the combined
13497              instructions, so we simply need to search back before
13498              FROM_INSN for the previous use or set of this register,
13499              then alter the notes there appropriately.
13500
13501              If the register is used as an input in I3, it dies there.
13502              Similarly for I2, if it is nonzero and adjacent to I3.
13503
13504              If the register is not used as an input in either I3 or I2
13505              and it is not one of the registers we were supposed to eliminate,
13506              there are two possibilities.  We might have a non-adjacent I2
13507              or we might have somehow eliminated an additional register
13508              from a computation.  For example, we might have had A & B where
13509              we discover that B will always be zero.  In this case we will
13510              eliminate the reference to A.
13511
13512              In both cases, we must search to see if we can find a previous
13513              use of A and put the death note there.  */
13514
13515           if (from_insn
13516               && from_insn == i2mod
13517               && !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
13518             tem = from_insn;
13519           else
13520             {
13521               if (from_insn
13522                   && CALL_P (from_insn)
13523                   && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
13524                 place = from_insn;
13525               else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
13526                 place = i3;
13527               else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
13528                        && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13529                 place = i2;
13530               else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
13531                         && !(i2mod
13532                              && reg_overlap_mentioned_p (XEXP (note, 0),
13533                                                          i2mod_old_rhs)))
13534                        || rtx_equal_p (XEXP (note, 0), elim_i1)
13535                        || rtx_equal_p (XEXP (note, 0), elim_i0))
13536                 break;
13537               tem = i3;
13538             }
13539
13540           if (place == 0)
13541             {
13542               basic_block bb = this_basic_block;
13543
13544               for (tem = PREV_INSN (tem); place == 0; tem = PREV_INSN (tem))
13545                 {
13546                   if (!NONDEBUG_INSN_P (tem))
13547                     {
13548                       if (tem == BB_HEAD (bb))
13549                         break;
13550                       continue;
13551                     }
13552
13553                   /* If the register is being set at TEM, see if that is all
13554                      TEM is doing.  If so, delete TEM.  Otherwise, make this
13555                      into a REG_UNUSED note instead. Don't delete sets to
13556                      global register vars.  */
13557                   if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
13558                        || !global_regs[REGNO (XEXP (note, 0))])
13559                       && reg_set_p (XEXP (note, 0), PATTERN (tem)))
13560                     {
13561                       rtx set = single_set (tem);
13562                       rtx inner_dest = 0;
13563 #ifdef HAVE_cc0
13564                       rtx cc0_setter = NULL_RTX;
13565 #endif
13566
13567                       if (set != 0)
13568                         for (inner_dest = SET_DEST (set);
13569                              (GET_CODE (inner_dest) == STRICT_LOW_PART
13570                               || GET_CODE (inner_dest) == SUBREG
13571                               || GET_CODE (inner_dest) == ZERO_EXTRACT);
13572                              inner_dest = XEXP (inner_dest, 0))
13573                           ;
13574
13575                       /* Verify that it was the set, and not a clobber that
13576                          modified the register.
13577
13578                          CC0 targets must be careful to maintain setter/user
13579                          pairs.  If we cannot delete the setter due to side
13580                          effects, mark the user with an UNUSED note instead
13581                          of deleting it.  */
13582
13583                       if (set != 0 && ! side_effects_p (SET_SRC (set))
13584                           && rtx_equal_p (XEXP (note, 0), inner_dest)
13585 #ifdef HAVE_cc0
13586                           && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
13587                               || ((cc0_setter = prev_cc0_setter (tem)) != NULL
13588                                   && sets_cc0_p (PATTERN (cc0_setter)) > 0))
13589 #endif
13590                           )
13591                         {
13592                           /* Move the notes and links of TEM elsewhere.
13593                              This might delete other dead insns recursively.
13594                              First set the pattern to something that won't use
13595                              any register.  */
13596                           rtx old_notes = REG_NOTES (tem);
13597
13598                           PATTERN (tem) = pc_rtx;
13599                           REG_NOTES (tem) = NULL;
13600
13601                           distribute_notes (old_notes, tem, tem, NULL_RTX,
13602                                             NULL_RTX, NULL_RTX, NULL_RTX);
13603                           distribute_links (LOG_LINKS (tem));
13604
13605                           SET_INSN_DELETED (tem);
13606                           if (tem == i2)
13607                             i2 = NULL_RTX;
13608
13609 #ifdef HAVE_cc0
13610                           /* Delete the setter too.  */
13611                           if (cc0_setter)
13612                             {
13613                               PATTERN (cc0_setter) = pc_rtx;
13614                               old_notes = REG_NOTES (cc0_setter);
13615                               REG_NOTES (cc0_setter) = NULL;
13616
13617                               distribute_notes (old_notes, cc0_setter,
13618                                                 cc0_setter, NULL_RTX,
13619                                                 NULL_RTX, NULL_RTX, NULL_RTX);
13620                               distribute_links (LOG_LINKS (cc0_setter));
13621
13622                               SET_INSN_DELETED (cc0_setter);
13623                               if (cc0_setter == i2)
13624                                 i2 = NULL_RTX;
13625                             }
13626 #endif
13627                         }
13628                       else
13629                         {
13630                           PUT_REG_NOTE_KIND (note, REG_UNUSED);
13631
13632                           /*  If there isn't already a REG_UNUSED note, put one
13633                               here.  Do not place a REG_DEAD note, even if
13634                               the register is also used here; that would not
13635                               match the algorithm used in lifetime analysis
13636                               and can cause the consistency check in the
13637                               scheduler to fail.  */
13638                           if (! find_regno_note (tem, REG_UNUSED,
13639                                                  REGNO (XEXP (note, 0))))
13640                             place = tem;
13641                           break;
13642                         }
13643                     }
13644                   else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
13645                            || (CALL_P (tem)
13646                                && find_reg_fusage (tem, USE, XEXP (note, 0))))
13647                     {
13648                       place = tem;
13649
13650                       /* If we are doing a 3->2 combination, and we have a
13651                          register which formerly died in i3 and was not used
13652                          by i2, which now no longer dies in i3 and is used in
13653                          i2 but does not die in i2, and place is between i2
13654                          and i3, then we may need to move a link from place to
13655                          i2.  */
13656                       if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
13657                           && from_insn
13658                           && DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
13659                           && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
13660                         {
13661                           struct insn_link *links = LOG_LINKS (place);
13662                           LOG_LINKS (place) = NULL;
13663                           distribute_links (links);
13664                         }
13665                       break;
13666                     }
13667
13668                   if (tem == BB_HEAD (bb))
13669                     break;
13670                 }
13671
13672             }
13673
13674           /* If the register is set or already dead at PLACE, we needn't do
13675              anything with this note if it is still a REG_DEAD note.
13676              We check here if it is set at all, not if is it totally replaced,
13677              which is what `dead_or_set_p' checks, so also check for it being
13678              set partially.  */
13679
13680           if (place && REG_NOTE_KIND (note) == REG_DEAD)
13681             {
13682               unsigned int regno = REGNO (XEXP (note, 0));
13683               reg_stat_type *rsp = VEC_index (reg_stat_type, reg_stat, regno);
13684
13685               if (dead_or_set_p (place, XEXP (note, 0))
13686                   || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
13687                 {
13688                   /* Unless the register previously died in PLACE, clear
13689                      last_death.  [I no longer understand why this is
13690                      being done.] */
13691                   if (rsp->last_death != place)
13692                     rsp->last_death = 0;
13693                   place = 0;
13694                 }
13695               else
13696                 rsp->last_death = place;
13697
13698               /* If this is a death note for a hard reg that is occupying
13699                  multiple registers, ensure that we are still using all
13700                  parts of the object.  If we find a piece of the object
13701                  that is unused, we must arrange for an appropriate REG_DEAD
13702                  note to be added for it.  However, we can't just emit a USE
13703                  and tag the note to it, since the register might actually
13704                  be dead; so we recourse, and the recursive call then finds
13705                  the previous insn that used this register.  */
13706
13707               if (place && regno < FIRST_PSEUDO_REGISTER
13708                   && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
13709                 {
13710                   unsigned int endregno = END_HARD_REGNO (XEXP (note, 0));
13711                   int all_used = 1;
13712                   unsigned int i;
13713
13714                   for (i = regno; i < endregno; i++)
13715                     if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
13716                          && ! find_regno_fusage (place, USE, i))
13717                         || dead_or_set_regno_p (place, i))
13718                       all_used = 0;
13719
13720                   if (! all_used)
13721                     {
13722                       /* Put only REG_DEAD notes for pieces that are
13723                          not already dead or set.  */
13724
13725                       for (i = regno; i < endregno;
13726                            i += hard_regno_nregs[i][reg_raw_mode[i]])
13727                         {
13728                           rtx piece = regno_reg_rtx[i];
13729                           basic_block bb = this_basic_block;
13730
13731                           if (! dead_or_set_p (place, piece)
13732                               && ! reg_bitfield_target_p (piece,
13733                                                           PATTERN (place)))
13734                             {
13735                               rtx new_note = alloc_reg_note (REG_DEAD, piece,
13736                                                              NULL_RTX);
13737
13738                               distribute_notes (new_note, place, place,
13739                                                 NULL_RTX, NULL_RTX, NULL_RTX,
13740                                                 NULL_RTX);
13741                             }
13742                           else if (! refers_to_regno_p (i, i + 1,
13743                                                         PATTERN (place), 0)
13744                                    && ! find_regno_fusage (place, USE, i))
13745                             for (tem = PREV_INSN (place); ;
13746                                  tem = PREV_INSN (tem))
13747                               {
13748                                 if (!NONDEBUG_INSN_P (tem))
13749                                   {
13750                                     if (tem == BB_HEAD (bb))
13751                                       break;
13752                                     continue;
13753                                   }
13754                                 if (dead_or_set_p (tem, piece)
13755                                     || reg_bitfield_target_p (piece,
13756                                                               PATTERN (tem)))
13757                                   {
13758                                     add_reg_note (tem, REG_UNUSED, piece);
13759                                     break;
13760                                   }
13761                               }
13762
13763                         }
13764
13765                       place = 0;
13766                     }
13767                 }
13768             }
13769           break;
13770
13771         default:
13772           /* Any other notes should not be present at this point in the
13773              compilation.  */
13774           gcc_unreachable ();
13775         }
13776
13777       if (place)
13778         {
13779           XEXP (note, 1) = REG_NOTES (place);
13780           REG_NOTES (place) = note;
13781         }
13782
13783       if (place2)
13784         add_reg_note (place2, REG_NOTE_KIND (note), XEXP (note, 0));
13785     }
13786 }
13787 \f
13788 /* Similarly to above, distribute the LOG_LINKS that used to be present on
13789    I3, I2, and I1 to new locations.  This is also called to add a link
13790    pointing at I3 when I3's destination is changed.  */
13791
13792 static void
13793 distribute_links (struct insn_link *links)
13794 {
13795   struct insn_link *link, *next_link;
13796
13797   for (link = links; link; link = next_link)
13798     {
13799       rtx place = 0;
13800       rtx insn;
13801       rtx set, reg;
13802
13803       next_link = link->next;
13804
13805       /* If the insn that this link points to is a NOTE or isn't a single
13806          set, ignore it.  In the latter case, it isn't clear what we
13807          can do other than ignore the link, since we can't tell which
13808          register it was for.  Such links wouldn't be used by combine
13809          anyway.
13810
13811          It is not possible for the destination of the target of the link to
13812          have been changed by combine.  The only potential of this is if we
13813          replace I3, I2, and I1 by I3 and I2.  But in that case the
13814          destination of I2 also remains unchanged.  */
13815
13816       if (NOTE_P (link->insn)
13817           || (set = single_set (link->insn)) == 0)
13818         continue;
13819
13820       reg = SET_DEST (set);
13821       while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
13822              || GET_CODE (reg) == STRICT_LOW_PART)
13823         reg = XEXP (reg, 0);
13824
13825       /* A LOG_LINK is defined as being placed on the first insn that uses
13826          a register and points to the insn that sets the register.  Start
13827          searching at the next insn after the target of the link and stop
13828          when we reach a set of the register or the end of the basic block.
13829
13830          Note that this correctly handles the link that used to point from
13831          I3 to I2.  Also note that not much searching is typically done here
13832          since most links don't point very far away.  */
13833
13834       for (insn = NEXT_INSN (link->insn);
13835            (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
13836                      || BB_HEAD (this_basic_block->next_bb) != insn));
13837            insn = NEXT_INSN (insn))
13838         if (DEBUG_INSN_P (insn))
13839           continue;
13840         else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
13841           {
13842             if (reg_referenced_p (reg, PATTERN (insn)))
13843               place = insn;
13844             break;
13845           }
13846         else if (CALL_P (insn)
13847                  && find_reg_fusage (insn, USE, reg))
13848           {
13849             place = insn;
13850             break;
13851           }
13852         else if (INSN_P (insn) && reg_set_p (reg, insn))
13853           break;
13854
13855       /* If we found a place to put the link, place it there unless there
13856          is already a link to the same insn as LINK at that point.  */
13857
13858       if (place)
13859         {
13860           struct insn_link *link2;
13861
13862           FOR_EACH_LOG_LINK (link2, place)
13863             if (link2->insn == link->insn)
13864               break;
13865
13866           if (link2 == NULL)
13867             {
13868               link->next = LOG_LINKS (place);
13869               LOG_LINKS (place) = link;
13870
13871               /* Set added_links_insn to the earliest insn we added a
13872                  link to.  */
13873               if (added_links_insn == 0
13874                   || DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
13875                 added_links_insn = place;
13876             }
13877         }
13878     }
13879 }
13880 \f
13881 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
13882    Check whether the expression pointer to by LOC is a register or
13883    memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
13884    Otherwise return zero.  */
13885
13886 static int
13887 unmentioned_reg_p_1 (rtx *loc, void *expr)
13888 {
13889   rtx x = *loc;
13890
13891   if (x != NULL_RTX
13892       && (REG_P (x) || MEM_P (x))
13893       && ! reg_mentioned_p (x, (rtx) expr))
13894     return 1;
13895   return 0;
13896 }
13897
13898 /* Check for any register or memory mentioned in EQUIV that is not
13899    mentioned in EXPR.  This is used to restrict EQUIV to "specializations"
13900    of EXPR where some registers may have been replaced by constants.  */
13901
13902 static bool
13903 unmentioned_reg_p (rtx equiv, rtx expr)
13904 {
13905   return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
13906 }
13907 \f
13908 void
13909 dump_combine_stats (FILE *file)
13910 {
13911   fprintf
13912     (file,
13913      ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
13914      combine_attempts, combine_merges, combine_extras, combine_successes);
13915 }
13916
13917 void
13918 dump_combine_total_stats (FILE *file)
13919 {
13920   fprintf
13921     (file,
13922      "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
13923      total_attempts, total_merges, total_extras, total_successes);
13924 }
13925 \f
13926 static bool
13927 gate_handle_combine (void)
13928 {
13929   return (optimize > 0);
13930 }
13931
13932 /* Try combining insns through substitution.  */
13933 static unsigned int
13934 rest_of_handle_combine (void)
13935 {
13936   int rebuild_jump_labels_after_combine;
13937
13938   df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
13939   df_note_add_problem ();
13940   df_analyze ();
13941
13942   regstat_init_n_sets_and_refs ();
13943
13944   rebuild_jump_labels_after_combine
13945     = combine_instructions (get_insns (), max_reg_num ());
13946
13947   /* Combining insns may have turned an indirect jump into a
13948      direct jump.  Rebuild the JUMP_LABEL fields of jumping
13949      instructions.  */
13950   if (rebuild_jump_labels_after_combine)
13951     {
13952       timevar_push (TV_JUMP);
13953       rebuild_jump_labels (get_insns ());
13954       cleanup_cfg (0);
13955       timevar_pop (TV_JUMP);
13956     }
13957
13958   regstat_free_n_sets_and_refs ();
13959   return 0;
13960 }
13961
13962 struct rtl_opt_pass pass_combine =
13963 {
13964  {
13965   RTL_PASS,
13966   "combine",                            /* name */
13967   gate_handle_combine,                  /* gate */
13968   rest_of_handle_combine,               /* execute */
13969   NULL,                                 /* sub */
13970   NULL,                                 /* next */
13971   0,                                    /* static_pass_number */
13972   TV_COMBINE,                           /* tv_id */
13973   PROP_cfglayout,                       /* properties_required */
13974   0,                                    /* properties_provided */
13975   0,                                    /* properties_destroyed */
13976   0,                                    /* todo_flags_start */
13977   TODO_df_finish | TODO_verify_rtl_sharing |
13978   TODO_ggc_collect,                     /* todo_flags_finish */
13979  }
13980 };