gcc/config/nds32/nds32.h

   1 /* Definitions of target machine of Andes NDS32 cpu for GNU compiler
   2    Copyright (C) 2012-2015 Free Software Foundation, Inc.
   3    Contributed by Andes Technology Corporation.
   4
   5    This file is part of GCC.
   6
   7    GCC is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published
   9    by the Free Software Foundation; either version 3, or (at your
  10    option) any later version.
  11
  12    GCC is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with GCC; see the file COPYING3.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21
  22 /* ------------------------------------------------------------------------ */
  23
  24 /* The following are auxiliary macros or structure declarations
  25    that are used all over the nds32.c and nds32.h.  */
  26
  27 /* Use SYMBOL_FLAG_MACH_DEP to define our own symbol_ref flag.
  28    It is used in nds32_encode_section_info() to store flag in symbol_ref
  29    in case the symbol should be placed in .rodata section.
  30    So that we can check it in nds32_legitimate_address_p().  */
  31 #define NDS32_SYMBOL_FLAG_RODATA \
  32   (SYMBOL_FLAG_MACH_DEP << 0)
  33 #define NDS32_SYMBOL_REF_RODATA_P(x) \
  34   ((SYMBOL_REF_FLAGS (x) & NDS32_SYMBOL_FLAG_RODATA) != 0)
  35
  36 /* Computing the Length of an Insn.  */
  37 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
  38   (LENGTH = nds32_adjust_insn_length (INSN, LENGTH))
  39
  40 /* Check instruction LS-37-FP-implied form.
  41    Note: actually its immediate range is imm9u
  42          since it is used for lwi37/swi37 instructions.  */
  43 #define NDS32_LS_37_FP_P(rt, ra, imm)       \
  44   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  45    && REGNO (ra) == FP_REGNUM               \
  46    && satisfies_constraint_Iu09 (imm))
  47
  48 /* Check instruction LS-37-SP-implied form.
  49    Note: actually its immediate range is imm9u
  50          since it is used for lwi37/swi37 instructions.  */
  51 #define NDS32_LS_37_SP_P(rt, ra, imm)       \
  52   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  53    && REGNO (ra) == SP_REGNUM               \
  54    && satisfies_constraint_Iu09 (imm))
  55
  56
  57 /* Check load/store instruction form : Rt3, Ra3, imm3u.  */
  58 #define NDS32_LS_333_P(rt, ra, imm, mode) nds32_ls_333_p (rt, ra, imm, mode)
  59
  60 /* Check load/store instruction form : Rt4, Ra5, const_int_0.
  61    Note: no need to check ra because Ra5 means it covers all registers.  */
  62 #define NDS32_LS_450_P(rt, ra, imm)                     \
  63   ((imm == const0_rtx)                                  \
  64    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS         \
  65        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
  66
  67 /* Check instruction RRI-333-form.  */
  68 #define NDS32_RRI_333_P(rt, ra, imm)           \
  69   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS    \
  70    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS \
  71    && satisfies_constraint_Iu03 (imm))
  72
  73 /* Check instruction RI-45-form.  */
  74 #define NDS32_RI_45_P(rt, ra, imm)                     \
  75   (REGNO (rt) == REGNO (ra)                            \
  76    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS        \
  77        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS) \
  78    && satisfies_constraint_Iu05 (imm))
  79
  80
  81 /* Check instruction RR-33-form.  */
  82 #define NDS32_RR_33_P(rt, ra)                   \
  83   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS     \
  84    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS)
  85
  86 /* Check instruction RRR-333-form.  */
  87 #define NDS32_RRR_333_P(rt, ra, rb)             \
  88   (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS     \
  89    && REGNO_REG_CLASS (REGNO (ra)) == LOW_REGS  \
  90    && REGNO_REG_CLASS (REGNO (rb)) == LOW_REGS)
  91
  92 /* Check instruction RR-45-form.
  93    Note: no need to check rb because Rb5 means it covers all registers.  */
  94 #define NDS32_RR_45_P(rt, ra, rb)               \
  95   (REGNO (rt) == REGNO (ra)                     \
  96    && (REGNO_REG_CLASS (REGNO (rt)) == LOW_REGS \
  97        || REGNO_REG_CLASS (REGNO (rt)) == MIDDLE_REGS))
  98
  99 /* Classifies address type to distinguish 16-bit/32-bit format.  */
 100 enum nds32_16bit_address_type
 101 {
 102   /* [reg]: 45 format address.  */
 103   ADDRESS_REG,
 104   /* [lo_reg + imm3u]: 333 format address.  */
 105   ADDRESS_LO_REG_IMM3U,
 106   /* post_inc [lo_reg + imm3u]: 333 format address.  */
 107   ADDRESS_POST_INC_LO_REG_IMM3U,
 108   /* [$fp + imm7u]: fp imply address.  */
 109   ADDRESS_FP_IMM7U,
 110   /* [$sp + imm7u]: sp imply address.  */
 111   ADDRESS_SP_IMM7U,
 112   /* Other address format.  */
 113   ADDRESS_NOT_16BIT_FORMAT
 114 };
 115
 116
 117 /* ------------------------------------------------------------------------ */
 118
 119 /* Define maximum numbers of registers for passing arguments.  */
 120 #define NDS32_MAX_GPR_REGS_FOR_ARGS 6
 121
 122 /* Define the register number for first argument.  */
 123 #define NDS32_GPR_ARG_FIRST_REGNUM 0
 124
 125 /* Define the register number for return value.  */
 126 #define NDS32_GPR_RET_FIRST_REGNUM 0
 127
 128 /* Define the first integer register number.  */
 129 #define NDS32_FIRST_GPR_REGNUM 0
 130 /* Define the last integer register number.  */
 131 #define NDS32_LAST_GPR_REGNUM 31
 132
 133 /* Define double word alignment bits.  */
 134 #define NDS32_DOUBLE_WORD_ALIGNMENT 64
 135
 136 /* Define alignment checking macros for convenience.  */
 137 #define NDS32_HALF_WORD_ALIGN_P(value)   (((value) & 0x01) == 0)
 138 #define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0)
 139 #define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0)
 140
 141 /* Get alignment according to mode or type information.
 142    When 'type' is nonnull, there is no need to look at 'mode'.  */
 143 #define NDS32_MODE_TYPE_ALIGN(mode, type) \
 144   (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode))
 145
 146 /* Round X up to the nearest double word.  */
 147 #define NDS32_ROUND_UP_DOUBLE_WORD(value)  (((value) + 7) & ~7)
 148
 149
 150 /* This macro is used to calculate the numbers of registers for
 151    containing 'size' bytes of the argument.
 152    The size of a register is a word in nds32 target.
 153    So we use UNITS_PER_WORD to do the calculation.  */
 154 #define NDS32_NEED_N_REGS_FOR_ARG(mode, type)                            \
 155   ((mode == BLKmode)                                                     \
 156    ? ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)  \
 157    : ((GET_MODE_SIZE (mode)     + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
 158
 159 /* This macro is used to return the register number for passing argument.
 160    We need to obey the following rules:
 161      1. If it is required MORE THAN one register,
 162         we need to further check if it really needs to be
 163         aligned on double words.
 164           a) If double word alignment is necessary,
 165              the register number must be even value.
 166           b) Otherwise, the register number can be odd or even value.
 167      2. If it is required ONLY one register,
 168         the register number can be odd or even value.  */
 169 #define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type)  \
 170   ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1)                     \
 171    ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY)          \
 172       ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1)      \
 173       : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))                \
 174    : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM))
 175
 176 /* This macro is to check if there are still available registers
 177    for passing argument, which must be entirely in registers.  */
 178 #define NDS32_ARG_ENTIRE_IN_GPR_REG_P(reg_offset, mode, type)   \
 179   ((NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
 180     + NDS32_NEED_N_REGS_FOR_ARG (mode, type))                   \
 181    <= (NDS32_GPR_ARG_FIRST_REGNUM                               \
 182        + NDS32_MAX_GPR_REGS_FOR_ARGS))
 183
 184 /* This macro is to check if there are still available registers
 185    for passing argument, either entirely in registers or partially
 186    in registers.  */
 187 #define NDS32_ARG_PARTIAL_IN_GPR_REG_P(reg_offset, mode, type) \
 188   (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \
 189    < NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS)
 190
 191 /* This macro is to check if the register is required to be saved on stack.
 192    If call_used_regs[regno] == 0, regno is the callee-saved register.
 193    If df_regs_ever_live_p(regno) == true, it is used in the current function.
 194    As long as the register satisfies both criteria above,
 195    it is required to be saved.  */
 196 #define NDS32_REQUIRED_CALLEE_SAVED_P(regno)                  \
 197   ((!call_used_regs[regno]) && (df_regs_ever_live_p (regno)))
 198
 199 /* ------------------------------------------------------------------------ */
 200
 201 /* A C structure for machine-specific, per-function data.
 202    This is added to the cfun structure.  */
 203 struct GTY(()) machine_function
 204 {
 205   /* Number of bytes allocated on the stack for variadic args
 206      if we want to push them into stack as pretend arguments by ourself.  */
 207   int va_args_size;
 208   /* Number of bytes reserved on the stack for
 209      local and temporary variables.  */
 210   int local_size;
 211   /* Number of bytes allocated on the stack for outgoing arguments.  */
 212   int out_args_size;
 213
 214   /* Number of bytes on the stack for saving $fp.  */
 215   int fp_size;
 216   /* Number of bytes on the stack for saving $gp.  */
 217   int gp_size;
 218   /* Number of bytes on the stack for saving $lp.  */
 219   int lp_size;
 220
 221   /* Number of bytes on the stack for saving callee-saved registers.  */
 222   int callee_saved_regs_size;
 223   /* The padding bytes in callee-saved area may be required.  */
 224   int callee_saved_area_padding_bytes;
 225
 226   /* The first required callee-saved register.  */
 227   int callee_saved_regs_first_regno;
 228   /* The last required callee-saved register.  */
 229   int callee_saved_regs_last_regno;
 230
 231   /* The padding bytes in varargs area may be required.  */
 232   int va_args_area_padding_bytes;
 233
 234   /* The first required register that should be saved on stack for va_args.  */
 235   int va_args_first_regno;
 236   /* The last required register that should be saved on stack for va_args.  */
 237   int va_args_last_regno;
 238
 239   /* Indicate that whether this function needs
 240      prologue/epilogue code generation.  */
 241   int naked_p;
 242   /* Indicate that whether this function
 243      uses fp_as_gp optimization.  */
 244   int fp_as_gp_p;
 245 };
 246
 247 /* A C structure that contains the arguments information.  */
 248 typedef struct
 249 {
 250   unsigned int gpr_offset;
 251 } nds32_cumulative_args;
 252
 253 /* ------------------------------------------------------------------------ */
 254
 255 /* The following we define C-ISR related stuff.
 256    In nds32 architecture, we have 73 vectors for interrupt/exception.
 257    For each vector (except for vector 0, which is used for reset behavior),
 258    we allow users to set its register saving scheme and interrupt level.  */
 259
 260 /* There are 73 vectors in nds32 architecture.
 261    0 for reset handler,
 262    1-8 for exception handler,
 263    and 9-72 for interrupt handler.
 264    We use an array, which is defined in nds32.c, to record
 265    essential information for each vector.  */
 266 #define NDS32_N_ISR_VECTORS 73
 267
 268 /* Define possible isr category.  */
 269 enum nds32_isr_category
 270 {
 271   NDS32_ISR_NONE,
 272   NDS32_ISR_INTERRUPT,
 273   NDS32_ISR_EXCEPTION,
 274   NDS32_ISR_RESET
 275 };
 276
 277 /* Define isr register saving scheme.  */
 278 enum nds32_isr_save_reg
 279 {
 280   NDS32_SAVE_ALL,
 281   NDS32_PARTIAL_SAVE
 282 };
 283
 284 /* Define isr nested type.  */
 285 enum nds32_isr_nested_type
 286 {
 287   NDS32_NESTED,
 288   NDS32_NOT_NESTED,
 289   NDS32_NESTED_READY
 290 };
 291
 292 /* Define structure to record isr information.
 293    The isr vector array 'isr_vectors[]' with this structure
 294    is defined in nds32.c.  */
 295 struct nds32_isr_info
 296 {
 297   /* The field to identify isr category.
 298      It should be set to NDS32_ISR_NONE by default.
 299      If user specifies a function as isr by using attribute,
 300      this field will be set accordingly.  */
 301   enum nds32_isr_category category;
 302
 303   /* A string for the applied function name.
 304      It should be set to empty string by default.  */
 305   char func_name[100];
 306
 307   /* The register saving scheme.
 308      It should be set to NDS32_PARTIAL_SAVE by default
 309      unless user specifies attribute to change it.  */
 310   enum nds32_isr_save_reg save_reg;
 311
 312   /* The nested type.
 313      It should be set to NDS32_NOT_NESTED by default
 314      unless user specifies attribute to change it.  */
 315   enum nds32_isr_nested_type nested_type;
 316
 317   /* Total vectors.
 318      The total vectors = interrupt + exception numbers + reset.
 319      It should be set to 0 by default.
 320      This field is ONLY used in NDS32_ISR_RESET category.  */
 321   unsigned int total_n_vectors;
 322
 323   /* A string for nmi handler name.
 324      It should be set to empty string by default.
 325      This field is ONLY used in NDS32_ISR_RESET category.  */
 326   char nmi_name[100];
 327
 328   /* A string for warm handler name.
 329      It should be set to empty string by default.
 330      This field is ONLY used in NDS32_ISR_RESET category.  */
 331   char warm_name[100];
 332 };
 333
 334 /* ------------------------------------------------------------------------ */
 335
 336 /* Define code for all nds32 builtins.  */
 337 enum nds32_builtins
 338 {
 339   NDS32_BUILTIN_ISYNC,
 340   NDS32_BUILTIN_ISB,
 341   NDS32_BUILTIN_MFSR,
 342   NDS32_BUILTIN_MFUSR,
 343   NDS32_BUILTIN_MTSR,
 344   NDS32_BUILTIN_MTUSR,
 345   NDS32_BUILTIN_SETGIE_EN,
 346   NDS32_BUILTIN_SETGIE_DIS
 347 };
 348
 349 /* ------------------------------------------------------------------------ */
 350
 351 #define TARGET_ISA_V2   (nds32_arch_option == ARCH_V2)
 352 #define TARGET_ISA_V3   (nds32_arch_option == ARCH_V3)
 353 #define TARGET_ISA_V3M  (nds32_arch_option == ARCH_V3M)
 354
 355 #define TARGET_CMODEL_SMALL \
 356    (nds32_cmodel_option == CMODEL_SMALL)
 357 #define TARGET_CMODEL_MEDIUM \
 358    (nds32_cmodel_option == CMODEL_MEDIUM)
 359 #define TARGET_CMODEL_LARGE \
 360    (nds32_cmodel_option == CMODEL_LARGE)
 361
 362 /* When -mcmodel=small or -mcmodel=medium,
 363    compiler may generate gp-base instruction directly.  */
 364 #define TARGET_GP_DIRECT \
 365    (nds32_cmodel_option == CMODEL_SMALL\
 366     || nds32_cmodel_option == CMODEL_MEDIUM)
 367
 368 #define TARGET_SOFT_FLOAT 1
 369 #define TARGET_HARD_FLOAT 0
 370
 371 /* ------------------------------------------------------------------------ */
 372 \f
 373 /* Controlling the Compilation Driver.  */
 374
 375 #define OPTION_DEFAULT_SPECS \
 376   {"arch", "%{!march=*:-march=%(VALUE)}" }
 377
 378 #define CC1_SPEC \
 379   ""
 380
 381 #define ASM_SPEC \
 382   " %{mbig-endian:-EB} %{mlittle-endian:-EL}"
 383
 384 /* If user issues -mrelax, we need to pass '--relax' to linker.  */
 385 #define LINK_SPEC \
 386   " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \
 387   " %{mrelax:--relax}"
 388
 389 #define LIB_SPEC \
 390   " -lc -lgloss"
 391
 392 /* The option -mno-ctor-dtor can disable constructor/destructor feature
 393    by applying different crt stuff.  In the convention, crt0.o is the
 394    startup file without constructor/destructor;
 395    crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the
 396    startup files with constructor/destructor.
 397    Note that crt0.o, crt1.o, crti.o, and crtn.o are provided
 398    by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are
 399    currently provided by GCC for nds32 target.
 400
 401    For nds32 target so far:
 402    If -mno-ctor-dtor, we are going to link
 403    "crt0.o [user objects]".
 404    If general cases, we are going to link
 405    "crt1.o crtbegin1.o [user objects] crtend1.o".  */
 406 #define STARTFILE_SPEC \
 407   " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \
 408   " %{!mno-ctor-dtor:crtbegin1.o%s}"
 409 #define ENDFILE_SPEC \
 410   " %{!mno-ctor-dtor:crtend1.o%s}"
 411
 412 /* The TARGET_BIG_ENDIAN_DEFAULT is defined if we
 413    configure gcc with --target=nds32be-* setting.
 414    Check gcc/config.gcc for more information.  */
 415 #ifdef TARGET_BIG_ENDIAN_DEFAULT
 416 #  define NDS32_ENDIAN_DEFAULT "mbig-endian"
 417 #else
 418 #  define NDS32_ENDIAN_DEFAULT "mlittle-endian"
 419 #endif
 420
 421 /* Currently we only have elf toolchain,
 422    where -mcmodel=medium is always the default.  */
 423 #define NDS32_CMODEL_DEFAULT "mcmodel=medium"
 424
 425 #define MULTILIB_DEFAULTS \
 426   { NDS32_ENDIAN_DEFAULT, NDS32_CMODEL_DEFAULT }
 427
 428 \f
 429 /* Run-time Target Specification.  */
 430
 431 #define TARGET_CPU_CPP_BUILTINS()                     \
 432   do                                                  \
 433     {                                                 \
 434       builtin_define ("__nds32__");                   \
 435                                                       \
 436       if (TARGET_ISA_V2)                              \
 437         builtin_define ("__NDS32_ISA_V2__");          \
 438       if (TARGET_ISA_V3)                              \
 439         builtin_define ("__NDS32_ISA_V3__");          \
 440       if (TARGET_ISA_V3M)                             \
 441         builtin_define ("__NDS32_ISA_V3M__");         \
 442                                                       \
 443       if (TARGET_BIG_ENDIAN)                          \
 444         builtin_define ("__big_endian__");            \
 445       if (TARGET_REDUCED_REGS)                        \
 446         builtin_define ("__NDS32_REDUCED_REGS__");    \
 447       if (TARGET_CMOV)                                \
 448         builtin_define ("__NDS32_CMOV__");            \
 449       if (TARGET_PERF_EXT)                            \
 450         builtin_define ("__NDS32_PERF_EXT__");        \
 451       if (TARGET_16_BIT)                              \
 452         builtin_define ("__NDS32_16_BIT__");          \
 453       if (TARGET_GP_DIRECT)                           \
 454         builtin_define ("__NDS32_GP_DIRECT__");       \
 455                                                       \
 456       builtin_assert ("cpu=nds32");                   \
 457       builtin_assert ("machine=nds32");               \
 458     } while (0)
 459
 460 \f
 461 /* Defining Data Structures for Per-function Information.  */
 462
 463 /* This macro is called once per function,
 464    before generation of any RTL has begun.  */
 465 #define INIT_EXPANDERS  nds32_init_expanders ()
 466
 467 \f
 468 /* Storage Layout.  */
 469
 470 #define BITS_BIG_ENDIAN 0
 471
 472 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN)
 473
 474 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN)
 475
 476 #define UNITS_PER_WORD 4
 477
 478 #define PROMOTE_MODE(m, unsignedp, type)                                    \
 479   if (GET_MODE_CLASS (m) == MODE_INT && GET_MODE_SIZE (m) < UNITS_PER_WORD) \
 480     {                                                                       \
 481       (m) = SImode;                                                         \
 482     }
 483
 484 #define PARM_BOUNDARY 32
 485
 486 #define STACK_BOUNDARY 64
 487
 488 #define FUNCTION_BOUNDARY 32
 489
 490 #define BIGGEST_ALIGNMENT 64
 491
 492 #define EMPTY_FIELD_BOUNDARY 32
 493
 494 #define STRUCTURE_SIZE_BOUNDARY 8
 495
 496 #define STRICT_ALIGNMENT 1
 497
 498 #define PCC_BITFIELD_TYPE_MATTERS 1
 499
 500 \f
 501 /* Layout of Source Language Data Types.  */
 502
 503 #define INT_TYPE_SIZE           32
 504 #define SHORT_TYPE_SIZE         16
 505 #define LONG_TYPE_SIZE          32
 506 #define LONG_LONG_TYPE_SIZE     64
 507
 508 #define FLOAT_TYPE_SIZE         32
 509 #define DOUBLE_TYPE_SIZE        64
 510 #define LONG_DOUBLE_TYPE_SIZE   64
 511
 512 #define DEFAULT_SIGNED_CHAR 1
 513
 514 #define SIZE_TYPE "long unsigned int"
 515 #define PTRDIFF_TYPE "long int"
 516 #define WCHAR_TYPE "short unsigned int"
 517 #define WCHAR_TYPE_SIZE 16
 518
 519 \f
 520 /* Register Usage.  */
 521
 522 /* Number of actual hardware registers.
 523    The hardware registers are assigned numbers for the compiler
 524    from 0 to just below FIRST_PSEUDO_REGISTER.
 525    All registers that the compiler knows about must be given numbers,
 526    even those that are not normally considered general registers.  */
 527 #define FIRST_PSEUDO_REGISTER 34
 528
 529 /* An initializer that says which registers are used for fixed
 530    purposes all throughout the compiled code and are therefore
 531    not available for general allocation.
 532
 533    $r28 : $fp
 534    $r29 : $gp
 535    $r30 : $lp
 536    $r31 : $sp
 537
 538    caller-save registers: $r0 ~ $r5, $r16 ~ $r23
 539    callee-save registers: $r6 ~ $r10, $r11 ~ $r14
 540
 541    reserved for assembler : $r15
 542    reserved for other use : $r24, $r25, $r26, $r27 */
 543 #define FIXED_REGISTERS                 \
 544 { /* r0  r1  r2  r3  r4  r5  r6  r7  */ \
 545       0,  0,  0,  0,  0,  0,  0,  0,    \
 546   /* r8  r9  r10 r11 r12 r13 r14 r15 */ \
 547       0,  0,  0,  0,  0,  0,  0,  1,    \
 548   /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
 549       0,  0,  0,  0,  0,  0,  0,  0,    \
 550   /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
 551       1,  1,  1,  1,  0,  1,  0,  1,    \
 552   /* ARG_POINTER:32 */                  \
 553       1,                                \
 554   /* FRAME_POINTER:33 */                \
 555       1                                 \
 556 }
 557
 558 /* Identifies the registers that are not available for
 559    general allocation of values that must live across
 560    function calls -- so they are caller-save registers.
 561
 562    0 : callee-save registers
 563    1 : caller-save registers */
 564 #define CALL_USED_REGISTERS             \
 565 { /* r0  r1  r2  r3  r4  r5  r6  r7  */ \
 566       1,  1,  1,  1,  1,  1,  0,  0,    \
 567   /* r8  r9  r10 r11 r12 r13 r14 r15 */ \
 568       0,  0,  0,  0,  0,  0,  0,  1,    \
 569   /* r16 r17 r18 r19 r20 r21 r22 r23 */ \
 570       1,  1,  1,  1,  1,  1,  1,  1,    \
 571   /* r24 r25 r26 r27 r28 r29 r30 r31 */ \
 572       1,  1,  1,  1,  0,  1,  0,  1,    \
 573   /* ARG_POINTER:32 */                  \
 574       1,                                \
 575   /* FRAME_POINTER:33 */                \
 576       1                                 \
 577 }
 578
 579 /* In nds32 target, we have three levels of registers:
 580      LOW_COST_REGS    : $r0 ~ $r7
 581      MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19
 582      HIGH_COST_REGS   : $r12 ~ $r14, $r20 ~ $r31 */
 583 #define REG_ALLOC_ORDER           \
 584 {                                 \
 585    0,  1,  2,  3,  4,  5,  6,  7, \
 586    8,  9, 10, 11, 16, 17, 18, 19, \
 587   12, 13, 14, 15, 20, 21, 22, 23, \
 588   24, 25, 26, 27, 28, 29, 30, 31, \
 589   32,                             \
 590   33                              \
 591 }
 592
 593 /* Tell IRA to use the order we define rather than messing it up with its
 594    own cost calculations.  */
 595 #define HONOR_REG_ALLOC_ORDER optimize_size
 596
 597 /* The number of consecutive hard regs needed starting at
 598    reg "regno" for holding a value of mode "mode".  */
 599 #define HARD_REGNO_NREGS(regno, mode) nds32_hard_regno_nregs (regno, mode)
 600
 601 /* Value is 1 if hard register "regno" can hold a value
 602    of machine-mode "mode".  */
 603 #define HARD_REGNO_MODE_OK(regno, mode) nds32_hard_regno_mode_ok (regno, mode)
 604
 605 /* A C expression that is nonzero if a value of mode1
 606    is accessible in mode2 without copying.
 607    Define this macro to return nonzero in as many cases as possible
 608    since doing so will allow GCC to perform better register allocation.
 609    We can use general registers to tie QI/HI/SI modes together.  */
 610 #define MODES_TIEABLE_P(mode1, mode2)          \
 611   (GET_MODE_CLASS (mode1) == MODE_INT          \
 612    && GET_MODE_CLASS (mode2) == MODE_INT       \
 613    && GET_MODE_SIZE (mode1) <= UNITS_PER_WORD  \
 614    && GET_MODE_SIZE (mode2) <= UNITS_PER_WORD)
 615
 616 \f
 617 /* Register Classes.  */
 618
 619 /* In nds32 target, we have three levels of registers:
 620      Low cost regsiters    : $r0 ~ $r7
 621      Middle cost registers : $r8 ~ $r11, $r16 ~ $r19
 622      High cost registers   : $r12 ~ $r14, $r20 ~ $r31
 623
 624    In practice, we have MIDDLE_REGS cover LOW_REGS register class contents
 625    so that it provides more chance to use low cost registers.  */
 626 enum reg_class
 627 {
 628   NO_REGS,
 629   R15_TA_REG,
 630   STACK_REG,
 631   LOW_REGS,
 632   MIDDLE_REGS,
 633   HIGH_REGS,
 634   GENERAL_REGS,
 635   FRAME_REGS,
 636   ALL_REGS,
 637   LIM_REG_CLASSES
 638 };
 639
 640 #define N_REG_CLASSES (int) LIM_REG_CLASSES
 641
 642 #define REG_CLASS_NAMES \
 643 {                       \
 644   "NO_REGS",            \
 645   "R15_TA_REG",         \
 646   "STACK_REG",          \
 647   "LOW_REGS",           \
 648   "MIDDLE_REGS",        \
 649   "HIGH_REGS",          \
 650   "GENERAL_REGS",       \
 651   "FRAME_REGS",         \
 652   "ALL_REGS"            \
 653 }
 654
 655 #define REG_CLASS_CONTENTS \
 656 {                                                            \
 657   {0x00000000, 0x00000000}, /* NO_REGS     :              */ \
 658   {0x00008000, 0x00000000}, /* R15_TA_REG  : 15           */ \
 659   {0x80000000, 0x00000000}, /* STACK_REG   : 31           */ \
 660   {0x000000ff, 0x00000000}, /* LOW_REGS    : 0-7          */ \
 661   {0x000f0fff, 0x00000000}, /* MIDDLE_REGS : 0-11, 16-19  */ \
 662   {0xfff07000, 0x00000000}, /* HIGH_REGS   : 12-14, 20-31 */ \
 663   {0xffffffff, 0x00000000}, /* GENERAL_REGS: 0-31         */ \
 664   {0x00000000, 0x00000003}, /* FRAME_REGS  : 32, 33       */ \
 665   {0xffffffff, 0x00000003}  /* ALL_REGS    : 0-31, 32, 33 */ \
 666 }
 667
 668 #define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno)
 669
 670 #define BASE_REG_CLASS GENERAL_REGS
 671 #define INDEX_REG_CLASS GENERAL_REGS
 672
 673 /* Return nonzero if it is suitable for use as a
 674    base register in operand addresses.
 675    So far, we return nonzero only if "num" is a hard reg
 676    of the suitable class or a pseudo register which is
 677    allocated to a suitable hard reg.  */
 678 #define REGNO_OK_FOR_BASE_P(num) \
 679   ((num) < 32 || (unsigned) reg_renumber[num] < 32)
 680
 681 /* Return nonzero if it is suitable for use as a
 682    index register in operand addresses.
 683    So far, we return nonzero only if "num" is a hard reg
 684    of the suitable class or a pseudo register which is
 685    allocated to a suitable hard reg.
 686    The difference between an index register and a base register is that
 687    the index register may be scaled.  */
 688 #define REGNO_OK_FOR_INDEX_P(num) \
 689   ((num) < 32 || (unsigned) reg_renumber[num] < 32)
 690
 691 \f
 692 /* Obsolete Macros for Defining Constraints.  */
 693
 694 \f
 695 /* Stack Layout and Calling Conventions.  */
 696
 697 #define STACK_GROWS_DOWNWARD
 698
 699 #define FRAME_GROWS_DOWNWARD 1
 700
 701 #define STARTING_FRAME_OFFSET 0
 702
 703 #define STACK_POINTER_OFFSET 0
 704
 705 #define FIRST_PARM_OFFSET(fundecl) \
 706   (NDS32_DOUBLE_WORD_ALIGN_P (crtl->args.pretend_args_size) ? 0 : 4)
 707
 708 #define RETURN_ADDR_RTX(count, frameaddr) \
 709   nds32_return_addr_rtx (count, frameaddr)
 710
 711 /* A C expression whose value is RTL representing the location
 712    of the incoming return address at the beginning of any function
 713    before the prologue.
 714    If this RTL is REG, you should also define
 715    DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO).  */
 716 #define INCOMING_RETURN_ADDR_RTX    gen_rtx_REG (Pmode, LP_REGNUM)
 717 #define DWARF_FRAME_RETURN_COLUMN   DWARF_FRAME_REGNUM (LP_REGNUM)
 718
 719 #define STACK_POINTER_REGNUM SP_REGNUM
 720
 721 #define FRAME_POINTER_REGNUM 33
 722
 723 #define HARD_FRAME_POINTER_REGNUM FP_REGNUM
 724
 725 #define ARG_POINTER_REGNUM 32
 726
 727 #define STATIC_CHAIN_REGNUM 16
 728
 729 #define ELIMINABLE_REGS                                \
 730 { { ARG_POINTER_REGNUM,   STACK_POINTER_REGNUM },      \
 731   { ARG_POINTER_REGNUM,   HARD_FRAME_POINTER_REGNUM }, \
 732   { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },      \
 733   { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM } }
 734
 735 #define INITIAL_ELIMINATION_OFFSET(from_reg, to_reg, offset_var) \
 736   (offset_var) = nds32_initial_elimination_offset (from_reg, to_reg)
 737
 738 #define ACCUMULATE_OUTGOING_ARGS 1
 739
 740 #define OUTGOING_REG_PARM_STACK_SPACE(fntype) 1
 741
 742 #define CUMULATIVE_ARGS nds32_cumulative_args
 743
 744 #define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
 745   nds32_init_cumulative_args (&cum, fntype, libname, fndecl, n_named_args)
 746
 747 /* The REGNO is an unsigned integer but NDS32_GPR_ARG_FIRST_REGNUM may be 0.
 748    We better cast REGNO into signed integer so that we can avoid
 749    'comparison of unsigned expression >= 0 is always true' warning.  */
 750 #define FUNCTION_ARG_REGNO_P(regno)                                        \
 751   (((int) regno - NDS32_GPR_ARG_FIRST_REGNUM >= 0)                         \
 752    && ((int) regno - NDS32_GPR_ARG_FIRST_REGNUM < NDS32_MAX_GPR_REGS_FOR_ARGS))
 753
 754 #define DEFAULT_PCC_STRUCT_RETURN 0
 755
 756 /* EXIT_IGNORE_STACK should be nonzero if, when returning
 757    from a function, the stack pointer does not matter.
 758    The value is tested only in functions that have frame pointers.
 759    In nds32 target, the function epilogue recovers the
 760    stack pointer from the frame.  */
 761 #define EXIT_IGNORE_STACK 1
 762
 763 #define FUNCTION_PROFILER(file, labelno) \
 764   fprintf (file, "/* profiler %d */", (labelno))
 765
 766 \f
 767 /* Implementing the Varargs Macros.  */
 768
 769 \f
 770 /* Trampolines for Nested Functions.  */
 771
 772 /* Giving A-function and B-function,
 773    if B-function wants to call A-function's nested function,
 774    we need to fill trampoline code into A-function's stack
 775    so that B-function can execute the code in stack to indirectly
 776    jump to (like 'trampoline' action) desired nested function.
 777
 778    The trampoline code for nds32 target must contains following parts:
 779
 780      1. instructions (4 * 4 = 16 bytes):
 781           get $pc first
 782           load chain_value to static chain register via $pc
 783           load nested function address to $r15 via $pc
 784           jump to desired nested function via $r15
 785      2. data (4 * 2 = 8 bytes):
 786           chain_value
 787           nested function address
 788
 789    Please check nds32.c implementation for more information.  */
 790 #define TRAMPOLINE_SIZE 24
 791
 792 /* Because all instructions/data in trampoline template are 4-byte size,
 793    we set trampoline alignment 8*4=32 bits.  */
 794 #define TRAMPOLINE_ALIGNMENT 32
 795
 796 \f
 797 /* Implicit Calls to Library Routines.  */
 798
 799 \f
 800 /* Addressing Modes.  */
 801
 802 /* We can use "LWI.bi  Rt, [Ra], 4" to support post increment.  */
 803 #define HAVE_POST_INCREMENT 1
 804 /* We can use "LWI.bi  Rt, [Ra], -4" to support post decrement.  */
 805 #define HAVE_POST_DECREMENT 1
 806
 807 /* We have "LWI.bi  Rt, [Ra], imm" instruction form.  */
 808 #define HAVE_POST_MODIFY_DISP 1
 809 /* We have "LW.bi   Rt, [Ra], Rb" instruction form.  */
 810 #define HAVE_POST_MODIFY_REG  1
 811
 812 #define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE)
 813
 814 #define MAX_REGS_PER_ADDRESS 2
 815
 816 \f
 817 /* Anchored Addresses.  */
 818
 819 \f
 820 /* Condition Code Status.  */
 821
 822 \f
 823 /* Describing Relative Costs of Operations.  */
 824
 825 /* A C expression for the cost of a branch instruction.
 826    A value of 1 is the default;
 827    other values are interpreted relative to that.  */
 828 #define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 0)
 829
 830 #define SLOW_BYTE_ACCESS 1
 831
 832 #define NO_FUNCTION_CSE
 833
 834 \f
 835 /* Adjusting the Instruction Scheduler.  */
 836
 837 \f
 838 /* Dividing the Output into Sections (Texts, Data, . . . ).  */
 839
 840 #define TEXT_SECTION_ASM_OP     "\t.text"
 841 #define DATA_SECTION_ASM_OP     "\t.data"
 842
 843 /* Currently, nds32 assembler does NOT handle '.bss' pseudo-op.
 844    So we use '.section .bss' alternatively.  */
 845 #define BSS_SECTION_ASM_OP      "\t.section\t.bss"
 846
 847 /* Define this macro to be an expression with a nonzero value if jump tables
 848    (for tablejump insns) should be output in the text section,
 849    along with the assembler instructions.
 850    Otherwise, the readonly data section is used.  */
 851 #define JUMP_TABLES_IN_TEXT_SECTION 1
 852
 853 \f
 854 /* Position Independent Code.  */
 855
 856 #define PIC_OFFSET_TABLE_REGNUM GP_REGNUM
 857
 858 \f
 859 /* Defining the Output Assembler Language.  */
 860
 861 #define ASM_COMMENT_START "!"
 862
 863 #define ASM_APP_ON "! #APP"
 864
 865 #define ASM_APP_OFF "! #NO_APP\n"
 866
 867 #define ASM_OUTPUT_LABELREF(stream, name) \
 868   asm_fprintf (stream, "%U%s", (*targetm.strip_name_encoding) (name))
 869
 870 #define ASM_OUTPUT_SYMBOL_REF(stream, sym) \
 871   assemble_name (stream, XSTR (sym, 0))
 872
 873 #define ASM_OUTPUT_LABEL_REF(stream, buf) \
 874   assemble_name (stream, buf)
 875
 876 #define LOCAL_LABEL_PREFIX "."
 877
 878 #define REGISTER_NAMES                                            \
 879 {                                                                 \
 880   "$r0",  "$r1",  "$r2",  "$r3",  "$r4",  "$r5",  "$r6",  "$r7",  \
 881   "$r8",  "$r9",  "$r10", "$r11", "$r12", "$r13", "$r14", "$ta",  \
 882   "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \
 883   "$r24", "$r25", "$r26", "$r27", "$fp",  "$gp",  "$lp",  "$sp",  \
 884   "$AP",                                                          \
 885   "$SFP"                                                          \
 886 }
 887
 888 /* Output normal jump table entry.  */
 889 #define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \
 890   asm_fprintf (stream, "\t.word\t%LL%d\n", value)
 891
 892 /* Output pc relative jump table entry.  */
 893 #define ASM_OUTPUT_ADDR_DIFF_ELT(stream, body, value, rel)              \
 894   do                                                                    \
 895     {                                                                   \
 896       switch (GET_MODE (body))                                          \
 897         {                                                               \
 898         case QImode:                                                    \
 899           asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel);     \
 900           break;                                                        \
 901         case HImode:                                                    \
 902           asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel);    \
 903           break;                                                        \
 904         case SImode:                                                    \
 905           asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel);     \
 906           break;                                                        \
 907         default:                                                        \
 908           gcc_unreachable();                                            \
 909         }                                                               \
 910     } while (0)
 911
 912 /* We have to undef it first because elfos.h formerly define it
 913    check gcc/config.gcc and gcc/config/elfos.h for more information.  */
 914 #undef  ASM_OUTPUT_CASE_LABEL
 915 #define ASM_OUTPUT_CASE_LABEL(stream, prefix, num, table)          \
 916   do                                                               \
 917     {                                                              \
 918       asm_fprintf (stream, "\t! Jump Table Begin\n");              \
 919       (*targetm.asm_out.internal_label) (stream, prefix, num);     \
 920     } while (0)
 921
 922 #define ASM_OUTPUT_CASE_END(stream, num, table)        \
 923   do                                                   \
 924     {                                                  \
 925       /* Because our jump table is in text section,    \
 926          we need to make sure 2-byte alignment after   \
 927          the jump table for instructions fetch.  */    \
 928       if (GET_MODE (PATTERN (table)) == QImode)        \
 929         ASM_OUTPUT_ALIGN (stream, 1);                  \
 930       asm_fprintf (stream, "\t! Jump Table End\n");    \
 931     }  while (0)
 932
 933 /* This macro is not documented yet.
 934    But we do need it to make jump table vector aligned.  */
 935 #define ADDR_VEC_ALIGN(JUMPTABLE) 2
 936
 937 #define DWARF2_UNWIND_INFO 1
 938
 939 #define JUMP_ALIGN(x) \
 940   (align_jumps_log ? align_jumps_log : nds32_target_alignment (x))
 941
 942 #define LOOP_ALIGN(x) \
 943   (align_loops_log ? align_loops_log : nds32_target_alignment (x))
 944
 945 #define LABEL_ALIGN(x) \
 946   (align_labels_log ? align_labels_log : nds32_target_alignment (x))
 947
 948 #define ASM_OUTPUT_ALIGN(stream, power) \
 949   fprintf (stream, "\t.align\t%d\n", power)
 950
 951 \f
 952 /* Controlling Debugging Information Format.  */
 953
 954 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG
 955
 956 #define DWARF2_DEBUGGING_INFO 1
 957
 958 #define DWARF2_ASM_LINE_DEBUG_INFO 1
 959
 960 \f
 961 /* Cross Compilation and Floating Point.  */
 962
 963 \f
 964 /* Mode Switching Instructions.  */
 965
 966 \f
 967 /* Defining target-specific uses of __attribute__.  */
 968
 969 \f
 970 /* Emulating TLS.  */
 971
 972 \f
 973 /* Defining coprocessor specifics for MIPS targets.  */
 974
 975 \f
 976 /* Parameters for Precompiled Header Validity Checking.  */
 977
 978 \f
 979 /* C++ ABI parameters.  */
 980
 981 \f
 982 /* Adding support for named address spaces.  */
 983
 984 \f
 985 /* Miscellaneous Parameters.  */
 986
 987 /* This is the machine mode that elements of a jump-table should have.  */
 988 #define CASE_VECTOR_MODE Pmode
 989
 990 /* Return the preferred mode for and addr_diff_vec when the mininum
 991    and maximum offset are known.  */
 992 #define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body)  \
 993    ((min_offset < 0 || max_offset >= 0x2000 ) ? SImode          \
 994    : (max_offset >= 100) ? HImode                               \
 995    : QImode)
 996
 997 /* Generate pc relative jump table when -fpic or -Os.  */
 998 #define CASE_VECTOR_PC_RELATIVE (flag_pic || optimize_size)
 999
1000 /* Define this macro if operations between registers with integral mode
1001    smaller than a word are always performed on the entire register.  */
1002 #define WORD_REGISTER_OPERATIONS
1003
1004 /* A C expression indicating when insns that read memory in mem_mode,
1005    an integral mode narrower than a word, set the bits outside of mem_mode
1006    to be either the sign-extension or the zero-extension of the data read.  */
1007 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1008
1009 /* The maximum number of bytes that a single instruction can move quickly
1010    between memory and registers or between two memory locations.  */
1011 #define MOVE_MAX 4
1012
1013 /* A C expression that is nonzero if on this machine the number of bits
1014    actually used for the count of a shift operation is equal to the number
1015    of bits needed to represent the size of the object being shifted.  */
1016 #define SHIFT_COUNT_TRUNCATED 1
1017
1018 /* A C expression which is nonzero if on this machine it is safe to "convert"
1019    an integer of 'inprec' bits to one of 'outprec' bits by merely operating
1020    on it as if it had only 'outprec' bits.  */
1021 #define TRULY_NOOP_TRUNCATION(outprec, inprec) 1
1022
1023 /* A C expression describing the value returned by a comparison operator with
1024    an integral mode and stored by a store-flag instruction ('cstoremode4')
1025    when the condition is true.  */
1026 #define STORE_FLAG_VALUE 1
1027
1028 /* An alias for the machine mode for pointers.  */
1029 #define Pmode SImode
1030
1031 /* An alias for the machine mode used for memory references to functions
1032    being called, in call RTL expressions.  */
1033 #define FUNCTION_MODE SImode
1034
1035 /* ------------------------------------------------------------------------ */