1 ;; C-SKY FPUV3 instruction descriptions.
2 ;; Copyright (C) 2018-2022 Free Software Foundation, Inc.
3 ;; Contributed by C-SKY Microsystems and Mentor Graphics.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful, but
13 ;; WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 ;; General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>. */
21 (define_c_enum "unspec" [
26 ;; -------------------------------------------------------------------------
27 ;; Float mov instructions
28 ;; -------------------------------------------------------------------------
30 (define_insn "*fpv3_movhf"
31 [(set (match_operand:HF 0 "nonimmediate_operand" "=r,r,v,r,m,r,Q,v,v,v, v")
32 (match_operand:HF 1 "general_operand" " r,F,r,v,r,m,v,Q,v,W,Dv"))]
33 "CSKY_ISA_FEATURE(fpv3_hf)"
35 switch (which_alternative)
38 return \"fmtvr.16\\t%0, %1\";
40 return \"fmfvr.16\\t%0, %1\";
44 return fpuv3_output_move(operands);
46 return \"fmov.16\\t%0, %1\";
48 return \"fmovi.16\\t%0, %1\";
54 bits = real_to_target (NULL, CONST_DOUBLE_REAL_VALUE (operands[1]), HFmode);
56 ops[1] = GEN_INT (bits);
58 output_asm_insn (\"lrw\\t%0, %1\", ops);
62 return csky_output_move(insn, operands, HFmode);
67 (define_insn "*fpv3_movsf"
68 [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r, r,m,v,r,Q,v,v,v, v")
69 (match_operand:SF 1 "general_operand" " r,m,mF,r,r,v,v,Q,v,W,Dv"))]
70 "CSKY_ISA_FEATURE(fpv3_sf)"
72 switch (which_alternative)
75 return \"fmtvr.32.1\\t%0, %1\";
77 return \"fmfvr.32.1\\t%0, %1\";
81 return fpuv3_output_move(operands);
83 return \"fmov.32\\t%0, %1\";
85 return \"fmovi.32\\t%0, %1\";
87 return csky_output_move(insn, operands, SFmode);
92 (define_insn "*fpv3_movdf"
93 [(set (match_operand:DF 0 "nonimmediate_operand" "=r, v,?r,Q,v,v,v, v,r, r,Y")
94 (match_operand:DF 1 "general_operand" " r,?r, v,v,Q,v,m,Dv,Y,YF,r"))]
95 "CSKY_ISA_FEATURE(fpv3_df)"
97 switch (which_alternative)
100 if (TARGET_BIG_ENDIAN)
101 return \"fmtvr.64\\t%0, %R1, %1\";
102 return \"fmtvr.64\\t%0, %1, %R1\";
104 if (TARGET_BIG_ENDIAN)
105 return \"fmfvr.64\\t%R0, %0, %1\";
106 return \"fmfvr.64\\t%0, %R0, %1\";
110 return fpuv3_output_move(operands);
112 return \"fmov.64\\t%0, %1\";
114 return \"fmovi.64\\t%0, %1\";
116 return csky_output_movedouble(operands, DFmode);
121 ;; -------------------------------------------------------------------------
122 ;; Float Mul instructions
123 ;; -------------------------------------------------------------------------
125 (define_insn "*fpv3_mul<mode>3"
126 [(set (match_operand:F3ANY 0 "register_operand" "=v")
127 (mult:F3ANY (match_operand:F3ANY 1 "register_operand" " v")
128 (match_operand:F3ANY 2 "register_operand" " v")))]
129 "CSKY_ISA_FEATURE(fpv3_<mode>)"
130 "fmul.<f3t>\t%0, %1, %2"
133 ;; -------------------------------------------------------------------------
134 ;; Float Muladd and mulsub instructions
135 ;; -------------------------------------------------------------------------
137 (define_insn "*fpv3_mula<mode>3"
138 [(set (match_operand:F3ANY 0 "register_operand" "+v")
139 (plus:F3ANY (mult:F3ANY (match_operand:F3ANY 1 "register_operand" " v")
140 (match_operand:F3ANY 2 "register_operand" " v"))
142 "CSKY_ISA_FEATURE(fpv3_<mode>)"
143 "fmula.<f3t>\t%0, %1, %2"
146 (define_insn "*fpv3_muls<mode>3"
147 [(set (match_operand:F3ANY 0 "register_operand" "+v")
148 (minus:F3ANY (match_dup 0)
149 (mult:F3ANY (match_operand:F3ANY 1 "register_operand" " v")
150 (match_operand:F3ANY 2 "register_operand" " v"))))]
151 "CSKY_ISA_FEATURE(fpv3_<mode>)"
152 "fmuls.<f3t>\t%0, %1, %2"
155 ;; -------------------------------------------------------------------------
156 ;; Float fmula/fmuls/fnmula/fnmuls instructions
157 ;; -------------------------------------------------------------------------
159 (define_insn "*fpv3_fmuls_<mode>4"
160 [(set (match_operand:F3ANY 0 "register_operand" "=v")
161 (fma:F3ANY (neg:F3ANY (match_operand:F3ANY 1 "register_operand" "v"))
162 (match_operand:F3ANY 2 "register_operand" "v")
163 (match_operand:F3ANY 3 "register_operand" "0")))]
164 "CSKY_ISA_FEATURE(fpv3_<mode>)"
165 "ffmuls.<f3t>\t%0, %1, %2"
168 (define_insn "*fpv3_fmula_<mode>4"
169 [(set (match_operand:F3ANY 0 "register_operand" "=v")
170 (fma:F3ANY (match_operand:F3ANY 1 "register_operand" " v")
171 (match_operand:F3ANY 2 "register_operand" " v")
172 (match_operand:F3ANY 3 "register_operand" "0")))]
173 "CSKY_ISA_FEATURE(fpv3_<mode>)"
174 "ffmula.<f3t>\t%0, %1, %2"
177 (define_insn "*fpv3_fnmula_<mode>4"
178 [(set (match_operand:F3ANY 0 "register_operand" "=v")
179 (neg: F3ANY (fma:F3ANY (match_operand:F3ANY 1 "register_operand" " v")
180 (match_operand:F3ANY 2 "register_operand" " v")
181 (match_operand:F3ANY 3 "register_operand" "0"))))]
182 "CSKY_ISA_FEATURE(fpv3_<mode>)"
183 "ffnmula.<f3t>\t%0, %1, %2"
186 (define_insn "*fpv3_fnmuls_<mode>4"
187 [(set (match_operand:F3ANY 0 "register_operand" "=v")
188 (fma:F3ANY (match_operand:F3ANY 1 "register_operand" " v")
189 (match_operand:F3ANY 2 "register_operand" " v")
190 (neg:F3ANY (match_operand:F3ANY 3 "register_operand" "0"))))]
191 "CSKY_ISA_FEATURE(fpv3_sf)"
192 "ffnmuls.<f3t>\t%0, %1, %2"
195 ;; -------------------------------------------------------------------------
196 ;; Float div/recipe/sqrt instructions
197 ;; -------------------------------------------------------------------------
199 (define_insn "*fpv3_div<mode>3"
200 [(set (match_operand:F3ANY 0 "register_operand" "=v")
201 (div:F3ANY (match_operand:F3ANY 1 "register_operand" " v")
202 (match_operand:F3ANY 2 "register_operand" " v")))]
203 "CSKY_ISA_FEATURE(fpv3_<mode>)"
204 "fdiv.<f3t>\t%0, %1, %2"
207 (define_insn "*fpv3_recip<mode>3"
208 [(set (match_operand:F3ANY 0 "register_operand" "=v")
209 (div:F3ANY (match_operand:F3ANY 1 "csky_const_float1_operand" " i")
210 (match_operand:F3ANY 2 "register_operand" " v")))]
211 "CSKY_ISA_FEATURE(fpv3_<mode>)"
212 "frecip.<f3t>\t%0, %2"
215 (define_insn "*fpv3_sqrt<mode>2"
216 [(set (match_operand:F3ANY 0 "register_operand" "=v")
217 (sqrt:F3ANY (match_operand:F3ANY 1 "register_operand" " v")))]
218 "CSKY_ISA_FEATURE(fpv3_<mode>)"
219 "fsqrt.<f3t>\t%0, %1"
222 ;; -------------------------------------------------------------------------
223 ;; Float fmax/fmin instructions
224 ;; -------------------------------------------------------------------------
226 (define_insn "fmax<mode>3"
227 [(set (match_operand:F3ANY 0 "register_operand" "=v")
228 (unspec:F3ANY [(match_operand:F3ANY 1 "register_operand" " v")
229 (match_operand:F3ANY 2 "register_operand" " v")]
231 "CSKY_ISA_FEATURE(fpv3_<mode>)"
232 "fmaxnm.<f3t>\t%0, %1, %2"
235 (define_insn "fmin<mode>3"
236 [(set (match_operand:F3ANY 0 "register_operand" "=v")
237 (unspec:F3ANY [(match_operand:F3ANY 1 "register_operand" " v")
238 (match_operand:F3ANY 2 "register_operand" " v")]
240 "CSKY_ISA_FEATURE(fpv3_<mode>)"
241 "fminnm.<f3t>\t%0, %1, %2"
244 ;; -------------------------------------------------------------------------
245 ;; Float compare instructions
246 ;; -------------------------------------------------------------------------
248 (define_insn "*fpv3_<zero_inst>_<mode>3"
249 [(set (reg:CC CSKY_CC_REGNUM)
250 (FCMPZ:CC (match_operand:F3ANY 0 "register_operand" "v")
251 (match_operand:F3ANY 1 "csky_const_float0_operand" "i")))]
252 "CSKY_ISA_FEATURE(fpv3_<mode>)"
253 "fcmp<zero_inst>.<f3t>\t%0"
256 (define_insn "*fpv3_<reg_inst>_<mode>3"
257 [(set (reg:CC CSKY_CC_REGNUM)
258 (FCMP:CC (match_operand:F3ANY 0 "register_operand" "v")
259 (match_operand:F3ANY 1 "register_operand" "v")))]
260 "CSKY_ISA_FEATURE(fpv3_<mode>)"
261 "fcmp<reg_inst>.<f3t>\t%0, %1"
264 (define_insn "*fpv3_gt<mode>3"
265 [(set (reg:CC CSKY_CC_REGNUM)
266 (gt:CC (match_operand:F3ANY 0 "register_operand" "v")
267 (match_operand:F3ANY 1 "register_operand" "v")))]
268 "CSKY_ISA_FEATURE(fpv3_<mode>)"
269 "fcmplt.<f3t>\t%1, %0"
272 (define_insn "*fpv3_le<mode>3"
273 [(set (reg:CC CSKY_CC_REGNUM)
274 (le:CC (match_operand:F3ANY 0 "register_operand" "v")
275 (match_operand:F3ANY 1 "register_operand" "v")))]
276 "CSKY_ISA_FEATURE(fpv3_<mode>)"
277 "fcmphs.<f3t>\t%1, %0"
280 (define_insn "*fpv3_unordered"
281 [(set (reg:CC CSKY_CC_REGNUM)
282 (unordered:CC (match_operand:F3ANY 0 "register_operand" "v")
283 (match_operand:F3ANY 1 "register_operand" "v")))]
284 "CSKY_ISA_FEATURE(fpv3_<mode>)"
285 "fcmpuo.<f3t>\t%0, %1")
287 (define_insn "*fpv3_unordered_zero"
288 [(set (reg:CC CSKY_CC_REGNUM)
289 (unordered:CC (match_operand:F3ANY 0 "register_operand" "v")
290 (match_operand:F3ANY 1 "csky_const_float0_operand" "i")))]
291 "CSKY_ISA_FEATURE(fpv3_<mode>)"
294 ;; -------------------------------------------------------------------------
295 ;; Float ADD instructions
296 ;; -------------------------------------------------------------------------
298 (define_insn "*fpv3_add<mode>3"
299 [(set (match_operand:F3ANY 0 "register_operand" "=v")
300 (plus:F3ANY (match_operand:F3ANY 1 "register_operand" " v")
301 (match_operand:F3ANY 2 "register_operand" " v")))]
302 "CSKY_ISA_FEATURE(fpv3_<mode>)"
303 "fadd.<f3t>\t%0, %1, %2"
306 ;; -------------------------------------------------------------------------
307 ;; Float SUB instructions
308 ;; -------------------------------------------------------------------------
310 (define_insn "*fpv3_sub<mode>3"
311 [(set (match_operand:F3ANY 0 "register_operand" "=v")
312 (minus:F3ANY (match_operand:F3ANY 1 "register_operand" " v")
313 (match_operand:F3ANY 2 "register_operand" " v")))]
314 "CSKY_ISA_FEATURE(fpv3_<mode>)"
315 "fsub.<f3t>\t%0, %1, %2"
318 ;; -------------------------------------------------------------------------
319 ;; Float NEG instructions
320 ;; -------------------------------------------------------------------------
322 (define_insn "*fpv3_neg<mode>2"
323 [(set (match_operand:F3ANY 0 "register_operand" "=v")
324 (neg:F3ANY (match_operand:F3ANY 1 "register_operand" " v")))]
325 "CSKY_ISA_FEATURE(fpv3_<mode>)"
329 ;; -------------------------------------------------------------------------
330 ;; Float ABS instructions
331 ;; -------------------------------------------------------------------------
333 (define_insn "*fpv3_abs<mode>2"
334 [(set (match_operand:F3ANY 0 "register_operand" "=v")
335 (abs:F3ANY (match_operand:F3ANY 1 "register_operand" " v")))]
336 "CSKY_ISA_FEATURE(fpv3_<mode>)"
340 ;; -------------------------------------------------------------------------
341 ;; Float common convert instructions
342 ;; -------------------------------------------------------------------------
345 (define_insn "*fpv3_extendhfsf2"
346 [(set (match_operand:SF 0 "register_operand" "=v")
347 (float_extend:SF (match_operand:HF 1 "register_operand" "v")))]
348 "CSKY_ISA_FEATURE(fpv3_hf)"
352 (define_insn "*fpv3_truncsfhf2"
353 [(set (match_operand:HF 0 "register_operand" "=v")
354 (float_truncate:HF (match_operand:SF 1 "register_operand" "v")))]
355 "CSKY_ISA_FEATURE(fpv3_hf)"
359 (define_insn "*fpv3_extendsfdf2"
360 [(set (match_operand:DF 0 "register_operand" "=v")
361 (float_extend:DF (match_operand:SF 1 "register_operand" "v")))]
362 "CSKY_ISA_FEATURE(fpv3_df)"
366 (define_insn "*fpv3_truncdfsf2"
367 [(set (match_operand:SF 0 "register_operand" "=v")
368 (float_truncate:SF (match_operand:DF 1 "register_operand" "v")))]
369 "CSKY_ISA_FEATURE(fpv3_df)"
372 ;; DF,SF,HF <- unsigned SI,SI
373 (define_insn "*fpv3_float<floatsuop>si<mode>2"
374 [(set (match_operand:F3ANY 0 "register_operand" "=v")
375 (FLOAT_SU:F3ANY (match_operand:SI 1 "register_operand" "v")))]
376 "CSKY_ISA_FEATURE(fpv3_<mode>)"
377 "fitof.<floatsu>32.f<f3t>\t%0, %1")
379 ;; HF <- unsigned HI,HI
380 (define_insn "*fpv3_float<floatsuop>hihf2"
381 [(set (match_operand:HF 0 "register_operand" "=v")
382 (FLOAT_SU:HF (match_operand:HI 1 "register_operand" "v")))]
383 "CSKY_ISA_FEATURE(fpv3_hi) && CSKY_ISA_FEATURE(fpv3_hf)"
384 "fitof.<floatsu>16.f16\t%0, %1")
386 ;; unsigned SI,SI <- DF,SF,HF
387 (define_insn "*fpv3_fix<fixsuop>_trunc<mode>si2"
388 [(set (match_operand:SI 0 "register_operand" "=v")
389 (FIX_SU:SI (fix:F3ANY (match_operand:F3ANY 1 "register_operand" "v"))))]
390 "CSKY_ISA_FEATURE(fpv3_<mode>)"
391 "fftoi.f<f3t>.<fixsu>32.rz\t%0, %1")
393 ;; -------------------------------------------------------------------------
394 ;; Float complex convert instructions
395 ;; -------------------------------------------------------------------------
397 ;; Fixed point to floating point conversions.
399 ;(define_insn "*combine_fcvt_fixed16_<mode>"
400 ; [(set (match_operand:F3ANY 0 "register_operand" "=v")
401 ; (mult:F3ANY (float:F3ANY (match_operand:HI 1 "register_operand" "0"))
403 ; "const_double_fcvt_power_of_two_reciprocal_hq" "Dt")))]
404 ; "CSKY_ISA_FEATURE(fpv3_<mode>) && !flag_rounding_math
405 ; && CSKY_ISA_FEATURE(fpv3_hi)"
406 ; "fxtof.s16.f<f3t>\t%0, %1, %v2")
408 ;(define_insn "*combine_fcvt_fixed32_<mode>"
409 ; [(set (match_operand:F3ANY 0 "register_operand" "=v")
410 ; (mult:F3ANY (float:F3ANY (match_operand:SI 1 "register_operand" "0"))
412 ; "const_double_fcvt_power_of_two_reciprocal_sq" "Dt")))]
413 ; "CSKY_ISA_FEATURE(fpv3_<mode>) && !flag_rounding_math"
414 ; "fxtof.s32.f<f3t>\t%0, %1, %v2")
416 ;(define_insn "*combine_fcvt_unfixed16_<mode>"
417 ; [(set (match_operand:F3ANY 0 "register_operand" "=v")
418 ; (mult:F3ANY (unsigned_float:F3ANY (match_operand:HI 1 "register_operand" "0"))
420 ; "const_double_fcvt_power_of_two_reciprocal_hq" "Dt")))]
421 ; "CSKY_ISA_FEATURE(fpv3_<mode>) && !flag_rounding_math
422 ; && CSKY_ISA_FEATURE(fpv3_hi)"
423 ; "fxtof.u16.f<f3t>\t%0, %1, %v2")
425 ;(define_insn "*combine_fcvt_unfixed32_<mode>"
426 ; [(set (match_operand:F3ANY 0 "register_operand" "=v")
427 ; (mult:F3ANY (unsigned_float:F3ANY (match_operand:SI 1 "register_operand" "0"))
429 ; "const_double_fcvt_power_of_two_reciprocal_sq" "Dt")))]
430 ; "CSKY_ISA_FEATURE(fpv3_<mode>) && !flag_rounding_math"
431 ; "fxtof.u32.f<f3t>\t%0, %1, %v2")
433 ;; Floating point to fixed point conversions.
435 ;(define_insn "*combine_fcvt<mode>_fixed16"
436 ; [(set (match_operand:HI 0 "register_operand" "=v")
437 ; (fix:HI (fix:F3ANY (mult:F3ANY (match_operand:F3ANY 1 "register_operand" "0")
439 ; "const_double_fcvt_power_of_two_hq" "Du")))))]
440 ; "CSKY_ISA_FEATURE(fpv3_<mode>) && !flag_rounding_math
441 ; && CSKY_ISA_FEATURE(fpv3_hi)"
442 ; "fftox.f<f3t>.s16\t%0, %1, %v2"
445 ;(define_insn "*combine_fcvt<mode>_fixed32"
446 ; [(set (match_operand:SI 0 "register_operand" "=v")
447 ; (fix:SI (fix:F3ANY (mult:F3ANY (match_operand:F3ANY 1 "register_operand" "0")
449 ; "const_double_fcvt_power_of_two_sq" "Du")))))]
450 ; "CSKY_ISA_FEATURE(fpv3_<mode>) && !flag_rounding_math"
451 ; "fftox.f<f3t>.s32\t%0, %1, %v2"
454 ;(define_insn "*combine_fcvt<mode>_unfixed16"
455 ; [(set (match_operand:HI 0 "register_operand" "=v")
456 ; (unsigned_fix:HI (fix:F3ANY (mult:F3ANY (match_operand:F3ANY 1 "register_operand" "0")
458 ; "const_double_fcvt_power_of_two_hq" "Du")))))]
459 ; "CSKY_ISA_FEATURE(fpv3_<mode>) && !flag_rounding_math
460 ; && CSKY_ISA_FEATURE(fpv3_hi)"
461 ; "fftox.f<f3t>.u16\t%0, %1, %v2"
464 ;(define_insn "*combine_fcvt<mode>_unfixed32"
465 ; [(set (match_operand:SI 0 "register_operand" "=v")
466 ; (unsigned_fix:SI (fix:F3ANY (mult:F3ANY (match_operand:F3ANY 1 "register_operand" "0")
468 ; "const_double_fcvt_power_of_two_sq" "Du")))))]
469 ; "CSKY_ISA_FEATURE(fpv3_<mode>) && !flag_rounding_math"
470 ; "fftox.f<f3t>.u32\t%0, %1, %v2"
473 ;; conversions need to be rounding to nearest.
475 (define_insn "l<frm_pattern><fixsuop><mode>si2"
476 [(set (match_operand:SI 0 "register_operand" "=v")
477 (FIX_SU:SI (unspec:F3ANY [(match_operand:F3ANY 1 "register_operand" "0")]
479 "CSKY_ISA_FEATURE(fpv3_<mode>)"
480 "fftoi.f<f3t>.<fixsu>32<rm>\t%0, %1"
483 (define_insn "<frm_pattern><mode>2"
484 [(set (match_operand:F3ANY 0 "register_operand" "=v")
485 (unspec:F3ANY [(match_operand:F3ANY 1 "register_operand" "0")] FRMF))]
486 "CSKY_ISA_FEATURE(fpv3_<mode>)"
487 "fftofi.f<f3t><rm>\t%0, %1"
490 ;; Write Floating-point Control Register.
491 (define_insn "csky_setfcrsi"
492 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] VUNSPEC_SET_FCR)]
493 "CSKY_ISA_FEATURE(fcr)"
497 ;; Read Floating-point Control Register.
498 (define_insn "csky_getfcrsi"
499 [(set (match_operand:SI 0 "register_operand" "=r")
500 (unspec_volatile:SI [(const_int 0)] VUNSPEC_GET_FCR))]
501 "CSKY_ISA_FEATURE(fcr)"
505 ;; Insert Floating-point Control Register.
506 (define_insn "csky_insfcrsi"
507 [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")
508 (match_operand:SI 1 "const_int_operand" "i")
509 (match_operand:SI 2 "const_int_operand" "i")]VUNSPEC_INS_FCR)
510 (clobber (reg: SI 13))]
511 "CSKY_ISA_FEATURE(fcr)"
513 operands[1] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[1]) - 1);
514 return "mfcr\tt1, fcr\n\tins\tt1, %0, %1, %2\n\tmtcr\tt1, fcr";