| blob | d21e041eccbc755b73703e144cd71559f86dc241 |
1 /* Machine description for AArch64 architecture.
2 Copyright (C) 2009-2022 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
12 GCC is distributed in the hope that it will be useful, but
13 WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
21 #define IN_TARGET_CODE 1
23 #define INCLUDE_STRING
24 #define INCLUDE_ALGORITHM
85 /* This file should be included last. */
88 /* Defined for convenience. */
89 #define POINTER_BYTES (POINTER_SIZE / BITS_PER_UNIT)
91 /* Information about a legitimate vector immediate operand. */
92 struct simd_immediate_info
93 {
105 /* The mode of the elements. */
106 scalar_mode elt_mode;
108 /* The instruction to use to move the immediate into a vector. */
109 insn_type insn;
111 union
112 {
113 /* For MOV and MVN. */
114 struct
115 {
116 /* The value of each element. */
117 rtx value;
119 /* The kind of shift modifier to use, and the number of bits to shift.
120 This is (LSL, 0) if no shift is needed. */
121 modifier_type modifier;
125 /* For INDEX. */
126 struct
127 {
128 /* The value of the first element and the step to be added for each
129 subsequent element. */
133 /* For PTRUE. */
134 aarch64_svpattern pattern;
136 };
138 /* Construct a floating-point immediate in which each element has mode
139 ELT_MODE_IN and value VALUE_IN. */
140 inline simd_immediate_info
143 {
147 }
149 /* Construct an integer immediate in which each element has mode ELT_MODE_IN
150 and value VALUE_IN. The other parameters are as for the structure
151 fields. */
152 inline simd_immediate_info
158 {
162 }
164 /* Construct an integer immediate in which each element has mode ELT_MODE_IN
165 and where element I is equal to BASE_IN + I * STEP_IN. */
166 inline simd_immediate_info
169 {
172 }
174 /* Construct a predicate that controls elements of mode ELT_MODE_IN
175 and has PTRUE pattern PATTERN_IN. */
176 inline simd_immediate_info
178 aarch64_svpattern pattern_in)
180 {
182 }
186 /* Describes types that map to Pure Scalable Types (PSTs) in the AAPCS64. */
187 class pure_scalable_type_info
188 {
190 /* Represents the result of analyzing a type. All values are nonzero,
191 in the possibly forlorn hope that accidental conversions to bool
192 trigger a warning. */
193 enum analysis_result
194 {
195 /* The type does not have an ABI identity; i.e. it doesn't contain
196 at least one object whose type is a Fundamental Data Type. */
199 /* The type is definitely a Pure Scalable Type. */
200 IS_PST,
202 /* The type is definitely not a Pure Scalable Type. */
203 ISNT_PST,
205 /* It doesn't matter for PCS purposes whether the type is a Pure
206 Scalable Type or not, since the type will be handled the same
207 way regardless.
209 Specifically, this means that if the type is a Pure Scalable Type,
210 there aren't enough argument registers to hold it, and so it will
211 need to be passed or returned in memory. If the type isn't a
212 Pure Scalable Type, it's too big to be passed or returned in core
213 or SIMD&FP registers, and so again will need to go in memory. */
214 DOESNT_MATTER
215 };
217 /* Aggregates of 17 bytes or more are normally passed and returned
218 in memory, so aggregates of that size can safely be analyzed as
219 DOESNT_MATTER. We need to be able to collect enough pieces to
220 represent a PST that is smaller than that. Since predicates are
221 2 bytes in size for -msve-vector-bits=128, that means we need to be
222 able to store at least 8 pieces.
224 We also need to be able to store enough pieces to represent
225 a single vector in each vector argument register and a single
226 predicate in each predicate argument register. This means that
227 we need at least 12 pieces. */
231 /* Describes one piece of a PST. Each piece is one of:
233 - a single Scalable Vector Type (SVT)
234 - a single Scalable Predicate Type (SPT)
235 - a PST containing 2, 3 or 4 SVTs, with no padding
237 It either represents a single built-in type or a PST formed from
238 multiple homogeneous built-in types. */
239 struct piece
240 {
243 /* The number of vector and predicate registers that the piece
244 occupies. One of the two is always zero. */
248 /* The mode of the registers described above. */
249 machine_mode mode;
251 /* If this piece is formed from multiple homogeneous built-in types,
252 this is the mode of the built-in types, otherwise it is MODE. */
253 machine_mode orig_mode;
255 /* The offset in bytes of the piece from the start of the type. */
256 poly_uint64_pod offset;
257 };
259 /* Divides types analyzed as IS_PST into individual pieces. The pieces
260 are in memory order. */
275 };
276 }
278 /* The current code model. */
281 /* The number of 64-bit elements in an SVE vector. */
282 poly_uint16 aarch64_sve_vg;
284 #ifdef HAVE_AS_TLS
285 #undef TARGET_HAVE_TLS
286 #define TARGET_HAVE_TLS 1
287 #endif
292 const_tree,
301 const_tree type,
306 aarch64_addr_query_type);
309 /* The processor for which instructions should be scheduled. */
312 /* Mask to specify which instruction scheduling options should be used. */
315 /* Global flag for PC relative loads. */
318 /* Global flag for whether frame pointer is enabled. */
321 #define BRANCH_PROTECT_STR_MAX 255
324 static enum aarch64_parse_opt_result
327 /* Support for command line parsing of boolean flags in the tuning
328 structures. */
329 struct aarch64_flag_desc
330 {
333 };
335 #define AARCH64_FUSION_PAIR(name, internal_name) \
336 { name, AARCH64_FUSE_##internal_name },
338 {
343 };
345 #define AARCH64_EXTRA_TUNING_OPTION(name, internal_name) \
346 { name, AARCH64_EXTRA_TUNE_##internal_name },
348 {
353 };
355 /* Tuning parameters. */
358 {
359 {
364 },
373 };
376 {
377 {
382 },
391 };
394 {
395 {
400 },
409 };
412 {
413 {
418 },
427 };
430 {
431 {
436 },
445 };
448 {
449 {
454 },
463 };
466 {
467 {
472 },
481 };
484 {
485 {
490 },
499 };
502 {
503 {
508 },
517 };
520 {
521 {
526 },
535 };
538 {
539 {
544 },
553 };
556 {
558 /* Avoid the use of slow int<->fp moves for spilling by setting
559 their cost higher than memmov_cost. */
563 };
566 {
568 /* Avoid the use of slow int<->fp moves for spilling by setting
569 their cost higher than memmov_cost. */
573 };
576 {
578 /* Avoid the use of slow int<->fp moves for spilling by setting
579 their cost higher than memmov_cost. */
583 };
586 {
588 /* Avoid the use of slow int<->fp moves for spilling by setting
589 their cost higher than memmov_cost (actual, 4 and 9). */
593 };
596 {
601 };
604 {
606 /* Avoid the use of slow int<->fp moves for spilling by setting
607 their cost higher than memmov_cost. */
611 };
614 {
616 /* Avoid the use of int<->fp moves for spilling. */
620 };
623 {
625 /* Avoid the use of int<->fp moves for spilling. */
629 };
632 {
634 /* Avoid the use of int<->fp moves for spilling. */
638 };
641 {
643 /* Avoid the use of slow int<->fp moves for spilling by setting
644 their cost higher than memmov_cost. */
648 };
651 {
653 /* Avoid the use of slow int<->fp moves for spilling by setting
654 their cost higher than memmov_cost. */
658 };
661 {
663 /* Spilling to int<->fp instead of memory is recommended so set
664 realistic costs compared to memmov_cost. */
668 };
671 {
673 /* Spilling to int<->fp instead of memory is recommended so set
674 realistic costs compared to memmov_cost. */
678 };
681 {
683 /* Spilling to int<->fp instead of memory is recommended so set
684 realistic costs compared to memmov_cost. */
688 };
690 /* Generic costs for Advanced SIMD vector operations. */
692 {
713 };
715 /* Generic costs for SVE vector operations. */
717 {
718 {
739 },
747 };
749 /* Generic costs for vector insn classes. */
751 {
761 };
764 {
785 };
788 {
789 {
810 },
818 };
821 {
831 };
834 {
855 };
857 /* QDF24XX costs for vector insn classes. */
859 {
869 };
873 {
894 };
896 /* ThunderX costs for vector insn classes. */
898 {
908 };
911 {
932 };
935 {
945 };
948 {
969 };
971 /* Cortex-A57 costs for vector insn classes. */
973 {
983 };
986 {
1007 };
1010 {
1020 };
1023 {
1044 };
1046 /* Generic costs for vector insn classes. */
1048 {
1058 };
1061 {
1082 };
1084 /* Costs for vector insn classes for Vulcan. */
1086 {
1096 };
1099 {
1120 };
1123 {
1133 };
1136 {
1157 };
1159 /* Ampere-1 costs for vector insn classes. */
1161 {
1171 };
1173 /* Generic costs for branch instructions. */
1175 {
1178 };
1180 /* Generic approximation modes. */
1182 {
1185 AARCH64_APPROX_NONE /* recip_sqrt */
1186 };
1188 /* Approximation modes for Exynos M1. */
1190 {
1193 AARCH64_APPROX_ALL /* recip_sqrt */
1194 };
1196 /* Approximation modes for X-Gene 1. */
1198 {
1201 AARCH64_APPROX_ALL /* recip_sqrt */
1202 };
1204 /* Generic prefetch settings (which disable prefetch). */
1206 {
1214 };
1217 {
1225 };
1228 {
1236 };
1239 {
1247 };
1250 {
1258 };
1261 {
1269 };
1272 {
1280 };
1283 {
1291 };
1294 {
1302 };
1305 {
1313 };
1316 {
1324 };
1327 {
1354 /* Enabling AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS significantly benefits
1355 Neoverse V1. It does not have a noticeable effect on A64FX and should
1356 have at most a very minor effect on SVE2 cores. */
1358 &generic_prefetch_tune
1359 };
1362 {
1391 &generic_prefetch_tune
1392 };
1395 {
1424 &generic_prefetch_tune
1425 };
1428 {
1457 &generic_prefetch_tune
1458 };
1461 {
1490 &generic_prefetch_tune
1491 };
1494 {
1523 &generic_prefetch_tune
1524 };
1529 {
1557 &exynosm1_prefetch_tune
1558 };
1561 {
1589 &thunderxt88_prefetch_tune
1590 };
1593 {
1620 (AARCH64_EXTRA_TUNE_SLOW_UNALIGNED_LDPW
1622 &thunderx_prefetch_tune
1623 };
1626 {
1655 &tsv110_prefetch_tune
1656 };
1659 {
1687 &xgene1_prefetch_tune
1688 };
1691 {
1698 SVE_NOT_IMPLEMENTED,
1719 &xgene1_prefetch_tune
1720 };
1723 {
1752 &qdf24xx_prefetch_tune
1753 };
1755 /* Tuning structure for the Qualcomm Saphira core. Default to falkor values
1756 for now. */
1758 {
1787 &generic_prefetch_tune
1788 };
1791 {
1820 &thunderx2t99_prefetch_tune
1821 };
1824 {
1853 &thunderx3t110_prefetch_tune
1854 };
1857 {
1885 &generic_prefetch_tune
1886 };
1889 {
1908 AARCH64_FUSE_CMP_BRANCH),
1909 /* fusible_ops */
1921 &ere1_prefetch_tune
1922 };
1925 {
1940 /* This value is just inherited from the Cortex-A57 table. */
1942 /* This depends very much on what the scalar value is and
1943 where it comes from. E.g. some constants take two dependent
1944 instructions or a load, while others might be moved from a GPR.
1945 4 seems to be a reasonable compromise in practice. */
1949 /* Although stores have a latency of 2 and compete for the
1950 vector pipes, in practice it's better not to model that. */
1953 };
1956 {
1957 {
1964 /* Theoretically, a reduction involving 31 scalar ADDs could
1965 complete in ~9 cycles and would have a cost of 31. [SU]ADDV
1966 completes in 14 cycles, so give it a cost of 31 + 5. */
1968 /* Likewise for 15 scalar ADDs (~5 cycles) vs. 12: 15 + 7. */
1970 /* Likewise for 7 scalar ADDs (~3 cycles) vs. 10: 7 + 7. */
1972 /* Likewise for 3 scalar ADDs (~2 cycles) vs. 10: 3 + 8. */
1974 /* Theoretically, a reduction involving 15 scalar FADDs could
1975 complete in ~9 cycles and would have a cost of 30. FADDV
1976 completes in 13 cycles, so give it a cost of 30 + 4. */
1978 /* Likewise for 7 scalar FADDs (~6 cycles) vs. 11: 14 + 5. */
1980 /* Likewise for 3 scalar FADDs (~4 cycles) vs. 9: 6 + 5. */
1983 /* This value is just inherited from the Cortex-A57 table. */
1985 /* See the comment above the Advanced SIMD versions. */
1989 /* Although stores have a latency of 2 and compete for the
1990 vector pipes, in practice it's better not to model that. */
1993 },
2001 };
2004 {
2010 };
2013 {
2014 {
2020 },
2024 };
2027 {
2028 {
2029 {
2035 },
2039 },
2046 };
2049 {
2052 &neoversev1_sve_issue_info
2053 };
2055 /* Neoverse V1 costs for vector insn classes. */
2057 {
2067 };
2070 {
2097 (AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS
2098 | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS
2099 | AARCH64_EXTRA_TUNE_MATCHED_VECTOR_THROUGHPUT
2101 &generic_prefetch_tune
2102 };
2105 {
2106 {
2113 /* Theoretically, a reduction involving 15 scalar ADDs could
2114 complete in ~5 cycles and would have a cost of 15. Assume that
2115 [SU]ADDV completes in 11 cycles and so give it a cost of 15 + 6. */
2117 /* Likewise for 7 scalar ADDs (~3 cycles) vs. 9: 7 + 6. */
2119 /* Likewise for 3 scalar ADDs (~2 cycles) vs. 8: 3 + 6. */
2121 /* Likewise for 1 scalar ADD (1 cycle) vs. 8: 1 + 7. */
2123 /* Theoretically, a reduction involving 7 scalar FADDs could
2124 complete in ~6 cycles and would have a cost of 14. Assume that
2125 FADDV completes in 8 cycles and so give it a cost of 14 + 2. */
2127 /* Likewise for 3 scalar FADDs (~4 cycles) vs. 6: 6 + 2. */
2129 /* Likewise for 1 scalar FADD (2 cycles) vs. 4: 2 + 2. */
2132 /* This value is just inherited from the Cortex-A57 table. */
2134 /* This depends very much on what the scalar value is and
2135 where it comes from. E.g. some constants take two dependent
2136 instructions or a load, while others might be moved from a GPR.
2137 4 seems to be a reasonable compromise in practice. */
2141 /* Although stores generally have a latency of 2 and compete for the
2142 vector pipes, in practice it's better not to model that. */
2145 },
2150 /* A strided Advanced SIMD x64 load would take two parallel FP loads
2151 (6 cycles) plus an insertion (2 cycles). Assume a 64-bit SVE gather
2152 is 1 cycle more. The Advanced SIMD version is costed as 2 scalar loads
2153 (cost 8) and a vec_construct (cost 2). Add a full vector operation
2154 (cost 2) to that, to avoid the difference being lost in rounding.
2156 There is no easy comparison between a strided Advanced SIMD x32 load
2157 and an SVE 32-bit gather, but cost an SVE 32-bit gather as 1 vector
2158 operation more than a 64-bit gather. */
2162 };
2165 {
2166 {
2167 {
2173 },
2177 },
2184 };
2187 {
2190 &neoverse512tvb_sve_issue_info
2191 };
2194 {
2204 };
2207 {
2234 (AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS
2235 | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS
2237 &generic_prefetch_tune
2238 };
2241 {
2256 /* This value is just inherited from the Cortex-A57 table. */
2258 /* This depends very much on what the scalar value is and
2259 where it comes from. E.g. some constants take two dependent
2260 instructions or a load, while others might be moved from a GPR.
2261 4 seems to be a reasonable compromise in practice. */
2265 /* Although stores have a latency of 2 and compete for the
2266 vector pipes, in practice it's better not to model that. */
2269 };
2272 {
2273 {
2280 /* Theoretically, a reduction involving 15 scalar ADDs could
2281 complete in ~5 cycles and would have a cost of 15. [SU]ADDV
2282 completes in 11 cycles, so give it a cost of 15 + 6. */
2284 /* Likewise for 7 scalar ADDs (~3 cycles) vs. 9: 7 + 6. */
2286 /* Likewise for 3 scalar ADDs (~2 cycles) vs. 8: 3 + 6. */
2288 /* Likewise for 1 scalar ADD (~1 cycles) vs. 2: 1 + 1. */
2290 /* Theoretically, a reduction involving 7 scalar FADDs could
2291 complete in ~8 cycles and would have a cost of 14. FADDV
2292 completes in 6 cycles, so give it a cost of 14 - 2. */
2294 /* Likewise for 3 scalar FADDs (~4 cycles) vs. 4: 6 - 0. */
2296 /* Likewise for 1 scalar FADD (~2 cycles) vs. 2: 2 - 0. */
2299 /* This value is just inherited from the Cortex-A57 table. */
2301 /* See the comment above the Advanced SIMD versions. */
2305 /* Although stores have a latency of 2 and compete for the
2306 vector pipes, in practice it's better not to model that. */
2309 },
2314 /* A strided Advanced SIMD x64 load would take two parallel FP loads
2315 (8 cycles) plus an insertion (2 cycles). Assume a 64-bit SVE gather
2316 is 1 cycle more. The Advanced SIMD version is costed as 2 scalar loads
2317 (cost 8) and a vec_construct (cost 2). Add a full vector operation
2318 (cost 2) to that, to avoid the difference being lost in rounding.
2320 There is no easy comparison between a strided Advanced SIMD x32 load
2321 and an SVE 32-bit gather, but cost an SVE 32-bit gather as 1 vector
2322 operation more than a 64-bit gather. */
2326 };
2329 {
2335 };
2338 {
2339 {
2345 },
2349 };
2352 {
2353 {
2354 {
2360 },
2364 },
2371 };
2374 {
2377 &neoversen2_sve_issue_info
2378 };
2380 /* Neoverse N2 costs for vector insn classes. */
2382 {
2392 };
2395 {
2422 (AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND
2423 | AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS
2424 | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS
2426 &generic_prefetch_tune
2427 };
2430 {
2445 /* This value is just inherited from the Cortex-A57 table. */
2447 /* This depends very much on what the scalar value is and
2448 where it comes from. E.g. some constants take two dependent
2449 instructions or a load, while others might be moved from a GPR.
2450 4 seems to be a reasonable compromise in practice. */
2454 /* Although stores have a latency of 2 and compete for the
2455 vector pipes, in practice it's better not to model that. */
2458 };
2461 {
2462 {
2469 /* Theoretically, a reduction involving 15 scalar ADDs could
2470 complete in ~3 cycles and would have a cost of 15. [SU]ADDV
2471 completes in 11 cycles, so give it a cost of 15 + 8. */
2473 /* Likewise for 7 scalar ADDs (~2 cycles) vs. 9: 7 + 7. */
2475 /* Likewise for 3 scalar ADDs (~2 cycles) vs. 8: 3 + 4. */
2477 /* Likewise for 1 scalar ADD (~1 cycles) vs. 2: 1 + 1. */
2479 /* Theoretically, a reduction involving 7 scalar FADDs could
2480 complete in ~6 cycles and would have a cost of 14. FADDV
2481 completes in 8 cycles, so give it a cost of 14 + 2. */
2483 /* Likewise for 3 scalar FADDs (~4 cycles) vs. 6: 6 + 2. */
2485 /* Likewise for 1 scalar FADD (~2 cycles) vs. 4: 2 + 2. */
2488 /* This value is just inherited from the Cortex-A57 table. */
2490 /* See the comment above the Advanced SIMD versions. */
2494 /* Although stores have a latency of 2 and compete for the
2495 vector pipes, in practice it's better not to model that. */
2498 },
2503 /* A strided Advanced SIMD x64 load would take two parallel FP loads
2504 (8 cycles) plus an insertion (2 cycles). Assume a 64-bit SVE gather
2505 is 1 cycle more. The Advanced SIMD version is costed as 2 scalar loads
2506 (cost 8) and a vec_construct (cost 2). Add a full vector operation
2507 (cost 2) to that, to avoid the difference being lost in rounding.
2509 There is no easy comparison between a strided Advanced SIMD x32 load
2510 and an SVE 32-bit gather, but cost an SVE 32-bit gather as 1 vector
2511 operation more than a 64-bit gather. */
2515 };
2518 {
2524 };
2527 {
2528 {
2534 },
2538 };
2541 {
2542 {
2543 {
2549 },
2553 },
2560 };
2563 {
2566 &demeter_sve_issue_info
2567 };
2569 /* Demeter costs for vector insn classes. */
2571 {
2581 };
2584 {
2611 (AARCH64_EXTRA_TUNE_CHEAP_SHIFT_EXTEND
2612 | AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS
2613 | AARCH64_EXTRA_TUNE_USE_NEW_VECTOR_COSTS
2615 &generic_prefetch_tune
2616 };
2619 {
2647 &a64fx_prefetch_tune
2648 };
2650 /* Support for fine-grained override of the tuning structures. */
2651 struct aarch64_tuning_override_function
2652 {
2655 };
2661 static const struct aarch64_tuning_override_function
2662 aarch64_tuning_override_functions[] =
2663 {
2668 };
2670 /* A processor implementing AArch64. */
2671 struct processor
2672 {
2679 };
2681 /* Architectures implementing AArch64. */
2683 {
2684 #define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
2685 {NAME, CORE, CORE, AARCH64_ARCH_##ARCH_IDENT, FLAGS, NULL},
2688 };
2690 /* Processor cores implementing AArch64. */
2692 {
2693 #define AARCH64_CORE(NAME, IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART, VARIANT) \
2694 {NAME, IDENT, SCHED, AARCH64_ARCH_##ARCH, \
2695 FLAGS, &COSTS##_tunings},
2700 };
2702 /* The current tuning set. */
2705 /* Check whether an 'aarch64_vector_pcs' attribute is valid. */
2707 static tree
2710 {
2711 /* Since we set fn_type_req to true, the caller should have checked
2712 this for us. */
2715 {
2722 name);
2729 }
2731 }
2733 /* Table of machine attributes. */
2735 {
2736 /* { name, min_len, max_len, decl_req, type_req, fn_type_req,
2737 affects_type_identity, handler, exclude } */
2742 NULL },
2747 };
2749 /* An ISA extension in the co-processor and main instruction set space. */
2750 struct aarch64_option_extension
2751 {
2755 };
2758 {
2762 }
2763 aarch64_cc;
2765 #define AARCH64_INVERSE_CONDITION_CODE(X) ((aarch64_cc) (((int) X) ^ 1))
2767 struct aarch64_branch_protect_type
2768 {
2769 /* The type's name that the user passes to the branch-protection option
2770 string. */
2772 /* Function to handle the protection type and set global variables.
2773 First argument is the string token corresponding with this type and the
2774 second argument is the next token in the option string.
2775 Return values:
2776 * AARCH64_PARSE_OK: Handling was sucessful.
2777 * AARCH64_INVALID_ARG: The type is invalid in this context and the caller
2778 should print an error.
2779 * AARCH64_INVALID_FEATURE: The type is invalid and the handler prints its
2780 own error. */
2782 /* A list of types that can follow this type in the option string. */
2785 };
2787 static enum aarch64_parse_opt_result
2789 {
2793 {
2796 }
2798 }
2800 static enum aarch64_parse_opt_result
2802 {
2807 {
2810 }
2812 }
2814 static enum aarch64_parse_opt_result
2817 {
2821 }
2823 static enum aarch64_parse_opt_result
2826 {
2829 }
2831 static enum aarch64_parse_opt_result
2834 {
2837 }
2839 static enum aarch64_parse_opt_result
2842 {
2845 }
2851 };
2860 };
2862 /* The condition codes of the processor, and the inverse function. */
2864 {
2867 };
2869 /* The preferred condition codes for SVE conditions. */
2871 {
2874 };
2876 /* Return the assembly token for svpattern value VALUE. */
2880 {
2882 {
2883 #define CASE(UPPER, LOWER, VALUE) case AARCH64_SV_##UPPER: return #LOWER;
2885 #undef CASE
2888 }
2890 }
2892 /* Return the location of a piece that is known to be passed or returned
2893 in registers. FIRST_ZR is the first unused vector argument register
2894 and FIRST_PR is the first unused predicate argument register. */
2896 rtx
2899 {
2911 }
2913 /* Return the total number of vector registers required by the PST. */
2915 unsigned int
2917 {
2922 }
2924 /* Return the total number of predicate registers required by the PST. */
2926 unsigned int
2928 {
2933 }
2935 /* Return the location of a PST that is known to be passed or returned
2936 in registers. FIRST_ZR is the first unused vector argument register
2937 and FIRST_PR is the first unused predicate argument register. */
2939 rtx
2943 {
2944 /* Try to return a single REG if possible. This leads to better
2945 code generation; it isn't required for correctness. */
2947 {
2950 }
2952 /* Build up a PARALLEL that contains the individual pieces. */
2955 {
2961 }
2963 }
2965 /* Analyze whether TYPE is a Pure Scalable Type according to the rules
2966 in the AAPCS64. */
2970 {
2971 /* Prevent accidental reuse. */
2974 /* No code will be generated for erroneous types, so we won't establish
2975 an ABI mapping. */
2979 /* Zero-sized types disappear in the language->ABI mapping. */
2983 /* Check for SVTs, SPTs, and built-in tuple types that map to PSTs. */
2984 piece p = {};
2986 {
2994 }
2996 /* Check for user-defined PSTs. */
3003 }
3005 /* Analyze a type that is known not to be passed or returned in memory.
3006 Return true if it has an ABI identity and is a Pure Scalable Type. */
3008 bool
3010 {
3014 }
3016 /* Subroutine of analyze for handling ARRAY_TYPEs. */
3020 {
3021 /* Analyze the element type. */
3022 pure_scalable_type_info element_info;
3027 /* An array of unknown, flexible or variable length will be passed and
3028 returned by reference whatever we do. */
3033 /* Likewise if the array is constant-sized but too big to be interesting.
3034 The double checks against MAX_PIECES are to protect against overflow. */
3042 /* The above checks should have weeded out elements of unknown size. */
3043 poly_uint64 element_bytes;
3047 /* Build up the list of individual vectors and predicates. */
3051 {
3055 }
3057 }
3059 /* Subroutine of analyze for handling RECORD_TYPEs. */
3063 {
3065 {
3069 /* Zero-sized fields disappear in the language->ABI mapping. */
3073 /* All fields with an ABI identity must be PSTs for the record as
3074 a whole to be a PST. If any individual field is too big to be
3075 interesting then the record is too. */
3076 pure_scalable_type_info field_info;
3083 /* Since all previous fields are PSTs, we ought to be able to track
3084 the field offset using poly_ints. */
3088 /* For the same reason, it shouldn't be possible to create a PST field
3089 whose offset isn't byte-aligned. */
3091 BITS_PER_UNIT);
3093 /* Punt if the record is too big to be interesting. */
3094 poly_uint64 bytepos;
3099 /* Add the individual vectors and predicates in the field to the
3100 record's list. */
3103 {
3107 }
3108 }
3109 /* Empty structures disappear in the language->ABI mapping. */
3111 }
3113 /* Add P to the list of pieces in the type. */
3115 void
3117 {
3118 /* Try to fold the new piece into the previous one to form a
3119 single-mode PST. For example, if we see three consecutive vectors
3120 of the same mode, we can represent them using the corresponding
3121 3-tuple mode.
3123 This is purely an optimization. */
3125 {
3137 {
3141 }
3142 }
3144 }
3146 /* Return true if at least one possible value of type TYPE includes at
3147 least one object of Pure Scalable Type, in the sense of the AAPCS64.
3149 This is a relatively expensive test for some types, so it should
3150 generally be made as late as possible. */
3152 static bool
3154 {
3171 }
3173 /* Return the descriptor of the SIMD ABI. */
3177 {
3180 {
3181 HARD_REG_SET full_reg_clobbers
3187 }
3189 }
3191 /* Return the descriptor of the SVE PCS. */
3195 {
3198 {
3199 HARD_REG_SET full_reg_clobbers
3206 }
3208 }
3210 /* If X is an UNSPEC_SALT_ADDR expression, return the address that it
3211 wraps, otherwise return X itself. */
3213 static rtx
3215 {
3222 }
3224 /* Like strip_offset, but also strip any UNSPEC_SALT_ADDR from the
3225 expression. */
3227 static rtx
3229 {
3231 }
3233 /* Generate code to enable conditional branches in functions over 1 MiB. */
3237 {
3254 }
3256 void
3258 {
3263 else
3266 else
3270 else
3273 }
3275 /* Report when we try to do something that requires SVE when SVE is disabled.
3276 This is an error of last resort and isn't very high-quality. It usually
3277 involves attempts to measure the vector length in some way. */
3278 static void
3280 {
3283 /* Avoid reporting a slew of messages for a single oversight. */
3289 " option %<-march%>, or by using the %<target%>"
3292 }
3294 /* Return true if REGNO is P0-P15 or one of the special FFR-related
3295 registers. */
3298 {
3300 }
3302 /* Implement TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS.
3303 The register allocator chooses POINTER_AND_FP_REGS if FP_REGS and
3304 GENERAL_REGS have the same cost - even if POINTER_AND_FP_REGS has a much
3305 higher cost. POINTER_AND_FP_REGS is also used if the cost of both FP_REGS
3306 and GENERAL_REGS is lower than the memory cost (in this case the best class
3307 is the lowest cost one). Using POINTER_AND_FP_REGS irrespectively of its
3308 cost results in bad allocations with many redundant int<->FP moves which
3309 are expensive on various cores.
3310 To avoid this we don't allow POINTER_AND_FP_REGS as the allocno class, but
3311 force a decision between FP_REGS and GENERAL_REGS. We use the allocno class
3312 if it isn't POINTER_AND_FP_REGS. Similarly, use the best class if it isn't
3313 POINTER_AND_FP_REGS. Otherwise set the allocno class depending on the mode.
3314 The result of this is that it is no longer inefficient to have a higher
3315 memory move cost than the register move cost.
3316 */
3318 static reg_class_t
3320 reg_class_t best_class)
3321 {
3322 machine_mode mode;
3334 }
3336 static unsigned int
3338 {
3342 }
3344 /* Return the reassociation width of treeop OPC with mode MODE. */
3345 static int
3347 {
3352 /* Avoid reassociating floating point addition so we emit more FMAs. */
3356 }
3358 /* Provide a mapping from gcc register numbers to dwarf register numbers. */
3359 unsigned
3361 {
3373 /* Return values >= DWARF_FRAME_REGISTERS indicate that there is no
3374 equivalent DWARF register. */
3376 }
3378 /* If X is a CONST_DOUBLE, return its bit representation as a constant
3379 integer, otherwise return X unmodified. */
3380 static rtx
3382 {
3386 }
3388 /* Return an estimate for the number of quadwords in an SVE vector. This is
3389 equivalent to the number of Advanced SIMD vectors in an SVE vector. */
3390 static unsigned int
3392 {
3394 }
3396 /* Return true if MODE is an SVE predicate mode. */
3397 static bool
3399 {
3405 }
3407 /* Three mutually-exclusive flags describing a vector or predicate type. */
3411 /* Can be used in combination with VEC_ADVSIMD or VEC_SVE_DATA to indicate
3412 a structure of 2, 3 or 4 vectors. */
3414 /* Can be used in combination with VEC_SVE_DATA to indicate that the
3415 vector has fewer significant bytes than a full SVE vector. */
3417 /* Useful combinations of the above. */
3421 /* Return a set of flags describing the vector properties of mode MODE.
3422 Ignore modes that are not supported by the current target. */
3423 static unsigned int
3425 {
3429 /* Make the decision based on the mode's enum value rather than its
3430 properties, so that we keep the correct classification regardless
3431 of -msve-vector-bits. */
3433 {
3434 /* Partial SVE QI vectors. */
3438 /* Partial SVE HI vectors. */
3441 /* Partial SVE SI vector. */
3443 /* Partial SVE HF vectors. */
3446 /* Partial SVE BF vectors. */
3449 /* Partial SVE SF vector. */
3463 /* x2 SVE vectors. */
3472 /* x3 SVE vectors. */
3481 /* x4 SVE vectors. */
3497 /* Structures of 64-bit Advanced SIMD vectors. */
3524 /* Structures of 128-bit Advanced SIMD vectors. */
3551 /* 64-bit Advanced SIMD vectors. */
3555 /* ...E_V1DImode doesn't exist. */
3560 /* 128-bit Advanced SIMD vectors. */
3573 }
3574 }
3576 /* Return true if MODE is any of the Advanced SIMD structure modes. */
3577 bool
3579 {
3582 }
3584 /* Return true if MODE is an Advanced SIMD D-register structure mode. */
3585 static bool
3587 {
3590 }
3592 /* Return true if MODE is an Advanced SIMD Q-register structure mode. */
3593 static bool
3595 {
3597 }
3599 /* Return true if MODE is any of the data vector modes, including
3600 structure modes. */
3601 static bool
3603 {
3605 }
3607 /* Return true if MODE is any form of SVE mode, including predicates,
3608 vectors and structures. */
3609 bool
3611 {
3613 }
3615 /* Return true if MODE is an SVE data vector mode; either a single vector
3616 or a structure of vectors. */
3617 static bool
3619 {
3621 }
3623 /* Return the number of defined bytes in one constituent vector of
3624 SVE mode MODE, which has vector flags VEC_FLAGS. */
3625 static poly_int64
3627 {
3629 /* A single partial vector. */
3633 /* A single vector or a tuple. */
3636 /* A single predicate. */
3639 }
3641 /* If MODE holds an array of vectors, return the number of vectors
3642 in the array, otherwise return 1. */
3644 static unsigned int
3646 {
3656 }
3658 /* Given an Advanced SIMD vector mode MODE and a tuple size NELEMS, return the
3659 corresponding vector structure mode. */
3660 static opt_machine_mode
3663 {
3668 machine_mode struct_mode;
3676 }
3678 /* Return the SVE vector mode that has NUNITS elements of mode INNER_MODE. */
3680 opt_machine_mode
3682 {
3685 machine_mode mode;
3692 }
3694 /* Implement target hook TARGET_ARRAY_MODE. */
3695 static opt_machine_mode
3697 {
3707 }
3709 /* Implement target hook TARGET_ARRAY_MODE_SUPPORTED_P. */
3710 static bool
3713 {
3721 }
3723 /* MODE is some form of SVE vector mode. For data modes, return the number
3724 of vector register bits that each element of MODE occupies, such as 64
3725 for both VNx2DImode and VNx2SImode (where each 32-bit value is stored
3726 in a 64-bit container). For predicate modes, return the number of
3727 data bits controlled by each significant predicate bit. */
3729 static unsigned int
3731 {
3734 ? BITS_PER_SVE_VECTOR
3737 }
3739 /* Return the SVE predicate mode to use for elements that have
3740 ELEM_NBYTES bytes, if such a mode exists. */
3742 opt_machine_mode
3744 {
3746 {
3755 }
3757 }
3759 /* Return the SVE predicate mode that should be used to control
3760 SVE mode MODE. */
3762 machine_mode
3764 {
3767 }
3769 /* Implement TARGET_VECTORIZE_GET_MASK_MODE. */
3771 static opt_machine_mode
3773 {
3779 }
3781 /* Return the integer element mode associated with SVE mode MODE. */
3783 static scalar_int_mode
3785 {
3787 ? BITS_PER_SVE_VECTOR
3792 }
3794 /* Return an integer element mode that contains exactly
3795 aarch64_sve_container_bits (MODE) bits. This is wider than
3796 aarch64_sve_element_int_mode if MODE is a partial vector,
3797 otherwise it's the same. */
3799 static scalar_int_mode
3801 {
3803 }
3805 /* Return the integer vector mode associated with SVE mode MODE.
3806 Unlike related_int_vector_mode, this can handle the case in which
3807 MODE is a predicate (and thus has a different total size). */
3809 machine_mode
3811 {
3814 }
3816 /* Implement TARGET_VECTORIZE_RELATED_MODE. */
3818 static opt_machine_mode
3820 scalar_mode element_mode,
3821 poly_uint64 nunits)
3822 {
3825 /* If we're operating on SVE vectors, try to return an SVE mode. */
3826 poly_uint64 sve_nunits;
3830 {
3831 machine_mode sve_mode;
3833 {
3834 /* Try to find a full or partial SVE mode with exactly
3835 NUNITS units. */
3840 }
3841 else
3842 {
3843 /* Take the preferred number of units from the number of bytes
3844 that fit in VECTOR_MODE. We always start by "autodetecting"
3845 a full vector mode with preferred_simd_mode, so vectors
3846 chosen here will also be full vector modes. Then
3847 autovectorize_vector_modes tries smaller starting modes
3848 and thus smaller preferred numbers of units. */
3853 }
3854 }
3856 /* Prefer to use 1 128-bit vector instead of 2 64-bit vectors. */
3862 {
3866 }
3869 }
3871 /* Implement TARGET_PREFERRED_ELSE_VALUE. For binary operations,
3872 prefer to use the first arithmetic operand as the else value if
3873 the else value doesn't matter, since that exactly matches the SVE
3874 destructive merging form. For ternary operations we could either
3875 pick the first operand and use FMAD-like instructions or the last
3876 operand and use FMLA-like instructions; the latter seems more
3877 natural. */
3879 static tree
3881 {
3883 }
3885 /* Implement TARGET_HARD_REGNO_NREGS. */
3887 static unsigned int
3889 {
3890 /* ??? Logically we should only need to provide a value when
3891 HARD_REGNO_MODE_OK says that the combination is valid,
3892 but at the moment we need to handle all modes. Just ignore
3893 any runtime parts for registers that can't store them. */
3896 {
3900 {
3908 }
3917 }
3919 }
3921 /* Implement TARGET_HARD_REGNO_MODE_OK. */
3923 static bool
3925 {
3934 /* This must have the same size as _Unwind_Word. */
3945 /* The purpose of comparing with ptr_mode is to support the
3946 global register variable associated with the stack pointer
3947 register via the syntax of asm ("wsp") in ILP32. */
3954 {
3961 }
3963 {
3966 else
3968 }
3971 }
3973 /* Return true if a function with type FNTYPE returns its value in
3974 SVE vector or predicate registers. */
3976 static bool
3978 {
3981 pure_scalable_type_info pst_info;
3983 {
3995 }
3997 }
3999 /* Return true if a function with type FNTYPE takes arguments in
4000 SVE vector or predicate registers. */
4002 static bool
4004 {
4005 CUMULATIVE_ARGS args_so_far_v;
4013 {
4020 pure_scalable_type_info pst_info;
4022 {
4027 }
4030 }
4032 }
4034 /* Implement TARGET_FNTYPE_ABI. */
4038 {
4047 }
4049 /* Implement TARGET_COMPATIBLE_VECTOR_TYPES_P. */
4051 static bool
4053 {
4056 }
4058 /* Return true if we should emit CFI for register REGNO. */
4060 static bool
4062 {
4065 }
4067 /* Return the mode we should use to save and restore register REGNO. */
4069 static machine_mode
4071 {
4077 {
4079 /* Only the low 64 bits are saved by the base PCS. */
4083 /* The vector PCS saves the low 128 bits (which is the full
4084 register on non-SVE targets). */
4088 /* Use vectors of DImode for registers that need frame
4089 information, so that the first 64 bytes of the save slot
4090 are always the equivalent of what storing D<n> would give. */
4094 /* Use vectors of bytes otherwise, so that the layout is
4095 endian-agnostic, and so that we can use LDR and STR for
4096 big-endian targets. */
4102 }
4105 /* Save the full predicate register. */
4109 }
4111 /* Implement TARGET_INSN_CALLEE_ABI. */
4115 {
4122 }
4124 /* Implement TARGET_HARD_REGNO_CALL_PART_CLOBBERED. The callee only saves
4125 the lower 64 bits of a 128-bit register. Tell the compiler the callee
4126 clobbers the top 64 bits when restoring the bottom 64 bits. */
4128 static bool
4131 machine_mode mode)
4132 {
4134 {
4142 }
4144 }
4146 /* Implement REGMODE_NATURAL_SIZE. */
4147 poly_uint64
4149 {
4150 /* The natural size for SVE data modes is one SVE data vector,
4151 and similarly for predicates. We can't independently modify
4152 anything smaller than that. */
4153 /* ??? For now, only do this for variable-width SVE registers.
4154 Doing it for constant-sized registers breaks lower-subreg.cc. */
4155 /* ??? And once that's fixed, we should probably have similar
4156 code for Advanced SIMD. */
4158 {
4164 }
4166 }
4168 /* Implement HARD_REGNO_CALLER_SAVE_MODE. */
4169 machine_mode
4171 machine_mode mode)
4172 {
4173 /* The predicate mode determines which bits are significant and
4174 which are "don't care". Decreasing the number of lanes would
4175 lose data while increasing the number of lanes would make bits
4176 unnecessarily significant. */
4181 else
4183 }
4185 /* Return true if I's bits are consecutive ones from the MSB. */
4186 bool
4188 {
4190 }
4192 /* Implement TARGET_CONSTANT_ALIGNMENT. Make strings word-aligned so
4193 that strcpy from constants will be faster. */
4195 static HOST_WIDE_INT
4197 {
4201 }
4203 /* Return true if calls to DECL should be treated as
4204 long-calls (ie called via a register). */
4205 static bool
4207 {
4209 }
4211 /* Return true if calls to symbol-ref SYM should be treated as
4212 long-calls (ie called via a register). */
4213 bool
4215 {
4217 }
4219 /* Return true if calls to symbol-ref SYM should not go through
4220 plt stubs. */
4222 bool
4224 {
4228 && decl
4229 && (!flag_plt
4235 }
4237 /* Emit an insn that's a simple single-set. Both the operands must be
4238 known to be valid. */
4241 {
4243 }
4245 /* X and Y are two things to compare using CODE. Emit the compare insn and
4246 return the rtx for register 0 in the proper mode. */
4247 rtx
4249 {
4251 machine_mode cc_mode;
4252 rtx cc_reg;
4255 {
4270 }
4271 else
4272 {
4276 }
4278 }
4280 /* Similarly, but maybe zero-extend Y if Y_MODE < SImode. */
4282 static rtx
4284 machine_mode y_mode)
4285 {
4287 {
4289 {
4292 }
4293 else
4294 {
4296 machine_mode cc_mode;
4304 }
4305 }
4311 }
4313 /* Consider the operation:
4315 OPERANDS[0] = CODE (OPERANDS[1], OPERANDS[2]) + OPERANDS[3]
4317 where:
4319 - CODE is [SU]MAX or [SU]MIN
4320 - OPERANDS[2] and OPERANDS[3] are constant integers
4321 - OPERANDS[3] is a positive or negative shifted 12-bit immediate
4322 - all operands have mode MODE
4324 Decide whether it is possible to implement the operation using:
4326 SUBS <tmp>, OPERANDS[1], -OPERANDS[3]
4327 or
4328 ADDS <tmp>, OPERANDS[1], OPERANDS[3]
4330 followed by:
4332 <insn> OPERANDS[0], <tmp>, [wx]zr, <cond>
4334 where <insn> is one of CSEL, CSINV or CSINC. Return true if so.
4335 If GENERATE_P is true, also update OPERANDS as follows:
4337 OPERANDS[4] = -OPERANDS[3]
4338 OPERANDS[5] = the rtl condition representing <cond>
4339 OPERANDS[6] = <tmp>
4340 OPERANDS[7] = 0 for CSEL, -1 for CSINV or 1 for CSINC. */
4341 bool
4343 {
4350 /* max (x, y) - z == (x >= y + 1 ? x : y) - z
4351 == (x >= y ? x : y) - z
4352 == (x > y ? x : y) - z
4353 == (x > y - 1 ? x : y) - z
4355 min (x, y) - z == (x <= y - 1 ? x : y) - z
4356 == (x <= y ? x : y) - z
4357 == (x < y ? x : y) - z
4358 == (x < y + 1 ? x : y) - z
4360 Check whether z is in { y - 1, y, y + 1 } and pick the form(s) for
4361 which x is compared with z. Set DIFF to y - z. Thus the supported
4362 combinations are as follows, with DIFF being the value after the ":":
4364 max (x, y) - z == x >= y + 1 ? x - (y + 1) : -1 [z == y + 1]
4365 == x >= y ? x - y : 0 [z == y]
4366 == x > y ? x - y : 0 [z == y]
4367 == x > y - 1 ? x - (y - 1) : 1 [z == y - 1]
4369 min (x, y) - z == x <= y - 1 ? x - (y - 1) : 1 [z == y - 1]
4370 == x <= y ? x - y : 0 [z == y]
4371 == x < y ? x - y : 0 [z == y]
4372 == x < y + 1 ? x - (y + 1) : -1 [z == y + 1]. */
4385 rtx_code cmp;
4387 {
4402 }
4409 else
4414 }
4417 /* Build the SYMBOL_REF for __tls_get_addr. */
4421 rtx
4423 {
4427 }
4429 /* Return the TLS model to use for ADDR. */
4431 static enum tls_model
4433 {
4435 poly_int64 offset;
4441 }
4443 /* We'll allow lo_sum's in addresses in our legitimate addresses
4444 so that combine would take care of combining addresses where
4445 necessary, but for generation purposes, we'll generate the address
4446 as :
4447 RTL Absolute
4448 tmp = hi (symbol_ref); adrp x1, foo
4449 dest = lo_sum (tmp, symbol_ref); add dest, x1, :lo_12:foo
4450 nop
4452 PIC TLS
4453 adrp x1, :got:foo adrp tmp, :tlsgd:foo
4454 ldr x1, [:got_lo12:foo] add dest, tmp, :tlsgd_lo12:foo
4455 bl __tls_get_addr
4456 nop
4458 Load TLS symbol, depending on TLS mechanism and TLS access model.
4460 Global Dynamic - Traditional TLS:
4461 adrp tmp, :tlsgd:imm
4462 add dest, tmp, #:tlsgd_lo12:imm
4463 bl __tls_get_addr
4465 Global Dynamic - TLS Descriptors:
4466 adrp dest, :tlsdesc:imm
4467 ldr tmp, [dest, #:tlsdesc_lo12:imm]
4468 add dest, dest, #:tlsdesc_lo12:imm
4469 blr tmp
4470 mrs tp, tpidr_el0
4471 add dest, dest, tp
4473 Initial Exec:
4474 mrs tp, tpidr_el0
4475 adrp tmp, :gottprel:imm
4476 ldr dest, [tmp, #:gottprel_lo12:imm]
4477 add dest, dest, tp
4479 Local Exec:
4480 mrs tp, tpidr_el0
4481 add t0, tp, #:tprel_hi12:imm, lsl #12
4482 add t0, t0, #:tprel_lo12_nc:imm
4483 */
4485 static void
4488 {
4490 {
4492 {
4493 /* In ILP32, the mode of dest can be either SImode or DImode. */
4505 }
4512 {
4515 rtx insn;
4516 rtx mem;
4518 /* NOTE: pic_offset_table_rtx can be NULL_RTX, because we can reach
4519 here before rtl expand. Tree IVOPT will generate rtl pattern to
4520 decide rtx costs, in which case pic_offset_table_rtx is not
4521 initialized. For that case no need to generate the first adrp
4522 instruction as the final cost for global variable access is
4523 one instruction. */
4525 {
4526 /* -fpic for -mcmodel=small allow 32K GOT table size (but we are
4527 using the page base as GOT base, the first page may be wasted,
4528 in the worst scenario, there is only 28K space for GOT).
4530 The generate instruction sequence for accessing global variable
4531 is:
4533 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym]
4535 Only one instruction needed. But we must initialize
4536 pic_offset_table_rtx properly. We generate initialize insn for
4537 every global access, and allow CSE to remove all redundant.
4539 The final instruction sequences will look like the following
4540 for multiply global variables access.
4542 adrp pic_offset_table_rtx, _GLOBAL_OFFSET_TABLE_
4544 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym1]
4545 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym2]
4546 ldr reg, [pic_offset_table_rtx, #:gotpage_lo15:sym3]
4547 ... */
4556 }
4559 {
4562 else
4566 }
4567 else
4568 {
4573 }
4575 /* The operand is expected to be MEM. Whenever the related insn
4576 pattern changed, above code which calculate mem should be
4577 updated. */
4583 }
4590 {
4592 /* The return type of __tls_get_addr is the C pointer type
4593 so use ptr_mode. */
4603 else
4610 /* Convert back to the mode of the dest adding a zero_extend
4611 from SImode (ptr_mode) to DImode (Pmode). */
4615 }
4618 {
4621 rtx tp;
4625 /* In ILP32, the got entry is always of SImode size. Unlike
4626 small GOT, the dest is fixed at reg 0. */
4629 else
4640 }
4643 {
4644 /* In ILP32, the mode of dest can be either SImode or DImode,
4645 while the got entry is always of SImode size. The mode of
4646 dest depends on how dest is used: if dest is assigned to a
4647 pointer (e.g. in the memory), it has SImode; it may have
4648 DImode if dest is dereferenced to access the memeory.
4649 This is why we have to handle three different tlsie_small
4650 patterns here (two patterns for ILP32). */
4656 {
4659 else
4660 {
4663 }
4664 }
4665 else
4666 {
4669 }
4675 }
4681 {
4689 {
4712 }
4717 }
4720 {
4721 rtx insn;
4726 else
4727 {
4730 }
4734 }
4737 {
4742 {
4745 else
4746 {
4749 }
4750 }
4751 else
4752 {
4755 }
4760 }
4764 }
4765 }
4767 /* Emit a move from SRC to DEST. Assume that the move expanders can
4768 handle all moves if !can_create_pseudo_p (). The distinction is
4769 important because, unlike emit_move_insn, the move expanders know
4770 how to force Pmode objects into the constant pool even when the
4771 constant pool address is not itself legitimate. */
4772 static rtx
4774 {
4778 }
4780 /* Apply UNOPTAB to OP and store the result in DEST. */
4782 static void
4784 {
4788 }
4790 /* Apply BINOPTAB to OP0 and OP1 and store the result in DEST. */
4792 static void
4794 {
4796 OPTAB_DIRECT);
4799 }
4801 /* Split a 128-bit move operation into two 64-bit move operations,
4802 taking care to handle partial overlap of register to register
4803 copies. Special cases are needed when moving between GP regs and
4804 FP regs. SRC can be a register, constant or memory; DST a register
4805 or memory. If either operand is memory it must not have any side
4806 effects. */
4807 void
4809 {
4820 {
4824 /* Handle FP <-> GP regs. */
4826 {
4833 }
4835 {
4842 }
4843 }
4850 /* At most one pairing may overlap. */
4852 {
4855 }
4856 else
4857 {
4860 }
4861 }
4863 /* Return true if we should split a move from 128-bit value SRC
4864 to 128-bit register DEST. */
4866 bool
4868 {
4871 /* All moves to GPRs need to be split. */
4873 }
4875 /* Split a complex SIMD move. */
4877 void
4879 {
4886 {
4889 }
4890 }
4892 bool
4895 {
4899 }
4901 /* Return TARGET if it is nonnull and a register of mode MODE.
4902 Otherwise, return a fresh register of mode MODE if we can,
4903 or TARGET reinterpreted as MODE if we can't. */
4905 static rtx
4907 {
4911 {
4914 }
4916 }
4918 /* Return a register that contains the constant in BUILDER, given that
4919 the constant is a legitimate move operand. Use TARGET as the register
4920 if it is nonnull and convenient. */
4922 static rtx
4924 {
4929 }
4931 static rtx
4933 {
4936 else
4937 {
4941 }
4942 }
4944 /* Return true if predicate value X is a constant in which every element
4945 is a CONST_INT. When returning true, describe X in BUILDER as a VNx16BI
4946 value, i.e. as a predicate in which all bits are significant. */
4948 static bool
4950 {
4962 {
4970 }
4973 }
4975 /* BUILDER contains a predicate constant of mode VNx16BI. Return the
4976 widest predicate element size it can have (that is, the largest size
4977 for which each element would still be 0 or 1). */
4979 unsigned int
4981 {
4982 /* Start with the most optimistic assumption: that we only need
4983 one bit per pattern. This is what we will use if only the first
4984 bit in each pattern is ever set. */
4988 /* Look for set bits. */
4992 {
4996 }
4998 }
5000 /* If VNx16BImode rtx X is a canonical PTRUE for a predicate mode,
5001 return that predicate mode, otherwise return opt_machine_mode (). */
5003 opt_machine_mode
5005 {
5019 }
5021 /* BUILDER is a predicate constant of mode VNx16BI. Consider the value
5022 that the constant would have with predicate element size ELT_SIZE
5023 (ignoring the upper bits in each element) and return:
5025 * -1 if all bits are set
5026 * N if the predicate has N leading set bits followed by all clear bits
5027 * 0 if the predicate does not have any of these forms. */
5029 int
5032 {
5033 /* If nelts_per_pattern is 3, we have set bits followed by clear bits
5034 followed by set bits. */
5038 /* Skip over leading set bits. */
5046 /* Check for the all-true case. */
5050 /* If nelts_per_pattern is 1, then either VL is zero, or we have a
5051 repeating pattern of set bits followed by clear bits. */
5055 /* We have a "foreground" value and a duplicated "background" value.
5056 If the background might repeat and the last set bit belongs to it,
5057 we might have set bits followed by clear bits followed by set bits. */
5061 /* Make sure that the rest are all clear. */
5067 }
5069 /* See if there is an svpattern that encodes an SVE predicate of mode
5070 PRED_MODE in which the first VL bits are set and the rest are clear.
5071 Return the pattern if so, otherwise return AARCH64_NUM_SVPATTERNS.
5072 A VL of -1 indicates an all-true vector. */
5074 aarch64_svpattern
5076 {
5091 {
5094 /* These would only trigger for non-power-of-2 lengths. */
5101 }
5103 }
5105 /* Return a VNx16BImode constant in which every sequence of ELT_SIZE
5106 bits has the lowest bit set and the upper bits clear. This is the
5107 VNx16BImode equivalent of a PTRUE for controlling elements of
5108 ELT_SIZE bytes. However, because the constant is VNx16BImode,
5109 all bits are significant, even the upper zeros. */
5111 rtx
5113 {
5119 }
5121 /* Return an all-true predicate register of mode MODE. */
5123 rtx
5125 {
5129 }
5131 /* Return an all-false predicate register of mode MODE. */
5133 rtx
5135 {
5139 }
5141 /* PRED1[0] is a PTEST predicate and PRED1[1] is an aarch64_sve_ptrue_flag
5142 for it. PRED2[0] is the predicate for the instruction whose result
5143 is tested by the PTEST and PRED2[1] is again an aarch64_sve_ptrue_flag
5144 for it. Return true if we can prove that the two predicates are
5145 equivalent for PTEST purposes; that is, if we can replace PRED2[0]
5146 with PRED1[0] without changing behavior. */
5148 bool
5150 {
5162 }
5164 /* Emit a comparison CMP between OP0 and OP1, both of which have mode
5165 DATA_MODE, and return the result in a predicate of mode PRED_MODE.
5166 Use TARGET as the target register if nonnull and convenient. */
5168 static rtx
5171 {
5181 }
5183 /* Use a comparison to convert integer vector SRC into MODE, which is
5184 the corresponding SVE predicate mode. Use TARGET for the result
5185 if it's nonnull and convenient. */
5187 rtx
5189 {
5193 }
5195 /* Return the assembly token for svprfop value PRFOP. */
5199 {
5201 {
5202 #define CASE(UPPER, LOWER, VALUE) case AARCH64_SV_##UPPER: return #LOWER;
5204 #undef CASE
5207 }
5209 }
5211 /* Return the assembly string for an SVE prefetch operation with
5212 mnemonic MNEMONIC, given that PRFOP_RTX is the prefetch operation
5213 and that SUFFIX is the format for the remaining operands. */
5218 {
5225 }
5227 /* Check whether we can calculate the number of elements in PATTERN
5228 at compile time, given that there are NELTS_PER_VQ elements per
5229 128-bit block. Return the value if so, otherwise return -1. */
5231 HOST_WIDE_INT
5233 {
5240 {
5241 /* There are two vector granules per quadword. */
5244 {
5250 }
5251 }
5252 else
5255 /* There are two vector granules per quadword. */
5260 /* Requesting more elements than are available results in a PFALSE. */
5265 }
5267 /* Return true if we can move VALUE into a register using a single
5268 CNT[BHWD] instruction. */
5270 static bool
5272 {
5274 /* The coefficient must be [1, 16] * {2, 4, 8, 16}. */
5279 }
5281 /* Likewise for rtx X. */
5283 bool
5285 {
5286 poly_int64 value;
5288 }
5290 /* Return the asm string for an instruction with a CNT-like vector size
5291 operand (a vector pattern followed by a multiplier in the range [1, 16]).
5292 PREFIX is the mnemonic without the size suffix and OPERANDS is the
5293 first part of the operands template (the part that comes before the
5294 vector size itself). PATTERN is the pattern to use. FACTOR is the
5295 number of quadwords. NELTS_PER_VQ, if nonzero, is the number of elements
5296 in each quadword. If it is zero, we can use any element size. */
5300 aarch64_svpattern pattern,
5303 {
5307 /* There is some overlap in the ranges of the four CNT instructions.
5308 Here we always use the smallest possible element size, so that the
5309 multiplier is 1 whereever possible. */
5323 else
5326 factor);
5329 }
5331 /* Return the asm string for an instruction with a CNT-like vector size
5332 operand (a vector pattern followed by a multiplier in the range [1, 16]).
5333 PREFIX is the mnemonic without the size suffix and OPERANDS is the
5334 first part of the operands template (the part that comes before the
5335 vector size itself). X is the value of the vector size operand,
5336 as a polynomial integer rtx; we need to convert this into an "all"
5337 pattern with a multiplier. */
5341 rtx x)
5342 {
5347 }
5349 /* Return the asm string for an instruction with a CNT-like vector size
5350 operand (a vector pattern followed by a multiplier in the range [1, 16]).
5351 PREFIX is the mnemonic without the size suffix and OPERANDS is the
5352 first part of the operands template (the part that comes before the
5353 vector size itself). CNT_PAT[0..2] are the operands of the
5354 UNSPEC_SVE_CNT_PAT; see aarch64_sve_cnt_pat for details. */
5359 {
5365 }
5367 /* Return true if we can add X using a single SVE INC or DEC instruction. */
5369 bool
5371 {
5372 poly_int64 value;
5376 }
5378 /* Return the asm string for adding SVE INC/DEC immediate OFFSET to
5379 operand 0. */
5383 {
5389 else
5392 }
5394 /* Return true if we can add VALUE to a register using a single ADDVL
5395 or ADDPL instruction. */
5397 static bool
5399 {
5403 /* FACTOR counts VG / 2, so a value of 2 is one predicate width
5404 and a value of 16 is one vector width. */
5407 }
5409 /* Likewise for rtx X. */
5411 bool
5413 {
5414 poly_int64 value;
5417 }
5419 /* Return the asm string for adding ADDVL or ADDPL immediate OFFSET
5420 to operand 1 and storing the result in operand 0. */
5424 {
5432 else
5435 }
5437 /* Return true if X is a valid immediate for an SVE vector INC or DEC
5438 instruction. If it is, store the number of elements in each vector
5439 quadword in *NELTS_PER_VQ_OUT (if nonnull) and store the multiplication
5440 factor in *FACTOR_OUT (if nonnull). */
5442 bool
5445 {
5446 rtx elt;
5447 poly_int64 value;
5455 /* There's no vector INCB. */
5462 /* The coefficient must be [1, 16] * NELTS_PER_VQ. */
5472 }
5474 /* Return true if X is a valid immediate for an SVE vector INC or DEC
5475 instruction. */
5477 bool
5479 {
5481 }
5483 /* Return the asm template for an SVE vector INC or DEC instruction.
5484 OPERANDS gives the operands before the vector count and X is the
5485 value of the vector count operand itself. */
5489 {
5497 else
5500 }
5502 static int
5504 scalar_int_mode mode)
5505 {
5514 {
5518 }
5520 /* Check to see if the low 32 bits are either 0xffffXXXX or 0xXXXXffff
5521 (with XXXX non-zero). In that case check to see if the move can be done in
5522 a smaller mode. */
5527 {
5531 /* Check if we have to emit a second instruction by checking to see
5532 if any of the upper 32 bits of the original DI mode value is set. */
5543 }
5546 {
5548 {
5553 else
5556 }
5558 }
5560 /* Remaining cases are all for DImode. */
5569 {
5570 /* Try emitting a bitmask immediate with a movk replacing 16 bits.
5571 For a 64-bit bitmask try whether changing 16 bits to all ones or
5572 zeroes creates a valid bitmask. To check any repeated bitmask,
5573 try using 16 bits from the other 32-bit half of val. */
5576 {
5587 }
5589 {
5591 {
5595 }
5597 }
5598 }
5600 /* Generate 2-4 instructions, skipping 16 bits of all zeroes or ones which
5601 are emitted by the initial mov. If one_match > zero_match, skip set bits,
5602 otherwise skip zero bits. */
5614 {
5620 num_insns ++;
5621 }
5624 }
5626 /* Return whether imm is a 128-bit immediate which is simple enough to
5627 expand inline. */
5628 bool
5630 {
5641 }
5644 /* Return the number of temporary registers that aarch64_add_offset_1
5645 would need to add OFFSET to a register. */
5647 static unsigned int
5649 {
5651 }
5653 /* A subroutine of aarch64_add_offset. Set DEST to SRC + OFFSET for
5654 a non-polynomial OFFSET. MODE is the mode of the addition.
5655 FRAME_RELATED_P is true if the RTX_FRAME_RELATED flag should
5656 be set and CFA adjustments added to the generated instructions.
5658 TEMP1, if nonnull, is a register of mode MODE that can be used as a
5659 temporary if register allocation is already complete. This temporary
5660 register may overlap DEST but must not overlap SRC. If TEMP1 is known
5661 to hold abs (OFFSET), EMIT_MOVE_IMM can be set to false to avoid emitting
5662 the immediate again.
5664 Since this function may be used to adjust the stack pointer, we must
5665 ensure that it cannot cause transient stack deallocation (for example
5666 by first incrementing SP and then decrementing when adjusting by a
5667 large immediate). */
5669 static void
5673 {
5681 {
5683 {
5686 }
5688 }
5690 /* Single instruction adjustment. */
5692 {
5696 }
5698 /* Emit 2 additions/subtractions if the adjustment is less than 24 bits
5699 and either:
5701 a) the offset cannot be loaded by a 16-bit move or
5702 b) there is no spare register into which we can move it. */
5706 {
5715 }
5717 /* Emit a move immediate if required and an addition/subtraction. */
5719 {
5723 }
5728 {
5732 }
5733 }
5735 /* Return the number of temporary registers that aarch64_add_offset
5736 would need to move OFFSET into a register or add OFFSET to a register;
5737 ADD_P is true if we want the latter rather than the former. */
5739 static unsigned int
5741 {
5742 /* This follows the same structure as aarch64_add_offset. */
5751 /* Need one register for the ADDVL/ADDPL result. */
5754 {
5757 /* Need one register for the CNT result and one for the multiplication
5758 factor. If necessary, the second temporary can be reused for the
5759 constant part of the offset. */
5761 /* Need one register for the CNT result (which might then
5762 be shifted). */
5764 }
5766 }
5768 /* If X can be represented as a poly_int64, return the number
5769 of temporaries that are required to add it to a register.
5770 Return -1 otherwise. */
5772 int
5774 {
5775 poly_int64 offset;
5779 }
5781 /* Set DEST to SRC + OFFSET. MODE is the mode of the addition.
5782 FRAME_RELATED_P is true if the RTX_FRAME_RELATED flag should
5783 be set and CFA adjustments added to the generated instructions.
5785 TEMP1, if nonnull, is a register of mode MODE that can be used as a
5786 temporary if register allocation is already complete. This temporary
5787 register may overlap DEST if !FRAME_RELATED_P but must not overlap SRC.
5788 If TEMP1 is known to hold abs (OFFSET), EMIT_MOVE_IMM can be set to
5789 false to avoid emitting the immediate again.
5791 TEMP2, if nonnull, is a second temporary register that doesn't
5792 overlap either DEST or REG.
5794 Since this function may be used to adjust the stack pointer, we must
5795 ensure that it cannot cause transient stack deallocation (for example
5796 by first incrementing SP and then decrementing when adjusting by a
5797 large immediate). */
5799 static void
5803 {
5807 || !frame_related_p
5811 /* Try using ADDVL or ADDPL to add the whole value. */
5813 {
5818 }
5820 /* Coefficient 1 is multiplied by the number of 128-bit blocks in an
5821 SVE vector register, over and above the minimum size of 128 bits.
5822 This is equivalent to half the value returned by CNTD with a
5823 vector shape of ALL. */
5827 /* Try using ADDVL or ADDPL to add the VG-based part. */
5831 {
5834 {
5838 }
5839 else
5840 {
5845 }
5846 }
5847 /* Otherwise use a CNT-based sequence. */
5849 {
5850 /* Use a subtraction if we have a negative factor. */
5853 {
5856 }
5858 /* Calculate CNTD * FACTOR / 2. First try to fold the division
5859 into the multiplication. */
5860 rtx val;
5863 /* Use a right shift by 1. */
5865 else
5869 {
5871 {
5872 /* "CNTB Xn, ALL, MUL #FACTOR" is out of range, so calculate
5873 the value with the minimum multiplier and shift it into
5874 position. */
5878 }
5880 }
5881 else
5882 {
5883 /* Base the factor on LOW_BIT if we can calculate LOW_BIT
5884 directly, since that should increase the chances of being
5885 able to use a shift and add sequence. If LOW_BIT itself
5886 is out of range, just use CNTD. */
5889 else
5896 {
5899 }
5900 else
5901 {
5902 /* Go back to using a negative multiplication factor if we have
5903 no register from which to subtract. */
5905 {
5908 }
5912 }
5913 }
5916 {
5917 /* Multiply by 1 << SHIFT. */
5920 }
5922 {
5923 /* Divide by 2. */
5926 }
5928 /* Calculate SRC +/- CNTD * FACTOR / 2. */
5930 {
5933 }
5935 {
5938 }
5941 {
5944 {
5948 poly_offset)));
5949 }
5953 }
5954 else
5955 {
5959 }
5962 }
5966 }
5968 /* Like aarch64_add_offset, but the offset is given as an rtx rather
5969 than a poly_int64. */
5971 void
5974 {
5977 }
5979 /* Add DELTA to the stack pointer, marking the instructions frame-related.
5980 TEMP1 is available as a temporary if nonnull. EMIT_MOVE_IMM is false
5981 if TEMP1 already contains abs (DELTA). */
5985 {
5988 }
5990 /* Subtract DELTA from the stack pointer, marking the instructions
5991 frame-related if FRAME_RELATED_P. TEMP1 is available as a temporary
5992 if nonnull. */
5997 {
6000 }
6002 /* Set DEST to (vec_series BASE STEP). */
6004 static void
6006 {
6010 /* Each operand can be a register or an immediate in the range [-16, 15]. */
6017 }
6019 /* Duplicate 128-bit Advanced SIMD vector SRC so that it fills an SVE
6020 register of mode MODE. Use TARGET for the result if it's nonnull
6021 and convenient.
6023 The two vector modes must have the same element mode. The behavior
6024 is to duplicate architectural lane N of SRC into architectural lanes
6025 N + I * STEP of the result. On big-endian targets, architectural
6026 lane 0 of an Advanced SIMD vector is the last element of the vector
6027 in memory layout, so for big-endian targets this operation has the
6028 effect of reversing SRC before duplicating it. Callers need to
6029 account for this. */
6031 rtx
6033 {
6036 insn_code icode = (BYTES_BIG_ENDIAN
6045 {
6046 /* Create a PARALLEL describing the reversal of SRC. */
6051 }
6054 }
6056 /* Try to force 128-bit vector value SRC into memory and use LD1RQ to fetch
6057 the memory image into DEST. Return true on success. */
6059 static bool
6061 {
6066 /* Make sure that the address is legitimate. */
6068 {
6071 }
6078 }
6080 /* SRC is an SVE CONST_VECTOR that contains N "foreground" values followed
6081 by N "background" values. Try to move it into TARGET using:
6083 PTRUE PRED.<T>, VL<N>
6084 MOV TRUE.<T>, #<foreground>
6085 MOV FALSE.<T>, #<background>
6086 SEL TARGET.<T>, PRED.<T>, TRUE.<T>, FALSE.<T>
6088 The PTRUE is always a single instruction but the MOVs might need a
6089 longer sequence. If the background value is zero (as it often is),
6090 the sequence can sometimes collapse to a PTRUE followed by a
6091 zero-predicated move.
6093 Return the target on success, otherwise return null. */
6095 static rtx
6097 {
6100 /* Make sure that the PTRUE is valid. */
6112 {
6115 }
6117 {
6120 }
6128 }
6130 /* Return a register containing CONST_VECTOR SRC, given that SRC has an
6131 SVE data mode and isn't a legitimate constant. Use TARGET for the
6132 result if convenient.
6134 The returned register can have whatever mode seems most natural
6135 given the contents of SRC. */
6137 static rtx
6139 {
6151 {
6152 /* We have a partial vector mode and a constant whose full-vector
6153 equivalent would occupy a repeating 128-bit sequence. Build that
6154 full-vector equivalent instead, so that we have the option of
6155 using LD1RQ and Advanced SIMD operations. */
6164 }
6167 {
6168 /* The constant is a duplicated quadword but can't be narrowed
6169 beyond a quadword. Get the memory image of the first quadword
6170 as a 128-bit vector and try using LD1RQ to load it from memory.
6172 The effect for both endiannesses is to load memory lane N into
6173 architectural lanes N + I * STEP of the result. On big-endian
6174 targets, the layout of the 128-bit vector in an Advanced SIMD
6175 register would be different from its layout in an SVE register,
6176 but this 128-bit vector is a memory value only. */
6181 }
6184 {
6185 /* The vector is a repeating sequence of 64 bits or fewer.
6186 See if we can load them using an Advanced SIMD move and then
6187 duplicate it to fill a vector. This is better than using a GPR
6188 move because it keeps everything in the same register file. */
6192 {
6193 /* We want memory lane N to go into architectural lane N,
6194 so reverse for big-endian targets. The DUP .Q pattern
6195 has a compensating reverse built-in. */
6198 }
6201 {
6204 }
6206 /* Get an integer representation of the repeating part of Advanced
6207 SIMD vector VQ_SRC. This preserves the endianness of VQ_SRC,
6208 which for big-endian targets is lane-swapped wrt a normal
6209 Advanced SIMD vector. This means that for both endiannesses,
6210 memory lane N of SVE vector SRC corresponds to architectural
6211 lane N of a register holding VQ_SRC. This in turn means that
6212 memory lane 0 of SVE vector SRC is in the lsb of VQ_SRC (viewed
6213 as a single 128-bit value) and thus that memory lane 0 of SRC is
6214 in the lsb of the integer. Duplicating the integer therefore
6215 ensures that memory lane N of SRC goes into architectural lane
6216 N + I * INDEX of the SVE register. */
6220 {
6221 /* Pretend that we had a vector of INT_MODE to start with. */
6225 /* If the integer can be moved into a general register by a
6226 single instruction, do that and duplicate the result. */
6229 {
6232 }
6233 }
6235 /* We're duplicating a single value, but can't do better than
6236 force it to memory and load from there. This handles things
6237 like symbolic constants. */
6241 {
6242 /* Load the element from memory if we can, otherwise move it into
6243 a register and use a DUP. */
6248 }
6249 }
6251 /* Try using INDEX. */
6254 {
6257 }
6259 /* From here on, it's better to force the whole constant to memory
6260 if we can. */
6268 /* Expand each pattern individually. */
6270 rtx_vector_builder builder;
6273 {
6278 }
6280 /* Use permutes to interleave the separate vectors. */
6282 {
6285 {
6290 }
6291 }
6294 }
6296 /* Use WHILE to set a predicate register of mode MODE in which the first
6297 VL bits are set and the rest are clear. Use TARGET for the register
6298 if it's nonnull and convenient. */
6300 static rtx
6303 {
6309 }
6311 static rtx
6314 /* BUILDER is a constant predicate in which the index of every set bit
6315 is a multiple of ELT_SIZE (which is <= 8). Try to load the constant
6316 by inverting every element at a multiple of ELT_SIZE and EORing the
6317 result with an ELT_SIZE PTRUE.
6319 Return a register that contains the constant on success, otherwise
6320 return null. Use TARGET as the register if it is nonnull and
6321 convenient. */
6323 static rtx
6326 {
6327 /* Invert every element at a multiple of ELT_SIZE, keeping the
6328 other bits zero. */
6334 else
6338 /* See if we can load the constant cheaply. */
6343 /* EOR the result with an ELT_SIZE PTRUE. */
6350 }
6352 /* BUILDER is a constant predicate in which the index of every set bit
6353 is a multiple of ELT_SIZE (which is <= 8). Try to load the constant
6354 using a TRN1 of size PERMUTE_SIZE, which is >= ELT_SIZE. Return the
6355 register on success, otherwise return null. Use TARGET as the register
6356 if nonnull and convenient. */
6358 static rtx
6362 {
6363 /* We're going to split the constant into two new constants A and B,
6364 with element I of BUILDER going into A if (I & PERMUTE_SIZE) == 0
6365 and into B otherwise. E.g. for PERMUTE_SIZE == 4 && ELT_SIZE == 1:
6367 A: { 0, 1, 2, 3, _, _, _, _, 8, 9, 10, 11, _, _, _, _ }
6368 B: { 4, 5, 6, 7, _, _, _, _, 12, 13, 14, 15, _, _, _, _ }
6370 where _ indicates elements that will be discarded by the permute.
6372 First calculate the ELT_SIZEs for A and B. */
6377 {
6380 else
6382 }
6386 /* Now construct the vectors themselves. */
6394 {
6397 }
6399 {
6400 /* The A and B elements are significant. */
6403 }
6404 else
6405 {
6406 /* The A and B elements are going to be discarded, so pick whatever
6407 is likely to give a nice constant. We are targeting element
6408 sizes A_ELT_SIZE and B_ELT_SIZE for A and B respectively,
6409 with the aim of each being a sequence of ones followed by
6410 a sequence of zeros. So:
6412 * if X_ELT_SIZE <= PERMUTE_SIZE, the best approach is to
6413 duplicate the last X_ELT_SIZE element, to extend the
6414 current sequence of ones or zeros.
6416 * if X_ELT_SIZE > PERMUTE_SIZE, the best approach is to add a
6417 zero, so that the constant really does have X_ELT_SIZE and
6418 not a smaller size. */
6421 else
6425 else
6427 }
6431 /* Try loading A into a register. */
6437 /* Try loading B into a register. */
6440 {
6443 {
6446 }
6447 }
6449 /* Emit the TRN1 itself. We emit a TRN that operates on VNx16BI
6450 operands but permutes them as though they had mode MODE. */
6456 }
6458 /* Subroutine of aarch64_expand_sve_const_pred. Try to load the VNx16BI
6459 constant in BUILDER into an SVE predicate register. Return the register
6460 on success, otherwise return null. Use TARGET for the register if
6461 nonnull and convenient.
6463 ALLOW_RECURSE_P is true if we can use methods that would call this
6464 function recursively. */
6466 static rtx
6469 {
6471 /* A PFALSE or a PTRUE .B ALL. */
6476 {
6477 /* If we can load the constant using PTRUE, use it as-is. */
6482 /* Otherwise use WHILE to set the first VL bits. */
6484 }
6489 /* Try inverting the vector in element size ELT_SIZE and then EORing
6490 the result with an ELT_SIZE PTRUE. */
6493 elt_size))
6496 /* Try using TRN1 to permute two simpler constants. */
6503 }
6505 /* Return an SVE predicate register that contains the VNx16BImode
6506 constant in BUILDER, without going through the move expanders.
6508 The returned register can have whatever mode seems most natural
6509 given the contents of BUILDER. Use TARGET for the result if
6510 convenient. */
6512 static rtx
6514 {
6515 /* Try loading the constant using pure predicate operations. */
6519 /* Try forcing the constant to memory. */
6522 {
6526 }
6528 /* The last resort is to load the constant as an integer and then
6529 compare it against zero. Use -1 for set bits in order to increase
6530 the changes of using SVE DUPM or an Advanced SIMD byte mask. */
6538 }
6540 /* Set DEST to immediate IMM. */
6542 void
6544 {
6547 /* Check on what type of symbol it is. */
6548 scalar_int_mode int_mode;
6554 {
6555 rtx mem;
6556 poly_int64 offset;
6557 HOST_WIDE_INT const_offset;
6560 /* If we have (const (plus symbol offset)), separate out the offset
6561 before we start classifying the symbol. */
6564 /* We must always add an offset involving VL separately, rather than
6565 folding it into the relocation. */
6567 {
6569 {
6572 }
6575 else
6576 {
6577 /* Do arithmetic on 32-bit values if the result is smaller
6578 than that. */
6580 {
6581 /* It is invalid to do symbol calculations in modes
6582 narrower than SImode. */
6586 }
6588 {
6592 }
6593 else
6596 }
6598 }
6602 {
6609 {
6615 }
6620 /* If we aren't generating PC relative literals, then
6621 we need to expand the literal pool access carefully.
6622 This is something that needs to be done in a number
6623 of places, so could well live as a separate function. */
6625 {
6632 }
6649 {
6655 }
6656 /* FALLTHRU */
6669 }
6670 }
6673 {
6675 {
6676 /* Only the low bit of each .H, .S and .D element is defined,
6677 so we can set the upper bits to whatever we like. If the
6678 predicate is all-true in MODE, prefer to set all the undefined
6679 bits as well, so that we can share a single .B predicate for
6680 all modes. */
6684 /* All methods for constructing predicate modes wider than VNx16BI
6685 will set the upper bits of each element to zero. Expose this
6686 by moving such constants as a VNx16BI, so that all bits are
6687 significant and so that constants for different modes can be
6688 shared. The wider constant will still be available as a
6689 REG_EQUAL note. */
6690 rtx_vector_builder builder;
6692 {
6697 }
6698 }
6702 {
6705 }
6709 {
6713 }
6719 }
6723 }
6725 /* Return the MEM rtx that provides the canary value that should be used
6726 for stack-smashing protection. MODE is the mode of the memory.
6727 For SSP_GLOBAL, DECL_RTL is the MEM rtx for the canary variable
6728 (__stack_chk_guard), otherwise it has no useful value. SALT_TYPE
6729 indicates whether the caller is performing a SET or a TEST operation. */
6731 rtx
6733 aarch64_salt_type salt_type)
6734 {
6735 rtx addr;
6737 {
6740 poly_int64 offset;
6749 }
6750 else
6751 {
6752 /* Calculate the address from the system register. */
6757 else
6758 {
6761 }
6763 }
6765 }
6767 /* Emit an SVE predicated move from SRC to DEST. PRED is a predicate
6768 that is known to contain PTRUE. */
6770 void
6772 {
6780 }
6782 /* Expand a pre-RA SVE data move from SRC to DEST in which at least one
6783 operand is in memory. In this case we need to use the predicated LD1
6784 and ST1 instead of LDR and STR, both for correctness on big-endian
6785 targets and because LD1 and ST1 support a wider range of addressing modes.
6786 PRED_MODE is the mode of the predicate.
6788 See the comment at the head of aarch64-sve.md for details about the
6789 big-endian handling. */
6791 void
6793 {
6798 {
6802 else
6805 }
6807 }
6809 /* Called only on big-endian targets. See whether an SVE vector move
6810 from SRC to DEST is effectively a REV[BHW] instruction, because at
6811 least one operand is a subreg of an SVE vector that has wider or
6812 narrower elements. Return true and emit the instruction if so.
6814 For example:
6816 (set (reg:VNx8HI R1) (subreg:VNx8HI (reg:VNx16QI R2) 0))
6818 represents a VIEW_CONVERT between the following vectors, viewed
6819 in memory order:
6821 R2: { [0].high, [0].low, [1].high, [1].low, ... }
6822 R1: { [0], [1], [2], [3], ... }
6824 The high part of lane X in R2 should therefore correspond to lane X*2
6825 of R1, but the register representations are:
6827 msb lsb
6828 R2: ...... [1].high [1].low [0].high [0].low
6829 R1: ...... [3] [2] [1] [0]
6831 where the low part of lane X in R2 corresponds to lane X*2 in R1.
6832 We therefore need a reverse operation to swap the high and low values
6833 around.
6835 This is purely an optimization. Without it we would spill the
6836 subreg operand to the stack in one mode and reload it in the
6837 other mode, which has the same effect as the REV. */
6839 bool
6841 {
6844 /* Do not try to optimize subregs that LRA has created for matched
6845 reloads. These subregs only exist as a temporary measure to make
6846 the RTL well-formed, but they are exempt from the usual
6847 TARGET_CAN_CHANGE_MODE_CLASS rules.
6849 For example, if we have:
6851 (set (reg:VNx8HI R1) (foo:VNx8HI (reg:VNx4SI R2)))
6853 and the constraints require R1 and R2 to be in the same register,
6854 LRA may need to create RTL such as:
6856 (set (subreg:VNx4SI (reg:VNx8HI TMP) 0) (reg:VNx4SI R2))
6857 (set (reg:VNx8HI TMP) (foo:VNx8HI (subreg:VNx4SI (reg:VNx8HI TMP) 0)))
6858 (set (reg:VNx8HI R1) (reg:VNx8HI TMP))
6860 which forces both the input and output of the original instruction
6861 to use the same hard register. But for this to work, the normal
6862 rules have to be suppressed on the subreg input, otherwise LRA
6863 would need to reload that input too, meaning that the process
6864 would never terminate. To compensate for this, the normal rules
6865 are also suppressed for the subreg output of the first move.
6866 Ignoring the special case and handling the first move normally
6867 would therefore generate wrong code: we would reverse the elements
6868 for the first subreg but not reverse them back for the second subreg. */
6874 /* The optimization handles two single SVE REGs with different element
6875 sizes. */
6884 /* Generate *aarch64_sve_mov<mode>_subreg_be. */
6887 UNSPEC_REV_SUBREG);
6890 }
6892 /* Return a copy of X with mode MODE, without changing its other
6893 attributes. Unlike gen_lowpart, this doesn't care whether the
6894 mode change is valid. */
6896 rtx
6898 {
6905 }
6907 /* Return the SVE REV[BHW] unspec for reversing quantites of mode MODE
6908 stored in wider integer containers. */
6910 static unsigned int
6912 {
6914 {
6918 }
6920 }
6922 /* Split a *aarch64_sve_mov<mode>_subreg_be pattern with the given
6923 operands. */
6925 void
6927 {
6928 /* Decide which REV operation we need. The mode with wider elements
6929 determines the mode of the operands and the mode with the narrower
6930 elements determines the reverse width. */
6940 /* Get the operands in the appropriate modes and emit the instruction. */
6946 }
6948 static bool
6950 {
6955 }
6957 /* Subroutine of aarch64_pass_by_reference for arguments that are not
6958 passed in SVE registers. */
6960 static bool
6963 {
6964 HOST_WIDE_INT size;
6965 machine_mode dummymode;
6968 /* GET_MODE_SIZE (BLKmode) is useless since it is 0. */
6971 else
6972 /* No frontends can create types with variable-sized modes, so we
6973 shouldn't be asked to pass or return them. */
6976 /* Aggregates are passed by reference based on their size. */
6980 /* Variable sized arguments are always returned by reference. */
6984 /* Can this be a candidate to be passed in fp/simd register(s)? */
6990 /* Arguments which are variable sized or larger than 2 registers are
6991 passed by reference unless they are a homogenous floating point
6992 aggregate. */
6994 }
6996 /* Implement TARGET_PASS_BY_REFERENCE. */
6998 static bool
7001 {
7007 pure_scalable_type_info pst_info;
7009 {
7012 /* We can't gracefully recover at this point, so make this a
7013 fatal error. */
7017 /* Variadic SVE types are passed by reference. Normal non-variadic
7018 arguments are too if we've run out of registers. */
7030 }
7032 }
7034 /* Return TRUE if VALTYPE is padded to its least significant bits. */
7035 static bool
7037 {
7038 machine_mode dummy_mode;
7041 /* Never happens in little-endian mode. */
7045 /* Only composite types smaller than or equal to 16 bytes can
7046 be potentially returned in registers. */
7052 /* But not a composite that is an HFA (Homogeneous Floating-point Aggregate)
7053 or an HVA (Homogeneous Short-Vector Aggregate); such a special composite
7054 is always passed/returned in the least significant bits of fp/simd
7055 register(s). */
7061 /* Likewise pure scalable types for SVE vector and predicate registers. */
7062 pure_scalable_type_info pst_info;
7067 }
7069 /* Implement TARGET_FUNCTION_VALUE.
7070 Define how to find the value returned by a function. */
7072 static rtx
7075 {
7076 machine_mode mode;
7083 pure_scalable_type_info pst_info;
7087 /* Generic vectors that map to full SVE modes with -msve-vector-bits=N
7088 are returned in memory, not by value. */
7093 {
7097 {
7100 }
7101 }
7104 machine_mode ag_mode;
7107 {
7110 {
7113 }
7120 else
7121 {
7123 rtx par;
7127 {
7132 }
7134 }
7135 }
7136 else
7137 {
7139 {
7140 /* Vector types can acquire a partial SVE mode using things like
7141 __attribute__((vector_size(N))), and this is potentially useful.
7142 However, the choice of mode doesn't affect the type's ABI
7143 identity, so we should treat the types as though they had
7144 the associated integer mode, just like they did before SVE
7145 was introduced.
7147 We know that the vector must be 128 bits or smaller,
7148 otherwise we'd have returned it in memory instead. */
7157 }
7159 }
7160 }
7162 /* Implements TARGET_FUNCTION_VALUE_REGNO_P.
7163 Return true if REGNO is the number of a hard register in which the values
7164 of called function may come back. */
7166 static bool
7168 {
7169 /* Maximum of 16 bytes can be returned in the general registers. Examples
7170 of 16-byte return values are: 128-bit integers and 16-byte small
7171 structures (excluding homogeneous floating-point aggregates). */
7175 /* Up to four fp/simd registers can return a function value, e.g. a
7176 homogeneous floating-point aggregate having four members. */
7181 }
7183 /* Subroutine for aarch64_return_in_memory for types that are not returned
7184 in SVE registers. */
7186 static bool
7188 {
7189 HOST_WIDE_INT size;
7190 machine_mode ag_mode;
7196 /* Simple scalar types always returned in registers. */
7203 /* Types larger than 2 registers returned in memory. */
7206 }
7208 /* Implement TARGET_RETURN_IN_MEMORY.
7210 If the type T of the result of a function is such that
7211 void func (T arg)
7212 would require that arg be passed as a value in a register (or set of
7213 registers) according to the parameter passing rules, then the result
7214 is returned in the same registers as would be used for such an
7215 argument. */
7217 static bool
7219 {
7220 pure_scalable_type_info pst_info;
7222 {
7234 }
7236 }
7238 static bool
7241 {
7246 }
7248 /* Given MODE and TYPE of a function argument, return the alignment in
7249 bits. The idea is to suppress any stronger alignment requested by
7250 the user and opt for the natural alignment (specified in AAPCS64 \S
7251 4.1). ABI_BREAK is set to true if the alignment was incorrectly
7252 calculated in versions of GCC prior to GCC-9. This is a helper
7253 function for local use only. */
7255 static unsigned int
7258 {
7278 {
7279 /* Note that we explicitly consider zero-sized fields here,
7280 even though they don't map to AAPCS64 machine types.
7281 For example, in:
7283 struct __attribute__((aligned(8))) empty {};
7285 struct s {
7286 [[no_unique_address]] empty e;
7287 int x;
7288 };
7290 "s" contains only one Fundamental Data Type (the int field)
7291 but gains 8-byte alignment and size thanks to "e". */
7294 bitfield_alignment
7297 }
7300 {
7303 }
7306 }
7308 /* Layout a function argument according to the AAPCS64 rules. The rule
7309 numbers refer to the rule numbers in the AAPCS64. ORIG_MODE is the
7310 mode that was originally given to us by the target hook, whereas the
7311 mode in ARG might be the result of replacing partial SVE modes with
7312 the equivalent integer mode. */
7314 static void
7316 {
7322 HOST_WIDE_INT size;
7325 /* We need to do this once per argument. */
7331 pure_scalable_type_info pst_info;
7333 {
7334 /* The PCS says that it is invalid to pass an SVE value to an
7335 unprototyped function. There is no ABI-defined location we
7336 can return in this case, so we have no real choice but to raise
7337 an error immediately, even though this is only a query function. */
7339 {
7343 /* Avoid repeating the message, and avoid tripping the assert
7344 below. */
7346 }
7348 /* We would have converted the argument into pass-by-reference
7349 form if it didn't fit in registers. */
7359 }
7361 /* Generic vectors that map to full SVE modes with -msve-vector-bits=N
7362 are passed by reference, not by value. */
7366 /* Vector types can acquire a partial SVE mode using things like
7367 __attribute__((vector_size(N))), and this is potentially useful.
7368 However, the choice of mode doesn't affect the type's ABI
7369 identity, so we should treat the types as though they had
7370 the associated integer mode, just like they did before SVE
7371 was introduced.
7373 We know that the vector must be 128 bits or smaller,
7374 otherwise we'd have passed it in memory instead. */
7379 /* Size in bytes, rounded to the nearest multiple of 8 bytes. */
7382 else
7383 /* No frontends can create types with variable-sized modes, so we
7384 shouldn't be asked to pass or return them. */
7390 mode,
7391 type,
7395 /* allocate_ncrn may be false-positive, but allocate_nvrn is quite reliable.
7396 The following code thus handles passing by SIMD/FP registers first. */
7400 /* C1 - C5 for floating point, homogenous floating point aggregates (HFA)
7401 and homogenous short-vector aggregates (HVA). */
7403 {
7408 {
7411 {
7414 }
7421 else
7422 {
7423 rtx par;
7427 {
7430 rtx offset = gen_int_mode
7434 }
7436 }
7438 }
7439 else
7440 {
7441 /* C.3 NSRN is set to 8. */
7444 }
7445 }
7450 /* C6 - C9. though the sign and zero extension semantics are
7451 handled elsewhere. This is the case where the argument fits
7452 entirely general registers. */
7454 {
7457 /* C.8 if the argument has an alignment of 16 then the NGRN is
7458 rounded up to the next even number. */
7461 /* The == 16 * BITS_PER_UNIT instead of >= 16 * BITS_PER_UNIT
7462 comparison is there because for > 16 * BITS_PER_UNIT
7463 alignment nregs should be > 2 and therefore it should be
7464 passed by reference rather than value. */
7467 {
7473 }
7475 /* If an argument with an SVE mode needs to be shifted up to the
7476 high part of the register, treat it as though it had an integer mode.
7477 Using the normal (parallel [...]) would suppress the shifting. */
7479 && BYTES_BIG_ENDIAN
7482 {
7485 }
7487 /* NREGS can be 0 when e.g. an empty structure is to be passed.
7488 A reg is still generated for it, but the caller should be smart
7489 enough not to use it. */
7494 else
7495 {
7496 rtx par;
7501 {
7509 }
7511 }
7515 }
7517 /* C.11 */
7520 /* The argument is passed on stack; record the needed number of words for
7521 this argument and align the total size if necessary. */
7522 on_stack:
7527 {
7530 {
7535 }
7536 }
7538 }
7540 /* Implement TARGET_FUNCTION_ARG. */
7542 static rtx
7544 {
7555 }
7557 void
7559 const_tree fntype,
7560 rtx libname ATTRIBUTE_UNUSED,
7561 const_tree fndecl ATTRIBUTE_UNUSED,
7564 {
7573 else
7582 && !TARGET_FLOAT
7584 {
7591 }
7594 && !TARGET_SVE
7596 {
7597 /* We can't gracefully recover at this point, so make this a
7598 fatal error. */
7601 fndecl);
7602 else
7605 }
7606 }
7608 static void
7611 {
7616 {
7627 }
7628 }
7630 bool
7632 {
7635 }
7637 /* Implement FUNCTION_ARG_BOUNDARY. Every parameter gets at least
7638 PARM_BOUNDARY bits of alignment, but will be given anything up
7639 to STACK_BOUNDARY bits if the type requires it. This makes sure
7640 that both before and after the layout of each argument, the Next
7641 Stacked Argument Address (NSAA) will have a minimum alignment of
7642 8 bytes. */
7644 static unsigned int
7646 {
7652 {
7657 }
7660 }
7662 /* Implement TARGET_GET_RAW_RESULT_MODE and TARGET_GET_RAW_ARG_MODE. */
7664 static fixed_size_mode
7666 {
7668 /* Don't use the SVE part of the register for __builtin_apply and
7669 __builtin_return. The SVE registers aren't used by the normal PCS,
7670 so using them there would be a waste of time. The PCS extensions
7671 for SVE types are fundamentally incompatible with the
7672 __builtin_return/__builtin_apply interface. */
7675 }
7677 /* Implement TARGET_FUNCTION_ARG_PADDING.
7679 Small aggregate types are placed in the lowest memory address.
7681 The related parameter passing rules are B.4, C.3, C.5 and C.14. */
7683 static pad_direction
7685 {
7686 /* On little-endian targets, the least significant byte of every stack
7687 argument is passed at the lowest byte address of the stack slot. */
7691 /* Otherwise, integral, floating-point and pointer types are padded downward:
7692 the least significant byte of a stack argument is passed at the highest
7693 byte address of the stack slot. */
7700 /* Everything else padded upward, i.e. data in first byte of stack slot. */
7702 }
7704 /* Similarly, for use by BLOCK_REG_PADDING (MODE, TYPE, FIRST).
7706 It specifies padding for the last (may also be the only)
7707 element of a block move between registers and memory. If
7708 assuming the block is in the memory, padding upward means that
7709 the last element is padded after its highest significant byte,
7710 while in downward padding, the last element is padded at the
7711 its least significant byte side.
7713 Small aggregates and small complex types are always padded
7714 upwards.
7716 We don't need to worry about homogeneous floating-point or
7717 short-vector aggregates; their move is not affected by the
7718 padding direction determined here. Regardless of endianness,
7719 each element of such an aggregate is put in the least
7720 significant bits of a fp/simd register.
7722 Return !BYTES_BIG_ENDIAN if the least significant byte of the
7723 register has useful data, and return the opposite if the most
7724 significant byte does. */
7726 bool
7729 {
7731 /* Aside from pure scalable types, small composite types are always
7732 padded upward. */
7734 {
7735 HOST_WIDE_INT size;
7738 else
7739 /* No frontends can create types with variable-sized modes, so we
7740 shouldn't be asked to pass or return them. */
7743 {
7744 pure_scalable_type_info pst_info;
7748 }
7749 }
7751 /* Otherwise, use the default padding. */
7753 }
7755 static scalar_int_mode
7757 {
7759 }
7761 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP)
7763 /* We use the 12-bit shifted immediate arithmetic instructions so values
7764 must be multiple of (1 << 12), i.e. 4096. */
7765 #define ARITH_FACTOR 4096
7767 #if (PROBE_INTERVAL % ARITH_FACTOR) != 0
7768 #error Cannot use simple address calculation for stack probing
7769 #endif
7771 /* Emit code to probe a range of stack addresses from FIRST to FIRST+POLY_SIZE,
7772 inclusive. These are offsets from the current stack pointer. */
7774 static void
7776 {
7777 HOST_WIDE_INT size;
7779 {
7782 }
7786 /* See the same assertion on PROBE_INTERVAL above. */
7789 /* See if we have a constant small number of probes to generate. If so,
7790 that's the easy case. */
7792 {
7799 }
7801 /* The run-time loop is made up of 8 insns in the generic case while the
7802 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */
7804 {
7809 stack_pointer_rtx,
7813 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until
7814 it exceeds SIZE. If only two probes are needed, this will not
7815 generate any code. Then probe at FIRST + SIZE. */
7817 {
7821 }
7825 {
7830 }
7831 else
7833 }
7835 /* Otherwise, do the same as above, but in a loop. Note that we must be
7836 extra careful with variables wrapping around because we might be at
7837 the very top (or the very bottom) of the address space and we have
7838 to be able to handle this case properly; in particular, we use an
7839 equality test for the loop condition. */
7840 else
7841 {
7844 /* Step 1: round SIZE to the previous multiple of the interval. */
7849 /* Step 2: compute initial and final value of the loop counter. */
7851 /* TEST_ADDR = SP + FIRST. */
7855 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */
7858 {
7862 }
7863 else
7867 /* Step 3: the loop
7869 do
7870 {
7871 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL
7872 probe at TEST_ADDR
7873 }
7874 while (TEST_ADDR != LAST_ADDR)
7876 probes at FIRST + N * PROBE_INTERVAL for values of N from 1
7877 until it is equal to ROUNDED_SIZE. */
7882 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time
7883 that SIZE is equal to ROUNDED_SIZE. */
7886 {
7890 {
7895 }
7896 else
7898 }
7899 }
7901 /* Make sure nothing is scheduled before we are done. */
7903 }
7905 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are
7906 absolute addresses. */
7910 {
7917 /* Loop. */
7920 HOST_WIDE_INT stack_clash_probe_interval
7923 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */
7925 HOST_WIDE_INT interval;
7928 else
7936 /* If doing stack clash protection then we probe up by the ABI specified
7937 amount. We do this because we're dropping full pages at a time in the
7938 loop. But if we're doing non-stack clash probing, probe at SP 0. */
7941 else
7944 /* Probe at TEST_ADDR. If we're inside the loop it is always safe to probe
7945 by this amount for each iteration. */
7948 /* Test if TEST_ADDR == LAST_ADDR. */
7952 /* Branch. */
7958 }
7960 /* Emit the probe loop for doing stack clash probes and stack adjustments for
7961 SVE. This emits probes from BASE to BASE - ADJUSTMENT based on a guard size
7962 of GUARD_SIZE. When a probe is emitted it is done at most
7963 MIN_PROBE_THRESHOLD bytes from the current BASE at an interval of
7964 at most MIN_PROBE_THRESHOLD. By the end of this function
7965 BASE = BASE - ADJUSTMENT. */
7970 {
7971 /* This function is not allowed to use any instruction generation function
7972 like gen_ and friends. If you do you'll likely ICE during CFG validation,
7973 so instead emit the code you want using output_asm_insn. */
7978 /* The minimum required allocation before the residual requires probing. */
7981 /* Clamp the value down to the nearest value that can be used with a cmp. */
7996 /* Emit loop start label. */
7999 /* ADJUSTMENT < RESIDUAL_PROBE_GUARD. */
8004 /* Branch to end if not enough adjustment to probe. */
8009 /* BASE = BASE - RESIDUAL_PROBE_GUARD. */
8014 /* Probe at BASE. */
8018 /* ADJUSTMENT = ADJUSTMENT - RESIDUAL_PROBE_GUARD. */
8023 /* Branch to start if still more bytes to allocate. */
8028 /* No probe leave. */
8031 /* BASE = BASE - ADJUSTMENT. */
8036 }
8038 /* Determine whether a frame chain needs to be generated. */
8039 static bool
8041 {
8042 /* Force a frame chain for EH returns so the return address is at FP+8. */
8046 /* A leaf function cannot have calls or write LR. */
8049 /* Don't use a frame chain in leaf functions if leaf frame pointers
8050 are disabled. */
8055 }
8057 /* Mark the registers that need to be saved by the callee and calculate
8058 the size of the callee-saved registers area and frame record (both FP
8059 and LR may be omitted). */
8060 static void
8062 {
8072 /* Adjust the outgoing arguments size if required. Keep it in sync with what
8073 the mid-end is doing. */
8076 #define SLOT_NOT_REQUIRED (-2)
8077 #define SLOT_REQUIRED (-1)
8083 /* First mark all the registers that really need to be saved... */
8087 /* ... that includes the eh data registers (if needed)... */
8092 /* ... and any callee saved register that dataflow says is live. */
8104 {
8109 }
8111 /* Big-endian SVE frames need a spare predicate register in order
8112 to save Z8-Z15. Decide which register they should use. Prefer
8113 an unused argument register if possible, so that we don't force P4
8114 to be saved unnecessarily. */
8118 {
8127 }
8135 /* With stack-clash, LR must be saved in non-leaf functions. The saving of
8136 LR counts as an implicit probe which allows us to maintain the invariant
8137 described in the comment at expand_prologue. */
8141 /* Now assign stack slots for the registers. Start with the predicate
8142 registers, since predicate LDR and STR have a relatively small
8143 offset range. These saves happen below the hard frame pointer. */
8146 {
8149 }
8152 {
8153 /* If we have any vector registers to save above the predicate registers,
8154 the offset of the vector register save slots need to be a multiple
8155 of the vector size. This lets us use the immediate forms of LDR/STR
8156 (or LD1/ST1 for big-endian).
8158 A vector register is 8 times the size of a predicate register,
8159 and we need to save a maximum of 12 predicate registers, so the
8160 first vector register will be at either #1, MUL VL or #2, MUL VL.
8162 If we don't have any vector registers to save, and we know how
8163 big the predicate save area is, we can just round it up to the
8164 next 16-byte boundary. */
8167 else
8168 {
8173 else
8175 }
8176 }
8178 /* If we need to save any SVE vector registers, add them next. */
8182 {
8185 }
8187 /* OFFSET is now the offset of the hard frame pointer from the bottom
8188 of the callee save area. */
8192 {
8193 /* FP and LR are placed in the linkage record. */
8199 }
8203 {
8210 }
8218 {
8219 /* If there is an alignment gap between integer and fp callee-saves,
8220 allocate the last fp register to it if possible. */
8222 && has_align_gap
8225 {
8228 }
8237 }
8245 poly_int64 above_outgoing_args
8250 frame.hard_fp_offset
8253 /* Both these values are already aligned. */
8269 /* Shadow call stack only deals with functions where the LR is pushed
8270 onto the stack and without specifying the "no_sanitize" attribute
8271 with the argument "shadow-call-stack". */
8272 frame.is_scs_enabled
8277 /* When shadow call stack is enabled, the scs_pop in the epilogue will
8278 restore x30, and we don't need to pop x30 again in the traditional
8279 way. Pop candidates record the registers that need to be popped
8280 eventually. */
8282 {
8287 }
8289 /* If candidate2 is INVALID_REGNUM, we need to adjust max_push_offset to
8290 256 to ensure that the offset meets the requirements of emit_move_insn.
8291 Similarly, if candidate1 is INVALID_REGNUM, we need to set
8292 max_push_offset to 0, because no registers are popped at this time,
8293 so callee_adjust cannot be adjusted. */
8301 HOST_WIDE_INT const_saved_regs_size;
8305 {
8306 /* Simple, small frame with no outgoing arguments:
8308 stp reg1, reg2, [sp, -frame_size]!
8309 stp reg3, reg4, [sp, 16] */
8311 }
8315 /* We could handle this case even with outgoing args, provided
8316 that the number of args left us with valid offsets for all
8317 predicate and vector save slots. It's such a rare case that
8318 it hardly seems worth the effort though. */
8323 {
8324 /* Frame with small outgoing arguments:
8326 sub sp, sp, frame_size
8327 stp reg1, reg2, [sp, outgoing_args_size]
8328 stp reg3, reg4, [sp, outgoing_args_size + 16] */
8331 }
8335 {
8336 /* Frame in which all saves are SVE saves:
8338 sub sp, sp, hard_fp_offset + below_hard_fp_saved_regs_size
8339 save SVE registers relative to SP
8340 sub sp, sp, outgoing_args_size */
8344 }
8347 {
8348 /* Frame with large outgoing arguments or SVE saves, but with
8349 a small local area:
8351 stp reg1, reg2, [sp, -hard_fp_offset]!
8352 stp reg3, reg4, [sp, 16]
8353 [sub sp, sp, below_hard_fp_saved_regs_size]
8354 [save SVE registers relative to SP]
8355 sub sp, sp, outgoing_args_size */
8359 }
8360 else
8361 {
8362 /* Frame with large local area and outgoing arguments or SVE saves,
8363 using frame pointer:
8365 sub sp, sp, hard_fp_offset
8366 stp x29, x30, [sp, 0]
8367 add x29, sp, 0
8368 stp reg3, reg4, [sp, 16]
8369 [sub sp, sp, below_hard_fp_saved_regs_size]
8370 [save SVE registers relative to SP]
8371 sub sp, sp, outgoing_args_size */
8375 }
8377 /* Make sure the individual adjustments add up to the full frame size. */
8384 {
8385 /* We've decided not to associate any register saves with the initial
8386 stack allocation. */
8389 }
8392 }
8394 /* Return true if the register REGNO is saved on entry to
8395 the current function. */
8397 static bool
8399 {
8401 }
8403 /* Return the next register up from REGNO up to LIMIT for the callee
8404 to save. */
8406 static unsigned
8408 {
8410 regno ++;
8412 }
8414 /* Push the register number REGNO of mode MODE to the stack with write-back
8415 adjusting the stack by ADJUSTMENT. */
8417 static void
8419 HOST_WIDE_INT adjustment)
8420 {
8431 }
8433 /* Generate and return an instruction to store the pair of registers
8434 REG and REG2 of mode MODE to location BASE with write-back adjusting
8435 the stack location BASE by ADJUSTMENT. */
8437 static rtx
8439 HOST_WIDE_INT adjustment)
8440 {
8442 {
8457 }
8458 }
8460 /* Push registers numbered REGNO1 and REGNO2 to the stack, adjusting the
8461 stack pointer by ADJUSTMENT. */
8463 static void
8465 {
8480 }
8482 /* Load the pair of register REG, REG2 of mode MODE from stack location BASE,
8483 adjusting it by ADJUSTMENT afterwards. */
8485 static rtx
8487 HOST_WIDE_INT adjustment)
8488 {
8490 {
8502 }
8503 }
8505 /* Pop the two registers numbered REGNO1, REGNO2 from the stack, adjusting it
8506 afterwards by ADJUSTMENT and writing the appropriate REG_CFA_RESTORE notes
8507 into CFI_OPS. */
8509 static void
8512 {
8519 {
8523 }
8524 else
8525 {
8530 }
8531 }
8533 /* Generate and return a store pair instruction of mode MODE to store
8534 register REG1 to MEM1 and register REG2 to MEM2. */
8536 static rtx
8538 rtx reg2)
8539 {
8541 {
8559 }
8560 }
8562 /* Generate and regurn a load pair isntruction of mode MODE to load register
8563 REG1 from MEM1 and register REG2 from MEM2. */
8565 static rtx
8567 rtx mem2)
8568 {
8570 {
8585 }
8586 }
8588 /* Return TRUE if return address signing should be enabled for the current
8589 function, otherwise return FALSE. */
8591 bool
8593 {
8594 /* This function should only be called after frame laid out. */
8597 /* Turn return address signing off in any function that uses
8598 __builtin_eh_return. The address passed to __builtin_eh_return
8599 is not signed so either it has to be signed (with original sp)
8600 or the code path that uses it has to avoid authenticating it.
8601 Currently eh return introduces a return to anywhere gadget, no
8602 matter what we do here since it uses ret with user provided
8603 address. An ideal fix for that is to use indirect branch which
8604 can be protected with BTI j (to some extent). */
8608 /* If signing scope is AARCH64_FUNCTION_NON_LEAF, we only sign a leaf function
8609 if its LR is pushed onto stack. */
8613 }
8615 /* Return TRUE if Branch Target Identification Mechanism is enabled. */
8616 bool
8618 {
8620 }
8622 /* The caller is going to use ST1D or LD1D to save or restore an SVE
8623 register in mode MODE at BASE_RTX + OFFSET, where OFFSET is in
8624 the range [1, 16] * GET_MODE_SIZE (MODE). Prepare for this by:
8626 (1) updating BASE_RTX + OFFSET so that it is a legitimate ST1D
8627 or LD1D address
8629 (2) setting PRED to a valid predicate register for the ST1D or LD1D,
8630 if the variable isn't already nonnull
8632 (1) is needed when OFFSET is in the range [8, 16] * GET_MODE_SIZE (MODE).
8633 Handle this case using a temporary base register that is suitable for
8634 all offsets in that range. Use ANCHOR_REG as this base register if it
8635 is nonnull, otherwise create a new register and store it in ANCHOR_REG. */
8641 {
8643 {
8644 /* This is the maximum valid offset of the anchor from the base.
8645 Lower values would be valid too. */
8648 {
8652 }
8655 }
8657 {
8662 }
8663 }
8665 /* Add a REG_CFA_EXPRESSION note to INSN to say that register REG
8666 is saved at BASE + OFFSET. */
8668 static void
8671 {
8675 }
8677 /* Emit code to save the callee-saved registers from register number START
8678 to LIMIT to the stack at the location starting at offset START_OFFSET,
8679 skipping any write-back candidates if SKIP_WB is true. HARD_FP_VALID_P
8680 is true if the hard frame pointer has been set up. */
8682 static void
8686 {
8695 {
8697 poly_int64 offset;
8714 HOST_WIDE_INT const_offset;
8720 {
8722 poly_int64 fp_offset
8726 else
8727 {
8729 {
8733 }
8735 }
8737 }
8747 {
8749 rtx mem2;
8754 reg2));
8756 /* The first part of a frame-related parallel insn is
8757 always assumed to be relevant to the frame
8758 calculations; subsequent parts, are only
8759 frame-related if explicitly marked. */
8761 {
8765 else
8767 }
8770 }
8772 {
8775 }
8778 else
8784 }
8785 }
8787 /* Emit code to restore the callee registers from register number START
8788 up to and including LIMIT. Restore from the stack offset START_OFFSET,
8789 skipping any write-back candidates if SKIP_WB is true. Write the
8790 appropriate REG_CFA_RESTORE notes into CFI_OPS. */
8792 static void
8795 {
8798 poly_int64 offset;
8804 {
8831 {
8833 rtx mem2;
8841 }
8846 else
8850 }
8851 }
8853 /* Return true if OFFSET is a signed 4-bit value multiplied by the size
8854 of MODE. */
8858 {
8859 HOST_WIDE_INT multiple;
8862 }
8864 /* Return true if OFFSET is a signed 6-bit value multiplied by the size
8865 of MODE. */
8869 {
8870 HOST_WIDE_INT multiple;
8873 }
8875 /* Return true if OFFSET is an unsigned 6-bit value multiplied by the size
8876 of MODE. */
8880 {
8881 HOST_WIDE_INT multiple;
8884 }
8886 /* Return true if OFFSET is a signed 7-bit value multiplied by the size
8887 of MODE. */
8889 bool
8891 {
8892 HOST_WIDE_INT multiple;
8895 }
8897 /* Return true if OFFSET is a signed 9-bit value. */
8899 bool
8901 poly_int64 offset)
8902 {
8903 HOST_WIDE_INT const_offset;
8906 }
8908 /* Return true if OFFSET is a signed 9-bit value multiplied by the size
8909 of MODE. */
8913 {
8914 HOST_WIDE_INT multiple;
8917 }
8919 /* Return true if OFFSET is an unsigned 12-bit value multiplied by the size
8920 of MODE. */
8924 {
8925 HOST_WIDE_INT multiple;
8928 }
8930 /* Implement TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS. */
8932 static sbitmap
8934 {
8938 /* The registers we need saved to the frame. */
8941 {
8942 /* Punt on saves and restores that use ST1D and LD1D. We could
8943 try to be smarter, but it would involve making sure that the
8944 spare predicate register itself is safe to use at the save
8945 and restore points. Also, when a frame pointer is being used,
8946 the slots are often out of reach of ST1D and LD1D anyway. */
8953 /* If the register is saved in the first SVE save slot, we use
8954 it as a stack probe for -fstack-clash-protection. */
8960 /* Get the offset relative to the register we'll use. */
8963 else
8966 /* Check that we can access the stack slot of the register with one
8967 direct load with no adjustments needed. */
8972 }
8974 /* Don't mess with the hard frame pointer. */
8978 /* If the spare predicate register used by big-endian SVE code
8979 is call-preserved, it must be saved in the main prologue
8980 before any saves that use it. */
8986 /* If registers have been chosen to be stored/restored with
8987 writeback don't interfere with them to avoid having to output explicit
8988 stack adjustment instructions. */
8998 }
9000 /* Implement TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB. */
9002 static sbitmap
9004 {
9012 /* Clobbered registers don't generate values in any meaningful sense,
9013 since nothing after the clobber can rely on their value. And we can't
9014 say that partially-clobbered registers are unconditionally killed,
9015 because whether they're killed or not depends on the mode of the
9016 value they're holding. Thus partially call-clobbered registers
9017 appear in neither the kill set nor the gen set.
9019 Check manually for any calls that clobber more of a register than the
9020 current function can. */
9021 function_abi_aggregator callee_abis;
9028 /* GPRs are used in a bb if they are in the IN, GEN, or KILL sets. */
9036 {
9039 /* If there is a callee-save at an adjacent offset, add it too
9040 to increase the use of LDP/STP. */
9045 {
9051 }
9052 }
9055 }
9057 /* Implement TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS.
9058 Nothing to do for aarch64. */
9060 static void
9062 {
9063 }
9065 /* Return the next set bit in BMP from START onwards. Return the total number
9066 of bits in BMP if no set bit is found at or after START. */
9068 static unsigned int
9070 {
9081 }
9083 /* Do the work for aarch64_emit_prologue_components and
9084 aarch64_emit_epilogue_components. COMPONENTS is the bitmap of registers
9085 to save/restore, PROLOGUE_P indicates whether to emit the prologue sequence
9086 for these components or the epilogue sequence. That is, it determines
9087 whether we should emit stores or loads and what kind of CFA notes to attach
9088 to the insns. Otherwise the logic for the two sequences is very
9089 similar. */
9091 static void
9093 {
9095 ? HARD_FRAME_POINTER_REGNUM
9103 {
9111 else
9119 /* No more registers to handle after REGNO.
9120 Emit a single save/restore and exit. */
9122 {
9125 {
9129 else
9131 }
9133 }
9136 /* The next register is not of the same class or its offset is not
9137 mergeable with the current one into a pair. */
9144 {
9147 {
9151 else
9153 }
9157 }
9161 /* REGNO2 can be saved/restored in a pair with REGNO. */
9165 else
9174 else
9178 {
9181 {
9186 }
9187 else
9188 {
9193 }
9194 }
9197 }
9198 }
9200 /* Implement TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS. */
9202 static void
9204 {
9206 }
9208 /* Implement TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS. */
9210 static void
9212 {
9214 }
9216 /* Implement TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS. */
9218 static void
9220 {
9224 }
9226 /* On AArch64 we have an ABI defined safe buffer. This constant is used to
9227 determining the probe offset for alloca. */
9229 static HOST_WIDE_INT
9231 {
9233 }
9236 /* Allocate POLY_SIZE bytes of stack space using TEMP1 and TEMP2 as scratch
9237 registers. If POLY_SIZE is not large enough to require a probe this function
9238 will only adjust the stack. When allocating the stack space
9239 FRAME_RELATED_P is then used to indicate if the allocation is frame related.
9240 FINAL_ADJUSTMENT_P indicates whether we are allocating the outgoing
9241 arguments. If we are then we ensure that any allocation larger than the ABI
9242 defined buffer needs a probe so that the invariant of having a 1KB buffer is
9243 maintained.
9245 We emit barriers after each stack adjustment to prevent optimizations from
9246 breaking the invariant that we never drop the stack more than a page. This
9247 invariant is needed to make it easier to correctly handle asynchronous
9248 events, e.g. if we were to allow the stack to be dropped by more than a page
9249 and then have multiple probes up and we take a signal somewhere in between
9250 then the signal handler doesn't know the state of the stack and can make no
9251 assumptions about which pages have been probed. */
9253 static void
9255 poly_int64 poly_size,
9258 {
9259 HOST_WIDE_INT guard_size
9262 HOST_WIDE_INT min_probe_threshold
9263 = (final_adjustment_p
9264 ? guard_used_by_caller
9266 /* When doing the final adjustment for the outgoing arguments, take into
9267 account any unprobed space there is above the current SP. There are
9268 two cases:
9270 - When saving SVE registers below the hard frame pointer, we force
9271 the lowest save to take place in the prologue before doing the final
9272 adjustment (i.e. we don't allow the save to be shrink-wrapped).
9273 This acts as a probe at SP, so there is no unprobed space.
9275 - When there are no SVE register saves, we use the store of the link
9276 register as a probe. We can't assume that LR was saved at position 0
9277 though, so treat any space below it as unprobed. */
9280 {
9284 else
9286 }
9290 /* We should always have a positive probe threshold. */
9294 {
9300 {
9302 }
9306 {
9308 }
9309 }
9311 /* If SIZE is not large enough to require probing, just adjust the stack and
9312 exit. */
9315 {
9318 }
9320 HOST_WIDE_INT size;
9321 /* Handle the SVE non-constant case first. */
9323 {
9325 {
9329 }
9331 /* First calculate the amount of bytes we're actually spilling. */
9338 {
9339 /* This is done to provide unwinding information for the stack
9340 adjustments we're about to do, however to prevent the optimizers
9341 from removing the R11 move and leaving the CFA note (which would be
9342 very wrong) we tie the old and new stack pointer together.
9343 The tie will expand to nothing but the optimizers will not touch
9344 the instruction. */
9349 /* We want the CFA independent of the stack pointer for the
9350 duration of the loop. */
9353 }
9362 /* Now reset the CFA register if needed. */
9364 {
9369 }
9372 }
9376 "Stack clash AArch64 prologue: " HOST_WIDE_INT_PRINT_DEC
9379 /* Round size to the nearest multiple of guard_size, and calculate the
9380 residual as the difference between the original size and the rounded
9381 size. */
9385 /* We can handle a small number of allocations/probes inline. Otherwise
9386 punt to a loop. */
9388 {
9390 {
9393 guard_used_by_caller));
9395 }
9397 }
9398 else
9399 {
9400 /* Compute the ending address. */
9405 /* For the initial allocation, we don't have a frame pointer
9406 set up, so we always need CFI notes. If we're doing the
9407 final allocation, then we may have a frame pointer, in which
9408 case it is the CFA, otherwise we need CFI notes.
9410 We can determine which allocation we are doing by looking at
9411 the value of FRAME_RELATED_P since the final allocations are not
9412 frame related. */
9414 {
9415 /* We want the CFA independent of the stack pointer for the
9416 duration of the loop. */
9420 }
9422 /* This allocates and probes the stack. Note that this re-uses some of
9423 the existing Ada stack protection code. However we are guaranteed not
9424 to enter the non loop or residual branches of that code.
9426 The non-loop part won't be entered because if our allocation amount
9427 doesn't require a loop, the case above would handle it.
9429 The residual amount won't be entered because TEMP1 is a mutliple of
9430 the allocation size. The residual will always be 0. As such, the only
9431 part we are actually using from that code is the loop setup. The
9432 actual probing is done in aarch64_output_probe_stack_range. */
9436 /* Now reset the CFA register if needed. */
9438 {
9442 }
9446 }
9448 /* Handle any residuals. Residuals of at least MIN_PROBE_THRESHOLD have to
9449 be probed. This maintains the requirement that each page is probed at
9450 least once. For initial probing we probe only if the allocation is
9451 more than GUARD_SIZE - buffer, and for the outgoing arguments we probe
9452 if the amount is larger than buffer. GUARD_SIZE - buffer + buffer ==
9453 GUARD_SIZE. This works that for any allocation that is large enough to
9454 trigger a probe here, we'll have at least one, and if they're not large
9455 enough for this code to emit anything for them, The page would have been
9456 probed by the saving of FP/LR either by this function or any callees. If
9457 we don't have any callees then we won't have more stack adjustments and so
9458 are still safe. */
9460 {
9462 /* If we're doing final adjustments, and we've done any full page
9463 allocations then any residual needs to be probed. */
9466 /* If doing a small final adjustment, we always probe at offset 0.
9467 This is done to avoid issues when LR is not at position 0 or when
9468 the final adjustment is smaller than the probing offset. */
9474 {
9477 "Stack clash AArch64 prologue residuals: "
9478 HOST_WIDE_INT_PRINT_DEC " bytes, probing will be required."
9482 residual_probe_offset));
9484 }
9485 }
9486 }
9488 /* Return 1 if the register is used by the epilogue. We need to say the
9489 return register is used, but only after epilogue generation is complete.
9490 Note that in the case of sibcalls, the values "used by the epilogue" are
9491 considered live at the start of the called function.
9493 For SIMD functions we need to return 1 for FP registers that are saved and
9494 restored by a function but are not zero in call_used_regs. If we do not do
9495 this optimizations may remove the restore of the register. */
9497 int
9499 {
9501 {
9504 }
9506 }
9508 /* AArch64 stack frames generated by this compiler look like:
9510 +-------------------------------+
9511 | |
9512 | incoming stack arguments |
9513 | |
9514 +-------------------------------+
9515 | | <-- incoming stack pointer (aligned)
9516 | callee-allocated save area |
9517 | for register varargs |
9518 | |
9519 +-------------------------------+
9520 | local variables | <-- frame_pointer_rtx
9521 | |
9522 +-------------------------------+
9523 | padding | \
9524 +-------------------------------+ |
9525 | callee-saved registers | | frame.saved_regs_size
9526 +-------------------------------+ |
9527 | LR' | |
9528 +-------------------------------+ |
9529 | FP' | |
9530 +-------------------------------+ |<- hard_frame_pointer_rtx (aligned)
9531 | SVE vector registers | | \
9532 +-------------------------------+ | | below_hard_fp_saved_regs_size
9533 | SVE predicate registers | / /
9534 +-------------------------------+
9535 | dynamic allocation |
9536 +-------------------------------+
9537 | padding |
9538 +-------------------------------+
9539 | outgoing stack arguments | <-- arg_pointer
9540 | |
9541 +-------------------------------+
9542 | | <-- stack_pointer_rtx (aligned)
9544 Dynamic stack allocations via alloca() decrease stack_pointer_rtx
9545 but leave frame_pointer_rtx and hard_frame_pointer_rtx
9546 unchanged.
9548 By default for stack-clash we assume the guard is at least 64KB, but this
9549 value is configurable to either 4KB or 64KB. We also force the guard size to
9550 be the same as the probing interval and both values are kept in sync.
9552 With those assumptions the callee can allocate up to 63KB (or 3KB depending
9553 on the guard size) of stack space without probing.
9555 When probing is needed, we emit a probe at the start of the prologue
9556 and every PARAM_STACK_CLASH_PROTECTION_GUARD_SIZE bytes thereafter.
9558 We have to track how much space has been allocated and the only stores
9559 to the stack we track as implicit probes are the FP/LR stores.
9561 For outgoing arguments we probe if the size is larger than 1KB, such that
9562 the ABI specified buffer is maintained for the next callee.
9564 The following registers are reserved during frame layout and should not be
9565 used for any other purpose:
9567 - r11: Used by stack clash protection when SVE is enabled, and also
9568 as an anchor register when saving and restoring registers
9569 - r12(EP0) and r13(EP1): Used as temporaries for stack adjustment.
9570 - r14 and r15: Used for speculation tracking.
9571 - r16(IP0), r17(IP1): Used by indirect tailcalls.
9572 - r30(LR), r29(FP): Used by standard frame layout.
9574 These registers must be avoided in frame layout related code unless the
9575 explicit intention is to interact with one of the features listed above. */
9577 /* Generate the prologue instructions for entry into a function.
9578 Establish the stack frame by decreasing the stack pointer with a
9579 properly calculated size and, if necessary, create a frame record
9580 filled with the values of LR and previous frame pointer. The
9581 current FP is also set up if it is in use. */
9583 void
9585 {
9592 poly_int64 below_hard_fp_saved_regs_size
9600 {
9601 /* Fold the SVE allocation into the initial allocation.
9602 We don't do this in aarch64_layout_arg to avoid pessimizing
9603 the epilogue code. */
9606 }
9608 /* Sign return address for functions. */
9610 {
9612 {
9621 }
9624 }
9626 /* Push return address to shadow call stack. */
9634 {
9636 {
9640 (frame_size
9642 }
9645 }
9650 /* In theory we should never have both an initial adjustment
9651 and a callee save adjustment. Verify that is the case since the
9652 code below does not handle it for -fstack-clash-protection. */
9655 /* Will only probe if the initial adjustment is larger than the guard
9656 less the amount of the guard reserved for use by the caller's
9657 outgoing args. */
9664 /* The offset of the frame chain record (if any) from the current SP. */
9669 /* The offset of the bottom of the save area from the current SP. */
9673 {
9675 {
9680 }
9681 else
9687 {
9688 /* Variable-sized frames need to describe the save slot
9689 address using DW_CFA_expression rather than DW_CFA_offset.
9690 This means that, without taking further action, the
9691 locations of the registers that we've already saved would
9692 remain based on the stack pointer even after we redefine
9693 the CFA based on the frame pointer. We therefore need new
9694 DW_CFA_expressions to re-express the save slots with addresses
9695 based on the frame pointer. */
9699 /* Add an explicit CFA definition if this was previously
9700 implicit. */
9702 {
9704 callee_offset);
9707 }
9709 /* Change the save slot expressions for the registers that
9710 we've already saved. */
9715 }
9717 }
9721 emit_frame_chain);
9723 {
9727 sve_callee_adjust,
9730 }
9735 emit_frame_chain);
9737 /* We may need to probe the final adjustment if it is larger than the guard
9738 that is assumed by the called. */
9741 }
9743 /* Return TRUE if we can use a simple_return insn.
9745 This function checks whether the callee saved stack is empty, which
9746 means no restore actions are need. The pro_and_epilogue will use
9747 this to check whether shrink-wrapping opt is feasible. */
9749 bool
9751 {
9759 }
9761 /* Generate the epilogue instructions for returning from a function.
9762 This is almost exactly the reverse of the prolog sequence, except
9763 that we need to insert barriers to avoid scheduling loads that read
9764 from a deallocated stack, and we optimize the unwind records by
9765 emitting them all together if possible. */
9766 void
9768 {
9774 poly_int64 below_hard_fp_saved_regs_size
9782 /* A stack clash protection prologue may not have left EP0_REGNUM or
9783 EP1_REGNUM in a usable state. The same is true for allocations
9784 with an SVE component, since we then need both temporary registers
9785 for each allocation. For stack clash we are in a usable state if
9786 the adjustment is less than GUARD_SIZE - GUARD_USED_BY_CALLER. */
9787 HOST_WIDE_INT guard_size
9791 /* We can re-use the registers when:
9793 (a) the deallocation amount is the same as the corresponding
9794 allocation amount (which is false if we combine the initial
9795 and SVE callee save allocations in the prologue); and
9797 (b) the allocation amount doesn't need a probe (which is false
9798 if the amount is guard_size - guard_used_by_caller or greater).
9800 In such situations the register should remain live with the correct
9801 value. */
9804 && (!flag_stack_clash_protection
9809 /* We need to add memory barrier to prevent read from deallocated stack. */
9810 bool need_barrier_p
9814 /* Emit a barrier to prevent loads from a deallocated stack. */
9818 {
9821 }
9823 /* Restore the stack pointer from the frame pointer if it may not
9824 be the same as the stack pointer. */
9829 /* If writeback is used when restoring callee-saves, the CFA
9830 is restored on the instruction doing the writeback. */
9832 hard_frame_pointer_rtx,
9835 else
9836 /* The case where we need to re-use the register here is very rare, so
9837 avoid the complicated condition and just always emit a move if the
9838 immediate doesn't fit. */
9841 /* Restore the vector registers before the predicate registers,
9842 so that we can use P4 as a temporary for big-endian SVE frames. */
9850 /* When shadow call stack is enabled, the scs_pop in the epilogue will
9851 restore x30, we don't need to restore x30 again in the traditional
9852 way. */
9863 /* If we have no register restore information, the CFA must have been
9864 defined in terms of the stack pointer since the end of the prologue. */
9868 {
9869 /* Emit delayed restores and set the CFA to be SP + initial_adjust. */
9875 }
9877 /* Liveness of EP0_REGNUM can not be trusted across function calls either, so
9878 add restriction on emit_move optimization to leaf functions. */
9884 {
9885 /* Emit delayed restores and reset the CFA to be SP. */
9890 }
9892 /* Pop return address from shadow call stack. */
9894 {
9901 }
9903 /* We prefer to emit the combined return/authenticate instruction RETAA,
9904 however there are three cases in which we must instead emit an explicit
9905 authentication instruction.
9907 1) Sibcalls don't return in a normal way, so if we're about to call one
9908 we must authenticate.
9910 2) The RETAA instruction is not available before ARMv8.3-A, so if we are
9911 generating code for !TARGET_ARMV8_3 we can't use it and must
9912 explicitly authenticate.
9913 */
9916 {
9918 {
9927 }
9930 }
9932 /* Stack adjustment for exception handler. */
9934 {
9935 /* We need to unwind the stack by the offset computed by
9936 EH_RETURN_STACKADJ_RTX. We have already reset the CFA
9937 to be SP; letting the CFA move during this adjustment
9938 is just as correct as retaining the CFA from the body
9939 of the function. Therefore, do nothing special. */
9941 }
9946 }
9948 /* Implement EH_RETURN_HANDLER_RTX. EH returns need to either return
9949 normally or return to a previous frame after unwinding.
9951 An EH return uses a single shared return sequence. The epilogue is
9952 exactly like a normal epilogue except that it has an extra input
9953 register (EH_RETURN_STACKADJ_RTX) which contains the stack adjustment
9954 that must be applied after the frame has been destroyed. An extra label
9955 is inserted before the epilogue which initializes this register to zero,
9956 and this is the entry point for a normal return.
9958 An actual EH return updates the return address, initializes the stack
9959 adjustment and jumps directly into the epilogue (bypassing the zeroing
9960 of the adjustment). Since the return address is typically saved on the
9961 stack when a function makes a call, the saved LR must be updated outside
9962 the epilogue.
9964 This poses problems as the store is generated well before the epilogue,
9965 so the offset of LR is not known yet. Also optimizations will remove the
9966 store as it appears dead, even after the epilogue is generated (as the
9967 base or offset for loading LR is different in many cases).
9969 To avoid these problems this implementation forces the frame pointer
9970 in eh_return functions so that the location of LR is fixed and known early.
9971 It also marks the store volatile, so no optimization is permitted to
9972 remove the store. */
9973 rtx
9975 {
9979 /* Mark the store volatile, so no optimization is permitted to remove it. */
9982 }
9984 /* Output code to add DELTA to the first argument, and then jump
9985 to FUNCTION. Used for C++ multiple inheritance. */
9986 static void
9988 HOST_WIDE_INT delta,
9989 HOST_WIDE_INT vcall_offset,
9990 tree function)
9991 {
9992 /* The this pointer is always in x0. Note that this differs from
9993 Arm where the this pointer maybe bumped to r1 if r0 is required
9994 to return a pointer to an aggregate. On AArch64 a result value
9995 pointer will be in x8. */
10013 else
10014 {
10019 {
10023 else
10026 }
10030 else
10037 else
10038 {
10040 Pmode);
10042 }
10046 else
10052 }
10054 /* Generate a tail call to the target function. */
10056 {
10059 }
10075 /* Stop pretending to be a post-reload pass. */
10077 }
10079 static bool
10081 {
10086 {
10090 /* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
10091 TLS offsets, not real symbol references. */
10094 }
10096 }
10099 /* Return true if val can be encoded as a 12-bit unsigned immediate with
10100 a left shift of 0 or 12 bits. */
10101 bool
10103 {
10106 );
10107 }
10109 /* Returns the nearest value to VAL that will fit as a 12-bit unsigned immediate
10110 that can be created with a left shift of 0 or 12. */
10111 static HOST_WIDE_INT
10113 {
10114 /* Check to see if the value fits in 24 bits, as that is the maximum we can
10115 handle correctly. */
10122 }
10124 /* Return true if val is an immediate that can be loaded into a
10125 register by a MOVZ instruction. */
10126 static bool
10128 {
10130 {
10134 }
10135 else
10136 {
10137 /* Ignore sign extension. */
10139 }
10142 }
10144 /* Test whether:
10146 X = (X & AND_VAL) | IOR_VAL;
10148 can be implemented using:
10150 MOVK X, #(IOR_VAL >> shift), LSL #shift
10152 Return the shift if so, otherwise return -1. */
10153 int
10156 {
10160 {
10164 }
10166 }
10168 /* VAL is a value with the inner mode of MODE. Replicate it to fill a
10169 64-bit (DImode) integer. */
10171 static unsigned HOST_WIDE_INT
10173 {
10176 {
10180 }
10182 }
10184 /* Multipliers for repeating bitmasks of width 32, 16, 8, 4, and 2. */
10187 {
10193 };
10196 /* Return true if val is a valid bitmask immediate. */
10198 bool
10200 {
10204 /* Check for a single sequence of one bits and return quickly if so.
10205 The special cases of all ones and all zeroes returns false. */
10212 /* Replicate 32-bit immediates so we can treat them as 64-bit. */
10216 /* Invert if the immediate doesn't start with a zero bit - this means we
10217 only need to search for sequences of one bits. */
10221 /* Find the first set bit and set tmp to val with the first sequence of one
10222 bits removed. Return success if there is a single sequence of ones. */
10229 /* Find the next set bit and compute the difference in bit position. */
10234 /* Check the bit position difference is a power of 2, and that the first
10235 sequence of one bits fits within 'bits' bits. */
10239 /* Check the sequence of one bits is repeated 64/bits times. */
10241 }
10243 /* Create mask of ones, covering the lowest to highest bits set in VAL_IN.
10244 Assumed precondition: VAL_IN Is not zero. */
10246 unsigned HOST_WIDE_INT
10248 {
10255 }
10257 /* Create constant where bits outside of lowest bit set to highest bit set
10258 are set to 1. */
10260 unsigned HOST_WIDE_INT
10262 {
10264 }
10266 /* Return true if VAL_IN is a valid 'and' bitmask immediate. */
10268 bool
10270 {
10271 scalar_int_mode int_mode;
10284 }
10286 /* Return true if val is an immediate that can be loaded into a
10287 register in a single instruction. */
10288 bool
10290 {
10291 scalar_int_mode int_mode;
10298 }
10300 static bool
10302 {
10306 /* There's no way to calculate VL-based values using relocations. */
10312 poly_int64 offset;
10315 {
10316 /* We checked for POLY_INT_CST offsets above. */
10320 else
10321 /* Avoid generating a 64-bit relocation in ILP32; leave
10322 to aarch64_expand_mov_immediate to handle it properly. */
10324 }
10327 }
10329 /* Implement TARGET_CASE_VALUES_THRESHOLD.
10330 The expansion for a table switch is quite expensive due to the number
10331 of instructions, the table lookup and hard to predict indirect jump.
10332 When optimizing for speed, and -O3 enabled, use the per-core tuning if
10333 set, otherwise use tables for >= 11 cases as a tradeoff between size and
10334 performance. When optimizing for size, use 8 for smallest codesize. */
10336 static unsigned int
10338 {
10339 /* Use the specified limit for the number of cases before using jump
10340 tables at higher optimization levels. */
10344 else
10346 }
10348 /* Return true if register REGNO is a valid index register.
10349 STRICT_P is true if REG_OK_STRICT is in effect. */
10351 bool
10353 {
10355 {
10363 }
10365 }
10367 /* Return true if register REGNO is a valid base register for mode MODE.
10368 STRICT_P is true if REG_OK_STRICT is in effect. */
10370 bool
10372 {
10374 {
10382 }
10384 /* The fake registers will be eliminated to either the stack or
10385 hard frame pointer, both of which are usually valid base registers.
10386 Reload deals with the cases where the eliminated form isn't valid. */
10391 }
10393 /* Return true if X is a valid base register for mode MODE.
10394 STRICT_P is true if REG_OK_STRICT is in effect. */
10396 static bool
10398 {
10405 }
10407 /* Return true if address offset is a valid index. If it is, fill in INFO
10408 appropriately. STRICT_P is true if REG_OK_STRICT is in effect. */
10410 static bool
10413 {
10415 rtx index;
10418 /* (reg:P) */
10421 {
10425 }
10426 /* (sign_extend:DI (reg:SI)) */
10431 {
10436 }
10437 /* (mult:DI (sign_extend:DI (reg:SI)) (const_int scale)) */
10444 {
10449 }
10450 /* (ashift:DI (sign_extend:DI (reg:SI)) (const_int shift)) */
10457 {
10462 }
10463 /* (and:DI (mult:DI (reg:DI) (const_int scale))
10464 (const_int 0xffffffff<<shift)) */
10471 {
10477 }
10478 /* (and:DI (ashift:DI (reg:DI) (const_int shift))
10479 (const_int 0xffffffff<<shift)) */
10486 {
10492 }
10493 /* (mult:P (reg:P) (const_int scale)) */
10498 {
10502 }
10503 /* (ashift:P (reg:P) (const_int shift)) */
10508 {
10512 }
10513 else
10522 {
10526 }
10527 else
10528 {
10533 }
10537 {
10542 }
10545 }
10547 /* Return true if MODE is one of the modes for which we
10548 support LDP/STP operations. */
10550 static bool
10552 {
10561 }
10563 /* Return true if REGNO is a virtual pointer register, or an eliminable
10564 "soft" frame register. Like REGNO_PTR_FRAME_P except that we don't
10565 include stack_pointer or hard_frame_pointer. */
10566 static bool
10568 {
10573 }
10575 /* Return true if X is a valid address of type TYPE for machine mode MODE.
10576 If it is, fill in INFO appropriately. STRICT_P is true if
10577 REG_OK_STRICT is in effect. */
10579 bool
10582 aarch64_addr_query_type type)
10583 {
10586 poly_int64 offset;
10588 HOST_WIDE_INT const_size;
10590 /* Whether a vector mode is partial doesn't affect address legitimacy.
10591 Partial vectors like VNx8QImode allow the same indexed addressing
10592 mode and MUL VL addressing mode as full vectors like VNx16QImode;
10593 in both cases, MUL VL counts multiples of GET_MODE_SIZE. */
10597 /* On BE, we use load/store pair for all large int mode load/stores.
10598 TI/TF/TDmode may also use a load/store pair. */
10606 /* If we are dealing with ADDR_QUERY_LDP_STP_N that means the incoming mode
10607 corresponds to the actual size of the memory being loaded/stored and the
10608 mode of the corresponding addressing mode is half of that. */
10610 {
10615 else
10617 }
10625 /* For SVE, only accept [Rn], [Rn, #offset, MUL VL] and [Rn, Rm, LSL #shift].
10626 The latter is not valid for SVE predicates, and that's rejected through
10627 allow_reg_index_p above. */
10632 /* On LE, for AdvSIMD, don't support anything other than POST_INC or
10633 REG addressing. */
10635 && !BYTES_BIG_ENDIAN
10643 {
10660 {
10667 }
10672 {
10678 /* TImode, TFmode and TDmode values are allowed in both pairs of X
10679 registers and individual Q registers. The available
10680 address modes are:
10681 X,X: 7-bit signed scaled offset
10682 Q: 9-bit signed offset
10683 We conservatively require an offset representable in either mode.
10684 When performing the check for pairs of X registers i.e. LDP/STP
10685 pass down DImode since that is the natural size of the LDP/STP
10686 instruction memory accesses. */
10696 /* A 7bit offset check because OImode will emit a ldp/stp
10697 instruction (only big endian will get here).
10698 For ldp/stp instructions, the offset is scaled for the size of a
10699 single element of the pair. */
10707 /* Three 9/12 bit offsets checks because CImode will emit three
10708 ldr/str instructions (only big endian will get here). */
10724 /* Two 7bit offsets checks because XImode will emit two ldp/stp
10725 instructions (only big endian will get here). */
10737 /* Make "m" use the LD1 offset range for SVE data modes, so
10738 that pre-RTL optimizers like ivopts will work to that
10739 instead of the wider LDR/STR range. */
10746 {
10747 poly_int64 end_offset = (offset
10754 end_offset)));
10755 }
10765 else
10768 }
10771 {
10772 /* Look for base + (scaled/extended) index register. */
10775 {
10778 }
10781 {
10784 }
10785 }
10806 {
10810 /* TImode, TFmode and TDmode values are allowed in both pairs of X
10811 registers and individual Q registers. The available
10812 address modes are:
10813 X,X: 7-bit signed scaled offset
10814 Q: 9-bit signed offset
10815 We conservatively require an offset representable in either mode.
10816 */
10826 else
10828 }
10834 /* load literal: pc-relative constant pool entry. Only supported
10835 for SI mode or larger. */
10841 {
10842 poly_int64 offset;
10848 }
10857 {
10858 poly_int64 offset;
10859 HOST_WIDE_INT const_offset;
10865 {
10866 /* The symbol and offset must be aligned to the access size. */
10872 {
10876 }
10882 else
10891 }
10892 }
10897 }
10898 }
10900 /* Return true if the address X is valid for a PRFM instruction.
10901 STRICT_P is true if we should do strict checking with
10902 aarch64_classify_address. */
10904 bool
10906 {
10909 /* PRFM accepts the same addresses as DImode... */
10914 /* ... except writeback forms. */
10916 }
10918 bool
10920 {
10921 poly_int64 offset;
10924 }
10926 /* Classify the base of symbolic expression X. */
10928 enum aarch64_symbol_type
10930 {
10931 rtx offset;
10935 }
10938 /* Return TRUE if X is a legitimate address for accessing memory in
10939 mode MODE. */
10940 static bool
10942 {
10946 }
10948 /* Return TRUE if X is a legitimate address of type TYPE for accessing
10949 memory in mode MODE. STRICT_P is true if REG_OK_STRICT is in effect. */
10950 bool
10952 aarch64_addr_query_type type)
10953 {
10957 }
10959 /* Implement TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT. */
10961 static bool
10963 poly_int64 orig_offset,
10964 machine_mode mode)
10965 {
10966 HOST_WIDE_INT size;
10968 {
10971 /* A general SVE offset is A * VQ + B. Remove the A component from
10972 coefficient 0 in order to get the constant B. */
10975 /* Split an out-of-range address displacement into a base and
10976 offset. Use 4KB range for 1- and 2-byte accesses and a 16KB
10977 range otherwise to increase opportunities for sharing the base
10978 address of different sizes. Unaligned accesses use the signed
10979 9-bit range, TImode/TFmode/TDmode use the intersection of signed
10980 scaled 7-bit and signed 9-bit offset. */
10985 else
10991 /* Split the offset into second_offset and the rest. */
10995 }
10996 else
10997 {
10998 /* Get the mode we should use as the basis of the range. For structure
10999 modes this is the mode of one vector. */
11001 machine_mode step_mode
11004 /* Get the "mul vl" multiplier we'd like to use. */
11008 /* LDR supports a 9-bit range, but the move patterns for
11009 structure modes require all vectors to be in range of the
11010 same base. The simplest way of accomodating that while still
11011 promoting reuse of anchor points between different modes is
11012 to use an 8-bit range unconditionally. */
11014 else
11015 /* Predicates are only handled singly, so we might as well use
11016 the full range. */
11021 /* Convert the "mul vl" multiplier into a byte offset. */
11026 /* Split the offset into second_offset and the rest. */
11030 }
11031 }
11033 /* Return the binary representation of floating point constant VALUE in INTVAL.
11034 If the value cannot be converted, return false without setting INTVAL.
11035 The conversion is done in the given MODE. */
11036 bool
11038 {
11040 /* We make a general exception for 0. */
11042 {
11045 }
11047 scalar_float_mode mode;
11051 /* Only support up to DF mode. */
11063 {
11067 }
11068 else
11073 }
11075 /* Return TRUE if rtx X is an immediate constant that can be moved using a
11076 single MOV(+MOVK) followed by an FMOV. */
11077 bool
11079 {
11084 /* Determine whether it's cheaper to write float constants as
11085 mov/movk pairs over ldr/adrp pairs. */
11091 {
11093 ? SImode
11098 }
11101 }
11103 /* Return TRUE if rtx X is immediate constant 0.0 (but not in Decimal
11104 Floating Point). */
11105 bool
11107 {
11108 /* 0.0 in Decimal Floating Point cannot be represented by #0 or
11109 zr as our callers expect, so no need to check the actual
11110 value if X is of Decimal Floating Point type. */
11117 }
11119 /* Return TRUE if rtx X is immediate constant that fits in a single
11120 MOVI immediate operation. */
11121 bool
11123 {
11127 machine_mode vmode;
11128 scalar_int_mode imode;
11133 {
11137 /* We make a general exception for 0. */
11142 }
11146 else
11149 /* use a 64 bit mode for everything except for DI/DF/DD mode, where we use
11150 a 128 bit vector mode. */
11157 }
11160 /* Return the fixed registers used for condition codes. */
11162 static bool
11164 {
11168 }
11170 /* This function is used by the call expanders of the machine description.
11171 RESULT is the register in which the result is returned. It's NULL for
11172 "call" and "sibcall".
11173 MEM is the location of the function call.
11174 CALLEE_ABI is a const_int that gives the arm_pcs of the callee.
11175 SIBCALL indicates whether this function call is normal call or sibling call.
11176 It will generate different pattern accordingly. */
11178 void
11180 {
11182 rtvec vec;
11183 machine_mode mode;
11190 /* Decide if we should generate indirect calls by loading the
11191 address of the callee into a register before performing
11192 the branch-and-link. */
11206 else
11211 UNSPEC_CALLEE_ABI);
11217 }
11219 /* Emit call insn with PAT and do aarch64-specific handling. */
11221 void
11223 {
11229 }
11231 machine_mode
11233 {
11237 /* All floating point compares return CCFP if it is an equality
11238 comparison, and CCFPE otherwise. */
11240 {
11242 {
11263 }
11264 }
11266 /* Equality comparisons of short modes against zero can be performed
11267 using the TST instruction with the appropriate bitmask. */
11273 /* Similarly, comparisons of zero_extends from shorter modes can
11274 be performed using an ANDS with an immediate mask. */
11290 /* A compare with a shifted operand. Because of canonicalization,
11291 the comparison will have to be swapped when we emit the assembly
11292 code. */
11300 /* Similarly for a negated operand, but we can only do this for
11301 equalities. */
11308 /* A test for unsigned overflow from an addition. */
11315 /* A test for unsigned overflow from an add with carry. */
11325 /* A test for signed overflow. */
11332 /* For everything else, return CCmode. */
11334 }
11336 static int
11339 int
11341 {
11348 }
11350 static int
11352 {
11354 {
11358 {
11372 }
11377 {
11389 }
11394 {
11406 }
11411 {
11421 }
11426 {
11432 }
11437 {
11441 }
11446 {
11450 }
11455 {
11459 }
11464 {
11468 }
11473 }
11476 }
11478 bool
11480 HOST_WIDE_INT minval,
11481 HOST_WIDE_INT maxval)
11482 {
11483 rtx elt;
11487 }
11489 bool
11491 {
11493 }
11495 /* Return true if VEC is a constant in which every element is in the range
11496 [MINVAL, MAXVAL]. The elements do not need to have the same value. */
11498 static bool
11500 HOST_WIDE_INT minval,
11501 HOST_WIDE_INT maxval)
11502 {
11514 {
11519 }
11521 }
11523 /* N Z C V. */
11524 #define AARCH64_CC_V 1
11525 #define AARCH64_CC_C (1 << 1)
11526 #define AARCH64_CC_Z (1 << 2)
11527 #define AARCH64_CC_N (1 << 3)
11529 /* N Z C V flags for ccmp. Indexed by AARCH64_COND_CODE. */
11531 {
11548 };
11550 /* Print floating-point vector immediate operand X to F, negating it
11551 first if NEGATE is true. Return true on success, false if it isn't
11552 a constant we can handle. */
11554 static bool
11556 {
11557 rtx elt;
11566 /* Handle the SVE single-bit immediates specially, since they have a
11567 fixed form in the assembly syntax. */
11576 else
11577 {
11583 }
11586 }
11588 /* Return the equivalent letter for size. */
11589 static char
11591 {
11593 {
11599 }
11600 }
11602 /* Print operand X to file F in a target specific manner according to CODE.
11603 The acceptable formatting commands given by CODE are:
11604 'c': An integer or symbol address without a preceding #
11605 sign.
11606 'C': Take the duplicated element in a vector constant
11607 and print it in hex.
11608 'D': Take the duplicated element in a vector constant
11609 and print it as an unsigned integer, in decimal.
11610 'e': Print the sign/zero-extend size as a character 8->b,
11611 16->h, 32->w. Can also be used for masks:
11612 0xff->b, 0xffff->h, 0xffffffff->w.
11613 'I': If the operand is a duplicated vector constant,
11614 replace it with the duplicated scalar. If the
11615 operand is then a floating-point constant, replace
11616 it with the integer bit representation. Print the
11617 transformed constant as a signed decimal number.
11618 'p': Prints N such that 2^N == X (X must be power of 2 and
11619 const int).
11620 'P': Print the number of non-zero bits in X (a const_int).
11621 'H': Print the higher numbered register of a pair (TImode)
11622 of regs.
11623 'm': Print a condition (eq, ne, etc).
11624 'M': Same as 'm', but invert condition.
11625 'N': Take the duplicated element in a vector constant
11626 and print the negative of it in decimal.
11627 'b/h/s/d/q': Print a scalar FP/SIMD register name.
11628 'S/T/U/V': Print a FP/SIMD register name for a register list.
11629 The register printed is the FP/SIMD register name
11630 of X + 0/1/2/3 for S/T/U/V.
11631 'R': Print a scalar Integer/FP/SIMD register name + 1.
11632 'X': Print bottom 16 bits of integer constant in hex.
11633 'w/x': Print a general register name or the zero register
11634 (32-bit or 64-bit).
11635 '0': Print a normal operand, if it's a general register,
11636 then we assume DImode.
11637 'k': Print NZCV for conditional compare instructions.
11638 'A': Output address constant representing the first
11639 argument of X, specifying a relocation offset
11640 if appropriate.
11641 'L': Output constant address specified by X
11642 with a relocation offset if appropriate.
11643 'G': Prints address of X, specifying a PC relative
11644 relocation mode if appropriate.
11645 'y': Output address of LDP or STP - this is used for
11646 some LDP/STPs which don't use a PARALLEL in their
11647 pattern (so the mode needs to be adjusted).
11648 'z': Output address of a typical LDP or STP. */
11650 static void
11652 {
11653 rtx elt;
11655 {
11659 else
11660 {
11661 poly_int64 offset;
11665 else
11667 }
11671 {
11674 {
11677 }
11686 else
11687 {
11690 }
11691 }
11695 {
11699 {
11702 }
11705 }
11710 {
11713 }
11720 {
11723 }
11726 {
11729 }
11735 {
11739 else
11740 {
11743 }
11745 }
11749 {
11751 /* CONST_TRUE_RTX means al/nv (al is the default, don't print it). */
11753 {
11757 }
11760 {
11763 }
11771 else
11773 }
11778 {
11781 }
11787 ;
11788 else
11789 {
11792 }
11801 {
11802 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
11804 }
11813 {
11814 output_operand_lossage ("incompatible floating point / vector register operand for '%%%c'", code);
11816 }
11830 else
11832 code);
11837 {
11840 }
11845 {
11846 /* Print a replicated constant in hex. */
11848 {
11851 }
11854 }
11858 {
11859 /* Print a replicated constant in decimal, treating it as
11860 unsigned. */
11862 {
11865 }
11868 }
11875 {
11878 }
11881 {
11884 }
11887 {
11890 }
11892 /* Fall through */
11896 {
11899 }
11902 {
11905 {
11908 else
11909 {
11910 char suffix
11915 }
11916 }
11917 else
11936 {
11939 }
11940 /* fall through */
11944 {
11947 }
11953 ;
11954 else
11955 {
11958 }
11962 /* Since we define TARGET_SUPPORTS_WIDE_INT we shouldn't ever
11963 be getting CONST_DOUBLEs holding integers. */
11966 {
11969 }
11971 {
11972 #define buf_size 20
11980 #undef buf_size
11981 }
11987 }
11995 {
12022 }
12028 {
12063 }
12069 {
12075 }
12080 {
12081 HOST_WIDE_INT cond_code;
12084 {
12087 }
12092 }
12097 {
12104 {
12107 }
12111 ? ADDR_QUERY_LDP_STP_N
12114 }
12120 }
12121 }
12123 /* Print address 'x' of a memory access with mode 'mode'.
12124 'op' is the context required by aarch64_classify_address. It can either be
12125 MEM for a normal memory access or PARALLEL for LDP/STP. */
12126 static bool
12128 aarch64_addr_query_type type)
12129 {
12133 /* Check all addresses are Pmode - including ILP32. */
12137 {
12140 }
12144 {
12147 {
12150 }
12154 {
12155 HOST_WIDE_INT vnum
12161 }
12171 else
12180 else
12189 else
12195 /* Writeback is only supported for fixed-width modes. */
12198 {
12221 }
12233 }
12236 }
12238 /* Print address 'x' of a memory access with mode 'mode'. */
12239 static void
12241 {
12244 }
12246 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */
12248 static bool
12250 {
12252 {
12255 }
12257 }
12259 bool
12261 {
12268 /* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
12269 referencing instruction, but they are constant offsets, not
12270 symbols. */
12276 {
12278 {
12284 }
12287 }
12290 }
12292 /* Implement REGNO_REG_CLASS. */
12294 enum reg_class
12296 {
12321 }
12323 /* OFFSET is an address offset for mode MODE, which has SIZE bytes.
12324 If OFFSET is out of range, return an offset of an anchor point
12325 that is in range. Return 0 otherwise. */
12327 static HOST_WIDE_INT
12329 machine_mode mode)
12330 {
12331 /* Does it look like we'll need a 16-byte load/store-pair operation? */
12335 /* For offsets that aren't a multiple of the access size, the limit is
12336 -256...255. */
12338 {
12339 /* BLKmode typically uses LDP of X-registers. */
12343 }
12345 /* Small negative offsets are supported. */
12352 /* Use 12-bit offset by access size. */
12354 }
12356 static rtx
12358 {
12359 /* Try to split X+CONST into Y=X+(CONST & ~mask), Y+(CONST&mask),
12360 where mask is selected by alignment and size of the offset.
12361 We try to pick as large a range for the offset as possible to
12362 maximize the chance of a CSE. However, for aligned addresses
12363 we limit the range to 4k so that structures with different sized
12364 elements are likely to use the same base. We need to be careful
12365 not to split a CONST for some forms of address expression, otherwise
12366 it will generate sub-optimal code. */
12369 {
12375 {
12379 /* Force any scaling into a temp for CSE. */
12383 /* Let the pointer register be in op0. */
12387 /* If the pointer is virtual or frame related, then we know that
12388 virtual register instantiation or register elimination is going
12389 to apply a second constant. We want the two constants folded
12390 together easily. Therefore, emit as (OP0 + CONST) + OP1. */
12392 {
12396 }
12398 /* Otherwise, in order to encourage CSE (and thence loop strength
12399 reduce) scaled addresses, emit as (OP0 + OP1) + CONST. */
12403 }
12405 HOST_WIDE_INT size;
12407 {
12409 mode);
12411 {
12415 }
12416 }
12417 }
12420 }
12422 static reg_class_t
12424 reg_class_t rclass,
12425 machine_mode mode,
12427 {
12428 /* Use aarch64_sve_reload_mem for SVE memory reloads that cannot use
12429 LDR and STR. See the comment at the head of aarch64-sve.md for
12430 more details about the big-endian handling. */
12435 {
12439 {
12442 }
12443 }
12445 /* If we have to disable direct literal pool loads and stores because the
12446 function is too big, then we need a scratch register. */
12451 {
12454 }
12456 /* Without the TARGET_SIMD instructions we cannot move a Q register
12457 to a Q register directly. We need a scratch. */
12463 {
12466 }
12468 /* A TFmode, TImode or TDmode memory access should be handled via an FP_REGS
12469 because AArch64 has richer addressing modes for LDR/STR instructions
12470 than LDP/STP instructions. */
12481 }
12483 static bool
12485 {
12488 /* If we need a frame pointer, ARG_POINTER_REGNUM and FRAME_POINTER_REGNUM
12489 can only eliminate to HARD_FRAME_POINTER_REGNUM. */
12493 }
12495 poly_int64
12497 {
12499 {
12506 }
12509 {
12513 }
12516 }
12519 /* Get return address without mangling. */
12521 rtx
12523 {
12525 /* Note: aarch64_return_address_signing_enabled only
12526 works after cfun->machine->frame.laid_out is set,
12527 so here we don't know if the return address will
12528 be signed or not. */
12533 }
12536 /* Implement RETURN_ADDR_RTX. We do not support moving back to a
12537 previous frame. */
12539 rtx
12541 {
12545 }
12547 static void
12549 {
12550 /* Even if the current function doesn't have branch protection, some
12551 later function might, so since this template is only generated once
12552 we have to add a BTI just in case. */
12556 {
12559 }
12560 else
12561 {
12564 }
12567 /* We always emit a speculation barrier.
12568 This is because the same trampoline template is used for every nested
12569 function. Since nested functions are not particularly common or
12570 performant we don't worry too much about the extra instructions to copy
12571 around.
12572 This is not yet a problem, since we have not yet implemented function
12573 specific attributes to choose between hardening against straight line
12574 speculation or not, but such function specific attributes are likely to
12575 happen in the future. */
12580 }
12582 static void
12584 {
12588 /* Don't need to copy the trailing D-words, we fill those in below. */
12589 /* We create our own memory address in Pmode so that `emit_block_move` can
12590 use parts of the backend which expect Pmode addresses. */
12604 /* XXX We should really define a "clear_cache" pattern and use
12605 gen_clear_cache(). */
12609 a_tramp,
12610 TRAMPOLINE_SIZE));
12611 }
12613 static unsigned char
12615 {
12616 /* ??? Logically we should only need to provide a value when
12617 HARD_REGNO_MODE_OK says that at least one register in REGCLASS
12618 can hold MODE, but at the moment we need to handle all modes.
12619 Just ignore any runtime parts for registers that can't store them. */
12623 {
12654 }
12656 }
12658 static reg_class_t
12660 {
12665 {
12671 }
12673 /* Register eliminiation can result in a request for
12674 SP+constant->FP_REGS. We cannot support such operations which
12675 use SP as source and an FP_REG as destination, so reject out
12676 right now. */
12678 {
12681 /* Look through a possible SUBREG introduced by ILP32. */
12687 POINTER_REGS));
12689 }
12692 }
12694 void
12696 {
12698 }
12700 static void
12702 {
12705 else
12706 {
12708 /* While priority is known to be in range [0, 65535], so 18 bytes
12709 would be enough, the compiler might not know that. To avoid
12710 -Wformat-truncation false positive, use a larger size. */
12717 }
12718 }
12720 static void
12722 {
12725 else
12726 {
12728 /* While priority is known to be in range [0, 65535], so 18 bytes
12729 would be enough, the compiler might not know that. To avoid
12730 -Wformat-truncation false positive, use a larger size. */
12737 }
12738 }
12742 {
12748 {
12749 {
12752 },
12753 {
12756 },
12757 {
12760 },
12761 /* We assume that DImode is only generated when not optimizing and
12762 that we don't really need 64-bit address offsets. That would
12763 imply an object file with 8GB of code in a single function! */
12764 {
12767 }
12768 };
12777 /* Need to implement table size reduction, by chaning the code below. */
12786 operands);
12789 }
12792 /* Return size in bits of an arithmetic operand which is shifted/scaled and
12793 masked such that it is suitable for a UXTB, UXTH, or UXTW extend
12794 operator. */
12796 int
12798 {
12800 {
12803 {
12807 }
12808 }
12810 }
12812 /* Constant pools are per function only when PC relative
12813 literal loads are true or we are in the large memory
12814 model. */
12818 {
12821 }
12823 static bool
12825 {
12826 /* We can't use blocks for constants when we're using a per-function
12827 constant pool. */
12829 }
12831 /* Select appropriate section for constants depending
12832 on where we place literal pools. */
12836 rtx x,
12838 {
12843 }
12845 /* Implement ASM_OUTPUT_POOL_EPILOGUE. */
12846 void
12848 HOST_WIDE_INT offset)
12849 {
12850 /* When using per-function literal pools, we must ensure that any code
12851 section is aligned to the minimal instruction length, lest we get
12852 errors from the assembler re "unaligned instructions". */
12855 }
12857 /* Costs. */
12859 /* Helper function for rtx cost calculation. Strip a shift expression
12860 from X. Returns the inner operand if successful, or the original
12861 expression on failure. */
12862 static rtx
12864 {
12867 /* We accept both ROTATERT and ROTATE: since the RHS must be a constant
12868 we can convert both to ROR during final output. */
12883 }
12885 /* Helper function for rtx cost calculation. Strip an extend
12886 expression from X. Returns the inner operand if successful, or the
12887 original expression on failure. We deal with a number of possible
12888 canonicalization variations here. If STRIP_SHIFT is true, then
12889 we can strip off a shift also. */
12890 static rtx
12892 {
12893 scalar_int_mode mode;
12907 /* Now handle extended register, as this may also have an optional
12908 left shift by 1..4. */
12923 }
12925 /* Helper function for rtx cost calculation. Strip extension as well as any
12926 inner VEC_SELECT high-half from X. Returns the inner vector operand if
12927 successful, or the original expression on failure. */
12928 static rtx
12930 {
12932 {
12938 }
12940 }
12942 /* Helper function for rtx cost calculation. Strip VEC_DUPLICATE as well as
12943 any subsequent extend and VEC_SELECT from X. Returns the inner scalar
12944 operand if successful, or the original expression on failure. */
12945 static rtx
12947 {
12950 {
12957 }
12959 }
12961 /* Return true iff CODE is a shift supported in combination
12962 with arithmetic instructions. */
12964 static bool
12966 {
12968 }
12971 /* Return true iff X is a cheap shift without a sign extend. */
12973 static bool
12975 {
13001 }
13003 /* Helper function for rtx cost calculation. Calculate the cost of
13004 a MULT or ASHIFT, which may be part of a compound PLUS/MINUS rtx.
13005 Return the calculated cost of the expression, recursing manually in to
13006 operands where needed. */
13008 static int
13010 {
13024 {
13027 {
13028 /* The select-operand-high-half versions of the instruction have the
13029 same cost as the three vector version - don't add the costs of the
13030 extension or selection into the costs of the multiply. */
13033 /* The by-element versions of the instruction have the same costs as
13034 the normal 3-vector version. We make an assumption that the input
13035 to the VEC_DUPLICATE is already on the FP & SIMD side. This means
13036 costing of a MUL by element pre RA is a bit optimistic. */
13039 }
13043 {
13046 /* This is to catch the SSRA costing currently flowing here. */
13047 else
13049 }
13051 }
13053 /* Integer multiply/fma. */
13055 {
13056 /* The multiply will be canonicalized as a shift, cost it as such. */
13060 {
13064 {
13066 {
13067 /* If the shift is considered cheap,
13068 then don't add any cost. */
13070 ;
13072 /* ARITH + shift-by-register. */
13075 /* ARITH + extended register. We don't have a cost field
13076 for ARITH+EXTEND+SHIFT, so use extend_arith here. */
13078 else
13079 /* ARITH + shift-by-immediate. */
13081 }
13082 else
13083 /* LSL (immediate). */
13086 }
13087 /* Strip extends as we will have costed them in the case above. */
13094 }
13096 /* MNEG or [US]MNEGL. Extract the NEG operand and indicate that it's a
13097 compound and let the below cases handle it. After all, MNEG is a
13098 special-case alias of MSUB. */
13100 {
13103 }
13105 /* Integer multiplies or FMAs have zero/sign extending variants. */
13110 {
13115 {
13117 /* SMADDL/UMADDL/UMSUBL/SMSUBL. */
13119 else
13120 /* MUL/SMULL/UMULL. */
13122 }
13125 }
13127 /* This is either an integer multiply or a MADD. In both cases
13128 we want to recurse and cost the operands. */
13133 {
13135 /* MADD/MSUB. */
13137 else
13138 /* MUL. */
13140 }
13143 }
13144 else
13145 {
13147 {
13148 /* Floating-point FMA/FMUL can also support negations of the
13149 operands, unless the rounding mode is upward or downward in
13150 which case FNMUL is different than FMUL with operand negation. */
13154 {
13159 }
13162 /* FMADD/FNMADD/FNMSUB/FMSUB. */
13164 else
13165 /* FMUL/FNMUL. */
13167 }
13172 }
13173 }
13175 static int
13177 machine_mode mode,
13178 addr_space_t as ATTRIBUTE_UNUSED,
13180 {
13188 {
13190 {
13191 /* This is a CONST or SYMBOL ref which will be split
13192 in a different way depending on the code model in use.
13193 Cost it through the generic infrastructure. */
13195 /* Divide through by the cost of one instruction to
13196 bring it to the same units as the address costs. */
13198 /* The cost is then the cost of preparing the address,
13199 followed by an immediate (possibly 0) offset. */
13201 }
13202 else
13203 {
13204 /* This is most likely a jump table from a case
13205 statement. */
13207 }
13208 }
13211 {
13222 {
13228 else
13230 }
13231 else
13250 }
13254 {
13255 /* For the sake of calculating the cost of the shifted register
13256 component, we can treat same sized modes in the same way. */
13263 else
13264 /* We can't tell, or this is a 128-bit vector. */
13266 }
13269 }
13271 /* Return the cost of a branch. If SPEED_P is true then the compiler is
13272 optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
13273 to be taken. */
13275 int
13277 {
13278 /* When optimizing for speed, use the cost of unpredictable branches. */
13284 else
13286 }
13288 /* Return true if X is a zero or sign extract
13289 usable in an ADD or SUB (extended register) instruction. */
13290 static bool
13292 {
13293 /* The simple case <ARITH>, XD, XN, XM, [us]xt.
13294 No shift. */
13300 }
13302 static bool
13304 {
13306 {
13318 }
13319 }
13321 /* Return true iff X is an rtx that will match an extr instruction
13322 i.e. as described in the *extr<mode>5_insn family of patterns.
13323 OP0 and OP1 will be set to the operands of the shifts involved
13324 on success and will be NULL_RTX otherwise. */
13326 static bool
13328 {
13330 scalar_int_mode mode;
13345 {
13346 /* Canonicalise locally to ashift in op0, lshiftrt in op1. */
13358 {
13362 }
13363 }
13366 }
13368 /* Calculate the cost of calculating (if_then_else (OP0) (OP1) (OP2)),
13369 storing it in *COST. Result is true if the total cost of the operation
13370 has now been calculated. */
13371 static bool
13373 {
13374 rtx inner;
13375 rtx comparator;
13381 {
13385 }
13386 else
13387 {
13391 }
13394 {
13395 /* Conditional branch. */
13398 else
13399 {
13401 {
13403 {
13404 /* TBZ/TBNZ/CBZ/CBNZ. */
13406 /* TBZ/TBNZ. */
13409 else
13410 /* CBZ/CBNZ. */
13414 }
13417 {
13418 /* SUB and SUBS. */
13423 }
13424 }
13426 {
13427 /* TBZ/TBNZ. */
13430 }
13431 }
13432 }
13434 {
13435 /* CCMP. */
13437 {
13438 /* Increase cost of CCMP reg, 0, imm, CC to prefer CMP reg, 0. */
13442 {
13447 else
13449 }
13451 }
13453 /* It's a conditional operation based on the status flags,
13454 so it must be some flavor of CSEL. */
13456 /* CSNEG, CSINV, and CSINC are handled for free as part of CSEL. */
13462 {
13463 /* CSEL with zero-extension (*cmovdi_insn_uxtw). */
13466 }
13468 {
13471 /* CSINV/NEG with zero extend + const 0 (*csinv3_uxtw_insn3). */
13473 }
13478 }
13480 /* We don't know what this is, cost all operands. */
13482 }
13484 /* Check whether X is a bitfield operation of the form shift + extend that
13485 maps down to a UBFIZ/SBFIZ/UBFX/SBFX instruction. If so, return the
13486 operand to which the bitfield operation is applied. Otherwise return
13487 NULL_RTX. */
13489 static rtx
13491 {
13505 {
13523 }
13526 }
13528 /* Return true if the mask and a shift amount from an RTX of the form
13529 (x << SHFT_AMNT) & MASK are valid to combine into a UBFIZ instruction of
13530 mode MODE. See the *andim_ashift<mode>_bfiz pattern. */
13532 bool
13534 rtx shft_amnt)
13535 {
13542 }
13544 /* Return true if the masks and a shift amount from an RTX of the form
13545 ((x & MASK1) | ((y << SHIFT_AMNT) & MASK2)) are valid to combine into
13546 a BFI instruction of mode MODE. See *arch64_bfi patterns. */
13548 bool
13553 {
13556 /* Verify that there is no overlap in what bits are set in the two masks. */
13560 /* Verify that mask2 is not all zeros or ones. */
13564 /* The shift amount should always be less than the mode size. */
13567 /* Verify that the mask being shifted is contiguous and would be in the
13568 least significant bits after shifting by shft_amnt. */
13571 }
13573 /* Calculate the cost of calculating X, storing it in *COST. Result
13574 is true if the total cost of the operation has now been calculated. */
13575 static bool
13578 {
13583 scalar_int_mode int_mode;
13585 /* By default, assume that everything has equivalent cost to the
13586 cheapest instruction. Any additional costs are applied as a delta
13587 above this default. */
13591 {
13593 /* The cost depends entirely on the operands to SET. */
13599 {
13602 {
13616 }
13625 /* Fall through. */
13627 /* The cost is one per vector-register copied. */
13629 {
13632 }
13633 /* const0_rtx is in general free, but we will use an
13634 instruction to set a register to 0. */
13636 {
13637 /* The cost is 1 per register copied. */
13640 }
13641 else
13642 /* Cost is just the cost of the RHS of the set. */
13648 /* Bit-field insertion. Strip any redundant widening of
13649 the RHS to meet the width of the target. */
13660 {
13661 /* MOV immediate is assumed to always be cheap. */
13663 }
13664 else
13665 {
13666 /* BFM. */
13670 }
13675 /* We can't make sense of this, assume default cost. */
13678 }
13682 /* If an instruction can incorporate a constant within the
13683 instruction, the instruction's expression avoids calling
13684 rtx_cost() on the constant. If rtx_cost() is called on a
13685 constant, then it is usually because the constant must be
13686 moved into a register by one or more instructions.
13688 The exception is constant 0, which can be expressed
13689 as XZR/WZR and is therefore free. The exception to this is
13690 if we have (set (reg) (const0_rtx)) in which case we must cost
13691 the move. However, we can catch that when we cost the SET, so
13692 we don't need to consider that here. */
13695 else
13696 {
13697 /* To an approximation, building any other constant is
13698 proportionally expensive to the number of instructions
13699 required to build that constant. This is true whether we
13700 are compiling for SPEED or otherwise. */
13705 }
13710 /* First determine number of instructions to do the move
13711 as an integer constant. */
13715 {
13721 ? SImode
13727 }
13730 {
13731 /* mov[df,sf]_aarch64. */
13733 /* FMOV (scalar immediate). */
13736 {
13737 /* This will be a load from memory. */
13740 else
13742 }
13743 else
13744 /* Otherwise this is +0.0. We get this using MOVI d0, #0
13745 or MOV v0.s[0], wzr - neither of which are modeled by the
13746 cost tables. Just use the default cost. */
13747 {
13748 }
13749 }
13755 {
13756 /* For loads we want the base cost of a load, plus an
13757 approximation for the additional cost of the addressing
13758 mode. */
13772 }
13780 {
13782 {
13783 /* FNEG. */
13785 }
13787 }
13790 {
13793 {
13794 /* CSETM. */
13797 }
13799 /* Cost this as SUB wzr, X. */
13803 }
13806 {
13807 /* Support (neg(fma...)) as a single instruction only if
13808 sign of zeros is unimportant. This matches the decision
13809 making in aarch64.md. */
13811 {
13812 /* FNMADD. */
13815 }
13817 {
13818 /* FNMUL. */
13821 }
13823 /* FNEG. */
13826 }
13833 {
13836 else
13838 }
13855 {
13859 }
13862 {
13863 /* TODO: A write to the CC flags possibly costs extra, this
13864 needs encoding in the cost tables. */
13867 /* ANDS. */
13869 {
13872 }
13875 {
13876 /* ADDS (and CMN alias). */
13879 }
13882 {
13883 /* SUBS. */
13886 }
13891 {
13892 /* COMPARE of ZERO_EXTRACT form of TST-immediate.
13893 Handle it here directly rather than going to cost_logic
13894 since we know the immediate generated for the TST is valid
13895 so we can avoid creating an intermediate rtx for it only
13896 for costing purposes. */
13903 }
13906 {
13907 /* CMN. */
13914 }
13916 /* CMP.
13918 Compare can freely swap the order of operands, and
13919 canonicalization puts the more complex operation first.
13920 But the integer MINUS logic expects the shift/extend
13921 operation in op1. */
13924 {
13927 }
13929 }
13932 {
13933 /* FCMP. */
13938 {
13940 /* FCMP supports constant 0.0 for no extra cost. */
13942 }
13944 }
13947 {
13948 /* Vector compare. */
13953 {
13954 /* Vector cm (eq|ge|gt|lt|le) supports constant 0.0 for no extra
13955 cost. */
13957 }
13959 }
13963 {
13967 cost_minus:
13969 {
13970 /* SUBL2 and SUBW2. */
13973 {
13974 /* The select-operand-high-half versions of the sub instruction
13975 have the same cost as the regular three vector version -
13976 don't add the costs of the select into the costs of the sub.
13977 */
13980 }
13981 }
13985 /* Detect valid immediates. */
13991 {
13993 /* SUB(S) (immediate). */
13996 }
13998 /* Look for SUB (extended register). */
14001 {
14009 }
14013 /* Cost this as an FMA-alike operation. */
14017 {
14020 speed);
14022 }
14027 {
14029 {
14030 /* Vector SUB. */
14032 }
14034 {
14035 /* SUB(S). */
14037 }
14039 {
14040 /* FSUB. */
14042 }
14043 }
14045 }
14048 {
14049 rtx new_op0;
14054 cost_plus:
14056 {
14057 /* ADDL2 and ADDW2. */
14060 {
14061 /* The select-operand-high-half versions of the add instruction
14062 have the same cost as the regular three vector version -
14063 don't add the costs of the select into the costs of the add.
14064 */
14067 }
14068 }
14072 {
14073 /* CSINC. */
14077 }
14082 {
14086 {
14087 /* ADD (immediate). */
14090 /* Some tunings prefer to not use the VL-based scalar ops.
14091 Increase the cost of the poly immediate to prevent their
14092 formation. */
14097 }
14099 }
14103 /* Look for ADD (extended register). */
14106 {
14114 }
14116 /* Strip any extend, leave shifts behind as we will
14117 cost them through mult_cost. */
14122 {
14124 speed);
14126 }
14131 {
14133 {
14134 /* Vector ADD. */
14136 }
14138 {
14139 /* ADD. */
14141 }
14143 {
14144 /* FADD. */
14146 }
14147 }
14149 }
14155 {
14158 else
14160 }
14165 {
14169 {
14172 else
14174 }
14176 }
14179 {
14186 }
14187 /* Fall through. */
14190 cost_logic:
14195 {
14199 }
14207 {
14208 /* This is a UBFM/SBFM. */
14213 }
14216 {
14218 {
14219 /* We have a mask + shift version of a UBFIZ
14220 i.e. the *andim_ashift<mode>_bfiz pattern. */
14224 {
14231 }
14233 {
14234 /* We possibly get the immediate for free, this is not
14235 modelled. */
14242 }
14243 }
14244 else
14245 {
14248 /* Handle ORN, EON, or BIC. */
14254 /* If we had a shift on op0 then this is a logical-shift-
14255 by-register/immediate operation. Otherwise, this is just
14256 a logical operation. */
14258 {
14260 {
14261 /* Shift by immediate. */
14264 else
14266 }
14267 else
14269 }
14271 /* In both cases we want to cost both operands. */
14278 }
14279 }
14287 {
14288 /* Vector NOT. */
14291 }
14293 /* MVN-shifted-reg. */
14295 {
14302 }
14303 /* EON can have two forms: (xor (not a) b) but also (not (xor a b)).
14304 Handle the second form here taking care that 'a' in the above can
14305 be a shift. */
14307 {
14316 {
14319 else
14321 }
14324 }
14325 /* MVN. */
14334 /* If a value is written in SI mode, then zero extended to DI
14335 mode, the operation will in general be free as a write to
14336 a 'w' register implicitly zeroes the upper bits of an 'x'
14337 register. However, if this is
14339 (set (reg) (zero_extend (reg)))
14341 we must cost the explicit register move. */
14344 {
14347 /* If OP_COST is non-zero, then the cost of the zero extend
14348 is effectively the cost of the inner operation. Otherwise
14349 we have a MOV instruction and we take the cost from the MOV
14350 itself. This is true independently of whether we are
14351 optimizing for space or time. */
14356 }
14358 {
14359 /* All loads can zero extend to any size for free. */
14362 }
14366 {
14371 }
14374 {
14376 {
14377 /* UMOV. */
14379 }
14380 else
14381 {
14382 /* We generate an AND instead of UXTB/UXTH. */
14384 }
14385 }
14390 {
14391 /* LDRSH. */
14393 {
14400 }
14402 }
14406 {
14411 }
14414 {
14417 else
14419 }
14427 {
14429 {
14431 {
14432 /* Vector shift (immediate). */
14434 }
14435 else
14436 {
14437 /* LSL (immediate), UBMF, UBFIZ and friends. These are all
14438 aliases. */
14440 }
14441 }
14443 /* We can incorporate zero/sign extend for free. */
14450 }
14451 else
14452 {
14454 {
14456 /* Vector shift (register). */
14458 }
14459 else
14460 {
14462 /* LSLV. */
14469 {
14471 /* We already demanded XEXP (op1, 0) to be REG_P, so
14472 don't recurse into it. */
14474 }
14475 }
14477 }
14487 {
14488 /* ASR (immediate) and friends. */
14490 {
14493 else
14495 }
14499 }
14500 else
14501 {
14503 {
14505 /* Vector shift (register). */
14507 }
14508 else
14509 {
14511 /* ASR (register) and friends. */
14518 {
14520 /* We already demanded XEXP (op1, 0) to be REG_P, so
14521 don't recurse into it. */
14523 }
14524 }
14526 }
14532 {
14533 /* LDR. */
14536 }
14539 {
14540 /* ADRP, followed by ADD. */
14544 }
14547 {
14548 /* ADR. */
14551 }
14554 {
14555 /* One extra load instruction, after accessing the GOT. */
14559 }
14564 /* ADRP/ADD (immediate). */
14571 /* UBFX/SBFX. */
14573 {
14576 else
14578 }
14580 /* We can trust that the immediates used will be correct (there
14581 are no by-register forms), so we need only cost op0. */
14587 /* aarch64_rtx_mult_cost always handles recursion to its
14588 operands. */
14592 /* We can expand signed mod by power of 2 using a NEGS, two parallel
14593 ANDs and a CSNEG. Assume here that CSNEG is the same as the cost of
14594 an unconditional negate. This case should only ever be reached through
14595 the set_smod_pow2_cheap check in expmed.cc. */
14599 {
14600 /* We expand to 4 instructions. Reset the baseline. */
14608 }
14610 /* Fall-through. */
14613 {
14614 /* Slighly prefer UMOD over SMOD. */
14621 }
14628 {
14632 /* There is no integer SQRT, so only DIV and UDIV can get
14633 here. */
14635 /* Slighly prefer UDIV over SDIV. */
14637 else
14639 }
14665 {
14668 else
14670 }
14672 /* FMSUB, FNMADD, and FNMSUB are free. */
14679 /* aarch64_fnma4_elt_to_64v2df has the NEG as operand 1,
14680 and the by-element operand as operand 0. */
14684 /* Catch vector-by-element operations. The by-element operand can
14685 either be (vec_duplicate (vec_select (x))) or just
14686 (vec_select (x)), depending on whether we are multiplying by
14687 a vector or a scalar.
14689 Canonicalization is not very good in these cases, FMA4 will put the
14690 by-element operand as operand 0, FNMA4 will have it as operand 1. */
14701 /* If the remaining parameters are not registers,
14702 get the cost to put them into registers. */
14716 {
14718 {
14719 /*Vector truncate. */
14721 }
14722 else
14724 }
14729 {
14731 {
14732 /*Vector conversion. */
14734 }
14735 else
14737 }
14743 /* Strip the rounding part. They will all be implemented
14744 by the fcvt* family of instructions anyway. */
14746 {
14755 }
14758 {
14761 else
14763 }
14765 /* We can combine fmul by a power of 2 followed by a fcvt into a single
14766 fixed-point fcvt. */
14771 {
14775 }
14782 {
14783 /* ABS (vector). */
14786 }
14788 {
14791 /* FABD, which is analogous to FADD. */
14793 {
14800 }
14801 /* Simple FABS is analogous to FNEG. */
14804 }
14805 else
14806 {
14807 /* Integer ABS will either be split to
14808 two arithmetic instructions, or will be an ABS
14809 (scalar), which we don't model. */
14813 }
14819 {
14822 else
14823 {
14824 /* FMAXNM/FMINNM/FMAX/FMIN.
14825 TODO: This may not be accurate for all implementations, but
14826 we do not model this in the cost tables. */
14828 }
14829 }
14833 /* The floating point round to integer frint* instructions. */
14835 {
14840 }
14843 {
14848 }
14853 /* Decompose <su>muldi3_highpart. */
14855 mode == DImode
14856 /* (lshiftrt:TI */
14859 /* (mult:TI */
14861 /* (ANY_EXTEND:TI (reg:DI))
14862 (ANY_EXTEND:TI (reg:DI))) */
14869 /* (const_int 64) */
14872 {
14873 /* UMULH/SMULH. */
14881 }
14884 {
14885 /* Load using MOVI/MVNI. */
14891 }
14893 /* depending on the operation, either DUP or INS.
14894 For now, keep default costing. */
14897 /* Load using a DUP. */
14901 {
14905 /* cost subreg of 0 as free, otherwise as DUP */
14908 ;
14911 else
14914 }
14917 }
14925 }
14927 /* Wrapper around aarch64_rtx_costs, dumps the partial, or total cost
14928 calculated for X. This cost is stored in *COST. Returns true
14929 if the total cost of X was calculated. */
14930 static bool
14933 {
14938 {
14943 }
14946 }
14948 static int
14951 {
14957 /* Caller save and pointer regs are equivalent to GENERAL_REGS. */
14966 /* Make RDFFR very expensive. In particular, if we know that the FFR
14967 contains a PTRUE (e.g. after a SETFFR), we must never use RDFFR
14968 as a way of obtaining a PTRUE. */
14974 /* Moving between GPR and stack cost is the same as GP2GP. */
14979 /* To/From the stack register, we move via the gprs. */
14985 {
14986 /* 128-bit operations on general registers require 2 instructions. */
14994 /* When AdvSIMD instructions are disabled it is not possible to move
14995 a 128-bit value directly between Q registers. This is handled in
14996 secondary reload. A general register is used as a scratch to move
14997 the upper DI value and the lower DI value is moved directly,
14998 hence the cost is the sum of three moves. */
15003 }
15013 }
15015 /* Implements TARGET_MEMORY_MOVE_COST. */
15016 static int
15018 {
15037 }
15039 /* Implement TARGET_INIT_BUILTINS. */
15040 static void
15042 {
15045 #ifdef SUBTARGET_INIT_BUILTINS
15046 SUBTARGET_INIT_BUILTINS;
15047 #endif
15048 }
15050 /* Implement TARGET_FOLD_BUILTIN. */
15051 static tree
15053 {
15058 {
15064 }
15066 }
15068 /* Implement TARGET_GIMPLE_FOLD_BUILTIN. */
15069 static bool
15071 {
15078 {
15086 }
15093 }
15095 /* Implement TARGET_EXPAND_BUILTIN. */
15096 static rtx
15098 {
15103 {
15109 }
15111 }
15113 /* Implement TARGET_BUILTIN_DECL. */
15114 static tree
15116 {
15119 {
15125 }
15127 }
15129 /* Return true if it is safe and beneficial to use the approximate rsqrt optabs
15130 to optimize 1.0/sqrt. */
15132 static bool
15134 {
15136 && flag_unsafe_math_optimizations
15140 }
15142 /* Function to decide when to use the approximate reciprocal square root
15143 builtin. */
15145 static tree
15147 {
15155 {
15161 }
15163 }
15165 /* Emit code to perform the floating-point operation:
15167 DST = SRC1 * SRC2
15169 where all three operands are already known to be registers.
15170 If the operation is an SVE one, PTRUE is a suitable all-true
15171 predicate. */
15173 static void
15175 {
15180 else
15182 }
15184 /* Emit instruction sequence to compute either the approximate square root
15185 or its approximate reciprocal, depending on the flag RECP, and return
15186 whether the sequence was emitted or not. */
15188 bool
15190 {
15194 {
15197 }
15200 {
15207 || flag_trapping_math
15208 || !flag_unsafe_math_optimizations
15211 }
15212 else
15213 /* Caller assumes we cannot fail. */
15224 {
15225 /* When calculating the approximate square root, compare the
15226 argument with 0.0 and create a mask. */
15229 {
15234 }
15235 else
15236 {
15241 }
15242 }
15244 /* Estimate the approximate reciprocal square root. */
15248 /* Iterate over the series twice for SF and thrice for DF. */
15251 /* Optionally iterate over the series once less for faster performance
15252 while sacrificing the accuracy. */
15255 iterations--;
15257 /* Iterate over the series to calculate the approximate reciprocal square
15258 root. */
15261 {
15269 }
15272 {
15274 /* Multiply nonzero source values by the corresponding intermediate
15275 result elements, so that the final calculation is the approximate
15276 square root rather than its reciprocal. Select a zero result for
15277 zero source values, to avoid the Inf * 0 -> NaN that we'd get
15278 otherwise. */
15281 else
15282 {
15283 /* Qualify the approximate reciprocal square root when the
15284 argument is 0.0 by squashing the intermediary result to 0.0. */
15290 /* Calculate the approximate square root. */
15292 }
15293 }
15295 /* Finalize the approximation. */
15299 }
15301 /* Emit the instruction sequence to compute the approximation for the division
15302 of NUM by DEN in QUO and return whether the sequence was emitted or not. */
15304 bool
15306 {
15317 || flag_trapping_math
15318 || !flag_unsafe_math_optimizations
15330 /* Estimate the approximate reciprocal. */
15334 /* Iterate over the series twice for SF and thrice for DF. */
15337 /* Optionally iterate over the series less for faster performance,
15338 while sacrificing the accuracy. The default is 2 for DF and 1 for SF. */
15341 ? aarch64_double_recp_precision
15344 /* Iterate over the series to calculate the approximate reciprocal. */
15347 {
15352 }
15355 {
15356 /* As the approximate reciprocal of DEN is already calculated, only
15357 calculate the approximate division when NUM is not 1.0. */
15360 }
15362 /* Finalize the approximation. */
15365 }
15367 /* Return the number of instructions that can be issued per cycle. */
15368 static int
15370 {
15372 }
15374 /* Implement TARGET_SCHED_VARIABLE_ISSUE. */
15375 static int
15377 {
15389 }
15391 static int
15393 {
15397 }
15400 /* Implement TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD as
15401 autopref_multipass_dfa_lookahead_guard from haifa-sched.cc. It only
15402 has an effect if PARAM_SCHED_AUTOPREF_QUEUE_DEPTH > 0. */
15404 static int
15407 {
15409 }
15412 /* Vectorizer cost model target hooks. */
15414 /* Information about how the CPU would issue the scalar, Advanced SIMD
15415 or SVE version of a vector loop, using the scheme defined by the
15416 aarch64_base_vec_issue_info hierarchy of structures. */
15417 class aarch64_vec_op_count
15418 {
15438 /* The number of individual "general" operations. See the comments
15439 in aarch64_base_vec_issue_info for details. */
15442 /* The number of load and store operations, under the same scheme
15443 as above. */
15447 /* The minimum number of cycles needed to execute all loop-carried
15448 operations, which in the vector code become associated with
15449 reductions. */
15452 /* The number of individual predicate operations. See the comments
15453 in aarch64_sve_vec_issue_info for details. */
15457 /* The issue information for the core. */
15460 /* - If M_VEC_FLAGS is zero then this structure describes scalar code
15461 - If M_VEC_FLAGS & VEC_ADVSIMD is nonzero then this structure describes
15462 Advanced SIMD code.
15463 - If M_VEC_FLAGS & VEC_ANY_SVE is nonzero then this structure describes
15464 SVE code. */
15467 /* Assume that, when the code is executing on the core described
15468 by M_ISSUE_INFO, one iteration of the loop will handle M_VF_FACTOR
15469 times more data than the vectorizer anticipates.
15471 This is only ever different from 1 for SVE. It allows us to consider
15472 what would happen on a 256-bit SVE target even when the -mtune
15473 parameters say that the “likely” SVE length is 128 bits. */
15475 };
15483 {
15484 }
15486 /* Return the base issue information (i.e. the parts that make sense
15487 for both scalar and vector code). Return null if we have no issue
15488 information. */
15491 {
15495 }
15497 /* If the structure describes vector code and we have associated issue
15498 information, return that issue information, otherwise return null. */
15501 {
15507 }
15509 /* If the structure describes SVE code and we have associated issue
15510 information, return that issue information, otherwise return null. */
15513 {
15517 }
15519 /* Estimate the minimum number of cycles per iteration needed to rename
15520 the instructions.
15522 ??? For now this is done inline rather than via cost tables, since it
15523 isn't clear how it should be parameterized for the general case. */
15524 fractional_cost
15526 {
15530 /* + 1 for an addition. We've already counted a general op for each
15531 store, so we don't need to account for stores separately. The branch
15532 reads no registers and so does not need to be counted either.
15534 ??? This value is very much on the pessimistic side, but seems to work
15535 pretty well in practice. */
15539 }
15541 /* Like min_cycles_per_iter, but excluding predicate operations. */
15542 fractional_cost
15544 {
15555 }
15557 /* Like min_cycles_per_iter, but including only the predicate operations. */
15558 fractional_cost
15560 {
15564 }
15566 /* Estimate the minimum number of cycles needed to issue the operations.
15567 This is a very simplistic model! */
15568 fractional_cost
15570 {
15573 }
15575 /* Dump information about the structure. */
15576 void
15578 {
15595 {
15597 " estimated min cycles per iteration"
15601 " estimated min cycles per iteration"
15603 }
15608 }
15610 /* Information about vector code that we're in the process of costing. */
15612 {
15627 aarch64_vec_op_count *);
15636 /* True if we have performed one-time initialization based on the
15637 vec_info. */
15640 /* This loop uses an average operation that is not supported by SVE, but is
15641 supported by Advanced SIMD and SVE2. */
15644 /* - If M_VEC_FLAGS is zero then we're costing the original scalar code.
15645 - If M_VEC_FLAGS & VEC_ADVSIMD is nonzero then we're costing Advanced
15646 SIMD code.
15647 - If M_VEC_FLAGS & VEC_ANY_SVE is nonzero then we're costing SVE code. */
15650 /* At the moment, we do not model LDP and STP in the vector and scalar costs.
15651 This means that code such as:
15653 a[0] = x;
15654 a[1] = x;
15656 will be costed as two scalar instructions and two vector instructions
15657 (a scalar_to_vec and an unaligned_store). For SLP, the vector form
15658 wins if the costs are equal, because of the fact that the vector costs
15659 include constant initializations whereas the scalar costs don't.
15660 We would therefore tend to vectorize the code above, even though
15661 the scalar version can use a single STP.
15663 We should eventually fix this and model LDP and STP in the main costs;
15664 see the comment in aarch64_sve_adjust_stmt_cost for some of the problems.
15665 Until then, we look specifically for code that does nothing more than
15666 STP-like operations. We cost them on that basis in addition to the
15667 normal latency-based costs.
15669 If the scalar or vector code could be a sequence of STPs +
15670 initialization, this variable counts the cost of the sequence,
15671 with 2 units per instruction. The variable is ~0U for other
15672 kinds of code. */
15675 /* On some CPUs, SVE and Advanced SIMD provide the same theoretical vector
15676 throughput, such as 4x128 Advanced SIMD vs. 2x256 SVE. In those
15677 situations, we try to predict whether an Advanced SIMD implementation
15678 of the loop could be completely unrolled and become straight-line code.
15679 If so, it is generally better to use the Advanced SIMD version rather
15680 than length-agnostic SVE, since the SVE loop would execute an unknown
15681 number of times and so could not be completely unrolled in the same way.
15683 If we're applying this heuristic, M_UNROLLED_ADVSIMD_NITERS is the
15684 number of Advanced SIMD loop iterations that would be unrolled and
15685 M_UNROLLED_ADVSIMD_STMTS estimates the total number of statements
15686 in the unrolled loop. Both values are zero if we're not applying
15687 the heuristic. */
15691 /* If we're vectorizing a loop that executes a constant number of times,
15692 this variable gives the number of times that the vector loop would
15693 iterate, otherwise it is zero. */
15696 /* Used only when vectorizing loops. Estimates the number and kind of
15697 operations that would be needed by one iteration of the scalar
15698 or vector loop. There is one entry for each tuning option of
15699 interest. */
15701 };
15708 {
15710 {
15713 {
15716 vf_factor });
15717 }
15718 }
15719 }
15721 /* Implement TARGET_VECTORIZE_CREATE_COSTS. */
15722 vector_costs *
15724 {
15726 }
15728 /* Return true if the current CPU should use the new costs defined
15729 in GCC 11. This should be removed for GCC 12 and above, with the
15730 costs applying to all CPUs instead. */
15731 static bool
15733 {
15736 }
15738 /* Return the appropriate SIMD costs for vectors of type VECTYPE. */
15741 {
15748 }
15750 /* Return the appropriate SIMD costs for vectors with VEC_* flags FLAGS. */
15753 {
15758 }
15760 /* If STMT_INFO is a memory reference, return the scalar memory type,
15761 otherwise return null. */
15762 static tree
15764 {
15768 }
15770 /* Decide whether to use the unrolling heuristic described above
15771 m_unrolled_advsimd_niters, updating that field if so. LOOP_VINFO
15772 describes the loop that we're vectorizing. */
15773 void
15776 {
15777 /* The heuristic only makes sense on targets that have the same
15778 vector throughput for SVE and Advanced SIMD. */
15783 /* We only want to apply the heuristic if LOOP_VINFO is being
15784 vectorized for SVE. */
15788 /* Check whether it is possible in principle to use Advanced SIMD
15789 instead. */
15793 /* We don't want to apply the heuristic to outer loops, since it's
15794 harder to track two levels of unrolling. */
15798 /* Only handle cases in which the number of Advanced SIMD iterations
15799 would be known at compile time but the number of SVE iterations
15800 would not. */
15805 /* Guess how many times the Advanced SIMD loop would iterate and make
15806 sure that it is within the complete unrolling limit. Even if the
15807 number of iterations is small enough, the number of statements might
15808 not be, which is why we need to estimate the number of statements too. */
15811 unsigned HOST_WIDE_INT unrolled_advsimd_niters
15816 /* Record that we're applying the heuristic and should try to estimate
15817 the number of statements in the Advanced SIMD loop. */
15819 }
15821 /* Do one-time initialization of the aarch64_vector_costs given that we're
15822 costing the loop vectorization described by LOOP_VINFO. */
15823 void
15825 {
15826 /* Record the number of times that the vector loop would execute,
15827 if known. */
15831 {
15835 else
15837 }
15839 /* Detect whether we're vectorizing for SVE and should apply the unrolling
15840 heuristic described above m_unrolled_advsimd_niters. */
15843 /* Record the issue information for any SVE WHILE instructions that the
15844 loop needs. */
15846 {
15856 }
15857 }
15859 /* Implement targetm.vectorize.builtin_vectorization_cost. */
15860 static int
15862 tree vectype,
15864 {
15875 {
15928 }
15929 }
15931 /* Return true if an access of kind KIND for STMT_INFO represents one
15932 vector of an LD[234] or ST[234] operation. Return the total number of
15933 vectors (2, 3 or 4) if so, otherwise return a value outside that range. */
15934 static int
15936 {
15942 {
15947 }
15949 }
15951 /* Return true if creating multiple copies of STMT_INFO for Advanced SIMD
15952 vectors would produce a series of LDP or STP operations. KIND is the
15953 kind of statement that STMT_INFO represents. */
15954 static bool
15956 stmt_vec_info stmt_info)
15957 {
15959 {
15968 }
15975 }
15977 /* Return true if STMT_INFO is the second part of a two-statement multiply-add
15978 or multiply-subtract sequence that might be suitable for fusing into a
15979 single instruction. If VEC_FLAGS is zero, analyze the operation as
15980 a scalar one, otherwise analyze it as an operation on vectors with those
15981 VEC_* flags. */
15982 static bool
15985 {
15998 {
16000 /* ??? Should we try to check for a single use as well? */
16013 {
16014 /* Scalar and SVE code can tie the result to any FMLA input (or none,
16015 although that requires a MOVPRFX for SVE). However, Advanced SIMD
16016 only supports MLA forms, so will require a move if the result
16017 cannot be tied to the accumulator. The most important case in
16018 which this is true is when the accumulator input is invariant. */
16026 }
16029 }
16031 }
16033 /* We are considering implementing STMT_INFO using SVE. If STMT_INFO is an
16034 in-loop reduction that SVE supports directly, return its latency in cycles,
16035 otherwise return zero. SVE_COSTS specifies the latencies of the relevant
16036 instructions. */
16037 static unsigned int
16039 stmt_vec_info stmt_info,
16041 {
16043 {
16049 {
16062 }
16064 }
16067 }
16069 /* STMT_INFO describes a loop-carried operation in the original scalar code
16070 that we are considering implementing as a reduction. Return one of the
16071 following values, depending on VEC_FLAGS:
16073 - If VEC_FLAGS is zero, return the loop carry latency of the original
16074 scalar operation.
16076 - If VEC_FLAGS & VEC_ADVSIMD, return the loop carry latency of the
16077 Advanced SIMD implementation.
16079 - If VEC_FLAGS & VEC_ANY_SVE, return the loop carry latency of the
16080 SVE implementation. */
16081 static unsigned int
16084 {
16090 /* If the caller is asking for the SVE latency, check for forms of reduction
16091 that only SVE can handle directly. */
16093 {
16094 unsigned int latency
16098 }
16100 /* Handle scalar costs. */
16103 {
16107 }
16109 /* Otherwise, the loop body just contains normal integer or FP operations,
16110 with a vector reduction outside the loop. */
16116 }
16118 /* STMT_COST is the cost calculated by aarch64_builtin_vectorization_cost
16119 for STMT_INFO, which has cost kind KIND. If this is a scalar operation,
16120 try to subdivide the target-independent categorization provided by KIND
16121 to get a more accurate cost. */
16122 static fractional_cost
16124 stmt_vec_info stmt_info,
16125 fractional_cost stmt_cost)
16126 {
16127 /* Detect an extension of a loaded value. In general, we'll be able to fuse
16128 the extension with the load. */
16133 }
16135 /* STMT_COST is the cost calculated by aarch64_builtin_vectorization_cost
16136 for the vectorized form of STMT_INFO, which has cost kind KIND and which
16137 when vectorized would operate on vector type VECTYPE. Try to subdivide
16138 the target-independent categorization provided by KIND to get a more
16139 accurate cost. WHERE specifies where the cost associated with KIND
16140 occurs. */
16141 static fractional_cost
16145 fractional_cost stmt_cost)
16146 {
16152 /* It's generally better to avoid costing inductions, since the induction
16153 will usually be hidden by other operations. This is particularly true
16154 for things like COND_REDUCTIONS. */
16158 /* Detect cases in which vec_to_scalar is describing the extraction of a
16159 vector element in preparation for a scalar store. The store itself is
16160 costed separately. */
16164 /* Detect SVE gather loads, which are costed as a single scalar_load
16165 for each element. We therefore need to divide the full-instruction
16166 cost by the number of elements in the vector. */
16168 && sve_costs
16170 {
16175 }
16177 /* Detect cases in which a scalar_store is really storing one element
16178 in a scatter operation. */
16180 && sve_costs
16184 /* Detect cases in which vec_to_scalar represents an in-loop reduction. */
16188 {
16189 unsigned int latency
16193 }
16195 /* Detect cases in which vec_to_scalar represents a single reduction
16196 instruction like FADDP or MAXV. */
16201 {
16226 }
16228 /* Otherwise stick with the original categorization. */
16230 }
16232 /* STMT_COST is the cost calculated by aarch64_builtin_vectorization_cost
16233 for STMT_INFO, which has cost kind KIND and which when vectorized would
16234 operate on vector type VECTYPE. Adjust the cost as necessary for SVE
16235 targets. */
16236 static fractional_cost
16239 fractional_cost stmt_cost)
16240 {
16241 /* Unlike vec_promote_demote, vector_stmt conversions do not change the
16242 vector register size or number of units. Integer promotions of this
16243 type therefore map to SXT[BHW] or UXT[BHW].
16245 Most loads have extending forms that can do the sign or zero extension
16246 on the fly. Optimistically assume that a load followed by an extension
16247 will fold to this form during combine, and that the extension therefore
16248 comes for free. */
16252 /* For similar reasons, vector_stmt integer truncations are a no-op,
16253 because we can just ignore the unused upper bits of the source. */
16257 /* Advanced SIMD can load and store pairs of registers using LDP and STP,
16258 but there are no equivalent instructions for SVE. This means that
16259 (all other things being equal) 128-bit SVE needs twice as many load
16260 and store instructions as Advanced SIMD in order to process vector pairs.
16262 Also, scalar code can often use LDP and STP to access pairs of values,
16263 so it is too simplistic to say that one SVE load or store replaces
16264 VF scalar loads and stores.
16266 Ideally we would account for this in the scalar and Advanced SIMD
16267 costs by making suitable load/store pairs as cheap as a single
16268 load/store. However, that would be a very invasive change and in
16269 practice it tends to stress other parts of the cost model too much.
16270 E.g. stores of scalar constants currently count just a store,
16271 whereas stores of vector constants count a store and a vec_init.
16272 This is an artificial distinction for AArch64, where stores of
16273 nonzero scalar constants need the same kind of register invariant
16274 as vector stores.
16276 An alternative would be to double the cost of any SVE loads and stores
16277 that could be paired in Advanced SIMD (and possibly also paired in
16278 scalar code). But this tends to stress other parts of the cost model
16279 in the same way. It also means that we can fall back to Advanced SIMD
16280 even if full-loop predication would have been useful.
16282 Here we go for a more conservative version: double the costs of SVE
16283 loads and stores if one iteration of the scalar loop processes enough
16284 elements for it to use a whole number of Advanced SIMD LDP or STP
16285 instructions. This makes it very likely that the VF would be 1 for
16286 Advanced SIMD, and so no epilogue should be needed. */
16288 {
16295 }
16298 }
16300 /* STMT_COST is the cost calculated for STMT_INFO, which has cost kind KIND
16301 and which when vectorized would operate on vector type VECTYPE. Add the
16302 cost of any embedded operations. */
16303 static fractional_cost
16306 {
16308 {
16311 /* Detect cases in which a vector load or store represents an
16312 LD[234] or ST[234] instruction. */
16314 {
16326 }
16330 {
16333 else
16335 }
16336 }
16340 {
16343 else
16345 }
16348 }
16350 /* COUNT, KIND and STMT_INFO are the same as for vector_costs::add_stmt_cost
16351 and they describe an operation in the body of a vector loop. Record issue
16352 information relating to the vector operation in OPS. */
16353 void
16355 stmt_vec_info stmt_info,
16357 {
16364 /* Calculate the minimum cycles per iteration imposed by a reduction
16365 operation. */
16368 {
16369 unsigned int base
16372 /* ??? Ideally we'd do COUNT reductions in parallel, but unfortunately
16373 that's not yet the case. */
16375 }
16377 /* Assume that multiply-adds will become a single operation. */
16381 /* Count the basic operation cost associated with KIND. */
16383 {
16388 /* We currently don't expect these to be used in a loop body. */
16416 }
16418 /* Add any embedded comparison operations. */
16423 /* COND_REDUCTIONS need two sets of VEC_COND_EXPRs, whereas so far we
16424 have only accounted for one. */
16429 /* Count the predicate operations needed by an SVE comparison. */
16432 {
16437 }
16439 /* Add any extra overhead associated with LD[234] and ST[234] operations. */
16442 {
16454 }
16456 /* Add any overhead associated with gather loads and scatter stores. */
16460 {
16464 }
16465 }
16467 /* Return true if STMT_INFO contains a memory access and if the constant
16468 component of the memory address is aligned to SIZE bytes. */
16469 static bool
16471 poly_uint64 size)
16472 {
16479 /* Needed for gathers & scatters, for example. */
16484 }
16486 /* Check if a scalar or vector stmt could be part of a region of code
16487 that does nothing more than store values to memory, in the scalar
16488 case using STP. Return the cost of the stmt if so, counting 2 for
16489 one instruction. Return ~0U otherwise.
16491 The arguments are a subset of those passed to add_stmt_cost. */
16492 unsigned int
16495 {
16496 /* Code that stores vector constants uses a vector_load to create
16497 the constant. We don't apply the heuristic to that case for two
16498 main reasons:
16500 - At the moment, STPs are only formed via peephole2, and the
16501 constant scalar moves would often come between STRs and so
16502 prevent STP formation.
16504 - The scalar code also has to load the constant somehow, and that
16505 isn't costed. */
16507 {
16509 /* Count 2 insns for a GPR->SIMD dup and 1 insn for a FPR->SIMD dup. */
16514 /* Count 1 insn for the maximum number of FP->SIMD INS
16515 instructions. */
16518 /* Count 2 insns for a GPR->SIMD move and 2 insns for the
16519 maximum number of GPR->SIMD INS instructions. */
16524 /* Count 1 insn per vector if we can't form STP Q pairs. */
16532 {
16533 /* Assume we won't be able to use STP if the constant offset
16534 component of the address is misaligned. ??? This could be
16535 removed if we formed STP pairs earlier, rather than relying
16536 on peephole2. */
16540 }
16545 {
16546 /* Check for a mode in which STP pairs can be formed. */
16551 /* Assume we won't be able to use STP if the constant offset
16552 component of the address is misaligned. ??? This could be
16553 removed if we formed STP pairs earlier, rather than relying
16554 on peephole2. */
16557 }
16562 }
16563 }
16565 unsigned
16569 vect_cost_model_location where)
16570 {
16571 fractional_cost stmt_cost
16575 && stmt_info
16578 /* Do one-time initialization based on the vinfo. */
16581 {
16586 }
16588 /* Apply the heuristic described above m_stp_sequence_cost. */
16590 {
16594 }
16596 /* Try to get a more accurate cost by looking at STMT_INFO instead
16597 of just looking at KIND. */
16599 {
16600 /* If we scalarize a strided store, the vectorizer costs one
16601 vec_to_scalar for each element. However, we can store the first
16602 element using an FP store without a separate extract step. */
16613 }
16615 /* Do any SVE-specific adjustments to the cost. */
16621 {
16622 /* Account for any extra "embedded" costs that apply additively
16623 to the base cost calculated above. */
16625 stmt_cost);
16627 /* If we're recording a nonzero vector loop body cost for the
16628 innermost loop, also estimate the operations that would need
16629 to be issued by all relevant implementations of the loop. */
16637 /* If we're applying the SVE vs. Advanced SIMD unrolling heuristic,
16638 estimate the number of statements in the unrolled Advanced SIMD
16639 loop. For simplicitly, we assume that one iteration of the
16640 Advanced SIMD loop would need the same number of statements
16641 as one iteration of the SVE loop. */
16645 /* Detect the use of an averaging operation. */
16649 {
16651 {
16657 }
16658 }
16659 }
16661 }
16663 /* Return true if (a) we're applying the Advanced SIMD vs. SVE unrolling
16664 heuristic described above m_unrolled_advsimd_niters and (b) the heuristic
16665 says that we should prefer the Advanced SIMD loop. */
16666 bool
16668 {
16675 m_unrolled_advsimd_stmts);
16677 /* The balance here is tricky. On the one hand, we can't be sure whether
16678 the code is vectorizable with Advanced SIMD or not. However, even if
16679 it isn't vectorizable with Advanced SIMD, there's a possibility that
16680 the scalar code could also be unrolled. Some of the code might then
16681 benefit from SLP, or from using LDP and STP. We therefore apply
16682 the heuristic regardless of can_use_advsimd_p. */
16684 && (m_unrolled_advsimd_stmts
16686 }
16688 /* Subroutine of adjust_body_cost for handling SVE. Use ISSUE_INFO to work out
16689 how fast the SVE code can be issued and compare it to the equivalent value
16690 for scalar code (SCALAR_CYCLES_PER_ITER). If COULD_USE_ADVSIMD is true,
16691 also compare it to the issue rate of Advanced SIMD code
16692 (ADVSIMD_CYCLES_PER_ITER).
16694 ORIG_BODY_COST is the cost originally passed to adjust_body_cost and
16695 *BODY_COST is the current value of the adjusted cost. *SHOULD_DISPARAGE
16696 is true if we think the loop body is too expensive. */
16698 fractional_cost
16701 fractional_cost scalar_cycles_per_iter,
16704 {
16711 /* If the scalar version of the loop could issue at least as
16712 quickly as the predicate parts of the SVE loop, make the SVE loop
16713 prohibitively expensive. In this case vectorization is adding an
16714 overhead that the original scalar code didn't have.
16716 This is mostly intended to detect cases in which WHILELOs dominate
16717 for very tight loops, which is something that normal latency-based
16718 costs would not model. Adding this kind of cliffedge would be
16719 too drastic for scalar_cycles_per_iter vs. sve_cycles_per_iter;
16720 code in the caller handles that case in a more conservative way. */
16723 {
16724 unsigned int min_cost
16727 {
16730 "Increasing body cost to %d because the"
16731 " scalar code could issue within the limit"
16733 min_cost);
16736 }
16737 }
16740 }
16742 unsigned int
16745 {
16747 /* If we are trying to unroll an Advanced SIMD main loop that contains
16748 an averaging operation that we do not support with SVE and we might use a
16749 predicated epilogue, we need to be conservative and block unrolling as
16750 this might lead to a less optimal loop for the first and only epilogue
16751 using the original loop's vectorization factor.
16752 TODO: Remove this constraint when we add support for multiple epilogue
16753 vectorization. */
16760 {
16765 /* Limit unroll factor to a value adjustable by the user, the default
16766 value is 4. */
16769 unsigned int factor
16773 /* Sanity check, this should never happen. */
16777 /* Check stores. */
16779 {
16783 }
16785 /* Check loads + stores. */
16787 {
16791 }
16793 /* Check general ops. */
16795 {
16799 }
16801 }
16803 /* Make sure unroll factor is power of 2. */
16805 }
16807 /* BODY_COST is the cost of a vector loop body. Adjust the cost as necessary
16808 and return the new cost. */
16809 unsigned int
16814 {
16828 fractional_cost scalar_cycles_per_iter
16834 {
16838 m_num_vector_iterations);
16842 " estimated cycles per vector iteration"
16845 }
16848 {
16851 vector_cycles_per_iter
16856 {
16857 /* Also take Neoverse V1 tuning into account, doubling the
16858 scalar and Advanced SIMD estimates to account for the
16859 doubling in SVE vector length. */
16866 }
16867 }
16868 else
16869 {
16871 {
16875 }
16876 }
16878 /* Decide whether to stick to latency-based costs or whether to try to
16879 take issue rates into account. */
16886 {
16889 "Low iteration count, so using pure latency"
16891 }
16892 /* Increase the cost of the vector code if it looks like the scalar code
16893 could issue more quickly. These values are only rough estimates,
16894 so minor differences should only result in minor changes. */
16896 {
16898 scalar_cycles_per_iter);
16901 "Increasing body cost to %d because scalar code"
16903 }
16904 /* In general, it's expected that the proposed vector code would be able
16905 to issue more quickly than the original scalar code. This should
16906 already be reflected to some extent in the latency-based costs.
16908 However, the latency-based costs effectively assume that the scalar
16909 code and the vector code execute serially, which tends to underplay
16910 one important case: if the real (non-serialized) execution time of
16911 a scalar iteration is dominated by loop-carried dependencies,
16912 and if the vector code is able to reduce both the length of
16913 the loop-carried dependencies *and* the number of cycles needed
16914 to issue the code in general, we can be more confident that the
16915 vector code is an improvement, even if adding the other (non-loop-carried)
16916 latencies tends to hide this saving. We therefore reduce the cost of the
16917 vector loop body in proportion to the saving. */
16922 {
16924 scalar_cycles_per_iter);
16927 "Decreasing body cost to %d account for smaller"
16929 }
16932 }
16934 void
16936 {
16941 && m_vec_flags
16943 {
16946 m_suggested_unroll_factor
16948 }
16950 /* Apply the heuristic described above m_stp_sequence_cost. Prefer
16951 the scalar code in the event of a tie, since there is more chance
16952 of scalar code being optimized with surrounding operations. */
16954 && scalar_costs
16960 }
16962 bool
16965 {
16979 /* Apply the unrolling heuristic described above
16980 m_unrolled_advsimd_niters. */
16983 {
16987 {
16990 "Preferring Advanced SIMD loop because"
16993 }
16994 }
16997 {
16999 {
17011 }
17018 /* If it appears that one loop could process the same amount of data
17019 in fewer cycles, prefer that loop over the other one. */
17020 fractional_cost this_cost
17022 fractional_cost other_cost
17025 {
17034 }
17036 {
17039 "Preferring loop with lower cycles"
17042 }
17044 /* If the issue rate of SVE code is limited by predicate operations
17045 (i.e. if sve_pred_cycles_per_iter > sve_nonpred_cycles_per_iter),
17046 and if Advanced SIMD code could issue within the limit imposed
17047 by the predicate operations, the predicate operations are adding an
17048 overhead that the original code didn't have and so we should prefer
17049 the Advanced SIMD version. */
17052 {
17056 {
17059 "Preferring Advanced SIMD loop since"
17062 }
17064 };
17069 }
17072 }
17076 /* Parse the TO_PARSE string and put the architecture struct that it
17077 selects into RES and the architectural features into ISA_FLAGS.
17078 Return an aarch64_parse_opt_result describing the parse result.
17079 If there is an error parsing, RES and ISA_FLAGS are left unchanged.
17080 When the TO_PARSE string contains an invalid extension,
17081 a copy of the string is created and stored to INVALID_EXTENSION. */
17083 static enum aarch64_parse_opt_result
17086 {
17095 else
17102 /* Loop through the list of supported ARCHes to find a match. */
17104 {
17107 {
17111 {
17112 /* TO_PARSE string contains at least one extension. */
17113 enum aarch64_parse_opt_result ext_res
17118 }
17119 /* Extension parsing was successful. Confirm the result
17120 arch and ISA flags. */
17124 }
17125 }
17127 /* ARCH name not found in list. */
17129 }
17131 /* Parse the TO_PARSE string and put the result tuning in RES and the
17132 architecture flags in ISA_FLAGS. Return an aarch64_parse_opt_result
17133 describing the parse result. If there is an error parsing, RES and
17134 ISA_FLAGS are left unchanged.
17135 When the TO_PARSE string contains an invalid extension,
17136 a copy of the string is created and stored to INVALID_EXTENSION. */
17138 static enum aarch64_parse_opt_result
17141 {
17150 else
17157 /* Loop through the list of supported CPUs to find a match. */
17159 {
17161 {
17166 {
17167 /* TO_PARSE string contains at least one extension. */
17168 enum aarch64_parse_opt_result ext_res
17173 }
17174 /* Extension parsing was successfull. Confirm the result
17175 cpu and ISA flags. */
17179 }
17180 }
17182 /* CPU name not found in list. */
17184 }
17186 /* Parse the TO_PARSE string and put the cpu it selects into RES.
17187 Return an aarch64_parse_opt_result describing the parse result.
17188 If the parsing fails the RES does not change. */
17190 static enum aarch64_parse_opt_result
17192 {
17195 /* Loop through the list of supported CPUs to find a match. */
17197 {
17199 {
17202 }
17203 }
17205 /* CPU name not found in list. */
17207 }
17209 /* Parse TOKEN, which has length LENGTH to see if it is an option
17210 described in FLAG. If it is, return the index bit for that fusion type.
17211 If not, error (printing OPTION_NAME) and return zero. */
17213 static unsigned int
17218 {
17220 {
17224 }
17228 }
17230 /* Parse OPTION which is a comma-separated list of flags to enable.
17231 FLAGS gives the list of flags we understand, INITIAL_STATE gives any
17232 default state we inherit from the CPU tuning structures. OPTION_NAME
17233 gives the top-level option we are parsing in the -moverride string,
17234 for use in error messages. */
17236 static unsigned int
17241 {
17248 {
17251 token_length,
17252 flags,
17253 option_name);
17254 /* If we find "none" (or, for simplicity's sake, an error) anywhere
17255 in the token stream, reset the supported operations. So:
17257 adrp+add.cmp+branch.none.adrp+add
17259 would have the result of turning on only adrp+add fusion. */
17265 }
17267 /* We ended with a comma, print something. */
17269 {
17272 }
17274 /* We still have one more token to parse. */
17277 token_length,
17278 flags,
17279 option_name);
17285 }
17287 /* Support for overriding instruction fusion. */
17289 static void
17292 {
17294 aarch64_fusible_pairs,
17297 }
17299 /* Support for overriding other tuning flags. */
17301 static void
17304 {
17305 tune->extra_tuning_flags
17307 aarch64_tuning_flags,
17310 }
17312 /* Parse the sve_width tuning moverride string in TUNE_STRING.
17313 Accept the valid SVE vector widths allowed by
17314 aarch64_sve_vector_bits_enum and use it to override sve_width
17315 in TUNE. */
17317 static void
17320 {
17325 {
17328 }
17330 {
17339 }
17341 }
17343 /* Parse TOKEN, which has length LENGTH to see if it is a tuning option
17344 we understand. If it is, extract the option string and handoff to
17345 the appropriate function. */
17347 void
17351 {
17357 {
17360 }
17362 /* Get the length of the option name. */
17364 /* Skip the '=' to get to the option string. */
17365 option_part++;
17368 {
17370 {
17373 }
17374 }
17378 }
17380 /* A checking mechanism for the implementation of the tls size. */
17382 static void
17384 {
17389 {
17391 /* Both the default and maximum TLS size allowed under tiny is 1M which
17392 needs two instructions to address, so we clamp the size to 24. */
17397 /* The maximum TLS size allowed under small is 4G. */
17402 /* The maximum TLS size allowed under large is 16E.
17403 FIXME: 16E should be 64bit, we only support 48bit offset now. */
17409 }
17412 }
17414 /* Return the CPU corresponding to the enum CPU. */
17418 {
17422 }
17424 /* Return the architecture corresponding to the enum ARCH. */
17428 {
17432 }
17434 /* Parse STRING looking for options in the format:
17435 string :: option:string
17436 option :: name=substring
17437 name :: {a-z}
17438 substring :: defined by option. */
17440 static void
17443 {
17454 {
17456 /* Make this substring look like a string. */
17460 }
17462 /* One last option to parse. */
17465 }
17467 /* Adjust CURRENT_TUNE (a generic tuning struct) with settings that
17468 are best for a generic target with the currently-enabled architecture
17469 extensions. */
17470 static void
17472 {
17473 /* Neoverse V1 is the only core that is known to benefit from
17474 AARCH64_EXTRA_TUNE_CSE_SVE_VL_CONSTANTS. There is therefore no
17475 point enabling it for SVE2 and above. */
17477 current_tune.extra_tuning_flags
17479 }
17481 static void
17483 {
17485 {
17486 opts->x_aarch64_branch_protection_string
17488 }
17490 /* PR 70044: We have to be careful about being called multiple times for the
17491 same function. This means all changes should be repeatable. */
17493 /* Set aarch64_use_frame_pointer based on -fno-omit-frame-pointer.
17494 Disable the frame pointer flag so the mid-end will not use a frame
17495 pointer in leaf functions in order to support -fomit-leaf-frame-pointer.
17496 Set x_flag_omit_frame_pointer to the special value 2 to differentiate
17497 between -fomit-frame-pointer (1) and -fno-omit-frame-pointer (2). */
17502 /* If not optimizing for size, set the default
17503 alignment to what the target wants. */
17505 {
17512 }
17514 /* We default to no pc-relative literal loads. */
17518 /* If -mpc-relative-literal-loads is set on the command line, this
17519 implies that the user asked for PC relative literal loads. */
17523 /* In the tiny memory model it makes no sense to disallow PC relative
17524 literal pool loads. */
17529 /* When enabling the lower precision Newton series for the square root, also
17530 enable it for the reciprocal square root, since the latter is an
17531 intermediary step for the former. */
17534 }
17536 /* 'Unpack' up the internal tuning structs and update the options
17537 in OPTS. The caller must have set up selected_tune and selected_arch
17538 as all the other target-specific codegen decisions are
17539 derived from them. */
17541 void
17543 {
17547 /* Make a copy of the tuning parameters attached to the core, which
17548 we may later overwrite. */
17557 /* This target defaults to strict volatile bitfields. */
17563 {
17566 aarch64_stack_protector_guard_offset_str);
17567 }
17572 {
17574 "%<-mstack-protector-guard-reg%> must be used "
17576 }
17579 {
17582 }
17585 {
17594 }
17605 {
17617 }
17619 /* We don't mind passing in global_options_set here as we don't use
17620 the *options_set structs anyway. */
17624 /* If using Advanced SIMD only for autovectorization disable SVE vector costs
17625 comparison. */
17630 /* Set up parameters to be used in prefetching algorithm. Do not
17631 override the defaults unless we are tuning for a core we have
17632 researched values for. */
17635 param_simultaneous_prefetches,
17639 param_l1_cache_size,
17643 param_l1_cache_line_size,
17647 {
17649 param_destruct_interfere_size,
17652 param_construct_interfere_size,
17654 }
17655 else
17656 {
17657 /* For a generic AArch64 target, cover the current range of cache line
17658 sizes. */
17660 param_destruct_interfere_size,
17663 param_construct_interfere_size,
17665 }
17669 param_l2_cache_size,
17676 param_prefetch_minimum_stride,
17679 /* Use the alternative scheduling-pressure algorithm by default. */
17681 param_sched_pressure_algorithm,
17682 SCHED_PRESSURE_MODEL);
17684 /* Validate the guard size. */
17692 /* Enforce that interval is the same size as size so the mid-end does the
17693 right thing. */
17695 param_stack_clash_protection_probe_interval,
17696 guard_size);
17698 /* The maybe_set calls won't update the value if the user has explicitly set
17699 one. Which means we need to validate that probing interval and guard size
17700 are equal. */
17701 int probe_interval
17707 /* Enable sw prefetching at specified optimization level for
17708 CPUS that have prefetch. Lower optimization level threshold by 1
17709 when profiling is enabled. */
17717 }
17719 /* Print a hint with a suggestion for a core or architecture name that
17720 most closely resembles what the user passed in STR. ARCH is true if
17721 the user is asking for an architecture name. ARCH is false if the user
17722 is asking for a core name. */
17724 static void
17726 {
17732 #ifdef HAVE_LOCAL_CPU_DETECT
17733 /* Add also "native" as possible value. */
17736 #endif
17743 else
17747 }
17749 /* Print a hint with a suggestion for a core name that most closely resembles
17750 what the user passed in STR. */
17754 {
17756 }
17758 /* Print a hint with a suggestion for an architecture name that most closely
17759 resembles what the user passed in STR. */
17763 {
17765 }
17768 /* Print a hint with a suggestion for an extension name
17769 that most closely resembles what the user passed in STR. */
17771 void
17773 {
17781 else
17785 }
17787 /* Validate a command-line -mcpu option. Parse the cpu and extensions (if any)
17788 specified in STR and throw errors if appropriate. Put the results if
17789 they are valid in RES and ISA_FLAGS. Return whether the option is
17790 valid. */
17792 static bool
17795 {
17797 enum aarch64_parse_opt_result parse_res
17804 {
17819 }
17822 }
17824 /* Straight line speculation indicators. */
17825 enum aarch64_sls_hardening_type
17826 {
17831 };
17834 /* Return whether we should mitigatate Straight Line Speculation for the RET
17835 and BR instructions. */
17836 bool
17838 {
17840 }
17842 /* Return whether we should mitigatate Straight Line Speculation for the BLR
17843 instruction. */
17844 bool
17846 {
17848 }
17850 /* As of yet we only allow setting these options globally, in the future we may
17851 allow setting them per function. */
17852 static void
17854 {
17859 {
17862 }
17864 {
17867 }
17876 {
17882 {
17885 }
17886 else
17887 {
17890 }
17892 }
17895 }
17897 /* Parses CONST_STR for branch protection features specified in
17898 aarch64_branch_protect_types, and set any global variables required. Returns
17899 the parsing result and assigns LAST_STR to the last processed token from
17900 CONST_STR so that it can be used for error reporting. */
17902 static enum
17905 {
17912 else
17913 {
17915 /* Reset the branch protection features to their defaults. */
17919 {
17922 /* Search for this type. */
17924 {
17926 {
17931 }
17932 else
17933 type++;
17934 }
17936 {
17938 /* Loop through each token until we find one that isn't a
17939 subtype. */
17941 {
17944 /* Search for the subtype. */
17947 {
17949 {
17954 }
17955 else
17956 subtype++;
17957 }
17958 }
17959 }
17962 }
17963 }
17964 /* Copy the last processed token into the argument to pass it back.
17965 Used by option and attribute validation to print the offending token. */
17967 {
17970 }
17972 {
17973 /* If needed, alloc the accepted string then copy in const_str.
17974 Used by override_option_after_change_1. */
17977 BRANCH_PROTECT_STR_MAX
17981 /* Forcibly null-terminate. */
17983 }
17985 }
17987 static bool
17989 {
17999 }
18001 /* Validate a command-line -march option. Parse the arch and extensions
18002 (if any) specified in STR and throw errors if appropriate. Put the
18003 results, if they are valid, in RES and ISA_FLAGS. Return whether the
18004 option is valid. */
18006 static bool
18009 {
18011 enum aarch64_parse_opt_result parse_res
18018 {
18033 }
18036 }
18038 /* Validate a command-line -mtune option. Parse the cpu
18039 specified in STR and throw errors if appropriate. Put the
18040 result, if it is valid, in RES. Return whether the option is
18041 valid. */
18043 static bool
18045 {
18046 enum aarch64_parse_opt_result parse_res
18053 {
18063 }
18065 }
18067 /* Return the VG value associated with -msve-vector-bits= value VALUE. */
18069 static poly_uint16
18071 {
18072 /* 128-bit SVE and Advanced SIMD modes use different register layouts
18073 on big-endian targets, so we would need to forbid subregs that convert
18074 from one to the other. By default a reinterpret sequence would then
18075 involve a store to memory in one mode and a load back in the other.
18076 Even if we optimize that sequence using reverse instructions,
18077 it would still be a significant potential overhead.
18079 For now, it seems better to generate length-agnostic code for that
18080 case instead. */
18084 else
18086 }
18088 /* Implement TARGET_OPTION_OVERRIDE. This is called once in the beginning
18089 and is used to parse the -m{cpu,tune,arch} strings and setup the initial
18090 tuning structs. In particular it must set selected_tune and
18091 aarch64_isa_flags that define the available ISA features and tuning
18092 decisions. It must also set selected_arch as this will be used to
18093 output the .arch asm tags for each function. */
18095 static void
18097 {
18112 /* -mcpu=CPU is shorthand for -march=ARCH_FOR_CPU, -mtune=CPU.
18113 If either of -march or -mtune is given, they override their
18114 respective component of -mcpu. */
18124 #ifdef SUBTARGET_OVERRIDE_OPTIONS
18125 SUBTARGET_OVERRIDE_OPTIONS;
18126 #endif
18129 {
18130 /* If both -mcpu and -march are specified, warn if they are not
18131 architecturally compatible and prefer the -march ISA flags. */
18133 {
18135 aarch64_cpu_string,
18136 aarch64_arch_string);
18137 }
18141 }
18143 {
18146 }
18148 {
18152 }
18153 else
18154 {
18155 /* No -mcpu or -march specified, so use the default CPU. */
18159 }
18164 {
18165 #ifdef TARGET_ENABLE_BTI
18167 #else
18169 #endif
18170 }
18172 /* Return address signing is currently not supported for ILP32 targets. For
18173 LP64 targets use the configured option in the absence of a command-line
18174 option for -mbranch-protection. */
18176 {
18177 #ifdef TARGET_ENABLE_PAC_RET
18179 #else
18181 #endif
18182 }
18184 #ifndef HAVE_AS_MABI_OPTION
18185 /* The compiler may have been configured with 2.23.* binutils, which does
18186 not have support for ILP32. */
18189 #endif
18191 /* Convert -msve-vector-bits to a VG count. */
18197 /* The pass to insert speculation tracking runs before
18198 shrink-wrapping and the latter does not know how to update the
18199 tracking status. So disable it in this case. */
18205 /* Save these options as the default ones in case we push and pop them later
18206 while processing functions with potential target attributes. */
18207 target_option_default_node = target_option_current_node
18209 }
18211 /* Implement targetm.override_options_after_change. */
18213 static void
18215 {
18217 }
18219 /* Implement the TARGET_OFFLOAD_OPTIONS hook. */
18222 {
18225 else
18227 }
18231 {
18235 }
18237 void
18239 {
18241 }
18243 /* A checking mechanism for the implementation of the various code models. */
18244 static void
18246 {
18249 {
18256 {
18257 #ifdef HAVE_AS_SMALL_PIC_RELOCS
18259 ? AARCH64_CMODEL_SMALL_PIC
18261 #else
18263 #endif
18264 }
18277 }
18278 }
18280 /* Implements TARGET_OPTION_RESTORE. Restore the backend codegen decisions
18281 using the information saved in PTR. */
18283 static void
18287 {
18289 }
18291 /* Implement TARGET_OPTION_PRINT. */
18293 static void
18295 {
18306 }
18310 void
18312 {
18314 }
18316 /* Restore or save the TREE_TARGET_GLOBALS from or to NEW_TREE.
18317 Used by aarch64_set_current_function and aarch64_pragma_target_parse to
18318 make sure optab availability predicates are recomputed when necessary. */
18320 void
18322 {
18327 else
18329 }
18331 /* Implement TARGET_SET_CURRENT_FUNCTION. Unpack the codegen decisions
18332 like tuning and ISA features from the DECL_FUNCTION_SPECIFIC_TARGET
18333 of the function, if such exists. This function may be called multiple
18334 times on a single function so use aarch64_previous_fndecl to avoid
18335 setting up identical state. */
18337 static void
18339 {
18343 tree old_tree = (aarch64_previous_fndecl
18349 /* If current function has no attributes but the previous one did,
18350 use the default node. */
18354 /* If nothing to do, return. #pragma GCC reset or #pragma GCC pop to
18355 the default have been handled by aarch64_save_restore_target_globals from
18356 aarch64_pragma_target_parse. */
18362 /* First set the target options. */
18367 }
18369 /* Enum describing the various ways we can handle attributes.
18370 In many cases we can reuse the generic option handling machinery. */
18372 enum aarch64_attr_opt_type
18373 {
18377 aarch64_attr_custom /* Attribute requires a custom handling function. */
18378 };
18380 /* All the information needed to handle a target attribute.
18381 NAME is the name of the attribute.
18382 ATTR_TYPE specifies the type of behavior of the attribute as described
18383 in the definition of enum aarch64_attr_opt_type.
18384 ALLOW_NEG is true if the attribute supports a "no-" form.
18385 HANDLER is the function that takes the attribute string as an argument
18386 It is needed only when the ATTR_TYPE is aarch64_attr_custom.
18387 OPT_NUM is the enum specifying the option that the attribute modifies.
18388 This is needed for attributes that mirror the behavior of a command-line
18389 option, that is it has ATTR_TYPE aarch64_attr_mask, aarch64_attr_bool or
18390 aarch64_attr_enum. */
18392 struct aarch64_attribute_info
18393 {
18399 };
18401 /* Handle the ARCH_STR argument to the arch= target attribute. */
18403 static bool
18405 {
18408 enum aarch64_parse_opt_result parse_res
18412 {
18416 }
18419 {
18434 }
18437 }
18439 /* Handle the argument CPU_STR to the cpu= target attribute. */
18441 static bool
18443 {
18446 enum aarch64_parse_opt_result parse_res
18450 {
18455 }
18458 {
18473 }
18476 }
18478 /* Handle the argument STR to the branch-protection= attribute. */
18480 static bool
18482 {
18488 {
18499 /* Fall through. */
18504 }
18507 }
18509 /* Handle the argument STR to the tune= target attribute. */
18511 static bool
18513 {
18515 enum aarch64_parse_opt_result parse_res
18519 {
18523 }
18526 {
18533 }
18536 }
18538 /* Parse an architecture extensions target attribute string specified in STR.
18539 For example "+fp+nosimd". Show any errors if needed. Return TRUE
18540 if successful. Update aarch64_isa_flags to reflect the ISA features
18541 modified. */
18543 static bool
18545 {
18549 /* We allow "+nothing" in the beginning to clear out all architectural
18550 features if the user wants to handpick specific features. */
18552 {
18555 }
18561 {
18564 }
18567 {
18579 }
18582 }
18584 /* The target attributes that we support. On top of these we also support just
18585 ISA extensions, like __attribute__ ((target ("+crc"))), but that case is
18586 handled explicitly in aarch64_process_one_target_attr. */
18589 {
18591 OPT_mgeneral_regs_only },
18593 OPT_mfix_cortex_a53_835769 },
18595 OPT_mfix_cortex_a53_843419 },
18599 OPT_momit_leaf_frame_pointer },
18602 OPT_march_ },
18605 OPT_mtune_ },
18609 OPT_msign_return_address_ },
18611 OPT_moutline_atomics},
18613 };
18615 /* Parse ARG_STR which contains the definition of one target attribute.
18616 Show appropriate errors if any or return true if the attribute is valid. */
18618 static bool
18620 {
18626 {
18629 }
18634 /* We have something like __attribute__ ((target ("+fp+nosimd"))).
18635 It is easier to detect and handle it explicitly here rather than going
18636 through the machinery for the rest of the target attributes in this
18637 function. */
18642 {
18645 }
18648 /* If we found opt=foo then terminate STR_TO_CHECK at the '='
18649 and point ARG to "foo". */
18651 {
18653 arg++;
18654 }
18658 {
18659 /* If the names don't match up, or the user has given an argument
18660 to an attribute that doesn't accept one, or didn't give an argument
18661 to an attribute that expects one, fail to match. */
18670 {
18673 }
18675 /* If the name matches but the attribute does not allow "no-" versions
18676 then we can't match. */
18678 {
18681 }
18684 {
18685 /* Has a custom handler registered.
18686 For example, cpu=, arch=, tune=. */
18693 /* Either set or unset a boolean option. */
18695 {
18703 }
18704 /* Set or unset a bit in the target_flags. aarch64_handle_option
18705 should know what mask to apply given the option number. */
18707 {
18709 /* We only need to specify the option number.
18710 aarch64_handle_option will know which mask to apply. */
18716 }
18717 /* Use the option setting machinery to set an option to an enum. */
18719 {
18726 {
18729 global_dc);
18730 }
18731 else
18732 {
18734 }
18736 }
18739 }
18740 }
18742 /* If we reached here we either have found an attribute and validated
18743 it or didn't match any. If we matched an attribute but its arguments
18744 were malformed we will have returned false already. */
18746 }
18748 /* Count how many times the character C appears in
18749 NULL-terminated string STR. */
18751 static unsigned int
18753 {
18756 {
18758 res++;
18760 str++;
18761 }
18764 }
18766 /* Parse the tree in ARGS that contains the target attribute information
18767 and update the global target options space. */
18769 bool
18771 {
18773 {
18774 do
18775 {
18778 {
18781 }
18786 }
18789 {
18792 }
18799 {
18802 }
18804 /* Used to catch empty spaces between commas i.e.
18805 attribute ((target ("attr1,,attr2"))). */
18808 /* Handle multiple target attributes separated by ','. */
18813 {
18814 num_attrs++;
18816 {
18817 /* Check if token is possibly an arch extension without
18818 leading '+'. */
18821 enum aarch64_parse_opt_result ext_res
18826 token);
18827 else
18830 }
18833 }
18836 {
18839 }
18842 }
18844 /* Implement TARGET_OPTION_VALID_ATTRIBUTE_P. This is used to
18845 process attribute ((target ("..."))). */
18847 static bool
18849 {
18852 tree old_optimize;
18856 /* If what we're processing is the current pragma string then the
18857 target option node is already stored in target_option_current_node
18858 by aarch64_pragma_target_parse in aarch64-c.cc. Use that to avoid
18859 having to re-parse the string. This is especially useful to keep
18860 arm_neon.h compile times down since that header contains a lot
18861 of intrinsics enclosed in pragmas. */
18863 {
18866 }
18869 old_optimize
18873 /* If the function changed the optimization levels as well as setting
18874 target options, start with the optimizations specified. */
18879 /* Save the current target options to restore at the end. */
18882 /* If fndecl already has some target attributes applied to it, unpack
18883 them so that we add this attribute on top of them, rather than
18884 overwriting them. */
18886 {
18892 existing_options);
18893 }
18894 else
18900 /* Set up any additional state. */
18902 {
18904 /* Initialize SIMD builtins if we haven't already.
18905 Set current_target_pragma to NULL for the duration so that
18906 the builtin initialization code doesn't try to tag the functions
18907 being built with the attributes specified by any current pragma, thus
18908 going into an infinite recursion. */
18910 {
18915 }
18918 }
18919 else
18926 {
18931 }
18939 }
18941 /* Helper for aarch64_can_inline_p. In the case where CALLER and CALLEE are
18942 tri-bool options (yes, no, don't care) and the default value is
18943 DEF, determine whether to reject inlining. */
18945 static bool
18948 {
18949 /* If the callee doesn't care, always allow inlining. */
18953 /* If the caller doesn't care, always allow inlining. */
18957 /* Otherwise, allow inlining if either the callee and caller values
18958 agree, or if the callee is using the default value. */
18960 }
18962 /* Implement TARGET_CAN_INLINE_P. Decide whether it is valid
18963 to inline CALLEE into CALLER based on target-specific info.
18964 Make sure that the caller and callee have compatible architectural
18965 features. Then go through the other possible target attributes
18966 and see if they can block inlining. Try not to reject always_inline
18967 callees unless they are incompatible architecturally. */
18969 static bool
18971 {
18983 /* Callee's ISA flags should be a subset of the caller's. */
18988 /* Allow non-strict aligned functions inlining into strict
18989 aligned ones. */
18999 /* If the architectural features match up and the callee is always_inline
19000 then the other attributes don't matter. */
19012 /* Honour explicit requests to workaround errata. */
19025 /* If the user explicitly specified -momit-leaf-frame-pointer for the
19026 caller and calle and they don't match up, reject inlining. */
19033 /* If the callee has specific tuning overrides, respect them. */
19038 /* If the user specified tuning override strings for the
19039 caller and callee and they don't match up, reject inlining.
19040 We just do a string compare here, we don't analyze the meaning
19041 of the string, as it would be too costly for little gain. */
19049 }
19051 /* Return the ID of the TLDESC ABI, initializing the descriptor if hasn't
19052 been already. */
19054 unsigned int
19056 {
19059 {
19060 HARD_REG_SET full_reg_clobbers;
19067 }
19069 }
19071 /* Return true if SYMBOL_REF X binds locally. */
19073 static bool
19075 {
19079 }
19081 /* Return true if SYMBOL_REF X is thread local */
19082 static bool
19084 {
19093 }
19095 /* Classify a TLS symbol into one of the TLS kinds. */
19096 enum aarch64_symbol_type
19098 {
19102 {
19109 {
19115 }
19126 else
19135 }
19136 }
19138 /* Return the correct method for accessing X + OFFSET, where X is either
19139 a SYMBOL_REF or LABEL_REF. */
19141 enum aarch64_symbol_type
19143 {
19147 {
19149 {
19164 }
19165 }
19168 {
19173 {
19176 /* With -fPIC non-local symbols use the GOT. For orthogonality
19177 always use the GOT for extern weak symbols. */
19182 /* When we retrieve symbol + offset address, we have to make sure
19183 the offset does not cause overflow of the final address. But
19184 we have no way of knowing the address of symbol at compile time
19185 so we can't accurately say if the distance between the PC and
19186 symbol + offset is outside the addressible range of +/-1MB in the
19187 TINY code model. So we limit the maximum offset to +/-64KB and
19188 assume the offset to the symbol is not larger than +/-(1MB - 64KB).
19189 If offset_within_block_p is true we allow larger offsets. */
19205 /* Same reasoning as the tiny code model, but the offset cap here is
19206 1MB, allowing +/-3.9GB for the offset to the symbol. */
19214 /* This is alright even in PIC code as the constant
19215 pool reference is always PC relative and within
19216 the same translation unit. */
19219 else
19224 }
19225 }
19227 /* By default push everything into the constant pool. */
19229 }
19231 bool
19233 {
19235 }
19237 bool
19239 {
19240 poly_int64 offset;
19246 }
19248 /* Implement TARGET_LEGITIMATE_CONSTANT_P hook. Return true for constants
19249 that should be rematerialized rather than spilled. */
19251 static bool
19253 {
19254 /* Support CSE and rematerialization of common constants. */
19259 /* Only accept variable-length vector constants if they can be
19260 handled directly.
19262 ??? It would be possible (but complex) to handle rematerialization
19263 of other constants via secondary reloads. */
19267 /* Otherwise, accept any CONST_VECTOR that, if all else fails, can at
19268 least be forced to memory and loaded from there. */
19272 /* Do not allow vector struct mode constants for Advanced SIMD.
19273 We could support 0 and -1 easily, but they need support in
19274 aarch64-simd.md. */
19282 /* Accept polynomial constants that can be calculated by using the
19283 destination of a move as the sole temporary. Constants that
19284 require a second temporary cannot be rematerialized (they can't be
19285 forced to memory and also aren't legitimate constants). */
19286 poly_int64 offset;
19290 /* If an offset is being added to something else, we need to allow the
19291 base to be moved into the destination register, meaning that there
19292 are no free temporaries for the offset. */
19297 /* Do not allow const (plus (anchor_symbol, const_int)). */
19301 /* Treat symbols as constants. Avoid TLS symbols as they are complex,
19302 so spilling them is better than rematerialization. */
19306 /* Label references are always constant. */
19311 }
19313 rtx
19315 {
19321 /* Can return in any reg. */
19324 }
19326 /* On AAPCS systems, this is the "struct __va_list". */
19329 /* Implement TARGET_BUILD_BUILTIN_VA_LIST.
19330 Return the type to use as __builtin_va_list.
19332 AAPCS64 \S 7.1.4 requires that va_list be a typedef for a type defined as:
19334 struct __va_list
19335 {
19336 void *__stack;
19337 void *__gr_top;
19338 void *__vr_top;
19339 int __gr_offs;
19340 int __vr_offs;
19341 }; */
19343 static tree
19345 {
19346 tree va_list_name;
19349 /* Create the type. */
19351 /* Give it the required name. */
19353 TYPE_DECL,
19355 va_list_type);
19360 /* Create the fields. */
19363 ptr_type_node);
19366 ptr_type_node);
19369 ptr_type_node);
19372 integer_type_node);
19375 integer_type_node);
19377 /* Tell tree-stdarg pass about our internal offset fields.
19378 NOTE: va_list_gpr/fpr_counter_field are only used for tree comparision
19379 purpose to identify whether the code is updating va_list internal
19380 offset fields through irregular way. */
19402 /* Compute its layout. */
19406 }
19408 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */
19409 static void
19411 {
19415 tree t;
19429 {
19432 }
19441 NULL_TREE);
19443 NULL_TREE);
19445 NULL_TREE);
19447 NULL_TREE);
19449 NULL_TREE);
19451 /* Emit code to initialize STACK, which points to the next varargs stack
19452 argument. CUM->AAPCS_STACK_SIZE gives the number of stack words used
19453 by named arguments. STACK is 8-byte aligned. */
19460 /* Emit code to initialize GRTOP, the top of the GR save area.
19461 virtual_incoming_args_rtx should have been 16 byte aligned. */
19466 /* Emit code to initialize VRTOP, the top of the VR save area.
19467 This address is gr_save_area_bytes below GRTOP, rounded
19468 down to the next 16-byte boundary. */
19478 /* Emit code to initialize GROFF, the offset from GRTOP of the
19479 next GPR argument. */
19484 /* Likewise emit code to initialize VROFF, the offset from FTOP
19485 of the next VR argument. */
19489 }
19491 /* Implement TARGET_GIMPLIFY_VA_ARG_EXPR. */
19493 static tree
19496 {
19497 tree addr;
19503 machine_mode mode;
19527 align
19534 {
19535 /* No frontends can create types with variable-sized modes, so we
19536 shouldn't be asked to pass or return them. */
19539 /* TYPE passed in fp/simd registers. */
19551 {
19554 }
19557 {
19559 }
19560 }
19561 else
19562 {
19563 /* TYPE passed in general registers. */
19572 {
19577 }
19581 {
19583 }
19584 }
19586 /* Get a local temporary for the field value. */
19589 /* Emit code to branch if off >= 0. */
19595 {
19596 /* Emit: offs = (offs + 15) & -16. */
19602 }
19603 else
19606 /* Update ap.__[g|v]r_offs */
19611 /* String up. */
19615 /* [cond2] if (ap.__[g|v]r_offs > 0) */
19620 /* String up: make sure the assignment happens before the use. */
19624 /* Prepare the trees handling the argument that is passed on the stack;
19625 the top level node will store in ON_STACK. */
19628 {
19629 /* if (alignof(type) > 8) (arg = arg + 15) & -16; */
19634 }
19635 else
19637 /* Advance ap.__stack */
19642 /* String up roundup and advance. */
19645 /* String up with arg */
19647 /* Big-endianness related address adjustment. */
19650 {
19654 }
19659 /* Adjustment to OFFSET in the case of BIG_ENDIAN. */
19669 {
19670 /* type ha; // treat as "struct {ftype field[n];}"
19671 ... [computing offs]
19672 for (i = 0; i <nregs; ++i, offs += 16)
19673 ha.field[i] = *((ftype *)(ap.__vr_top + offs));
19674 return ha; */
19678 /* Declare a local variable. */
19682 /* Establish the base type. */
19684 {
19719 {
19723 }
19727 }
19729 /* *(field_ptr_t)&ha = *((field_ptr_t)vr_saved_area */
19738 /* ha.field[i] = *((field_ptr_t)vr_saved_area + i) */
19740 {
19750 }
19754 }
19764 }
19766 /* Implement TARGET_SETUP_INCOMING_VARARGS. */
19768 static void
19772 {
19774 CUMULATIVE_ARGS local_cum;
19778 /* The caller has advanced CUM up to, but not beyond, the last named
19779 argument. Advance a local copy of CUM past the last "real" named
19780 argument, to find out how many registers are left over. */
19784 /* Found out how many registers we need to save.
19785 Honor tree-stdvar analysis results. */
19794 {
19797 }
19800 {
19802 {
19805 /* virtual_incoming_args_rtx should have been 16-byte aligned. */
19813 }
19815 {
19816 /* We can't use move_block_from_reg, because it will use
19817 the wrong mode, storing D regs only. */
19821 /* Set OFF to the offset from virtual_incoming_args_rtx of
19822 the first vector register. The VR save area lies below
19823 the GR one, and is aligned to 16 bytes. */
19830 {
19838 }
19839 }
19840 }
19842 /* We don't save the size into *PRETEND_SIZE because we want to avoid
19843 any complication of having crtl->args.pretend_args_size changed. */
19848 }
19850 static void
19852 {
19855 {
19857 {
19860 }
19861 }
19864 {
19867 }
19869 /* Only allow the FFR and FFRT to be accessed via special patterns. */
19873 /* When tracking speculation, we need a couple of call-clobbered registers
19874 to track the speculation state. It would be nice to just use
19875 IP0 and IP1, but currently there are numerous places that just
19876 assume these registers are free for other uses (eg pointer
19877 authentication). */
19879 {
19884 }
19885 }
19887 /* Implement TARGET_MEMBER_TYPE_FORCES_BLK. */
19889 bool
19891 {
19892 /* For records we're passed a FIELD_DECL, for arrays we're passed
19893 an ARRAY_TYPE. In both cases we're interested in the TREE_TYPE. */
19896 /* Assign BLKmode to anything that contains multiple SVE predicates.
19897 For structures, the "multiple" case is indicated by MODE being
19898 VOIDmode. */
19901 {
19906 }
19909 }
19911 /* Bitmasks that indicate whether earlier versions of GCC would have
19912 taken a different path through the ABI logic. This should result in
19913 a -Wpsabi warning if the earlier path led to a different ABI decision.
19915 WARN_PSABI_EMPTY_CXX17_BASE
19916 Indicates that the type includes an artificial empty C++17 base field
19917 that, prior to GCC 10.1, would prevent the type from being treated as
19918 a HFA or HVA. See PR94383 for details.
19920 WARN_PSABI_NO_UNIQUE_ADDRESS
19921 Indicates that the type includes an empty [[no_unique_address]] field
19922 that, prior to GCC 10.1, would prevent the type from being treated as
19923 a HFA or HVA. */
19928 /* Walk down the type tree of TYPE counting consecutive base elements.
19929 If *MODEP is VOIDmode, then set it to the first valid floating point
19930 type. If a non-floating point type is found, or if a floating point
19931 type that doesn't match a non-VOIDmode *MODEP is found, then return -1,
19932 otherwise return the count in the sub-tree.
19934 The WARN_PSABI_FLAGS argument allows the caller to check whether this
19935 function has changed its behavior relative to earlier versions of GCC.
19936 Normally the argument should be nonnull and point to a zero-initialized
19937 variable. The function then records whether the ABI decision might
19938 be affected by a known fix to the ABI logic, setting the associated
19939 WARN_PSABI_* bits if so.
19941 When the argument is instead a null pointer, the function tries to
19942 simulate the behavior of GCC before all such ABI fixes were made.
19943 This is useful to check whether the function returns something
19944 different after the ABI fixes. */
19945 static int
19948 {
19949 machine_mode mode;
19950 HOST_WIDE_INT size;
19956 {
19987 /* Use V2SImode and V4SImode as representatives of all 64-bit
19988 and 128-bit vector types. */
19991 {
20000 }
20005 /* Vector modes are considered to be opaque: two vectors are
20006 equivalent for the purposes of being homogeneous aggregates
20007 if they are the same size. */
20014 {
20018 /* Can't handle incomplete types nor sizes that are not
20019 fixed. */
20025 warn_psabi_flags);
20027 || !index
20038 /* There must be no padding. */
20044 }
20047 {
20050 tree field;
20052 /* Can't handle incomplete types nor sizes that are not
20053 fixed. */
20059 {
20064 {
20065 /* See whether this is something that earlier versions of
20066 GCC failed to ignore. */
20073 else
20074 /* No compatibility problem. */
20077 /* Simulate the old behavior when WARN_PSABI_FLAGS is null. */
20079 {
20082 }
20083 }
20084 /* A zero-width bitfield may affect layout in some
20085 circumstances, but adds no members. The determination
20086 of whether or not a type is an HFA is performed after
20087 layout is complete, so if the type still looks like an
20088 HFA afterwards, it is still classed as one. This is
20089 potentially an ABI break for the hard-float ABI. */
20092 {
20093 /* Prior to GCC-12 these fields were striped early,
20094 hiding them from the back-end entirely and
20095 resulting in the correct behaviour for argument
20096 passing. Simulate that old behaviour without
20097 generating a warning. */
20101 {
20104 }
20105 }
20108 warn_psabi_flags);
20112 }
20114 /* There must be no padding. */
20120 }
20124 {
20125 /* These aren't very interesting except in a degenerate case. */
20128 tree field;
20130 /* Can't handle incomplete types nor sizes that are not
20131 fixed. */
20137 {
20142 warn_psabi_flags);
20146 }
20148 /* There must be no padding. */
20154 }
20158 }
20161 }
20163 /* Return TRUE if the type, as described by TYPE and MODE, is a short vector
20164 type as described in AAPCS64 \S 4.1.2.
20166 See the comment above aarch64_composite_type_p for the notes on MODE. */
20168 static bool
20170 machine_mode mode)
20171 {
20175 {
20179 }
20182 {
20183 /* The containing "else if" is too loose: it means that we look at TYPE
20184 if the type is a vector type (good), but that we otherwise ignore TYPE
20185 and look only at the mode. This is wrong because the type describes
20186 the language-level information whereas the mode is purely an internal
20187 GCC concept. We can therefore reach here for types that are not
20188 vectors in the AAPCS64 sense.
20190 We can't "fix" that for the traditional Advanced SIMD vector modes
20191 without breaking backwards compatibility. However, there's no such
20192 baggage for the structure modes, which were introduced in GCC 12. */
20196 /* For similar reasons, rely only on the type, not the mode, when
20197 processing SVE types. */
20199 /* Leave later code to report an error if SVE is disabled. */
20201 else
20203 }
20205 {
20206 /* 64-bit and 128-bit vectors should only acquire an SVE mode if
20207 they are being treated as scalable AAPCS64 types. */
20211 }
20213 }
20215 /* Return TRUE if the type, as described by TYPE and MODE, is a composite
20216 type as described in AAPCS64 \S 4.3. This includes aggregate, union and
20217 array types. The C99 floating-point complex types are also considered
20218 as composite types, according to AAPCS64 \S 7.1.1. The complex integer
20219 types, which are GCC extensions and out of the scope of AAPCS64, are
20220 treated as composite types here as well.
20222 Note that MODE itself is not sufficient in determining whether a type
20223 is such a composite type or not. This is because
20224 stor-layout.cc:compute_record_mode may have already changed the MODE
20225 (BLKmode) of a RECORD_TYPE TYPE to some other mode. For example, a
20226 structure with only one field may have its MODE set to the mode of the
20227 field. Also an integer mode whose size matches the size of the
20228 RECORD_TYPE type may be used to substitute the original mode
20229 (i.e. BLKmode) in certain circumstances. In other words, MODE cannot be
20230 solely relied on. */
20232 static bool
20234 machine_mode mode)
20235 {
20248 }
20250 /* Return TRUE if an argument, whose type is described by TYPE and MODE,
20251 shall be passed or returned in simd/fp register(s) (providing these
20252 parameter passing registers are available).
20254 Upon successful return, *COUNT returns the number of needed registers,
20255 *BASE_MODE returns the mode of the individual register and when IS_HA
20256 is not NULL, *IS_HA indicates whether or not the argument is a homogeneous
20257 floating-point aggregate or a homogeneous short-vector aggregate.
20259 SILENT_P is true if the function should refrain from reporting any
20260 diagnostics. This should only be used if the caller is certain that
20261 any ABI decisions would eventually come through this function with
20262 SILENT_P set to false. */
20264 static bool
20266 const_tree type,
20271 {
20281 {
20284 }
20286 {
20290 }
20292 {
20297 {
20302 && warn_psabi
20303 && warn_psabi_flags
20307 {
20314 /* Use TYPE_MAIN_VARIANT to strip any redundant const
20315 qualification. */
20318 "type %qT with %<[[no_unique_address]]%> members "
20323 "type %qT when C++17 is enabled changed to match "
20330 }
20334 }
20335 else
20337 }
20338 else
20344 }
20346 /* Implement TARGET_STRUCT_VALUE_RTX. */
20348 static rtx
20351 {
20353 }
20355 /* Implements target hook vector_mode_supported_p. */
20356 static bool
20358 {
20361 }
20363 /* Return the full-width SVE vector mode for element mode MODE, if one
20364 exists. */
20365 opt_machine_mode
20367 {
20369 {
20388 }
20389 }
20391 /* Return the 128-bit Advanced SIMD vector mode for element mode MODE,
20392 if it exists. */
20393 opt_machine_mode
20395 {
20397 {
20416 }
20417 }
20419 /* Return appropriate SIMD container
20420 for MODE within a vector of WIDTH bits. */
20421 static machine_mode
20423 {
20431 {
20434 else
20436 {
20451 }
20452 }
20454 }
20456 /* Compare an SVE mode SVE_M and an Advanced SIMD mode ASIMD_M
20457 and return whether the SVE mode should be preferred over the
20458 Advanced SIMD one in aarch64_autovectorize_vector_modes. */
20459 static bool
20461 {
20462 /* Take into account the aarch64-autovec-preference param if non-zero. */
20471 /* The preference in case of a tie in costs. */
20477 /* If the CPU information does not have an SVE width registered use the
20478 generic poly_int comparison that prefers SVE. If a preference is
20479 explicitly requested avoid this path. */
20481 && !prefer_asimd
20485 /* Otherwise estimate the runtime width of the modes involved. */
20489 /* Preferring SVE means picking it first unless the Advanced SIMD mode
20490 is clearly wider. */
20493 /* Conversely, preferring Advanced SIMD means picking SVE only if SVE
20494 is clearly wider. */
20498 /* In the default case prefer Advanced SIMD over SVE in case of a tie. */
20500 }
20502 /* Return 128-bit container as the preferred SIMD mode for MODE. */
20503 static machine_mode
20505 {
20506 /* Take into account explicit auto-vectorization ISA preferences through
20507 aarch64_cmp_autovec_modes. */
20513 }
20515 /* Return a list of possible vector sizes for the vectorizer
20516 to iterate over. */
20517 static unsigned int
20519 {
20521 /* Try using full vectors for all element types. */
20522 VNx16QImode,
20524 /* Try using 16-bit containers for 8-bit elements and full vectors
20525 for wider elements. */
20526 VNx8QImode,
20528 /* Try using 32-bit containers for 8-bit and 16-bit elements and
20529 full vectors for wider elements. */
20530 VNx4QImode,
20532 /* Try using 64-bit containers for all element types. */
20533 VNx2QImode
20534 };
20537 /* Try using 128-bit vectors for all element types. */
20538 V16QImode,
20540 /* Try using 64-bit vectors for 8-bit elements and 128-bit vectors
20541 for wider elements. */
20542 V8QImode,
20544 /* Try using 64-bit vectors for 16-bit elements and 128-bit vectors
20545 for wider elements.
20547 TODO: We could support a limited form of V4QImode too, so that
20548 we use 32-bit vectors for 8-bit elements. */
20549 V4HImode,
20551 /* Try using 64-bit vectors for 32-bit elements and 128-bit vectors
20552 for 64-bit elements.
20554 TODO: We could similarly support limited forms of V2QImode and V2HImode
20555 for this case. */
20556 V2SImode
20557 };
20559 /* Try using N-byte SVE modes only after trying N-byte Advanced SIMD mode.
20560 This is because:
20562 - If we can't use N-byte Advanced SIMD vectors then the placement
20563 doesn't matter; we'll just continue as though the Advanced SIMD
20564 entry didn't exist.
20566 - If an SVE main loop with N bytes ends up being cheaper than an
20567 Advanced SIMD main loop with N bytes then by default we'll replace
20568 the Advanced SIMD version with the SVE one.
20570 - If an Advanced SIMD main loop with N bytes ends up being cheaper
20571 than an SVE main loop with N bytes then by default we'll try to
20572 use the SVE loop to vectorize the epilogue instead. */
20581 {
20586 else
20588 }
20593 /* Consider enabling VECT_COMPARE_COSTS for SVE, both so that we
20594 can compare SVE against Advanced SIMD and so that we can compare
20595 multiple SVE vectorization approaches against each other. There's
20596 not really any point doing this for Advanced SIMD only, since the
20597 first mode that works should always be the best. */
20601 }
20603 /* Implement TARGET_MANGLE_TYPE. */
20607 {
20608 /* The AArch64 ABI documents say that "__va_list" has to be
20609 mangled as if it is in the "std" namespace. */
20613 /* Half-precision floating point types. */
20615 {
20618 else
20620 }
20622 /* Mangle AArch64-specific internal types. TYPE_NAME is non-NULL_TREE for
20623 builtin types. */
20625 {
20630 }
20632 /* Use the default mangling. */
20634 }
20636 /* Implement TARGET_VERIFY_TYPE_CONTEXT. */
20638 static bool
20641 {
20643 }
20645 /* Find the first rtx_insn before insn that will generate an assembly
20646 instruction. */
20650 {
20654 do
20655 {
20657 }
20661 }
20663 static bool
20665 {
20667 /* A number of these may be AArch32 only. */
20672 };
20675 {
20678 }
20681 }
20683 /* Check if there is a register dependency between a load and the insn
20684 for which we hold recog_data. */
20686 static bool
20688 {
20689 rtx load_reg;
20699 {
20705 }
20707 }
20710 /* When working around the Cortex-A53 erratum 835769,
20711 given rtx_insn INSN, return true if it is a 64-bit multiply-accumulate
20712 instruction and has a preceding memory instruction such that a NOP
20713 should be inserted between them. */
20715 bool
20717 {
20720 rtx body;
20733 /* aarch64_prev_real_insn can call recog_memoized on insns other than INSN.
20734 Restore recog state to INSN to avoid state corruption. */
20742 /* If the previous insn is a memory op and there is no dependency between
20743 it and the DImode madd, emit a NOP between them. If body is NULL then we
20744 have a complex memory operation, probably a load/store pair.
20745 Be conservative for now and emit a NOP. */
20752 }
20755 /* Implement FINAL_PRESCAN_INSN. */
20757 void
20759 {
20762 }
20765 /* Return true if BASE_OR_STEP is a valid immediate operand for an SVE INDEX
20766 instruction. */
20768 bool
20770 {
20773 }
20775 /* Return true if X is a valid immediate for the SVE ADD and SUB instructions
20776 when applied to mode MODE. Negate X first if NEGATE_P is true. */
20778 bool
20780 {
20793 }
20795 /* Return true if X is a valid immediate for the SVE SQADD and SQSUB
20796 instructions when applied to mode MODE. Negate X first if NEGATE_P
20797 is true. */
20799 bool
20801 {
20805 /* After the optional negation, the immediate must be nonnegative.
20806 E.g. a saturating add of -127 must be done via SQSUB Zn.B, Zn.B, #127
20807 instead of SQADD Zn.B, Zn.B, #129. */
20810 }
20812 /* Return true if X is a valid immediate operand for an SVE logical
20813 instruction such as AND. */
20815 bool
20817 {
20818 rtx elt;
20824 }
20826 /* Return true if X is a valid immediate for the SVE DUP and CPY
20827 instructions. */
20829 bool
20831 {
20840 }
20842 /* Return true if X is a valid immediate operand for an SVE CMP instruction.
20843 SIGNED_P says whether the operand is signed rather than unsigned. */
20845 bool
20847 {
20850 && (signed_p
20853 }
20855 /* Return true if X is a valid immediate operand for an SVE FADD or FSUB
20856 instruction. Negate X first if NEGATE_P is true. */
20858 bool
20860 {
20861 rtx elt;
20862 REAL_VALUE_TYPE r;
20878 }
20880 /* Return true if X is a valid immediate operand for an SVE FMUL
20881 instruction. */
20883 bool
20885 {
20886 rtx elt;
20892 }
20894 /* Return true if replicating VAL32 is a valid 2-byte or 4-byte immediate
20895 for the Advanced SIMD operation described by WHICH and INSN. If INFO
20896 is nonnull, use it to describe valid immediates. */
20897 static bool
20902 {
20903 /* Try a 4-byte immediate with LSL. */
20906 {
20911 }
20913 /* Try a 2-byte immediate with LSL. */
20918 {
20923 }
20925 /* Try a 4-byte immediate with MSL, except for cases that MVN
20926 can handle. */
20929 {
20932 {
20937 }
20938 }
20941 }
20943 /* Return true if replicating VAL64 is a valid immediate for the
20944 Advanced SIMD operation described by WHICH. If INFO is nonnull,
20945 use it to describe valid immediates. */
20946 static bool
20950 {
20956 {
20967 /* Try using a replicated byte. */
20971 {
20975 }
20976 }
20978 /* Try using a bit-to-bytemask. */
20980 {
20983 {
20987 }
20989 {
20993 }
20994 }
20996 }
20998 /* Return true if replicating VAL64 gives a valid immediate for an SVE MOV
20999 instruction. If INFO is nonnull, use it to describe valid immediates. */
21001 static bool
21004 {
21008 {
21012 {
21017 }
21018 }
21021 {
21022 /* DUP with no shift. */
21026 }
21028 {
21029 /* DUP with LSL #8. */
21033 }
21035 {
21036 /* DUPM. */
21040 }
21042 }
21044 /* Return true if X is an UNSPEC_PTRUE constant of the form:
21046 (const (unspec [PATTERN ZERO] UNSPEC_PTRUE))
21048 where PATTERN is the svpattern as a CONST_INT and where ZERO
21049 is a zero constant of the required PTRUE mode (which can have
21050 fewer elements than X's mode, if zero bits are significant).
21052 If so, and if INFO is nonnull, describe the immediate in INFO. */
21053 bool
21055 {
21064 {
21065 aarch64_svpattern pattern
21070 }
21072 }
21074 /* Return true if X is a valid SVE predicate. If INFO is nonnull, use
21075 it to describe valid immediates. */
21077 static bool
21079 {
21084 {
21088 }
21090 /* Analyze the value as a VNx16BImode. This should be relatively
21091 efficient, since rtx_vector_builder has enough built-in capacity
21092 to store all VLA predicate constants without needing the heap. */
21093 rtx_vector_builder builder;
21099 {
21103 {
21105 {
21108 }
21110 }
21111 }
21113 }
21115 /* Return true if OP is a valid SIMD immediate for the operation
21116 described by WHICH. If INFO is nonnull, use it to describe valid
21117 immediates. */
21118 bool
21121 {
21138 {
21145 {
21146 /* Get the corresponding container mode. E.g. an INDEX on V2SI
21147 should yield two integer values per 128-bit block, meaning
21148 that we need to treat it in the same way as V2DI and then
21149 ignore the upper 32 bits of each element. */
21152 }
21154 }
21158 else
21161 scalar_float_mode elt_float_mode;
21164 {
21168 {
21172 }
21173 }
21175 /* If all elements in an SVE vector have the same value, we have a free
21176 choice between using the element mode and using the container mode.
21177 Using the element mode means that unused parts of the vector are
21178 duplicates of the used elements, while using the container mode means
21179 that the unused parts are an extension of the used elements. Using the
21180 element mode is better for (say) VNx4HI 0x101, since 0x01010101 is valid
21181 for its container mode VNx4SI while 0x00000101 isn't.
21183 If not all elements in an SVE vector have the same value, we need the
21184 transition from one element to the next to occur at container boundaries.
21185 E.g. a fixed-length VNx4HI containing { 1, 2, 3, 4 } should be treated
21186 in the same way as a VNx4SI containing { 1, 2, 3, 4 }. */
21187 scalar_int_mode elt_int_mode;
21190 else
21197 /* Expand the vector constant out into a byte vector, with the least
21198 significant byte of the register first. */
21202 {
21203 /* The vector is provided in gcc endian-neutral fashion.
21204 For aarch64_be Advanced SIMD, it must be laid out in the vector
21205 register in reverse order. */
21217 {
21220 }
21221 }
21223 /* The immediate must repeat every eight bytes. */
21229 /* Get the repeating 8-byte value as an integer. No endian correction
21230 is needed here because bytes is already in lsb-first order. */
21238 else
21240 }
21242 /* Check whether X is a VEC_SERIES-like constant that starts at 0 and
21243 has a step in the range of INDEX. Return the index expression if so,
21244 otherwise return null. */
21245 rtx
21247 {
21254 }
21256 /* Check of immediate shift constants are within range. */
21257 bool
21259 {
21266 else
21268 }
21270 /* Return the bitmask CONST_INT to select the bits required by a zero extract
21271 operation of width WIDTH at bit position POS. */
21273 rtx
21275 {
21279 unsigned HOST_WIDE_INT mask
21282 }
21284 bool
21286 {
21295 {
21296 /* Require predicate constants to be VNx16BI before RA, so that we
21297 force everything to have a canonical form. */
21299 && !reload_completed
21305 }
21307 /* Remove UNSPEC_SALT_ADDR before checking symbol reference. */
21310 /* GOT accesses are valid moves. */
21323 }
21325 /* Create a 0 constant that is based on V4SI to allow CSE to optimally share
21326 the constant creation. */
21328 rtx
21330 {
21335 }
21337 /* Return a const_int vector of VAL. */
21338 rtx
21340 {
21343 }
21345 /* Check OP is a legal scalar immediate for the MOVI instruction. */
21347 bool
21349 {
21350 machine_mode vmode;
21355 }
21357 /* Construct and return a PARALLEL RTX vector with elements numbering the
21358 lanes of either the high (HIGH == TRUE) or low (HIGH == FALSE) half of
21359 the vector - from the perspective of the architecture. This does not
21360 line up with GCC's perspective on lane numbers, so we end up with
21361 different masks depending on our target endian-ness. The diagram
21362 below may help. We must draw the distinction when building masks
21363 which select one half of the vector. An instruction selecting
21364 architectural low-lanes for a big-endian target, must be described using
21365 a mask selecting GCC high-lanes.
21367 Big-Endian Little-Endian
21369 GCC 0 1 2 3 3 2 1 0
21370 | x | x | x | x | | x | x | x | x |
21371 Architecture 3 2 1 0 3 2 1 0
21373 Low Mask: { 2, 3 } { 0, 1 }
21374 High Mask: { 0, 1 } { 2, 3 }
21376 MODE Is the mode of the vector and NUNITS is the number of units in it. */
21378 rtx
21380 {
21385 rtx t1;
21390 else
21398 }
21400 /* Check OP for validity as a PARALLEL RTX vector with elements
21401 numbering the lanes of either the high (HIGH == TRUE) or low lanes,
21402 from the perspective of the architecture. See the diagram above
21403 aarch64_simd_vect_par_cnst_half for more details. */
21405 bool
21408 {
21422 {
21429 }
21431 }
21433 /* Return a PARALLEL containing NELTS elements, with element I equal
21434 to BASE + I * STEP. */
21436 rtx
21438 {
21443 }
21445 /* Return true if OP is a PARALLEL of CONST_INTs that form a linear
21446 series with step STEP. */
21448 bool
21450 {
21461 }
21463 /* Bounds-check lanes. Ensure OPERAND lies between LOW (inclusive) and
21464 HIGH (exclusive). */
21465 void
21467 const_tree exp)
21468 {
21469 HOST_WIDE_INT lane;
21474 {
21478 else
21480 }
21481 }
21483 /* Peform endian correction on lane number N, which indexes a vector
21484 of mode MODE, and return the result as an SImode rtx. */
21486 rtx
21488 {
21490 }
21492 /* Return TRUE if OP is a valid vector addressing mode. */
21494 bool
21496 {
21499 }
21501 /* Return true if OP is a valid MEM operand for an SVE LD1R instruction. */
21503 bool
21505 {
21507 scalar_mode mode;
21514 }
21516 /* Return true if OP is a valid MEM operand for an SVE LD1R{Q,O} instruction
21517 where the size of the read data is specified by `mode` and the size of the
21518 vector elements are specified by `elem_mode`. */
21519 bool
21521 scalar_mode elem_mode)
21522 {
21535 }
21537 /* Return true if OP is a valid MEM operand for an SVE LD1RQ instruction. */
21538 bool
21540 {
21543 }
21545 /* Return true if OP is a valid MEM operand for an SVE LD1RO instruction for
21546 accessing a vector where the element size is specified by `elem_mode`. */
21547 bool
21549 {
21551 }
21553 /* Return true if OP is a valid MEM operand for an SVE LDFF1 instruction. */
21554 bool
21556 {
21568 }
21570 /* Return true if OP is a valid MEM operand for an SVE LDNF1 instruction. */
21571 bool
21573 {
21580 }
21582 /* Return true if OP is a valid MEM operand for an SVE LDR instruction.
21583 The conditions for STR are the same. */
21584 bool
21586 {
21593 }
21595 /* Return true if OP is a valid address for an SVE PRF[BHWD] instruction,
21596 addressing memory of mode MODE. */
21597 bool
21599 {
21608 }
21610 /* Return true if OP is a valid MEM operand for an SVE_STRUCT mode.
21611 We need to be able to access the individual pieces, so the range
21612 is different from LD[234] and ST[234]. */
21613 bool
21615 {
21622 ADDR_QUERY_ANY)
21630 }
21632 /* Emit a register copy from operand to operand, taking care not to
21633 early-clobber source registers in the process.
21635 COUNT is the number of components into which the copy needs to be
21636 decomposed. */
21637 void
21640 {
21650 else
21654 }
21656 /* Compute and return the length of aarch64_simd_reglist<mode>, where <mode> is
21657 one of VSTRUCT modes: OI, CI, or XI. */
21658 int
21660 {
21661 /* This is only used (and only meaningful) for Advanced SIMD, not SVE. */
21663 }
21665 /* Implement target hook TARGET_VECTOR_ALIGNMENT. The AAPCS64 sets the maximum
21666 alignment of a vector to 128 bits. SVE predicates have an alignment of
21667 16 bits. */
21668 static HOST_WIDE_INT
21670 {
21671 /* ??? Checking the mode isn't ideal, but VECTOR_BOOLEAN_TYPE_P can
21672 be set for non-predicate vectors of booleans. Modes are the most
21673 direct way we have of identifying real SVE predicate types. */
21676 widest_int min_size
21679 }
21681 /* Implement target hook TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT. */
21682 static poly_uint64
21684 {
21686 {
21687 /* If the length of the vector is a fixed power of 2, try to align
21688 to that length, otherwise don't try to align at all. */
21689 HOST_WIDE_INT result;
21694 }
21696 }
21698 /* Implement target hook TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE. */
21699 static bool
21701 {
21705 /* For fixed-length vectors, check that the vectorizer will aim for
21706 full-vector alignment. This isn't true for generic GCC vectors
21707 that are wider than the ABI maximum of 128 bits. */
21708 poly_uint64 preferred_alignment =
21712 preferred_alignment))
21715 /* Vectors whose size is <= BIGGEST_ALIGNMENT are naturally aligned. */
21717 }
21719 /* Return true if the vector misalignment factor is supported by the
21720 target. */
21721 static bool
21725 {
21727 {
21728 /* Return if movmisalign pattern is not supported for this mode. */
21732 /* Misalignment factor is unknown at compile time. */
21735 }
21737 is_packed);
21738 }
21740 /* If VALS is a vector constant that can be loaded into a register
21741 using DUP, generate instructions to do so and return an RTX to
21742 assign to the register. Otherwise return NULL_RTX. */
21743 static rtx
21745 {
21748 rtx x;
21753 /* We can load this constant by using DUP and a constant in a
21754 single ARM register. This will be cheaper than a vector
21755 load. */
21758 }
21761 /* Generate code to load VALS, which is a PARALLEL containing only
21762 constants (for vec_init) or CONST_VECTOR, efficiently into a
21763 register. Returns an RTX to copy into the register, or NULL_RTX
21764 for a PARALLEL that cannot be converted into a CONST_VECTOR. */
21765 static rtx
21767 {
21769 rtx const_dup;
21777 {
21778 /* A CONST_VECTOR must contain only CONST_INTs and
21779 CONST_DOUBLEs, but CONSTANT_P allows more (e.g. SYMBOL_REF).
21780 Only store valid constants in a CONST_VECTOR. */
21783 {
21786 n_const++;
21787 }
21790 }
21791 else
21796 /* Load using MOVI/MVNI. */
21799 /* Loaded using DUP. */
21802 /* Load from constant pool. We cannot take advantage of single-cycle
21803 LD1 because we need a PC-relative addressing mode. */
21805 else
21806 /* A PARALLEL containing something not valid inside CONST_VECTOR.
21807 We cannot construct an initializer. */
21809 }
21811 /* Expand a vector initialisation sequence, such that TARGET is
21812 initialised to contain VALS. */
21814 void
21816 {
21819 /* The number of vector elements. */
21821 /* The number of vector elements which are not constant. */
21824 /* The first element of vals. */
21828 /* This is a special vec_init<M><N> where N is not an element mode but a
21829 vector mode with half the elements of M. We expect to find two entries
21830 of mode N in VALS and we must put their concatentation into TARGET. */
21832 {
21841 }
21843 /* Count the number of variable elements to initialise. */
21845 {
21849 else
21853 }
21855 /* No variable elements, hand off to aarch64_simd_make_constant which knows
21856 how best to handle this. */
21858 {
21861 {
21864 }
21865 }
21867 /* Splat a single non-constant element if we can. */
21869 {
21873 }
21878 /* If there are only variable elements, try to optimize
21879 the insertion using dup for the most common element
21880 followed by insertions. */
21882 /* The algorithm will fill matches[*][0] with the earliest matching element,
21883 and matches[X][1] with the count of duplicate elements (if X is the
21884 earliest element which has duplicates). */
21887 {
21890 {
21892 {
21894 {
21898 }
21899 }
21900 }
21905 {
21908 }
21910 /* Create a duplicate of the most common element, unless all elements
21911 are equally useless to us, in which case just immediately set the
21912 vector register using the first element. */
21915 {
21916 /* For vectors of two 64-bit elements, we can do even better. */
21921 {
21924 /* Combine can pick up this case, but handling it directly
21925 here leaves clearer RTL.
21927 This is load_pair_lanes<mode>, and also gives us a clean-up
21928 for store_pair_lanes<mode>. */
21932 {
21933 rtx t;
21936 else
21940 }
21941 }
21942 /* The subreg-move sequence below will move into lane zero of the
21943 vector register. For big-endian we want that position to hold
21944 the last element of VALS. */
21948 }
21949 else
21950 {
21953 }
21955 /* Insert the rest. */
21957 {
21963 }
21965 }
21967 /* Initialise a vector which is part-variable. We want to first try
21968 to build those lanes which are constant in the most efficient way we
21969 can. */
21971 {
21974 /* Load constant part of vector. We really don't care what goes into the
21975 parts we will overwrite, but we're more likely to be able to load the
21976 constant efficiently if it has fewer, larger, repeating parts
21977 (see aarch64_simd_valid_immediate). */
21979 {
21985 {
21986 /* Look in the copied vector, as more elements are const. */
21989 {
21992 }
21993 }
21995 }
21997 }
21999 /* Insert the variable lanes directly. */
22001 {
22007 }
22008 }
22010 /* Emit RTL corresponding to:
22011 insr TARGET, ELEM. */
22013 static void
22015 {
22023 }
22025 /* Subroutine of aarch64_sve_expand_vector_init for handling
22026 trailing constants.
22027 This function works as follows:
22028 (a) Create a new vector consisting of trailing constants.
22029 (b) Initialize TARGET with the constant vector using emit_move_insn.
22030 (c) Insert remaining elements in TARGET using insr.
22031 NELTS is the total number of elements in original vector while
22032 while NELTS_REQD is the number of elements that are actually
22033 significant.
22035 ??? The heuristic used is to do above only if number of constants
22036 is at least half the total number of elements. May need fine tuning. */
22038 static bool
22039 aarch64_sve_expand_vector_init_handle_trailing_constants
22041 {
22048 i--)
22049 n_trailing_constants++;
22052 {
22053 /* Try to use the natural pattern of BUILDER to extend the trailing
22054 constant elements to a full vector. Replace any variables in the
22055 extra elements with zeros.
22057 ??? It would be better if the builders supported "don't care"
22058 elements, with the builder filling in whichever elements
22059 give the most compact encoding. */
22062 {
22067 }
22075 }
22078 }
22080 /* Subroutine of aarch64_sve_expand_vector_init.
22081 Works as follows:
22082 (a) Initialize TARGET by broadcasting element NELTS_REQD - 1 of BUILDER.
22083 (b) Skip trailing elements from BUILDER, which are the same as
22084 element NELTS_REQD - 1.
22085 (c) Insert earlier elements in reverse order in TARGET using insr. */
22087 static void
22091 {
22106 }
22108 /* Subroutine of aarch64_sve_expand_vector_init to handle case
22109 when all trailing elements of builder are same.
22110 This works as follows:
22111 (a) Use expand_insn interface to broadcast last vector element in TARGET.
22112 (b) Insert remaining elements in TARGET using insr.
22114 ??? The heuristic used is to do above if number of same trailing elements
22115 is at least 3/4 of total number of elements, loosely based on
22116 heuristic from mostly_zeros_p. May need fine-tuning. */
22118 static bool
22119 aarch64_sve_expand_vector_init_handle_trailing_same_elem
22121 {
22124 {
22128 }
22131 }
22133 /* Initialize register TARGET from BUILDER. NELTS is the constant number
22134 of elements in BUILDER.
22136 The function tries to initialize TARGET from BUILDER if it fits one
22137 of the special cases outlined below.
22139 Failing that, the function divides BUILDER into two sub-vectors:
22140 v_even = even elements of BUILDER;
22141 v_odd = odd elements of BUILDER;
22143 and recursively calls itself with v_even and v_odd.
22145 if (recursive call succeeded for v_even or v_odd)
22146 TARGET = zip (v_even, v_odd)
22148 The function returns true if it managed to build TARGET from BUILDER
22149 with one of the special cases, false otherwise.
22151 Example: {a, 1, b, 2, c, 3, d, 4}
22153 The vector gets divided into:
22154 v_even = {a, b, c, d}
22155 v_odd = {1, 2, 3, 4}
22157 aarch64_sve_expand_vector_init(v_odd) hits case 1 and
22158 initialize tmp2 from constant vector v_odd using emit_move_insn.
22160 aarch64_sve_expand_vector_init(v_even) fails since v_even contains
22161 4 elements, so we construct tmp1 from v_even using insr:
22162 tmp1 = dup(d)
22163 insr tmp1, c
22164 insr tmp1, b
22165 insr tmp1, a
22167 And finally:
22168 TARGET = zip (tmp1, tmp2)
22169 which sets TARGET to {a, 1, b, 2, c, 3, d, 4}. */
22171 static bool
22174 {
22177 /* Case 1: Vector contains trailing constants. */
22183 /* Case 2: Vector contains leading constants. */
22192 {
22195 }
22197 /* Case 3: Vector contains trailing same element. */
22203 /* Case 4: Vector contains leading same element. */
22207 {
22210 }
22212 /* Avoid recursing below 4-elements.
22213 ??? The threshold 4 may need fine-tuning. */
22222 {
22225 }
22241 /* Initialize v_even and v_odd using INSR if it didn't match any of the
22242 special cases and zip v_even, v_odd. */
22253 }
22255 /* Initialize register TARGET from the elements in PARALLEL rtx VALS. */
22257 void
22259 {
22268 /* If neither sub-vectors of v could be initialized specially,
22269 then use INSR to insert all elements from v into TARGET.
22270 ??? This might not be optimal for vectors with large
22271 initializers like 16-element or above.
22272 For nelts < 4, it probably isn't useful to handle specially. */
22277 }
22279 /* Check whether VALUE is a vector constant in which every element
22280 is either a power of 2 or a negated power of 2. If so, return
22281 a constant vector of log2s, and flip CODE between PLUS and MINUS
22282 if VALUE contains negated powers of 2. Return NULL_RTX otherwise. */
22284 static rtx
22286 {
22290 rtx_vector_builder builder;
22295 /* 1 if the result of the multiplication must be negated,
22296 0 if it mustn't, or -1 if we don't yet care. */
22300 {
22307 {
22308 /* It matters whether we negate or not. Make that choice,
22309 and make sure that it's consistent with previous elements. */
22315 }
22316 /* POW2 is now the value that we want to be a power of 2. */
22321 }
22323 /* PLUS and MINUS are equivalent; canonicalize on PLUS. */
22328 }
22330 /* Prepare for an integer SVE multiply-add or multiply-subtract pattern;
22331 CODE is PLUS for the former and MINUS for the latter. OPERANDS is the
22332 operands array, in the same order as for fma_optab. Return true if
22333 the function emitted all the necessary instructions, false if the caller
22334 should generate the pattern normally with the new OPERANDS array. */
22336 bool
22338 {
22341 {
22346 OPTAB_DIRECT);
22348 }
22351 }
22353 /* Likewise, but for a conditional pattern. */
22355 bool
22357 {
22360 {
22366 }
22369 }
22371 static unsigned HOST_WIDE_INT
22373 {
22377 }
22379 /* Select a format to encode pointers in exception handling data. */
22380 int
22382 {
22385 {
22391 /* text+got+data < 4Gb. 4-byte signed relocs are sufficient
22392 for everything. */
22396 /* No assumptions here. 8-byte relocs required. */
22399 }
22401 }
22403 /* Output .variant_pcs for aarch64_vector_pcs function symbols. */
22405 static void
22407 {
22409 {
22412 {
22416 }
22417 }
22418 }
22420 /* The last .arch and .tune assembly strings that we printed. */
22424 /* Implement ASM_DECLARE_FUNCTION_NAME. Output the ISA features used
22425 by the function fndecl. */
22427 void
22429 tree fndecl)
22430 {
22436 else
22447 /* Only update the assembler .arch string if it is distinct from the last
22448 such string we printed. */
22451 {
22454 }
22456 /* Print the cpu name we're tuning for in the comments, might be
22457 useful to readers of the generated asm. Do it only when it changes
22458 from function to function and verbose assembly is requested. */
22463 {
22467 }
22471 /* Don't forget the type directive for ELF. */
22476 }
22478 /* Implement PRINT_PATCHABLE_FUNCTION_ENTRY. Check if the patch area is after
22479 the function label and emit a BTI if necessary. */
22481 void
22485 {
22489 {
22490 /* Remove the BTI that follows the patch area and insert a new BTI
22491 before the patch area right after the function label. */
22499 }
22502 }
22504 /* Implement ASM_OUTPUT_DEF_FROM_DECLS. Output .variant_pcs for aliases. */
22506 void
22508 {
22513 }
22515 /* Implement ASM_OUTPUT_EXTERNAL. Output .variant_pcs for undefined
22516 function symbol references. */
22518 void
22520 {
22523 }
22525 /* Triggered after a .cfi_startproc directive is emitted into the assembly file.
22526 Used to output the .cfi_b_key_frame directive when signing the current
22527 function with the B key. */
22529 void
22531 {
22535 }
22537 /* Implements TARGET_ASM_FILE_START. Output the assembly header. */
22539 static void
22541 {
22558 }
22560 /* Emit load exclusive. */
22562 static void
22565 {
22570 else
22572 }
22574 /* Emit store exclusive. */
22576 static void
22579 {
22584 else
22586 }
22588 /* Mark the previous jump instruction as unlikely. */
22590 static void
22592 {
22595 }
22597 /* We store the names of the various atomic helpers in a 5x5 array.
22598 Return the libcall function given MODE, MODEL and NAMES. */
22600 rtx
22603 {
22608 {
22626 }
22629 {
22651 }
22654 VISIBILITY_HIDDEN);
22655 }
22657 #define DEF0(B, N) \
22664 #define DEF4(B) DEF0(B, 1), DEF0(B, 2), DEF0(B, 4), DEF0(B, 8), \
22665 { NULL, NULL, NULL, NULL }
22666 #define DEF5(B) DEF0(B, 1), DEF0(B, 2), DEF0(B, 4), DEF0(B, 8), DEF0(B, 16)
22675 #undef DEF0
22676 #undef DEF4
22677 #undef DEF5
22679 /* Expand a compare and swap pattern. */
22681 void
22683 {
22697 /* Normally the succ memory model must be stronger than fail, but in the
22698 unlikely event of fail being ACQUIRE and succ being RELEASE we need to
22699 promote succ to ACQ_REL so that we don't lose the acquire semantics. */
22706 {
22709 }
22712 {
22713 /* The CAS insn requires oldval and rval overlap, but we need to
22714 have a copy of oldval saved across the operation to tell if
22715 the operation is successful. */
22718 else
22724 }
22726 {
22727 /* Oldval must satisfy compare afterward. */
22735 }
22736 else
22737 {
22738 /* The oldval predicate varies by mode. Test it and force to reg. */
22746 }
22754 }
22756 /* Emit a barrier, that is appropriate for memory model MODEL, at the end of a
22757 sequence implementing an atomic operation. */
22759 static void
22761 {
22768 {
22770 }
22771 }
22773 /* Split a compare and swap pattern. */
22775 void
22777 {
22778 /* Split after prolog/epilog to avoid interactions with shrinkwrapping. */
22782 machine_mode mode;
22797 /* When OLDVAL is zero and we want the strong version we can emit a tighter
22798 loop:
22799 .label1:
22800 LD[A]XR rval, [mem]
22801 CBNZ rval, .label2
22802 ST[L]XR scratch, newval, [mem]
22803 CBNZ scratch, .label1
22804 .label2:
22805 CMP rval, 0. */
22811 {
22814 }
22817 /* The initial load can be relaxed for a __sync operation since a final
22818 barrier will be emitted to stop code hoisting. */
22821 else
22826 else
22827 {
22830 }
22838 {
22840 {
22841 /* Emit an explicit compare instruction, so that we can correctly
22842 track the condition codes. */
22845 }
22846 else
22852 }
22853 else
22858 /* If we used a CBNZ in the exchange loop emit an explicit compare with RVAL
22859 to set the condition flags. If this is not used it will be removed by
22860 later passes. */
22864 /* Emit any final barrier needed for a __sync operation. */
22867 }
22869 /* Split an atomic operation. */
22871 void
22874 {
22875 /* Split after prolog/epilog to avoid interactions with shrinkwrapping. */
22883 rtx x;
22885 /* Split the atomic operation into a sequence. */
22893 else
22897 /* The initial load can be relaxed for a __sync operation since a final
22898 barrier will be emitted to stop code hoisting. */
22902 else
22906 {
22920 {
22923 }
22924 /* Fall through. */
22930 }
22936 {
22937 /* Emit an explicit compare instruction, so that we can correctly
22938 track the condition codes. */
22941 }
22942 else
22949 /* Emit any final barrier needed for a __sync operation. */
22952 }
22954 static void
22956 {
22957 /* Half-precision float operations. The compiler handles all operations
22958 with NULL libfuncs by converting to SFmode. */
22960 /* Conversions. */
22964 /* Arithmetic. */
22971 /* Comparisons. */
22979 }
22981 /* Target hook for c_mode_for_suffix. */
22982 static machine_mode
22984 {
22989 }
22991 /* We can only represent floating point constants which will fit in
22992 "quarter-precision" values. These values are characterised by
22993 a sign bit, a 4-bit mantissa and a 3-bit exponent. And are given
22994 by:
22996 (-1)^s * (n/16) * 2^r
22998 Where:
22999 's' is the sign bit.
23000 'n' is an integer in the range 16 <= n <= 31.
23001 'r' is an integer in the range -3 <= r <= 4. */
23003 /* Return true iff X can be represented by a quarter-precision
23004 floating point immediate operand X. Note, we cannot represent 0.0. */
23005 bool
23007 {
23008 /* This represents our current view of how many bits
23009 make up the mantissa. */
23026 /* We cannot represent infinities, NaNs or +/-zero. We won't
23027 know if we have +zero until we analyse the mantissa, but we
23028 can reject the other invalid values. */
23033 /* Extract exponent. */
23037 /* For the mantissa, we expand into two HOST_WIDE_INTS, apart from the
23038 highest (sign) bit, with a fixed binary point at bit point_pos.
23039 m1 holds the low part of the mantissa, m2 the high part.
23040 WARNING: If we ever have a representation using more than 2 * H_W_I - 1
23041 bits for the mantissa, this can fail (low bits will be lost). */
23045 /* If the low part of the mantissa has bits set we cannot represent
23046 the value. */
23049 /* We have rejected the lower HOST_WIDE_INT, so update our
23050 understanding of how many bits lie in the mantissa and
23051 look only at the high HOST_WIDE_INT. */
23055 /* We can only represent values with a mantissa of the form 1.xxxx. */
23060 /* Having filtered unrepresentable values, we may now remove all
23061 but the highest 5 bits. */
23064 /* We cannot represent the value 0.0, so reject it. This is handled
23065 elsewhere. */
23069 /* Then, as bit 4 is always set, we can mask it off, leaving
23070 the mantissa in the range [0, 15]. */
23074 /* GCC internally does not use IEEE754-like encoding (where normalized
23075 significands are in the range [1, 2). GCC uses [0.5, 1) (see real.cc).
23076 Our mantissa values are shifted 4 places to the left relative to
23077 normalized IEEE754 so we must modify the exponent returned by REAL_EXP
23078 by 5 places to correct for GCC's representation. */
23082 }
23084 /* Returns the string with the instruction for AdvSIMD MOVI, MVNI, ORR or BIC
23085 immediate with a CONST_VECTOR of MODE and WIDTH. WHICH selects whether to
23086 output MOVI/MVNI, ORR or BIC immediate. */
23090 {
23100 /* This will return true to show const_vector is legal for use as either
23101 a AdvSIMD MOVI instruction (or, implicitly, MVNI), ORR or BIC immediate.
23102 It will also update INFO to show how the immediate should be generated.
23103 WHICH selects whether to check for MOVI/MVNI, ORR or BIC. */
23111 {
23114 /* For FP zero change it to a CONST_INT 0 and use the integer SIMD
23115 move immediate path. */
23118 else
23119 {
23128 else
23132 }
23133 }
23138 {
23150 else
23154 }
23155 else
23156 {
23157 /* For AARCH64_CHECK_BIC and AARCH64_CHECK_ORR. */
23164 else
23168 }
23170 }
23174 {
23176 /* If a floating point number was passed and we desire to use it in an
23177 integer mode do the conversion to integer. */
23179 {
23184 }
23186 machine_mode vmode;
23187 /* use a 64 bit mode for everything except for DI/DF/DD mode, where we use
23188 a 128 bit vector mode. */
23194 }
23196 /* Return the output string to use for moving immediate CONST_VECTOR
23197 into an SVE register. */
23201 {
23213 {
23216 {
23219 }
23220 else
23221 {
23228 else
23231 }
23233 }
23236 {
23242 }
23245 {
23248 else
23249 {
23259 }
23260 }
23265 }
23267 /* Return the asm template for a PTRUES. CONST_UNSPEC is the
23268 aarch64_sve_ptrue_svpattern_immediate that describes the predicate
23269 pattern. */
23273 {
23284 }
23286 /* Split operands into moves from op[1] + op[2] into op[0]. */
23288 void
23290 {
23301 {
23302 /* No-op move. Can't split to nothing; emit something. */
23305 }
23307 /* Preserve register attributes for variable tracking. */
23312 /* Special case of reversed high/low parts. */
23315 {
23319 }
23321 {
23322 /* Try to avoid unnecessary moves if part of the result
23323 is in the right place already. */
23328 }
23329 else
23330 {
23335 }
23336 }
23338 /* vec_perm support. */
23340 struct expand_vec_perm_d
23341 {
23343 vec_perm_indices perm;
23344 machine_mode vmode;
23345 machine_mode op_mode;
23350 };
23354 /* Generate a variable permutation. */
23356 static void
23358 {
23369 {
23371 {
23372 /* Expand the argument to a V16QI mode by duplicating it. */
23376 }
23377 else
23378 {
23380 }
23381 }
23382 else
23383 {
23384 rtx pair;
23387 {
23391 }
23392 else
23393 {
23397 }
23398 }
23399 }
23401 /* Expand a vec_perm with the operands given by TARGET, OP0, OP1 and SEL.
23402 NELT is the number of elements in the vector. */
23404 void
23407 {
23410 rtx mask;
23412 /* The TBL instruction does not use a modulo index, so we must take care
23413 of that ourselves. */
23418 /* For big-endian, we also need to reverse the index within the vector
23419 (but not which vector). */
23421 {
23422 /* If one_vector_p, mask is a vector of (nelt - 1)'s already. */
23427 }
23429 }
23431 /* Generate (set TARGET (unspec [OP0 OP1] CODE)). */
23433 static void
23435 {
23439 }
23441 /* Expand an SVE vec_perm with the given operands. */
23443 void
23445 {
23448 /* Enforced by the pattern condition. */
23451 /* Note: vec_perm indices are supposed to wrap when they go beyond the
23452 size of the two value vectors, i.e. the upper bits of the indices
23453 are effectively ignored. SVE TBL instead produces 0 for any
23454 out-of-range indices, so we need to modulo all the vec_perm indices
23455 to ensure they are all in range. */
23458 /* Check if the sel only references the first values vector. */
23461 {
23464 }
23466 /* Check if the two values vectors are the same. */
23468 {
23474 }
23476 /* Run TBL on for each value vector and combine the results. */
23483 {
23488 }
23495 else
23497 }
23499 /* Recognize patterns suitable for the TRN instructions. */
23500 static bool
23502 {
23503 HOST_WIDE_INT odd;
23511 /* Note that these are little-endian tests.
23512 We correct for big-endian later. */
23519 /* Success! */
23525 /* We don't need a big-endian lane correction for SVE; see the comment
23526 at the head of aarch64-sve.md for details. */
23528 {
23531 }
23537 }
23539 /* Try to re-encode the PERM constant so it combines odd and even elements.
23540 This rewrites constants such as {0, 1, 4, 5}/V4SF to {0, 2}/V2DI.
23541 We retry with this new constant with the full suite of patterns. */
23542 static bool
23544 {
23545 expand_vec_perm_d newd;
23551 /* Get the new mode. Always twice the size of the inner
23552 and half the elements. */
23561 /* to_constant is safe since this routine is specific to Advanced SIMD
23562 vectors. */
23565 vec_perm_builder newpermconst;
23568 /* Convert the perm constant if we can. Require even, odd as the pairs. */
23570 {
23573 poly_int64 newelt;
23577 }
23592 }
23594 /* Recognize patterns suitable for the UZP instructions. */
23595 static bool
23597 {
23598 HOST_WIDE_INT odd;
23605 /* Note that these are little-endian tests.
23606 We correct for big-endian later. */
23612 /* Success! */
23618 /* We don't need a big-endian lane correction for SVE; see the comment
23619 at the head of aarch64-sve.md for details. */
23621 {
23624 }
23630 }
23632 /* Recognize patterns suitable for the ZIP instructions. */
23633 static bool
23635 {
23644 /* Note that these are little-endian tests.
23645 We correct for big-endian later. */
23653 /* Success! */
23659 /* We don't need a big-endian lane correction for SVE; see the comment
23660 at the head of aarch64-sve.md for details. */
23662 {
23665 }
23671 }
23673 /* Recognize patterns for the EXT insn. */
23675 static bool
23677 {
23678 HOST_WIDE_INT location;
23679 rtx offset;
23681 /* The first element always refers to the first vector.
23682 Check if the extracted indices are increasing by one. */
23688 /* Success! */
23692 /* The case where (location == 0) is a no-op for both big- and little-endian,
23693 and is removed by the mid-end at optimization levels -O1 and higher.
23695 We don't need a big-endian lane correction for SVE; see the comment
23696 at the head of aarch64-sve.md for details. */
23698 {
23699 /* After setup, we want the high elements of the first vector (stored
23700 at the LSB end of the register), and the low elements of the second
23701 vector (stored at the MSB end of the register). So swap. */
23703 /* location != 0 (above), so safe to assume (nelt - location) < nelt.
23704 to_constant () is safe since this is restricted to Advanced SIMD
23705 vectors. */
23707 }
23713 UNSPEC_EXT));
23715 }
23717 /* Recognize patterns for the REV{64,32,16} insns, which reverse elements
23718 within each 64-bit, 32-bit or 16-bit granule. */
23720 static bool
23722 {
23723 HOST_WIDE_INT diff;
23725 machine_mode pred_mode;
23735 else
23738 {
23741 }
23743 {
23746 }
23748 {
23751 }
23752 else
23760 /* Success! */
23765 {
23770 }
23774 }
23776 /* Recognize patterns for the REV insn, which reverses elements within
23777 a full vector. */
23779 static bool
23781 {
23790 /* Success! */
23797 }
23799 static bool
23801 {
23803 rtx in0;
23804 HOST_WIDE_INT elt;
23806 rtx lane;
23817 /* Success! */
23821 /* The generic preparation in aarch64_expand_vec_perm_const_1
23822 swaps the operand order and the permute indices if it finds
23823 d->perm[0] to be in the second operand. Thus, we can always
23824 use d->op0 and need not do any extra arithmetic to get the
23825 correct lane number. */
23833 }
23835 static bool
23837 {
23841 /* Make sure that the indices are constant. */
23850 /* Generic code will try constant permutation twice. Once with the
23851 original mode and again with the elements lowered to QImode.
23852 So wait and don't do the selector expansion ourselves. */
23856 /* to_constant is safe since this routine is specific to Advanced SIMD
23857 vectors. */
23860 /* If big-endian and two vectors we end up with a weird mixed-endian
23861 mode on NEON. Reverse the index within each word but not the word
23862 itself. to_constant is safe because we checked is_constant above. */
23872 }
23874 /* Try to implement D using an SVE TBL instruction. */
23876 static bool
23878 {
23881 /* Permuting two variable-length vectors could overflow the
23882 index range. */
23893 else
23896 }
23898 /* Try to implement D using SVE dup instruction. */
23900 static bool
23902 {
23923 }
23925 /* Try to implement D using SVE SEL instruction. */
23927 static bool
23929 {
23955 /* Build a predicate that is true when op0 elements should be used. */
23958 {
23962 }
23966 /* TARGET = PRED ? OP0 : OP1. */
23969 }
23971 /* Recognize patterns suitable for the INS instructions. */
23972 static bool
23974 {
23981 /* to_constant is safe since this routine is specific to Advanced SIMD
23982 vectors. */
23989 {
23990 HOST_WIDE_INT elt;
23996 {
23999 }
24001 }
24004 {
24007 {
24013 }
24017 }
24027 {
24030 }
24043 }
24045 static bool
24047 {
24050 /* The pattern matching functions above are written to look for a small
24051 number to begin the sequence (0, 1, N/2). If we begin with an index
24052 from the second operand, we can swap the operands. */
24055 {
24058 }
24065 {
24067 {
24093 }
24094 else
24095 {
24098 }
24099 }
24101 }
24103 /* Implement TARGET_VECTORIZE_VEC_PERM_CONST. */
24105 static bool
24109 {
24112 /* Check whether the mask can be applied to a single vector. */
24117 {
24120 }
24122 {
24125 }
24126 else
24139 else
24151 }
24153 /* Generate a byte permute mask for a register of mode MODE,
24154 which has NUNITS units. */
24156 rtx
24158 {
24159 /* We have to reverse each vector because we dont have
24160 a permuted load that can reverse-load according to ABI rules. */
24161 rtx mask;
24174 }
24176 /* Expand an SVE integer comparison using the SVE equivalent of:
24178 (set TARGET (CODE OP0 OP1)). */
24180 void
24182 {
24189 }
24191 /* Return the UNSPEC_COND_* code for comparison CODE. */
24193 static unsigned int
24195 {
24197 {
24214 }
24215 }
24217 /* Emit:
24219 (set TARGET (unspec [PRED KNOWN_PTRUE_P OP0 OP1] UNSPEC_COND_<X>))
24221 where <X> is the operation associated with comparison CODE.
24222 KNOWN_PTRUE_P is true if PRED is known to be a PTRUE. */
24224 static void
24227 {
24233 }
24235 /* Emit the SVE equivalent of:
24237 (set TMP1 (unspec [PRED KNOWN_PTRUE_P OP0 OP1] UNSPEC_COND_<X1>))
24238 (set TMP2 (unspec [PRED KNOWN_PTRUE_P OP0 OP1] UNSPEC_COND_<X2>))
24239 (set TARGET (ior:PRED_MODE TMP1 TMP2))
24241 where <Xi> is the operation associated with comparison CODEi.
24242 KNOWN_PTRUE_P is true if PRED is known to be a PTRUE. */
24244 static void
24247 {
24254 }
24256 /* Emit the SVE equivalent of:
24258 (set TMP (unspec [PRED KNOWN_PTRUE_P OP0 OP1] UNSPEC_COND_<X>))
24259 (set TARGET (not TMP))
24261 where <X> is the operation associated with comparison CODE.
24262 KNOWN_PTRUE_P is true if PRED is known to be a PTRUE. */
24264 static void
24267 {
24272 }
24274 /* Expand an SVE floating-point comparison using the SVE equivalent of:
24276 (set TARGET (CODE OP0 OP1))
24278 If CAN_INVERT_P is true, the caller can also handle inverted results;
24279 return true if the result is in fact inverted. */
24281 bool
24284 {
24290 {
24292 /* UNORDERED has no immediate form. */
24294 /* fall through */
24301 {
24302 /* There is native support for the comparison. */
24305 }
24308 /* This is a trapping operation (LT or GT). */
24314 {
24315 /* This would trap for signaling NaNs. */
24320 }
24321 /* fall through */
24327 {
24328 /* Work out which elements are ordered. */
24334 /* Test the opposite condition for the ordered elements,
24335 then invert the result. */
24338 else
24341 {
24345 }
24349 }
24353 /* ORDERED has no immediate form. */
24359 }
24361 /* There is native support for the inverse comparison. */
24364 {
24367 }
24370 }
24372 /* Expand an SVE vcond pattern with operands OPS. DATA_MODE is the mode
24373 of the data being selected and CMP_MODE is the mode of the values being
24374 compared. */
24376 void
24379 {
24383 {
24387 }
24388 else
24393 /* The "false" value can only be zero if the "true" value is a constant. */
24400 }
24402 /* Implement TARGET_MODES_TIEABLE_P. In principle we should always return
24403 true. However due to issues with register allocation it is preferable
24404 to avoid tieing integer scalar and FP scalar modes. Executing integer
24405 operations in general registers is better than treating them as scalar
24406 vector operations. This reduces latency and avoids redundant int<->FP
24407 moves. So tie modes if they are either the same class, or vector modes
24408 with other vector modes, vector structs or any scalar mode. */
24410 static bool
24412 {
24422 /* We specifically want to allow elements of "structure" modes to
24423 be tieable to the structure. This more general condition allows
24424 other rarer situations too. The reason we don't extend this to
24425 predicate modes is that there are no predicate structure modes
24426 nor any specific instructions for extracting part of a predicate
24427 register. */
24432 /* Also allow any scalar modes with vectors. */
24438 }
24440 /* Return a new RTX holding the result of moving POINTER forward by
24441 AMOUNT bytes. */
24443 static rtx
24445 {
24450 }
24452 /* Return a new RTX holding the result of moving POINTER forward by the
24453 size of the mode it points to. */
24455 static rtx
24457 {
24459 }
24461 /* Copy one MODE sized block from SRC to DST, then progress SRC and DST by
24462 MODE bytes. */
24464 static void
24466 machine_mode mode)
24467 {
24468 /* Handle 256-bit memcpy separately. We do this by making 2 adjacent memory
24469 address copies using V4SImode so that we can use Q registers. */
24471 {
24475 /* "Cast" the pointers to the correct mode. */
24478 /* Emit the memcpy. */
24483 /* Move the pointers forward. */
24487 }
24491 /* "Cast" the pointers to the correct mode. */
24494 /* Emit the memcpy. */
24497 /* Move the pointers forward. */
24500 }
24502 /* Expand a cpymem using the MOPS extension. OPERANDS are taken
24503 from the cpymem pattern. Return true iff we succeeded. */
24504 static bool
24506 {
24510 /* All three registers are changed by the instruction, so each one
24511 must be a fresh pseudo. */
24520 }
24522 /* Expand cpymem, as if from a __builtin_memcpy. Return true if
24523 we succeed, otherwise return false, indicating that a libcall to
24524 memcpy should be emitted. */
24526 bool
24528 {
24532 rtx base;
24535 /* Variable-sized memcpy can go through the MOPS expansion if available. */
24541 /* Try to inline up to 256 bytes or use the MOPS threshold if available. */
24542 unsigned HOST_WIDE_INT max_copy_size
24547 /* Large constant-sized cpymem should go through MOPS when possible.
24548 It should be a win even for size optimization in the general case.
24549 For speed optimization the choice between MOPS and the SIMD sequence
24550 depends on the size of the copy, rather than number of instructions,
24551 alignment etc. */
24557 /* Default to 256-bit LDP/STP on large copies, however small copies, no SIMD
24558 support or slow 256-bit LDP/STP fall back to 128-bit chunks. */
24560 || !TARGET_SIMD
24565 /* Emit an inline load+store sequence and count the number of operations
24566 involved. We use a simple count of just the loads and stores emitted
24567 rather than rtx_insn count as all the pointer adjustments and reg copying
24568 in this function will get optimized away later in the pipeline. */
24578 /* Convert size to bits to make the rest of the code simpler. */
24582 {
24583 /* Find the largest mode in which to do the copy in without over reading
24584 or writing. */
24585 opt_scalar_int_mode mode_iter;
24594 /* Prefer Q-register accesses for the last bytes. */
24599 /* A single block copy is 1 load + 1 store. */
24603 /* Emit trailing copies using overlapping unaligned accesses
24604 (when !STRICT_ALIGNMENT) - this is smaller and faster. */
24606 {
24613 }
24614 }
24617 /* MOPS sequence requires 3 instructions for the memory copying + 1 to move
24618 the constant size into a register. */
24621 /* If MOPS is available at this point we don't consider the libcall as it's
24622 not a win even on code size. At this point only consider MOPS if
24623 optimizing for size. For speed optimizations we will have chosen between
24624 the two based on copy size already. */
24626 {
24631 }
24633 /* A memcpy libcall in the worst case takes 3 instructions to prepare the
24634 arguments + 1 for the call. When MOPS is not available and we're
24635 optimizing for size a libcall may be preferable. */
24642 }
24644 /* Like aarch64_copy_one_block_and_progress_pointers, except for memset where
24645 SRC is a register we have created with the duplicated value to be set. */
24646 static void
24648 machine_mode mode)
24649 {
24650 /* If we are copying 128bits or 256bits, we can do that straight from
24651 the SIMD register we prepared. */
24653 {
24655 /* "Cast" the *dst to the correct mode. */
24657 /* Emit the memset. */
24661 /* Move the pointers forward. */
24664 }
24666 {
24667 /* "Cast" the *dst to the correct mode. */
24669 /* Emit the memset. */
24671 /* Move the pointers forward. */
24674 }
24675 /* For copying less, we have to extract the right amount from src. */
24678 /* "Cast" the *dst to the correct mode. */
24680 /* Emit the memset. */
24682 /* Move the pointer forward. */
24684 }
24686 /* Expand a setmem using the MOPS instructions. OPERANDS are the same
24687 as for the setmem pattern. Return true iff we succeed. */
24688 static bool
24690 {
24694 /* The first two registers are changed by the instruction, so both
24695 of them must be a fresh pseudo. */
24704 }
24706 /* Expand setmem, as if from a __builtin_memset. Return true if
24707 we succeed, otherwise return false. */
24709 bool
24711 {
24716 rtx base;
24719 /* If we don't have SIMD registers or the size is variable use the MOPS
24720 inlined sequence if possible. */
24726 /* Default the maximum to 256-bytes when considering only libcall vs
24727 SIMD broadcast sequence. */
24735 /* The MOPS sequence takes:
24736 3 instructions for the memory storing
24737 + 1 to move the constant size into a reg
24738 + 1 if VAL is a non-zero constant to move into a reg
24739 (zero constants can use XZR directly). */
24741 /* A libcall to memset in the worst case takes 3 instructions to prepare
24742 the arguments + 1 for the call. */
24745 /* Upper bound check. For large constant-sized setmem use the MOPS sequence
24746 when available. */
24751 /* Attempt a sequence with a vector broadcast followed by stores.
24752 Count the number of operations involved to see if it's worth it
24753 against the alternatives. A simple counter simd_ops on the
24754 algorithmically-relevant operations is used rather than an rtx_insn count
24755 as all the pointer adjusmtents and mode reinterprets will be optimized
24756 away later. */
24763 /* Prepare the val using a DUP/MOVI v0.16B, val. */
24766 simd_ops++;
24767 /* Convert len to bits to make the rest of the code simpler. */
24770 /* Maximum amount to copy in one go. We allow 256-bit chunks based on the
24771 AARCH64_EXTRA_TUNE_NO_LDP_STP_QREGS tuning parameter. */
24777 {
24778 /* Find the largest mode in which to do the copy without
24779 over writing. */
24780 opt_scalar_int_mode mode_iter;
24789 simd_ops++;
24792 /* Do certain trailing copies as overlapping if it's going to be
24793 cheaper. i.e. less instructions to do so. For instance doing a 15
24794 byte copy it's more efficient to do two overlapping 8 byte copies than
24795 8 + 4 + 2 + 1. Only do this when -mstrict-align is not supplied. */
24797 {
24803 }
24804 }
24809 {
24810 /* When optimizing for size we have 3 options: the SIMD broadcast sequence,
24811 call to memset or the MOPS expansion. */
24816 /* If MOPS is not available or not shorter pick a libcall if the SIMD
24817 sequence is too long. */
24822 }
24824 /* At this point the SIMD broadcast sequence is the best choice when
24825 optimizing for speed. */
24828 }
24831 /* Split a DImode store of a CONST_INT SRC to MEM DST as two
24832 SImode stores. Handle the case when the constant has identical
24833 bottom and top halves. This is beneficial when the two stores can be
24834 merged into an STP and we avoid synthesising potentially expensive
24835 immediates twice. Return true if such a split is possible. */
24837 bool
24839 {
24848 unsigned int orig_cost
24850 unsigned int lo_cost
24853 /* We want to transform:
24854 MOV x1, 49370
24855 MOVK x1, 0x140, lsl 16
24856 MOVK x1, 0xc0da, lsl 32
24857 MOVK x1, 0x140, lsl 48
24858 STR x1, [x0]
24859 into:
24860 MOV w1, 49370
24861 MOVK w1, 0x140, lsl 16
24862 STP w1, w1, [x0]
24863 So we want to perform this only when we save two instructions
24864 or more. When optimizing for size, however, accept any code size
24865 savings we can. */
24880 /* Don't emit an explicit store pair as this may not be always profitable.
24881 Let the sched-fusion logic decide whether to merge them. */
24886 }
24888 /* Generate RTL for a conditional branch with rtx comparison CODE in
24889 mode CC_MODE. The destination of the unlikely conditional branch
24890 is LABEL_REF. */
24892 void
24894 rtx label_ref)
24895 {
24896 rtx x;
24899 const0_rtx);
24903 pc_rtx);
24905 }
24907 /* Generate DImode scratch registers for 128-bit (TImode) addition.
24909 OP1 represents the TImode destination operand 1
24910 OP2 represents the TImode destination operand 2
24911 LOW_DEST represents the low half (DImode) of TImode operand 0
24912 LOW_IN1 represents the low half (DImode) of TImode operand 1
24913 LOW_IN2 represents the low half (DImode) of TImode operand 2
24914 HIGH_DEST represents the high half (DImode) of TImode operand 0
24915 HIGH_IN1 represents the high half (DImode) of TImode operand 1
24916 HIGH_IN2 represents the high half (DImode) of TImode operand 2. */
24918 void
24923 {
24932 }
24934 /* Generate DImode scratch registers for 128-bit (TImode) subtraction.
24936 This function differs from 'arch64_addti_scratch_regs' in that
24937 OP1 can be an immediate constant (zero). We must call
24938 subreg_highpart_offset with DImode and TImode arguments, otherwise
24939 VOIDmode will be used for the const_int which generates an internal
24940 error from subreg_size_highpart_offset which does not expect a size of zero.
24942 OP1 represents the TImode destination operand 1
24943 OP2 represents the TImode destination operand 2
24944 LOW_DEST represents the low half (DImode) of TImode operand 0
24945 LOW_IN1 represents the low half (DImode) of TImode operand 1
24946 LOW_IN2 represents the low half (DImode) of TImode operand 2
24947 HIGH_DEST represents the high half (DImode) of TImode operand 0
24948 HIGH_IN1 represents the high half (DImode) of TImode operand 1
24949 HIGH_IN2 represents the high half (DImode) of TImode operand 2. */
24952 void
24957 {
24970 }
24972 /* Generate RTL for 128-bit (TImode) subtraction with overflow.
24974 OP0 represents the TImode destination operand 0
24975 LOW_DEST represents the low half (DImode) of TImode operand 0
24976 LOW_IN1 represents the low half (DImode) of TImode operand 1
24977 LOW_IN2 represents the low half (DImode) of TImode operand 2
24978 HIGH_DEST represents the high half (DImode) of TImode operand 0
24979 HIGH_IN1 represents the high half (DImode) of TImode operand 1
24980 HIGH_IN2 represents the high half (DImode) of TImode operand 2
24981 UNSIGNED_P is true if the operation is being performed on unsigned
24982 values. */
24983 void
24987 {
24989 {
24994 else
24996 }
24997 else
24998 {
25002 else
25003 {
25006 }
25011 else
25013 }
25018 }
25020 /* Implement the TARGET_ASAN_SHADOW_OFFSET hook. */
25022 static unsigned HOST_WIDE_INT
25024 {
25027 else
25029 }
25031 static rtx
25034 {
25038 insn_code icode;
25049 {
25077 }
25082 {
25085 }
25094 {
25097 }
25103 }
25105 static rtx
25108 {
25112 insn_code icode;
25124 {
25148 }
25155 {
25158 }
25166 {
25167 /* Treat the ccmp patterns as canonical and use them where possible,
25168 but fall back to ccmp_rev patterns if there's no other option. */
25177 else
25178 {
25181 }
25183 }
25194 {
25197 }
25203 }
25205 #undef TARGET_GEN_CCMP_FIRST
25206 #define TARGET_GEN_CCMP_FIRST aarch64_gen_ccmp_first
25208 #undef TARGET_GEN_CCMP_NEXT
25209 #define TARGET_GEN_CCMP_NEXT aarch64_gen_ccmp_next
25211 /* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
25212 instruction fusion of some sort. */
25214 static bool
25216 {
25218 }
25221 /* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
25222 should be kept together during scheduling. */
25224 static bool
25226 {
25227 rtx set_dest;
25230 /* prev and curr are simple SET insns i.e. no flag setting or branching. */
25237 {
25238 /* We are trying to match:
25239 prev (mov) == (set (reg r0) (const_int imm16))
25240 curr (movk) == (set (zero_extract (reg r0)
25241 (const_int 16)
25242 (const_int 16))
25243 (const_int imm16_1)) */
25255 {
25257 }
25258 }
25261 {
25263 /* We're trying to match:
25264 prev (adrp) == (set (reg r1)
25265 (high (symbol_ref ("SYM"))))
25266 curr (add) == (set (reg r0)
25267 (lo_sum (reg r1)
25268 (symbol_ref ("SYM"))))
25269 Note that r0 need not necessarily be the same as r1, especially
25270 during pre-regalloc scheduling. */
25274 {
25282 }
25283 }
25286 {
25288 /* We're trying to match:
25289 prev (movk) == (set (zero_extract (reg r0)
25290 (const_int 16)
25291 (const_int 32))
25292 (const_int imm16_1))
25293 curr (movk) == (set (zero_extract (reg r0)
25294 (const_int 16)
25295 (const_int 48))
25296 (const_int imm16_2)) */
25312 }
25314 {
25315 /* We're trying to match:
25316 prev (adrp) == (set (reg r0)
25317 (high (symbol_ref ("SYM"))))
25318 curr (ldr) == (set (reg r1)
25319 (mem (lo_sum (reg r0)
25320 (symbol_ref ("SYM")))))
25321 or
25322 curr (ldr) == (set (reg r1)
25323 (zero_extend (mem
25324 (lo_sum (reg r0)
25325 (symbol_ref ("SYM")))))) */
25328 {
25341 }
25342 }
25344 /* Fuse compare (CMP/CMN/TST/BICS) and conditional branch. */
25352 /* Fuse flag-setting ALU instructions and conditional branch. */
25355 {
25357 rtx cc_reg_1;
25362 && prev
25364 {
25367 /* FIXME: this misses some which is considered simple arthematic
25368 instructions for ThunderX. Simple shifts are missed here. */
25374 }
25375 }
25377 /* Fuse ALU instructions and CBZ/CBNZ. */
25379 && curr_set
25382 {
25383 /* We're trying to match:
25384 prev (alu_insn) == (set (r0) plus ((r0) (r1/imm)))
25385 curr (cbz) == (set (pc) (if_then_else (eq/ne) (r0)
25386 (const_int 0))
25387 (label_ref ("SYM"))
25388 (pc)) */
25395 {
25396 /* Fuse ALU operations followed by conditional branch instruction. */
25398 {
25419 }
25420 }
25421 }
25424 }
25426 /* Return true iff the instruction fusion described by OP is enabled. */
25428 bool
25430 {
25432 }
25434 /* If MEM is in the form of [base+offset], extract the two parts
25435 of address and set to BASE and OFFSET, otherwise return false
25436 after clearing BASE and OFFSET. */
25438 bool
25440 {
25441 rtx addr;
25448 {
25452 }
25456 {
25460 }
25466 }
25468 /* Types for scheduling fusion. */
25469 enum sched_fusion_type
25470 {
25472 SCHED_FUSION_LD_SIGN_EXTEND,
25473 SCHED_FUSION_LD_ZERO_EXTEND,
25474 SCHED_FUSION_LD,
25475 SCHED_FUSION_ST,
25476 SCHED_FUSION_NUM
25477 };
25479 /* If INSN is a load or store of address in the form of [base+offset],
25480 extract the two parts and set to BASE and OFFSET. Return scheduling
25481 fusion type this INSN is. */
25483 static enum sched_fusion_type
25485 {
25503 {
25508 }
25510 {
25515 }
25520 {
25523 }
25524 else
25531 }
25533 /* Implement the TARGET_SCHED_FUSION_PRIORITY hook.
25535 Currently we only support to fuse ldr or str instructions, so FUSION_PRI
25536 and PRI are only calculated for these instructions. For other instruction,
25537 FUSION_PRI and PRI are simply set to MAX_PRI - 1. In the future, other
25538 type instruction fusion can be added by returning different priorities.
25540 It's important that irrelevant instructions get the largest FUSION_PRI. */
25542 static void
25545 {
25555 {
25559 }
25561 /* Set FUSION_PRI according to fusion type and base register. */
25564 /* Calculate PRI. */
25567 /* INSN with smaller offset goes first. */
25571 else
25576 }
25578 /* Implement the TARGET_SCHED_ADJUST_PRIORITY hook.
25579 Adjust priority of sha1h instructions so they are scheduled before
25580 other SHA1 instructions. */
25582 static int
25584 {
25588 {
25593 }
25596 }
25598 /* If REVERSED is null, return true if memory reference *MEM2 comes
25599 immediately after memory reference *MEM1. Do not change the references
25600 in this case.
25602 Otherwise, check if *MEM1 and *MEM2 are consecutive memory references and,
25603 if they are, try to make them use constant offsets from the same base
25604 register. Return true on success. When returning true, set *REVERSED
25605 to true if *MEM1 comes after *MEM2, false if *MEM1 comes before *MEM2. */
25606 static bool
25608 {
25626 /* Make sure at least one memory is in base+offset form. */
25630 /* If both mems already use the same base register, just check the
25631 offsets. */
25633 {
25641 {
25644 }
25647 }
25649 /* Otherwise, check whether the MEM_EXPRs and MEM_OFFSETs together
25650 guarantee that the values are consecutive. */
25655 {
25656 poly_int64 expr_offset1;
25657 poly_int64 expr_offset2;
25663 || !expr_base2
25672 ;
25675 else
25679 {
25681 {
25685 }
25686 else
25687 {
25691 }
25692 }
25694 }
25697 }
25699 /* Return true if MEM1 and MEM2 can be combined into a single access
25700 of mode MODE, with the combined access having the same address as MEM1. */
25702 bool
25704 {
25708 }
25710 /* Given OPERANDS of consecutive load/store, check if we can merge
25711 them into ldp/stp. LOAD is true if they are load instructions.
25712 MODE is the mode of memory operands. */
25714 bool
25716 machine_mode mode)
25717 {
25722 {
25732 }
25733 else
25734 {
25739 }
25741 /* The mems cannot be volatile. */
25745 /* If we have SImode and slow unaligned ldp,
25746 check the alignment to be at least 8 byte. */
25750 && !optimize_size
25754 /* Check if the addresses are in the form of [base+offset]. */
25759 /* The operands must be of the same size. */
25763 /* One of the memory accesses must be a mempair operand.
25764 If it is not the first one, they need to be swapped by the
25765 peephole. */
25772 else
25777 else
25780 /* Check if the registers are of same class. */
25785 }
25787 /* Given OPERANDS of consecutive load/store that can be merged,
25788 swap them if they are not in ascending order. */
25789 void
25791 {
25799 {
25800 /* Irrespective of whether this is a load or a store,
25801 we do the same swap. */
25804 }
25805 }
25807 /* Taking X and Y to be HOST_WIDE_INT pointers, return the result of a
25808 comparison between the two. */
25809 int
25811 {
25814 }
25816 /* Taking X and Y to be pairs of RTX, one pointing to a MEM rtx and the
25817 other pointing to a REG rtx containing an offset, compare the offsets
25818 of the two pairs.
25820 Return:
25822 1 iff offset (X) > offset (Y)
25823 0 iff offset (X) == offset (Y)
25824 -1 iff offset (X) < offset (Y) */
25825 int
25827 {
25834 else
25839 else
25842 /* Extract the offsets. */
25849 }
25851 /* Given OPERANDS of consecutive load/store, check if we can merge
25852 them into ldp/stp by adjusting the offset. LOAD is true if they
25853 are load instructions. MODE is the mode of memory operands.
25855 Given below consecutive stores:
25857 str w1, [xb, 0x100]
25858 str w1, [xb, 0x104]
25859 str w1, [xb, 0x108]
25860 str w1, [xb, 0x10c]
25862 Though the offsets are out of the range supported by stp, we can
25863 still pair them after adjusting the offset, like:
25865 add scratch, xb, 0x100
25866 stp w1, w1, [scratch]
25867 stp w1, w1, [scratch, 0x8]
25869 The peephole patterns detecting this opportunity should guarantee
25870 the scratch register is avaliable. */
25872 bool
25874 machine_mode mode)
25875 {
25882 {
25884 {
25889 }
25891 /* Do not attempt to merge the loads if the loads clobber each other. */
25896 }
25897 else
25899 {
25902 }
25904 /* Skip if memory operand is by itself valid for ldp/stp. */
25909 {
25910 /* The mems cannot be volatile. */
25914 /* Check if the addresses are in the form of [base+offset]. */
25918 }
25920 /* Check if the registers are of same class. */
25926 {
25929 }
25930 else
25931 {
25934 }
25936 /* Only the last register in the order in which they occur
25937 may be clobbered by the load. */
25943 /* Check if the bases are same. */
25953 /* Check if the offsets can be put in the right order to do a ldp/stp. */
25955 aarch64_host_wide_int_compare);
25961 /* Check that offsets are within range of each other. The ldp/stp
25962 instructions have 7 bit immediate offsets, so use 0x80. */
25966 /* The offsets must be aligned with respect to each other. */
25970 /* If we have SImode and slow unaligned ldp,
25971 check the alignment to be at least 8 byte. */
25975 && !optimize_size
25980 }
25982 /* Given OPERANDS of consecutive load/store, this function pairs them
25983 into LDP/STP after adjusting the offset. It depends on the fact
25984 that the operands can be sorted so the offsets are correct for STP.
25985 MODE is the mode of memory operands. CODE is the rtl operator
25986 which should be applied to all memory operands, it's SIGN_EXTEND,
25987 ZERO_EXTEND or UNKNOWN. */
25989 bool
25992 {
25999 /* We make changes on a copy as we may still bail out. */
26003 /* Sort the operands. Note for cases as below:
26004 [base + 0x310] = A
26005 [base + 0x320] = B
26006 [base + 0x330] = C
26007 [base + 0x320] = D
26008 We need stable sorting otherwise wrong data may be store to offset 0x320.
26009 Also note the dead store in above case should be optimized away, but no
26010 guarantees here. */
26012 aarch64_ldrstr_offset_compare);
26014 /* Copy the memory operands so that if we have to bail for some
26015 reason the original addresses are unchanged. */
26017 {
26022 }
26023 else
26024 {
26030 }
26037 /* Adjust offset so it can fit in LDP/STP instruction. */
26045 /* The base offset is optimally half way between the two STP/LDP offsets. */
26048 else
26049 /* However, due to issues with negative LDP/STP offset generation for
26050 larger modes, for DF, DD, DI and vector modes. we must not use negative
26051 addresses smaller than 9 signed unadjusted bits can store. This
26052 provides the most range in this case. */
26055 /* Adjust the base so that it is aligned with the addresses but still
26056 optimal. */
26058 /* Fix the offset, bearing in mind we want to make it bigger not
26059 smaller. */
26062 /* The negative range of LDP/STP is one larger than the positive range. */
26065 /* Check if base offset is too big or too small. We can attempt to resolve
26066 this issue by setting it to the maximum value and seeing if the offsets
26067 still fit. */
26069 {
26071 /* We must still make sure that the base offset is aligned with respect
26072 to the address. But it may not be made any bigger. */
26074 }
26076 /* Likewise for the case where the base is too small. */
26078 {
26081 }
26083 /* Offset of the first STP/LDP. */
26086 /* Offset of the second STP/LDP. */
26089 /* The offsets must be within the range of the LDP/STP instructions. */
26108 {
26113 }
26115 {
26120 }
26123 {
26132 }
26133 else
26134 {
26143 }
26145 /* Emit adjusting instruction. */
26147 /* Emit ldp/stp instructions. */
26155 }
26157 /* Implement TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE. Assume for now that
26158 it isn't worth branching around empty masked ops (including masked
26159 stores). */
26161 static bool
26163 {
26165 }
26167 /* Return 1 if pseudo register should be created and used to hold
26168 GOT address for PIC code. */
26170 bool
26172 {
26174 }
26176 /* Implement TARGET_UNSPEC_MAY_TRAP_P. */
26178 static int
26180 {
26182 {
26189 }
26192 }
26195 /* If X is a positive CONST_DOUBLE with a value that is a power of 2
26196 return the log2 of that value. Otherwise return -1. */
26198 int
26200 {
26215 }
26217 /* If X is a positive CONST_DOUBLE with a value that is the reciprocal of a
26218 power of 2 (i.e 1/2^n) return the number of float bits. e.g. for x==(1/2^n)
26219 return n. Otherwise return -1. */
26221 int
26223 {
26224 REAL_VALUE_TYPE r0;
26232 {
26236 }
26238 }
26240 /* If X is a vector of equal CONST_DOUBLE values and that value is
26241 Y, return the aarch64_fpconst_pow_of_2 of Y. Otherwise return -1. */
26243 int
26245 {
26263 }
26265 /* Implement TARGET_PROMOTED_TYPE to promote 16-bit floating point types
26266 to float.
26268 __fp16 always promotes through this hook.
26269 _Float16 may promote if TARGET_FLT_EVAL_METHOD is 16, but we do that
26270 through the generic excess precision logic rather than here. */
26272 static tree
26274 {
26280 }
26282 /* Implement the TARGET_OPTAB_SUPPORTED_P hook. */
26284 static bool
26286 optimization_type opt_type)
26287 {
26289 {
26295 }
26296 }
26298 /* Implement the TARGET_DWARF_POLY_INDETERMINATE_VALUE hook. */
26300 static unsigned int
26303 {
26304 /* Polynomial invariant 1 == (VG / 2) - 1. */
26309 }
26311 /* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
26312 if MODE is HFmode, and punt to the generic implementation otherwise. */
26314 static bool
26316 {
26320 }
26322 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P - return TRUE
26323 if MODE is HFmode, and punt to the generic implementation otherwise. */
26325 static bool
26327 {
26334 }
26336 /* Set the value of FLT_EVAL_METHOD.
26337 ISO/IEC TS 18661-3 defines two values that we'd like to make use of:
26339 0: evaluate all operations and constants, whose semantic type has at
26340 most the range and precision of type float, to the range and
26341 precision of float; evaluate all other operations and constants to
26342 the range and precision of the semantic type;
26344 N, where _FloatN is a supported interchange floating type
26345 evaluate all operations and constants, whose semantic type has at
26346 most the range and precision of _FloatN type, to the range and
26347 precision of the _FloatN type; evaluate all other operations and
26348 constants to the range and precision of the semantic type;
26350 If we have the ARMv8.2-A extensions then we support _Float16 in native
26351 precision, so we should set this to 16. Otherwise, we support the type,
26352 but want to evaluate expressions in float precision, so set this to
26353 0. */
26355 static enum flt_eval_method
26357 {
26359 {
26362 /* We can calculate either in 16-bit range and precision or
26363 32-bit range and precision. Make that decision based on whether
26364 we have native support for the ARMv8.2-A 16-bit floating-point
26365 instructions or not. */
26367 ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16
26374 }
26376 }
26378 /* Implement TARGET_SCHED_CAN_SPECULATE_INSN. Return true if INSN can be
26379 scheduled for speculative execution. Reject the long-running division
26380 and square-root instructions. */
26382 static bool
26384 {
26386 {
26404 }
26405 }
26407 /* Implement TARGET_COMPUTE_PRESSURE_CLASSES. */
26409 static int
26411 {
26415 /* PR_REGS isn't a useful pressure class because many predicate pseudo
26416 registers need to go in PR_LO_REGS at some point during their
26417 lifetime. Splitting it into two halves has the effect of making
26418 all predicates count against PR_LO_REGS, so that we try whenever
26419 possible to restrict the number of live predicates to 8. This
26420 greatly reduces the amount of spilling in certain loops. */
26424 }
26426 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */
26428 static bool
26431 {
26448 /* Don't allow changes between predicate modes and other modes.
26449 Only predicate registers can hold predicate modes and only
26450 non-predicate registers can hold non-predicate modes, so any
26451 attempt to mix them would require a round trip through memory. */
26455 /* Don't allow changes between partial SVE modes and other modes.
26456 The contents of partial SVE modes are distributed evenly across
26457 the register, whereas GCC expects them to be clustered together. */
26461 /* Similarly reject changes between partial SVE modes that have
26462 different patterns of significant and insignificant bits. */
26468 /* Don't allow changes between partial and full Advanced SIMD structure
26469 modes. */
26474 {
26475 /* Don't allow changes between SVE modes and other modes that might
26476 be bigger than 128 bits. In particular, OImode, CImode and XImode
26477 divide into 128-bit quantities while SVE modes divide into
26478 BITS_PER_SVE_VECTOR quantities. */
26483 }
26486 {
26487 /* Don't allow changes between SVE data modes and non-SVE modes.
26488 See the comment at the head of aarch64-sve.md for details. */
26492 /* Don't allow changes in element size: lane 0 of the new vector
26493 would not then be lane 0 of the old vector. See the comment
26494 above aarch64_maybe_expand_sve_subreg_move for a more detailed
26495 description.
26497 In the worst case, this forces a register to be spilled in
26498 one mode and reloaded in the other, which handles the
26499 endianness correctly. */
26502 }
26504 }
26506 /* Implement TARGET_EARLY_REMAT_MODES. */
26508 static void
26510 {
26511 /* SVE values are not normally live across a call, so it should be
26512 worth doing early rematerialization even in VL-specific mode. */
26516 }
26518 /* Override the default target speculation_safe_value. */
26519 static rtx
26522 {
26523 /* Maybe we should warn if falling back to hard barriers. They are
26524 likely to be noticably more expensive than the alternative below. */
26536 }
26538 /* Implement TARGET_ESTIMATED_POLY_VALUE.
26539 Look into the tuning structure for an estimate.
26540 KIND specifies the type of requested estimate: min, max or likely.
26541 For cores with a known SVE width all three estimates are the same.
26542 For generic SVE tuning we want to distinguish the maximum estimate from
26543 the minimum and likely ones.
26544 The likely estimate is the same as the minimum in that case to give a
26545 conservative behavior of auto-vectorizing with SVE when it is a win
26546 even for 128-bit SVE.
26547 When SVE width information is available VAL.coeffs[1] is multiplied by
26548 the number of VQ chunks over the initial Advanced SIMD 128 bits. */
26550 static HOST_WIDE_INT
26552 poly_value_estimate_kind kind
26554 {
26557 /* If there is no core-specific information then the minimum and likely
26558 values are based on 128-bit vectors and the maximum is based on
26559 the architectural maximum of 2048 bits. */
26562 {
26568 }
26570 /* Allow sve_width to be a bitmask of different VL, treating the lowest
26571 as likely. This could be made more general if future -mtune options
26572 need it to be. */
26575 else
26578 /* If the core provides width information, use that. */
26581 }
26584 /* Return true for types that could be supported as SIMD return or
26585 argument types. */
26587 static bool
26589 {
26591 {
26594 }
26596 }
26598 /* Return true for types that currently are supported as SIMD return
26599 or argument types. */
26601 static bool
26603 {
26611 }
26613 /* Implement TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN. */
26615 static int
26619 {
26623 poly_uint64 vec_bits;
26628 /* For now, SVE simdclones won't produce illegal simdlen, So only check
26629 const simdlens here. */
26635 {
26639 }
26644 {
26647 "GCC does not currently support mixed size types "
26651 "GCC does not currently support return type %qT "
26653 else
26656 ret_type);
26658 }
26666 {
26671 {
26674 "GCC does not currently support mixed size types "
26676 else
26678 "GCC does not currently support argument type %qT "
26681 }
26682 }
26688 {
26692 }
26693 else
26694 {
26697 /* For now, SVE simdclones won't produce illegal simdlen, So only check
26698 const simdlens here. */
26701 {
26706 }
26707 }
26711 }
26713 /* Implement TARGET_SIMD_CLONE_ADJUST. */
26715 static void
26717 {
26718 /* Add aarch64_vector_pcs target attribute to SIMD clones so they
26719 use the correct ABI. */
26724 }
26726 /* Implement TARGET_SIMD_CLONE_USABLE. */
26728 static int
26730 {
26732 {
26739 }
26740 }
26742 /* Implement TARGET_COMP_TYPE_ATTRIBUTES */
26744 static int
26746 {
26754 };
26765 }
26767 /* Implement TARGET_GET_MULTILIB_ABI_NAME */
26771 {
26775 }
26777 /* Implement TARGET_STACK_PROTECT_GUARD. In case of a
26778 global variable based guard use the default else
26779 return a null tree. */
26780 static tree
26782 {
26787 }
26789 /* Return the diagnostic message string if conversion from FROMTYPE to
26790 TOTYPE is not allowed, NULL otherwise. */
26794 {
26796 {
26797 /* Do no allow conversions to/from BFmode scalar types. */
26802 }
26804 /* Conversion allowed. */
26806 }
26808 /* Return the diagnostic message string if the unary operation OP is
26809 not permitted on TYPE, NULL otherwise. */
26813 {
26814 /* Reject all single-operand operations on BFmode except for &. */
26818 /* Operation allowed. */
26820 }
26822 /* Return the diagnostic message string if the binary operation OP is
26823 not permitted on TYPE1 and TYPE2, NULL otherwise. */
26827 const_tree type2)
26828 {
26829 /* Reject all 2-operand operations on BFmode. */
26842 /* Operation allowed. */
26844 }
26846 /* Implement TARGET_MEMTAG_CAN_TAG_ADDRESSES. Here we tell the rest of the
26847 compiler that we automatically ignore the top byte of our pointers, which
26848 allows using -fsanitize=hwaddress. */
26849 bool
26851 {
26853 }
26855 /* Implement TARGET_ASM_FILE_END for AArch64. This adds the AArch64 GNU NOTE
26856 section at the end if needed. */
26857 #define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000
26858 #define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1U << 0)
26859 #define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1U << 1)
26860 void
26862 {
26873 {
26874 /* Generate .note.gnu.property section. */
26878 /* PT_NOTE header: namesz, descsz, type.
26879 namesz = 4 ("GNU\0")
26880 descsz = 16 (Size of the program property array)
26881 [(12 + padding) * Number of array elements]
26882 type = 5 (NT_GNU_PROPERTY_TYPE_0). */
26888 /* PT_NOTE name. */
26891 /* PT_NOTE contents for NT_GNU_PROPERTY_TYPE_0:
26892 type = GNU_PROPERTY_AARCH64_FEATURE_1_AND
26893 datasz = 4
26894 data = feature_1_and. */
26899 /* Pad the size of the note to the required alignment. */
26901 }
26902 }
26903 #undef GNU_PROPERTY_AARCH64_FEATURE_1_PAC
26904 #undef GNU_PROPERTY_AARCH64_FEATURE_1_BTI
26905 #undef GNU_PROPERTY_AARCH64_FEATURE_1_AND
26907 /* Helper function for straight line speculation.
26908 Return what barrier should be emitted for straight line speculation
26909 mitigation.
26910 When not mitigating against straight line speculation this function returns
26911 an empty string.
26912 When mitigating against straight line speculation, use:
26913 * SB when the v8.5-A SB extension is enabled.
26914 * DSB+ISB otherwise. */
26917 {
26918 return mitigation_required
26921 }
26956 };
26958 /* Function to create a BLR thunk. This thunk is used to mitigate straight
26959 line speculation. Instead of a simple BLR that can be speculated past,
26960 we emit a BL to this thunk, and this thunk contains a BR to the relevant
26961 register. These thunks have the relevant speculation barries put after
26962 their indirect branch so that speculation is blocked.
26964 We use such a thunk so the speculation barriers are kept off the
26965 architecturally executed path in order to reduce the performance overhead.
26967 When optimizing for size we use stubs shared by the linked object.
26968 When optimizing for performance we emit stubs for each function in the hope
26969 that the branch predictor can better train on jumps specific for a given
26970 function. */
26971 rtx
26973 {
26976 {
26977 /* For the thunks shared between different functions in this compilation
26978 unit we use a named symbol -- this is just for users to more easily
26979 understand the generated assembly. */
26983 {
26984 /* Build a decl representing this function stub and record it for
26985 later. We build a decl here so we can use the GCC machinery for
26986 handling sections automatically (through `get_named_section` and
26987 `make_decl_one_only`). That saves us a lot of trouble handling
26988 the specifics of different output file formats. */
26992 NULL_TREE));
27002 }
27005 }
27011 }
27013 /* Helper function for aarch64_sls_emit_blr_function_thunks and
27014 aarch64_sls_emit_shared_blr_thunks below. */
27015 static void
27017 {
27018 /* Save in x16 and branch to that function so this transformation does
27019 not prevent jumping to `BTI c` instructions. */
27022 }
27024 /* Emit all BLR stubs for this particular function.
27025 Here we emit all the BLR stubs needed for the current function. Since we
27026 emit these stubs in a consecutive block we know there will be no speculation
27027 gadgets between each stub, and hence we only emit a speculation barrier at
27028 the end of the stub sequences.
27030 This is called in the TARGET_ASM_FUNCTION_EPILOGUE hook. */
27031 void
27033 {
27038 /* We must save and restore the current function section since this assembly
27039 is emitted at the end of the function. This means it can be emitted *just
27040 after* the cold section of a function. That cold part would be emitted in
27041 a different section. That switch would trigger a `.cfi_endproc` directive
27042 to be emitted in the original section and a `.cfi_startproc` directive to
27043 be emitted in the new section. Switching to the original section without
27044 restoring would mean that the `.cfi_endproc` emitted as a function ends
27045 would happen in a different section -- leaving an unmatched
27046 `.cfi_startproc` in the cold text section and an unmatched `.cfi_endproc`
27047 in the standard text section. */
27051 {
27060 }
27062 /* Can use the SB if needs be here, since this stub will only be used
27063 by the current function, and hence for the current target. */
27066 }
27068 /* Emit shared BLR stubs for the current compilation unit.
27069 Over the course of compiling this unit we may have converted some BLR
27070 instructions to a BL to a shared stub function. This is where we emit those
27071 stub functions.
27072 This function is for the stubs shared between different functions in this
27073 compilation unit. We share when optimizing for size instead of speed.
27075 This function is called through the TARGET_ASM_FILE_END hook. */
27076 void
27078 {
27083 {
27092 /* Only emits if the compiler is configured for an assembler that can
27093 handle visibility directives. */
27098 /* Use the most conservative target to ensure it can always be used by any
27099 function in the translation unit. */
27102 }
27103 }
27105 /* Implement TARGET_ASM_FILE_END. */
27106 void
27108 {
27110 /* Since this function will be called for the ASM_FILE_END hook, we ensure
27111 that what would be called otherwise (e.g. `file_end_indicate_exec_stack`
27112 for FreeBSD) still gets called. */
27113 #ifdef TARGET_ASM_FILE_END
27115 #endif
27116 }
27120 {
27123 {
27126 }
27127 else
27130 }
27132 /* Target-specific selftests. */
27134 #if CHECKING_P
27138 /* Selftest for the RTL loader.
27139 Verify that the RTL loader copes with a dump from
27140 print_rtx_function. This is essentially just a test that class
27141 function_reader can handle a real dump, but it also verifies
27142 that lookup_reg_by_dump_name correctly handles hard regs.
27143 The presence of hard reg names in the dump means that the test is
27144 target-specific, hence it is in this file. */
27146 static void
27148 {
27160 /* Verify crtl->return_rtx. */
27164 }
27166 /* Test the fractional_cost class. */
27168 static void
27170 {
27257 }
27259 /* Run all target-specific selftests. */
27261 static void
27263 {
27266 }
27272 #undef TARGET_STACK_PROTECT_GUARD
27273 #define TARGET_STACK_PROTECT_GUARD aarch64_stack_protect_guard
27275 #undef TARGET_ADDRESS_COST
27276 #define TARGET_ADDRESS_COST aarch64_address_cost
27278 /* This hook will determines whether unnamed bitfields affect the alignment
27279 of the containing structure. The hook returns true if the structure
27280 should inherit the alignment requirements of an unnamed bitfield's
27281 type. */
27282 #undef TARGET_ALIGN_ANON_BITFIELD
27283 #define TARGET_ALIGN_ANON_BITFIELD hook_bool_void_true
27285 #undef TARGET_ASM_ALIGNED_DI_OP
27288 #undef TARGET_ASM_ALIGNED_HI_OP
27291 #undef TARGET_ASM_ALIGNED_SI_OP
27294 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
27295 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK \
27296 hook_bool_const_tree_hwi_hwi_const_tree_true
27298 #undef TARGET_ASM_FILE_START
27299 #define TARGET_ASM_FILE_START aarch64_start_file
27301 #undef TARGET_ASM_OUTPUT_MI_THUNK
27302 #define TARGET_ASM_OUTPUT_MI_THUNK aarch64_output_mi_thunk
27304 #undef TARGET_ASM_SELECT_RTX_SECTION
27305 #define TARGET_ASM_SELECT_RTX_SECTION aarch64_select_rtx_section
27307 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
27308 #define TARGET_ASM_TRAMPOLINE_TEMPLATE aarch64_asm_trampoline_template
27310 #undef TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY
27311 #define TARGET_ASM_PRINT_PATCHABLE_FUNCTION_ENTRY aarch64_print_patchable_function_entry
27313 #undef TARGET_BUILD_BUILTIN_VA_LIST
27314 #define TARGET_BUILD_BUILTIN_VA_LIST aarch64_build_builtin_va_list
27316 #undef TARGET_CALLEE_COPIES
27317 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_arg_info_false
27319 #undef TARGET_CAN_ELIMINATE
27320 #define TARGET_CAN_ELIMINATE aarch64_can_eliminate
27322 #undef TARGET_CAN_INLINE_P
27323 #define TARGET_CAN_INLINE_P aarch64_can_inline_p
27325 #undef TARGET_CANNOT_FORCE_CONST_MEM
27326 #define TARGET_CANNOT_FORCE_CONST_MEM aarch64_cannot_force_const_mem
27328 #undef TARGET_CASE_VALUES_THRESHOLD
27329 #define TARGET_CASE_VALUES_THRESHOLD aarch64_case_values_threshold
27331 #undef TARGET_CONDITIONAL_REGISTER_USAGE
27332 #define TARGET_CONDITIONAL_REGISTER_USAGE aarch64_conditional_register_usage
27334 #undef TARGET_MEMBER_TYPE_FORCES_BLK
27335 #define TARGET_MEMBER_TYPE_FORCES_BLK aarch64_member_type_forces_blk
27337 /* Only the least significant bit is used for initialization guard
27338 variables. */
27339 #undef TARGET_CXX_GUARD_MASK_BIT
27340 #define TARGET_CXX_GUARD_MASK_BIT hook_bool_void_true
27342 #undef TARGET_C_MODE_FOR_SUFFIX
27343 #define TARGET_C_MODE_FOR_SUFFIX aarch64_c_mode_for_suffix
27345 #ifdef TARGET_BIG_ENDIAN_DEFAULT
27346 #undef TARGET_DEFAULT_TARGET_FLAGS
27347 #define TARGET_DEFAULT_TARGET_FLAGS (MASK_BIG_END)
27348 #endif
27350 #undef TARGET_CLASS_MAX_NREGS
27351 #define TARGET_CLASS_MAX_NREGS aarch64_class_max_nregs
27353 #undef TARGET_BUILTIN_DECL
27354 #define TARGET_BUILTIN_DECL aarch64_builtin_decl
27356 #undef TARGET_BUILTIN_RECIPROCAL
27357 #define TARGET_BUILTIN_RECIPROCAL aarch64_builtin_reciprocal
27359 #undef TARGET_C_EXCESS_PRECISION
27360 #define TARGET_C_EXCESS_PRECISION aarch64_excess_precision
27362 #undef TARGET_EXPAND_BUILTIN
27363 #define TARGET_EXPAND_BUILTIN aarch64_expand_builtin
27365 #undef TARGET_EXPAND_BUILTIN_VA_START
27366 #define TARGET_EXPAND_BUILTIN_VA_START aarch64_expand_builtin_va_start
27368 #undef TARGET_FOLD_BUILTIN
27369 #define TARGET_FOLD_BUILTIN aarch64_fold_builtin
27371 #undef TARGET_FUNCTION_ARG
27372 #define TARGET_FUNCTION_ARG aarch64_function_arg
27374 #undef TARGET_FUNCTION_ARG_ADVANCE
27375 #define TARGET_FUNCTION_ARG_ADVANCE aarch64_function_arg_advance
27377 #undef TARGET_FUNCTION_ARG_BOUNDARY
27378 #define TARGET_FUNCTION_ARG_BOUNDARY aarch64_function_arg_boundary
27380 #undef TARGET_FUNCTION_ARG_PADDING
27381 #define TARGET_FUNCTION_ARG_PADDING aarch64_function_arg_padding
27383 #undef TARGET_GET_RAW_RESULT_MODE
27384 #define TARGET_GET_RAW_RESULT_MODE aarch64_get_reg_raw_mode
27385 #undef TARGET_GET_RAW_ARG_MODE
27386 #define TARGET_GET_RAW_ARG_MODE aarch64_get_reg_raw_mode
27388 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
27389 #define TARGET_FUNCTION_OK_FOR_SIBCALL aarch64_function_ok_for_sibcall
27391 #undef TARGET_FUNCTION_VALUE
27392 #define TARGET_FUNCTION_VALUE aarch64_function_value
27394 #undef TARGET_FUNCTION_VALUE_REGNO_P
27395 #define TARGET_FUNCTION_VALUE_REGNO_P aarch64_function_value_regno_p
27397 #undef TARGET_GIMPLE_FOLD_BUILTIN
27398 #define TARGET_GIMPLE_FOLD_BUILTIN aarch64_gimple_fold_builtin
27400 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
27401 #define TARGET_GIMPLIFY_VA_ARG_EXPR aarch64_gimplify_va_arg_expr
27403 #undef TARGET_INIT_BUILTINS
27404 #define TARGET_INIT_BUILTINS aarch64_init_builtins
27406 #undef TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS
27407 #define TARGET_IRA_CHANGE_PSEUDO_ALLOCNO_CLASS \
27408 aarch64_ira_change_pseudo_allocno_class
27410 #undef TARGET_LEGITIMATE_ADDRESS_P
27411 #define TARGET_LEGITIMATE_ADDRESS_P aarch64_legitimate_address_hook_p
27413 #undef TARGET_LEGITIMATE_CONSTANT_P
27414 #define TARGET_LEGITIMATE_CONSTANT_P aarch64_legitimate_constant_p
27416 #undef TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT
27417 #define TARGET_LEGITIMIZE_ADDRESS_DISPLACEMENT \
27418 aarch64_legitimize_address_displacement
27420 #undef TARGET_LIBGCC_CMP_RETURN_MODE
27421 #define TARGET_LIBGCC_CMP_RETURN_MODE aarch64_libgcc_cmp_return_mode
27423 #undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
27424 #define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
27425 aarch64_libgcc_floating_mode_supported_p
27427 #undef TARGET_MANGLE_TYPE
27428 #define TARGET_MANGLE_TYPE aarch64_mangle_type
27430 #undef TARGET_INVALID_CONVERSION
27431 #define TARGET_INVALID_CONVERSION aarch64_invalid_conversion
27433 #undef TARGET_INVALID_UNARY_OP
27434 #define TARGET_INVALID_UNARY_OP aarch64_invalid_unary_op
27436 #undef TARGET_INVALID_BINARY_OP
27437 #define TARGET_INVALID_BINARY_OP aarch64_invalid_binary_op
27439 #undef TARGET_VERIFY_TYPE_CONTEXT
27440 #define TARGET_VERIFY_TYPE_CONTEXT aarch64_verify_type_context
27442 #undef TARGET_MEMORY_MOVE_COST
27443 #define TARGET_MEMORY_MOVE_COST aarch64_memory_move_cost
27445 #undef TARGET_MIN_DIVISIONS_FOR_RECIP_MUL
27446 #define TARGET_MIN_DIVISIONS_FOR_RECIP_MUL aarch64_min_divisions_for_recip_mul
27448 #undef TARGET_MUST_PASS_IN_STACK
27449 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
27451 /* This target hook should return true if accesses to volatile bitfields
27452 should use the narrowest mode possible. It should return false if these
27453 accesses should use the bitfield container type. */
27454 #undef TARGET_NARROW_VOLATILE_BITFIELD
27455 #define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
27457 #undef TARGET_OPTION_OVERRIDE
27458 #define TARGET_OPTION_OVERRIDE aarch64_override_options
27460 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
27461 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE \
27462 aarch64_override_options_after_change
27464 #undef TARGET_OFFLOAD_OPTIONS
27465 #define TARGET_OFFLOAD_OPTIONS aarch64_offload_options
27467 #undef TARGET_OPTION_RESTORE
27468 #define TARGET_OPTION_RESTORE aarch64_option_restore
27470 #undef TARGET_OPTION_PRINT
27471 #define TARGET_OPTION_PRINT aarch64_option_print
27473 #undef TARGET_OPTION_VALID_ATTRIBUTE_P
27474 #define TARGET_OPTION_VALID_ATTRIBUTE_P aarch64_option_valid_attribute_p
27476 #undef TARGET_SET_CURRENT_FUNCTION
27477 #define TARGET_SET_CURRENT_FUNCTION aarch64_set_current_function
27479 #undef TARGET_PASS_BY_REFERENCE
27480 #define TARGET_PASS_BY_REFERENCE aarch64_pass_by_reference
27482 #undef TARGET_PREFERRED_RELOAD_CLASS
27483 #define TARGET_PREFERRED_RELOAD_CLASS aarch64_preferred_reload_class
27485 #undef TARGET_SCHED_REASSOCIATION_WIDTH
27486 #define TARGET_SCHED_REASSOCIATION_WIDTH aarch64_reassociation_width
27488 #undef TARGET_PROMOTED_TYPE
27489 #define TARGET_PROMOTED_TYPE aarch64_promoted_type
27491 #undef TARGET_SECONDARY_RELOAD
27492 #define TARGET_SECONDARY_RELOAD aarch64_secondary_reload
27494 #undef TARGET_SHIFT_TRUNCATION_MASK
27495 #define TARGET_SHIFT_TRUNCATION_MASK aarch64_shift_truncation_mask
27497 #undef TARGET_SETUP_INCOMING_VARARGS
27498 #define TARGET_SETUP_INCOMING_VARARGS aarch64_setup_incoming_varargs
27500 #undef TARGET_STRUCT_VALUE_RTX
27501 #define TARGET_STRUCT_VALUE_RTX aarch64_struct_value_rtx
27503 #undef TARGET_REGISTER_MOVE_COST
27504 #define TARGET_REGISTER_MOVE_COST aarch64_register_move_cost
27506 #undef TARGET_RETURN_IN_MEMORY
27507 #define TARGET_RETURN_IN_MEMORY aarch64_return_in_memory
27509 #undef TARGET_RETURN_IN_MSB
27510 #define TARGET_RETURN_IN_MSB aarch64_return_in_msb
27512 #undef TARGET_RTX_COSTS
27513 #define TARGET_RTX_COSTS aarch64_rtx_costs_wrapper
27515 #undef TARGET_SCALAR_MODE_SUPPORTED_P
27516 #define TARGET_SCALAR_MODE_SUPPORTED_P aarch64_scalar_mode_supported_p
27518 #undef TARGET_SCHED_ISSUE_RATE
27519 #define TARGET_SCHED_ISSUE_RATE aarch64_sched_issue_rate
27521 #undef TARGET_SCHED_VARIABLE_ISSUE
27522 #define TARGET_SCHED_VARIABLE_ISSUE aarch64_sched_variable_issue
27524 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
27525 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
27526 aarch64_sched_first_cycle_multipass_dfa_lookahead
27528 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
27529 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD \
27530 aarch64_first_cycle_multipass_dfa_lookahead_guard
27532 #undef TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS
27533 #define TARGET_SHRINK_WRAP_GET_SEPARATE_COMPONENTS \
27534 aarch64_get_separate_components
27536 #undef TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB
27537 #define TARGET_SHRINK_WRAP_COMPONENTS_FOR_BB \
27538 aarch64_components_for_bb
27540 #undef TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS
27541 #define TARGET_SHRINK_WRAP_DISQUALIFY_COMPONENTS \
27542 aarch64_disqualify_components
27544 #undef TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS
27545 #define TARGET_SHRINK_WRAP_EMIT_PROLOGUE_COMPONENTS \
27546 aarch64_emit_prologue_components
27548 #undef TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS
27549 #define TARGET_SHRINK_WRAP_EMIT_EPILOGUE_COMPONENTS \
27550 aarch64_emit_epilogue_components
27552 #undef TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS
27553 #define TARGET_SHRINK_WRAP_SET_HANDLED_COMPONENTS \
27554 aarch64_set_handled_components
27556 #undef TARGET_TRAMPOLINE_INIT
27557 #define TARGET_TRAMPOLINE_INIT aarch64_trampoline_init
27559 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
27560 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P aarch64_use_blocks_for_constant_p
27562 #undef TARGET_VECTOR_MODE_SUPPORTED_P
27563 #define TARGET_VECTOR_MODE_SUPPORTED_P aarch64_vector_mode_supported_p
27565 #undef TARGET_COMPATIBLE_VECTOR_TYPES_P
27566 #define TARGET_COMPATIBLE_VECTOR_TYPES_P aarch64_compatible_vector_types_p
27568 #undef TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT
27569 #define TARGET_VECTORIZE_SUPPORT_VECTOR_MISALIGNMENT \
27570 aarch64_builtin_support_vector_misalignment
27572 #undef TARGET_ARRAY_MODE
27573 #define TARGET_ARRAY_MODE aarch64_array_mode
27575 #undef TARGET_ARRAY_MODE_SUPPORTED_P
27576 #define TARGET_ARRAY_MODE_SUPPORTED_P aarch64_array_mode_supported_p
27578 #undef TARGET_VECTORIZE_CREATE_COSTS
27579 #define TARGET_VECTORIZE_CREATE_COSTS aarch64_vectorize_create_costs
27581 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST
27582 #define TARGET_VECTORIZE_BUILTIN_VECTORIZATION_COST \
27583 aarch64_builtin_vectorization_cost
27585 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE
27586 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE aarch64_preferred_simd_mode
27588 #undef TARGET_VECTORIZE_BUILTINS
27589 #define TARGET_VECTORIZE_BUILTINS
27591 #undef TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION
27592 #define TARGET_VECTORIZE_BUILTIN_VECTORIZED_FUNCTION \
27593 aarch64_builtin_vectorized_function
27595 #undef TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES
27596 #define TARGET_VECTORIZE_AUTOVECTORIZE_VECTOR_MODES \
27597 aarch64_autovectorize_vector_modes
27599 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV
27600 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV \
27601 aarch64_atomic_assign_expand_fenv
27603 /* Section anchor support. */
27605 #undef TARGET_MIN_ANCHOR_OFFSET
27606 #define TARGET_MIN_ANCHOR_OFFSET -256
27608 /* Limit the maximum anchor offset to 4k-1, since that's the limit for a
27609 byte offset; we can do much more for larger data types, but have no way
27610 to determine the size of the access. We assume accesses are aligned. */
27611 #undef TARGET_MAX_ANCHOR_OFFSET
27612 #define TARGET_MAX_ANCHOR_OFFSET 4095
27614 #undef TARGET_VECTOR_ALIGNMENT
27615 #define TARGET_VECTOR_ALIGNMENT aarch64_simd_vector_alignment
27617 #undef TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT
27618 #define TARGET_VECTORIZE_PREFERRED_VECTOR_ALIGNMENT \
27619 aarch64_vectorize_preferred_vector_alignment
27620 #undef TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE
27621 #define TARGET_VECTORIZE_VECTOR_ALIGNMENT_REACHABLE \
27622 aarch64_simd_vector_alignment_reachable
27624 /* vec_perm support. */
27626 #undef TARGET_VECTORIZE_VEC_PERM_CONST
27627 #define TARGET_VECTORIZE_VEC_PERM_CONST \
27628 aarch64_vectorize_vec_perm_const
27630 #undef TARGET_VECTORIZE_RELATED_MODE
27631 #define TARGET_VECTORIZE_RELATED_MODE aarch64_vectorize_related_mode
27632 #undef TARGET_VECTORIZE_GET_MASK_MODE
27633 #define TARGET_VECTORIZE_GET_MASK_MODE aarch64_get_mask_mode
27634 #undef TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE
27635 #define TARGET_VECTORIZE_EMPTY_MASK_IS_EXPENSIVE \
27636 aarch64_empty_mask_is_expensive
27637 #undef TARGET_PREFERRED_ELSE_VALUE
27638 #define TARGET_PREFERRED_ELSE_VALUE \
27639 aarch64_preferred_else_value
27641 #undef TARGET_INIT_LIBFUNCS
27642 #define TARGET_INIT_LIBFUNCS aarch64_init_libfuncs
27644 #undef TARGET_FIXED_CONDITION_CODE_REGS
27645 #define TARGET_FIXED_CONDITION_CODE_REGS aarch64_fixed_condition_code_regs
27647 #undef TARGET_FLAGS_REGNUM
27648 #define TARGET_FLAGS_REGNUM CC_REGNUM
27650 #undef TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS
27651 #define TARGET_CALL_FUSAGE_CONTAINS_NON_CALLEE_CLOBBERS true
27653 #undef TARGET_ASAN_SHADOW_OFFSET
27654 #define TARGET_ASAN_SHADOW_OFFSET aarch64_asan_shadow_offset
27656 #undef TARGET_LEGITIMIZE_ADDRESS
27657 #define TARGET_LEGITIMIZE_ADDRESS aarch64_legitimize_address
27659 #undef TARGET_SCHED_CAN_SPECULATE_INSN
27660 #define TARGET_SCHED_CAN_SPECULATE_INSN aarch64_sched_can_speculate_insn
27662 #undef TARGET_CAN_USE_DOLOOP_P
27663 #define TARGET_CAN_USE_DOLOOP_P can_use_doloop_if_innermost
27665 #undef TARGET_SCHED_ADJUST_PRIORITY
27666 #define TARGET_SCHED_ADJUST_PRIORITY aarch64_sched_adjust_priority
27668 #undef TARGET_SCHED_MACRO_FUSION_P
27669 #define TARGET_SCHED_MACRO_FUSION_P aarch64_macro_fusion_p
27671 #undef TARGET_SCHED_MACRO_FUSION_PAIR_P
27672 #define TARGET_SCHED_MACRO_FUSION_PAIR_P aarch_macro_fusion_pair_p
27674 #undef TARGET_SCHED_FUSION_PRIORITY
27675 #define TARGET_SCHED_FUSION_PRIORITY aarch64_sched_fusion_priority
27677 #undef TARGET_UNSPEC_MAY_TRAP_P
27678 #define TARGET_UNSPEC_MAY_TRAP_P aarch64_unspec_may_trap_p
27680 #undef TARGET_USE_PSEUDO_PIC_REG
27681 #define TARGET_USE_PSEUDO_PIC_REG aarch64_use_pseudo_pic_reg
27683 #undef TARGET_PRINT_OPERAND
27684 #define TARGET_PRINT_OPERAND aarch64_print_operand
27686 #undef TARGET_PRINT_OPERAND_ADDRESS
27687 #define TARGET_PRINT_OPERAND_ADDRESS aarch64_print_operand_address
27689 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA
27690 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA aarch64_output_addr_const_extra
27692 #undef TARGET_OPTAB_SUPPORTED_P
27693 #define TARGET_OPTAB_SUPPORTED_P aarch64_optab_supported_p
27695 #undef TARGET_OMIT_STRUCT_RETURN_REG
27696 #define TARGET_OMIT_STRUCT_RETURN_REG true
27698 #undef TARGET_DWARF_POLY_INDETERMINATE_VALUE
27699 #define TARGET_DWARF_POLY_INDETERMINATE_VALUE \
27700 aarch64_dwarf_poly_indeterminate_value
27702 /* The architecture reserves bits 0 and 1 so use bit 2 for descriptors. */
27703 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
27704 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 4
27706 #undef TARGET_HARD_REGNO_NREGS
27707 #define TARGET_HARD_REGNO_NREGS aarch64_hard_regno_nregs
27708 #undef TARGET_HARD_REGNO_MODE_OK
27709 #define TARGET_HARD_REGNO_MODE_OK aarch64_hard_regno_mode_ok
27711 #undef TARGET_MODES_TIEABLE_P
27712 #define TARGET_MODES_TIEABLE_P aarch64_modes_tieable_p
27714 #undef TARGET_HARD_REGNO_CALL_PART_CLOBBERED
27715 #define TARGET_HARD_REGNO_CALL_PART_CLOBBERED \
27716 aarch64_hard_regno_call_part_clobbered
27718 #undef TARGET_INSN_CALLEE_ABI
27719 #define TARGET_INSN_CALLEE_ABI aarch64_insn_callee_abi
27721 #undef TARGET_CONSTANT_ALIGNMENT
27722 #define TARGET_CONSTANT_ALIGNMENT aarch64_constant_alignment
27724 #undef TARGET_STACK_CLASH_PROTECTION_ALLOCA_PROBE_RANGE
27725 #define TARGET_STACK_CLASH_PROTECTION_ALLOCA_PROBE_RANGE \
27726 aarch64_stack_clash_protection_alloca_probe_range
27728 #undef TARGET_COMPUTE_PRESSURE_CLASSES
27729 #define TARGET_COMPUTE_PRESSURE_CLASSES aarch64_compute_pressure_classes
27731 #undef TARGET_CAN_CHANGE_MODE_CLASS
27732 #define TARGET_CAN_CHANGE_MODE_CLASS aarch64_can_change_mode_class
27734 #undef TARGET_SELECT_EARLY_REMAT_MODES
27735 #define TARGET_SELECT_EARLY_REMAT_MODES aarch64_select_early_remat_modes
27737 #undef TARGET_SPECULATION_SAFE_VALUE
27738 #define TARGET_SPECULATION_SAFE_VALUE aarch64_speculation_safe_value
27740 #undef TARGET_ESTIMATED_POLY_VALUE
27741 #define TARGET_ESTIMATED_POLY_VALUE aarch64_estimated_poly_value
27743 #undef TARGET_ATTRIBUTE_TABLE
27744 #define TARGET_ATTRIBUTE_TABLE aarch64_attribute_table
27746 #undef TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN
27747 #define TARGET_SIMD_CLONE_COMPUTE_VECSIZE_AND_SIMDLEN \
27748 aarch64_simd_clone_compute_vecsize_and_simdlen
27750 #undef TARGET_SIMD_CLONE_ADJUST
27751 #define TARGET_SIMD_CLONE_ADJUST aarch64_simd_clone_adjust
27753 #undef TARGET_SIMD_CLONE_USABLE
27754 #define TARGET_SIMD_CLONE_USABLE aarch64_simd_clone_usable
27756 #undef TARGET_COMP_TYPE_ATTRIBUTES
27757 #define TARGET_COMP_TYPE_ATTRIBUTES aarch64_comp_type_attributes
27759 #undef TARGET_GET_MULTILIB_ABI_NAME
27760 #define TARGET_GET_MULTILIB_ABI_NAME aarch64_get_multilib_abi_name
27762 #undef TARGET_FNTYPE_ABI
27763 #define TARGET_FNTYPE_ABI aarch64_fntype_abi
27765 #undef TARGET_MEMTAG_CAN_TAG_ADDRESSES
27766 #define TARGET_MEMTAG_CAN_TAG_ADDRESSES aarch64_can_tag_addresses
27768 #if CHECKING_P
27769 #undef TARGET_RUN_TARGET_SELFTESTS
27770 #define TARGET_RUN_TARGET_SELFTESTS selftest::aarch64_run_selftests
27773 #undef TARGET_ASM_POST_CFI_STARTPROC
27774 #define TARGET_ASM_POST_CFI_STARTPROC aarch64_post_cfi_startproc
27776 #undef TARGET_STRICT_ARGUMENT_NAMING
27777 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
27779 #undef TARGET_MD_ASM_ADJUST
27780 #define TARGET_MD_ASM_ADJUST arm_md_asm_adjust
27782 #undef TARGET_ASM_FILE_END
27783 #define TARGET_ASM_FILE_END aarch64_asm_file_end
27785 #undef TARGET_ASM_FUNCTION_EPILOGUE
27786 #define TARGET_ASM_FUNCTION_EPILOGUE aarch64_sls_emit_blr_function_thunks
27788 #undef TARGET_HAVE_SHADOW_CALL_STACK
27789 #define TARGET_HAVE_SHADOW_CALL_STACK true